From a3550ea665acd1922df8275379028c1634675629 Mon Sep 17 00:00:00 2001 From: Federico Simoncelli Date: Tue, 7 Jan 2014 19:13:21 -0300 Subject: [media] usbtv: split core and video implementation Signed-off-by: Federico Simoncelli Reviewed-by: Lubomir Rintel Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/usbtv/Makefile | 3 + drivers/media/usb/usbtv/usbtv-core.c | 136 ++++++ drivers/media/usb/usbtv/usbtv-video.c | 738 ++++++++++++++++++++++++++++ drivers/media/usb/usbtv/usbtv.c | 883 ---------------------------------- drivers/media/usb/usbtv/usbtv.h | 98 ++++ 5 files changed, 975 insertions(+), 883 deletions(-) create mode 100644 drivers/media/usb/usbtv/usbtv-core.c create mode 100644 drivers/media/usb/usbtv/usbtv-video.c delete mode 100644 drivers/media/usb/usbtv/usbtv.c create mode 100644 drivers/media/usb/usbtv/usbtv.h diff --git a/drivers/media/usb/usbtv/Makefile b/drivers/media/usb/usbtv/Makefile index 28b872f..775316a 100644 --- a/drivers/media/usb/usbtv/Makefile +++ b/drivers/media/usb/usbtv/Makefile @@ -1 +1,4 @@ +usbtv-y := usbtv-core.o \ + usbtv-video.o + obj-$(CONFIG_VIDEO_USBTV) += usbtv.o diff --git a/drivers/media/usb/usbtv/usbtv-core.c b/drivers/media/usb/usbtv/usbtv-core.c new file mode 100644 index 0000000..e89e48b --- /dev/null +++ b/drivers/media/usb/usbtv/usbtv-core.c @@ -0,0 +1,136 @@ +/* + * Fushicai USBTV007 Video Grabber Driver + * + * Product web site: + * http://www.fushicai.com/products_detail/&productId=d05449ee-b690-42f9-a661-aa7353894bed.html + * + * Following LWN articles were very useful in construction of this driver: + * Video4Linux2 API series: http://lwn.net/Articles/203924/ + * videobuf2 API explanation: http://lwn.net/Articles/447435/ + * Thanks go to Jonathan Corbet for providing this quality documentation. + * He is awesome. + * + * Copyright (c) 2013 Lubomir Rintel + * All rights reserved. + * No physical hardware was harmed running Windows during the + * reverse-engineering activity + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer, + * without modification. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * Alternatively, this software may be distributed under the terms of the + * GNU General Public License ("GPL"). + */ + +#include + +#include "usbtv.h" + +int usbtv_set_regs(struct usbtv *usbtv, const u16 regs[][2], int size) +{ + int ret; + int pipe = usb_rcvctrlpipe(usbtv->udev, 0); + int i; + + for (i = 0; i < size; i++) { + u16 index = regs[i][0]; + u16 value = regs[i][1]; + + ret = usb_control_msg(usbtv->udev, pipe, USBTV_REQUEST_REG, + USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, + value, index, NULL, 0, 0); + if (ret < 0) + return ret; + } + + return 0; +} + +static int usbtv_probe(struct usb_interface *intf, + const struct usb_device_id *id) +{ + int ret; + int size; + struct device *dev = &intf->dev; + struct usbtv *usbtv; + + /* Checks that the device is what we think it is. */ + if (intf->num_altsetting != 2) + return -ENODEV; + if (intf->altsetting[1].desc.bNumEndpoints != 4) + return -ENODEV; + + /* Packet size is split into 11 bits of base size and count of + * extra multiplies of it.*/ + size = usb_endpoint_maxp(&intf->altsetting[1].endpoint[0].desc); + size = (size & 0x07ff) * (((size & 0x1800) >> 11) + 1); + + /* Device structure */ + usbtv = kzalloc(sizeof(struct usbtv), GFP_KERNEL); + if (usbtv == NULL) + return -ENOMEM; + usbtv->dev = dev; + usbtv->udev = usb_get_dev(interface_to_usbdev(intf)); + + usbtv->iso_size = size; + + usb_set_intfdata(intf, usbtv); + + ret = usbtv_video_init(usbtv); + if (ret < 0) + goto usbtv_video_fail; + + /* for simplicity we exploit the v4l2_device reference counting */ + v4l2_device_get(&usbtv->v4l2_dev); + + dev_info(dev, "Fushicai USBTV007 Video Grabber\n"); + return 0; + +usbtv_video_fail: + kfree(usbtv); + + return ret; +} + +static void usbtv_disconnect(struct usb_interface *intf) +{ + struct usbtv *usbtv = usb_get_intfdata(intf); + usb_set_intfdata(intf, NULL); + + if (!usbtv) + return; + + usbtv_video_free(usbtv); + + usb_put_dev(usbtv->udev); + usbtv->udev = NULL; + + /* the usbtv structure will be deallocated when v4l2 will be + done using it */ + v4l2_device_put(&usbtv->v4l2_dev); +} + +struct usb_device_id usbtv_id_table[] = { + { USB_DEVICE(0x1b71, 0x3002) }, + {} +}; +MODULE_DEVICE_TABLE(usb, usbtv_id_table); + +MODULE_AUTHOR("Lubomir Rintel"); +MODULE_DESCRIPTION("Fushicai USBTV007 Video Grabber Driver"); +MODULE_LICENSE("Dual BSD/GPL"); + +struct usb_driver usbtv_usb_driver = { + .name = "usbtv", + .id_table = usbtv_id_table, + .probe = usbtv_probe, + .disconnect = usbtv_disconnect, +}; + +module_usb_driver(usbtv_usb_driver); diff --git a/drivers/media/usb/usbtv/usbtv-video.c b/drivers/media/usb/usbtv/usbtv-video.c new file mode 100644 index 0000000..496bc2e --- /dev/null +++ b/drivers/media/usb/usbtv/usbtv-video.c @@ -0,0 +1,738 @@ +/* + * Fushicai USBTV007 Video Grabber Driver + * + * Product web site: + * http://www.fushicai.com/products_detail/&productId=d05449ee-b690-42f9-a661-aa7353894bed.html + * + * Following LWN articles were very useful in construction of this driver: + * Video4Linux2 API series: http://lwn.net/Articles/203924/ + * videobuf2 API explanation: http://lwn.net/Articles/447435/ + * Thanks go to Jonathan Corbet for providing this quality documentation. + * He is awesome. + * + * Copyright (c) 2013 Lubomir Rintel + * All rights reserved. + * No physical hardware was harmed running Windows during the + * reverse-engineering activity + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer, + * without modification. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * Alternatively, this software may be distributed under the terms of the + * GNU General Public License ("GPL"). + */ + +#include +#include + +#include "usbtv.h" + +static struct usbtv_norm_params norm_params[] = { + { + .norm = V4L2_STD_525_60, + .cap_width = 720, + .cap_height = 480, + }, + { + .norm = V4L2_STD_PAL, + .cap_width = 720, + .cap_height = 576, + } +}; + +static int usbtv_configure_for_norm(struct usbtv *usbtv, v4l2_std_id norm) +{ + int i, ret = 0; + struct usbtv_norm_params *params = NULL; + + for (i = 0; i < ARRAY_SIZE(norm_params); i++) { + if (norm_params[i].norm & norm) { + params = &norm_params[i]; + break; + } + } + + if (params) { + usbtv->width = params->cap_width; + usbtv->height = params->cap_height; + usbtv->n_chunks = usbtv->width * usbtv->height + / 4 / USBTV_CHUNK; + usbtv->norm = params->norm; + } else + ret = -EINVAL; + + return ret; +} + +static int usbtv_select_input(struct usbtv *usbtv, int input) +{ + int ret; + + static const u16 composite[][2] = { + { USBTV_BASE + 0x0105, 0x0060 }, + { USBTV_BASE + 0x011f, 0x00f2 }, + { USBTV_BASE + 0x0127, 0x0060 }, + { USBTV_BASE + 0x00ae, 0x0010 }, + { USBTV_BASE + 0x0284, 0x00aa }, + { USBTV_BASE + 0x0239, 0x0060 }, + }; + + static const u16 svideo[][2] = { + { USBTV_BASE + 0x0105, 0x0010 }, + { USBTV_BASE + 0x011f, 0x00ff }, + { USBTV_BASE + 0x0127, 0x0060 }, + { USBTV_BASE + 0x00ae, 0x0030 }, + { USBTV_BASE + 0x0284, 0x0088 }, + { USBTV_BASE + 0x0239, 0x0060 }, + }; + + switch (input) { + case USBTV_COMPOSITE_INPUT: + ret = usbtv_set_regs(usbtv, composite, ARRAY_SIZE(composite)); + break; + case USBTV_SVIDEO_INPUT: + ret = usbtv_set_regs(usbtv, svideo, ARRAY_SIZE(svideo)); + break; + default: + ret = -EINVAL; + } + + if (!ret) + usbtv->input = input; + + return ret; +} + +static int usbtv_select_norm(struct usbtv *usbtv, v4l2_std_id norm) +{ + int ret; + static const u16 pal[][2] = { + { USBTV_BASE + 0x001a, 0x0068 }, + { USBTV_BASE + 0x010e, 0x0072 }, + { USBTV_BASE + 0x010f, 0x00a2 }, + { USBTV_BASE + 0x0112, 0x00b0 }, + { USBTV_BASE + 0x0117, 0x0001 }, + { USBTV_BASE + 0x0118, 0x002c }, + { USBTV_BASE + 0x012d, 0x0010 }, + { USBTV_BASE + 0x012f, 0x0020 }, + { USBTV_BASE + 0x024f, 0x0002 }, + { USBTV_BASE + 0x0254, 0x0059 }, + { USBTV_BASE + 0x025a, 0x0016 }, + { USBTV_BASE + 0x025b, 0x0035 }, + { USBTV_BASE + 0x0263, 0x0017 }, + { USBTV_BASE + 0x0266, 0x0016 }, + { USBTV_BASE + 0x0267, 0x0036 } + }; + + static const u16 ntsc[][2] = { + { USBTV_BASE + 0x001a, 0x0079 }, + { USBTV_BASE + 0x010e, 0x0068 }, + { USBTV_BASE + 0x010f, 0x009c }, + { USBTV_BASE + 0x0112, 0x00f0 }, + { USBTV_BASE + 0x0117, 0x0000 }, + { USBTV_BASE + 0x0118, 0x00fc }, + { USBTV_BASE + 0x012d, 0x0004 }, + { USBTV_BASE + 0x012f, 0x0008 }, + { USBTV_BASE + 0x024f, 0x0001 }, + { USBTV_BASE + 0x0254, 0x005f }, + { USBTV_BASE + 0x025a, 0x0012 }, + { USBTV_BASE + 0x025b, 0x0001 }, + { USBTV_BASE + 0x0263, 0x001c }, + { USBTV_BASE + 0x0266, 0x0011 }, + { USBTV_BASE + 0x0267, 0x0005 } + }; + + ret = usbtv_configure_for_norm(usbtv, norm); + + if (!ret) { + if (norm & V4L2_STD_525_60) + ret = usbtv_set_regs(usbtv, ntsc, ARRAY_SIZE(ntsc)); + else if (norm & V4L2_STD_PAL) + ret = usbtv_set_regs(usbtv, pal, ARRAY_SIZE(pal)); + } + + return ret; +} + +static int usbtv_setup_capture(struct usbtv *usbtv) +{ + int ret; + static const u16 setup[][2] = { + /* These seem to enable the device. */ + { USBTV_BASE + 0x0008, 0x0001 }, + { USBTV_BASE + 0x01d0, 0x00ff }, + { USBTV_BASE + 0x01d9, 0x0002 }, + + /* These seem to influence color parameters, such as + * brightness, etc. */ + { USBTV_BASE + 0x0239, 0x0040 }, + { USBTV_BASE + 0x0240, 0x0000 }, + { USBTV_BASE + 0x0241, 0x0000 }, + { USBTV_BASE + 0x0242, 0x0002 }, + { USBTV_BASE + 0x0243, 0x0080 }, + { USBTV_BASE + 0x0244, 0x0012 }, + { USBTV_BASE + 0x0245, 0x0090 }, + { USBTV_BASE + 0x0246, 0x0000 }, + + { USBTV_BASE + 0x0278, 0x002d }, + { USBTV_BASE + 0x0279, 0x000a }, + { USBTV_BASE + 0x027a, 0x0032 }, + { 0xf890, 0x000c }, + { 0xf894, 0x0086 }, + + { USBTV_BASE + 0x00ac, 0x00c0 }, + { USBTV_BASE + 0x00ad, 0x0000 }, + { USBTV_BASE + 0x00a2, 0x0012 }, + { USBTV_BASE + 0x00a3, 0x00e0 }, + { USBTV_BASE + 0x00a4, 0x0028 }, + { USBTV_BASE + 0x00a5, 0x0082 }, + { USBTV_BASE + 0x00a7, 0x0080 }, + { USBTV_BASE + 0x0000, 0x0014 }, + { USBTV_BASE + 0x0006, 0x0003 }, + { USBTV_BASE + 0x0090, 0x0099 }, + { USBTV_BASE + 0x0091, 0x0090 }, + { USBTV_BASE + 0x0094, 0x0068 }, + { USBTV_BASE + 0x0095, 0x0070 }, + { USBTV_BASE + 0x009c, 0x0030 }, + { USBTV_BASE + 0x009d, 0x00c0 }, + { USBTV_BASE + 0x009e, 0x00e0 }, + { USBTV_BASE + 0x0019, 0x0006 }, + { USBTV_BASE + 0x008c, 0x00ba }, + { USBTV_BASE + 0x0101, 0x00ff }, + { USBTV_BASE + 0x010c, 0x00b3 }, + { USBTV_BASE + 0x01b2, 0x0080 }, + { USBTV_BASE + 0x01b4, 0x00a0 }, + { USBTV_BASE + 0x014c, 0x00ff }, + { USBTV_BASE + 0x014d, 0x00ca }, + { USBTV_BASE + 0x0113, 0x0053 }, + { USBTV_BASE + 0x0119, 0x008a }, + { USBTV_BASE + 0x013c, 0x0003 }, + { USBTV_BASE + 0x0150, 0x009c }, + { USBTV_BASE + 0x0151, 0x0071 }, + { USBTV_BASE + 0x0152, 0x00c6 }, + { USBTV_BASE + 0x0153, 0x0084 }, + { USBTV_BASE + 0x0154, 0x00bc }, + { USBTV_BASE + 0x0155, 0x00a0 }, + { USBTV_BASE + 0x0156, 0x00a0 }, + { USBTV_BASE + 0x0157, 0x009c }, + { USBTV_BASE + 0x0158, 0x001f }, + { USBTV_BASE + 0x0159, 0x0006 }, + { USBTV_BASE + 0x015d, 0x0000 }, + + { USBTV_BASE + 0x0284, 0x0088 }, + { USBTV_BASE + 0x0003, 0x0004 }, + { USBTV_BASE + 0x0100, 0x00d3 }, + { USBTV_BASE + 0x0115, 0x0015 }, + { USBTV_BASE + 0x0220, 0x002e }, + { USBTV_BASE + 0x0225, 0x0008 }, + { USBTV_BASE + 0x024e, 0x0002 }, + { USBTV_BASE + 0x024e, 0x0002 }, + { USBTV_BASE + 0x024f, 0x0002 }, + }; + + ret = usbtv_set_regs(usbtv, setup, ARRAY_SIZE(setup)); + if (ret) + return ret; + + ret = usbtv_select_norm(usbtv, usbtv->norm); + if (ret) + return ret; + + ret = usbtv_select_input(usbtv, usbtv->input); + if (ret) + return ret; + + return 0; +} + +/* Copy data from chunk into a frame buffer, deinterlacing the data + * into every second line. Unfortunately, they don't align nicely into + * 720 pixel lines, as the chunk is 240 words long, which is 480 pixels. + * Therefore, we break down the chunk into two halves before copyting, + * so that we can interleave a line if needed. */ +static void usbtv_chunk_to_vbuf(u32 *frame, u32 *src, int chunk_no, int odd) +{ + int half; + + for (half = 0; half < 2; half++) { + int part_no = chunk_no * 2 + half; + int line = part_no / 3; + int part_index = (line * 2 + !odd) * 3 + (part_no % 3); + + u32 *dst = &frame[part_index * USBTV_CHUNK/2]; + memcpy(dst, src, USBTV_CHUNK/2 * sizeof(*src)); + src += USBTV_CHUNK/2; + } +} + +/* Called for each 256-byte image chunk. + * First word identifies the chunk, followed by 240 words of image + * data and padding. */ +static void usbtv_image_chunk(struct usbtv *usbtv, u32 *chunk) +{ + int frame_id, odd, chunk_no; + u32 *frame; + struct usbtv_buf *buf; + unsigned long flags; + + /* Ignore corrupted lines. */ + if (!USBTV_MAGIC_OK(chunk)) + return; + frame_id = USBTV_FRAME_ID(chunk); + odd = USBTV_ODD(chunk); + chunk_no = USBTV_CHUNK_NO(chunk); + if (chunk_no >= usbtv->n_chunks) + return; + + /* Beginning of a frame. */ + if (chunk_no == 0) { + usbtv->frame_id = frame_id; + usbtv->chunks_done = 0; + } + + if (usbtv->frame_id != frame_id) + return; + + spin_lock_irqsave(&usbtv->buflock, flags); + if (list_empty(&usbtv->bufs)) { + /* No free buffers. Userspace likely too slow. */ + spin_unlock_irqrestore(&usbtv->buflock, flags); + return; + } + + /* First available buffer. */ + buf = list_first_entry(&usbtv->bufs, struct usbtv_buf, list); + frame = vb2_plane_vaddr(&buf->vb, 0); + + /* Copy the chunk data. */ + usbtv_chunk_to_vbuf(frame, &chunk[1], chunk_no, odd); + usbtv->chunks_done++; + + /* Last chunk in a frame, signalling an end */ + if (odd && chunk_no == usbtv->n_chunks-1) { + int size = vb2_plane_size(&buf->vb, 0); + enum vb2_buffer_state state = usbtv->chunks_done == + usbtv->n_chunks ? + VB2_BUF_STATE_DONE : + VB2_BUF_STATE_ERROR; + + buf->vb.v4l2_buf.field = V4L2_FIELD_INTERLACED; + buf->vb.v4l2_buf.sequence = usbtv->sequence++; + v4l2_get_timestamp(&buf->vb.v4l2_buf.timestamp); + vb2_set_plane_payload(&buf->vb, 0, size); + vb2_buffer_done(&buf->vb, state); + list_del(&buf->list); + } + + spin_unlock_irqrestore(&usbtv->buflock, flags); +} + +/* Got image data. Each packet contains a number of 256-word chunks we + * compose the image from. */ +static void usbtv_iso_cb(struct urb *ip) +{ + int ret; + int i; + struct usbtv *usbtv = (struct usbtv *)ip->context; + + switch (ip->status) { + /* All fine. */ + case 0: + break; + /* Device disconnected or capture stopped? */ + case -ENODEV: + case -ENOENT: + case -ECONNRESET: + case -ESHUTDOWN: + return; + /* Unknown error. Retry. */ + default: + dev_warn(usbtv->dev, "Bad response for ISO request.\n"); + goto resubmit; + } + + for (i = 0; i < ip->number_of_packets; i++) { + int size = ip->iso_frame_desc[i].actual_length; + unsigned char *data = ip->transfer_buffer + + ip->iso_frame_desc[i].offset; + int offset; + + for (offset = 0; USBTV_CHUNK_SIZE * offset < size; offset++) + usbtv_image_chunk(usbtv, + (u32 *)&data[USBTV_CHUNK_SIZE * offset]); + } + +resubmit: + ret = usb_submit_urb(ip, GFP_ATOMIC); + if (ret < 0) + dev_warn(usbtv->dev, "Could not resubmit ISO URB\n"); +} + +static struct urb *usbtv_setup_iso_transfer(struct usbtv *usbtv) +{ + struct urb *ip; + int size = usbtv->iso_size; + int i; + + ip = usb_alloc_urb(USBTV_ISOC_PACKETS, GFP_KERNEL); + if (ip == NULL) + return NULL; + + ip->dev = usbtv->udev; + ip->context = usbtv; + ip->pipe = usb_rcvisocpipe(usbtv->udev, USBTV_VIDEO_ENDP); + ip->interval = 1; + ip->transfer_flags = URB_ISO_ASAP; + ip->transfer_buffer = kzalloc(size * USBTV_ISOC_PACKETS, + GFP_KERNEL); + ip->complete = usbtv_iso_cb; + ip->number_of_packets = USBTV_ISOC_PACKETS; + ip->transfer_buffer_length = size * USBTV_ISOC_PACKETS; + for (i = 0; i < USBTV_ISOC_PACKETS; i++) { + ip->iso_frame_desc[i].offset = size * i; + ip->iso_frame_desc[i].length = size; + } + + return ip; +} + +static void usbtv_stop(struct usbtv *usbtv) +{ + int i; + unsigned long flags; + + /* Cancel running transfers. */ + for (i = 0; i < USBTV_ISOC_TRANSFERS; i++) { + struct urb *ip = usbtv->isoc_urbs[i]; + if (ip == NULL) + continue; + usb_kill_urb(ip); + kfree(ip->transfer_buffer); + usb_free_urb(ip); + usbtv->isoc_urbs[i] = NULL; + } + + /* Return buffers to userspace. */ + spin_lock_irqsave(&usbtv->buflock, flags); + while (!list_empty(&usbtv->bufs)) { + struct usbtv_buf *buf = list_first_entry(&usbtv->bufs, + struct usbtv_buf, list); + vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR); + list_del(&buf->list); + } + spin_unlock_irqrestore(&usbtv->buflock, flags); +} + +static int usbtv_start(struct usbtv *usbtv) +{ + int i; + int ret; + + ret = usb_set_interface(usbtv->udev, 0, 0); + if (ret < 0) + return ret; + + ret = usbtv_setup_capture(usbtv); + if (ret < 0) + return ret; + + ret = usb_set_interface(usbtv->udev, 0, 1); + if (ret < 0) + return ret; + + for (i = 0; i < USBTV_ISOC_TRANSFERS; i++) { + struct urb *ip; + + ip = usbtv_setup_iso_transfer(usbtv); + if (ip == NULL) { + ret = -ENOMEM; + goto start_fail; + } + usbtv->isoc_urbs[i] = ip; + + ret = usb_submit_urb(ip, GFP_KERNEL); + if (ret < 0) + goto start_fail; + } + + return 0; + +start_fail: + usbtv_stop(usbtv); + return ret; +} + +static int usbtv_querycap(struct file *file, void *priv, + struct v4l2_capability *cap) +{ + struct usbtv *dev = video_drvdata(file); + + strlcpy(cap->driver, "usbtv", sizeof(cap->driver)); + strlcpy(cap->card, "usbtv", sizeof(cap->card)); + usb_make_path(dev->udev, cap->bus_info, sizeof(cap->bus_info)); + cap->device_caps = V4L2_CAP_VIDEO_CAPTURE; + cap->device_caps |= V4L2_CAP_READWRITE | V4L2_CAP_STREAMING; + cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS; + return 0; +} + +static int usbtv_enum_input(struct file *file, void *priv, + struct v4l2_input *i) +{ + struct usbtv *dev = video_drvdata(file); + + switch (i->index) { + case USBTV_COMPOSITE_INPUT: + strlcpy(i->name, "Composite", sizeof(i->name)); + break; + case USBTV_SVIDEO_INPUT: + strlcpy(i->name, "S-Video", sizeof(i->name)); + break; + default: + return -EINVAL; + } + + i->type = V4L2_INPUT_TYPE_CAMERA; + i->std = dev->vdev.tvnorms; + return 0; +} + +static int usbtv_enum_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_fmtdesc *f) +{ + if (f->index > 0) + return -EINVAL; + + strlcpy(f->description, "16 bpp YUY2, 4:2:2, packed", + sizeof(f->description)); + f->pixelformat = V4L2_PIX_FMT_YUYV; + return 0; +} + +static int usbtv_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct usbtv *usbtv = video_drvdata(file); + + f->fmt.pix.width = usbtv->width; + f->fmt.pix.height = usbtv->height; + f->fmt.pix.pixelformat = V4L2_PIX_FMT_YUYV; + f->fmt.pix.field = V4L2_FIELD_INTERLACED; + f->fmt.pix.bytesperline = usbtv->width * 2; + f->fmt.pix.sizeimage = (f->fmt.pix.bytesperline * f->fmt.pix.height); + f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M; + + return 0; +} + +static int usbtv_g_std(struct file *file, void *priv, v4l2_std_id *norm) +{ + struct usbtv *usbtv = video_drvdata(file); + *norm = usbtv->norm; + return 0; +} + +static int usbtv_s_std(struct file *file, void *priv, v4l2_std_id norm) +{ + int ret = -EINVAL; + struct usbtv *usbtv = video_drvdata(file); + + if ((norm & V4L2_STD_525_60) || (norm & V4L2_STD_PAL)) + ret = usbtv_select_norm(usbtv, norm); + + return ret; +} + +static int usbtv_g_input(struct file *file, void *priv, unsigned int *i) +{ + struct usbtv *usbtv = video_drvdata(file); + *i = usbtv->input; + return 0; +} + +static int usbtv_s_input(struct file *file, void *priv, unsigned int i) +{ + struct usbtv *usbtv = video_drvdata(file); + return usbtv_select_input(usbtv, i); +} + +struct v4l2_ioctl_ops usbtv_ioctl_ops = { + .vidioc_querycap = usbtv_querycap, + .vidioc_enum_input = usbtv_enum_input, + .vidioc_enum_fmt_vid_cap = usbtv_enum_fmt_vid_cap, + .vidioc_g_fmt_vid_cap = usbtv_fmt_vid_cap, + .vidioc_try_fmt_vid_cap = usbtv_fmt_vid_cap, + .vidioc_s_fmt_vid_cap = usbtv_fmt_vid_cap, + .vidioc_g_std = usbtv_g_std, + .vidioc_s_std = usbtv_s_std, + .vidioc_g_input = usbtv_g_input, + .vidioc_s_input = usbtv_s_input, + + .vidioc_reqbufs = vb2_ioctl_reqbufs, + .vidioc_prepare_buf = vb2_ioctl_prepare_buf, + .vidioc_querybuf = vb2_ioctl_querybuf, + .vidioc_create_bufs = vb2_ioctl_create_bufs, + .vidioc_qbuf = vb2_ioctl_qbuf, + .vidioc_dqbuf = vb2_ioctl_dqbuf, + .vidioc_streamon = vb2_ioctl_streamon, + .vidioc_streamoff = vb2_ioctl_streamoff, +}; + +struct v4l2_file_operations usbtv_fops = { + .owner = THIS_MODULE, + .unlocked_ioctl = video_ioctl2, + .mmap = vb2_fop_mmap, + .open = v4l2_fh_open, + .release = vb2_fop_release, + .read = vb2_fop_read, + .poll = vb2_fop_poll, +}; + +static int usbtv_queue_setup(struct vb2_queue *vq, + const struct v4l2_format *v4l_fmt, unsigned int *nbuffers, + unsigned int *nplanes, unsigned int sizes[], void *alloc_ctxs[]) +{ + struct usbtv *usbtv = vb2_get_drv_priv(vq); + + if (*nbuffers < 2) + *nbuffers = 2; + *nplanes = 1; + sizes[0] = USBTV_CHUNK * usbtv->n_chunks * 2 * sizeof(u32); + + return 0; +} + +static void usbtv_buf_queue(struct vb2_buffer *vb) +{ + struct usbtv *usbtv = vb2_get_drv_priv(vb->vb2_queue); + struct usbtv_buf *buf = container_of(vb, struct usbtv_buf, vb); + unsigned long flags; + + if (usbtv->udev == NULL) { + vb2_buffer_done(vb, VB2_BUF_STATE_ERROR); + return; + } + + spin_lock_irqsave(&usbtv->buflock, flags); + list_add_tail(&buf->list, &usbtv->bufs); + spin_unlock_irqrestore(&usbtv->buflock, flags); +} + +static int usbtv_start_streaming(struct vb2_queue *vq, unsigned int count) +{ + struct usbtv *usbtv = vb2_get_drv_priv(vq); + + if (usbtv->udev == NULL) + return -ENODEV; + + return usbtv_start(usbtv); +} + +static int usbtv_stop_streaming(struct vb2_queue *vq) +{ + struct usbtv *usbtv = vb2_get_drv_priv(vq); + + if (usbtv->udev == NULL) + return -ENODEV; + + usbtv_stop(usbtv); + return 0; +} + +struct vb2_ops usbtv_vb2_ops = { + .queue_setup = usbtv_queue_setup, + .buf_queue = usbtv_buf_queue, + .start_streaming = usbtv_start_streaming, + .stop_streaming = usbtv_stop_streaming, +}; + +static void usbtv_release(struct v4l2_device *v4l2_dev) +{ + struct usbtv *usbtv = container_of(v4l2_dev, struct usbtv, v4l2_dev); + + v4l2_device_unregister(&usbtv->v4l2_dev); + vb2_queue_release(&usbtv->vb2q); + kfree(usbtv); +} + +int usbtv_video_init(struct usbtv *usbtv) +{ + int ret; + + (void)usbtv_configure_for_norm(usbtv, V4L2_STD_525_60); + + spin_lock_init(&usbtv->buflock); + mutex_init(&usbtv->v4l2_lock); + mutex_init(&usbtv->vb2q_lock); + INIT_LIST_HEAD(&usbtv->bufs); + + /* videobuf2 structure */ + usbtv->vb2q.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + usbtv->vb2q.io_modes = VB2_MMAP | VB2_USERPTR | VB2_READ; + usbtv->vb2q.drv_priv = usbtv; + usbtv->vb2q.buf_struct_size = sizeof(struct usbtv_buf); + usbtv->vb2q.ops = &usbtv_vb2_ops; + usbtv->vb2q.mem_ops = &vb2_vmalloc_memops; + usbtv->vb2q.timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + usbtv->vb2q.lock = &usbtv->vb2q_lock; + ret = vb2_queue_init(&usbtv->vb2q); + if (ret < 0) { + dev_warn(usbtv->dev, "Could not initialize videobuf2 queue\n"); + return ret; + } + + /* v4l2 structure */ + usbtv->v4l2_dev.release = usbtv_release; + ret = v4l2_device_register(usbtv->dev, &usbtv->v4l2_dev); + if (ret < 0) { + dev_warn(usbtv->dev, "Could not register v4l2 device\n"); + goto v4l2_fail; + } + + /* Video structure */ + strlcpy(usbtv->vdev.name, "usbtv", sizeof(usbtv->vdev.name)); + usbtv->vdev.v4l2_dev = &usbtv->v4l2_dev; + usbtv->vdev.release = video_device_release_empty; + usbtv->vdev.fops = &usbtv_fops; + usbtv->vdev.ioctl_ops = &usbtv_ioctl_ops; + usbtv->vdev.tvnorms = USBTV_TV_STD; + usbtv->vdev.queue = &usbtv->vb2q; + usbtv->vdev.lock = &usbtv->v4l2_lock; + set_bit(V4L2_FL_USE_FH_PRIO, &usbtv->vdev.flags); + video_set_drvdata(&usbtv->vdev, usbtv); + ret = video_register_device(&usbtv->vdev, VFL_TYPE_GRABBER, -1); + if (ret < 0) { + dev_warn(usbtv->dev, "Could not register video device\n"); + goto vdev_fail; + } + + return 0; + +vdev_fail: + v4l2_device_unregister(&usbtv->v4l2_dev); +v4l2_fail: + vb2_queue_release(&usbtv->vb2q); + + return ret; +} + +void usbtv_video_free(struct usbtv *usbtv) +{ + mutex_lock(&usbtv->vb2q_lock); + mutex_lock(&usbtv->v4l2_lock); + + usbtv_stop(usbtv); + video_unregister_device(&usbtv->vdev); + v4l2_device_disconnect(&usbtv->v4l2_dev); + + mutex_unlock(&usbtv->v4l2_lock); + mutex_unlock(&usbtv->vb2q_lock); + + v4l2_device_put(&usbtv->v4l2_dev); +} diff --git a/drivers/media/usb/usbtv/usbtv.c b/drivers/media/usb/usbtv/usbtv.c deleted file mode 100644 index 6222a4a..0000000 --- a/drivers/media/usb/usbtv/usbtv.c +++ /dev/null @@ -1,883 +0,0 @@ -/* - * Fushicai USBTV007 Video Grabber Driver - * - * Product web site: - * http://www.fushicai.com/products_detail/&productId=d05449ee-b690-42f9-a661-aa7353894bed.html - * - * Following LWN articles were very useful in construction of this driver: - * Video4Linux2 API series: http://lwn.net/Articles/203924/ - * videobuf2 API explanation: http://lwn.net/Articles/447435/ - * Thanks go to Jonathan Corbet for providing this quality documentation. - * He is awesome. - * - * Copyright (c) 2013 Lubomir Rintel - * All rights reserved. - * No physical hardware was harmed running Windows during the - * reverse-engineering activity - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions, and the following disclaimer, - * without modification. - * 2. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * Alternatively, this software may be distributed under the terms of the - * GNU General Public License ("GPL"). - */ - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -/* Hardware. */ -#define USBTV_VIDEO_ENDP 0x81 -#define USBTV_BASE 0xc000 -#define USBTV_REQUEST_REG 12 - -/* Number of concurrent isochronous urbs submitted. - * Higher numbers was seen to overly saturate the USB bus. */ -#define USBTV_ISOC_TRANSFERS 16 -#define USBTV_ISOC_PACKETS 8 - -#define USBTV_CHUNK_SIZE 256 -#define USBTV_CHUNK 240 - -/* Chunk header. */ -#define USBTV_MAGIC_OK(chunk) ((be32_to_cpu(chunk[0]) & 0xff000000) \ - == 0x88000000) -#define USBTV_FRAME_ID(chunk) ((be32_to_cpu(chunk[0]) & 0x00ff0000) >> 16) -#define USBTV_ODD(chunk) ((be32_to_cpu(chunk[0]) & 0x0000f000) >> 15) -#define USBTV_CHUNK_NO(chunk) (be32_to_cpu(chunk[0]) & 0x00000fff) - -#define USBTV_TV_STD (V4L2_STD_525_60 | V4L2_STD_PAL) - -/* parameters for supported TV norms */ -struct usbtv_norm_params { - v4l2_std_id norm; - int cap_width, cap_height; -}; - -static struct usbtv_norm_params norm_params[] = { - { - .norm = V4L2_STD_525_60, - .cap_width = 720, - .cap_height = 480, - }, - { - .norm = V4L2_STD_PAL, - .cap_width = 720, - .cap_height = 576, - } -}; - -/* A single videobuf2 frame buffer. */ -struct usbtv_buf { - struct vb2_buffer vb; - struct list_head list; -}; - -/* Per-device structure. */ -struct usbtv { - struct device *dev; - struct usb_device *udev; - struct v4l2_device v4l2_dev; - struct video_device vdev; - struct vb2_queue vb2q; - struct mutex v4l2_lock; - struct mutex vb2q_lock; - - /* List of videobuf2 buffers protected by a lock. */ - spinlock_t buflock; - struct list_head bufs; - - /* Number of currently processed frame, useful find - * out when a new one begins. */ - u32 frame_id; - int chunks_done; - - enum { - USBTV_COMPOSITE_INPUT, - USBTV_SVIDEO_INPUT, - } input; - v4l2_std_id norm; - int width, height; - int n_chunks; - int iso_size; - unsigned int sequence; - struct urb *isoc_urbs[USBTV_ISOC_TRANSFERS]; -}; - -static int usbtv_configure_for_norm(struct usbtv *usbtv, v4l2_std_id norm) -{ - int i, ret = 0; - struct usbtv_norm_params *params = NULL; - - for (i = 0; i < ARRAY_SIZE(norm_params); i++) { - if (norm_params[i].norm & norm) { - params = &norm_params[i]; - break; - } - } - - if (params) { - usbtv->width = params->cap_width; - usbtv->height = params->cap_height; - usbtv->n_chunks = usbtv->width * usbtv->height - / 4 / USBTV_CHUNK; - usbtv->norm = params->norm; - } else - ret = -EINVAL; - - return ret; -} - -static int usbtv_set_regs(struct usbtv *usbtv, const u16 regs[][2], int size) -{ - int ret; - int pipe = usb_rcvctrlpipe(usbtv->udev, 0); - int i; - - for (i = 0; i < size; i++) { - u16 index = regs[i][0]; - u16 value = regs[i][1]; - - ret = usb_control_msg(usbtv->udev, pipe, USBTV_REQUEST_REG, - USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, - value, index, NULL, 0, 0); - if (ret < 0) - return ret; - } - - return 0; -} - -static int usbtv_select_input(struct usbtv *usbtv, int input) -{ - int ret; - - static const u16 composite[][2] = { - { USBTV_BASE + 0x0105, 0x0060 }, - { USBTV_BASE + 0x011f, 0x00f2 }, - { USBTV_BASE + 0x0127, 0x0060 }, - { USBTV_BASE + 0x00ae, 0x0010 }, - { USBTV_BASE + 0x0284, 0x00aa }, - { USBTV_BASE + 0x0239, 0x0060 }, - }; - - static const u16 svideo[][2] = { - { USBTV_BASE + 0x0105, 0x0010 }, - { USBTV_BASE + 0x011f, 0x00ff }, - { USBTV_BASE + 0x0127, 0x0060 }, - { USBTV_BASE + 0x00ae, 0x0030 }, - { USBTV_BASE + 0x0284, 0x0088 }, - { USBTV_BASE + 0x0239, 0x0060 }, - }; - - switch (input) { - case USBTV_COMPOSITE_INPUT: - ret = usbtv_set_regs(usbtv, composite, ARRAY_SIZE(composite)); - break; - case USBTV_SVIDEO_INPUT: - ret = usbtv_set_regs(usbtv, svideo, ARRAY_SIZE(svideo)); - break; - default: - ret = -EINVAL; - } - - if (!ret) - usbtv->input = input; - - return ret; -} - -static int usbtv_select_norm(struct usbtv *usbtv, v4l2_std_id norm) -{ - int ret; - static const u16 pal[][2] = { - { USBTV_BASE + 0x001a, 0x0068 }, - { USBTV_BASE + 0x010e, 0x0072 }, - { USBTV_BASE + 0x010f, 0x00a2 }, - { USBTV_BASE + 0x0112, 0x00b0 }, - { USBTV_BASE + 0x0117, 0x0001 }, - { USBTV_BASE + 0x0118, 0x002c }, - { USBTV_BASE + 0x012d, 0x0010 }, - { USBTV_BASE + 0x012f, 0x0020 }, - { USBTV_BASE + 0x024f, 0x0002 }, - { USBTV_BASE + 0x0254, 0x0059 }, - { USBTV_BASE + 0x025a, 0x0016 }, - { USBTV_BASE + 0x025b, 0x0035 }, - { USBTV_BASE + 0x0263, 0x0017 }, - { USBTV_BASE + 0x0266, 0x0016 }, - { USBTV_BASE + 0x0267, 0x0036 } - }; - - static const u16 ntsc[][2] = { - { USBTV_BASE + 0x001a, 0x0079 }, - { USBTV_BASE + 0x010e, 0x0068 }, - { USBTV_BASE + 0x010f, 0x009c }, - { USBTV_BASE + 0x0112, 0x00f0 }, - { USBTV_BASE + 0x0117, 0x0000 }, - { USBTV_BASE + 0x0118, 0x00fc }, - { USBTV_BASE + 0x012d, 0x0004 }, - { USBTV_BASE + 0x012f, 0x0008 }, - { USBTV_BASE + 0x024f, 0x0001 }, - { USBTV_BASE + 0x0254, 0x005f }, - { USBTV_BASE + 0x025a, 0x0012 }, - { USBTV_BASE + 0x025b, 0x0001 }, - { USBTV_BASE + 0x0263, 0x001c }, - { USBTV_BASE + 0x0266, 0x0011 }, - { USBTV_BASE + 0x0267, 0x0005 } - }; - - ret = usbtv_configure_for_norm(usbtv, norm); - - if (!ret) { - if (norm & V4L2_STD_525_60) - ret = usbtv_set_regs(usbtv, ntsc, ARRAY_SIZE(ntsc)); - else if (norm & V4L2_STD_PAL) - ret = usbtv_set_regs(usbtv, pal, ARRAY_SIZE(pal)); - } - - return ret; -} - -static int usbtv_setup_capture(struct usbtv *usbtv) -{ - int ret; - static const u16 setup[][2] = { - /* These seem to enable the device. */ - { USBTV_BASE + 0x0008, 0x0001 }, - { USBTV_BASE + 0x01d0, 0x00ff }, - { USBTV_BASE + 0x01d9, 0x0002 }, - - /* These seem to influence color parameters, such as - * brightness, etc. */ - { USBTV_BASE + 0x0239, 0x0040 }, - { USBTV_BASE + 0x0240, 0x0000 }, - { USBTV_BASE + 0x0241, 0x0000 }, - { USBTV_BASE + 0x0242, 0x0002 }, - { USBTV_BASE + 0x0243, 0x0080 }, - { USBTV_BASE + 0x0244, 0x0012 }, - { USBTV_BASE + 0x0245, 0x0090 }, - { USBTV_BASE + 0x0246, 0x0000 }, - - { USBTV_BASE + 0x0278, 0x002d }, - { USBTV_BASE + 0x0279, 0x000a }, - { USBTV_BASE + 0x027a, 0x0032 }, - { 0xf890, 0x000c }, - { 0xf894, 0x0086 }, - - { USBTV_BASE + 0x00ac, 0x00c0 }, - { USBTV_BASE + 0x00ad, 0x0000 }, - { USBTV_BASE + 0x00a2, 0x0012 }, - { USBTV_BASE + 0x00a3, 0x00e0 }, - { USBTV_BASE + 0x00a4, 0x0028 }, - { USBTV_BASE + 0x00a5, 0x0082 }, - { USBTV_BASE + 0x00a7, 0x0080 }, - { USBTV_BASE + 0x0000, 0x0014 }, - { USBTV_BASE + 0x0006, 0x0003 }, - { USBTV_BASE + 0x0090, 0x0099 }, - { USBTV_BASE + 0x0091, 0x0090 }, - { USBTV_BASE + 0x0094, 0x0068 }, - { USBTV_BASE + 0x0095, 0x0070 }, - { USBTV_BASE + 0x009c, 0x0030 }, - { USBTV_BASE + 0x009d, 0x00c0 }, - { USBTV_BASE + 0x009e, 0x00e0 }, - { USBTV_BASE + 0x0019, 0x0006 }, - { USBTV_BASE + 0x008c, 0x00ba }, - { USBTV_BASE + 0x0101, 0x00ff }, - { USBTV_BASE + 0x010c, 0x00b3 }, - { USBTV_BASE + 0x01b2, 0x0080 }, - { USBTV_BASE + 0x01b4, 0x00a0 }, - { USBTV_BASE + 0x014c, 0x00ff }, - { USBTV_BASE + 0x014d, 0x00ca }, - { USBTV_BASE + 0x0113, 0x0053 }, - { USBTV_BASE + 0x0119, 0x008a }, - { USBTV_BASE + 0x013c, 0x0003 }, - { USBTV_BASE + 0x0150, 0x009c }, - { USBTV_BASE + 0x0151, 0x0071 }, - { USBTV_BASE + 0x0152, 0x00c6 }, - { USBTV_BASE + 0x0153, 0x0084 }, - { USBTV_BASE + 0x0154, 0x00bc }, - { USBTV_BASE + 0x0155, 0x00a0 }, - { USBTV_BASE + 0x0156, 0x00a0 }, - { USBTV_BASE + 0x0157, 0x009c }, - { USBTV_BASE + 0x0158, 0x001f }, - { USBTV_BASE + 0x0159, 0x0006 }, - { USBTV_BASE + 0x015d, 0x0000 }, - - { USBTV_BASE + 0x0284, 0x0088 }, - { USBTV_BASE + 0x0003, 0x0004 }, - { USBTV_BASE + 0x0100, 0x00d3 }, - { USBTV_BASE + 0x0115, 0x0015 }, - { USBTV_BASE + 0x0220, 0x002e }, - { USBTV_BASE + 0x0225, 0x0008 }, - { USBTV_BASE + 0x024e, 0x0002 }, - { USBTV_BASE + 0x024e, 0x0002 }, - { USBTV_BASE + 0x024f, 0x0002 }, - }; - - ret = usbtv_set_regs(usbtv, setup, ARRAY_SIZE(setup)); - if (ret) - return ret; - - ret = usbtv_select_norm(usbtv, usbtv->norm); - if (ret) - return ret; - - ret = usbtv_select_input(usbtv, usbtv->input); - if (ret) - return ret; - - return 0; -} - -/* Copy data from chunk into a frame buffer, deinterlacing the data - * into every second line. Unfortunately, they don't align nicely into - * 720 pixel lines, as the chunk is 240 words long, which is 480 pixels. - * Therefore, we break down the chunk into two halves before copyting, - * so that we can interleave a line if needed. */ -static void usbtv_chunk_to_vbuf(u32 *frame, u32 *src, int chunk_no, int odd) -{ - int half; - - for (half = 0; half < 2; half++) { - int part_no = chunk_no * 2 + half; - int line = part_no / 3; - int part_index = (line * 2 + !odd) * 3 + (part_no % 3); - - u32 *dst = &frame[part_index * USBTV_CHUNK/2]; - memcpy(dst, src, USBTV_CHUNK/2 * sizeof(*src)); - src += USBTV_CHUNK/2; - } -} - -/* Called for each 256-byte image chunk. - * First word identifies the chunk, followed by 240 words of image - * data and padding. */ -static void usbtv_image_chunk(struct usbtv *usbtv, u32 *chunk) -{ - int frame_id, odd, chunk_no; - u32 *frame; - struct usbtv_buf *buf; - unsigned long flags; - - /* Ignore corrupted lines. */ - if (!USBTV_MAGIC_OK(chunk)) - return; - frame_id = USBTV_FRAME_ID(chunk); - odd = USBTV_ODD(chunk); - chunk_no = USBTV_CHUNK_NO(chunk); - if (chunk_no >= usbtv->n_chunks) - return; - - /* Beginning of a frame. */ - if (chunk_no == 0) { - usbtv->frame_id = frame_id; - usbtv->chunks_done = 0; - } - - if (usbtv->frame_id != frame_id) - return; - - spin_lock_irqsave(&usbtv->buflock, flags); - if (list_empty(&usbtv->bufs)) { - /* No free buffers. Userspace likely too slow. */ - spin_unlock_irqrestore(&usbtv->buflock, flags); - return; - } - - /* First available buffer. */ - buf = list_first_entry(&usbtv->bufs, struct usbtv_buf, list); - frame = vb2_plane_vaddr(&buf->vb, 0); - - /* Copy the chunk data. */ - usbtv_chunk_to_vbuf(frame, &chunk[1], chunk_no, odd); - usbtv->chunks_done++; - - /* Last chunk in a frame, signalling an end */ - if (odd && chunk_no == usbtv->n_chunks-1) { - int size = vb2_plane_size(&buf->vb, 0); - enum vb2_buffer_state state = usbtv->chunks_done == - usbtv->n_chunks ? - VB2_BUF_STATE_DONE : - VB2_BUF_STATE_ERROR; - - buf->vb.v4l2_buf.field = V4L2_FIELD_INTERLACED; - buf->vb.v4l2_buf.sequence = usbtv->sequence++; - v4l2_get_timestamp(&buf->vb.v4l2_buf.timestamp); - vb2_set_plane_payload(&buf->vb, 0, size); - vb2_buffer_done(&buf->vb, state); - list_del(&buf->list); - } - - spin_unlock_irqrestore(&usbtv->buflock, flags); -} - -/* Got image data. Each packet contains a number of 256-word chunks we - * compose the image from. */ -static void usbtv_iso_cb(struct urb *ip) -{ - int ret; - int i; - struct usbtv *usbtv = (struct usbtv *)ip->context; - - switch (ip->status) { - /* All fine. */ - case 0: - break; - /* Device disconnected or capture stopped? */ - case -ENODEV: - case -ENOENT: - case -ECONNRESET: - case -ESHUTDOWN: - return; - /* Unknown error. Retry. */ - default: - dev_warn(usbtv->dev, "Bad response for ISO request.\n"); - goto resubmit; - } - - for (i = 0; i < ip->number_of_packets; i++) { - int size = ip->iso_frame_desc[i].actual_length; - unsigned char *data = ip->transfer_buffer + - ip->iso_frame_desc[i].offset; - int offset; - - for (offset = 0; USBTV_CHUNK_SIZE * offset < size; offset++) - usbtv_image_chunk(usbtv, - (u32 *)&data[USBTV_CHUNK_SIZE * offset]); - } - -resubmit: - ret = usb_submit_urb(ip, GFP_ATOMIC); - if (ret < 0) - dev_warn(usbtv->dev, "Could not resubmit ISO URB\n"); -} - -static struct urb *usbtv_setup_iso_transfer(struct usbtv *usbtv) -{ - struct urb *ip; - int size = usbtv->iso_size; - int i; - - ip = usb_alloc_urb(USBTV_ISOC_PACKETS, GFP_KERNEL); - if (ip == NULL) - return NULL; - - ip->dev = usbtv->udev; - ip->context = usbtv; - ip->pipe = usb_rcvisocpipe(usbtv->udev, USBTV_VIDEO_ENDP); - ip->interval = 1; - ip->transfer_flags = URB_ISO_ASAP; - ip->transfer_buffer = kzalloc(size * USBTV_ISOC_PACKETS, - GFP_KERNEL); - ip->complete = usbtv_iso_cb; - ip->number_of_packets = USBTV_ISOC_PACKETS; - ip->transfer_buffer_length = size * USBTV_ISOC_PACKETS; - for (i = 0; i < USBTV_ISOC_PACKETS; i++) { - ip->iso_frame_desc[i].offset = size * i; - ip->iso_frame_desc[i].length = size; - } - - return ip; -} - -static void usbtv_stop(struct usbtv *usbtv) -{ - int i; - unsigned long flags; - - /* Cancel running transfers. */ - for (i = 0; i < USBTV_ISOC_TRANSFERS; i++) { - struct urb *ip = usbtv->isoc_urbs[i]; - if (ip == NULL) - continue; - usb_kill_urb(ip); - kfree(ip->transfer_buffer); - usb_free_urb(ip); - usbtv->isoc_urbs[i] = NULL; - } - - /* Return buffers to userspace. */ - spin_lock_irqsave(&usbtv->buflock, flags); - while (!list_empty(&usbtv->bufs)) { - struct usbtv_buf *buf = list_first_entry(&usbtv->bufs, - struct usbtv_buf, list); - vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR); - list_del(&buf->list); - } - spin_unlock_irqrestore(&usbtv->buflock, flags); -} - -static int usbtv_start(struct usbtv *usbtv) -{ - int i; - int ret; - - ret = usb_set_interface(usbtv->udev, 0, 0); - if (ret < 0) - return ret; - - ret = usbtv_setup_capture(usbtv); - if (ret < 0) - return ret; - - ret = usb_set_interface(usbtv->udev, 0, 1); - if (ret < 0) - return ret; - - for (i = 0; i < USBTV_ISOC_TRANSFERS; i++) { - struct urb *ip; - - ip = usbtv_setup_iso_transfer(usbtv); - if (ip == NULL) { - ret = -ENOMEM; - goto start_fail; - } - usbtv->isoc_urbs[i] = ip; - - ret = usb_submit_urb(ip, GFP_KERNEL); - if (ret < 0) - goto start_fail; - } - - return 0; - -start_fail: - usbtv_stop(usbtv); - return ret; -} - -struct usb_device_id usbtv_id_table[] = { - { USB_DEVICE(0x1b71, 0x3002) }, - {} -}; -MODULE_DEVICE_TABLE(usb, usbtv_id_table); - -static int usbtv_querycap(struct file *file, void *priv, - struct v4l2_capability *cap) -{ - struct usbtv *dev = video_drvdata(file); - - strlcpy(cap->driver, "usbtv", sizeof(cap->driver)); - strlcpy(cap->card, "usbtv", sizeof(cap->card)); - usb_make_path(dev->udev, cap->bus_info, sizeof(cap->bus_info)); - cap->device_caps = V4L2_CAP_VIDEO_CAPTURE; - cap->device_caps |= V4L2_CAP_READWRITE | V4L2_CAP_STREAMING; - cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS; - return 0; -} - -static int usbtv_enum_input(struct file *file, void *priv, - struct v4l2_input *i) -{ - struct usbtv *dev = video_drvdata(file); - - switch (i->index) { - case USBTV_COMPOSITE_INPUT: - strlcpy(i->name, "Composite", sizeof(i->name)); - break; - case USBTV_SVIDEO_INPUT: - strlcpy(i->name, "S-Video", sizeof(i->name)); - break; - default: - return -EINVAL; - } - - i->type = V4L2_INPUT_TYPE_CAMERA; - i->std = dev->vdev.tvnorms; - return 0; -} - -static int usbtv_enum_fmt_vid_cap(struct file *file, void *priv, - struct v4l2_fmtdesc *f) -{ - if (f->index > 0) - return -EINVAL; - - strlcpy(f->description, "16 bpp YUY2, 4:2:2, packed", - sizeof(f->description)); - f->pixelformat = V4L2_PIX_FMT_YUYV; - return 0; -} - -static int usbtv_fmt_vid_cap(struct file *file, void *priv, - struct v4l2_format *f) -{ - struct usbtv *usbtv = video_drvdata(file); - - f->fmt.pix.width = usbtv->width; - f->fmt.pix.height = usbtv->height; - f->fmt.pix.pixelformat = V4L2_PIX_FMT_YUYV; - f->fmt.pix.field = V4L2_FIELD_INTERLACED; - f->fmt.pix.bytesperline = usbtv->width * 2; - f->fmt.pix.sizeimage = (f->fmt.pix.bytesperline * f->fmt.pix.height); - f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M; - - return 0; -} - -static int usbtv_g_std(struct file *file, void *priv, v4l2_std_id *norm) -{ - struct usbtv *usbtv = video_drvdata(file); - *norm = usbtv->norm; - return 0; -} - -static int usbtv_s_std(struct file *file, void *priv, v4l2_std_id norm) -{ - int ret = -EINVAL; - struct usbtv *usbtv = video_drvdata(file); - - if ((norm & V4L2_STD_525_60) || (norm & V4L2_STD_PAL)) - ret = usbtv_select_norm(usbtv, norm); - - return ret; -} - -static int usbtv_g_input(struct file *file, void *priv, unsigned int *i) -{ - struct usbtv *usbtv = video_drvdata(file); - *i = usbtv->input; - return 0; -} - -static int usbtv_s_input(struct file *file, void *priv, unsigned int i) -{ - struct usbtv *usbtv = video_drvdata(file); - return usbtv_select_input(usbtv, i); -} - -struct v4l2_ioctl_ops usbtv_ioctl_ops = { - .vidioc_querycap = usbtv_querycap, - .vidioc_enum_input = usbtv_enum_input, - .vidioc_enum_fmt_vid_cap = usbtv_enum_fmt_vid_cap, - .vidioc_g_fmt_vid_cap = usbtv_fmt_vid_cap, - .vidioc_try_fmt_vid_cap = usbtv_fmt_vid_cap, - .vidioc_s_fmt_vid_cap = usbtv_fmt_vid_cap, - .vidioc_g_std = usbtv_g_std, - .vidioc_s_std = usbtv_s_std, - .vidioc_g_input = usbtv_g_input, - .vidioc_s_input = usbtv_s_input, - - .vidioc_reqbufs = vb2_ioctl_reqbufs, - .vidioc_prepare_buf = vb2_ioctl_prepare_buf, - .vidioc_querybuf = vb2_ioctl_querybuf, - .vidioc_create_bufs = vb2_ioctl_create_bufs, - .vidioc_qbuf = vb2_ioctl_qbuf, - .vidioc_dqbuf = vb2_ioctl_dqbuf, - .vidioc_streamon = vb2_ioctl_streamon, - .vidioc_streamoff = vb2_ioctl_streamoff, -}; - -struct v4l2_file_operations usbtv_fops = { - .owner = THIS_MODULE, - .unlocked_ioctl = video_ioctl2, - .mmap = vb2_fop_mmap, - .open = v4l2_fh_open, - .release = vb2_fop_release, - .read = vb2_fop_read, - .poll = vb2_fop_poll, -}; - -static int usbtv_queue_setup(struct vb2_queue *vq, - const struct v4l2_format *v4l_fmt, unsigned int *nbuffers, - unsigned int *nplanes, unsigned int sizes[], void *alloc_ctxs[]) -{ - struct usbtv *usbtv = vb2_get_drv_priv(vq); - - if (*nbuffers < 2) - *nbuffers = 2; - *nplanes = 1; - sizes[0] = USBTV_CHUNK * usbtv->n_chunks * 2 * sizeof(u32); - - return 0; -} - -static void usbtv_buf_queue(struct vb2_buffer *vb) -{ - struct usbtv *usbtv = vb2_get_drv_priv(vb->vb2_queue); - struct usbtv_buf *buf = container_of(vb, struct usbtv_buf, vb); - unsigned long flags; - - if (usbtv->udev == NULL) { - vb2_buffer_done(vb, VB2_BUF_STATE_ERROR); - return; - } - - spin_lock_irqsave(&usbtv->buflock, flags); - list_add_tail(&buf->list, &usbtv->bufs); - spin_unlock_irqrestore(&usbtv->buflock, flags); -} - -static int usbtv_start_streaming(struct vb2_queue *vq, unsigned int count) -{ - struct usbtv *usbtv = vb2_get_drv_priv(vq); - - if (usbtv->udev == NULL) - return -ENODEV; - - return usbtv_start(usbtv); -} - -static int usbtv_stop_streaming(struct vb2_queue *vq) -{ - struct usbtv *usbtv = vb2_get_drv_priv(vq); - - if (usbtv->udev == NULL) - return -ENODEV; - - usbtv_stop(usbtv); - return 0; -} - -struct vb2_ops usbtv_vb2_ops = { - .queue_setup = usbtv_queue_setup, - .buf_queue = usbtv_buf_queue, - .start_streaming = usbtv_start_streaming, - .stop_streaming = usbtv_stop_streaming, -}; - -static void usbtv_release(struct v4l2_device *v4l2_dev) -{ - struct usbtv *usbtv = container_of(v4l2_dev, struct usbtv, v4l2_dev); - - v4l2_device_unregister(&usbtv->v4l2_dev); - vb2_queue_release(&usbtv->vb2q); - kfree(usbtv); -} - -static int usbtv_probe(struct usb_interface *intf, - const struct usb_device_id *id) -{ - int ret; - int size; - struct device *dev = &intf->dev; - struct usbtv *usbtv; - - /* Checks that the device is what we think it is. */ - if (intf->num_altsetting != 2) - return -ENODEV; - if (intf->altsetting[1].desc.bNumEndpoints != 4) - return -ENODEV; - - /* Packet size is split into 11 bits of base size and count of - * extra multiplies of it.*/ - size = usb_endpoint_maxp(&intf->altsetting[1].endpoint[0].desc); - size = (size & 0x07ff) * (((size & 0x1800) >> 11) + 1); - - /* Device structure */ - usbtv = kzalloc(sizeof(struct usbtv), GFP_KERNEL); - if (usbtv == NULL) - return -ENOMEM; - usbtv->dev = dev; - usbtv->udev = usb_get_dev(interface_to_usbdev(intf)); - - usbtv->iso_size = size; - - (void)usbtv_configure_for_norm(usbtv, V4L2_STD_525_60); - - spin_lock_init(&usbtv->buflock); - mutex_init(&usbtv->v4l2_lock); - mutex_init(&usbtv->vb2q_lock); - INIT_LIST_HEAD(&usbtv->bufs); - - /* videobuf2 structure */ - usbtv->vb2q.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; - usbtv->vb2q.io_modes = VB2_MMAP | VB2_USERPTR | VB2_READ; - usbtv->vb2q.drv_priv = usbtv; - usbtv->vb2q.buf_struct_size = sizeof(struct usbtv_buf); - usbtv->vb2q.ops = &usbtv_vb2_ops; - usbtv->vb2q.mem_ops = &vb2_vmalloc_memops; - usbtv->vb2q.timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; - usbtv->vb2q.lock = &usbtv->vb2q_lock; - ret = vb2_queue_init(&usbtv->vb2q); - if (ret < 0) { - dev_warn(dev, "Could not initialize videobuf2 queue\n"); - goto usbtv_fail; - } - - /* v4l2 structure */ - usbtv->v4l2_dev.release = usbtv_release; - ret = v4l2_device_register(dev, &usbtv->v4l2_dev); - if (ret < 0) { - dev_warn(dev, "Could not register v4l2 device\n"); - goto v4l2_fail; - } - - usb_set_intfdata(intf, usbtv); - - /* Video structure */ - strlcpy(usbtv->vdev.name, "usbtv", sizeof(usbtv->vdev.name)); - usbtv->vdev.v4l2_dev = &usbtv->v4l2_dev; - usbtv->vdev.release = video_device_release_empty; - usbtv->vdev.fops = &usbtv_fops; - usbtv->vdev.ioctl_ops = &usbtv_ioctl_ops; - usbtv->vdev.tvnorms = USBTV_TV_STD; - usbtv->vdev.queue = &usbtv->vb2q; - usbtv->vdev.lock = &usbtv->v4l2_lock; - set_bit(V4L2_FL_USE_FH_PRIO, &usbtv->vdev.flags); - video_set_drvdata(&usbtv->vdev, usbtv); - ret = video_register_device(&usbtv->vdev, VFL_TYPE_GRABBER, -1); - if (ret < 0) { - dev_warn(dev, "Could not register video device\n"); - goto vdev_fail; - } - - dev_info(dev, "Fushicai USBTV007 Video Grabber\n"); - return 0; - -vdev_fail: - v4l2_device_unregister(&usbtv->v4l2_dev); -v4l2_fail: - vb2_queue_release(&usbtv->vb2q); -usbtv_fail: - kfree(usbtv); - - return ret; -} - -static void usbtv_disconnect(struct usb_interface *intf) -{ - struct usbtv *usbtv = usb_get_intfdata(intf); - - mutex_lock(&usbtv->vb2q_lock); - mutex_lock(&usbtv->v4l2_lock); - - usbtv_stop(usbtv); - usb_set_intfdata(intf, NULL); - video_unregister_device(&usbtv->vdev); - v4l2_device_disconnect(&usbtv->v4l2_dev); - usb_put_dev(usbtv->udev); - usbtv->udev = NULL; - - mutex_unlock(&usbtv->v4l2_lock); - mutex_unlock(&usbtv->vb2q_lock); - - v4l2_device_put(&usbtv->v4l2_dev); -} - -MODULE_AUTHOR("Lubomir Rintel"); -MODULE_DESCRIPTION("Fushicai USBTV007 Video Grabber Driver"); -MODULE_LICENSE("Dual BSD/GPL"); - -struct usb_driver usbtv_usb_driver = { - .name = "usbtv", - .id_table = usbtv_id_table, - .probe = usbtv_probe, - .disconnect = usbtv_disconnect, -}; - -module_usb_driver(usbtv_usb_driver); diff --git a/drivers/media/usb/usbtv/usbtv.h b/drivers/media/usb/usbtv/usbtv.h new file mode 100644 index 0000000..536343d --- /dev/null +++ b/drivers/media/usb/usbtv/usbtv.h @@ -0,0 +1,98 @@ +/* + * Fushicai USBTV007 Video Grabber Driver + * + * Copyright (c) 2013 Lubomir Rintel + * All rights reserved. + * No physical hardware was harmed running Windows during the + * reverse-engineering activity + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer, + * without modification. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * Alternatively, this software may be distributed under the terms of the + * GNU General Public License ("GPL"). + */ + +#include +#include + +#include +#include + +/* Hardware. */ +#define USBTV_VIDEO_ENDP 0x81 +#define USBTV_BASE 0xc000 +#define USBTV_REQUEST_REG 12 + +/* Number of concurrent isochronous urbs submitted. + * Higher numbers was seen to overly saturate the USB bus. */ +#define USBTV_ISOC_TRANSFERS 16 +#define USBTV_ISOC_PACKETS 8 + +#define USBTV_CHUNK_SIZE 256 +#define USBTV_CHUNK 240 + +/* Chunk header. */ +#define USBTV_MAGIC_OK(chunk) ((be32_to_cpu(chunk[0]) & 0xff000000) \ + == 0x88000000) +#define USBTV_FRAME_ID(chunk) ((be32_to_cpu(chunk[0]) & 0x00ff0000) >> 16) +#define USBTV_ODD(chunk) ((be32_to_cpu(chunk[0]) & 0x0000f000) >> 15) +#define USBTV_CHUNK_NO(chunk) (be32_to_cpu(chunk[0]) & 0x00000fff) + +#define USBTV_TV_STD (V4L2_STD_525_60 | V4L2_STD_PAL) + +/* parameters for supported TV norms */ +struct usbtv_norm_params { + v4l2_std_id norm; + int cap_width, cap_height; +}; + +/* A single videobuf2 frame buffer. */ +struct usbtv_buf { + struct vb2_buffer vb; + struct list_head list; +}; + +/* Per-device structure. */ +struct usbtv { + struct device *dev; + struct usb_device *udev; + + /* video */ + struct v4l2_device v4l2_dev; + struct video_device vdev; + struct vb2_queue vb2q; + struct mutex v4l2_lock; + struct mutex vb2q_lock; + + /* List of videobuf2 buffers protected by a lock. */ + spinlock_t buflock; + struct list_head bufs; + + /* Number of currently processed frame, useful find + * out when a new one begins. */ + u32 frame_id; + int chunks_done; + + enum { + USBTV_COMPOSITE_INPUT, + USBTV_SVIDEO_INPUT, + } input; + v4l2_std_id norm; + int width, height; + int n_chunks; + int iso_size; + unsigned int sequence; + struct urb *isoc_urbs[USBTV_ISOC_TRANSFERS]; +}; + +int usbtv_set_regs(struct usbtv *usbtv, const u16 regs[][2], int size); + +int usbtv_video_init(struct usbtv *usbtv); +void usbtv_video_free(struct usbtv *usbtv); -- cgit v1.1 From 9fd9330c2d0ae6c149ec817ec71797f943db98b4 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Tue, 4 Feb 2014 06:00:52 -0300 Subject: [media] usbtv: fix compiler error due to missing module.h usbtv-video.c needs module.h. So move the module.h include from usbtv-core.c to usbtv.h, that way both core.c and video.c have it. Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/usbtv/usbtv-core.c | 2 -- drivers/media/usb/usbtv/usbtv.h | 1 + 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/media/usb/usbtv/usbtv-core.c b/drivers/media/usb/usbtv/usbtv-core.c index e89e48b..d543928 100644 --- a/drivers/media/usb/usbtv/usbtv-core.c +++ b/drivers/media/usb/usbtv/usbtv-core.c @@ -28,8 +28,6 @@ * GNU General Public License ("GPL"). */ -#include - #include "usbtv.h" int usbtv_set_regs(struct usbtv *usbtv, const u16 regs[][2], int size) diff --git a/drivers/media/usb/usbtv/usbtv.h b/drivers/media/usb/usbtv/usbtv.h index 536343d..cb1d388 100644 --- a/drivers/media/usb/usbtv/usbtv.h +++ b/drivers/media/usb/usbtv/usbtv.h @@ -19,6 +19,7 @@ * GNU General Public License ("GPL"). */ +#include #include #include -- cgit v1.1 From 3857fcdee98911570770e61fc0480478a613117c Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Fri, 17 Jan 2014 07:27:27 -0300 Subject: [media] usbvision: drop unused define USBVISION_SAY_AND_WAIT This define uses the deprecated interruptible_sleep_on_timeout function. Since this define is unused anyway we just remove it. Signed-off-by: Hans Verkuil Cc: Arnd Bergmann Acked-by: Arnd Bergmann Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/usbvision/usbvision.h | 8 -------- 1 file changed, 8 deletions(-) diff --git a/drivers/media/usb/usbvision/usbvision.h b/drivers/media/usb/usbvision/usbvision.h index 8a25876..a0c73cf 100644 --- a/drivers/media/usb/usbvision/usbvision.h +++ b/drivers/media/usb/usbvision/usbvision.h @@ -203,14 +203,6 @@ enum { mr = LIMIT_RGB(mm_r); \ } -/* Debugging aid */ -#define USBVISION_SAY_AND_WAIT(what) { \ - wait_queue_head_t wq; \ - init_waitqueue_head(&wq); \ - printk(KERN_INFO "Say: %s\n", what); \ - interruptible_sleep_on_timeout(&wq, HZ * 3); \ -} - /* * This macro checks if usbvision is still operational. The 'usbvision' * pointer must be valid, usbvision->dev must be valid, we are not -- cgit v1.1 From 7c869651455d456af943c88797de3fcff44ecfde Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Mon, 20 Jan 2014 06:27:09 -0300 Subject: [media] s3c-camif: Remove use of deprecated V4L2_CTRL_FLAG_DISABLED I came across this while checking the kernel use of V4L2_CTRL_FLAG_DISABLED. This flag should not be used with the control framework. Instead, just don't add the control at all. Signed-off-by: Hans Verkuil Acked-by: Sylwester Nawrocki Signed-off-by: Mauro Carvalho Chehab --- drivers/media/platform/s3c-camif/camif-capture.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/media/platform/s3c-camif/camif-capture.c b/drivers/media/platform/s3c-camif/camif-capture.c index 40b298a..5372111 100644 --- a/drivers/media/platform/s3c-camif/camif-capture.c +++ b/drivers/media/platform/s3c-camif/camif-capture.c @@ -1592,26 +1592,27 @@ int s3c_camif_create_subdev(struct camif_dev *camif) ARRAY_SIZE(s3c_camif_test_pattern_menu) - 1, 0, 0, s3c_camif_test_pattern_menu); - camif->ctrl_colorfx = v4l2_ctrl_new_std_menu(handler, + if (camif->variant->has_img_effect) { + camif->ctrl_colorfx = v4l2_ctrl_new_std_menu(handler, &s3c_camif_subdev_ctrl_ops, V4L2_CID_COLORFX, V4L2_COLORFX_SET_CBCR, ~0x981f, V4L2_COLORFX_NONE); - camif->ctrl_colorfx_cbcr = v4l2_ctrl_new_std(handler, + camif->ctrl_colorfx_cbcr = v4l2_ctrl_new_std(handler, &s3c_camif_subdev_ctrl_ops, V4L2_CID_COLORFX_CBCR, 0, 0xffff, 1, 0); + } + if (handler->error) { v4l2_ctrl_handler_free(handler); media_entity_cleanup(&sd->entity); return handler->error; } - v4l2_ctrl_auto_cluster(2, &camif->ctrl_colorfx, + if (camif->variant->has_img_effect) + v4l2_ctrl_auto_cluster(2, &camif->ctrl_colorfx, V4L2_COLORFX_SET_CBCR, false); - if (!camif->variant->has_img_effect) { - camif->ctrl_colorfx->flags |= V4L2_CTRL_FLAG_DISABLED; - camif->ctrl_colorfx_cbcr->flags |= V4L2_CTRL_FLAG_DISABLED; - } + sd->ctrl_handler = handler; v4l2_set_subdevdata(sd, camif); -- cgit v1.1 From 933913da020d0a6099e00fbb652fb682996fba45 Mon Sep 17 00:00:00 2001 From: Martin Bugge Date: Fri, 24 Jan 2014 10:50:03 -0300 Subject: [media] adv7842: adjust gain and offset for DVI-D signals If the input signal is DVI-D and quantization range is RGB full range, gain and offset must be adjusted to get the right range on the output. Copied and adopted from adv7604. Signed-off-by: Martin Bugge Cc: Mats Randgaard Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/i2c/adv7842.c | 109 ++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 99 insertions(+), 10 deletions(-) diff --git a/drivers/media/i2c/adv7842.c b/drivers/media/i2c/adv7842.c index 1effc21..f7a4d79 100644 --- a/drivers/media/i2c/adv7842.c +++ b/drivers/media/i2c/adv7842.c @@ -546,6 +546,14 @@ static void main_reset(struct v4l2_subdev *sd) /* ----------------------------------------------------------------------- */ +static inline bool is_analog_input(struct v4l2_subdev *sd) +{ + struct adv7842_state *state = to_state(sd); + + return ((state->mode == ADV7842_MODE_RGB) || + (state->mode == ADV7842_MODE_COMP)); +} + static inline bool is_digital_input(struct v4l2_subdev *sd) { struct adv7842_state *state = to_state(sd); @@ -1027,12 +1035,72 @@ static void configure_custom_video_timings(struct v4l2_subdev *sd, cp_write(sd, 0xac, (height & 0x0f) << 4); } +static void adv7842_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c) +{ + struct adv7842_state *state = to_state(sd); + u8 offset_buf[4]; + + if (auto_offset) { + offset_a = 0x3ff; + offset_b = 0x3ff; + offset_c = 0x3ff; + } + + v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n", + __func__, auto_offset ? "Auto" : "Manual", + offset_a, offset_b, offset_c); + + offset_buf[0]= (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4); + offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6); + offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8); + offset_buf[3] = offset_c & 0x0ff; + + /* Registers must be written in this order with no i2c access in between */ + if (adv_smbus_write_i2c_block_data(state->i2c_cp, 0x77, 4, offset_buf)) + v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__); +} + +static void adv7842_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c) +{ + struct adv7842_state *state = to_state(sd); + u8 gain_buf[4]; + u8 gain_man = 1; + u8 agc_mode_man = 1; + + if (auto_gain) { + gain_man = 0; + agc_mode_man = 0; + gain_a = 0x100; + gain_b = 0x100; + gain_c = 0x100; + } + + v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n", + __func__, auto_gain ? "Auto" : "Manual", + gain_a, gain_b, gain_c); + + gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4)); + gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6)); + gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8)); + gain_buf[3] = ((gain_c & 0x0ff)); + + /* Registers must be written in this order with no i2c access in between */ + if (adv_smbus_write_i2c_block_data(state->i2c_cp, 0x73, 4, gain_buf)) + v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__); +} + static void set_rgb_quantization_range(struct v4l2_subdev *sd) { struct adv7842_state *state = to_state(sd); + bool rgb_output = io_read(sd, 0x02) & 0x02; + bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80; + + v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n", + __func__, state->rgb_quantization_range, + rgb_output, hdmi_signal); - v4l2_dbg(2, debug, sd, "%s: rgb_quantization_range = %d\n", - __func__, state->rgb_quantization_range); + adv7842_set_gain(sd, true, 0x0, 0x0, 0x0); + adv7842_set_offset(sd, true, 0x0, 0x0, 0x0); switch (state->rgb_quantization_range) { case V4L2_DV_RGB_RANGE_AUTO: @@ -1050,7 +1118,7 @@ static void set_rgb_quantization_range(struct v4l2_subdev *sd) break; } - if (hdmi_read(sd, 0x05) & 0x80) { + if (hdmi_signal) { /* Receiving HDMI signal * Set automode */ io_write_and_or(sd, 0x02, 0x0f, 0xf0); @@ -1066,24 +1134,45 @@ static void set_rgb_quantization_range(struct v4l2_subdev *sd) } else { /* RGB full range (0-255) */ io_write_and_or(sd, 0x02, 0x0f, 0x10); + + if (is_digital_input(sd) && rgb_output) { + adv7842_set_offset(sd, false, 0x40, 0x40, 0x40); + } else { + adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0); + adv7842_set_offset(sd, false, 0x70, 0x70, 0x70); + } } break; case V4L2_DV_RGB_RANGE_LIMITED: if (state->mode == ADV7842_MODE_COMP) { /* YCrCb limited range (16-235) */ io_write_and_or(sd, 0x02, 0x0f, 0x20); - } else { - /* RGB limited range (16-235) */ - io_write_and_or(sd, 0x02, 0x0f, 0x00); + break; } + + /* RGB limited range (16-235) */ + io_write_and_or(sd, 0x02, 0x0f, 0x00); + break; case V4L2_DV_RGB_RANGE_FULL: if (state->mode == ADV7842_MODE_COMP) { /* YCrCb full range (0-255) */ io_write_and_or(sd, 0x02, 0x0f, 0x60); + break; + } + + /* RGB full range (0-255) */ + io_write_and_or(sd, 0x02, 0x0f, 0x10); + + if (is_analog_input(sd) || hdmi_signal) + break; + + /* Adjust gain/offset for DVI-D signals only */ + if (rgb_output) { + adv7842_set_offset(sd, false, 0x40, 0x40, 0x40); } else { - /* RGB full range (0-255) */ - io_write_and_or(sd, 0x02, 0x0f, 0x10); + adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0); + adv7842_set_offset(sd, false, 0x70, 0x70, 0x70); } break; } @@ -1717,8 +1806,8 @@ static void select_input(struct v4l2_subdev *sd, * (rev. 2.5, June 2010)" p. 17. */ afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */ afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */ - cp_write(sd, 0x3e, 0x80); /* CP core pre-gain control, - enable color control */ + cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */ + /* CP coast control */ cp_write(sd, 0xc3, 0x33); /* Component mode */ -- cgit v1.1 From 81ba0a4e0ba4f92573440b8c455fc0d30f111092 Mon Sep 17 00:00:00 2001 From: Martin Bugge Date: Fri, 24 Jan 2014 10:50:04 -0300 Subject: [media] adv7842: pixelclock read-out Incorrect registers used for pixelclock read-out. Same registers as for adv7604 which actually gave an almost correct read-out, even they are not documented for adv7842. Corrected deep-color pixel-clock correction. Signed-off-by: Martin Bugge Cc: Mats Randgaard Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/i2c/adv7842.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/media/i2c/adv7842.c b/drivers/media/i2c/adv7842.c index f7a4d79..3aa1a7c 100644 --- a/drivers/media/i2c/adv7842.c +++ b/drivers/media/i2c/adv7842.c @@ -1449,12 +1449,11 @@ static int adv7842_query_dv_timings(struct v4l2_subdev *sd, bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08); bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a); - freq = (hdmi_read(sd, 0x06) * 1000000) + - ((hdmi_read(sd, 0x3b) & 0x30) >> 4) * 250000; - + freq = ((hdmi_read(sd, 0x51) << 1) + (hdmi_read(sd, 0x52) >> 7)) * 1000000; + freq += ((hdmi_read(sd, 0x52) & 0x7f) * 7813); if (is_hdmi(sd)) { /* adjust for deep color mode */ - freq = freq * 8 / (((hdmi_read(sd, 0x0b) & 0xc0) >> 5) + 8); + freq = freq * 8 / (((hdmi_read(sd, 0x0b) & 0xc0) >> 6) * 2 + 8); } bt->pixelclock = freq; bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 + -- cgit v1.1 From b60908a4e5164835678728bf185af9807e0e4560 Mon Sep 17 00:00:00 2001 From: Martin Bugge Date: Fri, 24 Jan 2014 10:50:05 -0300 Subject: [media] adv7842: log-status for Audio Video Info frames (AVI) Clear any pending AVI checksum-errors. To be able to display last received AVI. Signed-off-by: Martin Bugge Cc: Mats Randgaard Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/i2c/adv7842.c | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/drivers/media/i2c/adv7842.c b/drivers/media/i2c/adv7842.c index 3aa1a7c..209b175 100644 --- a/drivers/media/i2c/adv7842.c +++ b/drivers/media/i2c/adv7842.c @@ -2191,7 +2191,8 @@ static void print_avi_infoframe(struct v4l2_subdev *sd) { int i; uint8_t buf[14]; - uint8_t avi_inf_len; + u8 avi_len; + u8 avi_ver; struct avi_info_frame avi; if (!(hdmi_read(sd, 0x05) & 0x80)) { @@ -2204,18 +2205,20 @@ static void print_avi_infoframe(struct v4l2_subdev *sd) } if (io_read(sd, 0x88) & 0x10) { - /* Note: the ADV7842 calculated incorrect checksums for InfoFrames - with a length of 14 or 15. See the ADV7842 Register Settings - Recommendations document for more details. */ - v4l2_info(sd, "AVI infoframe checksum error\n"); - return; + v4l2_info(sd, "AVI infoframe checksum error has occurred earlier\n"); + io_write(sd, 0x8a, 0x10); /* clear AVI_INF_CKS_ERR_RAW */ + if (io_read(sd, 0x88) & 0x10) { + v4l2_info(sd, "AVI infoframe checksum error still present\n"); + io_write(sd, 0x8a, 0x10); /* clear AVI_INF_CKS_ERR_RAW */ + } } - avi_inf_len = infoframe_read(sd, 0xe2); + avi_len = infoframe_read(sd, 0xe2); + avi_ver = infoframe_read(sd, 0xe1); v4l2_info(sd, "AVI infoframe version %d (%d byte)\n", - infoframe_read(sd, 0xe1), avi_inf_len); + avi_ver, avi_len); - if (infoframe_read(sd, 0xe1) != 0x02) + if (avi_ver != 0x02) return; for (i = 0; i < 14; i++) -- cgit v1.1 From ce2d2b2d7a764cc9481efd896f119799a4aeafaf Mon Sep 17 00:00:00 2001 From: Martin Bugge Date: Fri, 24 Jan 2014 10:50:06 -0300 Subject: [media] adv7842: platform-data for Hotplug Active (HPA) manual/auto This applies to HDMI-map register 0x69. So far we have been using HPA manual mode. This way we had control of HPA which could be set after EDID had been programmed. Using a Mac Mini with mini-displayport to DVI-D converter as source caused the adv7842 to lock up and fail to detect any further signals. After experimenting with different configurations it was found that using the HPA auto mode and in addition letting RX-termination be controlled by HPA prevented this error from occuring. I was not able to re-create this problem on the adv7604. Signed-off-by: Martin Bugge Cc: Mats Randgaard Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/i2c/adv7842.c | 12 +++++++++--- include/media/adv7842.h | 3 +++ 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/media/i2c/adv7842.c b/drivers/media/i2c/adv7842.c index 209b175..e04fe3f 100644 --- a/drivers/media/i2c/adv7842.c +++ b/drivers/media/i2c/adv7842.c @@ -2693,9 +2693,15 @@ static int adv7842_core_init(struct v4l2_subdev *sd) /* disable I2C access to internal EDID ram from HDMI DDC ports */ rep_write_and_or(sd, 0x77, 0xf3, 0x00); - hdmi_write(sd, 0x69, 0xa3); /* HPA manual */ - /* HPA disable on port A and B */ - io_write_and_or(sd, 0x20, 0xcf, 0x00); + if (pdata->hpa_auto) { + /* HPA auto, HPA 0.5s after Edid set and Cable detect */ + hdmi_write(sd, 0x69, 0x5c); + } else { + /* HPA manual */ + hdmi_write(sd, 0x69, 0xa3); + /* HPA disable on port A and B */ + io_write_and_or(sd, 0x20, 0xcf, 0x00); + } /* LLC */ io_write(sd, 0x19, 0x80 | pdata->llc_dll_phase); diff --git a/include/media/adv7842.h b/include/media/adv7842.h index 3932209..924cbb8 100644 --- a/include/media/adv7842.h +++ b/include/media/adv7842.h @@ -220,6 +220,9 @@ struct adv7842_platform_data { unsigned sdp_free_run_cbar_en:1; unsigned sdp_free_run_force:1; + /* HPA manual (0) or auto (1), affects HDMI register 0x69 */ + unsigned hpa_auto:1; + struct adv7842_sdp_csc_coeff sdp_csc_coeff; struct adv7842_sdp_io_sync_adjustment sdp_io_sync_625; -- cgit v1.1 From 2d27b37d3598b1ae57c48a3ac8ce388708d8cab8 Mon Sep 17 00:00:00 2001 From: Sachin Kamat Date: Mon, 27 Jan 2014 08:56:02 -0300 Subject: [media] radio-keene: Use module_usb_driver module_usb_driver eliminates the boilerplate and makes the code simpler. Signed-off-by: Sachin Kamat Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/radio/radio-keene.c | 19 +------------------ 1 file changed, 1 insertion(+), 18 deletions(-) diff --git a/drivers/media/radio/radio-keene.c b/drivers/media/radio/radio-keene.c index fa39640..3d12782 100644 --- a/drivers/media/radio/radio-keene.c +++ b/drivers/media/radio/radio-keene.c @@ -416,22 +416,5 @@ static struct usb_driver usb_keene_driver = { .reset_resume = usb_keene_resume, }; -static int __init keene_init(void) -{ - int retval = usb_register(&usb_keene_driver); - - if (retval) - pr_err(KBUILD_MODNAME - ": usb_register failed. Error number %d\n", retval); - - return retval; -} - -static void __exit keene_exit(void) -{ - usb_deregister(&usb_keene_driver); -} - -module_init(keene_init); -module_exit(keene_exit); +module_usb_driver(usb_keene_driver); -- cgit v1.1 From f5402007da542ec5a583e92b8b6e2a96d625b537 Mon Sep 17 00:00:00 2001 From: sensoray-dev Date: Wed, 29 Jan 2014 15:24:07 -0300 Subject: [media] s2255drv: checkpatch fix: coding style fix Fixes all style warnings from scripts/checkpatch -f Signed-off-by: Dean Anderson Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/s2255/s2255drv.c | 333 +++++++++++++++++-------------------- 1 file changed, 151 insertions(+), 182 deletions(-) diff --git a/drivers/media/usb/s2255/s2255drv.c b/drivers/media/usb/s2255/s2255drv.c index 6bc9b8e..c6bdccc 100644 --- a/drivers/media/usb/s2255/s2255drv.c +++ b/drivers/media/usb/s2255/s2255drv.c @@ -218,6 +218,7 @@ struct s2255_fmt; /*forward declaration */ struct s2255_dev; struct s2255_channel { + struct s2255_dev *dev; struct video_device vdev; struct v4l2_ctrl_handler hdl; struct v4l2_ctrl *jpegqual_ctrl; @@ -259,7 +260,7 @@ struct s2255_channel { struct s2255_dev { struct s2255_channel channel[MAX_CHANNELS]; - struct v4l2_device v4l2_dev; + struct v4l2_device v4l2_dev; atomic_t num_channels; int frames; struct mutex lock; /* channels[].vdev.lock */ @@ -352,7 +353,6 @@ struct s2255_fh { static unsigned long G_chnmap[MAX_CHANNELS] = {3, 2, 1, 0}; static int debug; -static int *s2255_debug = &debug; static int s2255_start_readpipe(struct s2255_dev *dev); static void s2255_stop_readpipe(struct s2255_dev *dev); @@ -373,13 +373,8 @@ static long s2255_vendor_req(struct s2255_dev *dev, unsigned char req, #define s2255_dev_err(dev, fmt, arg...) \ dev_err(dev, S2255_DRIVER_NAME " - " fmt, ##arg) -#define dprintk(level, fmt, arg...) \ - do { \ - if (*s2255_debug >= (level)) { \ - printk(KERN_DEBUG S2255_DRIVER_NAME \ - ": " fmt, ##arg); \ - } \ - } while (0) +#define dprintk(dev, level, fmt, arg...) \ + v4l2_dbg(level, debug, &dev->v4l2_dev, fmt, ## arg) static struct usb_driver s2255_driver; @@ -498,7 +493,7 @@ static void planar422p_to_yuv_packed(const unsigned char *in, static void s2255_reset_dsppower(struct s2255_dev *dev) { s2255_vendor_req(dev, 0x40, 0x0000, 0x0001, NULL, 0, 1); - msleep(10); + msleep(20); s2255_vendor_req(dev, 0x50, 0x0000, 0x0000, NULL, 0, 1); msleep(600); s2255_vendor_req(dev, 0x10, 0x0000, 0x0000, NULL, 0, 1); @@ -510,9 +505,8 @@ static void s2255_reset_dsppower(struct s2255_dev *dev) static void s2255_timer(unsigned long user_data) { struct s2255_fw *data = (struct s2255_fw *)user_data; - dprintk(100, "%s\n", __func__); if (usb_submit_urb(data->fw_urb, GFP_ATOMIC) < 0) { - printk(KERN_ERR "s2255: can't submit urb\n"); + pr_err("s2255: can't submit urb\n"); atomic_set(&data->fw_state, S2255_FW_FAILED); /* wake up anything waiting for the firmware */ wake_up(&data->wait_fw); @@ -532,7 +526,6 @@ static void s2255_fwchunk_complete(struct urb *urb) struct s2255_fw *data = urb->context; struct usb_device *udev = urb->dev; int len; - dprintk(100, "%s: udev %p urb %p", __func__, udev, urb); if (urb->status) { dev_err(&udev->dev, "URB failed with status %d\n", urb->status); atomic_set(&data->fw_state, S2255_FW_FAILED); @@ -559,9 +552,6 @@ static void s2255_fwchunk_complete(struct urb *urb) if (len < CHUNK_SIZE) memset(data->pfw_data, 0, CHUNK_SIZE); - dprintk(100, "completed len %d, loaded %d \n", len, - data->fw_loaded); - memcpy(data->pfw_data, (char *) data->fw->data + data->fw_loaded, len); @@ -576,10 +566,8 @@ static void s2255_fwchunk_complete(struct urb *urb) return; } data->fw_loaded += len; - } else { + } else atomic_set(&data->fw_state, S2255_FW_LOADED_DSPWAIT); - dprintk(100, "%s: firmware upload complete\n", __func__); - } return; } @@ -593,7 +581,7 @@ static int s2255_got_frame(struct s2255_channel *channel, int jpgsize) int rc = 0; spin_lock_irqsave(&dev->slock, flags); if (list_empty(&dma_q->active)) { - dprintk(1, "No active queue to serve\n"); + dprintk(dev, 1, "No active queue to serve\n"); rc = -1; goto unlock; } @@ -603,7 +591,7 @@ static int s2255_got_frame(struct s2255_channel *channel, int jpgsize) v4l2_get_timestamp(&buf->vb.ts); s2255_fillbuff(channel, buf, jpgsize); wake_up(&buf->vb.done); - dprintk(2, "%s: [buf/i] [%p/%d]\n", __func__, buf, buf->vb.i); + dprintk(dev, 2, "%s: [buf/i] [%p/%d]\n", __func__, buf, buf->vb.i); unlock: spin_unlock_irqrestore(&dev->slock, flags); return rc; @@ -615,9 +603,9 @@ static const struct s2255_fmt *format_by_fourcc(int fourcc) for (i = 0; i < ARRAY_SIZE(formats); i++) { if (-1 == formats[i].fourcc) continue; - if (!jpeg_enable && ((formats[i].fourcc == V4L2_PIX_FMT_JPEG) || - (formats[i].fourcc == V4L2_PIX_FMT_MJPEG))) - continue; + if (!jpeg_enable && ((formats[i].fourcc == V4L2_PIX_FMT_JPEG) || + (formats[i].fourcc == V4L2_PIX_FMT_MJPEG))) + continue; if (formats[i].fourcc == fourcc) return formats + i; } @@ -639,6 +627,7 @@ static void s2255_fillbuff(struct s2255_channel *channel, const char *tmpbuf; char *vbuf = videobuf_to_vmalloc(&buf->vb); unsigned long last_frame; + struct s2255_dev *dev = channel->dev; if (!vbuf) return; @@ -667,18 +656,16 @@ static void s2255_fillbuff(struct s2255_channel *channel, buf->vb.width * buf->vb.height * 2); break; default: - printk(KERN_DEBUG "s2255: unknown format?\n"); + pr_info("s2255: unknown format?\n"); } channel->last_frame = -1; } else { - printk(KERN_ERR "s2255: =======no frame\n"); + pr_err("s2255: =======no frame\n"); return; - } - dprintk(2, "s2255fill at : Buffer 0x%08lx size= %d\n", + dprintk(dev, 2, "s2255fill at : Buffer 0x%08lx size= %d\n", (unsigned long)vbuf, pos); /* tell v4l buffer was filled */ - buf->vb.field_count = channel->frame_count * 2; v4l2_get_timestamp(&buf->vb.ts); buf->vb.state = VIDEOBUF_DONE; @@ -707,8 +694,6 @@ static int buffer_setup(struct videobuf_queue *vq, unsigned int *count, static void free_buffer(struct videobuf_queue *vq, struct s2255_buffer *buf) { - dprintk(4, "%s\n", __func__); - videobuf_vmalloc_free(&buf->vb); buf->vb.state = VIDEOBUF_NEEDS_INIT; } @@ -722,7 +707,7 @@ static int buffer_prepare(struct videobuf_queue *vq, struct videobuf_buffer *vb, int rc; int w = channel->width; int h = channel->height; - dprintk(4, "%s, field=%d\n", __func__, field); + dprintk(fh->dev, 4, "%s, field=%d\n", __func__, field); if (channel->fmt == NULL) return -EINVAL; @@ -730,12 +715,12 @@ static int buffer_prepare(struct videobuf_queue *vq, struct videobuf_buffer *vb, (w > norm_maxw(channel)) || (h < norm_minh(channel)) || (h > norm_maxh(channel))) { - dprintk(4, "invalid buffer prepare\n"); + dprintk(fh->dev, 4, "invalid buffer prepare\n"); return -EINVAL; } buf->vb.size = w * h * (channel->fmt->depth >> 3); if (0 != buf->vb.baddr && buf->vb.bsize < buf->vb.size) { - dprintk(4, "invalid buffer prepare\n"); + dprintk(fh->dev, 4, "invalid buffer prepare\n"); return -EINVAL; } @@ -763,7 +748,7 @@ static void buffer_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb) struct s2255_fh *fh = vq->priv_data; struct s2255_channel *channel = fh->channel; struct s2255_dmaqueue *vidq = &channel->vidq; - dprintk(1, "%s\n", __func__); + dprintk(fh->dev, 1, "%s\n", __func__); buf->vb.state = VIDEOBUF_QUEUED; list_add_tail(&buf->vb.queue, &vidq->active); } @@ -773,7 +758,7 @@ static void buffer_release(struct videobuf_queue *vq, { struct s2255_buffer *buf = container_of(vb, struct s2255_buffer, vb); struct s2255_fh *fh = vq->priv_data; - dprintk(4, "%s %d\n", __func__, fh->channel->idx); + dprintk(fh->dev, 4, "%s %d\n", __func__, fh->channel->idx); free_buffer(vq, buf); } @@ -794,7 +779,7 @@ static int res_get(struct s2255_fh *fh) /* it's free, grab it */ channel->resources = 1; fh->resources = 1; - dprintk(1, "s2255: res: get\n"); + dprintk(fh->dev, 1, "s2255: res: get\n"); return 1; } @@ -814,7 +799,6 @@ static void res_free(struct s2255_fh *fh) struct s2255_channel *channel = fh->channel; channel->resources = 0; fh->resources = 0; - dprintk(1, "res: put\n"); } static int vidioc_querycap(struct file *file, void *priv, @@ -841,7 +825,6 @@ static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv, if (!jpeg_enable && ((formats[index].fourcc == V4L2_PIX_FMT_JPEG) || (formats[index].fourcc == V4L2_PIX_FMT_MJPEG))) return -EINVAL; - dprintk(4, "name %s\n", formats[index].name); strlcpy(f->description, formats[index].name, sizeof(f->description)); f->pixelformat = formats[index].fourcc; return 0; @@ -885,7 +868,7 @@ static int vidioc_try_fmt_vid_cap(struct file *file, void *priv, field = f->fmt.pix.field; - dprintk(50, "%s NTSC: %d suggested width: %d, height: %d\n", + dprintk(fh->dev, 50, "%s NTSC: %d suggested width: %d, height: %d\n", __func__, is_ntsc, f->fmt.pix.width, f->fmt.pix.height); if (is_ntsc) { /* NTSC */ @@ -927,7 +910,7 @@ static int vidioc_try_fmt_vid_cap(struct file *file, void *priv, f->fmt.pix.sizeimage = f->fmt.pix.height * f->fmt.pix.bytesperline; f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M; f->fmt.pix.priv = 0; - dprintk(50, "%s: set width %d height %d field %d\n", __func__, + dprintk(fh->dev, 50, "%s: set width %d height %d field %d\n", __func__, f->fmt.pix.width, f->fmt.pix.height, f->fmt.pix.field); return 0; } @@ -955,13 +938,13 @@ static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, mutex_lock(&q->vb_lock); if (videobuf_queue_is_busy(&fh->vb_vidq)) { - dprintk(1, "queue busy\n"); + dprintk(fh->dev, 1, "queue busy\n"); ret = -EBUSY; goto out_s_fmt; } if (res_locked(fh)) { - dprintk(1, "%s: channel busy\n", __func__); + dprintk(fh->dev, 1, "%s: channel busy\n", __func__); ret = -EBUSY; goto out_s_fmt; } @@ -1160,7 +1143,7 @@ static int s2255_set_mode(struct s2255_channel *channel, int i; chn_rev = G_chnmap[channel->idx]; - dprintk(3, "%s channel: %d\n", __func__, channel->idx); + dprintk(dev, 3, "%s channel: %d\n", __func__, channel->idx); /* if JPEG, set the quality */ if ((mode->color & MASK_COLOR) == COLOR_JPG) { mode->color &= ~MASK_COLOR; @@ -1171,7 +1154,7 @@ static int s2255_set_mode(struct s2255_channel *channel, /* save the mode */ channel->mode = *mode; channel->req_image_size = get_transfer_size(mode); - dprintk(1, "%s: reqsize %ld\n", __func__, channel->req_image_size); + dprintk(dev, 1, "%s: reqsize %ld\n", __func__, channel->req_image_size); buffer = kzalloc(512, GFP_KERNEL); if (buffer == NULL) { dev_err(&dev->udev->dev, "out of mem\n"); @@ -1194,13 +1177,13 @@ static int s2255_set_mode(struct s2255_channel *channel, (channel->setmode_ready != 0), msecs_to_jiffies(S2255_SETMODE_TIMEOUT)); if (channel->setmode_ready != 1) { - printk(KERN_DEBUG "s2255: no set mode response\n"); + dprintk(dev, 0, "s2255: no set mode response\n"); res = -EFAULT; } } /* clear the restart flag */ channel->mode.restart = 0; - dprintk(1, "%s chn %d, result: %d\n", __func__, channel->idx, res); + dprintk(dev, 1, "%s chn %d, result: %d\n", __func__, channel->idx, res); return res; } @@ -1211,7 +1194,7 @@ static int s2255_cmd_status(struct s2255_channel *channel, u32 *pstatus) u32 chn_rev; struct s2255_dev *dev = to_s2255_dev(channel->vdev.v4l2_dev); chn_rev = G_chnmap[channel->idx]; - dprintk(4, "%s chan %d\n", __func__, channel->idx); + dprintk(dev, 4, "%s chan %d\n", __func__, channel->idx); buffer = kzalloc(512, GFP_KERNEL); if (buffer == NULL) { dev_err(&dev->udev->dev, "out of mem\n"); @@ -1229,11 +1212,11 @@ static int s2255_cmd_status(struct s2255_channel *channel, u32 *pstatus) (channel->vidstatus_ready != 0), msecs_to_jiffies(S2255_VIDSTATUS_TIMEOUT)); if (channel->vidstatus_ready != 1) { - printk(KERN_DEBUG "s2255: no vidstatus response\n"); + dprintk(dev, 0, "s2255: no vidstatus response\n"); res = -EFAULT; } *pstatus = channel->vidstatus; - dprintk(4, "%s, vid status %d\n", __func__, *pstatus); + dprintk(dev, 4, "%s, vid status %d\n", __func__, *pstatus); return res; } @@ -1244,7 +1227,7 @@ static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i) struct s2255_dev *dev = fh->dev; struct s2255_channel *channel = fh->channel; int j; - dprintk(4, "%s\n", __func__); + dprintk(dev, 4, "%s\n", __func__); if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) { dev_err(&dev->udev->dev, "invalid fh type0\n"); return -EINVAL; @@ -1279,15 +1262,13 @@ static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i) static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i) { struct s2255_fh *fh = priv; - dprintk(4, "%s\n, channel: %d", __func__, fh->channel->idx); + dprintk(fh->dev, 4, "%s\n, channel: %d", __func__, fh->channel->idx); if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) { - printk(KERN_ERR "invalid fh type0\n"); + dprintk(fh->dev, 1, "invalid fh type0\n"); return -EINVAL; } - if (i != fh->type) { - printk(KERN_ERR "invalid type i\n"); + if (i != fh->type) return -EINVAL; - } s2255_stop_acquire(fh->channel); videobuf_streamoff(&fh->vb_vidq); res_free(fh); @@ -1304,13 +1285,13 @@ static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id i) mutex_lock(&q->vb_lock); if (res_locked(fh)) { - dprintk(1, "can't change standard after started\n"); + dprintk(fh->dev, 1, "can't change standard after started\n"); ret = -EBUSY; goto out_s_std; } mode = fh->channel->mode; if (i & V4L2_STD_525_60) { - dprintk(4, "%s 60 Hz\n", __func__); + dprintk(fh->dev, 4, "%s 60 Hz\n", __func__); /* if changing format, reset frame decimation/intervals */ if (mode.format != FORMAT_NTSC) { mode.restart = 1; @@ -1320,7 +1301,7 @@ static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id i) channel->height = NUM_LINES_4CIFS_NTSC * 2; } } else if (i & V4L2_STD_625_50) { - dprintk(4, "%s 50 Hz\n", __func__); + dprintk(fh->dev, 4, "%s 50 Hz\n", __func__); if (mode.format != FORMAT_PAL) { mode.restart = 1; mode.format = FORMAT_PAL; @@ -1370,7 +1351,8 @@ static int vidioc_enum_input(struct file *file, void *priv, if (dev->dsp_fw_ver >= S2255_MIN_DSP_STATUS) { int rc; rc = s2255_cmd_status(fh->channel, &status); - dprintk(4, "s2255_cmd_status rc: %d status %x\n", rc, status); + dprintk(dev, 4, "s2255_cmd_status rc: %d status %x\n", + rc, status); if (rc == 0) inp->status = (status & 0x01) ? 0 : V4L2_IN_ST_NO_SIGNAL; @@ -1405,10 +1387,7 @@ static int s2255_s_ctrl(struct v4l2_ctrl *ctrl) struct s2255_channel *channel = container_of(ctrl->handler, struct s2255_channel, hdl); struct s2255_mode mode; - mode = channel->mode; - dprintk(4, "%s\n", __func__); - /* update the mode to the corresponding value */ switch (ctrl->id) { case V4L2_CID_BRIGHTNESS: @@ -1450,7 +1429,7 @@ static int vidioc_g_jpegcomp(struct file *file, void *priv, memset(jc, 0, sizeof(*jc)); jc->quality = channel->jpegqual; - dprintk(2, "%s: quality %d\n", __func__, jc->quality); + dprintk(fh->dev, 2, "%s: quality %d\n", __func__, jc->quality); return 0; } @@ -1462,7 +1441,7 @@ static int vidioc_s_jpegcomp(struct file *file, void *priv, if (jc->quality < 0 || jc->quality > 100) return -EINVAL; v4l2_ctrl_s_ctrl(channel->jpegqual_ctrl, jc->quality); - dprintk(2, "%s: quality %d\n", __func__, jc->quality); + dprintk(fh->dev, 2, "%s: quality %d\n", __func__, jc->quality); return 0; } @@ -1494,7 +1473,8 @@ static int vidioc_g_parm(struct file *file, void *priv, sp->parm.capture.timeperframe.numerator = def_num * 5; break; } - dprintk(4, "%s capture mode, %d timeperframe %d/%d\n", __func__, + dprintk(fh->dev, 4, "%s capture mode, %d timeperframe %d/%d\n", + __func__, sp->parm.capture.capturemode, sp->parm.capture.timeperframe.numerator, sp->parm.capture.timeperframe.denominator); @@ -1535,7 +1515,7 @@ static int vidioc_s_parm(struct file *file, void *priv, mode.fdec = fdec; sp->parm.capture.timeperframe.denominator = def_dem; s2255_set_mode(channel, &mode); - dprintk(4, "%s capture mode, %d timeperframe %d/%d, fdec %d\n", + dprintk(fh->dev, 4, "%s capture mode, %d timeperframe %d/%d, fdec %d\n", __func__, sp->parm.capture.capturemode, sp->parm.capture.timeperframe.numerator, @@ -1604,7 +1584,8 @@ static int vidioc_enum_frameintervals(struct file *file, void *priv, fe->type = V4L2_FRMIVAL_TYPE_DISCRETE; fe->discrete.denominator = is_ntsc ? 30000 : 25000; fe->discrete.numerator = (is_ntsc ? 1001 : 1000) * frm_dec[fe->index]; - dprintk(4, "%s discrete %d/%d\n", __func__, fe->discrete.numerator, + dprintk(fh->dev, 4, "%s discrete %d/%d\n", __func__, + fe->discrete.numerator, fe->discrete.denominator); return 0; } @@ -1617,7 +1598,7 @@ static int __s2255_open(struct file *file) struct s2255_fh *fh; enum v4l2_buf_type type = V4L2_BUF_TYPE_VIDEO_CAPTURE; int state; - dprintk(1, "s2255: open called (dev=%s)\n", + dprintk(dev, 1, "s2255: open called (dev=%s)\n", video_device_node_name(vdev)); state = atomic_read(&dev->fw_data->fw_state); switch (state) { @@ -1640,7 +1621,7 @@ static int __s2255_open(struct file *file) case S2255_FW_LOADED_DSPWAIT: /* give S2255_LOAD_TIMEOUT time for firmware to load in case driver loaded and then device immediately opened */ - printk(KERN_INFO "%s waiting for firmware load\n", __func__); + pr_info("%s waiting for firmware load\n", __func__); wait_event_timeout(dev->fw_data->wait_fw, ((atomic_read(&dev->fw_data->fw_state) == S2255_FW_SUCCESS) || @@ -1659,16 +1640,15 @@ static int __s2255_open(struct file *file) case S2255_FW_SUCCESS: break; case S2255_FW_FAILED: - printk(KERN_INFO "2255 firmware load failed.\n"); + pr_info("2255 firmware load failed.\n"); return -ENODEV; case S2255_FW_DISCONNECTING: - printk(KERN_INFO "%s: disconnecting\n", __func__); + pr_info("%s: disconnecting\n", __func__); return -ENODEV; case S2255_FW_LOADED_DSPWAIT: case S2255_FW_NOTLOADED: - printk(KERN_INFO "%s: firmware not loaded yet" - "please try again later\n", - __func__); + pr_info("%s: firmware not loaded, please retry\n", + __func__); /* * Timeout on firmware load means device unusable. * Set firmware failure state. @@ -1678,7 +1658,7 @@ static int __s2255_open(struct file *file) S2255_FW_FAILED); return -EAGAIN; default: - printk(KERN_INFO "%s: unknown state\n", __func__); + pr_info("%s: unknown state\n", __func__); return -EFAULT; } /* allocate + initialize per filehandle data */ @@ -1697,12 +1677,12 @@ static int __s2255_open(struct file *file) s2255_set_mode(channel, &channel->mode); channel->configured = 1; } - dprintk(1, "%s: dev=%s type=%s\n", __func__, + dprintk(dev, 1, "%s: dev=%s type=%s\n", __func__, video_device_node_name(vdev), v4l2_type_names[type]); - dprintk(2, "%s: fh=0x%08lx, dev=0x%08lx, vidq=0x%08lx\n", __func__, + dprintk(dev, 2, "%s: fh=0x%08lx, dev=0x%08lx, vidq=0x%08lx\n", __func__, (unsigned long)fh, (unsigned long)dev, (unsigned long)&channel->vidq); - dprintk(4, "%s: list_empty active=%d\n", __func__, + dprintk(dev, 4, "%s: list_empty active=%d\n", __func__, list_empty(&channel->vidq.active)); videobuf_queue_vmalloc_init(&fh->vb_vidq, &s2255_video_qops, NULL, &dev->slock, @@ -1732,7 +1712,7 @@ static unsigned int s2255_poll(struct file *file, struct s2255_dev *dev = fh->dev; int rc = v4l2_ctrl_poll(file, wait); - dprintk(100, "%s\n", __func__); + dprintk(dev, 100, "%s\n", __func__); if (V4L2_BUF_TYPE_VIDEO_CAPTURE != fh->type) return POLLERR; mutex_lock(&dev->lock); @@ -1743,6 +1723,7 @@ static unsigned int s2255_poll(struct file *file, static void s2255_destroy(struct s2255_dev *dev) { + dprintk(dev, 1, "%s", __func__); /* board shutdown stops the read pipe if it is running */ s2255_board_shutdown(dev); /* make sure firmware still not trying to load */ @@ -1760,7 +1741,6 @@ static void s2255_destroy(struct s2255_dev *dev) mutex_destroy(&dev->lock); usb_put_dev(dev->udev); v4l2_device_unregister(&dev->v4l2_dev); - dprintk(1, "%s", __func__); kfree(dev); } @@ -1782,7 +1762,7 @@ static int s2255_release(struct file *file) } videobuf_mmap_free(&fh->vb_vidq); mutex_unlock(&dev->lock); - dprintk(1, "%s (dev=%s)\n", __func__, video_device_node_name(vdev)); + dprintk(dev, 1, "%s[%s]\n", __func__, video_device_node_name(vdev)); v4l2_fh_del(&fh->fh); v4l2_fh_exit(&fh->fh); kfree(fh); @@ -1794,16 +1774,15 @@ static int s2255_mmap_v4l(struct file *file, struct vm_area_struct *vma) struct s2255_fh *fh = file->private_data; struct s2255_dev *dev; int ret; - if (!fh) return -ENODEV; dev = fh->dev; - dprintk(4, "%s, vma=0x%08lx\n", __func__, (unsigned long)vma); + dprintk(dev, 4, "%s, vma=0x%08lx\n", __func__, (unsigned long)vma); if (mutex_lock_interruptible(&dev->lock)) return -ERESTARTSYS; ret = videobuf_mmap_mapper(&fh->vb_vidq, vma); mutex_unlock(&dev->lock); - dprintk(4, "%s vma start=0x%08lx, size=%ld, ret=%d\n", __func__, + dprintk(dev, 4, "%s vma start=0x%08lx, size=%ld, ret=%d\n", __func__, (unsigned long)vma->vm_start, (unsigned long)vma->vm_end - (unsigned long)vma->vm_start, ret); return ret; @@ -1852,10 +1831,11 @@ static void s2255_video_device_release(struct video_device *vdev) struct s2255_channel *channel = container_of(vdev, struct s2255_channel, vdev); - v4l2_ctrl_handler_free(&channel->hdl); - dprintk(4, "%s, chnls: %d\n", __func__, + dprintk(dev, 4, "%s, chnls: %d\n", __func__, atomic_read(&dev->num_channels)); + v4l2_ctrl_handler_free(&channel->hdl); + if (atomic_dec_and_test(&dev->num_channels)) s2255_destroy(dev); return; @@ -1913,7 +1893,8 @@ static int s2255_probe_v4l(struct s2255_dev *dev) 0, 100, 1, S2255_DEF_JPEG_QUAL); if (dev->dsp_fw_ver >= S2255_MIN_DSP_COLORFILTER && (dev->pid != 0x2257 || channel->idx <= 1)) - v4l2_ctrl_new_custom(&channel->hdl, &color_filter_ctrl, NULL); + v4l2_ctrl_new_custom(&channel->hdl, &color_filter_ctrl, + NULL); if (channel->hdl.error) { ret = channel->hdl.error; v4l2_ctrl_handler_free(&channel->hdl); @@ -1947,15 +1928,15 @@ static int s2255_probe_v4l(struct s2255_dev *dev) video_device_node_name(&channel->vdev)); } - printk(KERN_INFO "Sensoray 2255 V4L driver Revision: %s\n", - S2255_VERSION); + pr_info("Sensoray 2255 V4L driver Revision: %s\n", + S2255_VERSION); /* if no channels registered, return error and probe will fail*/ if (atomic_read(&dev->num_channels) == 0) { v4l2_device_unregister(&dev->v4l2_dev); return ret; } if (atomic_read(&dev->num_channels) != MAX_CHANNELS) - printk(KERN_WARNING "s2255: Not all channels available.\n"); + pr_warn("s2255: Not all channels available.\n"); return 0; } @@ -1981,11 +1962,11 @@ static int save_frame(struct s2255_dev *dev, struct s2255_pipeinfo *pipe_info) s32 idx = -1; struct s2255_framei *frm; unsigned char *pdata; - struct s2255_channel *channel; - dprintk(100, "buffer to user\n"); - channel = &dev->channel[dev->cc]; - idx = channel->cur_frame; - frm = &channel->buffer.frame[idx]; + struct s2255_channel *ch; + dprintk(dev, 100, "buffer to user\n"); + ch = &dev->channel[dev->cc]; + idx = ch->cur_frame; + frm = &ch->buffer.frame[idx]; if (frm->ulState == S2255_READ_IDLE) { int jj; unsigned int cc; @@ -1997,28 +1978,27 @@ static int save_frame(struct s2255_dev *dev, struct s2255_pipeinfo *pipe_info) for (jj = 0; jj < (pipe_info->cur_transfer_size - 12); jj++) { switch (*pdword) { case S2255_MARKER_FRAME: - dprintk(4, "found frame marker at offset:" - " %d [%x %x]\n", jj, pdata[0], - pdata[1]); + dprintk(dev, 4, "marker @ offset: %d [%x %x]\n", + jj, pdata[0], pdata[1]); offset = jj + PREFIX_SIZE; bframe = 1; cc = le32_to_cpu(pdword[1]); if (cc >= MAX_CHANNELS) { - printk(KERN_ERR - "bad channel\n"); + dprintk(dev, 0, + "bad channel\n"); return -EINVAL; } /* reverse it */ dev->cc = G_chnmap[cc]; - channel = &dev->channel[dev->cc]; + ch = &dev->channel[dev->cc]; payload = le32_to_cpu(pdword[3]); - if (payload > channel->req_image_size) { - channel->bad_payload++; + if (payload > ch->req_image_size) { + ch->bad_payload++; /* discard the bad frame */ return -EINVAL; } - channel->pkt_size = payload; - channel->jpg_size = le32_to_cpu(pdword[4]); + ch->pkt_size = payload; + ch->jpg_size = le32_to_cpu(pdword[4]); break; case S2255_MARKER_RESPONSE: @@ -2029,34 +2009,34 @@ static int save_frame(struct s2255_dev *dev, struct s2255_pipeinfo *pipe_info) cc = G_chnmap[le32_to_cpu(pdword[1])]; if (cc >= MAX_CHANNELS) break; - channel = &dev->channel[cc]; + ch = &dev->channel[cc]; switch (pdword[2]) { case S2255_RESPONSE_SETMODE: /* check if channel valid */ /* set mode ready */ - channel->setmode_ready = 1; - wake_up(&channel->wait_setmode); - dprintk(5, "setmode ready %d\n", cc); + ch->setmode_ready = 1; + wake_up(&ch->wait_setmode); + dprintk(dev, 5, "setmode rdy %d\n", cc); break; case S2255_RESPONSE_FW: dev->chn_ready |= (1 << cc); if ((dev->chn_ready & 0x0f) != 0x0f) break; /* all channels ready */ - printk(KERN_INFO "s2255: fw loaded\n"); + pr_info("s2255: fw loaded\n"); atomic_set(&dev->fw_data->fw_state, S2255_FW_SUCCESS); wake_up(&dev->fw_data->wait_fw); break; case S2255_RESPONSE_STATUS: - channel->vidstatus = le32_to_cpu(pdword[3]); - channel->vidstatus_ready = 1; - wake_up(&channel->wait_vidstatus); - dprintk(5, "got vidstatus %x chan %d\n", + ch->vidstatus = le32_to_cpu(pdword[3]); + ch->vidstatus_ready = 1; + wake_up(&ch->wait_vidstatus); + dprintk(dev, 5, "vstat %x chan %d\n", le32_to_cpu(pdword[3]), cc); break; default: - printk(KERN_INFO "s2255 unknown resp\n"); + pr_info("s2255 unknown resp\n"); } default: pdata++; @@ -2068,11 +2048,11 @@ static int save_frame(struct s2255_dev *dev, struct s2255_pipeinfo *pipe_info) if (!bframe) return -EINVAL; } - channel = &dev->channel[dev->cc]; - idx = channel->cur_frame; - frm = &channel->buffer.frame[idx]; + ch = &dev->channel[dev->cc]; + idx = ch->cur_frame; + frm = &ch->buffer.frame[idx]; /* search done. now find out if should be acquiring on this channel */ - if (!channel->b_acquire) { + if (!ch->b_acquire) { /* we found a frame, but this channel is turned off */ frm->ulState = S2255_READ_IDLE; return -EINVAL; @@ -2088,7 +2068,7 @@ static int save_frame(struct s2255_dev *dev, struct s2255_pipeinfo *pipe_info) if (frm->lpvbits == NULL) { - dprintk(1, "s2255 frame buffer == NULL.%p %p %d %d", + dprintk(dev, 1, "s2255 frame buffer == NULL.%p %p %d %d", frm, dev, dev->cc, idx); return -ENOMEM; } @@ -2097,28 +2077,28 @@ static int save_frame(struct s2255_dev *dev, struct s2255_pipeinfo *pipe_info) copy_size = (pipe_info->cur_transfer_size - offset); - size = channel->pkt_size - PREFIX_SIZE; + size = ch->pkt_size - PREFIX_SIZE; /* sanity check on pdest */ - if ((copy_size + frm->cur_size) < channel->req_image_size) + if ((copy_size + frm->cur_size) < ch->req_image_size) memcpy(pdest, psrc, copy_size); frm->cur_size += copy_size; - dprintk(4, "cur_size size %lu size %lu \n", frm->cur_size, size); + dprintk(dev, 4, "cur_size: %lu, size: %lu\n", frm->cur_size, size); if (frm->cur_size >= size) { - dprintk(2, "****************[%d]Buffer[%d]full*************\n", + dprintk(dev, 2, "******[%d]Buffer[%d]full*******\n", dev->cc, idx); - channel->last_frame = channel->cur_frame; - channel->cur_frame++; + ch->last_frame = ch->cur_frame; + ch->cur_frame++; /* end of system frame ring buffer, start at zero */ - if ((channel->cur_frame == SYS_FRAMES) || - (channel->cur_frame == channel->buffer.dwFrames)) - channel->cur_frame = 0; + if ((ch->cur_frame == SYS_FRAMES) || + (ch->cur_frame == ch->buffer.dwFrames)) + ch->cur_frame = 0; /* frame ready */ - if (channel->b_acquire) - s2255_got_frame(channel, channel->jpg_size); - channel->frame_count++; + if (ch->b_acquire) + s2255_got_frame(ch, ch->jpg_size); + ch->frame_count++; frm->ulState = S2255_READ_IDLE; frm->cur_size = 0; @@ -2131,7 +2111,7 @@ static void s2255_read_video_callback(struct s2255_dev *dev, struct s2255_pipeinfo *pipe_info) { int res; - dprintk(50, "callback read video \n"); + dprintk(dev, 50, "callback read video\n"); if (dev->cc >= MAX_CHANNELS) { dev->cc = 0; @@ -2141,9 +2121,9 @@ static void s2255_read_video_callback(struct s2255_dev *dev, /* otherwise copy to the system buffers */ res = save_frame(dev, pipe_info); if (res != 0) - dprintk(4, "s2255: read callback failed\n"); + dprintk(dev, 4, "s2255: read callback failed\n"); - dprintk(50, "callback read video done\n"); + dprintk(dev, 50, "callback read video done\n"); return; } @@ -2181,9 +2161,9 @@ static int s2255_get_fx2fw(struct s2255_dev *dev) ret = s2255_vendor_req(dev, S2255_VR_FW, 0, 0, transBuffer, 2, S2255_VR_IN); if (ret < 0) - dprintk(2, "get fw error: %x\n", ret); + dprintk(dev, 2, "get fw error: %x\n", ret); fw = transBuffer[0] + (transBuffer[1] << 8); - dprintk(2, "Get FW %x %x\n", transBuffer[0], transBuffer[1]); + dprintk(dev, 2, "Get FW %x %x\n", transBuffer[0], transBuffer[1]); return fw; } @@ -2195,7 +2175,6 @@ static int s2255_create_sys_buffers(struct s2255_channel *channel) { unsigned long i; unsigned long reqsize; - dprintk(1, "create sys buffers\n"); channel->buffer.dwFrames = SYS_FRAMES; /* always allocate maximum size(PAL) for system buffers */ reqsize = SYS_FRAMES_MAXSIZE; @@ -2206,12 +2185,9 @@ static int s2255_create_sys_buffers(struct s2255_channel *channel) for (i = 0; i < SYS_FRAMES; i++) { /* allocate the frames */ channel->buffer.frame[i].lpvbits = vmalloc(reqsize); - dprintk(1, "valloc %p chan %d, idx %lu, pdata %p\n", - &channel->buffer.frame[i], channel->idx, i, - channel->buffer.frame[i].lpvbits); channel->buffer.frame[i].size = reqsize; if (channel->buffer.frame[i].lpvbits == NULL) { - printk(KERN_INFO "out of memory. using less frames\n"); + pr_info("out of memory. using less frames\n"); channel->buffer.dwFrames = i; break; } @@ -2231,13 +2207,9 @@ static int s2255_create_sys_buffers(struct s2255_channel *channel) static int s2255_release_sys_buffers(struct s2255_channel *channel) { unsigned long i; - dprintk(1, "release sys buffers\n"); for (i = 0; i < SYS_FRAMES; i++) { - if (channel->buffer.frame[i].lpvbits) { - dprintk(1, "vfree %p\n", - channel->buffer.frame[i].lpvbits); + if (channel->buffer.frame[i].lpvbits) vfree(channel->buffer.frame[i].lpvbits); - } channel->buffer.frame[i].lpvbits = NULL; } return 0; @@ -2249,7 +2221,7 @@ static int s2255_board_init(struct s2255_dev *dev) int fw_ver; int j; struct s2255_pipeinfo *pipe = &dev->pipe; - dprintk(4, "board init: %p", dev); + dprintk(dev, 4, "board init: %p", dev); memset(pipe, 0, sizeof(*pipe)); pipe->dev = dev; pipe->cur_transfer_size = S2255_USB_XFER_SIZE; @@ -2258,18 +2230,18 @@ static int s2255_board_init(struct s2255_dev *dev) pipe->transfer_buffer = kzalloc(pipe->max_transfer_size, GFP_KERNEL); if (pipe->transfer_buffer == NULL) { - dprintk(1, "out of memory!\n"); + dprintk(dev, 1, "out of memory!\n"); return -ENOMEM; } /* query the firmware */ fw_ver = s2255_get_fx2fw(dev); - printk(KERN_INFO "s2255: usb firmware version %d.%d\n", - (fw_ver >> 8) & 0xff, - fw_ver & 0xff); + pr_info("s2255: usb firmware version %d.%d\n", + (fw_ver >> 8) & 0xff, + fw_ver & 0xff); if (fw_ver < S2255_CUR_USB_FWVER) - printk(KERN_INFO "s2255: newer USB firmware available\n"); + pr_info("s2255: newer USB firmware available\n"); for (j = 0; j < MAX_CHANNELS; j++) { struct s2255_channel *channel = &dev->channel[j]; @@ -2290,14 +2262,14 @@ static int s2255_board_init(struct s2255_dev *dev) } /* start read pipe */ s2255_start_readpipe(dev); - dprintk(1, "%s: success\n", __func__); + dprintk(dev, 1, "%s: success\n", __func__); return 0; } static int s2255_board_shutdown(struct s2255_dev *dev) { u32 i; - dprintk(1, "%s: dev: %p", __func__, dev); + dprintk(dev, 1, "%s: dev: %p", __func__, dev); for (i = 0; i < MAX_CHANNELS; i++) { if (dev->channel[i].b_acquire) @@ -2318,13 +2290,10 @@ static void read_pipe_completion(struct urb *purb) int status; int pipe; pipe_info = purb->context; - dprintk(100, "%s: urb:%p, status %d\n", __func__, purb, - purb->status); if (pipe_info == NULL) { dev_err(&purb->dev->dev, "no context!\n"); return; } - dev = pipe_info->dev; if (dev == NULL) { dev_err(&purb->dev->dev, "no context!\n"); @@ -2333,13 +2302,13 @@ static void read_pipe_completion(struct urb *purb) status = purb->status; /* if shutting down, do not resubmit, exit immediately */ if (status == -ESHUTDOWN) { - dprintk(2, "%s: err shutdown\n", __func__); + dprintk(dev, 2, "%s: err shutdown\n", __func__); pipe_info->err_count++; return; } if (pipe_info->state == 0) { - dprintk(2, "%s: exiting USB pipe", __func__); + dprintk(dev, 2, "%s: exiting USB pipe", __func__); return; } @@ -2347,7 +2316,7 @@ static void read_pipe_completion(struct urb *purb) s2255_read_video_callback(dev, pipe_info); else { pipe_info->err_count++; - dprintk(1, "%s: failed URB %d\n", __func__, status); + dprintk(dev, 1, "%s: failed URB %d\n", __func__, status); } pipe = usb_rcvbulkpipe(dev->udev, dev->read_endpoint); @@ -2359,11 +2328,10 @@ static void read_pipe_completion(struct urb *purb) read_pipe_completion, pipe_info); if (pipe_info->state != 0) { - if (usb_submit_urb(pipe_info->stream_urb, GFP_ATOMIC)) { + if (usb_submit_urb(pipe_info->stream_urb, GFP_ATOMIC)) dev_err(&dev->udev->dev, "error submitting urb\n"); - } } else { - dprintk(2, "%s :complete state 0\n", __func__); + dprintk(dev, 2, "%s :complete state 0\n", __func__); } return; } @@ -2374,7 +2342,7 @@ static int s2255_start_readpipe(struct s2255_dev *dev) int retval; struct s2255_pipeinfo *pipe_info = &dev->pipe; pipe = usb_rcvbulkpipe(dev->udev, dev->read_endpoint); - dprintk(2, "%s: IN %d\n", __func__, dev->read_endpoint); + dprintk(dev, 2, "%s: IN %d\n", __func__, dev->read_endpoint); pipe_info->state = 1; pipe_info->err_count = 0; pipe_info->stream_urb = usb_alloc_urb(0, GFP_KERNEL); @@ -2391,7 +2359,7 @@ static int s2255_start_readpipe(struct s2255_dev *dev) read_pipe_completion, pipe_info); retval = usb_submit_urb(pipe_info->stream_urb, GFP_KERNEL); if (retval) { - printk(KERN_ERR "s2255: start read pipe failed\n"); + pr_err("s2255: start read pipe failed\n"); return retval; } return 0; @@ -2428,7 +2396,7 @@ static int s2255_start_acquire(struct s2255_channel *channel) if (res != 0) dev_err(&dev->udev->dev, "CMD_START error\n"); - dprintk(2, "start acquire exit[%d] %d \n", channel->idx, res); + dprintk(dev, 2, "start acquire exit[%d] %d\n", channel->idx, res); kfree(buffer); return 0; } @@ -2454,7 +2422,7 @@ static int s2255_stop_acquire(struct s2255_channel *channel) dev_err(&dev->udev->dev, "CMD_STOP error\n"); kfree(buffer); channel->b_acquire = 0; - dprintk(4, "%s: chn %d, res %d\n", __func__, channel->idx, res); + dprintk(dev, 4, "%s: chn %d, res %d\n", __func__, channel->idx, res); return res; } @@ -2469,7 +2437,7 @@ static void s2255_stop_readpipe(struct s2255_dev *dev) usb_free_urb(pipe->stream_urb); pipe->stream_urb = NULL; } - dprintk(4, "%s", __func__); + dprintk(dev, 4, "%s", __func__); return; } @@ -2501,7 +2469,6 @@ static int s2255_probe(struct usb_interface *interface, int retval = -ENOMEM; __le32 *pdata; int fw_size; - dprintk(2, "%s\n", __func__); /* allocate memory for our device state and initialize it to zero */ dev = kzalloc(sizeof(struct s2255_dev), GFP_KERNEL); if (dev == NULL) { @@ -2521,12 +2488,13 @@ static int s2255_probe(struct usb_interface *interface, retval = -ENODEV; goto errorUDEV; } - dprintk(1, "dev: %p, udev %p interface %p\n", dev, - dev->udev, interface); + dev_dbg(&interface->dev, "dev: %p, udev %p interface %p\n", + dev, dev->udev, interface); dev->interface = interface; /* set up the endpoint information */ iface_desc = interface->cur_altsetting; - dprintk(1, "num endpoints %d\n", iface_desc->desc.bNumEndpoints); + dev_dbg(&interface->dev, "num EP: %d\n", + iface_desc->desc.bNumEndpoints); for (i = 0; i < iface_desc->desc.bNumEndpoints; ++i) { endpoint = &iface_desc->endpoint[i].desc; if (!dev->read_endpoint && usb_endpoint_is_bulk_in(endpoint)) { @@ -2545,7 +2513,8 @@ static int s2255_probe(struct usb_interface *interface, init_waitqueue_head(&dev->fw_data->wait_fw); for (i = 0; i < MAX_CHANNELS; i++) { struct s2255_channel *channel = &dev->channel[i]; - dev->channel[i].idx = i; + channel->idx = i; + channel->dev = dev; init_waitqueue_head(&channel->wait_setmode); init_waitqueue_head(&channel->wait_vidstatus); } @@ -2564,7 +2533,7 @@ static int s2255_probe(struct usb_interface *interface, /* load the first chunk */ if (request_firmware(&dev->fw_data->fw, FIRMWARE_FILE_NAME, &dev->udev->dev)) { - printk(KERN_ERR "sensoray 2255 failed to get firmware\n"); + dev_err(&interface->dev, "sensoray 2255 failed to get firmware\n"); goto errorREQFW; } /* check the firmware is valid */ @@ -2572,21 +2541,21 @@ static int s2255_probe(struct usb_interface *interface, pdata = (__le32 *) &dev->fw_data->fw->data[fw_size - 8]; if (*pdata != S2255_FW_MARKER) { - printk(KERN_INFO "Firmware invalid.\n"); + dev_err(&interface->dev, "Firmware invalid.\n"); retval = -ENODEV; goto errorFWMARKER; } else { /* make sure firmware is the latest */ __le32 *pRel; pRel = (__le32 *) &dev->fw_data->fw->data[fw_size - 4]; - printk(KERN_INFO "s2255 dsp fw version %x\n", le32_to_cpu(*pRel)); + pr_info("s2255 dsp fw version %x\n", le32_to_cpu(*pRel)); dev->dsp_fw_ver = le32_to_cpu(*pRel); if (dev->dsp_fw_ver < S2255_CUR_DSP_FWVER) - printk(KERN_INFO "s2255: f2255usb.bin out of date.\n"); + pr_info("s2255: f2255usb.bin out of date.\n"); if (dev->pid == 0x2257 && dev->dsp_fw_ver < S2255_MIN_DSP_COLORFILTER) - printk(KERN_WARNING "s2255: 2257 requires firmware %d" - " or above.\n", S2255_MIN_DSP_COLORFILTER); + pr_warn("2257 needs firmware %d or above.\n", + S2255_MIN_DSP_COLORFILTER); } usb_reset_device(dev->udev); /* load 2255 board specific */ @@ -2618,7 +2587,7 @@ errorUDEV: mutex_destroy(&dev->lock); errorFWDATA1: kfree(dev); - printk(KERN_WARNING "Sensoray 2255 driver load failed: 0x%x\n", retval); + pr_warn("Sensoray 2255 driver load failed: 0x%x\n", retval); return retval; } -- cgit v1.1 From a1d16e0f59506d07935ec0a929a2c9f1d6d96077 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Fri, 31 Jan 2014 10:32:15 -0300 Subject: [media] v4l2-dv-timings.h: add new 4K DMT resolutions VESA added two new DMT timings in their latest standard document. Add these to v4l2-dv-timings.h. Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- include/uapi/linux/v4l2-dv-timings.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/include/uapi/linux/v4l2-dv-timings.h b/include/uapi/linux/v4l2-dv-timings.h index be709fe..b6a5fe0 100644 --- a/include/uapi/linux/v4l2-dv-timings.h +++ b/include/uapi/linux/v4l2-dv-timings.h @@ -823,4 +823,21 @@ V4L2_DV_FL_REDUCED_BLANKING) \ } +/* 4K resolutions */ +#define V4L2_DV_BT_DMT_4096X2160P60_RB { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \ + 556744000, 8, 32, 40, 48, 8, 6, 0, 0, 0, \ + V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ + V4L2_DV_FL_REDUCED_BLANKING) \ +} + +#define V4L2_DV_BT_DMT_4096X2160P59_94_RB { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \ + 556188000, 8, 32, 40, 48, 8, 6, 0, 0, 0, \ + V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ + V4L2_DV_FL_REDUCED_BLANKING) \ +} + #endif -- cgit v1.1 From 3be55e0407a0b0a6cfd5d1238aa4fa33e92ab133 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Fri, 31 Jan 2014 10:32:16 -0300 Subject: [media] v4l2-dv-timings: mention missing 'reduced blanking V2' The VESA standard added a version 2 of the reduced blanking formula. Note in the comment that this is not yet supported by the v4l2_detect_cvt function. Obviously this should be implemented eventually, but for now add this as a reminder. Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/v4l2-core/v4l2-dv-timings.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/media/v4l2-core/v4l2-dv-timings.c b/drivers/media/v4l2-core/v4l2-dv-timings.c index ee52b9f4..41bf3f9 100644 --- a/drivers/media/v4l2-core/v4l2-dv-timings.c +++ b/drivers/media/v4l2-core/v4l2-dv-timings.c @@ -324,6 +324,10 @@ EXPORT_SYMBOL_GPL(v4l2_print_dv_timings); * This function will attempt to detect if the given values correspond to a * valid CVT format. If so, then it will return true, and fmt will be filled * in with the found CVT timings. + * + * TODO: VESA defined a new version 2 of their reduced blanking + * formula. Support for that is currently missing in this CVT + * detection function. */ bool v4l2_detect_cvt(unsigned frame_height, unsigned hfreq, unsigned vsync, u32 polarities, struct v4l2_dv_timings *fmt) -- cgit v1.1 From 7183eeb9dc831f372d7d78b8939f3715042b971e Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Tue, 7 Jan 2014 06:41:16 -0300 Subject: [media] DocBook media: fix email addresses Mauro's old redhat email address is no longer valid, update to the current email address. Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/dvbapi.xml | 2 +- Documentation/DocBook/media/v4l/v4l2.xml | 2 +- Documentation/DocBook/media_api.tmpl | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/Documentation/DocBook/media/dvb/dvbapi.xml b/Documentation/DocBook/media/dvb/dvbapi.xml index 0197bcc..49f46e8 100644 --- a/Documentation/DocBook/media/dvb/dvbapi.xml +++ b/Documentation/DocBook/media/dvb/dvbapi.xml @@ -18,7 +18,7 @@ Mauro Carvalho Chehab -
mchehab@redhat.com
 +
m.chehab@samsung.com
 Ported document to Docbook XML. diff --git a/Documentation/DocBook/media/v4l/v4l2.xml b/Documentation/DocBook/media/v4l/v4l2.xml index 74b7f27..4584841 100644 --- a/Documentation/DocBook/media/v4l/v4l2.xml +++ b/Documentation/DocBook/media/v4l/v4l2.xml @@ -70,7 +70,7 @@ MPEG stream embedded, sliced VBI data format in this specification. Remote Controller chapter.
- mchehab@redhat.com + m.chehab@samsung.com
diff --git a/Documentation/DocBook/media_api.tmpl b/Documentation/DocBook/media_api.tmpl index 4c8d282..df6db3a 100644 --- a/Documentation/DocBook/media_api.tmpl +++ b/Documentation/DocBook/media_api.tmpl @@ -91,7 +91,7 @@ Foundation. A copy of the license is included in the chapter entitled Mauro Chehab Carvalho -
mchehab@redhat.com
 +
m.chehab@samsung.com
 Initial version. -- cgit v1.1 From 1b962087a792556f67191b88a2f80bf949175e54 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Tue, 7 Jan 2014 06:46:37 -0300 Subject: [media] DocBook media: update copyright years and Introduction It's now 2014, so update those copyright years. Also fix a typo in the introduction and mention that this document also covers output, codec and remote control devices. Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/dvbapi.xml | 2 +- Documentation/DocBook/media/v4l/v4l2.xml | 1 + Documentation/DocBook/media_api.tmpl | 13 +++++++------ 3 files changed, 9 insertions(+), 7 deletions(-) diff --git a/Documentation/DocBook/media/dvb/dvbapi.xml b/Documentation/DocBook/media/dvb/dvbapi.xml index 49f46e8..4c15396 100644 --- a/Documentation/DocBook/media/dvb/dvbapi.xml +++ b/Documentation/DocBook/media/dvb/dvbapi.xml @@ -28,7 +28,7 @@ Convergence GmbH - 2009-2012 + 2009-2014 Mauro Carvalho Chehab diff --git a/Documentation/DocBook/media/v4l/v4l2.xml b/Documentation/DocBook/media/v4l/v4l2.xml index 4584841..1a30463 100644 --- a/Documentation/DocBook/media/v4l/v4l2.xml +++ b/Documentation/DocBook/media/v4l/v4l2.xml @@ -125,6 +125,7 @@ Remote Controller chapter. 2011 2012 2013 + 2014 Bill Dirks, Michael H. Schimek, Hans Verkuil, Martin Rubli, Andy Walls, Muralidharan Karicheri, Mauro Carvalho Chehab, Pawel Osciak diff --git a/Documentation/DocBook/media_api.tmpl b/Documentation/DocBook/media_api.tmpl index df6db3a..ba1d704 100644 --- a/Documentation/DocBook/media_api.tmpl +++ b/Documentation/DocBook/media_api.tmpl @@ -37,7 +37,7 @@ LINUX MEDIA INFRASTRUCTURE API - 2009-2012 + 2009-2014 LinuxTV Developers @@ -58,12 +58,13 @@ Foundation. A copy of the license is included in the chapter entitled Introduction This document covers the Linux Kernel to Userspace API's used by - video and radio straming devices, including video cameras, + video and radio streaming devices, including video cameras, analog and digital TV receiver cards, AM/FM receiver cards, - streaming capture devices. + streaming capture and output devices, codec devices and remote + controllers. It is divided into four parts. - The first part covers radio, capture, - cameras and analog TV devices. + The first part covers radio, video capture and output, + cameras, analog TV devices and codecs. The second part covers the API used for digital TV and Internet reception via one of the several digital tv standards. While it is called as DVB API, @@ -96,7 +97,7 @@ Foundation. A copy of the license is included in the chapter entitled - 2009-2012 + 2009-2014 Mauro Carvalho Chehab -- cgit v1.1 From 1c656c87ac3f7a602cfa9b39b6cb955b27f2f0b0 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Tue, 7 Jan 2014 08:17:35 -0300 Subject: [media] DocBook media: Cleanup some sections at common.xml Updates sections "Querying Capabilities", "Application Priority", "Video Inputs and Outputs" and "Audio Inputs and Outputs". Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/v4l/common.xml | 89 ++++++++++++------------------ 1 file changed, 35 insertions(+), 54 deletions(-) diff --git a/Documentation/DocBook/media/v4l/common.xml b/Documentation/DocBook/media/v4l/common.xml index 1ddf354..5a97935 100644 --- a/Documentation/DocBook/media/v4l/common.xml +++ b/Documentation/DocBook/media/v4l/common.xml @@ -240,15 +240,15 @@ methods supported by the device. Starting with kernel version 3.1, VIDIOC-QUERYCAP will return the V4L2 API version used by the driver, with generally matches the Kernel version. -There's no need of using &VIDIOC-QUERYCAP; to check if an specific ioctl is -supported, the V4L2 core now returns ENOIOCTLCMD if a driver doesn't provide +There's no need of using &VIDIOC-QUERYCAP; to check if a specific ioctl is +supported, the V4L2 core now returns ENOTTY if a driver doesn't provide support for an ioctl. Other features can be queried by calling the respective ioctl, for example &VIDIOC-ENUMINPUT; to learn about the number, types and names of video connectors on the device. Although abstraction is a major objective of this API, the -ioctl also allows driver specific applications to reliable identify +&VIDIOC-QUERYCAP; ioctl also allows driver specific applications to reliably identify the driver. All V4L2 drivers must support @@ -278,9 +278,7 @@ Applications requiring a different priority will usually call the &VIDIOC-QUERYCAP; ioctl. Ioctls changing driver properties, such as &VIDIOC-S-INPUT;, -return an &EBUSY; after another application obtained higher priority. -An event mechanism to notify applications about asynchronous property -changes has been proposed but not added yet. +return an &EBUSY; after another application obtained higher priority.
@@ -288,9 +286,9 @@ changes has been proposed but not added yet. Video inputs and outputs are physical connectors of a device. These can be for example RF connectors (antenna/cable), CVBS -a.k.a. Composite Video, S-Video or RGB connectors. Only video and VBI -capture devices have inputs, output devices have outputs, at least one -each. Radio devices have no video inputs or outputs. +a.k.a. Composite Video, S-Video or RGB connectors. Video and VBI +capture devices have inputs. Video and VBI output devices have outputs, +at least one each. Radio devices have no video inputs or outputs. To learn about the number and attributes of the available inputs and outputs applications can enumerate them with the @@ -299,30 +297,13 @@ available inputs and outputs applications can enumerate them with the ioctl also contains signal status information applicable when the current video input is queried. - The &VIDIOC-G-INPUT; and &VIDIOC-G-OUTPUT; ioctl return the + The &VIDIOC-G-INPUT; and &VIDIOC-G-OUTPUT; ioctls return the index of the current video input or output. To select a different input or output applications call the &VIDIOC-S-INPUT; and -&VIDIOC-S-OUTPUT; ioctl. Drivers must implement all the input ioctls +&VIDIOC-S-OUTPUT; ioctls. Drivers must implement all the input ioctls when the device has one or more inputs, all the output ioctls when the device has one or more outputs. - - Information about the current video input @@ -330,20 +311,20 @@ device has one or more outputs. &v4l2-input; input; int index; -if (-1 == ioctl (fd, &VIDIOC-G-INPUT;, &index)) { - perror ("VIDIOC_G_INPUT"); - exit (EXIT_FAILURE); +if (-1 == ioctl(fd, &VIDIOC-G-INPUT;, &index)) { + perror("VIDIOC_G_INPUT"); + exit(EXIT_FAILURE); } -memset (&input, 0, sizeof (input)); +memset(&input, 0, sizeof(input)); input.index = index; -if (-1 == ioctl (fd, &VIDIOC-ENUMINPUT;, &input)) { - perror ("VIDIOC_ENUMINPUT"); - exit (EXIT_FAILURE); +if (-1 == ioctl(fd, &VIDIOC-ENUMINPUT;, &input)) { + perror("VIDIOC_ENUMINPUT"); + exit(EXIT_FAILURE); } -printf ("Current input: %s\n", input.name); +printf("Current input: %s\n", input.name); @@ -355,9 +336,9 @@ int index; index = 0; -if (-1 == ioctl (fd, &VIDIOC-S-INPUT;, &index)) { - perror ("VIDIOC_S_INPUT"); - exit (EXIT_FAILURE); +if (-1 == ioctl(fd, &VIDIOC-S-INPUT;, &index)) { + perror("VIDIOC_S_INPUT"); + exit(EXIT_FAILURE); } @@ -397,7 +378,7 @@ available inputs and outputs applications can enumerate them with the also contains signal status information applicable when the current audio input is queried. - The &VIDIOC-G-AUDIO; and &VIDIOC-G-AUDOUT; ioctl report + The &VIDIOC-G-AUDIO; and &VIDIOC-G-AUDOUT; ioctls report the current audio input and output, respectively. Note that, unlike &VIDIOC-G-INPUT; and &VIDIOC-G-OUTPUT; these ioctls return a structure as VIDIOC_ENUMAUDIO and @@ -408,11 +389,11 @@ applications call the &VIDIOC-S-AUDIO; ioctl. To select an audio output (which presently has no changeable properties) applications call the &VIDIOC-S-AUDOUT; ioctl. - Drivers must implement all input ioctls when the device -has one or more inputs, all output ioctls when the device has one -or more outputs. When the device has any audio inputs or outputs the -driver must set the V4L2_CAP_AUDIO flag in the -&v4l2-capability; returned by the &VIDIOC-QUERYCAP; ioctl. + Drivers must implement all audio input ioctls when the device +has multiple selectable audio inputs, all audio output ioctls when the +device has multiple selectable audio outputs. When the device has any +audio inputs or outputs the driver must set the V4L2_CAP_AUDIO +flag in the &v4l2-capability; returned by the &VIDIOC-QUERYCAP; ioctl. Information about the current audio input @@ -420,14 +401,14 @@ driver must set the V4L2_CAP_AUDIO flag in the &v4l2-audio; audio; -memset (&audio, 0, sizeof (audio)); +memset(&audio, 0, sizeof(audio)); -if (-1 == ioctl (fd, &VIDIOC-G-AUDIO;, &audio)) { - perror ("VIDIOC_G_AUDIO"); - exit (EXIT_FAILURE); +if (-1 == ioctl(fd, &VIDIOC-G-AUDIO;, &audio)) { + perror("VIDIOC_G_AUDIO"); + exit(EXIT_FAILURE); } -printf ("Current input: %s\n", audio.name); +printf("Current input: %s\n", audio.name); @@ -437,13 +418,13 @@ printf ("Current input: %s\n", audio.name); &v4l2-audio; audio; -memset (&audio, 0, sizeof (audio)); /* clear audio.mode, audio.reserved */ +memset(&audio, 0, sizeof(audio)); /* clear audio.mode, audio.reserved */ audio.index = 0; -if (-1 == ioctl (fd, &VIDIOC-S-AUDIO;, &audio)) { - perror ("VIDIOC_S_AUDIO"); - exit (EXIT_FAILURE); +if (-1 == ioctl(fd, &VIDIOC-S-AUDIO;, &audio)) { + perror("VIDIOC_S_AUDIO"); + exit(EXIT_FAILURE); } -- cgit v1.1 From d4d6819f9b9c0f605c3a849c2cf055c66de459b0 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Tue, 7 Jan 2014 09:39:57 -0300 Subject: [media] DocBook media: update three sections of common.xml Updates for the "Tuners and Modulators", "Video Standards" and "Digital Video (DV) Timings" sections. Besides lots of trivial little fixes the main changes are: - Remove two footnotes from "Video Standards": the first is a discussion of alternative methods of setting standards, which is pretty pointless since the standards API is effectively frozen anyway, and the second points to 'rationale' that makes little or no sense to me. - Clarify a few things in the "Digital Video (DV) Timings" section. It was awkwardly formatted as well: there used to be a list with multiple bullets that has been reduced to a single item, so drop the list and rewrite that text. Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/v4l/common.xml | 132 ++++++++++++----------------- 1 file changed, 53 insertions(+), 79 deletions(-) diff --git a/Documentation/DocBook/media/v4l/common.xml b/Documentation/DocBook/media/v4l/common.xml index 5a97935..0936dd2 100644 --- a/Documentation/DocBook/media/v4l/common.xml +++ b/Documentation/DocBook/media/v4l/common.xml @@ -449,7 +449,7 @@ the tuner. video inputs. To query and change tuner properties applications use the -&VIDIOC-G-TUNER; and &VIDIOC-S-TUNER; ioctl, respectively. The +&VIDIOC-G-TUNER; and &VIDIOC-S-TUNER; ioctls, respectively. The &v4l2-tuner; returned by VIDIOC_G_TUNER also contains signal status information applicable when the tuner of the current video or radio input is queried. Note that @@ -514,7 +514,7 @@ standards or variations of standards. Each video input and output may support another set of standards. This set is reported by the std field of &v4l2-input; and &v4l2-output; returned by the &VIDIOC-ENUMINPUT; and -&VIDIOC-ENUMOUTPUT; ioctl, respectively. +&VIDIOC-ENUMOUTPUT; ioctls, respectively. V4L2 defines one bit for each analog video standard currently in use worldwide, and sets aside bits for driver defined @@ -545,28 +545,10 @@ automatically. To query and select the standard used by the current video input or output applications call the &VIDIOC-G-STD; and &VIDIOC-S-STD; ioctl, respectively. The received -standard can be sensed with the &VIDIOC-QUERYSTD; ioctl. Note that the parameter of all these ioctls is a pointer to a &v4l2-std-id; type (a standard set), not an index into the standard enumeration. - An alternative to the current scheme is to use pointers -to indices as arguments of VIDIOC_G_STD and -VIDIOC_S_STD, the &v4l2-input; and -&v4l2-output; std field would be a set of -indices like audioset. - Indices are consistent with the rest of the API -and identify the standard unambiguously. In the present scheme of -things an enumerated standard is looked up by &v4l2-std-id;. Now the -standards supported by the inputs of a device can overlap. Just -assume the tuner and composite input in the example above both -exist on a device. An enumeration of "PAL-B/G", "PAL-H/I" suggests -a choice which does not exist. We cannot merge or omit sets, because -applications would be unable to find the standards reported by -VIDIOC_G_STD. That leaves separate enumerations -for each input. Also selecting a standard by &v4l2-std-id; can be -ambiguous. Advantage of this method is that applications need not -identify the standard indirectly, after enumerating.So in -summary, the lookup itself is unavoidable. The difference is only -whether the lookup is necessary to find an enumerated standard or to -switch to a standard by &v4l2-std-id;. - Drivers must implement all video standard ioctls +standard can be sensed with the &VIDIOC-QUERYSTD; ioctl. Note that the +parameter of all these ioctls is a pointer to a &v4l2-std-id; type +(a standard set), not an index into the standard +enumeration. Drivers must implement all video standard ioctls when the device has one or more video inputs or outputs. Special rules apply to devices such as USB cameras where the notion of video @@ -585,17 +567,10 @@ to zero and the VIDIOC_G_STD, VIDIOC_S_STD, VIDIOC_QUERYSTD and VIDIOC_ENUMSTD ioctls shall return the -&ENOTTY;. - See for a rationale. +&ENOTTY; or the &EINVAL;. Applications can make use of the and flags to determine whether the video standard ioctls -are available for the device. - - See for a rationale. Probably -even USB cameras follow some well known video standard. It might have -been better to explicitly indicate elsewhere if a device cannot live -up to normal expectations, instead of this exception. - +can be used with the given input or output. Information about the current video standard @@ -604,22 +579,22 @@ up to normal expectations, instead of this exception. &v4l2-std-id; std_id; &v4l2-standard; standard; -if (-1 == ioctl (fd, &VIDIOC-G-STD;, &std_id)) { +if (-1 == ioctl(fd, &VIDIOC-G-STD;, &std_id)) { /* Note when VIDIOC_ENUMSTD always returns ENOTTY this is no video device or it falls under the USB exception, and VIDIOC_G_STD returning ENOTTY is no error. */ - perror ("VIDIOC_G_STD"); - exit (EXIT_FAILURE); + perror("VIDIOC_G_STD"); + exit(EXIT_FAILURE); } -memset (&standard, 0, sizeof (standard)); +memset(&standard, 0, sizeof(standard)); standard.index = 0; -while (0 == ioctl (fd, &VIDIOC-ENUMSTD;, &standard)) { +while (0 == ioctl(fd, &VIDIOC-ENUMSTD;, &standard)) { if (standard.id & std_id) { - printf ("Current video standard: %s\n", standard.name); - exit (EXIT_SUCCESS); + printf("Current video standard: %s\n", standard.name); + exit(EXIT_SUCCESS); } standard.index++; @@ -629,8 +604,8 @@ while (0 == ioctl (fd, &VIDIOC-ENUMSTD;, &standard)) { empty unless this device falls under the USB exception. */ if (errno == EINVAL || standard.index == 0) { - perror ("VIDIOC_ENUMSTD"); - exit (EXIT_FAILURE); + perror("VIDIOC_ENUMSTD"); + exit(EXIT_FAILURE); } @@ -643,26 +618,26 @@ input &v4l2-input; input; &v4l2-standard; standard; -memset (&input, 0, sizeof (input)); +memset(&input, 0, sizeof(input)); -if (-1 == ioctl (fd, &VIDIOC-G-INPUT;, &input.index)) { - perror ("VIDIOC_G_INPUT"); - exit (EXIT_FAILURE); +if (-1 == ioctl(fd, &VIDIOC-G-INPUT;, &input.index)) { + perror("VIDIOC_G_INPUT"); + exit(EXIT_FAILURE); } -if (-1 == ioctl (fd, &VIDIOC-ENUMINPUT;, &input)) { - perror ("VIDIOC_ENUM_INPUT"); - exit (EXIT_FAILURE); +if (-1 == ioctl(fd, &VIDIOC-ENUMINPUT;, &input)) { + perror("VIDIOC_ENUM_INPUT"); + exit(EXIT_FAILURE); } -printf ("Current input %s supports:\n", input.name); +printf("Current input %s supports:\n", input.name); -memset (&standard, 0, sizeof (standard)); +memset(&standard, 0, sizeof(standard)); standard.index = 0; -while (0 == ioctl (fd, &VIDIOC-ENUMSTD;, &standard)) { +while (0 == ioctl(fd, &VIDIOC-ENUMSTD;, &standard)) { if (standard.id & input.std) - printf ("%s\n", standard.name); + printf("%s\n", standard.name); standard.index++; } @@ -671,8 +646,8 @@ while (0 == ioctl (fd, &VIDIOC-ENUMSTD;, &standard)) { empty unless this device falls under the USB exception. */ if (errno != EINVAL || standard.index == 0) { - perror ("VIDIOC_ENUMSTD"); - exit (EXIT_FAILURE); + perror("VIDIOC_ENUMSTD"); + exit(EXIT_FAILURE); } @@ -684,21 +659,21 @@ if (errno != EINVAL || standard.index == 0) { &v4l2-input; input; &v4l2-std-id; std_id; -memset (&input, 0, sizeof (input)); +memset(&input, 0, sizeof(input)); -if (-1 == ioctl (fd, &VIDIOC-G-INPUT;, &input.index)) { - perror ("VIDIOC_G_INPUT"); - exit (EXIT_FAILURE); +if (-1 == ioctl(fd, &VIDIOC-G-INPUT;, &input.index)) { + perror("VIDIOC_G_INPUT"); + exit(EXIT_FAILURE); } -if (-1 == ioctl (fd, &VIDIOC-ENUMINPUT;, &input)) { - perror ("VIDIOC_ENUM_INPUT"); - exit (EXIT_FAILURE); +if (-1 == ioctl(fd, &VIDIOC-ENUMINPUT;, &input)) { + perror("VIDIOC_ENUM_INPUT"); + exit(EXIT_FAILURE); } if (0 == (input.std & V4L2_STD_PAL_BG)) { - fprintf (stderr, "Oops. B/G PAL is not supported.\n"); - exit (EXIT_FAILURE); + fprintf(stderr, "Oops. B/G PAL is not supported.\n"); + exit(EXIT_FAILURE); } /* Note this is also supposed to work when only B @@ -706,9 +681,9 @@ if (0 == (input.std & V4L2_STD_PAL_BG)) { std_id = V4L2_STD_PAL_BG; -if (-1 == ioctl (fd, &VIDIOC-S-STD;, &std_id)) { - perror ("VIDIOC_S_STD"); - exit (EXIT_FAILURE); +if (-1 == ioctl(fd, &VIDIOC-S-STD;, &std_id)) { + perror("VIDIOC_S_STD"); + exit(EXIT_FAILURE); } @@ -721,26 +696,25 @@ corresponding video timings. Today there are many more different hardware interf such as High Definition TV interfaces (HDMI), VGA, DVI connectors etc., that carry video signals and there is a need to extend the API to select the video timings for these interfaces. Since it is not possible to extend the &v4l2-std-id; due to -the limited bits available, a new set of IOCTLs was added to set/get video timings at -the input and output: - - DV Timings: This will allow applications to define detailed -video timings for the interface. This includes parameters such as width, height, -polarities, frontporch, backporch etc. The linux/v4l2-dv-timings.h +the limited bits available, a new set of ioctls was added to set/get video timings at +the input and output. + + These ioctls deal with the detailed digital video timings that define +each video format. This includes parameters such as the active video width and height, +signal polarities, frontporches, backporches, sync widths etc. The linux/v4l2-dv-timings.h header can be used to get the timings of the formats in the and standards. - - - To enumerate and query the attributes of the DV timings supported by a device, + + To enumerate and query the attributes of the DV timings supported by a device applications use the &VIDIOC-ENUM-DV-TIMINGS; and &VIDIOC-DV-TIMINGS-CAP; ioctls. - To set DV timings for the device, applications use the + To set DV timings for the device applications use the &VIDIOC-S-DV-TIMINGS; ioctl and to get current DV timings they use the &VIDIOC-G-DV-TIMINGS; ioctl. To detect the DV timings as seen by the video receiver applications use the &VIDIOC-QUERY-DV-TIMINGS; ioctl. Applications can make use of the and - flags to decide what ioctls are available to set the -video timings for the device. + flags to determine whether the digital video ioctls +can be used with the given input or output.
&sub-controls; -- cgit v1.1 From 211e7f2e6c9c65f5b1d6727fb5cc6f824bfa8127 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Tue, 7 Jan 2014 10:01:27 -0300 Subject: [media] DocBook media: drop the old incorrect packed RGB table The old table is most definitely wrong. All applications and all drivers that I have ever tested follow the corrected table. Furthermore, that's what all applications expect as well. Any drivers that do not follow the corrected table are broken and should be fixed. This patch drops the old table and replaces it with the corrected table. This should prevent a lot of confusion. Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- .../DocBook/media/v4l/pixfmt-packed-rgb.xml | 513 ++------------------- 1 file changed, 49 insertions(+), 464 deletions(-) diff --git a/Documentation/DocBook/media/v4l/pixfmt-packed-rgb.xml b/Documentation/DocBook/media/v4l/pixfmt-packed-rgb.xml index 166c8d6..e1c4f8b 100644 --- a/Documentation/DocBook/media/v4l/pixfmt-packed-rgb.xml +++ b/Documentation/DocBook/media/v4l/pixfmt-packed-rgb.xml @@ -121,14 +121,14 @@ colorspace V4L2_COLORSPACE_SRGB. V4L2_PIX_FMT_RGB332 'RGB1' - b1 - b0 - g2 - g1 - g0 r2 r1 r0 + g2 + g1 + g0 + b1 + b0 V4L2_PIX_FMT_RGB444 @@ -159,18 +159,18 @@ colorspace V4L2_COLORSPACE_SRGB. g2 g1 g0 - r4 - r3 - r2 - r1 - r0 - - a b4 b3 b2 b1 b0 + + a + r4 + r3 + r2 + r1 + r0 g4 g3 @@ -181,17 +181,17 @@ colorspace V4L2_COLORSPACE_SRGB. g2 g1 g0 - r4 - r3 - r2 - r1 - r0 - b4 b3 b2 b1 b0 + + r4 + r3 + r2 + r1 + r0 g5 g4 g3 @@ -201,32 +201,32 @@ colorspace V4L2_COLORSPACE_SRGB. 'RGBQ' a - b4 - b3 - b2 - b1 - b0 - g4 - g3 - - g2 - g1 - g0 r4 r3 r2 r1 r0 - - - V4L2_PIX_FMT_RGB565X - 'RGBR' + g4 + g3 + g2 + g1 + g0 b4 b3 b2 b1 b0 + + + V4L2_PIX_FMT_RGB565X + 'RGBR' + + r4 + r3 + r2 + r1 + r0 g5 g4 g3 @@ -234,11 +234,11 @@ colorspace V4L2_COLORSPACE_SRGB. g2 g1 g0 - r4 - r3 - r2 - r1 - r0 + b4 + b3 + b2 + b1 + b0 V4L2_PIX_FMT_BGR666 @@ -385,6 +385,15 @@ colorspace V4L2_COLORSPACE_SRGB. V4L2_PIX_FMT_RGB32 'RGB4' + a7 + a6 + a5 + a4 + a3 + a2 + a1 + a0 + r7 r6 r5 @@ -411,25 +420,16 @@ colorspace V4L2_COLORSPACE_SRGB. b2 b1 b0 - - a7 - a6 - a5 - a4 - a3 - a2 - a1 - a0 - Bit 7 is the most significant bit. The value of a = alpha + Bit 7 is the most significant bit. The value of the a = alpha bits is undefined when reading from the driver, ignored when writing to the driver, except when alpha blending has been negotiated for a Video Overlay or -Video Output Overlay or when alpha component has been configured +Video Output Overlay or when the alpha component has been configured for a Video Capture by means of V4L2_CID_ALPHA_COMPONENT control. @@ -512,421 +512,6 @@ image - - Drivers may interpret these formats differently. - - - Some RGB formats above are uncommon and were probably -defined in error. Drivers may interpret them as in . - - - Packed RGB Image Formats (corrected) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Identifier - Code -   - Byte 0 in memory - Byte 1 - Byte 2 - Byte 3 - - -   -   - Bit - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 -   - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 -   - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 -   - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - - - - - V4L2_PIX_FMT_RGB332 - 'RGB1' - - r2 - r1 - r0 - g2 - g1 - g0 - b1 - b0 - - - V4L2_PIX_FMT_RGB444 - 'R444' - - g3 - g2 - g1 - g0 - b3 - b2 - b1 - b0 - - a3 - a2 - a1 - a0 - r3 - r2 - r1 - r0 - - - V4L2_PIX_FMT_RGB555 - 'RGBO' - - g2 - g1 - g0 - b4 - b3 - b2 - b1 - b0 - - a - r4 - r3 - r2 - r1 - r0 - g4 - g3 - - - V4L2_PIX_FMT_RGB565 - 'RGBP' - - g2 - g1 - g0 - b4 - b3 - b2 - b1 - b0 - - r4 - r3 - r2 - r1 - r0 - g5 - g4 - g3 - - - V4L2_PIX_FMT_RGB555X - 'RGBQ' - - a - r4 - r3 - r2 - r1 - r0 - g4 - g3 - - g2 - g1 - g0 - b4 - b3 - b2 - b1 - b0 - - - V4L2_PIX_FMT_RGB565X - 'RGBR' - - r4 - r3 - r2 - r1 - r0 - g5 - g4 - g3 - - g2 - g1 - g0 - b4 - b3 - b2 - b1 - b0 - - - V4L2_PIX_FMT_BGR666 - 'BGRH' - - b5 - b4 - b3 - b2 - b1 - b0 - g5 - g4 - - g3 - g2 - g1 - g0 - r5 - r4 - r3 - r2 - - r1 - r0 - - - - - - - - - - - - - - - - - V4L2_PIX_FMT_BGR24 - 'BGR3' - - b7 - b6 - b5 - b4 - b3 - b2 - b1 - b0 - - g7 - g6 - g5 - g4 - g3 - g2 - g1 - g0 - - r7 - r6 - r5 - r4 - r3 - r2 - r1 - r0 - - - V4L2_PIX_FMT_RGB24 - 'RGB3' - - r7 - r6 - r5 - r4 - r3 - r2 - r1 - r0 - - g7 - g6 - g5 - g4 - g3 - g2 - g1 - g0 - - b7 - b6 - b5 - b4 - b3 - b2 - b1 - b0 - - - V4L2_PIX_FMT_BGR32 - 'BGR4' - - b7 - b6 - b5 - b4 - b3 - b2 - b1 - b0 - - g7 - g6 - g5 - g4 - g3 - g2 - g1 - g0 - - r7 - r6 - r5 - r4 - r3 - r2 - r1 - r0 - - a7 - a6 - a5 - a4 - a3 - a2 - a1 - a0 - - - V4L2_PIX_FMT_RGB32 - 'RGB4' - - a7 - a6 - a5 - a4 - a3 - a2 - a1 - a0 - - r7 - r6 - r5 - r4 - r3 - r2 - r1 - r0 - - g7 - g6 - g5 - g4 - g3 - g2 - g1 - g0 - - b7 - b6 - b5 - b4 - b3 - b2 - b1 - b0 - - - -
- A test utility to determine which RGB formats a driver actually supports is available from the LinuxTV v4l-dvb repository. See &v4l-dvb; for access instructions. -- cgit v1.1 From 26f08db9b0d10dc901f7565fc350943ea46e0381 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Mon, 3 Feb 2014 07:29:03 -0300 Subject: [media] DocBook media: add revision entry for 3.15 [m.chehab@samsung.com: removed "Opening and Closing Devices" from the list of changes, as the patch with such change weren't applied] Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/v4l/v4l2.xml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/DocBook/media/v4l/v4l2.xml b/Documentation/DocBook/media/v4l/v4l2.xml index 1a30463..087e846 100644 --- a/Documentation/DocBook/media/v4l/v4l2.xml +++ b/Documentation/DocBook/media/v4l/v4l2.xml @@ -142,6 +142,16 @@ structs, ioctls) must be noted in more detail in the history chapter applications. --> + 3.15 + 2014-02-03 + hv + Update several sections of "Common API Elements": +"Querying Capabilities", "Application Priority", "Video Inputs and Outputs", "Audio Inputs and Outputs" +"Tuners and Modulators", "Video Standards" and "Digital Video (DV) Timings". + + + + 3.14 2013-11-25 rr -- cgit v1.1 From 5d5f87bce6cd30cde2ea02f9f8338d6dba97f8d2 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Tue, 4 Feb 2014 09:55:19 -0300 Subject: [media] DocBook: partial rewrite of "Opening and Closing Devices" This section was horribly out of date. A lot of references to old and obsolete behavior have been dropped. Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/v4l/common.xml | 191 +++++++++++------------------ Documentation/DocBook/media/v4l/v4l2.xml | 2 +- 2 files changed, 70 insertions(+), 123 deletions(-) diff --git a/Documentation/DocBook/media/v4l/common.xml b/Documentation/DocBook/media/v4l/common.xml index 0936dd2..71f6bf9 100644 --- a/Documentation/DocBook/media/v4l/common.xml +++ b/Documentation/DocBook/media/v4l/common.xml @@ -38,70 +38,41 @@ the basic concepts applicable to all devices. V4L2 drivers are implemented as kernel modules, loaded manually by the system administrator or automatically when a device is -first opened. The driver modules plug into the "videodev" kernel +first discovered. The driver modules plug into the "videodev" kernel module. It provides helper functions and a common application interface specified in this document. Each driver thus loaded registers one or more device nodes -with major number 81 and a minor number between 0 and 255. Assigning -minor numbers to V4L2 devices is entirely up to the system administrator, -this is primarily intended to solve conflicts between devices. - Access permissions are associated with character -device special files, hence we must ensure device numbers cannot -change with the module load order. To this end minor numbers are no -longer automatically assigned by the "videodev" module as in V4L but -requested by the driver. The defaults will suffice for most people -unless two drivers compete for the same minor numbers. - The module options to select minor numbers are named -after the device special file with a "_nr" suffix. For example "video_nr" -for /dev/video video capture devices. The number is -an offset to the base minor number associated with the device type. - - In earlier versions of the V4L2 API the module options -where named after the device special file with a "unit_" prefix, expressing -the minor number itself, not an offset. Rationale for this change is unknown. -Lastly the naming and semantics are just a convention among driver writers, -the point to note is that minor numbers are not supposed to be hardcoded -into drivers. - When the driver supports multiple devices of the same -type more than one minor number can be assigned, separated by commas: - +with major number 81 and a minor number between 0 and 255. Minor numbers +are allocated dynamically unless the kernel is compiled with the kernel +option CONFIG_VIDEO_FIXED_MINOR_RANGES. In that case minor numbers are +allocated in ranges depending on the device node type (video, radio, etc.). + + Many drivers support "video_nr", "radio_nr" or "vbi_nr" +module options to select specific video/radio/vbi node numbers. This allows +the user to request that the device node is named e.g. /dev/video5 instead +of leaving it to chance. When the driver supports multiple devices of the same +type more than one device node number can be assigned, separated by commas: + -> insmod mydriver.o video_nr=0,1 radio_nr=0,1 +> modprobe mydriver video_nr=0,1 radio_nr=0,1 In /etc/modules.conf this may be written as: -alias char-major-81-0 mydriver -alias char-major-81-1 mydriver -alias char-major-81-64 mydriver -options mydriver video_nr=0,1 radio_nr=0,1 +options mydriver video_nr=0,1 radio_nr=0,1 - - - When an application attempts to open a device -special file with major number 81 and minor number 0, 1, or 64, load -"mydriver" (and the "videodev" module it depends upon). - - - Register the first two video capture devices with -minor number 0 and 1 (base number is 0), the first two radio device -with minor number 64 and 65 (base 64). - - - When no minor number is given as module -option the driver supplies a default. -recommends the base minor numbers to be used for the various device -types. Obviously minor numbers must be unique. When the number is -already in use the offending device will not be -registered. - - By convention system administrators create various -character device special files with these major and minor numbers in -the /dev directory. The names recommended for the -different V4L2 device types are listed in . + When no device node number is given as module +option the driver supplies a default. + + Normally udev will create the device nodes in /dev automatically +for you. If udev is not installed, then you need to enable the +CONFIG_VIDEO_FIXED_MINOR_RANGES kernel option in order to be able to correctly +relate a minor number to a device node number. I.e., you need to be certain +that minor number 5 maps to device node name video5. With this kernel option +different device types have different minor number ranges. These ranges are +listed in . The creation of character special files (with @@ -110,85 +81,66 @@ devices cannot be opened by major and minor number. That means applications cannot reliable scan for loaded or installed drivers. The user must enter a device name, or the application can try the conventional device names. - - Under the device filesystem (devfs) the minor number -options are ignored. V4L2 drivers (or by proxy the "videodev" module) -automatically create the required device files in the -/dev/v4l directory using the conventional device -names above.
Multiple Opens - In general, V4L2 devices can be opened more than once. + V4L2 devices can be opened more than once. +There are still some old and obscure drivers that have not been updated to +allow for multiple opens. This implies that for such drivers &func-open; can +return an &EBUSY; when the device is already in use. When this is supported by the driver, users can for example start a "panel" application to change controls like brightness or audio volume, while another application captures video and audio. In other words, panel -applications are comparable to an OSS or ALSA audio mixer application. -When a device supports multiple functions like capturing and overlay -simultaneously, multiple opens allow concurrent -use of the device by forked processes or specialized applications. - - Multiple opens are optional, although drivers should -permit at least concurrent accesses without data exchange, &ie; panel -applications. This implies &func-open; can return an &EBUSY; when the -device is already in use, as well as &func-ioctl; functions initiating -data exchange (namely the &VIDIOC-S-FMT; ioctl), and the &func-read; -and &func-write; functions. - - Mere opening a V4L2 device does not grant exclusive +applications are comparable to an ALSA audio mixer application. +Just opening a V4L2 device should not change the state of the device. +Unfortunately, opening a radio device often switches the state of the +device to radio mode in many drivers. This behavior should be fixed eventually +as it violates the V4L2 specification. + + Once an application has allocated the memory buffers needed for +streaming data (by calling the &VIDIOC-REQBUFS; or &VIDIOC-CREATE-BUFS; ioctls, +or implicitly by calling the &func-read; or &func-write; functions) that +application (filehandle) becomes the owner of the device. It is no longer +allowed to make changes that would affect the buffer sizes (e.g. by calling +the &VIDIOC-S-FMT; ioctl) and other applications are no longer allowed to allocate +buffers or start or stop streaming. The &EBUSY; will be returned instead. + + Merely opening a V4L2 device does not grant exclusive access. Drivers could recognize the O_EXCL open flag. Presently this is not required, @@ -206,12 +158,7 @@ additional access privileges using the priority mechanism described in V4L2 drivers should not support multiple applications reading or writing the same data stream on a device by copying buffers, time multiplexing or similar means. This is better handled by -a proxy application in user space. When the driver supports stream -sharing anyway it must be implemented transparently. The V4L2 API does -not specify how conflicts are solved. +a proxy application in user space.
diff --git a/Documentation/DocBook/media/v4l/v4l2.xml b/Documentation/DocBook/media/v4l/v4l2.xml index 087e846..6bf3532 100644 --- a/Documentation/DocBook/media/v4l/v4l2.xml +++ b/Documentation/DocBook/media/v4l/v4l2.xml @@ -145,7 +145,7 @@ applications. --> 3.15 2014-02-03 hv - Update several sections of "Common API Elements": + Update several sections of "Common API Elements": "Opening and Closing Devices" "Querying Capabilities", "Application Priority", "Video Inputs and Outputs", "Audio Inputs and Outputs" "Tuners and Modulators", "Video Standards" and "Digital Video (DV) Timings". -- cgit v1.1 From 9e8ca38c5250d434874a13c7ba8b97b9126b746d Mon Sep 17 00:00:00 2001 From: Fengguang Wu Date: Wed, 15 Jan 2014 18:50:26 -0300 Subject: [media] em28xx-cards: em28xx_devused can be static Fix sparse warning: drivers/media/usb/em28xx/em28xx-cards.c:69:1: sparse: symbol 'em28xx_devused' was not declared. Should it be static? Signed-off-by: Fengguang Wu Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/em28xx/em28xx-cards.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/usb/em28xx/em28xx-cards.c b/drivers/media/usb/em28xx/em28xx-cards.c index 4d97a76..eb39903 100644 --- a/drivers/media/usb/em28xx/em28xx-cards.c +++ b/drivers/media/usb/em28xx/em28xx-cards.c @@ -66,7 +66,7 @@ MODULE_PARM_DESC(usb_xfer_mode, /* Bitmask marking allocated devices from 0 to EM28XX_MAXBOARDS - 1 */ -DECLARE_BITMAP(em28xx_devused, EM28XX_MAXBOARDS); +static DECLARE_BITMAP(em28xx_devused, EM28XX_MAXBOARDS); struct em28xx_hash_table { unsigned long hash; -- cgit v1.1 From 692a228e9ae419b3f51e94d1c60c1b18f37e3676 Mon Sep 17 00:00:00 2001 From: Fengguang Wu Date: Wed, 15 Jan 2014 19:42:57 -0300 Subject: [media] rc-core: ir_core_dev_number can be static Fix sparse warning: drivers/media/rc/rc-main.c:27:1: sparse: symbol 'ir_core_dev_number' was not declared. Should it be static? Signed-off-by: Fengguang Wu Signed-off-by: Mauro Carvalho Chehab --- drivers/media/rc/rc-main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/rc/rc-main.c b/drivers/media/rc/rc-main.c index 02e2f38..399eef4 100644 --- a/drivers/media/rc/rc-main.c +++ b/drivers/media/rc/rc-main.c @@ -24,7 +24,7 @@ /* Bitmap to store allocated device numbers from 0 to IRRCV_NUM_DEVICES - 1 */ #define IRRCV_NUM_DEVICES 256 -DECLARE_BITMAP(ir_core_dev_number, IRRCV_NUM_DEVICES); +static DECLARE_BITMAP(ir_core_dev_number, IRRCV_NUM_DEVICES); /* Sizes are in bytes, 256 bytes allows for 32 entries on x64 */ #define IR_TAB_MIN_SIZE 256 -- cgit v1.1 From def62216041a63d45d0fd0ff014abdc9832ee611 Mon Sep 17 00:00:00 2001 From: Georgi Chorbadzhiyski Date: Thu, 16 Jan 2014 12:07:11 -0300 Subject: [media] FE_READ_SNR and FE_READ_SIGNAL_STRENGTH docs Around 01/14/2014 06:07 PM, Mauro Carvalho Chehab scribbled: > Em Tue, 14 Jan 2014 17:55:19 +0200 > Georgi Chorbadzhiyski escreveu: >> Around 01/14/2014 05:30 PM, Mauro Carvalho Chehab scribbled: >>> Em Tue, 14 Jan 2014 17:16:10 +0200 >>> Georgi Chorbadzhiyski escreveu: >>> >>>> Hi guys, I'm confused the documentation on: >>>> >>>> http://linuxtv.org/downloads/v4l-dvb-apis/frontend_fcalls.html#FE_READ_SNR >>>> http://linuxtv.org/downloads/v4l-dvb-apis/frontend_fcalls.html#FE_READ_SIGNAL_STRENGTH >>>> >>>> states that these ioctls return int16_t values but frontend.h states: >>>> >>>> https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/include/uapi/linux/dvb/frontend.h >>>> >>>> #define FE_READ_SIGNAL_STRENGTH _IOR('o', 71, __u16) >>>> #define FE_READ_SNR _IOR('o', 72, __u16) >>>> >>>> So which one is true? >>> >>> Documentation is wrong. The returned values are unsigned. Would you mind send >>> us a patch fixing it? >> >> I would be happy to, but I can't find the repo that holds the documentation. > > It is in the Kernel tree, under Documentation/DocBook/media/dvb. The attached file contains the discussed documentation fixes. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/frontend.xml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Documentation/DocBook/media/dvb/frontend.xml b/Documentation/DocBook/media/dvb/frontend.xml index 0d6e81b..8a6a6ff 100644 --- a/Documentation/DocBook/media/dvb/frontend.xml +++ b/Documentation/DocBook/media/dvb/frontend.xml @@ -744,7 +744,7 @@ typedef enum fe_hierarchy { -int ioctl(int fd, int request = FE_READ_SNR, int16_t +int ioctl(int fd, int request = FE_READ_SNR, uint16_t ⋆snr); @@ -766,7 +766,7 @@ typedef enum fe_hierarchy { -int16_t *snr +uint16_t *snr The signal-to-noise ratio is stored into *snr. @@ -791,7 +791,7 @@ typedef enum fe_hierarchy { int ioctl( int fd, int request = - FE_READ_SIGNAL_STRENGTH, int16_t ⋆strength); + FE_READ_SIGNAL_STRENGTH, uint16_t ⋆strength); @@ -814,7 +814,7 @@ typedef enum fe_hierarchy { -int16_t *strength +uint16_t *strength The signal strength value is stored into *strength. -- cgit v1.1 From 70a2f9120ffdb9bf9732c55c3350cb002a78841d Mon Sep 17 00:00:00 2001 From: James Hogan Date: Thu, 16 Jan 2014 19:56:22 -0300 Subject: [media] media: rc: only turn on LED if keypress generated Since v3.12, specifically 153a60bb0fac ([media] rc: add feedback led trigger for rc keypresses), an LED trigger is activated on IR keydown whether or not a keypress is generated (i.e. even if there's no matching keycode). However the repeat and keyup logic isn't used unless there is a keypress, which results in non-keypress keydown events turning on the LED and not turning it off again. On the assumption that the intent was for the LED only to light up on valid key presses (you probably don't want it lighting up for the wrong remote control for example), move the led_trigger_event() call inside the keycode check. Signed-off-by: James Hogan Acked-by: Sean Young Signed-off-by: Mauro Carvalho Chehab --- drivers/media/rc/rc-main.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/media/rc/rc-main.c b/drivers/media/rc/rc-main.c index 399eef4..b75b63b 100644 --- a/drivers/media/rc/rc-main.c +++ b/drivers/media/rc/rc-main.c @@ -653,9 +653,10 @@ static void ir_do_keydown(struct rc_dev *dev, int scancode, "key 0x%04x, scancode 0x%04x\n", dev->input_name, keycode, scancode); input_report_key(dev->input_dev, keycode, 1); + + led_trigger_event(led_feedback, LED_FULL); } - led_trigger_event(led_feedback, LED_FULL); input_sync(dev->input_dev); } -- cgit v1.1 From 7bae89791eac2f18620ebd76a13c0351f4ec4319 Mon Sep 17 00:00:00 2001 From: James Hogan Date: Fri, 17 Jan 2014 10:58:46 -0300 Subject: [media] media: rc: document rc class sysfs API Briefly document /sys/class/rc/ API for remote controller devices in Documentation/ABI/teting. Signed-off-by: James Hogan Cc: Rob Landley Signed-off-by: Mauro Carvalho Chehab --- Documentation/ABI/testing/sysfs-class-rc | 34 ++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-class-rc diff --git a/Documentation/ABI/testing/sysfs-class-rc b/Documentation/ABI/testing/sysfs-class-rc new file mode 100644 index 0000000..52bc057 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-class-rc @@ -0,0 +1,34 @@ +What: /sys/class/rc/ +Date: Apr 2010 +KernelVersion: 2.6.35 +Contact: Mauro Carvalho Chehab +Description: + The rc/ class sub-directory belongs to the Remote Controller + core and provides a sysfs interface for configuring infrared + remote controller receivers. + +What: /sys/class/rc/rcN/ +Date: Apr 2010 +KernelVersion: 2.6.35 +Contact: Mauro Carvalho Chehab +Description: + A /sys/class/rc/rcN directory is created for each remote + control receiver device where N is the number of the receiver. + +What: /sys/class/rc/rcN/protocols +Date: Jun 2010 +KernelVersion: 2.6.36 +Contact: Mauro Carvalho Chehab +Description: + Reading this file returns a list of available protocols, + something like: + "rc5 [rc6] nec jvc [sony]" + Enabled protocols are shown in [] brackets. + Writing "+proto" will add a protocol to the list of enabled + protocols. + Writing "-proto" will remove a protocol from the list of enabled + protocols. + Writing "proto" will enable only "proto". + Writing "none" will disable all protocols. + Write fails with EINVAL if an invalid protocol combination or + unknown protocol name is used. -- cgit v1.1 From 38f2a214351ced1b32164da085a879d860011dcf Mon Sep 17 00:00:00 2001 From: James Hogan Date: Fri, 17 Jan 2014 10:58:47 -0300 Subject: [media] media: rc: add Sharp infrared protocol Add Sharp infrared protocol constants RC_TYPE_SHARP and RC_BIT_SHARP. Signed-off-by: James Hogan Signed-off-by: Mauro Carvalho Chehab --- drivers/media/rc/rc-main.c | 1 + include/media/rc-map.h | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/media/rc/rc-main.c b/drivers/media/rc/rc-main.c index b75b63b..f1b67db 100644 --- a/drivers/media/rc/rc-main.c +++ b/drivers/media/rc/rc-main.c @@ -791,6 +791,7 @@ static struct { RC_BIT_SONY20, "sony" }, { RC_BIT_RC5_SZ, "rc-5-sz" }, { RC_BIT_SANYO, "sanyo" }, + { RC_BIT_SHARP, "sharp" }, { RC_BIT_MCE_KBD, "mce_kbd" }, { RC_BIT_LIRC, "lirc" }, }; diff --git a/include/media/rc-map.h b/include/media/rc-map.h index a20ed97..b3224ed 100644 --- a/include/media/rc-map.h +++ b/include/media/rc-map.h @@ -30,6 +30,7 @@ enum rc_type { RC_TYPE_RC6_6A_24 = 15, /* Philips RC6-6A-24 protocol */ RC_TYPE_RC6_6A_32 = 16, /* Philips RC6-6A-32 protocol */ RC_TYPE_RC6_MCE = 17, /* MCE (Philips RC6-6A-32 subtype) protocol */ + RC_TYPE_SHARP = 18, /* Sharp protocol */ }; #define RC_BIT_NONE 0 @@ -51,6 +52,7 @@ enum rc_type { #define RC_BIT_RC6_6A_24 (1 << RC_TYPE_RC6_6A_24) #define RC_BIT_RC6_6A_32 (1 << RC_TYPE_RC6_6A_32) #define RC_BIT_RC6_MCE (1 << RC_TYPE_RC6_MCE) +#define RC_BIT_SHARP (1 << RC_TYPE_SHARP) #define RC_BIT_ALL (RC_BIT_UNKNOWN | RC_BIT_OTHER | RC_BIT_LIRC | \ RC_BIT_RC5 | RC_BIT_RC5X | RC_BIT_RC5_SZ | \ @@ -58,7 +60,7 @@ enum rc_type { RC_BIT_SONY12 | RC_BIT_SONY15 | RC_BIT_SONY20 | \ RC_BIT_NEC | RC_BIT_SANYO | RC_BIT_MCE_KBD | \ RC_BIT_RC6_0 | RC_BIT_RC6_6A_20 | RC_BIT_RC6_6A_24 | \ - RC_BIT_RC6_6A_32 | RC_BIT_RC6_MCE) + RC_BIT_RC6_6A_32 | RC_BIT_RC6_MCE | RC_BIT_SHARP) struct rc_map_table { u32 scancode; -- cgit v1.1 From 1d184b0bc13d49108e571033fc00f3b5f32670e1 Mon Sep 17 00:00:00 2001 From: James Hogan Date: Fri, 17 Jan 2014 10:58:48 -0300 Subject: [media] media: rc: add raw decoder for Sharp protocol Add a raw decoder for the Sharp protocol. It uses a pulse distance modulation with a pulse of 320us and a bit period of 2ms for a logical 1 and 1ms for a logical 0. The first part of the message consists of a 5-bit address, an 8-bit command, and two other bits, followed by a 40ms gap before the echo message which is an inverted version of the main message except for the address bits. Signed-off-by: James Hogan Cc: Mauro Carvalho Chehab Cc: linux-media@vger.kernel.org Signed-off-by: Mauro Carvalho Chehab --- drivers/media/rc/Kconfig | 9 ++ drivers/media/rc/Makefile | 1 + drivers/media/rc/ir-sharp-decoder.c | 200 ++++++++++++++++++++++++++++++++++++ drivers/media/rc/rc-core-priv.h | 6 ++ 4 files changed, 216 insertions(+) create mode 100644 drivers/media/rc/ir-sharp-decoder.c diff --git a/drivers/media/rc/Kconfig b/drivers/media/rc/Kconfig index 904f113..3b25887 100644 --- a/drivers/media/rc/Kconfig +++ b/drivers/media/rc/Kconfig @@ -106,6 +106,15 @@ config IR_SANYO_DECODER uses the Sanyo protocol (Sanyo, Aiwa, Chinon remotes), and you need software decoding support. +config IR_SHARP_DECODER + tristate "Enable IR raw decoder for the Sharp protocol" + depends on RC_CORE + default y + + ---help--- + Enable this option if you have an infrared remote control which + uses the Sharp protocol, and you need software decoding support. + config IR_MCE_KBD_DECODER tristate "Enable IR raw decoder for the MCE keyboard/mouse protocol" depends on RC_CORE diff --git a/drivers/media/rc/Makefile b/drivers/media/rc/Makefile index f4eb32c..36dafed 100644 --- a/drivers/media/rc/Makefile +++ b/drivers/media/rc/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_IR_JVC_DECODER) += ir-jvc-decoder.o obj-$(CONFIG_IR_SONY_DECODER) += ir-sony-decoder.o obj-$(CONFIG_IR_RC5_SZ_DECODER) += ir-rc5-sz-decoder.o obj-$(CONFIG_IR_SANYO_DECODER) += ir-sanyo-decoder.o +obj-$(CONFIG_IR_SHARP_DECODER) += ir-sharp-decoder.o obj-$(CONFIG_IR_MCE_KBD_DECODER) += ir-mce_kbd-decoder.o obj-$(CONFIG_IR_LIRC_CODEC) += ir-lirc-codec.o diff --git a/drivers/media/rc/ir-sharp-decoder.c b/drivers/media/rc/ir-sharp-decoder.c new file mode 100644 index 0000000..4c17be5 --- /dev/null +++ b/drivers/media/rc/ir-sharp-decoder.c @@ -0,0 +1,200 @@ +/* ir-sharp-decoder.c - handle Sharp IR Pulse/Space protocol + * + * Copyright (C) 2013-2014 Imagination Technologies Ltd. + * + * Based on NEC decoder: + * Copyright (C) 2010 by Mauro Carvalho Chehab + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include "rc-core-priv.h" + +#define SHARP_NBITS 15 +#define SHARP_UNIT 40000 /* ns */ +#define SHARP_BIT_PULSE (8 * SHARP_UNIT) /* 320us */ +#define SHARP_BIT_0_PERIOD (25 * SHARP_UNIT) /* 1ms (680us space) */ +#define SHARP_BIT_1_PERIOD (50 * SHARP_UNIT) /* 2ms (1680ms space) */ +#define SHARP_ECHO_SPACE (1000 * SHARP_UNIT) /* 40 ms */ +#define SHARP_TRAILER_SPACE (125 * SHARP_UNIT) /* 5 ms (even longer) */ + +enum sharp_state { + STATE_INACTIVE, + STATE_BIT_PULSE, + STATE_BIT_SPACE, + STATE_TRAILER_PULSE, + STATE_ECHO_SPACE, + STATE_TRAILER_SPACE, +}; + +/** + * ir_sharp_decode() - Decode one Sharp pulse or space + * @dev: the struct rc_dev descriptor of the device + * @duration: the struct ir_raw_event descriptor of the pulse/space + * + * This function returns -EINVAL if the pulse violates the state machine + */ +static int ir_sharp_decode(struct rc_dev *dev, struct ir_raw_event ev) +{ + struct sharp_dec *data = &dev->raw->sharp; + u32 msg, echo, address, command, scancode; + + if (!(dev->enabled_protocols & RC_BIT_SHARP)) + return 0; + + if (!is_timing_event(ev)) { + if (ev.reset) + data->state = STATE_INACTIVE; + return 0; + } + + IR_dprintk(2, "Sharp decode started at state %d (%uus %s)\n", + data->state, TO_US(ev.duration), TO_STR(ev.pulse)); + + switch (data->state) { + + case STATE_INACTIVE: + if (!ev.pulse) + break; + + if (!eq_margin(ev.duration, SHARP_BIT_PULSE, + SHARP_BIT_PULSE / 2)) + break; + + data->count = 0; + data->pulse_len = ev.duration; + data->state = STATE_BIT_SPACE; + return 0; + + case STATE_BIT_PULSE: + if (!ev.pulse) + break; + + if (!eq_margin(ev.duration, SHARP_BIT_PULSE, + SHARP_BIT_PULSE / 2)) + break; + + data->pulse_len = ev.duration; + data->state = STATE_BIT_SPACE; + return 0; + + case STATE_BIT_SPACE: + if (ev.pulse) + break; + + data->bits <<= 1; + if (eq_margin(data->pulse_len + ev.duration, SHARP_BIT_1_PERIOD, + SHARP_BIT_PULSE * 2)) + data->bits |= 1; + else if (!eq_margin(data->pulse_len + ev.duration, + SHARP_BIT_0_PERIOD, SHARP_BIT_PULSE * 2)) + break; + data->count++; + + if (data->count == SHARP_NBITS || + data->count == SHARP_NBITS * 2) + data->state = STATE_TRAILER_PULSE; + else + data->state = STATE_BIT_PULSE; + + return 0; + + case STATE_TRAILER_PULSE: + if (!ev.pulse) + break; + + if (!eq_margin(ev.duration, SHARP_BIT_PULSE, + SHARP_BIT_PULSE / 2)) + break; + + if (data->count == SHARP_NBITS) { + /* exp,chk bits should be 1,0 */ + if ((data->bits & 0x3) != 0x2) + break; + data->state = STATE_ECHO_SPACE; + } else { + data->state = STATE_TRAILER_SPACE; + } + return 0; + + case STATE_ECHO_SPACE: + if (ev.pulse) + break; + + if (!eq_margin(ev.duration, SHARP_ECHO_SPACE, + SHARP_ECHO_SPACE / 4)) + break; + + data->state = STATE_BIT_PULSE; + + return 0; + + case STATE_TRAILER_SPACE: + if (ev.pulse) + break; + + if (!geq_margin(ev.duration, SHARP_TRAILER_SPACE, + SHARP_BIT_PULSE / 2)) + break; + + /* Validate - command, ext, chk should be inverted in 2nd */ + msg = (data->bits >> 15) & 0x7fff; + echo = data->bits & 0x7fff; + if ((msg ^ echo) != 0x3ff) { + IR_dprintk(1, + "Sharp checksum error: received 0x%04x, 0x%04x\n", + msg, echo); + break; + } + + address = bitrev8((msg >> 7) & 0xf8); + command = bitrev8((msg >> 2) & 0xff); + + scancode = address << 8 | command; + IR_dprintk(1, "Sharp scancode 0x%04x\n", scancode); + + rc_keydown(dev, scancode, 0); + data->state = STATE_INACTIVE; + return 0; + } + + IR_dprintk(1, "Sharp decode failed at count %d state %d (%uus %s)\n", + data->count, data->state, TO_US(ev.duration), + TO_STR(ev.pulse)); + data->state = STATE_INACTIVE; + return -EINVAL; +} + +static struct ir_raw_handler sharp_handler = { + .protocols = RC_BIT_SHARP, + .decode = ir_sharp_decode, +}; + +static int __init ir_sharp_decode_init(void) +{ + ir_raw_handler_register(&sharp_handler); + + pr_info("IR Sharp protocol handler initialized\n"); + return 0; +} + +static void __exit ir_sharp_decode_exit(void) +{ + ir_raw_handler_unregister(&sharp_handler); +} + +module_init(ir_sharp_decode_init); +module_exit(ir_sharp_decode_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("James Hogan "); +MODULE_DESCRIPTION("Sharp IR protocol decoder"); diff --git a/drivers/media/rc/rc-core-priv.h b/drivers/media/rc/rc-core-priv.h index 70a180b..c40d666 100644 --- a/drivers/media/rc/rc-core-priv.h +++ b/drivers/media/rc/rc-core-priv.h @@ -88,6 +88,12 @@ struct ir_raw_event_ctrl { unsigned count; u64 bits; } sanyo; + struct sharp_dec { + int state; + unsigned count; + u32 bits; + unsigned int pulse_len; + } sharp; struct mce_kbd_dec { struct input_dev *idev; struct timer_list rx_timeout; -- cgit v1.1 From 01ae3b51af7144ea29eb28ba718b65ad59ab9493 Mon Sep 17 00:00:00 2001 From: Frank Schaefer Date: Fri, 17 Jan 2014 14:18:42 -0300 Subject: [media] em28xx-audio: fix user counting in snd_em28xx_capture_open() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit dev->adev.users always needs to be increased when snd_em28xx_capture_open() is called and succeeds. Signed-off-by: Frank Schäfer Cc: stable@vger.kernel.org Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/em28xx/em28xx-audio.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/media/usb/em28xx/em28xx-audio.c b/drivers/media/usb/em28xx/em28xx-audio.c index 05e9bd1..dfdfa77 100644 --- a/drivers/media/usb/em28xx/em28xx-audio.c +++ b/drivers/media/usb/em28xx/em28xx-audio.c @@ -252,7 +252,7 @@ static int snd_em28xx_capture_open(struct snd_pcm_substream *substream) { struct em28xx *dev = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; - int ret = 0; + int nonblock, ret = 0; if (!dev) { em28xx_err("BUG: em28xx can't find device struct." @@ -265,15 +265,15 @@ static int snd_em28xx_capture_open(struct snd_pcm_substream *substream) dprintk("opening device and trying to acquire exclusive lock\n"); + nonblock = !!(substream->f_flags & O_NONBLOCK); + if (nonblock) { + if (!mutex_trylock(&dev->lock)) + return -EAGAIN; + } else + mutex_lock(&dev->lock); + runtime->hw = snd_em28xx_hw_capture; if ((dev->alt == 0 || dev->is_audio_only) && dev->adev.users == 0) { - int nonblock = !!(substream->f_flags & O_NONBLOCK); - - if (nonblock) { - if (!mutex_trylock(&dev->lock)) - return -EAGAIN; - } else - mutex_lock(&dev->lock); if (dev->is_audio_only) /* vendor audio is on a separate interface */ dev->alt = 1; @@ -299,11 +299,11 @@ static int snd_em28xx_capture_open(struct snd_pcm_substream *substream) ret = em28xx_audio_analog_set(dev); if (ret < 0) goto err; - - dev->adev.users++; - mutex_unlock(&dev->lock); } + dev->adev.users++; + mutex_unlock(&dev->lock); + /* Dynamically adjust the period size */ snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, -- cgit v1.1 From 103f18a27d06839f07a62f923feeee2d71bf2909 Mon Sep 17 00:00:00 2001 From: Frank Schaefer Date: Fri, 17 Jan 2014 14:45:30 -0300 Subject: [media] em28xx-video: do not unregister the v4l2 dummy clock before v4l2_device_unregister() has been called MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Otherwiese the core refuses to unregister the clock and the following warning appears in the system log: "WARNING: ... at drivers/media/v4l2-core/v4l2-clk.c:231 v4l2_clk_unregister+0x8a/0x90 [videodev]() v4l2_clk_unregister(): Refusing to unregister ref-counted 11-0030:mclk clock!" Signed-off-by: Frank Schäfer Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/em28xx/em28xx-video.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/media/usb/em28xx/em28xx-video.c b/drivers/media/usb/em28xx/em28xx-video.c index c3c9289..09e18da 100644 --- a/drivers/media/usb/em28xx/em28xx-video.c +++ b/drivers/media/usb/em28xx/em28xx-video.c @@ -1918,14 +1918,14 @@ static int em28xx_v4l2_fini(struct em28xx *dev) video_unregister_device(dev->vdev); } + v4l2_ctrl_handler_free(&dev->ctrl_handler); + v4l2_device_unregister(&dev->v4l2_dev); + if (dev->clk) { v4l2_clk_unregister_fixed(dev->clk); dev->clk = NULL; } - v4l2_ctrl_handler_free(&dev->ctrl_handler); - v4l2_device_unregister(&dev->v4l2_dev); - if (dev->users) em28xx_warn("Device is open ! Memory deallocation is deferred on last close.\n"); mutex_unlock(&dev->lock); -- cgit v1.1 From cb497c75fd6ba3c4fb922d1f1b68746f426257a9 Mon Sep 17 00:00:00 2001 From: Frank Schaefer Date: Fri, 17 Jan 2014 14:45:31 -0300 Subject: [media] em28xx-camera: fix return value checks on sensor probing MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since commit e63b009d6e the returned error code in case of not connected/responding i2c clients is ENXIO isntead of ENODEV, which causes several error messages on sensor probing. Fix the i2c return value checks on sensor probing to silence these warnings. Signed-off-by: Frank Schäfer Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/em28xx/em28xx-camera.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/media/usb/em28xx/em28xx-camera.c b/drivers/media/usb/em28xx/em28xx-camera.c index c29f5c4..505e050 100644 --- a/drivers/media/usb/em28xx/em28xx-camera.c +++ b/drivers/media/usb/em28xx/em28xx-camera.c @@ -120,7 +120,7 @@ static int em28xx_probe_sensor_micron(struct em28xx *dev) reg = 0x00; ret = i2c_master_send(&client, ®, 1); if (ret < 0) { - if (ret != -ENODEV) + if (ret != -ENXIO) em28xx_errdev("couldn't read from i2c device 0x%02x: error %i\n", client.addr << 1, ret); continue; @@ -218,7 +218,7 @@ static int em28xx_probe_sensor_omnivision(struct em28xx *dev) reg = 0x1c; ret = i2c_smbus_read_byte_data(&client, reg); if (ret < 0) { - if (ret != -ENODEV) + if (ret != -ENXIO) em28xx_errdev("couldn't read from i2c device 0x%02x: error %i\n", client.addr << 1, ret); continue; -- cgit v1.1 From d86bc65a64e1e1536d9f5f3287f8707997b4e8fc Mon Sep 17 00:00:00 2001 From: Frank Schaefer Date: Fri, 17 Jan 2014 14:45:32 -0300 Subject: [media] em28xx-v4l: do not call em28xx_init_camera() if the device has no sensor MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This avoids the unnecessary temporary registration of a dummy V4L2 clock. Signed-off-by: Frank Schäfer Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/em28xx/em28xx-video.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/media/usb/em28xx/em28xx-video.c b/drivers/media/usb/em28xx/em28xx-video.c index 09e18da..2775c90 100644 --- a/drivers/media/usb/em28xx/em28xx-video.c +++ b/drivers/media/usb/em28xx/em28xx-video.c @@ -2273,7 +2273,8 @@ static int em28xx_v4l2_init(struct em28xx *dev) } em28xx_tuner_setup(dev); - em28xx_init_camera(dev); + if (dev->em28xx_sensor != EM28XX_NOSENSOR) + em28xx_init_camera(dev); /* Configure audio */ ret = em28xx_audio_setup(dev); -- cgit v1.1 From 8ae8cd6c3e2519128224c2fce0dbfd7a9e32c66c Mon Sep 17 00:00:00 2001 From: Frank Schaefer Date: Sun, 19 Jan 2014 18:48:34 -0300 Subject: [media] em28xx-i2c: fix the i2c error description strings for -ENXIO MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit d845fb3ae5 "em28xx-i2c: add timeout debug information if i2c_debug enabled" has added wrong error descriptions for -ENXIO. The strings are also missing terminating newline characters, which breaks the output format. Signed-off-by: Frank Schäfer Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/em28xx/em28xx-i2c.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/media/usb/em28xx/em28xx-i2c.c b/drivers/media/usb/em28xx/em28xx-i2c.c index 7e17240..bd8101d 100644 --- a/drivers/media/usb/em28xx/em28xx-i2c.c +++ b/drivers/media/usb/em28xx/em28xx-i2c.c @@ -81,7 +81,7 @@ static int em2800_i2c_send_bytes(struct em28xx *dev, u8 addr, u8 *buf, u16 len) return len; if (ret == 0x94 + len - 1) { if (i2c_debug == 1) - em28xx_warn("R05 returned 0x%02x: I2C timeout", + em28xx_warn("R05 returned 0x%02x: I2C ACK error\n", ret); return -ENXIO; } @@ -128,7 +128,7 @@ static int em2800_i2c_recv_bytes(struct em28xx *dev, u8 addr, u8 *buf, u16 len) break; if (ret == 0x94 + len - 1) { if (i2c_debug == 1) - em28xx_warn("R05 returned 0x%02x: I2C timeout", + em28xx_warn("R05 returned 0x%02x: I2C ACK error\n", ret); return -ENXIO; } @@ -210,7 +210,7 @@ static int em28xx_i2c_send_bytes(struct em28xx *dev, u16 addr, u8 *buf, return len; if (ret == 0x10) { if (i2c_debug == 1) - em28xx_warn("I2C transfer timeout on writing to addr 0x%02x", + em28xx_warn("I2C ACK error on writing to addr 0x%02x\n", addr); return -ENXIO; } @@ -274,7 +274,7 @@ static int em28xx_i2c_recv_bytes(struct em28xx *dev, u16 addr, u8 *buf, u16 len) } if (ret == 0x10) { if (i2c_debug == 1) - em28xx_warn("I2C transfer timeout on writing to addr 0x%02x", + em28xx_warn("I2C ACK error on writing to addr 0x%02x\n", addr); return -ENXIO; } @@ -337,7 +337,7 @@ static int em25xx_bus_B_send_bytes(struct em28xx *dev, u16 addr, u8 *buf, return len; else if (ret > 0) { if (i2c_debug == 1) - em28xx_warn("Bus B R08 returned 0x%02x: I2C timeout", + em28xx_warn("Bus B R08 returned 0x%02x: I2C ACK error\n", ret); return -ENXIO; } @@ -392,7 +392,7 @@ static int em25xx_bus_B_recv_bytes(struct em28xx *dev, u16 addr, u8 *buf, return len; else if (ret > 0) { if (i2c_debug == 1) - em28xx_warn("Bus B R08 returned 0x%02x: I2C timeout", + em28xx_warn("Bus B R08 returned 0x%02x: I2C ACK error\n", ret); return -ENXIO; } -- cgit v1.1 From 123a17d1427a2d7ad9142df1f6543c578864a0dd Mon Sep 17 00:00:00 2001 From: Frank Schaefer Date: Sun, 19 Jan 2014 18:48:35 -0300 Subject: [media] em28xx-i2c: fix the error code for unknown errors MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit e63b009d6e "em28xx-i2c: Fix error code for I2C error transfers" changed the code to return -ETIMEDOUT on all unknown errors. But the proper error code for unknown errors is -EIO. So only report -ETIMEDOUT in case of the errors 0x02 and 0x04, which are according to Mauro Carvalho Chehab's tests related to i2c clock stretching and return -EIO for the rest. Signed-off-by: Frank Schäfer Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/em28xx/em28xx-i2c.c | 29 +++++++++++++++++++++++------ 1 file changed, 23 insertions(+), 6 deletions(-) diff --git a/drivers/media/usb/em28xx/em28xx-i2c.c b/drivers/media/usb/em28xx/em28xx-i2c.c index bd8101d..ba6433c 100644 --- a/drivers/media/usb/em28xx/em28xx-i2c.c +++ b/drivers/media/usb/em28xx/em28xx-i2c.c @@ -226,10 +226,18 @@ static int em28xx_i2c_send_bytes(struct em28xx *dev, u16 addr, u8 *buf, * (even with high payload) ... */ } - if (i2c_debug) - em28xx_warn("write to i2c device at 0x%x timed out (status=%i)\n", - addr, ret); - return -ETIMEDOUT; + + if (ret == 0x02 || ret == 0x04) { + /* NOTE: these errors seem to be related to clock stretching */ + if (i2c_debug) + em28xx_warn("write to i2c device at 0x%x timed out (status=%i)\n", + addr, ret); + return -ETIMEDOUT; + } + + em28xx_warn("write to i2c device at 0x%x failed with unknown error (status=%i)\n", + addr, ret); + return -EIO; } /* @@ -279,8 +287,17 @@ static int em28xx_i2c_recv_bytes(struct em28xx *dev, u16 addr, u8 *buf, u16 len) return -ENXIO; } - em28xx_warn("unknown i2c error (status=%i)\n", ret); - return -ETIMEDOUT; + if (ret == 0x02 || ret == 0x04) { + /* NOTE: these errors seem to be related to clock stretching */ + if (i2c_debug) + em28xx_warn("write to i2c device at 0x%x timed out (status=%i)\n", + addr, ret); + return -ETIMEDOUT; + } + + em28xx_warn("write to i2c device at 0x%x failed with unknown error (status=%i)\n", + addr, ret); + return -EIO; } /* -- cgit v1.1 From dd3a5a1e7a8723b137f2af7905db53f011fd7287 Mon Sep 17 00:00:00 2001 From: Sean Young Date: Mon, 20 Jan 2014 19:10:38 -0300 Subject: [media] iguanair: explain tx carrier setup Just comments. No functional changes. Signed-off-by: Sean Young Signed-off-by: Mauro Carvalho Chehab --- drivers/media/rc/iguanair.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/drivers/media/rc/iguanair.c b/drivers/media/rc/iguanair.c index fdae05c..99a3a5a 100644 --- a/drivers/media/rc/iguanair.c +++ b/drivers/media/rc/iguanair.c @@ -286,10 +286,10 @@ static int iguanair_receiver(struct iguanair *ir, bool enable) } /* - * The iguana ir creates the carrier by busy spinning after each pulse or - * space. This is counted in CPU cycles, with the CPU running at 24MHz. It is + * The iguanair creates the carrier by busy spinning after each half period. + * This is counted in CPU cycles, with the CPU running at 24MHz. It is * broken down into 7-cycles and 4-cyles delays, with a preference for - * 4-cycle delays. + * 4-cycle delays, minus the overhead of the loop itself (cycle_overhead). */ static int iguanair_set_tx_carrier(struct rc_dev *dev, uint32_t carrier) { @@ -316,7 +316,14 @@ static int iguanair_set_tx_carrier(struct rc_dev *dev, uint32_t carrier) sevens = (4 - cycles) & 3; fours = (cycles - sevens * 7) / 4; - /* magic happens here */ + /* + * The firmware interprets these values as a relative offset + * for a branch. Immediately following the branches, there + * 4 instructions of 7 cycles (2 bytes each) and 110 + * instructions of 4 cycles (1 byte each). A relative branch + * of 0 will execute all of them, branch further for less + * cycle burning. + */ ir->packet->busy7 = (4 - sevens) * 2; ir->packet->busy4 = 110 - fours; } -- cgit v1.1 From 776eced0e336f88fdbe4374306de1f8acaeffcc4 Mon Sep 17 00:00:00 2001 From: Sean Young Date: Mon, 20 Jan 2014 19:10:39 -0300 Subject: [media] iguanair: simplify tx loop Make the code simpler. Signed-off-by: Sean Young Signed-off-by: Mauro Carvalho Chehab --- drivers/media/rc/iguanair.c | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/drivers/media/rc/iguanair.c b/drivers/media/rc/iguanair.c index 99a3a5a..a83519a 100644 --- a/drivers/media/rc/iguanair.c +++ b/drivers/media/rc/iguanair.c @@ -364,20 +364,14 @@ static int iguanair_tx(struct rc_dev *dev, unsigned *txbuf, unsigned count) rc = -EINVAL; goto out; } - while (periods > 127) { - ir->packet->payload[size++] = 127 | space; - periods -= 127; + while (periods) { + unsigned p = min(periods, 127u); + ir->packet->payload[size++] = p | space; + periods -= p; } - - ir->packet->payload[size++] = periods | space; space ^= 0x80; } - if (count == 0) { - rc = -EINVAL; - goto out; - } - ir->packet->header.start = 0; ir->packet->header.direction = DIR_OUT; ir->packet->header.cmd = CMD_SEND; -- cgit v1.1 From 6b4a16c36400143efe4b693bbdf65c0367b7e1ac Mon Sep 17 00:00:00 2001 From: Sean Young Date: Mon, 20 Jan 2014 19:10:44 -0300 Subject: [media] mceusb: improve error logging A number of recent bug reports involve usb_submit_urb() failing which was only reported with debug parameter on. In addition, remove custom debug function. [m.chehab@samsung.com: patch rebased, as one of the patches on this series need changes] Signed-off-by: Sean Young Signed-off-by: Mauro Carvalho Chehab --- drivers/media/rc/mceusb.c | 182 ++++++++++++++++++++++------------------------ 1 file changed, 85 insertions(+), 97 deletions(-) diff --git a/drivers/media/rc/mceusb.c b/drivers/media/rc/mceusb.c index a25bb15..c01b4c1 100644 --- a/drivers/media/rc/mceusb.c +++ b/drivers/media/rc/mceusb.c @@ -84,7 +84,7 @@ #define MCE_PORT_IR 0x4 /* (0x4 << 5) | MCE_CMD = 0x9f */ #define MCE_PORT_SYS 0x7 /* (0x7 << 5) | MCE_CMD = 0xff */ #define MCE_PORT_SER 0x6 /* 0xc0 thru 0xdf flush & 0x1f bytes */ -#define MCE_PORT_MASK 0xe0 /* Mask out command bits */ +#define MCE_PORT_MASK 0xe0 /* Mask out command bits */ /* Command port headers */ #define MCE_CMD_PORT_IR 0x9f /* IR-related cmd/rsp */ @@ -153,19 +153,6 @@ #define MCE_COMMAND_IRDATA 0x80 #define MCE_PACKET_LENGTH_MASK 0x1f /* Packet length mask */ -/* module parameters */ -#ifdef CONFIG_USB_DEBUG -static bool debug = 1; -#else -static bool debug; -#endif - -#define mce_dbg(dev, fmt, ...) \ - do { \ - if (debug) \ - dev_info(dev, fmt, ## __VA_ARGS__); \ - } while (0) - /* general constants */ #define SEND_FLAG_IN_PROGRESS 1 #define SEND_FLAG_COMPLETE 2 @@ -541,16 +528,13 @@ static int mceusb_cmd_datasize(u8 cmd, u8 subcmd) static void mceusb_dev_printdata(struct mceusb_dev *ir, char *buf, int offset, int len, bool out) { - char codes[USB_BUFLEN * 3 + 1]; - char inout[9]; +#if defined(DEBUG) || defined(CONFIG_DYNAMIC_DEBUG) + char *inout; u8 cmd, subcmd, data1, data2, data3, data4; struct device *dev = ir->dev; - int i, start, skip = 0; + int start, skip = 0; u32 carrier, period; - if (!debug) - return; - /* skip meaningless 0xb1 0x60 header bytes on orig receiver */ if (ir->flags.microsoft_gen1 && !out && !offset) skip = 2; @@ -558,16 +542,10 @@ static void mceusb_dev_printdata(struct mceusb_dev *ir, char *buf, if (len <= skip) return; - for (i = 0; i < len && i < USB_BUFLEN; i++) - snprintf(codes + i * 3, 4, "%02x ", buf[i + offset] & 0xff); - - dev_info(dev, "%sx data: %s(length=%d)\n", - (out ? "t" : "r"), codes, len); + dev_dbg(dev, "%cx data: %*ph (length=%d)", + (out ? 't' : 'r'), min(len, USB_BUFLEN), buf, len); - if (out) - strcpy(inout, "Request\0"); - else - strcpy(inout, "Got\0"); + inout = out ? "Request" : "Got"; start = offset + skip; cmd = buf[start] & 0xff; @@ -583,50 +561,50 @@ static void mceusb_dev_printdata(struct mceusb_dev *ir, char *buf, break; if ((subcmd == MCE_CMD_PORT_SYS) && (data1 == MCE_CMD_RESUME)) - dev_info(dev, "Device resume requested\n"); + dev_dbg(dev, "Device resume requested"); else - dev_info(dev, "Unknown command 0x%02x 0x%02x\n", + dev_dbg(dev, "Unknown command 0x%02x 0x%02x", cmd, subcmd); break; case MCE_CMD_PORT_SYS: switch (subcmd) { case MCE_RSP_EQEMVER: if (!out) - dev_info(dev, "Emulator interface version %x\n", + dev_dbg(dev, "Emulator interface version %x", data1); break; case MCE_CMD_G_REVISION: if (len == 2) - dev_info(dev, "Get hw/sw rev?\n"); + dev_dbg(dev, "Get hw/sw rev?"); else - dev_info(dev, "hw/sw rev 0x%02x 0x%02x " - "0x%02x 0x%02x\n", data1, data2, + dev_dbg(dev, "hw/sw rev 0x%02x 0x%02x 0x%02x 0x%02x", + data1, data2, buf[start + 4], buf[start + 5]); break; case MCE_CMD_RESUME: - dev_info(dev, "Device resume requested\n"); + dev_dbg(dev, "Device resume requested"); break; case MCE_RSP_CMD_ILLEGAL: - dev_info(dev, "Illegal PORT_SYS command\n"); + dev_dbg(dev, "Illegal PORT_SYS command"); break; case MCE_RSP_EQWAKEVERSION: if (!out) - dev_info(dev, "Wake version, proto: 0x%02x, " + dev_dbg(dev, "Wake version, proto: 0x%02x, " "payload: 0x%02x, address: 0x%02x, " - "version: 0x%02x\n", + "version: 0x%02x", data1, data2, data3, data4); break; case MCE_RSP_GETPORTSTATUS: if (!out) /* We use data1 + 1 here, to match hw labels */ - dev_info(dev, "TX port %d: blaster is%s connected\n", + dev_dbg(dev, "TX port %d: blaster is%s connected", data1 + 1, data4 ? " not" : ""); break; case MCE_CMD_FLASHLED: - dev_info(dev, "Attempting to flash LED\n"); + dev_dbg(dev, "Attempting to flash LED"); break; default: - dev_info(dev, "Unknown command 0x%02x 0x%02x\n", + dev_dbg(dev, "Unknown command 0x%02x 0x%02x", cmd, subcmd); break; } @@ -634,13 +612,13 @@ static void mceusb_dev_printdata(struct mceusb_dev *ir, char *buf, case MCE_CMD_PORT_IR: switch (subcmd) { case MCE_CMD_SIG_END: - dev_info(dev, "End of signal\n"); + dev_dbg(dev, "End of signal"); break; case MCE_CMD_PING: - dev_info(dev, "Ping\n"); + dev_dbg(dev, "Ping"); break; case MCE_CMD_UNKNOWN: - dev_info(dev, "Resp to 9f 05 of 0x%02x 0x%02x\n", + dev_dbg(dev, "Resp to 9f 05 of 0x%02x 0x%02x", data1, data2); break; case MCE_RSP_EQIRCFS: @@ -649,51 +627,51 @@ static void mceusb_dev_printdata(struct mceusb_dev *ir, char *buf, if (!period) break; carrier = (1000 * 1000) / period; - dev_info(dev, "%s carrier of %u Hz (period %uus)\n", + dev_dbg(dev, "%s carrier of %u Hz (period %uus)", inout, carrier, period); break; case MCE_CMD_GETIRCFS: - dev_info(dev, "Get carrier mode and freq\n"); + dev_dbg(dev, "Get carrier mode and freq"); break; case MCE_RSP_EQIRTXPORTS: - dev_info(dev, "%s transmit blaster mask of 0x%02x\n", + dev_dbg(dev, "%s transmit blaster mask of 0x%02x", inout, data1); break; case MCE_RSP_EQIRTIMEOUT: /* value is in units of 50us, so x*50/1000 ms */ period = ((data1 << 8) | data2) * MCE_TIME_UNIT / 1000; - dev_info(dev, "%s receive timeout of %d ms\n", + dev_dbg(dev, "%s receive timeout of %d ms", inout, period); break; case MCE_CMD_GETIRTIMEOUT: - dev_info(dev, "Get receive timeout\n"); + dev_dbg(dev, "Get receive timeout"); break; case MCE_CMD_GETIRTXPORTS: - dev_info(dev, "Get transmit blaster mask\n"); + dev_dbg(dev, "Get transmit blaster mask"); break; case MCE_RSP_EQIRRXPORTEN: - dev_info(dev, "%s %s-range receive sensor in use\n", + dev_dbg(dev, "%s %s-range receive sensor in use", inout, data1 == 0x02 ? "short" : "long"); break; case MCE_CMD_GETIRRXPORTEN: /* aka MCE_RSP_EQIRRXCFCNT */ if (out) - dev_info(dev, "Get receive sensor\n"); + dev_dbg(dev, "Get receive sensor"); else if (ir->learning_enabled) - dev_info(dev, "RX pulse count: %d\n", + dev_dbg(dev, "RX pulse count: %d", ((data1 << 8) | data2)); break; case MCE_RSP_EQIRNUMPORTS: if (out) break; - dev_info(dev, "Num TX ports: %x, num RX ports: %x\n", + dev_dbg(dev, "Num TX ports: %x, num RX ports: %x", data1, data2); break; case MCE_RSP_CMD_ILLEGAL: - dev_info(dev, "Illegal PORT_IR command\n"); + dev_dbg(dev, "Illegal PORT_IR command"); break; default: - dev_info(dev, "Unknown command 0x%02x 0x%02x\n", + dev_dbg(dev, "Unknown command 0x%02x 0x%02x", cmd, subcmd); break; } @@ -703,10 +681,11 @@ static void mceusb_dev_printdata(struct mceusb_dev *ir, char *buf, } if (cmd == MCE_IRDATA_TRAILER) - dev_info(dev, "End of raw IR data\n"); + dev_dbg(dev, "End of raw IR data"); else if ((cmd != MCE_CMD_PORT_IR) && ((cmd & MCE_PORT_MASK) == MCE_COMMAND_IRDATA)) - dev_info(dev, "Raw IR data, %d pulse/space samples\n", ir->rem); + dev_dbg(dev, "Raw IR data, %d pulse/space samples", ir->rem); +#endif } static void mce_async_callback(struct urb *urb) @@ -718,10 +697,25 @@ static void mce_async_callback(struct urb *urb) return; ir = urb->context; - if (ir) { + + switch (urb->status) { + /* success */ + case 0: len = urb->actual_length; mceusb_dev_printdata(ir, urb->transfer_buffer, 0, len, true); + break; + + case -ECONNRESET: + case -ENOENT: + case -EILSEQ: + case -ESHUTDOWN: + break; + + case -EPIPE: + default: + dev_err(ir->dev, "Error: request urb status = %d", urb->status); + break; } /* the transfer buffer and urb were allocated in mce_request_packet */ @@ -770,17 +764,17 @@ static void mce_request_packet(struct mceusb_dev *ir, unsigned char *data, return; } - mce_dbg(dev, "receive request called (size=%#x)\n", size); + dev_dbg(dev, "receive request called (size=%#x)", size); async_urb->transfer_buffer_length = size; async_urb->dev = ir->usbdev; res = usb_submit_urb(async_urb, GFP_ATOMIC); if (res) { - mce_dbg(dev, "receive request FAILED! (res=%d)\n", res); + dev_err(dev, "receive request FAILED! (res=%d)", res); return; } - mce_dbg(dev, "receive request complete (res=%d)\n", res); + dev_dbg(dev, "receive request complete (res=%d)", res); } static void mce_async_out(struct mceusb_dev *ir, unsigned char *data, int size) @@ -895,8 +889,7 @@ static int mceusb_set_tx_carrier(struct rc_dev *dev, u32 carrier) ir->carrier = carrier; cmdbuf[2] = MCE_CMD_SIG_END; cmdbuf[3] = MCE_IRDATA_TRAILER; - mce_dbg(ir->dev, "%s: disabling carrier " - "modulation\n", __func__); + dev_dbg(ir->dev, "disabling carrier modulation"); mce_async_out(ir, cmdbuf, sizeof(cmdbuf)); return carrier; } @@ -907,8 +900,8 @@ static int mceusb_set_tx_carrier(struct rc_dev *dev, u32 carrier) ir->carrier = carrier; cmdbuf[2] = prescaler; cmdbuf[3] = divisor; - mce_dbg(ir->dev, "%s: requesting %u HZ " - "carrier\n", __func__, carrier); + dev_dbg(ir->dev, "requesting %u HZ carrier", + carrier); /* Transmit new carrier to mce device */ mce_async_out(ir, cmdbuf, sizeof(cmdbuf)); @@ -998,7 +991,7 @@ static void mceusb_process_ir_data(struct mceusb_dev *ir, int buf_len) rawir.duration = (ir->buf_in[i] & MCE_PULSE_MASK) * US_TO_NS(MCE_TIME_UNIT); - mce_dbg(ir->dev, "Storing %s with duration %d\n", + dev_dbg(ir->dev, "Storing %s with duration %d", rawir.pulse ? "pulse" : "space", rawir.duration); @@ -1032,7 +1025,7 @@ static void mceusb_process_ir_data(struct mceusb_dev *ir, int buf_len) ir->parser_state = CMD_HEADER; } if (event) { - mce_dbg(ir->dev, "processed IR data, calling ir_raw_event_handle\n"); + dev_dbg(ir->dev, "processed IR data"); ir_raw_event_handle(ir->rc); } } @@ -1055,7 +1048,7 @@ static void mceusb_dev_recv(struct urb *urb) if (ir->send_flags == RECV_FLAG_IN_PROGRESS) { ir->send_flags = SEND_FLAG_COMPLETE; - mce_dbg(ir->dev, "setup answer received %d bytes\n", + dev_dbg(ir->dev, "setup answer received %d bytes\n", buf_len); } @@ -1067,13 +1060,14 @@ static void mceusb_dev_recv(struct urb *urb) case -ECONNRESET: case -ENOENT: + case -EILSEQ: case -ESHUTDOWN: usb_unlink_urb(urb); return; case -EPIPE: default: - mce_dbg(ir->dev, "Error: urb status = %d\n", urb->status); + dev_err(ir->dev, "Error: urb status = %d", urb->status); break; } @@ -1095,7 +1089,7 @@ static void mceusb_gen1_init(struct mceusb_dev *ir) data = kzalloc(USB_CTRL_MSG_SZ, GFP_KERNEL); if (!data) { - dev_err(dev, "%s: memory allocation failed!\n", __func__); + dev_err(dev, "%s: memory allocation failed!", __func__); return; } @@ -1106,28 +1100,28 @@ static void mceusb_gen1_init(struct mceusb_dev *ir) ret = usb_control_msg(ir->usbdev, usb_rcvctrlpipe(ir->usbdev, 0), USB_REQ_SET_ADDRESS, USB_TYPE_VENDOR, 0, 0, data, USB_CTRL_MSG_SZ, HZ * 3); - mce_dbg(dev, "%s - ret = %d\n", __func__, ret); - mce_dbg(dev, "%s - data[0] = %d, data[1] = %d\n", - __func__, data[0], data[1]); + dev_dbg(dev, "set address - ret = %d", ret); + dev_dbg(dev, "set address - data[0] = %d, data[1] = %d", + data[0], data[1]); /* set feature: bit rate 38400 bps */ ret = usb_control_msg(ir->usbdev, usb_sndctrlpipe(ir->usbdev, 0), USB_REQ_SET_FEATURE, USB_TYPE_VENDOR, 0xc04e, 0x0000, NULL, 0, HZ * 3); - mce_dbg(dev, "%s - ret = %d\n", __func__, ret); + dev_dbg(dev, "set feature - ret = %d", ret); /* bRequest 4: set char length to 8 bits */ ret = usb_control_msg(ir->usbdev, usb_sndctrlpipe(ir->usbdev, 0), 4, USB_TYPE_VENDOR, 0x0808, 0x0000, NULL, 0, HZ * 3); - mce_dbg(dev, "%s - retB = %d\n", __func__, ret); + dev_dbg(dev, "set char length - retB = %d", ret); /* bRequest 2: set handshaking to use DTR/DSR */ ret = usb_control_msg(ir->usbdev, usb_sndctrlpipe(ir->usbdev, 0), 2, USB_TYPE_VENDOR, 0x0000, 0x0100, NULL, 0, HZ * 3); - mce_dbg(dev, "%s - retC = %d\n", __func__, ret); + dev_dbg(dev, "set handshake - retC = %d", ret); /* device resume */ mce_async_out(ir, DEVICE_RESUME, sizeof(DEVICE_RESUME)); @@ -1198,7 +1192,7 @@ static struct rc_dev *mceusb_init_rc_dev(struct mceusb_dev *ir) rc = rc_allocate_device(); if (!rc) { - dev_err(dev, "remote dev allocation failed\n"); + dev_err(dev, "remote dev allocation failed"); goto out; } @@ -1230,7 +1224,7 @@ static struct rc_dev *mceusb_init_rc_dev(struct mceusb_dev *ir) ret = rc_register_device(rc); if (ret < 0) { - dev_err(dev, "remote dev registration failed\n"); + dev_err(dev, "remote dev registration failed"); goto out; } @@ -1258,7 +1252,7 @@ static int mceusb_dev_probe(struct usb_interface *intf, bool tx_mask_normal; int ir_intfnum; - mce_dbg(&intf->dev, "%s called\n", __func__); + dev_dbg(&intf->dev, "%s called", __func__); idesc = intf->cur_altsetting; @@ -1286,8 +1280,7 @@ static int mceusb_dev_probe(struct usb_interface *intf, ep_in = ep; ep_in->bmAttributes = USB_ENDPOINT_XFER_INT; ep_in->bInterval = 1; - mce_dbg(&intf->dev, "acceptable inbound endpoint " - "found\n"); + dev_dbg(&intf->dev, "acceptable inbound endpoint found"); } if ((ep_out == NULL) @@ -1301,12 +1294,11 @@ static int mceusb_dev_probe(struct usb_interface *intf, ep_out = ep; ep_out->bmAttributes = USB_ENDPOINT_XFER_INT; ep_out->bInterval = 1; - mce_dbg(&intf->dev, "acceptable outbound endpoint " - "found\n"); + dev_dbg(&intf->dev, "acceptable outbound endpoint found"); } } if (ep_in == NULL) { - mce_dbg(&intf->dev, "inbound and/or endpoint not found\n"); + dev_dbg(&intf->dev, "inbound and/or endpoint not found"); return -ENODEV; } @@ -1357,7 +1349,7 @@ static int mceusb_dev_probe(struct usb_interface *intf, ir->urb_in->transfer_flags |= URB_NO_TRANSFER_DMA_MAP; /* flush buffers on the device */ - mce_dbg(&intf->dev, "Flushing receive buffers\n"); + dev_dbg(&intf->dev, "Flushing receive buffers\n"); mce_flush_rx_buffer(ir, maxp); /* figure out which firmware/emulator version this hardware has */ @@ -1382,10 +1374,9 @@ static int mceusb_dev_probe(struct usb_interface *intf, device_set_wakeup_capable(ir->dev, true); device_set_wakeup_enable(ir->dev, true); - dev_info(&intf->dev, "Registered %s with mce emulator interface " - "version %x\n", name, ir->emver); - dev_info(&intf->dev, "%x tx ports (0x%x cabled) and " - "%x rx sensors (0x%x active)\n", + dev_info(&intf->dev, "Registered %s with mce emulator interface version %x", + name, ir->emver); + dev_info(&intf->dev, "%x tx ports (0x%x cabled) and %x rx sensors (0x%x active)", ir->num_txports, ir->txports_cabled, ir->num_rxports, ir->rxports_active); @@ -1399,7 +1390,7 @@ urb_in_alloc_fail: buf_in_alloc_fail: kfree(ir); mem_alloc_fail: - dev_err(&intf->dev, "%s: device setup failed!\n", __func__); + dev_err(&intf->dev, "%s: device setup failed!", __func__); return -ENOMEM; } @@ -1427,7 +1418,7 @@ static void mceusb_dev_disconnect(struct usb_interface *intf) static int mceusb_dev_suspend(struct usb_interface *intf, pm_message_t message) { struct mceusb_dev *ir = usb_get_intfdata(intf); - dev_info(ir->dev, "suspend\n"); + dev_info(ir->dev, "suspend"); usb_kill_urb(ir->urb_in); return 0; } @@ -1435,7 +1426,7 @@ static int mceusb_dev_suspend(struct usb_interface *intf, pm_message_t message) static int mceusb_dev_resume(struct usb_interface *intf) { struct mceusb_dev *ir = usb_get_intfdata(intf); - dev_info(ir->dev, "resume\n"); + dev_info(ir->dev, "resume"); if (usb_submit_urb(ir->urb_in, GFP_ATOMIC)) return -EIO; return 0; @@ -1457,6 +1448,3 @@ MODULE_DESCRIPTION(DRIVER_DESC); MODULE_AUTHOR(DRIVER_AUTHOR); MODULE_LICENSE("GPL"); MODULE_DEVICE_TABLE(usb, mceusb_dev_table); - -module_param(debug, bool, S_IRUGO | S_IWUSR); -MODULE_PARM_DESC(debug, "Debug enabled or not"); -- cgit v1.1 From 8d2b022911c2fa72085df39921dc5cd963bc159f Mon Sep 17 00:00:00 2001 From: Joakim Hernberg Date: Fri, 31 Jan 2014 07:15:48 -0300 Subject: [media] cx23885: Fix tuning regression for TeVii S471 When tuning to 10818V on Astra 28E2, the system tunes to 11343V instead. This is a regression in the S471 driver introduced with the changeset: b43ea8068d2090cb1e44632c8a938ab40d2c7419 [media] cx23885: Fix TeVii S471 regression since introduction of ts2020. Suggested-by: Mauro Carvalho Chehab Signed-off-by: Joakim Hernberg Tested-by: Mark Clarkstone Signed-off-by: Mauro Carvalho Chehab --- drivers/media/pci/cx23885/cx23885-dvb.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/media/pci/cx23885/cx23885-dvb.c b/drivers/media/pci/cx23885/cx23885-dvb.c index 0549205..4be01b3 100644 --- a/drivers/media/pci/cx23885/cx23885-dvb.c +++ b/drivers/media/pci/cx23885/cx23885-dvb.c @@ -473,6 +473,7 @@ static struct ds3000_config tevii_ds3000_config = { static struct ts2020_config tevii_ts2020_config = { .tuner_address = 0x60, .clk_out_div = 1, + .frequency_div = 1146000, }; static struct cx24116_config dvbworld_cx24116_config = { -- cgit v1.1 From dee88f4378d18b4e7ebca22c82dab2ed5dfd178c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Antti=20Sepp=C3=A4l=C3=A4?= Date: Sat, 25 Jan 2014 06:57:46 -0300 Subject: [media] nuvoton-cir: Don't touch PS/2 interrupts while initializing MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There are reports[1] that on some motherboards loading the nuvoton-cir disables PS/2 keyboard input. This is caused by an erroneous write of CIR_INTR_MOUSE_IRQ_BIT to ACPI control register. According to datasheet the write enables mouse power management event interrupts which will probably have ill effects if the motherboard has only one PS/2 port with keyboard in it. The cir hardware does not need mouse interrupts to function and should not touch them. This patch removes the illegal writes and registry definitions. [1] http://ubuntuforums.org/showthread.php?t=2106277&p=12461912&mode=threaded#post12461912 Reported-by: Bruno Maire Tested-by: Bruno Maire Signed-off-by: Antti Seppälä Acked-by: Jarod Wilson Signed-off-by: Mauro Carvalho Chehab --- drivers/media/rc/nuvoton-cir.c | 4 ---- drivers/media/rc/nuvoton-cir.h | 1 - 2 files changed, 5 deletions(-) diff --git a/drivers/media/rc/nuvoton-cir.c b/drivers/media/rc/nuvoton-cir.c index 21ee0dc..b41e52e 100644 --- a/drivers/media/rc/nuvoton-cir.c +++ b/drivers/media/rc/nuvoton-cir.c @@ -330,9 +330,6 @@ static void nvt_cir_wake_ldev_init(struct nvt_dev *nvt) /* Enable CIR Wake via PSOUT# (Pin60) */ nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE); - /* enable cir interrupt of mouse/keyboard IRQ event */ - nvt_set_reg_bit(nvt, CIR_INTR_MOUSE_IRQ_BIT, CR_ACPI_IRQ_EVENTS); - /* enable pme interrupt of cir wakeup event */ nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2); @@ -456,7 +453,6 @@ static void nvt_enable_wake(struct nvt_dev *nvt) nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI); nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE); - nvt_set_reg_bit(nvt, CIR_INTR_MOUSE_IRQ_BIT, CR_ACPI_IRQ_EVENTS); nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2); nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE); diff --git a/drivers/media/rc/nuvoton-cir.h b/drivers/media/rc/nuvoton-cir.h index 07e8310..e1cf23c 100644 --- a/drivers/media/rc/nuvoton-cir.h +++ b/drivers/media/rc/nuvoton-cir.h @@ -363,7 +363,6 @@ struct nvt_dev { #define LOGICAL_DEV_ENABLE 0x01 #define CIR_WAKE_ENABLE_BIT 0x08 -#define CIR_INTR_MOUSE_IRQ_BIT 0x80 #define PME_INTR_CIR_PASS_BIT 0x08 /* w83677hg CIR pin config */ -- cgit v1.1 From 261cb200e7227820cd0056435d7c1a3a9c476766 Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Sat, 1 Feb 2014 11:30:50 -0300 Subject: [media] af9035: add ID [2040:f900] Hauppauge WinTV-MiniStick 2 Add USB ID [2040:f900] for Hauppauge WinTV-MiniStick 2. Device is build upon IT9135 chipset. Tested-by: Stefan Becker Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/dvb-usb-v2/af9035.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/media/usb/dvb-usb-v2/af9035.c b/drivers/media/usb/dvb-usb-v2/af9035.c index 8f9b2cea..8ede8ea 100644 --- a/drivers/media/usb/dvb-usb-v2/af9035.c +++ b/drivers/media/usb/dvb-usb-v2/af9035.c @@ -1539,6 +1539,8 @@ static const struct usb_device_id af9035_id_table[] = { &af9035_props, "TerraTec Cinergy T Stick Dual RC (rev. 2)", NULL) }, { DVB_USB_DEVICE(USB_VID_LEADTEK, 0x6a05, &af9035_props, "Leadtek WinFast DTV Dongle Dual", NULL) }, + { DVB_USB_DEVICE(USB_VID_HAUPPAUGE, 0xf900, + &af9035_props, "Hauppauge WinTV-MiniStick 2", NULL) }, { } }; MODULE_DEVICE_TABLE(usb, af9035_id_table); -- cgit v1.1 From 324a6673a8635f050b68d78066ba25a2a17c2817 Mon Sep 17 00:00:00 2001 From: James Hogan Date: Wed, 5 Feb 2014 19:15:16 -0300 Subject: [media] rc: ir-raw: Load ir-sharp-decoder module at init Commit 1d184b0bc13d ([media] media: rc: add raw decoder for Sharp protocol) added a new raw IR decoder for the sharp protocol, but didn't add the code to load the module at init as is done for other raw decoders, so add that code now. Signed-off-by: James Hogan Signed-off-by: Mauro Carvalho Chehab --- drivers/media/rc/ir-raw.c | 1 + drivers/media/rc/rc-core-priv.h | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/drivers/media/rc/ir-raw.c b/drivers/media/rc/ir-raw.c index 5c42750..79a9cb6 100644 --- a/drivers/media/rc/ir-raw.c +++ b/drivers/media/rc/ir-raw.c @@ -352,6 +352,7 @@ void ir_raw_init(void) load_jvc_decode(); load_sony_decode(); load_sanyo_decode(); + load_sharp_decode(); load_mce_kbd_decode(); load_lirc_codec(); diff --git a/drivers/media/rc/rc-core-priv.h b/drivers/media/rc/rc-core-priv.h index c40d666..dc3b0b7 100644 --- a/drivers/media/rc/rc-core-priv.h +++ b/drivers/media/rc/rc-core-priv.h @@ -210,6 +210,13 @@ static inline void load_sony_decode(void) { } static inline void load_sanyo_decode(void) { } #endif +/* from ir-sharp-decoder.c */ +#ifdef CONFIG_IR_SHARP_DECODER_MODULE +#define load_sharp_decode() request_module_nowait("ir-sharp-decoder") +#else +static inline void load_sharp_decode(void) { } +#endif + /* from ir-mce_kbd-decoder.c */ #ifdef CONFIG_IR_MCE_KBD_DECODER_MODULE #define load_mce_kbd_decode() request_module_nowait("ir-mce_kbd-decoder") -- cgit v1.1 From 00942d1a1bd93ac108c1b92d504c568a37be1833 Mon Sep 17 00:00:00 2001 From: James Hogan Date: Fri, 17 Jan 2014 10:58:49 -0300 Subject: [media] media: rc: add sysfs scancode filtering interface Add and document a generic sysfs based scancode filtering interface for making use of IR data matching hardware to filter out uninteresting scancodes. Two filters exist, one for normal operation and one for filtering scancodes which are permitted to wake the system from suspend. The following files are added to /sys/class/rc/rc?/: - filter: normal scancode filter value - filter_mask: normal scancode filter mask - wakeup_filter: wakeup scancode filter value - wakeup_filter_mask: wakeup scancode filter mask A new s_filter() driver callback is added which must arrange for the specified filter to be applied at the right time. Drivers can convert the scancode filter into a raw IR data filter, which can be applied immediately or later (for wake up filters). Signed-off-by: James Hogan Cc: Mauro Carvalho Chehab Cc: linux-media@vger.kernel.org Cc: Rob Landley Cc: linux-doc@vger.kernel.org Signed-off-by: Mauro Carvalho Chehab --- Documentation/ABI/testing/sysfs-class-rc | 58 +++++++++++++ drivers/media/rc/rc-main.c | 136 +++++++++++++++++++++++++++++++ include/media/rc-core.h | 29 +++++++ 3 files changed, 223 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-class-rc b/Documentation/ABI/testing/sysfs-class-rc index 52bc057..c0e1d14 100644 --- a/Documentation/ABI/testing/sysfs-class-rc +++ b/Documentation/ABI/testing/sysfs-class-rc @@ -32,3 +32,61 @@ Description: Writing "none" will disable all protocols. Write fails with EINVAL if an invalid protocol combination or unknown protocol name is used. + +What: /sys/class/rc/rcN/filter +Date: Jan 2014 +KernelVersion: 3.15 +Contact: Mauro Carvalho Chehab +Description: + Sets the scancode filter expected value. + Use in combination with /sys/class/rc/rcN/filter_mask to set the + expected value of the bits set in the filter mask. + If the hardware supports it then scancodes which do not match + the filter will be ignored. Otherwise the write will fail with + an error. + This value may be reset to 0 if the current protocol is altered. + +What: /sys/class/rc/rcN/filter_mask +Date: Jan 2014 +KernelVersion: 3.15 +Contact: Mauro Carvalho Chehab +Description: + Sets the scancode filter mask of bits to compare. + Use in combination with /sys/class/rc/rcN/filter to set the bits + of the scancode which should be compared against the expected + value. A value of 0 disables the filter to allow all valid + scancodes to be processed. + If the hardware supports it then scancodes which do not match + the filter will be ignored. Otherwise the write will fail with + an error. + This value may be reset to 0 if the current protocol is altered. + +What: /sys/class/rc/rcN/wakeup_filter +Date: Jan 2014 +KernelVersion: 3.15 +Contact: Mauro Carvalho Chehab +Description: + Sets the scancode wakeup filter expected value. + Use in combination with /sys/class/rc/rcN/wakeup_filter_mask to + set the expected value of the bits set in the wakeup filter mask + to trigger a system wake event. + If the hardware supports it and wakeup_filter_mask is not 0 then + scancodes which match the filter will wake the system from e.g. + suspend to RAM or power off. + Otherwise the write will fail with an error. + This value may be reset to 0 if the current protocol is altered. + +What: /sys/class/rc/rcN/wakeup_filter_mask +Date: Jan 2014 +KernelVersion: 3.15 +Contact: Mauro Carvalho Chehab +Description: + Sets the scancode wakeup filter mask of bits to compare. + Use in combination with /sys/class/rc/rcN/wakeup_filter to set + the bits of the scancode which should be compared against the + expected value to trigger a system wake event. + If the hardware supports it and wakeup_filter_mask is not 0 then + scancodes which match the filter will wake the system from e.g. + suspend to RAM or power off. + Otherwise the write will fail with an error. + This value may be reset to 0 if the current protocol is altered. diff --git a/drivers/media/rc/rc-main.c b/drivers/media/rc/rc-main.c index f1b67db..fa8b957 100644 --- a/drivers/media/rc/rc-main.c +++ b/drivers/media/rc/rc-main.c @@ -969,6 +969,130 @@ out: return ret; } +/** + * struct rc_filter_attribute - Device attribute relating to a filter type. + * @attr: Device attribute. + * @type: Filter type. + * @mask: false for filter value, true for filter mask. + */ +struct rc_filter_attribute { + struct device_attribute attr; + enum rc_filter_type type; + bool mask; +}; +#define to_rc_filter_attr(a) container_of(a, struct rc_filter_attribute, attr) + +#define RC_FILTER_ATTR(_name, _mode, _show, _store, _type, _mask) \ + struct rc_filter_attribute dev_attr_##_name = { \ + .attr = __ATTR(_name, _mode, _show, _store), \ + .type = (_type), \ + .mask = (_mask), \ + } + +/** + * show_filter() - shows the current scancode filter value or mask + * @device: the device descriptor + * @attr: the device attribute struct + * @buf: a pointer to the output buffer + * + * This routine is a callback routine to read a scancode filter value or mask. + * It is trigged by reading /sys/class/rc/rc?/[wakeup_]filter[_mask]. + * It prints the current scancode filter value or mask of the appropriate filter + * type in hexadecimal into @buf and returns the size of the buffer. + * + * Bits of the filter value corresponding to set bits in the filter mask are + * compared against input scancodes and non-matching scancodes are discarded. + * + * dev->lock is taken to guard against races between device registration, + * store_filter and show_filter. + */ +static ssize_t show_filter(struct device *device, + struct device_attribute *attr, + char *buf) +{ + struct rc_dev *dev = to_rc_dev(device); + struct rc_filter_attribute *fattr = to_rc_filter_attr(attr); + u32 val; + + /* Device is being removed */ + if (!dev) + return -EINVAL; + + mutex_lock(&dev->lock); + if (!dev->s_filter) + val = 0; + else if (fattr->mask) + val = dev->scancode_filters[fattr->type].mask; + else + val = dev->scancode_filters[fattr->type].data; + mutex_unlock(&dev->lock); + + return sprintf(buf, "%#x\n", val); +} + +/** + * store_filter() - changes the scancode filter value + * @device: the device descriptor + * @attr: the device attribute struct + * @buf: a pointer to the input buffer + * @len: length of the input buffer + * + * This routine is for changing a scancode filter value or mask. + * It is trigged by writing to /sys/class/rc/rc?/[wakeup_]filter[_mask]. + * Returns -EINVAL if an invalid filter value for the current protocol was + * specified or if scancode filtering is not supported by the driver, otherwise + * returns @len. + * + * Bits of the filter value corresponding to set bits in the filter mask are + * compared against input scancodes and non-matching scancodes are discarded. + * + * dev->lock is taken to guard against races between device registration, + * store_filter and show_filter. + */ +static ssize_t store_filter(struct device *device, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + struct rc_dev *dev = to_rc_dev(device); + struct rc_filter_attribute *fattr = to_rc_filter_attr(attr); + struct rc_scancode_filter local_filter, *filter; + int ret; + unsigned long val; + + /* Device is being removed */ + if (!dev) + return -EINVAL; + + ret = kstrtoul(buf, 0, &val); + if (ret < 0) + return ret; + + /* Scancode filter not supported (but still accept 0) */ + if (!dev->s_filter) + return val ? -EINVAL : count; + + mutex_lock(&dev->lock); + + /* Tell the driver about the new filter */ + filter = &dev->scancode_filters[fattr->type]; + local_filter = *filter; + if (fattr->mask) + local_filter.mask = val; + else + local_filter.data = val; + ret = dev->s_filter(dev, fattr->type, &local_filter); + if (ret < 0) + goto unlock; + + /* Success, commit the new filter */ + *filter = local_filter; + +unlock: + mutex_unlock(&dev->lock); + return count; +} + static void rc_dev_release(struct device *device) { } @@ -1000,9 +1124,21 @@ static int rc_dev_uevent(struct device *device, struct kobj_uevent_env *env) */ static DEVICE_ATTR(protocols, S_IRUGO | S_IWUSR, show_protocols, store_protocols); +static RC_FILTER_ATTR(filter, S_IRUGO|S_IWUSR, + show_filter, store_filter, RC_FILTER_NORMAL, false); +static RC_FILTER_ATTR(filter_mask, S_IRUGO|S_IWUSR, + show_filter, store_filter, RC_FILTER_NORMAL, true); +static RC_FILTER_ATTR(wakeup_filter, S_IRUGO|S_IWUSR, + show_filter, store_filter, RC_FILTER_WAKEUP, false); +static RC_FILTER_ATTR(wakeup_filter_mask, S_IRUGO|S_IWUSR, + show_filter, store_filter, RC_FILTER_WAKEUP, true); static struct attribute *rc_dev_attrs[] = { &dev_attr_protocols.attr, + &dev_attr_filter.attr.attr, + &dev_attr_filter_mask.attr.attr, + &dev_attr_wakeup_filter.attr.attr, + &dev_attr_wakeup_filter_mask.attr.attr, NULL, }; diff --git a/include/media/rc-core.h b/include/media/rc-core.h index 2f6f1f7..4a72176 100644 --- a/include/media/rc-core.h +++ b/include/media/rc-core.h @@ -35,6 +35,29 @@ enum rc_driver_type { }; /** + * struct rc_scancode_filter - Filter scan codes. + * @data: Scancode data to match. + * @mask: Mask of bits of scancode to compare. + */ +struct rc_scancode_filter { + u32 data; + u32 mask; +}; + +/** + * enum rc_filter_type - Filter type constants. + * @RC_FILTER_NORMAL: Filter for normal operation. + * @RC_FILTER_WAKEUP: Filter for waking from suspend. + * @RC_FILTER_MAX: Number of filter types. + */ +enum rc_filter_type { + RC_FILTER_NORMAL = 0, + RC_FILTER_WAKEUP, + + RC_FILTER_MAX +}; + +/** * struct rc_dev - represents a remote control device * @dev: driver model's view of this device * @input_name: name of the input child device @@ -70,6 +93,7 @@ enum rc_driver_type { * @max_timeout: maximum timeout supported by device * @rx_resolution : resolution (in ns) of input sampler * @tx_resolution: resolution (in ns) of output sampler + * @scancode_filters: scancode filters (indexed by enum rc_filter_type) * @change_protocol: allow changing the protocol used on hardware decoders * @open: callback to allow drivers to enable polling/irq when IR input device * is opened. @@ -84,6 +108,7 @@ enum rc_driver_type { * device doesn't interrupt host until it sees IR pulses * @s_learning_mode: enable wide band receiver used for learning * @s_carrier_report: enable carrier reports + * @s_filter: set the scancode filter of a given type */ struct rc_dev { struct device dev; @@ -116,6 +141,7 @@ struct rc_dev { u32 max_timeout; u32 rx_resolution; u32 tx_resolution; + struct rc_scancode_filter scancode_filters[RC_FILTER_MAX]; int (*change_protocol)(struct rc_dev *dev, u64 *rc_type); int (*open)(struct rc_dev *dev); void (*close)(struct rc_dev *dev); @@ -127,6 +153,9 @@ struct rc_dev { void (*s_idle)(struct rc_dev *dev, bool enable); int (*s_learning_mode)(struct rc_dev *dev, int enable); int (*s_carrier_report) (struct rc_dev *dev, int enable); + int (*s_filter)(struct rc_dev *dev, + enum rc_filter_type type, + struct rc_scancode_filter *filter); }; #define to_rc_dev(d) container_of(d, struct rc_dev, dev) -- cgit v1.1 From 18bc17448147e93f31cc9b1a83be49f1224657b2 Mon Sep 17 00:00:00 2001 From: James Hogan Date: Fri, 17 Jan 2014 10:58:50 -0300 Subject: [media] media: rc: change 32bit NEC scancode format Change 32bit NEC scancode format (used by Apple and TiVo remotes) to encode the data with the correct bit order. Previously the raw bits were used without being bit reversed, now each 16bit half is bit reversed compared to before. So for the raw NEC data: (LSB/First) 0xAAaaCCcc (MSB/Last) (where traditionally AA=address, aa=~address, CC=command, cc=~command) We now generate the scancodes: (MSB) 0x0000AACC (LSB) (normal NEC) (MSB) 0x00AAaaCC (LSB) (extended NEC, address check wrong) (MSB) 0xaaAAccCC (LSB) (32-bit NEC, command check wrong) Note that the address byte order in 32-bit NEC scancodes is different to that of the extended NEC scancodes. I chose this way as it maintains the order of the bits in the address/command fields, and CC is clearly intended to be the LSB of the command if the TiVo codes are anything to go by so it makes sense for AA to also be the LSB. The TiVo keymap is updated accordingly. Signed-off-by: James Hogan Cc: Mauro Carvalho Chehab Cc: Jarod Wilson Cc: linux-media@vger.kernel.org Signed-off-by: Mauro Carvalho Chehab --- drivers/media/rc/ir-nec-decoder.c | 5 ++- drivers/media/rc/keymaps/rc-tivo.c | 86 +++++++++++++++++++------------------- 2 files changed, 47 insertions(+), 44 deletions(-) diff --git a/drivers/media/rc/ir-nec-decoder.c b/drivers/media/rc/ir-nec-decoder.c index 9a90094..1bab7ea 100644 --- a/drivers/media/rc/ir-nec-decoder.c +++ b/drivers/media/rc/ir-nec-decoder.c @@ -172,7 +172,10 @@ static int ir_nec_decode(struct rc_dev *dev, struct ir_raw_event ev) if (send_32bits) { /* NEC transport, but modified protocol, used by at * least Apple and TiVo remotes */ - scancode = data->bits; + scancode = not_address << 24 | + address << 16 | + not_command << 8 | + command; IR_dprintk(1, "NEC (modified) scancode 0x%08x\n", scancode); } else if ((address ^ not_address) != 0xff) { /* Extended NEC */ diff --git a/drivers/media/rc/keymaps/rc-tivo.c b/drivers/media/rc/keymaps/rc-tivo.c index 454e062..5cc1b45 100644 --- a/drivers/media/rc/keymaps/rc-tivo.c +++ b/drivers/media/rc/keymaps/rc-tivo.c @@ -15,62 +15,62 @@ * Initial mapping is for the TiVo remote included in the Nero LiquidTV bundle, * which also ships with a TiVo-branded IR transceiver, supported by the mceusb * driver. Note that the remote uses an NEC-ish protocol, but instead of having - * a command/not_command pair, it has a vendor ID of 0xa10c, but some keys, the + * a command/not_command pair, it has a vendor ID of 0x3085, but some keys, the * NEC extended checksums do pass, so the table presently has the intended * values and the checksum-passed versions for those keys. */ static struct rc_map_table tivo[] = { - { 0xa10c900f, KEY_MEDIA }, /* TiVo Button */ - { 0xa10c0807, KEY_POWER2 }, /* TV Power */ - { 0xa10c8807, KEY_TV }, /* Live TV/Swap */ - { 0xa10c2c03, KEY_VIDEO_NEXT }, /* TV Input */ - { 0xa10cc807, KEY_INFO }, - { 0xa10cfa05, KEY_CYCLEWINDOWS }, /* Window */ + { 0x3085f009, KEY_MEDIA }, /* TiVo Button */ + { 0x3085e010, KEY_POWER2 }, /* TV Power */ + { 0x3085e011, KEY_TV }, /* Live TV/Swap */ + { 0x3085c034, KEY_VIDEO_NEXT }, /* TV Input */ + { 0x3085e013, KEY_INFO }, + { 0x3085a05f, KEY_CYCLEWINDOWS }, /* Window */ { 0x0085305f, KEY_CYCLEWINDOWS }, - { 0xa10c6c03, KEY_EPG }, /* Guide */ + { 0x3085c036, KEY_EPG }, /* Guide */ - { 0xa10c2807, KEY_UP }, - { 0xa10c6807, KEY_DOWN }, - { 0xa10ce807, KEY_LEFT }, - { 0xa10ca807, KEY_RIGHT }, + { 0x3085e014, KEY_UP }, + { 0x3085e016, KEY_DOWN }, + { 0x3085e017, KEY_LEFT }, + { 0x3085e015, KEY_RIGHT }, - { 0xa10c1807, KEY_SCROLLDOWN }, /* Red Thumbs Down */ - { 0xa10c9807, KEY_SELECT }, - { 0xa10c5807, KEY_SCROLLUP }, /* Green Thumbs Up */ + { 0x3085e018, KEY_SCROLLDOWN }, /* Red Thumbs Down */ + { 0x3085e019, KEY_SELECT }, + { 0x3085e01a, KEY_SCROLLUP }, /* Green Thumbs Up */ - { 0xa10c3807, KEY_VOLUMEUP }, - { 0xa10cb807, KEY_VOLUMEDOWN }, - { 0xa10cd807, KEY_MUTE }, - { 0xa10c040b, KEY_RECORD }, - { 0xa10c7807, KEY_CHANNELUP }, - { 0xa10cf807, KEY_CHANNELDOWN }, + { 0x3085e01c, KEY_VOLUMEUP }, + { 0x3085e01d, KEY_VOLUMEDOWN }, + { 0x3085e01b, KEY_MUTE }, + { 0x3085d020, KEY_RECORD }, + { 0x3085e01e, KEY_CHANNELUP }, + { 0x3085e01f, KEY_CHANNELDOWN }, { 0x0085301f, KEY_CHANNELDOWN }, - { 0xa10c840b, KEY_PLAY }, - { 0xa10cc40b, KEY_PAUSE }, - { 0xa10ca40b, KEY_SLOW }, - { 0xa10c440b, KEY_REWIND }, - { 0xa10c240b, KEY_FASTFORWARD }, - { 0xa10c640b, KEY_PREVIOUS }, - { 0xa10ce40b, KEY_NEXT }, /* ->| */ + { 0x3085d021, KEY_PLAY }, + { 0x3085d023, KEY_PAUSE }, + { 0x3085d025, KEY_SLOW }, + { 0x3085d022, KEY_REWIND }, + { 0x3085d024, KEY_FASTFORWARD }, + { 0x3085d026, KEY_PREVIOUS }, + { 0x3085d027, KEY_NEXT }, /* ->| */ - { 0xa10c220d, KEY_ZOOM }, /* Aspect */ - { 0xa10c120d, KEY_STOP }, - { 0xa10c520d, KEY_DVD }, /* DVD Menu */ + { 0x3085b044, KEY_ZOOM }, /* Aspect */ + { 0x3085b048, KEY_STOP }, + { 0x3085b04a, KEY_DVD }, /* DVD Menu */ - { 0xa10c140b, KEY_NUMERIC_1 }, - { 0xa10c940b, KEY_NUMERIC_2 }, - { 0xa10c540b, KEY_NUMERIC_3 }, - { 0xa10cd40b, KEY_NUMERIC_4 }, - { 0xa10c340b, KEY_NUMERIC_5 }, - { 0xa10cb40b, KEY_NUMERIC_6 }, - { 0xa10c740b, KEY_NUMERIC_7 }, - { 0xa10cf40b, KEY_NUMERIC_8 }, + { 0x3085d028, KEY_NUMERIC_1 }, + { 0x3085d029, KEY_NUMERIC_2 }, + { 0x3085d02a, KEY_NUMERIC_3 }, + { 0x3085d02b, KEY_NUMERIC_4 }, + { 0x3085d02c, KEY_NUMERIC_5 }, + { 0x3085d02d, KEY_NUMERIC_6 }, + { 0x3085d02e, KEY_NUMERIC_7 }, + { 0x3085d02f, KEY_NUMERIC_8 }, { 0x0085302f, KEY_NUMERIC_8 }, - { 0xa10c0c03, KEY_NUMERIC_9 }, - { 0xa10c8c03, KEY_NUMERIC_0 }, - { 0xa10ccc03, KEY_ENTER }, - { 0xa10c4c03, KEY_CLEAR }, + { 0x3085c030, KEY_NUMERIC_9 }, + { 0x3085c031, KEY_NUMERIC_0 }, + { 0x3085c033, KEY_ENTER }, + { 0x3085c032, KEY_CLEAR }, }; static struct rc_map_list tivo_map = { -- cgit v1.1 From 90f745cea2190d42d2ee10eab6cddad526d6e521 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Thu, 6 Feb 2014 10:55:28 -0200 Subject: [media] DocBook/media_api: Better organize the DocBook All chapters/parts but Remote controllers have the revision tags inside the body. Move those to remote_controllers.xml and do some cleanup. No functional changes. Signed-off-by: Mauro Carvalho Chehab --- .../DocBook/media/v4l/remote_controllers.xml | 31 +++++++++ Documentation/DocBook/media_api.tmpl | 81 +++++----------------- 2 files changed, 50 insertions(+), 62 deletions(-) diff --git a/Documentation/DocBook/media/v4l/remote_controllers.xml b/Documentation/DocBook/media/v4l/remote_controllers.xml index 160e464..18288a3 100644 --- a/Documentation/DocBook/media/v4l/remote_controllers.xml +++ b/Documentation/DocBook/media/v4l/remote_controllers.xml @@ -1,4 +1,34 @@ + + + +Mauro +Chehab +Carvalho +
m.chehab@samsung.com
 +Initial version. + + + + 2009-2014 + Mauro Carvalho Chehab + + + + + +1.0.0 +2009-09-06 +mcc +Initial revision + + + + + Remote Controller API + + Remote Controllers +
Introduction @@ -175,3 +205,4 @@ keymapping.
&sub-lirc_device_interface; + diff --git a/Documentation/DocBook/media_api.tmpl b/Documentation/DocBook/media_api.tmpl index ba1d704..4decb46 100644 --- a/Documentation/DocBook/media_api.tmpl +++ b/Documentation/DocBook/media_api.tmpl @@ -34,22 +34,20 @@ -LINUX MEDIA INFRASTRUCTURE API - - - 2009-2014 - LinuxTV Developers - - - - -Permission is granted to copy, distribute and/or modify -this document under the terms of the GNU Free Documentation License, -Version 1.1 or any later version published by the Free Software -Foundation. A copy of the license is included in the chapter entitled -"GNU Free Documentation License" - - + LINUX MEDIA INFRASTRUCTURE API + + + 2009-2014 + LinuxTV Developers + + + + Permission is granted to copy, distribute and/or modify + this document under the terms of the GNU Free Documentation License, + Version 1.1 or any later version published by the Free Software + Foundation. A copy of the license is included in the chapter entitled + "GNU Free Documentation License" + @@ -76,55 +74,14 @@ Foundation. A copy of the license is included in the chapter entitled For additional information and for the latest development code, see: http://linuxtv.org. For discussing improvements, reporting troubles, sending new drivers, etc, please mail to: Linux Media Mailing List (LMML).. - - -&sub-v4l2; - - -&sub-dvbapi; - - - - - -Mauro -Chehab -Carvalho -
m.chehab@samsung.com
 -Initial version. - - - - 2009-2014 - Mauro Carvalho Chehab - - - - - -1.0.0 -2009-09-06 -mcc -Initial revision - - - - -Remote Controller API - -&sub-remote_controllers; - - - -&sub-media-controller; - - - -&sub-gen-errors; - +&sub-v4l2; +&sub-dvbapi; +&sub-remote_controllers; +&sub-media-controller; +&sub-gen-errors; &sub-fdl-appendix; -- cgit v1.1 From 4195086571d49e6ad63087621d397c4a9eddd152 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Thu, 6 Feb 2014 10:08:57 -0200 Subject: [media] DocBook: Add a description for the Remote Controller interface Adds a missing section to describe the remote controller interface. The DocBook is just addin the same documentation as written at Documentation/ABI/testing/sysfs-class-rc, using the DocBook's way, and dropping timestamps/contact info. While that means that we'll have the same info on two parts, there are parts of the remote controller interface that doesn't belong at Documentation/ABI/, and it makes sense to have everything on the same place. This also means that we'll need to manually track to be sure that both places will be synchronized, but, as it is not expected much changes on it, this sync can be done manually. It also adds an introduction that states that the IR is a normal evdev/input interface, plus the sysfs class nodes. Signed-off-by: Mauro Carvalho Chehab --- .../DocBook/media/v4l/remote_controllers.xml | 98 +++++++++++++++++++++- 1 file changed, 97 insertions(+), 1 deletion(-) diff --git a/Documentation/DocBook/media/v4l/remote_controllers.xml b/Documentation/DocBook/media/v4l/remote_controllers.xml index 18288a3..c440a81 100644 --- a/Documentation/DocBook/media/v4l/remote_controllers.xml +++ b/Documentation/DocBook/media/v4l/remote_controllers.xml @@ -16,7 +16,13 @@ -1.0.0 +3.15 +2014-02-06 +mcc +Added the interface description and the RC sysfs class description. + + +1.0 2009-09-06 mcc Initial revision @@ -35,6 +41,96 @@ Currently, most analog and digital devices have a Infrared input for remote controllers. Each manufacturer has their own type of control. It is not rare for the same manufacturer to ship different types of controls, depending on the device. +A Remote Controller interface is mapped as a normal evdev/input interface, just like a keyboard or a mouse. +So, it uses all ioctls already defined for any other input devices. +However, remove controllers are more flexible than a normal input device, as the IR +receiver (and/or transmitter) can be used in conjunction with a wide variety of different IR remotes. +In order to allow flexibility, the Remote Controller subsystem allows controlling the +RC-specific attributes via the sysfs class nodes. +
+ +
+Remote Controller's sysfs nodes +As defined at Documentation/ABI/testing/sysfs-class-rc, those are the sysfs nodes that control the Remote Controllers: + +
+/sys/class/rc/ +The /sys/class/rc/ class sub-directory belongs to the Remote Controller +core and provides a sysfs interface for configuring infrared remote controller receivers. + + +
+
+/sys/class/rc/rcN/ +A /sys/class/rc/rcN directory is created for each remote + control receiver device where N is the number of the receiver. + +
+
+/sys/class/rc/rcN/protocols +Reading this file returns a list of available protocols, something like: +rc5 [rc6] nec jvc [sony] +Enabled protocols are shown in [] brackets. +Writing "+proto" will add a protocol to the list of enabled protocols. +Writing "-proto" will remove a protocol from the list of enabled protocols. +Writing "proto" will enable only "proto". +Writing "none" will disable all protocols. +Write fails with EINVAL if an invalid protocol combination or unknown protocol name is used. + +
+
+/sys/class/rc/rcN/filter +Sets the scancode filter expected value. +Use in combination with /sys/class/rc/rcN/filter_mask to set the +expected value of the bits set in the filter mask. +If the hardware supports it then scancodes which do not match +the filter will be ignored. Otherwise the write will fail with +an error. +This value may be reset to 0 if the current protocol is altered. + +
+
+/sys/class/rc/rcN/filter_mask +Sets the scancode filter mask of bits to compare. +Use in combination with /sys/class/rc/rcN/filter to set the bits +of the scancode which should be compared against the expected +value. A value of 0 disables the filter to allow all valid +scancodes to be processed. +If the hardware supports it then scancodes which do not match +the filter will be ignored. Otherwise the write will fail with +an error. +This value may be reset to 0 if the current protocol is altered. + +
+
+/sys/class/rc/rcN/wakeup_filter +Sets the scancode wakeup filter expected value. +Use in combination with /sys/class/rc/rcN/wakeup_filter_mask to +set the expected value of the bits set in the wakeup filter mask +to trigger a system wake event. +If the hardware supports it and wakeup_filter_mask is not 0 then +scancodes which match the filter will wake the system from e.g. +suspend to RAM or power off. +Otherwise the write will fail with an error. +This value may be reset to 0 if the current protocol is altered. + +
+
+/sys/class/rc/rcN/wakeup_filter_mask +Sets the scancode wakeup filter mask of bits to compare. +Use in combination with /sys/class/rc/rcN/wakeup_filter to set +the bits of the scancode which should be compared against the +expected value to trigger a system wake event. +If the hardware supports it and wakeup_filter_mask is not 0 then +scancodes which match the filter will wake the system from e.g. +suspend to RAM or power off. +Otherwise the write will fail with an error. +This value may be reset to 0 if the current protocol is altered. +
+
+ +
+Remote controller tables Unfortunately, for several years, there was no effort to create uniform IR keycodes for different devices. This caused the same IR keyname to be mapped completely differently on different IR devices. This resulted that the same IR keyname to be mapped completely different on -- cgit v1.1 From 37e59f876bc710d67a30b660826a5e83e07101ce Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Fri, 7 Feb 2014 08:03:07 -0200 Subject: [media, edac] Change my email address There are several left overs with my old email address. Remove their occurrences and add myself at CREDITS, to allow people to be able to reach me on my new addresses. Signed-off-by: Mauro Carvalho Chehab --- CREDITS | 7 +++++++ Documentation/edac.txt | 2 +- drivers/edac/edac_mc_sysfs.c | 2 +- drivers/edac/ghes_edac.c | 2 +- drivers/edac/i5400_edac.c | 4 ++-- drivers/edac/i7300_edac.c | 4 ++-- drivers/edac/i7core_edac.c | 4 ++-- drivers/edac/sb_edac.c | 4 ++-- drivers/media/common/siano/smsdvb-debugfs.c | 2 +- drivers/media/dvb-frontends/mb86a20s.c | 4 ++-- drivers/media/dvb-frontends/mb86a20s.h | 2 +- drivers/media/dvb-frontends/s921.c | 4 ++-- drivers/media/dvb-frontends/s921.h | 2 +- drivers/media/i2c/mt9v011.c | 4 ++-- drivers/media/i2c/sr030pc30.c | 2 +- drivers/media/rc/ir-nec-decoder.c | 4 ++-- drivers/media/rc/ir-raw.c | 2 +- drivers/media/rc/ir-rc5-decoder.c | 4 ++-- drivers/media/rc/ir-rc5-sz-decoder.c | 2 +- drivers/media/rc/ir-sanyo-decoder.c | 4 ++-- drivers/media/rc/ir-sharp-decoder.c | 2 +- drivers/media/rc/keymaps/rc-adstech-dvb-t-pci.c | 4 ++-- drivers/media/rc/keymaps/rc-apac-viewcomp.c | 4 ++-- drivers/media/rc/keymaps/rc-asus-pc39.c | 4 ++-- drivers/media/rc/keymaps/rc-asus-ps3-100.c | 4 ++-- drivers/media/rc/keymaps/rc-ati-tv-wonder-hd-600.c | 4 ++-- drivers/media/rc/keymaps/rc-avermedia-a16d.c | 4 ++-- drivers/media/rc/keymaps/rc-avermedia-cardbus.c | 4 ++-- drivers/media/rc/keymaps/rc-avermedia-dvbt.c | 4 ++-- drivers/media/rc/keymaps/rc-avermedia-m135a.c | 4 ++-- drivers/media/rc/keymaps/rc-avermedia-m733a-rm-k6.c | 2 +- drivers/media/rc/keymaps/rc-avermedia.c | 4 ++-- drivers/media/rc/keymaps/rc-avertv-303.c | 4 ++-- drivers/media/rc/keymaps/rc-behold-columbus.c | 4 ++-- drivers/media/rc/keymaps/rc-behold.c | 4 ++-- drivers/media/rc/keymaps/rc-budget-ci-old.c | 4 ++-- drivers/media/rc/keymaps/rc-cinergy-1400.c | 4 ++-- drivers/media/rc/keymaps/rc-cinergy.c | 4 ++-- drivers/media/rc/keymaps/rc-dib0700-nec.c | 4 ++-- drivers/media/rc/keymaps/rc-dib0700-rc5.c | 4 ++-- drivers/media/rc/keymaps/rc-dm1105-nec.c | 4 ++-- drivers/media/rc/keymaps/rc-dntv-live-dvb-t.c | 4 ++-- drivers/media/rc/keymaps/rc-dntv-live-dvbt-pro.c | 4 ++-- drivers/media/rc/keymaps/rc-em-terratec.c | 4 ++-- drivers/media/rc/keymaps/rc-encore-enltv-fm53.c | 4 ++-- drivers/media/rc/keymaps/rc-encore-enltv.c | 4 ++-- drivers/media/rc/keymaps/rc-encore-enltv2.c | 4 ++-- drivers/media/rc/keymaps/rc-evga-indtube.c | 4 ++-- drivers/media/rc/keymaps/rc-eztv.c | 4 ++-- drivers/media/rc/keymaps/rc-flydvb.c | 4 ++-- drivers/media/rc/keymaps/rc-flyvideo.c | 4 ++-- drivers/media/rc/keymaps/rc-fusionhdtv-mce.c | 4 ++-- drivers/media/rc/keymaps/rc-gadmei-rm008z.c | 4 ++-- drivers/media/rc/keymaps/rc-genius-tvgo-a11mce.c | 4 ++-- drivers/media/rc/keymaps/rc-gotview7135.c | 4 ++-- drivers/media/rc/keymaps/rc-hauppauge.c | 4 ++-- drivers/media/rc/keymaps/rc-iodata-bctv7e.c | 4 ++-- drivers/media/rc/keymaps/rc-kaiomy.c | 4 ++-- drivers/media/rc/keymaps/rc-kworld-315u.c | 4 ++-- drivers/media/rc/keymaps/rc-kworld-pc150u.c | 2 +- drivers/media/rc/keymaps/rc-kworld-plus-tv-analog.c | 4 ++-- drivers/media/rc/keymaps/rc-manli.c | 4 ++-- drivers/media/rc/keymaps/rc-msi-tvanywhere-plus.c | 4 ++-- drivers/media/rc/keymaps/rc-msi-tvanywhere.c | 4 ++-- drivers/media/rc/keymaps/rc-nebula.c | 4 ++-- drivers/media/rc/keymaps/rc-nec-terratec-cinergy-xs.c | 6 +++--- drivers/media/rc/keymaps/rc-norwood.c | 4 ++-- drivers/media/rc/keymaps/rc-npgtech.c | 4 ++-- drivers/media/rc/keymaps/rc-pctv-sedna.c | 4 ++-- drivers/media/rc/keymaps/rc-pinnacle-color.c | 4 ++-- drivers/media/rc/keymaps/rc-pinnacle-grey.c | 4 ++-- drivers/media/rc/keymaps/rc-pinnacle-pctv-hd.c | 4 ++-- drivers/media/rc/keymaps/rc-pixelview-002t.c | 4 ++-- drivers/media/rc/keymaps/rc-pixelview-mk12.c | 4 ++-- drivers/media/rc/keymaps/rc-pixelview-new.c | 4 ++-- drivers/media/rc/keymaps/rc-pixelview.c | 4 ++-- drivers/media/rc/keymaps/rc-powercolor-real-angel.c | 4 ++-- drivers/media/rc/keymaps/rc-proteus-2309.c | 4 ++-- drivers/media/rc/keymaps/rc-purpletv.c | 4 ++-- drivers/media/rc/keymaps/rc-pv951.c | 4 ++-- drivers/media/rc/keymaps/rc-real-audio-220-32-keys.c | 4 ++-- drivers/media/rc/keymaps/rc-tbs-nec.c | 4 ++-- drivers/media/rc/keymaps/rc-terratec-cinergy-xs.c | 4 ++-- drivers/media/rc/keymaps/rc-tevii-nec.c | 4 ++-- drivers/media/rc/keymaps/rc-tt-1500.c | 4 ++-- drivers/media/rc/keymaps/rc-videomate-s350.c | 4 ++-- drivers/media/rc/keymaps/rc-videomate-tv-pvr.c | 4 ++-- drivers/media/rc/keymaps/rc-winfast-usbii-deluxe.c | 4 ++-- drivers/media/rc/keymaps/rc-winfast.c | 4 ++-- drivers/media/rc/rc-core-priv.h | 2 +- drivers/media/rc/rc-main.c | 4 ++-- drivers/media/tuners/mt2063.c | 4 ++-- drivers/media/tuners/r820t.c | 4 ++-- drivers/media/usb/cx231xx/cx231xx-input.c | 2 +- drivers/media/usb/dvb-usb-v2/az6007.c | 4 ++-- drivers/media/usb/em28xx/em28xx-audio.c | 2 +- drivers/media/usb/em28xx/em28xx-input.c | 2 +- drivers/media/usb/tm6000/tm6000-alsa.c | 4 ++-- drivers/media/usb/tm6000/tm6000-dvb.c | 2 +- drivers/media/usb/tm6000/tm6000-stds.c | 2 +- include/media/rc-core.h | 2 +- include/media/rc-map.h | 2 +- 102 files changed, 190 insertions(+), 183 deletions(-) diff --git a/CREDITS b/CREDITS index e371c55..9f21a01 100644 --- a/CREDITS +++ b/CREDITS @@ -630,6 +630,13 @@ N: Michael Elizabeth Chastain E: mec@shout.net D: Configure, Menuconfig, xconfig +N: Mauro Carvalho Chehab +E: m.chehab@samsung.org +E: mchehab@infradead.org +D: Media subsystem (V4L/DVB) drivers and core +D: EDAC drivers and EDAC 3.0 core rework +S: Brazil + N: Raymond Chen E: raymondc@microsoft.com D: Author of Configure script diff --git a/Documentation/edac.txt b/Documentation/edac.txt index 56c7e93..cb4c2cef 100644 --- a/Documentation/edac.txt +++ b/Documentation/edac.txt @@ -6,7 +6,7 @@ Written by Doug Thompson 7 Dec 2005 17 Jul 2007 Updated -(c) Mauro Carvalho Chehab +(c) Mauro Carvalho Chehab 05 Aug 2009 Nehalem interface EDAC is maintained and written by: diff --git a/drivers/edac/edac_mc_sysfs.c b/drivers/edac/edac_mc_sysfs.c index 51c0362..3c0d673 100644 --- a/drivers/edac/edac_mc_sysfs.c +++ b/drivers/edac/edac_mc_sysfs.c @@ -7,7 +7,7 @@ * * Written Doug Thompson www.softwarebitmaker.com * - * (c) 2012-2013 - Mauro Carvalho Chehab + * (c) 2012-2013 - Mauro Carvalho Chehab * The entire API were re-written, and ported to use struct device * */ diff --git a/drivers/edac/ghes_edac.c b/drivers/edac/ghes_edac.c index d5a98a4..8399b4e 100644 --- a/drivers/edac/ghes_edac.c +++ b/drivers/edac/ghes_edac.c @@ -4,7 +4,7 @@ * This file may be distributed under the terms of the GNU General Public * License version 2. * - * Copyright (c) 2013 by Mauro Carvalho Chehab + * Copyright (c) 2013 by Mauro Carvalho Chehab * * Red Hat Inc. http://www.redhat.com */ diff --git a/drivers/edac/i5400_edac.c b/drivers/edac/i5400_edac.c index e080cbf..f189c33 100644 --- a/drivers/edac/i5400_edac.c +++ b/drivers/edac/i5400_edac.c @@ -6,7 +6,7 @@ * * Copyright (c) 2008 by: * Ben Woodard - * Mauro Carvalho Chehab + * Mauro Carvalho Chehab * * Red Hat Inc. http://www.redhat.com * @@ -1467,7 +1467,7 @@ module_exit(i5400_exit); MODULE_LICENSE("GPL"); MODULE_AUTHOR("Ben Woodard "); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)"); MODULE_DESCRIPTION("MC Driver for Intel I5400 memory controllers - " I5400_REVISION); diff --git a/drivers/edac/i7300_edac.c b/drivers/edac/i7300_edac.c index d63f479..aea80a5 100644 --- a/drivers/edac/i7300_edac.c +++ b/drivers/edac/i7300_edac.c @@ -5,7 +5,7 @@ * GNU General Public License version 2 only. * * Copyright (c) 2010 by: - * Mauro Carvalho Chehab + * Mauro Carvalho Chehab * * Red Hat Inc. http://www.redhat.com * @@ -1207,7 +1207,7 @@ module_init(i7300_init); module_exit(i7300_exit); MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)"); MODULE_DESCRIPTION("MC Driver for Intel I7300 memory controllers - " I7300_REVISION); diff --git a/drivers/edac/i7core_edac.c b/drivers/edac/i7core_edac.c index 87533ca..40a228d 100644 --- a/drivers/edac/i7core_edac.c +++ b/drivers/edac/i7core_edac.c @@ -9,7 +9,7 @@ * GNU General Public License version 2 only. * * Copyright (c) 2009-2010 by: - * Mauro Carvalho Chehab + * Mauro Carvalho Chehab * * Red Hat Inc. http://www.redhat.com * @@ -2456,7 +2456,7 @@ module_init(i7core_init); module_exit(i7core_exit); MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)"); MODULE_DESCRIPTION("MC Driver for Intel i7 Core memory controllers - " I7CORE_REVISION); diff --git a/drivers/edac/sb_edac.c b/drivers/edac/sb_edac.c index 54e2abe..3fa13db 100644 --- a/drivers/edac/sb_edac.c +++ b/drivers/edac/sb_edac.c @@ -7,7 +7,7 @@ * GNU General Public License version 2 only. * * Copyright (c) 2011 by: - * Mauro Carvalho Chehab + * Mauro Carvalho Chehab */ #include @@ -2176,7 +2176,7 @@ module_param(edac_op_state, int, 0444); MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)"); MODULE_DESCRIPTION("MC Driver for Intel Sandy Bridge and Ivy Bridge memory controllers - " SBRIDGE_REVISION); diff --git a/drivers/media/common/siano/smsdvb-debugfs.c b/drivers/media/common/siano/smsdvb-debugfs.c index 0bb4430..2408d7e 100644 --- a/drivers/media/common/siano/smsdvb-debugfs.c +++ b/drivers/media/common/siano/smsdvb-debugfs.c @@ -1,6 +1,6 @@ /*********************************************************************** * - * Copyright(c) 2013 Mauro Carvalho Chehab + * Copyright(c) 2013 Mauro Carvalho Chehab * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/drivers/media/dvb-frontends/mb86a20s.c b/drivers/media/dvb-frontends/mb86a20s.c index 2c7217f..2f458bb 100644 --- a/drivers/media/dvb-frontends/mb86a20s.c +++ b/drivers/media/dvb-frontends/mb86a20s.c @@ -1,7 +1,7 @@ /* * Fujitu mb86a20s ISDB-T/ISDB-Tsb Module driver * - * Copyright (C) 2010-2013 Mauro Carvalho Chehab + * Copyright (C) 2010-2013 Mauro Carvalho Chehab * Copyright (C) 2009-2010 Douglas Landgraf * * This program is free software; you can redistribute it and/or @@ -2156,5 +2156,5 @@ static struct dvb_frontend_ops mb86a20s_ops = { }; MODULE_DESCRIPTION("DVB Frontend module for Fujitsu mb86A20s hardware"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); MODULE_LICENSE("GPL"); diff --git a/drivers/media/dvb-frontends/mb86a20s.h b/drivers/media/dvb-frontends/mb86a20s.h index 6627a39..cbeb941 100644 --- a/drivers/media/dvb-frontends/mb86a20s.h +++ b/drivers/media/dvb-frontends/mb86a20s.h @@ -1,7 +1,7 @@ /* * Fujitsu mb86a20s driver * - * Copyright (C) 2010 Mauro Carvalho Chehab + * Copyright (C) 2010 Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/drivers/media/dvb-frontends/s921.c b/drivers/media/dvb-frontends/s921.c index a271ac3..69862e1 100644 --- a/drivers/media/dvb-frontends/s921.c +++ b/drivers/media/dvb-frontends/s921.c @@ -2,7 +2,7 @@ * Sharp VA3A5JZ921 One Seg Broadcast Module driver * This device is labeled as just S. 921 at the top of the frontend can * - * Copyright (C) 2009-2010 Mauro Carvalho Chehab + * Copyright (C) 2009-2010 Mauro Carvalho Chehab * Copyright (C) 2009-2010 Douglas Landgraf * * Developed for Leadership SBTVD 1seg device sold in Brazil @@ -539,6 +539,6 @@ static struct dvb_frontend_ops s921_ops = { }; MODULE_DESCRIPTION("DVB Frontend module for Sharp S921 hardware"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); MODULE_AUTHOR("Douglas Landgraf "); MODULE_LICENSE("GPL"); diff --git a/drivers/media/dvb-frontends/s921.h b/drivers/media/dvb-frontends/s921.h index 8d5e2a6..9b20c9e 100644 --- a/drivers/media/dvb-frontends/s921.h +++ b/drivers/media/dvb-frontends/s921.h @@ -1,7 +1,7 @@ /* * Sharp s921 driver * - * Copyright (C) 2009 Mauro Carvalho Chehab + * Copyright (C) 2009 Mauro Carvalho Chehab * Copyright (C) 2009 Douglas Landgraf * * This program is free software; you can redistribute it and/or diff --git a/drivers/media/i2c/mt9v011.c b/drivers/media/i2c/mt9v011.c index f74698c..47e4753 100644 --- a/drivers/media/i2c/mt9v011.c +++ b/drivers/media/i2c/mt9v011.c @@ -1,7 +1,7 @@ /* * mt9v011 -Micron 1/4-Inch VGA Digital Image Sensor * - * Copyright (c) 2009 Mauro Carvalho Chehab (mchehab@redhat.com) + * Copyright (c) 2009 Mauro Carvalho Chehab * This code is placed under the terms of the GNU General Public License v2 */ @@ -16,7 +16,7 @@ #include MODULE_DESCRIPTION("Micron mt9v011 sensor driver"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); MODULE_LICENSE("GPL"); static int debug; diff --git a/drivers/media/i2c/sr030pc30.c b/drivers/media/i2c/sr030pc30.c index ae94326..118f8ee 100644 --- a/drivers/media/i2c/sr030pc30.c +++ b/drivers/media/i2c/sr030pc30.c @@ -8,7 +8,7 @@ * and HeungJun Kim . * * Based on mt9v011 Micron Digital Image Sensor driver - * Copyright (c) 2009 Mauro Carvalho Chehab (mchehab@redhat.com) + * Copyright (c) 2009 Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/drivers/media/rc/ir-nec-decoder.c b/drivers/media/rc/ir-nec-decoder.c index 1bab7ea..e687a42 100644 --- a/drivers/media/rc/ir-nec-decoder.c +++ b/drivers/media/rc/ir-nec-decoder.c @@ -1,6 +1,6 @@ /* ir-nec-decoder.c - handle NEC IR Pulse/Space protocol * - * Copyright (C) 2010 by Mauro Carvalho Chehab + * Copyright (C) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -225,6 +225,6 @@ module_init(ir_nec_decode_init); module_exit(ir_nec_decode_exit); MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)"); MODULE_DESCRIPTION("NEC IR protocol decoder"); diff --git a/drivers/media/rc/ir-raw.c b/drivers/media/rc/ir-raw.c index 79a9cb6..f0656fa 100644 --- a/drivers/media/rc/ir-raw.c +++ b/drivers/media/rc/ir-raw.c @@ -1,6 +1,6 @@ /* ir-raw.c - handle IR pulse/space events * - * Copyright (C) 2010 by Mauro Carvalho Chehab + * Copyright (C) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/drivers/media/rc/ir-rc5-decoder.c b/drivers/media/rc/ir-rc5-decoder.c index 4e53a31..1085e17 100644 --- a/drivers/media/rc/ir-rc5-decoder.c +++ b/drivers/media/rc/ir-rc5-decoder.c @@ -1,6 +1,6 @@ /* ir-rc5-decoder.c - handle RC5(x) IR Pulse/Space protocol * - * Copyright (C) 2010 by Mauro Carvalho Chehab + * Copyright (C) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -193,6 +193,6 @@ module_init(ir_rc5_decode_init); module_exit(ir_rc5_decode_exit); MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)"); MODULE_DESCRIPTION("RC5(x) IR protocol decoder"); diff --git a/drivers/media/rc/ir-rc5-sz-decoder.c b/drivers/media/rc/ir-rc5-sz-decoder.c index 865fe84..984e5b9 100644 --- a/drivers/media/rc/ir-rc5-sz-decoder.c +++ b/drivers/media/rc/ir-rc5-sz-decoder.c @@ -1,6 +1,6 @@ /* ir-rc5-sz-decoder.c - handle RC5 Streamzap IR Pulse/Space protocol * - * Copyright (C) 2010 by Mauro Carvalho Chehab + * Copyright (C) 2010 by Mauro Carvalho Chehab * Copyright (C) 2010 by Jarod Wilson * * This program is free software; you can redistribute it and/or modify diff --git a/drivers/media/rc/ir-sanyo-decoder.c b/drivers/media/rc/ir-sanyo-decoder.c index 0a06205..e1351ed 100644 --- a/drivers/media/rc/ir-sanyo-decoder.c +++ b/drivers/media/rc/ir-sanyo-decoder.c @@ -1,6 +1,6 @@ /* ir-sanyo-decoder.c - handle SANYO IR Pulse/Space protocol * - * Copyright (C) 2011 by Mauro Carvalho Chehab + * Copyright (C) 2011 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -200,6 +200,6 @@ module_init(ir_sanyo_decode_init); module_exit(ir_sanyo_decode_exit); MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)"); MODULE_DESCRIPTION("SANYO IR protocol decoder"); diff --git a/drivers/media/rc/ir-sharp-decoder.c b/drivers/media/rc/ir-sharp-decoder.c index 4c17be5..4895bc7 100644 --- a/drivers/media/rc/ir-sharp-decoder.c +++ b/drivers/media/rc/ir-sharp-decoder.c @@ -3,7 +3,7 @@ * Copyright (C) 2013-2014 Imagination Technologies Ltd. * * Based on NEC decoder: - * Copyright (C) 2010 by Mauro Carvalho Chehab + * Copyright (C) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/drivers/media/rc/keymaps/rc-adstech-dvb-t-pci.c b/drivers/media/rc/keymaps/rc-adstech-dvb-t-pci.c index b0e42df..01d901f 100644 --- a/drivers/media/rc/keymaps/rc-adstech-dvb-t-pci.c +++ b/drivers/media/rc/keymaps/rc-adstech-dvb-t-pci.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -87,4 +87,4 @@ module_init(init_rc_map_adstech_dvb_t_pci) module_exit(exit_rc_map_adstech_dvb_t_pci) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-apac-viewcomp.c b/drivers/media/rc/keymaps/rc-apac-viewcomp.c index 8c92ff9..bf9efa0 100644 --- a/drivers/media/rc/keymaps/rc-apac-viewcomp.c +++ b/drivers/media/rc/keymaps/rc-apac-viewcomp.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -78,4 +78,4 @@ module_init(init_rc_map_apac_viewcomp) module_exit(exit_rc_map_apac_viewcomp) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-asus-pc39.c b/drivers/media/rc/keymaps/rc-asus-pc39.c index 2caf211..9e674ba 100644 --- a/drivers/media/rc/keymaps/rc-asus-pc39.c +++ b/drivers/media/rc/keymaps/rc-asus-pc39.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -89,4 +89,4 @@ module_init(init_rc_map_asus_pc39) module_exit(exit_rc_map_asus_pc39) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-asus-ps3-100.c b/drivers/media/rc/keymaps/rc-asus-ps3-100.c index ba76609..e45de35 100644 --- a/drivers/media/rc/keymaps/rc-asus-ps3-100.c +++ b/drivers/media/rc/keymaps/rc-asus-ps3-100.c @@ -1,6 +1,6 @@ /* asus-ps3-100.h - Keytable for asus_ps3_100 Remote Controller * - * Copyright (c) 2012 by Mauro Carvalho Chehab + * Copyright (c) 2012 by Mauro Carvalho Chehab * * Based on a previous patch from Remi Schwartz * @@ -88,4 +88,4 @@ module_init(init_rc_map_asus_ps3_100) module_exit(exit_rc_map_asus_ps3_100) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-ati-tv-wonder-hd-600.c b/drivers/media/rc/keymaps/rc-ati-tv-wonder-hd-600.c index 2031224..91392d4 100644 --- a/drivers/media/rc/keymaps/rc-ati-tv-wonder-hd-600.c +++ b/drivers/media/rc/keymaps/rc-ati-tv-wonder-hd-600.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -67,4 +67,4 @@ module_init(init_rc_map_ati_tv_wonder_hd_600) module_exit(exit_rc_map_ati_tv_wonder_hd_600) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-avermedia-a16d.c b/drivers/media/rc/keymaps/rc-avermedia-a16d.c index 894939a..ff30a71 100644 --- a/drivers/media/rc/keymaps/rc-avermedia-a16d.c +++ b/drivers/media/rc/keymaps/rc-avermedia-a16d.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -73,4 +73,4 @@ module_init(init_rc_map_avermedia_a16d) module_exit(exit_rc_map_avermedia_a16d) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-avermedia-cardbus.c b/drivers/media/rc/keymaps/rc-avermedia-cardbus.c index d2aaf5b..d7471a6 100644 --- a/drivers/media/rc/keymaps/rc-avermedia-cardbus.c +++ b/drivers/media/rc/keymaps/rc-avermedia-cardbus.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -95,4 +95,4 @@ module_init(init_rc_map_avermedia_cardbus) module_exit(exit_rc_map_avermedia_cardbus) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-avermedia-dvbt.c b/drivers/media/rc/keymaps/rc-avermedia-dvbt.c index dc2baf0..e2417d6 100644 --- a/drivers/media/rc/keymaps/rc-avermedia-dvbt.c +++ b/drivers/media/rc/keymaps/rc-avermedia-dvbt.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -76,4 +76,4 @@ module_init(init_rc_map_avermedia_dvbt) module_exit(exit_rc_map_avermedia_dvbt) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-avermedia-m135a.c b/drivers/media/rc/keymaps/rc-avermedia-m135a.c index 04269d3..843598a 100644 --- a/drivers/media/rc/keymaps/rc-avermedia-m135a.c +++ b/drivers/media/rc/keymaps/rc-avermedia-m135a.c @@ -1,6 +1,6 @@ /* avermedia-m135a.c - Keytable for Avermedia M135A Remote Controllers * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * Copyright (c) 2010 by Herton Ronaldo Krzesinski * * This program is free software; you can redistribute it and/or modify @@ -145,4 +145,4 @@ module_init(init_rc_map_avermedia_m135a) module_exit(exit_rc_map_avermedia_m135a) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-avermedia-m733a-rm-k6.c b/drivers/media/rc/keymaps/rc-avermedia-m733a-rm-k6.c index e83b1a1..b24e748 100644 --- a/drivers/media/rc/keymaps/rc-avermedia-m733a-rm-k6.c +++ b/drivers/media/rc/keymaps/rc-avermedia-m733a-rm-k6.c @@ -93,4 +93,4 @@ module_init(init_rc_map_avermedia_m733a_rm_k6) module_exit(exit_rc_map_avermedia_m733a_rm_k6) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-avermedia.c b/drivers/media/rc/keymaps/rc-avermedia.c index c6063df..3f68fbe 100644 --- a/drivers/media/rc/keymaps/rc-avermedia.c +++ b/drivers/media/rc/keymaps/rc-avermedia.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -84,4 +84,4 @@ module_init(init_rc_map_avermedia) module_exit(exit_rc_map_avermedia) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-avertv-303.c b/drivers/media/rc/keymaps/rc-avertv-303.c index 14f7845..c35bc5b 100644 --- a/drivers/media/rc/keymaps/rc-avertv-303.c +++ b/drivers/media/rc/keymaps/rc-avertv-303.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -83,4 +83,4 @@ module_init(init_rc_map_avertv_303) module_exit(exit_rc_map_avertv_303) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-behold-columbus.c b/drivers/media/rc/keymaps/rc-behold-columbus.c index 086b4b1..1fc344e 100644 --- a/drivers/media/rc/keymaps/rc-behold-columbus.c +++ b/drivers/media/rc/keymaps/rc-behold-columbus.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -106,4 +106,4 @@ module_init(init_rc_map_behold_columbus) module_exit(exit_rc_map_behold_columbus) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-behold.c b/drivers/media/rc/keymaps/rc-behold.c index 0877e34..d6519f8 100644 --- a/drivers/media/rc/keymaps/rc-behold.c +++ b/drivers/media/rc/keymaps/rc-behold.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -139,4 +139,4 @@ module_init(init_rc_map_behold) module_exit(exit_rc_map_behold) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-budget-ci-old.c b/drivers/media/rc/keymaps/rc-budget-ci-old.c index 8311e09..b196a5f 100644 --- a/drivers/media/rc/keymaps/rc-budget-ci-old.c +++ b/drivers/media/rc/keymaps/rc-budget-ci-old.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -91,4 +91,4 @@ module_init(init_rc_map_budget_ci_old) module_exit(exit_rc_map_budget_ci_old) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-cinergy-1400.c b/drivers/media/rc/keymaps/rc-cinergy-1400.c index 0c87fba..a099c08 100644 --- a/drivers/media/rc/keymaps/rc-cinergy-1400.c +++ b/drivers/media/rc/keymaps/rc-cinergy-1400.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -82,4 +82,4 @@ module_init(init_rc_map_cinergy_1400) module_exit(exit_rc_map_cinergy_1400) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-cinergy.c b/drivers/media/rc/keymaps/rc-cinergy.c index 309e9e3..b0f4328 100644 --- a/drivers/media/rc/keymaps/rc-cinergy.c +++ b/drivers/media/rc/keymaps/rc-cinergy.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -76,4 +76,4 @@ module_init(init_rc_map_cinergy) module_exit(exit_rc_map_cinergy) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-dib0700-nec.c b/drivers/media/rc/keymaps/rc-dib0700-nec.c index 492a05a..a0fa543 100644 --- a/drivers/media/rc/keymaps/rc-dib0700-nec.c +++ b/drivers/media/rc/keymaps/rc-dib0700-nec.c @@ -1,6 +1,6 @@ /* rc-dvb0700-big.c - Keytable for devices in dvb0700 * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * TODO: This table is a real mess, as it merges RC codes from several * devices into a big table. It also has both RC-5 and NEC codes inside. @@ -122,4 +122,4 @@ module_init(init_rc_map) module_exit(exit_rc_map) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-dib0700-rc5.c b/drivers/media/rc/keymaps/rc-dib0700-rc5.c index 454ea59..9079411 100644 --- a/drivers/media/rc/keymaps/rc-dib0700-rc5.c +++ b/drivers/media/rc/keymaps/rc-dib0700-rc5.c @@ -1,6 +1,6 @@ /* rc-dvb0700-big.c - Keytable for devices in dvb0700 * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * TODO: This table is a real mess, as it merges RC codes from several * devices into a big table. It also has both RC-5 and NEC codes inside. @@ -233,4 +233,4 @@ module_init(init_rc_map) module_exit(exit_rc_map) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-dm1105-nec.c b/drivers/media/rc/keymaps/rc-dm1105-nec.c index 67fc9fb..46e7ae4 100644 --- a/drivers/media/rc/keymaps/rc-dm1105-nec.c +++ b/drivers/media/rc/keymaps/rc-dm1105-nec.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -74,4 +74,4 @@ module_init(init_rc_map_dm1105_nec) module_exit(exit_rc_map_dm1105_nec) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-dntv-live-dvb-t.c b/drivers/media/rc/keymaps/rc-dntv-live-dvb-t.c index 91ea91d..d2826b4 100644 --- a/drivers/media/rc/keymaps/rc-dntv-live-dvb-t.c +++ b/drivers/media/rc/keymaps/rc-dntv-live-dvb-t.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -76,4 +76,4 @@ module_init(init_rc_map_dntv_live_dvb_t) module_exit(exit_rc_map_dntv_live_dvb_t) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-dntv-live-dvbt-pro.c b/drivers/media/rc/keymaps/rc-dntv-live-dvbt-pro.c index fd680d4..0d74769 100644 --- a/drivers/media/rc/keymaps/rc-dntv-live-dvbt-pro.c +++ b/drivers/media/rc/keymaps/rc-dntv-live-dvbt-pro.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -95,4 +95,4 @@ module_init(init_rc_map_dntv_live_dvbt_pro) module_exit(exit_rc_map_dntv_live_dvbt_pro) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-em-terratec.c b/drivers/media/rc/keymaps/rc-em-terratec.c index d1fcd64..7f1e06b 100644 --- a/drivers/media/rc/keymaps/rc-em-terratec.c +++ b/drivers/media/rc/keymaps/rc-em-terratec.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -67,4 +67,4 @@ module_init(init_rc_map_em_terratec) module_exit(exit_rc_map_em_terratec) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-encore-enltv-fm53.c b/drivers/media/rc/keymaps/rc-encore-enltv-fm53.c index 2fe45e4..4fc3904 100644 --- a/drivers/media/rc/keymaps/rc-encore-enltv-fm53.c +++ b/drivers/media/rc/keymaps/rc-encore-enltv-fm53.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -79,4 +79,4 @@ module_init(init_rc_map_encore_enltv_fm53) module_exit(exit_rc_map_encore_enltv_fm53) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-encore-enltv.c b/drivers/media/rc/keymaps/rc-encore-enltv.c index 223de75..f1914e2 100644 --- a/drivers/media/rc/keymaps/rc-encore-enltv.c +++ b/drivers/media/rc/keymaps/rc-encore-enltv.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -110,4 +110,4 @@ module_init(init_rc_map_encore_enltv) module_exit(exit_rc_map_encore_enltv) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-encore-enltv2.c b/drivers/media/rc/keymaps/rc-encore-enltv2.c index 669cbff..9c6c552 100644 --- a/drivers/media/rc/keymaps/rc-encore-enltv2.c +++ b/drivers/media/rc/keymaps/rc-encore-enltv2.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -88,4 +88,4 @@ module_init(init_rc_map_encore_enltv2) module_exit(exit_rc_map_encore_enltv2) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-evga-indtube.c b/drivers/media/rc/keymaps/rc-evga-indtube.c index 2c647fc..2370d2a 100644 --- a/drivers/media/rc/keymaps/rc-evga-indtube.c +++ b/drivers/media/rc/keymaps/rc-evga-indtube.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -59,4 +59,4 @@ module_init(init_rc_map_evga_indtube) module_exit(exit_rc_map_evga_indtube) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-eztv.c b/drivers/media/rc/keymaps/rc-eztv.c index 7692144..b5c96ed 100644 --- a/drivers/media/rc/keymaps/rc-eztv.c +++ b/drivers/media/rc/keymaps/rc-eztv.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -94,4 +94,4 @@ module_init(init_rc_map_eztv) module_exit(exit_rc_map_eztv) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-flydvb.c b/drivers/media/rc/keymaps/rc-flydvb.c index 3a6bba3..25cb89f 100644 --- a/drivers/media/rc/keymaps/rc-flydvb.c +++ b/drivers/media/rc/keymaps/rc-flydvb.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -75,4 +75,4 @@ module_init(init_rc_map_flydvb) module_exit(exit_rc_map_flydvb) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-flyvideo.c b/drivers/media/rc/keymaps/rc-flyvideo.c index bf9da58..e71377d 100644 --- a/drivers/media/rc/keymaps/rc-flyvideo.c +++ b/drivers/media/rc/keymaps/rc-flyvideo.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -68,4 +68,4 @@ module_init(init_rc_map_flyvideo) module_exit(exit_rc_map_flyvideo) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-fusionhdtv-mce.c b/drivers/media/rc/keymaps/rc-fusionhdtv-mce.c index 2f0970f..cf0608d 100644 --- a/drivers/media/rc/keymaps/rc-fusionhdtv-mce.c +++ b/drivers/media/rc/keymaps/rc-fusionhdtv-mce.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -96,4 +96,4 @@ module_init(init_rc_map_fusionhdtv_mce) module_exit(exit_rc_map_fusionhdtv_mce) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-gadmei-rm008z.c b/drivers/media/rc/keymaps/rc-gadmei-rm008z.c index 0e98ec4..03575bd 100644 --- a/drivers/media/rc/keymaps/rc-gadmei-rm008z.c +++ b/drivers/media/rc/keymaps/rc-gadmei-rm008z.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -79,4 +79,4 @@ module_init(init_rc_map_gadmei_rm008z) module_exit(exit_rc_map_gadmei_rm008z) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-genius-tvgo-a11mce.c b/drivers/media/rc/keymaps/rc-genius-tvgo-a11mce.c index a2e2faa..b2ab13b 100644 --- a/drivers/media/rc/keymaps/rc-genius-tvgo-a11mce.c +++ b/drivers/media/rc/keymaps/rc-genius-tvgo-a11mce.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -82,4 +82,4 @@ module_init(init_rc_map_genius_tvgo_a11mce) module_exit(exit_rc_map_genius_tvgo_a11mce) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-gotview7135.c b/drivers/media/rc/keymaps/rc-gotview7135.c index 864614e..229a36a 100644 --- a/drivers/media/rc/keymaps/rc-gotview7135.c +++ b/drivers/media/rc/keymaps/rc-gotview7135.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -77,4 +77,4 @@ module_init(init_rc_map_gotview7135) module_exit(exit_rc_map_gotview7135) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-hauppauge.c b/drivers/media/rc/keymaps/rc-hauppauge.c index 929bbbc1..36d57f7c 100644 --- a/drivers/media/rc/keymaps/rc-hauppauge.c +++ b/drivers/media/rc/keymaps/rc-hauppauge.c @@ -8,7 +8,7 @@ * - Hauppauge Black; * - DSR-0112 remote bundled with Haupauge MiniStick. * - * Copyright (c) 2010-2011 by Mauro Carvalho Chehab + * Copyright (c) 2010-2011 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -290,4 +290,4 @@ module_init(init_rc_map_rc5_hauppauge_new) module_exit(exit_rc_map_rc5_hauppauge_new) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-iodata-bctv7e.c b/drivers/media/rc/keymaps/rc-iodata-bctv7e.c index 34540df..9ee154c 100644 --- a/drivers/media/rc/keymaps/rc-iodata-bctv7e.c +++ b/drivers/media/rc/keymaps/rc-iodata-bctv7e.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -86,4 +86,4 @@ module_init(init_rc_map_iodata_bctv7e) module_exit(exit_rc_map_iodata_bctv7e) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-kaiomy.c b/drivers/media/rc/keymaps/rc-kaiomy.c index 4264a78..60803a7 100644 --- a/drivers/media/rc/keymaps/rc-kaiomy.c +++ b/drivers/media/rc/keymaps/rc-kaiomy.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -85,4 +85,4 @@ module_init(init_rc_map_kaiomy) module_exit(exit_rc_map_kaiomy) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-kworld-315u.c b/drivers/media/rc/keymaps/rc-kworld-315u.c index e48cd26..ba087ee 100644 --- a/drivers/media/rc/keymaps/rc-kworld-315u.c +++ b/drivers/media/rc/keymaps/rc-kworld-315u.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -81,4 +81,4 @@ module_init(init_rc_map_kworld_315u) module_exit(exit_rc_map_kworld_315u) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-kworld-pc150u.c b/drivers/media/rc/keymaps/rc-kworld-pc150u.c index 233bb5e..b92e571 100644 --- a/drivers/media/rc/keymaps/rc-kworld-pc150u.c +++ b/drivers/media/rc/keymaps/rc-kworld-pc150u.c @@ -4,7 +4,7 @@ * * Copyright (c) 2010 by Kyle Strickland * (based on kworld-plus-tv-analog.c by - * Mauro Carvalho Chehab ) + * Mauro Carvalho Chehab) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/drivers/media/rc/keymaps/rc-kworld-plus-tv-analog.c b/drivers/media/rc/keymaps/rc-kworld-plus-tv-analog.c index 32998d6..edc8685 100644 --- a/drivers/media/rc/keymaps/rc-kworld-plus-tv-analog.c +++ b/drivers/media/rc/keymaps/rc-kworld-plus-tv-analog.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -97,4 +97,4 @@ module_init(init_rc_map_kworld_plus_tv_analog) module_exit(exit_rc_map_kworld_plus_tv_analog) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-manli.c b/drivers/media/rc/keymaps/rc-manli.c index e7038bb..92424ef 100644 --- a/drivers/media/rc/keymaps/rc-manli.c +++ b/drivers/media/rc/keymaps/rc-manli.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -132,4 +132,4 @@ module_init(init_rc_map_manli) module_exit(exit_rc_map_manli) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-msi-tvanywhere-plus.c b/drivers/media/rc/keymaps/rc-msi-tvanywhere-plus.c index c393d8a..fd7a55c 100644 --- a/drivers/media/rc/keymaps/rc-msi-tvanywhere-plus.c +++ b/drivers/media/rc/keymaps/rc-msi-tvanywhere-plus.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -121,4 +121,4 @@ module_init(init_rc_map_msi_tvanywhere_plus) module_exit(exit_rc_map_msi_tvanywhere_plus) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-msi-tvanywhere.c b/drivers/media/rc/keymaps/rc-msi-tvanywhere.c index a7003d3..4233a8d 100644 --- a/drivers/media/rc/keymaps/rc-msi-tvanywhere.c +++ b/drivers/media/rc/keymaps/rc-msi-tvanywhere.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -67,4 +67,4 @@ module_init(init_rc_map_msi_tvanywhere) module_exit(exit_rc_map_msi_tvanywhere) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-nebula.c b/drivers/media/rc/keymaps/rc-nebula.c index 3f0ddd7..8ec881a 100644 --- a/drivers/media/rc/keymaps/rc-nebula.c +++ b/drivers/media/rc/keymaps/rc-nebula.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -94,4 +94,4 @@ module_init(init_rc_map_nebula) module_exit(exit_rc_map_nebula) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-nec-terratec-cinergy-xs.c b/drivers/media/rc/keymaps/rc-nec-terratec-cinergy-xs.c index 8d4dae2..292bbad3 100644 --- a/drivers/media/rc/keymaps/rc-nec-terratec-cinergy-xs.c +++ b/drivers/media/rc/keymaps/rc-nec-terratec-cinergy-xs.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -14,7 +14,7 @@ #include /* Terratec Cinergy Hybrid T USB XS FM - Mauro Carvalho Chehab + Mauro Carvalho Chehab */ static struct rc_map_table nec_terratec_cinergy_xs[] = { @@ -155,4 +155,4 @@ module_init(init_rc_map_nec_terratec_cinergy_xs) module_exit(exit_rc_map_nec_terratec_cinergy_xs) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-norwood.c b/drivers/media/rc/keymaps/rc-norwood.c index 9e65f07..ca1b82a 100644 --- a/drivers/media/rc/keymaps/rc-norwood.c +++ b/drivers/media/rc/keymaps/rc-norwood.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -83,4 +83,4 @@ module_init(init_rc_map_norwood) module_exit(exit_rc_map_norwood) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-npgtech.c b/drivers/media/rc/keymaps/rc-npgtech.c index 65d0cfc..1fb9460 100644 --- a/drivers/media/rc/keymaps/rc-npgtech.c +++ b/drivers/media/rc/keymaps/rc-npgtech.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -78,4 +78,4 @@ module_init(init_rc_map_npgtech) module_exit(exit_rc_map_npgtech) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-pctv-sedna.c b/drivers/media/rc/keymaps/rc-pctv-sedna.c index bf2cbdf..5ef01ab 100644 --- a/drivers/media/rc/keymaps/rc-pctv-sedna.c +++ b/drivers/media/rc/keymaps/rc-pctv-sedna.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -78,4 +78,4 @@ module_init(init_rc_map_pctv_sedna) module_exit(exit_rc_map_pctv_sedna) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-pinnacle-color.c b/drivers/media/rc/keymaps/rc-pinnacle-color.c index b46cd8f..a218b47 100644 --- a/drivers/media/rc/keymaps/rc-pinnacle-color.c +++ b/drivers/media/rc/keymaps/rc-pinnacle-color.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -92,4 +92,4 @@ module_init(init_rc_map_pinnacle_color) module_exit(exit_rc_map_pinnacle_color) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-pinnacle-grey.c b/drivers/media/rc/keymaps/rc-pinnacle-grey.c index d525df9..4a3f467 100644 --- a/drivers/media/rc/keymaps/rc-pinnacle-grey.c +++ b/drivers/media/rc/keymaps/rc-pinnacle-grey.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -87,4 +87,4 @@ module_init(init_rc_map_pinnacle_grey) module_exit(exit_rc_map_pinnacle_grey) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-pinnacle-pctv-hd.c b/drivers/media/rc/keymaps/rc-pinnacle-pctv-hd.c index a4603d0..e89cc10 100644 --- a/drivers/media/rc/keymaps/rc-pinnacle-pctv-hd.c +++ b/drivers/media/rc/keymaps/rc-pinnacle-pctv-hd.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -68,4 +68,4 @@ module_init(init_rc_map_pinnacle_pctv_hd) module_exit(exit_rc_map_pinnacle_pctv_hd) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-pixelview-002t.c b/drivers/media/rc/keymaps/rc-pixelview-002t.c index 33eb643..d967c38 100644 --- a/drivers/media/rc/keymaps/rc-pixelview-002t.c +++ b/drivers/media/rc/keymaps/rc-pixelview-002t.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -75,4 +75,4 @@ module_init(init_rc_map_pixelview) module_exit(exit_rc_map_pixelview) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-pixelview-mk12.c b/drivers/media/rc/keymaps/rc-pixelview-mk12.c index 21f4dd2..224d0ef 100644 --- a/drivers/media/rc/keymaps/rc-pixelview-mk12.c +++ b/drivers/media/rc/keymaps/rc-pixelview-mk12.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -81,4 +81,4 @@ module_init(init_rc_map_pixelview) module_exit(exit_rc_map_pixelview) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-pixelview-new.c b/drivers/media/rc/keymaps/rc-pixelview-new.c index f944ad2..781d788 100644 --- a/drivers/media/rc/keymaps/rc-pixelview-new.c +++ b/drivers/media/rc/keymaps/rc-pixelview-new.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -81,4 +81,4 @@ module_init(init_rc_map_pixelview_new) module_exit(exit_rc_map_pixelview_new) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-pixelview.c b/drivers/media/rc/keymaps/rc-pixelview.c index a6020ee..39e6fea 100644 --- a/drivers/media/rc/keymaps/rc-pixelview.c +++ b/drivers/media/rc/keymaps/rc-pixelview.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -80,4 +80,4 @@ module_init(init_rc_map_pixelview) module_exit(exit_rc_map_pixelview) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-powercolor-real-angel.c b/drivers/media/rc/keymaps/rc-powercolor-real-angel.c index e74c571..e96fa3a 100644 --- a/drivers/media/rc/keymaps/rc-powercolor-real-angel.c +++ b/drivers/media/rc/keymaps/rc-powercolor-real-angel.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -79,4 +79,4 @@ module_init(init_rc_map_powercolor_real_angel) module_exit(exit_rc_map_powercolor_real_angel) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-proteus-2309.c b/drivers/media/rc/keymaps/rc-proteus-2309.c index adee803..eef626e 100644 --- a/drivers/media/rc/keymaps/rc-proteus-2309.c +++ b/drivers/media/rc/keymaps/rc-proteus-2309.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -67,4 +67,4 @@ module_init(init_rc_map_proteus_2309) module_exit(exit_rc_map_proteus_2309) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-purpletv.c b/drivers/media/rc/keymaps/rc-purpletv.c index 722597a..cec6fe4 100644 --- a/drivers/media/rc/keymaps/rc-purpletv.c +++ b/drivers/media/rc/keymaps/rc-purpletv.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -79,4 +79,4 @@ module_init(init_rc_map_purpletv) module_exit(exit_rc_map_purpletv) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-pv951.c b/drivers/media/rc/keymaps/rc-pv951.c index 0105d63..5ac89ce 100644 --- a/drivers/media/rc/keymaps/rc-pv951.c +++ b/drivers/media/rc/keymaps/rc-pv951.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -76,4 +76,4 @@ module_init(init_rc_map_pv951) module_exit(exit_rc_map_pv951) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-real-audio-220-32-keys.c b/drivers/media/rc/keymaps/rc-real-audio-220-32-keys.c index 073694d..9f778bd 100644 --- a/drivers/media/rc/keymaps/rc-real-audio-220-32-keys.c +++ b/drivers/media/rc/keymaps/rc-real-audio-220-32-keys.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -76,4 +76,4 @@ module_init(init_rc_map_real_audio_220_32_keys) module_exit(exit_rc_map_real_audio_220_32_keys) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-tbs-nec.c b/drivers/media/rc/keymaps/rc-tbs-nec.c index 5039be7..24ce2a2 100644 --- a/drivers/media/rc/keymaps/rc-tbs-nec.c +++ b/drivers/media/rc/keymaps/rc-tbs-nec.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -73,4 +73,4 @@ module_init(init_rc_map_tbs_nec) module_exit(exit_rc_map_tbs_nec) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-terratec-cinergy-xs.c b/drivers/media/rc/keymaps/rc-terratec-cinergy-xs.c index 53629fb..97eb83a 100644 --- a/drivers/media/rc/keymaps/rc-terratec-cinergy-xs.c +++ b/drivers/media/rc/keymaps/rc-terratec-cinergy-xs.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -90,4 +90,4 @@ module_init(init_rc_map_terratec_cinergy_xs) module_exit(exit_rc_map_terratec_cinergy_xs) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-tevii-nec.c b/drivers/media/rc/keymaps/rc-tevii-nec.c index f2c3b75..38e0c08 100644 --- a/drivers/media/rc/keymaps/rc-tevii-nec.c +++ b/drivers/media/rc/keymaps/rc-tevii-nec.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -86,4 +86,4 @@ module_init(init_rc_map_tevii_nec) module_exit(exit_rc_map_tevii_nec) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-tt-1500.c b/drivers/media/rc/keymaps/rc-tt-1500.c index 80217ff..c766d3b 100644 --- a/drivers/media/rc/keymaps/rc-tt-1500.c +++ b/drivers/media/rc/keymaps/rc-tt-1500.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -80,4 +80,4 @@ module_init(init_rc_map_tt_1500) module_exit(exit_rc_map_tt_1500) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-videomate-s350.c b/drivers/media/rc/keymaps/rc-videomate-s350.c index 8bfc3e8..8a35477 100644 --- a/drivers/media/rc/keymaps/rc-videomate-s350.c +++ b/drivers/media/rc/keymaps/rc-videomate-s350.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -83,4 +83,4 @@ module_init(init_rc_map_videomate_s350) module_exit(exit_rc_map_videomate_s350) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-videomate-tv-pvr.c b/drivers/media/rc/keymaps/rc-videomate-tv-pvr.c index 390ce94..eb0cda7 100644 --- a/drivers/media/rc/keymaps/rc-videomate-tv-pvr.c +++ b/drivers/media/rc/keymaps/rc-videomate-tv-pvr.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -85,4 +85,4 @@ module_init(init_rc_map_videomate_tv_pvr) module_exit(exit_rc_map_videomate_tv_pvr) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-winfast-usbii-deluxe.c b/drivers/media/rc/keymaps/rc-winfast-usbii-deluxe.c index 2852bf7..c1dd598 100644 --- a/drivers/media/rc/keymaps/rc-winfast-usbii-deluxe.c +++ b/drivers/media/rc/keymaps/rc-winfast-usbii-deluxe.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -80,4 +80,4 @@ module_init(init_rc_map_winfast_usbii_deluxe) module_exit(exit_rc_map_winfast_usbii_deluxe) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-winfast.c b/drivers/media/rc/keymaps/rc-winfast.c index 2df1cba..8a779da 100644 --- a/drivers/media/rc/keymaps/rc-winfast.c +++ b/drivers/media/rc/keymaps/rc-winfast.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -100,4 +100,4 @@ module_init(init_rc_map_winfast) module_exit(exit_rc_map_winfast) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/rc-core-priv.h b/drivers/media/rc/rc-core-priv.h index dc3b0b7..da536c9 100644 --- a/drivers/media/rc/rc-core-priv.h +++ b/drivers/media/rc/rc-core-priv.h @@ -1,7 +1,7 @@ /* * Remote Controller core raw events header * - * Copyright (C) 2010 by Mauro Carvalho Chehab + * Copyright (C) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/drivers/media/rc/rc-main.c b/drivers/media/rc/rc-main.c index fa8b957..2ec60f8 100644 --- a/drivers/media/rc/rc-main.c +++ b/drivers/media/rc/rc-main.c @@ -1,6 +1,6 @@ /* rc-main.c - Remote Controller core module * - * Copyright (C) 2009-2010 by Mauro Carvalho Chehab + * Copyright (C) 2009-2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -1398,5 +1398,5 @@ int rc_core_debug; /* ir_debug level (0,1,2) */ EXPORT_SYMBOL_GPL(rc_core_debug); module_param_named(debug, rc_core_debug, int, 0644); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); MODULE_LICENSE("GPL"); diff --git a/drivers/media/tuners/mt2063.c b/drivers/media/tuners/mt2063.c index 20cca40..f640dcf 100644 --- a/drivers/media/tuners/mt2063.c +++ b/drivers/media/tuners/mt2063.c @@ -1,7 +1,7 @@ /* * Driver for mt2063 Micronas tuner * - * Copyright (c) 2011 Mauro Carvalho Chehab + * Copyright (c) 2011 Mauro Carvalho Chehab * * This driver came from a driver originally written by: * Henry Wang @@ -2298,6 +2298,6 @@ static int tuner_MT2063_ClearPowerMaskBits(struct dvb_frontend *fe) } #endif -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); MODULE_DESCRIPTION("MT2063 Silicon tuner"); MODULE_LICENSE("GPL"); diff --git a/drivers/media/tuners/r820t.c b/drivers/media/tuners/r820t.c index d9ee43f..319adc4 100644 --- a/drivers/media/tuners/r820t.c +++ b/drivers/media/tuners/r820t.c @@ -1,7 +1,7 @@ /* * Rafael Micro R820T driver * - * Copyright (C) 2013 Mauro Carvalho Chehab + * Copyright (C) 2013 Mauro Carvalho Chehab * * This driver was written from scratch, based on an existing driver * that it is part of rtl-sdr git tree, released under GPLv2: @@ -2351,5 +2351,5 @@ err_no_gate: EXPORT_SYMBOL_GPL(r820t_attach); MODULE_DESCRIPTION("Rafael Micro r820t silicon tuner driver"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); MODULE_LICENSE("GPL"); diff --git a/drivers/media/usb/cx231xx/cx231xx-input.c b/drivers/media/usb/cx231xx/cx231xx-input.c index 0f7b424..46d52fa 100644 --- a/drivers/media/usb/cx231xx/cx231xx-input.c +++ b/drivers/media/usb/cx231xx/cx231xx-input.c @@ -1,7 +1,7 @@ /* * cx231xx IR glue driver * - * Copyright (C) 2010 Mauro Carvalho Chehab + * Copyright (C) 2010 Mauro Carvalho Chehab * * Polaris (cx231xx) has its support for IR's with a design close to MCE. * however, a few designs are using an external I2C chip for IR, instead diff --git a/drivers/media/usb/dvb-usb-v2/az6007.c b/drivers/media/usb/dvb-usb-v2/az6007.c index c1051c3..c3c4b98 100644 --- a/drivers/media/usb/dvb-usb-v2/az6007.c +++ b/drivers/media/usb/dvb-usb-v2/az6007.c @@ -7,7 +7,7 @@ * http://linux.terratec.de/files/TERRATEC_H7/20110323_TERRATEC_H7_Linux.tar.gz * The original driver's license is GPL, as declared with MODULE_LICENSE() * - * Copyright (c) 2010-2012 Mauro Carvalho Chehab + * Copyright (c) 2010-2012 Mauro Carvalho Chehab * Driver modified by in order to work with upstream drxk driver, and * tons of bugs got fixed, and converted to use dvb-usb-v2. * @@ -975,7 +975,7 @@ static struct usb_driver az6007_usb_driver = { module_usb_driver(az6007_usb_driver); MODULE_AUTHOR("Henry Wang "); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); MODULE_DESCRIPTION("Driver for AzureWave 6007 DVB-C/T USB2.0 and clones"); MODULE_VERSION("2.0"); MODULE_LICENSE("GPL"); diff --git a/drivers/media/usb/em28xx/em28xx-audio.c b/drivers/media/usb/em28xx/em28xx-audio.c index dfdfa77..566fa09 100644 --- a/drivers/media/usb/em28xx/em28xx-audio.c +++ b/drivers/media/usb/em28xx/em28xx-audio.c @@ -1008,7 +1008,7 @@ static void __exit em28xx_alsa_unregister(void) MODULE_LICENSE("GPL"); MODULE_AUTHOR("Markus Rechberger "); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); MODULE_DESCRIPTION(DRIVER_DESC " - audio interface"); MODULE_VERSION(EM28XX_VERSION); diff --git a/drivers/media/usb/em28xx/em28xx-input.c b/drivers/media/usb/em28xx/em28xx-input.c index 18f65d8..048e5b6 100644 --- a/drivers/media/usb/em28xx/em28xx-input.c +++ b/drivers/media/usb/em28xx/em28xx-input.c @@ -845,7 +845,7 @@ static void __exit em28xx_rc_unregister(void) } MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); MODULE_DESCRIPTION(DRIVER_DESC " - input interface"); MODULE_VERSION(EM28XX_VERSION); diff --git a/drivers/media/usb/tm6000/tm6000-alsa.c b/drivers/media/usb/tm6000/tm6000-alsa.c index 813c1ec..2c2a381 100644 --- a/drivers/media/usb/tm6000/tm6000-alsa.c +++ b/drivers/media/usb/tm6000/tm6000-alsa.c @@ -1,7 +1,7 @@ /* * * Support for audio capture for tm5600/6000/6010 - * (c) 2007-2008 Mauro Carvalho Chehab + * (c) 2007-2008 Mauro Carvalho Chehab * * Based on cx88-alsa.c * @@ -56,7 +56,7 @@ MODULE_PARM_DESC(index, "Index value for tm6000x capture interface(s)."); ****************************************************************************/ MODULE_DESCRIPTION("ALSA driver module for tm5600/tm6000/tm6010 based TV cards"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); MODULE_LICENSE("GPL"); MODULE_SUPPORTED_DEVICE("{{Trident,tm5600}," "{{Trident,tm6000}," diff --git a/drivers/media/usb/tm6000/tm6000-dvb.c b/drivers/media/usb/tm6000/tm6000-dvb.c index 9fc1e94..095f5db 100644 --- a/drivers/media/usb/tm6000/tm6000-dvb.c +++ b/drivers/media/usb/tm6000/tm6000-dvb.c @@ -32,7 +32,7 @@ #include "xc5000.h" MODULE_DESCRIPTION("DVB driver extension module for tm5600/6000/6010 based TV cards"); -MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Mauro Carvalho Chehab"); MODULE_LICENSE("GPL"); MODULE_SUPPORTED_DEVICE("{{Trident, tm5600}," diff --git a/drivers/media/usb/tm6000/tm6000-stds.c b/drivers/media/usb/tm6000/tm6000-stds.c index 5e28d6a..93a4b24 100644 --- a/drivers/media/usb/tm6000/tm6000-stds.c +++ b/drivers/media/usb/tm6000/tm6000-stds.c @@ -1,7 +1,7 @@ /* * tm6000-stds.c - driver for TM5600/TM6000/TM6010 USB video capture devices * - * Copyright (C) 2007 Mauro Carvalho Chehab + * Copyright (C) 2007 Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/include/media/rc-core.h b/include/media/rc-core.h index 4a72176..5e7197e 100644 --- a/include/media/rc-core.h +++ b/include/media/rc-core.h @@ -1,7 +1,7 @@ /* * Remote Controller core header * - * Copyright (C) 2009-2010 by Mauro Carvalho Chehab + * Copyright (C) 2009-2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/include/media/rc-map.h b/include/media/rc-map.h index b3224ed..e5aa240 100644 --- a/include/media/rc-map.h +++ b/include/media/rc-map.h @@ -1,7 +1,7 @@ /* * rc-map.h - define RC map names used by RC drivers * - * Copyright (c) 2010 by Mauro Carvalho Chehab + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by -- cgit v1.1 From 425f53aaf76cce77b3bedd8ed4902bc94ed254ff Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Wed, 12 Feb 2014 14:46:44 -0300 Subject: [media] em28xx-dvb: fix PCTV 461e tuner I2C binding Add missing m88ts2022 module reference counts as removing that module is not allowed when it is used by em28xx-dvb module. That same module was not unregistered correctly, fix it too. Error cases validated by returning errors from m88ds3103, m88ts2022 and a8293 probe(). Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/em28xx/em28xx-dvb.c | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/drivers/media/usb/em28xx/em28xx-dvb.c b/drivers/media/usb/em28xx/em28xx-dvb.c index a0a669e..defac24 100644 --- a/drivers/media/usb/em28xx/em28xx-dvb.c +++ b/drivers/media/usb/em28xx/em28xx-dvb.c @@ -1374,6 +1374,7 @@ static int em28xx_dvb_init(struct em28xx *dev) { /* demod I2C adapter */ struct i2c_adapter *i2c_adapter; + struct i2c_client *client; struct i2c_board_info info; struct m88ts2022_config m88ts2022_config = { .clock = 27000000, @@ -1396,7 +1397,19 @@ static int em28xx_dvb_init(struct em28xx *dev) info.addr = 0x60; info.platform_data = &m88ts2022_config; request_module("m88ts2022"); - dvb->i2c_client_tuner = i2c_new_device(i2c_adapter, &info); + client = i2c_new_device(i2c_adapter, &info); + if (client == NULL || client->dev.driver == NULL) { + dvb_frontend_detach(dvb->fe[0]); + result = -ENODEV; + goto out_free; + } + + if (!try_module_get(client->dev.driver->owner)) { + i2c_unregister_device(client); + dvb_frontend_detach(dvb->fe[0]); + result = -ENODEV; + goto out_free; + } /* delegate signal strength measurement to tuner */ dvb->fe[0]->ops.read_signal_strength = @@ -1406,10 +1419,14 @@ static int em28xx_dvb_init(struct em28xx *dev) if (!dvb_attach(a8293_attach, dvb->fe[0], &dev->i2c_adap[dev->def_i2c_bus], &em28xx_a8293_config)) { + module_put(client->dev.driver->owner); + i2c_unregister_device(client); dvb_frontend_detach(dvb->fe[0]); result = -ENODEV; goto out_free; } + + dvb->i2c_client_tuner = client; } break; default: @@ -1471,6 +1488,7 @@ static int em28xx_dvb_fini(struct em28xx *dev) if (dev->dvb) { struct em28xx_dvb *dvb = dev->dvb; + struct i2c_client *client = dvb->i2c_client_tuner; em28xx_uninit_usb_xfer(dev, EM28XX_DIGITAL_MODE); @@ -1483,7 +1501,12 @@ static int em28xx_dvb_fini(struct em28xx *dev) prevent_sleep(&dvb->fe[1]->ops); } - i2c_release_client(dvb->i2c_client_tuner); + /* remove I2C tuner */ + if (client) { + module_put(client->dev.driver->owner); + i2c_unregister_device(client); + } + em28xx_unregister_dvb(dvb); kfree(dvb); dev->dvb = NULL; -- cgit v1.1 From a24bc323eb07e2a3a751e23c172b68d1b239db67 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Till=20D=C3=B6rges?= Date: Tue, 11 Feb 2014 17:27:57 -0300 Subject: [media] rtl28xxu: add ID [0ccd:00b4] TerraTec NOXON DAB Stick (rev 3) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit I've got the following DAB USB stick that also works fine with the DVB_USB_RTL28XXU driver after I added its USB ID: Bus 001 Device 009: ID 0ccd:00b4 TerraTec Electronic GmbH [crope@iki.fi: apply patch partly manually] Signed-off-by: Till Dörges Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-core/dvb-usb-ids.h | 1 + drivers/media/usb/dvb-usb-v2/rtl28xxu.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/drivers/media/dvb-core/dvb-usb-ids.h b/drivers/media/dvb-core/dvb-usb-ids.h index f19a2cc..1bdc0e7 100644 --- a/drivers/media/dvb-core/dvb-usb-ids.h +++ b/drivers/media/dvb-core/dvb-usb-ids.h @@ -257,6 +257,7 @@ #define USB_PID_TERRATEC_T5 0x10a1 #define USB_PID_NOXON_DAB_STICK 0x00b3 #define USB_PID_NOXON_DAB_STICK_REV2 0x00e0 +#define USB_PID_NOXON_DAB_STICK_REV3 0x00b4 #define USB_PID_PINNACLE_EXPRESSCARD_320CX 0x022e #define USB_PID_PINNACLE_PCTV2000E 0x022c #define USB_PID_PINNACLE_PCTV_DVB_T_FLASH 0x0228 diff --git a/drivers/media/usb/dvb-usb-v2/rtl28xxu.c b/drivers/media/usb/dvb-usb-v2/rtl28xxu.c index fda5c64..8e61523 100644 --- a/drivers/media/usb/dvb-usb-v2/rtl28xxu.c +++ b/drivers/media/usb/dvb-usb-v2/rtl28xxu.c @@ -1401,6 +1401,8 @@ static const struct usb_device_id rtl28xxu_id_table[] = { &rtl2832u_props, "TerraTec NOXON DAB Stick", NULL) }, { DVB_USB_DEVICE(USB_VID_TERRATEC, USB_PID_NOXON_DAB_STICK_REV2, &rtl2832u_props, "TerraTec NOXON DAB Stick (rev 2)", NULL) }, + { DVB_USB_DEVICE(USB_VID_TERRATEC, USB_PID_NOXON_DAB_STICK_REV3, + &rtl2832u_props, "TerraTec NOXON DAB Stick (rev 3)", NULL) }, { DVB_USB_DEVICE(USB_VID_GTEK, USB_PID_TREKSTOR_TERRES_2_0, &rtl2832u_props, "Trekstor DVB-T Stick Terres 2.0", NULL) }, { DVB_USB_DEVICE(USB_VID_DEXATEK, 0x1101, -- cgit v1.1 From a3a528ba8ed1272af4b7d2f115eff7eb21c3971f Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Thu, 30 Jan 2014 09:00:34 -0300 Subject: [media] tda10071: remove a duplicative test "ret" is an error code here, we already tested that. Signed-off-by: Dan Carpenter Acked-by: Antti Palosaari Reviewed-by: Antti Palosaari Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/tda10071.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/media/dvb-frontends/tda10071.c b/drivers/media/dvb-frontends/tda10071.c index 8ad3a57..a76df29 100644 --- a/drivers/media/dvb-frontends/tda10071.c +++ b/drivers/media/dvb-frontends/tda10071.c @@ -1006,8 +1006,7 @@ static int tda10071_init(struct dvb_frontend *fe) dev_err(&priv->i2c->dev, "%s: firmware " \ "download failed=%d\n", KBUILD_MODNAME, ret); - if (ret) - goto error_release_firmware; + goto error_release_firmware; } } release_firmware(fw); -- cgit v1.1 From 07115606773bbb534307fd22c80832a5d5d478fa Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Tue, 11 Feb 2014 00:17:37 -0300 Subject: [media] tda10071: do not check tuner PLL lock on read_status() Tuner PLL lock flag was mapped to FE_HAS_SIGNAL, which is wrong. PLL lock has nothing to do with received signal. In real life that flag is always set. Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/tda10071.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/media/dvb-frontends/tda10071.c b/drivers/media/dvb-frontends/tda10071.c index a76df29..13c823a 100644 --- a/drivers/media/dvb-frontends/tda10071.c +++ b/drivers/media/dvb-frontends/tda10071.c @@ -491,10 +491,9 @@ static int tda10071_read_status(struct dvb_frontend *fe, fe_status_t *status) if (ret) goto error; - if (tmp & 0x01) /* tuner PLL */ - *status |= FE_HAS_SIGNAL; + /* 0x39[0] tuner PLL */ if (tmp & 0x02) /* demod PLL */ - *status |= FE_HAS_CARRIER; + *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER; if (tmp & 0x04) /* viterbi or LDPC*/ *status |= FE_HAS_VITERBI; if (tmp & 0x08) /* RS or BCH */ -- cgit v1.1 From 116802f1ce2ee2fc521adf888b8f4fc3f298d8ac Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Tue, 11 Feb 2014 15:13:46 -0300 Subject: [media] tda10071: coding style issues Fix some coding style issues, mostly reported by checkpatch.pl. Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/tda10071.c | 60 +++++++++++++++++++--------------- drivers/media/dvb-frontends/tda10071.h | 2 +- 2 files changed, 34 insertions(+), 28 deletions(-) diff --git a/drivers/media/dvb-frontends/tda10071.c b/drivers/media/dvb-frontends/tda10071.c index 13c823a..522fe00 100644 --- a/drivers/media/dvb-frontends/tda10071.c +++ b/drivers/media/dvb-frontends/tda10071.c @@ -42,8 +42,8 @@ static int tda10071_wr_regs(struct tda10071_priv *priv, u8 reg, u8 *val, if (1 + len > sizeof(buf)) { dev_warn(&priv->i2c->dev, - "%s: i2c wr reg=%04x: len=%d is too big!\n", - KBUILD_MODNAME, reg, len); + "%s: i2c wr reg=%04x: len=%d is too big!\n", + KBUILD_MODNAME, reg, len); return -EINVAL; } @@ -54,8 +54,9 @@ static int tda10071_wr_regs(struct tda10071_priv *priv, u8 reg, u8 *val, if (ret == 1) { ret = 0; } else { - dev_warn(&priv->i2c->dev, "%s: i2c wr failed=%d reg=%02x " \ - "len=%d\n", KBUILD_MODNAME, ret, reg, len); + dev_warn(&priv->i2c->dev, + "%s: i2c wr failed=%d reg=%02x len=%d\n", + KBUILD_MODNAME, ret, reg, len); ret = -EREMOTEIO; } return ret; @@ -83,8 +84,8 @@ static int tda10071_rd_regs(struct tda10071_priv *priv, u8 reg, u8 *val, if (len > sizeof(buf)) { dev_warn(&priv->i2c->dev, - "%s: i2c wr reg=%04x: len=%d is too big!\n", - KBUILD_MODNAME, reg, len); + "%s: i2c wr reg=%04x: len=%d is too big!\n", + KBUILD_MODNAME, reg, len); return -EINVAL; } @@ -93,8 +94,9 @@ static int tda10071_rd_regs(struct tda10071_priv *priv, u8 reg, u8 *val, memcpy(val, buf, len); ret = 0; } else { - dev_warn(&priv->i2c->dev, "%s: i2c rd failed=%d reg=%02x " \ - "len=%d\n", KBUILD_MODNAME, ret, reg, len); + dev_warn(&priv->i2c->dev, + "%s: i2c rd failed=%d reg=%02x len=%d\n", + KBUILD_MODNAME, ret, reg, len); ret = -EREMOTEIO; } return ret; @@ -667,11 +669,11 @@ static int tda10071_set_frontend(struct dvb_frontend *fe) int ret, i; u8 mode, rolloff, pilot, inversion, div; - dev_dbg(&priv->i2c->dev, "%s: delivery_system=%d modulation=%d " \ - "frequency=%d symbol_rate=%d inversion=%d pilot=%d " \ - "rolloff=%d\n", __func__, c->delivery_system, c->modulation, - c->frequency, c->symbol_rate, c->inversion, c->pilot, - c->rolloff); + dev_dbg(&priv->i2c->dev, + "%s: delivery_system=%d modulation=%d frequency=%d symbol_rate=%d inversion=%d pilot=%d rolloff=%d\n", + __func__, c->delivery_system, c->modulation, + c->frequency, c->symbol_rate, c->inversion, c->pilot, + c->rolloff); priv->delivery_system = SYS_UNDEFINED; @@ -951,10 +953,8 @@ static int tda10071_init(struct dvb_frontend *fe) /* request the firmware, this will block and timeout */ ret = request_firmware(&fw, fw_file, priv->i2c->dev.parent); if (ret) { - dev_err(&priv->i2c->dev, "%s: did not find the " \ - "firmware file. (%s) Please see " \ - "linux/Documentation/dvb/ for more " \ - "details on firmware-problems. (%d)\n", + dev_err(&priv->i2c->dev, + "%s: did not find the firmware file. (%s) Please see linux/Documentation/dvb/ for more details on firmware-problems. (%d)\n", KBUILD_MODNAME, fw_file, ret); goto error; } @@ -984,11 +984,12 @@ static int tda10071_init(struct dvb_frontend *fe) if (ret) goto error_release_firmware; - dev_info(&priv->i2c->dev, "%s: found a '%s' in cold state, " \ - "will try to load a firmware\n", KBUILD_MODNAME, - tda10071_ops.info.name); - dev_info(&priv->i2c->dev, "%s: downloading firmware from " \ - "file '%s'\n", KBUILD_MODNAME, fw_file); + dev_info(&priv->i2c->dev, + "%s: found a '%s' in cold state, will try to load a firmware\n", + KBUILD_MODNAME, tda10071_ops.info.name); + dev_info(&priv->i2c->dev, + "%s: downloading firmware from file '%s'\n", + KBUILD_MODNAME, fw_file); /* do not download last byte */ fw_size = fw->size - 1; @@ -1002,8 +1003,8 @@ static int tda10071_init(struct dvb_frontend *fe) ret = tda10071_wr_regs(priv, 0xfa, (u8 *) &fw->data[fw_size - remaining], len); if (ret) { - dev_err(&priv->i2c->dev, "%s: firmware " \ - "download failed=%d\n", + dev_err(&priv->i2c->dev, + "%s: firmware download failed=%d\n", KBUILD_MODNAME, ret); goto error_release_firmware; } @@ -1067,12 +1068,17 @@ static int tda10071_init(struct dvb_frontend *fe) if (ret) goto error; + if (priv->cfg.tuner_i2c_addr) + tmp = priv->cfg.tuner_i2c_addr; + else + tmp = 0x14; + cmd.args[0] = CMD_TUNER_INIT; cmd.args[1] = 0x00; cmd.args[2] = 0x00; cmd.args[3] = 0x00; cmd.args[4] = 0x00; - cmd.args[5] = (priv->cfg.tuner_i2c_addr) ? priv->cfg.tuner_i2c_addr : 0x14; + cmd.args[5] = tmp; cmd.args[6] = 0x00; cmd.args[7] = 0x03; cmd.args[8] = 0x02; @@ -1212,14 +1218,14 @@ struct dvb_frontend *tda10071_attach(const struct tda10071_config *config, /* make sure demod i2c address is specified */ if (!config->demod_i2c_addr) { - dev_dbg(&i2c->dev, "%s: invalid demod i2c address!\n", __func__); + dev_dbg(&i2c->dev, "%s: invalid demod i2c address\n", __func__); ret = -EINVAL; goto error; } /* make sure tuner i2c address is specified */ if (!config->tuner_i2c_addr) { - dev_dbg(&i2c->dev, "%s: invalid tuner i2c address!\n", __func__); + dev_dbg(&i2c->dev, "%s: invalid tuner i2c address\n", __func__); ret = -EINVAL; goto error; } diff --git a/drivers/media/dvb-frontends/tda10071.h b/drivers/media/dvb-frontends/tda10071.h index f9542f6..331b5a8 100644 --- a/drivers/media/dvb-frontends/tda10071.h +++ b/drivers/media/dvb-frontends/tda10071.h @@ -79,7 +79,7 @@ extern struct dvb_frontend *tda10071_attach( static inline struct dvb_frontend *tda10071_attach( const struct tda10071_config *config, struct i2c_adapter *i2c) { - printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); + dev_warn(&i2c->dev, "%s: driver disabled by Kconfig\n", __func__); return NULL; } #endif -- cgit v1.1 From 7a541ce08ce25e2037bdc1ff2c22fbf790072466 Mon Sep 17 00:00:00 2001 From: Malcolm Priestley Date: Sat, 8 Feb 2014 13:11:16 -0300 Subject: [media] af9035: Move it913x single devices to af9035 The generic v1 and v2 devices have been all tested. IDs tested USB_PID_ITETECH_IT9135 v1 & v2 USB_PID_ITETECH_IT9135_9005 v1 USB_PID_ITETECH_IT9135_9006 v2 Current Issues There is no signal on USB_PID_ITETECH_IT9135 v2 No SNR reported all devices. All single devices tune and scan fine. All remotes tested okay. Dual device failed to register second adapter USB_PID_KWORLD_UB499_2T_T09 It is not clear what the problem is at the moment. So only single IDs are transferred in this patch. Signed-off-by: Malcolm Priestley Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/dvb-usb-v2/af9035.c | 22 ++++++++++++++++------ drivers/media/usb/dvb-usb-v2/it913x.c | 24 ------------------------ 2 files changed, 16 insertions(+), 30 deletions(-) diff --git a/drivers/media/usb/dvb-usb-v2/af9035.c b/drivers/media/usb/dvb-usb-v2/af9035.c index 8ede8ea..3825c2f 100644 --- a/drivers/media/usb/dvb-usb-v2/af9035.c +++ b/drivers/media/usb/dvb-usb-v2/af9035.c @@ -1528,12 +1528,22 @@ static const struct usb_device_id af9035_id_table[] = { { DVB_USB_DEVICE(USB_VID_TERRATEC, 0x00aa, &af9035_props, "TerraTec Cinergy T Stick (rev. 2)", NULL) }, /* IT9135 devices */ -#if 0 - { DVB_USB_DEVICE(0x048d, 0x9135, - &af9035_props, "IT9135 reference design", NULL) }, - { DVB_USB_DEVICE(0x048d, 0x9006, - &af9035_props, "IT9135 reference design", NULL) }, -#endif + { DVB_USB_DEVICE(USB_VID_ITETECH, USB_PID_ITETECH_IT9135, + &af9035_props, "ITE 9135 Generic", RC_MAP_IT913X_V1) }, + { DVB_USB_DEVICE(USB_VID_ITETECH, USB_PID_ITETECH_IT9135_9005, + &af9035_props, "ITE 9135(9005) Generic", RC_MAP_IT913X_V2) }, + { DVB_USB_DEVICE(USB_VID_ITETECH, USB_PID_ITETECH_IT9135_9006, + &af9035_props, "ITE 9135(9006) Generic", RC_MAP_IT913X_V1) }, + { DVB_USB_DEVICE(USB_VID_AVERMEDIA, USB_PID_AVERMEDIA_A835B_1835, + &af9035_props, "Avermedia A835B(1835)", RC_MAP_IT913X_V2) }, + { DVB_USB_DEVICE(USB_VID_AVERMEDIA, USB_PID_AVERMEDIA_A835B_2835, + &af9035_props, "Avermedia A835B(2835)", RC_MAP_IT913X_V2) }, + { DVB_USB_DEVICE(USB_VID_AVERMEDIA, USB_PID_AVERMEDIA_A835B_3835, + &af9035_props, "Avermedia A835B(3835)", RC_MAP_IT913X_V2) }, + { DVB_USB_DEVICE(USB_VID_AVERMEDIA, USB_PID_AVERMEDIA_A835B_4835, + &af9035_props, "Avermedia A835B(4835)", RC_MAP_IT913X_V2) }, + { DVB_USB_DEVICE(USB_VID_AVERMEDIA, USB_PID_AVERMEDIA_H335, + &af9035_props, "Avermedia H335", RC_MAP_IT913X_V2) }, /* XXX: that same ID [0ccd:0099] is used by af9015 driver too */ { DVB_USB_DEVICE(USB_VID_TERRATEC, 0x0099, &af9035_props, "TerraTec Cinergy T Stick Dual RC (rev. 2)", NULL) }, diff --git a/drivers/media/usb/dvb-usb-v2/it913x.c b/drivers/media/usb/dvb-usb-v2/it913x.c index fe95a58..78bf8fd 100644 --- a/drivers/media/usb/dvb-usb-v2/it913x.c +++ b/drivers/media/usb/dvb-usb-v2/it913x.c @@ -772,36 +772,12 @@ static const struct usb_device_id it913x_id_table[] = { { DVB_USB_DEVICE(USB_VID_KWORLD_2, USB_PID_KWORLD_UB499_2T_T09, &it913x_properties, "Kworld UB499-2T T09(IT9137)", RC_MAP_IT913X_V1) }, - { DVB_USB_DEVICE(USB_VID_ITETECH, USB_PID_ITETECH_IT9135, - &it913x_properties, "ITE 9135 Generic", - RC_MAP_IT913X_V1) }, { DVB_USB_DEVICE(USB_VID_KWORLD_2, USB_PID_SVEON_STV22_IT9137, &it913x_properties, "Sveon STV22 Dual DVB-T HDTV(IT9137)", RC_MAP_IT913X_V1) }, - { DVB_USB_DEVICE(USB_VID_ITETECH, USB_PID_ITETECH_IT9135_9005, - &it913x_properties, "ITE 9135(9005) Generic", - RC_MAP_IT913X_V2) }, - { DVB_USB_DEVICE(USB_VID_ITETECH, USB_PID_ITETECH_IT9135_9006, - &it913x_properties, "ITE 9135(9006) Generic", - RC_MAP_IT913X_V1) }, - { DVB_USB_DEVICE(USB_VID_AVERMEDIA, USB_PID_AVERMEDIA_A835B_1835, - &it913x_properties, "Avermedia A835B(1835)", - RC_MAP_IT913X_V2) }, - { DVB_USB_DEVICE(USB_VID_AVERMEDIA, USB_PID_AVERMEDIA_A835B_2835, - &it913x_properties, "Avermedia A835B(2835)", - RC_MAP_IT913X_V2) }, - { DVB_USB_DEVICE(USB_VID_AVERMEDIA, USB_PID_AVERMEDIA_A835B_3835, - &it913x_properties, "Avermedia A835B(3835)", - RC_MAP_IT913X_V2) }, - { DVB_USB_DEVICE(USB_VID_AVERMEDIA, USB_PID_AVERMEDIA_A835B_4835, - &it913x_properties, "Avermedia A835B(4835)", - RC_MAP_IT913X_V2) }, { DVB_USB_DEVICE(USB_VID_KWORLD_2, USB_PID_CTVDIGDUAL_V2, &it913x_properties, "Digital Dual TV Receiver CTVDIGDUAL_V2", RC_MAP_IT913X_V1) }, - { DVB_USB_DEVICE(USB_VID_AVERMEDIA, USB_PID_AVERMEDIA_H335, - &it913x_properties, "Avermedia H335", - RC_MAP_IT913X_V2) }, {} /* Terminating entry */ }; -- cgit v1.1 From a1310ff4c438bbdbd76dda5cbc27cc108d08d1c1 Mon Sep 17 00:00:00 2001 From: Malcolm Priestley Date: Sun, 9 Feb 2014 10:02:49 -0300 Subject: [media] af9035: add default 0x9135 slave I2C address On some devices the vendor has not set EEPROM_2ND_DEMOD_ADDR. Checks tmp is not zero after call to get EEPROM_2ND_DEMOD_ADDR and sets the default slave address of 0x3a on 0x9135 devices. Signed-off-by: Malcolm Priestley Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/dvb-usb-v2/af9035.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/media/usb/dvb-usb-v2/af9035.c b/drivers/media/usb/dvb-usb-v2/af9035.c index 3825c2f..4f682ad 100644 --- a/drivers/media/usb/dvb-usb-v2/af9035.c +++ b/drivers/media/usb/dvb-usb-v2/af9035.c @@ -576,6 +576,10 @@ static int af9035_download_firmware(struct dvb_usb_device *d, goto err; if (state->chip_type == 0x9135) { + if (!tmp) + /* default 0x9135 slave I2C address */ + tmp = 0x3a; + ret = af9035_wr_reg(d, 0x004bfb, tmp); if (ret < 0) goto err; @@ -684,6 +688,10 @@ static int af9035_read_config(struct dvb_usb_device *d) if (ret < 0) goto err; + if (!tmp && state->chip_type == 0x9135) + /* default 0x9135 slave I2C address */ + tmp = 0x3a; + state->af9033_config[1].i2c_addr = tmp; dev_dbg(&d->udev->dev, "%s: 2nd demod I2C addr=%02x\n", __func__, tmp); -- cgit v1.1 From 37973e01d1c3ddd69982907c68312bb314d2398f Mon Sep 17 00:00:00 2001 From: Malcolm Priestley Date: Sun, 9 Feb 2014 10:04:06 -0300 Subject: [media] af9035: Add remaining it913x dual ids to af9035 As follow on to patch af9035: Move it913x single devices to af9035 and patch 1. SNR is reported as db/10 values. All dual ids are added to af9035 and it913x driver disabled. it913x/it913x-fe removal patches to follow. Signed-off-by: Malcolm Priestley Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/dvb-usb-v2/af9035.c | 8 ++++++++ drivers/media/usb/dvb-usb-v2/it913x.c | 5 +++++ 2 files changed, 13 insertions(+) diff --git a/drivers/media/usb/dvb-usb-v2/af9035.c b/drivers/media/usb/dvb-usb-v2/af9035.c index 4f682ad..49e8360 100644 --- a/drivers/media/usb/dvb-usb-v2/af9035.c +++ b/drivers/media/usb/dvb-usb-v2/af9035.c @@ -1552,6 +1552,14 @@ static const struct usb_device_id af9035_id_table[] = { &af9035_props, "Avermedia A835B(4835)", RC_MAP_IT913X_V2) }, { DVB_USB_DEVICE(USB_VID_AVERMEDIA, USB_PID_AVERMEDIA_H335, &af9035_props, "Avermedia H335", RC_MAP_IT913X_V2) }, + { DVB_USB_DEVICE(USB_VID_KWORLD_2, USB_PID_KWORLD_UB499_2T_T09, + &af9035_props, "Kworld UB499-2T T09", RC_MAP_IT913X_V1) }, + { DVB_USB_DEVICE(USB_VID_KWORLD_2, USB_PID_SVEON_STV22_IT9137, + &af9035_props, "Sveon STV22 Dual DVB-T HDTV", + RC_MAP_IT913X_V1) }, + { DVB_USB_DEVICE(USB_VID_KWORLD_2, USB_PID_CTVDIGDUAL_V2, + &af9035_props, "Digital Dual TV Receiver CTVDIGDUAL_V2", + RC_MAP_IT913X_V1) }, /* XXX: that same ID [0ccd:0099] is used by af9015 driver too */ { DVB_USB_DEVICE(USB_VID_TERRATEC, 0x0099, &af9035_props, "TerraTec Cinergy T Stick Dual RC (rev. 2)", NULL) }, diff --git a/drivers/media/usb/dvb-usb-v2/it913x.c b/drivers/media/usb/dvb-usb-v2/it913x.c index 78bf8fd..39488f8b 100644 --- a/drivers/media/usb/dvb-usb-v2/it913x.c +++ b/drivers/media/usb/dvb-usb-v2/it913x.c @@ -781,6 +781,8 @@ static const struct usb_device_id it913x_id_table[] = { {} /* Terminating entry */ }; +#if 0 + MODULE_DEVICE_TABLE(usb, it913x_id_table); static struct usb_driver it913x_driver = { @@ -792,8 +794,11 @@ static struct usb_driver it913x_driver = { .id_table = it913x_id_table, }; + module_usb_driver(it913x_driver); +#endif + MODULE_AUTHOR("Malcolm Priestley "); MODULE_DESCRIPTION("it913x USB 2 Driver"); MODULE_VERSION("1.33"); -- cgit v1.1 From 14992f0185ab8efd513d71e5a546090c2d41ffd4 Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Wed, 12 Feb 2014 15:50:17 -0300 Subject: [media] af9035: use default i2c slave address for af9035 too Some device vendors has forgotten set correct slave demod I2C address to eeprom. Use default I2C address when eeprom has no address at all. Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/dvb-usb-v2/af9035.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/drivers/media/usb/dvb-usb-v2/af9035.c b/drivers/media/usb/dvb-usb-v2/af9035.c index 49e8360..1434d37 100644 --- a/drivers/media/usb/dvb-usb-v2/af9035.c +++ b/drivers/media/usb/dvb-usb-v2/af9035.c @@ -575,11 +575,11 @@ static int af9035_download_firmware(struct dvb_usb_device *d, if (ret < 0) goto err; - if (state->chip_type == 0x9135) { - if (!tmp) - /* default 0x9135 slave I2C address */ - tmp = 0x3a; + /* use default I2C address if eeprom has no address set */ + if (!tmp) + tmp = 0x3a; + if (state->chip_type == 0x9135) { ret = af9035_wr_reg(d, 0x004bfb, tmp); if (ret < 0) goto err; @@ -641,6 +641,7 @@ static int af9035_read_config(struct dvb_usb_device *d) /* demod I2C "address" */ state->af9033_config[0].i2c_addr = 0x38; + state->af9033_config[1].i2c_addr = 0x3a; state->af9033_config[0].adc_multiplier = AF9033_ADC_MULTIPLIER_2X; state->af9033_config[1].adc_multiplier = AF9033_ADC_MULTIPLIER_2X; state->af9033_config[0].ts_mode = AF9033_TS_MODE_USB; @@ -688,11 +689,9 @@ static int af9035_read_config(struct dvb_usb_device *d) if (ret < 0) goto err; - if (!tmp && state->chip_type == 0x9135) - /* default 0x9135 slave I2C address */ - tmp = 0x3a; + if (tmp) + state->af9033_config[1].i2c_addr = tmp; - state->af9033_config[1].i2c_addr = tmp; dev_dbg(&d->udev->dev, "%s: 2nd demod I2C addr=%02x\n", __func__, tmp); } -- cgit v1.1 From ec2b1ae9db5ccbb781a89e2d2156acad5ea4b270 Mon Sep 17 00:00:00 2001 From: Malcolm Priestley Date: Thu, 13 Feb 2014 18:28:28 -0300 Subject: [media] it913x: dead code Remove driver Following moving ids to af9035. This driver is no longer in use. Signed-off-by: Malcolm Priestley Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/dvb-usb-v2/Kconfig | 7 - drivers/media/usb/dvb-usb-v2/Makefile | 3 - drivers/media/usb/dvb-usb-v2/it913x.c | 809 ---------------------------------- 3 files changed, 819 deletions(-) delete mode 100644 drivers/media/usb/dvb-usb-v2/it913x.c diff --git a/drivers/media/usb/dvb-usb-v2/Kconfig b/drivers/media/usb/dvb-usb-v2/Kconfig index 2059d0c8..bfb7378 100644 --- a/drivers/media/usb/dvb-usb-v2/Kconfig +++ b/drivers/media/usb/dvb-usb-v2/Kconfig @@ -100,13 +100,6 @@ config DVB_USB_GL861 Say Y here to support the MSI Megasky 580 (55801) DVB-T USB2.0 receiver with USB ID 0db0:5581. -config DVB_USB_IT913X - tristate "ITE IT913X DVB-T USB2.0 support" - depends on DVB_USB_V2 - select DVB_IT913X_FE - help - Say Y here to support the ITE IT913X DVB-T USB2.0 - config DVB_USB_LME2510 tristate "LME DM04/QQBOX DVB-S USB2.0 support" depends on DVB_USB_V2 diff --git a/drivers/media/usb/dvb-usb-v2/Makefile b/drivers/media/usb/dvb-usb-v2/Makefile index 2c06714..bc38f03 100644 --- a/drivers/media/usb/dvb-usb-v2/Makefile +++ b/drivers/media/usb/dvb-usb-v2/Makefile @@ -22,9 +22,6 @@ obj-$(CONFIG_DVB_USB_CE6230) += dvb-usb-ce6230.o dvb-usb-ec168-objs := ec168.o obj-$(CONFIG_DVB_USB_EC168) += dvb-usb-ec168.o -dvb-usb-it913x-objs := it913x.o -obj-$(CONFIG_DVB_USB_IT913X) += dvb-usb-it913x.o - dvb-usb-lmedm04-objs := lmedm04.o obj-$(CONFIG_DVB_USB_LME2510) += dvb-usb-lmedm04.o diff --git a/drivers/media/usb/dvb-usb-v2/it913x.c b/drivers/media/usb/dvb-usb-v2/it913x.c deleted file mode 100644 index 39488f8b..0000000 --- a/drivers/media/usb/dvb-usb-v2/it913x.c +++ /dev/null @@ -1,809 +0,0 @@ -/* - * DVB USB compliant linux driver for ITE IT9135 and IT9137 - * - * Copyright (C) 2011 Malcolm Priestley (tvboxspy@gmail.com) - * IT9135 (C) ITE Tech Inc. - * IT9137 (C) ITE Tech Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License Version 2, as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - * - * - * see Documentation/dvb/README.dvb-usb for more information - * see Documentation/dvb/it9137.txt for firmware information - * - */ -#define DVB_USB_LOG_PREFIX "it913x" - -#include -#include -#include - -#include "dvb_usb.h" -#include "it913x-fe.h" - -/* debug */ -static int dvb_usb_it913x_debug; -#define it_debug(var, level, args...) \ - do { if ((var & level)) pr_debug(DVB_USB_LOG_PREFIX": " args); \ -} while (0) -#define deb_info(level, args...) it_debug(dvb_usb_it913x_debug, level, args) -#define info(args...) pr_info(DVB_USB_LOG_PREFIX": " args) - -module_param_named(debug, dvb_usb_it913x_debug, int, 0644); -MODULE_PARM_DESC(debug, "set debugging level (1=info (or-able))."); - -static int dvb_usb_it913x_firmware; -module_param_named(firmware, dvb_usb_it913x_firmware, int, 0644); -MODULE_PARM_DESC(firmware, "set firmware 0=auto "\ - "1=IT9137 2=IT9135 V1 3=IT9135 V2"); -#define FW_IT9137 "dvb-usb-it9137-01.fw" -#define FW_IT9135_V1 "dvb-usb-it9135-01.fw" -#define FW_IT9135_V2 "dvb-usb-it9135-02.fw" - -DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); - -struct it913x_state { - struct ite_config it913x_config; - u8 pid_filter_onoff; - bool proprietary_ir; - int cmd_counter; -}; - -static u16 check_sum(u8 *p, u8 len) -{ - u16 sum = 0; - u8 i = 1; - while (i < len) - sum += (i++ & 1) ? (*p++) << 8 : *p++; - return ~sum; -} - -static int it913x_io(struct dvb_usb_device *d, u8 mode, u8 pro, - u8 cmd, u32 reg, u8 addr, u8 *data, u8 len) -{ - struct it913x_state *st = d->priv; - int ret = 0, i, buf_size = 1; - u8 *buff; - u8 rlen; - u16 chk_sum; - - buff = kzalloc(256, GFP_KERNEL); - if (!buff) { - info("USB Buffer Failed"); - return -ENOMEM; - } - - buff[buf_size++] = pro; - buff[buf_size++] = cmd; - buff[buf_size++] = st->cmd_counter; - - switch (mode) { - case READ_LONG: - case WRITE_LONG: - buff[buf_size++] = len; - buff[buf_size++] = 2; - buff[buf_size++] = (reg >> 24); - buff[buf_size++] = (reg >> 16) & 0xff; - buff[buf_size++] = (reg >> 8) & 0xff; - buff[buf_size++] = reg & 0xff; - break; - case READ_SHORT: - buff[buf_size++] = addr; - break; - case WRITE_SHORT: - buff[buf_size++] = len; - buff[buf_size++] = addr; - buff[buf_size++] = (reg >> 8) & 0xff; - buff[buf_size++] = reg & 0xff; - break; - case READ_DATA: - case WRITE_DATA: - break; - case WRITE_CMD: - mode = 7; - break; - default: - kfree(buff); - return -EINVAL; - } - - if (mode & 1) { - for (i = 0; i < len ; i++) - buff[buf_size++] = data[i]; - } - chk_sum = check_sum(&buff[1], buf_size); - - buff[buf_size++] = chk_sum >> 8; - buff[0] = buf_size; - buff[buf_size++] = (chk_sum & 0xff); - - ret = dvb_usbv2_generic_rw(d, buff, buf_size, buff, (mode & 1) ? - 5 : len + 5); - if (ret < 0) - goto error; - - rlen = (mode & 0x1) ? 0x1 : len; - - if (mode & 1) - ret = buff[2]; - else - memcpy(data, &buff[3], rlen); - - st->cmd_counter++; - -error: kfree(buff); - - return ret; -} - -static int it913x_wr_reg(struct dvb_usb_device *d, u8 pro, u32 reg , u8 data) -{ - int ret; - u8 b[1]; - b[0] = data; - ret = it913x_io(d, WRITE_LONG, pro, - CMD_DEMOD_WRITE, reg, 0, b, sizeof(b)); - - return ret; -} - -static int it913x_read_reg(struct dvb_usb_device *d, u32 reg) -{ - int ret; - u8 data[1]; - - ret = it913x_io(d, READ_LONG, DEV_0, - CMD_DEMOD_READ, reg, 0, &data[0], sizeof(data)); - - return (ret < 0) ? ret : data[0]; -} - -static int it913x_query(struct dvb_usb_device *d, u8 pro) -{ - struct it913x_state *st = d->priv; - int ret, i; - u8 data[4]; - u8 ver; - - for (i = 0; i < 5; i++) { - ret = it913x_io(d, READ_LONG, pro, CMD_DEMOD_READ, - 0x1222, 0, &data[0], 3); - ver = data[0]; - if (ver > 0 && ver < 3) - break; - msleep(100); - } - - if (ver < 1 || ver > 2) { - info("Failed to identify chip version applying 1"); - st->it913x_config.chip_ver = 0x1; - st->it913x_config.chip_type = 0x9135; - return 0; - } - - st->it913x_config.chip_ver = ver; - st->it913x_config.chip_type = (u16)(data[2] << 8) + data[1]; - - info("Chip Version=%02x Chip Type=%04x", st->it913x_config.chip_ver, - st->it913x_config.chip_type); - - ret = it913x_io(d, READ_SHORT, pro, - CMD_QUERYINFO, 0, 0x1, &data[0], 4); - - st->it913x_config.firmware = (data[0] << 24) | (data[1] << 16) | - (data[2] << 8) | data[3]; - - return ret; -} - -static int it913x_pid_filter_ctrl(struct dvb_usb_adapter *adap, int onoff) -{ - struct dvb_usb_device *d = adap_to_d(adap); - struct it913x_state *st = adap_to_priv(adap); - int ret; - u8 pro = (adap->id == 0) ? DEV_0_DMOD : DEV_1_DMOD; - - mutex_lock(&d->i2c_mutex); - - deb_info(1, "PID_C (%02x)", onoff); - - st->pid_filter_onoff = adap->pid_filtering; - ret = it913x_wr_reg(d, pro, PID_EN, st->pid_filter_onoff); - - mutex_unlock(&d->i2c_mutex); - return ret; -} - -static int it913x_pid_filter(struct dvb_usb_adapter *adap, - int index, u16 pid, int onoff) -{ - struct dvb_usb_device *d = adap_to_d(adap); - struct it913x_state *st = adap_to_priv(adap); - int ret; - u8 pro = (adap->id == 0) ? DEV_0_DMOD : DEV_1_DMOD; - - mutex_lock(&d->i2c_mutex); - - deb_info(1, "PID_F (%02x)", onoff); - - ret = it913x_wr_reg(d, pro, PID_LSB, (u8)(pid & 0xff)); - - ret |= it913x_wr_reg(d, pro, PID_MSB, (u8)(pid >> 8)); - - ret |= it913x_wr_reg(d, pro, PID_INX_EN, (u8)onoff); - - ret |= it913x_wr_reg(d, pro, PID_INX, (u8)(index & 0x1f)); - - if (d->udev->speed == USB_SPEED_HIGH && pid == 0x2000) { - ret |= it913x_wr_reg(d , pro, PID_EN, !onoff); - st->pid_filter_onoff = !onoff; - } else - st->pid_filter_onoff = - adap->pid_filtering; - - mutex_unlock(&d->i2c_mutex); - return 0; -} - - -static int it913x_return_status(struct dvb_usb_device *d) -{ - struct it913x_state *st = d->priv; - int ret = it913x_query(d, DEV_0); - if (st->it913x_config.firmware > 0) - info("Firmware Version %d", st->it913x_config.firmware); - - return ret; -} - -static int it913x_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msg[], - int num) -{ - struct dvb_usb_device *d = i2c_get_adapdata(adap); - static u8 data[256]; - int ret; - u32 reg; - u8 pro; - - mutex_lock(&d->i2c_mutex); - - deb_info(2, "num of messages %d address %02x", num, msg[0].addr); - - pro = (msg[0].addr & 0x2) ? DEV_0_DMOD : 0x0; - pro |= (msg[0].addr & 0x20) ? DEV_1 : DEV_0; - memcpy(data, msg[0].buf, msg[0].len); - reg = (data[0] << 24) + (data[1] << 16) + - (data[2] << 8) + data[3]; - if (num == 2) { - ret = it913x_io(d, READ_LONG, pro, - CMD_DEMOD_READ, reg, 0, data, msg[1].len); - memcpy(msg[1].buf, data, msg[1].len); - } else - ret = it913x_io(d, WRITE_LONG, pro, CMD_DEMOD_WRITE, - reg, 0, &data[4], msg[0].len - 4); - - mutex_unlock(&d->i2c_mutex); - - return ret; -} - -static u32 it913x_i2c_func(struct i2c_adapter *adapter) -{ - return I2C_FUNC_I2C; -} - -static struct i2c_algorithm it913x_i2c_algo = { - .master_xfer = it913x_i2c_xfer, - .functionality = it913x_i2c_func, -}; - -/* Callbacks for DVB USB */ -#if IS_ENABLED(CONFIG_RC_CORE) -static int it913x_rc_query(struct dvb_usb_device *d) -{ - u8 ibuf[4]; - int ret; - u32 key; - /* Avoid conflict with frontends*/ - mutex_lock(&d->i2c_mutex); - - ret = it913x_io(d, READ_LONG, PRO_LINK, CMD_IR_GET, - 0, 0, &ibuf[0], sizeof(ibuf)); - - if ((ibuf[2] + ibuf[3]) == 0xff) { - key = ibuf[2]; - key += ibuf[0] << 16; - key += ibuf[1] << 8; - deb_info(1, "NEC Extended Key =%08x", key); - if (d->rc_dev != NULL) - rc_keydown(d->rc_dev, key, 0); - } - - mutex_unlock(&d->i2c_mutex); - - return ret; -} - -static int it913x_get_rc_config(struct dvb_usb_device *d, struct dvb_usb_rc *rc) -{ - struct it913x_state *st = d->priv; - - if (st->proprietary_ir == false) { - rc->map_name = NULL; - return 0; - } - - rc->allowed_protos = RC_BIT_NEC; - rc->query = it913x_rc_query; - rc->interval = 250; - - return 0; -} -#else - #define it913x_get_rc_config NULL -#endif - -/* Firmware sets raw */ -static const char fw_it9135_v1[] = FW_IT9135_V1; -static const char fw_it9135_v2[] = FW_IT9135_V2; -static const char fw_it9137[] = FW_IT9137; - -static void ite_get_firmware_name(struct dvb_usb_device *d, - const char **name) -{ - struct it913x_state *st = d->priv; - int sw; - /* auto switch */ - if (le16_to_cpu(d->udev->descriptor.idVendor) == USB_VID_KWORLD_2) - sw = IT9137_FW; - else if (st->it913x_config.chip_ver == 1) - sw = IT9135_V1_FW; - else - sw = IT9135_V2_FW; - - /* force switch */ - if (dvb_usb_it913x_firmware != IT9135_AUTO) - sw = dvb_usb_it913x_firmware; - - switch (sw) { - case IT9135_V1_FW: - st->it913x_config.firmware_ver = 1; - st->it913x_config.adc_x2 = 1; - st->it913x_config.read_slevel = false; - *name = fw_it9135_v1; - break; - case IT9135_V2_FW: - st->it913x_config.firmware_ver = 1; - st->it913x_config.adc_x2 = 1; - st->it913x_config.read_slevel = false; - *name = fw_it9135_v2; - switch (st->it913x_config.tuner_id_0) { - case IT9135_61: - case IT9135_62: - break; - default: - info("Unknown tuner ID applying default 0x60"); - case IT9135_60: - st->it913x_config.tuner_id_0 = IT9135_60; - } - break; - case IT9137_FW: - default: - st->it913x_config.firmware_ver = 0; - st->it913x_config.adc_x2 = 0; - st->it913x_config.read_slevel = true; - *name = fw_it9137; - } - - return; -} - -#define TS_MPEG_PKT_SIZE 188 -#define EP_LOW 21 -#define TS_BUFFER_SIZE_PID (EP_LOW*TS_MPEG_PKT_SIZE) -#define EP_HIGH 348 -#define TS_BUFFER_SIZE_MAX (EP_HIGH*TS_MPEG_PKT_SIZE) - -static int it913x_get_stream_config(struct dvb_frontend *fe, u8 *ts_type, - struct usb_data_stream_properties *stream) -{ - struct dvb_usb_adapter *adap = fe_to_adap(fe); - if (adap->pid_filtering) - stream->u.bulk.buffersize = TS_BUFFER_SIZE_PID; - else - stream->u.bulk.buffersize = TS_BUFFER_SIZE_MAX; - - return 0; -} - -static int it913x_select_config(struct dvb_usb_device *d) -{ - struct it913x_state *st = d->priv; - int ret, reg; - - ret = it913x_return_status(d); - if (ret < 0) - return ret; - - if (st->it913x_config.chip_ver == 0x02 - && st->it913x_config.chip_type == 0x9135) - reg = it913x_read_reg(d, 0x461d); - else - reg = it913x_read_reg(d, 0x461b); - - if (reg < 0) - return reg; - - if (reg == 0) { - st->it913x_config.dual_mode = 0; - st->it913x_config.tuner_id_0 = IT9135_38; - st->proprietary_ir = true; - } else { - /* TS mode */ - reg = it913x_read_reg(d, 0x49c5); - if (reg < 0) - return reg; - st->it913x_config.dual_mode = reg; - - /* IR mode type */ - reg = it913x_read_reg(d, 0x49ac); - if (reg < 0) - return reg; - if (reg == 5) { - info("Remote propriety (raw) mode"); - st->proprietary_ir = true; - } else if (reg == 1) { - info("Remote HID mode NOT SUPPORTED"); - st->proprietary_ir = false; - } - - /* Tuner_id */ - reg = it913x_read_reg(d, 0x49d0); - if (reg < 0) - return reg; - st->it913x_config.tuner_id_0 = reg; - } - - info("Dual mode=%x Tuner Type=%x", st->it913x_config.dual_mode, - st->it913x_config.tuner_id_0); - - return ret; -} - -static int it913x_streaming_ctrl(struct dvb_frontend *fe, int onoff) -{ - struct dvb_usb_adapter *adap = fe_to_adap(fe); - struct dvb_usb_device *d = adap_to_d(adap); - struct it913x_state *st = fe_to_priv(fe); - int ret = 0; - u8 pro = (adap->id == 0) ? DEV_0_DMOD : DEV_1_DMOD; - - deb_info(1, "STM (%02x)", onoff); - - if (!onoff) { - mutex_lock(&d->i2c_mutex); - - ret = it913x_wr_reg(d, pro, PID_RST, 0x1); - - mutex_unlock(&d->i2c_mutex); - st->pid_filter_onoff = - adap->pid_filtering; - - } - - return ret; -} - -static int it913x_identify_state(struct dvb_usb_device *d, const char **name) -{ - struct it913x_state *st = d->priv; - int ret; - u8 reg; - - /* Read and select config */ - ret = it913x_select_config(d); - if (ret < 0) - return ret; - - ite_get_firmware_name(d, name); - - if (st->it913x_config.firmware > 0) - return WARM; - - if (st->it913x_config.dual_mode) { - st->it913x_config.tuner_id_1 = it913x_read_reg(d, 0x49e0); - ret = it913x_wr_reg(d, DEV_0, GPIOH1_EN, 0x1); - ret |= it913x_wr_reg(d, DEV_0, GPIOH1_ON, 0x1); - ret |= it913x_wr_reg(d, DEV_0, GPIOH1_O, 0x1); - msleep(50); - ret |= it913x_wr_reg(d, DEV_0, GPIOH1_O, 0x0); - msleep(50); - reg = it913x_read_reg(d, GPIOH1_O); - if (reg == 0) { - ret |= it913x_wr_reg(d, DEV_0, GPIOH1_O, 0x1); - ret |= it913x_return_status(d); - if (ret != 0) - ret = it913x_wr_reg(d, DEV_0, - GPIOH1_O, 0x0); - } - } - - reg = it913x_read_reg(d, IO_MUX_POWER_CLK); - - if (st->it913x_config.dual_mode) { - ret |= it913x_wr_reg(d, DEV_0, 0x4bfb, CHIP2_I2C_ADDR); - if (st->it913x_config.firmware_ver == 1) - ret |= it913x_wr_reg(d, DEV_0, 0xcfff, 0x1); - else - ret |= it913x_wr_reg(d, DEV_0, CLK_O_EN, 0x1); - } else { - ret |= it913x_wr_reg(d, DEV_0, 0x4bfb, 0x0); - if (st->it913x_config.firmware_ver == 1) - ret |= it913x_wr_reg(d, DEV_0, 0xcfff, 0x0); - else - ret |= it913x_wr_reg(d, DEV_0, CLK_O_EN, 0x0); - } - - ret |= it913x_wr_reg(d, DEV_0, I2C_CLK, I2C_CLK_100); - - return (ret < 0) ? ret : COLD; -} - -static int it913x_download_firmware(struct dvb_usb_device *d, - const struct firmware *fw) -{ - struct it913x_state *st = d->priv; - int ret = 0, i = 0, pos = 0; - u8 packet_size, min_pkt; - u8 *fw_data; - - ret = it913x_wr_reg(d, DEV_0, I2C_CLK, I2C_CLK_100); - - info("FRM Starting Firmware Download"); - - /* Multi firmware loader */ - /* This uses scatter write firmware headers */ - /* The firmware must start with 03 XX 00 */ - /* and be the extact firmware length */ - - if (st->it913x_config.chip_ver == 2) - min_pkt = 0x11; - else - min_pkt = 0x19; - - while (i <= fw->size) { - if (((fw->data[i] == 0x3) && (fw->data[i + 2] == 0x0)) - || (i == fw->size)) { - packet_size = i - pos; - if ((packet_size > min_pkt) || (i == fw->size)) { - fw_data = (u8 *)(fw->data + pos); - pos += packet_size; - if (packet_size > 0) { - ret = it913x_io(d, WRITE_DATA, - DEV_0, CMD_SCATTER_WRITE, 0, - 0, fw_data, packet_size); - if (ret < 0) - break; - } - udelay(1000); - } - } - i++; - } - - if (ret < 0) - info("FRM Firmware Download Failed (%d)" , ret); - else - info("FRM Firmware Download Completed - Resetting Device"); - - msleep(30); - - ret = it913x_io(d, WRITE_CMD, DEV_0, CMD_BOOT, 0, 0, NULL, 0); - if (ret < 0) - info("FRM Device not responding to reboot"); - - ret = it913x_return_status(d); - if (st->it913x_config.firmware == 0) { - info("FRM Failed to reboot device"); - return -ENODEV; - } - - msleep(30); - - ret = it913x_wr_reg(d, DEV_0, I2C_CLK, I2C_CLK_400); - - msleep(30); - - /* Tuner function */ - if (st->it913x_config.dual_mode) - ret |= it913x_wr_reg(d, DEV_0_DMOD , 0xec4c, 0xa0); - else - ret |= it913x_wr_reg(d, DEV_0_DMOD , 0xec4c, 0x68); - - if ((st->it913x_config.chip_ver == 1) && - (st->it913x_config.chip_type == 0x9135)) { - ret |= it913x_wr_reg(d, DEV_0, PADODPU, 0x0); - ret |= it913x_wr_reg(d, DEV_0, AGC_O_D, 0x0); - if (st->it913x_config.dual_mode) { - ret |= it913x_wr_reg(d, DEV_1, PADODPU, 0x0); - ret |= it913x_wr_reg(d, DEV_1, AGC_O_D, 0x0); - } - } - - return (ret < 0) ? -ENODEV : 0; -} - -static int it913x_name(struct dvb_usb_adapter *adap) -{ - struct dvb_usb_device *d = adap_to_d(adap); - const char *desc = d->name; - char *fe_name[] = {"_1", "_2", "_3", "_4"}; - char *name = adap->fe[0]->ops.info.name; - - strlcpy(name, desc, 128); - strlcat(name, fe_name[adap->id], 128); - - return 0; -} - -static int it913x_frontend_attach(struct dvb_usb_adapter *adap) -{ - struct dvb_usb_device *d = adap_to_d(adap); - struct it913x_state *st = d->priv; - int ret = 0; - u8 adap_addr = I2C_BASE_ADDR + (adap->id << 5); - u16 ep_size = (adap->pid_filtering) ? TS_BUFFER_SIZE_PID / 4 : - TS_BUFFER_SIZE_MAX / 4; - u8 pkt_size = 0x80; - - if (d->udev->speed != USB_SPEED_HIGH) - pkt_size = 0x10; - - st->it913x_config.adf = it913x_read_reg(d, IO_MUX_POWER_CLK); - - adap->fe[0] = dvb_attach(it913x_fe_attach, - &d->i2c_adap, adap_addr, &st->it913x_config); - - if (adap->id == 0 && adap->fe[0]) { - it913x_wr_reg(d, DEV_0_DMOD, MP2_SW_RST, 0x1); - it913x_wr_reg(d, DEV_0_DMOD, MP2IF2_SW_RST, 0x1); - it913x_wr_reg(d, DEV_0, EP0_TX_EN, 0x0f); - it913x_wr_reg(d, DEV_0, EP0_TX_NAK, 0x1b); - if (st->proprietary_ir == false) /* Enable endpoint 3 */ - it913x_wr_reg(d, DEV_0, EP0_TX_EN, 0x3f); - else - it913x_wr_reg(d, DEV_0, EP0_TX_EN, 0x2f); - it913x_wr_reg(d, DEV_0, EP4_TX_LEN_LSB, - ep_size & 0xff); - it913x_wr_reg(d, DEV_0, EP4_TX_LEN_MSB, ep_size >> 8); - ret = it913x_wr_reg(d, DEV_0, EP4_MAX_PKT, pkt_size); - } else if (adap->id == 1 && adap->fe[0]) { - if (st->proprietary_ir == false) - it913x_wr_reg(d, DEV_0, EP0_TX_EN, 0x7f); - else - it913x_wr_reg(d, DEV_0, EP0_TX_EN, 0x6f); - it913x_wr_reg(d, DEV_0, EP5_TX_LEN_LSB, - ep_size & 0xff); - it913x_wr_reg(d, DEV_0, EP5_TX_LEN_MSB, ep_size >> 8); - it913x_wr_reg(d, DEV_0, EP5_MAX_PKT, pkt_size); - it913x_wr_reg(d, DEV_0_DMOD, MP2IF2_EN, 0x1); - it913x_wr_reg(d, DEV_1_DMOD, MP2IF_SERIAL, 0x1); - it913x_wr_reg(d, DEV_1, TOP_HOSTB_SER_MODE, 0x1); - it913x_wr_reg(d, DEV_0_DMOD, TSIS_ENABLE, 0x1); - it913x_wr_reg(d, DEV_0_DMOD, MP2_SW_RST, 0x0); - it913x_wr_reg(d, DEV_0_DMOD, MP2IF2_SW_RST, 0x0); - it913x_wr_reg(d, DEV_0_DMOD, MP2IF2_HALF_PSB, 0x0); - it913x_wr_reg(d, DEV_0_DMOD, MP2IF_STOP_EN, 0x1); - it913x_wr_reg(d, DEV_1_DMOD, MPEG_FULL_SPEED, 0x0); - ret = it913x_wr_reg(d, DEV_1_DMOD, MP2IF_STOP_EN, 0x0); - } else - return -ENODEV; - - ret |= it913x_name(adap); - - return ret; -} - -/* DVB USB Driver */ -static int it913x_get_adapter_count(struct dvb_usb_device *d) -{ - struct it913x_state *st = d->priv; - if (st->it913x_config.dual_mode) - return 2; - return 1; -} - -static struct dvb_usb_device_properties it913x_properties = { - .driver_name = KBUILD_MODNAME, - .owner = THIS_MODULE, - .bInterfaceNumber = 0, - .generic_bulk_ctrl_endpoint = 0x02, - .generic_bulk_ctrl_endpoint_response = 0x81, - - .adapter_nr = adapter_nr, - .size_of_priv = sizeof(struct it913x_state), - - .identify_state = it913x_identify_state, - .i2c_algo = &it913x_i2c_algo, - - .download_firmware = it913x_download_firmware, - - .frontend_attach = it913x_frontend_attach, - .get_rc_config = it913x_get_rc_config, - .get_stream_config = it913x_get_stream_config, - .get_adapter_count = it913x_get_adapter_count, - .streaming_ctrl = it913x_streaming_ctrl, - - - .adapter = { - { - .caps = DVB_USB_ADAP_HAS_PID_FILTER| - DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF, - .pid_filter_count = 32, - .pid_filter = it913x_pid_filter, - .pid_filter_ctrl = it913x_pid_filter_ctrl, - .stream = - DVB_USB_STREAM_BULK(0x84, 10, TS_BUFFER_SIZE_MAX), - }, - { - .caps = DVB_USB_ADAP_HAS_PID_FILTER| - DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF, - .pid_filter_count = 32, - .pid_filter = it913x_pid_filter, - .pid_filter_ctrl = it913x_pid_filter_ctrl, - .stream = - DVB_USB_STREAM_BULK(0x85, 10, TS_BUFFER_SIZE_MAX), - } - } -}; - -static const struct usb_device_id it913x_id_table[] = { - { DVB_USB_DEVICE(USB_VID_KWORLD_2, USB_PID_KWORLD_UB499_2T_T09, - &it913x_properties, "Kworld UB499-2T T09(IT9137)", - RC_MAP_IT913X_V1) }, - { DVB_USB_DEVICE(USB_VID_KWORLD_2, USB_PID_SVEON_STV22_IT9137, - &it913x_properties, "Sveon STV22 Dual DVB-T HDTV(IT9137)", - RC_MAP_IT913X_V1) }, - { DVB_USB_DEVICE(USB_VID_KWORLD_2, USB_PID_CTVDIGDUAL_V2, - &it913x_properties, "Digital Dual TV Receiver CTVDIGDUAL_V2", - RC_MAP_IT913X_V1) }, - {} /* Terminating entry */ -}; - -#if 0 - -MODULE_DEVICE_TABLE(usb, it913x_id_table); - -static struct usb_driver it913x_driver = { - .name = KBUILD_MODNAME, - .probe = dvb_usbv2_probe, - .disconnect = dvb_usbv2_disconnect, - .suspend = dvb_usbv2_suspend, - .resume = dvb_usbv2_resume, - .id_table = it913x_id_table, -}; - - -module_usb_driver(it913x_driver); - -#endif - -MODULE_AUTHOR("Malcolm Priestley "); -MODULE_DESCRIPTION("it913x USB 2 Driver"); -MODULE_VERSION("1.33"); -MODULE_LICENSE("GPL"); -MODULE_FIRMWARE(FW_IT9135_V1); -MODULE_FIRMWARE(FW_IT9135_V2); -MODULE_FIRMWARE(FW_IT9137); - -- cgit v1.1 From 182f3fe92967d2287c1eab11bafe86a896fda949 Mon Sep 17 00:00:00 2001 From: Malcolm Priestley Date: Thu, 13 Feb 2014 18:29:33 -0300 Subject: [media] it913x-fe: Dead code remove driver This driver has been replaced by af9033 and tuner_it913x Signed-off-by: Malcolm Priestley Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/Kconfig | 8 - drivers/media/dvb-frontends/Makefile | 1 - drivers/media/dvb-frontends/it913x-fe-priv.h | 1051 -------------------------- drivers/media/dvb-frontends/it913x-fe.c | 1045 ------------------------- drivers/media/dvb-frontends/it913x-fe.h | 237 ------ 5 files changed, 2342 deletions(-) delete mode 100644 drivers/media/dvb-frontends/it913x-fe-priv.h delete mode 100644 drivers/media/dvb-frontends/it913x-fe.c delete mode 100644 drivers/media/dvb-frontends/it913x-fe.h diff --git a/drivers/media/dvb-frontends/Kconfig b/drivers/media/dvb-frontends/Kconfig index dd12a1e..4433071 100644 --- a/drivers/media/dvb-frontends/Kconfig +++ b/drivers/media/dvb-frontends/Kconfig @@ -733,14 +733,6 @@ config DVB_IX2505V help A DVB-S tuner module. Say Y when you want to support this frontend. -config DVB_IT913X_FE - tristate "it913x frontend and it9137 tuner" - depends on DVB_CORE && I2C - default m if !MEDIA_SUBDRV_AUTOSELECT - help - A DVB-T tuner module. - Say Y when you want to support this frontend. - config DVB_M88RS2000 tristate "M88RS2000 DVB-S demodulator and tuner" depends on DVB_CORE && I2C diff --git a/drivers/media/dvb-frontends/Makefile b/drivers/media/dvb-frontends/Makefile index 0c75a6a..b5815c8 100644 --- a/drivers/media/dvb-frontends/Makefile +++ b/drivers/media/dvb-frontends/Makefile @@ -98,7 +98,6 @@ obj-$(CONFIG_DVB_STV0367) += stv0367.o obj-$(CONFIG_DVB_CXD2820R) += cxd2820r.o obj-$(CONFIG_DVB_DRXK) += drxk.o obj-$(CONFIG_DVB_TDA18271C2DD) += tda18271c2dd.o -obj-$(CONFIG_DVB_IT913X_FE) += it913x-fe.o obj-$(CONFIG_DVB_A8293) += a8293.o obj-$(CONFIG_DVB_TDA10071) += tda10071.o obj-$(CONFIG_DVB_RTL2830) += rtl2830.o diff --git a/drivers/media/dvb-frontends/it913x-fe-priv.h b/drivers/media/dvb-frontends/it913x-fe-priv.h deleted file mode 100644 index eb6fd8a..0000000 --- a/drivers/media/dvb-frontends/it913x-fe-priv.h +++ /dev/null @@ -1,1051 +0,0 @@ - -struct it913xset { u32 pro; - u32 address; - u8 reg[15]; - u8 count; -}; - -struct adctable { u32 adcFrequency; - u32 bandwidth; - u32 coeff_1_2048; - u32 coeff_1_4096; - u32 coeff_1_8191; - u32 coeff_1_8192; - u32 coeff_1_8193; - u32 coeff_2_2k; - u32 coeff_2_4k; - u32 coeff_2_8k; - u16 bfsfcw_fftinx_ratio; - u16 fftinx_bfsfcw_ratio; -}; - -/* clock and coeff tables only table 3 is used with IT9137*/ -/* TODO other tables relate AF9035 may be removed */ -static struct adctable tab1[] = { - { 20156250, 6000000, - 0x02b8ba6e, 0x015c5d37, 0x00ae340d, 0x00ae2e9b, 0x00ae292a, - 0x015c5d37, 0x00ae2e9b, 0x0057174e, 0x02f1, 0x015c }, - { 20156250, 7000000, - 0x032cd980, 0x01966cc0, 0x00cb3cba, 0x00cb3660, 0x00cb3007, - 0x01966cc0, 0x00cb3660, 0x00659b30, 0x0285, 0x0196 }, - { 20156250, 8000000, - 0x03a0f893, 0x01d07c49, 0x00e84567, 0x00e83e25, 0x00e836e3, - 0x01d07c49, 0x00e83e25, 0x00741f12, 0x0234, 0x01d0 }, - { 20156250, 5000000, - 0x02449b5c, 0x01224dae, 0x00912b60, 0x009126d7, 0x0091224e, - 0x01224dae, 0x009126d7, 0x0048936b, 0x0387, 0x0122 } -}; - -static struct adctable tab2[] = { - { 20187500, 6000000, - 0x02b7a654, 0x015bd32a, 0x00adef04, 0x00ade995, 0x00ade426, - 0x015bd32a, 0x00ade995, 0x0056f4ca, 0x02f2, 0x015c }, - { 20187500, 7000000, - 0x032b9761, 0x0195cbb1, 0x00caec30, 0x00cae5d8, 0x00cadf81, - 0x0195cbb1, 0x00cae5d8, 0x006572ec, 0x0286, 0x0196 }, - { 20187500, 8000000, - 0x039f886f, 0x01cfc438, 0x00e7e95b, 0x00e7e21c, 0x00e7dadd, - 0x01cfc438, 0x00e7e21c, 0x0073f10e, 0x0235, 0x01d0 }, - { 20187500, 5000000, - 0x0243b546, 0x0121daa3, 0x0090f1d9, 0x0090ed51, 0x0090e8ca, - 0x0121daa3, 0x0090ed51, 0x004876a9, 0x0388, 0x0122 } - -}; - -static struct adctable tab3[] = { - { 20250000, 6000000, - 0x02b580ad, 0x015ac057, 0x00ad6597, 0x00ad602b, 0x00ad5ac1, - 0x015ac057, 0x00ad602b, 0x0056b016, 0x02f4, 0x015b }, - { 20250000, 7000000, - 0x03291620, 0x01948b10, 0x00ca4bda, 0x00ca4588, 0x00ca3f36, - 0x01948b10, 0x00ca4588, 0x006522c4, 0x0288, 0x0195 }, - { 20250000, 8000000, - 0x039cab92, 0x01ce55c9, 0x00e7321e, 0x00e72ae4, 0x00e723ab, - 0x01ce55c9, 0x00e72ae4, 0x00739572, 0x0237, 0x01ce }, - { 20250000, 5000000, - 0x0241eb3b, 0x0120f59e, 0x00907f53, 0x00907acf, 0x0090764b, - 0x0120f59e, 0x00907acf, 0x00483d67, 0x038b, 0x0121 } - -}; - -static struct adctable tab4[] = { - { 20583333, 6000000, - 0x02aa4598, 0x015522cc, 0x00aa96bb, 0x00aa9166, 0x00aa8c12, - 0x015522cc, 0x00aa9166, 0x005548b3, 0x0300, 0x0155 }, - { 20583333, 7000000, - 0x031bfbdc, 0x018dfdee, 0x00c7052f, 0x00c6fef7, 0x00c6f8bf, - 0x018dfdee, 0x00c6fef7, 0x00637f7b, 0x0293, 0x018e }, - { 20583333, 8000000, - 0x038db21f, 0x01c6d910, 0x00e373a3, 0x00e36c88, 0x00e3656d, - 0x01c6d910, 0x00e36c88, 0x0071b644, 0x0240, 0x01c7 }, - { 20583333, 5000000, - 0x02388f54, 0x011c47aa, 0x008e2846, 0x008e23d5, 0x008e1f64, - 0x011c47aa, 0x008e23d5, 0x004711ea, 0x039a, 0x011c } - -}; - -static struct adctable tab5[] = { - { 20416667, 6000000, - 0x02afd765, 0x0157ebb3, 0x00abfb39, 0x00abf5d9, 0x00abf07a, - 0x0157ebb3, 0x00abf5d9, 0x0055faed, 0x02fa, 0x0158 }, - { 20416667, 7000000, - 0x03227b4b, 0x01913da6, 0x00c8a518, 0x00c89ed3, 0x00c8988e, - 0x01913da6, 0x00c89ed3, 0x00644f69, 0x028d, 0x0191 }, - { 20416667, 8000000, - 0x03951f32, 0x01ca8f99, 0x00e54ef7, 0x00e547cc, 0x00e540a2, - 0x01ca8f99, 0x00e547cc, 0x0072a3e6, 0x023c, 0x01cb }, - { 20416667, 5000000, - 0x023d337f, 0x011e99c0, 0x008f515a, 0x008f4ce0, 0x008f4865, - 0x011e99c0, 0x008f4ce0, 0x0047a670, 0x0393, 0x011f } - -}; - -static struct adctable tab6[] = { - { 20480000, 6000000, - 0x02adb6db, 0x0156db6e, 0x00ab7312, 0x00ab6db7, 0x00ab685c, - 0x0156db6e, 0x00ab6db7, 0x0055b6db, 0x02fd, 0x0157 }, - { 20480000, 7000000, - 0x03200000, 0x01900000, 0x00c80640, 0x00c80000, 0x00c7f9c0, - 0x01900000, 0x00c80000, 0x00640000, 0x028f, 0x0190 }, - { 20480000, 8000000, - 0x03924925, 0x01c92492, 0x00e4996e, 0x00e49249, 0x00e48b25, - 0x01c92492, 0x00e49249, 0x00724925, 0x023d, 0x01c9 }, - { 20480000, 5000000, - 0x023b6db7, 0x011db6db, 0x008edfe5, 0x008edb6e, 0x008ed6f7, - 0x011db6db, 0x008edb6e, 0x00476db7, 0x0396, 0x011e } -}; - -static struct adctable tab7[] = { - { 20500000, 6000000, - 0x02ad0b99, 0x015685cc, 0x00ab4840, 0x00ab42e6, 0x00ab3d8c, - 0x015685cc, 0x00ab42e6, 0x0055a173, 0x02fd, 0x0157 }, - { 20500000, 7000000, - 0x031f3832, 0x018f9c19, 0x00c7d44b, 0x00c7ce0c, 0x00c7c7ce, - 0x018f9c19, 0x00c7ce0c, 0x0063e706, 0x0290, 0x0190 }, - { 20500000, 8000000, - 0x039164cb, 0x01c8b266, 0x00e46056, 0x00e45933, 0x00e45210, - 0x01c8b266, 0x00e45933, 0x00722c99, 0x023e, 0x01c9 }, - { 20500000, 5000000, - 0x023adeff, 0x011d6f80, 0x008ebc36, 0x008eb7c0, 0x008eb34a, - 0x011d6f80, 0x008eb7c0, 0x00475be0, 0x0396, 0x011d } - -}; - -static struct adctable tab8[] = { - { 20625000, 6000000, - 0x02a8e4bd, 0x0154725e, 0x00aa3e81, 0x00aa392f, 0x00aa33de, - 0x0154725e, 0x00aa392f, 0x00551c98, 0x0302, 0x0154 }, - { 20625000, 7000000, - 0x031a6032, 0x018d3019, 0x00c69e41, 0x00c6980c, 0x00c691d8, - 0x018d3019, 0x00c6980c, 0x00634c06, 0x0294, 0x018d }, - { 20625000, 8000000, - 0x038bdba6, 0x01c5edd3, 0x00e2fe02, 0x00e2f6ea, 0x00e2efd2, - 0x01c5edd3, 0x00e2f6ea, 0x00717b75, 0x0242, 0x01c6 }, - { 20625000, 5000000, - 0x02376948, 0x011bb4a4, 0x008ddec1, 0x008dda52, 0x008dd5e3, - 0x011bb4a4, 0x008dda52, 0x0046ed29, 0x039c, 0x011c } - -}; - -struct table { - u32 xtal; - struct adctable *table; -}; - -static struct table fe_clockTable[] = { - {12000000, tab3}, /* 12.00MHz */ - {20480000, tab6}, /* 20.48MHz */ - {36000000, tab3}, /* 36.00MHz */ - {30000000, tab1}, /* 30.00MHz */ - {26000000, tab4}, /* 26.00MHz */ - {28000000, tab5}, /* 28.00MHz */ - {32000000, tab7}, /* 32.00MHz */ - {34000000, tab2}, /* 34.00MHz */ - {24000000, tab1}, /* 24.00MHz */ - {22000000, tab8}, /* 22.00MHz */ -}; - -/* fe get */ -fe_code_rate_t fe_code[] = { - FEC_1_2, - FEC_2_3, - FEC_3_4, - FEC_5_6, - FEC_7_8, - FEC_NONE, -}; - -fe_guard_interval_t fe_gi[] = { - GUARD_INTERVAL_1_32, - GUARD_INTERVAL_1_16, - GUARD_INTERVAL_1_8, - GUARD_INTERVAL_1_4, -}; - -fe_hierarchy_t fe_hi[] = { - HIERARCHY_NONE, - HIERARCHY_1, - HIERARCHY_2, - HIERARCHY_4, -}; - -fe_transmit_mode_t fe_mode[] = { - TRANSMISSION_MODE_2K, - TRANSMISSION_MODE_8K, - TRANSMISSION_MODE_4K, -}; - -fe_modulation_t fe_con[] = { - QPSK, - QAM_16, - QAM_64, -}; - -enum { - PRIORITY_HIGH = 0, /* High-priority stream */ - PRIORITY_LOW, /* Low-priority stream */ -}; - -/* Standard demodulator functions */ -static struct it913xset set_solo_fe[] = { - {PRO_LINK, GPIOH5_EN, {0x01}, 0x01}, - {PRO_LINK, GPIOH5_ON, {0x01}, 0x01}, - {PRO_LINK, GPIOH5_O, {0x00}, 0x01}, - {PRO_LINK, GPIOH5_O, {0x01}, 0x01}, - {PRO_LINK, DVBT_INTEN, {0x04}, 0x01}, - {PRO_LINK, DVBT_ENABLE, {0x05}, 0x01}, - {PRO_DMOD, MP2IF_MPEG_PAR_MODE, {0x00}, 0x01}, - {PRO_LINK, HOSTB_MPEG_SER_MODE, {0x00}, 0x01}, - {PRO_LINK, HOSTB_MPEG_PAR_MODE, {0x00}, 0x01}, - {PRO_DMOD, DCA_UPPER_CHIP, {0x00}, 0x01}, - {PRO_LINK, HOSTB_DCA_UPPER, {0x00}, 0x01}, - {PRO_DMOD, DCA_LOWER_CHIP, {0x00}, 0x01}, - {PRO_LINK, HOSTB_DCA_LOWER, {0x00}, 0x01}, - {PRO_DMOD, DCA_PLATCH, {0x00}, 0x01}, - {PRO_DMOD, DCA_FPGA_LATCH, {0x00}, 0x01}, - {PRO_DMOD, DCA_STAND_ALONE, {0x01}, 0x01}, - {PRO_DMOD, DCA_ENABLE, {0x00}, 0x01}, - {PRO_DMOD, MP2IF_MPEG_PAR_MODE, {0x00}, 0x01}, - {PRO_DMOD, BFS_FCW, {0x00, 0x00, 0x00}, 0x03}, - {0xff, 0x0000, {0x00}, 0x00}, /* Terminating Entry */ -}; - - -static struct it913xset init_1[] = { - {PRO_LINK, LOCK3_OUT, {0x01}, 0x01}, - {PRO_LINK, PADMISCDRSR, {0x01}, 0x01}, - {PRO_LINK, PADMISCDR2, {0x00}, 0x01}, - {PRO_DMOD, 0xec57, {0x00, 0x00}, 0x02}, - {PRO_LINK, PADMISCDR4, {0x00}, 0x01}, /* Power up */ - {PRO_LINK, PADMISCDR8, {0x00}, 0x01}, - {0xff, 0x0000, {0x00}, 0x00} /* Terminating Entry */ -}; - - -/* Version 1 types */ -static struct it913xset it9135_v1[] = { - {PRO_DMOD, 0x0051, {0x01}, 0x01}, - {PRO_DMOD, 0x0070, {0x0a}, 0x01}, - {PRO_DMOD, 0x007e, {0x04}, 0x01}, - {PRO_DMOD, 0x0081, {0x0a}, 0x01}, - {PRO_DMOD, 0x008a, {0x01}, 0x01}, - {PRO_DMOD, 0x008e, {0x01}, 0x01}, - {PRO_DMOD, 0x0092, {0x06}, 0x01}, - {PRO_DMOD, 0x0099, {0x01}, 0x01}, - {PRO_DMOD, 0x009f, {0xe1}, 0x01}, - {PRO_DMOD, 0x00a0, {0xcf}, 0x01}, - {PRO_DMOD, 0x00a3, {0x01}, 0x01}, - {PRO_DMOD, 0x00a5, {0x01}, 0x01}, - {PRO_DMOD, 0x00a6, {0x01}, 0x01}, - {PRO_DMOD, 0x00a9, {0x00}, 0x01}, - {PRO_DMOD, 0x00aa, {0x01}, 0x01}, - {PRO_DMOD, 0x00b0, {0x01}, 0x01}, - {PRO_DMOD, 0x00c2, {0x05}, 0x01}, - {PRO_DMOD, 0x00c6, {0x19}, 0x01}, - {PRO_DMOD, 0xf000, {0x0f}, 0x01}, - {PRO_DMOD, 0xf016, {0x10}, 0x01}, - {PRO_DMOD, 0xf017, {0x04}, 0x01}, - {PRO_DMOD, 0xf018, {0x05}, 0x01}, - {PRO_DMOD, 0xf019, {0x04}, 0x01}, - {PRO_DMOD, 0xf01a, {0x05}, 0x01}, - {PRO_DMOD, 0xf021, {0x03}, 0x01}, - {PRO_DMOD, 0xf022, {0x0a}, 0x01}, - {PRO_DMOD, 0xf023, {0x0a}, 0x01}, - {PRO_DMOD, 0xf02b, {0x00}, 0x01}, - {PRO_DMOD, 0xf02c, {0x01}, 0x01}, - {PRO_DMOD, 0xf064, {0x03}, 0x01}, - {PRO_DMOD, 0xf065, {0xf9}, 0x01}, - {PRO_DMOD, 0xf066, {0x03}, 0x01}, - {PRO_DMOD, 0xf067, {0x01}, 0x01}, - {PRO_DMOD, 0xf06f, {0xe0}, 0x01}, - {PRO_DMOD, 0xf070, {0x03}, 0x01}, - {PRO_DMOD, 0xf072, {0x0f}, 0x01}, - {PRO_DMOD, 0xf073, {0x03}, 0x01}, - {PRO_DMOD, 0xf078, {0x00}, 0x01}, - {PRO_DMOD, 0xf087, {0x00}, 0x01}, - {PRO_DMOD, 0xf09b, {0x3f}, 0x01}, - {PRO_DMOD, 0xf09c, {0x00}, 0x01}, - {PRO_DMOD, 0xf09d, {0x20}, 0x01}, - {PRO_DMOD, 0xf09e, {0x00}, 0x01}, - {PRO_DMOD, 0xf09f, {0x0c}, 0x01}, - {PRO_DMOD, 0xf0a0, {0x00}, 0x01}, - {PRO_DMOD, 0xf130, {0x04}, 0x01}, - {PRO_DMOD, 0xf132, {0x04}, 0x01}, - {PRO_DMOD, 0xf144, {0x1a}, 0x01}, - {PRO_DMOD, 0xf146, {0x00}, 0x01}, - {PRO_DMOD, 0xf14a, {0x01}, 0x01}, - {PRO_DMOD, 0xf14c, {0x00}, 0x01}, - {PRO_DMOD, 0xf14d, {0x00}, 0x01}, - {PRO_DMOD, 0xf14f, {0x04}, 0x01}, - {PRO_DMOD, 0xf158, {0x7f}, 0x01}, - {PRO_DMOD, 0xf15a, {0x00}, 0x01}, - {PRO_DMOD, 0xf15b, {0x08}, 0x01}, - {PRO_DMOD, 0xf15d, {0x03}, 0x01}, - {PRO_DMOD, 0xf15e, {0x05}, 0x01}, - {PRO_DMOD, 0xf163, {0x05}, 0x01}, - {PRO_DMOD, 0xf166, {0x01}, 0x01}, - {PRO_DMOD, 0xf167, {0x40}, 0x01}, - {PRO_DMOD, 0xf168, {0x0f}, 0x01}, - {PRO_DMOD, 0xf17a, {0x00}, 0x01}, - {PRO_DMOD, 0xf17b, {0x00}, 0x01}, - {PRO_DMOD, 0xf183, {0x01}, 0x01}, - {PRO_DMOD, 0xf19d, {0x40}, 0x01}, - {PRO_DMOD, 0xf1bc, {0x36}, 0x01}, - {PRO_DMOD, 0xf1bd, {0x00}, 0x01}, - {PRO_DMOD, 0xf1cb, {0xa0}, 0x01}, - {PRO_DMOD, 0xf1cc, {0x01}, 0x01}, - {PRO_DMOD, 0xf204, {0x10}, 0x01}, - {PRO_DMOD, 0xf214, {0x00}, 0x01}, - {PRO_DMOD, 0xf40e, {0x0a}, 0x01}, - {PRO_DMOD, 0xf40f, {0x40}, 0x01}, - {PRO_DMOD, 0xf410, {0x08}, 0x01}, - {PRO_DMOD, 0xf55f, {0x0a}, 0x01}, - {PRO_DMOD, 0xf561, {0x15}, 0x01}, - {PRO_DMOD, 0xf562, {0x20}, 0x01}, - {PRO_DMOD, 0xf5df, {0xfb}, 0x01}, - {PRO_DMOD, 0xf5e0, {0x00}, 0x01}, - {PRO_DMOD, 0xf5e3, {0x09}, 0x01}, - {PRO_DMOD, 0xf5e4, {0x01}, 0x01}, - {PRO_DMOD, 0xf5e5, {0x01}, 0x01}, - {PRO_DMOD, 0xf5f8, {0x01}, 0x01}, - {PRO_DMOD, 0xf5fd, {0x01}, 0x01}, - {PRO_DMOD, 0xf600, {0x05}, 0x01}, - {PRO_DMOD, 0xf601, {0x08}, 0x01}, - {PRO_DMOD, 0xf602, {0x0b}, 0x01}, - {PRO_DMOD, 0xf603, {0x0e}, 0x01}, - {PRO_DMOD, 0xf604, {0x11}, 0x01}, - {PRO_DMOD, 0xf605, {0x14}, 0x01}, - {PRO_DMOD, 0xf606, {0x17}, 0x01}, - {PRO_DMOD, 0xf607, {0x1f}, 0x01}, - {PRO_DMOD, 0xf60e, {0x00}, 0x01}, - {PRO_DMOD, 0xf60f, {0x04}, 0x01}, - {PRO_DMOD, 0xf610, {0x32}, 0x01}, - {PRO_DMOD, 0xf611, {0x10}, 0x01}, - {PRO_DMOD, 0xf707, {0xfc}, 0x01}, - {PRO_DMOD, 0xf708, {0x00}, 0x01}, - {PRO_DMOD, 0xf709, {0x37}, 0x01}, - {PRO_DMOD, 0xf70a, {0x00}, 0x01}, - {PRO_DMOD, 0xf78b, {0x01}, 0x01}, - {PRO_DMOD, 0xf80f, {0x40}, 0x01}, - {PRO_DMOD, 0xf810, {0x54}, 0x01}, - {PRO_DMOD, 0xf811, {0x5a}, 0x01}, - {PRO_DMOD, 0xf905, {0x01}, 0x01}, - {PRO_DMOD, 0xfb06, {0x03}, 0x01}, - {PRO_DMOD, 0xfd8b, {0x00}, 0x01}, - {0xff, 0x0000, {0x00}, 0x00} /* Terminating Entry */ -}; - -static struct it913xset it9135_38[] = { - {PRO_DMOD, 0x0043, {0x00}, 0x01}, - {PRO_DMOD, 0x0046, {0x38}, 0x01}, - {PRO_DMOD, 0x0051, {0x01}, 0x01}, - {PRO_DMOD, 0x005f, {0x00, 0x00}, 0x02}, - {PRO_DMOD, 0x0068, {0x0a}, 0x01}, - {PRO_DMOD, 0x0070, {0x0a, 0x05, 0x02}, 0x03}, - {PRO_DMOD, 0x0075, {0x8c, 0x8c, 0x8c, 0xc8, 0x01}, 0x05}, - {PRO_DMOD, 0x007e, {0x04, 0x00}, 0x02}, - {PRO_DMOD, 0x0081, { 0x0a, 0x12, 0x02, 0x0a, 0x03, 0xc8, 0xb8, - 0xd0, 0xc3, 0x01}, 0x0a}, - {PRO_DMOD, 0x008e, {0x01}, 0x01}, - {PRO_DMOD, 0x0092, {0x06, 0x00, 0x00, 0x00, 0x00}, 0x05}, - {PRO_DMOD, 0x0099, {0x01}, 0x01}, - {PRO_DMOD, 0x009b, {0x3c, 0x28}, 0x02}, - {PRO_DMOD, 0x009f, {0xe1, 0xcf}, 0x02}, - {PRO_DMOD, 0x00a3, {0x01, 0x5a, 0x01, 0x01}, 0x04}, - {PRO_DMOD, 0x00a9, {0x00, 0x01}, 0x02}, - {PRO_DMOD, 0x00b0, {0x01}, 0x01}, - {PRO_DMOD, 0x00b3, {0x02, 0x32}, 0x02}, - {PRO_DMOD, 0x00b6, {0x14}, 0x01}, - {PRO_DMOD, 0x00c0, {0x11, 0x00, 0x05}, 0x03}, - {PRO_DMOD, 0x00c4, {0x00}, 0x01}, - {PRO_DMOD, 0x00c6, {0x19, 0x00}, 0x02}, - {PRO_DMOD, 0x00cc, {0x2e, 0x51, 0x33}, 0x03}, - {PRO_DMOD, 0x00f3, {0x05, 0x8c, 0x8c}, 0x03}, - {PRO_DMOD, 0x00f8, {0x03, 0x06, 0x06}, 0x03}, - {PRO_DMOD, 0x00fc, { 0x02, 0x02, 0x02, 0x09, 0x50, 0x7b, 0x77, - 0x00, 0x02, 0xc8, 0x05, 0x7b}, 0x0c}, - {PRO_DMOD, 0x0109, {0x02}, 0x01}, - {PRO_DMOD, 0x0115, {0x0a, 0x03, 0x02, 0x80}, 0x04}, - {PRO_DMOD, 0x011a, {0xc8, 0x7b, 0x8a, 0xa0}, 0x04}, - {PRO_DMOD, 0x0122, {0x02, 0x18, 0xc3}, 0x03}, - {PRO_DMOD, 0x0127, {0x00, 0x07}, 0x02}, - {PRO_DMOD, 0x012a, {0x53, 0x51, 0x4e, 0x43}, 0x04}, - {PRO_DMOD, 0x0137, {0x01, 0x00, 0x07, 0x00, 0x06}, 0x05}, - {PRO_DMOD, 0x013d, {0x00, 0x01, 0x5b, 0xc8, 0x59}, 0x05}, - {PRO_DMOD, 0xf000, {0x0f}, 0x01}, - {PRO_DMOD, 0xf016, {0x10, 0x04, 0x05, 0x04, 0x05}, 0x05}, - {PRO_DMOD, 0xf01f, {0x8c, 0x00, 0x03, 0x0a, 0x0a}, 0x05}, - {PRO_DMOD, 0xf029, {0x8c, 0x00, 0x00, 0x01}, 0x04}, - {PRO_DMOD, 0xf064, {0x03, 0xf9, 0x03, 0x01}, 0x04}, - {PRO_DMOD, 0xf06f, {0xe0, 0x03}, 0x02}, - {PRO_DMOD, 0xf072, {0x0f, 0x03}, 0x02}, - {PRO_DMOD, 0xf077, {0x01, 0x00}, 0x02}, - {PRO_DMOD, 0xf085, {0x00, 0x02, 0x00}, 0x03}, - {PRO_DMOD, 0xf09b, {0x3f, 0x00, 0x20, 0x00, 0x0c, 0x00}, 0x06}, - {PRO_DMOD, 0xf130, {0x04}, 0x01}, - {PRO_DMOD, 0xf132, {0x04}, 0x01}, - {PRO_DMOD, 0xf144, {0x1a}, 0x01}, - {PRO_DMOD, 0xf146, {0x00}, 0x01}, - {PRO_DMOD, 0xf14a, {0x01}, 0x01}, - {PRO_DMOD, 0xf14c, {0x00, 0x00}, 0x02}, - {PRO_DMOD, 0xf14f, {0x04}, 0x01}, - {PRO_DMOD, 0xf158, {0x7f}, 0x01}, - {PRO_DMOD, 0xf15a, {0x00, 0x08}, 0x02}, - {PRO_DMOD, 0xf15d, {0x03, 0x05}, 0x02}, - {PRO_DMOD, 0xf163, {0x05}, 0x01}, - {PRO_DMOD, 0xf166, {0x01, 0x40, 0x0f}, 0x03}, - {PRO_DMOD, 0xf17a, {0x00, 0x00}, 0x02}, - {PRO_DMOD, 0xf183, {0x01}, 0x01}, - {PRO_DMOD, 0xf19d, {0x40}, 0x01}, - {PRO_DMOD, 0xf1bc, {0x36, 0x00}, 0x02}, - {PRO_DMOD, 0xf1cb, {0xa0, 0x01}, 0x02}, - {PRO_DMOD, 0xf204, {0x10}, 0x01}, - {PRO_DMOD, 0xf214, {0x00}, 0x01}, - {PRO_DMOD, 0xf24c, {0x88, 0x95, 0x9a, 0x90}, 0x04}, - {PRO_DMOD, 0xf25a, {0x07, 0xe8, 0x03, 0xb0, 0x04}, 0x05}, - {PRO_DMOD, 0xf270, {0x01, 0x02, 0x01, 0x02}, 0x04}, - {PRO_DMOD, 0xf40e, {0x0a, 0x40, 0x08}, 0x03}, - {PRO_DMOD, 0xf55f, {0x0a}, 0x01}, - {PRO_DMOD, 0xf561, {0x15, 0x20}, 0x02}, - {PRO_DMOD, 0xf5df, {0xfb, 0x00}, 0x02}, - {PRO_DMOD, 0xf5e3, {0x09, 0x01, 0x01}, 0x03}, - {PRO_DMOD, 0xf5f8, {0x01}, 0x01}, - {PRO_DMOD, 0xf5fd, {0x01}, 0x01}, - {PRO_DMOD, 0xf600, { 0x05, 0x08, 0x0b, 0x0e, 0x11, 0x14, 0x17, - 0x1f}, 0x08}, - {PRO_DMOD, 0xf60e, {0x00, 0x04, 0x32, 0x10}, 0x04}, - {PRO_DMOD, 0xf707, {0xfc, 0x00, 0x37, 0x00}, 0x04}, - {PRO_DMOD, 0xf78b, {0x01}, 0x01}, - {PRO_DMOD, 0xf80f, {0x40, 0x54, 0x5a}, 0x03}, - {PRO_DMOD, 0xf905, {0x01}, 0x01}, - {PRO_DMOD, 0xfb06, {0x03}, 0x01}, - {PRO_DMOD, 0xfd8b, {0x00}, 0x01}, - {0xff, 0x0000, {0x00}, 0x00} /* Terminating Entry */ -}; - -static struct it913xset it9135_51[] = { - {PRO_DMOD, 0x0043, {0x00}, 0x01}, - {PRO_DMOD, 0x0046, {0x51}, 0x01}, - {PRO_DMOD, 0x0051, {0x01}, 0x01}, - {PRO_DMOD, 0x005f, {0x00, 0x00}, 0x02}, - {PRO_DMOD, 0x0068, {0x0a}, 0x01}, - {PRO_DMOD, 0x0070, {0x0a, 0x06, 0x02}, 0x03}, - {PRO_DMOD, 0x0075, {0x8c, 0x8c, 0x8c, 0xc8, 0x01}, 0x05}, - {PRO_DMOD, 0x007e, {0x04, 0x00}, 0x02}, - {PRO_DMOD, 0x0081, { 0x0a, 0x12, 0x02, 0x0a, 0x03, 0xc0, 0x96, - 0xcf, 0xc3, 0x01}, 0x0a}, - {PRO_DMOD, 0x008e, {0x01}, 0x01}, - {PRO_DMOD, 0x0092, {0x06, 0x00, 0x00, 0x00, 0x00}, 0x05}, - {PRO_DMOD, 0x0099, {0x01}, 0x01}, - {PRO_DMOD, 0x009b, {0x3c, 0x28}, 0x02}, - {PRO_DMOD, 0x009f, {0xe1, 0xcf}, 0x02}, - {PRO_DMOD, 0x00a3, {0x01, 0x5a, 0x01, 0x01}, 0x04}, - {PRO_DMOD, 0x00a9, {0x00, 0x01}, 0x02}, - {PRO_DMOD, 0x00b0, {0x01}, 0x01}, - {PRO_DMOD, 0x00b3, {0x02, 0x3c}, 0x02}, - {PRO_DMOD, 0x00b6, {0x14}, 0x01}, - {PRO_DMOD, 0x00c0, {0x11, 0x00, 0x05}, 0x03}, - {PRO_DMOD, 0x00c4, {0x00}, 0x01}, - {PRO_DMOD, 0x00c6, {0x19, 0x00}, 0x02}, - {PRO_DMOD, 0x00cc, {0x2e, 0x51, 0x33}, 0x03}, - {PRO_DMOD, 0x00f3, {0x05, 0x8c, 0x8c}, 0x03}, - {PRO_DMOD, 0x00f8, {0x03, 0x06, 0x06}, 0x03}, - {PRO_DMOD, 0x00fc, { 0x03, 0x02, 0x02, 0x09, 0x50, 0x7a, 0x77, - 0x01, 0x02, 0xb0, 0x02, 0x7a}, 0x0c}, - {PRO_DMOD, 0x0109, {0x02}, 0x01}, - {PRO_DMOD, 0x0115, {0x0a, 0x03, 0x02, 0x80}, 0x04}, - {PRO_DMOD, 0x011a, {0xc0, 0x7a, 0xac, 0x8c}, 0x04}, - {PRO_DMOD, 0x0122, {0x02, 0x70, 0xa4}, 0x03}, - {PRO_DMOD, 0x0127, {0x00, 0x07}, 0x02}, - {PRO_DMOD, 0x012a, {0x53, 0x51, 0x4e, 0x43}, 0x04}, - {PRO_DMOD, 0x0137, {0x01, 0x00, 0x07, 0x00, 0x06}, 0x05}, - {PRO_DMOD, 0x013d, {0x00, 0x01, 0x5b, 0xc0, 0x59}, 0x05}, - {PRO_DMOD, 0xf000, {0x0f}, 0x01}, - {PRO_DMOD, 0xf016, {0x10, 0x04, 0x05, 0x04, 0x05}, 0x05}, - {PRO_DMOD, 0xf01f, {0x8c, 0x00, 0x03, 0x0a, 0x0a}, 0x05}, - {PRO_DMOD, 0xf029, {0x8c, 0x00, 0x00, 0x01}, 0x04}, - {PRO_DMOD, 0xf064, {0x03, 0xf9, 0x03, 0x01}, 0x04}, - {PRO_DMOD, 0xf06f, {0xe0, 0x03}, 0x02}, - {PRO_DMOD, 0xf072, {0x0f, 0x03}, 0x02}, - {PRO_DMOD, 0xf077, {0x01, 0x00}, 0x02}, - {PRO_DMOD, 0xf085, {0xc0, 0x01, 0x00}, 0x03}, - {PRO_DMOD, 0xf09b, {0x3f, 0x00, 0x20, 0x00, 0x0c, 0x00}, 0x06}, - {PRO_DMOD, 0xf130, {0x04}, 0x01}, - {PRO_DMOD, 0xf132, {0x04}, 0x01}, - {PRO_DMOD, 0xf144, {0x1a}, 0x01}, - {PRO_DMOD, 0xf146, {0x00}, 0x01}, - {PRO_DMOD, 0xf14a, {0x01}, 0x01}, - {PRO_DMOD, 0xf14c, {0x00, 0x00}, 0x02}, - {PRO_DMOD, 0xf14f, {0x04}, 0x01}, - {PRO_DMOD, 0xf158, {0x7f}, 0x01}, - {PRO_DMOD, 0xf15a, {0x00, 0x08}, 0x02}, - {PRO_DMOD, 0xf15d, {0x03, 0x05}, 0x02}, - {PRO_DMOD, 0xf163, {0x05}, 0x01}, - {PRO_DMOD, 0xf166, {0x01, 0x40, 0x0f}, 0x03}, - {PRO_DMOD, 0xf17a, {0x00, 0x00}, 0x02}, - {PRO_DMOD, 0xf183, {0x01}, 0x01}, - {PRO_DMOD, 0xf19d, {0x40}, 0x01}, - {PRO_DMOD, 0xf1bc, {0x36, 0x00}, 0x02}, - {PRO_DMOD, 0xf1cb, {0xa0, 0x01}, 0x02}, - {PRO_DMOD, 0xf204, {0x10}, 0x01}, - {PRO_DMOD, 0xf214, {0x00}, 0x01}, - {PRO_DMOD, 0xf24c, {0x88, 0x95, 0x9a, 0x90}, 0x04}, - {PRO_DMOD, 0xf25a, {0x07, 0xe8, 0x03, 0xb0, 0x04}, 0x05}, - {PRO_DMOD, 0xf270, {0x01, 0x02, 0x01, 0x02}, 0x04}, - {PRO_DMOD, 0xf40e, {0x0a, 0x40, 0x08}, 0x03}, - {PRO_DMOD, 0xf55f, {0x0a}, 0x01}, - {PRO_DMOD, 0xf561, {0x15, 0x20}, 0x02}, - {PRO_DMOD, 0xf5df, {0xfb, 0x00}, 0x02}, - {PRO_DMOD, 0xf5e3, {0x09, 0x01, 0x01}, 0x03}, - {PRO_DMOD, 0xf5f8, {0x01}, 0x01}, - {PRO_DMOD, 0xf5fd, {0x01}, 0x01}, - {PRO_DMOD, 0xf600, { 0x05, 0x08, 0x0b, 0x0e, 0x11, 0x14, 0x17, - 0x1f}, 0x08}, - {PRO_DMOD, 0xf60e, {0x00, 0x04, 0x32, 0x10}, 0x04}, - {PRO_DMOD, 0xf707, {0xfc, 0x00, 0x37, 0x00}, 0x04}, - {PRO_DMOD, 0xf78b, {0x01}, 0x01}, - {PRO_DMOD, 0xf80f, {0x40, 0x54, 0x5a}, 0x03}, - {PRO_DMOD, 0xf905, {0x01}, 0x01}, - {PRO_DMOD, 0xfb06, {0x03}, 0x01}, - {PRO_DMOD, 0xfd8b, {0x00}, 0x01}, - {0xff, 0x0000, {0x00}, 0x00} /* Terminating Entry */ -}; - -static struct it913xset it9135_52[] = { - {PRO_DMOD, 0x0043, {0x00}, 0x01}, - {PRO_DMOD, 0x0046, {0x52}, 0x01}, - {PRO_DMOD, 0x0051, {0x01}, 0x01}, - {PRO_DMOD, 0x005f, {0x00, 0x00}, 0x02}, - {PRO_DMOD, 0x0068, {0x10}, 0x01}, - {PRO_DMOD, 0x0070, {0x0a, 0x05, 0x02}, 0x03}, - {PRO_DMOD, 0x0075, {0x8c, 0x8c, 0x8c, 0xa0, 0x01}, 0x05}, - {PRO_DMOD, 0x007e, {0x04, 0x00}, 0x02}, - {PRO_DMOD, 0x0081, { 0x0a, 0x12, 0x03, 0x0a, 0x03, 0xb3, 0x97, - 0xc0, 0x9e, 0x01}, 0x0a}, - {PRO_DMOD, 0x008e, {0x01}, 0x01}, - {PRO_DMOD, 0x0092, {0x06, 0x00, 0x00, 0x00, 0x00}, 0x05}, - {PRO_DMOD, 0x0099, {0x01}, 0x01}, - {PRO_DMOD, 0x009b, {0x3c, 0x28}, 0x02}, - {PRO_DMOD, 0x009f, {0xe1, 0xcf}, 0x02}, - {PRO_DMOD, 0x00a3, {0x01, 0x5c, 0x01, 0x01}, 0x04}, - {PRO_DMOD, 0x00a9, {0x00, 0x01}, 0x02}, - {PRO_DMOD, 0x00b0, {0x01}, 0x01}, - {PRO_DMOD, 0x00b3, {0x02, 0x3c}, 0x02}, - {PRO_DMOD, 0x00b6, {0x14}, 0x01}, - {PRO_DMOD, 0x00c0, {0x11, 0x00, 0x05}, 0x03}, - {PRO_DMOD, 0x00c4, {0x00}, 0x01}, - {PRO_DMOD, 0x00c6, {0x19, 0x00}, 0x02}, - {PRO_DMOD, 0x00cc, {0x2e, 0x51, 0x33}, 0x03}, - {PRO_DMOD, 0x00f3, {0x05, 0x91, 0x8c}, 0x03}, - {PRO_DMOD, 0x00f8, {0x03, 0x06, 0x06}, 0x03}, - {PRO_DMOD, 0x00fc, { 0x03, 0x02, 0x02, 0x09, 0x50, 0x74, 0x77, - 0x02, 0x02, 0xae, 0x02, 0x6e}, 0x0c}, - {PRO_DMOD, 0x0109, {0x02}, 0x01}, - {PRO_DMOD, 0x0115, {0x0a, 0x03, 0x02, 0x80}, 0x04}, - {PRO_DMOD, 0x011a, {0xcd, 0x62, 0xa4, 0x8c}, 0x04}, - {PRO_DMOD, 0x0122, {0x03, 0x18, 0x9e}, 0x03}, - {PRO_DMOD, 0x0127, {0x00, 0x07}, 0x02}, - {PRO_DMOD, 0x012a, {0x53, 0x51, 0x4e, 0x43}, 0x04}, - {PRO_DMOD, 0x0137, {0x00, 0x00, 0x07, 0x00, 0x06}, 0x05}, - {PRO_DMOD, 0x013d, {0x00, 0x01, 0x5b, 0xb6, 0x59}, 0x05}, - {PRO_DMOD, 0xf000, {0x0f}, 0x01}, - {PRO_DMOD, 0xf016, {0x10, 0x04, 0x05, 0x04, 0x05}, 0x05}, - {PRO_DMOD, 0xf01f, {0x8c, 0x00, 0x03, 0x0a, 0x0a}, 0x05}, - {PRO_DMOD, 0xf029, {0x8c, 0x00, 0x00, 0x01}, 0x04}, - {PRO_DMOD, 0xf064, {0x03, 0xf9, 0x03, 0x01}, 0x04}, - {PRO_DMOD, 0xf06f, {0xe0, 0x03}, 0x02}, - {PRO_DMOD, 0xf072, {0x0f, 0x03}, 0x02}, - {PRO_DMOD, 0xf077, {0x01, 0x00}, 0x02}, - {PRO_DMOD, 0xf085, {0xc0, 0x01, 0x00}, 0x03}, - {PRO_DMOD, 0xf09b, {0x3f, 0x00, 0x20, 0x00, 0x0c, 0x00}, 0x06}, - {PRO_DMOD, 0xf130, {0x04}, 0x01}, - {PRO_DMOD, 0xf132, {0x04}, 0x01}, - {PRO_DMOD, 0xf144, {0x1a}, 0x01}, - {PRO_DMOD, 0xf146, {0x00}, 0x01}, - {PRO_DMOD, 0xf14a, {0x01}, 0x01}, - {PRO_DMOD, 0xf14c, {0x00, 0x00}, 0x02}, - {PRO_DMOD, 0xf14f, {0x04}, 0x01}, - {PRO_DMOD, 0xf158, {0x7f}, 0x01}, - {PRO_DMOD, 0xf15a, {0x00, 0x08}, 0x02}, - {PRO_DMOD, 0xf15d, {0x03, 0x05}, 0x02}, - {PRO_DMOD, 0xf163, {0x05}, 0x01}, - {PRO_DMOD, 0xf166, {0x01, 0x40, 0x0f}, 0x03}, - {PRO_DMOD, 0xf17a, {0x00, 0x00}, 0x02}, - {PRO_DMOD, 0xf183, {0x01}, 0x01}, - {PRO_DMOD, 0xf19d, {0x40}, 0x01}, - {PRO_DMOD, 0xf1bc, {0x36, 0x00}, 0x02}, - {PRO_DMOD, 0xf1cb, {0xa0, 0x01}, 0x02}, - {PRO_DMOD, 0xf204, {0x10}, 0x01}, - {PRO_DMOD, 0xf214, {0x00}, 0x01}, - {PRO_DMOD, 0xf24c, {0x88, 0x95, 0x9a, 0x90}, 0x04}, - {PRO_DMOD, 0xf25a, {0x07, 0xe8, 0x03, 0xb0, 0x04}, 0x05}, - {PRO_DMOD, 0xf270, {0x01, 0x02, 0x01, 0x02}, 0x04}, - {PRO_DMOD, 0xf40e, {0x0a, 0x40, 0x08}, 0x03}, - {PRO_DMOD, 0xf55f, {0x0a}, 0x01}, - {PRO_DMOD, 0xf561, {0x15, 0x20}, 0x02}, - {PRO_DMOD, 0xf5df, {0xfb, 0x00}, 0x02}, - {PRO_DMOD, 0xf5e3, {0x09, 0x01, 0x01}, 0x03}, - {PRO_DMOD, 0xf5f8, {0x01}, 0x01}, - {PRO_DMOD, 0xf5fd, {0x01}, 0x01}, - {PRO_DMOD, 0xf600, {0x05, 0x08, 0x0b, 0x0e, 0x11, 0x14, 0x17, - 0x1f}, 0x08}, - {PRO_DMOD, 0xf60e, {0x00, 0x04, 0x32, 0x10}, 0x04}, - {PRO_DMOD, 0xf707, {0xfc, 0x00, 0x37, 0x00}, 0x04}, - {PRO_DMOD, 0xf78b, {0x01}, 0x01}, - {PRO_DMOD, 0xf80f, {0x40, 0x54, 0x5a}, 0x03}, - {PRO_DMOD, 0xf905, {0x01}, 0x01}, - {PRO_DMOD, 0xfb06, {0x03}, 0x01}, - {PRO_DMOD, 0xfd8b, {0x00}, 0x01}, - {0xff, 0x0000, {0x00}, 0x00} /* Terminating Entry */ -}; - -/* Version 2 types */ -static struct it913xset it9135_v2[] = { - {PRO_DMOD, 0x0051, {0x01}, 0x01}, - {PRO_DMOD, 0x0070, {0x0a}, 0x01}, - {PRO_DMOD, 0x007e, {0x04}, 0x01}, - {PRO_DMOD, 0x0081, {0x0a}, 0x01}, - {PRO_DMOD, 0x008a, {0x01}, 0x01}, - {PRO_DMOD, 0x008e, {0x01}, 0x01}, - {PRO_DMOD, 0x0092, {0x06}, 0x01}, - {PRO_DMOD, 0x0099, {0x01}, 0x01}, - {PRO_DMOD, 0x009f, {0xe1}, 0x01}, - {PRO_DMOD, 0x00a0, {0xcf}, 0x01}, - {PRO_DMOD, 0x00a3, {0x01}, 0x01}, - {PRO_DMOD, 0x00a5, {0x01}, 0x01}, - {PRO_DMOD, 0x00a6, {0x01}, 0x01}, - {PRO_DMOD, 0x00a9, {0x00}, 0x01}, - {PRO_DMOD, 0x00aa, {0x01}, 0x01}, - {PRO_DMOD, 0x00b0, {0x01}, 0x01}, - {PRO_DMOD, 0x00c2, {0x05}, 0x01}, - {PRO_DMOD, 0x00c6, {0x19}, 0x01}, - {PRO_DMOD, 0xf000, {0x0f}, 0x01}, - {PRO_DMOD, 0xf02b, {0x00}, 0x01}, - {PRO_DMOD, 0xf064, {0x03}, 0x01}, - {PRO_DMOD, 0xf065, {0xf9}, 0x01}, - {PRO_DMOD, 0xf066, {0x03}, 0x01}, - {PRO_DMOD, 0xf067, {0x01}, 0x01}, - {PRO_DMOD, 0xf06f, {0xe0}, 0x01}, - {PRO_DMOD, 0xf070, {0x03}, 0x01}, - {PRO_DMOD, 0xf072, {0x0f}, 0x01}, - {PRO_DMOD, 0xf073, {0x03}, 0x01}, - {PRO_DMOD, 0xf078, {0x00}, 0x01}, - {PRO_DMOD, 0xf087, {0x00}, 0x01}, - {PRO_DMOD, 0xf09b, {0x3f}, 0x01}, - {PRO_DMOD, 0xf09c, {0x00}, 0x01}, - {PRO_DMOD, 0xf09d, {0x20}, 0x01}, - {PRO_DMOD, 0xf09e, {0x00}, 0x01}, - {PRO_DMOD, 0xf09f, {0x0c}, 0x01}, - {PRO_DMOD, 0xf0a0, {0x00}, 0x01}, - {PRO_DMOD, 0xf130, {0x04}, 0x01}, - {PRO_DMOD, 0xf132, {0x04}, 0x01}, - {PRO_DMOD, 0xf144, {0x1a}, 0x01}, - {PRO_DMOD, 0xf146, {0x00}, 0x01}, - {PRO_DMOD, 0xf14a, {0x01}, 0x01}, - {PRO_DMOD, 0xf14c, {0x00}, 0x01}, - {PRO_DMOD, 0xf14d, {0x00}, 0x01}, - {PRO_DMOD, 0xf14f, {0x04}, 0x01}, - {PRO_DMOD, 0xf158, {0x7f}, 0x01}, - {PRO_DMOD, 0xf15a, {0x00}, 0x01}, - {PRO_DMOD, 0xf15b, {0x08}, 0x01}, - {PRO_DMOD, 0xf15d, {0x03}, 0x01}, - {PRO_DMOD, 0xf15e, {0x05}, 0x01}, - {PRO_DMOD, 0xf163, {0x05}, 0x01}, - {PRO_DMOD, 0xf166, {0x01}, 0x01}, - {PRO_DMOD, 0xf167, {0x40}, 0x01}, - {PRO_DMOD, 0xf168, {0x0f}, 0x01}, - {PRO_DMOD, 0xf17a, {0x00}, 0x01}, - {PRO_DMOD, 0xf17b, {0x00}, 0x01}, - {PRO_DMOD, 0xf183, {0x01}, 0x01}, - {PRO_DMOD, 0xf19d, {0x40}, 0x01}, - {PRO_DMOD, 0xf1bc, {0x36}, 0x01}, - {PRO_DMOD, 0xf1bd, {0x00}, 0x01}, - {PRO_DMOD, 0xf1cb, {0xa0}, 0x01}, - {PRO_DMOD, 0xf1cc, {0x01}, 0x01}, - {PRO_DMOD, 0xf204, {0x10}, 0x01}, - {PRO_DMOD, 0xf214, {0x00}, 0x01}, - {PRO_DMOD, 0xf40e, {0x0a}, 0x01}, - {PRO_DMOD, 0xf40f, {0x40}, 0x01}, - {PRO_DMOD, 0xf410, {0x08}, 0x01}, - {PRO_DMOD, 0xf55f, {0x0a}, 0x01}, - {PRO_DMOD, 0xf561, {0x15}, 0x01}, - {PRO_DMOD, 0xf562, {0x20}, 0x01}, - {PRO_DMOD, 0xf5e3, {0x09}, 0x01}, - {PRO_DMOD, 0xf5e4, {0x01}, 0x01}, - {PRO_DMOD, 0xf5e5, {0x01}, 0x01}, - {PRO_DMOD, 0xf600, {0x05}, 0x01}, - {PRO_DMOD, 0xf601, {0x08}, 0x01}, - {PRO_DMOD, 0xf602, {0x0b}, 0x01}, - {PRO_DMOD, 0xf603, {0x0e}, 0x01}, - {PRO_DMOD, 0xf604, {0x11}, 0x01}, - {PRO_DMOD, 0xf605, {0x14}, 0x01}, - {PRO_DMOD, 0xf606, {0x17}, 0x01}, - {PRO_DMOD, 0xf607, {0x1f}, 0x01}, - {PRO_DMOD, 0xf60e, {0x00}, 0x01}, - {PRO_DMOD, 0xf60f, {0x04}, 0x01}, - {PRO_DMOD, 0xf610, {0x32}, 0x01}, - {PRO_DMOD, 0xf611, {0x10}, 0x01}, - {PRO_DMOD, 0xf707, {0xfc}, 0x01}, - {PRO_DMOD, 0xf708, {0x00}, 0x01}, - {PRO_DMOD, 0xf709, {0x37}, 0x01}, - {PRO_DMOD, 0xf70a, {0x00}, 0x01}, - {PRO_DMOD, 0xf78b, {0x01}, 0x01}, - {PRO_DMOD, 0xf80f, {0x40}, 0x01}, - {PRO_DMOD, 0xf810, {0x54}, 0x01}, - {PRO_DMOD, 0xf811, {0x5a}, 0x01}, - {PRO_DMOD, 0xf905, {0x01}, 0x01}, - {PRO_DMOD, 0xfb06, {0x03}, 0x01}, - {PRO_DMOD, 0xfd8b, {0x00}, 0x01}, - {0xff, 0x0000, {0x00}, 0x00} /* Terminating Entry */ -}; - -static struct it913xset it9135_60[] = { - {PRO_DMOD, 0x0043, {0x00}, 0x01}, - {PRO_DMOD, 0x0046, {0x60}, 0x01}, - {PRO_DMOD, 0x0051, {0x01}, 0x01}, - {PRO_DMOD, 0x005f, {0x00, 0x00}, 0x02}, - {PRO_DMOD, 0x0068, {0x0a}, 0x01}, - {PRO_DMOD, 0x006a, {0x03}, 0x01}, - {PRO_DMOD, 0x0070, {0x0a, 0x05, 0x02}, 0x03}, - {PRO_DMOD, 0x0075, {0x8c, 0x8c, 0x8c, 0x8c, 0x01}, 0x05}, - {PRO_DMOD, 0x007e, {0x04}, 0x01}, - {PRO_DMOD, 0x0081, {0x0a, 0x12}, 0x02}, - {PRO_DMOD, 0x0084, {0x0a, 0x33, 0xbe, 0xa0, 0xc6, 0xb6, 0x01}, 0x07}, - {PRO_DMOD, 0x008e, {0x01}, 0x01}, - {PRO_DMOD, 0x0092, {0x06, 0x00, 0x00, 0x00, 0x00}, 0x05}, - {PRO_DMOD, 0x0099, {0x01}, 0x01}, - {PRO_DMOD, 0x009b, {0x3c, 0x28}, 0x02}, - {PRO_DMOD, 0x009f, {0xe1, 0xcf}, 0x02}, - {PRO_DMOD, 0x00a3, {0x01, 0x5a, 0x01, 0x01}, 0x04}, - {PRO_DMOD, 0x00a9, {0x00, 0x01}, 0x02}, - {PRO_DMOD, 0x00b0, {0x01}, 0x01}, - {PRO_DMOD, 0x00b3, {0x02, 0x3a}, 0x02}, - {PRO_DMOD, 0x00b6, {0x14}, 0x01}, - {PRO_DMOD, 0x00c0, {0x11, 0x00, 0x05, 0x01, 0x00}, 0x05}, - {PRO_DMOD, 0x00c6, {0x19, 0x00}, 0x02}, - {PRO_DMOD, 0x00cb, {0x32, 0x2c, 0x4f, 0x30}, 0x04}, - {PRO_DMOD, 0x00f3, {0x05, 0xa0, 0x8c}, 0x03}, - {PRO_DMOD, 0x00f8, {0x03, 0x06, 0x06}, 0x03}, - {PRO_DMOD, 0x00fc, { 0x03, 0x03, 0x02, 0x0a, 0x50, 0x7b, 0x8c, - 0x00, 0x02, 0xbe, 0x00}, 0x0b}, - {PRO_DMOD, 0x0109, {0x02}, 0x01}, - {PRO_DMOD, 0x0115, {0x0a, 0x03}, 0x02}, - {PRO_DMOD, 0x011a, {0xbe}, 0x01}, - {PRO_DMOD, 0x0124, {0xae}, 0x01}, - {PRO_DMOD, 0x0127, {0x00}, 0x01}, - {PRO_DMOD, 0x012a, {0x56, 0x50, 0x47, 0x42}, 0x04}, - {PRO_DMOD, 0x0137, {0x00}, 0x01}, - {PRO_DMOD, 0x013b, {0x08}, 0x01}, - {PRO_DMOD, 0x013f, {0x5b}, 0x01}, - {PRO_DMOD, 0x0141, { 0x59, 0xf9, 0x19, 0x19, 0x8c, 0x8c, 0x8c, - 0x6e, 0x8c, 0x50, 0x8c, 0x8c, 0xac, 0xc6, - 0x33}, 0x0f}, - {PRO_DMOD, 0x0151, {0x28}, 0x01}, - {PRO_DMOD, 0x0153, {0xbc}, 0x01}, - {PRO_DMOD, 0x0178, {0x09}, 0x01}, - {PRO_DMOD, 0x0181, {0x94, 0x6e}, 0x02}, - {PRO_DMOD, 0x0185, {0x24}, 0x01}, - {PRO_DMOD, 0x0187, {0x00, 0x00, 0xbe, 0x02, 0x80}, 0x05}, - {PRO_DMOD, 0xed02, {0xff}, 0x01}, - {PRO_DMOD, 0xee42, {0xff}, 0x01}, - {PRO_DMOD, 0xee82, {0xff}, 0x01}, - {PRO_DMOD, 0xf000, {0x0f}, 0x01}, - {PRO_DMOD, 0xf01f, {0x8c, 0x00}, 0x02}, - {PRO_DMOD, 0xf029, {0x8c, 0x00, 0x00}, 0x03}, - {PRO_DMOD, 0xf064, {0x03, 0xf9, 0x03, 0x01}, 0x04}, - {PRO_DMOD, 0xf06f, {0xe0, 0x03}, 0x02}, - {PRO_DMOD, 0xf072, {0x0f, 0x03}, 0x02}, - {PRO_DMOD, 0xf077, {0x01, 0x00}, 0x02}, - {PRO_DMOD, 0xf087, {0x00}, 0x01}, - {PRO_DMOD, 0xf09b, {0x3f, 0x00, 0x20, 0x00, 0x0c, 0x00}, 0x06}, - {PRO_DMOD, 0xf130, {0x04}, 0x01}, - {PRO_DMOD, 0xf132, {0x04}, 0x01}, - {PRO_DMOD, 0xf144, {0x1a}, 0x01}, - {PRO_DMOD, 0xf146, {0x00}, 0x01}, - {PRO_DMOD, 0xf14a, {0x01}, 0x01}, - {PRO_DMOD, 0xf14c, {0x00, 0x00}, 0x02}, - {PRO_DMOD, 0xf14f, {0x04}, 0x01}, - {PRO_DMOD, 0xf158, {0x7f}, 0x01}, - {PRO_DMOD, 0xf15a, {0x00, 0x08}, 0x02}, - {PRO_DMOD, 0xf15d, {0x03, 0x05}, 0x02}, - {PRO_DMOD, 0xf163, {0x05}, 0x01}, - {PRO_DMOD, 0xf166, {0x01, 0x40, 0x0f}, 0x03}, - {PRO_DMOD, 0xf17a, {0x00, 0x00}, 0x02}, - {PRO_DMOD, 0xf183, {0x01}, 0x01}, - {PRO_DMOD, 0xf19d, {0x40}, 0x01}, - {PRO_DMOD, 0xf1bc, {0x36, 0x00}, 0x02}, - {PRO_DMOD, 0xf1cb, {0xa0, 0x01}, 0x02}, - {PRO_DMOD, 0xf204, {0x10}, 0x01}, - {PRO_DMOD, 0xf214, {0x00}, 0x01}, - {PRO_DMOD, 0xf24c, {0x88, 0x95, 0x9a, 0x90}, 0x04}, - {PRO_DMOD, 0xf25a, {0x07, 0xe8, 0x03, 0xb0, 0x04}, 0x05}, - {PRO_DMOD, 0xf270, {0x01, 0x02, 0x01, 0x02}, 0x04}, - {PRO_DMOD, 0xf40e, {0x0a, 0x40, 0x08}, 0x03}, - {PRO_DMOD, 0xf55f, {0x0a}, 0x01}, - {PRO_DMOD, 0xf561, {0x15, 0x20}, 0x02}, - {PRO_DMOD, 0xf5e3, {0x09, 0x01, 0x01}, 0x03}, - {PRO_DMOD, 0xf600, {0x05, 0x08, 0x0b, 0x0e, 0x11, 0x14, 0x17 - , 0x1f}, 0x08}, - {PRO_DMOD, 0xf60e, {0x00, 0x04, 0x32, 0x10}, 0x04}, - {PRO_DMOD, 0xf707, {0xfc, 0x00, 0x37, 0x00}, 0x04}, - {PRO_DMOD, 0xf78b, {0x01}, 0x01}, - {PRO_DMOD, 0xf80f, {0x40, 0x54, 0x5a}, 0x03}, - {PRO_DMOD, 0xf905, {0x01}, 0x01}, - {PRO_DMOD, 0xfb06, {0x03}, 0x01}, - {PRO_DMOD, 0xfd8b, {0x00}, 0x01}, - {0xff, 0x0000, {0x00}, 0x00} /* Terminating Entry */ -}; - -static struct it913xset it9135_61[] = { - {PRO_DMOD, 0x0043, {0x00}, 0x01}, - {PRO_DMOD, 0x0046, {0x61}, 0x01}, - {PRO_DMOD, 0x0051, {0x01}, 0x01}, - {PRO_DMOD, 0x005f, {0x00, 0x00}, 0x02}, - {PRO_DMOD, 0x0068, {0x06}, 0x01}, - {PRO_DMOD, 0x006a, {0x03}, 0x01}, - {PRO_DMOD, 0x0070, {0x0a, 0x05, 0x02}, 0x03}, - {PRO_DMOD, 0x0075, {0x8c, 0x8c, 0x8c, 0x90, 0x01}, 0x05}, - {PRO_DMOD, 0x007e, {0x04}, 0x01}, - {PRO_DMOD, 0x0081, {0x0a, 0x12}, 0x02}, - {PRO_DMOD, 0x0084, {0x0a, 0x33, 0xbc, 0x9c, 0xcc, 0xa8, 0x01}, 0x07}, - {PRO_DMOD, 0x008e, {0x01}, 0x01}, - {PRO_DMOD, 0x0092, {0x06, 0x00, 0x00, 0x00, 0x00}, 0x05}, - {PRO_DMOD, 0x0099, {0x01}, 0x01}, - {PRO_DMOD, 0x009b, {0x3c, 0x28}, 0x02}, - {PRO_DMOD, 0x009f, {0xe1, 0xcf}, 0x02}, - {PRO_DMOD, 0x00a3, {0x01, 0x5c, 0x01, 0x01}, 0x04}, - {PRO_DMOD, 0x00a9, {0x00, 0x01}, 0x02}, - {PRO_DMOD, 0x00b0, {0x01}, 0x01}, - {PRO_DMOD, 0x00b3, {0x02, 0x3a}, 0x02}, - {PRO_DMOD, 0x00b6, {0x14}, 0x01}, - {PRO_DMOD, 0x00c0, {0x11, 0x00, 0x05, 0x01, 0x00}, 0x05}, - {PRO_DMOD, 0x00c6, {0x19, 0x00}, 0x02}, - {PRO_DMOD, 0x00cb, {0x32, 0x2c, 0x4f, 0x30}, 0x04}, - {PRO_DMOD, 0x00f3, {0x05, 0xa0, 0x8c}, 0x03}, - {PRO_DMOD, 0x00f8, {0x03, 0x06, 0x06}, 0x03}, - {PRO_DMOD, 0x00fc, { 0x03, 0x03, 0x02, 0x08, 0x50, 0x7b, 0x8c, - 0x01, 0x02, 0xc8, 0x00}, 0x0b}, - {PRO_DMOD, 0x0109, {0x02}, 0x01}, - {PRO_DMOD, 0x0115, {0x0a, 0x03}, 0x02}, - {PRO_DMOD, 0x011a, {0xc6}, 0x01}, - {PRO_DMOD, 0x0124, {0xa8}, 0x01}, - {PRO_DMOD, 0x0127, {0x00}, 0x01}, - {PRO_DMOD, 0x012a, {0x59, 0x50, 0x47, 0x42}, 0x04}, - {PRO_DMOD, 0x0137, {0x00}, 0x01}, - {PRO_DMOD, 0x013b, {0x05}, 0x01}, - {PRO_DMOD, 0x013f, {0x5b}, 0x01}, - {PRO_DMOD, 0x0141, { 0x59, 0xf9, 0x59, 0x59, 0x8c, 0x8c, 0x8c, - 0x7b, 0x8c, 0x50, 0x8c, 0x8c, 0xa8, 0xc6, - 0x33}, 0x0f}, - {PRO_DMOD, 0x0151, {0x28}, 0x01}, - {PRO_DMOD, 0x0153, {0xcc}, 0x01}, - {PRO_DMOD, 0x0178, {0x09}, 0x01}, - {PRO_DMOD, 0x0181, {0x9c, 0x76}, 0x02}, - {PRO_DMOD, 0x0185, {0x28}, 0x01}, - {PRO_DMOD, 0x0187, {0x01, 0x00, 0xaa, 0x02, 0x80}, 0x05}, - {PRO_DMOD, 0xed02, {0xff}, 0x01}, - {PRO_DMOD, 0xee42, {0xff}, 0x01}, - {PRO_DMOD, 0xee82, {0xff}, 0x01}, - {PRO_DMOD, 0xf000, {0x0f}, 0x01}, - {PRO_DMOD, 0xf01f, {0x8c, 0x00}, 0x02}, - {PRO_DMOD, 0xf029, {0x8c, 0x00, 0x00}, 0x03}, - {PRO_DMOD, 0xf064, {0x03, 0xf9, 0x03, 0x01}, 0x04}, - {PRO_DMOD, 0xf06f, {0xe0, 0x03}, 0x02}, - {PRO_DMOD, 0xf072, {0x0f, 0x03}, 0x02}, - {PRO_DMOD, 0xf077, {0x01, 0x00}, 0x02}, - {PRO_DMOD, 0xf087, {0x00}, 0x01}, - {PRO_DMOD, 0xf09b, {0x3f, 0x00, 0x20, 0x00, 0x0c, 0x00}, 0x06}, - {PRO_DMOD, 0xf130, {0x04}, 0x01}, - {PRO_DMOD, 0xf132, {0x04}, 0x01}, - {PRO_DMOD, 0xf144, {0x1a}, 0x01}, - {PRO_DMOD, 0xf146, {0x00}, 0x01}, - {PRO_DMOD, 0xf14a, {0x01}, 0x01}, - {PRO_DMOD, 0xf14c, {0x00, 0x00}, 0x02}, - {PRO_DMOD, 0xf14f, {0x04}, 0x01}, - {PRO_DMOD, 0xf158, {0x7f}, 0x01}, - {PRO_DMOD, 0xf15a, {0x00, 0x08}, 0x02}, - {PRO_DMOD, 0xf15d, {0x03, 0x05}, 0x02}, - {PRO_DMOD, 0xf163, {0x05}, 0x01}, - {PRO_DMOD, 0xf166, {0x01, 0x40, 0x0f}, 0x03}, - {PRO_DMOD, 0xf17a, {0x00, 0x00}, 0x02}, - {PRO_DMOD, 0xf183, {0x01}, 0x01}, - {PRO_DMOD, 0xf19d, {0x40}, 0x01}, - {PRO_DMOD, 0xf1bc, {0x36, 0x00}, 0x02}, - {PRO_DMOD, 0xf1cb, {0xa0, 0x01}, 0x02}, - {PRO_DMOD, 0xf204, {0x10}, 0x01}, - {PRO_DMOD, 0xf214, {0x00}, 0x01}, - {PRO_DMOD, 0xf24c, {0x88, 0x95, 0x9a, 0x90}, 0x04}, - {PRO_DMOD, 0xf25a, {0x07, 0xe8, 0x03, 0xb0, 0x04}, 0x05}, - {PRO_DMOD, 0xf270, {0x01, 0x02, 0x01, 0x02}, 0x04}, - {PRO_DMOD, 0xf40e, {0x0a, 0x40, 0x08}, 0x03}, - {PRO_DMOD, 0xf55f, {0x0a}, 0x01}, - {PRO_DMOD, 0xf561, {0x15, 0x20}, 0x02}, - {PRO_DMOD, 0xf5e3, {0x09, 0x01, 0x01}, 0x03}, - {PRO_DMOD, 0xf600, { 0x05, 0x08, 0x0b, 0x0e, 0x11, 0x14, 0x17, - 0x1f}, 0x08}, - {PRO_DMOD, 0xf60e, {0x00, 0x04, 0x32, 0x10}, 0x04}, - {PRO_DMOD, 0xf707, {0xfc, 0x00, 0x37, 0x00}, 0x04}, - {PRO_DMOD, 0xf78b, {0x01}, 0x01}, - {PRO_DMOD, 0xf80f, {0x40, 0x54, 0x5a}, 0x03}, - {PRO_DMOD, 0xf905, {0x01}, 0x01}, - {PRO_DMOD, 0xfb06, {0x03}, 0x01}, - {PRO_DMOD, 0xfd8b, {0x00}, 0x01}, - {0xff, 0x0000, {0x00}, 0x00} /* Terminating Entry */ -}; - -static struct it913xset it9135_62[] = { - {PRO_DMOD, 0x0043, {0x00}, 0x01}, - {PRO_DMOD, 0x0046, {0x62}, 0x01}, - {PRO_DMOD, 0x0051, {0x01}, 0x01}, - {PRO_DMOD, 0x005f, {0x00, 0x00}, 0x02}, - {PRO_DMOD, 0x0068, {0x0a}, 0x01}, - {PRO_DMOD, 0x006a, {0x03}, 0x01}, - {PRO_DMOD, 0x0070, {0x0a, 0x05, 0x02}, 0x03}, - {PRO_DMOD, 0x0075, {0x8c, 0x8c, 0x8c, 0x8c, 0x01}, 0x05}, - {PRO_DMOD, 0x007e, {0x04}, 0x01}, - {PRO_DMOD, 0x0081, {0x0a, 0x12}, 0x02}, - {PRO_DMOD, 0x0084, { 0x0a, 0x33, 0xb8, 0x9c, 0xb2, 0xa6, 0x01}, - 0x07}, - {PRO_DMOD, 0x008e, {0x01}, 0x01}, - {PRO_DMOD, 0x0092, {0x06, 0x00, 0x00, 0x00, 0x00}, 0x05}, - {PRO_DMOD, 0x0099, {0x01}, 0x01}, - {PRO_DMOD, 0x009b, {0x3c, 0x28}, 0x02}, - {PRO_DMOD, 0x009f, {0xe1, 0xcf}, 0x02}, - {PRO_DMOD, 0x00a3, {0x01, 0x5a, 0x01, 0x01}, 0x04}, - {PRO_DMOD, 0x00a9, {0x00, 0x01}, 0x02}, - {PRO_DMOD, 0x00b0, {0x01}, 0x01}, - {PRO_DMOD, 0x00b3, {0x02, 0x3a}, 0x02}, - {PRO_DMOD, 0x00b6, {0x14}, 0x01}, - {PRO_DMOD, 0x00c0, {0x11, 0x00, 0x05, 0x01, 0x00}, 0x05}, - {PRO_DMOD, 0x00c6, {0x19, 0x00}, 0x02}, - {PRO_DMOD, 0x00cb, {0x32, 0x2c, 0x4f, 0x30}, 0x04}, - {PRO_DMOD, 0x00f3, {0x05, 0x8c, 0x8c}, 0x03}, - {PRO_DMOD, 0x00f8, {0x03, 0x06, 0x06}, 0x03}, - {PRO_DMOD, 0x00fc, { 0x02, 0x03, 0x02, 0x09, 0x50, 0x6e, 0x8c, - 0x02, 0x02, 0xc2, 0x00}, 0x0b}, - {PRO_DMOD, 0x0109, {0x02}, 0x01}, - {PRO_DMOD, 0x0115, {0x0a, 0x03}, 0x02}, - {PRO_DMOD, 0x011a, {0xb8}, 0x01}, - {PRO_DMOD, 0x0124, {0xa8}, 0x01}, - {PRO_DMOD, 0x0127, {0x00}, 0x01}, - {PRO_DMOD, 0x012a, {0x53, 0x51, 0x4e, 0x43}, 0x04}, - {PRO_DMOD, 0x0137, {0x00}, 0x01}, - {PRO_DMOD, 0x013b, {0x05}, 0x01}, - {PRO_DMOD, 0x013f, {0x5b}, 0x01}, - {PRO_DMOD, 0x0141, { 0x59, 0xf9, 0x59, 0x19, 0x8c, 0x8c, 0x8c, - 0x7b, 0x8c, 0x50, 0x70, 0x8c, 0x96, 0xd0, - 0x33}, 0x0f}, - {PRO_DMOD, 0x0151, {0x28}, 0x01}, - {PRO_DMOD, 0x0153, {0xb2}, 0x01}, - {PRO_DMOD, 0x0178, {0x09}, 0x01}, - {PRO_DMOD, 0x0181, {0x9c, 0x6e}, 0x02}, - {PRO_DMOD, 0x0185, {0x24}, 0x01}, - {PRO_DMOD, 0x0187, {0x00, 0x00, 0xb8, 0x02, 0x80}, 0x05}, - {PRO_DMOD, 0xed02, {0xff}, 0x01}, - {PRO_DMOD, 0xee42, {0xff}, 0x01}, - {PRO_DMOD, 0xee82, {0xff}, 0x01}, - {PRO_DMOD, 0xf000, {0x0f}, 0x01}, - {PRO_DMOD, 0xf01f, {0x8c, 0x00}, 0x02}, - {PRO_DMOD, 0xf029, {0x8c, 0x00, 0x00}, 0x03}, - {PRO_DMOD, 0xf064, {0x03, 0xf9, 0x03, 0x01}, 0x04}, - {PRO_DMOD, 0xf06f, {0xe0, 0x03}, 0x02}, - {PRO_DMOD, 0xf072, {0x0f, 0x03}, 0x02}, - {PRO_DMOD, 0xf077, {0x01, 0x00}, 0x02}, - {PRO_DMOD, 0xf087, {0x00}, 0x01}, - {PRO_DMOD, 0xf09b, {0x3f, 0x00, 0x20, 0x00, 0x0c, 0x00}, 0x06}, - {PRO_DMOD, 0xf130, {0x04}, 0x01}, - {PRO_DMOD, 0xf132, {0x04}, 0x01}, - {PRO_DMOD, 0xf144, {0x1a}, 0x01}, - {PRO_DMOD, 0xf146, {0x00}, 0x01}, - {PRO_DMOD, 0xf14a, {0x01}, 0x01}, - {PRO_DMOD, 0xf14c, {0x00, 0x00}, 0x02}, - {PRO_DMOD, 0xf14f, {0x04}, 0x01}, - {PRO_DMOD, 0xf158, {0x7f}, 0x01}, - {PRO_DMOD, 0xf15a, {0x00, 0x08}, 0x02}, - {PRO_DMOD, 0xf15d, {0x03, 0x05}, 0x02}, - {PRO_DMOD, 0xf163, {0x05}, 0x01}, - {PRO_DMOD, 0xf166, {0x01, 0x40, 0x0f}, 0x03}, - {PRO_DMOD, 0xf17a, {0x00, 0x00}, 0x02}, - {PRO_DMOD, 0xf183, {0x01}, 0x01}, - {PRO_DMOD, 0xf19d, {0x40}, 0x01}, - {PRO_DMOD, 0xf1bc, {0x36, 0x00}, 0x02}, - {PRO_DMOD, 0xf1cb, {0xa0, 0x01}, 0x02}, - {PRO_DMOD, 0xf204, {0x10}, 0x01}, - {PRO_DMOD, 0xf214, {0x00}, 0x01}, - {PRO_DMOD, 0xf24c, {0x88, 0x95, 0x9a, 0x90}, 0x04}, - {PRO_DMOD, 0xf25a, {0x07, 0xe8, 0x03, 0xb0, 0x04}, 0x05}, - {PRO_DMOD, 0xf270, {0x01, 0x02, 0x01, 0x02}, 0x04}, - {PRO_DMOD, 0xf40e, {0x0a, 0x40, 0x08}, 0x03}, - {PRO_DMOD, 0xf55f, {0x0a}, 0x01}, - {PRO_DMOD, 0xf561, {0x15, 0x20}, 0x02}, - {PRO_DMOD, 0xf5e3, {0x09, 0x01, 0x01}, 0x03}, - {PRO_DMOD, 0xf600, { 0x05, 0x08, 0x0b, 0x0e, 0x11, 0x14, 0x17, - 0x1f}, 0x08}, - {PRO_DMOD, 0xf60e, {0x00, 0x04, 0x32, 0x10}, 0x04}, - {PRO_DMOD, 0xf707, {0xfc, 0x00, 0x37, 0x00}, 0x04}, - {PRO_DMOD, 0xf78b, {0x01}, 0x01}, - {PRO_DMOD, 0xf80f, {0x40, 0x54, 0x5a}, 0x03}, - {PRO_DMOD, 0xf905, {0x01}, 0x01}, - {PRO_DMOD, 0xfb06, {0x03}, 0x01}, - {PRO_DMOD, 0xfd8b, {0x00}, 0x01}, - {0xff, 0x0000, {0x00}, 0x00} /* Terminating Entry */ -}; - -/* Tuner setting scripts (still keeping it9137) */ -static struct it913xset it9137_tuner_off[] = { - {PRO_DMOD, 0xfba8, {0x01}, 0x01}, /* Tuner Clock Off */ - {PRO_DMOD, 0xec40, {0x00}, 0x01}, /* Power Down Tuner */ - {PRO_DMOD, 0xec02, {0x3f, 0x1f, 0x3f, 0x3f}, 0x04}, - {PRO_DMOD, 0xec06, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00}, 0x0c}, - {PRO_DMOD, 0xec12, {0x00, 0x00, 0x00, 0x00}, 0x04}, - {PRO_DMOD, 0xec17, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00}, 0x09}, - {PRO_DMOD, 0xec22, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00}, 0x0a}, - {PRO_DMOD, 0xec20, {0x00}, 0x01}, - {PRO_DMOD, 0xec3f, {0x01}, 0x01}, - {0xff, 0x0000, {0x00}, 0x00}, /* Terminating Entry */ -}; - -static struct it913xset set_it9135_template[] = { - {PRO_DMOD, 0xee06, {0x00}, 0x01}, - {PRO_DMOD, 0xec56, {0x00}, 0x01}, - {PRO_DMOD, 0xec4c, {0x00}, 0x01}, - {PRO_DMOD, 0xec4d, {0x00}, 0x01}, - {PRO_DMOD, 0xec4e, {0x00}, 0x01}, - {PRO_DMOD, 0x011e, {0x00}, 0x01}, /* Older Devices */ - {PRO_DMOD, 0x011f, {0x00}, 0x01}, - {0xff, 0x0000, {0x00}, 0x00}, /* Terminating Entry */ -}; - -static struct it913xset set_it9137_template[] = { - {PRO_DMOD, 0xee06, {0x00}, 0x01}, - {PRO_DMOD, 0xec56, {0x00}, 0x01}, - {PRO_DMOD, 0xec4c, {0x00}, 0x01}, - {PRO_DMOD, 0xec4d, {0x00}, 0x01}, - {PRO_DMOD, 0xec4e, {0x00}, 0x01}, - {PRO_DMOD, 0xec4f, {0x00}, 0x01}, - {PRO_DMOD, 0xec50, {0x00}, 0x01}, - {0xff, 0x0000, {0x00}, 0x00}, /* Terminating Entry */ -}; diff --git a/drivers/media/dvb-frontends/it913x-fe.c b/drivers/media/dvb-frontends/it913x-fe.c deleted file mode 100644 index 6e1c6eb..0000000 --- a/drivers/media/dvb-frontends/it913x-fe.c +++ /dev/null @@ -1,1045 +0,0 @@ -/* - * Driver for it913x-fe Frontend - * - * with support for on chip it9137 integral tuner - * - * Copyright (C) 2011 Malcolm Priestley (tvboxspy@gmail.com) - * IT9137 Copyright (C) ITE Tech Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.= - */ - -#include -#include -#include -#include - -#include "dvb_frontend.h" -#include "it913x-fe.h" -#include "it913x-fe-priv.h" - -static int it913x_debug; - -module_param_named(debug, it913x_debug, int, 0644); -MODULE_PARM_DESC(debug, "set debugging level (1=info (or-able))."); - -#define dprintk(level, args...) do { \ - if (level & it913x_debug) \ - printk(KERN_DEBUG "it913x-fe: " args); \ -} while (0) - -#define deb_info(args...) dprintk(0x01, args) -#define debug_data_snipet(level, name, p) \ - dprintk(level, name" (%02x%02x%02x%02x%02x%02x%02x%02x)", \ - *p, *(p+1), *(p+2), *(p+3), *(p+4), \ - *(p+5), *(p+6), *(p+7)); -#define info(format, arg...) \ - printk(KERN_INFO "it913x-fe: " format "\n" , ## arg) - -struct it913x_fe_state { - struct dvb_frontend frontend; - struct i2c_adapter *i2c_adap; - struct ite_config *config; - u8 i2c_addr; - u32 frequency; - fe_modulation_t constellation; - fe_transmit_mode_t transmission_mode; - u8 priority; - u32 crystalFrequency; - u32 adcFrequency; - u8 tuner_type; - struct adctable *table; - fe_status_t it913x_status; - u16 tun_xtal; - u8 tun_fdiv; - u8 tun_clk_mode; - u32 tun_fn_min; - u32 ucblocks; -}; - -static int it913x_read_reg(struct it913x_fe_state *state, - u32 reg, u8 *data, u8 count) -{ - int ret; - u8 pro = PRO_DMOD; /* All reads from demodulator */ - u8 b[4]; - struct i2c_msg msg[2] = { - { .addr = state->i2c_addr + (pro << 1), .flags = 0, - .buf = b, .len = sizeof(b) }, - { .addr = state->i2c_addr + (pro << 1), .flags = I2C_M_RD, - .buf = data, .len = count } - }; - b[0] = (u8) reg >> 24; - b[1] = (u8)(reg >> 16) & 0xff; - b[2] = (u8)(reg >> 8) & 0xff; - b[3] = (u8) reg & 0xff; - - ret = i2c_transfer(state->i2c_adap, msg, 2); - - return ret; -} - -static int it913x_read_reg_u8(struct it913x_fe_state *state, u32 reg) -{ - int ret; - u8 b[1]; - ret = it913x_read_reg(state, reg, &b[0], sizeof(b)); - return (ret < 0) ? -ENODEV : b[0]; -} - -static int it913x_write(struct it913x_fe_state *state, - u8 pro, u32 reg, u8 buf[], u8 count) -{ - u8 b[256]; - struct i2c_msg msg[1] = { - { .addr = state->i2c_addr + (pro << 1), .flags = 0, - .buf = b, .len = count + 4 } - }; - int ret; - - b[0] = (u8) reg >> 24; - b[1] = (u8)(reg >> 16) & 0xff; - b[2] = (u8)(reg >> 8) & 0xff; - b[3] = (u8) reg & 0xff; - memcpy(&b[4], buf, count); - - ret = i2c_transfer(state->i2c_adap, msg, 1); - - if (ret < 0) - return -EIO; - - return 0; -} - -static int it913x_write_reg(struct it913x_fe_state *state, - u8 pro, u32 reg, u32 data) -{ - int ret; - u8 b[4]; - u8 s; - - b[0] = data >> 24; - b[1] = (data >> 16) & 0xff; - b[2] = (data >> 8) & 0xff; - b[3] = data & 0xff; - /* expand write as needed */ - if (data < 0x100) - s = 3; - else if (data < 0x1000) - s = 2; - else if (data < 0x100000) - s = 1; - else - s = 0; - - ret = it913x_write(state, pro, reg, &b[s], sizeof(b) - s); - - return ret; -} - -static int it913x_fe_script_loader(struct it913x_fe_state *state, - struct it913xset *loadscript) -{ - int ret, i; - if (loadscript == NULL) - return -EINVAL; - - for (i = 0; i < 1000; ++i) { - if (loadscript[i].pro == 0xff) - break; - ret = it913x_write(state, loadscript[i].pro, - loadscript[i].address, - loadscript[i].reg, loadscript[i].count); - if (ret < 0) - return -ENODEV; - } - return 0; -} - -static int it913x_init_tuner(struct it913x_fe_state *state) -{ - int ret, i, reg; - u8 val, nv_val; - u8 nv[] = {48, 32, 24, 16, 12, 8, 6, 4, 2}; - u8 b[2]; - - reg = it913x_read_reg_u8(state, 0xec86); - switch (reg) { - case 0: - state->tun_clk_mode = reg; - state->tun_xtal = 2000; - state->tun_fdiv = 3; - val = 16; - break; - case -ENODEV: - return -ENODEV; - case 1: - default: - state->tun_clk_mode = reg; - state->tun_xtal = 640; - state->tun_fdiv = 1; - val = 6; - break; - } - - reg = it913x_read_reg_u8(state, 0xed03); - - if (reg < 0) - return -ENODEV; - else if (reg < ARRAY_SIZE(nv)) - nv_val = nv[reg]; - else - nv_val = 2; - - for (i = 0; i < 50; i++) { - ret = it913x_read_reg(state, 0xed23, &b[0], sizeof(b)); - reg = (b[1] << 8) + b[0]; - if (reg > 0) - break; - if (ret < 0) - return -ENODEV; - udelay(2000); - } - state->tun_fn_min = state->tun_xtal * reg; - state->tun_fn_min /= (state->tun_fdiv * nv_val); - deb_info("Tuner fn_min %d", state->tun_fn_min); - - if (state->config->chip_ver > 1) - msleep(50); - else { - for (i = 0; i < 50; i++) { - reg = it913x_read_reg_u8(state, 0xec82); - if (reg > 0) - break; - if (reg < 0) - return -ENODEV; - udelay(2000); - } - } - - return it913x_write_reg(state, PRO_DMOD, 0xed81, val); -} - -static int it9137_set_tuner(struct it913x_fe_state *state, - u32 bandwidth, u32 frequency_m) -{ - struct it913xset *set_tuner = set_it9137_template; - int ret, reg; - u32 frequency = frequency_m / 1000; - u32 freq, temp_f, tmp; - u16 iqik_m_cal; - u16 n_div; - u8 n; - u8 l_band; - u8 lna_band; - u8 bw; - - if (state->config->firmware_ver == 1) - set_tuner = set_it9135_template; - else - set_tuner = set_it9137_template; - - deb_info("Tuner Frequency %d Bandwidth %d", frequency, bandwidth); - - if (frequency >= 51000 && frequency <= 440000) { - l_band = 0; - lna_band = 0; - } else if (frequency > 440000 && frequency <= 484000) { - l_band = 1; - lna_band = 1; - } else if (frequency > 484000 && frequency <= 533000) { - l_band = 1; - lna_band = 2; - } else if (frequency > 533000 && frequency <= 587000) { - l_band = 1; - lna_band = 3; - } else if (frequency > 587000 && frequency <= 645000) { - l_band = 1; - lna_band = 4; - } else if (frequency > 645000 && frequency <= 710000) { - l_band = 1; - lna_band = 5; - } else if (frequency > 710000 && frequency <= 782000) { - l_band = 1; - lna_band = 6; - } else if (frequency > 782000 && frequency <= 860000) { - l_band = 1; - lna_band = 7; - } else if (frequency > 1450000 && frequency <= 1492000) { - l_band = 1; - lna_band = 0; - } else if (frequency > 1660000 && frequency <= 1685000) { - l_band = 1; - lna_band = 1; - } else - return -EINVAL; - set_tuner[0].reg[0] = lna_band; - - switch (bandwidth) { - case 5000000: - bw = 0; - break; - case 6000000: - bw = 2; - break; - case 7000000: - bw = 4; - break; - default: - case 8000000: - bw = 6; - break; - } - - set_tuner[1].reg[0] = bw; - set_tuner[2].reg[0] = 0xa0 | (l_band << 3); - - if (frequency > 53000 && frequency <= 74000) { - n_div = 48; - n = 0; - } else if (frequency > 74000 && frequency <= 111000) { - n_div = 32; - n = 1; - } else if (frequency > 111000 && frequency <= 148000) { - n_div = 24; - n = 2; - } else if (frequency > 148000 && frequency <= 222000) { - n_div = 16; - n = 3; - } else if (frequency > 222000 && frequency <= 296000) { - n_div = 12; - n = 4; - } else if (frequency > 296000 && frequency <= 445000) { - n_div = 8; - n = 5; - } else if (frequency > 445000 && frequency <= state->tun_fn_min) { - n_div = 6; - n = 6; - } else if (frequency > state->tun_fn_min && frequency <= 950000) { - n_div = 4; - n = 7; - } else if (frequency > 1450000 && frequency <= 1680000) { - n_div = 2; - n = 0; - } else - return -EINVAL; - - reg = it913x_read_reg_u8(state, 0xed81); - iqik_m_cal = (u16)reg * n_div; - - if (reg < 0x20) { - if (state->tun_clk_mode == 0) - iqik_m_cal = (iqik_m_cal * 9) >> 5; - else - iqik_m_cal >>= 1; - } else { - iqik_m_cal = 0x40 - iqik_m_cal; - if (state->tun_clk_mode == 0) - iqik_m_cal = ~((iqik_m_cal * 9) >> 5); - else - iqik_m_cal = ~(iqik_m_cal >> 1); - } - - temp_f = frequency * (u32)n_div * (u32)state->tun_fdiv; - freq = temp_f / state->tun_xtal; - tmp = freq * state->tun_xtal; - - if ((temp_f - tmp) >= (state->tun_xtal >> 1)) - freq++; - - freq += (u32) n << 13; - /* Frequency OMEGA_IQIK_M_CAL_MID*/ - temp_f = freq + (u32)iqik_m_cal; - - set_tuner[3].reg[0] = temp_f & 0xff; - set_tuner[4].reg[0] = (temp_f >> 8) & 0xff; - - deb_info("High Frequency = %04x", temp_f); - - /* Lower frequency */ - set_tuner[5].reg[0] = freq & 0xff; - set_tuner[6].reg[0] = (freq >> 8) & 0xff; - - deb_info("low Frequency = %04x", freq); - - ret = it913x_fe_script_loader(state, set_tuner); - - return (ret < 0) ? -ENODEV : 0; -} - -static int it913x_fe_select_bw(struct it913x_fe_state *state, - u32 bandwidth, u32 adcFrequency) -{ - int ret, i; - u8 buffer[256]; - u32 coeff[8]; - u16 bfsfcw_fftinx_ratio; - u16 fftinx_bfsfcw_ratio; - u8 count; - u8 bw; - u8 adcmultiplier; - - deb_info("Bandwidth %d Adc %d", bandwidth, adcFrequency); - - switch (bandwidth) { - case 5000000: - bw = 3; - break; - case 6000000: - bw = 0; - break; - case 7000000: - bw = 1; - break; - default: - case 8000000: - bw = 2; - break; - } - ret = it913x_write_reg(state, PRO_DMOD, REG_BW, bw); - - if (state->table == NULL) - return -EINVAL; - - /* In write order */ - coeff[0] = state->table[bw].coeff_1_2048; - coeff[1] = state->table[bw].coeff_2_2k; - coeff[2] = state->table[bw].coeff_1_8191; - coeff[3] = state->table[bw].coeff_1_8192; - coeff[4] = state->table[bw].coeff_1_8193; - coeff[5] = state->table[bw].coeff_2_8k; - coeff[6] = state->table[bw].coeff_1_4096; - coeff[7] = state->table[bw].coeff_2_4k; - bfsfcw_fftinx_ratio = state->table[bw].bfsfcw_fftinx_ratio; - fftinx_bfsfcw_ratio = state->table[bw].fftinx_bfsfcw_ratio; - - /* ADC multiplier */ - ret = it913x_read_reg_u8(state, ADC_X_2); - if (ret < 0) - return -EINVAL; - - adcmultiplier = ret; - - count = 0; - - /* Build Buffer for COEFF Registers */ - for (i = 0; i < 8; i++) { - if (adcmultiplier == 1) - coeff[i] /= 2; - buffer[count++] = (coeff[i] >> 24) & 0x3; - buffer[count++] = (coeff[i] >> 16) & 0xff; - buffer[count++] = (coeff[i] >> 8) & 0xff; - buffer[count++] = coeff[i] & 0xff; - } - - /* bfsfcw_fftinx_ratio register 0x21-0x22 */ - buffer[count++] = bfsfcw_fftinx_ratio & 0xff; - buffer[count++] = (bfsfcw_fftinx_ratio >> 8) & 0xff; - /* fftinx_bfsfcw_ratio register 0x23-0x24 */ - buffer[count++] = fftinx_bfsfcw_ratio & 0xff; - buffer[count++] = (fftinx_bfsfcw_ratio >> 8) & 0xff; - /* start at COEFF_1_2048 and write through to fftinx_bfsfcw_ratio*/ - ret = it913x_write(state, PRO_DMOD, COEFF_1_2048, buffer, count); - - for (i = 0; i < 42; i += 8) - debug_data_snipet(0x1, "Buffer", &buffer[i]); - - return ret; -} - - - -static int it913x_fe_read_status(struct dvb_frontend *fe, fe_status_t *status) -{ - struct it913x_fe_state *state = fe->demodulator_priv; - int ret, i; - fe_status_t old_status = state->it913x_status; - *status = 0; - - if (state->it913x_status == 0) { - ret = it913x_read_reg_u8(state, EMPTY_CHANNEL_STATUS); - if (ret == 0x1) { - *status |= FE_HAS_SIGNAL; - for (i = 0; i < 40; i++) { - ret = it913x_read_reg_u8(state, MP2IF_SYNC_LK); - if (ret == 0x1) - break; - msleep(25); - } - if (ret == 0x1) - *status |= FE_HAS_CARRIER - | FE_HAS_VITERBI - | FE_HAS_SYNC; - state->it913x_status = *status; - } - } - - if (state->it913x_status & FE_HAS_SYNC) { - ret = it913x_read_reg_u8(state, TPSD_LOCK); - if (ret == 0x1) - *status |= FE_HAS_LOCK - | state->it913x_status; - else - state->it913x_status = 0; - if (old_status != state->it913x_status) - ret = it913x_write_reg(state, PRO_LINK, GPIOH3_O, ret); - } - - return 0; -} - -/* FEC values based on fe_code_rate_t non supported values 0*/ -int it913x_qpsk_pval[] = {0, -93, -91, -90, 0, -89, -88}; -int it913x_16qam_pval[] = {0, -87, -85, -84, 0, -83, -82}; -int it913x_64qam_pval[] = {0, -82, -80, -78, 0, -77, -76}; - -static int it913x_get_signal_strength(struct dvb_frontend *fe) -{ - struct dtv_frontend_properties *p = &fe->dtv_property_cache; - struct it913x_fe_state *state = fe->demodulator_priv; - u8 code_rate; - int ret, temp; - u8 lna_gain_os; - - ret = it913x_read_reg_u8(state, VAR_P_INBAND); - if (ret < 0) - return ret; - - /* VHF/UHF gain offset */ - if (state->frequency < 300000000) - lna_gain_os = 7; - else - lna_gain_os = 14; - - temp = (ret - 100) - lna_gain_os; - - if (state->priority == PRIORITY_HIGH) - code_rate = p->code_rate_HP; - else - code_rate = p->code_rate_LP; - - if (code_rate >= ARRAY_SIZE(it913x_qpsk_pval)) - return -EINVAL; - - deb_info("Reg VAR_P_INBAND:%d Calc Offset Value:%d", ret, temp); - - /* Apply FEC offset values*/ - switch (p->modulation) { - case QPSK: - temp -= it913x_qpsk_pval[code_rate]; - break; - case QAM_16: - temp -= it913x_16qam_pval[code_rate]; - break; - case QAM_64: - temp -= it913x_64qam_pval[code_rate]; - break; - default: - return -EINVAL; - } - - if (temp < -15) - ret = 0; - else if ((-15 <= temp) && (temp < 0)) - ret = (2 * (temp + 15)) / 3; - else if ((0 <= temp) && (temp < 20)) - ret = 4 * temp + 10; - else if ((20 <= temp) && (temp < 35)) - ret = (2 * (temp - 20)) / 3 + 90; - else if (temp >= 35) - ret = 100; - - deb_info("Signal Strength :%d", ret); - - return ret; -} - -static int it913x_fe_read_signal_strength(struct dvb_frontend *fe, - u16 *strength) -{ - struct it913x_fe_state *state = fe->demodulator_priv; - int ret = 0; - if (state->config->read_slevel) { - if (state->it913x_status & FE_HAS_SIGNAL) - ret = it913x_read_reg_u8(state, SIGNAL_LEVEL); - } else - ret = it913x_get_signal_strength(fe); - - if (ret >= 0) - *strength = (u16)((u32)ret * 0xffff / 0x64); - - return (ret < 0) ? -ENODEV : 0; -} - -static int it913x_fe_read_snr(struct dvb_frontend *fe, u16 *snr) -{ - struct it913x_fe_state *state = fe->demodulator_priv; - int ret; - u8 reg[3]; - u32 snr_val, snr_min, snr_max; - u32 temp; - - ret = it913x_read_reg(state, 0x2c, reg, sizeof(reg)); - - snr_val = (u32)(reg[2] << 16) | (reg[1] << 8) | reg[0]; - - ret |= it913x_read_reg(state, 0xf78b, reg, 1); - if (reg[0]) - snr_val /= reg[0]; - - if (state->transmission_mode == TRANSMISSION_MODE_2K) - snr_val *= 4; - else if (state->transmission_mode == TRANSMISSION_MODE_4K) - snr_val *= 2; - - if (state->constellation == QPSK) { - snr_min = 0xb4711; - snr_max = 0x191451; - } else if (state->constellation == QAM_16) { - snr_min = 0x4f0d5; - snr_max = 0xc7925; - } else if (state->constellation == QAM_64) { - snr_min = 0x256d0; - snr_max = 0x626be; - } else - return -EINVAL; - - if (snr_val < snr_min) - *snr = 0; - else if (snr_val < snr_max) { - temp = (snr_val - snr_min) >> 5; - temp *= 0xffff; - temp /= (snr_max - snr_min) >> 5; - *snr = (u16)temp; - } else - *snr = 0xffff; - - return (ret < 0) ? -ENODEV : 0; -} - -static int it913x_fe_read_ber(struct dvb_frontend *fe, u32 *ber) -{ - struct it913x_fe_state *state = fe->demodulator_priv; - u8 reg[5]; - /* Read Aborted Packets and Pre-Viterbi error rate 5 bytes */ - it913x_read_reg(state, RSD_ABORT_PKT_LSB, reg, sizeof(reg)); - state->ucblocks += (u32)(reg[1] << 8) | reg[0]; - *ber = (u32)(reg[4] << 16) | (reg[3] << 8) | reg[2]; - return 0; -} - -static int it913x_fe_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) -{ - struct it913x_fe_state *state = fe->demodulator_priv; - int ret; - u8 reg[2]; - /* Aborted Packets */ - ret = it913x_read_reg(state, RSD_ABORT_PKT_LSB, reg, sizeof(reg)); - state->ucblocks += (u32)(reg[1] << 8) | reg[0]; - *ucblocks = state->ucblocks; - return ret; -} - -static int it913x_fe_get_frontend(struct dvb_frontend *fe) -{ - struct dtv_frontend_properties *p = &fe->dtv_property_cache; - struct it913x_fe_state *state = fe->demodulator_priv; - u8 reg[8]; - - it913x_read_reg(state, REG_TPSD_TX_MODE, reg, sizeof(reg)); - - if (reg[3] < 3) - p->modulation = fe_con[reg[3]]; - - if (reg[0] < 3) - p->transmission_mode = fe_mode[reg[0]]; - - if (reg[1] < 4) - p->guard_interval = fe_gi[reg[1]]; - - if (reg[2] < 4) - p->hierarchy = fe_hi[reg[2]]; - - state->priority = reg[5]; - - p->code_rate_HP = (reg[6] < 6) ? fe_code[reg[6]] : FEC_NONE; - p->code_rate_LP = (reg[7] < 6) ? fe_code[reg[7]] : FEC_NONE; - - /* Update internal state to reflect the autodetected props */ - state->constellation = p->modulation; - state->transmission_mode = p->transmission_mode; - - return 0; -} - -static int it913x_fe_set_frontend(struct dvb_frontend *fe) -{ - struct dtv_frontend_properties *p = &fe->dtv_property_cache; - struct it913x_fe_state *state = fe->demodulator_priv; - int i; - u8 empty_ch, last_ch; - - state->it913x_status = 0; - - /* Set bw*/ - it913x_fe_select_bw(state, p->bandwidth_hz, - state->adcFrequency); - - /* Training Mode Off */ - it913x_write_reg(state, PRO_LINK, TRAINING_MODE, 0x0); - - /* Clear Empty Channel */ - it913x_write_reg(state, PRO_DMOD, EMPTY_CHANNEL_STATUS, 0x0); - - /* Clear bits */ - it913x_write_reg(state, PRO_DMOD, MP2IF_SYNC_LK, 0x0); - /* LED on */ - it913x_write_reg(state, PRO_LINK, GPIOH3_O, 0x1); - /* Select Band*/ - if ((p->frequency >= 51000000) && (p->frequency <= 230000000)) - i = 0; - else if ((p->frequency >= 350000000) && (p->frequency <= 900000000)) - i = 1; - else if ((p->frequency >= 1450000000) && (p->frequency <= 1680000000)) - i = 2; - else - return -EOPNOTSUPP; - - it913x_write_reg(state, PRO_DMOD, FREE_BAND, i); - - deb_info("Frontend Set Tuner Type %02x", state->tuner_type); - switch (state->tuner_type) { - case IT9135_38: - case IT9135_51: - case IT9135_52: - case IT9135_60: - case IT9135_61: - case IT9135_62: - it9137_set_tuner(state, - p->bandwidth_hz, p->frequency); - break; - default: - if (fe->ops.tuner_ops.set_params) { - fe->ops.tuner_ops.set_params(fe); - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 0); - } - break; - } - /* LED off */ - it913x_write_reg(state, PRO_LINK, GPIOH3_O, 0x0); - /* Trigger ofsm */ - it913x_write_reg(state, PRO_DMOD, TRIGGER_OFSM, 0x0); - last_ch = 2; - for (i = 0; i < 40; ++i) { - empty_ch = it913x_read_reg_u8(state, EMPTY_CHANNEL_STATUS); - if (last_ch == 1 && empty_ch == 1) - break; - if (last_ch == 2 && empty_ch == 2) - return 0; - last_ch = empty_ch; - msleep(25); - } - for (i = 0; i < 40; ++i) { - if (it913x_read_reg_u8(state, D_TPSD_LOCK) == 1) - break; - msleep(25); - } - - state->frequency = p->frequency; - return 0; -} - -static int it913x_fe_suspend(struct it913x_fe_state *state) -{ - int ret, i; - u8 b; - - ret = it913x_write_reg(state, PRO_DMOD, SUSPEND_FLAG, 0x1); - - ret |= it913x_write_reg(state, PRO_DMOD, TRIGGER_OFSM, 0x0); - - for (i = 0; i < 128; i++) { - ret = it913x_read_reg(state, SUSPEND_FLAG, &b, 1); - if (ret < 0) - return -ENODEV; - if (b == 0) - break; - - } - - ret |= it913x_write_reg(state, PRO_DMOD, AFE_MEM0, 0x8); - /* Turn LED off */ - ret |= it913x_write_reg(state, PRO_LINK, GPIOH3_O, 0x0); - - ret |= it913x_fe_script_loader(state, it9137_tuner_off); - - return (ret < 0) ? -ENODEV : 0; -} - -/* Power sequence */ -/* Power Up Tuner on -> Frontend suspend off -> Tuner clk on */ -/* Power Down Frontend suspend on -> Tuner clk off -> Tuner off */ - -static int it913x_fe_sleep(struct dvb_frontend *fe) -{ - struct it913x_fe_state *state = fe->demodulator_priv; - return it913x_fe_suspend(state); -} - -static u32 compute_div(u32 a, u32 b, u32 x) -{ - u32 res = 0; - u32 c = 0; - u32 i = 0; - - if (a > b) { - c = a / b; - a = a - c * b; - } - - for (i = 0; i < x; i++) { - if (a >= b) { - res += 1; - a -= b; - } - a <<= 1; - res <<= 1; - } - - res = (c << x) + res; - - return res; -} - -static int it913x_fe_start(struct it913x_fe_state *state) -{ - struct it913xset *set_lna; - struct it913xset *set_mode; - int ret; - u8 adf = (state->config->adf & 0xf); - u32 adc, xtal; - u8 b[4]; - - if (state->config->chip_ver == 1) - ret = it913x_init_tuner(state); - - info("ADF table value :%02x", adf); - - if (adf < 10) { - state->crystalFrequency = fe_clockTable[adf].xtal ; - state->table = fe_clockTable[adf].table; - state->adcFrequency = state->table->adcFrequency; - - adc = compute_div(state->adcFrequency, 1000000ul, 19ul); - xtal = compute_div(state->crystalFrequency, 1000000ul, 19ul); - - } else - return -EINVAL; - - /* Set LED indicator on GPIOH3 */ - ret = it913x_write_reg(state, PRO_LINK, GPIOH3_EN, 0x1); - ret |= it913x_write_reg(state, PRO_LINK, GPIOH3_ON, 0x1); - ret |= it913x_write_reg(state, PRO_LINK, GPIOH3_O, 0x1); - - ret |= it913x_write_reg(state, PRO_LINK, 0xf641, state->tuner_type); - ret |= it913x_write_reg(state, PRO_DMOD, 0xf5ca, 0x01); - ret |= it913x_write_reg(state, PRO_DMOD, 0xf715, 0x01); - - b[0] = xtal & 0xff; - b[1] = (xtal >> 8) & 0xff; - b[2] = (xtal >> 16) & 0xff; - b[3] = (xtal >> 24); - ret |= it913x_write(state, PRO_DMOD, XTAL_CLK, b , 4); - - b[0] = adc & 0xff; - b[1] = (adc >> 8) & 0xff; - b[2] = (adc >> 16) & 0xff; - ret |= it913x_write(state, PRO_DMOD, ADC_FREQ, b, 3); - - if (state->config->adc_x2) - ret |= it913x_write_reg(state, PRO_DMOD, ADC_X_2, 0x01); - b[0] = 0; - b[1] = 0; - b[2] = 0; - ret |= it913x_write(state, PRO_DMOD, 0x0029, b, 3); - - info("Crystal Frequency :%d Adc Frequency :%d ADC X2: %02x", - state->crystalFrequency, state->adcFrequency, - state->config->adc_x2); - deb_info("Xtal value :%04x Adc value :%04x", xtal, adc); - - if (ret < 0) - return -ENODEV; - - /* v1 or v2 tuner script */ - if (state->config->chip_ver > 1) - ret = it913x_fe_script_loader(state, it9135_v2); - else - ret = it913x_fe_script_loader(state, it9135_v1); - if (ret < 0) - return ret; - - /* LNA Scripts */ - switch (state->tuner_type) { - case IT9135_51: - set_lna = it9135_51; - break; - case IT9135_52: - set_lna = it9135_52; - break; - case IT9135_60: - set_lna = it9135_60; - break; - case IT9135_61: - set_lna = it9135_61; - break; - case IT9135_62: - set_lna = it9135_62; - break; - case IT9135_38: - default: - set_lna = it9135_38; - } - info("Tuner LNA type :%02x", state->tuner_type); - - ret = it913x_fe_script_loader(state, set_lna); - if (ret < 0) - return ret; - - if (state->config->chip_ver == 2) { - ret = it913x_write_reg(state, PRO_DMOD, TRIGGER_OFSM, 0x1); - ret |= it913x_write_reg(state, PRO_LINK, PADODPU, 0x0); - ret |= it913x_write_reg(state, PRO_LINK, AGC_O_D, 0x0); - ret |= it913x_init_tuner(state); - } - if (ret < 0) - return -ENODEV; - - /* Always solo frontend */ - set_mode = set_solo_fe; - ret |= it913x_fe_script_loader(state, set_mode); - - ret |= it913x_fe_suspend(state); - return (ret < 0) ? -ENODEV : 0; -} - -static int it913x_fe_init(struct dvb_frontend *fe) -{ - struct it913x_fe_state *state = fe->demodulator_priv; - int ret = 0; - /* Power Up Tuner - common all versions */ - ret = it913x_write_reg(state, PRO_DMOD, 0xec40, 0x1); - - ret |= it913x_fe_script_loader(state, init_1); - - ret |= it913x_write_reg(state, PRO_DMOD, AFE_MEM0, 0x0); - - ret |= it913x_write_reg(state, PRO_DMOD, 0xfba8, 0x0); - - return (ret < 0) ? -ENODEV : 0; -} - -static void it913x_fe_release(struct dvb_frontend *fe) -{ - struct it913x_fe_state *state = fe->demodulator_priv; - kfree(state); -} - -static struct dvb_frontend_ops it913x_fe_ofdm_ops; - -struct dvb_frontend *it913x_fe_attach(struct i2c_adapter *i2c_adap, - u8 i2c_addr, struct ite_config *config) -{ - struct it913x_fe_state *state = NULL; - int ret; - - /* allocate memory for the internal state */ - state = kzalloc(sizeof(struct it913x_fe_state), GFP_KERNEL); - if (state == NULL) - return NULL; - if (config == NULL) - goto error; - - state->i2c_adap = i2c_adap; - state->i2c_addr = i2c_addr; - state->config = config; - - switch (state->config->tuner_id_0) { - case IT9135_51: - case IT9135_52: - case IT9135_60: - case IT9135_61: - case IT9135_62: - state->tuner_type = state->config->tuner_id_0; - break; - default: - case IT9135_38: - state->tuner_type = IT9135_38; - } - - ret = it913x_fe_start(state); - if (ret < 0) - goto error; - - - /* create dvb_frontend */ - memcpy(&state->frontend.ops, &it913x_fe_ofdm_ops, - sizeof(struct dvb_frontend_ops)); - state->frontend.demodulator_priv = state; - - return &state->frontend; -error: - kfree(state); - return NULL; -} -EXPORT_SYMBOL(it913x_fe_attach); - -static struct dvb_frontend_ops it913x_fe_ofdm_ops = { - .delsys = { SYS_DVBT }, - .info = { - .name = "it913x-fe DVB-T", - .frequency_min = 51000000, - .frequency_max = 1680000000, - .frequency_stepsize = 62500, - .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | - FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 | - FE_CAN_FEC_7_8 | FE_CAN_FEC_8_9 | FE_CAN_FEC_AUTO | - FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | - FE_CAN_TRANSMISSION_MODE_AUTO | - FE_CAN_GUARD_INTERVAL_AUTO | - FE_CAN_HIERARCHY_AUTO, - }, - - .release = it913x_fe_release, - - .init = it913x_fe_init, - .sleep = it913x_fe_sleep, - - .set_frontend = it913x_fe_set_frontend, - .get_frontend = it913x_fe_get_frontend, - - .read_status = it913x_fe_read_status, - .read_signal_strength = it913x_fe_read_signal_strength, - .read_snr = it913x_fe_read_snr, - .read_ber = it913x_fe_read_ber, - .read_ucblocks = it913x_fe_read_ucblocks, -}; - -MODULE_DESCRIPTION("it913x Frontend and it9137 tuner"); -MODULE_AUTHOR("Malcolm Priestley tvboxspy@gmail.com"); -MODULE_VERSION("1.15"); -MODULE_LICENSE("GPL"); diff --git a/drivers/media/dvb-frontends/it913x-fe.h b/drivers/media/dvb-frontends/it913x-fe.h deleted file mode 100644 index df0ad42..0000000 --- a/drivers/media/dvb-frontends/it913x-fe.h +++ /dev/null @@ -1,237 +0,0 @@ -/* - * Driver for it913x Frontend - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.= - */ - -#ifndef IT913X_FE_H -#define IT913X_FE_H - -#include -#include -#include "dvb_frontend.h" - -struct ite_config { - u8 chip_ver; - u16 chip_type; - u32 firmware; - u8 firmware_ver; - u8 adc_x2; - u8 tuner_id_0; - u8 tuner_id_1; - u8 dual_mode; - u8 adf; - /* option to read SIGNAL_LEVEL */ - u8 read_slevel; -}; - -#if IS_ENABLED(CONFIG_DVB_IT913X_FE) -extern struct dvb_frontend *it913x_fe_attach(struct i2c_adapter *i2c_adap, - u8 i2c_addr, struct ite_config *config); -#else -static inline struct dvb_frontend *it913x_fe_attach( - struct i2c_adapter *i2c_adap, - u8 i2c_addr, struct ite_config *config) -{ - printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); - return NULL; -} -#endif /* CONFIG_IT913X_FE */ -#define I2C_BASE_ADDR 0x10 -#define DEV_0 0x0 -#define DEV_1 0x10 -#define PRO_LINK 0x0 -#define PRO_DMOD 0x1 -#define DEV_0_DMOD (PRO_DMOD << 0x7) -#define DEV_1_DMOD (DEV_0_DMOD | DEV_1) -#define CHIP2_I2C_ADDR 0x3a - -#define AFE_MEM0 0xfb24 - -#define MP2_SW_RST 0xf99d -#define MP2IF2_SW_RST 0xf9a4 - -#define PADODPU 0xd827 -#define THIRDODPU 0xd828 -#define AGC_O_D 0xd829 - -#define EP0_TX_EN 0xdd11 -#define EP0_TX_NAK 0xdd13 -#define EP4_TX_LEN_LSB 0xdd88 -#define EP4_TX_LEN_MSB 0xdd89 -#define EP4_MAX_PKT 0xdd0c -#define EP5_TX_LEN_LSB 0xdd8a -#define EP5_TX_LEN_MSB 0xdd8b -#define EP5_MAX_PKT 0xdd0d - -#define IO_MUX_POWER_CLK 0xd800 -#define CLK_O_EN 0xd81a -#define I2C_CLK 0xf103 -#define I2C_CLK_100 0x7 -#define I2C_CLK_400 0x1a - -#define D_TPSD_LOCK 0xf5a9 -#define MP2IF2_EN 0xf9a3 -#define MP2IF_SERIAL 0xf985 -#define TSIS_ENABLE 0xf9cd -#define MP2IF2_HALF_PSB 0xf9a5 -#define MP2IF_STOP_EN 0xf9b5 -#define MPEG_FULL_SPEED 0xf990 -#define TOP_HOSTB_SER_MODE 0xd91c - -#define PID_RST 0xf992 -#define PID_EN 0xf993 -#define PID_INX_EN 0xf994 -#define PID_INX 0xf995 -#define PID_LSB 0xf996 -#define PID_MSB 0xf997 - -#define MP2IF_MPEG_PAR_MODE 0xf986 -#define DCA_UPPER_CHIP 0xf731 -#define DCA_LOWER_CHIP 0xf732 -#define DCA_PLATCH 0xf730 -#define DCA_FPGA_LATCH 0xf778 -#define DCA_STAND_ALONE 0xf73c -#define DCA_ENABLE 0xf776 - -#define DVBT_INTEN 0xf41f -#define DVBT_ENABLE 0xf41a -#define HOSTB_DCA_LOWER 0xd91f -#define HOSTB_MPEG_PAR_MODE 0xd91b -#define HOSTB_MPEG_SER_MODE 0xd91c -#define HOSTB_MPEG_SER_DO7 0xd91d -#define HOSTB_DCA_UPPER 0xd91e -#define PADMISCDR2 0xd830 -#define PADMISCDR4 0xd831 -#define PADMISCDR8 0xd832 -#define PADMISCDRSR 0xd833 -#define LOCK3_OUT 0xd8fd - -#define GPIOH1_O 0xd8af -#define GPIOH1_EN 0xd8b0 -#define GPIOH1_ON 0xd8b1 -#define GPIOH3_O 0xd8b3 -#define GPIOH3_EN 0xd8b4 -#define GPIOH3_ON 0xd8b5 -#define GPIOH5_O 0xd8bb -#define GPIOH5_EN 0xd8bc -#define GPIOH5_ON 0xd8bd - -#define AFE_MEM0 0xfb24 - -#define REG_TPSD_TX_MODE 0xf900 -#define REG_TPSD_GI 0xf901 -#define REG_TPSD_HIER 0xf902 -#define REG_TPSD_CONST 0xf903 -#define REG_BW 0xf904 -#define REG_PRIV 0xf905 -#define REG_TPSD_HP_CODE 0xf906 -#define REG_TPSD_LP_CODE 0xf907 - -#define MP2IF_SYNC_LK 0xf999 -#define ADC_FREQ 0xf1cd - -#define TRIGGER_OFSM 0x0000 -/* COEFF Registers start at 0x0001 to 0x0020 */ -#define COEFF_1_2048 0x0001 -#define XTAL_CLK 0x0025 -#define BFS_FCW 0x0029 - -/* Error Regs */ -#define RSD_ABORT_PKT_LSB 0x0032 -#define RSD_ABORT_PKT_MSB 0x0033 -#define RSD_BIT_ERR_0_7 0x0034 -#define RSD_BIT_ERR_8_15 0x0035 -#define RSD_BIT_ERR_23_16 0x0036 -#define RSD_BIT_COUNT_LSB 0x0037 -#define RSD_BIT_COUNT_MSB 0x0038 - -#define TPSD_LOCK 0x003c -#define TRAINING_MODE 0x0040 -#define ADC_X_2 0x0045 -#define TUNER_ID 0x0046 -#define EMPTY_CHANNEL_STATUS 0x0047 -#define SIGNAL_LEVEL 0x0048 -#define SIGNAL_QUALITY 0x0049 -#define EST_SIGNAL_LEVEL 0x004a -#define FREE_BAND 0x004b -#define SUSPEND_FLAG 0x004c -#define VAR_P_INBAND 0x00f7 - -/* Build in tuner types */ -#define IT9137 0x38 -#define IT9135_38 0x38 -#define IT9135_51 0x51 -#define IT9135_52 0x52 -#define IT9135_60 0x60 -#define IT9135_61 0x61 -#define IT9135_62 0x62 - -enum { - CMD_DEMOD_READ = 0, - CMD_DEMOD_WRITE, - CMD_TUNER_READ, - CMD_TUNER_WRITE, - CMD_REG_EEPROM_READ, - CMD_REG_EEPROM_WRITE, - CMD_DATA_READ, - CMD_VAR_READ = 8, - CMD_VAR_WRITE, - CMD_PLATFORM_GET, - CMD_PLATFORM_SET, - CMD_IP_CACHE, - CMD_IP_ADD, - CMD_IP_REMOVE, - CMD_PID_ADD, - CMD_PID_REMOVE, - CMD_SIPSI_GET, - CMD_SIPSI_MPE_RESET, - CMD_H_PID_ADD = 0x15, - CMD_H_PID_REMOVE, - CMD_ABORT, - CMD_IR_GET, - CMD_IR_SET, - CMD_FW_DOWNLOAD = 0x21, - CMD_QUERYINFO, - CMD_BOOT, - CMD_FW_DOWNLOAD_BEGIN, - CMD_FW_DOWNLOAD_END, - CMD_RUN_CODE, - CMD_SCATTER_READ = 0x28, - CMD_SCATTER_WRITE, - CMD_GENERIC_READ, - CMD_GENERIC_WRITE -}; - -enum { - READ_LONG, - WRITE_LONG, - READ_SHORT, - WRITE_SHORT, - READ_DATA, - WRITE_DATA, - WRITE_CMD, -}; - -enum { - IT9135_AUTO = 0, - IT9137_FW, - IT9135_V1_FW, - IT9135_V2_FW, -}; - -#endif /* IT913X_FE_H */ -- cgit v1.1 From 62146a2ae45a3606d7395e88ee26f07485624129 Mon Sep 17 00:00:00 2001 From: Malcolm Priestley Date: Thu, 13 Feb 2014 18:31:02 -0300 Subject: [media] MAINTAINERS: Remove it913x* maintainers entries This driver was removed, and supported devices got moved to anoher driver. So, cleanup MAINTAINERS as well. Signed-off-by: Malcolm Priestley Signed-off-by: Mauro Carvalho Chehab --- MAINTAINERS | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index b2cf5cf..538b894 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4771,22 +4771,6 @@ F: Documentation/hwmon/it87 F: drivers/hwmon/it87.c IT913X MEDIA DRIVER -M: Malcolm Priestley -L: linux-media@vger.kernel.org -W: http://linuxtv.org/ -Q: http://patchwork.linuxtv.org/project/linux-media/list/ -S: Maintained -F: drivers/media/usb/dvb-usb-v2/it913x* - -IT913X FE MEDIA DRIVER -M: Malcolm Priestley -L: linux-media@vger.kernel.org -W: http://linuxtv.org/ -Q: http://patchwork.linuxtv.org/project/linux-media/list/ -S: Maintained -F: drivers/media/dvb-frontends/it913x-fe* - -IT913X MEDIA DRIVER M: Antti Palosaari L: linux-media@vger.kernel.org W: http://linuxtv.org/ -- cgit v1.1 From 7a016b0880ebf9096af577020856810bf6920c89 Mon Sep 17 00:00:00 2001 From: Malcolm Priestley Date: Thu, 13 Feb 2014 18:32:19 -0300 Subject: [media] get_dvb_firmware: it913x: Remove it9137 firmware files Remove it9137 firmware files it9137.txt and it9137 get_dvb_firmware. dvb-usb-it9137-01.fw firmware is no longer in use. Signed-off-by: Malcolm Priestley Signed-off-by: Mauro Carvalho Chehab --- Documentation/dvb/get_dvb_firmware | 22 ++-------------------- Documentation/dvb/it9137.txt | 9 --------- 2 files changed, 2 insertions(+), 29 deletions(-) delete mode 100644 Documentation/dvb/it9137.txt diff --git a/Documentation/dvb/get_dvb_firmware b/Documentation/dvb/get_dvb_firmware index 5d5ee4c..d91b8be 100755 --- a/Documentation/dvb/get_dvb_firmware +++ b/Documentation/dvb/get_dvb_firmware @@ -28,8 +28,8 @@ use IO::Handle; "opera1", "cx231xx", "cx18", "cx23885", "pvrusb2", "mpc718", "af9015", "ngene", "az6027", "lme2510_lg", "lme2510c_s7395", "lme2510c_s7395_old", "drxk", "drxk_terratec_h5", - "drxk_hauppauge_hvr930c", "tda10071", "it9135", "it9137", - "drxk_pctv", "drxk_terratec_htc_stick", "sms1xxx_hcw"); + "drxk_hauppauge_hvr930c", "tda10071", "it9135", "drxk_pctv", + "drxk_terratec_htc_stick", "sms1xxx_hcw"); # Check args syntax() if (scalar(@ARGV) != 1); @@ -727,24 +727,6 @@ sub it9135 { "$fwfile1 $fwfile2" } -sub it9137 { - my $url = "http://kworld.server261.com/kworld/CD/ITE_TiVme/V1.00/"; - my $zipfile = "Driver_V10.323.1.0412.100412.zip"; - my $hash = "79b597dc648698ed6820845c0c9d0d37"; - my $tmpdir = tempdir(DIR => "/tmp", CLEANUP => 0); - my $drvfile = "Driver_V10.323.1.0412.100412/Data/x86/IT9135BDA.sys"; - my $fwfile = "dvb-usb-it9137-01.fw"; - - checkstandard(); - - wgetfile($zipfile, $url . $zipfile); - verify($zipfile, $hash); - unzip($zipfile, $tmpdir); - extract("$tmpdir/$drvfile", 69632, 5731, "$fwfile"); - - "$fwfile" -} - sub tda10071 { my $sourcefile = "PCTV_460e_reference.zip"; my $url = "ftp://ftp.pctvsystems.com/TV/driver/PCTV%2070e%2080e%20100e%20320e%20330e%20800e/"; diff --git a/Documentation/dvb/it9137.txt b/Documentation/dvb/it9137.txt deleted file mode 100644 index 9e6726e..0000000 --- a/Documentation/dvb/it9137.txt +++ /dev/null @@ -1,9 +0,0 @@ -To extract firmware for Kworld UB499-2T (id 1b80:e409) you need to copy the -following file(s) to this directory. - -IT9135BDA.sys Dated Mon 22 Mar 2010 02:20:08 GMT - -extract using dd -dd if=IT9135BDA.sys ibs=1 skip=69632 count=5731 of=dvb-usb-it9137-01.fw - -copy to default firmware location. -- cgit v1.1 From ab3cacf6d92b0c0b4b5c8817b8988dc67a6397ac Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Mon, 10 Feb 2014 08:08:43 -0300 Subject: [media] radio-usb-si4713: make array of structs const The start_seq[] should be const. Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/radio/si4713/radio-usb-si4713.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/media/radio/si4713/radio-usb-si4713.c b/drivers/media/radio/si4713/radio-usb-si4713.c index 779855b..86502b2 100644 --- a/drivers/media/radio/si4713/radio-usb-si4713.c +++ b/drivers/media/radio/si4713/radio-usb-si4713.c @@ -223,7 +223,7 @@ struct si4713_start_seq_table { * (0x03): Get serial number of the board (Response : CB000-00-00) * (0x06, 0x03, 0x03, 0x08, 0x01, 0x0f) : Get Component revision */ -static struct si4713_start_seq_table start_seq[] = { +static const struct si4713_start_seq_table start_seq[] = { { 1, { 0x03 } }, { 2, { 0x32, 0x7f } }, @@ -261,7 +261,7 @@ static int si4713_start_seq(struct si4713_usb_device *radio) for (i = 0; i < ARRAY_SIZE(start_seq); i++) { int len = start_seq[i].len; - u8 *payload = start_seq[i].payload; + const u8 *payload = start_seq[i].payload; memcpy(radio->buffer + 1, payload, len); memset(radio->buffer + len + 1, 0, BUFFER_LENGTH - 1 - len); -- cgit v1.1 From ab58a30162f0383c06388af522bc889a5da38fc6 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Mon, 10 Feb 2014 08:08:44 -0300 Subject: [media] v4l2-subdev: Allow 32-bit compat ioctls Add support for 32-bit ioctls with v4l-subdev device nodes. Rather than keep adding new ioctls to the list in v4l2-compat-ioctl32.c, just check if the ioctl is a non-private V4L2 ioctl and if so, call the conversion code. We keep forgetting to add new ioctls, so this is a more robust solution. In addition extend the subdev API with support for a compat32 function to convert custom v4l-subdev ioctls. Signed-off-by: Hans Verkuil Tested-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab --- drivers/media/v4l2-core/v4l2-compat-ioctl32.c | 101 ++------------------------ drivers/media/v4l2-core/v4l2-subdev.c | 14 ++++ include/media/v4l2-subdev.h | 4 + 3 files changed, 24 insertions(+), 95 deletions(-) diff --git a/drivers/media/v4l2-core/v4l2-compat-ioctl32.c b/drivers/media/v4l2-core/v4l2-compat-ioctl32.c index 8f7a6a4..1b18616 100644 --- a/drivers/media/v4l2-core/v4l2-compat-ioctl32.c +++ b/drivers/media/v4l2-core/v4l2-compat-ioctl32.c @@ -1006,103 +1006,14 @@ long v4l2_compat_ioctl32(struct file *file, unsigned int cmd, unsigned long arg) if (!file->f_op->unlocked_ioctl) return ret; - switch (cmd) { - case VIDIOC_QUERYCAP: - case VIDIOC_RESERVED: - case VIDIOC_ENUM_FMT: - case VIDIOC_G_FMT32: - case VIDIOC_S_FMT32: - case VIDIOC_REQBUFS: - case VIDIOC_QUERYBUF32: - case VIDIOC_G_FBUF32: - case VIDIOC_S_FBUF32: - case VIDIOC_OVERLAY32: - case VIDIOC_QBUF32: - case VIDIOC_EXPBUF: - case VIDIOC_DQBUF32: - case VIDIOC_STREAMON32: - case VIDIOC_STREAMOFF32: - case VIDIOC_G_PARM: - case VIDIOC_S_PARM: - case VIDIOC_G_STD: - case VIDIOC_S_STD: - case VIDIOC_ENUMSTD32: - case VIDIOC_ENUMINPUT32: - case VIDIOC_G_CTRL: - case VIDIOC_S_CTRL: - case VIDIOC_G_TUNER: - case VIDIOC_S_TUNER: - case VIDIOC_G_AUDIO: - case VIDIOC_S_AUDIO: - case VIDIOC_QUERYCTRL: - case VIDIOC_QUERYMENU: - case VIDIOC_G_INPUT32: - case VIDIOC_S_INPUT32: - case VIDIOC_G_OUTPUT32: - case VIDIOC_S_OUTPUT32: - case VIDIOC_ENUMOUTPUT: - case VIDIOC_G_AUDOUT: - case VIDIOC_S_AUDOUT: - case VIDIOC_G_MODULATOR: - case VIDIOC_S_MODULATOR: - case VIDIOC_S_FREQUENCY: - case VIDIOC_G_FREQUENCY: - case VIDIOC_CROPCAP: - case VIDIOC_G_CROP: - case VIDIOC_S_CROP: - case VIDIOC_G_SELECTION: - case VIDIOC_S_SELECTION: - case VIDIOC_G_JPEGCOMP: - case VIDIOC_S_JPEGCOMP: - case VIDIOC_QUERYSTD: - case VIDIOC_TRY_FMT32: - case VIDIOC_ENUMAUDIO: - case VIDIOC_ENUMAUDOUT: - case VIDIOC_G_PRIORITY: - case VIDIOC_S_PRIORITY: - case VIDIOC_G_SLICED_VBI_CAP: - case VIDIOC_LOG_STATUS: - case VIDIOC_G_EXT_CTRLS32: - case VIDIOC_S_EXT_CTRLS32: - case VIDIOC_TRY_EXT_CTRLS32: - case VIDIOC_ENUM_FRAMESIZES: - case VIDIOC_ENUM_FRAMEINTERVALS: - case VIDIOC_G_ENC_INDEX: - case VIDIOC_ENCODER_CMD: - case VIDIOC_TRY_ENCODER_CMD: - case VIDIOC_DECODER_CMD: - case VIDIOC_TRY_DECODER_CMD: - case VIDIOC_DBG_S_REGISTER: - case VIDIOC_DBG_G_REGISTER: - case VIDIOC_S_HW_FREQ_SEEK: - case VIDIOC_S_DV_TIMINGS: - case VIDIOC_G_DV_TIMINGS: - case VIDIOC_DQEVENT: - case VIDIOC_DQEVENT32: - case VIDIOC_SUBSCRIBE_EVENT: - case VIDIOC_UNSUBSCRIBE_EVENT: - case VIDIOC_CREATE_BUFS32: - case VIDIOC_PREPARE_BUF32: - case VIDIOC_ENUM_DV_TIMINGS: - case VIDIOC_QUERY_DV_TIMINGS: - case VIDIOC_DV_TIMINGS_CAP: - case VIDIOC_ENUM_FREQ_BANDS: - case VIDIOC_SUBDEV_G_EDID32: - case VIDIOC_SUBDEV_S_EDID32: + if (_IOC_TYPE(cmd) == 'V' && _IOC_NR(cmd) < BASE_VIDIOC_PRIVATE) ret = do_video_ioctl(file, cmd, arg); - break; + else if (vdev->fops->compat_ioctl32) + ret = vdev->fops->compat_ioctl32(file, cmd, arg); - default: - if (vdev->fops->compat_ioctl32) - ret = vdev->fops->compat_ioctl32(file, cmd, arg); - - if (ret == -ENOIOCTLCMD) - printk(KERN_WARNING "compat_ioctl32: " - "unknown ioctl '%c', dir=%d, #%d (0x%08x)\n", - _IOC_TYPE(cmd), _IOC_DIR(cmd), _IOC_NR(cmd), - cmd); - break; - } + if (ret == -ENOIOCTLCMD) + pr_warn("compat_ioctl32: unknown ioctl '%c', dir=%d, #%d (0x%08x)\n", + _IOC_TYPE(cmd), _IOC_DIR(cmd), _IOC_NR(cmd), cmd); return ret; } EXPORT_SYMBOL_GPL(v4l2_compat_ioctl32); diff --git a/drivers/media/v4l2-core/v4l2-subdev.c b/drivers/media/v4l2-core/v4l2-subdev.c index 996c248..60d2550 100644 --- a/drivers/media/v4l2-core/v4l2-subdev.c +++ b/drivers/media/v4l2-core/v4l2-subdev.c @@ -368,6 +368,17 @@ static long subdev_ioctl(struct file *file, unsigned int cmd, return video_usercopy(file, cmd, arg, subdev_do_ioctl); } +#ifdef CONFIG_COMPAT +static long subdev_compat_ioctl32(struct file *file, unsigned int cmd, + unsigned long arg) +{ + struct video_device *vdev = video_devdata(file); + struct v4l2_subdev *sd = vdev_to_v4l2_subdev(vdev); + + return v4l2_subdev_call(sd, core, compat_ioctl32, cmd, arg); +} +#endif + static unsigned int subdev_poll(struct file *file, poll_table *wait) { struct video_device *vdev = video_devdata(file); @@ -389,6 +400,9 @@ const struct v4l2_file_operations v4l2_subdev_fops = { .owner = THIS_MODULE, .open = subdev_open, .unlocked_ioctl = subdev_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl32 = subdev_compat_ioctl32, +#endif .release = subdev_close, .poll = subdev_poll, }; diff --git a/include/media/v4l2-subdev.h b/include/media/v4l2-subdev.h index d67210a..1752530 100644 --- a/include/media/v4l2-subdev.h +++ b/include/media/v4l2-subdev.h @@ -162,6 +162,10 @@ struct v4l2_subdev_core_ops { int (*g_std)(struct v4l2_subdev *sd, v4l2_std_id *norm); int (*s_std)(struct v4l2_subdev *sd, v4l2_std_id norm); long (*ioctl)(struct v4l2_subdev *sd, unsigned int cmd, void *arg); +#ifdef CONFIG_COMPAT + long (*compat_ioctl32)(struct v4l2_subdev *sd, unsigned int cmd, + unsigned long arg); +#endif #ifdef CONFIG_VIDEO_ADV_DEBUG int (*g_register)(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg); int (*s_register)(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg); -- cgit v1.1 From f0af5e8f018daa83a0e8cfe7d406f81be82ae45d Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Mon, 10 Feb 2014 08:08:45 -0300 Subject: [media] vivi: fix sequence counting The sequence counting was not reset to 0 between each streaming run, and it was increased only every other frame. This is incorrect behavior: the confusion is with FIELD_ALTERNATE systems where each field is transmitted separately and only when both fields have been received is the frame sequence number increased. Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/platform/vivi.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/media/platform/vivi.c b/drivers/media/platform/vivi.c index 2d4e73b..eb09fe6 100644 --- a/drivers/media/platform/vivi.c +++ b/drivers/media/platform/vivi.c @@ -254,7 +254,7 @@ struct vivi_dev { struct v4l2_fract timeperframe; unsigned int width, height; struct vb2_queue vb_vidq; - unsigned int field_count; + unsigned int seq_count; u8 bars[9][3]; u8 line[MAX_WIDTH * 8] __attribute__((__aligned__(4))); @@ -675,8 +675,7 @@ static void vivi_fillbuff(struct vivi_dev *dev, struct vivi_buffer *buf) dev->mv_count += 2; buf->vb.v4l2_buf.field = V4L2_FIELD_INTERLACED; - dev->field_count++; - buf->vb.v4l2_buf.sequence = dev->field_count >> 1; + buf->vb.v4l2_buf.sequence = dev->seq_count++; v4l2_get_timestamp(&buf->vb.v4l2_buf.timestamp); } @@ -901,7 +900,9 @@ static void buffer_queue(struct vb2_buffer *vb) static int start_streaming(struct vb2_queue *vq, unsigned int count) { struct vivi_dev *dev = vb2_get_drv_priv(vq); + dprintk(dev, 1, "%s\n", __func__); + dev->seq_count = 0; return vivi_start_generating(dev); } -- cgit v1.1 From 38aed47b7e0f6e9a6fe38ef7544970604f7bb595 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Mon, 10 Feb 2014 08:08:46 -0300 Subject: [media] vivi: drop unused field Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/platform/vivi.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/media/platform/vivi.c b/drivers/media/platform/vivi.c index eb09fe6..4114bb6 100644 --- a/drivers/media/platform/vivi.c +++ b/drivers/media/platform/vivi.c @@ -191,7 +191,6 @@ struct vivi_buffer { /* common v4l buffer stuff -- must be first */ struct vb2_buffer vb; struct list_head list; - const struct vivi_fmt *fmt; }; struct vivi_dmaqueue { @@ -875,8 +874,6 @@ static int buffer_prepare(struct vb2_buffer *vb) vb2_set_plane_payload(&buf->vb, 0, size); - buf->fmt = dev->fmt; - precalculate_bars(dev); precalculate_line(dev); -- cgit v1.1 From efab6b6a6ea9364ececb955f69a9d3ffc6b782a1 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Mon, 10 Feb 2014 08:08:47 -0300 Subject: [media] vivi: queue_setup improvements Drop the vid_limit module option: there is really no need to limit this. No other driver does that. If you try to allocate more buffers then vb2 will automatically reduce the number of buffers anyway. Also add sanity checks if the size in the fmt argument is going to be used and drop the code that checks against *nbuffers == 0: this can never happen (the vb2 framework ensures that) and the code was wrong anyway since *nbuffers should have been set to the minimum number of required buffers which is 1 for this driver. Since vivi is often used as a template driver it is good to have this driver be as compliant as possible. This broken code was for example copied to the s2255 driver (which is being fixed as well). Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/platform/vivi.c | 24 ++++++++---------------- 1 file changed, 8 insertions(+), 16 deletions(-) diff --git a/drivers/media/platform/vivi.c b/drivers/media/platform/vivi.c index 4114bb6..e9cd96e 100644 --- a/drivers/media/platform/vivi.c +++ b/drivers/media/platform/vivi.c @@ -70,10 +70,6 @@ static unsigned debug; module_param(debug, uint, 0644); MODULE_PARM_DESC(debug, "activates debug info"); -static unsigned int vid_limit = 16; -module_param(vid_limit, uint, 0644); -MODULE_PARM_DESC(vid_limit, "capture memory limit in megabytes"); - /* Global font descriptor */ static const u8 *font8x16; @@ -816,19 +812,15 @@ static int queue_setup(struct vb2_queue *vq, const struct v4l2_format *fmt, struct vivi_dev *dev = vb2_get_drv_priv(vq); unsigned long size; - if (fmt) + size = dev->width * dev->height * dev->pixelsize; + if (fmt) { + if (fmt->fmt.pix.sizeimage < size) + return -EINVAL; size = fmt->fmt.pix.sizeimage; - else - size = dev->width * dev->height * dev->pixelsize; - - if (size == 0) - return -EINVAL; - - if (0 == *nbuffers) - *nbuffers = 32; - - while (size * *nbuffers > vid_limit * 1024 * 1024) - (*nbuffers)--; + /* check against insane over 8K resolution buffers */ + if (size > 7680 * 4320 * dev->pixelsize) + return -EINVAL; + } *nplanes = 1; -- cgit v1.1 From 8b57b9669aa884ac75b8d09c251d6b1755533c15 Mon Sep 17 00:00:00 2001 From: Florian Vaussard Date: Fri, 17 Jan 2014 16:37:38 -0300 Subject: [media] omap3isp: preview: Fix the crop margins Commit 3fdfedaaa "[media] omap3isp: preview: Lower the crop margins" accidentally changed the previewer's cropping, causing the previewer to miss four pixels on each line, thus corrupting the final image. Restored the removed setting. Cc: stable@vger.kernel.org Signed-off-by: Florian Vaussard Signed-off-by: Laurent Pinchart Signed-off-by: Mauro Carvalho Chehab --- drivers/media/platform/omap3isp/isppreview.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/media/platform/omap3isp/isppreview.c b/drivers/media/platform/omap3isp/isppreview.c index 1c776c1..1dbff14 100644 --- a/drivers/media/platform/omap3isp/isppreview.c +++ b/drivers/media/platform/omap3isp/isppreview.c @@ -1079,6 +1079,7 @@ static void preview_config_input_format(struct isp_prev_device *prev, */ static void preview_config_input_size(struct isp_prev_device *prev, u32 active) { + const struct v4l2_mbus_framefmt *format = &prev->formats[PREV_PAD_SINK]; struct isp_device *isp = to_isp_device(prev); unsigned int sph = prev->crop.left; unsigned int eph = prev->crop.left + prev->crop.width - 1; @@ -1086,6 +1087,14 @@ static void preview_config_input_size(struct isp_prev_device *prev, u32 active) unsigned int elv = prev->crop.top + prev->crop.height - 1; u32 features; + if (format->code != V4L2_MBUS_FMT_Y8_1X8 && + format->code != V4L2_MBUS_FMT_Y10_1X10) { + sph -= 2; + eph += 2; + slv -= 2; + elv += 2; + } + features = (prev->params.params[0].features & active) | (prev->params.params[1].features & ~active); -- cgit v1.1 From 4b2f1ed15e01984b5225df715df949084796dfb9 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Fri, 14 Feb 2014 21:40:48 -0300 Subject: [media] omap3isp: Don't try to locate external subdev for mem-to-mem pipelines Memory-to-memory pipelines have no external subdev, we shouldn't try to locate one and validate its configuration. The driver currently works by chance due to another bug that results in failure to locate the external subdev being ignored. This gets rid of the "omap3isp omap3isp: can't find source, failing now" error message in the kernel log when operating on a memory-to-memory pipeline. Signed-off-by: Laurent Pinchart Acked-by: Sakari Ailus Tested-by: Peter Meerwald Signed-off-by: Mauro Carvalho Chehab --- drivers/media/platform/omap3isp/ispvideo.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/media/platform/omap3isp/ispvideo.c b/drivers/media/platform/omap3isp/ispvideo.c index 856fdf5..313fd13 100644 --- a/drivers/media/platform/omap3isp/ispvideo.c +++ b/drivers/media/platform/omap3isp/ispvideo.c @@ -888,6 +888,10 @@ static int isp_video_check_external_subdevs(struct isp_video *video, unsigned int i; int ret = 0; + /* Memory-to-memory pipelines have no external subdev. */ + if (pipe->input != NULL) + return 0; + for (i = 0; i < ARRAY_SIZE(ents); i++) { /* Is the entity part of the pipeline? */ if (!(pipe->entities & (1 << ents[i]->id))) -- cgit v1.1 From 7c486c0fe6c57e06fea5ecb1214b3bc28bafe0e2 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Fri, 14 Feb 2014 21:45:50 -0300 Subject: [media] omap3isp: Don't ignore failure to locate external subdev A failure to locate the external subdev for a non memory-to-memory pipeline is a fatal error, don't ignore it. Signed-off-by: Laurent Pinchart Acked-by: Sakari Ailus Tested-by: Peter Meerwald Signed-off-by: Mauro Carvalho Chehab --- drivers/media/platform/omap3isp/ispvideo.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/omap3isp/ispvideo.c b/drivers/media/platform/omap3isp/ispvideo.c index 313fd13..a62cf0b 100644 --- a/drivers/media/platform/omap3isp/ispvideo.c +++ b/drivers/media/platform/omap3isp/ispvideo.c @@ -886,7 +886,7 @@ static int isp_video_check_external_subdevs(struct isp_video *video, struct v4l2_ext_controls ctrls; struct v4l2_ext_control ctrl; unsigned int i; - int ret = 0; + int ret; /* Memory-to-memory pipelines have no external subdev. */ if (pipe->input != NULL) @@ -909,7 +909,7 @@ static int isp_video_check_external_subdevs(struct isp_video *video, if (!source) { dev_warn(isp->dev, "can't find source, failing now\n"); - return ret; + return -EINVAL; } if (media_entity_type(source) != MEDIA_ENT_T_V4L2_SUBDEV) -- cgit v1.1 From e68084c661953e7b7d78a952156d35e83187c038 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sat, 8 Feb 2014 13:32:11 -0300 Subject: [media] ARM: omap2: cm-t35: Add regulators and clock for camera sensor The camera sensor will soon require regulators and clocks. Register fixed regulators for its VAA and VDD power supplies and a fixed rate clock for its master clock. Signed-off-by: Laurent Pinchart Acked-by: Igor Grinberg Acked-by: Tony Lindgren Signed-off-by: Mauro Carvalho Chehab --- arch/arm/mach-omap2/board-cm-t35.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c index 8dd0ec8..018353d 100644 --- a/arch/arm/mach-omap2/board-cm-t35.c +++ b/arch/arm/mach-omap2/board-cm-t35.c @@ -16,6 +16,8 @@ * */ +#include +#include #include #include #include @@ -542,8 +544,22 @@ static struct isp_platform_data cm_t35_isp_pdata = { .subdevs = cm_t35_isp_subdevs, }; +static struct regulator_consumer_supply cm_t35_camera_supplies[] = { + REGULATOR_SUPPLY("vaa", "3-005d"), + REGULATOR_SUPPLY("vdd", "3-005d"), +}; + static void __init cm_t35_init_camera(void) { + struct clk *clk; + + clk = clk_register_fixed_rate(NULL, "mt9t001-clkin", NULL, CLK_IS_ROOT, + 48000000); + clk_register_clkdev(clk, NULL, "3-005d"); + + regulator_register_fixed(2, cm_t35_camera_supplies, + ARRAY_SIZE(cm_t35_camera_supplies)); + if (omap3_init_camera(&cm_t35_isp_pdata) < 0) pr_warn("CM-T3x: Failed registering camera device!\n"); } -- cgit v1.1 From b2b3593e331cce1718d7388f8a1182b5195be5fb Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sat, 8 Feb 2014 13:33:46 -0300 Subject: [media] mt9t001: Add regulator support The sensor needs two power supplies, VAA and VDD. Require a regulator for each of them. Signed-off-by: Laurent Pinchart Signed-off-by: Mauro Carvalho Chehab --- drivers/media/i2c/mt9t001.c | 206 +++++++++++++++++++++++++++++++++----------- 1 file changed, 156 insertions(+), 50 deletions(-) diff --git a/drivers/media/i2c/mt9t001.c b/drivers/media/i2c/mt9t001.c index d41c70e..9a0bb06 100644 --- a/drivers/media/i2c/mt9t001.c +++ b/drivers/media/i2c/mt9t001.c @@ -13,8 +13,9 @@ */ #include -#include #include +#include +#include #include #include #include @@ -55,6 +56,7 @@ #define MT9T001_OUTPUT_CONTROL_SYNC (1 << 0) #define MT9T001_OUTPUT_CONTROL_CHIP_ENABLE (1 << 1) #define MT9T001_OUTPUT_CONTROL_TEST_DATA (1 << 6) +#define MT9T001_OUTPUT_CONTROL_DEF 0x0002 #define MT9T001_SHUTTER_WIDTH_HIGH 0x08 #define MT9T001_SHUTTER_WIDTH_LOW 0x09 #define MT9T001_SHUTTER_WIDTH_MIN 1 @@ -116,6 +118,11 @@ struct mt9t001 { struct v4l2_subdev subdev; struct media_pad pad; + struct regulator_bulk_data regulators[2]; + + struct mutex power_lock; /* lock to protect power_count */ + int power_count; + struct v4l2_mbus_framefmt format; struct v4l2_rect crop; @@ -159,6 +166,62 @@ static int mt9t001_set_output_control(struct mt9t001 *mt9t001, u16 clear, return 0; } +static int mt9t001_reset(struct mt9t001 *mt9t001) +{ + struct i2c_client *client = v4l2_get_subdevdata(&mt9t001->subdev); + int ret; + + /* Reset the chip and stop data read out */ + ret = mt9t001_write(client, MT9T001_RESET, 1); + if (ret < 0) + return ret; + + ret = mt9t001_write(client, MT9T001_RESET, 0); + if (ret < 0) + return ret; + + mt9t001->output_control = MT9T001_OUTPUT_CONTROL_DEF; + + return mt9t001_set_output_control(mt9t001, + MT9T001_OUTPUT_CONTROL_CHIP_ENABLE, + 0); +} + +static int mt9t001_power_on(struct mt9t001 *mt9t001) +{ + /* Bring up the supplies */ + return regulator_bulk_enable(ARRAY_SIZE(mt9t001->regulators), + mt9t001->regulators); +} + +static void mt9t001_power_off(struct mt9t001 *mt9t001) +{ + regulator_bulk_disable(ARRAY_SIZE(mt9t001->regulators), + mt9t001->regulators); + +static int __mt9t001_set_power(struct mt9t001 *mt9t001, bool on) +{ + struct i2c_client *client = v4l2_get_subdevdata(&mt9t001->subdev); + int ret; + + if (!on) { + mt9t001_power_off(mt9t001); + return 0; + } + + ret = mt9t001_power_on(mt9t001); + if (ret < 0) + return ret; + + ret = mt9t001_reset(mt9t001); + if (ret < 0) { + dev_err(&client->dev, "Failed to reset the camera\n"); + return ret; + } + + return v4l2_ctrl_handler_setup(&mt9t001->ctrls); +} + /* ----------------------------------------------------------------------------- * V4L2 subdev video operations */ @@ -195,6 +258,7 @@ static int mt9t001_s_stream(struct v4l2_subdev *subdev, int enable) { const u16 mode = MT9T001_OUTPUT_CONTROL_CHIP_ENABLE; struct i2c_client *client = v4l2_get_subdevdata(subdev); + struct mt9t001_platform_data *pdata = client->dev.platform_data; struct mt9t001 *mt9t001 = to_mt9t001(subdev); struct v4l2_mbus_framefmt *format = &mt9t001->format; struct v4l2_rect *crop = &mt9t001->crop; @@ -205,6 +269,14 @@ static int mt9t001_s_stream(struct v4l2_subdev *subdev, int enable) if (!enable) return mt9t001_set_output_control(mt9t001, mode, 0); + /* Configure the pixel clock polarity */ + if (pdata->clk_pol) { + ret = mt9t001_write(client, MT9T001_PIXEL_CLOCK, + MT9T001_PIXEL_CLOCK_INVERT); + if (ret < 0) + return ret; + } + /* Configure the window size and row/column bin */ hratio = DIV_ROUND_CLOSEST(crop->width, format->width); vratio = DIV_ROUND_CLOSEST(crop->height, format->height); @@ -630,9 +702,67 @@ static const struct v4l2_ctrl_config mt9t001_gains[] = { }; /* ----------------------------------------------------------------------------- + * V4L2 subdev core operations + */ + +static int mt9t001_set_power(struct v4l2_subdev *subdev, int on) +{ + struct mt9t001 *mt9t001 = to_mt9t001(subdev); + int ret = 0; + + mutex_lock(&mt9t001->power_lock); + + /* If the power count is modified from 0 to != 0 or from != 0 to 0, + * update the power state. + */ + if (mt9t001->power_count == !on) { + ret = __mt9t001_set_power(mt9t001, !!on); + if (ret < 0) + goto out; + } + + /* Update the power count. */ + mt9t001->power_count += on ? 1 : -1; + WARN_ON(mt9t001->power_count < 0); + +out: + mutex_unlock(&mt9t001->power_lock); + return ret; +} + +/* ----------------------------------------------------------------------------- * V4L2 subdev internal operations */ +static int mt9t001_registered(struct v4l2_subdev *subdev) +{ + struct i2c_client *client = v4l2_get_subdevdata(subdev); + struct mt9t001 *mt9t001 = to_mt9t001(subdev); + s32 data; + int ret; + + ret = mt9t001_power_on(mt9t001); + if (ret < 0) { + dev_err(&client->dev, "MT9T001 power up failed\n"); + return ret; + } + + /* Read out the chip version register */ + data = mt9t001_read(client, MT9T001_CHIP_VERSION); + mt9t001_power_off(mt9t001); + + if (data != MT9T001_CHIP_ID) { + dev_err(&client->dev, + "MT9T001 not detected, wrong version 0x%04x\n", data); + return -ENODEV; + } + + dev_info(&client->dev, "MT9T001 detected at address 0x%02x\n", + client->addr); + + return 0; +} + static int mt9t001_open(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh) { struct v4l2_mbus_framefmt *format; @@ -651,9 +781,18 @@ static int mt9t001_open(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh) format->field = V4L2_FIELD_NONE; format->colorspace = V4L2_COLORSPACE_SRGB; - return 0; + return mt9t001_set_power(subdev, 1); } +static int mt9t001_close(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh) +{ + return mt9t001_set_power(subdev, 0); +} + +static struct v4l2_subdev_core_ops mt9t001_subdev_core_ops = { + .s_power = mt9t001_set_power, +}; + static struct v4l2_subdev_video_ops mt9t001_subdev_video_ops = { .s_stream = mt9t001_s_stream, }; @@ -668,58 +807,17 @@ static struct v4l2_subdev_pad_ops mt9t001_subdev_pad_ops = { }; static struct v4l2_subdev_ops mt9t001_subdev_ops = { + .core = &mt9t001_subdev_core_ops, .video = &mt9t001_subdev_video_ops, .pad = &mt9t001_subdev_pad_ops, }; static struct v4l2_subdev_internal_ops mt9t001_subdev_internal_ops = { + .registered = mt9t001_registered, .open = mt9t001_open, + .close = mt9t001_close, }; -static int mt9t001_video_probe(struct i2c_client *client) -{ - struct mt9t001_platform_data *pdata = client->dev.platform_data; - s32 data; - int ret; - - dev_info(&client->dev, "Probing MT9T001 at address 0x%02x\n", - client->addr); - - /* Reset the chip and stop data read out */ - ret = mt9t001_write(client, MT9T001_RESET, 1); - if (ret < 0) - return ret; - - ret = mt9t001_write(client, MT9T001_RESET, 0); - if (ret < 0) - return ret; - - ret = mt9t001_write(client, MT9T001_OUTPUT_CONTROL, 0); - if (ret < 0) - return ret; - - /* Configure the pixel clock polarity */ - if (pdata->clk_pol) { - ret = mt9t001_write(client, MT9T001_PIXEL_CLOCK, - MT9T001_PIXEL_CLOCK_INVERT); - if (ret < 0) - return ret; - } - - /* Read and check the sensor version */ - data = mt9t001_read(client, MT9T001_CHIP_VERSION); - if (data != MT9T001_CHIP_ID) { - dev_err(&client->dev, "MT9T001 not detected, wrong version " - "0x%04x\n", data); - return -ENODEV; - } - - dev_info(&client->dev, "MT9T001 detected at address 0x%02x\n", - client->addr); - - return ret; -} - static int mt9t001_probe(struct i2c_client *client, const struct i2c_device_id *did) { @@ -740,14 +838,22 @@ static int mt9t001_probe(struct i2c_client *client, return -EIO; } - ret = mt9t001_video_probe(client); - if (ret < 0) - return ret; - mt9t001 = devm_kzalloc(&client->dev, sizeof(*mt9t001), GFP_KERNEL); if (!mt9t001) return -ENOMEM; + mutex_init(&mt9t001->power_lock); + mt9t001->output_control = MT9T001_OUTPUT_CONTROL_DEF; + + mt9t001->regulators[0].supply = "vdd"; + mt9t001->regulators[1].supply = "vaa"; + + ret = devm_regulator_bulk_get(&client->dev, 2, mt9t001->regulators); + if (ret < 0) { + dev_err(&client->dev, "Unable to get regulators\n"); + return ret; + } + v4l2_ctrl_handler_init(&mt9t001->ctrls, ARRAY_SIZE(mt9t001_ctrls) + ARRAY_SIZE(mt9t001_gains) + 4); -- cgit v1.1 From b16fdd53de8f46da425a87f7175276d1c8d92355 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sat, 8 Feb 2014 13:33:46 -0300 Subject: [media] mt9t001: Add clock support The sensor needs a master clock, handle it explictly in the driver. Signed-off-by: Laurent Pinchart Signed-off-by: Mauro Carvalho Chehab --- drivers/media/i2c/mt9t001.c | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/drivers/media/i2c/mt9t001.c b/drivers/media/i2c/mt9t001.c index 9a0bb06..422e068 100644 --- a/drivers/media/i2c/mt9t001.c +++ b/drivers/media/i2c/mt9t001.c @@ -12,6 +12,7 @@ * published by the Free Software Foundation. */ +#include #include #include #include @@ -118,6 +119,7 @@ struct mt9t001 { struct v4l2_subdev subdev; struct media_pad pad; + struct clk *clk; struct regulator_bulk_data regulators[2]; struct mutex power_lock; /* lock to protect power_count */ @@ -189,9 +191,21 @@ static int mt9t001_reset(struct mt9t001 *mt9t001) static int mt9t001_power_on(struct mt9t001 *mt9t001) { + int ret; + /* Bring up the supplies */ - return regulator_bulk_enable(ARRAY_SIZE(mt9t001->regulators), - mt9t001->regulators); + ret = regulator_bulk_enable(ARRAY_SIZE(mt9t001->regulators), + mt9t001->regulators); + if (ret < 0) + return ret; + + /* Enable clock */ + ret = clk_prepare_enable(mt9t001->clk); + if (ret < 0) + regulator_bulk_disable(ARRAY_SIZE(mt9t001->regulators), + mt9t001->regulators); + + return ret; } static void mt9t001_power_off(struct mt9t001 *mt9t001) @@ -199,6 +213,9 @@ static void mt9t001_power_off(struct mt9t001 *mt9t001) regulator_bulk_disable(ARRAY_SIZE(mt9t001->regulators), mt9t001->regulators); + clk_disable_unprepare(mt9t001->clk); +} + static int __mt9t001_set_power(struct mt9t001 *mt9t001, bool on) { struct i2c_client *client = v4l2_get_subdevdata(&mt9t001->subdev); @@ -854,6 +871,12 @@ static int mt9t001_probe(struct i2c_client *client, return ret; } + mt9t001->clk = devm_clk_get(&client->dev, NULL); + if (IS_ERR(mt9t001->clk)) { + dev_err(&client->dev, "Unable to get clock\n"); + return PTR_ERR(mt9t001->clk); + } + v4l2_ctrl_handler_init(&mt9t001->ctrls, ARRAY_SIZE(mt9t001_ctrls) + ARRAY_SIZE(mt9t001_gains) + 4); -- cgit v1.1 From e8e45593c920a05b1f4b9d94738a84039b9b4f22 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sat, 8 Feb 2014 13:31:58 -0300 Subject: [media] mt9p031: Fix typo in comment Signed-off-by: Laurent Pinchart Signed-off-by: Mauro Carvalho Chehab --- drivers/media/i2c/mt9p031.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/i2c/mt9p031.c b/drivers/media/i2c/mt9p031.c index e5ddf47..a271662 100644 --- a/drivers/media/i2c/mt9p031.c +++ b/drivers/media/i2c/mt9p031.c @@ -285,7 +285,7 @@ static int mt9p031_power_on(struct mt9p031 *mt9p031) if (ret < 0) return ret; - /* Emable clock */ + /* Enable clock */ if (mt9p031->clk) clk_prepare_enable(mt9p031->clk); -- cgit v1.1 From a970449e40789a0056424668da5b56f57569ea73 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sun, 9 Feb 2014 17:31:47 -0300 Subject: [media] mt9p031: Add support for PLL bypass When the input clock frequency is out of bounds for the PLL, bypass the PLL and just divide the input clock to achieve the requested output frequency. Signed-off-by: Laurent Pinchart Signed-off-by: Mauro Carvalho Chehab --- drivers/media/i2c/mt9p031.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/media/i2c/mt9p031.c b/drivers/media/i2c/mt9p031.c index a271662..fec76d3 100644 --- a/drivers/media/i2c/mt9p031.c +++ b/drivers/media/i2c/mt9p031.c @@ -78,6 +78,9 @@ #define MT9P031_PLL_CONFIG_1 0x11 #define MT9P031_PLL_CONFIG_2 0x12 #define MT9P031_PIXEL_CLOCK_CONTROL 0x0a +#define MT9P031_PIXEL_CLOCK_INVERT (1 << 15) +#define MT9P031_PIXEL_CLOCK_SHIFT(n) ((n) << 8) +#define MT9P031_PIXEL_CLOCK_DIVIDE(n) ((n) << 0) #define MT9P031_FRAME_RESTART 0x0b #define MT9P031_SHUTTER_DELAY 0x0c #define MT9P031_RST 0x0d @@ -130,6 +133,8 @@ struct mt9p031 { enum mt9p031_model model; struct aptina_pll pll; + unsigned int clk_div; + bool use_pll; int reset; struct v4l2_ctrl_handler ctrls; @@ -198,6 +203,11 @@ static int mt9p031_reset(struct mt9p031 *mt9p031) if (ret < 0) return ret; + ret = mt9p031_write(client, MT9P031_PIXEL_CLOCK_CONTROL, + MT9P031_PIXEL_CLOCK_DIVIDE(mt9p031->clk_div)); + if (ret < 0) + return ret; + return mt9p031_set_output_control(mt9p031, MT9P031_OUTPUT_CONTROL_CEN, 0); } @@ -229,8 +239,24 @@ static int mt9p031_clk_setup(struct mt9p031 *mt9p031) clk_set_rate(mt9p031->clk, pdata->ext_freq); + /* If the external clock frequency is out of bounds for the PLL use the + * pixel clock divider only and disable the PLL. + */ + if (pdata->ext_freq > limits.ext_clock_max) { + unsigned int div; + + div = DIV_ROUND_UP(pdata->ext_freq, pdata->target_freq); + div = roundup_pow_of_two(div) / 2; + + mt9p031->clk_div = max_t(unsigned int, div, 64); + mt9p031->use_pll = false; + + return 0; + } + mt9p031->pll.ext_clock = pdata->ext_freq; mt9p031->pll.pix_clock = pdata->target_freq; + mt9p031->use_pll = true; return aptina_pll_calculate(&client->dev, &limits, &mt9p031->pll); } @@ -240,6 +266,9 @@ static int mt9p031_pll_enable(struct mt9p031 *mt9p031) struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); int ret; + if (!mt9p031->use_pll) + return 0; + ret = mt9p031_write(client, MT9P031_PLL_CONTROL, MT9P031_PLL_CONTROL_PWRON); if (ret < 0) @@ -265,6 +294,9 @@ static inline int mt9p031_pll_disable(struct mt9p031 *mt9p031) { struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); + if (!mt9p031->use_pll) + return 0; + return mt9p031_write(client, MT9P031_PLL_CONTROL, MT9P031_PLL_CONTROL_PWROFF); } -- cgit v1.1 From ee2d16d7b3c95a65ed0434841568bd3f82712338 Mon Sep 17 00:00:00 2001 From: "Lad, Prabhakar" Date: Tue, 21 Jan 2014 02:20:57 -0300 Subject: [media] mt9p031: Check return value of clk_prepare_enable/clk_set_rate clk_set_rate(), clk_prepare_enable() functions can fail, so check the return values to avoid surprises. Signed-off-by: Lad, Prabhakar Signed-off-by: Laurent Pinchart Signed-off-by: Mauro Carvalho Chehab --- drivers/media/i2c/mt9p031.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/media/i2c/mt9p031.c b/drivers/media/i2c/mt9p031.c index fec76d3..dd7b258 100644 --- a/drivers/media/i2c/mt9p031.c +++ b/drivers/media/i2c/mt9p031.c @@ -232,12 +232,15 @@ static int mt9p031_clk_setup(struct mt9p031 *mt9p031) struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); struct mt9p031_platform_data *pdata = mt9p031->pdata; + int ret; mt9p031->clk = devm_clk_get(&client->dev, NULL); if (IS_ERR(mt9p031->clk)) return PTR_ERR(mt9p031->clk); - clk_set_rate(mt9p031->clk, pdata->ext_freq); + ret = clk_set_rate(mt9p031->clk, pdata->ext_freq); + if (ret < 0) + return ret; /* If the external clock frequency is out of bounds for the PLL use the * pixel clock divider only and disable the PLL. @@ -318,8 +321,14 @@ static int mt9p031_power_on(struct mt9p031 *mt9p031) return ret; /* Enable clock */ - if (mt9p031->clk) - clk_prepare_enable(mt9p031->clk); + if (mt9p031->clk) { + ret = clk_prepare_enable(mt9p031->clk); + if (ret) { + regulator_bulk_disable(ARRAY_SIZE(mt9p031->regulators), + mt9p031->regulators); + return ret; + } + } /* Now RESET_BAR must be high */ if (gpio_is_valid(mt9p031->reset)) { -- cgit v1.1 From 79019190a4c3a082c739cf7cc73a040c48b333bb Mon Sep 17 00:00:00 2001 From: "Lad, Prabhakar" Date: Fri, 17 Jan 2014 06:22:47 -0300 Subject: [media] mt9v032: Check return value of clk_prepare_enable/clk_set_rate clk_set_rate(), clk_prepare_enable() functions can fail, so check the return values to avoid surprises. Signed-off-by: Lad, Prabhakar Signed-off-by: Laurent Pinchart Signed-off-by: Mauro Carvalho Chehab --- drivers/media/i2c/mt9v032.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/media/i2c/mt9v032.c b/drivers/media/i2c/mt9v032.c index 36c504b..40172b8 100644 --- a/drivers/media/i2c/mt9v032.c +++ b/drivers/media/i2c/mt9v032.c @@ -317,8 +317,14 @@ static int mt9v032_power_on(struct mt9v032 *mt9v032) struct i2c_client *client = v4l2_get_subdevdata(&mt9v032->subdev); int ret; - clk_set_rate(mt9v032->clk, mt9v032->sysclk); - clk_prepare_enable(mt9v032->clk); + ret = clk_set_rate(mt9v032->clk, mt9v032->sysclk); + if (ret < 0) + return ret; + + ret = clk_prepare_enable(mt9v032->clk); + if (ret) + return ret; + udelay(1); /* Reset the chip and stop data read out */ -- cgit v1.1 From daf41ac2c4b5b2e663079ccc58b8d6a70a3c111b Mon Sep 17 00:00:00 2001 From: Oliver Neukum Date: Thu, 23 Jan 2014 07:28:24 -0300 Subject: [media] uvcvideo: Simplify redundant check x < constant implies x + unsigned < constant That check just obfuscates the code Signed-off-by: Oliver Neukum Signed-off-by: Laurent Pinchart Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/uvc/uvc_driver.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/usb/uvc/uvc_driver.c b/drivers/media/usb/uvc/uvc_driver.c index c3bb250..b6cac17 100644 --- a/drivers/media/usb/uvc/uvc_driver.c +++ b/drivers/media/usb/uvc/uvc_driver.c @@ -925,7 +925,7 @@ static int uvc_parse_standard_control(struct uvc_device *dev, case UVC_VC_HEADER: n = buflen >= 12 ? buffer[11] : 0; - if (buflen < 12 || buflen < 12 + n) { + if (buflen < 12 + n) { uvc_trace(UVC_TRACE_DESCR, "device %d videocontrol " "interface %d HEADER error\n", udev->devnum, alts->desc.bInterfaceNumber); -- cgit v1.1 From 79af67e77f86404e77e65ad954bfe5030db2ca02 Mon Sep 17 00:00:00 2001 From: Thomas Pugliese Date: Fri, 24 Jan 2014 18:17:28 -0300 Subject: [media] uvcvideo: Update uvc_endpoint_max_bpi to handle USB_SPEED_WIRELESS devices Isochronous endpoints on devices with speed == USB_SPEED_WIRELESS can have a max packet size ranging from 1-3584 bytes. Add a case to uvc_endpoint_max_bpi to handle USB_SPEED_WIRELESS. Otherwise endpoints for those devices will fall to the default case which masks off any values > 2047. This causes uvc_init_video to underestimate the bandwidth available and fail to find a suitable alt setting for high bandwidth video streams. Signed-off-by: Thomas Pugliese Signed-off-by: Laurent Pinchart Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/uvc/uvc_video.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/media/usb/uvc/uvc_video.c b/drivers/media/usb/uvc/uvc_video.c index 898c208..103cd4e 100644 --- a/drivers/media/usb/uvc/uvc_video.c +++ b/drivers/media/usb/uvc/uvc_video.c @@ -1453,6 +1453,9 @@ static unsigned int uvc_endpoint_max_bpi(struct usb_device *dev, case USB_SPEED_HIGH: psize = usb_endpoint_maxp(&ep->desc); return (psize & 0x07ff) * (1 + ((psize >> 11) & 3)); + case USB_SPEED_WIRELESS: + psize = usb_endpoint_maxp(&ep->desc); + return psize; default: psize = usb_endpoint_maxp(&ep->desc); return psize & 0x07ff; -- cgit v1.1 From ccc135c380338ccc6643f6dd7f16000ae7384a13 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 18 Feb 2014 10:02:50 -0300 Subject: [media] uvcvideo: Remove duplicate check for number of buffers in queue_setup videobuf2 already ensures that the number of buffers will not exceed VIDEO_MAX_FRAME, which is equal to our arbitraty limit of UVC_MAX_VIDEO_BUFFERS. Remove the duplicate check. Signed-off-by: Laurent Pinchart Tested-by: Philipp Zabel Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/uvc/uvc_queue.c | 3 --- drivers/media/usb/uvc/uvcvideo.h | 2 -- 2 files changed, 5 deletions(-) diff --git a/drivers/media/usb/uvc/uvc_queue.c b/drivers/media/usb/uvc/uvc_queue.c index cd962be..254bc34 100644 --- a/drivers/media/usb/uvc/uvc_queue.c +++ b/drivers/media/usb/uvc/uvc_queue.c @@ -48,9 +48,6 @@ static int uvc_queue_setup(struct vb2_queue *vq, const struct v4l2_format *fmt, struct uvc_streaming *stream = container_of(queue, struct uvc_streaming, queue); - if (*nbuffers > UVC_MAX_VIDEO_BUFFERS) - *nbuffers = UVC_MAX_VIDEO_BUFFERS; - *nplanes = 1; sizes[0] = stream->ctrl.dwMaxVideoFrameSize; diff --git a/drivers/media/usb/uvc/uvcvideo.h b/drivers/media/usb/uvc/uvcvideo.h index 9e35982..6173632 100644 --- a/drivers/media/usb/uvc/uvcvideo.h +++ b/drivers/media/usb/uvc/uvcvideo.h @@ -115,8 +115,6 @@ #define UVC_URBS 5 /* Maximum number of packets per URB. */ #define UVC_MAX_PACKETS 32 -/* Maximum number of video buffers. */ -#define UVC_MAX_VIDEO_BUFFERS 32 /* Maximum status buffer size in bytes of interrupt URB. */ #define UVC_MAX_STATUS_SIZE 16 -- cgit v1.1 From bddb9d0e97f20dfd614d3dd56043418766703936 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 18 Feb 2014 10:40:47 -0300 Subject: [media] uvcvideo: Support allocating buffers larger than the current frame size The queue_setup handler takes an optional format argument that can be used to allocate buffers for a format different than the current format. The uvcvideo driver doesn't support changing the format when buffers have been allocated, but there's no reason not to support allocating buffers larger than the minimum size. When the format argument isn't NULL verify that the requested image size is large enough for the current format and use it for the buffer size. Signed-off-by: Laurent Pinchart Tested-by: Philipp Zabel Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/uvc/uvc_queue.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/media/usb/uvc/uvc_queue.c b/drivers/media/usb/uvc/uvc_queue.c index 254bc34..d46dd70 100644 --- a/drivers/media/usb/uvc/uvc_queue.c +++ b/drivers/media/usb/uvc/uvc_queue.c @@ -48,9 +48,14 @@ static int uvc_queue_setup(struct vb2_queue *vq, const struct v4l2_format *fmt, struct uvc_streaming *stream = container_of(queue, struct uvc_streaming, queue); + /* Make sure the image size is large enough. */ + if (fmt && fmt->fmt.pix.sizeimage < stream->ctrl.dwMaxVideoFrameSize) + return -EINVAL; + *nplanes = 1; - sizes[0] = stream->ctrl.dwMaxVideoFrameSize; + sizes[0] = fmt ? fmt->fmt.pix.sizeimage + : stream->ctrl.dwMaxVideoFrameSize; return 0; } -- cgit v1.1 From 6e9179e2af61f93e6416c3dd11aca46dcd5a68e8 Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Wed, 29 Jan 2014 13:13:52 -0300 Subject: [media] uvcvideo: Enable VIDIOC_CREATE_BUFS This patch enables the ioctl to create additional buffers on the videobuf2 capture queue. [laurent.pinchart@ideasonboard.com: Acquire privileges instead of just checking them in VIDIOC_CREATE_BUFS implementation] Signed-off-by: Philipp Zabel Signed-off-by: Laurent Pinchart Tested-by: Philipp Zabel Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/uvc/uvc_queue.c | 12 ++++++++++++ drivers/media/usb/uvc/uvc_v4l2.c | 11 +++++++++++ drivers/media/usb/uvc/uvcvideo.h | 2 ++ 3 files changed, 25 insertions(+) diff --git a/drivers/media/usb/uvc/uvc_queue.c b/drivers/media/usb/uvc/uvc_queue.c index d46dd70..ff7be97 100644 --- a/drivers/media/usb/uvc/uvc_queue.c +++ b/drivers/media/usb/uvc/uvc_queue.c @@ -198,6 +198,18 @@ int uvc_query_buffer(struct uvc_video_queue *queue, struct v4l2_buffer *buf) return ret; } +int uvc_create_buffers(struct uvc_video_queue *queue, + struct v4l2_create_buffers *cb) +{ + int ret; + + mutex_lock(&queue->mutex); + ret = vb2_create_bufs(&queue->queue, cb); + mutex_unlock(&queue->mutex); + + return ret; +} + int uvc_queue_buffer(struct uvc_video_queue *queue, struct v4l2_buffer *buf) { int ret; diff --git a/drivers/media/usb/uvc/uvc_v4l2.c b/drivers/media/usb/uvc/uvc_v4l2.c index 3afff92..378ae02 100644 --- a/drivers/media/usb/uvc/uvc_v4l2.c +++ b/drivers/media/usb/uvc/uvc_v4l2.c @@ -1000,6 +1000,17 @@ static long uvc_v4l2_do_ioctl(struct file *file, unsigned int cmd, void *arg) return uvc_query_buffer(&stream->queue, buf); } + case VIDIOC_CREATE_BUFS: + { + struct v4l2_create_buffers *cb = arg; + + ret = uvc_acquire_privileges(handle); + if (ret < 0) + return ret; + + return uvc_create_buffers(&stream->queue, cb); + } + case VIDIOC_QBUF: if (!uvc_has_privileges(handle)) return -EBUSY; diff --git a/drivers/media/usb/uvc/uvcvideo.h b/drivers/media/usb/uvc/uvcvideo.h index 6173632..143d5e5 100644 --- a/drivers/media/usb/uvc/uvcvideo.h +++ b/drivers/media/usb/uvc/uvcvideo.h @@ -614,6 +614,8 @@ extern int uvc_alloc_buffers(struct uvc_video_queue *queue, extern void uvc_free_buffers(struct uvc_video_queue *queue); extern int uvc_query_buffer(struct uvc_video_queue *queue, struct v4l2_buffer *v4l2_buf); +extern int uvc_create_buffers(struct uvc_video_queue *queue, + struct v4l2_create_buffers *v4l2_cb); extern int uvc_queue_buffer(struct uvc_video_queue *queue, struct v4l2_buffer *v4l2_buf); extern int uvc_dequeue_buffer(struct uvc_video_queue *queue, -- cgit v1.1 From 57802c52610b534fbec7537da4f7d5554964cb60 Mon Sep 17 00:00:00 2001 From: Levente Kurusa Date: Sat, 15 Feb 2014 07:17:11 -0300 Subject: [media] staging: davinci_vpfe: fix error check The check would check the pointer, which is never less than 0. According to the error message, the correct check would be to check the return value of ipipe_mode. Check that instead. Reported-by: David Binderman Signed-off-by: Levente Kurusa Reviewed-by: Josh Triplett Signed-off-by: Lad, Prabhakar Signed-off-by: Mauro Carvalho Chehab --- drivers/staging/media/davinci_vpfe/dm365_ipipe_hw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/staging/media/davinci_vpfe/dm365_ipipe_hw.c b/drivers/staging/media/davinci_vpfe/dm365_ipipe_hw.c index 2d36b60..b2daf5e 100644 --- a/drivers/staging/media/davinci_vpfe/dm365_ipipe_hw.c +++ b/drivers/staging/media/davinci_vpfe/dm365_ipipe_hw.c @@ -267,7 +267,7 @@ int config_ipipe_hw(struct vpfe_ipipe_device *ipipe) } ipipe_mode = get_ipipe_mode(ipipe); - if (ipipe < 0) { + if (ipipe_mode < 0) { pr_err("Failed to get ipipe mode"); return -EINVAL; } -- cgit v1.1 From 381d0a40a494526886dd2320b773e87441de485e Mon Sep 17 00:00:00 2001 From: Michael Opdenacker Date: Mon, 9 Dec 2013 07:16:22 -0300 Subject: [media] davinci: vpfe: remove deprecated IRQF_DISABLED This patch proposes to remove the use of the IRQF_DISABLED flag It's a NOOP since 2.6.35 and it will be removed one day. Signed-off-by: Michael Opdenacker Acked-by: Lad, Prabhakar Signed-off-by: Lad, Prabhakar Signed-off-by: Mauro Carvalho Chehab --- drivers/staging/media/davinci_vpfe/vpfe_mc_capture.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/staging/media/davinci_vpfe/vpfe_mc_capture.c b/drivers/staging/media/davinci_vpfe/vpfe_mc_capture.c index d8ce20d..cda8388 100644 --- a/drivers/staging/media/davinci_vpfe/vpfe_mc_capture.c +++ b/drivers/staging/media/davinci_vpfe/vpfe_mc_capture.c @@ -298,7 +298,7 @@ static int vpfe_attach_irq(struct vpfe_device *vpfe_dev) { int ret = 0; - ret = request_irq(vpfe_dev->ccdc_irq0, vpfe_isr, IRQF_DISABLED, + ret = request_irq(vpfe_dev->ccdc_irq0, vpfe_isr, 0, "vpfe_capture0", vpfe_dev); if (ret < 0) { v4l2_err(&vpfe_dev->v4l2_dev, @@ -306,7 +306,7 @@ static int vpfe_attach_irq(struct vpfe_device *vpfe_dev) return ret; } - ret = request_irq(vpfe_dev->ccdc_irq1, vpfe_vdint1_isr, IRQF_DISABLED, + ret = request_irq(vpfe_dev->ccdc_irq1, vpfe_vdint1_isr, 0, "vpfe_capture1", vpfe_dev); if (ret < 0) { v4l2_err(&vpfe_dev->v4l2_dev, @@ -316,7 +316,7 @@ static int vpfe_attach_irq(struct vpfe_device *vpfe_dev) } ret = request_irq(vpfe_dev->imp_dma_irq, vpfe_imp_dma_isr, - IRQF_DISABLED, "Imp_Sdram_Irq", vpfe_dev); + 0, "Imp_Sdram_Irq", vpfe_dev); if (ret < 0) { v4l2_err(&vpfe_dev->v4l2_dev, "Error: requesting IMP IRQ interrupt\n"); -- cgit v1.1 From d86c6a8cc5ce53d539425ae3aa5e93122628ff52 Mon Sep 17 00:00:00 2001 From: Dean Anderson Date: Tue, 4 Feb 2014 17:18:03 -0300 Subject: [media] s2255drv: removal of s2255_dmaqueue structure Removal of unused and unnecessary s2255dma_queue structure. Signed-off-by: Dean Anderson Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/s2255/s2255drv.c | 29 ++++++++++------------------- 1 file changed, 10 insertions(+), 19 deletions(-) diff --git a/drivers/media/usb/s2255/s2255drv.c b/drivers/media/usb/s2255/s2255drv.c index c6bdccc..5f09a56 100644 --- a/drivers/media/usb/s2255/s2255drv.c +++ b/drivers/media/usb/s2255/s2255drv.c @@ -1,7 +1,7 @@ /* * s2255drv.c - a driver for the Sensoray 2255 USB video capture device * - * Copyright (C) 2007-2013 by Sensoray Company Inc. + * Copyright (C) 2007-2014 by Sensoray Company Inc. * Dean Anderson * * Some video buffer code based on vivi driver: @@ -52,7 +52,7 @@ #include #include -#define S2255_VERSION "1.23.1" +#define S2255_VERSION "1.24.1" #define FIRMWARE_FILE_NAME "f2255usb.bin" /* default JPEG quality */ @@ -178,11 +178,6 @@ struct s2255_bufferi { DEF_FDEC, DEF_BRIGHT, DEF_CONTRAST, DEF_SATURATION, \ DEF_HUE, 0, DEF_USB_BLOCK, 0} -struct s2255_dmaqueue { - struct list_head active; - struct s2255_dev *dev; -}; - /* for firmware loading, fw_state */ #define S2255_FW_NOTLOADED 0 #define S2255_FW_LOADED_DSPWAIT 1 @@ -223,7 +218,7 @@ struct s2255_channel { struct v4l2_ctrl_handler hdl; struct v4l2_ctrl *jpegqual_ctrl; int resources; - struct s2255_dmaqueue vidq; + struct list_head buf_list; struct s2255_bufferi buffer; struct s2255_mode mode; v4l2_std_id std; @@ -574,18 +569,17 @@ static void s2255_fwchunk_complete(struct urb *urb) static int s2255_got_frame(struct s2255_channel *channel, int jpgsize) { - struct s2255_dmaqueue *dma_q = &channel->vidq; struct s2255_buffer *buf; struct s2255_dev *dev = to_s2255_dev(channel->vdev.v4l2_dev); unsigned long flags = 0; int rc = 0; spin_lock_irqsave(&dev->slock, flags); - if (list_empty(&dma_q->active)) { + if (list_empty(&channel->buf_list)) { dprintk(dev, 1, "No active queue to serve\n"); rc = -1; goto unlock; } - buf = list_entry(dma_q->active.next, + buf = list_entry(channel->buf_list.next, struct s2255_buffer, vb.queue); list_del(&buf->vb.queue); v4l2_get_timestamp(&buf->vb.ts); @@ -747,10 +741,9 @@ static void buffer_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb) struct s2255_buffer *buf = container_of(vb, struct s2255_buffer, vb); struct s2255_fh *fh = vq->priv_data; struct s2255_channel *channel = fh->channel; - struct s2255_dmaqueue *vidq = &channel->vidq; dprintk(fh->dev, 1, "%s\n", __func__); buf->vb.state = VIDEOBUF_QUEUED; - list_add_tail(&buf->vb.queue, &vidq->active); + list_add_tail(&buf->vb.queue, &channel->buf_list); } static void buffer_release(struct videobuf_queue *vq, @@ -1679,11 +1672,10 @@ static int __s2255_open(struct file *file) } dprintk(dev, 1, "%s: dev=%s type=%s\n", __func__, video_device_node_name(vdev), v4l2_type_names[type]); - dprintk(dev, 2, "%s: fh=0x%08lx, dev=0x%08lx, vidq=0x%08lx\n", __func__, - (unsigned long)fh, (unsigned long)dev, - (unsigned long)&channel->vidq); + dprintk(dev, 2, "%s: fh=0x%08lx, dev=0x%08lx\n", __func__, + (unsigned long)fh, (unsigned long)dev); dprintk(dev, 4, "%s: list_empty active=%d\n", __func__, - list_empty(&channel->vidq.active)); + list_empty(&channel->buf_list)); videobuf_queue_vmalloc_init(&fh->vb_vidq, &s2255_video_qops, NULL, &dev->slock, fh->type, @@ -1876,7 +1868,7 @@ static int s2255_probe_v4l(struct s2255_dev *dev) /* register 4 video devices */ for (i = 0; i < MAX_CHANNELS; i++) { channel = &dev->channel[i]; - INIT_LIST_HEAD(&channel->vidq.active); + INIT_LIST_HEAD(&channel->buf_list); v4l2_ctrl_handler_init(&channel->hdl, 6); v4l2_ctrl_new_std(&channel->hdl, &s2255_ctrl_ops, @@ -1901,7 +1893,6 @@ static int s2255_probe_v4l(struct s2255_dev *dev) dev_err(&dev->udev->dev, "couldn't register control\n"); break; } - channel->vidq.dev = dev; /* register 4 video devices */ channel->vdev = template; channel->vdev.ctrl_handler = &channel->hdl; -- cgit v1.1 From 5e950faffc74e71be416ea3cf4e68ab3f326535c Mon Sep 17 00:00:00 2001 From: Dean Anderson Date: Tue, 4 Feb 2014 18:16:24 -0300 Subject: [media] s2255drv: refactoring s2255_channel to s2255_vc Renaming s2255_channel and all instances of channel to vc (video channel). Signed-off-by: Dean Anderson Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/s2255/s2255drv.c | 517 +++++++++++++++++++------------------ 1 file changed, 259 insertions(+), 258 deletions(-) diff --git a/drivers/media/usb/s2255/s2255drv.c b/drivers/media/usb/s2255/s2255drv.c index 5f09a56..2e24aee 100644 --- a/drivers/media/usb/s2255/s2255drv.c +++ b/drivers/media/usb/s2255/s2255drv.c @@ -212,7 +212,8 @@ struct s2255_pipeinfo { struct s2255_fmt; /*forward declaration */ struct s2255_dev; -struct s2255_channel { +/* 2255 video channel */ +struct s2255_vc { struct s2255_dev *dev; struct video_device vdev; struct v4l2_ctrl_handler hdl; @@ -254,7 +255,7 @@ struct s2255_channel { struct s2255_dev { - struct s2255_channel channel[MAX_CHANNELS]; + struct s2255_vc vc[MAX_CHANNELS]; struct v4l2_device v4l2_dev; atomic_t num_channels; int frames; @@ -298,7 +299,7 @@ struct s2255_fh { struct s2255_dev *dev; struct videobuf_queue vb_vidq; enum v4l2_buf_type type; - struct s2255_channel *channel; + struct s2255_vc *vc; int resources; }; @@ -351,11 +352,11 @@ static int debug; static int s2255_start_readpipe(struct s2255_dev *dev); static void s2255_stop_readpipe(struct s2255_dev *dev); -static int s2255_start_acquire(struct s2255_channel *channel); -static int s2255_stop_acquire(struct s2255_channel *channel); -static void s2255_fillbuff(struct s2255_channel *chn, struct s2255_buffer *buf, +static int s2255_start_acquire(struct s2255_vc *vc); +static int s2255_stop_acquire(struct s2255_vc *vc); +static void s2255_fillbuff(struct s2255_vc *vc, struct s2255_buffer *buf, int jpgsize); -static int s2255_set_mode(struct s2255_channel *chan, struct s2255_mode *mode); +static int s2255_set_mode(struct s2255_vc *vc, struct s2255_mode *mode); static int s2255_board_shutdown(struct s2255_dev *dev); static void s2255_fwload_start(struct s2255_dev *dev, int reset); static void s2255_destroy(struct s2255_dev *dev); @@ -434,27 +435,27 @@ static const struct s2255_fmt formats[] = { } }; -static int norm_maxw(struct s2255_channel *channel) +static int norm_maxw(struct s2255_vc *vc) { - return (channel->std & V4L2_STD_525_60) ? + return (vc->std & V4L2_STD_525_60) ? LINE_SZ_4CIFS_NTSC : LINE_SZ_4CIFS_PAL; } -static int norm_maxh(struct s2255_channel *channel) +static int norm_maxh(struct s2255_vc *vc) { - return (channel->std & V4L2_STD_525_60) ? + return (vc->std & V4L2_STD_525_60) ? (NUM_LINES_1CIFS_NTSC * 2) : (NUM_LINES_1CIFS_PAL * 2); } -static int norm_minw(struct s2255_channel *channel) +static int norm_minw(struct s2255_vc *vc) { - return (channel->std & V4L2_STD_525_60) ? + return (vc->std & V4L2_STD_525_60) ? LINE_SZ_1CIFS_NTSC : LINE_SZ_1CIFS_PAL; } -static int norm_minh(struct s2255_channel *channel) +static int norm_minh(struct s2255_vc *vc) { - return (channel->std & V4L2_STD_525_60) ? + return (vc->std & V4L2_STD_525_60) ? (NUM_LINES_1CIFS_NTSC) : (NUM_LINES_1CIFS_PAL); } @@ -567,23 +568,23 @@ static void s2255_fwchunk_complete(struct urb *urb) } -static int s2255_got_frame(struct s2255_channel *channel, int jpgsize) +static int s2255_got_frame(struct s2255_vc *vc, int jpgsize) { struct s2255_buffer *buf; - struct s2255_dev *dev = to_s2255_dev(channel->vdev.v4l2_dev); + struct s2255_dev *dev = to_s2255_dev(vc->vdev.v4l2_dev); unsigned long flags = 0; int rc = 0; spin_lock_irqsave(&dev->slock, flags); - if (list_empty(&channel->buf_list)) { + if (list_empty(&vc->buf_list)) { dprintk(dev, 1, "No active queue to serve\n"); rc = -1; goto unlock; } - buf = list_entry(channel->buf_list.next, + buf = list_entry(vc->buf_list.next, struct s2255_buffer, vb.queue); list_del(&buf->vb.queue); v4l2_get_timestamp(&buf->vb.ts); - s2255_fillbuff(channel, buf, jpgsize); + s2255_fillbuff(vc, buf, jpgsize); wake_up(&buf->vb.done); dprintk(dev, 2, "%s: [buf/i] [%p/%d]\n", __func__, buf, buf->vb.i); unlock: @@ -614,21 +615,21 @@ static const struct s2255_fmt *format_by_fourcc(int fourcc) * http://v4l.videotechnology.com/ * */ -static void s2255_fillbuff(struct s2255_channel *channel, +static void s2255_fillbuff(struct s2255_vc *vc, struct s2255_buffer *buf, int jpgsize) { int pos = 0; const char *tmpbuf; char *vbuf = videobuf_to_vmalloc(&buf->vb); unsigned long last_frame; - struct s2255_dev *dev = channel->dev; + struct s2255_dev *dev = vc->dev; if (!vbuf) return; - last_frame = channel->last_frame; + last_frame = vc->last_frame; if (last_frame != -1) { tmpbuf = - (const char *)channel->buffer.frame[last_frame].lpvbits; + (const char *)vc->buffer.frame[last_frame].lpvbits; switch (buf->fmt->fourcc) { case V4L2_PIX_FMT_YUYV: case V4L2_PIX_FMT_UYVY: @@ -652,7 +653,7 @@ static void s2255_fillbuff(struct s2255_channel *channel, default: pr_info("s2255: unknown format?\n"); } - channel->last_frame = -1; + vc->last_frame = -1; } else { pr_err("s2255: =======no frame\n"); return; @@ -660,7 +661,7 @@ static void s2255_fillbuff(struct s2255_channel *channel, dprintk(dev, 2, "s2255fill at : Buffer 0x%08lx size= %d\n", (unsigned long)vbuf, pos); /* tell v4l buffer was filled */ - buf->vb.field_count = channel->frame_count * 2; + buf->vb.field_count = vc->frame_count * 2; v4l2_get_timestamp(&buf->vb.ts); buf->vb.state = VIDEOBUF_DONE; } @@ -674,8 +675,8 @@ static int buffer_setup(struct videobuf_queue *vq, unsigned int *count, unsigned int *size) { struct s2255_fh *fh = vq->priv_data; - struct s2255_channel *channel = fh->channel; - *size = channel->width * channel->height * (channel->fmt->depth >> 3); + struct s2255_vc *vc = fh->vc; + *size = vc->width * vc->height * (vc->fmt->depth >> 3); if (0 == *count) *count = S2255_DEF_BUFS; @@ -696,29 +697,29 @@ static int buffer_prepare(struct videobuf_queue *vq, struct videobuf_buffer *vb, enum v4l2_field field) { struct s2255_fh *fh = vq->priv_data; - struct s2255_channel *channel = fh->channel; + struct s2255_vc *vc = fh->vc; struct s2255_buffer *buf = container_of(vb, struct s2255_buffer, vb); int rc; - int w = channel->width; - int h = channel->height; + int w = vc->width; + int h = vc->height; dprintk(fh->dev, 4, "%s, field=%d\n", __func__, field); - if (channel->fmt == NULL) + if (vc->fmt == NULL) return -EINVAL; - if ((w < norm_minw(channel)) || - (w > norm_maxw(channel)) || - (h < norm_minh(channel)) || - (h > norm_maxh(channel))) { + if ((w < norm_minw(vc)) || + (w > norm_maxw(vc)) || + (h < norm_minh(vc)) || + (h > norm_maxh(vc))) { dprintk(fh->dev, 4, "invalid buffer prepare\n"); return -EINVAL; } - buf->vb.size = w * h * (channel->fmt->depth >> 3); + buf->vb.size = w * h * (vc->fmt->depth >> 3); if (0 != buf->vb.baddr && buf->vb.bsize < buf->vb.size) { dprintk(fh->dev, 4, "invalid buffer prepare\n"); return -EINVAL; } - buf->fmt = channel->fmt; + buf->fmt = vc->fmt; buf->vb.width = w; buf->vb.height = h; buf->vb.field = field; @@ -740,10 +741,10 @@ static void buffer_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb) { struct s2255_buffer *buf = container_of(vb, struct s2255_buffer, vb); struct s2255_fh *fh = vq->priv_data; - struct s2255_channel *channel = fh->channel; + struct s2255_vc *vc = fh->vc; dprintk(fh->dev, 1, "%s\n", __func__); buf->vb.state = VIDEOBUF_QUEUED; - list_add_tail(&buf->vb.queue, &channel->buf_list); + list_add_tail(&buf->vb.queue, &vc->buf_list); } static void buffer_release(struct videobuf_queue *vq, @@ -751,7 +752,7 @@ static void buffer_release(struct videobuf_queue *vq, { struct s2255_buffer *buf = container_of(vb, struct s2255_buffer, vb); struct s2255_fh *fh = vq->priv_data; - dprintk(fh->dev, 4, "%s %d\n", __func__, fh->channel->idx); + dprintk(fh->dev, 4, "%s %d\n", __func__, fh->vc->idx); free_buffer(vq, buf); } @@ -765,12 +766,12 @@ static struct videobuf_queue_ops s2255_video_qops = { static int res_get(struct s2255_fh *fh) { - struct s2255_channel *channel = fh->channel; + struct s2255_vc *vc = fh->vc; /* is it free? */ - if (channel->resources) + if (vc->resources) return 0; /* no, someone else uses it */ /* it's free, grab it */ - channel->resources = 1; + vc->resources = 1; fh->resources = 1; dprintk(fh->dev, 1, "s2255: res: get\n"); return 1; @@ -778,7 +779,7 @@ static int res_get(struct s2255_fh *fh) static int res_locked(struct s2255_fh *fh) { - return fh->channel->resources; + return fh->vc->resources; } static int res_check(struct s2255_fh *fh) @@ -789,8 +790,8 @@ static int res_check(struct s2255_fh *fh) static void res_free(struct s2255_fh *fh) { - struct s2255_channel *channel = fh->channel; - channel->resources = 0; + struct s2255_vc *vc = fh->vc; + vc->resources = 0; fh->resources = 0; } @@ -827,18 +828,18 @@ static int vidioc_g_fmt_vid_cap(struct file *file, void *priv, struct v4l2_format *f) { struct s2255_fh *fh = priv; - struct s2255_channel *channel = fh->channel; - int is_ntsc = channel->std & V4L2_STD_525_60; + struct s2255_vc *vc = fh->vc; + int is_ntsc = vc->std & V4L2_STD_525_60; - f->fmt.pix.width = channel->width; - f->fmt.pix.height = channel->height; + f->fmt.pix.width = vc->width; + f->fmt.pix.height = vc->height; if (f->fmt.pix.height >= (is_ntsc ? NUM_LINES_1CIFS_NTSC : NUM_LINES_1CIFS_PAL) * 2) f->fmt.pix.field = V4L2_FIELD_INTERLACED; else f->fmt.pix.field = V4L2_FIELD_TOP; - f->fmt.pix.pixelformat = channel->fmt->fourcc; - f->fmt.pix.bytesperline = f->fmt.pix.width * (channel->fmt->depth >> 3); + f->fmt.pix.pixelformat = vc->fmt->fourcc; + f->fmt.pix.bytesperline = f->fmt.pix.width * (vc->fmt->depth >> 3); f->fmt.pix.sizeimage = f->fmt.pix.height * f->fmt.pix.bytesperline; f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M; f->fmt.pix.priv = 0; @@ -851,8 +852,8 @@ static int vidioc_try_fmt_vid_cap(struct file *file, void *priv, const struct s2255_fmt *fmt; enum v4l2_field field; struct s2255_fh *fh = priv; - struct s2255_channel *channel = fh->channel; - int is_ntsc = channel->std & V4L2_STD_525_60; + struct s2255_vc *vc = fh->vc; + int is_ntsc = vc->std & V4L2_STD_525_60; fmt = format_by_fourcc(f->fmt.pix.pixelformat); @@ -912,7 +913,7 @@ static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, struct v4l2_format *f) { struct s2255_fh *fh = priv; - struct s2255_channel *channel = fh->channel; + struct s2255_vc *vc = fh->vc; const struct s2255_fmt *fmt; struct videobuf_queue *q = &fh->vb_vidq; struct s2255_mode mode; @@ -941,15 +942,15 @@ static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, ret = -EBUSY; goto out_s_fmt; } - mode = channel->mode; - channel->fmt = fmt; - channel->width = f->fmt.pix.width; - channel->height = f->fmt.pix.height; + mode = vc->mode; + vc->fmt = fmt; + vc->width = f->fmt.pix.width; + vc->height = f->fmt.pix.height; fh->vb_vidq.field = f->fmt.pix.field; fh->type = f->type; - if (channel->width > norm_minw(channel)) { - if (channel->height > norm_minh(channel)) { - if (channel->cap_parm.capturemode & + if (vc->width > norm_minw(vc)) { + if (vc->height > norm_minh(vc)) { + if (vc->cap_parm.capturemode & V4L2_MODE_HIGHQUALITY) mode.scale = SCALE_4CIFSI; else @@ -961,7 +962,7 @@ static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, mode.scale = SCALE_1CIFS; } /* color mode */ - switch (channel->fmt->fourcc) { + switch (vc->fmt->fourcc) { case V4L2_PIX_FMT_GREY: mode.color &= ~MASK_COLOR; mode.color |= COLOR_Y8; @@ -970,7 +971,7 @@ static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, case V4L2_PIX_FMT_MJPEG: mode.color &= ~MASK_COLOR; mode.color |= COLOR_JPG; - mode.color |= (channel->jpegqual << 8); + mode.color |= (vc->jpegqual << 8); break; case V4L2_PIX_FMT_YUV422P: mode.color &= ~MASK_COLOR; @@ -983,14 +984,14 @@ static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, mode.color |= COLOR_YUVPK; break; } - if ((mode.color & MASK_COLOR) != (channel->mode.color & MASK_COLOR)) + if ((mode.color & MASK_COLOR) != (vc->mode.color & MASK_COLOR)) mode.restart = 1; - else if (mode.scale != channel->mode.scale) + else if (mode.scale != vc->mode.scale) mode.restart = 1; - else if (mode.format != channel->mode.format) + else if (mode.format != vc->mode.format) mode.restart = 1; - channel->mode = mode; - (void) s2255_set_mode(channel, &mode); + vc->mode = mode; + (void) s2255_set_mode(vc, &mode); ret = 0; out_s_fmt: mutex_unlock(&q->vb_lock); @@ -1126,28 +1127,28 @@ static void s2255_print_cfg(struct s2255_dev *sdev, struct s2255_mode *mode) * When the restart parameter is set, we sleep for ONE frame to allow the * DSP time to get the new frame */ -static int s2255_set_mode(struct s2255_channel *channel, +static int s2255_set_mode(struct s2255_vc *vc, struct s2255_mode *mode) { int res; __le32 *buffer; unsigned long chn_rev; - struct s2255_dev *dev = to_s2255_dev(channel->vdev.v4l2_dev); + struct s2255_dev *dev = to_s2255_dev(vc->vdev.v4l2_dev); int i; - chn_rev = G_chnmap[channel->idx]; - dprintk(dev, 3, "%s channel: %d\n", __func__, channel->idx); + chn_rev = G_chnmap[vc->idx]; + dprintk(dev, 3, "%s channel: %d\n", __func__, vc->idx); /* if JPEG, set the quality */ if ((mode->color & MASK_COLOR) == COLOR_JPG) { mode->color &= ~MASK_COLOR; mode->color |= COLOR_JPG; mode->color &= ~MASK_JPG_QUALITY; - mode->color |= (channel->jpegqual << 8); + mode->color |= (vc->jpegqual << 8); } /* save the mode */ - channel->mode = *mode; - channel->req_image_size = get_transfer_size(mode); - dprintk(dev, 1, "%s: reqsize %ld\n", __func__, channel->req_image_size); + vc->mode = *mode; + vc->req_image_size = get_transfer_size(mode); + dprintk(dev, 1, "%s: reqsize %ld\n", __func__, vc->req_image_size); buffer = kzalloc(512, GFP_KERNEL); if (buffer == NULL) { dev_err(&dev->udev->dev, "out of mem\n"); @@ -1158,36 +1159,36 @@ static int s2255_set_mode(struct s2255_channel *channel, buffer[1] = (__le32) cpu_to_le32(chn_rev); buffer[2] = CMD_SET_MODE; for (i = 0; i < sizeof(struct s2255_mode) / sizeof(u32); i++) - buffer[3 + i] = cpu_to_le32(((u32 *)&channel->mode)[i]); - channel->setmode_ready = 0; + buffer[3 + i] = cpu_to_le32(((u32 *)&vc->mode)[i]); + vc->setmode_ready = 0; res = s2255_write_config(dev->udev, (unsigned char *)buffer, 512); if (debug) s2255_print_cfg(dev, mode); kfree(buffer); /* wait at least 3 frames before continuing */ if (mode->restart) { - wait_event_timeout(channel->wait_setmode, - (channel->setmode_ready != 0), + wait_event_timeout(vc->wait_setmode, + (vc->setmode_ready != 0), msecs_to_jiffies(S2255_SETMODE_TIMEOUT)); - if (channel->setmode_ready != 1) { + if (vc->setmode_ready != 1) { dprintk(dev, 0, "s2255: no set mode response\n"); res = -EFAULT; } } /* clear the restart flag */ - channel->mode.restart = 0; - dprintk(dev, 1, "%s chn %d, result: %d\n", __func__, channel->idx, res); + vc->mode.restart = 0; + dprintk(dev, 1, "%s chn %d, result: %d\n", __func__, vc->idx, res); return res; } -static int s2255_cmd_status(struct s2255_channel *channel, u32 *pstatus) +static int s2255_cmd_status(struct s2255_vc *vc, u32 *pstatus) { int res; __le32 *buffer; u32 chn_rev; - struct s2255_dev *dev = to_s2255_dev(channel->vdev.v4l2_dev); - chn_rev = G_chnmap[channel->idx]; - dprintk(dev, 4, "%s chan %d\n", __func__, channel->idx); + struct s2255_dev *dev = to_s2255_dev(vc->vdev.v4l2_dev); + chn_rev = G_chnmap[vc->idx]; + dprintk(dev, 4, "%s chan %d\n", __func__, vc->idx); buffer = kzalloc(512, GFP_KERNEL); if (buffer == NULL) { dev_err(&dev->udev->dev, "out of mem\n"); @@ -1198,17 +1199,17 @@ static int s2255_cmd_status(struct s2255_channel *channel, u32 *pstatus) buffer[1] = (__le32) cpu_to_le32(chn_rev); buffer[2] = CMD_STATUS; *pstatus = 0; - channel->vidstatus_ready = 0; + vc->vidstatus_ready = 0; res = s2255_write_config(dev->udev, (unsigned char *)buffer, 512); kfree(buffer); - wait_event_timeout(channel->wait_vidstatus, - (channel->vidstatus_ready != 0), + wait_event_timeout(vc->wait_vidstatus, + (vc->vidstatus_ready != 0), msecs_to_jiffies(S2255_VIDSTATUS_TIMEOUT)); - if (channel->vidstatus_ready != 1) { + if (vc->vidstatus_ready != 1) { dprintk(dev, 0, "s2255: no vidstatus response\n"); res = -EFAULT; } - *pstatus = channel->vidstatus; + *pstatus = vc->vidstatus; dprintk(dev, 4, "%s, vid status %d\n", __func__, *pstatus); return res; } @@ -1218,7 +1219,7 @@ static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i) int res; struct s2255_fh *fh = priv; struct s2255_dev *dev = fh->dev; - struct s2255_channel *channel = fh->channel; + struct s2255_vc *vc = fh->vc; int j; dprintk(dev, 4, "%s\n", __func__); if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) { @@ -1234,18 +1235,18 @@ static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i) s2255_dev_err(&dev->udev->dev, "stream busy\n"); return -EBUSY; } - channel->last_frame = -1; - channel->bad_payload = 0; - channel->cur_frame = 0; - channel->frame_count = 0; + vc->last_frame = -1; + vc->bad_payload = 0; + vc->cur_frame = 0; + vc->frame_count = 0; for (j = 0; j < SYS_FRAMES; j++) { - channel->buffer.frame[j].ulState = S2255_READ_IDLE; - channel->buffer.frame[j].cur_size = 0; + vc->buffer.frame[j].ulState = S2255_READ_IDLE; + vc->buffer.frame[j].cur_size = 0; } res = videobuf_streamon(&fh->vb_vidq); if (res == 0) { - s2255_start_acquire(channel); - channel->b_acquire = 1; + s2255_start_acquire(vc); + vc->b_acquire = 1; } else res_free(fh); @@ -1255,14 +1256,14 @@ static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i) static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i) { struct s2255_fh *fh = priv; - dprintk(fh->dev, 4, "%s\n, channel: %d", __func__, fh->channel->idx); + dprintk(fh->dev, 4, "%s\n, channel: %d", __func__, fh->vc->idx); if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) { dprintk(fh->dev, 1, "invalid fh type0\n"); return -EINVAL; } if (i != fh->type) return -EINVAL; - s2255_stop_acquire(fh->channel); + s2255_stop_acquire(fh->vc); videobuf_streamoff(&fh->vb_vidq); res_free(fh); return 0; @@ -1273,7 +1274,7 @@ static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id i) struct s2255_fh *fh = priv; struct s2255_mode mode; struct videobuf_queue *q = &fh->vb_vidq; - struct s2255_channel *channel = fh->channel; + struct s2255_vc *vc = fh->vc; int ret = 0; mutex_lock(&q->vb_lock); @@ -1282,7 +1283,7 @@ static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id i) ret = -EBUSY; goto out_s_std; } - mode = fh->channel->mode; + mode = fh->vc->mode; if (i & V4L2_STD_525_60) { dprintk(fh->dev, 4, "%s 60 Hz\n", __func__); /* if changing format, reset frame decimation/intervals */ @@ -1290,8 +1291,8 @@ static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id i) mode.restart = 1; mode.format = FORMAT_NTSC; mode.fdec = FDEC_1; - channel->width = LINE_SZ_4CIFS_NTSC; - channel->height = NUM_LINES_4CIFS_NTSC * 2; + vc->width = LINE_SZ_4CIFS_NTSC; + vc->height = NUM_LINES_4CIFS_NTSC * 2; } } else if (i & V4L2_STD_625_50) { dprintk(fh->dev, 4, "%s 50 Hz\n", __func__); @@ -1299,16 +1300,16 @@ static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id i) mode.restart = 1; mode.format = FORMAT_PAL; mode.fdec = FDEC_1; - channel->width = LINE_SZ_4CIFS_PAL; - channel->height = NUM_LINES_4CIFS_PAL * 2; + vc->width = LINE_SZ_4CIFS_PAL; + vc->height = NUM_LINES_4CIFS_PAL * 2; } } else { ret = -EINVAL; goto out_s_std; } - fh->channel->std = i; + fh->vc->std = i; if (mode.restart) - s2255_set_mode(fh->channel, &mode); + s2255_set_mode(fh->vc, &mode); out_s_std: mutex_unlock(&q->vb_lock); return ret; @@ -1318,7 +1319,7 @@ static int vidioc_g_std(struct file *file, void *priv, v4l2_std_id *i) { struct s2255_fh *fh = priv; - *i = fh->channel->std; + *i = fh->vc->std; return 0; } @@ -1334,7 +1335,7 @@ static int vidioc_enum_input(struct file *file, void *priv, { struct s2255_fh *fh = priv; struct s2255_dev *dev = fh->dev; - struct s2255_channel *channel = fh->channel; + struct s2255_vc *vc = fh->vc; u32 status = 0; if (inp->index != 0) return -EINVAL; @@ -1343,7 +1344,7 @@ static int vidioc_enum_input(struct file *file, void *priv, inp->status = 0; if (dev->dsp_fw_ver >= S2255_MIN_DSP_STATUS) { int rc; - rc = s2255_cmd_status(fh->channel, &status); + rc = s2255_cmd_status(fh->vc, &status); dprintk(dev, 4, "s2255_cmd_status rc: %d status %x\n", rc, status); if (rc == 0) @@ -1356,7 +1357,7 @@ static int vidioc_enum_input(struct file *file, void *priv, strlcpy(inp->name, "Composite", sizeof(inp->name)); break; case 0x2257: - strlcpy(inp->name, (channel->idx < 2) ? "Composite" : "S-Video", + strlcpy(inp->name, (vc->idx < 2) ? "Composite" : "S-Video", sizeof(inp->name)); break; } @@ -1377,10 +1378,10 @@ static int vidioc_s_input(struct file *file, void *priv, unsigned int i) static int s2255_s_ctrl(struct v4l2_ctrl *ctrl) { - struct s2255_channel *channel = - container_of(ctrl->handler, struct s2255_channel, hdl); + struct s2255_vc *vc = + container_of(ctrl->handler, struct s2255_vc, hdl); struct s2255_mode mode; - mode = channel->mode; + mode = vc->mode; /* update the mode to the corresponding value */ switch (ctrl->id) { case V4L2_CID_BRIGHTNESS: @@ -1400,7 +1401,7 @@ static int s2255_s_ctrl(struct v4l2_ctrl *ctrl) mode.color |= !ctrl->val << 16; break; case V4L2_CID_JPEG_COMPRESSION_QUALITY: - channel->jpegqual = ctrl->val; + vc->jpegqual = ctrl->val; return 0; default: return -EINVAL; @@ -1410,7 +1411,7 @@ static int s2255_s_ctrl(struct v4l2_ctrl *ctrl) some V4L programs restart stream unnecessarily after a s_crtl. */ - s2255_set_mode(channel, &mode); + s2255_set_mode(vc, &mode); return 0; } @@ -1418,10 +1419,10 @@ static int vidioc_g_jpegcomp(struct file *file, void *priv, struct v4l2_jpegcompression *jc) { struct s2255_fh *fh = priv; - struct s2255_channel *channel = fh->channel; + struct s2255_vc *vc = fh->vc; memset(jc, 0, sizeof(*jc)); - jc->quality = channel->jpegqual; + jc->quality = vc->jpegqual; dprintk(fh->dev, 2, "%s: quality %d\n", __func__, jc->quality); return 0; } @@ -1430,10 +1431,10 @@ static int vidioc_s_jpegcomp(struct file *file, void *priv, const struct v4l2_jpegcompression *jc) { struct s2255_fh *fh = priv; - struct s2255_channel *channel = fh->channel; + struct s2255_vc *vc = fh->vc; if (jc->quality < 0 || jc->quality > 100) return -EINVAL; - v4l2_ctrl_s_ctrl(channel->jpegqual_ctrl, jc->quality); + v4l2_ctrl_s_ctrl(vc->jpegqual_ctrl, jc->quality); dprintk(fh->dev, 2, "%s: quality %d\n", __func__, jc->quality); return 0; } @@ -1443,15 +1444,15 @@ static int vidioc_g_parm(struct file *file, void *priv, { struct s2255_fh *fh = priv; __u32 def_num, def_dem; - struct s2255_channel *channel = fh->channel; + struct s2255_vc *vc = fh->vc; if (sp->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) return -EINVAL; sp->parm.capture.capability = V4L2_CAP_TIMEPERFRAME; - sp->parm.capture.capturemode = channel->cap_parm.capturemode; - def_num = (channel->mode.format == FORMAT_NTSC) ? 1001 : 1000; - def_dem = (channel->mode.format == FORMAT_NTSC) ? 30000 : 25000; + sp->parm.capture.capturemode = vc->cap_parm.capturemode; + def_num = (vc->mode.format == FORMAT_NTSC) ? 1001 : 1000; + def_dem = (vc->mode.format == FORMAT_NTSC) ? 30000 : 25000; sp->parm.capture.timeperframe.denominator = def_dem; - switch (channel->mode.fdec) { + switch (vc->mode.fdec) { default: case FDEC_1: sp->parm.capture.timeperframe.numerator = def_num; @@ -1478,15 +1479,15 @@ static int vidioc_s_parm(struct file *file, void *priv, struct v4l2_streamparm *sp) { struct s2255_fh *fh = priv; - struct s2255_channel *channel = fh->channel; + struct s2255_vc *vc = fh->vc; struct s2255_mode mode; int fdec = FDEC_1; __u32 def_num, def_dem; if (sp->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) return -EINVAL; - mode = channel->mode; + mode = vc->mode; /* high quality capture mode requires a stream restart */ - if (channel->cap_parm.capturemode + if (vc->cap_parm.capturemode != sp->parm.capture.capturemode && res_locked(fh)) return -EBUSY; def_num = (mode.format == FORMAT_NTSC) ? 1001 : 1000; @@ -1507,7 +1508,7 @@ static int vidioc_s_parm(struct file *file, void *priv, } mode.fdec = fdec; sp->parm.capture.timeperframe.denominator = def_dem; - s2255_set_mode(channel, &mode); + s2255_set_mode(vc, &mode); dprintk(fh->dev, 4, "%s capture mode, %d timeperframe %d/%d, fdec %d\n", __func__, sp->parm.capture.capturemode, @@ -1532,8 +1533,8 @@ static int vidioc_enum_framesizes(struct file *file, void *priv, struct v4l2_frmsizeenum *fe) { struct s2255_fh *fh = priv; - struct s2255_channel *channel = fh->channel; - int is_ntsc = channel->std & V4L2_STD_525_60; + struct s2255_vc *vc = fh->vc; + int is_ntsc = vc->std & V4L2_STD_525_60; const struct s2255_fmt *fmt; if (fe->index >= NUM_SIZE_ENUMS) @@ -1551,10 +1552,10 @@ static int vidioc_enum_frameintervals(struct file *file, void *priv, struct v4l2_frmivalenum *fe) { struct s2255_fh *fh = priv; - struct s2255_channel *channel = fh->channel; + struct s2255_vc *vc = fh->vc; const struct s2255_fmt *fmt; const struct v4l2_frmsize_discrete *sizes; - int is_ntsc = channel->std & V4L2_STD_525_60; + int is_ntsc = vc->std & V4L2_STD_525_60; #define NUM_FRAME_ENUMS 4 int frm_dec[NUM_FRAME_ENUMS] = {1, 2, 3, 5}; int i; @@ -1586,7 +1587,7 @@ static int vidioc_enum_frameintervals(struct file *file, void *priv, static int __s2255_open(struct file *file) { struct video_device *vdev = video_devdata(file); - struct s2255_channel *channel = video_drvdata(file); + struct s2255_vc *vc = video_drvdata(file); struct s2255_dev *dev = to_s2255_dev(vdev->v4l2_dev); struct s2255_fh *fh; enum v4l2_buf_type type = V4L2_BUF_TYPE_VIDEO_CAPTURE; @@ -1663,19 +1664,19 @@ static int __s2255_open(struct file *file) file->private_data = &fh->fh; fh->dev = dev; fh->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; - fh->channel = channel; - if (!channel->configured) { + fh->vc = vc; + if (!vc->configured) { /* configure channel to default state */ - channel->fmt = &formats[0]; - s2255_set_mode(channel, &channel->mode); - channel->configured = 1; + vc->fmt = &formats[0]; + s2255_set_mode(vc, &vc->mode); + vc->configured = 1; } dprintk(dev, 1, "%s: dev=%s type=%s\n", __func__, video_device_node_name(vdev), v4l2_type_names[type]); dprintk(dev, 2, "%s: fh=0x%08lx, dev=0x%08lx\n", __func__, (unsigned long)fh, (unsigned long)dev); dprintk(dev, 4, "%s: list_empty active=%d\n", __func__, - list_empty(&channel->buf_list)); + list_empty(&vc->buf_list)); videobuf_queue_vmalloc_init(&fh->vb_vidq, &s2255_video_qops, NULL, &dev->slock, fh->type, @@ -1741,14 +1742,14 @@ static int s2255_release(struct file *file) struct s2255_fh *fh = file->private_data; struct s2255_dev *dev = fh->dev; struct video_device *vdev = video_devdata(file); - struct s2255_channel *channel = fh->channel; + struct s2255_vc *vc = fh->vc; if (!dev) return -ENODEV; mutex_lock(&dev->lock); /* turn off stream */ if (res_check(fh)) { - if (channel->b_acquire) - s2255_stop_acquire(fh->channel); + if (vc->b_acquire) + s2255_stop_acquire(fh->vc); videobuf_streamoff(&fh->vb_vidq); res_free(fh); } @@ -1820,13 +1821,13 @@ static const struct v4l2_ioctl_ops s2255_ioctl_ops = { static void s2255_video_device_release(struct video_device *vdev) { struct s2255_dev *dev = to_s2255_dev(vdev->v4l2_dev); - struct s2255_channel *channel = - container_of(vdev, struct s2255_channel, vdev); + struct s2255_vc *vc = + container_of(vdev, struct s2255_vc, vdev); dprintk(dev, 4, "%s, chnls: %d\n", __func__, atomic_read(&dev->num_channels)); - v4l2_ctrl_handler_free(&channel->hdl); + v4l2_ctrl_handler_free(&vc->hdl); if (atomic_dec_and_test(&dev->num_channels)) s2255_destroy(dev); @@ -1860,52 +1861,52 @@ static int s2255_probe_v4l(struct s2255_dev *dev) int ret; int i; int cur_nr = video_nr; - struct s2255_channel *channel; + struct s2255_vc *vc; ret = v4l2_device_register(&dev->interface->dev, &dev->v4l2_dev); if (ret) return ret; /* initialize all video 4 linux */ /* register 4 video devices */ for (i = 0; i < MAX_CHANNELS; i++) { - channel = &dev->channel[i]; - INIT_LIST_HEAD(&channel->buf_list); + vc = &dev->vc[i]; + INIT_LIST_HEAD(&vc->buf_list); - v4l2_ctrl_handler_init(&channel->hdl, 6); - v4l2_ctrl_new_std(&channel->hdl, &s2255_ctrl_ops, + v4l2_ctrl_handler_init(&vc->hdl, 6); + v4l2_ctrl_new_std(&vc->hdl, &s2255_ctrl_ops, V4L2_CID_BRIGHTNESS, -127, 127, 1, DEF_BRIGHT); - v4l2_ctrl_new_std(&channel->hdl, &s2255_ctrl_ops, + v4l2_ctrl_new_std(&vc->hdl, &s2255_ctrl_ops, V4L2_CID_CONTRAST, 0, 255, 1, DEF_CONTRAST); - v4l2_ctrl_new_std(&channel->hdl, &s2255_ctrl_ops, + v4l2_ctrl_new_std(&vc->hdl, &s2255_ctrl_ops, V4L2_CID_SATURATION, 0, 255, 1, DEF_SATURATION); - v4l2_ctrl_new_std(&channel->hdl, &s2255_ctrl_ops, + v4l2_ctrl_new_std(&vc->hdl, &s2255_ctrl_ops, V4L2_CID_HUE, 0, 255, 1, DEF_HUE); - channel->jpegqual_ctrl = v4l2_ctrl_new_std(&channel->hdl, + vc->jpegqual_ctrl = v4l2_ctrl_new_std(&vc->hdl, &s2255_ctrl_ops, V4L2_CID_JPEG_COMPRESSION_QUALITY, 0, 100, 1, S2255_DEF_JPEG_QUAL); if (dev->dsp_fw_ver >= S2255_MIN_DSP_COLORFILTER && - (dev->pid != 0x2257 || channel->idx <= 1)) - v4l2_ctrl_new_custom(&channel->hdl, &color_filter_ctrl, + (dev->pid != 0x2257 || vc->idx <= 1)) + v4l2_ctrl_new_custom(&vc->hdl, &color_filter_ctrl, NULL); - if (channel->hdl.error) { - ret = channel->hdl.error; - v4l2_ctrl_handler_free(&channel->hdl); + if (vc->hdl.error) { + ret = vc->hdl.error; + v4l2_ctrl_handler_free(&vc->hdl); dev_err(&dev->udev->dev, "couldn't register control\n"); break; } /* register 4 video devices */ - channel->vdev = template; - channel->vdev.ctrl_handler = &channel->hdl; - channel->vdev.lock = &dev->lock; - channel->vdev.v4l2_dev = &dev->v4l2_dev; - set_bit(V4L2_FL_USE_FH_PRIO, &channel->vdev.flags); - video_set_drvdata(&channel->vdev, channel); + vc->vdev = template; + vc->vdev.ctrl_handler = &vc->hdl; + vc->vdev.lock = &dev->lock; + vc->vdev.v4l2_dev = &dev->v4l2_dev; + set_bit(V4L2_FL_USE_FH_PRIO, &vc->vdev.flags); + video_set_drvdata(&vc->vdev, vc); if (video_nr == -1) - ret = video_register_device(&channel->vdev, + ret = video_register_device(&vc->vdev, VFL_TYPE_GRABBER, video_nr); else - ret = video_register_device(&channel->vdev, + ret = video_register_device(&vc->vdev, VFL_TYPE_GRABBER, cur_nr + i); @@ -1916,7 +1917,7 @@ static int s2255_probe_v4l(struct s2255_dev *dev) } atomic_inc(&dev->num_channels); v4l2_info(&dev->v4l2_dev, "V4L2 device registered as %s\n", - video_device_node_name(&channel->vdev)); + video_device_node_name(&vc->vdev)); } pr_info("Sensoray 2255 V4L driver Revision: %s\n", @@ -1953,11 +1954,11 @@ static int save_frame(struct s2255_dev *dev, struct s2255_pipeinfo *pipe_info) s32 idx = -1; struct s2255_framei *frm; unsigned char *pdata; - struct s2255_channel *ch; + struct s2255_vc *vc; dprintk(dev, 100, "buffer to user\n"); - ch = &dev->channel[dev->cc]; - idx = ch->cur_frame; - frm = &ch->buffer.frame[idx]; + vc = &dev->vc[dev->cc]; + idx = vc->cur_frame; + frm = &vc->buffer.frame[idx]; if (frm->ulState == S2255_READ_IDLE) { int jj; unsigned int cc; @@ -1981,15 +1982,15 @@ static int save_frame(struct s2255_dev *dev, struct s2255_pipeinfo *pipe_info) } /* reverse it */ dev->cc = G_chnmap[cc]; - ch = &dev->channel[dev->cc]; + vc = &dev->vc[dev->cc]; payload = le32_to_cpu(pdword[3]); - if (payload > ch->req_image_size) { - ch->bad_payload++; + if (payload > vc->req_image_size) { + vc->bad_payload++; /* discard the bad frame */ return -EINVAL; } - ch->pkt_size = payload; - ch->jpg_size = le32_to_cpu(pdword[4]); + vc->pkt_size = payload; + vc->jpg_size = le32_to_cpu(pdword[4]); break; case S2255_MARKER_RESPONSE: @@ -2000,13 +2001,13 @@ static int save_frame(struct s2255_dev *dev, struct s2255_pipeinfo *pipe_info) cc = G_chnmap[le32_to_cpu(pdword[1])]; if (cc >= MAX_CHANNELS) break; - ch = &dev->channel[cc]; + vc = &dev->vc[cc]; switch (pdword[2]) { case S2255_RESPONSE_SETMODE: /* check if channel valid */ /* set mode ready */ - ch->setmode_ready = 1; - wake_up(&ch->wait_setmode); + vc->setmode_ready = 1; + wake_up(&vc->wait_setmode); dprintk(dev, 5, "setmode rdy %d\n", cc); break; case S2255_RESPONSE_FW: @@ -2020,9 +2021,9 @@ static int save_frame(struct s2255_dev *dev, struct s2255_pipeinfo *pipe_info) wake_up(&dev->fw_data->wait_fw); break; case S2255_RESPONSE_STATUS: - ch->vidstatus = le32_to_cpu(pdword[3]); - ch->vidstatus_ready = 1; - wake_up(&ch->wait_vidstatus); + vc->vidstatus = le32_to_cpu(pdword[3]); + vc->vidstatus_ready = 1; + wake_up(&vc->wait_vidstatus); dprintk(dev, 5, "vstat %x chan %d\n", le32_to_cpu(pdword[3]), cc); break; @@ -2039,11 +2040,11 @@ static int save_frame(struct s2255_dev *dev, struct s2255_pipeinfo *pipe_info) if (!bframe) return -EINVAL; } - ch = &dev->channel[dev->cc]; - idx = ch->cur_frame; - frm = &ch->buffer.frame[idx]; + vc = &dev->vc[dev->cc]; + idx = vc->cur_frame; + frm = &vc->buffer.frame[idx]; /* search done. now find out if should be acquiring on this channel */ - if (!ch->b_acquire) { + if (!vc->b_acquire) { /* we found a frame, but this channel is turned off */ frm->ulState = S2255_READ_IDLE; return -EINVAL; @@ -2068,10 +2069,10 @@ static int save_frame(struct s2255_dev *dev, struct s2255_pipeinfo *pipe_info) copy_size = (pipe_info->cur_transfer_size - offset); - size = ch->pkt_size - PREFIX_SIZE; + size = vc->pkt_size - PREFIX_SIZE; /* sanity check on pdest */ - if ((copy_size + frm->cur_size) < ch->req_image_size) + if ((copy_size + frm->cur_size) < vc->req_image_size) memcpy(pdest, psrc, copy_size); frm->cur_size += copy_size; @@ -2080,16 +2081,16 @@ static int save_frame(struct s2255_dev *dev, struct s2255_pipeinfo *pipe_info) if (frm->cur_size >= size) { dprintk(dev, 2, "******[%d]Buffer[%d]full*******\n", dev->cc, idx); - ch->last_frame = ch->cur_frame; - ch->cur_frame++; + vc->last_frame = vc->cur_frame; + vc->cur_frame++; /* end of system frame ring buffer, start at zero */ - if ((ch->cur_frame == SYS_FRAMES) || - (ch->cur_frame == ch->buffer.dwFrames)) - ch->cur_frame = 0; + if ((vc->cur_frame == SYS_FRAMES) || + (vc->cur_frame == vc->buffer.dwFrames)) + vc->cur_frame = 0; /* frame ready */ - if (ch->b_acquire) - s2255_got_frame(ch, ch->jpg_size); - ch->frame_count++; + if (vc->b_acquire) + s2255_got_frame(vc, vc->jpg_size); + vc->frame_count++; frm->ulState = S2255_READ_IDLE; frm->cur_size = 0; @@ -2162,11 +2163,11 @@ static int s2255_get_fx2fw(struct s2255_dev *dev) * Create the system ring buffer to copy frames into from the * usb read pipe. */ -static int s2255_create_sys_buffers(struct s2255_channel *channel) +static int s2255_create_sys_buffers(struct s2255_vc *vc) { unsigned long i; unsigned long reqsize; - channel->buffer.dwFrames = SYS_FRAMES; + vc->buffer.dwFrames = SYS_FRAMES; /* always allocate maximum size(PAL) for system buffers */ reqsize = SYS_FRAMES_MAXSIZE; @@ -2175,33 +2176,33 @@ static int s2255_create_sys_buffers(struct s2255_channel *channel) for (i = 0; i < SYS_FRAMES; i++) { /* allocate the frames */ - channel->buffer.frame[i].lpvbits = vmalloc(reqsize); - channel->buffer.frame[i].size = reqsize; - if (channel->buffer.frame[i].lpvbits == NULL) { + vc->buffer.frame[i].lpvbits = vmalloc(reqsize); + vc->buffer.frame[i].size = reqsize; + if (vc->buffer.frame[i].lpvbits == NULL) { pr_info("out of memory. using less frames\n"); - channel->buffer.dwFrames = i; + vc->buffer.dwFrames = i; break; } } /* make sure internal states are set */ for (i = 0; i < SYS_FRAMES; i++) { - channel->buffer.frame[i].ulState = 0; - channel->buffer.frame[i].cur_size = 0; + vc->buffer.frame[i].ulState = 0; + vc->buffer.frame[i].cur_size = 0; } - channel->cur_frame = 0; - channel->last_frame = -1; + vc->cur_frame = 0; + vc->last_frame = -1; return 0; } -static int s2255_release_sys_buffers(struct s2255_channel *channel) +static int s2255_release_sys_buffers(struct s2255_vc *vc) { unsigned long i; for (i = 0; i < SYS_FRAMES; i++) { - if (channel->buffer.frame[i].lpvbits) - vfree(channel->buffer.frame[i].lpvbits); - channel->buffer.frame[i].lpvbits = NULL; + if (vc->buffer.frame[i].lpvbits) + vfree(vc->buffer.frame[i].lpvbits); + vc->buffer.frame[i].lpvbits = NULL; } return 0; } @@ -2235,21 +2236,21 @@ static int s2255_board_init(struct s2255_dev *dev) pr_info("s2255: newer USB firmware available\n"); for (j = 0; j < MAX_CHANNELS; j++) { - struct s2255_channel *channel = &dev->channel[j]; - channel->b_acquire = 0; - channel->mode = mode_def; + struct s2255_vc *vc = &dev->vc[j]; + vc->b_acquire = 0; + vc->mode = mode_def; if (dev->pid == 0x2257 && j > 1) - channel->mode.color |= (1 << 16); - channel->jpegqual = S2255_DEF_JPEG_QUAL; - channel->width = LINE_SZ_4CIFS_NTSC; - channel->height = NUM_LINES_4CIFS_NTSC * 2; - channel->std = V4L2_STD_NTSC_M; - channel->fmt = &formats[0]; - channel->mode.restart = 1; - channel->req_image_size = get_transfer_size(&mode_def); - channel->frame_count = 0; + vc->mode.color |= (1 << 16); + vc->jpegqual = S2255_DEF_JPEG_QUAL; + vc->width = LINE_SZ_4CIFS_NTSC; + vc->height = NUM_LINES_4CIFS_NTSC * 2; + vc->std = V4L2_STD_NTSC_M; + vc->fmt = &formats[0]; + vc->mode.restart = 1; + vc->req_image_size = get_transfer_size(&mode_def); + vc->frame_count = 0; /* create the system buffers */ - s2255_create_sys_buffers(channel); + s2255_create_sys_buffers(vc); } /* start read pipe */ s2255_start_readpipe(dev); @@ -2263,12 +2264,12 @@ static int s2255_board_shutdown(struct s2255_dev *dev) dprintk(dev, 1, "%s: dev: %p", __func__, dev); for (i = 0; i < MAX_CHANNELS; i++) { - if (dev->channel[i].b_acquire) - s2255_stop_acquire(&dev->channel[i]); + if (dev->vc[i].b_acquire) + s2255_stop_acquire(&dev->vc[i]); } s2255_stop_readpipe(dev); for (i = 0; i < MAX_CHANNELS; i++) - s2255_release_sys_buffers(&dev->channel[i]); + s2255_release_sys_buffers(&dev->vc[i]); /* release transfer buffer */ kfree(dev->pipe.transfer_buffer); return 0; @@ -2357,26 +2358,26 @@ static int s2255_start_readpipe(struct s2255_dev *dev) } /* starts acquisition process */ -static int s2255_start_acquire(struct s2255_channel *channel) +static int s2255_start_acquire(struct s2255_vc *vc) { unsigned char *buffer; int res; unsigned long chn_rev; int j; - struct s2255_dev *dev = to_s2255_dev(channel->vdev.v4l2_dev); - chn_rev = G_chnmap[channel->idx]; + struct s2255_dev *dev = to_s2255_dev(vc->vdev.v4l2_dev); + chn_rev = G_chnmap[vc->idx]; buffer = kzalloc(512, GFP_KERNEL); if (buffer == NULL) { dev_err(&dev->udev->dev, "out of mem\n"); return -ENOMEM; } - channel->last_frame = -1; - channel->bad_payload = 0; - channel->cur_frame = 0; + vc->last_frame = -1; + vc->bad_payload = 0; + vc->cur_frame = 0; for (j = 0; j < SYS_FRAMES; j++) { - channel->buffer.frame[j].ulState = 0; - channel->buffer.frame[j].cur_size = 0; + vc->buffer.frame[j].ulState = 0; + vc->buffer.frame[j].cur_size = 0; } /* send the start command */ @@ -2387,18 +2388,18 @@ static int s2255_start_acquire(struct s2255_channel *channel) if (res != 0) dev_err(&dev->udev->dev, "CMD_START error\n"); - dprintk(dev, 2, "start acquire exit[%d] %d\n", channel->idx, res); + dprintk(dev, 2, "start acquire exit[%d] %d\n", vc->idx, res); kfree(buffer); return 0; } -static int s2255_stop_acquire(struct s2255_channel *channel) +static int s2255_stop_acquire(struct s2255_vc *vc) { unsigned char *buffer; int res; unsigned long chn_rev; - struct s2255_dev *dev = to_s2255_dev(channel->vdev.v4l2_dev); - chn_rev = G_chnmap[channel->idx]; + struct s2255_dev *dev = to_s2255_dev(vc->vdev.v4l2_dev); + chn_rev = G_chnmap[vc->idx]; buffer = kzalloc(512, GFP_KERNEL); if (buffer == NULL) { dev_err(&dev->udev->dev, "out of mem\n"); @@ -2412,8 +2413,8 @@ static int s2255_stop_acquire(struct s2255_channel *channel) if (res != 0) dev_err(&dev->udev->dev, "CMD_STOP error\n"); kfree(buffer); - channel->b_acquire = 0; - dprintk(dev, 4, "%s: chn %d, res %d\n", __func__, channel->idx, res); + vc->b_acquire = 0; + dprintk(dev, 4, "%s: chn %d, res %d\n", __func__, vc->idx, res); return res; } @@ -2503,11 +2504,11 @@ static int s2255_probe(struct usb_interface *interface, dev->timer.data = (unsigned long)dev->fw_data; init_waitqueue_head(&dev->fw_data->wait_fw); for (i = 0; i < MAX_CHANNELS; i++) { - struct s2255_channel *channel = &dev->channel[i]; - channel->idx = i; - channel->dev = dev; - init_waitqueue_head(&channel->wait_setmode); - init_waitqueue_head(&channel->wait_vidstatus); + struct s2255_vc *vc = &dev->vc[i]; + vc->idx = i; + vc->dev = dev; + init_waitqueue_head(&vc->wait_setmode); + init_waitqueue_head(&vc->wait_vidstatus); } dev->fw_data->fw_urb = usb_alloc_urb(0, GFP_KERNEL); @@ -2595,15 +2596,15 @@ static void s2255_disconnect(struct usb_interface *interface) atomic_inc(&dev->num_channels); /* unregister each video device. */ for (i = 0; i < channels; i++) - video_unregister_device(&dev->channel[i].vdev); + video_unregister_device(&dev->vc[i].vdev); /* wake up any of our timers */ atomic_set(&dev->fw_data->fw_state, S2255_FW_DISCONNECTING); wake_up(&dev->fw_data->wait_fw); for (i = 0; i < MAX_CHANNELS; i++) { - dev->channel[i].setmode_ready = 1; - wake_up(&dev->channel[i].wait_setmode); - dev->channel[i].vidstatus_ready = 1; - wake_up(&dev->channel[i].wait_vidstatus); + dev->vc[i].setmode_ready = 1; + wake_up(&dev->vc[i].wait_setmode); + dev->vc[i].vidstatus_ready = 1; + wake_up(&dev->vc[i].wait_vidstatus); } if (atomic_dec_and_test(&dev->num_channels)) s2255_destroy(dev); -- cgit v1.1 From 9da62eb01f7b38af3c9e75e786eed5dfdb622753 Mon Sep 17 00:00:00 2001 From: Dean Anderson Date: Wed, 5 Feb 2014 14:58:06 -0300 Subject: [media] s2255drv: buffer setup fix Buffer setup should check if minimum number of buffers is used. Signed-off-by: Dean Anderson Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/s2255/s2255drv.c | 16 ++++------------ 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/drivers/media/usb/s2255/s2255drv.c b/drivers/media/usb/s2255/s2255drv.c index 2e24aee..1b267b1 100644 --- a/drivers/media/usb/s2255/s2255drv.c +++ b/drivers/media/usb/s2255/s2255drv.c @@ -69,7 +69,7 @@ #define S2255_DSP_BOOTTIME 800 /* maximum time to wait for firmware to load (ms) */ #define S2255_LOAD_TIMEOUT (5000 + S2255_DSP_BOOTTIME) -#define S2255_DEF_BUFS 16 +#define S2255_MIN_BUFS 2 #define S2255_SETMODE_TIMEOUT 500 #define S2255_VIDSTATUS_TIMEOUT 350 #define S2255_MARKER_FRAME cpu_to_le32(0x2255DA4AL) @@ -374,9 +374,6 @@ static long s2255_vendor_req(struct s2255_dev *dev, unsigned char req, static struct usb_driver s2255_driver; -/* Declare static vars that will be used as parameters */ -static unsigned int vid_limit = 16; /* Video memory limit, in Mb */ - /* start video number */ static int video_nr = -1; /* /dev/videoN, -1 for autodetect */ @@ -385,8 +382,6 @@ static int jpeg_enable = 1; module_param(debug, int, 0644); MODULE_PARM_DESC(debug, "Debug level(0-100) default 0"); -module_param(vid_limit, int, 0644); -MODULE_PARM_DESC(vid_limit, "video memory limit(Mb)"); module_param(video_nr, int, 0644); MODULE_PARM_DESC(video_nr, "start video minor(-1 default autodetect)"); module_param(jpeg_enable, int, 0644); @@ -671,18 +666,15 @@ static void s2255_fillbuff(struct s2255_vc *vc, Videobuf operations ------------------------------------------------------------------*/ -static int buffer_setup(struct videobuf_queue *vq, unsigned int *count, +static int buffer_setup(struct videobuf_queue *vq, unsigned int *nbuffers, unsigned int *size) { struct s2255_fh *fh = vq->priv_data; struct s2255_vc *vc = fh->vc; *size = vc->width * vc->height * (vc->fmt->depth >> 3); - if (0 == *count) - *count = S2255_DEF_BUFS; - - if (*size * *count > vid_limit * 1024 * 1024) - *count = (vid_limit * 1024 * 1024) / *size; + if (*nbuffers < S2255_MIN_BUFS) + *nbuffers = S2255_MIN_BUFS; return 0; } -- cgit v1.1 From 8bf405a0da59cee39e244ec75465017248bdef10 Mon Sep 17 00:00:00 2001 From: Dean Anderson Date: Wed, 5 Feb 2014 15:18:55 -0300 Subject: [media] s2255drv: remove redundant parameter Removing duplicate fmt from buffer structure. Signed-off-by: Dean Anderson Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/s2255/s2255drv.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/media/usb/s2255/s2255drv.c b/drivers/media/usb/s2255/s2255drv.c index 1b267b1..517901b 100644 --- a/drivers/media/usb/s2255/s2255drv.c +++ b/drivers/media/usb/s2255/s2255drv.c @@ -290,7 +290,6 @@ struct s2255_fmt { struct s2255_buffer { /* common v4l buffer stuff -- must be first */ struct videobuf_buffer vb; - const struct s2255_fmt *fmt; }; struct s2255_fh { @@ -625,13 +624,13 @@ static void s2255_fillbuff(struct s2255_vc *vc, if (last_frame != -1) { tmpbuf = (const char *)vc->buffer.frame[last_frame].lpvbits; - switch (buf->fmt->fourcc) { + switch (vc->fmt->fourcc) { case V4L2_PIX_FMT_YUYV: case V4L2_PIX_FMT_UYVY: planar422p_to_yuv_packed((const unsigned char *)tmpbuf, vbuf, buf->vb.width, buf->vb.height, - buf->fmt->fourcc); + vc->fmt->fourcc); break; case V4L2_PIX_FMT_GREY: memcpy(vbuf, tmpbuf, buf->vb.width * buf->vb.height); @@ -711,7 +710,6 @@ static int buffer_prepare(struct videobuf_queue *vq, struct videobuf_buffer *vb, return -EINVAL; } - buf->fmt = vc->fmt; buf->vb.width = w; buf->vb.height = h; buf->vb.field = field; -- cgit v1.1 From 47d8c881c304642a68d398b87d9e8846e643c81a Mon Sep 17 00:00:00 2001 From: Dean Anderson Date: Wed, 5 Feb 2014 15:43:51 -0300 Subject: [media] s2255drv: dynamic memory allocation efficiency fix Driver was allocating a kernel buffer each time it was sending a command. It is better to allocate this buffer once at startup. Signed-off-by: Dean Anderson Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/s2255/s2255drv.c | 67 +++++++++++++++++++++----------------- 1 file changed, 37 insertions(+), 30 deletions(-) diff --git a/drivers/media/usb/s2255/s2255drv.c b/drivers/media/usb/s2255/s2255drv.c index 517901b..4c483ad 100644 --- a/drivers/media/usb/s2255/s2255drv.c +++ b/drivers/media/usb/s2255/s2255drv.c @@ -260,6 +260,7 @@ struct s2255_dev { atomic_t num_channels; int frames; struct mutex lock; /* channels[].vdev.lock */ + struct mutex cmdlock; /* protects cmdbuf */ struct usb_device *udev; struct usb_interface *interface; u8 read_endpoint; @@ -273,6 +274,8 @@ struct s2255_dev { /* dsp firmware version (f2255usb.bin) */ int dsp_fw_ver; u16 pid; /* product id */ +#define S2255_CMDBUF_SIZE 512 + __le32 *cmdbuf; }; static inline struct s2255_dev *to_s2255_dev(struct v4l2_device *v4l2_dev) @@ -1121,11 +1124,12 @@ static int s2255_set_mode(struct s2255_vc *vc, struct s2255_mode *mode) { int res; - __le32 *buffer; unsigned long chn_rev; struct s2255_dev *dev = to_s2255_dev(vc->vdev.v4l2_dev); int i; + __le32 *buffer = dev->cmdbuf; + mutex_lock(&dev->cmdlock); chn_rev = G_chnmap[vc->idx]; dprintk(dev, 3, "%s channel: %d\n", __func__, vc->idx); /* if JPEG, set the quality */ @@ -1139,11 +1143,6 @@ static int s2255_set_mode(struct s2255_vc *vc, vc->mode = *mode; vc->req_image_size = get_transfer_size(mode); dprintk(dev, 1, "%s: reqsize %ld\n", __func__, vc->req_image_size); - buffer = kzalloc(512, GFP_KERNEL); - if (buffer == NULL) { - dev_err(&dev->udev->dev, "out of mem\n"); - return -ENOMEM; - } /* set the mode */ buffer[0] = IN_DATA_TOKEN; buffer[1] = (__le32) cpu_to_le32(chn_rev); @@ -1154,7 +1153,6 @@ static int s2255_set_mode(struct s2255_vc *vc, res = s2255_write_config(dev->udev, (unsigned char *)buffer, 512); if (debug) s2255_print_cfg(dev, mode); - kfree(buffer); /* wait at least 3 frames before continuing */ if (mode->restart) { wait_event_timeout(vc->wait_setmode, @@ -1168,22 +1166,20 @@ static int s2255_set_mode(struct s2255_vc *vc, /* clear the restart flag */ vc->mode.restart = 0; dprintk(dev, 1, "%s chn %d, result: %d\n", __func__, vc->idx, res); + mutex_unlock(&dev->cmdlock); return res; } static int s2255_cmd_status(struct s2255_vc *vc, u32 *pstatus) { int res; - __le32 *buffer; u32 chn_rev; struct s2255_dev *dev = to_s2255_dev(vc->vdev.v4l2_dev); + __le32 *buffer = dev->cmdbuf; + + mutex_lock(&dev->cmdlock); chn_rev = G_chnmap[vc->idx]; dprintk(dev, 4, "%s chan %d\n", __func__, vc->idx); - buffer = kzalloc(512, GFP_KERNEL); - if (buffer == NULL) { - dev_err(&dev->udev->dev, "out of mem\n"); - return -ENOMEM; - } /* form the get vid status command */ buffer[0] = IN_DATA_TOKEN; buffer[1] = (__le32) cpu_to_le32(chn_rev); @@ -1191,7 +1187,6 @@ static int s2255_cmd_status(struct s2255_vc *vc, u32 *pstatus) *pstatus = 0; vc->vidstatus_ready = 0; res = s2255_write_config(dev->udev, (unsigned char *)buffer, 512); - kfree(buffer); wait_event_timeout(vc->wait_vidstatus, (vc->vidstatus_ready != 0), msecs_to_jiffies(S2255_VIDSTATUS_TIMEOUT)); @@ -1201,6 +1196,7 @@ static int s2255_cmd_status(struct s2255_vc *vc, u32 *pstatus) } *pstatus = vc->vidstatus; dprintk(dev, 4, "%s, vid status %d\n", __func__, *pstatus); + mutex_unlock(&dev->cmdlock); return res; } @@ -1724,6 +1720,7 @@ static void s2255_destroy(struct s2255_dev *dev) mutex_destroy(&dev->lock); usb_put_dev(dev->udev); v4l2_device_unregister(&dev->v4l2_dev); + kfree(dev->cmdbuf); kfree(dev); } @@ -2350,18 +2347,14 @@ static int s2255_start_readpipe(struct s2255_dev *dev) /* starts acquisition process */ static int s2255_start_acquire(struct s2255_vc *vc) { - unsigned char *buffer; int res; unsigned long chn_rev; int j; struct s2255_dev *dev = to_s2255_dev(vc->vdev.v4l2_dev); - chn_rev = G_chnmap[vc->idx]; - buffer = kzalloc(512, GFP_KERNEL); - if (buffer == NULL) { - dev_err(&dev->udev->dev, "out of mem\n"); - return -ENOMEM; - } + __le32 *buffer = dev->cmdbuf; + mutex_lock(&dev->cmdlock); + chn_rev = G_chnmap[vc->idx]; vc->last_frame = -1; vc->bad_payload = 0; vc->cur_frame = 0; @@ -2371,24 +2364,26 @@ static int s2255_start_acquire(struct s2255_vc *vc) } /* send the start command */ - *(__le32 *) buffer = IN_DATA_TOKEN; - *((__le32 *) buffer + 1) = (__le32) cpu_to_le32(chn_rev); - *((__le32 *) buffer + 2) = CMD_START; + buffer[0] = IN_DATA_TOKEN; + buffer[1] = (__le32) cpu_to_le32(chn_rev); + buffer[2] = CMD_START; res = s2255_write_config(dev->udev, (unsigned char *)buffer, 512); if (res != 0) dev_err(&dev->udev->dev, "CMD_START error\n"); dprintk(dev, 2, "start acquire exit[%d] %d\n", vc->idx, res); - kfree(buffer); + mutex_unlock(&dev->cmdlock); return 0; } static int s2255_stop_acquire(struct s2255_vc *vc) { - unsigned char *buffer; int res; unsigned long chn_rev; struct s2255_dev *dev = to_s2255_dev(vc->vdev.v4l2_dev); + __le32 *buffer = dev->cmdbuf; + + mutex_lock(&dev->cmdlock); chn_rev = G_chnmap[vc->idx]; buffer = kzalloc(512, GFP_KERNEL); if (buffer == NULL) { @@ -2396,15 +2391,17 @@ static int s2255_stop_acquire(struct s2255_vc *vc) return -ENOMEM; } /* send the stop command */ - *(__le32 *) buffer = IN_DATA_TOKEN; - *((__le32 *) buffer + 1) = (__le32) cpu_to_le32(chn_rev); - *((__le32 *) buffer + 2) = CMD_STOP; + buffer[0] = IN_DATA_TOKEN; + buffer[1] = (__le32) cpu_to_le32(chn_rev); + buffer[2] = CMD_STOP; + res = s2255_write_config(dev->udev, (unsigned char *)buffer, 512); if (res != 0) dev_err(&dev->udev->dev, "CMD_STOP error\n"); - kfree(buffer); + vc->b_acquire = 0; dprintk(dev, 4, "%s: chn %d, res %d\n", __func__, vc->idx, res); + mutex_unlock(&dev->cmdlock); return res; } @@ -2451,18 +2448,27 @@ static int s2255_probe(struct usb_interface *interface, int retval = -ENOMEM; __le32 *pdata; int fw_size; + /* allocate memory for our device state and initialize it to zero */ dev = kzalloc(sizeof(struct s2255_dev), GFP_KERNEL); if (dev == NULL) { s2255_dev_err(&interface->dev, "out of memory\n"); return -ENOMEM; } + + dev->cmdbuf = kzalloc(S2255_CMDBUF_SIZE, GFP_KERNEL); + if (dev->cmdbuf == NULL) { + s2255_dev_err(&interface->dev, "out of memory\n"); + return -ENOMEM; + } + atomic_set(&dev->num_channels, 0); dev->pid = le16_to_cpu(id->idProduct); dev->fw_data = kzalloc(sizeof(struct s2255_fw), GFP_KERNEL); if (!dev->fw_data) goto errorFWDATA1; mutex_init(&dev->lock); + mutex_init(&dev->cmdlock); /* grab usb_device and save it */ dev->udev = usb_get_dev(interface_to_usbdev(interface)); if (dev->udev == NULL) { @@ -2568,6 +2574,7 @@ errorUDEV: kfree(dev->fw_data); mutex_destroy(&dev->lock); errorFWDATA1: + kfree(dev->cmdbuf); kfree(dev); pr_warn("Sensoray 2255 driver load failed: 0x%x\n", retval); return retval; -- cgit v1.1 From 6a5b63b3cbf774f6a576133fccb92f54cc8a23e1 Mon Sep 17 00:00:00 2001 From: Dean Anderson Date: Wed, 5 Feb 2014 15:58:20 -0300 Subject: [media] s2255drv: fix for return code not checked Start acquisition return code was not being checked. Return error if start acquisition fails. Signed-off-by: Dean Anderson Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/s2255/s2255drv.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/media/usb/s2255/s2255drv.c b/drivers/media/usb/s2255/s2255drv.c index 4c483ad..787b591 100644 --- a/drivers/media/usb/s2255/s2255drv.c +++ b/drivers/media/usb/s2255/s2255drv.c @@ -1230,12 +1230,16 @@ static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i) vc->buffer.frame[j].cur_size = 0; } res = videobuf_streamon(&fh->vb_vidq); - if (res == 0) { - s2255_start_acquire(vc); - vc->b_acquire = 1; - } else + if (res != 0) { res_free(fh); - + return res; + } + res = s2255_start_acquire(vc); + if (res != 0) { + res_free(fh); + return res; + } + vc->b_acquire = 1; return res; } @@ -2373,7 +2377,7 @@ static int s2255_start_acquire(struct s2255_vc *vc) dprintk(dev, 2, "start acquire exit[%d] %d\n", vc->idx, res); mutex_unlock(&dev->cmdlock); - return 0; + return res; } static int s2255_stop_acquire(struct s2255_vc *vc) -- cgit v1.1 From 92cde477c0cb7fc46c4428145d91f53bb5ffc46a Mon Sep 17 00:00:00 2001 From: Dean Anderson Date: Wed, 5 Feb 2014 17:38:42 -0300 Subject: [media] s2255drv: cleanup of s2255_fh Removal of unnecessary parameters from s2255_fh. Signed-off-by: Dean Anderson Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/s2255/s2255drv.c | 94 ++++++++++++++++++-------------------- 1 file changed, 44 insertions(+), 50 deletions(-) diff --git a/drivers/media/usb/s2255/s2255drv.c b/drivers/media/usb/s2255/s2255drv.c index 787b591..e0663ce 100644 --- a/drivers/media/usb/s2255/s2255drv.c +++ b/drivers/media/usb/s2255/s2255drv.c @@ -298,9 +298,7 @@ struct s2255_buffer { struct s2255_fh { /* this must be the first field in this struct */ struct v4l2_fh fh; - struct s2255_dev *dev; struct videobuf_queue vb_vidq; - enum v4l2_buf_type type; struct s2255_vc *vc; int resources; }; @@ -673,6 +671,7 @@ static int buffer_setup(struct videobuf_queue *vq, unsigned int *nbuffers, { struct s2255_fh *fh = vq->priv_data; struct s2255_vc *vc = fh->vc; + *size = vc->width * vc->height * (vc->fmt->depth >> 3); if (*nbuffers < S2255_MIN_BUFS) @@ -696,7 +695,7 @@ static int buffer_prepare(struct videobuf_queue *vq, struct videobuf_buffer *vb, int rc; int w = vc->width; int h = vc->height; - dprintk(fh->dev, 4, "%s, field=%d\n", __func__, field); + dprintk(vc->dev, 4, "%s, field=%d\n", __func__, field); if (vc->fmt == NULL) return -EINVAL; @@ -704,12 +703,12 @@ static int buffer_prepare(struct videobuf_queue *vq, struct videobuf_buffer *vb, (w > norm_maxw(vc)) || (h < norm_minh(vc)) || (h > norm_maxh(vc))) { - dprintk(fh->dev, 4, "invalid buffer prepare\n"); + dprintk(vc->dev, 4, "invalid buffer prepare\n"); return -EINVAL; } buf->vb.size = w * h * (vc->fmt->depth >> 3); if (0 != buf->vb.baddr && buf->vb.bsize < buf->vb.size) { - dprintk(fh->dev, 4, "invalid buffer prepare\n"); + dprintk(vc->dev, 4, "invalid buffer prepare\n"); return -EINVAL; } @@ -735,7 +734,7 @@ static void buffer_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb) struct s2255_buffer *buf = container_of(vb, struct s2255_buffer, vb); struct s2255_fh *fh = vq->priv_data; struct s2255_vc *vc = fh->vc; - dprintk(fh->dev, 1, "%s\n", __func__); + dprintk(vc->dev, 1, "%s\n", __func__); buf->vb.state = VIDEOBUF_QUEUED; list_add_tail(&buf->vb.queue, &vc->buf_list); } @@ -745,7 +744,8 @@ static void buffer_release(struct videobuf_queue *vq, { struct s2255_buffer *buf = container_of(vb, struct s2255_buffer, vb); struct s2255_fh *fh = vq->priv_data; - dprintk(fh->dev, 4, "%s %d\n", __func__, fh->vc->idx); + struct s2255_vc *vc = fh->vc; + dprintk(vc->dev, 4, "%s %d\n", __func__, vc->idx); free_buffer(vq, buf); } @@ -766,7 +766,7 @@ static int res_get(struct s2255_fh *fh) /* it's free, grab it */ vc->resources = 1; fh->resources = 1; - dprintk(fh->dev, 1, "s2255: res: get\n"); + dprintk(vc->dev, 1, "s2255: res: get\n"); return 1; } @@ -792,7 +792,7 @@ static int vidioc_querycap(struct file *file, void *priv, struct v4l2_capability *cap) { struct s2255_fh *fh = file->private_data; - struct s2255_dev *dev = fh->dev; + struct s2255_dev *dev = fh->vc->dev; strlcpy(cap->driver, "s2255", sizeof(cap->driver)); strlcpy(cap->card, "s2255", sizeof(cap->card)); @@ -855,7 +855,7 @@ static int vidioc_try_fmt_vid_cap(struct file *file, void *priv, field = f->fmt.pix.field; - dprintk(fh->dev, 50, "%s NTSC: %d suggested width: %d, height: %d\n", + dprintk(vc->dev, 50, "%s NTSC: %d suggested width: %d, height: %d\n", __func__, is_ntsc, f->fmt.pix.width, f->fmt.pix.height); if (is_ntsc) { /* NTSC */ @@ -897,7 +897,7 @@ static int vidioc_try_fmt_vid_cap(struct file *file, void *priv, f->fmt.pix.sizeimage = f->fmt.pix.height * f->fmt.pix.bytesperline; f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M; f->fmt.pix.priv = 0; - dprintk(fh->dev, 50, "%s: set width %d height %d field %d\n", __func__, + dprintk(vc->dev, 50, "%s: set width %d height %d field %d\n", __func__, f->fmt.pix.width, f->fmt.pix.height, f->fmt.pix.field); return 0; } @@ -925,13 +925,13 @@ static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, mutex_lock(&q->vb_lock); if (videobuf_queue_is_busy(&fh->vb_vidq)) { - dprintk(fh->dev, 1, "queue busy\n"); + dprintk(vc->dev, 1, "queue busy\n"); ret = -EBUSY; goto out_s_fmt; } if (res_locked(fh)) { - dprintk(fh->dev, 1, "%s: channel busy\n", __func__); + dprintk(vc->dev, 1, "%s: channel busy\n", __func__); ret = -EBUSY; goto out_s_fmt; } @@ -940,7 +940,6 @@ static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, vc->width = f->fmt.pix.width; vc->height = f->fmt.pix.height; fh->vb_vidq.field = f->fmt.pix.field; - fh->type = f->type; if (vc->width > norm_minw(vc)) { if (vc->height > norm_minh(vc)) { if (vc->cap_parm.capturemode & @@ -1204,15 +1203,12 @@ static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i) { int res; struct s2255_fh *fh = priv; - struct s2255_dev *dev = fh->dev; struct s2255_vc *vc = fh->vc; + struct s2255_dev *dev = vc->dev; int j; + dprintk(dev, 4, "%s\n", __func__); - if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) { - dev_err(&dev->udev->dev, "invalid fh type0\n"); - return -EINVAL; - } - if (i != fh->type) { + if (i != V4L2_BUF_TYPE_VIDEO_CAPTURE) { dev_err(&dev->udev->dev, "invalid fh type1\n"); return -EINVAL; } @@ -1246,14 +1242,12 @@ static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i) static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i) { struct s2255_fh *fh = priv; - dprintk(fh->dev, 4, "%s\n, channel: %d", __func__, fh->vc->idx); - if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) { - dprintk(fh->dev, 1, "invalid fh type0\n"); - return -EINVAL; - } - if (i != fh->type) + struct s2255_vc *vc = fh->vc; + dprintk(vc->dev, 4, "%s\n, channel: %d", __func__, vc->idx); + + if (i != V4L2_BUF_TYPE_VIDEO_CAPTURE) return -EINVAL; - s2255_stop_acquire(fh->vc); + s2255_stop_acquire(vc); videobuf_streamoff(&fh->vb_vidq); res_free(fh); return 0; @@ -1269,13 +1263,13 @@ static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id i) mutex_lock(&q->vb_lock); if (res_locked(fh)) { - dprintk(fh->dev, 1, "can't change standard after started\n"); + dprintk(vc->dev, 1, "can't change standard after started\n"); ret = -EBUSY; goto out_s_std; } - mode = fh->vc->mode; + mode = vc->mode; if (i & V4L2_STD_525_60) { - dprintk(fh->dev, 4, "%s 60 Hz\n", __func__); + dprintk(vc->dev, 4, "%s 60 Hz\n", __func__); /* if changing format, reset frame decimation/intervals */ if (mode.format != FORMAT_NTSC) { mode.restart = 1; @@ -1285,7 +1279,7 @@ static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id i) vc->height = NUM_LINES_4CIFS_NTSC * 2; } } else if (i & V4L2_STD_625_50) { - dprintk(fh->dev, 4, "%s 50 Hz\n", __func__); + dprintk(vc->dev, 4, "%s 50 Hz\n", __func__); if (mode.format != FORMAT_PAL) { mode.restart = 1; mode.format = FORMAT_PAL; @@ -1297,9 +1291,9 @@ static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id i) ret = -EINVAL; goto out_s_std; } - fh->vc->std = i; + vc->std = i; if (mode.restart) - s2255_set_mode(fh->vc, &mode); + s2255_set_mode(vc, &mode); out_s_std: mutex_unlock(&q->vb_lock); return ret; @@ -1308,8 +1302,9 @@ out_s_std: static int vidioc_g_std(struct file *file, void *priv, v4l2_std_id *i) { struct s2255_fh *fh = priv; + struct s2255_vc *vc = fh->vc; - *i = fh->vc->std; + *i = vc->std; return 0; } @@ -1324,9 +1319,10 @@ static int vidioc_enum_input(struct file *file, void *priv, struct v4l2_input *inp) { struct s2255_fh *fh = priv; - struct s2255_dev *dev = fh->dev; struct s2255_vc *vc = fh->vc; + struct s2255_dev *dev = vc->dev; u32 status = 0; + if (inp->index != 0) return -EINVAL; inp->type = V4L2_INPUT_TYPE_CAMERA; @@ -1334,7 +1330,7 @@ static int vidioc_enum_input(struct file *file, void *priv, inp->status = 0; if (dev->dsp_fw_ver >= S2255_MIN_DSP_STATUS) { int rc; - rc = s2255_cmd_status(fh->vc, &status); + rc = s2255_cmd_status(vc, &status); dprintk(dev, 4, "s2255_cmd_status rc: %d status %x\n", rc, status); if (rc == 0) @@ -1413,7 +1409,7 @@ static int vidioc_g_jpegcomp(struct file *file, void *priv, memset(jc, 0, sizeof(*jc)); jc->quality = vc->jpegqual; - dprintk(fh->dev, 2, "%s: quality %d\n", __func__, jc->quality); + dprintk(vc->dev, 2, "%s: quality %d\n", __func__, jc->quality); return 0; } @@ -1425,7 +1421,7 @@ static int vidioc_s_jpegcomp(struct file *file, void *priv, if (jc->quality < 0 || jc->quality > 100) return -EINVAL; v4l2_ctrl_s_ctrl(vc->jpegqual_ctrl, jc->quality); - dprintk(fh->dev, 2, "%s: quality %d\n", __func__, jc->quality); + dprintk(vc->dev, 2, "%s: quality %d\n", __func__, jc->quality); return 0; } @@ -1457,7 +1453,7 @@ static int vidioc_g_parm(struct file *file, void *priv, sp->parm.capture.timeperframe.numerator = def_num * 5; break; } - dprintk(fh->dev, 4, "%s capture mode, %d timeperframe %d/%d\n", + dprintk(vc->dev, 4, "%s capture mode, %d timeperframe %d/%d\n", __func__, sp->parm.capture.capturemode, sp->parm.capture.timeperframe.numerator, @@ -1499,7 +1495,7 @@ static int vidioc_s_parm(struct file *file, void *priv, mode.fdec = fdec; sp->parm.capture.timeperframe.denominator = def_dem; s2255_set_mode(vc, &mode); - dprintk(fh->dev, 4, "%s capture mode, %d timeperframe %d/%d, fdec %d\n", + dprintk(vc->dev, 4, "%s capture mode, %d timeperframe %d/%d, fdec %d\n", __func__, sp->parm.capture.capturemode, sp->parm.capture.timeperframe.numerator, @@ -1568,7 +1564,7 @@ static int vidioc_enum_frameintervals(struct file *file, void *priv, fe->type = V4L2_FRMIVAL_TYPE_DISCRETE; fe->discrete.denominator = is_ntsc ? 30000 : 25000; fe->discrete.numerator = (is_ntsc ? 1001 : 1000) * frm_dec[fe->index]; - dprintk(fh->dev, 4, "%s discrete %d/%d\n", __func__, + dprintk(vc->dev, 4, "%s discrete %d/%d\n", __func__, fe->discrete.numerator, fe->discrete.denominator); return 0; @@ -1652,8 +1648,6 @@ static int __s2255_open(struct file *file) v4l2_fh_init(&fh->fh, vdev); v4l2_fh_add(&fh->fh); file->private_data = &fh->fh; - fh->dev = dev; - fh->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; fh->vc = vc; if (!vc->configured) { /* configure channel to default state */ @@ -1669,7 +1663,7 @@ static int __s2255_open(struct file *file) list_empty(&vc->buf_list)); videobuf_queue_vmalloc_init(&fh->vb_vidq, &s2255_video_qops, NULL, &dev->slock, - fh->type, + V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_INTERLACED, sizeof(struct s2255_buffer), fh, vdev->lock); @@ -1692,12 +1686,10 @@ static unsigned int s2255_poll(struct file *file, struct poll_table_struct *wait) { struct s2255_fh *fh = file->private_data; - struct s2255_dev *dev = fh->dev; + struct s2255_dev *dev = fh->vc->dev; int rc = v4l2_ctrl_poll(file, wait); dprintk(dev, 100, "%s\n", __func__); - if (V4L2_BUF_TYPE_VIDEO_CAPTURE != fh->type) - return POLLERR; mutex_lock(&dev->lock); rc |= videobuf_poll_stream(file, &fh->vb_vidq, wait); mutex_unlock(&dev->lock); @@ -1731,16 +1723,17 @@ static void s2255_destroy(struct s2255_dev *dev) static int s2255_release(struct file *file) { struct s2255_fh *fh = file->private_data; - struct s2255_dev *dev = fh->dev; struct video_device *vdev = video_devdata(file); struct s2255_vc *vc = fh->vc; + struct s2255_dev *dev = vc->dev; + if (!dev) return -ENODEV; mutex_lock(&dev->lock); /* turn off stream */ if (res_check(fh)) { if (vc->b_acquire) - s2255_stop_acquire(fh->vc); + s2255_stop_acquire(vc); videobuf_streamoff(&fh->vb_vidq); res_free(fh); } @@ -1758,9 +1751,10 @@ static int s2255_mmap_v4l(struct file *file, struct vm_area_struct *vma) struct s2255_fh *fh = file->private_data; struct s2255_dev *dev; int ret; + if (!fh) return -ENODEV; - dev = fh->dev; + dev = fh->vc->dev; dprintk(dev, 4, "%s, vma=0x%08lx\n", __func__, (unsigned long)vma); if (mutex_lock_interruptible(&dev->lock)) return -ERESTARTSYS; -- cgit v1.1 From 8a027faf4cb2b071dcb565c94492e143f6786213 Mon Sep 17 00:00:00 2001 From: Martin Bugge Date: Fri, 7 Feb 2014 05:11:03 -0300 Subject: [media] ths8200: Zero blanking level for RGB Currently only RGB444 input data is supported so set to zero. Acked-by: Lad, Prabhakar Signed-off-by: Martin Bugge Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/i2c/ths8200.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/media/i2c/ths8200.c b/drivers/media/i2c/ths8200.c index 04139ee..5c7dca3 100644 --- a/drivers/media/i2c/ths8200.c +++ b/drivers/media/i2c/ths8200.c @@ -217,8 +217,8 @@ static void ths8200_core_init(struct v4l2_subdev *sd) /* Disable embedded syncs on the output by setting * the amplitude to zero for all channels. */ - ths8200_write(sd, THS8200_DTG1_Y_SYNC_MSB, 0x2a); - ths8200_write(sd, THS8200_DTG1_CBCR_SYNC_MSB, 0x2a); + ths8200_write(sd, THS8200_DTG1_Y_SYNC_MSB, 0x00); + ths8200_write(sd, THS8200_DTG1_CBCR_SYNC_MSB, 0x00); } static void ths8200_setup(struct v4l2_subdev *sd, struct v4l2_bt_timings *bt) -- cgit v1.1 From 00b9f51e1fda8a10ad6f52656722ee618e6a431d Mon Sep 17 00:00:00 2001 From: Martin Bugge Date: Fri, 7 Feb 2014 05:11:04 -0300 Subject: [media] ths8200: Corrected sync polarities setting HS_IN/VS_IN was always set to positive. Acked-by: Lad, Prabhakar Signed-off-by: Martin Bugge Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/i2c/ths8200.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/i2c/ths8200.c b/drivers/media/i2c/ths8200.c index 5c7dca3..bcacf52 100644 --- a/drivers/media/i2c/ths8200.c +++ b/drivers/media/i2c/ths8200.c @@ -356,7 +356,7 @@ static void ths8200_setup(struct v4l2_subdev *sd, struct v4l2_bt_timings *bt) /* Timing of video input bus is derived from HS, VS, and FID dedicated * inputs */ - ths8200_write(sd, THS8200_DTG2_CNTL, 0x47 | polarity); + ths8200_write(sd, THS8200_DTG2_CNTL, 0x44 | polarity); /* leave reset */ ths8200_s_stream(sd, true); -- cgit v1.1 From 2dfb1c939cf7fa03aaa36e7c7da02dd105c6b273 Mon Sep 17 00:00:00 2001 From: Martin Bugge Date: Fri, 7 Feb 2014 05:11:05 -0300 Subject: [media] ths8200: Format adjustment Closer inspection on exact transmitted format showed that we needed to add 1 on vertical sync. Acked-by: Lad, Prabhakar Signed-off-by: Martin Bugge Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/i2c/ths8200.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/media/i2c/ths8200.c b/drivers/media/i2c/ths8200.c index bcacf52..f72561e 100644 --- a/drivers/media/i2c/ths8200.c +++ b/drivers/media/i2c/ths8200.c @@ -318,15 +318,15 @@ static void ths8200_setup(struct v4l2_subdev *sd, struct v4l2_bt_timings *bt) (htotal(bt) >> 8) & 0x1f); ths8200_write(sd, THS8200_DTG2_HLENGTH_HDLY_LSB, htotal(bt)); - /* v sync width transmitted */ - ths8200_write(sd, THS8200_DTG2_VLENGTH1_LSB, (bt->vsync) & 0xff); + /* v sync width transmitted (must add 1 to get correct output) */ + ths8200_write(sd, THS8200_DTG2_VLENGTH1_LSB, (bt->vsync + 1) & 0xff); ths8200_write_and_or(sd, THS8200_DTG2_VLENGTH1_MSB_VDLY1_MSB, 0x3f, - ((bt->vsync) >> 2) & 0xc0); + ((bt->vsync + 1) >> 2) & 0xc0); - /* The pixel value v sync is asserted on */ + /* The pixel value v sync is asserted on (must add 1 to get correct output) */ ths8200_write_and_or(sd, THS8200_DTG2_VLENGTH1_MSB_VDLY1_MSB, 0xf8, - (vtotal(bt)>>8) & 0x7); - ths8200_write(sd, THS8200_DTG2_VDLY1_LSB, vtotal(bt)); + ((vtotal(bt) + 1) >> 8) & 0x7); + ths8200_write(sd, THS8200_DTG2_VDLY1_LSB, vtotal(bt) + 1); /* For progressive video vlength2 must be set to all 0 and vdly2 must * be set to all 1. @@ -336,11 +336,11 @@ static void ths8200_setup(struct v4l2_subdev *sd, struct v4l2_bt_timings *bt) ths8200_write(sd, THS8200_DTG2_VDLY2_LSB, 0xff); /* Internal delay factors to synchronize the sync pulses and the data */ - /* Experimental values delays (hor 4, ver 1) */ - ths8200_write(sd, THS8200_DTG2_HS_IN_DLY_MSB, (htotal(bt)>>8) & 0x1f); - ths8200_write(sd, THS8200_DTG2_HS_IN_DLY_LSB, (htotal(bt) - 4) & 0xff); + /* Experimental values delays (hor 0, ver 0) */ + ths8200_write(sd, THS8200_DTG2_HS_IN_DLY_MSB, 0); + ths8200_write(sd, THS8200_DTG2_HS_IN_DLY_LSB, 0); ths8200_write(sd, THS8200_DTG2_VS_IN_DLY_MSB, 0); - ths8200_write(sd, THS8200_DTG2_VS_IN_DLY_LSB, 1); + ths8200_write(sd, THS8200_DTG2_VS_IN_DLY_LSB, 0); /* Polarity of received and transmitted sync signals */ if (bt->polarities & V4L2_DV_HSYNC_POS_POL) { -- cgit v1.1 From ce0ede2c06202dace68a2f0401ebaafdaa2720d2 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Mon, 10 Feb 2014 07:21:36 -0300 Subject: [media] radio-cadet: avoid interruptible_sleep_on race interruptible_sleep_on is racy and going away. This replaces one use in the radio-cadet driver with a wait_event_interruptible call. Special care was taken that accesses to the rdsin and rdsout indices are always done with dev->lock held. Signed-off-by: Hans Verkuil Acked-by: Arnd Bergmann Signed-off-by: Mauro Carvalho Chehab --- drivers/media/radio/radio-cadet.c | 46 +++++++++++++++++++++++---------------- 1 file changed, 27 insertions(+), 19 deletions(-) diff --git a/drivers/media/radio/radio-cadet.c b/drivers/media/radio/radio-cadet.c index 545c04c..d719e59 100644 --- a/drivers/media/radio/radio-cadet.c +++ b/drivers/media/radio/radio-cadet.c @@ -270,6 +270,16 @@ reset_rds: outb(inb(dev->io + 1) & 0x7f, dev->io + 1); } +static bool cadet_has_rds_data(struct cadet *dev) +{ + bool result; + + mutex_lock(&dev->lock); + result = dev->rdsin != dev->rdsout; + mutex_unlock(&dev->lock); + return result; +} + static void cadet_handler(unsigned long data) { @@ -279,13 +289,12 @@ static void cadet_handler(unsigned long data) if (mutex_trylock(&dev->lock)) { outb(0x3, dev->io); /* Select RDS Decoder Control */ if ((inb(dev->io + 1) & 0x20) != 0) - printk(KERN_CRIT "cadet: RDS fifo overflow\n"); + pr_err("cadet: RDS fifo overflow\n"); outb(0x80, dev->io); /* Select RDS fifo */ + while ((inb(dev->io) & 0x80) != 0) { dev->rdsbuf[dev->rdsin] = inb(dev->io + 1); - if (dev->rdsin + 1 == dev->rdsout) - printk(KERN_WARNING "cadet: RDS buffer overflow\n"); - else + if (dev->rdsin + 1 != dev->rdsout) dev->rdsin++; } mutex_unlock(&dev->lock); @@ -294,7 +303,7 @@ static void cadet_handler(unsigned long data) /* * Service pending read */ - if (dev->rdsin != dev->rdsout) + if (cadet_has_rds_data(dev)) wake_up_interruptible(&dev->read_queue); /* @@ -327,22 +336,21 @@ static ssize_t cadet_read(struct file *file, char __user *data, size_t count, lo mutex_lock(&dev->lock); if (dev->rdsstat == 0) cadet_start_rds(dev); - if (dev->rdsin == dev->rdsout) { - if (file->f_flags & O_NONBLOCK) { - i = -EWOULDBLOCK; - goto unlock; - } - mutex_unlock(&dev->lock); - interruptible_sleep_on(&dev->read_queue); - mutex_lock(&dev->lock); - } + mutex_unlock(&dev->lock); + + if (!cadet_has_rds_data(dev) && (file->f_flags & O_NONBLOCK)) + return -EWOULDBLOCK; + i = wait_event_interruptible(dev->read_queue, cadet_has_rds_data(dev)); + if (i) + return i; + + mutex_lock(&dev->lock); while (i < count && dev->rdsin != dev->rdsout) readbuf[i++] = dev->rdsbuf[dev->rdsout++]; + mutex_unlock(&dev->lock); if (i && copy_to_user(data, readbuf, i)) - i = -EFAULT; -unlock: - mutex_unlock(&dev->lock); + return -EFAULT; return i; } @@ -352,7 +360,7 @@ static int vidioc_querycap(struct file *file, void *priv, { strlcpy(v->driver, "ADS Cadet", sizeof(v->driver)); strlcpy(v->card, "ADS Cadet", sizeof(v->card)); - strlcpy(v->bus_info, "ISA", sizeof(v->bus_info)); + strlcpy(v->bus_info, "ISA:radio-cadet", sizeof(v->bus_info)); v->device_caps = V4L2_CAP_TUNER | V4L2_CAP_RADIO | V4L2_CAP_READWRITE | V4L2_CAP_RDS_CAPTURE; v->capabilities = v->device_caps | V4L2_CAP_DEVICE_CAPS; @@ -491,7 +499,7 @@ static unsigned int cadet_poll(struct file *file, struct poll_table_struct *wait cadet_start_rds(dev); mutex_unlock(&dev->lock); } - if (dev->rdsin != dev->rdsout) + if (cadet_has_rds_data(dev)) res |= POLLIN | POLLRDNORM; return res; } -- cgit v1.1 From 6a859e09c40f09fd77411ca46d8b6ca1c08444fe Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 2 Jan 2014 09:07:29 -0300 Subject: [media] omap_vout: avoid sleep_on race sleep_on and its variants are broken and going away soon. This changes the omap vout driver to use wait_event_interruptible_timeout instead, which fixes potential race where the dma is complete before we schedule. [hans.verkuil@cisco.com: replaced interruptible_sleep_on_timeout by wait_event_interruptible_timeout in the commit msg, obvious typo] Signed-off-by: Arnd Bergmann Cc: Mauro Carvalho Chehab Cc: linux-media@vger.kernel.org Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/platform/omap/omap_vout_vrfb.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/omap/omap_vout_vrfb.c b/drivers/media/platform/omap/omap_vout_vrfb.c index cf1c437..62e7e57 100644 --- a/drivers/media/platform/omap/omap_vout_vrfb.c +++ b/drivers/media/platform/omap/omap_vout_vrfb.c @@ -270,7 +270,8 @@ int omap_vout_prepare_vrfb(struct omap_vout_device *vout, omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE, 0x20, 0); omap_start_dma(tx->dma_ch); - interruptible_sleep_on_timeout(&tx->wait, VRFB_TX_TIMEOUT); + wait_event_interruptible_timeout(tx->wait, tx->tx_status == 1, + VRFB_TX_TIMEOUT); if (tx->tx_status == 0) { omap_stop_dma(tx->dma_ch); -- cgit v1.1 From 340a30c5148d162ea054fd80112b864f14db9138 Mon Sep 17 00:00:00 2001 From: sensoray-dev Date: Wed, 12 Feb 2014 17:25:45 -0300 Subject: [media] s2255drv: upgrade to videobuf2 Upgrade to videobuf2 libraries. No errors reported with "v4l2-compliance -s". Signed-off-by: Dean Anderson Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/s2255/s2255drv.c | 512 +++++++++++-------------------------- 1 file changed, 152 insertions(+), 360 deletions(-) diff --git a/drivers/media/usb/s2255/s2255drv.c b/drivers/media/usb/s2255/s2255drv.c index e0663ce..ef66b1b 100644 --- a/drivers/media/usb/s2255/s2255drv.c +++ b/drivers/media/usb/s2255/s2255drv.c @@ -45,14 +45,14 @@ #include #include #include -#include +#include #include #include #include #include #include -#define S2255_VERSION "1.24.1" +#define S2255_VERSION "1.25.1" #define FIRMWARE_FILE_NAME "f2255usb.bin" /* default JPEG quality */ @@ -229,8 +229,6 @@ struct s2255_vc { struct v4l2_captureparm cap_parm; int cur_frame; int last_frame; - - int b_acquire; /* allocated image size */ unsigned long req_image_size; /* received packet size */ @@ -249,8 +247,12 @@ struct s2255_vc { int vidstatus_ready; unsigned int width; unsigned int height; + enum v4l2_field field; const struct s2255_fmt *fmt; int idx; /* channel number on device, 0-3 */ + struct vb2_queue vb_vidq; + struct mutex vb_lock; /* streaming lock */ + spinlock_t qlock; }; @@ -270,7 +272,6 @@ struct s2255_dev { u32 cc; /* current channel */ int frame_ready; int chn_ready; - spinlock_t slock; /* dsp firmware version (f2255usb.bin) */ int dsp_fw_ver; u16 pid; /* product id */ @@ -292,16 +293,10 @@ struct s2255_fmt { /* buffer for one video frame */ struct s2255_buffer { /* common v4l buffer stuff -- must be first */ - struct videobuf_buffer vb; + struct vb2_buffer vb; + struct list_head list; }; -struct s2255_fh { - /* this must be the first field in this struct */ - struct v4l2_fh fh; - struct videobuf_queue vb_vidq; - struct s2255_vc *vc; - int resources; -}; /* current cypress EEPROM firmware version */ #define S2255_CUR_USB_FWVER ((3 << 8) | 12) @@ -569,21 +564,20 @@ static int s2255_got_frame(struct s2255_vc *vc, int jpgsize) struct s2255_dev *dev = to_s2255_dev(vc->vdev.v4l2_dev); unsigned long flags = 0; int rc = 0; - spin_lock_irqsave(&dev->slock, flags); + spin_lock_irqsave(&vc->qlock, flags); if (list_empty(&vc->buf_list)) { dprintk(dev, 1, "No active queue to serve\n"); rc = -1; goto unlock; } buf = list_entry(vc->buf_list.next, - struct s2255_buffer, vb.queue); - list_del(&buf->vb.queue); - v4l2_get_timestamp(&buf->vb.ts); + struct s2255_buffer, list); + list_del(&buf->list); + v4l2_get_timestamp(&buf->vb.v4l2_buf.timestamp); s2255_fillbuff(vc, buf, jpgsize); - wake_up(&buf->vb.done); - dprintk(dev, 2, "%s: [buf/i] [%p/%d]\n", __func__, buf, buf->vb.i); + dprintk(dev, 2, "%s: [buf] [%p]\n", __func__, buf); unlock: - spin_unlock_irqrestore(&dev->slock, flags); + spin_unlock_irqrestore(&vc->qlock, flags); return rc; } @@ -615,7 +609,7 @@ static void s2255_fillbuff(struct s2255_vc *vc, { int pos = 0; const char *tmpbuf; - char *vbuf = videobuf_to_vmalloc(&buf->vb); + char *vbuf = vb2_plane_vaddr(&buf->vb, 0); unsigned long last_frame; struct s2255_dev *dev = vc->dev; @@ -629,21 +623,21 @@ static void s2255_fillbuff(struct s2255_vc *vc, case V4L2_PIX_FMT_YUYV: case V4L2_PIX_FMT_UYVY: planar422p_to_yuv_packed((const unsigned char *)tmpbuf, - vbuf, buf->vb.width, - buf->vb.height, + vbuf, vc->width, + vc->height, vc->fmt->fourcc); break; case V4L2_PIX_FMT_GREY: - memcpy(vbuf, tmpbuf, buf->vb.width * buf->vb.height); + memcpy(vbuf, tmpbuf, vc->width * vc->height); break; case V4L2_PIX_FMT_JPEG: case V4L2_PIX_FMT_MJPEG: - buf->vb.size = jpgsize; - memcpy(vbuf, tmpbuf, buf->vb.size); + buf->vb.v4l2_buf.length = jpgsize; + memcpy(vbuf, tmpbuf, jpgsize); break; case V4L2_PIX_FMT_YUV422P: memcpy(vbuf, tmpbuf, - buf->vb.width * buf->vb.height * 2); + vc->width * vc->height * 2); break; default: pr_info("s2255: unknown format?\n"); @@ -656,9 +650,10 @@ static void s2255_fillbuff(struct s2255_vc *vc, dprintk(dev, 2, "s2255fill at : Buffer 0x%08lx size= %d\n", (unsigned long)vbuf, pos); /* tell v4l buffer was filled */ - buf->vb.field_count = vc->frame_count * 2; - v4l2_get_timestamp(&buf->vb.ts); - buf->vb.state = VIDEOBUF_DONE; + buf->vb.v4l2_buf.field = vc->field; + buf->vb.v4l2_buf.sequence = vc->frame_count; + v4l2_get_timestamp(&buf->vb.v4l2_buf.timestamp); + vb2_buffer_done(&buf->vb, VB2_BUF_STATE_DONE); } @@ -666,36 +661,27 @@ static void s2255_fillbuff(struct s2255_vc *vc, Videobuf operations ------------------------------------------------------------------*/ -static int buffer_setup(struct videobuf_queue *vq, unsigned int *nbuffers, - unsigned int *size) +static int queue_setup(struct vb2_queue *vq, const struct v4l2_format *fmt, + unsigned int *nbuffers, unsigned int *nplanes, + unsigned int sizes[], void *alloc_ctxs[]) { - struct s2255_fh *fh = vq->priv_data; - struct s2255_vc *vc = fh->vc; - - *size = vc->width * vc->height * (vc->fmt->depth >> 3); - + struct s2255_vc *vc = vb2_get_drv_priv(vq); if (*nbuffers < S2255_MIN_BUFS) *nbuffers = S2255_MIN_BUFS; - + *nplanes = 1; + sizes[0] = vc->width * vc->height * (vc->fmt->depth >> 3); return 0; } -static void free_buffer(struct videobuf_queue *vq, struct s2255_buffer *buf) -{ - videobuf_vmalloc_free(&buf->vb); - buf->vb.state = VIDEOBUF_NEEDS_INIT; -} - -static int buffer_prepare(struct videobuf_queue *vq, struct videobuf_buffer *vb, - enum v4l2_field field) +static int buffer_prepare(struct vb2_buffer *vb) { - struct s2255_fh *fh = vq->priv_data; - struct s2255_vc *vc = fh->vc; + struct s2255_vc *vc = vb2_get_drv_priv(vb->vb2_queue); struct s2255_buffer *buf = container_of(vb, struct s2255_buffer, vb); - int rc; int w = vc->width; int h = vc->height; - dprintk(vc->dev, 4, "%s, field=%d\n", __func__, field); + unsigned long size; + + dprintk(vc->dev, 4, "%s\n", __func__); if (vc->fmt == NULL) return -EINVAL; @@ -706,98 +692,51 @@ static int buffer_prepare(struct videobuf_queue *vq, struct videobuf_buffer *vb, dprintk(vc->dev, 4, "invalid buffer prepare\n"); return -EINVAL; } - buf->vb.size = w * h * (vc->fmt->depth >> 3); - if (0 != buf->vb.baddr && buf->vb.bsize < buf->vb.size) { + size = w * h * (vc->fmt->depth >> 3); + if (vb2_plane_size(vb, 0) < size) { dprintk(vc->dev, 4, "invalid buffer prepare\n"); return -EINVAL; } - buf->vb.width = w; - buf->vb.height = h; - buf->vb.field = field; - - if (VIDEOBUF_NEEDS_INIT == buf->vb.state) { - rc = videobuf_iolock(vq, &buf->vb, NULL); - if (rc < 0) - goto fail; - } - - buf->vb.state = VIDEOBUF_PREPARED; + vb2_set_plane_payload(&buf->vb, 0, size); return 0; -fail: - free_buffer(vq, buf); - return rc; } -static void buffer_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb) +static void buffer_queue(struct vb2_buffer *vb) { struct s2255_buffer *buf = container_of(vb, struct s2255_buffer, vb); - struct s2255_fh *fh = vq->priv_data; - struct s2255_vc *vc = fh->vc; + struct s2255_vc *vc = vb2_get_drv_priv(vb->vb2_queue); + unsigned long flags = 0; dprintk(vc->dev, 1, "%s\n", __func__); - buf->vb.state = VIDEOBUF_QUEUED; - list_add_tail(&buf->vb.queue, &vc->buf_list); + spin_lock_irqsave(&vc->qlock, flags); + list_add_tail(&buf->list, &vc->buf_list); + spin_unlock_irqrestore(&vc->qlock, flags); } -static void buffer_release(struct videobuf_queue *vq, - struct videobuf_buffer *vb) -{ - struct s2255_buffer *buf = container_of(vb, struct s2255_buffer, vb); - struct s2255_fh *fh = vq->priv_data; - struct s2255_vc *vc = fh->vc; - dprintk(vc->dev, 4, "%s %d\n", __func__, vc->idx); - free_buffer(vq, buf); -} +static int start_streaming(struct vb2_queue *vq, unsigned int count); +static int stop_streaming(struct vb2_queue *vq); -static struct videobuf_queue_ops s2255_video_qops = { - .buf_setup = buffer_setup, +static struct vb2_ops s2255_video_qops = { + .queue_setup = queue_setup, .buf_prepare = buffer_prepare, .buf_queue = buffer_queue, - .buf_release = buffer_release, + .start_streaming = start_streaming, + .stop_streaming = stop_streaming, + .wait_prepare = vb2_ops_wait_prepare, + .wait_finish = vb2_ops_wait_finish, }; - -static int res_get(struct s2255_fh *fh) -{ - struct s2255_vc *vc = fh->vc; - /* is it free? */ - if (vc->resources) - return 0; /* no, someone else uses it */ - /* it's free, grab it */ - vc->resources = 1; - fh->resources = 1; - dprintk(vc->dev, 1, "s2255: res: get\n"); - return 1; -} - -static int res_locked(struct s2255_fh *fh) -{ - return fh->vc->resources; -} - -static int res_check(struct s2255_fh *fh) -{ - return fh->resources; -} - - -static void res_free(struct s2255_fh *fh) -{ - struct s2255_vc *vc = fh->vc; - vc->resources = 0; - fh->resources = 0; -} - static int vidioc_querycap(struct file *file, void *priv, struct v4l2_capability *cap) { - struct s2255_fh *fh = file->private_data; - struct s2255_dev *dev = fh->vc->dev; + struct s2255_vc *vc = video_drvdata(file); + struct s2255_dev *dev = vc->dev; strlcpy(cap->driver, "s2255", sizeof(cap->driver)); strlcpy(cap->card, "s2255", sizeof(cap->card)); usb_make_path(dev->udev, cap->bus_info, sizeof(cap->bus_info)); - cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; + cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING | + V4L2_CAP_READWRITE; cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS; return 0; } @@ -820,8 +759,7 @@ static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv, static int vidioc_g_fmt_vid_cap(struct file *file, void *priv, struct v4l2_format *f) { - struct s2255_fh *fh = priv; - struct s2255_vc *vc = fh->vc; + struct s2255_vc *vc = video_drvdata(file); int is_ntsc = vc->std & V4L2_STD_525_60; f->fmt.pix.width = vc->width; @@ -844,8 +782,7 @@ static int vidioc_try_fmt_vid_cap(struct file *file, void *priv, { const struct s2255_fmt *fmt; enum v4l2_field field; - struct s2255_fh *fh = priv; - struct s2255_vc *vc = fh->vc; + struct s2255_vc *vc = video_drvdata(file); int is_ntsc = vc->std & V4L2_STD_525_60; fmt = format_by_fourcc(f->fmt.pix.pixelformat); @@ -905,14 +842,13 @@ static int vidioc_try_fmt_vid_cap(struct file *file, void *priv, static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, struct v4l2_format *f) { - struct s2255_fh *fh = priv; - struct s2255_vc *vc = fh->vc; + struct s2255_vc *vc = video_drvdata(file); const struct s2255_fmt *fmt; - struct videobuf_queue *q = &fh->vb_vidq; + struct vb2_queue *q = &vc->vb_vidq; struct s2255_mode mode; int ret; - ret = vidioc_try_fmt_vid_cap(file, fh, f); + ret = vidioc_try_fmt_vid_cap(file, vc, f); if (ret < 0) return ret; @@ -922,24 +858,16 @@ static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, if (fmt == NULL) return -EINVAL; - mutex_lock(&q->vb_lock); - - if (videobuf_queue_is_busy(&fh->vb_vidq)) { + if (vb2_is_busy(q)) { dprintk(vc->dev, 1, "queue busy\n"); - ret = -EBUSY; - goto out_s_fmt; + return -EBUSY; } - if (res_locked(fh)) { - dprintk(vc->dev, 1, "%s: channel busy\n", __func__); - ret = -EBUSY; - goto out_s_fmt; - } mode = vc->mode; vc->fmt = fmt; vc->width = f->fmt.pix.width; vc->height = f->fmt.pix.height; - fh->vb_vidq.field = f->fmt.pix.field; + vc->field = f->fmt.pix.field; if (vc->width > norm_minw(vc)) { if (vc->height > norm_minh(vc)) { if (vc->cap_parm.capturemode & @@ -984,44 +912,9 @@ static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, mode.restart = 1; vc->mode = mode; (void) s2255_set_mode(vc, &mode); - ret = 0; -out_s_fmt: - mutex_unlock(&q->vb_lock); - return ret; -} - -static int vidioc_reqbufs(struct file *file, void *priv, - struct v4l2_requestbuffers *p) -{ - int rc; - struct s2255_fh *fh = priv; - rc = videobuf_reqbufs(&fh->vb_vidq, p); - return rc; -} - -static int vidioc_querybuf(struct file *file, void *priv, struct v4l2_buffer *p) -{ - int rc; - struct s2255_fh *fh = priv; - rc = videobuf_querybuf(&fh->vb_vidq, p); - return rc; -} - -static int vidioc_qbuf(struct file *file, void *priv, struct v4l2_buffer *p) -{ - int rc; - struct s2255_fh *fh = priv; - rc = videobuf_qbuf(&fh->vb_vidq, p); - return rc; + return 0; } -static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *p) -{ - int rc; - struct s2255_fh *fh = priv; - rc = videobuf_dqbuf(&fh->vb_vidq, p, file->f_flags & O_NONBLOCK); - return rc; -} /* write to the configuration pipe, synchronously */ static int s2255_write_config(struct usb_device *udev, unsigned char *pbuf, @@ -1199,24 +1092,11 @@ static int s2255_cmd_status(struct s2255_vc *vc, u32 *pstatus) return res; } -static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i) +static int start_streaming(struct vb2_queue *vq, unsigned int count) { - int res; - struct s2255_fh *fh = priv; - struct s2255_vc *vc = fh->vc; - struct s2255_dev *dev = vc->dev; + struct s2255_vc *vc = vb2_get_drv_priv(vq); int j; - dprintk(dev, 4, "%s\n", __func__); - if (i != V4L2_BUF_TYPE_VIDEO_CAPTURE) { - dev_err(&dev->udev->dev, "invalid fh type1\n"); - return -EINVAL; - } - - if (!res_get(fh)) { - s2255_dev_err(&dev->udev->dev, "stream busy\n"); - return -EBUSY; - } vc->last_frame = -1; vc->bad_payload = 0; vc->cur_frame = 0; @@ -1225,48 +1105,40 @@ static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i) vc->buffer.frame[j].ulState = S2255_READ_IDLE; vc->buffer.frame[j].cur_size = 0; } - res = videobuf_streamon(&fh->vb_vidq); - if (res != 0) { - res_free(fh); - return res; - } - res = s2255_start_acquire(vc); - if (res != 0) { - res_free(fh); - return res; - } - vc->b_acquire = 1; - return res; + return s2255_start_acquire(vc); } -static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i) +/* abort streaming and wait for last buffer */ +static int stop_streaming(struct vb2_queue *vq) { - struct s2255_fh *fh = priv; - struct s2255_vc *vc = fh->vc; - dprintk(vc->dev, 4, "%s\n, channel: %d", __func__, vc->idx); - - if (i != V4L2_BUF_TYPE_VIDEO_CAPTURE) - return -EINVAL; - s2255_stop_acquire(vc); - videobuf_streamoff(&fh->vb_vidq); - res_free(fh); + struct s2255_vc *vc = vb2_get_drv_priv(vq); + struct s2255_buffer *buf, *node; + unsigned long flags; + (void) s2255_stop_acquire(vc); + spin_lock_irqsave(&vc->qlock, flags); + list_for_each_entry_safe(buf, node, &vc->buf_list, list) { + list_del(&buf->list); + vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR); + dprintk(vc->dev, 2, "[%p/%d] done\n", + buf, buf->vb.v4l2_buf.index); + } + spin_unlock_irqrestore(&vc->qlock, flags); return 0; } static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id i) { - struct s2255_fh *fh = priv; + struct s2255_vc *vc = video_drvdata(file); struct s2255_mode mode; - struct videobuf_queue *q = &fh->vb_vidq; - struct s2255_vc *vc = fh->vc; - int ret = 0; + struct vb2_queue *q = &vc->vb_vidq; + + /* + * Changing the standard implies a format change, which is not allowed + * while buffers for use with streaming have already been allocated. + */ + if (vb2_is_busy(q)) + return -EBUSY; - mutex_lock(&q->vb_lock); - if (res_locked(fh)) { - dprintk(vc->dev, 1, "can't change standard after started\n"); - ret = -EBUSY; - goto out_s_std; - } mode = vc->mode; if (i & V4L2_STD_525_60) { dprintk(vc->dev, 4, "%s 60 Hz\n", __func__); @@ -1287,22 +1159,17 @@ static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id i) vc->width = LINE_SZ_4CIFS_PAL; vc->height = NUM_LINES_4CIFS_PAL * 2; } - } else { - ret = -EINVAL; - goto out_s_std; - } + } else + return -EINVAL; vc->std = i; if (mode.restart) s2255_set_mode(vc, &mode); -out_s_std: - mutex_unlock(&q->vb_lock); - return ret; + return 0; } static int vidioc_g_std(struct file *file, void *priv, v4l2_std_id *i) { - struct s2255_fh *fh = priv; - struct s2255_vc *vc = fh->vc; + struct s2255_vc *vc = video_drvdata(file); *i = vc->std; return 0; @@ -1318,8 +1185,7 @@ static int vidioc_g_std(struct file *file, void *priv, v4l2_std_id *i) static int vidioc_enum_input(struct file *file, void *priv, struct v4l2_input *inp) { - struct s2255_fh *fh = priv; - struct s2255_vc *vc = fh->vc; + struct s2255_vc *vc = video_drvdata(file); struct s2255_dev *dev = vc->dev; u32 status = 0; @@ -1404,8 +1270,7 @@ static int s2255_s_ctrl(struct v4l2_ctrl *ctrl) static int vidioc_g_jpegcomp(struct file *file, void *priv, struct v4l2_jpegcompression *jc) { - struct s2255_fh *fh = priv; - struct s2255_vc *vc = fh->vc; + struct s2255_vc *vc = video_drvdata(file); memset(jc, 0, sizeof(*jc)); jc->quality = vc->jpegqual; @@ -1416,8 +1281,8 @@ static int vidioc_g_jpegcomp(struct file *file, void *priv, static int vidioc_s_jpegcomp(struct file *file, void *priv, const struct v4l2_jpegcompression *jc) { - struct s2255_fh *fh = priv; - struct s2255_vc *vc = fh->vc; + struct s2255_vc *vc = video_drvdata(file); + if (jc->quality < 0 || jc->quality > 100) return -EINVAL; v4l2_ctrl_s_ctrl(vc->jpegqual_ctrl, jc->quality); @@ -1428,13 +1293,14 @@ static int vidioc_s_jpegcomp(struct file *file, void *priv, static int vidioc_g_parm(struct file *file, void *priv, struct v4l2_streamparm *sp) { - struct s2255_fh *fh = priv; __u32 def_num, def_dem; - struct s2255_vc *vc = fh->vc; + struct s2255_vc *vc = video_drvdata(file); + if (sp->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) return -EINVAL; sp->parm.capture.capability = V4L2_CAP_TIMEPERFRAME; sp->parm.capture.capturemode = vc->cap_parm.capturemode; + sp->parm.capture.readbuffers = S2255_MIN_BUFS; def_num = (vc->mode.format == FORMAT_NTSC) ? 1001 : 1000; def_dem = (vc->mode.format == FORMAT_NTSC) ? 30000 : 25000; sp->parm.capture.timeperframe.denominator = def_dem; @@ -1464,8 +1330,7 @@ static int vidioc_g_parm(struct file *file, void *priv, static int vidioc_s_parm(struct file *file, void *priv, struct v4l2_streamparm *sp) { - struct s2255_fh *fh = priv; - struct s2255_vc *vc = fh->vc; + struct s2255_vc *vc = video_drvdata(file); struct s2255_mode mode; int fdec = FDEC_1; __u32 def_num, def_dem; @@ -1473,8 +1338,8 @@ static int vidioc_s_parm(struct file *file, void *priv, return -EINVAL; mode = vc->mode; /* high quality capture mode requires a stream restart */ - if (vc->cap_parm.capturemode - != sp->parm.capture.capturemode && res_locked(fh)) + if ((vc->cap_parm.capturemode != sp->parm.capture.capturemode) + && vb2_is_streaming(&vc->vb_vidq)) return -EBUSY; def_num = (mode.format == FORMAT_NTSC) ? 1001 : 1000; def_dem = (mode.format == FORMAT_NTSC) ? 30000 : 25000; @@ -1494,6 +1359,7 @@ static int vidioc_s_parm(struct file *file, void *priv, } mode.fdec = fdec; sp->parm.capture.timeperframe.denominator = def_dem; + sp->parm.capture.readbuffers = S2255_MIN_BUFS; s2255_set_mode(vc, &mode); dprintk(vc->dev, 4, "%s capture mode, %d timeperframe %d/%d, fdec %d\n", __func__, @@ -1518,8 +1384,7 @@ static const struct v4l2_frmsize_discrete pal_sizes[] = { static int vidioc_enum_framesizes(struct file *file, void *priv, struct v4l2_frmsizeenum *fe) { - struct s2255_fh *fh = priv; - struct s2255_vc *vc = fh->vc; + struct s2255_vc *vc = video_drvdata(file); int is_ntsc = vc->std & V4L2_STD_525_60; const struct s2255_fmt *fmt; @@ -1537,8 +1402,7 @@ static int vidioc_enum_framesizes(struct file *file, void *priv, static int vidioc_enum_frameintervals(struct file *file, void *priv, struct v4l2_frmivalenum *fe) { - struct s2255_fh *fh = priv; - struct s2255_vc *vc = fh->vc; + struct s2255_vc *vc = video_drvdata(file); const struct s2255_fmt *fmt; const struct v4l2_frmsize_discrete *sizes; int is_ntsc = vc->std & V4L2_STD_525_60; @@ -1570,16 +1434,18 @@ static int vidioc_enum_frameintervals(struct file *file, void *priv, return 0; } -static int __s2255_open(struct file *file) +static int s2255_open(struct file *file) { - struct video_device *vdev = video_devdata(file); struct s2255_vc *vc = video_drvdata(file); - struct s2255_dev *dev = to_s2255_dev(vdev->v4l2_dev); - struct s2255_fh *fh; - enum v4l2_buf_type type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + struct s2255_dev *dev = vc->dev; int state; - dprintk(dev, 1, "s2255: open called (dev=%s)\n", - video_device_node_name(vdev)); + int rc = 0; + + rc = v4l2_fh_open(file); + if (rc != 0) + return rc; + + dprintk(dev, 1, "s2255: %s\n", __func__); state = atomic_read(&dev->fw_data->fw_state); switch (state) { case S2255_FW_DISCONNECTING: @@ -1641,61 +1507,15 @@ static int __s2255_open(struct file *file) pr_info("%s: unknown state\n", __func__); return -EFAULT; } - /* allocate + initialize per filehandle data */ - fh = kzalloc(sizeof(*fh), GFP_KERNEL); - if (NULL == fh) - return -ENOMEM; - v4l2_fh_init(&fh->fh, vdev); - v4l2_fh_add(&fh->fh); - file->private_data = &fh->fh; - fh->vc = vc; if (!vc->configured) { /* configure channel to default state */ vc->fmt = &formats[0]; s2255_set_mode(vc, &vc->mode); vc->configured = 1; } - dprintk(dev, 1, "%s: dev=%s type=%s\n", __func__, - video_device_node_name(vdev), v4l2_type_names[type]); - dprintk(dev, 2, "%s: fh=0x%08lx, dev=0x%08lx\n", __func__, - (unsigned long)fh, (unsigned long)dev); - dprintk(dev, 4, "%s: list_empty active=%d\n", __func__, - list_empty(&vc->buf_list)); - videobuf_queue_vmalloc_init(&fh->vb_vidq, &s2255_video_qops, - NULL, &dev->slock, - V4L2_BUF_TYPE_VIDEO_CAPTURE, - V4L2_FIELD_INTERLACED, - sizeof(struct s2255_buffer), - fh, vdev->lock); return 0; } -static int s2255_open(struct file *file) -{ - struct video_device *vdev = video_devdata(file); - int ret; - - if (mutex_lock_interruptible(vdev->lock)) - return -ERESTARTSYS; - ret = __s2255_open(file); - mutex_unlock(vdev->lock); - return ret; -} - -static unsigned int s2255_poll(struct file *file, - struct poll_table_struct *wait) -{ - struct s2255_fh *fh = file->private_data; - struct s2255_dev *dev = fh->vc->dev; - int rc = v4l2_ctrl_poll(file, wait); - - dprintk(dev, 100, "%s\n", __func__); - mutex_lock(&dev->lock); - rc |= videobuf_poll_stream(file, &fh->vb_vidq, wait); - mutex_unlock(&dev->lock); - return rc; -} - static void s2255_destroy(struct s2255_dev *dev) { dprintk(dev, 1, "%s", __func__); @@ -1720,59 +1540,14 @@ static void s2255_destroy(struct s2255_dev *dev) kfree(dev); } -static int s2255_release(struct file *file) -{ - struct s2255_fh *fh = file->private_data; - struct video_device *vdev = video_devdata(file); - struct s2255_vc *vc = fh->vc; - struct s2255_dev *dev = vc->dev; - - if (!dev) - return -ENODEV; - mutex_lock(&dev->lock); - /* turn off stream */ - if (res_check(fh)) { - if (vc->b_acquire) - s2255_stop_acquire(vc); - videobuf_streamoff(&fh->vb_vidq); - res_free(fh); - } - videobuf_mmap_free(&fh->vb_vidq); - mutex_unlock(&dev->lock); - dprintk(dev, 1, "%s[%s]\n", __func__, video_device_node_name(vdev)); - v4l2_fh_del(&fh->fh); - v4l2_fh_exit(&fh->fh); - kfree(fh); - return 0; -} - -static int s2255_mmap_v4l(struct file *file, struct vm_area_struct *vma) -{ - struct s2255_fh *fh = file->private_data; - struct s2255_dev *dev; - int ret; - - if (!fh) - return -ENODEV; - dev = fh->vc->dev; - dprintk(dev, 4, "%s, vma=0x%08lx\n", __func__, (unsigned long)vma); - if (mutex_lock_interruptible(&dev->lock)) - return -ERESTARTSYS; - ret = videobuf_mmap_mapper(&fh->vb_vidq, vma); - mutex_unlock(&dev->lock); - dprintk(dev, 4, "%s vma start=0x%08lx, size=%ld, ret=%d\n", __func__, - (unsigned long)vma->vm_start, - (unsigned long)vma->vm_end - (unsigned long)vma->vm_start, ret); - return ret; -} - static const struct v4l2_file_operations s2255_fops_v4l = { .owner = THIS_MODULE, .open = s2255_open, - .release = s2255_release, - .poll = s2255_poll, + .release = vb2_fop_release, + .poll = vb2_fop_poll, .unlocked_ioctl = video_ioctl2, /* V4L2 ioctl handler */ - .mmap = s2255_mmap_v4l, + .mmap = vb2_fop_mmap, + .read = vb2_fop_read, }; static const struct v4l2_ioctl_ops s2255_ioctl_ops = { @@ -1781,17 +1556,17 @@ static const struct v4l2_ioctl_ops s2255_ioctl_ops = { .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap, .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap, .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap, - .vidioc_reqbufs = vidioc_reqbufs, - .vidioc_querybuf = vidioc_querybuf, - .vidioc_qbuf = vidioc_qbuf, - .vidioc_dqbuf = vidioc_dqbuf, + .vidioc_reqbufs = vb2_ioctl_reqbufs, + .vidioc_querybuf = vb2_ioctl_querybuf, + .vidioc_qbuf = vb2_ioctl_qbuf, + .vidioc_dqbuf = vb2_ioctl_dqbuf, .vidioc_s_std = vidioc_s_std, .vidioc_g_std = vidioc_g_std, .vidioc_enum_input = vidioc_enum_input, .vidioc_g_input = vidioc_g_input, .vidioc_s_input = vidioc_s_input, - .vidioc_streamon = vidioc_streamon, - .vidioc_streamoff = vidioc_streamoff, + .vidioc_streamon = vb2_ioctl_streamon, + .vidioc_streamoff = vb2_ioctl_streamoff, .vidioc_s_jpegcomp = vidioc_s_jpegcomp, .vidioc_g_jpegcomp = vidioc_g_jpegcomp, .vidioc_s_parm = vidioc_s_parm, @@ -1847,6 +1622,8 @@ static int s2255_probe_v4l(struct s2255_dev *dev) int i; int cur_nr = video_nr; struct s2255_vc *vc; + struct vb2_queue *q; + ret = v4l2_device_register(&dev->interface->dev, &dev->v4l2_dev); if (ret) return ret; @@ -1879,8 +1656,24 @@ static int s2255_probe_v4l(struct s2255_dev *dev) dev_err(&dev->udev->dev, "couldn't register control\n"); break; } - /* register 4 video devices */ + q = &vc->vb_vidq; + q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + q->io_modes = VB2_MMAP | VB2_READ | VB2_USERPTR; + q->drv_priv = vc; + q->lock = &vc->vb_lock; + q->buf_struct_size = sizeof(struct s2255_buffer); + q->mem_ops = &vb2_vmalloc_memops; + q->ops = &s2255_video_qops; + q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + ret = vb2_queue_init(q); + if (ret != 0) { + dev_err(&dev->udev->dev, + "%s vb2_queue_init 0x%x\n", __func__, ret); + break; + } + /* register video devices */ vc->vdev = template; + vc->vdev.queue = q; vc->vdev.ctrl_handler = &vc->hdl; vc->vdev.lock = &dev->lock; vc->vdev.v4l2_dev = &dev->v4l2_dev; @@ -2029,7 +1822,7 @@ static int save_frame(struct s2255_dev *dev, struct s2255_pipeinfo *pipe_info) idx = vc->cur_frame; frm = &vc->buffer.frame[idx]; /* search done. now find out if should be acquiring on this channel */ - if (!vc->b_acquire) { + if (!vb2_is_streaming(&vc->vb_vidq)) { /* we found a frame, but this channel is turned off */ frm->ulState = S2255_READ_IDLE; return -EINVAL; @@ -2073,7 +1866,7 @@ static int save_frame(struct s2255_dev *dev, struct s2255_pipeinfo *pipe_info) (vc->cur_frame == vc->buffer.dwFrames)) vc->cur_frame = 0; /* frame ready */ - if (vc->b_acquire) + if (vb2_is_streaming(&vc->vb_vidq)) s2255_got_frame(vc, vc->jpg_size); vc->frame_count++; frm->ulState = S2255_READ_IDLE; @@ -2222,7 +2015,6 @@ static int s2255_board_init(struct s2255_dev *dev) for (j = 0; j < MAX_CHANNELS; j++) { struct s2255_vc *vc = &dev->vc[j]; - vc->b_acquire = 0; vc->mode = mode_def; if (dev->pid == 0x2257 && j > 1) vc->mode.color |= (1 << 16); @@ -2249,7 +2041,7 @@ static int s2255_board_shutdown(struct s2255_dev *dev) dprintk(dev, 1, "%s: dev: %p", __func__, dev); for (i = 0; i < MAX_CHANNELS; i++) { - if (dev->vc[i].b_acquire) + if (vb2_is_streaming(&dev->vc[i].vb_vidq)) s2255_stop_acquire(&dev->vc[i]); } s2255_stop_readpipe(dev); @@ -2397,7 +2189,6 @@ static int s2255_stop_acquire(struct s2255_vc *vc) if (res != 0) dev_err(&dev->udev->dev, "CMD_STOP error\n"); - vc->b_acquire = 0; dprintk(dev, 4, "%s: chn %d, res %d\n", __func__, vc->idx, res); mutex_unlock(&dev->cmdlock); return res; @@ -2503,6 +2294,8 @@ static int s2255_probe(struct usb_interface *interface, vc->dev = dev; init_waitqueue_head(&vc->wait_setmode); init_waitqueue_head(&vc->wait_vidstatus); + spin_lock_init(&vc->qlock); + mutex_init(&vc->vb_lock); } dev->fw_data->fw_urb = usb_alloc_urb(0, GFP_KERNEL); @@ -2548,7 +2341,6 @@ static int s2255_probe(struct usb_interface *interface, retval = s2255_board_init(dev); if (retval) goto errorBOARDINIT; - spin_lock_init(&dev->slock); s2255_fwload_start(dev, 0); /* loads v4l specific */ retval = s2255_probe_v4l(dev); -- cgit v1.1 From 840d94eacea399b3bfe2ebcbf75e0dec202cd922 Mon Sep 17 00:00:00 2001 From: Antonio Ospite Date: Mon, 30 Dec 2013 13:41:45 -0300 Subject: [media] gspca_kinect: fix kinect_read() error path The error checking code relative to the invocations of kinect_read() does not return the actual return code of the function just called, it returns "res" which still contains the value of the last invocation of a previous kinect_write(). Return the proper value, and while at it also report with -EREMOTEIO the case of a partial transfer. Reported-by: Julia Lawall Signed-off-by: Antonio Ospite Signed-off-by: Hans de Goede Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/gspca/kinect.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/usb/gspca/kinect.c b/drivers/media/usb/gspca/kinect.c index 3773a8a..48084736 100644 --- a/drivers/media/usb/gspca/kinect.c +++ b/drivers/media/usb/gspca/kinect.c @@ -158,7 +158,7 @@ static int send_cmd(struct gspca_dev *gspca_dev, uint16_t cmd, void *cmdbuf, PDEBUG(D_USBO, "Control reply: %d", res); if (actual_len < sizeof(*rhdr)) { pr_err("send_cmd: Input control transfer failed (%d)\n", res); - return res; + return actual_len < 0 ? actual_len : -EREMOTEIO; } actual_len -= sizeof(*rhdr); -- cgit v1.1 From ccf78070d7ec8ff0231c5c2b1b16c78e10c768fc Mon Sep 17 00:00:00 2001 From: Antonio Ospite Date: Mon, 30 Dec 2013 13:41:46 -0300 Subject: [media] gspca_kinect: fix messages about kinect_read() return value Messages relative to kinect_read() are printing "res" which contains the return value of a previous kinect_write(). Print the correct value in the messages. Cc: Julia Lawall Signed-off-by: Antonio Ospite Signed-off-by: Hans de Goede Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/gspca/kinect.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/media/usb/gspca/kinect.c b/drivers/media/usb/gspca/kinect.c index 48084736..081f051 100644 --- a/drivers/media/usb/gspca/kinect.c +++ b/drivers/media/usb/gspca/kinect.c @@ -155,9 +155,10 @@ static int send_cmd(struct gspca_dev *gspca_dev, uint16_t cmd, void *cmdbuf, do { actual_len = kinect_read(udev, ibuf, 0x200); } while (actual_len == 0); - PDEBUG(D_USBO, "Control reply: %d", res); + PDEBUG(D_USBO, "Control reply: %d", actual_len); if (actual_len < sizeof(*rhdr)) { - pr_err("send_cmd: Input control transfer failed (%d)\n", res); + pr_err("send_cmd: Input control transfer failed (%d)\n", + actual_len); return actual_len < 0 ? actual_len : -EREMOTEIO; } actual_len -= sizeof(*rhdr); -- cgit v1.1 From 61f0319193c44adbbada920162d880b1fdb3aeb3 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Sat, 1 Feb 2014 15:26:00 -0300 Subject: [media] media: gspca: sn9c20x: add ID for Genius Look 1320 V2 Signed-off-by: Wolfram Sang Signed-off-by: Hans de Goede Cc: stable@vger.kernel.org Signed-off-by: Mauro Carvalho Chehab --- Documentation/video4linux/gspca.txt | 1 + drivers/media/usb/gspca/sn9c20x.c | 1 + 2 files changed, 2 insertions(+) diff --git a/Documentation/video4linux/gspca.txt b/Documentation/video4linux/gspca.txt index 1e6b653..d2ba80b 100644 --- a/Documentation/video4linux/gspca.txt +++ b/Documentation/video4linux/gspca.txt @@ -55,6 +55,7 @@ zc3xx 0458:700f Genius VideoCam Web V2 sonixj 0458:7025 Genius Eye 311Q sn9c20x 0458:7029 Genius Look 320s sonixj 0458:702e Genius Slim 310 NB +sn9c20x 0458:7045 Genius Look 1320 V2 sn9c20x 0458:704a Genius Slim 1320 sn9c20x 0458:704c Genius i-Look 1321 sn9c20x 045e:00f4 LifeCam VX-6000 (SN9C20x + OV9650) diff --git a/drivers/media/usb/gspca/sn9c20x.c b/drivers/media/usb/gspca/sn9c20x.c index 2a38621..41a9a89 100644 --- a/drivers/media/usb/gspca/sn9c20x.c +++ b/drivers/media/usb/gspca/sn9c20x.c @@ -2359,6 +2359,7 @@ static const struct usb_device_id device_table[] = { {USB_DEVICE(0x045e, 0x00f4), SN9C20X(OV9650, 0x30, 0)}, {USB_DEVICE(0x145f, 0x013d), SN9C20X(OV7660, 0x21, 0)}, {USB_DEVICE(0x0458, 0x7029), SN9C20X(HV7131R, 0x11, 0)}, + {USB_DEVICE(0x0458, 0x7045), SN9C20X(MT9M112, 0x5d, LED_REVERSE)}, {USB_DEVICE(0x0458, 0x704a), SN9C20X(MT9M112, 0x5d, 0)}, {USB_DEVICE(0x0458, 0x704c), SN9C20X(MT9M112, 0x5d, 0)}, {USB_DEVICE(0xa168, 0x0610), SN9C20X(HV7131R, 0x11, 0)}, -- cgit v1.1 From ce4452e65dad27295f7ceb553727b55e2abbdd90 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Tue, 18 Feb 2014 12:00:45 -0300 Subject: [media] gspca_stv06xx: remove an unneeded check "err" is zero here so we don't need to check again. Signed-off-by: Dan Carpenter Signed-off-by: Hans de Goede Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/gspca/stv06xx/stv06xx_vv6410.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/usb/gspca/stv06xx/stv06xx_vv6410.c b/drivers/media/usb/gspca/stv06xx/stv06xx_vv6410.c index bf3e5c3..e60cbb3 100644 --- a/drivers/media/usb/gspca/stv06xx/stv06xx_vv6410.c +++ b/drivers/media/usb/gspca/stv06xx/stv06xx_vv6410.c @@ -178,7 +178,7 @@ static int vv6410_stop(struct sd *sd) PDEBUG(D_STREAM, "Halting stream"); - return (err < 0) ? err : 0; + return 0; } static int vv6410_dump(struct sd *sd) -- cgit v1.1 From e15fd24495dedb50068e649173ba65a70af63d16 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sun, 23 Feb 2014 19:01:58 -0300 Subject: [media] gspca_topro: Add a couple of missing length check in the packet parsing code Reported-by: Dan Carpenter Signed-off-by: Hans de Goede Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/gspca/topro.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/media/usb/gspca/topro.c b/drivers/media/usb/gspca/topro.c index 640c2fe..5fcd1ee 100644 --- a/drivers/media/usb/gspca/topro.c +++ b/drivers/media/usb/gspca/topro.c @@ -4631,8 +4631,16 @@ static void sd_pkt_scan(struct gspca_dev *gspca_dev, } data++; len--; + if (len < 2) { + gspca_dev->last_packet_type = DISCARD_PACKET; + return; + } if (*data == 0xff && data[1] == 0xd8) { /*fixme: there may be information in the 4 high bits*/ + if (len < 7) { + gspca_dev->last_packet_type = DISCARD_PACKET; + return; + } if ((data[6] & 0x0f) != sd->quality) set_dqt(gspca_dev, data[6] & 0x0f); gspca_frame_add(gspca_dev, FIRST_PACKET, @@ -4672,7 +4680,7 @@ static void sd_pkt_scan(struct gspca_dev *gspca_dev, gspca_dev->last_packet_type = DISCARD_PACKET; break; case 0xcc: - if (data[1] != 0xff || data[2] != 0xd8) + if (len >= 3 && (data[1] != 0xff || data[2] != 0xd8)) gspca_frame_add(gspca_dev, INTER_PACKET, data + 1, len - 1); else -- cgit v1.1 From ac298ccdde4fe9b0a966e548a232ff4e8a6b8a31 Mon Sep 17 00:00:00 2001 From: Jan Vcelak Date: Wed, 26 Feb 2014 15:33:39 -0300 Subject: [media] rtl28xxu: add USB ID for Genius TVGo DVB-T03 0458:707f KYE Systems Corp. (Mouse Systems) TVGo DVB-T03 [RTL2832] The USB dongle uses RTL2832U demodulator and FC0012 tuner. Signed-off-by: Jan Vcelak Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/dvb-usb-v2/rtl28xxu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/media/usb/dvb-usb-v2/rtl28xxu.c b/drivers/media/usb/dvb-usb-v2/rtl28xxu.c index 8e61523..44f7607 100644 --- a/drivers/media/usb/dvb-usb-v2/rtl28xxu.c +++ b/drivers/media/usb/dvb-usb-v2/rtl28xxu.c @@ -1431,6 +1431,8 @@ static const struct usb_device_id rtl28xxu_id_table[] = { &rtl2832u_props, "Leadtek WinFast DTV Dongle mini", NULL) }, { DVB_USB_DEVICE(USB_VID_GTEK, USB_PID_CPYTO_REDI_PC50A, &rtl2832u_props, "Crypto ReDi PC 50 A", NULL) }, + { DVB_USB_DEVICE(USB_VID_KYE, 0x707f, + &rtl2832u_props, "Genius TVGo DVB-T03", NULL) }, { DVB_USB_DEVICE(USB_VID_HANFTEK, 0x0131, &rtl2832u_props, "Astrometa DVB-T2", NULL) }, -- cgit v1.1 From 60aa4c6fa5723af72cff154a5cd33ac4995d1e0a Mon Sep 17 00:00:00 2001 From: Jan Vcelak Date: Wed, 26 Feb 2014 15:33:40 -0300 Subject: [media] rtl28xxu: add chipset version comments into device list Signed-off-by: Jan Vcelak Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/dvb-usb-v2/rtl28xxu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/media/usb/dvb-usb-v2/rtl28xxu.c b/drivers/media/usb/dvb-usb-v2/rtl28xxu.c index 44f7607..a331af1 100644 --- a/drivers/media/usb/dvb-usb-v2/rtl28xxu.c +++ b/drivers/media/usb/dvb-usb-v2/rtl28xxu.c @@ -1382,6 +1382,7 @@ static const struct dvb_usb_device_properties rtl2832u_props = { }; static const struct usb_device_id rtl28xxu_id_table[] = { + /* RTL2831U devices: */ { DVB_USB_DEVICE(USB_VID_REALTEK, USB_PID_REALTEK_RTL2831U, &rtl2831u_props, "Realtek RTL2831U reference design", NULL) }, { DVB_USB_DEVICE(USB_VID_WIDEVIEW, USB_PID_FREECOM_DVBT, @@ -1389,6 +1390,7 @@ static const struct usb_device_id rtl28xxu_id_table[] = { { DVB_USB_DEVICE(USB_VID_WIDEVIEW, USB_PID_FREECOM_DVBT_2, &rtl2831u_props, "Freecom USB2.0 DVB-T", NULL) }, + /* RTL2832U devices: */ { DVB_USB_DEVICE(USB_VID_REALTEK, 0x2832, &rtl2832u_props, "Realtek RTL2832U reference design", NULL) }, { DVB_USB_DEVICE(USB_VID_REALTEK, 0x2838, @@ -1434,6 +1436,7 @@ static const struct usb_device_id rtl28xxu_id_table[] = { { DVB_USB_DEVICE(USB_VID_KYE, 0x707f, &rtl2832u_props, "Genius TVGo DVB-T03", NULL) }, + /* RTL2832P devices: */ { DVB_USB_DEVICE(USB_VID_HANFTEK, 0x0131, &rtl2832u_props, "Astrometa DVB-T2", NULL) }, { } -- cgit v1.1 From bf0bedd371574837caaeeaa01f674cdf90508275 Mon Sep 17 00:00:00 2001 From: Amit Grover Date: Tue, 4 Feb 2014 06:59:58 -0300 Subject: [media] v4l2: Add settings for Horizontal and Vertical MV Search Range Adding V4L2 controls for horizontal and vertical search range in pixels for motion estimation module in video encoder. Signed-off-by: Swami Nathan Signed-off-by: Amit Grover Acked-by: Hans Verkuil Acked-by: Lad, Prabhakar Signed-off-by: Kamil Debski Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/v4l/controls.xml | 20 ++++++++++++++++++++ drivers/media/v4l2-core/v4l2-ctrls.c | 6 ++++++ include/uapi/linux/v4l2-controls.h | 2 ++ 3 files changed, 28 insertions(+) diff --git a/Documentation/DocBook/media/v4l/controls.xml b/Documentation/DocBook/media/v4l/controls.xml index a5a3188..0e1770c 100644 --- a/Documentation/DocBook/media/v4l/controls.xml +++ b/Documentation/DocBook/media/v4l/controls.xml @@ -2258,6 +2258,26 @@ Applicable to the MPEG1, MPEG2, MPEG4 encoders. VBV buffer control. + + + V4L2_CID_MPEG_VIDEO_MV_H_SEARCH_RANGE  + integer + + Horizontal search range defines maximum horizontal search area in pixels +to search and match for the present Macroblock (MB) in the reference picture. This V4L2 control macro is used to set +horizontal search range for motion estimation module in video encoder. + + + + + V4L2_CID_MPEG_VIDEO_MV_V_SEARCH_RANGE  + integer + + Vertical search range defines maximum vertical search area in pixels +to search and match for the present Macroblock (MB) in the reference picture. This V4L2 control macro is used to set +vertical search range for motion estimation module in video encoder. + + V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE  diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c index 6ff002b..e9e12c4 100644 --- a/drivers/media/v4l2-core/v4l2-ctrls.c +++ b/drivers/media/v4l2-core/v4l2-ctrls.c @@ -735,6 +735,8 @@ const char *v4l2_ctrl_get_name(u32 id) case V4L2_CID_MPEG_VIDEO_DEC_PTS: return "Video Decoder PTS"; case V4L2_CID_MPEG_VIDEO_DEC_FRAME: return "Video Decoder Frame Count"; case V4L2_CID_MPEG_VIDEO_VBV_DELAY: return "Initial Delay for VBV Control"; + case V4L2_CID_MPEG_VIDEO_MV_H_SEARCH_RANGE: return "Horizontal MV Search Range"; + case V4L2_CID_MPEG_VIDEO_MV_V_SEARCH_RANGE: return "Vertical MV Search Range"; case V4L2_CID_MPEG_VIDEO_REPEAT_SEQ_HEADER: return "Repeat Sequence Header"; /* VPX controls */ @@ -910,6 +912,10 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, *min = 0; *max = *step = 1; break; + case V4L2_CID_MPEG_VIDEO_MV_H_SEARCH_RANGE: + case V4L2_CID_MPEG_VIDEO_MV_V_SEARCH_RANGE: + *type = V4L2_CTRL_TYPE_INTEGER; + break; case V4L2_CID_PAN_RESET: case V4L2_CID_TILT_RESET: case V4L2_CID_FLASH_STROBE: diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h index 2cbe605..cda6fa0 100644 --- a/include/uapi/linux/v4l2-controls.h +++ b/include/uapi/linux/v4l2-controls.h @@ -376,6 +376,8 @@ enum v4l2_mpeg_video_multi_slice_mode { #define V4L2_CID_MPEG_VIDEO_DEC_FRAME (V4L2_CID_MPEG_BASE+224) #define V4L2_CID_MPEG_VIDEO_VBV_DELAY (V4L2_CID_MPEG_BASE+225) #define V4L2_CID_MPEG_VIDEO_REPEAT_SEQ_HEADER (V4L2_CID_MPEG_BASE+226) +#define V4L2_CID_MPEG_VIDEO_MV_H_SEARCH_RANGE (V4L2_CID_MPEG_BASE+227) +#define V4L2_CID_MPEG_VIDEO_MV_V_SEARCH_RANGE (V4L2_CID_MPEG_BASE+228) #define V4L2_CID_MPEG_VIDEO_H263_I_FRAME_QP (V4L2_CID_MPEG_BASE+300) #define V4L2_CID_MPEG_VIDEO_H263_P_FRAME_QP (V4L2_CID_MPEG_BASE+301) -- cgit v1.1 From a378a320aa5bfeacf5bade374d126e4a8d01b115 Mon Sep 17 00:00:00 2001 From: Amit Grover Date: Tue, 4 Feb 2014 06:59:59 -0300 Subject: [media] s5p-mfc: Add Horizontal and Vertical MV Search Range This patch adds Controls to set Horizontal and Vertical search range for Motion Estimation block for Samsung MFC video Encoders. Signed-off-by: Swami Nathan Signed-off-by: Amit Grover Signed-off-by: Kamil Debski Signed-off-by: Mauro Carvalho Chehab --- drivers/media/platform/s5p-mfc/regs-mfc-v6.h | 1 + drivers/media/platform/s5p-mfc/s5p_mfc_common.h | 2 ++ drivers/media/platform/s5p-mfc/s5p_mfc_enc.c | 24 ++++++++++++++++++++++++ drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c | 8 ++------ 4 files changed, 29 insertions(+), 6 deletions(-) diff --git a/drivers/media/platform/s5p-mfc/regs-mfc-v6.h b/drivers/media/platform/s5p-mfc/regs-mfc-v6.h index 2398cdf..8d0b686 100644 --- a/drivers/media/platform/s5p-mfc/regs-mfc-v6.h +++ b/drivers/media/platform/s5p-mfc/regs-mfc-v6.h @@ -229,6 +229,7 @@ #define S5P_FIMV_E_PADDING_CTRL_V6 0xf7a4 #define S5P_FIMV_E_MV_HOR_RANGE_V6 0xf7ac #define S5P_FIMV_E_MV_VER_RANGE_V6 0xf7b0 +#define S5P_FIMV_E_MV_RANGE_V6_MASK 0x3fff #define S5P_FIMV_E_VBV_BUFFER_SIZE_V6 0xf84c #define S5P_FIMV_E_VBV_INIT_DELAY_V6 0xf850 diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_common.h b/drivers/media/platform/s5p-mfc/s5p_mfc_common.h index f723f1f..5c28cc3 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc_common.h +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_common.h @@ -426,6 +426,8 @@ struct s5p_mfc_vp8_enc_params { struct s5p_mfc_enc_params { u16 width; u16 height; + u32 mv_h_range; + u32 mv_v_range; u16 gop_size; enum v4l2_mpeg_video_multi_slice_mode slice_mode; diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c b/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c index 91b6e02..df83cd1 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c @@ -208,6 +208,24 @@ static struct mfc_control controls[] = { .default_value = 0, }, { + .id = V4L2_CID_MPEG_VIDEO_MV_H_SEARCH_RANGE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Horizontal MV Search Range", + .minimum = 16, + .maximum = 128, + .step = 16, + .default_value = 32, + }, + { + .id = V4L2_CID_MPEG_VIDEO_MV_V_SEARCH_RANGE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Vertical MV Search Range", + .minimum = 16, + .maximum = 128, + .step = 16, + .default_value = 32, + }, + { .id = V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE, .type = V4L2_CTRL_TYPE_INTEGER, .minimum = 0, @@ -1417,6 +1435,12 @@ static int s5p_mfc_enc_s_ctrl(struct v4l2_ctrl *ctrl) case V4L2_CID_MPEG_VIDEO_VBV_SIZE: p->vbv_size = ctrl->val; break; + case V4L2_CID_MPEG_VIDEO_MV_H_SEARCH_RANGE: + p->mv_h_range = ctrl->val; + break; + case V4L2_CID_MPEG_VIDEO_MV_V_SEARCH_RANGE: + p->mv_v_range = ctrl->val; + break; case V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE: p->codec.h264.cpb_size = ctrl->val; break; diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c index f6ff2db..f64621a 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c @@ -727,14 +727,10 @@ static int s5p_mfc_set_enc_params(struct s5p_mfc_ctx *ctx) WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6); /* setting for MV range [16, 256] */ - reg = 0; - reg &= ~(0x3FFF); - reg = 256; + reg = (p->mv_h_range & S5P_FIMV_E_MV_RANGE_V6_MASK); WRITEL(reg, S5P_FIMV_E_MV_HOR_RANGE_V6); - reg = 0; - reg &= ~(0x3FFF); - reg = 256; + reg = (p->mv_v_range & S5P_FIMV_E_MV_RANGE_V6_MASK); WRITEL(reg, S5P_FIMV_E_MV_VER_RANGE_V6); WRITEL(0x0, S5P_FIMV_E_FRAME_INSERTION_V6); -- cgit v1.1 From 3c8023a782964c72574ad8268ba0ea4e2d9772fc Mon Sep 17 00:00:00 2001 From: Malcolm Priestley Date: Tue, 25 Feb 2014 23:05:39 -0300 Subject: [media] m88rs2000: add caps FE_CAN_INVERSION_AUTO The m88rs2000 frontend is always auto inversion. Signed-off-by: Malcolm Priestley Cc: stable@vger.kernel.org Signed-off-by: Michael Krufky Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/m88rs2000.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/dvb-frontends/m88rs2000.c b/drivers/media/dvb-frontends/m88rs2000.c index b235146..ee2fec8 100644 --- a/drivers/media/dvb-frontends/m88rs2000.c +++ b/drivers/media/dvb-frontends/m88rs2000.c @@ -746,7 +746,7 @@ static struct dvb_frontend_ops m88rs2000_ops = { .symbol_rate_tolerance = 500, /* ppm */ .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | - FE_CAN_QPSK | + FE_CAN_QPSK | FE_CAN_INVERSION_AUTO | FE_CAN_FEC_AUTO }, -- cgit v1.1 From 8272d0a0c0d374a01721e579df6e8add5577132b Mon Sep 17 00:00:00 2001 From: Malcolm Priestley Date: Tue, 25 Feb 2014 23:11:34 -0300 Subject: [media] m88rs2000: prevent frontend crash on continuous transponder scans Add m88rs2000_get_tune_settings, min delay of 2000 ms on symbol rate more than 3000000 and delay of 3000ms less than this. Adding min delay prevents crashing the frontend on continuous transponder scans. Other dvb_frontend_tune_settings remain as default. This makes very little time difference to good channel scans, but slows down the set frontend where lock can never be achieved i.e. DVB-S2. Signed-off-by: Malcolm Priestley Cc: stable@vger.kernel.org Signed-off-by: Michael Krufky Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/m88rs2000.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/media/dvb-frontends/m88rs2000.c b/drivers/media/dvb-frontends/m88rs2000.c index ee2fec8..32cffca 100644 --- a/drivers/media/dvb-frontends/m88rs2000.c +++ b/drivers/media/dvb-frontends/m88rs2000.c @@ -715,6 +715,22 @@ static int m88rs2000_get_frontend(struct dvb_frontend *fe) return 0; } +static int m88rs2000_get_tune_settings(struct dvb_frontend *fe, + struct dvb_frontend_tune_settings *tune) +{ + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + + if (c->symbol_rate > 3000000) + tune->min_delay_ms = 2000; + else + tune->min_delay_ms = 3000; + + tune->step_size = c->symbol_rate / 16000; + tune->max_drift = c->symbol_rate / 2000; + + return 0; +} + static int m88rs2000_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) { struct m88rs2000_state *state = fe->demodulator_priv; @@ -766,6 +782,7 @@ static struct dvb_frontend_ops m88rs2000_ops = { .set_frontend = m88rs2000_set_frontend, .get_frontend = m88rs2000_get_frontend, + .get_tune_settings = m88rs2000_get_tune_settings, }; struct dvb_frontend *m88rs2000_attach(const struct m88rs2000_config *config, -- cgit v1.1 From c6aa852ae0c265da2f7dd84f5d864d55415e37c9 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Tue, 25 Feb 2014 23:26:41 -0300 Subject: [media] stv0900: remove an unneeded check No need to check lock twice here. Signed-off-by: Dan Carpenter Signed-off-by: Michael Krufky Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/stv0900_sw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/dvb-frontends/stv0900_sw.c b/drivers/media/dvb-frontends/stv0900_sw.c index 0a40edf..4ce1d26 100644 --- a/drivers/media/dvb-frontends/stv0900_sw.c +++ b/drivers/media/dvb-frontends/stv0900_sw.c @@ -1081,7 +1081,7 @@ static int stv0900_wait_for_lock(struct stv0900_internal *intp, lock = stv0900_get_demod_lock(intp, demod, dmd_timeout); if (lock) - lock = lock && stv0900_get_fec_lock(intp, demod, fec_timeout); + lock = stv0900_get_fec_lock(intp, demod, fec_timeout); if (lock) { lock = 0; -- cgit v1.1 From 7e6bd12fb77b0067df13fb3ba3fadbdff2945396 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Tue, 25 Feb 2014 23:41:14 -0300 Subject: [media] stb6100: fix buffer length check in stb6100_write_reg_range() We are checking sizeof() the wrong variable! Signed-off-by: Alexander Shiyan Signed-off-by: Michael Krufky Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/stb6100.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/dvb-frontends/stb6100.c b/drivers/media/dvb-frontends/stb6100.c index cea175d..4ef8a5c 100644 --- a/drivers/media/dvb-frontends/stb6100.c +++ b/drivers/media/dvb-frontends/stb6100.c @@ -193,7 +193,7 @@ static int stb6100_write_reg_range(struct stb6100_state *state, u8 buf[], int st .len = len + 1 }; - if (1 + len > sizeof(buf)) { + if (1 + len > sizeof(cmdbuf)) { printk(KERN_WARNING "%s: i2c wr: len=%d is too big!\n", KBUILD_MODNAME, len); -- cgit v1.1 From b59de95bed526467f21c9978460cb15952b462e8 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Thu, 27 Feb 2014 23:04:08 -0300 Subject: [media] ds3000: fix reading array out of bound in ds3000_read_snr An attempt was made to read dvbs2_snr_tab[80], though dvbs2_snr_tab has only 80 elements. Signed-off-by: Heinrich Schuchardt Signed-off-by: Michael Krufky Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/ds3000.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/dvb-frontends/ds3000.c b/drivers/media/dvb-frontends/ds3000.c index 1e344b0..335daef 100644 --- a/drivers/media/dvb-frontends/ds3000.c +++ b/drivers/media/dvb-frontends/ds3000.c @@ -616,7 +616,7 @@ static int ds3000_read_snr(struct dvb_frontend *fe, u16 *snr) snr_reading = dvbs2_noise_reading / tmp; if (snr_reading > 80) snr_reading = 80; - *snr = -(dvbs2_snr_tab[snr_reading] / 1000); + *snr = -(dvbs2_snr_tab[snr_reading - 1] / 1000); } dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__, snr_reading, *snr); -- cgit v1.1 From a06b429df49bb50ec1e671123a45147a1d1a6186 Mon Sep 17 00:00:00 2001 From: Devin Heitmueller Date: Mon, 19 Aug 2013 18:25:16 -0300 Subject: [media] au0828: rework GPIO management for HVR-950q Restructure the way we bring the various GPIOs out of reset. In particular: 1. we only need to setup the GPIOs as outputs once 2. there's no point in writing 0x40 to register 0x00 since that's the EEPROM write protect and already it's configured as an input 3. Separate out the act of enabling the power supply and bringing the tuner and demod out of reset. If you don't then the chip may not be properly enabled (as the power supply is still ramping up when the chip comes out of reset). This can result in probing failures. Signed-off-by: Devin Heitmueller Signed-off-by: Michael Krufky Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/au0828/au0828-cards.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/drivers/media/usb/au0828/au0828-cards.c b/drivers/media/usb/au0828/au0828-cards.c index dd32dec..00291ea 100644 --- a/drivers/media/usb/au0828/au0828-cards.c +++ b/drivers/media/usb/au0828/au0828-cards.c @@ -270,18 +270,25 @@ void au0828_gpio_setup(struct au0828_dev *dev) * 9 - XC5000 Tuner */ - /* Into reset */ + /* Set relevant GPIOs as outputs (leave the EEPROM W/P + as an input since we will never touch it and it has + a pullup) */ au0828_write(dev, REG_003, 0x02); au0828_write(dev, REG_002, 0x80 | 0x20 | 0x10); + + /* Into reset */ au0828_write(dev, REG_001, 0x0); au0828_write(dev, REG_000, 0x0); - msleep(100); + msleep(50); - /* Out of reset (leave the cs5340 in reset until needed) */ - au0828_write(dev, REG_003, 0x02); - au0828_write(dev, REG_001, 0x02); - au0828_write(dev, REG_002, 0x80 | 0x20 | 0x10); - au0828_write(dev, REG_000, 0x80 | 0x40 | 0x20); + /* Bring power supply out of reset */ + au0828_write(dev, REG_000, 0x80); + msleep(50); + + /* Bring xc5000 and au8522 out of reset (leave the + cs5340 in reset until needed) */ + au0828_write(dev, REG_001, 0x02); /* xc5000 */ + au0828_write(dev, REG_000, 0x80 | 0x20); /* PS + au8522 */ msleep(250); break; -- cgit v1.1 From 9c669b731470154a1f7b0ad1c3231cf02114c163 Mon Sep 17 00:00:00 2001 From: Shuah Khan Date: Fri, 21 Feb 2014 21:50:13 -0300 Subject: [media] em28xx: add suspend/resume to em28xx_ops em28xx usb driver will have to suspend and resume its extensions. Adding suspend and resume to em28xx_ops gives extensions the ability to install suspend and resume that can be invoked from em28xx_usb driver suspend() and resume() interfaces. Approach: Add power management support to em28xx usb driver. This driver works in conjunction with extensions for each of the functions on the USB device for video/audio/dvb/remote functionality that is present on media USB devices it supports. During suspend and resume each of these extensions will have to do their part in suspending the components they control. Adding suspend and resume hooks to the existing struct em28xx_ops will enable the extensions the ability to implement suspend and resume hooks to be called from em28xx driver. The overall approach is as follows: -- add suspend and resume hooks to em28xx_ops -- add suspend and resume routines to em28xx-core to invoke suspend and resume hooks for all registered extensions. -- change em28xx dvb, audio, input, and video extensions to implement em28xx_ops: suspend and resume hooks. These hooks do what is necessary to suspend and resume the devices they control. Signed-off-by: Shuah Khan Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/em28xx/em28xx-core.c | 28 ++++++++++++++++++++++++++++ drivers/media/usb/em28xx/em28xx.h | 4 ++++ 2 files changed, 32 insertions(+) diff --git a/drivers/media/usb/em28xx/em28xx-core.c b/drivers/media/usb/em28xx/em28xx-core.c index 898fb9b..6de41c6 100644 --- a/drivers/media/usb/em28xx/em28xx-core.c +++ b/drivers/media/usb/em28xx/em28xx-core.c @@ -1106,3 +1106,31 @@ void em28xx_close_extension(struct em28xx *dev) list_del(&dev->devlist); mutex_unlock(&em28xx_devlist_mutex); } + +int em28xx_suspend_extension(struct em28xx *dev) +{ + const struct em28xx_ops *ops = NULL; + + em28xx_info("Suspending extensions"); + mutex_lock(&em28xx_devlist_mutex); + list_for_each_entry(ops, &em28xx_extension_devlist, next) { + if (ops->suspend) + ops->suspend(dev); + } + mutex_unlock(&em28xx_devlist_mutex); + return 0; +} + +int em28xx_resume_extension(struct em28xx *dev) +{ + const struct em28xx_ops *ops = NULL; + + em28xx_info("Resuming extensions"); + mutex_lock(&em28xx_devlist_mutex); + list_for_each_entry(ops, &em28xx_extension_devlist, next) { + if (ops->resume) + ops->resume(dev); + } + mutex_unlock(&em28xx_devlist_mutex); + return 0; +} diff --git a/drivers/media/usb/em28xx/em28xx.h b/drivers/media/usb/em28xx/em28xx.h index 32d8a4b..9b02f15 100644 --- a/drivers/media/usb/em28xx/em28xx.h +++ b/drivers/media/usb/em28xx/em28xx.h @@ -713,6 +713,8 @@ struct em28xx_ops { int id; int (*init)(struct em28xx *); int (*fini)(struct em28xx *); + int (*suspend)(struct em28xx *); + int (*resume)(struct em28xx *); }; /* Provided by em28xx-i2c.c */ @@ -758,6 +760,8 @@ int em28xx_register_extension(struct em28xx_ops *dev); void em28xx_unregister_extension(struct em28xx_ops *dev); void em28xx_init_extension(struct em28xx *dev); void em28xx_close_extension(struct em28xx *dev); +int em28xx_suspend_extension(struct em28xx *dev); +int em28xx_resume_extension(struct em28xx *dev); /* Provided by em28xx-cards.c */ extern struct em28xx_board em28xx_boards[]; -- cgit v1.1 From 6d746f91f23098c7613938b85e9b345d53b6de3f Mon Sep 17 00:00:00 2001 From: Shuah Khan Date: Fri, 21 Feb 2014 21:50:14 -0300 Subject: [media] em28xx-audio: implement em28xx_ops: suspend/resume hooks Implement em28xx_ops: suspend/resume hooks. em28xx usb driver will invoke em28xx_ops: suspend and resume hooks for all its extensions from its suspend() and resume() interfaces. Signed-off-by: Shuah Khan Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/em28xx/em28xx-audio.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/media/usb/em28xx/em28xx-audio.c b/drivers/media/usb/em28xx/em28xx-audio.c index 566fa09..0f5b6f3 100644 --- a/drivers/media/usb/em28xx/em28xx-audio.c +++ b/drivers/media/usb/em28xx/em28xx-audio.c @@ -989,11 +989,41 @@ static int em28xx_audio_fini(struct em28xx *dev) return 0; } +static int em28xx_audio_suspend(struct em28xx *dev) +{ + if (dev == NULL) + return 0; + + if (!dev->has_alsa_audio) + return 0; + + em28xx_info("Suspending audio extension"); + em28xx_deinit_isoc_audio(dev); + atomic_set(&dev->stream_started, 0); + return 0; +} + +static int em28xx_audio_resume(struct em28xx *dev) +{ + if (dev == NULL) + return 0; + + if (!dev->has_alsa_audio) + return 0; + + em28xx_info("Resuming audio extension"); + /* Nothing to do other than schedule_work() ?? */ + schedule_work(&dev->wq_trigger); + return 0; +} + static struct em28xx_ops audio_ops = { .id = EM28XX_AUDIO, .name = "Em28xx Audio Extension", .init = em28xx_audio_init, .fini = em28xx_audio_fini, + .suspend = em28xx_audio_suspend, + .resume = em28xx_audio_resume, }; static int __init em28xx_alsa_register(void) -- cgit v1.1 From ca2b46dacbf5caaa070c0195c794a35b49b189d1 Mon Sep 17 00:00:00 2001 From: Shuah Khan Date: Fri, 21 Feb 2014 21:50:15 -0300 Subject: [media] em28xx-dvb: implement em28xx_ops: suspend/resume hooks Implement em28xx_ops: suspend/resume hooks. em28xx usb driver will invoke em28xx_ops: suspend and resume hooks for all its extensions from its suspend() and resume() interfaces. Signed-off-by: Shuah Khan Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/em28xx/em28xx-dvb.c | 57 +++++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/drivers/media/usb/em28xx/em28xx-dvb.c b/drivers/media/usb/em28xx/em28xx-dvb.c index defac24..c1091c4 100644 --- a/drivers/media/usb/em28xx/em28xx-dvb.c +++ b/drivers/media/usb/em28xx/em28xx-dvb.c @@ -1515,11 +1515,68 @@ static int em28xx_dvb_fini(struct em28xx *dev) return 0; } +static int em28xx_dvb_suspend(struct em28xx *dev) +{ + int ret = 0; + + if (dev->is_audio_only) + return 0; + + if (!dev->board.has_dvb) + return 0; + + em28xx_info("Suspending DVB extension"); + if (dev->dvb) { + struct em28xx_dvb *dvb = dev->dvb; + + if (dvb->fe[0]) { + ret = dvb_frontend_suspend(dvb->fe[0]); + em28xx_info("fe0 suspend %d", ret); + } + if (dvb->fe[1]) { + dvb_frontend_suspend(dvb->fe[1]); + em28xx_info("fe1 suspend %d", ret); + } + } + + return 0; +} + +static int em28xx_dvb_resume(struct em28xx *dev) +{ + int ret = 0; + + if (dev->is_audio_only) + return 0; + + if (!dev->board.has_dvb) + return 0; + + em28xx_info("Resuming DVB extension"); + if (dev->dvb) { + struct em28xx_dvb *dvb = dev->dvb; + + if (dvb->fe[0]) { + ret = dvb_frontend_resume(dvb->fe[0]); + em28xx_info("fe0 resume %d", ret); + } + + if (dvb->fe[1]) { + ret = dvb_frontend_resume(dvb->fe[1]); + em28xx_info("fe1 resume %d", ret); + } + } + + return 0; +} + static struct em28xx_ops dvb_ops = { .id = EM28XX_DVB, .name = "Em28xx dvb Extension", .init = em28xx_dvb_init, .fini = em28xx_dvb_fini, + .suspend = em28xx_dvb_suspend, + .resume = em28xx_dvb_resume, }; static int __init em28xx_dvb_register(void) -- cgit v1.1 From 5025076aadfeaf774f341b852b997f2bc718da6a Mon Sep 17 00:00:00 2001 From: Shuah Khan Date: Fri, 21 Feb 2014 21:50:16 -0300 Subject: [media] em28xx-input: implement em28xx_ops: suspend/resume hooks Implement em28xx_ops: suspend/resume hooks. em28xx usb driver will invoke em28xx_ops: suspend and resume hooks for all its extensions from its suspend() and resume() interfaces. [m.chehab@samsung.com: Fix a breakage caused by calling a non-existing function call: schedule_delayed_work_sync(), and test if IR was defined at suspend/resume] Signed-off-by: Shuah Khan Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/em28xx/em28xx-input.c | 37 +++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/drivers/media/usb/em28xx/em28xx-input.c b/drivers/media/usb/em28xx/em28xx-input.c index 048e5b6..47a2c1d 100644 --- a/drivers/media/usb/em28xx/em28xx-input.c +++ b/drivers/media/usb/em28xx/em28xx-input.c @@ -827,11 +827,48 @@ static int em28xx_ir_fini(struct em28xx *dev) return 0; } +static int em28xx_ir_suspend(struct em28xx *dev) +{ + struct em28xx_IR *ir = dev->ir; + + if (dev->is_audio_only) + return 0; + + em28xx_info("Suspending input extension"); + if (ir) + cancel_delayed_work_sync(&ir->work); + cancel_delayed_work_sync(&dev->buttons_query_work); + /* is canceling delayed work sufficient or does the rc event + kthread needs stopping? kthread is stopped in + ir_raw_event_unregister() */ + return 0; +} + +static int em28xx_ir_resume(struct em28xx *dev) +{ + struct em28xx_IR *ir = dev->ir; + + if (dev->is_audio_only) + return 0; + + em28xx_info("Resuming input extension"); + /* if suspend calls ir_raw_event_unregister(), the should call + ir_raw_event_register() */ + if (ir) + schedule_delayed_work(&ir->work, msecs_to_jiffies(ir->polling)); + if (dev->num_button_polling_addresses) + schedule_delayed_work(&dev->buttons_query_work, + msecs_to_jiffies(dev->button_polling_interval)); + return 0; +} + static struct em28xx_ops rc_ops = { .id = EM28XX_RC, .name = "Em28xx Input Extension", .init = em28xx_ir_init, .fini = em28xx_ir_fini, + .suspend = em28xx_ir_suspend, + .resume = em28xx_ir_resume, }; static int __init em28xx_rc_register(void) -- cgit v1.1 From a61f68119af399b2911e9881abd5bd123f886611 Mon Sep 17 00:00:00 2001 From: Shuah Khan Date: Fri, 21 Feb 2014 21:50:17 -0300 Subject: [media] em28xx-video: implement em28xx_ops: suspend/resume hooks Implement em28xx_ops: suspend/resume hooks. em28xx usb driver will invoke em28xx_ops: suspend and resume hooks for all its extensions from its suspend() and resume() interfaces. Signed-off-by: Shuah Khan Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/em28xx/em28xx-video.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/media/usb/em28xx/em28xx-video.c b/drivers/media/usb/em28xx/em28xx-video.c index 2775c90..19af6b3 100644 --- a/drivers/media/usb/em28xx/em28xx-video.c +++ b/drivers/media/usb/em28xx/em28xx-video.c @@ -1933,6 +1933,32 @@ static int em28xx_v4l2_fini(struct em28xx *dev) return 0; } +static int em28xx_v4l2_suspend(struct em28xx *dev) +{ + if (dev->is_audio_only) + return 0; + + if (!dev->has_video) + return 0; + + em28xx_info("Suspending video extension"); + em28xx_stop_urbs(dev); + return 0; +} + +static int em28xx_v4l2_resume(struct em28xx *dev) +{ + if (dev->is_audio_only) + return 0; + + if (!dev->has_video) + return 0; + + em28xx_info("Resuming video extension"); + /* what do we do here */ + return 0; +} + /* * em28xx_v4l2_close() * stops streaming and deallocates all resources allocated by the v4l2 @@ -2505,6 +2531,8 @@ static struct em28xx_ops v4l2_ops = { .name = "Em28xx v4l2 Extension", .init = em28xx_v4l2_init, .fini = em28xx_v4l2_fini, + .suspend = em28xx_v4l2_suspend, + .resume = em28xx_v4l2_resume, }; static int __init em28xx_video_register(void) -- cgit v1.1 From cd701c89751d5c63230f47da9a78cdbb39384fdc Mon Sep 17 00:00:00 2001 From: Shuah Khan Date: Fri, 21 Feb 2014 21:50:18 -0300 Subject: [media] em28xx: implement em28xx_usb_driver suspend, resume, reset_resume hooks Implement em28xx_usb_driver suspend, resume, and reset_resume hooks. These hooks will invoke em28xx core em28xx_suspend_extension() and em28xx_resume_extension() to suspend and resume registered extensions. Approach: Add power management support to em28xx usb driver. This driver works in conjunction with extensions for each of the functions on the USB device for video/audio/dvb/remote functionality that is present on media USB devices it supports. During suspend and resume each of these extensions will have to do their part in suspending the components they control. Adding suspend and resume hooks to the existing struct em28xx_ops will enable the extensions the ability to implement suspend and resume hooks to be called from em28xx driver. The overall approach is as follows: -- add suspend and resume hooks to em28xx_ops -- add suspend and resume routines to em28xx-core to invoke suspend and resume hooks for all registered extensions. -- change em28xx dvb, audio, input, and video extensions to implement em28xx_ops: suspend and resume hooks. These hooks do what is necessary to suspend and resume the devices they control. Signed-off-by: Shuah Khan Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/em28xx/em28xx-cards.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/media/usb/em28xx/em28xx-cards.c b/drivers/media/usb/em28xx/em28xx-cards.c index eb39903..1752e7e 100644 --- a/drivers/media/usb/em28xx/em28xx-cards.c +++ b/drivers/media/usb/em28xx/em28xx-cards.c @@ -3393,10 +3393,36 @@ static void em28xx_usb_disconnect(struct usb_interface *interface) } } +static int em28xx_usb_suspend(struct usb_interface *interface, + pm_message_t message) +{ + struct em28xx *dev; + + dev = usb_get_intfdata(interface); + if (!dev) + return 0; + em28xx_suspend_extension(dev); + return 0; +} + +static int em28xx_usb_resume(struct usb_interface *interface) +{ + struct em28xx *dev; + + dev = usb_get_intfdata(interface); + if (!dev) + return 0; + em28xx_resume_extension(dev); + return 0; +} + static struct usb_driver em28xx_usb_driver = { .name = "em28xx", .probe = em28xx_usb_probe, .disconnect = em28xx_usb_disconnect, + .suspend = em28xx_usb_suspend, + .resume = em28xx_usb_resume, + .reset_resume = em28xx_usb_resume, .id_table = em28xx_id_table, }; -- cgit v1.1 From ffdeca885e887dcdde40c03d8910373bd1f62296 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sun, 2 Mar 2014 08:20:54 -0300 Subject: [media] em28xx_dvb: only call the software filter if data Several URBs will be simply not filled. Don't call the DVB core software filter for those empty URBs. Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/em28xx/em28xx-dvb.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/media/usb/em28xx/em28xx-dvb.c b/drivers/media/usb/em28xx/em28xx-dvb.c index c1091c4..301463f 100644 --- a/drivers/media/usb/em28xx/em28xx-dvb.c +++ b/drivers/media/usb/em28xx/em28xx-dvb.c @@ -161,6 +161,8 @@ static inline int em28xx_dvb_urb_data_copy(struct em28xx *dev, struct urb *urb) if (urb->status != -EPROTO) continue; } + if (!urb->actual_length) + continue; dvb_dmx_swfilter(&dev->dvb->demux, urb->transfer_buffer, urb->actual_length); } else { @@ -170,6 +172,8 @@ static inline int em28xx_dvb_urb_data_copy(struct em28xx *dev, struct urb *urb) if (urb->iso_frame_desc[i].status != -EPROTO) continue; } + if (!urb->iso_frame_desc[i].actual_length) + continue; dvb_dmx_swfilter(&dev->dvb->demux, urb->transfer_buffer + urb->iso_frame_desc[i].offset, -- cgit v1.1 From 52f7b00e645b2c85020bca2cc3dc720ab7f93ac0 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Fri, 24 Jan 2014 23:17:00 -0300 Subject: [media] em28xx: Display the used DVB alternate That helps to understand what's going there. Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/em28xx/em28xx-dvb.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/media/usb/em28xx/em28xx-dvb.c b/drivers/media/usb/em28xx/em28xx-dvb.c index 301463f..16c4d58 100644 --- a/drivers/media/usb/em28xx/em28xx-dvb.c +++ b/drivers/media/usb/em28xx/em28xx-dvb.c @@ -212,10 +212,10 @@ static int em28xx_start_streaming(struct em28xx_dvb *dvb) if (rc < 0) return rc; - dprintk(1, "Using %d buffers each with %d x %d bytes\n", + dprintk(1, "Using %d buffers each with %d x %d bytes, alternate %d\n", EM28XX_DVB_NUM_BUFS, packet_multiplier, - dvb_max_packet_size); + dvb_max_packet_size, dvb_alt); return em28xx_init_usb_xfer(dev, EM28XX_DIGITAL_MODE, dev->dvb_xfer_bulk, -- cgit v1.1 From e6876692ca86f1aacccec42fc68f628a8f2a022b Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sun, 16 Feb 2014 06:36:17 -0300 Subject: [media] dvb_frontend: better handle lna set errors If an attempt to set LNA fails, restore the cache to LNA_AUTO, in order to make it to reflect the current LNA status. Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-core/dvb_frontend.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/media/dvb-core/dvb_frontend.c b/drivers/media/dvb-core/dvb_frontend.c index 1f925e8..2d32c13 100644 --- a/drivers/media/dvb-core/dvb_frontend.c +++ b/drivers/media/dvb-core/dvb_frontend.c @@ -1882,6 +1882,8 @@ static int dtv_property_process_set(struct dvb_frontend *fe, c->lna = tvp->u.data; if (fe->ops.set_lna) r = fe->ops.set_lna(fe); + if (r < 0) + c->lna = LNA_AUTO; break; default: -- cgit v1.1 From 4872b46b73618190bc3debcbc552460ddb4aad11 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 18 Feb 2014 20:35:51 -0300 Subject: [media] DocBook: document DVB DMX_[ADD|REMOVE]_PID Those ioctls were added back in 2009, at changeset 1cb662a3144 but were never documented. Fortunately, the original commit is good enough to serve as the basis for documenting it. Also, the support for it is done by dmxdev implementation. So, add a proper documentation for it, based on the description of the original changeset. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/demux.xml | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/Documentation/DocBook/media/dvb/demux.xml b/Documentation/DocBook/media/dvb/demux.xml index 86de89c..c8683d6 100644 --- a/Documentation/DocBook/media/dvb/demux.xml +++ b/Documentation/DocBook/media/dvb/demux.xml @@ -1042,7 +1042,14 @@ role="subsection">DMX_ADD_PID -This ioctl is undocumented. Documentation is welcome. +This ioctl call allows to add multiple PIDs to a transport stream filter +previously set up with DMX_SET_PES_FILTER and output equal to DMX_OUT_TSDEMUX_TAP. + +It is used by readers of /dev/dvb/adapterX/demuxY. + +It may be called at any time, i.e. before or after the first filter on the +shared file descriptor was started. It makes it possible to record multiple +services without the need to de-multiplex or re-multiplex TS packets. SYNOPSIS @@ -1075,7 +1082,7 @@ role="subsection">DMX_ADD_PID -Undocumented. +PID number to be filtered. &return-value-dvb; @@ -1087,7 +1094,15 @@ role="subsection">DMX_REMOVE_PID -This ioctl is undocumented. Documentation is welcome. +This ioctl call allows to remove a PID when multiple PIDs are set on a +transport stream filter, e. g. a filter previously set up with output equal to +DMX_OUT_TSDEMUX_TAP, created via either DMX_SET_PES_FILTER or DMX_ADD_PID. + +It is used by readers of /dev/dvb/adapterX/demuxY. + +It may be called at any time, i.e. before or after the first filter on the +shared file descriptor was started. It makes it possible to record multiple +services without the need to de-multiplex or re-multiplex TS packets. SYNOPSIS @@ -1120,7 +1135,7 @@ role="subsection">DMX_REMOVE_PID -Undocumented. +PID of the PES filter to be removed. &return-value-dvb; -- cgit v1.1 From 38b2df95c53be4bd5421d933ca0dabbcb82741d0 Mon Sep 17 00:00:00 2001 From: Devin Heitmueller Date: Mon, 13 Aug 2012 21:18:02 -0300 Subject: [media] drx-j: add a driver for Trident drx-j frontend Add support for the Trident DRX-J driver, including a card profile for the PCTV 80e which uses the chip. Thanks to Trident for allowing the release of this code under a BSD license, and of course Hauppauge/PCTV for pushing for its release to the community. [pdickeybeta@gmail.com: modified to fix compilation errors and also to move the driver files from the drx39xy subdirectory to the frontends directory] [m.chehab@samsung.com: fix merge conflicts, commented drx-j compilation and added EM28XX_R06_I2C_CLK setup also to the board setup] Signed-off-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- Documentation/video4linux/CARDLIST.em28xx | 1 + drivers/media/dvb-frontends/Kconfig | 2 + drivers/media/dvb-frontends/Makefile | 1 + drivers/media/dvb-frontends/drx39xyj/Kconfig | 8 + drivers/media/dvb-frontends/drx39xyj/Makefile | 3 + drivers/media/dvb-frontends/drx39xyj/bsp_host.h | 82 + drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h | 219 + drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h | 218 + drivers/media/dvb-frontends/drx39xyj/bsp_types.h | 230 + drivers/media/dvb-frontends/drx39xyj/drx39xxj.c | 456 + drivers/media/dvb-frontends/drx39xyj/drx39xxj.h | 40 + .../media/dvb-frontends/drx39xyj/drx39xxj_dummy.c | 134 + .../media/dvb-frontends/drx39xyj/drx_dap_fasi.c | 674 + .../media/dvb-frontends/drx39xyj/drx_dap_fasi.h | 267 + drivers/media/dvb-frontends/drx39xyj/drx_driver.c | 1600 ++ drivers/media/dvb-frontends/drx39xyj/drx_driver.h | 2588 +++ .../dvb-frontends/drx39xyj/drx_driver_version.h | 83 + drivers/media/dvb-frontends/drx39xyj/drxj.c | 16680 +++++++++++++++++++ drivers/media/dvb-frontends/drx39xyj/drxj.h | 732 + drivers/media/dvb-frontends/drx39xyj/drxj_map.h | 15350 +++++++++++++++++ drivers/media/dvb-frontends/drx39xyj/drxj_mc.h | 3947 +++++ drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsb.h | 752 + .../media/dvb-frontends/drx39xyj/drxj_mc_vsbqam.h | 1444 ++ .../media/dvb-frontends/drx39xyj/drxj_options.h | 68 + drivers/media/usb/em28xx/em28xx-cards.c | 20 + drivers/media/usb/em28xx/em28xx-dvb.c | 27 + drivers/media/usb/em28xx/em28xx.h | 1 + 27 files changed, 45627 insertions(+) create mode 100644 drivers/media/dvb-frontends/drx39xyj/Kconfig create mode 100644 drivers/media/dvb-frontends/drx39xyj/Makefile create mode 100644 drivers/media/dvb-frontends/drx39xyj/bsp_host.h create mode 100644 drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h create mode 100644 drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h create mode 100644 drivers/media/dvb-frontends/drx39xyj/bsp_types.h create mode 100644 drivers/media/dvb-frontends/drx39xyj/drx39xxj.c create mode 100644 drivers/media/dvb-frontends/drx39xyj/drx39xxj.h create mode 100644 drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c create mode 100644 drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c create mode 100644 drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.h create mode 100644 drivers/media/dvb-frontends/drx39xyj/drx_driver.c create mode 100644 drivers/media/dvb-frontends/drx39xyj/drx_driver.h create mode 100644 drivers/media/dvb-frontends/drx39xyj/drx_driver_version.h create mode 100644 drivers/media/dvb-frontends/drx39xyj/drxj.c create mode 100644 drivers/media/dvb-frontends/drx39xyj/drxj.h create mode 100644 drivers/media/dvb-frontends/drx39xyj/drxj_map.h create mode 100644 drivers/media/dvb-frontends/drx39xyj/drxj_mc.h create mode 100644 drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsb.h create mode 100644 drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsbqam.h create mode 100644 drivers/media/dvb-frontends/drx39xyj/drxj_options.h diff --git a/Documentation/video4linux/CARDLIST.em28xx b/Documentation/video4linux/CARDLIST.em28xx index e818644..404ac9b 100644 --- a/Documentation/video4linux/CARDLIST.em28xx +++ b/Documentation/video4linux/CARDLIST.em28xx @@ -57,6 +57,7 @@ 56 -> Pinnacle Hybrid Pro (330e) (em2882) [2304:0226] 57 -> Kworld PlusTV HD Hybrid 330 (em2883) [eb1a:a316] 58 -> Compro VideoMate ForYou/Stereo (em2820/em2840) [185b:2041] + 59 -> Pinnacle PCTV HD Mini (em2874) [2304:023f] 60 -> Hauppauge WinTV HVR 850 (em2883) [2040:651f] 61 -> Pixelview PlayTV Box 4 USB 2.0 (em2820/em2840) 62 -> Gadmei TVR200 (em2820/em2840) diff --git a/drivers/media/dvb-frontends/Kconfig b/drivers/media/dvb-frontends/Kconfig index 4433071..611c794 100644 --- a/drivers/media/dvb-frontends/Kconfig +++ b/drivers/media/dvb-frontends/Kconfig @@ -650,6 +650,8 @@ config DVB_TUNER_DIB0090 comment "SEC control devices for DVB-S" depends on DVB_CORE +source "drivers/media/dvb-frontends/drx39xyj/Kconfig" + config DVB_LNBP21 tristate "LNBP21/LNBH24 SEC controllers" depends on DVB_CORE && I2C diff --git a/drivers/media/dvb-frontends/Makefile b/drivers/media/dvb-frontends/Makefile index b5815c8..282aba2 100644 --- a/drivers/media/dvb-frontends/Makefile +++ b/drivers/media/dvb-frontends/Makefile @@ -92,6 +92,7 @@ obj-$(CONFIG_DVB_HD29L2) += hd29l2.o obj-$(CONFIG_DVB_DS3000) += ds3000.o obj-$(CONFIG_DVB_TS2020) += ts2020.o obj-$(CONFIG_DVB_MB86A16) += mb86a16.o +obj-$(CONFIG_DVB_DRX39XYJ) += drx39xyj/ obj-$(CONFIG_DVB_MB86A20S) += mb86a20s.o obj-$(CONFIG_DVB_IX2505V) += ix2505v.o obj-$(CONFIG_DVB_STV0367) += stv0367.o diff --git a/drivers/media/dvb-frontends/drx39xyj/Kconfig b/drivers/media/dvb-frontends/drx39xyj/Kconfig new file mode 100644 index 0000000..5bcf6b4 --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/Kconfig @@ -0,0 +1,8 @@ +config DVB_DRX39XYJ + tristate "Micronas DRX-J demodulator" + depends on DVB_CORE && I2C + default m if DVB_FE_CUSTOMISE + depends on BROKEN + help + An ATSC 8VSB and QAM64/256 tuner module. Say Y when you want + to support this frontend. diff --git a/drivers/media/dvb-frontends/drx39xyj/Makefile b/drivers/media/dvb-frontends/drx39xyj/Makefile new file mode 100644 index 0000000..b44dc37 --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/Makefile @@ -0,0 +1,3 @@ +drx39xyj-objs := drx39xxj.o drx_driver.o drx39xxj_dummy.o drxj.o drx_dap_fasi.o + +obj-$(CONFIG_DVB_DRX39XYJ) += drx39xyj.o diff --git a/drivers/media/dvb-frontends/drx39xyj/bsp_host.h b/drivers/media/dvb-frontends/drx39xyj/bsp_host.h new file mode 100644 index 0000000..30f711d --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/bsp_host.h @@ -0,0 +1,82 @@ +/** +* \file $Id: bsp_host.h,v 1.3 2009/07/07 14:20:30 justin Exp $ +* +* \brief Host and OS dependent type definitions, macro's and functions +* +*/ + +/* +* $(c) 2004-2005,2007-2009 Trident Microsystems, Inc. - All rights reserved. +* +* This software and related documentation (the 'Software') are intellectual +* property owned by Trident and are copyright of Trident, unless specifically +* noted otherwise. +* +* Any use of the Software is permitted only pursuant to the terms of the +* license agreement, if any, which accompanies, is included with or applicable +* to the Software ('License Agreement') or upon express written consent of +* Trident. Any copying, reproduction or redistribution of the Software in +* whole or in part by any means not in accordance with the License Agreement +* or as agreed in writing by Trident is expressly prohibited. +* +* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE +* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE +* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND +* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES +* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT +* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL +* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY +* TO USE THE SOFTWARE. +* +* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, +* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, +* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS +* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE +* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM +* TRIDENT'S NEGLIGENCE. $ +* +*/ +#ifndef __DRXBSP_HOST_H__ +#define __DRXBSP_HOST_H__ +/*------------------------------------------------------------------------- +INCLUDES +-------------------------------------------------------------------------*/ +#include "bsp_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------- +TYPEDEFS +-------------------------------------------------------------------------*/ + + +/*------------------------------------------------------------------------- +DEFINES +-------------------------------------------------------------------------*/ + +/*------------------------------------------------------------------------- +Exported FUNCTIONS +-------------------------------------------------------------------------*/ +DRXStatus_t DRXBSP_HST_Init( void ); + +DRXStatus_t DRXBSP_HST_Term( void ); + +void* DRXBSP_HST_Memcpy( void *to, void *from, u32_t n); + +int DRXBSP_HST_Memcmp( void *s1, void *s2, u32_t n); + +u32_t DRXBSP_HST_Clock( void ); + +DRXStatus_t DRXBSP_HST_Sleep( u32_t n ); + +/*------------------------------------------------------------------------- +THE END +-------------------------------------------------------------------------*/ +#ifdef __cplusplus +} +#endif + +#endif /* __DRXBSP_HOST_H__ */ diff --git a/drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h b/drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h new file mode 100644 index 0000000..6f4e69f --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h @@ -0,0 +1,219 @@ +/** +* \file $Id: bsp_i2c.h,v 1.5 2009/07/07 14:20:30 justin Exp $ +* +* \brief I2C API, implementation depends on board specifics +* +* This module encapsulates I2C access.In some applications several devices +* share one I2C bus. If these devices have the same I2C address some kind +* off "switch" must be implemented to ensure error free communication with +* one device. In case such a "switch" is used, the device ID can be used +* to implement control over this "switch". +* +* +*/ + +/* +* $(c) 2004-2005,2008-2009 Trident Microsystems, Inc. - All rights reserved. +* +* This software and related documentation (the 'Software') are intellectual +* property owned by Trident and are copyright of Trident, unless specifically +* noted otherwise. +* +* Any use of the Software is permitted only pursuant to the terms of the +* license agreement, if any, which accompanies, is included with or applicable +* to the Software ('License Agreement') or upon express written consent of +* Trident. Any copying, reproduction or redistribution of the Software in +* whole or in part by any means not in accordance with the License Agreement +* or as agreed in writing by Trident is expressly prohibited. +* +* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE +* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE +* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND +* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES +* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT +* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL +* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY +* TO USE THE SOFTWARE. +* +* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, +* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, +* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS +* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE +* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM +* TRIDENT'S NEGLIGENCE. $ +* +*/ + +#ifndef __BSPI2C_H__ +#define __BSPI2C_H__ +/*------------------------------------------------------------------------------ +INCLUDES +------------------------------------------------------------------------------*/ +#include "bsp_types.h" + +#ifdef __cplusplus +extern "C" { +#endif +/*------------------------------------------------------------------------------ +TYPEDEFS +------------------------------------------------------------------------------*/ +/** +* \typedef I2Caddr_t +* \brief I2C device address (7-bit or 10-bit) +*/ +typedef u16_t I2Caddr_t; + +/** +* \typedef I2CdevId_t +* \brief Device identifier. +* +* The device ID can be useful if several devices share an I2C address, +* or if multiple I2C busses are used. +* It can be used to control a "switch" selecting the correct device and/or +* I2C bus. +* +*/ +typedef u16_t I2CdevId_t; + +/** +* \struct _I2CDeviceAddr_t +* \brief I2C device parameters. +* +* This structure contains the I2C address, the device ID and a userData pointer. +* The userData pointer can be used for application specific purposes. +* +*/ +struct _I2CDeviceAddr_t { + I2Caddr_t i2cAddr; /**< The I2C address of the device. */ + I2CdevId_t i2cDevId; /**< The device identifier. */ + void *userData; /**< User data pointer */ +}; + +/** +* \typedef I2CDeviceAddr_t +* \brief I2C device parameters. +* +* This structure contains the I2C address and the device ID. +* +*/ +typedef struct _I2CDeviceAddr_t I2CDeviceAddr_t; + +/** +* \typedef pI2CDeviceAddr_t +* \brief Pointer to I2C device parameters. +*/ +typedef I2CDeviceAddr_t *pI2CDeviceAddr_t; + +/*------------------------------------------------------------------------------ +DEFINES +------------------------------------------------------------------------------*/ + +/*------------------------------------------------------------------------------ +MACROS +------------------------------------------------------------------------------*/ + +/** +* \def IS_I2C_10BIT( addr ) +* \brief Determine if I2C address 'addr' is a 10 bits address or not. +* \param addr The I2C address. +* \return int. +* \retval 0 if address is not a 10 bits I2C address. +* \retval 1 if address is a 10 bits I2C address. +*/ +#define IS_I2C_10BIT(addr) \ + (((addr) & 0xF8) == 0xF0) + +/*------------------------------------------------------------------------------ +ENUM +------------------------------------------------------------------------------*/ + +/*------------------------------------------------------------------------------ +STRUCTS +------------------------------------------------------------------------------*/ + +/*------------------------------------------------------------------------------ +Exported FUNCTIONS +------------------------------------------------------------------------------*/ + + +/** +* \fn DRXBSP_I2C_Init() +* \brief Initialize I2C communication module. +* \return DRXStatus_t Return status. +* \retval DRX_STS_OK Initialization successful. +* \retval DRX_STS_ERROR Initialization failed. +*/ +DRXStatus_t DRXBSP_I2C_Init( void ); + + +/** +* \fn DRXBSP_I2C_Term() +* \brief Terminate I2C communication module. +* \return DRXStatus_t Return status. +* \retval DRX_STS_OK Termination successful. +* \retval DRX_STS_ERROR Termination failed. +*/ +DRXStatus_t DRXBSP_I2C_Term( void ); + +/** +* \fn DRXStatus_t DRXBSP_I2C_WriteRead( pI2CDeviceAddr_t wDevAddr, +* u16_t wCount, +* pu8_t wData, +* pI2CDeviceAddr_t rDevAddr, +* u16_t rCount, +* pu8_t rData) +* \brief Read and/or write count bytes from I2C bus, store them in data[]. +* \param wDevAddr The device i2c address and the device ID to write to +* \param wCount The number of bytes to write +* \param wData The array to write the data to +* \param rDevAddr The device i2c address and the device ID to read from +* \param rCount The number of bytes to read +* \param rData The array to read the data from +* \return DRXStatus_t Return status. +* \retval DRX_STS_OK Succes. +* \retval DRX_STS_ERROR Failure. +* \retval DRX_STS_INVALID_ARG Parameter 'wcount' is not zero but parameter +* 'wdata' contains NULL. +* Idem for 'rcount' and 'rdata'. +* Both wDevAddr and rDevAddr are NULL. +* +* This function must implement an atomic write and/or read action on the I2C bus +* No other process may use the I2C bus when this function is executing. +* The critical section of this function runs from and including the I2C +* write, up to and including the I2C read action. +* +* The device ID can be useful if several devices share an I2C address. +* It can be used to control a "switch" on the I2C bus to the correct device. +*/ +DRXStatus_t DRXBSP_I2C_WriteRead( pI2CDeviceAddr_t wDevAddr, + u16_t wCount, + pu8_t wData, + pI2CDeviceAddr_t rDevAddr, + u16_t rCount, + pu8_t rData); + + +/** +* \fn DRXBSP_I2C_ErrorText() +* \brief Returns a human readable error. +* Counter part of numerical DRX_I2C_Error_g. +* +* \return char* Pointer to human readable error text. +*/ +char* DRXBSP_I2C_ErrorText( void ); + +/** +* \var DRX_I2C_Error_g; +* \brief I2C specific error codes, platform dependent. +*/ +extern int DRX_I2C_Error_g; + + +/*------------------------------------------------------------------------------ +THE END +------------------------------------------------------------------------------*/ +#ifdef __cplusplus +} +#endif +#endif /* __BSPI2C_H__ */ diff --git a/drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h b/drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h new file mode 100644 index 0000000..e5693d0 --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h @@ -0,0 +1,218 @@ +/** +* \file $Id: bsp_tuner.h,v 1.5 2009/10/19 22:15:13 dingtao Exp $ +* +* \brief Tuner dependable type definitions, macro's and functions +* +*/ + +/* +* $(c) 2004-2006,2008-2009 Trident Microsystems, Inc. - All rights reserved. +* +* This software and related documentation (the 'Software') are intellectual +* property owned by Trident and are copyright of Trident, unless specifically +* noted otherwise. +* +* Any use of the Software is permitted only pursuant to the terms of the +* license agreement, if any, which accompanies, is included with or applicable +* to the Software ('License Agreement') or upon express written consent of +* Trident. Any copying, reproduction or redistribution of the Software in +* whole or in part by any means not in accordance with the License Agreement +* or as agreed in writing by Trident is expressly prohibited. +* +* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE +* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE +* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND +* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES +* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT +* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL +* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY +* TO USE THE SOFTWARE. +* +* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, +* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, +* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS +* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE +* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM +* TRIDENT'S NEGLIGENCE. $ +* +*/ + +#ifndef __DRXBSP_TUNER_H__ +#define __DRXBSP_TUNER_H__ +/*------------------------------------------------------------------------------ +INCLUDES +------------------------------------------------------------------------------*/ +#include "bsp_types.h" +#include "bsp_i2c.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------ +DEFINES +------------------------------------------------------------------------------*/ + + + /* Sub-mode bits should be adjacent and incremental */ +#define TUNER_MODE_SUB0 0x0001 /* for sub-mode (e.g. RF-AGC setting) */ +#define TUNER_MODE_SUB1 0x0002 /* for sub-mode (e.g. RF-AGC setting) */ +#define TUNER_MODE_SUB2 0x0004 /* for sub-mode (e.g. RF-AGC setting) */ +#define TUNER_MODE_SUB3 0x0008 /* for sub-mode (e.g. RF-AGC setting) */ +#define TUNER_MODE_SUB4 0x0010 /* for sub-mode (e.g. RF-AGC setting) */ +#define TUNER_MODE_SUB5 0x0020 /* for sub-mode (e.g. RF-AGC setting) */ +#define TUNER_MODE_SUB6 0x0040 /* for sub-mode (e.g. RF-AGC setting) */ +#define TUNER_MODE_SUB7 0x0080 /* for sub-mode (e.g. RF-AGC setting) */ + +#define TUNER_MODE_DIGITAL 0x0100 /* for digital channel (e.g. DVB-T) */ +#define TUNER_MODE_ANALOG 0x0200 /* for analog channel (e.g. PAL) */ +#define TUNER_MODE_SWITCH 0x0400 /* during channel switch & scanning */ +#define TUNER_MODE_LOCK 0x0800 /* after tuner has locked */ +#define TUNER_MODE_6MHZ 0x1000 /* for 6MHz bandwidth channels */ +#define TUNER_MODE_7MHZ 0x2000 /* for 7MHz bandwidth channels */ +#define TUNER_MODE_8MHZ 0x4000 /* for 8MHz bandwidth channels */ + +#define TUNER_MODE_SUB_MAX 8 +#define TUNER_MODE_SUBALL ( TUNER_MODE_SUB0 | TUNER_MODE_SUB1 | \ + TUNER_MODE_SUB2 | TUNER_MODE_SUB3 | \ + TUNER_MODE_SUB4 | TUNER_MODE_SUB5 | \ + TUNER_MODE_SUB6 | TUNER_MODE_SUB7 ) + +/*------------------------------------------------------------------------------ +TYPEDEFS +------------------------------------------------------------------------------*/ + +typedef u32_t TUNERMode_t; +typedef pu32_t pTUNERMode_t; + +typedef char* TUNERSubMode_t; /* description of submode */ +typedef TUNERSubMode_t *pTUNERSubMode_t; + + +typedef enum { + + TUNER_LOCKED, + TUNER_NOT_LOCKED + +} TUNERLockStatus_t, *pTUNERLockStatus_t; + + +typedef struct { + + char *name; /* Tuner brand & type name */ + DRXFrequency_t minFreqRF; /* Lowest RF input frequency, in kHz */ + DRXFrequency_t maxFreqRF; /* Highest RF input frequency, in kHz */ + + u8_t subMode; /* Index to sub-mode in use */ + pTUNERSubMode_t subModeDescriptions; /* Pointer to description of sub-modes*/ + u8_t subModes; /* Number of available sub-modes */ + + /* The following fields will be either 0, NULL or FALSE and do not need + initialisation */ + void *selfCheck; /* gives proof of initialization */ + Bool_t programmed; /* only valid if selfCheck is OK */ + DRXFrequency_t RFfrequency; /* only valid if programmed */ + DRXFrequency_t IFfrequency; /* only valid if programmed */ + + void* myUserData; /* pointer to associated demod instance */ + u16_t myCapabilities; /* value for storing application flags */ + +} TUNERCommonAttr_t, *pTUNERCommonAttr_t; + + +/* +* Generic functions for DRX devices. +*/ +typedef struct TUNERInstance_s *pTUNERInstance_t; + +typedef DRXStatus_t (*TUNEROpenFunc_t)( pTUNERInstance_t tuner ); +typedef DRXStatus_t (*TUNERCloseFunc_t)( pTUNERInstance_t tuner ); + +typedef DRXStatus_t (*TUNERSetFrequencyFunc_t)( pTUNERInstance_t tuner, + TUNERMode_t mode, + DRXFrequency_t frequency ); + +typedef DRXStatus_t (*TUNERGetFrequencyFunc_t)( pTUNERInstance_t tuner, + TUNERMode_t mode, + pDRXFrequency_t RFfrequency, + pDRXFrequency_t IFfrequency ); + +typedef DRXStatus_t (*TUNERLockStatusFunc_t)( pTUNERInstance_t tuner, + pTUNERLockStatus_t lockStat ); + +typedef DRXStatus_t (*TUNERi2cWriteReadFunc_t)( pTUNERInstance_t tuner, + pI2CDeviceAddr_t wDevAddr, + u16_t wCount, + pu8_t wData, + pI2CDeviceAddr_t rDevAddr, + u16_t rCount, + pu8_t rData ); + +typedef struct +{ + TUNEROpenFunc_t openFunc; + TUNERCloseFunc_t closeFunc; + TUNERSetFrequencyFunc_t setFrequencyFunc; + TUNERGetFrequencyFunc_t getFrequencyFunc; + TUNERLockStatusFunc_t lockStatusFunc; + TUNERi2cWriteReadFunc_t i2cWriteReadFunc; + +} TUNERFunc_t, *pTUNERFunc_t; + +typedef struct TUNERInstance_s { + + I2CDeviceAddr_t myI2CDevAddr; + pTUNERCommonAttr_t myCommonAttr; + void* myExtAttr; + pTUNERFunc_t myFunct; + +} TUNERInstance_t; + + +/*------------------------------------------------------------------------------ +ENUM +------------------------------------------------------------------------------*/ + +/*------------------------------------------------------------------------------ +STRUCTS +------------------------------------------------------------------------------*/ + + +/*------------------------------------------------------------------------------ +Exported FUNCTIONS +------------------------------------------------------------------------------*/ + +DRXStatus_t DRXBSP_TUNER_Open( pTUNERInstance_t tuner ); + +DRXStatus_t DRXBSP_TUNER_Close( pTUNERInstance_t tuner ); + +DRXStatus_t DRXBSP_TUNER_SetFrequency( pTUNERInstance_t tuner, + TUNERMode_t mode, + DRXFrequency_t frequency ); + +DRXStatus_t DRXBSP_TUNER_GetFrequency( pTUNERInstance_t tuner, + TUNERMode_t mode, + pDRXFrequency_t RFfrequency, + pDRXFrequency_t IFfrequency ); + +DRXStatus_t DRXBSP_TUNER_LockStatus( pTUNERInstance_t tuner, + pTUNERLockStatus_t lockStat ); + +DRXStatus_t DRXBSP_TUNER_DefaultI2CWriteRead( pTUNERInstance_t tuner, + pI2CDeviceAddr_t wDevAddr, + u16_t wCount, + pu8_t wData, + pI2CDeviceAddr_t rDevAddr, + u16_t rCount, + pu8_t rData); + +/*------------------------------------------------------------------------------ +THE END +------------------------------------------------------------------------------*/ +#ifdef __cplusplus +} +#endif +#endif /* __DRXBSP_TUNER_H__ */ + +/* End of file */ diff --git a/drivers/media/dvb-frontends/drx39xyj/bsp_types.h b/drivers/media/dvb-frontends/drx39xyj/bsp_types.h new file mode 100644 index 0000000..4a0dc0b --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/bsp_types.h @@ -0,0 +1,230 @@ +/** +* \file $Id: bsp_types.h,v 1.5 2009/08/06 12:55:57 carlo Exp $ +* +* \brief General type definitions for board support packages +* +* This file contains type definitions that are needed for almost any +* board support package. +* The definitions are host and project independent. +* +*/ + +/* +* $(c) 2004-2006,2008-2009 Trident Microsystems, Inc. - All rights reserved. +* +* This software and related documentation (the 'Software') are intellectual +* property owned by Trident and are copyright of Trident, unless specifically +* noted otherwise. +* +* Any use of the Software is permitted only pursuant to the terms of the +* license agreement, if any, which accompanies, is included with or applicable +* to the Software ('License Agreement') or upon express written consent of +* Trident. Any copying, reproduction or redistribution of the Software in +* whole or in part by any means not in accordance with the License Agreement +* or as agreed in writing by Trident is expressly prohibited. +* +* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE +* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE +* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND +* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES +* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT +* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL +* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY +* TO USE THE SOFTWARE. +* +* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, +* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, +* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS +* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE +* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM +* TRIDENT'S NEGLIGENCE. $ +* +*/ +#ifndef __BSP_TYPES_H__ +#define __BSP_TYPES_H__ +/*------------------------------------------------------------------------- +INCLUDES +-------------------------------------------------------------------------*/ + +#ifdef __cplusplus +extern "C" { +#endif +/*------------------------------------------------------------------------- +TYPEDEFS +-------------------------------------------------------------------------*/ + +/** +* \typedef unsigned char u8_t +* \brief type definition of an unsigned 8 bits integer +*/ +typedef unsigned char u8_t; +/** +* \typedef char s8_t +* \brief type definition of a signed 8 bits integer +*/ +typedef char s8_t; +/** +* \typedef unsigned short u16_t *pu16_t +* \brief type definition of an unsigned 16 bits integer +*/ +typedef unsigned short u16_t; +/** +* \typedef short s16_t +* \brief type definition of a signed 16 bits integer +*/ +typedef short s16_t; +/** +* \typedef unsigned long u32_t +* \brief type definition of an unsigned 32 bits integer +*/ +typedef unsigned long u32_t; +/** +* \typedef long s32_t +* \brief type definition of a signed 32 bits integer +*/ +typedef long s32_t; +/* +* \typedef struct ... u64_t +* \brief type definition of an usigned 64 bits integer +*/ +typedef struct { + u32_t MSLW; + u32_t LSLW; +} u64_t; +/* +* \typedef struct ... i64_t +* \brief type definition of a signed 64 bits integer +*/ +typedef struct { + s32_t MSLW; + u32_t LSLW; +} s64_t; + +/** +* \typedef u8_t *pu8_t +* \brief type definition of pointer to an unsigned 8 bits integer +*/ +typedef u8_t *pu8_t; +/** +* \typedef s8_t *ps8_t +* \brief type definition of pointer to a signed 8 bits integer +*/ +typedef s8_t *ps8_t; +/** +* \typedef u16_t *pu16_t +* \brief type definition of pointer to an unsigned 16 bits integer +*/ +typedef u16_t *pu16_t; +/** +* \typedef s16_t *ps16_t +* \brief type definition of pointer to a signed 16 bits integer +*/ +typedef s16_t *ps16_t; +/** +* \typedef u32_t *pu32_t +* \brief type definition of pointer to an unsigned 32 bits integer +*/ +typedef u32_t *pu32_t; +/** +* \typedef s32_t *ps32_t +* \brief type definition of pointer to a signed 32 bits integer +*/ +typedef s32_t *ps32_t; +/** +* \typedef u64_t *pu64_t +* \brief type definition of pointer to an usigned 64 bits integer +*/ +typedef u64_t *pu64_t; +/** +* \typedef s64_t *ps64_t +* \brief type definition of pointer to a signed 64 bits integer +*/ +typedef s64_t *ps64_t; + + +/** +* \typedef s32_t DRXFrequency_t +* \brief type definition of frequency +*/ +typedef s32_t DRXFrequency_t; + +/** +* \typedef DRXFrequency_t *pDRXFrequency_t +* \brief type definition of a pointer to a frequency +*/ +typedef DRXFrequency_t *pDRXFrequency_t; + +/** +* \typedef u32_t DRXSymbolrate_t +* \brief type definition of symbol rate +*/ +typedef u32_t DRXSymbolrate_t; + +/** +* \typedef DRXSymbolrate_t *pDRXSymbolrate_t +* \brief type definition of a pointer to a symbol rate +*/ +typedef DRXSymbolrate_t *pDRXSymbolrate_t; + +/*------------------------------------------------------------------------- +DEFINES +-------------------------------------------------------------------------*/ +/** +* \def NULL +* \brief Define NULL for target. +*/ +#ifndef NULL +#define NULL (0) +#endif + +/*------------------------------------------------------------------------- +ENUM +-------------------------------------------------------------------------*/ + +/* +* Boolean datatype. Only define if not already defined TRUE or FALSE. +*/ +#if defined (TRUE) || defined (FALSE) +typedef int Bool_t; +#else +/** +* \enum Bool_t +* \brief Boolean type +*/ +typedef enum { + FALSE = 0, + TRUE +} Bool_t; +#endif +typedef Bool_t *pBool_t; + +/** +* \enum DRXStatus_t +* \brief Various return statusses +*/ +typedef enum { + DRX_STS_READY = 3, /**< device/service is ready */ + DRX_STS_BUSY = 2, /**< device/service is busy */ + DRX_STS_OK = 1, /**< everything is OK */ + DRX_STS_INVALID_ARG = -1, /**< invalid arguments */ + DRX_STS_ERROR = -2, /**< general error */ + DRX_STS_FUNC_NOT_AVAILABLE = -3 /**< unavailable functionality */ +} DRXStatus_t, *pDRXStatus_t; + + +/*------------------------------------------------------------------------- +STRUCTS +-------------------------------------------------------------------------*/ + +/** +Exported FUNCTIONS +-------------------------------------------------------------------------*/ + +/*------------------------------------------------------------------------- +THE END +-------------------------------------------------------------------------*/ +#ifdef __cplusplus +} +#endif +#endif /* __BSP_TYPES_H__ */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c new file mode 100644 index 0000000..524c07d --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c @@ -0,0 +1,456 @@ +/* + * Driver for Micronas DRX39xx family (drx3933j) + * + * Written by Devin Heitmueller + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.= + */ + +#include +#include +#include +#include + +#include "dvb_frontend.h" +#include "drx39xxj.h" +#include "drx_driver.h" +#include "bsp_types.h" +#include "bsp_tuner.h" +#include "drxj_mc.h" +#include "drxj.h" + +static int drx39xxj_set_powerstate(struct dvb_frontend* fe, int enable) +{ + struct drx39xxj_state *state = fe->demodulator_priv; + DRXDemodInstance_t *demod = state->demod; + DRXStatus_t result; + DRXPowerMode_t powerMode; + + if (enable) + powerMode = DRX_POWER_UP; + else + powerMode = DRX_POWER_DOWN; + + result = DRX_Ctrl(demod, DRX_CTRL_POWER_MODE, &powerMode); + if (result != DRX_STS_OK) { + printk("Power state change failed\n"); + return 0; + } + + state->powered_up = enable; + return 0; +} + +static int drx39xxj_read_status(struct dvb_frontend* fe, fe_status_t* status) +{ + struct drx39xxj_state* state = fe->demodulator_priv; + DRXDemodInstance_t *demod = state->demod; + DRXStatus_t result; + DRXLockStatus_t lock_status; + + *status = 0; + + result = DRX_Ctrl(demod, DRX_CTRL_LOCK_STATUS, &lock_status); + if (result != DRX_STS_OK) { + printk("drx39xxj: could not get lock status!\n"); + *status = 0; + } + + switch (lock_status) { + case DRX_NEVER_LOCK: + *status = 0; + printk("drx says NEVER_LOCK\n"); + break; + case DRX_NOT_LOCKED: + *status = 0; + break; + case DRX_LOCK_STATE_1: + case DRX_LOCK_STATE_2: + case DRX_LOCK_STATE_3: + case DRX_LOCK_STATE_4: + case DRX_LOCK_STATE_5: + case DRX_LOCK_STATE_6: + case DRX_LOCK_STATE_7: + case DRX_LOCK_STATE_8: + case DRX_LOCK_STATE_9: + *status = FE_HAS_SIGNAL + | FE_HAS_CARRIER + | FE_HAS_VITERBI + | FE_HAS_SYNC; + break; + case DRX_LOCKED: + *status = FE_HAS_SIGNAL + | FE_HAS_CARRIER + | FE_HAS_VITERBI + | FE_HAS_SYNC + | FE_HAS_LOCK; + break; + default: + printk("Lock state unknown %d\n", lock_status); + } + + return 0; +} + +static int drx39xxj_read_ber(struct dvb_frontend* fe, u32* ber) +{ + struct drx39xxj_state* state = fe->demodulator_priv; + DRXDemodInstance_t *demod = state->demod; + DRXStatus_t result; + DRXSigQuality_t sig_quality; + + result = DRX_Ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); + if (result != DRX_STS_OK) { + printk("drx39xxj: could not get ber!\n"); + *ber = 0; + return 0; + } + + *ber = sig_quality.postReedSolomonBER; + return 0; +} + +static int drx39xxj_read_signal_strength(struct dvb_frontend* fe, u16* strength) +{ + struct drx39xxj_state* state = fe->demodulator_priv; + DRXDemodInstance_t *demod = state->demod; + DRXStatus_t result; + DRXSigQuality_t sig_quality; + + result = DRX_Ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); + if (result != DRX_STS_OK) { + printk("drx39xxj: could not get signal strength!\n"); + *strength = 0; + return 0; + } + + /* 1-100% scaled to 0-65535 */ + *strength = (sig_quality.indicator * 65535 / 100); + return 0; +} + +static int drx39xxj_read_snr(struct dvb_frontend* fe, u16* snr) +{ + struct drx39xxj_state* state = fe->demodulator_priv; + DRXDemodInstance_t *demod = state->demod; + DRXStatus_t result; + DRXSigQuality_t sig_quality; + + result = DRX_Ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); + if (result != DRX_STS_OK) { + printk("drx39xxj: could not read snr!\n"); + *snr = 0; + return 0; + } + + *snr = sig_quality.MER; + return 0; +} + +static int drx39xxj_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks) +{ + struct drx39xxj_state* state = fe->demodulator_priv; + DRXDemodInstance_t *demod = state->demod; + DRXStatus_t result; + DRXSigQuality_t sig_quality; + + result = DRX_Ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); + if (result != DRX_STS_OK) { + printk("drx39xxj: could not get uc blocks!\n"); + *ucblocks = 0; + return 0; + } + + *ucblocks = sig_quality.packetError; + return 0; +} + +static int drx39xxj_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p) +{ + return 0; +} + +static int drx39xxj_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p) +{ +#ifdef DJH_DEBUG + int i; +#endif + struct drx39xxj_state* state = fe->demodulator_priv; + DRXDemodInstance_t *demod = state->demod; + DRXStandard_t standard = DRX_STANDARD_8VSB; + DRXChannel_t channel; + DRXStatus_t result; + DRXUIOData_t uioData; + DRXChannel_t defChannel = {/* frequency */ 0, + /* bandwidth */ DRX_BANDWIDTH_6MHZ, + /* mirror */ DRX_MIRROR_NO, + /* constellation */ DRX_CONSTELLATION_AUTO, + /* hierarchy */ DRX_HIERARCHY_UNKNOWN, + /* priority */ DRX_PRIORITY_UNKNOWN, + /* coderate */ DRX_CODERATE_UNKNOWN, + /* guard */ DRX_GUARD_UNKNOWN, + /* fftmode */ DRX_FFTMODE_UNKNOWN, + /* classification */ DRX_CLASSIFICATION_AUTO, + /* symbolrate */ 5057000, + /* interleavemode */ DRX_INTERLEAVEMODE_UNKNOWN, + /* ldpc */ DRX_LDPC_UNKNOWN, + /* carrier */ DRX_CARRIER_UNKNOWN, + /* frame mode */ DRX_FRAMEMODE_UNKNOWN + }; + + /* Bring the demod out of sleep */ + drx39xxj_set_powerstate(fe, 1); + + /* Now make the tuner do it's thing... */ + if (fe->ops.tuner_ops.set_params) { + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + fe->ops.tuner_ops.set_params(fe, p); + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 0); + } + + if (standard != state->current_standard || state->powered_up == 0) { + /* Set the standard (will be powered up if necessary */ + result = DRX_Ctrl(demod, DRX_CTRL_SET_STANDARD, &standard); + if (result != DRX_STS_OK) { + printk("Failed to set standard! result=%02x\n", result); + return -EINVAL; + } + state->powered_up = 1; + state->current_standard = standard; + } + + /* set channel parameters */ + channel = defChannel; + channel.frequency = p->frequency / 1000; + channel.bandwidth = DRX_BANDWIDTH_6MHZ; + channel.constellation = DRX_CONSTELLATION_AUTO; + + /* program channel */ + result = DRX_Ctrl(demod, DRX_CTRL_SET_CHANNEL, &channel); + if (result != DRX_STS_OK) { + printk("Failed to set channel!\n"); + return -EINVAL; + } + + // Just for giggles, let's shut off the LNA again.... + uioData.uio = DRX_UIO1; + uioData.value = FALSE; + result = DRX_Ctrl(demod, DRX_CTRL_UIO_WRITE, &uioData); + if (result != DRX_STS_OK) { + printk("Failed to disable LNA!\n"); + return 0; + } + +#ifdef DJH_DEBUG + for(i = 0; i < 2000; i++) { + fe_status_t status; + drx39xxj_read_status(fe, &status); + printk("i=%d status=%d\n", i, status); + msleep(100); + i += 100; + } +#endif + + return 0; +} + + +static int drx39xxj_sleep(struct dvb_frontend* fe) +{ + /* power-down the demodulator */ + return drx39xxj_set_powerstate(fe, 0); +} + +static int drx39xxj_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) +{ + struct drx39xxj_state *state = fe->demodulator_priv; + DRXDemodInstance_t *demod = state->demod; + Bool_t i2c_gate_state; + DRXStatus_t result; + +#ifdef DJH_DEBUG + printk("i2c gate call: enable=%d state=%d\n", enable, + state->i2c_gate_open); +#endif + + if (enable) + i2c_gate_state = TRUE; + else + i2c_gate_state = FALSE; + + if (state->i2c_gate_open == enable) { + /* We're already in the desired state */ + return 0; + } + + result = DRX_Ctrl(demod, DRX_CTRL_I2C_BRIDGE, &i2c_gate_state); + if (result != DRX_STS_OK) { + printk("drx39xxj: could not open i2c gate [%d]\n", result); + dump_stack(); + } else { + state->i2c_gate_open = enable; + } + return 0; +} + + +static int drx39xxj_init(struct dvb_frontend* fe) +{ + /* Bring the demod out of sleep */ + drx39xxj_set_powerstate(fe, 1); + + return 0; +} + +static int drx39xxj_get_tune_settings(struct dvb_frontend *fe, + struct dvb_frontend_tune_settings *tune) +{ + tune->min_delay_ms = 1000; + return 0; +} + +static void drx39xxj_release(struct dvb_frontend* fe) +{ + struct drx39xxj_state* state = fe->demodulator_priv; + kfree(state); +} + +static struct dvb_frontend_ops drx39xxj_ops; + +struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) +{ + struct drx39xxj_state* state = NULL; + + I2CDeviceAddr_t *demodAddr = NULL; + DRXCommonAttr_t *demodCommAttr = NULL; + DRXJData_t *demodExtAttr = NULL; + DRXDemodInstance_t *demod = NULL; + DRXUIOCfg_t uioCfg; + DRXUIOData_t uioData; + DRXStatus_t result; + + /* allocate memory for the internal state */ + state = kmalloc(sizeof(struct drx39xxj_state), GFP_KERNEL); + if (state == NULL) goto error; + + demod = kmalloc(sizeof(DRXDemodInstance_t), GFP_KERNEL); + if (demod == NULL) goto error; + + demodAddr = kmalloc(sizeof(I2CDeviceAddr_t), GFP_KERNEL); + if (demodAddr == NULL) goto error; + + demodCommAttr = kmalloc(sizeof(DRXCommonAttr_t), GFP_KERNEL); + if (demodCommAttr == NULL) goto error; + + demodExtAttr = kmalloc(sizeof(DRXJData_t), GFP_KERNEL); + if (demodExtAttr == NULL) goto error; + + /* setup the state */ + state->i2c = i2c; + state->demod = demod; + + memcpy(demod, &DRXJDefaultDemod_g, sizeof(DRXDemodInstance_t)); + + demod->myI2CDevAddr = demodAddr; + memcpy(demod->myI2CDevAddr, &DRXJDefaultAddr_g, + sizeof(I2CDeviceAddr_t)); + demod->myI2CDevAddr->userData = state; + demod->myCommonAttr = demodCommAttr; + memcpy(demod->myCommonAttr, &DRXJDefaultCommAttr_g, + sizeof(DRXCommonAttr_t)); + demod->myCommonAttr->microcode = DRXJ_MC_MAIN; + // demod->myCommonAttr->verifyMicrocode = FALSE; + demod->myCommonAttr->verifyMicrocode = TRUE; + demod->myCommonAttr->intermediateFreq = 5000; + + demod->myExtAttr = demodExtAttr; + memcpy(demod->myExtAttr, &DRXJData_g, sizeof(DRXJData_t)); + ((DRXJData_t *) demod->myExtAttr)->uioSmaTxMode = DRX_UIO_MODE_READWRITE; + + demod->myTuner = NULL; + + result = DRX_Open(demod); + if (result != DRX_STS_OK) { + printk("DRX open failed! Aborting\n"); + kfree(state); + return NULL; + } + + /* Turn off the LNA */ + uioCfg.uio = DRX_UIO1; + uioCfg.mode = DRX_UIO_MODE_READWRITE; + /* Configure user-I/O #3: enable read/write */ + result = DRX_Ctrl(demod, DRX_CTRL_UIO_CFG, &uioCfg); + if (result != DRX_STS_OK) { + printk("Failed to setup LNA GPIO!\n"); + return NULL; + } + + uioData.uio = DRX_UIO1; + uioData.value = FALSE; + result = DRX_Ctrl(demod, DRX_CTRL_UIO_WRITE, &uioData); + if (result != DRX_STS_OK) { + printk("Failed to disable LNA!\n"); + return NULL; + } + + /* create dvb_frontend */ + memcpy(&state->frontend.ops, &drx39xxj_ops, + sizeof(struct dvb_frontend_ops)); + + state->frontend.demodulator_priv = state; + return &state->frontend; + +error: + if (state != NULL) + kfree(state); + if (demod != NULL) + kfree(demod); + return NULL; +} + +static struct dvb_frontend_ops drx39xxj_ops = { + + .info = { + .name = "Micronas DRX39xxj family Frontend", + .type = FE_ATSC | FE_QAM, + .frequency_stepsize = 62500, + .frequency_min = 51000000, + .frequency_max = 858000000, + .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB + }, + + .init = drx39xxj_init, + .i2c_gate_ctrl = drx39xxj_i2c_gate_ctrl, + .sleep = drx39xxj_sleep, + .set_frontend = drx39xxj_set_frontend, + .get_frontend = drx39xxj_get_frontend, + .get_tune_settings = drx39xxj_get_tune_settings, + .read_status = drx39xxj_read_status, + .read_ber = drx39xxj_read_ber, + .read_signal_strength = drx39xxj_read_signal_strength, + .read_snr = drx39xxj_read_snr, + .read_ucblocks = drx39xxj_read_ucblocks, + .release = drx39xxj_release, +}; + +MODULE_DESCRIPTION("Micronas DRX39xxj Frontend"); +MODULE_AUTHOR("Devin Heitmueller"); +MODULE_LICENSE("GPL"); + +EXPORT_SYMBOL(drx39xxj_attach); diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h new file mode 100644 index 0000000..eea6a01a --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h @@ -0,0 +1,40 @@ +/* + * Driver for Micronas DRX39xx family (drx3933j) + * + * Written by Devin Heitmueller + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.= + */ + +#ifndef DRX39XXJ_H +#define DRX39XXJ_H + +#include +#include "dvb_frontend.h" +#include "drx_driver.h" + +struct drx39xxj_state { + struct i2c_adapter *i2c; + DRXDemodInstance_t *demod; + DRXStandard_t current_standard; + struct dvb_frontend frontend; + int powered_up:1; + unsigned int i2c_gate_open:1; +}; + +extern struct dvb_frontend* drx39xxj_attach(struct i2c_adapter *i2c); + +#endif // DVB_DUMMY_FE_H diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c b/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c new file mode 100644 index 0000000..2b9344f --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c @@ -0,0 +1,134 @@ +#include +#include +#include +#include +#include +#include +#include +#include + +#include "drx_driver.h" +#include "bsp_types.h" +#include "bsp_tuner.h" +#include "drx39xxj.h" + +/* Dummy function to satisfy drxj.c */ +DRXStatus_t DRXBSP_TUNER_Open( pTUNERInstance_t tuner ) +{ + return DRX_STS_OK; +} + +DRXStatus_t DRXBSP_TUNER_Close( pTUNERInstance_t tuner ) +{ + return DRX_STS_OK; +} + +DRXStatus_t DRXBSP_TUNER_SetFrequency( pTUNERInstance_t tuner, + TUNERMode_t mode, + DRXFrequency_t centerFrequency ) +{ + return DRX_STS_OK; +} + +DRXStatus_t +DRXBSP_TUNER_GetFrequency( pTUNERInstance_t tuner, + TUNERMode_t mode, + pDRXFrequency_t RFfrequency, + pDRXFrequency_t IFfrequency ) +{ + return DRX_STS_OK; +} + +DRXStatus_t DRXBSP_HST_Sleep( u32_t n ) +{ + msleep(n); + return DRX_STS_OK; +} + +u32_t DRXBSP_HST_Clock( void ) +{ + return jiffies_to_msecs(jiffies); +} + +int DRXBSP_HST_Memcmp( void *s1, void *s2, u32_t n) +{ + return ( memcmp( s1, s2, (size_t) n) ); +} + +void* DRXBSP_HST_Memcpy( void *to, void *from, u32_t n) +{ + return ( memcpy( to, from, (size_t) n) ); +} + +DRXStatus_t DRXBSP_I2C_WriteRead( pI2CDeviceAddr_t wDevAddr, + u16_t wCount, + pu8_t wData, + pI2CDeviceAddr_t rDevAddr, + u16_t rCount, + pu8_t rData ) +{ + struct drx39xxj_state *state; + struct i2c_msg msg[2]; + unsigned int num_msgs; + + if (wDevAddr == NULL) { + /* Read only */ + state = rDevAddr->userData; + msg[0].addr = rDevAddr->i2cAddr >> 1; + msg[0].flags = I2C_M_RD; + msg[0].buf = rData; + msg[0].len = rCount; + num_msgs = 1; + } else if (rDevAddr == NULL) { + /* Write only */ + state = wDevAddr->userData; + msg[0].addr = wDevAddr->i2cAddr >> 1; + msg[0].flags = 0; + msg[0].buf = wData; + msg[0].len = wCount; + num_msgs = 1; + } else { + /* Both write and read */ + state = wDevAddr->userData; + msg[0].addr = wDevAddr->i2cAddr >> 1; + msg[0].flags = 0; + msg[0].buf = wData; + msg[0].len = wCount; + msg[1].addr = rDevAddr->i2cAddr >> 1; + msg[1].flags = I2C_M_RD; + msg[1].buf = rData; + msg[1].len = rCount; + num_msgs = 2; + } + + if (state->i2c == NULL) { + printk("i2c was zero, aborting\n"); + return 0; + } + if (i2c_transfer(state->i2c, msg, num_msgs) != num_msgs) { + printk(KERN_WARNING "drx3933: I2C write/read failed\n"); + return -EREMOTEIO; + } + + return DRX_STS_OK; + +#ifdef DJH_DEBUG + struct drx39xxj_state *state = wDevAddr->userData; + + struct i2c_msg msg[2] = { + { .addr = wDevAddr->i2cAddr, + .flags = 0, .buf = wData, .len = wCount }, + { .addr = rDevAddr->i2cAddr, + .flags = I2C_M_RD, .buf = rData, .len = rCount }, + }; + + printk("drx3933 i2c operation addr=%x i2c=%p, wc=%x rc=%x\n", + wDevAddr->i2cAddr, state->i2c, wCount, rCount); + + if (i2c_transfer(state->i2c, msg, 2) != 2) { + printk(KERN_WARNING "drx3933: I2C write/read failed\n"); + return -EREMOTEIO; + } +#endif + return 0; +} diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c new file mode 100644 index 0000000..cc10dae --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c @@ -0,0 +1,674 @@ +/******************************************************************************* +* FILENAME: $Id: drx_dap_fasi.c,v 1.7 2009/12/28 14:36:21 carlo Exp $ +* +* DESCRIPTION: +* Part of DRX driver. +* Data access protocol: Fast Access Sequential Interface (fasi) +* Fast access, because of short addressing format (16 instead of 32 bits addr) +* Sequential, because of I2C. +* These functions know how the chip's memory and registers are to be accessed, +* but nothing more. +* +* These functions should not need adapting to a new platform. +* +* USAGE: +* - +* +* NOTES: +* $(c) 2009 Trident Microsystems, Inc. - All rights reserved. +* +* This software and related documentation (the 'Software') are intellectual +* property owned by Trident and are copyright of Trident, unless specifically +* noted otherwise. +* +* Any use of the Software is permitted only pursuant to the terms of the +* license agreement, if any, which accompanies, is included with or applicable +* to the Software ('License Agreement') or upon express written consent of +* Trident. Any copying, reproduction or redistribution of the Software in +* whole or in part by any means not in accordance with the License Agreement +* or as agreed in writing by Trident is expressly prohibited. +* +* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE +* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE +* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND +* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES +* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT +* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL +* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY +* TO USE THE SOFTWARE. +* +* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, +* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, +* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS +* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE +* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM +* TRIDENT'S NEGLIGENCE. $ +* +* +*******************************************************************************/ + +#include "drx_dap_fasi.h" +#include "bsp_host.h" /* for DRXBSP_HST_Memcpy() */ + +/*============================================================================*/ + +/* Function prototypes */ +static DRXStatus_t DRXDAP_FASI_WriteBlock ( + pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register/memory */ + u16_t datasize, /* size of data */ + pu8_t data, /* data to send */ + DRXflags_t flags); /* special device flags */ + +static DRXStatus_t DRXDAP_FASI_ReadBlock ( + pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register/memory */ + u16_t datasize, /* size of data */ + pu8_t data, /* data to send */ + DRXflags_t flags); /* special device flags */ + +static DRXStatus_t DRXDAP_FASI_WriteReg8 ( + pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register */ + u8_t data, /* data to write */ + DRXflags_t flags); /* special device flags */ + +static DRXStatus_t DRXDAP_FASI_ReadReg8 ( + pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register */ + pu8_t data, /* buffer to receive data */ + DRXflags_t flags); /* special device flags */ + +static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg8 ( + pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t waddr, /* address of register */ + DRXaddr_t raddr, /* address to read back from */ + u8_t datain, /* data to send */ + pu8_t dataout); /* data to receive back */ + +static DRXStatus_t DRXDAP_FASI_WriteReg16 ( + pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register */ + u16_t data, /* data to write */ + DRXflags_t flags); /* special device flags */ + +static DRXStatus_t DRXDAP_FASI_ReadReg16 ( + pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register */ + pu16_t data, /* buffer to receive data */ + DRXflags_t flags); /* special device flags */ + +static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg16 ( + pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t waddr, /* address of register */ + DRXaddr_t raddr, /* address to read back from */ + u16_t datain, /* data to send */ + pu16_t dataout); /* data to receive back */ + +static DRXStatus_t DRXDAP_FASI_WriteReg32 ( + pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register */ + u32_t data, /* data to write */ + DRXflags_t flags); /* special device flags */ + +static DRXStatus_t DRXDAP_FASI_ReadReg32 ( + pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register */ + pu32_t data, /* buffer to receive data */ + DRXflags_t flags); /* special device flags */ + +static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg32 ( + pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t waddr, /* address of register */ + DRXaddr_t raddr, /* address to read back from */ + u32_t datain, /* data to send */ + pu32_t dataout); /* data to receive back */ + +/* The version structure of this protocol implementation */ +char drxDapFASIModuleName[] = "FASI Data Access Protocol"; +char drxDapFASIVersionText[] = ""; + +DRXVersion_t drxDapFASIVersion = +{ + DRX_MODULE_DAP, /**< type identifier of the module */ + drxDapFASIModuleName, /**< name or description of module */ + + 0, /**< major version number */ + 0, /**< minor version number */ + 0, /**< patch version number */ + drxDapFASIVersionText /**< version as text string */ +}; + +/* The structure containing the protocol interface */ +DRXAccessFunc_t drxDapFASIFunct_g = +{ + &drxDapFASIVersion, + DRXDAP_FASI_WriteBlock, /* Supported */ + DRXDAP_FASI_ReadBlock, /* Supported */ + DRXDAP_FASI_WriteReg8, /* Not supported */ + DRXDAP_FASI_ReadReg8, /* Not supported */ + DRXDAP_FASI_ReadModifyWriteReg8, /* Not supported */ + DRXDAP_FASI_WriteReg16, /* Supported */ + DRXDAP_FASI_ReadReg16, /* Supported */ + DRXDAP_FASI_ReadModifyWriteReg16, /* Supported */ + DRXDAP_FASI_WriteReg32, /* Supported */ + DRXDAP_FASI_ReadReg32, /* Supported */ + DRXDAP_FASI_ReadModifyWriteReg32 /* Not supported */ +}; + +/*============================================================================*/ + +/* Functions not supported by protocol*/ + +static DRXStatus_t DRXDAP_FASI_WriteReg8 ( + pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register */ + u8_t data, /* data to write */ + DRXflags_t flags) /* special device flags */ +{ + return DRX_STS_ERROR; +} + +static DRXStatus_t DRXDAP_FASI_ReadReg8 ( + pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register */ + pu8_t data, /* buffer to receive data */ + DRXflags_t flags) /* special device flags */ +{ + return DRX_STS_ERROR; +} + +static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg8 ( + pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t waddr, /* address of register */ + DRXaddr_t raddr, /* address to read back from */ + u8_t datain, /* data to send */ + pu8_t dataout) /* data to receive back */ +{ + return DRX_STS_ERROR; +} + +static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg32 ( + pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t waddr, /* address of register */ + DRXaddr_t raddr, /* address to read back from */ + u32_t datain, /* data to send */ + pu32_t dataout) /* data to receive back */ +{ + return DRX_STS_ERROR; +} + +/*============================================================================*/ + +/****************************** +* +* DRXStatus_t DRXDAP_FASI_ReadBlock ( +* pI2CDeviceAddr_t devAddr, -- address of I2C device +* DRXaddr_t addr, -- address of chip register/memory +* u16_t datasize, -- number of bytes to read +* pu8_t data, -- data to receive +* DRXflags_t flags) -- special device flags +* +* Read block data from chip address. Because the chip is word oriented, +* the number of bytes to read must be even. +* +* Make sure that the buffer to receive the data is large enough. +* +* Although this function expects an even number of bytes, it is still byte +* oriented, and the data read back is NOT translated to the endianness of +* the target platform. +* +* Output: +* - DRX_STS_OK if reading was successful +* in that case: data read is in *data. +* - DRX_STS_ERROR if anything went wrong +* +******************************/ + +static DRXStatus_t DRXDAP_FASI_ReadBlock ( pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + u16_t datasize, + pu8_t data, + DRXflags_t flags ) +{ + u8_t buf[4]; + u16_t bufx; + DRXStatus_t rc; + u16_t overheadSize = 0; + + /* Check parameters ********************************************************/ + if ( devAddr == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + overheadSize = (IS_I2C_10BIT (devAddr->i2cAddr) ? 2 : 1) + + (DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2 ); + + if ( ( DRXDAP_FASI_OFFSET_TOO_LARGE(addr) ) || + ( ( !(DRXDAPFASI_LONG_ADDR_ALLOWED) ) && + DRXDAP_FASI_LONG_FORMAT( addr ) ) || + (overheadSize > (DRXDAP_MAX_WCHUNKSIZE)) || + ((datasize!=0) && (data==NULL)) || + ((datasize & 1)==1 ) ) + { + return DRX_STS_INVALID_ARG; + } + + /* ReadModifyWrite & mode flag bits are not allowed */ + flags &= (~DRXDAP_FASI_RMW & ~DRXDAP_FASI_MODEFLAGS); +#if DRXDAP_SINGLE_MASTER + flags |= DRXDAP_FASI_SINGLE_MASTER; +#endif + + /* Read block from I2C *****************************************************/ + do { + u16_t todo = ( datasize < DRXDAP_MAX_RCHUNKSIZE ? + datasize : DRXDAP_MAX_RCHUNKSIZE); + + bufx = 0; + + addr &= ~DRXDAP_FASI_FLAGS; + addr |= flags; + +#if ( ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 ) && \ + ( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 ) ) + /* short format address preferred but long format otherwise */ + if ( DRXDAP_FASI_LONG_FORMAT(addr) ) + { +#endif +#if ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 ) + buf[bufx++] = (u8_t) (((addr << 1) & 0xFF)|0x01); + buf[bufx++] = (u8_t) ((addr >> 16) & 0xFF); + buf[bufx++] = (u8_t) ((addr >> 24) & 0xFF); + buf[bufx++] = (u8_t) ((addr >> 7) & 0xFF); +#endif +#if ( ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 ) && \ + ( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 ) ) + } else { +#endif +#if ( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 ) + buf[bufx++] = (u8_t) ((addr << 1) & 0xFF); + buf[bufx++] = (u8_t) ( ((addr >> 16) & 0x0F) | ((addr >> 18) & 0xF0) ); +#endif +#if ( ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 ) && \ + ( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 ) ) + } +#endif + + + + +#if DRXDAP_SINGLE_MASTER + /* + * In single master mode, split the read and write actions. + * No special action is needed for write chunks here. + */ + rc = DRXBSP_I2C_WriteRead (devAddr, bufx, buf, 0, 0, 0); + if (rc == DRX_STS_OK) + { + rc = DRXBSP_I2C_WriteRead (0, 0, 0, devAddr, todo, data); + } +#else + /* In multi master mode, do everything in one RW action */ + rc = DRXBSP_I2C_WriteRead (devAddr, bufx, buf, devAddr, todo, data); +#endif + data += todo; + addr += (todo >> 1); + datasize -= todo; + } while (datasize && rc == DRX_STS_OK); + + return rc; +} + + + + +/****************************** +* +* DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg16 ( +* pI2CDeviceAddr_t devAddr, -- address of I2C device +* DRXaddr_t waddr, -- address of chip register/memory +* DRXaddr_t raddr, -- chip address to read back from +* u16_t wdata, -- data to send +* pu16_t rdata) -- data to receive back +* +* Write 16-bit data, then read back the original contents of that location. +* Requires long addressing format to be allowed. +* +* Before sending data, the data is converted to little endian. The +* data received back is converted back to the target platform's endianness. +* +* WARNING: This function is only guaranteed to work if there is one +* master on the I2C bus. +* +* Output: +* - DRX_STS_OK if reading was successful +* in that case: read back data is at *rdata +* - DRX_STS_ERROR if anything went wrong +* +******************************/ + +static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg16 ( pI2CDeviceAddr_t devAddr, + DRXaddr_t waddr, + DRXaddr_t raddr, + u16_t wdata, + pu16_t rdata ) +{ + DRXStatus_t rc=DRX_STS_ERROR; + +#if ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 ) + if (rdata == NULL) + { + return DRX_STS_INVALID_ARG; + } + + rc = DRXDAP_FASI_WriteReg16 (devAddr, waddr, wdata, DRXDAP_FASI_RMW); + if (rc == DRX_STS_OK) + { + rc = DRXDAP_FASI_ReadReg16 (devAddr, raddr, rdata, 0); + } +#endif + + return rc; +} + + + + +/****************************** +* +* DRXStatus_t DRXDAP_FASI_ReadReg16 ( +* pI2CDeviceAddr_t devAddr, -- address of I2C device +* DRXaddr_t addr, -- address of chip register/memory +* pu16_t data, -- data to receive +* DRXflags_t flags) -- special device flags +* +* Read one 16-bit register or memory location. The data received back is +* converted back to the target platform's endianness. +* +* Output: +* - DRX_STS_OK if reading was successful +* in that case: read data is at *data +* - DRX_STS_ERROR if anything went wrong +* +******************************/ + +static DRXStatus_t DRXDAP_FASI_ReadReg16 ( pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + pu16_t data, + DRXflags_t flags ) +{ + u8_t buf[sizeof (*data)]; + DRXStatus_t rc; + + if (!data) + { + return DRX_STS_INVALID_ARG; + } + rc = DRXDAP_FASI_ReadBlock (devAddr, addr, sizeof (*data), buf, flags); + *data = buf[0] + (((u16_t) buf[1]) << 8); + return rc; +} + + + + +/****************************** +* +* DRXStatus_t DRXDAP_FASI_ReadReg32 ( +* pI2CDeviceAddr_t devAddr, -- address of I2C device +* DRXaddr_t addr, -- address of chip register/memory +* pu32_t data, -- data to receive +* DRXflags_t flags) -- special device flags +* +* Read one 32-bit register or memory location. The data received back is +* converted back to the target platform's endianness. +* +* Output: +* - DRX_STS_OK if reading was successful +* in that case: read data is at *data +* - DRX_STS_ERROR if anything went wrong +* +******************************/ + +static DRXStatus_t DRXDAP_FASI_ReadReg32 ( pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + pu32_t data, + DRXflags_t flags ) +{ + u8_t buf[sizeof (*data)]; + DRXStatus_t rc; + + if (!data) + { + return DRX_STS_INVALID_ARG; + } + rc = DRXDAP_FASI_ReadBlock (devAddr, addr, sizeof (*data), buf, flags); + *data = (((u32_t) buf[0]) << 0) + + (((u32_t) buf[1]) << 8) + + (((u32_t) buf[2]) << 16) + + (((u32_t) buf[3]) << 24); + return rc; +} + + + + +/****************************** +* +* DRXStatus_t DRXDAP_FASI_WriteBlock ( +* pI2CDeviceAddr_t devAddr, -- address of I2C device +* DRXaddr_t addr, -- address of chip register/memory +* u16_t datasize, -- number of bytes to read +* pu8_t data, -- data to receive +* DRXflags_t flags) -- special device flags +* +* Write block data to chip address. Because the chip is word oriented, +* the number of bytes to write must be even. +* +* Although this function expects an even number of bytes, it is still byte +* oriented, and the data being written is NOT translated from the endianness of +* the target platform. +* +* Output: +* - DRX_STS_OK if writing was successful +* - DRX_STS_ERROR if anything went wrong +* +******************************/ + +static DRXStatus_t DRXDAP_FASI_WriteBlock ( pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + u16_t datasize, + pu8_t data, + DRXflags_t flags ) +{ + u8_t buf[ DRXDAP_MAX_WCHUNKSIZE ]; + DRXStatus_t st = DRX_STS_ERROR; + DRXStatus_t firstErr = DRX_STS_OK; + u16_t overheadSize = 0; + u16_t blockSize = 0; + + /* Check parameters ********************************************************/ + if ( devAddr == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + overheadSize = (IS_I2C_10BIT (devAddr->i2cAddr) ? 2 : 1) + + (DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2 ); + + if ( ( DRXDAP_FASI_OFFSET_TOO_LARGE(addr) ) || + ( ( !(DRXDAPFASI_LONG_ADDR_ALLOWED) ) && + DRXDAP_FASI_LONG_FORMAT( addr ) ) || + (overheadSize > (DRXDAP_MAX_WCHUNKSIZE)) || + ((datasize!=0) && (data==NULL)) || + ((datasize & 1)==1 ) ) + { + return DRX_STS_INVALID_ARG; + } + + flags &= DRXDAP_FASI_FLAGS; + flags &= ~DRXDAP_FASI_MODEFLAGS; +#if DRXDAP_SINGLE_MASTER + flags |= DRXDAP_FASI_SINGLE_MASTER; +#endif + + /* Write block to I2C ******************************************************/ + blockSize = ( (DRXDAP_MAX_WCHUNKSIZE) - overheadSize) & ~1; + do + { + u16_t todo = 0; + u16_t bufx = 0; + + /* Buffer device address */ + addr &= ~DRXDAP_FASI_FLAGS; + addr |= flags; +#if ( ( (DRXDAPFASI_LONG_ADDR_ALLOWED)==1 ) && \ + ( (DRXDAPFASI_SHORT_ADDR_ALLOWED)==1 ) ) + /* short format address preferred but long format otherwise */ + if ( DRXDAP_FASI_LONG_FORMAT(addr) ) + { +#endif +#if ( (DRXDAPFASI_LONG_ADDR_ALLOWED)==1 ) + buf[bufx++] = (u8_t) (((addr << 1) & 0xFF)|0x01); + buf[bufx++] = (u8_t) ((addr >> 16) & 0xFF); + buf[bufx++] = (u8_t) ((addr >> 24) & 0xFF); + buf[bufx++] = (u8_t) ((addr >> 7) & 0xFF); +#endif +#if ( ( (DRXDAPFASI_LONG_ADDR_ALLOWED)==1 ) && \ + ( (DRXDAPFASI_SHORT_ADDR_ALLOWED)==1 ) ) + } else { +#endif +#if ( (DRXDAPFASI_SHORT_ADDR_ALLOWED)==1 ) + buf[bufx++] = (u8_t) ((addr << 1) & 0xFF); + buf[bufx++] = (u8_t) ( ((addr >> 16) & 0x0F) | ((addr >> 18) & 0xF0) ); +#endif +#if ( ( (DRXDAPFASI_LONG_ADDR_ALLOWED)==1 ) && \ + ( (DRXDAPFASI_SHORT_ADDR_ALLOWED)==1 ) ) + } +#endif + + /* + In single master mode blockSize can be 0. In such a case this I2C + sequense will be visible: (1) write address {i2c addr, + 4 bytes chip address} (2) write data {i2c addr, 4 bytes data } + (3) write address (4) write data etc... + Addres must be rewriten because HI is reset after data transport and + expects an address. + */ + todo = (blockSize < datasize ? blockSize : datasize); + if (todo==0) + { + u16_t overheadSizeI2cAddr = 0; + u16_t dataBlockSize = 0; + + overheadSizeI2cAddr = (IS_I2C_10BIT (devAddr->i2cAddr) ? 2 : 1); + dataBlockSize = ( DRXDAP_MAX_WCHUNKSIZE - overheadSizeI2cAddr) & ~1; + + /* write device address */ + st = DRXBSP_I2C_WriteRead( devAddr, + (u16_t) (bufx), + buf, + (pI2CDeviceAddr_t)(NULL), + 0, + (pu8_t)(NULL) ); + + if ( ( st != DRX_STS_OK ) && ( firstErr == DRX_STS_OK ) ) + { + /* at the end, return the first error encountered */ + firstErr = st; + } + bufx = 0; + todo = (dataBlockSize < datasize ? dataBlockSize : datasize); + } + DRXBSP_HST_Memcpy (&buf[bufx], data, todo); + /* write (address if can do and) data */ + st = DRXBSP_I2C_WriteRead( devAddr, + (u16_t)(bufx + todo), + buf, + (pI2CDeviceAddr_t)(NULL), + 0, + (pu8_t)(NULL) ); + + if ( ( st != DRX_STS_OK ) && ( firstErr == DRX_STS_OK ) ) + { + /* at the end, return the first error encountered */ + firstErr = st; + } + datasize -= todo; + data += todo; + addr += (todo >> 1); + } while (datasize); + + return firstErr; +} + + + + +/****************************** +* +* DRXStatus_t DRXDAP_FASI_WriteReg16 ( +* pI2CDeviceAddr_t devAddr, -- address of I2C device +* DRXaddr_t addr, -- address of chip register/memory +* u16_t data, -- data to send +* DRXflags_t flags) -- special device flags +* +* Write one 16-bit register or memory location. The data being written is +* converted from the target platform's endianness to little endian. +* +* Output: +* - DRX_STS_OK if writing was successful +* - DRX_STS_ERROR if anything went wrong +* +******************************/ + +static DRXStatus_t DRXDAP_FASI_WriteReg16 ( pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + u16_t data, + DRXflags_t flags ) +{ + u8_t buf[sizeof (data)]; + + buf[0] = (u8_t) ( (data >> 0 ) & 0xFF ); + buf[1] = (u8_t) ( (data >> 8 ) & 0xFF ); + + return DRXDAP_FASI_WriteBlock (devAddr, addr, sizeof (data), buf, flags); +} + + + + +/****************************** +* +* DRXStatus_t DRXDAP_FASI_WriteReg32 ( +* pI2CDeviceAddr_t devAddr, -- address of I2C device +* DRXaddr_t addr, -- address of chip register/memory +* u32_t data, -- data to send +* DRXflags_t flags) -- special device flags +* +* Write one 32-bit register or memory location. The data being written is +* converted from the target platform's endianness to little endian. +* +* Output: +* - DRX_STS_OK if writing was successful +* - DRX_STS_ERROR if anything went wrong +* +******************************/ + +static DRXStatus_t DRXDAP_FASI_WriteReg32 ( pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + u32_t data, + DRXflags_t flags ) +{ + u8_t buf[sizeof (data)]; + + buf[0] = (u8_t) ( (data >> 0 ) & 0xFF ); + buf[1] = (u8_t) ( (data >> 8 ) & 0xFF ); + buf[2] = (u8_t) ( (data >> 16) & 0xFF ); + buf[3] = (u8_t) ( (data >> 24) & 0xFF ); + + return DRXDAP_FASI_WriteBlock (devAddr, addr, sizeof (data), buf, flags); +} diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.h b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.h new file mode 100644 index 0000000..77ff371 --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.h @@ -0,0 +1,267 @@ +/******************************************************************************* +* FILENAME: $Id: drx_dap_fasi.h,v 1.5 2009/07/07 14:21:40 justin Exp $ +* +* DESCRIPTION: +* Part of DRX driver. +* Data access protocol: Fast Access Sequential Interface (fasi) +* Fast access, because of short addressing format (16 instead of 32 bits addr) +* Sequential, because of I2C. +* +* USAGE: +* Include. +* +* NOTES: +* $(c) 2008-2009 Trident Microsystems, Inc. - All rights reserved. +* +* This software and related documentation (the 'Software') are intellectual +* property owned by Trident and are copyright of Trident, unless specifically +* noted otherwise. +* +* Any use of the Software is permitted only pursuant to the terms of the +* license agreement, if any, which accompanies, is included with or applicable +* to the Software ('License Agreement') or upon express written consent of +* Trident. Any copying, reproduction or redistribution of the Software in +* whole or in part by any means not in accordance with the License Agreement +* or as agreed in writing by Trident is expressly prohibited. +* +* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE +* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE +* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND +* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES +* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT +* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL +* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY +* TO USE THE SOFTWARE. +* +* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, +* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, +* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS +* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE +* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM +* TRIDENT'S NEGLIGENCE. $ +* +* +*******************************************************************************/ + +/*-------- compilation control switches --------------------------------------*/ + +#ifndef __DRX_DAP_FASI_H__ +#define __DRX_DAP_FASI_H__ + +/*-------- Required includes -------------------------------------------------*/ + +#include "drx_driver.h" + +/*-------- Defines, configuring the API --------------------------------------*/ + +/******************************************** +* Allowed address formats +********************************************/ + +/* +* Comments about short/long addressing format: +* +* The DAP FASI offers long address format (4 bytes) and short address format +* (2 bytes). The DAP can operate in 3 modes: +* (1) only short +* (2) only long +* (3) both long and short but short preferred and long only when necesarry +* +* These modes must be selected compile time via compile switches. +* Compile switch settings for the diffrent modes: +* (1) DRXDAPFASI_LONG_ADDR_ALLOWED=0, DRXDAPFASI_SHORT_ADDR_ALLOWED=1 +* (2) DRXDAPFASI_LONG_ADDR_ALLOWED=1, DRXDAPFASI_SHORT_ADDR_ALLOWED=0 +* (3) DRXDAPFASI_LONG_ADDR_ALLOWED=1, DRXDAPFASI_SHORT_ADDR_ALLOWED=1 +* +* The default setting will be (3) both long and short. +* The default setting will need no compile switches. +* The default setting must be overridden if compile switches are already +* defined. +* +*/ + +/* set default */ +#if !defined( DRXDAPFASI_LONG_ADDR_ALLOWED ) +#define DRXDAPFASI_LONG_ADDR_ALLOWED 1 +#endif + +/* set default */ +#if !defined( DRXDAPFASI_SHORT_ADDR_ALLOWED ) +#define DRXDAPFASI_SHORT_ADDR_ALLOWED 1 +#endif + +/* check */ +#if ( ( DRXDAPFASI_LONG_ADDR_ALLOWED==0 ) && \ + ( DRXDAPFASI_SHORT_ADDR_ALLOWED==0 ) ) +#error At least one of short- or long-addressing format must be allowed. +*; /* illegal statement to force compiler error */ +#endif + + +/******************************************** +* Single/master multi master setting +********************************************/ +/* +* Comments about SINGLE MASTER/MULTI MASTER modes: +* +* Consider the two sides:1) the master and 2)the slave. +* +* Master: +* Single/multimaster operation set via DRXDAP_SINGLE_MASTER compile switch +* + single master mode means no use of repeated starts +* + multi master mode means use of repeated starts +* Default is single master. +* Default can be overriden by setting the compile switch DRXDAP_SINGLE_MASTER. +* +* Slave: +* Single/multi master selected via the flags in the FASI protocol. +* + single master means remember memory address between i2c packets +* + multimaster means flush memory address between i2c packets +* Default is single master, DAP FASI changes multi-master setting silently +* into single master setting. This cannot be overrriden. +* +*/ +/* set default */ +#ifndef DRXDAP_SINGLE_MASTER +#define DRXDAP_SINGLE_MASTER 0 +#endif + +/******************************************** +* Chunk/mode checking +********************************************/ +/* +* Comments about DRXDAP_MAX_WCHUNKSIZE in single or multi master mode and +* in combination with short and long addressing format. All text below +* assumes long addressing format. The table also includes information +* for short ADDRessing format. +* +* In single master mode, data can be written by sending the register address +* first, then two or four bytes of data in the next packet. +* Because the device address plus a register address equals five bytes, +* the mimimum chunk size must be five. +* If ten-bit I2C device addresses are used, the minimum chunk size must be six, +* because the I2C device address will then occupy two bytes when writing. +* +* Data in single master mode is transferred as follows: +* a0 a1 a2 a3

+* d0 d1 [d2 d3]

+* .. +* or +* .. +* a0 a1 a2 a3

+* ---

+* +* In multi-master mode, the data must immediately follow the address (an I2C +* stop resets the internal address), and hence the minimum chunk size is +* 1 + 4 (register address) + 2 (data to send) = 7 bytes (8 if +* 10-bit I2C device addresses are used). +* +* The 7-bit or 10-bit i2c address parameters is a runtime parameter. +* The other parameters can be limited via compile time switches. +* +*------------------------------------------------------------------------------- +* +* Minimum chunk size table (in bytes): +* +* +----------------+----------------+ +* | 7b i2c addr | 10b i2c addr | +* +----------------+----------------+ +* | single | multi | single | multi | +* ------+--------+-------+--------+-------+ +* short | 3 | 5 | 4 | 6 | +* long | 5 | 7 | 6 | 8 | +* ------+--------+-------+--------+-------+ +* +*/ + +/* set default */ +#if !defined( DRXDAP_MAX_WCHUNKSIZE) +#define DRXDAP_MAX_WCHUNKSIZE 254 +#endif + +/* check */ +#if ( (DRXDAPFASI_LONG_ADDR_ALLOWED==0)&&(DRXDAPFASI_SHORT_ADDR_ALLOWED==1) ) +#if DRXDAP_SINGLE_MASTER +#define DRXDAP_MAX_WCHUNKSIZE_MIN 3 +#else +#define DRXDAP_MAX_WCHUNKSIZE_MIN 5 +#endif +#else +#if DRXDAP_SINGLE_MASTER +#define DRXDAP_MAX_WCHUNKSIZE_MIN 5 +#else +#define DRXDAP_MAX_WCHUNKSIZE_MIN 7 +#endif +#endif + +#if DRXDAP_MAX_WCHUNKSIZE < DRXDAP_MAX_WCHUNKSIZE_MIN +#if ( (DRXDAPFASI_LONG_ADDR_ALLOWED==0)&&(DRXDAPFASI_SHORT_ADDR_ALLOWED==1) ) +#if DRXDAP_SINGLE_MASTER +#error DRXDAP_MAX_WCHUNKSIZE must be at least 3 in single master mode +*; /* illegal statement to force compiler error */ +#else +#error DRXDAP_MAX_WCHUNKSIZE must be at least 5 in multi master mode +*; /* illegal statement to force compiler error */ +#endif +#else +#if DRXDAP_SINGLE_MASTER +#error DRXDAP_MAX_WCHUNKSIZE must be at least 5 in single master mode +*; /* illegal statement to force compiler error */ +#else +#error DRXDAP_MAX_WCHUNKSIZE must be at least 7 in multi master mode +*; /* illegal statement to force compiler error */ +#endif +#endif +#endif + +/* set default */ +#if !defined( DRXDAP_MAX_RCHUNKSIZE) +#define DRXDAP_MAX_RCHUNKSIZE 254 +#endif + +/* check */ +#if DRXDAP_MAX_RCHUNKSIZE < 2 +#error DRXDAP_MAX_RCHUNKSIZE must be at least 2 +*; /* illegal statement to force compiler error */ +#endif + +/* check */ +#if DRXDAP_MAX_RCHUNKSIZE & 1 +#error DRXDAP_MAX_RCHUNKSIZE must be even +*; /* illegal statement to force compiler error */ +#endif + +/*-------- Public API functions ----------------------------------------------*/ + +#ifdef __cplusplus +extern "C" { +#endif + + +extern DRXAccessFunc_t drxDapFASIFunct_g; + +#define DRXDAP_FASI_RMW 0x10000000 +#define DRXDAP_FASI_BROADCAST 0x20000000 +#define DRXDAP_FASI_CLEARCRC 0x80000000 +#define DRXDAP_FASI_SINGLE_MASTER 0xC0000000 +#define DRXDAP_FASI_MULTI_MASTER 0x40000000 +#define DRXDAP_FASI_SMM_SWITCH 0x40000000 /* single/multi master switch */ +#define DRXDAP_FASI_MODEFLAGS 0xC0000000 +#define DRXDAP_FASI_FLAGS 0xF0000000 + +#define DRXDAP_FASI_ADDR2BLOCK( addr ) (((addr)>>22)&0x3F) +#define DRXDAP_FASI_ADDR2BANK( addr ) (((addr)>>16)&0x3F) +#define DRXDAP_FASI_ADDR2OFFSET( addr ) ((addr)&0x7FFF) + +#define DRXDAP_FASI_SHORT_FORMAT( addr ) (((addr)& 0xFC30FF80)==0) +#define DRXDAP_FASI_LONG_FORMAT( addr ) (((addr)& 0xFC30FF80)!=0) +#define DRXDAP_FASI_OFFSET_TOO_LARGE( addr ) (((addr)& 0x00008000)!=0) + + +#ifdef __cplusplus +} +#endif + + +#endif /* __DRX_DAP_FASI_H__ */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c new file mode 100644 index 0000000..7b02841 --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c @@ -0,0 +1,1600 @@ +/** +* \file $Id: drx_driver.c,v 1.40 2010/01/12 01:24:56 lfeng Exp $ +* +* \brief Generic DRX functionality, DRX driver core. +* +* $(c) 2004-2010 Trident Microsystems, Inc. - All rights reserved. +* +* This software and related documentation (the 'Software') are intellectual +* property owned by Trident and are copyright of Trident, unless specifically +* noted otherwise. +* +* Any use of the Software is permitted only pursuant to the terms of the +* license agreement, if any, which accompanies, is included with or applicable +* to the Software ('License Agreement') or upon express written consent of +* Trident. Any copying, reproduction or redistribution of the Software in +* whole or in part by any means not in accordance with the License Agreement +* or as agreed in writing by Trident is expressly prohibited. +* +* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE +* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE +* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND +* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES +* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT +* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL +* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY +* TO USE THE SOFTWARE. +* +* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, +* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, +* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS +* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE +* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM +* TRIDENT'S NEGLIGENCE. $ +* +*/ + +/*------------------------------------------------------------------------------ +INCLUDE FILES +------------------------------------------------------------------------------*/ +#include "drx_driver.h" +#include "bsp_host.h" + +#define VERSION_FIXED 0 +#if VERSION_FIXED +#define VERSION_MAJOR 0 +#define VERSION_MINOR 0 +#define VERSION_PATCH 0 +#else +#include "drx_driver_version.h" +#endif + +/*------------------------------------------------------------------------------ +DEFINES +------------------------------------------------------------------------------*/ + +/*============================================================================*/ +/*=== MICROCODE RELATED DEFINES ==============================================*/ +/*============================================================================*/ + +/** \brief Magic word for checking correct Endianess of microcode data. */ +#ifndef DRX_UCODE_MAGIC_WORD +#define DRX_UCODE_MAGIC_WORD ((((u16_t)'H')<<8)+((u16_t)'L')) +#endif + +/** \brief CRC flag in ucode header, flags field. */ +#ifndef DRX_UCODE_CRC_FLAG +#define DRX_UCODE_CRC_FLAG (0x0001) +#endif + +/** \brief Compression flag in ucode header, flags field. */ +#ifndef DRX_UCODE_COMPRESSION_FLAG +#define DRX_UCODE_COMPRESSION_FLAG (0x0002) +#endif + +/** \brief Maximum size of buffer used to verify the microcode. + Must be an even number. */ +#ifndef DRX_UCODE_MAX_BUF_SIZE +#define DRX_UCODE_MAX_BUF_SIZE (DRXDAP_MAX_RCHUNKSIZE) +#endif +#if DRX_UCODE_MAX_BUF_SIZE & 1 +#error DRX_UCODE_MAX_BUF_SIZE must be an even number +#endif + +/*============================================================================*/ +/*=== CHANNEL SCAN RELATED DEFINES ===========================================*/ +/*============================================================================*/ + +/** +* \brief Maximum progress indication. +* +* Progress indication will run from 0 upto DRX_SCAN_MAX_PROGRESS during scan. +* +*/ +#ifndef DRX_SCAN_MAX_PROGRESS +#define DRX_SCAN_MAX_PROGRESS 1000 +#endif + +/*============================================================================*/ +/*=== MACROS =================================================================*/ +/*============================================================================*/ + +#define DRX_ISPOWERDOWNMODE( mode ) ( ( mode == DRX_POWER_MODE_9 ) || \ + ( mode == DRX_POWER_MODE_10 ) || \ + ( mode == DRX_POWER_MODE_11 ) || \ + ( mode == DRX_POWER_MODE_12 ) || \ + ( mode == DRX_POWER_MODE_13 ) || \ + ( mode == DRX_POWER_MODE_14 ) || \ + ( mode == DRX_POWER_MODE_15 ) || \ + ( mode == DRX_POWER_MODE_16 ) || \ + ( mode == DRX_POWER_DOWN ) ) + +/*------------------------------------------------------------------------------ +GLOBAL VARIABLES +------------------------------------------------------------------------------*/ + +/*------------------------------------------------------------------------------ +STRUCTURES +------------------------------------------------------------------------------*/ +/** \brief Structure of the microcode block headers */ +typedef struct { + u32_t addr; /**< Destination address of the data in this block */ + u16_t size; /**< Size of the block data following this header counted in + 16 bits words */ + u16_t flags; /**< Flags for this data block: + - bit[0]= CRC on/off + - bit[1]= compression on/off + - bit[15..2]=reserved */ + u16_t CRC; /**< CRC value of the data block, only valid if CRC flag is + set. */ +} DRXUCodeBlockHdr_t, *pDRXUCodeBlockHdr_t; + +/*------------------------------------------------------------------------------ +FUNCTIONS +------------------------------------------------------------------------------*/ + +/*============================================================================*/ +/*============================================================================*/ +/*== Channel Scan Functions ==================================================*/ +/*============================================================================*/ +/*============================================================================*/ + +#ifndef DRX_EXCLUDE_SCAN + +/* Prototype of default scanning function */ +static DRXStatus_t +ScanFunctionDefault( void *scanContext, + DRXScanCommand_t scanCommand, + pDRXChannel_t scanChannel, + pBool_t getNextChannel ); + +/** +* \brief Get pointer to scanning function. +* \param demod: Pointer to demodulator instance. +* \return DRXScanFunc_t. +*/ +static DRXScanFunc_t +GetScanFunction( pDRXDemodInstance_t demod ) +{ + pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t)(NULL); + DRXScanFunc_t scanFunc = (DRXScanFunc_t)(NULL); + + /* get scan function from common attributes */ + commonAttr = (pDRXCommonAttr_t)demod->myCommonAttr; + scanFunc = commonAttr->scanFunction; + + if ( scanFunc != NULL ) + { + /* return device-specific scan function if it's not NULL */ + return scanFunc; + } + /* otherwise return default scan function in core driver */ + return &ScanFunctionDefault; +} + +/** +* \brief Get Context pointer. +* \param demod: Pointer to demodulator instance. +* \param scanContext: Context Pointer. +* \return DRXScanFunc_t. +*/ +void *GetScanContext( pDRXDemodInstance_t demod, + void *scanContext) +{ + pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t)(NULL); + + /* get scan function from common attributes */ + commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; + scanContext = commonAttr->scanContext; + + if ( scanContext == NULL ) + { + scanContext = (void *) demod; + } + + return scanContext; +} + +/** +* \brief Wait for lock while scanning. +* \param demod: Pointer to demodulator instance. +* \param lockStat: Pointer to bool indicating if end result is lock or not. +* \return DRXStatus_t. +* \retval DRX_STS_OK: Success +* \retval DRX_STS_ERROR: I2C failure or bsp function failure. +* +* Wait until timeout, desired lock or NEVER_LOCK. +* Assume: +* - lock function returns : at least DRX_NOT_LOCKED and a lock state +* higher than DRX_NOT_LOCKED. +* - BSP has a clock function to retrieve a millisecond ticker value. +* - BSP has a sleep function to enable sleep of n millisecond. +* +* In case DRX_NEVER_LOCK is returned the poll-wait will be aborted. +* +*/ +static DRXStatus_t +ScanWaitForLock( pDRXDemodInstance_t demod, + pBool_t isLocked ) +{ + Bool_t doneWaiting = FALSE; + DRXLockStatus_t lockState = DRX_NOT_LOCKED; + DRXLockStatus_t desiredLockState = DRX_NOT_LOCKED; + u32_t timeoutValue = 0; + u32_t startTimeLockStage = 0; + u32_t currentTime = 0; + u32_t timerValue = 0; + + *isLocked = FALSE; + timeoutValue = (u32_t) demod->myCommonAttr->scanDemodLockTimeout; + desiredLockState = demod->myCommonAttr->scanDesiredLock; + startTimeLockStage = DRXBSP_HST_Clock(); + + /* Start polling loop, checking for lock & timeout */ + while ( doneWaiting == FALSE ) + { + + if ( DRX_Ctrl( demod, DRX_CTRL_LOCK_STATUS, &lockState ) != DRX_STS_OK ) + { + return DRX_STS_ERROR; + } + currentTime = DRXBSP_HST_Clock(); + + timerValue = currentTime - startTimeLockStage; + if ( lockState >= desiredLockState ) + { + *isLocked = TRUE; + doneWaiting = TRUE; + } /* if ( lockState >= desiredLockState ) .. */ + else if ( lockState == DRX_NEVER_LOCK ) + { + doneWaiting = TRUE; + } /* if ( lockState == DRX_NEVER_LOCK ) .. */ + else if ( timerValue > timeoutValue ) + { + /* lockState == DRX_NOT_LOCKED and timeout */ + doneWaiting = TRUE; + } + else + { + if ( DRXBSP_HST_Sleep( 10 ) != DRX_STS_OK ) + { + return DRX_STS_ERROR; + } + } /* if ( timerValue > timeoutValue ) .. */ + + } /* while */ + + return DRX_STS_OK; +} + +/*============================================================================*/ + +/** +* \brief Determine next frequency to scan. +* \param demod: Pointer to demodulator instance. +* \param skip : Minimum frequency step to take. +* \return DRXStatus_t. +* \retval DRX_STS_OK: Succes. +* \retval DRX_STS_INVALID_ARG: Invalid frequency plan. +* +* Helper function for CtrlScanNext() function. +* Compute next frequency & index in frequency plan. +* Check if scan is ready. +* +*/ +static DRXStatus_t +ScanPrepareNextScan ( pDRXDemodInstance_t demod, + DRXFrequency_t skip ) +{ + pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t)(NULL); + u16_t tableIndex = 0; + u16_t frequencyPlanSize = 0; + pDRXFrequencyPlan_t frequencyPlan = (pDRXFrequencyPlan_t)(NULL); + DRXFrequency_t nextFrequency = 0; + DRXFrequency_t tunerMinFrequency = 0; + DRXFrequency_t tunerMaxFrequency = 0; + + commonAttr = (pDRXCommonAttr_t)demod->myCommonAttr; + tableIndex = commonAttr->scanFreqPlanIndex; + frequencyPlan = commonAttr->scanParam->frequencyPlan; + nextFrequency = commonAttr->scanNextFrequency; + tunerMinFrequency = commonAttr->tunerMinFreqRF; + tunerMaxFrequency = commonAttr->tunerMaxFreqRF; + + do + { + /* Search next frequency to scan */ + + /* always take at least one step */ + (commonAttr->scanChannelsScanned) ++; + nextFrequency += frequencyPlan[tableIndex].step; + skip -= frequencyPlan[tableIndex].step; + + /* and then as many steps necessary to exceed 'skip' + without exceeding end of the band */ + while ( ( skip > 0 ) && + ( nextFrequency <= frequencyPlan[tableIndex].last ) ) + { + (commonAttr->scanChannelsScanned) ++; + nextFrequency += frequencyPlan[tableIndex].step; + skip -= frequencyPlan[tableIndex].step; + } + /* reset skip, in case we move to the next band later */ + skip = 0; + + if ( nextFrequency > frequencyPlan[tableIndex].last ) + { + /* reached end of this band */ + tableIndex++; + frequencyPlanSize = commonAttr->scanParam->frequencyPlanSize; + if ( tableIndex >= frequencyPlanSize ) + { + /* reached end of frequency plan */ + commonAttr->scanReady = TRUE; + } + else + { + nextFrequency = frequencyPlan[tableIndex].first; + } + } + if ( nextFrequency > (tunerMaxFrequency) ) + { + /* reached end of tuner range */ + commonAttr->scanReady = TRUE; + } + } while( ( nextFrequency < tunerMinFrequency ) && + ( commonAttr->scanReady == FALSE ) ); + + /* Store new values */ + commonAttr->scanFreqPlanIndex = tableIndex; + commonAttr->scanNextFrequency = nextFrequency; + + return DRX_STS_OK; +} + +/*============================================================================*/ + +/** +* \brief Default DTV scanning function. +* +* \param demod: Pointer to demodulator instance. +* \param scanCommand: Scanning command: INIT, NEXT or STOP. +* \param scanChannel: Channel to check: frequency and bandwidth, others AUTO +* \param getNextChannel: Return TRUE if next frequency is desired at next call +* +* \return DRXStatus_t. +* \retval DRX_STS_OK: Channel found, DRX_CTRL_GET_CHANNEL can be used +* to retrieve channel parameters. +* \retval DRX_STS_BUSY: Channel not found (yet). +* \retval DRX_STS_ERROR: Something went wrong. +* +* scanChannel and getNextChannel will be NULL for INIT and STOP. +*/ +static DRXStatus_t +ScanFunctionDefault ( void *scanContext, + DRXScanCommand_t scanCommand, + pDRXChannel_t scanChannel, + pBool_t getNextChannel ) +{ + pDRXDemodInstance_t demod = NULL; + DRXStatus_t status = DRX_STS_ERROR; + Bool_t isLocked = FALSE; + + demod = (pDRXDemodInstance_t) scanContext; + + if ( scanCommand != DRX_SCAN_COMMAND_NEXT ) + { + /* just return OK if not doing "scan next" */ + return DRX_STS_OK; + } + + *getNextChannel = FALSE; + + status = DRX_Ctrl ( demod, DRX_CTRL_SET_CHANNEL, scanChannel ); + if ( status != DRX_STS_OK ) + { + return (status); + } + + status = ScanWaitForLock ( demod, &isLocked ); + if ( status != DRX_STS_OK ) + { + return status; + } + + /* done with this channel, move to next one */ + *getNextChannel = TRUE; + + if ( isLocked == FALSE ) + { + /* no channel found */ + return DRX_STS_BUSY; + } + /* channel found */ + return DRX_STS_OK; +} + +/*============================================================================*/ + +/** +* \brief Initialize for channel scan. +* \param demod: Pointer to demodulator instance. +* \param scanParam: Pointer to scan parameters. +* \return DRXStatus_t. +* \retval DRX_STS_OK: Initialized for scan. +* \retval DRX_STS_ERROR: No overlap between frequency plan and tuner +* range. +* \retval DRX_STS_INVALID_ARG: Wrong parameters. +* +* This function should be called before starting a complete channel scan. +* It will prepare everything for a complete channel scan. +* After calling this function the DRX_CTRL_SCAN_NEXT control function can be +* used to perform the actual scanning. Scanning will start at the first +* center frequency of the frequency plan that is within the tuner range. +* +*/ +static DRXStatus_t +CtrlScanInit( pDRXDemodInstance_t demod, + pDRXScanParam_t scanParam ) +{ + DRXStatus_t status = DRX_STS_ERROR; + pDRXCommonAttr_t commonAttr =(pDRXCommonAttr_t)(NULL); + DRXFrequency_t maxTunerFreq = 0; + DRXFrequency_t minTunerFreq = 0; + u16_t nrChannelsInPlan = 0; + u16_t i = 0; + void *scanContext = NULL; + + commonAttr = (pDRXCommonAttr_t)demod->myCommonAttr; + commonAttr->scanActive = TRUE; + + /* invalidate a previous SCAN_INIT */ + commonAttr->scanParam = (pDRXScanParam_t)(NULL); + commonAttr->scanNextFrequency = 0; + + /* Check parameters */ + if ( ( ( demod->myTuner == NULL ) && + ( scanParam->numTries !=1) ) || + + ( scanParam == NULL) || + ( scanParam->numTries == 0) || + ( scanParam->frequencyPlan == NULL) || + ( scanParam->frequencyPlanSize == 0 ) + ) + { + commonAttr->scanActive = FALSE; + return DRX_STS_INVALID_ARG; + } + + /* Check frequency plan contents */ + maxTunerFreq = commonAttr->tunerMaxFreqRF; + minTunerFreq = commonAttr->tunerMinFreqRF; + for( i = 0; i < (scanParam->frequencyPlanSize); i++ ) + { + DRXFrequency_t width = 0; + DRXFrequency_t step = scanParam->frequencyPlan[i].step; + DRXFrequency_t firstFreq = scanParam->frequencyPlan[i].first; + DRXFrequency_t lastFreq = scanParam->frequencyPlan[i].last; + DRXFrequency_t minFreq = 0; + DRXFrequency_t maxFreq = 0; + + if ( step <= 0 ) + { + /* Step must be positive and non-zero */ + commonAttr->scanActive = FALSE; + return DRX_STS_INVALID_ARG; + } + + if ( firstFreq > lastFreq ) + { + /* First center frequency is higher than last center frequency */ + commonAttr->scanActive = FALSE; + return DRX_STS_INVALID_ARG; + } + + width = lastFreq - firstFreq; + + if ( ( width % step ) != 0 ) + { + /* Difference between last and first center frequency is not + an integer number of steps */ + commonAttr->scanActive = FALSE; + return DRX_STS_INVALID_ARG; + } + + /* Check if frequency plan entry intersects with tuner range */ + if ( lastFreq >= minTunerFreq ) + { + if ( firstFreq <= maxTunerFreq ) + { + if ( firstFreq >= minTunerFreq ) + { + minFreq = firstFreq; + } + else + { + DRXFrequency_t n = 0; + + n = ( minTunerFreq - firstFreq ) / step; + if ( ( ( minTunerFreq - firstFreq ) % step ) != 0 ) + { + n++; + } + minFreq = firstFreq + n*step; + } + + if ( lastFreq <= maxTunerFreq ) + { + maxFreq = lastFreq; + } + else + { + DRXFrequency_t n=0; + + n=( lastFreq - maxTunerFreq )/step; + if ( (( lastFreq - maxTunerFreq )%step) !=0 ) + { + n++; + } + maxFreq = lastFreq - n*step; + } + } + } + + /* Keep track of total number of channels within tuner range + in this frequency plan. */ + if ( (minFreq !=0 ) && ( maxFreq != 0 ) ) + { + nrChannelsInPlan += (u16_t)( ( ( maxFreq-minFreq ) / step ) +1 ); + + /* Determine first frequency (within tuner range) to scan */ + if ( commonAttr->scanNextFrequency == 0 ) + { + commonAttr->scanNextFrequency = minFreq; + commonAttr->scanFreqPlanIndex = i; + } + } + + }/* for ( ... ) */ + + if ( nrChannelsInPlan == 0 ) + { + /* Tuner range and frequency plan ranges do not overlap */ + commonAttr->scanActive = FALSE; + return DRX_STS_ERROR; + } + + /* Store parameters */ + commonAttr->scanReady = FALSE; + commonAttr->scanMaxChannels = nrChannelsInPlan; + commonAttr->scanChannelsScanned = 0; + commonAttr->scanParam = scanParam; /* SCAN_NEXT is now allowed */ + + scanContext = GetScanContext(demod, scanContext); + + status = (*(GetScanFunction( demod ))) + ( scanContext, DRX_SCAN_COMMAND_INIT, NULL, NULL ); + + commonAttr->scanActive = FALSE; + + return DRX_STS_OK; +} + +/*============================================================================*/ + +/** +* \brief Stop scanning. +* \param demod: Pointer to demodulator instance. +* \return DRXStatus_t. +* \retval DRX_STS_OK: Scan stopped. +* \retval DRX_STS_ERROR: Something went wrong. +* \retval DRX_STS_INVALID_ARG: Wrong parameters. +*/ +static DRXStatus_t +CtrlScanStop( pDRXDemodInstance_t demod ) +{ + DRXStatus_t status = DRX_STS_ERROR; + pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); + void *scanContext = NULL; + + commonAttr = (pDRXCommonAttr_t)demod->myCommonAttr; + commonAttr->scanActive = TRUE; + + if ( ( commonAttr->scanParam == NULL ) || + ( commonAttr->scanMaxChannels == 0 ) ) + { + /* Scan was not running, just return OK */ + commonAttr->scanActive = FALSE; + return DRX_STS_OK; + } + + /* Call default or device-specific scanning stop function */ + scanContext = GetScanContext(demod, scanContext); + + status = (*(GetScanFunction( demod ))) + ( scanContext, DRX_SCAN_COMMAND_STOP, NULL, NULL ); + + /* All done, invalidate scan-init */ + commonAttr->scanParam = NULL; + commonAttr->scanMaxChannels = 0; + commonAttr->scanActive = FALSE; + + return status; +} + +/*============================================================================*/ + +/** +* \brief Scan for next channel. +* \param demod: Pointer to demodulator instance. +* \param scanProgress: Pointer to scan progress. +* \return DRXStatus_t. +* \retval DRX_STS_OK: Channel found, DRX_CTRL_GET_CHANNEL can be used +* to retrieve channel parameters. +* \retval DRX_STS_BUSY: Tried part of the channels, as specified in +* numTries field of scan parameters. At least one +* more call to DRX_CTRL_SCAN_NEXT is needed to +* complete scanning. +* \retval DRX_STS_READY: Reached end of scan range. +* \retval DRX_STS_ERROR: Something went wrong. +* \retval DRX_STS_INVALID_ARG: Wrong parameters. The scanProgress may be NULL. +* +* Progress indication will run from 0 upto DRX_SCAN_MAX_PROGRESS during scan. +* +*/ +static DRXStatus_t +CtrlScanNext ( pDRXDemodInstance_t demod, + pu16_t scanProgress ) +{ + pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t)(NULL); + pBool_t scanReady = (pBool_t)(NULL); + u16_t maxProgress = DRX_SCAN_MAX_PROGRESS; + u32_t numTries = 0; + u32_t i = 0; + + commonAttr = (pDRXCommonAttr_t)demod->myCommonAttr; + + /* Check scan parameters */ + if ( scanProgress == NULL ) + { + commonAttr->scanActive = FALSE; + return DRX_STS_INVALID_ARG; + } + + *scanProgress = 0; + commonAttr->scanActive = TRUE; + if ( ( commonAttr->scanParam == NULL) || + ( commonAttr->scanMaxChannels == 0 ) ) + { + /* CtrlScanInit() was not called succesfully before CtrlScanNext() */ + commonAttr->scanActive = FALSE; + return DRX_STS_ERROR; + } + + *scanProgress = (u16_t)( ( ( commonAttr->scanChannelsScanned)* + ( (u32_t)(maxProgress) ) ) / + ( commonAttr->scanMaxChannels ) ); + + /* Scan */ + numTries = commonAttr->scanParam->numTries; + scanReady = &(commonAttr->scanReady); + + for ( i = 0; ( (i < numTries) && ( (*scanReady) == FALSE) ); i++) + { + DRXChannel_t scanChannel = { 0 }; + DRXStatus_t status = DRX_STS_ERROR; + pDRXFrequencyPlan_t freqPlan = (pDRXFrequencyPlan_t) (NULL); + Bool_t nextChannel = FALSE; + void *scanContext = NULL; + + /* Next channel to scan */ + freqPlan = + &(commonAttr->scanParam->frequencyPlan[commonAttr->scanFreqPlanIndex]); + scanChannel.frequency = commonAttr->scanNextFrequency; + scanChannel.bandwidth = freqPlan->bandwidth; + scanChannel.mirror = DRX_MIRROR_AUTO; + scanChannel.constellation = DRX_CONSTELLATION_AUTO; + scanChannel.hierarchy = DRX_HIERARCHY_AUTO; + scanChannel.priority = DRX_PRIORITY_HIGH; + scanChannel.coderate = DRX_CODERATE_AUTO; + scanChannel.guard = DRX_GUARD_AUTO; + scanChannel.fftmode = DRX_FFTMODE_AUTO; + scanChannel.classification = DRX_CLASSIFICATION_AUTO; + scanChannel.symbolrate = 0; + scanChannel.interleavemode = DRX_INTERLEAVEMODE_AUTO; + scanChannel.ldpc = DRX_LDPC_AUTO; + scanChannel.carrier = DRX_CARRIER_AUTO; + scanChannel.framemode = DRX_FRAMEMODE_AUTO; + scanChannel.pilot = DRX_PILOT_AUTO; + + /* Call default or device-specific scanning function */ + scanContext = GetScanContext(demod, scanContext); + + status = (*(GetScanFunction( demod ))) + ( scanContext,DRX_SCAN_COMMAND_NEXT,&scanChannel,&nextChannel ); + + /* Proceed to next channel if requested */ + if ( nextChannel == TRUE ) + { + DRXStatus_t nextStatus = DRX_STS_ERROR; + DRXFrequency_t skip = 0; + + if ( status == DRX_STS_OK ) + { + /* a channel was found, so skip some frequency steps */ + skip = commonAttr->scanParam->skip; + } + nextStatus = ScanPrepareNextScan( demod, skip ); + + /* keep track of progress */ + *scanProgress = (u16_t)(((commonAttr->scanChannelsScanned)* + ((u32_t)(maxProgress)))/ + (commonAttr->scanMaxChannels)); + + if ( nextStatus != DRX_STS_OK ) + { + commonAttr->scanActive = FALSE; + return (nextStatus); + } + } + if ( status != DRX_STS_BUSY ) + { + /* channel found or error */ + commonAttr->scanActive = FALSE; + return status; + } + } /* for ( i = 0; i < ( ... numTries); i++) */ + + if ( (*scanReady) == TRUE ) + { + /* End of scan reached: call stop-scan, ignore any error */ + CtrlScanStop( demod ); + commonAttr->scanActive = FALSE; + return (DRX_STS_READY); + } + + commonAttr->scanActive = FALSE; + + return DRX_STS_BUSY; +} + +#endif /* #ifndef DRX_EXCLUDE_SCAN */ + +/*============================================================================*/ + +/** +* \brief Program tuner. +* \param demod: Pointer to demodulator instance. +* \param tunerChannel: Pointer to tuning parameters. +* \return DRXStatus_t. +* \retval DRX_STS_OK: Tuner programmed successfully. +* \retval DRX_STS_ERROR: Something went wrong. +* \retval DRX_STS_INVALID_ARG: Wrong parameters. +* +* tunerChannel passes parameters to program the tuner, +* but also returns the actual RF and IF frequency from the tuner. +* +*/ +static DRXStatus_t +CtrlProgramTuner( pDRXDemodInstance_t demod, + pDRXChannel_t channel ) +{ + pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t)(NULL); + DRXStandard_t standard = DRX_STANDARD_UNKNOWN; + TUNERMode_t tunerMode = 0; + DRXStatus_t status = DRX_STS_ERROR; + DRXFrequency_t ifFrequency = 0; + Bool_t tunerSlowMode = FALSE; + + /* can't tune without a tuner */ + if ( demod->myTuner == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; + + /* select analog or digital tuner mode based on current standard */ + if ( DRX_Ctrl( demod, DRX_CTRL_GET_STANDARD, &standard ) != DRX_STS_OK ) + { + return DRX_STS_ERROR; + } + + if ( DRX_ISATVSTD( standard ) ) + { + tunerMode |= TUNER_MODE_ANALOG; + } + else /* note: also for unknown standard */ + { + tunerMode |= TUNER_MODE_DIGITAL; + } + + /* select tuner bandwidth */ + switch ( channel->bandwidth ) + { + case DRX_BANDWIDTH_6MHZ: + tunerMode |= TUNER_MODE_6MHZ; + break; + case DRX_BANDWIDTH_7MHZ: + tunerMode |= TUNER_MODE_7MHZ; + break; + case DRX_BANDWIDTH_8MHZ: + tunerMode |= TUNER_MODE_8MHZ; + break; + default: /* note: also for unknown bandwidth */ + return DRX_STS_INVALID_ARG; + } + + DRX_GET_TUNERSLOWMODE (demod, tunerSlowMode); + + /* select fast (switch) or slow (lock) tuner mode */ + if ( tunerSlowMode ) + { + tunerMode |= TUNER_MODE_LOCK; + } + else + { + tunerMode |= TUNER_MODE_SWITCH; + } + + if ( commonAttr->tunerPortNr == 1 ) + { + Bool_t bridgeClosed = TRUE; + DRXStatus_t statusBridge = DRX_STS_ERROR; + + statusBridge = DRX_Ctrl( demod, DRX_CTRL_I2C_BRIDGE, &bridgeClosed ); + if ( statusBridge != DRX_STS_OK ) + { + return statusBridge; + } + } + + status = DRXBSP_TUNER_SetFrequency( demod->myTuner, + tunerMode, + channel->frequency ); + + /* attempt restoring bridge before checking status of SetFrequency */ + if ( commonAttr->tunerPortNr == 1 ) + { + Bool_t bridgeClosed = FALSE; + DRXStatus_t statusBridge = DRX_STS_ERROR; + + statusBridge = DRX_Ctrl( demod, DRX_CTRL_I2C_BRIDGE, &bridgeClosed ); + if ( statusBridge != DRX_STS_OK ) + { + return statusBridge; + } + } + + /* now check status of DRXBSP_TUNER_SetFrequency */ + if ( status != DRX_STS_OK ) + { + return status; + } + + /* get actual RF and IF frequencies from tuner */ + status = DRXBSP_TUNER_GetFrequency( demod->myTuner, + tunerMode, + &(channel->frequency), + &(ifFrequency) ); + if ( status != DRX_STS_OK ) + { + return status; + } + + /* update common attributes with information available from this function; + TODO: check if this is required and safe */ + DRX_SET_INTERMEDIATEFREQ( demod, ifFrequency ); + + return DRX_STS_OK; +} + +/*============================================================================*/ + +/** +* \brief function to do a register dump. +* \param demod: Pointer to demodulator instance. +* \param registers: Registers to dump. +* \return DRXStatus_t. +* \retval DRX_STS_OK: Dump executed successfully. +* \retval DRX_STS_ERROR: Something went wrong. +* \retval DRX_STS_INVALID_ARG: Wrong parameters. +* +*/ +DRXStatus_t CtrlDumpRegisters( pDRXDemodInstance_t demod, + pDRXRegDump_t registers ) +{ + u16_t i = 0; + + if ( registers == NULL ) + { + /* registers not supplied */ + return DRX_STS_INVALID_ARG; + } + + /* start dumping registers */ + while ( registers[i].address != 0 ) + { + DRXStatus_t status = DRX_STS_ERROR; + u16_t value = 0; + u32_t data = 0; + + status = demod->myAccessFunct->readReg16Func( + demod->myI2CDevAddr, registers[i].address, &value, 0 ); + + data = (u32_t)value; + + if ( status != DRX_STS_OK ) + { + /* no breakouts; + depending on device ID, some HW blocks might not be available */ + data |= ( (u32_t)status ) << 16; + } + registers[i].data = data; + i++; + } + + /* all done, all OK (any errors are saved inside data) */ + return DRX_STS_OK; +} + +/*============================================================================*/ +/*============================================================================*/ +/*===Microcode related functions==============================================*/ +/*============================================================================*/ +/*============================================================================*/ + +/** +* \brief Read a 16 bits word, expects big endian data. +* \param addr: Pointer to memory from which to read the 16 bits word. +* \return u16_t The data read. +* +* This function takes care of the possible difference in endianness between the +* host and the data contained in the microcode image file. +* +*/ +static u16_t +UCodeRead16( pu8_t addr) +{ + /* Works fo any host processor */ + + u16_t word=0; + + word = ((u16_t)addr[0]); + word <<= 8; + word |=((u16_t)addr[1]); + + return word; +} + +/*============================================================================*/ + +/** +* \brief Read a 32 bits word, expects big endian data. +* \param addr: Pointer to memory from which to read the 32 bits word. +* \return u32_t The data read. +* +* This function takes care of the possible difference in endianness between the +* host and the data contained in the microcode image file. +* +*/ +static u32_t +UCodeRead32( pu8_t addr) +{ + /* Works fo any host processor */ + + u32_t word=0; + + word = ((u16_t)addr[0]); + word <<= 8; + word |= ((u16_t)addr[1]); + word <<= 8; + word |= ((u16_t)addr[2]); + word <<= 8; + word |= ((u16_t)addr[3]); + + return word ; +} + +/*============================================================================*/ + +/** +* \brief Compute CRC of block of microcode data. +* \param blockData: Pointer to microcode data. +* \param nrWords: Size of microcode block (number of 16 bits words). +* \return u16_t The computed CRC residu. +*/ +static u16_t +UCodeComputeCRC (pu8_t blockData, u16_t nrWords) +{ + u16_t i = 0; + u16_t j = 0; + u32_t CRCWord = 0; + u32_t carry = 0; + + while ( i < nrWords ) + { + CRCWord |= (u32_t) UCodeRead16(blockData); + for (j = 0; j < 16; j++) + { + CRCWord <<= 1; + if (carry != 0) + { + CRCWord ^= 0x80050000UL; + } + carry = CRCWord & 0x80000000UL; + } + i++; + blockData+=(sizeof(u16_t)); + } + return ((u16_t) (CRCWord >> 16)); +} + +/*============================================================================*/ + +/** +* \brief Handle microcode upload or verify. +* \param devAddr: Address of device. +* \param mcInfo: Pointer to information about microcode data. +* \param action: Either UCODE_UPLOAD or UCODE_VERIFY +* \return DRXStatus_t. +* \retval DRX_STS_OK: +* - In case of UCODE_UPLOAD: code is successfully uploaded. +* - In case of UCODE_VERIFY: image on device is equal to +* image provided to this control function. +* \retval DRX_STS_ERROR: +* - In case of UCODE_UPLOAD: I2C error. +* - In case of UCODE_VERIFY: I2C error or image on device +* is not equal to image provided to this control function. +* \retval DRX_STS_INVALID_ARG: +* - Invalid arguments. +* - Provided image is corrupt +*/ +static DRXStatus_t +CtrlUCode( pDRXDemodInstance_t demod, + pDRXUCodeInfo_t mcInfo, + DRXUCodeAction_t action) +{ + DRXStatus_t rc; + u16_t i = 0; + u16_t mcNrOfBlks = 0; + u16_t mcMagicWord = 0; + pu8_t mcData = (pu8_t)(NULL); + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)(NULL); + + devAddr = demod -> myI2CDevAddr; + + /* Check arguments */ + if ( ( mcInfo == NULL ) || + ( mcInfo->mcData == NULL ) ) + { + return DRX_STS_INVALID_ARG; + } + + mcData = mcInfo->mcData; + + /* Check data */ + mcMagicWord = UCodeRead16( mcData ); + mcData += sizeof( u16_t ); + mcNrOfBlks = UCodeRead16( mcData ); + mcData += sizeof( u16_t ); + + if ( ( mcMagicWord != DRX_UCODE_MAGIC_WORD ) || + ( mcNrOfBlks == 0 ) ) + { + /* wrong endianess or wrong data ? */ + return DRX_STS_INVALID_ARG; + } + + /* Scan microcode blocks first for version info if uploading */ + if (action == UCODE_UPLOAD) + { + /* Clear version block */ + DRX_SET_MCVERTYPE (demod, 0); + DRX_SET_MCDEV (demod, 0); + DRX_SET_MCVERSION (demod, 0); + DRX_SET_MCPATCH (demod, 0); + for (i = 0; i < mcNrOfBlks; i++) + { + DRXUCodeBlockHdr_t blockHdr; + + /* Process block header */ + blockHdr.addr = UCodeRead32( mcData ); + mcData += sizeof(u32_t); + blockHdr.size = UCodeRead16( mcData ); + mcData += sizeof(u16_t); + blockHdr.flags = UCodeRead16( mcData ); + mcData += sizeof(u16_t); + blockHdr.CRC = UCodeRead16( mcData ); + mcData += sizeof(u16_t); + + if (blockHdr.flags & 0x8) + { + /* Aux block. Check type */ + pu8_t auxblk = mcInfo->mcData + blockHdr.addr; + u16_t auxtype = UCodeRead16 (auxblk); + if (DRX_ISMCVERTYPE (auxtype)) + { + DRX_SET_MCVERTYPE (demod, UCodeRead16 (auxblk)); + auxblk += sizeof (u16_t); + DRX_SET_MCDEV (demod, UCodeRead32 (auxblk)); + auxblk += sizeof (u32_t); + DRX_SET_MCVERSION (demod, UCodeRead32 (auxblk)); + auxblk += sizeof (u32_t); + DRX_SET_MCPATCH (demod, UCodeRead32 (auxblk)); + } + } + + /* Next block */ + mcData += blockHdr.size * sizeof (u16_t); + } + + /* After scanning, validate the microcode. + It is also valid if no validation control exists. + */ + rc = DRX_Ctrl (demod, DRX_CTRL_VALIDATE_UCODE, NULL); + if (rc != DRX_STS_OK && rc != DRX_STS_FUNC_NOT_AVAILABLE) + { + return rc; + } + + /* Restore data pointer */ + mcData = mcInfo->mcData + 2 * sizeof( u16_t ); + } + + /* Process microcode blocks */ + for( i = 0 ; i 0x7FFF ) || + ( ( ( blockHdr.flags & DRX_UCODE_CRC_FLAG ) != 0 ) && + ( blockHdr.CRC != UCodeComputeCRC ( mcData, blockHdr.size) ) ) + ) + { + /* Wrong data ! */ + return DRX_STS_INVALID_ARG; + } + + mcBlockNrBytes = blockHdr.size * ((u16_t)sizeof( u16_t )); + + if ( blockHdr.size != 0 ) + { + /* Perform the desired action */ + switch ( action ) { + /*================================================================*/ + case UCODE_UPLOAD : + { + /* Upload microcode */ + if ( demod->myAccessFunct->writeBlockFunc( + devAddr, + (DRXaddr_t) blockHdr.addr, + mcBlockNrBytes, + mcData, + 0x0000) != DRX_STS_OK) + { + return (DRX_STS_ERROR); + } /* if */ + }; + break; + + /*================================================================*/ + case UCODE_VERIFY : + { + int result = 0; + u8_t mcDataBuffer[DRX_UCODE_MAX_BUF_SIZE]; + u32_t bytesToCompare=0; + u32_t bytesLeftToCompare=0; + DRXaddr_t currAddr = (DRXaddr_t)0; + pu8_t currPtr =NULL; + + bytesLeftToCompare = mcBlockNrBytes; + currAddr = blockHdr.addr; + currPtr = mcData; + + while( bytesLeftToCompare != 0 ) + { + if (bytesLeftToCompare > ( (u32_t)DRX_UCODE_MAX_BUF_SIZE) ) + { + bytesToCompare = ( (u32_t)DRX_UCODE_MAX_BUF_SIZE ); + } + else + { + bytesToCompare = bytesLeftToCompare; + } + + if ( demod->myAccessFunct->readBlockFunc( + devAddr, + currAddr, + (u16_t)bytesToCompare, + (pu8_t)mcDataBuffer, + 0x0000) != DRX_STS_OK) + { + return (DRX_STS_ERROR); + } + + result = DRXBSP_HST_Memcmp( currPtr, + mcDataBuffer, + bytesToCompare); + + if ( result != 0 ) + { + return DRX_STS_ERROR; + } + + currAddr += ((DRXaddr_t)(bytesToCompare/2)); + currPtr = &(currPtr[bytesToCompare]); + bytesLeftToCompare -= ((u32_t)bytesToCompare); + } /* while( bytesToCompare > DRX_UCODE_MAX_BUF_SIZE ) */ + }; + break; + + /*================================================================*/ + default: + return DRX_STS_INVALID_ARG; + break; + + } /* switch ( action ) */ + } /* if (blockHdr.size != 0 ) */ + + /* Next block */ + mcData += mcBlockNrBytes; + + } /* for( i = 0 ; imyDemodFunct->ctrlFunc))( + demod, + DRX_CTRL_VERSION, + (void *) &demodVersionList ); + + /* Always fill in the information of the driver SW . */ + drxDriverCoreVersion.moduleType = DRX_MODULE_DRIVERCORE; + drxDriverCoreVersion.moduleName = drxDriverCoreModuleName; + drxDriverCoreVersion.vMajor = VERSION_MAJOR; + drxDriverCoreVersion.vMinor = VERSION_MINOR; + drxDriverCoreVersion.vPatch = VERSION_PATCH; + drxDriverCoreVersion.vString = drxDriverCoreVersionText; + + drxDriverCoreVersionList.version = &drxDriverCoreVersion; + drxDriverCoreVersionList.next = (pDRXVersionList_t)(NULL); + + if ( ( returnStatus == DRX_STS_OK ) && ( demodVersionList != NULL ) ) + { + /* Append versioninfo from driver to versioninfo from demod */ + /* Return version info in "bottom-up" order. This way, multiple + devices can be handled without using malloc. */ + pDRXVersionList_t currentListElement = demodVersionList; + while ( currentListElement->next != NULL ) + { + currentListElement = currentListElement->next; + } + currentListElement->next = &drxDriverCoreVersionList; + + *versionList = demodVersionList; + } + else + { + /* Just return versioninfo from driver */ + *versionList = &drxDriverCoreVersionList; + } + + return DRX_STS_OK; +} + +/*============================================================================*/ +/*============================================================================*/ +/*== Exported functions ======================================================*/ +/*============================================================================*/ +/*============================================================================*/ + + + +/** +* \brief This function is obsolete. +* \param demods: Don't care, parameter is ignored. +* \return DRXStatus_t Return status. +* \retval DRX_STS_OK: Initialization completed. +* +* This function is obsolete, prototype available for backward compatability. +* +*/ + +DRXStatus_t +DRX_Init( pDRXDemodInstance_t demods[] ) +{ + return DRX_STS_OK; +} + +/*============================================================================*/ + +/** +* \brief This function is obsolete. +* \return DRXStatus_t Return status. +* \retval DRX_STS_OK: Terminated driver successful. +* +* This function is obsolete, prototype available for backward compatability. +* +*/ + +DRXStatus_t +DRX_Term( void ) +{ + return DRX_STS_OK; +} + +/*============================================================================*/ + +/** +* \brief Open a demodulator instance. +* \param demod: A pointer to a demodulator instance. +* \return DRXStatus_t Return status. +* \retval DRX_STS_OK: Opened demod instance with succes. +* \retval DRX_STS_ERROR: Driver not initialized or unable to initialize +* demod. +* \retval DRX_STS_INVALID_ARG: Demod instance has invalid content. +* +*/ + +DRXStatus_t +DRX_Open(pDRXDemodInstance_t demod) +{ + DRXStatus_t status = DRX_STS_OK; + + if ( ( demod == NULL ) || + ( demod->myDemodFunct == NULL ) || + ( demod->myCommonAttr == NULL ) || + ( demod->myExtAttr == NULL ) || + ( demod->myI2CDevAddr == NULL ) || + ( demod->myCommonAttr->isOpened == TRUE )) + { + return (DRX_STS_INVALID_ARG); + } + + status = (*(demod->myDemodFunct->openFunc))( demod ); + + if ( status == DRX_STS_OK ) + { + demod->myCommonAttr->isOpened = TRUE; + } + + return status; +} + +/*============================================================================*/ + +/** +* \brief Close device. +* \param demod: A pointer to a demodulator instance. +* \return DRXStatus_t Return status. +* \retval DRX_STS_OK: Closed demod instance with succes. +* \retval DRX_STS_ERROR: Driver not initialized or error during close +* demod. +* \retval DRX_STS_INVALID_ARG: Demod instance has invalid content. +* +* Free resources occupied by device instance. +* Put device into sleep mode. +*/ + +DRXStatus_t +DRX_Close(pDRXDemodInstance_t demod) +{ + DRXStatus_t status = DRX_STS_OK; + + if ( ( demod == NULL ) || + ( demod->myDemodFunct == NULL ) || + ( demod->myCommonAttr == NULL ) || + ( demod->myExtAttr == NULL ) || + ( demod->myI2CDevAddr == NULL ) || + ( demod->myCommonAttr->isOpened == FALSE )) + { + return DRX_STS_INVALID_ARG; + } + + status = (*(demod->myDemodFunct->closeFunc))( demod ); + + DRX_SET_ISOPENED (demod, FALSE); + + return status; +} + +/*============================================================================*/ + +/** +* \brief Control the device. +* \param demod: A pointer to a demodulator instance. +* \param ctrl: Reference to desired control function. +* \param ctrlData: Pointer to data structure for control function. +* \return DRXStatus_t Return status. +* \retval DRX_STS_OK: Control function completed successfully. +* \retval DRX_STS_ERROR: Driver not initialized or error during +* control demod. +* \retval DRX_STS_INVALID_ARG: Demod instance or ctrlData has invalid +* content. +* \retval DRX_STS_FUNC_NOT_AVAILABLE: Specified control function is not +* available. +* +* Data needed or returned by the control function is stored in ctrlData. +* +*/ + +DRXStatus_t +DRX_Ctrl(pDRXDemodInstance_t demod, DRXCtrlIndex_t ctrl, void *ctrlData) +{ + DRXStatus_t status = DRX_STS_ERROR; + + if ( ( demod == NULL ) || + ( demod->myDemodFunct == NULL ) || + ( demod->myCommonAttr == NULL ) || + ( demod->myExtAttr == NULL ) || + ( demod->myI2CDevAddr == NULL ) + ) + { + return (DRX_STS_INVALID_ARG); + } + + if ( ( ( demod->myCommonAttr->isOpened == FALSE ) && + ( ctrl != DRX_CTRL_PROBE_DEVICE ) && + ( ctrl != DRX_CTRL_VERSION) ) + ) + { + return (DRX_STS_INVALID_ARG); + } + + if ( ( DRX_ISPOWERDOWNMODE( demod->myCommonAttr->currentPowerMode ) && + ( ctrl != DRX_CTRL_POWER_MODE ) && + ( ctrl != DRX_CTRL_PROBE_DEVICE ) && + ( ctrl != DRX_CTRL_NOP ) && + ( ctrl != DRX_CTRL_VERSION) + ) + ) + { + return DRX_STS_FUNC_NOT_AVAILABLE; + } + + /* Fixed control functions */ + switch ( ctrl ) { + /*======================================================================*/ + case DRX_CTRL_NOP: + /* No operation */ + return DRX_STS_OK; + break; + + /*======================================================================*/ + case DRX_CTRL_VERSION: + return CtrlVersion( demod, (pDRXVersionList_t *) ctrlData ); + break; + + /*======================================================================*/ + default : + /* Do nothing */ + break; + } + + /* Virtual functions */ + /* First try calling function from derived class */ + status = (*(demod->myDemodFunct->ctrlFunc))( demod, ctrl, ctrlData ); + if (status == DRX_STS_FUNC_NOT_AVAILABLE) + { + /* Now try calling a the base class function */ + switch ( ctrl ) { + /*===================================================================*/ + case DRX_CTRL_LOAD_UCODE: + return CtrlUCode ( demod, + (pDRXUCodeInfo_t) ctrlData, + UCODE_UPLOAD ); + break; + + /*===================================================================*/ + case DRX_CTRL_VERIFY_UCODE: + { + return CtrlUCode ( demod, + (pDRXUCodeInfo_t) ctrlData, + UCODE_VERIFY); + } + break; + +#ifndef DRX_EXCLUDE_SCAN + /*===================================================================*/ + case DRX_CTRL_SCAN_INIT: + { + return CtrlScanInit( demod, (pDRXScanParam_t) ctrlData ); + } + break; + + /*===================================================================*/ + case DRX_CTRL_SCAN_NEXT: + { + return CtrlScanNext( demod, (pu16_t) ctrlData ); + } + break; + + /*===================================================================*/ + case DRX_CTRL_SCAN_STOP: + { + return CtrlScanStop( demod ); + } + break; +#endif /* #ifndef DRX_EXCLUDE_SCAN */ + + /*===================================================================*/ + case DRX_CTRL_PROGRAM_TUNER: + { + return CtrlProgramTuner( demod, (pDRXChannel_t) ctrlData ); + } + break; + + /*===================================================================*/ + case DRX_CTRL_DUMP_REGISTERS: + { + return CtrlDumpRegisters( demod, (pDRXRegDump_t) ctrlData ); + } + break; + + /*===================================================================*/ + default : + return DRX_STS_FUNC_NOT_AVAILABLE; + } + } + else + { + return (status); + } + + return DRX_STS_OK; +} + + +/*============================================================================*/ + +/* END OF FILE */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h new file mode 100644 index 0000000..d3bfe06 --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h @@ -0,0 +1,2588 @@ +/** +* \file $Id: drx_driver.h,v 1.84 2010/01/14 22:47:50 dingtao Exp $ +* +* \brief DRX driver API +* +* $(c) 2004-2010 Trident Microsystems, Inc. - All rights reserved. +* +* This software and related documentation (the 'Software') are intellectual +* property owned by Trident and are copyright of Trident, unless specifically +* noted otherwise. +* +* Any use of the Software is permitted only pursuant to the terms of the +* license agreement, if any, which accompanies, is included with or applicable +* to the Software ('License Agreement') or upon express written consent of +* Trident. Any copying, reproduction or redistribution of the Software in +* whole or in part by any means not in accordance with the License Agreement +* or as agreed in writing by Trident is expressly prohibited. +* +* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE +* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE +* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND +* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES +* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT +* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL +* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY +* TO USE THE SOFTWARE. +* +* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, +* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, +* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS +* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE +* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM +* TRIDENT'S NEGLIGENCE. $ +* +*/ +#ifndef __DRXDRIVER_H__ +#define __DRXDRIVER_H__ +/*------------------------------------------------------------------------- +INCLUDES +-------------------------------------------------------------------------*/ +#include "bsp_types.h" +#include "bsp_i2c.h" +#include "bsp_tuner.h" +#include "bsp_host.h" + +#ifdef __cplusplus +extern "C" { +#endif +/*------------------------------------------------------------------------- +TYPEDEFS +-------------------------------------------------------------------------*/ + +/*------------------------------------------------------------------------- +DEFINES +-------------------------------------------------------------------------*/ + +/************** +* +* This section configures the DRX Data Access Protocols (DAPs). +* +**************/ + +/** +* \def DRXDAP_SINGLE_MASTER +* \brief Enable I2C single or I2C multimaster mode on host. +* +* Set to 1 to enable single master mode +* Set to 0 to enable multi master mode +* +* The actual DAP implementation may be restricted to only one of the modes. +* A compiler warning or error will be generated if the DAP implementation +* overides or cannot handle the mode defined below. +* +*/ +#ifndef DRXDAP_SINGLE_MASTER +#define DRXDAP_SINGLE_MASTER 0 +#endif + +/** +* \def DRXDAP_MAX_WCHUNKSIZE +* \brief Defines maximum chunksize of an i2c write action by host. +* +* This indicates the maximum size of data the I2C device driver is able to +* write at a time. This includes I2C device address and register addressing. +* +* This maximum size may be restricted by the actual DAP implementation. +* A compiler warning or error will be generated if the DAP implementation +* overides or cannot handle the chunksize defined below. +* +* Beware that the DAP uses DRXDAP_MAX_WCHUNKSIZE to create a temporary data +* buffer. Do not undefine or choose too large, unless your system is able to +* handle a stack buffer of that size. +* +*/ +#ifndef DRXDAP_MAX_WCHUNKSIZE +#define DRXDAP_MAX_WCHUNKSIZE 60 +#endif + +/** +* \def DRXDAP_MAX_RCHUNKSIZE +* \brief Defines maximum chunksize of an i2c read action by host. +* +* This indicates the maximum size of data the I2C device driver is able to read +* at a time. Minimum value is 2. Also, the read chunk size must be even. +* +* This maximum size may be restricted by the actual DAP implementation. +* A compiler warning or error will be generated if the DAP implementation +* overides or cannot handle the chunksize defined below. +* +*/ +#ifndef DRXDAP_MAX_RCHUNKSIZE +#define DRXDAP_MAX_RCHUNKSIZE 60 +#endif + +/************** +* +* This section describes drxdriver defines. +* +**************/ + +/** +* \def DRX_UNKNOWN +* \brief Generic UNKNOWN value for DRX enumerated types. +* +* Used to indicate that the parameter value is unknown or not yet initalized. +*/ +#ifndef DRX_UNKNOWN +#define DRX_UNKNOWN (254) +#endif + +/** +* \def DRX_AUTO +* \brief Generic AUTO value for DRX enumerated types. +* +* Used to instruct the driver to automatically determine the value of the +* parameter. +*/ +#ifndef DRX_AUTO +#define DRX_AUTO (255) +#endif + + +/************** +* +* This section describes flag definitions for the device capbilities. +* +**************/ + +/** +* \brief LNA capability flag +* +* Device has a Low Noise Amplifier +* +*/ +#define DRX_CAPABILITY_HAS_LNA (1UL << 0) +/** +* \brief OOB-RX capability flag +* +* Device has OOB-RX +* +*/ +#define DRX_CAPABILITY_HAS_OOBRX (1UL << 1) +/** +* \brief ATV capability flag +* +* Device has ATV +* +*/ +#define DRX_CAPABILITY_HAS_ATV (1UL << 2) +/** +* \brief DVB-T capability flag +* +* Device has DVB-T +* +*/ +#define DRX_CAPABILITY_HAS_DVBT (1UL << 3) +/** +* \brief ITU-B capability flag +* +* Device has ITU-B +* +*/ +#define DRX_CAPABILITY_HAS_ITUB (1UL << 4) +/** +* \brief Audio capability flag +* +* Device has Audio +* +*/ +#define DRX_CAPABILITY_HAS_AUD (1UL << 5) +/** +* \brief SAW switch capability flag +* +* Device has SAW switch +* +*/ +#define DRX_CAPABILITY_HAS_SAWSW (1UL << 6) +/** +* \brief GPIO1 capability flag +* +* Device has GPIO1 +* +*/ +#define DRX_CAPABILITY_HAS_GPIO1 (1UL << 7) +/** +* \brief GPIO2 capability flag +* +* Device has GPIO2 +* +*/ +#define DRX_CAPABILITY_HAS_GPIO2 (1UL << 8) +/** +* \brief IRQN capability flag +* +* Device has IRQN +* +*/ +#define DRX_CAPABILITY_HAS_IRQN (1UL << 9) +/** +* \brief 8VSB capability flag +* +* Device has 8VSB +* +*/ +#define DRX_CAPABILITY_HAS_8VSB (1UL << 10) +/** +* \brief SMA-TX capability flag +* +* Device has SMATX +* +*/ +#define DRX_CAPABILITY_HAS_SMATX (1UL << 11) +/** +* \brief SMA-RX capability flag +* +* Device has SMARX +* +*/ +#define DRX_CAPABILITY_HAS_SMARX (1UL << 12) +/** +* \brief ITU-A/C capability flag +* +* Device has ITU-A/C +* +*/ +#define DRX_CAPABILITY_HAS_ITUAC (1UL << 13) + +/*------------------------------------------------------------------------- +MACROS +-------------------------------------------------------------------------*/ +/* Macros to stringify the version number */ +#define DRX_VERSIONSTRING( MAJOR, MINOR, PATCH ) \ + DRX_VERSIONSTRING_HELP(MAJOR)"." \ + DRX_VERSIONSTRING_HELP(MINOR)"." \ + DRX_VERSIONSTRING_HELP(PATCH) +#define DRX_VERSIONSTRING_HELP( NUM ) #NUM + +/** +* \brief Macro to create byte array elements from 16 bit integers. +* This macro is used to create byte arrays for block writes. +* Block writes speed up I2C traffic between host and demod. +* The macro takes care of the required byte order in a 16 bits word. +* x->lowbyte(x), highbyte(x) +*/ +#define DRX_16TO8( x ) ((u8_t) (((u16_t)x) &0xFF)), \ + ((u8_t)((((u16_t)x)>>8)&0xFF)) + +/** +* \brief Macro to sign extend signed 9 bit value to signed 16 bit value +*/ +#define DRX_S9TOS16(x) ((((u16_t)x)&0x100 )?((s16_t)((u16_t)(x)|0xFF00)):(x)) + +/** +* \brief Macro to sign extend signed 9 bit value to signed 16 bit value +*/ +#define DRX_S24TODRXFREQ(x) ( ( ( (u32_t) x ) & 0x00800000UL ) ? \ + ( (DRXFrequency_t) \ + ( ( (u32_t) x ) | 0xFF000000 ) ) : \ + ( (DRXFrequency_t) x ) ) + +/** +* \brief Macro to convert 16 bit register value to a DRXFrequency_t +*/ +#define DRX_U16TODRXFREQ(x) ( ( x & 0x8000 ) ? \ + ( (DRXFrequency_t) \ + ( ( (u32_t) x ) | 0xFFFF0000 ) ) : \ + ( (DRXFrequency_t) x ) ) + +/*------------------------------------------------------------------------- +ENUM +-------------------------------------------------------------------------*/ + +/** +* \enum DRXStandard_t +* \brief Modulation standards. +*/ +typedef enum { + DRX_STANDARD_DVBT = 0, /**< Terrestrial DVB-T. */ + DRX_STANDARD_8VSB, /**< Terrestrial 8VSB. */ + DRX_STANDARD_NTSC, /**< Terrestrial\Cable analog NTSC. */ + DRX_STANDARD_PAL_SECAM_BG, /**< Terrestrial analog PAL/SECAM B/G */ + DRX_STANDARD_PAL_SECAM_DK, /**< Terrestrial analog PAL/SECAM D/K */ + DRX_STANDARD_PAL_SECAM_I, /**< Terrestrial analog PAL/SECAM I */ + DRX_STANDARD_PAL_SECAM_L, /**< Terrestrial analog PAL/SECAM L + with negative modulation */ + DRX_STANDARD_PAL_SECAM_LP, /**< Terrestrial analog PAL/SECAM L + with positive modulation */ + DRX_STANDARD_ITU_A, /**< Cable ITU ANNEX A. */ + DRX_STANDARD_ITU_B, /**< Cable ITU ANNEX B. */ + DRX_STANDARD_ITU_C, /**< Cable ITU ANNEX C. */ + DRX_STANDARD_ITU_D, /**< Cable ITU ANNEX D. */ + DRX_STANDARD_FM, /**< Terrestrial\Cable FM radio */ + DRX_STANDARD_DTMB, /**< Terrestrial DTMB standard (China)*/ + DRX_STANDARD_UNKNOWN = DRX_UNKNOWN, /**< Standard unknown. */ + DRX_STANDARD_AUTO = DRX_AUTO /**< Autodetect standard. */ +} DRXStandard_t, *pDRXStandard_t; + +/** +* \enum DRXStandard_t +* \brief Modulation sub-standards. +*/ +typedef enum { + DRX_SUBSTANDARD_MAIN = 0, /**< Main subvariant of standard */ + DRX_SUBSTANDARD_ATV_BG_SCANDINAVIA, + DRX_SUBSTANDARD_ATV_DK_POLAND, + DRX_SUBSTANDARD_ATV_DK_CHINA, + DRX_SUBSTANDARD_UNKNOWN = DRX_UNKNOWN, /**< Sub-standard unknown. */ + DRX_SUBSTANDARD_AUTO = DRX_AUTO /**< Auto (default) sub-standard */ +} DRXSubstandard_t, *pDRXSubstandard_t; + +/** +* \enum DRXBandwidth_t +* \brief Channel bandwidth or channel spacing. +*/ +typedef enum { + DRX_BANDWIDTH_8MHZ = 0, /**< Bandwidth 8 MHz. */ + DRX_BANDWIDTH_7MHZ, /**< Bandwidth 7 MHz. */ + DRX_BANDWIDTH_6MHZ, /**< Bandwidth 6 MHz. */ + DRX_BANDWIDTH_UNKNOWN = DRX_UNKNOWN, /**< Bandwidth unknown. */ + DRX_BANDWIDTH_AUTO = DRX_AUTO /**< Auto Set Bandwidth */ +} DRXBandwidth_t, *pDRXBandwidth_t; + +/** +* \enum DRXMirror_t +* \brief Indicate if channel spectrum is mirrored or not. +*/ +typedef enum { + DRX_MIRROR_NO = 0, /**< Spectrum is not mirrored. */ + DRX_MIRROR_YES, /**< Spectrum is mirrored. */ + DRX_MIRROR_UNKNOWN = DRX_UNKNOWN, /**< Unknown if spectrum is mirrored. */ + DRX_MIRROR_AUTO = DRX_AUTO /**< Autodetect if spectrum is mirrored. */ +} DRXMirror_t, *pDRXMirror_t; + +/** +* \enum DRXConstellation_t +* \brief Constellation type of the channel. +*/ +typedef enum { + DRX_CONSTELLATION_BPSK = 0, /**< Modulation is BPSK. */ + DRX_CONSTELLATION_QPSK, /**< Constellation is QPSK. */ + DRX_CONSTELLATION_PSK8, /**< Constellation is PSK8. */ + DRX_CONSTELLATION_QAM16, /**< Constellation is QAM16. */ + DRX_CONSTELLATION_QAM32, /**< Constellation is QAM32. */ + DRX_CONSTELLATION_QAM64, /**< Constellation is QAM64. */ + DRX_CONSTELLATION_QAM128, /**< Constellation is QAM128. */ + DRX_CONSTELLATION_QAM256, /**< Constellation is QAM256. */ + DRX_CONSTELLATION_QAM512, /**< Constellation is QAM512. */ + DRX_CONSTELLATION_QAM1024, /**< Constellation is QAM1024. */ + DRX_CONSTELLATION_QPSK_NR, /**< Constellation is QPSK_NR */ + DRX_CONSTELLATION_UNKNOWN = DRX_UNKNOWN, /**< Constellation unknown. */ + DRX_CONSTELLATION_AUTO = DRX_AUTO /**< Autodetect constellation. */ +} DRXConstellation_t, *pDRXConstellation_t; + +/** +* \enum DRXHierarchy_t +* \brief Hierarchy of the channel. +*/ +typedef enum { + DRX_HIERARCHY_NONE = 0, /**< None hierarchical channel. */ + DRX_HIERARCHY_ALPHA1, /**< Hierarchical channel, alpha=1. */ + DRX_HIERARCHY_ALPHA2, /**< Hierarchical channel, alpha=2. */ + DRX_HIERARCHY_ALPHA4, /**< Hierarchical channel, alpha=4. */ + DRX_HIERARCHY_UNKNOWN = DRX_UNKNOWN, /**< Hierarchy unknown. */ + DRX_HIERARCHY_AUTO = DRX_AUTO /**< Autodetect hierarchy. */ +} DRXHierarchy_t, *pDRXHierarchy_t; + +/** +* \enum DRXPriority_t +* \brief Channel priority in case of hierarchical transmission. +*/ +typedef enum { + DRX_PRIORITY_LOW = 0, /**< Low priority channel. */ + DRX_PRIORITY_HIGH, /**< High priority channel. */ + DRX_PRIORITY_UNKNOWN = DRX_UNKNOWN /**< Priority unknown. */ +} DRXPriority_t, *pDRXPriority_t; + +/** +* \enum DRXCoderate_t +* \brief Channel priority in case of hierarchical transmission. +*/ +typedef enum { + DRX_CODERATE_1DIV2 = 0, /**< Code rate 1/2nd. */ + DRX_CODERATE_2DIV3, /**< Code rate 2/3nd. */ + DRX_CODERATE_3DIV4, /**< Code rate 3/4nd. */ + DRX_CODERATE_5DIV6, /**< Code rate 5/6nd. */ + DRX_CODERATE_7DIV8, /**< Code rate 7/8nd. */ + DRX_CODERATE_UNKNOWN = DRX_UNKNOWN, /**< Code rate unknown. */ + DRX_CODERATE_AUTO = DRX_AUTO /**< Autodetect code rate. */ +} DRXCoderate_t, *pDRXCoderate_t; + +/** +* \enum DRXGuard_t +* \brief Guard interval of a channel. +*/ +typedef enum { + DRX_GUARD_1DIV32 = 0, /**< Guard interval 1/32nd. */ + DRX_GUARD_1DIV16, /**< Guard interval 1/16th. */ + DRX_GUARD_1DIV8, /**< Guard interval 1/8th. */ + DRX_GUARD_1DIV4, /**< Guard interval 1/4th. */ + DRX_GUARD_UNKNOWN = DRX_UNKNOWN, /**< Guard interval unknown. */ + DRX_GUARD_AUTO = DRX_AUTO /**< Autodetect guard interval. */ +} DRXGuard_t, *pDRXGuard_t; + +/** +* \enum DRXFftmode_t +* \brief FFT mode. +*/ +typedef enum { + DRX_FFTMODE_2K = 0, /**< 2K FFT mode. */ + DRX_FFTMODE_4K, /**< 4K FFT mode. */ + DRX_FFTMODE_8K, /**< 8K FFT mode. */ + DRX_FFTMODE_UNKNOWN = DRX_UNKNOWN, /**< FFT mode unknown. */ + DRX_FFTMODE_AUTO = DRX_AUTO /**< Autodetect FFT mode. */ +} DRXFftmode_t, *pDRXFftmode_t; + +/** +* \enum DRXClassification_t +* \brief Channel classification. +*/ +typedef enum { + DRX_CLASSIFICATION_GAUSS = 0, /**< Gaussion noise. */ + DRX_CLASSIFICATION_HVY_GAUSS, /**< Heavy Gaussion noise. */ + DRX_CLASSIFICATION_COCHANNEL, /**< Co-channel. */ + DRX_CLASSIFICATION_STATIC, /**< Static echo. */ + DRX_CLASSIFICATION_MOVING, /**< Moving echo. */ + DRX_CLASSIFICATION_ZERODB, /**< Zero dB echo. */ + DRX_CLASSIFICATION_UNKNOWN = DRX_UNKNOWN, /**< Unknown classification */ + DRX_CLASSIFICATION_AUTO = DRX_AUTO /**< Autodetect classification. */ +} DRXClassification_t, *pDRXClassification_t; + +/** +* /enum DRXInterleaveModes_t +* /brief Interleave modes +*/ +typedef enum { + DRX_INTERLEAVEMODE_I128_J1 = 0, + DRX_INTERLEAVEMODE_I128_J1_V2, + DRX_INTERLEAVEMODE_I128_J2, + DRX_INTERLEAVEMODE_I64_J2, + DRX_INTERLEAVEMODE_I128_J3, + DRX_INTERLEAVEMODE_I32_J4, + DRX_INTERLEAVEMODE_I128_J4, + DRX_INTERLEAVEMODE_I16_J8, + DRX_INTERLEAVEMODE_I128_J5, + DRX_INTERLEAVEMODE_I8_J16, + DRX_INTERLEAVEMODE_I128_J6, + DRX_INTERLEAVEMODE_RESERVED_11, + DRX_INTERLEAVEMODE_I128_J7, + DRX_INTERLEAVEMODE_RESERVED_13, + DRX_INTERLEAVEMODE_I128_J8, + DRX_INTERLEAVEMODE_RESERVED_15, + DRX_INTERLEAVEMODE_I12_J17, + DRX_INTERLEAVEMODE_I5_J4, + DRX_INTERLEAVEMODE_B52_M240, + DRX_INTERLEAVEMODE_B52_M720, + DRX_INTERLEAVEMODE_B52_M48, + DRX_INTERLEAVEMODE_B52_M0, + DRX_INTERLEAVEMODE_UNKNOWN = DRX_UNKNOWN, /**< Unknown interleave mode */ + DRX_INTERLEAVEMODE_AUTO = DRX_AUTO /**< Autodetect interleave mode */ +} DRXInterleaveModes_t, *pDRXInterleaveModes_t; + +/** +* \enum DRXCarrier_t +* \brief Channel Carrier Mode. +*/ +typedef enum { + DRX_CARRIER_MULTI = 0, /**< Multi carrier mode */ + DRX_CARRIER_SINGLE, /**< Single carrier mode */ + DRX_CARRIER_UNKNOWN = DRX_UNKNOWN, /**< Carrier mode unknown. */ + DRX_CARRIER_AUTO = DRX_AUTO /**< Autodetect carrier mode */ +} DRXCarrier_t, *pDRXCarrier_t; + +/** +* \enum DRXFramemode_t +* \brief Channel Frame Mode. +*/ +typedef enum { + DRX_FRAMEMODE_420 = 0, /**< 420 with variable PN */ + DRX_FRAMEMODE_595, /**< 595 */ + DRX_FRAMEMODE_945, /**< 945 with variable PN */ + DRX_FRAMEMODE_420_FIXED_PN, /**< 420 with fixed PN */ + DRX_FRAMEMODE_945_FIXED_PN, /**< 945 with fixed PN */ + DRX_FRAMEMODE_UNKNOWN = DRX_UNKNOWN, /**< Frame mode unknown. */ + DRX_FRAMEMODE_AUTO = DRX_AUTO /**< Autodetect frame mode */ +} DRXFramemode_t, *pDRXFramemode_t; + +/** +* \enum DRXTPSFrame_t +* \brief Frame number in current super-frame. +*/ +typedef enum { + DRX_TPS_FRAME1 = 0, /**< TPS frame 1. */ + DRX_TPS_FRAME2, /**< TPS frame 2. */ + DRX_TPS_FRAME3, /**< TPS frame 3. */ + DRX_TPS_FRAME4, /**< TPS frame 4. */ + DRX_TPS_FRAME_UNKNOWN = DRX_UNKNOWN /**< TPS frame unknown. */ +} DRXTPSFrame_t, *pDRXTPSFrame_t; + +/** +* \enum DRXLDPC_t +* \brief TPS LDPC . +*/ +typedef enum { + DRX_LDPC_0_4 = 0, /**< LDPC 0.4 */ + DRX_LDPC_0_6, /**< LDPC 0.6 */ + DRX_LDPC_0_8, /**< LDPC 0.8 */ + DRX_LDPC_UNKNOWN = DRX_UNKNOWN, /**< LDPC unknown. */ + DRX_LDPC_AUTO = DRX_AUTO /**< Autodetect LDPC */ +} DRXLDPC_t, *pDRXLDPC_t; + +/** +* \enum DRXPilotMode_t +* \brief Pilot modes in DTMB. +*/ +typedef enum { + DRX_PILOT_ON = 0, /**< Pilot On */ + DRX_PILOT_OFF, /**< Pilot Off */ + DRX_PILOT_UNKNOWN = DRX_UNKNOWN, /**< Pilot unknown. */ + DRX_PILOT_AUTO = DRX_AUTO /**< Autodetect Pilot */ +} DRXPilotMode_t, *pDRXPilotMode_t; + + + +/** +* \enum DRXCtrlIndex_t +* \brief Indices of the control functions. +*/ +typedef u32_t DRXCtrlIndex_t, *pDRXCtrlIndex_t; + +#ifndef DRX_CTRL_BASE +#define DRX_CTRL_BASE ((DRXCtrlIndex_t)0) +#endif + +#define DRX_CTRL_NOP ( DRX_CTRL_BASE + 0)/**< No Operation */ +#define DRX_CTRL_PROBE_DEVICE ( DRX_CTRL_BASE + 1)/**< Probe device */ + +#define DRX_CTRL_LOAD_UCODE ( DRX_CTRL_BASE + 2)/**< Load microcode */ +#define DRX_CTRL_VERIFY_UCODE ( DRX_CTRL_BASE + 3)/**< Verify microcode */ +#define DRX_CTRL_SET_CHANNEL ( DRX_CTRL_BASE + 4)/**< Set channel */ +#define DRX_CTRL_GET_CHANNEL ( DRX_CTRL_BASE + 5)/**< Get channel */ +#define DRX_CTRL_LOCK_STATUS ( DRX_CTRL_BASE + 6)/**< Get lock status */ +#define DRX_CTRL_SIG_QUALITY ( DRX_CTRL_BASE + 7)/**< Get signal quality */ +#define DRX_CTRL_SIG_STRENGTH ( DRX_CTRL_BASE + 8)/**< Get signal strength*/ +#define DRX_CTRL_RF_POWER ( DRX_CTRL_BASE + 9)/**< Get RF power */ +#define DRX_CTRL_CONSTEL ( DRX_CTRL_BASE + 10)/**< Get constel point */ +#define DRX_CTRL_SCAN_INIT ( DRX_CTRL_BASE + 11)/**< Initialize scan */ +#define DRX_CTRL_SCAN_NEXT ( DRX_CTRL_BASE + 12)/**< Scan for next */ +#define DRX_CTRL_SCAN_STOP ( DRX_CTRL_BASE + 13)/**< Stop scan */ +#define DRX_CTRL_TPS_INFO ( DRX_CTRL_BASE + 14)/**< Get TPS info */ +#define DRX_CTRL_SET_CFG ( DRX_CTRL_BASE + 15)/**< Set configuration */ +#define DRX_CTRL_GET_CFG ( DRX_CTRL_BASE + 16)/**< Get configuration */ +#define DRX_CTRL_VERSION ( DRX_CTRL_BASE + 17)/**< Get version info */ +#define DRX_CTRL_I2C_BRIDGE ( DRX_CTRL_BASE + 18)/**< Open/close bridge */ +#define DRX_CTRL_SET_STANDARD ( DRX_CTRL_BASE + 19)/**< Set demod std */ +#define DRX_CTRL_GET_STANDARD ( DRX_CTRL_BASE + 20)/**< Get demod std */ +#define DRX_CTRL_SET_OOB ( DRX_CTRL_BASE + 21)/**< Set OOB param */ +#define DRX_CTRL_GET_OOB ( DRX_CTRL_BASE + 22)/**< Get OOB param */ +#define DRX_CTRL_AUD_SET_STANDARD (DRX_CTRL_BASE + 23)/**< Set audio param */ +#define DRX_CTRL_AUD_GET_STANDARD (DRX_CTRL_BASE + 24)/**< Get audio param */ +#define DRX_CTRL_AUD_GET_STATUS ( DRX_CTRL_BASE + 25)/**< Read RDS */ +#define DRX_CTRL_AUD_BEEP ( DRX_CTRL_BASE + 26)/**< Read RDS */ +#define DRX_CTRL_I2C_READWRITE ( DRX_CTRL_BASE + 27)/**< Read/write I2C */ +#define DRX_CTRL_PROGRAM_TUNER ( DRX_CTRL_BASE + 28)/**< Program tuner */ + + /* Professional */ +#define DRX_CTRL_MB_CFG ( DRX_CTRL_BASE + 29) /**< */ +#define DRX_CTRL_MB_READ ( DRX_CTRL_BASE + 30) /**< */ +#define DRX_CTRL_MB_WRITE ( DRX_CTRL_BASE + 31) /**< */ +#define DRX_CTRL_MB_CONSTEL ( DRX_CTRL_BASE + 32) /**< */ +#define DRX_CTRL_MB_MER ( DRX_CTRL_BASE + 33) /**< */ + + /* Misc */ +#define DRX_CTRL_UIO_CFG DRX_CTRL_SET_UIO_CFG /**< Configure UIO */ +#define DRX_CTRL_SET_UIO_CFG ( DRX_CTRL_BASE + 34) /**< Configure UIO */ +#define DRX_CTRL_GET_UIO_CFG ( DRX_CTRL_BASE + 35) /**< Configure UIO */ +#define DRX_CTRL_UIO_READ ( DRX_CTRL_BASE + 36) /**< Read from UIO */ +#define DRX_CTRL_UIO_WRITE ( DRX_CTRL_BASE + 37) /**< Write to UIO */ +#define DRX_CTRL_READ_EVENTS ( DRX_CTRL_BASE + 38) /**< Read events */ +#define DRX_CTRL_HDL_EVENTS ( DRX_CTRL_BASE + 39) /**< Handle events */ +#define DRX_CTRL_POWER_MODE ( DRX_CTRL_BASE + 40) /**< Set power mode */ +#define DRX_CTRL_LOAD_FILTER ( DRX_CTRL_BASE + 41) /**< Load chan. filter */ +#define DRX_CTRL_VALIDATE_UCODE ( DRX_CTRL_BASE + 42) /**< Validate ucode */ +#define DRX_CTRL_DUMP_REGISTERS ( DRX_CTRL_BASE + 43) /**< Dump registers */ + +#define DRX_CTRL_MAX ( DRX_CTRL_BASE + 44) /* never to be used */ + +/** +* \enum DRXUCodeAction_t +* \brief Used to indicate if firmware has to be uploaded or verified. +*/ + +typedef enum { + UCODE_UPLOAD, /**< Upload the microcode image to device */ + UCODE_VERIFY /**< Compare microcode image with code on device */ +} DRXUCodeAction_t, *pDRXUCodeAction_t; + + +/** +* \enum DRXLockStatus_t +* \brief Used to reflect current lock status of demodulator. +* +* The generic lock states have device dependent semantics. +*/ +typedef enum{ + DRX_NEVER_LOCK = 0, /**< Device will never lock on this signal */ + DRX_NOT_LOCKED, /**< Device has no lock at all */ + DRX_LOCK_STATE_1, /**< Generic lock state */ + DRX_LOCK_STATE_2, /**< Generic lock state */ + DRX_LOCK_STATE_3, /**< Generic lock state */ + DRX_LOCK_STATE_4, /**< Generic lock state */ + DRX_LOCK_STATE_5, /**< Generic lock state */ + DRX_LOCK_STATE_6, /**< Generic lock state */ + DRX_LOCK_STATE_7, /**< Generic lock state */ + DRX_LOCK_STATE_8, /**< Generic lock state */ + DRX_LOCK_STATE_9, /**< Generic lock state */ + DRX_LOCKED /**< Device is in lock */ +} DRXLockStatus_t, *pDRXLockStatus_t; + +/** +* \enum DRXUIO_t +* \brief Used to address a User IO (UIO). +*/ +typedef enum{ + DRX_UIO1 , + DRX_UIO2 , + DRX_UIO3 , + DRX_UIO4 , + DRX_UIO5 , + DRX_UIO6 , + DRX_UIO7 , + DRX_UIO8 , + DRX_UIO9 , + DRX_UIO10 , + DRX_UIO11 , + DRX_UIO12 , + DRX_UIO13 , + DRX_UIO14 , + DRX_UIO15 , + DRX_UIO16 , + DRX_UIO17 , + DRX_UIO18 , + DRX_UIO19 , + DRX_UIO20 , + DRX_UIO21 , + DRX_UIO22 , + DRX_UIO23 , + DRX_UIO24 , + DRX_UIO25 , + DRX_UIO26 , + DRX_UIO27 , + DRX_UIO28 , + DRX_UIO29 , + DRX_UIO30 , + DRX_UIO31 , + DRX_UIO32 , + DRX_UIO_MAX = DRX_UIO32 +} DRXUIO_t, *pDRXUIO_t; + +/** +* \enum DRXUIOMode_t +* \brief Used to configure the modus oprandi of a UIO. +* +* DRX_UIO_MODE_FIRMWARE is an old uio mode. +* It is replaced by the modes DRX_UIO_MODE_FIRMWARE0 .. DRX_UIO_MODE_FIRMWARE9. +* To be backward compatible DRX_UIO_MODE_FIRMWARE is equivalent to +* DRX_UIO_MODE_FIRMWARE0. +*/ +typedef enum{ + DRX_UIO_MODE_DISABLE = 0x01, /**< not used, pin is configured as input */ + DRX_UIO_MODE_READWRITE = 0x02, /**< used for read/write by application */ + DRX_UIO_MODE_FIRMWARE = 0x04, /**< controlled by firmware, function 0 */ + DRX_UIO_MODE_FIRMWARE0 = DRX_UIO_MODE_FIRMWARE , /**< same as above */ + DRX_UIO_MODE_FIRMWARE1 = 0x08, /**< controlled by firmware, function 1 */ + DRX_UIO_MODE_FIRMWARE2 = 0x10, /**< controlled by firmware, function 2 */ + DRX_UIO_MODE_FIRMWARE3 = 0x20, /**< controlled by firmware, function 3 */ + DRX_UIO_MODE_FIRMWARE4 = 0x40, /**< controlled by firmware, function 4 */ + DRX_UIO_MODE_FIRMWARE5 = 0x80 /**< controlled by firmware, function 5 */ +} DRXUIOMode_t, *pDRXUIOMode_t; + +/** +* \enum DRXOOBDownstreamStandard_t +* \brief Used to select OOB standard. +* +* Based on ANSI 55-1 and 55-2 +*/ +typedef enum { + DRX_OOB_MODE_A = 0, /**< ANSI 55-1 */ + DRX_OOB_MODE_B_GRADE_A, /**< ANSI 55-2 A */ + DRX_OOB_MODE_B_GRADE_B /**< ANSI 55-2 B */ +} DRXOOBDownstreamStandard_t, *pDRXOOBDownstreamStandard_t; + + +/*------------------------------------------------------------------------- +STRUCTS +-------------------------------------------------------------------------*/ + +/*============================================================================*/ +/*============================================================================*/ +/*== CTRL CFG related data structures ========================================*/ +/*============================================================================*/ +/*============================================================================*/ + +/** +* \enum DRXCfgType_t +* \brief Generic configuration function identifiers. +*/ +typedef u32_t DRXCfgType_t, *pDRXCfgType_t; + +#ifndef DRX_CFG_BASE +#define DRX_CFG_BASE ((DRXCfgType_t)0) +#endif + +#define DRX_CFG_MPEG_OUTPUT ( DRX_CFG_BASE + 0) /* MPEG TS output */ +#define DRX_CFG_PKTERR ( DRX_CFG_BASE + 1) /* Packet Error */ +#define DRX_CFG_SYMCLK_OFFS ( DRX_CFG_BASE + 2) /* Symbol Clk Offset */ +#define DRX_CFG_SMA ( DRX_CFG_BASE + 3) /* Smart Antenna */ +#define DRX_CFG_PINSAFE ( DRX_CFG_BASE + 4) /* Pin safe mode */ +#define DRX_CFG_SUBSTANDARD ( DRX_CFG_BASE + 5) /* substandard */ +#define DRX_CFG_AUD_VOLUME ( DRX_CFG_BASE + 6) /* volume */ +#define DRX_CFG_AUD_RDS ( DRX_CFG_BASE + 7) /* rds */ +#define DRX_CFG_AUD_AUTOSOUND ( DRX_CFG_BASE + 8) /* ASS & ASC */ +#define DRX_CFG_AUD_ASS_THRES ( DRX_CFG_BASE + 9) /* ASS Thresholds */ +#define DRX_CFG_AUD_DEVIATION ( DRX_CFG_BASE + 10) /* Deviation */ +#define DRX_CFG_AUD_PRESCALE ( DRX_CFG_BASE + 11) /* Prescale */ +#define DRX_CFG_AUD_MIXER ( DRX_CFG_BASE + 12) /* Mixer */ +#define DRX_CFG_AUD_AVSYNC ( DRX_CFG_BASE + 13) /* AVSync */ +#define DRX_CFG_AUD_CARRIER ( DRX_CFG_BASE + 14) /* Audio carriers */ +#define DRX_CFG_I2S_OUTPUT ( DRX_CFG_BASE + 15) /* I2S output */ +#define DRX_CFG_ATV_STANDARD ( DRX_CFG_BASE + 16) /* ATV standard */ +#define DRX_CFG_SQI_SPEED ( DRX_CFG_BASE + 17) /* SQI speed */ +#define DRX_CTRL_CFG_MAX ( DRX_CFG_BASE + 18) /* never to be used */ + +#define DRX_CFG_PINS_SAFE_MODE DRX_CFG_PINSAFE +/*============================================================================*/ +/*============================================================================*/ +/*== CTRL related data structures ============================================*/ +/*============================================================================*/ +/*============================================================================*/ + +/** +* \struct DRXUCodeInfo_t +* \brief Parameters for microcode upload and verfiy. +* +* Used by DRX_CTRL_LOAD_UCODE and DRX_CTRL_VERIFY_UCODE +*/ +typedef struct { + pu8_t mcData; /**< Pointer to microcode image. */ + u16_t mcSize; /**< Microcode image size. */ +} DRXUCodeInfo_t, *pDRXUCodeInfo_t; + +/** +* \struct DRXMcVersionRec_t +* \brief Microcode version record +* Version numbers are stored in BCD format, as usual: +* o major number = bits 31-20 (first three nibbles of MSW) +* o minor number = bits 19-16 (fourth nibble of MSW) +* o patch number = bits 15-0 (remaining nibbles in LSW) +* +* The device type indicates for which the device is meant. It is based on the +* JTAG ID, using everything except the bond ID and the metal fix. +* +* Special values: +* - mcDevType == 0 => any device allowed +* - mcBaseVersion == 0.0.0 => full microcode (mcVersion is the version) +* - mcBaseVersion != 0.0.0 => patch microcode, the base microcode version +* (mcVersion is the version) +*/ +#define AUX_VER_RECORD 0x8000 + +typedef struct { + u16_t auxType; /* type of aux data - 0x8000 for version record */ + u32_t mcDevType; /* device type, based on JTAG ID */ + u32_t mcVersion; /* version of microcode */ + u32_t mcBaseVersion; /* in case of patch: the original microcode version */ +} DRXMcVersionRec_t, *pDRXMcVersionRec_t; + +/*========================================*/ + +/** +* \struct DRXFilterInfo_t +* \brief Parameters for loading filter coefficients +* +* Used by DRX_CTRL_LOAD_FILTER +*/ +typedef struct { + pu8_t dataRe; /**< pointer to coefficients for RE */ + pu8_t dataIm; /**< pointer to coefficients for IM */ + u16_t sizeRe; /**< size of coefficients for RE */ + u16_t sizeIm; /**< size of coefficients for IM */ +} DRXFilterInfo_t, *pDRXFilterInfo_t; + + + +/*========================================*/ + +/** +* \struct DRXChannel_t +* \brief The set of parameters describing a single channel. +* +* Used by DRX_CTRL_SET_CHANNEL and DRX_CTRL_GET_CHANNEL. +* Only certain fields need to be used for a specfic standard. +* +*/ +typedef struct { + DRXFrequency_t frequency; /**< frequency in kHz */ + DRXBandwidth_t bandwidth; /**< bandwidth */ + DRXMirror_t mirror; /**< mirrored or not on RF */ + DRXConstellation_t constellation; /**< constellation */ + DRXHierarchy_t hierarchy; /**< hierarchy */ + DRXPriority_t priority; /**< priority */ + DRXCoderate_t coderate; /**< coderate */ + DRXGuard_t guard; /**< guard interval */ + DRXFftmode_t fftmode; /**< fftmode */ + DRXClassification_t classification; /**< classification */ + DRXSymbolrate_t symbolrate; /**< symbolrate in symbols/sec */ + DRXInterleaveModes_t interleavemode; /**< interleaveMode QAM */ + DRXLDPC_t ldpc; /**< ldpc */ + DRXCarrier_t carrier; /**< carrier */ + DRXFramemode_t framemode; /**< frame mode */ + DRXPilotMode_t pilot; /**< pilot mode */ +} DRXChannel_t, *pDRXChannel_t; + +/*========================================*/ + +/** +* \struct DRXSigQuality_t +* Signal quality metrics. +* +* Used by DRX_CTRL_SIG_QUALITY. +*/ +typedef struct { + u16_t MER; /**< in steps of 0.1 dB */ + u32_t preViterbiBER ; /**< in steps of 1/scaleFactorBER */ + u32_t postViterbiBER ; /**< in steps of 1/scaleFactorBER */ + u32_t scaleFactorBER; /**< scale factor for BER */ + u16_t packetError ; /**< number of packet errors */ + u32_t postReedSolomonBER ; /**< in steps of 1/scaleFactorBER */ + u32_t preLdpcBER; /**< in steps of 1/scaleFactorBER */ + u32_t averIter; /**< in steps of 0.01 */ + u16_t indicator; /**< indicative signal quality low=0..100=high */ +}DRXSigQuality_t, *pDRXSigQuality_t; + + +typedef enum { + DRX_SQI_SPEED_FAST = 0, + DRX_SQI_SPEED_MEDIUM, + DRX_SQI_SPEED_SLOW, + DRX_SQI_SPEED_UNKNOWN = DRX_UNKNOWN +} DRXCfgSqiSpeed_t, *pDRXCfgSqiSpeed_t; + +/*========================================*/ + +/** +* \struct DRXComplex_t +* A complex number. +* +* Used by DRX_CTRL_CONSTEL. +*/ +typedef struct { + s16_t im; /**< Imaginary part. */ + s16_t re; /**< Real part. */ +} DRXComplex_t, *pDRXComplex_t; + + +/*========================================*/ + +/** +* \struct DRXFrequencyPlan_t +* Array element of a frequency plan. +* +* Used by DRX_CTRL_SCAN_INIT. +*/ +typedef struct { + DRXFrequency_t first; /**< First centre frequency in this band */ + DRXFrequency_t last; /**< Last centre frequency in this band */ + DRXFrequency_t step; /**< Stepping frequency in this band */ + DRXBandwidth_t bandwidth; /**< Bandwidth within this frequency band */ + u16_t chNumber; /**< First channel number in this band, or first + index in chNames */ + char **chNames; /**< Optional list of channel names in this + band */ +} DRXFrequencyPlan_t, *pDRXFrequencyPlan_t; + +/*========================================*/ + +/** +* \struct DRXFrequencyPlanInfo_t +* Array element of a list of frequency plans. +* +* Used by frequency_plan.h +*/ +typedef struct{ + pDRXFrequencyPlan_t freqPlan; + int freqPlanSize; + char *freqPlanName; +}DRXFrequencyPlanInfo_t, *pDRXFrequencyPlanInfo_t; + +/*========================================*/ + +/** +* /struct DRXScanDataQam_t +* QAM specific scanning variables +*/ +typedef struct { + pu32_t symbolrate; /**< list of symbolrates to scan */ + u16_t symbolrateSize; /**< size of symbolrate array */ + pDRXConstellation_t constellation; /**< list of constellations */ + u16_t constellationSize; /**< size of constellation array */ + u16_t ifAgcThreshold; /**< thresholf for IF-AGC based + scanning filter */ +} DRXScanDataQam_t, *pDRXScanDataQam_t; + +/*========================================*/ + +/** +* /struct DRXScanDataAtv_t +* ATV specific scanning variables +*/ +typedef struct { + s16_t svrThreshold; /**< threshold of Sound/Video ratio in 0.1dB steps */ +} DRXScanDataAtv_t, *pDRXScanDataAtv_t; + +/*========================================*/ + +/** +* \struct DRXScanParam_t +* Parameters for channel scan. +* +* Used by DRX_CTRL_SCAN_INIT. +*/ +typedef struct { + pDRXFrequencyPlan_t frequencyPlan; /**< Frequency plan (array)*/ + u16_t frequencyPlanSize; /**< Number of bands */ + u32_t numTries; /**< Max channels tried */ + DRXFrequency_t skip; /**< Minimum frequency step to take + after a channel is found */ + void *extParams; /**< Standard specific params */ +} DRXScanParam_t, *pDRXScanParam_t; + +/*========================================*/ + +/** +* \brief Scan commands. +* Used by scanning algorithms. +*/ +typedef enum { + DRX_SCAN_COMMAND_INIT = 0, /**< Initialize scanning */ + DRX_SCAN_COMMAND_NEXT, /**< Next scan */ + DRX_SCAN_COMMAND_STOP /**< Stop scanning */ +}DRXScanCommand_t, *pDRXScanCommand_t; + +/*========================================*/ + +/** +* \brief Inner scan function prototype. +*/ +typedef DRXStatus_t (*DRXScanFunc_t) (void* scanContext, + DRXScanCommand_t scanCommand, + pDRXChannel_t scanChannel, + pBool_t getNextChannel ); + +/*========================================*/ + +/** +* \struct DRXTPSInfo_t +* TPS information, DVB-T specific. +* +* Used by DRX_CTRL_TPS_INFO. +*/ +typedef struct { + DRXFftmode_t fftmode; /**< Fft mode */ + DRXGuard_t guard; /**< Guard interval */ + DRXConstellation_t constellation; /**< Constellation */ + DRXHierarchy_t hierarchy; /**< Hierarchy */ + DRXCoderate_t highCoderate; /**< High code rate */ + DRXCoderate_t lowCoderate; /**< Low cod rate */ + DRXTPSFrame_t frame; /**< Tps frame */ + u8_t length; /**< Length */ + u16_t cellId; /**< Cell id */ +}DRXTPSInfo_t, *pDRXTPSInfo_t; + +/*========================================*/ + +/** +* \brief Power mode of device. +* +* Used by DRX_CTRL_SET_POWER_MODE. +*/ +typedef enum { + DRX_POWER_UP = 0, /**< Generic , Power Up Mode */ + DRX_POWER_MODE_1, /**< Device specific , Power Up Mode */ + DRX_POWER_MODE_2, /**< Device specific , Power Up Mode */ + DRX_POWER_MODE_3, /**< Device specific , Power Up Mode */ + DRX_POWER_MODE_4, /**< Device specific , Power Up Mode */ + DRX_POWER_MODE_5, /**< Device specific , Power Up Mode */ + DRX_POWER_MODE_6, /**< Device specific , Power Up Mode */ + DRX_POWER_MODE_7, /**< Device specific , Power Up Mode */ + DRX_POWER_MODE_8, /**< Device specific , Power Up Mode */ + + DRX_POWER_MODE_9, /**< Device specific , Power Down Mode */ + DRX_POWER_MODE_10, /**< Device specific , Power Down Mode */ + DRX_POWER_MODE_11, /**< Device specific , Power Down Mode */ + DRX_POWER_MODE_12, /**< Device specific , Power Down Mode */ + DRX_POWER_MODE_13, /**< Device specific , Power Down Mode */ + DRX_POWER_MODE_14, /**< Device specific , Power Down Mode */ + DRX_POWER_MODE_15, /**< Device specific , Power Down Mode */ + DRX_POWER_MODE_16, /**< Device specific , Power Down Mode */ + DRX_POWER_DOWN = 255 /**< Generic , Power Down Mode */ +}DRXPowerMode_t, *pDRXPowerMode_t; + +/*========================================*/ + +/** +* \enum DRXModule_t +* \brief Software module identification. +* +* Used by DRX_CTRL_VERSION. +*/ +typedef enum { + DRX_MODULE_DEVICE, + DRX_MODULE_MICROCODE, + DRX_MODULE_DRIVERCORE, + DRX_MODULE_DEVICEDRIVER, + DRX_MODULE_DAP, + DRX_MODULE_BSP_I2C, + DRX_MODULE_BSP_TUNER, + DRX_MODULE_BSP_HOST, + DRX_MODULE_UNKNOWN +} DRXModule_t, *pDRXModule_t; + + +/** +* \enum DRXVersion_t +* \brief Version information of one software module. +* +* Used by DRX_CTRL_VERSION. +*/ +typedef struct { + DRXModule_t moduleType; /**< Type identifier of the module */ + char *moduleName; /**< Name or description of module */ + u16_t vMajor; /**< Major version number */ + u16_t vMinor; /**< Minor version number */ + u16_t vPatch; /**< Patch version number */ + char *vString; /**< Version as text string */ +} DRXVersion_t, *pDRXVersion_t; + +/** +* \enum DRXVersionList_t +* \brief List element of NULL terminated, linked list for version information. +* +* Used by DRX_CTRL_VERSION. +*/ +typedef struct DRXVersionList_s { + pDRXVersion_t version; /**< Version information */ + struct DRXVersionList_s *next; /**< Next list element */ +} DRXVersionList_t, *pDRXVersionList_t; + +/*========================================*/ + +/** +* \brief Parameters needed to confiugure a UIO. +* +* Used by DRX_CTRL_UIO_CFG. +*/ +typedef struct { + DRXUIO_t uio; /**< UIO identifier */ + DRXUIOMode_t mode; /**< UIO operational mode */ +} DRXUIOCfg_t, *pDRXUIOCfg_t; + +/*========================================*/ + +/** +* \brief Parameters needed to read from or write to a UIO. +* +* Used by DRX_CTRL_UIO_READ and DRX_CTRL_UIO_WRITE. +*/ +typedef struct { + DRXUIO_t uio; /**< UIO identifier */ + Bool_t value; /**< UIO value (TRUE=1, FALSE=0) */ +} DRXUIOData_t, *pDRXUIOData_t; + +/*========================================*/ + +/** +* \brief Parameters needed to configure OOB. +* +* Used by DRX_CTRL_SET_OOB. +*/ +typedef struct { + DRXFrequency_t frequency; /**< Frequency in kHz */ + DRXOOBDownstreamStandard_t standard; /**< OOB standard */ + Bool_t spectrumInverted; /**< If TRUE, then spectrum + is inverted */ +} DRXOOB_t, *pDRXOOB_t; + + +/*========================================*/ + +/** +* \brief Metrics from OOB. +* +* Used by DRX_CTRL_GET_OOB. +*/ +typedef struct { + DRXFrequency_t frequency; /**< Frequency in Khz */ + DRXLockStatus_t lock; /**< Lock status */ + u32_t mer; /**< MER */ + s32_t symbolRateOffset; /**< Symbolrate offset in ppm */ +} DRXOOBStatus_t, *pDRXOOBStatus_t; + + +/*========================================*/ + +/** +* \brief Device dependent configuration data. +* +* Used by DRX_CTRL_SET_CFG and DRX_CTRL_GET_CFG. +* A sort of nested DRX_Ctrl() functionality for device specific controls. +*/ +typedef struct { + DRXCfgType_t cfgType ; /**< Function identifier */ + void* cfgData ; /**< Function data */ +} DRXCfg_t, *pDRXCfg_t; + +/*========================================*/ + +/** +* /struct DRXMpegStartWidth_t +* MStart width [nr MCLK cycles] for serial MPEG output. +*/ + +typedef enum { + DRX_MPEG_STR_WIDTH_1, + DRX_MPEG_STR_WIDTH_8 +} DRXMPEGStrWidth_t, *pDRXMPEGStrWidth_t; + + +/* CTRL CFG MPEG ouput */ +/** +* \struct DRXCfgMPEGOutput_t +* \brief Configuartion parameters for MPEG output control. +* +* Used by DRX_CFG_MPEG_OUTPUT, in combination with DRX_CTRL_SET_CFG and +* DRX_CTRL_GET_CFG. +*/ + +typedef struct { + Bool_t enableMPEGOutput; /**< If TRUE, enable MPEG output */ + Bool_t insertRSByte; /**< If TRUE, insert RS byte */ + Bool_t enableParallel; /**< If TRUE, parallel out otherwise + serial */ + Bool_t invertDATA; /**< If TRUE, invert DATA signals */ + Bool_t invertERR; /**< If TRUE, invert ERR signal */ + Bool_t invertSTR; /**< If TRUE, invert STR signals */ + Bool_t invertVAL; /**< If TRUE, invert VAL signals */ + Bool_t invertCLK; /**< If TRUE, invert CLK signals */ + Bool_t staticCLK; /**< If TRUE, static MPEG clockrate + will be used, otherwise clockrate + will adapt to the bitrate of the + TS */ + u32_t bitrate; /**< Maximum bitrate in b/s in case + static clockrate is selected */ + DRXMPEGStrWidth_t widthSTR; /**< MPEG start width */ +} DRXCfgMPEGOutput_t, *pDRXCfgMPEGOutput_t; + +/* CTRL CFG SMA */ +/** +* /struct DRXCfgSMAIO_t +* smart antenna i/o. +*/ +typedef enum DRXCfgSMAIO_t { + DRX_SMA_OUTPUT = 0, + DRX_SMA_INPUT +} DRXCfgSMAIO_t, *pDRXCfgSMAIO_t; + +/** +* /struct DRXCfgSMA_t +* Set smart antenna. +*/ +typedef struct { + DRXCfgSMAIO_t io; + u16_t ctrlData; + Bool_t smartAntInverted; +} DRXCfgSMA_t, *pDRXCfgSMA_t; + +/*========================================*/ + +/** +* \struct DRXI2CData_t +* \brief Data for I2C via 2nd or 3rd or etc I2C port. +* +* Used by DRX_CTRL_I2C_READWRITE. +* If portNr is equal to primairy portNr BSPI2C will be used. +* +*/ +typedef struct { + u16_t portNr; /**< I2C port number */ + pI2CDeviceAddr_t wDevAddr; /**< Write device address */ + u16_t wCount; /**< Size of write data in bytes */ + pu8_t wData; /**< Pointer to write data */ + pI2CDeviceAddr_t rDevAddr; /**< Read device address */ + u16_t rCount; /**< Size of data to read in bytes */ + pu8_t rData; /**< Pointer to read buffer */ +} DRXI2CData_t, *pDRXI2CData_t; + +/*========================================*/ + +/** +* \enum DRXAudStandard_t +* \brief Audio standard identifier. +* +* Used by DRX_CTRL_SET_AUD. +*/ +typedef enum { + DRX_AUD_STANDARD_BTSC, /**< set BTSC standard (USA) */ + DRX_AUD_STANDARD_A2, /**< set A2-Korea FM Stereo */ + DRX_AUD_STANDARD_EIAJ, /**< set to Japanese FM Stereo */ + DRX_AUD_STANDARD_FM_STEREO, /**< set to FM-Stereo Radio */ + DRX_AUD_STANDARD_M_MONO, /**< for 4.5 MHz mono detected */ + DRX_AUD_STANDARD_D_K_MONO, /**< for 6.5 MHz mono detected */ + DRX_AUD_STANDARD_BG_FM, /**< set BG_FM standard */ + DRX_AUD_STANDARD_D_K1, /**< set D_K1 standard */ + DRX_AUD_STANDARD_D_K2, /**< set D_K2 standard */ + DRX_AUD_STANDARD_D_K3, /**< set D_K3 standard */ + DRX_AUD_STANDARD_BG_NICAM_FM, /**< set BG_NICAM_FM standard */ + DRX_AUD_STANDARD_L_NICAM_AM, /**< set L_NICAM_AM standard */ + DRX_AUD_STANDARD_I_NICAM_FM, /**< set I_NICAM_FM standard */ + DRX_AUD_STANDARD_D_K_NICAM_FM, /**< set D_K_NICAM_FM standard */ + DRX_AUD_STANDARD_NOT_READY, /**< used to detect audio standard */ + DRX_AUD_STANDARD_AUTO = DRX_AUTO, /**< Automatic Standard Detection */ + DRX_AUD_STANDARD_UNKNOWN = DRX_UNKNOWN /**< used as auto and for readback */ +} DRXAudStandard_t, *pDRXAudStandard_t; + +/* CTRL_AUD_GET_STATUS - DRXAudStatus_t */ +/** +* \enum DRXAudNICAMStatus_t +* \brief Status of NICAM carrier. +*/ +typedef enum { + DRX_AUD_NICAM_DETECTED = 0, /**< NICAM carrier detected */ + DRX_AUD_NICAM_NOT_DETECTED, /**< NICAM carrier not detected */ + DRX_AUD_NICAM_BAD /**< NICAM carrier bad quality */ +} DRXAudNICAMStatus_t, *pDRXAudNICAMStatus_t; + +/** +* \struct DRXAudStatus_t +* \brief Audio status characteristics. +*/ +typedef struct { + Bool_t stereo; /**< stereo detection */ + Bool_t carrierA; /**< carrier A detected */ + Bool_t carrierB; /**< carrier B detected */ + Bool_t sap; /**< sap / bilingual detection */ + Bool_t rds; /**< RDS data array present */ + DRXAudNICAMStatus_t nicamStatus; /**< status of NICAM carrier */ + s8_t fmIdent; /**< FM Identification value */ +} DRXAudStatus_t, *pDRXAudStatus_t; + +/* CTRL_AUD_READ_RDS - DRXRDSdata_t */ + +/** +* \struct DRXRDSdata_t +* \brief Raw RDS data array. +*/ +typedef struct { + Bool_t valid; /**< RDS data validation */ + u16_t data[18]; /**< data from one RDS data array */ +} DRXCfgAudRDS_t, *pDRXCfgAudRDS_t; + +/* DRX_CFG_AUD_VOLUME - DRXCfgAudVolume_t - set/get */ +/** +* \enum DRXAudAVCDecayTime_t +* \brief Automatic volume control configuration. +*/ +typedef enum { + DRX_AUD_AVC_OFF, /**< Automatic volume control off */ + DRX_AUD_AVC_DECAYTIME_8S, /**< level volume in 8 seconds */ + DRX_AUD_AVC_DECAYTIME_4S, /**< level volume in 4 seconds */ + DRX_AUD_AVC_DECAYTIME_2S, /**< level volume in 2 seconds */ + DRX_AUD_AVC_DECAYTIME_20MS /**< level volume in 20 millisec */ +} DRXAudAVCMode_t, *pDRXAudAVCMode_t; + +/** +* /enum DRXAudMaxAVCGain_t +* /brief Automatic volume control max gain in audio baseband. +*/ +typedef enum { + DRX_AUD_AVC_MAX_GAIN_0DB, /**< maximum AVC gain 0 dB */ + DRX_AUD_AVC_MAX_GAIN_6DB, /**< maximum AVC gain 6 dB */ + DRX_AUD_AVC_MAX_GAIN_12DB /**< maximum AVC gain 12 dB */ +} DRXAudAVCMaxGain_t, *pDRXAudAVCMaxGain_t; + +/** +* /enum DRXAudMaxAVCAtten_t +* /brief Automatic volume control max attenuation in audio baseband. +*/ +typedef enum { + DRX_AUD_AVC_MAX_ATTEN_12DB, /**< maximum AVC attenuation 12 dB */ + DRX_AUD_AVC_MAX_ATTEN_18DB, /**< maximum AVC attenuation 18 dB */ + DRX_AUD_AVC_MAX_ATTEN_24DB /**< maximum AVC attenuation 24 dB */ +} DRXAudAVCMaxAtten_t, *pDRXAudAVCMaxAtten_t; +/** +* \struct DRXCfgAudVolume_t +* \brief Audio volume configuration. +*/ +typedef struct { + Bool_t mute; /**< mute overrides volume setting */ + s16_t volume; /**< volume, range -114 to 12 dB */ + DRXAudAVCMode_t avcMode; /**< AVC auto volume control mode */ + u16_t avcRefLevel; /**< AVC reference level */ + DRXAudAVCMaxGain_t avcMaxGain; /**< AVC max gain selection */ + DRXAudAVCMaxAtten_t avcMaxAtten; /**< AVC max attenuation selection */ + s16_t strengthLeft; /**< quasi-peak, left speaker */ + s16_t strengthRight; /**< quasi-peak, right speaker */ +} DRXCfgAudVolume_t, *pDRXCfgAudVolume_t; + +/* DRX_CFG_I2S_OUTPUT - DRXCfgI2SOutput_t - set/get */ +/** +* \enum DRXI2SMode_t +* \brief I2S output mode. +*/ +typedef enum { + DRX_I2S_MODE_MASTER, /**< I2S is in master mode */ + DRX_I2S_MODE_SLAVE /**< I2S is in slave mode */ +} DRXI2SMode_t, *pDRXI2SMode_t; + +/** +* \enum DRXI2SWordLength_t +* \brief Width of I2S data. +*/ +typedef enum { + DRX_I2S_WORDLENGTH_32 = 0, /**< I2S data is 32 bit wide */ + DRX_I2S_WORDLENGTH_16 = 1 /**< I2S data is 16 bit wide */ +} DRXI2SWordLength_t, *pDRXI2SWordLength_t; + +/** +* \enum DRXI2SFormat_t +* \brief Data wordstrobe alignment for I2S. +*/ +typedef enum { + DRX_I2S_FORMAT_WS_WITH_DATA, /**< I2S data and wordstrobe are aligned */ + DRX_I2S_FORMAT_WS_ADVANCED /**< I2S data one cycle after wordstrobe */ +} DRXI2SFormat_t, *pDRXI2SFormat_t; + +/** +* \enum DRXI2SPolarity_t +* \brief Polarity of I2S data. +*/ +typedef enum { + DRX_I2S_POLARITY_RIGHT, /**< wordstrobe - right high, left low */ + DRX_I2S_POLARITY_LEFT /**< wordstrobe - right low, left high */ +} DRXI2SPolarity_t, *pDRXI2SPolarity_t; + + + +/** +* \struct DRXCfgI2SOutput_t +* \brief I2S output configuration. +*/ +typedef struct { + Bool_t outputEnable; /**< I2S output enable */ + u32_t frequency; /**< range from 8000-48000 Hz */ + DRXI2SMode_t mode; /**< I2S mode, master or slave */ + DRXI2SWordLength_t wordLength; /**< I2S wordlength, 16 or 32 bits */ + DRXI2SPolarity_t polarity; /**< I2S wordstrobe polarity */ + DRXI2SFormat_t format; /**< I2S wordstrobe delay to data */ +} DRXCfgI2SOutput_t, *pDRXCfgI2SOutput_t; + + +/* ------------------------------expert interface-----------------------------*/ +/** +* /enum DRXAudFMDeemphasis_t +* setting for FM-Deemphasis in audio demodulator. +* +*/ +typedef enum { + DRX_AUD_FM_DEEMPH_50US, + DRX_AUD_FM_DEEMPH_75US, + DRX_AUD_FM_DEEMPH_OFF +} DRXAudFMDeemphasis_t, *pDRXAudFMDeemphasis_t; + +/** +* /enum DRXAudDeviation_t +* setting for deviation mode in audio demodulator. +* +*/ +typedef enum { + DRX_AUD_DEVIATION_NORMAL, + DRX_AUD_DEVIATION_HIGH +} DRXCfgAudDeviation_t, *pDRXCfgAudDeviation_t; + +/** +* /enum DRXNoCarrierOption_t +* setting for carrier, mute/noise. +* +*/ +typedef enum { + DRX_NO_CARRIER_MUTE, + DRX_NO_CARRIER_NOISE +} DRXNoCarrierOption_t, *pDRXNoCarrierOption_t; + + +/** +* \enum DRXAudAutoSound_t +* \brief Automatic Sound +*/ +typedef enum { + DRX_AUD_AUTO_SOUND_OFF = 0, + DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON, + DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_OFF +} DRXCfgAudAutoSound_t, *pDRXCfgAudAutoSound_t; + +/** +* \enum DRXAudASSThres_t +* \brief Automatic Sound Select Thresholds +*/ +typedef struct { + u16_t a2; /* A2 Threshold for ASS configuration */ + u16_t btsc; /* BTSC Threshold for ASS configuration */ + u16_t nicam; /* Nicam Threshold for ASS configuration */ +} DRXCfgAudASSThres_t, *pDRXCfgAudASSThres_t; + +/** +* \struct DRXAudCarrier_t +* \brief Carrier detection related parameters +*/ +typedef struct { + u16_t thres; /* carrier detetcion threshold for primary carrier (A) */ + DRXNoCarrierOption_t opt; /* Mute or noise at no carrier detection (A) */ + DRXFrequency_t shift; /* DC level of incoming signal (A) */ + DRXFrequency_t dco; /* frequency adjustment (A) */ +} DRXAudCarrier_t, *pDRXCfgAudCarrier_t; + +/** +* \struct DRXCfgAudCarriers_t +* \brief combining carrier A & B to one struct +*/ +typedef struct { + DRXAudCarrier_t a; + DRXAudCarrier_t b; +} DRXCfgAudCarriers_t, *pDRXCfgAudCarriers_t; + +/** +* /enum DRXAudI2SSrc_t +* Selection of audio source +*/ +typedef enum { + DRX_AUD_SRC_MONO, + DRX_AUD_SRC_STEREO_OR_AB, + DRX_AUD_SRC_STEREO_OR_A, + DRX_AUD_SRC_STEREO_OR_B +} DRXAudI2SSrc_t, *pDRXAudI2SSrc_t; + + +/** +* \enum DRXAudI2SMatrix_t +* \brief Used for selecting I2S output. +*/ +typedef enum { + DRX_AUD_I2S_MATRIX_A_MONO, /**< A sound only, stereo or mono */ + DRX_AUD_I2S_MATRIX_B_MONO, /**< B sound only, stereo or mono */ + DRX_AUD_I2S_MATRIX_STEREO, /**< A+B sound, transparant */ + DRX_AUD_I2S_MATRIX_MONO /**< A+B mixed to mono sum, (L+R)/2 */ +} DRXAudI2SMatrix_t, *pDRXAudI2SMatrix_t; + + +/** +* /enum DRXAudFMMatrix_t +* setting for FM-Matrix in audio demodulator. +* +*/ +typedef enum { + DRX_AUD_FM_MATRIX_NO_MATRIX, + DRX_AUD_FM_MATRIX_GERMAN, + DRX_AUD_FM_MATRIX_KOREAN, + DRX_AUD_FM_MATRIX_SOUND_A, + DRX_AUD_FM_MATRIX_SOUND_B +} DRXAudFMMatrix_t, *pDRXAudFMMatrix_t; + +/** +* \struct DRXAudMatrices_t +* \brief Mixer settings +*/ +typedef struct { + DRXAudI2SSrc_t sourceI2S; + DRXAudI2SMatrix_t matrixI2S; + DRXAudFMMatrix_t matrixFm; +} DRXCfgAudMixer_t, *pDRXCfgAudMixer_t; + +/** +* \enum DRXI2SVidSync_t +* \brief Audio/video synchronization, interacts with I2S mode. +* AUTO_1 and AUTO_2 are for automatic video standard detection with preference +* for NTSC or Monochrome, because the frequencies are too close (59.94 & 60 Hz) +*/ +typedef enum { + DRX_AUD_AVSYNC_OFF, /**< audio/video synchronization is off */ + DRX_AUD_AVSYNC_NTSC, /**< it is an NTSC system */ + DRX_AUD_AVSYNC_MONOCHROME, /**< it is a MONOCHROME system */ + DRX_AUD_AVSYNC_PAL_SECAM /**< it is a PAL/SECAM system */ +} DRXCfgAudAVSync_t, *pDRXCfgAudAVSync_t; + +/** +* \struct DRXCfgAudPrescale_t +* \brief Prescalers +*/ +typedef struct { + u16_t fmDeviation; + s16_t nicamGain; +} DRXCfgAudPrescale_t, *pDRXCfgAudPrescale_t; + +/** +* \struct DRXAudBeep_t +* \brief Beep +*/ +typedef struct { + s16_t volume; /* dB */ + u16_t frequency; /* Hz */ + Bool_t mute; +} DRXAudBeep_t, *pDRXAudBeep_t; + + +/** +* \enum DRXAudBtscDetect_t +* \brief BTSC detetcion mode +*/ +typedef enum { + DRX_BTSC_STEREO, + DRX_BTSC_MONO_AND_SAP +} DRXAudBtscDetect_t, *pDRXAudBtscDetect_t; + +/** +* \struct DRXAudData_t +* \brief Audio data structure +*/ +typedef struct +{ + /* audio storage */ + Bool_t audioIsActive; + DRXAudStandard_t audioStandard; + DRXCfgI2SOutput_t i2sdata; + DRXCfgAudVolume_t volume; + DRXCfgAudAutoSound_t autoSound; + DRXCfgAudASSThres_t assThresholds; + DRXCfgAudCarriers_t carriers; + DRXCfgAudMixer_t mixer; + DRXCfgAudDeviation_t deviation; + DRXCfgAudAVSync_t avSync; + DRXCfgAudPrescale_t prescale; + DRXAudFMDeemphasis_t deemph; + DRXAudBtscDetect_t btscDetect; + /* rds */ + u16_t rdsDataCounter; + Bool_t rdsDataPresent; +} DRXAudData_t, *pDRXAudData_t; + + +/** +* \enum DRXQamLockRange_t +* \brief QAM lock range mode +*/ +typedef enum +{ + DRX_QAM_LOCKRANGE_NORMAL, + DRX_QAM_LOCKRANGE_EXTENDED +}DRXQamLockRange_t, *pDRXQamLockRange_t; + +/*============================================================================*/ +/*============================================================================*/ +/*== Data access structures ==================================================*/ +/*============================================================================*/ +/*============================================================================*/ + +/* Address on device */ +typedef u32_t DRXaddr_t, *pDRXaddr_t; + +/* Protocol specific flags */ +typedef u32_t DRXflags_t, *pDRXflags_t; + +/* Write block of data to device */ +typedef DRXStatus_t (*DRXWriteBlockFunc_t) ( + pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register/memory */ + u16_t datasize, /* size of data in bytes */ + pu8_t data, /* data to send */ + DRXflags_t flags); + +/* Read block of data from device */ +typedef DRXStatus_t (*DRXReadBlockFunc_t) ( + pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register/memory */ + u16_t datasize, /* size of data in bytes */ + pu8_t data, /* receive buffer */ + DRXflags_t flags); + +/* Write 8-bits value to device */ +typedef DRXStatus_t (*DRXWriteReg8Func_t) ( + pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register/memory */ + u8_t data, /* data to send */ + DRXflags_t flags); + +/* Read 8-bits value to device */ +typedef DRXStatus_t (*DRXReadReg8Func_t) ( + pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register/memory */ + pu8_t data, /* receive buffer */ + DRXflags_t flags); + +/* Read modify write 8-bits value to device */ +typedef DRXStatus_t (*DRXReadModifyWriteReg8Func_t) ( + pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t waddr, /* write address of register */ + DRXaddr_t raddr, /* read address of register */ + u8_t wdata, /* data to write */ + pu8_t rdata); /* data to read */ + +/* Write 16-bits value to device */ +typedef DRXStatus_t (*DRXWriteReg16Func_t) ( + pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register/memory */ + u16_t data, /* data to send */ + DRXflags_t flags); + +/* Read 16-bits value to device */ +typedef DRXStatus_t (*DRXReadReg16Func_t) ( + pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register/memory */ + pu16_t data, /* receive buffer */ + DRXflags_t flags); + +/* Read modify write 16-bits value to device */ +typedef DRXStatus_t (*DRXReadModifyWriteReg16Func_t) ( + pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t waddr, /* write address of register */ + DRXaddr_t raddr, /* read address of register */ + u16_t wdata, /* data to write */ + pu16_t rdata); /* data to read */ + +/* Write 32-bits value to device */ +typedef DRXStatus_t (*DRXWriteReg32Func_t) ( + pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register/memory */ + u32_t data, /* data to send */ + DRXflags_t flags); + +/* Read 32-bits value to device */ +typedef DRXStatus_t (*DRXReadReg32Func_t) ( + pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register/memory */ + pu32_t data, /* receive buffer */ + DRXflags_t flags); + +/* Read modify write 32-bits value to device */ +typedef DRXStatus_t (*DRXReadModifyWriteReg32Func_t) ( + pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t waddr, /* write address of register */ + DRXaddr_t raddr, /* read address of register */ + u32_t wdata, /* data to write */ + pu32_t rdata); /* data to read */ + +/** +* \struct DRXAccessFunc_t +* \brief Interface to an access protocol. +*/ +typedef struct { + pDRXVersion_t protocolVersion; + DRXWriteBlockFunc_t writeBlockFunc; + DRXReadBlockFunc_t readBlockFunc; + DRXWriteReg8Func_t writeReg8Func; + DRXReadReg8Func_t readReg8Func; + DRXReadModifyWriteReg8Func_t readModifyWriteReg8Func; + DRXWriteReg16Func_t writeReg16Func; + DRXReadReg16Func_t readReg16Func; + DRXReadModifyWriteReg16Func_t readModifyWriteReg16Func; + DRXWriteReg32Func_t writeReg32Func; + DRXReadReg32Func_t readReg32Func; + DRXReadModifyWriteReg32Func_t readModifyWriteReg32Func; +} DRXAccessFunc_t, *pDRXAccessFunc_t; + +/* Register address and data for register dump function */ +typedef struct { + + DRXaddr_t address; + u32_t data; + +} DRXRegDump_t, *pDRXRegDump_t ; + +/*============================================================================*/ +/*============================================================================*/ +/*== Demod instance data structures ==========================================*/ +/*============================================================================*/ +/*============================================================================*/ + +/** +* \struct DRXCommonAttr_t +* \brief Set of common attributes, shared by all DRX devices. +*/ +typedef struct { + /* Microcode (firmware) attributes */ + pu8_t microcode; /**< Pointer to microcode image. */ + u16_t microcodeSize; /**< Size of microcode image in bytes. */ + Bool_t verifyMicrocode; /**< Use microcode verify or not. */ + DRXMcVersionRec_t mcversion; /**< Version record of microcode from file */ + + /* Clocks and tuner attributes */ + DRXFrequency_t intermediateFreq; /**< IF,if tuner instance not used. (kHz)*/ + DRXFrequency_t sysClockFreq; /**< Systemclock frequency. (kHz) */ + DRXFrequency_t oscClockFreq; /**< Oscillator clock frequency. (kHz) */ + s16_t oscClockDeviation; /**< Oscillator clock deviation. (ppm) */ + Bool_t mirrorFreqSpect; /**< Mirror IF frequency spectrum or not.*/ + + /* Initial MPEG output attributes */ + DRXCfgMPEGOutput_t mpegCfg; /**< MPEG configuration */ + + Bool_t isOpened; /**< if TRUE instance is already opened. */ + + /* Channel scan */ + pDRXScanParam_t scanParam; /**< scan parameters */ + u16_t scanFreqPlanIndex; /**< next index in freq plan */ + DRXFrequency_t scanNextFrequency; /**< next freq to scan */ + Bool_t scanReady; /**< scan ready flag */ + u32_t scanMaxChannels; /**< number of channels in freqplan */ + u32_t scanChannelsScanned; /**< number of channels scanned */ + /* Channel scan - inner loop: demod related */ + DRXScanFunc_t scanFunction; /**< function to check channel */ + /* Channel scan - inner loop: SYSObj related */ + void* scanContext; /**< Context Pointer of SYSObj */ + /* Channel scan - parameters for default DTV scan function in core driver */ + u16_t scanDemodLockTimeout; /**< millisecs to wait for lock */ + DRXLockStatus_t scanDesiredLock; /**< lock requirement for channel found */ + /* scanActive can be used by SetChannel to decide how to program the tuner, + fast or slow (but stable). Usually fast during scan. */ + Bool_t scanActive; /**< TRUE when scan routines are active */ + + /* Power management */ + DRXPowerMode_t currentPowerMode; /**< current power management mode */ + + /* Tuner */ + u8_t tunerPortNr; /**< nr of I2C port to wich tuner is */ + DRXFrequency_t tunerMinFreqRF; /**< minimum RF input frequency, in kHz */ + DRXFrequency_t tunerMaxFreqRF; /**< maximum RF input frequency, in kHz */ + Bool_t tunerRfAgcPol; /**< if TRUE invert RF AGC polarity */ + Bool_t tunerIfAgcPol; /**< if TRUE invert IF AGC polarity */ + Bool_t tunerSlowMode; /**< if TRUE invert IF AGC polarity */ + + DRXChannel_t currentChannel; /**< current channel parameters */ + DRXStandard_t currentStandard; /**< current standard selection */ + DRXStandard_t prevStandard; /**< previous standard selection */ + DRXStandard_t diCacheStandard; /**< standard in DI cache if available */ + Bool_t useBootloader; /**< use bootloader in open */ + u32_t capabilities; /**< capabilities flags */ + u32_t productId; /**< product ID inc. metal fix number */ + +} DRXCommonAttr_t, *pDRXCommonAttr_t; + + +/* +* Generic functions for DRX devices. +*/ +typedef struct DRXDemodInstance_s *pDRXDemodInstance_t; + +typedef DRXStatus_t (*DRXOpenFunc_t) (pDRXDemodInstance_t demod); +typedef DRXStatus_t (*DRXCloseFunc_t) (pDRXDemodInstance_t demod); +typedef DRXStatus_t (*DRXCtrlFunc_t) (pDRXDemodInstance_t demod, + DRXCtrlIndex_t ctrl, + void *ctrlData); + +/** +* \struct DRXDemodFunc_t +* \brief A stucture containing all functions of a demodulator. +*/ +typedef struct { + u32_t typeId; /**< Device type identifier. */ + DRXOpenFunc_t openFunc; /**< Pointer to Open() function. */ + DRXCloseFunc_t closeFunc; /**< Pointer to Close() function. */ + DRXCtrlFunc_t ctrlFunc; /**< Pointer to Ctrl() function. */ +} DRXDemodFunc_t, *pDRXDemodFunc_t; + +/** +* \struct DRXDemodInstance_t +* \brief Top structure of demodulator instance. +*/ +typedef struct DRXDemodInstance_s { + /* type specific demodulator data */ + pDRXDemodFunc_t myDemodFunct; /**< demodulator functions */ + pDRXAccessFunc_t myAccessFunct; /**< data access protocol functions */ + pTUNERInstance_t myTuner; /**< tuner instance,if NULL then baseband */ + pI2CDeviceAddr_t myI2CDevAddr; /**< i2c address and device identifier */ + pDRXCommonAttr_t myCommonAttr; /**< common DRX attributes */ + void* myExtAttr; /**< device specific attributes */ + /* generic demodulator data */ +} DRXDemodInstance_t; + + + +/*------------------------------------------------------------------------- +MACROS +Conversion from enum values to human readable form. +-------------------------------------------------------------------------*/ + +/* standard */ + +#define DRX_STR_STANDARD(x) ( \ + ( x == DRX_STANDARD_DVBT ) ? "DVB-T" : \ + ( x == DRX_STANDARD_8VSB ) ? "8VSB" : \ + ( x == DRX_STANDARD_NTSC ) ? "NTSC" : \ + ( x == DRX_STANDARD_PAL_SECAM_BG ) ? "PAL/SECAM B/G" : \ + ( x == DRX_STANDARD_PAL_SECAM_DK ) ? "PAL/SECAM D/K" : \ + ( x == DRX_STANDARD_PAL_SECAM_I ) ? "PAL/SECAM I" : \ + ( x == DRX_STANDARD_PAL_SECAM_L ) ? "PAL/SECAM L" : \ + ( x == DRX_STANDARD_PAL_SECAM_LP ) ? "PAL/SECAM LP" : \ + ( x == DRX_STANDARD_ITU_A ) ? "ITU-A" : \ + ( x == DRX_STANDARD_ITU_B ) ? "ITU-B" : \ + ( x == DRX_STANDARD_ITU_C ) ? "ITU-C" : \ + ( x == DRX_STANDARD_ITU_D ) ? "ITU-D" : \ + ( x == DRX_STANDARD_FM ) ? "FM" : \ + ( x == DRX_STANDARD_DTMB ) ? "DTMB" : \ + ( x == DRX_STANDARD_AUTO ) ? "Auto" : \ + ( x == DRX_STANDARD_UNKNOWN ) ? "Unknown" : \ + "(Invalid)" ) + +/* channel */ + +#define DRX_STR_BANDWIDTH(x) ( \ + ( x == DRX_BANDWIDTH_8MHZ ) ? "8 MHz" : \ + ( x == DRX_BANDWIDTH_7MHZ ) ? "7 MHz" : \ + ( x == DRX_BANDWIDTH_6MHZ ) ? "6 MHz" : \ + ( x == DRX_BANDWIDTH_AUTO ) ? "Auto" : \ + ( x == DRX_BANDWIDTH_UNKNOWN ) ? "Unknown" : \ + "(Invalid)" ) +#define DRX_STR_FFTMODE(x) ( \ + ( x == DRX_FFTMODE_2K ) ? "2k" : \ + ( x == DRX_FFTMODE_4K ) ? "4k" : \ + ( x == DRX_FFTMODE_8K ) ? "8k" : \ + ( x == DRX_FFTMODE_AUTO ) ? "Auto" : \ + ( x == DRX_FFTMODE_UNKNOWN ) ? "Unknown" : \ + "(Invalid)" ) +#define DRX_STR_GUARD(x) ( \ + ( x == DRX_GUARD_1DIV32 ) ? "1/32nd" : \ + ( x == DRX_GUARD_1DIV16 ) ? "1/16th" : \ + ( x == DRX_GUARD_1DIV8 ) ? "1/8th" : \ + ( x == DRX_GUARD_1DIV4 ) ? "1/4th" : \ + ( x == DRX_GUARD_AUTO ) ? "Auto" : \ + ( x == DRX_GUARD_UNKNOWN ) ? "Unknown" : \ + "(Invalid)" ) +#define DRX_STR_CONSTELLATION(x) ( \ + ( x == DRX_CONSTELLATION_BPSK ) ? "BPSK" : \ + ( x == DRX_CONSTELLATION_QPSK ) ? "QPSK" : \ + ( x == DRX_CONSTELLATION_PSK8 ) ? "PSK8" : \ + ( x == DRX_CONSTELLATION_QAM16 ) ? "QAM16" : \ + ( x == DRX_CONSTELLATION_QAM32 ) ? "QAM32" : \ + ( x == DRX_CONSTELLATION_QAM64 ) ? "QAM64" : \ + ( x == DRX_CONSTELLATION_QAM128 ) ? "QAM128" : \ + ( x == DRX_CONSTELLATION_QAM256 ) ? "QAM256" : \ + ( x == DRX_CONSTELLATION_QAM512 ) ? "QAM512" : \ + ( x == DRX_CONSTELLATION_QAM1024 ) ? "QAM1024" : \ + ( x == DRX_CONSTELLATION_QPSK_NR ) ? "QPSK_NR" : \ + ( x == DRX_CONSTELLATION_AUTO ) ? "Auto" : \ + ( x == DRX_CONSTELLATION_UNKNOWN ) ? "Unknown" : \ + "(Invalid)" ) +#define DRX_STR_CODERATE(x) ( \ + ( x == DRX_CODERATE_1DIV2 ) ? "1/2nd" : \ + ( x == DRX_CODERATE_2DIV3 ) ? "2/3rd" : \ + ( x == DRX_CODERATE_3DIV4 ) ? "3/4th" : \ + ( x == DRX_CODERATE_5DIV6 ) ? "5/6th" : \ + ( x == DRX_CODERATE_7DIV8 ) ? "7/8th" : \ + ( x == DRX_CODERATE_AUTO ) ? "Auto" : \ + ( x == DRX_CODERATE_UNKNOWN ) ? "Unknown" : \ + "(Invalid)" ) +#define DRX_STR_HIERARCHY(x) ( \ + ( x == DRX_HIERARCHY_NONE ) ? "None" : \ + ( x == DRX_HIERARCHY_ALPHA1 ) ? "Alpha=1" : \ + ( x == DRX_HIERARCHY_ALPHA2 ) ? "Alpha=2" : \ + ( x == DRX_HIERARCHY_ALPHA4 ) ? "Alpha=4" : \ + ( x == DRX_HIERARCHY_AUTO ) ? "Auto" : \ + ( x == DRX_HIERARCHY_UNKNOWN ) ? "Unknown" : \ + "(Invalid)" ) +#define DRX_STR_PRIORITY(x) ( \ + ( x == DRX_PRIORITY_LOW ) ? "Low" : \ + ( x == DRX_PRIORITY_HIGH ) ? "High" : \ + ( x == DRX_PRIORITY_UNKNOWN ) ? "Unknown" : \ + "(Invalid)" ) +#define DRX_STR_MIRROR(x) ( \ + ( x == DRX_MIRROR_NO ) ? "Normal" : \ + ( x == DRX_MIRROR_YES ) ? "Mirrored" : \ + ( x == DRX_MIRROR_AUTO ) ? "Auto" : \ + ( x == DRX_MIRROR_UNKNOWN ) ? "Unknown" : \ + "(Invalid)" ) +#define DRX_STR_CLASSIFICATION(x) ( \ + ( x == DRX_CLASSIFICATION_GAUSS ) ? "Gaussion" : \ + ( x == DRX_CLASSIFICATION_HVY_GAUSS ) ? "Heavy Gaussion" : \ + ( x == DRX_CLASSIFICATION_COCHANNEL ) ? "Co-channel" : \ + ( x == DRX_CLASSIFICATION_STATIC ) ? "Static echo" : \ + ( x == DRX_CLASSIFICATION_MOVING ) ? "Moving echo" : \ + ( x == DRX_CLASSIFICATION_ZERODB ) ? "Zero dB echo" : \ + ( x == DRX_CLASSIFICATION_UNKNOWN ) ? "Unknown" : \ + ( x == DRX_CLASSIFICATION_AUTO ) ? "Auto" : \ + "(Invalid)" ) + +#define DRX_STR_INTERLEAVEMODE(x) ( \ + ( x == DRX_INTERLEAVEMODE_I128_J1 ) ? "I128_J1" : \ + ( x == DRX_INTERLEAVEMODE_I128_J1_V2 ) ? "I128_J1_V2" : \ + ( x == DRX_INTERLEAVEMODE_I128_J2 ) ? "I128_J2" : \ + ( x == DRX_INTERLEAVEMODE_I64_J2 ) ? "I64_J2" : \ + ( x == DRX_INTERLEAVEMODE_I128_J3 ) ? "I128_J3" : \ + ( x == DRX_INTERLEAVEMODE_I32_J4 ) ? "I32_J4" : \ + ( x == DRX_INTERLEAVEMODE_I128_J4 ) ? "I128_J4" : \ + ( x == DRX_INTERLEAVEMODE_I16_J8 ) ? "I16_J8" : \ + ( x == DRX_INTERLEAVEMODE_I128_J5 ) ? "I128_J5" : \ + ( x == DRX_INTERLEAVEMODE_I8_J16 ) ? "I8_J16" : \ + ( x == DRX_INTERLEAVEMODE_I128_J6 ) ? "I128_J6" : \ + ( x == DRX_INTERLEAVEMODE_RESERVED_11 ) ? "Reserved 11" : \ + ( x == DRX_INTERLEAVEMODE_I128_J7 ) ? "I128_J7" : \ + ( x == DRX_INTERLEAVEMODE_RESERVED_13 ) ? "Reserved 13" : \ + ( x == DRX_INTERLEAVEMODE_I128_J8 ) ? "I128_J8" : \ + ( x == DRX_INTERLEAVEMODE_RESERVED_15 ) ? "Reserved 15" : \ + ( x == DRX_INTERLEAVEMODE_I12_J17 ) ? "I12_J17" : \ + ( x == DRX_INTERLEAVEMODE_I5_J4 ) ? "I5_J4" : \ + ( x == DRX_INTERLEAVEMODE_B52_M240 ) ? "B52_M240" : \ + ( x == DRX_INTERLEAVEMODE_B52_M720 ) ? "B52_M720" : \ + ( x == DRX_INTERLEAVEMODE_B52_M48 ) ? "B52_M48" : \ + ( x == DRX_INTERLEAVEMODE_B52_M0 ) ? "B52_M0" : \ + ( x == DRX_INTERLEAVEMODE_UNKNOWN ) ? "Unknown" : \ + ( x == DRX_INTERLEAVEMODE_AUTO ) ? "Auto" : \ + "(Invalid)" ) + +#define DRX_STR_LDPC(x) ( \ + ( x == DRX_LDPC_0_4 ) ? "0.4" : \ + ( x == DRX_LDPC_0_6 ) ? "0.6" : \ + ( x == DRX_LDPC_0_8 ) ? "0.8" : \ + ( x == DRX_LDPC_AUTO ) ? "Auto" : \ + ( x == DRX_LDPC_UNKNOWN ) ? "Unknown" : \ + "(Invalid)" ) + +#define DRX_STR_CARRIER(x) ( \ + ( x == DRX_CARRIER_MULTI ) ? "Multi" : \ + ( x == DRX_CARRIER_SINGLE ) ? "Single" : \ + ( x == DRX_CARRIER_AUTO ) ? "Auto" : \ + ( x == DRX_CARRIER_UNKNOWN ) ? "Unknown" : \ + "(Invalid)" ) + +#define DRX_STR_FRAMEMODE(x) ( \ + ( x == DRX_FRAMEMODE_420 ) ? "420" : \ + ( x == DRX_FRAMEMODE_595 ) ? "595" : \ + ( x == DRX_FRAMEMODE_945 ) ? "945" : \ + ( x == DRX_FRAMEMODE_420_FIXED_PN ) ? "420 with fixed PN" : \ + ( x == DRX_FRAMEMODE_945_FIXED_PN ) ? "945 with fixed PN" : \ + ( x == DRX_FRAMEMODE_AUTO ) ? "Auto" : \ + ( x == DRX_FRAMEMODE_UNKNOWN ) ? "Unknown" : \ + "(Invalid)" ) + +#define DRX_STR_PILOT(x) ( \ + ( x == DRX_PILOT_ON ) ? "On" : \ + ( x == DRX_PILOT_OFF ) ? "Off" : \ + ( x == DRX_PILOT_AUTO ) ? "Auto" : \ + ( x == DRX_PILOT_UNKNOWN ) ? "Unknown" : \ + "(Invalid)" ) +/* TPS */ + +#define DRX_STR_TPS_FRAME(x) ( \ + ( x == DRX_TPS_FRAME1 ) ? "Frame1" : \ + ( x == DRX_TPS_FRAME2 ) ? "Frame2" : \ + ( x == DRX_TPS_FRAME3 ) ? "Frame3" : \ + ( x == DRX_TPS_FRAME4 ) ? "Frame4" : \ + ( x == DRX_TPS_FRAME_UNKNOWN ) ? "Unknown" : \ + "(Invalid)" ) + +/* lock status */ + +#define DRX_STR_LOCKSTATUS(x) ( \ + ( x == DRX_NEVER_LOCK ) ? "Never" : \ + ( x == DRX_NOT_LOCKED ) ? "No" : \ + ( x == DRX_LOCKED ) ? "Locked" : \ + ( x == DRX_LOCK_STATE_1 ) ? "Lock state 1" : \ + ( x == DRX_LOCK_STATE_2 ) ? "Lock state 2" : \ + ( x == DRX_LOCK_STATE_3 ) ? "Lock state 3" : \ + ( x == DRX_LOCK_STATE_4 ) ? "Lock state 4" : \ + ( x == DRX_LOCK_STATE_5 ) ? "Lock state 5" : \ + ( x == DRX_LOCK_STATE_6 ) ? "Lock state 6" : \ + ( x == DRX_LOCK_STATE_7 ) ? "Lock state 7" : \ + ( x == DRX_LOCK_STATE_8 ) ? "Lock state 8" : \ + ( x == DRX_LOCK_STATE_9 ) ? "Lock state 9" : \ + "(Invalid)" ) + +/* version information , modules */ +#define DRX_STR_MODULE(x) ( \ + ( x == DRX_MODULE_DEVICE ) ? "Device" : \ + ( x == DRX_MODULE_MICROCODE ) ? "Microcode" : \ + ( x == DRX_MODULE_DRIVERCORE ) ? "CoreDriver" : \ + ( x == DRX_MODULE_DEVICEDRIVER ) ? "DeviceDriver" : \ + ( x == DRX_MODULE_BSP_I2C ) ? "BSP I2C" : \ + ( x == DRX_MODULE_BSP_TUNER ) ? "BSP Tuner" : \ + ( x == DRX_MODULE_BSP_HOST ) ? "BSP Host" : \ + ( x == DRX_MODULE_DAP ) ? "Data Access Protocol" : \ + ( x == DRX_MODULE_UNKNOWN ) ? "Unknown" : \ + "(Invalid)" ) + +#define DRX_STR_POWER_MODE(x) ( \ + ( x == DRX_POWER_UP ) ? "DRX_POWER_UP " : \ + ( x == DRX_POWER_MODE_1 ) ? "DRX_POWER_MODE_1" : \ + ( x == DRX_POWER_MODE_2 ) ? "DRX_POWER_MODE_2" : \ + ( x == DRX_POWER_MODE_3 ) ? "DRX_POWER_MODE_3" : \ + ( x == DRX_POWER_MODE_4 ) ? "DRX_POWER_MODE_4" : \ + ( x == DRX_POWER_MODE_5 ) ? "DRX_POWER_MODE_5" : \ + ( x == DRX_POWER_MODE_6 ) ? "DRX_POWER_MODE_6" : \ + ( x == DRX_POWER_MODE_7 ) ? "DRX_POWER_MODE_7" : \ + ( x == DRX_POWER_MODE_8 ) ? "DRX_POWER_MODE_8" : \ + ( x == DRX_POWER_MODE_9 ) ? "DRX_POWER_MODE_9" : \ + ( x == DRX_POWER_MODE_10 ) ? "DRX_POWER_MODE_10" : \ + ( x == DRX_POWER_MODE_11 ) ? "DRX_POWER_MODE_11" : \ + ( x == DRX_POWER_MODE_12 ) ? "DRX_POWER_MODE_12" : \ + ( x == DRX_POWER_MODE_13 ) ? "DRX_POWER_MODE_13" : \ + ( x == DRX_POWER_MODE_14 ) ? "DRX_POWER_MODE_14" : \ + ( x == DRX_POWER_MODE_15 ) ? "DRX_POWER_MODE_15" : \ + ( x == DRX_POWER_MODE_16 ) ? "DRX_POWER_MODE_16" : \ + ( x == DRX_POWER_DOWN ) ? "DRX_POWER_DOWN " : \ + "(Invalid)" ) + +#define DRX_STR_OOB_STANDARD(x) ( \ + ( x == DRX_OOB_MODE_A ) ? "ANSI 55-1 " : \ + ( x == DRX_OOB_MODE_B_GRADE_A ) ? "ANSI 55-2 A" : \ + ( x == DRX_OOB_MODE_B_GRADE_B ) ? "ANSI 55-2 B" : \ + "(Invalid)" ) + +#define DRX_STR_AUD_STANDARD(x) ( \ + ( x == DRX_AUD_STANDARD_BTSC ) ? "BTSC" : \ + ( x == DRX_AUD_STANDARD_A2 ) ? "A2" : \ + ( x == DRX_AUD_STANDARD_EIAJ ) ? "EIAJ" : \ + ( x == DRX_AUD_STANDARD_FM_STEREO ) ? "FM Stereo" : \ + ( x == DRX_AUD_STANDARD_AUTO ) ? "Auto" : \ + ( x == DRX_AUD_STANDARD_M_MONO ) ? "M-Standard Mono" : \ + ( x == DRX_AUD_STANDARD_D_K_MONO ) ? "D/K Mono FM" : \ + ( x == DRX_AUD_STANDARD_BG_FM ) ? "B/G-Dual Carrier FM (A2)" : \ + ( x == DRX_AUD_STANDARD_D_K1 ) ? "D/K1-Dual Carrier FM" : \ + ( x == DRX_AUD_STANDARD_D_K2 ) ? "D/K2-Dual Carrier FM" : \ + ( x == DRX_AUD_STANDARD_D_K3 ) ? "D/K3-Dual Carrier FM" : \ + ( x == DRX_AUD_STANDARD_BG_NICAM_FM ) ? "B/G-NICAM-FM" : \ + ( x == DRX_AUD_STANDARD_L_NICAM_AM ) ? "L-NICAM-AM" : \ + ( x == DRX_AUD_STANDARD_I_NICAM_FM ) ? "I-NICAM-FM" : \ + ( x == DRX_AUD_STANDARD_D_K_NICAM_FM ) ? "D/K-NICAM-FM" : \ + ( x == DRX_AUD_STANDARD_UNKNOWN ) ? "Unknown" : \ + "(Invalid)" ) +#define DRX_STR_AUD_STEREO(x) ( \ + ( x == TRUE ) ? "Stereo" : \ + ( x == FALSE ) ? "Mono" : \ + "(Invalid)" ) + +#define DRX_STR_AUD_SAP(x) ( \ + ( x == TRUE ) ? "Present" : \ + ( x == FALSE ) ? "Not present" : \ + "(Invalid)" ) + +#define DRX_STR_AUD_CARRIER(x) ( \ + ( x == TRUE ) ? "Present" : \ + ( x == FALSE ) ? "Not present" : \ + "(Invalid)" ) + +#define DRX_STR_AUD_RDS(x) ( \ + ( x == TRUE ) ? "Available" : \ + ( x == FALSE ) ? "Not Available" : \ + "(Invalid)" ) + +#define DRX_STR_AUD_NICAM_STATUS(x) ( \ + ( x == DRX_AUD_NICAM_DETECTED ) ? "Detected" : \ + ( x == DRX_AUD_NICAM_NOT_DETECTED ) ? "Not detected" : \ + ( x == DRX_AUD_NICAM_BAD ) ? "Bad" : \ + "(Invalid)" ) + +#define DRX_STR_RDS_VALID(x) ( \ + ( x == TRUE ) ? "Valid" : \ + ( x == FALSE ) ? "Not Valid" : \ + "(Invalid)" ) + +/*------------------------------------------------------------------------- +Access macros +-------------------------------------------------------------------------*/ + + +/** +* \brief Create a compilable reference to the microcode attribute +* \param d pointer to demod instance +* +* Used as main reference to an attribute field. +* Used by both macro implementation and function implementation. +* These macros are defined to avoid duplication of code in macro and function +* definitions that handle access of demod common or extended attributes. +* +*/ + +#define DRX_ATTR_MCRECORD( d ) ((d)->myCommonAttr->mcversion) +#define DRX_ATTR_MIRRORFREQSPECT( d ) ((d)->myCommonAttr->mirrorFreqSpect) +#define DRX_ATTR_CURRENTPOWERMODE( d )((d)->myCommonAttr->currentPowerMode) +#define DRX_ATTR_ISOPENED( d ) ((d)->myCommonAttr->isOpened) +#define DRX_ATTR_USEBOOTLOADER( d ) ((d)->myCommonAttr->useBootloader) +#define DRX_ATTR_CURRENTSTANDARD( d ) ((d)->myCommonAttr->currentStandard) +#define DRX_ATTR_PREVSTANDARD( d ) ((d)->myCommonAttr->prevStandard) +#define DRX_ATTR_CACHESTANDARD( d ) ((d)->myCommonAttr->diCacheStandard) +#define DRX_ATTR_CURRENTCHANNEL( d ) ((d)->myCommonAttr->currentChannel) +#define DRX_ATTR_MICROCODE( d ) ((d)->myCommonAttr->microcode) +#define DRX_ATTR_MICROCODESIZE( d ) ((d)->myCommonAttr->microcodeSize) +#define DRX_ATTR_VERIFYMICROCODE( d ) ((d)->myCommonAttr->verifyMicrocode) +#define DRX_ATTR_CAPABILITIES( d ) ((d)->myCommonAttr->capabilities) +#define DRX_ATTR_PRODUCTID( d ) ((d)->myCommonAttr->productId) +#define DRX_ATTR_INTERMEDIATEFREQ( d) ((d)->myCommonAttr->intermediateFreq) +#define DRX_ATTR_SYSCLOCKFREQ( d) ((d)->myCommonAttr->sysClockFreq) +#define DRX_ATTR_TUNERRFAGCPOL( d ) ((d)->myCommonAttr->tunerRfAgcPol) +#define DRX_ATTR_TUNERIFAGCPOL( d) ((d)->myCommonAttr->tunerIfAgcPol) +#define DRX_ATTR_TUNERSLOWMODE( d) ((d)->myCommonAttr->tunerSlowMode) +#define DRX_ATTR_TUNERSPORTNR( d) ((d)->myCommonAttr->tunerPortNr) +#define DRX_ATTR_TUNER( d ) ((d)->myTuner) +#define DRX_ATTR_I2CADDR( d ) ((d)->myI2CDevAddr->i2cAddr) +#define DRX_ATTR_I2CDEVID( d ) ((d)->myI2CDevAddr->i2cDevId) + +/** +* \brief Actual access macro's +* \param d pointer to demod instance +* \param x value to set ar to get +* +* SET macro's must be used to set the value of an attribute. +* GET macro's must be used to retrieve the value of an attribute. +* +*/ + +/**************************/ + +#define DRX_SET_MIRRORFREQSPECT( d, x ) \ + do { \ + DRX_ATTR_MIRRORFREQSPECT( d ) = (x); \ + } while(0) + +#define DRX_GET_MIRRORFREQSPECT( d, x ) \ + do { \ + (x)=DRX_ATTR_MIRRORFREQSPECT( d ); \ + } while(0) + +/**************************/ + +#define DRX_SET_CURRENTPOWERMODE( d, x ) \ + do { \ + DRX_ATTR_CURRENTPOWERMODE( d ) = (x); \ + } while(0) + +#define DRX_GET_CURRENTPOWERMODE( d, x ) \ + do { \ + (x)=DRX_ATTR_CURRENTPOWERMODE( d ); \ + } while(0) + +/**************************/ + +#define DRX_SET_MICROCODE( d, x ) \ + do { \ + DRX_ATTR_MICROCODE( d ) = (x); \ + } while(0) + +#define DRX_GET_MICROCODE( d, x ) \ + do { \ + (x)=DRX_ATTR_MICROCODE( d ); \ + } while(0) + +/**************************/ + +#define DRX_SET_MICROCODESIZE( d, x ) \ + do { \ + DRX_ATTR_MICROCODESIZE(d) = (x); \ + } while(0) + +#define DRX_GET_MICROCODESIZE( d, x ) \ + do { \ + (x)=DRX_ATTR_MICROCODESIZE(d); \ + } while(0) + +/**************************/ + +#define DRX_SET_VERIFYMICROCODE( d, x ) \ + do { \ + DRX_ATTR_VERIFYMICROCODE(d) = (x); \ + } while(0) + +#define DRX_GET_VERIFYMICROCODE( d, x ) \ + do { \ + (x)=DRX_ATTR_VERIFYMICROCODE(d); \ + } while(0) + +/**************************/ + +#define DRX_SET_MCVERTYPE( d, x ) \ + do { \ + DRX_ATTR_MCRECORD(d).auxType = (x); \ + } while (0) + +#define DRX_GET_MCVERTYPE( d, x ) \ + do { \ + (x) = DRX_ATTR_MCRECORD(d).auxType; \ + } while (0) + +/**************************/ + +#define DRX_ISMCVERTYPE(x) ((x) == AUX_VER_RECORD) + +/**************************/ + +#define DRX_SET_MCDEV( d, x ) \ + do { \ + DRX_ATTR_MCRECORD(d).mcDevType = (x); \ + } while (0) + +#define DRX_GET_MCDEV( d, x ) \ + do { \ + (x) = DRX_ATTR_MCRECORD(d).mcDevType; \ + } while (0) + +/**************************/ + +#define DRX_SET_MCVERSION( d, x ) \ + do { \ + DRX_ATTR_MCRECORD(d).mcVersion = (x); \ + } while (0) + +#define DRX_GET_MCVERSION( d, x ) \ + do { \ + (x) = DRX_ATTR_MCRECORD(d).mcVersion; \ + } while (0) + +/**************************/ +#define DRX_SET_MCPATCH( d, x ) \ + do { \ + DRX_ATTR_MCRECORD(d).mcBaseVersion = (x); \ + } while (0) + +#define DRX_GET_MCPATCH( d, x ) \ + do { \ + (x) = DRX_ATTR_MCRECORD(d).mcBaseVersion; \ + } while (0) + +/**************************/ + +#define DRX_SET_I2CADDR( d, x ) \ + do { \ + DRX_ATTR_I2CADDR(d) = (x); \ + } while(0) + +#define DRX_GET_I2CADDR( d, x ) \ + do { \ + (x)=DRX_ATTR_I2CADDR(d); \ + } while(0) + +/**************************/ + +#define DRX_SET_I2CDEVID( d, x ) \ + do { \ + DRX_ATTR_I2CDEVID(d) = (x); \ + } while(0) + +#define DRX_GET_I2CDEVID( d, x ) \ + do { \ + (x)=DRX_ATTR_I2CDEVID(d); \ + } while(0) + +/**************************/ + +#define DRX_SET_USEBOOTLOADER( d, x ) \ + do { \ + DRX_ATTR_USEBOOTLOADER(d) = (x); \ + } while(0) + +#define DRX_GET_USEBOOTLOADER( d, x) \ + do { \ + (x)=DRX_ATTR_USEBOOTLOADER(d); \ + } while(0) + +/**************************/ + +#define DRX_SET_CURRENTSTANDARD( d, x ) \ + do { \ + DRX_ATTR_CURRENTSTANDARD(d) = (x); \ + } while(0) + +#define DRX_GET_CURRENTSTANDARD( d, x) \ + do { \ + (x)=DRX_ATTR_CURRENTSTANDARD(d); \ + } while(0) + +/**************************/ + +#define DRX_SET_PREVSTANDARD( d, x ) \ + do { \ + DRX_ATTR_PREVSTANDARD(d) = (x); \ + } while(0) + +#define DRX_GET_PREVSTANDARD( d, x) \ + do { \ + (x)=DRX_ATTR_PREVSTANDARD(d); \ + } while(0) + +/**************************/ + +#define DRX_SET_CACHESTANDARD( d, x ) \ + do { \ + DRX_ATTR_CACHESTANDARD(d) = (x); \ + } while(0) + +#define DRX_GET_CACHESTANDARD( d, x) \ + do { \ + (x)=DRX_ATTR_CACHESTANDARD(d); \ + } while(0) + +/**************************/ + +#define DRX_SET_CURRENTCHANNEL( d, x ) \ + do { \ + DRX_ATTR_CURRENTCHANNEL(d) = (x); \ + } while(0) + +#define DRX_GET_CURRENTCHANNEL( d, x) \ + do { \ + (x)=DRX_ATTR_CURRENTCHANNEL(d); \ + } while(0) + +/**************************/ + +#define DRX_SET_ISOPENED( d, x ) \ + do { \ + DRX_ATTR_ISOPENED(d) = (x); \ + } while(0) + +#define DRX_GET_ISOPENED( d, x) \ + do { \ + (x) = DRX_ATTR_ISOPENED(d); \ + } while(0) + +/**************************/ + +#define DRX_SET_TUNER( d, x ) \ + do { \ + DRX_ATTR_TUNER(d) = (x); \ + } while(0) + +#define DRX_GET_TUNER( d, x) \ + do { \ + (x) = DRX_ATTR_TUNER(d); \ + } while(0) + +/**************************/ + +#define DRX_SET_CAPABILITIES( d, x ) \ + do { \ + DRX_ATTR_CAPABILITIES(d) = (x); \ + } while(0) + +#define DRX_GET_CAPABILITIES( d, x) \ + do { \ + (x) = DRX_ATTR_CAPABILITIES(d); \ + } while(0) + +/**************************/ + +#define DRX_SET_PRODUCTID( d, x ) \ + do { \ + DRX_ATTR_PRODUCTID(d) |= (x << 4); \ + } while(0) + +#define DRX_GET_PRODUCTID( d, x) \ + do { \ + (x) = (DRX_ATTR_PRODUCTID(d) >> 4); \ + } while(0) + +/**************************/ + +#define DRX_SET_MFX( d, x ) \ + do { \ + DRX_ATTR_PRODUCTID(d) |= (x); \ + } while(0) + +#define DRX_GET_MFX( d, x) \ + do { \ + (x) = (DRX_ATTR_PRODUCTID(d) & 0xF); \ + } while(0) + +/**************************/ + +#define DRX_SET_INTERMEDIATEFREQ( d, x ) \ + do { \ + DRX_ATTR_INTERMEDIATEFREQ(d) = (x); \ + } while(0) + +#define DRX_GET_INTERMEDIATEFREQ( d, x) \ + do { \ + (x) = DRX_ATTR_INTERMEDIATEFREQ(d); \ + } while(0) + +/**************************/ + +#define DRX_SET_SYSCLOCKFREQ( d, x ) \ + do { \ + DRX_ATTR_SYSCLOCKFREQ(d) = (x); \ + } while(0) + +#define DRX_GET_SYSCLOCKFREQ( d, x) \ + do { \ + (x) = DRX_ATTR_SYSCLOCKFREQ(d); \ + } while(0) + +/**************************/ + +#define DRX_SET_TUNERRFAGCPOL( d, x ) \ + do { \ + DRX_ATTR_TUNERRFAGCPOL(d) = (x); \ + } while(0) + +#define DRX_GET_TUNERRFAGCPOL( d, x) \ + do { \ + (x) = DRX_ATTR_TUNERRFAGCPOL(d); \ + } while(0) + +/**************************/ + +#define DRX_SET_TUNERIFAGCPOL( d, x ) \ + do { \ + DRX_ATTR_TUNERIFAGCPOL(d) = (x); \ + } while(0) + +#define DRX_GET_TUNERIFAGCPOL( d, x) \ + do { \ + (x) = DRX_ATTR_TUNERIFAGCPOL(d); \ + } while(0) + +/**************************/ + +#define DRX_SET_TUNERSLOWMODE( d, x ) \ + do { \ + DRX_ATTR_TUNERSLOWMODE(d) = (x); \ + } while(0) + +#define DRX_GET_TUNERSLOWMODE( d, x) \ + do { \ + (x) = DRX_ATTR_TUNERSLOWMODE(d); \ + } while(0) + +/**************************/ + +#define DRX_SET_TUNERPORTNR( d, x ) \ + do { \ + DRX_ATTR_TUNERSPORTNR(d) = (x); \ + } while(0) + +/**************************/ + +/* Macros with device-specific handling are converted to CFG functions */ + +#define DRX_ACCESSMACRO_SET( demod, value, cfgName, dataType ) \ + do { \ + DRXCfg_t config; \ + dataType cfgData; \ + config.cfgType = cfgName; \ + config.cfgData = &cfgData; \ + cfgData = value; \ + DRX_Ctrl( demod, DRX_CTRL_SET_CFG, &config ); \ + } while ( 0 ) + +#define DRX_ACCESSMACRO_GET( demod, value, cfgName, dataType, errorValue ) \ + do { \ + DRXStatus_t cfgStatus; \ + DRXCfg_t config; \ + dataType cfgData; \ + config.cfgType = cfgName; \ + config.cfgData = &cfgData; \ + cfgStatus = DRX_Ctrl( demod, DRX_CTRL_GET_CFG, &config ); \ + if ( cfgStatus == DRX_STS_OK ) { \ + value = cfgData; \ + } else { \ + value = (dataType)errorValue; \ + } \ + } while ( 0 ) + + +/* Configuration functions for usage by Access (XS) Macros */ + +#ifndef DRX_XS_CFG_BASE +#define DRX_XS_CFG_BASE (500) +#endif + +#define DRX_XS_CFG_PRESET ( DRX_XS_CFG_BASE + 0 ) +#define DRX_XS_CFG_AUD_BTSC_DETECT ( DRX_XS_CFG_BASE + 1 ) +#define DRX_XS_CFG_QAM_LOCKRANGE ( DRX_XS_CFG_BASE + 2 ) + +/* Access Macros with device-specific handling */ + +#define DRX_SET_PRESET( d, x ) \ + DRX_ACCESSMACRO_SET( (d), (x), DRX_XS_CFG_PRESET, char* ) +#define DRX_GET_PRESET( d, x ) \ + DRX_ACCESSMACRO_GET( (d), (x), DRX_XS_CFG_PRESET, char*, "ERROR" ) + +#define DRX_SET_AUD_BTSC_DETECT( d, x ) DRX_ACCESSMACRO_SET( (d), (x), \ + DRX_XS_CFG_AUD_BTSC_DETECT, DRXAudBtscDetect_t ) +#define DRX_GET_AUD_BTSC_DETECT( d, x ) DRX_ACCESSMACRO_GET( (d), (x), \ + DRX_XS_CFG_AUD_BTSC_DETECT, DRXAudBtscDetect_t, DRX_UNKNOWN ) + +#define DRX_SET_QAM_LOCKRANGE( d, x ) DRX_ACCESSMACRO_SET( (d), (x), \ + DRX_XS_CFG_QAM_LOCKRANGE, DRXQamLockRange_t ) +#define DRX_GET_QAM_LOCKRANGE( d, x ) DRX_ACCESSMACRO_GET( (d), (x), \ + DRX_XS_CFG_QAM_LOCKRANGE, DRXQamLockRange_t, DRX_UNKNOWN ) + + +/** +* \brief Macro to check if std is an ATV standard +* \retval TRUE std is an ATV standard +* \retval FALSE std is an ATV standard +*/ +#define DRX_ISATVSTD( std ) ( ( (std) == DRX_STANDARD_PAL_SECAM_BG ) || \ + ( (std) == DRX_STANDARD_PAL_SECAM_DK ) || \ + ( (std) == DRX_STANDARD_PAL_SECAM_I ) || \ + ( (std) == DRX_STANDARD_PAL_SECAM_L ) || \ + ( (std) == DRX_STANDARD_PAL_SECAM_LP ) || \ + ( (std) == DRX_STANDARD_NTSC ) || \ + ( (std) == DRX_STANDARD_FM ) ) + +/** +* \brief Macro to check if std is an QAM standard +* \retval TRUE std is an QAM standards +* \retval FALSE std is an QAM standards +*/ +#define DRX_ISQAMSTD( std ) ( ( (std) == DRX_STANDARD_ITU_A ) || \ + ( (std) == DRX_STANDARD_ITU_B ) || \ + ( (std) == DRX_STANDARD_ITU_C ) || \ + ( (std) == DRX_STANDARD_ITU_D )) + +/** +* \brief Macro to check if std is VSB standard +* \retval TRUE std is VSB standard +* \retval FALSE std is not VSB standard +*/ +#define DRX_ISVSBSTD( std ) ( (std) == DRX_STANDARD_8VSB ) + +/** +* \brief Macro to check if std is DVBT standard +* \retval TRUE std is DVBT standard +* \retval FALSE std is not DVBT standard +*/ +#define DRX_ISDVBTSTD( std ) ( (std) == DRX_STANDARD_DVBT ) + + + + +/*------------------------------------------------------------------------- +Exported FUNCTIONS +-------------------------------------------------------------------------*/ + +DRXStatus_t DRX_Init( pDRXDemodInstance_t demods[] ); + +DRXStatus_t DRX_Term( void ); + +DRXStatus_t DRX_Open(pDRXDemodInstance_t demod); + +DRXStatus_t DRX_Close(pDRXDemodInstance_t demod); + +DRXStatus_t DRX_Ctrl(pDRXDemodInstance_t demod, + DRXCtrlIndex_t ctrl, + void *ctrlData); + +/*------------------------------------------------------------------------- +THE END +-------------------------------------------------------------------------*/ +#ifdef __cplusplus +} +#endif +#endif /* __DRXDRIVER_H__ */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver_version.h b/drivers/media/dvb-frontends/drx39xyj/drx_driver_version.h new file mode 100644 index 0000000..e6c777c --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver_version.h @@ -0,0 +1,83 @@ +/* + ******************************************************************************* + * WARNING - THIS FILE HAS BEEN GENERATED - DO NOT CHANGE + * + * Filename: drx_driver_version.h + * Generated on: Mon Jan 18 12:09:23 2010 + * Generated by: IDF:x 1.3.0 + * Generated from: ../../../device/drxj/version + * Output start: [entry point] + * + * filename last modified re-use + * ----------------------------------------------------- + * version.idf Mon Jan 18 11:56:10 2010 - + * + * $(c) 2010 Trident Microsystems, Inc. - All rights reserved. + * + * This software and related documentation (the 'Software') are intellectual + * property owned by Trident and are copyright of Trident, unless specifically + * noted otherwise. + * + * Any use of the Software is permitted only pursuant to the terms of the + * license agreement, if any, which accompanies, is included with or applicable + * to the Software ('License Agreement') or upon express written consent of + * Trident. Any copying, reproduction or redistribution of the Software in + * whole or in part by any means not in accordance with the License Agreement + * or as agreed in writing by Trident is expressly prohibited. + * + * THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE + * LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE + * IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND + * CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES AND + * CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT + * ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL + * PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY TO + * USE THE SOFTWARE. + * + * IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, + * PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, + * DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF + * BUSINESS INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF + * OR THE INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING + * FROM TRIDENT'S NEGLIGENCE. $ + * + ******************************************************************************* + */ + +#ifndef __DRX_DRIVER_VERSION__H__ +#define __DRX_DRIVER_VERSION__H__ INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef _REGISTERTABLE_ +#include +extern RegisterTable_t drx_driver_version[]; +extern RegisterTableInfo_t drx_driver_version_info[]; +#endif /* _REGISTERTABLE_ */ + + +/* + *============================================================================== + * VERSION + * version@/var/cvs/projects/drxj.cvsroot/hostcode/drxdriver/device/drxj + *============================================================================== + */ + +#define VERSION__A 0x0 +#define VERSION_MAJOR 1 +#define VERSION_MINOR 0 +#define VERSION_PATCH 56 + +#ifdef __cplusplus +} +#endif + +#endif /* __DRX_DRIVER_VERSION__H__ */ + +/* + * End of file (drx_driver_version.h) + ******************************************************************************* + */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c new file mode 100644 index 0000000..a83f2ad --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -0,0 +1,16680 @@ +/** +* \file $Id: drxj.c,v 1.637 2010/01/18 17:21:10 dingtao Exp $ +* +* \brief DRXJ specific implementation of DRX driver +* +* \author Dragan Savic, Milos Nikolic, Mihajlo Katona, Tao Ding, Paul Janssen +*/ + +/* +* $(c) 2006-2010 Trident Microsystems, Inc. - All rights reserved. +* +* This software and related documentation (the 'Software') are intellectual +* property owned by Trident and are copyright of Trident, unless specifically +* noted otherwise. +* +* Any use of the Software is permitted only pursuant to the terms of the +* license agreement, if any, which accompanies, is included with or applicable +* to the Software ('License Agreement') or upon express written consent of +* Trident. Any copying, reproduction or redistribution of the Software in +* whole or in part by any means not in accordance with the License Agreement +* or as agreed in writing by Trident is expressly prohibited. +* +* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE +* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE +* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND +* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES +* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT +* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL +* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY +* TO USE THE SOFTWARE. +* +* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, +* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, +* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS +* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE +* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM +* TRIDENT'S NEGLIGENCE. $ +* +*/ + +/*----------------------------------------------------------------------------- +INCLUDE FILES +----------------------------------------------------------------------------*/ + +#include "drxj.h" +#include "drxj_map.h" + +#ifdef DRXJ_OPTIONS_H +#include "drxj_options.h" +#endif + + +/*============================================================================*/ +/*=== DEFINES ================================================================*/ +/*============================================================================*/ + +/** +* \brief Maximum u32_t value. +*/ +#ifndef MAX_U32 +#define MAX_U32 ((u32_t) (0xFFFFFFFFL)) +#endif + +/* Customer configurable hardware settings, etc */ +#ifndef MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH +#define MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH 0x02 +#endif + +#ifndef MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH +#define MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH 0x02 +#endif + +#ifndef MPEG_OUTPUT_CLK_DRIVE_STRENGTH +#define MPEG_OUTPUT_CLK_DRIVE_STRENGTH 0x06 +#endif + +#ifndef OOB_CRX_DRIVE_STRENGTH +#define OOB_CRX_DRIVE_STRENGTH 0x02 +#endif + +#ifndef OOB_DRX_DRIVE_STRENGTH +#define OOB_DRX_DRIVE_STRENGTH 0x02 +#endif +/**** START DJCOMBO patches to DRXJ registermap constants *********************/ +/**** registermap 200706071303 from drxj **************************************/ +#define ATV_TOP_CR_AMP_TH_FM 0x0 +#define ATV_TOP_CR_AMP_TH_L 0xA +#define ATV_TOP_CR_AMP_TH_LP 0xA +#define ATV_TOP_CR_AMP_TH_BG 0x8 +#define ATV_TOP_CR_AMP_TH_DK 0x8 +#define ATV_TOP_CR_AMP_TH_I 0x8 +#define ATV_TOP_CR_CONT_CR_D_MN 0x18 +#define ATV_TOP_CR_CONT_CR_D_FM 0x0 +#define ATV_TOP_CR_CONT_CR_D_L 0x20 +#define ATV_TOP_CR_CONT_CR_D_LP 0x20 +#define ATV_TOP_CR_CONT_CR_D_BG 0x18 +#define ATV_TOP_CR_CONT_CR_D_DK 0x18 +#define ATV_TOP_CR_CONT_CR_D_I 0x18 +#define ATV_TOP_CR_CONT_CR_I_MN 0x80 +#define ATV_TOP_CR_CONT_CR_I_FM 0x0 +#define ATV_TOP_CR_CONT_CR_I_L 0x80 +#define ATV_TOP_CR_CONT_CR_I_LP 0x80 +#define ATV_TOP_CR_CONT_CR_I_BG 0x80 +#define ATV_TOP_CR_CONT_CR_I_DK 0x80 +#define ATV_TOP_CR_CONT_CR_I_I 0x80 +#define ATV_TOP_CR_CONT_CR_P_MN 0x4 +#define ATV_TOP_CR_CONT_CR_P_FM 0x0 +#define ATV_TOP_CR_CONT_CR_P_L 0x4 +#define ATV_TOP_CR_CONT_CR_P_LP 0x4 +#define ATV_TOP_CR_CONT_CR_P_BG 0x4 +#define ATV_TOP_CR_CONT_CR_P_DK 0x4 +#define ATV_TOP_CR_CONT_CR_P_I 0x4 +#define ATV_TOP_CR_OVM_TH_MN 0xA0 +#define ATV_TOP_CR_OVM_TH_FM 0x0 +#define ATV_TOP_CR_OVM_TH_L 0xA0 +#define ATV_TOP_CR_OVM_TH_LP 0xA0 +#define ATV_TOP_CR_OVM_TH_BG 0xA0 +#define ATV_TOP_CR_OVM_TH_DK 0xA0 +#define ATV_TOP_CR_OVM_TH_I 0xA0 +#define ATV_TOP_EQU0_EQU_C0_FM 0x0 +#define ATV_TOP_EQU0_EQU_C0_L 0x3 +#define ATV_TOP_EQU0_EQU_C0_LP 0x3 +#define ATV_TOP_EQU0_EQU_C0_BG 0x7 +#define ATV_TOP_EQU0_EQU_C0_DK 0x0 +#define ATV_TOP_EQU0_EQU_C0_I 0x3 +#define ATV_TOP_EQU1_EQU_C1_FM 0x0 +#define ATV_TOP_EQU1_EQU_C1_L 0x1F6 +#define ATV_TOP_EQU1_EQU_C1_LP 0x1F6 +#define ATV_TOP_EQU1_EQU_C1_BG 0x197 +#define ATV_TOP_EQU1_EQU_C1_DK 0x198 +#define ATV_TOP_EQU1_EQU_C1_I 0x1F6 +#define ATV_TOP_EQU2_EQU_C2_FM 0x0 +#define ATV_TOP_EQU2_EQU_C2_L 0x28 +#define ATV_TOP_EQU2_EQU_C2_LP 0x28 +#define ATV_TOP_EQU2_EQU_C2_BG 0xC5 +#define ATV_TOP_EQU2_EQU_C2_DK 0xB0 +#define ATV_TOP_EQU2_EQU_C2_I 0x28 +#define ATV_TOP_EQU3_EQU_C3_FM 0x0 +#define ATV_TOP_EQU3_EQU_C3_L 0x192 +#define ATV_TOP_EQU3_EQU_C3_LP 0x192 +#define ATV_TOP_EQU3_EQU_C3_BG 0x12E +#define ATV_TOP_EQU3_EQU_C3_DK 0x18E +#define ATV_TOP_EQU3_EQU_C3_I 0x192 +#define ATV_TOP_STD_MODE_MN 0x0 +#define ATV_TOP_STD_MODE_FM 0x1 +#define ATV_TOP_STD_MODE_L 0x0 +#define ATV_TOP_STD_MODE_LP 0x0 +#define ATV_TOP_STD_MODE_BG 0x0 +#define ATV_TOP_STD_MODE_DK 0x0 +#define ATV_TOP_STD_MODE_I 0x0 +#define ATV_TOP_STD_VID_POL_MN 0x0 +#define ATV_TOP_STD_VID_POL_FM 0x0 +#define ATV_TOP_STD_VID_POL_L 0x2 +#define ATV_TOP_STD_VID_POL_LP 0x2 +#define ATV_TOP_STD_VID_POL_BG 0x0 +#define ATV_TOP_STD_VID_POL_DK 0x0 +#define ATV_TOP_STD_VID_POL_I 0x0 +#define ATV_TOP_VID_AMP_MN 0x380 +#define ATV_TOP_VID_AMP_FM 0x0 +#define ATV_TOP_VID_AMP_L 0xF50 +#define ATV_TOP_VID_AMP_LP 0xF50 +#define ATV_TOP_VID_AMP_BG 0x380 +#define ATV_TOP_VID_AMP_DK 0x394 +#define ATV_TOP_VID_AMP_I 0x3D8 +#define IQM_CF_OUT_ENA_OFDM__M 0x4 +#define IQM_FS_ADJ_SEL_B_QAM 0x1 +#define IQM_FS_ADJ_SEL_B_OFF 0x0 +#define IQM_FS_ADJ_SEL_B_VSB 0x2 +#define IQM_RC_ADJ_SEL_B_OFF 0x0 +#define IQM_RC_ADJ_SEL_B_QAM 0x1 +#define IQM_RC_ADJ_SEL_B_VSB 0x2 +/**** END DJCOMBO patches to DRXJ registermap *********************************/ + +#include "drx_driver_version.h" + +//#define DRX_DEBUG +#ifdef DRX_DEBUG +#include +#endif + +/*----------------------------------------------------------------------------- +ENUMS +----------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------- +DEFINES +----------------------------------------------------------------------------*/ +#ifndef DRXJ_WAKE_UP_KEY +#define DRXJ_WAKE_UP_KEY (demod -> myI2CDevAddr -> i2cAddr) +#endif + +/** +* \def DRXJ_DEF_I2C_ADDR +* \brief Default I2C addres of a demodulator instance. +*/ +#define DRXJ_DEF_I2C_ADDR (0x52) + +/** +* \def DRXJ_DEF_DEMOD_DEV_ID +* \brief Default device identifier of a demodultor instance. +*/ +#define DRXJ_DEF_DEMOD_DEV_ID (1) + +/** +* \def DRXJ_SCAN_TIMEOUT +* \brief Timeout value for waiting on demod lock during channel scan (millisec). +*/ +#define DRXJ_SCAN_TIMEOUT 1000 + +/** +* \def DRXJ_DAP +* \brief Name of structure containing all data access protocol functions. +*/ +#define DRXJ_DAP drxDapDRXJFunct_g + +/** +* \def HI_I2C_DELAY +* \brief HI timing delay for I2C timing (in nano seconds) +* +* Used to compute HI_CFG_DIV +*/ +#define HI_I2C_DELAY 42 + +/** +* \def HI_I2C_BRIDGE_DELAY +* \brief HI timing delay for I2C timing (in nano seconds) +* +* Used to compute HI_CFG_BDL +*/ +#define HI_I2C_BRIDGE_DELAY 750 + +/** +* \brief Time Window for MER and SER Measurement in Units of Segment duration. +*/ +#define VSB_TOP_MEASUREMENT_PERIOD 64 +#define SYMBOLS_PER_SEGMENT 832 + +/** +* \brief bit rate and segment rate constants used for SER and BER. +*/ +/* values taken from the QAM microcode */ +#define DRXJ_QAM_SL_SIG_POWER_QAM_UNKNOWN 0 +#define DRXJ_QAM_SL_SIG_POWER_QPSK 32768 +#define DRXJ_QAM_SL_SIG_POWER_QAM8 24576 +#define DRXJ_QAM_SL_SIG_POWER_QAM16 40960 +#define DRXJ_QAM_SL_SIG_POWER_QAM32 20480 +#define DRXJ_QAM_SL_SIG_POWER_QAM64 43008 +#define DRXJ_QAM_SL_SIG_POWER_QAM128 20992 +#define DRXJ_QAM_SL_SIG_POWER_QAM256 43520 +/** +* \brief Min supported symbolrates. +*/ +#ifndef DRXJ_QAM_SYMBOLRATE_MIN +#define DRXJ_QAM_SYMBOLRATE_MIN (520000) +#endif + +/** +* \brief Max supported symbolrates. +*/ +#ifndef DRXJ_QAM_SYMBOLRATE_MAX +#define DRXJ_QAM_SYMBOLRATE_MAX (7233000) +#endif + +/** +* \def DRXJ_QAM_MAX_WAITTIME +* \brief Maximal wait time for QAM auto constellation in ms +*/ +#ifndef DRXJ_QAM_MAX_WAITTIME +#define DRXJ_QAM_MAX_WAITTIME 900 +#endif + +#ifndef DRXJ_QAM_FEC_LOCK_WAITTIME +#define DRXJ_QAM_FEC_LOCK_WAITTIME 150 +#endif + +#ifndef DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME +#define DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME 200 +#endif + +/** +* \def SCU status and results +* \brief SCU +*/ +#define DRX_SCU_READY 0 +#define DRXJ_MAX_WAITTIME 100 /* ms */ +#define FEC_RS_MEASUREMENT_PERIOD 12894 /* 1 sec */ +#define FEC_RS_MEASUREMENT_PRESCALE 1 /* n sec */ + +/** +* \def DRX_AUD_MAX_DEVIATION +* \brief Needed for calculation of prescale feature in AUD +*/ +#ifndef DRXJ_AUD_MAX_FM_DEVIATION +#define DRXJ_AUD_MAX_FM_DEVIATION 100 /* kHz */ +#endif + +/** +* \brief Needed for calculation of NICAM prescale feature in AUD +*/ +#ifndef DRXJ_AUD_MAX_NICAM_PRESCALE +#define DRXJ_AUD_MAX_NICAM_PRESCALE (9) /* dB */ +#endif + +/** +* \brief Needed for calculation of NICAM prescale feature in AUD +*/ +#ifndef DRXJ_AUD_MAX_WAITTIME +#define DRXJ_AUD_MAX_WAITTIME 250 /* ms */ +#endif + +/* ATV config changed flags */ +#define DRXJ_ATV_CHANGED_COEF ( 0x00000001UL ) +#define DRXJ_ATV_CHANGED_PEAK_FLT ( 0x00000008UL ) +#define DRXJ_ATV_CHANGED_NOISE_FLT ( 0x00000010UL ) +#define DRXJ_ATV_CHANGED_OUTPUT ( 0x00000020UL ) +#define DRXJ_ATV_CHANGED_SIF_ATT ( 0x00000040UL ) + +/* UIO define */ +#define DRX_UIO_MODE_FIRMWARE_SMA DRX_UIO_MODE_FIRMWARE0 +#define DRX_UIO_MODE_FIRMWARE_SAW DRX_UIO_MODE_FIRMWARE1 + +#ifdef DRXJ_SPLIT_UCODE_UPLOAD +/*============================================================================*/ +/*=== MICROCODE RELATED DEFINES ==============================================*/ +/*============================================================================*/ + +/** +* \def DRXJ_UCODE_MAGIC_WORD +* \brief Magic word for checking correct Endianess of microcode data. +* +*/ + +#ifndef DRXJ_UCODE_MAGIC_WORD +#define DRXJ_UCODE_MAGIC_WORD ((((u16_t)'H')<<8)+((u16_t)'L')) +#endif + +/** +* \def DRXJ_UCODE_CRC_FLAG +* \brief CRC flag in ucode header, flags field. +* +*/ + +#ifndef DRXJ_UCODE_CRC_FLAG +#define DRXJ_UCODE_CRC_FLAG (0x0001) +#endif + +/** +* \def DRXJ_UCODE_COMPRESSION_FLAG +* \brief Compression flag in ucode header, flags field. +* +*/ + +#ifndef DRXJ_UCODE_COMPRESSION_FLAG +#define DRXJ_UCODE_COMPRESSION_FLAG (0x0002) +#endif + +/** +* \def DRXJ_UCODE_MAX_BUF_SIZE +* \brief Maximum size of buffer used to verify the microcode.Must be an even number. +* +*/ + +#ifndef DRXJ_UCODE_MAX_BUF_SIZE +#define DRXJ_UCODE_MAX_BUF_SIZE (DRXDAP_MAX_RCHUNKSIZE) +#endif +#if DRXJ_UCODE_MAX_BUF_SIZE & 1 +#error DRXJ_UCODE_MAX_BUF_SIZE must be an even number +#endif + +#endif /* DRXJ_SPLIT_UCODE_UPLOAD */ + +/* Pin safe mode macro */ +#define DRXJ_PIN_SAFE_MODE 0x0000 +/*============================================================================*/ +/*=== GLOBAL VARIABLEs =======================================================*/ +/*============================================================================*/ +/** +*/ + +/** +* \brief Temporary register definitions. +* (register definitions that are not yet available in register master) +*/ + +/******************************************************************************/ +/* Audio block 0x103 is write only. To avoid shadowing in driver accessing */ +/* RAM adresses directly. This must be READ ONLY to avoid problems. */ +/* Writing to the interface adresses is more than only writing the RAM */ +/* locations */ +/******************************************************************************/ +/** +* \brief RAM location of MODUS registers +*/ +#define AUD_DEM_RAM_MODUS_HI__A 0x10204A3 +#define AUD_DEM_RAM_MODUS_HI__M 0xF000 + +#define AUD_DEM_RAM_MODUS_LO__A 0x10204A4 +#define AUD_DEM_RAM_MODUS_LO__M 0x0FFF + +/** +* \brief RAM location of I2S config registers +*/ +#define AUD_DEM_RAM_I2S_CONFIG1__A 0x10204B1 +#define AUD_DEM_RAM_I2S_CONFIG2__A 0x10204B2 + +/** +* \brief RAM location of DCO config registers +*/ +#define AUD_DEM_RAM_DCO_B_HI__A 0x1020461 +#define AUD_DEM_RAM_DCO_B_LO__A 0x1020462 +#define AUD_DEM_RAM_DCO_A_HI__A 0x1020463 +#define AUD_DEM_RAM_DCO_A_LO__A 0x1020464 + +/** +* \brief RAM location of Threshold registers +*/ +#define AUD_DEM_RAM_NICAM_THRSHLD__A 0x102045A +#define AUD_DEM_RAM_A2_THRSHLD__A 0x10204BB +#define AUD_DEM_RAM_BTSC_THRSHLD__A 0x10204A6 + +/** +* \brief RAM location of Carrier Threshold registers +*/ +#define AUD_DEM_RAM_CM_A_THRSHLD__A 0x10204AF +#define AUD_DEM_RAM_CM_B_THRSHLD__A 0x10204B0 + +/** +* \brief FM Matrix register fix +*/ +#ifdef AUD_DEM_WR_FM_MATRIX__A +#undef AUD_DEM_WR_FM_MATRIX__A +#endif +#define AUD_DEM_WR_FM_MATRIX__A 0x105006F + +/*============================================================================*/ +/** +* \brief Defines required for audio +*/ +#define AUD_VOLUME_ZERO_DB 115 +#define AUD_VOLUME_DB_MIN -60 +#define AUD_VOLUME_DB_MAX 12 +#define AUD_CARRIER_STRENGTH_QP_0DB 0x4000 +#define AUD_CARRIER_STRENGTH_QP_0DB_LOG10T100 421 +#define AUD_MAX_AVC_REF_LEVEL 15 +#define AUD_I2S_FREQUENCY_MAX 48000UL +#define AUD_I2S_FREQUENCY_MIN 12000UL +#define AUD_RDS_ARRAY_SIZE 18 + +/** +* \brief Needed for calculation of prescale feature in AUD +*/ +#ifndef DRX_AUD_MAX_FM_DEVIATION +#define DRX_AUD_MAX_FM_DEVIATION (100) /* kHz */ +#endif + +/** +* \brief Needed for calculation of NICAM prescale feature in AUD +*/ +#ifndef DRX_AUD_MAX_NICAM_PRESCALE +#define DRX_AUD_MAX_NICAM_PRESCALE (9) /* dB */ +#endif + + +/*============================================================================*/ +/* Values for I2S Master/Slave pin configurations */ +#define SIO_PDR_I2S_CL_CFG_MODE__MASTER 0x0004 +#define SIO_PDR_I2S_CL_CFG_DRIVE__MASTER 0x0008 +#define SIO_PDR_I2S_CL_CFG_MODE__SLAVE 0x0004 +#define SIO_PDR_I2S_CL_CFG_DRIVE__SLAVE 0x0000 + +#define SIO_PDR_I2S_DA_CFG_MODE__MASTER 0x0003 +#define SIO_PDR_I2S_DA_CFG_DRIVE__MASTER 0x0008 +#define SIO_PDR_I2S_DA_CFG_MODE__SLAVE 0x0003 +#define SIO_PDR_I2S_DA_CFG_DRIVE__SLAVE 0x0008 + +#define SIO_PDR_I2S_WS_CFG_MODE__MASTER 0x0004 +#define SIO_PDR_I2S_WS_CFG_DRIVE__MASTER 0x0008 +#define SIO_PDR_I2S_WS_CFG_MODE__SLAVE 0x0004 +#define SIO_PDR_I2S_WS_CFG_DRIVE__SLAVE 0x0000 + +/*============================================================================*/ +/*=== REGISTER ACCESS MACROS =================================================*/ +/*============================================================================*/ + +#ifdef DRXJDRIVER_DEBUG +#include +#define CHK_ERROR( s ) \ + do{ \ + if ( (s) != DRX_STS_OK ) \ + { \ + fprintf(stderr, \ + "ERROR[\n file : %s\n line : %d\n]\n", \ + __FILE__,__LINE__); \ + goto rw_error; }; \ + } \ + while (0 != 0) +#else +#define CHK_ERROR( s ) \ + do{ \ + if ( (s) != DRX_STS_OK ) { goto rw_error; } \ + } while (0 != 0) +#endif + +#define CHK_ZERO( s ) \ + do{ \ + if ( (s) == 0 ) return DRX_STS_ERROR; \ + } while (0) + +#define DUMMY_READ() \ + do{ \ + u16_t dummy; \ + RR16( demod->myI2CDevAddr, SCU_RAM_VERSION_HI__A, &dummy ); \ + } while (0) + +#define WR16( dev, addr, val) \ + CHK_ERROR( DRXJ_DAP.writeReg16Func( (dev), (addr), (val), 0 ) ) + +#define RR16( dev, addr, val) \ + CHK_ERROR( DRXJ_DAP.readReg16Func( (dev), (addr), (val), 0 ) ) + +#define WR32( dev, addr, val) \ + CHK_ERROR( DRXJ_DAP.writeReg32Func( (dev), (addr), (val), 0 ) ) + +#define RR32( dev, addr, val) \ + CHK_ERROR( DRXJ_DAP.readReg32Func( (dev), (addr), (val), 0 ) ) + +#define WRB( dev, addr, len, block ) \ + CHK_ERROR( DRXJ_DAP.writeBlockFunc( (dev), (addr), (len), (block), 0 ) ) + +#define RRB( dev, addr, len, block ) \ + CHK_ERROR( DRXJ_DAP.readBlockFunc( (dev), (addr), (len), (block), 0 ) ) + +#define BCWR16( dev, addr, val ) \ + CHK_ERROR( DRXJ_DAP.writeReg16Func( (dev), (addr), (val), DRXDAP_FASI_BROADCAST ) ) + +#define ARR32( dev, addr, val) \ + CHK_ERROR( DRXJ_DAP_AtomicReadReg32( (dev), (addr), (val), 0 ) ) + +#define SARR16( dev, addr, val) \ + CHK_ERROR( DRXJ_DAP_SCU_AtomicReadReg16( (dev), (addr), (val), 0 ) ) + +#define SAWR16( dev, addr, val) \ + CHK_ERROR( DRXJ_DAP_SCU_AtomicWriteReg16( (dev), (addr), (val), 0 ) ) + +/** +* This macro is used to create byte arrays for block writes. +* Block writes speed up I2C traffic between host and demod. +* The macro takes care of the required byte order in a 16 bits word. +* x -> lowbyte(x), highbyte(x) +*/ +#define DRXJ_16TO8( x ) ((u8_t) (((u16_t)x) &0xFF)), \ + ((u8_t)((((u16_t)x)>>8)&0xFF)) +/** +* This macro is used to convert byte array to 16 bit register value for block read. +* Block read speed up I2C traffic between host and demod. +* The macro takes care of the required byte order in a 16 bits word. +*/ +#define DRXJ_8TO16( x ) ((u16_t) (x[0] | (x[1] << 8))) + +/*============================================================================*/ +/*=== MISC DEFINES ===========================================================*/ +/*============================================================================*/ + +/*============================================================================*/ +/*=== HI COMMAND RELATED DEFINES =============================================*/ +/*============================================================================*/ + +/** +* \brief General maximum number of retries for ucode command interfaces +*/ +#define DRXJ_MAX_RETRIES (100) + +/*============================================================================*/ +/*=== STANDARD RELATED MACROS ================================================*/ +/*============================================================================*/ + +#define DRXJ_ISATVSTD( std ) ( ( std == DRX_STANDARD_PAL_SECAM_BG ) || \ + ( std == DRX_STANDARD_PAL_SECAM_DK ) || \ + ( std == DRX_STANDARD_PAL_SECAM_I ) || \ + ( std == DRX_STANDARD_PAL_SECAM_L ) || \ + ( std == DRX_STANDARD_PAL_SECAM_LP ) || \ + ( std == DRX_STANDARD_NTSC ) || \ + ( std == DRX_STANDARD_FM ) ) + +#define DRXJ_ISQAMSTD( std ) ( ( std == DRX_STANDARD_ITU_A ) || \ + ( std == DRX_STANDARD_ITU_B ) || \ + ( std == DRX_STANDARD_ITU_C ) || \ + ( std == DRX_STANDARD_ITU_D )) + +/*----------------------------------------------------------------------------- +STATIC VARIABLES +----------------------------------------------------------------------------*/ +DRXStatus_t DRXJ_Open ( pDRXDemodInstance_t demod ); +DRXStatus_t DRXJ_Close ( pDRXDemodInstance_t demod); +DRXStatus_t DRXJ_Ctrl ( pDRXDemodInstance_t demod, + DRXCtrlIndex_t ctrl, + void *ctrlData); + +/*----------------------------------------------------------------------------- +GLOBAL VARIABLES +----------------------------------------------------------------------------*/ +/* + * DRXJ DAP structures + */ + +static DRXStatus_t DRXJ_DAP_ReadBlock ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + u16_t datasize, + pu8_t data, + DRXflags_t flags); + +static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg8 ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t waddr, + DRXaddr_t raddr, + u8_t wdata, + pu8_t rdata); + +static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg16 ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t waddr, + DRXaddr_t raddr, + u16_t wdata, + pu16_t rdata); + +static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg32 ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t waddr, + DRXaddr_t raddr, + u32_t wdata, + pu32_t rdata); + +static DRXStatus_t DRXJ_DAP_ReadReg8 ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + pu8_t data, + DRXflags_t flags); + +static DRXStatus_t DRXJ_DAP_ReadReg16 ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + pu16_t data, + DRXflags_t flags); + +static DRXStatus_t DRXJ_DAP_ReadReg32 ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + pu32_t data, + DRXflags_t flags); + +static DRXStatus_t DRXJ_DAP_WriteBlock ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + u16_t datasize, + pu8_t data, + DRXflags_t flags); + +static DRXStatus_t DRXJ_DAP_WriteReg8 ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + u8_t data, + DRXflags_t flags); + +static DRXStatus_t DRXJ_DAP_WriteReg16 ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + u16_t data, + DRXflags_t flags); + +static DRXStatus_t DRXJ_DAP_WriteReg32 ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + u32_t data, + DRXflags_t flags); + +/* The version structure of this protocol implementation */ +char drxDapDRXJModuleName[] = "DRXJ Data Access Protocol"; +char drxDapDRXJVersionText[] = "0.0.0"; + +DRXVersion_t drxDapDRXJVersion = { + DRX_MODULE_DAP, /**< type identifier of the module */ + drxDapDRXJModuleName, /**< name or description of module */ + + 0, /**< major version number */ + 0, /**< minor version number */ + 0, /**< patch version number */ + drxDapDRXJVersionText /**< version as text string */ +}; + +/* The structure containing the protocol interface */ +DRXAccessFunc_t drxDapDRXJFunct_g = { + &drxDapDRXJVersion, + DRXJ_DAP_WriteBlock, /* Supported */ + DRXJ_DAP_ReadBlock, /* Supported */ + DRXJ_DAP_WriteReg8, /* Not supported */ + DRXJ_DAP_ReadReg8, /* Not supported */ + DRXJ_DAP_ReadModifyWriteReg8, /* Not supported */ + DRXJ_DAP_WriteReg16, /* Supported */ + DRXJ_DAP_ReadReg16, /* Supported */ + DRXJ_DAP_ReadModifyWriteReg16, /* Supported */ + DRXJ_DAP_WriteReg32, /* Supported */ + DRXJ_DAP_ReadReg32, /* Supported */ + DRXJ_DAP_ReadModifyWriteReg32, /* Not supported */ +}; + +/** +* /var DRXJ_Func_g +* /brief The driver functions of the drxj +*/ +DRXDemodFunc_t DRXJFunctions_g = +{ + DRXJ_TYPE_ID, + DRXJ_Open, + DRXJ_Close, + DRXJ_Ctrl +}; + +DRXJData_t DRXJData_g = +{ + FALSE, /* hasLNA : TRUE if LNA (aka PGA) present */ + FALSE, /* hasOOB : TRUE if OOB supported */ + FALSE, /* hasNTSC: TRUE if NTSC supported */ + FALSE, /* hasBTSC: TRUE if BTSC supported */ + FALSE, /* hasSMATX: TRUE if SMA_TX pin is available */ + FALSE, /* hasSMARX: TRUE if SMA_RX pin is available */ + FALSE, /* hasGPIO : TRUE if GPIO pin is available */ + FALSE, /* hasIRQN : TRUE if IRQN pin is available */ + 0, /* mfx A1/A2/A... */ + + /* tuner settings */ + FALSE, /* tuner mirrors RF signal */ + /* standard/channel settings */ + DRX_STANDARD_UNKNOWN, /* current standard */ + DRX_CONSTELLATION_AUTO, /* constellation */ + 0, /* frequency in KHz */ + DRX_BANDWIDTH_UNKNOWN, /* currBandwidth */ + DRX_MIRROR_NO, /* mirror */ + + /* signal quality information: */ + /* default values taken from the QAM Programming guide */ + /* fecBitsDesired should not be less than 4000000 */ + 4000000, /* fecBitsDesired */ + 5, /* fecVdPlen */ + 4, /* qamVdPrescale */ + 0xFFFF, /* qamVDPeriod */ + 204*8, /* fecRsPlen annex A */ + 1, /* fecRsPrescale */ + FEC_RS_MEASUREMENT_PERIOD,/* fecRsPeriod */ + TRUE, /* resetPktErrAcc */ + 0, /* pktErrAccStart */ + + /* HI configuration */ + 0, /* HICfgTimingDiv */ + 0, /* HICfgBridgeDelay */ + 0, /* HICfgWakeUpKey */ + 0, /* HICfgCtrl */ + 0, /* HICfgTimeout */ + /* UIO configuartion */ + DRX_UIO_MODE_DISABLE, /* uioSmaRxMode */ + DRX_UIO_MODE_DISABLE, /* uioSmaTxMode */ + DRX_UIO_MODE_DISABLE, /* uioASELMode */ + DRX_UIO_MODE_DISABLE, /* uioIRQNMode */ + /* FS setting */ + 0UL, /* iqmFsRateOfs */ + FALSE, /* posImage */ + /* RC setting */ + 0UL, /* iqmRcRateOfs */ + /* AUD information */ +/* FALSE, * flagSetAUDdone */ +/* FALSE, * detectedRDS */ +/* TRUE, * flagASDRequest */ +/* FALSE, * flagHDevClear */ +/* FALSE, * flagHDevSet */ +/* (u16_t) 0xFFF, * rdsLastCount */ + +/*#ifdef DRXJ_SPLIT_UCODE_UPLOAD + FALSE, * flagAudMcUploaded */ +/*#endif * DRXJ_SPLIT_UCODE_UPLOAD */ + /* ATV configuartion */ + 0UL, /* flags cfg changes */ + /* shadow of ATV_TOP_EQU0__A */ + {-5, + ATV_TOP_EQU0_EQU_C0_FM, + ATV_TOP_EQU0_EQU_C0_L, + ATV_TOP_EQU0_EQU_C0_LP, + ATV_TOP_EQU0_EQU_C0_BG, + ATV_TOP_EQU0_EQU_C0_DK, + ATV_TOP_EQU0_EQU_C0_I + }, + /* shadow of ATV_TOP_EQU1__A */ + {-50, + ATV_TOP_EQU1_EQU_C1_FM, + ATV_TOP_EQU1_EQU_C1_L, + ATV_TOP_EQU1_EQU_C1_LP, + ATV_TOP_EQU1_EQU_C1_BG, + ATV_TOP_EQU1_EQU_C1_DK, + ATV_TOP_EQU1_EQU_C1_I + }, + /* shadow of ATV_TOP_EQU2__A */ + {210, + ATV_TOP_EQU2_EQU_C2_FM, + ATV_TOP_EQU2_EQU_C2_L, + ATV_TOP_EQU2_EQU_C2_LP, + ATV_TOP_EQU2_EQU_C2_BG, + ATV_TOP_EQU2_EQU_C2_DK, + ATV_TOP_EQU2_EQU_C2_I + }, + /* shadow of ATV_TOP_EQU3__A */ + {-160, + ATV_TOP_EQU3_EQU_C3_FM, + ATV_TOP_EQU3_EQU_C3_L, + ATV_TOP_EQU3_EQU_C3_LP, + ATV_TOP_EQU3_EQU_C3_BG, + ATV_TOP_EQU3_EQU_C3_DK, + ATV_TOP_EQU3_EQU_C3_I + }, + FALSE, /* flag: TRUE=bypass */ + ATV_TOP_VID_PEAK__PRE, /* shadow of ATV_TOP_VID_PEAK__A */ + ATV_TOP_NOISE_TH__PRE, /* shadow of ATV_TOP_NOISE_TH__A */ + TRUE, /* flag CVBS ouput enable */ + FALSE, /* flag SIF ouput enable */ + DRXJ_SIF_ATTENUATION_0DB, /* current SIF att setting */ + { /* qamRfAgcCfg */ + DRX_STANDARD_ITU_B, /* standard */ + DRX_AGC_CTRL_AUTO, /* ctrlMode */ + 0, /* outputLevel */ + 0, /* minOutputLevel */ + 0xFFFF, /* maxOutputLevel */ + 0x0000, /* speed */ + 0x0000, /* top */ + 0x0000 /* c.o.c. */ + }, + { /* qamIfAgcCfg */ + DRX_STANDARD_ITU_B, /* standard */ + DRX_AGC_CTRL_AUTO, /* ctrlMode */ + 0, /* outputLevel */ + 0, /* minOutputLevel */ + 0xFFFF, /* maxOutputLevel */ + 0x0000, /* speed */ + 0x0000, /* top (don't care) */ + 0x0000 /* c.o.c. (don't care) */ + }, + { /* vsbRfAgcCfg */ + DRX_STANDARD_8VSB, /* standard */ + DRX_AGC_CTRL_AUTO, /* ctrlMode */ + 0, /* outputLevel */ + 0, /* minOutputLevel */ + 0xFFFF, /* maxOutputLevel */ + 0x0000, /* speed */ + 0x0000, /* top (don't care) */ + 0x0000 /* c.o.c. (don't care) */ + }, + { /* vsbIfAgcCfg */ + DRX_STANDARD_8VSB, /* standard */ + DRX_AGC_CTRL_AUTO, /* ctrlMode */ + 0, /* outputLevel */ + 0, /* minOutputLevel */ + 0xFFFF, /* maxOutputLevel */ + 0x0000, /* speed */ + 0x0000, /* top (don't care) */ + 0x0000 /* c.o.c. (don't care) */ + }, + 0, /* qamPgaCfg */ + 0, /* vsbPgaCfg */ + { /* qamPreSawCfg */ + DRX_STANDARD_ITU_B, /* standard */ + 0, /* reference */ + FALSE /* usePreSaw */ + }, + { /* vsbPreSawCfg */ + DRX_STANDARD_8VSB, /* standard */ + 0, /* reference */ + FALSE /* usePreSaw */ + }, + + /* Version information */ +#ifndef _CH_ + { + "01234567890", /* human readable version microcode */ + "01234567890" /* human readable version device specific code */ + }, + { + { /* DRXVersion_t for microcode */ + DRX_MODULE_UNKNOWN, + (char*)(NULL), + 0, + 0, + 0, + (char*)(NULL) + }, + { /* DRXVersion_t for device specific code */ + DRX_MODULE_UNKNOWN, + (char*)(NULL), + 0, + 0, + 0, + (char*)(NULL) + } + }, + { + { /* DRXVersionList_t for microcode */ + (pDRXVersion_t)(NULL), + (pDRXVersionList_t)(NULL) + }, + { /* DRXVersionList_t for device specific code */ + (pDRXVersion_t)(NULL), + (pDRXVersionList_t)(NULL) + } + }, +#endif + FALSE, /* smartAntInverted */ + /* Tracking filter setting for OOB */ + { + 12000, + 9300, + 6600, + 5280, + 3700, + 3000, + 2000, + 0 + }, + FALSE, /* oobPowerOn */ + 0, /* mpegTsStaticBitrate */ + FALSE, /* disableTEIhandling */ + FALSE, /* bitReverseMpegOutout */ + DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO, /* mpegOutputClockRate */ + DRXJ_MPEG_START_WIDTH_1CLKCYC, /* mpegStartWidth */ + + /* Pre SAW & Agc configuration for ATV */ + { + DRX_STANDARD_NTSC, /* standard */ + 7, /* reference */ + TRUE /* usePreSaw */ + }, + { /* ATV RF-AGC */ + DRX_STANDARD_NTSC, /* standard */ + DRX_AGC_CTRL_AUTO, /* ctrlMode */ + 0, /* outputLevel */ + 0, /* minOutputLevel (d.c.) */ + 0, /* maxOutputLevel (d.c.) */ + 3, /* speed */ + 9500, /* top */ + 4000 /* cut-off current */ + }, + { /* ATV IF-AGC */ + DRX_STANDARD_NTSC, /* standard */ + DRX_AGC_CTRL_AUTO, /* ctrlMode */ + 0, /* outputLevel */ + 0, /* minOutputLevel (d.c.) */ + 0, /* maxOutputLevel (d.c.) */ + 3, /* speed */ + 2400, /* top */ + 0 /* c.o.c. (d.c.) */ + }, + 140, /* ATV PGA config */ + 0, /* currSymbolRate */ + + FALSE, /* pdrSafeMode */ + SIO_PDR_GPIO_CFG__PRE, /* pdrSafeRestoreValGpio */ + SIO_PDR_VSYNC_CFG__PRE, /* pdrSafeRestoreValVSync */ + SIO_PDR_SMA_RX_CFG__PRE, /* pdrSafeRestoreValSmaRx */ + SIO_PDR_SMA_TX_CFG__PRE, /* pdrSafeRestoreValSmaTx */ + + 4, /* oobPreSaw */ + DRXJ_OOB_LO_POW_MINUS10DB, /* oobLoPow */ + { + FALSE /* audData, only first member */ + }, +}; + + +/** +* \var DRXJDefaultAddr_g +* \brief Default I2C address and device identifier. +*/ +I2CDeviceAddr_t DRXJDefaultAddr_g = { + DRXJ_DEF_I2C_ADDR, /* i2c address */ + DRXJ_DEF_DEMOD_DEV_ID /* device id */ +}; + +/** +* \var DRXJDefaultCommAttr_g +* \brief Default common attributes of a drxj demodulator instance. +*/ +DRXCommonAttr_t DRXJDefaultCommAttr_g = { + (pu8_t)NULL, /* ucode ptr */ + 0, /* ucode size */ + TRUE, /* ucode verify switch */ + { 0 }, /* version record */ + + 44000, /* IF in kHz in case no tuner instance is used */ + (151875-0), /* system clock frequency in kHz */ + 0, /* oscillator frequency kHz */ + 0, /* oscillator deviation in ppm, signed */ + FALSE, /* If TRUE mirror frequency spectrum */ + { + /* MPEG output configuration */ + TRUE, /* If TRUE, enable MPEG ouput */ + FALSE, /* If TRUE, insert RS byte */ + TRUE, /* If TRUE, parallel out otherwise serial */ + FALSE, /* If TRUE, invert DATA signals */ + FALSE, /* If TRUE, invert ERR signal */ + FALSE, /* If TRUE, invert STR signals */ + FALSE, /* If TRUE, invert VAL signals */ + FALSE, /* If TRUE, invert CLK signals */ + TRUE, /* If TRUE, static MPEG clockrate will + be used, otherwise clockrate will + adapt to the bitrate of the TS */ + 19392658UL, /* Maximum bitrate in b/s in case + static clockrate is selected */ + DRX_MPEG_STR_WIDTH_1 /* MPEG Start width in clock cycles */ + }, + /* Initilisations below can be ommited, they require no user input and + are initialy 0, NULL or FALSE. The compiler will initialize them to these + values when ommited. */ + FALSE, /* isOpened */ + + /* SCAN */ + NULL, /* no scan params yet */ + 0, /* current scan index */ + 0, /* next scan frequency */ + FALSE, /* scan ready flag */ + 0, /* max channels to scan */ + 0, /* nr of channels scanned */ + NULL, /* default scan function */ + NULL, /* default context pointer */ + 0, /* millisec to wait for demod lock */ + DRXJ_DEMOD_LOCK, /* desired lock */ + FALSE, + + /* Power management */ + DRX_POWER_UP, + + /* Tuner */ + 1, /* nr of I2C port to wich tuner is */ + 0L, /* minimum RF input frequency, in kHz */ + 0L, /* maximum RF input frequency, in kHz */ + FALSE, /* Rf Agc Polarity */ + FALSE, /* If Agc Polarity */ + FALSE, /* tuner slow mode */ + + + { /* current channel (all 0) */ + 0UL /* channel.frequency */ + }, + DRX_STANDARD_UNKNOWN, /* current standard */ + DRX_STANDARD_UNKNOWN, /* previous standard */ + DRX_STANDARD_UNKNOWN, /* diCacheStandard */ + FALSE, /* useBootloader */ + 0UL, /* capabilities */ + 0 /* mfx */ + +}; + +/** +* \var DRXJDefaultDemod_g +* \brief Default drxj demodulator instance. +*/ +DRXDemodInstance_t DRXJDefaultDemod_g = { + &DRXJFunctions_g, /* demod functions */ + &DRXJ_DAP, /* data access protocol functions */ + NULL, /* tuner instance */ + &DRXJDefaultAddr_g, /* i2c address & device id */ + &DRXJDefaultCommAttr_g, /* demod common attributes */ + &DRXJData_g /* demod device specific attributes */ +}; + +/** +* \brief Default audio data structure for DRK demodulator instance. +* +* This structure is DRXK specific. +* +*/ +DRXAudData_t DRXJDefaultAudData_g = +{ + FALSE, /* audioIsActive */ + DRX_AUD_STANDARD_AUTO, /* audioStandard */ + + /* i2sdata */ + { + FALSE, /* outputEnable */ + 48000, /* frequency */ + DRX_I2S_MODE_MASTER, /* mode */ + DRX_I2S_WORDLENGTH_32, /* wordLength */ + DRX_I2S_POLARITY_RIGHT, /* polarity */ + DRX_I2S_FORMAT_WS_WITH_DATA /* format */ + }, + /* volume */ + { + TRUE, /* mute; */ + 0, /* volume */ + DRX_AUD_AVC_OFF , /* avcMode */ + 0, /* avcRefLevel */ + DRX_AUD_AVC_MAX_GAIN_12DB, /* avcMaxGain */ + DRX_AUD_AVC_MAX_ATTEN_24DB, /* avcMaxAtten */ + 0, /* strengthLeft */ + 0 /* strengthRight */ + }, + DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON,/* autoSound */ + /* assThresholds */ + { + 440, /* A2 */ + 12, /* BTSC */ + 700, /* NICAM */ + }, + /* carrier */ + { + /* a */ + { + 42, /* thres */ + DRX_NO_CARRIER_NOISE, /* opt */ + 0, /* shift */ + 0 /* dco */ + }, + /* b */ + { + 42, /* thres */ + DRX_NO_CARRIER_MUTE, /* opt */ + 0, /* shift */ + 0 /* dco */ + }, + + }, + /* mixer */ + { + DRX_AUD_SRC_STEREO_OR_A, /* sourceI2S */ + DRX_AUD_I2S_MATRIX_STEREO, /* matrixI2S */ + DRX_AUD_FM_MATRIX_SOUND_A /* matrixFm */ + }, + DRX_AUD_DEVIATION_NORMAL, /* deviation */ + DRX_AUD_AVSYNC_OFF, /* avSync */ + + /* prescale */ + { + DRX_AUD_MAX_FM_DEVIATION, /* fmDeviation */ + DRX_AUD_MAX_NICAM_PRESCALE /* nicamGain */ + }, + DRX_AUD_FM_DEEMPH_75US, /* deemph */ + DRX_BTSC_STEREO, /* btscDetect */ + 0, /* rdsDataCounter */ + FALSE /* rdsDataPresent */ +}; + + +/*----------------------------------------------------------------------------- +STRUCTURES +----------------------------------------------------------------------------*/ +typedef struct { + u16_t eqMSE; + u8_t eqMode; + u8_t eqCtrl; + u8_t eqStat; +} DRXJEQStat_t, *pDRXJEQStat_t; + +/* HI command */ +typedef struct { + u16_t cmd; + u16_t param1; + u16_t param2; + u16_t param3; + u16_t param4; + u16_t param5; + u16_t param6; +} DRXJHiCmd_t, *pDRXJHiCmd_t; + +#ifdef DRXJ_SPLIT_UCODE_UPLOAD +/*============================================================================*/ +/*=== MICROCODE RELATED STRUCTURES ===========================================*/ +/*============================================================================*/ + +typedef struct { + u32_t addr; + u16_t size; + u16_t flags; /* bit[15..2]=reserved, + bit[1]= compression on/off + bit[0]= CRC on/off */ + u16_t CRC; +} DRXUCodeBlockHdr_t, *pDRXUCodeBlockHdr_t; +#endif /* DRXJ_SPLIT_UCODE_UPLOAD */ + +/*----------------------------------------------------------------------------- +FUNCTIONS +----------------------------------------------------------------------------*/ +/* Some prototypes */ +static DRXStatus_t +HICommand(const pI2CDeviceAddr_t devAddr, + const pDRXJHiCmd_t cmd, + pu16_t result); + +static DRXStatus_t +CtrlLockStatus( pDRXDemodInstance_t demod, + pDRXLockStatus_t lockStat ); + +static DRXStatus_t +CtrlPowerMode( pDRXDemodInstance_t demod, + pDRXPowerMode_t mode ); + +static DRXStatus_t +PowerDownAud( pDRXDemodInstance_t demod ); + +#ifndef DRXJ_DIGITAL_ONLY +static DRXStatus_t +PowerUpAud( pDRXDemodInstance_t demod, + Bool_t setStandard ); +#endif + +static DRXStatus_t +AUDCtrlSetStandard ( pDRXDemodInstance_t demod, + pDRXAudStandard_t standard ); + +static DRXStatus_t +CtrlSetCfgPreSaw ( pDRXDemodInstance_t demod, pDRXJCfgPreSaw_t preSaw ); + +static DRXStatus_t +CtrlSetCfgAfeGain ( pDRXDemodInstance_t demod, pDRXJCfgAfeGain_t afeGain ); + +#ifdef DRXJ_SPLIT_UCODE_UPLOAD +static DRXStatus_t +CtrlUCodeUpload( pDRXDemodInstance_t demod, + pDRXUCodeInfo_t mcInfo, + DRXUCodeAction_t action, + Bool_t audioMCUpload ); +#endif /* DRXJ_SPLIT_UCODE_UPLOAD */ + +/*============================================================================*/ +/*============================================================================*/ +/*== HELPER FUNCTIONS ==*/ +/*============================================================================*/ +/*============================================================================*/ + +/** +* \fn void Mult32(u32_t a, u32_t b, pu32_t h, pu32_t l) +* \brief 32bitsx32bits signed multiplication +* \param a 32 bits multiplicant, typecast from signed to unisgned +* \param b 32 bits multiplier, typecast from signed to unisgned +* \param h pointer to high part 64 bits result, typecast from signed to unisgned +* \param l pointer to low part 64 bits result +* +* For the 2n+n addition a + b: +* if a >= 0, then h += 0 (sign extension = 0) +* but if a < 0, then h += 2^n-1 ==> h -= 1. +* +* Also, if a + b < 2^n, then a + b >= a && a + b >= b +* but if a + b >= 2^n, then R = a + b - 2^n, +* and because a < 2^n && b < 2*n ==> R < a && R < b. +* Therefore, to detect overflow, simply compare the addition result with +* one of the operands; if the result is smaller, overflow has occurred and +* h must be incremented. +* +* Booth multiplication uses additions and subtractions to reduce the number +* of iterations. This is done by taking three subsequent bits abc and calculating +* the following multiplication factor: -2a + b + c. This factor is multiplied +* by the second operand and added to the result. Next, the first operand is +* shifted two bits (hence one of the three bits is reused) and the process +* repeated. The last iteration has only two bits left, but we simply add +* a zero to the end. +* +* Hence: (n=4) +* 1 * a = 0 * 4a + 1 * a +* 2 * a = 1 * 4a - 2 * a +* 3 * a = 1 * 4a - 1 * a +* -1 * a = 0 * 4a - 1 * a +* -5 * a = -1 * 4a - 1 * a +* +* etc. +* +* Note that the function is type size independent. Any unsigned integer type +* can be substituted for booth_t. +* +*/ + +#define DRX_IS_BOOTH_NEGATIVE(__a) (((__a) & (1 << (sizeof (u32_t) * 8 - 1))) != 0) + +static void Mult32(u32_t a, u32_t b, pu32_t h, pu32_t l) +{ + unsigned int i; + *h = *l = 0; + + /* n/2 iterations; shift operand a left two bits after each iteration. */ + /* This automatically appends a zero to the operand for the last iteration. */ + for (i = 0; i < sizeof (a) * 8; i += 2, a = a << 2) + { + /* Shift result left two bits */ + *h = (*h << 2) + (*l >> (sizeof (*l) * 8 - 2)); + *l = (*l << 2); + + /* Take the first three bits of operand a for the Booth conversion: */ + /* 0, 7: do nothing */ + /* 1, 2: add b */ + /* 3 : add 2b */ + /* 4 : subtract 2b */ + /* 5, 6: subtract b */ + switch (a >> (sizeof (a) * 8 - 3)) + { + case 3: + *l += b; + *h = *h - DRX_IS_BOOTH_NEGATIVE (b) + (*l < b); + case 1: + case 2: + *l += b; + *h = *h - DRX_IS_BOOTH_NEGATIVE (b) + (*l < b); + break; + case 4: + *l -= b; + *h = *h - !DRX_IS_BOOTH_NEGATIVE (b) + !b + (*l < ((u32_t) (-((s32_t)b))) ); + case 5: + case 6: + *l -= b; + *h = *h - !DRX_IS_BOOTH_NEGATIVE (b) + !b + (*l < ((u32_t) (-((s32_t)b))) ); + break; + } + } +} + +/*============================================================================*/ + +/* +* \fn u32_t Frac28(u32_t N, u32_t D) +* \brief Compute: (1<<28)*N/D +* \param N 32 bits +* \param D 32 bits +* \return (1<<28)*N/D +* This function is used to avoid floating-point calculations as they may +* not be present on the target platform. + +* Frac28 performs an unsigned 28/28 bits division to 32-bit fixed point +* fraction used for setting the Frequency Shifter registers. +* N and D can hold numbers up to width: 28-bits. +* The 4 bits integer part and the 28 bits fractional part are calculated. + +* Usage condition: ((1<<28)*n)/d < ((1<<32)-1) => (n/d) < 15.999 + +* N: 0...(1<<28)-1 = 268435454 +* D: 0...(1<<28)-1 +* Q: 0...(1<<32)-1 +*/ +static u32_t Frac28(u32_t N, u32_t D) +{ + int i=0; + u32_t Q1=0; + u32_t R0=0; + + R0 = (N%D)<<4; /* 32-28 == 4 shifts possible at max */ + Q1 = N/D; /* integer part, only the 4 least significant bits + will be visible in the result */ + + /* division using radix 16, 7 nibbles in the result */ + for (i=0; i<7; i++) { + Q1 = (Q1 << 4) | R0/D; + R0 = (R0%D)<<4; + } + /* rounding */ + if ((R0>>3) >= D) Q1++; + + return Q1; +} + +/** +* \fn u32_t Log10Times100( u32_t x) +* \brief Compute: 100*log10(x) +* \param x 32 bits +* \return 100*log10(x) +* +* 100*log10(x) +* = 100*(log2(x)/log2(10))) +* = (100*(2^15)*log2(x))/((2^15)*log2(10)) +* = ((200*(2^15)*log2(x))/((2^15)*log2(10)))/2 +* = ((200*(2^15)*(log2(x/y)+log2(y)))/((2^15)*log2(10)))/2 +* = ((200*(2^15)*log2(x/y))+(200*(2^15)*log2(y)))/((2^15)*log2(10)))/2 +* +* where y = 2^k and 1<= (x/y) < 2 +*/ + +static u32_t Log10Times100( u32_t x) +{ + static const u8_t scale=15; + static const u8_t indexWidth=5; + /* + log2lut[n] = (1<0 ; k--) + { + if (x & (((u32_t)1)<>= 1; + } + } + /* + Now x has binary point between bit[scale] and bit[scale-1] + and 1.0 <= x < 2.0 */ + + /* correction for divison: log(x) = log(x/y)+log(y) */ + y = k * ( ( ((u32_t)1) << scale ) * 200 ); + + /* remove integer part */ + x &= ((((u32_t)1) << scale)-1); + /* get index */ + i = (u8_t) (x >> (scale -indexWidth)); + /* compute delta (x-a) */ + d = x & ((((u32_t)1) << (scale-indexWidth))-1); + /* compute log, multiplication ( d* (.. )) must be within range ! */ + y += log2lut[i] + (( d*( log2lut[i+1]-log2lut[i] ))>>(scale-indexWidth)); + /* Conver to log10() */ + y /= 108853; /* (log2(10) << scale) */ + r = (y>>1); + /* rounding */ + if (y&((u32_t)1)) r++; + + return (r); + +} + +/** +* \fn u32_t FracTimes1e6( u16_t N, u32_t D) +* \brief Compute: (N/D) * 1000000. +* \param N nominator 16-bits. +* \param D denominator 32-bits. +* \return u32_t +* \retval ((N/D) * 1000000), 32 bits +* +* No check on D=0! +*/ +static u32_t FracTimes1e6( u32_t N, u32_t D) +{ + u32_t remainder = 0; + u32_t frac = 0; + + /* + frac = (N * 1000000) / D + To let it fit in a 32 bits computation: + frac = (N * (1000000 >> 4)) / (D >> 4) + This would result in a problem in case D < 16 (div by 0). + So we do it more elaborate as shown below. + */ + frac = ( ((u32_t)N) * (1000000 >> 4) ) / D ; + frac <<= 4 ; + remainder = ( ((u32_t)N) * (1000000 >> 4) ) % D ; + remainder <<= 4; + frac += remainder / D; + remainder = remainder % D ; + if( (remainder * 2) > D ) + { + frac++; + } + + return ( frac ); +} + +/*============================================================================*/ + +/** +* \brief Compute: 100 * 10^( GdB / 200 ). +* \param u32_t GdB Gain in 0.1dB +* \return u32_t Gainfactor in 0.01 resolution +* +*/ +static u32_t dB2LinTimes100( u32_t GdB ) +{ + u32_t result = 0; + u32_t nr6dBSteps = 0; + u32_t remainder = 0; + u32_t remainderFac = 0; + + /* start with factors 2 (6.02dB) */ + nr6dBSteps = GdB * 1000UL / 60206UL; + if ( nr6dBSteps > 17 ) + { + /* Result max overflow if > log2( maxu32 / 2e4 ) ~= 17.7 */ + return MAX_U32; + } + result = (1< N ) + { + frac = 0; + remainder = N; + } + else + { + remainder = 0; + frac = N; + while ( bitCnt-- > 0 ) + { + remainder <<= 1; + remainder |= ( ( frac & 0x80000000 ) >> 31 ); + frac <<= 1; + if ( remainder < D ) + { + frac &= 0xFFFFFFFE; + } + else + { + remainder -= D; + frac |= 0x1; + } + } + + /* result correction if needed */ + if ( ( RC == FRAC_CEIL ) && ( remainder != 0 ) ) + { + /* ceil the result */ + /*(remainder is not zero -> value behind decimal point exists) */ + frac++; + } + if ( ( RC == FRAC_ROUND ) && ( remainder >= D>>1 ) ) + { + /* remainder is bigger from D/2 -> round the result */ + frac++; + } + } + + return ( frac ); +} +#endif + +#ifdef DRXJ_SPLIT_UCODE_UPLOAD +/*============================================================================*/ + +/** +* \fn u16_t UCodeRead16( pu8_t addr) +* \brief Read a 16 bits word, expect big endian data. +* \return u16_t The data read. +*/ +static u16_t +UCodeRead16( pu8_t addr) +{ + /* Works fo any host processor */ + + u16_t word=0; + + word = ((u16_t)addr[0]); + word <<= 8; + word |=((u16_t)addr[1]); + + return ( word ); +} + +/*============================================================================*/ + +/** +* \fn u32_t UCodeRead32( pu8_t addr) +* \brief Read a 32 bits word, expect big endian data. +* \return u32_t The data read. +*/ +static u32_t +UCodeRead32( pu8_t addr) +{ + /* Works fo any host processor */ + + u32_t word=0; + + word = ((u16_t)addr[0]); + word <<= 8; + word |= ((u16_t)addr[1]); + word <<= 8; + word |= ((u16_t)addr[2]); + word <<= 8; + word |= ((u16_t)addr[3]); + + return ( word ); +} + +/*============================================================================*/ + +/** +* \fn u16_t UCodeComputeCRC (pu8_t blockData, u16_t nrWords) +* \brief Compute CRC of block of microcode data. +* \param blockData Pointer to microcode data. +* \param nrWords Size of microcode block (number of 16 bits words). +* \return u16_t The computed CRC residu. +*/ +static u16_t +UCodeComputeCRC (pu8_t blockData, u16_t nrWords) +{ + u16_t i = 0; + u16_t j = 0; + u32_t CRCWord=0; + u32_t carry=0; + + while (i < nrWords) { + CRCWord |= (u32_t) UCodeRead16(blockData); + for (j = 0; j < 16; j++) + { + CRCWord <<= 1; + if (carry != 0) + CRCWord ^= 0x80050000UL; + carry = CRCWord & 0x80000000UL; + } + i++; + blockData+=(sizeof(u16_t)); + } + return ((u16_t) (CRCWord >> 16)); +} +#endif /* DRXJ_SPLIT_UCODE_UPLOAD */ + +/** +* \brief Values for NICAM prescaler gain. Computed from dB to integer +* and rounded. For calc used formula: 16*10^(prescaleGain[dB]/20). +* +*/ +static const u16_t NicamPrescTableVal[43] = { 1,1,1,1,2,2,2,2,3,3,3,4,4, + 5,5,6,6,7,8,9,10,11,13,14,16, + 18,20,23,25,28,32,36,40,45, + 51,57,64,71,80,90,101,113,127 + }; + +/*============================================================================*/ +/*== END HELPER FUNCTIONS ==*/ +/*============================================================================*/ + + +/*============================================================================*/ +/*============================================================================*/ +/*== DRXJ DAP FUNCTIONS ==*/ +/*============================================================================*/ +/*============================================================================*/ + +/* + This layer takes care of some device specific register access protocols: + -conversion to short address format + -access to audio block + This layer is placed between the drx_dap_fasi and the rest of the drxj + specific implementation. This layer can use address map knowledge whereas + dap_fasi may not use memory map knowledge. + + * For audio currently only 16 bits read and write register access is + supported. More is not needed. RMW and 32 or 8 bit access on audio + registers will have undefined behaviour. Flags (RMW, CRC reset, broadcast + single/multi master) will be ignored. + + + TODO: check ignoring single/multimaster is ok for AUD access ? +*/ + +#define DRXJ_ISAUDWRITE( addr ) (((((addr)>>16)&1)==1)?TRUE:FALSE) +#define DRXJ_DAP_AUDTRIF_TIMEOUT 80 /* millisec */ +/*============================================================================*/ + +/** +* \fn Bool_t IsHandledByAudTrIf( DRXaddr_t addr ) +* \brief Check if this address is handled by the audio token ring interface. +* \param addr +* \return Bool_t +* \retval TRUE Yes, handled by audio token ring interface +* \retval FALSE No, not handled by audio token ring interface +* +*/ +static +Bool_t IsHandledByAudTrIf( DRXaddr_t addr ) +{ + Bool_t retval = FALSE; + + if ( (DRXDAP_FASI_ADDR2BLOCK( addr ) == 4) && + ( DRXDAP_FASI_ADDR2BANK( addr) > 1 ) && + ( DRXDAP_FASI_ADDR2BANK( addr) < 6 ) ) + { + retval=TRUE; + } + + return (retval); +} + +/*============================================================================*/ + +static DRXStatus_t DRXJ_DAP_ReadBlock ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + u16_t datasize, + pu8_t data, + DRXflags_t flags) +{ + return drxDapFASIFunct_g.readBlockFunc( devAddr, + addr, + datasize, + data, + flags); +} + +/*============================================================================*/ + +static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg8 ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t waddr, + DRXaddr_t raddr, + u8_t wdata, + pu8_t rdata) +{ + return drxDapFASIFunct_g.readModifyWriteReg8Func( devAddr, + waddr, + raddr, + wdata, + rdata); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t DRXJ_DAP_RMWriteReg16Short +* \brief Read modify write 16 bits audio register using short format only. +* \param devAddr +* \param waddr Address to write to +* \param raddr Address to read from (usually SIO_HI_RA_RAM_S0_RMWBUF__A) +* \param wdata Data to write +* \param rdata Buffer for data to read +* \return DRXStatus_t +* \retval DRX_STS_OK Succes +* \retval DRX_STS_ERROR Timeout, I2C error, illegal bank +* +* 16 bits register read modify write access using short addressing format only. +* Requires knowledge of the registermap, thus device dependent. +* Using DAP FASI directly to avoid endless recursion of RMWs to audio registers. +* +*/ + +/* TODO correct define should be #if ( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 ) + See comments DRXJ_DAP_ReadModifyWriteReg16 */ +#if ( DRXDAPFASI_LONG_ADDR_ALLOWED == 0 ) +static DRXStatus_t DRXJ_DAP_RMWriteReg16Short ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t waddr, + DRXaddr_t raddr, + u16_t wdata, + pu16_t rdata) +{ + DRXStatus_t rc; + + if (rdata == NULL) + { + return DRX_STS_INVALID_ARG; + } + + /* Set RMW flag */ + rc = drxDapFASIFunct_g.writeReg16Func (devAddr, + SIO_HI_RA_RAM_S0_FLG_ACC__A, + SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__M, + 0x0000); + if (rc == DRX_STS_OK) + { + /* Write new data: triggers RMW */ + rc = drxDapFASIFunct_g.writeReg16Func (devAddr, waddr, wdata, 0x0000 ); + } + if (rc == DRX_STS_OK) + { + /* Read old data */ + rc = drxDapFASIFunct_g.readReg16Func (devAddr, raddr, rdata, 0x0000 ); + } + if (rc == DRX_STS_OK) + { + /* Reset RMW flag */ + rc = drxDapFASIFunct_g.writeReg16Func (devAddr, + SIO_HI_RA_RAM_S0_FLG_ACC__A, + 0, + 0x0000); + } + + return rc; +} +#endif + +/*============================================================================*/ + +static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg16 ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t waddr, + DRXaddr_t raddr, + u16_t wdata, + pu16_t rdata) +{ + /* TODO: correct short/long addressing format decision, + now long format has higher prio then short because short also + needs virt bnks (not impl yet) for certain audio registers */ +#if ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 ) + return drxDapFASIFunct_g.readModifyWriteReg16Func( devAddr, + waddr, + raddr, + wdata, + rdata); +#else + return DRXJ_DAP_RMWriteReg16Short( devAddr, + waddr, + raddr, + wdata, + rdata); +#endif +} + +/*============================================================================*/ + +static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg32 ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t waddr, + DRXaddr_t raddr, + u32_t wdata, + pu32_t rdata) +{ + return drxDapFASIFunct_g.readModifyWriteReg32Func( devAddr, + waddr, + raddr, + wdata, + rdata); +} + +/*============================================================================*/ + +static DRXStatus_t DRXJ_DAP_ReadReg8 ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + pu8_t data, + DRXflags_t flags) +{ + return drxDapFASIFunct_g.readReg8Func( devAddr, + addr, + data, + flags); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t DRXJ_DAP_ReadAudReg16 +* \brief Read 16 bits audio register +* \param devAddr +* \param addr +* \param data +* \return DRXStatus_t +* \retval DRX_STS_OK Succes +* \retval DRX_STS_ERROR Timeout, I2C error, illegal bank +* +* 16 bits register read access via audio token ring interface. +* +*/ +static DRXStatus_t DRXJ_DAP_ReadAudReg16 ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + pu16_t data) +{ + u32_t startTimer = 0; + u32_t currentTimer = 0; + u32_t deltaTimer = 0; + u16_t trStatus = 0; + DRXStatus_t stat = DRX_STS_ERROR; + + /* No read possible for bank 3, return with error */ + if ( DRXDAP_FASI_ADDR2BANK(addr) == 3 ) + { + stat=DRX_STS_INVALID_ARG; + } else { + const DRXaddr_t writeBit = ((DRXaddr_t)1)<<16; + + /* Force reset write bit */ + addr &= (~writeBit); + + /* Set up read */ + startTimer = DRXBSP_HST_Clock(); + do { + /* RMW to aud TR IF until request is granted or timeout */ + stat = DRXJ_DAP_ReadModifyWriteReg16( devAddr, + addr, + SIO_HI_RA_RAM_S0_RMWBUF__A, + 0x0000, + &trStatus); + + if ( stat != DRX_STS_OK ) + { + break; + }; + + currentTimer = DRXBSP_HST_Clock(); + deltaTimer = currentTimer - startTimer; + if ( deltaTimer > DRXJ_DAP_AUDTRIF_TIMEOUT ) + { + stat = DRX_STS_ERROR; + break; + }; + + } while ( ( ( trStatus & AUD_TOP_TR_CTR_FIFO_LOCK__M ) == + AUD_TOP_TR_CTR_FIFO_LOCK_LOCKED ) || + ( ( trStatus & AUD_TOP_TR_CTR_FIFO_FULL__M ) == + AUD_TOP_TR_CTR_FIFO_FULL_FULL ) ); + } /* if ( DRXDAP_FASI_ADDR2BANK(addr)!=3 ) */ + + /* Wait for read ready status or timeout */ + if ( stat == DRX_STS_OK ) + { + startTimer = DRXBSP_HST_Clock(); + + while ( ( trStatus & AUD_TOP_TR_CTR_FIFO_RD_RDY__M) != + AUD_TOP_TR_CTR_FIFO_RD_RDY_READY) + { + stat = DRXJ_DAP_ReadReg16( devAddr, + AUD_TOP_TR_CTR__A, + &trStatus, + 0x0000); + if ( stat != DRX_STS_OK ) + { + break; + }; + + currentTimer = DRXBSP_HST_Clock(); + deltaTimer = currentTimer - startTimer; + if ( deltaTimer > DRXJ_DAP_AUDTRIF_TIMEOUT ) + { + stat = DRX_STS_ERROR; + break; + }; + } /* while ( ... ) */ + } /* if { stat == DRX_STS_OK ) */ + + /* Read value */ + if ( stat == DRX_STS_OK ) + { + stat = DRXJ_DAP_ReadModifyWriteReg16( devAddr, + AUD_TOP_TR_RD_REG__A, + SIO_HI_RA_RAM_S0_RMWBUF__A, + 0x0000, + data); + } /* if { stat == DRX_STS_OK ) */ + + return stat; +} + +/*============================================================================*/ + +static DRXStatus_t DRXJ_DAP_ReadReg16 ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + pu16_t data, + DRXflags_t flags) +{ + DRXStatus_t stat = DRX_STS_ERROR; + + /* Check param */ + if ( ( devAddr == NULL ) || ( data == NULL ) ) + { + return DRX_STS_INVALID_ARG; + } + + if ( IsHandledByAudTrIf(addr) ) + { + stat = DRXJ_DAP_ReadAudReg16 (devAddr, + addr, + data); + } else { + stat = drxDapFASIFunct_g.readReg16Func( devAddr, + addr, + data, + flags); + } + + return stat; +} + +/*============================================================================*/ + +static DRXStatus_t DRXJ_DAP_ReadReg32 ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + pu32_t data, + DRXflags_t flags) +{ + return drxDapFASIFunct_g.readReg32Func( devAddr, + addr, + data, + flags); +} + +/*============================================================================*/ + +static DRXStatus_t DRXJ_DAP_WriteBlock ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + u16_t datasize, + pu8_t data, + DRXflags_t flags) +{ + return drxDapFASIFunct_g.writeBlockFunc( devAddr, + addr, + datasize, + data, + flags); +} + +/*============================================================================*/ + +static DRXStatus_t DRXJ_DAP_WriteReg8 ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + u8_t data, + DRXflags_t flags) +{ + return drxDapFASIFunct_g.writeReg8Func( devAddr, + addr, + data, + flags); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t DRXJ_DAP_WriteAudReg16 +* \brief Write 16 bits audio register +* \param devAddr +* \param addr +* \param data +* \return DRXStatus_t +* \retval DRX_STS_OK Succes +* \retval DRX_STS_ERROR Timeout, I2C error, illegal bank +* +* 16 bits register write access via audio token ring interface. +* +*/ +static DRXStatus_t DRXJ_DAP_WriteAudReg16 ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + u16_t data) +{ + DRXStatus_t stat = DRX_STS_ERROR; + + /* No write possible for bank 2, return with error */ + if ( DRXDAP_FASI_ADDR2BANK(addr) == 2 ) + { + stat=DRX_STS_INVALID_ARG; + } else { + u32_t startTimer = 0; + u32_t currentTimer = 0; + u32_t deltaTimer = 0; + u16_t trStatus = 0; + const DRXaddr_t writeBit = ((DRXaddr_t)1)<<16; + + /* Force write bit */ + addr |= writeBit; + startTimer = DRXBSP_HST_Clock(); + do { + /* RMW to aud TR IF until request is granted or timeout */ + stat = DRXJ_DAP_ReadModifyWriteReg16( devAddr, + addr, + SIO_HI_RA_RAM_S0_RMWBUF__A, + data, + &trStatus); + if ( stat != DRX_STS_OK ) + { + break; + }; + + currentTimer = DRXBSP_HST_Clock(); + deltaTimer = currentTimer - startTimer; + if ( deltaTimer > DRXJ_DAP_AUDTRIF_TIMEOUT ) + { + stat = DRX_STS_ERROR; + break; + }; + + } while ( ( ( trStatus & AUD_TOP_TR_CTR_FIFO_LOCK__M ) == + AUD_TOP_TR_CTR_FIFO_LOCK_LOCKED ) || + ( ( trStatus & AUD_TOP_TR_CTR_FIFO_FULL__M ) == + AUD_TOP_TR_CTR_FIFO_FULL_FULL ) ); + + } /* if ( DRXDAP_FASI_ADDR2BANK(addr)!=2 ) */ + + return stat; +} + +/*============================================================================*/ + +static DRXStatus_t DRXJ_DAP_WriteReg16 ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + u16_t data, + DRXflags_t flags) +{ + DRXStatus_t stat=DRX_STS_ERROR; + + /* Check param */ + if ( devAddr == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + + if ( IsHandledByAudTrIf(addr) ) + { + stat = DRXJ_DAP_WriteAudReg16 (devAddr, + addr, + data); + } else { + stat = drxDapFASIFunct_g.writeReg16Func( devAddr, + addr, + data, + flags); + } + + return stat; +} + +/*============================================================================*/ + +static DRXStatus_t DRXJ_DAP_WriteReg32 ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + u32_t data, + DRXflags_t flags) +{ + return drxDapFASIFunct_g.writeReg32Func( devAddr, + addr, + data, + flags); +} + +/*============================================================================*/ + +/* Free data ram in SIO HI */ +#define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040 +#define SIO_HI_RA_RAM_USR_END__A 0x420060 + +#define DRXJ_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A) +#define DRXJ_HI_ATOMIC_BUF_END (SIO_HI_RA_RAM_USR_BEGIN__A + 7) +#define DRXJ_HI_ATOMIC_READ SIO_HI_RA_RAM_PAR_3_ACP_RW_READ +#define DRXJ_HI_ATOMIC_WRITE SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE + +/** +* \fn DRXStatus_t DRXJ_DAP_AtomicReadWriteBlock() +* \brief Basic access routine for atomic read or write access +* \param devAddr pointer to i2c dev address +* \param addr destination/source address +* \param datasize size of data buffer in bytes +* \param data pointer to data buffer +* \return DRXStatus_t +* \retval DRX_STS_OK Succes +* \retval DRX_STS_ERROR Timeout, I2C error, illegal bank +* +*/ +static +DRXStatus_t DRXJ_DAP_AtomicReadWriteBlock ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + u16_t datasize, + pu8_t data, + Bool_t readFlag) +{ + DRXJHiCmd_t hiCmd; + + u16_t word; + u16_t dummy=0; + u16_t i=0; + + /* Parameter check */ + if ( ( data == NULL ) || + ( devAddr == NULL ) || + ( (datasize%2)!= 0 ) || + ( (datasize/2) > 8 ) + ) + { + return (DRX_STS_INVALID_ARG); + } + + /* Set up HI parameters to read or write n bytes */ + hiCmd.cmd = SIO_HI_RA_RAM_CMD_ATOMIC_COPY; + hiCmd.param1 = + (u16_t)(( DRXDAP_FASI_ADDR2BLOCK( DRXJ_HI_ATOMIC_BUF_START ) << 6 ) + + DRXDAP_FASI_ADDR2BANK( DRXJ_HI_ATOMIC_BUF_START ) ); + hiCmd.param2 = (u16_t)DRXDAP_FASI_ADDR2OFFSET( DRXJ_HI_ATOMIC_BUF_START ); + hiCmd.param3 = (u16_t)((datasize/2) - 1); + if ( readFlag == FALSE ) + { + hiCmd.param3 |= DRXJ_HI_ATOMIC_WRITE; + } else { + hiCmd.param3 |= DRXJ_HI_ATOMIC_READ; + } + hiCmd.param4 = (u16_t) ( ( DRXDAP_FASI_ADDR2BLOCK(addr) << 6 ) + + DRXDAP_FASI_ADDR2BANK(addr) ); + hiCmd.param5 = (u16_t)DRXDAP_FASI_ADDR2OFFSET(addr); + + if ( readFlag == FALSE ) + { + /* write data to buffer */ + for (i = 0; i < (datasize/2); i++) + { + + + word = ((u16_t)data[2*i]); + word += (((u16_t)data[(2*i)+1])<<8); + DRXJ_DAP_WriteReg16 (devAddr, (DRXJ_HI_ATOMIC_BUF_START + i), word, 0); + } + } + + CHK_ERROR( HICommand( devAddr, &hiCmd, &dummy) ); + + if ( readFlag == TRUE ) + { + /* read data from buffer */ + for (i = 0; i < (datasize/2); i++) + { + DRXJ_DAP_ReadReg16 (devAddr, (DRXJ_HI_ATOMIC_BUF_START + i), &word, 0); + data[2*i] = (u8_t) (word & 0xFF); + data[(2*i) + 1] = (u8_t) (word >> 8 ); + } + } + + return DRX_STS_OK; + + rw_error: + return (DRX_STS_ERROR); + +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t DRXJ_DAP_AtomicReadReg32() +* \brief Atomic read of 32 bits words +*/ +static +DRXStatus_t DRXJ_DAP_AtomicReadReg32 ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + pu32_t data, + DRXflags_t flags) +{ + u8_t buf[sizeof (*data)]; + DRXStatus_t rc = DRX_STS_ERROR; + u32_t word = 0; + + if (!data) + { + return DRX_STS_INVALID_ARG; + } + + rc = DRXJ_DAP_AtomicReadWriteBlock ( devAddr, addr, + sizeof (*data), buf, TRUE); + + word = (u32_t)buf[3]; + word <<= 8; + word |= (u32_t)buf[2]; + word <<= 8; + word |= (u32_t)buf[1]; + word <<= 8; + word |= (u32_t)buf[0]; + + *data = word; + + return rc; +} + + +/*============================================================================*/ + + +/*============================================================================*/ +/*== END DRXJ DAP FUNCTIONS ==*/ +/*============================================================================*/ + +/*============================================================================*/ +/*============================================================================*/ +/*== HOST INTERFACE FUNCTIONS ==*/ +/*============================================================================*/ +/*============================================================================*/ + +/** +* \fn DRXStatus_t HICfgCommand() +* \brief Configure HI with settings stored in the demod structure. +* \param demod Demodulator. +* \return DRXStatus_t. +* +* This routine was created because to much orthogonal settings have +* been put into one HI API function (configure). Especially the I2C bridge +* enable/disable should not need re-configuration of the HI. +* +*/ +static DRXStatus_t +HICfgCommand(const pDRXDemodInstance_t demod) +{ + pDRXJData_t extAttr = (pDRXJData_t)(NULL); + DRXJHiCmd_t hiCmd; + u16_t result=0; + + extAttr = (pDRXJData_t)demod -> myExtAttr; + + hiCmd.cmd = SIO_HI_RA_RAM_CMD_CONFIG; + hiCmd.param1 = SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY; + hiCmd.param2 = extAttr -> HICfgTimingDiv; + hiCmd.param3 = extAttr -> HICfgBridgeDelay; + hiCmd.param4 = extAttr -> HICfgWakeUpKey; + hiCmd.param5 = extAttr -> HICfgCtrl; + hiCmd.param6 = extAttr -> HICfgTransmit; + + CHK_ERROR( HICommand( demod -> myI2CDevAddr, &hiCmd, &result) ); + + /* Reset power down flag (set one call only) */ + extAttr -> HICfgCtrl &= (~(SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ)); + + return (DRX_STS_OK); + + rw_error: + return (DRX_STS_ERROR); +} + +/** +* \fn DRXStatus_t HICommand() +* \brief Configure HI with settings stored in the demod structure. +* \param devAddr I2C address. +* \param cmd HI command. +* \param result HI command result. +* \return DRXStatus_t. +* +* Sends command to HI +* +*/ +static DRXStatus_t +HICommand(const pI2CDeviceAddr_t devAddr, + const pDRXJHiCmd_t cmd, + pu16_t result) +{ + u16_t waitCmd=0; + u16_t nrRetries = 0; + Bool_t powerdown_cmd = FALSE; + + + /* Write parameters */ + switch ( cmd->cmd ) { + + case SIO_HI_RA_RAM_CMD_CONFIG: + case SIO_HI_RA_RAM_CMD_ATOMIC_COPY: + WR16(devAddr, SIO_HI_RA_RAM_PAR_6__A, cmd->param6); + WR16(devAddr, SIO_HI_RA_RAM_PAR_5__A, cmd->param5); + WR16(devAddr, SIO_HI_RA_RAM_PAR_4__A, cmd->param4); + WR16(devAddr, SIO_HI_RA_RAM_PAR_3__A, cmd->param3); + /* fallthrough */ + case SIO_HI_RA_RAM_CMD_BRDCTRL: + WR16(devAddr, SIO_HI_RA_RAM_PAR_2__A, cmd->param2); + WR16(devAddr, SIO_HI_RA_RAM_PAR_1__A, cmd->param1); + /* fallthrough */ + case SIO_HI_RA_RAM_CMD_NULL: + /* No parameters */ + break; + + default: + return (DRX_STS_INVALID_ARG); + break; + } + + /* Write command */ + WR16(devAddr, SIO_HI_RA_RAM_CMD__A, cmd->cmd); + + if ( (cmd->cmd) == SIO_HI_RA_RAM_CMD_RESET ) + { + /* Allow for HI to reset */ + DRXBSP_HST_Sleep(1); + } + + /* Detect power down to ommit reading result */ + powerdown_cmd = (Bool_t)( ( cmd->cmd == SIO_HI_RA_RAM_CMD_CONFIG ) && + ( ((cmd->param5) & SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) == + SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ ) ); + if ( powerdown_cmd == FALSE ) + { + /* Wait until command rdy */ + do + { + nrRetries++; + if ( nrRetries > DRXJ_MAX_RETRIES ) + { + goto rw_error; + }; + + RR16(devAddr, SIO_HI_RA_RAM_CMD__A, &waitCmd); + } while ( waitCmd != 0 ); + + /* Read result */ + RR16(devAddr, SIO_HI_RA_RAM_RES__A, result); + + } /* if ( powerdown_cmd == TRUE ) */ + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/** +* \fn DRXStatus_t InitHI( const pDRXDemodInstance_t demod ) +* \brief Initialise and configurate HI. +* \param demod pointer to demod data. +* \return DRXStatus_t Return status. +* \retval DRX_STS_OK Success. +* \retval DRX_STS_ERROR Failure. +* +* Needs to know Psys (System Clock period) and Posc (Osc Clock period) +* Need to store configuration in driver because of the way I2C +* bridging is controlled. +* +*/ +static DRXStatus_t +InitHI( const pDRXDemodInstance_t demod ) +{ + pDRXJData_t extAttr =(pDRXJData_t)(NULL); + pDRXCommonAttr_t commonAttr =(pDRXCommonAttr_t)(NULL); + pI2CDeviceAddr_t devAddr =(pI2CDeviceAddr_t)(NULL); + + extAttr = (pDRXJData_t) demod -> myExtAttr; + commonAttr = (pDRXCommonAttr_t) demod -> myCommonAttr; + devAddr = demod -> myI2CDevAddr; + + /* PATCH for bug 5003, HI ucode v3.1.0 */ + WR16( devAddr, 0x4301D7, 0x801 ); + + /* Timing div, 250ns/Psys */ + /* Timing div, = ( delay (nano seconds) * sysclk (kHz) )/ 1000 */ + extAttr -> HICfgTimingDiv = + (u16_t)((commonAttr->sysClockFreq/1000)* HI_I2C_DELAY)/1000 ; + /* Clipping */ + if ( (extAttr -> HICfgTimingDiv) > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M ) + { + extAttr -> HICfgTimingDiv = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M; + } + /* Bridge delay, uses oscilator clock */ + /* Delay = ( delay (nano seconds) * oscclk (kHz) )/ 1000 */ + /* SDA brdige delay */ + extAttr -> HICfgBridgeDelay = + (u16_t)((commonAttr->oscClockFreq/1000)* HI_I2C_BRIDGE_DELAY)/1000 ; + /* Clipping */ + if ( (extAttr -> HICfgBridgeDelay) > SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M ) + { + extAttr -> HICfgBridgeDelay = SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M; + } + /* SCL bridge delay, same as SDA for now */ + extAttr -> HICfgBridgeDelay += ((extAttr -> HICfgBridgeDelay)<< + SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B); + /* Wakeup key, setting the read flag (as suggest in the documentation) does + not always result into a working solution (barebones worked VI2C failed). + Not setting the bit works in all cases . */ + extAttr -> HICfgWakeUpKey = DRXJ_WAKE_UP_KEY; + /* port/bridge/power down ctrl */ + extAttr -> HICfgCtrl = ( SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE ); + /* transit mode time out delay and watch dog divider */ + extAttr ->HICfgTransmit = SIO_HI_RA_RAM_PAR_6__PRE; + + CHK_ERROR( HICfgCommand( demod ) ); + + return (DRX_STS_OK); + + rw_error: + return (DRX_STS_ERROR); +} + + +/*============================================================================*/ +/*== END HOST INTERFACE FUNCTIONS ==*/ +/*============================================================================*/ + +/*============================================================================*/ +/*============================================================================*/ +/*== AUXILIARY FUNCTIONS ==*/ +/*============================================================================*/ +/*============================================================================*/ + +/** +* \fn DRXStatus_t GetDeviceCapabilities() +* \brief Get and store device capabilities. +* \param demod Pointer to demodulator instance. +* \return DRXStatus_t. +* \return DRX_STS_OK Success +* \retval DRX_STS_ERROR Failure +* +* Depending on pulldowns on MDx pins the following internals are set: +* * commonAttr->oscClockFreq +* * extAttr->hasLNA +* * extAttr->hasNTSC +* * extAttr->hasBTSC +* * extAttr->hasOOB +* +*/ +static DRXStatus_t +GetDeviceCapabilities( pDRXDemodInstance_t demod ) +{ + pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t)(NULL); + pDRXJData_t extAttr = (pDRXJData_t)NULL; + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)(NULL); + u16_t sioPdrOhwCfg = 0; + u32_t sioTopJtagidLo = 0; + u16_t bid = 0; + + commonAttr = (pDRXCommonAttr_t) demod -> myCommonAttr; + extAttr = (pDRXJData_t) demod -> myExtAttr; + devAddr = demod -> myI2CDevAddr; + + WR16 ( devAddr, SIO_TOP_COMM_KEY__A , SIO_TOP_COMM_KEY_KEY); + RR16 ( devAddr, SIO_PDR_OHW_CFG__A , &sioPdrOhwCfg); + WR16 ( devAddr, SIO_TOP_COMM_KEY__A , SIO_TOP_COMM_KEY__PRE); + + switch ( (sioPdrOhwCfg & SIO_PDR_OHW_CFG_FREF_SEL__M ) ) + { + case 0: + /* ignore (bypass ?)*/ + break; + case 1: + /* 27 MHz */ + commonAttr->oscClockFreq = 27000; + break; + case 2: + /* 20.25 MHz */ + commonAttr->oscClockFreq = 20250; + break; + case 3: + /* 4 MHz */ + commonAttr->oscClockFreq = 4000; + break; + default: + return (DRX_STS_ERROR); + } + + /* + Determine device capabilities + Based on pinning v47 + */ + RR32( devAddr, SIO_TOP_JTAGID_LO__A , &sioTopJtagidLo); + extAttr->mfx = (u8_t)((sioTopJtagidLo>>29)&0xF) ; + + switch ((sioTopJtagidLo>>12)&0xFF) + { + case 0x31: + WR16( devAddr, SIO_TOP_COMM_KEY__A , SIO_TOP_COMM_KEY_KEY); + RR16( devAddr, SIO_PDR_UIO_IN_HI__A , &bid); + bid = (bid >> 10) & 0xf; + WR16( devAddr, SIO_TOP_COMM_KEY__A , SIO_TOP_COMM_KEY__PRE); + + extAttr->hasLNA = TRUE; + extAttr->hasNTSC = FALSE; + extAttr->hasBTSC = FALSE; + extAttr->hasOOB = FALSE; + extAttr->hasSMATX = TRUE; + extAttr->hasSMARX = FALSE; + extAttr->hasGPIO = FALSE; + extAttr->hasIRQN = FALSE; + break; + case 0x33: + extAttr->hasLNA = FALSE; + extAttr->hasNTSC = FALSE; + extAttr->hasBTSC = FALSE; + extAttr->hasOOB = FALSE; + extAttr->hasSMATX = TRUE; + extAttr->hasSMARX = FALSE; + extAttr->hasGPIO = FALSE; + extAttr->hasIRQN = FALSE; + break; + case 0x45: + extAttr->hasLNA = TRUE; + extAttr->hasNTSC = TRUE; + extAttr->hasBTSC = FALSE; + extAttr->hasOOB = FALSE; + extAttr->hasSMATX = TRUE; + extAttr->hasSMARX = TRUE; + extAttr->hasGPIO = TRUE; + extAttr->hasIRQN = FALSE; + break; + case 0x46: + extAttr->hasLNA = FALSE; + extAttr->hasNTSC = TRUE; + extAttr->hasBTSC = FALSE; + extAttr->hasOOB = FALSE; + extAttr->hasSMATX = TRUE; + extAttr->hasSMARX = TRUE; + extAttr->hasGPIO = TRUE; + extAttr->hasIRQN = FALSE; + break; + case 0x41: + extAttr->hasLNA = TRUE; + extAttr->hasNTSC = TRUE; + extAttr->hasBTSC = TRUE; + extAttr->hasOOB = FALSE; + extAttr->hasSMATX = TRUE; + extAttr->hasSMARX = TRUE; + extAttr->hasGPIO = TRUE; + extAttr->hasIRQN = FALSE; + break; + case 0x43: + extAttr->hasLNA = FALSE; + extAttr->hasNTSC = TRUE; + extAttr->hasBTSC = TRUE; + extAttr->hasOOB = FALSE; + extAttr->hasSMATX = TRUE; + extAttr->hasSMARX = TRUE; + extAttr->hasGPIO = TRUE; + extAttr->hasIRQN = FALSE; + break; + case 0x32: + extAttr->hasLNA = TRUE; + extAttr->hasNTSC = FALSE; + extAttr->hasBTSC = FALSE; + extAttr->hasOOB = TRUE; + extAttr->hasSMATX = TRUE; + extAttr->hasSMARX = TRUE; + extAttr->hasGPIO = TRUE; + extAttr->hasIRQN = TRUE; + break; + case 0x34: + extAttr->hasLNA = FALSE; + extAttr->hasNTSC = TRUE; + extAttr->hasBTSC = TRUE; + extAttr->hasOOB = TRUE; + extAttr->hasSMATX = TRUE; + extAttr->hasSMARX = TRUE; + extAttr->hasGPIO = TRUE; + extAttr->hasIRQN = TRUE; + break; + case 0x42: + extAttr->hasLNA = TRUE ; + extAttr->hasNTSC = TRUE ; + extAttr->hasBTSC = TRUE ; + extAttr->hasOOB = TRUE ; + extAttr->hasSMATX = TRUE; + extAttr->hasSMARX = TRUE; + extAttr->hasGPIO = TRUE; + extAttr->hasIRQN = TRUE; + break; + case 0x44: + extAttr->hasLNA = FALSE; + extAttr->hasNTSC = TRUE; + extAttr->hasBTSC = TRUE; + extAttr->hasOOB = TRUE; + extAttr->hasSMATX = TRUE; + extAttr->hasSMARX = TRUE; + extAttr->hasGPIO = TRUE; + extAttr->hasIRQN = TRUE; + break; + default: + /* Unknown device variant */ + return (DRX_STS_ERROR); + break; + } + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + + +/** +* \fn DRXStatus_t PowerUpDevice() +* \brief Power up device. +* \param demod Pointer to demodulator instance. +* \return DRXStatus_t. +* \return DRX_STS_OK Success +* \retval DRX_STS_ERROR Failure, I2C or max retries reached +* +*/ + +#ifndef DRXJ_MAX_RETRIES_POWERUP +#define DRXJ_MAX_RETRIES_POWERUP 10 +#endif + +static DRXStatus_t +PowerUpDevice( pDRXDemodInstance_t demod ) +{ + pI2CDeviceAddr_t devAddr =(pI2CDeviceAddr_t)(NULL); + u8_t data = 0 ; + u16_t retryCount = 0; + I2CDeviceAddr_t wakeUpAddr; + + devAddr = demod->myI2CDevAddr; + wakeUpAddr.i2cAddr = DRXJ_WAKE_UP_KEY; + wakeUpAddr.i2cDevId = devAddr->i2cDevId; + wakeUpAddr.userData = devAddr->userData; + /* CHK_ERROR macro not used, I2C access may fail in this case: no ack + dummy write must be used to wake uop device, dummy read must be used to + reset HI state machine (avoiding actual writes) */ + do + { + data = 0; + DRXBSP_I2C_WriteRead( &wakeUpAddr, 1, &data, + (pI2CDeviceAddr_t)(NULL), 0, (pu8_t)(NULL) ); + DRXBSP_HST_Sleep(10); + retryCount++ ; + }while ( (DRXBSP_I2C_WriteRead( (pI2CDeviceAddr_t)(NULL), 0, (pu8_t)(NULL), + devAddr, 1, &data ) + != DRX_STS_OK ) && + (retryCount < DRXJ_MAX_RETRIES_POWERUP) ); + + /* Need some recovery time .... */ + DRXBSP_HST_Sleep(10); + + if ( retryCount == DRXJ_MAX_RETRIES_POWERUP ) + { + return (DRX_STS_ERROR); + } + + return (DRX_STS_OK); +} + +/*----------------------------------------------------------------------------*/ +/* MPEG Output Configuration Functions - begin */ +/*----------------------------------------------------------------------------*/ +/** +* \fn DRXStatus_t CtrlSetCfgMPEGOutput() +* \brief Set MPEG output configuration of the device. +* \param devmod Pointer to demodulator instance. +* \param cfgData Pointer to mpeg output configuaration. +* \return DRXStatus_t. +* +* Configure MPEG output parameters. +* +*/ +static DRXStatus_t +CtrlSetCfgMPEGOutput( pDRXDemodInstance_t demod, + pDRXCfgMPEGOutput_t cfgData ) +{ + pI2CDeviceAddr_t devAddr =(pI2CDeviceAddr_t)(NULL); + pDRXJData_t extAttr =(pDRXJData_t)(NULL); + pDRXCommonAttr_t commonAttr =(pDRXCommonAttr_t)(NULL); + u16_t fecOcRegMode = 0; + u16_t fecOcRegIprMode = 0; + u16_t fecOcRegIprInvert = 0; + u32_t maxBitRate = 0; + u32_t rcnRate = 0; + u32_t nrBits = 0; + u16_t sioPdrMdCfg = 0; + /* data mask for the output data byte */ + u16_t InvertDataMask = FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M | + FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M | + FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M | + FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M; + /* check arguments */ + if (( demod == NULL ) || + ( cfgData == NULL )) + { + return (DRX_STS_INVALID_ARG); + } + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t) demod -> myExtAttr; + commonAttr = (pDRXCommonAttr_t) demod -> myCommonAttr; + + if ( cfgData->enableMPEGOutput == TRUE ) + { + /* quick and dirty patch to set MPEG incase current std is not + producing MPEG */ + switch ( extAttr->standard ) + { + case DRX_STANDARD_8VSB: + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: + break; + default: + /* not an MPEG producing std, just store MPEG cfg */ + commonAttr->mpegCfg.enableMPEGOutput = cfgData->enableMPEGOutput; + commonAttr->mpegCfg.insertRSByte = cfgData->insertRSByte; + commonAttr->mpegCfg.enableParallel = cfgData->enableParallel; + commonAttr->mpegCfg.invertDATA = cfgData->invertDATA; + commonAttr->mpegCfg.invertERR = cfgData->invertERR; + commonAttr->mpegCfg.invertSTR = cfgData->invertSTR; + commonAttr->mpegCfg.invertVAL = cfgData->invertVAL; + commonAttr->mpegCfg.invertCLK = cfgData->invertCLK; + commonAttr->mpegCfg.staticCLK = cfgData->staticCLK; + commonAttr->mpegCfg.bitrate = cfgData->bitrate; + return (DRX_STS_OK); + } + + WR16( devAddr, FEC_OC_OCR_INVERT__A, 0); + switch (extAttr->standard) + { + case DRX_STANDARD_8VSB: + WR16( devAddr, FEC_OC_FCT_USAGE__A, 7 ); /* 2048 bytes fifo ram */ + WR16( devAddr, FEC_OC_TMD_CTL_UPD_RATE__A, 10); + WR16( devAddr, FEC_OC_TMD_INT_UPD_RATE__A, 10); + WR16( devAddr, FEC_OC_AVR_PARM_A__A, 5); + WR16( devAddr, FEC_OC_AVR_PARM_B__A, 7); + WR16( devAddr, FEC_OC_RCN_GAIN__A, 10); + /* Low Water Mark for synchronization */ + WR16( devAddr, FEC_OC_SNC_LWM__A, 3 ); + /* High Water Mark for synchronization */ + WR16( devAddr, FEC_OC_SNC_HWM__A, 5 ); + break; + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_C: + switch ( extAttr->constellation ) + { + case DRX_CONSTELLATION_QAM256: + nrBits = 8; + break; + case DRX_CONSTELLATION_QAM128: + nrBits = 7; + break; + case DRX_CONSTELLATION_QAM64: + nrBits = 6; + break; + case DRX_CONSTELLATION_QAM32: + nrBits = 5; + break; + case DRX_CONSTELLATION_QAM16: + nrBits = 4; + break; + default: + return (DRX_STS_ERROR); + } /* extAttr->constellation */ + /* maxBitRate = symbolRate * nrBits * coef */ + /* coef = 188/204 */ + maxBitRate = ( extAttr->currSymbolRate / 8 ) * nrBits * 188; + /* pass through b/c Annex A/c need following settings */ + case DRX_STANDARD_ITU_B: + WR16( devAddr, FEC_OC_FCT_USAGE__A, FEC_OC_FCT_USAGE__PRE); + WR16( devAddr, FEC_OC_TMD_CTL_UPD_RATE__A, FEC_OC_TMD_CTL_UPD_RATE__PRE); + WR16( devAddr, FEC_OC_TMD_INT_UPD_RATE__A, 5); + WR16( devAddr, FEC_OC_AVR_PARM_A__A, FEC_OC_AVR_PARM_A__PRE); + WR16( devAddr, FEC_OC_AVR_PARM_B__A, FEC_OC_AVR_PARM_B__PRE); + if (cfgData->staticCLK == TRUE) + { + WR16( devAddr, FEC_OC_RCN_GAIN__A, 0xD ); + } + else + { + WR16( devAddr, FEC_OC_RCN_GAIN__A, FEC_OC_RCN_GAIN__PRE ); + } + WR16( devAddr, FEC_OC_SNC_LWM__A, 2); + WR16( devAddr, FEC_OC_SNC_HWM__A, 12); + break; + default: + break; + }/* swtich (standard) */ + + /* Check insertion of the Reed-Solomon parity bytes */ + RR16( devAddr, FEC_OC_MODE__A , &fecOcRegMode ); + RR16( devAddr, FEC_OC_IPR_MODE__A, &fecOcRegIprMode ); + if ( cfgData->insertRSByte == TRUE ) + { + /* enable parity symbol forward */ + fecOcRegMode |= FEC_OC_MODE_PARITY__M; + /* MVAL disable during parity bytes */ + fecOcRegIprMode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M; + switch ( extAttr->standard ) + { + case DRX_STANDARD_8VSB: + rcnRate = 0x004854D3; + break; + case DRX_STANDARD_ITU_B: + fecOcRegMode |= FEC_OC_MODE_TRANSPARENT__M; + switch ( extAttr->constellation ) + { + case DRX_CONSTELLATION_QAM256: + rcnRate = 0x008945E7; + break; + case DRX_CONSTELLATION_QAM64: + rcnRate = 0x005F64D4; + break; + default: + return (DRX_STS_ERROR); + } + break; + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_C: + /* insertRSByte = TRUE -> coef = 188/188 -> 1, RS bits are in MPEG output */ + rcnRate = ( Frac28 ( maxBitRate, ( u32_t )( commonAttr->sysClockFreq / 8 ) ) ) / 188; + break; + default: + return (DRX_STS_ERROR); + } /* extAttr->standard */ + } + else /* insertRSByte == FALSE */ + { + /* disable parity symbol forward */ + fecOcRegMode &= (~FEC_OC_MODE_PARITY__M); + /* MVAL enable during parity bytes */ + fecOcRegIprMode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M); + switch ( extAttr->standard ) + { + case DRX_STANDARD_8VSB: + rcnRate = 0x0041605C; + break; + case DRX_STANDARD_ITU_B: + fecOcRegMode &= (~FEC_OC_MODE_TRANSPARENT__M); + switch ( extAttr->constellation ) + { + case DRX_CONSTELLATION_QAM256: + rcnRate = 0x0082D6A0; + break; + case DRX_CONSTELLATION_QAM64: + rcnRate = 0x005AEC1A; + break; + default: + return (DRX_STS_ERROR); + } + break; + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_C: + /* insertRSByte = FALSE -> coef = 188/204, RS bits not in MPEG output */ + rcnRate = ( Frac28 ( maxBitRate, ( u32_t )( commonAttr->sysClockFreq / 8 ) ) ) / 204; + break; + default: + return (DRX_STS_ERROR); + } /* extAttr->standard */ + } + + if ( cfgData->enableParallel == TRUE ) + { /* MPEG data output is paralel -> clear ipr_mode[0] */ + fecOcRegIprMode &= (~(FEC_OC_IPR_MODE_SERIAL__M)); + } + else + { /* MPEG data output is serial -> set ipr_mode[0] */ + fecOcRegIprMode |= FEC_OC_IPR_MODE_SERIAL__M; + } + + /* Control slective inversion of output bits */ + if ( cfgData->invertDATA == TRUE ) + { + fecOcRegIprInvert |= InvertDataMask; + } + else + { + fecOcRegIprInvert &= (~(InvertDataMask)); + } + + if ( cfgData->invertERR == TRUE ) + { + fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MERR__M; + } + else + { + fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MERR__M)); + } + + if ( cfgData->invertSTR == TRUE ) + { + fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MSTRT__M; + } + else + { + fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MSTRT__M)); + } + + if ( cfgData->invertVAL == TRUE ) + { + fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MVAL__M; + } + else + { + fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MVAL__M)); + } + + if ( cfgData->invertCLK == TRUE ) + { + fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MCLK__M; + } + else + { + fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MCLK__M)); + } + + if ( cfgData->staticCLK == TRUE ) /* Static mode */ + { + u32_t dtoRate = 0; + u32_t bitRate = 0; + u16_t fecOcDtoBurstLen = 0; + u16_t fecOcDtoPeriod = 0; + + fecOcDtoBurstLen = FEC_OC_DTO_BURST_LEN__PRE; + + switch ( extAttr->standard ) + { + case DRX_STANDARD_8VSB: + fecOcDtoPeriod = 4; + if ( cfgData->insertRSByte == TRUE ) + { + fecOcDtoBurstLen = 208; + } + break; + case DRX_STANDARD_ITU_A: + { + u32_t symbolRateTh = 6400000; + if ( cfgData->insertRSByte == TRUE ) + { + fecOcDtoBurstLen = 204; + symbolRateTh = 5900000; + } + if ( extAttr->currSymbolRate >= symbolRateTh) + { + fecOcDtoPeriod = 0; + } + else + { + fecOcDtoPeriod = 1; + } + } + break; + case DRX_STANDARD_ITU_B: + fecOcDtoPeriod = 1; + if ( cfgData->insertRSByte == TRUE ) + { + fecOcDtoBurstLen = 128; + } + break; + case DRX_STANDARD_ITU_C: + fecOcDtoPeriod = 1; + if ( cfgData->insertRSByte == TRUE ) + { + fecOcDtoBurstLen = 204; + } + break; + default: + return (DRX_STS_ERROR); + } + bitRate = commonAttr->sysClockFreq * 1000 / (fecOcDtoPeriod + 2); + dtoRate = Frac28(bitRate, commonAttr->sysClockFreq * 1000 ); + dtoRate >>= 3; + WR16 ( devAddr, FEC_OC_DTO_RATE_HI__A, (u16_t) ((dtoRate >> 16) & FEC_OC_DTO_RATE_HI__M) ); + WR16 ( devAddr, FEC_OC_DTO_RATE_LO__A, (u16_t) (dtoRate & FEC_OC_DTO_RATE_LO_RATE_LO__M) ); + WR16 ( devAddr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M | FEC_OC_DTO_MODE_OFFSET_ENABLE__M ); + WR16 ( devAddr, FEC_OC_FCT_MODE__A, FEC_OC_FCT_MODE_RAT_ENA__M | FEC_OC_FCT_MODE_VIRT_ENA__M ); + WR16 ( devAddr, FEC_OC_DTO_BURST_LEN__A, fecOcDtoBurstLen ); + if ( extAttr->mpegOutputClockRate != DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO ) + fecOcDtoPeriod = extAttr->mpegOutputClockRate - 1; + WR16 ( devAddr, FEC_OC_DTO_PERIOD__A, fecOcDtoPeriod ); + } + else /* Dynamic mode */ + { + WR16 ( devAddr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M ); + WR16 ( devAddr, FEC_OC_FCT_MODE__A, 0 ); + } + + WR32 ( devAddr, FEC_OC_RCN_CTL_RATE_LO__A, rcnRate ); + + /* Write appropriate registers with requested configuration */ + WR16 ( devAddr, FEC_OC_MODE__A, fecOcRegMode ); + WR16 ( devAddr, FEC_OC_IPR_MODE__A, fecOcRegIprMode ); + WR16 ( devAddr, FEC_OC_IPR_INVERT__A, fecOcRegIprInvert ); + + /* enabling for both parallel and serial now */ + /* Write magic word to enable pdr reg write */ + WR16 ( devAddr, SIO_TOP_COMM_KEY__A, 0xFABA); + /* Set MPEG TS pads to outputmode */ + WR16 ( devAddr, SIO_PDR_MSTRT_CFG__A, 0x0013); + WR16 ( devAddr, SIO_PDR_MERR_CFG__A, 0x0013); + WR16 ( devAddr, SIO_PDR_MCLK_CFG__A, + MPEG_OUTPUT_CLK_DRIVE_STRENGTH << SIO_PDR_MCLK_CFG_DRIVE__B + | 0x03 << SIO_PDR_MCLK_CFG_MODE__B ); + WR16 ( devAddr, SIO_PDR_MVAL_CFG__A, 0x0013); + sioPdrMdCfg = MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH << SIO_PDR_MD0_CFG_DRIVE__B + |0x03 << SIO_PDR_MD0_CFG_MODE__B; + WR16 ( devAddr, SIO_PDR_MD0_CFG__A, sioPdrMdCfg); + if ( cfgData->enableParallel == TRUE ) + { /* MPEG data output is paralel -> set MD1 to MD7 to output mode */ + sioPdrMdCfg = MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH << SIO_PDR_MD0_CFG_DRIVE__B + |0x03 << SIO_PDR_MD0_CFG_MODE__B; + WR16 ( devAddr, SIO_PDR_MD0_CFG__A, sioPdrMdCfg); + WR16 ( devAddr, SIO_PDR_MD1_CFG__A, sioPdrMdCfg); + WR16 ( devAddr, SIO_PDR_MD2_CFG__A, sioPdrMdCfg); + WR16 ( devAddr, SIO_PDR_MD3_CFG__A, sioPdrMdCfg); + WR16 ( devAddr, SIO_PDR_MD4_CFG__A, sioPdrMdCfg); + WR16 ( devAddr, SIO_PDR_MD5_CFG__A, sioPdrMdCfg); + WR16 ( devAddr, SIO_PDR_MD6_CFG__A, sioPdrMdCfg); + WR16 ( devAddr, SIO_PDR_MD7_CFG__A, sioPdrMdCfg); + } + else + { /* MPEG data output is serial -> set MD1 to MD7 to tri-state */ + WR16 ( devAddr, SIO_PDR_MD1_CFG__A, 0x0000); + WR16 ( devAddr, SIO_PDR_MD2_CFG__A, 0x0000); + WR16 ( devAddr, SIO_PDR_MD3_CFG__A, 0x0000); + WR16 ( devAddr, SIO_PDR_MD4_CFG__A, 0x0000); + WR16 ( devAddr, SIO_PDR_MD5_CFG__A, 0x0000); + WR16 ( devAddr, SIO_PDR_MD6_CFG__A, 0x0000); + WR16 ( devAddr, SIO_PDR_MD7_CFG__A, 0x0000); + } + /* Enable Monitor Bus output over MPEG pads and ctl input */ + WR16 ( devAddr, SIO_PDR_MON_CFG__A, 0x0000); + /* Write nomagic word to enable pdr reg write */ + WR16 ( devAddr, SIO_TOP_COMM_KEY__A, 0x0000); + } + else + { + /* Write magic word to enable pdr reg write */ + WR16 ( devAddr, SIO_TOP_COMM_KEY__A , 0xFABA); + /* Set MPEG TS pads to inputmode */ + WR16 ( devAddr, SIO_PDR_MSTRT_CFG__A , 0x0000); + WR16 ( devAddr, SIO_PDR_MERR_CFG__A , 0x0000); + WR16 ( devAddr, SIO_PDR_MCLK_CFG__A , 0x0000); + WR16 ( devAddr, SIO_PDR_MVAL_CFG__A , 0x0000); + WR16 ( devAddr, SIO_PDR_MD0_CFG__A , 0x0000); + WR16 ( devAddr, SIO_PDR_MD1_CFG__A , 0x0000); + WR16 ( devAddr, SIO_PDR_MD2_CFG__A , 0x0000); + WR16 ( devAddr, SIO_PDR_MD3_CFG__A , 0x0000); + WR16 ( devAddr, SIO_PDR_MD4_CFG__A , 0x0000); + WR16 ( devAddr, SIO_PDR_MD5_CFG__A , 0x0000); + WR16 ( devAddr, SIO_PDR_MD6_CFG__A , 0x0000); + WR16 ( devAddr, SIO_PDR_MD7_CFG__A , 0x0000); + /* Enable Monitor Bus output over MPEG pads and ctl input */ + WR16 ( devAddr, SIO_PDR_MON_CFG__A , 0x0000); + /* Write nomagic word to enable pdr reg write */ + WR16 ( devAddr, SIO_TOP_COMM_KEY__A , 0x0000); + } + + /* save values for restore after re-acquire */ + commonAttr->mpegCfg.enableMPEGOutput = cfgData->enableMPEGOutput; + commonAttr->mpegCfg.insertRSByte = cfgData->insertRSByte; + commonAttr->mpegCfg.enableParallel = cfgData->enableParallel; + commonAttr->mpegCfg.invertDATA = cfgData->invertDATA; + commonAttr->mpegCfg.invertERR = cfgData->invertERR; + commonAttr->mpegCfg.invertSTR = cfgData->invertSTR; + commonAttr->mpegCfg.invertVAL = cfgData->invertVAL; + commonAttr->mpegCfg.invertCLK = cfgData->invertCLK; + commonAttr->mpegCfg.staticCLK = cfgData->staticCLK; + commonAttr->mpegCfg.bitrate = cfgData->bitrate; + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*----------------------------------------------------------------------------*/ + +/** +* \fn DRXStatus_t CtrlGetCfgMPEGOutput() +* \brief Get MPEG output configuration of the device. +* \param devmod Pointer to demodulator instance. +* \param cfgData Pointer to MPEG output configuaration struct. +* \return DRXStatus_t. +* +* Retrieve MPEG output configuartion. +* +*/ +static DRXStatus_t +CtrlGetCfgMPEGOutput( pDRXDemodInstance_t demod, + pDRXCfgMPEGOutput_t cfgData ) +{ + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)(NULL); + pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t)(NULL); + DRXLockStatus_t lockStatus = DRX_NOT_LOCKED; + u32_t rateReg = 0; + u32_t data64Hi = 0; + u32_t data64Lo = 0; + + if( cfgData == NULL ) + { + return (DRX_STS_INVALID_ARG); + } + devAddr = demod->myI2CDevAddr; + commonAttr = demod->myCommonAttr; + + cfgData->enableMPEGOutput = commonAttr->mpegCfg.enableMPEGOutput; + cfgData->insertRSByte = commonAttr->mpegCfg.insertRSByte; + cfgData->enableParallel = commonAttr->mpegCfg.enableParallel; + cfgData->invertDATA = commonAttr->mpegCfg.invertDATA; + cfgData->invertERR = commonAttr->mpegCfg.invertERR; + cfgData->invertSTR = commonAttr->mpegCfg.invertSTR; + cfgData->invertVAL = commonAttr->mpegCfg.invertVAL; + cfgData->invertCLK = commonAttr->mpegCfg.invertCLK; + cfgData->staticCLK = commonAttr->mpegCfg.staticCLK; + cfgData->bitrate = 0; + + CHK_ERROR( CtrlLockStatus( demod, &lockStatus) ); + if ( (lockStatus == DRX_LOCKED) ) + { + RR32 (devAddr, FEC_OC_RCN_DYN_RATE_LO__A, &rateReg); + /* Frcn_rate = rateReg * Fsys / 2 ^ 25 */ + Mult32 ( rateReg, commonAttr->sysClockFreq * 1000, &data64Hi, &data64Lo ); + cfgData->bitrate = (data64Hi << 7) | (data64Lo >> 25); + } + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*----------------------------------------------------------------------------*/ +/* MPEG Output Configuration Functions - end */ +/*----------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------*/ +/* miscellaneous configuartions - begin */ +/*----------------------------------------------------------------------------*/ + +/** +* \fn DRXStatus_t SetMPEGTEIHandling() +* \brief Activate MPEG TEI handling settings. +* \param devmod Pointer to demodulator instance. +* \return DRXStatus_t. +* +* This routine should be called during a set channel of QAM/VSB +* +*/ +static DRXStatus_t +SetMPEGTEIHandling( pDRXDemodInstance_t demod ) +{ + pDRXJData_t extAttr = (pDRXJData_t)(NULL); + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)(NULL); + u16_t fecOcDprMode = 0; + u16_t fecOcSncMode = 0; + u16_t fecOcEmsMode = 0; + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t) demod -> myExtAttr; + + RR16( devAddr, FEC_OC_DPR_MODE__A, &fecOcDprMode ); + RR16( devAddr, FEC_OC_SNC_MODE__A, &fecOcSncMode ); + RR16( devAddr, FEC_OC_EMS_MODE__A, &fecOcEmsMode ); + + /* reset to default, allow TEI bit to be changed */ + fecOcDprMode &= (~FEC_OC_DPR_MODE_ERR_DISABLE__M); + fecOcSncMode &= (~(FEC_OC_SNC_MODE_ERROR_CTL__M | + FEC_OC_SNC_MODE_CORR_DISABLE__M)); + fecOcEmsMode &= (~FEC_OC_EMS_MODE_MODE__M); + + if ( extAttr->disableTEIhandling == TRUE ) + { + /* do not change TEI bit */ + fecOcDprMode |= FEC_OC_DPR_MODE_ERR_DISABLE__M; + fecOcSncMode |= FEC_OC_SNC_MODE_CORR_DISABLE__M | + ( (0x2)<<(FEC_OC_SNC_MODE_ERROR_CTL__B)); + fecOcEmsMode |= ((0x01)<<(FEC_OC_EMS_MODE_MODE__B)); + } + + WR16( devAddr, FEC_OC_DPR_MODE__A, fecOcDprMode ); + WR16( devAddr, FEC_OC_SNC_MODE__A, fecOcSncMode ); + WR16( devAddr, FEC_OC_EMS_MODE__A, fecOcEmsMode ); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*----------------------------------------------------------------------------*/ +/** +* \fn DRXStatus_t BitReverseMPEGOutput() +* \brief Set MPEG output bit-endian settings. +* \param devmod Pointer to demodulator instance. +* \return DRXStatus_t. +* +* This routine should be called during a set channel of QAM/VSB +* +*/ +static DRXStatus_t +BitReverseMPEGOutput ( pDRXDemodInstance_t demod ) +{ + pDRXJData_t extAttr = (pDRXJData_t)(NULL); + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)(NULL); + u16_t fecOcIprMode = 0; + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t) demod -> myExtAttr; + + RR16( devAddr, FEC_OC_IPR_MODE__A, &fecOcIprMode ); + + /* reset to default (normal bit order) */ + fecOcIprMode &= (~FEC_OC_IPR_MODE_REVERSE_ORDER__M); + + if ( extAttr->bitReverseMpegOutout == TRUE) + { + /* reverse bit order */ + fecOcIprMode |= FEC_OC_IPR_MODE_REVERSE_ORDER__M; + } + + WR16( devAddr, FEC_OC_IPR_MODE__A, fecOcIprMode ); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*----------------------------------------------------------------------------*/ +/** +* \fn DRXStatus_t SetMPEGOutputClockRate() +* \brief Set MPEG output clock rate. +* \param devmod Pointer to demodulator instance. +* \return DRXStatus_t. +* +* This routine should be called during a set channel of QAM/VSB +* +*/ +static DRXStatus_t +SetMPEGOutputClockRate ( pDRXDemodInstance_t demod ) +{ + pDRXJData_t extAttr = (pDRXJData_t)(NULL); + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)(NULL); + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t) demod -> myExtAttr; + + if ( extAttr->mpegOutputClockRate != DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO ) + { + WR16 ( devAddr, FEC_OC_DTO_PERIOD__A, extAttr->mpegOutputClockRate - 1 ); + } + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*----------------------------------------------------------------------------*/ +/** +* \fn DRXStatus_t SetMPEGStartWidth() +* \brief Set MPEG start width. +* \param devmod Pointer to demodulator instance. +* \return DRXStatus_t. +* +* This routine should be called during a set channel of QAM/VSB +* +*/ +static DRXStatus_t +SetMPEGStartWidth ( pDRXDemodInstance_t demod ) +{ + pDRXJData_t extAttr = (pDRXJData_t)(NULL); + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)(NULL); + u16_t fecOcCommMb = 0; + pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) NULL; + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t) demod -> myExtAttr; + commonAttr = demod->myCommonAttr; + + if ((commonAttr->mpegCfg.staticCLK == TRUE) && (commonAttr->mpegCfg.enableParallel == FALSE)) + { + RR16 ( devAddr, FEC_OC_COMM_MB__A, &fecOcCommMb ); + fecOcCommMb &= ~FEC_OC_COMM_MB_CTL_ON; + if ( extAttr->mpegStartWidth == DRXJ_MPEG_START_WIDTH_8CLKCYC ) + { + fecOcCommMb |= FEC_OC_COMM_MB_CTL_ON; + } + WR16 ( devAddr, FEC_OC_COMM_MB__A, fecOcCommMb); + } + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*----------------------------------------------------------------------------*/ +/** +* \fn DRXStatus_t CtrlSetCfgMpegOutputMisc() +* \brief Set miscellaneous configuartions +* \param devmod Pointer to demodulator instance. +* \param cfgData pDRXJCfgMisc_t +* \return DRXStatus_t. +* +* This routine can be used to set configuartion options that are DRXJ +* specific and/or added to the requirements at a late stage. +* +*/ +static DRXStatus_t +CtrlSetCfgMpegOutputMisc( + pDRXDemodInstance_t demod, + pDRXJCfgMpegOutputMisc_t cfgData ) +{ + pDRXJData_t extAttr = (pDRXJData_t)(NULL); + + if(cfgData == NULL) + { + return (DRX_STS_INVALID_ARG); + } + + extAttr = (pDRXJData_t) demod -> myExtAttr; + + /* + Set disable TEI bit handling flag. + TEI must be left untouched by device in case of BER measurements using + external equipment that is unable to ignore the TEI bit in the TS. + Default will FALSE (enable TEI bit handling). + Reverse output bit order. Default is FALSE (msb on MD7 (parallel) or out first (serial)). + Set clock rate. Default is auto that is derived from symbol rate. + The flags and values will also be used to set registers during a set channel. + */ + extAttr->disableTEIhandling = cfgData->disableTEIHandling; + extAttr->bitReverseMpegOutout = cfgData->bitReverseMpegOutout; + extAttr->mpegOutputClockRate = cfgData->mpegOutputClockRate; + extAttr->mpegStartWidth = cfgData->mpegStartWidth; + /* Don't care what the active standard is, activate setting immediatly */ + CHK_ERROR ( SetMPEGTEIHandling( demod ) ); + CHK_ERROR ( BitReverseMPEGOutput( demod ) ); + CHK_ERROR ( SetMPEGOutputClockRate( demod ) ); + CHK_ERROR ( SetMPEGStartWidth ( demod ) ); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*----------------------------------------------------------------------------*/ + +/** +* \fn DRXStatus_t CtrlGetCfgMpegOutputMisc() +* \brief Get miscellaneous configuartions. +* \param devmod Pointer to demodulator instance. +* \param cfgData Pointer to DRXJCfgMisc_t. +* \return DRXStatus_t. +* +* This routine can be used to retreive the current setting of the configuartion +* options that are DRXJ specific and/or added to the requirements at a +* late stage. +* +*/ +static DRXStatus_t +CtrlGetCfgMpegOutputMisc( + pDRXDemodInstance_t demod, + pDRXJCfgMpegOutputMisc_t cfgData ) +{ + pDRXJData_t extAttr = (pDRXJData_t)(NULL); + u16_t data = 0; + + if(cfgData == NULL) + { + return (DRX_STS_INVALID_ARG); + } + + extAttr = (pDRXJData_t) demod -> myExtAttr; + cfgData->disableTEIHandling = extAttr->disableTEIhandling; + cfgData->bitReverseMpegOutout = extAttr->bitReverseMpegOutout; + cfgData->mpegStartWidth = extAttr->mpegStartWidth; + if (extAttr->mpegOutputClockRate != DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO) + { + cfgData->mpegOutputClockRate = extAttr->mpegOutputClockRate; + } + else + { + RR16 ( demod->myI2CDevAddr, FEC_OC_DTO_PERIOD__A, &data ); + cfgData->mpegOutputClockRate = (DRXJMpegOutputClockRate_t) (data + 1); + } + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*----------------------------------------------------------------------------*/ + +/** +* \fn DRXStatus_t CtrlGetCfgHwCfg() +* \brief Get HW configuartions. +* \param devmod Pointer to demodulator instance. +* \param cfgData Pointer to Bool. +* \return DRXStatus_t. +* +* This routine can be used to retreive the current setting of the configuartion +* options that are DRXJ specific and/or added to the requirements at a +* late stage. +* +*/ +static DRXStatus_t +CtrlGetCfgHwCfg( pDRXDemodInstance_t demod, + pDRXJCfgHwCfg_t cfgData ) +{ + u16_t data = 0; + pDRXJData_t extAttr = (pDRXJData_t)(NULL); + + if(cfgData == NULL) + { + return (DRX_STS_INVALID_ARG); + } + + extAttr = (pDRXJData_t) demod -> myExtAttr; + WR16 ( demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, 0xFABA); + RR16 ( demod->myI2CDevAddr, SIO_PDR_OHW_CFG__A, &data ); + WR16 ( demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, 0x0000); + + cfgData->i2cSpeed = (DRXJI2CSpeed_t)((data >> 6) & 0x1); + cfgData->xtalFreq = (DRXJXtalFreq_t)(data & 0x3); + + return (DRX_STS_OK); + rw_error: + return (DRX_STS_ERROR); +} +/*----------------------------------------------------------------------------*/ +/* miscellaneous configuartions - end */ +/*----------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------*/ +/* UIO Configuration Functions - begin */ +/*----------------------------------------------------------------------------*/ +/** +* \fn DRXStatus_t CtrlSetUIOCfg() +* \brief Configure modus oprandi UIO. +* \param demod Pointer to demodulator instance. +* \param UIOCfg Pointer to a configuration setting for a certain UIO. +* \return DRXStatus_t. +*/ +static DRXStatus_t +CtrlSetUIOCfg( pDRXDemodInstance_t demod, pDRXUIOCfg_t UIOCfg ) +{ + pDRXJData_t extAttr = (pDRXJData_t)(NULL); + + if (( UIOCfg == NULL ) || ( demod == NULL )) + { + return DRX_STS_INVALID_ARG; + } + extAttr = (pDRXJData_t)demod -> myExtAttr; + + /* Write magic word to enable pdr reg write */ + WR16( demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY ); + switch ( UIOCfg->uio ) { + /*====================================================================*/ + case DRX_UIO1 : + /* DRX_UIO1: SMA_TX UIO-1 */ + if (extAttr->hasSMATX != TRUE) + return DRX_STS_ERROR; + switch ( UIOCfg->mode ) + { + case DRX_UIO_MODE_FIRMWARE_SMA: /* falltrough */ + case DRX_UIO_MODE_FIRMWARE_SAW: /* falltrough */ + case DRX_UIO_MODE_READWRITE: + extAttr->uioSmaTxMode = UIOCfg->mode; + break; + case DRX_UIO_MODE_DISABLE: + extAttr->uioSmaTxMode = UIOCfg->mode; + /* pad configuration register is set 0 - input mode */ + WR16( demod->myI2CDevAddr, SIO_PDR_SMA_TX_CFG__A, 0 ); + break; + default: + return DRX_STS_INVALID_ARG; + } /* switch ( UIOCfg->mode ) */ + break; + /*====================================================================*/ + case DRX_UIO2 : + /* DRX_UIO2: SMA_RX UIO-2 */ + if (extAttr->hasSMARX != TRUE) + return DRX_STS_ERROR; + switch ( UIOCfg->mode ) + { + case DRX_UIO_MODE_FIRMWARE0: /* falltrough */ + case DRX_UIO_MODE_READWRITE: + extAttr->uioSmaRxMode = UIOCfg->mode; + break; + case DRX_UIO_MODE_DISABLE: + extAttr->uioSmaRxMode = UIOCfg->mode; + /* pad configuration register is set 0 - input mode */ + WR16( demod->myI2CDevAddr, SIO_PDR_SMA_RX_CFG__A, 0 ); + break; + default: + return DRX_STS_INVALID_ARG; + break; + } /* switch ( UIOCfg->mode ) */ + break; + /*====================================================================*/ + case DRX_UIO3 : + /* DRX_UIO3: GPIO UIO-3 */ + if (extAttr->hasGPIO != TRUE) + return DRX_STS_ERROR; + switch ( UIOCfg->mode ) + { + case DRX_UIO_MODE_FIRMWARE0: /* falltrough */ + case DRX_UIO_MODE_READWRITE: + extAttr->uioGPIOMode = UIOCfg->mode; + break; + case DRX_UIO_MODE_DISABLE: + extAttr->uioGPIOMode = UIOCfg->mode; + /* pad configuration register is set 0 - input mode */ + WR16( demod->myI2CDevAddr, SIO_PDR_GPIO_CFG__A, 0 ); + break; + default: + return DRX_STS_INVALID_ARG; + break; + } /* switch ( UIOCfg->mode ) */ + break; + /*====================================================================*/ + case DRX_UIO4 : + /* DRX_UIO4: IRQN UIO-4 */ + if (extAttr->hasIRQN != TRUE) + return DRX_STS_ERROR; + switch ( UIOCfg->mode ) + { + case DRX_UIO_MODE_READWRITE: + extAttr->uioIRQNMode = UIOCfg->mode; + break; + case DRX_UIO_MODE_DISABLE: + /* pad configuration register is set 0 - input mode */ + WR16( demod->myI2CDevAddr, SIO_PDR_IRQN_CFG__A, 0 ); + extAttr->uioIRQNMode = UIOCfg->mode; + break; + case DRX_UIO_MODE_FIRMWARE0: /* falltrough */ + default: + return DRX_STS_INVALID_ARG; + break; + } /* switch ( UIOCfg->mode ) */ + break; + /*====================================================================*/ + default: + return DRX_STS_INVALID_ARG; + } /* switch ( UIOCfg->uio ) */ + + /* Write magic word to disable pdr reg write */ + WR16 ( demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, 0x0000); + + return (DRX_STS_OK); + rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================*/ +/** +* \fn DRXStatus_t CtrlGetUIOCfg() +* \brief Get modus oprandi UIO. +* \param demod Pointer to demodulator instance. +* \param UIOCfg Pointer to a configuration setting for a certain UIO. +* \return DRXStatus_t. +*/ +static DRXStatus_t +CtrlGetUIOCfg( pDRXDemodInstance_t demod, pDRXUIOCfg_t UIOCfg ) +{ + + pDRXJData_t extAttr = (pDRXJData_t) NULL; + pDRXUIOMode_t UIOMode[4] = {NULL}; + pBool_t UIOAvailable[4] = {NULL}; + + extAttr = demod->myExtAttr; + + UIOMode[DRX_UIO1] = &extAttr->uioSmaTxMode; + UIOMode[DRX_UIO2] = &extAttr->uioSmaRxMode; + UIOMode[DRX_UIO3] = &extAttr->uioGPIOMode; + UIOMode[DRX_UIO4] = &extAttr->uioIRQNMode; + + UIOAvailable[DRX_UIO1] = &extAttr->hasSMATX; + UIOAvailable[DRX_UIO2] = &extAttr->hasSMARX; + UIOAvailable[DRX_UIO3] = &extAttr->hasGPIO; + UIOAvailable[DRX_UIO4] = &extAttr->hasIRQN; + + if ( UIOCfg == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + if ( ( UIOCfg->uio > DRX_UIO4 ) || + ( UIOCfg->uio < DRX_UIO1 ) ) + { + return DRX_STS_INVALID_ARG; + } + + if( *UIOAvailable[UIOCfg->uio] == FALSE ) + { + return DRX_STS_ERROR; + } + + UIOCfg->mode = *UIOMode[ UIOCfg->uio ]; + + return DRX_STS_OK; +} + +/** +* \fn DRXStatus_t CtrlUIOWrite() +* \brief Write to a UIO. +* \param demod Pointer to demodulator instance. +* \param UIOData Pointer to data container for a certain UIO. +* \return DRXStatus_t. +*/ +static DRXStatus_t +CtrlUIOWrite( pDRXDemodInstance_t demod, + pDRXUIOData_t UIOData) +{ + pDRXJData_t extAttr = (pDRXJData_t)(NULL); + u16_t pinCfgValue = 0; + u16_t value = 0; + + if (( UIOData == NULL ) || ( demod == NULL )) + { + return DRX_STS_INVALID_ARG; + } + + extAttr = (pDRXJData_t)demod -> myExtAttr; + + /* Write magic word to enable pdr reg write */ + WR16( demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY ); + switch ( UIOData->uio ) { + /*====================================================================*/ + case DRX_UIO1: + /* DRX_UIO1: SMA_TX UIO-1 */ + if (extAttr->hasSMATX != TRUE) + return DRX_STS_ERROR; + if ( ( extAttr->uioSmaTxMode != DRX_UIO_MODE_READWRITE ) + && ( extAttr->uioSmaTxMode != DRX_UIO_MODE_FIRMWARE_SAW ) ) + { + return DRX_STS_ERROR; + } + pinCfgValue = 0; + /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ + pinCfgValue |= 0x0113; + /* io_pad_cfg_mode output mode is drive always */ + /* io_pad_cfg_drive is set to power 2 (23 mA) */ + + /* write to io pad configuration register - output mode */ + WR16( demod->myI2CDevAddr, SIO_PDR_SMA_TX_CFG__A, pinCfgValue ); + + /* use corresponding bit in io data output registar */ + RR16( demod->myI2CDevAddr, SIO_PDR_UIO_OUT_LO__A, &value ); + if (UIOData->value == FALSE) + { + value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */ + } else { + value |= 0x8000; /* write one to 15th bit - 1st UIO */ + } + /* write back to io data output register */ + WR16( demod->myI2CDevAddr, SIO_PDR_UIO_OUT_LO__A, value ); + break; + /*======================================================================*/ + case DRX_UIO2: + /* DRX_UIO2: SMA_RX UIO-2 */ + if (extAttr->hasSMARX != TRUE) + return DRX_STS_ERROR; + if ( extAttr->uioSmaRxMode != DRX_UIO_MODE_READWRITE ) + { + return DRX_STS_ERROR; + } + pinCfgValue = 0; + /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ + pinCfgValue |= 0x0113; + /* io_pad_cfg_mode output mode is drive always */ + /* io_pad_cfg_drive is set to power 2 (23 mA) */ + + /* write to io pad configuration register - output mode */ + WR16( demod->myI2CDevAddr, SIO_PDR_SMA_RX_CFG__A, pinCfgValue ); + + /* use corresponding bit in io data output registar */ + RR16( demod->myI2CDevAddr, SIO_PDR_UIO_OUT_LO__A, &value ); + if (UIOData->value == FALSE) + { + value &= 0xBFFF; /* write zero to 14th bit - 2nd UIO */ + } else { + value |= 0x4000; /* write one to 14th bit - 2nd UIO */ + } + /* write back to io data output register */ + WR16( demod->myI2CDevAddr, SIO_PDR_UIO_OUT_LO__A, value ); + break; + /*====================================================================*/ + case DRX_UIO3: + /* DRX_UIO3: ASEL UIO-3 */ + if (extAttr->hasGPIO != TRUE) + return DRX_STS_ERROR; + if ( extAttr->uioGPIOMode != DRX_UIO_MODE_READWRITE ) + { + return DRX_STS_ERROR; + } + pinCfgValue = 0; + /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ + pinCfgValue |= 0x0113; + /* io_pad_cfg_mode output mode is drive always */ + /* io_pad_cfg_drive is set to power 2 (23 mA) */ + + /* write to io pad configuration register - output mode */ + WR16( demod->myI2CDevAddr, SIO_PDR_GPIO_CFG__A, pinCfgValue ); + + /* use corresponding bit in io data output registar */ + RR16( demod->myI2CDevAddr, SIO_PDR_UIO_OUT_HI__A, &value ); + if (UIOData->value == FALSE) + { + value &= 0xFFFB; /* write zero to 2nd bit - 3rd UIO */ + } else { + value |= 0x0004; /* write one to 2nd bit - 3rd UIO */ + } + /* write back to io data output register */ + WR16( demod->myI2CDevAddr, SIO_PDR_UIO_OUT_HI__A, value ); + break; + /*=====================================================================*/ + case DRX_UIO4: + /* DRX_UIO4: IRQN UIO-4 */ + if (extAttr->hasIRQN != TRUE) + return DRX_STS_ERROR; + + if ( extAttr->uioIRQNMode != DRX_UIO_MODE_READWRITE ) + { + return DRX_STS_ERROR; + } + pinCfgValue = 0; + /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ + pinCfgValue |= 0x0113; + /* io_pad_cfg_mode output mode is drive always */ + /* io_pad_cfg_drive is set to power 2 (23 mA) */ + + /* write to io pad configuration register - output mode */ + WR16( demod->myI2CDevAddr, SIO_PDR_IRQN_CFG__A, pinCfgValue ); + + /* use corresponding bit in io data output registar */ + RR16( demod->myI2CDevAddr, SIO_PDR_UIO_OUT_LO__A, &value ); + if (UIOData->value == FALSE) + { + value &= 0xEFFF; /* write zero to 12th bit - 4th UIO */ + } else { + value |= 0x1000; /* write one to 12th bit - 4th UIO */ + } + /* write back to io data output register */ + WR16( demod->myI2CDevAddr, SIO_PDR_UIO_OUT_LO__A, value ); + break; + /*=====================================================================*/ + default: + return DRX_STS_INVALID_ARG; + } /* switch ( UIOData->uio ) */ + + /* Write magic word to disable pdr reg write */ + WR16 ( demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, 0x0000); + + return (DRX_STS_OK); + rw_error: + return (DRX_STS_ERROR); +} + + +/** +*\fn DRXStatus_t CtrlUIORead +*\brief Read from a UIO. +* \param demod Pointer to demodulator instance. +* \param UIOData Pointer to data container for a certain UIO. +* \return DRXStatus_t. +*/ +static DRXStatus_t +CtrlUIORead( pDRXDemodInstance_t demod, + pDRXUIOData_t UIOData) +{ + pDRXJData_t extAttr = (pDRXJData_t)(NULL); + u16_t pinCfgValue = 0; + u16_t value = 0; + + if (( UIOData == NULL ) || ( demod == NULL )) + { + return DRX_STS_INVALID_ARG; + } + + extAttr = (pDRXJData_t)demod -> myExtAttr; + + /* Write magic word to enable pdr reg write */ + WR16( demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY ); + switch ( UIOData->uio ) { + /*====================================================================*/ + case DRX_UIO1: + /* DRX_UIO1: SMA_TX UIO-1 */ + if (extAttr->hasSMATX != TRUE) + return DRX_STS_ERROR; + + if ( extAttr->uioSmaTxMode != DRX_UIO_MODE_READWRITE ) + { + return DRX_STS_ERROR; + } + pinCfgValue = 0; + /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ + pinCfgValue |= 0x0110; + /* io_pad_cfg_mode output mode is drive always */ + /* io_pad_cfg_drive is set to power 2 (23 mA) */ + + /* write to io pad configuration register - input mode */ + WR16( demod->myI2CDevAddr, SIO_PDR_SMA_TX_CFG__A, pinCfgValue ); + + RR16( demod->myI2CDevAddr, SIO_PDR_UIO_IN_LO__A, &value ); + if ( (value & 0x8000) != 0 ) /* check 15th bit - 1st UIO */ + { + UIOData->value = TRUE; + } else { + UIOData->value = FALSE; + } + break; + /*======================================================================*/ + case DRX_UIO2: + /* DRX_UIO2: SMA_RX UIO-2 */ + if (extAttr->hasSMARX != TRUE) + return DRX_STS_ERROR; + + if ( extAttr->uioSmaRxMode != DRX_UIO_MODE_READWRITE ) + { + return DRX_STS_ERROR; + } + pinCfgValue = 0; + /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ + pinCfgValue |= 0x0110; + /* io_pad_cfg_mode output mode is drive always */ + /* io_pad_cfg_drive is set to power 2 (23 mA) */ + + /* write to io pad configuration register - input mode */ + WR16( demod->myI2CDevAddr, SIO_PDR_SMA_RX_CFG__A, pinCfgValue ); + + RR16( demod->myI2CDevAddr, SIO_PDR_UIO_IN_LO__A, &value ); + + if ( (value & 0x4000) != 0 ) /* check 14th bit - 2nd UIO */ + { + UIOData->value = TRUE; + } else { + UIOData->value = FALSE; + } + break; + /*=====================================================================*/ + case DRX_UIO3: + /* DRX_UIO3: GPIO UIO-3 */ + if (extAttr->hasGPIO != TRUE) + return DRX_STS_ERROR; + + if ( extAttr->uioGPIOMode != DRX_UIO_MODE_READWRITE ) + { + return DRX_STS_ERROR; + } + pinCfgValue = 0; + /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ + pinCfgValue |= 0x0110; + /* io_pad_cfg_mode output mode is drive always */ + /* io_pad_cfg_drive is set to power 2 (23 mA) */ + + /* write to io pad configuration register - input mode */ + WR16( demod->myI2CDevAddr, SIO_PDR_GPIO_CFG__A, pinCfgValue ); + + /* read io input data registar */ + RR16( demod->myI2CDevAddr, SIO_PDR_UIO_IN_HI__A, &value ); + if ( (value & 0x0004) != 0 ) /* check 2nd bit - 3rd UIO */ + { + UIOData->value = TRUE; + } else { + UIOData->value = FALSE; + } + break; + /*=====================================================================*/ + case DRX_UIO4: + /* DRX_UIO4: IRQN UIO-4 */ + if (extAttr->hasIRQN != TRUE) + return DRX_STS_ERROR; + + if ( extAttr->uioIRQNMode != DRX_UIO_MODE_READWRITE ) + { + return DRX_STS_ERROR; + } + pinCfgValue = 0; + /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ + pinCfgValue |= 0x0110; + /* io_pad_cfg_mode output mode is drive always */ + /* io_pad_cfg_drive is set to power 2 (23 mA) */ + + /* write to io pad configuration register - input mode */ + WR16( demod->myI2CDevAddr, SIO_PDR_IRQN_CFG__A, pinCfgValue ); + + /* read io input data registar */ + RR16( demod->myI2CDevAddr, SIO_PDR_UIO_IN_LO__A, &value ); + if ( (value & 0x1000) != 0 ) /* check 12th bit - 4th UIO */ + { + UIOData->value = TRUE; + } else { + UIOData->value = FALSE; + } + break; + /*====================================================================*/ + default: + return DRX_STS_INVALID_ARG; + } /* switch ( UIOData->uio ) */ + + /* Write magic word to disable pdr reg write */ + WR16 ( demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, 0x0000); + + return (DRX_STS_OK); + rw_error: + return (DRX_STS_ERROR); +} +/*---------------------------------------------------------------------------*/ +/* UIO Configuration Functions - end */ +/*---------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------*/ +/* I2C Bridge Functions - begin */ +/*----------------------------------------------------------------------------*/ +/** +* \fn DRXStatus_t CtrlI2CBridge() +* \brief Open or close the I2C switch to tuner. +* \param demod Pointer to demodulator instance. +* \param bridgeClosed Pointer to bool indication if bridge is closed not. +* \return DRXStatus_t. + +*/ +static DRXStatus_t +CtrlI2CBridge( pDRXDemodInstance_t demod, + pBool_t bridgeClosed ) +{ + DRXJHiCmd_t hiCmd; + u16_t result = 0; + + /* check arguments */ + if (bridgeClosed == NULL ) + { + return (DRX_STS_INVALID_ARG); + } + + hiCmd.cmd = SIO_HI_RA_RAM_CMD_BRDCTRL; + hiCmd.param1 = SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY; + if (*bridgeClosed == TRUE) + { + hiCmd.param2 = SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED; + } + else + { + hiCmd.param2 = SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN; + } + + return HICommand( demod -> myI2CDevAddr, &hiCmd, &result); +} +/*----------------------------------------------------------------------------*/ +/* I2C Bridge Functions - end */ +/*----------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------*/ +/* Smart antenna Functions - begin */ +/*----------------------------------------------------------------------------*/ +/** +* \fn DRXStatus_t SmartAntInit() +* \brief Initialize Smart Antenna. +* \param pointer to DRXDemodInstance_t. +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +SmartAntInit(pDRXDemodInstance_t demod) +{ + u16_t data = 0; + pDRXJData_t extAttr = NULL; + pI2CDeviceAddr_t devAddr = NULL; + DRXUIOCfg_t UIOCfg = {DRX_UIO1, DRX_UIO_MODE_FIRMWARE_SMA}; + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t) demod -> myExtAttr; + + /* Write magic word to enable pdr reg write */ + WR16( demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY ); + /* init smart antenna */ + RR16( devAddr, SIO_SA_TX_COMMAND__A, &data ); + if (extAttr->smartAntInverted) + WR16( devAddr, SIO_SA_TX_COMMAND__A, + (data | SIO_SA_TX_COMMAND_TX_INVERT__M ) + | SIO_SA_TX_COMMAND_TX_ENABLE__M ); + else + WR16( devAddr, SIO_SA_TX_COMMAND__A, + (data & (~SIO_SA_TX_COMMAND_TX_INVERT__M)) + | SIO_SA_TX_COMMAND_TX_ENABLE__M ); + + /* config SMA_TX pin to smart antenna mode*/ + CHK_ERROR( CtrlSetUIOCfg( demod, &UIOCfg ) ); + WR16( demod->myI2CDevAddr, SIO_PDR_SMA_TX_CFG__A, 0x13 ); + WR16( demod->myI2CDevAddr, SIO_PDR_SMA_TX_GPIO_FNC__A, 0x03 ); + + /* Write magic word to disable pdr reg write */ + WR16( demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, 0x0000 ); + + return ( DRX_STS_OK ); +rw_error: + return (DRX_STS_ERROR); +} + +/** +* \fn DRXStatus_t CtrlSetCfgSmartAnt() +* \brief Set Smart Antenna. +* \param pointer to DRXJCfgSmartAnt_t. +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +CtrlSetCfgSmartAnt ( pDRXDemodInstance_t demod, pDRXJCfgSmartAnt_t smartAnt ) +{ + pDRXJData_t extAttr = NULL; + pI2CDeviceAddr_t devAddr = NULL; + u16_t data = 0; + u32_t startTime = 0; + static Bool_t bitInverted = FALSE; + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* check arguments */ + if ( smartAnt == NULL ) + { + return (DRX_STS_INVALID_ARG); + } + + if ( bitInverted != extAttr->smartAntInverted + || extAttr->uioSmaTxMode != DRX_UIO_MODE_FIRMWARE_SMA) + { + CHK_ERROR(SmartAntInit(demod)); + bitInverted = extAttr->smartAntInverted; + } + + /* Write magic word to enable pdr reg write */ + WR16( demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY ); + + switch (smartAnt->io) + { + case DRXJ_SMT_ANT_OUTPUT: + /* enable Tx if Mode B (input) is supported */ + /* + RR16( devAddr, SIO_SA_TX_COMMAND__A, &data ); + WR16( devAddr, SIO_SA_TX_COMMAND__A, data | SIO_SA_TX_COMMAND_TX_ENABLE__M ); + */ + startTime = DRXBSP_HST_Clock(); + do{ + RR16( devAddr, SIO_SA_TX_STATUS__A, &data ); + } while ( (data & SIO_SA_TX_STATUS_BUSY__M) && ( (DRXBSP_HST_Clock() - startTime) < DRXJ_MAX_WAITTIME ) ); + + if ( data & SIO_SA_TX_STATUS_BUSY__M ) + { + return (DRX_STS_ERROR); + } + + /* write to smart antenna configuration register */ + WR16( devAddr, SIO_SA_TX_DATA0__A, 0x9200 + | ((smartAnt->ctrlData & 0x0001) << 8) + | ((smartAnt->ctrlData & 0x0002) << 10) + | ((smartAnt->ctrlData & 0x0004) << 12) + ); + WR16( devAddr, SIO_SA_TX_DATA1__A, 0x4924 + | ((smartAnt->ctrlData & 0x0008) >> 2) + | ((smartAnt->ctrlData & 0x0010) ) + | ((smartAnt->ctrlData & 0x0020) << 2) + | ((smartAnt->ctrlData & 0x0040) << 4) + | ((smartAnt->ctrlData & 0x0080) << 6) + ); + WR16( devAddr, SIO_SA_TX_DATA2__A, 0x2492 + | ((smartAnt->ctrlData & 0x0100) >> 8) + | ((smartAnt->ctrlData & 0x0200) >> 6) + | ((smartAnt->ctrlData & 0x0400) >> 4) + | ((smartAnt->ctrlData & 0x0800) >> 2) + | ((smartAnt->ctrlData & 0x1000) ) + | ((smartAnt->ctrlData & 0x2000) << 2) + ); + WR16( devAddr, SIO_SA_TX_DATA3__A, 0xff8d ); + + /* trigger the sending */ + WR16( devAddr, SIO_SA_TX_LENGTH__A, 56 ); + + break; + case DRXJ_SMT_ANT_INPUT: + /* disable Tx if Mode B (input) is supported */ + /* + RR16( devAddr, SIO_SA_TX_COMMAND__A, &data ); + WR16( devAddr, SIO_SA_TX_COMMAND__A, data & (~SIO_SA_TX_COMMAND_TX_ENABLE__M) ); + */ + default: + return (DRX_STS_INVALID_ARG); + } + /* Write magic word to enable pdr reg write */ + WR16( demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, 0x0000 ); + + return ( DRX_STS_OK ); +rw_error: + return (DRX_STS_ERROR); +} + +static DRXStatus_t +SCUCommand( pI2CDeviceAddr_t devAddr, pDRXJSCUCmd_t cmd ) +{ + u16_t curCmd = 0; + u32_t startTime = 0; + + /* Check param */ + if ( cmd == NULL ) + return (DRX_STS_INVALID_ARG); + + /* Wait until SCU command interface is ready to receive command */ + RR16( devAddr, SCU_RAM_COMMAND__A, &curCmd ); + if ( curCmd != DRX_SCU_READY ) + { + return (DRX_STS_ERROR); + } + + switch ( cmd->parameterLen ) + { + case 5: + WR16( devAddr, SCU_RAM_PARAM_4__A , *(cmd->parameter + 4)); /* fallthrough */ + case 4: + WR16( devAddr, SCU_RAM_PARAM_3__A , *(cmd->parameter + 3)); /* fallthrough */ + case 3: + WR16( devAddr, SCU_RAM_PARAM_2__A , *(cmd->parameter + 2)); /* fallthrough */ + case 2: + WR16( devAddr, SCU_RAM_PARAM_1__A , *(cmd->parameter + 1)); /* fallthrough */ + case 1: + WR16( devAddr, SCU_RAM_PARAM_0__A , *(cmd->parameter + 0)); /* fallthrough */ + case 0: + /* do nothing */ + break; + default: + /* this number of parameters is not supported */ + return (DRX_STS_ERROR); + } + WR16( devAddr, SCU_RAM_COMMAND__A, cmd->command ); + + /* Wait until SCU has processed command */ + startTime = DRXBSP_HST_Clock(); + do{ + RR16( devAddr, SCU_RAM_COMMAND__A, &curCmd ); + } while ( ! ( curCmd == DRX_SCU_READY ) && ( (DRXBSP_HST_Clock() - startTime) < DRXJ_MAX_WAITTIME ) ); + + if ( curCmd != DRX_SCU_READY ) + { + return (DRX_STS_ERROR); + } + + /* read results */ + if ( (cmd->resultLen > 0) && (cmd->result != NULL) ) + { + s16_t err; + + switch ( cmd->resultLen ) + { + case 4: + RR16( devAddr, SCU_RAM_PARAM_3__A , cmd->result + 3); /* fallthrough */ + case 3: + RR16( devAddr, SCU_RAM_PARAM_2__A , cmd->result + 2); /* fallthrough */ + case 2: + RR16( devAddr, SCU_RAM_PARAM_1__A , cmd->result + 1); /* fallthrough */ + case 1: + RR16( devAddr, SCU_RAM_PARAM_0__A , cmd->result + 0); /* fallthrough */ + case 0: + /* do nothing */ + break; + default: + /* this number of parameters is not supported */ + return (DRX_STS_ERROR); + } + + + /* Check if an error was reported by SCU */ + err = cmd->result[0]; + + /* check a few fixed error codes */ + if ( ( err == (s16_t)SCU_RAM_PARAM_0_RESULT_UNKSTD ) + || ( err == (s16_t)SCU_RAM_PARAM_0_RESULT_UNKCMD ) + || ( err == (s16_t)SCU_RAM_PARAM_0_RESULT_INVPAR ) + || ( err == (s16_t)SCU_RAM_PARAM_0_RESULT_SIZE ) + ) + { + return DRX_STS_INVALID_ARG; + } + /* here it is assumed that negative means error, and positive no error */ + else if ( err < 0 ) + { + return DRX_STS_ERROR; + } + else + { + return DRX_STS_OK; + } + } + + return (DRX_STS_OK); + + rw_error: + return (DRX_STS_ERROR); +} +/** +* \fn DRXStatus_t DRXJ_DAP_SCUAtomicReadWriteBlock() +* \brief Basic access routine for SCU atomic read or write access +* \param devAddr pointer to i2c dev address +* \param addr destination/source address +* \param datasize size of data buffer in bytes +* \param data pointer to data buffer +* \return DRXStatus_t +* \retval DRX_STS_OK Succes +* \retval DRX_STS_ERROR Timeout, I2C error, illegal bank +* +*/ +#define ADDR_AT_SCU_SPACE(x) ((x - 0x82E000) * 2) +static +DRXStatus_t DRXJ_DAP_SCU_AtomicReadWriteBlock ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + u16_t datasize, /* max 30 bytes because the limit of SCU parameter */ + pu8_t data, + Bool_t readFlag) +{ + DRXJSCUCmd_t scuCmd; + u16_t setParamParameters[15]; + u16_t cmdResult[15]; + + /* Parameter check */ + if ( ( data == NULL ) || + ( devAddr == NULL ) || + ( (datasize%2)!= 0 ) || + ( (datasize/2) > 16 ) + ) + { + return (DRX_STS_INVALID_ARG); + } + + setParamParameters[1] = (u16_t)ADDR_AT_SCU_SPACE (addr); + if (readFlag) /* read */ + { + setParamParameters[0] = ((~(0x0080)) & datasize); + scuCmd.parameterLen = 2; + scuCmd.resultLen = datasize/2 + 2; + } else { + int i = 0; + + setParamParameters[0] = 0x0080 | datasize; + for (i = 0; i < (datasize/2); i++) + { + setParamParameters[i+2] = (data[2*i] | (data[(2*i)+1]<<8)); + } + scuCmd.parameterLen = datasize / 2 + 2; + scuCmd.resultLen = 1; + } + + scuCmd.command = SCU_RAM_COMMAND_STANDARD_TOP | SCU_RAM_COMMAND_CMD_AUX_SCU_ATOMIC_ACCESS; + scuCmd.result = cmdResult; + scuCmd.parameter = setParamParameters; + CHK_ERROR( SCUCommand( devAddr, &scuCmd ) ); + + if ( readFlag==TRUE ) + { + int i = 0; + /* read data from buffer */ + for (i = 0; i < (datasize/2); i++) + { + data[2*i] = (u8_t) (scuCmd.result[i+2] & 0xFF); + data[(2*i) + 1] = (u8_t) (scuCmd.result[i+2] >> 8 ); + } + } + + return DRX_STS_OK; + + rw_error: + return (DRX_STS_ERROR); + +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t DRXJ_DAP_AtomicReadReg16() +* \brief Atomic read of 16 bits words +*/ +static +DRXStatus_t DRXJ_DAP_SCU_AtomicReadReg16 ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + pu16_t data, + DRXflags_t flags) +{ + u8_t buf[2]; + DRXStatus_t rc = DRX_STS_ERROR; + u16_t word = 0; + + if (!data) + { + return DRX_STS_INVALID_ARG; + } + + rc = DRXJ_DAP_SCU_AtomicReadWriteBlock ( devAddr, addr, + 2, buf, TRUE); + + word = (u16_t)(buf[0] + (buf[1] << 8)); + + *data = word; + + return rc; +} +/*============================================================================*/ +/** +* \fn DRXStatus_t DRXJ_DAP_SCU_AtomicWriteReg16() +* \brief Atomic read of 16 bits words +*/ +static +DRXStatus_t DRXJ_DAP_SCU_AtomicWriteReg16 ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + u16_t data, + DRXflags_t flags) +{ + u8_t buf[2]; + DRXStatus_t rc = DRX_STS_ERROR; + + buf[0] = (u8_t) (data & 0xff); + buf[1] = (u8_t) ((data >> 8) & 0xff); + + rc = DRXJ_DAP_SCU_AtomicReadWriteBlock ( devAddr, addr, + 2, buf, FALSE); + + return rc; +} + +static DRXStatus_t +CtrlI2CWriteRead( pDRXDemodInstance_t demod, + pDRXI2CData_t i2cData ) +{ + return (DRX_STS_FUNC_NOT_AVAILABLE); +} + +DRXStatus_t +TunerI2CWriteRead( pTUNERInstance_t tuner, + pI2CDeviceAddr_t wDevAddr, + u16_t wCount, + pu8_t wData, + pI2CDeviceAddr_t rDevAddr, + u16_t rCount, + pu8_t rData) +{ + pDRXDemodInstance_t demod; + DRXI2CData_t i2cData = { 2, wDevAddr, wCount, wData, rDevAddr, rCount, rData }; + + demod = (pDRXDemodInstance_t) (tuner->myCommonAttr->myUserData); + + return ( CtrlI2CWriteRead( demod, &i2cData ) ); +} + +/* -------------------------------------------------------------------------- */ +/** +* \brief Measure result of ADC synchronisation +* \param demod demod instance +* \param count (returned) count +* \return DRXStatus_t. +* \retval DRX_STS_OK Success +* \retval DRX_STS_ERROR Failure: I2C error +* +*/ +static DRXStatus_t +ADCSyncMeasurement( pDRXDemodInstance_t demod, + pu16_t count ) +{ + u16_t data = 0; + pI2CDeviceAddr_t devAddr = NULL; + + devAddr = demod -> myI2CDevAddr; + + /* Start measurement */ + WR16( devAddr, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE); + WR16( devAddr, IQM_AF_START_LOCK__A, 1); + + /* Wait at least 3*128*(1/sysclk) <<< 1 millisec */ + CHK_ERROR( DRXBSP_HST_Sleep(1)); + + *count = 0; + RR16( devAddr, IQM_AF_PHASE0__A, &data); + if ( data == 127 ) + { + *count = *count+1; + } + RR16( devAddr, IQM_AF_PHASE1__A, &data); + if ( data == 127 ) + { + *count = *count+1; + } + RR16( devAddr, IQM_AF_PHASE2__A, &data); + if ( data == 127 ) + { + *count = *count+1; + } + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/** +* \brief Synchronize analog and digital clock domains +* \param demod demod instance +* \return DRXStatus_t. +* \retval DRX_STS_OK Success +* \retval DRX_STS_ERROR Failure: I2C error or failure to synchronize +* +* An IQM reset will also reset the results of this synchronization. +* After an IQM reset this routine needs to be called again. +* +*/ + +static DRXStatus_t +ADCSynchronization( pDRXDemodInstance_t demod ) +{ + u16_t count = 0; + pI2CDeviceAddr_t devAddr = NULL; + + devAddr = demod -> myI2CDevAddr; + + CHK_ERROR( ADCSyncMeasurement( demod, &count )); + + if (count==1) + { + /* Try sampling on a diffrent edge */ + u16_t clkNeg = 0; + + RR16( devAddr, IQM_AF_CLKNEG__A, &clkNeg); + + clkNeg ^= IQM_AF_CLKNEG_CLKNEGDATA__M; + WR16( devAddr, IQM_AF_CLKNEG__A, clkNeg); + + CHK_ERROR( ADCSyncMeasurement( demod, &count )); + } + + if ( count < 2 ) + { + /* TODO: implement fallback scenarios */ + return (DRX_STS_ERROR); + } + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/** +* \brief Configure IQM AF registers +* \param demod instance of demodulator. +* \param active +* \return DRXStatus_t. +*/ +static DRXStatus_t +IQMSetAf ( pDRXDemodInstance_t demod, Bool_t active ) +{ + u16_t data = 0; + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + + extAttr = (pDRXJData_t)demod->myExtAttr; + devAddr = demod -> myI2CDevAddr; + + /* Configure IQM */ + RR16( devAddr, IQM_AF_STDBY__A , &data ); + if( !active ) + { + data &= ((~IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE) + & (~IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE) + & (~IQM_AF_STDBY_STDBY_PD_A2_ACTIVE) + & (~IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE) + & (~IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE) + ); + } else /* active */ + { + data |= (IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE + | IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE + | IQM_AF_STDBY_STDBY_PD_A2_ACTIVE + | IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE + | IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE + ); + } + WR16( devAddr, IQM_AF_STDBY__A , data ); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/* -------------------------------------------------------------------------- */ +static DRXStatus_t +CtrlSetCfgATVOutput( pDRXDemodInstance_t demod , + pDRXJCfgAtvOutput_t outputCfg ); + +/** +* \brief set configuration of pin-safe mode +* \param demod instance of demodulator. +* \param enable boolean; TRUE: activate pin-safe mode, FALSE: de-activate p.s.m. +* \return DRXStatus_t. +*/ +static DRXStatus_t +CtrlSetCfgPdrSafeMode ( pDRXDemodInstance_t demod, + pBool_t enable ) +{ + pDRXJData_t extAttr = (pDRXJData_t) NULL; + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) NULL; + pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) NULL; + + if ( enable == NULL) + { + return (DRX_STS_INVALID_ARG); + } + + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; + commonAttr = demod->myCommonAttr; + + /* Write magic word to enable pdr reg write */ + WR16( devAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY ); + + if ( *enable == TRUE ) + { + Bool_t bridgeEnabled = FALSE; + + /* MPEG pins to input */ + WR16 ( devAddr, SIO_PDR_MSTRT_CFG__A, DRXJ_PIN_SAFE_MODE ); + WR16 ( devAddr, SIO_PDR_MERR_CFG__A, DRXJ_PIN_SAFE_MODE ); + WR16 ( devAddr, SIO_PDR_MCLK_CFG__A, DRXJ_PIN_SAFE_MODE ); + WR16 ( devAddr, SIO_PDR_MVAL_CFG__A, DRXJ_PIN_SAFE_MODE ); + WR16 ( devAddr, SIO_PDR_MD0_CFG__A, DRXJ_PIN_SAFE_MODE ); + WR16 ( devAddr, SIO_PDR_MD1_CFG__A, DRXJ_PIN_SAFE_MODE ); + WR16 ( devAddr, SIO_PDR_MD2_CFG__A, DRXJ_PIN_SAFE_MODE ); + WR16 ( devAddr, SIO_PDR_MD3_CFG__A, DRXJ_PIN_SAFE_MODE ); + WR16 ( devAddr, SIO_PDR_MD4_CFG__A, DRXJ_PIN_SAFE_MODE ); + WR16 ( devAddr, SIO_PDR_MD5_CFG__A, DRXJ_PIN_SAFE_MODE ); + WR16 ( devAddr, SIO_PDR_MD6_CFG__A, DRXJ_PIN_SAFE_MODE ); + WR16 ( devAddr, SIO_PDR_MD7_CFG__A, DRXJ_PIN_SAFE_MODE ); + + /* PD_I2C_SDA2 Bridge off, Port2 Inactive + PD_I2C_SCL2 Bridge off, Port2 Inactive */ + CHK_ERROR( CtrlI2CBridge( demod, &bridgeEnabled ) ); + WR16 ( devAddr, SIO_PDR_I2C_SDA2_CFG__A, DRXJ_PIN_SAFE_MODE ); + WR16 ( devAddr, SIO_PDR_I2C_SCL2_CFG__A, DRXJ_PIN_SAFE_MODE ); + + /* PD_GPIO Store and set to input + PD_VSYNC Store and set to input + PD_SMA_RX Store and set to input + PD_SMA_TX Store and set to input */ + RR16 ( devAddr, SIO_PDR_GPIO_CFG__A, &extAttr->pdrSafeRestoreValGpio ); + RR16 ( devAddr, SIO_PDR_VSYNC_CFG__A, &extAttr->pdrSafeRestoreValVSync ); + RR16 ( devAddr, SIO_PDR_SMA_RX_CFG__A, &extAttr->pdrSafeRestoreValSmaRx ); + RR16 ( devAddr, SIO_PDR_SMA_TX_CFG__A, &extAttr->pdrSafeRestoreValSmaTx ); + WR16 ( devAddr, SIO_PDR_GPIO_CFG__A, DRXJ_PIN_SAFE_MODE ); + WR16 ( devAddr, SIO_PDR_VSYNC_CFG__A, DRXJ_PIN_SAFE_MODE ); + WR16 ( devAddr, SIO_PDR_SMA_RX_CFG__A, DRXJ_PIN_SAFE_MODE ); + WR16 ( devAddr, SIO_PDR_SMA_TX_CFG__A, DRXJ_PIN_SAFE_MODE ); + + /* PD_RF_AGC Analog DAC outputs, cannot be set to input or tristate! + PD_IF_AGC Analog DAC outputs, cannot be set to input or tristate! */ + CHK_ERROR( IQMSetAf ( demod, FALSE ) ); + + /* PD_CVBS Analog DAC output, standby mode + PD_SIF Analog DAC output, standby mode */ + WR16 ( devAddr, ATV_TOP_STDBY__A, ( ATV_TOP_STDBY_SIF_STDBY_STANDBY & + (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE) ) ); + + /* PD_I2S_CL Input + PD_I2S_DA Input + PD_I2S_WS Input */ + WR16 ( devAddr, SIO_PDR_I2S_CL_CFG__A, DRXJ_PIN_SAFE_MODE ); + WR16 ( devAddr, SIO_PDR_I2S_DA_CFG__A, DRXJ_PIN_SAFE_MODE ); + WR16 ( devAddr, SIO_PDR_I2S_WS_CFG__A, DRXJ_PIN_SAFE_MODE ); + } + else + { + /* No need to restore MPEG pins; + is done in SetStandard/SetChannel */ + + /* PD_I2C_SDA2 Port2 active + PD_I2C_SCL2 Port2 active */ + WR16 ( devAddr, SIO_PDR_I2C_SDA2_CFG__A, SIO_PDR_I2C_SDA2_CFG__PRE ); + WR16 ( devAddr, SIO_PDR_I2C_SCL2_CFG__A, SIO_PDR_I2C_SCL2_CFG__PRE ); + + /* PD_GPIO Restore + PD_VSYNC Restore + PD_SMA_RX Restore + PD_SMA_TX Restore */ + WR16 ( devAddr, SIO_PDR_GPIO_CFG__A, extAttr->pdrSafeRestoreValGpio ); + WR16 ( devAddr, SIO_PDR_VSYNC_CFG__A, extAttr->pdrSafeRestoreValVSync ); + WR16 ( devAddr, SIO_PDR_SMA_RX_CFG__A, extAttr->pdrSafeRestoreValSmaRx ); + WR16 ( devAddr, SIO_PDR_SMA_TX_CFG__A, extAttr->pdrSafeRestoreValSmaTx ); + + /* PD_RF_AGC, PD_IF_AGC + No need to restore; will be restored in SetStandard/SetChannel */ + + /* PD_CVBS, PD_SIF + No need to restore; will be restored in SetStandard/SetChannel */ + + /* PD_I2S_CL, PD_I2S_DA, PD_I2S_WS + Should be restored via DRX_CTRL_SET_AUD */ + } + + /* Write magic word to disable pdr reg write */ + WR16 ( devAddr, SIO_TOP_COMM_KEY__A, 0x0000 ); + extAttr->pdrSafeMode = *enable; + + return (DRX_STS_OK); + + rw_error: + return (DRX_STS_ERROR); +} + +/* -------------------------------------------------------------------------- */ + +/** +* \brief get configuration of pin-safe mode +* \param demod instance of demodulator. +* \param enable boolean indicating whether pin-safe mode is active +* \return DRXStatus_t. +*/ +static DRXStatus_t +CtrlGetCfgPdrSafeMode ( pDRXDemodInstance_t demod, + pBool_t enabled ) +{ + pDRXJData_t extAttr = (pDRXJData_t) NULL; + + if ( enabled == NULL ) + { + return (DRX_STS_INVALID_ARG); + } + + extAttr = (pDRXJData_t) demod->myExtAttr; + *enabled = extAttr->pdrSafeMode; + + return (DRX_STS_OK); +} + +/** +* \brief Verifies whether microcode can be loaded. +* \param demod Demodulator instance. +* \return DRXStatus_t. +*/ +static DRXStatus_t +CtrlValidateUCode (pDRXDemodInstance_t demod) +{ + u32_t mcDev, mcPatch; + u16_t verType; + + /* Check device. + * Disallow microcode if: + * - MC has version record AND + * - device ID in version record is not 0 AND + * - product ID in version record's device ID does not + * match DRXJ1 product IDs - 0x393 or 0x394 + */ + DRX_GET_MCVERTYPE (demod, verType); + DRX_GET_MCDEV (demod, mcDev); + DRX_GET_MCPATCH (demod, mcPatch); + + if (DRX_ISMCVERTYPE (verType)) + { + if ((mcDev != 0) && + (((mcDev >> 16) & 0xFFF) != 0x393) && + (((mcDev >> 16) & 0xFFF) != 0x394)) + { + /* Microcode is marked for another device - error */ + return DRX_STS_INVALID_ARG; + } + else if (mcPatch != 0) + { + /* Patch not allowed because there is no ROM */ + return DRX_STS_INVALID_ARG; + } + } + + /* Everything else: OK */ + return DRX_STS_OK; +} + +/*============================================================================*/ +/*== END AUXILIARY FUNCTIONS ==*/ +/*============================================================================*/ + +/*============================================================================*/ +/*============================================================================*/ +/*== 8VSB & QAM COMMON DATAPATH FUNCTIONS ==*/ +/*============================================================================*/ +/*============================================================================*/ +/** +* \fn DRXStatus_t InitAGC () +* \brief Initialize AGC for all standards. +* \param demod instance of demodulator. +* \param channel pointer to channel data. +* \return DRXStatus_t. +*/ +static DRXStatus_t +InitAGC ( pDRXDemodInstance_t demod ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXCommonAttr_t commonAttr = NULL; + pDRXJData_t extAttr = NULL; + pDRXJCfgAgc_t pAgcRfSettings = NULL; + pDRXJCfgAgc_t pAgcIfSettings = NULL; + u16_t IngainTgtMax = 0; + u16_t clpDirTo = 0; + u16_t snsSumMax = 0; + u16_t clpSumMax = 0; + u16_t snsDirTo = 0; + u16_t kiInnergainMin = 0; + u16_t agcKi = 0; + u16_t kiMax = 0; + u16_t ifIaccuHiTgtMin = 0; + u16_t data = 0; + u16_t agcKiDgain = 0; + u16_t kiMin = 0; + u16_t clpCtrlMode = 0; + u16_t agcRf = 0; + u16_t agcIf = 0; + devAddr = demod->myI2CDevAddr; + commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + switch (extAttr->standard) + { + case DRX_STANDARD_8VSB : + clpSumMax = 1023; + clpDirTo = (u16_t)(-9); + snsSumMax = 1023; + snsDirTo = (u16_t)(-9); + kiInnergainMin = (u16_t)(-32768); + kiMax = 0x032C; + agcKiDgain = 0xC; + ifIaccuHiTgtMin = 2047; + kiMin = 0x0117; + IngainTgtMax = 16383; + clpCtrlMode = 0; + WR16( devAddr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff ); + WR16( devAddr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0 ); + WR16( devAddr, SCU_RAM_AGC_CLP_SUM__A, 0 ); + WR16( devAddr, SCU_RAM_AGC_CLP_CYCCNT__A, 0 ); + WR16( devAddr, SCU_RAM_AGC_CLP_DIR_WD__A, 0 ); + WR16( devAddr, SCU_RAM_AGC_CLP_DIR_STP__A, 1 ); + WR16( devAddr, SCU_RAM_AGC_SNS_SUM__A, 0 ); + WR16( devAddr, SCU_RAM_AGC_SNS_CYCCNT__A, 0 ); + WR16( devAddr, SCU_RAM_AGC_SNS_DIR_WD__A, 0 ); + WR16( devAddr, SCU_RAM_AGC_SNS_DIR_STP__A, 1 ); + WR16( devAddr, SCU_RAM_AGC_INGAIN__A, 1024 ); + WR16( devAddr, SCU_RAM_VSB_AGC_POW_TGT__A, 22600 ); + WR16( devAddr, SCU_RAM_AGC_INGAIN_TGT__A, 13200 ); + pAgcIfSettings = &(extAttr->vsbIfAgcCfg); + pAgcRfSettings = &(extAttr->vsbRfAgcCfg); + break; +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_C: + case DRX_STANDARD_ITU_B: + IngainTgtMax = 5119; + clpSumMax = 1023; + clpDirTo = (u16_t)(-5); + snsSumMax = 127; + snsDirTo = (u16_t)(-3); + kiInnergainMin = 0; + kiMax = 0x0657; + ifIaccuHiTgtMin = 2047; + agcKiDgain = 0x7; + kiMin = 0x0117; + clpCtrlMode = 0; + WR16( devAddr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff ); + WR16( devAddr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0 ); + WR16( devAddr, SCU_RAM_AGC_CLP_SUM__A, 0 ); + WR16( devAddr, SCU_RAM_AGC_CLP_CYCCNT__A, 0 ); + WR16( devAddr, SCU_RAM_AGC_CLP_DIR_WD__A, 0 ); + WR16( devAddr, SCU_RAM_AGC_CLP_DIR_STP__A, 1 ); + WR16( devAddr, SCU_RAM_AGC_SNS_SUM__A, 0 ); + WR16( devAddr, SCU_RAM_AGC_SNS_CYCCNT__A, 0 ); + WR16( devAddr, SCU_RAM_AGC_SNS_DIR_WD__A, 0 ); + WR16( devAddr, SCU_RAM_AGC_SNS_DIR_STP__A, 1 ); + pAgcIfSettings = &(extAttr->qamIfAgcCfg); + pAgcRfSettings = &(extAttr->qamRfAgcCfg); + WR16( devAddr, SCU_RAM_AGC_INGAIN_TGT__A, pAgcIfSettings->top ); + + RR16( devAddr, SCU_RAM_AGC_KI__A, &agcKi ); + agcKi &= 0xf000; + WR16( devAddr, SCU_RAM_AGC_KI__A, agcKi ); + break; +#endif +#ifndef DRXJ_DIGITAL_ONLY + case DRX_STANDARD_FM: + clpSumMax = 1023; + snsSumMax = 1023; + kiInnergainMin = (u16_t)(-32768); + ifIaccuHiTgtMin = 2047; + agcKiDgain = 0x7; + kiMin = 0x0225; + kiMax = 0x0547; + clpDirTo = (u16_t)(-9); + snsDirTo = (u16_t)(-9); + IngainTgtMax = 9000; + clpCtrlMode = 1; + pAgcIfSettings = &(extAttr->atvIfAgcCfg); + pAgcRfSettings = &(extAttr->atvRfAgcCfg); + WR16( devAddr, SCU_RAM_AGC_INGAIN_TGT__A, pAgcIfSettings->top ); + break; + case DRX_STANDARD_NTSC: + case DRX_STANDARD_PAL_SECAM_BG: + case DRX_STANDARD_PAL_SECAM_DK: + case DRX_STANDARD_PAL_SECAM_I : + clpSumMax = 1023; + snsSumMax = 1023; + kiInnergainMin = (u16_t)(-32768); + ifIaccuHiTgtMin = 2047; + agcKiDgain = 0x7; + kiMin = 0x0225; + kiMax = 0x0547; + clpDirTo = (u16_t)(-9); + IngainTgtMax = 9000; + pAgcIfSettings = &(extAttr->atvIfAgcCfg); + pAgcRfSettings = &(extAttr->atvRfAgcCfg); + snsDirTo = (u16_t)(-9); + clpCtrlMode = 1; + WR16( devAddr, SCU_RAM_AGC_INGAIN_TGT__A, pAgcIfSettings->top ); + break; + case DRX_STANDARD_PAL_SECAM_L : + case DRX_STANDARD_PAL_SECAM_LP: + clpSumMax = 1023; + snsSumMax = 1023; + kiInnergainMin = (u16_t)(-32768); + ifIaccuHiTgtMin = 2047; + agcKiDgain = 0x7; + kiMin = 0x0225; + kiMax = 0x0547; + clpDirTo = (u16_t)(-9); + snsDirTo = (u16_t)(-9); + IngainTgtMax = 9000; + clpCtrlMode = 1; + pAgcIfSettings = &(extAttr->atvIfAgcCfg); + pAgcRfSettings = &(extAttr->atvRfAgcCfg); + WR16( devAddr, SCU_RAM_AGC_INGAIN_TGT__A, pAgcIfSettings->top ); + break; +#endif + default: + return ( DRX_STS_INVALID_ARG ); + } + + /* for new AGC interface */ + WR16( devAddr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, pAgcIfSettings->top ); + WR16( devAddr, SCU_RAM_AGC_INGAIN__A, pAgcIfSettings->top ); /* Gain fed from inner to outer AGC */ + WR16( devAddr, SCU_RAM_AGC_INGAIN_TGT_MAX__A, IngainTgtMax ); + WR16( devAddr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, ifIaccuHiTgtMin ); + WR16( devAddr, SCU_RAM_AGC_IF_IACCU_HI__A, 0 ); /* set to pAgcSettings->top before */ + WR16( devAddr, SCU_RAM_AGC_IF_IACCU_LO__A, 0 ); + WR16( devAddr, SCU_RAM_AGC_RF_IACCU_HI__A, 0 ); + WR16( devAddr, SCU_RAM_AGC_RF_IACCU_LO__A, 0 ); + WR16( devAddr, SCU_RAM_AGC_RF_MAX__A, 32767 ); + WR16( devAddr, SCU_RAM_AGC_CLP_SUM_MAX__A, clpSumMax ); + WR16( devAddr, SCU_RAM_AGC_SNS_SUM_MAX__A, snsSumMax ); + WR16( devAddr, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, kiInnergainMin ); + WR16( devAddr, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50 ); + WR16( devAddr, SCU_RAM_AGC_KI_CYCLEN__A, 500 ); + WR16( devAddr, SCU_RAM_AGC_SNS_CYCLEN__A, 500 ); + WR16( devAddr, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20 ); + WR16( devAddr, SCU_RAM_AGC_KI_MIN__A, kiMin ); + WR16( devAddr, SCU_RAM_AGC_KI_MAX__A, kiMax ); + WR16( devAddr, SCU_RAM_AGC_KI_RED__A, 0 ); + WR16( devAddr, SCU_RAM_AGC_CLP_SUM_MIN__A, 8 ); + WR16( devAddr, SCU_RAM_AGC_CLP_CYCLEN__A, 500 ); + WR16( devAddr, SCU_RAM_AGC_CLP_DIR_TO__A, clpDirTo ); + WR16( devAddr, SCU_RAM_AGC_SNS_SUM_MIN__A, 8 ); + WR16( devAddr, SCU_RAM_AGC_SNS_DIR_TO__A, snsDirTo ); + WR16( devAddr, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, 50 ); + WR16( devAddr, SCU_RAM_AGC_CLP_CTRL_MODE__A, clpCtrlMode ); + + agcRf = 0x800 + pAgcRfSettings->cutOffCurrent; + if ( commonAttr->tunerRfAgcPol == TRUE ) + { + agcRf = 0x87ff - agcRf; + } + + agcIf = 0x800; + if ( commonAttr->tunerIfAgcPol == TRUE ) + { + agcRf = 0x87ff - agcRf; + } + + WR16( devAddr, IQM_AF_AGC_RF__A, agcRf ); + WR16( devAddr, IQM_AF_AGC_IF__A, agcIf ); + + /* Set/restore Ki DGAIN factor */ + RR16( devAddr, SCU_RAM_AGC_KI__A, &data ); + data &= ~SCU_RAM_AGC_KI_DGAIN__M; + data |= ( agcKiDgain << SCU_RAM_AGC_KI_DGAIN__B ); + WR16( devAddr, SCU_RAM_AGC_KI__A, data ); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/** +* \fn DRXStatus_t SetFrequency () +* \brief Set frequency shift. +* \param demod instance of demodulator. +* \param channel pointer to channel data. +* \param tunerFreqOffset residual frequency from tuner. +* \return DRXStatus_t. +*/ +static DRXStatus_t +SetFrequency ( pDRXDemodInstance_t demod, + pDRXChannel_t channel, + DRXFrequency_t tunerFreqOffset + ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXCommonAttr_t commonAttr = NULL; + DRXFrequency_t samplingFrequency = 0; + DRXFrequency_t frequencyShift = 0; + DRXFrequency_t ifFreqActual = 0; + DRXFrequency_t rfFreqResidual = 0; + DRXFrequency_t adcFreq = 0; + DRXFrequency_t intermediateFreq = 0; + u32_t iqmFsRateOfs = 0; + pDRXJData_t extAttr = NULL; + Bool_t adcFlip = TRUE; + Bool_t selectPosImage = FALSE; + Bool_t rfMirror = FALSE; + Bool_t tunerMirror = TRUE; + Bool_t imageToSelect = TRUE; + DRXFrequency_t fmFrequencyShift = 0; + + devAddr = demod -> myI2CDevAddr; + commonAttr = (pDRXCommonAttr_t) demod -> myCommonAttr; + extAttr = (pDRXJData_t)demod->myExtAttr; + rfFreqResidual = -1 * tunerFreqOffset; + rfMirror = (extAttr->mirror == DRX_MIRROR_YES)?TRUE:FALSE; + tunerMirror = demod->myCommonAttr->mirrorFreqSpect?FALSE:TRUE; + /* + Program frequency shifter + No need to account for mirroring on RF + */ + switch (extAttr->standard) + { + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_C: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_LP: /* fallthrough */ + case DRX_STANDARD_8VSB: + selectPosImage = TRUE; + break; + case DRX_STANDARD_FM: + /* After IQM FS sound carrier must appear at 4 Mhz in spect. + Sound carrier is already 3Mhz above centre frequency due + to tuner setting so now add an extra shift of 1MHz... */ + fmFrequencyShift = 1000; + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_NTSC: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_L: + selectPosImage = FALSE; + break; + default: + return ( DRX_STS_INVALID_ARG ); + } + intermediateFreq = demod->myCommonAttr->intermediateFreq; + samplingFrequency = demod->myCommonAttr->sysClockFreq/3; + if ( tunerMirror == TRUE ) + { + /* tuner doesn't mirror */ + ifFreqActual = intermediateFreq + rfFreqResidual + fmFrequencyShift; + } else { + /* tuner mirrors */ + ifFreqActual = intermediateFreq - rfFreqResidual - fmFrequencyShift; + } + if ( ifFreqActual > samplingFrequency / 2) + { + /* adc mirrors */ + adcFreq = samplingFrequency - ifFreqActual; + adcFlip = TRUE; + } else { + /* adc doesn't mirror */ + adcFreq = ifFreqActual; + adcFlip = FALSE; + } + + frequencyShift = adcFreq; + imageToSelect = (Bool_t)(rfMirror ^ tunerMirror ^ adcFlip ^ selectPosImage); + iqmFsRateOfs = Frac28(frequencyShift,samplingFrequency); + + if (imageToSelect) + iqmFsRateOfs = ~iqmFsRateOfs + 1; + + /* Program frequency shifter with tuner offset compensation */ + /* frequencyShift += tunerFreqOffset; TODO */ + WR32( devAddr, IQM_FS_RATE_OFS_LO__A , iqmFsRateOfs ); + extAttr->iqmFsRateOfs = iqmFsRateOfs; + extAttr->posImage = (Bool_t)(rfMirror ^ tunerMirror ^ selectPosImage); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/** +* \fn DRXStatus_t GetSigStrength() +* \brief Retrieve signal strength for VSB and QAM. +* \param demod Pointer to demod instance +* \param u16-t Pointer to signal strength data; range 0, .. , 100. +* \return DRXStatus_t. +* \retval DRX_STS_OK sigStrength contains valid data. +* \retval DRX_STS_INVALID_ARG sigStrength is NULL. +* \retval DRX_STS_ERROR Erroneous data, sigStrength contains invalid data. +*/ +#define DRXJ_AGC_TOP 0x2800 +#define DRXJ_AGC_SNS 0x1600 +#define DRXJ_RFAGC_MAX 0x3fff +#define DRXJ_RFAGC_MIN 0x800 + +static DRXStatus_t +GetSigStrength( pDRXDemodInstance_t demod, + pu16_t sigStrength ) +{ + u16_t rfGain = 0; + u16_t ifGain = 0; + u16_t ifAgcSns = 0; + u16_t ifAgcTop = 0; + u16_t rfAgcMax = 0; + u16_t rfAgcMin = 0; + pDRXJData_t extAttr = NULL; + pI2CDeviceAddr_t devAddr = NULL; + + extAttr = (pDRXJData_t)demod->myExtAttr; + devAddr = demod -> myI2CDevAddr; + + RR16( devAddr, IQM_AF_AGC_IF__A, &ifGain ); + ifGain &= IQM_AF_AGC_IF__M; + RR16( devAddr, IQM_AF_AGC_RF__A, &rfGain ); + rfGain &= IQM_AF_AGC_RF__M; + + ifAgcSns = DRXJ_AGC_SNS; + ifAgcTop = DRXJ_AGC_TOP; + rfAgcMax = DRXJ_RFAGC_MAX; + rfAgcMin = DRXJ_RFAGC_MIN; + + if (ifGain > ifAgcTop) + { + if (rfGain > rfAgcMax) + *sigStrength = 100; + else if (rfGain > rfAgcMin) + { + CHK_ZERO (rfAgcMax - rfAgcMin); + *sigStrength = 75 + 25 * (rfGain - rfAgcMin) / (rfAgcMax - rfAgcMin); + } + else + *sigStrength = 75; + } + else if (ifGain > ifAgcSns) + { + CHK_ZERO(ifAgcTop - ifAgcSns); + *sigStrength = 20 + 55* (ifGain - ifAgcSns)/ (ifAgcTop - ifAgcSns); + } + else + { + CHK_ZERO (ifAgcSns); + *sigStrength = (20 * ifGain / ifAgcSns); + } + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/** +* \fn DRXStatus_t GetAccPktErr() +* \brief Retrieve signal strength for VSB and QAM. +* \param demod Pointer to demod instance +* \param packetErr Pointer to packet error +* \return DRXStatus_t. +* \retval DRX_STS_OK sigStrength contains valid data. +* \retval DRX_STS_INVALID_ARG sigStrength is NULL. +* \retval DRX_STS_ERROR Erroneous data, sigStrength contains invalid data. +*/ +#ifdef DRXJ_SIGNAL_ACCUM_ERR +static DRXStatus_t +GetAccPktErr( pDRXDemodInstance_t demod, + pu16_t packetErr ) +{ + static u16_t pktErr = 0; + static u16_t lastPktErr = 0; + u16_t data = 0; + pDRXJData_t extAttr = NULL; + pI2CDeviceAddr_t devAddr = NULL; + + extAttr = (pDRXJData_t)demod->myExtAttr; + devAddr = demod -> myI2CDevAddr; + + RR16( devAddr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, &data ); + if ( extAttr->resetPktErrAcc == TRUE ) + { + lastPktErr = data; + pktErr = 0; + extAttr->resetPktErrAcc = FALSE; + } + + if (data < lastPktErr) + { + pktErr += 0xffff - lastPktErr; + pktErr += data; + } + else + { + pktErr += (data - lastPktErr); + } + *packetErr = pktErr; + lastPktErr = data; + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} +#endif + +/** +* \fn DRXStatus_t ResetAccPktErr() +* \brief Reset Accumulating packet error count. +* \param demod Pointer to demod instance +* \return DRXStatus_t. +* \retval DRX_STS_OK. +* \retval DRX_STS_ERROR Erroneous data. +*/ +static DRXStatus_t +CtrlSetCfgResetPktErr( pDRXDemodInstance_t demod ) +{ +#ifdef DRXJ_SIGNAL_ACCUM_ERR + pDRXJData_t extAttr = NULL; + u16_t packetError = 0; + + extAttr = (pDRXJData_t)demod->myExtAttr; + extAttr->resetPktErrAcc = TRUE; + /* call to reset counter */ + CHK_ERROR (GetAccPktErr (demod, &packetError)); + + return (DRX_STS_OK); +rw_error: +#endif + return (DRX_STS_ERROR); +} + +/** +* \fn static short GetSTRFreqOffset() +* \brief Get symbol rate offset in QAM & 8VSB mode +* \return Error code +*/ +static DRXStatus_t +GetSTRFreqOffset( pDRXDemodInstance_t demod, + s32_t *STRFreq + ) +{ + u32_t symbolFrequencyRatio = 0; + u32_t symbolNomFrequencyRatio = 0; + + DRXStandard_t standard = DRX_STANDARD_UNKNOWN; + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + standard = extAttr->standard; + + ARR32( devAddr, IQM_RC_RATE_LO__A, &symbolFrequencyRatio ); + symbolNomFrequencyRatio = extAttr->iqmRcRateOfs; + + if ( symbolFrequencyRatio > symbolNomFrequencyRatio ) + *STRFreq = -1 * FracTimes1e6( ( symbolFrequencyRatio - symbolNomFrequencyRatio ), (symbolFrequencyRatio + (1 << 23)) ); + else + *STRFreq = FracTimes1e6( ( symbolNomFrequencyRatio - symbolFrequencyRatio ), (symbolFrequencyRatio + (1 << 23)) ); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/** +* \fn static short GetCTLFreqOffset +* \brief Get the value of CTLFreq in QAM & ATSC mode +* \return Error code +*/ +static DRXStatus_t +GetCTLFreqOffset ( pDRXDemodInstance_t demod, + s32_t *CTLFreq + ) +{ + DRXFrequency_t samplingFrequency = 0; + s32_t currentFrequency = 0; + s32_t nominalFrequency = 0; + s32_t carrierFrequencyShift = 0; + s32_t sign = 1; + u32_t data64Hi = 0; + u32_t data64Lo = 0; + pDRXJData_t extAttr = NULL; + pDRXCommonAttr_t commonAttr = NULL; + pI2CDeviceAddr_t devAddr = NULL; + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + commonAttr = (pDRXCommonAttr_t) demod -> myCommonAttr; + + samplingFrequency = commonAttr->sysClockFreq/3; + + /* both registers are sign extended */ + nominalFrequency = extAttr->iqmFsRateOfs; + ARR32( devAddr, IQM_FS_RATE_LO__A, (pu32_t) ¤tFrequency ); + + if ( extAttr->posImage == TRUE ) + { + /* negative image */ + carrierFrequencyShift = nominalFrequency - currentFrequency; + } else { + /* positive image */ + carrierFrequencyShift = currentFrequency - nominalFrequency; + } + + /* carrier Frequency Shift In Hz */ + if (carrierFrequencyShift < 0) + { + sign = -1; + carrierFrequencyShift *= sign; + } + + /* *CTLFreq = carrierFrequencyShift * 50.625e6 / (1 << 28); */ + Mult32 ( carrierFrequencyShift, samplingFrequency, &data64Hi, &data64Lo ); + *CTLFreq = (s32_t)((((data64Lo >> 28) & 0xf) | (data64Hi << 4)) * sign); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t SetAgcRf () +* \brief Configure RF AGC +* \param demod instance of demodulator. +* \param agcSettings AGC configuration structure +* \return DRXStatus_t. +*/ +static DRXStatus_t +SetAgcRf ( pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings, Bool_t atomic ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + pDRXJCfgAgc_t pAgcSettings = NULL; + pDRXCommonAttr_t commonAttr = NULL; + DRXWriteReg16Func_t ScuWr16 = NULL; + DRXReadReg16Func_t ScuRr16 = NULL; + + commonAttr = (pDRXCommonAttr_t) demod -> myCommonAttr; + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + if (atomic) + { + ScuRr16 = DRXJ_DAP_SCU_AtomicReadReg16; + ScuWr16 = DRXJ_DAP_SCU_AtomicWriteReg16; + } + else + { + ScuRr16 = DRXJ_DAP.readReg16Func; + ScuWr16 = DRXJ_DAP.writeReg16Func; + } + + /* Configure AGC only if standard is currently active*/ + if ( ( extAttr->standard == agcSettings->standard ) || + ( DRXJ_ISQAMSTD( extAttr->standard ) && + DRXJ_ISQAMSTD( agcSettings->standard ) ) || + ( DRXJ_ISATVSTD( extAttr->standard ) && + DRXJ_ISATVSTD( agcSettings->standard ) ) ) + { + u16_t data = 0; + + switch ( agcSettings->ctrlMode ) + { + case DRX_AGC_CTRL_AUTO: + + /* Enable RF AGC DAC */ + RR16( devAddr, IQM_AF_STDBY__A , &data ); + data |= IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE; + WR16( devAddr, IQM_AF_STDBY__A, data ); + + /* Enable SCU RF AGC loop */ + CHK_ERROR((*ScuRr16)( devAddr, SCU_RAM_AGC_KI__A, &data, 0 )); + data &= ~SCU_RAM_AGC_KI_RF__M; + if ( extAttr->standard == DRX_STANDARD_8VSB ) + { + data |= ( 2 << SCU_RAM_AGC_KI_RF__B ); + } + else if (DRXJ_ISQAMSTD( extAttr->standard )) + { + data |= ( 5 << SCU_RAM_AGC_KI_RF__B ); + } + else + { + data |= ( 4 << SCU_RAM_AGC_KI_RF__B ); + } + + if (commonAttr->tunerRfAgcPol) + { + data |= SCU_RAM_AGC_KI_INV_RF_POL__M; + } + else + { + data &= ~SCU_RAM_AGC_KI_INV_RF_POL__M; + } + CHK_ERROR((*ScuWr16)( devAddr, SCU_RAM_AGC_KI__A, data, 0 )); + + /* Set speed ( using complementary reduction value ) */ + CHK_ERROR((*ScuRr16)( devAddr, SCU_RAM_AGC_KI_RED__A , &data, 0 )); + data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M; + CHK_ERROR((*ScuWr16)( devAddr, SCU_RAM_AGC_KI_RED__A , + (~(agcSettings->speed << SCU_RAM_AGC_KI_RED_RAGC_RED__B) + & SCU_RAM_AGC_KI_RED_RAGC_RED__M ) + | data, 0 )); + + if (agcSettings->standard == DRX_STANDARD_8VSB) + pAgcSettings = &(extAttr->vsbIfAgcCfg); + else if (DRXJ_ISQAMSTD( agcSettings->standard )) + pAgcSettings = &(extAttr->qamIfAgcCfg); + else if (DRXJ_ISATVSTD( agcSettings->standard )) + pAgcSettings = &(extAttr->atvIfAgcCfg); + else + return (DRX_STS_INVALID_ARG); + + /* Set TOP, only if IF-AGC is in AUTO mode */ + if ( pAgcSettings->ctrlMode == DRX_AGC_CTRL_AUTO) + { + CHK_ERROR((*ScuWr16)( devAddr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, + agcSettings->top, 0 )); + CHK_ERROR((*ScuWr16)( devAddr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, + agcSettings->top, 0 )); + } + + /* Cut-Off current */ + CHK_ERROR((*ScuWr16)( devAddr, SCU_RAM_AGC_RF_IACCU_HI_CO__A, + agcSettings->cutOffCurrent, 0 )); + break; + case DRX_AGC_CTRL_USER: + + /* Enable RF AGC DAC */ + RR16( devAddr, IQM_AF_STDBY__A , &data ); + data |= IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE; + WR16( devAddr, IQM_AF_STDBY__A , data ); + + /* Disable SCU RF AGC loop */ + CHK_ERROR((*ScuRr16)( devAddr, SCU_RAM_AGC_KI__A, &data, 0 )); + data &= ~SCU_RAM_AGC_KI_RF__M; + if (commonAttr->tunerRfAgcPol) + { + data |= SCU_RAM_AGC_KI_INV_RF_POL__M; + } + else + { + data &= ~SCU_RAM_AGC_KI_INV_RF_POL__M; + } + CHK_ERROR((*ScuWr16)( devAddr, SCU_RAM_AGC_KI__A, data, 0 )); + + /* Write value to output pin */ + CHK_ERROR((*ScuWr16)( devAddr, SCU_RAM_AGC_RF_IACCU_HI__A, agcSettings->outputLevel, 0 )); + break; + case DRX_AGC_CTRL_OFF: + + /* Disable RF AGC DAC */ + RR16( devAddr, IQM_AF_STDBY__A , &data ); + data &= (~IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE); + WR16( devAddr, IQM_AF_STDBY__A , data ); + + /* Disable SCU RF AGC loop */ + CHK_ERROR((*ScuRr16)( devAddr, SCU_RAM_AGC_KI__A, &data, 0 )); + data &= ~SCU_RAM_AGC_KI_RF__M; + CHK_ERROR((*ScuWr16)( devAddr, SCU_RAM_AGC_KI__A, data, 0 )); + break; + default: + return (DRX_STS_INVALID_ARG); + } /* switch ( agcsettings->ctrlMode ) */ + } + + /* Store rf agc settings */ + switch ( agcSettings->standard){ + case DRX_STANDARD_8VSB: + extAttr->vsbRfAgcCfg = *agcSettings; + break; +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: + extAttr->qamRfAgcCfg = *agcSettings; + break; +#endif +#ifndef DRXJ_DIGITAL_ONLY + case DRX_STANDARD_PAL_SECAM_BG: + case DRX_STANDARD_PAL_SECAM_DK: + case DRX_STANDARD_PAL_SECAM_I: + case DRX_STANDARD_PAL_SECAM_L: + case DRX_STANDARD_PAL_SECAM_LP: + case DRX_STANDARD_NTSC: + case DRX_STANDARD_FM: + extAttr->atvRfAgcCfg = *agcSettings; + break; +#endif + default: + return (DRX_STS_ERROR); + } + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/** +* \fn DRXStatus_t GetAgcRf () +* \brief get configuration of RF AGC +* \param demod instance of demodulator. +* \param agcSettings AGC configuration structure +* \return DRXStatus_t. +*/ +static DRXStatus_t +GetAgcRf ( pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + DRXStandard_t standard = DRX_STANDARD_UNKNOWN; + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* Return stored AGC settings */ + standard = agcSettings->standard; + switch ( agcSettings->standard){ + case DRX_STANDARD_8VSB: + *agcSettings = extAttr->vsbRfAgcCfg; + break; +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: + *agcSettings = extAttr->qamRfAgcCfg; + break; +#endif +#ifndef DRXJ_DIGITAL_ONLY + case DRX_STANDARD_PAL_SECAM_BG: + case DRX_STANDARD_PAL_SECAM_DK: + case DRX_STANDARD_PAL_SECAM_I: + case DRX_STANDARD_PAL_SECAM_L: + case DRX_STANDARD_PAL_SECAM_LP: + case DRX_STANDARD_NTSC: + case DRX_STANDARD_FM: + *agcSettings = extAttr->atvRfAgcCfg; + break; +#endif + default: + return (DRX_STS_ERROR); + } + agcSettings->standard = standard; + + /* Get AGC output only if standard is currently active. */ + if ( ( extAttr->standard == agcSettings->standard ) || + ( DRXJ_ISQAMSTD( extAttr->standard ) && + DRXJ_ISQAMSTD( agcSettings->standard ) ) || + ( DRXJ_ISATVSTD( extAttr->standard ) && + DRXJ_ISATVSTD( agcSettings->standard ) ) ) + { + SARR16( devAddr, SCU_RAM_AGC_RF_IACCU_HI__A, + &(agcSettings->outputLevel)); + } + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/** +* \fn DRXStatus_t SetAgcIf () +* \brief Configure If AGC +* \param demod instance of demodulator. +* \param agcSettings AGC configuration structure +* \return DRXStatus_t. +*/ +static DRXStatus_t +SetAgcIf ( pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings, Bool_t atomic ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + pDRXJCfgAgc_t pAgcSettings = NULL; + pDRXCommonAttr_t commonAttr = NULL; + DRXWriteReg16Func_t ScuWr16 = NULL; + DRXReadReg16Func_t ScuRr16 = NULL; + + commonAttr = (pDRXCommonAttr_t) demod -> myCommonAttr; + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + if (atomic) + { + ScuRr16 = DRXJ_DAP_SCU_AtomicReadReg16; + ScuWr16 = DRXJ_DAP_SCU_AtomicWriteReg16; + } + else + { + ScuRr16 = DRXJ_DAP.readReg16Func; + ScuWr16 = DRXJ_DAP.writeReg16Func; + } + + /* Configure AGC only if standard is currently active*/ + if ( ( extAttr->standard == agcSettings->standard ) || + ( DRXJ_ISQAMSTD( extAttr->standard ) && + DRXJ_ISQAMSTD( agcSettings->standard ) ) || + ( DRXJ_ISATVSTD( extAttr->standard ) && + DRXJ_ISATVSTD( agcSettings->standard ) ) ) + { + u16_t data = 0; + + switch ( agcSettings->ctrlMode ) + { + case DRX_AGC_CTRL_AUTO: + /* Enable IF AGC DAC */ + RR16( devAddr, IQM_AF_STDBY__A , &data ); + data |= IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE; + WR16( devAddr, IQM_AF_STDBY__A , data ); + + /* Enable SCU IF AGC loop */ + CHK_ERROR((*ScuRr16)( devAddr, SCU_RAM_AGC_KI__A, &data, 0 )); + data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M; + data &= ~SCU_RAM_AGC_KI_IF__M; + if ( extAttr->standard == DRX_STANDARD_8VSB ) + { + data |= (3 << SCU_RAM_AGC_KI_IF__B ); + } + else if (DRXJ_ISQAMSTD( extAttr->standard )) + { + data |= (6 << SCU_RAM_AGC_KI_IF__B ); + } + else + { + data |= ( 5 << SCU_RAM_AGC_KI_IF__B ); + } + + if (commonAttr->tunerIfAgcPol) + { + data |= SCU_RAM_AGC_KI_INV_IF_POL__M; + } + else + { + data &= ~SCU_RAM_AGC_KI_INV_IF_POL__M; + } + CHK_ERROR((*ScuWr16)( devAddr, SCU_RAM_AGC_KI__A, data, 0 )); + + /* Set speed (using complementary reduction value) */ + CHK_ERROR((*ScuRr16)( devAddr, SCU_RAM_AGC_KI_RED__A , &data, 0 )); + data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M; + CHK_ERROR((*ScuWr16)( devAddr, SCU_RAM_AGC_KI_RED__A , + (~(agcSettings->speed << SCU_RAM_AGC_KI_RED_IAGC_RED__B) + & SCU_RAM_AGC_KI_RED_IAGC_RED__M ) + | data, 0 )); + + if (agcSettings->standard == DRX_STANDARD_8VSB) + pAgcSettings = &(extAttr->vsbRfAgcCfg); + else if (DRXJ_ISQAMSTD( agcSettings->standard )) + pAgcSettings = &(extAttr->qamRfAgcCfg); + else if (DRXJ_ISATVSTD( agcSettings->standard )) + pAgcSettings = &(extAttr->atvRfAgcCfg); + else + return (DRX_STS_INVALID_ARG); + + /* Restore TOP */ + if ( pAgcSettings->ctrlMode == DRX_AGC_CTRL_AUTO) + { + CHK_ERROR((*ScuWr16)( devAddr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, + pAgcSettings->top, 0 )); + CHK_ERROR((*ScuWr16)( devAddr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, + pAgcSettings->top, 0 )); + } + else + { + CHK_ERROR((*ScuWr16)( devAddr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, 0, 0 )); + CHK_ERROR((*ScuWr16)( devAddr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, 0, 0 )); + } + break; + + case DRX_AGC_CTRL_USER: + + /* Enable IF AGC DAC */ + RR16( devAddr, IQM_AF_STDBY__A , &data ); + data |= IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE; + WR16( devAddr, IQM_AF_STDBY__A , data ); + + /* Disable SCU IF AGC loop */ + CHK_ERROR((*ScuRr16)( devAddr, SCU_RAM_AGC_KI__A, &data, 0 )); + data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M; + data |= SCU_RAM_AGC_KI_IF_AGC_DISABLE__M; + if (commonAttr->tunerIfAgcPol) + { + data |= SCU_RAM_AGC_KI_INV_IF_POL__M; + } + else + { + data &= ~SCU_RAM_AGC_KI_INV_IF_POL__M; + } + CHK_ERROR((*ScuWr16)( devAddr, SCU_RAM_AGC_KI__A, data, 0 )); + + /* Write value to output pin */ + CHK_ERROR((*ScuWr16)( devAddr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, + agcSettings->outputLevel, 0 )); + break; + + case DRX_AGC_CTRL_OFF: + + /* Disable If AGC DAC */ + RR16( devAddr, IQM_AF_STDBY__A , &data ); + data &= (~IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE); + WR16( devAddr, IQM_AF_STDBY__A , data ); + + /* Disable SCU IF AGC loop */ + CHK_ERROR((*ScuRr16)( devAddr, SCU_RAM_AGC_KI__A, &data, 0 )); + data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M; + data |= SCU_RAM_AGC_KI_IF_AGC_DISABLE__M; + CHK_ERROR((*ScuWr16)( devAddr, SCU_RAM_AGC_KI__A, data, 0 )); + break; + default: + return (DRX_STS_INVALID_ARG); + } /* switch ( agcsettings->ctrlMode ) */ + + /* always set the top to support configurations without if-loop */ + CHK_ERROR((*ScuWr16)( devAddr, + SCU_RAM_AGC_INGAIN_TGT_MIN__A, + agcSettings->top, + 0 ) ); + } + + /* Store if agc settings */ + switch ( agcSettings->standard){ + case DRX_STANDARD_8VSB: + extAttr->vsbIfAgcCfg = *agcSettings; + break; +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: + extAttr->qamIfAgcCfg = *agcSettings; + break; +#endif +#ifndef DRXJ_DIGITAL_ONLY + case DRX_STANDARD_PAL_SECAM_BG: + case DRX_STANDARD_PAL_SECAM_DK: + case DRX_STANDARD_PAL_SECAM_I: + case DRX_STANDARD_PAL_SECAM_L: + case DRX_STANDARD_PAL_SECAM_LP: + case DRX_STANDARD_NTSC: + case DRX_STANDARD_FM: + extAttr->atvIfAgcCfg = *agcSettings; + break; +#endif + default: + return (DRX_STS_ERROR); + } + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/** +* \fn DRXStatus_t GetAgcIf () +* \brief get configuration of If AGC +* \param demod instance of demodulator. +* \param agcSettings AGC configuration structure +* \return DRXStatus_t. +*/ +static DRXStatus_t +GetAgcIf ( pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + DRXStandard_t standard = DRX_STANDARD_UNKNOWN; + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* Return stored ATV AGC settings */ + standard = agcSettings->standard; + switch ( agcSettings->standard){ + case DRX_STANDARD_8VSB: + *agcSettings = extAttr->vsbIfAgcCfg; + break; +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: + *agcSettings = extAttr->qamIfAgcCfg; + break; +#endif +#ifndef DRXJ_DIGITAL_ONLY + case DRX_STANDARD_PAL_SECAM_BG: + case DRX_STANDARD_PAL_SECAM_DK: + case DRX_STANDARD_PAL_SECAM_I: + case DRX_STANDARD_PAL_SECAM_L: + case DRX_STANDARD_PAL_SECAM_LP: + case DRX_STANDARD_NTSC: + case DRX_STANDARD_FM: + *agcSettings = extAttr->atvIfAgcCfg; + break; +#endif + default: + return (DRX_STS_ERROR); + } + agcSettings->standard = standard; + + /* Get AGC output only if standard is currently active */ + if ( ( extAttr->standard == agcSettings->standard ) || + ( DRXJ_ISQAMSTD( extAttr->standard ) && + DRXJ_ISQAMSTD( agcSettings->standard ) ) || + ( DRXJ_ISATVSTD( extAttr->standard ) && + DRXJ_ISATVSTD( agcSettings->standard ) ) ) + { + /* read output level */ + SARR16( devAddr, SCU_RAM_AGC_IF_IACCU_HI__A, + &(agcSettings->outputLevel) ); + } + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/** +* \fn DRXStatus_t SetIqmAf () +* \brief Configure IQM AF registers +* \param demod instance of demodulator. +* \param active +* \return DRXStatus_t. +*/ +static DRXStatus_t +SetIqmAf ( pDRXDemodInstance_t demod, Bool_t active ) +{ + u16_t data = 0; + pI2CDeviceAddr_t devAddr = NULL; + + devAddr = demod -> myI2CDevAddr; + + /* Configure IQM */ + RR16( devAddr, IQM_AF_STDBY__A , &data ); + if( !active ) + { + data &= ((~IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE) + & (~IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE) + & (~IQM_AF_STDBY_STDBY_PD_A2_ACTIVE) + & (~IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE) + & (~IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE) + ); + } + else /* active */ + { + data |= (IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE + | IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE + | IQM_AF_STDBY_STDBY_PD_A2_ACTIVE + | IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE + | IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE + ); + } + WR16( devAddr, IQM_AF_STDBY__A , data ); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================*/ +/*== END 8VSB & QAM COMMON DATAPATH FUNCTIONS ==*/ +/*============================================================================*/ + +/*============================================================================*/ +/*============================================================================*/ +/*== 8VSB DATAPATH FUNCTIONS ==*/ +/*============================================================================*/ +/*============================================================================*/ + + +/** +* \fn DRXStatus_t PowerDownVSB () +* \brief Powr down QAM related blocks. +* \param demod instance of demodulator. +* \param channel pointer to channel data. +* \return DRXStatus_t. +*/ +static DRXStatus_t +PowerDownVSB( pDRXDemodInstance_t demod, Bool_t primary ) +{ + pI2CDeviceAddr_t devAddr = NULL; + DRXJSCUCmd_t cmdSCU = { /* command */ 0, + /* parameterLen */ 0, + /* resultLen */ 0, + /* *parameter */ NULL, + /* *result */ NULL }; + u16_t cmdResult = 0; + pDRXJData_t extAttr = NULL; + DRXCfgMPEGOutput_t cfgMPEGOutput; + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; + /* + STOP demodulator + reset of FEC and VSB HW + */ + cmdSCU.command = SCU_RAM_COMMAND_STANDARD_VSB | + SCU_RAM_COMMAND_CMD_DEMOD_STOP; + cmdSCU.parameterLen = 0; + cmdSCU.resultLen = 1; + cmdSCU.parameter = NULL; + cmdSCU.result = &cmdResult; + CHK_ERROR( SCUCommand( devAddr, &cmdSCU ) ); + + /* stop all comm_exec */ + WR16( devAddr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP ); + WR16( devAddr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP ); + if (primary == TRUE) + { + WR16( devAddr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP ); + CHK_ERROR( SetIqmAf( demod, FALSE ) ); + } + else + { + WR16( devAddr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP ); + WR16( devAddr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP ); + WR16( devAddr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP ); + WR16( devAddr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP ); + WR16( devAddr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP ); + } + + cfgMPEGOutput.enableMPEGOutput = FALSE; + CHK_ERROR( CtrlSetCfgMPEGOutput( demod, &cfgMPEGOutput) ); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} +/** +* \fn DRXStatus_t SetVSBLeakNGain () +* \brief Set ATSC demod. +* \param demod instance of demodulator. +* \return DRXStatus_t. +*/ +static DRXStatus_t +SetVSBLeakNGain ( pDRXDemodInstance_t demod ) +{ + pI2CDeviceAddr_t devAddr = NULL; + + const u8_t vsb_ffe_leak_gain_ram0[]= { + DRXJ_16TO8( 0x8 ), /* FFETRAINLKRATIO1 */ + DRXJ_16TO8( 0x8 ), /* FFETRAINLKRATIO2 */ + DRXJ_16TO8( 0x8 ), /* FFETRAINLKRATIO3 */ + DRXJ_16TO8( 0xf ), /* FFETRAINLKRATIO4 */ + DRXJ_16TO8( 0xf ), /* FFETRAINLKRATIO5 */ + DRXJ_16TO8( 0xf ), /* FFETRAINLKRATIO6 */ + DRXJ_16TO8( 0xf ), /* FFETRAINLKRATIO7 */ + DRXJ_16TO8( 0xf ), /* FFETRAINLKRATIO8 */ + DRXJ_16TO8( 0xf ), /* FFETRAINLKRATIO9 */ + DRXJ_16TO8( 0x8 ), /* FFETRAINLKRATIO10 */ + DRXJ_16TO8( 0x8 ), /* FFETRAINLKRATIO11 */ + DRXJ_16TO8( 0x8 ), /* FFETRAINLKRATIO12 */ + DRXJ_16TO8( 0x10 ), /* FFERCA1TRAINLKRATIO1 */ + DRXJ_16TO8( 0x10 ), /* FFERCA1TRAINLKRATIO2 */ + DRXJ_16TO8( 0x10 ), /* FFERCA1TRAINLKRATIO3 */ + DRXJ_16TO8( 0x20 ), /* FFERCA1TRAINLKRATIO4 */ + DRXJ_16TO8( 0x20 ), /* FFERCA1TRAINLKRATIO5 */ + DRXJ_16TO8( 0x20 ), /* FFERCA1TRAINLKRATIO6 */ + DRXJ_16TO8( 0x20 ), /* FFERCA1TRAINLKRATIO7 */ + DRXJ_16TO8( 0x20 ), /* FFERCA1TRAINLKRATIO8 */ + DRXJ_16TO8( 0x20 ), /* FFERCA1TRAINLKRATIO9 */ + DRXJ_16TO8( 0x10 ), /* FFERCA1TRAINLKRATIO10 */ + DRXJ_16TO8( 0x10 ), /* FFERCA1TRAINLKRATIO11 */ + DRXJ_16TO8( 0x10 ), /* FFERCA1TRAINLKRATIO12 */ + DRXJ_16TO8( 0x10 ), /* FFERCA1DATALKRATIO1 */ + DRXJ_16TO8( 0x10 ), /* FFERCA1DATALKRATIO2 */ + DRXJ_16TO8( 0x10 ), /* FFERCA1DATALKRATIO3 */ + DRXJ_16TO8( 0x20 ), /* FFERCA1DATALKRATIO4 */ + DRXJ_16TO8( 0x20 ), /* FFERCA1DATALKRATIO5 */ + DRXJ_16TO8( 0x20 ), /* FFERCA1DATALKRATIO6 */ + DRXJ_16TO8( 0x20 ), /* FFERCA1DATALKRATIO7 */ + DRXJ_16TO8( 0x20 ), /* FFERCA1DATALKRATIO8 */ + DRXJ_16TO8( 0x20 ), /* FFERCA1DATALKRATIO9 */ + DRXJ_16TO8( 0x10 ), /* FFERCA1DATALKRATIO10 */ + DRXJ_16TO8( 0x10 ), /* FFERCA1DATALKRATIO11 */ + DRXJ_16TO8( 0x10 ), /* FFERCA1DATALKRATIO12 */ + DRXJ_16TO8( 0x10 ), /* FFERCA2TRAINLKRATIO1 */ + DRXJ_16TO8( 0x10 ), /* FFERCA2TRAINLKRATIO2 */ + DRXJ_16TO8( 0x10 ), /* FFERCA2TRAINLKRATIO3 */ + DRXJ_16TO8( 0x20 ), /* FFERCA2TRAINLKRATIO4 */ + DRXJ_16TO8( 0x20 ), /* FFERCA2TRAINLKRATIO5 */ + DRXJ_16TO8( 0x20 ), /* FFERCA2TRAINLKRATIO6 */ + DRXJ_16TO8( 0x20 ), /* FFERCA2TRAINLKRATIO7 */ + DRXJ_16TO8( 0x20 ), /* FFERCA2TRAINLKRATIO8 */ + DRXJ_16TO8( 0x20 ), /* FFERCA2TRAINLKRATIO9 */ + DRXJ_16TO8( 0x10 ), /* FFERCA2TRAINLKRATIO10 */ + DRXJ_16TO8( 0x10 ), /* FFERCA2TRAINLKRATIO11 */ + DRXJ_16TO8( 0x10 ), /* FFERCA2TRAINLKRATIO12 */ + DRXJ_16TO8( 0x10 ), /* FFERCA2DATALKRATIO1 */ + DRXJ_16TO8( 0x10 ), /* FFERCA2DATALKRATIO2 */ + DRXJ_16TO8( 0x10 ), /* FFERCA2DATALKRATIO3 */ + DRXJ_16TO8( 0x20 ), /* FFERCA2DATALKRATIO4 */ + DRXJ_16TO8( 0x20 ), /* FFERCA2DATALKRATIO5 */ + DRXJ_16TO8( 0x20 ), /* FFERCA2DATALKRATIO6 */ + DRXJ_16TO8( 0x20 ), /* FFERCA2DATALKRATIO7 */ + DRXJ_16TO8( 0x20 ), /* FFERCA2DATALKRATIO8 */ + DRXJ_16TO8( 0x20 ), /* FFERCA2DATALKRATIO9 */ + DRXJ_16TO8( 0x10 ), /* FFERCA2DATALKRATIO10 */ + DRXJ_16TO8( 0x10 ), /* FFERCA2DATALKRATIO11 */ + DRXJ_16TO8( 0x10 ), /* FFERCA2DATALKRATIO12 */ + DRXJ_16TO8( 0x07 ), /* FFEDDM1TRAINLKRATIO1 */ + DRXJ_16TO8( 0x07 ), /* FFEDDM1TRAINLKRATIO2 */ + DRXJ_16TO8( 0x07 ), /* FFEDDM1TRAINLKRATIO3 */ + DRXJ_16TO8( 0x0e ), /* FFEDDM1TRAINLKRATIO4 */ + DRXJ_16TO8( 0x0e ), /* FFEDDM1TRAINLKRATIO5 */ + DRXJ_16TO8( 0x0e ), /* FFEDDM1TRAINLKRATIO6 */ + DRXJ_16TO8( 0x0e ), /* FFEDDM1TRAINLKRATIO7 */ + DRXJ_16TO8( 0x0e ), /* FFEDDM1TRAINLKRATIO8 */ + DRXJ_16TO8( 0x0e ), /* FFEDDM1TRAINLKRATIO9 */ + DRXJ_16TO8( 0x07 ), /* FFEDDM1TRAINLKRATIO10 */ + DRXJ_16TO8( 0x07 ), /* FFEDDM1TRAINLKRATIO11 */ + DRXJ_16TO8( 0x07 ), /* FFEDDM1TRAINLKRATIO12 */ + DRXJ_16TO8( 0x07 ), /* FFEDDM1DATALKRATIO1 */ + DRXJ_16TO8( 0x07 ), /* FFEDDM1DATALKRATIO2 */ + DRXJ_16TO8( 0x07 ), /* FFEDDM1DATALKRATIO3 */ + DRXJ_16TO8( 0x0e ), /* FFEDDM1DATALKRATIO4 */ + DRXJ_16TO8( 0x0e ), /* FFEDDM1DATALKRATIO5 */ + DRXJ_16TO8( 0x0e ), /* FFEDDM1DATALKRATIO6 */ + DRXJ_16TO8( 0x0e ), /* FFEDDM1DATALKRATIO7 */ + DRXJ_16TO8( 0x0e ), /* FFEDDM1DATALKRATIO8 */ + DRXJ_16TO8( 0x0e ), /* FFEDDM1DATALKRATIO9 */ + DRXJ_16TO8( 0x07 ), /* FFEDDM1DATALKRATIO10 */ + DRXJ_16TO8( 0x07 ), /* FFEDDM1DATALKRATIO11 */ + DRXJ_16TO8( 0x07 ), /* FFEDDM1DATALKRATIO12 */ + DRXJ_16TO8( 0x06 ), /* FFEDDM2TRAINLKRATIO1 */ + DRXJ_16TO8( 0x06 ), /* FFEDDM2TRAINLKRATIO2 */ + DRXJ_16TO8( 0x06 ), /* FFEDDM2TRAINLKRATIO3 */ + DRXJ_16TO8( 0x0c ), /* FFEDDM2TRAINLKRATIO4 */ + DRXJ_16TO8( 0x0c ), /* FFEDDM2TRAINLKRATIO5 */ + DRXJ_16TO8( 0x0c ), /* FFEDDM2TRAINLKRATIO6 */ + DRXJ_16TO8( 0x0c ), /* FFEDDM2TRAINLKRATIO7 */ + DRXJ_16TO8( 0x0c ), /* FFEDDM2TRAINLKRATIO8 */ + DRXJ_16TO8( 0x0c ), /* FFEDDM2TRAINLKRATIO9 */ + DRXJ_16TO8( 0x06 ), /* FFEDDM2TRAINLKRATIO10 */ + DRXJ_16TO8( 0x06 ), /* FFEDDM2TRAINLKRATIO11 */ + DRXJ_16TO8( 0x06 ), /* FFEDDM2TRAINLKRATIO12 */ + DRXJ_16TO8( 0x06 ), /* FFEDDM2DATALKRATIO1 */ + DRXJ_16TO8( 0x06 ), /* FFEDDM2DATALKRATIO2 */ + DRXJ_16TO8( 0x06 ), /* FFEDDM2DATALKRATIO3 */ + DRXJ_16TO8( 0x0c ), /* FFEDDM2DATALKRATIO4 */ + DRXJ_16TO8( 0x0c ), /* FFEDDM2DATALKRATIO5 */ + DRXJ_16TO8( 0x0c ), /* FFEDDM2DATALKRATIO6 */ + DRXJ_16TO8( 0x0c ), /* FFEDDM2DATALKRATIO7 */ + DRXJ_16TO8( 0x0c ), /* FFEDDM2DATALKRATIO8 */ + DRXJ_16TO8( 0x0c ), /* FFEDDM2DATALKRATIO9 */ + DRXJ_16TO8( 0x06 ), /* FFEDDM2DATALKRATIO10 */ + DRXJ_16TO8( 0x06 ), /* FFEDDM2DATALKRATIO11 */ + DRXJ_16TO8( 0x06 ), /* FFEDDM2DATALKRATIO12 */ + DRXJ_16TO8( 0x2020 ), /* FIRTRAINGAIN1 */ + DRXJ_16TO8( 0x2020 ), /* FIRTRAINGAIN2 */ + DRXJ_16TO8( 0x2020 ), /* FIRTRAINGAIN3 */ + DRXJ_16TO8( 0x4040 ), /* FIRTRAINGAIN4 */ + DRXJ_16TO8( 0x4040 ), /* FIRTRAINGAIN5 */ + DRXJ_16TO8( 0x4040 ), /* FIRTRAINGAIN6 */ + DRXJ_16TO8( 0x4040 ), /* FIRTRAINGAIN7 */ + DRXJ_16TO8( 0x4040 ), /* FIRTRAINGAIN8 */ + DRXJ_16TO8( 0x4040 ), /* FIRTRAINGAIN9 */ + DRXJ_16TO8( 0x2020 ), /* FIRTRAINGAIN10 */ + DRXJ_16TO8( 0x2020 ), /* FIRTRAINGAIN11 */ + DRXJ_16TO8( 0x2020 ), /* FIRTRAINGAIN12 */ + DRXJ_16TO8( 0x0808 ), /* FIRRCA1GAIN1 */ + DRXJ_16TO8( 0x0808 ), /* FIRRCA1GAIN2 */ + DRXJ_16TO8( 0x0808 ), /* FIRRCA1GAIN3 */ + DRXJ_16TO8( 0x1010 ), /* FIRRCA1GAIN4 */ + DRXJ_16TO8( 0x1010 ), /* FIRRCA1GAIN5 */ + DRXJ_16TO8( 0x1010 ), /* FIRRCA1GAIN6 */ + DRXJ_16TO8( 0x1010 ), /* FIRRCA1GAIN7 */ + DRXJ_16TO8( 0x1010 ) /* FIRRCA1GAIN8 */ + }; + + const u8_t vsb_ffe_leak_gain_ram1[]= { + DRXJ_16TO8( 0x1010 ), /* FIRRCA1GAIN9 */ + DRXJ_16TO8( 0x0808 ), /* FIRRCA1GAIN10 */ + DRXJ_16TO8( 0x0808 ), /* FIRRCA1GAIN11 */ + DRXJ_16TO8( 0x0808 ), /* FIRRCA1GAIN12 */ + DRXJ_16TO8( 0x0808 ), /* FIRRCA2GAIN1 */ + DRXJ_16TO8( 0x0808 ), /* FIRRCA2GAIN2 */ + DRXJ_16TO8( 0x0808 ), /* FIRRCA2GAIN3 */ + DRXJ_16TO8( 0x1010 ), /* FIRRCA2GAIN4 */ + DRXJ_16TO8( 0x1010 ), /* FIRRCA2GAIN5 */ + DRXJ_16TO8( 0x1010 ), /* FIRRCA2GAIN6 */ + DRXJ_16TO8( 0x1010 ), /* FIRRCA2GAIN7 */ + DRXJ_16TO8( 0x1010 ), /* FIRRCA2GAIN8 */ + DRXJ_16TO8( 0x1010 ), /* FIRRCA2GAIN9 */ + DRXJ_16TO8( 0x0808 ), /* FIRRCA2GAIN10 */ + DRXJ_16TO8( 0x0808 ), /* FIRRCA2GAIN11 */ + DRXJ_16TO8( 0x0808 ), /* FIRRCA2GAIN12 */ + DRXJ_16TO8( 0x0303 ), /* FIRDDM1GAIN1 */ + DRXJ_16TO8( 0x0303 ), /* FIRDDM1GAIN2 */ + DRXJ_16TO8( 0x0303 ), /* FIRDDM1GAIN3 */ + DRXJ_16TO8( 0x0606 ), /* FIRDDM1GAIN4 */ + DRXJ_16TO8( 0x0606 ), /* FIRDDM1GAIN5 */ + DRXJ_16TO8( 0x0606 ), /* FIRDDM1GAIN6 */ + DRXJ_16TO8( 0x0606 ), /* FIRDDM1GAIN7 */ + DRXJ_16TO8( 0x0606 ), /* FIRDDM1GAIN8 */ + DRXJ_16TO8( 0x0606 ), /* FIRDDM1GAIN9 */ + DRXJ_16TO8( 0x0303 ), /* FIRDDM1GAIN10 */ + DRXJ_16TO8( 0x0303 ), /* FIRDDM1GAIN11 */ + DRXJ_16TO8( 0x0303 ), /* FIRDDM1GAIN12 */ + DRXJ_16TO8( 0x0303 ), /* FIRDDM2GAIN1 */ + DRXJ_16TO8( 0x0303 ), /* FIRDDM2GAIN2 */ + DRXJ_16TO8( 0x0303 ), /* FIRDDM2GAIN3 */ + DRXJ_16TO8( 0x0505 ), /* FIRDDM2GAIN4 */ + DRXJ_16TO8( 0x0505 ), /* FIRDDM2GAIN5 */ + DRXJ_16TO8( 0x0505 ), /* FIRDDM2GAIN6 */ + DRXJ_16TO8( 0x0505 ), /* FIRDDM2GAIN7 */ + DRXJ_16TO8( 0x0505 ), /* FIRDDM2GAIN8 */ + DRXJ_16TO8( 0x0505 ), /* FIRDDM2GAIN9 */ + DRXJ_16TO8( 0x0303 ), /* FIRDDM2GAIN10 */ + DRXJ_16TO8( 0x0303 ), /* FIRDDM2GAIN11 */ + DRXJ_16TO8( 0x0303 ), /* FIRDDM2GAIN12 */ + DRXJ_16TO8( 0x001f ), /* DFETRAINLKRATIO */ + DRXJ_16TO8( 0x01ff ), /* DFERCA1TRAINLKRATIO */ + DRXJ_16TO8( 0x01ff ), /* DFERCA1DATALKRATIO */ + DRXJ_16TO8( 0x004f ), /* DFERCA2TRAINLKRATIO */ + DRXJ_16TO8( 0x004f ), /* DFERCA2DATALKRATIO */ + DRXJ_16TO8( 0x01ff ), /* DFEDDM1TRAINLKRATIO */ + DRXJ_16TO8( 0x01ff ), /* DFEDDM1DATALKRATIO */ + DRXJ_16TO8( 0x0352 ), /* DFEDDM2TRAINLKRATIO */ + DRXJ_16TO8( 0x0352 ), /* DFEDDM2DATALKRATIO */ + DRXJ_16TO8( 0x0000 ), /* DFETRAINGAIN */ + DRXJ_16TO8( 0x2020 ), /* DFERCA1GAIN */ + DRXJ_16TO8( 0x1010 ), /* DFERCA2GAIN */ + DRXJ_16TO8( 0x1818 ), /* DFEDDM1GAIN */ + DRXJ_16TO8( 0x1212 ) /* DFEDDM2GAIN */ + }; + + devAddr = demod -> myI2CDevAddr; + WRB ( devAddr, VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__A, + sizeof(vsb_ffe_leak_gain_ram0), ((pu8_t)vsb_ffe_leak_gain_ram0) ); + WRB ( devAddr, VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__A, + sizeof(vsb_ffe_leak_gain_ram1), ((pu8_t)vsb_ffe_leak_gain_ram1) ); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/** +* \fn DRXStatus_t SetVSB() +* \brief Set 8VSB demod. +* \param demod instance of demodulator. +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +SetVSB ( pDRXDemodInstance_t demod ) +{ + pI2CDeviceAddr_t devAddr = NULL; + u16_t cmdResult = 0; + u16_t cmdParam = 0; + pDRXCommonAttr_t commonAttr = NULL; + DRXJSCUCmd_t cmdSCU; + pDRXJData_t extAttr = NULL; + const u8_t vsb_taps_re[]= { + DRXJ_16TO8( -2 ), /* re0 */ + DRXJ_16TO8( 4 ), /* re1 */ + DRXJ_16TO8( 1 ), /* re2 */ + DRXJ_16TO8( -4 ), /* re3 */ + DRXJ_16TO8( 1 ), /* re4 */ + DRXJ_16TO8( 4 ), /* re5 */ + DRXJ_16TO8( -3 ), /* re6 */ + DRXJ_16TO8( -3 ), /* re7 */ + DRXJ_16TO8( 6 ), /* re8 */ + DRXJ_16TO8( 1 ), /* re9 */ + DRXJ_16TO8( -9 ), /* re10 */ + DRXJ_16TO8( 3 ), /* re11 */ + DRXJ_16TO8( 12 ), /* re12 */ + DRXJ_16TO8( -9 ), /* re13 */ + DRXJ_16TO8( -15 ), /* re14 */ + DRXJ_16TO8( 17 ), /* re15 */ + DRXJ_16TO8( 19 ), /* re16 */ + DRXJ_16TO8( -29 ), /* re17 */ + DRXJ_16TO8( -22 ), /* re18 */ + DRXJ_16TO8( 45 ), /* re19 */ + DRXJ_16TO8( 25 ), /* re20 */ + DRXJ_16TO8( -70 ), /* re21 */ + DRXJ_16TO8( -28 ), /* re22 */ + DRXJ_16TO8( 111 ), /* re23 */ + DRXJ_16TO8( 30 ), /* re24 */ + DRXJ_16TO8( -201 ), /* re25 */ + DRXJ_16TO8( -31 ), /* re26 */ + DRXJ_16TO8( 629 ) /* re27 */ + }; + + devAddr = demod -> myI2CDevAddr; + commonAttr = (pDRXCommonAttr_t) demod -> myCommonAttr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* stop all comm_exec */ + WR16( devAddr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP ); + WR16( devAddr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP ); + WR16( devAddr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP ); + WR16( devAddr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP ); + WR16( devAddr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP ); + WR16( devAddr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP ); + WR16( devAddr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP ); + + /* reset demodulator */ + cmdSCU.command = SCU_RAM_COMMAND_STANDARD_VSB + | SCU_RAM_COMMAND_CMD_DEMOD_RESET; + cmdSCU.parameterLen = 0; + cmdSCU.resultLen = 1; + cmdSCU.parameter = NULL; + cmdSCU.result = &cmdResult; + CHK_ERROR( SCUCommand( devAddr, &cmdSCU ) ); + + WR16( devAddr, IQM_AF_DCF_BYPASS__A, 1 ); + WR16( devAddr, IQM_FS_ADJ_SEL__A, IQM_FS_ADJ_SEL_B_VSB ); + WR16( devAddr, IQM_RC_ADJ_SEL__A, IQM_RC_ADJ_SEL_B_VSB ); + extAttr->iqmRcRateOfs = 0x00AD0D79; + WR32( devAddr, IQM_RC_RATE_OFS_LO__A, extAttr->iqmRcRateOfs ); + WR16( devAddr, VSB_TOP_CFAGC_GAINSHIFT__A, 4); + WR16( devAddr, VSB_TOP_CYGN1TRK__A, 1); + + WR16( devAddr, IQM_RC_CROUT_ENA__A, 1 ); + WR16( devAddr, IQM_RC_STRETCH__A, 28 ); + WR16( devAddr, IQM_RT_ACTIVE__A, 0 ); + WR16( devAddr, IQM_CF_SYMMETRIC__A, 0 ); + WR16( devAddr, IQM_CF_MIDTAP__A, 3 ); + WR16( devAddr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_VSB__M ); + WR16( devAddr, IQM_CF_SCALE__A, 1393 ); + WR16( devAddr, IQM_CF_SCALE_SH__A, 0 ); + WR16( devAddr, IQM_CF_POW_MEAS_LEN__A, 1); + + WRB ( devAddr, IQM_CF_TAP_RE0__A, sizeof(vsb_taps_re), ((pu8_t)vsb_taps_re) ); + WRB ( devAddr, IQM_CF_TAP_IM0__A, sizeof(vsb_taps_re), ((pu8_t)vsb_taps_re) ); + + WR16( devAddr, VSB_TOP_BNTHRESH__A, 330 ); /* set higher threshold */ + WR16( devAddr, VSB_TOP_CLPLASTNUM__A, 90 ); /* burst detection on */ + WR16( devAddr, VSB_TOP_SNRTH_RCA1__A, 0x0042 ); /* drop thresholds by 1 dB */ + WR16( devAddr, VSB_TOP_SNRTH_RCA2__A, 0x0053 ); /* drop thresholds by 2 dB */ + WR16( devAddr, VSB_TOP_EQCTRL__A, 0x1 ); /* cma on */ + WR16( devAddr, SCU_RAM_GPIO__A, 0 ); /* GPIO */ + + /* Initialize the FEC Subsystem */ + WR16( devAddr, FEC_TOP_ANNEX__A, FEC_TOP_ANNEX_D ); + { + u16_t fecOcSncMode = 0; + RR16( devAddr, FEC_OC_SNC_MODE__A, &fecOcSncMode ); + /* output data even when not locked */ + WR16( devAddr, FEC_OC_SNC_MODE__A, fecOcSncMode | FEC_OC_SNC_MODE_UNLOCK_ENABLE__M ); + } + + /* set clip */ + WR16( devAddr, IQM_AF_CLP_LEN__A, 0); + WR16( devAddr, IQM_AF_CLP_TH__A, 470); + WR16( devAddr, IQM_AF_SNS_LEN__A, 0); + WR16( devAddr, VSB_TOP_SNRTH_PT__A, 0xD4 ); + /* no transparent, no A&C framing; parity is set in mpegoutput*/ + { + u16_t fecOcRegMode = 0; + RR16 ( devAddr, FEC_OC_MODE__A , &fecOcRegMode ); + WR16( devAddr, FEC_OC_MODE__A, fecOcRegMode & + (~(FEC_OC_MODE_TRANSPARENT__M + | FEC_OC_MODE_CLEAR__M + | FEC_OC_MODE_RETAIN_FRAMING__M) + ) ); + } + + WR16( devAddr, FEC_DI_TIMEOUT_LO__A, 0 ); /* timeout counter for restarting */ + WR16( devAddr, FEC_DI_TIMEOUT_HI__A, 3 ); + WR16( devAddr, FEC_RS_MODE__A, 0 ); /* bypass disabled */ + /* initialize RS packet error measurement parameters */ + WR16( devAddr, FEC_RS_MEASUREMENT_PERIOD__A, FEC_RS_MEASUREMENT_PERIOD ); + WR16( devAddr, FEC_RS_MEASUREMENT_PRESCALE__A, FEC_RS_MEASUREMENT_PRESCALE ); + + /* init measurement period of MER/SER */ + WR16( devAddr, VSB_TOP_MEASUREMENT_PERIOD__A, VSB_TOP_MEASUREMENT_PERIOD ); + WR32( devAddr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0 ); + WR16( devAddr, SCU_RAM_FEC_MEAS_COUNT__A, 0 ); + WR16( devAddr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0 ); + + WR16( devAddr, VSB_TOP_CKGN1TRK__A, 128 ); + /* B-Input to ADC, PGA+filter in standby */ + if ( extAttr->hasLNA == FALSE ) + { + WR16( devAddr, IQM_AF_AMUX__A, 0x02); + }; + + /* turn on IQMAF. It has to be in front of setAgc**() */ + CHK_ERROR( SetIqmAf( demod, TRUE ) ); + CHK_ERROR(ADCSynchronization (demod)); + + CHK_ERROR( InitAGC( demod ) ); + CHK_ERROR( SetAgcIf( demod, &(extAttr->vsbIfAgcCfg), FALSE ) ); + CHK_ERROR( SetAgcRf( demod, &(extAttr->vsbRfAgcCfg), FALSE ) ); + { + /* TODO fix this, store a DRXJCfgAfeGain_t structure in DRXJData_t instead + of only the gain */ + DRXJCfgAfeGain_t vsbPgaCfg = { DRX_STANDARD_8VSB, 0 }; + + vsbPgaCfg.gain = extAttr->vsbPgaCfg; + CHK_ERROR( CtrlSetCfgAfeGain( demod, &vsbPgaCfg ) ); + } + CHK_ERROR( CtrlSetCfgPreSaw( demod, &(extAttr->vsbPreSawCfg)) ); + + /* Mpeg output has to be in front of FEC active */ + CHK_ERROR ( SetMPEGTEIHandling ( demod )); + CHK_ERROR ( BitReverseMPEGOutput( demod ) ); + CHK_ERROR ( SetMPEGStartWidth ( demod ) ); + { + /* TODO: move to setStandard after hardware reset value problem is solved */ + /* Configure initial MPEG output */ + DRXCfgMPEGOutput_t cfgMPEGOutput; + cfgMPEGOutput.enableMPEGOutput = TRUE; + cfgMPEGOutput.insertRSByte = commonAttr->mpegCfg.insertRSByte; + cfgMPEGOutput.enableParallel = commonAttr->mpegCfg.enableParallel; + cfgMPEGOutput.invertDATA = commonAttr->mpegCfg.invertDATA; + cfgMPEGOutput.invertERR = commonAttr->mpegCfg.invertERR; + cfgMPEGOutput.invertSTR = commonAttr->mpegCfg.invertSTR; + cfgMPEGOutput.invertVAL = commonAttr->mpegCfg.invertVAL; + cfgMPEGOutput.invertCLK = commonAttr->mpegCfg.invertCLK; + cfgMPEGOutput.staticCLK = commonAttr->mpegCfg.staticCLK; + cfgMPEGOutput.bitrate = commonAttr->mpegCfg.bitrate; + CHK_ERROR( CtrlSetCfgMPEGOutput( demod, &cfgMPEGOutput) ); + } + + /* TBD: what parameters should be set */ + cmdParam = 0x00; /* Default mode AGC on, etc */ + cmdSCU.command = SCU_RAM_COMMAND_STANDARD_VSB + | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM; + cmdSCU.parameterLen = 1; + cmdSCU.resultLen = 1; + cmdSCU.parameter = &cmdParam; + cmdSCU.result = &cmdResult; + CHK_ERROR( SCUCommand( devAddr, &cmdSCU ) ); + + WR16(devAddr, VSB_TOP_BEAGC_GAINSHIFT__A, 0x0004 ); + WR16(devAddr, VSB_TOP_SNRTH_PT__A, 0x00D2 ); + WR16(devAddr, VSB_TOP_SYSSMTRNCTRL__A, VSB_TOP_SYSSMTRNCTRL__PRE + |VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__M ); + WR16(devAddr, VSB_TOP_BEDETCTRL__A, 0x142 ); + WR16(devAddr, VSB_TOP_LBAGCREFLVL__A, 640 ); + WR16(devAddr, VSB_TOP_CYGN1ACQ__A, 4 ); + WR16(devAddr, VSB_TOP_CYGN1TRK__A, 2 ); + WR16(devAddr, VSB_TOP_CYGN2TRK__A, 3 ); + + /* start demodulator */ + cmdSCU.command = SCU_RAM_COMMAND_STANDARD_VSB + | SCU_RAM_COMMAND_CMD_DEMOD_START; + cmdSCU.parameterLen = 0; + cmdSCU.resultLen = 1; + cmdSCU.parameter = NULL; + cmdSCU.result = &cmdResult; + CHK_ERROR( SCUCommand( devAddr, &cmdSCU ) ); + + WR16(devAddr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE ); + WR16(devAddr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_ACTIVE ); + WR16(devAddr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE ); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/** +* \fn static short GetVSBPostRSPckErr(pI2CDeviceAddr_t devAddr, pu16_t PckErrs) +* \brief Get the values of packet error in 8VSB mode +* \return Error code +*/ +static DRXStatus_t +GetVSBPostRSPckErr(pI2CDeviceAddr_t devAddr, pu16_t pckErrs) +{ + u16_t data = 0; + u16_t period = 0; + u16_t prescale = 0; + u16_t packetErrorsMant = 0; + u16_t packetErrorsExp = 0; + + RR16(devAddr, FEC_RS_NR_FAILURES__A, &data ); + packetErrorsMant = data & FEC_RS_NR_FAILURES_FIXED_MANT__M; + packetErrorsExp = (data & FEC_RS_NR_FAILURES_EXP__M) + >> FEC_RS_NR_FAILURES_EXP__B; + period = FEC_RS_MEASUREMENT_PERIOD; + prescale = FEC_RS_MEASUREMENT_PRESCALE; + /* packet error rate = (error packet number) per second */ + /* 77.3 us is time for per packet */ + CHK_ZERO (period * prescale); + *pckErrs = (u16_t)FracTimes1e6(packetErrorsMant * (1 << packetErrorsExp), + (period * prescale * 77)); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/** +* \fn static short GetVSBBer(pI2CDeviceAddr_t devAddr, pu32_t ber) +* \brief Get the values of ber in VSB mode +* \return Error code +*/ +static DRXStatus_t +GetVSBpostViterbiBer(pI2CDeviceAddr_t devAddr, pu32_t ber) +{ + u16_t data = 0; + u16_t period = 0; + u16_t prescale = 0; + u16_t bitErrorsMant = 0; + u16_t bitErrorsExp = 0; + + RR16 ( devAddr, FEC_RS_NR_BIT_ERRORS__A, &data ); + period = FEC_RS_MEASUREMENT_PERIOD; + prescale = FEC_RS_MEASUREMENT_PRESCALE; + + bitErrorsMant = data & FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M; + bitErrorsExp = (data & FEC_RS_NR_BIT_ERRORS_EXP__M) + >> FEC_RS_NR_BIT_ERRORS_EXP__B; + + if ( ((bitErrorsMant << bitErrorsExp) >> 3) > 68700) + *ber = 26570; + else + { + CHK_ZERO (period * prescale); + *ber = FracTimes1e6(bitErrorsMant << ((bitErrorsExp > 2)? (bitErrorsExp - 3):bitErrorsExp), + period * prescale * 207 * ((bitErrorsExp > 2)?1:8) ); + } + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/** +* \fn static short GetVSBpreViterbiBer(pI2CDeviceAddr_t devAddr, pu32_t ber) +* \brief Get the values of ber in VSB mode +* \return Error code +*/ +static DRXStatus_t +GetVSBpreViterbiBer(pI2CDeviceAddr_t devAddr, pu32_t ber) +{ + u16_t data = 0; + + RR16 ( devAddr, VSB_TOP_NR_SYM_ERRS__A, &data ); + *ber = FracTimes1e6( data, VSB_TOP_MEASUREMENT_PERIOD * SYMBOLS_PER_SEGMENT ); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/** +* \fn static short GetVSBSymbErr(pI2CDeviceAddr_t devAddr, pu32_t ber) +* \brief Get the values of ber in VSB mode +* \return Error code +*/ +static DRXStatus_t +GetVSBSymbErr(pI2CDeviceAddr_t devAddr, pu32_t ser) +{ + u16_t data = 0; + u16_t period = 0; + u16_t prescale = 0; + u16_t symbErrorsMant = 0; + u16_t symbErrorsExp = 0; + + RR16 ( devAddr, FEC_RS_NR_SYMBOL_ERRORS__A, &data ); + period = FEC_RS_MEASUREMENT_PERIOD; + prescale = FEC_RS_MEASUREMENT_PRESCALE; + + symbErrorsMant = data & FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__M; + symbErrorsExp = (data & FEC_RS_NR_SYMBOL_ERRORS_EXP__M) + >> FEC_RS_NR_SYMBOL_ERRORS_EXP__B; + + CHK_ZERO (period * prescale); + *ser = (u32_t)FracTimes1e6((symbErrorsMant << symbErrorsExp) * 1000, + (period * prescale * 77318)); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/** +* \fn static DRXStatus_t GetVSBMER(pI2CDeviceAddr_t devAddr, pu16_t mer) +* \brief Get the values of MER +* \return Error code +*/ +static DRXStatus_t +GetVSBMER (pI2CDeviceAddr_t devAddr, pu16_t mer) +{ + u16_t dataHi = 0; + + RR16( devAddr, VSB_TOP_ERR_ENERGY_H__A, &dataHi ); + *mer = (u16_t)(Log10Times100( 21504 ) - Log10Times100( (dataHi << 6) / 52 )); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================*/ +/** +* \fn DRXStatus_t CtrlGetVSBConstel() +* \brief Retreive a VSB constellation point via I2C. +* \param demod Pointer to demodulator instance. +* \param complexNr Pointer to the structure in which to store the + constellation point. +* \return DRXStatus_t. +*/ +static DRXStatus_t +CtrlGetVSBConstel( pDRXDemodInstance_t demod, + pDRXComplex_t complexNr ) +{ + pI2CDeviceAddr_t devAddr = NULL; /**< device address */ + u16_t vsbTopCommMb = 0; /**< VSB SL MB configuration */ + u16_t vsbTopCommMbInit = 0; /**< VSB SL MB intial configuration */ + u16_t re = 0; /**< constellation Re part */ + u32_t data = 0; + + /* read device info */ + devAddr = demod -> myI2CDevAddr; + + /* TODO: */ + /* Monitor bus grabbing is an open external interface issue */ + /* Needs to be checked when external interface PG is updated */ + + /* Configure MB (Monitor bus) */ + RR16( devAddr, VSB_TOP_COMM_MB__A, &vsbTopCommMbInit ); + /* set observe flag & MB mux */ + vsbTopCommMb = (vsbTopCommMbInit | + VSB_TOP_COMM_MB_OBS_OBS_ON | + VSB_TOP_COMM_MB_MUX_OBS_VSB_TCMEQ_2 ); + WR16( devAddr, VSB_TOP_COMM_MB__A, vsbTopCommMb ); + + /* Enable MB grabber in the FEC OC */ + WR16( devAddr, FEC_OC_OCR_MODE__A, FEC_OC_OCR_MODE_GRAB_ENABLE__M ); + + /* Disable MB grabber in the FEC OC */ + WR16( devAddr, FEC_OC_OCR_MODE__A, 0x0 ); + + /* read data */ + RR32( devAddr, FEC_OC_OCR_GRAB_RD1__A, &data ); + re = (u16_t)(((data >> 10) & 0x300 ) | ((data >> 2) & 0xff)); + if (re & 0x0200) + { + re |= 0xfc00; + } + complexNr->re = re; + complexNr->im = 0; + + /* Restore MB (Monitor bus) */ + WR16( devAddr, VSB_TOP_COMM_MB__A, vsbTopCommMbInit ); + + return (DRX_STS_OK); + rw_error: + return (DRX_STS_ERROR); +} +/*============================================================================*/ +/*== END 8VSB DATAPATH FUNCTIONS ==*/ +/*============================================================================*/ + +/*============================================================================*/ +/*============================================================================*/ +/*== QAM DATAPATH FUNCTIONS ==*/ +/*============================================================================*/ +/*============================================================================*/ + +/** +* \fn DRXStatus_t PowerDownQAM () +* \brief Powr down QAM related blocks. +* \param demod instance of demodulator. +* \param channel pointer to channel data. +* \return DRXStatus_t. +*/ +static DRXStatus_t +PowerDownQAM( pDRXDemodInstance_t demod, Bool_t primary ) +{ + DRXJSCUCmd_t cmdSCU = { /* command */ 0, + /* parameterLen */ 0, + /* resultLen */ 0, + /* *parameter */ NULL, + /* *result */ NULL }; + u16_t cmdResult = 0; + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + DRXCfgMPEGOutput_t cfgMPEGOutput; + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* + STOP demodulator + resets IQM, QAM and FEC HW blocks + */ + /* stop all comm_exec */ + WR16( devAddr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP); + WR16( devAddr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP); + + cmdSCU.command = SCU_RAM_COMMAND_STANDARD_QAM | + SCU_RAM_COMMAND_CMD_DEMOD_STOP; + cmdSCU.parameterLen = 0; + cmdSCU.resultLen = 1; + cmdSCU.parameter = NULL; + cmdSCU.result = &cmdResult; + CHK_ERROR( SCUCommand( devAddr, &cmdSCU ) ); + + if (primary == TRUE) + { + WR16( devAddr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP ); + CHK_ERROR( SetIqmAf( demod, FALSE ) ); + } + else + { + WR16( devAddr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP ); + WR16( devAddr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP ); + WR16( devAddr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP ); + WR16( devAddr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP ); + WR16( devAddr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP ); + } + + cfgMPEGOutput.enableMPEGOutput = FALSE; + CHK_ERROR( CtrlSetCfgMPEGOutput( demod, &cfgMPEGOutput) ); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t SetQAMMeasurement () +* \brief Setup of the QAM Measuremnt intervals for signal quality +* \param demod instance of demod. +* \param constellation current constellation. +* \return DRXStatus_t. +* +* NOTE: +* Take into account that for certain settings the errorcounters can overflow. +* The implementation does not check this. +* +* TODO: overriding the extAttr->fecBitsDesired by constellation dependent +* constants to get a measurement period of approx. 1 sec. Remove fecBitsDesired +* field ? +* +*/ +#ifndef DRXJ_VSB_ONLY +static DRXStatus_t +SetQAMMeasurement ( pDRXDemodInstance_t demod, + DRXConstellation_t constellation, + u32_t symbolRate ) +{ + pI2CDeviceAddr_t devAddr = NULL; /* device address for I2C writes */ + pDRXJData_t extAttr = NULL; /* Global data container for DRXJ specif data */ + u32_t fecBitsDesired = 0; /* BER accounting period */ + u16_t fecRsPlen = 0; /* defines RS BER measurement period */ + u16_t fecRsPrescale = 0; /* ReedSolomon Measurement Prescale */ + u32_t fecRsPeriod = 0; /* Value for corresponding I2C register */ + u32_t fecRsBitCnt = 0; /* Actual precise amount of bits */ + u32_t fecOcSncFailPeriod = 0; /* Value for corresponding I2C register */ + u32_t qamVdPeriod = 0; /* Value for corresponding I2C register */ + u32_t qamVdBitCnt = 0; /* Actual precise amount of bits */ + u16_t fecVdPlen = 0; /* no of trellis symbols: VD SER measur period */ + u16_t qamVdPrescale = 0; /* Viterbi Measurement Prescale */ + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + fecBitsDesired = extAttr->fecBitsDesired; + fecRsPrescale = extAttr->fecRsPrescale; + + switch ( constellation ) { + case DRX_CONSTELLATION_QAM16: + fecBitsDesired = 4 * symbolRate; + break; + case DRX_CONSTELLATION_QAM32: + fecBitsDesired = 5 * symbolRate; + break; + case DRX_CONSTELLATION_QAM64: + fecBitsDesired = 6 * symbolRate; + break; + case DRX_CONSTELLATION_QAM128: + fecBitsDesired = 7 * symbolRate; + break; + case DRX_CONSTELLATION_QAM256: + fecBitsDesired = 8 * symbolRate; + break; + default: + return (DRX_STS_INVALID_ARG); + } + + /* Parameters for Reed-Solomon Decoder */ + /* fecrs_period = (int)ceil(FEC_BITS_DESIRED/(fecrs_prescale*plen)) */ + /* rs_bit_cnt = fecrs_period*fecrs_prescale*plen */ + /* result is within 32 bit arithmetic -> */ + /* no need for mult or frac functions */ + + /* TODO: use constant instead of calculation and remove the fecRsPlen in extAttr */ + switch ( extAttr->standard ) + { + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_C: + fecRsPlen = 204 * 8; + break; + case DRX_STANDARD_ITU_B: + fecRsPlen = 128 * 7; + break; + default: + return (DRX_STS_INVALID_ARG); + } + + extAttr->fecRsPlen = fecRsPlen; /* for getSigQual */ + fecRsBitCnt = fecRsPrescale * fecRsPlen; /* temp storage */ + CHK_ZERO (fecRsBitCnt); + fecRsPeriod = fecBitsDesired / fecRsBitCnt + 1; /* ceil */ + if (extAttr->standard != DRX_STANDARD_ITU_B) + fecOcSncFailPeriod = fecRsPeriod; + + /* limit to max 16 bit value (I2C register width) if needed */ + if ( fecRsPeriod > 0xFFFF ) + fecRsPeriod = 0xFFFF; + + /* write corresponding registers */ + switch ( extAttr->standard ) + { + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_C: + break; + case DRX_STANDARD_ITU_B: + switch ( constellation ) { + case DRX_CONSTELLATION_QAM64: + fecRsPeriod = 31581; + fecOcSncFailPeriod = 17932; + break; + case DRX_CONSTELLATION_QAM256: + fecRsPeriod = 45446; + fecOcSncFailPeriod = 25805; + break; + default: + return (DRX_STS_INVALID_ARG); + } + break; + default: + return (DRX_STS_INVALID_ARG); + } + + WR16 ( devAddr, FEC_OC_SNC_FAIL_PERIOD__A , ( u16_t ) fecOcSncFailPeriod ); + WR16 ( devAddr, FEC_RS_MEASUREMENT_PERIOD__A , ( u16_t ) fecRsPeriod ); + WR16 ( devAddr, FEC_RS_MEASUREMENT_PRESCALE__A , fecRsPrescale ); + extAttr->fecRsPeriod = (u16_t) fecRsPeriod; + extAttr->fecRsPrescale = fecRsPrescale; + WR32( devAddr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0 ); + WR16( devAddr, SCU_RAM_FEC_MEAS_COUNT__A, 0 ); + WR16( devAddr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0 ); + + if (extAttr->standard == DRX_STANDARD_ITU_B) + { + /* Parameters for Viterbi Decoder */ + /* qamvd_period = (int)ceil(FEC_BITS_DESIRED/ */ + /* (qamvd_prescale*plen*(qam_constellation+1))) */ + /* vd_bit_cnt = qamvd_period*qamvd_prescale*plen */ + /* result is within 32 bit arithmetic -> */ + /* no need for mult or frac functions */ + + /* a(8 bit) * b(8 bit) = 16 bit result => Mult32 not needed */ + fecVdPlen = extAttr->fecVdPlen; + qamVdPrescale = extAttr->qamVdPrescale; + qamVdBitCnt = qamVdPrescale * fecVdPlen; /* temp storage */ + + switch ( constellation ) { + case DRX_CONSTELLATION_QAM64: + /* a(16 bit) * b(4 bit) = 20 bit result => Mult32 not needed */ + qamVdPeriod = qamVdBitCnt * ( QAM_TOP_CONSTELLATION_QAM64 + 1 ) + * ( QAM_TOP_CONSTELLATION_QAM64 + 1 ); + break; + case DRX_CONSTELLATION_QAM256: + /* a(16 bit) * b(5 bit) = 21 bit result => Mult32 not needed */ + qamVdPeriod = qamVdBitCnt * ( QAM_TOP_CONSTELLATION_QAM256 + 1 ) + * ( QAM_TOP_CONSTELLATION_QAM256 + 1 ); + break; + default: + return (DRX_STS_INVALID_ARG); + } + CHK_ZERO (qamVdPeriod); + qamVdPeriod = fecBitsDesired / qamVdPeriod; + /* limit to max 16 bit value (I2C register width) if needed */ + if ( qamVdPeriod > 0xFFFF ) + qamVdPeriod = 0xFFFF; + + /* a(16 bit) * b(16 bit) = 32 bit result => Mult32 not needed */ + qamVdBitCnt *= qamVdPeriod; + + WR16 ( devAddr, QAM_VD_MEASUREMENT_PERIOD__A , ( u16_t ) qamVdPeriod ); + WR16 ( devAddr, QAM_VD_MEASUREMENT_PRESCALE__A , qamVdPrescale ); + extAttr->qamVdPeriod = (u16_t) qamVdPeriod; + extAttr->qamVdPrescale = qamVdPrescale; + } + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t SetQAM16 () +* \brief QAM16 specific setup +* \param demod instance of demod. +* \return DRXStatus_t. +*/ +static DRXStatus_t +SetQAM16 ( pDRXDemodInstance_t demod ) +{ + pI2CDeviceAddr_t devAddr = demod -> myI2CDevAddr; + const u8_t qamDqQualFun[]= { + DRXJ_16TO8( 2 ), /* fun0 */ + DRXJ_16TO8( 2 ), /* fun1 */ + DRXJ_16TO8( 2 ), /* fun2 */ + DRXJ_16TO8( 2 ), /* fun3 */ + DRXJ_16TO8( 3 ), /* fun4 */ + DRXJ_16TO8( 3 ), /* fun5 */ + }; + const u8_t qamEqCmaRad[]= { + DRXJ_16TO8( 13517 ), /* RAD0 */ + DRXJ_16TO8( 13517 ), /* RAD1 */ + DRXJ_16TO8( 13517 ), /* RAD2 */ + DRXJ_16TO8( 13517 ), /* RAD3 */ + DRXJ_16TO8( 13517 ), /* RAD4 */ + DRXJ_16TO8( 13517 ), /* RAD5 */ + }; + + WRB ( devAddr, QAM_DQ_QUAL_FUN0__A, sizeof(qamDqQualFun), ((pu8_t)qamDqQualFun) ); + WRB ( devAddr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qamEqCmaRad), ((pu8_t)qamEqCmaRad) ); + + WR16 ( devAddr, SCU_RAM_QAM_FSM_RTH__A, 140); + WR16 ( devAddr, SCU_RAM_QAM_FSM_FTH__A, 50); + WR16 ( devAddr, SCU_RAM_QAM_FSM_PTH__A, 120); + WR16 ( devAddr, SCU_RAM_QAM_FSM_QTH__A, 230); + WR16 ( devAddr, SCU_RAM_QAM_FSM_CTH__A, 95); + WR16 ( devAddr, SCU_RAM_QAM_FSM_MTH__A, 105); + + WR16 ( devAddr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); + WR16 ( devAddr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56); + WR16 ( devAddr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3); + + WR16 ( devAddr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 16 ); + WR16 ( devAddr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 220); + WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 25 ); + WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 6 ); + WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16_t)(-24) ); + WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16_t)(-65)); + WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16_t)(-127)); + + WR16 ( devAddr, SCU_RAM_QAM_LC_CA_FINE__A, 15); + WR16 ( devAddr, SCU_RAM_QAM_LC_CA_COARSE__A, 40); + WR16 ( devAddr, SCU_RAM_QAM_LC_CP_FINE__A, 2); + WR16 ( devAddr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20); + WR16 ( devAddr, SCU_RAM_QAM_LC_CP_COARSE__A, 255); + WR16 ( devAddr, SCU_RAM_QAM_LC_CI_FINE__A, 2); + WR16 ( devAddr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10); + WR16 ( devAddr, SCU_RAM_QAM_LC_CI_COARSE__A, 50); + WR16 ( devAddr, SCU_RAM_QAM_LC_EP_FINE__A, 12); + WR16 ( devAddr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); + WR16 ( devAddr, SCU_RAM_QAM_LC_EP_COARSE__A, 24); + WR16 ( devAddr, SCU_RAM_QAM_LC_EI_FINE__A, 12); + WR16 ( devAddr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); + WR16 ( devAddr, SCU_RAM_QAM_LC_EI_COARSE__A, 16); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF_FINE__A, 16); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF_COARSE__A, 240); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF1_FINE__A, 5); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32); + + WR16 ( devAddr, SCU_RAM_QAM_SL_SIG_POWER__A, 40960); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t SetQAM32 () +* \brief QAM32 specific setup +* \param demod instance of demod. +* \return DRXStatus_t. +*/ +static DRXStatus_t +SetQAM32 ( pDRXDemodInstance_t demod ) +{ + pI2CDeviceAddr_t devAddr = demod -> myI2CDevAddr; + const u8_t qamDqQualFun[]= { + DRXJ_16TO8( 3 ), /* fun0 */ + DRXJ_16TO8( 3 ), /* fun1 */ + DRXJ_16TO8( 3 ), /* fun2 */ + DRXJ_16TO8( 3 ), /* fun3 */ + DRXJ_16TO8( 4 ), /* fun4 */ + DRXJ_16TO8( 4 ), /* fun5 */ + }; + const u8_t qamEqCmaRad[]= { + DRXJ_16TO8( 6707 ), /* RAD0 */ + DRXJ_16TO8( 6707 ), /* RAD1 */ + DRXJ_16TO8( 6707 ), /* RAD2 */ + DRXJ_16TO8( 6707 ), /* RAD3 */ + DRXJ_16TO8( 6707 ), /* RAD4 */ + DRXJ_16TO8( 6707 ), /* RAD5 */ + }; + + WRB ( devAddr, QAM_DQ_QUAL_FUN0__A, sizeof(qamDqQualFun), ((pu8_t)qamDqQualFun) ); + WRB ( devAddr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qamEqCmaRad), ((pu8_t)qamEqCmaRad) ); + + WR16 ( devAddr, SCU_RAM_QAM_FSM_RTH__A, 90); + WR16 ( devAddr, SCU_RAM_QAM_FSM_FTH__A, 50); + WR16 ( devAddr, SCU_RAM_QAM_FSM_PTH__A, 100); + WR16 ( devAddr, SCU_RAM_QAM_FSM_QTH__A, 170); + WR16 ( devAddr, SCU_RAM_QAM_FSM_CTH__A, 80); + WR16 ( devAddr, SCU_RAM_QAM_FSM_MTH__A, 100); + + WR16 ( devAddr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); + WR16 ( devAddr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56); + WR16 ( devAddr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3); + + WR16 ( devAddr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12 ); + WR16 ( devAddr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 140); + WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16_t)(-8) ); + WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16_t)(-16) ); + WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16_t)(-26) ); + WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16_t)(-56)); + WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16_t)(-86)); + + WR16 ( devAddr, SCU_RAM_QAM_LC_CA_FINE__A, 15); + WR16 ( devAddr, SCU_RAM_QAM_LC_CA_COARSE__A, 40); + WR16 ( devAddr, SCU_RAM_QAM_LC_CP_FINE__A, 2); + WR16 ( devAddr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20); + WR16 ( devAddr, SCU_RAM_QAM_LC_CP_COARSE__A, 255); + WR16 ( devAddr, SCU_RAM_QAM_LC_CI_FINE__A, 2); + WR16 ( devAddr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10); + WR16 ( devAddr, SCU_RAM_QAM_LC_CI_COARSE__A, 50); + WR16 ( devAddr, SCU_RAM_QAM_LC_EP_FINE__A, 12); + WR16 ( devAddr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); + WR16 ( devAddr, SCU_RAM_QAM_LC_EP_COARSE__A, 24); + WR16 ( devAddr, SCU_RAM_QAM_LC_EI_FINE__A, 12); + WR16 ( devAddr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); + WR16 ( devAddr, SCU_RAM_QAM_LC_EI_COARSE__A, 16); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF_FINE__A, 16); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF_COARSE__A, 176); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF1_FINE__A, 5); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF1_COARSE__A, 8); + + WR16 ( devAddr, SCU_RAM_QAM_SL_SIG_POWER__A, 20480); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t SetQAM64 () +* \brief QAM64 specific setup +* \param demod instance of demod. +* \return DRXStatus_t. +*/ +static DRXStatus_t +SetQAM64 ( pDRXDemodInstance_t demod ) +{ + pI2CDeviceAddr_t devAddr = demod -> myI2CDevAddr; + const u8_t qamDqQualFun[]= { /* this is hw reset value. no necessary to re-write */ + DRXJ_16TO8( 4 ), /* fun0 */ + DRXJ_16TO8( 4 ), /* fun1 */ + DRXJ_16TO8( 4 ), /* fun2 */ + DRXJ_16TO8( 4 ), /* fun3 */ + DRXJ_16TO8( 6 ), /* fun4 */ + DRXJ_16TO8( 6 ), /* fun5 */ + }; + const u8_t qamEqCmaRad[]= { + DRXJ_16TO8( 13336 ), /* RAD0 */ + DRXJ_16TO8( 12618 ), /* RAD1 */ + DRXJ_16TO8( 11988 ), /* RAD2 */ + DRXJ_16TO8( 13809 ), /* RAD3 */ + DRXJ_16TO8( 13809 ), /* RAD4 */ + DRXJ_16TO8( 15609 ), /* RAD5 */ + }; + + WRB ( devAddr, QAM_DQ_QUAL_FUN0__A, sizeof(qamDqQualFun), ((pu8_t)qamDqQualFun) ); + WRB ( devAddr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qamEqCmaRad), ((pu8_t)qamEqCmaRad) ); + + WR16 ( devAddr, SCU_RAM_QAM_FSM_RTH__A, 105); + WR16 ( devAddr, SCU_RAM_QAM_FSM_FTH__A, 60); + WR16 ( devAddr, SCU_RAM_QAM_FSM_PTH__A, 100); + WR16 ( devAddr, SCU_RAM_QAM_FSM_QTH__A, 195); + WR16 ( devAddr, SCU_RAM_QAM_FSM_CTH__A, 80); + WR16 ( devAddr, SCU_RAM_QAM_FSM_MTH__A, 84); + + WR16 ( devAddr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); + WR16 ( devAddr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32); + WR16 ( devAddr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3); + + WR16 ( devAddr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12 ); + WR16 ( devAddr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 141); + WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 7 ); + WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 0 ); + WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16_t)(-15)); + WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16_t)(-45)); + WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16_t)(-80)); + + WR16 ( devAddr, SCU_RAM_QAM_LC_CA_FINE__A, 15); + WR16 ( devAddr, SCU_RAM_QAM_LC_CA_COARSE__A, 40); + WR16 ( devAddr, SCU_RAM_QAM_LC_CP_FINE__A, 2); + WR16 ( devAddr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30); + WR16 ( devAddr, SCU_RAM_QAM_LC_CP_COARSE__A, 255); + WR16 ( devAddr, SCU_RAM_QAM_LC_CI_FINE__A, 2); + WR16 ( devAddr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 15); + WR16 ( devAddr, SCU_RAM_QAM_LC_CI_COARSE__A, 80); + WR16 ( devAddr, SCU_RAM_QAM_LC_EP_FINE__A, 12); + WR16 ( devAddr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); + WR16 ( devAddr, SCU_RAM_QAM_LC_EP_COARSE__A, 24); + WR16 ( devAddr, SCU_RAM_QAM_LC_EI_FINE__A, 12); + WR16 ( devAddr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); + WR16 ( devAddr, SCU_RAM_QAM_LC_EI_COARSE__A, 16); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF_FINE__A, 16); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF_COARSE__A, 160); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF1_FINE__A, 5); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32); + + WR16 ( devAddr, SCU_RAM_QAM_SL_SIG_POWER__A, 43008); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t SetQAM128 () +* \brief QAM128 specific setup +* \param demod: instance of demod. +* \return DRXStatus_t. +*/ +static DRXStatus_t +SetQAM128( pDRXDemodInstance_t demod ) +{ + pI2CDeviceAddr_t devAddr = demod -> myI2CDevAddr; + const u8_t qamDqQualFun[]= { + DRXJ_16TO8( 6 ), /* fun0 */ + DRXJ_16TO8( 6 ), /* fun1 */ + DRXJ_16TO8( 6 ), /* fun2 */ + DRXJ_16TO8( 6 ), /* fun3 */ + DRXJ_16TO8( 9 ), /* fun4 */ + DRXJ_16TO8( 9 ), /* fun5 */ + }; + const u8_t qamEqCmaRad[]= { + DRXJ_16TO8( 6164 ), /* RAD0 */ + DRXJ_16TO8( 6598 ), /* RAD1 */ + DRXJ_16TO8( 6394 ), /* RAD2 */ + DRXJ_16TO8( 6409 ), /* RAD3 */ + DRXJ_16TO8( 6656 ), /* RAD4 */ + DRXJ_16TO8( 7238 ), /* RAD5 */ + }; + + WRB ( devAddr, QAM_DQ_QUAL_FUN0__A, sizeof(qamDqQualFun), ((pu8_t)qamDqQualFun) ); + WRB ( devAddr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qamEqCmaRad), ((pu8_t)qamEqCmaRad) ); + + WR16 ( devAddr, SCU_RAM_QAM_FSM_RTH__A, 50); + WR16 ( devAddr, SCU_RAM_QAM_FSM_FTH__A, 60); + WR16 ( devAddr, SCU_RAM_QAM_FSM_PTH__A, 100); + WR16 ( devAddr, SCU_RAM_QAM_FSM_QTH__A, 140); + WR16 ( devAddr, SCU_RAM_QAM_FSM_CTH__A, 80); + WR16 ( devAddr, SCU_RAM_QAM_FSM_MTH__A, 100); + + WR16 ( devAddr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); + WR16 ( devAddr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32); + WR16 ( devAddr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3); + + WR16 ( devAddr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8 ); + WR16 ( devAddr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 65 ); + WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 5 ); + WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 3 ); + WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16_t)(-1) ); + WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 12); + WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16_t)(-23)); + + WR16 ( devAddr, SCU_RAM_QAM_LC_CA_FINE__A, 15); + WR16 ( devAddr, SCU_RAM_QAM_LC_CA_COARSE__A, 40); + WR16 ( devAddr, SCU_RAM_QAM_LC_CP_FINE__A, 2); + WR16 ( devAddr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40); + WR16 ( devAddr, SCU_RAM_QAM_LC_CP_COARSE__A, 255); + WR16 ( devAddr, SCU_RAM_QAM_LC_CI_FINE__A, 2); + WR16 ( devAddr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20); + WR16 ( devAddr, SCU_RAM_QAM_LC_CI_COARSE__A, 80); + WR16 ( devAddr, SCU_RAM_QAM_LC_EP_FINE__A, 12); + WR16 ( devAddr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); + WR16 ( devAddr, SCU_RAM_QAM_LC_EP_COARSE__A, 24); + WR16 ( devAddr, SCU_RAM_QAM_LC_EI_FINE__A, 12); + WR16 ( devAddr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); + WR16 ( devAddr, SCU_RAM_QAM_LC_EI_COARSE__A, 16); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF_FINE__A, 16); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF_COARSE__A, 144); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF1_FINE__A, 5); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16); + + WR16 ( devAddr, SCU_RAM_QAM_SL_SIG_POWER__A, 20992); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t SetQAM256 () +* \brief QAM256 specific setup +* \param demod: instance of demod. +* \return DRXStatus_t. +*/ +static DRXStatus_t +SetQAM256( pDRXDemodInstance_t demod ) +{ + pI2CDeviceAddr_t devAddr = demod -> myI2CDevAddr; + const u8_t qamDqQualFun[]= { + DRXJ_16TO8( 8 ), /* fun0 */ + DRXJ_16TO8( 8 ), /* fun1 */ + DRXJ_16TO8( 8 ), /* fun2 */ + DRXJ_16TO8( 8 ), /* fun3 */ + DRXJ_16TO8( 12 ), /* fun4 */ + DRXJ_16TO8( 12 ), /* fun5 */ + }; + const u8_t qamEqCmaRad[]= { + DRXJ_16TO8( 12345 ), /* RAD0 */ + DRXJ_16TO8( 12345 ), /* RAD1 */ + DRXJ_16TO8( 13626 ), /* RAD2 */ + DRXJ_16TO8( 12931 ), /* RAD3 */ + DRXJ_16TO8( 14719 ), /* RAD4 */ + DRXJ_16TO8( 15356 ), /* RAD5 */ + }; + + WRB ( devAddr, QAM_DQ_QUAL_FUN0__A, sizeof(qamDqQualFun), ((pu8_t)qamDqQualFun) ); + WRB ( devAddr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qamEqCmaRad), ((pu8_t)qamEqCmaRad) ); + + WR16 ( devAddr, SCU_RAM_QAM_FSM_RTH__A, 50); + WR16 ( devAddr, SCU_RAM_QAM_FSM_FTH__A, 60); + WR16 ( devAddr, SCU_RAM_QAM_FSM_PTH__A, 100); + WR16 ( devAddr, SCU_RAM_QAM_FSM_QTH__A, 150); + WR16 ( devAddr, SCU_RAM_QAM_FSM_CTH__A, 80); + WR16 ( devAddr, SCU_RAM_QAM_FSM_MTH__A, 110); + + WR16 ( devAddr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); + WR16 ( devAddr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 16); + WR16 ( devAddr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3); + + WR16 ( devAddr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8); + WR16 ( devAddr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 74); + WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 18); + WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 13); + WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, 7); + WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 0); + WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16_t)(-8)); + + WR16 ( devAddr, SCU_RAM_QAM_LC_CA_FINE__A, 15); + WR16 ( devAddr, SCU_RAM_QAM_LC_CA_COARSE__A, 40); + WR16 ( devAddr, SCU_RAM_QAM_LC_CP_FINE__A, 2); + WR16 ( devAddr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50); + WR16 ( devAddr, SCU_RAM_QAM_LC_CP_COARSE__A, 255); + WR16 ( devAddr, SCU_RAM_QAM_LC_CI_FINE__A, 2); + WR16 ( devAddr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 25); + WR16 ( devAddr, SCU_RAM_QAM_LC_CI_COARSE__A, 80); + WR16 ( devAddr, SCU_RAM_QAM_LC_EP_FINE__A, 12); + WR16 ( devAddr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); + WR16 ( devAddr, SCU_RAM_QAM_LC_EP_COARSE__A, 24); + WR16 ( devAddr, SCU_RAM_QAM_LC_EI_FINE__A, 12); + WR16 ( devAddr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); + WR16 ( devAddr, SCU_RAM_QAM_LC_EI_COARSE__A, 16); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF_FINE__A, 16); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF_COARSE__A, 80); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF1_FINE__A, 5); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16); + + WR16 ( devAddr, SCU_RAM_QAM_SL_SIG_POWER__A, 43520); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================*/ +#define QAM_SET_OP_ALL 0x1 +#define QAM_SET_OP_CONSTELLATION 0x2 +#define QAM_SET_OP_SPECTRUM 0X4 + +/** +* \fn DRXStatus_t SetQAM () +* \brief Set QAM demod. +* \param demod: instance of demod. +* \param channel: pointer to channel data. +* \return DRXStatus_t. +*/ +static DRXStatus_t +SetQAM( pDRXDemodInstance_t demod, + pDRXChannel_t channel, + DRXFrequency_t tunerFreqOffset, + u32_t op + ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + pDRXCommonAttr_t commonAttr = NULL; + u16_t cmdResult = 0; + u32_t adcFrequency = 0; + u32_t iqmRcRate = 0; + u16_t lcSymbolFreq = 0; + u16_t iqmRcStretch = 0; + u16_t setEnvParameters = 0; + u16_t setParamParameters[2] = {0}; + DRXJSCUCmd_t cmdSCU = { /* command */ 0, + /* parameterLen */ 0, + /* resultLen */ 0, + /* parameter */ NULL, + /* result */ NULL }; + const u8_t qamA_taps[]= { + DRXJ_16TO8( -1 ), /* re0 */ + DRXJ_16TO8( 1 ), /* re1 */ + DRXJ_16TO8( 1 ), /* re2 */ + DRXJ_16TO8( -1 ), /* re3 */ + DRXJ_16TO8( -1 ), /* re4 */ + DRXJ_16TO8( 2 ), /* re5 */ + DRXJ_16TO8( 1 ), /* re6 */ + DRXJ_16TO8( -2 ), /* re7 */ + DRXJ_16TO8( 0 ), /* re8 */ + DRXJ_16TO8( 3 ), /* re9 */ + DRXJ_16TO8( -1 ), /* re10 */ + DRXJ_16TO8( -3 ), /* re11 */ + DRXJ_16TO8( 4 ), /* re12 */ + DRXJ_16TO8( 1 ), /* re13 */ + DRXJ_16TO8( -8 ), /* re14 */ + DRXJ_16TO8( 4 ), /* re15 */ + DRXJ_16TO8( 13 ), /* re16 */ + DRXJ_16TO8( -13 ), /* re17 */ + DRXJ_16TO8( -19 ), /* re18 */ + DRXJ_16TO8( 28 ), /* re19 */ + DRXJ_16TO8( 25 ), /* re20 */ + DRXJ_16TO8( -53 ), /* re21 */ + DRXJ_16TO8( -31 ), /* re22 */ + DRXJ_16TO8( 96 ), /* re23 */ + DRXJ_16TO8( 37 ), /* re24 */ + DRXJ_16TO8( -190 ), /* re25 */ + DRXJ_16TO8( -40 ), /* re26 */ + DRXJ_16TO8( 619 ) /* re27 */ + }; + const u8_t qamB64_taps[]= { + DRXJ_16TO8( 0 ), /* re0 */ + DRXJ_16TO8( -2 ), /* re1 */ + DRXJ_16TO8( 1 ), /* re2 */ + DRXJ_16TO8( 2 ), /* re3 */ + DRXJ_16TO8( -2 ), /* re4 */ + DRXJ_16TO8( 0 ), /* re5 */ + DRXJ_16TO8( 4 ), /* re6 */ + DRXJ_16TO8( -2 ), /* re7 */ + DRXJ_16TO8( -4 ), /* re8 */ + DRXJ_16TO8( 4 ), /* re9 */ + DRXJ_16TO8( 3 ), /* re10 */ + DRXJ_16TO8( -6 ), /* re11 */ + DRXJ_16TO8( 0 ), /* re12 */ + DRXJ_16TO8( 6 ), /* re13 */ + DRXJ_16TO8( -5 ), /* re14 */ + DRXJ_16TO8( -3 ), /* re15 */ + DRXJ_16TO8( 11 ), /* re16 */ + DRXJ_16TO8( -4 ), /* re17 */ + DRXJ_16TO8( -19 ), /* re18 */ + DRXJ_16TO8( 19 ), /* re19 */ + DRXJ_16TO8( 28 ), /* re20 */ + DRXJ_16TO8( -45 ), /* re21 */ + DRXJ_16TO8( -36 ), /* re22 */ + DRXJ_16TO8( 90 ), /* re23 */ + DRXJ_16TO8( 42 ), /* re24 */ + DRXJ_16TO8( -185 ), /* re25 */ + DRXJ_16TO8( -46 ), /* re26 */ + DRXJ_16TO8( 614 ) /* re27 */ + }; + const u8_t qamB256_taps[]= { + DRXJ_16TO8( -2 ), /* re0 */ + DRXJ_16TO8( 4 ), /* re1 */ + DRXJ_16TO8( 1 ), /* re2 */ + DRXJ_16TO8( -4 ), /* re3 */ + DRXJ_16TO8( 0 ), /* re4 */ + DRXJ_16TO8( 4 ), /* re5 */ + DRXJ_16TO8( -2 ), /* re6 */ + DRXJ_16TO8( -4 ), /* re7 */ + DRXJ_16TO8( 5 ), /* re8 */ + DRXJ_16TO8( 2 ), /* re9 */ + DRXJ_16TO8( -8 ), /* re10 */ + DRXJ_16TO8( 2 ), /* re11 */ + DRXJ_16TO8( 11 ), /* re12 */ + DRXJ_16TO8( -8 ), /* re13 */ + DRXJ_16TO8( -15 ), /* re14 */ + DRXJ_16TO8( 16 ), /* re15 */ + DRXJ_16TO8( 19 ), /* re16 */ + DRXJ_16TO8( -27 ), /* re17 */ + DRXJ_16TO8( -22 ), /* re18 */ + DRXJ_16TO8( 44 ), /* re19 */ + DRXJ_16TO8( 26 ), /* re20 */ + DRXJ_16TO8( -69 ), /* re21 */ + DRXJ_16TO8( -28 ), /* re22 */ + DRXJ_16TO8( 110 ), /* re23 */ + DRXJ_16TO8( 31 ), /* re24 */ + DRXJ_16TO8( -201 ), /* re25 */ + DRXJ_16TO8( -32 ), /* re26 */ + DRXJ_16TO8( 628 ) /* re27 */ + }; + const u8_t qamC_taps[]= { + DRXJ_16TO8( -3 ), /* re0 */ + DRXJ_16TO8( 3 ), /* re1 */ + DRXJ_16TO8( 2 ), /* re2 */ + DRXJ_16TO8( -4 ), /* re3 */ + DRXJ_16TO8( 0 ), /* re4 */ + DRXJ_16TO8( 4 ), /* re5 */ + DRXJ_16TO8( -1 ), /* re6 */ + DRXJ_16TO8( -4 ), /* re7 */ + DRXJ_16TO8( 3 ), /* re8 */ + DRXJ_16TO8( 3 ), /* re9 */ + DRXJ_16TO8( -5 ), /* re10 */ + DRXJ_16TO8( 0 ), /* re11 */ + DRXJ_16TO8( 9 ), /* re12 */ + DRXJ_16TO8( -4 ), /* re13 */ + DRXJ_16TO8( -12 ), /* re14 */ + DRXJ_16TO8( 10 ), /* re15 */ + DRXJ_16TO8( 16 ), /* re16 */ + DRXJ_16TO8( -21 ), /* re17 */ + DRXJ_16TO8( -20 ), /* re18 */ + DRXJ_16TO8( 37 ), /* re19 */ + DRXJ_16TO8( 25 ), /* re20 */ + DRXJ_16TO8( -62 ), /* re21 */ + DRXJ_16TO8( -28 ), /* re22 */ + DRXJ_16TO8( 105 ), /* re23 */ + DRXJ_16TO8( 31 ), /* re24 */ + DRXJ_16TO8( -197 ), /* re25 */ + DRXJ_16TO8( -33 ), /* re26 */ + DRXJ_16TO8( 626 ) /* re27 */ + }; + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod -> myExtAttr; + commonAttr = (pDRXCommonAttr_t) demod -> myCommonAttr; + + if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION )) + { + if ( extAttr->standard == DRX_STANDARD_ITU_B ) + { + switch ( channel->constellation ) + { + case DRX_CONSTELLATION_QAM256 : + iqmRcRate = 0x00AE3562; + lcSymbolFreq = QAM_LC_SYMBOL_FREQ_FREQ_QAM_B_256; + channel->symbolrate = 5360537; + iqmRcStretch = IQM_RC_STRETCH_QAM_B_256; + break; + case DRX_CONSTELLATION_QAM64 : + iqmRcRate = 0x00C05A0E; + lcSymbolFreq = 409; + channel->symbolrate = 5056941; + iqmRcStretch = IQM_RC_STRETCH_QAM_B_64; + break; + default : + return (DRX_STS_INVALID_ARG); + } + } + else + { + adcFrequency = ( commonAttr->sysClockFreq * 1000 ) / 3; + CHK_ZERO (channel->symbolrate); + iqmRcRate = ( adcFrequency / channel->symbolrate ) * ( 1 << 21 ) + + ( Frac28 ( ( adcFrequency % channel->symbolrate ), channel->symbolrate ) >> 7 ) - ( 1 << 23 ); + lcSymbolFreq = (u16_t)( Frac28 ( channel->symbolrate + (adcFrequency >> 13), adcFrequency ) >> 16 ); + if (lcSymbolFreq > 511) + lcSymbolFreq = 511; + + iqmRcStretch = 21; + } + + if( extAttr->standard == DRX_STANDARD_ITU_A ) + { + setEnvParameters = QAM_TOP_ANNEX_A; /* annex */ + setParamParameters[0] = channel->constellation; /* constellation */ + setParamParameters[1] = DRX_INTERLEAVEMODE_I12_J17; /* interleave mode */ + } + else if( extAttr->standard == DRX_STANDARD_ITU_B ) + { + setEnvParameters = QAM_TOP_ANNEX_B; /* annex */ + setParamParameters[0] = channel->constellation; /* constellation */ + setParamParameters[1] = channel->interleavemode; /* interleave mode */ + } + else if( extAttr->standard == DRX_STANDARD_ITU_C ) + { + setEnvParameters = QAM_TOP_ANNEX_C; /* annex */ + setParamParameters[0] = channel->constellation; /* constellation */ + setParamParameters[1] = DRX_INTERLEAVEMODE_I12_J17; /* interleave mode */ + } + else + { + return (DRX_STS_INVALID_ARG); + } + } + + if (op & QAM_SET_OP_ALL) + { + /* + STEP 1: reset demodulator + resets IQM, QAM and FEC HW blocks + resets SCU variables + */ + /* stop all comm_exec */ + WR16( devAddr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP ); + WR16( devAddr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP ); + WR16( devAddr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP ); + WR16( devAddr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP ); + WR16( devAddr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP ); + WR16( devAddr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP ); + WR16( devAddr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP ); + + cmdSCU.command = SCU_RAM_COMMAND_STANDARD_QAM | + SCU_RAM_COMMAND_CMD_DEMOD_RESET; + cmdSCU.parameterLen = 0; + cmdSCU.resultLen = 1; + cmdSCU.parameter = NULL; + cmdSCU.result = &cmdResult; + CHK_ERROR( SCUCommand( devAddr, &cmdSCU ) ); + } + + if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION )) + { + /* + STEP 2: configure demodulator + -set env + -set params (resets IQM,QAM,FEC HW; initializes some SCU variables ) + */ + cmdSCU.command = SCU_RAM_COMMAND_STANDARD_QAM | + SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV; + cmdSCU.parameterLen = 1; + cmdSCU.resultLen = 1; + cmdSCU.parameter = &setEnvParameters; + cmdSCU.result = &cmdResult; + CHK_ERROR( SCUCommand( devAddr, &cmdSCU ) ); + + cmdSCU.command = SCU_RAM_COMMAND_STANDARD_QAM | + SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM; + cmdSCU.parameterLen = 2; + cmdSCU.resultLen = 1; + cmdSCU.parameter = setParamParameters; + cmdSCU.result = &cmdResult; + CHK_ERROR( SCUCommand( devAddr, &cmdSCU ) ); + /* set symbol rate */ + WR32( devAddr, IQM_RC_RATE_OFS_LO__A, iqmRcRate ); + extAttr->iqmRcRateOfs = iqmRcRate; + CHK_ERROR( SetQAMMeasurement ( demod, channel->constellation, channel->symbolrate)); + } + /* STEP 3: enable the system in a mode where the ADC provides valid signal + setup constellation independent registers */ + /* from qam_cmd.py script (qam_driver_b)*/ + /* TODO: remove re-writes of HW reset values */ + if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_SPECTRUM )) + { + CHK_ERROR ( SetFrequency ( demod, channel, tunerFreqOffset ) ); + } + + if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION )) + { + + WR16( devAddr, QAM_LC_SYMBOL_FREQ__A, lcSymbolFreq); + WR16( devAddr, IQM_RC_STRETCH__A, iqmRcStretch ); + } + + if (op & QAM_SET_OP_ALL) + { + if (extAttr->hasLNA==FALSE) + { + WR16( devAddr, IQM_AF_AMUX__A, 0x02); + } + WR16( devAddr, IQM_CF_SYMMETRIC__A, 0 ); + WR16( devAddr, IQM_CF_MIDTAP__A, 3 ); + WR16( devAddr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_QAM__M ); + + WR16( devAddr, SCU_RAM_QAM_WR_RSV_0__A, 0x5f); /* scu temporary shut down agc */ + + WR16( devAddr, IQM_AF_SYNC_SEL__A, 3); + WR16( devAddr, IQM_AF_CLP_LEN__A, 0); + WR16( devAddr, IQM_AF_CLP_TH__A, 448); + WR16( devAddr, IQM_AF_SNS_LEN__A, 0); + WR16( devAddr, IQM_AF_PDREF__A, 4); + WR16( devAddr, IQM_AF_STDBY__A, 0x10); + WR16( devAddr, IQM_AF_PGA_GAIN__A, 11); + + WR16( devAddr, IQM_CF_POW_MEAS_LEN__A, 1); + WR16( devAddr, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE); /*! reset default val ! */ + + WR16( devAddr, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE); /*! reset default val ! */ + if( extAttr->standard == DRX_STANDARD_ITU_B ) + { + WR16( devAddr, QAM_SY_SYNC_LWM__A, QAM_SY_SYNC_LWM__PRE); /*! reset default val ! */ + WR16( devAddr, QAM_SY_SYNC_AWM__A, QAM_SY_SYNC_AWM__PRE); /*! reset default val ! */ + WR16( devAddr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE); /*! reset default val ! */ + } + else + { + switch ( channel->constellation ) { + case DRX_CONSTELLATION_QAM16: + case DRX_CONSTELLATION_QAM64: + case DRX_CONSTELLATION_QAM256: + WR16( devAddr, QAM_SY_SYNC_LWM__A, 0x03); + WR16( devAddr, QAM_SY_SYNC_AWM__A, 0x04); + WR16( devAddr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE); /*! reset default val ! */ + break; + case DRX_CONSTELLATION_QAM32: + case DRX_CONSTELLATION_QAM128: + WR16( devAddr, QAM_SY_SYNC_LWM__A, 0x03); + WR16( devAddr, QAM_SY_SYNC_AWM__A, 0x05); + WR16( devAddr, QAM_SY_SYNC_HWM__A, 0x06); + break; + default: + return (DRX_STS_ERROR); + } /* switch */ + } + + WR16( devAddr, QAM_LC_MODE__A, QAM_LC_MODE__PRE); /*! reset default val ! */ + WR16( devAddr, QAM_LC_RATE_LIMIT__A, 3); + WR16( devAddr, QAM_LC_LPF_FACTORP__A, 4); + WR16( devAddr, QAM_LC_LPF_FACTORI__A, 4); + WR16( devAddr, QAM_LC_MODE__A, 7); + WR16( devAddr, QAM_LC_QUAL_TAB0__A, 1); + WR16( devAddr, QAM_LC_QUAL_TAB1__A, 1); + WR16( devAddr, QAM_LC_QUAL_TAB2__A, 1); + WR16( devAddr, QAM_LC_QUAL_TAB3__A, 1); + WR16( devAddr, QAM_LC_QUAL_TAB4__A, 2); + WR16( devAddr, QAM_LC_QUAL_TAB5__A, 2); + WR16( devAddr, QAM_LC_QUAL_TAB6__A, 2); + WR16( devAddr, QAM_LC_QUAL_TAB8__A, 2); + WR16( devAddr, QAM_LC_QUAL_TAB9__A, 2); + WR16( devAddr, QAM_LC_QUAL_TAB10__A, 2); + WR16( devAddr, QAM_LC_QUAL_TAB12__A, 2); + WR16( devAddr, QAM_LC_QUAL_TAB15__A, 3); + WR16( devAddr, QAM_LC_QUAL_TAB16__A, 3); + WR16( devAddr, QAM_LC_QUAL_TAB20__A, 4); + WR16( devAddr, QAM_LC_QUAL_TAB25__A, 4); + + WR16( devAddr, IQM_FS_ADJ_SEL__A, 1); + WR16( devAddr, IQM_RC_ADJ_SEL__A, 1); + WR16( devAddr, IQM_CF_ADJ_SEL__A, 1); + WR16( devAddr, IQM_CF_POW_MEAS_LEN__A, 0); + WR16( devAddr, SCU_RAM_GPIO__A, 0 ); + + /* No more resets of the IQM, current standard correctly set => + now AGCs can be configured. */ + /* turn on IQMAF. It has to be in front of setAgc**() */ + CHK_ERROR( SetIqmAf( demod, TRUE ) ); + CHK_ERROR(ADCSynchronization (demod)); + + CHK_ERROR( InitAGC( demod ) ); + CHK_ERROR( SetAgcIf( demod, &(extAttr->qamIfAgcCfg), FALSE ) ); + CHK_ERROR( SetAgcRf( demod, &(extAttr->qamRfAgcCfg), FALSE ) ); + { + /* TODO fix this, store a DRXJCfgAfeGain_t structure in DRXJData_t instead + of only the gain */ + DRXJCfgAfeGain_t qamPgaCfg = { DRX_STANDARD_ITU_B, 0 }; + + qamPgaCfg.gain = extAttr->qamPgaCfg; + CHK_ERROR( CtrlSetCfgAfeGain( demod, &qamPgaCfg ) ); + } + CHK_ERROR( CtrlSetCfgPreSaw( demod, &(extAttr->qamPreSawCfg)) ); + } + + if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION )) + { + if( extAttr->standard == DRX_STANDARD_ITU_A ) + { + WRB ( devAddr, IQM_CF_TAP_RE0__A, sizeof(qamA_taps), ((pu8_t)qamA_taps) ); + WRB ( devAddr, IQM_CF_TAP_IM0__A, sizeof(qamA_taps), ((pu8_t)qamA_taps) ); + } + else if ( extAttr->standard == DRX_STANDARD_ITU_B ) + { + switch ( channel->constellation ) { + case DRX_CONSTELLATION_QAM64: + WRB ( devAddr, IQM_CF_TAP_RE0__A, sizeof(qamB64_taps), ((pu8_t)qamB64_taps) ); + WRB ( devAddr, IQM_CF_TAP_IM0__A, sizeof(qamB64_taps), ((pu8_t)qamB64_taps) ); + break; + case DRX_CONSTELLATION_QAM256: + WRB ( devAddr, IQM_CF_TAP_RE0__A, sizeof(qamB256_taps), ((pu8_t)qamB256_taps) ); + WRB ( devAddr, IQM_CF_TAP_IM0__A, sizeof(qamB256_taps), ((pu8_t)qamB256_taps) ); + break; + default: + return (DRX_STS_ERROR); + } + } + else if ( extAttr->standard == DRX_STANDARD_ITU_C ) + { + WRB ( devAddr, IQM_CF_TAP_RE0__A, sizeof(qamC_taps), ((pu8_t)qamC_taps) ); + WRB ( devAddr, IQM_CF_TAP_IM0__A, sizeof(qamC_taps), ((pu8_t)qamC_taps) ); + } + + /* SETP 4: constellation specific setup */ + switch ( channel->constellation ) { + case DRX_CONSTELLATION_QAM16: + CHK_ERROR(SetQAM16( demod )); + break; + case DRX_CONSTELLATION_QAM32: + CHK_ERROR(SetQAM32( demod )); + break; + case DRX_CONSTELLATION_QAM64: + CHK_ERROR(SetQAM64( demod )); + break; + case DRX_CONSTELLATION_QAM128: + CHK_ERROR(SetQAM128( demod )); + break; + case DRX_CONSTELLATION_QAM256: + CHK_ERROR(SetQAM256( demod )); + break; + default: + return (DRX_STS_ERROR); + } /* switch */ + } + + if ((op & QAM_SET_OP_ALL)) + { + WR16(devAddr, IQM_CF_SCALE_SH__A, 0 ); + + /* Mpeg output has to be in front of FEC active */ + CHK_ERROR ( SetMPEGTEIHandling( demod )); + CHK_ERROR ( BitReverseMPEGOutput( demod ) ); + CHK_ERROR ( SetMPEGStartWidth ( demod ) ); + { + /* TODO: move to setStandard after hardware reset value problem is solved */ + /* Configure initial MPEG output */ + DRXCfgMPEGOutput_t cfgMPEGOutput; + + cfgMPEGOutput.enableMPEGOutput = TRUE; + cfgMPEGOutput.insertRSByte = commonAttr->mpegCfg.insertRSByte; + cfgMPEGOutput.enableParallel = commonAttr->mpegCfg.enableParallel; + cfgMPEGOutput.invertDATA = commonAttr->mpegCfg.invertDATA; + cfgMPEGOutput.invertERR = commonAttr->mpegCfg.invertERR; + cfgMPEGOutput.invertSTR = commonAttr->mpegCfg.invertSTR; + cfgMPEGOutput.invertVAL = commonAttr->mpegCfg.invertVAL; + cfgMPEGOutput.invertCLK = commonAttr->mpegCfg.invertCLK; + cfgMPEGOutput.staticCLK = commonAttr->mpegCfg.staticCLK; + cfgMPEGOutput.bitrate = commonAttr->mpegCfg.bitrate; + CHK_ERROR( CtrlSetCfgMPEGOutput( demod, &cfgMPEGOutput) ); + } + } + + if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION )) + { + + /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */ + cmdSCU.command = SCU_RAM_COMMAND_STANDARD_QAM | + SCU_RAM_COMMAND_CMD_DEMOD_START; + cmdSCU.parameterLen = 0; + cmdSCU.resultLen = 1; + cmdSCU.parameter = NULL; + cmdSCU.result = &cmdResult; + CHK_ERROR( SCUCommand( devAddr, &cmdSCU ) ); + } + + WR16(devAddr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE ); + WR16(devAddr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE ); + WR16(devAddr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE ); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================*/ +static DRXStatus_t +CtrlGetQAMSigQuality( pDRXDemodInstance_t demod, + pDRXSigQuality_t sigQuality ); +static DRXStatus_t +qamFlipSpec ( pDRXDemodInstance_t demod, + pDRXChannel_t channel) +{ + u32_t iqmFsRateOfs = 0; + u32_t iqmFsRateLo = 0; + u16_t qamCtlEna = 0; + u16_t data = 0; + u16_t equMode = 0; + u16_t fsmState = 0; + int i = 0; + int ofsofs = 0; + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* Silence the controlling of lc, equ, and the acquisition state machine */ + RR16( devAddr, SCU_RAM_QAM_CTL_ENA__A, &qamCtlEna ); + WR16( devAddr, SCU_RAM_QAM_CTL_ENA__A, qamCtlEna + & ~ ( SCU_RAM_QAM_CTL_ENA_ACQ__M + | SCU_RAM_QAM_CTL_ENA_EQU__M + | SCU_RAM_QAM_CTL_ENA_LC__M) ); + + /* freeze the frequency control loop */ + WR16( devAddr, QAM_LC_CF__A, 0); + WR16( devAddr, QAM_LC_CF1__A, 0); + + ARR32( devAddr, IQM_FS_RATE_OFS_LO__A , &iqmFsRateOfs ); + ARR32( devAddr, IQM_FS_RATE_LO__A, &iqmFsRateLo ); + ofsofs = iqmFsRateLo - iqmFsRateOfs; + iqmFsRateOfs = ~iqmFsRateOfs + 1; + iqmFsRateOfs -= 2 * ofsofs; + + /* freeze dq/fq updating */ + RR16( devAddr, QAM_DQ_MODE__A, &data); + data = (data & 0xfff9); + WR16( devAddr, QAM_DQ_MODE__A, data ); + WR16( devAddr, QAM_FQ_MODE__A, data ); + + /* lc_cp / _ci / _ca */ + WR16( devAddr, QAM_LC_CI__A, 0 ); + WR16( devAddr, QAM_LC_EP__A, 0 ); + WR16( devAddr, QAM_FQ_LA_FACTOR__A, 0 ); + + /* flip the spec */ + WR32( devAddr, IQM_FS_RATE_OFS_LO__A , iqmFsRateOfs ); + extAttr->iqmFsRateOfs = iqmFsRateOfs; + extAttr->posImage = (extAttr->posImage)?FALSE:TRUE; + + /* freeze dq/fq updating */ + RR16( devAddr, QAM_DQ_MODE__A, &data); + equMode = data; + data = (data & 0xfff9); + WR16( devAddr, QAM_DQ_MODE__A, data ); + WR16( devAddr, QAM_FQ_MODE__A, data ); + + for ( i = 0; i < 28; i++) + { + RR16( devAddr, QAM_DQ_TAP_IM_EL0__A + (2 * i), &data); + WR16( devAddr, QAM_DQ_TAP_IM_EL0__A + (2 * i), -data); + } + + for ( i = 0; i < 24; i++) + { + RR16( devAddr, QAM_FQ_TAP_IM_EL0__A + (2 * i), &data); + WR16( devAddr, QAM_FQ_TAP_IM_EL0__A + (2 * i), -data); + } + + data = equMode; + WR16( devAddr, QAM_DQ_MODE__A, data ); + WR16( devAddr, QAM_FQ_MODE__A, data ); + + WR16( devAddr, SCU_RAM_QAM_FSM_STATE_TGT__A, 4 ); + + i = 0; + while ( (fsmState != 4) && (i++ < 100) ) + { + RR16( devAddr, SCU_RAM_QAM_FSM_STATE__A, &fsmState ); + } + WR16( devAddr, SCU_RAM_QAM_CTL_ENA__A, (qamCtlEna | 0x0016) ); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); + +} + +#define NO_LOCK 0x0 +#define DEMOD_LOCKED 0x1 +#define SYNC_FLIPPED 0x2 +#define SPEC_MIRRORED 0x4 +/** +* \fn DRXStatus_t QAM64Auto () +* \brief auto do sync pattern switching and mirroring. +* \param demod: instance of demod. +* \param channel: pointer to channel data. +* \param tunerFreqOffset: tuner frequency offset. +* \param lockStatus: pointer to lock status. +* \return DRXStatus_t. +*/ +static DRXStatus_t +QAM64Auto( pDRXDemodInstance_t demod, + pDRXChannel_t channel, + DRXFrequency_t tunerFreqOffset, + pDRXLockStatus_t lockStatus + ) +{ + DRXSigQuality_t sigQuality; + u16_t data = 0; + u32_t state = NO_LOCK; + u32_t startTime = 0; + u32_t dLockedTime= 0; + pDRXJData_t extAttr = NULL; + u32_t timeoutOfs = 0; + + /* external attributes for storing aquired channel constellation */ + extAttr = (pDRXJData_t)demod -> myExtAttr; + *lockStatus = DRX_NOT_LOCKED; + startTime = DRXBSP_HST_Clock(); + state = NO_LOCK; + do + { + CHK_ERROR( CtrlLockStatus(demod, lockStatus) ); + + switch (state) + { + case NO_LOCK: + if ( *lockStatus == DRXJ_DEMOD_LOCK ) + { + CHK_ERROR ( CtrlGetQAMSigQuality ( demod, &sigQuality ) ); + if (sigQuality.MER > 208) + { + state = DEMOD_LOCKED; + /* some delay to see if fec_lock possible TODO find the right value */ + timeoutOfs += DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME; /* see something, waiting longer */ + dLockedTime = DRXBSP_HST_Clock(); + } + } + break; + case DEMOD_LOCKED: + if ((*lockStatus == DRXJ_DEMOD_LOCK) && /* still demod_lock in 150ms*/ + ((DRXBSP_HST_Clock() - dLockedTime) > DRXJ_QAM_FEC_LOCK_WAITTIME)) + { + RR16( demod->myI2CDevAddr, QAM_SY_TIMEOUT__A, &data ); + WR16( demod->myI2CDevAddr, QAM_SY_TIMEOUT__A, data | 0x1 ); + state = SYNC_FLIPPED; + DRXBSP_HST_Sleep(10); + } + break; + case SYNC_FLIPPED: + if (*lockStatus == DRXJ_DEMOD_LOCK) + { + if (channel->mirror == DRX_MIRROR_AUTO) + { + /* flip sync pattern back */ + RR16( demod->myI2CDevAddr, QAM_SY_TIMEOUT__A, &data ); + WR16( demod->myI2CDevAddr, QAM_SY_TIMEOUT__A, data & 0xFFFE ); + /* flip spectrum */ + extAttr->mirror = DRX_MIRROR_YES; + CHK_ERROR ( qamFlipSpec ( demod, channel ) ); + state = SPEC_MIRRORED; + /* reset timer TODO: still need 500ms? */ + startTime = dLockedTime = DRXBSP_HST_Clock(); + timeoutOfs = 0; + } + else /* no need to wait lock */ + { + startTime = DRXBSP_HST_Clock() - DRXJ_QAM_MAX_WAITTIME - timeoutOfs; + } + } + break; + case SPEC_MIRRORED: + if ((*lockStatus == DRXJ_DEMOD_LOCK) && /* still demod_lock in 150ms*/ + ((DRXBSP_HST_Clock() - dLockedTime) > DRXJ_QAM_FEC_LOCK_WAITTIME)) + { + CHK_ERROR ( CtrlGetQAMSigQuality ( demod, &sigQuality ) ); + if (sigQuality.MER > 208) + { + RR16( demod->myI2CDevAddr, QAM_SY_TIMEOUT__A, &data ); + WR16( demod->myI2CDevAddr, QAM_SY_TIMEOUT__A, data | 0x1 ); + /* no need to wait lock */ + startTime = DRXBSP_HST_Clock() - DRXJ_QAM_MAX_WAITTIME - timeoutOfs; + } + } + break; + default: + break; + } + DRXBSP_HST_Sleep(10); + } while + ( ( *lockStatus != DRX_LOCKED ) && + ( *lockStatus != DRX_NEVER_LOCK ) && + ( (DRXBSP_HST_Clock() - startTime) < (DRXJ_QAM_MAX_WAITTIME + timeoutOfs)) + ); + /* Returning control to apllication ... */ + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/** +* \fn DRXStatus_t QAM256Auto () +* \brief auto do sync pattern switching and mirroring. +* \param demod: instance of demod. +* \param channel: pointer to channel data. +* \param tunerFreqOffset: tuner frequency offset. +* \param lockStatus: pointer to lock status. +* \return DRXStatus_t. +*/ +static DRXStatus_t +QAM256Auto( pDRXDemodInstance_t demod, + pDRXChannel_t channel, + DRXFrequency_t tunerFreqOffset, + pDRXLockStatus_t lockStatus + ) +{ + DRXSigQuality_t sigQuality; + u32_t state = NO_LOCK; + u32_t startTime = 0; + u32_t dLockedTime= 0; + pDRXJData_t extAttr = NULL; + u32_t timeoutOfs = DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME; + + /* external attributes for storing aquired channel constellation */ + extAttr = (pDRXJData_t)demod -> myExtAttr; + *lockStatus = DRX_NOT_LOCKED; + startTime = DRXBSP_HST_Clock(); + state = NO_LOCK; + do + { + CHK_ERROR( CtrlLockStatus( demod, lockStatus) ); + switch (state) + { + case NO_LOCK: + if ( *lockStatus == DRXJ_DEMOD_LOCK ) + { + CHK_ERROR ( CtrlGetQAMSigQuality ( demod, &sigQuality ) ); + if (sigQuality.MER > 268) + { + state = DEMOD_LOCKED; + timeoutOfs += DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME; /* see something, wait longer */ + dLockedTime = DRXBSP_HST_Clock(); + } + } + break; + case DEMOD_LOCKED: + if ( *lockStatus == DRXJ_DEMOD_LOCK ) + { + if ((channel->mirror == DRX_MIRROR_AUTO) && + ((DRXBSP_HST_Clock() - dLockedTime) > DRXJ_QAM_FEC_LOCK_WAITTIME)) + { + extAttr->mirror = DRX_MIRROR_YES; + CHK_ERROR ( qamFlipSpec ( demod, channel ) ); + state = SPEC_MIRRORED; + /* reset timer TODO: still need 300ms? */ + startTime = DRXBSP_HST_Clock(); + timeoutOfs = - DRXJ_QAM_MAX_WAITTIME / 2; + } + } + break; + case SPEC_MIRRORED: + break; + default: + break; + } + DRXBSP_HST_Sleep(10); + } while + ( ( *lockStatus < DRX_LOCKED ) && + ( *lockStatus != DRX_NEVER_LOCK ) && + ( (DRXBSP_HST_Clock() - startTime) < (DRXJ_QAM_MAX_WAITTIME + timeoutOfs)) ); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/** +* \fn DRXStatus_t SetQAMChannel () +* \brief Set QAM channel according to the requested constellation. +* \param demod: instance of demod. +* \param channel: pointer to channel data. +* \return DRXStatus_t. +*/ +static DRXStatus_t +SetQAMChannel( pDRXDemodInstance_t demod, + pDRXChannel_t channel, + DRXFrequency_t tunerFreqOffset + ) +{ + DRXLockStatus_t lockStatus = DRX_NOT_LOCKED; + pDRXJData_t extAttr = NULL; + Bool_t autoFlag = FALSE; + + /* external attributes for storing aquired channel constellation */ + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* set QAM channel constellation */ + switch ( channel->constellation ) { + case DRX_CONSTELLATION_QAM16 : + case DRX_CONSTELLATION_QAM32 : + case DRX_CONSTELLATION_QAM64 : + case DRX_CONSTELLATION_QAM128 : + case DRX_CONSTELLATION_QAM256 : + extAttr->constellation = channel->constellation; + if (channel->mirror == DRX_MIRROR_AUTO) + { + extAttr->mirror = DRX_MIRROR_NO; + } + else + { + extAttr->mirror = channel->mirror; + } + CHK_ERROR ( SetQAM( demod, channel, tunerFreqOffset, QAM_SET_OP_ALL) ); + + if ( (extAttr->standard == DRX_STANDARD_ITU_B) && + (channel->constellation == DRX_CONSTELLATION_QAM64) ) + { + CHK_ERROR ( QAM64Auto( demod, channel, tunerFreqOffset, &lockStatus)); + } + + if ( (extAttr->standard == DRX_STANDARD_ITU_B) && + (channel->mirror == DRX_MIRROR_AUTO) && + (channel->constellation == DRX_CONSTELLATION_QAM256) ) + { + CHK_ERROR ( QAM256Auto( demod, channel, tunerFreqOffset, &lockStatus)); + } + break; + case DRX_CONSTELLATION_AUTO: /* for channel scan */ + if ( extAttr->standard == DRX_STANDARD_ITU_B ) + { + autoFlag = TRUE; + /* try to lock default QAM constellation: QAM64 */ + channel->constellation = DRX_CONSTELLATION_QAM256; + extAttr->constellation = DRX_CONSTELLATION_QAM256; + if (channel->mirror == DRX_MIRROR_AUTO) + { + extAttr->mirror = DRX_MIRROR_NO; + } + else + { + extAttr->mirror = channel->mirror; + } + CHK_ERROR ( SetQAM( demod, channel, tunerFreqOffset, QAM_SET_OP_ALL ) ); + CHK_ERROR ( QAM256Auto( demod, channel, tunerFreqOffset, &lockStatus )); + + if ( lockStatus < DRX_LOCKED ) + { + /* QAM254 not locked -> try to lock QAM64 constellation */ + channel->constellation = DRX_CONSTELLATION_QAM64; + extAttr->constellation = DRX_CONSTELLATION_QAM64; + if (channel->mirror == DRX_MIRROR_AUTO) + { + extAttr->mirror = DRX_MIRROR_NO; + } + else + { + extAttr->mirror = channel->mirror; + } + { + u16_t qamCtlEna = 0; + RR16( demod->myI2CDevAddr, SCU_RAM_QAM_CTL_ENA__A, &qamCtlEna ); + WR16( demod->myI2CDevAddr, SCU_RAM_QAM_CTL_ENA__A, qamCtlEna & ~SCU_RAM_QAM_CTL_ENA_ACQ__M ); + WR16( demod->myI2CDevAddr, SCU_RAM_QAM_FSM_STATE_TGT__A, 0x2 ); /* force to rate hunting */ + + CHK_ERROR ( SetQAM( demod, channel, tunerFreqOffset, QAM_SET_OP_CONSTELLATION) ); + WR16( demod->myI2CDevAddr, SCU_RAM_QAM_CTL_ENA__A, qamCtlEna ); + } + CHK_ERROR ( QAM64Auto( demod, channel, tunerFreqOffset, &lockStatus )); + } + channel->constellation = DRX_CONSTELLATION_AUTO; + } + else if ( extAttr->standard == DRX_STANDARD_ITU_C ) + { + channel->constellation = DRX_CONSTELLATION_QAM64; + extAttr->constellation = DRX_CONSTELLATION_QAM64; + autoFlag = TRUE; + + if (channel->mirror == DRX_MIRROR_AUTO) + { + extAttr->mirror = DRX_MIRROR_NO; + } + else + { + extAttr->mirror = channel->mirror; + } + { + u16_t qamCtlEna = 0; + RR16( demod->myI2CDevAddr, SCU_RAM_QAM_CTL_ENA__A, &qamCtlEna ); + WR16( demod->myI2CDevAddr, SCU_RAM_QAM_CTL_ENA__A, qamCtlEna & ~SCU_RAM_QAM_CTL_ENA_ACQ__M ); + WR16( demod->myI2CDevAddr, SCU_RAM_QAM_FSM_STATE_TGT__A, 0x2 ); /* force to rate hunting */ + + CHK_ERROR ( SetQAM( demod, channel, tunerFreqOffset, QAM_SET_OP_CONSTELLATION) ); + WR16( demod->myI2CDevAddr, SCU_RAM_QAM_CTL_ENA__A, qamCtlEna ); + } + CHK_ERROR ( QAM64Auto( demod, channel, tunerFreqOffset, &lockStatus )); + channel->constellation = DRX_CONSTELLATION_AUTO; + } + else + { + channel->constellation = DRX_CONSTELLATION_AUTO; + return (DRX_STS_INVALID_ARG); + } + break; + default: + return (DRX_STS_INVALID_ARG); + } + + return (DRX_STS_OK); +rw_error: + /* restore starting value */ + if (autoFlag) + channel->constellation = DRX_CONSTELLATION_AUTO; + return (DRX_STS_ERROR); +} + +/*============================================================================*/ + +/** +* \fn static short GetQAMRSErrCount(pI2CDeviceAddr_t devAddr) +* \brief Get RS error count in QAM mode (used for post RS BER calculation) +* \return Error code +* +* precondition: measurement period & measurement prescale must be set +* +*/ +static DRXStatus_t +GetQAMRSErrCount(pI2CDeviceAddr_t devAddr, pDRXJRSErrors_t RSErrors) +{ + u16_t nrBitErrors = 0, + nrSymbolErrors = 0, + nrPacketErrors = 0, + nrFailures = 0, + nrSncParFailCount = 0; + + /* check arguments */ + if ( devAddr == NULL ) + { + return (DRX_STS_INVALID_ARG); + } + + /* all reported errors are received in the */ + /* most recently finished measurment period */ + /* no of pre RS bit errors */ + RR16( devAddr, FEC_RS_NR_BIT_ERRORS__A, &nrBitErrors ); + /* no of symbol errors */ + RR16( devAddr, FEC_RS_NR_SYMBOL_ERRORS__A, &nrSymbolErrors ); + /* no of packet errors */ + RR16( devAddr, FEC_RS_NR_PACKET_ERRORS__A, &nrPacketErrors ); + /* no of failures to decode */ + RR16( devAddr, FEC_RS_NR_FAILURES__A, &nrFailures ); + /* no of post RS bit erros */ + RR16( devAddr, FEC_OC_SNC_FAIL_COUNT__A, &nrSncParFailCount ); + /* TODO: NOTE */ + /* These register values are fetched in non-atomic fashion */ + /* It is possible that the read values contain unrelated information */ + + RSErrors->nrBitErrors = nrBitErrors & FEC_RS_NR_BIT_ERRORS__M; + RSErrors->nrSymbolErrors = nrSymbolErrors & FEC_RS_NR_SYMBOL_ERRORS__M; + RSErrors->nrPacketErrors = nrPacketErrors & FEC_RS_NR_PACKET_ERRORS__M; + RSErrors->nrFailures = nrFailures & FEC_RS_NR_FAILURES__M; + RSErrors->nrSncParFailCount = nrSncParFailCount & FEC_OC_SNC_FAIL_COUNT__M; + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t CtrlGetQAMSigQuality() +* \brief Retreive QAM signal quality from device. +* \param devmod Pointer to demodulator instance. +* \param sigQuality Pointer to signal quality data. +* \return DRXStatus_t. +* \retval DRX_STS_OK sigQuality contains valid data. +* \retval DRX_STS_INVALID_ARG sigQuality is NULL. +* \retval DRX_STS_ERROR Erroneous data, sigQuality contains invalid data. + +* Pre-condition: Device must be started and in lock. +*/ +static DRXStatus_t +CtrlGetQAMSigQuality( pDRXDemodInstance_t demod, + pDRXSigQuality_t sigQuality ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + DRXConstellation_t constellation = DRX_CONSTELLATION_UNKNOWN; + DRXJRSErrors_t measuredRSErrors = { 0, 0, 0, 0, 0 }; + + u32_t preBitErrRS = 0; /* pre RedSolomon Bit Error Rate */ + u32_t postBitErrRS = 0; /* post RedSolomon Bit Error Rate */ + u32_t pktErrs = 0; /* no of packet errors in RS */ + u16_t qamSlErrPower = 0; /* accumulated error between raw and sliced symbols */ + u16_t qsymErrVD = 0; /* quadrature symbol errors in QAM_VD */ + u16_t fecOcPeriod = 0; /* SNC sync failure measurement period */ + u16_t fecRsPrescale = 0; /* ReedSolomon Measurement Prescale */ + u16_t fecRsPeriod = 0; /* Value for corresponding I2C register */ + /* calculation constants */ + u32_t rsBitCnt = 0; /* RedSolomon Bit Count */ + u32_t qamSlSigPower = 0; /* used for MER, depends of QAM constellation */ + /* intermediate results */ + u32_t e = 0; /* exponent value used for QAM BER/SER */ + u32_t m = 0; /* mantisa value used for QAM BER/SER */ + u32_t berCnt = 0; /* BER count */ + /* signal quality info */ + u32_t qamSlMer = 0; /* QAM MER */ + u32_t qamPreRSBer = 0; /* Pre RedSolomon BER */ + u32_t qamPostRSBer = 0; /* Post RedSolomon BER */ + u32_t qamVDSer = 0; /* ViterbiDecoder SER */ + u16_t qamVdPrescale = 0; /* Viterbi Measurement Prescale */ + u16_t qamVdPeriod = 0; /* Viterbi Measurement period */ + u32_t vdBitCnt = 0; /* ViterbiDecoder Bit Count */ + + /* get device basic information */ + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + constellation = extAttr->constellation; + + /* read the physical registers */ + /* Get the RS error data */ + CHK_ERROR ( GetQAMRSErrCount ( devAddr, &measuredRSErrors ) ); + /* get the register value needed for MER */ + RR16( devAddr, QAM_SL_ERR_POWER__A, &qamSlErrPower ); + /* get the register value needed for post RS BER */ + RR16 ( devAddr, FEC_OC_SNC_FAIL_PERIOD__A, &fecOcPeriod ); + + /* get constants needed for signal quality calculation */ + fecRsPeriod = extAttr->fecRsPeriod; + fecRsPrescale = extAttr->fecRsPrescale; + rsBitCnt = fecRsPeriod * fecRsPrescale * extAttr->fecRsPlen; + qamVdPeriod = extAttr->qamVdPeriod; + qamVdPrescale = extAttr->qamVdPrescale; + vdBitCnt = qamVdPeriod * qamVdPrescale * extAttr->fecVdPlen; + + /* DRXJ_QAM_SL_SIG_POWER_QAMxxx * 4 */ + switch ( constellation ) + { + case DRX_CONSTELLATION_QAM16: + qamSlSigPower = DRXJ_QAM_SL_SIG_POWER_QAM16 << 2; + break; + case DRX_CONSTELLATION_QAM32: + qamSlSigPower = DRXJ_QAM_SL_SIG_POWER_QAM32 << 2; + break; + case DRX_CONSTELLATION_QAM64: + qamSlSigPower = DRXJ_QAM_SL_SIG_POWER_QAM64 << 2; + break; + case DRX_CONSTELLATION_QAM128: + qamSlSigPower = DRXJ_QAM_SL_SIG_POWER_QAM128 << 2; + break; + case DRX_CONSTELLATION_QAM256: + qamSlSigPower = DRXJ_QAM_SL_SIG_POWER_QAM256 << 2; + break; + default: + return (DRX_STS_ERROR); + } + + /* ------------------------------ */ + /* MER Calculation */ + /* ------------------------------ */ + /* MER is good if it is above 27.5 for QAM256 or 21.5 for QAM64 */ + + /* 10.0*log10(qam_sl_sig_power * 4.0 / qam_sl_err_power); */ + if ( qamSlErrPower == 0 ) + qamSlMer = 0; + else + qamSlMer = Log10Times100( qamSlSigPower ) - Log10Times100( ( u32_t ) qamSlErrPower ); + + + /* ----------------------------------------- */ + /* Pre Viterbi Symbol Error Rate Calculation */ + /* ----------------------------------------- */ + /* pre viterbi SER is good if it is bellow 0.025 */ + + /* get the register value */ + /* no of quadrature symbol errors */ + RR16( devAddr, QAM_VD_NR_QSYM_ERRORS__A , &qsymErrVD ); + /* Extract the Exponent and the Mantisa */ + /* of number of quadrature symbol errors */ + e = ( qsymErrVD & QAM_VD_NR_QSYM_ERRORS_EXP__M ) >> + QAM_VD_NR_QSYM_ERRORS_EXP__B; + m = ( qsymErrVD & QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__M ) >> + QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__B; + + if ( (m << e) >> 3 > 549752 ) /* the max of FracTimes1e6 */ + { + qamVDSer = 500000; /* clip BER 0.5 */ + } + else + { + qamVDSer = FracTimes1e6(m << ((e > 2)? (e - 3):e), vdBitCnt * ((e > 2)?1:8) / 8 ); + } + + /* --------------------------------------- */ + /* pre and post RedSolomon BER Calculation */ + /* --------------------------------------- */ + /* pre RS BER is good if it is below 3.5e-4 */ + + /* get the register values */ + preBitErrRS = ( u32_t ) measuredRSErrors.nrBitErrors; + pktErrs = postBitErrRS = ( u32_t ) measuredRSErrors.nrSncParFailCount; + + /* Extract the Exponent and the Mantisa of the */ + /* pre Reed-Solomon bit error count */ + e = ( preBitErrRS & FEC_RS_NR_BIT_ERRORS_EXP__M ) >> + FEC_RS_NR_BIT_ERRORS_EXP__B; + m = ( preBitErrRS & FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M ) >> + FEC_RS_NR_BIT_ERRORS_FIXED_MANT__B; + + berCnt = m << e; + + /*qamPreRSBer = FracTimes1e6( berCnt, rsBitCnt ); */ + if ( m > (rsBitCnt >> (e + 1)) || (rsBitCnt >> e) == 0 ) + { + qamPreRSBer = 500000; /* clip BER 0.5 */ + } + else + { + qamPreRSBer = FracTimes1e6(m, rsBitCnt >> e ); + } + + /* post RS BER = 1000000* (11.17 * FEC_OC_SNC_FAIL_COUNT__A) / */ + /* (1504.0 * FEC_OC_SNC_FAIL_PERIOD__A) */ + /* + => c = (1000000*100*11.17)/1504 = + post RS BER = (( c* FEC_OC_SNC_FAIL_COUNT__A) / + (100 * FEC_OC_SNC_FAIL_PERIOD__A) + *100 and /100 is for more precision. + => (20 bits * 12 bits) /(16 bits * 7 bits) => safe in 32 bits computation + + Precision errors still possible. + */ + e = postBitErrRS * 742686; + m = fecOcPeriod * 100; + if ( fecOcPeriod == 0 ) + qamPostRSBer = 0xFFFFFFFF; + else + qamPostRSBer = e/m; + + /* fill signal quality data structure */ + sigQuality->MER = ( ( u16_t ) qamSlMer ); + if (extAttr->standard == DRX_STANDARD_ITU_B) + { + sigQuality->preViterbiBER = qamVDSer; + } + else + { + sigQuality->preViterbiBER = qamPreRSBer; + } + sigQuality->postViterbiBER = qamPreRSBer; + sigQuality->postReedSolomonBER = qamPostRSBer; + sigQuality->scaleFactorBER = ( ( u32_t ) 1000000 ); +#ifdef DRXJ_SIGNAL_ACCUM_ERR + CHK_ERROR (GetAccPktErr (demod, &sigQuality->packetError)); +#else + sigQuality->packetError = ( ( u16_t ) pktErrs ); +#endif + + return (DRX_STS_OK); + rw_error: + return (DRX_STS_ERROR); +} + +/** +* \fn DRXStatus_t CtrlGetQAMConstel() +* \brief Retreive a QAM constellation point via I2C. +* \param demod Pointer to demodulator instance. +* \param complexNr Pointer to the structure in which to store the + constellation point. +* \return DRXStatus_t. +*/ +static DRXStatus_t +CtrlGetQAMConstel( pDRXDemodInstance_t demod, + pDRXComplex_t complexNr ) +{ + u16_t fecOcOcrMode = 0; /**< FEC OCR grabber configuration */ + u16_t qamSlCommMb = 0; /**< QAM SL MB configuration */ + u16_t qamSlCommMbInit = 0; /**< QAM SL MB intial configuration */ + u16_t im = 0; /**< constellation Im part */ + u16_t re = 0; /**< constellation Re part */ + u32_t data = 0; + pI2CDeviceAddr_t devAddr = NULL; /**< device address */ + + /* read device info */ + devAddr = demod -> myI2CDevAddr; + + /* TODO: */ + /* Monitor bus grabbing is an open external interface issue */ + /* Needs to be checked when external interface PG is updated */ + + /* Configure MB (Monitor bus) */ + RR16( devAddr, QAM_SL_COMM_MB__A, &qamSlCommMbInit ); + /* set observe flag & MB mux */ + qamSlCommMb = qamSlCommMbInit & (~ ( QAM_SL_COMM_MB_OBS__M + + QAM_SL_COMM_MB_MUX_OBS__M ) ); + qamSlCommMb |= ( QAM_SL_COMM_MB_OBS_ON + + QAM_SL_COMM_MB_MUX_OBS_CONST_CORR ); + WR16( devAddr, QAM_SL_COMM_MB__A, qamSlCommMb ); + + /* Enable MB grabber in the FEC OC */ + fecOcOcrMode = ( /* output select: observe bus */ + ( FEC_OC_OCR_MODE_MB_SELECT__M & + ( 0x0 << FEC_OC_OCR_MODE_MB_SELECT__B ) ) | + /* grabber enable: on */ + ( FEC_OC_OCR_MODE_GRAB_ENABLE__M & + ( 0x1 << FEC_OC_OCR_MODE_GRAB_ENABLE__B ) ) | + /* grabber select: observe bus */ + ( FEC_OC_OCR_MODE_GRAB_SELECT__M & + ( 0x0 << FEC_OC_OCR_MODE_GRAB_SELECT__B ) ) | + /* grabber mode: continuous */ + ( FEC_OC_OCR_MODE_GRAB_COUNTED__M & + ( 0x0 << FEC_OC_OCR_MODE_GRAB_COUNTED__B ) ) ); + WR16( devAddr, FEC_OC_OCR_MODE__A, fecOcOcrMode ); + + /* Disable MB grabber in the FEC OC */ + WR16( devAddr, FEC_OC_OCR_MODE__A, 0x00 ); + + /* read data */ + RR32( devAddr, FEC_OC_OCR_GRAB_RD0__A, &data ); + re = (u16_t)(data & FEC_OC_OCR_GRAB_RD0__M); + im = (u16_t)((data >> 16) & FEC_OC_OCR_GRAB_RD1__M); + + /* TODO: */ + /* interpret data (re & im) according to the Monitor bus mapping ?? */ + + /* sign extension, 10th bit is sign bit */ + if ( (re & 0x0200) == 0x0200 ) + { + re |= 0xFC00; + } + if ( (im & 0x0200) == 0x0200 ) + { + im |= 0xFC00; + } + complexNr->re = ( ( s16_t ) re ) ; + complexNr->im = ( ( s16_t ) im ) ; + + /* Restore MB (Monitor bus) */ + WR16( devAddr, QAM_SL_COMM_MB__A, qamSlCommMbInit ); + + return (DRX_STS_OK); + rw_error: + return (DRX_STS_ERROR); +} +#endif /* #ifndef DRXJ_VSB_ONLY */ + +/*============================================================================*/ +/*== END QAM DATAPATH FUNCTIONS ==*/ +/*============================================================================*/ + +/*============================================================================*/ +/*============================================================================*/ +/*== ATV DATAPATH FUNCTIONS ==*/ +/*============================================================================*/ +/*============================================================================*/ + +/* + Implementation notes. + + NTSC/FM AGCs + + Four AGCs are used for NTSC: + (1) RF (used to attenuate the input signal in case of to much power) + (2) IF (used to attenuate the input signal in case of to much power) + (3) Video AGC (used to amplify the output signal in case input to low) + (4) SIF AGC (used to amplify the output signal in case input to low) + + Video AGC is coupled to RF and IF. SIF AGC is not coupled. It is assumed + that the coupling between Video AGC and the RF and IF AGCs also works in + favor of the SIF AGC. + + Three AGCs are used for FM: + (1) RF (used to attenuate the input signal in case of to much power) + (2) IF (used to attenuate the input signal in case of to much power) + (3) SIF AGC (used to amplify the output signal in case input to low) + + The SIF AGC is now coupled to the RF/IF AGCs. + The SIF AGC is needed for both SIF ouput and the internal SIF signal to + the AUD block. + + RF and IF AGCs DACs are part of AFE, Video and SIF AGC DACs are part of + the ATV block. The AGC control algorithms are all implemented in + microcode. + + ATV SETTINGS + + (Shadow settings will not be used for now, they will be implemented + later on because of the schedule) + + Several HW/SCU "settings" can be used for ATV. The standard selection + will reset most of these settings. To avoid that the end user apllication + has to perform these settings each time the ATV or FM standards is + selected the driver will shadow these settings. This enables the end user + to perform the settings only once after a DRX_Open(). The driver must + write the shadow settings to HW/SCU incase: + ( setstandard FM/ATV) || + ( settings have changed && FM/ATV standard is active) + The shadow settings will be stored in the device specific data container. + A set of flags will be defined to flag changes in shadow settings. + A routine will be implemented to write all changed shadow settings to + HW/SCU. + + The "settings" will consist of: AGC settings, filter settings etc. + + Disadvantage of use of shadow settings: + Direct changes in HW/SCU registers will not be reflected in the + shadow settings and these changes will be overwritten during a next + update. This can happen during evaluation. This will not be a problem + for normal customer usage. +*/ +/* -------------------------------------------------------------------------- */ + +/** +* \brief Get array index for atv coef (extAttr->atvTopCoefX[index]) +* \param standard +* \param pointer to index +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AtvEquCoefIndex( DRXStandard_t standard, int *index) +{ + switch(standard) + { + case DRX_STANDARD_PAL_SECAM_BG: + *index=(int)DRXJ_COEF_IDX_BG; + break; + case DRX_STANDARD_PAL_SECAM_DK: + *index=(int)DRXJ_COEF_IDX_DK; + break; + case DRX_STANDARD_PAL_SECAM_I: + *index=(int)DRXJ_COEF_IDX_I; + break; + case DRX_STANDARD_PAL_SECAM_L: + *index=(int)DRXJ_COEF_IDX_L; + break; + case DRX_STANDARD_PAL_SECAM_LP: + *index=(int)DRXJ_COEF_IDX_LP; + break; + case DRX_STANDARD_NTSC: + *index=(int)DRXJ_COEF_IDX_MN; + break; + case DRX_STANDARD_FM: + *index=(int)DRXJ_COEF_IDX_FM; + break; + default: + *index=(int)DRXJ_COEF_IDX_MN; /* still return a valid index */ + return DRX_STS_ERROR; + break; + } + + return DRX_STS_OK; +} + +/* -------------------------------------------------------------------------- */ +/** +* \fn DRXStatus_t AtvUpdateConfig () +* \brief Flush changes in ATV shadow registers to physical registers. +* \param demod instance of demodulator +* \param forceUpdate don't look at standard or change flags, flush all. +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AtvUpdateConfig( pDRXDemodInstance_t demod, + Bool_t forceUpdate ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* equalizer coefficients */ + if ( forceUpdate || + ((extAttr->atvCfgChangedFlags & DRXJ_ATV_CHANGED_COEF) != 0) ) + { + int index=0; + + CHK_ERROR(AtvEquCoefIndex( extAttr->standard, &index )); + WR16( devAddr, ATV_TOP_EQU0__A, extAttr->atvTopEqu0[index] ); + WR16( devAddr, ATV_TOP_EQU1__A, extAttr->atvTopEqu1[index] ); + WR16( devAddr, ATV_TOP_EQU2__A, extAttr->atvTopEqu2[index] ); + WR16( devAddr, ATV_TOP_EQU3__A, extAttr->atvTopEqu3[index] ); + } + + /* bypass fast carrier recovery */ + if ( forceUpdate ) + { + u16_t data=0; + + RR16( devAddr, IQM_RT_ROT_BP__A, &data ); + data &= (~((u16_t)IQM_RT_ROT_BP_ROT_OFF__M)); + if (extAttr->phaseCorrectionBypass) + { + data |= IQM_RT_ROT_BP_ROT_OFF_OFF; + } else { + data |= IQM_RT_ROT_BP_ROT_OFF_ACTIVE; + } + WR16( devAddr, IQM_RT_ROT_BP__A, data ); + } + + /* peak filter setting */ + if ( forceUpdate || + ((extAttr->atvCfgChangedFlags & DRXJ_ATV_CHANGED_PEAK_FLT) != 0) ) + { + WR16( devAddr, ATV_TOP_VID_PEAK__A, extAttr->atvTopVidPeak ); + } + + /* noise filter setting */ + if ( forceUpdate || + ((extAttr->atvCfgChangedFlags & DRXJ_ATV_CHANGED_NOISE_FLT) != 0) ) + { + WR16( devAddr, ATV_TOP_NOISE_TH__A, extAttr->atvTopNoiseTh ); + } + + /* SIF attenuation */ + if ( forceUpdate || + ((extAttr->atvCfgChangedFlags & DRXJ_ATV_CHANGED_SIF_ATT) != 0) ) + { + u16_t attenuation=0; + + switch( extAttr->sifAttenuation ){ + case DRXJ_SIF_ATTENUATION_0DB: + attenuation = ATV_TOP_AF_SIF_ATT_0DB; + break; + case DRXJ_SIF_ATTENUATION_3DB: + attenuation = ATV_TOP_AF_SIF_ATT_M3DB; + break; + case DRXJ_SIF_ATTENUATION_6DB: + attenuation = ATV_TOP_AF_SIF_ATT_M6DB; + break; + case DRXJ_SIF_ATTENUATION_9DB: + attenuation = ATV_TOP_AF_SIF_ATT_M9DB; + break; + default: + return DRX_STS_ERROR; + break; + } + WR16( devAddr, ATV_TOP_AF_SIF_ATT__A, attenuation ); + } + + /* SIF & CVBS enable */ + if ( forceUpdate || + ((extAttr->atvCfgChangedFlags & DRXJ_ATV_CHANGED_OUTPUT) != 0) ) + { + u16_t data = 0; + + RR16( devAddr, ATV_TOP_STDBY__A, &data ); + if ( extAttr->enableCVBSOutput ) + { + data |=ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE; + } else { + data &= (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE); + } + + if ( extAttr->enableSIFOutput ) + { + data &= (~ATV_TOP_STDBY_SIF_STDBY_STANDBY); + } else { + data |= ATV_TOP_STDBY_SIF_STDBY_STANDBY; + } + WR16( devAddr, ATV_TOP_STDBY__A, data ); + } + + extAttr->atvCfgChangedFlags = 0; + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/* -------------------------------------------------------------------------- */ +/** +* \fn DRXStatus_t CtrlSetCfgATVOutput() +* \brief Configure ATV ouputs +* \param demod instance of demodulator +* \param outputCfg output configuaration +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +CtrlSetCfgATVOutput( pDRXDemodInstance_t demod, + pDRXJCfgAtvOutput_t outputCfg ) +{ + pDRXJData_t extAttr = NULL; + + /* Check arguments */ + if ( outputCfg == NULL ) + { + return (DRX_STS_INVALID_ARG); + } + + extAttr = (pDRXJData_t)demod->myExtAttr; + if ( outputCfg->enableSIFOutput ) + { + switch( outputCfg->sifAttenuation ){ + case DRXJ_SIF_ATTENUATION_0DB: /* fallthrough */ + case DRXJ_SIF_ATTENUATION_3DB: /* fallthrough */ + case DRXJ_SIF_ATTENUATION_6DB: /* fallthrough */ + case DRXJ_SIF_ATTENUATION_9DB: + /* Do nothing */ + break; + default: + return DRX_STS_INVALID_ARG; + break; + } + + if(extAttr->sifAttenuation != outputCfg->sifAttenuation ) + { + extAttr->sifAttenuation = outputCfg->sifAttenuation; + extAttr->atvCfgChangedFlags |= DRXJ_ATV_CHANGED_SIF_ATT; + } + } + + if ( extAttr->enableCVBSOutput != outputCfg->enableCVBSOutput ) + { + extAttr->enableCVBSOutput = outputCfg->enableCVBSOutput; + extAttr->atvCfgChangedFlags |= DRXJ_ATV_CHANGED_OUTPUT; + } + + if ( extAttr->enableSIFOutput != outputCfg->enableSIFOutput ) + { + extAttr->enableSIFOutput = outputCfg->enableSIFOutput; + extAttr->atvCfgChangedFlags |= DRXJ_ATV_CHANGED_OUTPUT; + } + + CHK_ERROR( AtvUpdateConfig(demod, FALSE) ); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/* -------------------------------------------------------------------------- */ +#ifndef DRXJ_DIGITAL_ONLY +/** +* \fn DRXStatus_t CtrlSetCfgAtvEquCoef() +* \brief Set ATV equalizer coefficients +* \param demod instance of demodulator +* \param coef the equalizer coefficients +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +CtrlSetCfgAtvEquCoef( pDRXDemodInstance_t demod , + pDRXJCfgAtvEquCoef_t coef) +{ + pDRXJData_t extAttr = NULL; + int index; + + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* current standard needs to be an ATV standard */ + if (!DRXJ_ISATVSTD(extAttr->standard )) + { + return DRX_STS_ERROR; + } + + /* Check arguments */ + if ( ( coef == NULL ) || + ( coef->coef0 > (ATV_TOP_EQU0_EQU_C0__M / 2) ) || + ( coef->coef1 > (ATV_TOP_EQU1_EQU_C1__M / 2) ) || + ( coef->coef2 > (ATV_TOP_EQU2_EQU_C2__M / 2) ) || + ( coef->coef3 > (ATV_TOP_EQU3_EQU_C3__M / 2) ) || + ( coef->coef0 < ((s16_t)~(ATV_TOP_EQU0_EQU_C0__M >> 1)) ) || + ( coef->coef1 < ((s16_t)~(ATV_TOP_EQU1_EQU_C1__M >> 1)) ) || + ( coef->coef2 < ((s16_t)~(ATV_TOP_EQU2_EQU_C2__M >> 1)) ) || + ( coef->coef3 < ((s16_t)~(ATV_TOP_EQU3_EQU_C3__M >> 1)) ) ) + { + return (DRX_STS_INVALID_ARG); + } + + CHK_ERROR(AtvEquCoefIndex( extAttr->standard, &index )); + extAttr->atvTopEqu0[index] = coef->coef0; + extAttr->atvTopEqu1[index] = coef->coef1; + extAttr->atvTopEqu2[index] = coef->coef2; + extAttr->atvTopEqu3[index] = coef->coef3; + extAttr->atvCfgChangedFlags |= DRXJ_ATV_CHANGED_COEF; + + CHK_ERROR( AtvUpdateConfig(demod, FALSE) ); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/* -------------------------------------------------------------------------- */ +/** +* \fn DRXStatus_t CtrlGetCfgAtvEquCoef() +* \brief Get ATV equ coef settings +* \param demod instance of demodulator +* \param coef The ATV equ coefficients +* \return DRXStatus_t. +* +* The values are read from the shadow registers maintained by the drxdriver +* If registers are manipulated outside of the drxdriver scope the reported +* settings will not reflect these changes because of the use of shadow +* regitsers. +* +*/ +static DRXStatus_t +CtrlGetCfgAtvEquCoef( pDRXDemodInstance_t demod , + pDRXJCfgAtvEquCoef_t coef) +{ + pDRXJData_t extAttr = NULL; + int index=0; + + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* current standard needs to be an ATV standard */ + if (!DRXJ_ISATVSTD(extAttr->standard )) + { + return DRX_STS_ERROR; + } + + /* Check arguments */ + if ( coef == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + CHK_ERROR(AtvEquCoefIndex( extAttr->standard, &index )); + coef->coef0 = extAttr->atvTopEqu0[index]; + coef->coef1 = extAttr->atvTopEqu1[index]; + coef->coef2 = extAttr->atvTopEqu2[index]; + coef->coef3 = extAttr->atvTopEqu3[index]; + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/* -------------------------------------------------------------------------- */ +/** +* \fn DRXStatus_t CtrlSetCfgAtvMisc() +* \brief Set misc. settings for ATV. +* \param demod instance of demodulator +* \param +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +CtrlSetCfgAtvMisc( pDRXDemodInstance_t demod , + pDRXJCfgAtvMisc_t settings ) +{ + pDRXJData_t extAttr = NULL; + + /* Check arguments */ + if ( ( settings == NULL ) || + ((settings->peakFilter) < (s16_t)(-8) ) || + ((settings->peakFilter) > (s16_t)(15) ) || + ((settings->noiseFilter) > 15 ) ) + { + return (DRX_STS_INVALID_ARG); + } /* if */ + + extAttr = (pDRXJData_t)demod->myExtAttr; + + if ( settings->peakFilter != extAttr->atvTopVidPeak ) + { + extAttr->atvTopVidPeak = settings->peakFilter; + extAttr->atvCfgChangedFlags |= DRXJ_ATV_CHANGED_PEAK_FLT; + } + + if ( settings->noiseFilter != extAttr->atvTopNoiseTh ) + { + extAttr->atvTopNoiseTh = settings->noiseFilter; + extAttr->atvCfgChangedFlags |= DRXJ_ATV_CHANGED_NOISE_FLT; + } + + CHK_ERROR( AtvUpdateConfig(demod, FALSE) ); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/* -------------------------------------------------------------------------- */ +/** +* \fn DRXStatus_t CtrlGetCfgAtvMisc() +* \brief Get misc settings of ATV. +* \param demod instance of demodulator +* \param settings misc. ATV settings +* \return DRXStatus_t. +* +* The values are read from the shadow registers maintained by the drxdriver +* If registers are manipulated outside of the drxdriver scope the reported +* settings will not reflect these changes because of the use of shadow +* regitsers. +*/ +static DRXStatus_t +CtrlGetCfgAtvMisc( pDRXDemodInstance_t demod , + pDRXJCfgAtvMisc_t settings ) +{ + pDRXJData_t extAttr = NULL; + + /* Check arguments */ + if ( settings == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + extAttr = (pDRXJData_t)demod->myExtAttr; + + settings->peakFilter = extAttr->atvTopVidPeak ; + settings->noiseFilter = extAttr->atvTopNoiseTh ; + + return (DRX_STS_OK); +} + +/* -------------------------------------------------------------------------- */ + +/* -------------------------------------------------------------------------- */ +/** +* \fn DRXStatus_t CtrlGetCfgAtvOutput() +* \brief +* \param demod instance of demodulator +* \param outputCfg output configuaration +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +CtrlGetCfgAtvOutput( pDRXDemodInstance_t demod , + pDRXJCfgAtvOutput_t outputCfg ) +{ + u16_t data = 0; + + /* Check arguments */ + if ( outputCfg == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + RR16( demod->myI2CDevAddr, ATV_TOP_STDBY__A, &data ); + if ( data & ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE ) + { + outputCfg->enableCVBSOutput = TRUE; + } else { + outputCfg->enableCVBSOutput = FALSE; + } + + if ( data & ATV_TOP_STDBY_SIF_STDBY_STANDBY ) + { + outputCfg->enableSIFOutput = FALSE; + } else { + outputCfg->enableSIFOutput = TRUE; + RR16( demod->myI2CDevAddr, ATV_TOP_AF_SIF_ATT__A, &data ); + outputCfg->sifAttenuation = (DRXJSIFAttenuation_t) data; + } + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/* -------------------------------------------------------------------------- */ +/** +* \fn DRXStatus_t CtrlGetCfgAtvAgcStatus() +* \brief +* \param demod instance of demodulator +* \param agcStatus agc status +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +CtrlGetCfgAtvAgcStatus( pDRXDemodInstance_t demod , + pDRXJCfgAtvAgcStatus_t agcStatus ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + u16_t data = 0; + u32_t tmp = 0; + + /* Check arguments */ + if ( agcStatus == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* + RFgain = (IQM_AF_AGC_RF__A * 26.75)/1000 (uA) + = ((IQM_AF_AGC_RF__A * 27) - (0.25*IQM_AF_AGC_RF__A))/1000 + + IQM_AF_AGC_RF__A * 27 is 20 bits worst case. + */ + RR16( devAddr, IQM_AF_AGC_RF__A, &data ); + tmp = ((u32_t)data) * 27 - ((u32_t)(data>>2)); /* nA */ + agcStatus->rfAgcGain = (u16_t)(tmp/1000) ; /* uA */ + /* rounding */ + if ( tmp%1000 >= 500 ) + { + (agcStatus->rfAgcGain)++; + } + + /* + IFgain = (IQM_AF_AGC_IF__A * 26.75)/1000 (uA) + = ((IQM_AF_AGC_IF__A * 27) - (0.25*IQM_AF_AGC_IF__A))/1000 + + IQM_AF_AGC_IF__A * 27 is 20 bits worst case. + */ + RR16( devAddr, IQM_AF_AGC_IF__A, &data ); + tmp = ((u32_t)data) * 27 - ((u32_t)(data>>2)); /* nA */ + agcStatus->ifAgcGain = (u16_t)(tmp/1000) ; /* uA */ + /* rounding */ + if ( tmp%1000 >= 500 ) + { + (agcStatus->ifAgcGain)++; + } + + /* + videoGain = (ATV_TOP_SFR_VID_GAIN__A/16 -150)* 0.05 (dB) + = (ATV_TOP_SFR_VID_GAIN__A/16 -150)/20 (dB) + = 10*(ATV_TOP_SFR_VID_GAIN__A/16 -150)/20 (in 0.1 dB) + = (ATV_TOP_SFR_VID_GAIN__A/16 -150)/2 (in 0.1 dB) + = (ATV_TOP_SFR_VID_GAIN__A/32) - 75 (in 0.1 dB) + */ + + SARR16( devAddr, SCU_RAM_ATV_VID_GAIN_HI__A , &data ); + /* dividing by 32 inclusive rounding */ + data >>=4; + if ((data & 1) !=0 ) + { + data++; + } + data >>= 1; + agcStatus->videoAgcGain = ((s16_t)data)-75; /* 0.1 dB */ + + /* + audioGain = (SCU_RAM_ATV_SIF_GAIN__A -8)* 0.05 (dB) + = (SCU_RAM_ATV_SIF_GAIN__A -8)/20 (dB) + = 10*(SCU_RAM_ATV_SIF_GAIN__A -8)/20 (in 0.1 dB) + = (SCU_RAM_ATV_SIF_GAIN__A -8)/2 (in 0.1 dB) + = (SCU_RAM_ATV_SIF_GAIN__A/2) - 4 (in 0.1 dB) + */ + + SARR16( devAddr, SCU_RAM_ATV_SIF_GAIN__A, &data ); + data &= SCU_RAM_ATV_SIF_GAIN__M; + /* dividing by 2 inclusive rounding */ + if ((data & 1) !=0 ) + { + data++; + } + data >>= 1; + agcStatus->audioAgcGain = ((s16_t)data)-4; /* 0.1 dB */ + + /* Loop gain's */ + SARR16( devAddr, SCU_RAM_AGC_KI__A, &data ); + agcStatus->videoAgcLoopGain = + ( (data & SCU_RAM_AGC_KI_DGAIN__M)>>SCU_RAM_AGC_KI_DGAIN__B) ; + agcStatus->rfAgcLoopGain = + ( (data & SCU_RAM_AGC_KI_RF__M)>>SCU_RAM_AGC_KI_RF__B) ; + agcStatus->ifAgcLoopGain = + ( (data & SCU_RAM_AGC_KI_IF__M)>>SCU_RAM_AGC_KI_IF__B) ; + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/* -------------------------------------------------------------------------- */ + +/** +* \fn DRXStatus_t PowerUpATV () +* \brief Power up ATV. +* \param demod instance of demodulator +* \param standard either NTSC or FM (sub strandard for ATV ) +* \return DRXStatus_t. +* +* * Starts ATV and IQM +* * AUdio already started during standard init for ATV. +*/ +static DRXStatus_t +PowerUpATV( pDRXDemodInstance_t demod , DRXStandard_t standard ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* ATV NTSC */ + WR16( devAddr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_ACTIVE ); + /* turn on IQM_AF */ + CHK_ERROR( SetIqmAf( demod, TRUE ) ); + CHK_ERROR(ADCSynchronization (demod)); + + WR16( devAddr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE ); + + /* Audio, already done during set standard */ + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} +#endif /* #ifndef DRXJ_DIGITAL_ONLY */ + +/* -------------------------------------------------------------------------- */ + +/** +* \fn DRXStatus_t PowerDownATV () +* \brief Power down ATV. +* \param demod instance of demodulator +* \param standard either NTSC or FM (sub strandard for ATV ) +* \return DRXStatus_t. +* +* Stops and thus resets ATV and IQM block +* SIF and CVBS ADC are powered down +* Calls audio power down +*/ +static DRXStatus_t +PowerDownATV( pDRXDemodInstance_t demod , DRXStandard_t standard, Bool_t primary ) +{ + pI2CDeviceAddr_t devAddr = NULL; + DRXJSCUCmd_t cmdSCU = { /* command */ 0, + /* parameterLen */ 0, + /* resultLen */ 0, + /* *parameter */ NULL, + /* *result */ NULL }; + u16_t cmdResult = 0; + pDRXJData_t extAttr = NULL; + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; + /* ATV NTSC */ + + /* Stop ATV SCU (will reset ATV and IQM hardware */ + cmdSCU.command = SCU_RAM_COMMAND_STANDARD_ATV | + SCU_RAM_COMMAND_CMD_DEMOD_STOP; + cmdSCU.parameterLen = 0; + cmdSCU.resultLen = 1; + cmdSCU.parameter = NULL; + cmdSCU.result = &cmdResult; + CHK_ERROR( SCUCommand( devAddr, &cmdSCU ) ); + /* Disable ATV outputs (ATV reset enables CVBS, undo this) */ + WR16 ( devAddr, ATV_TOP_STDBY__A, ( ATV_TOP_STDBY_SIF_STDBY_STANDBY & + (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE) ) ); + + WR16( devAddr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_STOP); + if (primary == TRUE) + { + WR16( devAddr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP ); + CHK_ERROR( SetIqmAf( demod, FALSE ) ); + } + else + { + WR16( devAddr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP ); + WR16( devAddr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP ); + WR16( devAddr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP ); + WR16( devAddr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP ); + WR16( devAddr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP ); + } + CHK_ERROR( PowerDownAud(demod) ); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/* -------------------------------------------------------------------------- */ +/** +* \fn DRXStatus_t SetATVStandard () +* \brief Set up ATV demodulator. +* \param demod instance of demodulator +* \param standard either NTSC or FM (sub strandard for ATV ) +* \return DRXStatus_t. +* +* Init all channel independent registers. +* Assuming that IQM, ATV and AUD blocks have been reset and are in STOP mode +* +*/ +#ifndef DRXJ_DIGITAL_ONLY +#define SCU_RAM_ATV_ENABLE_IIR_WA__A 0x831F6D /* TODO remove after done with reg import */ +static DRXStatus_t +SetATVStandard( pDRXDemodInstance_t demod , pDRXStandard_t standard ) +{ +/* TODO: enable alternative for tap settings via external file + +something like: +#ifdef DRXJ_ATV_COEF_FILE +#include DRXJ_ATV_COEF_FILE +#else +... code defining fixed coef's ... +#endif + +Cutsomer must create file "customer_coefs.c.inc" containing +modified copy off the constants below, and define the compiler +switch DRXJ_ATV_COEF_FILE="customer_coefs.c.inc". + +Still to check if this will work; DRXJ_16TO8 macro may cause +trouble ? +*/ + const u8_t ntsc_taps_re[]= { + DRXJ_16TO8(-12 ), /* re0 */ + DRXJ_16TO8(-9 ), /* re1 */ + DRXJ_16TO8( 9 ), /* re2 */ + DRXJ_16TO8( 19 ), /* re3 */ + DRXJ_16TO8(-4 ), /* re4 */ + DRXJ_16TO8(-24 ), /* re5 */ + DRXJ_16TO8(-6 ), /* re6 */ + DRXJ_16TO8( 16 ), /* re7 */ + DRXJ_16TO8( 6 ), /* re8 */ + DRXJ_16TO8(-16 ), /* re9 */ + DRXJ_16TO8(-5 ), /* re10 */ + DRXJ_16TO8( 13 ), /* re11 */ + DRXJ_16TO8(-2 ), /* re12 */ + DRXJ_16TO8(-20 ), /* re13 */ + DRXJ_16TO8( 4 ), /* re14 */ + DRXJ_16TO8( 25 ), /* re15 */ + DRXJ_16TO8(-6 ), /* re16 */ + DRXJ_16TO8(-36 ), /* re17 */ + DRXJ_16TO8( 2 ), /* re18 */ + DRXJ_16TO8( 38 ), /* re19 */ + DRXJ_16TO8(-10 ), /* re20 */ + DRXJ_16TO8(-48 ), /* re21 */ + DRXJ_16TO8( 35 ), /* re22 */ + DRXJ_16TO8( 94 ), /* re23 */ + DRXJ_16TO8(-59 ), /* re24 */ + DRXJ_16TO8(-217 ), /* re25 */ + DRXJ_16TO8( 50 ), /* re26 */ + DRXJ_16TO8( 679 ) /* re27 */ + }; + const u8_t ntsc_taps_im[]= { + DRXJ_16TO8( 11 ), /* im0 */ + DRXJ_16TO8( 1 ), /* im1 */ + DRXJ_16TO8(-10 ), /* im2 */ + DRXJ_16TO8( 2 ), /* im3 */ + DRXJ_16TO8( 24 ), /* im4 */ + DRXJ_16TO8( 21 ), /* im5 */ + DRXJ_16TO8( 1 ), /* im6 */ + DRXJ_16TO8(-4 ), /* im7 */ + DRXJ_16TO8( 7 ), /* im8 */ + DRXJ_16TO8( 14 ), /* im9 */ + DRXJ_16TO8( 27 ), /* im10 */ + DRXJ_16TO8( 42 ), /* im11 */ + DRXJ_16TO8( 22 ), /* im12 */ + DRXJ_16TO8(-20 ), /* im13 */ + DRXJ_16TO8( 2 ), /* im14 */ + DRXJ_16TO8( 98 ), /* im15 */ + DRXJ_16TO8( 122 ), /* im16 */ + DRXJ_16TO8( 0 ), /* im17 */ + DRXJ_16TO8(-85 ), /* im18 */ + DRXJ_16TO8( 51 ), /* im19 */ + DRXJ_16TO8( 247 ), /* im20 */ + DRXJ_16TO8( 192 ), /* im21 */ + DRXJ_16TO8(-55 ), /* im22 */ + DRXJ_16TO8(-95 ), /* im23 */ + DRXJ_16TO8( 217 ), /* im24 */ + DRXJ_16TO8( 544 ), /* im25 */ + DRXJ_16TO8( 553 ), /* im26 */ + DRXJ_16TO8( 302 ) /* im27 */ + }; + const u8_t bg_taps_re[]= { + DRXJ_16TO8(-18 ), /* re0 */ + DRXJ_16TO8( 18 ), /* re1 */ + DRXJ_16TO8( 19 ), /* re2 */ + DRXJ_16TO8(-26 ), /* re3 */ + DRXJ_16TO8(-20 ), /* re4 */ + DRXJ_16TO8( 36 ), /* re5 */ + DRXJ_16TO8( 5 ), /* re6 */ + DRXJ_16TO8(-51 ), /* re7 */ + DRXJ_16TO8( 15 ), /* re8 */ + DRXJ_16TO8( 45 ), /* re9 */ + DRXJ_16TO8(-46 ), /* re10 */ + DRXJ_16TO8(-24 ), /* re11 */ + DRXJ_16TO8( 71 ), /* re12 */ + DRXJ_16TO8(-17 ), /* re13 */ + DRXJ_16TO8(-83 ), /* re14 */ + DRXJ_16TO8( 74 ), /* re15 */ + DRXJ_16TO8( 75 ), /* re16 */ + DRXJ_16TO8(-134 ), /* re17 */ + DRXJ_16TO8(-40 ), /* re18 */ + DRXJ_16TO8( 191 ), /* re19 */ + DRXJ_16TO8(-11 ), /* re20 */ + DRXJ_16TO8(-233 ), /* re21 */ + DRXJ_16TO8( 74 ), /* re22 */ + DRXJ_16TO8( 271 ), /* re23 */ + DRXJ_16TO8(-132 ), /* re24 */ + DRXJ_16TO8(-341 ), /* re25 */ + DRXJ_16TO8( 172 ), /* re26 */ + DRXJ_16TO8( 801 ) /* re27 */ + }; + const u8_t bg_taps_im[]= { + DRXJ_16TO8(-24 ), /* im0 */ + DRXJ_16TO8(-10 ), /* im1 */ + DRXJ_16TO8( 9 ), /* im2 */ + DRXJ_16TO8(-5 ), /* im3 */ + DRXJ_16TO8(-51 ), /* im4 */ + DRXJ_16TO8(-17 ), /* im5 */ + DRXJ_16TO8( 31 ), /* im6 */ + DRXJ_16TO8(-48 ), /* im7 */ + DRXJ_16TO8(-95 ), /* im8 */ + DRXJ_16TO8( 25 ), /* im9 */ + DRXJ_16TO8( 37 ), /* im10 */ + DRXJ_16TO8(-123 ), /* im11 */ + DRXJ_16TO8(-77 ), /* im12 */ + DRXJ_16TO8( 94 ), /* im13 */ + DRXJ_16TO8(-10 ), /* im14 */ + DRXJ_16TO8(-149 ), /* im15 */ + DRXJ_16TO8( 10 ), /* im16 */ + DRXJ_16TO8( 108 ), /* im17 */ + DRXJ_16TO8(-49 ), /* im18 */ + DRXJ_16TO8(-59 ), /* im19 */ + DRXJ_16TO8( 90 ), /* im20 */ + DRXJ_16TO8( 73 ), /* im21 */ + DRXJ_16TO8( 55 ), /* im22 */ + DRXJ_16TO8( 148 ), /* im23 */ + DRXJ_16TO8( 86 ), /* im24 */ + DRXJ_16TO8( 146 ), /* im25 */ + DRXJ_16TO8( 687 ), /* im26 */ + DRXJ_16TO8( 877 ) /* im27 */ + }; + const u8_t dk_i_l_lp_taps_re[]= { + DRXJ_16TO8(-23 ), /* re0 */ + DRXJ_16TO8( 9 ), /* re1 */ + DRXJ_16TO8( 16 ), /* re2 */ + DRXJ_16TO8(-26 ), /* re3 */ + DRXJ_16TO8(-3 ), /* re4 */ + DRXJ_16TO8( 13 ), /* re5 */ + DRXJ_16TO8(-19 ), /* re6 */ + DRXJ_16TO8(-3 ), /* re7 */ + DRXJ_16TO8( 13 ), /* re8 */ + DRXJ_16TO8(-26 ), /* re9 */ + DRXJ_16TO8(-4 ), /* re10 */ + DRXJ_16TO8( 28 ), /* re11 */ + DRXJ_16TO8(-15 ), /* re12 */ + DRXJ_16TO8(-14 ), /* re13 */ + DRXJ_16TO8( 10 ), /* re14 */ + DRXJ_16TO8( 1 ), /* re15 */ + DRXJ_16TO8( 39 ), /* re16 */ + DRXJ_16TO8(-18 ), /* re17 */ + DRXJ_16TO8(-90 ), /* re18 */ + DRXJ_16TO8( 109 ), /* re19 */ + DRXJ_16TO8( 113 ), /* re20 */ + DRXJ_16TO8(-235 ), /* re21 */ + DRXJ_16TO8(-49 ), /* re22 */ + DRXJ_16TO8( 359 ), /* re23 */ + DRXJ_16TO8(-79 ), /* re24 */ + DRXJ_16TO8(-459 ), /* re25 */ + DRXJ_16TO8( 206 ), /* re26 */ + DRXJ_16TO8( 894 ) /* re27 */ + }; + const u8_t dk_i_l_lp_taps_im[]= { + DRXJ_16TO8(-8 ), /* im0 */ + DRXJ_16TO8(-20 ), /* im1 */ + DRXJ_16TO8( 17 ), /* im2 */ + DRXJ_16TO8(-14 ), /* im3 */ + DRXJ_16TO8(-52 ), /* im4 */ + DRXJ_16TO8( 4 ), /* im5 */ + DRXJ_16TO8( 9 ), /* im6 */ + DRXJ_16TO8(-62 ), /* im7 */ + DRXJ_16TO8(-47 ), /* im8 */ + DRXJ_16TO8( 0 ), /* im9 */ + DRXJ_16TO8(-20 ), /* im10 */ + DRXJ_16TO8(-48 ), /* im11 */ + DRXJ_16TO8(-65 ), /* im12 */ + DRXJ_16TO8(-23 ), /* im13 */ + DRXJ_16TO8( 44 ), /* im14 */ + DRXJ_16TO8(-60 ), /* im15 */ + DRXJ_16TO8(-113 ), /* im16 */ + DRXJ_16TO8( 92 ), /* im17 */ + DRXJ_16TO8( 81 ), /* im18 */ + DRXJ_16TO8(-125 ), /* im19 */ + DRXJ_16TO8( 28 ), /* im20 */ + DRXJ_16TO8( 182 ), /* im21 */ + DRXJ_16TO8( 35 ), /* im22 */ + DRXJ_16TO8( 94 ), /* im23 */ + DRXJ_16TO8( 180 ), /* im24 */ + DRXJ_16TO8( 134 ), /* im25 */ + DRXJ_16TO8( 657 ), /* im26 */ + DRXJ_16TO8( 1023 ) /* im27 */ + }; + const u8_t fm_taps_re[]= { + DRXJ_16TO8( 0 ), /* re0 */ + DRXJ_16TO8( 0 ), /* re1 */ + DRXJ_16TO8( 0 ), /* re2 */ + DRXJ_16TO8( 0 ), /* re3 */ + DRXJ_16TO8( 0 ), /* re4 */ + DRXJ_16TO8( 0 ), /* re5 */ + DRXJ_16TO8( 0 ), /* re6 */ + DRXJ_16TO8( 0 ), /* re7 */ + DRXJ_16TO8( 0 ), /* re8 */ + DRXJ_16TO8( 0 ), /* re9 */ + DRXJ_16TO8( 0 ), /* re10 */ + DRXJ_16TO8( 0 ), /* re11 */ + DRXJ_16TO8( 0 ), /* re12 */ + DRXJ_16TO8( 0 ), /* re13 */ + DRXJ_16TO8( 0 ), /* re14 */ + DRXJ_16TO8( 0 ), /* re15 */ + DRXJ_16TO8( 0 ), /* re16 */ + DRXJ_16TO8( 0 ), /* re17 */ + DRXJ_16TO8( 0 ), /* re18 */ + DRXJ_16TO8( 0 ), /* re19 */ + DRXJ_16TO8( 0 ), /* re20 */ + DRXJ_16TO8( 0 ), /* re21 */ + DRXJ_16TO8( 0 ), /* re22 */ + DRXJ_16TO8( 0 ), /* re23 */ + DRXJ_16TO8( 0 ), /* re24 */ + DRXJ_16TO8( 0 ), /* re25 */ + DRXJ_16TO8( 0 ), /* re26 */ + DRXJ_16TO8( 0 ) /* re27 */ + }; + const u8_t fm_taps_im[]= { + DRXJ_16TO8(-6 ), /* im0 */ + DRXJ_16TO8( 2 ), /* im1 */ + DRXJ_16TO8( 14 ), /* im2 */ + DRXJ_16TO8(-38 ), /* im3 */ + DRXJ_16TO8( 58 ), /* im4 */ + DRXJ_16TO8(-62 ), /* im5 */ + DRXJ_16TO8( 42 ), /* im6 */ + DRXJ_16TO8( 0 ), /* im7 */ + DRXJ_16TO8(-45 ), /* im8 */ + DRXJ_16TO8( 73 ), /* im9 */ + DRXJ_16TO8(-65 ), /* im10 */ + DRXJ_16TO8( 23 ), /* im11 */ + DRXJ_16TO8( 34 ), /* im12 */ + DRXJ_16TO8(-77 ), /* im13 */ + DRXJ_16TO8( 80 ), /* im14 */ + DRXJ_16TO8(-39 ), /* im15 */ + DRXJ_16TO8(-25 ), /* im16 */ + DRXJ_16TO8( 78 ), /* im17 */ + DRXJ_16TO8(-90 ), /* im18 */ + DRXJ_16TO8( 52 ), /* im19 */ + DRXJ_16TO8( 16 ), /* im20 */ + DRXJ_16TO8(-77 ), /* im21 */ + DRXJ_16TO8( 97 ), /* im22 */ + DRXJ_16TO8(-62 ), /* im23 */ + DRXJ_16TO8(-8 ), /* im24 */ + DRXJ_16TO8( 75 ), /* im25 */ + DRXJ_16TO8(-100 ), /* im26 */ + DRXJ_16TO8( 70 ) /* im27 */ + }; + + pI2CDeviceAddr_t devAddr = NULL; + DRXJSCUCmd_t cmdSCU = { /* command */ 0, + /* parameterLen */ 0, + /* resultLen */ 0, + /* *parameter */ NULL, + /* *result */ NULL }; + u16_t cmdResult = 0; + u16_t cmdParam = 0; +#ifdef DRXJ_SPLIT_UCODE_UPLOAD + DRXUCodeInfo_t ucodeInfo; + pDRXCommonAttr_t commonAttr = NULL; +#endif /* DRXJ_SPLIT_UCODE_UPLOAD */ + pDRXJData_t extAttr = NULL; + + extAttr = (pDRXJData_t)demod->myExtAttr; + devAddr = demod -> myI2CDevAddr; + +#ifdef DRXJ_SPLIT_UCODE_UPLOAD + commonAttr = demod -> myCommonAttr; + + /* Check if audio microcode is already uploaded */ + if ( !( extAttr->flagAudMcUploaded ) ) + { + ucodeInfo.mcData = commonAttr->microcode; + ucodeInfo.mcSize = commonAttr->microcodeSize; + + /* Upload only audio microcode */ + CHK_ERROR ( CtrlUCodeUpload( demod, &ucodeInfo, UCODE_UPLOAD, TRUE ) ); + + if ( commonAttr->verifyMicrocode == TRUE ) + { + CHK_ERROR( CtrlUCodeUpload( demod, &ucodeInfo, UCODE_VERIFY, TRUE ) ); + } + + /* Prevent uploading audio microcode again */ + extAttr->flagAudMcUploaded = TRUE; + } +#endif /* DRXJ_SPLIT_UCODE_UPLOAD */ + + WR16( devAddr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_STOP ); + WR16( devAddr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP ); + WR16( devAddr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP ); + WR16( devAddr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP ); + WR16( devAddr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP ); + WR16( devAddr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP ); + /* Reset ATV SCU */ + cmdSCU.command = SCU_RAM_COMMAND_STANDARD_ATV | + SCU_RAM_COMMAND_CMD_DEMOD_RESET; + cmdSCU.parameterLen = 0; + cmdSCU.resultLen = 1; + cmdSCU.parameter = NULL; + cmdSCU.result = &cmdResult; + CHK_ERROR( SCUCommand( devAddr, &cmdSCU ) ); + + WR16( devAddr, ATV_TOP_MOD_CONTROL__A, ATV_TOP_MOD_CONTROL__PRE ); + + /* TODO remove AUTO/OFF patches after ucode fix. */ + switch ( *standard ) + { + case DRX_STANDARD_NTSC: + /* NTSC */ + cmdParam = SCU_RAM_ATV_STANDARD_STANDARD_MN; + + WR16( devAddr, IQM_RT_LO_INCR__A , IQM_RT_LO_INCR_MN ); + WR16( devAddr, IQM_CF_MIDTAP__A , IQM_CF_MIDTAP_RE__M ); + WRB ( devAddr, IQM_CF_TAP_RE0__A , sizeof(ntsc_taps_re) , + ((pu8_t)ntsc_taps_re) ); + WRB ( devAddr, IQM_CF_TAP_IM0__A , sizeof(ntsc_taps_im) , + ((pu8_t)ntsc_taps_im) ); + + WR16( devAddr, ATV_TOP_CR_AMP_TH__A , ATV_TOP_CR_AMP_TH_MN ); + WR16( devAddr, ATV_TOP_CR_CONT__A , + ( ATV_TOP_CR_CONT_CR_P_MN | + ATV_TOP_CR_CONT_CR_D_MN | + ATV_TOP_CR_CONT_CR_I_MN ) ); + WR16( devAddr, ATV_TOP_CR_OVM_TH__A , ATV_TOP_CR_OVM_TH_MN ); + WR16( devAddr, ATV_TOP_STD__A , (ATV_TOP_STD_MODE_MN | + ATV_TOP_STD_VID_POL_MN ) ); + WR16( devAddr, ATV_TOP_VID_AMP__A , ATV_TOP_VID_AMP_MN ); + + WR16( devAddr, SCU_RAM_ATV_AGC_MODE__A, + ( SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM | + SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE ) ); + WR16( devAddr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000 ); + WR16( devAddr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000 ); + WR16( devAddr, SCU_RAM_ATV_AMS_MAX_REF__A, + SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_BG_MN); + extAttr->phaseCorrectionBypass = FALSE; + extAttr->enableCVBSOutput = TRUE; + break; + case DRX_STANDARD_FM: + /* FM */ + cmdParam = SCU_RAM_ATV_STANDARD_STANDARD_FM; + + WR16( devAddr, IQM_RT_LO_INCR__A , 2994 ); + WR16( devAddr, IQM_CF_MIDTAP__A , 0 ); + WRB ( devAddr, IQM_CF_TAP_RE0__A , sizeof(fm_taps_re) , + ((pu8_t)fm_taps_re) ); + WRB ( devAddr, IQM_CF_TAP_IM0__A , sizeof(fm_taps_im) , + ((pu8_t)fm_taps_im) ); + WR16( devAddr, ATV_TOP_STD__A , (ATV_TOP_STD_MODE_FM | + ATV_TOP_STD_VID_POL_FM ) ); + WR16( devAddr, ATV_TOP_MOD_CONTROL__A, 0 ); + WR16( devAddr, ATV_TOP_CR_CONT__A , 0 ); + + WR16( devAddr, SCU_RAM_ATV_AGC_MODE__A , + ( SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW | + SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM )); + WR16( devAddr, IQM_RT_ROT_BP__A, IQM_RT_ROT_BP_ROT_OFF_OFF ); + extAttr->phaseCorrectionBypass = TRUE; + extAttr->enableCVBSOutput = FALSE; + break; + case DRX_STANDARD_PAL_SECAM_BG: + /* PAL/SECAM B/G */ + cmdParam = SCU_RAM_ATV_STANDARD_STANDARD_B; + + WR16( devAddr, IQM_RT_LO_INCR__A , 1820 );/* TODO check with IS */ + WR16( devAddr, IQM_CF_MIDTAP__A , IQM_CF_MIDTAP_RE__M ); + WRB ( devAddr, IQM_CF_TAP_RE0__A , sizeof(bg_taps_re) , + ((pu8_t)bg_taps_re) ); + WRB ( devAddr, IQM_CF_TAP_IM0__A , sizeof(bg_taps_im) , + ((pu8_t)bg_taps_im) ); + WR16( devAddr, ATV_TOP_VID_AMP__A , ATV_TOP_VID_AMP_BG ); + WR16( devAddr, ATV_TOP_CR_AMP_TH__A, ATV_TOP_CR_AMP_TH_BG ); + WR16( devAddr, ATV_TOP_CR_CONT__A , + ( ATV_TOP_CR_CONT_CR_P_BG | + ATV_TOP_CR_CONT_CR_D_BG | + ATV_TOP_CR_CONT_CR_I_BG ) ); + WR16( devAddr, ATV_TOP_CR_OVM_TH__A , ATV_TOP_CR_OVM_TH_BG ); + WR16( devAddr, ATV_TOP_STD__A , (ATV_TOP_STD_MODE_BG | + ATV_TOP_STD_VID_POL_BG ) ); + WR16( devAddr, SCU_RAM_ATV_AGC_MODE__A , + ( SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM | + SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE ) ); + WR16( devAddr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000 ); + WR16( devAddr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000 ); + WR16( devAddr, SCU_RAM_ATV_AMS_MAX_REF__A, + SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_BG_MN); + extAttr->phaseCorrectionBypass = FALSE; + extAttr->atvIfAgcCfg.ctrlMode = DRX_AGC_CTRL_AUTO; + extAttr->enableCVBSOutput = TRUE; + break; + case DRX_STANDARD_PAL_SECAM_DK: + /* PAL/SECAM D/K */ + cmdParam = SCU_RAM_ATV_STANDARD_STANDARD_DK; + + WR16( devAddr, IQM_RT_LO_INCR__A , 2225 );/* TODO check with IS */ + WR16( devAddr, IQM_CF_MIDTAP__A , IQM_CF_MIDTAP_RE__M ); + WRB ( devAddr, IQM_CF_TAP_RE0__A , sizeof(dk_i_l_lp_taps_re) , + ((pu8_t)dk_i_l_lp_taps_re) ); + WRB ( devAddr, IQM_CF_TAP_IM0__A , sizeof(dk_i_l_lp_taps_im) , + ((pu8_t)dk_i_l_lp_taps_im) ); + WR16( devAddr, ATV_TOP_CR_AMP_TH__A , ATV_TOP_CR_AMP_TH_DK ); + WR16( devAddr, ATV_TOP_VID_AMP__A , ATV_TOP_VID_AMP_DK ); + WR16( devAddr, ATV_TOP_CR_CONT__A , + ( ATV_TOP_CR_CONT_CR_P_DK | + ATV_TOP_CR_CONT_CR_D_DK | + ATV_TOP_CR_CONT_CR_I_DK ) ); + WR16( devAddr, ATV_TOP_CR_OVM_TH__A , ATV_TOP_CR_OVM_TH_DK ); + WR16( devAddr, ATV_TOP_STD__A , (ATV_TOP_STD_MODE_DK | + ATV_TOP_STD_VID_POL_DK ) ); + WR16( devAddr, SCU_RAM_ATV_AGC_MODE__A , + ( SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM | + SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE ) ); + WR16( devAddr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000 ); + WR16( devAddr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000 ); + WR16( devAddr, SCU_RAM_ATV_AMS_MAX_REF__A, + SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_DK); + extAttr->phaseCorrectionBypass = FALSE; + extAttr->atvIfAgcCfg.ctrlMode =DRX_AGC_CTRL_AUTO; + extAttr->enableCVBSOutput = TRUE; + break; + case DRX_STANDARD_PAL_SECAM_I: + /* PAL/SECAM I */ + cmdParam = SCU_RAM_ATV_STANDARD_STANDARD_I; + + WR16( devAddr, IQM_RT_LO_INCR__A , 2225 );/* TODO check with IS */ + WR16( devAddr, IQM_CF_MIDTAP__A , IQM_CF_MIDTAP_RE__M ); + WRB ( devAddr, IQM_CF_TAP_RE0__A , sizeof(dk_i_l_lp_taps_re) , + ((pu8_t)dk_i_l_lp_taps_re) ); + WRB ( devAddr, IQM_CF_TAP_IM0__A , sizeof(dk_i_l_lp_taps_im) , + ((pu8_t)dk_i_l_lp_taps_im) ); + WR16( devAddr, ATV_TOP_CR_AMP_TH__A , ATV_TOP_CR_AMP_TH_I ); + WR16( devAddr, ATV_TOP_VID_AMP__A , ATV_TOP_VID_AMP_I ); + WR16( devAddr, ATV_TOP_CR_CONT__A , + ( ATV_TOP_CR_CONT_CR_P_I | + ATV_TOP_CR_CONT_CR_D_I | + ATV_TOP_CR_CONT_CR_I_I ) ); + WR16( devAddr, ATV_TOP_CR_OVM_TH__A , ATV_TOP_CR_OVM_TH_I ); + WR16( devAddr, ATV_TOP_STD__A , (ATV_TOP_STD_MODE_I | + ATV_TOP_STD_VID_POL_I ) ); + WR16( devAddr, SCU_RAM_ATV_AGC_MODE__A , + ( SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM | + SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE ) ); + WR16( devAddr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000 ); + WR16( devAddr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000 ); + WR16( devAddr, SCU_RAM_ATV_AMS_MAX_REF__A, + SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_I); + extAttr->phaseCorrectionBypass = FALSE; + extAttr->atvIfAgcCfg.ctrlMode = DRX_AGC_CTRL_AUTO; + extAttr->enableCVBSOutput = TRUE; + break; + case DRX_STANDARD_PAL_SECAM_L: + /* PAL/SECAM L with negative modulation */ + cmdParam = SCU_RAM_ATV_STANDARD_STANDARD_L; + + WR16( devAddr, IQM_RT_LO_INCR__A , 2225 ); /* TODO check with IS */ + WR16( devAddr, ATV_TOP_VID_AMP__A , ATV_TOP_VID_AMP_L ); + WR16( devAddr, IQM_CF_MIDTAP__A , IQM_CF_MIDTAP_RE__M ); + WRB ( devAddr, IQM_CF_TAP_RE0__A , sizeof(dk_i_l_lp_taps_re) , + ((pu8_t)dk_i_l_lp_taps_re) ); + WRB ( devAddr, IQM_CF_TAP_IM0__A , sizeof(dk_i_l_lp_taps_im) , + ((pu8_t)dk_i_l_lp_taps_im) ); + WR16( devAddr, ATV_TOP_CR_AMP_TH__A , 0x2 ); /* TODO check with IS */ + WR16( devAddr, ATV_TOP_CR_CONT__A , + ( ATV_TOP_CR_CONT_CR_P_L | + ATV_TOP_CR_CONT_CR_D_L | + ATV_TOP_CR_CONT_CR_I_L ) ); + WR16( devAddr, ATV_TOP_CR_OVM_TH__A , ATV_TOP_CR_OVM_TH_L ); + WR16( devAddr, ATV_TOP_STD__A , (ATV_TOP_STD_MODE_L | + ATV_TOP_STD_VID_POL_L ) ); + WR16( devAddr, SCU_RAM_ATV_AGC_MODE__A , + ( SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_AM | + SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_ENABLE | + SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW ) ); + WR16( devAddr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000 ); + WR16( devAddr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000 ); + WR16( devAddr, SCU_RAM_ATV_AMS_MAX_REF__A, + SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_LLP); + extAttr->phaseCorrectionBypass = FALSE; + extAttr->atvIfAgcCfg.ctrlMode = DRX_AGC_CTRL_USER; + extAttr->atvIfAgcCfg.outputLevel = extAttr->atvRfAgcCfg.top; + extAttr->enableCVBSOutput = TRUE; + break; + case DRX_STANDARD_PAL_SECAM_LP: + /* PAL/SECAM L with positive modulation */ + cmdParam = SCU_RAM_ATV_STANDARD_STANDARD_LP; + + WR16( devAddr, ATV_TOP_VID_AMP__A , ATV_TOP_VID_AMP_LP ); + WR16( devAddr, IQM_RT_LO_INCR__A , 2225 ); /* TODO check with IS */ + WR16( devAddr, IQM_CF_MIDTAP__A , IQM_CF_MIDTAP_RE__M ); + WRB ( devAddr, IQM_CF_TAP_RE0__A , sizeof(dk_i_l_lp_taps_re) , + ((pu8_t)dk_i_l_lp_taps_re) ); + WRB ( devAddr, IQM_CF_TAP_IM0__A , sizeof(dk_i_l_lp_taps_im) , + ((pu8_t)dk_i_l_lp_taps_im) ); + WR16( devAddr, ATV_TOP_CR_AMP_TH__A , 0x2 ); /* TODO check with IS */ + WR16( devAddr, ATV_TOP_CR_CONT__A , + ( ATV_TOP_CR_CONT_CR_P_LP | + ATV_TOP_CR_CONT_CR_D_LP | + ATV_TOP_CR_CONT_CR_I_LP ) ); + WR16( devAddr, ATV_TOP_CR_OVM_TH__A , ATV_TOP_CR_OVM_TH_LP ); + WR16( devAddr, ATV_TOP_STD__A , (ATV_TOP_STD_MODE_LP | + ATV_TOP_STD_VID_POL_LP ) ); + WR16( devAddr, SCU_RAM_ATV_AGC_MODE__A , + ( SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_AM | + SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_ENABLE | + SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW ) ); + WR16( devAddr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000 ); + WR16( devAddr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000 ); + WR16( devAddr, SCU_RAM_ATV_AMS_MAX_REF__A, + SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_LLP); + extAttr->phaseCorrectionBypass = FALSE; + extAttr->atvIfAgcCfg.ctrlMode = DRX_AGC_CTRL_USER; + extAttr->atvIfAgcCfg.outputLevel = extAttr->atvRfAgcCfg.top; + extAttr->enableCVBSOutput = TRUE; + break; + default: + return ( DRX_STS_ERROR ); + } + + /* Common initializations FM & NTSC & B/G & D/K & I & L & LP */ + if (extAttr->hasLNA == FALSE) + { + WR16( devAddr, IQM_AF_AMUX__A, 0x01); + } + + WR16( devAddr, SCU_RAM_ATV_STANDARD__A , 0x002 ); + WR16( devAddr, IQM_AF_CLP_LEN__A , IQM_AF_CLP_LEN_ATV ); + WR16( devAddr, IQM_AF_CLP_TH__A , IQM_AF_CLP_TH_ATV ); + WR16( devAddr, IQM_AF_SNS_LEN__A , IQM_AF_SNS_LEN_ATV ); + CHK_ERROR( CtrlSetCfgPreSaw( demod, &(extAttr->atvPreSawCfg)) ); + WR16( devAddr, IQM_AF_AGC_IF__A , 10248 ); + + extAttr->iqmRcRateOfs = 0x00200000L; + WR32( devAddr, IQM_RC_RATE_OFS_LO__A , extAttr->iqmRcRateOfs ); + WR16( devAddr, IQM_RC_ADJ_SEL__A , IQM_RC_ADJ_SEL_B_OFF ); + WR16( devAddr, IQM_RC_STRETCH__A , IQM_RC_STRETCH_ATV ); + + WR16( devAddr, IQM_RT_ACTIVE__A , IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_ON | + IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_ON ); + + WR16( devAddr, IQM_CF_OUT_ENA__A , IQM_CF_OUT_ENA_ATV__M ); + WR16( devAddr, IQM_CF_SYMMETRIC__A , IQM_CF_SYMMETRIC_IM__M ); + /* default: SIF in standby */ + WR16( devAddr, ATV_TOP_SYNC_SLICE__A , ATV_TOP_SYNC_SLICE_MN ); + WR16( devAddr, ATV_TOP_MOD_ACCU__A , ATV_TOP_MOD_ACCU__PRE ); + + WR16( devAddr, SCU_RAM_ATV_SIF_GAIN__A , 0x080 ); + WR16( devAddr, SCU_RAM_ATV_FAGC_TH_RED__A , 10 ); + WR16( devAddr, SCU_RAM_ATV_AAGC_CNT__A , 7 ); + WR16( devAddr, SCU_RAM_ATV_NAGC_KI_MIN__A , 0x0225 ); + WR16( devAddr, SCU_RAM_ATV_NAGC_KI_MAX__A , 0x0547 ); + WR16( devAddr, SCU_RAM_ATV_KI_CHANGE_TH__A , 20 ); + WR16( devAddr, SCU_RAM_ATV_LOCK__A , 0 ); + + WR16( devAddr, IQM_RT_DELAY__A , IQM_RT_DELAY__PRE ); + WR16( devAddr, SCU_RAM_ATV_BPC_KI_MIN__A , 531 ); + WR16( devAddr, SCU_RAM_ATV_PAGC_KI_MIN__A, 1061 ); + WR16( devAddr, SCU_RAM_ATV_BP_REF_MIN__A , 100 ); + WR16( devAddr, SCU_RAM_ATV_BP_REF_MAX__A , 260 ); + WR16( devAddr, SCU_RAM_ATV_BP_LVL__A , 0 ); + WR16( devAddr, SCU_RAM_ATV_AMS_MAX__A , 0 ); + WR16( devAddr, SCU_RAM_ATV_AMS_MIN__A , 2047 ); + WR16( devAddr, SCU_RAM_GPIO__A , 0 ); + + /* Override reset values with current shadow settings */ + CHK_ERROR( AtvUpdateConfig( demod, TRUE) ); + + /* Configure/restore AGC settings */ + CHK_ERROR( InitAGC( demod ) ); + CHK_ERROR( SetAgcIf( demod, &(extAttr->atvIfAgcCfg), FALSE ) ); + CHK_ERROR( SetAgcRf( demod, &(extAttr->atvRfAgcCfg), FALSE ) ); + CHK_ERROR( CtrlSetCfgPreSaw( demod, &(extAttr->atvPreSawCfg)) ); + + /* Set SCU ATV substandard,assuming this doesn't require running ATV block */ + cmdSCU.command = SCU_RAM_COMMAND_STANDARD_ATV | + SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV; + cmdSCU.parameterLen = 1; + cmdSCU.resultLen = 1; + cmdSCU.parameter = &cmdParam; + cmdSCU.result = &cmdResult; + CHK_ERROR( SCUCommand( devAddr, &cmdSCU ) ); + + /* turn the analog work around on/off (must after set_env b/c it is set in mc)*/ + if ( extAttr->mfx == 0x03 ) + { + WR16( devAddr, SCU_RAM_ATV_ENABLE_IIR_WA__A, 0 ); + } + else + { + WR16( devAddr, SCU_RAM_ATV_ENABLE_IIR_WA__A, 1 ); + WR16( devAddr, SCU_RAM_ATV_IIR_CRIT__A , 225 ); + } + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} +#endif + +/* -------------------------------------------------------------------------- */ + +#ifndef DRXJ_DIGITAL_ONLY +/** +* \fn DRXStatus_t SetATVChannel () +* \brief Set ATV channel. +* \param demod: instance of demod. +* \return DRXStatus_t. +* +* Not much needs to be done here, only start the SCU for NTSC/FM. +* Mirrored channels are not expected in the RF domain, so IQM FS setting +* doesn't need to be remembered. +* The channel->mirror parameter is therefor ignored. +* +*/ +static DRXStatus_t +SetATVChannel( pDRXDemodInstance_t demod, + DRXFrequency_t tunerFreqOffset, + pDRXChannel_t channel, + DRXStandard_t standard ) +{ + DRXJSCUCmd_t cmdSCU = {/* command */ 0, + /* parameterLen */ 0, + /* resultLen */ 0, + /* parameter */ NULL, + /* result */ NULL }; + u16_t cmdResult = 0; + pDRXJData_t extAttr = NULL; + pI2CDeviceAddr_t devAddr = NULL; + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* + Program frequency shifter + No need to account for mirroring on RF + */ + if (channel->mirror == DRX_MIRROR_AUTO) + { + extAttr->mirror = DRX_MIRROR_NO; + } + else + { + extAttr->mirror = channel->mirror; + } + + CHK_ERROR ( SetFrequency ( demod, channel, tunerFreqOffset ) ); + WR16(devAddr, ATV_TOP_CR_FREQ__A, ATV_TOP_CR_FREQ__PRE); + + /* Start ATV SCU */ + cmdSCU.command = SCU_RAM_COMMAND_STANDARD_ATV | + SCU_RAM_COMMAND_CMD_DEMOD_START; + cmdSCU.parameterLen = 0; + cmdSCU.resultLen = 1; + cmdSCU.parameter = NULL; + cmdSCU.result = &cmdResult; + CHK_ERROR( SCUCommand( devAddr, &cmdSCU ) ); + +/* if ( (extAttr->standard == DRX_STANDARD_FM) && (extAttr->flagSetAUDdone == TRUE) ) + { + extAttr->detectedRDS = (Bool_t)FALSE; + }*/ + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} +#endif + +/* -------------------------------------------------------------------------- */ + +/** +* \fn DRXStatus_t GetATVChannel () +* \brief Set ATV channel. +* \param demod: instance of demod. +* \param channel: pointer to channel data. +* \param standard: NTSC or FM. +* \return DRXStatus_t. +* +* Covers NTSC, PAL/SECAM - B/G, D/K, I, L, LP and FM. +* Computes the frequency offset in te RF domain and adds it to +* channel->frequency. Determines the value for channel->bandwidth. +* +*/ +#ifndef DRXJ_DIGITAL_ONLY +static DRXStatus_t +GetATVChannel( pDRXDemodInstance_t demod, + pDRXChannel_t channel, + DRXStandard_t standard ) +{ + DRXFrequency_t offset = 0; + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* Bandwidth */ + channel->bandwidth = ((pDRXJData_t)demod -> myExtAttr)->currBandwidth; + + switch ( standard ) + { + case DRX_STANDARD_NTSC: + case DRX_STANDARD_PAL_SECAM_BG: + case DRX_STANDARD_PAL_SECAM_DK: + case DRX_STANDARD_PAL_SECAM_I: + case DRX_STANDARD_PAL_SECAM_L: + { + u16_t measuredOffset=0; + + /* get measured frequency offset */ + RR16(devAddr, ATV_TOP_CR_FREQ__A, &measuredOffset); + /* Signed 8 bit register => sign extension needed */ + if ( (measuredOffset & 0x0080) != 0) + { + /* sign extension */ + measuredOffset |= 0xFF80; + } + offset+= (DRXFrequency_t)( ((s16_t)measuredOffset)*10); + break; + } + case DRX_STANDARD_PAL_SECAM_LP: + { + u16_t measuredOffset=0; + + /* get measured frequency offset */ + RR16(devAddr, ATV_TOP_CR_FREQ__A, &measuredOffset); + /* Signed 8 bit register => sign extension needed */ + if ( (measuredOffset & 0x0080) != 0) + { + /* sign extension */ + measuredOffset |= 0xFF80; + } + offset-= (DRXFrequency_t)( ((s16_t)measuredOffset)*10); + } + break; + case DRX_STANDARD_FM: + /* TODO: compute offset using AUD_DSP_RD_FM_DC_LEVEL_A__A and + AUD_DSP_RD_FM_DC_LEVEL_B__A. For now leave frequency as is. + */ + /* No bandwidth know for FM */ + channel->bandwidth = DRX_BANDWIDTH_UNKNOWN; + break; + default: + return ( DRX_STS_ERROR ); + } + + channel->frequency -= offset; + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/* -------------------------------------------------------------------------- */ +/** +* \fn DRXStatus_t GetAtvSigStrength() +* \brief Retrieve signal strength for ATV & FM. +* \param devmod Pointer to demodulator instance. +* \param sigQuality Pointer to signal strength data; range 0, .. , 100. +* \return DRXStatus_t. +* \retval DRX_STS_OK sigStrength contains valid data. +* \retval DRX_STS_ERROR Erroneous data, sigStrength equals 0. +* +* Taking into account: +* * digital gain +* * IF gain (not implemented yet, waiting for IF gain control by ucode) +* * RF gain +* +* All weights (digital, if, rf) must add up to 100. +* +* TODO: ? dynamically adapt weights in case RF and/or IF agc of drxj +* is not used ? +*/ +static DRXStatus_t +GetAtvSigStrength( pDRXDemodInstance_t demod, + pu16_t sigStrength ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + + /* All weights must add up to 100 (%) + TODO: change weights when IF ctrl is available */ + u32_t digitalWeight = 50; /* 0 .. 100 */ + u32_t rfWeight = 50; /* 0 .. 100 */ + u32_t ifWeight = 0; /* 0 .. 100 */ + + u16_t digitalCurrGain = 0; + u32_t digitalMaxGain = 0; + u32_t digitalMinGain = 0; + u16_t rfCurrGain = 0; + u32_t rfMaxGain = 0x800; /* taken from ucode */ + u32_t rfMinGain = 0x7fff; + u16_t ifCurrGain = 0; + u32_t ifMaxGain = 0x800; /* taken from ucode */ + u32_t ifMinGain = 0x7fff; + + u32_t digitalStrength = 0; /* 0.. 100 */ + u32_t rfStrength = 0; /* 0.. 100 */ + u32_t ifStrength = 0; /* 0.. 100 */ + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + *sigStrength = 0; + + switch( extAttr->standard ) + { + case DRX_STANDARD_PAL_SECAM_BG : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_DK : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_I : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_L : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_LP : /* fallthrough */ + case DRX_STANDARD_NTSC: + SARR16(devAddr, SCU_RAM_ATV_VID_GAIN_HI__A, &digitalCurrGain); + digitalMaxGain = 22512; /* taken from ucode */ + digitalMinGain = 2400; /* taken from ucode */ + break; + case DRX_STANDARD_FM: + SARR16(devAddr, SCU_RAM_ATV_SIF_GAIN__A, &digitalCurrGain); + digitalMaxGain = 0x4ff; /* taken from ucode */ + digitalMinGain = 0; /* taken from ucode */ + break; + default: + return (DRX_STS_ERROR); + break; + } + RR16(devAddr, IQM_AF_AGC_RF__A, &rfCurrGain); + RR16(devAddr, IQM_AF_AGC_IF__A, &ifCurrGain); + + /* clipping */ + if ( digitalCurrGain >= digitalMaxGain ) digitalCurrGain = (u16_t)digitalMaxGain; + if ( digitalCurrGain <= digitalMinGain ) digitalCurrGain = (u16_t)digitalMinGain; + if ( ifCurrGain <= ifMaxGain ) ifCurrGain = (u16_t)ifMaxGain; + if ( ifCurrGain >= ifMinGain ) ifCurrGain = (u16_t)ifMinGain; + if ( rfCurrGain <= rfMaxGain ) rfCurrGain = (u16_t)rfMaxGain; + if ( rfCurrGain >= rfMinGain ) rfCurrGain = (u16_t)rfMinGain; + + /* TODO: use SCU_RAM_ATV_RAGC_HR__A to shift max and min in case + of clipping at ADC */ + + /* Compute signal strength (in %) per "gain domain" */ + + /* Digital gain */ + /* TODO: ADC clipping not handled */ + digitalStrength = ( 100 *(digitalMaxGain-(u32_t)digitalCurrGain) )/ + (digitalMaxGain -digitalMinGain); + + /* TODO: IF gain not implemented yet in microcode, check after impl. */ + ifStrength = ( 100 *((u32_t)ifCurrGain-ifMaxGain) )/ + ( ifMinGain - ifMaxGain ); + + /* Rf gain */ + /* TODO: ADC clipping not handled */ + rfStrength = ( 100 *((u32_t)rfCurrGain-rfMaxGain) )/ + ( rfMinGain - rfMaxGain ); + + /* Compute a weighted signal strength (in %) */ + *sigStrength = (u16_t) (digitalWeight*digitalStrength + + rfWeight*rfStrength + + ifWeight*ifStrength); + *sigStrength /= 100; + + return (DRX_STS_OK); + rw_error: + return (DRX_STS_ERROR); +} + +/* -------------------------------------------------------------------------- */ +/** +* \fn DRXStatus_t AtvSigQuality() +* \brief Retrieve signal quality indication for ATV. +* \param devmod Pointer to demodulator instance. +* \param sigQuality Pointer to signal quality structure. +* \return DRXStatus_t. +* \retval DRX_STS_OK sigQuality contains valid data. +* \retval DRX_STS_ERROR Erroneous data, sigQuality indicator equals 0. +* +* +*/ +static DRXStatus_t +AtvSigQuality( pDRXDemodInstance_t demod, + pDRXSigQuality_t sigQuality ) +{ + pI2CDeviceAddr_t devAddr = NULL; + u16_t qualityIndicator = 0; + + devAddr = demod -> myI2CDevAddr; + + /* defined values for fields not used */ + sigQuality->MER = 0; + sigQuality->preViterbiBER = 0; + sigQuality->postViterbiBER = 0; + sigQuality->scaleFactorBER = 1; + sigQuality->packetError = 0; + sigQuality->postReedSolomonBER = 0; + + /* + Mapping: + 0x000..0x080: strong signal => 80% .. 100% + 0x080..0x700: weak signal => 30% .. 80% + 0x700..0x7ff: no signal => 0% .. 30% + */ + + SARR16( devAddr, SCU_RAM_ATV_CR_LOCK__A, &qualityIndicator ); + qualityIndicator &= SCU_RAM_ATV_CR_LOCK_CR_LOCK__M; + if ( qualityIndicator <= 0x80 ) + { + sigQuality->indicator = 80 + ( (20*(0x80-qualityIndicator))/0x80); + } else if ( qualityIndicator <= 0x700 ) + { + sigQuality->indicator = 30 + + ( (50*(0x700-qualityIndicator))/(0x700-0x81)); + } else { + sigQuality->indicator = + (30*(0x7FF-qualityIndicator))/(0x7FF-0x701); + } + + return (DRX_STS_OK); + rw_error: + return (DRX_STS_ERROR); +} +#endif /* DRXJ_DIGITAL_ONLY */ + +/*============================================================================*/ +/*== END ATV DATAPATH FUNCTIONS ==*/ +/*============================================================================*/ + +#ifndef DRXJ_EXCLUDE_AUDIO +/*===========================================================================*/ +/*===========================================================================*/ +/*== AUDIO DATAPATH FUNCTIONS ==*/ +/*===========================================================================*/ +/*===========================================================================*/ + +/* +* \brief Power up AUD. +* \param demod instance of demodulator +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +PowerUpAud( pDRXDemodInstance_t demod, + Bool_t setStandard) +{ + DRXAudStandard_t audStandard = DRX_AUD_STANDARD_AUTO; + pI2CDeviceAddr_t devAddr = NULL; + + devAddr = demod->myI2CDevAddr; + + WR16( devAddr, AUD_TOP_COMM_EXEC__A, AUD_TOP_COMM_EXEC_ACTIVE); + /* setup TR interface: R/W mode, fifosize=8 */ + WR16( devAddr, AUD_TOP_TR_MDE__A, 8); + WR16( devAddr, AUD_COMM_EXEC__A, AUD_COMM_EXEC_ACTIVE); + + if ( setStandard == TRUE ) + { + CHK_ERROR( AUDCtrlSetStandard ( demod, &audStandard ) ); + } + + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; +} + +/*============================================================================*/ + +/** +* \brief Power up AUD. +* \param demod instance of demodulator +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +PowerDownAud( pDRXDemodInstance_t demod ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + + devAddr = (pI2CDeviceAddr_t)demod->myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + WR16( devAddr, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP ); + + extAttr->audData.audioIsActive = FALSE; + + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; +} +/*============================================================================*/ +/** +* \brief Get Modus data from audio RAM +* \param demod instance of demodulator +* \param pointer to modus +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AUDGetModus ( pDRXDemodInstance_t demod, + pu16_t modus ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + + u16_t rModus = 0; + u16_t rModusHi = 0; + u16_t rModusLo = 0; + + if ( modus == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + devAddr = (pI2CDeviceAddr_t)demod->myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* power up */ + if ( extAttr->audData.audioIsActive == FALSE ) + { + CHK_ERROR ( PowerUpAud( demod , TRUE ) ); + extAttr->audData.audioIsActive = TRUE; + } + + /* Modus register is combined in to RAM location */ + RR16( devAddr, AUD_DEM_RAM_MODUS_HI__A, &rModusHi ); + RR16( devAddr, AUD_DEM_RAM_MODUS_LO__A, &rModusLo ); + + rModus = ( (rModusHi << 12 ) & AUD_DEM_RAM_MODUS_HI__M) + | ((( rModusLo & AUD_DEM_RAM_MODUS_LO__M) )); + + *modus = rModus; + + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; + +} + +/*============================================================================*/ +/** +* \brief Get audio RDS dat +* \param demod instance of demodulator +* \param pointer to DRXCfgAudRDS_t +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AUDCtrlGetCfgRDS ( pDRXDemodInstance_t demod, + pDRXCfgAudRDS_t status ) +{ + pI2CDeviceAddr_t addr = NULL; + pDRXJData_t extAttr = NULL; + + u16_t rRDSArrayCntInit = 0; + u16_t rRDSArrayCntCheck = 0; + u16_t rRDSData = 0; + u16_t RDSDataCnt = 0; + + addr = (pI2CDeviceAddr_t)demod->myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + + if ( status == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + /* power up */ + if ( extAttr->audData.audioIsActive == FALSE ) + { + CHK_ERROR ( PowerUpAud( demod , TRUE ) ); + extAttr->audData.audioIsActive = TRUE; + } + + status->valid = FALSE; + + RR16( addr, AUD_DEM_RD_RDS_ARRAY_CNT__A, &rRDSArrayCntInit); + + if ( rRDSArrayCntInit == + AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT_RDS_DATA_NOT_VALID ) + { + /* invalid data */ + return DRX_STS_OK; + } + + if ( extAttr->audData.rdsDataCounter == rRDSArrayCntInit) + { + /* no new data */ + return DRX_STS_OK; + } + + /* RDS is detected, as long as FM radio is selected assume + RDS will be available */ + extAttr->audData.rdsDataPresent = TRUE; + + /* new data */ + /* read the data */ + for ( RDSDataCnt = 0; + RDSDataCnt < AUD_RDS_ARRAY_SIZE; + RDSDataCnt++) + { + RR16 ( addr, AUD_DEM_RD_RDS_DATA__A, &rRDSData ); + status->data[RDSDataCnt] = rRDSData; + } + + RR16( addr, AUD_DEM_RD_RDS_ARRAY_CNT__A, &rRDSArrayCntCheck); + + if ( rRDSArrayCntCheck == rRDSArrayCntInit ) + { + status->valid = TRUE; + extAttr->audData.rdsDataCounter = rRDSArrayCntCheck; + } + + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; +} + +/*============================================================================*/ +/** +* \brief Get the current audio carrier detection status +* \param demod instance of demodulator +* \param pointer to AUDCtrlGetStatus +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AUDCtrlGetCarrierDetectStatus ( pDRXDemodInstance_t demod, + pDRXAudStatus_t status ) +{ + pDRXJData_t extAttr = NULL; + pI2CDeviceAddr_t devAddr = NULL; + + u16_t rData = 0; + + if ( status == NULL) + { + return DRX_STS_INVALID_ARG; + } + + devAddr = (pI2CDeviceAddr_t)demod->myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* power up */ + if ( extAttr->audData.audioIsActive == FALSE ) + { + CHK_ERROR ( PowerUpAud( demod , TRUE ) ); + extAttr->audData.audioIsActive = TRUE; + } + + /* initialize the variables */ + status->carrierA = FALSE; + status->carrierB = FALSE; + status->nicamStatus = DRX_AUD_NICAM_NOT_DETECTED; + status->sap = FALSE; + status->stereo = FALSE; + + /* read stereo sound mode indication */ + RR16( devAddr, AUD_DEM_RD_STATUS__A, &rData ); + + /* carrier a detected */ + if ( (rData & AUD_DEM_RD_STATUS_STAT_CARR_A__M ) == + AUD_DEM_RD_STATUS_STAT_CARR_A_DETECTED ) + { + status->carrierA = TRUE; + } + + /* carrier b detected */ + if ( (rData & AUD_DEM_RD_STATUS_STAT_CARR_B__M ) == + AUD_DEM_RD_STATUS_STAT_CARR_B_DETECTED ) + { + status->carrierB = TRUE; + } + /* nicam detected */ + if ( (rData & AUD_DEM_RD_STATUS_STAT_NICAM__M) == + AUD_DEM_RD_STATUS_STAT_NICAM_NICAM_DETECTED) + { + if ((rData & AUD_DEM_RD_STATUS_BAD_NICAM__M) == + AUD_DEM_RD_STATUS_BAD_NICAM_OK) + { + status->nicamStatus = DRX_AUD_NICAM_DETECTED; + } + else + { + status->nicamStatus = DRX_AUD_NICAM_BAD; + } + } + + /* audio mode bilingual or SAP detected */ + if ( (rData & AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__M) == + AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP_SAP) + { + status->sap = TRUE; + } + + /* stereo detected */ + if ( (rData & AUD_DEM_RD_STATUS_STAT_STEREO__M) == + AUD_DEM_RD_STATUS_STAT_STEREO_STEREO) + { + status->stereo = TRUE; + } + + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; +} + + +/*============================================================================*/ +/** +* \brief Get the current audio status parameters +* \param demod instance of demodulator +* \param pointer to AUDCtrlGetStatus +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AUDCtrlGetStatus ( pDRXDemodInstance_t demod, + pDRXAudStatus_t status ) +{ + pDRXJData_t extAttr = NULL; + pI2CDeviceAddr_t devAddr = NULL; + DRXCfgAudRDS_t rds = { FALSE, {0} }; + u16_t rData = 0; + + if ( status == NULL) + { + return DRX_STS_INVALID_ARG; + } + + devAddr = (pI2CDeviceAddr_t)demod->myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* carrier detection */ + CHK_ERROR ( AUDCtrlGetCarrierDetectStatus ( demod, status ) ); + + /* rds data */ + status->rds = FALSE; + CHK_ERROR ( AUDCtrlGetCfgRDS ( demod, &rds ) ); + status->rds = extAttr->audData.rdsDataPresent; + + /* fmIdent */ + RR16( devAddr, AUD_DSP_RD_FM_IDENT_VALUE__A, &rData); + rData >>= AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__B; + status->fmIdent = (s8_t)rData; + + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; +} + +/*============================================================================*/ +/** +* \brief Get the current volume settings +* \param demod instance of demodulator +* \param pointer to DRXCfgAudVolume_t +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AUDCtrlGetCfgVolume ( pDRXDemodInstance_t demod, + pDRXCfgAudVolume_t volume ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + + u16_t rVolume = 0; + u16_t rAVC = 0; + u16_t rStrengthLeft = 0; + u16_t rStrengthRight = 0; + + if ( volume == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + devAddr = (pI2CDeviceAddr_t)demod->myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* power up */ + if ( extAttr->audData.audioIsActive == FALSE ) + { + CHK_ERROR ( PowerUpAud( demod , TRUE ) ); + extAttr->audData.audioIsActive = TRUE; + } + + /* volume */ + volume->mute = extAttr->audData.volume.mute; + RR16( devAddr, AUD_DSP_WR_VOLUME__A, &rVolume ); + if ( rVolume == 0 ) + { + volume->mute = TRUE; + volume->volume = extAttr->audData.volume.volume; + } + else + { + volume->mute = FALSE; + volume->volume = ( ( rVolume & AUD_DSP_WR_VOLUME_VOL_MAIN__M ) >> + AUD_DSP_WR_VOLUME_VOL_MAIN__B ) - + AUD_VOLUME_ZERO_DB; + if ( volume->volume < AUD_VOLUME_DB_MIN ) + { + volume->volume = AUD_VOLUME_DB_MIN; + } + if ( volume->volume > AUD_VOLUME_DB_MAX ) + { + volume->volume = AUD_VOLUME_DB_MAX; + } + } + + /* automatic volume control */ + RR16( devAddr, AUD_DSP_WR_AVC__A, &rAVC ); + + if( ( rAVC & AUD_DSP_WR_AVC_AVC_ON__M) == + AUD_DSP_WR_AVC_AVC_ON_OFF ) + + { + volume->avcMode = DRX_AUD_AVC_OFF; + } + else + { + switch ( rAVC & AUD_DSP_WR_AVC_AVC_DECAY__M ) + { + case AUD_DSP_WR_AVC_AVC_DECAY_20_MSEC: + volume->avcMode = DRX_AUD_AVC_DECAYTIME_20MS; + break; + case AUD_DSP_WR_AVC_AVC_DECAY_8_SEC: + volume->avcMode = DRX_AUD_AVC_DECAYTIME_8S; + break; + case AUD_DSP_WR_AVC_AVC_DECAY_4_SEC: + volume->avcMode = DRX_AUD_AVC_DECAYTIME_4S; + break; + case AUD_DSP_WR_AVC_AVC_DECAY_2_SEC: + volume->avcMode = DRX_AUD_AVC_DECAYTIME_2S; + break; + default: + return DRX_STS_ERROR; + break; + } + } + + /* max attenuation */ + switch ( rAVC & AUD_DSP_WR_AVC_AVC_MAX_ATT__M ) + { + case AUD_DSP_WR_AVC_AVC_MAX_ATT_12DB: + volume->avcMaxAtten = DRX_AUD_AVC_MAX_ATTEN_12DB; + break; + case AUD_DSP_WR_AVC_AVC_MAX_ATT_18DB: + volume->avcMaxAtten = DRX_AUD_AVC_MAX_ATTEN_18DB; + break; + case AUD_DSP_WR_AVC_AVC_MAX_ATT_24DB: + volume->avcMaxAtten = DRX_AUD_AVC_MAX_ATTEN_24DB; + break; + default: + return DRX_STS_ERROR; + break; + } + + /* max gain */ + switch ( rAVC & AUD_DSP_WR_AVC_AVC_MAX_GAIN__M ) + { + case AUD_DSP_WR_AVC_AVC_MAX_GAIN_0DB: + volume->avcMaxGain = DRX_AUD_AVC_MAX_GAIN_0DB; + break; + case AUD_DSP_WR_AVC_AVC_MAX_GAIN_6DB: + volume->avcMaxGain = DRX_AUD_AVC_MAX_GAIN_6DB; + break; + case AUD_DSP_WR_AVC_AVC_MAX_GAIN_12DB: + volume->avcMaxGain = DRX_AUD_AVC_MAX_GAIN_12DB; + break; + default: + return DRX_STS_ERROR; + break; + } + + /* reference level */ + volume->avcRefLevel = (u16_t)( ( rAVC & AUD_DSP_WR_AVC_AVC_REF_LEV__M) >> + AUD_DSP_WR_AVC_AVC_REF_LEV__B ); + + /* read qpeak registers and calculate strength of left and right carrier */ + /* quasi peaks formula: QP(dB) = 20 * log( AUD_DSP_RD_QPEAKx / Q(0dB) */ + /* Q(0dB) represents QP value of 0dB (hex value 0x4000) */ + /* left carrier */ + + /* QP vaues */ + /* left carrier */ + RR16 (devAddr, AUD_DSP_RD_QPEAK_L__A, &rStrengthLeft); + volume->strengthLeft = ( ( (s16_t) Log10Times100 ( rStrengthLeft ) ) - + AUD_CARRIER_STRENGTH_QP_0DB_LOG10T100 ) / 5; + + /* right carrier */ + RR16 (devAddr, AUD_DSP_RD_QPEAK_R__A, &rStrengthRight); + volume->strengthRight = ( ( (s16_t) Log10Times100 ( rStrengthRight ) ) - + AUD_CARRIER_STRENGTH_QP_0DB_LOG10T100 ) / 5; + + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; +} + + +/*============================================================================*/ +/** +* \brief Set the current volume settings +* \param demod instance of demodulator +* \param pointer to DRXCfgAudVolume_t +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AUDCtrlSetCfgVolume ( pDRXDemodInstance_t demod, + pDRXCfgAudVolume_t volume ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + + u16_t wVolume = 0; + u16_t wAVC = 0; + + + if ( volume == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + devAddr = (pI2CDeviceAddr_t)demod->myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* power up */ + if ( extAttr->audData.audioIsActive == FALSE ) + { + CHK_ERROR ( PowerUpAud( demod , TRUE ) ); + extAttr->audData.audioIsActive = TRUE; + } + + /* volume */ + /* volume range from -60 to 12 (expressed in dB) */ + if ( ( volume->volume < AUD_VOLUME_DB_MIN ) || + ( volume->volume > AUD_VOLUME_DB_MAX ) ) + { + return DRX_STS_INVALID_ARG; + } + + RR16( devAddr, AUD_DSP_WR_VOLUME__A, &wVolume ); + + /* clear the volume mask */ + wVolume &= (u16_t)~AUD_DSP_WR_VOLUME_VOL_MAIN__M; + if ( volume->mute == TRUE ) + { + /* mute */ + /* mute overrules volume */ + wVolume |= (u16_t) ( 0 ); + + } + else + { + wVolume |= (u16_t) ( ( volume->volume + AUD_VOLUME_ZERO_DB ) << + AUD_DSP_WR_VOLUME_VOL_MAIN__B ); + } + + WR16( devAddr, AUD_DSP_WR_VOLUME__A, wVolume ); + + /* automatic volume control */ + RR16( devAddr, AUD_DSP_WR_AVC__A, &wAVC ); + + /* clear masks that require writing */ + wAVC &= (u16_t) ~AUD_DSP_WR_AVC_AVC_ON__M; + wAVC &= (u16_t) ~AUD_DSP_WR_AVC_AVC_DECAY__M; + + if ( volume->avcMode == DRX_AUD_AVC_OFF ) + { + wAVC |= ( AUD_DSP_WR_AVC_AVC_ON_OFF ); + } + else + { + + wAVC |= ( AUD_DSP_WR_AVC_AVC_ON_ON ); + + /* avc decay */ + switch ( volume->avcMode ) + { + case DRX_AUD_AVC_DECAYTIME_20MS: + wAVC |= AUD_DSP_WR_AVC_AVC_DECAY_20_MSEC; + break; + case DRX_AUD_AVC_DECAYTIME_8S: + wAVC |= AUD_DSP_WR_AVC_AVC_DECAY_8_SEC; + break; + case DRX_AUD_AVC_DECAYTIME_4S: + wAVC |= AUD_DSP_WR_AVC_AVC_DECAY_4_SEC; + break; + case DRX_AUD_AVC_DECAYTIME_2S: + wAVC |= AUD_DSP_WR_AVC_AVC_DECAY_2_SEC; + break; + default: + return DRX_STS_INVALID_ARG; + } + } + + /* max attenuation */ + wAVC &= (u16_t) ~AUD_DSP_WR_AVC_AVC_MAX_ATT__M; + switch ( volume->avcMaxAtten ) + { + case DRX_AUD_AVC_MAX_ATTEN_12DB: + wAVC |= AUD_DSP_WR_AVC_AVC_MAX_ATT_12DB; + break; + case DRX_AUD_AVC_MAX_ATTEN_18DB: + wAVC |= AUD_DSP_WR_AVC_AVC_MAX_ATT_18DB; + break; + case DRX_AUD_AVC_MAX_ATTEN_24DB: + wAVC |= AUD_DSP_WR_AVC_AVC_MAX_ATT_24DB; + break; + default: + return DRX_STS_INVALID_ARG; + } + + /* max gain */ + wAVC &= (u16_t) ~AUD_DSP_WR_AVC_AVC_MAX_GAIN__M; + switch ( volume->avcMaxGain ) + { + case DRX_AUD_AVC_MAX_GAIN_0DB: + wAVC |= AUD_DSP_WR_AVC_AVC_MAX_GAIN_0DB; + break; + case DRX_AUD_AVC_MAX_GAIN_6DB: + wAVC |= AUD_DSP_WR_AVC_AVC_MAX_GAIN_6DB; + break; + case DRX_AUD_AVC_MAX_GAIN_12DB: + wAVC |= AUD_DSP_WR_AVC_AVC_MAX_GAIN_12DB; + break; + default: + return DRX_STS_INVALID_ARG; + } + + /* avc reference level */ + if ( volume->avcRefLevel > AUD_MAX_AVC_REF_LEVEL ) + { + return DRX_STS_INVALID_ARG; + } + + wAVC &= (u16_t)~AUD_DSP_WR_AVC_AVC_REF_LEV__M; + wAVC |= (u16_t)( volume->avcRefLevel << AUD_DSP_WR_AVC_AVC_REF_LEV__B ); + + WR16( devAddr, AUD_DSP_WR_AVC__A, wAVC ); + + /* all done, store config in data structure */ + extAttr->audData.volume = *volume; + + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; +} + + +/*============================================================================*/ +/** +* \brief Get the I2S settings +* \param demod instance of demodulator +* \param pointer to DRXCfgI2SOutput_t +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AUDCtrlGetCfgOutputI2S ( pDRXDemodInstance_t demod, + pDRXCfgI2SOutput_t output ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + + u16_t wI2SConfig = 0; + u16_t rI2SFreq = 0; + + if ( output == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + devAddr = (pI2CDeviceAddr_t)demod->myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* power up */ + if ( extAttr->audData.audioIsActive == FALSE ) + { + CHK_ERROR ( PowerUpAud( demod , TRUE ) ); + extAttr->audData.audioIsActive = TRUE; + } + + RR16( devAddr, AUD_DEM_RAM_I2S_CONFIG2__A, &wI2SConfig ); + RR16( devAddr, AUD_DSP_WR_I2S_OUT_FS__A, &rI2SFreq ); + + /* I2S mode */ + switch ( wI2SConfig & AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__M ) + { + case AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST_MASTER: + output->mode = DRX_I2S_MODE_MASTER; + break; + case AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST_SLAVE: + output->mode = DRX_I2S_MODE_SLAVE; + break; + default: + return DRX_STS_ERROR; + } + + /* I2S format */ + switch ( wI2SConfig & AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__M ) + { + case AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE_DELAY: + output->format = DRX_I2S_FORMAT_WS_ADVANCED; + break; + case AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE_NO_DELAY: + output->format = DRX_I2S_FORMAT_WS_WITH_DATA; + break; + default: + return DRX_STS_ERROR; + } + + /* I2S word length */ + switch ( wI2SConfig & AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__M ) + { + case AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_16: + output->wordLength = DRX_I2S_WORDLENGTH_16; + break; + case AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_32: + output->wordLength = DRX_I2S_WORDLENGTH_32; + break; + default: + return DRX_STS_ERROR; + } + + /* I2S polarity */ + switch ( wI2SConfig & AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__M ) + { + case AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL_LEFT_HIGH: + output->polarity = DRX_I2S_POLARITY_LEFT; + break; + case AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL_LEFT_LOW: + output->polarity = DRX_I2S_POLARITY_RIGHT; + break; + default: + return DRX_STS_ERROR; + } + + /* I2S output enabled */ + if ( ( wI2SConfig & AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__M ) + == AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_ENABLE ) + { + output->outputEnable = TRUE; + } + else + { + output->outputEnable = FALSE; + } + + if ( rI2SFreq > 0 ) + { + output->frequency = 6144UL * 48000 / rI2SFreq; + if ( output->wordLength == DRX_I2S_WORDLENGTH_16 ) + { + output->frequency *= 2; + } + } + else + { + output->frequency = AUD_I2S_FREQUENCY_MAX; + } + + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; +} + +/*============================================================================*/ +/** +* \brief Set the I2S settings +* \param demod instance of demodulator +* \param pointer to DRXCfgI2SOutput_t +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AUDCtrlSetCfgOutputI2S ( pDRXDemodInstance_t demod, + pDRXCfgI2SOutput_t output ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + + u16_t wI2SConfig = 0; + u16_t wI2SPadsDataDa = 0; + u16_t wI2SPadsDataCl = 0; + u16_t wI2SPadsDataWs = 0; + u32_t wI2SFreq = 0; + + if ( output == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + devAddr = (pI2CDeviceAddr_t)demod->myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* power up */ + if ( extAttr->audData.audioIsActive == FALSE ) + { + CHK_ERROR ( PowerUpAud( demod , TRUE ) ); + extAttr->audData.audioIsActive = TRUE; + } + + RR16( devAddr, AUD_DEM_RAM_I2S_CONFIG2__A, &wI2SConfig ); + + /* I2S mode */ + wI2SConfig &= (u16_t)~AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__M; + + switch ( output->mode ) + { + case DRX_I2S_MODE_MASTER: + wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST_MASTER; + break; + case DRX_I2S_MODE_SLAVE: + wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST_SLAVE; + break; + default: + return DRX_STS_INVALID_ARG; + } + + /* I2S format */ + wI2SConfig &= (u16_t)~AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__M; + + switch ( output->format ) + { + case DRX_I2S_FORMAT_WS_ADVANCED: + wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE_DELAY; + break; + case DRX_I2S_FORMAT_WS_WITH_DATA: + wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE_NO_DELAY; + break; + default: + return DRX_STS_INVALID_ARG; + } + + /* I2S word length */ + wI2SConfig &= (u16_t)~AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__M; + + switch ( output->wordLength ) + { + case DRX_I2S_WORDLENGTH_16: + wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_16; + break; + case DRX_I2S_WORDLENGTH_32: + wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_32; + break; + default: + return DRX_STS_INVALID_ARG; + } + + /* I2S polarity */ + wI2SConfig &= (u16_t)~AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__M; + switch ( output->polarity ) + { + case DRX_I2S_POLARITY_LEFT: + wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL_LEFT_HIGH; + break; + case DRX_I2S_POLARITY_RIGHT: + wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL_LEFT_LOW; + break; + default: + return DRX_STS_INVALID_ARG; + } + + /* I2S output enabled */ + wI2SConfig &= (u16_t)~AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__M; + if ( output->outputEnable == TRUE ) + { + wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_ENABLE; + } + else + { + wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_DISABLE; + } + + /* + I2S frequency + + wI2SFreq = 6144 * 48000 * nrbits / ( 32 * frequency ) + + 16bit: 6144 * 48000 / ( 2 * freq ) = ( 6144 * 48000 / freq ) / 2 + 32bit: 6144 * 48000 / freq = ( 6144 * 48000 / freq ) + */ + if ( ( output->frequency > AUD_I2S_FREQUENCY_MAX ) || + output->frequency < AUD_I2S_FREQUENCY_MIN ) + { + return DRX_STS_INVALID_ARG; + } + + wI2SFreq = (6144UL * 48000UL) + (output->frequency >> 1); + wI2SFreq /= output->frequency; + + if ( output->wordLength == DRX_I2S_WORDLENGTH_16 ) + { + wI2SFreq *= 2; + } + + WR16( devAddr, AUD_DEM_WR_I2S_CONFIG2__A, wI2SConfig ); + WR16( devAddr, AUD_DSP_WR_I2S_OUT_FS__A, (u16_t) wI2SFreq ); + + /* configure I2S output pads for master or slave mode */ + WR16( devAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY ); + + if (output->mode == DRX_I2S_MODE_MASTER) + { + wI2SPadsDataDa = SIO_PDR_I2S_DA_CFG_MODE__MASTER | + SIO_PDR_I2S_DA_CFG_DRIVE__MASTER; + wI2SPadsDataCl = SIO_PDR_I2S_CL_CFG_MODE__MASTER | + SIO_PDR_I2S_CL_CFG_DRIVE__MASTER; + wI2SPadsDataWs = SIO_PDR_I2S_WS_CFG_MODE__MASTER | + SIO_PDR_I2S_WS_CFG_DRIVE__MASTER; + } + else + { + wI2SPadsDataDa = SIO_PDR_I2S_DA_CFG_MODE__SLAVE | + SIO_PDR_I2S_DA_CFG_DRIVE__SLAVE; + wI2SPadsDataCl = SIO_PDR_I2S_CL_CFG_MODE__SLAVE | + SIO_PDR_I2S_CL_CFG_DRIVE__SLAVE; + wI2SPadsDataWs = SIO_PDR_I2S_WS_CFG_MODE__SLAVE | + SIO_PDR_I2S_WS_CFG_DRIVE__SLAVE; + } + + WR16( devAddr, SIO_PDR_I2S_DA_CFG__A, wI2SPadsDataDa ); + WR16( devAddr, SIO_PDR_I2S_CL_CFG__A, wI2SPadsDataCl ); + WR16( devAddr, SIO_PDR_I2S_WS_CFG__A, wI2SPadsDataWs ); + + WR16( devAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE ); + + + /* all done, store config in data structure */ + extAttr->audData.i2sdata = *output; + + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; +} + +/*============================================================================*/ +/** +* \brief Get the Automatic Standard Select (ASS) +* and Automatic Sound Change (ASC) +* \param demod instance of demodulator +* \param pointer to pDRXAudAutoSound_t +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AUDCtrlGetCfgAutoSound ( pDRXDemodInstance_t demod, + pDRXCfgAudAutoSound_t autoSound ) +{ + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)NULL; + pDRXJData_t extAttr = (pDRXJData_t)NULL; + + u16_t rModus = 0; + + if ( autoSound == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* power up */ + if ( extAttr->audData.audioIsActive == FALSE ) + { + CHK_ERROR ( PowerUpAud( demod , TRUE ) ); + extAttr->audData.audioIsActive = TRUE; + } + + CHK_ERROR ( AUDGetModus ( demod, &rModus )); + + switch ( rModus & ( AUD_DEM_WR_MODUS_MOD_ASS__M | + AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__M ) ) + { + case AUD_DEM_WR_MODUS_MOD_ASS_OFF | + AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_DISABLED: + case AUD_DEM_WR_MODUS_MOD_ASS_OFF | + AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_ENABLED: + *autoSound = DRX_AUD_AUTO_SOUND_OFF; + break; + case AUD_DEM_WR_MODUS_MOD_ASS_ON | + AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_ENABLED: + *autoSound = DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON; + break; + case AUD_DEM_WR_MODUS_MOD_ASS_ON | + AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_DISABLED: + *autoSound = DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_OFF; + break; + default: + return DRX_STS_ERROR; + } + + + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; +} +/*============================================================================*/ +/** +* \brief Set the Automatic Standard Select (ASS) +* and Automatic Sound Change (ASC) +* \param demod instance of demodulator +* \param pointer to pDRXAudAutoSound_t +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AUDCtrSetlCfgAutoSound ( pDRXDemodInstance_t demod, + pDRXCfgAudAutoSound_t autoSound ) +{ + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)NULL; + pDRXJData_t extAttr = (pDRXJData_t)NULL; + + u16_t rModus = 0; + u16_t wModus = 0; + + if ( autoSound == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* power up */ + if ( extAttr->audData.audioIsActive == FALSE ) + { + CHK_ERROR ( PowerUpAud( demod , TRUE ) ); + extAttr->audData.audioIsActive = TRUE; + } + + + CHK_ERROR ( AUDGetModus ( demod, &rModus )); + + wModus = rModus; + /* clear ASS & ASC bits */ + wModus &= (u16_t)~AUD_DEM_WR_MODUS_MOD_ASS__M; + wModus &= (u16_t)~AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__M; + + switch ( *autoSound ) + { + case DRX_AUD_AUTO_SOUND_OFF: + wModus |= AUD_DEM_WR_MODUS_MOD_ASS_OFF; + wModus |= AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_DISABLED; + break; + case DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON: + wModus |= AUD_DEM_WR_MODUS_MOD_ASS_ON; + wModus |= AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_ENABLED; + break; + case DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_OFF: + wModus |= AUD_DEM_WR_MODUS_MOD_ASS_ON; + wModus |= AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_DISABLED; + break; + default: + return DRX_STS_INVALID_ARG; + } + + if ( wModus != rModus ) + { + WR16( devAddr, AUD_DEM_WR_MODUS__A, wModus ); + } + /* copy to data structure */ + extAttr->audData.autoSound = *autoSound; + + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; +} + +/*============================================================================*/ +/** +* \brief Get the Automatic Standard Select thresholds +* \param demod instance of demodulator +* \param pointer to pDRXAudASSThres_t +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AUDCtrlGetCfgASSThres ( pDRXDemodInstance_t demod, + pDRXCfgAudASSThres_t thres ) +{ + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)NULL; + pDRXJData_t extAttr = (pDRXJData_t)NULL; + + u16_t thresA2 = 0; + u16_t thresBtsc = 0; + u16_t thresNicam = 0; + + if ( thres == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* power up */ + if ( extAttr->audData.audioIsActive == FALSE ) + { + CHK_ERROR ( PowerUpAud( demod , TRUE ) ); + extAttr->audData.audioIsActive = TRUE; + } + + RR16( devAddr , AUD_DEM_RAM_A2_THRSHLD__A, &thresA2 ); + RR16( devAddr , AUD_DEM_RAM_BTSC_THRSHLD__A, &thresBtsc ); + RR16( devAddr , AUD_DEM_RAM_NICAM_THRSHLD__A, &thresNicam ); + + thres->a2 = thresA2; + thres->btsc = thresBtsc; + thres->nicam = thresNicam; + + + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; +} + +/*============================================================================*/ +/** +* \brief Get the Automatic Standard Select thresholds +* \param demod instance of demodulator +* \param pointer to pDRXAudASSThres_t +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AUDCtrlSetCfgASSThres ( pDRXDemodInstance_t demod, + pDRXCfgAudASSThres_t thres ) +{ + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)NULL; + pDRXJData_t extAttr = (pDRXJData_t)NULL; + + if ( thres == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* power up */ + if ( extAttr->audData.audioIsActive == FALSE ) + { + CHK_ERROR ( PowerUpAud( demod , TRUE ) ); + extAttr->audData.audioIsActive = TRUE; + } + + WR16( devAddr , AUD_DEM_WR_A2_THRSHLD__A, thres->a2 ); + WR16( devAddr , AUD_DEM_WR_BTSC_THRSHLD__A, thres->btsc ); + WR16( devAddr , AUD_DEM_WR_NICAM_THRSHLD__A, thres->nicam ); + + /* update DRXK data structure with hardware values */ + extAttr->audData.assThresholds = *thres; + + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; +} + +/*============================================================================*/ +/** +* \brief Get Audio Carrier settings +* \param demod instance of demodulator +* \param pointer to pDRXAudCarrier_t +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AUDCtrlGetCfgCarrier ( pDRXDemodInstance_t demod, + pDRXCfgAudCarriers_t carriers ) +{ + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)NULL; + pDRXJData_t extAttr = (pDRXJData_t)NULL; + + u16_t wModus = 0; + + u16_t dcoAHi = 0; + u16_t dcoALo = 0; + u16_t dcoBHi = 0; + u16_t dcoBLo = 0; + + u32_t valA = 0; + u32_t valB = 0; + + u16_t dcLvlA = 0; + u16_t dcLvlB = 0; + + u16_t cmThesA = 0; + u16_t cmThesB = 0; + + if ( carriers == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* power up */ + if ( extAttr->audData.audioIsActive == FALSE ) + { + CHK_ERROR ( PowerUpAud( demod , TRUE ) ); + extAttr->audData.audioIsActive = TRUE; + } + + CHK_ERROR ( AUDGetModus ( demod, &wModus )); + + /* Behaviour of primary audio channel */ + switch ( wModus & ( AUD_DEM_WR_MODUS_MOD_CM_A__M) ) + { + case AUD_DEM_WR_MODUS_MOD_CM_A_MUTE: + carriers->a.opt = DRX_NO_CARRIER_MUTE; + break; + case AUD_DEM_WR_MODUS_MOD_CM_A_NOISE: + carriers->a.opt = DRX_NO_CARRIER_NOISE; + break; + default: + return DRX_STS_ERROR; + break; + } + + /* Behaviour of secondary audio channel */ + switch ( wModus & ( AUD_DEM_WR_MODUS_MOD_CM_B__M) ) + { + case AUD_DEM_WR_MODUS_MOD_CM_B_MUTE: + carriers->b.opt = DRX_NO_CARRIER_MUTE; + break; + case AUD_DEM_WR_MODUS_MOD_CM_B_NOISE: + carriers->b.opt = DRX_NO_CARRIER_NOISE; + break; + default: + return DRX_STS_ERROR; + break; + } + + /* frequency adjustment for primary & secondary audio channel */ + RR16( devAddr, AUD_DEM_RAM_DCO_A_HI__A, &dcoAHi ); + RR16( devAddr, AUD_DEM_RAM_DCO_A_LO__A, &dcoALo ); + RR16( devAddr, AUD_DEM_RAM_DCO_B_HI__A, &dcoBHi ); + RR16( devAddr, AUD_DEM_RAM_DCO_B_LO__A, &dcoBLo ); + + valA = ( ( (u32_t) dcoAHi) << 12 ) | ( (u32_t) dcoALo & 0xFFF ); + valB = ( ( (u32_t) dcoBHi) << 12 ) | ( (u32_t) dcoBLo & 0xFFF ); + + /* Multiply by 20250 * 1>>24 ~= 2 / 1657 */ + carriers->a.dco = DRX_S24TODRXFREQ( valA ) * 2L / 1657L; + carriers->b.dco = DRX_S24TODRXFREQ( valB ) * 2L / 1657L; + + /* DC level of the incoming FM signal on the primary + & seconday sound channel */ + RR16( devAddr, AUD_DSP_RD_FM_DC_LEVEL_A__A, &dcLvlA ); + RR16( devAddr, AUD_DSP_RD_FM_DC_LEVEL_B__A, &dcLvlB ); + + /* offset (kHz) = (dcLvl / 322) */ + carriers->a.shift = ( DRX_U16TODRXFREQ( dcLvlA ) / 322L ); + carriers->b.shift = ( DRX_U16TODRXFREQ( dcLvlB ) / 322L ); + + /* Carrier detetcion threshold for primary & secondary channel */ + RR16( devAddr, AUD_DEM_RAM_CM_A_THRSHLD__A, &cmThesA); + RR16( devAddr, AUD_DEM_RAM_CM_B_THRSHLD__A, &cmThesB); + + carriers->a.thres = cmThesA; + carriers->b.thres = cmThesB; + + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; +} + +/*============================================================================*/ +/** +* \brief Set Audio Carrier settings +* \param demod instance of demodulator +* \param pointer to pDRXAudCarrier_t +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AUDCtrlSetCfgCarrier ( pDRXDemodInstance_t demod, + pDRXCfgAudCarriers_t carriers ) +{ + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)NULL; + pDRXJData_t extAttr = (pDRXJData_t)NULL; + + u16_t wModus = 0; + u16_t rModus = 0; + + u16_t dcoAHi = 0; + u16_t dcoALo = 0; + u16_t dcoBHi = 0; + u16_t dcoBLo = 0; + + s32_t valA = 0; + s32_t valB = 0; + + if ( carriers == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* power up */ + if ( extAttr->audData.audioIsActive == FALSE ) + { + CHK_ERROR ( PowerUpAud( demod , TRUE ) ); + extAttr->audData.audioIsActive = TRUE; + } + + + CHK_ERROR ( AUDGetModus ( demod, &rModus )); + + + wModus = rModus; + wModus &= (u16_t)~AUD_DEM_WR_MODUS_MOD_CM_A__M; + /* Behaviour of primary audio channel */ + switch ( carriers->a.opt ) + { + case DRX_NO_CARRIER_MUTE: + wModus |= AUD_DEM_WR_MODUS_MOD_CM_A_MUTE; + break; + case DRX_NO_CARRIER_NOISE: + wModus |= AUD_DEM_WR_MODUS_MOD_CM_A_NOISE; + break; + default: + return DRX_STS_INVALID_ARG; + break; + } + + /* Behaviour of secondary audio channel */ + wModus &= (u16_t)~AUD_DEM_WR_MODUS_MOD_CM_B__M; + switch ( carriers->b.opt ) + { + case DRX_NO_CARRIER_MUTE: + wModus |= AUD_DEM_WR_MODUS_MOD_CM_B_MUTE; + break; + case DRX_NO_CARRIER_NOISE: + wModus |= AUD_DEM_WR_MODUS_MOD_CM_B_NOISE; + break; + default: + return DRX_STS_INVALID_ARG; + break; + } + + /* now update the modus register */ + if ( wModus != rModus) + { + WR16( devAddr, AUD_DEM_WR_MODUS__A, wModus ); + } + + /* frequency adjustment for primary & secondary audio channel */ + valA = (s32_t) ( ( carriers->a.dco ) * 1657L / 2); + valB = (s32_t) ( ( carriers->b.dco ) * 1657L / 2); + + dcoAHi = (u16_t) ( ( valA >> 12 ) & 0xFFF ); + dcoALo = (u16_t) ( valA & 0xFFF ); + dcoBHi = (u16_t) ( ( valB >> 12 ) & 0xFFF ); + dcoBLo = (u16_t) ( valB & 0xFFF ); + + WR16( devAddr, AUD_DEM_WR_DCO_A_HI__A, dcoAHi ); + WR16( devAddr, AUD_DEM_WR_DCO_A_LO__A, dcoALo ); + WR16( devAddr, AUD_DEM_WR_DCO_B_HI__A, dcoBHi ); + WR16( devAddr, AUD_DEM_WR_DCO_B_LO__A, dcoBLo ); + + /* Carrier detetcion threshold for primary & secondary channel */ + WR16( devAddr, AUD_DEM_WR_CM_A_THRSHLD__A, carriers->a.thres); + WR16( devAddr, AUD_DEM_WR_CM_B_THRSHLD__A, carriers->b.thres); + + /* update DRXK data structure */ + extAttr->audData.carriers = *carriers; + + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; +} + +/*============================================================================*/ +/** +* \brief Get I2S Source, I2S matrix and FM matrix +* \param demod instance of demodulator +* \param pointer to pDRXAudmixer_t +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AUDCtrlGetCfgMixer ( pDRXDemodInstance_t demod, + pDRXCfgAudMixer_t mixer ) +{ + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)NULL; + pDRXJData_t extAttr = (pDRXJData_t)NULL; + + u16_t srcI2SMatr = 0; + u16_t fmMatr = 0; + + if ( mixer == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* power up */ + if ( extAttr->audData.audioIsActive == FALSE ) + { + CHK_ERROR ( PowerUpAud( demod , TRUE ) ); + extAttr->audData.audioIsActive = TRUE; + } + + /* Source Selctor */ + RR16( devAddr, AUD_DSP_WR_SRC_I2S_MATR__A, &srcI2SMatr); + + switch ( srcI2SMatr & AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__M ) + { + case AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_MONO: + mixer->sourceI2S = DRX_AUD_SRC_MONO; + break; + case AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_AB: + mixer->sourceI2S = DRX_AUD_SRC_STEREO_OR_AB; + break; + case AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_A: + mixer->sourceI2S = DRX_AUD_SRC_STEREO_OR_A; + break; + case AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_B: + mixer->sourceI2S = DRX_AUD_SRC_STEREO_OR_B; + break; + default: + return DRX_STS_ERROR; + } + + /* Matrix */ + switch ( srcI2SMatr & AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__M ) + { + case AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_MONO: + mixer->matrixI2S = DRX_AUD_I2S_MATRIX_MONO; + break; + case AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_STEREO: + mixer->matrixI2S = DRX_AUD_I2S_MATRIX_STEREO; + break; + case AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_SOUND_A: + mixer->matrixI2S = DRX_AUD_I2S_MATRIX_A_MONO; + break; + case AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_SOUND_B: + mixer->matrixI2S = DRX_AUD_I2S_MATRIX_B_MONO; + break; + default: + return DRX_STS_ERROR; + } + + /* FM Matrix */ + RR16( devAddr, AUD_DEM_WR_FM_MATRIX__A, &fmMatr ); + switch ( fmMatr & AUD_DEM_WR_FM_MATRIX__M ) + { + case AUD_DEM_WR_FM_MATRIX_NO_MATRIX: + mixer->matrixFm = DRX_AUD_FM_MATRIX_NO_MATRIX; + break; + case AUD_DEM_WR_FM_MATRIX_GERMAN_MATRIX: + mixer->matrixFm = DRX_AUD_FM_MATRIX_GERMAN; + break; + case AUD_DEM_WR_FM_MATRIX_KOREAN_MATRIX: + mixer->matrixFm = DRX_AUD_FM_MATRIX_KOREAN; + break; + case AUD_DEM_WR_FM_MATRIX_SOUND_A: + mixer->matrixFm = DRX_AUD_FM_MATRIX_SOUND_A; + break; + case AUD_DEM_WR_FM_MATRIX_SOUND_B: + mixer->matrixFm = DRX_AUD_FM_MATRIX_SOUND_B; + break; + default: + return DRX_STS_ERROR; + } + + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; +} + +/*============================================================================*/ +/** +* \brief Set I2S Source, I2S matrix and FM matrix +* \param demod instance of demodulator +* \param pointer to DRXAudmixer_t +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AUDCtrlSetCfgMixer ( pDRXDemodInstance_t demod, + pDRXCfgAudMixer_t mixer ) + { + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)NULL; + pDRXJData_t extAttr = (pDRXJData_t)NULL; + + u16_t srcI2SMatr = 0; + u16_t fmMatr = 0; + + if ( mixer == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* power up */ + if ( extAttr->audData.audioIsActive == FALSE ) + { + CHK_ERROR ( PowerUpAud( demod , TRUE ) ); + extAttr->audData.audioIsActive = TRUE; + } + + /* Source Selctor */ + RR16( devAddr, AUD_DSP_WR_SRC_I2S_MATR__A, &srcI2SMatr); + srcI2SMatr &= (u16_t)~AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__M; + + switch (mixer->sourceI2S) + { + case DRX_AUD_SRC_MONO: + srcI2SMatr |= AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_MONO; + break; + case DRX_AUD_SRC_STEREO_OR_AB: + srcI2SMatr |= AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_AB; + break; + case DRX_AUD_SRC_STEREO_OR_A: + srcI2SMatr |= AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_A; + break; + case DRX_AUD_SRC_STEREO_OR_B: + srcI2SMatr |= AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_B; + break; + default: + return DRX_STS_INVALID_ARG; + } + + /* Matrix */ + srcI2SMatr &= (u16_t)~AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__M; + switch (mixer->matrixI2S) + { + case DRX_AUD_I2S_MATRIX_MONO: + srcI2SMatr |= AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_MONO; + break; + case DRX_AUD_I2S_MATRIX_STEREO: + srcI2SMatr |= AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_STEREO ; + break; + case DRX_AUD_I2S_MATRIX_A_MONO: + srcI2SMatr |= AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_SOUND_A; + break; + case DRX_AUD_I2S_MATRIX_B_MONO: + srcI2SMatr |= AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_SOUND_B; + break; + default: + return DRX_STS_INVALID_ARG; + } + /* write the result */ + WR16( devAddr, AUD_DSP_WR_SRC_I2S_MATR__A, srcI2SMatr); + + /* FM Matrix */ + RR16( devAddr, AUD_DEM_WR_FM_MATRIX__A, &fmMatr ); + fmMatr &= (u16_t)~AUD_DEM_WR_FM_MATRIX__M; + switch (mixer->matrixFm) + { + case DRX_AUD_FM_MATRIX_NO_MATRIX: + fmMatr |= AUD_DEM_WR_FM_MATRIX_NO_MATRIX; + break; + case DRX_AUD_FM_MATRIX_GERMAN: + fmMatr |= AUD_DEM_WR_FM_MATRIX_GERMAN_MATRIX; + break; + case DRX_AUD_FM_MATRIX_KOREAN: + fmMatr |= AUD_DEM_WR_FM_MATRIX_KOREAN_MATRIX; + break; + case DRX_AUD_FM_MATRIX_SOUND_A: + fmMatr |= AUD_DEM_WR_FM_MATRIX_SOUND_A; + break; + case DRX_AUD_FM_MATRIX_SOUND_B: + fmMatr |= AUD_DEM_WR_FM_MATRIX_SOUND_B; + break; + default: + return DRX_STS_INVALID_ARG; + } + + /* Only write if ASS is off */ + if ( extAttr->audData.autoSound == DRX_AUD_AUTO_SOUND_OFF ) + { + WR16( devAddr, AUD_DEM_WR_FM_MATRIX__A, fmMatr ); + } + + /* update the data structure with hardware state */ + extAttr->audData.mixer = *mixer; + + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; +} + +/*============================================================================*/ +/** +* \brief Set AV Sync settings +* \param demod instance of demodulator +* \param pointer to DRXICfgAVSync_t +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AUDCtrlSetCfgAVSync ( pDRXDemodInstance_t demod, + pDRXCfgAudAVSync_t avSync ) +{ + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)NULL; + pDRXJData_t extAttr = (pDRXJData_t)NULL; + + u16_t wAudVidSync = 0; + + if ( avSync == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* power up */ + if ( extAttr->audData.audioIsActive == FALSE ) + { + CHK_ERROR ( PowerUpAud( demod , TRUE ) ); + extAttr->audData.audioIsActive = TRUE; + } + + /* audio/video synchronisation */ + RR16( devAddr, AUD_DSP_WR_AV_SYNC__A, &wAudVidSync ); + + wAudVidSync &= (u16_t)~AUD_DSP_WR_AV_SYNC_AV_ON__M; + + if ( *avSync == DRX_AUD_AVSYNC_OFF ) + { + wAudVidSync |= AUD_DSP_WR_AV_SYNC_AV_ON_DISABLE; + } + else + { + wAudVidSync |= AUD_DSP_WR_AV_SYNC_AV_ON_ENABLE; + } + + wAudVidSync &= (u16_t)~AUD_DSP_WR_AV_SYNC_AV_STD_SEL__M; + + switch ( *avSync ) + { + case DRX_AUD_AVSYNC_NTSC: + wAudVidSync |= AUD_DSP_WR_AV_SYNC_AV_STD_SEL_NTSC; + break; + case DRX_AUD_AVSYNC_MONOCHROME: + wAudVidSync |= AUD_DSP_WR_AV_SYNC_AV_STD_SEL_MONOCHROME; + break; + case DRX_AUD_AVSYNC_PAL_SECAM: + wAudVidSync |= AUD_DSP_WR_AV_SYNC_AV_STD_SEL_PAL_SECAM; + break; + case DRX_AUD_AVSYNC_OFF: + /* OK */ + break; + default: + return DRX_STS_INVALID_ARG; + } + + WR16( devAddr, AUD_DSP_WR_AV_SYNC__A, wAudVidSync ); + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; +} + +/*============================================================================*/ +/** +* \brief Get AV Sync settings +* \param demod instance of demodulator +* \param pointer to DRXICfgAVSync_t +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AUDCtrlGetCfgAVSync ( pDRXDemodInstance_t demod, + pDRXCfgAudAVSync_t avSync ) +{ + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)NULL; + pDRXJData_t extAttr = (pDRXJData_t)NULL; + + u16_t wAudVidSync = 0; + + if ( avSync == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* power up */ + if ( extAttr->audData.audioIsActive == FALSE ) + { + CHK_ERROR ( PowerUpAud( demod , TRUE ) ); + extAttr->audData.audioIsActive = TRUE; + } + + /* audio/video synchronisation */ + RR16( devAddr, AUD_DSP_WR_AV_SYNC__A, &wAudVidSync ); + + if ( ( wAudVidSync & AUD_DSP_WR_AV_SYNC_AV_ON__M ) == + AUD_DSP_WR_AV_SYNC_AV_ON_DISABLE ) + { + *avSync = DRX_AUD_AVSYNC_OFF; + return DRX_STS_OK; + } + + switch ( wAudVidSync & AUD_DSP_WR_AV_SYNC_AV_STD_SEL__M ) + { + case AUD_DSP_WR_AV_SYNC_AV_STD_SEL_NTSC: + *avSync = DRX_AUD_AVSYNC_NTSC; + break; + case AUD_DSP_WR_AV_SYNC_AV_STD_SEL_MONOCHROME: + *avSync = DRX_AUD_AVSYNC_MONOCHROME; + break; + case AUD_DSP_WR_AV_SYNC_AV_STD_SEL_PAL_SECAM: + *avSync = DRX_AUD_AVSYNC_PAL_SECAM; + break; + default: + return DRX_STS_ERROR; + } + + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; +} + +/*============================================================================*/ +/** +* \brief Get deviation mode +* \param demod instance of demodulator +* \param pointer to DRXCfgAudDeviation_t +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AUDCtrlGetCfgDev ( pDRXDemodInstance_t demod, + pDRXCfgAudDeviation_t dev ) +{ + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)NULL; + pDRXJData_t extAttr = (pDRXJData_t)NULL; + + u16_t rModus = 0; + + + if ( dev == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + extAttr = (pDRXJData_t)demod->myExtAttr; + devAddr = demod->myI2CDevAddr; + + CHK_ERROR ( AUDGetModus ( demod, &rModus )); + + switch ( rModus & AUD_DEM_WR_MODUS_MOD_HDEV_A__M) + { + case AUD_DEM_WR_MODUS_MOD_HDEV_A_NORMAL: + *dev = DRX_AUD_DEVIATION_NORMAL; + break; + case AUD_DEM_WR_MODUS_MOD_HDEV_A_HIGH_DEVIATION: + *dev = DRX_AUD_DEVIATION_HIGH; + break; + default: + return DRX_STS_ERROR; + } + + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; +} + +/*============================================================================*/ +/** +* \brief Get deviation mode +* \param demod instance of demodulator +* \param pointer to DRXCfgAudDeviation_t +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AUDCtrlSetCfgDev ( pDRXDemodInstance_t demod, + pDRXCfgAudDeviation_t dev ) +{ + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)NULL; + pDRXJData_t extAttr = (pDRXJData_t)NULL; + + u16_t wModus = 0; + u16_t rModus = 0; + + if ( dev == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + extAttr = (pDRXJData_t)demod->myExtAttr; + devAddr = demod->myI2CDevAddr; + + CHK_ERROR ( AUDGetModus ( demod, &rModus )); + + wModus = rModus; + + wModus &= (u16_t)~AUD_DEM_WR_MODUS_MOD_HDEV_A__M; + + switch ( *dev ) + { + case DRX_AUD_DEVIATION_NORMAL: + wModus |= AUD_DEM_WR_MODUS_MOD_HDEV_A_NORMAL; + break; + case DRX_AUD_DEVIATION_HIGH: + wModus |= AUD_DEM_WR_MODUS_MOD_HDEV_A_HIGH_DEVIATION; + break; + default: + return DRX_STS_INVALID_ARG; + } + + /* now update the modus register */ + if ( wModus != rModus) + { + WR16( devAddr, AUD_DEM_WR_MODUS__A, wModus ); + } + /* store in drxk data struct */ + extAttr->audData.deviation = *dev; + + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; +} + + +/*============================================================================*/ +/** +* \brief Get Prescaler settings +* \param demod instance of demodulator +* \param pointer to DRXCfgAudPrescale_t +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AUDCtrlGetCfgPrescale( pDRXDemodInstance_t demod, + pDRXCfgAudPrescale_t presc ) +{ + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)NULL; + pDRXJData_t extAttr = (pDRXJData_t)NULL; + + u16_t rMaxFMDeviation = 0; + u16_t rNicamPrescaler = 0; + + if ( presc == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* power up */ + if ( extAttr->audData.audioIsActive == FALSE ) + { + CHK_ERROR ( PowerUpAud( demod , TRUE ) ); + extAttr->audData.audioIsActive = TRUE; + } + + /* read register data */ + RR16( devAddr, AUD_DSP_WR_NICAM_PRESC__A, &rNicamPrescaler ); + RR16( devAddr, AUD_DSP_WR_FM_PRESC__A, &rMaxFMDeviation ); + + /* calculate max FM deviation */ + rMaxFMDeviation >>= AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__B; + if ( rMaxFMDeviation > 0 ) + { + presc->fmDeviation = 3600UL + (rMaxFMDeviation >> 1); + presc->fmDeviation /= rMaxFMDeviation; + } + else + { + presc->fmDeviation = 380; /* kHz */ + } + + /* calculate NICAM gain from pre-scaler */ + /* + nicamGain = 20 * ( log10( preScaler / 16) ) + = ( 100log10( preScaler ) - 100log10( 16 ) ) / 5 + + because Log10Times100() cannot return negative numbers + = ( 100log10( 10 * preScaler ) - 100log10( 10 * 16) ) / 5 + + + for 0.1dB resolution: + + nicamGain = 200 * ( log10( preScaler / 16) ) + = 2 * ( 100log10( 10 * preScaler ) - 100log10( 10 * 16) ) + = ( 100log10( 10 * preScaler^2 ) - 100log10( 10 * 16^2 ) ) + + + */ + rNicamPrescaler >>= 8; + if ( rNicamPrescaler <= 1 ) + { + presc->nicamGain = -241; + } + else + { + + presc->nicamGain = (s16_t)( ( (s32_t) + ( Log10Times100( 10 * rNicamPrescaler * + rNicamPrescaler ) ) - + (s32_t) + ( Log10Times100( 10 * 16 * 16 ) ) ) ); + } + + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; +} + + +/*============================================================================*/ +/** +* \brief Set Prescaler settings +* \param demod instance of demodulator +* \param pointer to DRXCfgAudPrescale_t +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AUDCtrlSetCfgPrescale( pDRXDemodInstance_t demod, + pDRXCfgAudPrescale_t presc ) +{ + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)NULL; + pDRXJData_t extAttr = (pDRXJData_t)NULL; + + u16_t wMaxFMDeviation = 0; + u16_t nicamPrescaler; + + if ( presc == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* power up */ + if ( extAttr->audData.audioIsActive == FALSE ) + { + CHK_ERROR ( PowerUpAud( demod , TRUE ) ); + extAttr->audData.audioIsActive = TRUE; + } + + /* setting of max FM deviation */ + wMaxFMDeviation = (u16_t)(Frac (3600UL, presc->fmDeviation, 0)); + wMaxFMDeviation <<= AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__B; + if ( wMaxFMDeviation >= AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_28_KHZ_FM_DEVIATION ) + { + wMaxFMDeviation = AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_28_KHZ_FM_DEVIATION; + } + + /* NICAM Prescaler */ + if( ( presc->nicamGain >= -241) && ( presc->nicamGain <= 180) ) + { + /* calculation + + prescaler = 16 * 10^( GdB / 20 ) + + minval of GdB = -20*log( 16 ) = -24.1dB + + negative numbers not allowed for dB2LinTimes100, so + + prescaler = 16 * 10^( GdB / 20 ) + = 10^( (GdB / 20) + log10(16) ) + = 10^( (GdB + 20log10(16)) / 20 ) + + in 0.1dB + + = 10^( G0.1dB + 200log10(16)) / 200 ) + + */ + nicamPrescaler = (u16_t) + ( ( dB2LinTimes100( presc->nicamGain + 241UL ) + 50UL ) / 100UL ); + + /* clip result */ + if ( nicamPrescaler > 127 ) + { + nicamPrescaler = 127; + } + + /* shift before writing to register */ + nicamPrescaler <<= 8; + } + else + { + return(DRX_STS_INVALID_ARG); + } + /* end of setting NICAM Prescaler */ + + WR16( devAddr, AUD_DSP_WR_NICAM_PRESC__A, nicamPrescaler ); + WR16( devAddr, AUD_DSP_WR_FM_PRESC__A, wMaxFMDeviation ); + + extAttr->audData.prescale = *presc; + + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; +} + +/*============================================================================*/ +/** +* \brief Beep +* \param demod instance of demodulator +* \param pointer to DRXAudBeep_t +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AUDCtrlBeep ( pDRXDemodInstance_t demod, + pDRXAudBeep_t beep ) +{ + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)NULL; + pDRXJData_t extAttr = (pDRXJData_t)NULL; + + u16_t theBeep = 0; + u16_t volume = 0; + u32_t frequency = 0; + + + if ( beep == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* power up */ + if ( extAttr->audData.audioIsActive == FALSE ) + { + CHK_ERROR ( PowerUpAud( demod , TRUE ) ); + extAttr->audData.audioIsActive = TRUE; + } + + if (( beep->volume > 0 ) || ( beep->volume < -127 )) + { + return DRX_STS_INVALID_ARG; + } + + if ( beep->frequency > 3000 ) + { + return DRX_STS_INVALID_ARG; + } + + volume = (u16_t)beep->volume + 127; + theBeep |= volume << AUD_DSP_WR_BEEPER_BEEP_VOLUME__B; + + + frequency = ( (u32_t) beep->frequency ) * 23 / 500 ; + if ( frequency > AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__M ) + { + frequency = AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__M; + } + theBeep |= (u16_t) frequency; + + if ( beep->mute == TRUE ) + { + theBeep = 0; + } + + WR16( devAddr, AUD_DSP_WR_BEEPER__A, theBeep); + + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; +} + +/*============================================================================*/ +/** +* \brief Set an audio standard +* \param demod instance of demodulator +* \param pointer to DRXAudStandard_t +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AUDCtrlSetStandard ( pDRXDemodInstance_t demod, + pDRXAudStandard_t standard ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + DRXStandard_t currentStandard = DRX_STANDARD_UNKNOWN; + + u16_t wStandard = 0; + u16_t wModus = 0; + u16_t rModus = 0; + + Bool_t muteBuffer = FALSE; + s16_t volumeBuffer = 0; + u16_t wVolume = 0; + + if ( standard == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + devAddr = (pI2CDeviceAddr_t)demod->myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* power up */ + if ( extAttr->audData.audioIsActive == FALSE ) + { + CHK_ERROR ( PowerUpAud( demod , FALSE ) ); + extAttr->audData.audioIsActive = TRUE; + } + + + /* reset RDS data availability flag */ + extAttr->audData.rdsDataPresent = FALSE; + + + /* we need to mute from here to avoid noise during standard switching */ + muteBuffer = extAttr->audData.volume.mute; + volumeBuffer = extAttr->audData.volume.volume; + + extAttr->audData.volume.mute = TRUE; + /* restore data structure from DRX ExtAttr, call volume first to mute */ + CHK_ERROR ( AUDCtrlSetCfgVolume + ( demod, &extAttr->audData.volume ) ); + CHK_ERROR ( AUDCtrlSetCfgCarrier + ( demod, &extAttr->audData.carriers ) ); + CHK_ERROR ( AUDCtrlSetCfgASSThres + ( demod, &extAttr->audData.assThresholds ) ); + CHK_ERROR ( AUDCtrSetlCfgAutoSound + ( demod, &extAttr->audData.autoSound ) ); + CHK_ERROR ( AUDCtrlSetCfgMixer + ( demod, &extAttr->audData.mixer ) ); + CHK_ERROR ( AUDCtrlSetCfgAVSync + ( demod, &extAttr->audData.avSync ) ); + CHK_ERROR ( AUDCtrlSetCfgOutputI2S + ( demod, &extAttr->audData.i2sdata ) ); + + /* get prescaler from presets */ + CHK_ERROR ( AUDCtrlSetCfgPrescale + ( demod, &extAttr->audData.prescale) ); + + CHK_ERROR ( AUDGetModus ( demod, &rModus )); + + wModus = rModus; + + switch ( *standard ) + { + case DRX_AUD_STANDARD_AUTO: + wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_AUTO; + break; + case DRX_AUD_STANDARD_BTSC: + wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_BTSC_STEREO; + if (extAttr->audData.btscDetect == DRX_BTSC_MONO_AND_SAP) + { + wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_BTSC_SAP; + } + break; + case DRX_AUD_STANDARD_A2: + wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_M_KOREA; + break; + case DRX_AUD_STANDARD_EIAJ: + wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_EIA_J; + break; + case DRX_AUD_STANDARD_FM_STEREO: + wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_FM_RADIO; + break; + case DRX_AUD_STANDARD_BG_FM: + wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_BG_FM; + break; + case DRX_AUD_STANDARD_D_K1: + wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K1; + break; + case DRX_AUD_STANDARD_D_K2: + wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K2; + break; + case DRX_AUD_STANDARD_D_K3: + wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K3; + break; + case DRX_AUD_STANDARD_BG_NICAM_FM: + wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_BG_NICAM_FM; + break; + case DRX_AUD_STANDARD_L_NICAM_AM: + wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_L_NICAM_AM; + break; + case DRX_AUD_STANDARD_I_NICAM_FM: + wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_I_NICAM_FM; + break; + case DRX_AUD_STANDARD_D_K_NICAM_FM: + wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K_NICAM_FM; + break; + case DRX_AUD_STANDARD_UNKNOWN: + wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_AUTO; + break; + default: + return DRX_STS_ERROR; + } + + if ( *standard == DRX_AUD_STANDARD_AUTO ) + { + /* we need the current standard here */ + currentStandard = extAttr->standard; + + + wModus &= (u16_t)~AUD_DEM_WR_MODUS_MOD_6_5MHZ__M; + + if ( ( currentStandard == DRX_STANDARD_PAL_SECAM_L ) || + ( currentStandard == DRX_STANDARD_PAL_SECAM_LP ) ) + { + wModus |= (AUD_DEM_WR_MODUS_MOD_6_5MHZ_SECAM); + } + else + { + wModus |= (AUD_DEM_WR_MODUS_MOD_6_5MHZ_D_K); + } + + wModus &= (u16_t)~AUD_DEM_WR_MODUS_MOD_4_5MHZ__M; + if ( currentStandard == DRX_STANDARD_NTSC ) + { + wModus |= ( AUD_DEM_WR_MODUS_MOD_4_5MHZ_M_BTSC); + + } + else /* non USA, ignore standard M to save time */ + { + wModus |= ( AUD_DEM_WR_MODUS_MOD_4_5MHZ_CHROMA); + } + + + } + + wModus &= (u16_t)~AUD_DEM_WR_MODUS_MOD_FMRADIO__M; + + /* just get hardcoded deemphasis and activate here */ + if ( extAttr->audData.deemph == DRX_AUD_FM_DEEMPH_50US ) + { + wModus |= ( AUD_DEM_WR_MODUS_MOD_FMRADIO_EU_50U); + } + else + { + wModus |= ( AUD_DEM_WR_MODUS_MOD_FMRADIO_US_75U); + } + + wModus &= (u16_t)~AUD_DEM_WR_MODUS_MOD_BTSC__M; + if( extAttr->audData.btscDetect == DRX_BTSC_STEREO ) + { + wModus |= ( AUD_DEM_WR_MODUS_MOD_BTSC_BTSC_STEREO); + } + else /* DRX_BTSC_MONO_AND_SAP */ + { + wModus |= ( AUD_DEM_WR_MODUS_MOD_BTSC_BTSC_SAP); + } + + if ( wModus != rModus) + { + WR16( devAddr, AUD_DEM_WR_MODUS__A, wModus ); + } + + WR16( devAddr, AUD_DEM_WR_STANDARD_SEL__A, wStandard ); + + /**************************************************************************/ + /* NOT calling AUDCtrlSetCfgVolume to avoid interfering standard */ + /* detection, need to keep things very minimal here, but keep audio */ + /* buffers intact */ + /**************************************************************************/ + extAttr->audData.volume.mute = muteBuffer; + if ( extAttr->audData.volume.mute == FALSE ) + { + wVolume |= (u16_t) ( ( volumeBuffer + AUD_VOLUME_ZERO_DB ) << + AUD_DSP_WR_VOLUME_VOL_MAIN__B ); + WR16( devAddr, AUD_DSP_WR_VOLUME__A, wVolume ); + } + + /* write standard selected */ + extAttr->audData.audioStandard = *standard; + + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; +} + +/*============================================================================*/ +/** +* \brief Get the current audio standard +* \param demod instance of demodulator +* \param pointer to DRXAudStandard_t +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AUDCtrlGetStandard ( pDRXDemodInstance_t demod, + pDRXAudStandard_t standard ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + + u16_t rData = 0; + + if ( standard == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + extAttr = (pDRXJData_t)demod->myExtAttr; + devAddr = (pI2CDeviceAddr_t)demod->myI2CDevAddr; + + /* power up */ + if ( extAttr->audData.audioIsActive == FALSE ) + { + CHK_ERROR ( PowerUpAud( demod , TRUE ) ); + extAttr->audData.audioIsActive = TRUE; + } + + *standard = DRX_AUD_STANDARD_UNKNOWN; + + RR16( devAddr, AUD_DEM_RD_STANDARD_RES__A, &rData ); + + /* return OK if the detection is not ready yet */ + if ( rData >= + AUD_DEM_RD_STANDARD_RES_STD_RESULT_DETECTION_STILL_ACTIVE ) + { + *standard = DRX_AUD_STANDARD_NOT_READY; + return DRX_STS_OK; + } + + /* detection done, return correct standard */ + switch ( rData ) + { + /* no standard detected */ + case AUD_DEM_RD_STANDARD_RES_STD_RESULT_NO_SOUND_STANDARD: + *standard = DRX_AUD_STANDARD_UNKNOWN; + break; + /* standard is KOREA(A2) */ + case AUD_DEM_RD_STANDARD_RES_STD_RESULT_NTSC_M_DUAL_CARRIER_FM: + *standard = DRX_AUD_STANDARD_A2; + break; + /* standard is EIA-J (Japan) */ + case AUD_DEM_RD_STANDARD_RES_STD_RESULT_NTSC_EIA_J: + *standard = DRX_AUD_STANDARD_EIAJ; + break; + /* standard is BTSC-stereo */ + case AUD_DEM_RD_STANDARD_RES_STD_RESULT_BTSC_STEREO: + *standard = DRX_AUD_STANDARD_BTSC; + break; + /* standard is BTSC-mono (SAP) */ + case AUD_DEM_RD_STANDARD_RES_STD_RESULT_BTSC_MONO_SAP: + *standard = DRX_AUD_STANDARD_BTSC; + break; + /* standard is FM radio */ + case AUD_DEM_RD_STANDARD_RES_STD_RESULT_FM_RADIO: + *standard = DRX_AUD_STANDARD_FM_STEREO; + break; + /* standard is BG FM */ + case AUD_DEM_RD_STANDARD_RES_STD_RESULT_B_G_DUAL_CARRIER_FM: + *standard = DRX_AUD_STANDARD_BG_FM; + break; + /* standard is DK-1 FM */ + case AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K1_DUAL_CARRIER_FM: + *standard = DRX_AUD_STANDARD_D_K1; + break; + /* standard is DK-2 FM */ + case AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K2_DUAL_CARRIER_FM: + *standard = DRX_AUD_STANDARD_D_K2; + break; + /* standard is DK-3 FM */ + case AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K3_DUAL_CARRIER_FM: + *standard = DRX_AUD_STANDARD_D_K3; + break; + /* standard is BG-NICAM FM */ + case AUD_DEM_RD_STANDARD_RES_STD_RESULT_B_G_NICAM_FM: + *standard = DRX_AUD_STANDARD_BG_NICAM_FM; + break; + /* standard is L-NICAM AM */ + case AUD_DEM_RD_STANDARD_RES_STD_RESULT_L_NICAM_AM: + *standard = DRX_AUD_STANDARD_L_NICAM_AM; + break; + /* standard is I-NICAM FM */ + case AUD_DEM_RD_STANDARD_RES_STD_RESULT_I_NICAM_FM: + *standard = DRX_AUD_STANDARD_I_NICAM_FM; + break; + /* standard is DK-NICAM FM */ + case AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K_NICAM_FM: + *standard = DRX_AUD_STANDARD_D_K_NICAM_FM; + break; + default: + *standard = DRX_AUD_STANDARD_UNKNOWN; + } + + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; + +} + + +/*============================================================================*/ +/** +* \brief Retreive lock status in case of FM standard +* \param demod instance of demodulator +* \param pointer to lock status +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +FmLockStatus( pDRXDemodInstance_t demod, + pDRXLockStatus_t lockStat ) +{ + DRXAudStatus_t status; + + /* Check detection of audio carriers */ + CHK_ERROR( AUDCtrlGetCarrierDetectStatus ( demod, &status ) ); + + /* locked if either primary or secondary carrier is detected */ + if ( ( status.carrierA == TRUE ) || + ( status.carrierB == TRUE ) ) + { + *lockStat = DRX_LOCKED; + } else { + *lockStat = DRX_NOT_LOCKED; + } + + return (DRX_STS_OK); + +rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================*/ +/** +* \brief retreive signal quality in case of FM standard +* \param demod instance of demodulator +* \param pointer to signal quality +* \return DRXStatus_t. +* +* Only the quality indicator field is will be supplied. +* This will either be 0% or 100%, nothing in between. +* +*/ +static DRXStatus_t +FmSigQuality( pDRXDemodInstance_t demod, + pDRXSigQuality_t sigQuality ) +{ + DRXLockStatus_t lockStatus = DRX_NOT_LOCKED; + + CHK_ERROR( FmLockStatus( demod, &lockStatus ) ); + if ( lockStatus == DRX_LOCKED ) + { + sigQuality->indicator = 100; + } else { + sigQuality->indicator = 0; + } + + return (DRX_STS_OK); + +rw_error: + return (DRX_STS_ERROR); +} + +#endif + + +/*===========================================================================*/ +/*== END AUDIO DATAPATH FUNCTIONS ==*/ +/*===========================================================================*/ + +/*============================================================================*/ +/*============================================================================*/ +/*== OOB DATAPATH FUNCTIONS ==*/ +/*============================================================================*/ +/*============================================================================*/ +#ifndef DRXJ_DIGITAL_ONLY +/** +* \fn DRXStatus_t GetOOBLockStatus () +* \brief Get OOB lock status. +* \param devAddr I2C address + \ oobLock OOB lock status. +* \return DRXStatus_t. +* +* Gets OOB lock status +* +*/ +static DRXStatus_t +GetOOBLockStatus( pDRXDemodInstance_t demod, + pI2CDeviceAddr_t devAddr, + pDRXLockStatus_t oobLock ) +{ + DRXJSCUCmd_t scuCmd; + u16_t cmdResult[2]; + u16_t OOBLockState; + + *oobLock = DRX_NOT_LOCKED; + + scuCmd.command = SCU_RAM_COMMAND_STANDARD_OOB | + SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK; + scuCmd.resultLen = 2; + scuCmd.result = cmdResult; + scuCmd.parameterLen = 0; + + CHK_ERROR( SCUCommand( devAddr, &scuCmd ) ); + + if ( scuCmd.result[1] < 0x4000 ) + { + /* 0x00 NOT LOCKED */ + *oobLock = DRX_NOT_LOCKED; + } + else if ( scuCmd.result[1] < 0x8000 ) + { + /* 0x40 DEMOD LOCKED */ + *oobLock = DRXJ_OOB_SYNC_LOCK; + } + else if ( scuCmd.result[1] < 0xC000 ) + { + /* 0x80 DEMOD + OOB LOCKED (system lock) */ + OOBLockState = scuCmd.result[1] & 0x00FF; + + if(OOBLockState & 0x0008) + { + *oobLock = DRXJ_OOB_SYNC_LOCK; + } + else if ((OOBLockState & 0x0002) && (OOBLockState & 0x0001)) + { + *oobLock = DRXJ_OOB_AGC_LOCK; + } + } + else + { + /* 0xC0 NEVER LOCKED (system will never be able to lock to the signal) */ + *oobLock = DRX_NEVER_LOCK; + } + + /* *oobLock = scuCmd.result[1]; */ + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/** +* \fn DRXStatus_t GetOOBSymbolRateOffset () +* \brief Get OOB Symbol rate offset. Unit is [ppm] +* \param devAddr I2C address +* \ Symbol Rate Offset OOB parameter. +* \return DRXStatus_t. +* +* Gets OOB frequency offset +* +*/ +static DRXStatus_t +GetOOBSymbolRateOffset( pI2CDeviceAddr_t devAddr, ps32_t SymbolRateOffset ) +{ +/* offset = -{(timingOffset/2^19)*(symbolRate/12,656250MHz)}*10^6 [ppm] */ +/* offset = -{(timingOffset/2^19)*(symbolRate/12656250)}*10^6 [ppm] */ +/* after reconfiguration: */ +/* offset = -{(timingOffset*symbolRate)/(2^19*12656250)}*10^6 [ppm] */ +/* shift symbol rate left by 5 without lossing information */ +/* offset = -{(timingOffset*(symbolRate * 2^-5))/(2^14*12656250)}*10^6 [ppm]*/ +/* shift 10^6 left by 6 without loosing information */ +/* offset = -{(timingOffset*(symbolRate * 2^-5))/(2^8*12656250)}*15625 [ppm]*/ +/* trim 12656250/15625 = 810 */ +/* offset = -{(timingOffset*(symbolRate * 2^-5))/(2^8*810)} [ppm] */ +/* offset = -[(symbolRate * 2^-5)*(timingOffset)/(2^8)]/810 [ppm] */ + s32_t timingOffset = 0; + u32_t unsignedTimingOffset = 0; + s32_t divisionFactor = 810; + u16_t data = 0; + u32_t symbolRate = 0; + Bool_t negative = FALSE; + + *SymbolRateOffset = 0; + /* read data rate */ + SARR16( devAddr, SCU_RAM_ORX_RF_RX_DATA_RATE__A, &data ); + switch(data & SCU_RAM_ORX_RF_RX_DATA_RATE__M) + { + case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC: + case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC: + case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC_ALT: + case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC_ALT: + symbolRate = 1024000;/* bps */ + break; + case SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_REGSPEC: + case SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_INVSPEC: + symbolRate = 772000;/* bps */ + break; + case SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_REGSPEC: + case SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_INVSPEC: + symbolRate = 1544000;/* bps */ + break; + default: + return (DRX_STS_ERROR); + } + + RR16( devAddr, ORX_CON_CTI_DTI_R__A, &data ); + /* convert data to positive and keep information about sign */ + if((data & 0x8000) == 0x8000){ + if(data == 0x8000) + unsignedTimingOffset = 32768; + else + unsignedTimingOffset = 0x00007FFF & (u32_t)(-data); + negative = TRUE; + } + else + unsignedTimingOffset = (u32_t)data; + + symbolRate = symbolRate >> 5; + unsignedTimingOffset = ( unsignedTimingOffset * symbolRate ); + unsignedTimingOffset = Frac( unsignedTimingOffset, 256, FRAC_ROUND ); + unsignedTimingOffset = Frac( unsignedTimingOffset, + divisionFactor, FRAC_ROUND ); + if(negative) + timingOffset = (s32_t)unsignedTimingOffset; + else + timingOffset = -(s32_t)unsignedTimingOffset; + + *SymbolRateOffset = timingOffset; + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/** +* \fn DRXStatus_t GetOOBFreqOffset () +* \brief Get OOB lock status. +* \param devAddr I2C address +* \ freqOffset OOB frequency offset. +* \return DRXStatus_t. +* +* Gets OOB frequency offset +* +*/ +static DRXStatus_t +GetOOBFreqOffset( pDRXDemodInstance_t demod, pDRXFrequency_t freqOffset ) +{ + u16_t data = 0; + u16_t rot = 0; + u16_t symbolRateReg = 0; + u32_t symbolRate = 0; + s32_t coarseFreqOffset = 0; + s32_t fineFreqOffset = 0; + s32_t fineSign = 1; + s32_t coarseSign = 1; + u32_t data64Hi = 0; + u32_t data64Lo = 0; + u32_t tempFreqOffset = 0; + pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t)(NULL); + pI2CDeviceAddr_t devAddr = NULL; + + /* check arguments */ + if ( ( demod == NULL ) || + ( freqOffset == NULL ) ) + { + return DRX_STS_INVALID_ARG; + } + + devAddr = demod -> myI2CDevAddr; + commonAttr = (pDRXCommonAttr_t) demod -> myCommonAttr; + + *freqOffset = 0; + + /* read sign (spectrum inversion) */ + RR16( devAddr, ORX_FWP_IQM_FRQ_W__A, &rot ); + + /* read frequency offset */ + SARR16( devAddr, SCU_RAM_ORX_FRQ_OFFSET__A, &data ); + /* find COARSE frequency offset */ + /* coarseFreqOffset = ( 25312500Hz*FRQ_OFFSET >> 21 ); */ + if (data & 0x8000) + { + data = (0xffff - data + 1); + coarseSign = -1; + } + Mult32 ( data, (commonAttr->sysClockFreq * 1000)/6, &data64Hi, &data64Lo ); + tempFreqOffset = (((data64Lo >> 21) & 0x7ff) | (data64Hi << 11)); + + /* get value in KHz */ + coarseFreqOffset = coarseSign * Frac( tempFreqOffset, 1000, FRAC_ROUND ); /* KHz */ + /* read data rate */ + SARR16( devAddr, SCU_RAM_ORX_RF_RX_DATA_RATE__A, &symbolRateReg ); + switch(symbolRateReg & SCU_RAM_ORX_RF_RX_DATA_RATE__M) + { + case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC: + case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC: + case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC_ALT: + case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC_ALT: + symbolRate = 1024000; + break; + case SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_REGSPEC: + case SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_INVSPEC: + symbolRate = 772000; + break; + case SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_REGSPEC: + case SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_INVSPEC: + symbolRate = 1544000; + break; + default: + return (DRX_STS_ERROR); + } + + /* find FINE frequency offset */ + /* fineFreqOffset = ( (CORRECTION_VALUE*symbolRate) >> 18 ); */ + RR16( devAddr, ORX_CON_CPH_FRQ_R__A, &data ); + /* at least 5 MSB are 0 so first divide with 2^5 without information loss*/ + fineFreqOffset = ( symbolRate >> 5 ); + if (data & 0x8000) + { + fineFreqOffset *= 0xffff - data + 1; /* Hz */ + fineSign = -1; + } else { + fineFreqOffset *= data; /* Hz */ + } + /* Left to divide with 8192 (2^13) */ + fineFreqOffset = Frac( fineFreqOffset, 8192, FRAC_ROUND ); + /* and to divide with 1000 to get KHz*/ + fineFreqOffset = fineSign * Frac( fineFreqOffset, 1000, FRAC_ROUND ); /* KHz */ + + if ( (rot & 0x8000) == 0x8000 ) + *freqOffset = -(coarseFreqOffset + fineFreqOffset); + else + *freqOffset = (coarseFreqOffset + fineFreqOffset); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} +/** +* \fn DRXStatus_t GetOOBFrequency () +* \brief Get OOB frequency (Unit:KHz). +* \param devAddr I2C address +* \ frequency OOB frequency parameters. +* \return DRXStatus_t. +* +* Gets OOB frequency +* +*/ +static DRXStatus_t +GetOOBFrequency( pDRXDemodInstance_t demod, pDRXFrequency_t frequency ) +{ + u16_t data = 0; + DRXFrequency_t freqOffset = 0; + DRXFrequency_t freq = 0; + pI2CDeviceAddr_t devAddr = NULL; + + devAddr = demod -> myI2CDevAddr; + + *frequency = 0;/* KHz */ + + SARR16( devAddr, SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__A, &data ); + + freq = (DRXFrequency_t)((DRXFrequency_t)data * 50 + 50000L); + + CHK_ERROR ( GetOOBFreqOffset ( demod, &freqOffset ) ); + + *frequency = freq + freqOffset; + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} +/** +* \fn DRXStatus_t GetOOBMER () +* \brief Get OOB MER. +* \param devAddr I2C address + \ MER OOB parameter in dB. +* \return DRXStatus_t. +* +* Gets OOB MER. Table for MER is in Programming guide. +* +*/ +static DRXStatus_t +GetOOBMER( pI2CDeviceAddr_t devAddr, pu32_t mer ) +{ + u16_t data = 0; + + *mer = 0; + /* READ MER */ + RR16( devAddr, ORX_EQU_MER_MER_R__A, &data ); + switch (data) + { + case 0:/* fall through */ + case 1: + *mer = 39; + break; + case 2: + *mer = 33; + break; + case 3: + *mer = 29; + break; + case 4: + *mer = 27; + break; + case 5: + *mer = 25; + break; + case 6: + *mer = 23; + break; + case 7: + *mer = 22; + break; + case 8: + *mer = 21; + break; + case 9: + *mer = 20; + break; + case 10: + *mer = 19; + break; + case 11: + *mer = 18; + break; + case 12: + *mer = 17; + break; + case 13:/* fall through */ + case 14: + *mer = 16; + break; + case 15:/* fall through */ + case 16: + *mer = 15; + break; + case 17:/* fall through */ + case 18: + *mer = 14; + break; + case 19:/* fall through */ + case 20: + *mer = 13; + break; + case 21:/* fall through */ + case 22: + *mer = 12; + break; + case 23:/* fall through */ + case 24:/* fall through */ + case 25: + *mer = 11; + break; + case 26:/* fall through */ + case 27:/* fall through */ + case 28: + *mer = 10; + break; + case 29:/* fall through */ + case 30:/* fall through */ + case 31:/* fall through */ + case 32: + *mer = 9; + break; + case 33:/* fall through */ + case 34:/* fall through */ + case 35:/* fall through */ + case 36: + *mer = 8; + break; + case 37:/* fall through */ + case 38:/* fall through */ + case 39:/* fall through */ + case 40: + *mer = 7; + break; + case 41:/* fall through */ + case 42:/* fall through */ + case 43:/* fall through */ + case 44:/* fall through */ + case 45: + *mer = 6; + break; + case 46:/* fall through */ + case 47:/* fall through */ + case 48:/* fall through */ + case 49:/* fall through */ + case 50:/* fall through */ + *mer = 5; + break; + case 51:/* fall through */ + case 52:/* fall through */ + case 53:/* fall through */ + case 54:/* fall through */ + case 55:/* fall through */ + case 56:/* fall through */ + case 57: + *mer = 4; + break; + case 58:/* fall through */ + case 59:/* fall through */ + case 60:/* fall through */ + case 61:/* fall through */ + case 62:/* fall through */ + case 63: + *mer = 0; + break; + default: + *mer = 0; + break; + } + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} +#endif /*#ifndef DRXJ_DIGITAL_ONLY */ + +/** +* \fn DRXStatus_t SetOrxNsuAox() +* \brief Configure OrxNsuAox for OOB +* \param demod instance of demodulator. +* \param active +* \return DRXStatus_t. +*/ +static DRXStatus_t +SetOrxNsuAox ( pDRXDemodInstance_t demod, Bool_t active ) +{ + u16_t data = 0; + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + + extAttr = (pDRXJData_t)demod->myExtAttr; + devAddr = demod -> myI2CDevAddr; + + /* Configure NSU_AOX */ + RR16( devAddr, ORX_NSU_AOX_STDBY_W__A , &data ); + if( !active ) + { + data &= ((~ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON) + & (~ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON) + & (~ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON) + & (~ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON) + & (~ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON) + & (~ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON) + & (~ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON) + & (~ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON) + ); + } + else /* active */ + { + data |= (ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON + | ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON + | ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON + | ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON + | ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON + | ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON + | ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON + | ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON + ); + } + WR16( devAddr, ORX_NSU_AOX_STDBY_W__A , data ); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/** +* \fn DRXStatus_t CtrlSetOOB() +* \brief Set OOB channel to be used. +* \param demod instance of demodulator +* \param oobParam OOB parameters for channel setting. +* \frequency should be in KHz +* \return DRXStatus_t. +* +* Accepts only. Returns error otherwise. +* Demapper value is written after SCUCommand START +* because START command causes COMM_EXEC transition +* from 0 to 1 which causes all registers to be +* overwritten with initial value +* +*/ + +/* Nyquist filter impulse response */ +#define IMPULSE_COSINE_ALPHA_0_3 {-3,-4,-1, 6,10, 7,-5,-20,-25,-10,29,79,123,140} /*sqrt raised-cosine filter with alpha=0.3 */ +#define IMPULSE_COSINE_ALPHA_0_5 { 2, 0,-2,-2, 2, 5, 2,-10,-20,-14,20,74,125,145} /*sqrt raised-cosine filter with alpha=0.5 */ +#define IMPULSE_COSINE_ALPHA_RO_0_5 { 0, 0, 1, 2, 3, 0,-7,-15,-16, 0,34,77,114,128} /*full raised-cosine filter with alpha=0.5 (receiver only) */ + +/* Coefficients for the nyquist fitler (total: 27 taps) */ +#define NYQFILTERLEN 27 + +static DRXStatus_t +CtrlSetOOB( pDRXDemodInstance_t demod, pDRXOOB_t oobParam ) +{ +#ifndef DRXJ_DIGITAL_ONLY + DRXOOBDownstreamStandard_t standard = DRX_OOB_MODE_A; + DRXFrequency_t freq = 0; /* KHz */ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + u16_t i = 0; + Bool_t mirrorFreqSpectOOB = FALSE; + u16_t trkFilterValue = 0; + DRXJSCUCmd_t scuCmd; + u16_t setParamParameters[3]; + u16_t cmdResult[2] = {0, 0}; + s16_t NyquistCoeffs[4][(NYQFILTERLEN+1)/2] = + { + IMPULSE_COSINE_ALPHA_0_3, /* Target Mode 0 */ + IMPULSE_COSINE_ALPHA_0_3, /* Target Mode 1 */ + IMPULSE_COSINE_ALPHA_0_5, /* Target Mode 2 */ + IMPULSE_COSINE_ALPHA_RO_0_5 /* Target Mode 3 */ + }; + u8_t mode_val[4] = {2, 2, 0, 1}; + u8_t PFICoeffs[4][6] = + { + {DRXJ_16TO8(-92), DRXJ_16TO8(-108), DRXJ_16TO8(100) }, /* TARGET_MODE = 0: PFI_A = -23/32; PFI_B = -54/32; PFI_C = 25/32; fg = 0.5 MHz (Att=26dB) */ + {DRXJ_16TO8(-64), DRXJ_16TO8(-80), DRXJ_16TO8(80) }, /* TARGET_MODE = 1: PFI_A = -16/32; PFI_B = -40/32; PFI_C = 20/32; fg = 1.0 MHz (Att=28dB) */ + {DRXJ_16TO8(-80), DRXJ_16TO8(-98), DRXJ_16TO8(92) }, /* TARGET_MODE = 2, 3: PFI_A = -20/32; PFI_B = -49/32; PFI_C = 23/32; fg = 0.8 MHz (Att=25dB) */ + {DRXJ_16TO8(-80), DRXJ_16TO8(-98), DRXJ_16TO8(92) } /* TARGET_MODE = 2, 3: PFI_A = -20/32; PFI_B = -49/32; PFI_C = 23/32; fg = 0.8 MHz (Att=25dB) */ + }; + u16_t mode_index; + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod -> myExtAttr; + mirrorFreqSpectOOB = extAttr->mirrorFreqSpectOOB; + + /* Check parameters */ + if (oobParam == NULL) + { + /* power off oob module */ + scuCmd.command = SCU_RAM_COMMAND_STANDARD_OOB + | SCU_RAM_COMMAND_CMD_DEMOD_STOP; + scuCmd.parameterLen = 0; + scuCmd.resultLen = 1; + scuCmd.result = cmdResult; + CHK_ERROR( SCUCommand( devAddr, &scuCmd ) ); + CHK_ERROR( SetOrxNsuAox( demod, FALSE ) ); + WR16 ( devAddr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP); + + extAttr->oobPowerOn = FALSE; + return (DRX_STS_OK); + } + + standard = oobParam->standard; + + freq = oobParam->frequency; + if ((freq < 70000) || (freq > 130000)) + return (DRX_STS_ERROR); + freq = (freq - 50000) / 50; + + { + u16_t index = 0; + u16_t remainder = 0; + pu16_t trkFiltercfg = extAttr->oobTrkFilterCfg; + + index = (u16_t)((freq - 400) / 200); + remainder = (u16_t)((freq - 400) % 200); + trkFilterValue = trkFiltercfg[index] - (trkFiltercfg[index] - trkFiltercfg[index + 1])/10 + * remainder / 20; + } + + + /*********/ + /* Stop */ + /*********/ + WR16 ( devAddr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP); + scuCmd.command = SCU_RAM_COMMAND_STANDARD_OOB + | SCU_RAM_COMMAND_CMD_DEMOD_STOP; + scuCmd.parameterLen = 0; + scuCmd.resultLen = 1; + scuCmd.result = cmdResult; + CHK_ERROR( SCUCommand( devAddr, &scuCmd ) ); + /*********/ + /* Reset */ + /*********/ + scuCmd.command = SCU_RAM_COMMAND_STANDARD_OOB + | SCU_RAM_COMMAND_CMD_DEMOD_RESET; + scuCmd.parameterLen = 0; + scuCmd.resultLen = 1; + scuCmd.result = cmdResult; + CHK_ERROR( SCUCommand( devAddr, &scuCmd ) ); + /***********/ + /* SET_ENV */ + /***********/ + /* set frequency, spectrum inversion and data rate */ + scuCmd.command = SCU_RAM_COMMAND_STANDARD_OOB + | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV; + scuCmd.parameterLen = 3; + /* 1-data rate;2-frequency */ + switch ( oobParam->standard ) + { + case DRX_OOB_MODE_A: + if( + /* signal is transmitted inverted */ + ( (oobParam->spectrumInverted == TRUE) & + /* and tuner is not mirroring the signal */ + (mirrorFreqSpectOOB == FALSE) ) | + /* or */ + /* signal is transmitted noninverted */ + ( (oobParam->spectrumInverted == FALSE) & + /* and tuner is mirroring the signal */ + (mirrorFreqSpectOOB == TRUE) ) + ) + setParamParameters[0] = SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC; + else + setParamParameters[0] = SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC; + break; + case DRX_OOB_MODE_B_GRADE_A: + if( + /* signal is transmitted inverted */ + ( (oobParam->spectrumInverted == TRUE) & + /* and tuner is not mirroring the signal */ + (mirrorFreqSpectOOB == FALSE) ) | + /* or */ + /* signal is transmitted noninverted */ + ( (oobParam->spectrumInverted == FALSE) & + /* and tuner is mirroring the signal */ + (mirrorFreqSpectOOB == TRUE) ) + ) + setParamParameters[0] = SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_INVSPEC; + else + setParamParameters[0] = SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_REGSPEC; + break; + case DRX_OOB_MODE_B_GRADE_B: + default: + if( + /* signal is transmitted inverted */ + ( (oobParam->spectrumInverted == TRUE) & + /* and tuner is not mirroring the signal */ + (mirrorFreqSpectOOB == FALSE) ) | + /* or */ + /* signal is transmitted noninverted */ + ( (oobParam->spectrumInverted == FALSE) & + /* and tuner is mirroring the signal */ + (mirrorFreqSpectOOB == TRUE) ) + ) + setParamParameters[0] = SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_INVSPEC; + else + setParamParameters[0] = SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_REGSPEC; + break; + } + setParamParameters[1] = ( u16_t )( freq & 0xFFFF ); + setParamParameters[2] = trkFilterValue; + scuCmd.parameter = setParamParameters; + scuCmd.resultLen = 1; + scuCmd.result = cmdResult; + mode_index = mode_val[(setParamParameters[0] & 0xC0) >> 6]; + CHK_ERROR( SCUCommand( devAddr, &scuCmd ) ); + + WR16 ( devAddr, SIO_TOP_COMM_KEY__A, 0xFABA); /* Write magic word to enable pdr reg write */ + WR16 ( devAddr, SIO_PDR_OOB_CRX_CFG__A, + OOB_CRX_DRIVE_STRENGTH << SIO_PDR_OOB_CRX_CFG_DRIVE__B + | 0x03 << SIO_PDR_OOB_CRX_CFG_MODE__B ); + WR16 ( devAddr, SIO_PDR_OOB_DRX_CFG__A, + OOB_DRX_DRIVE_STRENGTH << SIO_PDR_OOB_DRX_CFG_DRIVE__B + | 0x03 << SIO_PDR_OOB_DRX_CFG_MODE__B ); + WR16 ( devAddr, SIO_TOP_COMM_KEY__A, 0x0000); /* Write magic word to disable pdr reg write */ + + WR16 ( devAddr, ORX_TOP_COMM_KEY__A, 0); + WR16 ( devAddr, ORX_FWP_AAG_LEN_W__A, 16000); + WR16 ( devAddr, ORX_FWP_AAG_THR_W__A, 40); + + /* ddc */ + WR16( devAddr, ORX_DDC_OFO_SET_W__A, ORX_DDC_OFO_SET_W__PRE); + + /* nsu */ + WR16( devAddr, ORX_NSU_AOX_LOPOW_W__A, extAttr->oobLoPow); + + /* initialization for target mode */ + WR16( devAddr, SCU_RAM_ORX_TARGET_MODE__A, SCU_RAM_ORX_TARGET_MODE_2048KBPS_SQRT); + WR16( devAddr, SCU_RAM_ORX_FREQ_GAIN_CORR__A, SCU_RAM_ORX_FREQ_GAIN_CORR_2048KBPS); + + /* Reset bits for timing and freq. recovery */ + WR16( devAddr, SCU_RAM_ORX_RST_CPH__A, 0x0001); + WR16( devAddr, SCU_RAM_ORX_RST_CTI__A, 0x0002); + WR16( devAddr, SCU_RAM_ORX_RST_KRN__A, 0x0004); + WR16( devAddr, SCU_RAM_ORX_RST_KRP__A, 0x0008); + + /* AGN_LOCK = {2048>>3, -2048, 8, -8, 0, 1}; */ + WR16( devAddr, SCU_RAM_ORX_AGN_LOCK_TH__A, 2048>>3); + WR16( devAddr, SCU_RAM_ORX_AGN_LOCK_TOTH__A, (u16_t) (-2048)); + WR16( devAddr, SCU_RAM_ORX_AGN_ONLOCK_TTH__A, 8); + WR16( devAddr, SCU_RAM_ORX_AGN_UNLOCK_TTH__A, (u16_t)(-8)); + WR16( devAddr, SCU_RAM_ORX_AGN_LOCK_MASK__A, 1); + + /* DGN_LOCK = {10, -2048, 8, -8, 0, 1<<1}; */ + WR16( devAddr, SCU_RAM_ORX_DGN_LOCK_TH__A, 10); + WR16( devAddr, SCU_RAM_ORX_DGN_LOCK_TOTH__A, (u16_t)(-2048)); + WR16( devAddr, SCU_RAM_ORX_DGN_ONLOCK_TTH__A, 8); + WR16( devAddr, SCU_RAM_ORX_DGN_UNLOCK_TTH__A, (u16_t)(-8)); + WR16( devAddr, SCU_RAM_ORX_DGN_LOCK_MASK__A, 1<<1); + + /* FRQ_LOCK = {15,-2048, 8, -8, 0, 1<<2}; */ + WR16( devAddr, SCU_RAM_ORX_FRQ_LOCK_TH__A, 17); + WR16( devAddr, SCU_RAM_ORX_FRQ_LOCK_TOTH__A, (u16_t)(-2048)); + WR16( devAddr, SCU_RAM_ORX_FRQ_ONLOCK_TTH__A, 8); + WR16( devAddr, SCU_RAM_ORX_FRQ_UNLOCK_TTH__A, (u16_t)(-8)); + WR16( devAddr, SCU_RAM_ORX_FRQ_LOCK_MASK__A, 1<<2); + + /* PHA_LOCK = {5000, -2048, 8, -8, 0, 1<<3}; */ + WR16( devAddr, SCU_RAM_ORX_PHA_LOCK_TH__A, 3000); + WR16( devAddr, SCU_RAM_ORX_PHA_LOCK_TOTH__A, (u16_t)(-2048)); + WR16( devAddr, SCU_RAM_ORX_PHA_ONLOCK_TTH__A, 8); + WR16( devAddr, SCU_RAM_ORX_PHA_UNLOCK_TTH__A, (u16_t)(-8)); + WR16( devAddr, SCU_RAM_ORX_PHA_LOCK_MASK__A, 1<<3); + + /* TIM_LOCK = {300, -2048, 8, -8, 0, 1<<4}; */ + WR16( devAddr, SCU_RAM_ORX_TIM_LOCK_TH__A, 400); + WR16( devAddr, SCU_RAM_ORX_TIM_LOCK_TOTH__A, (u16_t)(-2048)); + WR16( devAddr, SCU_RAM_ORX_TIM_ONLOCK_TTH__A, 8); + WR16( devAddr, SCU_RAM_ORX_TIM_UNLOCK_TTH__A, (u16_t)(-8)); + WR16( devAddr, SCU_RAM_ORX_TIM_LOCK_MASK__A, 1<<4); + + /* EQU_LOCK = {20, -2048, 8, -8, 0, 1<<5}; */ + WR16( devAddr, SCU_RAM_ORX_EQU_LOCK_TH__A, 20); + WR16( devAddr, SCU_RAM_ORX_EQU_LOCK_TOTH__A, (u16_t)(-2048)); + WR16( devAddr, SCU_RAM_ORX_EQU_ONLOCK_TTH__A, 4); + WR16( devAddr, SCU_RAM_ORX_EQU_UNLOCK_TTH__A, (u16_t)(-4)); + WR16( devAddr, SCU_RAM_ORX_EQU_LOCK_MASK__A, 1<<5); + + /* PRE-Filter coefficients (PFI) */ + WRB( devAddr, ORX_FWP_PFI_A_W__A, sizeof(PFICoeffs[mode_index]), ((pu8_t)PFICoeffs[mode_index])); + WR16( devAddr, ORX_TOP_MDE_W__A, mode_index); + + /* NYQUIST-Filter coefficients (NYQ) */ + for (i = 0; i < (NYQFILTERLEN + 1) / 2; i++) + { + WR16( devAddr, ORX_FWP_NYQ_ADR_W__A, i); + WR16( devAddr, ORX_FWP_NYQ_COF_RW__A, NyquistCoeffs[mode_index][i]); + } + WR16( devAddr, ORX_FWP_NYQ_ADR_W__A, 31); + WR16 ( devAddr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_ACTIVE); + /*********/ + /* Start */ + /*********/ + scuCmd.command = SCU_RAM_COMMAND_STANDARD_OOB + | SCU_RAM_COMMAND_CMD_DEMOD_START; + scuCmd.parameterLen = 0; + scuCmd.resultLen = 1; + scuCmd.result = cmdResult; + CHK_ERROR( SCUCommand( devAddr, &scuCmd ) ); + + CHK_ERROR( SetOrxNsuAox( demod, TRUE ) ); + WR16( devAddr, ORX_NSU_AOX_STHR_W__A, extAttr->oobPreSaw ); + + extAttr->oobPowerOn = TRUE; + + return (DRX_STS_OK); +rw_error: +#endif + return (DRX_STS_ERROR); +} +/** +* \fn DRXStatus_t CtrlGetOOB() +* \brief Set modulation standard to be used. +* \param demod instance of demodulator +* \param oobStatus OOB status parameters. +* \return DRXStatus_t. +*/ +static DRXStatus_t +CtrlGetOOB( pDRXDemodInstance_t demod, pDRXOOBStatus_t oobStatus ) +{ +#ifndef DRXJ_DIGITAL_ONLY + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + u16_t data = 0; + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; + + /* check arguments */ + if ( oobStatus == NULL ) + { + return (DRX_STS_INVALID_ARG); + } + + if ( extAttr->oobPowerOn == FALSE) + return (DRX_STS_ERROR); + + RR16 ( devAddr, ORX_DDC_OFO_SET_W__A, &data); + RR16 ( devAddr, ORX_NSU_TUN_RFGAIN_W__A, &data); + RR16 ( devAddr, ORX_FWP_AAG_THR_W__A, &data); + SARR16 ( devAddr, SCU_RAM_ORX_DGN_KI__A, &data); + RR16 ( devAddr, ORX_FWP_SRC_DGN_W__A, &data); + + CHK_ERROR ( GetOOBLockStatus ( demod, devAddr, &oobStatus->lock )); + CHK_ERROR ( GetOOBFrequency ( demod, &oobStatus->frequency )); + CHK_ERROR ( GetOOBMER ( devAddr, &oobStatus->mer )); + CHK_ERROR ( GetOOBSymbolRateOffset ( devAddr, &oobStatus->symbolRateOffset )); + + return (DRX_STS_OK); +rw_error: +#endif + return (DRX_STS_ERROR); +} + +/** +* \fn DRXStatus_t CtrlSetCfgOOBPreSAW() +* \brief Configure PreSAW treshold value +* \param cfgData Pointer to configuration parameter +* \return Error code +*/ +#ifndef DRXJ_DIGITAL_ONLY +static DRXStatus_t +CtrlSetCfgOOBPreSAW( pDRXDemodInstance_t demod, pu16_t cfgData ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + + if(cfgData == NULL) + { + return (DRX_STS_INVALID_ARG); + } + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + WR16( devAddr, ORX_NSU_AOX_STHR_W__A, *cfgData ); + extAttr->oobPreSaw = *cfgData; + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} +#endif + +/** +* \fn DRXStatus_t CtrlGetCfgOOBPreSAW() +* \brief Configure PreSAW treshold value +* \param cfgData Pointer to configuration parameter +* \return Error code +*/ +#ifndef DRXJ_DIGITAL_ONLY +static DRXStatus_t +CtrlGetCfgOOBPreSAW( pDRXDemodInstance_t demod, pu16_t cfgData ) +{ + pDRXJData_t extAttr = NULL; + + if(cfgData == NULL) + { + return (DRX_STS_INVALID_ARG); + } + extAttr = (pDRXJData_t)demod->myExtAttr; + + *cfgData = extAttr->oobPreSaw; + + return (DRX_STS_OK); +} +#endif + +/** +* \fn DRXStatus_t CtrlSetCfgOOBLoPower() +* \brief Configure LO Power value +* \param cfgData Pointer to pDRXJCfgOobLoPower_t +* \return Error code +*/ +#ifndef DRXJ_DIGITAL_ONLY +static DRXStatus_t +CtrlSetCfgOOBLoPower( pDRXDemodInstance_t demod, pDRXJCfgOobLoPower_t cfgData ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + + if(cfgData == NULL) + { + return (DRX_STS_INVALID_ARG); + } + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + WR16( devAddr, ORX_NSU_AOX_LOPOW_W__A, *cfgData ); + extAttr->oobLoPow = *cfgData; + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} +#endif + +/** +* \fn DRXStatus_t CtrlGetCfgOOBLoPower() +* \brief Configure LO Power value +* \param cfgData Pointer to pDRXJCfgOobLoPower_t +* \return Error code +*/ +#ifndef DRXJ_DIGITAL_ONLY +static DRXStatus_t +CtrlGetCfgOOBLoPower( pDRXDemodInstance_t demod, pDRXJCfgOobLoPower_t cfgData ) +{ + pDRXJData_t extAttr = NULL; + + if(cfgData == NULL) + { + return (DRX_STS_INVALID_ARG); + } + extAttr = (pDRXJData_t)demod->myExtAttr; + + *cfgData = extAttr->oobLoPow; + + return (DRX_STS_OK); +} +#endif +/*============================================================================*/ +/*== END OOB DATAPATH FUNCTIONS ==*/ +/*============================================================================*/ + +/*============================================================================= + ===== MC command related functions ========================================== + ===========================================================================*/ + +/*============================================================================= + ===== CtrlSetChannel() ========================================================== + ===========================================================================*/ +/** +* \fn DRXStatus_t CtrlSetChannel() +* \brief Select a new transmission channel. +* \param demod instance of demod. +* \param channel Pointer to channel data. +* \return DRXStatus_t. +* +* In case the tuner module is not used and in case of NTSC/FM the pogrammer +* must tune the tuner to the centre frequency of the NTSC/FM channel. +* +*/ +static DRXStatus_t +CtrlSetChannel( pDRXDemodInstance_t demod, + pDRXChannel_t channel ) +{ + + DRXFrequency_t tunerSetFreq = 0; + DRXFrequency_t tunerGetFreq = 0; + DRXFrequency_t tunerFreqOffset = 0; + DRXFrequency_t intermediateFreq = 0; + pDRXJData_t extAttr = NULL; + pI2CDeviceAddr_t devAddr = NULL; + DRXStandard_t standard = DRX_STANDARD_UNKNOWN; + TUNERMode_t tunerMode = 0; + pDRXCommonAttr_t commonAttr = NULL; + Bool_t bridgeClosed = FALSE; +#ifndef DRXJ_VSB_ONLY + u32_t minSymbolRate = 0; + u32_t maxSymbolRate = 0; + int bandwidthTemp = 0; + int bandwidth = 0; +#endif + /*== check arguments ======================================================*/ + if ( ( demod == NULL ) || + ( channel == NULL ) ) + { + return DRX_STS_INVALID_ARG; + } + + commonAttr = (pDRXCommonAttr_t) demod -> myCommonAttr; + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod -> myExtAttr; + standard = extAttr->standard; + + /* check valid standards */ + switch ( standard ) + { + case DRX_STANDARD_8VSB: +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: +#endif /* DRXJ_VSB_ONLY */ +#ifndef DRXJ_DIGITAL_ONLY + case DRX_STANDARD_NTSC: + case DRX_STANDARD_FM: + case DRX_STANDARD_PAL_SECAM_BG: + case DRX_STANDARD_PAL_SECAM_DK: + case DRX_STANDARD_PAL_SECAM_I: + case DRX_STANDARD_PAL_SECAM_L: + case DRX_STANDARD_PAL_SECAM_LP: +#endif /* DRXJ_DIGITAL_ONLY */ + break; + case DRX_STANDARD_UNKNOWN: + default: + return (DRX_STS_INVALID_ARG); + } + + /* check bandwidth QAM annex B, NTSC and 8VSB */ + if ( ( standard == DRX_STANDARD_ITU_B ) || + ( standard == DRX_STANDARD_8VSB ) || + ( standard == DRX_STANDARD_NTSC ) ) + { + switch ( channel->bandwidth ) { + case DRX_BANDWIDTH_6MHZ : + case DRX_BANDWIDTH_UNKNOWN : /* fall through */ + channel->bandwidth = DRX_BANDWIDTH_6MHZ; + break; + case DRX_BANDWIDTH_8MHZ : /* fall through */ + case DRX_BANDWIDTH_7MHZ : /* fall through */ + default : + return (DRX_STS_INVALID_ARG); + } + } + +#ifndef DRXJ_DIGITAL_ONLY + if ( standard == DRX_STANDARD_PAL_SECAM_BG ) + { + switch ( channel->bandwidth ) + { + case DRX_BANDWIDTH_7MHZ : /* fall through */ + case DRX_BANDWIDTH_8MHZ : + /* ok */ + break; + case DRX_BANDWIDTH_6MHZ : /* fall through */ + case DRX_BANDWIDTH_UNKNOWN : /* fall through */ + default : + return (DRX_STS_INVALID_ARG); + } + } + /* check bandwidth PAL/SECAM */ + if ( ( standard == DRX_STANDARD_PAL_SECAM_BG ) || + ( standard == DRX_STANDARD_PAL_SECAM_DK ) || + ( standard == DRX_STANDARD_PAL_SECAM_I ) || + ( standard == DRX_STANDARD_PAL_SECAM_L ) || + ( standard == DRX_STANDARD_PAL_SECAM_LP ) ) + { + switch ( channel->bandwidth ) + { + case DRX_BANDWIDTH_8MHZ : + case DRX_BANDWIDTH_UNKNOWN : /* fall through */ + channel->bandwidth = DRX_BANDWIDTH_8MHZ; + break; + case DRX_BANDWIDTH_6MHZ : /* fall through */ + case DRX_BANDWIDTH_7MHZ : /* fall through */ + default : + return (DRX_STS_INVALID_ARG); + } + } +#endif + + /* For QAM annex A and annex C: + -check symbolrate and constellation + -derive bandwidth from symbolrate (input bandwidth is ignored) + */ +#ifndef DRXJ_VSB_ONLY + if( ( standard == DRX_STANDARD_ITU_A ) || + ( standard == DRX_STANDARD_ITU_C ) ) + { + DRXUIOCfg_t UIOCfg = {DRX_UIO1, DRX_UIO_MODE_FIRMWARE_SAW}; + int bwRolloffFactor = 0; + + bwRolloffFactor = (standard == DRX_STANDARD_ITU_A)?115:113; + minSymbolRate = DRXJ_QAM_SYMBOLRATE_MIN; + maxSymbolRate = DRXJ_QAM_SYMBOLRATE_MAX; + /* config SMA_TX pin to SAW switch mode*/ + CHK_ERROR( CtrlSetUIOCfg( demod, &UIOCfg ) ); + + if ( channel->symbolrate < minSymbolRate || + channel->symbolrate > maxSymbolRate ) + { + return ( DRX_STS_INVALID_ARG ); + } + + switch ( channel->constellation ) { + case DRX_CONSTELLATION_QAM16 : /* fall through */ + case DRX_CONSTELLATION_QAM32 : /* fall through */ + case DRX_CONSTELLATION_QAM64 : /* fall through */ + case DRX_CONSTELLATION_QAM128 : /* fall through */ + case DRX_CONSTELLATION_QAM256 : + bandwidthTemp = channel->symbolrate * bwRolloffFactor; + bandwidth = bandwidthTemp / 100; + + if( ( bandwidthTemp % 100 ) >= 50 ) + { + bandwidth++; + } + + if( bandwidth <= 6100000 ) + { + channel->bandwidth = DRX_BANDWIDTH_6MHZ; + } + else if( ( bandwidth > 6100000 ) && ( bandwidth <= 7100000 ) ) + { + channel->bandwidth = DRX_BANDWIDTH_7MHZ; + } + else if( bandwidth > 7100000 ) + { + channel->bandwidth = DRX_BANDWIDTH_8MHZ; + } + break; + default: + return (DRX_STS_INVALID_ARG); + } + } + + /* For QAM annex B: + -check constellation + */ + if ( standard == DRX_STANDARD_ITU_B ) + { + switch ( channel->constellation ) { + case DRX_CONSTELLATION_AUTO : + case DRX_CONSTELLATION_QAM256 : + case DRX_CONSTELLATION_QAM64 : + break; + default : + return (DRX_STS_INVALID_ARG); + } + + switch (channel->interleavemode) + { + case DRX_INTERLEAVEMODE_I128_J1: + case DRX_INTERLEAVEMODE_I128_J1_V2: + case DRX_INTERLEAVEMODE_I128_J2: + case DRX_INTERLEAVEMODE_I64_J2: + case DRX_INTERLEAVEMODE_I128_J3: + case DRX_INTERLEAVEMODE_I32_J4: + case DRX_INTERLEAVEMODE_I128_J4: + case DRX_INTERLEAVEMODE_I16_J8: + case DRX_INTERLEAVEMODE_I128_J5: + case DRX_INTERLEAVEMODE_I8_J16: + case DRX_INTERLEAVEMODE_I128_J6: + case DRX_INTERLEAVEMODE_I128_J7: + case DRX_INTERLEAVEMODE_I128_J8: + case DRX_INTERLEAVEMODE_I12_J17: + case DRX_INTERLEAVEMODE_I5_J4: + case DRX_INTERLEAVEMODE_B52_M240: + case DRX_INTERLEAVEMODE_B52_M720: + case DRX_INTERLEAVEMODE_UNKNOWN: + case DRX_INTERLEAVEMODE_AUTO: + break; + default: + return (DRX_STS_INVALID_ARG); + } + } + + if ( (extAttr->uioSmaTxMode) == DRX_UIO_MODE_FIRMWARE_SAW ) + { + /* SAW SW, user UIO is used for switchable SAW */ + DRXUIOData_t uio1 = { DRX_UIO1, FALSE }; + + switch ( channel->bandwidth ) + { + case DRX_BANDWIDTH_8MHZ: + uio1.value = TRUE; + break; + case DRX_BANDWIDTH_7MHZ: + uio1.value = FALSE; + break; + case DRX_BANDWIDTH_6MHZ: + uio1.value = FALSE; + break; + case DRX_BANDWIDTH_UNKNOWN: + default: + return (DRX_STS_INVALID_ARG); + } + + CHK_ERROR( CtrlUIOWrite( demod, &uio1 ) ); + } +#endif /* DRXJ_VSB_ONLY */ + WR16( devAddr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); + /*== Tune, fast mode ======================================================*/ + if ( demod->myTuner != NULL ) + { + /* Determine tuner mode and freq to tune to ... */ + switch ( standard ) { +#ifndef DRXJ_DIGITAL_ONLY + case DRX_STANDARD_NTSC: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_LP: + /* expecting center frequency, not picture carrier so no + conversion .... */ + tunerMode |= TUNER_MODE_ANALOG; + tunerSetFreq = channel->frequency; + break; + case DRX_STANDARD_FM: + /* center frequency (equals sound carrier) as input, + tune to edge of SAW */ + tunerMode |= TUNER_MODE_ANALOG; + tunerSetFreq = channel->frequency + DRXJ_FM_CARRIER_FREQ_OFFSET; + break; +#endif + case DRX_STANDARD_8VSB: /* fallthrough */ +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: +#endif + tunerMode |= TUNER_MODE_DIGITAL; + tunerSetFreq = channel->frequency; + break; + case DRX_STANDARD_UNKNOWN: + default: + return (DRX_STS_ERROR); + } /* switch(standard) */ + + tunerMode |= TUNER_MODE_SWITCH; + switch ( channel->bandwidth ) { + case DRX_BANDWIDTH_8MHZ : + tunerMode |= TUNER_MODE_8MHZ; + break; + case DRX_BANDWIDTH_7MHZ : + tunerMode |= TUNER_MODE_7MHZ; + break; + case DRX_BANDWIDTH_6MHZ : + tunerMode |= TUNER_MODE_6MHZ; + break; + default: + /* TODO: for FM which bandwidth to use ? + also check offset from centre frequency ? + For now using 6MHz. + */ + tunerMode |= TUNER_MODE_6MHZ; + break; + /* return (DRX_STS_INVALID_ARG); */ + } + + /* store bandwidth for GetChannel() */ + extAttr->currBandwidth = channel->bandwidth; + extAttr->currSymbolRate = channel->symbolrate; + extAttr->frequency = tunerSetFreq; + if ( commonAttr->tunerPortNr == 1 ) + { + /* close tuner bridge */ + bridgeClosed = TRUE; + CHK_ERROR( CtrlI2CBridge( demod, &bridgeClosed ) ); + /* set tuner frequency */ + } + + CHK_ERROR( DRXBSP_TUNER_SetFrequency( demod->myTuner, + tunerMode, + tunerSetFreq ) ); + if ( commonAttr->tunerPortNr == 1 ) + { + /* open tuner bridge */ + bridgeClosed = FALSE; + CHK_ERROR( CtrlI2CBridge( demod, &bridgeClosed ) ); + } + + /* Get actual frequency set by tuner and compute offset */ + CHK_ERROR( DRXBSP_TUNER_GetFrequency( demod->myTuner, + 0, + &tunerGetFreq, + &intermediateFreq ) ); + tunerFreqOffset = tunerGetFreq - tunerSetFreq; + commonAttr->intermediateFreq = intermediateFreq; + } + else + { + /* no tuner instance defined, use fixed intermediate frequency */ + tunerFreqOffset = 0; + intermediateFreq = demod->myCommonAttr->intermediateFreq; + } /* if ( demod->myTuner != NULL ) */ + + /*== Setup demod for specific standard ====================================*/ + switch ( standard ) { + case DRX_STANDARD_8VSB: + if (channel->mirror == DRX_MIRROR_AUTO) + { + extAttr->mirror = DRX_MIRROR_NO; + } + else + { + extAttr->mirror = channel->mirror; + } + CHK_ERROR ( SetVSB(demod) ); + CHK_ERROR ( SetFrequency ( demod, channel, tunerFreqOffset ) ); + break; +#ifndef DRXJ_DIGITAL_ONLY + case DRX_STANDARD_NTSC: /* fallthrough */ + case DRX_STANDARD_FM: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_LP: + if (channel->mirror == DRX_MIRROR_AUTO) + { + extAttr->mirror = DRX_MIRROR_NO; + } + else + { + extAttr->mirror = channel->mirror; + } + CHK_ERROR ( SetATVChannel( demod, + tunerFreqOffset, + channel, + standard ) ); + break; +#endif +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: + CHK_ERROR ( SetQAMChannel( demod, channel, tunerFreqOffset ) ); + break; +#endif + case DRX_STANDARD_UNKNOWN: + default: + return (DRX_STS_ERROR); + } + + /*== Re-tune, slow mode ===================================================*/ + if ( demod->myTuner != NULL ) + { + /* tune to slow mode */ + tunerMode &= ~TUNER_MODE_SWITCH; + tunerMode |= TUNER_MODE_LOCK; + + if ( commonAttr->tunerPortNr == 1 ) + { + /* close tuner bridge */ + bridgeClosed = TRUE; + CHK_ERROR( CtrlI2CBridge( demod, &bridgeClosed ) ); + } + + /* set tuner frequency*/ + CHK_ERROR( DRXBSP_TUNER_SetFrequency( demod->myTuner, + tunerMode, + tunerSetFreq ) ); + if ( commonAttr->tunerPortNr == 1 ) + { + /* open tuner bridge */ + bridgeClosed = FALSE; + CHK_ERROR( CtrlI2CBridge( demod, &bridgeClosed ) ); + } + } /* if ( demod->myTuner !=NULL ) */ + + /* flag the packet error counter reset */ + extAttr->resetPktErrAcc = TRUE; + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================= + ===== CtrlGetChannel() ========================================================== + ===========================================================================*/ +/** +* \fn DRXStatus_t CtrlGetChannel() +* \brief Retreive parameters of current transmission channel. +* \param demod Pointer to demod instance. +* \param channel Pointer to channel data. +* \return DRXStatus_t. +*/ +static DRXStatus_t +CtrlGetChannel( pDRXDemodInstance_t demod, + pDRXChannel_t channel ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + DRXLockStatus_t lockStatus = DRX_NOT_LOCKED; + DRXStandard_t standard = DRX_STANDARD_UNKNOWN; + pDRXCommonAttr_t commonAttr = NULL; + DRXFrequency_t intermediateFreq = 0; + s32_t CTLFreqOffset = 0; + u32_t iqmRcRateLo = 0; + u32_t adcFrequency = 0; +#ifndef DRXJ_VSB_ONLY + int bandwidthTemp = 0; + int bandwidth = 0; +#endif + + /* check arguments */ + if ( ( demod == NULL ) || + ( channel == NULL ) ) + { + return DRX_STS_INVALID_ARG; + } + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod -> myExtAttr; + standard = extAttr->standard; + commonAttr = (pDRXCommonAttr_t) demod -> myCommonAttr; + + /* initialize channel fields */ + channel->mirror = DRX_MIRROR_UNKNOWN; + channel->hierarchy = DRX_HIERARCHY_UNKNOWN; + channel->priority = DRX_PRIORITY_UNKNOWN; + channel->coderate = DRX_CODERATE_UNKNOWN; + channel->guard = DRX_GUARD_UNKNOWN; + channel->fftmode = DRX_FFTMODE_UNKNOWN; + channel->classification = DRX_CLASSIFICATION_UNKNOWN; + channel->bandwidth = DRX_BANDWIDTH_UNKNOWN; + channel->constellation = DRX_CONSTELLATION_UNKNOWN; + channel->symbolrate = 0; + channel->interleavemode = DRX_INTERLEAVEMODE_UNKNOWN; + channel->carrier = DRX_CARRIER_UNKNOWN; + channel->framemode = DRX_FRAMEMODE_UNKNOWN; +/* channel->interleaver = DRX_INTERLEAVER_UNKNOWN;*/ + channel->ldpc = DRX_LDPC_UNKNOWN; + + if ( demod->myTuner != NULL ) + { + DRXFrequency_t tunerFreqOffset = 0; + Bool_t tunerMirror = commonAttr->mirrorFreqSpect?FALSE:TRUE; + + /* Get frequency from tuner */ + CHK_ERROR( DRXBSP_TUNER_GetFrequency( demod->myTuner, + 0, + &(channel->frequency), + &intermediateFreq ) ); + tunerFreqOffset = channel->frequency - extAttr->frequency; + if ( tunerMirror == TRUE ) + { + /* positive image */ + channel->frequency += tunerFreqOffset; + } else { + /* negative image */ + channel->frequency -= tunerFreqOffset; + } + + /* Handle sound carrier offset in RF domain */ + if ( standard == DRX_STANDARD_FM ) + { + channel->frequency -= DRXJ_FM_CARRIER_FREQ_OFFSET; + } + } + else + { + intermediateFreq = commonAttr->intermediateFreq; + } + + /* check lock status */ + CHK_ERROR( CtrlLockStatus( demod, &lockStatus) ); + if ( (lockStatus == DRX_LOCKED) || (lockStatus == DRXJ_DEMOD_LOCK) ) + { + ARR32( devAddr, IQM_RC_RATE_LO__A, &iqmRcRateLo ); + adcFrequency = ( commonAttr->sysClockFreq * 1000 ) / 3; + + channel->symbolrate = Frac28(adcFrequency, (iqmRcRateLo + (1<<23))) >> 7; + + switch ( standard ) + { + case DRX_STANDARD_8VSB: + channel->bandwidth = DRX_BANDWIDTH_6MHZ; + /* get the channel frequency */ + CHK_ERROR( GetCTLFreqOffset ( demod, &CTLFreqOffset ) ); + channel->frequency -= CTLFreqOffset; + /* get the channel constellation */ + channel->constellation = DRX_CONSTELLATION_AUTO; + break; +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: + { + /* get the channel frequency */ + CHK_ERROR( GetCTLFreqOffset ( demod, &CTLFreqOffset ) ); + channel->frequency -= CTLFreqOffset; + + if (standard == DRX_STANDARD_ITU_B) + { + channel->bandwidth = DRX_BANDWIDTH_6MHZ; + } + else + { + /* annex A & C */ + + u32_t rollOff=113; /* default annex C */ + + if ( standard==DRX_STANDARD_ITU_A) + { + rollOff=115; + } + + bandwidthTemp = channel->symbolrate * rollOff; + bandwidth = bandwidthTemp / 100; + + if( ( bandwidthTemp % 100 ) >= 50 ) + { + bandwidth++; + } + + if( bandwidth <= 6000000 ) + { + channel->bandwidth = DRX_BANDWIDTH_6MHZ; + } + else if( ( bandwidth > 6000000 ) && ( bandwidth <= 7000000 ) ) + { + channel->bandwidth = DRX_BANDWIDTH_7MHZ; + } + else if( bandwidth > 7000000 ) + { + channel->bandwidth = DRX_BANDWIDTH_8MHZ; + } + } /* if (standard == DRX_STANDARD_ITU_B) */ + + { + DRXJSCUCmd_t cmdSCU = { /* command */ 0, + /* parameterLen */ 0, + /* resultLen */ 0, + /* parameter */ NULL, + /* result */ NULL }; + u16_t cmdResult[3] = { 0, 0, 0 }; + + cmdSCU.command = SCU_RAM_COMMAND_STANDARD_QAM | + SCU_RAM_COMMAND_CMD_DEMOD_GET_PARAM; + cmdSCU.parameterLen = 0; + cmdSCU.resultLen = 3; + cmdSCU.parameter = NULL; + cmdSCU.result = cmdResult; + CHK_ERROR( SCUCommand( devAddr, &cmdSCU ) ); + + channel->interleavemode = (DRXInterleaveModes_t)(cmdSCU.result[2]); + } + + switch ( extAttr->constellation ) + { + case DRX_CONSTELLATION_QAM256: + channel->constellation = DRX_CONSTELLATION_QAM256; + break; + case DRX_CONSTELLATION_QAM128: + channel->constellation = DRX_CONSTELLATION_QAM128; + break; + case DRX_CONSTELLATION_QAM64: + channel->constellation = DRX_CONSTELLATION_QAM64; + break; + case DRX_CONSTELLATION_QAM32: + channel->constellation = DRX_CONSTELLATION_QAM32; + break; + case DRX_CONSTELLATION_QAM16: + channel->constellation = DRX_CONSTELLATION_QAM16; + break; + default: + channel->constellation = DRX_CONSTELLATION_UNKNOWN; + return (DRX_STS_ERROR); + } + } + break; +#endif +#ifndef DRXJ_DIGITAL_ONLY + case DRX_STANDARD_NTSC: /* fall trough */ + case DRX_STANDARD_PAL_SECAM_BG: + case DRX_STANDARD_PAL_SECAM_DK: + case DRX_STANDARD_PAL_SECAM_I: + case DRX_STANDARD_PAL_SECAM_L: + case DRX_STANDARD_PAL_SECAM_LP: + case DRX_STANDARD_FM: + CHK_ERROR( GetATVChannel(demod, channel, standard)); + break; +#endif + case DRX_STANDARD_UNKNOWN: /* fall trough */ + default: + return (DRX_STS_ERROR); + } /* switch ( standard ) */ + + if (lockStatus == DRX_LOCKED) + { + channel->mirror = extAttr->mirror; + } + } /* if ( lockStatus == DRX_LOCKED ) */ + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================= + ===== SigQuality() ========================================================== + ===========================================================================*/ + +static u16_t +mer2indicator ( + u16_t mer, + u16_t minMer, + u16_t thresholdMer, + u16_t maxMer) +{ + u16_t indicator = 0; + + if ( mer < minMer ) + { + indicator = 0; + } + else if ( mer < thresholdMer ) + { + if ((thresholdMer - minMer) != 0) + { + indicator = 25 * (mer - minMer) / (thresholdMer - minMer); + } + } + else if ( mer < maxMer ) + { + if ((maxMer - thresholdMer) != 0) + { + indicator = 25 + 75 * (mer - thresholdMer) / (maxMer - thresholdMer); + } + else + { + indicator = 25; + } + } + else + { + indicator = 100; + } + + return indicator; +} +/** +* \fn DRXStatus_t CtrlSigQuality() +* \brief Retreive signal quality form device. +* \param devmod Pointer to demodulator instance. +* \param sigQuality Pointer to signal quality data. +* \return DRXStatus_t. +* \retval DRX_STS_OK sigQuality contains valid data. +* \retval DRX_STS_INVALID_ARG sigQuality is NULL. +* \retval DRX_STS_ERROR Erroneous data, sigQuality contains invalid data. + +*/ +static DRXStatus_t +CtrlSigQuality( pDRXDemodInstance_t demod, + pDRXSigQuality_t sigQuality ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + DRXStandard_t standard = DRX_STANDARD_UNKNOWN; + DRXLockStatus_t lockStatus = DRX_NOT_LOCKED; + u16_t minMer = 0; + u16_t maxMer = 0; + u16_t thresholdMer = 0; + + /* Check arguments */ + if (( sigQuality == NULL ) || + ( demod == NULL )) + { + return (DRX_STS_INVALID_ARG); + } + + extAttr = (pDRXJData_t)demod->myExtAttr; + standard = extAttr->standard; + + /* get basic information */ + devAddr = demod -> myI2CDevAddr; + CHK_ERROR( CtrlLockStatus( demod, &lockStatus) ); + switch ( standard ) { + case DRX_STANDARD_8VSB: +#ifdef DRXJ_SIGNAL_ACCUM_ERR + CHK_ERROR (GetAccPktErr (demod, &sigQuality->packetError)); +#else + CHK_ERROR (GetVSBPostRSPckErr (devAddr, &sigQuality->packetError)); +#endif + if ( lockStatus != DRXJ_DEMOD_LOCK && lockStatus != DRX_LOCKED ) + { + sigQuality->postViterbiBER = 500000; + sigQuality->MER = 20; + sigQuality->preViterbiBER = 0; + } else { + /* PostViterbi is compute in steps of 10^(-6) */ + CHK_ERROR (GetVSBpreViterbiBer (devAddr, &sigQuality->preViterbiBER)); + CHK_ERROR (GetVSBpostViterbiBer (devAddr, &sigQuality->postViterbiBER)); + CHK_ERROR (GetVSBMER (devAddr, &sigQuality->MER)); + } + minMer = 20; + maxMer = 360; + thresholdMer = 145; + sigQuality->postReedSolomonBER = 0; + sigQuality->scaleFactorBER = 1000000; + sigQuality->indicator = mer2indicator (sigQuality->MER, minMer, thresholdMer, maxMer); + break; +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: + CHK_ERROR ( CtrlGetQAMSigQuality ( demod, sigQuality ) ); + if ( lockStatus != DRXJ_DEMOD_LOCK && lockStatus != DRX_LOCKED ) + { + switch ( extAttr->constellation ) + { + case DRX_CONSTELLATION_QAM256: + sigQuality->MER = 210; + break; + case DRX_CONSTELLATION_QAM128: + sigQuality->MER = 180; + break; + case DRX_CONSTELLATION_QAM64: + sigQuality->MER = 150; + break; + case DRX_CONSTELLATION_QAM32: + sigQuality->MER = 120; + break; + case DRX_CONSTELLATION_QAM16: + sigQuality->MER = 90; + break; + default: + sigQuality->MER = 0; + return (DRX_STS_ERROR); + } + } + + switch ( extAttr->constellation ) + { + case DRX_CONSTELLATION_QAM256: + minMer = 210; + thresholdMer = 270; + maxMer = 380; + break; + case DRX_CONSTELLATION_QAM64: + minMer = 150; + thresholdMer = 210; + maxMer = 380; + break; + case DRX_CONSTELLATION_QAM128: + case DRX_CONSTELLATION_QAM32: + case DRX_CONSTELLATION_QAM16: + break; + default: + return (DRX_STS_ERROR); + } + sigQuality->indicator = mer2indicator (sigQuality->MER, minMer, thresholdMer, maxMer); + break; +#endif +#ifndef DRXJ_DIGITAL_ONLY + case DRX_STANDARD_PAL_SECAM_BG: + case DRX_STANDARD_PAL_SECAM_DK: + case DRX_STANDARD_PAL_SECAM_I: + case DRX_STANDARD_PAL_SECAM_L: + case DRX_STANDARD_PAL_SECAM_LP: + case DRX_STANDARD_NTSC: + CHK_ERROR ( AtvSigQuality ( demod, sigQuality ) ); + break; + case DRX_STANDARD_FM: + CHK_ERROR ( FmSigQuality ( demod, sigQuality ) ); + break; +#endif + default: + return (DRX_STS_ERROR); + } + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t CtrlLockStatus() +* \brief Retreive lock status . +* \param devAddr Pointer to demodulator device address. +* \param lockStat Pointer to lock status structure. +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +CtrlLockStatus( pDRXDemodInstance_t demod, + pDRXLockStatus_t lockStat ) +{ + DRXStandard_t standard = DRX_STANDARD_UNKNOWN; + pDRXJData_t extAttr = NULL; + pI2CDeviceAddr_t devAddr = NULL; + DRXJSCUCmd_t cmdSCU = { /* command */ 0, + /* parameterLen */ 0, + /* resultLen */ 0, + /* *parameter */ NULL, + /* *result */ NULL }; + u16_t cmdResult[2] = { 0, 0 }; + u16_t demodLock = SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_DEMOD_LOCKED; + + /* check arguments */ + if ( ( demod == NULL ) || + ( lockStat == NULL ) ) + { + return (DRX_STS_INVALID_ARG); + } + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + standard = extAttr->standard; + + *lockStat = DRX_NOT_LOCKED; + + /* define the SCU command code */ + switch ( standard ) { + case DRX_STANDARD_8VSB: + cmdSCU.command = SCU_RAM_COMMAND_STANDARD_VSB | + SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK; + demodLock |= 0x6; + break; +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: + cmdSCU.command = SCU_RAM_COMMAND_STANDARD_QAM | + SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK; + break; +#endif +#ifndef DRXJ_DIGITAL_ONLY + case DRX_STANDARD_NTSC: + case DRX_STANDARD_PAL_SECAM_BG: + case DRX_STANDARD_PAL_SECAM_DK: + case DRX_STANDARD_PAL_SECAM_I: + case DRX_STANDARD_PAL_SECAM_L: + case DRX_STANDARD_PAL_SECAM_LP: + cmdSCU.command = SCU_RAM_COMMAND_STANDARD_ATV | + SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK; + break; + case DRX_STANDARD_FM: + return FmLockStatus( demod, lockStat); +#endif + case DRX_STANDARD_UNKNOWN: /* fallthrough */ + default: + return (DRX_STS_ERROR); + } + + /* define the SCU command paramters and execute the command */ + cmdSCU.parameterLen = 0; + cmdSCU.resultLen = 2; + cmdSCU.parameter = NULL; + cmdSCU.result = cmdResult; + CHK_ERROR( SCUCommand( devAddr, &cmdSCU ) ); + + /* set the lock status */ + if ( cmdSCU.result[1] < demodLock ) + { + /* 0x0000 NOT LOCKED */ + *lockStat = DRX_NOT_LOCKED; + } + else if ( cmdSCU.result[1] < SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_LOCKED ) + { + *lockStat = DRXJ_DEMOD_LOCK; + } + else if ( cmdSCU.result[1] < SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NEVER_LOCK ) + { + /* 0x8000 DEMOD + FEC LOCKED (system lock) */ + *lockStat = DRX_LOCKED; + } + else + { + /* 0xC000 NEVER LOCKED */ + /* (system will never be able to lock to the signal) */ + *lockStat = DRX_NEVER_LOCK; + } + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t CtrlConstel() +* \brief Retreive a constellation point via I2C. +* \param demod Pointer to demodulator instance. +* \param complexNr Pointer to the structure in which to store the + constellation point. +* \return DRXStatus_t. +*/ +static DRXStatus_t +CtrlConstel( pDRXDemodInstance_t demod, + pDRXComplex_t complexNr ) +{ + DRXStandard_t standard = DRX_STANDARD_UNKNOWN; /**< active standard */ + + /* check arguments */ + if ( ( demod == NULL ) || + ( complexNr == NULL ) ) + { + return (DRX_STS_INVALID_ARG); + } + + /* read device info */ + standard = ((pDRXJData_t)demod->myExtAttr)->standard; + + /* Read constellation point */ + switch ( standard ) { + case DRX_STANDARD_8VSB: + CHK_ERROR( CtrlGetVSBConstel( demod, complexNr ) ); + break; +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: + CHK_ERROR( CtrlGetQAMConstel( demod, complexNr ) ); + break; +#endif + case DRX_STANDARD_UNKNOWN: + default: + return (DRX_STS_ERROR); + } + + return (DRX_STS_OK); + rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t CtrlSetStandard() +* \brief Set modulation standard to be used. +* \param standard Modulation standard. +* \return DRXStatus_t. +* +* Setup stuff for the desired demodulation standard. +* Disable and power down the previous selected demodulation standard +* +*/ +static DRXStatus_t +CtrlSetStandard( pDRXDemodInstance_t demod, pDRXStandard_t standard ) +{ + pDRXJData_t extAttr = NULL; + DRXStandard_t prevStandard; + + /* check arguments */ + if (( standard == NULL ) || + ( demod == NULL )) + { + return (DRX_STS_INVALID_ARG); + } + + extAttr = (pDRXJData_t)demod->myExtAttr; + prevStandard=extAttr->standard; + + /* + Stop and power down previous standard + */ + switch ( prevStandard ) + { +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: + CHK_ERROR( PowerDownQAM(demod, FALSE) ); + break; +#endif + case DRX_STANDARD_8VSB: + CHK_ERROR( PowerDownVSB(demod, FALSE) ); + break; +#ifndef DRXJ_DIGITAL_ONLY + case DRX_STANDARD_NTSC: /* fallthrough */ + case DRX_STANDARD_FM: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_LP: + CHK_ERROR( PowerDownATV( demod, prevStandard, FALSE )); + break; +#endif + case DRX_STANDARD_UNKNOWN: + /* Do nothing */ + break; + case DRX_STANDARD_AUTO: /* fallthrough */ + default: + return ( DRX_STS_INVALID_ARG ); + } + + /* + Initialize channel independent registers + Power up new standard + */ + extAttr->standard=*standard; + + switch ( *standard ) + { +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: + DUMMY_READ(); + break; +#endif + case DRX_STANDARD_8VSB: + CHK_ERROR(SetVSBLeakNGain(demod)); + break; +#ifndef DRXJ_DIGITAL_ONLY + case DRX_STANDARD_NTSC: /* fallthrough */ + case DRX_STANDARD_FM: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_LP: + CHK_ERROR( SetATVStandard( demod, standard )); + CHK_ERROR( PowerUpATV( demod, *standard )); + break; +#endif + default: + extAttr->standard=DRX_STANDARD_UNKNOWN; + return ( DRX_STS_INVALID_ARG ); + break; + } + + return (DRX_STS_OK); +rw_error: + /* Don't know what the standard is now ... try again */ + extAttr->standard=DRX_STANDARD_UNKNOWN; + return (DRX_STS_ERROR); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t CtrlGetStandard() +* \brief Get modulation standard currently used to demodulate. +* \param standard Modulation standard. +* \return DRXStatus_t. +* +* Returns 8VSB, NTSC, QAM only. +* +*/ +static DRXStatus_t +CtrlGetStandard( pDRXDemodInstance_t demod, pDRXStandard_t standard ) +{ + pDRXJData_t extAttr = NULL; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* check arguments */ + if ( standard == NULL ) + { + return (DRX_STS_INVALID_ARG); + } + (*standard) = extAttr->standard; + DUMMY_READ(); + + return ( DRX_STS_OK ); +rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t CtrlGetCfgSymbolClockOffset() +* \brief Get frequency offsets of STR. +* \param pointer to s32_t. +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +CtrlGetCfgSymbolClockOffset ( pDRXDemodInstance_t demod, + ps32_t rateOffset ) +{ + DRXStandard_t standard = DRX_STANDARD_UNKNOWN; + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + + /* check arguments */ + if ( rateOffset == NULL ) + { + return (DRX_STS_INVALID_ARG); + } + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + standard = extAttr->standard; + + switch ( standard ) { + case DRX_STANDARD_8VSB: /* fallthrough */ +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: +#endif + CHK_ERROR ( GetSTRFreqOffset ( demod, rateOffset )); + break; + case DRX_STANDARD_NTSC: + case DRX_STANDARD_UNKNOWN: + default: + return (DRX_STS_INVALID_ARG); + } + + return ( DRX_STS_OK ); +rw_error: + return (DRX_STS_ERROR); +} +/*============================================================================*/ + +/** +* \fn DRXStatus_t CtrlPowerMode() +* \brief Set the power mode of the device to the specified power mode +* \param demod Pointer to demodulator instance. +* \param mode Pointer to new power mode. +* \return DRXStatus_t. +* \retval DRX_STS_OK Success +* \retval DRX_STS_ERROR I2C error or other failure +* \retval DRX_STS_INVALID_ARG Invalid mode argument. +* +* +*/ +static DRXStatus_t +CtrlPowerMode( pDRXDemodInstance_t demod, + pDRXPowerMode_t mode ) +{ + pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t)NULL; + pDRXJData_t extAttr = (pDRXJData_t)NULL; + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)NULL; + u16_t sioCcPwdMode = 0; + + commonAttr = (pDRXCommonAttr_t)demod -> myCommonAttr; + extAttr = (pDRXJData_t)demod->myExtAttr; + devAddr = demod -> myI2CDevAddr; + + /* Check arguments */ + if ( mode == NULL ) + { + return (DRX_STS_INVALID_ARG); + } + + /* If already in requested power mode, do nothing */ + if ( commonAttr->currentPowerMode == *mode ) + { + return (DRX_STS_OK); + } + + switch ( *mode ) + { + case DRX_POWER_UP: + case DRXJ_POWER_DOWN_MAIN_PATH: + sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_NONE; + break; + case DRXJ_POWER_DOWN_CORE: + sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_CLOCK; + break; + case DRXJ_POWER_DOWN_PLL: + sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_PLL; + break; + case DRX_POWER_DOWN: + sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OSC; + break; + default: + /* Unknow sleep mode */ + return (DRX_STS_INVALID_ARG); + break; + } + + + /* Check if device needs to be powered up */ + if ( ( commonAttr->currentPowerMode != DRX_POWER_UP ) ) + { + CHK_ERROR(PowerUpDevice(demod)); + } + + if ( ( *mode == DRX_POWER_UP ) ) + { + /* Restore analog & pin configuartion */ + } else { + /* Power down to requested mode */ + /* Backup some register settings */ + /* Set pins with possible pull-ups connected to them in input mode */ + /* Analog power down */ + /* ADC power down */ + /* Power down device */ + /* stop all comm_exec */ + /* + Stop and power down previous standard + */ + + switch ( extAttr->standard ) + { + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: + CHK_ERROR( PowerDownQAM(demod, TRUE) ); + break; + case DRX_STANDARD_8VSB: + CHK_ERROR( PowerDownVSB(demod, TRUE) ); + break; + case DRX_STANDARD_PAL_SECAM_BG : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_DK : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_I : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_L : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_LP : /* fallthrough */ + case DRX_STANDARD_NTSC: /* fallthrough */ + case DRX_STANDARD_FM: + CHK_ERROR( PowerDownATV( demod, extAttr->standard, TRUE )); + break; + case DRX_STANDARD_UNKNOWN: + /* Do nothing */ + break; + case DRX_STANDARD_AUTO: /* fallthrough */ + default: + return ( DRX_STS_ERROR ); + } + + if (*mode != DRXJ_POWER_DOWN_MAIN_PATH) + { + WR16( devAddr, SIO_CC_PWD_MODE__A, sioCcPwdMode); + WR16( devAddr, SIO_CC_UPDATE__A , SIO_CC_UPDATE_KEY); + + /* Initialize HI, wakeup key especially before put IC to sleep */ + CHK_ERROR(InitHI(demod) ); + + extAttr -> HICfgCtrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; + CHK_ERROR( HICfgCommand( demod ) ); + } + } + + commonAttr->currentPowerMode = *mode; + + return ( DRX_STS_OK ); +rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t CtrlVersion() +* \brief Report version of microcode and if possible version of device +* \param demod Pointer to demodulator instance. +* \param versionList Pointer to pointer of linked list of versions. +* \return DRXStatus_t. +* +* Using static structures so no allocation of memory is needed. +* Filling in all the fields each time, cause you don't know if they are +* changed by the application. +* +* For device: +* Major version number will be last two digits of family number. +* Minor number will be full respin number +* Patch will be metal fix number+1 +* Examples: +* DRX3942J A2 => number: 42.1.2 text: "DRX3942J:A2" +* DRX3933J B1 => number: 33.2.1 text: "DRX3933J:B1" +* +*/ +static DRXStatus_t +CtrlVersion( pDRXDemodInstance_t demod, + pDRXVersionList_t *versionList ) +{ + pDRXJData_t extAttr = (pDRXJData_t) (NULL); + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) (NULL); + pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t)(NULL); + u16_t ucodeMajorMinor = 0; /* BCD Ma:Ma:Ma:Mi */ + u16_t ucodePatch = 0; /* BCD Pa:Pa:Pa:Pa */ + u16_t major = 0; + u16_t minor = 0; + u16_t patch = 0; + u16_t idx = 0; + u32_t jtag = 0; + u16_t subtype = 0; + u16_t mfx = 0; + u16_t bid = 0; + u16_t key = 0; + + static char ucodeName[] = "Microcode"; + static char deviceName[] = "Device"; + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod -> myExtAttr; + commonAttr = (pDRXCommonAttr_t)demod->myCommonAttr; + + /* Microcode version ****************************************/ + + extAttr->vVersion[0].moduleType = DRX_MODULE_MICROCODE; + extAttr->vVersion[0].moduleName = ucodeName; + extAttr->vVersion[0].vString = extAttr->vText[0]; + + if ( commonAttr->isOpened == TRUE ) + { + SARR16( devAddr, SCU_RAM_VERSION_HI__A, &ucodeMajorMinor ); + SARR16( devAddr, SCU_RAM_VERSION_LO__A, &ucodePatch ); + + /* Translate BCD to numbers and string */ + /* TODO: The most significant Ma and Pa will be ignored, check with spec */ + minor = (ucodeMajorMinor & 0xF); + ucodeMajorMinor >>= 4; + major = (ucodeMajorMinor & 0xF); + ucodeMajorMinor >>= 4; + major += (10* (ucodeMajorMinor & 0xF)); + patch = (ucodePatch & 0xF); + ucodePatch >>= 4; + patch += (10*(ucodePatch & 0xF)); + ucodePatch >>= 4; + patch += (100*(ucodePatch & 0xF)); + } + else + { + /* No microcode uploaded, No Rom existed, set version to 0.0.0 */ + patch = 0; + minor = 0; + major = 0; + } + extAttr->vVersion[0].vMajor = major; + extAttr->vVersion[0].vMinor = minor; + extAttr->vVersion[0].vPatch = patch; + + if ( major/10 != 0 ) + { + extAttr->vVersion[0].vString[idx++] = ((char)(major/10))+'0'; + major %= 10; + } + extAttr->vVersion[0].vString[idx++] = ((char)major)+'0'; + extAttr->vVersion[0].vString[idx++] = '.'; + extAttr->vVersion[0].vString[idx++] = ((char)minor)+'0'; + extAttr->vVersion[0].vString[idx++] = '.'; + if ( patch/100 != 0 ) + { + extAttr->vVersion[0].vString[idx++] = ((char)(patch/100))+'0'; + patch %= 100; + } + if ( patch/10 != 0 ) + { + extAttr->vVersion[0].vString[idx++] = ((char)(patch/10))+'0'; + patch %= 10; + } + extAttr->vVersion[0].vString[idx++] = ((char)patch)+'0'; + extAttr->vVersion[0].vString[idx] = '\0'; + + extAttr->vListElements[0].version = &(extAttr->vVersion[0]); + extAttr->vListElements[0].next = &(extAttr->vListElements[1]); + + + /* Device version ****************************************/ + /* Check device id */ + RR16( devAddr, SIO_TOP_COMM_KEY__A , &key); + WR16( devAddr, SIO_TOP_COMM_KEY__A , 0xFABA); + RR32( devAddr, SIO_TOP_JTAGID_LO__A , &jtag ); + RR16( devAddr, SIO_PDR_UIO_IN_HI__A , &bid); + WR16( devAddr, SIO_TOP_COMM_KEY__A , key); + + extAttr->vVersion[1].moduleType = DRX_MODULE_DEVICE; + extAttr->vVersion[1].moduleName = deviceName; + extAttr->vVersion[1].vString = extAttr->vText[1]; + extAttr->vVersion[1].vString[0] = 'D'; + extAttr->vVersion[1].vString[1] = 'R'; + extAttr->vVersion[1].vString[2] = 'X'; + extAttr->vVersion[1].vString[3] = '3'; + extAttr->vVersion[1].vString[4] = '9'; + extAttr->vVersion[1].vString[7] = 'J'; + extAttr->vVersion[1].vString[8] = ':'; + extAttr->vVersion[1].vString[11] = '\0'; + + /* DRX39xxJ type Ax */ + /* TODO semantics of mfx and spin are unclear */ + subtype = (u16_t)((jtag>>12)&0xFF); + mfx = (u16_t)(jtag>>29); + extAttr->vVersion[1].vMinor = 1; + if (mfx == 0x03) + { + extAttr->vVersion[1].vPatch = mfx+2; + } + else + { + extAttr->vVersion[1].vPatch = mfx+1; + } + extAttr->vVersion[1].vString[6] = ((char)(subtype&0xF))+'0'; + extAttr->vVersion[1].vMajor = (subtype & 0x0F); + subtype>>=4; + extAttr->vVersion[1].vString[5] = ((char)(subtype&0xF))+'0'; + extAttr->vVersion[1].vMajor += 10*subtype; + extAttr->vVersion[1].vString[9] = 'A'; + if (mfx == 0x03) + { + extAttr->vVersion[1].vString[10] = ((char)(mfx&0xF)) + '2' ; + } + else + { + extAttr->vVersion[1].vString[10] = ((char)(mfx&0xF)) + '1' ; + } + + extAttr->vListElements[1].version = &(extAttr->vVersion[1]); + extAttr->vListElements[1].next = (pDRXVersionList_t)(NULL); + + *versionList = &(extAttr->vListElements[0]); + + return ( DRX_STS_OK ); + + rw_error: + *versionList = (pDRXVersionList_t)(NULL); + return (DRX_STS_ERROR); + +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t CtrlProbeDevice() +* \brief Probe device, check if it is present +* \param demod Pointer to demodulator instance. +* \return DRXStatus_t. +* \retval DRX_STS_OK a drx39xxj device has been detected. +* \retval DRX_STS_ERROR no drx39xxj device detected. +* +* This funtion can be caled before open() and after close(). +* +*/ + +static DRXStatus_t +CtrlProbeDevice( pDRXDemodInstance_t demod ) +{ + DRXPowerMode_t orgPowerMode = DRX_POWER_UP; + DRXStatus_t retStatus = DRX_STS_OK; + pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t)(NULL); + + commonAttr = (pDRXCommonAttr_t)demod -> myCommonAttr; + + if ( commonAttr->isOpened == FALSE || commonAttr->currentPowerMode != DRX_POWER_UP) + { + pI2CDeviceAddr_t devAddr = NULL; + DRXPowerMode_t powerMode = DRX_POWER_UP; + u32_t jtag = 0; + + devAddr = demod -> myI2CDevAddr; + + /* Remeber original power mode */ + orgPowerMode = commonAttr->currentPowerMode; + + if(demod->myCommonAttr->isOpened == FALSE) + { + CHK_ERROR(PowerUpDevice(demod)); + commonAttr->currentPowerMode = DRX_POWER_UP; + } + else + { + /* Wake-up device, feedback from device */ + CHK_ERROR( CtrlPowerMode( demod, &powerMode )); + } + /* Initialize HI, wakeup key especially */ + CHK_ERROR(InitHI(demod) ); + + /* Check device id */ + RR32( devAddr, SIO_TOP_JTAGID_LO__A , &jtag); + jtag = (jtag>>12) & 0xFFFF; + switch ( jtag ) + { + case 0x3931: /* fallthrough */ + case 0x3932: /* fallthrough */ + case 0x3933: /* fallthrough */ + case 0x3934: /* fallthrough */ + case 0x3941: /* fallthrough */ + case 0x3942: /* fallthrough */ + case 0x3943: /* fallthrough */ + case 0x3944: /* fallthrough */ + case 0x3945: /* fallthrough */ + case 0x3946: + /* ok , do nothing */ + break; + default: + retStatus = DRX_STS_ERROR; + break; + } + + /* Device was not opened, return to orginal powermode, + feedback from device */ + CHK_ERROR( CtrlPowerMode( demod, &orgPowerMode )); + } + else + { + /* dummy read to make this function fail in case device + suddenly disappears after a succesful DRX_Open */ + DUMMY_READ(); + } + + return ( retStatus ); + + rw_error: + commonAttr->currentPowerMode=orgPowerMode; + return (DRX_STS_ERROR); +} + +#ifdef DRXJ_SPLIT_UCODE_UPLOAD +/*============================================================================*/ + +/** +* \fn DRXStatus_t IsMCBlockAudio() +* \brief Check if MC block is Audio or not Audio. +* \param addr Pointer to demodulator instance. +* \param audioUpload TRUE if MC block is Audio + FALSE if MC block not Audio +* \return Bool_t. +*/ +Bool_t IsMCBlockAudio( u32_t addr ) +{ + if ( ( addr == AUD_XFP_PRAM_4K__A ) || + ( addr == AUD_XDFP_PRAM_4K__A ) ) + { + return ( TRUE ); + } + return ( FALSE ); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t CtrlUCodeUpload() +* \brief Handle Audio or !Audio part of microcode upload. +* \param demod Pointer to demodulator instance. +* \param mcInfo Pointer to information about microcode data. +* \param action Either UCODE_UPLOAD or UCODE_VERIFY. +* \param uploadAudioMC TRUE if Audio MC need to be uploaded. + FALSE if !Audio MC need to be uploaded. +* \return DRXStatus_t. +*/ +static DRXStatus_t +CtrlUCodeUpload( pDRXDemodInstance_t demod, + pDRXUCodeInfo_t mcInfo, + DRXUCodeAction_t action, + Bool_t uploadAudioMC ) +{ + u16_t i = 0; + u16_t mcNrOfBlks = 0; + u16_t mcMagicWord = 0; + pu8_t mcData = (pu8_t)(NULL); + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)(NULL); + pDRXJData_t extAttr = (pDRXJData_t)(NULL); + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod -> myExtAttr; + + /* Check arguments */ + if ( ( mcInfo == NULL ) || + ( mcInfo->mcData == NULL ) || + ( mcInfo->mcSize == 0 ) ) + { + return DRX_STS_INVALID_ARG; + } + + mcData = mcInfo->mcData; + + /* Check data */ + mcMagicWord = UCodeRead16( mcData ); + mcData += sizeof( u16_t ); + mcNrOfBlks = UCodeRead16( mcData ); + mcData += sizeof( u16_t ); + + if ( ( mcMagicWord != DRXJ_UCODE_MAGIC_WORD ) || + ( mcNrOfBlks == 0 ) ) + { + /* wrong endianess or wrong data ? */ + return DRX_STS_INVALID_ARG; + } + + /* Process microcode blocks */ + for( i = 0 ; i 0x7FFF ) || + ( (( blockHdr.flags & DRXJ_UCODE_CRC_FLAG ) != 0) && + ( blockHdr.CRC != UCodeComputeCRC( mcData, blockHdr.size)) ) + ) + { + /* Wrong data ! */ + return DRX_STS_INVALID_ARG; + } + + mcBlockNrBytes = blockHdr.size * sizeof(u16_t); + + /* Perform the desired action */ + /* Check which part of MC need to be uploaded - Audio or not Audio */ + if( IsMCBlockAudio( blockHdr.addr ) == uploadAudioMC ) + { + switch ( action ) { + /*===================================================================*/ + case UCODE_UPLOAD : + { + /* Upload microcode */ + if ( demod->myAccessFunct->writeBlockFunc( + devAddr, + (DRXaddr_t) blockHdr.addr, + mcBlockNrBytes, + mcData, + 0x0000) != DRX_STS_OK) + { + return (DRX_STS_ERROR); + } + }; + break; + + /*===================================================================*/ + case UCODE_VERIFY : + { + int result = 0; + u8_t mcDataBuffer[DRXJ_UCODE_MAX_BUF_SIZE]; + u32_t bytesToCompare=0; + u32_t bytesLeftToCompare=0; + DRXaddr_t currAddr = (DRXaddr_t)0; + pu8_t currPtr =NULL; + + bytesLeftToCompare = mcBlockNrBytes; + currAddr = blockHdr.addr; + currPtr = mcData; + + while( bytesLeftToCompare != 0 ) + { + if (bytesLeftToCompare > ((u32_t)DRXJ_UCODE_MAX_BUF_SIZE) ) + { + bytesToCompare = ((u32_t)DRXJ_UCODE_MAX_BUF_SIZE); + } else { + bytesToCompare = bytesLeftToCompare; + } + + if ( demod->myAccessFunct->readBlockFunc( + devAddr, + currAddr, + (u16_t)bytesToCompare, + (pu8_t)mcDataBuffer, + 0x0000) != DRX_STS_OK) + { + return (DRX_STS_ERROR); + } + + result = DRXBSP_HST_Memcmp( currPtr, + mcDataBuffer, + bytesToCompare); + + if ( result != 0 ) + { + return (DRX_STS_ERROR); + }; + + currAddr += ((DRXaddr_t)(bytesToCompare/2)); + currPtr = &(currPtr[bytesToCompare]); + bytesLeftToCompare -= ((u32_t)bytesToCompare); + } /* while( bytesToCompare > DRXJ_UCODE_MAX_BUF_SIZE ) */ + }; + break; + + /*===================================================================*/ + default: + return DRX_STS_INVALID_ARG; + break; + + } /* switch ( action ) */ + } /* if( IsMCBlockAudio( blockHdr.addr ) == uploadAudioMC ) */ + + /* Next block */ + mcData += mcBlockNrBytes; + } /* for( i = 0 ; iflagAudMcUploaded = FALSE; + } + + return (DRX_STS_OK); +} +#endif /* DRXJ_SPLIT_UCODE_UPLOAD */ + +/*============================================================================*/ +/*== CTRL Set/Get Config related functions ===================================*/ +/*============================================================================*/ + +/*===== SigStrength() =========================================================*/ +/** +* \fn DRXStatus_t CtrlSigStrength() +* \brief Retrieve signal strength. +* \param devmod Pointer to demodulator instance. +* \param sigQuality Pointer to signal strength data; range 0, .. , 100. +* \return DRXStatus_t. +* \retval DRX_STS_OK sigStrength contains valid data. +* \retval DRX_STS_INVALID_ARG sigStrength is NULL. +* \retval DRX_STS_ERROR Erroneous data, sigStrength contains invalid data. + +*/ +static DRXStatus_t +CtrlSigStrength( pDRXDemodInstance_t demod, + pu16_t sigStrength ) +{ + pDRXJData_t extAttr = NULL; + DRXStandard_t standard = DRX_STANDARD_UNKNOWN; + + /* Check arguments */ + if ( ( sigStrength == NULL ) || + ( demod == NULL ) ) + { + return (DRX_STS_INVALID_ARG); + } + + extAttr = (pDRXJData_t)demod->myExtAttr; + standard = extAttr->standard; + *sigStrength = 0; + + /* Signal strength indication for each standard */ + switch ( standard ) { + case DRX_STANDARD_8VSB: /* fallthrough */ +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: +#endif + CHK_ERROR( GetSigStrength( demod, sigStrength ) ); + break; +#ifndef DRXJ_DIGITAL_ONLY + case DRX_STANDARD_PAL_SECAM_BG : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_DK : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_I : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_L : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_LP : /* fallthrough */ + case DRX_STANDARD_NTSC: /* fallthrough */ + case DRX_STANDARD_FM: + CHK_ERROR( GetAtvSigStrength( demod, sigStrength ) ); + break; +#endif + case DRX_STANDARD_UNKNOWN: /* fallthrough */ + default: + return (DRX_STS_INVALID_ARG); + } + + /* TODO */ + /* find out if signal strength is calculated in the same way for all standards */ + return (DRX_STS_OK); + rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================*/ +/** +* \fn DRXStatus_t CtrlGetCfgOOBMisc() +* \brief Get current state information of OOB. +* \param pointer to DRXJCfgOOBMisc_t. +* \return DRXStatus_t. +* +*/ +#ifndef DRXJ_DIGITAL_ONLY +static DRXStatus_t +CtrlGetCfgOOBMisc ( pDRXDemodInstance_t demod, pDRXJCfgOOBMisc_t misc ) +{ + pI2CDeviceAddr_t devAddr = NULL; + u16_t lock = 0U; + u16_t state = 0U; + u16_t data = 0U; + u16_t digitalAGCMant = 0U; + u16_t digitalAGCExp = 0U; + + /* check arguments */ + if ( misc == NULL ) + { + return (DRX_STS_INVALID_ARG); + } + devAddr = demod -> myI2CDevAddr; + + /* TODO */ + /* check if the same registers are used for all standards (QAM/VSB/ATV) */ + RR16( devAddr, ORX_NSU_TUN_IFGAIN_W__A, &misc->agc.IFAGC ); + RR16( devAddr, ORX_NSU_TUN_RFGAIN_W__A, &misc->agc.RFAGC ); + RR16( devAddr, ORX_FWP_SRC_DGN_W__A, &data ); + + digitalAGCMant = data & ORX_FWP_SRC_DGN_W_MANT__M; + digitalAGCExp = (data & ORX_FWP_SRC_DGN_W_EXP__M) + >> ORX_FWP_SRC_DGN_W_EXP__B; + misc->agc.DigitalAGC = digitalAGCMant << digitalAGCExp; + + SARR16( devAddr, SCU_RAM_ORX_SCU_LOCK__A, &lock ); + + misc->anaGainLock = ((lock & 0x0001)?TRUE:FALSE); + misc->digGainLock = ((lock & 0x0002)?TRUE:FALSE); + misc->freqLock = ((lock & 0x0004)?TRUE:FALSE); + misc->phaseLock = ((lock & 0x0008)?TRUE:FALSE); + misc->symTimingLock = ((lock & 0x0010)?TRUE:FALSE); + misc->eqLock = ((lock & 0x0020)?TRUE:FALSE); + + SARR16( devAddr, SCU_RAM_ORX_SCU_STATE__A, &state ); + misc->state = (state>>8) & 0xff; + + return ( DRX_STS_OK ); +rw_error: + return (DRX_STS_ERROR); +} +#endif + +/** +* \fn DRXStatus_t CtrlGetCfgVSBMisc() +* \brief Get current state information of OOB. +* \param pointer to DRXJCfgOOBMisc_t. +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +CtrlGetCfgVSBMisc ( pDRXDemodInstance_t demod, pDRXJCfgVSBMisc_t misc ) +{ + pI2CDeviceAddr_t devAddr = NULL; + + /* check arguments */ + if ( misc == NULL ) + { + return (DRX_STS_INVALID_ARG); + } + devAddr = demod -> myI2CDevAddr; + + CHK_ERROR(GetVSBSymbErr(devAddr, &misc->symbError)); + + return ( DRX_STS_OK ); +rw_error: + return (DRX_STS_ERROR); +} +/*============================================================================*/ + +/** +* \fn DRXStatus_t CtrlSetCfgAgcIf() +* \brief Set IF AGC. +* \param demod demod instance +* \param agcSettings If agc configuration +* \return DRXStatus_t. +* +* Check arguments +* Dispatch handling to standard specific function. +* +*/ +static DRXStatus_t +CtrlSetCfgAgcIf ( pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings ) +{ + /* check arguments */ + if ( agcSettings == NULL ) + { + return ( DRX_STS_INVALID_ARG ); + } + + switch ( agcSettings->ctrlMode ) { + case DRX_AGC_CTRL_AUTO: /* fallthrough */ + case DRX_AGC_CTRL_USER: /* fallthrough */ + case DRX_AGC_CTRL_OFF: /* fallthrough */ + break; + default: + return ( DRX_STS_INVALID_ARG ); + } + + /* Distpatch */ + switch ( agcSettings->standard ) { + case DRX_STANDARD_8VSB: /* fallthrough */ +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: +#endif +#ifndef DRXJ_DIGITAL_ONLY + case DRX_STANDARD_PAL_SECAM_BG : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_DK : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_I : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_L : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_LP : /* fallthrough */ + case DRX_STANDARD_NTSC: /* fallthrough */ + case DRX_STANDARD_FM: +#endif + return SetAgcIf ( demod, agcSettings, TRUE); + case DRX_STANDARD_UNKNOWN: + default: + return ( DRX_STS_INVALID_ARG ); + } + + return ( DRX_STS_OK ); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t CtrlGetCfgAgcIf() +* \brief Retrieve IF AGC settings. +* \param demod demod instance +* \param agcSettings If agc configuration +* \return DRXStatus_t. +* +* Check arguments +* Dispatch handling to standard specific function. +* +*/ +static DRXStatus_t +CtrlGetCfgAgcIf ( pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings ) +{ + /* check arguments */ + if ( agcSettings == NULL ) + { + return ( DRX_STS_INVALID_ARG ); + } + + /* Distpatch */ + switch ( agcSettings->standard ) { + case DRX_STANDARD_8VSB: /* fallthrough */ +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: +#endif +#ifndef DRXJ_DIGITAL_ONLY + case DRX_STANDARD_PAL_SECAM_BG : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_DK : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_I : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_L : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_LP : /* fallthrough */ + case DRX_STANDARD_NTSC: /* fallthrough */ + case DRX_STANDARD_FM: +#endif + return GetAgcIf ( demod, agcSettings); + case DRX_STANDARD_UNKNOWN: + default: + return ( DRX_STS_INVALID_ARG ); + } + + return ( DRX_STS_OK ); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t CtrlSetCfgAgcRf() +* \brief Set RF AGC. +* \param demod demod instance +* \param agcSettings rf agc configuration +* \return DRXStatus_t. +* +* Check arguments +* Dispatch handling to standard specific function. +* +*/ +static DRXStatus_t +CtrlSetCfgAgcRf ( pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings ) +{ + /* check arguments */ + if ( agcSettings == NULL ) + { + return ( DRX_STS_INVALID_ARG ); + } + + switch ( agcSettings->ctrlMode ) { + case DRX_AGC_CTRL_AUTO: /* fallthrough */ + case DRX_AGC_CTRL_USER: /* fallthrough */ + case DRX_AGC_CTRL_OFF: + break; + default: + return ( DRX_STS_INVALID_ARG ); + } + + /* Distpatch */ + switch ( agcSettings->standard ) { + case DRX_STANDARD_8VSB: /* fallthrough */ +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: +#endif +#ifndef DRXJ_DIGITAL_ONLY + case DRX_STANDARD_PAL_SECAM_BG : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_DK : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_I : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_L : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_LP : /* fallthrough */ + case DRX_STANDARD_NTSC: /* fallthrough */ + case DRX_STANDARD_FM: +#endif + return SetAgcRf ( demod, agcSettings, TRUE); + case DRX_STANDARD_UNKNOWN: + default: + return ( DRX_STS_INVALID_ARG ); + } + + return ( DRX_STS_OK ); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t CtrlGetCfgAgcRf() +* \brief Retrieve RF AGC settings. +* \param demod demod instance +* \param agcSettings Rf agc configuration +* \return DRXStatus_t. +* +* Check arguments +* Dispatch handling to standard specific function. +* +*/ +static DRXStatus_t +CtrlGetCfgAgcRf ( pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings ) +{ + /* check arguments */ + if ( agcSettings == NULL ) + { + return ( DRX_STS_INVALID_ARG ); + } + + /* Distpatch */ + switch ( agcSettings->standard ) { + case DRX_STANDARD_8VSB: /* fallthrough */ +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: +#endif +#ifndef DRXJ_DIGITAL_ONLY + case DRX_STANDARD_PAL_SECAM_BG : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_DK : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_I : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_L : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_LP : /* fallthrough */ + case DRX_STANDARD_NTSC: /* fallthrough */ + case DRX_STANDARD_FM: +#endif + return GetAgcRf ( demod, agcSettings); + case DRX_STANDARD_UNKNOWN: + default: + return ( DRX_STS_INVALID_ARG ); + } + + return ( DRX_STS_OK ); +} + + +/*============================================================================*/ + +/** +* \fn DRXStatus_t CtrlGetCfgAgcInternal() +* \brief Retrieve internal AGC value. +* \param demod demod instance +* \param u16_t +* \return DRXStatus_t. +* +* Check arguments +* Dispatch handling to standard specific function. +* +*/ +static DRXStatus_t +CtrlGetCfgAgcInternal ( pDRXDemodInstance_t demod, pu16_t agcInternal ) +{ + pI2CDeviceAddr_t devAddr = NULL; + DRXLockStatus_t lockStatus = DRX_NOT_LOCKED; + pDRXJData_t extAttr = NULL; + u16_t iqmCfScaleSh = 0; + u16_t iqmCfPower = 0; + u16_t iqmCfAmp = 0; + u16_t iqmCfGain = 0; + + /* check arguments */ + if ( agcInternal == NULL ) + { + return ( DRX_STS_INVALID_ARG ); + } + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + CHK_ERROR( CtrlLockStatus( demod, &lockStatus) ); + if ( lockStatus != DRXJ_DEMOD_LOCK && lockStatus != DRX_LOCKED ) + { + *agcInternal = 0; + return DRX_STS_OK; + } + + /* Distpatch */ + switch ( extAttr->standard ) { + case DRX_STANDARD_8VSB: + iqmCfGain = 57; + break; +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: + switch ( extAttr->constellation ) + { + case DRX_CONSTELLATION_QAM256: + case DRX_CONSTELLATION_QAM128: + case DRX_CONSTELLATION_QAM32: + case DRX_CONSTELLATION_QAM16: + iqmCfGain = 57; + break; + case DRX_CONSTELLATION_QAM64: + iqmCfGain = 56; + break; + default: + return (DRX_STS_ERROR); + } + break; +#endif + default: + return ( DRX_STS_INVALID_ARG ); + } + + RR16( devAddr, IQM_CF_POW__A, &iqmCfPower); + RR16( devAddr, IQM_CF_SCALE_SH__A, &iqmCfScaleSh); + RR16( devAddr, IQM_CF_AMP__A, &iqmCfAmp); + /* IQM_CF_PWR_CORRECTION_dB = 3; + P5dB =10*log10(IQM_CF_POW)+12-6*9-IQM_CF_PWR_CORRECTION_dB; */ + /* P4dB = P5dB -20*log10(IQM_CF_AMP)-6*10 + -IQM_CF_Gain_dB-18+6*(27-IQM_CF_SCALE_SH*2-10) + +6*7+10*log10(1+0.115/4); */ + /* PadcdB = P4dB +3 -6 +60; dBmV */ + *agcInternal = (u16_t) ( Log10Times100 (iqmCfPower) + - 2 * Log10Times100 (iqmCfAmp) + - iqmCfGain + - 120 * iqmCfScaleSh + + 781 ); + + return ( DRX_STS_OK ); +rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t CtrlSetCfgPreSaw() +* \brief Set Pre-saw reference. +* \param demod demod instance +* \param pu16_t +* \return DRXStatus_t. +* +* Check arguments +* Dispatch handling to standard specific function. +* +*/ +static DRXStatus_t +CtrlSetCfgPreSaw ( pDRXDemodInstance_t demod, pDRXJCfgPreSaw_t preSaw ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* check arguments */ + if ( ( preSaw == NULL ) || + ( preSaw->reference > IQM_AF_PDREF__M ) + ) + { + return ( DRX_STS_INVALID_ARG ); + } + + /* Only if standard is currently active*/ + if ( ( extAttr->standard == preSaw->standard ) || + ( DRXJ_ISQAMSTD( extAttr->standard ) && + DRXJ_ISQAMSTD( preSaw->standard ) ) || + ( DRXJ_ISATVSTD( extAttr->standard ) && + DRXJ_ISATVSTD( preSaw->standard ) ) ) + { + WR16( devAddr, IQM_AF_PDREF__A , preSaw->reference); + } + + /* Store pre-saw settings */ + switch ( preSaw->standard){ + case DRX_STANDARD_8VSB: + extAttr->vsbPreSawCfg = *preSaw; + break; +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: + extAttr->qamPreSawCfg = *preSaw; + break; +#endif +#ifndef DRXJ_DIGITAL_ONLY + case DRX_STANDARD_PAL_SECAM_BG : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_DK : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_I : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_L : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_LP : /* fallthrough */ + case DRX_STANDARD_NTSC: /* fallthrough */ + case DRX_STANDARD_FM: + extAttr->atvPreSawCfg = *preSaw; + break; +#endif + default: + return (DRX_STS_INVALID_ARG); + } + + return ( DRX_STS_OK ); +rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t CtrlSetCfgAfeGain() +* \brief Set AFE Gain. +* \param demod demod instance +* \param pu16_t +* \return DRXStatus_t. +* +* Check arguments +* Dispatch handling to standard specific function. +* +*/ +static DRXStatus_t +CtrlSetCfgAfeGain ( pDRXDemodInstance_t demod, pDRXJCfgAfeGain_t afeGain ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + u8_t gain = 0; + + /* check arguments */ + if ( afeGain == NULL ) + { + return (DRX_STS_INVALID_ARG); + } + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + switch ( afeGain->standard){ + case DRX_STANDARD_8VSB: /* fallthrough */ +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: +#endif + /* Do nothing */ + break; + default: + return (DRX_STS_INVALID_ARG); + } + + /* TODO PGA gain is also written by microcode (at least by QAM and VSB) + So I (PJ) think interface requires choice between auto, user mode */ + + if (afeGain->gain >= 329) + gain = 15; + else if (afeGain->gain <= 147) + gain = 0; + else + gain = (afeGain->gain - 140 + 6) / 13; + + /* Only if standard is currently active*/ + if( extAttr->standard == afeGain->standard ) + WR16( devAddr, IQM_AF_PGA_GAIN__A, gain); + + /* Store AFE Gain settings */ + switch ( afeGain->standard){ + case DRX_STANDARD_8VSB: + extAttr->vsbPgaCfg = gain * 13 + 140; + break; +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: + extAttr->qamPgaCfg = gain * 13 + 140; + break; +#endif + default: + return (DRX_STS_ERROR); + } + + return ( DRX_STS_OK ); +rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t CtrlGetCfgPreSaw() +* \brief Get Pre-saw reference setting. +* \param demod demod instance +* \param pu16_t +* \return DRXStatus_t. +* +* Check arguments +* Dispatch handling to standard specific function. +* +*/ +static DRXStatus_t +CtrlGetCfgPreSaw ( pDRXDemodInstance_t demod, pDRXJCfgPreSaw_t preSaw ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + + /* check arguments */ + if ( preSaw == NULL ) + { + return ( DRX_STS_INVALID_ARG ); + } + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + switch ( preSaw->standard ){ + case DRX_STANDARD_8VSB: + *preSaw = extAttr->vsbPreSawCfg; + break; +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: + *preSaw = extAttr->qamPreSawCfg; + break; +#endif +#ifndef DRXJ_DIGITAL_ONLY + case DRX_STANDARD_PAL_SECAM_BG : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_DK : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_I : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_L : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_LP : /* fallthrough */ + case DRX_STANDARD_NTSC: + extAttr->atvPreSawCfg.standard = DRX_STANDARD_NTSC; + *preSaw = extAttr->atvPreSawCfg; + break; + case DRX_STANDARD_FM: + extAttr->atvPreSawCfg.standard = DRX_STANDARD_FM; + *preSaw = extAttr->atvPreSawCfg; + break; +#endif + default: + return (DRX_STS_INVALID_ARG); + } + + return ( DRX_STS_OK ); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t CtrlGetCfgAfeGain() +* \brief Get AFE Gain. +* \param demod demod instance +* \param pu16_t +* \return DRXStatus_t. +* +* Check arguments +* Dispatch handling to standard specific function. +* +*/ +static DRXStatus_t +CtrlGetCfgAfeGain ( pDRXDemodInstance_t demod, pDRXJCfgAfeGain_t afeGain ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + + /* check arguments */ + if ( afeGain == NULL ) + { + return ( DRX_STS_INVALID_ARG ); + } + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + switch ( afeGain->standard){ + case DRX_STANDARD_8VSB: + afeGain->gain = extAttr->vsbPgaCfg; + break; +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: + afeGain->gain = extAttr->qamPgaCfg; + break; +#endif + default: + return (DRX_STS_INVALID_ARG); + } + + return ( DRX_STS_OK ); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t CtrlGetFecMeasSeqCount() +* \brief Get FEC measurement sequnce number. +* \param demod demod instance +* \param pu16_t +* \return DRXStatus_t. +* +* Check arguments +* Dispatch handling to standard specific function. +* +*/ +static DRXStatus_t +CtrlGetFecMeasSeqCount ( pDRXDemodInstance_t demod, pu16_t fecMeasSeqCount) +{ + /* check arguments */ + if ( fecMeasSeqCount == NULL ) + { + return ( DRX_STS_INVALID_ARG ); + } + + RR16 ( demod->myI2CDevAddr, SCU_RAM_FEC_MEAS_COUNT__A, fecMeasSeqCount ); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} +/*============================================================================*/ + +/** +* \fn DRXStatus_t CtrlGetAccumCrRSCwErr() +* \brief Get accumulative corrected RS codeword number. +* \param demod demod instance +* \param pu32_t +* \return DRXStatus_t. +* +* Check arguments +* Dispatch handling to standard specific function. +* +*/ +static DRXStatus_t +CtrlGetAccumCrRSCwErr ( pDRXDemodInstance_t demod, pu32_t accumCrRsCWErr) +{ + if(accumCrRsCWErr == NULL) + { + return (DRX_STS_INVALID_ARG); + } + + RR32 ( demod->myI2CDevAddr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, accumCrRsCWErr ); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/** +* \fn DRXStatus_t CtrlSetCfg() +* \brief Set 'some' configuration of the device. +* \param devmod Pointer to demodulator instance. +* \param config Pointer to configuration parameters (type and data). +* \return DRXStatus_t. + +*/ +static DRXStatus_t +CtrlSetCfg( pDRXDemodInstance_t demod, + pDRXCfg_t config ) +{ + if ( config == NULL ) + { + return (DRX_STS_INVALID_ARG); + } + + DUMMY_READ(); + switch ( config->cfgType ) + { + case DRX_CFG_MPEG_OUTPUT: + return CtrlSetCfgMPEGOutput( demod, (pDRXCfgMPEGOutput_t) config->cfgData ); + case DRX_CFG_PINS_SAFE_MODE: + return CtrlSetCfgPdrSafeMode( demod, (pBool_t) config->cfgData ); + case DRXJ_CFG_AGC_RF: + return CtrlSetCfgAgcRf ( demod, (pDRXJCfgAgc_t) config->cfgData ); + case DRXJ_CFG_AGC_IF: + return CtrlSetCfgAgcIf ( demod, (pDRXJCfgAgc_t) config->cfgData ); + case DRXJ_CFG_PRE_SAW: + return CtrlSetCfgPreSaw ( demod, (pDRXJCfgPreSaw_t) config->cfgData ); + case DRXJ_CFG_AFE_GAIN: + return CtrlSetCfgAfeGain ( demod, (pDRXJCfgAfeGain_t) config->cfgData ); + case DRXJ_CFG_SMART_ANT: + return CtrlSetCfgSmartAnt ( demod, (pDRXJCfgSmartAnt_t)(config->cfgData) ); + case DRXJ_CFG_RESET_PACKET_ERR: + return CtrlSetCfgResetPktErr ( demod ); +#ifndef DRXJ_DIGITAL_ONLY + case DRXJ_CFG_OOB_PRE_SAW: + return CtrlSetCfgOOBPreSAW ( demod, (pu16_t)(config->cfgData) ); + case DRXJ_CFG_OOB_LO_POW: + return CtrlSetCfgOOBLoPower ( demod, (pDRXJCfgOobLoPower_t)(config->cfgData) ); + case DRXJ_CFG_ATV_MISC: + return CtrlSetCfgAtvMisc( demod, (pDRXJCfgAtvMisc_t) config->cfgData ); + case DRXJ_CFG_ATV_EQU_COEF: + return CtrlSetCfgAtvEquCoef( demod, + (pDRXJCfgAtvEquCoef_t) config->cfgData ); + case DRXJ_CFG_ATV_OUTPUT: + return CtrlSetCfgATVOutput( demod, + (pDRXJCfgAtvOutput_t) config->cfgData ); +#endif + case DRXJ_CFG_MPEG_OUTPUT_MISC: + return CtrlSetCfgMpegOutputMisc( demod, + (pDRXJCfgMpegOutputMisc_t) config->cfgData ); +#ifndef DRXJ_EXCLUDE_AUDIO + case DRX_CFG_AUD_VOLUME: + return AUDCtrlSetCfgVolume( demod, + (pDRXCfgAudVolume_t)config->cfgData ); + case DRX_CFG_I2S_OUTPUT: + return AUDCtrlSetCfgOutputI2S( demod, + (pDRXCfgI2SOutput_t)config->cfgData ); + case DRX_CFG_AUD_AUTOSOUND: + return AUDCtrSetlCfgAutoSound( demod, + (pDRXCfgAudAutoSound_t) + config->cfgData); + case DRX_CFG_AUD_ASS_THRES: + return AUDCtrlSetCfgASSThres( demod, + (pDRXCfgAudASSThres_t) + config->cfgData); + case DRX_CFG_AUD_CARRIER: + return AUDCtrlSetCfgCarrier( demod, + (pDRXCfgAudCarriers_t)config->cfgData); + case DRX_CFG_AUD_DEVIATION: + return AUDCtrlSetCfgDev( demod, + (pDRXCfgAudDeviation_t)config->cfgData); + case DRX_CFG_AUD_PRESCALE: + return AUDCtrlSetCfgPrescale( demod, + (pDRXCfgAudPrescale_t)config->cfgData); + case DRX_CFG_AUD_MIXER: + return AUDCtrlSetCfgMixer( demod, + (pDRXCfgAudMixer_t)config->cfgData); + case DRX_CFG_AUD_AVSYNC: + return AUDCtrlSetCfgAVSync( demod, + (pDRXCfgAudAVSync_t)config->cfgData); + +#endif + default: + return (DRX_STS_INVALID_ARG); + } + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t CtrlGetCfg() +* \brief Get 'some' configuration of the device. +* \param devmod Pointer to demodulator instance. +* \param config Pointer to configuration parameters (type and data). +* \return DRXStatus_t. +*/ + +static DRXStatus_t +CtrlGetCfg( pDRXDemodInstance_t demod, + pDRXCfg_t config ) +{ + if ( config == NULL ) + { + return (DRX_STS_INVALID_ARG); + } + + DUMMY_READ(); + + switch ( config->cfgType ) + { + case DRX_CFG_MPEG_OUTPUT: + return CtrlGetCfgMPEGOutput( demod, + (pDRXCfgMPEGOutput_t) config->cfgData ); + case DRX_CFG_PINS_SAFE_MODE: + return CtrlGetCfgPdrSafeMode( demod, (pBool_t) config->cfgData ); + case DRXJ_CFG_AGC_RF: + return CtrlGetCfgAgcRf ( demod, (pDRXJCfgAgc_t) config->cfgData ); + case DRXJ_CFG_AGC_IF: + return CtrlGetCfgAgcIf ( demod, (pDRXJCfgAgc_t) config->cfgData ); + case DRXJ_CFG_AGC_INTERNAL: + return CtrlGetCfgAgcInternal ( demod, (pu16_t) config->cfgData ); + case DRXJ_CFG_PRE_SAW: + return CtrlGetCfgPreSaw ( demod, (pDRXJCfgPreSaw_t) config->cfgData ); + case DRXJ_CFG_AFE_GAIN: + return CtrlGetCfgAfeGain ( demod, (pDRXJCfgAfeGain_t) config->cfgData ); + case DRXJ_CFG_ACCUM_CR_RS_CW_ERR: + return CtrlGetAccumCrRSCwErr ( demod, (pu32_t) config->cfgData ); + case DRXJ_CFG_FEC_MERS_SEQ_COUNT: + return CtrlGetFecMeasSeqCount ( demod, (pu16_t) config->cfgData ); + case DRXJ_CFG_VSB_MISC: + return CtrlGetCfgVSBMisc ( demod, (pDRXJCfgVSBMisc_t) config->cfgData ); + case DRXJ_CFG_SYMBOL_CLK_OFFSET: + return CtrlGetCfgSymbolClockOffset ( demod, (ps32_t) config->cfgData ); +#ifndef DRXJ_DIGITAL_ONLY + case DRXJ_CFG_OOB_MISC: + return CtrlGetCfgOOBMisc ( demod, (pDRXJCfgOOBMisc_t) config->cfgData ); + case DRXJ_CFG_OOB_PRE_SAW: + return CtrlGetCfgOOBPreSAW ( demod, (pu16_t)(config->cfgData) ); + case DRXJ_CFG_OOB_LO_POW: + return CtrlGetCfgOOBLoPower ( demod, (pDRXJCfgOobLoPower_t)(config->cfgData) ); + case DRXJ_CFG_ATV_EQU_COEF: + return CtrlGetCfgAtvEquCoef( demod, + (pDRXJCfgAtvEquCoef_t) config->cfgData ); + case DRXJ_CFG_ATV_MISC: + return CtrlGetCfgAtvMisc( demod, (pDRXJCfgAtvMisc_t) config->cfgData ); + case DRXJ_CFG_ATV_OUTPUT: + return CtrlGetCfgAtvOutput( demod, + (pDRXJCfgAtvOutput_t) config->cfgData ); + case DRXJ_CFG_ATV_AGC_STATUS: + return CtrlGetCfgAtvAgcStatus( demod, + (pDRXJCfgAtvAgcStatus_t) config->cfgData ); +#endif + case DRXJ_CFG_MPEG_OUTPUT_MISC: + return CtrlGetCfgMpegOutputMisc( demod, + (pDRXJCfgMpegOutputMisc_t) config->cfgData ); + case DRXJ_CFG_HW_CFG: + return CtrlGetCfgHwCfg( demod, + (pDRXJCfgHwCfg_t) config->cfgData ); +#ifndef DRXJ_EXCLUDE_AUDIO + case DRX_CFG_AUD_VOLUME: + return AUDCtrlGetCfgVolume ( demod, + (pDRXCfgAudVolume_t)config->cfgData ); + case DRX_CFG_I2S_OUTPUT: + return AUDCtrlGetCfgOutputI2S ( demod, + (pDRXCfgI2SOutput_t)config->cfgData ); + + case DRX_CFG_AUD_RDS: + return AUDCtrlGetCfgRDS ( demod, + (pDRXCfgAudRDS_t)config->cfgData ); + case DRX_CFG_AUD_AUTOSOUND: + return AUDCtrlGetCfgAutoSound ( demod, + (pDRXCfgAudAutoSound_t)config->cfgData); + case DRX_CFG_AUD_ASS_THRES: + return AUDCtrlGetCfgASSThres ( demod, + (pDRXCfgAudASSThres_t)config->cfgData); + case DRX_CFG_AUD_CARRIER: + return AUDCtrlGetCfgCarrier ( demod, + (pDRXCfgAudCarriers_t)config->cfgData); + case DRX_CFG_AUD_DEVIATION: + return AUDCtrlGetCfgDev ( demod, + (pDRXCfgAudDeviation_t)config->cfgData); + case DRX_CFG_AUD_PRESCALE: + return AUDCtrlGetCfgPrescale ( demod, + (pDRXCfgAudPrescale_t)config->cfgData); + case DRX_CFG_AUD_MIXER: + return AUDCtrlGetCfgMixer ( demod, + (pDRXCfgAudMixer_t)config->cfgData); + case DRX_CFG_AUD_AVSYNC: + return AUDCtrlGetCfgAVSync ( demod, + (pDRXCfgAudAVSync_t)config->cfgData); +#endif + + default: + return (DRX_STS_INVALID_ARG); + } + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================= +===== EXPORTED FUNCTIONS ====================================================*/ +/** +* \fn DRXJ_Open() +* \brief Open the demod instance, configure device, configure drxdriver +* \return Status_t Return status. +* +* DRXJ_Open() can be called with a NULL ucode image => no ucode upload. +* This means that DRXJ_Open() must NOT contain SCU commands or, in general, +* rely on SCU or AUD ucode to be present. +* +*/ +DRXStatus_t +DRXJ_Open(pDRXDemodInstance_t demod) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + pDRXCommonAttr_t commonAttr = NULL; + u32_t driverVersion = 0; + DRXUCodeInfo_t ucodeInfo; + DRXCfgMPEGOutput_t cfgMPEGOutput; + + /* Check arguments */ + if (demod -> myExtAttr == NULL ) + { + return ( DRX_STS_INVALID_ARG); + } + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t) demod -> myExtAttr; + commonAttr = (pDRXCommonAttr_t) demod -> myCommonAttr; + + CHK_ERROR(PowerUpDevice(demod)); + commonAttr->currentPowerMode = DRX_POWER_UP; + + /* has to be in front of setIqmAf and setOrxNsuAox */ + CHK_ERROR(GetDeviceCapabilities(demod)); + + /* Soft reset of sys- and osc-clockdomain */ + WR16( devAddr, SIO_CC_SOFT_RST__A, ( SIO_CC_SOFT_RST_SYS__M | + SIO_CC_SOFT_RST_OSC__M ) ); + WR16( devAddr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); + CHK_ERROR( DRXBSP_HST_Sleep(1) ); + + /* TODO first make sure that everything keeps working before enabling this */ + /* PowerDownAnalogBlocks() */ + WR16( devAddr, ATV_TOP_STDBY__A, (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE) + |ATV_TOP_STDBY_SIF_STDBY_STANDBY ); + + CHK_ERROR( SetIqmAf( demod, FALSE ) ); + CHK_ERROR( SetOrxNsuAox( demod, FALSE ) ); + + CHK_ERROR(InitHI(demod) ); + + /* disable mpegoutput pins */ + cfgMPEGOutput.enableMPEGOutput = FALSE; + CHK_ERROR( CtrlSetCfgMPEGOutput( demod, &cfgMPEGOutput) ); + /* Stop AUD Inform SetAudio it will need to do all setting */ + CHK_ERROR( PowerDownAud(demod) ); + /* Stop SCU */ + WR16( devAddr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP); + + /* Upload microcode */ + if ( commonAttr->microcode != NULL ) + { + /* Dirty trick to use common ucode upload & verify, + pretend device is already open */ + commonAttr->isOpened = TRUE; + ucodeInfo.mcData = commonAttr->microcode; + ucodeInfo.mcSize = commonAttr->microcodeSize; + +#ifdef DRXJ_SPLIT_UCODE_UPLOAD + /* Upload microcode without audio part */ + CHK_ERROR( CtrlUCodeUpload( demod, &ucodeInfo, UCODE_UPLOAD, FALSE ) ); +#else + CHK_ERROR( DRX_Ctrl( demod, DRX_CTRL_LOAD_UCODE, &ucodeInfo) ); +#endif /* DRXJ_SPLIT_UCODE_UPLOAD */ + if ( commonAttr->verifyMicrocode == TRUE ) + { +#ifdef DRXJ_SPLIT_UCODE_UPLOAD + CHK_ERROR( CtrlUCodeUpload( demod, &ucodeInfo, UCODE_VERIFY, FALSE ) ); +#else + CHK_ERROR( DRX_Ctrl ( demod, DRX_CTRL_VERIFY_UCODE, &ucodeInfo) ); +#endif /* DRXJ_SPLIT_UCODE_UPLOAD */ + } + commonAttr->isOpened = FALSE; + } + + /* Run SCU for a little while to initialize microcode version numbers */ + WR16( devAddr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); + + /* Open tuner instance */ + if ( demod->myTuner != NULL ) + { + demod->myTuner->myCommonAttr->myUserData = (void *)demod; + + if ( commonAttr->tunerPortNr == 1 ) + { + Bool_t bridgeClosed = TRUE; + CHK_ERROR( CtrlI2CBridge( demod, &bridgeClosed ) ); + } + + CHK_ERROR( DRXBSP_TUNER_Open( demod -> myTuner ) ); + + if ( commonAttr->tunerPortNr == 1 ) + { + Bool_t bridgeClosed = FALSE; + CHK_ERROR( CtrlI2CBridge( demod, &bridgeClosed ) ); + } + commonAttr->tunerMinFreqRF = ((demod->myTuner)->myCommonAttr->minFreqRF); + commonAttr->tunerMaxFreqRF = ((demod->myTuner)->myCommonAttr->maxFreqRF); + } + + /* Initialize scan timeout */ + commonAttr -> scanDemodLockTimeout = DRXJ_SCAN_TIMEOUT; + commonAttr -> scanDesiredLock = DRX_LOCKED; + + /* Initialize default AFE configuartion for QAM */ + if (extAttr->hasLNA) + { + /* IF AGC off, PGA active */ +#ifndef DRXJ_VSB_ONLY + extAttr->qamIfAgcCfg.standard = DRX_STANDARD_ITU_B; + extAttr->qamIfAgcCfg.ctrlMode = DRX_AGC_CTRL_OFF; + extAttr->qamPgaCfg = 140+(11*13); +#endif + extAttr->vsbIfAgcCfg.standard = DRX_STANDARD_8VSB; + extAttr->vsbIfAgcCfg.ctrlMode = DRX_AGC_CTRL_OFF; + extAttr->vsbPgaCfg = 140+(11*13); + } else { + /* IF AGC on, PGA not active */ +#ifndef DRXJ_VSB_ONLY + extAttr->qamIfAgcCfg.standard = DRX_STANDARD_ITU_B; + extAttr->qamIfAgcCfg.ctrlMode = DRX_AGC_CTRL_AUTO; + extAttr->qamIfAgcCfg.minOutputLevel = 0; + extAttr->qamIfAgcCfg.maxOutputLevel = 0x7FFF; + extAttr->qamIfAgcCfg.speed = 3; + extAttr->qamIfAgcCfg.top = 1297; + extAttr->qamPgaCfg = 140; +#endif + extAttr->vsbIfAgcCfg.standard = DRX_STANDARD_8VSB; + extAttr->vsbIfAgcCfg.ctrlMode = DRX_AGC_CTRL_AUTO; + extAttr->vsbIfAgcCfg.minOutputLevel = 0; + extAttr->vsbIfAgcCfg.maxOutputLevel = 0x7FFF; + extAttr->vsbIfAgcCfg.speed = 3; + extAttr->vsbIfAgcCfg.top = 1024; + extAttr->vsbPgaCfg = 140; + } + /* TODO: remove minOutputLevel and maxOutputLevel for both QAM and VSB after */ + /* mc has not used them */ +#ifndef DRXJ_VSB_ONLY + extAttr->qamRfAgcCfg.standard = DRX_STANDARD_ITU_B; + extAttr->qamRfAgcCfg.ctrlMode = DRX_AGC_CTRL_AUTO; + extAttr->qamRfAgcCfg.minOutputLevel = 0; + extAttr->qamRfAgcCfg.maxOutputLevel = 0x7FFF; + extAttr->qamRfAgcCfg.speed = 3; + extAttr->qamRfAgcCfg.top = 9500; + extAttr->qamRfAgcCfg.cutOffCurrent = 4000; + extAttr->qamPreSawCfg.standard = DRX_STANDARD_ITU_B; + extAttr->qamPreSawCfg.reference = 0x07; + extAttr->qamPreSawCfg.usePreSaw = TRUE; +#endif + /* Initialize default AFE configuartion for VSB */ + extAttr->vsbRfAgcCfg.standard = DRX_STANDARD_8VSB; + extAttr->vsbRfAgcCfg.ctrlMode = DRX_AGC_CTRL_AUTO; + extAttr->vsbRfAgcCfg.minOutputLevel = 0; + extAttr->vsbRfAgcCfg.maxOutputLevel = 0x7FFF; + extAttr->vsbRfAgcCfg.speed = 3; + extAttr->vsbRfAgcCfg.top = 9500; + extAttr->vsbRfAgcCfg.cutOffCurrent = 4000; + extAttr->vsbPreSawCfg.standard = DRX_STANDARD_8VSB; + extAttr->vsbPreSawCfg.reference = 0x07; + extAttr->vsbPreSawCfg.usePreSaw = TRUE; + +#ifndef DRXJ_DIGITAL_ONLY + /* Initialize default AFE configuartion for ATV */ + extAttr->atvRfAgcCfg.standard = DRX_STANDARD_NTSC; + extAttr->atvRfAgcCfg.ctrlMode = DRX_AGC_CTRL_AUTO; + extAttr->atvRfAgcCfg.top = 9500; + extAttr->atvRfAgcCfg.cutOffCurrent = 4000; + extAttr->atvRfAgcCfg.speed = 3; + extAttr->atvIfAgcCfg.standard = DRX_STANDARD_NTSC; + extAttr->atvIfAgcCfg.ctrlMode = DRX_AGC_CTRL_AUTO; + extAttr->atvIfAgcCfg.speed = 3; + extAttr->atvIfAgcCfg.top = 2400; + extAttr->atvPreSawCfg.reference = 0x0007; + extAttr->atvPreSawCfg.usePreSaw = TRUE; + extAttr->atvPreSawCfg.standard = DRX_STANDARD_NTSC; +#endif + extAttr->standard=DRX_STANDARD_UNKNOWN; + + CHK_ERROR(SmartAntInit(demod)); + + /* Stamp driver version number in SCU data RAM in BCD code + Done to enable field application engineers to retreive drxdriver version + via I2C from SCU RAM + */ + driverVersion = (VERSION_MAJOR/100) % 10; + driverVersion <<= 4; + driverVersion += (VERSION_MAJOR/10) % 10; + driverVersion <<= 4; + driverVersion += (VERSION_MAJOR%10); + driverVersion <<= 4; + driverVersion += (VERSION_MINOR%10); + driverVersion <<= 4; + driverVersion += (VERSION_PATCH/1000) % 10; + driverVersion <<= 4; + driverVersion += (VERSION_PATCH/100) % 10; + driverVersion <<= 4; + driverVersion += (VERSION_PATCH/10) % 10; + driverVersion <<= 4; + driverVersion += (VERSION_PATCH%10); + WR16(devAddr, SCU_RAM_DRIVER_VER_HI__A, (u16_t)(driverVersion>>16) ); + WR16(devAddr, SCU_RAM_DRIVER_VER_LO__A, (u16_t)(driverVersion&0xFFFF) ); + + /* refresh the audio data structure with default */ + extAttr->audData = DRXJDefaultAudData_g; + + return ( DRX_STS_OK ); +rw_error: + commonAttr->isOpened = FALSE; + return (DRX_STS_ERROR); +} + +/*============================================================================*/ +/** +* \fn DRXJ_Close() +* \brief Close the demod instance, power down the device +* \return Status_t Return status. +* +*/ +DRXStatus_t +DRXJ_Close(pDRXDemodInstance_t demod) +{ + pI2CDeviceAddr_t devAddr =NULL; + pDRXJData_t extAttr =NULL; + pDRXCommonAttr_t commonAttr =NULL; + DRXPowerMode_t powerMode =DRX_POWER_UP; + + commonAttr = (pDRXCommonAttr_t) demod -> myCommonAttr; + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t) demod -> myExtAttr; + + /* power up */ + CHK_ERROR( CtrlPowerMode( demod, &powerMode )); + + if ( demod->myTuner != NULL ) + { + /* Check if bridge is used */ + if ( commonAttr->tunerPortNr == 1 ) + { + Bool_t bridgeClosed = TRUE; + CHK_ERROR( CtrlI2CBridge( demod, &bridgeClosed ) ); + } + CHK_ERROR( DRXBSP_TUNER_Close( demod -> myTuner ) ); + if ( commonAttr->tunerPortNr == 1 ) + { + Bool_t bridgeClosed = FALSE; + CHK_ERROR( CtrlI2CBridge( demod, &bridgeClosed ) ); + } + }; + + WR16( devAddr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); + powerMode =DRX_POWER_DOWN; + CHK_ERROR( CtrlPowerMode( demod, &powerMode )); + + return DRX_STS_OK; +rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================*/ +/** +* \fn DRXJ_Ctrl() +* \brief DRXJ specific control function +* \return Status_t Return status. +*/ +DRXStatus_t +DRXJ_Ctrl(pDRXDemodInstance_t demod, DRXCtrlIndex_t ctrl, + void *ctrlData) +{ + switch ( ctrl ) { + /*======================================================================*/ + case DRX_CTRL_SET_CHANNEL: + { + return CtrlSetChannel ( demod, + (pDRXChannel_t) ctrlData ); + } + break; + /*======================================================================*/ + case DRX_CTRL_GET_CHANNEL: + { + return CtrlGetChannel ( demod, + (pDRXChannel_t) ctrlData ); + } + break; + /*======================================================================*/ + case DRX_CTRL_SIG_QUALITY: + { + return CtrlSigQuality ( demod, + (pDRXSigQuality_t) ctrlData); + } + break; + /*======================================================================*/ + case DRX_CTRL_SIG_STRENGTH: + { + return CtrlSigStrength ( demod, + (pu16_t) ctrlData); + } + break; + /*======================================================================*/ + case DRX_CTRL_CONSTEL: + { + return CtrlConstel ( demod, + (pDRXComplex_t) ctrlData); + } + break; + /*======================================================================*/ + case DRX_CTRL_SET_CFG: + { + return CtrlSetCfg ( demod, + (pDRXCfg_t) ctrlData); + } + break; + /*======================================================================*/ + case DRX_CTRL_GET_CFG: + { + return CtrlGetCfg ( demod, (pDRXCfg_t) ctrlData); + } + break; + /*======================================================================*/ + case DRX_CTRL_I2C_BRIDGE: + { + return CtrlI2CBridge( demod, (pBool_t) ctrlData ); + } + break; + /*======================================================================*/ + case DRX_CTRL_LOCK_STATUS: + { + return CtrlLockStatus( demod, (pDRXLockStatus_t) ctrlData ); + } + break; + /*======================================================================*/ + case DRX_CTRL_SET_STANDARD: + { + return CtrlSetStandard( demod, (pDRXStandard_t) ctrlData ); + } + break; + /*======================================================================*/ + case DRX_CTRL_GET_STANDARD: + { + return CtrlGetStandard( demod, (pDRXStandard_t) ctrlData ); + } + break; + /*======================================================================*/ + case DRX_CTRL_POWER_MODE: + { + return CtrlPowerMode( demod, (pDRXPowerMode_t) ctrlData ); + } + break; + /*======================================================================*/ + case DRX_CTRL_VERSION: + { + return CtrlVersion( demod, (pDRXVersionList_t *) ctrlData ); + } + break; + /*======================================================================*/ + case DRX_CTRL_PROBE_DEVICE: + { + return CtrlProbeDevice( demod ); + } + break; + /*======================================================================*/ + case DRX_CTRL_SET_OOB: + { + return CtrlSetOOB( demod, (pDRXOOB_t) ctrlData ); + } + break; + /*======================================================================*/ + case DRX_CTRL_GET_OOB: + { + return CtrlGetOOB( demod, (pDRXOOBStatus_t) ctrlData ); + } + break; + /*======================================================================*/ + case DRX_CTRL_SET_UIO_CFG: + { + return CtrlSetUIOCfg( demod, (pDRXUIOCfg_t) ctrlData ); + } + break; + /*======================================================================*/ + case DRX_CTRL_GET_UIO_CFG: + { + return CtrlGetUIOCfg( demod, (pDRXUIOCfg_t) ctrlData ); + } + break; + /*======================================================================*/ + case DRX_CTRL_UIO_READ: + { + return CtrlUIORead( demod, (pDRXUIOData_t) ctrlData ); + } + break; + /*======================================================================*/ + case DRX_CTRL_UIO_WRITE: + { + return CtrlUIOWrite( demod, (pDRXUIOData_t) ctrlData ); + } + break; + /*======================================================================*/ + case DRX_CTRL_AUD_SET_STANDARD: + { + return AUDCtrlSetStandard( demod, (pDRXAudStandard_t) ctrlData ); + } + break; + /*======================================================================*/ + case DRX_CTRL_AUD_GET_STANDARD: + { + return AUDCtrlGetStandard( demod, (pDRXAudStandard_t) ctrlData ); + } + break; + /*======================================================================*/ + case DRX_CTRL_AUD_GET_STATUS: + { + return AUDCtrlGetStatus( demod, (pDRXAudStatus_t) ctrlData ); + } + break; + /*======================================================================*/ + case DRX_CTRL_AUD_BEEP: + { + return AUDCtrlBeep( demod, (pDRXAudBeep_t) ctrlData ); + } + break; + + /*======================================================================*/ + case DRX_CTRL_I2C_READWRITE: + { + return CtrlI2CWriteRead( demod, (pDRXI2CData_t) ctrlData ); + } + break; +#ifdef DRXJ_SPLIT_UCODE_UPLOAD + case DRX_CTRL_LOAD_UCODE: + { + return CtrlUCodeUpload( demod, (pDRXUCodeInfo_t) ctrlData, UCODE_UPLOAD, FALSE ); + } + break; + case DRX_CTRL_VERIFY_UCODE: + { + return CtrlUCodeUpload( demod, (pDRXUCodeInfo_t) ctrlData, UCODE_VERIFY, FALSE ); + } + break; +#endif /* DRXJ_SPLIT_UCODE_UPLOAD */ + case DRX_CTRL_VALIDATE_UCODE: + { + return CtrlValidateUCode (demod); + } + break; + default: + return (DRX_STS_FUNC_NOT_AVAILABLE); + } + return (DRX_STS_OK); +} +/* END OF FILE */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.h b/drivers/media/dvb-frontends/drx39xyj/drxj.h new file mode 100644 index 0000000..ee7aa6a --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.h @@ -0,0 +1,732 @@ +/** +* \file $Id: drxj.h,v 1.132 2009/12/22 12:13:48 danielg Exp $ +* +* \brief DRXJ specific header file +* +* \author Dragan Savic, Milos Nikolic, Mihajlo Katona, Tao Ding, Paul Janssen +*/ + +/* +* $(c) 2006-2009 Trident Microsystems, Inc. - All rights reserved. +* +* This software and related documentation (the 'Software') are intellectual +* property owned by Trident and are copyright of Trident, unless specifically +* noted otherwise. +* +* Any use of the Software is permitted only pursuant to the terms of the +* license agreement, if any, which accompanies, is included with or applicable +* to the Software ('License Agreement') or upon express written consent of +* Trident. Any copying, reproduction or redistribution of the Software in +* whole or in part by any means not in accordance with the License Agreement +* or as agreed in writing by Trident is expressly prohibited. +* +* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE +* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE +* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND +* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES +* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT +* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL +* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY +* TO USE THE SOFTWARE. +* +* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, +* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, +* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS +* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE +* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM +* TRIDENT'S NEGLIGENCE. $ +* +*/ +#ifndef __DRXJ_H__ +#define __DRXJ_H__ +/*------------------------------------------------------------------------- +INCLUDES +-------------------------------------------------------------------------*/ + +#include "drx_driver.h" +#include "drx_dap_fasi.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Check DRX-J specific dap condition */ +/* Multi master mode and short addr format only will not work. + RMW, CRC reset, broadcast and switching back to single master mode + cannot be done with short addr only in multi master mode. */ +#if ((DRXDAP_SINGLE_MASTER==0)&&(DRXDAPFASI_LONG_ADDR_ALLOWED==0)) +#error "Multi master mode and short addressing only is an illegal combination" +*; /* Generate a fatal compiler error to make sure it stops here, + this is necesarry because not all compilers stop after a #error. */ +#endif + +/*------------------------------------------------------------------------- +TYPEDEFS +-------------------------------------------------------------------------*/ +/*============================================================================*/ +/*============================================================================*/ +/*== code support ============================================================*/ +/*============================================================================*/ +/*============================================================================*/ + +/*============================================================================*/ +/*============================================================================*/ +/*== SCU cmd if =============================================================*/ +/*============================================================================*/ +/*============================================================================*/ + +typedef struct { + u16_t command; /**< Command number */ + u16_t parameterLen; /**< Data length in byte */ + u16_t resultLen; /**< result length in byte */ + u16_t *parameter; /**< General purpous param */ + u16_t *result; /**< General purpous param */ +} DRXJSCUCmd_t, *pDRXJSCUCmd_t; + + +/*============================================================================*/ +/*============================================================================*/ +/*== CTRL CFG related data structures ========================================*/ +/*============================================================================*/ +/*============================================================================*/ + +/* extra intermediate lock state for VSB,QAM,NTSC */ +#define DRXJ_DEMOD_LOCK (DRX_LOCK_STATE_1) + +/* OOB lock states */ +#define DRXJ_OOB_AGC_LOCK (DRX_LOCK_STATE_1) /* analog gain control lock */ +#define DRXJ_OOB_SYNC_LOCK (DRX_LOCK_STATE_2) /* digital gain control lock */ + +/* Intermediate powermodes for DRXJ */ +#define DRXJ_POWER_DOWN_MAIN_PATH DRX_POWER_MODE_8 +#define DRXJ_POWER_DOWN_CORE DRX_POWER_MODE_9 +#define DRXJ_POWER_DOWN_PLL DRX_POWER_MODE_10 + +/* supstition for GPIO FNC mux */ +#define APP_O (0x0000) + +/*#define DRX_CTRL_BASE (0x0000)*/ + +#define DRXJ_CTRL_CFG_BASE (0x1000) +typedef enum { + DRXJ_CFG_AGC_RF = DRXJ_CTRL_CFG_BASE, + DRXJ_CFG_AGC_IF, + DRXJ_CFG_AGC_INTERNAL, + DRXJ_CFG_PRE_SAW, + DRXJ_CFG_AFE_GAIN, + DRXJ_CFG_SYMBOL_CLK_OFFSET, + DRXJ_CFG_ACCUM_CR_RS_CW_ERR, + DRXJ_CFG_FEC_MERS_SEQ_COUNT, + DRXJ_CFG_OOB_MISC, + DRXJ_CFG_SMART_ANT, + DRXJ_CFG_OOB_PRE_SAW, + DRXJ_CFG_VSB_MISC, + DRXJ_CFG_RESET_PACKET_ERR, + + /* ATV (FM) */ + DRXJ_CFG_ATV_OUTPUT, /* also for FM (SIF control) but not likely */ + DRXJ_CFG_ATV_MISC, + DRXJ_CFG_ATV_EQU_COEF, + DRXJ_CFG_ATV_AGC_STATUS, /* also for FM ( IF,RF, audioAGC ) */ + + DRXJ_CFG_MPEG_OUTPUT_MISC, + DRXJ_CFG_HW_CFG, + DRXJ_CFG_OOB_LO_POW, + + DRXJ_CFG_MAX /* dummy, never to be used */ + +} DRXJCfgType_t, *pDRXJCfgType_t; + +/** +* /struct DRXJCfgSmartAntIO_t +* smart antenna i/o. +*/ +typedef enum DRXJCfgSmartAntIO_t { + DRXJ_SMT_ANT_OUTPUT = 0, + DRXJ_SMT_ANT_INPUT +} DRXJCfgSmartAntIO_t, *pDRXJCfgSmartAntIO_t; + +/** +* /struct DRXJCfgSmartAnt_t +* Set smart antenna. +*/ +typedef struct { + DRXJCfgSmartAntIO_t io; + u16_t ctrlData; +} DRXJCfgSmartAnt_t, *pDRXJCfgSmartAnt_t; + +/** +* /struct DRXJAGCSTATUS_t +* AGC status information from the DRXJ-IQM-AF. +*/ +typedef struct { + u16_t IFAGC; + u16_t RFAGC; + u16_t DigitalAGC; +}DRXJAgcStatus_t, *pDRXJAgcStatus_t; + +/* DRXJ_CFG_AGC_RF, DRXJ_CFG_AGC_IF */ + +/** +* /struct DRXJAgcCtrlMode_t +* Available AGCs modes in the DRXJ. +*/ +typedef enum { + DRX_AGC_CTRL_AUTO = 0, + DRX_AGC_CTRL_USER, + DRX_AGC_CTRL_OFF +} DRXJAgcCtrlMode_t, *pDRXJAgcCtrlMode_t; + +/** +* /struct DRXJCfgAgc_t +* Generic interface for all AGCs present on the DRXJ. +*/ +typedef struct { + DRXStandard_t standard; /* standard for which these settings apply */ + DRXJAgcCtrlMode_t ctrlMode; /* off, user, auto */ + u16_t outputLevel; /* range dependent on AGC */ + u16_t minOutputLevel; /* range dependent on AGC */ + u16_t maxOutputLevel; /* range dependent on AGC */ + u16_t speed; /* range dependent on AGC */ + u16_t top; /* rf-agc take over point */ + u16_t cutOffCurrent; /* rf-agc is accelerated if output current + is below cut-off current */ +}DRXJCfgAgc_t, *pDRXJCfgAgc_t; + +/* DRXJ_CFG_PRE_SAW */ + +/** +* /struct DRXJCfgPreSaw_t +* Interface to configure pre SAW sense. +*/ +typedef struct { + DRXStandard_t standard; /* standard to which these settings apply */ + u16_t reference; /* pre SAW reference value, range 0 .. 31 */ + Bool_t usePreSaw; /* TRUE algorithms must use pre SAW sense */ +} DRXJCfgPreSaw_t, *pDRXJCfgPreSaw_t; + +/* DRXJ_CFG_AFE_GAIN */ + +/** +* /struct DRXJCfgAfeGain_t +* Interface to configure gain of AFE (LNA + PGA). +*/ +typedef struct { + DRXStandard_t standard; /* standard to which these settings apply */ + u16_t gain; /* gain in 0.1 dB steps, DRXJ range 140 .. 335 */ +} DRXJCfgAfeGain_t, *pDRXJCfgAfeGain_t; + +/** +* /struct DRXJRSErrors_t +* Available failure information in DRXJ_FEC_RS. +* +* Container for errors that are received in the most recently finished measurment period +* +*/ +typedef struct { + u16_t nrBitErrors; /**< no of pre RS bit errors */ + u16_t nrSymbolErrors; /**< no of pre RS symbol errors */ + u16_t nrPacketErrors; /**< no of pre RS packet errors */ + u16_t nrFailures; /**< no of post RS failures to decode */ + u16_t nrSncParFailCount; /**< no of post RS bit erros */ +} DRXJRSErrors_t, *pDRXJRSErrors_t; + +/** +* /struct DRXJCfgVSBMisc_t +* symbol error rate +*/ +typedef struct{ + u32_t symbError; /**< symbol error rate sps */ +}DRXJCfgVSBMisc_t, *pDRXJCfgVSBMisc_t; + +/** +* /enum DRXJMpegOutputClockRate_t +* Mpeg output clock rate. +* +*/ +typedef enum { + DRXJ_MPEG_START_WIDTH_1CLKCYC, + DRXJ_MPEG_START_WIDTH_8CLKCYC +} DRXJMpegStartWidth_t, *pDRXJMpegStartWidth_t; + +/** +* /enum DRXJMpegOutputClockRate_t +* Mpeg output clock rate. +* +*/ +typedef enum { + DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO, + DRXJ_MPEGOUTPUT_CLOCK_RATE_75973K, + DRXJ_MPEGOUTPUT_CLOCK_RATE_50625K, + DRXJ_MPEGOUTPUT_CLOCK_RATE_37968K, + DRXJ_MPEGOUTPUT_CLOCK_RATE_30375K, + DRXJ_MPEGOUTPUT_CLOCK_RATE_25313K, + DRXJ_MPEGOUTPUT_CLOCK_RATE_21696K +} DRXJMpegOutputClockRate_t, *pDRXJMpegOutputClockRate_t; + +/** +* /struct DRXJCfgMisc_t +* Change TEI bit of MPEG output +* reverse MPEG output bit order +* set MPEG output clock rate +*/ +typedef struct{ + Bool_t disableTEIHandling; /**< if TRUE pass (not change) TEI bit */ + Bool_t bitReverseMpegOutout; /**< if TRUE, parallel: msb on MD0; serial: lsb out first */ + DRXJMpegOutputClockRate_t mpegOutputClockRate; /**< set MPEG output clock rate that overwirtes the derived one from symbol rate */ + DRXJMpegStartWidth_t mpegStartWidth; /**< set MPEG output start width */ +}DRXJCfgMpegOutputMisc_t, *pDRXJCfgMpegOutputMisc_t; + +/** +* /enum DRXJXtalFreq_t +* Supported external crystal reference frequency. +*/ +typedef enum{ + DRXJ_XTAL_FREQ_RSVD, + DRXJ_XTAL_FREQ_27MHZ, + DRXJ_XTAL_FREQ_20P25MHZ, + DRXJ_XTAL_FREQ_4MHZ +}DRXJXtalFreq_t, *pDRXJXtalFreq_t; + +/** +* /enum DRXJXtalFreq_t +* Supported external crystal reference frequency. +*/ +typedef enum{ + DRXJ_I2C_SPEED_400KBPS, + DRXJ_I2C_SPEED_100KBPS +}DRXJI2CSpeed_t, *pDRXJI2CSpeed_t; + +/** +* /struct DRXJCfgHwCfg_t +* Get hw configuration, such as crystal reference frequency, I2C speed, etc... +*/ +typedef struct{ + DRXJXtalFreq_t xtalFreq; /**< crystal reference frequency */ + DRXJI2CSpeed_t i2cSpeed; /**< 100 or 400 kbps */ +}DRXJCfgHwCfg_t, *pDRXJCfgHwCfg_t; + +/* + * DRXJ_CFG_ATV_MISC + */ +typedef struct{ + s16_t peakFilter; /* -8 .. 15 */ + u16_t noiseFilter; /* 0 .. 15 */ +}DRXJCfgAtvMisc_t, *pDRXJCfgAtvMisc_t; + +/* + * DRXJCfgOOBMisc_t + */ +#define DRXJ_OOB_STATE_RESET 0x0 +#define DRXJ_OOB_STATE_AGN_HUNT 0x1 +#define DRXJ_OOB_STATE_DGN_HUNT 0x2 +#define DRXJ_OOB_STATE_AGC_HUNT 0x3 +#define DRXJ_OOB_STATE_FRQ_HUNT 0x4 +#define DRXJ_OOB_STATE_PHA_HUNT 0x8 +#define DRXJ_OOB_STATE_TIM_HUNT 0x10 +#define DRXJ_OOB_STATE_EQU_HUNT 0x20 +#define DRXJ_OOB_STATE_EQT_HUNT 0x30 +#define DRXJ_OOB_STATE_SYNC 0x40 + +typedef struct{ + DRXJAgcStatus_t agc; + Bool_t eqLock; + Bool_t symTimingLock; + Bool_t phaseLock; + Bool_t freqLock; + Bool_t digGainLock; + Bool_t anaGainLock; + u8_t state; +}DRXJCfgOOBMisc_t, *pDRXJCfgOOBMisc_t; + +/* + * Index of in array of coef + */ +typedef enum { + DRXJ_OOB_LO_POW_MINUS0DB = 0, + DRXJ_OOB_LO_POW_MINUS5DB, + DRXJ_OOB_LO_POW_MINUS10DB, + DRXJ_OOB_LO_POW_MINUS15DB, + DRXJ_OOB_LO_POW_MAX +} DRXJCfgOobLoPower_t, *pDRXJCfgOobLoPower_t; + +/* + * DRXJ_CFG_ATV_EQU_COEF + */ +typedef struct { + s16_t coef0; /* -256 .. 255 */ + s16_t coef1; /* -256 .. 255 */ + s16_t coef2; /* -256 .. 255 */ + s16_t coef3; /* -256 .. 255 */ +} DRXJCfgAtvEquCoef_t, *pDRXJCfgAtvEquCoef_t; + +/* + * Index of in array of coef + */ +typedef enum { + DRXJ_COEF_IDX_MN = 0, + DRXJ_COEF_IDX_FM , + DRXJ_COEF_IDX_L , + DRXJ_COEF_IDX_LP , + DRXJ_COEF_IDX_BG , + DRXJ_COEF_IDX_DK , + DRXJ_COEF_IDX_I , + DRXJ_COEF_IDX_MAX +} DRXJCoefArrayIndex_t, *pDRXJCoefArrayIndex_t; + +/* + * DRXJ_CFG_ATV_OUTPUT + */ + +/** +* /enum DRXJAttenuation_t +* Attenuation setting for SIF AGC. +* +*/ +typedef enum { + DRXJ_SIF_ATTENUATION_0DB, + DRXJ_SIF_ATTENUATION_3DB, + DRXJ_SIF_ATTENUATION_6DB, + DRXJ_SIF_ATTENUATION_9DB +} DRXJSIFAttenuation_t, *pDRXJSIFAttenuation_t; + +/** +* /struct DRXJCfgAtvOutput_t +* SIF attenuation setting. +* +*/ +typedef struct { + Bool_t enableCVBSOutput; /* TRUE= enabled */ + Bool_t enableSIFOutput; /* TRUE= enabled */ + DRXJSIFAttenuation_t sifAttenuation; +} DRXJCfgAtvOutput_t, *pDRXJCfgAtvOutput_t; + +/* + DRXJ_CFG_ATV_AGC_STATUS (get only) +*/ +/* TODO : AFE interface not yet finished, subject to change */ +typedef struct { + u16_t rfAgcGain ; /* 0 .. 877 uA */ + u16_t ifAgcGain ; /* 0 .. 877 uA */ + s16_t videoAgcGain ; /* -75 .. 1972 in 0.1 dB steps */ + s16_t audioAgcGain ; /* -4 .. 1020 in 0.1 dB steps */ + u16_t rfAgcLoopGain ; /* 0 .. 7 */ + u16_t ifAgcLoopGain ; /* 0 .. 7 */ + u16_t videoAgcLoopGain; /* 0 .. 7 */ +} DRXJCfgAtvAgcStatus_t, *pDRXJCfgAtvAgcStatus_t; + +/*============================================================================*/ +/*============================================================================*/ +/*== CTRL related data structures ============================================*/ +/*============================================================================*/ +/*============================================================================*/ + +/* NONE */ + +/*============================================================================*/ +/*============================================================================*/ + +/*========================================*/ +/** +* /struct DRXJData_t +* DRXJ specific attributes. +* +* Global data container for DRXJ specific data. +* +*/ +typedef struct { + /* device capabilties (determined during DRX_Open()) */ + Bool_t hasLNA; /**< TRUE if LNA (aka PGA) present */ + Bool_t hasOOB; /**< TRUE if OOB supported */ + Bool_t hasNTSC; /**< TRUE if NTSC supported */ + Bool_t hasBTSC; /**< TRUE if BTSC supported */ + Bool_t hasSMATX; /**< TRUE if mat_tx is available */ + Bool_t hasSMARX; /**< TRUE if mat_rx is available */ + Bool_t hasGPIO; /**< TRUE if GPIO is available */ + Bool_t hasIRQN; /**< TRUE if IRQN is available */ + /* A1/A2/A... */ + u8_t mfx; /**< metal fix */ + + /* tuner settings */ + Bool_t mirrorFreqSpectOOB; /**< tuner inversion (TRUE = tuner mirrors the signal */ + + /* standard/channel settings */ + DRXStandard_t standard; /**< current standard information */ + DRXConstellation_t constellation; /**< current constellation */ + DRXFrequency_t frequency; /**< center signal frequency in KHz */ + DRXBandwidth_t currBandwidth; /**< current channel bandwidth */ + DRXMirror_t mirror; /**< current channel mirror */ + + /* signal quality information */ + u32_t fecBitsDesired; /**< BER accounting period */ + u16_t fecVdPlen; /**< no of trellis symbols: VD SER measurement period */ + u16_t qamVdPrescale; /**< Viterbi Measurement Prescale */ + u16_t qamVdPeriod; /**< Viterbi Measurement period */ + u16_t fecRsPlen; /**< defines RS BER measurement period */ + u16_t fecRsPrescale; /**< ReedSolomon Measurement Prescale */ + u16_t fecRsPeriod; /**< ReedSolomon Measurement period */ + Bool_t resetPktErrAcc; /**< Set a flag to reset accumulated packet error */ + u16_t pktErrAccStart; /**< Set a flag to reset accumulated packet error */ + + /* HI configuration */ + u16_t HICfgTimingDiv; /**< HI Configure() parameter 2 */ + u16_t HICfgBridgeDelay; /**< HI Configure() parameter 3 */ + u16_t HICfgWakeUpKey; /**< HI Configure() parameter 4 */ + u16_t HICfgCtrl; /**< HI Configure() parameter 5 */ + u16_t HICfgTransmit; /**< HI Configure() parameter 6 */ + + /* UIO configuartion */ + DRXUIOMode_t uioSmaRxMode; /**< current mode of SmaRx pin */ + DRXUIOMode_t uioSmaTxMode; /**< current mode of SmaTx pin */ + DRXUIOMode_t uioGPIOMode; /**< current mode of ASEL pin */ + DRXUIOMode_t uioIRQNMode; /**< current mode of IRQN pin */ + + /* IQM fs frequecy shift and inversion */ + u32_t iqmFsRateOfs; /**< frequency shifter setting after setchannel */ + Bool_t posImage; /**< Ture: positive image */ + /* IQM RC frequecy shift */ + u32_t iqmRcRateOfs; /**< frequency shifter setting after setchannel */ + + /* ATV configuartion */ + u32_t atvCfgChangedFlags; /**< flag: flags cfg changes */ + s16_t atvTopEqu0[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU0__A */ + s16_t atvTopEqu1[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU1__A */ + s16_t atvTopEqu2[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU2__A */ + s16_t atvTopEqu3[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU3__A */ + Bool_t phaseCorrectionBypass; /**< flag: TRUE=bypass */ + s16_t atvTopVidPeak; /**< shadow of ATV_TOP_VID_PEAK__A */ + u16_t atvTopNoiseTh; /**< shadow of ATV_TOP_NOISE_TH__A */ + Bool_t enableCVBSOutput; /**< flag CVBS ouput enable */ + Bool_t enableSIFOutput; /**< flag SIF ouput enable */ + DRXJSIFAttenuation_t + sifAttenuation; /**< current SIF att setting */ + /* Agc configuration for QAM and VSB */ + DRXJCfgAgc_t qamRfAgcCfg; /**< qam RF AGC config */ + DRXJCfgAgc_t qamIfAgcCfg; /**< qam IF AGC config */ + DRXJCfgAgc_t vsbRfAgcCfg; /**< vsb RF AGC config */ + DRXJCfgAgc_t vsbIfAgcCfg; /**< vsb IF AGC config */ + + /* PGA gain configuration for QAM and VSB */ + u16_t qamPgaCfg; /**< qam PGA config */ + u16_t vsbPgaCfg; /**< vsb PGA config */ + + /* Pre SAW configuration for QAM and VSB */ + DRXJCfgPreSaw_t qamPreSawCfg; /**< qam pre SAW config */ + DRXJCfgPreSaw_t vsbPreSawCfg; /**< qam pre SAW config */ + + /* Version information */ + char vText[2][12]; /**< allocated text versions */ + DRXVersion_t vVersion[2]; /**< allocated versions structs */ + DRXVersionList_t vListElements[2]; /**< allocated version list */ + + /* smart antenna configuration */ + Bool_t smartAntInverted; + + /* Tracking filter setting for OOB */ + u16_t oobTrkFilterCfg[8]; + Bool_t oobPowerOn; + + /* MPEG static bitrate setting */ + u32_t mpegTsStaticBitrate; /**< bitrate static MPEG output */ + Bool_t disableTEIhandling; /**< MPEG TS TEI handling */ + Bool_t bitReverseMpegOutout; /**< MPEG output bit order */ + DRXJMpegOutputClockRate_t + mpegOutputClockRate; /**< MPEG output clock rate */ + DRXJMpegStartWidth_t + mpegStartWidth; /**< MPEG Start width */ + + /* Pre SAW & Agc configuration for ATV */ + DRXJCfgPreSaw_t atvPreSawCfg; /**< atv pre SAW config */ + DRXJCfgAgc_t atvRfAgcCfg; /**< atv RF AGC config */ + DRXJCfgAgc_t atvIfAgcCfg; /**< atv IF AGC config */ + u16_t atvPgaCfg; /**< atv pga config */ + + u32_t currSymbolRate; + + /* pin-safe mode */ + Bool_t pdrSafeMode; /**< PDR safe mode activated */ + u16_t pdrSafeRestoreValGpio; + u16_t pdrSafeRestoreValVSync; + u16_t pdrSafeRestoreValSmaRx; + u16_t pdrSafeRestoreValSmaTx; + + /* OOB pre-saw value */ + u16_t oobPreSaw; + DRXJCfgOobLoPower_t oobLoPow; + + DRXAudData_t audData; /**< audio storage */ + +} DRXJData_t, *pDRXJData_t; + +/*------------------------------------------------------------------------- +Access MACROS +-------------------------------------------------------------------------*/ +/** +* \brief Compilable references to attributes +* \param d pointer to demod instance +* +* Used as main reference to an attribute field. +* Can be used by both macro implementation and function implementation. +* These macros are defined to avoid duplication of code in macro and function +* definitions that handle access of demod common or extended attributes. +* +*/ + +#define DRXJ_ATTR_BTSC_DETECT( d ) \ + (((pDRXJData_t)(d)->myExtAttr)->audData.btscDetect) + +/** +* \brief Actual access macros +* \param d pointer to demod instance +* \param x value to set or to get +* +* SET macros must be used to set the value of an attribute. +* GET macros must be used to retrieve the value of an attribute. +* Depending on the value of DRX_USE_ACCESS_FUNCTIONS the macro's will be +* substituted by "direct-access-inline-code" or a function call. +* +*/ +#define DRXJ_GET_BTSC_DETECT( d, x ) \ + do { \ + (x) = DRXJ_ATTR_BTSC_DETECT(( d ); \ + } while(0) + +#define DRXJ_SET_BTSC_DETECT( d, x ) \ + do { \ + DRXJ_ATTR_BTSC_DETECT( d ) = (x); \ + } while(0) + + +/*------------------------------------------------------------------------- +DEFINES +-------------------------------------------------------------------------*/ + +/** +* \def DRXJ_NTSC_CARRIER_FREQ_OFFSET +* \brief Offset from picture carrier to centre frequency in kHz, in RF domain +* +* For NTSC standard. +* NTSC channels are listed by their picture carrier frequency (Fpc). +* The function DRX_CTRL_SET_CHANNEL requires the centre frequency as input. +* In case the tuner module is not used the DRX-J requires that the tuner is +* tuned to the centre frequency of the channel: +* +* Fcentre = Fpc + DRXJ_NTSC_CARRIER_FREQ_OFFSET +* +*/ +#define DRXJ_NTSC_CARRIER_FREQ_OFFSET ((DRXFrequency_t)(1750)) + +/** +* \def DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET +* \brief Offset from picture carrier to centre frequency in kHz, in RF domain +* +* For PAL/SECAM - BG standard. This define is needed in case the tuner module +* is NOT used. PAL/SECAM channels are listed by their picture carrier frequency (Fpc). +* The DRX-J requires that the tuner is tuned to: +* Fpc + DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET +* +* In case the tuner module is used the drxdriver takes care of this. +* In case the tuner module is NOT used the application programmer must take +* care of this. +* +*/ +#define DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET ((DRXFrequency_t)(2375)) + +/** +* \def DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET +* \brief Offset from picture carrier to centre frequency in kHz, in RF domain +* +* For PAL/SECAM - DK, I, L standards. This define is needed in case the tuner module +* is NOT used. PAL/SECAM channels are listed by their picture carrier frequency (Fpc). +* The DRX-J requires that the tuner is tuned to: +* Fpc + DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET +* +* In case the tuner module is used the drxdriver takes care of this. +* In case the tuner module is NOT used the application programmer must take +* care of this. +* +*/ +#define DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET ((DRXFrequency_t)(2775)) + +/** +* \def DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET +* \brief Offset from picture carrier to centre frequency in kHz, in RF domain +* +* For PAL/SECAM - LP standard. This define is needed in case the tuner module +* is NOT used. PAL/SECAM channels are listed by their picture carrier frequency (Fpc). +* The DRX-J requires that the tuner is tuned to: +* Fpc + DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET +* +* In case the tuner module is used the drxdriver takes care of this. +* In case the tuner module is NOT used the application programmer must take +* care of this. +*/ +#define DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET ((DRXFrequency_t)(-3255)) + +/** +* \def DRXJ_FM_CARRIER_FREQ_OFFSET +* \brief Offset from sound carrier to centre frequency in kHz, in RF domain +* +* For FM standard. +* FM channels are listed by their sound carrier frequency (Fsc). +* The function DRX_CTRL_SET_CHANNEL requires the Ffm frequency (see below) as +* input. +* In case the tuner module is not used the DRX-J requires that the tuner is +* tuned to the Ffm frequency of the channel. +* +* Ffm = Fsc + DRXJ_FM_CARRIER_FREQ_OFFSET +* +*/ +#define DRXJ_FM_CARRIER_FREQ_OFFSET ((DRXFrequency_t)(-3000)) + +/* Revision types -------------------------------------------------------*/ + +#define DRXJ_TYPE_ID (0x3946000DUL) + +/* Macros ---------------------------------------------------------------*/ + +/* Convert OOB lock status to string */ +#define DRXJ_STR_OOB_LOCKSTATUS(x) ( \ + ( x == DRX_NEVER_LOCK ) ? "Never" : \ + ( x == DRX_NOT_LOCKED ) ? "No" : \ + ( x == DRX_LOCKED ) ? "Locked" : \ + ( x == DRX_LOCK_STATE_1 ) ? "AGC lock" : \ + ( x == DRX_LOCK_STATE_2 ) ? "sync lock" : \ + "(Invalid)" ) + +/*------------------------------------------------------------------------- +ENUM +-------------------------------------------------------------------------*/ + +/*------------------------------------------------------------------------- +STRUCTS +-------------------------------------------------------------------------*/ + +/*------------------------------------------------------------------------- +Exported FUNCTIONS +-------------------------------------------------------------------------*/ + +extern DRXStatus_t DRXJ_Open(pDRXDemodInstance_t demod); +extern DRXStatus_t DRXJ_Close(pDRXDemodInstance_t demod); +extern DRXStatus_t DRXJ_Ctrl(pDRXDemodInstance_t demod, + DRXCtrlIndex_t ctrl, + void *ctrlData); + +/*------------------------------------------------------------------------- +Exported GLOBAL VARIABLES +-------------------------------------------------------------------------*/ +extern DRXAccessFunc_t drxDapDRXJFunct_g; +extern DRXDemodFunc_t DRXJFunctions_g; +extern DRXJData_t DRXJData_g; +extern I2CDeviceAddr_t DRXJDefaultAddr_g; +extern DRXCommonAttr_t DRXJDefaultCommAttr_g; +extern DRXDemodInstance_t DRXJDefaultDemod_g; + +/*------------------------------------------------------------------------- +THE END +-------------------------------------------------------------------------*/ +#ifdef __cplusplus +} +#endif +#endif /* __DRXJ_H__ */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj_map.h b/drivers/media/dvb-frontends/drx39xyj/drxj_map.h new file mode 100644 index 0000000..941aa14 --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/drxj_map.h @@ -0,0 +1,15350 @@ +/* + *********************************************************************************************************************** + * WARNING - THIS FILE HAS BEEN GENERATED - DO NOT CHANGE + * + * Filename: drxj_map.h + * Generated on: Mon Jan 18 12:09:24 2010 + * Generated by: IDF:x 1.3.0 + * Generated from: reg_map + * Output start: [entry point] + * + * filename last modified re-use + * ----------------------------------------------------- + * reg_map.1.tmp Mon Jan 18 12:09:24 2010 - + * + * $(c) 2010 Trident Microsystems, Inc. - All rights reserved. + * + * This software and related documentation (the 'Software') are intellectual property owned by Trident and are + * copyright of Trident, unless specifically noted otherwise. + * + * Any use of the Software is permitted only pursuant to the terms of the license agreement, if any, which accompanies, + * is included with or applicable to the Software ('License Agreement') or upon express written consent of Trident. Any + * copying, reproduction or redistribution of the Software in whole or in part by any means not in accordance with the + * License Agreement or as agreed in writing by Trident is expressly prohibited. + * + * THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE LICENSE AGREEMENT. EXCEPT AS WARRANTED IN + * THE LICENSE AGREEMENT THE SOFTWARE IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS + * WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE, QUIT ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL PROPERTY OR OTHER + * RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY TO USE THE SOFTWARE. + * + * IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, PUNITIVE, SPECIAL OR OTHER DAMAGES + * WHATSOEVER INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF + * BUSINESS INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE INABILITY TO USE THE SOFTWARE, + * EVEN IF TRIDENT HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM + * TRIDENT'S NEGLIGENCE. $ + * + *********************************************************************************************************************** + */ + +#ifndef __DRXJ_MAP__H__ +#define __DRXJ_MAP__H__ INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef _REGISTERTABLE_ +#include +extern RegisterTable_t drxj_map[]; +extern RegisterTableInfo_t drxj_map_info[]; +#endif + + + + + + +#define ATV_COMM_EXEC__A 0xC00000 +#define ATV_COMM_EXEC__W 2 +#define ATV_COMM_EXEC__M 0x3 +#define ATV_COMM_EXEC__PRE 0x0 +#define ATV_COMM_EXEC_STOP 0x0 +#define ATV_COMM_EXEC_ACTIVE 0x1 +#define ATV_COMM_EXEC_HOLD 0x2 + +#define ATV_COMM_STATE__A 0xC00001 +#define ATV_COMM_STATE__W 16 +#define ATV_COMM_STATE__M 0xFFFF +#define ATV_COMM_STATE__PRE 0x0 +#define ATV_COMM_MB__A 0xC00002 +#define ATV_COMM_MB__W 16 +#define ATV_COMM_MB__M 0xFFFF +#define ATV_COMM_MB__PRE 0x0 +#define ATV_COMM_INT_REQ__A 0xC00003 +#define ATV_COMM_INT_REQ__W 16 +#define ATV_COMM_INT_REQ__M 0xFFFF +#define ATV_COMM_INT_REQ__PRE 0x0 +#define ATV_COMM_INT_REQ_COMM_INT_REQ__B 0 +#define ATV_COMM_INT_REQ_COMM_INT_REQ__W 1 +#define ATV_COMM_INT_REQ_COMM_INT_REQ__M 0x1 +#define ATV_COMM_INT_REQ_COMM_INT_REQ__PRE 0x0 + +#define ATV_COMM_INT_STA__A 0xC00005 +#define ATV_COMM_INT_STA__W 16 +#define ATV_COMM_INT_STA__M 0xFFFF +#define ATV_COMM_INT_STA__PRE 0x0 +#define ATV_COMM_INT_MSK__A 0xC00006 +#define ATV_COMM_INT_MSK__W 16 +#define ATV_COMM_INT_MSK__M 0xFFFF +#define ATV_COMM_INT_MSK__PRE 0x0 +#define ATV_COMM_INT_STM__A 0xC00007 +#define ATV_COMM_INT_STM__W 16 +#define ATV_COMM_INT_STM__M 0xFFFF +#define ATV_COMM_INT_STM__PRE 0x0 + +#define ATV_COMM_KEY__A 0xC0000F +#define ATV_COMM_KEY__W 16 +#define ATV_COMM_KEY__M 0xFFFF +#define ATV_COMM_KEY__PRE 0x0 +#define ATV_COMM_KEY_KEY 0xFABA +#define ATV_COMM_KEY_MIN 0x0 +#define ATV_COMM_KEY_MAX 0xFFFF + + + +#define ATV_TOP_COMM_EXEC__A 0xC10000 +#define ATV_TOP_COMM_EXEC__W 2 +#define ATV_TOP_COMM_EXEC__M 0x3 +#define ATV_TOP_COMM_EXEC__PRE 0x0 +#define ATV_TOP_COMM_EXEC_STOP 0x0 +#define ATV_TOP_COMM_EXEC_ACTIVE 0x1 +#define ATV_TOP_COMM_EXEC_HOLD 0x2 + +#define ATV_TOP_COMM_STATE__A 0xC10001 +#define ATV_TOP_COMM_STATE__W 16 +#define ATV_TOP_COMM_STATE__M 0xFFFF +#define ATV_TOP_COMM_STATE__PRE 0x0 +#define ATV_TOP_COMM_STATE_STATE__B 0 +#define ATV_TOP_COMM_STATE_STATE__W 16 +#define ATV_TOP_COMM_STATE_STATE__M 0xFFFF +#define ATV_TOP_COMM_STATE_STATE__PRE 0x0 + +#define ATV_TOP_COMM_MB__A 0xC10002 +#define ATV_TOP_COMM_MB__W 16 +#define ATV_TOP_COMM_MB__M 0xFFFF +#define ATV_TOP_COMM_MB__PRE 0x0 +#define ATV_TOP_COMM_MB_CTL__B 0 +#define ATV_TOP_COMM_MB_CTL__W 1 +#define ATV_TOP_COMM_MB_CTL__M 0x1 +#define ATV_TOP_COMM_MB_CTL__PRE 0x0 +#define ATV_TOP_COMM_MB_OBS__B 1 +#define ATV_TOP_COMM_MB_OBS__W 1 +#define ATV_TOP_COMM_MB_OBS__M 0x2 +#define ATV_TOP_COMM_MB_OBS__PRE 0x0 + +#define ATV_TOP_COMM_MB_MUX_CTRL__B 2 +#define ATV_TOP_COMM_MB_MUX_CTRL__W 4 +#define ATV_TOP_COMM_MB_MUX_CTRL__M 0x3C +#define ATV_TOP_COMM_MB_MUX_CTRL__PRE 0x0 +#define ATV_TOP_COMM_MB_MUX_CTRL_PEAK_S 0x0 +#define ATV_TOP_COMM_MB_MUX_CTRL_VID_GAIN 0x4 +#define ATV_TOP_COMM_MB_MUX_CTRL_CORR_O 0x8 +#define ATV_TOP_COMM_MB_MUX_CTRL_CR_ROT_O 0xC +#define ATV_TOP_COMM_MB_MUX_CTRL_CR_IIR_IQ 0x10 +#define ATV_TOP_COMM_MB_MUX_CTRL_VIDEO_O 0x14 +#define ATV_TOP_COMM_MB_MUX_CTRL_SIF_O 0x18 +#define ATV_TOP_COMM_MB_MUX_CTRL_SIF2025_O 0x1C +#define ATV_TOP_COMM_MB_MUX_CTRL_POST_S 0x20 + +#define ATV_TOP_COMM_MB_MUX_OBS__B 6 +#define ATV_TOP_COMM_MB_MUX_OBS__W 4 +#define ATV_TOP_COMM_MB_MUX_OBS__M 0x3C0 +#define ATV_TOP_COMM_MB_MUX_OBS__PRE 0x0 +#define ATV_TOP_COMM_MB_MUX_OBS_PEAK_S 0x0 +#define ATV_TOP_COMM_MB_MUX_OBS_VID_GAIN 0x40 +#define ATV_TOP_COMM_MB_MUX_OBS_CORR_O 0x80 +#define ATV_TOP_COMM_MB_MUX_OBS_CR_ROT_O 0xC0 +#define ATV_TOP_COMM_MB_MUX_OBS_CR_IIR_IQ 0x100 +#define ATV_TOP_COMM_MB_MUX_OBS_VIDEO_O 0x140 +#define ATV_TOP_COMM_MB_MUX_OBS_SIF_O 0x180 +#define ATV_TOP_COMM_MB_MUX_OBS_SIF2025_O 0x1C0 +#define ATV_TOP_COMM_MB_MUX_OBS_POST_S 0x200 + + +#define ATV_TOP_COMM_INT_REQ__A 0xC10003 +#define ATV_TOP_COMM_INT_REQ__W 16 +#define ATV_TOP_COMM_INT_REQ__M 0xFFFF +#define ATV_TOP_COMM_INT_REQ__PRE 0x0 +#define ATV_TOP_COMM_INT_STA__A 0xC10005 +#define ATV_TOP_COMM_INT_STA__W 16 +#define ATV_TOP_COMM_INT_STA__M 0xFFFF +#define ATV_TOP_COMM_INT_STA__PRE 0x0 + +#define ATV_TOP_COMM_INT_STA_FAGC_STA__B 0 +#define ATV_TOP_COMM_INT_STA_FAGC_STA__W 1 +#define ATV_TOP_COMM_INT_STA_FAGC_STA__M 0x1 +#define ATV_TOP_COMM_INT_STA_FAGC_STA__PRE 0x0 + +#define ATV_TOP_COMM_INT_STA_OVM_STA__B 1 +#define ATV_TOP_COMM_INT_STA_OVM_STA__W 1 +#define ATV_TOP_COMM_INT_STA_OVM_STA__M 0x2 +#define ATV_TOP_COMM_INT_STA_OVM_STA__PRE 0x0 + +#define ATV_TOP_COMM_INT_STA_AMPTH_STA__B 2 +#define ATV_TOP_COMM_INT_STA_AMPTH_STA__W 1 +#define ATV_TOP_COMM_INT_STA_AMPTH_STA__M 0x4 +#define ATV_TOP_COMM_INT_STA_AMPTH_STA__PRE 0x0 + +#define ATV_TOP_COMM_INT_MSK__A 0xC10006 +#define ATV_TOP_COMM_INT_MSK__W 16 +#define ATV_TOP_COMM_INT_MSK__M 0xFFFF +#define ATV_TOP_COMM_INT_MSK__PRE 0x0 + +#define ATV_TOP_COMM_INT_MSK_FAGC_MSK__B 0 +#define ATV_TOP_COMM_INT_MSK_FAGC_MSK__W 1 +#define ATV_TOP_COMM_INT_MSK_FAGC_MSK__M 0x1 +#define ATV_TOP_COMM_INT_MSK_FAGC_MSK__PRE 0x0 + +#define ATV_TOP_COMM_INT_MSK_OVM_MSK__B 1 +#define ATV_TOP_COMM_INT_MSK_OVM_MSK__W 1 +#define ATV_TOP_COMM_INT_MSK_OVM_MSK__M 0x2 +#define ATV_TOP_COMM_INT_MSK_OVM_MSK__PRE 0x0 + +#define ATV_TOP_COMM_INT_MSK_AMPTH_MSK__B 2 +#define ATV_TOP_COMM_INT_MSK_AMPTH_MSK__W 1 +#define ATV_TOP_COMM_INT_MSK_AMPTH_MSK__M 0x4 +#define ATV_TOP_COMM_INT_MSK_AMPTH_MSK__PRE 0x0 + +#define ATV_TOP_COMM_INT_STM__A 0xC10007 +#define ATV_TOP_COMM_INT_STM__W 16 +#define ATV_TOP_COMM_INT_STM__M 0xFFFF +#define ATV_TOP_COMM_INT_STM__PRE 0x0 + +#define ATV_TOP_COMM_INT_STM_FAGC_STM__B 0 +#define ATV_TOP_COMM_INT_STM_FAGC_STM__W 1 +#define ATV_TOP_COMM_INT_STM_FAGC_STM__M 0x1 +#define ATV_TOP_COMM_INT_STM_FAGC_STM__PRE 0x0 + +#define ATV_TOP_COMM_INT_STM_OVM_STM__B 1 +#define ATV_TOP_COMM_INT_STM_OVM_STM__W 1 +#define ATV_TOP_COMM_INT_STM_OVM_STM__M 0x2 +#define ATV_TOP_COMM_INT_STM_OVM_STM__PRE 0x0 + +#define ATV_TOP_COMM_INT_STM_AMPTH_STM__B 2 +#define ATV_TOP_COMM_INT_STM_AMPTH_STM__W 1 +#define ATV_TOP_COMM_INT_STM_AMPTH_STM__M 0x4 +#define ATV_TOP_COMM_INT_STM_AMPTH_STM__PRE 0x0 + +#define ATV_TOP_COMM_KEY__A 0xC1000F +#define ATV_TOP_COMM_KEY__W 16 +#define ATV_TOP_COMM_KEY__M 0xFFFF +#define ATV_TOP_COMM_KEY__PRE 0x0 + +#define ATV_TOP_COMM_KEY_KEY__B 0 +#define ATV_TOP_COMM_KEY_KEY__W 16 +#define ATV_TOP_COMM_KEY_KEY__M 0xFFFF +#define ATV_TOP_COMM_KEY_KEY__PRE 0x0 +#define ATV_TOP_COMM_KEY_KEY_KEY 0xFABA +#define ATV_TOP_COMM_KEY_KEY_MIN 0x0 +#define ATV_TOP_COMM_KEY_KEY_MAX 0xFFFF + + +#define ATV_TOP_CR_AMP_TH__A 0xC10010 +#define ATV_TOP_CR_AMP_TH__W 8 +#define ATV_TOP_CR_AMP_TH__M 0xFF +#define ATV_TOP_CR_AMP_TH__PRE 0x8 +#define ATV_TOP_CR_AMP_TH_MN 0x8 + +#define ATV_TOP_CR_CONT__A 0xC10011 +#define ATV_TOP_CR_CONT__W 9 +#define ATV_TOP_CR_CONT__M 0x1FF +#define ATV_TOP_CR_CONT__PRE 0x9C + +#define ATV_TOP_CR_CONT_CR_P__B 0 +#define ATV_TOP_CR_CONT_CR_P__W 3 +#define ATV_TOP_CR_CONT_CR_P__M 0x7 +#define ATV_TOP_CR_CONT_CR_P__PRE 0x4 +#define ATV_TOP_CR_CONT_CR_P_MN 0x4 +#define ATV_TOP_CR_CONT_CR_P_FM 0x0 + +#define ATV_TOP_CR_CONT_CR_D__B 3 +#define ATV_TOP_CR_CONT_CR_D__W 3 +#define ATV_TOP_CR_CONT_CR_D__M 0x38 +#define ATV_TOP_CR_CONT_CR_D__PRE 0x18 +#define ATV_TOP_CR_CONT_CR_D_MN 0x18 +#define ATV_TOP_CR_CONT_CR_D_FM 0x0 + +#define ATV_TOP_CR_CONT_CR_I__B 6 +#define ATV_TOP_CR_CONT_CR_I__W 3 +#define ATV_TOP_CR_CONT_CR_I__M 0x1C0 +#define ATV_TOP_CR_CONT_CR_I__PRE 0x80 +#define ATV_TOP_CR_CONT_CR_I_MN 0x80 +#define ATV_TOP_CR_CONT_CR_I_FM 0x0 + + +#define ATV_TOP_CR_OVM_TH__A 0xC10012 +#define ATV_TOP_CR_OVM_TH__W 8 +#define ATV_TOP_CR_OVM_TH__M 0xFF +#define ATV_TOP_CR_OVM_TH__PRE 0xA0 +#define ATV_TOP_CR_OVM_TH_MN 0xA0 +#define ATV_TOP_CR_OVM_TH_FM 0x0 + + +#define ATV_TOP_NOISE_TH__A 0xC10013 +#define ATV_TOP_NOISE_TH__W 4 +#define ATV_TOP_NOISE_TH__M 0xF +#define ATV_TOP_NOISE_TH__PRE 0x8 +#define ATV_TOP_NOISE_TH_MN 0x8 + +#define ATV_TOP_EQU0__A 0xC10014 +#define ATV_TOP_EQU0__W 9 +#define ATV_TOP_EQU0__M 0x1FF +#define ATV_TOP_EQU0__PRE 0x1FB + +#define ATV_TOP_EQU0_EQU_C0__B 0 +#define ATV_TOP_EQU0_EQU_C0__W 9 +#define ATV_TOP_EQU0_EQU_C0__M 0x1FF +#define ATV_TOP_EQU0_EQU_C0__PRE 0x1FB +#define ATV_TOP_EQU0_EQU_C0_MN 0xFB + +#define ATV_TOP_EQU1__A 0xC10015 +#define ATV_TOP_EQU1__W 9 +#define ATV_TOP_EQU1__M 0x1FF +#define ATV_TOP_EQU1__PRE 0x1CE + +#define ATV_TOP_EQU1_EQU_C1__B 0 +#define ATV_TOP_EQU1_EQU_C1__W 9 +#define ATV_TOP_EQU1_EQU_C1__M 0x1FF +#define ATV_TOP_EQU1_EQU_C1__PRE 0x1CE +#define ATV_TOP_EQU1_EQU_C1_MN 0xCE + +#define ATV_TOP_EQU2__A 0xC10016 +#define ATV_TOP_EQU2__W 9 +#define ATV_TOP_EQU2__M 0x1FF +#define ATV_TOP_EQU2__PRE 0xD2 + +#define ATV_TOP_EQU2_EQU_C2__B 0 +#define ATV_TOP_EQU2_EQU_C2__W 9 +#define ATV_TOP_EQU2_EQU_C2__M 0x1FF +#define ATV_TOP_EQU2_EQU_C2__PRE 0xD2 +#define ATV_TOP_EQU2_EQU_C2_MN 0xD2 + +#define ATV_TOP_EQU3__A 0xC10017 +#define ATV_TOP_EQU3__W 9 +#define ATV_TOP_EQU3__M 0x1FF +#define ATV_TOP_EQU3__PRE 0x160 + +#define ATV_TOP_EQU3_EQU_C3__B 0 +#define ATV_TOP_EQU3_EQU_C3__W 9 +#define ATV_TOP_EQU3_EQU_C3__M 0x1FF +#define ATV_TOP_EQU3_EQU_C3__PRE 0x160 +#define ATV_TOP_EQU3_EQU_C3_MN 0x60 + + +#define ATV_TOP_ROT_MODE__A 0xC10018 +#define ATV_TOP_ROT_MODE__W 1 +#define ATV_TOP_ROT_MODE__M 0x1 +#define ATV_TOP_ROT_MODE__PRE 0x0 +#define ATV_TOP_ROT_MODE_AMPTH_DEPEND 0x0 +#define ATV_TOP_ROT_MODE_ALWAYS 0x1 + +#define ATV_TOP_MOD_CONTROL__A 0xC10019 +#define ATV_TOP_MOD_CONTROL__W 12 +#define ATV_TOP_MOD_CONTROL__M 0xFFF +#define ATV_TOP_MOD_CONTROL__PRE 0x5B1 + +#define ATV_TOP_MOD_CONTROL_MOD_IR__B 0 +#define ATV_TOP_MOD_CONTROL_MOD_IR__W 3 +#define ATV_TOP_MOD_CONTROL_MOD_IR__M 0x7 +#define ATV_TOP_MOD_CONTROL_MOD_IR__PRE 0x1 +#define ATV_TOP_MOD_CONTROL_MOD_IR_MN 0x1 +#define ATV_TOP_MOD_CONTROL_MOD_IR_FM 0x0 + +#define ATV_TOP_MOD_CONTROL_MOD_IF__B 3 +#define ATV_TOP_MOD_CONTROL_MOD_IF__W 4 +#define ATV_TOP_MOD_CONTROL_MOD_IF__M 0x78 +#define ATV_TOP_MOD_CONTROL_MOD_IF__PRE 0x30 +#define ATV_TOP_MOD_CONTROL_MOD_IF_MN 0x30 +#define ATV_TOP_MOD_CONTROL_MOD_IF_FM 0x0 + +#define ATV_TOP_MOD_CONTROL_MOD_MODE__B 7 +#define ATV_TOP_MOD_CONTROL_MOD_MODE__W 1 +#define ATV_TOP_MOD_CONTROL_MOD_MODE__M 0x80 +#define ATV_TOP_MOD_CONTROL_MOD_MODE__PRE 0x80 +#define ATV_TOP_MOD_CONTROL_MOD_MODE_RISE 0x0 +#define ATV_TOP_MOD_CONTROL_MOD_MODE_RISE_FALL 0x80 + +#define ATV_TOP_MOD_CONTROL_MOD_TH__B 8 +#define ATV_TOP_MOD_CONTROL_MOD_TH__W 4 +#define ATV_TOP_MOD_CONTROL_MOD_TH__M 0xF00 +#define ATV_TOP_MOD_CONTROL_MOD_TH__PRE 0x500 +#define ATV_TOP_MOD_CONTROL_MOD_TH_MN 0x500 +#define ATV_TOP_MOD_CONTROL_MOD_TH_FM 0x0 + +#define ATV_TOP_STD__A 0xC1001A +#define ATV_TOP_STD__W 2 +#define ATV_TOP_STD__M 0x3 +#define ATV_TOP_STD__PRE 0x0 + +#define ATV_TOP_STD_MODE__B 0 +#define ATV_TOP_STD_MODE__W 1 +#define ATV_TOP_STD_MODE__M 0x1 +#define ATV_TOP_STD_MODE__PRE 0x0 +#define ATV_TOP_STD_MODE_MN 0x0 +#define ATV_TOP_STD_MODE_FM 0x1 + +#define ATV_TOP_STD_VID_POL__B 1 +#define ATV_TOP_STD_VID_POL__W 1 +#define ATV_TOP_STD_VID_POL__M 0x2 +#define ATV_TOP_STD_VID_POL__PRE 0x0 +#define ATV_TOP_STD_VID_POL_NEG 0x0 +#define ATV_TOP_STD_VID_POL_POS 0x2 + + +#define ATV_TOP_VID_AMP__A 0xC1001B +#define ATV_TOP_VID_AMP__W 12 +#define ATV_TOP_VID_AMP__M 0xFFF +#define ATV_TOP_VID_AMP__PRE 0x380 +#define ATV_TOP_VID_AMP_MN 0x380 +#define ATV_TOP_VID_AMP_FM 0x0 + + +#define ATV_TOP_VID_PEAK__A 0xC1001C +#define ATV_TOP_VID_PEAK__W 5 +#define ATV_TOP_VID_PEAK__M 0x1F +#define ATV_TOP_VID_PEAK__PRE 0x1 + +#define ATV_TOP_FAGC_TH__A 0xC1001D +#define ATV_TOP_FAGC_TH__W 11 +#define ATV_TOP_FAGC_TH__M 0x7FF +#define ATV_TOP_FAGC_TH__PRE 0x2B2 +#define ATV_TOP_FAGC_TH_MN 0x2B2 + + +#define ATV_TOP_SYNC_SLICE__A 0xC1001E +#define ATV_TOP_SYNC_SLICE__W 11 +#define ATV_TOP_SYNC_SLICE__M 0x7FF +#define ATV_TOP_SYNC_SLICE__PRE 0x243 +#define ATV_TOP_SYNC_SLICE_MN 0x243 + + +#define ATV_TOP_SIF_GAIN__A 0xC1001F +#define ATV_TOP_SIF_GAIN__W 11 +#define ATV_TOP_SIF_GAIN__M 0x7FF +#define ATV_TOP_SIF_GAIN__PRE 0x0 + +#define ATV_TOP_SIF_TP__A 0xC10020 +#define ATV_TOP_SIF_TP__W 6 +#define ATV_TOP_SIF_TP__M 0x3F +#define ATV_TOP_SIF_TP__PRE 0x0 + +#define ATV_TOP_MOD_ACCU__A 0xC10021 +#define ATV_TOP_MOD_ACCU__W 10 +#define ATV_TOP_MOD_ACCU__M 0x3FF +#define ATV_TOP_MOD_ACCU__PRE 0x0 + +#define ATV_TOP_CR_FREQ__A 0xC10022 +#define ATV_TOP_CR_FREQ__W 8 +#define ATV_TOP_CR_FREQ__M 0xFF +#define ATV_TOP_CR_FREQ__PRE 0x0 + +#define ATV_TOP_CR_PHAD__A 0xC10023 +#define ATV_TOP_CR_PHAD__W 12 +#define ATV_TOP_CR_PHAD__M 0xFFF +#define ATV_TOP_CR_PHAD__PRE 0x0 + +#define ATV_TOP_AF_SIF_ATT__A 0xC10024 +#define ATV_TOP_AF_SIF_ATT__W 2 +#define ATV_TOP_AF_SIF_ATT__M 0x3 +#define ATV_TOP_AF_SIF_ATT__PRE 0x0 +#define ATV_TOP_AF_SIF_ATT_0DB 0x0 +#define ATV_TOP_AF_SIF_ATT_M3DB 0x1 +#define ATV_TOP_AF_SIF_ATT_M6DB 0x2 +#define ATV_TOP_AF_SIF_ATT_M9DB 0x3 + +#define ATV_TOP_STDBY__A 0xC10025 +#define ATV_TOP_STDBY__W 2 +#define ATV_TOP_STDBY__M 0x3 +#define ATV_TOP_STDBY__PRE 0x1 + +#define ATV_TOP_STDBY_SIF_STDBY__B 0 +#define ATV_TOP_STDBY_SIF_STDBY__W 1 +#define ATV_TOP_STDBY_SIF_STDBY__M 0x1 +#define ATV_TOP_STDBY_SIF_STDBY__PRE 0x1 +#define ATV_TOP_STDBY_SIF_STDBY_ACTIVE 0x0 +#define ATV_TOP_STDBY_SIF_STDBY_STANDBY 0x1 + +#define ATV_TOP_STDBY_CVBS_STDBY__B 1 +#define ATV_TOP_STDBY_CVBS_STDBY__W 1 +#define ATV_TOP_STDBY_CVBS_STDBY__M 0x2 +#define ATV_TOP_STDBY_CVBS_STDBY__PRE 0x0 +#define ATV_TOP_STDBY_CVBS_STDBY_A1_ACTIVE 0x0 +#define ATV_TOP_STDBY_CVBS_STDBY_A1_STANDBY 0x2 +#define ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE 0x2 +#define ATV_TOP_STDBY_CVBS_STDBY_A2_STANDBY 0x0 + + +#define ATV_TOP_OVERRIDE_SFR__A 0xC10026 +#define ATV_TOP_OVERRIDE_SFR__W 1 +#define ATV_TOP_OVERRIDE_SFR__M 0x1 +#define ATV_TOP_OVERRIDE_SFR__PRE 0x0 +#define ATV_TOP_OVERRIDE_SFR_ACTIVE 0x0 +#define ATV_TOP_OVERRIDE_SFR_OVERRIDE 0x1 + + +#define ATV_TOP_SFR_VID_GAIN__A 0xC10027 +#define ATV_TOP_SFR_VID_GAIN__W 16 +#define ATV_TOP_SFR_VID_GAIN__M 0xFFFF +#define ATV_TOP_SFR_VID_GAIN__PRE 0x0 + +#define ATV_TOP_SFR_AGC_RES__A 0xC10028 +#define ATV_TOP_SFR_AGC_RES__W 5 +#define ATV_TOP_SFR_AGC_RES__M 0x1F +#define ATV_TOP_SFR_AGC_RES__PRE 0x0 + +#define ATV_TOP_OVM_COMP__A 0xC10029 +#define ATV_TOP_OVM_COMP__W 12 +#define ATV_TOP_OVM_COMP__M 0xFFF +#define ATV_TOP_OVM_COMP__PRE 0x0 +#define ATV_TOP_OUT_CONF__A 0xC1002A +#define ATV_TOP_OUT_CONF__W 5 +#define ATV_TOP_OUT_CONF__M 0x1F +#define ATV_TOP_OUT_CONF__PRE 0x0 + +#define ATV_TOP_OUT_CONF_CVBS_DAC_SIGN__B 0 +#define ATV_TOP_OUT_CONF_CVBS_DAC_SIGN__W 1 +#define ATV_TOP_OUT_CONF_CVBS_DAC_SIGN__M 0x1 +#define ATV_TOP_OUT_CONF_CVBS_DAC_SIGN__PRE 0x0 +#define ATV_TOP_OUT_CONF_CVBS_DAC_SIGN_UNSIGNED 0x0 +#define ATV_TOP_OUT_CONF_CVBS_DAC_SIGN_SIGNED 0x1 + +#define ATV_TOP_OUT_CONF_SIF_DAC_SIGN__B 1 +#define ATV_TOP_OUT_CONF_SIF_DAC_SIGN__W 1 +#define ATV_TOP_OUT_CONF_SIF_DAC_SIGN__M 0x2 +#define ATV_TOP_OUT_CONF_SIF_DAC_SIGN__PRE 0x0 +#define ATV_TOP_OUT_CONF_SIF_DAC_SIGN_UNSIGNED 0x0 +#define ATV_TOP_OUT_CONF_SIF_DAC_SIGN_SIGNED 0x2 + +#define ATV_TOP_OUT_CONF_SIF20_SIGN__B 2 +#define ATV_TOP_OUT_CONF_SIF20_SIGN__W 1 +#define ATV_TOP_OUT_CONF_SIF20_SIGN__M 0x4 +#define ATV_TOP_OUT_CONF_SIF20_SIGN__PRE 0x0 +#define ATV_TOP_OUT_CONF_SIF20_SIGN_UNSIGNED 0x0 +#define ATV_TOP_OUT_CONF_SIF20_SIGN_SIGNED 0x4 + +#define ATV_TOP_OUT_CONF_CVBS_DAC_BR__B 3 +#define ATV_TOP_OUT_CONF_CVBS_DAC_BR__W 1 +#define ATV_TOP_OUT_CONF_CVBS_DAC_BR__M 0x8 +#define ATV_TOP_OUT_CONF_CVBS_DAC_BR__PRE 0x0 +#define ATV_TOP_OUT_CONF_CVBS_DAC_BR_NORMAL 0x0 +#define ATV_TOP_OUT_CONF_CVBS_DAC_BR_BITREVERSED 0x8 + +#define ATV_TOP_OUT_CONF_SIF_DAC_BR__B 4 +#define ATV_TOP_OUT_CONF_SIF_DAC_BR__W 1 +#define ATV_TOP_OUT_CONF_SIF_DAC_BR__M 0x10 +#define ATV_TOP_OUT_CONF_SIF_DAC_BR__PRE 0x0 +#define ATV_TOP_OUT_CONF_SIF_DAC_BR_NORMAL 0x0 +#define ATV_TOP_OUT_CONF_SIF_DAC_BR_BITREVERSED 0x10 + + + +#define ATV_AFT_COMM_EXEC__A 0xFF0000 +#define ATV_AFT_COMM_EXEC__W 2 +#define ATV_AFT_COMM_EXEC__M 0x3 +#define ATV_AFT_COMM_EXEC__PRE 0x0 +#define ATV_AFT_COMM_EXEC_STOP 0x0 +#define ATV_AFT_COMM_EXEC_ACTIVE 0x1 +#define ATV_AFT_COMM_EXEC_HOLD 0x2 + + +#define ATV_AFT_TST__A 0xFF0010 +#define ATV_AFT_TST__W 4 +#define ATV_AFT_TST__M 0xF +#define ATV_AFT_TST__PRE 0x0 + + + + + +#define AUD_COMM_EXEC__A 0x1000000 +#define AUD_COMM_EXEC__W 2 +#define AUD_COMM_EXEC__M 0x3 +#define AUD_COMM_EXEC__PRE 0x0 +#define AUD_COMM_EXEC_STOP 0x0 +#define AUD_COMM_EXEC_ACTIVE 0x1 + +#define AUD_COMM_MB__A 0x1000002 +#define AUD_COMM_MB__W 16 +#define AUD_COMM_MB__M 0xFFFF +#define AUD_COMM_MB__PRE 0x0 + + + +#define AUD_TOP_COMM_EXEC__A 0x1010000 +#define AUD_TOP_COMM_EXEC__W 2 +#define AUD_TOP_COMM_EXEC__M 0x3 +#define AUD_TOP_COMM_EXEC__PRE 0x0 +#define AUD_TOP_COMM_EXEC_STOP 0x0 +#define AUD_TOP_COMM_EXEC_ACTIVE 0x1 + +#define AUD_TOP_COMM_MB__A 0x1010002 +#define AUD_TOP_COMM_MB__W 16 +#define AUD_TOP_COMM_MB__M 0xFFFF +#define AUD_TOP_COMM_MB__PRE 0x0 + +#define AUD_TOP_COMM_MB_CTL__B 0 +#define AUD_TOP_COMM_MB_CTL__W 1 +#define AUD_TOP_COMM_MB_CTL__M 0x1 +#define AUD_TOP_COMM_MB_CTL__PRE 0x0 +#define AUD_TOP_COMM_MB_CTL_CTR_OFF 0x0 +#define AUD_TOP_COMM_MB_CTL_CTR_ON 0x1 + +#define AUD_TOP_COMM_MB_OBS__B 1 +#define AUD_TOP_COMM_MB_OBS__W 1 +#define AUD_TOP_COMM_MB_OBS__M 0x2 +#define AUD_TOP_COMM_MB_OBS__PRE 0x0 +#define AUD_TOP_COMM_MB_OBS_OBS_OFF 0x0 +#define AUD_TOP_COMM_MB_OBS_OBS_ON 0x2 + +#define AUD_TOP_COMM_MB_MUX_CTRL__B 2 +#define AUD_TOP_COMM_MB_MUX_CTRL__W 4 +#define AUD_TOP_COMM_MB_MUX_CTRL__M 0x3C +#define AUD_TOP_COMM_MB_MUX_CTRL__PRE 0x0 +#define AUD_TOP_COMM_MB_MUX_CTRL_DEMOD_TBO 0x0 +#define AUD_TOP_COMM_MB_MUX_CTRL_XDFP_IRQS 0x4 +#define AUD_TOP_COMM_MB_MUX_CTRL_OBSERVEPC 0x8 +#define AUD_TOP_COMM_MB_MUX_CTRL_SAOUT 0xC +#define AUD_TOP_COMM_MB_MUX_CTRL_XDFP_SCHEQ 0x10 + +#define AUD_TOP_COMM_MB_MUX_OBS__B 6 +#define AUD_TOP_COMM_MB_MUX_OBS__W 4 +#define AUD_TOP_COMM_MB_MUX_OBS__M 0x3C0 +#define AUD_TOP_COMM_MB_MUX_OBS__PRE 0x0 +#define AUD_TOP_COMM_MB_MUX_OBS_DEMOD_TBO 0x0 +#define AUD_TOP_COMM_MB_MUX_OBS_XDFP_IRQS 0x40 +#define AUD_TOP_COMM_MB_MUX_OBS_OBSERVEPC 0x80 +#define AUD_TOP_COMM_MB_MUX_OBS_SAOUT 0xC0 +#define AUD_TOP_COMM_MB_MUX_OBS_XDFP_SCHEQ 0x100 + +#define AUD_TOP_TR_MDE__A 0x1010010 +#define AUD_TOP_TR_MDE__W 5 +#define AUD_TOP_TR_MDE__M 0x1F +#define AUD_TOP_TR_MDE__PRE 0x18 + +#define AUD_TOP_TR_MDE_FIFO_SIZE__B 0 +#define AUD_TOP_TR_MDE_FIFO_SIZE__W 4 +#define AUD_TOP_TR_MDE_FIFO_SIZE__M 0xF +#define AUD_TOP_TR_MDE_FIFO_SIZE__PRE 0x8 + +#define AUD_TOP_TR_MDE_RD_LOCK__B 4 +#define AUD_TOP_TR_MDE_RD_LOCK__W 1 +#define AUD_TOP_TR_MDE_RD_LOCK__M 0x10 +#define AUD_TOP_TR_MDE_RD_LOCK__PRE 0x10 +#define AUD_TOP_TR_MDE_RD_LOCK_NORMAL 0x0 +#define AUD_TOP_TR_MDE_RD_LOCK_LOCK 0x10 + +#define AUD_TOP_TR_CTR__A 0x1010011 +#define AUD_TOP_TR_CTR__W 4 +#define AUD_TOP_TR_CTR__M 0xF +#define AUD_TOP_TR_CTR__PRE 0x0 + +#define AUD_TOP_TR_CTR_FIFO_RD_RDY__B 0 +#define AUD_TOP_TR_CTR_FIFO_RD_RDY__W 1 +#define AUD_TOP_TR_CTR_FIFO_RD_RDY__M 0x1 +#define AUD_TOP_TR_CTR_FIFO_RD_RDY__PRE 0x0 +#define AUD_TOP_TR_CTR_FIFO_RD_RDY_NOT_READY 0x0 +#define AUD_TOP_TR_CTR_FIFO_RD_RDY_READY 0x1 + +#define AUD_TOP_TR_CTR_FIFO_EMPTY__B 1 +#define AUD_TOP_TR_CTR_FIFO_EMPTY__W 1 +#define AUD_TOP_TR_CTR_FIFO_EMPTY__M 0x2 +#define AUD_TOP_TR_CTR_FIFO_EMPTY__PRE 0x0 +#define AUD_TOP_TR_CTR_FIFO_EMPTY_NOT_EMPTY 0x0 +#define AUD_TOP_TR_CTR_FIFO_EMPTY_EMPTY 0x2 + +#define AUD_TOP_TR_CTR_FIFO_LOCK__B 2 +#define AUD_TOP_TR_CTR_FIFO_LOCK__W 1 +#define AUD_TOP_TR_CTR_FIFO_LOCK__M 0x4 +#define AUD_TOP_TR_CTR_FIFO_LOCK__PRE 0x0 +#define AUD_TOP_TR_CTR_FIFO_LOCK_UNLOCKED 0x0 +#define AUD_TOP_TR_CTR_FIFO_LOCK_LOCKED 0x4 + +#define AUD_TOP_TR_CTR_FIFO_FULL__B 3 +#define AUD_TOP_TR_CTR_FIFO_FULL__W 1 +#define AUD_TOP_TR_CTR_FIFO_FULL__M 0x8 +#define AUD_TOP_TR_CTR_FIFO_FULL__PRE 0x0 +#define AUD_TOP_TR_CTR_FIFO_FULL_EMPTY 0x0 +#define AUD_TOP_TR_CTR_FIFO_FULL_FULL 0x8 + +#define AUD_TOP_TR_RD_REG__A 0x1010012 +#define AUD_TOP_TR_RD_REG__W 16 +#define AUD_TOP_TR_RD_REG__M 0xFFFF +#define AUD_TOP_TR_RD_REG__PRE 0x0 + +#define AUD_TOP_TR_RD_REG_RESULT__B 0 +#define AUD_TOP_TR_RD_REG_RESULT__W 16 +#define AUD_TOP_TR_RD_REG_RESULT__M 0xFFFF +#define AUD_TOP_TR_RD_REG_RESULT__PRE 0x0 + +#define AUD_TOP_TR_TIMER__A 0x1010013 +#define AUD_TOP_TR_TIMER__W 16 +#define AUD_TOP_TR_TIMER__M 0xFFFF +#define AUD_TOP_TR_TIMER__PRE 0x0 + +#define AUD_TOP_TR_TIMER_CYCLES__B 0 +#define AUD_TOP_TR_TIMER_CYCLES__W 16 +#define AUD_TOP_TR_TIMER_CYCLES__M 0xFFFF +#define AUD_TOP_TR_TIMER_CYCLES__PRE 0x0 + + +#define AUD_TOP_DEMOD_TBO_SEL__A 0x1010014 +#define AUD_TOP_DEMOD_TBO_SEL__W 5 +#define AUD_TOP_DEMOD_TBO_SEL__M 0x1F +#define AUD_TOP_DEMOD_TBO_SEL__PRE 0x0 + + + +#define AUD_DEM_WR_MODUS__A 0x1030030 +#define AUD_DEM_WR_MODUS__W 16 +#define AUD_DEM_WR_MODUS__M 0xFFFF +#define AUD_DEM_WR_MODUS__PRE 0x0 + +#define AUD_DEM_WR_MODUS_MOD_ASS__B 0 +#define AUD_DEM_WR_MODUS_MOD_ASS__W 1 +#define AUD_DEM_WR_MODUS_MOD_ASS__M 0x1 +#define AUD_DEM_WR_MODUS_MOD_ASS__PRE 0x0 +#define AUD_DEM_WR_MODUS_MOD_ASS_OFF 0x0 +#define AUD_DEM_WR_MODUS_MOD_ASS_ON 0x1 + +#define AUD_DEM_WR_MODUS_MOD_STATINTERR__B 1 +#define AUD_DEM_WR_MODUS_MOD_STATINTERR__W 1 +#define AUD_DEM_WR_MODUS_MOD_STATINTERR__M 0x2 +#define AUD_DEM_WR_MODUS_MOD_STATINTERR__PRE 0x0 +#define AUD_DEM_WR_MODUS_MOD_STATINTERR_DISABLE 0x0 +#define AUD_DEM_WR_MODUS_MOD_STATINTERR_ENABLE 0x2 + +#define AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__B 2 +#define AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__W 1 +#define AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__M 0x4 +#define AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__PRE 0x0 +#define AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_ENABLED 0x0 +#define AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_DISABLED 0x4 + +#define AUD_DEM_WR_MODUS_MOD_HDEV_A__B 8 +#define AUD_DEM_WR_MODUS_MOD_HDEV_A__W 1 +#define AUD_DEM_WR_MODUS_MOD_HDEV_A__M 0x100 +#define AUD_DEM_WR_MODUS_MOD_HDEV_A__PRE 0x0 +#define AUD_DEM_WR_MODUS_MOD_HDEV_A_NORMAL 0x0 +#define AUD_DEM_WR_MODUS_MOD_HDEV_A_HIGH_DEVIATION 0x100 + +#define AUD_DEM_WR_MODUS_MOD_CM_A__B 9 +#define AUD_DEM_WR_MODUS_MOD_CM_A__W 1 +#define AUD_DEM_WR_MODUS_MOD_CM_A__M 0x200 +#define AUD_DEM_WR_MODUS_MOD_CM_A__PRE 0x0 +#define AUD_DEM_WR_MODUS_MOD_CM_A_MUTE 0x0 +#define AUD_DEM_WR_MODUS_MOD_CM_A_NOISE 0x200 + +#define AUD_DEM_WR_MODUS_MOD_CM_B__B 10 +#define AUD_DEM_WR_MODUS_MOD_CM_B__W 1 +#define AUD_DEM_WR_MODUS_MOD_CM_B__M 0x400 +#define AUD_DEM_WR_MODUS_MOD_CM_B__PRE 0x0 +#define AUD_DEM_WR_MODUS_MOD_CM_B_MUTE 0x0 +#define AUD_DEM_WR_MODUS_MOD_CM_B_NOISE 0x400 + +#define AUD_DEM_WR_MODUS_MOD_FMRADIO__B 11 +#define AUD_DEM_WR_MODUS_MOD_FMRADIO__W 1 +#define AUD_DEM_WR_MODUS_MOD_FMRADIO__M 0x800 +#define AUD_DEM_WR_MODUS_MOD_FMRADIO__PRE 0x0 +#define AUD_DEM_WR_MODUS_MOD_FMRADIO_US_75U 0x0 +#define AUD_DEM_WR_MODUS_MOD_FMRADIO_EU_50U 0x800 + +#define AUD_DEM_WR_MODUS_MOD_6_5MHZ__B 12 +#define AUD_DEM_WR_MODUS_MOD_6_5MHZ__W 1 +#define AUD_DEM_WR_MODUS_MOD_6_5MHZ__M 0x1000 +#define AUD_DEM_WR_MODUS_MOD_6_5MHZ__PRE 0x0 +#define AUD_DEM_WR_MODUS_MOD_6_5MHZ_SECAM 0x0 +#define AUD_DEM_WR_MODUS_MOD_6_5MHZ_D_K 0x1000 + +#define AUD_DEM_WR_MODUS_MOD_4_5MHZ__B 13 +#define AUD_DEM_WR_MODUS_MOD_4_5MHZ__W 2 +#define AUD_DEM_WR_MODUS_MOD_4_5MHZ__M 0x6000 +#define AUD_DEM_WR_MODUS_MOD_4_5MHZ__PRE 0x0 +#define AUD_DEM_WR_MODUS_MOD_4_5MHZ_M_KOREA 0x0 +#define AUD_DEM_WR_MODUS_MOD_4_5MHZ_M_BTSC 0x2000 +#define AUD_DEM_WR_MODUS_MOD_4_5MHZ_M_EIAJ 0x4000 +#define AUD_DEM_WR_MODUS_MOD_4_5MHZ_CHROMA 0x6000 + +#define AUD_DEM_WR_MODUS_MOD_BTSC__B 15 +#define AUD_DEM_WR_MODUS_MOD_BTSC__W 1 +#define AUD_DEM_WR_MODUS_MOD_BTSC__M 0x8000 +#define AUD_DEM_WR_MODUS_MOD_BTSC__PRE 0x0 +#define AUD_DEM_WR_MODUS_MOD_BTSC_BTSC_STEREO 0x0 +#define AUD_DEM_WR_MODUS_MOD_BTSC_BTSC_SAP 0x8000 + +#define AUD_DEM_WR_STANDARD_SEL__A 0x1030020 +#define AUD_DEM_WR_STANDARD_SEL__W 16 +#define AUD_DEM_WR_STANDARD_SEL__M 0xFFFF +#define AUD_DEM_WR_STANDARD_SEL__PRE 0x0 + +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL__B 0 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL__W 12 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL__M 0xFFF +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL__PRE 0x0 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_AUTO 0x1 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_M_KOREA 0x2 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_BG_FM 0x3 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K1 0x4 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K2 0x5 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K3 0x7 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_BG_NICAM_FM 0x8 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_L_NICAM_AM 0x9 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_I_NICAM_FM 0xA +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K_NICAM_FM 0xB +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_BTSC_STEREO 0x20 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_BTSC_SAP 0x21 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_EIA_J 0x30 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_FM_RADIO 0x40 + + + +#define AUD_DEM_RD_STANDARD_RES__A 0x102007E +#define AUD_DEM_RD_STANDARD_RES__W 16 +#define AUD_DEM_RD_STANDARD_RES__M 0xFFFF +#define AUD_DEM_RD_STANDARD_RES__PRE 0x0 + +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT__B 0 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT__W 16 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT__M 0xFFFF +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT__PRE 0x0 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_NO_SOUND_STANDARD 0x0 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_NTSC_M_DUAL_CARRIER_FM 0x2 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_B_G_DUAL_CARRIER_FM 0x3 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K1_DUAL_CARRIER_FM 0x4 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K2_DUAL_CARRIER_FM 0x5 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K3_DUAL_CARRIER_FM 0x7 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_B_G_NICAM_FM 0x8 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_L_NICAM_AM 0x9 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_I_NICAM_FM 0xA +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K_NICAM_FM 0xB +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_BTSC_STEREO 0x20 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_BTSC_MONO_SAP 0x21 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_NTSC_EIA_J 0x30 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_FM_RADIO 0x40 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_DETECTION_STILL_ACTIVE 0x7FF + +#define AUD_DEM_RD_STATUS__A 0x1020200 +#define AUD_DEM_RD_STATUS__W 16 +#define AUD_DEM_RD_STATUS__M 0xFFFF +#define AUD_DEM_RD_STATUS__PRE 0x0 + +#define AUD_DEM_RD_STATUS_STAT_NEW_RDS__B 0 +#define AUD_DEM_RD_STATUS_STAT_NEW_RDS__W 1 +#define AUD_DEM_RD_STATUS_STAT_NEW_RDS__M 0x1 +#define AUD_DEM_RD_STATUS_STAT_NEW_RDS__PRE 0x0 +#define AUD_DEM_RD_STATUS_STAT_NEW_RDS_NO_RDS_DATA 0x0 +#define AUD_DEM_RD_STATUS_STAT_NEW_RDS_NEW_RDS_DATA 0x1 + +#define AUD_DEM_RD_STATUS_STAT_CARR_A__B 1 +#define AUD_DEM_RD_STATUS_STAT_CARR_A__W 1 +#define AUD_DEM_RD_STATUS_STAT_CARR_A__M 0x2 +#define AUD_DEM_RD_STATUS_STAT_CARR_A__PRE 0x0 +#define AUD_DEM_RD_STATUS_STAT_CARR_A_DETECTED 0x0 +#define AUD_DEM_RD_STATUS_STAT_CARR_A_NOT_DETECTED 0x2 + +#define AUD_DEM_RD_STATUS_STAT_CARR_B__B 2 +#define AUD_DEM_RD_STATUS_STAT_CARR_B__W 1 +#define AUD_DEM_RD_STATUS_STAT_CARR_B__M 0x4 +#define AUD_DEM_RD_STATUS_STAT_CARR_B__PRE 0x0 +#define AUD_DEM_RD_STATUS_STAT_CARR_B_DETECTED 0x0 +#define AUD_DEM_RD_STATUS_STAT_CARR_B_NOT_DETECTED 0x4 + +#define AUD_DEM_RD_STATUS_STAT_NICAM__B 5 +#define AUD_DEM_RD_STATUS_STAT_NICAM__W 1 +#define AUD_DEM_RD_STATUS_STAT_NICAM__M 0x20 +#define AUD_DEM_RD_STATUS_STAT_NICAM__PRE 0x0 +#define AUD_DEM_RD_STATUS_STAT_NICAM_NO_NICAM 0x0 +#define AUD_DEM_RD_STATUS_STAT_NICAM_NICAM_DETECTED 0x20 + +#define AUD_DEM_RD_STATUS_STAT_STEREO__B 6 +#define AUD_DEM_RD_STATUS_STAT_STEREO__W 1 +#define AUD_DEM_RD_STATUS_STAT_STEREO__M 0x40 +#define AUD_DEM_RD_STATUS_STAT_STEREO__PRE 0x0 +#define AUD_DEM_RD_STATUS_STAT_STEREO_NO_STEREO 0x0 +#define AUD_DEM_RD_STATUS_STAT_STEREO_STEREO 0x40 + +#define AUD_DEM_RD_STATUS_STAT_INDEP_MONO__B 7 +#define AUD_DEM_RD_STATUS_STAT_INDEP_MONO__W 1 +#define AUD_DEM_RD_STATUS_STAT_INDEP_MONO__M 0x80 +#define AUD_DEM_RD_STATUS_STAT_INDEP_MONO__PRE 0x0 +#define AUD_DEM_RD_STATUS_STAT_INDEP_MONO_DEPENDENT_FM_MONO_PROGRAM 0x0 +#define AUD_DEM_RD_STATUS_STAT_INDEP_MONO_INDEPENDENT_FM_MONO_PROGRAM 0x80 + +#define AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__B 8 +#define AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__W 1 +#define AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__M 0x100 +#define AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__PRE 0x0 +#define AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP_NO_SAP 0x0 +#define AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP_SAP 0x100 + +#define AUD_DEM_RD_STATUS_BAD_NICAM__B 9 +#define AUD_DEM_RD_STATUS_BAD_NICAM__W 1 +#define AUD_DEM_RD_STATUS_BAD_NICAM__M 0x200 +#define AUD_DEM_RD_STATUS_BAD_NICAM__PRE 0x0 +#define AUD_DEM_RD_STATUS_BAD_NICAM_OK 0x0 +#define AUD_DEM_RD_STATUS_BAD_NICAM_BAD 0x200 + +#define AUD_DEM_RD_RDS_ARRAY_CNT__A 0x102020F +#define AUD_DEM_RD_RDS_ARRAY_CNT__W 12 +#define AUD_DEM_RD_RDS_ARRAY_CNT__M 0xFFF +#define AUD_DEM_RD_RDS_ARRAY_CNT__PRE 0x0 + +#define AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT__B 0 +#define AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT__W 12 +#define AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT__M 0xFFF +#define AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT__PRE 0x0 +#define AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT_RDS_DATA_NOT_VALID 0xFFF + + +#define AUD_DEM_RD_RDS_DATA__A 0x1020210 +#define AUD_DEM_RD_RDS_DATA__W 12 +#define AUD_DEM_RD_RDS_DATA__M 0xFFF +#define AUD_DEM_RD_RDS_DATA__PRE 0x0 + + + +#define AUD_DSP_WR_FM_PRESC__A 0x105000E +#define AUD_DSP_WR_FM_PRESC__W 16 +#define AUD_DSP_WR_FM_PRESC__M 0xFFFF +#define AUD_DSP_WR_FM_PRESC__PRE 0x0 + +#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__B 8 +#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__W 8 +#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__M 0xFF00 +#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__PRE 0x0 +#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_28_KHZ_FM_DEVIATION 0x7F00 +#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_50_KHZ_FM_DEVIATION 0x4800 +#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_75_KHZ_FM_DEVIATION 0x3000 +#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_100_KHZ_FM_DEVIATION 0x2400 +#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_150_KHZ_FM_DEVIATION 0x1800 +#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_180_KHZ_FM_DEVIATION 0x1300 +#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_380_KHZ_FM_DEVIATION 0x900 + + +#define AUD_DSP_WR_NICAM_PRESC__A 0x1050010 +#define AUD_DSP_WR_NICAM_PRESC__W 16 +#define AUD_DSP_WR_NICAM_PRESC__M 0xFFFF +#define AUD_DSP_WR_NICAM_PRESC__PRE 0x0 +#define AUD_DSP_WR_VOLUME__A 0x1050000 +#define AUD_DSP_WR_VOLUME__W 16 +#define AUD_DSP_WR_VOLUME__M 0xFFFF +#define AUD_DSP_WR_VOLUME__PRE 0x0 + +#define AUD_DSP_WR_VOLUME_VOL_MAIN__B 8 +#define AUD_DSP_WR_VOLUME_VOL_MAIN__W 8 +#define AUD_DSP_WR_VOLUME_VOL_MAIN__M 0xFF00 +#define AUD_DSP_WR_VOLUME_VOL_MAIN__PRE 0x0 + +#define AUD_DSP_WR_SRC_I2S_MATR__A 0x1050038 +#define AUD_DSP_WR_SRC_I2S_MATR__W 16 +#define AUD_DSP_WR_SRC_I2S_MATR__M 0xFFFF +#define AUD_DSP_WR_SRC_I2S_MATR__PRE 0x0 + +#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__B 8 +#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__W 8 +#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__M 0xFF00 +#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__PRE 0x0 +#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_MONO 0x0 +#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_AB 0x100 +#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_A 0x300 +#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_B 0x400 + +#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__B 0 +#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__W 8 +#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__M 0xFF +#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__PRE 0x0 +#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_SOUND_A 0x0 +#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_SOUND_B 0x10 +#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_STEREO 0x20 +#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_MONO 0x30 + +#define AUD_DSP_WR_AVC__A 0x1050029 +#define AUD_DSP_WR_AVC__W 16 +#define AUD_DSP_WR_AVC__M 0xFFFF +#define AUD_DSP_WR_AVC__PRE 0x0 + +#define AUD_DSP_WR_AVC_AVC_ON__B 14 +#define AUD_DSP_WR_AVC_AVC_ON__W 2 +#define AUD_DSP_WR_AVC_AVC_ON__M 0xC000 +#define AUD_DSP_WR_AVC_AVC_ON__PRE 0x0 +#define AUD_DSP_WR_AVC_AVC_ON_OFF 0x0 +#define AUD_DSP_WR_AVC_AVC_ON_ON 0xC000 + +#define AUD_DSP_WR_AVC_AVC_DECAY__B 8 +#define AUD_DSP_WR_AVC_AVC_DECAY__W 4 +#define AUD_DSP_WR_AVC_AVC_DECAY__M 0xF00 +#define AUD_DSP_WR_AVC_AVC_DECAY__PRE 0x0 +#define AUD_DSP_WR_AVC_AVC_DECAY_8_SEC 0x800 +#define AUD_DSP_WR_AVC_AVC_DECAY_4_SEC 0x400 +#define AUD_DSP_WR_AVC_AVC_DECAY_2_SEC 0x200 +#define AUD_DSP_WR_AVC_AVC_DECAY_20_MSEC 0x100 + +#define AUD_DSP_WR_AVC_AVC_REF_LEV__B 4 +#define AUD_DSP_WR_AVC_AVC_REF_LEV__W 4 +#define AUD_DSP_WR_AVC_AVC_REF_LEV__M 0xF0 +#define AUD_DSP_WR_AVC_AVC_REF_LEV__PRE 0x0 + +#define AUD_DSP_WR_AVC_AVC_MAX_ATT__B 2 +#define AUD_DSP_WR_AVC_AVC_MAX_ATT__W 2 +#define AUD_DSP_WR_AVC_AVC_MAX_ATT__M 0xC +#define AUD_DSP_WR_AVC_AVC_MAX_ATT__PRE 0x0 +#define AUD_DSP_WR_AVC_AVC_MAX_ATT_24DB 0x0 +#define AUD_DSP_WR_AVC_AVC_MAX_ATT_18DB 0x4 +#define AUD_DSP_WR_AVC_AVC_MAX_ATT_12DB 0x8 + +#define AUD_DSP_WR_AVC_AVC_MAX_GAIN__B 0 +#define AUD_DSP_WR_AVC_AVC_MAX_GAIN__W 2 +#define AUD_DSP_WR_AVC_AVC_MAX_GAIN__M 0x3 +#define AUD_DSP_WR_AVC_AVC_MAX_GAIN__PRE 0x0 +#define AUD_DSP_WR_AVC_AVC_MAX_GAIN_6DB 0x0 +#define AUD_DSP_WR_AVC_AVC_MAX_GAIN_12DB 0x1 +#define AUD_DSP_WR_AVC_AVC_MAX_GAIN_0DB 0x3 + +#define AUD_DSP_WR_QPEAK__A 0x105000C +#define AUD_DSP_WR_QPEAK__W 16 +#define AUD_DSP_WR_QPEAK__M 0xFFFF +#define AUD_DSP_WR_QPEAK__PRE 0x0 + +#define AUD_DSP_WR_QPEAK_SRC_QP__B 8 +#define AUD_DSP_WR_QPEAK_SRC_QP__W 8 +#define AUD_DSP_WR_QPEAK_SRC_QP__M 0xFF00 +#define AUD_DSP_WR_QPEAK_SRC_QP__PRE 0x0 +#define AUD_DSP_WR_QPEAK_SRC_QP_MONO 0x0 +#define AUD_DSP_WR_QPEAK_SRC_QP_STEREO_AB 0x100 +#define AUD_DSP_WR_QPEAK_SRC_QP_STEREO_A 0x300 +#define AUD_DSP_WR_QPEAK_SRC_QP_STEREO_B 0x400 + +#define AUD_DSP_WR_QPEAK_MAT_QP__B 0 +#define AUD_DSP_WR_QPEAK_MAT_QP__W 8 +#define AUD_DSP_WR_QPEAK_MAT_QP__M 0xFF +#define AUD_DSP_WR_QPEAK_MAT_QP__PRE 0x0 +#define AUD_DSP_WR_QPEAK_MAT_QP_SOUND_A 0x0 +#define AUD_DSP_WR_QPEAK_MAT_QP_SOUND_B 0x10 +#define AUD_DSP_WR_QPEAK_MAT_QP_STEREO 0x20 +#define AUD_DSP_WR_QPEAK_MAT_QP_MONO 0x30 + + + + +#define AUD_DSP_RD_QPEAK_L__A 0x1040019 +#define AUD_DSP_RD_QPEAK_L__W 16 +#define AUD_DSP_RD_QPEAK_L__M 0xFFFF +#define AUD_DSP_RD_QPEAK_L__PRE 0x0 + +#define AUD_DSP_RD_QPEAK_R__A 0x104001A +#define AUD_DSP_RD_QPEAK_R__W 16 +#define AUD_DSP_RD_QPEAK_R__M 0xFFFF +#define AUD_DSP_RD_QPEAK_R__PRE 0x0 + + + +#define AUD_DSP_WR_BEEPER__A 0x1050014 +#define AUD_DSP_WR_BEEPER__W 16 +#define AUD_DSP_WR_BEEPER__M 0xFFFF +#define AUD_DSP_WR_BEEPER__PRE 0x0 + +#define AUD_DSP_WR_BEEPER_BEEP_VOLUME__B 8 +#define AUD_DSP_WR_BEEPER_BEEP_VOLUME__W 7 +#define AUD_DSP_WR_BEEPER_BEEP_VOLUME__M 0x7F00 +#define AUD_DSP_WR_BEEPER_BEEP_VOLUME__PRE 0x0 + +#define AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__B 0 +#define AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__W 7 +#define AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__M 0x7F +#define AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__PRE 0x0 + + + +#define AUD_DEM_WR_I2S_CONFIG2__A 0x1030050 +#define AUD_DEM_WR_I2S_CONFIG2__W 16 +#define AUD_DEM_WR_I2S_CONFIG2__M 0xFFFF +#define AUD_DEM_WR_I2S_CONFIG2__PRE 0x0 + +#define AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL__B 6 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL__W 1 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL__M 0x40 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL__PRE 0x0 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL_NORMAL 0x0 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL_INVERTED 0x40 + +#define AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__B 4 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__W 1 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__M 0x10 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__PRE 0x0 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_DISABLE 0x0 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_ENABLE 0x10 + +#define AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__B 3 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__W 1 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__M 0x8 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__PRE 0x0 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST_MASTER 0x0 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST_SLAVE 0x8 + +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__B 2 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__W 1 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__M 0x4 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__PRE 0x0 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL_LEFT_LOW 0x0 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL_LEFT_HIGH 0x4 + +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__B 1 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__W 1 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__M 0x2 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__PRE 0x0 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE_NO_DELAY 0x0 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE_DELAY 0x2 + +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__B 0 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__W 1 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__M 0x1 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__PRE 0x0 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_32 0x0 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_16 0x1 + + + +#define AUD_DSP_WR_I2S_OUT_FS__A 0x105002A +#define AUD_DSP_WR_I2S_OUT_FS__W 16 +#define AUD_DSP_WR_I2S_OUT_FS__M 0xFFFF +#define AUD_DSP_WR_I2S_OUT_FS__PRE 0x0 + +#define AUD_DSP_WR_I2S_OUT_FS_FS_OUT__B 0 +#define AUD_DSP_WR_I2S_OUT_FS_FS_OUT__W 16 +#define AUD_DSP_WR_I2S_OUT_FS_FS_OUT__M 0xFFFF +#define AUD_DSP_WR_I2S_OUT_FS_FS_OUT__PRE 0x0 + +#define AUD_DSP_WR_AV_SYNC__A 0x105002B +#define AUD_DSP_WR_AV_SYNC__W 16 +#define AUD_DSP_WR_AV_SYNC__M 0xFFFF +#define AUD_DSP_WR_AV_SYNC__PRE 0x0 + +#define AUD_DSP_WR_AV_SYNC_AV_ON__B 15 +#define AUD_DSP_WR_AV_SYNC_AV_ON__W 1 +#define AUD_DSP_WR_AV_SYNC_AV_ON__M 0x8000 +#define AUD_DSP_WR_AV_SYNC_AV_ON__PRE 0x0 +#define AUD_DSP_WR_AV_SYNC_AV_ON_DISABLE 0x0 +#define AUD_DSP_WR_AV_SYNC_AV_ON_ENABLE 0x8000 + +#define AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ__B 14 +#define AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ__W 1 +#define AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ__M 0x4000 +#define AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ__PRE 0x0 +#define AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ_MONOCHROME 0x0 +#define AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ_NTSC 0x4000 + +#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL__B 0 +#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL__W 2 +#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL__M 0x3 +#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL__PRE 0x0 +#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL_AUTO 0x0 +#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL_PAL_SECAM 0x1 +#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL_NTSC 0x2 +#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL_MONOCHROME 0x3 + + + +#define AUD_DSP_RD_STATUS2__A 0x104007B +#define AUD_DSP_RD_STATUS2__W 16 +#define AUD_DSP_RD_STATUS2__M 0xFFFF +#define AUD_DSP_RD_STATUS2__PRE 0x0 + +#define AUD_DSP_RD_STATUS2_AV_ACTIVE__B 15 +#define AUD_DSP_RD_STATUS2_AV_ACTIVE__W 1 +#define AUD_DSP_RD_STATUS2_AV_ACTIVE__M 0x8000 +#define AUD_DSP_RD_STATUS2_AV_ACTIVE__PRE 0x0 +#define AUD_DSP_RD_STATUS2_AV_ACTIVE_NO_SYNC 0x0 +#define AUD_DSP_RD_STATUS2_AV_ACTIVE_SYNC_ACTIVE 0x8000 + +#define AUD_DSP_RD_XDFP_FW__A 0x104001D +#define AUD_DSP_RD_XDFP_FW__W 16 +#define AUD_DSP_RD_XDFP_FW__M 0xFFFF +#define AUD_DSP_RD_XDFP_FW__PRE 0x344 + +#define AUD_DSP_RD_XDFP_FW_DSP_FW_REV__B 0 +#define AUD_DSP_RD_XDFP_FW_DSP_FW_REV__W 16 +#define AUD_DSP_RD_XDFP_FW_DSP_FW_REV__M 0xFFFF +#define AUD_DSP_RD_XDFP_FW_DSP_FW_REV__PRE 0x344 + +#define AUD_DSP_RD_XFP_FW__A 0x10404B8 +#define AUD_DSP_RD_XFP_FW__W 16 +#define AUD_DSP_RD_XFP_FW__M 0xFFFF +#define AUD_DSP_RD_XFP_FW__PRE 0x42 + +#define AUD_DSP_RD_XFP_FW_FP_FW_REV__B 0 +#define AUD_DSP_RD_XFP_FW_FP_FW_REV__W 16 +#define AUD_DSP_RD_XFP_FW_FP_FW_REV__M 0xFFFF +#define AUD_DSP_RD_XFP_FW_FP_FW_REV__PRE 0x42 + + + + +#define AUD_DEM_WR_DCO_B_HI__A 0x103009B +#define AUD_DEM_WR_DCO_B_HI__W 16 +#define AUD_DEM_WR_DCO_B_HI__M 0xFFFF +#define AUD_DEM_WR_DCO_B_HI__PRE 0x0 + +#define AUD_DEM_WR_DCO_B_LO__A 0x1030093 +#define AUD_DEM_WR_DCO_B_LO__W 16 +#define AUD_DEM_WR_DCO_B_LO__M 0xFFFF +#define AUD_DEM_WR_DCO_B_LO__PRE 0x0 + +#define AUD_DEM_WR_DCO_A_HI__A 0x10300AB +#define AUD_DEM_WR_DCO_A_HI__W 16 +#define AUD_DEM_WR_DCO_A_HI__M 0xFFFF +#define AUD_DEM_WR_DCO_A_HI__PRE 0x0 + +#define AUD_DEM_WR_DCO_A_LO__A 0x10300A3 +#define AUD_DEM_WR_DCO_A_LO__W 16 +#define AUD_DEM_WR_DCO_A_LO__M 0xFFFF +#define AUD_DEM_WR_DCO_A_LO__PRE 0x0 +#define AUD_DEM_WR_NICAM_THRSHLD__A 0x1030021 +#define AUD_DEM_WR_NICAM_THRSHLD__W 16 +#define AUD_DEM_WR_NICAM_THRSHLD__M 0xFFFF +#define AUD_DEM_WR_NICAM_THRSHLD__PRE 0x2BC + +#define AUD_DEM_WR_NICAM_THRSHLD_NICAM_THLD__B 0 +#define AUD_DEM_WR_NICAM_THRSHLD_NICAM_THLD__W 12 +#define AUD_DEM_WR_NICAM_THRSHLD_NICAM_THLD__M 0xFFF +#define AUD_DEM_WR_NICAM_THRSHLD_NICAM_THLD__PRE 0x2BC + +#define AUD_DEM_WR_A2_THRSHLD__A 0x1030022 +#define AUD_DEM_WR_A2_THRSHLD__W 16 +#define AUD_DEM_WR_A2_THRSHLD__M 0xFFFF +#define AUD_DEM_WR_A2_THRSHLD__PRE 0x190 + +#define AUD_DEM_WR_A2_THRSHLD_A2_THLD__B 0 +#define AUD_DEM_WR_A2_THRSHLD_A2_THLD__W 12 +#define AUD_DEM_WR_A2_THRSHLD_A2_THLD__M 0xFFF +#define AUD_DEM_WR_A2_THRSHLD_A2_THLD__PRE 0x190 + +#define AUD_DEM_WR_BTSC_THRSHLD__A 0x1030023 +#define AUD_DEM_WR_BTSC_THRSHLD__W 16 +#define AUD_DEM_WR_BTSC_THRSHLD__M 0xFFFF +#define AUD_DEM_WR_BTSC_THRSHLD__PRE 0xC + +#define AUD_DEM_WR_BTSC_THRSHLD_BTSC_THLD__B 0 +#define AUD_DEM_WR_BTSC_THRSHLD_BTSC_THLD__W 12 +#define AUD_DEM_WR_BTSC_THRSHLD_BTSC_THLD__M 0xFFF +#define AUD_DEM_WR_BTSC_THRSHLD_BTSC_THLD__PRE 0xC + +#define AUD_DEM_WR_CM_A_THRSHLD__A 0x1030024 +#define AUD_DEM_WR_CM_A_THRSHLD__W 16 +#define AUD_DEM_WR_CM_A_THRSHLD__M 0xFFFF +#define AUD_DEM_WR_CM_A_THRSHLD__PRE 0x2A + +#define AUD_DEM_WR_CM_A_THRSHLD_CM_A_THLD__B 0 +#define AUD_DEM_WR_CM_A_THRSHLD_CM_A_THLD__W 12 +#define AUD_DEM_WR_CM_A_THRSHLD_CM_A_THLD__M 0xFFF +#define AUD_DEM_WR_CM_A_THRSHLD_CM_A_THLD__PRE 0x2A + +#define AUD_DEM_WR_CM_B_THRSHLD__A 0x1030025 +#define AUD_DEM_WR_CM_B_THRSHLD__W 16 +#define AUD_DEM_WR_CM_B_THRSHLD__M 0xFFFF +#define AUD_DEM_WR_CM_B_THRSHLD__PRE 0x2A + +#define AUD_DEM_WR_CM_B_THRSHLD_CM_B_THLD__B 0 +#define AUD_DEM_WR_CM_B_THRSHLD_CM_B_THLD__W 12 +#define AUD_DEM_WR_CM_B_THRSHLD_CM_B_THLD__M 0xFFF +#define AUD_DEM_WR_CM_B_THRSHLD_CM_B_THLD__PRE 0x2A + + + +#define AUD_DEM_RD_NIC_C_AD_BITS__A 0x1020023 +#define AUD_DEM_RD_NIC_C_AD_BITS__W 16 +#define AUD_DEM_RD_NIC_C_AD_BITS__M 0xFFFF +#define AUD_DEM_RD_NIC_C_AD_BITS__PRE 0x0 + +#define AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC__B 0 +#define AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC__W 1 +#define AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC__M 0x1 +#define AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC__PRE 0x0 +#define AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC_NOT_SYNCED 0x0 +#define AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC_SYNCED 0x1 + +#define AUD_DEM_RD_NIC_C_AD_BITS_C__B 1 +#define AUD_DEM_RD_NIC_C_AD_BITS_C__W 4 +#define AUD_DEM_RD_NIC_C_AD_BITS_C__M 0x1E +#define AUD_DEM_RD_NIC_C_AD_BITS_C__PRE 0x0 + +#define AUD_DEM_RD_NIC_C_AD_BITS_ADD_BIT_LO__B 5 +#define AUD_DEM_RD_NIC_C_AD_BITS_ADD_BIT_LO__W 3 +#define AUD_DEM_RD_NIC_C_AD_BITS_ADD_BIT_LO__M 0xE0 +#define AUD_DEM_RD_NIC_C_AD_BITS_ADD_BIT_LO__PRE 0x0 + +#define AUD_DEM_RD_NIC_ADD_BITS_HI__A 0x1020038 +#define AUD_DEM_RD_NIC_ADD_BITS_HI__W 16 +#define AUD_DEM_RD_NIC_ADD_BITS_HI__M 0xFFFF +#define AUD_DEM_RD_NIC_ADD_BITS_HI__PRE 0x0 + +#define AUD_DEM_RD_NIC_ADD_BITS_HI_ADD_BIT_HI__B 0 +#define AUD_DEM_RD_NIC_ADD_BITS_HI_ADD_BIT_HI__W 8 +#define AUD_DEM_RD_NIC_ADD_BITS_HI_ADD_BIT_HI__M 0xFF +#define AUD_DEM_RD_NIC_ADD_BITS_HI_ADD_BIT_HI__PRE 0x0 + +#define AUD_DEM_RD_NIC_CIB__A 0x1020038 +#define AUD_DEM_RD_NIC_CIB__W 16 +#define AUD_DEM_RD_NIC_CIB__M 0xFFFF +#define AUD_DEM_RD_NIC_CIB__PRE 0x0 + +#define AUD_DEM_RD_NIC_CIB_CIB2__B 0 +#define AUD_DEM_RD_NIC_CIB_CIB2__W 1 +#define AUD_DEM_RD_NIC_CIB_CIB2__M 0x1 +#define AUD_DEM_RD_NIC_CIB_CIB2__PRE 0x0 + +#define AUD_DEM_RD_NIC_CIB_CIB1__B 1 +#define AUD_DEM_RD_NIC_CIB_CIB1__W 1 +#define AUD_DEM_RD_NIC_CIB_CIB1__M 0x2 +#define AUD_DEM_RD_NIC_CIB_CIB1__PRE 0x0 + +#define AUD_DEM_RD_NIC_ERROR_RATE__A 0x1020057 +#define AUD_DEM_RD_NIC_ERROR_RATE__W 16 +#define AUD_DEM_RD_NIC_ERROR_RATE__M 0xFFFF +#define AUD_DEM_RD_NIC_ERROR_RATE__PRE 0x0 + +#define AUD_DEM_RD_NIC_ERROR_RATE_ERROR_RATE__B 0 +#define AUD_DEM_RD_NIC_ERROR_RATE_ERROR_RATE__W 12 +#define AUD_DEM_RD_NIC_ERROR_RATE_ERROR_RATE__M 0xFFF +#define AUD_DEM_RD_NIC_ERROR_RATE_ERROR_RATE__PRE 0x0 + + + + +#define AUD_DEM_WR_FM_DEEMPH__A 0x103000F +#define AUD_DEM_WR_FM_DEEMPH__W 16 +#define AUD_DEM_WR_FM_DEEMPH__M 0xFFFF +#define AUD_DEM_WR_FM_DEEMPH__PRE 0x0 +#define AUD_DEM_WR_FM_DEEMPH_50US 0x0 +#define AUD_DEM_WR_FM_DEEMPH_75US 0x1 +#define AUD_DEM_WR_FM_DEEMPH_OFF 0x3F + + +#define AUD_DEM_WR_FM_MATRIX__A 0x103006F +#define AUD_DEM_WR_FM_MATRIX__W 16 +#define AUD_DEM_WR_FM_MATRIX__M 0xFFFF +#define AUD_DEM_WR_FM_MATRIX__PRE 0x0 +#define AUD_DEM_WR_FM_MATRIX_NO_MATRIX 0x0 +#define AUD_DEM_WR_FM_MATRIX_GERMAN_MATRIX 0x1 +#define AUD_DEM_WR_FM_MATRIX_KOREAN_MATRIX 0x2 +#define AUD_DEM_WR_FM_MATRIX_SOUND_A 0x3 +#define AUD_DEM_WR_FM_MATRIX_SOUND_B 0x4 + + + +#define AUD_DSP_RD_FM_IDENT_VALUE__A 0x1040018 +#define AUD_DSP_RD_FM_IDENT_VALUE__W 16 +#define AUD_DSP_RD_FM_IDENT_VALUE__M 0xFFFF +#define AUD_DSP_RD_FM_IDENT_VALUE__PRE 0x0 + +#define AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__B 8 +#define AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__W 8 +#define AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__M 0xFF00 +#define AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__PRE 0x0 + +#define AUD_DSP_RD_FM_DC_LEVEL_A__A 0x104001B +#define AUD_DSP_RD_FM_DC_LEVEL_A__W 16 +#define AUD_DSP_RD_FM_DC_LEVEL_A__M 0xFFFF +#define AUD_DSP_RD_FM_DC_LEVEL_A__PRE 0x0 + +#define AUD_DSP_RD_FM_DC_LEVEL_A_FM_DC_LEV_A__B 0 +#define AUD_DSP_RD_FM_DC_LEVEL_A_FM_DC_LEV_A__W 16 +#define AUD_DSP_RD_FM_DC_LEVEL_A_FM_DC_LEV_A__M 0xFFFF +#define AUD_DSP_RD_FM_DC_LEVEL_A_FM_DC_LEV_A__PRE 0x0 + +#define AUD_DSP_RD_FM_DC_LEVEL_B__A 0x104001C +#define AUD_DSP_RD_FM_DC_LEVEL_B__W 16 +#define AUD_DSP_RD_FM_DC_LEVEL_B__M 0xFFFF +#define AUD_DSP_RD_FM_DC_LEVEL_B__PRE 0x0 + +#define AUD_DSP_RD_FM_DC_LEVEL_B_FM_DC_LEV_B__B 0 +#define AUD_DSP_RD_FM_DC_LEVEL_B_FM_DC_LEV_B__W 16 +#define AUD_DSP_RD_FM_DC_LEVEL_B_FM_DC_LEV_B__M 0xFFFF +#define AUD_DSP_RD_FM_DC_LEVEL_B_FM_DC_LEV_B__PRE 0x0 + + + +#define AUD_DEM_WR_FM_DC_NOTCH_SW__A 0x1030017 +#define AUD_DEM_WR_FM_DC_NOTCH_SW__W 16 +#define AUD_DEM_WR_FM_DC_NOTCH_SW__M 0xFFFF +#define AUD_DEM_WR_FM_DC_NOTCH_SW__PRE 0x0 + +#define AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW__B 0 +#define AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW__W 16 +#define AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW__M 0xFFFF +#define AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW__PRE 0x0 +#define AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW_ON 0x0 +#define AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW_OFF 0x3F + + + + +#define AUD_DSP_WR_SYNC_OUT__A 0x1050026 +#define AUD_DSP_WR_SYNC_OUT__W 16 +#define AUD_DSP_WR_SYNC_OUT__M 0xFFFF +#define AUD_DSP_WR_SYNC_OUT__PRE 0x0 +#define AUD_DSP_WR_SYNC_OUT_OFF 0x0 +#define AUD_DSP_WR_SYNC_OUT_SYNCHRONOUS 0x1 + + + +#define AUD_XFP_DRAM_1K__A 0x1060000 +#define AUD_XFP_DRAM_1K__W 16 +#define AUD_XFP_DRAM_1K__M 0xFFFF +#define AUD_XFP_DRAM_1K__PRE 0x0 +#define AUD_XFP_DRAM_1K_D__B 0 +#define AUD_XFP_DRAM_1K_D__W 16 +#define AUD_XFP_DRAM_1K_D__M 0xFFFF +#define AUD_XFP_DRAM_1K_D__PRE 0x0 + + + +#define AUD_XFP_PRAM_4K__A 0x1070000 +#define AUD_XFP_PRAM_4K__W 16 +#define AUD_XFP_PRAM_4K__M 0xFFFF +#define AUD_XFP_PRAM_4K__PRE 0x0 +#define AUD_XFP_PRAM_4K_D__B 0 +#define AUD_XFP_PRAM_4K_D__W 16 +#define AUD_XFP_PRAM_4K_D__M 0xFFFF +#define AUD_XFP_PRAM_4K_D__PRE 0x0 + + + +#define AUD_XDFP_DRAM_1K__A 0x1080000 +#define AUD_XDFP_DRAM_1K__W 16 +#define AUD_XDFP_DRAM_1K__M 0xFFFF +#define AUD_XDFP_DRAM_1K__PRE 0x0 +#define AUD_XDFP_DRAM_1K_D__B 0 +#define AUD_XDFP_DRAM_1K_D__W 16 +#define AUD_XDFP_DRAM_1K_D__M 0xFFFF +#define AUD_XDFP_DRAM_1K_D__PRE 0x0 + + + +#define AUD_XDFP_PRAM_4K__A 0x1090000 +#define AUD_XDFP_PRAM_4K__W 16 +#define AUD_XDFP_PRAM_4K__M 0xFFFF +#define AUD_XDFP_PRAM_4K__PRE 0x0 +#define AUD_XDFP_PRAM_4K_D__B 0 +#define AUD_XDFP_PRAM_4K_D__W 16 +#define AUD_XDFP_PRAM_4K_D__M 0xFFFF +#define AUD_XDFP_PRAM_4K_D__PRE 0x0 + + + + + +#define FEC_COMM_EXEC__A 0x2400000 +#define FEC_COMM_EXEC__W 2 +#define FEC_COMM_EXEC__M 0x3 +#define FEC_COMM_EXEC__PRE 0x0 +#define FEC_COMM_EXEC_STOP 0x0 +#define FEC_COMM_EXEC_ACTIVE 0x1 +#define FEC_COMM_EXEC_HOLD 0x2 + +#define FEC_COMM_MB__A 0x2400002 +#define FEC_COMM_MB__W 16 +#define FEC_COMM_MB__M 0xFFFF +#define FEC_COMM_MB__PRE 0x0 +#define FEC_COMM_INT_REQ__A 0x2400003 +#define FEC_COMM_INT_REQ__W 16 +#define FEC_COMM_INT_REQ__M 0xFFFF +#define FEC_COMM_INT_REQ__PRE 0x0 +#define FEC_COMM_INT_REQ_OC_REQ__B 0 +#define FEC_COMM_INT_REQ_OC_REQ__W 1 +#define FEC_COMM_INT_REQ_OC_REQ__M 0x1 +#define FEC_COMM_INT_REQ_OC_REQ__PRE 0x0 +#define FEC_COMM_INT_REQ_RS_REQ__B 1 +#define FEC_COMM_INT_REQ_RS_REQ__W 1 +#define FEC_COMM_INT_REQ_RS_REQ__M 0x2 +#define FEC_COMM_INT_REQ_RS_REQ__PRE 0x0 +#define FEC_COMM_INT_REQ_DI_REQ__B 2 +#define FEC_COMM_INT_REQ_DI_REQ__W 1 +#define FEC_COMM_INT_REQ_DI_REQ__M 0x4 +#define FEC_COMM_INT_REQ_DI_REQ__PRE 0x0 + +#define FEC_COMM_INT_STA__A 0x2400005 +#define FEC_COMM_INT_STA__W 16 +#define FEC_COMM_INT_STA__M 0xFFFF +#define FEC_COMM_INT_STA__PRE 0x0 +#define FEC_COMM_INT_MSK__A 0x2400006 +#define FEC_COMM_INT_MSK__W 16 +#define FEC_COMM_INT_MSK__M 0xFFFF +#define FEC_COMM_INT_MSK__PRE 0x0 +#define FEC_COMM_INT_STM__A 0x2400007 +#define FEC_COMM_INT_STM__W 16 +#define FEC_COMM_INT_STM__M 0xFFFF +#define FEC_COMM_INT_STM__PRE 0x0 + + + +#define FEC_TOP_COMM_EXEC__A 0x2410000 +#define FEC_TOP_COMM_EXEC__W 2 +#define FEC_TOP_COMM_EXEC__M 0x3 +#define FEC_TOP_COMM_EXEC__PRE 0x0 +#define FEC_TOP_COMM_EXEC_STOP 0x0 +#define FEC_TOP_COMM_EXEC_ACTIVE 0x1 +#define FEC_TOP_COMM_EXEC_HOLD 0x2 + + +#define FEC_TOP_ANNEX__A 0x2410010 +#define FEC_TOP_ANNEX__W 2 +#define FEC_TOP_ANNEX__M 0x3 +#define FEC_TOP_ANNEX__PRE 0x0 +#define FEC_TOP_ANNEX_A 0x0 +#define FEC_TOP_ANNEX_B 0x1 +#define FEC_TOP_ANNEX_C 0x2 +#define FEC_TOP_ANNEX_D 0x3 + + + +#define FEC_DI_COMM_EXEC__A 0x2420000 +#define FEC_DI_COMM_EXEC__W 2 +#define FEC_DI_COMM_EXEC__M 0x3 +#define FEC_DI_COMM_EXEC__PRE 0x0 +#define FEC_DI_COMM_EXEC_STOP 0x0 +#define FEC_DI_COMM_EXEC_ACTIVE 0x1 +#define FEC_DI_COMM_EXEC_HOLD 0x2 + +#define FEC_DI_COMM_MB__A 0x2420002 +#define FEC_DI_COMM_MB__W 2 +#define FEC_DI_COMM_MB__M 0x3 +#define FEC_DI_COMM_MB__PRE 0x0 +#define FEC_DI_COMM_MB_CTL__B 0 +#define FEC_DI_COMM_MB_CTL__W 1 +#define FEC_DI_COMM_MB_CTL__M 0x1 +#define FEC_DI_COMM_MB_CTL__PRE 0x0 +#define FEC_DI_COMM_MB_CTL_OFF 0x0 +#define FEC_DI_COMM_MB_CTL_ON 0x1 +#define FEC_DI_COMM_MB_OBS__B 1 +#define FEC_DI_COMM_MB_OBS__W 1 +#define FEC_DI_COMM_MB_OBS__M 0x2 +#define FEC_DI_COMM_MB_OBS__PRE 0x0 +#define FEC_DI_COMM_MB_OBS_OFF 0x0 +#define FEC_DI_COMM_MB_OBS_ON 0x2 + +#define FEC_DI_COMM_INT_REQ__A 0x2420003 +#define FEC_DI_COMM_INT_REQ__W 1 +#define FEC_DI_COMM_INT_REQ__M 0x1 +#define FEC_DI_COMM_INT_REQ__PRE 0x0 +#define FEC_DI_COMM_INT_STA__A 0x2420005 +#define FEC_DI_COMM_INT_STA__W 2 +#define FEC_DI_COMM_INT_STA__M 0x3 +#define FEC_DI_COMM_INT_STA__PRE 0x0 + +#define FEC_DI_COMM_INT_STA_STAT_INT__B 0 +#define FEC_DI_COMM_INT_STA_STAT_INT__W 1 +#define FEC_DI_COMM_INT_STA_STAT_INT__M 0x1 +#define FEC_DI_COMM_INT_STA_STAT_INT__PRE 0x0 + +#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__B 1 +#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__W 1 +#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__M 0x2 +#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__PRE 0x0 + +#define FEC_DI_COMM_INT_MSK__A 0x2420006 +#define FEC_DI_COMM_INT_MSK__W 2 +#define FEC_DI_COMM_INT_MSK__M 0x3 +#define FEC_DI_COMM_INT_MSK__PRE 0x0 +#define FEC_DI_COMM_INT_MSK_STAT_INT__B 0 +#define FEC_DI_COMM_INT_MSK_STAT_INT__W 1 +#define FEC_DI_COMM_INT_MSK_STAT_INT__M 0x1 +#define FEC_DI_COMM_INT_MSK_STAT_INT__PRE 0x0 +#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__B 1 +#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__W 1 +#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__M 0x2 +#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__PRE 0x0 + +#define FEC_DI_COMM_INT_STM__A 0x2420007 +#define FEC_DI_COMM_INT_STM__W 2 +#define FEC_DI_COMM_INT_STM__M 0x3 +#define FEC_DI_COMM_INT_STM__PRE 0x0 +#define FEC_DI_COMM_INT_STM_STAT_INT__B 0 +#define FEC_DI_COMM_INT_STM_STAT_INT__W 1 +#define FEC_DI_COMM_INT_STM_STAT_INT__M 0x1 +#define FEC_DI_COMM_INT_STM_STAT_INT__PRE 0x0 +#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__B 1 +#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__W 1 +#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__M 0x2 +#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__PRE 0x0 + + +#define FEC_DI_STATUS__A 0x2420010 +#define FEC_DI_STATUS__W 1 +#define FEC_DI_STATUS__M 0x1 +#define FEC_DI_STATUS__PRE 0x0 +#define FEC_DI_MODE__A 0x2420011 +#define FEC_DI_MODE__W 3 +#define FEC_DI_MODE__M 0x7 +#define FEC_DI_MODE__PRE 0x0 + +#define FEC_DI_MODE_NO_SYNC__B 0 +#define FEC_DI_MODE_NO_SYNC__W 1 +#define FEC_DI_MODE_NO_SYNC__M 0x1 +#define FEC_DI_MODE_NO_SYNC__PRE 0x0 + +#define FEC_DI_MODE_IGNORE_LOST_SYNC__B 1 +#define FEC_DI_MODE_IGNORE_LOST_SYNC__W 1 +#define FEC_DI_MODE_IGNORE_LOST_SYNC__M 0x2 +#define FEC_DI_MODE_IGNORE_LOST_SYNC__PRE 0x0 + +#define FEC_DI_MODE_IGNORE_TIMEOUT__B 2 +#define FEC_DI_MODE_IGNORE_TIMEOUT__W 1 +#define FEC_DI_MODE_IGNORE_TIMEOUT__M 0x4 +#define FEC_DI_MODE_IGNORE_TIMEOUT__PRE 0x0 + + +#define FEC_DI_CONTROL_WORD__A 0x2420012 +#define FEC_DI_CONTROL_WORD__W 4 +#define FEC_DI_CONTROL_WORD__M 0xF +#define FEC_DI_CONTROL_WORD__PRE 0x0 + +#define FEC_DI_RESTART__A 0x2420013 +#define FEC_DI_RESTART__W 1 +#define FEC_DI_RESTART__M 0x1 +#define FEC_DI_RESTART__PRE 0x0 + +#define FEC_DI_TIMEOUT_LO__A 0x2420014 +#define FEC_DI_TIMEOUT_LO__W 16 +#define FEC_DI_TIMEOUT_LO__M 0xFFFF +#define FEC_DI_TIMEOUT_LO__PRE 0x0 + +#define FEC_DI_TIMEOUT_HI__A 0x2420015 +#define FEC_DI_TIMEOUT_HI__W 8 +#define FEC_DI_TIMEOUT_HI__M 0xFF +#define FEC_DI_TIMEOUT_HI__PRE 0xA + + + +#define FEC_RS_COMM_EXEC__A 0x2430000 +#define FEC_RS_COMM_EXEC__W 2 +#define FEC_RS_COMM_EXEC__M 0x3 +#define FEC_RS_COMM_EXEC__PRE 0x0 +#define FEC_RS_COMM_EXEC_STOP 0x0 +#define FEC_RS_COMM_EXEC_ACTIVE 0x1 +#define FEC_RS_COMM_EXEC_HOLD 0x2 + +#define FEC_RS_COMM_MB__A 0x2430002 +#define FEC_RS_COMM_MB__W 2 +#define FEC_RS_COMM_MB__M 0x3 +#define FEC_RS_COMM_MB__PRE 0x0 +#define FEC_RS_COMM_MB_CTL__B 0 +#define FEC_RS_COMM_MB_CTL__W 1 +#define FEC_RS_COMM_MB_CTL__M 0x1 +#define FEC_RS_COMM_MB_CTL__PRE 0x0 +#define FEC_RS_COMM_MB_CTL_OFF 0x0 +#define FEC_RS_COMM_MB_CTL_ON 0x1 +#define FEC_RS_COMM_MB_OBS__B 1 +#define FEC_RS_COMM_MB_OBS__W 1 +#define FEC_RS_COMM_MB_OBS__M 0x2 +#define FEC_RS_COMM_MB_OBS__PRE 0x0 +#define FEC_RS_COMM_MB_OBS_OFF 0x0 +#define FEC_RS_COMM_MB_OBS_ON 0x2 + +#define FEC_RS_COMM_INT_REQ__A 0x2430003 +#define FEC_RS_COMM_INT_REQ__W 1 +#define FEC_RS_COMM_INT_REQ__M 0x1 +#define FEC_RS_COMM_INT_REQ__PRE 0x0 +#define FEC_RS_COMM_INT_STA__A 0x2430005 +#define FEC_RS_COMM_INT_STA__W 2 +#define FEC_RS_COMM_INT_STA__M 0x3 +#define FEC_RS_COMM_INT_STA__PRE 0x0 + +#define FEC_RS_COMM_INT_STA_FAILURE_INT__B 0 +#define FEC_RS_COMM_INT_STA_FAILURE_INT__W 1 +#define FEC_RS_COMM_INT_STA_FAILURE_INT__M 0x1 +#define FEC_RS_COMM_INT_STA_FAILURE_INT__PRE 0x0 + +#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__B 1 +#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__W 1 +#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__M 0x2 +#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__PRE 0x0 + +#define FEC_RS_COMM_INT_MSK__A 0x2430006 +#define FEC_RS_COMM_INT_MSK__W 2 +#define FEC_RS_COMM_INT_MSK__M 0x3 +#define FEC_RS_COMM_INT_MSK__PRE 0x0 +#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__B 0 +#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__W 1 +#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__M 0x1 +#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__PRE 0x0 +#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__B 1 +#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__W 1 +#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__M 0x2 +#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__PRE 0x0 + +#define FEC_RS_COMM_INT_STM__A 0x2430007 +#define FEC_RS_COMM_INT_STM__W 2 +#define FEC_RS_COMM_INT_STM__M 0x3 +#define FEC_RS_COMM_INT_STM__PRE 0x0 +#define FEC_RS_COMM_INT_STM_FAILURE_MSK__B 0 +#define FEC_RS_COMM_INT_STM_FAILURE_MSK__W 1 +#define FEC_RS_COMM_INT_STM_FAILURE_MSK__M 0x1 +#define FEC_RS_COMM_INT_STM_FAILURE_MSK__PRE 0x0 +#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__B 1 +#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__W 1 +#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__M 0x2 +#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__PRE 0x0 + +#define FEC_RS_STATUS__A 0x2430010 +#define FEC_RS_STATUS__W 1 +#define FEC_RS_STATUS__M 0x1 +#define FEC_RS_STATUS__PRE 0x0 +#define FEC_RS_MODE__A 0x2430011 +#define FEC_RS_MODE__W 1 +#define FEC_RS_MODE__M 0x1 +#define FEC_RS_MODE__PRE 0x0 + +#define FEC_RS_MODE_BYPASS__B 0 +#define FEC_RS_MODE_BYPASS__W 1 +#define FEC_RS_MODE_BYPASS__M 0x1 +#define FEC_RS_MODE_BYPASS__PRE 0x0 + +#define FEC_RS_MEASUREMENT_PERIOD__A 0x2430012 +#define FEC_RS_MEASUREMENT_PERIOD__W 16 +#define FEC_RS_MEASUREMENT_PERIOD__M 0xFFFF +#define FEC_RS_MEASUREMENT_PERIOD__PRE 0x1171 + +#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__B 0 +#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__W 16 +#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__M 0xFFFF +#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__PRE 0x1171 + +#define FEC_RS_MEASUREMENT_PRESCALE__A 0x2430013 +#define FEC_RS_MEASUREMENT_PRESCALE__W 16 +#define FEC_RS_MEASUREMENT_PRESCALE__M 0xFFFF +#define FEC_RS_MEASUREMENT_PRESCALE__PRE 0x1 + +#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__B 0 +#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__W 16 +#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__M 0xFFFF +#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__PRE 0x1 + +#define FEC_RS_NR_BIT_ERRORS__A 0x2430014 +#define FEC_RS_NR_BIT_ERRORS__W 16 +#define FEC_RS_NR_BIT_ERRORS__M 0xFFFF +#define FEC_RS_NR_BIT_ERRORS__PRE 0xFFFF + +#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__B 0 +#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__W 12 +#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M 0xFFF +#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__PRE 0xFFF + +#define FEC_RS_NR_BIT_ERRORS_EXP__B 12 +#define FEC_RS_NR_BIT_ERRORS_EXP__W 4 +#define FEC_RS_NR_BIT_ERRORS_EXP__M 0xF000 +#define FEC_RS_NR_BIT_ERRORS_EXP__PRE 0xF000 + +#define FEC_RS_NR_SYMBOL_ERRORS__A 0x2430015 +#define FEC_RS_NR_SYMBOL_ERRORS__W 16 +#define FEC_RS_NR_SYMBOL_ERRORS__M 0xFFFF +#define FEC_RS_NR_SYMBOL_ERRORS__PRE 0xFFFF + +#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__B 0 +#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__W 12 +#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__M 0xFFF +#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__PRE 0xFFF + +#define FEC_RS_NR_SYMBOL_ERRORS_EXP__B 12 +#define FEC_RS_NR_SYMBOL_ERRORS_EXP__W 4 +#define FEC_RS_NR_SYMBOL_ERRORS_EXP__M 0xF000 +#define FEC_RS_NR_SYMBOL_ERRORS_EXP__PRE 0xF000 + +#define FEC_RS_NR_PACKET_ERRORS__A 0x2430016 +#define FEC_RS_NR_PACKET_ERRORS__W 16 +#define FEC_RS_NR_PACKET_ERRORS__M 0xFFFF +#define FEC_RS_NR_PACKET_ERRORS__PRE 0xFFFF + +#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__B 0 +#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__W 12 +#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__M 0xFFF +#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__PRE 0xFFF + +#define FEC_RS_NR_PACKET_ERRORS_EXP__B 12 +#define FEC_RS_NR_PACKET_ERRORS_EXP__W 4 +#define FEC_RS_NR_PACKET_ERRORS_EXP__M 0xF000 +#define FEC_RS_NR_PACKET_ERRORS_EXP__PRE 0xF000 + +#define FEC_RS_NR_FAILURES__A 0x2430017 +#define FEC_RS_NR_FAILURES__W 16 +#define FEC_RS_NR_FAILURES__M 0xFFFF +#define FEC_RS_NR_FAILURES__PRE 0x0 + +#define FEC_RS_NR_FAILURES_FIXED_MANT__B 0 +#define FEC_RS_NR_FAILURES_FIXED_MANT__W 12 +#define FEC_RS_NR_FAILURES_FIXED_MANT__M 0xFFF +#define FEC_RS_NR_FAILURES_FIXED_MANT__PRE 0x0 + +#define FEC_RS_NR_FAILURES_EXP__B 12 +#define FEC_RS_NR_FAILURES_EXP__W 4 +#define FEC_RS_NR_FAILURES_EXP__M 0xF000 +#define FEC_RS_NR_FAILURES_EXP__PRE 0x0 + + + +#define FEC_OC_COMM_EXEC__A 0x2440000 +#define FEC_OC_COMM_EXEC__W 2 +#define FEC_OC_COMM_EXEC__M 0x3 +#define FEC_OC_COMM_EXEC__PRE 0x0 +#define FEC_OC_COMM_EXEC_STOP 0x0 +#define FEC_OC_COMM_EXEC_ACTIVE 0x1 +#define FEC_OC_COMM_EXEC_HOLD 0x2 + +#define FEC_OC_COMM_MB__A 0x2440002 +#define FEC_OC_COMM_MB__W 2 +#define FEC_OC_COMM_MB__M 0x3 +#define FEC_OC_COMM_MB__PRE 0x0 +#define FEC_OC_COMM_MB_CTL__B 0 +#define FEC_OC_COMM_MB_CTL__W 1 +#define FEC_OC_COMM_MB_CTL__M 0x1 +#define FEC_OC_COMM_MB_CTL__PRE 0x0 +#define FEC_OC_COMM_MB_CTL_OFF 0x0 +#define FEC_OC_COMM_MB_CTL_ON 0x1 +#define FEC_OC_COMM_MB_OBS__B 1 +#define FEC_OC_COMM_MB_OBS__W 1 +#define FEC_OC_COMM_MB_OBS__M 0x2 +#define FEC_OC_COMM_MB_OBS__PRE 0x0 +#define FEC_OC_COMM_MB_OBS_OFF 0x0 +#define FEC_OC_COMM_MB_OBS_ON 0x2 + +#define FEC_OC_COMM_INT_REQ__A 0x2440003 +#define FEC_OC_COMM_INT_REQ__W 1 +#define FEC_OC_COMM_INT_REQ__M 0x1 +#define FEC_OC_COMM_INT_REQ__PRE 0x0 +#define FEC_OC_COMM_INT_STA__A 0x2440005 +#define FEC_OC_COMM_INT_STA__W 8 +#define FEC_OC_COMM_INT_STA__M 0xFF +#define FEC_OC_COMM_INT_STA__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__B 0 +#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__W 1 +#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__M 0x1 +#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__B 1 +#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__W 1 +#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__M 0x2 +#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__B 2 +#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__W 1 +#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__M 0x4 +#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__B 3 +#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__W 1 +#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__M 0x8 +#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__B 4 +#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__W 1 +#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__M 0x10 +#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__B 5 +#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__W 1 +#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__M 0x20 +#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__B 6 +#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__W 1 +#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__M 0x40 +#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__B 7 +#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__W 1 +#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__M 0x80 +#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_MSK__A 0x2440006 +#define FEC_OC_COMM_INT_MSK__W 8 +#define FEC_OC_COMM_INT_MSK__M 0xFF +#define FEC_OC_COMM_INT_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__B 0 +#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__M 0x1 +#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__B 1 +#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__M 0x2 +#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__B 2 +#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__M 0x4 +#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__B 3 +#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__M 0x8 +#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__B 4 +#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__M 0x10 +#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__B 5 +#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__M 0x20 +#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__B 6 +#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__M 0x40 +#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__B 7 +#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__M 0x80 +#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__PRE 0x0 + +#define FEC_OC_COMM_INT_STM__A 0x2440007 +#define FEC_OC_COMM_INT_STM__W 8 +#define FEC_OC_COMM_INT_STM__M 0xFF +#define FEC_OC_COMM_INT_STM__PRE 0x0 +#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__B 0 +#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__W 1 +#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__M 0x1 +#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__B 1 +#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__W 1 +#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__M 0x2 +#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__B 2 +#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__W 1 +#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__M 0x4 +#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__B 3 +#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__W 1 +#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__M 0x8 +#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__B 4 +#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__W 1 +#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__M 0x10 +#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__B 5 +#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__W 1 +#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__M 0x20 +#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__B 6 +#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__W 1 +#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__M 0x40 +#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__B 7 +#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__W 1 +#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__M 0x80 +#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__PRE 0x0 + +#define FEC_OC_STATUS__A 0x2440010 +#define FEC_OC_STATUS__W 5 +#define FEC_OC_STATUS__M 0x1F +#define FEC_OC_STATUS__PRE 0x0 + +#define FEC_OC_STATUS_DPR_STATUS__B 0 +#define FEC_OC_STATUS_DPR_STATUS__W 1 +#define FEC_OC_STATUS_DPR_STATUS__M 0x1 +#define FEC_OC_STATUS_DPR_STATUS__PRE 0x0 + +#define FEC_OC_STATUS_SNC_STATUS__B 1 +#define FEC_OC_STATUS_SNC_STATUS__W 2 +#define FEC_OC_STATUS_SNC_STATUS__M 0x6 +#define FEC_OC_STATUS_SNC_STATUS__PRE 0x0 + +#define FEC_OC_STATUS_FIFO_FULL__B 3 +#define FEC_OC_STATUS_FIFO_FULL__W 1 +#define FEC_OC_STATUS_FIFO_FULL__M 0x8 +#define FEC_OC_STATUS_FIFO_FULL__PRE 0x0 + +#define FEC_OC_STATUS_FIFO_EMPTY__B 4 +#define FEC_OC_STATUS_FIFO_EMPTY__W 1 +#define FEC_OC_STATUS_FIFO_EMPTY__M 0x10 +#define FEC_OC_STATUS_FIFO_EMPTY__PRE 0x0 + +#define FEC_OC_MODE__A 0x2440011 +#define FEC_OC_MODE__W 4 +#define FEC_OC_MODE__M 0xF +#define FEC_OC_MODE__PRE 0x0 + +#define FEC_OC_MODE_PARITY__B 0 +#define FEC_OC_MODE_PARITY__W 1 +#define FEC_OC_MODE_PARITY__M 0x1 +#define FEC_OC_MODE_PARITY__PRE 0x0 + +#define FEC_OC_MODE_TRANSPARENT__B 1 +#define FEC_OC_MODE_TRANSPARENT__W 1 +#define FEC_OC_MODE_TRANSPARENT__M 0x2 +#define FEC_OC_MODE_TRANSPARENT__PRE 0x0 + +#define FEC_OC_MODE_CLEAR__B 2 +#define FEC_OC_MODE_CLEAR__W 1 +#define FEC_OC_MODE_CLEAR__M 0x4 +#define FEC_OC_MODE_CLEAR__PRE 0x0 + +#define FEC_OC_MODE_RETAIN_FRAMING__B 3 +#define FEC_OC_MODE_RETAIN_FRAMING__W 1 +#define FEC_OC_MODE_RETAIN_FRAMING__M 0x8 +#define FEC_OC_MODE_RETAIN_FRAMING__PRE 0x0 + +#define FEC_OC_DPR_MODE__A 0x2440012 +#define FEC_OC_DPR_MODE__W 2 +#define FEC_OC_DPR_MODE__M 0x3 +#define FEC_OC_DPR_MODE__PRE 0x0 + +#define FEC_OC_DPR_MODE_ERR_DISABLE__B 0 +#define FEC_OC_DPR_MODE_ERR_DISABLE__W 1 +#define FEC_OC_DPR_MODE_ERR_DISABLE__M 0x1 +#define FEC_OC_DPR_MODE_ERR_DISABLE__PRE 0x0 + +#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__B 1 +#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__W 1 +#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__M 0x2 +#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__PRE 0x0 + + +#define FEC_OC_DPR_UNLOCK__A 0x2440013 +#define FEC_OC_DPR_UNLOCK__W 1 +#define FEC_OC_DPR_UNLOCK__M 0x1 +#define FEC_OC_DPR_UNLOCK__PRE 0x0 +#define FEC_OC_DTO_MODE__A 0x2440014 +#define FEC_OC_DTO_MODE__W 3 +#define FEC_OC_DTO_MODE__M 0x7 +#define FEC_OC_DTO_MODE__PRE 0x0 + +#define FEC_OC_DTO_MODE_DYNAMIC__B 0 +#define FEC_OC_DTO_MODE_DYNAMIC__W 1 +#define FEC_OC_DTO_MODE_DYNAMIC__M 0x1 +#define FEC_OC_DTO_MODE_DYNAMIC__PRE 0x0 + +#define FEC_OC_DTO_MODE_DUTY_CYCLE__B 1 +#define FEC_OC_DTO_MODE_DUTY_CYCLE__W 1 +#define FEC_OC_DTO_MODE_DUTY_CYCLE__M 0x2 +#define FEC_OC_DTO_MODE_DUTY_CYCLE__PRE 0x0 + +#define FEC_OC_DTO_MODE_OFFSET_ENABLE__B 2 +#define FEC_OC_DTO_MODE_OFFSET_ENABLE__W 1 +#define FEC_OC_DTO_MODE_OFFSET_ENABLE__M 0x4 +#define FEC_OC_DTO_MODE_OFFSET_ENABLE__PRE 0x0 + + +#define FEC_OC_DTO_PERIOD__A 0x2440015 +#define FEC_OC_DTO_PERIOD__W 8 +#define FEC_OC_DTO_PERIOD__M 0xFF +#define FEC_OC_DTO_PERIOD__PRE 0x0 +#define FEC_OC_DTO_RATE_LO__A 0x2440016 +#define FEC_OC_DTO_RATE_LO__W 16 +#define FEC_OC_DTO_RATE_LO__M 0xFFFF +#define FEC_OC_DTO_RATE_LO__PRE 0x0 + +#define FEC_OC_DTO_RATE_LO_RATE_LO__B 0 +#define FEC_OC_DTO_RATE_LO_RATE_LO__W 16 +#define FEC_OC_DTO_RATE_LO_RATE_LO__M 0xFFFF +#define FEC_OC_DTO_RATE_LO_RATE_LO__PRE 0x0 + +#define FEC_OC_DTO_RATE_HI__A 0x2440017 +#define FEC_OC_DTO_RATE_HI__W 10 +#define FEC_OC_DTO_RATE_HI__M 0x3FF +#define FEC_OC_DTO_RATE_HI__PRE 0xC0 + +#define FEC_OC_DTO_RATE_HI_RATE_HI__B 0 +#define FEC_OC_DTO_RATE_HI_RATE_HI__W 10 +#define FEC_OC_DTO_RATE_HI_RATE_HI__M 0x3FF +#define FEC_OC_DTO_RATE_HI_RATE_HI__PRE 0xC0 + +#define FEC_OC_DTO_BURST_LEN__A 0x2440018 +#define FEC_OC_DTO_BURST_LEN__W 8 +#define FEC_OC_DTO_BURST_LEN__M 0xFF +#define FEC_OC_DTO_BURST_LEN__PRE 0xBC + +#define FEC_OC_DTO_BURST_LEN_BURST_LEN__B 0 +#define FEC_OC_DTO_BURST_LEN_BURST_LEN__W 8 +#define FEC_OC_DTO_BURST_LEN_BURST_LEN__M 0xFF +#define FEC_OC_DTO_BURST_LEN_BURST_LEN__PRE 0xBC + +#define FEC_OC_FCT_MODE__A 0x244001A +#define FEC_OC_FCT_MODE__W 2 +#define FEC_OC_FCT_MODE__M 0x3 +#define FEC_OC_FCT_MODE__PRE 0x0 + +#define FEC_OC_FCT_MODE_RAT_ENA__B 0 +#define FEC_OC_FCT_MODE_RAT_ENA__W 1 +#define FEC_OC_FCT_MODE_RAT_ENA__M 0x1 +#define FEC_OC_FCT_MODE_RAT_ENA__PRE 0x0 + +#define FEC_OC_FCT_MODE_VIRT_ENA__B 1 +#define FEC_OC_FCT_MODE_VIRT_ENA__W 1 +#define FEC_OC_FCT_MODE_VIRT_ENA__M 0x2 +#define FEC_OC_FCT_MODE_VIRT_ENA__PRE 0x0 + +#define FEC_OC_FCT_USAGE__A 0x244001B +#define FEC_OC_FCT_USAGE__W 3 +#define FEC_OC_FCT_USAGE__M 0x7 +#define FEC_OC_FCT_USAGE__PRE 0x2 + +#define FEC_OC_FCT_USAGE_USAGE__B 0 +#define FEC_OC_FCT_USAGE_USAGE__W 3 +#define FEC_OC_FCT_USAGE_USAGE__M 0x7 +#define FEC_OC_FCT_USAGE_USAGE__PRE 0x2 + +#define FEC_OC_FCT_OCCUPATION__A 0x244001C +#define FEC_OC_FCT_OCCUPATION__W 12 +#define FEC_OC_FCT_OCCUPATION__M 0xFFF +#define FEC_OC_FCT_OCCUPATION__PRE 0x0 + +#define FEC_OC_FCT_OCCUPATION_OCCUPATION__B 0 +#define FEC_OC_FCT_OCCUPATION_OCCUPATION__W 12 +#define FEC_OC_FCT_OCCUPATION_OCCUPATION__M 0xFFF +#define FEC_OC_FCT_OCCUPATION_OCCUPATION__PRE 0x0 + +#define FEC_OC_TMD_MODE__A 0x244001E +#define FEC_OC_TMD_MODE__W 3 +#define FEC_OC_TMD_MODE__M 0x7 +#define FEC_OC_TMD_MODE__PRE 0x4 + +#define FEC_OC_TMD_MODE_MODE__B 0 +#define FEC_OC_TMD_MODE_MODE__W 3 +#define FEC_OC_TMD_MODE_MODE__M 0x7 +#define FEC_OC_TMD_MODE_MODE__PRE 0x4 + +#define FEC_OC_TMD_COUNT__A 0x244001F +#define FEC_OC_TMD_COUNT__W 10 +#define FEC_OC_TMD_COUNT__M 0x3FF +#define FEC_OC_TMD_COUNT__PRE 0x1F4 + +#define FEC_OC_TMD_COUNT_COUNT__B 0 +#define FEC_OC_TMD_COUNT_COUNT__W 10 +#define FEC_OC_TMD_COUNT_COUNT__M 0x3FF +#define FEC_OC_TMD_COUNT_COUNT__PRE 0x1F4 + +#define FEC_OC_TMD_HI_MARGIN__A 0x2440020 +#define FEC_OC_TMD_HI_MARGIN__W 11 +#define FEC_OC_TMD_HI_MARGIN__M 0x7FF +#define FEC_OC_TMD_HI_MARGIN__PRE 0x200 + +#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__B 0 +#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__W 11 +#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__M 0x7FF +#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__PRE 0x200 + +#define FEC_OC_TMD_LO_MARGIN__A 0x2440021 +#define FEC_OC_TMD_LO_MARGIN__W 11 +#define FEC_OC_TMD_LO_MARGIN__M 0x7FF +#define FEC_OC_TMD_LO_MARGIN__PRE 0x100 + +#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__B 0 +#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__W 11 +#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__M 0x7FF +#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__PRE 0x100 + +#define FEC_OC_TMD_CTL_UPD_RATE__A 0x2440022 +#define FEC_OC_TMD_CTL_UPD_RATE__W 4 +#define FEC_OC_TMD_CTL_UPD_RATE__M 0xF +#define FEC_OC_TMD_CTL_UPD_RATE__PRE 0x1 + +#define FEC_OC_TMD_CTL_UPD_RATE_RATE__B 0 +#define FEC_OC_TMD_CTL_UPD_RATE_RATE__W 4 +#define FEC_OC_TMD_CTL_UPD_RATE_RATE__M 0xF +#define FEC_OC_TMD_CTL_UPD_RATE_RATE__PRE 0x1 + +#define FEC_OC_TMD_INT_UPD_RATE__A 0x2440023 +#define FEC_OC_TMD_INT_UPD_RATE__W 4 +#define FEC_OC_TMD_INT_UPD_RATE__M 0xF +#define FEC_OC_TMD_INT_UPD_RATE__PRE 0x4 + +#define FEC_OC_TMD_INT_UPD_RATE_RATE__B 0 +#define FEC_OC_TMD_INT_UPD_RATE_RATE__W 4 +#define FEC_OC_TMD_INT_UPD_RATE_RATE__M 0xF +#define FEC_OC_TMD_INT_UPD_RATE_RATE__PRE 0x4 + +#define FEC_OC_AVR_PARM_A__A 0x2440026 +#define FEC_OC_AVR_PARM_A__W 4 +#define FEC_OC_AVR_PARM_A__M 0xF +#define FEC_OC_AVR_PARM_A__PRE 0x6 + +#define FEC_OC_AVR_PARM_A_PARM__B 0 +#define FEC_OC_AVR_PARM_A_PARM__W 4 +#define FEC_OC_AVR_PARM_A_PARM__M 0xF +#define FEC_OC_AVR_PARM_A_PARM__PRE 0x6 + +#define FEC_OC_AVR_PARM_B__A 0x2440027 +#define FEC_OC_AVR_PARM_B__W 4 +#define FEC_OC_AVR_PARM_B__M 0xF +#define FEC_OC_AVR_PARM_B__PRE 0x4 + +#define FEC_OC_AVR_PARM_B_PARM__B 0 +#define FEC_OC_AVR_PARM_B_PARM__W 4 +#define FEC_OC_AVR_PARM_B_PARM__M 0xF +#define FEC_OC_AVR_PARM_B_PARM__PRE 0x4 + +#define FEC_OC_AVR_AVG_LO__A 0x2440028 +#define FEC_OC_AVR_AVG_LO__W 16 +#define FEC_OC_AVR_AVG_LO__M 0xFFFF +#define FEC_OC_AVR_AVG_LO__PRE 0x0 + +#define FEC_OC_AVR_AVG_LO_AVG_LO__B 0 +#define FEC_OC_AVR_AVG_LO_AVG_LO__W 16 +#define FEC_OC_AVR_AVG_LO_AVG_LO__M 0xFFFF +#define FEC_OC_AVR_AVG_LO_AVG_LO__PRE 0x0 + +#define FEC_OC_AVR_AVG_HI__A 0x2440029 +#define FEC_OC_AVR_AVG_HI__W 6 +#define FEC_OC_AVR_AVG_HI__M 0x3F +#define FEC_OC_AVR_AVG_HI__PRE 0x0 + +#define FEC_OC_AVR_AVG_HI_AVG_HI__B 0 +#define FEC_OC_AVR_AVG_HI_AVG_HI__W 6 +#define FEC_OC_AVR_AVG_HI_AVG_HI__M 0x3F +#define FEC_OC_AVR_AVG_HI_AVG_HI__PRE 0x0 + +#define FEC_OC_RCN_MODE__A 0x244002C +#define FEC_OC_RCN_MODE__W 5 +#define FEC_OC_RCN_MODE__M 0x1F +#define FEC_OC_RCN_MODE__PRE 0x1F + +#define FEC_OC_RCN_MODE_MODE__B 0 +#define FEC_OC_RCN_MODE_MODE__W 5 +#define FEC_OC_RCN_MODE_MODE__M 0x1F +#define FEC_OC_RCN_MODE_MODE__PRE 0x1F + +#define FEC_OC_RCN_OCC_SETTLE__A 0x244002D +#define FEC_OC_RCN_OCC_SETTLE__W 11 +#define FEC_OC_RCN_OCC_SETTLE__M 0x7FF +#define FEC_OC_RCN_OCC_SETTLE__PRE 0x180 + +#define FEC_OC_RCN_OCC_SETTLE_LEVEL__B 0 +#define FEC_OC_RCN_OCC_SETTLE_LEVEL__W 11 +#define FEC_OC_RCN_OCC_SETTLE_LEVEL__M 0x7FF +#define FEC_OC_RCN_OCC_SETTLE_LEVEL__PRE 0x180 + +#define FEC_OC_RCN_GAIN__A 0x244002E +#define FEC_OC_RCN_GAIN__W 4 +#define FEC_OC_RCN_GAIN__M 0xF +#define FEC_OC_RCN_GAIN__PRE 0xC + +#define FEC_OC_RCN_GAIN_GAIN__B 0 +#define FEC_OC_RCN_GAIN_GAIN__W 4 +#define FEC_OC_RCN_GAIN_GAIN__M 0xF +#define FEC_OC_RCN_GAIN_GAIN__PRE 0xC + +#define FEC_OC_RCN_CTL_RATE_LO__A 0x2440030 +#define FEC_OC_RCN_CTL_RATE_LO__W 16 +#define FEC_OC_RCN_CTL_RATE_LO__M 0xFFFF +#define FEC_OC_RCN_CTL_RATE_LO__PRE 0x0 + +#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__B 0 +#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__W 16 +#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__M 0xFFFF +#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__PRE 0x0 + +#define FEC_OC_RCN_CTL_RATE_HI__A 0x2440031 +#define FEC_OC_RCN_CTL_RATE_HI__W 8 +#define FEC_OC_RCN_CTL_RATE_HI__M 0xFF +#define FEC_OC_RCN_CTL_RATE_HI__PRE 0xC0 + +#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__B 0 +#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__W 8 +#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__M 0xFF +#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__PRE 0xC0 + +#define FEC_OC_RCN_CTL_STEP_LO__A 0x2440032 +#define FEC_OC_RCN_CTL_STEP_LO__W 16 +#define FEC_OC_RCN_CTL_STEP_LO__M 0xFFFF +#define FEC_OC_RCN_CTL_STEP_LO__PRE 0x0 + +#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__B 0 +#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__W 16 +#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__M 0xFFFF +#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__PRE 0x0 + +#define FEC_OC_RCN_CTL_STEP_HI__A 0x2440033 +#define FEC_OC_RCN_CTL_STEP_HI__W 8 +#define FEC_OC_RCN_CTL_STEP_HI__M 0xFF +#define FEC_OC_RCN_CTL_STEP_HI__PRE 0x8 + +#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__B 0 +#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__W 8 +#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__M 0xFF +#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__PRE 0x8 + +#define FEC_OC_RCN_DTO_OFS_LO__A 0x2440034 +#define FEC_OC_RCN_DTO_OFS_LO__W 16 +#define FEC_OC_RCN_DTO_OFS_LO__M 0xFFFF +#define FEC_OC_RCN_DTO_OFS_LO__PRE 0x0 + +#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__B 0 +#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__W 16 +#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__M 0xFFFF +#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__PRE 0x0 + +#define FEC_OC_RCN_DTO_OFS_HI__A 0x2440035 +#define FEC_OC_RCN_DTO_OFS_HI__W 8 +#define FEC_OC_RCN_DTO_OFS_HI__M 0xFF +#define FEC_OC_RCN_DTO_OFS_HI__PRE 0x0 + +#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__B 0 +#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__W 8 +#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__M 0xFF +#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__PRE 0x0 + +#define FEC_OC_RCN_DTO_RATE_LO__A 0x2440036 +#define FEC_OC_RCN_DTO_RATE_LO__W 16 +#define FEC_OC_RCN_DTO_RATE_LO__M 0xFFFF +#define FEC_OC_RCN_DTO_RATE_LO__PRE 0x0 + +#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__B 0 +#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__W 16 +#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__M 0xFFFF +#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__PRE 0x0 + +#define FEC_OC_RCN_DTO_RATE_HI__A 0x2440037 +#define FEC_OC_RCN_DTO_RATE_HI__W 8 +#define FEC_OC_RCN_DTO_RATE_HI__M 0xFF +#define FEC_OC_RCN_DTO_RATE_HI__PRE 0x0 + +#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__B 0 +#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__W 8 +#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__M 0xFF +#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__PRE 0x0 + +#define FEC_OC_RCN_RATE_CLIP_LO__A 0x2440038 +#define FEC_OC_RCN_RATE_CLIP_LO__W 16 +#define FEC_OC_RCN_RATE_CLIP_LO__M 0xFFFF +#define FEC_OC_RCN_RATE_CLIP_LO__PRE 0x0 + +#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__B 0 +#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__W 16 +#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__M 0xFFFF +#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__PRE 0x0 + +#define FEC_OC_RCN_RATE_CLIP_HI__A 0x2440039 +#define FEC_OC_RCN_RATE_CLIP_HI__W 8 +#define FEC_OC_RCN_RATE_CLIP_HI__M 0xFF +#define FEC_OC_RCN_RATE_CLIP_HI__PRE 0xF0 + +#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__B 0 +#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__W 8 +#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__M 0xFF +#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__PRE 0xF0 + +#define FEC_OC_RCN_DYN_RATE_LO__A 0x244003A +#define FEC_OC_RCN_DYN_RATE_LO__W 16 +#define FEC_OC_RCN_DYN_RATE_LO__M 0xFFFF +#define FEC_OC_RCN_DYN_RATE_LO__PRE 0x0 + +#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__B 0 +#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__W 16 +#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__M 0xFFFF +#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__PRE 0x0 + +#define FEC_OC_RCN_DYN_RATE_HI__A 0x244003B +#define FEC_OC_RCN_DYN_RATE_HI__W 8 +#define FEC_OC_RCN_DYN_RATE_HI__M 0xFF +#define FEC_OC_RCN_DYN_RATE_HI__PRE 0x0 + +#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__B 0 +#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__W 8 +#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__M 0xFF +#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__PRE 0x0 + +#define FEC_OC_SNC_MODE__A 0x2440040 +#define FEC_OC_SNC_MODE__W 4 +#define FEC_OC_SNC_MODE__M 0xF +#define FEC_OC_SNC_MODE__PRE 0x0 + +#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__B 0 +#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__W 1 +#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__M 0x1 +#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__PRE 0x0 + +#define FEC_OC_SNC_MODE_ERROR_CTL__B 1 +#define FEC_OC_SNC_MODE_ERROR_CTL__W 2 +#define FEC_OC_SNC_MODE_ERROR_CTL__M 0x6 +#define FEC_OC_SNC_MODE_ERROR_CTL__PRE 0x0 + +#define FEC_OC_SNC_MODE_CORR_DISABLE__B 3 +#define FEC_OC_SNC_MODE_CORR_DISABLE__W 1 +#define FEC_OC_SNC_MODE_CORR_DISABLE__M 0x8 +#define FEC_OC_SNC_MODE_CORR_DISABLE__PRE 0x0 + +#define FEC_OC_SNC_LWM__A 0x2440041 +#define FEC_OC_SNC_LWM__W 4 +#define FEC_OC_SNC_LWM__M 0xF +#define FEC_OC_SNC_LWM__PRE 0x3 + +#define FEC_OC_SNC_LWM_MARK__B 0 +#define FEC_OC_SNC_LWM_MARK__W 4 +#define FEC_OC_SNC_LWM_MARK__M 0xF +#define FEC_OC_SNC_LWM_MARK__PRE 0x3 + +#define FEC_OC_SNC_HWM__A 0x2440042 +#define FEC_OC_SNC_HWM__W 4 +#define FEC_OC_SNC_HWM__M 0xF +#define FEC_OC_SNC_HWM__PRE 0x5 + +#define FEC_OC_SNC_HWM_MARK__B 0 +#define FEC_OC_SNC_HWM_MARK__W 4 +#define FEC_OC_SNC_HWM_MARK__M 0xF +#define FEC_OC_SNC_HWM_MARK__PRE 0x5 + +#define FEC_OC_SNC_UNLOCK__A 0x2440043 +#define FEC_OC_SNC_UNLOCK__W 1 +#define FEC_OC_SNC_UNLOCK__M 0x1 +#define FEC_OC_SNC_UNLOCK__PRE 0x0 + +#define FEC_OC_SNC_UNLOCK_RESTART__B 0 +#define FEC_OC_SNC_UNLOCK_RESTART__W 1 +#define FEC_OC_SNC_UNLOCK_RESTART__M 0x1 +#define FEC_OC_SNC_UNLOCK_RESTART__PRE 0x0 + +#define FEC_OC_SNC_LOCK_COUNT__A 0x2440044 +#define FEC_OC_SNC_LOCK_COUNT__W 12 +#define FEC_OC_SNC_LOCK_COUNT__M 0xFFF +#define FEC_OC_SNC_LOCK_COUNT__PRE 0x0 + +#define FEC_OC_SNC_LOCK_COUNT_COUNT__B 0 +#define FEC_OC_SNC_LOCK_COUNT_COUNT__W 12 +#define FEC_OC_SNC_LOCK_COUNT_COUNT__M 0xFFF +#define FEC_OC_SNC_LOCK_COUNT_COUNT__PRE 0x0 + +#define FEC_OC_SNC_FAIL_COUNT__A 0x2440045 +#define FEC_OC_SNC_FAIL_COUNT__W 12 +#define FEC_OC_SNC_FAIL_COUNT__M 0xFFF +#define FEC_OC_SNC_FAIL_COUNT__PRE 0x0 + +#define FEC_OC_SNC_FAIL_COUNT_COUNT__B 0 +#define FEC_OC_SNC_FAIL_COUNT_COUNT__W 12 +#define FEC_OC_SNC_FAIL_COUNT_COUNT__M 0xFFF +#define FEC_OC_SNC_FAIL_COUNT_COUNT__PRE 0x0 + +#define FEC_OC_SNC_FAIL_PERIOD__A 0x2440046 +#define FEC_OC_SNC_FAIL_PERIOD__W 16 +#define FEC_OC_SNC_FAIL_PERIOD__M 0xFFFF +#define FEC_OC_SNC_FAIL_PERIOD__PRE 0x1171 + +#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__B 0 +#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__W 16 +#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__M 0xFFFF +#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__PRE 0x1171 + +#define FEC_OC_EMS_MODE__A 0x2440047 +#define FEC_OC_EMS_MODE__W 2 +#define FEC_OC_EMS_MODE__M 0x3 +#define FEC_OC_EMS_MODE__PRE 0x0 + +#define FEC_OC_EMS_MODE_MODE__B 0 +#define FEC_OC_EMS_MODE_MODE__W 2 +#define FEC_OC_EMS_MODE_MODE__M 0x3 +#define FEC_OC_EMS_MODE_MODE__PRE 0x0 + +#define FEC_OC_IPR_MODE__A 0x2440048 +#define FEC_OC_IPR_MODE__W 12 +#define FEC_OC_IPR_MODE__M 0xFFF +#define FEC_OC_IPR_MODE__PRE 0x0 + +#define FEC_OC_IPR_MODE_SERIAL__B 0 +#define FEC_OC_IPR_MODE_SERIAL__W 1 +#define FEC_OC_IPR_MODE_SERIAL__M 0x1 +#define FEC_OC_IPR_MODE_SERIAL__PRE 0x0 + +#define FEC_OC_IPR_MODE_REVERSE_ORDER__B 1 +#define FEC_OC_IPR_MODE_REVERSE_ORDER__W 1 +#define FEC_OC_IPR_MODE_REVERSE_ORDER__M 0x2 +#define FEC_OC_IPR_MODE_REVERSE_ORDER__PRE 0x0 + +#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__B 2 +#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__W 1 +#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M 0x4 +#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__PRE 0x0 + +#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__B 3 +#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__W 1 +#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__M 0x8 +#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__B 4 +#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__W 1 +#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__M 0x10 +#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MERR_DIS_PAR__B 5 +#define FEC_OC_IPR_MODE_MERR_DIS_PAR__W 1 +#define FEC_OC_IPR_MODE_MERR_DIS_PAR__M 0x20 +#define FEC_OC_IPR_MODE_MERR_DIS_PAR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MD_DIS_PAR__B 6 +#define FEC_OC_IPR_MODE_MD_DIS_PAR__W 1 +#define FEC_OC_IPR_MODE_MD_DIS_PAR__M 0x40 +#define FEC_OC_IPR_MODE_MD_DIS_PAR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__B 7 +#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__W 1 +#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__M 0x80 +#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__B 8 +#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__W 1 +#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__M 0x100 +#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MERR_DIS_ERR__B 9 +#define FEC_OC_IPR_MODE_MERR_DIS_ERR__W 1 +#define FEC_OC_IPR_MODE_MERR_DIS_ERR__M 0x200 +#define FEC_OC_IPR_MODE_MERR_DIS_ERR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MD_DIS_ERR__B 10 +#define FEC_OC_IPR_MODE_MD_DIS_ERR__W 1 +#define FEC_OC_IPR_MODE_MD_DIS_ERR__M 0x400 +#define FEC_OC_IPR_MODE_MD_DIS_ERR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__B 11 +#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__W 1 +#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__M 0x800 +#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__PRE 0x0 + +#define FEC_OC_IPR_INVERT__A 0x2440049 +#define FEC_OC_IPR_INVERT__W 12 +#define FEC_OC_IPR_INVERT__M 0xFFF +#define FEC_OC_IPR_INVERT__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD0__B 0 +#define FEC_OC_IPR_INVERT_MD0__W 1 +#define FEC_OC_IPR_INVERT_MD0__M 0x1 +#define FEC_OC_IPR_INVERT_MD0__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD1__B 1 +#define FEC_OC_IPR_INVERT_MD1__W 1 +#define FEC_OC_IPR_INVERT_MD1__M 0x2 +#define FEC_OC_IPR_INVERT_MD1__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD2__B 2 +#define FEC_OC_IPR_INVERT_MD2__W 1 +#define FEC_OC_IPR_INVERT_MD2__M 0x4 +#define FEC_OC_IPR_INVERT_MD2__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD3__B 3 +#define FEC_OC_IPR_INVERT_MD3__W 1 +#define FEC_OC_IPR_INVERT_MD3__M 0x8 +#define FEC_OC_IPR_INVERT_MD3__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD4__B 4 +#define FEC_OC_IPR_INVERT_MD4__W 1 +#define FEC_OC_IPR_INVERT_MD4__M 0x10 +#define FEC_OC_IPR_INVERT_MD4__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD5__B 5 +#define FEC_OC_IPR_INVERT_MD5__W 1 +#define FEC_OC_IPR_INVERT_MD5__M 0x20 +#define FEC_OC_IPR_INVERT_MD5__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD6__B 6 +#define FEC_OC_IPR_INVERT_MD6__W 1 +#define FEC_OC_IPR_INVERT_MD6__M 0x40 +#define FEC_OC_IPR_INVERT_MD6__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD7__B 7 +#define FEC_OC_IPR_INVERT_MD7__W 1 +#define FEC_OC_IPR_INVERT_MD7__M 0x80 +#define FEC_OC_IPR_INVERT_MD7__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MERR__B 8 +#define FEC_OC_IPR_INVERT_MERR__W 1 +#define FEC_OC_IPR_INVERT_MERR__M 0x100 +#define FEC_OC_IPR_INVERT_MERR__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MSTRT__B 9 +#define FEC_OC_IPR_INVERT_MSTRT__W 1 +#define FEC_OC_IPR_INVERT_MSTRT__M 0x200 +#define FEC_OC_IPR_INVERT_MSTRT__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MVAL__B 10 +#define FEC_OC_IPR_INVERT_MVAL__W 1 +#define FEC_OC_IPR_INVERT_MVAL__M 0x400 +#define FEC_OC_IPR_INVERT_MVAL__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MCLK__B 11 +#define FEC_OC_IPR_INVERT_MCLK__W 1 +#define FEC_OC_IPR_INVERT_MCLK__M 0x800 +#define FEC_OC_IPR_INVERT_MCLK__PRE 0x0 + +#define FEC_OC_OCR_MODE__A 0x2440050 +#define FEC_OC_OCR_MODE__W 4 +#define FEC_OC_OCR_MODE__M 0xF +#define FEC_OC_OCR_MODE__PRE 0x0 + +#define FEC_OC_OCR_MODE_MB_SELECT__B 0 +#define FEC_OC_OCR_MODE_MB_SELECT__W 1 +#define FEC_OC_OCR_MODE_MB_SELECT__M 0x1 +#define FEC_OC_OCR_MODE_MB_SELECT__PRE 0x0 + +#define FEC_OC_OCR_MODE_GRAB_ENABLE__B 1 +#define FEC_OC_OCR_MODE_GRAB_ENABLE__W 1 +#define FEC_OC_OCR_MODE_GRAB_ENABLE__M 0x2 +#define FEC_OC_OCR_MODE_GRAB_ENABLE__PRE 0x0 + +#define FEC_OC_OCR_MODE_GRAB_SELECT__B 2 +#define FEC_OC_OCR_MODE_GRAB_SELECT__W 1 +#define FEC_OC_OCR_MODE_GRAB_SELECT__M 0x4 +#define FEC_OC_OCR_MODE_GRAB_SELECT__PRE 0x0 + +#define FEC_OC_OCR_MODE_GRAB_COUNTED__B 3 +#define FEC_OC_OCR_MODE_GRAB_COUNTED__W 1 +#define FEC_OC_OCR_MODE_GRAB_COUNTED__M 0x8 +#define FEC_OC_OCR_MODE_GRAB_COUNTED__PRE 0x0 + +#define FEC_OC_OCR_RATE__A 0x2440051 +#define FEC_OC_OCR_RATE__W 4 +#define FEC_OC_OCR_RATE__M 0xF +#define FEC_OC_OCR_RATE__PRE 0x0 + +#define FEC_OC_OCR_RATE_RATE__B 0 +#define FEC_OC_OCR_RATE_RATE__W 4 +#define FEC_OC_OCR_RATE_RATE__M 0xF +#define FEC_OC_OCR_RATE_RATE__PRE 0x0 + +#define FEC_OC_OCR_INVERT__A 0x2440052 +#define FEC_OC_OCR_INVERT__W 12 +#define FEC_OC_OCR_INVERT__M 0xFFF +#define FEC_OC_OCR_INVERT__PRE 0x800 + +#define FEC_OC_OCR_INVERT_INVERT__B 0 +#define FEC_OC_OCR_INVERT_INVERT__W 12 +#define FEC_OC_OCR_INVERT_INVERT__M 0xFFF +#define FEC_OC_OCR_INVERT_INVERT__PRE 0x800 + +#define FEC_OC_OCR_GRAB_COUNT__A 0x2440053 +#define FEC_OC_OCR_GRAB_COUNT__W 16 +#define FEC_OC_OCR_GRAB_COUNT__M 0xFFFF +#define FEC_OC_OCR_GRAB_COUNT__PRE 0x0 + +#define FEC_OC_OCR_GRAB_COUNT_COUNT__B 0 +#define FEC_OC_OCR_GRAB_COUNT_COUNT__W 16 +#define FEC_OC_OCR_GRAB_COUNT_COUNT__M 0xFFFF +#define FEC_OC_OCR_GRAB_COUNT_COUNT__PRE 0x0 + +#define FEC_OC_OCR_GRAB_SYNC__A 0x2440054 +#define FEC_OC_OCR_GRAB_SYNC__W 8 +#define FEC_OC_OCR_GRAB_SYNC__M 0xFF +#define FEC_OC_OCR_GRAB_SYNC__PRE 0x0 + +#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__B 0 +#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__W 3 +#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__M 0x7 +#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__PRE 0x0 + +#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__B 3 +#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__W 4 +#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__M 0x78 +#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__PRE 0x0 + +#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__B 7 +#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__W 1 +#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__M 0x80 +#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD0__A 0x2440055 +#define FEC_OC_OCR_GRAB_RD0__W 10 +#define FEC_OC_OCR_GRAB_RD0__M 0x3FF +#define FEC_OC_OCR_GRAB_RD0__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD0_DATA__B 0 +#define FEC_OC_OCR_GRAB_RD0_DATA__W 10 +#define FEC_OC_OCR_GRAB_RD0_DATA__M 0x3FF +#define FEC_OC_OCR_GRAB_RD0_DATA__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD1__A 0x2440056 +#define FEC_OC_OCR_GRAB_RD1__W 10 +#define FEC_OC_OCR_GRAB_RD1__M 0x3FF +#define FEC_OC_OCR_GRAB_RD1__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD1_DATA__B 0 +#define FEC_OC_OCR_GRAB_RD1_DATA__W 10 +#define FEC_OC_OCR_GRAB_RD1_DATA__M 0x3FF +#define FEC_OC_OCR_GRAB_RD1_DATA__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD2__A 0x2440057 +#define FEC_OC_OCR_GRAB_RD2__W 10 +#define FEC_OC_OCR_GRAB_RD2__M 0x3FF +#define FEC_OC_OCR_GRAB_RD2__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD2_DATA__B 0 +#define FEC_OC_OCR_GRAB_RD2_DATA__W 10 +#define FEC_OC_OCR_GRAB_RD2_DATA__M 0x3FF +#define FEC_OC_OCR_GRAB_RD2_DATA__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD3__A 0x2440058 +#define FEC_OC_OCR_GRAB_RD3__W 10 +#define FEC_OC_OCR_GRAB_RD3__M 0x3FF +#define FEC_OC_OCR_GRAB_RD3__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD3_DATA__B 0 +#define FEC_OC_OCR_GRAB_RD3_DATA__W 10 +#define FEC_OC_OCR_GRAB_RD3_DATA__M 0x3FF +#define FEC_OC_OCR_GRAB_RD3_DATA__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD4__A 0x2440059 +#define FEC_OC_OCR_GRAB_RD4__W 10 +#define FEC_OC_OCR_GRAB_RD4__M 0x3FF +#define FEC_OC_OCR_GRAB_RD4__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD4_DATA__B 0 +#define FEC_OC_OCR_GRAB_RD4_DATA__W 10 +#define FEC_OC_OCR_GRAB_RD4_DATA__M 0x3FF +#define FEC_OC_OCR_GRAB_RD4_DATA__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD5__A 0x244005A +#define FEC_OC_OCR_GRAB_RD5__W 10 +#define FEC_OC_OCR_GRAB_RD5__M 0x3FF +#define FEC_OC_OCR_GRAB_RD5__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD5_DATA__B 0 +#define FEC_OC_OCR_GRAB_RD5_DATA__W 10 +#define FEC_OC_OCR_GRAB_RD5_DATA__M 0x3FF +#define FEC_OC_OCR_GRAB_RD5_DATA__PRE 0x0 + + + +#define FEC_DI_RAM__A 0x2450000 + + + +#define FEC_RS_RAM__A 0x2460000 + + + +#define FEC_OC_RAM__A 0x2470000 + + + + + +#define IQM_COMM_EXEC__A 0x1800000 +#define IQM_COMM_EXEC__W 2 +#define IQM_COMM_EXEC__M 0x3 +#define IQM_COMM_EXEC__PRE 0x0 +#define IQM_COMM_EXEC_STOP 0x0 +#define IQM_COMM_EXEC_ACTIVE 0x1 +#define IQM_COMM_EXEC_HOLD 0x2 + +#define IQM_COMM_MB__A 0x1800002 +#define IQM_COMM_MB__W 16 +#define IQM_COMM_MB__M 0xFFFF +#define IQM_COMM_MB__PRE 0x0 +#define IQM_COMM_INT_REQ__A 0x1800003 +#define IQM_COMM_INT_REQ__W 2 +#define IQM_COMM_INT_REQ__M 0x3 +#define IQM_COMM_INT_REQ__PRE 0x0 + +#define IQM_COMM_INT_REQ_AF_REQ__B 0 +#define IQM_COMM_INT_REQ_AF_REQ__W 1 +#define IQM_COMM_INT_REQ_AF_REQ__M 0x1 +#define IQM_COMM_INT_REQ_AF_REQ__PRE 0x0 + +#define IQM_COMM_INT_REQ_CF_REQ__B 1 +#define IQM_COMM_INT_REQ_CF_REQ__W 1 +#define IQM_COMM_INT_REQ_CF_REQ__M 0x2 +#define IQM_COMM_INT_REQ_CF_REQ__PRE 0x0 + +#define IQM_COMM_INT_STA__A 0x1800005 +#define IQM_COMM_INT_STA__W 16 +#define IQM_COMM_INT_STA__M 0xFFFF +#define IQM_COMM_INT_STA__PRE 0x0 +#define IQM_COMM_INT_MSK__A 0x1800006 +#define IQM_COMM_INT_MSK__W 16 +#define IQM_COMM_INT_MSK__M 0xFFFF +#define IQM_COMM_INT_MSK__PRE 0x0 +#define IQM_COMM_INT_STM__A 0x1800007 +#define IQM_COMM_INT_STM__W 16 +#define IQM_COMM_INT_STM__M 0xFFFF +#define IQM_COMM_INT_STM__PRE 0x0 + + + +#define IQM_FS_COMM_EXEC__A 0x1820000 +#define IQM_FS_COMM_EXEC__W 2 +#define IQM_FS_COMM_EXEC__M 0x3 +#define IQM_FS_COMM_EXEC__PRE 0x0 +#define IQM_FS_COMM_EXEC_STOP 0x0 +#define IQM_FS_COMM_EXEC_ACTIVE 0x1 +#define IQM_FS_COMM_EXEC_HOLD 0x2 + +#define IQM_FS_COMM_MB__A 0x1820002 +#define IQM_FS_COMM_MB__W 2 +#define IQM_FS_COMM_MB__M 0x3 +#define IQM_FS_COMM_MB__PRE 0x0 +#define IQM_FS_COMM_MB_CTL__B 0 +#define IQM_FS_COMM_MB_CTL__W 1 +#define IQM_FS_COMM_MB_CTL__M 0x1 +#define IQM_FS_COMM_MB_CTL__PRE 0x0 +#define IQM_FS_COMM_MB_CTL_CTL_OFF 0x0 +#define IQM_FS_COMM_MB_CTL_CTL_ON 0x1 +#define IQM_FS_COMM_MB_OBS__B 1 +#define IQM_FS_COMM_MB_OBS__W 1 +#define IQM_FS_COMM_MB_OBS__M 0x2 +#define IQM_FS_COMM_MB_OBS__PRE 0x0 +#define IQM_FS_COMM_MB_OBS_OBS_OFF 0x0 +#define IQM_FS_COMM_MB_OBS_OBS_ON 0x2 + +#define IQM_FS_RATE_OFS_LO__A 0x1820010 +#define IQM_FS_RATE_OFS_LO__W 16 +#define IQM_FS_RATE_OFS_LO__M 0xFFFF +#define IQM_FS_RATE_OFS_LO__PRE 0x0 +#define IQM_FS_RATE_OFS_HI__A 0x1820011 +#define IQM_FS_RATE_OFS_HI__W 12 +#define IQM_FS_RATE_OFS_HI__M 0xFFF +#define IQM_FS_RATE_OFS_HI__PRE 0x0 +#define IQM_FS_RATE_LO__A 0x1820012 +#define IQM_FS_RATE_LO__W 16 +#define IQM_FS_RATE_LO__M 0xFFFF +#define IQM_FS_RATE_LO__PRE 0x0 +#define IQM_FS_RATE_HI__A 0x1820013 +#define IQM_FS_RATE_HI__W 12 +#define IQM_FS_RATE_HI__M 0xFFF +#define IQM_FS_RATE_HI__PRE 0x0 + +#define IQM_FS_ADJ_SEL__A 0x1820014 +#define IQM_FS_ADJ_SEL__W 2 +#define IQM_FS_ADJ_SEL__M 0x3 +#define IQM_FS_ADJ_SEL__PRE 0x0 +#define IQM_FS_ADJ_SEL_OFF 0x0 +#define IQM_FS_ADJ_SEL_QAM 0x1 +#define IQM_FS_ADJ_SEL_VSB 0x2 + + + +#define IQM_FD_COMM_EXEC__A 0x1830000 +#define IQM_FD_COMM_EXEC__W 2 +#define IQM_FD_COMM_EXEC__M 0x3 +#define IQM_FD_COMM_EXEC__PRE 0x0 +#define IQM_FD_COMM_EXEC_STOP 0x0 +#define IQM_FD_COMM_EXEC_ACTIVE 0x1 +#define IQM_FD_COMM_EXEC_HOLD 0x2 + +#define IQM_FD_COMM_MB__A 0x1830002 +#define IQM_FD_COMM_MB__W 2 +#define IQM_FD_COMM_MB__M 0x3 +#define IQM_FD_COMM_MB__PRE 0x0 +#define IQM_FD_COMM_MB_CTL__B 0 +#define IQM_FD_COMM_MB_CTL__W 1 +#define IQM_FD_COMM_MB_CTL__M 0x1 +#define IQM_FD_COMM_MB_CTL__PRE 0x0 +#define IQM_FD_COMM_MB_CTL_CTL_OFF 0x0 +#define IQM_FD_COMM_MB_CTL_CTL_ON 0x1 +#define IQM_FD_COMM_MB_OBS__B 1 +#define IQM_FD_COMM_MB_OBS__W 1 +#define IQM_FD_COMM_MB_OBS__M 0x2 +#define IQM_FD_COMM_MB_OBS__PRE 0x0 +#define IQM_FD_COMM_MB_OBS_OBS_OFF 0x0 +#define IQM_FD_COMM_MB_OBS_OBS_ON 0x2 + + + +#define IQM_RC_COMM_EXEC__A 0x1840000 +#define IQM_RC_COMM_EXEC__W 2 +#define IQM_RC_COMM_EXEC__M 0x3 +#define IQM_RC_COMM_EXEC__PRE 0x0 +#define IQM_RC_COMM_EXEC_STOP 0x0 +#define IQM_RC_COMM_EXEC_ACTIVE 0x1 +#define IQM_RC_COMM_EXEC_HOLD 0x2 + +#define IQM_RC_COMM_MB__A 0x1840002 +#define IQM_RC_COMM_MB__W 2 +#define IQM_RC_COMM_MB__M 0x3 +#define IQM_RC_COMM_MB__PRE 0x0 +#define IQM_RC_COMM_MB_CTL__B 0 +#define IQM_RC_COMM_MB_CTL__W 1 +#define IQM_RC_COMM_MB_CTL__M 0x1 +#define IQM_RC_COMM_MB_CTL__PRE 0x0 +#define IQM_RC_COMM_MB_CTL_CTL_OFF 0x0 +#define IQM_RC_COMM_MB_CTL_CTL_ON 0x1 +#define IQM_RC_COMM_MB_OBS__B 1 +#define IQM_RC_COMM_MB_OBS__W 1 +#define IQM_RC_COMM_MB_OBS__M 0x2 +#define IQM_RC_COMM_MB_OBS__PRE 0x0 +#define IQM_RC_COMM_MB_OBS_OBS_OFF 0x0 +#define IQM_RC_COMM_MB_OBS_OBS_ON 0x2 + +#define IQM_RC_RATE_OFS_LO__A 0x1840010 +#define IQM_RC_RATE_OFS_LO__W 16 +#define IQM_RC_RATE_OFS_LO__M 0xFFFF +#define IQM_RC_RATE_OFS_LO__PRE 0x0 +#define IQM_RC_RATE_OFS_HI__A 0x1840011 +#define IQM_RC_RATE_OFS_HI__W 8 +#define IQM_RC_RATE_OFS_HI__M 0xFF +#define IQM_RC_RATE_OFS_HI__PRE 0x0 +#define IQM_RC_RATE_LO__A 0x1840012 +#define IQM_RC_RATE_LO__W 16 +#define IQM_RC_RATE_LO__M 0xFFFF +#define IQM_RC_RATE_LO__PRE 0x0 +#define IQM_RC_RATE_HI__A 0x1840013 +#define IQM_RC_RATE_HI__W 8 +#define IQM_RC_RATE_HI__M 0xFF +#define IQM_RC_RATE_HI__PRE 0x0 + +#define IQM_RC_ADJ_SEL__A 0x1840014 +#define IQM_RC_ADJ_SEL__W 2 +#define IQM_RC_ADJ_SEL__M 0x3 +#define IQM_RC_ADJ_SEL__PRE 0x0 +#define IQM_RC_ADJ_SEL_OFF 0x0 +#define IQM_RC_ADJ_SEL_QAM 0x1 +#define IQM_RC_ADJ_SEL_VSB 0x2 + +#define IQM_RC_CROUT_ENA__A 0x1840015 +#define IQM_RC_CROUT_ENA__W 1 +#define IQM_RC_CROUT_ENA__M 0x1 +#define IQM_RC_CROUT_ENA__PRE 0x0 + +#define IQM_RC_CROUT_ENA_ENA__B 0 +#define IQM_RC_CROUT_ENA_ENA__W 1 +#define IQM_RC_CROUT_ENA_ENA__M 0x1 +#define IQM_RC_CROUT_ENA_ENA__PRE 0x0 + + +#define IQM_RC_STRETCH__A 0x1840016 +#define IQM_RC_STRETCH__W 5 +#define IQM_RC_STRETCH__M 0x1F +#define IQM_RC_STRETCH__PRE 0x0 +#define IQM_RC_STRETCH_QAM_B_64 0x1E +#define IQM_RC_STRETCH_QAM_B_256 0x1C +#define IQM_RC_STRETCH_ATV 0xF + + + +#define IQM_RT_COMM_EXEC__A 0x1850000 +#define IQM_RT_COMM_EXEC__W 2 +#define IQM_RT_COMM_EXEC__M 0x3 +#define IQM_RT_COMM_EXEC__PRE 0x0 +#define IQM_RT_COMM_EXEC_STOP 0x0 +#define IQM_RT_COMM_EXEC_ACTIVE 0x1 +#define IQM_RT_COMM_EXEC_HOLD 0x2 + +#define IQM_RT_COMM_MB__A 0x1850002 +#define IQM_RT_COMM_MB__W 2 +#define IQM_RT_COMM_MB__M 0x3 +#define IQM_RT_COMM_MB__PRE 0x0 +#define IQM_RT_COMM_MB_CTL__B 0 +#define IQM_RT_COMM_MB_CTL__W 1 +#define IQM_RT_COMM_MB_CTL__M 0x1 +#define IQM_RT_COMM_MB_CTL__PRE 0x0 +#define IQM_RT_COMM_MB_CTL_CTL_OFF 0x0 +#define IQM_RT_COMM_MB_CTL_CTL_ON 0x1 +#define IQM_RT_COMM_MB_OBS__B 1 +#define IQM_RT_COMM_MB_OBS__W 1 +#define IQM_RT_COMM_MB_OBS__M 0x2 +#define IQM_RT_COMM_MB_OBS__PRE 0x0 +#define IQM_RT_COMM_MB_OBS_OBS_OFF 0x0 +#define IQM_RT_COMM_MB_OBS_OBS_ON 0x2 + +#define IQM_RT_ACTIVE__A 0x1850010 +#define IQM_RT_ACTIVE__W 2 +#define IQM_RT_ACTIVE__M 0x3 +#define IQM_RT_ACTIVE__PRE 0x0 + +#define IQM_RT_ACTIVE_ACTIVE_RT__B 0 +#define IQM_RT_ACTIVE_ACTIVE_RT__W 1 +#define IQM_RT_ACTIVE_ACTIVE_RT__M 0x1 +#define IQM_RT_ACTIVE_ACTIVE_RT__PRE 0x0 +#define IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_OFF 0x0 +#define IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_ON 0x1 + +#define IQM_RT_ACTIVE_ACTIVE_CR__B 1 +#define IQM_RT_ACTIVE_ACTIVE_CR__W 1 +#define IQM_RT_ACTIVE_ACTIVE_CR__M 0x2 +#define IQM_RT_ACTIVE_ACTIVE_CR__PRE 0x0 +#define IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_OFF 0x0 +#define IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_ON 0x2 + + +#define IQM_RT_LO_INCR__A 0x1850011 +#define IQM_RT_LO_INCR__W 12 +#define IQM_RT_LO_INCR__M 0xFFF +#define IQM_RT_LO_INCR__PRE 0x588 +#define IQM_RT_LO_INCR_FM 0x0 +#define IQM_RT_LO_INCR_MN 0x588 + +#define IQM_RT_ROT_BP__A 0x1850012 +#define IQM_RT_ROT_BP__W 2 +#define IQM_RT_ROT_BP__M 0x3 +#define IQM_RT_ROT_BP__PRE 0x0 + +#define IQM_RT_ROT_BP_ROT_OFF__B 0 +#define IQM_RT_ROT_BP_ROT_OFF__W 1 +#define IQM_RT_ROT_BP_ROT_OFF__M 0x1 +#define IQM_RT_ROT_BP_ROT_OFF__PRE 0x0 +#define IQM_RT_ROT_BP_ROT_OFF_ACTIVE 0x0 +#define IQM_RT_ROT_BP_ROT_OFF_OFF 0x1 + +#define IQM_RT_ROT_BP_ROT_BPF__B 1 +#define IQM_RT_ROT_BP_ROT_BPF__W 1 +#define IQM_RT_ROT_BP_ROT_BPF__M 0x2 +#define IQM_RT_ROT_BP_ROT_BPF__PRE 0x0 + + +#define IQM_RT_LP_BP__A 0x1850013 +#define IQM_RT_LP_BP__W 1 +#define IQM_RT_LP_BP__M 0x1 +#define IQM_RT_LP_BP__PRE 0x0 + +#define IQM_RT_DELAY__A 0x1850014 +#define IQM_RT_DELAY__W 7 +#define IQM_RT_DELAY__M 0x7F +#define IQM_RT_DELAY__PRE 0x45 + + + +#define IQM_CF_COMM_EXEC__A 0x1860000 +#define IQM_CF_COMM_EXEC__W 2 +#define IQM_CF_COMM_EXEC__M 0x3 +#define IQM_CF_COMM_EXEC__PRE 0x0 +#define IQM_CF_COMM_EXEC_STOP 0x0 +#define IQM_CF_COMM_EXEC_ACTIVE 0x1 +#define IQM_CF_COMM_EXEC_HOLD 0x2 + +#define IQM_CF_COMM_MB__A 0x1860002 +#define IQM_CF_COMM_MB__W 2 +#define IQM_CF_COMM_MB__M 0x3 +#define IQM_CF_COMM_MB__PRE 0x0 +#define IQM_CF_COMM_MB_CTL__B 0 +#define IQM_CF_COMM_MB_CTL__W 1 +#define IQM_CF_COMM_MB_CTL__M 0x1 +#define IQM_CF_COMM_MB_CTL__PRE 0x0 +#define IQM_CF_COMM_MB_CTL_CTL_OFF 0x0 +#define IQM_CF_COMM_MB_CTL_CTL_ON 0x1 +#define IQM_CF_COMM_MB_OBS__B 1 +#define IQM_CF_COMM_MB_OBS__W 1 +#define IQM_CF_COMM_MB_OBS__M 0x2 +#define IQM_CF_COMM_MB_OBS__PRE 0x0 +#define IQM_CF_COMM_MB_OBS_OBS_OFF 0x0 +#define IQM_CF_COMM_MB_OBS_OBS_ON 0x2 + +#define IQM_CF_COMM_INT_REQ__A 0x1860003 +#define IQM_CF_COMM_INT_REQ__W 1 +#define IQM_CF_COMM_INT_REQ__M 0x1 +#define IQM_CF_COMM_INT_REQ__PRE 0x0 +#define IQM_CF_COMM_INT_STA__A 0x1860005 +#define IQM_CF_COMM_INT_STA__W 1 +#define IQM_CF_COMM_INT_STA__M 0x1 +#define IQM_CF_COMM_INT_STA__PRE 0x0 +#define IQM_CF_COMM_INT_STA_PM__B 0 +#define IQM_CF_COMM_INT_STA_PM__W 1 +#define IQM_CF_COMM_INT_STA_PM__M 0x1 +#define IQM_CF_COMM_INT_STA_PM__PRE 0x0 + +#define IQM_CF_COMM_INT_MSK__A 0x1860006 +#define IQM_CF_COMM_INT_MSK__W 1 +#define IQM_CF_COMM_INT_MSK__M 0x1 +#define IQM_CF_COMM_INT_MSK__PRE 0x0 +#define IQM_CF_COMM_INT_MSK_PM__B 0 +#define IQM_CF_COMM_INT_MSK_PM__W 1 +#define IQM_CF_COMM_INT_MSK_PM__M 0x1 +#define IQM_CF_COMM_INT_MSK_PM__PRE 0x0 + +#define IQM_CF_COMM_INT_STM__A 0x1860007 +#define IQM_CF_COMM_INT_STM__W 1 +#define IQM_CF_COMM_INT_STM__M 0x1 +#define IQM_CF_COMM_INT_STM__PRE 0x0 +#define IQM_CF_COMM_INT_STM_PM__B 0 +#define IQM_CF_COMM_INT_STM_PM__W 1 +#define IQM_CF_COMM_INT_STM_PM__M 0x1 +#define IQM_CF_COMM_INT_STM_PM__PRE 0x0 + +#define IQM_CF_SYMMETRIC__A 0x1860010 +#define IQM_CF_SYMMETRIC__W 2 +#define IQM_CF_SYMMETRIC__M 0x3 +#define IQM_CF_SYMMETRIC__PRE 0x0 + +#define IQM_CF_SYMMETRIC_RE__B 0 +#define IQM_CF_SYMMETRIC_RE__W 1 +#define IQM_CF_SYMMETRIC_RE__M 0x1 +#define IQM_CF_SYMMETRIC_RE__PRE 0x0 + +#define IQM_CF_SYMMETRIC_IM__B 1 +#define IQM_CF_SYMMETRIC_IM__W 1 +#define IQM_CF_SYMMETRIC_IM__M 0x2 +#define IQM_CF_SYMMETRIC_IM__PRE 0x0 + +#define IQM_CF_MIDTAP__A 0x1860011 +#define IQM_CF_MIDTAP__W 2 +#define IQM_CF_MIDTAP__M 0x3 +#define IQM_CF_MIDTAP__PRE 0x3 + +#define IQM_CF_MIDTAP_RE__B 0 +#define IQM_CF_MIDTAP_RE__W 1 +#define IQM_CF_MIDTAP_RE__M 0x1 +#define IQM_CF_MIDTAP_RE__PRE 0x1 + +#define IQM_CF_MIDTAP_IM__B 1 +#define IQM_CF_MIDTAP_IM__W 1 +#define IQM_CF_MIDTAP_IM__M 0x2 +#define IQM_CF_MIDTAP_IM__PRE 0x2 + +#define IQM_CF_OUT_ENA__A 0x1860012 +#define IQM_CF_OUT_ENA__W 3 +#define IQM_CF_OUT_ENA__M 0x7 +#define IQM_CF_OUT_ENA__PRE 0x0 + +#define IQM_CF_OUT_ENA_ATV__B 0 +#define IQM_CF_OUT_ENA_ATV__W 1 +#define IQM_CF_OUT_ENA_ATV__M 0x1 +#define IQM_CF_OUT_ENA_ATV__PRE 0x0 + +#define IQM_CF_OUT_ENA_QAM__B 1 +#define IQM_CF_OUT_ENA_QAM__W 1 +#define IQM_CF_OUT_ENA_QAM__M 0x2 +#define IQM_CF_OUT_ENA_QAM__PRE 0x0 + +#define IQM_CF_OUT_ENA_VSB__B 2 +#define IQM_CF_OUT_ENA_VSB__W 1 +#define IQM_CF_OUT_ENA_VSB__M 0x4 +#define IQM_CF_OUT_ENA_VSB__PRE 0x0 + + +#define IQM_CF_ADJ_SEL__A 0x1860013 +#define IQM_CF_ADJ_SEL__W 2 +#define IQM_CF_ADJ_SEL__M 0x3 +#define IQM_CF_ADJ_SEL__PRE 0x0 +#define IQM_CF_SCALE__A 0x1860014 +#define IQM_CF_SCALE__W 14 +#define IQM_CF_SCALE__M 0x3FFF +#define IQM_CF_SCALE__PRE 0x400 + +#define IQM_CF_SCALE_SH__A 0x1860015 +#define IQM_CF_SCALE_SH__W 2 +#define IQM_CF_SCALE_SH__M 0x3 +#define IQM_CF_SCALE_SH__PRE 0x0 + +#define IQM_CF_AMP__A 0x1860016 +#define IQM_CF_AMP__W 14 +#define IQM_CF_AMP__M 0x3FFF +#define IQM_CF_AMP__PRE 0x0 + +#define IQM_CF_POW_MEAS_LEN__A 0x1860017 +#define IQM_CF_POW_MEAS_LEN__W 3 +#define IQM_CF_POW_MEAS_LEN__M 0x7 +#define IQM_CF_POW_MEAS_LEN__PRE 0x2 +#define IQM_CF_POW_MEAS_LEN_QAM_B_64 0x1 +#define IQM_CF_POW_MEAS_LEN_QAM_B_256 0x1 + +#define IQM_CF_POW__A 0x1860018 +#define IQM_CF_POW__W 16 +#define IQM_CF_POW__M 0xFFFF +#define IQM_CF_POW__PRE 0x2 +#define IQM_CF_TAP_RE0__A 0x1860020 +#define IQM_CF_TAP_RE0__W 7 +#define IQM_CF_TAP_RE0__M 0x7F +#define IQM_CF_TAP_RE0__PRE 0x2 +#define IQM_CF_TAP_RE1__A 0x1860021 +#define IQM_CF_TAP_RE1__W 7 +#define IQM_CF_TAP_RE1__M 0x7F +#define IQM_CF_TAP_RE1__PRE 0x2 +#define IQM_CF_TAP_RE2__A 0x1860022 +#define IQM_CF_TAP_RE2__W 7 +#define IQM_CF_TAP_RE2__M 0x7F +#define IQM_CF_TAP_RE2__PRE 0x2 +#define IQM_CF_TAP_RE3__A 0x1860023 +#define IQM_CF_TAP_RE3__W 7 +#define IQM_CF_TAP_RE3__M 0x7F +#define IQM_CF_TAP_RE3__PRE 0x2 +#define IQM_CF_TAP_RE4__A 0x1860024 +#define IQM_CF_TAP_RE4__W 7 +#define IQM_CF_TAP_RE4__M 0x7F +#define IQM_CF_TAP_RE4__PRE 0x2 +#define IQM_CF_TAP_RE5__A 0x1860025 +#define IQM_CF_TAP_RE5__W 7 +#define IQM_CF_TAP_RE5__M 0x7F +#define IQM_CF_TAP_RE5__PRE 0x2 +#define IQM_CF_TAP_RE6__A 0x1860026 +#define IQM_CF_TAP_RE6__W 7 +#define IQM_CF_TAP_RE6__M 0x7F +#define IQM_CF_TAP_RE6__PRE 0x2 +#define IQM_CF_TAP_RE7__A 0x1860027 +#define IQM_CF_TAP_RE7__W 9 +#define IQM_CF_TAP_RE7__M 0x1FF +#define IQM_CF_TAP_RE7__PRE 0x2 +#define IQM_CF_TAP_RE8__A 0x1860028 +#define IQM_CF_TAP_RE8__W 9 +#define IQM_CF_TAP_RE8__M 0x1FF +#define IQM_CF_TAP_RE8__PRE 0x2 +#define IQM_CF_TAP_RE9__A 0x1860029 +#define IQM_CF_TAP_RE9__W 9 +#define IQM_CF_TAP_RE9__M 0x1FF +#define IQM_CF_TAP_RE9__PRE 0x2 +#define IQM_CF_TAP_RE10__A 0x186002A +#define IQM_CF_TAP_RE10__W 9 +#define IQM_CF_TAP_RE10__M 0x1FF +#define IQM_CF_TAP_RE10__PRE 0x2 +#define IQM_CF_TAP_RE11__A 0x186002B +#define IQM_CF_TAP_RE11__W 9 +#define IQM_CF_TAP_RE11__M 0x1FF +#define IQM_CF_TAP_RE11__PRE 0x2 +#define IQM_CF_TAP_RE12__A 0x186002C +#define IQM_CF_TAP_RE12__W 9 +#define IQM_CF_TAP_RE12__M 0x1FF +#define IQM_CF_TAP_RE12__PRE 0x2 +#define IQM_CF_TAP_RE13__A 0x186002D +#define IQM_CF_TAP_RE13__W 9 +#define IQM_CF_TAP_RE13__M 0x1FF +#define IQM_CF_TAP_RE13__PRE 0x2 +#define IQM_CF_TAP_RE14__A 0x186002E +#define IQM_CF_TAP_RE14__W 9 +#define IQM_CF_TAP_RE14__M 0x1FF +#define IQM_CF_TAP_RE14__PRE 0x2 +#define IQM_CF_TAP_RE15__A 0x186002F +#define IQM_CF_TAP_RE15__W 9 +#define IQM_CF_TAP_RE15__M 0x1FF +#define IQM_CF_TAP_RE15__PRE 0x2 +#define IQM_CF_TAP_RE16__A 0x1860030 +#define IQM_CF_TAP_RE16__W 9 +#define IQM_CF_TAP_RE16__M 0x1FF +#define IQM_CF_TAP_RE16__PRE 0x2 +#define IQM_CF_TAP_RE17__A 0x1860031 +#define IQM_CF_TAP_RE17__W 9 +#define IQM_CF_TAP_RE17__M 0x1FF +#define IQM_CF_TAP_RE17__PRE 0x2 +#define IQM_CF_TAP_RE18__A 0x1860032 +#define IQM_CF_TAP_RE18__W 9 +#define IQM_CF_TAP_RE18__M 0x1FF +#define IQM_CF_TAP_RE18__PRE 0x2 +#define IQM_CF_TAP_RE19__A 0x1860033 +#define IQM_CF_TAP_RE19__W 9 +#define IQM_CF_TAP_RE19__M 0x1FF +#define IQM_CF_TAP_RE19__PRE 0x2 +#define IQM_CF_TAP_RE20__A 0x1860034 +#define IQM_CF_TAP_RE20__W 9 +#define IQM_CF_TAP_RE20__M 0x1FF +#define IQM_CF_TAP_RE20__PRE 0x2 +#define IQM_CF_TAP_RE21__A 0x1860035 +#define IQM_CF_TAP_RE21__W 11 +#define IQM_CF_TAP_RE21__M 0x7FF +#define IQM_CF_TAP_RE21__PRE 0x2 +#define IQM_CF_TAP_RE22__A 0x1860036 +#define IQM_CF_TAP_RE22__W 11 +#define IQM_CF_TAP_RE22__M 0x7FF +#define IQM_CF_TAP_RE22__PRE 0x2 +#define IQM_CF_TAP_RE23__A 0x1860037 +#define IQM_CF_TAP_RE23__W 11 +#define IQM_CF_TAP_RE23__M 0x7FF +#define IQM_CF_TAP_RE23__PRE 0x2 +#define IQM_CF_TAP_RE24__A 0x1860038 +#define IQM_CF_TAP_RE24__W 11 +#define IQM_CF_TAP_RE24__M 0x7FF +#define IQM_CF_TAP_RE24__PRE 0x2 +#define IQM_CF_TAP_RE25__A 0x1860039 +#define IQM_CF_TAP_RE25__W 11 +#define IQM_CF_TAP_RE25__M 0x7FF +#define IQM_CF_TAP_RE25__PRE 0x2 +#define IQM_CF_TAP_RE26__A 0x186003A +#define IQM_CF_TAP_RE26__W 11 +#define IQM_CF_TAP_RE26__M 0x7FF +#define IQM_CF_TAP_RE26__PRE 0x2 +#define IQM_CF_TAP_RE27__A 0x186003B +#define IQM_CF_TAP_RE27__W 11 +#define IQM_CF_TAP_RE27__M 0x7FF +#define IQM_CF_TAP_RE27__PRE 0x2 +#define IQM_CF_TAP_IM0__A 0x1860040 +#define IQM_CF_TAP_IM0__W 7 +#define IQM_CF_TAP_IM0__M 0x7F +#define IQM_CF_TAP_IM0__PRE 0x2 +#define IQM_CF_TAP_IM1__A 0x1860041 +#define IQM_CF_TAP_IM1__W 7 +#define IQM_CF_TAP_IM1__M 0x7F +#define IQM_CF_TAP_IM1__PRE 0x2 +#define IQM_CF_TAP_IM2__A 0x1860042 +#define IQM_CF_TAP_IM2__W 7 +#define IQM_CF_TAP_IM2__M 0x7F +#define IQM_CF_TAP_IM2__PRE 0x2 +#define IQM_CF_TAP_IM3__A 0x1860043 +#define IQM_CF_TAP_IM3__W 7 +#define IQM_CF_TAP_IM3__M 0x7F +#define IQM_CF_TAP_IM3__PRE 0x2 +#define IQM_CF_TAP_IM4__A 0x1860044 +#define IQM_CF_TAP_IM4__W 7 +#define IQM_CF_TAP_IM4__M 0x7F +#define IQM_CF_TAP_IM4__PRE 0x2 +#define IQM_CF_TAP_IM5__A 0x1860045 +#define IQM_CF_TAP_IM5__W 7 +#define IQM_CF_TAP_IM5__M 0x7F +#define IQM_CF_TAP_IM5__PRE 0x2 +#define IQM_CF_TAP_IM6__A 0x1860046 +#define IQM_CF_TAP_IM6__W 7 +#define IQM_CF_TAP_IM6__M 0x7F +#define IQM_CF_TAP_IM6__PRE 0x2 +#define IQM_CF_TAP_IM7__A 0x1860047 +#define IQM_CF_TAP_IM7__W 9 +#define IQM_CF_TAP_IM7__M 0x1FF +#define IQM_CF_TAP_IM7__PRE 0x2 +#define IQM_CF_TAP_IM8__A 0x1860048 +#define IQM_CF_TAP_IM8__W 9 +#define IQM_CF_TAP_IM8__M 0x1FF +#define IQM_CF_TAP_IM8__PRE 0x2 +#define IQM_CF_TAP_IM9__A 0x1860049 +#define IQM_CF_TAP_IM9__W 9 +#define IQM_CF_TAP_IM9__M 0x1FF +#define IQM_CF_TAP_IM9__PRE 0x2 +#define IQM_CF_TAP_IM10__A 0x186004A +#define IQM_CF_TAP_IM10__W 9 +#define IQM_CF_TAP_IM10__M 0x1FF +#define IQM_CF_TAP_IM10__PRE 0x2 +#define IQM_CF_TAP_IM11__A 0x186004B +#define IQM_CF_TAP_IM11__W 9 +#define IQM_CF_TAP_IM11__M 0x1FF +#define IQM_CF_TAP_IM11__PRE 0x2 +#define IQM_CF_TAP_IM12__A 0x186004C +#define IQM_CF_TAP_IM12__W 9 +#define IQM_CF_TAP_IM12__M 0x1FF +#define IQM_CF_TAP_IM12__PRE 0x2 +#define IQM_CF_TAP_IM13__A 0x186004D +#define IQM_CF_TAP_IM13__W 9 +#define IQM_CF_TAP_IM13__M 0x1FF +#define IQM_CF_TAP_IM13__PRE 0x2 +#define IQM_CF_TAP_IM14__A 0x186004E +#define IQM_CF_TAP_IM14__W 9 +#define IQM_CF_TAP_IM14__M 0x1FF +#define IQM_CF_TAP_IM14__PRE 0x2 +#define IQM_CF_TAP_IM15__A 0x186004F +#define IQM_CF_TAP_IM15__W 9 +#define IQM_CF_TAP_IM15__M 0x1FF +#define IQM_CF_TAP_IM15__PRE 0x2 +#define IQM_CF_TAP_IM16__A 0x1860050 +#define IQM_CF_TAP_IM16__W 9 +#define IQM_CF_TAP_IM16__M 0x1FF +#define IQM_CF_TAP_IM16__PRE 0x2 +#define IQM_CF_TAP_IM17__A 0x1860051 +#define IQM_CF_TAP_IM17__W 9 +#define IQM_CF_TAP_IM17__M 0x1FF +#define IQM_CF_TAP_IM17__PRE 0x2 +#define IQM_CF_TAP_IM18__A 0x1860052 +#define IQM_CF_TAP_IM18__W 9 +#define IQM_CF_TAP_IM18__M 0x1FF +#define IQM_CF_TAP_IM18__PRE 0x2 +#define IQM_CF_TAP_IM19__A 0x1860053 +#define IQM_CF_TAP_IM19__W 9 +#define IQM_CF_TAP_IM19__M 0x1FF +#define IQM_CF_TAP_IM19__PRE 0x2 +#define IQM_CF_TAP_IM20__A 0x1860054 +#define IQM_CF_TAP_IM20__W 9 +#define IQM_CF_TAP_IM20__M 0x1FF +#define IQM_CF_TAP_IM20__PRE 0x2 +#define IQM_CF_TAP_IM21__A 0x1860055 +#define IQM_CF_TAP_IM21__W 11 +#define IQM_CF_TAP_IM21__M 0x7FF +#define IQM_CF_TAP_IM21__PRE 0x2 +#define IQM_CF_TAP_IM22__A 0x1860056 +#define IQM_CF_TAP_IM22__W 11 +#define IQM_CF_TAP_IM22__M 0x7FF +#define IQM_CF_TAP_IM22__PRE 0x2 +#define IQM_CF_TAP_IM23__A 0x1860057 +#define IQM_CF_TAP_IM23__W 11 +#define IQM_CF_TAP_IM23__M 0x7FF +#define IQM_CF_TAP_IM23__PRE 0x2 +#define IQM_CF_TAP_IM24__A 0x1860058 +#define IQM_CF_TAP_IM24__W 11 +#define IQM_CF_TAP_IM24__M 0x7FF +#define IQM_CF_TAP_IM24__PRE 0x2 +#define IQM_CF_TAP_IM25__A 0x1860059 +#define IQM_CF_TAP_IM25__W 11 +#define IQM_CF_TAP_IM25__M 0x7FF +#define IQM_CF_TAP_IM25__PRE 0x2 +#define IQM_CF_TAP_IM26__A 0x186005A +#define IQM_CF_TAP_IM26__W 11 +#define IQM_CF_TAP_IM26__M 0x7FF +#define IQM_CF_TAP_IM26__PRE 0x2 +#define IQM_CF_TAP_IM27__A 0x186005B +#define IQM_CF_TAP_IM27__W 11 +#define IQM_CF_TAP_IM27__M 0x7FF +#define IQM_CF_TAP_IM27__PRE 0x2 + + + +#define IQM_AF_COMM_EXEC__A 0x1870000 +#define IQM_AF_COMM_EXEC__W 2 +#define IQM_AF_COMM_EXEC__M 0x3 +#define IQM_AF_COMM_EXEC__PRE 0x0 +#define IQM_AF_COMM_EXEC_STOP 0x0 +#define IQM_AF_COMM_EXEC_ACTIVE 0x1 +#define IQM_AF_COMM_EXEC_HOLD 0x2 + +#define IQM_AF_COMM_MB__A 0x1870002 +#define IQM_AF_COMM_MB__W 8 +#define IQM_AF_COMM_MB__M 0xFF +#define IQM_AF_COMM_MB__PRE 0x0 +#define IQM_AF_COMM_MB_CTL__B 0 +#define IQM_AF_COMM_MB_CTL__W 1 +#define IQM_AF_COMM_MB_CTL__M 0x1 +#define IQM_AF_COMM_MB_CTL__PRE 0x0 +#define IQM_AF_COMM_MB_CTL_CTL_OFF 0x0 +#define IQM_AF_COMM_MB_CTL_CTL_ON 0x1 +#define IQM_AF_COMM_MB_OBS__B 1 +#define IQM_AF_COMM_MB_OBS__W 1 +#define IQM_AF_COMM_MB_OBS__M 0x2 +#define IQM_AF_COMM_MB_OBS__PRE 0x0 +#define IQM_AF_COMM_MB_OBS_OBS_OFF 0x0 +#define IQM_AF_COMM_MB_OBS_OBS_ON 0x2 +#define IQM_AF_COMM_MB_MUX_CTRL__B 2 +#define IQM_AF_COMM_MB_MUX_CTRL__W 3 +#define IQM_AF_COMM_MB_MUX_CTRL__M 0x1C +#define IQM_AF_COMM_MB_MUX_CTRL__PRE 0x0 +#define IQM_AF_COMM_MB_MUX_CTRL_AF_DATA_INPUT 0x0 +#define IQM_AF_COMM_MB_MUX_CTRL_SENSE_INPUT 0x4 +#define IQM_AF_COMM_MB_MUX_CTRL_AF_DATA_OUTPUT 0x8 +#define IQM_AF_COMM_MB_MUX_CTRL_IF_AGC_OUTPUT 0xC +#define IQM_AF_COMM_MB_MUX_CTRL_RF_AGC_OUTPUT 0x10 +#define IQM_AF_COMM_MB_MUX_OBS__B 5 +#define IQM_AF_COMM_MB_MUX_OBS__W 3 +#define IQM_AF_COMM_MB_MUX_OBS__M 0xE0 +#define IQM_AF_COMM_MB_MUX_OBS__PRE 0x0 +#define IQM_AF_COMM_MB_MUX_OBS_AF_DATA_INPUT 0x0 +#define IQM_AF_COMM_MB_MUX_OBS_SENSE_INPUT 0x20 +#define IQM_AF_COMM_MB_MUX_OBS_AF_DATA_OUTPUT 0x40 +#define IQM_AF_COMM_MB_MUX_OBS_IF_AGC_OUTPUT 0x60 +#define IQM_AF_COMM_MB_MUX_OBS_RF_AGC_OUTPUT 0x80 + +#define IQM_AF_COMM_INT_REQ__A 0x1870003 +#define IQM_AF_COMM_INT_REQ__W 1 +#define IQM_AF_COMM_INT_REQ__M 0x1 +#define IQM_AF_COMM_INT_REQ__PRE 0x0 +#define IQM_AF_COMM_INT_STA__A 0x1870005 +#define IQM_AF_COMM_INT_STA__W 2 +#define IQM_AF_COMM_INT_STA__M 0x3 +#define IQM_AF_COMM_INT_STA__PRE 0x0 +#define IQM_AF_COMM_INT_STA_CLP_INT_STA__B 0 +#define IQM_AF_COMM_INT_STA_CLP_INT_STA__W 1 +#define IQM_AF_COMM_INT_STA_CLP_INT_STA__M 0x1 +#define IQM_AF_COMM_INT_STA_CLP_INT_STA__PRE 0x0 +#define IQM_AF_COMM_INT_STA_SNS_INT_STA__B 1 +#define IQM_AF_COMM_INT_STA_SNS_INT_STA__W 1 +#define IQM_AF_COMM_INT_STA_SNS_INT_STA__M 0x2 +#define IQM_AF_COMM_INT_STA_SNS_INT_STA__PRE 0x0 + +#define IQM_AF_COMM_INT_MSK__A 0x1870006 +#define IQM_AF_COMM_INT_MSK__W 2 +#define IQM_AF_COMM_INT_MSK__M 0x3 +#define IQM_AF_COMM_INT_MSK__PRE 0x0 +#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__B 0 +#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__W 1 +#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__M 0x1 +#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__PRE 0x0 +#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__B 1 +#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__W 1 +#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__M 0x2 +#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__PRE 0x0 + +#define IQM_AF_COMM_INT_STM__A 0x1870007 +#define IQM_AF_COMM_INT_STM__W 2 +#define IQM_AF_COMM_INT_STM__M 0x3 +#define IQM_AF_COMM_INT_STM__PRE 0x0 +#define IQM_AF_COMM_INT_STM_CLP_INT_STA__B 0 +#define IQM_AF_COMM_INT_STM_CLP_INT_STA__W 1 +#define IQM_AF_COMM_INT_STM_CLP_INT_STA__M 0x1 +#define IQM_AF_COMM_INT_STM_CLP_INT_STA__PRE 0x0 +#define IQM_AF_COMM_INT_STM_SNS_INT_STA__B 1 +#define IQM_AF_COMM_INT_STM_SNS_INT_STA__W 1 +#define IQM_AF_COMM_INT_STM_SNS_INT_STA__M 0x2 +#define IQM_AF_COMM_INT_STM_SNS_INT_STA__PRE 0x0 + + +#define IQM_AF_FDB_SEL__A 0x1870010 +#define IQM_AF_FDB_SEL__W 1 +#define IQM_AF_FDB_SEL__M 0x1 +#define IQM_AF_FDB_SEL__PRE 0x0 + +#define IQM_AF_INVEXT__A 0x1870011 +#define IQM_AF_INVEXT__W 1 +#define IQM_AF_INVEXT__M 0x1 +#define IQM_AF_INVEXT__PRE 0x0 +#define IQM_AF_CLKNEG__A 0x1870012 +#define IQM_AF_CLKNEG__W 2 +#define IQM_AF_CLKNEG__M 0x3 +#define IQM_AF_CLKNEG__PRE 0x0 + +#define IQM_AF_CLKNEG_CLKNEGPEAK__B 0 +#define IQM_AF_CLKNEG_CLKNEGPEAK__W 1 +#define IQM_AF_CLKNEG_CLKNEGPEAK__M 0x1 +#define IQM_AF_CLKNEG_CLKNEGPEAK__PRE 0x0 +#define IQM_AF_CLKNEG_CLKNEGPEAK_CLK_ADC_PEAK_POS 0x0 +#define IQM_AF_CLKNEG_CLKNEGPEAK_CLK_ADC_PEAK_NEG 0x1 + +#define IQM_AF_CLKNEG_CLKNEGDATA__B 1 +#define IQM_AF_CLKNEG_CLKNEGDATA__W 1 +#define IQM_AF_CLKNEG_CLKNEGDATA__M 0x2 +#define IQM_AF_CLKNEG_CLKNEGDATA__PRE 0x0 +#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS 0x0 +#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG 0x2 + + +#define IQM_AF_MON_IN_MUX__A 0x1870013 +#define IQM_AF_MON_IN_MUX__W 2 +#define IQM_AF_MON_IN_MUX__M 0x3 +#define IQM_AF_MON_IN_MUX__PRE 0x0 + +#define IQM_AF_MON_IN5__A 0x1870014 +#define IQM_AF_MON_IN5__W 10 +#define IQM_AF_MON_IN5__M 0x3FF +#define IQM_AF_MON_IN5__PRE 0x0 + +#define IQM_AF_MON_IN4__A 0x1870015 +#define IQM_AF_MON_IN4__W 10 +#define IQM_AF_MON_IN4__M 0x3FF +#define IQM_AF_MON_IN4__PRE 0x0 + +#define IQM_AF_MON_IN3__A 0x1870016 +#define IQM_AF_MON_IN3__W 10 +#define IQM_AF_MON_IN3__M 0x3FF +#define IQM_AF_MON_IN3__PRE 0x0 + +#define IQM_AF_MON_IN2__A 0x1870017 +#define IQM_AF_MON_IN2__W 10 +#define IQM_AF_MON_IN2__M 0x3FF +#define IQM_AF_MON_IN2__PRE 0x0 + +#define IQM_AF_MON_IN1__A 0x1870018 +#define IQM_AF_MON_IN1__W 10 +#define IQM_AF_MON_IN1__M 0x3FF +#define IQM_AF_MON_IN1__PRE 0x0 + +#define IQM_AF_MON_IN0__A 0x1870019 +#define IQM_AF_MON_IN0__W 10 +#define IQM_AF_MON_IN0__M 0x3FF +#define IQM_AF_MON_IN0__PRE 0x0 + +#define IQM_AF_MON_IN_VAL__A 0x187001A +#define IQM_AF_MON_IN_VAL__W 1 +#define IQM_AF_MON_IN_VAL__M 0x1 +#define IQM_AF_MON_IN_VAL__PRE 0x0 + +#define IQM_AF_START_LOCK__A 0x187001B +#define IQM_AF_START_LOCK__W 1 +#define IQM_AF_START_LOCK__M 0x1 +#define IQM_AF_START_LOCK__PRE 0x0 + +#define IQM_AF_PHASE0__A 0x187001C +#define IQM_AF_PHASE0__W 7 +#define IQM_AF_PHASE0__M 0x7F +#define IQM_AF_PHASE0__PRE 0x0 + +#define IQM_AF_PHASE1__A 0x187001D +#define IQM_AF_PHASE1__W 7 +#define IQM_AF_PHASE1__M 0x7F +#define IQM_AF_PHASE1__PRE 0x0 + +#define IQM_AF_PHASE2__A 0x187001E +#define IQM_AF_PHASE2__W 7 +#define IQM_AF_PHASE2__M 0x7F +#define IQM_AF_PHASE2__PRE 0x0 + +#define IQM_AF_SCU_PHASE__A 0x187001F +#define IQM_AF_SCU_PHASE__W 2 +#define IQM_AF_SCU_PHASE__M 0x3 +#define IQM_AF_SCU_PHASE__PRE 0x0 + +#define IQM_AF_SYNC_SEL__A 0x1870020 +#define IQM_AF_SYNC_SEL__W 2 +#define IQM_AF_SYNC_SEL__M 0x3 +#define IQM_AF_SYNC_SEL__PRE 0x0 +#define IQM_AF_ADC_CONF__A 0x1870021 +#define IQM_AF_ADC_CONF__W 4 +#define IQM_AF_ADC_CONF__M 0xF +#define IQM_AF_ADC_CONF__PRE 0x0 + +#define IQM_AF_ADC_CONF_ADC_SIGN__B 0 +#define IQM_AF_ADC_CONF_ADC_SIGN__W 1 +#define IQM_AF_ADC_CONF_ADC_SIGN__M 0x1 +#define IQM_AF_ADC_CONF_ADC_SIGN__PRE 0x0 +#define IQM_AF_ADC_CONF_ADC_SIGN_ADC_SIGNED 0x0 +#define IQM_AF_ADC_CONF_ADC_SIGN_ADC_UNSIGNED 0x1 + +#define IQM_AF_ADC_CONF_BITREVERSE_ADC__B 1 +#define IQM_AF_ADC_CONF_BITREVERSE_ADC__W 1 +#define IQM_AF_ADC_CONF_BITREVERSE_ADC__M 0x2 +#define IQM_AF_ADC_CONF_BITREVERSE_ADC__PRE 0x0 +#define IQM_AF_ADC_CONF_BITREVERSE_ADC_ADC_NORMAL 0x0 +#define IQM_AF_ADC_CONF_BITREVERSE_ADC_ADC_BITREVERSED 0x2 + +#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__B 2 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__W 1 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__M 0x4 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__PRE 0x0 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSI_IFAGC_DAC_NORMAL 0x0 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSI_IFAGC_DAC_BITREVERSED 0x4 + +#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__B 3 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__W 1 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__M 0x8 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__PRE 0x0 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSR_RFAGC_DAC_NORMAL 0x0 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSR_RFAGC_DAC_BITREVERSED 0x8 + + +#define IQM_AF_CLP_CLIP__A 0x1870022 +#define IQM_AF_CLP_CLIP__W 16 +#define IQM_AF_CLP_CLIP__M 0xFFFF +#define IQM_AF_CLP_CLIP__PRE 0x0 + +#define IQM_AF_CLP_LEN__A 0x1870023 +#define IQM_AF_CLP_LEN__W 16 +#define IQM_AF_CLP_LEN__M 0xFFFF +#define IQM_AF_CLP_LEN__PRE 0x0 +#define IQM_AF_CLP_LEN_QAM_B_64 0x400 +#define IQM_AF_CLP_LEN_QAM_B_256 0x400 +#define IQM_AF_CLP_LEN_ATV 0x0 + + +#define IQM_AF_CLP_TH__A 0x1870024 +#define IQM_AF_CLP_TH__W 9 +#define IQM_AF_CLP_TH__M 0x1FF +#define IQM_AF_CLP_TH__PRE 0x0 +#define IQM_AF_CLP_TH_QAM_B_64 0x80 +#define IQM_AF_CLP_TH_QAM_B_256 0x80 +#define IQM_AF_CLP_TH_ATV 0x1C0 + + +#define IQM_AF_DCF_BYPASS__A 0x1870025 +#define IQM_AF_DCF_BYPASS__W 1 +#define IQM_AF_DCF_BYPASS__M 0x1 +#define IQM_AF_DCF_BYPASS__PRE 0x0 +#define IQM_AF_DCF_BYPASS_ACTIVE 0x0 +#define IQM_AF_DCF_BYPASS_BYPASS 0x1 + + +#define IQM_AF_SNS_LEN__A 0x1870026 +#define IQM_AF_SNS_LEN__W 16 +#define IQM_AF_SNS_LEN__M 0xFFFF +#define IQM_AF_SNS_LEN__PRE 0x0 +#define IQM_AF_SNS_LEN_QAM_B_64 0x400 +#define IQM_AF_SNS_LEN_QAM_B_256 0x400 +#define IQM_AF_SNS_LEN_ATV 0x0 + + +#define IQM_AF_SNS_SENSE__A 0x1870027 +#define IQM_AF_SNS_SENSE__W 16 +#define IQM_AF_SNS_SENSE__M 0xFFFF +#define IQM_AF_SNS_SENSE__PRE 0x0 + +#define IQM_AF_AGC_IF__A 0x1870028 +#define IQM_AF_AGC_IF__W 15 +#define IQM_AF_AGC_IF__M 0x7FFF +#define IQM_AF_AGC_IF__PRE 0x0 + +#define IQM_AF_AGC_RF__A 0x1870029 +#define IQM_AF_AGC_RF__W 15 +#define IQM_AF_AGC_RF__M 0x7FFF +#define IQM_AF_AGC_RF__PRE 0x0 + +#define IQM_AF_PGA_GAIN__A 0x187002A +#define IQM_AF_PGA_GAIN__W 4 +#define IQM_AF_PGA_GAIN__M 0xF +#define IQM_AF_PGA_GAIN__PRE 0x0 + +#define IQM_AF_PDREF__A 0x187002B +#define IQM_AF_PDREF__W 5 +#define IQM_AF_PDREF__M 0x1F +#define IQM_AF_PDREF__PRE 0x0 +#define IQM_AF_PDREF_QAM_B_64 0xF +#define IQM_AF_PDREF_QAM_B_256 0xF +#define IQM_AF_PDREF_ATV 0xF + +#define IQM_AF_STDBY__A 0x187002C +#define IQM_AF_STDBY__W 6 +#define IQM_AF_STDBY__M 0x3F +#define IQM_AF_STDBY__PRE 0x0 + +#define IQM_AF_STDBY_STDBY_BIAS__B 0 +#define IQM_AF_STDBY_STDBY_BIAS__W 1 +#define IQM_AF_STDBY_STDBY_BIAS__M 0x1 +#define IQM_AF_STDBY_STDBY_BIAS__PRE 0x0 +#define IQM_AF_STDBY_STDBY_BIAS_ACTIVE 0x0 +#define IQM_AF_STDBY_STDBY_BIAS_STANDBY 0x1 + +#define IQM_AF_STDBY_STDBY_ADC__B 1 +#define IQM_AF_STDBY_STDBY_ADC__W 1 +#define IQM_AF_STDBY_STDBY_ADC__M 0x2 +#define IQM_AF_STDBY_STDBY_ADC__PRE 0x0 +#define IQM_AF_STDBY_STDBY_ADC_A1_ACTIVE 0x0 +#define IQM_AF_STDBY_STDBY_ADC_A1_STANDBY 0x2 +#define IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE 0x2 +#define IQM_AF_STDBY_STDBY_ADC_A2_STANDBY 0x0 + +#define IQM_AF_STDBY_STDBY_AMP__B 2 +#define IQM_AF_STDBY_STDBY_AMP__W 1 +#define IQM_AF_STDBY_STDBY_AMP__M 0x4 +#define IQM_AF_STDBY_STDBY_AMP__PRE 0x0 +#define IQM_AF_STDBY_STDBY_AMP_A1_ACTIVE 0x0 +#define IQM_AF_STDBY_STDBY_AMP_A1_STANDBY 0x4 +#define IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE 0x4 +#define IQM_AF_STDBY_STDBY_AMP_A2_STANDBY 0x0 + +#define IQM_AF_STDBY_STDBY_PD__B 3 +#define IQM_AF_STDBY_STDBY_PD__W 1 +#define IQM_AF_STDBY_STDBY_PD__M 0x8 +#define IQM_AF_STDBY_STDBY_PD__PRE 0x0 +#define IQM_AF_STDBY_STDBY_PD_A1_ACTIVE 0x0 +#define IQM_AF_STDBY_STDBY_PD_A1_STANDBY 0x8 +#define IQM_AF_STDBY_STDBY_PD_A2_ACTIVE 0x8 +#define IQM_AF_STDBY_STDBY_PD_A2_STANDBY 0x0 + +#define IQM_AF_STDBY_STDBY_TAGC_IF__B 4 +#define IQM_AF_STDBY_STDBY_TAGC_IF__W 1 +#define IQM_AF_STDBY_STDBY_TAGC_IF__M 0x10 +#define IQM_AF_STDBY_STDBY_TAGC_IF__PRE 0x0 +#define IQM_AF_STDBY_STDBY_TAGC_IF_A1_ACTIVE 0x0 +#define IQM_AF_STDBY_STDBY_TAGC_IF_A1_STANDBY 0x10 +#define IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE 0x10 +#define IQM_AF_STDBY_STDBY_TAGC_IF_A2_STANDBY 0x0 + +#define IQM_AF_STDBY_STDBY_TAGC_RF__B 5 +#define IQM_AF_STDBY_STDBY_TAGC_RF__W 1 +#define IQM_AF_STDBY_STDBY_TAGC_RF__M 0x20 +#define IQM_AF_STDBY_STDBY_TAGC_RF__PRE 0x0 +#define IQM_AF_STDBY_STDBY_TAGC_RF_A1_ACTIVE 0x0 +#define IQM_AF_STDBY_STDBY_TAGC_RF_A1_STANDBY 0x20 +#define IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE 0x20 +#define IQM_AF_STDBY_STDBY_TAGC_RF_A2_STANDBY 0x0 + + +#define IQM_AF_AMUX__A 0x187002D +#define IQM_AF_AMUX__W 2 +#define IQM_AF_AMUX__M 0x3 +#define IQM_AF_AMUX__PRE 0x0 + +#define IQM_AF_TST_AFEMAIN__A 0x187002E +#define IQM_AF_TST_AFEMAIN__W 8 +#define IQM_AF_TST_AFEMAIN__M 0xFF +#define IQM_AF_TST_AFEMAIN__PRE 0x0 + + + +#define IQM_RT_RAM__A 0x1880000 + +#define IQM_RT_RAM_DLY__B 0 +#define IQM_RT_RAM_DLY__W 13 +#define IQM_RT_RAM_DLY__M 0x1FFF +#define IQM_RT_RAM_DLY__PRE 0x0 + + + + + +#define ORX_COMM_EXEC__A 0x2000000 +#define ORX_COMM_EXEC__W 2 +#define ORX_COMM_EXEC__M 0x3 +#define ORX_COMM_EXEC__PRE 0x0 +#define ORX_COMM_EXEC_STOP 0x0 +#define ORX_COMM_EXEC_ACTIVE 0x1 +#define ORX_COMM_EXEC_HOLD 0x2 + +#define ORX_COMM_STATE__A 0x2000001 +#define ORX_COMM_STATE__W 16 +#define ORX_COMM_STATE__M 0xFFFF +#define ORX_COMM_STATE__PRE 0x0 +#define ORX_COMM_MB__A 0x2000002 +#define ORX_COMM_MB__W 16 +#define ORX_COMM_MB__M 0xFFFF +#define ORX_COMM_MB__PRE 0x0 +#define ORX_COMM_INT_REQ__A 0x2000003 +#define ORX_COMM_INT_REQ__W 16 +#define ORX_COMM_INT_REQ__M 0xFFFF +#define ORX_COMM_INT_REQ__PRE 0x0 +#define ORX_COMM_INT_REQ_EQU_REQ__B 0 +#define ORX_COMM_INT_REQ_EQU_REQ__W 1 +#define ORX_COMM_INT_REQ_EQU_REQ__M 0x1 +#define ORX_COMM_INT_REQ_EQU_REQ__PRE 0x0 +#define ORX_COMM_INT_REQ_DDC_REQ__B 1 +#define ORX_COMM_INT_REQ_DDC_REQ__W 1 +#define ORX_COMM_INT_REQ_DDC_REQ__M 0x2 +#define ORX_COMM_INT_REQ_DDC_REQ__PRE 0x0 +#define ORX_COMM_INT_REQ_FWP_REQ__B 2 +#define ORX_COMM_INT_REQ_FWP_REQ__W 1 +#define ORX_COMM_INT_REQ_FWP_REQ__M 0x4 +#define ORX_COMM_INT_REQ_FWP_REQ__PRE 0x0 +#define ORX_COMM_INT_REQ_CON_REQ__B 3 +#define ORX_COMM_INT_REQ_CON_REQ__W 1 +#define ORX_COMM_INT_REQ_CON_REQ__M 0x8 +#define ORX_COMM_INT_REQ_CON_REQ__PRE 0x0 +#define ORX_COMM_INT_REQ_NSU_REQ__B 4 +#define ORX_COMM_INT_REQ_NSU_REQ__W 1 +#define ORX_COMM_INT_REQ_NSU_REQ__M 0x10 +#define ORX_COMM_INT_REQ_NSU_REQ__PRE 0x0 + + +#define ORX_COMM_INT_STA__A 0x2000005 +#define ORX_COMM_INT_STA__W 16 +#define ORX_COMM_INT_STA__M 0xFFFF +#define ORX_COMM_INT_STA__PRE 0x0 +#define ORX_COMM_INT_MSK__A 0x2000006 +#define ORX_COMM_INT_MSK__W 16 +#define ORX_COMM_INT_MSK__M 0xFFFF +#define ORX_COMM_INT_MSK__PRE 0x0 +#define ORX_COMM_INT_STM__A 0x2000007 +#define ORX_COMM_INT_STM__W 16 +#define ORX_COMM_INT_STM__M 0xFFFF +#define ORX_COMM_INT_STM__PRE 0x0 + + + +#define ORX_TOP_COMM_EXEC__A 0x2010000 +#define ORX_TOP_COMM_EXEC__W 2 +#define ORX_TOP_COMM_EXEC__M 0x3 +#define ORX_TOP_COMM_EXEC__PRE 0x0 +#define ORX_TOP_COMM_EXEC_STOP 0x0 +#define ORX_TOP_COMM_EXEC_ACTIVE 0x1 +#define ORX_TOP_COMM_EXEC_HOLD 0x2 + + +#define ORX_TOP_COMM_KEY__A 0x201000F +#define ORX_TOP_COMM_KEY__W 16 +#define ORX_TOP_COMM_KEY__M 0xFFFF +#define ORX_TOP_COMM_KEY__PRE 0x0 +#define ORX_TOP_COMM_KEY_KEY 0xFABA + +#define ORX_TOP_MDE_W__A 0x2010010 +#define ORX_TOP_MDE_W__W 2 +#define ORX_TOP_MDE_W__M 0x3 +#define ORX_TOP_MDE_W__PRE 0x2 +#define ORX_TOP_MDE_W_RATE_1544KBPS 0x0 +#define ORX_TOP_MDE_W_RATE_3088KBPS 0x1 +#define ORX_TOP_MDE_W_RATE_2048KBPS_SQRT 0x2 +#define ORX_TOP_MDE_W_RATE_2048KBPS_RO 0x3 + +#define ORX_TOP_AIF_CTRL_W__A 0x2010011 +#define ORX_TOP_AIF_CTRL_W__W 3 +#define ORX_TOP_AIF_CTRL_W__M 0x7 +#define ORX_TOP_AIF_CTRL_W__PRE 0x0 +#define ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE__B 0 +#define ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE__W 1 +#define ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE__M 0x1 +#define ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE__PRE 0x0 +#define ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE_ADC_SAMPL_ON_POS_CLK_EDGE 0x0 +#define ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE_ADC_SAMPL_ON_NEG_CLK_EDGE 0x1 +#define ORX_TOP_AIF_CTRL_W_BIT_REVERSE__B 1 +#define ORX_TOP_AIF_CTRL_W_BIT_REVERSE__W 1 +#define ORX_TOP_AIF_CTRL_W_BIT_REVERSE__M 0x2 +#define ORX_TOP_AIF_CTRL_W_BIT_REVERSE__PRE 0x0 +#define ORX_TOP_AIF_CTRL_W_BIT_REVERSE_REGULAR_BIT_ORDER_ADC 0x0 +#define ORX_TOP_AIF_CTRL_W_BIT_REVERSE_REVERSAL_BIT_ORDER_ADC 0x2 +#define ORX_TOP_AIF_CTRL_W_INV_MSB__B 2 +#define ORX_TOP_AIF_CTRL_W_INV_MSB__W 1 +#define ORX_TOP_AIF_CTRL_W_INV_MSB__M 0x4 +#define ORX_TOP_AIF_CTRL_W_INV_MSB__PRE 0x0 +#define ORX_TOP_AIF_CTRL_W_INV_MSB_NO_MSB_INVERSION_ADC 0x0 +#define ORX_TOP_AIF_CTRL_W_INV_MSB_MSB_INVERSION_ADC 0x4 + + + +#define ORX_FWP_COMM_EXEC__A 0x2020000 +#define ORX_FWP_COMM_EXEC__W 2 +#define ORX_FWP_COMM_EXEC__M 0x3 +#define ORX_FWP_COMM_EXEC__PRE 0x0 +#define ORX_FWP_COMM_EXEC_STOP 0x0 +#define ORX_FWP_COMM_EXEC_ACTIVE 0x1 +#define ORX_FWP_COMM_EXEC_HOLD 0x2 + +#define ORX_FWP_COMM_MB__A 0x2020002 +#define ORX_FWP_COMM_MB__W 8 +#define ORX_FWP_COMM_MB__M 0xFF +#define ORX_FWP_COMM_MB__PRE 0x0 +#define ORX_FWP_COMM_MB_CTL__B 0 +#define ORX_FWP_COMM_MB_CTL__W 1 +#define ORX_FWP_COMM_MB_CTL__M 0x1 +#define ORX_FWP_COMM_MB_CTL__PRE 0x0 +#define ORX_FWP_COMM_MB_CTL_OFF 0x0 +#define ORX_FWP_COMM_MB_CTL_ON 0x1 +#define ORX_FWP_COMM_MB_OBS__B 1 +#define ORX_FWP_COMM_MB_OBS__W 1 +#define ORX_FWP_COMM_MB_OBS__M 0x2 +#define ORX_FWP_COMM_MB_OBS__PRE 0x0 +#define ORX_FWP_COMM_MB_OBS_OFF 0x0 +#define ORX_FWP_COMM_MB_OBS_ON 0x2 + +#define ORX_FWP_COMM_MB_CTL_MUX__B 2 +#define ORX_FWP_COMM_MB_CTL_MUX__W 3 +#define ORX_FWP_COMM_MB_CTL_MUX__M 0x1C +#define ORX_FWP_COMM_MB_CTL_MUX__PRE 0x0 + +#define ORX_FWP_COMM_MB_OBS_MUX__B 5 +#define ORX_FWP_COMM_MB_OBS_MUX__W 3 +#define ORX_FWP_COMM_MB_OBS_MUX__M 0xE0 +#define ORX_FWP_COMM_MB_OBS_MUX__PRE 0x0 + + +#define ORX_FWP_AAG_LEN_W__A 0x2020010 +#define ORX_FWP_AAG_LEN_W__W 16 +#define ORX_FWP_AAG_LEN_W__M 0xFFFF +#define ORX_FWP_AAG_LEN_W__PRE 0x800 + +#define ORX_FWP_AAG_THR_W__A 0x2020011 +#define ORX_FWP_AAG_THR_W__W 8 +#define ORX_FWP_AAG_THR_W__M 0xFF +#define ORX_FWP_AAG_THR_W__PRE 0x50 + +#define ORX_FWP_AAG_THR_CNT_R__A 0x2020012 +#define ORX_FWP_AAG_THR_CNT_R__W 16 +#define ORX_FWP_AAG_THR_CNT_R__M 0xFFFF +#define ORX_FWP_AAG_THR_CNT_R__PRE 0x0 + +#define ORX_FWP_AAG_SNS_CNT_R__A 0x2020013 +#define ORX_FWP_AAG_SNS_CNT_R__W 16 +#define ORX_FWP_AAG_SNS_CNT_R__M 0xFFFF +#define ORX_FWP_AAG_SNS_CNT_R__PRE 0x0 + +#define ORX_FWP_PFI_A_W__A 0x2020014 +#define ORX_FWP_PFI_A_W__W 8 +#define ORX_FWP_PFI_A_W__M 0xFF +#define ORX_FWP_PFI_A_W__PRE 0xB0 +#define ORX_FWP_PFI_A_W_RATE_2048KBPS 0xB0 +#define ORX_FWP_PFI_A_W_RATE_1544KBPS 0xA4 +#define ORX_FWP_PFI_A_W_RATE_3088KBPS 0xC0 + + +#define ORX_FWP_PFI_B_W__A 0x2020015 +#define ORX_FWP_PFI_B_W__W 8 +#define ORX_FWP_PFI_B_W__M 0xFF +#define ORX_FWP_PFI_B_W__PRE 0x9E +#define ORX_FWP_PFI_B_W_RATE_2048KBPS 0x9E +#define ORX_FWP_PFI_B_W_RATE_1544KBPS 0x94 +#define ORX_FWP_PFI_B_W_RATE_3088KBPS 0xB0 + + +#define ORX_FWP_PFI_C_W__A 0x2020016 +#define ORX_FWP_PFI_C_W__W 8 +#define ORX_FWP_PFI_C_W__M 0xFF +#define ORX_FWP_PFI_C_W__PRE 0x5C +#define ORX_FWP_PFI_C_W_RATE_2048KBPS 0x5C +#define ORX_FWP_PFI_C_W_RATE_1544KBPS 0x64 +#define ORX_FWP_PFI_C_W_RATE_3088KBPS 0x50 + + +#define ORX_FWP_KR1_AMP_R__A 0x2020017 +#define ORX_FWP_KR1_AMP_R__W 9 +#define ORX_FWP_KR1_AMP_R__M 0x1FF +#define ORX_FWP_KR1_AMP_R__PRE 0x0 + +#define ORX_FWP_KR1_LDT_W__A 0x2020018 +#define ORX_FWP_KR1_LDT_W__W 3 +#define ORX_FWP_KR1_LDT_W__M 0x7 +#define ORX_FWP_KR1_LDT_W__PRE 0x2 +#define ORX_FWP_SRC_DGN_W__A 0x2020019 +#define ORX_FWP_SRC_DGN_W__W 16 +#define ORX_FWP_SRC_DGN_W__M 0xFFFF +#define ORX_FWP_SRC_DGN_W__PRE 0x1FF + +#define ORX_FWP_SRC_DGN_W_MANT__B 0 +#define ORX_FWP_SRC_DGN_W_MANT__W 9 +#define ORX_FWP_SRC_DGN_W_MANT__M 0x1FF +#define ORX_FWP_SRC_DGN_W_MANT__PRE 0x1FF + +#define ORX_FWP_SRC_DGN_W_EXP__B 12 +#define ORX_FWP_SRC_DGN_W_EXP__W 4 +#define ORX_FWP_SRC_DGN_W_EXP__M 0xF000 +#define ORX_FWP_SRC_DGN_W_EXP__PRE 0x0 + + +#define ORX_FWP_NYQ_ADR_W__A 0x202001A +#define ORX_FWP_NYQ_ADR_W__W 5 +#define ORX_FWP_NYQ_ADR_W__M 0x1F +#define ORX_FWP_NYQ_ADR_W__PRE 0x1F + +#define ORX_FWP_NYQ_COF_RW__A 0x202001B +#define ORX_FWP_NYQ_COF_RW__W 10 +#define ORX_FWP_NYQ_COF_RW__M 0x3FF +#define ORX_FWP_NYQ_COF_RW__PRE 0x0 + +#define ORX_FWP_IQM_FRQ_W__A 0x202001C +#define ORX_FWP_IQM_FRQ_W__W 16 +#define ORX_FWP_IQM_FRQ_W__M 0xFFFF +#define ORX_FWP_IQM_FRQ_W__PRE 0x4301 + + + +#define ORX_EQU_COMM_EXEC__A 0x2030000 +#define ORX_EQU_COMM_EXEC__W 2 +#define ORX_EQU_COMM_EXEC__M 0x3 +#define ORX_EQU_COMM_EXEC__PRE 0x0 +#define ORX_EQU_COMM_EXEC_STOP 0x0 +#define ORX_EQU_COMM_EXEC_ACTIVE 0x1 +#define ORX_EQU_COMM_EXEC_HOLD 0x2 + +#define ORX_EQU_COMM_MB__A 0x2030002 +#define ORX_EQU_COMM_MB__W 8 +#define ORX_EQU_COMM_MB__M 0xFF +#define ORX_EQU_COMM_MB__PRE 0x0 +#define ORX_EQU_COMM_MB_CTL__B 0 +#define ORX_EQU_COMM_MB_CTL__W 1 +#define ORX_EQU_COMM_MB_CTL__M 0x1 +#define ORX_EQU_COMM_MB_CTL__PRE 0x0 +#define ORX_EQU_COMM_MB_CTL_OFF 0x0 +#define ORX_EQU_COMM_MB_CTL_ON 0x1 +#define ORX_EQU_COMM_MB_OBS__B 1 +#define ORX_EQU_COMM_MB_OBS__W 1 +#define ORX_EQU_COMM_MB_OBS__M 0x2 +#define ORX_EQU_COMM_MB_OBS__PRE 0x0 +#define ORX_EQU_COMM_MB_OBS_OFF 0x0 +#define ORX_EQU_COMM_MB_OBS_ON 0x2 + +#define ORX_EQU_COMM_MB_CTL_MUX__B 2 +#define ORX_EQU_COMM_MB_CTL_MUX__W 3 +#define ORX_EQU_COMM_MB_CTL_MUX__M 0x1C +#define ORX_EQU_COMM_MB_CTL_MUX__PRE 0x0 + +#define ORX_EQU_COMM_MB_OBS_MUX__B 5 +#define ORX_EQU_COMM_MB_OBS_MUX__W 3 +#define ORX_EQU_COMM_MB_OBS_MUX__M 0xE0 +#define ORX_EQU_COMM_MB_OBS_MUX__PRE 0x0 + +#define ORX_EQU_COMM_INT_REQ__A 0x2030003 +#define ORX_EQU_COMM_INT_REQ__W 1 +#define ORX_EQU_COMM_INT_REQ__M 0x1 +#define ORX_EQU_COMM_INT_REQ__PRE 0x0 +#define ORX_EQU_COMM_INT_STA__A 0x2030005 +#define ORX_EQU_COMM_INT_STA__W 2 +#define ORX_EQU_COMM_INT_STA__M 0x3 +#define ORX_EQU_COMM_INT_STA__PRE 0x0 + +#define ORX_EQU_COMM_INT_STA_FFF_READ__B 0 +#define ORX_EQU_COMM_INT_STA_FFF_READ__W 1 +#define ORX_EQU_COMM_INT_STA_FFF_READ__M 0x1 +#define ORX_EQU_COMM_INT_STA_FFF_READ__PRE 0x0 + +#define ORX_EQU_COMM_INT_STA_FBF_READ__B 1 +#define ORX_EQU_COMM_INT_STA_FBF_READ__W 1 +#define ORX_EQU_COMM_INT_STA_FBF_READ__M 0x2 +#define ORX_EQU_COMM_INT_STA_FBF_READ__PRE 0x0 + +#define ORX_EQU_COMM_INT_MSK__A 0x2030006 +#define ORX_EQU_COMM_INT_MSK__W 2 +#define ORX_EQU_COMM_INT_MSK__M 0x3 +#define ORX_EQU_COMM_INT_MSK__PRE 0x0 +#define ORX_EQU_COMM_INT_MSK_FFF_READ__B 0 +#define ORX_EQU_COMM_INT_MSK_FFF_READ__W 1 +#define ORX_EQU_COMM_INT_MSK_FFF_READ__M 0x1 +#define ORX_EQU_COMM_INT_MSK_FFF_READ__PRE 0x0 +#define ORX_EQU_COMM_INT_MSK_FBF_READ__B 1 +#define ORX_EQU_COMM_INT_MSK_FBF_READ__W 1 +#define ORX_EQU_COMM_INT_MSK_FBF_READ__M 0x2 +#define ORX_EQU_COMM_INT_MSK_FBF_READ__PRE 0x0 + +#define ORX_EQU_COMM_INT_STM__A 0x2030007 +#define ORX_EQU_COMM_INT_STM__W 2 +#define ORX_EQU_COMM_INT_STM__M 0x3 +#define ORX_EQU_COMM_INT_STM__PRE 0x0 +#define ORX_EQU_COMM_INT_STM_FFF_READ__B 0 +#define ORX_EQU_COMM_INT_STM_FFF_READ__W 1 +#define ORX_EQU_COMM_INT_STM_FFF_READ__M 0x1 +#define ORX_EQU_COMM_INT_STM_FFF_READ__PRE 0x0 +#define ORX_EQU_COMM_INT_STM_FBF_READ__B 1 +#define ORX_EQU_COMM_INT_STM_FBF_READ__W 1 +#define ORX_EQU_COMM_INT_STM_FBF_READ__M 0x2 +#define ORX_EQU_COMM_INT_STM_FBF_READ__PRE 0x0 + + +#define ORX_EQU_FFF_SCL_W__A 0x2030010 +#define ORX_EQU_FFF_SCL_W__W 1 +#define ORX_EQU_FFF_SCL_W__M 0x1 +#define ORX_EQU_FFF_SCL_W__PRE 0x0 +#define ORX_EQU_FFF_SCL_W_SCALE_GAIN_1 0x0 +#define ORX_EQU_FFF_SCL_W_SCALE_GAIN_2 0x1 + + +#define ORX_EQU_FFF_UPD_W__A 0x2030011 +#define ORX_EQU_FFF_UPD_W__W 1 +#define ORX_EQU_FFF_UPD_W__M 0x1 +#define ORX_EQU_FFF_UPD_W__PRE 0x0 +#define ORX_EQU_FFF_UPD_W_NO_UPDATE 0x0 +#define ORX_EQU_FFF_UPD_W_LMS_UPDATE 0x1 + + +#define ORX_EQU_FFF_STP_W__A 0x2030012 +#define ORX_EQU_FFF_STP_W__W 3 +#define ORX_EQU_FFF_STP_W__M 0x7 +#define ORX_EQU_FFF_STP_W__PRE 0x2 + +#define ORX_EQU_FFF_LEA_W__A 0x2030013 +#define ORX_EQU_FFF_LEA_W__W 4 +#define ORX_EQU_FFF_LEA_W__M 0xF +#define ORX_EQU_FFF_LEA_W__PRE 0x4 + +#define ORX_EQU_FFF_RWT_W__A 0x2030014 +#define ORX_EQU_FFF_RWT_W__W 2 +#define ORX_EQU_FFF_RWT_W__M 0x3 +#define ORX_EQU_FFF_RWT_W__PRE 0x0 + +#define ORX_EQU_FFF_C0RE_RW__A 0x2030015 +#define ORX_EQU_FFF_C0RE_RW__W 12 +#define ORX_EQU_FFF_C0RE_RW__M 0xFFF +#define ORX_EQU_FFF_C0RE_RW__PRE 0x0 + +#define ORX_EQU_FFF_C0IM_RW__A 0x2030016 +#define ORX_EQU_FFF_C0IM_RW__W 12 +#define ORX_EQU_FFF_C0IM_RW__M 0xFFF +#define ORX_EQU_FFF_C0IM_RW__PRE 0x0 + +#define ORX_EQU_FFF_C1RE_RW__A 0x2030017 +#define ORX_EQU_FFF_C1RE_RW__W 12 +#define ORX_EQU_FFF_C1RE_RW__M 0xFFF +#define ORX_EQU_FFF_C1RE_RW__PRE 0x0 + +#define ORX_EQU_FFF_C1IM_RW__A 0x2030018 +#define ORX_EQU_FFF_C1IM_RW__W 12 +#define ORX_EQU_FFF_C1IM_RW__M 0xFFF +#define ORX_EQU_FFF_C1IM_RW__PRE 0x0 + +#define ORX_EQU_FFF_C2RE_RW__A 0x2030019 +#define ORX_EQU_FFF_C2RE_RW__W 12 +#define ORX_EQU_FFF_C2RE_RW__M 0xFFF +#define ORX_EQU_FFF_C2RE_RW__PRE 0x0 + +#define ORX_EQU_FFF_C2IM_RW__A 0x203001A +#define ORX_EQU_FFF_C2IM_RW__W 12 +#define ORX_EQU_FFF_C2IM_RW__M 0xFFF +#define ORX_EQU_FFF_C2IM_RW__PRE 0x0 + +#define ORX_EQU_FFF_C3RE_RW__A 0x203001B +#define ORX_EQU_FFF_C3RE_RW__W 12 +#define ORX_EQU_FFF_C3RE_RW__M 0xFFF +#define ORX_EQU_FFF_C3RE_RW__PRE 0x0 + +#define ORX_EQU_FFF_C3IM_RW__A 0x203001C +#define ORX_EQU_FFF_C3IM_RW__W 12 +#define ORX_EQU_FFF_C3IM_RW__M 0xFFF +#define ORX_EQU_FFF_C3IM_RW__PRE 0x0 + +#define ORX_EQU_FFF_C4RE_RW__A 0x203001D +#define ORX_EQU_FFF_C4RE_RW__W 12 +#define ORX_EQU_FFF_C4RE_RW__M 0xFFF +#define ORX_EQU_FFF_C4RE_RW__PRE 0x400 + +#define ORX_EQU_FFF_C4IM_RW__A 0x203001E +#define ORX_EQU_FFF_C4IM_RW__W 12 +#define ORX_EQU_FFF_C4IM_RW__M 0xFFF +#define ORX_EQU_FFF_C4IM_RW__PRE 0x0 + +#define ORX_EQU_FFF_C5RE_RW__A 0x203001F +#define ORX_EQU_FFF_C5RE_RW__W 12 +#define ORX_EQU_FFF_C5RE_RW__M 0xFFF +#define ORX_EQU_FFF_C5RE_RW__PRE 0x0 + +#define ORX_EQU_FFF_C5IM_RW__A 0x2030020 +#define ORX_EQU_FFF_C5IM_RW__W 12 +#define ORX_EQU_FFF_C5IM_RW__M 0xFFF +#define ORX_EQU_FFF_C5IM_RW__PRE 0x0 + +#define ORX_EQU_FFF_C6RE_RW__A 0x2030021 +#define ORX_EQU_FFF_C6RE_RW__W 12 +#define ORX_EQU_FFF_C6RE_RW__M 0xFFF +#define ORX_EQU_FFF_C6RE_RW__PRE 0x0 + +#define ORX_EQU_FFF_C6IM_RW__A 0x2030022 +#define ORX_EQU_FFF_C6IM_RW__W 12 +#define ORX_EQU_FFF_C6IM_RW__M 0xFFF +#define ORX_EQU_FFF_C6IM_RW__PRE 0x0 + +#define ORX_EQU_FFF_C7RE_RW__A 0x2030023 +#define ORX_EQU_FFF_C7RE_RW__W 12 +#define ORX_EQU_FFF_C7RE_RW__M 0xFFF +#define ORX_EQU_FFF_C7RE_RW__PRE 0x0 + +#define ORX_EQU_FFF_C7IM_RW__A 0x2030024 +#define ORX_EQU_FFF_C7IM_RW__W 12 +#define ORX_EQU_FFF_C7IM_RW__M 0xFFF +#define ORX_EQU_FFF_C7IM_RW__PRE 0x0 + +#define ORX_EQU_FFF_C8RE_RW__A 0x2030025 +#define ORX_EQU_FFF_C8RE_RW__W 12 +#define ORX_EQU_FFF_C8RE_RW__M 0xFFF +#define ORX_EQU_FFF_C8RE_RW__PRE 0x0 + +#define ORX_EQU_FFF_C8IM_RW__A 0x2030026 +#define ORX_EQU_FFF_C8IM_RW__W 12 +#define ORX_EQU_FFF_C8IM_RW__M 0xFFF +#define ORX_EQU_FFF_C8IM_RW__PRE 0x0 + +#define ORX_EQU_FFF_C9RE_RW__A 0x2030027 +#define ORX_EQU_FFF_C9RE_RW__W 12 +#define ORX_EQU_FFF_C9RE_RW__M 0xFFF +#define ORX_EQU_FFF_C9RE_RW__PRE 0x0 + +#define ORX_EQU_FFF_C9IM_RW__A 0x2030028 +#define ORX_EQU_FFF_C9IM_RW__W 12 +#define ORX_EQU_FFF_C9IM_RW__M 0xFFF +#define ORX_EQU_FFF_C9IM_RW__PRE 0x0 + +#define ORX_EQU_FFF_C10RE_RW__A 0x2030029 +#define ORX_EQU_FFF_C10RE_RW__W 12 +#define ORX_EQU_FFF_C10RE_RW__M 0xFFF +#define ORX_EQU_FFF_C10RE_RW__PRE 0x0 + +#define ORX_EQU_FFF_C10IM_RW__A 0x203002A +#define ORX_EQU_FFF_C10IM_RW__W 12 +#define ORX_EQU_FFF_C10IM_RW__M 0xFFF +#define ORX_EQU_FFF_C10IM_RW__PRE 0x0 + +#define ORX_EQU_MXB_SEL_W__A 0x203002B +#define ORX_EQU_MXB_SEL_W__W 1 +#define ORX_EQU_MXB_SEL_W__M 0x1 +#define ORX_EQU_MXB_SEL_W__PRE 0x0 +#define ORX_EQU_MXB_SEL_W_UNDECIDED_SYMBOLS 0x0 +#define ORX_EQU_MXB_SEL_W_DECIDED_SYMBOLS 0x1 + + +#define ORX_EQU_FBF_UPD_W__A 0x203002C +#define ORX_EQU_FBF_UPD_W__W 1 +#define ORX_EQU_FBF_UPD_W__M 0x1 +#define ORX_EQU_FBF_UPD_W__PRE 0x0 +#define ORX_EQU_FBF_UPD_W_NO_UPDATE 0x0 +#define ORX_EQU_FBF_UPD_W_LMS_UPDATE 0x1 + + +#define ORX_EQU_FBF_STP_W__A 0x203002D +#define ORX_EQU_FBF_STP_W__W 3 +#define ORX_EQU_FBF_STP_W__M 0x7 +#define ORX_EQU_FBF_STP_W__PRE 0x2 + +#define ORX_EQU_FBF_LEA_W__A 0x203002E +#define ORX_EQU_FBF_LEA_W__W 4 +#define ORX_EQU_FBF_LEA_W__M 0xF +#define ORX_EQU_FBF_LEA_W__PRE 0x4 + +#define ORX_EQU_FBF_RWT_W__A 0x203002F +#define ORX_EQU_FBF_RWT_W__W 2 +#define ORX_EQU_FBF_RWT_W__M 0x3 +#define ORX_EQU_FBF_RWT_W__PRE 0x0 + +#define ORX_EQU_FBF_C0RE_RW__A 0x2030030 +#define ORX_EQU_FBF_C0RE_RW__W 12 +#define ORX_EQU_FBF_C0RE_RW__M 0xFFF +#define ORX_EQU_FBF_C0RE_RW__PRE 0x0 + +#define ORX_EQU_FBF_C0IM_RW__A 0x2030031 +#define ORX_EQU_FBF_C0IM_RW__W 12 +#define ORX_EQU_FBF_C0IM_RW__M 0xFFF +#define ORX_EQU_FBF_C0IM_RW__PRE 0x0 + +#define ORX_EQU_FBF_C1RE_RW__A 0x2030032 +#define ORX_EQU_FBF_C1RE_RW__W 12 +#define ORX_EQU_FBF_C1RE_RW__M 0xFFF +#define ORX_EQU_FBF_C1RE_RW__PRE 0x0 + +#define ORX_EQU_FBF_C1IM_RW__A 0x2030033 +#define ORX_EQU_FBF_C1IM_RW__W 12 +#define ORX_EQU_FBF_C1IM_RW__M 0xFFF +#define ORX_EQU_FBF_C1IM_RW__PRE 0x0 + +#define ORX_EQU_FBF_C2RE_RW__A 0x2030034 +#define ORX_EQU_FBF_C2RE_RW__W 12 +#define ORX_EQU_FBF_C2RE_RW__M 0xFFF +#define ORX_EQU_FBF_C2RE_RW__PRE 0x0 + +#define ORX_EQU_FBF_C2IM_RW__A 0x2030035 +#define ORX_EQU_FBF_C2IM_RW__W 12 +#define ORX_EQU_FBF_C2IM_RW__M 0xFFF +#define ORX_EQU_FBF_C2IM_RW__PRE 0x0 + +#define ORX_EQU_FBF_C3RE_RW__A 0x2030036 +#define ORX_EQU_FBF_C3RE_RW__W 12 +#define ORX_EQU_FBF_C3RE_RW__M 0xFFF +#define ORX_EQU_FBF_C3RE_RW__PRE 0x0 + +#define ORX_EQU_FBF_C3IM_RW__A 0x2030037 +#define ORX_EQU_FBF_C3IM_RW__W 12 +#define ORX_EQU_FBF_C3IM_RW__M 0xFFF +#define ORX_EQU_FBF_C3IM_RW__PRE 0x0 + +#define ORX_EQU_FBF_C4RE_RW__A 0x2030038 +#define ORX_EQU_FBF_C4RE_RW__W 12 +#define ORX_EQU_FBF_C4RE_RW__M 0xFFF +#define ORX_EQU_FBF_C4RE_RW__PRE 0x0 + +#define ORX_EQU_FBF_C4IM_RW__A 0x2030039 +#define ORX_EQU_FBF_C4IM_RW__W 12 +#define ORX_EQU_FBF_C4IM_RW__M 0xFFF +#define ORX_EQU_FBF_C4IM_RW__PRE 0x0 + +#define ORX_EQU_FBF_C5RE_RW__A 0x203003A +#define ORX_EQU_FBF_C5RE_RW__W 12 +#define ORX_EQU_FBF_C5RE_RW__M 0xFFF +#define ORX_EQU_FBF_C5RE_RW__PRE 0x0 + +#define ORX_EQU_FBF_C5IM_RW__A 0x203003B +#define ORX_EQU_FBF_C5IM_RW__W 12 +#define ORX_EQU_FBF_C5IM_RW__M 0xFFF +#define ORX_EQU_FBF_C5IM_RW__PRE 0x0 + +#define ORX_EQU_ERR_SEL_W__A 0x203003C +#define ORX_EQU_ERR_SEL_W__W 1 +#define ORX_EQU_ERR_SEL_W__M 0x1 +#define ORX_EQU_ERR_SEL_W__PRE 0x0 +#define ORX_EQU_ERR_SEL_W_CMA_ERROR 0x0 +#define ORX_EQU_ERR_SEL_W_DDA_ERROR 0x1 + + +#define ORX_EQU_ERR_TIS_W__A 0x203003D +#define ORX_EQU_ERR_TIS_W__W 1 +#define ORX_EQU_ERR_TIS_W__M 0x1 +#define ORX_EQU_ERR_TIS_W__PRE 0x0 +#define ORX_EQU_ERR_TIS_W_CMA_SIGNALS 0x0 +#define ORX_EQU_ERR_TIS_W_DDA_SIGNALS 0x1 + + +#define ORX_EQU_ERR_EDI_R__A 0x203003E +#define ORX_EQU_ERR_EDI_R__W 5 +#define ORX_EQU_ERR_EDI_R__M 0x1F +#define ORX_EQU_ERR_EDI_R__PRE 0xF + +#define ORX_EQU_ERR_EDQ_R__A 0x203003F +#define ORX_EQU_ERR_EDQ_R__W 5 +#define ORX_EQU_ERR_EDQ_R__M 0x1F +#define ORX_EQU_ERR_EDQ_R__PRE 0xF + +#define ORX_EQU_ERR_ECI_R__A 0x2030040 +#define ORX_EQU_ERR_ECI_R__W 5 +#define ORX_EQU_ERR_ECI_R__M 0x1F +#define ORX_EQU_ERR_ECI_R__PRE 0xF + +#define ORX_EQU_ERR_ECQ_R__A 0x2030041 +#define ORX_EQU_ERR_ECQ_R__W 5 +#define ORX_EQU_ERR_ECQ_R__M 0x1F +#define ORX_EQU_ERR_ECQ_R__PRE 0xF + +#define ORX_EQU_MER_MER_R__A 0x2030042 +#define ORX_EQU_MER_MER_R__W 6 +#define ORX_EQU_MER_MER_R__M 0x3F +#define ORX_EQU_MER_MER_R__PRE 0x3F + +#define ORX_EQU_MER_LDT_W__A 0x2030043 +#define ORX_EQU_MER_LDT_W__W 3 +#define ORX_EQU_MER_LDT_W__M 0x7 +#define ORX_EQU_MER_LDT_W__PRE 0x4 + +#define ORX_EQU_SYN_LEN_W__A 0x2030044 +#define ORX_EQU_SYN_LEN_W__W 16 +#define ORX_EQU_SYN_LEN_W__M 0xFFFF +#define ORX_EQU_SYN_LEN_W__PRE 0x0 + + + +#define ORX_DDC_COMM_EXEC__A 0x2040000 +#define ORX_DDC_COMM_EXEC__W 2 +#define ORX_DDC_COMM_EXEC__M 0x3 +#define ORX_DDC_COMM_EXEC__PRE 0x0 +#define ORX_DDC_COMM_EXEC_STOP 0x0 +#define ORX_DDC_COMM_EXEC_ACTIVE 0x1 +#define ORX_DDC_COMM_EXEC_HOLD 0x2 + +#define ORX_DDC_COMM_MB__A 0x2040002 +#define ORX_DDC_COMM_MB__W 6 +#define ORX_DDC_COMM_MB__M 0x3F +#define ORX_DDC_COMM_MB__PRE 0x0 +#define ORX_DDC_COMM_MB_CTL__B 0 +#define ORX_DDC_COMM_MB_CTL__W 1 +#define ORX_DDC_COMM_MB_CTL__M 0x1 +#define ORX_DDC_COMM_MB_CTL__PRE 0x0 +#define ORX_DDC_COMM_MB_CTL_OFF 0x0 +#define ORX_DDC_COMM_MB_CTL_ON 0x1 +#define ORX_DDC_COMM_MB_OBS__B 1 +#define ORX_DDC_COMM_MB_OBS__W 1 +#define ORX_DDC_COMM_MB_OBS__M 0x2 +#define ORX_DDC_COMM_MB_OBS__PRE 0x0 +#define ORX_DDC_COMM_MB_OBS_OFF 0x0 +#define ORX_DDC_COMM_MB_OBS_ON 0x2 + +#define ORX_DDC_COMM_MB_CTL_MUX__B 2 +#define ORX_DDC_COMM_MB_CTL_MUX__W 2 +#define ORX_DDC_COMM_MB_CTL_MUX__M 0xC +#define ORX_DDC_COMM_MB_CTL_MUX__PRE 0x0 + +#define ORX_DDC_COMM_MB_OBS_MUX__B 4 +#define ORX_DDC_COMM_MB_OBS_MUX__W 2 +#define ORX_DDC_COMM_MB_OBS_MUX__M 0x30 +#define ORX_DDC_COMM_MB_OBS_MUX__PRE 0x0 + +#define ORX_DDC_COMM_INT_REQ__A 0x2040003 +#define ORX_DDC_COMM_INT_REQ__W 1 +#define ORX_DDC_COMM_INT_REQ__M 0x1 +#define ORX_DDC_COMM_INT_REQ__PRE 0x0 +#define ORX_DDC_COMM_INT_STA__A 0x2040005 +#define ORX_DDC_COMM_INT_STA__W 1 +#define ORX_DDC_COMM_INT_STA__M 0x1 +#define ORX_DDC_COMM_INT_STA__PRE 0x0 +#define ORX_DDC_COMM_INT_MSK__A 0x2040006 +#define ORX_DDC_COMM_INT_MSK__W 1 +#define ORX_DDC_COMM_INT_MSK__M 0x1 +#define ORX_DDC_COMM_INT_MSK__PRE 0x0 +#define ORX_DDC_COMM_INT_STM__A 0x2040007 +#define ORX_DDC_COMM_INT_STM__W 1 +#define ORX_DDC_COMM_INT_STM__M 0x1 +#define ORX_DDC_COMM_INT_STM__PRE 0x0 +#define ORX_DDC_DEC_MAP_W__A 0x2040010 +#define ORX_DDC_DEC_MAP_W__W 9 +#define ORX_DDC_DEC_MAP_W__M 0x1FF +#define ORX_DDC_DEC_MAP_W__PRE 0x178 + +#define ORX_DDC_DEC_MAP_W_QUADR0__B 0 +#define ORX_DDC_DEC_MAP_W_QUADR0__W 2 +#define ORX_DDC_DEC_MAP_W_QUADR0__M 0x3 +#define ORX_DDC_DEC_MAP_W_QUADR0__PRE 0x0 +#define ORX_DDC_DEC_MAP_W_QUADR0_ROTATE_DEFAULT 0x0 +#define ORX_DDC_DEC_MAP_W_QUADR0_ROTATE_ALTERNATE 0x0 + +#define ORX_DDC_DEC_MAP_W_QUADR1__B 2 +#define ORX_DDC_DEC_MAP_W_QUADR1__W 2 +#define ORX_DDC_DEC_MAP_W_QUADR1__M 0xC +#define ORX_DDC_DEC_MAP_W_QUADR1__PRE 0x8 +#define ORX_DDC_DEC_MAP_W_QUADR1_ROTATE_DEFAULT 0x8 +#define ORX_DDC_DEC_MAP_W_QUADR1_ROTATE_ALTERNATE 0x4 + +#define ORX_DDC_DEC_MAP_W_QUADR2__B 4 +#define ORX_DDC_DEC_MAP_W_QUADR2__W 2 +#define ORX_DDC_DEC_MAP_W_QUADR2__M 0x30 +#define ORX_DDC_DEC_MAP_W_QUADR2__PRE 0x30 +#define ORX_DDC_DEC_MAP_W_QUADR2_ROTATE_DEFAULT 0x30 +#define ORX_DDC_DEC_MAP_W_QUADR2_ROTATE_ALTERNATE 0x30 + +#define ORX_DDC_DEC_MAP_W_QUADR3__B 6 +#define ORX_DDC_DEC_MAP_W_QUADR3__W 2 +#define ORX_DDC_DEC_MAP_W_QUADR3__M 0xC0 +#define ORX_DDC_DEC_MAP_W_QUADR3__PRE 0x40 +#define ORX_DDC_DEC_MAP_W_QUADR3_ROTATE_DEFAULT 0x40 +#define ORX_DDC_DEC_MAP_W_QUADR3_ROTATE_ALTERNATE 0x80 +#define ORX_DDC_DEC_MAP_W_DIFF_DECOD__B 8 +#define ORX_DDC_DEC_MAP_W_DIFF_DECOD__W 1 +#define ORX_DDC_DEC_MAP_W_DIFF_DECOD__M 0x100 +#define ORX_DDC_DEC_MAP_W_DIFF_DECOD__PRE 0x100 +#define ORX_DDC_DEC_MAP_W_DIFF_DECOD_COHERENT_DECODING 0x0 +#define ORX_DDC_DEC_MAP_W_DIFF_DECOD_DIFF_DECODING 0x100 + +#define ORX_DDC_OFO_SET_W__A 0x2040011 +#define ORX_DDC_OFO_SET_W__W 16 +#define ORX_DDC_OFO_SET_W__M 0xFFFF +#define ORX_DDC_OFO_SET_W__PRE 0x1402 + +#define ORX_DDC_OFO_SET_W_PHASE__B 0 +#define ORX_DDC_OFO_SET_W_PHASE__W 7 +#define ORX_DDC_OFO_SET_W_PHASE__M 0x7F +#define ORX_DDC_OFO_SET_W_PHASE__PRE 0x2 + +#define ORX_DDC_OFO_SET_W_CRXHITIME__B 7 +#define ORX_DDC_OFO_SET_W_CRXHITIME__W 7 +#define ORX_DDC_OFO_SET_W_CRXHITIME__M 0x3F80 +#define ORX_DDC_OFO_SET_W_CRXHITIME__PRE 0x1400 + +#define ORX_DDC_OFO_SET_W_CRXINV__B 14 +#define ORX_DDC_OFO_SET_W_CRXINV__W 1 +#define ORX_DDC_OFO_SET_W_CRXINV__M 0x4000 +#define ORX_DDC_OFO_SET_W_CRXINV__PRE 0x0 + +#define ORX_DDC_OFO_SET_W_DISABLE__B 15 +#define ORX_DDC_OFO_SET_W_DISABLE__W 1 +#define ORX_DDC_OFO_SET_W_DISABLE__M 0x8000 +#define ORX_DDC_OFO_SET_W_DISABLE__PRE 0x0 + + + +#define ORX_CON_COMM_EXEC__A 0x2050000 +#define ORX_CON_COMM_EXEC__W 2 +#define ORX_CON_COMM_EXEC__M 0x3 +#define ORX_CON_COMM_EXEC__PRE 0x0 +#define ORX_CON_COMM_EXEC_STOP 0x0 +#define ORX_CON_COMM_EXEC_ACTIVE 0x1 +#define ORX_CON_COMM_EXEC_HOLD 0x2 + +#define ORX_CON_LDT_W__A 0x2050010 +#define ORX_CON_LDT_W__W 3 +#define ORX_CON_LDT_W__M 0x7 +#define ORX_CON_LDT_W__PRE 0x3 + +#define ORX_CON_LDT_W_CON_LDT_W__B 0 +#define ORX_CON_LDT_W_CON_LDT_W__W 3 +#define ORX_CON_LDT_W_CON_LDT_W__M 0x7 +#define ORX_CON_LDT_W_CON_LDT_W__PRE 0x3 + +#define ORX_CON_RST_W__A 0x2050011 +#define ORX_CON_RST_W__W 4 +#define ORX_CON_RST_W__M 0xF +#define ORX_CON_RST_W__PRE 0x0 + +#define ORX_CON_RST_W_CPH__B 0 +#define ORX_CON_RST_W_CPH__W 1 +#define ORX_CON_RST_W_CPH__M 0x1 +#define ORX_CON_RST_W_CPH__PRE 0x0 + +#define ORX_CON_RST_W_CTI__B 1 +#define ORX_CON_RST_W_CTI__W 1 +#define ORX_CON_RST_W_CTI__M 0x2 +#define ORX_CON_RST_W_CTI__PRE 0x0 + +#define ORX_CON_RST_W_KRN__B 2 +#define ORX_CON_RST_W_KRN__W 1 +#define ORX_CON_RST_W_KRN__M 0x4 +#define ORX_CON_RST_W_KRN__PRE 0x0 + +#define ORX_CON_RST_W_KRP__B 3 +#define ORX_CON_RST_W_KRP__W 1 +#define ORX_CON_RST_W_KRP__M 0x8 +#define ORX_CON_RST_W_KRP__PRE 0x0 + + +#define ORX_CON_CPH_PHI_R__A 0x2050012 +#define ORX_CON_CPH_PHI_R__W 16 +#define ORX_CON_CPH_PHI_R__M 0xFFFF +#define ORX_CON_CPH_PHI_R__PRE 0x0 + +#define ORX_CON_CPH_FRQ_R__A 0x2050013 +#define ORX_CON_CPH_FRQ_R__W 16 +#define ORX_CON_CPH_FRQ_R__M 0xFFFF +#define ORX_CON_CPH_FRQ_R__PRE 0x0 + +#define ORX_CON_CPH_AMP_R__A 0x2050014 +#define ORX_CON_CPH_AMP_R__W 16 +#define ORX_CON_CPH_AMP_R__M 0xFFFF +#define ORX_CON_CPH_AMP_R__PRE 0x0 + +#define ORX_CON_CPH_KDF_W__A 0x2050015 +#define ORX_CON_CPH_KDF_W__W 4 +#define ORX_CON_CPH_KDF_W__M 0xF +#define ORX_CON_CPH_KDF_W__PRE 0x0 + +#define ORX_CON_CPH_KPF_W__A 0x2050016 +#define ORX_CON_CPH_KPF_W__W 4 +#define ORX_CON_CPH_KPF_W__M 0xF +#define ORX_CON_CPH_KPF_W__PRE 0x0 + +#define ORX_CON_CPH_KIF_W__A 0x2050017 +#define ORX_CON_CPH_KIF_W__W 4 +#define ORX_CON_CPH_KIF_W__M 0xF +#define ORX_CON_CPH_KIF_W__PRE 0x0 +#define ORX_CON_CPH_APT_W__A 0x2050018 +#define ORX_CON_CPH_APT_W__W 16 +#define ORX_CON_CPH_APT_W__M 0xFFFF +#define ORX_CON_CPH_APT_W__PRE 0x804 + +#define ORX_CON_CPH_APT_W_PTH__B 0 +#define ORX_CON_CPH_APT_W_PTH__W 8 +#define ORX_CON_CPH_APT_W_PTH__M 0xFF +#define ORX_CON_CPH_APT_W_PTH__PRE 0x4 + +#define ORX_CON_CPH_APT_W_ATH__B 8 +#define ORX_CON_CPH_APT_W_ATH__W 8 +#define ORX_CON_CPH_APT_W_ATH__M 0xFF00 +#define ORX_CON_CPH_APT_W_ATH__PRE 0x800 + +#define ORX_CON_CPH_WLC_W__A 0x2050019 +#define ORX_CON_CPH_WLC_W__W 8 +#define ORX_CON_CPH_WLC_W__M 0xFF +#define ORX_CON_CPH_WLC_W__PRE 0x81 + +#define ORX_CON_CPH_WLC_W_LATC__B 0 +#define ORX_CON_CPH_WLC_W_LATC__W 4 +#define ORX_CON_CPH_WLC_W_LATC__M 0xF +#define ORX_CON_CPH_WLC_W_LATC__PRE 0x1 + +#define ORX_CON_CPH_WLC_W_WLIM__B 4 +#define ORX_CON_CPH_WLC_W_WLIM__W 4 +#define ORX_CON_CPH_WLC_W_WLIM__M 0xF0 +#define ORX_CON_CPH_WLC_W_WLIM__PRE 0x80 + + +#define ORX_CON_CPH_DLY_W__A 0x205001A +#define ORX_CON_CPH_DLY_W__W 3 +#define ORX_CON_CPH_DLY_W__M 0x7 +#define ORX_CON_CPH_DLY_W__PRE 0x4 + +#define ORX_CON_CPH_TCL_W__A 0x205001B +#define ORX_CON_CPH_TCL_W__W 3 +#define ORX_CON_CPH_TCL_W__M 0x7 +#define ORX_CON_CPH_TCL_W__PRE 0x3 + +#define ORX_CON_KRP_AMP_R__A 0x205001C +#define ORX_CON_KRP_AMP_R__W 9 +#define ORX_CON_KRP_AMP_R__M 0x1FF +#define ORX_CON_KRP_AMP_R__PRE 0x0 + +#define ORX_CON_KRN_AMP_R__A 0x205001D +#define ORX_CON_KRN_AMP_R__W 9 +#define ORX_CON_KRN_AMP_R__M 0x1FF +#define ORX_CON_KRN_AMP_R__PRE 0x0 + +#define ORX_CON_CTI_DTI_R__A 0x205001E +#define ORX_CON_CTI_DTI_R__W 16 +#define ORX_CON_CTI_DTI_R__M 0xFFFF +#define ORX_CON_CTI_DTI_R__PRE 0x0 + +#define ORX_CON_CTI_KDT_W__A 0x205001F +#define ORX_CON_CTI_KDT_W__W 4 +#define ORX_CON_CTI_KDT_W__M 0xF +#define ORX_CON_CTI_KDT_W__PRE 0x4 + +#define ORX_CON_CTI_KPT_W__A 0x2050020 +#define ORX_CON_CTI_KPT_W__W 4 +#define ORX_CON_CTI_KPT_W__M 0xF +#define ORX_CON_CTI_KPT_W__PRE 0x3 + +#define ORX_CON_CTI_KIT_W__A 0x2050021 +#define ORX_CON_CTI_KIT_W__W 4 +#define ORX_CON_CTI_KIT_W__M 0xF +#define ORX_CON_CTI_KIT_W__PRE 0xB + +#define ORX_CON_CTI_TAT_W__A 0x2050022 +#define ORX_CON_CTI_TAT_W__W 4 +#define ORX_CON_CTI_TAT_W__M 0xF +#define ORX_CON_CTI_TAT_W__PRE 0x3 + + + +#define ORX_NSU_COMM_EXEC__A 0x2060000 +#define ORX_NSU_COMM_EXEC__W 2 +#define ORX_NSU_COMM_EXEC__M 0x3 +#define ORX_NSU_COMM_EXEC__PRE 0x0 +#define ORX_NSU_COMM_EXEC_STOP 0x0 +#define ORX_NSU_COMM_EXEC_ACTIVE 0x1 +#define ORX_NSU_COMM_EXEC_HOLD 0x2 + +#define ORX_NSU_AOX_STDBY_W__A 0x2060010 +#define ORX_NSU_AOX_STDBY_W__W 8 +#define ORX_NSU_AOX_STDBY_W__M 0xFF +#define ORX_NSU_AOX_STDBY_W__PRE 0x0 + +#define ORX_NSU_AOX_STDBY_W_STDBYADC__B 0 +#define ORX_NSU_AOX_STDBY_W_STDBYADC__W 1 +#define ORX_NSU_AOX_STDBY_W_STDBYADC__M 0x1 +#define ORX_NSU_AOX_STDBY_W_STDBYADC__PRE 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYADC_A1_ON 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYADC_A1_OFF 0x1 +#define ORX_NSU_AOX_STDBY_W_STDBYADC_A2_OFF 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON 0x1 + +#define ORX_NSU_AOX_STDBY_W_STDBYAMP__B 1 +#define ORX_NSU_AOX_STDBY_W_STDBYAMP__W 1 +#define ORX_NSU_AOX_STDBY_W_STDBYAMP__M 0x2 +#define ORX_NSU_AOX_STDBY_W_STDBYAMP__PRE 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYAMP_A1_ON 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYAMP_A1_OFF 0x2 +#define ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_OFF 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON 0x2 + +#define ORX_NSU_AOX_STDBY_W_STDBYBIAS__B 2 +#define ORX_NSU_AOX_STDBY_W_STDBYBIAS__W 1 +#define ORX_NSU_AOX_STDBY_W_STDBYBIAS__M 0x4 +#define ORX_NSU_AOX_STDBY_W_STDBYBIAS__PRE 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYBIAS_A1_ON 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYBIAS_A1_OFF 0x4 +#define ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_OFF 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON 0x4 + +#define ORX_NSU_AOX_STDBY_W_STDBYPLL__B 3 +#define ORX_NSU_AOX_STDBY_W_STDBYPLL__W 1 +#define ORX_NSU_AOX_STDBY_W_STDBYPLL__M 0x8 +#define ORX_NSU_AOX_STDBY_W_STDBYPLL__PRE 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYPLL_A1_ON 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYPLL_A1_OFF 0x8 +#define ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_OFF 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON 0x8 + +#define ORX_NSU_AOX_STDBY_W_STDBYPD__B 4 +#define ORX_NSU_AOX_STDBY_W_STDBYPD__W 1 +#define ORX_NSU_AOX_STDBY_W_STDBYPD__M 0x10 +#define ORX_NSU_AOX_STDBY_W_STDBYPD__PRE 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYPD_A1_ON 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYPD_A1_OFF 0x10 +#define ORX_NSU_AOX_STDBY_W_STDBYPD_A2_OFF 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON 0x10 + +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF__B 5 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF__W 1 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF__M 0x20 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF__PRE 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A1_ON 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A1_OFF 0x20 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_OFF 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON 0x20 + +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF__B 6 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF__W 1 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF__M 0x40 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF__PRE 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A1_ON 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A1_OFF 0x40 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_OFF 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON 0x40 + +#define ORX_NSU_AOX_STDBY_W_STDBYFLT__B 7 +#define ORX_NSU_AOX_STDBY_W_STDBYFLT__W 1 +#define ORX_NSU_AOX_STDBY_W_STDBYFLT__M 0x80 +#define ORX_NSU_AOX_STDBY_W_STDBYFLT__PRE 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYFLT_A1_ON 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYFLT_A1_OFF 0x80 +#define ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_OFF 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON 0x80 + + +#define ORX_NSU_AOX_LOFRQ_W__A 0x2060011 +#define ORX_NSU_AOX_LOFRQ_W__W 16 +#define ORX_NSU_AOX_LOFRQ_W__M 0xFFFF +#define ORX_NSU_AOX_LOFRQ_W__PRE 0x0 +#define ORX_NSU_AOX_LOMDE_W__A 0x2060012 +#define ORX_NSU_AOX_LOMDE_W__W 16 +#define ORX_NSU_AOX_LOMDE_W__M 0xFFFF +#define ORX_NSU_AOX_LOMDE_W__PRE 0x0 + +#define ORX_NSU_AOX_LOMDE_W_AOX_LOFRQ_EXT__B 0 +#define ORX_NSU_AOX_LOMDE_W_AOX_LOFRQ_EXT__W 8 +#define ORX_NSU_AOX_LOMDE_W_AOX_LOFRQ_EXT__M 0xFF +#define ORX_NSU_AOX_LOMDE_W_AOX_LOFRQ_EXT__PRE 0x0 + +#define ORX_NSU_AOX_LOMDE_W_RESET_VCO__B 13 +#define ORX_NSU_AOX_LOMDE_W_RESET_VCO__W 1 +#define ORX_NSU_AOX_LOMDE_W_RESET_VCO__M 0x2000 +#define ORX_NSU_AOX_LOMDE_W_RESET_VCO__PRE 0x0 + +#define ORX_NSU_AOX_LOMDE_W_PLL_DIV__B 14 +#define ORX_NSU_AOX_LOMDE_W_PLL_DIV__W 2 +#define ORX_NSU_AOX_LOMDE_W_PLL_DIV__M 0xC000 +#define ORX_NSU_AOX_LOMDE_W_PLL_DIV__PRE 0x0 + + +#define ORX_NSU_AOX_LOPOW_W__A 0x2060013 +#define ORX_NSU_AOX_LOPOW_W__W 2 +#define ORX_NSU_AOX_LOPOW_W__M 0x3 +#define ORX_NSU_AOX_LOPOW_W__PRE 0x0 +#define ORX_NSU_AOX_LOPOW_W_POWER_MINUS0DB 0x0 +#define ORX_NSU_AOX_LOPOW_W_POWER_MINUS5DB 0x1 +#define ORX_NSU_AOX_LOPOW_W_POWER_MINUS10DB 0x2 +#define ORX_NSU_AOX_LOPOW_W_POWER_MINUS15DB 0x3 + + +#define ORX_NSU_AOX_STHR_W__A 0x2060014 +#define ORX_NSU_AOX_STHR_W__W 5 +#define ORX_NSU_AOX_STHR_W__M 0x1F +#define ORX_NSU_AOX_STHR_W__PRE 0x0 + +#define ORX_NSU_TUN_RFGAIN_W__A 0x2060015 +#define ORX_NSU_TUN_RFGAIN_W__W 15 +#define ORX_NSU_TUN_RFGAIN_W__M 0x7FFF +#define ORX_NSU_TUN_RFGAIN_W__PRE 0x0 + +#define ORX_NSU_TUN_IFGAIN_W__A 0x2060016 +#define ORX_NSU_TUN_IFGAIN_W__W 15 +#define ORX_NSU_TUN_IFGAIN_W__M 0x7FFF +#define ORX_NSU_TUN_IFGAIN_W__PRE 0x0 + +#define ORX_NSU_TUN_BPF_W__A 0x2060017 +#define ORX_NSU_TUN_BPF_W__W 15 +#define ORX_NSU_TUN_BPF_W__M 0x7FFF +#define ORX_NSU_TUN_BPF_W__PRE 0x1F9 +#define ORX_NSU_NSS_BITSWAP_W__A 0x2060018 +#define ORX_NSU_NSS_BITSWAP_W__W 3 +#define ORX_NSU_NSS_BITSWAP_W__M 0x7 +#define ORX_NSU_NSS_BITSWAP_W__PRE 0x0 + +#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS0_RF__B 0 +#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS0_RF__W 1 +#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS0_RF__M 0x1 +#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS0_RF__PRE 0x0 + +#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS1_IF__B 1 +#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS1_IF__W 1 +#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS1_IF__M 0x2 +#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS1_IF__PRE 0x0 + +#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS2_BP__B 2 +#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS2_BP__W 1 +#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS2_BP__M 0x4 +#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS2_BP__PRE 0x0 + + + +#define ORX_TST_COMM_EXEC__A 0x23F0000 +#define ORX_TST_COMM_EXEC__W 2 +#define ORX_TST_COMM_EXEC__M 0x3 +#define ORX_TST_COMM_EXEC__PRE 0x0 +#define ORX_TST_COMM_EXEC_STOP 0x0 +#define ORX_TST_COMM_EXEC_ACTIVE 0x1 +#define ORX_TST_COMM_EXEC_HOLD 0x2 + + +#define ORX_TST_AOX_TST_W__A 0x23F0010 +#define ORX_TST_AOX_TST_W__W 8 +#define ORX_TST_AOX_TST_W__M 0xFF +#define ORX_TST_AOX_TST_W__PRE 0x0 + + + + + +#define QAM_COMM_EXEC__A 0x1400000 +#define QAM_COMM_EXEC__W 2 +#define QAM_COMM_EXEC__M 0x3 +#define QAM_COMM_EXEC__PRE 0x0 +#define QAM_COMM_EXEC_STOP 0x0 +#define QAM_COMM_EXEC_ACTIVE 0x1 +#define QAM_COMM_EXEC_HOLD 0x2 + +#define QAM_COMM_MB__A 0x1400002 +#define QAM_COMM_MB__W 16 +#define QAM_COMM_MB__M 0xFFFF +#define QAM_COMM_MB__PRE 0x0 +#define QAM_COMM_INT_REQ__A 0x1400003 +#define QAM_COMM_INT_REQ__W 16 +#define QAM_COMM_INT_REQ__M 0xFFFF +#define QAM_COMM_INT_REQ__PRE 0x0 + +#define QAM_COMM_INT_REQ_SL_REQ__B 0 +#define QAM_COMM_INT_REQ_SL_REQ__W 1 +#define QAM_COMM_INT_REQ_SL_REQ__M 0x1 +#define QAM_COMM_INT_REQ_SL_REQ__PRE 0x0 + +#define QAM_COMM_INT_REQ_LC_REQ__B 1 +#define QAM_COMM_INT_REQ_LC_REQ__W 1 +#define QAM_COMM_INT_REQ_LC_REQ__M 0x2 +#define QAM_COMM_INT_REQ_LC_REQ__PRE 0x0 + +#define QAM_COMM_INT_REQ_VD_REQ__B 2 +#define QAM_COMM_INT_REQ_VD_REQ__W 1 +#define QAM_COMM_INT_REQ_VD_REQ__M 0x4 +#define QAM_COMM_INT_REQ_VD_REQ__PRE 0x0 + +#define QAM_COMM_INT_REQ_SY_REQ__B 3 +#define QAM_COMM_INT_REQ_SY_REQ__W 1 +#define QAM_COMM_INT_REQ_SY_REQ__M 0x8 +#define QAM_COMM_INT_REQ_SY_REQ__PRE 0x0 + +#define QAM_COMM_INT_STA__A 0x1400005 +#define QAM_COMM_INT_STA__W 16 +#define QAM_COMM_INT_STA__M 0xFFFF +#define QAM_COMM_INT_STA__PRE 0x0 +#define QAM_COMM_INT_MSK__A 0x1400006 +#define QAM_COMM_INT_MSK__W 16 +#define QAM_COMM_INT_MSK__M 0xFFFF +#define QAM_COMM_INT_MSK__PRE 0x0 +#define QAM_COMM_INT_STM__A 0x1400007 +#define QAM_COMM_INT_STM__W 16 +#define QAM_COMM_INT_STM__M 0xFFFF +#define QAM_COMM_INT_STM__PRE 0x0 + + + +#define QAM_TOP_COMM_EXEC__A 0x1410000 +#define QAM_TOP_COMM_EXEC__W 2 +#define QAM_TOP_COMM_EXEC__M 0x3 +#define QAM_TOP_COMM_EXEC__PRE 0x0 +#define QAM_TOP_COMM_EXEC_STOP 0x0 +#define QAM_TOP_COMM_EXEC_ACTIVE 0x1 +#define QAM_TOP_COMM_EXEC_HOLD 0x2 + + +#define QAM_TOP_ANNEX__A 0x1410010 +#define QAM_TOP_ANNEX__W 2 +#define QAM_TOP_ANNEX__M 0x3 +#define QAM_TOP_ANNEX__PRE 0x1 +#define QAM_TOP_ANNEX_A 0x0 +#define QAM_TOP_ANNEX_B 0x1 +#define QAM_TOP_ANNEX_C 0x2 +#define QAM_TOP_ANNEX_D 0x3 + + +#define QAM_TOP_CONSTELLATION__A 0x1410011 +#define QAM_TOP_CONSTELLATION__W 3 +#define QAM_TOP_CONSTELLATION__M 0x7 +#define QAM_TOP_CONSTELLATION__PRE 0x5 +#define QAM_TOP_CONSTELLATION_NONE 0x0 +#define QAM_TOP_CONSTELLATION_QPSK 0x1 +#define QAM_TOP_CONSTELLATION_QAM8 0x2 +#define QAM_TOP_CONSTELLATION_QAM16 0x3 +#define QAM_TOP_CONSTELLATION_QAM32 0x4 +#define QAM_TOP_CONSTELLATION_QAM64 0x5 +#define QAM_TOP_CONSTELLATION_QAM128 0x6 +#define QAM_TOP_CONSTELLATION_QAM256 0x7 + + + +#define QAM_FQ_COMM_EXEC__A 0x1420000 +#define QAM_FQ_COMM_EXEC__W 2 +#define QAM_FQ_COMM_EXEC__M 0x3 +#define QAM_FQ_COMM_EXEC__PRE 0x0 +#define QAM_FQ_COMM_EXEC_STOP 0x0 +#define QAM_FQ_COMM_EXEC_ACTIVE 0x1 +#define QAM_FQ_COMM_EXEC_HOLD 0x2 + +#define QAM_FQ_MODE__A 0x1420010 +#define QAM_FQ_MODE__W 3 +#define QAM_FQ_MODE__M 0x7 +#define QAM_FQ_MODE__PRE 0x0 + +#define QAM_FQ_MODE_TAPRESET__B 0 +#define QAM_FQ_MODE_TAPRESET__W 1 +#define QAM_FQ_MODE_TAPRESET__M 0x1 +#define QAM_FQ_MODE_TAPRESET__PRE 0x0 +#define QAM_FQ_MODE_TAPRESET_RST 0x1 + +#define QAM_FQ_MODE_TAPLMS__B 1 +#define QAM_FQ_MODE_TAPLMS__W 1 +#define QAM_FQ_MODE_TAPLMS__M 0x2 +#define QAM_FQ_MODE_TAPLMS__PRE 0x0 +#define QAM_FQ_MODE_TAPLMS_UPD 0x2 + +#define QAM_FQ_MODE_TAPDRAIN__B 2 +#define QAM_FQ_MODE_TAPDRAIN__W 1 +#define QAM_FQ_MODE_TAPDRAIN__M 0x4 +#define QAM_FQ_MODE_TAPDRAIN__PRE 0x0 +#define QAM_FQ_MODE_TAPDRAIN_DRAIN 0x4 + + +#define QAM_FQ_MU_FACTOR__A 0x1420011 +#define QAM_FQ_MU_FACTOR__W 3 +#define QAM_FQ_MU_FACTOR__M 0x7 +#define QAM_FQ_MU_FACTOR__PRE 0x0 + +#define QAM_FQ_LA_FACTOR__A 0x1420012 +#define QAM_FQ_LA_FACTOR__W 4 +#define QAM_FQ_LA_FACTOR__M 0xF +#define QAM_FQ_LA_FACTOR__PRE 0xC +#define QAM_FQ_CENTTAP_IDX__A 0x1420016 +#define QAM_FQ_CENTTAP_IDX__W 5 +#define QAM_FQ_CENTTAP_IDX__M 0x1F +#define QAM_FQ_CENTTAP_IDX__PRE 0x13 + +#define QAM_FQ_CENTTAP_IDX_IDX__B 0 +#define QAM_FQ_CENTTAP_IDX_IDX__W 5 +#define QAM_FQ_CENTTAP_IDX_IDX__M 0x1F +#define QAM_FQ_CENTTAP_IDX_IDX__PRE 0x13 + +#define QAM_FQ_CENTTAP_VALUE__A 0x1420017 +#define QAM_FQ_CENTTAP_VALUE__W 12 +#define QAM_FQ_CENTTAP_VALUE__M 0xFFF +#define QAM_FQ_CENTTAP_VALUE__PRE 0x600 + +#define QAM_FQ_CENTTAP_VALUE_TAP__B 0 +#define QAM_FQ_CENTTAP_VALUE_TAP__W 12 +#define QAM_FQ_CENTTAP_VALUE_TAP__M 0xFFF +#define QAM_FQ_CENTTAP_VALUE_TAP__PRE 0x600 + +#define QAM_FQ_TAP_RE_EL0__A 0x1420020 +#define QAM_FQ_TAP_RE_EL0__W 12 +#define QAM_FQ_TAP_RE_EL0__M 0xFFF +#define QAM_FQ_TAP_RE_EL0__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL0_TAP__B 0 +#define QAM_FQ_TAP_RE_EL0_TAP__W 12 +#define QAM_FQ_TAP_RE_EL0_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL0_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL0__A 0x1420021 +#define QAM_FQ_TAP_IM_EL0__W 12 +#define QAM_FQ_TAP_IM_EL0__M 0xFFF +#define QAM_FQ_TAP_IM_EL0__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL0_TAP__B 0 +#define QAM_FQ_TAP_IM_EL0_TAP__W 12 +#define QAM_FQ_TAP_IM_EL0_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL0_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL1__A 0x1420022 +#define QAM_FQ_TAP_RE_EL1__W 12 +#define QAM_FQ_TAP_RE_EL1__M 0xFFF +#define QAM_FQ_TAP_RE_EL1__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL1_TAP__B 0 +#define QAM_FQ_TAP_RE_EL1_TAP__W 12 +#define QAM_FQ_TAP_RE_EL1_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL1_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL1__A 0x1420023 +#define QAM_FQ_TAP_IM_EL1__W 12 +#define QAM_FQ_TAP_IM_EL1__M 0xFFF +#define QAM_FQ_TAP_IM_EL1__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL1_TAP__B 0 +#define QAM_FQ_TAP_IM_EL1_TAP__W 12 +#define QAM_FQ_TAP_IM_EL1_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL1_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL2__A 0x1420024 +#define QAM_FQ_TAP_RE_EL2__W 12 +#define QAM_FQ_TAP_RE_EL2__M 0xFFF +#define QAM_FQ_TAP_RE_EL2__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL2_TAP__B 0 +#define QAM_FQ_TAP_RE_EL2_TAP__W 12 +#define QAM_FQ_TAP_RE_EL2_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL2_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL2__A 0x1420025 +#define QAM_FQ_TAP_IM_EL2__W 12 +#define QAM_FQ_TAP_IM_EL2__M 0xFFF +#define QAM_FQ_TAP_IM_EL2__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL2_TAP__B 0 +#define QAM_FQ_TAP_IM_EL2_TAP__W 12 +#define QAM_FQ_TAP_IM_EL2_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL2_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL3__A 0x1420026 +#define QAM_FQ_TAP_RE_EL3__W 12 +#define QAM_FQ_TAP_RE_EL3__M 0xFFF +#define QAM_FQ_TAP_RE_EL3__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL3_TAP__B 0 +#define QAM_FQ_TAP_RE_EL3_TAP__W 12 +#define QAM_FQ_TAP_RE_EL3_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL3_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL3__A 0x1420027 +#define QAM_FQ_TAP_IM_EL3__W 12 +#define QAM_FQ_TAP_IM_EL3__M 0xFFF +#define QAM_FQ_TAP_IM_EL3__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL3_TAP__B 0 +#define QAM_FQ_TAP_IM_EL3_TAP__W 12 +#define QAM_FQ_TAP_IM_EL3_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL3_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL4__A 0x1420028 +#define QAM_FQ_TAP_RE_EL4__W 12 +#define QAM_FQ_TAP_RE_EL4__M 0xFFF +#define QAM_FQ_TAP_RE_EL4__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL4_TAP__B 0 +#define QAM_FQ_TAP_RE_EL4_TAP__W 12 +#define QAM_FQ_TAP_RE_EL4_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL4_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL4__A 0x1420029 +#define QAM_FQ_TAP_IM_EL4__W 12 +#define QAM_FQ_TAP_IM_EL4__M 0xFFF +#define QAM_FQ_TAP_IM_EL4__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL4_TAP__B 0 +#define QAM_FQ_TAP_IM_EL4_TAP__W 12 +#define QAM_FQ_TAP_IM_EL4_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL4_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL5__A 0x142002A +#define QAM_FQ_TAP_RE_EL5__W 12 +#define QAM_FQ_TAP_RE_EL5__M 0xFFF +#define QAM_FQ_TAP_RE_EL5__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL5_TAP__B 0 +#define QAM_FQ_TAP_RE_EL5_TAP__W 12 +#define QAM_FQ_TAP_RE_EL5_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL5_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL5__A 0x142002B +#define QAM_FQ_TAP_IM_EL5__W 12 +#define QAM_FQ_TAP_IM_EL5__M 0xFFF +#define QAM_FQ_TAP_IM_EL5__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL5_TAP__B 0 +#define QAM_FQ_TAP_IM_EL5_TAP__W 12 +#define QAM_FQ_TAP_IM_EL5_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL5_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL6__A 0x142002C +#define QAM_FQ_TAP_RE_EL6__W 12 +#define QAM_FQ_TAP_RE_EL6__M 0xFFF +#define QAM_FQ_TAP_RE_EL6__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL6_TAP__B 0 +#define QAM_FQ_TAP_RE_EL6_TAP__W 12 +#define QAM_FQ_TAP_RE_EL6_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL6_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL6__A 0x142002D +#define QAM_FQ_TAP_IM_EL6__W 12 +#define QAM_FQ_TAP_IM_EL6__M 0xFFF +#define QAM_FQ_TAP_IM_EL6__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL6_TAP__B 0 +#define QAM_FQ_TAP_IM_EL6_TAP__W 12 +#define QAM_FQ_TAP_IM_EL6_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL6_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL7__A 0x142002E +#define QAM_FQ_TAP_RE_EL7__W 12 +#define QAM_FQ_TAP_RE_EL7__M 0xFFF +#define QAM_FQ_TAP_RE_EL7__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL7_TAP__B 0 +#define QAM_FQ_TAP_RE_EL7_TAP__W 12 +#define QAM_FQ_TAP_RE_EL7_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL7_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL7__A 0x142002F +#define QAM_FQ_TAP_IM_EL7__W 12 +#define QAM_FQ_TAP_IM_EL7__M 0xFFF +#define QAM_FQ_TAP_IM_EL7__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL7_TAP__B 0 +#define QAM_FQ_TAP_IM_EL7_TAP__W 12 +#define QAM_FQ_TAP_IM_EL7_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL7_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL8__A 0x1420030 +#define QAM_FQ_TAP_RE_EL8__W 12 +#define QAM_FQ_TAP_RE_EL8__M 0xFFF +#define QAM_FQ_TAP_RE_EL8__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL8_TAP__B 0 +#define QAM_FQ_TAP_RE_EL8_TAP__W 12 +#define QAM_FQ_TAP_RE_EL8_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL8_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL8__A 0x1420031 +#define QAM_FQ_TAP_IM_EL8__W 12 +#define QAM_FQ_TAP_IM_EL8__M 0xFFF +#define QAM_FQ_TAP_IM_EL8__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL8_TAP__B 0 +#define QAM_FQ_TAP_IM_EL8_TAP__W 12 +#define QAM_FQ_TAP_IM_EL8_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL8_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL9__A 0x1420032 +#define QAM_FQ_TAP_RE_EL9__W 12 +#define QAM_FQ_TAP_RE_EL9__M 0xFFF +#define QAM_FQ_TAP_RE_EL9__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL9_TAP__B 0 +#define QAM_FQ_TAP_RE_EL9_TAP__W 12 +#define QAM_FQ_TAP_RE_EL9_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL9_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL9__A 0x1420033 +#define QAM_FQ_TAP_IM_EL9__W 12 +#define QAM_FQ_TAP_IM_EL9__M 0xFFF +#define QAM_FQ_TAP_IM_EL9__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL9_TAP__B 0 +#define QAM_FQ_TAP_IM_EL9_TAP__W 12 +#define QAM_FQ_TAP_IM_EL9_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL9_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL10__A 0x1420034 +#define QAM_FQ_TAP_RE_EL10__W 12 +#define QAM_FQ_TAP_RE_EL10__M 0xFFF +#define QAM_FQ_TAP_RE_EL10__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL10_TAP__B 0 +#define QAM_FQ_TAP_RE_EL10_TAP__W 12 +#define QAM_FQ_TAP_RE_EL10_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL10_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL10__A 0x1420035 +#define QAM_FQ_TAP_IM_EL10__W 12 +#define QAM_FQ_TAP_IM_EL10__M 0xFFF +#define QAM_FQ_TAP_IM_EL10__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL10_TAP__B 0 +#define QAM_FQ_TAP_IM_EL10_TAP__W 12 +#define QAM_FQ_TAP_IM_EL10_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL10_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL11__A 0x1420036 +#define QAM_FQ_TAP_RE_EL11__W 12 +#define QAM_FQ_TAP_RE_EL11__M 0xFFF +#define QAM_FQ_TAP_RE_EL11__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL11_TAP__B 0 +#define QAM_FQ_TAP_RE_EL11_TAP__W 12 +#define QAM_FQ_TAP_RE_EL11_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL11_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL11__A 0x1420037 +#define QAM_FQ_TAP_IM_EL11__W 12 +#define QAM_FQ_TAP_IM_EL11__M 0xFFF +#define QAM_FQ_TAP_IM_EL11__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL11_TAP__B 0 +#define QAM_FQ_TAP_IM_EL11_TAP__W 12 +#define QAM_FQ_TAP_IM_EL11_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL11_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL12__A 0x1420038 +#define QAM_FQ_TAP_RE_EL12__W 12 +#define QAM_FQ_TAP_RE_EL12__M 0xFFF +#define QAM_FQ_TAP_RE_EL12__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL12_TAP__B 0 +#define QAM_FQ_TAP_RE_EL12_TAP__W 12 +#define QAM_FQ_TAP_RE_EL12_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL12_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL12__A 0x1420039 +#define QAM_FQ_TAP_IM_EL12__W 12 +#define QAM_FQ_TAP_IM_EL12__M 0xFFF +#define QAM_FQ_TAP_IM_EL12__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL12_TAP__B 0 +#define QAM_FQ_TAP_IM_EL12_TAP__W 12 +#define QAM_FQ_TAP_IM_EL12_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL12_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL13__A 0x142003A +#define QAM_FQ_TAP_RE_EL13__W 12 +#define QAM_FQ_TAP_RE_EL13__M 0xFFF +#define QAM_FQ_TAP_RE_EL13__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL13_TAP__B 0 +#define QAM_FQ_TAP_RE_EL13_TAP__W 12 +#define QAM_FQ_TAP_RE_EL13_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL13_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL13__A 0x142003B +#define QAM_FQ_TAP_IM_EL13__W 12 +#define QAM_FQ_TAP_IM_EL13__M 0xFFF +#define QAM_FQ_TAP_IM_EL13__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL13_TAP__B 0 +#define QAM_FQ_TAP_IM_EL13_TAP__W 12 +#define QAM_FQ_TAP_IM_EL13_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL13_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL14__A 0x142003C +#define QAM_FQ_TAP_RE_EL14__W 12 +#define QAM_FQ_TAP_RE_EL14__M 0xFFF +#define QAM_FQ_TAP_RE_EL14__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL14_TAP__B 0 +#define QAM_FQ_TAP_RE_EL14_TAP__W 12 +#define QAM_FQ_TAP_RE_EL14_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL14_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL14__A 0x142003D +#define QAM_FQ_TAP_IM_EL14__W 12 +#define QAM_FQ_TAP_IM_EL14__M 0xFFF +#define QAM_FQ_TAP_IM_EL14__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL14_TAP__B 0 +#define QAM_FQ_TAP_IM_EL14_TAP__W 12 +#define QAM_FQ_TAP_IM_EL14_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL14_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL15__A 0x142003E +#define QAM_FQ_TAP_RE_EL15__W 12 +#define QAM_FQ_TAP_RE_EL15__M 0xFFF +#define QAM_FQ_TAP_RE_EL15__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL15_TAP__B 0 +#define QAM_FQ_TAP_RE_EL15_TAP__W 12 +#define QAM_FQ_TAP_RE_EL15_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL15_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL15__A 0x142003F +#define QAM_FQ_TAP_IM_EL15__W 12 +#define QAM_FQ_TAP_IM_EL15__M 0xFFF +#define QAM_FQ_TAP_IM_EL15__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL15_TAP__B 0 +#define QAM_FQ_TAP_IM_EL15_TAP__W 12 +#define QAM_FQ_TAP_IM_EL15_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL15_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL16__A 0x1420040 +#define QAM_FQ_TAP_RE_EL16__W 12 +#define QAM_FQ_TAP_RE_EL16__M 0xFFF +#define QAM_FQ_TAP_RE_EL16__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL16_TAP__B 0 +#define QAM_FQ_TAP_RE_EL16_TAP__W 12 +#define QAM_FQ_TAP_RE_EL16_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL16_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL16__A 0x1420041 +#define QAM_FQ_TAP_IM_EL16__W 12 +#define QAM_FQ_TAP_IM_EL16__M 0xFFF +#define QAM_FQ_TAP_IM_EL16__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL16_TAP__B 0 +#define QAM_FQ_TAP_IM_EL16_TAP__W 12 +#define QAM_FQ_TAP_IM_EL16_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL16_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL17__A 0x1420042 +#define QAM_FQ_TAP_RE_EL17__W 12 +#define QAM_FQ_TAP_RE_EL17__M 0xFFF +#define QAM_FQ_TAP_RE_EL17__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL17_TAP__B 0 +#define QAM_FQ_TAP_RE_EL17_TAP__W 12 +#define QAM_FQ_TAP_RE_EL17_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL17_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL17__A 0x1420043 +#define QAM_FQ_TAP_IM_EL17__W 12 +#define QAM_FQ_TAP_IM_EL17__M 0xFFF +#define QAM_FQ_TAP_IM_EL17__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL17_TAP__B 0 +#define QAM_FQ_TAP_IM_EL17_TAP__W 12 +#define QAM_FQ_TAP_IM_EL17_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL17_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL18__A 0x1420044 +#define QAM_FQ_TAP_RE_EL18__W 12 +#define QAM_FQ_TAP_RE_EL18__M 0xFFF +#define QAM_FQ_TAP_RE_EL18__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL18_TAP__B 0 +#define QAM_FQ_TAP_RE_EL18_TAP__W 12 +#define QAM_FQ_TAP_RE_EL18_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL18_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL18__A 0x1420045 +#define QAM_FQ_TAP_IM_EL18__W 12 +#define QAM_FQ_TAP_IM_EL18__M 0xFFF +#define QAM_FQ_TAP_IM_EL18__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL18_TAP__B 0 +#define QAM_FQ_TAP_IM_EL18_TAP__W 12 +#define QAM_FQ_TAP_IM_EL18_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL18_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL19__A 0x1420046 +#define QAM_FQ_TAP_RE_EL19__W 12 +#define QAM_FQ_TAP_RE_EL19__M 0xFFF +#define QAM_FQ_TAP_RE_EL19__PRE 0x600 + +#define QAM_FQ_TAP_RE_EL19_TAP__B 0 +#define QAM_FQ_TAP_RE_EL19_TAP__W 12 +#define QAM_FQ_TAP_RE_EL19_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL19_TAP__PRE 0x600 + +#define QAM_FQ_TAP_IM_EL19__A 0x1420047 +#define QAM_FQ_TAP_IM_EL19__W 12 +#define QAM_FQ_TAP_IM_EL19__M 0xFFF +#define QAM_FQ_TAP_IM_EL19__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL19_TAP__B 0 +#define QAM_FQ_TAP_IM_EL19_TAP__W 12 +#define QAM_FQ_TAP_IM_EL19_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL19_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL20__A 0x1420048 +#define QAM_FQ_TAP_RE_EL20__W 12 +#define QAM_FQ_TAP_RE_EL20__M 0xFFF +#define QAM_FQ_TAP_RE_EL20__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL20_TAP__B 0 +#define QAM_FQ_TAP_RE_EL20_TAP__W 12 +#define QAM_FQ_TAP_RE_EL20_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL20_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL20__A 0x1420049 +#define QAM_FQ_TAP_IM_EL20__W 12 +#define QAM_FQ_TAP_IM_EL20__M 0xFFF +#define QAM_FQ_TAP_IM_EL20__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL20_TAP__B 0 +#define QAM_FQ_TAP_IM_EL20_TAP__W 12 +#define QAM_FQ_TAP_IM_EL20_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL20_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL21__A 0x142004A +#define QAM_FQ_TAP_RE_EL21__W 12 +#define QAM_FQ_TAP_RE_EL21__M 0xFFF +#define QAM_FQ_TAP_RE_EL21__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL21_TAP__B 0 +#define QAM_FQ_TAP_RE_EL21_TAP__W 12 +#define QAM_FQ_TAP_RE_EL21_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL21_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL21__A 0x142004B +#define QAM_FQ_TAP_IM_EL21__W 12 +#define QAM_FQ_TAP_IM_EL21__M 0xFFF +#define QAM_FQ_TAP_IM_EL21__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL21_TAP__B 0 +#define QAM_FQ_TAP_IM_EL21_TAP__W 12 +#define QAM_FQ_TAP_IM_EL21_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL21_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL22__A 0x142004C +#define QAM_FQ_TAP_RE_EL22__W 12 +#define QAM_FQ_TAP_RE_EL22__M 0xFFF +#define QAM_FQ_TAP_RE_EL22__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL22_TAP__B 0 +#define QAM_FQ_TAP_RE_EL22_TAP__W 12 +#define QAM_FQ_TAP_RE_EL22_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL22_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL22__A 0x142004D +#define QAM_FQ_TAP_IM_EL22__W 12 +#define QAM_FQ_TAP_IM_EL22__M 0xFFF +#define QAM_FQ_TAP_IM_EL22__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL22_TAP__B 0 +#define QAM_FQ_TAP_IM_EL22_TAP__W 12 +#define QAM_FQ_TAP_IM_EL22_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL22_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL23__A 0x142004E +#define QAM_FQ_TAP_RE_EL23__W 12 +#define QAM_FQ_TAP_RE_EL23__M 0xFFF +#define QAM_FQ_TAP_RE_EL23__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL23_TAP__B 0 +#define QAM_FQ_TAP_RE_EL23_TAP__W 12 +#define QAM_FQ_TAP_RE_EL23_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL23_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL23__A 0x142004F +#define QAM_FQ_TAP_IM_EL23__W 12 +#define QAM_FQ_TAP_IM_EL23__M 0xFFF +#define QAM_FQ_TAP_IM_EL23__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL23_TAP__B 0 +#define QAM_FQ_TAP_IM_EL23_TAP__W 12 +#define QAM_FQ_TAP_IM_EL23_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL23_TAP__PRE 0x2 + + + +#define QAM_SL_COMM_EXEC__A 0x1430000 +#define QAM_SL_COMM_EXEC__W 2 +#define QAM_SL_COMM_EXEC__M 0x3 +#define QAM_SL_COMM_EXEC__PRE 0x0 +#define QAM_SL_COMM_EXEC_STOP 0x0 +#define QAM_SL_COMM_EXEC_ACTIVE 0x1 +#define QAM_SL_COMM_EXEC_HOLD 0x2 + +#define QAM_SL_COMM_MB__A 0x1430002 +#define QAM_SL_COMM_MB__W 4 +#define QAM_SL_COMM_MB__M 0xF +#define QAM_SL_COMM_MB__PRE 0x0 +#define QAM_SL_COMM_MB_CTL__B 0 +#define QAM_SL_COMM_MB_CTL__W 1 +#define QAM_SL_COMM_MB_CTL__M 0x1 +#define QAM_SL_COMM_MB_CTL__PRE 0x0 +#define QAM_SL_COMM_MB_CTL_OFF 0x0 +#define QAM_SL_COMM_MB_CTL_ON 0x1 +#define QAM_SL_COMM_MB_OBS__B 1 +#define QAM_SL_COMM_MB_OBS__W 1 +#define QAM_SL_COMM_MB_OBS__M 0x2 +#define QAM_SL_COMM_MB_OBS__PRE 0x0 +#define QAM_SL_COMM_MB_OBS_OFF 0x0 +#define QAM_SL_COMM_MB_OBS_ON 0x2 +#define QAM_SL_COMM_MB_MUX_OBS__B 2 +#define QAM_SL_COMM_MB_MUX_OBS__W 2 +#define QAM_SL_COMM_MB_MUX_OBS__M 0xC +#define QAM_SL_COMM_MB_MUX_OBS__PRE 0x0 +#define QAM_SL_COMM_MB_MUX_OBS_CONST_CORR 0x0 +#define QAM_SL_COMM_MB_MUX_OBS_CONST2LC_O 0x4 +#define QAM_SL_COMM_MB_MUX_OBS_CONST2DQ_O 0x8 +#define QAM_SL_COMM_MB_MUX_OBS_VDEC_O 0xC + +#define QAM_SL_COMM_INT_REQ__A 0x1430003 +#define QAM_SL_COMM_INT_REQ__W 1 +#define QAM_SL_COMM_INT_REQ__M 0x1 +#define QAM_SL_COMM_INT_REQ__PRE 0x0 +#define QAM_SL_COMM_INT_STA__A 0x1430005 +#define QAM_SL_COMM_INT_STA__W 2 +#define QAM_SL_COMM_INT_STA__M 0x3 +#define QAM_SL_COMM_INT_STA__PRE 0x0 + +#define QAM_SL_COMM_INT_STA_MED_ERR_INT__B 0 +#define QAM_SL_COMM_INT_STA_MED_ERR_INT__W 1 +#define QAM_SL_COMM_INT_STA_MED_ERR_INT__M 0x1 +#define QAM_SL_COMM_INT_STA_MED_ERR_INT__PRE 0x0 + +#define QAM_SL_COMM_INT_STA_MER_INT__B 1 +#define QAM_SL_COMM_INT_STA_MER_INT__W 1 +#define QAM_SL_COMM_INT_STA_MER_INT__M 0x2 +#define QAM_SL_COMM_INT_STA_MER_INT__PRE 0x0 + +#define QAM_SL_COMM_INT_MSK__A 0x1430006 +#define QAM_SL_COMM_INT_MSK__W 2 +#define QAM_SL_COMM_INT_MSK__M 0x3 +#define QAM_SL_COMM_INT_MSK__PRE 0x0 +#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__B 0 +#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__W 1 +#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__M 0x1 +#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__PRE 0x0 +#define QAM_SL_COMM_INT_MSK_MER_MSK__B 1 +#define QAM_SL_COMM_INT_MSK_MER_MSK__W 1 +#define QAM_SL_COMM_INT_MSK_MER_MSK__M 0x2 +#define QAM_SL_COMM_INT_MSK_MER_MSK__PRE 0x0 + +#define QAM_SL_COMM_INT_STM__A 0x1430007 +#define QAM_SL_COMM_INT_STM__W 2 +#define QAM_SL_COMM_INT_STM__M 0x3 +#define QAM_SL_COMM_INT_STM__PRE 0x0 +#define QAM_SL_COMM_INT_STM_MED_ERR_STM__B 0 +#define QAM_SL_COMM_INT_STM_MED_ERR_STM__W 1 +#define QAM_SL_COMM_INT_STM_MED_ERR_STM__M 0x1 +#define QAM_SL_COMM_INT_STM_MED_ERR_STM__PRE 0x0 +#define QAM_SL_COMM_INT_STM_MER_STM__B 1 +#define QAM_SL_COMM_INT_STM_MER_STM__W 1 +#define QAM_SL_COMM_INT_STM_MER_STM__M 0x2 +#define QAM_SL_COMM_INT_STM_MER_STM__PRE 0x0 + +#define QAM_SL_MODE__A 0x1430010 +#define QAM_SL_MODE__W 11 +#define QAM_SL_MODE__M 0x7FF +#define QAM_SL_MODE__PRE 0x0 + +#define QAM_SL_MODE_SLICER4LC__B 0 +#define QAM_SL_MODE_SLICER4LC__W 2 +#define QAM_SL_MODE_SLICER4LC__M 0x3 +#define QAM_SL_MODE_SLICER4LC__PRE 0x0 +#define QAM_SL_MODE_SLICER4LC_RECT 0x0 +#define QAM_SL_MODE_SLICER4LC_ONET 0x1 +#define QAM_SL_MODE_SLICER4LC_RAD 0x2 + +#define QAM_SL_MODE_SLICER4DQ__B 2 +#define QAM_SL_MODE_SLICER4DQ__W 2 +#define QAM_SL_MODE_SLICER4DQ__M 0xC +#define QAM_SL_MODE_SLICER4DQ__PRE 0x0 +#define QAM_SL_MODE_SLICER4DQ_RECT 0x0 +#define QAM_SL_MODE_SLICER4DQ_ONET 0x4 +#define QAM_SL_MODE_SLICER4DQ_RAD 0x8 + +#define QAM_SL_MODE_SLICER4VD__B 4 +#define QAM_SL_MODE_SLICER4VD__W 2 +#define QAM_SL_MODE_SLICER4VD__M 0x30 +#define QAM_SL_MODE_SLICER4VD__PRE 0x0 +#define QAM_SL_MODE_SLICER4VD_RECT 0x0 +#define QAM_SL_MODE_SLICER4VD_ONET 0x10 +#define QAM_SL_MODE_SLICER4VD_RAD 0x20 + +#define QAM_SL_MODE_ROT_DIS__B 6 +#define QAM_SL_MODE_ROT_DIS__W 1 +#define QAM_SL_MODE_ROT_DIS__M 0x40 +#define QAM_SL_MODE_ROT_DIS__PRE 0x0 + +#define QAM_SL_MODE_DQROT_DIS__B 7 +#define QAM_SL_MODE_DQROT_DIS__W 1 +#define QAM_SL_MODE_DQROT_DIS__M 0x80 +#define QAM_SL_MODE_DQROT_DIS__PRE 0x0 + +#define QAM_SL_MODE_DFE_DIS__B 8 +#define QAM_SL_MODE_DFE_DIS__W 1 +#define QAM_SL_MODE_DFE_DIS__M 0x100 +#define QAM_SL_MODE_DFE_DIS__PRE 0x0 + +#define QAM_SL_MODE_RADIUS_MIX__B 9 +#define QAM_SL_MODE_RADIUS_MIX__W 1 +#define QAM_SL_MODE_RADIUS_MIX__M 0x200 +#define QAM_SL_MODE_RADIUS_MIX__PRE 0x0 + +#define QAM_SL_MODE_TILT_COMP__B 10 +#define QAM_SL_MODE_TILT_COMP__W 1 +#define QAM_SL_MODE_TILT_COMP__M 0x400 +#define QAM_SL_MODE_TILT_COMP__PRE 0x0 + + +#define QAM_SL_K_FACTOR__A 0x1430011 +#define QAM_SL_K_FACTOR__W 4 +#define QAM_SL_K_FACTOR__M 0xF +#define QAM_SL_K_FACTOR__PRE 0x0 +#define QAM_SL_MEDIAN__A 0x1430012 +#define QAM_SL_MEDIAN__W 14 +#define QAM_SL_MEDIAN__M 0x3FFF +#define QAM_SL_MEDIAN__PRE 0x0 + +#define QAM_SL_MEDIAN_LENGTH__B 0 +#define QAM_SL_MEDIAN_LENGTH__W 2 +#define QAM_SL_MEDIAN_LENGTH__M 0x3 +#define QAM_SL_MEDIAN_LENGTH__PRE 0x0 + +#define QAM_SL_MEDIAN_CORRECT__B 2 +#define QAM_SL_MEDIAN_CORRECT__W 4 +#define QAM_SL_MEDIAN_CORRECT__M 0x3C +#define QAM_SL_MEDIAN_CORRECT__PRE 0x0 + +#define QAM_SL_MEDIAN_TOLERANCE__B 6 +#define QAM_SL_MEDIAN_TOLERANCE__W 7 +#define QAM_SL_MEDIAN_TOLERANCE__M 0x1FC0 +#define QAM_SL_MEDIAN_TOLERANCE__PRE 0x0 + +#define QAM_SL_MEDIAN_FAST__B 13 +#define QAM_SL_MEDIAN_FAST__W 1 +#define QAM_SL_MEDIAN_FAST__M 0x2000 +#define QAM_SL_MEDIAN_FAST__PRE 0x0 + + +#define QAM_SL_ALPHA__A 0x1430013 +#define QAM_SL_ALPHA__W 3 +#define QAM_SL_ALPHA__M 0x7 +#define QAM_SL_ALPHA__PRE 0x0 + +#define QAM_SL_PHASELIMIT__A 0x1430014 +#define QAM_SL_PHASELIMIT__W 9 +#define QAM_SL_PHASELIMIT__M 0x1FF +#define QAM_SL_PHASELIMIT__PRE 0x0 +#define QAM_SL_MTA_LENGTH__A 0x1430015 +#define QAM_SL_MTA_LENGTH__W 2 +#define QAM_SL_MTA_LENGTH__M 0x3 +#define QAM_SL_MTA_LENGTH__PRE 0x1 + +#define QAM_SL_MTA_LENGTH_LENGTH__B 0 +#define QAM_SL_MTA_LENGTH_LENGTH__W 2 +#define QAM_SL_MTA_LENGTH_LENGTH__M 0x3 +#define QAM_SL_MTA_LENGTH_LENGTH__PRE 0x1 + +#define QAM_SL_MEDIAN_ERROR__A 0x1430016 +#define QAM_SL_MEDIAN_ERROR__W 10 +#define QAM_SL_MEDIAN_ERROR__M 0x3FF +#define QAM_SL_MEDIAN_ERROR__PRE 0x0 + +#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__B 0 +#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__W 10 +#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__M 0x3FF +#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__PRE 0x0 + + +#define QAM_SL_ERR_POWER__A 0x1430017 +#define QAM_SL_ERR_POWER__W 16 +#define QAM_SL_ERR_POWER__M 0xFFFF +#define QAM_SL_ERR_POWER__PRE 0x0 + + + +#define QAM_DQ_COMM_EXEC__A 0x1440000 +#define QAM_DQ_COMM_EXEC__W 2 +#define QAM_DQ_COMM_EXEC__M 0x3 +#define QAM_DQ_COMM_EXEC__PRE 0x0 +#define QAM_DQ_COMM_EXEC_STOP 0x0 +#define QAM_DQ_COMM_EXEC_ACTIVE 0x1 +#define QAM_DQ_COMM_EXEC_HOLD 0x2 + +#define QAM_DQ_MODE__A 0x1440010 +#define QAM_DQ_MODE__W 5 +#define QAM_DQ_MODE__M 0x1F +#define QAM_DQ_MODE__PRE 0x0 + +#define QAM_DQ_MODE_TAPRESET__B 0 +#define QAM_DQ_MODE_TAPRESET__W 1 +#define QAM_DQ_MODE_TAPRESET__M 0x1 +#define QAM_DQ_MODE_TAPRESET__PRE 0x0 +#define QAM_DQ_MODE_TAPRESET_RST 0x1 + +#define QAM_DQ_MODE_TAPLMS__B 1 +#define QAM_DQ_MODE_TAPLMS__W 1 +#define QAM_DQ_MODE_TAPLMS__M 0x2 +#define QAM_DQ_MODE_TAPLMS__PRE 0x0 +#define QAM_DQ_MODE_TAPLMS_UPD 0x2 + +#define QAM_DQ_MODE_TAPDRAIN__B 2 +#define QAM_DQ_MODE_TAPDRAIN__W 1 +#define QAM_DQ_MODE_TAPDRAIN__M 0x4 +#define QAM_DQ_MODE_TAPDRAIN__PRE 0x0 +#define QAM_DQ_MODE_TAPDRAIN_DRAIN 0x4 + +#define QAM_DQ_MODE_FB__B 3 +#define QAM_DQ_MODE_FB__W 2 +#define QAM_DQ_MODE_FB__M 0x18 +#define QAM_DQ_MODE_FB__PRE 0x0 +#define QAM_DQ_MODE_FB_CMA 0x0 +#define QAM_DQ_MODE_FB_RADIUS 0x8 +#define QAM_DQ_MODE_FB_DFB 0x10 +#define QAM_DQ_MODE_FB_TRELLIS 0x18 + + +#define QAM_DQ_MU_FACTOR__A 0x1440011 +#define QAM_DQ_MU_FACTOR__W 3 +#define QAM_DQ_MU_FACTOR__M 0x7 +#define QAM_DQ_MU_FACTOR__PRE 0x0 + +#define QAM_DQ_LA_FACTOR__A 0x1440012 +#define QAM_DQ_LA_FACTOR__W 4 +#define QAM_DQ_LA_FACTOR__M 0xF +#define QAM_DQ_LA_FACTOR__PRE 0xC + +#define QAM_DQ_CMA_RATIO__A 0x1440013 +#define QAM_DQ_CMA_RATIO__W 14 +#define QAM_DQ_CMA_RATIO__M 0x3FFF +#define QAM_DQ_CMA_RATIO__PRE 0x3CF9 +#define QAM_DQ_CMA_RATIO_QPSK 0x2000 +#define QAM_DQ_CMA_RATIO_QAM16 0x34CD +#define QAM_DQ_CMA_RATIO_QAM64 0x3A00 +#define QAM_DQ_CMA_RATIO_QAM256 0x3B4D +#define QAM_DQ_CMA_RATIO_QAM1024 0x3BA0 + +#define QAM_DQ_QUAL_RADSEL__A 0x1440014 +#define QAM_DQ_QUAL_RADSEL__W 3 +#define QAM_DQ_QUAL_RADSEL__M 0x7 +#define QAM_DQ_QUAL_RADSEL__PRE 0x0 + +#define QAM_DQ_QUAL_RADSEL_BIT__B 0 +#define QAM_DQ_QUAL_RADSEL_BIT__W 3 +#define QAM_DQ_QUAL_RADSEL_BIT__M 0x7 +#define QAM_DQ_QUAL_RADSEL_BIT__PRE 0x0 +#define QAM_DQ_QUAL_RADSEL_BIT_PURE_RADIUS 0x0 +#define QAM_DQ_QUAL_RADSEL_BIT_PURE_CMA 0x6 + +#define QAM_DQ_QUAL_ENA__A 0x1440015 +#define QAM_DQ_QUAL_ENA__W 1 +#define QAM_DQ_QUAL_ENA__M 0x1 +#define QAM_DQ_QUAL_ENA__PRE 0x0 + +#define QAM_DQ_QUAL_ENA_ENA__B 0 +#define QAM_DQ_QUAL_ENA_ENA__W 1 +#define QAM_DQ_QUAL_ENA_ENA__M 0x1 +#define QAM_DQ_QUAL_ENA_ENA__PRE 0x0 +#define QAM_DQ_QUAL_ENA_ENA_QUAL_WEIGHTING 0x1 + +#define QAM_DQ_QUAL_FUN0__A 0x1440018 +#define QAM_DQ_QUAL_FUN0__W 6 +#define QAM_DQ_QUAL_FUN0__M 0x3F +#define QAM_DQ_QUAL_FUN0__PRE 0x4 + +#define QAM_DQ_QUAL_FUN0_BIT__B 0 +#define QAM_DQ_QUAL_FUN0_BIT__W 6 +#define QAM_DQ_QUAL_FUN0_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN0_BIT__PRE 0x4 + +#define QAM_DQ_QUAL_FUN1__A 0x1440019 +#define QAM_DQ_QUAL_FUN1__W 6 +#define QAM_DQ_QUAL_FUN1__M 0x3F +#define QAM_DQ_QUAL_FUN1__PRE 0x4 + +#define QAM_DQ_QUAL_FUN1_BIT__B 0 +#define QAM_DQ_QUAL_FUN1_BIT__W 6 +#define QAM_DQ_QUAL_FUN1_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN1_BIT__PRE 0x4 + +#define QAM_DQ_QUAL_FUN2__A 0x144001A +#define QAM_DQ_QUAL_FUN2__W 6 +#define QAM_DQ_QUAL_FUN2__M 0x3F +#define QAM_DQ_QUAL_FUN2__PRE 0x4 + +#define QAM_DQ_QUAL_FUN2_BIT__B 0 +#define QAM_DQ_QUAL_FUN2_BIT__W 6 +#define QAM_DQ_QUAL_FUN2_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN2_BIT__PRE 0x4 + +#define QAM_DQ_QUAL_FUN3__A 0x144001B +#define QAM_DQ_QUAL_FUN3__W 6 +#define QAM_DQ_QUAL_FUN3__M 0x3F +#define QAM_DQ_QUAL_FUN3__PRE 0x4 + +#define QAM_DQ_QUAL_FUN3_BIT__B 0 +#define QAM_DQ_QUAL_FUN3_BIT__W 6 +#define QAM_DQ_QUAL_FUN3_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN3_BIT__PRE 0x4 + +#define QAM_DQ_QUAL_FUN4__A 0x144001C +#define QAM_DQ_QUAL_FUN4__W 6 +#define QAM_DQ_QUAL_FUN4__M 0x3F +#define QAM_DQ_QUAL_FUN4__PRE 0x6 + +#define QAM_DQ_QUAL_FUN4_BIT__B 0 +#define QAM_DQ_QUAL_FUN4_BIT__W 6 +#define QAM_DQ_QUAL_FUN4_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN4_BIT__PRE 0x6 + +#define QAM_DQ_QUAL_FUN5__A 0x144001D +#define QAM_DQ_QUAL_FUN5__W 6 +#define QAM_DQ_QUAL_FUN5__M 0x3F +#define QAM_DQ_QUAL_FUN5__PRE 0x6 + +#define QAM_DQ_QUAL_FUN5_BIT__B 0 +#define QAM_DQ_QUAL_FUN5_BIT__W 6 +#define QAM_DQ_QUAL_FUN5_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN5_BIT__PRE 0x6 + +#define QAM_DQ_RAW_LIM__A 0x144001E +#define QAM_DQ_RAW_LIM__W 5 +#define QAM_DQ_RAW_LIM__M 0x1F +#define QAM_DQ_RAW_LIM__PRE 0x1F + +#define QAM_DQ_RAW_LIM_BIT__B 0 +#define QAM_DQ_RAW_LIM_BIT__W 5 +#define QAM_DQ_RAW_LIM_BIT__M 0x1F +#define QAM_DQ_RAW_LIM_BIT__PRE 0x1F + +#define QAM_DQ_TAP_RE_EL0__A 0x1440020 +#define QAM_DQ_TAP_RE_EL0__W 12 +#define QAM_DQ_TAP_RE_EL0__M 0xFFF +#define QAM_DQ_TAP_RE_EL0__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL0_TAP__B 0 +#define QAM_DQ_TAP_RE_EL0_TAP__W 12 +#define QAM_DQ_TAP_RE_EL0_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL0_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL0__A 0x1440021 +#define QAM_DQ_TAP_IM_EL0__W 12 +#define QAM_DQ_TAP_IM_EL0__M 0xFFF +#define QAM_DQ_TAP_IM_EL0__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL0_TAP__B 0 +#define QAM_DQ_TAP_IM_EL0_TAP__W 12 +#define QAM_DQ_TAP_IM_EL0_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL0_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL1__A 0x1440022 +#define QAM_DQ_TAP_RE_EL1__W 12 +#define QAM_DQ_TAP_RE_EL1__M 0xFFF +#define QAM_DQ_TAP_RE_EL1__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL1_TAP__B 0 +#define QAM_DQ_TAP_RE_EL1_TAP__W 12 +#define QAM_DQ_TAP_RE_EL1_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL1_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL1__A 0x1440023 +#define QAM_DQ_TAP_IM_EL1__W 12 +#define QAM_DQ_TAP_IM_EL1__M 0xFFF +#define QAM_DQ_TAP_IM_EL1__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL1_TAP__B 0 +#define QAM_DQ_TAP_IM_EL1_TAP__W 12 +#define QAM_DQ_TAP_IM_EL1_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL1_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL2__A 0x1440024 +#define QAM_DQ_TAP_RE_EL2__W 12 +#define QAM_DQ_TAP_RE_EL2__M 0xFFF +#define QAM_DQ_TAP_RE_EL2__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL2_TAP__B 0 +#define QAM_DQ_TAP_RE_EL2_TAP__W 12 +#define QAM_DQ_TAP_RE_EL2_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL2_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL2__A 0x1440025 +#define QAM_DQ_TAP_IM_EL2__W 12 +#define QAM_DQ_TAP_IM_EL2__M 0xFFF +#define QAM_DQ_TAP_IM_EL2__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL2_TAP__B 0 +#define QAM_DQ_TAP_IM_EL2_TAP__W 12 +#define QAM_DQ_TAP_IM_EL2_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL2_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL3__A 0x1440026 +#define QAM_DQ_TAP_RE_EL3__W 12 +#define QAM_DQ_TAP_RE_EL3__M 0xFFF +#define QAM_DQ_TAP_RE_EL3__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL3_TAP__B 0 +#define QAM_DQ_TAP_RE_EL3_TAP__W 12 +#define QAM_DQ_TAP_RE_EL3_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL3_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL3__A 0x1440027 +#define QAM_DQ_TAP_IM_EL3__W 12 +#define QAM_DQ_TAP_IM_EL3__M 0xFFF +#define QAM_DQ_TAP_IM_EL3__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL3_TAP__B 0 +#define QAM_DQ_TAP_IM_EL3_TAP__W 12 +#define QAM_DQ_TAP_IM_EL3_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL3_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL4__A 0x1440028 +#define QAM_DQ_TAP_RE_EL4__W 12 +#define QAM_DQ_TAP_RE_EL4__M 0xFFF +#define QAM_DQ_TAP_RE_EL4__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL4_TAP__B 0 +#define QAM_DQ_TAP_RE_EL4_TAP__W 12 +#define QAM_DQ_TAP_RE_EL4_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL4_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL4__A 0x1440029 +#define QAM_DQ_TAP_IM_EL4__W 12 +#define QAM_DQ_TAP_IM_EL4__M 0xFFF +#define QAM_DQ_TAP_IM_EL4__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL4_TAP__B 0 +#define QAM_DQ_TAP_IM_EL4_TAP__W 12 +#define QAM_DQ_TAP_IM_EL4_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL4_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL5__A 0x144002A +#define QAM_DQ_TAP_RE_EL5__W 12 +#define QAM_DQ_TAP_RE_EL5__M 0xFFF +#define QAM_DQ_TAP_RE_EL5__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL5_TAP__B 0 +#define QAM_DQ_TAP_RE_EL5_TAP__W 12 +#define QAM_DQ_TAP_RE_EL5_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL5_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL5__A 0x144002B +#define QAM_DQ_TAP_IM_EL5__W 12 +#define QAM_DQ_TAP_IM_EL5__M 0xFFF +#define QAM_DQ_TAP_IM_EL5__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL5_TAP__B 0 +#define QAM_DQ_TAP_IM_EL5_TAP__W 12 +#define QAM_DQ_TAP_IM_EL5_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL5_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL6__A 0x144002C +#define QAM_DQ_TAP_RE_EL6__W 12 +#define QAM_DQ_TAP_RE_EL6__M 0xFFF +#define QAM_DQ_TAP_RE_EL6__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL6_TAP__B 0 +#define QAM_DQ_TAP_RE_EL6_TAP__W 12 +#define QAM_DQ_TAP_RE_EL6_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL6_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL6__A 0x144002D +#define QAM_DQ_TAP_IM_EL6__W 12 +#define QAM_DQ_TAP_IM_EL6__M 0xFFF +#define QAM_DQ_TAP_IM_EL6__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL6_TAP__B 0 +#define QAM_DQ_TAP_IM_EL6_TAP__W 12 +#define QAM_DQ_TAP_IM_EL6_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL6_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL7__A 0x144002E +#define QAM_DQ_TAP_RE_EL7__W 12 +#define QAM_DQ_TAP_RE_EL7__M 0xFFF +#define QAM_DQ_TAP_RE_EL7__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL7_TAP__B 0 +#define QAM_DQ_TAP_RE_EL7_TAP__W 12 +#define QAM_DQ_TAP_RE_EL7_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL7_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL7__A 0x144002F +#define QAM_DQ_TAP_IM_EL7__W 12 +#define QAM_DQ_TAP_IM_EL7__M 0xFFF +#define QAM_DQ_TAP_IM_EL7__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL7_TAP__B 0 +#define QAM_DQ_TAP_IM_EL7_TAP__W 12 +#define QAM_DQ_TAP_IM_EL7_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL7_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL8__A 0x1440030 +#define QAM_DQ_TAP_RE_EL8__W 12 +#define QAM_DQ_TAP_RE_EL8__M 0xFFF +#define QAM_DQ_TAP_RE_EL8__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL8_TAP__B 0 +#define QAM_DQ_TAP_RE_EL8_TAP__W 12 +#define QAM_DQ_TAP_RE_EL8_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL8_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL8__A 0x1440031 +#define QAM_DQ_TAP_IM_EL8__W 12 +#define QAM_DQ_TAP_IM_EL8__M 0xFFF +#define QAM_DQ_TAP_IM_EL8__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL8_TAP__B 0 +#define QAM_DQ_TAP_IM_EL8_TAP__W 12 +#define QAM_DQ_TAP_IM_EL8_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL8_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL9__A 0x1440032 +#define QAM_DQ_TAP_RE_EL9__W 12 +#define QAM_DQ_TAP_RE_EL9__M 0xFFF +#define QAM_DQ_TAP_RE_EL9__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL9_TAP__B 0 +#define QAM_DQ_TAP_RE_EL9_TAP__W 12 +#define QAM_DQ_TAP_RE_EL9_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL9_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL9__A 0x1440033 +#define QAM_DQ_TAP_IM_EL9__W 12 +#define QAM_DQ_TAP_IM_EL9__M 0xFFF +#define QAM_DQ_TAP_IM_EL9__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL9_TAP__B 0 +#define QAM_DQ_TAP_IM_EL9_TAP__W 12 +#define QAM_DQ_TAP_IM_EL9_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL9_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL10__A 0x1440034 +#define QAM_DQ_TAP_RE_EL10__W 12 +#define QAM_DQ_TAP_RE_EL10__M 0xFFF +#define QAM_DQ_TAP_RE_EL10__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL10_TAP__B 0 +#define QAM_DQ_TAP_RE_EL10_TAP__W 12 +#define QAM_DQ_TAP_RE_EL10_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL10_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL10__A 0x1440035 +#define QAM_DQ_TAP_IM_EL10__W 12 +#define QAM_DQ_TAP_IM_EL10__M 0xFFF +#define QAM_DQ_TAP_IM_EL10__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL10_TAP__B 0 +#define QAM_DQ_TAP_IM_EL10_TAP__W 12 +#define QAM_DQ_TAP_IM_EL10_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL10_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL11__A 0x1440036 +#define QAM_DQ_TAP_RE_EL11__W 12 +#define QAM_DQ_TAP_RE_EL11__M 0xFFF +#define QAM_DQ_TAP_RE_EL11__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL11_TAP__B 0 +#define QAM_DQ_TAP_RE_EL11_TAP__W 12 +#define QAM_DQ_TAP_RE_EL11_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL11_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL11__A 0x1440037 +#define QAM_DQ_TAP_IM_EL11__W 12 +#define QAM_DQ_TAP_IM_EL11__M 0xFFF +#define QAM_DQ_TAP_IM_EL11__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL11_TAP__B 0 +#define QAM_DQ_TAP_IM_EL11_TAP__W 12 +#define QAM_DQ_TAP_IM_EL11_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL11_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL12__A 0x1440038 +#define QAM_DQ_TAP_RE_EL12__W 12 +#define QAM_DQ_TAP_RE_EL12__M 0xFFF +#define QAM_DQ_TAP_RE_EL12__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL12_TAP__B 0 +#define QAM_DQ_TAP_RE_EL12_TAP__W 12 +#define QAM_DQ_TAP_RE_EL12_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL12_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL12__A 0x1440039 +#define QAM_DQ_TAP_IM_EL12__W 12 +#define QAM_DQ_TAP_IM_EL12__M 0xFFF +#define QAM_DQ_TAP_IM_EL12__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL12_TAP__B 0 +#define QAM_DQ_TAP_IM_EL12_TAP__W 12 +#define QAM_DQ_TAP_IM_EL12_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL12_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL13__A 0x144003A +#define QAM_DQ_TAP_RE_EL13__W 12 +#define QAM_DQ_TAP_RE_EL13__M 0xFFF +#define QAM_DQ_TAP_RE_EL13__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL13_TAP__B 0 +#define QAM_DQ_TAP_RE_EL13_TAP__W 12 +#define QAM_DQ_TAP_RE_EL13_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL13_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL13__A 0x144003B +#define QAM_DQ_TAP_IM_EL13__W 12 +#define QAM_DQ_TAP_IM_EL13__M 0xFFF +#define QAM_DQ_TAP_IM_EL13__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL13_TAP__B 0 +#define QAM_DQ_TAP_IM_EL13_TAP__W 12 +#define QAM_DQ_TAP_IM_EL13_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL13_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL14__A 0x144003C +#define QAM_DQ_TAP_RE_EL14__W 12 +#define QAM_DQ_TAP_RE_EL14__M 0xFFF +#define QAM_DQ_TAP_RE_EL14__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL14_TAP__B 0 +#define QAM_DQ_TAP_RE_EL14_TAP__W 12 +#define QAM_DQ_TAP_RE_EL14_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL14_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL14__A 0x144003D +#define QAM_DQ_TAP_IM_EL14__W 12 +#define QAM_DQ_TAP_IM_EL14__M 0xFFF +#define QAM_DQ_TAP_IM_EL14__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL14_TAP__B 0 +#define QAM_DQ_TAP_IM_EL14_TAP__W 12 +#define QAM_DQ_TAP_IM_EL14_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL14_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL15__A 0x144003E +#define QAM_DQ_TAP_RE_EL15__W 12 +#define QAM_DQ_TAP_RE_EL15__M 0xFFF +#define QAM_DQ_TAP_RE_EL15__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL15_TAP__B 0 +#define QAM_DQ_TAP_RE_EL15_TAP__W 12 +#define QAM_DQ_TAP_RE_EL15_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL15_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL15__A 0x144003F +#define QAM_DQ_TAP_IM_EL15__W 12 +#define QAM_DQ_TAP_IM_EL15__M 0xFFF +#define QAM_DQ_TAP_IM_EL15__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL15_TAP__B 0 +#define QAM_DQ_TAP_IM_EL15_TAP__W 12 +#define QAM_DQ_TAP_IM_EL15_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL15_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL16__A 0x1440040 +#define QAM_DQ_TAP_RE_EL16__W 12 +#define QAM_DQ_TAP_RE_EL16__M 0xFFF +#define QAM_DQ_TAP_RE_EL16__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL16_TAP__B 0 +#define QAM_DQ_TAP_RE_EL16_TAP__W 12 +#define QAM_DQ_TAP_RE_EL16_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL16_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL16__A 0x1440041 +#define QAM_DQ_TAP_IM_EL16__W 12 +#define QAM_DQ_TAP_IM_EL16__M 0xFFF +#define QAM_DQ_TAP_IM_EL16__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL16_TAP__B 0 +#define QAM_DQ_TAP_IM_EL16_TAP__W 12 +#define QAM_DQ_TAP_IM_EL16_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL16_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL17__A 0x1440042 +#define QAM_DQ_TAP_RE_EL17__W 12 +#define QAM_DQ_TAP_RE_EL17__M 0xFFF +#define QAM_DQ_TAP_RE_EL17__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL17_TAP__B 0 +#define QAM_DQ_TAP_RE_EL17_TAP__W 12 +#define QAM_DQ_TAP_RE_EL17_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL17_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL17__A 0x1440043 +#define QAM_DQ_TAP_IM_EL17__W 12 +#define QAM_DQ_TAP_IM_EL17__M 0xFFF +#define QAM_DQ_TAP_IM_EL17__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL17_TAP__B 0 +#define QAM_DQ_TAP_IM_EL17_TAP__W 12 +#define QAM_DQ_TAP_IM_EL17_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL17_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL18__A 0x1440044 +#define QAM_DQ_TAP_RE_EL18__W 12 +#define QAM_DQ_TAP_RE_EL18__M 0xFFF +#define QAM_DQ_TAP_RE_EL18__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL18_TAP__B 0 +#define QAM_DQ_TAP_RE_EL18_TAP__W 12 +#define QAM_DQ_TAP_RE_EL18_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL18_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL18__A 0x1440045 +#define QAM_DQ_TAP_IM_EL18__W 12 +#define QAM_DQ_TAP_IM_EL18__M 0xFFF +#define QAM_DQ_TAP_IM_EL18__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL18_TAP__B 0 +#define QAM_DQ_TAP_IM_EL18_TAP__W 12 +#define QAM_DQ_TAP_IM_EL18_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL18_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL19__A 0x1440046 +#define QAM_DQ_TAP_RE_EL19__W 12 +#define QAM_DQ_TAP_RE_EL19__M 0xFFF +#define QAM_DQ_TAP_RE_EL19__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL19_TAP__B 0 +#define QAM_DQ_TAP_RE_EL19_TAP__W 12 +#define QAM_DQ_TAP_RE_EL19_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL19_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL19__A 0x1440047 +#define QAM_DQ_TAP_IM_EL19__W 12 +#define QAM_DQ_TAP_IM_EL19__M 0xFFF +#define QAM_DQ_TAP_IM_EL19__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL19_TAP__B 0 +#define QAM_DQ_TAP_IM_EL19_TAP__W 12 +#define QAM_DQ_TAP_IM_EL19_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL19_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL20__A 0x1440048 +#define QAM_DQ_TAP_RE_EL20__W 12 +#define QAM_DQ_TAP_RE_EL20__M 0xFFF +#define QAM_DQ_TAP_RE_EL20__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL20_TAP__B 0 +#define QAM_DQ_TAP_RE_EL20_TAP__W 12 +#define QAM_DQ_TAP_RE_EL20_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL20_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL20__A 0x1440049 +#define QAM_DQ_TAP_IM_EL20__W 12 +#define QAM_DQ_TAP_IM_EL20__M 0xFFF +#define QAM_DQ_TAP_IM_EL20__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL20_TAP__B 0 +#define QAM_DQ_TAP_IM_EL20_TAP__W 12 +#define QAM_DQ_TAP_IM_EL20_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL20_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL21__A 0x144004A +#define QAM_DQ_TAP_RE_EL21__W 12 +#define QAM_DQ_TAP_RE_EL21__M 0xFFF +#define QAM_DQ_TAP_RE_EL21__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL21_TAP__B 0 +#define QAM_DQ_TAP_RE_EL21_TAP__W 12 +#define QAM_DQ_TAP_RE_EL21_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL21_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL21__A 0x144004B +#define QAM_DQ_TAP_IM_EL21__W 12 +#define QAM_DQ_TAP_IM_EL21__M 0xFFF +#define QAM_DQ_TAP_IM_EL21__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL21_TAP__B 0 +#define QAM_DQ_TAP_IM_EL21_TAP__W 12 +#define QAM_DQ_TAP_IM_EL21_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL21_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL22__A 0x144004C +#define QAM_DQ_TAP_RE_EL22__W 12 +#define QAM_DQ_TAP_RE_EL22__M 0xFFF +#define QAM_DQ_TAP_RE_EL22__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL22_TAP__B 0 +#define QAM_DQ_TAP_RE_EL22_TAP__W 12 +#define QAM_DQ_TAP_RE_EL22_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL22_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL22__A 0x144004D +#define QAM_DQ_TAP_IM_EL22__W 12 +#define QAM_DQ_TAP_IM_EL22__M 0xFFF +#define QAM_DQ_TAP_IM_EL22__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL22_TAP__B 0 +#define QAM_DQ_TAP_IM_EL22_TAP__W 12 +#define QAM_DQ_TAP_IM_EL22_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL22_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL23__A 0x144004E +#define QAM_DQ_TAP_RE_EL23__W 12 +#define QAM_DQ_TAP_RE_EL23__M 0xFFF +#define QAM_DQ_TAP_RE_EL23__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL23_TAP__B 0 +#define QAM_DQ_TAP_RE_EL23_TAP__W 12 +#define QAM_DQ_TAP_RE_EL23_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL23_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL23__A 0x144004F +#define QAM_DQ_TAP_IM_EL23__W 12 +#define QAM_DQ_TAP_IM_EL23__M 0xFFF +#define QAM_DQ_TAP_IM_EL23__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL23_TAP__B 0 +#define QAM_DQ_TAP_IM_EL23_TAP__W 12 +#define QAM_DQ_TAP_IM_EL23_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL23_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL24__A 0x1440050 +#define QAM_DQ_TAP_RE_EL24__W 12 +#define QAM_DQ_TAP_RE_EL24__M 0xFFF +#define QAM_DQ_TAP_RE_EL24__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL24_TAP__B 0 +#define QAM_DQ_TAP_RE_EL24_TAP__W 12 +#define QAM_DQ_TAP_RE_EL24_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL24_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL24__A 0x1440051 +#define QAM_DQ_TAP_IM_EL24__W 12 +#define QAM_DQ_TAP_IM_EL24__M 0xFFF +#define QAM_DQ_TAP_IM_EL24__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL24_TAP__B 0 +#define QAM_DQ_TAP_IM_EL24_TAP__W 12 +#define QAM_DQ_TAP_IM_EL24_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL24_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL25__A 0x1440052 +#define QAM_DQ_TAP_RE_EL25__W 12 +#define QAM_DQ_TAP_RE_EL25__M 0xFFF +#define QAM_DQ_TAP_RE_EL25__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL25_TAP__B 0 +#define QAM_DQ_TAP_RE_EL25_TAP__W 12 +#define QAM_DQ_TAP_RE_EL25_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL25_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL25__A 0x1440053 +#define QAM_DQ_TAP_IM_EL25__W 12 +#define QAM_DQ_TAP_IM_EL25__M 0xFFF +#define QAM_DQ_TAP_IM_EL25__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL25_TAP__B 0 +#define QAM_DQ_TAP_IM_EL25_TAP__W 12 +#define QAM_DQ_TAP_IM_EL25_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL25_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL26__A 0x1440054 +#define QAM_DQ_TAP_RE_EL26__W 12 +#define QAM_DQ_TAP_RE_EL26__M 0xFFF +#define QAM_DQ_TAP_RE_EL26__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL26_TAP__B 0 +#define QAM_DQ_TAP_RE_EL26_TAP__W 12 +#define QAM_DQ_TAP_RE_EL26_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL26_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL26__A 0x1440055 +#define QAM_DQ_TAP_IM_EL26__W 12 +#define QAM_DQ_TAP_IM_EL26__M 0xFFF +#define QAM_DQ_TAP_IM_EL26__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL26_TAP__B 0 +#define QAM_DQ_TAP_IM_EL26_TAP__W 12 +#define QAM_DQ_TAP_IM_EL26_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL26_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL27__A 0x1440056 +#define QAM_DQ_TAP_RE_EL27__W 12 +#define QAM_DQ_TAP_RE_EL27__M 0xFFF +#define QAM_DQ_TAP_RE_EL27__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL27_TAP__B 0 +#define QAM_DQ_TAP_RE_EL27_TAP__W 12 +#define QAM_DQ_TAP_RE_EL27_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL27_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL27__A 0x1440057 +#define QAM_DQ_TAP_IM_EL27__W 12 +#define QAM_DQ_TAP_IM_EL27__M 0xFFF +#define QAM_DQ_TAP_IM_EL27__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL27_TAP__B 0 +#define QAM_DQ_TAP_IM_EL27_TAP__W 12 +#define QAM_DQ_TAP_IM_EL27_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL27_TAP__PRE 0x2 + + + +#define QAM_LC_COMM_EXEC__A 0x1450000 +#define QAM_LC_COMM_EXEC__W 2 +#define QAM_LC_COMM_EXEC__M 0x3 +#define QAM_LC_COMM_EXEC__PRE 0x0 +#define QAM_LC_COMM_EXEC_STOP 0x0 +#define QAM_LC_COMM_EXEC_ACTIVE 0x1 +#define QAM_LC_COMM_EXEC_HOLD 0x2 + +#define QAM_LC_COMM_MB__A 0x1450002 +#define QAM_LC_COMM_MB__W 2 +#define QAM_LC_COMM_MB__M 0x3 +#define QAM_LC_COMM_MB__PRE 0x0 +#define QAM_LC_COMM_MB_CTL__B 0 +#define QAM_LC_COMM_MB_CTL__W 1 +#define QAM_LC_COMM_MB_CTL__M 0x1 +#define QAM_LC_COMM_MB_CTL__PRE 0x0 +#define QAM_LC_COMM_MB_CTL_OFF 0x0 +#define QAM_LC_COMM_MB_CTL_ON 0x1 +#define QAM_LC_COMM_MB_OBS__B 1 +#define QAM_LC_COMM_MB_OBS__W 1 +#define QAM_LC_COMM_MB_OBS__M 0x2 +#define QAM_LC_COMM_MB_OBS__PRE 0x0 +#define QAM_LC_COMM_MB_OBS_OFF 0x0 +#define QAM_LC_COMM_MB_OBS_ON 0x2 + +#define QAM_LC_COMM_INT_REQ__A 0x1450003 +#define QAM_LC_COMM_INT_REQ__W 1 +#define QAM_LC_COMM_INT_REQ__M 0x1 +#define QAM_LC_COMM_INT_REQ__PRE 0x0 +#define QAM_LC_COMM_INT_STA__A 0x1450005 +#define QAM_LC_COMM_INT_STA__W 3 +#define QAM_LC_COMM_INT_STA__M 0x7 +#define QAM_LC_COMM_INT_STA__PRE 0x0 + +#define QAM_LC_COMM_INT_STA_READY__B 0 +#define QAM_LC_COMM_INT_STA_READY__W 1 +#define QAM_LC_COMM_INT_STA_READY__M 0x1 +#define QAM_LC_COMM_INT_STA_READY__PRE 0x0 + +#define QAM_LC_COMM_INT_STA_OVERFLOW__B 1 +#define QAM_LC_COMM_INT_STA_OVERFLOW__W 1 +#define QAM_LC_COMM_INT_STA_OVERFLOW__M 0x2 +#define QAM_LC_COMM_INT_STA_OVERFLOW__PRE 0x0 + +#define QAM_LC_COMM_INT_STA_FREQ_WRAP__B 2 +#define QAM_LC_COMM_INT_STA_FREQ_WRAP__W 1 +#define QAM_LC_COMM_INT_STA_FREQ_WRAP__M 0x4 +#define QAM_LC_COMM_INT_STA_FREQ_WRAP__PRE 0x0 + +#define QAM_LC_COMM_INT_MSK__A 0x1450006 +#define QAM_LC_COMM_INT_MSK__W 3 +#define QAM_LC_COMM_INT_MSK__M 0x7 +#define QAM_LC_COMM_INT_MSK__PRE 0x0 +#define QAM_LC_COMM_INT_MSK_READY__B 0 +#define QAM_LC_COMM_INT_MSK_READY__W 1 +#define QAM_LC_COMM_INT_MSK_READY__M 0x1 +#define QAM_LC_COMM_INT_MSK_READY__PRE 0x0 +#define QAM_LC_COMM_INT_MSK_OVERFLOW__B 1 +#define QAM_LC_COMM_INT_MSK_OVERFLOW__W 1 +#define QAM_LC_COMM_INT_MSK_OVERFLOW__M 0x2 +#define QAM_LC_COMM_INT_MSK_OVERFLOW__PRE 0x0 +#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__B 2 +#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__W 1 +#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__M 0x4 +#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__PRE 0x0 + +#define QAM_LC_COMM_INT_STM__A 0x1450007 +#define QAM_LC_COMM_INT_STM__W 3 +#define QAM_LC_COMM_INT_STM__M 0x7 +#define QAM_LC_COMM_INT_STM__PRE 0x0 +#define QAM_LC_COMM_INT_STM_READY__B 0 +#define QAM_LC_COMM_INT_STM_READY__W 1 +#define QAM_LC_COMM_INT_STM_READY__M 0x1 +#define QAM_LC_COMM_INT_STM_READY__PRE 0x0 +#define QAM_LC_COMM_INT_STM_OVERFLOW__B 1 +#define QAM_LC_COMM_INT_STM_OVERFLOW__W 1 +#define QAM_LC_COMM_INT_STM_OVERFLOW__M 0x2 +#define QAM_LC_COMM_INT_STM_OVERFLOW__PRE 0x0 +#define QAM_LC_COMM_INT_STM_FREQ_WRAP__B 2 +#define QAM_LC_COMM_INT_STM_FREQ_WRAP__W 1 +#define QAM_LC_COMM_INT_STM_FREQ_WRAP__M 0x4 +#define QAM_LC_COMM_INT_STM_FREQ_WRAP__PRE 0x0 + +#define QAM_LC_MODE__A 0x1450010 +#define QAM_LC_MODE__W 3 +#define QAM_LC_MODE__M 0x7 +#define QAM_LC_MODE__PRE 0x7 + +#define QAM_LC_MODE_ENABLE_A__B 0 +#define QAM_LC_MODE_ENABLE_A__W 1 +#define QAM_LC_MODE_ENABLE_A__M 0x1 +#define QAM_LC_MODE_ENABLE_A__PRE 0x1 + +#define QAM_LC_MODE_ENABLE_F__B 1 +#define QAM_LC_MODE_ENABLE_F__W 1 +#define QAM_LC_MODE_ENABLE_F__M 0x2 +#define QAM_LC_MODE_ENABLE_F__PRE 0x2 + +#define QAM_LC_MODE_ENABLE_R__B 2 +#define QAM_LC_MODE_ENABLE_R__W 1 +#define QAM_LC_MODE_ENABLE_R__M 0x4 +#define QAM_LC_MODE_ENABLE_R__PRE 0x4 + +#define QAM_LC_CA__A 0x1450011 +#define QAM_LC_CA__W 6 +#define QAM_LC_CA__M 0x3F +#define QAM_LC_CA__PRE 0x28 + +#define QAM_LC_CA_COEF__B 0 +#define QAM_LC_CA_COEF__W 6 +#define QAM_LC_CA_COEF__M 0x3F +#define QAM_LC_CA_COEF__PRE 0x28 + +#define QAM_LC_CF__A 0x1450012 +#define QAM_LC_CF__W 8 +#define QAM_LC_CF__M 0xFF +#define QAM_LC_CF__PRE 0x8C + +#define QAM_LC_CF_COEF__B 0 +#define QAM_LC_CF_COEF__W 8 +#define QAM_LC_CF_COEF__M 0xFF +#define QAM_LC_CF_COEF__PRE 0x8C + +#define QAM_LC_CF1__A 0x1450013 +#define QAM_LC_CF1__W 8 +#define QAM_LC_CF1__M 0xFF +#define QAM_LC_CF1__PRE 0x1E + +#define QAM_LC_CF1_COEF__B 0 +#define QAM_LC_CF1_COEF__W 8 +#define QAM_LC_CF1_COEF__M 0xFF +#define QAM_LC_CF1_COEF__PRE 0x1E + +#define QAM_LC_CP__A 0x1450014 +#define QAM_LC_CP__W 8 +#define QAM_LC_CP__M 0xFF +#define QAM_LC_CP__PRE 0x78 + +#define QAM_LC_CP_COEF__B 0 +#define QAM_LC_CP_COEF__W 8 +#define QAM_LC_CP_COEF__M 0xFF +#define QAM_LC_CP_COEF__PRE 0x78 + +#define QAM_LC_CI__A 0x1450015 +#define QAM_LC_CI__W 8 +#define QAM_LC_CI__M 0xFF +#define QAM_LC_CI__PRE 0x46 + +#define QAM_LC_CI_COEF__B 0 +#define QAM_LC_CI_COEF__W 8 +#define QAM_LC_CI_COEF__M 0xFF +#define QAM_LC_CI_COEF__PRE 0x46 + +#define QAM_LC_EP__A 0x1450016 +#define QAM_LC_EP__W 6 +#define QAM_LC_EP__M 0x3F +#define QAM_LC_EP__PRE 0x0 + +#define QAM_LC_EP_COEF__B 0 +#define QAM_LC_EP_COEF__W 6 +#define QAM_LC_EP_COEF__M 0x3F +#define QAM_LC_EP_COEF__PRE 0x0 + +#define QAM_LC_EI__A 0x1450017 +#define QAM_LC_EI__W 6 +#define QAM_LC_EI__M 0x3F +#define QAM_LC_EI__PRE 0x0 + +#define QAM_LC_EI_COEF__B 0 +#define QAM_LC_EI_COEF__W 6 +#define QAM_LC_EI_COEF__M 0x3F +#define QAM_LC_EI_COEF__PRE 0x0 + +#define QAM_LC_QUAL_TAB0__A 0x1450018 +#define QAM_LC_QUAL_TAB0__W 5 +#define QAM_LC_QUAL_TAB0__M 0x1F +#define QAM_LC_QUAL_TAB0__PRE 0x1 + +#define QAM_LC_QUAL_TAB0_VALUE__B 0 +#define QAM_LC_QUAL_TAB0_VALUE__W 5 +#define QAM_LC_QUAL_TAB0_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB0_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB1__A 0x1450019 +#define QAM_LC_QUAL_TAB1__W 5 +#define QAM_LC_QUAL_TAB1__M 0x1F +#define QAM_LC_QUAL_TAB1__PRE 0x1 + +#define QAM_LC_QUAL_TAB1_VALUE__B 0 +#define QAM_LC_QUAL_TAB1_VALUE__W 5 +#define QAM_LC_QUAL_TAB1_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB1_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB2__A 0x145001A +#define QAM_LC_QUAL_TAB2__W 5 +#define QAM_LC_QUAL_TAB2__M 0x1F +#define QAM_LC_QUAL_TAB2__PRE 0x1 + +#define QAM_LC_QUAL_TAB2_VALUE__B 0 +#define QAM_LC_QUAL_TAB2_VALUE__W 5 +#define QAM_LC_QUAL_TAB2_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB2_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB3__A 0x145001B +#define QAM_LC_QUAL_TAB3__W 5 +#define QAM_LC_QUAL_TAB3__M 0x1F +#define QAM_LC_QUAL_TAB3__PRE 0x1 + +#define QAM_LC_QUAL_TAB3_VALUE__B 0 +#define QAM_LC_QUAL_TAB3_VALUE__W 5 +#define QAM_LC_QUAL_TAB3_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB3_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB4__A 0x145001C +#define QAM_LC_QUAL_TAB4__W 5 +#define QAM_LC_QUAL_TAB4__M 0x1F +#define QAM_LC_QUAL_TAB4__PRE 0x1 + +#define QAM_LC_QUAL_TAB4_VALUE__B 0 +#define QAM_LC_QUAL_TAB4_VALUE__W 5 +#define QAM_LC_QUAL_TAB4_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB4_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB5__A 0x145001D +#define QAM_LC_QUAL_TAB5__W 5 +#define QAM_LC_QUAL_TAB5__M 0x1F +#define QAM_LC_QUAL_TAB5__PRE 0x1 + +#define QAM_LC_QUAL_TAB5_VALUE__B 0 +#define QAM_LC_QUAL_TAB5_VALUE__W 5 +#define QAM_LC_QUAL_TAB5_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB5_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB6__A 0x145001E +#define QAM_LC_QUAL_TAB6__W 5 +#define QAM_LC_QUAL_TAB6__M 0x1F +#define QAM_LC_QUAL_TAB6__PRE 0x1 + +#define QAM_LC_QUAL_TAB6_VALUE__B 0 +#define QAM_LC_QUAL_TAB6_VALUE__W 5 +#define QAM_LC_QUAL_TAB6_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB6_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB8__A 0x145001F +#define QAM_LC_QUAL_TAB8__W 5 +#define QAM_LC_QUAL_TAB8__M 0x1F +#define QAM_LC_QUAL_TAB8__PRE 0x1 + +#define QAM_LC_QUAL_TAB8_VALUE__B 0 +#define QAM_LC_QUAL_TAB8_VALUE__W 5 +#define QAM_LC_QUAL_TAB8_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB8_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB9__A 0x1450020 +#define QAM_LC_QUAL_TAB9__W 5 +#define QAM_LC_QUAL_TAB9__M 0x1F +#define QAM_LC_QUAL_TAB9__PRE 0x1 + +#define QAM_LC_QUAL_TAB9_VALUE__B 0 +#define QAM_LC_QUAL_TAB9_VALUE__W 5 +#define QAM_LC_QUAL_TAB9_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB9_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB10__A 0x1450021 +#define QAM_LC_QUAL_TAB10__W 5 +#define QAM_LC_QUAL_TAB10__M 0x1F +#define QAM_LC_QUAL_TAB10__PRE 0x1 + +#define QAM_LC_QUAL_TAB10_VALUE__B 0 +#define QAM_LC_QUAL_TAB10_VALUE__W 5 +#define QAM_LC_QUAL_TAB10_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB10_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB12__A 0x1450022 +#define QAM_LC_QUAL_TAB12__W 5 +#define QAM_LC_QUAL_TAB12__M 0x1F +#define QAM_LC_QUAL_TAB12__PRE 0x1 + +#define QAM_LC_QUAL_TAB12_VALUE__B 0 +#define QAM_LC_QUAL_TAB12_VALUE__W 5 +#define QAM_LC_QUAL_TAB12_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB12_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB15__A 0x1450023 +#define QAM_LC_QUAL_TAB15__W 5 +#define QAM_LC_QUAL_TAB15__M 0x1F +#define QAM_LC_QUAL_TAB15__PRE 0x1 + +#define QAM_LC_QUAL_TAB15_VALUE__B 0 +#define QAM_LC_QUAL_TAB15_VALUE__W 5 +#define QAM_LC_QUAL_TAB15_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB15_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB16__A 0x1450024 +#define QAM_LC_QUAL_TAB16__W 5 +#define QAM_LC_QUAL_TAB16__M 0x1F +#define QAM_LC_QUAL_TAB16__PRE 0x1 + +#define QAM_LC_QUAL_TAB16_VALUE__B 0 +#define QAM_LC_QUAL_TAB16_VALUE__W 5 +#define QAM_LC_QUAL_TAB16_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB16_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB20__A 0x1450025 +#define QAM_LC_QUAL_TAB20__W 5 +#define QAM_LC_QUAL_TAB20__M 0x1F +#define QAM_LC_QUAL_TAB20__PRE 0x1 + +#define QAM_LC_QUAL_TAB20_VALUE__B 0 +#define QAM_LC_QUAL_TAB20_VALUE__W 5 +#define QAM_LC_QUAL_TAB20_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB20_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB25__A 0x1450026 +#define QAM_LC_QUAL_TAB25__W 5 +#define QAM_LC_QUAL_TAB25__M 0x1F +#define QAM_LC_QUAL_TAB25__PRE 0x1 + +#define QAM_LC_QUAL_TAB25_VALUE__B 0 +#define QAM_LC_QUAL_TAB25_VALUE__W 5 +#define QAM_LC_QUAL_TAB25_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB25_VALUE__PRE 0x1 + +#define QAM_LC_EQ_TIMING__A 0x1450027 +#define QAM_LC_EQ_TIMING__W 10 +#define QAM_LC_EQ_TIMING__M 0x3FF +#define QAM_LC_EQ_TIMING__PRE 0x0 + +#define QAM_LC_EQ_TIMING_OFFS__B 0 +#define QAM_LC_EQ_TIMING_OFFS__W 10 +#define QAM_LC_EQ_TIMING_OFFS__M 0x3FF +#define QAM_LC_EQ_TIMING_OFFS__PRE 0x0 + +#define QAM_LC_LPF_FACTORP__A 0x1450028 +#define QAM_LC_LPF_FACTORP__W 3 +#define QAM_LC_LPF_FACTORP__M 0x7 +#define QAM_LC_LPF_FACTORP__PRE 0x3 + +#define QAM_LC_LPF_FACTORP_FACTOR__B 0 +#define QAM_LC_LPF_FACTORP_FACTOR__W 3 +#define QAM_LC_LPF_FACTORP_FACTOR__M 0x7 +#define QAM_LC_LPF_FACTORP_FACTOR__PRE 0x3 + +#define QAM_LC_LPF_FACTORI__A 0x1450029 +#define QAM_LC_LPF_FACTORI__W 3 +#define QAM_LC_LPF_FACTORI__M 0x7 +#define QAM_LC_LPF_FACTORI__PRE 0x3 + +#define QAM_LC_LPF_FACTORI_FACTOR__B 0 +#define QAM_LC_LPF_FACTORI_FACTOR__W 3 +#define QAM_LC_LPF_FACTORI_FACTOR__M 0x7 +#define QAM_LC_LPF_FACTORI_FACTOR__PRE 0x3 + +#define QAM_LC_RATE_LIMIT__A 0x145002A +#define QAM_LC_RATE_LIMIT__W 2 +#define QAM_LC_RATE_LIMIT__M 0x3 +#define QAM_LC_RATE_LIMIT__PRE 0x3 + +#define QAM_LC_RATE_LIMIT_LIMIT__B 0 +#define QAM_LC_RATE_LIMIT_LIMIT__W 2 +#define QAM_LC_RATE_LIMIT_LIMIT__M 0x3 +#define QAM_LC_RATE_LIMIT_LIMIT__PRE 0x3 + +#define QAM_LC_SYMBOL_FREQ__A 0x145002B +#define QAM_LC_SYMBOL_FREQ__W 10 +#define QAM_LC_SYMBOL_FREQ__M 0x3FF +#define QAM_LC_SYMBOL_FREQ__PRE 0x199 + +#define QAM_LC_SYMBOL_FREQ_FREQ__B 0 +#define QAM_LC_SYMBOL_FREQ_FREQ__W 10 +#define QAM_LC_SYMBOL_FREQ_FREQ__M 0x3FF +#define QAM_LC_SYMBOL_FREQ_FREQ__PRE 0x199 +#define QAM_LC_SYMBOL_FREQ_FREQ_QAM_B_64 0x197 +#define QAM_LC_SYMBOL_FREQ_FREQ_QAM_B_256 0x1B2 + +#define QAM_LC_MTA_LENGTH__A 0x145002C +#define QAM_LC_MTA_LENGTH__W 2 +#define QAM_LC_MTA_LENGTH__M 0x3 +#define QAM_LC_MTA_LENGTH__PRE 0x2 + +#define QAM_LC_MTA_LENGTH_LENGTH__B 0 +#define QAM_LC_MTA_LENGTH_LENGTH__W 2 +#define QAM_LC_MTA_LENGTH_LENGTH__M 0x3 +#define QAM_LC_MTA_LENGTH_LENGTH__PRE 0x2 + +#define QAM_LC_AMP_ACCU__A 0x145002D +#define QAM_LC_AMP_ACCU__W 14 +#define QAM_LC_AMP_ACCU__M 0x3FFF +#define QAM_LC_AMP_ACCU__PRE 0x600 + +#define QAM_LC_AMP_ACCU_ACCU__B 0 +#define QAM_LC_AMP_ACCU_ACCU__W 14 +#define QAM_LC_AMP_ACCU_ACCU__M 0x3FFF +#define QAM_LC_AMP_ACCU_ACCU__PRE 0x600 + +#define QAM_LC_FREQ_ACCU__A 0x145002E +#define QAM_LC_FREQ_ACCU__W 10 +#define QAM_LC_FREQ_ACCU__M 0x3FF +#define QAM_LC_FREQ_ACCU__PRE 0x0 + +#define QAM_LC_FREQ_ACCU_ACCU__B 0 +#define QAM_LC_FREQ_ACCU_ACCU__W 10 +#define QAM_LC_FREQ_ACCU_ACCU__M 0x3FF +#define QAM_LC_FREQ_ACCU_ACCU__PRE 0x0 + +#define QAM_LC_RATE_ACCU__A 0x145002F +#define QAM_LC_RATE_ACCU__W 10 +#define QAM_LC_RATE_ACCU__M 0x3FF +#define QAM_LC_RATE_ACCU__PRE 0x0 + +#define QAM_LC_RATE_ACCU_ACCU__B 0 +#define QAM_LC_RATE_ACCU_ACCU__W 10 +#define QAM_LC_RATE_ACCU_ACCU__M 0x3FF +#define QAM_LC_RATE_ACCU_ACCU__PRE 0x0 + +#define QAM_LC_AMPLITUDE__A 0x1450030 +#define QAM_LC_AMPLITUDE__W 10 +#define QAM_LC_AMPLITUDE__M 0x3FF +#define QAM_LC_AMPLITUDE__PRE 0x0 + +#define QAM_LC_AMPLITUDE_SIZE__B 0 +#define QAM_LC_AMPLITUDE_SIZE__W 10 +#define QAM_LC_AMPLITUDE_SIZE__M 0x3FF +#define QAM_LC_AMPLITUDE_SIZE__PRE 0x0 + +#define QAM_LC_RAD_ERROR__A 0x1450031 +#define QAM_LC_RAD_ERROR__W 10 +#define QAM_LC_RAD_ERROR__M 0x3FF +#define QAM_LC_RAD_ERROR__PRE 0x0 + +#define QAM_LC_RAD_ERROR_SIZE__B 0 +#define QAM_LC_RAD_ERROR_SIZE__W 10 +#define QAM_LC_RAD_ERROR_SIZE__M 0x3FF +#define QAM_LC_RAD_ERROR_SIZE__PRE 0x0 + +#define QAM_LC_FREQ_OFFS__A 0x1450032 +#define QAM_LC_FREQ_OFFS__W 10 +#define QAM_LC_FREQ_OFFS__M 0x3FF +#define QAM_LC_FREQ_OFFS__PRE 0x0 + +#define QAM_LC_FREQ_OFFS_OFFS__B 0 +#define QAM_LC_FREQ_OFFS_OFFS__W 10 +#define QAM_LC_FREQ_OFFS_OFFS__M 0x3FF +#define QAM_LC_FREQ_OFFS_OFFS__PRE 0x0 + +#define QAM_LC_PHASE_ERROR__A 0x1450033 +#define QAM_LC_PHASE_ERROR__W 10 +#define QAM_LC_PHASE_ERROR__M 0x3FF +#define QAM_LC_PHASE_ERROR__PRE 0x0 + +#define QAM_LC_PHASE_ERROR_SIZE__B 0 +#define QAM_LC_PHASE_ERROR_SIZE__W 10 +#define QAM_LC_PHASE_ERROR_SIZE__M 0x3FF +#define QAM_LC_PHASE_ERROR_SIZE__PRE 0x0 + + + +#define QAM_VD_COMM_EXEC__A 0x1460000 +#define QAM_VD_COMM_EXEC__W 2 +#define QAM_VD_COMM_EXEC__M 0x3 +#define QAM_VD_COMM_EXEC__PRE 0x0 +#define QAM_VD_COMM_EXEC_STOP 0x0 +#define QAM_VD_COMM_EXEC_ACTIVE 0x1 +#define QAM_VD_COMM_EXEC_HOLD 0x2 + +#define QAM_VD_COMM_MB__A 0x1460002 +#define QAM_VD_COMM_MB__W 2 +#define QAM_VD_COMM_MB__M 0x3 +#define QAM_VD_COMM_MB__PRE 0x0 +#define QAM_VD_COMM_MB_CTL__B 0 +#define QAM_VD_COMM_MB_CTL__W 1 +#define QAM_VD_COMM_MB_CTL__M 0x1 +#define QAM_VD_COMM_MB_CTL__PRE 0x0 +#define QAM_VD_COMM_MB_CTL_OFF 0x0 +#define QAM_VD_COMM_MB_CTL_ON 0x1 +#define QAM_VD_COMM_MB_OBS__B 1 +#define QAM_VD_COMM_MB_OBS__W 1 +#define QAM_VD_COMM_MB_OBS__M 0x2 +#define QAM_VD_COMM_MB_OBS__PRE 0x0 +#define QAM_VD_COMM_MB_OBS_OFF 0x0 +#define QAM_VD_COMM_MB_OBS_ON 0x2 + +#define QAM_VD_COMM_INT_REQ__A 0x1460003 +#define QAM_VD_COMM_INT_REQ__W 1 +#define QAM_VD_COMM_INT_REQ__M 0x1 +#define QAM_VD_COMM_INT_REQ__PRE 0x0 +#define QAM_VD_COMM_INT_STA__A 0x1460005 +#define QAM_VD_COMM_INT_STA__W 2 +#define QAM_VD_COMM_INT_STA__M 0x3 +#define QAM_VD_COMM_INT_STA__PRE 0x0 + +#define QAM_VD_COMM_INT_STA_LOCK_INT__B 0 +#define QAM_VD_COMM_INT_STA_LOCK_INT__W 1 +#define QAM_VD_COMM_INT_STA_LOCK_INT__M 0x1 +#define QAM_VD_COMM_INT_STA_LOCK_INT__PRE 0x0 + +#define QAM_VD_COMM_INT_STA_PERIOD_INT__B 1 +#define QAM_VD_COMM_INT_STA_PERIOD_INT__W 1 +#define QAM_VD_COMM_INT_STA_PERIOD_INT__M 0x2 +#define QAM_VD_COMM_INT_STA_PERIOD_INT__PRE 0x0 + +#define QAM_VD_COMM_INT_MSK__A 0x1460006 +#define QAM_VD_COMM_INT_MSK__W 2 +#define QAM_VD_COMM_INT_MSK__M 0x3 +#define QAM_VD_COMM_INT_MSK__PRE 0x0 +#define QAM_VD_COMM_INT_MSK_LOCK_INT__B 0 +#define QAM_VD_COMM_INT_MSK_LOCK_INT__W 1 +#define QAM_VD_COMM_INT_MSK_LOCK_INT__M 0x1 +#define QAM_VD_COMM_INT_MSK_LOCK_INT__PRE 0x0 +#define QAM_VD_COMM_INT_MSK_PERIOD_INT__B 1 +#define QAM_VD_COMM_INT_MSK_PERIOD_INT__W 1 +#define QAM_VD_COMM_INT_MSK_PERIOD_INT__M 0x2 +#define QAM_VD_COMM_INT_MSK_PERIOD_INT__PRE 0x0 + +#define QAM_VD_COMM_INT_STM__A 0x1460007 +#define QAM_VD_COMM_INT_STM__W 2 +#define QAM_VD_COMM_INT_STM__M 0x3 +#define QAM_VD_COMM_INT_STM__PRE 0x0 +#define QAM_VD_COMM_INT_STM_LOCK_INT__B 0 +#define QAM_VD_COMM_INT_STM_LOCK_INT__W 1 +#define QAM_VD_COMM_INT_STM_LOCK_INT__M 0x1 +#define QAM_VD_COMM_INT_STM_LOCK_INT__PRE 0x0 +#define QAM_VD_COMM_INT_STM_PERIOD_INT__B 1 +#define QAM_VD_COMM_INT_STM_PERIOD_INT__W 1 +#define QAM_VD_COMM_INT_STM_PERIOD_INT__M 0x2 +#define QAM_VD_COMM_INT_STM_PERIOD_INT__PRE 0x0 + +#define QAM_VD_STATUS__A 0x1460010 +#define QAM_VD_STATUS__W 1 +#define QAM_VD_STATUS__M 0x1 +#define QAM_VD_STATUS__PRE 0x0 + +#define QAM_VD_STATUS_LOCK__B 0 +#define QAM_VD_STATUS_LOCK__W 1 +#define QAM_VD_STATUS_LOCK__M 0x1 +#define QAM_VD_STATUS_LOCK__PRE 0x0 + +#define QAM_VD_UNLOCK_CONTROL__A 0x1460011 +#define QAM_VD_UNLOCK_CONTROL__W 1 +#define QAM_VD_UNLOCK_CONTROL__M 0x1 +#define QAM_VD_UNLOCK_CONTROL__PRE 0x0 + +#define QAM_VD_UNLOCK_CONTROL_UNLOCK_CTRL__B 0 +#define QAM_VD_UNLOCK_CONTROL_UNLOCK_CTRL__W 1 +#define QAM_VD_UNLOCK_CONTROL_UNLOCK_CTRL__M 0x1 +#define QAM_VD_UNLOCK_CONTROL_UNLOCK_CTRL__PRE 0x0 + +#define QAM_VD_MIN_VOTING_ROUNDS__A 0x1460012 +#define QAM_VD_MIN_VOTING_ROUNDS__W 6 +#define QAM_VD_MIN_VOTING_ROUNDS__M 0x3F +#define QAM_VD_MIN_VOTING_ROUNDS__PRE 0x10 + +#define QAM_VD_MIN_VOTING_ROUNDS_ROUNDS__B 0 +#define QAM_VD_MIN_VOTING_ROUNDS_ROUNDS__W 6 +#define QAM_VD_MIN_VOTING_ROUNDS_ROUNDS__M 0x3F +#define QAM_VD_MIN_VOTING_ROUNDS_ROUNDS__PRE 0x10 + +#define QAM_VD_MAX_VOTING_ROUNDS__A 0x1460013 +#define QAM_VD_MAX_VOTING_ROUNDS__W 6 +#define QAM_VD_MAX_VOTING_ROUNDS__M 0x3F +#define QAM_VD_MAX_VOTING_ROUNDS__PRE 0x10 + +#define QAM_VD_MAX_VOTING_ROUNDS_ROUNDS__B 0 +#define QAM_VD_MAX_VOTING_ROUNDS_ROUNDS__W 6 +#define QAM_VD_MAX_VOTING_ROUNDS_ROUNDS__M 0x3F +#define QAM_VD_MAX_VOTING_ROUNDS_ROUNDS__PRE 0x10 + +#define QAM_VD_TRACEBACK_DEPTH__A 0x1460014 +#define QAM_VD_TRACEBACK_DEPTH__W 5 +#define QAM_VD_TRACEBACK_DEPTH__M 0x1F +#define QAM_VD_TRACEBACK_DEPTH__PRE 0x10 + +#define QAM_VD_TRACEBACK_DEPTH_LENGTH__B 0 +#define QAM_VD_TRACEBACK_DEPTH_LENGTH__W 5 +#define QAM_VD_TRACEBACK_DEPTH_LENGTH__M 0x1F +#define QAM_VD_TRACEBACK_DEPTH_LENGTH__PRE 0x10 + + +#define QAM_VD_UNLOCK__A 0x1460015 +#define QAM_VD_UNLOCK__W 1 +#define QAM_VD_UNLOCK__M 0x1 +#define QAM_VD_UNLOCK__PRE 0x0 +#define QAM_VD_MEASUREMENT_PERIOD__A 0x1460016 +#define QAM_VD_MEASUREMENT_PERIOD__W 16 +#define QAM_VD_MEASUREMENT_PERIOD__M 0xFFFF +#define QAM_VD_MEASUREMENT_PERIOD__PRE 0x8236 + +#define QAM_VD_MEASUREMENT_PERIOD_PERIOD__B 0 +#define QAM_VD_MEASUREMENT_PERIOD_PERIOD__W 16 +#define QAM_VD_MEASUREMENT_PERIOD_PERIOD__M 0xFFFF +#define QAM_VD_MEASUREMENT_PERIOD_PERIOD__PRE 0x8236 + +#define QAM_VD_MEASUREMENT_PRESCALE__A 0x1460017 +#define QAM_VD_MEASUREMENT_PRESCALE__W 16 +#define QAM_VD_MEASUREMENT_PRESCALE__M 0xFFFF +#define QAM_VD_MEASUREMENT_PRESCALE__PRE 0x4 + +#define QAM_VD_MEASUREMENT_PRESCALE_PRESCALE__B 0 +#define QAM_VD_MEASUREMENT_PRESCALE_PRESCALE__W 16 +#define QAM_VD_MEASUREMENT_PRESCALE_PRESCALE__M 0xFFFF +#define QAM_VD_MEASUREMENT_PRESCALE_PRESCALE__PRE 0x4 + +#define QAM_VD_DELTA_PATH_METRIC__A 0x1460018 +#define QAM_VD_DELTA_PATH_METRIC__W 16 +#define QAM_VD_DELTA_PATH_METRIC__M 0xFFFF +#define QAM_VD_DELTA_PATH_METRIC__PRE 0xFFFF + +#define QAM_VD_DELTA_PATH_METRIC_FIXED_MANT__B 0 +#define QAM_VD_DELTA_PATH_METRIC_FIXED_MANT__W 12 +#define QAM_VD_DELTA_PATH_METRIC_FIXED_MANT__M 0xFFF +#define QAM_VD_DELTA_PATH_METRIC_FIXED_MANT__PRE 0xFFF + +#define QAM_VD_DELTA_PATH_METRIC_EXP__B 12 +#define QAM_VD_DELTA_PATH_METRIC_EXP__W 4 +#define QAM_VD_DELTA_PATH_METRIC_EXP__M 0xF000 +#define QAM_VD_DELTA_PATH_METRIC_EXP__PRE 0xF000 + +#define QAM_VD_NR_QSYM_ERRORS__A 0x1460019 +#define QAM_VD_NR_QSYM_ERRORS__W 16 +#define QAM_VD_NR_QSYM_ERRORS__M 0xFFFF +#define QAM_VD_NR_QSYM_ERRORS__PRE 0xFFFF + +#define QAM_VD_NR_QSYM_ERRORS_FIXED_MANT__B 0 +#define QAM_VD_NR_QSYM_ERRORS_FIXED_MANT__W 12 +#define QAM_VD_NR_QSYM_ERRORS_FIXED_MANT__M 0xFFF +#define QAM_VD_NR_QSYM_ERRORS_FIXED_MANT__PRE 0xFFF + +#define QAM_VD_NR_QSYM_ERRORS_EXP__B 12 +#define QAM_VD_NR_QSYM_ERRORS_EXP__W 4 +#define QAM_VD_NR_QSYM_ERRORS_EXP__M 0xF000 +#define QAM_VD_NR_QSYM_ERRORS_EXP__PRE 0xF000 + +#define QAM_VD_NR_SYMBOL_ERRORS__A 0x146001A +#define QAM_VD_NR_SYMBOL_ERRORS__W 16 +#define QAM_VD_NR_SYMBOL_ERRORS__M 0xFFFF +#define QAM_VD_NR_SYMBOL_ERRORS__PRE 0xFFFF + +#define QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__B 0 +#define QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__W 12 +#define QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__M 0xFFF +#define QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__PRE 0xFFF + +#define QAM_VD_NR_SYMBOL_ERRORS_EXP__B 12 +#define QAM_VD_NR_SYMBOL_ERRORS_EXP__W 4 +#define QAM_VD_NR_SYMBOL_ERRORS_EXP__M 0xF000 +#define QAM_VD_NR_SYMBOL_ERRORS_EXP__PRE 0xF000 + +#define QAM_VD_RELOCK_COUNT__A 0x146001B +#define QAM_VD_RELOCK_COUNT__W 16 +#define QAM_VD_RELOCK_COUNT__M 0xFFFF +#define QAM_VD_RELOCK_COUNT__PRE 0x0 + +#define QAM_VD_RELOCK_COUNT_COUNT__B 0 +#define QAM_VD_RELOCK_COUNT_COUNT__W 8 +#define QAM_VD_RELOCK_COUNT_COUNT__M 0xFF +#define QAM_VD_RELOCK_COUNT_COUNT__PRE 0x0 + + + +#define QAM_SY_COMM_EXEC__A 0x1470000 +#define QAM_SY_COMM_EXEC__W 2 +#define QAM_SY_COMM_EXEC__M 0x3 +#define QAM_SY_COMM_EXEC__PRE 0x0 +#define QAM_SY_COMM_EXEC_STOP 0x0 +#define QAM_SY_COMM_EXEC_ACTIVE 0x1 +#define QAM_SY_COMM_EXEC_HOLD 0x2 + +#define QAM_SY_COMM_MB__A 0x1470002 +#define QAM_SY_COMM_MB__W 2 +#define QAM_SY_COMM_MB__M 0x3 +#define QAM_SY_COMM_MB__PRE 0x0 +#define QAM_SY_COMM_MB_CTL__B 0 +#define QAM_SY_COMM_MB_CTL__W 1 +#define QAM_SY_COMM_MB_CTL__M 0x1 +#define QAM_SY_COMM_MB_CTL__PRE 0x0 +#define QAM_SY_COMM_MB_CTL_OFF 0x0 +#define QAM_SY_COMM_MB_CTL_ON 0x1 +#define QAM_SY_COMM_MB_OBS__B 1 +#define QAM_SY_COMM_MB_OBS__W 1 +#define QAM_SY_COMM_MB_OBS__M 0x2 +#define QAM_SY_COMM_MB_OBS__PRE 0x0 +#define QAM_SY_COMM_MB_OBS_OFF 0x0 +#define QAM_SY_COMM_MB_OBS_ON 0x2 + +#define QAM_SY_COMM_INT_REQ__A 0x1470003 +#define QAM_SY_COMM_INT_REQ__W 1 +#define QAM_SY_COMM_INT_REQ__M 0x1 +#define QAM_SY_COMM_INT_REQ__PRE 0x0 +#define QAM_SY_COMM_INT_STA__A 0x1470005 +#define QAM_SY_COMM_INT_STA__W 4 +#define QAM_SY_COMM_INT_STA__M 0xF +#define QAM_SY_COMM_INT_STA__PRE 0x0 + +#define QAM_SY_COMM_INT_STA_LOCK_INT__B 0 +#define QAM_SY_COMM_INT_STA_LOCK_INT__W 1 +#define QAM_SY_COMM_INT_STA_LOCK_INT__M 0x1 +#define QAM_SY_COMM_INT_STA_LOCK_INT__PRE 0x0 + +#define QAM_SY_COMM_INT_STA_UNLOCK_INT__B 1 +#define QAM_SY_COMM_INT_STA_UNLOCK_INT__W 1 +#define QAM_SY_COMM_INT_STA_UNLOCK_INT__M 0x2 +#define QAM_SY_COMM_INT_STA_UNLOCK_INT__PRE 0x0 + +#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__B 2 +#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__W 1 +#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__M 0x4 +#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__PRE 0x0 + +#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__B 3 +#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__W 1 +#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__M 0x8 +#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__PRE 0x0 + +#define QAM_SY_COMM_INT_MSK__A 0x1470006 +#define QAM_SY_COMM_INT_MSK__W 4 +#define QAM_SY_COMM_INT_MSK__M 0xF +#define QAM_SY_COMM_INT_MSK__PRE 0x0 +#define QAM_SY_COMM_INT_MSK_LOCK_MSK__B 0 +#define QAM_SY_COMM_INT_MSK_LOCK_MSK__W 1 +#define QAM_SY_COMM_INT_MSK_LOCK_MSK__M 0x1 +#define QAM_SY_COMM_INT_MSK_LOCK_MSK__PRE 0x0 +#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__B 1 +#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__W 1 +#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__M 0x2 +#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__PRE 0x0 +#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__B 2 +#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__W 1 +#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__M 0x4 +#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__PRE 0x0 +#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__B 3 +#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__W 1 +#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__M 0x8 +#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__PRE 0x0 + +#define QAM_SY_COMM_INT_STM__A 0x1470007 +#define QAM_SY_COMM_INT_STM__W 4 +#define QAM_SY_COMM_INT_STM__M 0xF +#define QAM_SY_COMM_INT_STM__PRE 0x0 +#define QAM_SY_COMM_INT_STM_LOCK_MSK__B 0 +#define QAM_SY_COMM_INT_STM_LOCK_MSK__W 1 +#define QAM_SY_COMM_INT_STM_LOCK_MSK__M 0x1 +#define QAM_SY_COMM_INT_STM_LOCK_MSK__PRE 0x0 +#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__B 1 +#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__W 1 +#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__M 0x2 +#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__PRE 0x0 +#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__B 2 +#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__W 1 +#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__M 0x4 +#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__PRE 0x0 +#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__B 3 +#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__W 1 +#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__M 0x8 +#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__PRE 0x0 + +#define QAM_SY_STATUS__A 0x1470010 +#define QAM_SY_STATUS__W 2 +#define QAM_SY_STATUS__M 0x3 +#define QAM_SY_STATUS__PRE 0x0 + +#define QAM_SY_STATUS_SYNC_STATE__B 0 +#define QAM_SY_STATUS_SYNC_STATE__W 2 +#define QAM_SY_STATUS_SYNC_STATE__M 0x3 +#define QAM_SY_STATUS_SYNC_STATE__PRE 0x0 + + +#define QAM_SY_TIMEOUT__A 0x1470011 +#define QAM_SY_TIMEOUT__W 16 +#define QAM_SY_TIMEOUT__M 0xFFFF +#define QAM_SY_TIMEOUT__PRE 0x3A98 + +#define QAM_SY_SYNC_LWM__A 0x1470012 +#define QAM_SY_SYNC_LWM__W 4 +#define QAM_SY_SYNC_LWM__M 0xF +#define QAM_SY_SYNC_LWM__PRE 0x2 + +#define QAM_SY_SYNC_AWM__A 0x1470013 +#define QAM_SY_SYNC_AWM__W 4 +#define QAM_SY_SYNC_AWM__M 0xF +#define QAM_SY_SYNC_AWM__PRE 0x3 + +#define QAM_SY_SYNC_HWM__A 0x1470014 +#define QAM_SY_SYNC_HWM__W 4 +#define QAM_SY_SYNC_HWM__M 0xF +#define QAM_SY_SYNC_HWM__PRE 0x5 + +#define QAM_SY_UNLOCK__A 0x1470015 +#define QAM_SY_UNLOCK__W 1 +#define QAM_SY_UNLOCK__M 0x1 +#define QAM_SY_UNLOCK__PRE 0x0 +#define QAM_SY_CONTROL_WORD__A 0x1470016 +#define QAM_SY_CONTROL_WORD__W 4 +#define QAM_SY_CONTROL_WORD__M 0xF +#define QAM_SY_CONTROL_WORD__PRE 0x0 + +#define QAM_SY_CONTROL_WORD_CTRL_WORD__B 0 +#define QAM_SY_CONTROL_WORD_CTRL_WORD__W 4 +#define QAM_SY_CONTROL_WORD_CTRL_WORD__M 0xF +#define QAM_SY_CONTROL_WORD_CTRL_WORD__PRE 0x0 + + + +#define QAM_VD_ISS_RAM__A 0x1480000 + + + +#define QAM_VD_QSS_RAM__A 0x1490000 + + + +#define QAM_VD_SYM_RAM__A 0x14A0000 + + + + + +#define SCU_COMM_EXEC__A 0x800000 +#define SCU_COMM_EXEC__W 2 +#define SCU_COMM_EXEC__M 0x3 +#define SCU_COMM_EXEC__PRE 0x0 +#define SCU_COMM_EXEC_STOP 0x0 +#define SCU_COMM_EXEC_ACTIVE 0x1 +#define SCU_COMM_EXEC_HOLD 0x2 + +#define SCU_COMM_STATE__A 0x800001 +#define SCU_COMM_STATE__W 16 +#define SCU_COMM_STATE__M 0xFFFF +#define SCU_COMM_STATE__PRE 0x0 + +#define SCU_COMM_STATE_COMM_STATE__B 0 +#define SCU_COMM_STATE_COMM_STATE__W 16 +#define SCU_COMM_STATE_COMM_STATE__M 0xFFFF +#define SCU_COMM_STATE_COMM_STATE__PRE 0x0 + + + +#define SCU_TOP_COMM_EXEC__A 0x810000 +#define SCU_TOP_COMM_EXEC__W 2 +#define SCU_TOP_COMM_EXEC__M 0x3 +#define SCU_TOP_COMM_EXEC__PRE 0x0 +#define SCU_TOP_COMM_EXEC_STOP 0x0 +#define SCU_TOP_COMM_EXEC_ACTIVE 0x1 +#define SCU_TOP_COMM_EXEC_HOLD 0x2 + + +#define SCU_TOP_COMM_STATE__A 0x810001 +#define SCU_TOP_COMM_STATE__W 16 +#define SCU_TOP_COMM_STATE__M 0xFFFF +#define SCU_TOP_COMM_STATE__PRE 0x0 +#define SCU_TOP_MWAIT_CTR__A 0x810010 +#define SCU_TOP_MWAIT_CTR__W 2 +#define SCU_TOP_MWAIT_CTR__M 0x3 +#define SCU_TOP_MWAIT_CTR__PRE 0x0 + +#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__B 0 +#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__W 1 +#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__M 0x1 +#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__PRE 0x0 +#define SCU_TOP_MWAIT_CTR_MWAIT_SEL_TR_MW_OFF 0x0 +#define SCU_TOP_MWAIT_CTR_MWAIT_SEL_TR_MW_ON 0x1 + +#define SCU_TOP_MWAIT_CTR_READY_DIS__B 1 +#define SCU_TOP_MWAIT_CTR_READY_DIS__W 1 +#define SCU_TOP_MWAIT_CTR_READY_DIS__M 0x2 +#define SCU_TOP_MWAIT_CTR_READY_DIS__PRE 0x0 +#define SCU_TOP_MWAIT_CTR_READY_DIS_NMI_ON 0x0 +#define SCU_TOP_MWAIT_CTR_READY_DIS_NMI_OFF 0x2 + + + +#define SCU_LOW_RAM__A 0x820000 + +#define SCU_LOW_RAM_LOW__B 0 +#define SCU_LOW_RAM_LOW__W 16 +#define SCU_LOW_RAM_LOW__M 0xFFFF +#define SCU_LOW_RAM_LOW__PRE 0x0 + + + +#define SCU_HIGH_RAM__A 0x830000 + +#define SCU_HIGH_RAM_HIGH__B 0 +#define SCU_HIGH_RAM_HIGH__W 16 +#define SCU_HIGH_RAM_HIGH__M 0xFFFF +#define SCU_HIGH_RAM_HIGH__PRE 0x0 + + + + + + +#define SCU_RAM_AGC_RF_MAX__A 0x831E96 +#define SCU_RAM_AGC_RF_MAX__W 15 +#define SCU_RAM_AGC_RF_MAX__M 0x7FFF +#define SCU_RAM_AGC_RF_MAX__PRE 0x0 + +#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A 0x831E97 +#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__W 16 +#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__M 0xFFFF +#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__PRE 0x0 + +#define SCU_RAM_AGC_KI_CYCCNT__A 0x831E98 +#define SCU_RAM_AGC_KI_CYCCNT__W 16 +#define SCU_RAM_AGC_KI_CYCCNT__M 0xFFFF +#define SCU_RAM_AGC_KI_CYCCNT__PRE 0x0 + +#define SCU_RAM_AGC_KI_CYCLEN__A 0x831E99 +#define SCU_RAM_AGC_KI_CYCLEN__W 16 +#define SCU_RAM_AGC_KI_CYCLEN__M 0xFFFF +#define SCU_RAM_AGC_KI_CYCLEN__PRE 0x0 + +#define SCU_RAM_AGC_SNS_CYCLEN__A 0x831E9A +#define SCU_RAM_AGC_SNS_CYCLEN__W 16 +#define SCU_RAM_AGC_SNS_CYCLEN__M 0xFFFF +#define SCU_RAM_AGC_SNS_CYCLEN__PRE 0x0 + +#define SCU_RAM_AGC_RF_SNS_DEV_MAX__A 0x831E9B +#define SCU_RAM_AGC_RF_SNS_DEV_MAX__W 16 +#define SCU_RAM_AGC_RF_SNS_DEV_MAX__M 0xFFFF +#define SCU_RAM_AGC_RF_SNS_DEV_MAX__PRE 0x0 + +#define SCU_RAM_AGC_RF_SNS_DEV_MIN__A 0x831E9C +#define SCU_RAM_AGC_RF_SNS_DEV_MIN__W 16 +#define SCU_RAM_AGC_RF_SNS_DEV_MIN__M 0xFFFF +#define SCU_RAM_AGC_RF_SNS_DEV_MIN__PRE 0x0 +#define SCU_RAM_AGC_KI__A 0x831E9D +#define SCU_RAM_AGC_KI__W 15 +#define SCU_RAM_AGC_KI__M 0x7FFF +#define SCU_RAM_AGC_KI__PRE 0x0 + +#define SCU_RAM_AGC_KI_DGAIN__B 0 +#define SCU_RAM_AGC_KI_DGAIN__W 4 +#define SCU_RAM_AGC_KI_DGAIN__M 0xF +#define SCU_RAM_AGC_KI_DGAIN__PRE 0x0 + +#define SCU_RAM_AGC_KI_RF__B 4 +#define SCU_RAM_AGC_KI_RF__W 4 +#define SCU_RAM_AGC_KI_RF__M 0xF0 +#define SCU_RAM_AGC_KI_RF__PRE 0x0 + +#define SCU_RAM_AGC_KI_IF__B 8 +#define SCU_RAM_AGC_KI_IF__W 4 +#define SCU_RAM_AGC_KI_IF__M 0xF00 +#define SCU_RAM_AGC_KI_IF__PRE 0x0 + +#define SCU_RAM_AGC_KI_IF_AGC_DISABLE__B 12 +#define SCU_RAM_AGC_KI_IF_AGC_DISABLE__W 1 +#define SCU_RAM_AGC_KI_IF_AGC_DISABLE__M 0x1000 +#define SCU_RAM_AGC_KI_IF_AGC_DISABLE__PRE 0x0 + +#define SCU_RAM_AGC_KI_INV_IF_POL__B 13 +#define SCU_RAM_AGC_KI_INV_IF_POL__W 1 +#define SCU_RAM_AGC_KI_INV_IF_POL__M 0x2000 +#define SCU_RAM_AGC_KI_INV_IF_POL__PRE 0x0 + +#define SCU_RAM_AGC_KI_INV_RF_POL__B 14 +#define SCU_RAM_AGC_KI_INV_RF_POL__W 1 +#define SCU_RAM_AGC_KI_INV_RF_POL__M 0x4000 +#define SCU_RAM_AGC_KI_INV_RF_POL__PRE 0x0 + +#define SCU_RAM_AGC_KI_RED__A 0x831E9E +#define SCU_RAM_AGC_KI_RED__W 6 +#define SCU_RAM_AGC_KI_RED__M 0x3F +#define SCU_RAM_AGC_KI_RED__PRE 0x0 + +#define SCU_RAM_AGC_KI_RED_INNER_RED__B 0 +#define SCU_RAM_AGC_KI_RED_INNER_RED__W 2 +#define SCU_RAM_AGC_KI_RED_INNER_RED__M 0x3 +#define SCU_RAM_AGC_KI_RED_INNER_RED__PRE 0x0 + +#define SCU_RAM_AGC_KI_RED_RAGC_RED__B 2 +#define SCU_RAM_AGC_KI_RED_RAGC_RED__W 2 +#define SCU_RAM_AGC_KI_RED_RAGC_RED__M 0xC +#define SCU_RAM_AGC_KI_RED_RAGC_RED__PRE 0x0 + +#define SCU_RAM_AGC_KI_RED_IAGC_RED__B 4 +#define SCU_RAM_AGC_KI_RED_IAGC_RED__W 2 +#define SCU_RAM_AGC_KI_RED_IAGC_RED__M 0x30 +#define SCU_RAM_AGC_KI_RED_IAGC_RED__PRE 0x0 + + +#define SCU_RAM_AGC_KI_INNERGAIN_MIN__A 0x831E9F +#define SCU_RAM_AGC_KI_INNERGAIN_MIN__W 16 +#define SCU_RAM_AGC_KI_INNERGAIN_MIN__M 0xFFFF +#define SCU_RAM_AGC_KI_INNERGAIN_MIN__PRE 0x0 + +#define SCU_RAM_AGC_KI_MINGAIN__A 0x831EA0 +#define SCU_RAM_AGC_KI_MINGAIN__W 16 +#define SCU_RAM_AGC_KI_MINGAIN__M 0xFFFF +#define SCU_RAM_AGC_KI_MINGAIN__PRE 0x0 + +#define SCU_RAM_AGC_KI_MAXGAIN__A 0x831EA1 +#define SCU_RAM_AGC_KI_MAXGAIN__W 16 +#define SCU_RAM_AGC_KI_MAXGAIN__M 0xFFFF +#define SCU_RAM_AGC_KI_MAXGAIN__PRE 0x0 + +#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__A 0x831EA2 +#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__W 16 +#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__M 0xFFFF +#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__PRE 0x0 +#define SCU_RAM_AGC_KI_MIN__A 0x831EA3 +#define SCU_RAM_AGC_KI_MIN__W 12 +#define SCU_RAM_AGC_KI_MIN__M 0xFFF +#define SCU_RAM_AGC_KI_MIN__PRE 0x0 + +#define SCU_RAM_AGC_KI_MIN_DGAIN__B 0 +#define SCU_RAM_AGC_KI_MIN_DGAIN__W 4 +#define SCU_RAM_AGC_KI_MIN_DGAIN__M 0xF +#define SCU_RAM_AGC_KI_MIN_DGAIN__PRE 0x0 + +#define SCU_RAM_AGC_KI_MIN_RF__B 4 +#define SCU_RAM_AGC_KI_MIN_RF__W 4 +#define SCU_RAM_AGC_KI_MIN_RF__M 0xF0 +#define SCU_RAM_AGC_KI_MIN_RF__PRE 0x0 + +#define SCU_RAM_AGC_KI_MIN_IF__B 8 +#define SCU_RAM_AGC_KI_MIN_IF__W 4 +#define SCU_RAM_AGC_KI_MIN_IF__M 0xF00 +#define SCU_RAM_AGC_KI_MIN_IF__PRE 0x0 + +#define SCU_RAM_AGC_KI_MAX__A 0x831EA4 +#define SCU_RAM_AGC_KI_MAX__W 12 +#define SCU_RAM_AGC_KI_MAX__M 0xFFF +#define SCU_RAM_AGC_KI_MAX__PRE 0x0 + +#define SCU_RAM_AGC_KI_MAX_DGAIN__B 0 +#define SCU_RAM_AGC_KI_MAX_DGAIN__W 4 +#define SCU_RAM_AGC_KI_MAX_DGAIN__M 0xF +#define SCU_RAM_AGC_KI_MAX_DGAIN__PRE 0x0 + +#define SCU_RAM_AGC_KI_MAX_RF__B 4 +#define SCU_RAM_AGC_KI_MAX_RF__W 4 +#define SCU_RAM_AGC_KI_MAX_RF__M 0xF0 +#define SCU_RAM_AGC_KI_MAX_RF__PRE 0x0 + +#define SCU_RAM_AGC_KI_MAX_IF__B 8 +#define SCU_RAM_AGC_KI_MAX_IF__W 4 +#define SCU_RAM_AGC_KI_MAX_IF__M 0xF00 +#define SCU_RAM_AGC_KI_MAX_IF__PRE 0x0 + + +#define SCU_RAM_AGC_CLP_SUM__A 0x831EA5 +#define SCU_RAM_AGC_CLP_SUM__W 16 +#define SCU_RAM_AGC_CLP_SUM__M 0xFFFF +#define SCU_RAM_AGC_CLP_SUM__PRE 0x0 + +#define SCU_RAM_AGC_CLP_SUM_MIN__A 0x831EA6 +#define SCU_RAM_AGC_CLP_SUM_MIN__W 16 +#define SCU_RAM_AGC_CLP_SUM_MIN__M 0xFFFF +#define SCU_RAM_AGC_CLP_SUM_MIN__PRE 0x0 + +#define SCU_RAM_AGC_CLP_SUM_MAX__A 0x831EA7 +#define SCU_RAM_AGC_CLP_SUM_MAX__W 16 +#define SCU_RAM_AGC_CLP_SUM_MAX__M 0xFFFF +#define SCU_RAM_AGC_CLP_SUM_MAX__PRE 0x0 + +#define SCU_RAM_AGC_CLP_CYCLEN__A 0x831EA8 +#define SCU_RAM_AGC_CLP_CYCLEN__W 16 +#define SCU_RAM_AGC_CLP_CYCLEN__M 0xFFFF +#define SCU_RAM_AGC_CLP_CYCLEN__PRE 0x0 + +#define SCU_RAM_AGC_CLP_CYCCNT__A 0x831EA9 +#define SCU_RAM_AGC_CLP_CYCCNT__W 16 +#define SCU_RAM_AGC_CLP_CYCCNT__M 0xFFFF +#define SCU_RAM_AGC_CLP_CYCCNT__PRE 0x0 + +#define SCU_RAM_AGC_CLP_DIR_TO__A 0x831EAA +#define SCU_RAM_AGC_CLP_DIR_TO__W 8 +#define SCU_RAM_AGC_CLP_DIR_TO__M 0xFF +#define SCU_RAM_AGC_CLP_DIR_TO__PRE 0x0 + +#define SCU_RAM_AGC_CLP_DIR_WD__A 0x831EAB +#define SCU_RAM_AGC_CLP_DIR_WD__W 8 +#define SCU_RAM_AGC_CLP_DIR_WD__M 0xFF +#define SCU_RAM_AGC_CLP_DIR_WD__PRE 0x0 + +#define SCU_RAM_AGC_CLP_DIR_STP__A 0x831EAC +#define SCU_RAM_AGC_CLP_DIR_STP__W 16 +#define SCU_RAM_AGC_CLP_DIR_STP__M 0xFFFF +#define SCU_RAM_AGC_CLP_DIR_STP__PRE 0x0 + +#define SCU_RAM_AGC_SNS_SUM__A 0x831EAD +#define SCU_RAM_AGC_SNS_SUM__W 16 +#define SCU_RAM_AGC_SNS_SUM__M 0xFFFF +#define SCU_RAM_AGC_SNS_SUM__PRE 0x0 + +#define SCU_RAM_AGC_SNS_SUM_MIN__A 0x831EAE +#define SCU_RAM_AGC_SNS_SUM_MIN__W 16 +#define SCU_RAM_AGC_SNS_SUM_MIN__M 0xFFFF +#define SCU_RAM_AGC_SNS_SUM_MIN__PRE 0x0 + +#define SCU_RAM_AGC_SNS_SUM_MAX__A 0x831EAF +#define SCU_RAM_AGC_SNS_SUM_MAX__W 16 +#define SCU_RAM_AGC_SNS_SUM_MAX__M 0xFFFF +#define SCU_RAM_AGC_SNS_SUM_MAX__PRE 0x0 + +#define SCU_RAM_AGC_SNS_CYCCNT__A 0x831EB0 +#define SCU_RAM_AGC_SNS_CYCCNT__W 16 +#define SCU_RAM_AGC_SNS_CYCCNT__M 0xFFFF +#define SCU_RAM_AGC_SNS_CYCCNT__PRE 0x0 + +#define SCU_RAM_AGC_SNS_DIR_TO__A 0x831EB1 +#define SCU_RAM_AGC_SNS_DIR_TO__W 8 +#define SCU_RAM_AGC_SNS_DIR_TO__M 0xFF +#define SCU_RAM_AGC_SNS_DIR_TO__PRE 0x0 + +#define SCU_RAM_AGC_SNS_DIR_WD__A 0x831EB2 +#define SCU_RAM_AGC_SNS_DIR_WD__W 8 +#define SCU_RAM_AGC_SNS_DIR_WD__M 0xFF +#define SCU_RAM_AGC_SNS_DIR_WD__PRE 0x0 + +#define SCU_RAM_AGC_SNS_DIR_STP__A 0x831EB3 +#define SCU_RAM_AGC_SNS_DIR_STP__W 16 +#define SCU_RAM_AGC_SNS_DIR_STP__M 0xFFFF +#define SCU_RAM_AGC_SNS_DIR_STP__PRE 0x0 + +#define SCU_RAM_AGC_INGAIN__A 0x831EB4 +#define SCU_RAM_AGC_INGAIN__W 16 +#define SCU_RAM_AGC_INGAIN__M 0xFFFF +#define SCU_RAM_AGC_INGAIN__PRE 0x0 + +#define SCU_RAM_AGC_INGAIN_TGT__A 0x831EB5 +#define SCU_RAM_AGC_INGAIN_TGT__W 15 +#define SCU_RAM_AGC_INGAIN_TGT__M 0x7FFF +#define SCU_RAM_AGC_INGAIN_TGT__PRE 0x0 + +#define SCU_RAM_AGC_INGAIN_TGT_MIN__A 0x831EB6 +#define SCU_RAM_AGC_INGAIN_TGT_MIN__W 15 +#define SCU_RAM_AGC_INGAIN_TGT_MIN__M 0x7FFF +#define SCU_RAM_AGC_INGAIN_TGT_MIN__PRE 0x0 + +#define SCU_RAM_AGC_INGAIN_TGT_MAX__A 0x831EB7 +#define SCU_RAM_AGC_INGAIN_TGT_MAX__W 15 +#define SCU_RAM_AGC_INGAIN_TGT_MAX__M 0x7FFF +#define SCU_RAM_AGC_INGAIN_TGT_MAX__PRE 0x0 + +#define SCU_RAM_AGC_IF_IACCU_HI__A 0x831EB8 +#define SCU_RAM_AGC_IF_IACCU_HI__W 16 +#define SCU_RAM_AGC_IF_IACCU_HI__M 0xFFFF +#define SCU_RAM_AGC_IF_IACCU_HI__PRE 0x0 + +#define SCU_RAM_AGC_IF_IACCU_LO__A 0x831EB9 +#define SCU_RAM_AGC_IF_IACCU_LO__W 8 +#define SCU_RAM_AGC_IF_IACCU_LO__M 0xFF +#define SCU_RAM_AGC_IF_IACCU_LO__PRE 0x0 + +#define SCU_RAM_AGC_IF_IACCU_HI_TGT__A 0x831EBA +#define SCU_RAM_AGC_IF_IACCU_HI_TGT__W 15 +#define SCU_RAM_AGC_IF_IACCU_HI_TGT__M 0x7FFF +#define SCU_RAM_AGC_IF_IACCU_HI_TGT__PRE 0x0 + +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A 0x831EBB +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__W 15 +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__M 0x7FFF +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__PRE 0x0 + +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A 0x831EBC +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__W 15 +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__M 0x7FFF +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__PRE 0x0 + +#define SCU_RAM_AGC_RF_IACCU_HI__A 0x831EBD +#define SCU_RAM_AGC_RF_IACCU_HI__W 16 +#define SCU_RAM_AGC_RF_IACCU_HI__M 0xFFFF +#define SCU_RAM_AGC_RF_IACCU_HI__PRE 0x0 + +#define SCU_RAM_AGC_RF_IACCU_LO__A 0x831EBE +#define SCU_RAM_AGC_RF_IACCU_LO__W 8 +#define SCU_RAM_AGC_RF_IACCU_LO__M 0xFF +#define SCU_RAM_AGC_RF_IACCU_LO__PRE 0x0 + +#define SCU_RAM_AGC_RF_IACCU_HI_CO__A 0x831EBF +#define SCU_RAM_AGC_RF_IACCU_HI_CO__W 16 +#define SCU_RAM_AGC_RF_IACCU_HI_CO__M 0xFFFF +#define SCU_RAM_AGC_RF_IACCU_HI_CO__PRE 0x0 + +#define SCU_RAM_SP__A 0x831EC0 +#define SCU_RAM_SP__W 16 +#define SCU_RAM_SP__M 0xFFFF +#define SCU_RAM_SP__PRE 0x0 + +#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A 0x831EC1 +#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__W 16 +#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__M 0xFFFF +#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__PRE 0x0 + +#define SCU_RAM_AGC_KI_MIN_IFGAIN__A 0x831EC2 +#define SCU_RAM_AGC_KI_MIN_IFGAIN__W 16 +#define SCU_RAM_AGC_KI_MIN_IFGAIN__M 0xFFFF +#define SCU_RAM_AGC_KI_MIN_IFGAIN__PRE 0x0 + +#define SCU_RAM_AGC_KI_MAX_IFGAIN__A 0x831EC3 +#define SCU_RAM_AGC_KI_MAX_IFGAIN__W 16 +#define SCU_RAM_AGC_KI_MAX_IFGAIN__M 0xFFFF +#define SCU_RAM_AGC_KI_MAX_IFGAIN__PRE 0x0 + +#define SCU_RAM_FEC_MEAS_COUNT__A 0x831EC4 +#define SCU_RAM_FEC_MEAS_COUNT__W 16 +#define SCU_RAM_FEC_MEAS_COUNT__M 0xFFFF +#define SCU_RAM_FEC_MEAS_COUNT__PRE 0x0 + +#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A 0x831EC5 +#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__W 16 +#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__M 0xFFFF +#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__PRE 0x0 + +#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_HI__A 0x831EC6 +#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_HI__W 16 +#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_HI__M 0xFFFF +#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_HI__PRE 0x0 +#define SCU_RAM_GPIO__A 0x831EC7 +#define SCU_RAM_GPIO__W 1 +#define SCU_RAM_GPIO__M 0x1 +#define SCU_RAM_GPIO__PRE 0x0 + +#define SCU_RAM_GPIO_HW_LOCK_IND__B 0 +#define SCU_RAM_GPIO_HW_LOCK_IND__W 1 +#define SCU_RAM_GPIO_HW_LOCK_IND__M 0x1 +#define SCU_RAM_GPIO_HW_LOCK_IND__PRE 0x0 +#define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0 +#define SCU_RAM_GPIO_HW_LOCK_IND_ENABLE 0x1 + +#define SCU_RAM_AGC_CLP_CTRL_MODE__A 0x831EC8 +#define SCU_RAM_AGC_CLP_CTRL_MODE__W 8 +#define SCU_RAM_AGC_CLP_CTRL_MODE__M 0xFF +#define SCU_RAM_AGC_CLP_CTRL_MODE__PRE 0x0 + +#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__B 0 +#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__W 1 +#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__M 0x1 +#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__PRE 0x0 +#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW_FALSE 0x0 +#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW_TRUE 0x1 + +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__B 1 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__W 1 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__M 0x2 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__PRE 0x0 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP_FCC_ENABLE 0x0 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP_FCC_DISABLE 0x2 + +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__B 2 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__W 1 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__M 0x4 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__PRE 0x0 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC_DEC_DISABLE 0x0 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC_DEC_ENABLE 0x4 + + +#define SCU_RAM_AGC_KI_MIN_RFGAIN__A 0x831EC9 +#define SCU_RAM_AGC_KI_MIN_RFGAIN__W 16 +#define SCU_RAM_AGC_KI_MIN_RFGAIN__M 0xFFFF +#define SCU_RAM_AGC_KI_MIN_RFGAIN__PRE 0x0 + +#define SCU_RAM_AGC_KI_MAX_RFGAIN__A 0x831ECA +#define SCU_RAM_AGC_KI_MAX_RFGAIN__W 16 +#define SCU_RAM_AGC_KI_MAX_RFGAIN__M 0xFFFF +#define SCU_RAM_AGC_KI_MAX_RFGAIN__PRE 0x0 + +#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__A 0x831ECB +#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__W 16 +#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__M 0xFFFF +#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__PRE 0x0 + +#define SCU_RAM_INHIBIT_1__A 0x831ECC +#define SCU_RAM_INHIBIT_1__W 16 +#define SCU_RAM_INHIBIT_1__M 0xFFFF +#define SCU_RAM_INHIBIT_1__PRE 0x0 + +#define SCU_RAM_HTOL_BUF_0__A 0x831ECD +#define SCU_RAM_HTOL_BUF_0__W 16 +#define SCU_RAM_HTOL_BUF_0__M 0xFFFF +#define SCU_RAM_HTOL_BUF_0__PRE 0x0 + +#define SCU_RAM_HTOL_BUF_1__A 0x831ECE +#define SCU_RAM_HTOL_BUF_1__W 16 +#define SCU_RAM_HTOL_BUF_1__M 0xFFFF +#define SCU_RAM_HTOL_BUF_1__PRE 0x0 + +#define SCU_RAM_INHIBIT_2__A 0x831ECF +#define SCU_RAM_INHIBIT_2__W 16 +#define SCU_RAM_INHIBIT_2__M 0xFFFF +#define SCU_RAM_INHIBIT_2__PRE 0x0 + +#define SCU_RAM_TR_SHORT_BUF_0__A 0x831ED0 +#define SCU_RAM_TR_SHORT_BUF_0__W 16 +#define SCU_RAM_TR_SHORT_BUF_0__M 0xFFFF +#define SCU_RAM_TR_SHORT_BUF_0__PRE 0x0 + +#define SCU_RAM_TR_SHORT_BUF_1__A 0x831ED1 +#define SCU_RAM_TR_SHORT_BUF_1__W 16 +#define SCU_RAM_TR_SHORT_BUF_1__M 0xFFFF +#define SCU_RAM_TR_SHORT_BUF_1__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_0__A 0x831ED2 +#define SCU_RAM_TR_LONG_BUF_0__W 16 +#define SCU_RAM_TR_LONG_BUF_0__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_0__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_1__A 0x831ED3 +#define SCU_RAM_TR_LONG_BUF_1__W 16 +#define SCU_RAM_TR_LONG_BUF_1__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_1__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_2__A 0x831ED4 +#define SCU_RAM_TR_LONG_BUF_2__W 16 +#define SCU_RAM_TR_LONG_BUF_2__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_2__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_3__A 0x831ED5 +#define SCU_RAM_TR_LONG_BUF_3__W 16 +#define SCU_RAM_TR_LONG_BUF_3__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_3__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_4__A 0x831ED6 +#define SCU_RAM_TR_LONG_BUF_4__W 16 +#define SCU_RAM_TR_LONG_BUF_4__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_4__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_5__A 0x831ED7 +#define SCU_RAM_TR_LONG_BUF_5__W 16 +#define SCU_RAM_TR_LONG_BUF_5__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_5__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_6__A 0x831ED8 +#define SCU_RAM_TR_LONG_BUF_6__W 16 +#define SCU_RAM_TR_LONG_BUF_6__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_6__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_7__A 0x831ED9 +#define SCU_RAM_TR_LONG_BUF_7__W 16 +#define SCU_RAM_TR_LONG_BUF_7__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_7__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_8__A 0x831EDA +#define SCU_RAM_TR_LONG_BUF_8__W 16 +#define SCU_RAM_TR_LONG_BUF_8__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_8__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_9__A 0x831EDB +#define SCU_RAM_TR_LONG_BUF_9__W 16 +#define SCU_RAM_TR_LONG_BUF_9__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_9__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_10__A 0x831EDC +#define SCU_RAM_TR_LONG_BUF_10__W 16 +#define SCU_RAM_TR_LONG_BUF_10__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_10__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_11__A 0x831EDD +#define SCU_RAM_TR_LONG_BUF_11__W 16 +#define SCU_RAM_TR_LONG_BUF_11__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_11__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_12__A 0x831EDE +#define SCU_RAM_TR_LONG_BUF_12__W 16 +#define SCU_RAM_TR_LONG_BUF_12__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_12__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_13__A 0x831EDF +#define SCU_RAM_TR_LONG_BUF_13__W 16 +#define SCU_RAM_TR_LONG_BUF_13__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_13__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_14__A 0x831EE0 +#define SCU_RAM_TR_LONG_BUF_14__W 16 +#define SCU_RAM_TR_LONG_BUF_14__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_14__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_15__A 0x831EE1 +#define SCU_RAM_TR_LONG_BUF_15__W 16 +#define SCU_RAM_TR_LONG_BUF_15__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_15__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_16__A 0x831EE2 +#define SCU_RAM_TR_LONG_BUF_16__W 16 +#define SCU_RAM_TR_LONG_BUF_16__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_16__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_17__A 0x831EE3 +#define SCU_RAM_TR_LONG_BUF_17__W 16 +#define SCU_RAM_TR_LONG_BUF_17__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_17__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_18__A 0x831EE4 +#define SCU_RAM_TR_LONG_BUF_18__W 16 +#define SCU_RAM_TR_LONG_BUF_18__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_18__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_19__A 0x831EE5 +#define SCU_RAM_TR_LONG_BUF_19__W 16 +#define SCU_RAM_TR_LONG_BUF_19__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_19__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_20__A 0x831EE6 +#define SCU_RAM_TR_LONG_BUF_20__W 16 +#define SCU_RAM_TR_LONG_BUF_20__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_20__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_21__A 0x831EE7 +#define SCU_RAM_TR_LONG_BUF_21__W 16 +#define SCU_RAM_TR_LONG_BUF_21__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_21__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_22__A 0x831EE8 +#define SCU_RAM_TR_LONG_BUF_22__W 16 +#define SCU_RAM_TR_LONG_BUF_22__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_22__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_23__A 0x831EE9 +#define SCU_RAM_TR_LONG_BUF_23__W 16 +#define SCU_RAM_TR_LONG_BUF_23__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_23__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_24__A 0x831EEA +#define SCU_RAM_TR_LONG_BUF_24__W 16 +#define SCU_RAM_TR_LONG_BUF_24__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_24__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_25__A 0x831EEB +#define SCU_RAM_TR_LONG_BUF_25__W 16 +#define SCU_RAM_TR_LONG_BUF_25__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_25__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_26__A 0x831EEC +#define SCU_RAM_TR_LONG_BUF_26__W 16 +#define SCU_RAM_TR_LONG_BUF_26__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_26__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_27__A 0x831EED +#define SCU_RAM_TR_LONG_BUF_27__W 16 +#define SCU_RAM_TR_LONG_BUF_27__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_27__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_28__A 0x831EEE +#define SCU_RAM_TR_LONG_BUF_28__W 16 +#define SCU_RAM_TR_LONG_BUF_28__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_28__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_29__A 0x831EEF +#define SCU_RAM_TR_LONG_BUF_29__W 16 +#define SCU_RAM_TR_LONG_BUF_29__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_29__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_30__A 0x831EF0 +#define SCU_RAM_TR_LONG_BUF_30__W 16 +#define SCU_RAM_TR_LONG_BUF_30__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_30__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_31__A 0x831EF1 +#define SCU_RAM_TR_LONG_BUF_31__W 16 +#define SCU_RAM_TR_LONG_BUF_31__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_31__PRE 0x0 +#define SCU_RAM_ATV_AMS_MAX__A 0x831EF2 +#define SCU_RAM_ATV_AMS_MAX__W 11 +#define SCU_RAM_ATV_AMS_MAX__M 0x7FF +#define SCU_RAM_ATV_AMS_MAX__PRE 0x0 + +#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__B 0 +#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__W 11 +#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__M 0x7FF +#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__PRE 0x0 + +#define SCU_RAM_ATV_AMS_MIN__A 0x831EF3 +#define SCU_RAM_ATV_AMS_MIN__W 11 +#define SCU_RAM_ATV_AMS_MIN__M 0x7FF +#define SCU_RAM_ATV_AMS_MIN__PRE 0x0 + +#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__B 0 +#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__W 11 +#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__M 0x7FF +#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__PRE 0x0 + +#define SCU_RAM_ATV_FIELD_CNT__A 0x831EF4 +#define SCU_RAM_ATV_FIELD_CNT__W 9 +#define SCU_RAM_ATV_FIELD_CNT__M 0x1FF +#define SCU_RAM_ATV_FIELD_CNT__PRE 0x0 + +#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__B 0 +#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__W 9 +#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__M 0x1FF +#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__PRE 0x0 + +#define SCU_RAM_ATV_AAGC_FAST__A 0x831EF5 +#define SCU_RAM_ATV_AAGC_FAST__W 1 +#define SCU_RAM_ATV_AAGC_FAST__M 0x1 +#define SCU_RAM_ATV_AAGC_FAST__PRE 0x0 + +#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__B 0 +#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__W 1 +#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__M 0x1 +#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__PRE 0x0 +#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST_OFF 0x0 +#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST_ON 0x1 + +#define SCU_RAM_ATV_AAGC_LP2__A 0x831EF6 +#define SCU_RAM_ATV_AAGC_LP2__W 16 +#define SCU_RAM_ATV_AAGC_LP2__M 0xFFFF +#define SCU_RAM_ATV_AAGC_LP2__PRE 0x0 + +#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__B 0 +#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__W 16 +#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__M 0xFFFF +#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__PRE 0x0 + +#define SCU_RAM_ATV_BP_LVL__A 0x831EF7 +#define SCU_RAM_ATV_BP_LVL__W 11 +#define SCU_RAM_ATV_BP_LVL__M 0x7FF +#define SCU_RAM_ATV_BP_LVL__PRE 0x0 + +#define SCU_RAM_ATV_BP_LVL_BP_LVL__B 0 +#define SCU_RAM_ATV_BP_LVL_BP_LVL__W 11 +#define SCU_RAM_ATV_BP_LVL_BP_LVL__M 0x7FF +#define SCU_RAM_ATV_BP_LVL_BP_LVL__PRE 0x0 + +#define SCU_RAM_ATV_BP_RELY__A 0x831EF8 +#define SCU_RAM_ATV_BP_RELY__W 8 +#define SCU_RAM_ATV_BP_RELY__M 0xFF +#define SCU_RAM_ATV_BP_RELY__PRE 0x0 + +#define SCU_RAM_ATV_BP_RELY_BP_RELY__B 0 +#define SCU_RAM_ATV_BP_RELY_BP_RELY__W 8 +#define SCU_RAM_ATV_BP_RELY_BP_RELY__M 0xFF +#define SCU_RAM_ATV_BP_RELY_BP_RELY__PRE 0x0 + +#define SCU_RAM_ATV_BP_MTA__A 0x831EF9 +#define SCU_RAM_ATV_BP_MTA__W 14 +#define SCU_RAM_ATV_BP_MTA__M 0x3FFF +#define SCU_RAM_ATV_BP_MTA__PRE 0x0 + +#define SCU_RAM_ATV_BP_MTA_BP_MTA__B 0 +#define SCU_RAM_ATV_BP_MTA_BP_MTA__W 14 +#define SCU_RAM_ATV_BP_MTA_BP_MTA__M 0x3FFF +#define SCU_RAM_ATV_BP_MTA_BP_MTA__PRE 0x0 + +#define SCU_RAM_ATV_BP_REF__A 0x831EFA +#define SCU_RAM_ATV_BP_REF__W 11 +#define SCU_RAM_ATV_BP_REF__M 0x7FF +#define SCU_RAM_ATV_BP_REF__PRE 0x0 + +#define SCU_RAM_ATV_BP_REF_BP_REF__B 0 +#define SCU_RAM_ATV_BP_REF_BP_REF__W 11 +#define SCU_RAM_ATV_BP_REF_BP_REF__M 0x7FF +#define SCU_RAM_ATV_BP_REF_BP_REF__PRE 0x0 + +#define SCU_RAM_ATV_BP_REF_MIN__A 0x831EFB +#define SCU_RAM_ATV_BP_REF_MIN__W 11 +#define SCU_RAM_ATV_BP_REF_MIN__M 0x7FF +#define SCU_RAM_ATV_BP_REF_MIN__PRE 0x0 + +#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__B 0 +#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__W 11 +#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__M 0x7FF +#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__PRE 0x0 + +#define SCU_RAM_ATV_BP_REF_MAX__A 0x831EFC +#define SCU_RAM_ATV_BP_REF_MAX__W 11 +#define SCU_RAM_ATV_BP_REF_MAX__M 0x7FF +#define SCU_RAM_ATV_BP_REF_MAX__PRE 0x0 + +#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__B 0 +#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__W 11 +#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__M 0x7FF +#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__PRE 0x0 + +#define SCU_RAM_ATV_BP_CNT__A 0x831EFD +#define SCU_RAM_ATV_BP_CNT__W 8 +#define SCU_RAM_ATV_BP_CNT__M 0xFF +#define SCU_RAM_ATV_BP_CNT__PRE 0x0 + +#define SCU_RAM_ATV_BP_CNT_BP_CNT__B 0 +#define SCU_RAM_ATV_BP_CNT_BP_CNT__W 8 +#define SCU_RAM_ATV_BP_CNT_BP_CNT__M 0xFF +#define SCU_RAM_ATV_BP_CNT_BP_CNT__PRE 0x0 + +#define SCU_RAM_ATV_BP_XD_CNT__A 0x831EFE +#define SCU_RAM_ATV_BP_XD_CNT__W 12 +#define SCU_RAM_ATV_BP_XD_CNT__M 0xFFF +#define SCU_RAM_ATV_BP_XD_CNT__PRE 0x0 + +#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__B 0 +#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__W 12 +#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__M 0xFFF +#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__PRE 0x0 + +#define SCU_RAM_ATV_PAGC_KI_MIN__A 0x831EFF +#define SCU_RAM_ATV_PAGC_KI_MIN__W 12 +#define SCU_RAM_ATV_PAGC_KI_MIN__M 0xFFF +#define SCU_RAM_ATV_PAGC_KI_MIN__PRE 0x0 + +#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__B 0 +#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__W 12 +#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__M 0xFFF +#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__PRE 0x0 + +#define SCU_RAM_ATV_BPC_KI_MIN__A 0x831F00 +#define SCU_RAM_ATV_BPC_KI_MIN__W 12 +#define SCU_RAM_ATV_BPC_KI_MIN__M 0xFFF +#define SCU_RAM_ATV_BPC_KI_MIN__PRE 0x0 + +#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__B 0 +#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__W 12 +#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__M 0xFFF +#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__PRE 0x0 + + +#define SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__A 0x831F01 +#define SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__W 16 +#define SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__M 0xFFFF +#define SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__PRE 0x0 + +#define SCU_RAM_ORX_RF_RX_DATA_RATE__A 0x831F02 +#define SCU_RAM_ORX_RF_RX_DATA_RATE__W 8 +#define SCU_RAM_ORX_RF_RX_DATA_RATE__M 0xFF +#define SCU_RAM_ORX_RF_RX_DATA_RATE__PRE 0x0 +#define SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC 0x0 +#define SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC 0x1 +#define SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC_ALT 0x40 +#define SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC_ALT 0x41 +#define SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_REGSPEC 0x80 +#define SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_INVSPEC 0x81 +#define SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_REGSPEC 0xC0 +#define SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_INVSPEC 0xC1 + + +#define SCU_RAM_ORX_SCU_STATE__A 0x831F03 +#define SCU_RAM_ORX_SCU_STATE__W 8 +#define SCU_RAM_ORX_SCU_STATE__M 0xFF +#define SCU_RAM_ORX_SCU_STATE__PRE 0x0 +#define SCU_RAM_ORX_SCU_STATE_RESET 0x0 +#define SCU_RAM_ORX_SCU_STATE_AGN_HUNT 0x1 +#define SCU_RAM_ORX_SCU_STATE_DGN_HUNT 0x2 +#define SCU_RAM_ORX_SCU_STATE_AGC_HUNT 0x3 +#define SCU_RAM_ORX_SCU_STATE_FRQ_HUNT 0x4 +#define SCU_RAM_ORX_SCU_STATE_PHA_HUNT 0x8 +#define SCU_RAM_ORX_SCU_STATE_TIM_HUNT 0x10 +#define SCU_RAM_ORX_SCU_STATE_EQU_HUNT 0x20 +#define SCU_RAM_ORX_SCU_STATE_EQT_HUNT 0x30 +#define SCU_RAM_ORX_SCU_STATE_SYNC 0x40 + + +#define SCU_RAM_ORX_SCU_LOCK__A 0x831F04 +#define SCU_RAM_ORX_SCU_LOCK__W 16 +#define SCU_RAM_ORX_SCU_LOCK__M 0xFFFF +#define SCU_RAM_ORX_SCU_LOCK__PRE 0x0 + +#define SCU_RAM_ORX_TARGET_MODE__A 0x831F05 +#define SCU_RAM_ORX_TARGET_MODE__W 2 +#define SCU_RAM_ORX_TARGET_MODE__M 0x3 +#define SCU_RAM_ORX_TARGET_MODE__PRE 0x0 +#define SCU_RAM_ORX_TARGET_MODE_1544KBPS 0x0 +#define SCU_RAM_ORX_TARGET_MODE_3088KBPS 0x1 +#define SCU_RAM_ORX_TARGET_MODE_2048KBPS_SQRT 0x2 +#define SCU_RAM_ORX_TARGET_MODE_2048KBPS_RO 0x3 + + +#define SCU_RAM_ORX_MER_MIN_DB__A 0x831F06 +#define SCU_RAM_ORX_MER_MIN_DB__W 8 +#define SCU_RAM_ORX_MER_MIN_DB__M 0xFF +#define SCU_RAM_ORX_MER_MIN_DB__PRE 0x0 + +#define SCU_RAM_ORX_RF_GAIN__A 0x831F07 +#define SCU_RAM_ORX_RF_GAIN__W 16 +#define SCU_RAM_ORX_RF_GAIN__M 0xFFFF +#define SCU_RAM_ORX_RF_GAIN__PRE 0x0 + +#define SCU_RAM_ORX_RF_GAIN_MIN__A 0x831F08 +#define SCU_RAM_ORX_RF_GAIN_MIN__W 16 +#define SCU_RAM_ORX_RF_GAIN_MIN__M 0xFFFF +#define SCU_RAM_ORX_RF_GAIN_MIN__PRE 0x0 + +#define SCU_RAM_ORX_RF_GAIN_MAX__A 0x831F09 +#define SCU_RAM_ORX_RF_GAIN_MAX__W 16 +#define SCU_RAM_ORX_RF_GAIN_MAX__M 0xFFFF +#define SCU_RAM_ORX_RF_GAIN_MAX__PRE 0x0 + +#define SCU_RAM_ORX_IF_GAIN__A 0x831F0A +#define SCU_RAM_ORX_IF_GAIN__W 16 +#define SCU_RAM_ORX_IF_GAIN__M 0xFFFF +#define SCU_RAM_ORX_IF_GAIN__PRE 0x0 + +#define SCU_RAM_ORX_IF_GAIN_MIN__A 0x831F0B +#define SCU_RAM_ORX_IF_GAIN_MIN__W 16 +#define SCU_RAM_ORX_IF_GAIN_MIN__M 0xFFFF +#define SCU_RAM_ORX_IF_GAIN_MIN__PRE 0x0 + +#define SCU_RAM_ORX_IF_GAIN_MAX__A 0x831F0C +#define SCU_RAM_ORX_IF_GAIN_MAX__W 16 +#define SCU_RAM_ORX_IF_GAIN_MAX__M 0xFFFF +#define SCU_RAM_ORX_IF_GAIN_MAX__PRE 0x0 + +#define SCU_RAM_ORX_AGN_HEADR__A 0x831F0D +#define SCU_RAM_ORX_AGN_HEADR__W 16 +#define SCU_RAM_ORX_AGN_HEADR__M 0xFFFF +#define SCU_RAM_ORX_AGN_HEADR__PRE 0x0 + +#define SCU_RAM_ORX_AGN_HEADR_STP__A 0x831F0E +#define SCU_RAM_ORX_AGN_HEADR_STP__W 8 +#define SCU_RAM_ORX_AGN_HEADR_STP__M 0xFF +#define SCU_RAM_ORX_AGN_HEADR_STP__PRE 0x0 + +#define SCU_RAM_ORX_AGN_KI__A 0x831F0F +#define SCU_RAM_ORX_AGN_KI__W 8 +#define SCU_RAM_ORX_AGN_KI__M 0xFF +#define SCU_RAM_ORX_AGN_KI__PRE 0x0 + +#define SCU_RAM_ORX_AGN_LOCK_TH__A 0x831F10 +#define SCU_RAM_ORX_AGN_LOCK_TH__W 16 +#define SCU_RAM_ORX_AGN_LOCK_TH__M 0xFFFF +#define SCU_RAM_ORX_AGN_LOCK_TH__PRE 0x0 + +#define SCU_RAM_ORX_AGN_LOCK_WD__A 0x831F11 +#define SCU_RAM_ORX_AGN_LOCK_WD__W 16 +#define SCU_RAM_ORX_AGN_LOCK_WD__M 0xFFFF +#define SCU_RAM_ORX_AGN_LOCK_WD__PRE 0x0 + +#define SCU_RAM_ORX_AGN_ONLOCK_TTH__A 0x831F12 +#define SCU_RAM_ORX_AGN_ONLOCK_TTH__W 16 +#define SCU_RAM_ORX_AGN_ONLOCK_TTH__M 0xFFFF +#define SCU_RAM_ORX_AGN_ONLOCK_TTH__PRE 0x0 + +#define SCU_RAM_ORX_AGN_UNLOCK_TTH__A 0x831F13 +#define SCU_RAM_ORX_AGN_UNLOCK_TTH__W 16 +#define SCU_RAM_ORX_AGN_UNLOCK_TTH__M 0xFFFF +#define SCU_RAM_ORX_AGN_UNLOCK_TTH__PRE 0x0 + +#define SCU_RAM_ORX_AGN_LOCK_TOTH__A 0x831F14 +#define SCU_RAM_ORX_AGN_LOCK_TOTH__W 16 +#define SCU_RAM_ORX_AGN_LOCK_TOTH__M 0xFFFF +#define SCU_RAM_ORX_AGN_LOCK_TOTH__PRE 0x0 + +#define SCU_RAM_ORX_AGN_LOCK_MASK__A 0x831F15 +#define SCU_RAM_ORX_AGN_LOCK_MASK__W 8 +#define SCU_RAM_ORX_AGN_LOCK_MASK__M 0xFF +#define SCU_RAM_ORX_AGN_LOCK_MASK__PRE 0x0 + +#define SCU_RAM_ORX_DGN__A 0x831F16 +#define SCU_RAM_ORX_DGN__W 16 +#define SCU_RAM_ORX_DGN__M 0xFFFF +#define SCU_RAM_ORX_DGN__PRE 0x0 + +#define SCU_RAM_ORX_DGN_MIN__A 0x831F17 +#define SCU_RAM_ORX_DGN_MIN__W 16 +#define SCU_RAM_ORX_DGN_MIN__M 0xFFFF +#define SCU_RAM_ORX_DGN_MIN__PRE 0x0 + +#define SCU_RAM_ORX_DGN_MAX__A 0x831F18 +#define SCU_RAM_ORX_DGN_MAX__W 16 +#define SCU_RAM_ORX_DGN_MAX__M 0xFFFF +#define SCU_RAM_ORX_DGN_MAX__PRE 0x0 + +#define SCU_RAM_ORX_DGN_AMP__A 0x831F19 +#define SCU_RAM_ORX_DGN_AMP__W 16 +#define SCU_RAM_ORX_DGN_AMP__M 0xFFFF +#define SCU_RAM_ORX_DGN_AMP__PRE 0x0 + +#define SCU_RAM_ORX_DGN_AMPTARGET__A 0x831F1A +#define SCU_RAM_ORX_DGN_AMPTARGET__W 16 +#define SCU_RAM_ORX_DGN_AMPTARGET__M 0xFFFF +#define SCU_RAM_ORX_DGN_AMPTARGET__PRE 0x0 + +#define SCU_RAM_ORX_DGN_KI__A 0x831F1B +#define SCU_RAM_ORX_DGN_KI__W 8 +#define SCU_RAM_ORX_DGN_KI__M 0xFF +#define SCU_RAM_ORX_DGN_KI__PRE 0x0 + +#define SCU_RAM_ORX_DGN_LOCK_TH__A 0x831F1C +#define SCU_RAM_ORX_DGN_LOCK_TH__W 16 +#define SCU_RAM_ORX_DGN_LOCK_TH__M 0xFFFF +#define SCU_RAM_ORX_DGN_LOCK_TH__PRE 0x0 + +#define SCU_RAM_ORX_DGN_LOCK_WD__A 0x831F1D +#define SCU_RAM_ORX_DGN_LOCK_WD__W 16 +#define SCU_RAM_ORX_DGN_LOCK_WD__M 0xFFFF +#define SCU_RAM_ORX_DGN_LOCK_WD__PRE 0x0 + +#define SCU_RAM_ORX_DGN_ONLOCK_TTH__A 0x831F1E +#define SCU_RAM_ORX_DGN_ONLOCK_TTH__W 16 +#define SCU_RAM_ORX_DGN_ONLOCK_TTH__M 0xFFFF +#define SCU_RAM_ORX_DGN_ONLOCK_TTH__PRE 0x0 + +#define SCU_RAM_ORX_DGN_UNLOCK_TTH__A 0x831F1F +#define SCU_RAM_ORX_DGN_UNLOCK_TTH__W 16 +#define SCU_RAM_ORX_DGN_UNLOCK_TTH__M 0xFFFF +#define SCU_RAM_ORX_DGN_UNLOCK_TTH__PRE 0x0 + +#define SCU_RAM_ORX_DGN_LOCK_TOTH__A 0x831F20 +#define SCU_RAM_ORX_DGN_LOCK_TOTH__W 16 +#define SCU_RAM_ORX_DGN_LOCK_TOTH__M 0xFFFF +#define SCU_RAM_ORX_DGN_LOCK_TOTH__PRE 0x0 + +#define SCU_RAM_ORX_DGN_LOCK_MASK__A 0x831F21 +#define SCU_RAM_ORX_DGN_LOCK_MASK__W 8 +#define SCU_RAM_ORX_DGN_LOCK_MASK__M 0xFF +#define SCU_RAM_ORX_DGN_LOCK_MASK__PRE 0x0 + +#define SCU_RAM_ORX_FREQ_GAIN_CORR__A 0x831F22 +#define SCU_RAM_ORX_FREQ_GAIN_CORR__W 8 +#define SCU_RAM_ORX_FREQ_GAIN_CORR__M 0xFF +#define SCU_RAM_ORX_FREQ_GAIN_CORR__PRE 0x0 +#define SCU_RAM_ORX_FREQ_GAIN_CORR_1544KBPS 0x60 +#define SCU_RAM_ORX_FREQ_GAIN_CORR_2048KBPS 0x80 +#define SCU_RAM_ORX_FREQ_GAIN_CORR_3088KBPS 0xC0 + + +#define SCU_RAM_ORX_FRQ_OFFSET__A 0x831F23 +#define SCU_RAM_ORX_FRQ_OFFSET__W 16 +#define SCU_RAM_ORX_FRQ_OFFSET__M 0xFFFF +#define SCU_RAM_ORX_FRQ_OFFSET__PRE 0x0 + +#define SCU_RAM_ORX_FRQ_OFFSET_MAX__A 0x831F24 +#define SCU_RAM_ORX_FRQ_OFFSET_MAX__W 15 +#define SCU_RAM_ORX_FRQ_OFFSET_MAX__M 0x7FFF +#define SCU_RAM_ORX_FRQ_OFFSET_MAX__PRE 0x0 + +#define SCU_RAM_ORX_FRQ_KI__A 0x831F25 +#define SCU_RAM_ORX_FRQ_KI__W 8 +#define SCU_RAM_ORX_FRQ_KI__M 0xFF +#define SCU_RAM_ORX_FRQ_KI__PRE 0x0 + +#define SCU_RAM_ORX_FRQ_DIFF__A 0x831F26 +#define SCU_RAM_ORX_FRQ_DIFF__W 16 +#define SCU_RAM_ORX_FRQ_DIFF__M 0xFFFF +#define SCU_RAM_ORX_FRQ_DIFF__PRE 0x0 + +#define SCU_RAM_ORX_FRQ_LOCK_TH__A 0x831F27 +#define SCU_RAM_ORX_FRQ_LOCK_TH__W 16 +#define SCU_RAM_ORX_FRQ_LOCK_TH__M 0xFFFF +#define SCU_RAM_ORX_FRQ_LOCK_TH__PRE 0x0 + +#define SCU_RAM_ORX_FRQ_LOCK_WD__A 0x831F28 +#define SCU_RAM_ORX_FRQ_LOCK_WD__W 16 +#define SCU_RAM_ORX_FRQ_LOCK_WD__M 0xFFFF +#define SCU_RAM_ORX_FRQ_LOCK_WD__PRE 0x0 + +#define SCU_RAM_ORX_FRQ_ONLOCK_TTH__A 0x831F29 +#define SCU_RAM_ORX_FRQ_ONLOCK_TTH__W 16 +#define SCU_RAM_ORX_FRQ_ONLOCK_TTH__M 0xFFFF +#define SCU_RAM_ORX_FRQ_ONLOCK_TTH__PRE 0x0 + +#define SCU_RAM_ORX_FRQ_UNLOCK_TTH__A 0x831F2A +#define SCU_RAM_ORX_FRQ_UNLOCK_TTH__W 16 +#define SCU_RAM_ORX_FRQ_UNLOCK_TTH__M 0xFFFF +#define SCU_RAM_ORX_FRQ_UNLOCK_TTH__PRE 0x0 + +#define SCU_RAM_ORX_FRQ_LOCK_TOTH__A 0x831F2B +#define SCU_RAM_ORX_FRQ_LOCK_TOTH__W 16 +#define SCU_RAM_ORX_FRQ_LOCK_TOTH__M 0xFFFF +#define SCU_RAM_ORX_FRQ_LOCK_TOTH__PRE 0x0 + +#define SCU_RAM_ORX_FRQ_LOCK_MASK__A 0x831F2C +#define SCU_RAM_ORX_FRQ_LOCK_MASK__W 8 +#define SCU_RAM_ORX_FRQ_LOCK_MASK__M 0xFF +#define SCU_RAM_ORX_FRQ_LOCK_MASK__PRE 0x0 + +#define SCU_RAM_ORX_PHA_DIFF__A 0x831F2D +#define SCU_RAM_ORX_PHA_DIFF__W 16 +#define SCU_RAM_ORX_PHA_DIFF__M 0xFFFF +#define SCU_RAM_ORX_PHA_DIFF__PRE 0x0 + +#define SCU_RAM_ORX_PHA_LOCK_TH__A 0x831F2E +#define SCU_RAM_ORX_PHA_LOCK_TH__W 16 +#define SCU_RAM_ORX_PHA_LOCK_TH__M 0xFFFF +#define SCU_RAM_ORX_PHA_LOCK_TH__PRE 0x0 + +#define SCU_RAM_ORX_PHA_LOCK_WD__A 0x831F2F +#define SCU_RAM_ORX_PHA_LOCK_WD__W 16 +#define SCU_RAM_ORX_PHA_LOCK_WD__M 0xFFFF +#define SCU_RAM_ORX_PHA_LOCK_WD__PRE 0x0 + +#define SCU_RAM_ORX_PHA_ONLOCK_TTH__A 0x831F30 +#define SCU_RAM_ORX_PHA_ONLOCK_TTH__W 16 +#define SCU_RAM_ORX_PHA_ONLOCK_TTH__M 0xFFFF +#define SCU_RAM_ORX_PHA_ONLOCK_TTH__PRE 0x0 + +#define SCU_RAM_ORX_PHA_UNLOCK_TTH__A 0x831F31 +#define SCU_RAM_ORX_PHA_UNLOCK_TTH__W 16 +#define SCU_RAM_ORX_PHA_UNLOCK_TTH__M 0xFFFF +#define SCU_RAM_ORX_PHA_UNLOCK_TTH__PRE 0x0 + +#define SCU_RAM_ORX_PHA_LOCK_TOTH__A 0x831F32 +#define SCU_RAM_ORX_PHA_LOCK_TOTH__W 16 +#define SCU_RAM_ORX_PHA_LOCK_TOTH__M 0xFFFF +#define SCU_RAM_ORX_PHA_LOCK_TOTH__PRE 0x0 + +#define SCU_RAM_ORX_PHA_LOCK_MASK__A 0x831F33 +#define SCU_RAM_ORX_PHA_LOCK_MASK__W 8 +#define SCU_RAM_ORX_PHA_LOCK_MASK__M 0xFF +#define SCU_RAM_ORX_PHA_LOCK_MASK__PRE 0x0 + +#define SCU_RAM_ORX_TIM_OFFSET__A 0x831F34 +#define SCU_RAM_ORX_TIM_OFFSET__W 16 +#define SCU_RAM_ORX_TIM_OFFSET__M 0xFFFF +#define SCU_RAM_ORX_TIM_OFFSET__PRE 0x0 + +#define SCU_RAM_ORX_TIM_DIFF__A 0x831F35 +#define SCU_RAM_ORX_TIM_DIFF__W 16 +#define SCU_RAM_ORX_TIM_DIFF__M 0xFFFF +#define SCU_RAM_ORX_TIM_DIFF__PRE 0x0 + +#define SCU_RAM_ORX_TIM_LOCK_TH__A 0x831F36 +#define SCU_RAM_ORX_TIM_LOCK_TH__W 16 +#define SCU_RAM_ORX_TIM_LOCK_TH__M 0xFFFF +#define SCU_RAM_ORX_TIM_LOCK_TH__PRE 0x0 + +#define SCU_RAM_ORX_TIM_LOCK_WD__A 0x831F37 +#define SCU_RAM_ORX_TIM_LOCK_WD__W 16 +#define SCU_RAM_ORX_TIM_LOCK_WD__M 0xFFFF +#define SCU_RAM_ORX_TIM_LOCK_WD__PRE 0x0 + +#define SCU_RAM_ORX_TIM_ONLOCK_TTH__A 0x831F38 +#define SCU_RAM_ORX_TIM_ONLOCK_TTH__W 16 +#define SCU_RAM_ORX_TIM_ONLOCK_TTH__M 0xFFFF +#define SCU_RAM_ORX_TIM_ONLOCK_TTH__PRE 0x0 + +#define SCU_RAM_ORX_TIM_UNLOCK_TTH__A 0x831F39 +#define SCU_RAM_ORX_TIM_UNLOCK_TTH__W 16 +#define SCU_RAM_ORX_TIM_UNLOCK_TTH__M 0xFFFF +#define SCU_RAM_ORX_TIM_UNLOCK_TTH__PRE 0x0 + +#define SCU_RAM_ORX_TIM_LOCK_TOTH__A 0x831F3A +#define SCU_RAM_ORX_TIM_LOCK_TOTH__W 16 +#define SCU_RAM_ORX_TIM_LOCK_TOTH__M 0xFFFF +#define SCU_RAM_ORX_TIM_LOCK_TOTH__PRE 0x0 + +#define SCU_RAM_ORX_TIM_LOCK_MASK__A 0x831F3B +#define SCU_RAM_ORX_TIM_LOCK_MASK__W 8 +#define SCU_RAM_ORX_TIM_LOCK_MASK__M 0xFF +#define SCU_RAM_ORX_TIM_LOCK_MASK__PRE 0x0 + +#define SCU_RAM_ORX_EQU_DIFF__A 0x831F3C +#define SCU_RAM_ORX_EQU_DIFF__W 16 +#define SCU_RAM_ORX_EQU_DIFF__M 0xFFFF +#define SCU_RAM_ORX_EQU_DIFF__PRE 0x0 + +#define SCU_RAM_ORX_EQU_LOCK_TH__A 0x831F3D +#define SCU_RAM_ORX_EQU_LOCK_TH__W 16 +#define SCU_RAM_ORX_EQU_LOCK_TH__M 0xFFFF +#define SCU_RAM_ORX_EQU_LOCK_TH__PRE 0x0 + +#define SCU_RAM_ORX_EQU_LOCK_WD__A 0x831F3E +#define SCU_RAM_ORX_EQU_LOCK_WD__W 16 +#define SCU_RAM_ORX_EQU_LOCK_WD__M 0xFFFF +#define SCU_RAM_ORX_EQU_LOCK_WD__PRE 0x0 + +#define SCU_RAM_ORX_EQU_ONLOCK_TTH__A 0x831F3F +#define SCU_RAM_ORX_EQU_ONLOCK_TTH__W 16 +#define SCU_RAM_ORX_EQU_ONLOCK_TTH__M 0xFFFF +#define SCU_RAM_ORX_EQU_ONLOCK_TTH__PRE 0x0 + +#define SCU_RAM_ORX_EQU_UNLOCK_TTH__A 0x831F40 +#define SCU_RAM_ORX_EQU_UNLOCK_TTH__W 16 +#define SCU_RAM_ORX_EQU_UNLOCK_TTH__M 0xFFFF +#define SCU_RAM_ORX_EQU_UNLOCK_TTH__PRE 0x0 + +#define SCU_RAM_ORX_EQU_LOCK_TOTH__A 0x831F41 +#define SCU_RAM_ORX_EQU_LOCK_TOTH__W 16 +#define SCU_RAM_ORX_EQU_LOCK_TOTH__M 0xFFFF +#define SCU_RAM_ORX_EQU_LOCK_TOTH__PRE 0x0 + +#define SCU_RAM_ORX_EQU_LOCK_MASK__A 0x831F42 +#define SCU_RAM_ORX_EQU_LOCK_MASK__W 8 +#define SCU_RAM_ORX_EQU_LOCK_MASK__M 0xFF +#define SCU_RAM_ORX_EQU_LOCK_MASK__PRE 0x0 + +#define SCU_RAM_ORX_FLT_FRQ__A 0x831F43 +#define SCU_RAM_ORX_FLT_FRQ__W 16 +#define SCU_RAM_ORX_FLT_FRQ__M 0xFFFF +#define SCU_RAM_ORX_FLT_FRQ__PRE 0x0 +#define SCU_RAM_ORX_RST_CPH__A 0x831F44 +#define SCU_RAM_ORX_RST_CPH__W 4 +#define SCU_RAM_ORX_RST_CPH__M 0xF +#define SCU_RAM_ORX_RST_CPH__PRE 0x0 + +#define SCU_RAM_ORX_RST_CPH_RST_CPH__B 0 +#define SCU_RAM_ORX_RST_CPH_RST_CPH__W 4 +#define SCU_RAM_ORX_RST_CPH_RST_CPH__M 0xF +#define SCU_RAM_ORX_RST_CPH_RST_CPH__PRE 0x0 + +#define SCU_RAM_ORX_RST_CTI__A 0x831F45 +#define SCU_RAM_ORX_RST_CTI__W 4 +#define SCU_RAM_ORX_RST_CTI__M 0xF +#define SCU_RAM_ORX_RST_CTI__PRE 0x0 + +#define SCU_RAM_ORX_RST_CTI_RST_CTI__B 0 +#define SCU_RAM_ORX_RST_CTI_RST_CTI__W 4 +#define SCU_RAM_ORX_RST_CTI_RST_CTI__M 0xF +#define SCU_RAM_ORX_RST_CTI_RST_CTI__PRE 0x0 + +#define SCU_RAM_ORX_RST_KRN__A 0x831F46 +#define SCU_RAM_ORX_RST_KRN__W 4 +#define SCU_RAM_ORX_RST_KRN__M 0xF +#define SCU_RAM_ORX_RST_KRN__PRE 0x0 + +#define SCU_RAM_ORX_RST_KRN_RST_KRN__B 0 +#define SCU_RAM_ORX_RST_KRN_RST_KRN__W 4 +#define SCU_RAM_ORX_RST_KRN_RST_KRN__M 0xF +#define SCU_RAM_ORX_RST_KRN_RST_KRN__PRE 0x0 + +#define SCU_RAM_ORX_RST_KRP__A 0x831F47 +#define SCU_RAM_ORX_RST_KRP__W 4 +#define SCU_RAM_ORX_RST_KRP__M 0xF +#define SCU_RAM_ORX_RST_KRP__PRE 0x0 + +#define SCU_RAM_ORX_RST_KRP_RST_KRP__B 0 +#define SCU_RAM_ORX_RST_KRP_RST_KRP__W 4 +#define SCU_RAM_ORX_RST_KRP_RST_KRP__M 0xF +#define SCU_RAM_ORX_RST_KRP_RST_KRP__PRE 0x0 + +#define SCU_RAM_ATV_STANDARD__A 0x831F48 +#define SCU_RAM_ATV_STANDARD__W 12 +#define SCU_RAM_ATV_STANDARD__M 0xFFF +#define SCU_RAM_ATV_STANDARD__PRE 0x0 + +#define SCU_RAM_ATV_STANDARD_STANDARD__B 0 +#define SCU_RAM_ATV_STANDARD_STANDARD__W 12 +#define SCU_RAM_ATV_STANDARD_STANDARD__M 0xFFF +#define SCU_RAM_ATV_STANDARD_STANDARD__PRE 0x0 +#define SCU_RAM_ATV_STANDARD_STANDARD_MN 0x2 +#define SCU_RAM_ATV_STANDARD_STANDARD_B 0x103 +#define SCU_RAM_ATV_STANDARD_STANDARD_G 0x3 +#define SCU_RAM_ATV_STANDARD_STANDARD_DK 0x4 +#define SCU_RAM_ATV_STANDARD_STANDARD_L 0x9 +#define SCU_RAM_ATV_STANDARD_STANDARD_LP 0x109 +#define SCU_RAM_ATV_STANDARD_STANDARD_I 0xA +#define SCU_RAM_ATV_STANDARD_STANDARD_FM 0x40 + +#define SCU_RAM_ATV_DETECT__A 0x831F49 +#define SCU_RAM_ATV_DETECT__W 1 +#define SCU_RAM_ATV_DETECT__M 0x1 +#define SCU_RAM_ATV_DETECT__PRE 0x0 + +#define SCU_RAM_ATV_DETECT_DETECT__B 0 +#define SCU_RAM_ATV_DETECT_DETECT__W 1 +#define SCU_RAM_ATV_DETECT_DETECT__M 0x1 +#define SCU_RAM_ATV_DETECT_DETECT__PRE 0x0 +#define SCU_RAM_ATV_DETECT_DETECT_FALSE 0x0 +#define SCU_RAM_ATV_DETECT_DETECT_TRUE 0x1 + +#define SCU_RAM_ATV_DETECT_TH__A 0x831F4A +#define SCU_RAM_ATV_DETECT_TH__W 8 +#define SCU_RAM_ATV_DETECT_TH__M 0xFF +#define SCU_RAM_ATV_DETECT_TH__PRE 0x0 + +#define SCU_RAM_ATV_DETECT_TH_DETECT_TH__B 0 +#define SCU_RAM_ATV_DETECT_TH_DETECT_TH__W 8 +#define SCU_RAM_ATV_DETECT_TH_DETECT_TH__M 0xFF +#define SCU_RAM_ATV_DETECT_TH_DETECT_TH__PRE 0x0 + +#define SCU_RAM_ATV_LOCK__A 0x831F4B +#define SCU_RAM_ATV_LOCK__W 2 +#define SCU_RAM_ATV_LOCK__M 0x3 +#define SCU_RAM_ATV_LOCK__PRE 0x0 + +#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT__B 0 +#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT__W 1 +#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT__M 0x1 +#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT__PRE 0x0 +#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT_NO_LOCK 0x0 +#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT_LOCK 0x1 + +#define SCU_RAM_ATV_LOCK_SYNC_FLAG__B 1 +#define SCU_RAM_ATV_LOCK_SYNC_FLAG__W 1 +#define SCU_RAM_ATV_LOCK_SYNC_FLAG__M 0x2 +#define SCU_RAM_ATV_LOCK_SYNC_FLAG__PRE 0x0 +#define SCU_RAM_ATV_LOCK_SYNC_FLAG_NO_SYNC 0x0 +#define SCU_RAM_ATV_LOCK_SYNC_FLAG_SYNC 0x2 + +#define SCU_RAM_ATV_CR_LOCK__A 0x831F4C +#define SCU_RAM_ATV_CR_LOCK__W 11 +#define SCU_RAM_ATV_CR_LOCK__M 0x7FF +#define SCU_RAM_ATV_CR_LOCK__PRE 0x0 + +#define SCU_RAM_ATV_CR_LOCK_CR_LOCK__B 0 +#define SCU_RAM_ATV_CR_LOCK_CR_LOCK__W 11 +#define SCU_RAM_ATV_CR_LOCK_CR_LOCK__M 0x7FF +#define SCU_RAM_ATV_CR_LOCK_CR_LOCK__PRE 0x0 + +#define SCU_RAM_ATV_AGC_MODE__A 0x831F4D +#define SCU_RAM_ATV_AGC_MODE__W 8 +#define SCU_RAM_ATV_AGC_MODE__M 0xFF +#define SCU_RAM_ATV_AGC_MODE__PRE 0x0 + +#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL__B 2 +#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL__W 1 +#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL__M 0x4 +#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL__PRE 0x0 +#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_FAST 0x0 +#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW 0x4 + +#define SCU_RAM_ATV_AGC_MODE_BP_EN__B 3 +#define SCU_RAM_ATV_AGC_MODE_BP_EN__W 1 +#define SCU_RAM_ATV_AGC_MODE_BP_EN__M 0x8 +#define SCU_RAM_ATV_AGC_MODE_BP_EN__PRE 0x0 +#define SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_DISABLE 0x0 +#define SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_ENABLE 0x8 + +#define SCU_RAM_ATV_AGC_MODE_SIF_STD__B 4 +#define SCU_RAM_ATV_AGC_MODE_SIF_STD__W 2 +#define SCU_RAM_ATV_AGC_MODE_SIF_STD__M 0x30 +#define SCU_RAM_ATV_AGC_MODE_SIF_STD__PRE 0x0 +#define SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_OFF 0x0 +#define SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM 0x10 +#define SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_AM 0x20 + +#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__B 6 +#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__W 1 +#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__M 0x40 +#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__PRE 0x0 +#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_DISABLE 0x0 +#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE 0x40 + +#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__B 7 +#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__W 1 +#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__M 0x80 +#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__PRE 0x0 +#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP_MWA_ENABLE 0x0 +#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP_MWA_DISABLE 0x80 + + +#define SCU_RAM_ATV_RSV_01__A 0x831F4E +#define SCU_RAM_ATV_RSV_01__W 16 +#define SCU_RAM_ATV_RSV_01__M 0xFFFF +#define SCU_RAM_ATV_RSV_01__PRE 0x0 + +#define SCU_RAM_ATV_RSV_02__A 0x831F4F +#define SCU_RAM_ATV_RSV_02__W 16 +#define SCU_RAM_ATV_RSV_02__M 0xFFFF +#define SCU_RAM_ATV_RSV_02__PRE 0x0 + +#define SCU_RAM_ATV_RSV_03__A 0x831F50 +#define SCU_RAM_ATV_RSV_03__W 16 +#define SCU_RAM_ATV_RSV_03__M 0xFFFF +#define SCU_RAM_ATV_RSV_03__PRE 0x0 + +#define SCU_RAM_ATV_RSV_04__A 0x831F51 +#define SCU_RAM_ATV_RSV_04__W 16 +#define SCU_RAM_ATV_RSV_04__M 0xFFFF +#define SCU_RAM_ATV_RSV_04__PRE 0x0 +#define SCU_RAM_ATV_FAGC_TH_RED__A 0x831F52 +#define SCU_RAM_ATV_FAGC_TH_RED__W 8 +#define SCU_RAM_ATV_FAGC_TH_RED__M 0xFF +#define SCU_RAM_ATV_FAGC_TH_RED__PRE 0x0 + +#define SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__B 0 +#define SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__W 8 +#define SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__M 0xFF +#define SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__PRE 0x0 + +#define SCU_RAM_ATV_AMS_MAX_REF__A 0x831F53 +#define SCU_RAM_ATV_AMS_MAX_REF__W 11 +#define SCU_RAM_ATV_AMS_MAX_REF__M 0x7FF +#define SCU_RAM_ATV_AMS_MAX_REF__PRE 0x0 + +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__B 0 +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__W 11 +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__M 0x7FF +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__PRE 0x0 +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_BG_MN 0x2BC +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_DK 0x2D0 +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_I 0x314 +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_LLP 0x28A + +#define SCU_RAM_ATV_ACT_AMX__A 0x831F54 +#define SCU_RAM_ATV_ACT_AMX__W 11 +#define SCU_RAM_ATV_ACT_AMX__M 0x7FF +#define SCU_RAM_ATV_ACT_AMX__PRE 0x0 + +#define SCU_RAM_ATV_ACT_AMX_ACT_AMX__B 0 +#define SCU_RAM_ATV_ACT_AMX_ACT_AMX__W 11 +#define SCU_RAM_ATV_ACT_AMX_ACT_AMX__M 0x7FF +#define SCU_RAM_ATV_ACT_AMX_ACT_AMX__PRE 0x0 + +#define SCU_RAM_ATV_ACT_AMI__A 0x831F55 +#define SCU_RAM_ATV_ACT_AMI__W 11 +#define SCU_RAM_ATV_ACT_AMI__M 0x7FF +#define SCU_RAM_ATV_ACT_AMI__PRE 0x0 + +#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__B 0 +#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__W 11 +#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__M 0x7FF +#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__PRE 0x0 + + +#define SCU_RAM_ATV_RSV_05__A 0x831F56 +#define SCU_RAM_ATV_RSV_05__W 16 +#define SCU_RAM_ATV_RSV_05__M 0xFFFF +#define SCU_RAM_ATV_RSV_05__PRE 0x0 + +#define SCU_RAM_ATV_RSV_06__A 0x831F57 +#define SCU_RAM_ATV_RSV_06__W 16 +#define SCU_RAM_ATV_RSV_06__M 0xFFFF +#define SCU_RAM_ATV_RSV_06__PRE 0x0 + +#define SCU_RAM_ATV_RSV_07__A 0x831F58 +#define SCU_RAM_ATV_RSV_07__W 16 +#define SCU_RAM_ATV_RSV_07__M 0xFFFF +#define SCU_RAM_ATV_RSV_07__PRE 0x0 + +#define SCU_RAM_ATV_RSV_08__A 0x831F59 +#define SCU_RAM_ATV_RSV_08__W 16 +#define SCU_RAM_ATV_RSV_08__M 0xFFFF +#define SCU_RAM_ATV_RSV_08__PRE 0x0 + +#define SCU_RAM_ATV_RSV_09__A 0x831F5A +#define SCU_RAM_ATV_RSV_09__W 16 +#define SCU_RAM_ATV_RSV_09__M 0xFFFF +#define SCU_RAM_ATV_RSV_09__PRE 0x0 + +#define SCU_RAM_ATV_RSV_10__A 0x831F5B +#define SCU_RAM_ATV_RSV_10__W 16 +#define SCU_RAM_ATV_RSV_10__M 0xFFFF +#define SCU_RAM_ATV_RSV_10__PRE 0x0 + +#define SCU_RAM_ATV_RSV_11__A 0x831F5C +#define SCU_RAM_ATV_RSV_11__W 16 +#define SCU_RAM_ATV_RSV_11__M 0xFFFF +#define SCU_RAM_ATV_RSV_11__PRE 0x0 + +#define SCU_RAM_ATV_RSV_12__A 0x831F5D +#define SCU_RAM_ATV_RSV_12__W 16 +#define SCU_RAM_ATV_RSV_12__M 0xFFFF +#define SCU_RAM_ATV_RSV_12__PRE 0x0 +#define SCU_RAM_ATV_VID_GAIN_HI__A 0x831F5E +#define SCU_RAM_ATV_VID_GAIN_HI__W 16 +#define SCU_RAM_ATV_VID_GAIN_HI__M 0xFFFF +#define SCU_RAM_ATV_VID_GAIN_HI__PRE 0x0 + +#define SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__B 0 +#define SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__W 16 +#define SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__M 0xFFFF +#define SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__PRE 0x0 + +#define SCU_RAM_ATV_VID_GAIN_LO__A 0x831F5F +#define SCU_RAM_ATV_VID_GAIN_LO__W 8 +#define SCU_RAM_ATV_VID_GAIN_LO__M 0xFF +#define SCU_RAM_ATV_VID_GAIN_LO__PRE 0x0 + +#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__B 0 +#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__W 8 +#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__M 0xFF +#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__PRE 0x0 + + +#define SCU_RAM_ATV_RSV_13__A 0x831F60 +#define SCU_RAM_ATV_RSV_13__W 16 +#define SCU_RAM_ATV_RSV_13__M 0xFFFF +#define SCU_RAM_ATV_RSV_13__PRE 0x0 + +#define SCU_RAM_ATV_RSV_14__A 0x831F61 +#define SCU_RAM_ATV_RSV_14__W 16 +#define SCU_RAM_ATV_RSV_14__M 0xFFFF +#define SCU_RAM_ATV_RSV_14__PRE 0x0 + +#define SCU_RAM_ATV_RSV_15__A 0x831F62 +#define SCU_RAM_ATV_RSV_15__W 16 +#define SCU_RAM_ATV_RSV_15__M 0xFFFF +#define SCU_RAM_ATV_RSV_15__PRE 0x0 + +#define SCU_RAM_ATV_RSV_16__A 0x831F63 +#define SCU_RAM_ATV_RSV_16__W 16 +#define SCU_RAM_ATV_RSV_16__M 0xFFFF +#define SCU_RAM_ATV_RSV_16__PRE 0x0 +#define SCU_RAM_ATV_AAGC_CNT__A 0x831F64 +#define SCU_RAM_ATV_AAGC_CNT__W 8 +#define SCU_RAM_ATV_AAGC_CNT__M 0xFF +#define SCU_RAM_ATV_AAGC_CNT__PRE 0x0 + +#define SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__B 0 +#define SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__W 8 +#define SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__M 0xFF +#define SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__PRE 0x0 + +#define SCU_RAM_ATV_SIF_GAIN__A 0x831F65 +#define SCU_RAM_ATV_SIF_GAIN__W 11 +#define SCU_RAM_ATV_SIF_GAIN__M 0x7FF +#define SCU_RAM_ATV_SIF_GAIN__PRE 0x0 + +#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__B 0 +#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__W 11 +#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__M 0x7FF +#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__PRE 0x0 + + +#define SCU_RAM_ATV_RSV_17__A 0x831F66 +#define SCU_RAM_ATV_RSV_17__W 16 +#define SCU_RAM_ATV_RSV_17__M 0xFFFF +#define SCU_RAM_ATV_RSV_17__PRE 0x0 + +#define SCU_RAM_ATV_RSV_18__A 0x831F67 +#define SCU_RAM_ATV_RSV_18__W 16 +#define SCU_RAM_ATV_RSV_18__M 0xFFFF +#define SCU_RAM_ATV_RSV_18__PRE 0x0 + +#define SCU_RAM_ATV_RATE_OFS__A 0x831F68 +#define SCU_RAM_ATV_RATE_OFS__W 12 +#define SCU_RAM_ATV_RATE_OFS__M 0xFFF +#define SCU_RAM_ATV_RATE_OFS__PRE 0x0 + +#define SCU_RAM_ATV_LO_INCR__A 0x831F69 +#define SCU_RAM_ATV_LO_INCR__W 12 +#define SCU_RAM_ATV_LO_INCR__M 0xFFF +#define SCU_RAM_ATV_LO_INCR__PRE 0x0 + +#define SCU_RAM_ATV_IIR_CRIT__A 0x831F6A +#define SCU_RAM_ATV_IIR_CRIT__W 12 +#define SCU_RAM_ATV_IIR_CRIT__M 0xFFF +#define SCU_RAM_ATV_IIR_CRIT__PRE 0x0 + +#define SCU_RAM_ATV_DEF_RATE_OFS__A 0x831F6B +#define SCU_RAM_ATV_DEF_RATE_OFS__W 12 +#define SCU_RAM_ATV_DEF_RATE_OFS__M 0xFFF +#define SCU_RAM_ATV_DEF_RATE_OFS__PRE 0x0 + +#define SCU_RAM_ATV_DEF_LO_INCR__A 0x831F6C +#define SCU_RAM_ATV_DEF_LO_INCR__W 12 +#define SCU_RAM_ATV_DEF_LO_INCR__M 0xFFF +#define SCU_RAM_ATV_DEF_LO_INCR__PRE 0x0 + +#define SCU_RAM_ATV_ENABLE_IIR_WA__A 0x831F6D +#define SCU_RAM_ATV_ENABLE_IIR_WA__W 1 +#define SCU_RAM_ATV_ENABLE_IIR_WA__M 0x1 +#define SCU_RAM_ATV_ENABLE_IIR_WA__PRE 0x0 + +#define SCU_RAM_ATV_MOD_CONTROL__A 0x831F6E +#define SCU_RAM_ATV_MOD_CONTROL__W 12 +#define SCU_RAM_ATV_MOD_CONTROL__M 0xFFF +#define SCU_RAM_ATV_MOD_CONTROL__PRE 0x0 + +#define SCU_RAM_ATV_PAGC_KI_MAX__A 0x831F6F +#define SCU_RAM_ATV_PAGC_KI_MAX__W 12 +#define SCU_RAM_ATV_PAGC_KI_MAX__M 0xFFF +#define SCU_RAM_ATV_PAGC_KI_MAX__PRE 0x0 + +#define SCU_RAM_ATV_BPC_KI_MAX__A 0x831F70 +#define SCU_RAM_ATV_BPC_KI_MAX__W 12 +#define SCU_RAM_ATV_BPC_KI_MAX__M 0xFFF +#define SCU_RAM_ATV_BPC_KI_MAX__PRE 0x0 + +#define SCU_RAM_ATV_NAGC_KI_MAX__A 0x831F71 +#define SCU_RAM_ATV_NAGC_KI_MAX__W 12 +#define SCU_RAM_ATV_NAGC_KI_MAX__M 0xFFF +#define SCU_RAM_ATV_NAGC_KI_MAX__PRE 0x0 +#define SCU_RAM_ATV_NAGC_KI_MIN__A 0x831F72 +#define SCU_RAM_ATV_NAGC_KI_MIN__W 12 +#define SCU_RAM_ATV_NAGC_KI_MIN__M 0xFFF +#define SCU_RAM_ATV_NAGC_KI_MIN__PRE 0x0 + +#define SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__B 0 +#define SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__W 12 +#define SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__M 0xFFF +#define SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__PRE 0x0 + +#define SCU_RAM_ATV_KI_CHANGE_TH__A 0x831F73 +#define SCU_RAM_ATV_KI_CHANGE_TH__W 8 +#define SCU_RAM_ATV_KI_CHANGE_TH__M 0xFF +#define SCU_RAM_ATV_KI_CHANGE_TH__PRE 0x0 + +#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__B 0 +#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__W 8 +#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__M 0xFF +#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__PRE 0x0 +#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH_NEG_MOD 0x14 +#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH_POS_MOD 0x28 + +#define SCU_RAM_QAM_PARAM_ANNEX__A 0x831F74 +#define SCU_RAM_QAM_PARAM_ANNEX__W 2 +#define SCU_RAM_QAM_PARAM_ANNEX__M 0x3 +#define SCU_RAM_QAM_PARAM_ANNEX__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_ANNEX_BIT__B 0 +#define SCU_RAM_QAM_PARAM_ANNEX_BIT__W 2 +#define SCU_RAM_QAM_PARAM_ANNEX_BIT__M 0x3 +#define SCU_RAM_QAM_PARAM_ANNEX_BIT__PRE 0x0 +#define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_A 0x0 +#define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_B 0x1 +#define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_C 0x2 +#define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_D 0x3 + +#define SCU_RAM_QAM_PARAM_CONSTELLATION__A 0x831F75 +#define SCU_RAM_QAM_PARAM_CONSTELLATION__W 3 +#define SCU_RAM_QAM_PARAM_CONSTELLATION__M 0x7 +#define SCU_RAM_QAM_PARAM_CONSTELLATION__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__B 0 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__W 3 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__M 0x7 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__PRE 0x0 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_UNKNOWN 0x0 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_16 0x3 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_32 0x4 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_64 0x5 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_128 0x6 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_256 0x7 + +#define SCU_RAM_QAM_PARAM_INTERLEAVE__A 0x831F76 +#define SCU_RAM_QAM_PARAM_INTERLEAVE__W 8 +#define SCU_RAM_QAM_PARAM_INTERLEAVE__M 0xFF +#define SCU_RAM_QAM_PARAM_INTERLEAVE__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__B 0 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__W 8 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__M 0xFF +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__PRE 0x0 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J1 0x0 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J1_V2 0x1 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J2 0x2 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I64_J2 0x3 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J3 0x4 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I32_J4 0x5 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J4 0x6 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I16_J8 0x7 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J5 0x8 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I8_J16 0x9 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J6 0xA +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J7 0xC +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J8 0xE +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I12_J17 0x10 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I5_J4 0x11 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_UNKNOWN 0xFE +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_AUTO 0xFF + +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__A 0x831F77 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__W 16 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__M 0xFFFF +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__B 0 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__W 16 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__M 0xFFFF +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__A 0x831F78 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__W 16 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__M 0xFFFF +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__B 0 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__W 16 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__M 0xFFFF +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__PRE 0x0 + +#define SCU_RAM_QAM_EQ_CENTERTAP__A 0x831F79 +#define SCU_RAM_QAM_EQ_CENTERTAP__W 16 +#define SCU_RAM_QAM_EQ_CENTERTAP__M 0xFFFF +#define SCU_RAM_QAM_EQ_CENTERTAP__PRE 0x0 + +#define SCU_RAM_QAM_EQ_CENTERTAP_BIT__B 0 +#define SCU_RAM_QAM_EQ_CENTERTAP_BIT__W 8 +#define SCU_RAM_QAM_EQ_CENTERTAP_BIT__M 0xFF +#define SCU_RAM_QAM_EQ_CENTERTAP_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_0__A 0x831F7A +#define SCU_RAM_QAM_WR_RSV_0__W 16 +#define SCU_RAM_QAM_WR_RSV_0__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_0__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_0_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_0_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_0_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_0_BIT__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__A 0x831F7B +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__W 16 +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__M 0xFFFF +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__B 0 +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__W 16 +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__M 0xFFFF +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__A 0x831F7C +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__W 16 +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__M 0xFFFF +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__B 0 +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__W 16 +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__M 0xFFFF +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_5__A 0x831F7D +#define SCU_RAM_QAM_WR_RSV_5__W 16 +#define SCU_RAM_QAM_WR_RSV_5__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_5__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_5_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_5_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_5_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_5_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_6__A 0x831F7E +#define SCU_RAM_QAM_WR_RSV_6__W 16 +#define SCU_RAM_QAM_WR_RSV_6__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_6__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_6_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_6_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_6_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_6_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_7__A 0x831F7F +#define SCU_RAM_QAM_WR_RSV_7__W 16 +#define SCU_RAM_QAM_WR_RSV_7__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_7__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_7_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_7_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_7_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_7_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_8__A 0x831F80 +#define SCU_RAM_QAM_WR_RSV_8__W 16 +#define SCU_RAM_QAM_WR_RSV_8__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_8__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_8_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_8_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_8_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_8_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_9__A 0x831F81 +#define SCU_RAM_QAM_WR_RSV_9__W 16 +#define SCU_RAM_QAM_WR_RSV_9__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_9__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_9_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_9_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_9_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_9_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_10__A 0x831F82 +#define SCU_RAM_QAM_WR_RSV_10__W 16 +#define SCU_RAM_QAM_WR_RSV_10__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_10__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_10_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_10_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_10_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_10_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_FMHUM_TO__A 0x831F83 +#define SCU_RAM_QAM_FSM_FMHUM_TO__W 16 +#define SCU_RAM_QAM_FSM_FMHUM_TO__M 0xFFFF +#define SCU_RAM_QAM_FSM_FMHUM_TO__PRE 0x0 + +#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT__B 0 +#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT__W 16 +#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT_NO_FMHUM_TO 0x0 + +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A 0x831F84 +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__W 16 +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__M 0xFFFF +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__B 0 +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__W 16 +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A 0x831F85 +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__W 16 +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__B 0 +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__W 16 +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A 0x831F86 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A 0x831F87 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A 0x831F88 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A 0x831F89 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A 0x831F8A +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_STATE_TGT__A 0x831F8B +#define SCU_RAM_QAM_FSM_STATE_TGT__W 4 +#define SCU_RAM_QAM_FSM_STATE_TGT__M 0xF +#define SCU_RAM_QAM_FSM_STATE_TGT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT__B 0 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT__W 4 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT__M 0xF +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_AMP 0x0 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_RATE 0x1 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_FREQ 0x2 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_UPRIGHT 0x3 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_PHASE 0x4 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_TRACKING_PHNOISE 0x5 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_TRACKING 0x6 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_TRACKING_BURST 0x7 + +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__A 0x831F8C +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__W 9 +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__M 0x1FF +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__B 0 +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__W 1 +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__M 0x1 +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__PRE 0x0 + +#define SCU_RAM_QAM_FSM_ATH__A 0x831F8D +#define SCU_RAM_QAM_FSM_ATH__W 16 +#define SCU_RAM_QAM_FSM_ATH__M 0xFFFF +#define SCU_RAM_QAM_FSM_ATH__PRE 0x0 + +#define SCU_RAM_QAM_FSM_ATH_BIT__B 0 +#define SCU_RAM_QAM_FSM_ATH_BIT__W 16 +#define SCU_RAM_QAM_FSM_ATH_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_ATH_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_RTH__A 0x831F8E +#define SCU_RAM_QAM_FSM_RTH__W 16 +#define SCU_RAM_QAM_FSM_RTH__M 0xFFFF +#define SCU_RAM_QAM_FSM_RTH__PRE 0x0 + +#define SCU_RAM_QAM_FSM_RTH_BIT__B 0 +#define SCU_RAM_QAM_FSM_RTH_BIT__W 16 +#define SCU_RAM_QAM_FSM_RTH_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_RTH_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_16 0x8C +#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_32 0x50 +#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_64 0x4E +#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_128 0x32 +#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_256 0x2D + +#define SCU_RAM_QAM_FSM_FTH__A 0x831F8F +#define SCU_RAM_QAM_FSM_FTH__W 16 +#define SCU_RAM_QAM_FSM_FTH__M 0xFFFF +#define SCU_RAM_QAM_FSM_FTH__PRE 0x0 + +#define SCU_RAM_QAM_FSM_FTH_BIT__B 0 +#define SCU_RAM_QAM_FSM_FTH_BIT__W 16 +#define SCU_RAM_QAM_FSM_FTH_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_FTH_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_16 0x32 +#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_32 0x1E +#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_64 0x1E +#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_128 0x14 +#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_256 0x14 + +#define SCU_RAM_QAM_FSM_PTH__A 0x831F90 +#define SCU_RAM_QAM_FSM_PTH__W 16 +#define SCU_RAM_QAM_FSM_PTH__M 0xFFFF +#define SCU_RAM_QAM_FSM_PTH__PRE 0x0 + +#define SCU_RAM_QAM_FSM_PTH_BIT__B 0 +#define SCU_RAM_QAM_FSM_PTH_BIT__W 16 +#define SCU_RAM_QAM_FSM_PTH_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_PTH_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_16 0xC8 +#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_32 0x96 +#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_64 0x8C +#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_128 0x64 +#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_256 0x64 + +#define SCU_RAM_QAM_FSM_MTH__A 0x831F91 +#define SCU_RAM_QAM_FSM_MTH__W 16 +#define SCU_RAM_QAM_FSM_MTH__M 0xFFFF +#define SCU_RAM_QAM_FSM_MTH__PRE 0x0 + +#define SCU_RAM_QAM_FSM_MTH_BIT__B 0 +#define SCU_RAM_QAM_FSM_MTH_BIT__W 16 +#define SCU_RAM_QAM_FSM_MTH_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_MTH_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_16 0x5A +#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_32 0x50 +#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_64 0x46 +#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_128 0x3C +#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_256 0x50 + +#define SCU_RAM_QAM_FSM_CTH__A 0x831F92 +#define SCU_RAM_QAM_FSM_CTH__W 16 +#define SCU_RAM_QAM_FSM_CTH__M 0xFFFF +#define SCU_RAM_QAM_FSM_CTH__PRE 0x0 + +#define SCU_RAM_QAM_FSM_CTH_BIT__B 0 +#define SCU_RAM_QAM_FSM_CTH_BIT__W 16 +#define SCU_RAM_QAM_FSM_CTH_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_CTH_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_16 0xA0 +#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_32 0x8C +#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_64 0x8C +#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_128 0x8C +#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_256 0x8C + +#define SCU_RAM_QAM_FSM_QTH__A 0x831F93 +#define SCU_RAM_QAM_FSM_QTH__W 16 +#define SCU_RAM_QAM_FSM_QTH__M 0xFFFF +#define SCU_RAM_QAM_FSM_QTH__PRE 0x0 + +#define SCU_RAM_QAM_FSM_QTH_BIT__B 0 +#define SCU_RAM_QAM_FSM_QTH_BIT__W 16 +#define SCU_RAM_QAM_FSM_QTH_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_QTH_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_16 0xE6 +#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_32 0xAA +#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_64 0xC3 +#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_128 0x8C +#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_256 0x96 + +#define SCU_RAM_QAM_FSM_RATE_LIM__A 0x831F94 +#define SCU_RAM_QAM_FSM_RATE_LIM__W 16 +#define SCU_RAM_QAM_FSM_RATE_LIM__M 0xFFFF +#define SCU_RAM_QAM_FSM_RATE_LIM__PRE 0x0 + +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT__B 0 +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT__W 16 +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_16 0x46 +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_32 0x46 +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_64 0x46 +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_128 0x46 +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_256 0x46 + +#define SCU_RAM_QAM_FSM_FREQ_LIM__A 0x831F95 +#define SCU_RAM_QAM_FSM_FREQ_LIM__W 16 +#define SCU_RAM_QAM_FSM_FREQ_LIM__M 0xFFFF +#define SCU_RAM_QAM_FSM_FREQ_LIM__PRE 0x0 + +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT__B 0 +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT__W 16 +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_16 0x1E +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_32 0x14 +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_64 0x28 +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_128 0x8 +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_256 0x28 + +#define SCU_RAM_QAM_FSM_COUNT_LIM__A 0x831F96 +#define SCU_RAM_QAM_FSM_COUNT_LIM__W 16 +#define SCU_RAM_QAM_FSM_COUNT_LIM__M 0xFFFF +#define SCU_RAM_QAM_FSM_COUNT_LIM__PRE 0x0 + +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT__B 0 +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT__W 16 +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_16 0x4 +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_32 0x6 +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_64 0x6 +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_128 0x7 +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_256 0x6 + +#define SCU_RAM_QAM_LC_CA_COARSE__A 0x831F97 +#define SCU_RAM_QAM_LC_CA_COARSE__W 16 +#define SCU_RAM_QAM_LC_CA_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CA_COARSE__PRE 0x0 + +#define SCU_RAM_QAM_LC_CA_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CA_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CA_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CA_COARSE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CA_MEDIUM__A 0x831F98 +#define SCU_RAM_QAM_LC_CA_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CA_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CA_MEDIUM__PRE 0x0 + +#define SCU_RAM_QAM_LC_CA_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CA_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CA_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CA_MEDIUM_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CA_FINE__A 0x831F99 +#define SCU_RAM_QAM_LC_CA_FINE__W 16 +#define SCU_RAM_QAM_LC_CA_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CA_FINE__PRE 0x0 + +#define SCU_RAM_QAM_LC_CA_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CA_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CA_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CA_FINE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CP_COARSE__A 0x831F9A +#define SCU_RAM_QAM_LC_CP_COARSE__W 16 +#define SCU_RAM_QAM_LC_CP_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CP_COARSE__PRE 0x0 + +#define SCU_RAM_QAM_LC_CP_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CP_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CP_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CP_COARSE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CP_MEDIUM__A 0x831F9B +#define SCU_RAM_QAM_LC_CP_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CP_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CP_MEDIUM__PRE 0x0 + +#define SCU_RAM_QAM_LC_CP_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CP_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CP_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CP_MEDIUM_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CP_FINE__A 0x831F9C +#define SCU_RAM_QAM_LC_CP_FINE__W 16 +#define SCU_RAM_QAM_LC_CP_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CP_FINE__PRE 0x0 + +#define SCU_RAM_QAM_LC_CP_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CP_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CP_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CP_FINE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CI_COARSE__A 0x831F9D +#define SCU_RAM_QAM_LC_CI_COARSE__W 16 +#define SCU_RAM_QAM_LC_CI_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CI_COARSE__PRE 0x0 + +#define SCU_RAM_QAM_LC_CI_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CI_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CI_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CI_COARSE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CI_MEDIUM__A 0x831F9E +#define SCU_RAM_QAM_LC_CI_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CI_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CI_MEDIUM__PRE 0x0 + +#define SCU_RAM_QAM_LC_CI_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CI_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CI_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CI_MEDIUM_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CI_FINE__A 0x831F9F +#define SCU_RAM_QAM_LC_CI_FINE__W 16 +#define SCU_RAM_QAM_LC_CI_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CI_FINE__PRE 0x0 + +#define SCU_RAM_QAM_LC_CI_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CI_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CI_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CI_FINE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_EP_COARSE__A 0x831FA0 +#define SCU_RAM_QAM_LC_EP_COARSE__W 16 +#define SCU_RAM_QAM_LC_EP_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_EP_COARSE__PRE 0x0 + +#define SCU_RAM_QAM_LC_EP_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_EP_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_EP_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_EP_COARSE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_EP_MEDIUM__A 0x831FA1 +#define SCU_RAM_QAM_LC_EP_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_EP_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_EP_MEDIUM__PRE 0x0 + +#define SCU_RAM_QAM_LC_EP_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_EP_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_EP_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_EP_MEDIUM_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_EP_FINE__A 0x831FA2 +#define SCU_RAM_QAM_LC_EP_FINE__W 16 +#define SCU_RAM_QAM_LC_EP_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_EP_FINE__PRE 0x0 + +#define SCU_RAM_QAM_LC_EP_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_EP_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_EP_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_EP_FINE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_EI_COARSE__A 0x831FA3 +#define SCU_RAM_QAM_LC_EI_COARSE__W 16 +#define SCU_RAM_QAM_LC_EI_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_EI_COARSE__PRE 0x0 + +#define SCU_RAM_QAM_LC_EI_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_EI_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_EI_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_EI_COARSE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_EI_MEDIUM__A 0x831FA4 +#define SCU_RAM_QAM_LC_EI_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_EI_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_EI_MEDIUM__PRE 0x0 + +#define SCU_RAM_QAM_LC_EI_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_EI_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_EI_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_EI_MEDIUM_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_EI_FINE__A 0x831FA5 +#define SCU_RAM_QAM_LC_EI_FINE__W 16 +#define SCU_RAM_QAM_LC_EI_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_EI_FINE__PRE 0x0 + +#define SCU_RAM_QAM_LC_EI_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_EI_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_EI_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_EI_FINE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 +#define SCU_RAM_QAM_LC_CF_COARSE__W 16 +#define SCU_RAM_QAM_LC_CF_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF_COARSE__PRE 0x0 + +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 +#define SCU_RAM_QAM_LC_CF_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CF_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CF_MEDIUM__PRE 0x0 + +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 +#define SCU_RAM_QAM_LC_CF_FINE__W 16 +#define SCU_RAM_QAM_LC_CF_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF_FINE__PRE 0x0 + +#define SCU_RAM_QAM_LC_CF_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF_FINE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CF1_COARSE__A 0x831FA9 +#define SCU_RAM_QAM_LC_CF1_COARSE__W 16 +#define SCU_RAM_QAM_LC_CF1_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF1_COARSE__PRE 0x0 + +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CF1_MEDIUM__A 0x831FAA +#define SCU_RAM_QAM_LC_CF1_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CF1_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CF1_MEDIUM__PRE 0x0 + +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CF1_FINE__A 0x831FAB +#define SCU_RAM_QAM_LC_CF1_FINE__W 16 +#define SCU_RAM_QAM_LC_CF1_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF1_FINE__PRE 0x0 + +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_SL_SIG_POWER__A 0x831FAC +#define SCU_RAM_QAM_SL_SIG_POWER__W 16 +#define SCU_RAM_QAM_SL_SIG_POWER__M 0xFFFF +#define SCU_RAM_QAM_SL_SIG_POWER__PRE 0x0 + +#define SCU_RAM_QAM_SL_SIG_POWER_BIT__B 0 +#define SCU_RAM_QAM_SL_SIG_POWER_BIT__W 16 +#define SCU_RAM_QAM_SL_SIG_POWER_BIT__M 0xFFFF +#define SCU_RAM_QAM_SL_SIG_POWER_BIT__PRE 0x0 + +#define SCU_RAM_QAM_EQ_CMA_RAD0__A 0x831FAD +#define SCU_RAM_QAM_EQ_CMA_RAD0__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD0__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD0__PRE 0x0 + +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__PRE 0x0 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_64 0x3418 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_128 0x1814 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_256 0x2CEE + +#define SCU_RAM_QAM_EQ_CMA_RAD1__A 0x831FAE +#define SCU_RAM_QAM_EQ_CMA_RAD1__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD1__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD1__PRE 0x0 + +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__PRE 0x0 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_64 0x314A +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_128 0x19C6 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_256 0x2F34 + +#define SCU_RAM_QAM_EQ_CMA_RAD2__A 0x831FAF +#define SCU_RAM_QAM_EQ_CMA_RAD2__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD2__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD2__PRE 0x0 + +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__PRE 0x0 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_64 0x2ED4 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_128 0x18FA +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_256 0x30FF + +#define SCU_RAM_QAM_EQ_CMA_RAD3__A 0x831FB0 +#define SCU_RAM_QAM_EQ_CMA_RAD3__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD3__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD3__PRE 0x0 + +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__PRE 0x0 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_64 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_128 0x1909 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_256 0x3283 + +#define SCU_RAM_QAM_EQ_CMA_RAD4__A 0x831FB1 +#define SCU_RAM_QAM_EQ_CMA_RAD4__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD4__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD4__PRE 0x0 + +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__PRE 0x0 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_64 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_128 0x1A00 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_256 0x353D + +#define SCU_RAM_QAM_EQ_CMA_RAD5__A 0x831FB2 +#define SCU_RAM_QAM_EQ_CMA_RAD5__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD5__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD5__PRE 0x0 + +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__PRE 0x0 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_64 0x3CF9 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_128 0x1C46 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_256 0x3C19 + +#define SCU_RAM_QAM_CTL_ENA__A 0x831FB3 +#define SCU_RAM_QAM_CTL_ENA__W 16 +#define SCU_RAM_QAM_CTL_ENA__M 0xFFFF +#define SCU_RAM_QAM_CTL_ENA__PRE 0x0 + +#define SCU_RAM_QAM_CTL_ENA_AMP__B 0 +#define SCU_RAM_QAM_CTL_ENA_AMP__W 1 +#define SCU_RAM_QAM_CTL_ENA_AMP__M 0x1 +#define SCU_RAM_QAM_CTL_ENA_AMP__PRE 0x0 + +#define SCU_RAM_QAM_CTL_ENA_ACQ__B 1 +#define SCU_RAM_QAM_CTL_ENA_ACQ__W 1 +#define SCU_RAM_QAM_CTL_ENA_ACQ__M 0x2 +#define SCU_RAM_QAM_CTL_ENA_ACQ__PRE 0x0 + +#define SCU_RAM_QAM_CTL_ENA_EQU__B 2 +#define SCU_RAM_QAM_CTL_ENA_EQU__W 1 +#define SCU_RAM_QAM_CTL_ENA_EQU__M 0x4 +#define SCU_RAM_QAM_CTL_ENA_EQU__PRE 0x0 + +#define SCU_RAM_QAM_CTL_ENA_SLC__B 3 +#define SCU_RAM_QAM_CTL_ENA_SLC__W 1 +#define SCU_RAM_QAM_CTL_ENA_SLC__M 0x8 +#define SCU_RAM_QAM_CTL_ENA_SLC__PRE 0x0 + +#define SCU_RAM_QAM_CTL_ENA_LC__B 4 +#define SCU_RAM_QAM_CTL_ENA_LC__W 1 +#define SCU_RAM_QAM_CTL_ENA_LC__M 0x10 +#define SCU_RAM_QAM_CTL_ENA_LC__PRE 0x0 + +#define SCU_RAM_QAM_CTL_ENA_AGC__B 5 +#define SCU_RAM_QAM_CTL_ENA_AGC__W 1 +#define SCU_RAM_QAM_CTL_ENA_AGC__M 0x20 +#define SCU_RAM_QAM_CTL_ENA_AGC__PRE 0x0 + +#define SCU_RAM_QAM_CTL_ENA_FEC__B 6 +#define SCU_RAM_QAM_CTL_ENA_FEC__W 1 +#define SCU_RAM_QAM_CTL_ENA_FEC__M 0x40 +#define SCU_RAM_QAM_CTL_ENA_FEC__PRE 0x0 + +#define SCU_RAM_QAM_CTL_ENA_AXIS__B 7 +#define SCU_RAM_QAM_CTL_ENA_AXIS__W 1 +#define SCU_RAM_QAM_CTL_ENA_AXIS__M 0x80 +#define SCU_RAM_QAM_CTL_ENA_AXIS__PRE 0x0 + +#define SCU_RAM_QAM_CTL_ENA_FMHUM__B 8 +#define SCU_RAM_QAM_CTL_ENA_FMHUM__W 1 +#define SCU_RAM_QAM_CTL_ENA_FMHUM__M 0x100 +#define SCU_RAM_QAM_CTL_ENA_FMHUM__PRE 0x0 + +#define SCU_RAM_QAM_CTL_ENA_EQTIME__B 9 +#define SCU_RAM_QAM_CTL_ENA_EQTIME__W 1 +#define SCU_RAM_QAM_CTL_ENA_EQTIME__M 0x200 +#define SCU_RAM_QAM_CTL_ENA_EQTIME__PRE 0x0 + +#define SCU_RAM_QAM_CTL_ENA_EXTLCK__B 10 +#define SCU_RAM_QAM_CTL_ENA_EXTLCK__W 1 +#define SCU_RAM_QAM_CTL_ENA_EXTLCK__M 0x400 +#define SCU_RAM_QAM_CTL_ENA_EXTLCK__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_1__A 0x831FB4 +#define SCU_RAM_QAM_WR_RSV_1__W 16 +#define SCU_RAM_QAM_WR_RSV_1__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_1__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_1_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_1_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_1_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_1_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_2__A 0x831FB5 +#define SCU_RAM_QAM_WR_RSV_2__W 16 +#define SCU_RAM_QAM_WR_RSV_2__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_2__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_2_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_2_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_2_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_2_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_3__A 0x831FB6 +#define SCU_RAM_QAM_WR_RSV_3__W 16 +#define SCU_RAM_QAM_WR_RSV_3__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_3__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_3_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_3_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_3_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_3_BIT__PRE 0x0 + +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__A 0x831FB7 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__W 3 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__M 0x7 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__PRE 0x0 + +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__B 0 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__W 3 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__M 0x7 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__PRE 0x0 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_UNKNOWN 0x0 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_16 0x3 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_32 0x4 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_64 0x5 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_128 0x6 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_256 0x7 + +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__A 0x831FB8 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__W 8 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__M 0xFF +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__PRE 0x0 + +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__B 0 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__W 8 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__M 0xFF +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__PRE 0x0 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J1 0x0 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J1_V2 0x1 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J2 0x2 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I64_J2 0x3 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J3 0x4 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I32_J4 0x5 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J4 0x6 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I16_J8 0x7 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J5 0x8 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I8_J16 0x9 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J6 0xA +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J7 0xC +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J8 0xE +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I12_J17 0x10 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I5_J4 0x11 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_UNKNOWN 0xFE + +#define SCU_RAM_QAM_RD_RSV_4__A 0x831FB9 +#define SCU_RAM_QAM_RD_RSV_4__W 16 +#define SCU_RAM_QAM_RD_RSV_4__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_4__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_4_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_4_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_4_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_4_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LOCKED__A 0x831FBA +#define SCU_RAM_QAM_LOCKED__W 16 +#define SCU_RAM_QAM_LOCKED__M 0xFFFF +#define SCU_RAM_QAM_LOCKED__PRE 0x0 + +#define SCU_RAM_QAM_LOCKED_INTLEVEL__B 0 +#define SCU_RAM_QAM_LOCKED_INTLEVEL__W 8 +#define SCU_RAM_QAM_LOCKED_INTLEVEL__M 0xFF +#define SCU_RAM_QAM_LOCKED_INTLEVEL__PRE 0x0 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_NOT_LOCKED 0x0 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_AMP_OK 0x1 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_RATE_OK 0x2 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_FREQ_OK 0x3 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_UPRIGHT_OK 0x4 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_PHNOISE_OK 0x5 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_TRACK_OK 0x6 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_IMPNOISE_OK 0x7 + +#define SCU_RAM_QAM_LOCKED_LOCKED__B 8 +#define SCU_RAM_QAM_LOCKED_LOCKED__W 8 +#define SCU_RAM_QAM_LOCKED_LOCKED__M 0xFF00 +#define SCU_RAM_QAM_LOCKED_LOCKED__PRE 0x0 +#define SCU_RAM_QAM_LOCKED_LOCKED_NOT_LOCKED 0x0 +#define SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED 0x4000 +#define SCU_RAM_QAM_LOCKED_LOCKED_LOCKED 0x8000 +#define SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK 0xC000 + +#define SCU_RAM_QAM_EVENTS_OCC_HI__A 0x831FBB +#define SCU_RAM_QAM_EVENTS_OCC_HI__W 16 +#define SCU_RAM_QAM_EVENTS_OCC_HI__M 0xFFFF +#define SCU_RAM_QAM_EVENTS_OCC_HI__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__B 0 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__M 0x1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__B 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__M 0x2 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__B 2 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__M 0x4 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__B 3 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__M 0x8 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__B 4 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__M 0x10 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__B 5 +#define SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__M 0x20 +#define SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__B 6 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__M 0x40 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__B 7 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__M 0x80 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__B 8 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__M 0x100 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__B 9 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__M 0x200 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__B 10 +#define SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__M 0x400 +#define SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__B 11 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__M 0x800 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_RSV__B 12 +#define SCU_RAM_QAM_EVENTS_OCC_HI_RSV__W 4 +#define SCU_RAM_QAM_EVENTS_OCC_HI_RSV__M 0xF000 +#define SCU_RAM_QAM_EVENTS_OCC_HI_RSV__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO__A 0x831FBC +#define SCU_RAM_QAM_EVENTS_OCC_LO__W 16 +#define SCU_RAM_QAM_EVENTS_OCC_LO__M 0xFFFF +#define SCU_RAM_QAM_EVENTS_OCC_LO__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__B 0 +#define SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__M 0x1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__B 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__M 0x2 +#define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__B 2 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__M 0x4 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_POWER__B 3 +#define SCU_RAM_QAM_EVENTS_OCC_LO_POWER__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_POWER__M 0x8 +#define SCU_RAM_QAM_EVENTS_OCC_LO_POWER__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__B 4 +#define SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__M 0x10 +#define SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_MER__B 5 +#define SCU_RAM_QAM_EVENTS_OCC_LO_MER__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_MER__M 0x20 +#define SCU_RAM_QAM_EVENTS_OCC_LO_MER__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__B 6 +#define SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__M 0x40 +#define SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__B 7 +#define SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__M 0x80 +#define SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_SER__B 8 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SER__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SER__M 0x100 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SER__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__B 9 +#define SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__M 0x200 +#define SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__B 10 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__M 0x400 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__B 11 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__M 0x800 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__B 12 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__M 0x1000 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__B 13 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__M 0x2000 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__B 14 +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__M 0x4000 +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__B 15 +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__M 0x8000 +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_SCHED_HI__A 0x831FBD +#define SCU_RAM_QAM_EVENTS_SCHED_HI__W 16 +#define SCU_RAM_QAM_EVENTS_SCHED_HI__M 0xFFFF +#define SCU_RAM_QAM_EVENTS_SCHED_HI__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__B 0 +#define SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__W 16 +#define SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__M 0xFFFF +#define SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_SCHED_LO__A 0x831FBE +#define SCU_RAM_QAM_EVENTS_SCHED_LO__W 16 +#define SCU_RAM_QAM_EVENTS_SCHED_LO__M 0xFFFF +#define SCU_RAM_QAM_EVENTS_SCHED_LO__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__B 0 +#define SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__W 16 +#define SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__M 0xFFFF +#define SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__PRE 0x0 + +#define SCU_RAM_QAM_TASKLETS_SCHED__A 0x831FBF +#define SCU_RAM_QAM_TASKLETS_SCHED__W 16 +#define SCU_RAM_QAM_TASKLETS_SCHED__M 0xFFFF +#define SCU_RAM_QAM_TASKLETS_SCHED__PRE 0x0 + +#define SCU_RAM_QAM_TASKLETS_SCHED_BIT__B 0 +#define SCU_RAM_QAM_TASKLETS_SCHED_BIT__W 16 +#define SCU_RAM_QAM_TASKLETS_SCHED_BIT__M 0xFFFF +#define SCU_RAM_QAM_TASKLETS_SCHED_BIT__PRE 0x0 + +#define SCU_RAM_QAM_TASKLETS_RUN__A 0x831FC0 +#define SCU_RAM_QAM_TASKLETS_RUN__W 16 +#define SCU_RAM_QAM_TASKLETS_RUN__M 0xFFFF +#define SCU_RAM_QAM_TASKLETS_RUN__PRE 0x0 + +#define SCU_RAM_QAM_TASKLETS_RUN_BIT__B 0 +#define SCU_RAM_QAM_TASKLETS_RUN_BIT__W 16 +#define SCU_RAM_QAM_TASKLETS_RUN_BIT__M 0xFFFF +#define SCU_RAM_QAM_TASKLETS_RUN_BIT__PRE 0x0 + +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__A 0x831FC1 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__W 16 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__M 0xFFFF +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__PRE 0x0 + +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__B 0 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__W 16 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__M 0xFFFF +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__PRE 0x0 + +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__A 0x831FC2 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__W 16 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__M 0xFFFF +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__PRE 0x0 + +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__B 0 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__W 16 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__M 0xFFFF +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_5__A 0x831FC3 +#define SCU_RAM_QAM_RD_RSV_5__W 16 +#define SCU_RAM_QAM_RD_RSV_5__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_5__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_5_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_5_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_5_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_5_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_6__A 0x831FC4 +#define SCU_RAM_QAM_RD_RSV_6__W 16 +#define SCU_RAM_QAM_RD_RSV_6__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_6__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_6_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_6_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_6_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_6_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_7__A 0x831FC5 +#define SCU_RAM_QAM_RD_RSV_7__W 16 +#define SCU_RAM_QAM_RD_RSV_7__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_7__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_7_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_7_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_7_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_7_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_8__A 0x831FC6 +#define SCU_RAM_QAM_RD_RSV_8__W 16 +#define SCU_RAM_QAM_RD_RSV_8__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_8__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_8_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_8_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_8_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_8_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_9__A 0x831FC7 +#define SCU_RAM_QAM_RD_RSV_9__W 16 +#define SCU_RAM_QAM_RD_RSV_9__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_9__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_9_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_9_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_9_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_9_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_10__A 0x831FC8 +#define SCU_RAM_QAM_RD_RSV_10__W 16 +#define SCU_RAM_QAM_RD_RSV_10__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_10__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_10_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_10_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_10_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_10_BIT__PRE 0x0 + +#define SCU_RAM_QAM_AGC_TPOW_OFFS__A 0x831FC9 +#define SCU_RAM_QAM_AGC_TPOW_OFFS__W 16 +#define SCU_RAM_QAM_AGC_TPOW_OFFS__M 0xFFFF +#define SCU_RAM_QAM_AGC_TPOW_OFFS__PRE 0x0 + +#define SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__B 0 +#define SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__W 16 +#define SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__M 0xFFFF +#define SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_STATE__A 0x831FCA +#define SCU_RAM_QAM_FSM_STATE__W 4 +#define SCU_RAM_QAM_FSM_STATE__M 0xF +#define SCU_RAM_QAM_FSM_STATE__PRE 0x0 + +#define SCU_RAM_QAM_FSM_STATE_BIT__B 0 +#define SCU_RAM_QAM_FSM_STATE_BIT__W 4 +#define SCU_RAM_QAM_FSM_STATE_BIT__M 0xF +#define SCU_RAM_QAM_FSM_STATE_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_AMP 0x0 +#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_RATE 0x1 +#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_FREQ 0x2 +#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_UPRIGHT 0x3 +#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_PHASE 0x4 +#define SCU_RAM_QAM_FSM_STATE_BIT_TRACKING_PHNOISE 0x5 +#define SCU_RAM_QAM_FSM_STATE_BIT_TRACKING 0x6 +#define SCU_RAM_QAM_FSM_STATE_BIT_TRACKING_BURST 0x7 + +#define SCU_RAM_QAM_FSM_STATE_NEW__A 0x831FCB +#define SCU_RAM_QAM_FSM_STATE_NEW__W 4 +#define SCU_RAM_QAM_FSM_STATE_NEW__M 0xF +#define SCU_RAM_QAM_FSM_STATE_NEW__PRE 0x0 + +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT__B 0 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT__W 4 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT__M 0xF +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_AMP 0x0 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_RATE 0x1 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_FREQ 0x2 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_UPRIGHT 0x3 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_PHASE 0x4 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_TRACKING_PHNOISE 0x5 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_TRACKING 0x6 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_TRACKING_BURST 0x7 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS__A 0x831FCC +#define SCU_RAM_QAM_FSM_LOCK_FLAGS__W 9 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS__M 0x1FF +#define SCU_RAM_QAM_FSM_LOCK_FLAGS__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__B 0 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__M 0x1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__B 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__M 0x2 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__B 2 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__M 0x4 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__B 3 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__M 0x8 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__B 4 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__M 0x10 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__B 5 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__M 0x20 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__B 6 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__M 0x40 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__B 7 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__M 0x80 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__B 8 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__M 0x100 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__PRE 0x0 + +#define SCU_RAM_QAM_FSM_RATE_VARIATION__A 0x831FCD +#define SCU_RAM_QAM_FSM_RATE_VARIATION__W 16 +#define SCU_RAM_QAM_FSM_RATE_VARIATION__M 0xFFFF +#define SCU_RAM_QAM_FSM_RATE_VARIATION__PRE 0x0 + +#define SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__B 0 +#define SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__W 16 +#define SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_FREQ_VARIATION__A 0x831FCE +#define SCU_RAM_QAM_FSM_FREQ_VARIATION__W 16 +#define SCU_RAM_QAM_FSM_FREQ_VARIATION__M 0xFFFF +#define SCU_RAM_QAM_FSM_FREQ_VARIATION__PRE 0x0 + +#define SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__B 0 +#define SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__W 16 +#define SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__PRE 0x0 + +#define SCU_RAM_QAM_ERR_STATE__A 0x831FCF +#define SCU_RAM_QAM_ERR_STATE__W 4 +#define SCU_RAM_QAM_ERR_STATE__M 0xF +#define SCU_RAM_QAM_ERR_STATE__PRE 0x0 + +#define SCU_RAM_QAM_ERR_STATE_BIT__B 0 +#define SCU_RAM_QAM_ERR_STATE_BIT__W 4 +#define SCU_RAM_QAM_ERR_STATE_BIT__M 0xF +#define SCU_RAM_QAM_ERR_STATE_BIT__PRE 0x0 +#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_AMP 0x0 +#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_RATE 0x1 +#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_FREQ 0x2 +#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_UPRIGHT 0x3 +#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_PHASE 0x4 +#define SCU_RAM_QAM_ERR_STATE_BIT_TRACKING_PHNOISE 0x5 +#define SCU_RAM_QAM_ERR_STATE_BIT_TRACKING 0x6 +#define SCU_RAM_QAM_ERR_STATE_BIT_TRACKING_BURST 0x7 + +#define SCU_RAM_QAM_ERR_LOCK_FLAGS__A 0x831FD0 +#define SCU_RAM_QAM_ERR_LOCK_FLAGS__W 9 +#define SCU_RAM_QAM_ERR_LOCK_FLAGS__M 0x1FF +#define SCU_RAM_QAM_ERR_LOCK_FLAGS__PRE 0x0 + +#define SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__B 0 +#define SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__W 1 +#define SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__M 0x1 +#define SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__PRE 0x0 + +#define SCU_RAM_QAM_EQ_LOCK__A 0x831FD1 +#define SCU_RAM_QAM_EQ_LOCK__W 1 +#define SCU_RAM_QAM_EQ_LOCK__M 0x1 +#define SCU_RAM_QAM_EQ_LOCK__PRE 0x0 + +#define SCU_RAM_QAM_EQ_LOCK_BIT__B 0 +#define SCU_RAM_QAM_EQ_LOCK_BIT__W 1 +#define SCU_RAM_QAM_EQ_LOCK_BIT__M 0x1 +#define SCU_RAM_QAM_EQ_LOCK_BIT__PRE 0x0 + +#define SCU_RAM_QAM_EQ_STATE__A 0x831FD2 +#define SCU_RAM_QAM_EQ_STATE__W 16 +#define SCU_RAM_QAM_EQ_STATE__M 0xFFFF +#define SCU_RAM_QAM_EQ_STATE__PRE 0x0 + +#define SCU_RAM_QAM_EQ_STATE_BIT__B 0 +#define SCU_RAM_QAM_EQ_STATE_BIT__W 16 +#define SCU_RAM_QAM_EQ_STATE_BIT__M 0xFFFF +#define SCU_RAM_QAM_EQ_STATE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_0__A 0x831FD3 +#define SCU_RAM_QAM_RD_RSV_0__W 16 +#define SCU_RAM_QAM_RD_RSV_0__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_0__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_0_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_0_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_0_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_0_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_1__A 0x831FD4 +#define SCU_RAM_QAM_RD_RSV_1__W 16 +#define SCU_RAM_QAM_RD_RSV_1__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_1__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_1_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_1_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_1_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_1_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_2__A 0x831FD5 +#define SCU_RAM_QAM_RD_RSV_2__W 16 +#define SCU_RAM_QAM_RD_RSV_2__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_2__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_2_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_2_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_2_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_2_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_3__A 0x831FD6 +#define SCU_RAM_QAM_RD_RSV_3__W 16 +#define SCU_RAM_QAM_RD_RSV_3__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_3__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_3_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_3_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_3_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_3_BIT__PRE 0x0 + +#define SCU_RAM_VSB_CTL_MODE__A 0x831FD7 +#define SCU_RAM_VSB_CTL_MODE__W 2 +#define SCU_RAM_VSB_CTL_MODE__M 0x3 +#define SCU_RAM_VSB_CTL_MODE__PRE 0x0 + +#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_AGC__B 0 +#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_AGC__W 1 +#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_AGC__M 0x1 +#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_AGC__PRE 0x0 +#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_AGC_OFF 0x0 +#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_AGC_ON 0x1 + +#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON__B 1 +#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON__W 1 +#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON__M 0x2 +#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON__PRE 0x0 +#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON_OFF 0x0 +#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON_ON 0x2 + + +#define SCU_RAM_VSB_NOTCH_THRESHOLD__A 0x831FD8 +#define SCU_RAM_VSB_NOTCH_THRESHOLD__W 16 +#define SCU_RAM_VSB_NOTCH_THRESHOLD__M 0xFFFF +#define SCU_RAM_VSB_NOTCH_THRESHOLD__PRE 0x0 + +#define SCU_RAM_VSB_RSV_0__A 0x831FD9 +#define SCU_RAM_VSB_RSV_0__W 16 +#define SCU_RAM_VSB_RSV_0__M 0xFFFF +#define SCU_RAM_VSB_RSV_0__PRE 0x0 + +#define SCU_RAM_VSB_RSV_1__A 0x831FDA +#define SCU_RAM_VSB_RSV_1__W 16 +#define SCU_RAM_VSB_RSV_1__M 0xFFFF +#define SCU_RAM_VSB_RSV_1__PRE 0x0 + +#define SCU_RAM_VSB_RSV_2__A 0x831FDB +#define SCU_RAM_VSB_RSV_2__W 16 +#define SCU_RAM_VSB_RSV_2__M 0xFFFF +#define SCU_RAM_VSB_RSV_2__PRE 0x0 + +#define SCU_RAM_VSB_RSV_3__A 0x831FDC +#define SCU_RAM_VSB_RSV_3__W 16 +#define SCU_RAM_VSB_RSV_3__M 0xFFFF +#define SCU_RAM_VSB_RSV_3__PRE 0x0 + +#define SCU_RAM_VSB_RSV_4__A 0x831FDD +#define SCU_RAM_VSB_RSV_4__W 16 +#define SCU_RAM_VSB_RSV_4__M 0xFFFF +#define SCU_RAM_VSB_RSV_4__PRE 0x0 + +#define SCU_RAM_VSB_RSV_5__A 0x831FDE +#define SCU_RAM_VSB_RSV_5__W 16 +#define SCU_RAM_VSB_RSV_5__M 0xFFFF +#define SCU_RAM_VSB_RSV_5__PRE 0x0 + +#define SCU_RAM_VSB_RSV_6__A 0x831FDF +#define SCU_RAM_VSB_RSV_6__W 16 +#define SCU_RAM_VSB_RSV_6__M 0xFFFF +#define SCU_RAM_VSB_RSV_6__PRE 0x0 + +#define SCU_RAM_VSB_RSV_7__A 0x831FE0 +#define SCU_RAM_VSB_RSV_7__W 16 +#define SCU_RAM_VSB_RSV_7__M 0xFFFF +#define SCU_RAM_VSB_RSV_7__PRE 0x0 + +#define SCU_RAM_VSB_RSV_8__A 0x831FE1 +#define SCU_RAM_VSB_RSV_8__W 16 +#define SCU_RAM_VSB_RSV_8__M 0xFFFF +#define SCU_RAM_VSB_RSV_8__PRE 0x0 + +#define SCU_RAM_VSB_RSV_9__A 0x831FE2 +#define SCU_RAM_VSB_RSV_9__W 16 +#define SCU_RAM_VSB_RSV_9__M 0xFFFF +#define SCU_RAM_VSB_RSV_9__PRE 0x0 + +#define SCU_RAM_VSB_RSV_10__A 0x831FE3 +#define SCU_RAM_VSB_RSV_10__W 16 +#define SCU_RAM_VSB_RSV_10__M 0xFFFF +#define SCU_RAM_VSB_RSV_10__PRE 0x0 + +#define SCU_RAM_VSB_RSV_11__A 0x831FE4 +#define SCU_RAM_VSB_RSV_11__W 16 +#define SCU_RAM_VSB_RSV_11__M 0xFFFF +#define SCU_RAM_VSB_RSV_11__PRE 0x0 + +#define SCU_RAM_VSB_RSV_12__A 0x831FE5 +#define SCU_RAM_VSB_RSV_12__W 16 +#define SCU_RAM_VSB_RSV_12__M 0xFFFF +#define SCU_RAM_VSB_RSV_12__PRE 0x0 + +#define SCU_RAM_VSB_RSV_13__A 0x831FE6 +#define SCU_RAM_VSB_RSV_13__W 16 +#define SCU_RAM_VSB_RSV_13__M 0xFFFF +#define SCU_RAM_VSB_RSV_13__PRE 0x0 + +#define SCU_RAM_VSB_AGC_POW_TGT__A 0x831FE7 +#define SCU_RAM_VSB_AGC_POW_TGT__W 15 +#define SCU_RAM_VSB_AGC_POW_TGT__M 0x7FFF +#define SCU_RAM_VSB_AGC_POW_TGT__PRE 0x0 + +#define SCU_RAM_VSB_OUTER_LOOP_CYCLE__A 0x831FE8 +#define SCU_RAM_VSB_OUTER_LOOP_CYCLE__W 8 +#define SCU_RAM_VSB_OUTER_LOOP_CYCLE__M 0xFF +#define SCU_RAM_VSB_OUTER_LOOP_CYCLE__PRE 0x0 + +#define SCU_RAM_VSB_FIELD_NUMBER__A 0x831FE9 +#define SCU_RAM_VSB_FIELD_NUMBER__W 9 +#define SCU_RAM_VSB_FIELD_NUMBER__M 0x1FF +#define SCU_RAM_VSB_FIELD_NUMBER__PRE 0x0 + +#define SCU_RAM_VSB_SEGMENT_NUMBER__A 0x831FEA +#define SCU_RAM_VSB_SEGMENT_NUMBER__W 10 +#define SCU_RAM_VSB_SEGMENT_NUMBER__M 0x3FF +#define SCU_RAM_VSB_SEGMENT_NUMBER__PRE 0x0 + +#define SCU_RAM_DRIVER_VER_HI__A 0x831FEB +#define SCU_RAM_DRIVER_VER_HI__W 16 +#define SCU_RAM_DRIVER_VER_HI__M 0xFFFF +#define SCU_RAM_DRIVER_VER_HI__PRE 0x0 + +#define SCU_RAM_DRIVER_VER_LO__A 0x831FEC +#define SCU_RAM_DRIVER_VER_LO__W 16 +#define SCU_RAM_DRIVER_VER_LO__M 0xFFFF +#define SCU_RAM_DRIVER_VER_LO__PRE 0x0 + +#define SCU_RAM_PARAM_15__A 0x831FED +#define SCU_RAM_PARAM_15__W 16 +#define SCU_RAM_PARAM_15__M 0xFFFF +#define SCU_RAM_PARAM_15__PRE 0x0 + +#define SCU_RAM_PARAM_14__A 0x831FEE +#define SCU_RAM_PARAM_14__W 16 +#define SCU_RAM_PARAM_14__M 0xFFFF +#define SCU_RAM_PARAM_14__PRE 0x0 + +#define SCU_RAM_PARAM_13__A 0x831FEF +#define SCU_RAM_PARAM_13__W 16 +#define SCU_RAM_PARAM_13__M 0xFFFF +#define SCU_RAM_PARAM_13__PRE 0x0 + +#define SCU_RAM_PARAM_12__A 0x831FF0 +#define SCU_RAM_PARAM_12__W 16 +#define SCU_RAM_PARAM_12__M 0xFFFF +#define SCU_RAM_PARAM_12__PRE 0x0 + +#define SCU_RAM_PARAM_11__A 0x831FF1 +#define SCU_RAM_PARAM_11__W 16 +#define SCU_RAM_PARAM_11__M 0xFFFF +#define SCU_RAM_PARAM_11__PRE 0x0 + +#define SCU_RAM_PARAM_10__A 0x831FF2 +#define SCU_RAM_PARAM_10__W 16 +#define SCU_RAM_PARAM_10__M 0xFFFF +#define SCU_RAM_PARAM_10__PRE 0x0 + +#define SCU_RAM_PARAM_9__A 0x831FF3 +#define SCU_RAM_PARAM_9__W 16 +#define SCU_RAM_PARAM_9__M 0xFFFF +#define SCU_RAM_PARAM_9__PRE 0x0 + +#define SCU_RAM_PARAM_8__A 0x831FF4 +#define SCU_RAM_PARAM_8__W 16 +#define SCU_RAM_PARAM_8__M 0xFFFF +#define SCU_RAM_PARAM_8__PRE 0x0 + +#define SCU_RAM_PARAM_7__A 0x831FF5 +#define SCU_RAM_PARAM_7__W 16 +#define SCU_RAM_PARAM_7__M 0xFFFF +#define SCU_RAM_PARAM_7__PRE 0x0 + +#define SCU_RAM_PARAM_6__A 0x831FF6 +#define SCU_RAM_PARAM_6__W 16 +#define SCU_RAM_PARAM_6__M 0xFFFF +#define SCU_RAM_PARAM_6__PRE 0x0 + +#define SCU_RAM_PARAM_5__A 0x831FF7 +#define SCU_RAM_PARAM_5__W 16 +#define SCU_RAM_PARAM_5__M 0xFFFF +#define SCU_RAM_PARAM_5__PRE 0x0 + +#define SCU_RAM_PARAM_4__A 0x831FF8 +#define SCU_RAM_PARAM_4__W 16 +#define SCU_RAM_PARAM_4__M 0xFFFF +#define SCU_RAM_PARAM_4__PRE 0x0 + +#define SCU_RAM_PARAM_3__A 0x831FF9 +#define SCU_RAM_PARAM_3__W 16 +#define SCU_RAM_PARAM_3__M 0xFFFF +#define SCU_RAM_PARAM_3__PRE 0x0 + +#define SCU_RAM_PARAM_2__A 0x831FFA +#define SCU_RAM_PARAM_2__W 16 +#define SCU_RAM_PARAM_2__M 0xFFFF +#define SCU_RAM_PARAM_2__PRE 0x0 + +#define SCU_RAM_PARAM_1__A 0x831FFB +#define SCU_RAM_PARAM_1__W 16 +#define SCU_RAM_PARAM_1__M 0xFFFF +#define SCU_RAM_PARAM_1__PRE 0x0 +#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NOT_LOCKED 0x0 +#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_DEMOD_LOCKED 0x4000 +#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_LOCKED 0x8000 +#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NEVER_LOCK 0xC000 + + +#define SCU_RAM_PARAM_0__A 0x831FFC +#define SCU_RAM_PARAM_0__W 16 +#define SCU_RAM_PARAM_0__M 0xFFFF +#define SCU_RAM_PARAM_0__PRE 0x0 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_MN_STANDARD 0x2 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_B_STANDARD 0x103 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_G_STANDARD 0x3 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_DK_STANDARD 0x4 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_L_STANDARD 0x9 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_LP_STANDARD 0x109 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_I_STANDARD 0xA +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_FM_STANDARD 0x40 +#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_A 0x0 +#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_B 0x1 +#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_C 0x2 +#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_D 0x3 +#define SCU_RAM_PARAM_0_RESULT_OK 0x0 +#define SCU_RAM_PARAM_0_RESULT_UNKCMD 0xFFFF +#define SCU_RAM_PARAM_0_RESULT_UNKSTD 0xFFFE +#define SCU_RAM_PARAM_0_RESULT_INVPAR 0xFFFD +#define SCU_RAM_PARAM_0_RESULT_SIZE 0xFFFC + + +#define SCU_RAM_COMMAND__A 0x831FFD +#define SCU_RAM_COMMAND__W 16 +#define SCU_RAM_COMMAND__M 0xFFFF +#define SCU_RAM_COMMAND__PRE 0x0 +#define SCU_RAM_COMMAND_CMD_DEMOD_RESET 0x1 +#define SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV 0x2 +#define SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM 0x3 +#define SCU_RAM_COMMAND_CMD_DEMOD_START 0x4 +#define SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK 0x5 +#define SCU_RAM_COMMAND_CMD_DEMOD_GET_PARAM 0x6 +#define SCU_RAM_COMMAND_CMD_DEMOD_HOLD 0x7 +#define SCU_RAM_COMMAND_CMD_DEMOD_RESUME 0x8 +#define SCU_RAM_COMMAND_CMD_DEMOD_STOP 0x9 +#define SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_ACTIVATE 0x80 +#define SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_INACTIVATE 0x81 +#define SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_SIGNAL 0x82 +#define SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_MONITOR 0x83 +#define SCU_RAM_COMMAND_CMD_STD_QAM_TSK_ENABLE 0x84 +#define SCU_RAM_COMMAND_CMD_STD_QAM_FSM_SET_STATE 0x85 +#define SCU_RAM_COMMAND_CMD_DEBUG_GET_IRQ_REGS 0x80 +#define SCU_RAM_COMMAND_CMD_DEBUG_HTOL 0x81 +#define SCU_RAM_COMMAND_CMD_DEBUG_GET_STACK_POINTER 0x82 +#define SCU_RAM_COMMAND_CMD_DEBUG_START_STACK_CHECK 0x83 +#define SCU_RAM_COMMAND_CMD_DEBUG_STOP_STACK_CHECK 0x84 +#define SCU_RAM_COMMAND_CMD_ADMIN_NOP 0xFF +#define SCU_RAM_COMMAND_CMD_ADMIN_GET_VERSION 0xFE +#define SCU_RAM_COMMAND_CMD_ADMIN_GET_JTAG_VERSION 0xFD +#define SCU_RAM_COMMAND_CMD_AUX_SCU_ATOMIC_ACCESS 0xC0 + +#define SCU_RAM_COMMAND_STANDARD__B 8 +#define SCU_RAM_COMMAND_STANDARD__W 8 +#define SCU_RAM_COMMAND_STANDARD__M 0xFF00 +#define SCU_RAM_COMMAND_STANDARD__PRE 0x0 +#define SCU_RAM_COMMAND_STANDARD_ATV 0x100 +#define SCU_RAM_COMMAND_STANDARD_QAM 0x200 +#define SCU_RAM_COMMAND_STANDARD_VSB 0x300 +#define SCU_RAM_COMMAND_STANDARD_OFDM 0x400 +#define SCU_RAM_COMMAND_STANDARD_OOB 0x8000 +#define SCU_RAM_COMMAND_STANDARD_TOP 0xFF00 + +#define SCU_RAM_VERSION_HI__A 0x831FFE +#define SCU_RAM_VERSION_HI__W 16 +#define SCU_RAM_VERSION_HI__M 0xFFFF +#define SCU_RAM_VERSION_HI__PRE 0x0 + +#define SCU_RAM_VERSION_HI_VER_MAJOR_N3__B 12 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N3__W 4 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N3__M 0xF000 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N3__PRE 0x0 + +#define SCU_RAM_VERSION_HI_VER_MAJOR_N2__B 8 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N2__W 4 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N2__M 0xF00 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N2__PRE 0x0 + +#define SCU_RAM_VERSION_HI_VER_MAJOR_N1__B 4 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N1__W 4 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N1__M 0xF0 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N1__PRE 0x0 + +#define SCU_RAM_VERSION_HI_VER_MINOR_N1__B 0 +#define SCU_RAM_VERSION_HI_VER_MINOR_N1__W 4 +#define SCU_RAM_VERSION_HI_VER_MINOR_N1__M 0xF +#define SCU_RAM_VERSION_HI_VER_MINOR_N1__PRE 0x0 + +#define SCU_RAM_VERSION_LO__A 0x831FFF +#define SCU_RAM_VERSION_LO__W 16 +#define SCU_RAM_VERSION_LO__M 0xFFFF +#define SCU_RAM_VERSION_LO__PRE 0x0 + +#define SCU_RAM_VERSION_LO_VER_PATCH_N4__B 12 +#define SCU_RAM_VERSION_LO_VER_PATCH_N4__W 4 +#define SCU_RAM_VERSION_LO_VER_PATCH_N4__M 0xF000 +#define SCU_RAM_VERSION_LO_VER_PATCH_N4__PRE 0x0 + +#define SCU_RAM_VERSION_LO_VER_PATCH_N3__B 8 +#define SCU_RAM_VERSION_LO_VER_PATCH_N3__W 4 +#define SCU_RAM_VERSION_LO_VER_PATCH_N3__M 0xF00 +#define SCU_RAM_VERSION_LO_VER_PATCH_N3__PRE 0x0 + +#define SCU_RAM_VERSION_LO_VER_PATCH_N2__B 4 +#define SCU_RAM_VERSION_LO_VER_PATCH_N2__W 4 +#define SCU_RAM_VERSION_LO_VER_PATCH_N2__M 0xF0 +#define SCU_RAM_VERSION_LO_VER_PATCH_N2__PRE 0x0 + +#define SCU_RAM_VERSION_LO_VER_PATCH_N1__B 0 +#define SCU_RAM_VERSION_LO_VER_PATCH_N1__W 4 +#define SCU_RAM_VERSION_LO_VER_PATCH_N1__M 0xF +#define SCU_RAM_VERSION_LO_VER_PATCH_N1__PRE 0x0 + + + + + +#define SIO_COMM_EXEC__A 0x400000 +#define SIO_COMM_EXEC__W 2 +#define SIO_COMM_EXEC__M 0x3 +#define SIO_COMM_EXEC__PRE 0x0 +#define SIO_COMM_EXEC_STOP 0x0 +#define SIO_COMM_EXEC_ACTIVE 0x1 +#define SIO_COMM_EXEC_HOLD 0x2 + +#define SIO_COMM_STATE__A 0x400001 +#define SIO_COMM_STATE__W 16 +#define SIO_COMM_STATE__M 0xFFFF +#define SIO_COMM_STATE__PRE 0x0 +#define SIO_COMM_MB__A 0x400002 +#define SIO_COMM_MB__W 16 +#define SIO_COMM_MB__M 0xFFFF +#define SIO_COMM_MB__PRE 0x0 +#define SIO_COMM_INT_REQ__A 0x400003 +#define SIO_COMM_INT_REQ__W 16 +#define SIO_COMM_INT_REQ__M 0xFFFF +#define SIO_COMM_INT_REQ__PRE 0x0 + +#define SIO_COMM_INT_REQ_HI_REQ__B 0 +#define SIO_COMM_INT_REQ_HI_REQ__W 1 +#define SIO_COMM_INT_REQ_HI_REQ__M 0x1 +#define SIO_COMM_INT_REQ_HI_REQ__PRE 0x0 + +#define SIO_COMM_INT_REQ_SA_REQ__B 1 +#define SIO_COMM_INT_REQ_SA_REQ__W 1 +#define SIO_COMM_INT_REQ_SA_REQ__M 0x2 +#define SIO_COMM_INT_REQ_SA_REQ__PRE 0x0 + +#define SIO_COMM_INT_STA__A 0x400005 +#define SIO_COMM_INT_STA__W 16 +#define SIO_COMM_INT_STA__M 0xFFFF +#define SIO_COMM_INT_STA__PRE 0x0 +#define SIO_COMM_INT_MSK__A 0x400006 +#define SIO_COMM_INT_MSK__W 16 +#define SIO_COMM_INT_MSK__M 0xFFFF +#define SIO_COMM_INT_MSK__PRE 0x0 +#define SIO_COMM_INT_STM__A 0x400007 +#define SIO_COMM_INT_STM__W 16 +#define SIO_COMM_INT_STM__M 0xFFFF +#define SIO_COMM_INT_STM__PRE 0x0 + + + +#define SIO_TOP_COMM_EXEC__A 0x410000 +#define SIO_TOP_COMM_EXEC__W 2 +#define SIO_TOP_COMM_EXEC__M 0x3 +#define SIO_TOP_COMM_EXEC__PRE 0x0 +#define SIO_TOP_COMM_EXEC_STOP 0x0 +#define SIO_TOP_COMM_EXEC_ACTIVE 0x1 +#define SIO_TOP_COMM_EXEC_HOLD 0x2 + + +#define SIO_TOP_COMM_KEY__A 0x41000F +#define SIO_TOP_COMM_KEY__W 16 +#define SIO_TOP_COMM_KEY__M 0xFFFF +#define SIO_TOP_COMM_KEY__PRE 0x0 +#define SIO_TOP_COMM_KEY_KEY 0xFABA + + +#define SIO_TOP_JTAGID_LO__A 0x410012 +#define SIO_TOP_JTAGID_LO__W 16 +#define SIO_TOP_JTAGID_LO__M 0xFFFF +#define SIO_TOP_JTAGID_LO__PRE 0x0 + +#define SIO_TOP_JTAGID_HI__A 0x410013 +#define SIO_TOP_JTAGID_HI__W 16 +#define SIO_TOP_JTAGID_HI__M 0xFFFF +#define SIO_TOP_JTAGID_HI__PRE 0x0 + + + + +#define SIO_HI_RA_RAM_S0_FLG_SMM__A 0x420010 +#define SIO_HI_RA_RAM_S0_FLG_SMM__W 1 +#define SIO_HI_RA_RAM_S0_FLG_SMM__M 0x1 +#define SIO_HI_RA_RAM_S0_FLG_SMM__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_DEV_ID__A 0x420011 +#define SIO_HI_RA_RAM_S0_DEV_ID__W 7 +#define SIO_HI_RA_RAM_S0_DEV_ID__M 0x7F +#define SIO_HI_RA_RAM_S0_DEV_ID__PRE 0x52 + +#define SIO_HI_RA_RAM_S0_FLG_CRC__A 0x420012 +#define SIO_HI_RA_RAM_S0_FLG_CRC__W 1 +#define SIO_HI_RA_RAM_S0_FLG_CRC__M 0x1 +#define SIO_HI_RA_RAM_S0_FLG_CRC__PRE 0x0 +#define SIO_HI_RA_RAM_S0_FLG_ACC__A 0x420013 +#define SIO_HI_RA_RAM_S0_FLG_ACC__W 4 +#define SIO_HI_RA_RAM_S0_FLG_ACC__M 0xF +#define SIO_HI_RA_RAM_S0_FLG_ACC__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__B 0 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__W 2 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__M 0x3 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__B 2 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__W 1 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__M 0x4 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__B 3 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__W 1 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__M 0x8 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_STATE__A 0x420014 +#define SIO_HI_RA_RAM_S0_STATE__W 1 +#define SIO_HI_RA_RAM_S0_STATE__M 0x1 +#define SIO_HI_RA_RAM_S0_STATE__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__B 0 +#define SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__W 1 +#define SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__M 0x1 +#define SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_BLK_BNK__A 0x420015 +#define SIO_HI_RA_RAM_S0_BLK_BNK__W 12 +#define SIO_HI_RA_RAM_S0_BLK_BNK__M 0xFFF +#define SIO_HI_RA_RAM_S0_BLK_BNK__PRE 0x82 + +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__B 0 +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__W 6 +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__M 0x3F +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__PRE 0x2 + +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__B 6 +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__W 6 +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__PRE 0x80 + +#define SIO_HI_RA_RAM_S0_ADDR__A 0x420016 +#define SIO_HI_RA_RAM_S0_ADDR__W 16 +#define SIO_HI_RA_RAM_S0_ADDR__M 0xFFFF +#define SIO_HI_RA_RAM_S0_ADDR__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__B 0 +#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__W 16 +#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__M 0xFFFF +#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__PRE 0x0 + + +#define SIO_HI_RA_RAM_S0_CRC__A 0x420017 +#define SIO_HI_RA_RAM_S0_CRC__W 16 +#define SIO_HI_RA_RAM_S0_CRC__M 0xFFFF +#define SIO_HI_RA_RAM_S0_CRC__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_BUFFER__A 0x420018 +#define SIO_HI_RA_RAM_S0_BUFFER__W 16 +#define SIO_HI_RA_RAM_S0_BUFFER__M 0xFFFF +#define SIO_HI_RA_RAM_S0_BUFFER__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_RMWBUF__A 0x420019 +#define SIO_HI_RA_RAM_S0_RMWBUF__W 16 +#define SIO_HI_RA_RAM_S0_RMWBUF__M 0xFFFF +#define SIO_HI_RA_RAM_S0_RMWBUF__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_FLG_VB__A 0x42001A +#define SIO_HI_RA_RAM_S0_FLG_VB__W 1 +#define SIO_HI_RA_RAM_S0_FLG_VB__M 0x1 +#define SIO_HI_RA_RAM_S0_FLG_VB__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_TEMP0__A 0x42001B +#define SIO_HI_RA_RAM_S0_TEMP0__W 16 +#define SIO_HI_RA_RAM_S0_TEMP0__M 0xFFFF +#define SIO_HI_RA_RAM_S0_TEMP0__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_TEMP1__A 0x42001C +#define SIO_HI_RA_RAM_S0_TEMP1__W 16 +#define SIO_HI_RA_RAM_S0_TEMP1__M 0xFFFF +#define SIO_HI_RA_RAM_S0_TEMP1__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_OFFSET__A 0x42001D +#define SIO_HI_RA_RAM_S0_OFFSET__W 16 +#define SIO_HI_RA_RAM_S0_OFFSET__M 0xFFFF +#define SIO_HI_RA_RAM_S0_OFFSET__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_FLG_SMM__A 0x420020 +#define SIO_HI_RA_RAM_S1_FLG_SMM__W 1 +#define SIO_HI_RA_RAM_S1_FLG_SMM__M 0x1 +#define SIO_HI_RA_RAM_S1_FLG_SMM__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_DEV_ID__A 0x420021 +#define SIO_HI_RA_RAM_S1_DEV_ID__W 7 +#define SIO_HI_RA_RAM_S1_DEV_ID__M 0x7F +#define SIO_HI_RA_RAM_S1_DEV_ID__PRE 0x52 + +#define SIO_HI_RA_RAM_S1_FLG_CRC__A 0x420022 +#define SIO_HI_RA_RAM_S1_FLG_CRC__W 1 +#define SIO_HI_RA_RAM_S1_FLG_CRC__M 0x1 +#define SIO_HI_RA_RAM_S1_FLG_CRC__PRE 0x0 +#define SIO_HI_RA_RAM_S1_FLG_ACC__A 0x420023 +#define SIO_HI_RA_RAM_S1_FLG_ACC__W 4 +#define SIO_HI_RA_RAM_S1_FLG_ACC__M 0xF +#define SIO_HI_RA_RAM_S1_FLG_ACC__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__B 0 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__W 2 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__M 0x3 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__B 2 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__W 1 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__M 0x4 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__B 3 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__W 1 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__M 0x8 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_STATE__A 0x420024 +#define SIO_HI_RA_RAM_S1_STATE__W 1 +#define SIO_HI_RA_RAM_S1_STATE__M 0x1 +#define SIO_HI_RA_RAM_S1_STATE__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__B 0 +#define SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__W 1 +#define SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__M 0x1 +#define SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_BLK_BNK__A 0x420025 +#define SIO_HI_RA_RAM_S1_BLK_BNK__W 12 +#define SIO_HI_RA_RAM_S1_BLK_BNK__M 0xFFF +#define SIO_HI_RA_RAM_S1_BLK_BNK__PRE 0x82 + +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__B 0 +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__W 6 +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__M 0x3F +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__PRE 0x2 + +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__B 6 +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__W 6 +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__PRE 0x80 + +#define SIO_HI_RA_RAM_S1_ADDR__A 0x420026 +#define SIO_HI_RA_RAM_S1_ADDR__W 16 +#define SIO_HI_RA_RAM_S1_ADDR__M 0xFFFF +#define SIO_HI_RA_RAM_S1_ADDR__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__B 0 +#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__W 16 +#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__M 0xFFFF +#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__PRE 0x0 + + +#define SIO_HI_RA_RAM_S1_CRC__A 0x420027 +#define SIO_HI_RA_RAM_S1_CRC__W 16 +#define SIO_HI_RA_RAM_S1_CRC__M 0xFFFF +#define SIO_HI_RA_RAM_S1_CRC__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_BUFFER__A 0x420028 +#define SIO_HI_RA_RAM_S1_BUFFER__W 16 +#define SIO_HI_RA_RAM_S1_BUFFER__M 0xFFFF +#define SIO_HI_RA_RAM_S1_BUFFER__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_RMWBUF__A 0x420029 +#define SIO_HI_RA_RAM_S1_RMWBUF__W 16 +#define SIO_HI_RA_RAM_S1_RMWBUF__M 0xFFFF +#define SIO_HI_RA_RAM_S1_RMWBUF__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_FLG_VB__A 0x42002A +#define SIO_HI_RA_RAM_S1_FLG_VB__W 1 +#define SIO_HI_RA_RAM_S1_FLG_VB__M 0x1 +#define SIO_HI_RA_RAM_S1_FLG_VB__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_TEMP0__A 0x42002B +#define SIO_HI_RA_RAM_S1_TEMP0__W 16 +#define SIO_HI_RA_RAM_S1_TEMP0__M 0xFFFF +#define SIO_HI_RA_RAM_S1_TEMP0__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_TEMP1__A 0x42002C +#define SIO_HI_RA_RAM_S1_TEMP1__W 16 +#define SIO_HI_RA_RAM_S1_TEMP1__M 0xFFFF +#define SIO_HI_RA_RAM_S1_TEMP1__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_OFFSET__A 0x42002D +#define SIO_HI_RA_RAM_S1_OFFSET__W 16 +#define SIO_HI_RA_RAM_S1_OFFSET__M 0xFFFF +#define SIO_HI_RA_RAM_S1_OFFSET__PRE 0x0 +#define SIO_HI_RA_RAM_SEMA__A 0x420030 +#define SIO_HI_RA_RAM_SEMA__W 1 +#define SIO_HI_RA_RAM_SEMA__M 0x1 +#define SIO_HI_RA_RAM_SEMA__PRE 0x0 +#define SIO_HI_RA_RAM_SEMA_FREE 0x0 +#define SIO_HI_RA_RAM_SEMA_BUSY 0x1 + +#define SIO_HI_RA_RAM_RES__A 0x420031 +#define SIO_HI_RA_RAM_RES__W 3 +#define SIO_HI_RA_RAM_RES__M 0x7 +#define SIO_HI_RA_RAM_RES__PRE 0x0 +#define SIO_HI_RA_RAM_RES_OK 0x0 +#define SIO_HI_RA_RAM_RES_ERROR 0x1 +#define SIO_HI_RA_RAM_RES_I2C_START_FOUND 0x1 +#define SIO_HI_RA_RAM_RES_I2C_STOP_FOUND 0x2 +#define SIO_HI_RA_RAM_RES_I2C_ARB_LOST 0x3 +#define SIO_HI_RA_RAM_RES_I2C_ERROR 0x4 + +#define SIO_HI_RA_RAM_CMD__A 0x420032 +#define SIO_HI_RA_RAM_CMD__W 4 +#define SIO_HI_RA_RAM_CMD__M 0xF +#define SIO_HI_RA_RAM_CMD__PRE 0x0 +#define SIO_HI_RA_RAM_CMD_NULL 0x0 +#define SIO_HI_RA_RAM_CMD_UIO 0x1 +#define SIO_HI_RA_RAM_CMD_RESET 0x2 +#define SIO_HI_RA_RAM_CMD_CONFIG 0x3 +#define SIO_HI_RA_RAM_CMD_INTERNAL_TRANSFER 0x4 +#define SIO_HI_RA_RAM_CMD_I2C_TRANSMIT 0x5 +#define SIO_HI_RA_RAM_CMD_EXEC 0x6 +#define SIO_HI_RA_RAM_CMD_BRDCTRL 0x7 +#define SIO_HI_RA_RAM_CMD_ATOMIC_COPY 0x8 + +#define SIO_HI_RA_RAM_PAR_1__A 0x420033 +#define SIO_HI_RA_RAM_PAR_1__W 16 +#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0 +#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16 +#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945 + +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2 + +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_2__A 0x420034 +#define SIO_HI_RA_RAM_PAR_2__W 16 +#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0 +#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16 +#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25 + +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4 + +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_3__A 0x420035 +#define SIO_HI_RA_RAM_PAR_3__W 16 +#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0 +#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16 +#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F + +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80 + +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8 + +#define SIO_HI_RA_RAM_PAR_4__A 0x420036 +#define SIO_HI_RA_RAM_PAR_4__W 16 +#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_4__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0 +#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16 +#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1 + +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_5__A 0x420037 +#define SIO_HI_RA_RAM_PAR_5__W 16 +#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0 +#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16 +#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1 + +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2 + +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8 + +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20 + +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_6__A 0x420038 +#define SIO_HI_RA_RAM_PAR_6__W 16 +#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF +#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0 +#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16 +#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0 +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF + +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500 + + +#define SIO_HI_RA_RAM_AB_TEMP__A 0x42006E +#define SIO_HI_RA_RAM_AB_TEMP__W 16 +#define SIO_HI_RA_RAM_AB_TEMP__M 0xFFFF +#define SIO_HI_RA_RAM_AB_TEMP__PRE 0x0 + +#define SIO_HI_RA_RAM_I2C_CTL__A 0x42006F +#define SIO_HI_RA_RAM_I2C_CTL__W 16 +#define SIO_HI_RA_RAM_I2C_CTL__M 0xFFFF +#define SIO_HI_RA_RAM_I2C_CTL__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_ENTRY0__A 0x420070 +#define SIO_HI_RA_RAM_VB_ENTRY0__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY0__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY0__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__B 0 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__W 4 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__M 0xF +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__B 4 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__W 4 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__M 0xF0 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__B 8 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__W 4 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__M 0xF00 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__B 12 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__W 4 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__M 0xF000 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET0__A 0x420071 +#define SIO_HI_RA_RAM_VB_OFFSET0__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET0__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET0__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__PRE 0x0 + + +#define SIO_HI_RA_RAM_VB_ENTRY1__A 0x420072 +#define SIO_HI_RA_RAM_VB_ENTRY1__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY1__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY1__PRE 0x0 +#define SIO_HI_RA_RAM_VB_OFFSET1__A 0x420073 +#define SIO_HI_RA_RAM_VB_OFFSET1__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET1__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET1__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__PRE 0x0 + + +#define SIO_HI_RA_RAM_VB_ENTRY2__A 0x420074 +#define SIO_HI_RA_RAM_VB_ENTRY2__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY2__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY2__PRE 0x0 +#define SIO_HI_RA_RAM_VB_OFFSET2__A 0x420075 +#define SIO_HI_RA_RAM_VB_OFFSET2__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET2__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET2__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__PRE 0x0 + + +#define SIO_HI_RA_RAM_VB_ENTRY3__A 0x420076 +#define SIO_HI_RA_RAM_VB_ENTRY3__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY3__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY3__PRE 0x0 +#define SIO_HI_RA_RAM_VB_OFFSET3__A 0x420077 +#define SIO_HI_RA_RAM_VB_OFFSET3__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET3__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET3__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__PRE 0x0 + + +#define SIO_HI_RA_RAM_VB_ENTRY4__A 0x420078 +#define SIO_HI_RA_RAM_VB_ENTRY4__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY4__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY4__PRE 0x0 +#define SIO_HI_RA_RAM_VB_OFFSET4__A 0x420079 +#define SIO_HI_RA_RAM_VB_OFFSET4__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET4__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET4__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__PRE 0x0 + + +#define SIO_HI_RA_RAM_VB_ENTRY5__A 0x42007A +#define SIO_HI_RA_RAM_VB_ENTRY5__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY5__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY5__PRE 0x0 +#define SIO_HI_RA_RAM_VB_OFFSET5__A 0x42007B +#define SIO_HI_RA_RAM_VB_OFFSET5__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET5__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET5__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__PRE 0x0 + + +#define SIO_HI_RA_RAM_VB_ENTRY6__A 0x42007C +#define SIO_HI_RA_RAM_VB_ENTRY6__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY6__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY6__PRE 0x0 +#define SIO_HI_RA_RAM_VB_OFFSET6__A 0x42007D +#define SIO_HI_RA_RAM_VB_OFFSET6__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET6__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET6__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__PRE 0x0 + + +#define SIO_HI_RA_RAM_VB_ENTRY7__A 0x42007E +#define SIO_HI_RA_RAM_VB_ENTRY7__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY7__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY7__PRE 0x0 +#define SIO_HI_RA_RAM_VB_OFFSET7__A 0x42007F +#define SIO_HI_RA_RAM_VB_OFFSET7__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET7__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET7__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__PRE 0x0 + + + +#define SIO_HI_IF_RAM_TRP_BPT_0__A 0x430000 +#define SIO_HI_IF_RAM_TRP_BPT_0__W 12 +#define SIO_HI_IF_RAM_TRP_BPT_0__M 0xFFF +#define SIO_HI_IF_RAM_TRP_BPT_0__PRE 0x0 +#define SIO_HI_IF_RAM_TRP_BPT_1__A 0x430001 +#define SIO_HI_IF_RAM_TRP_BPT_1__W 12 +#define SIO_HI_IF_RAM_TRP_BPT_1__M 0xFFF +#define SIO_HI_IF_RAM_TRP_BPT_1__PRE 0x0 +#define SIO_HI_IF_RAM_TRP_STK_0__A 0x430002 +#define SIO_HI_IF_RAM_TRP_STK_0__W 12 +#define SIO_HI_IF_RAM_TRP_STK_0__M 0xFFF +#define SIO_HI_IF_RAM_TRP_STK_0__PRE 0x0 +#define SIO_HI_IF_RAM_TRP_STK_1__A 0x430003 +#define SIO_HI_IF_RAM_TRP_STK_1__W 12 +#define SIO_HI_IF_RAM_TRP_STK_1__M 0xFFF +#define SIO_HI_IF_RAM_TRP_STK_1__PRE 0x0 +#define SIO_HI_IF_RAM_FUN_BASE__A 0x430300 +#define SIO_HI_IF_RAM_FUN_BASE__W 12 +#define SIO_HI_IF_RAM_FUN_BASE__M 0xFFF +#define SIO_HI_IF_RAM_FUN_BASE__PRE 0x0 + + + +#define SIO_HI_IF_COMM_EXEC__A 0x440000 +#define SIO_HI_IF_COMM_EXEC__W 2 +#define SIO_HI_IF_COMM_EXEC__M 0x3 +#define SIO_HI_IF_COMM_EXEC__PRE 0x0 +#define SIO_HI_IF_COMM_EXEC_STOP 0x0 +#define SIO_HI_IF_COMM_EXEC_ACTIVE 0x1 +#define SIO_HI_IF_COMM_EXEC_HOLD 0x2 +#define SIO_HI_IF_COMM_EXEC_STEP 0x3 + + +#define SIO_HI_IF_COMM_STATE__A 0x440001 +#define SIO_HI_IF_COMM_STATE__W 10 +#define SIO_HI_IF_COMM_STATE__M 0x3FF +#define SIO_HI_IF_COMM_STATE__PRE 0x0 +#define SIO_HI_IF_COMM_INT_REQ__A 0x440003 +#define SIO_HI_IF_COMM_INT_REQ__W 1 +#define SIO_HI_IF_COMM_INT_REQ__M 0x1 +#define SIO_HI_IF_COMM_INT_REQ__PRE 0x0 +#define SIO_HI_IF_COMM_INT_STA__A 0x440005 +#define SIO_HI_IF_COMM_INT_STA__W 1 +#define SIO_HI_IF_COMM_INT_STA__M 0x1 +#define SIO_HI_IF_COMM_INT_STA__PRE 0x0 +#define SIO_HI_IF_COMM_INT_STA_STAT__B 0 +#define SIO_HI_IF_COMM_INT_STA_STAT__W 1 +#define SIO_HI_IF_COMM_INT_STA_STAT__M 0x1 +#define SIO_HI_IF_COMM_INT_STA_STAT__PRE 0x0 + +#define SIO_HI_IF_COMM_INT_MSK__A 0x440006 +#define SIO_HI_IF_COMM_INT_MSK__W 1 +#define SIO_HI_IF_COMM_INT_MSK__M 0x1 +#define SIO_HI_IF_COMM_INT_MSK__PRE 0x0 +#define SIO_HI_IF_COMM_INT_MSK_STAT__B 0 +#define SIO_HI_IF_COMM_INT_MSK_STAT__W 1 +#define SIO_HI_IF_COMM_INT_MSK_STAT__M 0x1 +#define SIO_HI_IF_COMM_INT_MSK_STAT__PRE 0x0 + +#define SIO_HI_IF_COMM_INT_STM__A 0x440007 +#define SIO_HI_IF_COMM_INT_STM__W 1 +#define SIO_HI_IF_COMM_INT_STM__M 0x1 +#define SIO_HI_IF_COMM_INT_STM__PRE 0x0 +#define SIO_HI_IF_COMM_INT_STM_STAT__B 0 +#define SIO_HI_IF_COMM_INT_STM_STAT__W 1 +#define SIO_HI_IF_COMM_INT_STM_STAT__M 0x1 +#define SIO_HI_IF_COMM_INT_STM_STAT__PRE 0x0 + +#define SIO_HI_IF_STK_0__A 0x440010 +#define SIO_HI_IF_STK_0__W 10 +#define SIO_HI_IF_STK_0__M 0x3FF +#define SIO_HI_IF_STK_0__PRE 0x2 + +#define SIO_HI_IF_STK_0_ADDR__B 0 +#define SIO_HI_IF_STK_0_ADDR__W 10 +#define SIO_HI_IF_STK_0_ADDR__M 0x3FF +#define SIO_HI_IF_STK_0_ADDR__PRE 0x2 + +#define SIO_HI_IF_STK_1__A 0x440011 +#define SIO_HI_IF_STK_1__W 10 +#define SIO_HI_IF_STK_1__M 0x3FF +#define SIO_HI_IF_STK_1__PRE 0x2 +#define SIO_HI_IF_STK_1_ADDR__B 0 +#define SIO_HI_IF_STK_1_ADDR__W 10 +#define SIO_HI_IF_STK_1_ADDR__M 0x3FF +#define SIO_HI_IF_STK_1_ADDR__PRE 0x2 + +#define SIO_HI_IF_STK_2__A 0x440012 +#define SIO_HI_IF_STK_2__W 10 +#define SIO_HI_IF_STK_2__M 0x3FF +#define SIO_HI_IF_STK_2__PRE 0x2 +#define SIO_HI_IF_STK_2_ADDR__B 0 +#define SIO_HI_IF_STK_2_ADDR__W 10 +#define SIO_HI_IF_STK_2_ADDR__M 0x3FF +#define SIO_HI_IF_STK_2_ADDR__PRE 0x2 + +#define SIO_HI_IF_STK_3__A 0x440013 +#define SIO_HI_IF_STK_3__W 10 +#define SIO_HI_IF_STK_3__M 0x3FF +#define SIO_HI_IF_STK_3__PRE 0x2 + +#define SIO_HI_IF_STK_3_ADDR__B 0 +#define SIO_HI_IF_STK_3_ADDR__W 10 +#define SIO_HI_IF_STK_3_ADDR__M 0x3FF +#define SIO_HI_IF_STK_3_ADDR__PRE 0x2 + +#define SIO_HI_IF_BPT_IDX__A 0x44001F +#define SIO_HI_IF_BPT_IDX__W 1 +#define SIO_HI_IF_BPT_IDX__M 0x1 +#define SIO_HI_IF_BPT_IDX__PRE 0x0 + +#define SIO_HI_IF_BPT_IDX_ADDR__B 0 +#define SIO_HI_IF_BPT_IDX_ADDR__W 1 +#define SIO_HI_IF_BPT_IDX_ADDR__M 0x1 +#define SIO_HI_IF_BPT_IDX_ADDR__PRE 0x0 + +#define SIO_HI_IF_BPT__A 0x440020 +#define SIO_HI_IF_BPT__W 10 +#define SIO_HI_IF_BPT__M 0x3FF +#define SIO_HI_IF_BPT__PRE 0x2 + +#define SIO_HI_IF_BPT_ADDR__B 0 +#define SIO_HI_IF_BPT_ADDR__W 10 +#define SIO_HI_IF_BPT_ADDR__M 0x3FF +#define SIO_HI_IF_BPT_ADDR__PRE 0x2 + + + +#define SIO_CC_COMM_EXEC__A 0x450000 +#define SIO_CC_COMM_EXEC__W 2 +#define SIO_CC_COMM_EXEC__M 0x3 +#define SIO_CC_COMM_EXEC__PRE 0x0 +#define SIO_CC_COMM_EXEC_STOP 0x0 +#define SIO_CC_COMM_EXEC_ACTIVE 0x1 +#define SIO_CC_COMM_EXEC_HOLD 0x2 + +#define SIO_CC_PLL_MODE__A 0x450010 +#define SIO_CC_PLL_MODE__W 6 +#define SIO_CC_PLL_MODE__M 0x3F +#define SIO_CC_PLL_MODE__PRE 0x0 + +#define SIO_CC_PLL_MODE_FREF_SEL__B 0 +#define SIO_CC_PLL_MODE_FREF_SEL__W 2 +#define SIO_CC_PLL_MODE_FREF_SEL__M 0x3 +#define SIO_CC_PLL_MODE_FREF_SEL__PRE 0x0 +#define SIO_CC_PLL_MODE_FREF_SEL_OHW 0x0 +#define SIO_CC_PLL_MODE_FREF_SEL_27_00 0x1 +#define SIO_CC_PLL_MODE_FREF_SEL_20_25 0x2 +#define SIO_CC_PLL_MODE_FREF_SEL_4_00 0x3 + +#define SIO_CC_PLL_MODE_LOCKSEL__B 2 +#define SIO_CC_PLL_MODE_LOCKSEL__W 2 +#define SIO_CC_PLL_MODE_LOCKSEL__M 0xC +#define SIO_CC_PLL_MODE_LOCKSEL__PRE 0x0 + +#define SIO_CC_PLL_MODE_BYPASS__B 4 +#define SIO_CC_PLL_MODE_BYPASS__W 2 +#define SIO_CC_PLL_MODE_BYPASS__M 0x30 +#define SIO_CC_PLL_MODE_BYPASS__PRE 0x0 +#define SIO_CC_PLL_MODE_BYPASS_OHW 0x0 +#define SIO_CC_PLL_MODE_BYPASS_OFF 0x10 +#define SIO_CC_PLL_MODE_BYPASS_ON 0x20 + + +#define SIO_CC_PLL_TEST__A 0x450011 +#define SIO_CC_PLL_TEST__W 8 +#define SIO_CC_PLL_TEST__M 0xFF +#define SIO_CC_PLL_TEST__PRE 0x0 + +#define SIO_CC_PLL_LOCK__A 0x450012 +#define SIO_CC_PLL_LOCK__W 1 +#define SIO_CC_PLL_LOCK__M 0x1 +#define SIO_CC_PLL_LOCK__PRE 0x0 +#define SIO_CC_CLK_MODE__A 0x450014 +#define SIO_CC_CLK_MODE__W 5 +#define SIO_CC_CLK_MODE__M 0x1F +#define SIO_CC_CLK_MODE__PRE 0x0 + +#define SIO_CC_CLK_MODE_DELAY__B 0 +#define SIO_CC_CLK_MODE_DELAY__W 4 +#define SIO_CC_CLK_MODE_DELAY__M 0xF +#define SIO_CC_CLK_MODE_DELAY__PRE 0x0 + +#define SIO_CC_CLK_MODE_INVERT__B 4 +#define SIO_CC_CLK_MODE_INVERT__W 1 +#define SIO_CC_CLK_MODE_INVERT__M 0x10 +#define SIO_CC_CLK_MODE_INVERT__PRE 0x0 + +#define SIO_CC_PWD_MODE__A 0x450015 +#define SIO_CC_PWD_MODE__W 3 +#define SIO_CC_PWD_MODE__M 0x7 +#define SIO_CC_PWD_MODE__PRE 0x0 + +#define SIO_CC_PWD_MODE_LEVEL__B 0 +#define SIO_CC_PWD_MODE_LEVEL__W 2 +#define SIO_CC_PWD_MODE_LEVEL__M 0x3 +#define SIO_CC_PWD_MODE_LEVEL__PRE 0x0 +#define SIO_CC_PWD_MODE_LEVEL_NONE 0x0 +#define SIO_CC_PWD_MODE_LEVEL_CLOCK 0x1 +#define SIO_CC_PWD_MODE_LEVEL_PLL 0x2 +#define SIO_CC_PWD_MODE_LEVEL_OSC 0x3 + +#define SIO_CC_PWD_MODE_USE_LOCK__B 2 +#define SIO_CC_PWD_MODE_USE_LOCK__W 1 +#define SIO_CC_PWD_MODE_USE_LOCK__M 0x4 +#define SIO_CC_PWD_MODE_USE_LOCK__PRE 0x0 + +#define SIO_CC_SOFT_RST__A 0x450016 +#define SIO_CC_SOFT_RST__W 2 +#define SIO_CC_SOFT_RST__M 0x3 +#define SIO_CC_SOFT_RST__PRE 0x0 + +#define SIO_CC_SOFT_RST_SYS__B 0 +#define SIO_CC_SOFT_RST_SYS__W 1 +#define SIO_CC_SOFT_RST_SYS__M 0x1 +#define SIO_CC_SOFT_RST_SYS__PRE 0x0 + +#define SIO_CC_SOFT_RST_OSC__B 1 +#define SIO_CC_SOFT_RST_OSC__W 1 +#define SIO_CC_SOFT_RST_OSC__M 0x2 +#define SIO_CC_SOFT_RST_OSC__PRE 0x0 + + +#define SIO_CC_UPDATE__A 0x450017 +#define SIO_CC_UPDATE__W 16 +#define SIO_CC_UPDATE__M 0xFFFF +#define SIO_CC_UPDATE__PRE 0x0 +#define SIO_CC_UPDATE_KEY 0xFABA + + + +#define SIO_SA_COMM_EXEC__A 0x460000 +#define SIO_SA_COMM_EXEC__W 2 +#define SIO_SA_COMM_EXEC__M 0x3 +#define SIO_SA_COMM_EXEC__PRE 0x0 +#define SIO_SA_COMM_EXEC_STOP 0x0 +#define SIO_SA_COMM_EXEC_ACTIVE 0x1 +#define SIO_SA_COMM_EXEC_HOLD 0x2 + +#define SIO_SA_COMM_INT_REQ__A 0x460003 +#define SIO_SA_COMM_INT_REQ__W 1 +#define SIO_SA_COMM_INT_REQ__M 0x1 +#define SIO_SA_COMM_INT_REQ__PRE 0x0 +#define SIO_SA_COMM_INT_STA__A 0x460005 +#define SIO_SA_COMM_INT_STA__W 4 +#define SIO_SA_COMM_INT_STA__M 0xF +#define SIO_SA_COMM_INT_STA__PRE 0x0 + +#define SIO_SA_COMM_INT_STA_TR_END_INT_STA__B 0 +#define SIO_SA_COMM_INT_STA_TR_END_INT_STA__W 1 +#define SIO_SA_COMM_INT_STA_TR_END_INT_STA__M 0x1 +#define SIO_SA_COMM_INT_STA_TR_END_INT_STA__PRE 0x0 + +#define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__B 1 +#define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__W 1 +#define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__M 0x2 +#define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__PRE 0x0 + +#define SIO_SA_COMM_INT_STA_RX_END_INT_STA__B 2 +#define SIO_SA_COMM_INT_STA_RX_END_INT_STA__W 1 +#define SIO_SA_COMM_INT_STA_RX_END_INT_STA__M 0x4 +#define SIO_SA_COMM_INT_STA_RX_END_INT_STA__PRE 0x0 + +#define SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__B 3 +#define SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__W 1 +#define SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__M 0x8 +#define SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__PRE 0x0 + +#define SIO_SA_COMM_INT_MSK__A 0x460006 +#define SIO_SA_COMM_INT_MSK__W 4 +#define SIO_SA_COMM_INT_MSK__M 0xF +#define SIO_SA_COMM_INT_MSK__PRE 0x0 + +#define SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__B 0 +#define SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__W 1 +#define SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__M 0x1 +#define SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__PRE 0x0 + +#define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__B 1 +#define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__W 1 +#define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__M 0x2 +#define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__PRE 0x0 + +#define SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__B 2 +#define SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__W 1 +#define SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__M 0x4 +#define SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__PRE 0x0 + +#define SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__B 3 +#define SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__W 1 +#define SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__M 0x8 +#define SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__PRE 0x0 + +#define SIO_SA_COMM_INT_STM__A 0x460007 +#define SIO_SA_COMM_INT_STM__W 4 +#define SIO_SA_COMM_INT_STM__M 0xF +#define SIO_SA_COMM_INT_STM__PRE 0x0 + +#define SIO_SA_COMM_INT_STM_TR_END_INT_MASK__B 0 +#define SIO_SA_COMM_INT_STM_TR_END_INT_MASK__W 1 +#define SIO_SA_COMM_INT_STM_TR_END_INT_MASK__M 0x1 +#define SIO_SA_COMM_INT_STM_TR_END_INT_MASK__PRE 0x0 + +#define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__B 1 +#define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__W 1 +#define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__M 0x2 +#define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__PRE 0x0 + +#define SIO_SA_COMM_INT_STM_RX_END_INT_MASK__B 2 +#define SIO_SA_COMM_INT_STM_RX_END_INT_MASK__W 1 +#define SIO_SA_COMM_INT_STM_RX_END_INT_MASK__M 0x4 +#define SIO_SA_COMM_INT_STM_RX_END_INT_MASK__PRE 0x0 + +#define SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__B 3 +#define SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__W 1 +#define SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__M 0x8 +#define SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__PRE 0x0 + +#define SIO_SA_PRESCALER__A 0x460010 +#define SIO_SA_PRESCALER__W 13 +#define SIO_SA_PRESCALER__M 0x1FFF +#define SIO_SA_PRESCALER__PRE 0x18B7 +#define SIO_SA_TX_DATA0__A 0x460011 +#define SIO_SA_TX_DATA0__W 16 +#define SIO_SA_TX_DATA0__M 0xFFFF +#define SIO_SA_TX_DATA0__PRE 0x0 +#define SIO_SA_TX_DATA1__A 0x460012 +#define SIO_SA_TX_DATA1__W 16 +#define SIO_SA_TX_DATA1__M 0xFFFF +#define SIO_SA_TX_DATA1__PRE 0x0 +#define SIO_SA_TX_DATA2__A 0x460013 +#define SIO_SA_TX_DATA2__W 16 +#define SIO_SA_TX_DATA2__M 0xFFFF +#define SIO_SA_TX_DATA2__PRE 0x0 +#define SIO_SA_TX_DATA3__A 0x460014 +#define SIO_SA_TX_DATA3__W 16 +#define SIO_SA_TX_DATA3__M 0xFFFF +#define SIO_SA_TX_DATA3__PRE 0x0 +#define SIO_SA_TX_LENGTH__A 0x460015 +#define SIO_SA_TX_LENGTH__W 6 +#define SIO_SA_TX_LENGTH__M 0x3F +#define SIO_SA_TX_LENGTH__PRE 0x0 +#define SIO_SA_TX_COMMAND__A 0x460016 +#define SIO_SA_TX_COMMAND__W 2 +#define SIO_SA_TX_COMMAND__M 0x3 +#define SIO_SA_TX_COMMAND__PRE 0x3 + +#define SIO_SA_TX_COMMAND_TX_INVERT__B 0 +#define SIO_SA_TX_COMMAND_TX_INVERT__W 1 +#define SIO_SA_TX_COMMAND_TX_INVERT__M 0x1 +#define SIO_SA_TX_COMMAND_TX_INVERT__PRE 0x1 + +#define SIO_SA_TX_COMMAND_TX_ENABLE__B 1 +#define SIO_SA_TX_COMMAND_TX_ENABLE__W 1 +#define SIO_SA_TX_COMMAND_TX_ENABLE__M 0x2 +#define SIO_SA_TX_COMMAND_TX_ENABLE__PRE 0x2 + +#define SIO_SA_TX_STATUS__A 0x460017 +#define SIO_SA_TX_STATUS__W 2 +#define SIO_SA_TX_STATUS__M 0x3 +#define SIO_SA_TX_STATUS__PRE 0x0 + +#define SIO_SA_TX_STATUS_BUSY__B 0 +#define SIO_SA_TX_STATUS_BUSY__W 1 +#define SIO_SA_TX_STATUS_BUSY__M 0x1 +#define SIO_SA_TX_STATUS_BUSY__PRE 0x0 + +#define SIO_SA_TX_STATUS_BUFF_FULL__B 1 +#define SIO_SA_TX_STATUS_BUFF_FULL__W 1 +#define SIO_SA_TX_STATUS_BUFF_FULL__M 0x2 +#define SIO_SA_TX_STATUS_BUFF_FULL__PRE 0x0 + +#define SIO_SA_RX_DATA0__A 0x460018 +#define SIO_SA_RX_DATA0__W 16 +#define SIO_SA_RX_DATA0__M 0xFFFF +#define SIO_SA_RX_DATA0__PRE 0x0 +#define SIO_SA_RX_DATA1__A 0x460019 +#define SIO_SA_RX_DATA1__W 16 +#define SIO_SA_RX_DATA1__M 0xFFFF +#define SIO_SA_RX_DATA1__PRE 0x0 +#define SIO_SA_RX_LENGTH__A 0x46001A +#define SIO_SA_RX_LENGTH__W 6 +#define SIO_SA_RX_LENGTH__M 0x3F +#define SIO_SA_RX_LENGTH__PRE 0x0 +#define SIO_SA_RX_COMMAND__A 0x46001B +#define SIO_SA_RX_COMMAND__W 1 +#define SIO_SA_RX_COMMAND__M 0x1 +#define SIO_SA_RX_COMMAND__PRE 0x1 + +#define SIO_SA_RX_COMMAND_RX_INVERT__B 0 +#define SIO_SA_RX_COMMAND_RX_INVERT__W 1 +#define SIO_SA_RX_COMMAND_RX_INVERT__M 0x1 +#define SIO_SA_RX_COMMAND_RX_INVERT__PRE 0x1 + +#define SIO_SA_RX_STATUS__A 0x46001C +#define SIO_SA_RX_STATUS__W 2 +#define SIO_SA_RX_STATUS__M 0x3 +#define SIO_SA_RX_STATUS__PRE 0x0 + +#define SIO_SA_RX_STATUS_BUSY__B 0 +#define SIO_SA_RX_STATUS_BUSY__W 1 +#define SIO_SA_RX_STATUS_BUSY__M 0x1 +#define SIO_SA_RX_STATUS_BUSY__PRE 0x0 + +#define SIO_SA_RX_STATUS_BUFF_FULL__B 1 +#define SIO_SA_RX_STATUS_BUFF_FULL__W 1 +#define SIO_SA_RX_STATUS_BUFF_FULL__M 0x2 +#define SIO_SA_RX_STATUS_BUFF_FULL__PRE 0x0 + + + +#define SIO_PDR_COMM_EXEC__A 0x7F0000 +#define SIO_PDR_COMM_EXEC__W 2 +#define SIO_PDR_COMM_EXEC__M 0x3 +#define SIO_PDR_COMM_EXEC__PRE 0x0 +#define SIO_PDR_COMM_EXEC_STOP 0x0 +#define SIO_PDR_COMM_EXEC_ACTIVE 0x1 +#define SIO_PDR_COMM_EXEC_HOLD 0x2 + +#define SIO_PDR_MON_CFG__A 0x7F0010 +#define SIO_PDR_MON_CFG__W 2 +#define SIO_PDR_MON_CFG__M 0x3 +#define SIO_PDR_MON_CFG__PRE 0x0 + +#define SIO_PDR_MON_CFG_OSEL__B 0 +#define SIO_PDR_MON_CFG_OSEL__W 1 +#define SIO_PDR_MON_CFG_OSEL__M 0x1 +#define SIO_PDR_MON_CFG_OSEL__PRE 0x0 + +#define SIO_PDR_MON_CFG_IACT__B 1 +#define SIO_PDR_MON_CFG_IACT__W 1 +#define SIO_PDR_MON_CFG_IACT__M 0x2 +#define SIO_PDR_MON_CFG_IACT__PRE 0x0 + +#define SIO_PDR_FDB_CFG__A 0x7F0011 +#define SIO_PDR_FDB_CFG__W 2 +#define SIO_PDR_FDB_CFG__M 0x3 +#define SIO_PDR_FDB_CFG__PRE 0x0 +#define SIO_PDR_FDB_CFG_SEL__B 0 +#define SIO_PDR_FDB_CFG_SEL__W 2 +#define SIO_PDR_FDB_CFG_SEL__M 0x3 +#define SIO_PDR_FDB_CFG_SEL__PRE 0x0 + +#define SIO_PDR_SMA_RX_SEL__A 0x7F0012 +#define SIO_PDR_SMA_RX_SEL__W 4 +#define SIO_PDR_SMA_RX_SEL__M 0xF +#define SIO_PDR_SMA_RX_SEL__PRE 0x0 +#define SIO_PDR_SMA_RX_SEL_SEL__B 0 +#define SIO_PDR_SMA_RX_SEL_SEL__W 4 +#define SIO_PDR_SMA_RX_SEL_SEL__M 0xF +#define SIO_PDR_SMA_RX_SEL_SEL__PRE 0x0 + +#define SIO_PDR_SMA_TX_SILENT__A 0x7F0013 +#define SIO_PDR_SMA_TX_SILENT__W 1 +#define SIO_PDR_SMA_TX_SILENT__M 0x1 +#define SIO_PDR_SMA_TX_SILENT__PRE 0x0 +#define SIO_PDR_UIO_IN_LO__A 0x7F0014 +#define SIO_PDR_UIO_IN_LO__W 16 +#define SIO_PDR_UIO_IN_LO__M 0xFFFF +#define SIO_PDR_UIO_IN_LO__PRE 0x0 +#define SIO_PDR_UIO_IN_LO_DATA__B 0 +#define SIO_PDR_UIO_IN_LO_DATA__W 16 +#define SIO_PDR_UIO_IN_LO_DATA__M 0xFFFF +#define SIO_PDR_UIO_IN_LO_DATA__PRE 0x0 + +#define SIO_PDR_UIO_IN_HI__A 0x7F0015 +#define SIO_PDR_UIO_IN_HI__W 14 +#define SIO_PDR_UIO_IN_HI__M 0x3FFF +#define SIO_PDR_UIO_IN_HI__PRE 0x0 +#define SIO_PDR_UIO_IN_HI_DATA__B 0 +#define SIO_PDR_UIO_IN_HI_DATA__W 14 +#define SIO_PDR_UIO_IN_HI_DATA__M 0x3FFF +#define SIO_PDR_UIO_IN_HI_DATA__PRE 0x0 + +#define SIO_PDR_UIO_OUT_LO__A 0x7F0016 +#define SIO_PDR_UIO_OUT_LO__W 16 +#define SIO_PDR_UIO_OUT_LO__M 0xFFFF +#define SIO_PDR_UIO_OUT_LO__PRE 0x0 +#define SIO_PDR_UIO_OUT_LO_DATA__B 0 +#define SIO_PDR_UIO_OUT_LO_DATA__W 16 +#define SIO_PDR_UIO_OUT_LO_DATA__M 0xFFFF +#define SIO_PDR_UIO_OUT_LO_DATA__PRE 0x0 + +#define SIO_PDR_UIO_OUT_HI__A 0x7F0017 +#define SIO_PDR_UIO_OUT_HI__W 14 +#define SIO_PDR_UIO_OUT_HI__M 0x3FFF +#define SIO_PDR_UIO_OUT_HI__PRE 0x0 +#define SIO_PDR_UIO_OUT_HI_DATA__B 0 +#define SIO_PDR_UIO_OUT_HI_DATA__W 14 +#define SIO_PDR_UIO_OUT_HI_DATA__M 0x3FFF +#define SIO_PDR_UIO_OUT_HI_DATA__PRE 0x0 + +#define SIO_PDR_PWM1_MODE__A 0x7F0018 +#define SIO_PDR_PWM1_MODE__W 2 +#define SIO_PDR_PWM1_MODE__M 0x3 +#define SIO_PDR_PWM1_MODE__PRE 0x0 +#define SIO_PDR_PWM1_PRESCALE__A 0x7F0019 +#define SIO_PDR_PWM1_PRESCALE__W 6 +#define SIO_PDR_PWM1_PRESCALE__M 0x3F +#define SIO_PDR_PWM1_PRESCALE__PRE 0x0 +#define SIO_PDR_PWM1_VALUE__A 0x7F001A +#define SIO_PDR_PWM1_VALUE__W 11 +#define SIO_PDR_PWM1_VALUE__M 0x7FF +#define SIO_PDR_PWM1_VALUE__PRE 0x0 +#define SIO_PDR_PWM2_MODE__A 0x7F001C +#define SIO_PDR_PWM2_MODE__W 2 +#define SIO_PDR_PWM2_MODE__M 0x3 +#define SIO_PDR_PWM2_MODE__PRE 0x0 +#define SIO_PDR_PWM2_PRESCALE__A 0x7F001D +#define SIO_PDR_PWM2_PRESCALE__W 6 +#define SIO_PDR_PWM2_PRESCALE__M 0x3F +#define SIO_PDR_PWM2_PRESCALE__PRE 0x0 +#define SIO_PDR_PWM2_VALUE__A 0x7F001E +#define SIO_PDR_PWM2_VALUE__W 11 +#define SIO_PDR_PWM2_VALUE__M 0x7FF +#define SIO_PDR_PWM2_VALUE__PRE 0x0 +#define SIO_PDR_OHW_CFG__A 0x7F001F +#define SIO_PDR_OHW_CFG__W 7 +#define SIO_PDR_OHW_CFG__M 0x7F +#define SIO_PDR_OHW_CFG__PRE 0x0 + +#define SIO_PDR_OHW_CFG_FREF_SEL__B 0 +#define SIO_PDR_OHW_CFG_FREF_SEL__W 2 +#define SIO_PDR_OHW_CFG_FREF_SEL__M 0x3 +#define SIO_PDR_OHW_CFG_FREF_SEL__PRE 0x0 + +#define SIO_PDR_OHW_CFG_BYPASS__B 2 +#define SIO_PDR_OHW_CFG_BYPASS__W 1 +#define SIO_PDR_OHW_CFG_BYPASS__M 0x4 +#define SIO_PDR_OHW_CFG_BYPASS__PRE 0x0 + +#define SIO_PDR_OHW_CFG_ASEL__B 3 +#define SIO_PDR_OHW_CFG_ASEL__W 3 +#define SIO_PDR_OHW_CFG_ASEL__M 0x38 +#define SIO_PDR_OHW_CFG_ASEL__PRE 0x0 + +#define SIO_PDR_OHW_CFG_SPEED__B 6 +#define SIO_PDR_OHW_CFG_SPEED__W 1 +#define SIO_PDR_OHW_CFG_SPEED__M 0x40 +#define SIO_PDR_OHW_CFG_SPEED__PRE 0x0 + +#define SIO_PDR_I2S_WS_CFG__A 0x7F0020 +#define SIO_PDR_I2S_WS_CFG__W 9 +#define SIO_PDR_I2S_WS_CFG__M 0x1FF +#define SIO_PDR_I2S_WS_CFG__PRE 0x10 +#define SIO_PDR_I2S_WS_CFG_MODE__B 0 +#define SIO_PDR_I2S_WS_CFG_MODE__W 3 +#define SIO_PDR_I2S_WS_CFG_MODE__M 0x7 +#define SIO_PDR_I2S_WS_CFG_MODE__PRE 0x0 +#define SIO_PDR_I2S_WS_CFG_DRIVE__B 3 +#define SIO_PDR_I2S_WS_CFG_DRIVE__W 3 +#define SIO_PDR_I2S_WS_CFG_DRIVE__M 0x38 +#define SIO_PDR_I2S_WS_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_I2S_WS_CFG_KEEP__B 6 +#define SIO_PDR_I2S_WS_CFG_KEEP__W 2 +#define SIO_PDR_I2S_WS_CFG_KEEP__M 0xC0 +#define SIO_PDR_I2S_WS_CFG_KEEP__PRE 0x0 +#define SIO_PDR_I2S_WS_CFG_UIO__B 8 +#define SIO_PDR_I2S_WS_CFG_UIO__W 1 +#define SIO_PDR_I2S_WS_CFG_UIO__M 0x100 +#define SIO_PDR_I2S_WS_CFG_UIO__PRE 0x0 + +#define SIO_PDR_GPIO_CFG__A 0x7F0021 +#define SIO_PDR_GPIO_CFG__W 9 +#define SIO_PDR_GPIO_CFG__M 0x1FF +#define SIO_PDR_GPIO_CFG__PRE 0x10 +#define SIO_PDR_GPIO_CFG_MODE__B 0 +#define SIO_PDR_GPIO_CFG_MODE__W 3 +#define SIO_PDR_GPIO_CFG_MODE__M 0x7 +#define SIO_PDR_GPIO_CFG_MODE__PRE 0x0 +#define SIO_PDR_GPIO_CFG_DRIVE__B 3 +#define SIO_PDR_GPIO_CFG_DRIVE__W 3 +#define SIO_PDR_GPIO_CFG_DRIVE__M 0x38 +#define SIO_PDR_GPIO_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_GPIO_CFG_KEEP__B 6 +#define SIO_PDR_GPIO_CFG_KEEP__W 2 +#define SIO_PDR_GPIO_CFG_KEEP__M 0xC0 +#define SIO_PDR_GPIO_CFG_KEEP__PRE 0x0 +#define SIO_PDR_GPIO_CFG_UIO__B 8 +#define SIO_PDR_GPIO_CFG_UIO__W 1 +#define SIO_PDR_GPIO_CFG_UIO__M 0x100 +#define SIO_PDR_GPIO_CFG_UIO__PRE 0x0 + +#define SIO_PDR_IRQN_CFG__A 0x7F0022 +#define SIO_PDR_IRQN_CFG__W 9 +#define SIO_PDR_IRQN_CFG__M 0x1FF +#define SIO_PDR_IRQN_CFG__PRE 0x10 +#define SIO_PDR_IRQN_CFG_MODE__B 0 +#define SIO_PDR_IRQN_CFG_MODE__W 3 +#define SIO_PDR_IRQN_CFG_MODE__M 0x7 +#define SIO_PDR_IRQN_CFG_MODE__PRE 0x0 +#define SIO_PDR_IRQN_CFG_DRIVE__B 3 +#define SIO_PDR_IRQN_CFG_DRIVE__W 3 +#define SIO_PDR_IRQN_CFG_DRIVE__M 0x38 +#define SIO_PDR_IRQN_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_IRQN_CFG_KEEP__B 6 +#define SIO_PDR_IRQN_CFG_KEEP__W 2 +#define SIO_PDR_IRQN_CFG_KEEP__M 0xC0 +#define SIO_PDR_IRQN_CFG_KEEP__PRE 0x0 +#define SIO_PDR_IRQN_CFG_UIO__B 8 +#define SIO_PDR_IRQN_CFG_UIO__W 1 +#define SIO_PDR_IRQN_CFG_UIO__M 0x100 +#define SIO_PDR_IRQN_CFG_UIO__PRE 0x0 + +#define SIO_PDR_OOB_CRX_CFG__A 0x7F0023 +#define SIO_PDR_OOB_CRX_CFG__W 9 +#define SIO_PDR_OOB_CRX_CFG__M 0x1FF +#define SIO_PDR_OOB_CRX_CFG__PRE 0x10 +#define SIO_PDR_OOB_CRX_CFG_MODE__B 0 +#define SIO_PDR_OOB_CRX_CFG_MODE__W 3 +#define SIO_PDR_OOB_CRX_CFG_MODE__M 0x7 +#define SIO_PDR_OOB_CRX_CFG_MODE__PRE 0x0 +#define SIO_PDR_OOB_CRX_CFG_DRIVE__B 3 +#define SIO_PDR_OOB_CRX_CFG_DRIVE__W 3 +#define SIO_PDR_OOB_CRX_CFG_DRIVE__M 0x38 +#define SIO_PDR_OOB_CRX_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_OOB_CRX_CFG_KEEP__B 6 +#define SIO_PDR_OOB_CRX_CFG_KEEP__W 2 +#define SIO_PDR_OOB_CRX_CFG_KEEP__M 0xC0 +#define SIO_PDR_OOB_CRX_CFG_KEEP__PRE 0x0 +#define SIO_PDR_OOB_CRX_CFG_UIO__B 8 +#define SIO_PDR_OOB_CRX_CFG_UIO__W 1 +#define SIO_PDR_OOB_CRX_CFG_UIO__M 0x100 +#define SIO_PDR_OOB_CRX_CFG_UIO__PRE 0x0 + +#define SIO_PDR_OOB_DRX_CFG__A 0x7F0024 +#define SIO_PDR_OOB_DRX_CFG__W 9 +#define SIO_PDR_OOB_DRX_CFG__M 0x1FF +#define SIO_PDR_OOB_DRX_CFG__PRE 0x10 +#define SIO_PDR_OOB_DRX_CFG_MODE__B 0 +#define SIO_PDR_OOB_DRX_CFG_MODE__W 3 +#define SIO_PDR_OOB_DRX_CFG_MODE__M 0x7 +#define SIO_PDR_OOB_DRX_CFG_MODE__PRE 0x0 +#define SIO_PDR_OOB_DRX_CFG_DRIVE__B 3 +#define SIO_PDR_OOB_DRX_CFG_DRIVE__W 3 +#define SIO_PDR_OOB_DRX_CFG_DRIVE__M 0x38 +#define SIO_PDR_OOB_DRX_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_OOB_DRX_CFG_KEEP__B 6 +#define SIO_PDR_OOB_DRX_CFG_KEEP__W 2 +#define SIO_PDR_OOB_DRX_CFG_KEEP__M 0xC0 +#define SIO_PDR_OOB_DRX_CFG_KEEP__PRE 0x0 +#define SIO_PDR_OOB_DRX_CFG_UIO__B 8 +#define SIO_PDR_OOB_DRX_CFG_UIO__W 1 +#define SIO_PDR_OOB_DRX_CFG_UIO__M 0x100 +#define SIO_PDR_OOB_DRX_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MSTRT_CFG__A 0x7F0025 +#define SIO_PDR_MSTRT_CFG__W 9 +#define SIO_PDR_MSTRT_CFG__M 0x1FF +#define SIO_PDR_MSTRT_CFG__PRE 0x50 +#define SIO_PDR_MSTRT_CFG_MODE__B 0 +#define SIO_PDR_MSTRT_CFG_MODE__W 3 +#define SIO_PDR_MSTRT_CFG_MODE__M 0x7 +#define SIO_PDR_MSTRT_CFG_MODE__PRE 0x0 +#define SIO_PDR_MSTRT_CFG_DRIVE__B 3 +#define SIO_PDR_MSTRT_CFG_DRIVE__W 3 +#define SIO_PDR_MSTRT_CFG_DRIVE__M 0x38 +#define SIO_PDR_MSTRT_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MSTRT_CFG_KEEP__B 6 +#define SIO_PDR_MSTRT_CFG_KEEP__W 2 +#define SIO_PDR_MSTRT_CFG_KEEP__M 0xC0 +#define SIO_PDR_MSTRT_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MSTRT_CFG_UIO__B 8 +#define SIO_PDR_MSTRT_CFG_UIO__W 1 +#define SIO_PDR_MSTRT_CFG_UIO__M 0x100 +#define SIO_PDR_MSTRT_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MERR_CFG__A 0x7F0026 +#define SIO_PDR_MERR_CFG__W 9 +#define SIO_PDR_MERR_CFG__M 0x1FF +#define SIO_PDR_MERR_CFG__PRE 0x50 +#define SIO_PDR_MERR_CFG_MODE__B 0 +#define SIO_PDR_MERR_CFG_MODE__W 3 +#define SIO_PDR_MERR_CFG_MODE__M 0x7 +#define SIO_PDR_MERR_CFG_MODE__PRE 0x0 +#define SIO_PDR_MERR_CFG_DRIVE__B 3 +#define SIO_PDR_MERR_CFG_DRIVE__W 3 +#define SIO_PDR_MERR_CFG_DRIVE__M 0x38 +#define SIO_PDR_MERR_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MERR_CFG_KEEP__B 6 +#define SIO_PDR_MERR_CFG_KEEP__W 2 +#define SIO_PDR_MERR_CFG_KEEP__M 0xC0 +#define SIO_PDR_MERR_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MERR_CFG_UIO__B 8 +#define SIO_PDR_MERR_CFG_UIO__W 1 +#define SIO_PDR_MERR_CFG_UIO__M 0x100 +#define SIO_PDR_MERR_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MCLK_CFG__A 0x7F0028 +#define SIO_PDR_MCLK_CFG__W 9 +#define SIO_PDR_MCLK_CFG__M 0x1FF +#define SIO_PDR_MCLK_CFG__PRE 0x50 +#define SIO_PDR_MCLK_CFG_MODE__B 0 +#define SIO_PDR_MCLK_CFG_MODE__W 3 +#define SIO_PDR_MCLK_CFG_MODE__M 0x7 +#define SIO_PDR_MCLK_CFG_MODE__PRE 0x0 +#define SIO_PDR_MCLK_CFG_DRIVE__B 3 +#define SIO_PDR_MCLK_CFG_DRIVE__W 3 +#define SIO_PDR_MCLK_CFG_DRIVE__M 0x38 +#define SIO_PDR_MCLK_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MCLK_CFG_KEEP__B 6 +#define SIO_PDR_MCLK_CFG_KEEP__W 2 +#define SIO_PDR_MCLK_CFG_KEEP__M 0xC0 +#define SIO_PDR_MCLK_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MCLK_CFG_UIO__B 8 +#define SIO_PDR_MCLK_CFG_UIO__W 1 +#define SIO_PDR_MCLK_CFG_UIO__M 0x100 +#define SIO_PDR_MCLK_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MVAL_CFG__A 0x7F0029 +#define SIO_PDR_MVAL_CFG__W 9 +#define SIO_PDR_MVAL_CFG__M 0x1FF +#define SIO_PDR_MVAL_CFG__PRE 0x50 +#define SIO_PDR_MVAL_CFG_MODE__B 0 +#define SIO_PDR_MVAL_CFG_MODE__W 3 +#define SIO_PDR_MVAL_CFG_MODE__M 0x7 +#define SIO_PDR_MVAL_CFG_MODE__PRE 0x0 +#define SIO_PDR_MVAL_CFG_DRIVE__B 3 +#define SIO_PDR_MVAL_CFG_DRIVE__W 3 +#define SIO_PDR_MVAL_CFG_DRIVE__M 0x38 +#define SIO_PDR_MVAL_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MVAL_CFG_KEEP__B 6 +#define SIO_PDR_MVAL_CFG_KEEP__W 2 +#define SIO_PDR_MVAL_CFG_KEEP__M 0xC0 +#define SIO_PDR_MVAL_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MVAL_CFG_UIO__B 8 +#define SIO_PDR_MVAL_CFG_UIO__W 1 +#define SIO_PDR_MVAL_CFG_UIO__M 0x100 +#define SIO_PDR_MVAL_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD0_CFG__A 0x7F002A +#define SIO_PDR_MD0_CFG__W 9 +#define SIO_PDR_MD0_CFG__M 0x1FF +#define SIO_PDR_MD0_CFG__PRE 0x50 +#define SIO_PDR_MD0_CFG_MODE__B 0 +#define SIO_PDR_MD0_CFG_MODE__W 3 +#define SIO_PDR_MD0_CFG_MODE__M 0x7 +#define SIO_PDR_MD0_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD0_CFG_DRIVE__B 3 +#define SIO_PDR_MD0_CFG_DRIVE__W 3 +#define SIO_PDR_MD0_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD0_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD0_CFG_KEEP__B 6 +#define SIO_PDR_MD0_CFG_KEEP__W 2 +#define SIO_PDR_MD0_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD0_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD0_CFG_UIO__B 8 +#define SIO_PDR_MD0_CFG_UIO__W 1 +#define SIO_PDR_MD0_CFG_UIO__M 0x100 +#define SIO_PDR_MD0_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD1_CFG__A 0x7F002B +#define SIO_PDR_MD1_CFG__W 9 +#define SIO_PDR_MD1_CFG__M 0x1FF +#define SIO_PDR_MD1_CFG__PRE 0x50 +#define SIO_PDR_MD1_CFG_MODE__B 0 +#define SIO_PDR_MD1_CFG_MODE__W 3 +#define SIO_PDR_MD1_CFG_MODE__M 0x7 +#define SIO_PDR_MD1_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD1_CFG_DRIVE__B 3 +#define SIO_PDR_MD1_CFG_DRIVE__W 3 +#define SIO_PDR_MD1_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD1_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD1_CFG_KEEP__B 6 +#define SIO_PDR_MD1_CFG_KEEP__W 2 +#define SIO_PDR_MD1_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD1_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD1_CFG_UIO__B 8 +#define SIO_PDR_MD1_CFG_UIO__W 1 +#define SIO_PDR_MD1_CFG_UIO__M 0x100 +#define SIO_PDR_MD1_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD2_CFG__A 0x7F002C +#define SIO_PDR_MD2_CFG__W 9 +#define SIO_PDR_MD2_CFG__M 0x1FF +#define SIO_PDR_MD2_CFG__PRE 0x50 +#define SIO_PDR_MD2_CFG_MODE__B 0 +#define SIO_PDR_MD2_CFG_MODE__W 3 +#define SIO_PDR_MD2_CFG_MODE__M 0x7 +#define SIO_PDR_MD2_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD2_CFG_DRIVE__B 3 +#define SIO_PDR_MD2_CFG_DRIVE__W 3 +#define SIO_PDR_MD2_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD2_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD2_CFG_KEEP__B 6 +#define SIO_PDR_MD2_CFG_KEEP__W 2 +#define SIO_PDR_MD2_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD2_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD2_CFG_UIO__B 8 +#define SIO_PDR_MD2_CFG_UIO__W 1 +#define SIO_PDR_MD2_CFG_UIO__M 0x100 +#define SIO_PDR_MD2_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD3_CFG__A 0x7F002D +#define SIO_PDR_MD3_CFG__W 9 +#define SIO_PDR_MD3_CFG__M 0x1FF +#define SIO_PDR_MD3_CFG__PRE 0x50 +#define SIO_PDR_MD3_CFG_MODE__B 0 +#define SIO_PDR_MD3_CFG_MODE__W 3 +#define SIO_PDR_MD3_CFG_MODE__M 0x7 +#define SIO_PDR_MD3_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD3_CFG_DRIVE__B 3 +#define SIO_PDR_MD3_CFG_DRIVE__W 3 +#define SIO_PDR_MD3_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD3_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD3_CFG_KEEP__B 6 +#define SIO_PDR_MD3_CFG_KEEP__W 2 +#define SIO_PDR_MD3_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD3_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD3_CFG_UIO__B 8 +#define SIO_PDR_MD3_CFG_UIO__W 1 +#define SIO_PDR_MD3_CFG_UIO__M 0x100 +#define SIO_PDR_MD3_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD4_CFG__A 0x7F002F +#define SIO_PDR_MD4_CFG__W 9 +#define SIO_PDR_MD4_CFG__M 0x1FF +#define SIO_PDR_MD4_CFG__PRE 0x50 +#define SIO_PDR_MD4_CFG_MODE__B 0 +#define SIO_PDR_MD4_CFG_MODE__W 3 +#define SIO_PDR_MD4_CFG_MODE__M 0x7 +#define SIO_PDR_MD4_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD4_CFG_DRIVE__B 3 +#define SIO_PDR_MD4_CFG_DRIVE__W 3 +#define SIO_PDR_MD4_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD4_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD4_CFG_KEEP__B 6 +#define SIO_PDR_MD4_CFG_KEEP__W 2 +#define SIO_PDR_MD4_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD4_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD4_CFG_UIO__B 8 +#define SIO_PDR_MD4_CFG_UIO__W 1 +#define SIO_PDR_MD4_CFG_UIO__M 0x100 +#define SIO_PDR_MD4_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD5_CFG__A 0x7F0030 +#define SIO_PDR_MD5_CFG__W 9 +#define SIO_PDR_MD5_CFG__M 0x1FF +#define SIO_PDR_MD5_CFG__PRE 0x50 +#define SIO_PDR_MD5_CFG_MODE__B 0 +#define SIO_PDR_MD5_CFG_MODE__W 3 +#define SIO_PDR_MD5_CFG_MODE__M 0x7 +#define SIO_PDR_MD5_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD5_CFG_DRIVE__B 3 +#define SIO_PDR_MD5_CFG_DRIVE__W 3 +#define SIO_PDR_MD5_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD5_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD5_CFG_KEEP__B 6 +#define SIO_PDR_MD5_CFG_KEEP__W 2 +#define SIO_PDR_MD5_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD5_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD5_CFG_UIO__B 8 +#define SIO_PDR_MD5_CFG_UIO__W 1 +#define SIO_PDR_MD5_CFG_UIO__M 0x100 +#define SIO_PDR_MD5_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD6_CFG__A 0x7F0031 +#define SIO_PDR_MD6_CFG__W 9 +#define SIO_PDR_MD6_CFG__M 0x1FF +#define SIO_PDR_MD6_CFG__PRE 0x50 +#define SIO_PDR_MD6_CFG_MODE__B 0 +#define SIO_PDR_MD6_CFG_MODE__W 3 +#define SIO_PDR_MD6_CFG_MODE__M 0x7 +#define SIO_PDR_MD6_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD6_CFG_DRIVE__B 3 +#define SIO_PDR_MD6_CFG_DRIVE__W 3 +#define SIO_PDR_MD6_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD6_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD6_CFG_KEEP__B 6 +#define SIO_PDR_MD6_CFG_KEEP__W 2 +#define SIO_PDR_MD6_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD6_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD6_CFG_UIO__B 8 +#define SIO_PDR_MD6_CFG_UIO__W 1 +#define SIO_PDR_MD6_CFG_UIO__M 0x100 +#define SIO_PDR_MD6_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD7_CFG__A 0x7F0032 +#define SIO_PDR_MD7_CFG__W 9 +#define SIO_PDR_MD7_CFG__M 0x1FF +#define SIO_PDR_MD7_CFG__PRE 0x50 +#define SIO_PDR_MD7_CFG_MODE__B 0 +#define SIO_PDR_MD7_CFG_MODE__W 3 +#define SIO_PDR_MD7_CFG_MODE__M 0x7 +#define SIO_PDR_MD7_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD7_CFG_DRIVE__B 3 +#define SIO_PDR_MD7_CFG_DRIVE__W 3 +#define SIO_PDR_MD7_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD7_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD7_CFG_KEEP__B 6 +#define SIO_PDR_MD7_CFG_KEEP__W 2 +#define SIO_PDR_MD7_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD7_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD7_CFG_UIO__B 8 +#define SIO_PDR_MD7_CFG_UIO__W 1 +#define SIO_PDR_MD7_CFG_UIO__M 0x100 +#define SIO_PDR_MD7_CFG_UIO__PRE 0x0 + +#define SIO_PDR_I2C_SCL1_CFG__A 0x7F0033 +#define SIO_PDR_I2C_SCL1_CFG__W 9 +#define SIO_PDR_I2C_SCL1_CFG__M 0x1FF +#define SIO_PDR_I2C_SCL1_CFG__PRE 0x11 +#define SIO_PDR_I2C_SCL1_CFG_MODE__B 0 +#define SIO_PDR_I2C_SCL1_CFG_MODE__W 3 +#define SIO_PDR_I2C_SCL1_CFG_MODE__M 0x7 +#define SIO_PDR_I2C_SCL1_CFG_MODE__PRE 0x1 +#define SIO_PDR_I2C_SCL1_CFG_DRIVE__B 3 +#define SIO_PDR_I2C_SCL1_CFG_DRIVE__W 3 +#define SIO_PDR_I2C_SCL1_CFG_DRIVE__M 0x38 +#define SIO_PDR_I2C_SCL1_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_I2C_SCL1_CFG_KEEP__B 6 +#define SIO_PDR_I2C_SCL1_CFG_KEEP__W 2 +#define SIO_PDR_I2C_SCL1_CFG_KEEP__M 0xC0 +#define SIO_PDR_I2C_SCL1_CFG_KEEP__PRE 0x0 +#define SIO_PDR_I2C_SCL1_CFG_UIO__B 8 +#define SIO_PDR_I2C_SCL1_CFG_UIO__W 1 +#define SIO_PDR_I2C_SCL1_CFG_UIO__M 0x100 +#define SIO_PDR_I2C_SCL1_CFG_UIO__PRE 0x0 + +#define SIO_PDR_I2C_SDA1_CFG__A 0x7F0034 +#define SIO_PDR_I2C_SDA1_CFG__W 9 +#define SIO_PDR_I2C_SDA1_CFG__M 0x1FF +#define SIO_PDR_I2C_SDA1_CFG__PRE 0x11 +#define SIO_PDR_I2C_SDA1_CFG_MODE__B 0 +#define SIO_PDR_I2C_SDA1_CFG_MODE__W 3 +#define SIO_PDR_I2C_SDA1_CFG_MODE__M 0x7 +#define SIO_PDR_I2C_SDA1_CFG_MODE__PRE 0x1 +#define SIO_PDR_I2C_SDA1_CFG_DRIVE__B 3 +#define SIO_PDR_I2C_SDA1_CFG_DRIVE__W 3 +#define SIO_PDR_I2C_SDA1_CFG_DRIVE__M 0x38 +#define SIO_PDR_I2C_SDA1_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_I2C_SDA1_CFG_KEEP__B 6 +#define SIO_PDR_I2C_SDA1_CFG_KEEP__W 2 +#define SIO_PDR_I2C_SDA1_CFG_KEEP__M 0xC0 +#define SIO_PDR_I2C_SDA1_CFG_KEEP__PRE 0x0 +#define SIO_PDR_I2C_SDA1_CFG_UIO__B 8 +#define SIO_PDR_I2C_SDA1_CFG_UIO__W 1 +#define SIO_PDR_I2C_SDA1_CFG_UIO__M 0x100 +#define SIO_PDR_I2C_SDA1_CFG_UIO__PRE 0x0 + +#define SIO_PDR_VSYNC_CFG__A 0x7F0036 +#define SIO_PDR_VSYNC_CFG__W 9 +#define SIO_PDR_VSYNC_CFG__M 0x1FF +#define SIO_PDR_VSYNC_CFG__PRE 0x10 +#define SIO_PDR_VSYNC_CFG_MODE__B 0 +#define SIO_PDR_VSYNC_CFG_MODE__W 3 +#define SIO_PDR_VSYNC_CFG_MODE__M 0x7 +#define SIO_PDR_VSYNC_CFG_MODE__PRE 0x0 +#define SIO_PDR_VSYNC_CFG_DRIVE__B 3 +#define SIO_PDR_VSYNC_CFG_DRIVE__W 3 +#define SIO_PDR_VSYNC_CFG_DRIVE__M 0x38 +#define SIO_PDR_VSYNC_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_VSYNC_CFG_KEEP__B 6 +#define SIO_PDR_VSYNC_CFG_KEEP__W 2 +#define SIO_PDR_VSYNC_CFG_KEEP__M 0xC0 +#define SIO_PDR_VSYNC_CFG_KEEP__PRE 0x0 +#define SIO_PDR_VSYNC_CFG_UIO__B 8 +#define SIO_PDR_VSYNC_CFG_UIO__W 1 +#define SIO_PDR_VSYNC_CFG_UIO__M 0x100 +#define SIO_PDR_VSYNC_CFG_UIO__PRE 0x0 + +#define SIO_PDR_SMA_RX_CFG__A 0x7F0037 +#define SIO_PDR_SMA_RX_CFG__W 9 +#define SIO_PDR_SMA_RX_CFG__M 0x1FF +#define SIO_PDR_SMA_RX_CFG__PRE 0x10 +#define SIO_PDR_SMA_RX_CFG_MODE__B 0 +#define SIO_PDR_SMA_RX_CFG_MODE__W 3 +#define SIO_PDR_SMA_RX_CFG_MODE__M 0x7 +#define SIO_PDR_SMA_RX_CFG_MODE__PRE 0x0 +#define SIO_PDR_SMA_RX_CFG_DRIVE__B 3 +#define SIO_PDR_SMA_RX_CFG_DRIVE__W 3 +#define SIO_PDR_SMA_RX_CFG_DRIVE__M 0x38 +#define SIO_PDR_SMA_RX_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_SMA_RX_CFG_KEEP__B 6 +#define SIO_PDR_SMA_RX_CFG_KEEP__W 2 +#define SIO_PDR_SMA_RX_CFG_KEEP__M 0xC0 +#define SIO_PDR_SMA_RX_CFG_KEEP__PRE 0x0 +#define SIO_PDR_SMA_RX_CFG_UIO__B 8 +#define SIO_PDR_SMA_RX_CFG_UIO__W 1 +#define SIO_PDR_SMA_RX_CFG_UIO__M 0x100 +#define SIO_PDR_SMA_RX_CFG_UIO__PRE 0x0 + +#define SIO_PDR_SMA_TX_CFG__A 0x7F0038 +#define SIO_PDR_SMA_TX_CFG__W 9 +#define SIO_PDR_SMA_TX_CFG__M 0x1FF +#define SIO_PDR_SMA_TX_CFG__PRE 0x90 +#define SIO_PDR_SMA_TX_CFG_MODE__B 0 +#define SIO_PDR_SMA_TX_CFG_MODE__W 3 +#define SIO_PDR_SMA_TX_CFG_MODE__M 0x7 +#define SIO_PDR_SMA_TX_CFG_MODE__PRE 0x0 +#define SIO_PDR_SMA_TX_CFG_DRIVE__B 3 +#define SIO_PDR_SMA_TX_CFG_DRIVE__W 3 +#define SIO_PDR_SMA_TX_CFG_DRIVE__M 0x38 +#define SIO_PDR_SMA_TX_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_SMA_TX_CFG_KEEP__B 6 +#define SIO_PDR_SMA_TX_CFG_KEEP__W 2 +#define SIO_PDR_SMA_TX_CFG_KEEP__M 0xC0 +#define SIO_PDR_SMA_TX_CFG_KEEP__PRE 0x80 +#define SIO_PDR_SMA_TX_CFG_UIO__B 8 +#define SIO_PDR_SMA_TX_CFG_UIO__W 1 +#define SIO_PDR_SMA_TX_CFG_UIO__M 0x100 +#define SIO_PDR_SMA_TX_CFG_UIO__PRE 0x0 + +#define SIO_PDR_I2C_SDA2_CFG__A 0x7F003F +#define SIO_PDR_I2C_SDA2_CFG__W 9 +#define SIO_PDR_I2C_SDA2_CFG__M 0x1FF +#define SIO_PDR_I2C_SDA2_CFG__PRE 0x11 +#define SIO_PDR_I2C_SDA2_CFG_MODE__B 0 +#define SIO_PDR_I2C_SDA2_CFG_MODE__W 3 +#define SIO_PDR_I2C_SDA2_CFG_MODE__M 0x7 +#define SIO_PDR_I2C_SDA2_CFG_MODE__PRE 0x1 +#define SIO_PDR_I2C_SDA2_CFG_DRIVE__B 3 +#define SIO_PDR_I2C_SDA2_CFG_DRIVE__W 3 +#define SIO_PDR_I2C_SDA2_CFG_DRIVE__M 0x38 +#define SIO_PDR_I2C_SDA2_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_I2C_SDA2_CFG_KEEP__B 6 +#define SIO_PDR_I2C_SDA2_CFG_KEEP__W 2 +#define SIO_PDR_I2C_SDA2_CFG_KEEP__M 0xC0 +#define SIO_PDR_I2C_SDA2_CFG_KEEP__PRE 0x0 +#define SIO_PDR_I2C_SDA2_CFG_UIO__B 8 +#define SIO_PDR_I2C_SDA2_CFG_UIO__W 1 +#define SIO_PDR_I2C_SDA2_CFG_UIO__M 0x100 +#define SIO_PDR_I2C_SDA2_CFG_UIO__PRE 0x0 + +#define SIO_PDR_I2C_SCL2_CFG__A 0x7F0040 +#define SIO_PDR_I2C_SCL2_CFG__W 9 +#define SIO_PDR_I2C_SCL2_CFG__M 0x1FF +#define SIO_PDR_I2C_SCL2_CFG__PRE 0x11 +#define SIO_PDR_I2C_SCL2_CFG_MODE__B 0 +#define SIO_PDR_I2C_SCL2_CFG_MODE__W 3 +#define SIO_PDR_I2C_SCL2_CFG_MODE__M 0x7 +#define SIO_PDR_I2C_SCL2_CFG_MODE__PRE 0x1 +#define SIO_PDR_I2C_SCL2_CFG_DRIVE__B 3 +#define SIO_PDR_I2C_SCL2_CFG_DRIVE__W 3 +#define SIO_PDR_I2C_SCL2_CFG_DRIVE__M 0x38 +#define SIO_PDR_I2C_SCL2_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_I2C_SCL2_CFG_KEEP__B 6 +#define SIO_PDR_I2C_SCL2_CFG_KEEP__W 2 +#define SIO_PDR_I2C_SCL2_CFG_KEEP__M 0xC0 +#define SIO_PDR_I2C_SCL2_CFG_KEEP__PRE 0x0 +#define SIO_PDR_I2C_SCL2_CFG_UIO__B 8 +#define SIO_PDR_I2C_SCL2_CFG_UIO__W 1 +#define SIO_PDR_I2C_SCL2_CFG_UIO__M 0x100 +#define SIO_PDR_I2C_SCL2_CFG_UIO__PRE 0x0 + +#define SIO_PDR_I2S_CL_CFG__A 0x7F0041 +#define SIO_PDR_I2S_CL_CFG__W 9 +#define SIO_PDR_I2S_CL_CFG__M 0x1FF +#define SIO_PDR_I2S_CL_CFG__PRE 0x10 +#define SIO_PDR_I2S_CL_CFG_MODE__B 0 +#define SIO_PDR_I2S_CL_CFG_MODE__W 3 +#define SIO_PDR_I2S_CL_CFG_MODE__M 0x7 +#define SIO_PDR_I2S_CL_CFG_MODE__PRE 0x0 +#define SIO_PDR_I2S_CL_CFG_DRIVE__B 3 +#define SIO_PDR_I2S_CL_CFG_DRIVE__W 3 +#define SIO_PDR_I2S_CL_CFG_DRIVE__M 0x38 +#define SIO_PDR_I2S_CL_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_I2S_CL_CFG_KEEP__B 6 +#define SIO_PDR_I2S_CL_CFG_KEEP__W 2 +#define SIO_PDR_I2S_CL_CFG_KEEP__M 0xC0 +#define SIO_PDR_I2S_CL_CFG_KEEP__PRE 0x0 +#define SIO_PDR_I2S_CL_CFG_UIO__B 8 +#define SIO_PDR_I2S_CL_CFG_UIO__W 1 +#define SIO_PDR_I2S_CL_CFG_UIO__M 0x100 +#define SIO_PDR_I2S_CL_CFG_UIO__PRE 0x0 + +#define SIO_PDR_I2S_DA_CFG__A 0x7F0042 +#define SIO_PDR_I2S_DA_CFG__W 9 +#define SIO_PDR_I2S_DA_CFG__M 0x1FF +#define SIO_PDR_I2S_DA_CFG__PRE 0x10 +#define SIO_PDR_I2S_DA_CFG_MODE__B 0 +#define SIO_PDR_I2S_DA_CFG_MODE__W 3 +#define SIO_PDR_I2S_DA_CFG_MODE__M 0x7 +#define SIO_PDR_I2S_DA_CFG_MODE__PRE 0x0 +#define SIO_PDR_I2S_DA_CFG_DRIVE__B 3 +#define SIO_PDR_I2S_DA_CFG_DRIVE__W 3 +#define SIO_PDR_I2S_DA_CFG_DRIVE__M 0x38 +#define SIO_PDR_I2S_DA_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_I2S_DA_CFG_KEEP__B 6 +#define SIO_PDR_I2S_DA_CFG_KEEP__W 2 +#define SIO_PDR_I2S_DA_CFG_KEEP__M 0xC0 +#define SIO_PDR_I2S_DA_CFG_KEEP__PRE 0x0 +#define SIO_PDR_I2S_DA_CFG_UIO__B 8 +#define SIO_PDR_I2S_DA_CFG_UIO__W 1 +#define SIO_PDR_I2S_DA_CFG_UIO__M 0x100 +#define SIO_PDR_I2S_DA_CFG_UIO__PRE 0x0 + +#define SIO_PDR_GPIO_GPIO_FNC__A 0x7F0050 +#define SIO_PDR_GPIO_GPIO_FNC__W 2 +#define SIO_PDR_GPIO_GPIO_FNC__M 0x3 +#define SIO_PDR_GPIO_GPIO_FNC__PRE 0x0 +#define SIO_PDR_GPIO_GPIO_FNC_SEL__B 0 +#define SIO_PDR_GPIO_GPIO_FNC_SEL__W 2 +#define SIO_PDR_GPIO_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_GPIO_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_IRQN_GPIO_FNC__A 0x7F0051 +#define SIO_PDR_IRQN_GPIO_FNC__W 2 +#define SIO_PDR_IRQN_GPIO_FNC__M 0x3 +#define SIO_PDR_IRQN_GPIO_FNC__PRE 0x0 +#define SIO_PDR_IRQN_GPIO_FNC_SEL__B 0 +#define SIO_PDR_IRQN_GPIO_FNC_SEL__W 2 +#define SIO_PDR_IRQN_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_IRQN_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MSTRT_GPIO_FNC__A 0x7F0052 +#define SIO_PDR_MSTRT_GPIO_FNC__W 2 +#define SIO_PDR_MSTRT_GPIO_FNC__M 0x3 +#define SIO_PDR_MSTRT_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MSTRT_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MSTRT_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MSTRT_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MSTRT_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MERR_GPIO_FNC__A 0x7F0053 +#define SIO_PDR_MERR_GPIO_FNC__W 2 +#define SIO_PDR_MERR_GPIO_FNC__M 0x3 +#define SIO_PDR_MERR_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MERR_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MERR_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MERR_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MERR_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MCLK_GPIO_FNC__A 0x7F0054 +#define SIO_PDR_MCLK_GPIO_FNC__W 2 +#define SIO_PDR_MCLK_GPIO_FNC__M 0x3 +#define SIO_PDR_MCLK_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MCLK_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MCLK_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MCLK_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MCLK_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MVAL_GPIO_FNC__A 0x7F0055 +#define SIO_PDR_MVAL_GPIO_FNC__W 2 +#define SIO_PDR_MVAL_GPIO_FNC__M 0x3 +#define SIO_PDR_MVAL_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MVAL_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MVAL_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MVAL_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MVAL_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD0_GPIO_FNC__A 0x7F0056 +#define SIO_PDR_MD0_GPIO_FNC__W 2 +#define SIO_PDR_MD0_GPIO_FNC__M 0x3 +#define SIO_PDR_MD0_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD0_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD0_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD0_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD0_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD1_GPIO_FNC__A 0x7F0057 +#define SIO_PDR_MD1_GPIO_FNC__W 2 +#define SIO_PDR_MD1_GPIO_FNC__M 0x3 +#define SIO_PDR_MD1_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD1_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD1_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD1_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD1_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD2_GPIO_FNC__A 0x7F0058 +#define SIO_PDR_MD2_GPIO_FNC__W 2 +#define SIO_PDR_MD2_GPIO_FNC__M 0x3 +#define SIO_PDR_MD2_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD2_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD2_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD2_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD2_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD3_GPIO_FNC__A 0x7F0059 +#define SIO_PDR_MD3_GPIO_FNC__W 2 +#define SIO_PDR_MD3_GPIO_FNC__M 0x3 +#define SIO_PDR_MD3_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD3_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD3_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD3_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD3_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD4_GPIO_FNC__A 0x7F005A +#define SIO_PDR_MD4_GPIO_FNC__W 2 +#define SIO_PDR_MD4_GPIO_FNC__M 0x3 +#define SIO_PDR_MD4_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD4_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD4_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD4_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD4_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD5_GPIO_FNC__A 0x7F005B +#define SIO_PDR_MD5_GPIO_FNC__W 2 +#define SIO_PDR_MD5_GPIO_FNC__M 0x3 +#define SIO_PDR_MD5_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD5_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD5_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD5_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD5_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD6_GPIO_FNC__A 0x7F005C +#define SIO_PDR_MD6_GPIO_FNC__W 2 +#define SIO_PDR_MD6_GPIO_FNC__M 0x3 +#define SIO_PDR_MD6_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD6_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD6_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD6_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD6_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD7_GPIO_FNC__A 0x7F005D +#define SIO_PDR_MD7_GPIO_FNC__W 2 +#define SIO_PDR_MD7_GPIO_FNC__M 0x3 +#define SIO_PDR_MD7_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD7_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD7_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD7_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD7_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_SMA_RX_GPIO_FNC__A 0x7F005E +#define SIO_PDR_SMA_RX_GPIO_FNC__W 2 +#define SIO_PDR_SMA_RX_GPIO_FNC__M 0x3 +#define SIO_PDR_SMA_RX_GPIO_FNC__PRE 0x0 +#define SIO_PDR_SMA_RX_GPIO_FNC_SEL__B 0 +#define SIO_PDR_SMA_RX_GPIO_FNC_SEL__W 2 +#define SIO_PDR_SMA_RX_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_SMA_RX_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_SMA_TX_GPIO_FNC__A 0x7F005F +#define SIO_PDR_SMA_TX_GPIO_FNC__W 2 +#define SIO_PDR_SMA_TX_GPIO_FNC__M 0x3 +#define SIO_PDR_SMA_TX_GPIO_FNC__PRE 0x0 +#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__B 0 +#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__W 2 +#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__PRE 0x0 + + + + + + +#define VSB_COMM_EXEC__A 0x1C00000 +#define VSB_COMM_EXEC__W 2 +#define VSB_COMM_EXEC__M 0x3 +#define VSB_COMM_EXEC__PRE 0x0 +#define VSB_COMM_EXEC_STOP 0x0 +#define VSB_COMM_EXEC_ACTIVE 0x1 +#define VSB_COMM_EXEC_HOLD 0x2 + + +#define VSB_COMM_MB__A 0x1C00002 +#define VSB_COMM_MB__W 16 +#define VSB_COMM_MB__M 0xFFFF +#define VSB_COMM_MB__PRE 0x0 +#define VSB_COMM_INT_REQ__A 0x1C00003 +#define VSB_COMM_INT_REQ__W 1 +#define VSB_COMM_INT_REQ__M 0x1 +#define VSB_COMM_INT_REQ__PRE 0x0 + +#define VSB_COMM_INT_REQ_TOP_INT_REQ__B 0 +#define VSB_COMM_INT_REQ_TOP_INT_REQ__W 1 +#define VSB_COMM_INT_REQ_TOP_INT_REQ__M 0x1 +#define VSB_COMM_INT_REQ_TOP_INT_REQ__PRE 0x0 + + +#define VSB_COMM_INT_STA__A 0x1C00005 +#define VSB_COMM_INT_STA__W 16 +#define VSB_COMM_INT_STA__M 0xFFFF +#define VSB_COMM_INT_STA__PRE 0x0 + +#define VSB_COMM_INT_MSK__A 0x1C00006 +#define VSB_COMM_INT_MSK__W 16 +#define VSB_COMM_INT_MSK__M 0xFFFF +#define VSB_COMM_INT_MSK__PRE 0x0 + +#define VSB_COMM_INT_STM__A 0x1C00007 +#define VSB_COMM_INT_STM__W 16 +#define VSB_COMM_INT_STM__M 0xFFFF +#define VSB_COMM_INT_STM__PRE 0x0 + + + + +#define VSB_TOP_COMM_EXEC__A 0x1C10000 +#define VSB_TOP_COMM_EXEC__W 2 +#define VSB_TOP_COMM_EXEC__M 0x3 +#define VSB_TOP_COMM_EXEC__PRE 0x0 +#define VSB_TOP_COMM_EXEC_STOP 0x0 +#define VSB_TOP_COMM_EXEC_ACTIVE 0x1 +#define VSB_TOP_COMM_EXEC_HOLD 0x2 + +#define VSB_TOP_COMM_MB__A 0x1C10002 +#define VSB_TOP_COMM_MB__W 10 +#define VSB_TOP_COMM_MB__M 0x3FF +#define VSB_TOP_COMM_MB__PRE 0x0 + +#define VSB_TOP_COMM_MB_CTL__B 0 +#define VSB_TOP_COMM_MB_CTL__W 1 +#define VSB_TOP_COMM_MB_CTL__M 0x1 +#define VSB_TOP_COMM_MB_CTL__PRE 0x0 +#define VSB_TOP_COMM_MB_CTL_CTL_OFF 0x0 +#define VSB_TOP_COMM_MB_CTL_CTL_ON 0x1 + +#define VSB_TOP_COMM_MB_OBS__B 1 +#define VSB_TOP_COMM_MB_OBS__W 1 +#define VSB_TOP_COMM_MB_OBS__M 0x2 +#define VSB_TOP_COMM_MB_OBS__PRE 0x0 +#define VSB_TOP_COMM_MB_OBS_OBS_OFF 0x0 +#define VSB_TOP_COMM_MB_OBS_OBS_ON 0x2 + +#define VSB_TOP_COMM_MB_MUX_CTL__B 2 +#define VSB_TOP_COMM_MB_MUX_CTL__W 4 +#define VSB_TOP_COMM_MB_MUX_CTL__M 0x3C +#define VSB_TOP_COMM_MB_MUX_CTL__PRE 0x0 + +#define VSB_TOP_COMM_MB_MUX_OBS__B 6 +#define VSB_TOP_COMM_MB_MUX_OBS__W 4 +#define VSB_TOP_COMM_MB_MUX_OBS__M 0x3C0 +#define VSB_TOP_COMM_MB_MUX_OBS__PRE 0x0 +#define VSB_TOP_COMM_MB_MUX_OBS_VSB_FEC 0x0 +#define VSB_TOP_COMM_MB_MUX_OBS_VSB_IQM 0x40 +#define VSB_TOP_COMM_MB_MUX_OBS_VSB_IQM_AMPLITUDE 0x80 +#define VSB_TOP_COMM_MB_MUX_OBS_VSB_TCMEQ_1 0xC0 +#define VSB_TOP_COMM_MB_MUX_OBS_VSB_TCMEQ_2 0x100 +#define VSB_TOP_COMM_MB_MUX_OBS_VSB_FFE_1 0x140 +#define VSB_TOP_COMM_MB_MUX_OBS_VSB_FFE_2 0x180 +#define VSB_TOP_COMM_MB_MUX_OBS_VSB_DFE_1 0x1C0 +#define VSB_TOP_COMM_MB_MUX_OBS_VSB_DFE_2 0x200 + + +#define VSB_TOP_COMM_INT_REQ__A 0x1C10003 +#define VSB_TOP_COMM_INT_REQ__W 1 +#define VSB_TOP_COMM_INT_REQ__M 0x1 +#define VSB_TOP_COMM_INT_REQ__PRE 0x0 +#define VSB_TOP_COMM_INT_STA__A 0x1C10005 +#define VSB_TOP_COMM_INT_STA__W 6 +#define VSB_TOP_COMM_INT_STA__M 0x3F +#define VSB_TOP_COMM_INT_STA__PRE 0x0 + +#define VSB_TOP_COMM_INT_STA_FIELD_INT_STA__B 0 +#define VSB_TOP_COMM_INT_STA_FIELD_INT_STA__W 1 +#define VSB_TOP_COMM_INT_STA_FIELD_INT_STA__M 0x1 +#define VSB_TOP_COMM_INT_STA_FIELD_INT_STA__PRE 0x0 + +#define VSB_TOP_COMM_INT_STA_LOCK_STA__B 1 +#define VSB_TOP_COMM_INT_STA_LOCK_STA__W 1 +#define VSB_TOP_COMM_INT_STA_LOCK_STA__M 0x2 +#define VSB_TOP_COMM_INT_STA_LOCK_STA__PRE 0x0 + +#define VSB_TOP_COMM_INT_STA_UNLOCK_STA__B 2 +#define VSB_TOP_COMM_INT_STA_UNLOCK_STA__W 1 +#define VSB_TOP_COMM_INT_STA_UNLOCK_STA__M 0x4 +#define VSB_TOP_COMM_INT_STA_UNLOCK_STA__PRE 0x0 + +#define VSB_TOP_COMM_INT_STA_TAPREADER_STA__B 3 +#define VSB_TOP_COMM_INT_STA_TAPREADER_STA__W 1 +#define VSB_TOP_COMM_INT_STA_TAPREADER_STA__M 0x8 +#define VSB_TOP_COMM_INT_STA_TAPREADER_STA__PRE 0x0 + +#define VSB_TOP_COMM_INT_STA_SEGSYNCINTR_STA__B 4 +#define VSB_TOP_COMM_INT_STA_SEGSYNCINTR_STA__W 1 +#define VSB_TOP_COMM_INT_STA_SEGSYNCINTR_STA__M 0x10 +#define VSB_TOP_COMM_INT_STA_SEGSYNCINTR_STA__PRE 0x0 + +#define VSB_TOP_COMM_INT_STA_MERSER_STA__B 5 +#define VSB_TOP_COMM_INT_STA_MERSER_STA__W 1 +#define VSB_TOP_COMM_INT_STA_MERSER_STA__M 0x20 +#define VSB_TOP_COMM_INT_STA_MERSER_STA__PRE 0x0 + +#define VSB_TOP_COMM_INT_MSK__A 0x1C10006 +#define VSB_TOP_COMM_INT_MSK__W 6 +#define VSB_TOP_COMM_INT_MSK__M 0x3F +#define VSB_TOP_COMM_INT_MSK__PRE 0x0 + +#define VSB_TOP_COMM_INT_MSK_FIELD_INT_MSK__B 0 +#define VSB_TOP_COMM_INT_MSK_FIELD_INT_MSK__W 1 +#define VSB_TOP_COMM_INT_MSK_FIELD_INT_MSK__M 0x1 +#define VSB_TOP_COMM_INT_MSK_FIELD_INT_MSK__PRE 0x0 + +#define VSB_TOP_COMM_INT_MSK_LOCK_MSK__B 1 +#define VSB_TOP_COMM_INT_MSK_LOCK_MSK__W 1 +#define VSB_TOP_COMM_INT_MSK_LOCK_MSK__M 0x2 +#define VSB_TOP_COMM_INT_MSK_LOCK_MSK__PRE 0x0 + +#define VSB_TOP_COMM_INT_MSK_UNLOCK_MSK__B 2 +#define VSB_TOP_COMM_INT_MSK_UNLOCK_MSK__W 1 +#define VSB_TOP_COMM_INT_MSK_UNLOCK_MSK__M 0x4 +#define VSB_TOP_COMM_INT_MSK_UNLOCK_MSK__PRE 0x0 + +#define VSB_TOP_COMM_INT_MSK_TAPREADER_MSK__B 3 +#define VSB_TOP_COMM_INT_MSK_TAPREADER_MSK__W 1 +#define VSB_TOP_COMM_INT_MSK_TAPREADER_MSK__M 0x8 +#define VSB_TOP_COMM_INT_MSK_TAPREADER_MSK__PRE 0x0 + +#define VSB_TOP_COMM_INT_MSK_SEGSYNCINTR_MSK__B 4 +#define VSB_TOP_COMM_INT_MSK_SEGSYNCINTR_MSK__W 1 +#define VSB_TOP_COMM_INT_MSK_SEGSYNCINTR_MSK__M 0x10 +#define VSB_TOP_COMM_INT_MSK_SEGSYNCINTR_MSK__PRE 0x0 + +#define VSB_TOP_COMM_INT_MSK_MERSER_MSK__B 5 +#define VSB_TOP_COMM_INT_MSK_MERSER_MSK__W 1 +#define VSB_TOP_COMM_INT_MSK_MERSER_MSK__M 0x20 +#define VSB_TOP_COMM_INT_MSK_MERSER_MSK__PRE 0x0 + +#define VSB_TOP_COMM_INT_STM__A 0x1C10007 +#define VSB_TOP_COMM_INT_STM__W 6 +#define VSB_TOP_COMM_INT_STM__M 0x3F +#define VSB_TOP_COMM_INT_STM__PRE 0x0 + +#define VSB_TOP_COMM_INT_STM_FIELD_INT_STM__B 0 +#define VSB_TOP_COMM_INT_STM_FIELD_INT_STM__W 1 +#define VSB_TOP_COMM_INT_STM_FIELD_INT_STM__M 0x1 +#define VSB_TOP_COMM_INT_STM_FIELD_INT_STM__PRE 0x0 + +#define VSB_TOP_COMM_INT_STM_LOCK_STM__B 1 +#define VSB_TOP_COMM_INT_STM_LOCK_STM__W 1 +#define VSB_TOP_COMM_INT_STM_LOCK_STM__M 0x2 +#define VSB_TOP_COMM_INT_STM_LOCK_STM__PRE 0x0 + +#define VSB_TOP_COMM_INT_STM_UNLOCK_STM__B 2 +#define VSB_TOP_COMM_INT_STM_UNLOCK_STM__W 1 +#define VSB_TOP_COMM_INT_STM_UNLOCK_STM__M 0x4 +#define VSB_TOP_COMM_INT_STM_UNLOCK_STM__PRE 0x0 + +#define VSB_TOP_COMM_INT_STM_TAPREADER_STM__B 3 +#define VSB_TOP_COMM_INT_STM_TAPREADER_STM__W 1 +#define VSB_TOP_COMM_INT_STM_TAPREADER_STM__M 0x8 +#define VSB_TOP_COMM_INT_STM_TAPREADER_STM__PRE 0x0 + +#define VSB_TOP_COMM_INT_STM_SEGSYNCINTR_STM__B 4 +#define VSB_TOP_COMM_INT_STM_SEGSYNCINTR_STM__W 1 +#define VSB_TOP_COMM_INT_STM_SEGSYNCINTR_STM__M 0x10 +#define VSB_TOP_COMM_INT_STM_SEGSYNCINTR_STM__PRE 0x0 + +#define VSB_TOP_COMM_INT_STM_MERSER_STM__B 5 +#define VSB_TOP_COMM_INT_STM_MERSER_STM__W 1 +#define VSB_TOP_COMM_INT_STM_MERSER_STM__M 0x20 +#define VSB_TOP_COMM_INT_STM_MERSER_STM__PRE 0x0 + + +#define VSB_TOP_CKGN1ACQ__A 0x1C10010 +#define VSB_TOP_CKGN1ACQ__W 8 +#define VSB_TOP_CKGN1ACQ__M 0xFF +#define VSB_TOP_CKGN1ACQ__PRE 0x4 + +#define VSB_TOP_CKGN1TRK__A 0x1C10011 +#define VSB_TOP_CKGN1TRK__W 8 +#define VSB_TOP_CKGN1TRK__M 0xFF +#define VSB_TOP_CKGN1TRK__PRE 0x0 + +#define VSB_TOP_CKGN2ACQ__A 0x1C10012 +#define VSB_TOP_CKGN2ACQ__W 8 +#define VSB_TOP_CKGN2ACQ__M 0xFF +#define VSB_TOP_CKGN2ACQ__PRE 0x2 + +#define VSB_TOP_CKGN2TRK__A 0x1C10013 +#define VSB_TOP_CKGN2TRK__W 8 +#define VSB_TOP_CKGN2TRK__M 0xFF +#define VSB_TOP_CKGN2TRK__PRE 0x1 + +#define VSB_TOP_CKGN3__A 0x1C10014 +#define VSB_TOP_CKGN3__W 8 +#define VSB_TOP_CKGN3__M 0xFF +#define VSB_TOP_CKGN3__PRE 0x5 + +#define VSB_TOP_CYGN1ACQ__A 0x1C10015 +#define VSB_TOP_CYGN1ACQ__W 8 +#define VSB_TOP_CYGN1ACQ__M 0xFF +#define VSB_TOP_CYGN1ACQ__PRE 0x3 + +#define VSB_TOP_CYGN1TRK__A 0x1C10016 +#define VSB_TOP_CYGN1TRK__W 8 +#define VSB_TOP_CYGN1TRK__M 0xFF +#define VSB_TOP_CYGN1TRK__PRE 0x0 + +#define VSB_TOP_CYGN2ACQ__A 0x1C10017 +#define VSB_TOP_CYGN2ACQ__W 8 +#define VSB_TOP_CYGN2ACQ__M 0xFF +#define VSB_TOP_CYGN2ACQ__PRE 0x3 + +#define VSB_TOP_CYGN2TRK__A 0x1C10018 +#define VSB_TOP_CYGN2TRK__W 8 +#define VSB_TOP_CYGN2TRK__M 0xFF +#define VSB_TOP_CYGN2TRK__PRE 0x2 + +#define VSB_TOP_CYGN3__A 0x1C10019 +#define VSB_TOP_CYGN3__W 8 +#define VSB_TOP_CYGN3__M 0xFF +#define VSB_TOP_CYGN3__PRE 0x6 +#define VSB_TOP_SYNCCTRLWORD__A 0x1C1001A +#define VSB_TOP_SYNCCTRLWORD__W 5 +#define VSB_TOP_SYNCCTRLWORD__M 0x1F +#define VSB_TOP_SYNCCTRLWORD__PRE 0x0 + +#define VSB_TOP_SYNCCTRLWORD_PRST__B 0 +#define VSB_TOP_SYNCCTRLWORD_PRST__W 1 +#define VSB_TOP_SYNCCTRLWORD_PRST__M 0x1 +#define VSB_TOP_SYNCCTRLWORD_PRST__PRE 0x0 + +#define VSB_TOP_SYNCCTRLWORD_DCFREEZ__B 1 +#define VSB_TOP_SYNCCTRLWORD_DCFREEZ__W 1 +#define VSB_TOP_SYNCCTRLWORD_DCFREEZ__M 0x2 +#define VSB_TOP_SYNCCTRLWORD_DCFREEZ__PRE 0x0 + +#define VSB_TOP_SYNCCTRLWORD_INVCNST__B 2 +#define VSB_TOP_SYNCCTRLWORD_INVCNST__W 1 +#define VSB_TOP_SYNCCTRLWORD_INVCNST__M 0x4 +#define VSB_TOP_SYNCCTRLWORD_INVCNST__PRE 0x0 + +#define VSB_TOP_SYNCCTRLWORD_CPUAGCRST__B 3 +#define VSB_TOP_SYNCCTRLWORD_CPUAGCRST__W 1 +#define VSB_TOP_SYNCCTRLWORD_CPUAGCRST__M 0x8 +#define VSB_TOP_SYNCCTRLWORD_CPUAGCRST__PRE 0x0 + +#define VSB_TOP_SYNCCTRLWORD_AGCIGNOREFS__B 4 +#define VSB_TOP_SYNCCTRLWORD_AGCIGNOREFS__W 1 +#define VSB_TOP_SYNCCTRLWORD_AGCIGNOREFS__M 0x10 +#define VSB_TOP_SYNCCTRLWORD_AGCIGNOREFS__PRE 0x0 + + +#define VSB_TOP_MAINSMUP__A 0x1C1001B +#define VSB_TOP_MAINSMUP__W 8 +#define VSB_TOP_MAINSMUP__M 0xFF +#define VSB_TOP_MAINSMUP__PRE 0xFF + +#define VSB_TOP_EQSMUP__A 0x1C1001C +#define VSB_TOP_EQSMUP__W 8 +#define VSB_TOP_EQSMUP__M 0xFF +#define VSB_TOP_EQSMUP__PRE 0xFF +#define VSB_TOP_SYSMUXCTRL__A 0x1C1001D +#define VSB_TOP_SYSMUXCTRL__W 13 +#define VSB_TOP_SYSMUXCTRL__M 0x1FFF +#define VSB_TOP_SYSMUXCTRL__PRE 0x0 + +#define VSB_TOP_SYSMUXCTRL_CYLK_STATIC__B 0 +#define VSB_TOP_SYSMUXCTRL_CYLK_STATIC__W 1 +#define VSB_TOP_SYSMUXCTRL_CYLK_STATIC__M 0x1 +#define VSB_TOP_SYSMUXCTRL_CYLK_STATIC__PRE 0x0 + +#define VSB_TOP_SYSMUXCTRL_CYLK_SEL_STATIC__B 1 +#define VSB_TOP_SYSMUXCTRL_CYLK_SEL_STATIC__W 1 +#define VSB_TOP_SYSMUXCTRL_CYLK_SEL_STATIC__M 0x2 +#define VSB_TOP_SYSMUXCTRL_CYLK_SEL_STATIC__PRE 0x0 + +#define VSB_TOP_SYSMUXCTRL_CTCALDONE_STATIC__B 2 +#define VSB_TOP_SYSMUXCTRL_CTCALDONE_STATIC__W 1 +#define VSB_TOP_SYSMUXCTRL_CTCALDONE_STATIC__M 0x4 +#define VSB_TOP_SYSMUXCTRL_CTCALDONE_STATIC__PRE 0x0 + +#define VSB_TOP_SYSMUXCTRL_CTCALDONE_SEL_STATIC__B 3 +#define VSB_TOP_SYSMUXCTRL_CTCALDONE_SEL_STATIC__W 1 +#define VSB_TOP_SYSMUXCTRL_CTCALDONE_SEL_STATIC__M 0x8 +#define VSB_TOP_SYSMUXCTRL_CTCALDONE_SEL_STATIC__PRE 0x0 + +#define VSB_TOP_SYSMUXCTRL_FRAMELOCK_STATIC__B 4 +#define VSB_TOP_SYSMUXCTRL_FRAMELOCK_STATIC__W 1 +#define VSB_TOP_SYSMUXCTRL_FRAMELOCK_STATIC__M 0x10 +#define VSB_TOP_SYSMUXCTRL_FRAMELOCK_STATIC__PRE 0x0 + +#define VSB_TOP_SYSMUXCTRL_FRAMELOCK_SEL_STATIC__B 5 +#define VSB_TOP_SYSMUXCTRL_FRAMELOCK_SEL_STATIC__W 1 +#define VSB_TOP_SYSMUXCTRL_FRAMELOCK_SEL_STATIC__M 0x20 +#define VSB_TOP_SYSMUXCTRL_FRAMELOCK_SEL_STATIC__PRE 0x0 + +#define VSB_TOP_SYSMUXCTRL_FRAMESYNC_STATIC__B 6 +#define VSB_TOP_SYSMUXCTRL_FRAMESYNC_STATIC__W 1 +#define VSB_TOP_SYSMUXCTRL_FRAMESYNC_STATIC__M 0x40 +#define VSB_TOP_SYSMUXCTRL_FRAMESYNC_STATIC__PRE 0x0 + +#define VSB_TOP_SYSMUXCTRL_FRAMESYNC_SEL_STATIC__B 7 +#define VSB_TOP_SYSMUXCTRL_FRAMESYNC_SEL_STATIC__W 1 +#define VSB_TOP_SYSMUXCTRL_FRAMESYNC_SEL_STATIC__M 0x80 +#define VSB_TOP_SYSMUXCTRL_FRAMESYNC_SEL_STATIC__PRE 0x0 + +#define VSB_TOP_SYSMUXCTRL_SNROVTH_STATIC__B 8 +#define VSB_TOP_SYSMUXCTRL_SNROVTH_STATIC__W 4 +#define VSB_TOP_SYSMUXCTRL_SNROVTH_STATIC__M 0xF00 +#define VSB_TOP_SYSMUXCTRL_SNROVTH_STATIC__PRE 0x0 + +#define VSB_TOP_SYSMUXCTRL_SNROVTH_SEL_STATIC__B 12 +#define VSB_TOP_SYSMUXCTRL_SNROVTH_SEL_STATIC__W 1 +#define VSB_TOP_SYSMUXCTRL_SNROVTH_SEL_STATIC__M 0x1000 +#define VSB_TOP_SYSMUXCTRL_SNROVTH_SEL_STATIC__PRE 0x0 + +#define VSB_TOP_SNRTH_RCA1__A 0x1C1001E +#define VSB_TOP_SNRTH_RCA1__W 8 +#define VSB_TOP_SNRTH_RCA1__M 0xFF +#define VSB_TOP_SNRTH_RCA1__PRE 0x53 + +#define VSB_TOP_SNRTH_RCA1_DN__B 0 +#define VSB_TOP_SNRTH_RCA1_DN__W 4 +#define VSB_TOP_SNRTH_RCA1_DN__M 0xF +#define VSB_TOP_SNRTH_RCA1_DN__PRE 0x3 + +#define VSB_TOP_SNRTH_RCA1_UP__B 4 +#define VSB_TOP_SNRTH_RCA1_UP__W 4 +#define VSB_TOP_SNRTH_RCA1_UP__M 0xF0 +#define VSB_TOP_SNRTH_RCA1_UP__PRE 0x50 + +#define VSB_TOP_SNRTH_RCA2__A 0x1C1001F +#define VSB_TOP_SNRTH_RCA2__W 8 +#define VSB_TOP_SNRTH_RCA2__M 0xFF +#define VSB_TOP_SNRTH_RCA2__PRE 0x75 + +#define VSB_TOP_SNRTH_RCA2_DN__B 0 +#define VSB_TOP_SNRTH_RCA2_DN__W 4 +#define VSB_TOP_SNRTH_RCA2_DN__M 0xF +#define VSB_TOP_SNRTH_RCA2_DN__PRE 0x5 + +#define VSB_TOP_SNRTH_RCA2_UP__B 4 +#define VSB_TOP_SNRTH_RCA2_UP__W 4 +#define VSB_TOP_SNRTH_RCA2_UP__M 0xF0 +#define VSB_TOP_SNRTH_RCA2_UP__PRE 0x70 + +#define VSB_TOP_SNRTH_DDM1__A 0x1C10020 +#define VSB_TOP_SNRTH_DDM1__W 8 +#define VSB_TOP_SNRTH_DDM1__M 0xFF +#define VSB_TOP_SNRTH_DDM1__PRE 0xCA + +#define VSB_TOP_SNRTH_DDM1_DN__B 0 +#define VSB_TOP_SNRTH_DDM1_DN__W 4 +#define VSB_TOP_SNRTH_DDM1_DN__M 0xF +#define VSB_TOP_SNRTH_DDM1_DN__PRE 0xA + +#define VSB_TOP_SNRTH_DDM1_UP__B 4 +#define VSB_TOP_SNRTH_DDM1_UP__W 4 +#define VSB_TOP_SNRTH_DDM1_UP__M 0xF0 +#define VSB_TOP_SNRTH_DDM1_UP__PRE 0xC0 + +#define VSB_TOP_SNRTH_DDM2__A 0x1C10021 +#define VSB_TOP_SNRTH_DDM2__W 8 +#define VSB_TOP_SNRTH_DDM2__M 0xFF +#define VSB_TOP_SNRTH_DDM2__PRE 0xCA + +#define VSB_TOP_SNRTH_DDM2_DN__B 0 +#define VSB_TOP_SNRTH_DDM2_DN__W 4 +#define VSB_TOP_SNRTH_DDM2_DN__M 0xF +#define VSB_TOP_SNRTH_DDM2_DN__PRE 0xA + +#define VSB_TOP_SNRTH_DDM2_UP__B 4 +#define VSB_TOP_SNRTH_DDM2_UP__W 4 +#define VSB_TOP_SNRTH_DDM2_UP__M 0xF0 +#define VSB_TOP_SNRTH_DDM2_UP__PRE 0xC0 + +#define VSB_TOP_SNRTH_PT__A 0x1C10022 +#define VSB_TOP_SNRTH_PT__W 8 +#define VSB_TOP_SNRTH_PT__M 0xFF +#define VSB_TOP_SNRTH_PT__PRE 0xD8 + +#define VSB_TOP_SNRTH_PT_DN__B 0 +#define VSB_TOP_SNRTH_PT_DN__W 4 +#define VSB_TOP_SNRTH_PT_DN__M 0xF +#define VSB_TOP_SNRTH_PT_DN__PRE 0x8 + +#define VSB_TOP_SNRTH_PT_UP__B 4 +#define VSB_TOP_SNRTH_PT_UP__W 4 +#define VSB_TOP_SNRTH_PT_UP__M 0xF0 +#define VSB_TOP_SNRTH_PT_UP__PRE 0xD0 + +#define VSB_TOP_CYSMSTATES__A 0x1C10023 +#define VSB_TOP_CYSMSTATES__W 8 +#define VSB_TOP_CYSMSTATES__M 0xFF +#define VSB_TOP_CYSMSTATES__PRE 0x0 + +#define VSB_TOP_CYSMSTATES_SYSST__B 0 +#define VSB_TOP_CYSMSTATES_SYSST__W 4 +#define VSB_TOP_CYSMSTATES_SYSST__M 0xF +#define VSB_TOP_CYSMSTATES_SYSST__PRE 0x0 + +#define VSB_TOP_CYSMSTATES_EQST__B 4 +#define VSB_TOP_CYSMSTATES_EQST__W 4 +#define VSB_TOP_CYSMSTATES_EQST__M 0xF0 +#define VSB_TOP_CYSMSTATES_EQST__PRE 0x0 + +#define VSB_TOP_SMALL_NOTCH_CONTROL__A 0x1C10024 +#define VSB_TOP_SMALL_NOTCH_CONTROL__W 8 +#define VSB_TOP_SMALL_NOTCH_CONTROL__M 0xFF +#define VSB_TOP_SMALL_NOTCH_CONTROL__PRE 0x0 + +#define VSB_TOP_SMALL_NOTCH_CONTROL_GO__B 0 +#define VSB_TOP_SMALL_NOTCH_CONTROL_GO__W 1 +#define VSB_TOP_SMALL_NOTCH_CONTROL_GO__M 0x1 +#define VSB_TOP_SMALL_NOTCH_CONTROL_GO__PRE 0x0 + +#define VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS1__B 1 +#define VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS1__W 1 +#define VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS1__M 0x2 +#define VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS1__PRE 0x0 + +#define VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS2__B 2 +#define VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS2__W 1 +#define VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS2__M 0x4 +#define VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS2__PRE 0x0 + +#define VSB_TOP_SMALL_NOTCH_CONTROL_SPARE__B 3 +#define VSB_TOP_SMALL_NOTCH_CONTROL_SPARE__W 4 +#define VSB_TOP_SMALL_NOTCH_CONTROL_SPARE__M 0x78 +#define VSB_TOP_SMALL_NOTCH_CONTROL_SPARE__PRE 0x0 + +#define VSB_TOP_SMALL_NOTCH_CONTROL_SOFT_RESET__B 7 +#define VSB_TOP_SMALL_NOTCH_CONTROL_SOFT_RESET__W 1 +#define VSB_TOP_SMALL_NOTCH_CONTROL_SOFT_RESET__M 0x80 +#define VSB_TOP_SMALL_NOTCH_CONTROL_SOFT_RESET__PRE 0x0 + + +#define VSB_TOP_TAPREADCYC__A 0x1C10025 +#define VSB_TOP_TAPREADCYC__W 9 +#define VSB_TOP_TAPREADCYC__M 0x1FF +#define VSB_TOP_TAPREADCYC__PRE 0x1 + +#define VSB_TOP_VALIDPKLVL__A 0x1C10026 +#define VSB_TOP_VALIDPKLVL__W 13 +#define VSB_TOP_VALIDPKLVL__M 0x1FFF +#define VSB_TOP_VALIDPKLVL__PRE 0x100 + +#define VSB_TOP_CENTROID_FINE_DELAY__A 0x1C10027 +#define VSB_TOP_CENTROID_FINE_DELAY__W 10 +#define VSB_TOP_CENTROID_FINE_DELAY__M 0x3FF +#define VSB_TOP_CENTROID_FINE_DELAY__PRE 0xFF + +#define VSB_TOP_CENTROID_SMACH_DELAY__A 0x1C10028 +#define VSB_TOP_CENTROID_SMACH_DELAY__W 10 +#define VSB_TOP_CENTROID_SMACH_DELAY__M 0x3FF +#define VSB_TOP_CENTROID_SMACH_DELAY__PRE 0x1FF + +#define VSB_TOP_SNR__A 0x1C10029 +#define VSB_TOP_SNR__W 14 +#define VSB_TOP_SNR__M 0x3FFF +#define VSB_TOP_SNR__PRE 0x0 +#define VSB_TOP_LOCKSTATUS__A 0x1C1002A +#define VSB_TOP_LOCKSTATUS__W 7 +#define VSB_TOP_LOCKSTATUS__M 0x7F +#define VSB_TOP_LOCKSTATUS__PRE 0x0 + +#define VSB_TOP_LOCKSTATUS_VSBMODE__B 0 +#define VSB_TOP_LOCKSTATUS_VSBMODE__W 4 +#define VSB_TOP_LOCKSTATUS_VSBMODE__M 0xF +#define VSB_TOP_LOCKSTATUS_VSBMODE__PRE 0x0 + +#define VSB_TOP_LOCKSTATUS_FRMLOCK__B 4 +#define VSB_TOP_LOCKSTATUS_FRMLOCK__W 1 +#define VSB_TOP_LOCKSTATUS_FRMLOCK__M 0x10 +#define VSB_TOP_LOCKSTATUS_FRMLOCK__PRE 0x0 + +#define VSB_TOP_LOCKSTATUS_CYLOCK__B 5 +#define VSB_TOP_LOCKSTATUS_CYLOCK__W 1 +#define VSB_TOP_LOCKSTATUS_CYLOCK__M 0x20 +#define VSB_TOP_LOCKSTATUS_CYLOCK__PRE 0x0 + +#define VSB_TOP_LOCKSTATUS_DDMON__B 6 +#define VSB_TOP_LOCKSTATUS_DDMON__W 1 +#define VSB_TOP_LOCKSTATUS_DDMON__M 0x40 +#define VSB_TOP_LOCKSTATUS_DDMON__PRE 0x0 + + +#define VSB_TOP_CTST__A 0x1C1002B +#define VSB_TOP_CTST__W 4 +#define VSB_TOP_CTST__M 0xF +#define VSB_TOP_CTST__PRE 0x0 +#define VSB_TOP_EQSMRSTCTRL__A 0x1C1002C +#define VSB_TOP_EQSMRSTCTRL__W 7 +#define VSB_TOP_EQSMRSTCTRL__M 0x7F +#define VSB_TOP_EQSMRSTCTRL__PRE 0x0 + +#define VSB_TOP_EQSMRSTCTRL_RCAON__B 0 +#define VSB_TOP_EQSMRSTCTRL_RCAON__W 1 +#define VSB_TOP_EQSMRSTCTRL_RCAON__M 0x1 +#define VSB_TOP_EQSMRSTCTRL_RCAON__PRE 0x0 + +#define VSB_TOP_EQSMRSTCTRL_DFEON__B 1 +#define VSB_TOP_EQSMRSTCTRL_DFEON__W 1 +#define VSB_TOP_EQSMRSTCTRL_DFEON__M 0x2 +#define VSB_TOP_EQSMRSTCTRL_DFEON__PRE 0x0 + +#define VSB_TOP_EQSMRSTCTRL_DDMEN1__B 2 +#define VSB_TOP_EQSMRSTCTRL_DDMEN1__W 1 +#define VSB_TOP_EQSMRSTCTRL_DDMEN1__M 0x4 +#define VSB_TOP_EQSMRSTCTRL_DDMEN1__PRE 0x0 + +#define VSB_TOP_EQSMRSTCTRL_DDMEN2__B 3 +#define VSB_TOP_EQSMRSTCTRL_DDMEN2__W 1 +#define VSB_TOP_EQSMRSTCTRL_DDMEN2__M 0x8 +#define VSB_TOP_EQSMRSTCTRL_DDMEN2__PRE 0x0 + +#define VSB_TOP_EQSMRSTCTRL_DIGIAGCON__B 4 +#define VSB_TOP_EQSMRSTCTRL_DIGIAGCON__W 1 +#define VSB_TOP_EQSMRSTCTRL_DIGIAGCON__M 0x10 +#define VSB_TOP_EQSMRSTCTRL_DIGIAGCON__PRE 0x0 + +#define VSB_TOP_EQSMRSTCTRL_PARAINITEN__B 5 +#define VSB_TOP_EQSMRSTCTRL_PARAINITEN__W 1 +#define VSB_TOP_EQSMRSTCTRL_PARAINITEN__M 0x20 +#define VSB_TOP_EQSMRSTCTRL_PARAINITEN__PRE 0x0 + +#define VSB_TOP_EQSMRSTCTRL_TIMEOUTFRMCNTEN__B 6 +#define VSB_TOP_EQSMRSTCTRL_TIMEOUTFRMCNTEN__W 1 +#define VSB_TOP_EQSMRSTCTRL_TIMEOUTFRMCNTEN__M 0x40 +#define VSB_TOP_EQSMRSTCTRL_TIMEOUTFRMCNTEN__PRE 0x0 + +#define VSB_TOP_EQSMTRNCTRL__A 0x1C1002D +#define VSB_TOP_EQSMTRNCTRL__W 7 +#define VSB_TOP_EQSMTRNCTRL__M 0x7F +#define VSB_TOP_EQSMTRNCTRL__PRE 0x40 + +#define VSB_TOP_EQSMTRNCTRL_RCAON__B 0 +#define VSB_TOP_EQSMTRNCTRL_RCAON__W 1 +#define VSB_TOP_EQSMTRNCTRL_RCAON__M 0x1 +#define VSB_TOP_EQSMTRNCTRL_RCAON__PRE 0x0 + +#define VSB_TOP_EQSMTRNCTRL_DFEON__B 1 +#define VSB_TOP_EQSMTRNCTRL_DFEON__W 1 +#define VSB_TOP_EQSMTRNCTRL_DFEON__M 0x2 +#define VSB_TOP_EQSMTRNCTRL_DFEON__PRE 0x0 + +#define VSB_TOP_EQSMTRNCTRL_DDMEN1__B 2 +#define VSB_TOP_EQSMTRNCTRL_DDMEN1__W 1 +#define VSB_TOP_EQSMTRNCTRL_DDMEN1__M 0x4 +#define VSB_TOP_EQSMTRNCTRL_DDMEN1__PRE 0x0 + +#define VSB_TOP_EQSMTRNCTRL_DDMEN2__B 3 +#define VSB_TOP_EQSMTRNCTRL_DDMEN2__W 1 +#define VSB_TOP_EQSMTRNCTRL_DDMEN2__M 0x8 +#define VSB_TOP_EQSMTRNCTRL_DDMEN2__PRE 0x0 + +#define VSB_TOP_EQSMTRNCTRL_DIGIAGCON__B 4 +#define VSB_TOP_EQSMTRNCTRL_DIGIAGCON__W 1 +#define VSB_TOP_EQSMTRNCTRL_DIGIAGCON__M 0x10 +#define VSB_TOP_EQSMTRNCTRL_DIGIAGCON__PRE 0x0 + +#define VSB_TOP_EQSMTRNCTRL_PARAINITEN__B 5 +#define VSB_TOP_EQSMTRNCTRL_PARAINITEN__W 1 +#define VSB_TOP_EQSMTRNCTRL_PARAINITEN__M 0x20 +#define VSB_TOP_EQSMTRNCTRL_PARAINITEN__PRE 0x0 + +#define VSB_TOP_EQSMTRNCTRL_TIMEOUTFRMCNTEN__B 6 +#define VSB_TOP_EQSMTRNCTRL_TIMEOUTFRMCNTEN__W 1 +#define VSB_TOP_EQSMTRNCTRL_TIMEOUTFRMCNTEN__M 0x40 +#define VSB_TOP_EQSMTRNCTRL_TIMEOUTFRMCNTEN__PRE 0x40 + +#define VSB_TOP_EQSMRCA1CTRL__A 0x1C1002E +#define VSB_TOP_EQSMRCA1CTRL__W 7 +#define VSB_TOP_EQSMRCA1CTRL__M 0x7F +#define VSB_TOP_EQSMRCA1CTRL__PRE 0x1 + +#define VSB_TOP_EQSMRCA1CTRL_RCAON__B 0 +#define VSB_TOP_EQSMRCA1CTRL_RCAON__W 1 +#define VSB_TOP_EQSMRCA1CTRL_RCAON__M 0x1 +#define VSB_TOP_EQSMRCA1CTRL_RCAON__PRE 0x1 + +#define VSB_TOP_EQSMRCA1CTRL_DFEON__B 1 +#define VSB_TOP_EQSMRCA1CTRL_DFEON__W 1 +#define VSB_TOP_EQSMRCA1CTRL_DFEON__M 0x2 +#define VSB_TOP_EQSMRCA1CTRL_DFEON__PRE 0x0 + +#define VSB_TOP_EQSMRCA1CTRL_DDMEN1__B 2 +#define VSB_TOP_EQSMRCA1CTRL_DDMEN1__W 1 +#define VSB_TOP_EQSMRCA1CTRL_DDMEN1__M 0x4 +#define VSB_TOP_EQSMRCA1CTRL_DDMEN1__PRE 0x0 + +#define VSB_TOP_EQSMRCA1CTRL_DDMEN2__B 3 +#define VSB_TOP_EQSMRCA1CTRL_DDMEN2__W 1 +#define VSB_TOP_EQSMRCA1CTRL_DDMEN2__M 0x8 +#define VSB_TOP_EQSMRCA1CTRL_DDMEN2__PRE 0x0 + +#define VSB_TOP_EQSMRCA1CTRL_DIGIAGCON__B 4 +#define VSB_TOP_EQSMRCA1CTRL_DIGIAGCON__W 1 +#define VSB_TOP_EQSMRCA1CTRL_DIGIAGCON__M 0x10 +#define VSB_TOP_EQSMRCA1CTRL_DIGIAGCON__PRE 0x0 + +#define VSB_TOP_EQSMRCA1CTRL_PARAINITEN__B 5 +#define VSB_TOP_EQSMRCA1CTRL_PARAINITEN__W 1 +#define VSB_TOP_EQSMRCA1CTRL_PARAINITEN__M 0x20 +#define VSB_TOP_EQSMRCA1CTRL_PARAINITEN__PRE 0x0 + +#define VSB_TOP_EQSMRCA1CTRL_TIMEOUTFRMCNTEN__B 6 +#define VSB_TOP_EQSMRCA1CTRL_TIMEOUTFRMCNTEN__W 1 +#define VSB_TOP_EQSMRCA1CTRL_TIMEOUTFRMCNTEN__M 0x40 +#define VSB_TOP_EQSMRCA1CTRL_TIMEOUTFRMCNTEN__PRE 0x0 + +#define VSB_TOP_EQSMRCA2CTRL__A 0x1C1002F +#define VSB_TOP_EQSMRCA2CTRL__W 7 +#define VSB_TOP_EQSMRCA2CTRL__M 0x7F +#define VSB_TOP_EQSMRCA2CTRL__PRE 0x3 + +#define VSB_TOP_EQSMRCA2CTRL_RCAON__B 0 +#define VSB_TOP_EQSMRCA2CTRL_RCAON__W 1 +#define VSB_TOP_EQSMRCA2CTRL_RCAON__M 0x1 +#define VSB_TOP_EQSMRCA2CTRL_RCAON__PRE 0x1 + +#define VSB_TOP_EQSMRCA2CTRL_DFEON__B 1 +#define VSB_TOP_EQSMRCA2CTRL_DFEON__W 1 +#define VSB_TOP_EQSMRCA2CTRL_DFEON__M 0x2 +#define VSB_TOP_EQSMRCA2CTRL_DFEON__PRE 0x2 + +#define VSB_TOP_EQSMRCA2CTRL_DDMEN1__B 2 +#define VSB_TOP_EQSMRCA2CTRL_DDMEN1__W 1 +#define VSB_TOP_EQSMRCA2CTRL_DDMEN1__M 0x4 +#define VSB_TOP_EQSMRCA2CTRL_DDMEN1__PRE 0x0 + +#define VSB_TOP_EQSMRCA2CTRL_DDMEN2__B 3 +#define VSB_TOP_EQSMRCA2CTRL_DDMEN2__W 1 +#define VSB_TOP_EQSMRCA2CTRL_DDMEN2__M 0x8 +#define VSB_TOP_EQSMRCA2CTRL_DDMEN2__PRE 0x0 + +#define VSB_TOP_EQSMRCA2CTRL_DIGIAGCON__B 4 +#define VSB_TOP_EQSMRCA2CTRL_DIGIAGCON__W 1 +#define VSB_TOP_EQSMRCA2CTRL_DIGIAGCON__M 0x10 +#define VSB_TOP_EQSMRCA2CTRL_DIGIAGCON__PRE 0x0 + +#define VSB_TOP_EQSMRCA2CTRL_PARAINITEN__B 5 +#define VSB_TOP_EQSMRCA2CTRL_PARAINITEN__W 1 +#define VSB_TOP_EQSMRCA2CTRL_PARAINITEN__M 0x20 +#define VSB_TOP_EQSMRCA2CTRL_PARAINITEN__PRE 0x0 + +#define VSB_TOP_EQSMRCA2CTRL_TIMEOUTFRMCNTEN__B 6 +#define VSB_TOP_EQSMRCA2CTRL_TIMEOUTFRMCNTEN__W 1 +#define VSB_TOP_EQSMRCA2CTRL_TIMEOUTFRMCNTEN__M 0x40 +#define VSB_TOP_EQSMRCA2CTRL_TIMEOUTFRMCNTEN__PRE 0x0 + +#define VSB_TOP_EQSMDDM1CTRL__A 0x1C10030 +#define VSB_TOP_EQSMDDM1CTRL__W 7 +#define VSB_TOP_EQSMDDM1CTRL__M 0x7F +#define VSB_TOP_EQSMDDM1CTRL__PRE 0x6 + +#define VSB_TOP_EQSMDDM1CTRL_RCAON__B 0 +#define VSB_TOP_EQSMDDM1CTRL_RCAON__W 1 +#define VSB_TOP_EQSMDDM1CTRL_RCAON__M 0x1 +#define VSB_TOP_EQSMDDM1CTRL_RCAON__PRE 0x0 + +#define VSB_TOP_EQSMDDM1CTRL_DFEON__B 1 +#define VSB_TOP_EQSMDDM1CTRL_DFEON__W 1 +#define VSB_TOP_EQSMDDM1CTRL_DFEON__M 0x2 +#define VSB_TOP_EQSMDDM1CTRL_DFEON__PRE 0x2 + +#define VSB_TOP_EQSMDDM1CTRL_DDMEN1__B 2 +#define VSB_TOP_EQSMDDM1CTRL_DDMEN1__W 1 +#define VSB_TOP_EQSMDDM1CTRL_DDMEN1__M 0x4 +#define VSB_TOP_EQSMDDM1CTRL_DDMEN1__PRE 0x4 + +#define VSB_TOP_EQSMDDM1CTRL_DDMEN2__B 3 +#define VSB_TOP_EQSMDDM1CTRL_DDMEN2__W 1 +#define VSB_TOP_EQSMDDM1CTRL_DDMEN2__M 0x8 +#define VSB_TOP_EQSMDDM1CTRL_DDMEN2__PRE 0x0 + +#define VSB_TOP_EQSMDDM1CTRL_DIGIAGCON__B 4 +#define VSB_TOP_EQSMDDM1CTRL_DIGIAGCON__W 1 +#define VSB_TOP_EQSMDDM1CTRL_DIGIAGCON__M 0x10 +#define VSB_TOP_EQSMDDM1CTRL_DIGIAGCON__PRE 0x0 + +#define VSB_TOP_EQSMDDM1CTRL_PARAINITEN__B 5 +#define VSB_TOP_EQSMDDM1CTRL_PARAINITEN__W 1 +#define VSB_TOP_EQSMDDM1CTRL_PARAINITEN__M 0x20 +#define VSB_TOP_EQSMDDM1CTRL_PARAINITEN__PRE 0x0 + +#define VSB_TOP_EQSMDDM1CTRL_TIMEOUTFRMCNTEN__B 6 +#define VSB_TOP_EQSMDDM1CTRL_TIMEOUTFRMCNTEN__W 1 +#define VSB_TOP_EQSMDDM1CTRL_TIMEOUTFRMCNTEN__M 0x40 +#define VSB_TOP_EQSMDDM1CTRL_TIMEOUTFRMCNTEN__PRE 0x0 + +#define VSB_TOP_EQSMDDM2CTRL__A 0x1C10031 +#define VSB_TOP_EQSMDDM2CTRL__W 7 +#define VSB_TOP_EQSMDDM2CTRL__M 0x7F +#define VSB_TOP_EQSMDDM2CTRL__PRE 0x1E + +#define VSB_TOP_EQSMDDM2CTRL_RCAON__B 0 +#define VSB_TOP_EQSMDDM2CTRL_RCAON__W 1 +#define VSB_TOP_EQSMDDM2CTRL_RCAON__M 0x1 +#define VSB_TOP_EQSMDDM2CTRL_RCAON__PRE 0x0 + +#define VSB_TOP_EQSMDDM2CTRL_DFEON__B 1 +#define VSB_TOP_EQSMDDM2CTRL_DFEON__W 1 +#define VSB_TOP_EQSMDDM2CTRL_DFEON__M 0x2 +#define VSB_TOP_EQSMDDM2CTRL_DFEON__PRE 0x2 + +#define VSB_TOP_EQSMDDM2CTRL_DDMEN1__B 2 +#define VSB_TOP_EQSMDDM2CTRL_DDMEN1__W 1 +#define VSB_TOP_EQSMDDM2CTRL_DDMEN1__M 0x4 +#define VSB_TOP_EQSMDDM2CTRL_DDMEN1__PRE 0x4 + +#define VSB_TOP_EQSMDDM2CTRL_DDMEN2__B 3 +#define VSB_TOP_EQSMDDM2CTRL_DDMEN2__W 1 +#define VSB_TOP_EQSMDDM2CTRL_DDMEN2__M 0x8 +#define VSB_TOP_EQSMDDM2CTRL_DDMEN2__PRE 0x8 + +#define VSB_TOP_EQSMDDM2CTRL_DIGIAGCON__B 4 +#define VSB_TOP_EQSMDDM2CTRL_DIGIAGCON__W 1 +#define VSB_TOP_EQSMDDM2CTRL_DIGIAGCON__M 0x10 +#define VSB_TOP_EQSMDDM2CTRL_DIGIAGCON__PRE 0x10 + +#define VSB_TOP_EQSMDDM2CTRL_PARAINITEN__B 5 +#define VSB_TOP_EQSMDDM2CTRL_PARAINITEN__W 1 +#define VSB_TOP_EQSMDDM2CTRL_PARAINITEN__M 0x20 +#define VSB_TOP_EQSMDDM2CTRL_PARAINITEN__PRE 0x0 + +#define VSB_TOP_EQSMDDM2CTRL_TIMEOUTFRMCNTEN__B 6 +#define VSB_TOP_EQSMDDM2CTRL_TIMEOUTFRMCNTEN__W 1 +#define VSB_TOP_EQSMDDM2CTRL_TIMEOUTFRMCNTEN__M 0x40 +#define VSB_TOP_EQSMDDM2CTRL_TIMEOUTFRMCNTEN__PRE 0x0 + +#define VSB_TOP_SYSSMRSTCTRL__A 0x1C10032 +#define VSB_TOP_SYSSMRSTCTRL__W 11 +#define VSB_TOP_SYSSMRSTCTRL__M 0x7FF +#define VSB_TOP_SYSSMRSTCTRL__PRE 0x7F9 + +#define VSB_TOP_SYSSMRSTCTRL_RSTCTCAL__B 0 +#define VSB_TOP_SYSSMRSTCTRL_RSTCTCAL__W 1 +#define VSB_TOP_SYSSMRSTCTRL_RSTCTCAL__M 0x1 +#define VSB_TOP_SYSSMRSTCTRL_RSTCTCAL__PRE 0x1 + +#define VSB_TOP_SYSSMRSTCTRL_CTCALEN__B 1 +#define VSB_TOP_SYSSMRSTCTRL_CTCALEN__W 1 +#define VSB_TOP_SYSSMRSTCTRL_CTCALEN__M 0x2 +#define VSB_TOP_SYSSMRSTCTRL_CTCALEN__PRE 0x0 + +#define VSB_TOP_SYSSMRSTCTRL_STARTTRN__B 2 +#define VSB_TOP_SYSSMRSTCTRL_STARTTRN__W 1 +#define VSB_TOP_SYSSMRSTCTRL_STARTTRN__M 0x4 +#define VSB_TOP_SYSSMRSTCTRL_STARTTRN__PRE 0x0 + +#define VSB_TOP_SYSSMRSTCTRL_RSTFRMSYNCDET__B 3 +#define VSB_TOP_SYSSMRSTCTRL_RSTFRMSYNCDET__W 1 +#define VSB_TOP_SYSSMRSTCTRL_RSTFRMSYNCDET__M 0x8 +#define VSB_TOP_SYSSMRSTCTRL_RSTFRMSYNCDET__PRE 0x8 + +#define VSB_TOP_SYSSMRSTCTRL_RSTCYDET__B 4 +#define VSB_TOP_SYSSMRSTCTRL_RSTCYDET__W 1 +#define VSB_TOP_SYSSMRSTCTRL_RSTCYDET__M 0x10 +#define VSB_TOP_SYSSMRSTCTRL_RSTCYDET__PRE 0x10 + +#define VSB_TOP_SYSSMRSTCTRL_RSTDCRMV__B 5 +#define VSB_TOP_SYSSMRSTCTRL_RSTDCRMV__W 1 +#define VSB_TOP_SYSSMRSTCTRL_RSTDCRMV__M 0x20 +#define VSB_TOP_SYSSMRSTCTRL_RSTDCRMV__PRE 0x20 + +#define VSB_TOP_SYSSMRSTCTRL_RSTEQSIG__B 6 +#define VSB_TOP_SYSSMRSTCTRL_RSTEQSIG__W 1 +#define VSB_TOP_SYSSMRSTCTRL_RSTEQSIG__M 0x40 +#define VSB_TOP_SYSSMRSTCTRL_RSTEQSIG__PRE 0x40 + +#define VSB_TOP_SYSSMRSTCTRL_CKFRZ__B 7 +#define VSB_TOP_SYSSMRSTCTRL_CKFRZ__W 1 +#define VSB_TOP_SYSSMRSTCTRL_CKFRZ__M 0x80 +#define VSB_TOP_SYSSMRSTCTRL_CKFRZ__PRE 0x80 + +#define VSB_TOP_SYSSMRSTCTRL_CKBWSW__B 8 +#define VSB_TOP_SYSSMRSTCTRL_CKBWSW__W 1 +#define VSB_TOP_SYSSMRSTCTRL_CKBWSW__M 0x100 +#define VSB_TOP_SYSSMRSTCTRL_CKBWSW__PRE 0x100 + +#define VSB_TOP_SYSSMRSTCTRL_NCOBWSW__B 9 +#define VSB_TOP_SYSSMRSTCTRL_NCOBWSW__W 1 +#define VSB_TOP_SYSSMRSTCTRL_NCOBWSW__M 0x200 +#define VSB_TOP_SYSSMRSTCTRL_NCOBWSW__PRE 0x200 + +#define VSB_TOP_SYSSMRSTCTRL_NCOTIMEOUTCNTEN__B 10 +#define VSB_TOP_SYSSMRSTCTRL_NCOTIMEOUTCNTEN__W 1 +#define VSB_TOP_SYSSMRSTCTRL_NCOTIMEOUTCNTEN__M 0x400 +#define VSB_TOP_SYSSMRSTCTRL_NCOTIMEOUTCNTEN__PRE 0x400 + +#define VSB_TOP_SYSSMCYCTRL__A 0x1C10033 +#define VSB_TOP_SYSSMCYCTRL__W 11 +#define VSB_TOP_SYSSMCYCTRL__M 0x7FF +#define VSB_TOP_SYSSMCYCTRL__PRE 0x4E9 + +#define VSB_TOP_SYSSMCYCTRL_RSTCTCAL__B 0 +#define VSB_TOP_SYSSMCYCTRL_RSTCTCAL__W 1 +#define VSB_TOP_SYSSMCYCTRL_RSTCTCAL__M 0x1 +#define VSB_TOP_SYSSMCYCTRL_RSTCTCAL__PRE 0x1 + +#define VSB_TOP_SYSSMCYCTRL_CTCALEN__B 1 +#define VSB_TOP_SYSSMCYCTRL_CTCALEN__W 1 +#define VSB_TOP_SYSSMCYCTRL_CTCALEN__M 0x2 +#define VSB_TOP_SYSSMCYCTRL_CTCALEN__PRE 0x0 + +#define VSB_TOP_SYSSMCYCTRL_STARTTRN__B 2 +#define VSB_TOP_SYSSMCYCTRL_STARTTRN__W 1 +#define VSB_TOP_SYSSMCYCTRL_STARTTRN__M 0x4 +#define VSB_TOP_SYSSMCYCTRL_STARTTRN__PRE 0x0 + +#define VSB_TOP_SYSSMCYCTRL_RSTFRMSYNCDET__B 3 +#define VSB_TOP_SYSSMCYCTRL_RSTFRMSYNCDET__W 1 +#define VSB_TOP_SYSSMCYCTRL_RSTFRMSYNCDET__M 0x8 +#define VSB_TOP_SYSSMCYCTRL_RSTFRMSYNCDET__PRE 0x8 + +#define VSB_TOP_SYSSMCYCTRL_RSTCYDET__B 4 +#define VSB_TOP_SYSSMCYCTRL_RSTCYDET__W 1 +#define VSB_TOP_SYSSMCYCTRL_RSTCYDET__M 0x10 +#define VSB_TOP_SYSSMCYCTRL_RSTCYDET__PRE 0x0 + +#define VSB_TOP_SYSSMCYCTRL_RSTDCRMV__B 5 +#define VSB_TOP_SYSSMCYCTRL_RSTDCRMV__W 1 +#define VSB_TOP_SYSSMCYCTRL_RSTDCRMV__M 0x20 +#define VSB_TOP_SYSSMCYCTRL_RSTDCRMV__PRE 0x20 + +#define VSB_TOP_SYSSMCYCTRL_RSTEQSIG__B 6 +#define VSB_TOP_SYSSMCYCTRL_RSTEQSIG__W 1 +#define VSB_TOP_SYSSMCYCTRL_RSTEQSIG__M 0x40 +#define VSB_TOP_SYSSMCYCTRL_RSTEQSIG__PRE 0x40 + +#define VSB_TOP_SYSSMCYCTRL_CKFRZ__B 7 +#define VSB_TOP_SYSSMCYCTRL_CKFRZ__W 1 +#define VSB_TOP_SYSSMCYCTRL_CKFRZ__M 0x80 +#define VSB_TOP_SYSSMCYCTRL_CKFRZ__PRE 0x80 + +#define VSB_TOP_SYSSMCYCTRL_CKBWSW__B 8 +#define VSB_TOP_SYSSMCYCTRL_CKBWSW__W 1 +#define VSB_TOP_SYSSMCYCTRL_CKBWSW__M 0x100 +#define VSB_TOP_SYSSMCYCTRL_CKBWSW__PRE 0x0 + +#define VSB_TOP_SYSSMCYCTRL_NCOBWSW__B 9 +#define VSB_TOP_SYSSMCYCTRL_NCOBWSW__W 1 +#define VSB_TOP_SYSSMCYCTRL_NCOBWSW__M 0x200 +#define VSB_TOP_SYSSMCYCTRL_NCOBWSW__PRE 0x0 + +#define VSB_TOP_SYSSMCYCTRL_NCOTIMEOUTCNTEN__B 10 +#define VSB_TOP_SYSSMCYCTRL_NCOTIMEOUTCNTEN__W 1 +#define VSB_TOP_SYSSMCYCTRL_NCOTIMEOUTCNTEN__M 0x400 +#define VSB_TOP_SYSSMCYCTRL_NCOTIMEOUTCNTEN__PRE 0x400 + +#define VSB_TOP_SYSSMTRNCTRL__A 0x1C10034 +#define VSB_TOP_SYSSMTRNCTRL__W 11 +#define VSB_TOP_SYSSMTRNCTRL__M 0x7FF +#define VSB_TOP_SYSSMTRNCTRL__PRE 0x204 + +#define VSB_TOP_SYSSMTRNCTRL_RSTCTCAL__B 0 +#define VSB_TOP_SYSSMTRNCTRL_RSTCTCAL__W 1 +#define VSB_TOP_SYSSMTRNCTRL_RSTCTCAL__M 0x1 +#define VSB_TOP_SYSSMTRNCTRL_RSTCTCAL__PRE 0x0 + +#define VSB_TOP_SYSSMTRNCTRL_CTCALEN__B 1 +#define VSB_TOP_SYSSMTRNCTRL_CTCALEN__W 1 +#define VSB_TOP_SYSSMTRNCTRL_CTCALEN__M 0x2 +#define VSB_TOP_SYSSMTRNCTRL_CTCALEN__PRE 0x0 + +#define VSB_TOP_SYSSMTRNCTRL_STARTTRN__B 2 +#define VSB_TOP_SYSSMTRNCTRL_STARTTRN__W 1 +#define VSB_TOP_SYSSMTRNCTRL_STARTTRN__M 0x4 +#define VSB_TOP_SYSSMTRNCTRL_STARTTRN__PRE 0x4 + +#define VSB_TOP_SYSSMTRNCTRL_RSTFRMSYNCDET__B 3 +#define VSB_TOP_SYSSMTRNCTRL_RSTFRMSYNCDET__W 1 +#define VSB_TOP_SYSSMTRNCTRL_RSTFRMSYNCDET__M 0x8 +#define VSB_TOP_SYSSMTRNCTRL_RSTFRMSYNCDET__PRE 0x0 + +#define VSB_TOP_SYSSMTRNCTRL_RSTCYDET__B 4 +#define VSB_TOP_SYSSMTRNCTRL_RSTCYDET__W 1 +#define VSB_TOP_SYSSMTRNCTRL_RSTCYDET__M 0x10 +#define VSB_TOP_SYSSMTRNCTRL_RSTCYDET__PRE 0x0 + +#define VSB_TOP_SYSSMTRNCTRL_RSTDCRMV__B 5 +#define VSB_TOP_SYSSMTRNCTRL_RSTDCRMV__W 1 +#define VSB_TOP_SYSSMTRNCTRL_RSTDCRMV__M 0x20 +#define VSB_TOP_SYSSMTRNCTRL_RSTDCRMV__PRE 0x0 + +#define VSB_TOP_SYSSMTRNCTRL_RSTEQSIG__B 6 +#define VSB_TOP_SYSSMTRNCTRL_RSTEQSIG__W 1 +#define VSB_TOP_SYSSMTRNCTRL_RSTEQSIG__M 0x40 +#define VSB_TOP_SYSSMTRNCTRL_RSTEQSIG__PRE 0x0 + +#define VSB_TOP_SYSSMTRNCTRL_CKFRZ__B 7 +#define VSB_TOP_SYSSMTRNCTRL_CKFRZ__W 1 +#define VSB_TOP_SYSSMTRNCTRL_CKFRZ__M 0x80 +#define VSB_TOP_SYSSMTRNCTRL_CKFRZ__PRE 0x0 + +#define VSB_TOP_SYSSMTRNCTRL_CKBWSW__B 8 +#define VSB_TOP_SYSSMTRNCTRL_CKBWSW__W 1 +#define VSB_TOP_SYSSMTRNCTRL_CKBWSW__M 0x100 +#define VSB_TOP_SYSSMTRNCTRL_CKBWSW__PRE 0x0 + +#define VSB_TOP_SYSSMTRNCTRL_NCOBWSW__B 9 +#define VSB_TOP_SYSSMTRNCTRL_NCOBWSW__W 1 +#define VSB_TOP_SYSSMTRNCTRL_NCOBWSW__M 0x200 +#define VSB_TOP_SYSSMTRNCTRL_NCOBWSW__PRE 0x200 + +#define VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__B 10 +#define VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__W 1 +#define VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__M 0x400 +#define VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__PRE 0x0 + +#define VSB_TOP_SYSSMEQCTRL__A 0x1C10035 +#define VSB_TOP_SYSSMEQCTRL__W 11 +#define VSB_TOP_SYSSMEQCTRL__M 0x7FF +#define VSB_TOP_SYSSMEQCTRL__PRE 0x304 + +#define VSB_TOP_SYSSMEQCTRL_RSTCTCAL__B 0 +#define VSB_TOP_SYSSMEQCTRL_RSTCTCAL__W 1 +#define VSB_TOP_SYSSMEQCTRL_RSTCTCAL__M 0x1 +#define VSB_TOP_SYSSMEQCTRL_RSTCTCAL__PRE 0x0 + +#define VSB_TOP_SYSSMEQCTRL_CTCALEN__B 1 +#define VSB_TOP_SYSSMEQCTRL_CTCALEN__W 1 +#define VSB_TOP_SYSSMEQCTRL_CTCALEN__M 0x2 +#define VSB_TOP_SYSSMEQCTRL_CTCALEN__PRE 0x0 + +#define VSB_TOP_SYSSMEQCTRL_STARTTRN__B 2 +#define VSB_TOP_SYSSMEQCTRL_STARTTRN__W 1 +#define VSB_TOP_SYSSMEQCTRL_STARTTRN__M 0x4 +#define VSB_TOP_SYSSMEQCTRL_STARTTRN__PRE 0x4 + +#define VSB_TOP_SYSSMEQCTRL_RSTFRMSYNCDET__B 3 +#define VSB_TOP_SYSSMEQCTRL_RSTFRMSYNCDET__W 1 +#define VSB_TOP_SYSSMEQCTRL_RSTFRMSYNCDET__M 0x8 +#define VSB_TOP_SYSSMEQCTRL_RSTFRMSYNCDET__PRE 0x0 + +#define VSB_TOP_SYSSMEQCTRL_RSTCYDET__B 4 +#define VSB_TOP_SYSSMEQCTRL_RSTCYDET__W 1 +#define VSB_TOP_SYSSMEQCTRL_RSTCYDET__M 0x10 +#define VSB_TOP_SYSSMEQCTRL_RSTCYDET__PRE 0x0 + +#define VSB_TOP_SYSSMEQCTRL_RSTDCRMV__B 5 +#define VSB_TOP_SYSSMEQCTRL_RSTDCRMV__W 1 +#define VSB_TOP_SYSSMEQCTRL_RSTDCRMV__M 0x20 +#define VSB_TOP_SYSSMEQCTRL_RSTDCRMV__PRE 0x0 + +#define VSB_TOP_SYSSMEQCTRL_RSTEQSIG__B 6 +#define VSB_TOP_SYSSMEQCTRL_RSTEQSIG__W 1 +#define VSB_TOP_SYSSMEQCTRL_RSTEQSIG__M 0x40 +#define VSB_TOP_SYSSMEQCTRL_RSTEQSIG__PRE 0x0 + +#define VSB_TOP_SYSSMEQCTRL_CKFRZ__B 7 +#define VSB_TOP_SYSSMEQCTRL_CKFRZ__W 1 +#define VSB_TOP_SYSSMEQCTRL_CKFRZ__M 0x80 +#define VSB_TOP_SYSSMEQCTRL_CKFRZ__PRE 0x0 + +#define VSB_TOP_SYSSMEQCTRL_CKBWSW__B 8 +#define VSB_TOP_SYSSMEQCTRL_CKBWSW__W 1 +#define VSB_TOP_SYSSMEQCTRL_CKBWSW__M 0x100 +#define VSB_TOP_SYSSMEQCTRL_CKBWSW__PRE 0x100 + +#define VSB_TOP_SYSSMEQCTRL_NCOBWSW__B 9 +#define VSB_TOP_SYSSMEQCTRL_NCOBWSW__W 1 +#define VSB_TOP_SYSSMEQCTRL_NCOBWSW__M 0x200 +#define VSB_TOP_SYSSMEQCTRL_NCOBWSW__PRE 0x200 + +#define VSB_TOP_SYSSMEQCTRL_NCOTIMEOUTCNTEN__B 10 +#define VSB_TOP_SYSSMEQCTRL_NCOTIMEOUTCNTEN__W 1 +#define VSB_TOP_SYSSMEQCTRL_NCOTIMEOUTCNTEN__M 0x400 +#define VSB_TOP_SYSSMEQCTRL_NCOTIMEOUTCNTEN__PRE 0x0 + +#define VSB_TOP_SYSSMAGCCTRL__A 0x1C10036 +#define VSB_TOP_SYSSMAGCCTRL__W 11 +#define VSB_TOP_SYSSMAGCCTRL__M 0x7FF +#define VSB_TOP_SYSSMAGCCTRL__PRE 0xF9 + +#define VSB_TOP_SYSSMAGCCTRL_RSTCTCAL__B 0 +#define VSB_TOP_SYSSMAGCCTRL_RSTCTCAL__W 1 +#define VSB_TOP_SYSSMAGCCTRL_RSTCTCAL__M 0x1 +#define VSB_TOP_SYSSMAGCCTRL_RSTCTCAL__PRE 0x1 + +#define VSB_TOP_SYSSMAGCCTRL_CTCALEN__B 1 +#define VSB_TOP_SYSSMAGCCTRL_CTCALEN__W 1 +#define VSB_TOP_SYSSMAGCCTRL_CTCALEN__M 0x2 +#define VSB_TOP_SYSSMAGCCTRL_CTCALEN__PRE 0x0 + +#define VSB_TOP_SYSSMAGCCTRL_STARTTRN__B 2 +#define VSB_TOP_SYSSMAGCCTRL_STARTTRN__W 1 +#define VSB_TOP_SYSSMAGCCTRL_STARTTRN__M 0x4 +#define VSB_TOP_SYSSMAGCCTRL_STARTTRN__PRE 0x0 + +#define VSB_TOP_SYSSMAGCCTRL_RSTFRMSYNCDET__B 3 +#define VSB_TOP_SYSSMAGCCTRL_RSTFRMSYNCDET__W 1 +#define VSB_TOP_SYSSMAGCCTRL_RSTFRMSYNCDET__M 0x8 +#define VSB_TOP_SYSSMAGCCTRL_RSTFRMSYNCDET__PRE 0x8 + +#define VSB_TOP_SYSSMAGCCTRL_RSTCYDET__B 4 +#define VSB_TOP_SYSSMAGCCTRL_RSTCYDET__W 1 +#define VSB_TOP_SYSSMAGCCTRL_RSTCYDET__M 0x10 +#define VSB_TOP_SYSSMAGCCTRL_RSTCYDET__PRE 0x10 + +#define VSB_TOP_SYSSMAGCCTRL_RSTDCRMV__B 5 +#define VSB_TOP_SYSSMAGCCTRL_RSTDCRMV__W 1 +#define VSB_TOP_SYSSMAGCCTRL_RSTDCRMV__M 0x20 +#define VSB_TOP_SYSSMAGCCTRL_RSTDCRMV__PRE 0x20 + +#define VSB_TOP_SYSSMAGCCTRL_RSTEQSIG__B 6 +#define VSB_TOP_SYSSMAGCCTRL_RSTEQSIG__W 1 +#define VSB_TOP_SYSSMAGCCTRL_RSTEQSIG__M 0x40 +#define VSB_TOP_SYSSMAGCCTRL_RSTEQSIG__PRE 0x40 + +#define VSB_TOP_SYSSMAGCCTRL_CKFRZ__B 7 +#define VSB_TOP_SYSSMAGCCTRL_CKFRZ__W 1 +#define VSB_TOP_SYSSMAGCCTRL_CKFRZ__M 0x80 +#define VSB_TOP_SYSSMAGCCTRL_CKFRZ__PRE 0x80 + +#define VSB_TOP_SYSSMAGCCTRL_CKBWSW__B 8 +#define VSB_TOP_SYSSMAGCCTRL_CKBWSW__W 1 +#define VSB_TOP_SYSSMAGCCTRL_CKBWSW__M 0x100 +#define VSB_TOP_SYSSMAGCCTRL_CKBWSW__PRE 0x0 + +#define VSB_TOP_SYSSMAGCCTRL_NCOBWSW__B 9 +#define VSB_TOP_SYSSMAGCCTRL_NCOBWSW__W 1 +#define VSB_TOP_SYSSMAGCCTRL_NCOBWSW__M 0x200 +#define VSB_TOP_SYSSMAGCCTRL_NCOBWSW__PRE 0x0 + +#define VSB_TOP_SYSSMAGCCTRL_NCOTIMEOUTCNTEN__B 10 +#define VSB_TOP_SYSSMAGCCTRL_NCOTIMEOUTCNTEN__W 1 +#define VSB_TOP_SYSSMAGCCTRL_NCOTIMEOUTCNTEN__M 0x400 +#define VSB_TOP_SYSSMAGCCTRL_NCOTIMEOUTCNTEN__PRE 0x0 + +#define VSB_TOP_SYSSMCTCTRL__A 0x1C10037 +#define VSB_TOP_SYSSMCTCTRL__W 11 +#define VSB_TOP_SYSSMCTCTRL__M 0x7FF +#define VSB_TOP_SYSSMCTCTRL__PRE 0x4A + +#define VSB_TOP_SYSSMCTCTRL_RSTCTCAL__B 0 +#define VSB_TOP_SYSSMCTCTRL_RSTCTCAL__W 1 +#define VSB_TOP_SYSSMCTCTRL_RSTCTCAL__M 0x1 +#define VSB_TOP_SYSSMCTCTRL_RSTCTCAL__PRE 0x0 + +#define VSB_TOP_SYSSMCTCTRL_CTCALEN__B 1 +#define VSB_TOP_SYSSMCTCTRL_CTCALEN__W 1 +#define VSB_TOP_SYSSMCTCTRL_CTCALEN__M 0x2 +#define VSB_TOP_SYSSMCTCTRL_CTCALEN__PRE 0x2 + +#define VSB_TOP_SYSSMCTCTRL_STARTTRN__B 2 +#define VSB_TOP_SYSSMCTCTRL_STARTTRN__W 1 +#define VSB_TOP_SYSSMCTCTRL_STARTTRN__M 0x4 +#define VSB_TOP_SYSSMCTCTRL_STARTTRN__PRE 0x0 + +#define VSB_TOP_SYSSMCTCTRL_RSTFRMSYNCDET__B 3 +#define VSB_TOP_SYSSMCTCTRL_RSTFRMSYNCDET__W 1 +#define VSB_TOP_SYSSMCTCTRL_RSTFRMSYNCDET__M 0x8 +#define VSB_TOP_SYSSMCTCTRL_RSTFRMSYNCDET__PRE 0x8 + +#define VSB_TOP_SYSSMCTCTRL_RSTCYDET__B 4 +#define VSB_TOP_SYSSMCTCTRL_RSTCYDET__W 1 +#define VSB_TOP_SYSSMCTCTRL_RSTCYDET__M 0x10 +#define VSB_TOP_SYSSMCTCTRL_RSTCYDET__PRE 0x0 + +#define VSB_TOP_SYSSMCTCTRL_RSTDCRMV__B 5 +#define VSB_TOP_SYSSMCTCTRL_RSTDCRMV__W 1 +#define VSB_TOP_SYSSMCTCTRL_RSTDCRMV__M 0x20 +#define VSB_TOP_SYSSMCTCTRL_RSTDCRMV__PRE 0x0 + +#define VSB_TOP_SYSSMCTCTRL_RSTEQSIG__B 6 +#define VSB_TOP_SYSSMCTCTRL_RSTEQSIG__W 1 +#define VSB_TOP_SYSSMCTCTRL_RSTEQSIG__M 0x40 +#define VSB_TOP_SYSSMCTCTRL_RSTEQSIG__PRE 0x40 + +#define VSB_TOP_SYSSMCTCTRL_CKFRZ__B 7 +#define VSB_TOP_SYSSMCTCTRL_CKFRZ__W 1 +#define VSB_TOP_SYSSMCTCTRL_CKFRZ__M 0x80 +#define VSB_TOP_SYSSMCTCTRL_CKFRZ__PRE 0x0 + +#define VSB_TOP_SYSSMCTCTRL_CKBWSW__B 8 +#define VSB_TOP_SYSSMCTCTRL_CKBWSW__W 1 +#define VSB_TOP_SYSSMCTCTRL_CKBWSW__M 0x100 +#define VSB_TOP_SYSSMCTCTRL_CKBWSW__PRE 0x0 + +#define VSB_TOP_SYSSMCTCTRL_NCOBWSW__B 9 +#define VSB_TOP_SYSSMCTCTRL_NCOBWSW__W 1 +#define VSB_TOP_SYSSMCTCTRL_NCOBWSW__M 0x200 +#define VSB_TOP_SYSSMCTCTRL_NCOBWSW__PRE 0x0 + +#define VSB_TOP_SYSSMCTCTRL_NCOTIMEOUTCNTEN__B 10 +#define VSB_TOP_SYSSMCTCTRL_NCOTIMEOUTCNTEN__W 1 +#define VSB_TOP_SYSSMCTCTRL_NCOTIMEOUTCNTEN__M 0x400 +#define VSB_TOP_SYSSMCTCTRL_NCOTIMEOUTCNTEN__PRE 0x0 + +#define VSB_TOP_EQCTRL__A 0x1C10038 +#define VSB_TOP_EQCTRL__W 10 +#define VSB_TOP_EQCTRL__M 0x3FF +#define VSB_TOP_EQCTRL__PRE 0x6 + +#define VSB_TOP_EQCTRL_STASSIGNEN__B 0 +#define VSB_TOP_EQCTRL_STASSIGNEN__W 1 +#define VSB_TOP_EQCTRL_STASSIGNEN__M 0x1 +#define VSB_TOP_EQCTRL_STASSIGNEN__PRE 0x0 + +#define VSB_TOP_EQCTRL_ORCANCMAEN__B 1 +#define VSB_TOP_EQCTRL_ORCANCMAEN__W 1 +#define VSB_TOP_EQCTRL_ORCANCMAEN__M 0x2 +#define VSB_TOP_EQCTRL_ORCANCMAEN__PRE 0x2 + +#define VSB_TOP_EQCTRL_ODAGCGO__B 2 +#define VSB_TOP_EQCTRL_ODAGCGO__W 1 +#define VSB_TOP_EQCTRL_ODAGCGO__M 0x4 +#define VSB_TOP_EQCTRL_ODAGCGO__PRE 0x4 + +#define VSB_TOP_EQCTRL_OPTGAIN__B 3 +#define VSB_TOP_EQCTRL_OPTGAIN__W 3 +#define VSB_TOP_EQCTRL_OPTGAIN__M 0x38 +#define VSB_TOP_EQCTRL_OPTGAIN__PRE 0x0 + +#define VSB_TOP_EQCTRL_TAPRAMWRTEN__B 6 +#define VSB_TOP_EQCTRL_TAPRAMWRTEN__W 1 +#define VSB_TOP_EQCTRL_TAPRAMWRTEN__M 0x40 +#define VSB_TOP_EQCTRL_TAPRAMWRTEN__PRE 0x0 + +#define VSB_TOP_EQCTRL_CMAGAIN__B 7 +#define VSB_TOP_EQCTRL_CMAGAIN__W 3 +#define VSB_TOP_EQCTRL_CMAGAIN__M 0x380 +#define VSB_TOP_EQCTRL_CMAGAIN__PRE 0x0 + +#define VSB_TOP_PREEQAGCCTRL__A 0x1C10039 +#define VSB_TOP_PREEQAGCCTRL__W 5 +#define VSB_TOP_PREEQAGCCTRL__M 0x1F +#define VSB_TOP_PREEQAGCCTRL__PRE 0x10 + +#define VSB_TOP_PREEQAGCCTRL_PREEQAGCBWSEL__B 0 +#define VSB_TOP_PREEQAGCCTRL_PREEQAGCBWSEL__W 4 +#define VSB_TOP_PREEQAGCCTRL_PREEQAGCBWSEL__M 0xF +#define VSB_TOP_PREEQAGCCTRL_PREEQAGCBWSEL__PRE 0x0 + +#define VSB_TOP_PREEQAGCCTRL_PREEQAGCFRZ__B 4 +#define VSB_TOP_PREEQAGCCTRL_PREEQAGCFRZ__W 1 +#define VSB_TOP_PREEQAGCCTRL_PREEQAGCFRZ__M 0x10 +#define VSB_TOP_PREEQAGCCTRL_PREEQAGCFRZ__PRE 0x10 + + +#define VSB_TOP_PREEQAGCPWRREFLVLHI__A 0x1C1003A +#define VSB_TOP_PREEQAGCPWRREFLVLHI__W 8 +#define VSB_TOP_PREEQAGCPWRREFLVLHI__M 0xFF +#define VSB_TOP_PREEQAGCPWRREFLVLHI__PRE 0x0 + +#define VSB_TOP_PREEQAGCPWRREFLVLLO__A 0x1C1003B +#define VSB_TOP_PREEQAGCPWRREFLVLLO__W 16 +#define VSB_TOP_PREEQAGCPWRREFLVLLO__M 0xFFFF +#define VSB_TOP_PREEQAGCPWRREFLVLLO__PRE 0x1D66 + +#define VSB_TOP_CORINGSEL__A 0x1C1003C +#define VSB_TOP_CORINGSEL__W 8 +#define VSB_TOP_CORINGSEL__M 0xFF +#define VSB_TOP_CORINGSEL__PRE 0x3 +#define VSB_TOP_BEDETCTRL__A 0x1C1003D +#define VSB_TOP_BEDETCTRL__W 9 +#define VSB_TOP_BEDETCTRL__M 0x1FF +#define VSB_TOP_BEDETCTRL__PRE 0x145 + +#define VSB_TOP_BEDETCTRL_MIXRATIO__B 0 +#define VSB_TOP_BEDETCTRL_MIXRATIO__W 3 +#define VSB_TOP_BEDETCTRL_MIXRATIO__M 0x7 +#define VSB_TOP_BEDETCTRL_MIXRATIO__PRE 0x5 + +#define VSB_TOP_BEDETCTRL_CYOFFSEL__B 3 +#define VSB_TOP_BEDETCTRL_CYOFFSEL__W 1 +#define VSB_TOP_BEDETCTRL_CYOFFSEL__M 0x8 +#define VSB_TOP_BEDETCTRL_CYOFFSEL__PRE 0x0 + +#define VSB_TOP_BEDETCTRL_DATAOFFSEL__B 4 +#define VSB_TOP_BEDETCTRL_DATAOFFSEL__W 1 +#define VSB_TOP_BEDETCTRL_DATAOFFSEL__M 0x10 +#define VSB_TOP_BEDETCTRL_DATAOFFSEL__PRE 0x0 + +#define VSB_TOP_BEDETCTRL_BYPASS_DSQ__B 5 +#define VSB_TOP_BEDETCTRL_BYPASS_DSQ__W 1 +#define VSB_TOP_BEDETCTRL_BYPASS_DSQ__M 0x20 +#define VSB_TOP_BEDETCTRL_BYPASS_DSQ__PRE 0x0 + +#define VSB_TOP_BEDETCTRL_BYPASS_PSQ__B 6 +#define VSB_TOP_BEDETCTRL_BYPASS_PSQ__W 1 +#define VSB_TOP_BEDETCTRL_BYPASS_PSQ__M 0x40 +#define VSB_TOP_BEDETCTRL_BYPASS_PSQ__PRE 0x40 + +#define VSB_TOP_BEDETCTRL_BYPASS_CSQ__B 7 +#define VSB_TOP_BEDETCTRL_BYPASS_CSQ__W 1 +#define VSB_TOP_BEDETCTRL_BYPASS_CSQ__M 0x80 +#define VSB_TOP_BEDETCTRL_BYPASS_CSQ__PRE 0x0 + +#define VSB_TOP_BEDETCTRL_BYPASS_DMP__B 8 +#define VSB_TOP_BEDETCTRL_BYPASS_DMP__W 1 +#define VSB_TOP_BEDETCTRL_BYPASS_DMP__M 0x100 +#define VSB_TOP_BEDETCTRL_BYPASS_DMP__PRE 0x100 + + +#define VSB_TOP_LBAGCREFLVL__A 0x1C1003E +#define VSB_TOP_LBAGCREFLVL__W 12 +#define VSB_TOP_LBAGCREFLVL__M 0xFFF +#define VSB_TOP_LBAGCREFLVL__PRE 0x200 + +#define VSB_TOP_UBAGCREFLVL__A 0x1C1003F +#define VSB_TOP_UBAGCREFLVL__W 12 +#define VSB_TOP_UBAGCREFLVL__M 0xFFF +#define VSB_TOP_UBAGCREFLVL__PRE 0x400 + +#define VSB_TOP_NOTCH1_BIN_NUM__A 0x1C10040 +#define VSB_TOP_NOTCH1_BIN_NUM__W 11 +#define VSB_TOP_NOTCH1_BIN_NUM__M 0x7FF +#define VSB_TOP_NOTCH1_BIN_NUM__PRE 0xB2 + +#define VSB_TOP_NOTCH2_BIN_NUM__A 0x1C10041 +#define VSB_TOP_NOTCH2_BIN_NUM__W 11 +#define VSB_TOP_NOTCH2_BIN_NUM__M 0x7FF +#define VSB_TOP_NOTCH2_BIN_NUM__PRE 0x40B + +#define VSB_TOP_NOTCH_START_BIN_NUM__A 0x1C10042 +#define VSB_TOP_NOTCH_START_BIN_NUM__W 11 +#define VSB_TOP_NOTCH_START_BIN_NUM__M 0x7FF +#define VSB_TOP_NOTCH_START_BIN_NUM__PRE 0x7C0 + +#define VSB_TOP_NOTCH_STOP_BIN_NUM__A 0x1C10043 +#define VSB_TOP_NOTCH_STOP_BIN_NUM__W 11 +#define VSB_TOP_NOTCH_STOP_BIN_NUM__M 0x7FF +#define VSB_TOP_NOTCH_STOP_BIN_NUM__PRE 0x43F + +#define VSB_TOP_NOTCH_TEST_DURATION__A 0x1C10044 +#define VSB_TOP_NOTCH_TEST_DURATION__W 11 +#define VSB_TOP_NOTCH_TEST_DURATION__M 0x7FF +#define VSB_TOP_NOTCH_TEST_DURATION__PRE 0x7FF + +#define VSB_TOP_RESULT_LARGE_PEAK_BIN__A 0x1C10045 +#define VSB_TOP_RESULT_LARGE_PEAK_BIN__W 11 +#define VSB_TOP_RESULT_LARGE_PEAK_BIN__M 0x7FF +#define VSB_TOP_RESULT_LARGE_PEAK_BIN__PRE 0x0 + +#define VSB_TOP_RESULT_LARGE_PEAK_VALUE__A 0x1C10046 +#define VSB_TOP_RESULT_LARGE_PEAK_VALUE__W 16 +#define VSB_TOP_RESULT_LARGE_PEAK_VALUE__M 0xFFFF +#define VSB_TOP_RESULT_LARGE_PEAK_VALUE__PRE 0x0 + +#define VSB_TOP_RESULT_SMALL_PEAK_BIN__A 0x1C10047 +#define VSB_TOP_RESULT_SMALL_PEAK_BIN__W 11 +#define VSB_TOP_RESULT_SMALL_PEAK_BIN__M 0x7FF +#define VSB_TOP_RESULT_SMALL_PEAK_BIN__PRE 0x0 + +#define VSB_TOP_RESULT_SMALL_PEAK_VALUE__A 0x1C10048 +#define VSB_TOP_RESULT_SMALL_PEAK_VALUE__W 16 +#define VSB_TOP_RESULT_SMALL_PEAK_VALUE__M 0xFFFF +#define VSB_TOP_RESULT_SMALL_PEAK_VALUE__PRE 0x0 + +#define VSB_TOP_NOTCH_SWEEP_RUNNING__A 0x1C10049 +#define VSB_TOP_NOTCH_SWEEP_RUNNING__W 1 +#define VSB_TOP_NOTCH_SWEEP_RUNNING__M 0x1 +#define VSB_TOP_NOTCH_SWEEP_RUNNING__PRE 0x0 + +#define VSB_TOP_PREEQDAGCRATIO__A 0x1C1004A +#define VSB_TOP_PREEQDAGCRATIO__W 13 +#define VSB_TOP_PREEQDAGCRATIO__M 0x1FFF +#define VSB_TOP_PREEQDAGCRATIO__PRE 0x0 +#define VSB_TOP_AGC_TRUNCCTRL__A 0x1C1004B +#define VSB_TOP_AGC_TRUNCCTRL__W 4 +#define VSB_TOP_AGC_TRUNCCTRL__M 0xF +#define VSB_TOP_AGC_TRUNCCTRL__PRE 0xF + +#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_LSB__B 0 +#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_LSB__W 2 +#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_LSB__M 0x3 +#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_LSB__PRE 0x3 + +#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_12N__B 2 +#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_12N__W 1 +#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_12N__M 0x4 +#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_12N__PRE 0x4 + +#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_EN__B 3 +#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_EN__W 1 +#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_EN__M 0x8 +#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_EN__PRE 0x8 + + +#define VSB_TOP_BEAGC_DEADZONEINIT__A 0x1C1004C +#define VSB_TOP_BEAGC_DEADZONEINIT__W 8 +#define VSB_TOP_BEAGC_DEADZONEINIT__M 0xFF +#define VSB_TOP_BEAGC_DEADZONEINIT__PRE 0x50 + +#define VSB_TOP_BEAGC_REFLEVEL__A 0x1C1004D +#define VSB_TOP_BEAGC_REFLEVEL__W 9 +#define VSB_TOP_BEAGC_REFLEVEL__M 0x1FF +#define VSB_TOP_BEAGC_REFLEVEL__PRE 0xAE + +#define VSB_TOP_BEAGC_GAINSHIFT__A 0x1C1004E +#define VSB_TOP_BEAGC_GAINSHIFT__W 3 +#define VSB_TOP_BEAGC_GAINSHIFT__M 0x7 +#define VSB_TOP_BEAGC_GAINSHIFT__PRE 0x3 + +#define VSB_TOP_BEAGC_REGINIT__A 0x1C1004F +#define VSB_TOP_BEAGC_REGINIT__W 15 +#define VSB_TOP_BEAGC_REGINIT__M 0x7FFF +#define VSB_TOP_BEAGC_REGINIT__PRE 0x40 + +#define VSB_TOP_BEAGC_REGINIT_BEAGC_RST__B 14 +#define VSB_TOP_BEAGC_REGINIT_BEAGC_RST__W 1 +#define VSB_TOP_BEAGC_REGINIT_BEAGC_RST__M 0x4000 +#define VSB_TOP_BEAGC_REGINIT_BEAGC_RST__PRE 0x0 + + +#define VSB_TOP_BEAGC_SCALE__A 0x1C10050 +#define VSB_TOP_BEAGC_SCALE__W 14 +#define VSB_TOP_BEAGC_SCALE__M 0x3FFF +#define VSB_TOP_BEAGC_SCALE__PRE 0x0 + +#define VSB_TOP_CFAGC_DEADZONEINIT__A 0x1C10051 +#define VSB_TOP_CFAGC_DEADZONEINIT__W 8 +#define VSB_TOP_CFAGC_DEADZONEINIT__M 0xFF +#define VSB_TOP_CFAGC_DEADZONEINIT__PRE 0x50 + +#define VSB_TOP_CFAGC_REFLEVEL__A 0x1C10052 +#define VSB_TOP_CFAGC_REFLEVEL__W 9 +#define VSB_TOP_CFAGC_REFLEVEL__M 0x1FF +#define VSB_TOP_CFAGC_REFLEVEL__PRE 0xAE + +#define VSB_TOP_CFAGC_GAINSHIFT__A 0x1C10053 +#define VSB_TOP_CFAGC_GAINSHIFT__W 3 +#define VSB_TOP_CFAGC_GAINSHIFT__M 0x7 +#define VSB_TOP_CFAGC_GAINSHIFT__PRE 0x3 + +#define VSB_TOP_CFAGC_REGINIT__A 0x1C10054 +#define VSB_TOP_CFAGC_REGINIT__W 15 +#define VSB_TOP_CFAGC_REGINIT__M 0x7FFF +#define VSB_TOP_CFAGC_REGINIT__PRE 0x80 + +#define VSB_TOP_CFAGC_REGINIT_CFAGC_RST__B 14 +#define VSB_TOP_CFAGC_REGINIT_CFAGC_RST__W 1 +#define VSB_TOP_CFAGC_REGINIT_CFAGC_RST__M 0x4000 +#define VSB_TOP_CFAGC_REGINIT_CFAGC_RST__PRE 0x0 + + +#define VSB_TOP_CFAGC_SCALE__A 0x1C10055 +#define VSB_TOP_CFAGC_SCALE__W 14 +#define VSB_TOP_CFAGC_SCALE__M 0x3FFF +#define VSB_TOP_CFAGC_SCALE__PRE 0x0 + +#define VSB_TOP_CKTRKONCTL__A 0x1C10056 +#define VSB_TOP_CKTRKONCTL__W 2 +#define VSB_TOP_CKTRKONCTL__M 0x3 +#define VSB_TOP_CKTRKONCTL__PRE 0x0 + +#define VSB_TOP_CYTRKONCTL__A 0x1C10057 +#define VSB_TOP_CYTRKONCTL__W 2 +#define VSB_TOP_CYTRKONCTL__M 0x3 +#define VSB_TOP_CYTRKONCTL__PRE 0x0 + +#define VSB_TOP_PTONCTL__A 0x1C10058 +#define VSB_TOP_PTONCTL__W 2 +#define VSB_TOP_PTONCTL__M 0x3 +#define VSB_TOP_PTONCTL__PRE 0x0 + +#define VSB_TOP_NOTCH_SCALE_1__A 0x1C10059 +#define VSB_TOP_NOTCH_SCALE_1__W 8 +#define VSB_TOP_NOTCH_SCALE_1__M 0xFF +#define VSB_TOP_NOTCH_SCALE_1__PRE 0xA + +#define VSB_TOP_NOTCH_SCALE_2__A 0x1C1005A +#define VSB_TOP_NOTCH_SCALE_2__W 8 +#define VSB_TOP_NOTCH_SCALE_2__M 0xFF +#define VSB_TOP_NOTCH_SCALE_2__PRE 0xA + +#define VSB_TOP_FIRSTLARGFFETAP__A 0x1C1005B +#define VSB_TOP_FIRSTLARGFFETAP__W 12 +#define VSB_TOP_FIRSTLARGFFETAP__M 0xFFF +#define VSB_TOP_FIRSTLARGFFETAP__PRE 0x0 + +#define VSB_TOP_FIRSTLARGFFETAPADDR__A 0x1C1005C +#define VSB_TOP_FIRSTLARGFFETAPADDR__W 11 +#define VSB_TOP_FIRSTLARGFFETAPADDR__M 0x7FF +#define VSB_TOP_FIRSTLARGFFETAPADDR__PRE 0x0 + +#define VSB_TOP_SECONDLARGFFETAP__A 0x1C1005D +#define VSB_TOP_SECONDLARGFFETAP__W 12 +#define VSB_TOP_SECONDLARGFFETAP__M 0xFFF +#define VSB_TOP_SECONDLARGFFETAP__PRE 0x0 + +#define VSB_TOP_SECONDLARGFFETAPADDR__A 0x1C1005E +#define VSB_TOP_SECONDLARGFFETAPADDR__W 11 +#define VSB_TOP_SECONDLARGFFETAPADDR__M 0x7FF +#define VSB_TOP_SECONDLARGFFETAPADDR__PRE 0x0 + +#define VSB_TOP_FIRSTLARGDFETAP__A 0x1C1005F +#define VSB_TOP_FIRSTLARGDFETAP__W 12 +#define VSB_TOP_FIRSTLARGDFETAP__M 0xFFF +#define VSB_TOP_FIRSTLARGDFETAP__PRE 0x0 + +#define VSB_TOP_FIRSTLARGDFETAPADDR__A 0x1C10060 +#define VSB_TOP_FIRSTLARGDFETAPADDR__W 11 +#define VSB_TOP_FIRSTLARGDFETAPADDR__M 0x7FF +#define VSB_TOP_FIRSTLARGDFETAPADDR__PRE 0x0 + +#define VSB_TOP_SECONDLARGDFETAP__A 0x1C10061 +#define VSB_TOP_SECONDLARGDFETAP__W 12 +#define VSB_TOP_SECONDLARGDFETAP__M 0xFFF +#define VSB_TOP_SECONDLARGDFETAP__PRE 0x0 + +#define VSB_TOP_SECONDLARGDFETAPADDR__A 0x1C10062 +#define VSB_TOP_SECONDLARGDFETAPADDR__W 11 +#define VSB_TOP_SECONDLARGDFETAPADDR__M 0x7FF +#define VSB_TOP_SECONDLARGDFETAPADDR__PRE 0x0 + +#define VSB_TOP_PARAOWDBUS__A 0x1C10063 +#define VSB_TOP_PARAOWDBUS__W 12 +#define VSB_TOP_PARAOWDBUS__M 0xFFF +#define VSB_TOP_PARAOWDBUS__PRE 0x0 +#define VSB_TOP_PARAOWCTRL__A 0x1C10064 +#define VSB_TOP_PARAOWCTRL__W 7 +#define VSB_TOP_PARAOWCTRL__M 0x7F +#define VSB_TOP_PARAOWCTRL__PRE 0x0 + +#define VSB_TOP_PARAOWCTRL_PARAOWABUS__B 0 +#define VSB_TOP_PARAOWCTRL_PARAOWABUS__W 6 +#define VSB_TOP_PARAOWCTRL_PARAOWABUS__M 0x3F +#define VSB_TOP_PARAOWCTRL_PARAOWABUS__PRE 0x0 + +#define VSB_TOP_PARAOWCTRL_PARAOWEN__B 6 +#define VSB_TOP_PARAOWCTRL_PARAOWEN__W 1 +#define VSB_TOP_PARAOWCTRL_PARAOWEN__M 0x40 +#define VSB_TOP_PARAOWCTRL_PARAOWEN__PRE 0x0 + + +#define VSB_TOP_CURRENTSEGLOCAT__A 0x1C10065 +#define VSB_TOP_CURRENTSEGLOCAT__W 10 +#define VSB_TOP_CURRENTSEGLOCAT__M 0x3FF +#define VSB_TOP_CURRENTSEGLOCAT__PRE 0x0 + +#define VSB_TOP_MEASUREMENT_PERIOD__A 0x1C10066 +#define VSB_TOP_MEASUREMENT_PERIOD__W 16 +#define VSB_TOP_MEASUREMENT_PERIOD__M 0xFFFF +#define VSB_TOP_MEASUREMENT_PERIOD__PRE 0x0 + +#define VSB_TOP_NR_SYM_ERRS__A 0x1C10067 +#define VSB_TOP_NR_SYM_ERRS__W 16 +#define VSB_TOP_NR_SYM_ERRS__M 0xFFFF +#define VSB_TOP_NR_SYM_ERRS__PRE 0xFFFF + +#define VSB_TOP_ERR_ENERGY_L__A 0x1C10068 +#define VSB_TOP_ERR_ENERGY_L__W 16 +#define VSB_TOP_ERR_ENERGY_L__M 0xFFFF +#define VSB_TOP_ERR_ENERGY_L__PRE 0xFFFF + +#define VSB_TOP_ERR_ENERGY_H__A 0x1C10069 +#define VSB_TOP_ERR_ENERGY_H__W 16 +#define VSB_TOP_ERR_ENERGY_H__M 0xFFFF +#define VSB_TOP_ERR_ENERGY_H__PRE 0xFFFF + +#define VSB_TOP_SLICER_SEL_8LEV__A 0x1C1006A +#define VSB_TOP_SLICER_SEL_8LEV__W 1 +#define VSB_TOP_SLICER_SEL_8LEV__M 0x1 +#define VSB_TOP_SLICER_SEL_8LEV__PRE 0x1 + +#define VSB_TOP_BNFIELD__A 0x1C1006B +#define VSB_TOP_BNFIELD__W 3 +#define VSB_TOP_BNFIELD__M 0x7 +#define VSB_TOP_BNFIELD__PRE 0x3 + +#define VSB_TOP_CLPLASTNUM__A 0x1C1006C +#define VSB_TOP_CLPLASTNUM__W 8 +#define VSB_TOP_CLPLASTNUM__M 0xFF +#define VSB_TOP_CLPLASTNUM__PRE 0x0 + +#define VSB_TOP_BNSQERR__A 0x1C1006D +#define VSB_TOP_BNSQERR__W 16 +#define VSB_TOP_BNSQERR__M 0xFFFF +#define VSB_TOP_BNSQERR__PRE 0x1AD + +#define VSB_TOP_BNTHRESH__A 0x1C1006E +#define VSB_TOP_BNTHRESH__W 9 +#define VSB_TOP_BNTHRESH__M 0x1FF +#define VSB_TOP_BNTHRESH__PRE 0x120 + +#define VSB_TOP_BNCLPNUM__A 0x1C1006F +#define VSB_TOP_BNCLPNUM__W 16 +#define VSB_TOP_BNCLPNUM__M 0xFFFF +#define VSB_TOP_BNCLPNUM__PRE 0x0 +#define VSB_TOP_PHASELOCKCTRL__A 0x1C10070 +#define VSB_TOP_PHASELOCKCTRL__W 7 +#define VSB_TOP_PHASELOCKCTRL__M 0x7F +#define VSB_TOP_PHASELOCKCTRL__PRE 0x0 + +#define VSB_TOP_PHASELOCKCTRL_DFORCEPOLARITY__B 0 +#define VSB_TOP_PHASELOCKCTRL_DFORCEPOLARITY__W 1 +#define VSB_TOP_PHASELOCKCTRL_DFORCEPOLARITY__M 0x1 +#define VSB_TOP_PHASELOCKCTRL_DFORCEPOLARITY__PRE 0x0 + +#define VSB_TOP_PHASELOCKCTRL_DFORCEPLL__B 1 +#define VSB_TOP_PHASELOCKCTRL_DFORCEPLL__W 1 +#define VSB_TOP_PHASELOCKCTRL_DFORCEPLL__M 0x2 +#define VSB_TOP_PHASELOCKCTRL_DFORCEPLL__PRE 0x0 + +#define VSB_TOP_PHASELOCKCTRL_PFORCEPOLARITY__B 2 +#define VSB_TOP_PHASELOCKCTRL_PFORCEPOLARITY__W 1 +#define VSB_TOP_PHASELOCKCTRL_PFORCEPOLARITY__M 0x4 +#define VSB_TOP_PHASELOCKCTRL_PFORCEPOLARITY__PRE 0x0 + +#define VSB_TOP_PHASELOCKCTRL_PFORCEPLL__B 3 +#define VSB_TOP_PHASELOCKCTRL_PFORCEPLL__W 1 +#define VSB_TOP_PHASELOCKCTRL_PFORCEPLL__M 0x8 +#define VSB_TOP_PHASELOCKCTRL_PFORCEPLL__PRE 0x0 + +#define VSB_TOP_PHASELOCKCTRL_CFORCEPOLARITY__B 4 +#define VSB_TOP_PHASELOCKCTRL_CFORCEPOLARITY__W 1 +#define VSB_TOP_PHASELOCKCTRL_CFORCEPOLARITY__M 0x10 +#define VSB_TOP_PHASELOCKCTRL_CFORCEPOLARITY__PRE 0x0 + +#define VSB_TOP_PHASELOCKCTRL_CFORCEPLL__B 5 +#define VSB_TOP_PHASELOCKCTRL_CFORCEPLL__W 1 +#define VSB_TOP_PHASELOCKCTRL_CFORCEPLL__M 0x20 +#define VSB_TOP_PHASELOCKCTRL_CFORCEPLL__PRE 0x0 + +#define VSB_TOP_PHASELOCKCTRL_IQSWITCH__B 6 +#define VSB_TOP_PHASELOCKCTRL_IQSWITCH__W 1 +#define VSB_TOP_PHASELOCKCTRL_IQSWITCH__M 0x40 +#define VSB_TOP_PHASELOCKCTRL_IQSWITCH__PRE 0x0 + + +#define VSB_TOP_DLOCKACCUM__A 0x1C10071 +#define VSB_TOP_DLOCKACCUM__W 16 +#define VSB_TOP_DLOCKACCUM__M 0xFFFF +#define VSB_TOP_DLOCKACCUM__PRE 0x0 + +#define VSB_TOP_PLOCKACCUM__A 0x1C10072 +#define VSB_TOP_PLOCKACCUM__W 16 +#define VSB_TOP_PLOCKACCUM__M 0xFFFF +#define VSB_TOP_PLOCKACCUM__PRE 0x0 + +#define VSB_TOP_CLOCKACCUM__A 0x1C10073 +#define VSB_TOP_CLOCKACCUM__W 16 +#define VSB_TOP_CLOCKACCUM__M 0xFFFF +#define VSB_TOP_CLOCKACCUM__PRE 0x0 + +#define VSB_TOP_DCRMVACUMI__A 0x1C10074 +#define VSB_TOP_DCRMVACUMI__W 10 +#define VSB_TOP_DCRMVACUMI__M 0x3FF +#define VSB_TOP_DCRMVACUMI__PRE 0x0 + +#define VSB_TOP_DCRMVACUMQ__A 0x1C10075 +#define VSB_TOP_DCRMVACUMQ__W 10 +#define VSB_TOP_DCRMVACUMQ__M 0x3FF +#define VSB_TOP_DCRMVACUMQ__PRE 0x0 + + + + +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__A 0x1C20000 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__W 12 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO2__A 0x1C20001 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO2__W 12 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO2__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO2__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO3__A 0x1C20002 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO3__W 12 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO3__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO3__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO4__A 0x1C20003 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO4__W 12 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO4__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO4__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO5__A 0x1C20004 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO5__W 12 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO5__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO5__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO6__A 0x1C20005 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO6__W 12 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO6__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO6__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO7__A 0x1C20006 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO7__W 12 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO7__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO7__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO8__A 0x1C20007 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO8__W 12 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO8__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO8__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO9__A 0x1C20008 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO9__W 12 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO9__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO9__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO10__A 0x1C20009 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO10__W 12 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO10__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO10__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO11__A 0x1C2000A +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO11__W 12 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO11__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO11__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO12__A 0x1C2000B +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO12__W 12 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO12__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO12__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO1__A 0x1C2000C +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO1__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO1__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO1__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO2__A 0x1C2000D +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO2__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO2__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO2__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO3__A 0x1C2000E +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO3__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO3__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO3__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO4__A 0x1C2000F +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO4__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO4__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO4__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO5__A 0x1C20010 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO5__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO5__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO5__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO6__A 0x1C20011 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO6__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO6__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO6__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO7__A 0x1C20012 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO7__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO7__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO7__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO8__A 0x1C20013 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO8__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO8__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO8__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO9__A 0x1C20014 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO9__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO9__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO9__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO10__A 0x1C20015 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO10__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO10__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO10__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO11__A 0x1C20016 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO11__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO11__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO11__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO12__A 0x1C20017 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO12__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO12__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO12__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO1__A 0x1C20018 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO1__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO1__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO1__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO2__A 0x1C20019 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO2__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO2__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO2__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO3__A 0x1C2001A +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO3__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO3__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO3__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO4__A 0x1C2001B +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO4__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO4__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO4__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO5__A 0x1C2001C +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO5__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO5__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO5__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO6__A 0x1C2001D +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO6__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO6__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO6__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO7__A 0x1C2001E +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO7__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO7__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO7__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO8__A 0x1C2001F +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO8__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO8__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO8__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO9__A 0x1C20020 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO9__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO9__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO9__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO10__A 0x1C20021 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO10__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO10__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO10__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO11__A 0x1C20022 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO11__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO11__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO11__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO12__A 0x1C20023 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO12__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO12__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO12__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO1__A 0x1C20024 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO1__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO1__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO1__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO2__A 0x1C20025 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO2__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO2__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO2__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO3__A 0x1C20026 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO3__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO3__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO3__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO4__A 0x1C20027 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO4__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO4__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO4__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO5__A 0x1C20028 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO5__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO5__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO5__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO6__A 0x1C20029 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO6__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO6__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO6__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO7__A 0x1C2002A +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO7__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO7__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO7__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO8__A 0x1C2002B +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO8__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO8__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO8__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO9__A 0x1C2002C +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO9__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO9__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO9__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO10__A 0x1C2002D +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO10__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO10__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO10__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO11__A 0x1C2002E +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO11__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO11__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO11__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO12__A 0x1C2002F +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO12__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO12__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO12__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO1__A 0x1C20030 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO1__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO1__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO1__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO2__A 0x1C20031 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO2__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO2__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO2__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO3__A 0x1C20032 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO3__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO3__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO3__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO4__A 0x1C20033 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO4__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO4__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO4__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO5__A 0x1C20034 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO5__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO5__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO5__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO6__A 0x1C20035 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO6__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO6__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO6__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO7__A 0x1C20036 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO7__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO7__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO7__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO8__A 0x1C20037 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO8__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO8__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO8__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO9__A 0x1C20038 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO9__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO9__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO9__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO10__A 0x1C20039 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO10__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO10__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO10__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO11__A 0x1C2003A +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO11__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO11__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO11__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO12__A 0x1C2003B +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO12__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO12__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO12__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO1__A 0x1C2003C +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO1__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO1__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO1__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO2__A 0x1C2003D +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO2__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO2__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO2__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO3__A 0x1C2003E +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO3__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO3__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO3__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO4__A 0x1C2003F +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO4__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO4__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO4__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO5__A 0x1C20040 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO5__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO5__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO5__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO6__A 0x1C20041 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO6__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO6__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO6__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO7__A 0x1C20042 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO7__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO7__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO7__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO8__A 0x1C20043 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO8__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO8__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO8__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO9__A 0x1C20044 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO9__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO9__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO9__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO10__A 0x1C20045 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO10__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO10__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO10__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO11__A 0x1C20046 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO11__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO11__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO11__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO12__A 0x1C20047 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO12__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO12__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO12__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO1__A 0x1C20048 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO1__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO1__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO1__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO2__A 0x1C20049 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO2__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO2__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO2__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO3__A 0x1C2004A +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO3__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO3__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO3__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO4__A 0x1C2004B +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO4__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO4__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO4__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO5__A 0x1C2004C +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO5__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO5__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO5__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO6__A 0x1C2004D +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO6__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO6__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO6__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO7__A 0x1C2004E +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO7__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO7__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO7__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO8__A 0x1C2004F +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO8__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO8__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO8__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO9__A 0x1C20050 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO9__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO9__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO9__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO10__A 0x1C20051 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO10__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO10__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO10__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO11__A 0x1C20052 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO11__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO11__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO11__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO12__A 0x1C20053 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO12__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO12__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO12__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO1__A 0x1C20054 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO1__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO1__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO1__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO2__A 0x1C20055 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO2__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO2__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO2__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO3__A 0x1C20056 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO3__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO3__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO3__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO4__A 0x1C20057 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO4__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO4__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO4__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO5__A 0x1C20058 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO5__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO5__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO5__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO6__A 0x1C20059 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO6__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO6__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO6__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO7__A 0x1C2005A +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO7__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO7__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO7__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO8__A 0x1C2005B +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO8__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO8__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO8__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO9__A 0x1C2005C +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO9__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO9__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO9__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO10__A 0x1C2005D +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO10__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO10__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO10__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO11__A 0x1C2005E +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO11__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO11__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO11__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO12__A 0x1C2005F +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO12__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO12__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO12__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO1__A 0x1C20060 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO1__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO1__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO1__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO2__A 0x1C20061 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO2__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO2__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO2__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO3__A 0x1C20062 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO3__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO3__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO3__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO4__A 0x1C20063 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO4__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO4__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO4__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO5__A 0x1C20064 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO5__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO5__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO5__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO6__A 0x1C20065 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO6__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO6__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO6__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO7__A 0x1C20066 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO7__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO7__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO7__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO8__A 0x1C20067 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO8__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO8__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO8__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO9__A 0x1C20068 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO9__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO9__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO9__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO10__A 0x1C20069 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO10__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO10__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO10__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO11__A 0x1C2006A +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO11__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO11__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO11__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO12__A 0x1C2006B +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO12__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO12__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO12__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN1__A 0x1C2006C +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN1__W 7 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN1__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN1__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN2__A 0x1C2006D +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN2__W 7 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN2__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN2__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN3__A 0x1C2006E +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN3__W 7 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN3__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN3__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN4__A 0x1C2006F +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN4__W 7 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN4__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN4__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN5__A 0x1C20070 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN5__W 7 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN5__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN5__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN6__A 0x1C20071 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN6__W 7 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN6__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN6__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN7__A 0x1C20072 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN7__W 7 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN7__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN7__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN8__A 0x1C20073 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN8__W 7 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN8__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN8__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN9__A 0x1C20074 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN9__W 7 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN9__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN9__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN10__A 0x1C20075 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN10__W 7 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN10__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN10__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN11__A 0x1C20076 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN11__W 7 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN11__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN11__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN12__A 0x1C20077 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN12__W 7 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN12__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN12__PRE 0x0 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1__A 0x1C20078 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1__W 15 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1__M 0x7FFF +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1TRAINGAIN1__B 0 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1TRAINGAIN1__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1TRAINGAIN1__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1TRAINGAIN1__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1DATAGAIN1__B 8 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1DATAGAIN1__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1DATAGAIN1__M 0x7F00 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1DATAGAIN1__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2__A 0x1C20079 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2__W 15 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2__M 0x7FFF +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1TRAINGAIN2__B 0 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1TRAINGAIN2__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1TRAINGAIN2__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1TRAINGAIN2__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1DATAGAIN2__B 8 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1DATAGAIN2__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1DATAGAIN2__M 0x7F00 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1DATAGAIN2__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3__A 0x1C2007A +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3__W 15 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3__M 0x7FFF +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1TRAINGAIN3__B 0 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1TRAINGAIN3__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1TRAINGAIN3__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1TRAINGAIN3__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1DATAGAIN3__B 8 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1DATAGAIN3__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1DATAGAIN3__M 0x7F00 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1DATAGAIN3__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4__A 0x1C2007B +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4__W 15 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4__M 0x7FFF +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1TRAINGAIN4__B 0 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1TRAINGAIN4__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1TRAINGAIN4__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1TRAINGAIN4__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1DATAGAIN4__B 8 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1DATAGAIN4__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1DATAGAIN4__M 0x7F00 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1DATAGAIN4__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5__A 0x1C2007C +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5__W 15 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5__M 0x7FFF +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1TRAINGAIN5__B 0 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1TRAINGAIN5__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1TRAINGAIN5__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1TRAINGAIN5__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1DATAGAIN5__B 8 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1DATAGAIN5__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1DATAGAIN5__M 0x7F00 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1DATAGAIN5__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6__A 0x1C2007D +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6__W 15 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6__M 0x7FFF +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1TRAINGAIN6__B 0 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1TRAINGAIN6__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1TRAINGAIN6__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1TRAINGAIN6__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1DATAGAIN6__B 8 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1DATAGAIN6__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1DATAGAIN6__M 0x7F00 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1DATAGAIN6__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7__A 0x1C2007E +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7__W 15 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7__M 0x7FFF +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1TRAINGAIN7__B 0 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1TRAINGAIN7__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1TRAINGAIN7__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1TRAINGAIN7__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1DATAGAIN7__B 8 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1DATAGAIN7__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1DATAGAIN7__M 0x7F00 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1DATAGAIN7__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8__A 0x1C2007F +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8__W 15 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8__M 0x7FFF +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1TRAINGAIN8__B 0 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1TRAINGAIN8__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1TRAINGAIN8__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1TRAINGAIN8__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1DATAGAIN8__B 8 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1DATAGAIN8__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1DATAGAIN8__M 0x7F00 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1DATAGAIN8__PRE 0x0 + + + +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__A 0x1C30000 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1TRAINGAIN9__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1TRAINGAIN9__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1TRAINGAIN9__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1TRAINGAIN9__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1DATAGAIN9__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1DATAGAIN9__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1DATAGAIN9__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1DATAGAIN9__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10__A 0x1C30001 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1TRAINGAIN10__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1TRAINGAIN10__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1TRAINGAIN10__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1TRAINGAIN10__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1DATAGAIN10__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1DATAGAIN10__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1DATAGAIN10__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1DATAGAIN10__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11__A 0x1C30002 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1TRAINGAIN11__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1TRAINGAIN11__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1TRAINGAIN11__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1TRAINGAIN11__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1DATAGAIN11__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1DATAGAIN11__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1DATAGAIN11__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1DATAGAIN11__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12__A 0x1C30003 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1TRAINGAIN12__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1TRAINGAIN12__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1TRAINGAIN12__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1TRAINGAIN12__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1DATAGAIN12__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1DATAGAIN12__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1DATAGAIN12__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1DATAGAIN12__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1__A 0x1C30004 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2TRAINGAIN1__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2TRAINGAIN1__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2TRAINGAIN1__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2TRAINGAIN1__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2DATAGAIN1__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2DATAGAIN1__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2DATAGAIN1__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2DATAGAIN1__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2__A 0x1C30005 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2TRAINGAIN2__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2TRAINGAIN2__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2TRAINGAIN2__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2TRAINGAIN2__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2DATAGAIN2__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2DATAGAIN2__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2DATAGAIN2__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2DATAGAIN2__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3__A 0x1C30006 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2TRAINGAIN3__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2TRAINGAIN3__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2TRAINGAIN3__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2TRAINGAIN3__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2DATAGAIN3__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2DATAGAIN3__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2DATAGAIN3__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2DATAGAIN3__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4__A 0x1C30007 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2TRAINGAIN4__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2TRAINGAIN4__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2TRAINGAIN4__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2TRAINGAIN4__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2DATAGAIN4__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2DATAGAIN4__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2DATAGAIN4__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2DATAGAIN4__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5__A 0x1C30008 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2TRAINGAIN5__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2TRAINGAIN5__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2TRAINGAIN5__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2TRAINGAIN5__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2DATAGAIN5__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2DATAGAIN5__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2DATAGAIN5__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2DATAGAIN5__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6__A 0x1C30009 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2TRAINGAIN6__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2TRAINGAIN6__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2TRAINGAIN6__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2TRAINGAIN6__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2DATAGAIN6__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2DATAGAIN6__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2DATAGAIN6__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2DATAGAIN6__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7__A 0x1C3000A +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2TRAINGAIN7__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2TRAINGAIN7__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2TRAINGAIN7__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2TRAINGAIN7__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2DATAGAIN7__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2DATAGAIN7__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2DATAGAIN7__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2DATAGAIN7__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8__A 0x1C3000B +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2TRAINGAIN8__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2TRAINGAIN8__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2TRAINGAIN8__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2TRAINGAIN8__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2DATAGAIN8__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2DATAGAIN8__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2DATAGAIN8__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2DATAGAIN8__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9__A 0x1C3000C +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2TRAINGAIN9__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2TRAINGAIN9__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2TRAINGAIN9__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2TRAINGAIN9__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2DATAGAIN9__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2DATAGAIN9__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2DATAGAIN9__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2DATAGAIN9__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10__A 0x1C3000D +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2TRAINGAIN10__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2TRAINGAIN10__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2TRAINGAIN10__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2TRAINGAIN10__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2DATAGAIN10__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2DATAGAIN10__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2DATAGAIN10__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2DATAGAIN10__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11__A 0x1C3000E +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2TRAINGAIN11__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2TRAINGAIN11__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2TRAINGAIN11__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2TRAINGAIN11__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2DATAGAIN11__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2DATAGAIN11__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2DATAGAIN11__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2DATAGAIN11__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12__A 0x1C3000F +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2TRAINGAIN12__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2TRAINGAIN12__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2TRAINGAIN12__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2TRAINGAIN12__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2DATAGAIN12__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2DATAGAIN12__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2DATAGAIN12__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2DATAGAIN12__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1__A 0x1C30010 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1TRAINGAIN1__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1TRAINGAIN1__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1TRAINGAIN1__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1TRAINGAIN1__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1DATAGAIN1__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1DATAGAIN1__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1DATAGAIN1__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1DATAGAIN1__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2__A 0x1C30011 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1TRAINGAIN2__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1TRAINGAIN2__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1TRAINGAIN2__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1TRAINGAIN2__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1DATAGAIN2__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1DATAGAIN2__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1DATAGAIN2__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1DATAGAIN2__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3__A 0x1C30012 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1TRAINGAIN3__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1TRAINGAIN3__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1TRAINGAIN3__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1TRAINGAIN3__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1DATAGAIN3__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1DATAGAIN3__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1DATAGAIN3__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1DATAGAIN3__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4__A 0x1C30013 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1TRAINGAIN4__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1TRAINGAIN4__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1TRAINGAIN4__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1TRAINGAIN4__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1DATAGAIN4__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1DATAGAIN4__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1DATAGAIN4__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1DATAGAIN4__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5__A 0x1C30014 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1TRAINGAIN5__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1TRAINGAIN5__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1TRAINGAIN5__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1TRAINGAIN5__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1DATAGAIN5__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1DATAGAIN5__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1DATAGAIN5__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1DATAGAIN5__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6__A 0x1C30015 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1TRAINGAIN6__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1TRAINGAIN6__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1TRAINGAIN6__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1TRAINGAIN6__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1DATAGAIN6__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1DATAGAIN6__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1DATAGAIN6__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1DATAGAIN6__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7__A 0x1C30016 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1TRAINGAIN7__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1TRAINGAIN7__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1TRAINGAIN7__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1TRAINGAIN7__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1DATAGAIN7__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1DATAGAIN7__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1DATAGAIN7__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1DATAGAIN7__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8__A 0x1C30017 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1TRAINGAIN8__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1TRAINGAIN8__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1TRAINGAIN8__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1TRAINGAIN8__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1DATAGAIN8__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1DATAGAIN8__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1DATAGAIN8__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1DATAGAIN8__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9__A 0x1C30018 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1TRAINGAIN9__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1TRAINGAIN9__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1TRAINGAIN9__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1TRAINGAIN9__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1DATAGAIN9__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1DATAGAIN9__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1DATAGAIN9__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1DATAGAIN9__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10__A 0x1C30019 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1TRAINGAIN10__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1TRAINGAIN10__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1TRAINGAIN10__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1TRAINGAIN10__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1DATAGAIN10__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1DATAGAIN10__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1DATAGAIN10__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1DATAGAIN10__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11__A 0x1C3001A +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1TRAINGAIN11__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1TRAINGAIN11__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1TRAINGAIN11__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1TRAINGAIN11__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1DATAGAIN11__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1DATAGAIN11__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1DATAGAIN11__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1DATAGAIN11__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12__A 0x1C3001B +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1TRAINGAIN12__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1TRAINGAIN12__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1TRAINGAIN12__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1TRAINGAIN12__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1DATAGAIN12__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1DATAGAIN12__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1DATAGAIN12__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1DATAGAIN12__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1__A 0x1C3001C +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2TRAINGAIN1__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2TRAINGAIN1__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2TRAINGAIN1__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2TRAINGAIN1__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2DATAGAIN1__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2DATAGAIN1__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2DATAGAIN1__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2DATAGAIN1__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2__A 0x1C3001D +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2TRAINGAIN2__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2TRAINGAIN2__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2TRAINGAIN2__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2TRAINGAIN2__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2DATAGAIN2__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2DATAGAIN2__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2DATAGAIN2__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2DATAGAIN2__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3__A 0x1C3001E +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2TRAINGAIN3__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2TRAINGAIN3__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2TRAINGAIN3__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2TRAINGAIN3__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2DATAGAIN3__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2DATAGAIN3__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2DATAGAIN3__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2DATAGAIN3__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4__A 0x1C3001F +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2TRAINGAIN4__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2TRAINGAIN4__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2TRAINGAIN4__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2TRAINGAIN4__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2DATAGAIN4__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2DATAGAIN4__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2DATAGAIN4__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2DATAGAIN4__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5__A 0x1C30020 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2TRAINGAIN5__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2TRAINGAIN5__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2TRAINGAIN5__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2TRAINGAIN5__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2DATAGAIN5__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2DATAGAIN5__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2DATAGAIN5__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2DATAGAIN5__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6__A 0x1C30021 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2TRAINGAIN6__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2TRAINGAIN6__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2TRAINGAIN6__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2TRAINGAIN6__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2DATAGAIN6__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2DATAGAIN6__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2DATAGAIN6__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2DATAGAIN6__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7__A 0x1C30022 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2TRAINGAIN7__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2TRAINGAIN7__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2TRAINGAIN7__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2TRAINGAIN7__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2DATAGAIN7__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2DATAGAIN7__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2DATAGAIN7__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2DATAGAIN7__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8__A 0x1C30023 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2TRAINGAIN8__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2TRAINGAIN8__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2TRAINGAIN8__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2TRAINGAIN8__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2DATAGAIN8__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2DATAGAIN8__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2DATAGAIN8__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2DATAGAIN8__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9__A 0x1C30024 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2TRAINGAIN9__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2TRAINGAIN9__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2TRAINGAIN9__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2TRAINGAIN9__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2DATAGAIN9__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2DATAGAIN9__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2DATAGAIN9__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2DATAGAIN9__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10__A 0x1C30025 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2TRAINGAIN10__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2TRAINGAIN10__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2TRAINGAIN10__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2TRAINGAIN10__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2DATAGAIN10__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2DATAGAIN10__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2DATAGAIN10__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2DATAGAIN10__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11__A 0x1C30026 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2TRAINGAIN11__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2TRAINGAIN11__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2TRAINGAIN11__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2TRAINGAIN11__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2DATAGAIN11__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2DATAGAIN11__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2DATAGAIN11__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2DATAGAIN11__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12__A 0x1C30027 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2TRAINGAIN12__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2TRAINGAIN12__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2TRAINGAIN12__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2TRAINGAIN12__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2DATAGAIN12__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2DATAGAIN12__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2DATAGAIN12__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2DATAGAIN12__PRE 0x0 + + +#define VSB_SYSCTRL_RAM1_DFETRAINLKRATIO__A 0x1C30028 +#define VSB_SYSCTRL_RAM1_DFETRAINLKRATIO__W 12 +#define VSB_SYSCTRL_RAM1_DFETRAINLKRATIO__M 0xFFF +#define VSB_SYSCTRL_RAM1_DFETRAINLKRATIO__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFERCA1TRAINLKRATIO__A 0x1C30029 +#define VSB_SYSCTRL_RAM1_DFERCA1TRAINLKRATIO__W 12 +#define VSB_SYSCTRL_RAM1_DFERCA1TRAINLKRATIO__M 0xFFF +#define VSB_SYSCTRL_RAM1_DFERCA1TRAINLKRATIO__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFERCA1DATALKRATIO__A 0x1C3002A +#define VSB_SYSCTRL_RAM1_DFERCA1DATALKRATIO__W 12 +#define VSB_SYSCTRL_RAM1_DFERCA1DATALKRATIO__M 0xFFF +#define VSB_SYSCTRL_RAM1_DFERCA1DATALKRATIO__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFERCA2TRAINLKRATIO__A 0x1C3002B +#define VSB_SYSCTRL_RAM1_DFERCA2TRAINLKRATIO__W 12 +#define VSB_SYSCTRL_RAM1_DFERCA2TRAINLKRATIO__M 0xFFF +#define VSB_SYSCTRL_RAM1_DFERCA2TRAINLKRATIO__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFERCA2DATALKRATIO__A 0x1C3002C +#define VSB_SYSCTRL_RAM1_DFERCA2DATALKRATIO__W 12 +#define VSB_SYSCTRL_RAM1_DFERCA2DATALKRATIO__M 0xFFF +#define VSB_SYSCTRL_RAM1_DFERCA2DATALKRATIO__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFEDDM1TRAINLKRATIO__A 0x1C3002D +#define VSB_SYSCTRL_RAM1_DFEDDM1TRAINLKRATIO__W 12 +#define VSB_SYSCTRL_RAM1_DFEDDM1TRAINLKRATIO__M 0xFFF +#define VSB_SYSCTRL_RAM1_DFEDDM1TRAINLKRATIO__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFEDDM1DATALKRATIO__A 0x1C3002E +#define VSB_SYSCTRL_RAM1_DFEDDM1DATALKRATIO__W 12 +#define VSB_SYSCTRL_RAM1_DFEDDM1DATALKRATIO__M 0xFFF +#define VSB_SYSCTRL_RAM1_DFEDDM1DATALKRATIO__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFEDDM2TRAINLKRATIO__A 0x1C3002F +#define VSB_SYSCTRL_RAM1_DFEDDM2TRAINLKRATIO__W 12 +#define VSB_SYSCTRL_RAM1_DFEDDM2TRAINLKRATIO__M 0xFFF +#define VSB_SYSCTRL_RAM1_DFEDDM2TRAINLKRATIO__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFEDDM2DATALKRATIO__A 0x1C30030 +#define VSB_SYSCTRL_RAM1_DFEDDM2DATALKRATIO__W 12 +#define VSB_SYSCTRL_RAM1_DFEDDM2DATALKRATIO__M 0xFFF +#define VSB_SYSCTRL_RAM1_DFEDDM2DATALKRATIO__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFETRAINGAIN__A 0x1C30031 +#define VSB_SYSCTRL_RAM1_DFETRAINGAIN__W 7 +#define VSB_SYSCTRL_RAM1_DFETRAINGAIN__M 0x7F +#define VSB_SYSCTRL_RAM1_DFETRAINGAIN__PRE 0x0 +#define VSB_SYSCTRL_RAM1_DFERCA1GAIN__A 0x1C30032 +#define VSB_SYSCTRL_RAM1_DFERCA1GAIN__W 15 +#define VSB_SYSCTRL_RAM1_DFERCA1GAIN__M 0x7FFF +#define VSB_SYSCTRL_RAM1_DFERCA1GAIN__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1TRAINGAIN__B 0 +#define VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1TRAINGAIN__W 7 +#define VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1TRAINGAIN__M 0x7F +#define VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1TRAINGAIN__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1DATAGAIN__B 8 +#define VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1DATAGAIN__W 7 +#define VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1DATAGAIN__M 0x7F00 +#define VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1DATAGAIN__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFERCA2GAIN__A 0x1C30033 +#define VSB_SYSCTRL_RAM1_DFERCA2GAIN__W 15 +#define VSB_SYSCTRL_RAM1_DFERCA2GAIN__M 0x7FFF +#define VSB_SYSCTRL_RAM1_DFERCA2GAIN__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2TRAINGAIN__B 0 +#define VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2TRAINGAIN__W 7 +#define VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2TRAINGAIN__M 0x7F +#define VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2TRAINGAIN__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2DATAGAIN__B 8 +#define VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2DATAGAIN__W 7 +#define VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2DATAGAIN__M 0x7F00 +#define VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2DATAGAIN__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN__A 0x1C30034 +#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN__W 15 +#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN__M 0x7FFF +#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1TRAINGAIN__B 0 +#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1TRAINGAIN__W 7 +#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1TRAINGAIN__M 0x7F +#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1TRAINGAIN__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1DATAGAIN__B 8 +#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1DATAGAIN__W 7 +#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1DATAGAIN__M 0x7F00 +#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1DATAGAIN__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN__A 0x1C30035 +#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN__W 15 +#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN__M 0x7FFF +#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2TRAINGAIN__B 0 +#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2TRAINGAIN__W 7 +#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2TRAINGAIN__M 0x7F +#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2TRAINGAIN__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2DATAGAIN__B 8 +#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2DATAGAIN__W 7 +#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2DATAGAIN__M 0x7F00 +#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2DATAGAIN__PRE 0x0 + + + +#define VSB_TCMEQ_RAM__A 0x1C40000 + +#define VSB_TCMEQ_RAM_TCMEQ_RAM__B 0 +#define VSB_TCMEQ_RAM_TCMEQ_RAM__W 16 +#define VSB_TCMEQ_RAM_TCMEQ_RAM__M 0xFFFF +#define VSB_TCMEQ_RAM_TCMEQ_RAM__PRE 0x0 + + + +#define VSB_FCPRE_RAM__A 0x1C50000 + +#define VSB_FCPRE_RAM_FCPRE_RAM__B 0 +#define VSB_FCPRE_RAM_FCPRE_RAM__W 16 +#define VSB_FCPRE_RAM_FCPRE_RAM__M 0xFFFF +#define VSB_FCPRE_RAM_FCPRE_RAM__PRE 0x0 + + + +#define VSB_EQTAP_RAM__A 0x1C60000 + +#define VSB_EQTAP_RAM_EQTAP_RAM__B 0 +#define VSB_EQTAP_RAM_EQTAP_RAM__W 12 +#define VSB_EQTAP_RAM_EQTAP_RAM__M 0xFFF +#define VSB_EQTAP_RAM_EQTAP_RAM__PRE 0x0 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj_mc.h b/drivers/media/dvb-frontends/drx39xyj/drxj_mc.h new file mode 100644 index 0000000..8be8272 --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/drxj_mc.h @@ -0,0 +1,3947 @@ +/*----------------------------------------------------------------------------- +* DESCRIPTION: +* Contains firmware version: 1.0.8 +* +* USAGE: +* Include. +* +* NOTES: +* (c) 2009 Trident Microsystems, Inc. - All rights reserved. +* +* This software and related documentation (the 'Software') are intellectual +* property owned by Trident and are copyright of Trident, unless specifically +* noted otherwise. +* +* Any use of the Software is permitted only pursuant to the terms of the +* license agreement, if any, which accompanies, is included with or applicable +* to the Software ('License Agreement') or upon express written consent of +* Trident. Any copying, reproduction or redistribution of the Software in +* whole or in part by any means not in accordance with the License Agreement +* or as agreed in writing by Trident is expressly prohibited. +* +* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE +* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE +* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND +* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES +* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT +* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL +* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY +* TO USE THE SOFTWARE. +* +* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, +* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, +* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS +* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE +* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM +* TRIDENT'S NEGLIGENCE. +* +* IN NO EVENT SHALL MICRONAS BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, +* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, +* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS +* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE +* INABILITY TO USE THE SOFTWARE, EVEN IF MICRONAS HAS BEEN ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM +* MICRONAS' NEGLIGENCE. +* +----------------------------------------------------------------------------*/ + +#ifndef __DRXJ_MC_MAIN_H__ +#define __DRXJ_MC_MAIN_H__ + +#define DRXJ_MC_MAIN ((pu8_t) drxj_mc_main_g) + +const u8_t drxj_mc_main_g[] = { +0x48, 0x4c, 0x00, 0x06, 0x00, 0x00, 0xf3, 0x10, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x01, 0x07, +0x00, 0x00, 0x1f, 0xf0, 0x00, 0x01, 0xdd, 0x81, 0x00, 0x40, 0x0a, 0x00, 0xa4, 0x00, 0x00, 0x00, +0x03, 0x00, 0x2c, 0x16, 0xa4, 0x00, 0x00, 0x00, 0xfe, 0x01, 0xef, 0xff, 0xc8, 0x00, 0x00, 0x00, +0x03, 0x00, 0x0c, 0xa6, 0x27, 0x00, 0x00, 0x00, 0x51, 0x90, 0x08, 0x05, 0xff, 0x00, 0x00, 0x00, +0xa4, 0x81, 0x0c, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x9f, 0x3d, 0x0b, 0x00, 0xa4, 0x00, 0x00, 0x00, +0x9d, 0x35, 0xeb, 0x99, 0xb3, 0x00, 0x00, 0x00, 0x9b, 0x2d, 0xcb, 0x19, 0xb3, 0x00, 0x00, 0x00, +0x99, 0x25, 0xab, 0x99, 0xb2, 0x00, 0x00, 0x00, 0x97, 0x1d, 0x8b, 0x19, 0xb2, 0x00, 0x00, 0x00, +0x91, 0x41, 0x2a, 0x99, 0xb0, 0x00, 0x00, 0x00, 0xa5, 0x20, 0x6d, 0x22, 0xd2, 0x00, 0x00, 0x00, +0x33, 0x18, 0x4d, 0xbb, 0xd1, 0x00, 0x00, 0x00, 0x56, 0x00, 0x0f, 0x24, 0xd0, 0x00, 0x00, 0x00, +0xc4, 0x2b, 0x3d, 0x0a, 0xf0, 0x00, 0x00, 0x00, 0xad, 0x02, 0xcd, 0x2a, 0xd0, 0x00, 0x00, 0x00, +0x64, 0x00, 0x3d, 0x0c, 0xd0, 0x00, 0x00, 0x00, 0x8c, 0x80, 0x3e, 0x0b, 0xf0, 0x00, 0x00, 0x00, +0x08, 0x19, 0x9d, 0x20, 0xd1, 0x00, 0x00, 0x00, 0x00, 0x40, 0x0a, 0x01, 0xa4, 0x00, 0x00, 0x00, +0x5c, 0x80, 0x3c, 0x0b, 0xf0, 0x00, 0x00, 0x00, 0x83, 0x80, 0x0c, 0x03, 0xa4, 0x00, 0x00, 0x00, +0x00, 0x20, 0x25, 0x1a, 0x51, 0x00, 0x00, 0x00, 0x92, 0x12, 0x06, 0x20, 0x61, 0x00, 0x00, 0x00, +0x21, 0x83, 0x18, 0xc5, 0x32, 0x00, 0x00, 0x00, 0xc6, 0x80, 0x0c, 0x12, 0xa4, 0x00, 0x00, 0x00, +0x07, 0x81, 0x1c, 0x24, 0xe4, 0x00, 0x00, 0x00, 0xd3, 0x40, 0x3a, 0x34, 0xc8, 0x00, 0x00, 0x00, +0x55, 0x41, 0x4a, 0x11, 0xa4, 0x00, 0x00, 0x00, 0x35, 0x02, 0x0c, 0x00, 0xa4, 0x00, 0x00, 0x00, +0xa0, 0x41, 0x3a, 0x09, 0xf0, 0x00, 0x00, 0x00, 0xdb, 0x87, 0xed, 0x22, 0xd0, 0x00, 0x00, 0x00, +0x9d, 0x40, 0xca, 0x19, 0xa4, 0x00, 0x00, 0x00, 0x00, 0x40, 0x0c, 0x00, 0xf0, 0x00, 0x00, 0x00, +0x00, 0x08, 0x1a, 0x26, 0xd0, 0x00, 0x00, 0x00, 0x00, 0x40, 0x0c, 0x40, 0x11, 0x00, 0x00, 0x00, +0x00, 0x08, 0x0a, 0x40, 0x21, 0x00, 0x00, 0x00, 0x20, 0x80, 0x3c, 0x09, 0xf0, 0x00, 0x00, 0x00, +0x30, 0x81, 0x3c, 0x1b, 0xa4, 0x00, 0x00, 0x00, 0xe1, 0x68, 0x05, 0x00, 0xf0, 0x00, 0x00, 0x00, +0x00, 0x60, 0x13, 0x4d, 0xd0, 0x00, 0x00, 0x00, 0x4b, 0x02, 0x7d, 0x06, 0x81, 0x00, 0x00, 0x00, +0x20, 0x00, 0xaf, 0x24, 0xd0, 0x00, 0x00, 0x00, 0x03, 0x00, 0x9d, 0x24, 0xd0, 0x00, 0x00, 0x00, +0x25, 0x00, 0x6d, 0x05, 0xf0, 0x00, 0x00, 0x00, 0xa3, 0x00, 0x1f, 0xff, 0xd7, 0x00, 0x00, 0x00, +0x37, 0x69, 0x53, 0x08, 0xe8, 0x00, 0x00, 0x00, 0xa1, 0x41, 0x0a, 0x3a, 0x84, 0x00, 0x00, 0x00, +0x00, 0x46, 0x71, 0x08, 0xed, 0x00, 0x00, 0x00, 0x00, 0x48, 0x28, 0x8b, 0x51, 0x00, 0x00, 0x00, +0x00, 0x42, 0x09, 0x60, 0x12, 0x00, 0x00, 0x00, 0x92, 0x40, 0x0a, 0x52, 0x22, 0x00, 0x00, 0x00, +0x17, 0x81, 0x36, 0x0b, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x80, 0x66, 0x0b, 0x68, 0x00, 0x00, 0x00, +0x00, 0xc4, 0x06, 0x40, 0x6a, 0x00, 0x00, 0x00, 0x00, 0x44, 0x01, 0x80, 0x6f, 0x00, 0x00, 0x00, +0x00, 0x40, 0x01, 0xe0, 0x14, 0x00, 0x00, 0x00, 0xb7, 0xda, 0x66, 0xb1, 0x6d, 0x00, 0x00, 0x00, +0x00, 0xa4, 0x06, 0xa0, 0x6d, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x06, 0x40, 0x6c, 0x00, 0x00, 0x00, +0x00, 0x4e, 0x01, 0x40, 0x14, 0x00, 0x00, 0x00, 0x17, 0x6d, 0x06, 0xa0, 0x14, 0x00, 0x00, 0x00, +0x93, 0x00, 0x1f, 0x92, 0xb4, 0x00, 0x00, 0x00, 0x7e, 0xff, 0x5c, 0x08, 0xea, 0x00, 0x00, 0x00, +0x00, 0x40, 0x4a, 0x67, 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b/drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsb.h new file mode 100644 index 0000000..a117ec1 --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsb.h @@ -0,0 +1,752 @@ +/*----------------------------------------------------------------------------- +* DESCRIPTION: +* Contains firmware version: 1.0.8 +* +* USAGE: +* Include. +* +* NOTES: +* (c) 2009 Trident Microsystems, Inc. - All rights reserved. +* +* This software and related documentation (the 'Software') are intellectual +* property owned by Trident and are copyright of Trident, unless specifically +* noted otherwise. +* +* Any use of the Software is permitted only pursuant to the terms of the +* license agreement, if any, which accompanies, is included with or applicable +* to the Software ('License Agreement') or upon express written consent of +* Trident. Any copying, reproduction or redistribution of the Software in +* whole or in part by any means not in accordance with the License Agreement +* or as agreed in writing by Trident is expressly prohibited. +* +* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE +* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE +* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND +* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES +* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT +* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL +* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY +* TO USE THE SOFTWARE. +* +* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, +* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, +* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS +* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE +* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM +* TRIDENT'S NEGLIGENCE. +* +* IN NO EVENT SHALL MICRONAS BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, +* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, +* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS +* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE +* INABILITY TO USE THE SOFTWARE, EVEN IF MICRONAS HAS BEEN ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM +* MICRONAS' NEGLIGENCE. +* +----------------------------------------------------------------------------*/ + +#ifndef __DRXJ_MC_VSB_H__ +#define __DRXJ_MC_VSB_H__ + +#define DRXJ_MC_VSB ((pu8_t) drxj_mc_vsb_g) + +const u8_t drxj_mc_vsb_g[] = { +0x48, 0x4c, 0x00, 0x03, 0x00, 0x00, 0x2b, 0x62, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x82, +0x00, 0x00, 0x15, 0x9e, 0x00, 0x01, 0x92, 0x3b, 0x2a, 0x02, 0xe4, 0xf8, 0x7f, 0x90, 0xf0, 0xf8, +0xf0, 0xa3, 0x02, 0x22, 0xa6, 0x15, 0x23, 0x7f, 0x71, 0x7e, 0x29, 0x12, 0x90, 0x61, 0x19, 0x7b, +0xf0, 0xef, 0xd0, 0xc0, 0xaf, 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0x03, 0x94, 0x00, 0xd9, 0x00, 0x10, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00 +}; + +#endif /* __DRXJ_MC_VSB_H__ */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsbqam.h b/drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsbqam.h new file mode 100644 index 0000000..4ef0a07 --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsbqam.h @@ -0,0 +1,1444 @@ +/*----------------------------------------------------------------------------- +* DESCRIPTION: +* Contains firmware version: 1.0.8 +* +* USAGE: +* Include. +* +* NOTES: +* (c) 2009 Trident Microsystems, Inc. - All rights reserved. +* +* This software and related documentation (the 'Software') are intellectual +* property owned by Trident and are copyright of Trident, unless specifically +* noted otherwise. +* +* Any use of the Software is permitted only pursuant to the terms of the +* license agreement, if any, which accompanies, is included with or applicable +* to the Software ('License Agreement') or upon express written consent of +* Trident. Any copying, reproduction or redistribution of the Software in +* whole or in part by any means not in accordance with the License Agreement +* or as agreed in writing by Trident is expressly prohibited. +* +* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE +* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE +* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND +* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES +* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT +* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL +* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY +* TO USE THE SOFTWARE. +* +* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, +* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, +* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS +* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE +* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM +* TRIDENT'S NEGLIGENCE. +* +* IN NO EVENT SHALL MICRONAS BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, +* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, +* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS +* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE +* INABILITY TO USE THE SOFTWARE, EVEN IF MICRONAS HAS BEEN ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM +* MICRONAS' NEGLIGENCE. +* +----------------------------------------------------------------------------*/ + +#ifndef __DRXJ_MC_VSBQAM_H__ +#define __DRXJ_MC_VSBQAM_H__ + +#define DRXJ_MC_VSBQAM ((pu8_t) drxj_mc_vsbqam_g) + +const u8_t drxj_mc_vsbqam_g[] = { +0x48, 0x4c, 0x00, 0x04, 0x00, 0x00, 0x56, 0xa0, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x82, +0x00, 0x00, 0x20, 0x00, 0x00, 0x01, 0xc4, 0x4d, 0x55, 0x02, 0xe4, 0xee, 0x7f, 0x90, 0xf0, 0xf8, +0xf0, 0xa3, 0x02, 0x22, 0x4b, 0x23, 0xd0, 0xc0, 0xaf, 0xa2, 0xd1, 0x92, 0xaf, 0xc2, 0xa8, 0x53, +0x53, 0xfb, 0xef, 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0x00, 0xff, 0x5b, 0xca, 0xff, 0x90, 0xe0, 0x4b, 0x7b, +0x2f, 0x74, 0x90, 0xf0, 0xf2, 0x7e, 0xa3, 0xe0, 0x25, 0xe0, 0x04, 0xe0, 0x7b, 0x90, 0xf0, 0x58, +0x3a, 0x02, 0x7d, 0x9a, 0x7c, 0x16, 0x7f, 0x71, 0x7e, 0x04, 0x12, 0x00, 0xf5, 0x53, 0x18, 0x7d, +0x71, 0x7c, 0x03, 0x7f, 0x00, 0x7e, 0x53, 0x02, 0x30, 0xf5, 0xfd, 0x40, 0x40, 0xc2, 0xd3, 0x8e, +0xd2, 0x8f, 0x24, 0xed, 0xff, 0xff, 0x34, 0xec, 0xf5, 0xff, 0x8f, 0xda, 0x22, 0xd9, 0xa9, 0x53, +0x53, 0xe7, 0xf7, 0xab, 0x04, 0x7f, 0x25, 0x12, 0xc2, 0x01, 0xe4, 0x62, 0x7f, 0x90, 0xf0, 0xf8, +0xf0, 0xa3, 0x90, 0x22, 0x66, 0x7f, 0x1f, 0x74, 0xa3, 0xf0, 0x7f, 0x74, 0xe4, 0xf0, 0x7f, 0x90, +0xf0, 0xf8, 0xf0, 0xa3, 0x30, 0x22, 0xfd, 0x40, 0x40, 0xc2, 0x54, 0xef, 0x8e, 0xfe, 0xf5, 0xc2, +0x8c, 0xc1, 0x8d, 0xc3, 0x22, 0xc5, 0x7a, 0x90, 0xe0, 0xbd, 0x90, 0x04, 0xe9, 0x7b, 0x60, 0xf0, +0xe0, 0x05, 0x7a, 0x90, 0xf0, 0xbd, 0x12, 0x22, 0x79, 0x00, 0x55, 0x12, 0x12, 0x41, 0xfa, 0x55, +0x4a, 0x12, 0x02, 0x63, 0x5b, 0x48, 0x40, 0xc2, 0x54, 0xef, 0x8e, 0xfe, 0xf5, 0xc2, 0x8c, 0xc1, +0x8d, 0xc3, 0x22, 0xc4, 0x90, 0xe4, 0x66, 0x7f, 0xa3, 0xf0, 0x90, 0xf0, 0xf8, 0x7f, 0xa3, 0xf0, +0x22, 0xf0, 0x7a, 0x90, 0xe0, 0xbd, 0x7a, 0x90, 0xf0, 0xbe, 0x90, 0xe4, 0xbd, 0x7a, 0x22, 0xf0, +0x7f, 0x78, 0xf6, 0xe4, 0xfd, 0xd8, 0x81, 0x75, 0x02, 0x3f, 0x3e, 0x24, 0x06, 0x7d, 0x90, 0x7c, +0x02, 0x7f, 0x00, 0x7e, 0x53, 0x02, 0x8e, 0xf5, 0x8f, 0x82, 0xa3, 0x83, 0x82, 0xae, 0x83, 0xaf, +0x20, 0x22, 0x00, 0x59, 0x00, 0x00, 0x00, 0x00, 0x33, 0x00, 0x74, 0x92, 0x90, 0xff, 0xf8, 0x7f, +0xa3, 0xf0, 0x22, 0xf0, 0x90, 0xe4, 0xf8, 0x7f, 0xa3, 0xf0, 0x22, 0xf0, 0x90, 0xe4, 0xf8, 0x7f, +0xa3, 0xf0, 0x22, 0xf0, 0x90, 0xe4, 0xf8, 0x7f, 0xa3, 0xf0, 0x22, 0xf0, 0x90, 0xe4, 0xf8, 0x7f, +0xa3, 0xf0, 0x22, 0xf0, 0x90, 0xe4, 0xf8, 0x7f, 0xa3, 0xf0, 0x22, 0xf0, 0x90, 0xe4, 0xf8, 0x7f, +0xa3, 0xf0, 0x22, 0xf0, 0x90, 0xe4, 0xf8, 0x7f, 0xa3, 0xf0, 0x22, 0xf0, 0x90, 0xe4, 0xf8, 0x7f, +0xa3, 0xf0, 0x22, 0xf0, 0x90, 0xe4, 0xf8, 0x7f, 0xa3, 0xf0, 0x22, 0xf0, 0x00, 0x02, 0x02, 0x4a, +0xef, 0x52, 0x00, 0x83, 0x1f, 0xfe, 0x00, 0x02, 0x00, 0x01, 0xe8, 0x03, 0x10, 0x00, 0x08, 0x00, +0x80, 0x00, 0x03, 0x94, 0x00, 0xd9, 0x00, 0x10, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00 +}; + +#endif /* __DRXJ_MC_VSBQAM_H__ */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj_options.h b/drivers/media/dvb-frontends/drx39xyj/drxj_options.h new file mode 100644 index 0000000..9299551 --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/drxj_options.h @@ -0,0 +1,68 @@ +/** +* \file $Id: drxj_options.h,v 1.5 2009/10/05 21:32:49 dingtao Exp $ +* +* \brief DRXJ optional settings +* +* \author Tao Ding +*/ + +/* +* $(c) 2006-2007,2009 Trident Microsystems, Inc. - All rights reserved. +* +* This software and related documentation (the 'Software') are intellectual +* property owned by Trident and are copyright of Trident, unless specifically +* noted otherwise. +* +* Any use of the Software is permitted only pursuant to the terms of the +* license agreement, if any, which accompanies, is included with or applicable +* to the Software ('License Agreement') or upon express written consent of +* Trident. Any copying, reproduction or redistribution of the Software in +* whole or in part by any means not in accordance with the License Agreement +* or as agreed in writing by Trident is expressly prohibited. +* +* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE +* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE +* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND +* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES +* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT +* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL +* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY +* TO USE THE SOFTWARE. +* +* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, +* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, +* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS +* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE +* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM +* TRIDENT'S NEGLIGENCE. $ +* +*/ + +/* Note: Please add preprocessor DRXJ_OPTIONS_H for drxj.c to include this file */ +#ifndef __DRXJ_OPTIONS_H__ +#define __DRXJ_OPTIONS_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* #define DRXJ_DIGITAL_ONLY */ +/* #define DRXJ_VSB_ONLY */ +/* #define DRXJ_SIGNAL_ACCUM_ERR */ +/* #define MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH 0x03 */ +/* #define MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH 0x04 */ +/* #define MPEG_OUTPUT_CLK_DRIVE_STRENGTH 0x05 */ +/* #define OOB_CRX_DRIVE_STRENGTH 0x04 */ +/* #define OOB_DRX_DRIVE_STRENGTH 0x05 */ +/* #define DRXJ_QAM_MAX_WAITTIME 1000 */ +/* #define DRXJ_QAM_FEC_LOCK_WAITTIME 200 */ +/* #define DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME 250 */ + +/*------------------------------------------------------------------------- +THE END +-------------------------------------------------------------------------*/ +#ifdef __cplusplus +} +#endif +#endif /* __DRXJ_OPTIONS_H__ */ diff --git a/drivers/media/usb/em28xx/em28xx-cards.c b/drivers/media/usb/em28xx/em28xx-cards.c index 1752e7e..ed0edfd 100644 --- a/drivers/media/usb/em28xx/em28xx-cards.c +++ b/drivers/media/usb/em28xx/em28xx-cards.c @@ -214,6 +214,17 @@ static struct em28xx_reg_seq terratec_cinergy_USB_XS_FR_digital[] = { { -1, -1, -1, -1}, }; +/* PCTV HD Mini (80e) GPIOs + 0-5: not used + 6: demod reset, active low + 7: LED on, active high */ +static struct em28xx_reg_seq em2874_pctv_80e_digital[] = { + {EM28XX_R06_I2C_CLK, 0x45, 0xff, 10}, /*400 KHz*/ + {EM2874_R80_GPIO_P0_CTRL, 0x80, 0xff, 100},/*Demod reset*/ + {EM2874_R80_GPIO_P0_CTRL, 0xc0, 0xff, 10}, + { -1, -1, -1, -1}, +}; + /* eb1a:2868 Reddo DVB-C USB TV Box GPIO4 - CU1216L NIM Other GPIOs seems to be don't care. */ @@ -2128,6 +2139,13 @@ struct em28xx_board em28xx_boards[] = { .tuner_gpio = default_tuner_gpio, .def_i2c_bus = 1, }, + [EM2874_BOARD_PCTV_HD_MINI_80E] = { + .name = "Pinnacle PCTV HD Mini", + .tuner_type = TUNER_ABSENT, + .has_dvb = 1, + .dvb_gpio = em2874_pctv_80e_digital, + .decoder = EM28XX_NODECODER, + }, /* 1ae7:9003/9004 SpeedLink Vicious And Devine Laplace webcam * Empia EM2765 + OmniVision OV2640 */ [EM2765_BOARD_SPEEDLINK_VAD_LAPLACE] = { @@ -2290,6 +2308,8 @@ struct usb_device_id em28xx_id_table[] = { .driver_info = EM2882_BOARD_PINNACLE_HYBRID_PRO_330E }, { USB_DEVICE(0x2304, 0x0227), .driver_info = EM2880_BOARD_PINNACLE_PCTV_HD_PRO }, + { USB_DEVICE(0x2304, 0x023f), + .driver_info = EM2874_BOARD_PCTV_HD_MINI_80E }, { USB_DEVICE(0x0413, 0x6023), .driver_info = EM2800_BOARD_LEADTEK_WINFAST_USBII }, { USB_DEVICE(0x093b, 0xa003), diff --git a/drivers/media/usb/em28xx/em28xx-dvb.c b/drivers/media/usb/em28xx/em28xx-dvb.c index 16c4d58..a63a3a2 100644 --- a/drivers/media/usb/em28xx/em28xx-dvb.c +++ b/drivers/media/usb/em28xx/em28xx-dvb.c @@ -41,6 +41,7 @@ #include "mt352.h" #include "mt352_priv.h" /* FIXME */ #include "tda1002x.h" +#include "drx39xyj/drx39xxj.h" #include "tda18271.h" #include "s921.h" #include "drxd.h" @@ -821,6 +822,20 @@ static const struct m88ds3103_config pctv_461e_m88ds3103_config = { .agc = 0x99, }; + +static struct tda18271_std_map drx_j_std_map = { + .atsc_6 = { .if_freq = 5000, .agc_mode = 3, .std = 0, .if_lvl = 1, + .rfagc_top = 0x37, }, + .qam_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3, .if_lvl = 1, + .rfagc_top = 0x37, }, +}; + +static struct tda18271_config pinnacle_80e_dvb_config = { + .std_map = &drx_j_std_map, + .gate = TDA18271_GATE_DIGITAL, + .role = TDA18271_MASTER, +}; + /* ------------------------------------------------------------------ */ static int em28xx_attach_xc3028(u8 addr, struct em28xx *dev) @@ -1374,6 +1389,18 @@ static int em28xx_dvb_init(struct em28xx *dev) goto out_free; } break; + case EM2874_BOARD_PCTV_HD_MINI_80E: + dvb->fe[0] = dvb_attach(drx39xxj_attach, &dev->i2c_adap[dev->def_i2c_bus]); + if (dvb->fe[0] != NULL) { + dvb->fe[0] = dvb_attach(tda18271_attach, dvb->fe[0], 0x60, + &dev->i2c_adap[dev->def_i2c_bus], + &pinnacle_80e_dvb_config); + if (!dvb->fe[0]) { + result = -EINVAL; + goto out_free; + } + } + break; case EM28178_BOARD_PCTV_461E: { /* demod I2C adapter */ diff --git a/drivers/media/usb/em28xx/em28xx.h b/drivers/media/usb/em28xx/em28xx.h index 9b02f15..90e7cec 100644 --- a/drivers/media/usb/em28xx/em28xx.h +++ b/drivers/media/usb/em28xx/em28xx.h @@ -104,6 +104,7 @@ #define EM2882_BOARD_PINNACLE_HYBRID_PRO_330E 56 #define EM2883_BOARD_KWORLD_HYBRID_330U 57 #define EM2820_BOARD_COMPRO_VIDEOMATE_FORYOU 58 +#define EM2874_BOARD_PCTV_HD_MINI_80E 59 #define EM2883_BOARD_HAUPPAUGE_WINTV_HVR_850 60 #define EM2820_BOARD_PROLINK_PLAYTV_BOX4_USB2 61 #define EM2820_BOARD_GADMEI_TVR200 62 -- cgit v1.1 From ca3355a94755cad2a334354b1a9bcbab9239bec9 Mon Sep 17 00:00:00 2001 From: Devin Heitmueller Date: Sun, 4 Jul 2010 18:42:11 -0300 Subject: [media] drx-j: put under 3-clause BSD license Relicense the drx-j driver under a standard 3-clause BSD license, which makes it GPL compatible. This was done explicitly with permission from Trident Microsystems. Signed-off-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/bsp_host.h | 62 ++++++++++--------- drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h | 63 ++++++++++--------- drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h | 63 ++++++++++--------- drivers/media/dvb-frontends/drx39xyj/bsp_types.h | 62 ++++++++++--------- drivers/media/dvb-frontends/drx39xyj/drx39xxj.c | 2 +- drivers/media/dvb-frontends/drx39xyj/drx39xxj.h | 2 +- .../media/dvb-frontends/drx39xyj/drx_dap_fasi.c | 59 +++++++++--------- .../media/dvb-frontends/drx39xyj/drx_dap_fasi.h | 59 +++++++++--------- drivers/media/dvb-frontends/drx39xyj/drx_driver.c | 60 +++++++++---------- drivers/media/dvb-frontends/drx39xyj/drx_driver.h | 60 +++++++++---------- .../dvb-frontends/drx39xyj/drx_driver_version.h | 63 ++++++++++--------- drivers/media/dvb-frontends/drx39xyj/drxj.c | 63 ++++++++++--------- drivers/media/dvb-frontends/drx39xyj/drxj.h | 62 ++++++++++--------- drivers/media/dvb-frontends/drx39xyj/drxj_map.h | 53 +++++++++------- drivers/media/dvb-frontends/drx39xyj/drxj_mc.h | 70 ++++++++++------------ drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsb.h | 68 ++++++++++----------- .../media/dvb-frontends/drx39xyj/drxj_mc_vsbqam.h | 67 ++++++++++----------- .../media/dvb-frontends/drx39xyj/drxj_options.h | 63 ++++++++++--------- 18 files changed, 484 insertions(+), 517 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/bsp_host.h b/drivers/media/dvb-frontends/drx39xyj/bsp_host.h index 30f711d..95b5232 100644 --- a/drivers/media/dvb-frontends/drx39xyj/bsp_host.h +++ b/drivers/media/dvb-frontends/drx39xyj/bsp_host.h @@ -1,3 +1,33 @@ +/* + Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + * Neither the name of Trident Microsystems nor Hauppauge Computer Works + nor the names of its contributors may be used to endorse or promote + products derived from this software without specific prior written + permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. +*/ + /** * \file $Id: bsp_host.h,v 1.3 2009/07/07 14:20:30 justin Exp $ * @@ -5,38 +35,6 @@ * */ -/* -* $(c) 2004-2005,2007-2009 Trident Microsystems, Inc. - All rights reserved. -* -* This software and related documentation (the 'Software') are intellectual -* property owned by Trident and are copyright of Trident, unless specifically -* noted otherwise. -* -* Any use of the Software is permitted only pursuant to the terms of the -* license agreement, if any, which accompanies, is included with or applicable -* to the Software ('License Agreement') or upon express written consent of -* Trident. Any copying, reproduction or redistribution of the Software in -* whole or in part by any means not in accordance with the License Agreement -* or as agreed in writing by Trident is expressly prohibited. -* -* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE -* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE -* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND -* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES -* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT -* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL -* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY -* TO USE THE SOFTWARE. -* -* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, -* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, -* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS -* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE -* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM -* TRIDENT'S NEGLIGENCE. $ -* -*/ #ifndef __DRXBSP_HOST_H__ #define __DRXBSP_HOST_H__ /*------------------------------------------------------------------------- diff --git a/drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h b/drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h index 6f4e69f..25207c8 100644 --- a/drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h +++ b/drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h @@ -1,3 +1,33 @@ +/* + Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + * Neither the name of Trident Microsystems nor Hauppauge Computer Works + nor the names of its contributors may be used to endorse or promote + products derived from this software without specific prior written + permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. +*/ + /** * \file $Id: bsp_i2c.h,v 1.5 2009/07/07 14:20:30 justin Exp $ * @@ -12,39 +42,6 @@ * */ -/* -* $(c) 2004-2005,2008-2009 Trident Microsystems, Inc. - All rights reserved. -* -* This software and related documentation (the 'Software') are intellectual -* property owned by Trident and are copyright of Trident, unless specifically -* noted otherwise. -* -* Any use of the Software is permitted only pursuant to the terms of the -* license agreement, if any, which accompanies, is included with or applicable -* to the Software ('License Agreement') or upon express written consent of -* Trident. Any copying, reproduction or redistribution of the Software in -* whole or in part by any means not in accordance with the License Agreement -* or as agreed in writing by Trident is expressly prohibited. -* -* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE -* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE -* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND -* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES -* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT -* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL -* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY -* TO USE THE SOFTWARE. -* -* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, -* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, -* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS -* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE -* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM -* TRIDENT'S NEGLIGENCE. $ -* -*/ - #ifndef __BSPI2C_H__ #define __BSPI2C_H__ /*------------------------------------------------------------------------------ diff --git a/drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h b/drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h index e5693d0..668f988 100644 --- a/drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h +++ b/drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h @@ -1,3 +1,33 @@ +/* + Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + * Neither the name of Trident Microsystems nor Hauppauge Computer Works + nor the names of its contributors may be used to endorse or promote + products derived from this software without specific prior written + permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. +*/ + /** * \file $Id: bsp_tuner.h,v 1.5 2009/10/19 22:15:13 dingtao Exp $ * @@ -5,39 +35,6 @@ * */ -/* -* $(c) 2004-2006,2008-2009 Trident Microsystems, Inc. - All rights reserved. -* -* This software and related documentation (the 'Software') are intellectual -* property owned by Trident and are copyright of Trident, unless specifically -* noted otherwise. -* -* Any use of the Software is permitted only pursuant to the terms of the -* license agreement, if any, which accompanies, is included with or applicable -* to the Software ('License Agreement') or upon express written consent of -* Trident. Any copying, reproduction or redistribution of the Software in -* whole or in part by any means not in accordance with the License Agreement -* or as agreed in writing by Trident is expressly prohibited. -* -* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE -* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE -* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND -* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES -* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT -* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL -* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY -* TO USE THE SOFTWARE. -* -* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, -* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, -* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS -* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE -* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM -* TRIDENT'S NEGLIGENCE. $ -* -*/ - #ifndef __DRXBSP_TUNER_H__ #define __DRXBSP_TUNER_H__ /*------------------------------------------------------------------------------ diff --git a/drivers/media/dvb-frontends/drx39xyj/bsp_types.h b/drivers/media/dvb-frontends/drx39xyj/bsp_types.h index 4a0dc0b..15a483d 100644 --- a/drivers/media/dvb-frontends/drx39xyj/bsp_types.h +++ b/drivers/media/dvb-frontends/drx39xyj/bsp_types.h @@ -1,3 +1,33 @@ +/* + Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + * Neither the name of Trident Microsystems nor Hauppauge Computer Works + nor the names of its contributors may be used to endorse or promote + products derived from this software without specific prior written + permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. +*/ + /** * \file $Id: bsp_types.h,v 1.5 2009/08/06 12:55:57 carlo Exp $ * @@ -9,38 +39,6 @@ * */ -/* -* $(c) 2004-2006,2008-2009 Trident Microsystems, Inc. - All rights reserved. -* -* This software and related documentation (the 'Software') are intellectual -* property owned by Trident and are copyright of Trident, unless specifically -* noted otherwise. -* -* Any use of the Software is permitted only pursuant to the terms of the -* license agreement, if any, which accompanies, is included with or applicable -* to the Software ('License Agreement') or upon express written consent of -* Trident. Any copying, reproduction or redistribution of the Software in -* whole or in part by any means not in accordance with the License Agreement -* or as agreed in writing by Trident is expressly prohibited. -* -* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE -* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE -* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND -* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES -* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT -* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL -* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY -* TO USE THE SOFTWARE. -* -* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, -* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, -* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS -* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE -* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM -* TRIDENT'S NEGLIGENCE. $ -* -*/ #ifndef __BSP_TYPES_H__ #define __BSP_TYPES_H__ /*------------------------------------------------------------------------- diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c index 524c07d..36db20a8e 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c @@ -1,7 +1,7 @@ /* * Driver for Micronas DRX39xx family (drx3933j) * - * Written by Devin Heitmueller + * Written by Devin Heitmueller * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h index eea6a01a..c29cd43 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h @@ -1,7 +1,7 @@ /* * Driver for Micronas DRX39xx family (drx3933j) * - * Written by Devin Heitmueller + * Written by Devin Heitmueller * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c index cc10dae..8289b90 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c @@ -1,3 +1,33 @@ +/* + Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + * Neither the name of Trident Microsystems nor Hauppauge Computer Works + nor the names of its contributors may be used to endorse or promote + products derived from this software without specific prior written + permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. +*/ + /******************************************************************************* * FILENAME: $Id: drx_dap_fasi.c,v 1.7 2009/12/28 14:36:21 carlo Exp $ * @@ -15,35 +45,6 @@ * - * * NOTES: -* $(c) 2009 Trident Microsystems, Inc. - All rights reserved. -* -* This software and related documentation (the 'Software') are intellectual -* property owned by Trident and are copyright of Trident, unless specifically -* noted otherwise. -* -* Any use of the Software is permitted only pursuant to the terms of the -* license agreement, if any, which accompanies, is included with or applicable -* to the Software ('License Agreement') or upon express written consent of -* Trident. Any copying, reproduction or redistribution of the Software in -* whole or in part by any means not in accordance with the License Agreement -* or as agreed in writing by Trident is expressly prohibited. -* -* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE -* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE -* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND -* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES -* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT -* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL -* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY -* TO USE THE SOFTWARE. -* -* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, -* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, -* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS -* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE -* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM -* TRIDENT'S NEGLIGENCE. $ * * *******************************************************************************/ diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.h b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.h index 77ff371..4429ef7 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.h @@ -1,3 +1,33 @@ +/* + Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + * Neither the name of Trident Microsystems nor Hauppauge Computer Works + nor the names of its contributors may be used to endorse or promote + products derived from this software without specific prior written + permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. +*/ + /******************************************************************************* * FILENAME: $Id: drx_dap_fasi.h,v 1.5 2009/07/07 14:21:40 justin Exp $ * @@ -11,35 +41,6 @@ * Include. * * NOTES: -* $(c) 2008-2009 Trident Microsystems, Inc. - All rights reserved. -* -* This software and related documentation (the 'Software') are intellectual -* property owned by Trident and are copyright of Trident, unless specifically -* noted otherwise. -* -* Any use of the Software is permitted only pursuant to the terms of the -* license agreement, if any, which accompanies, is included with or applicable -* to the Software ('License Agreement') or upon express written consent of -* Trident. Any copying, reproduction or redistribution of the Software in -* whole or in part by any means not in accordance with the License Agreement -* or as agreed in writing by Trident is expressly prohibited. -* -* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE -* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE -* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND -* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES -* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT -* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL -* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY -* TO USE THE SOFTWARE. -* -* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, -* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, -* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS -* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE -* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM -* TRIDENT'S NEGLIGENCE. $ * * *******************************************************************************/ diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c index 7b02841..84c7dd4 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c @@ -1,38 +1,38 @@ +/* + Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + * Neither the name of Trident Microsystems nor Hauppauge Computer Works + nor the names of its contributors may be used to endorse or promote + products derived from this software without specific prior written + permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. +*/ + /** * \file $Id: drx_driver.c,v 1.40 2010/01/12 01:24:56 lfeng Exp $ * * \brief Generic DRX functionality, DRX driver core. * -* $(c) 2004-2010 Trident Microsystems, Inc. - All rights reserved. -* -* This software and related documentation (the 'Software') are intellectual -* property owned by Trident and are copyright of Trident, unless specifically -* noted otherwise. -* -* Any use of the Software is permitted only pursuant to the terms of the -* license agreement, if any, which accompanies, is included with or applicable -* to the Software ('License Agreement') or upon express written consent of -* Trident. Any copying, reproduction or redistribution of the Software in -* whole or in part by any means not in accordance with the License Agreement -* or as agreed in writing by Trident is expressly prohibited. -* -* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE -* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE -* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND -* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES -* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT -* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL -* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY -* TO USE THE SOFTWARE. -* -* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, -* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, -* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS -* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE -* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM -* TRIDENT'S NEGLIGENCE. $ -* */ /*------------------------------------------------------------------------------ diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h index d3bfe06..0533344 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h @@ -1,38 +1,38 @@ +/* + Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + * Neither the name of Trident Microsystems nor Hauppauge Computer Works + nor the names of its contributors may be used to endorse or promote + products derived from this software without specific prior written + permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. +*/ + /** * \file $Id: drx_driver.h,v 1.84 2010/01/14 22:47:50 dingtao Exp $ * * \brief DRX driver API * -* $(c) 2004-2010 Trident Microsystems, Inc. - All rights reserved. -* -* This software and related documentation (the 'Software') are intellectual -* property owned by Trident and are copyright of Trident, unless specifically -* noted otherwise. -* -* Any use of the Software is permitted only pursuant to the terms of the -* license agreement, if any, which accompanies, is included with or applicable -* to the Software ('License Agreement') or upon express written consent of -* Trident. Any copying, reproduction or redistribution of the Software in -* whole or in part by any means not in accordance with the License Agreement -* or as agreed in writing by Trident is expressly prohibited. -* -* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE -* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE -* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND -* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES -* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT -* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL -* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY -* TO USE THE SOFTWARE. -* -* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, -* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, -* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS -* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE -* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM -* TRIDENT'S NEGLIGENCE. $ -* */ #ifndef __DRXDRIVER_H__ #define __DRXDRIVER_H__ diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver_version.h b/drivers/media/dvb-frontends/drx39xyj/drx_driver_version.h index e6c777c..fd2b278 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver_version.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver_version.h @@ -9,40 +9,39 @@ * Output start: [entry point] * * filename last modified re-use - * ----------------------------------------------------- - * version.idf Mon Jan 18 11:56:10 2010 - - * - * $(c) 2010 Trident Microsystems, Inc. - All rights reserved. - * - * This software and related documentation (the 'Software') are intellectual - * property owned by Trident and are copyright of Trident, unless specifically - * noted otherwise. * - * Any use of the Software is permitted only pursuant to the terms of the - * license agreement, if any, which accompanies, is included with or applicable - * to the Software ('License Agreement') or upon express written consent of - * Trident. Any copying, reproduction or redistribution of the Software in - * whole or in part by any means not in accordance with the License Agreement - * or as agreed in writing by Trident is expressly prohibited. - * - * THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE - * LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE - * IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND - * CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES AND - * CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT - * ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL - * PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY TO - * USE THE SOFTWARE. - * - * IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, - * PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, - * DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF - * BUSINESS INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF - * OR THE INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING - * FROM TRIDENT'S NEGLIGENCE. $ + Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + * Neither the name of Trident Microsystems nor Hauppauge Computer Works + nor the names of its contributors may be used to endorse or promote + products derived from this software without specific prior written + permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. +*/ + +/* ----------------------------------------------------- + * version.idf Mon Jan 18 11:56:10 2010 - * - ******************************************************************************* */ #ifndef __DRX_DRIVER_VERSION__H__ diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index a83f2ad..b4c70ac 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -1,3 +1,33 @@ +/* + Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + * Neither the name of Trident Microsystems nor Hauppauge Computer Works + nor the names of its contributors may be used to endorse or promote + products derived from this software without specific prior written + permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. +*/ + /** * \file $Id: drxj.c,v 1.637 2010/01/18 17:21:10 dingtao Exp $ * @@ -6,39 +36,6 @@ * \author Dragan Savic, Milos Nikolic, Mihajlo Katona, Tao Ding, Paul Janssen */ -/* -* $(c) 2006-2010 Trident Microsystems, Inc. - All rights reserved. -* -* This software and related documentation (the 'Software') are intellectual -* property owned by Trident and are copyright of Trident, unless specifically -* noted otherwise. -* -* Any use of the Software is permitted only pursuant to the terms of the -* license agreement, if any, which accompanies, is included with or applicable -* to the Software ('License Agreement') or upon express written consent of -* Trident. Any copying, reproduction or redistribution of the Software in -* whole or in part by any means not in accordance with the License Agreement -* or as agreed in writing by Trident is expressly prohibited. -* -* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE -* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE -* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND -* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES -* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT -* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL -* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY -* TO USE THE SOFTWARE. -* -* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, -* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, -* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS -* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE -* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM -* TRIDENT'S NEGLIGENCE. $ -* -*/ - /*----------------------------------------------------------------------------- INCLUDE FILES ----------------------------------------------------------------------------*/ diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.h b/drivers/media/dvb-frontends/drx39xyj/drxj.h index ee7aa6a..cb6cc3f 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.h +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.h @@ -1,3 +1,33 @@ +/* + Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + * Neither the name of Trident Microsystems nor Hauppauge Computer Works + nor the names of its contributors may be used to endorse or promote + products derived from this software without specific prior written + permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. +*/ + /** * \file $Id: drxj.h,v 1.132 2009/12/22 12:13:48 danielg Exp $ * @@ -6,38 +36,6 @@ * \author Dragan Savic, Milos Nikolic, Mihajlo Katona, Tao Ding, Paul Janssen */ -/* -* $(c) 2006-2009 Trident Microsystems, Inc. - All rights reserved. -* -* This software and related documentation (the 'Software') are intellectual -* property owned by Trident and are copyright of Trident, unless specifically -* noted otherwise. -* -* Any use of the Software is permitted only pursuant to the terms of the -* license agreement, if any, which accompanies, is included with or applicable -* to the Software ('License Agreement') or upon express written consent of -* Trident. Any copying, reproduction or redistribution of the Software in -* whole or in part by any means not in accordance with the License Agreement -* or as agreed in writing by Trident is expressly prohibited. -* -* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE -* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE -* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND -* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES -* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT -* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL -* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY -* TO USE THE SOFTWARE. -* -* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, -* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, -* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS -* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE -* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM -* TRIDENT'S NEGLIGENCE. $ -* -*/ #ifndef __DRXJ_H__ #define __DRXJ_H__ /*------------------------------------------------------------------------- diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj_map.h b/drivers/media/dvb-frontends/drx39xyj/drxj_map.h index 941aa14..35ecaae 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj_map.h +++ b/drivers/media/dvb-frontends/drx39xyj/drxj_map.h @@ -1,4 +1,34 @@ /* + Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + * Neither the name of Trident Microsystems nor Hauppauge Computer Works + nor the names of its contributors may be used to endorse or promote + products derived from this software without specific prior written + permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. +*/ + +/* *********************************************************************************************************************** * WARNING - THIS FILE HAS BEEN GENERATED - DO NOT CHANGE * @@ -12,29 +42,6 @@ * ----------------------------------------------------- * reg_map.1.tmp Mon Jan 18 12:09:24 2010 - * - * $(c) 2010 Trident Microsystems, Inc. - All rights reserved. - * - * This software and related documentation (the 'Software') are intellectual property owned by Trident and are - * copyright of Trident, unless specifically noted otherwise. - * - * Any use of the Software is permitted only pursuant to the terms of the license agreement, if any, which accompanies, - * is included with or applicable to the Software ('License Agreement') or upon express written consent of Trident. Any - * copying, reproduction or redistribution of the Software in whole or in part by any means not in accordance with the - * License Agreement or as agreed in writing by Trident is expressly prohibited. - * - * THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE LICENSE AGREEMENT. EXCEPT AS WARRANTED IN - * THE LICENSE AGREEMENT THE SOFTWARE IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS - * WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A - * PARTICULAR PURPOSE, QUIT ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL PROPERTY OR OTHER - * RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY TO USE THE SOFTWARE. - * - * IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, PUNITIVE, SPECIAL OR OTHER DAMAGES - * WHATSOEVER INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF - * BUSINESS INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE INABILITY TO USE THE SOFTWARE, - * EVEN IF TRIDENT HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM - * TRIDENT'S NEGLIGENCE. $ - * - *********************************************************************************************************************** */ #ifndef __DRXJ_MAP__H__ diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj_mc.h b/drivers/media/dvb-frontends/drx39xyj/drxj_mc.h index 8be8272..cecc31d 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj_mc.h +++ b/drivers/media/dvb-frontends/drx39xyj/drxj_mc.h @@ -1,3 +1,33 @@ +/* + Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + * Neither the name of Trident Microsystems nor Hauppauge Computer Works + nor the names of its contributors may be used to endorse or promote + products derived from this software without specific prior written + permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. +*/ + /*----------------------------------------------------------------------------- * DESCRIPTION: * Contains firmware version: 1.0.8 @@ -6,45 +36,7 @@ * Include. * * NOTES: -* (c) 2009 Trident Microsystems, Inc. - All rights reserved. -* -* This software and related documentation (the 'Software') are intellectual -* property owned by Trident and are copyright of Trident, unless specifically -* noted otherwise. -* -* Any use of the Software is permitted only pursuant to the terms of the -* license agreement, if any, which accompanies, is included with or applicable -* to the Software ('License Agreement') or upon express written consent of -* Trident. Any copying, reproduction or redistribution of the Software in -* whole or in part by any means not in accordance with the License Agreement -* or as agreed in writing by Trident is expressly prohibited. -* -* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE -* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE -* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND -* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES -* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT -* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL -* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY -* TO USE THE SOFTWARE. -* -* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, -* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, -* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS -* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE -* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM -* TRIDENT'S NEGLIGENCE. -* -* IN NO EVENT SHALL MICRONAS BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, -* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, -* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS -* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE -* INABILITY TO USE THE SOFTWARE, EVEN IF MICRONAS HAS BEEN ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM -* MICRONAS' NEGLIGENCE. -* -----------------------------------------------------------------------------*/ +*/ #ifndef __DRXJ_MC_MAIN_H__ #define __DRXJ_MC_MAIN_H__ diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsb.h b/drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsb.h index a117ec1..9c24d3e 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsb.h +++ b/drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsb.h @@ -1,3 +1,33 @@ +/* + Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + * Neither the name of Trident Microsystems nor Hauppauge Computer Works + nor the names of its contributors may be used to endorse or promote + products derived from this software without specific prior written + permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. +*/ + /*----------------------------------------------------------------------------- * DESCRIPTION: * Contains firmware version: 1.0.8 @@ -6,44 +36,6 @@ * Include. * * NOTES: -* (c) 2009 Trident Microsystems, Inc. - All rights reserved. -* -* This software and related documentation (the 'Software') are intellectual -* property owned by Trident and are copyright of Trident, unless specifically -* noted otherwise. -* -* Any use of the Software is permitted only pursuant to the terms of the -* license agreement, if any, which accompanies, is included with or applicable -* to the Software ('License Agreement') or upon express written consent of -* Trident. Any copying, reproduction or redistribution of the Software in -* whole or in part by any means not in accordance with the License Agreement -* or as agreed in writing by Trident is expressly prohibited. -* -* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE -* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE -* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND -* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES -* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT -* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL -* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY -* TO USE THE SOFTWARE. -* -* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, -* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, -* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS -* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE -* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM -* TRIDENT'S NEGLIGENCE. -* -* IN NO EVENT SHALL MICRONAS BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, -* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, -* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS -* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE -* INABILITY TO USE THE SOFTWARE, EVEN IF MICRONAS HAS BEEN ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM -* MICRONAS' NEGLIGENCE. -* ----------------------------------------------------------------------------*/ #ifndef __DRXJ_MC_VSB_H__ diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsbqam.h b/drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsbqam.h index 4ef0a07..2eda7b8 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsbqam.h +++ b/drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsbqam.h @@ -1,3 +1,33 @@ +/* + Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + * Neither the name of Trident Microsystems nor Hauppauge Computer Works + nor the names of its contributors may be used to endorse or promote + products derived from this software without specific prior written + permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. +*/ + /*----------------------------------------------------------------------------- * DESCRIPTION: * Contains firmware version: 1.0.8 @@ -6,43 +36,6 @@ * Include. * * NOTES: -* (c) 2009 Trident Microsystems, Inc. - All rights reserved. -* -* This software and related documentation (the 'Software') are intellectual -* property owned by Trident and are copyright of Trident, unless specifically -* noted otherwise. -* -* Any use of the Software is permitted only pursuant to the terms of the -* license agreement, if any, which accompanies, is included with or applicable -* to the Software ('License Agreement') or upon express written consent of -* Trident. Any copying, reproduction or redistribution of the Software in -* whole or in part by any means not in accordance with the License Agreement -* or as agreed in writing by Trident is expressly prohibited. -* -* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE -* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE -* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND -* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES -* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT -* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL -* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY -* TO USE THE SOFTWARE. -* -* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, -* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, -* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS -* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE -* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM -* TRIDENT'S NEGLIGENCE. -* -* IN NO EVENT SHALL MICRONAS BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, -* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, -* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS -* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE -* INABILITY TO USE THE SOFTWARE, EVEN IF MICRONAS HAS BEEN ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM -* MICRONAS' NEGLIGENCE. * ----------------------------------------------------------------------------*/ diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj_options.h b/drivers/media/dvb-frontends/drx39xyj/drxj_options.h index 9299551..64ed170 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj_options.h +++ b/drivers/media/dvb-frontends/drx39xyj/drxj_options.h @@ -1,3 +1,33 @@ +/* + Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + * Neither the name of Trident Microsystems nor Hauppauge Computer Works + nor the names of its contributors may be used to endorse or promote + products derived from this software without specific prior written + permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. +*/ + /** * \file $Id: drxj_options.h,v 1.5 2009/10/05 21:32:49 dingtao Exp $ * @@ -6,39 +36,6 @@ * \author Tao Ding */ -/* -* $(c) 2006-2007,2009 Trident Microsystems, Inc. - All rights reserved. -* -* This software and related documentation (the 'Software') are intellectual -* property owned by Trident and are copyright of Trident, unless specifically -* noted otherwise. -* -* Any use of the Software is permitted only pursuant to the terms of the -* license agreement, if any, which accompanies, is included with or applicable -* to the Software ('License Agreement') or upon express written consent of -* Trident. Any copying, reproduction or redistribution of the Software in -* whole or in part by any means not in accordance with the License Agreement -* or as agreed in writing by Trident is expressly prohibited. -* -* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE -* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE -* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND -* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES -* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT -* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL -* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY -* TO USE THE SOFTWARE. -* -* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, -* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, -* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS -* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE -* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM -* TRIDENT'S NEGLIGENCE. $ -* -*/ - /* Note: Please add preprocessor DRXJ_OPTIONS_H for drxj.c to include this file */ #ifndef __DRXJ_OPTIONS_H__ #define __DRXJ_OPTIONS_H__ -- cgit v1.1 From 443f18d0d52d513810311601a9235cb22c72a85b Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 20 Mar 2012 00:00:42 -0300 Subject: [media] drx-j: CodingStyle fixes Do the automatic CodingStyle fixes found at Lindent. No functional changes. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/bsp_host.h | 16 +- drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h | 46 +- drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h | 218 +- drivers/media/dvb-frontends/drx39xyj/bsp_types.h | 86 +- drivers/media/dvb-frontends/drx39xyj/drx39xxj.c | 168 +- drivers/media/dvb-frontends/drx39xyj/drx39xxj.h | 2 +- .../media/dvb-frontends/drx39xyj/drx39xxj_dummy.c | 53 +- .../media/dvb-frontends/drx39xyj/drx_dap_fasi.c | 710 +- .../media/dvb-frontends/drx39xyj/drx_dap_fasi.h | 25 +- drivers/media/dvb-frontends/drx39xyj/drx_driver.c | 2024 +- drivers/media/dvb-frontends/drx39xyj/drx_driver.h | 1832 +- .../dvb-frontends/drx39xyj/drx_driver_version.h | 11 +- drivers/media/dvb-frontends/drx39xyj/drxj.c | 24031 +++++++++---------- drivers/media/dvb-frontends/drx39xyj/drxj.h | 645 +- drivers/media/dvb-frontends/drx39xyj/drxj_map.h | 299 +- drivers/media/dvb-frontends/drx39xyj/drxj_mc.h | 11670 ++++++--- drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsb.h | 2085 +- .../media/dvb-frontends/drx39xyj/drxj_mc_vsbqam.h | 4161 ++-- .../media/dvb-frontends/drx39xyj/drxj_options.h | 2 +- 19 files changed, 26522 insertions(+), 21562 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/bsp_host.h b/drivers/media/dvb-frontends/drx39xyj/bsp_host.h index 95b5232..5a2dd5f 100644 --- a/drivers/media/dvb-frontends/drx39xyj/bsp_host.h +++ b/drivers/media/dvb-frontends/drx39xyj/bsp_host.h @@ -50,7 +50,6 @@ extern "C" { TYPEDEFS -------------------------------------------------------------------------*/ - /*------------------------------------------------------------------------- DEFINES -------------------------------------------------------------------------*/ @@ -58,17 +57,17 @@ DEFINES /*------------------------------------------------------------------------- Exported FUNCTIONS -------------------------------------------------------------------------*/ -DRXStatus_t DRXBSP_HST_Init( void ); + DRXStatus_t DRXBSP_HST_Init(void); -DRXStatus_t DRXBSP_HST_Term( void ); + DRXStatus_t DRXBSP_HST_Term(void); -void* DRXBSP_HST_Memcpy( void *to, void *from, u32_t n); + void *DRXBSP_HST_Memcpy(void *to, void *from, u32_t n); -int DRXBSP_HST_Memcmp( void *s1, void *s2, u32_t n); + int DRXBSP_HST_Memcmp(void *s1, void *s2, u32_t n); -u32_t DRXBSP_HST_Clock( void ); + u32_t DRXBSP_HST_Clock(void); -DRXStatus_t DRXBSP_HST_Sleep( u32_t n ); + DRXStatus_t DRXBSP_HST_Sleep(u32_t n); /*------------------------------------------------------------------------- THE END @@ -76,5 +75,4 @@ THE END #ifdef __cplusplus } #endif - -#endif /* __DRXBSP_HOST_H__ */ +#endif /* __DRXBSP_HOST_H__ */ diff --git a/drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h b/drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h index 25207c8..982fc6b 100644 --- a/drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h +++ b/drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h @@ -59,7 +59,7 @@ TYPEDEFS * \typedef I2Caddr_t * \brief I2C device address (7-bit or 10-bit) */ -typedef u16_t I2Caddr_t; + typedef u16_t I2Caddr_t; /** * \typedef I2CdevId_t @@ -71,7 +71,7 @@ typedef u16_t I2Caddr_t; * I2C bus. * */ -typedef u16_t I2CdevId_t; + typedef u16_t I2CdevId_t; /** * \struct _I2CDeviceAddr_t @@ -81,11 +81,14 @@ typedef u16_t I2CdevId_t; * The userData pointer can be used for application specific purposes. * */ -struct _I2CDeviceAddr_t { - I2Caddr_t i2cAddr; /**< The I2C address of the device. */ - I2CdevId_t i2cDevId; /**< The device identifier. */ - void *userData; /**< User data pointer */ -}; + struct _I2CDeviceAddr_t { + I2Caddr_t i2cAddr; + /**< The I2C address of the device. */ + I2CdevId_t i2cDevId; + /**< The device identifier. */ + void *userData; + /**< User data pointer */ + }; /** * \typedef I2CDeviceAddr_t @@ -94,13 +97,13 @@ struct _I2CDeviceAddr_t { * This structure contains the I2C address and the device ID. * */ -typedef struct _I2CDeviceAddr_t I2CDeviceAddr_t; + typedef struct _I2CDeviceAddr_t I2CDeviceAddr_t; /** * \typedef pI2CDeviceAddr_t * \brief Pointer to I2C device parameters. */ -typedef I2CDeviceAddr_t *pI2CDeviceAddr_t; + typedef I2CDeviceAddr_t *pI2CDeviceAddr_t; /*------------------------------------------------------------------------------ DEFINES @@ -133,7 +136,6 @@ STRUCTS Exported FUNCTIONS ------------------------------------------------------------------------------*/ - /** * \fn DRXBSP_I2C_Init() * \brief Initialize I2C communication module. @@ -141,8 +143,7 @@ Exported FUNCTIONS * \retval DRX_STS_OK Initialization successful. * \retval DRX_STS_ERROR Initialization failed. */ -DRXStatus_t DRXBSP_I2C_Init( void ); - + DRXStatus_t DRXBSP_I2C_Init(void); /** * \fn DRXBSP_I2C_Term() @@ -151,7 +152,7 @@ DRXStatus_t DRXBSP_I2C_Init( void ); * \retval DRX_STS_OK Termination successful. * \retval DRX_STS_ERROR Termination failed. */ -DRXStatus_t DRXBSP_I2C_Term( void ); + DRXStatus_t DRXBSP_I2C_Term(void); /** * \fn DRXStatus_t DRXBSP_I2C_WriteRead( pI2CDeviceAddr_t wDevAddr, @@ -183,13 +184,11 @@ DRXStatus_t DRXBSP_I2C_Term( void ); * The device ID can be useful if several devices share an I2C address. * It can be used to control a "switch" on the I2C bus to the correct device. */ -DRXStatus_t DRXBSP_I2C_WriteRead( pI2CDeviceAddr_t wDevAddr, - u16_t wCount, - pu8_t wData, - pI2CDeviceAddr_t rDevAddr, - u16_t rCount, - pu8_t rData); - + DRXStatus_t DRXBSP_I2C_WriteRead(pI2CDeviceAddr_t wDevAddr, + u16_t wCount, + pu8_t wData, + pI2CDeviceAddr_t rDevAddr, + u16_t rCount, pu8_t rData); /** * \fn DRXBSP_I2C_ErrorText() @@ -198,14 +197,13 @@ DRXStatus_t DRXBSP_I2C_WriteRead( pI2CDeviceAddr_t wDevAddr, * * \return char* Pointer to human readable error text. */ -char* DRXBSP_I2C_ErrorText( void ); + char *DRXBSP_I2C_ErrorText(void); /** * \var DRX_I2C_Error_g; * \brief I2C specific error codes, platform dependent. */ -extern int DRX_I2C_Error_g; - + extern int DRX_I2C_Error_g; /*------------------------------------------------------------------------------ THE END @@ -213,4 +211,4 @@ THE END #ifdef __cplusplus } #endif -#endif /* __BSPI2C_H__ */ +#endif /* __BSPI2C_H__ */ diff --git a/drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h b/drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h index 668f988..6a92a68 100644 --- a/drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h +++ b/drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h @@ -51,24 +51,23 @@ extern "C" { DEFINES ------------------------------------------------------------------------------*/ - - /* Sub-mode bits should be adjacent and incremental */ -#define TUNER_MODE_SUB0 0x0001 /* for sub-mode (e.g. RF-AGC setting) */ -#define TUNER_MODE_SUB1 0x0002 /* for sub-mode (e.g. RF-AGC setting) */ -#define TUNER_MODE_SUB2 0x0004 /* for sub-mode (e.g. RF-AGC setting) */ -#define TUNER_MODE_SUB3 0x0008 /* for sub-mode (e.g. RF-AGC setting) */ -#define TUNER_MODE_SUB4 0x0010 /* for sub-mode (e.g. RF-AGC setting) */ -#define TUNER_MODE_SUB5 0x0020 /* for sub-mode (e.g. RF-AGC setting) */ -#define TUNER_MODE_SUB6 0x0040 /* for sub-mode (e.g. RF-AGC setting) */ -#define TUNER_MODE_SUB7 0x0080 /* for sub-mode (e.g. RF-AGC setting) */ - -#define TUNER_MODE_DIGITAL 0x0100 /* for digital channel (e.g. DVB-T) */ -#define TUNER_MODE_ANALOG 0x0200 /* for analog channel (e.g. PAL) */ -#define TUNER_MODE_SWITCH 0x0400 /* during channel switch & scanning */ -#define TUNER_MODE_LOCK 0x0800 /* after tuner has locked */ -#define TUNER_MODE_6MHZ 0x1000 /* for 6MHz bandwidth channels */ -#define TUNER_MODE_7MHZ 0x2000 /* for 7MHz bandwidth channels */ -#define TUNER_MODE_8MHZ 0x4000 /* for 8MHz bandwidth channels */ + /* Sub-mode bits should be adjacent and incremental */ +#define TUNER_MODE_SUB0 0x0001 /* for sub-mode (e.g. RF-AGC setting) */ +#define TUNER_MODE_SUB1 0x0002 /* for sub-mode (e.g. RF-AGC setting) */ +#define TUNER_MODE_SUB2 0x0004 /* for sub-mode (e.g. RF-AGC setting) */ +#define TUNER_MODE_SUB3 0x0008 /* for sub-mode (e.g. RF-AGC setting) */ +#define TUNER_MODE_SUB4 0x0010 /* for sub-mode (e.g. RF-AGC setting) */ +#define TUNER_MODE_SUB5 0x0020 /* for sub-mode (e.g. RF-AGC setting) */ +#define TUNER_MODE_SUB6 0x0040 /* for sub-mode (e.g. RF-AGC setting) */ +#define TUNER_MODE_SUB7 0x0080 /* for sub-mode (e.g. RF-AGC setting) */ + +#define TUNER_MODE_DIGITAL 0x0100 /* for digital channel (e.g. DVB-T) */ +#define TUNER_MODE_ANALOG 0x0200 /* for analog channel (e.g. PAL) */ +#define TUNER_MODE_SWITCH 0x0400 /* during channel switch & scanning */ +#define TUNER_MODE_LOCK 0x0800 /* after tuner has locked */ +#define TUNER_MODE_6MHZ 0x1000 /* for 6MHz bandwidth channels */ +#define TUNER_MODE_7MHZ 0x2000 /* for 7MHz bandwidth channels */ +#define TUNER_MODE_8MHZ 0x4000 /* for 8MHz bandwidth channels */ #define TUNER_MODE_SUB_MAX 8 #define TUNER_MODE_SUBALL ( TUNER_MODE_SUB0 | TUNER_MODE_SUB1 | \ @@ -80,92 +79,90 @@ DEFINES TYPEDEFS ------------------------------------------------------------------------------*/ -typedef u32_t TUNERMode_t; -typedef pu32_t pTUNERMode_t; - -typedef char* TUNERSubMode_t; /* description of submode */ -typedef TUNERSubMode_t *pTUNERSubMode_t; - - -typedef enum { - - TUNER_LOCKED, - TUNER_NOT_LOCKED + typedef u32_t TUNERMode_t; + typedef pu32_t pTUNERMode_t; -} TUNERLockStatus_t, *pTUNERLockStatus_t; + typedef char *TUNERSubMode_t; /* description of submode */ + typedef TUNERSubMode_t *pTUNERSubMode_t; + typedef enum { -typedef struct { + TUNER_LOCKED, + TUNER_NOT_LOCKED + } TUNERLockStatus_t, *pTUNERLockStatus_t; - char *name; /* Tuner brand & type name */ - DRXFrequency_t minFreqRF; /* Lowest RF input frequency, in kHz */ - DRXFrequency_t maxFreqRF; /* Highest RF input frequency, in kHz */ + typedef struct { - u8_t subMode; /* Index to sub-mode in use */ - pTUNERSubMode_t subModeDescriptions; /* Pointer to description of sub-modes*/ - u8_t subModes; /* Number of available sub-modes */ + char *name; /* Tuner brand & type name */ + DRXFrequency_t minFreqRF; /* Lowest RF input frequency, in kHz */ + DRXFrequency_t maxFreqRF; /* Highest RF input frequency, in kHz */ - /* The following fields will be either 0, NULL or FALSE and do not need - initialisation */ - void *selfCheck; /* gives proof of initialization */ - Bool_t programmed; /* only valid if selfCheck is OK */ - DRXFrequency_t RFfrequency; /* only valid if programmed */ - DRXFrequency_t IFfrequency; /* only valid if programmed */ + u8_t subMode; /* Index to sub-mode in use */ + pTUNERSubMode_t subModeDescriptions; /* Pointer to description of sub-modes */ + u8_t subModes; /* Number of available sub-modes */ - void* myUserData; /* pointer to associated demod instance */ - u16_t myCapabilities; /* value for storing application flags */ + /* The following fields will be either 0, NULL or FALSE and do not need + initialisation */ + void *selfCheck; /* gives proof of initialization */ + Bool_t programmed; /* only valid if selfCheck is OK */ + DRXFrequency_t RFfrequency; /* only valid if programmed */ + DRXFrequency_t IFfrequency; /* only valid if programmed */ -} TUNERCommonAttr_t, *pTUNERCommonAttr_t; + void *myUserData; /* pointer to associated demod instance */ + u16_t myCapabilities; /* value for storing application flags */ + } TUNERCommonAttr_t, *pTUNERCommonAttr_t; /* * Generic functions for DRX devices. */ -typedef struct TUNERInstance_s *pTUNERInstance_t; - -typedef DRXStatus_t (*TUNEROpenFunc_t)( pTUNERInstance_t tuner ); -typedef DRXStatus_t (*TUNERCloseFunc_t)( pTUNERInstance_t tuner ); - -typedef DRXStatus_t (*TUNERSetFrequencyFunc_t)( pTUNERInstance_t tuner, - TUNERMode_t mode, - DRXFrequency_t frequency ); - -typedef DRXStatus_t (*TUNERGetFrequencyFunc_t)( pTUNERInstance_t tuner, - TUNERMode_t mode, - pDRXFrequency_t RFfrequency, - pDRXFrequency_t IFfrequency ); - -typedef DRXStatus_t (*TUNERLockStatusFunc_t)( pTUNERInstance_t tuner, - pTUNERLockStatus_t lockStat ); - -typedef DRXStatus_t (*TUNERi2cWriteReadFunc_t)( pTUNERInstance_t tuner, - pI2CDeviceAddr_t wDevAddr, - u16_t wCount, - pu8_t wData, - pI2CDeviceAddr_t rDevAddr, - u16_t rCount, - pu8_t rData ); - -typedef struct -{ - TUNEROpenFunc_t openFunc; - TUNERCloseFunc_t closeFunc; - TUNERSetFrequencyFunc_t setFrequencyFunc; - TUNERGetFrequencyFunc_t getFrequencyFunc; - TUNERLockStatusFunc_t lockStatusFunc; - TUNERi2cWriteReadFunc_t i2cWriteReadFunc; - -} TUNERFunc_t, *pTUNERFunc_t; - -typedef struct TUNERInstance_s { - - I2CDeviceAddr_t myI2CDevAddr; - pTUNERCommonAttr_t myCommonAttr; - void* myExtAttr; - pTUNERFunc_t myFunct; - -} TUNERInstance_t; - + typedef struct TUNERInstance_s *pTUNERInstance_t; + + typedef DRXStatus_t(*TUNEROpenFunc_t) (pTUNERInstance_t tuner); + typedef DRXStatus_t(*TUNERCloseFunc_t) (pTUNERInstance_t tuner); + + typedef DRXStatus_t(*TUNERSetFrequencyFunc_t) (pTUNERInstance_t tuner, + TUNERMode_t mode, + DRXFrequency_t + frequency); + + typedef DRXStatus_t(*TUNERGetFrequencyFunc_t) (pTUNERInstance_t tuner, + TUNERMode_t mode, + pDRXFrequency_t + RFfrequency, + pDRXFrequency_t + IFfrequency); + + typedef DRXStatus_t(*TUNERLockStatusFunc_t) (pTUNERInstance_t tuner, + pTUNERLockStatus_t + lockStat); + + typedef DRXStatus_t(*TUNERi2cWriteReadFunc_t) (pTUNERInstance_t tuner, + pI2CDeviceAddr_t + wDevAddr, u16_t wCount, + pu8_t wData, + pI2CDeviceAddr_t + rDevAddr, u16_t rCount, + pu8_t rData); + + typedef struct { + TUNEROpenFunc_t openFunc; + TUNERCloseFunc_t closeFunc; + TUNERSetFrequencyFunc_t setFrequencyFunc; + TUNERGetFrequencyFunc_t getFrequencyFunc; + TUNERLockStatusFunc_t lockStatusFunc; + TUNERi2cWriteReadFunc_t i2cWriteReadFunc; + + } TUNERFunc_t, *pTUNERFunc_t; + + typedef struct TUNERInstance_s { + + I2CDeviceAddr_t myI2CDevAddr; + pTUNERCommonAttr_t myCommonAttr; + void *myExtAttr; + pTUNERFunc_t myFunct; + + } TUNERInstance_t; /*------------------------------------------------------------------------------ ENUM @@ -175,34 +172,32 @@ ENUM STRUCTS ------------------------------------------------------------------------------*/ - /*------------------------------------------------------------------------------ Exported FUNCTIONS ------------------------------------------------------------------------------*/ -DRXStatus_t DRXBSP_TUNER_Open( pTUNERInstance_t tuner ); + DRXStatus_t DRXBSP_TUNER_Open(pTUNERInstance_t tuner); -DRXStatus_t DRXBSP_TUNER_Close( pTUNERInstance_t tuner ); + DRXStatus_t DRXBSP_TUNER_Close(pTUNERInstance_t tuner); -DRXStatus_t DRXBSP_TUNER_SetFrequency( pTUNERInstance_t tuner, - TUNERMode_t mode, - DRXFrequency_t frequency ); + DRXStatus_t DRXBSP_TUNER_SetFrequency(pTUNERInstance_t tuner, + TUNERMode_t mode, + DRXFrequency_t frequency); -DRXStatus_t DRXBSP_TUNER_GetFrequency( pTUNERInstance_t tuner, - TUNERMode_t mode, - pDRXFrequency_t RFfrequency, - pDRXFrequency_t IFfrequency ); + DRXStatus_t DRXBSP_TUNER_GetFrequency(pTUNERInstance_t tuner, + TUNERMode_t mode, + pDRXFrequency_t RFfrequency, + pDRXFrequency_t IFfrequency); -DRXStatus_t DRXBSP_TUNER_LockStatus( pTUNERInstance_t tuner, - pTUNERLockStatus_t lockStat ); + DRXStatus_t DRXBSP_TUNER_LockStatus(pTUNERInstance_t tuner, + pTUNERLockStatus_t lockStat); -DRXStatus_t DRXBSP_TUNER_DefaultI2CWriteRead( pTUNERInstance_t tuner, - pI2CDeviceAddr_t wDevAddr, - u16_t wCount, - pu8_t wData, - pI2CDeviceAddr_t rDevAddr, - u16_t rCount, - pu8_t rData); + DRXStatus_t DRXBSP_TUNER_DefaultI2CWriteRead(pTUNERInstance_t tuner, + pI2CDeviceAddr_t wDevAddr, + u16_t wCount, + pu8_t wData, + pI2CDeviceAddr_t rDevAddr, + u16_t rCount, pu8_t rData); /*------------------------------------------------------------------------------ THE END @@ -210,6 +205,5 @@ THE END #ifdef __cplusplus } #endif -#endif /* __DRXBSP_TUNER_H__ */ - +#endif /* __DRXBSP_TUNER_H__ */ /* End of file */ diff --git a/drivers/media/dvb-frontends/drx39xyj/bsp_types.h b/drivers/media/dvb-frontends/drx39xyj/bsp_types.h index 15a483d..e10a79b 100644 --- a/drivers/media/dvb-frontends/drx39xyj/bsp_types.h +++ b/drivers/media/dvb-frontends/drx39xyj/bsp_types.h @@ -56,114 +56,113 @@ TYPEDEFS * \typedef unsigned char u8_t * \brief type definition of an unsigned 8 bits integer */ -typedef unsigned char u8_t; + typedef unsigned char u8_t; /** * \typedef char s8_t * \brief type definition of a signed 8 bits integer */ -typedef char s8_t; + typedef char s8_t; /** * \typedef unsigned short u16_t *pu16_t * \brief type definition of an unsigned 16 bits integer */ -typedef unsigned short u16_t; + typedef unsigned short u16_t; /** * \typedef short s16_t * \brief type definition of a signed 16 bits integer */ -typedef short s16_t; + typedef short s16_t; /** * \typedef unsigned long u32_t * \brief type definition of an unsigned 32 bits integer */ -typedef unsigned long u32_t; + typedef unsigned long u32_t; /** * \typedef long s32_t * \brief type definition of a signed 32 bits integer */ -typedef long s32_t; + typedef long s32_t; /* * \typedef struct ... u64_t * \brief type definition of an usigned 64 bits integer */ -typedef struct { - u32_t MSLW; - u32_t LSLW; -} u64_t; + typedef struct { + u32_t MSLW; + u32_t LSLW; + } u64_t; /* * \typedef struct ... i64_t * \brief type definition of a signed 64 bits integer */ -typedef struct { - s32_t MSLW; - u32_t LSLW; -} s64_t; + typedef struct { + s32_t MSLW; + u32_t LSLW; + } s64_t; /** * \typedef u8_t *pu8_t * \brief type definition of pointer to an unsigned 8 bits integer */ -typedef u8_t *pu8_t; + typedef u8_t *pu8_t; /** * \typedef s8_t *ps8_t * \brief type definition of pointer to a signed 8 bits integer */ -typedef s8_t *ps8_t; + typedef s8_t *ps8_t; /** * \typedef u16_t *pu16_t * \brief type definition of pointer to an unsigned 16 bits integer */ -typedef u16_t *pu16_t; + typedef u16_t *pu16_t; /** * \typedef s16_t *ps16_t * \brief type definition of pointer to a signed 16 bits integer */ -typedef s16_t *ps16_t; + typedef s16_t *ps16_t; /** * \typedef u32_t *pu32_t * \brief type definition of pointer to an unsigned 32 bits integer */ -typedef u32_t *pu32_t; + typedef u32_t *pu32_t; /** * \typedef s32_t *ps32_t * \brief type definition of pointer to a signed 32 bits integer */ -typedef s32_t *ps32_t; + typedef s32_t *ps32_t; /** * \typedef u64_t *pu64_t * \brief type definition of pointer to an usigned 64 bits integer */ -typedef u64_t *pu64_t; + typedef u64_t *pu64_t; /** * \typedef s64_t *ps64_t * \brief type definition of pointer to a signed 64 bits integer */ -typedef s64_t *ps64_t; - + typedef s64_t *ps64_t; /** * \typedef s32_t DRXFrequency_t * \brief type definition of frequency */ -typedef s32_t DRXFrequency_t; + typedef s32_t DRXFrequency_t; /** * \typedef DRXFrequency_t *pDRXFrequency_t * \brief type definition of a pointer to a frequency */ -typedef DRXFrequency_t *pDRXFrequency_t; + typedef DRXFrequency_t *pDRXFrequency_t; /** * \typedef u32_t DRXSymbolrate_t * \brief type definition of symbol rate */ -typedef u32_t DRXSymbolrate_t; + typedef u32_t DRXSymbolrate_t; /** * \typedef DRXSymbolrate_t *pDRXSymbolrate_t * \brief type definition of a pointer to a symbol rate */ -typedef DRXSymbolrate_t *pDRXSymbolrate_t; + typedef DRXSymbolrate_t *pDRXSymbolrate_t; /*------------------------------------------------------------------------- DEFINES @@ -184,32 +183,33 @@ ENUM * Boolean datatype. Only define if not already defined TRUE or FALSE. */ #if defined (TRUE) || defined (FALSE) -typedef int Bool_t; + typedef int Bool_t; #else /** * \enum Bool_t * \brief Boolean type */ -typedef enum { - FALSE = 0, - TRUE -} Bool_t; + typedef enum { + FALSE = 0, + TRUE + } Bool_t; #endif -typedef Bool_t *pBool_t; + typedef Bool_t *pBool_t; /** * \enum DRXStatus_t * \brief Various return statusses */ -typedef enum { - DRX_STS_READY = 3, /**< device/service is ready */ - DRX_STS_BUSY = 2, /**< device/service is busy */ - DRX_STS_OK = 1, /**< everything is OK */ - DRX_STS_INVALID_ARG = -1, /**< invalid arguments */ - DRX_STS_ERROR = -2, /**< general error */ - DRX_STS_FUNC_NOT_AVAILABLE = -3 /**< unavailable functionality */ -} DRXStatus_t, *pDRXStatus_t; - + typedef enum { + DRX_STS_READY = 3, /**< device/service is ready */ + DRX_STS_BUSY = 2, /**< device/service is busy */ + DRX_STS_OK = 1, /**< everything is OK */ + DRX_STS_INVALID_ARG = -1, + /**< invalid arguments */ + DRX_STS_ERROR = -2, /**< general error */ + DRX_STS_FUNC_NOT_AVAILABLE = -3 + /**< unavailable functionality */ + } DRXStatus_t, *pDRXStatus_t; /*------------------------------------------------------------------------- STRUCTS @@ -225,4 +225,4 @@ THE END #ifdef __cplusplus } #endif -#endif /* __BSP_TYPES_H__ */ +#endif /* __BSP_TYPES_H__ */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c index 36db20a8e..6c8c845 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c @@ -32,7 +32,7 @@ #include "drxj_mc.h" #include "drxj.h" -static int drx39xxj_set_powerstate(struct dvb_frontend* fe, int enable) +static int drx39xxj_set_powerstate(struct dvb_frontend *fe, int enable) { struct drx39xxj_state *state = fe->demodulator_priv; DRXDemodInstance_t *demod = state->demod; @@ -54,10 +54,10 @@ static int drx39xxj_set_powerstate(struct dvb_frontend* fe, int enable) return 0; } -static int drx39xxj_read_status(struct dvb_frontend* fe, fe_status_t* status) +static int drx39xxj_read_status(struct dvb_frontend *fe, fe_status_t * status) { - struct drx39xxj_state* state = fe->demodulator_priv; - DRXDemodInstance_t *demod = state->demod; + struct drx39xxj_state *state = fe->demodulator_priv; + DRXDemodInstance_t *demod = state->demod; DRXStatus_t result; DRXLockStatus_t lock_status; @@ -87,16 +87,12 @@ static int drx39xxj_read_status(struct dvb_frontend* fe, fe_status_t* status) case DRX_LOCK_STATE_8: case DRX_LOCK_STATE_9: *status = FE_HAS_SIGNAL - | FE_HAS_CARRIER - | FE_HAS_VITERBI - | FE_HAS_SYNC; + | FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC; break; case DRX_LOCKED: *status = FE_HAS_SIGNAL - | FE_HAS_CARRIER - | FE_HAS_VITERBI - | FE_HAS_SYNC - | FE_HAS_LOCK; + | FE_HAS_CARRIER + | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK; break; default: printk("Lock state unknown %d\n", lock_status); @@ -105,10 +101,10 @@ static int drx39xxj_read_status(struct dvb_frontend* fe, fe_status_t* status) return 0; } -static int drx39xxj_read_ber(struct dvb_frontend* fe, u32* ber) +static int drx39xxj_read_ber(struct dvb_frontend *fe, u32 * ber) { - struct drx39xxj_state* state = fe->demodulator_priv; - DRXDemodInstance_t *demod = state->demod; + struct drx39xxj_state *state = fe->demodulator_priv; + DRXDemodInstance_t *demod = state->demod; DRXStatus_t result; DRXSigQuality_t sig_quality; @@ -123,10 +119,11 @@ static int drx39xxj_read_ber(struct dvb_frontend* fe, u32* ber) return 0; } -static int drx39xxj_read_signal_strength(struct dvb_frontend* fe, u16* strength) +static int drx39xxj_read_signal_strength(struct dvb_frontend *fe, + u16 * strength) { - struct drx39xxj_state* state = fe->demodulator_priv; - DRXDemodInstance_t *demod = state->demod; + struct drx39xxj_state *state = fe->demodulator_priv; + DRXDemodInstance_t *demod = state->demod; DRXStatus_t result; DRXSigQuality_t sig_quality; @@ -142,10 +139,10 @@ static int drx39xxj_read_signal_strength(struct dvb_frontend* fe, u16* strength) return 0; } -static int drx39xxj_read_snr(struct dvb_frontend* fe, u16* snr) +static int drx39xxj_read_snr(struct dvb_frontend *fe, u16 * snr) { - struct drx39xxj_state* state = fe->demodulator_priv; - DRXDemodInstance_t *demod = state->demod; + struct drx39xxj_state *state = fe->demodulator_priv; + DRXDemodInstance_t *demod = state->demod; DRXStatus_t result; DRXSigQuality_t sig_quality; @@ -160,10 +157,10 @@ static int drx39xxj_read_snr(struct dvb_frontend* fe, u16* snr) return 0; } -static int drx39xxj_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks) +static int drx39xxj_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks) { - struct drx39xxj_state* state = fe->demodulator_priv; - DRXDemodInstance_t *demod = state->demod; + struct drx39xxj_state *state = fe->demodulator_priv; + DRXDemodInstance_t *demod = state->demod; DRXStatus_t result; DRXSigQuality_t sig_quality; @@ -178,38 +175,40 @@ static int drx39xxj_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks) return 0; } -static int drx39xxj_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p) +static int drx39xxj_get_frontend(struct dvb_frontend *fe, + struct dvb_frontend_parameters *p) { return 0; } -static int drx39xxj_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p) +static int drx39xxj_set_frontend(struct dvb_frontend *fe, + struct dvb_frontend_parameters *p) { #ifdef DJH_DEBUG int i; #endif - struct drx39xxj_state* state = fe->demodulator_priv; - DRXDemodInstance_t *demod = state->demod; + struct drx39xxj_state *state = fe->demodulator_priv; + DRXDemodInstance_t *demod = state->demod; DRXStandard_t standard = DRX_STANDARD_8VSB; DRXChannel_t channel; DRXStatus_t result; DRXUIOData_t uioData; - DRXChannel_t defChannel = {/* frequency */ 0, - /* bandwidth */ DRX_BANDWIDTH_6MHZ, - /* mirror */ DRX_MIRROR_NO, - /* constellation */ DRX_CONSTELLATION_AUTO, - /* hierarchy */ DRX_HIERARCHY_UNKNOWN, - /* priority */ DRX_PRIORITY_UNKNOWN, - /* coderate */ DRX_CODERATE_UNKNOWN, - /* guard */ DRX_GUARD_UNKNOWN, - /* fftmode */ DRX_FFTMODE_UNKNOWN, - /* classification */ DRX_CLASSIFICATION_AUTO, - /* symbolrate */ 5057000, - /* interleavemode */ DRX_INTERLEAVEMODE_UNKNOWN, - /* ldpc */ DRX_LDPC_UNKNOWN, - /* carrier */ DRX_CARRIER_UNKNOWN, - /* frame mode */ DRX_FRAMEMODE_UNKNOWN - }; + DRXChannel_t defChannel = { /* frequency */ 0, + /* bandwidth */ DRX_BANDWIDTH_6MHZ, + /* mirror */ DRX_MIRROR_NO, + /* constellation */ DRX_CONSTELLATION_AUTO, + /* hierarchy */ DRX_HIERARCHY_UNKNOWN, + /* priority */ DRX_PRIORITY_UNKNOWN, + /* coderate */ DRX_CODERATE_UNKNOWN, + /* guard */ DRX_GUARD_UNKNOWN, + /* fftmode */ DRX_FFTMODE_UNKNOWN, + /* classification */ DRX_CLASSIFICATION_AUTO, + /* symbolrate */ 5057000, + /* interleavemode */ DRX_INTERLEAVEMODE_UNKNOWN, + /* ldpc */ DRX_LDPC_UNKNOWN, + /* carrier */ DRX_CARRIER_UNKNOWN, + /* frame mode */ DRX_FRAMEMODE_UNKNOWN + }; /* Bring the demod out of sleep */ drx39xxj_set_powerstate(fe, 1); @@ -236,9 +235,9 @@ static int drx39xxj_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_pa /* set channel parameters */ channel = defChannel; - channel.frequency = p->frequency / 1000; - channel.bandwidth = DRX_BANDWIDTH_6MHZ; - channel.constellation = DRX_CONSTELLATION_AUTO; + channel.frequency = p->frequency / 1000; + channel.bandwidth = DRX_BANDWIDTH_6MHZ; + channel.constellation = DRX_CONSTELLATION_AUTO; /* program channel */ result = DRX_Ctrl(demod, DRX_CTRL_SET_CHANNEL, &channel); @@ -246,31 +245,28 @@ static int drx39xxj_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_pa printk("Failed to set channel!\n"); return -EINVAL; } - // Just for giggles, let's shut off the LNA again.... - uioData.uio = DRX_UIO1; + uioData.uio = DRX_UIO1; uioData.value = FALSE; result = DRX_Ctrl(demod, DRX_CTRL_UIO_WRITE, &uioData); if (result != DRX_STS_OK) { printk("Failed to disable LNA!\n"); return 0; } - #ifdef DJH_DEBUG - for(i = 0; i < 2000; i++) { - fe_status_t status; - drx39xxj_read_status(fe, &status); - printk("i=%d status=%d\n", i, status); - msleep(100); - i += 100; + for (i = 0; i < 2000; i++) { + fe_status_t status; + drx39xxj_read_status(fe, &status); + printk("i=%d status=%d\n", i, status); + msleep(100); + i += 100; } #endif return 0; } - -static int drx39xxj_sleep(struct dvb_frontend* fe) +static int drx39xxj_sleep(struct dvb_frontend *fe) { /* power-down the demodulator */ return drx39xxj_set_powerstate(fe, 0); @@ -308,8 +304,7 @@ static int drx39xxj_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) return 0; } - -static int drx39xxj_init(struct dvb_frontend* fe) +static int drx39xxj_init(struct dvb_frontend *fe) { /* Bring the demod out of sleep */ drx39xxj_set_powerstate(fe, 1); @@ -318,15 +313,15 @@ static int drx39xxj_init(struct dvb_frontend* fe) } static int drx39xxj_get_tune_settings(struct dvb_frontend *fe, - struct dvb_frontend_tune_settings *tune) + struct dvb_frontend_tune_settings *tune) { tune->min_delay_ms = 1000; return 0; } -static void drx39xxj_release(struct dvb_frontend* fe) +static void drx39xxj_release(struct dvb_frontend *fe) { - struct drx39xxj_state* state = fe->demodulator_priv; + struct drx39xxj_state *state = fe->demodulator_priv; kfree(state); } @@ -334,31 +329,36 @@ static struct dvb_frontend_ops drx39xxj_ops; struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) { - struct drx39xxj_state* state = NULL; + struct drx39xxj_state *state = NULL; - I2CDeviceAddr_t *demodAddr = NULL; - DRXCommonAttr_t *demodCommAttr = NULL; - DRXJData_t *demodExtAttr = NULL; - DRXDemodInstance_t *demod = NULL; + I2CDeviceAddr_t *demodAddr = NULL; + DRXCommonAttr_t *demodCommAttr = NULL; + DRXJData_t *demodExtAttr = NULL; + DRXDemodInstance_t *demod = NULL; DRXUIOCfg_t uioCfg; DRXUIOData_t uioData; DRXStatus_t result; /* allocate memory for the internal state */ state = kmalloc(sizeof(struct drx39xxj_state), GFP_KERNEL); - if (state == NULL) goto error; + if (state == NULL) + goto error; demod = kmalloc(sizeof(DRXDemodInstance_t), GFP_KERNEL); - if (demod == NULL) goto error; + if (demod == NULL) + goto error; demodAddr = kmalloc(sizeof(I2CDeviceAddr_t), GFP_KERNEL); - if (demodAddr == NULL) goto error; + if (demodAddr == NULL) + goto error; demodCommAttr = kmalloc(sizeof(DRXCommonAttr_t), GFP_KERNEL); - if (demodCommAttr == NULL) goto error; + if (demodCommAttr == NULL) + goto error; demodExtAttr = kmalloc(sizeof(DRXJData_t), GFP_KERNEL); - if (demodExtAttr == NULL) goto error; + if (demodExtAttr == NULL) + goto error; /* setup the state */ state->i2c = i2c; @@ -374,13 +374,14 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) memcpy(demod->myCommonAttr, &DRXJDefaultCommAttr_g, sizeof(DRXCommonAttr_t)); demod->myCommonAttr->microcode = DRXJ_MC_MAIN; - // demod->myCommonAttr->verifyMicrocode = FALSE; + // demod->myCommonAttr->verifyMicrocode = FALSE; demod->myCommonAttr->verifyMicrocode = TRUE; demod->myCommonAttr->intermediateFreq = 5000; demod->myExtAttr = demodExtAttr; memcpy(demod->myExtAttr, &DRXJData_g, sizeof(DRXJData_t)); - ((DRXJData_t *) demod->myExtAttr)->uioSmaTxMode = DRX_UIO_MODE_READWRITE; + ((DRXJData_t *) demod->myExtAttr)->uioSmaTxMode = + DRX_UIO_MODE_READWRITE; demod->myTuner = NULL; @@ -392,8 +393,8 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) } /* Turn off the LNA */ - uioCfg.uio = DRX_UIO1; - uioCfg.mode = DRX_UIO_MODE_READWRITE; + uioCfg.uio = DRX_UIO1; + uioCfg.mode = DRX_UIO_MODE_READWRITE; /* Configure user-I/O #3: enable read/write */ result = DRX_Ctrl(demod, DRX_CTRL_UIO_CFG, &uioCfg); if (result != DRX_STS_OK) { @@ -401,7 +402,7 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) return NULL; } - uioData.uio = DRX_UIO1; + uioData.uio = DRX_UIO1; uioData.value = FALSE; result = DRX_Ctrl(demod, DRX_CTRL_UIO_WRITE, &uioData); if (result != DRX_STS_OK) { @@ -427,13 +428,12 @@ error: static struct dvb_frontend_ops drx39xxj_ops = { .info = { - .name = "Micronas DRX39xxj family Frontend", - .type = FE_ATSC | FE_QAM, - .frequency_stepsize = 62500, - .frequency_min = 51000000, - .frequency_max = 858000000, - .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB - }, + .name = "Micronas DRX39xxj family Frontend", + .type = FE_ATSC | FE_QAM, + .frequency_stepsize = 62500, + .frequency_min = 51000000, + .frequency_max = 858000000, + .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB}, .init = drx39xxj_init, .i2c_gate_ctrl = drx39xxj_i2c_gate_ctrl, diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h index c29cd43..467b390 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h @@ -35,6 +35,6 @@ struct drx39xxj_state { unsigned int i2c_gate_open:1; }; -extern struct dvb_frontend* drx39xxj_attach(struct i2c_adapter *i2c); +extern struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c); #endif // DVB_DUMMY_FE_H diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c b/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c index 2b9344f..37967b2 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c @@ -13,59 +13,58 @@ #include "drx39xxj.h" /* Dummy function to satisfy drxj.c */ -DRXStatus_t DRXBSP_TUNER_Open( pTUNERInstance_t tuner ) +DRXStatus_t DRXBSP_TUNER_Open(pTUNERInstance_t tuner) { return DRX_STS_OK; } -DRXStatus_t DRXBSP_TUNER_Close( pTUNERInstance_t tuner ) +DRXStatus_t DRXBSP_TUNER_Close(pTUNERInstance_t tuner) { return DRX_STS_OK; } -DRXStatus_t DRXBSP_TUNER_SetFrequency( pTUNERInstance_t tuner, - TUNERMode_t mode, - DRXFrequency_t centerFrequency ) +DRXStatus_t DRXBSP_TUNER_SetFrequency(pTUNERInstance_t tuner, + TUNERMode_t mode, + DRXFrequency_t centerFrequency) { return DRX_STS_OK; } DRXStatus_t -DRXBSP_TUNER_GetFrequency( pTUNERInstance_t tuner, - TUNERMode_t mode, - pDRXFrequency_t RFfrequency, - pDRXFrequency_t IFfrequency ) +DRXBSP_TUNER_GetFrequency(pTUNERInstance_t tuner, + TUNERMode_t mode, + pDRXFrequency_t RFfrequency, + pDRXFrequency_t IFfrequency) { return DRX_STS_OK; } -DRXStatus_t DRXBSP_HST_Sleep( u32_t n ) +DRXStatus_t DRXBSP_HST_Sleep(u32_t n) { msleep(n); return DRX_STS_OK; } -u32_t DRXBSP_HST_Clock( void ) +u32_t DRXBSP_HST_Clock(void) { return jiffies_to_msecs(jiffies); } -int DRXBSP_HST_Memcmp( void *s1, void *s2, u32_t n) +int DRXBSP_HST_Memcmp(void *s1, void *s2, u32_t n) { - return ( memcmp( s1, s2, (size_t) n) ); + return (memcmp(s1, s2, (size_t) n)); } -void* DRXBSP_HST_Memcpy( void *to, void *from, u32_t n) +void *DRXBSP_HST_Memcpy(void *to, void *from, u32_t n) { - return ( memcpy( to, from, (size_t) n) ); + return (memcpy(to, from, (size_t) n)); } -DRXStatus_t DRXBSP_I2C_WriteRead( pI2CDeviceAddr_t wDevAddr, - u16_t wCount, - pu8_t wData, - pI2CDeviceAddr_t rDevAddr, - u16_t rCount, - pu8_t rData ) +DRXStatus_t DRXBSP_I2C_WriteRead(pI2CDeviceAddr_t wDevAddr, + u16_t wCount, + pu8_t wData, + pI2CDeviceAddr_t rDevAddr, + u16_t rCount, pu8_t rData) { struct drx39xxj_state *state; struct i2c_msg msg[2]; @@ -102,8 +101,8 @@ DRXStatus_t DRXBSP_I2C_WriteRead( pI2CDeviceAddr_t wDevAddr, } if (state->i2c == NULL) { - printk("i2c was zero, aborting\n"); - return 0; + printk("i2c was zero, aborting\n"); + return 0; } if (i2c_transfer(state->i2c, msg, num_msgs) != num_msgs) { printk(KERN_WARNING "drx3933: I2C write/read failed\n"); @@ -116,10 +115,10 @@ DRXStatus_t DRXBSP_I2C_WriteRead( pI2CDeviceAddr_t wDevAddr, struct drx39xxj_state *state = wDevAddr->userData; struct i2c_msg msg[2] = { - { .addr = wDevAddr->i2cAddr, - .flags = 0, .buf = wData, .len = wCount }, - { .addr = rDevAddr->i2cAddr, - .flags = I2C_M_RD, .buf = rData, .len = rCount }, + {.addr = wDevAddr->i2cAddr, + .flags = 0,.buf = wData,.len = wCount}, + {.addr = rDevAddr->i2cAddr, + .flags = I2C_M_RD,.buf = rData,.len = rCount}, }; printk("drx3933 i2c operation addr=%x i2c=%p, wc=%x rc=%x\n", diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c index 8289b90..a4d3ed3 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c @@ -50,154 +50,137 @@ *******************************************************************************/ #include "drx_dap_fasi.h" -#include "bsp_host.h" /* for DRXBSP_HST_Memcpy() */ +#include "bsp_host.h" /* for DRXBSP_HST_Memcpy() */ /*============================================================================*/ /* Function prototypes */ -static DRXStatus_t DRXDAP_FASI_WriteBlock ( - pI2CDeviceAddr_t devAddr, /* address of I2C device */ - DRXaddr_t addr, /* address of register/memory */ - u16_t datasize, /* size of data */ - pu8_t data, /* data to send */ - DRXflags_t flags); /* special device flags */ - -static DRXStatus_t DRXDAP_FASI_ReadBlock ( - pI2CDeviceAddr_t devAddr, /* address of I2C device */ - DRXaddr_t addr, /* address of register/memory */ - u16_t datasize, /* size of data */ - pu8_t data, /* data to send */ - DRXflags_t flags); /* special device flags */ - -static DRXStatus_t DRXDAP_FASI_WriteReg8 ( - pI2CDeviceAddr_t devAddr, /* address of I2C device */ - DRXaddr_t addr, /* address of register */ - u8_t data, /* data to write */ - DRXflags_t flags); /* special device flags */ - -static DRXStatus_t DRXDAP_FASI_ReadReg8 ( - pI2CDeviceAddr_t devAddr, /* address of I2C device */ - DRXaddr_t addr, /* address of register */ - pu8_t data, /* buffer to receive data */ - DRXflags_t flags); /* special device flags */ - -static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg8 ( - pI2CDeviceAddr_t devAddr, /* address of I2C device */ - DRXaddr_t waddr, /* address of register */ - DRXaddr_t raddr, /* address to read back from */ - u8_t datain, /* data to send */ - pu8_t dataout); /* data to receive back */ - -static DRXStatus_t DRXDAP_FASI_WriteReg16 ( - pI2CDeviceAddr_t devAddr, /* address of I2C device */ - DRXaddr_t addr, /* address of register */ - u16_t data, /* data to write */ - DRXflags_t flags); /* special device flags */ - -static DRXStatus_t DRXDAP_FASI_ReadReg16 ( - pI2CDeviceAddr_t devAddr, /* address of I2C device */ - DRXaddr_t addr, /* address of register */ - pu16_t data, /* buffer to receive data */ - DRXflags_t flags); /* special device flags */ - -static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg16 ( - pI2CDeviceAddr_t devAddr, /* address of I2C device */ - DRXaddr_t waddr, /* address of register */ - DRXaddr_t raddr, /* address to read back from */ - u16_t datain, /* data to send */ - pu16_t dataout); /* data to receive back */ - -static DRXStatus_t DRXDAP_FASI_WriteReg32 ( - pI2CDeviceAddr_t devAddr, /* address of I2C device */ - DRXaddr_t addr, /* address of register */ - u32_t data, /* data to write */ - DRXflags_t flags); /* special device flags */ - -static DRXStatus_t DRXDAP_FASI_ReadReg32 ( - pI2CDeviceAddr_t devAddr, /* address of I2C device */ - DRXaddr_t addr, /* address of register */ - pu32_t data, /* buffer to receive data */ - DRXflags_t flags); /* special device flags */ - -static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg32 ( - pI2CDeviceAddr_t devAddr, /* address of I2C device */ - DRXaddr_t waddr, /* address of register */ - DRXaddr_t raddr, /* address to read back from */ - u32_t datain, /* data to send */ - pu32_t dataout); /* data to receive back */ +static DRXStatus_t DRXDAP_FASI_WriteBlock(pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register/memory */ + u16_t datasize, /* size of data */ + pu8_t data, /* data to send */ + DRXflags_t flags); /* special device flags */ + +static DRXStatus_t DRXDAP_FASI_ReadBlock(pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register/memory */ + u16_t datasize, /* size of data */ + pu8_t data, /* data to send */ + DRXflags_t flags); /* special device flags */ + +static DRXStatus_t DRXDAP_FASI_WriteReg8(pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register */ + u8_t data, /* data to write */ + DRXflags_t flags); /* special device flags */ + +static DRXStatus_t DRXDAP_FASI_ReadReg8(pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register */ + pu8_t data, /* buffer to receive data */ + DRXflags_t flags); /* special device flags */ + +static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg8(pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t waddr, /* address of register */ + DRXaddr_t raddr, /* address to read back from */ + u8_t datain, /* data to send */ + pu8_t dataout); /* data to receive back */ + +static DRXStatus_t DRXDAP_FASI_WriteReg16(pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register */ + u16_t data, /* data to write */ + DRXflags_t flags); /* special device flags */ + +static DRXStatus_t DRXDAP_FASI_ReadReg16(pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register */ + pu16_t data, /* buffer to receive data */ + DRXflags_t flags); /* special device flags */ + +static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg16(pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t waddr, /* address of register */ + DRXaddr_t raddr, /* address to read back from */ + u16_t datain, /* data to send */ + pu16_t dataout); /* data to receive back */ + +static DRXStatus_t DRXDAP_FASI_WriteReg32(pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register */ + u32_t data, /* data to write */ + DRXflags_t flags); /* special device flags */ + +static DRXStatus_t DRXDAP_FASI_ReadReg32(pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register */ + pu32_t data, /* buffer to receive data */ + DRXflags_t flags); /* special device flags */ + +static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg32(pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t waddr, /* address of register */ + DRXaddr_t raddr, /* address to read back from */ + u32_t datain, /* data to send */ + pu32_t dataout); /* data to receive back */ /* The version structure of this protocol implementation */ -char drxDapFASIModuleName[] = "FASI Data Access Protocol"; +char drxDapFASIModuleName[] = "FASI Data Access Protocol"; char drxDapFASIVersionText[] = ""; -DRXVersion_t drxDapFASIVersion = -{ - DRX_MODULE_DAP, /**< type identifier of the module */ - drxDapFASIModuleName, /**< name or description of module */ +DRXVersion_t drxDapFASIVersion = { + DRX_MODULE_DAP, /**< type identifier of the module */ + drxDapFASIModuleName, /**< name or description of module */ - 0, /**< major version number */ - 0, /**< minor version number */ - 0, /**< patch version number */ - drxDapFASIVersionText /**< version as text string */ + 0, /**< major version number */ + 0, /**< minor version number */ + 0, /**< patch version number */ + drxDapFASIVersionText /**< version as text string */ }; /* The structure containing the protocol interface */ -DRXAccessFunc_t drxDapFASIFunct_g = -{ - &drxDapFASIVersion, - DRXDAP_FASI_WriteBlock, /* Supported */ - DRXDAP_FASI_ReadBlock, /* Supported */ - DRXDAP_FASI_WriteReg8, /* Not supported */ - DRXDAP_FASI_ReadReg8, /* Not supported */ - DRXDAP_FASI_ReadModifyWriteReg8, /* Not supported */ - DRXDAP_FASI_WriteReg16, /* Supported */ - DRXDAP_FASI_ReadReg16, /* Supported */ - DRXDAP_FASI_ReadModifyWriteReg16, /* Supported */ - DRXDAP_FASI_WriteReg32, /* Supported */ - DRXDAP_FASI_ReadReg32, /* Supported */ - DRXDAP_FASI_ReadModifyWriteReg32 /* Not supported */ +DRXAccessFunc_t drxDapFASIFunct_g = { + &drxDapFASIVersion, + DRXDAP_FASI_WriteBlock, /* Supported */ + DRXDAP_FASI_ReadBlock, /* Supported */ + DRXDAP_FASI_WriteReg8, /* Not supported */ + DRXDAP_FASI_ReadReg8, /* Not supported */ + DRXDAP_FASI_ReadModifyWriteReg8, /* Not supported */ + DRXDAP_FASI_WriteReg16, /* Supported */ + DRXDAP_FASI_ReadReg16, /* Supported */ + DRXDAP_FASI_ReadModifyWriteReg16, /* Supported */ + DRXDAP_FASI_WriteReg32, /* Supported */ + DRXDAP_FASI_ReadReg32, /* Supported */ + DRXDAP_FASI_ReadModifyWriteReg32 /* Not supported */ }; /*============================================================================*/ /* Functions not supported by protocol*/ -static DRXStatus_t DRXDAP_FASI_WriteReg8 ( - pI2CDeviceAddr_t devAddr, /* address of I2C device */ - DRXaddr_t addr, /* address of register */ - u8_t data, /* data to write */ - DRXflags_t flags) /* special device flags */ -{ - return DRX_STS_ERROR; +static DRXStatus_t DRXDAP_FASI_WriteReg8(pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register */ + u8_t data, /* data to write */ + DRXflags_t flags) +{ /* special device flags */ + return DRX_STS_ERROR; } -static DRXStatus_t DRXDAP_FASI_ReadReg8 ( - pI2CDeviceAddr_t devAddr, /* address of I2C device */ - DRXaddr_t addr, /* address of register */ - pu8_t data, /* buffer to receive data */ - DRXflags_t flags) /* special device flags */ -{ - return DRX_STS_ERROR; +static DRXStatus_t DRXDAP_FASI_ReadReg8(pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register */ + pu8_t data, /* buffer to receive data */ + DRXflags_t flags) +{ /* special device flags */ + return DRX_STS_ERROR; } -static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg8 ( - pI2CDeviceAddr_t devAddr, /* address of I2C device */ - DRXaddr_t waddr, /* address of register */ - DRXaddr_t raddr, /* address to read back from */ - u8_t datain, /* data to send */ - pu8_t dataout) /* data to receive back */ -{ - return DRX_STS_ERROR; +static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg8(pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t waddr, /* address of register */ + DRXaddr_t raddr, /* address to read back from */ + u8_t datain, /* data to send */ + pu8_t dataout) +{ /* data to receive back */ + return DRX_STS_ERROR; } -static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg32 ( - pI2CDeviceAddr_t devAddr, /* address of I2C device */ - DRXaddr_t waddr, /* address of register */ - DRXaddr_t raddr, /* address to read back from */ - u32_t datain, /* data to send */ - pu32_t dataout) /* data to receive back */ -{ - return DRX_STS_ERROR; +static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg32(pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t waddr, /* address of register */ + DRXaddr_t raddr, /* address to read back from */ + u32_t datain, /* data to send */ + pu32_t dataout) +{ /* data to receive back */ + return DRX_STS_ERROR; } /*============================================================================*/ @@ -227,105 +210,96 @@ static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg32 ( * ******************************/ -static DRXStatus_t DRXDAP_FASI_ReadBlock ( pI2CDeviceAddr_t devAddr, - DRXaddr_t addr, - u16_t datasize, - pu8_t data, - DRXflags_t flags ) +static DRXStatus_t DRXDAP_FASI_ReadBlock(pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + u16_t datasize, + pu8_t data, DRXflags_t flags) { - u8_t buf[4]; - u16_t bufx; - DRXStatus_t rc; - u16_t overheadSize = 0; - - /* Check parameters ********************************************************/ - if ( devAddr == NULL ) - { - return DRX_STS_INVALID_ARG; - } - - overheadSize = (IS_I2C_10BIT (devAddr->i2cAddr) ? 2 : 1) + - (DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2 ); - - if ( ( DRXDAP_FASI_OFFSET_TOO_LARGE(addr) ) || - ( ( !(DRXDAPFASI_LONG_ADDR_ALLOWED) ) && - DRXDAP_FASI_LONG_FORMAT( addr ) ) || - (overheadSize > (DRXDAP_MAX_WCHUNKSIZE)) || - ((datasize!=0) && (data==NULL)) || - ((datasize & 1)==1 ) ) - { - return DRX_STS_INVALID_ARG; - } - - /* ReadModifyWrite & mode flag bits are not allowed */ - flags &= (~DRXDAP_FASI_RMW & ~DRXDAP_FASI_MODEFLAGS); + u8_t buf[4]; + u16_t bufx; + DRXStatus_t rc; + u16_t overheadSize = 0; + + /* Check parameters ******************************************************* */ + if (devAddr == NULL) { + return DRX_STS_INVALID_ARG; + } + + overheadSize = (IS_I2C_10BIT(devAddr->i2cAddr) ? 2 : 1) + + (DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2); + + if ((DRXDAP_FASI_OFFSET_TOO_LARGE(addr)) || + ((!(DRXDAPFASI_LONG_ADDR_ALLOWED)) && + DRXDAP_FASI_LONG_FORMAT(addr)) || + (overheadSize > (DRXDAP_MAX_WCHUNKSIZE)) || + ((datasize != 0) && (data == NULL)) || ((datasize & 1) == 1)) { + return DRX_STS_INVALID_ARG; + } + + /* ReadModifyWrite & mode flag bits are not allowed */ + flags &= (~DRXDAP_FASI_RMW & ~DRXDAP_FASI_MODEFLAGS); #if DRXDAP_SINGLE_MASTER - flags |= DRXDAP_FASI_SINGLE_MASTER; + flags |= DRXDAP_FASI_SINGLE_MASTER; #endif - /* Read block from I2C *****************************************************/ - do { - u16_t todo = ( datasize < DRXDAP_MAX_RCHUNKSIZE ? - datasize : DRXDAP_MAX_RCHUNKSIZE); + /* Read block from I2C **************************************************** */ + do { + u16_t todo = (datasize < DRXDAP_MAX_RCHUNKSIZE ? + datasize : DRXDAP_MAX_RCHUNKSIZE); - bufx = 0; + bufx = 0; - addr &= ~DRXDAP_FASI_FLAGS; - addr |= flags; + addr &= ~DRXDAP_FASI_FLAGS; + addr |= flags; #if ( ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 ) && \ ( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 ) ) - /* short format address preferred but long format otherwise */ - if ( DRXDAP_FASI_LONG_FORMAT(addr) ) - { + /* short format address preferred but long format otherwise */ + if (DRXDAP_FASI_LONG_FORMAT(addr)) { #endif #if ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 ) - buf[bufx++] = (u8_t) (((addr << 1) & 0xFF)|0x01); - buf[bufx++] = (u8_t) ((addr >> 16) & 0xFF); - buf[bufx++] = (u8_t) ((addr >> 24) & 0xFF); - buf[bufx++] = (u8_t) ((addr >> 7) & 0xFF); + buf[bufx++] = (u8_t) (((addr << 1) & 0xFF) | 0x01); + buf[bufx++] = (u8_t) ((addr >> 16) & 0xFF); + buf[bufx++] = (u8_t) ((addr >> 24) & 0xFF); + buf[bufx++] = (u8_t) ((addr >> 7) & 0xFF); #endif #if ( ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 ) && \ ( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 ) ) - } else { + } else { #endif #if ( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 ) - buf[bufx++] = (u8_t) ((addr << 1) & 0xFF); - buf[bufx++] = (u8_t) ( ((addr >> 16) & 0x0F) | ((addr >> 18) & 0xF0) ); + buf[bufx++] = (u8_t) ((addr << 1) & 0xFF); + buf[bufx++] = + (u8_t) (((addr >> 16) & 0x0F) | + ((addr >> 18) & 0xF0)); #endif #if ( ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 ) && \ ( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 ) ) - } + } #endif - - - #if DRXDAP_SINGLE_MASTER - /* - * In single master mode, split the read and write actions. - * No special action is needed for write chunks here. - */ - rc = DRXBSP_I2C_WriteRead (devAddr, bufx, buf, 0, 0, 0); - if (rc == DRX_STS_OK) - { - rc = DRXBSP_I2C_WriteRead (0, 0, 0, devAddr, todo, data); - } + /* + * In single master mode, split the read and write actions. + * No special action is needed for write chunks here. + */ + rc = DRXBSP_I2C_WriteRead(devAddr, bufx, buf, 0, 0, 0); + if (rc == DRX_STS_OK) { + rc = DRXBSP_I2C_WriteRead(0, 0, 0, devAddr, todo, data); + } #else - /* In multi master mode, do everything in one RW action */ - rc = DRXBSP_I2C_WriteRead (devAddr, bufx, buf, devAddr, todo, data); + /* In multi master mode, do everything in one RW action */ + rc = DRXBSP_I2C_WriteRead(devAddr, bufx, buf, devAddr, todo, + data); #endif - data += todo; - addr += (todo >> 1); - datasize -= todo; - } while (datasize && rc == DRX_STS_OK); + data += todo; + addr += (todo >> 1); + datasize -= todo; + } while (datasize && rc == DRX_STS_OK); - return rc; + return rc; } - - - /****************************** * * DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg16 ( @@ -351,33 +325,27 @@ static DRXStatus_t DRXDAP_FASI_ReadBlock ( pI2CDeviceAddr_t devAddr, * ******************************/ -static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg16 ( pI2CDeviceAddr_t devAddr, - DRXaddr_t waddr, - DRXaddr_t raddr, - u16_t wdata, - pu16_t rdata ) +static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg16(pI2CDeviceAddr_t devAddr, + DRXaddr_t waddr, + DRXaddr_t raddr, + u16_t wdata, pu16_t rdata) { - DRXStatus_t rc=DRX_STS_ERROR; + DRXStatus_t rc = DRX_STS_ERROR; #if ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 ) - if (rdata == NULL) - { - return DRX_STS_INVALID_ARG; - } - - rc = DRXDAP_FASI_WriteReg16 (devAddr, waddr, wdata, DRXDAP_FASI_RMW); - if (rc == DRX_STS_OK) - { - rc = DRXDAP_FASI_ReadReg16 (devAddr, raddr, rdata, 0); - } + if (rdata == NULL) { + return DRX_STS_INVALID_ARG; + } + + rc = DRXDAP_FASI_WriteReg16(devAddr, waddr, wdata, DRXDAP_FASI_RMW); + if (rc == DRX_STS_OK) { + rc = DRXDAP_FASI_ReadReg16(devAddr, raddr, rdata, 0); + } #endif - return rc; + return rc; } - - - /****************************** * * DRXStatus_t DRXDAP_FASI_ReadReg16 ( @@ -396,26 +364,21 @@ static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg16 ( pI2CDeviceAddr_t devAddr, * ******************************/ -static DRXStatus_t DRXDAP_FASI_ReadReg16 ( pI2CDeviceAddr_t devAddr, - DRXaddr_t addr, - pu16_t data, - DRXflags_t flags ) +static DRXStatus_t DRXDAP_FASI_ReadReg16(pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + pu16_t data, DRXflags_t flags) { - u8_t buf[sizeof (*data)]; - DRXStatus_t rc; - - if (!data) - { - return DRX_STS_INVALID_ARG; - } - rc = DRXDAP_FASI_ReadBlock (devAddr, addr, sizeof (*data), buf, flags); - *data = buf[0] + (((u16_t) buf[1]) << 8); - return rc; + u8_t buf[sizeof(*data)]; + DRXStatus_t rc; + + if (!data) { + return DRX_STS_INVALID_ARG; + } + rc = DRXDAP_FASI_ReadBlock(devAddr, addr, sizeof(*data), buf, flags); + *data = buf[0] + (((u16_t) buf[1]) << 8); + return rc; } - - - /****************************** * * DRXStatus_t DRXDAP_FASI_ReadReg32 ( @@ -434,29 +397,23 @@ static DRXStatus_t DRXDAP_FASI_ReadReg16 ( pI2CDeviceAddr_t devAddr, * ******************************/ -static DRXStatus_t DRXDAP_FASI_ReadReg32 ( pI2CDeviceAddr_t devAddr, - DRXaddr_t addr, - pu32_t data, - DRXflags_t flags ) +static DRXStatus_t DRXDAP_FASI_ReadReg32(pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + pu32_t data, DRXflags_t flags) { - u8_t buf[sizeof (*data)]; - DRXStatus_t rc; - - if (!data) - { - return DRX_STS_INVALID_ARG; - } - rc = DRXDAP_FASI_ReadBlock (devAddr, addr, sizeof (*data), buf, flags); - *data = (((u32_t) buf[0]) << 0) + - (((u32_t) buf[1]) << 8) + - (((u32_t) buf[2]) << 16) + - (((u32_t) buf[3]) << 24); - return rc; + u8_t buf[sizeof(*data)]; + DRXStatus_t rc; + + if (!data) { + return DRX_STS_INVALID_ARG; + } + rc = DRXDAP_FASI_ReadBlock(devAddr, addr, sizeof(*data), buf, flags); + *data = (((u32_t) buf[0]) << 0) + + (((u32_t) buf[1]) << 8) + + (((u32_t) buf[2]) << 16) + (((u32_t) buf[3]) << 24); + return rc; } - - - /****************************** * * DRXStatus_t DRXDAP_FASI_WriteBlock ( @@ -479,136 +436,128 @@ static DRXStatus_t DRXDAP_FASI_ReadReg32 ( pI2CDeviceAddr_t devAddr, * ******************************/ -static DRXStatus_t DRXDAP_FASI_WriteBlock ( pI2CDeviceAddr_t devAddr, - DRXaddr_t addr, - u16_t datasize, - pu8_t data, - DRXflags_t flags ) +static DRXStatus_t DRXDAP_FASI_WriteBlock(pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + u16_t datasize, + pu8_t data, DRXflags_t flags) { - u8_t buf[ DRXDAP_MAX_WCHUNKSIZE ]; - DRXStatus_t st = DRX_STS_ERROR; - DRXStatus_t firstErr = DRX_STS_OK; - u16_t overheadSize = 0; - u16_t blockSize = 0; - - /* Check parameters ********************************************************/ - if ( devAddr == NULL ) - { - return DRX_STS_INVALID_ARG; - } - - overheadSize = (IS_I2C_10BIT (devAddr->i2cAddr) ? 2 : 1) + - (DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2 ); - - if ( ( DRXDAP_FASI_OFFSET_TOO_LARGE(addr) ) || - ( ( !(DRXDAPFASI_LONG_ADDR_ALLOWED) ) && - DRXDAP_FASI_LONG_FORMAT( addr ) ) || - (overheadSize > (DRXDAP_MAX_WCHUNKSIZE)) || - ((datasize!=0) && (data==NULL)) || - ((datasize & 1)==1 ) ) - { - return DRX_STS_INVALID_ARG; - } - - flags &= DRXDAP_FASI_FLAGS; - flags &= ~DRXDAP_FASI_MODEFLAGS; + u8_t buf[DRXDAP_MAX_WCHUNKSIZE]; + DRXStatus_t st = DRX_STS_ERROR; + DRXStatus_t firstErr = DRX_STS_OK; + u16_t overheadSize = 0; + u16_t blockSize = 0; + + /* Check parameters ******************************************************* */ + if (devAddr == NULL) { + return DRX_STS_INVALID_ARG; + } + + overheadSize = (IS_I2C_10BIT(devAddr->i2cAddr) ? 2 : 1) + + (DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2); + + if ((DRXDAP_FASI_OFFSET_TOO_LARGE(addr)) || + ((!(DRXDAPFASI_LONG_ADDR_ALLOWED)) && + DRXDAP_FASI_LONG_FORMAT(addr)) || + (overheadSize > (DRXDAP_MAX_WCHUNKSIZE)) || + ((datasize != 0) && (data == NULL)) || ((datasize & 1) == 1)) { + return DRX_STS_INVALID_ARG; + } + + flags &= DRXDAP_FASI_FLAGS; + flags &= ~DRXDAP_FASI_MODEFLAGS; #if DRXDAP_SINGLE_MASTER - flags |= DRXDAP_FASI_SINGLE_MASTER; + flags |= DRXDAP_FASI_SINGLE_MASTER; #endif - /* Write block to I2C ******************************************************/ - blockSize = ( (DRXDAP_MAX_WCHUNKSIZE) - overheadSize) & ~1; - do - { - u16_t todo = 0; - u16_t bufx = 0; + /* Write block to I2C ***************************************************** */ + blockSize = ((DRXDAP_MAX_WCHUNKSIZE) - overheadSize) & ~1; + do { + u16_t todo = 0; + u16_t bufx = 0; - /* Buffer device address */ - addr &= ~DRXDAP_FASI_FLAGS; - addr |= flags; + /* Buffer device address */ + addr &= ~DRXDAP_FASI_FLAGS; + addr |= flags; #if ( ( (DRXDAPFASI_LONG_ADDR_ALLOWED)==1 ) && \ ( (DRXDAPFASI_SHORT_ADDR_ALLOWED)==1 ) ) - /* short format address preferred but long format otherwise */ - if ( DRXDAP_FASI_LONG_FORMAT(addr) ) - { + /* short format address preferred but long format otherwise */ + if (DRXDAP_FASI_LONG_FORMAT(addr)) { #endif #if ( (DRXDAPFASI_LONG_ADDR_ALLOWED)==1 ) - buf[bufx++] = (u8_t) (((addr << 1) & 0xFF)|0x01); - buf[bufx++] = (u8_t) ((addr >> 16) & 0xFF); - buf[bufx++] = (u8_t) ((addr >> 24) & 0xFF); - buf[bufx++] = (u8_t) ((addr >> 7) & 0xFF); + buf[bufx++] = (u8_t) (((addr << 1) & 0xFF) | 0x01); + buf[bufx++] = (u8_t) ((addr >> 16) & 0xFF); + buf[bufx++] = (u8_t) ((addr >> 24) & 0xFF); + buf[bufx++] = (u8_t) ((addr >> 7) & 0xFF); #endif #if ( ( (DRXDAPFASI_LONG_ADDR_ALLOWED)==1 ) && \ ( (DRXDAPFASI_SHORT_ADDR_ALLOWED)==1 ) ) - } else { + } else { #endif #if ( (DRXDAPFASI_SHORT_ADDR_ALLOWED)==1 ) - buf[bufx++] = (u8_t) ((addr << 1) & 0xFF); - buf[bufx++] = (u8_t) ( ((addr >> 16) & 0x0F) | ((addr >> 18) & 0xF0) ); + buf[bufx++] = (u8_t) ((addr << 1) & 0xFF); + buf[bufx++] = + (u8_t) (((addr >> 16) & 0x0F) | + ((addr >> 18) & 0xF0)); #endif #if ( ( (DRXDAPFASI_LONG_ADDR_ALLOWED)==1 ) && \ ( (DRXDAPFASI_SHORT_ADDR_ALLOWED)==1 ) ) - } + } #endif - /* - In single master mode blockSize can be 0. In such a case this I2C - sequense will be visible: (1) write address {i2c addr, - 4 bytes chip address} (2) write data {i2c addr, 4 bytes data } - (3) write address (4) write data etc... - Addres must be rewriten because HI is reset after data transport and - expects an address. - */ - todo = (blockSize < datasize ? blockSize : datasize); - if (todo==0) - { - u16_t overheadSizeI2cAddr = 0; - u16_t dataBlockSize = 0; - - overheadSizeI2cAddr = (IS_I2C_10BIT (devAddr->i2cAddr) ? 2 : 1); - dataBlockSize = ( DRXDAP_MAX_WCHUNKSIZE - overheadSizeI2cAddr) & ~1; - - /* write device address */ - st = DRXBSP_I2C_WriteRead( devAddr, - (u16_t) (bufx), - buf, - (pI2CDeviceAddr_t)(NULL), - 0, - (pu8_t)(NULL) ); - - if ( ( st != DRX_STS_OK ) && ( firstErr == DRX_STS_OK ) ) - { - /* at the end, return the first error encountered */ - firstErr = st; - } - bufx = 0; - todo = (dataBlockSize < datasize ? dataBlockSize : datasize); - } - DRXBSP_HST_Memcpy (&buf[bufx], data, todo); - /* write (address if can do and) data */ - st = DRXBSP_I2C_WriteRead( devAddr, - (u16_t)(bufx + todo), - buf, - (pI2CDeviceAddr_t)(NULL), - 0, - (pu8_t)(NULL) ); - - if ( ( st != DRX_STS_OK ) && ( firstErr == DRX_STS_OK ) ) - { - /* at the end, return the first error encountered */ - firstErr = st; - } - datasize -= todo; - data += todo; - addr += (todo >> 1); - } while (datasize); - - return firstErr; + /* + In single master mode blockSize can be 0. In such a case this I2C + sequense will be visible: (1) write address {i2c addr, + 4 bytes chip address} (2) write data {i2c addr, 4 bytes data } + (3) write address (4) write data etc... + Addres must be rewriten because HI is reset after data transport and + expects an address. + */ + todo = (blockSize < datasize ? blockSize : datasize); + if (todo == 0) { + u16_t overheadSizeI2cAddr = 0; + u16_t dataBlockSize = 0; + + overheadSizeI2cAddr = + (IS_I2C_10BIT(devAddr->i2cAddr) ? 2 : 1); + dataBlockSize = + (DRXDAP_MAX_WCHUNKSIZE - overheadSizeI2cAddr) & ~1; + + /* write device address */ + st = DRXBSP_I2C_WriteRead(devAddr, + (u16_t) (bufx), + buf, + (pI2CDeviceAddr_t) (NULL), + 0, (pu8_t) (NULL)); + + if ((st != DRX_STS_OK) && (firstErr == DRX_STS_OK)) { + /* at the end, return the first error encountered */ + firstErr = st; + } + bufx = 0; + todo = + (dataBlockSize < + datasize ? dataBlockSize : datasize); + } + DRXBSP_HST_Memcpy(&buf[bufx], data, todo); + /* write (address if can do and) data */ + st = DRXBSP_I2C_WriteRead(devAddr, + (u16_t) (bufx + todo), + buf, + (pI2CDeviceAddr_t) (NULL), + 0, (pu8_t) (NULL)); + + if ((st != DRX_STS_OK) && (firstErr == DRX_STS_OK)) { + /* at the end, return the first error encountered */ + firstErr = st; + } + datasize -= todo; + data += todo; + addr += (todo >> 1); + } while (datasize); + + return firstErr; } - - - /****************************** * * DRXStatus_t DRXDAP_FASI_WriteReg16 ( @@ -626,22 +575,18 @@ static DRXStatus_t DRXDAP_FASI_WriteBlock ( pI2CDeviceAddr_t devAddr, * ******************************/ -static DRXStatus_t DRXDAP_FASI_WriteReg16 ( pI2CDeviceAddr_t devAddr, - DRXaddr_t addr, - u16_t data, - DRXflags_t flags ) +static DRXStatus_t DRXDAP_FASI_WriteReg16(pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + u16_t data, DRXflags_t flags) { - u8_t buf[sizeof (data)]; + u8_t buf[sizeof(data)]; - buf[0] = (u8_t) ( (data >> 0 ) & 0xFF ); - buf[1] = (u8_t) ( (data >> 8 ) & 0xFF ); + buf[0] = (u8_t) ((data >> 0) & 0xFF); + buf[1] = (u8_t) ((data >> 8) & 0xFF); - return DRXDAP_FASI_WriteBlock (devAddr, addr, sizeof (data), buf, flags); + return DRXDAP_FASI_WriteBlock(devAddr, addr, sizeof(data), buf, flags); } - - - /****************************** * * DRXStatus_t DRXDAP_FASI_WriteReg32 ( @@ -659,17 +604,16 @@ static DRXStatus_t DRXDAP_FASI_WriteReg16 ( pI2CDeviceAddr_t devAddr, * ******************************/ -static DRXStatus_t DRXDAP_FASI_WriteReg32 ( pI2CDeviceAddr_t devAddr, - DRXaddr_t addr, - u32_t data, - DRXflags_t flags ) +static DRXStatus_t DRXDAP_FASI_WriteReg32(pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + u32_t data, DRXflags_t flags) { - u8_t buf[sizeof (data)]; + u8_t buf[sizeof(data)]; - buf[0] = (u8_t) ( (data >> 0 ) & 0xFF ); - buf[1] = (u8_t) ( (data >> 8 ) & 0xFF ); - buf[2] = (u8_t) ( (data >> 16) & 0xFF ); - buf[3] = (u8_t) ( (data >> 24) & 0xFF ); + buf[0] = (u8_t) ((data >> 0) & 0xFF); + buf[1] = (u8_t) ((data >> 8) & 0xFF); + buf[2] = (u8_t) ((data >> 16) & 0xFF); + buf[3] = (u8_t) ((data >> 24) & 0xFF); - return DRXDAP_FASI_WriteBlock (devAddr, addr, sizeof (data), buf, flags); + return DRXDAP_FASI_WriteBlock(devAddr, addr, sizeof(data), buf, flags); } diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.h b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.h index 4429ef7..756f08d 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.h @@ -96,10 +96,9 @@ #if ( ( DRXDAPFASI_LONG_ADDR_ALLOWED==0 ) && \ ( DRXDAPFASI_SHORT_ADDR_ALLOWED==0 ) ) #error At least one of short- or long-addressing format must be allowed. -*; /* illegal statement to force compiler error */ +*; /* illegal statement to force compiler error */ #endif - /******************************************** * Single/master multi master setting ********************************************/ @@ -200,18 +199,18 @@ #if ( (DRXDAPFASI_LONG_ADDR_ALLOWED==0)&&(DRXDAPFASI_SHORT_ADDR_ALLOWED==1) ) #if DRXDAP_SINGLE_MASTER #error DRXDAP_MAX_WCHUNKSIZE must be at least 3 in single master mode -*; /* illegal statement to force compiler error */ +*; /* illegal statement to force compiler error */ #else #error DRXDAP_MAX_WCHUNKSIZE must be at least 5 in multi master mode -*; /* illegal statement to force compiler error */ +*; /* illegal statement to force compiler error */ #endif #else #if DRXDAP_SINGLE_MASTER #error DRXDAP_MAX_WCHUNKSIZE must be at least 5 in single master mode -*; /* illegal statement to force compiler error */ +*; /* illegal statement to force compiler error */ #else #error DRXDAP_MAX_WCHUNKSIZE must be at least 7 in multi master mode -*; /* illegal statement to force compiler error */ +*; /* illegal statement to force compiler error */ #endif #endif #endif @@ -224,13 +223,13 @@ /* check */ #if DRXDAP_MAX_RCHUNKSIZE < 2 #error DRXDAP_MAX_RCHUNKSIZE must be at least 2 -*; /* illegal statement to force compiler error */ +*; /* illegal statement to force compiler error */ #endif /* check */ #if DRXDAP_MAX_RCHUNKSIZE & 1 #error DRXDAP_MAX_RCHUNKSIZE must be even -*; /* illegal statement to force compiler error */ +*; /* illegal statement to force compiler error */ #endif /*-------- Public API functions ----------------------------------------------*/ @@ -239,15 +238,14 @@ extern "C" { #endif - -extern DRXAccessFunc_t drxDapFASIFunct_g; + extern DRXAccessFunc_t drxDapFASIFunct_g; #define DRXDAP_FASI_RMW 0x10000000 #define DRXDAP_FASI_BROADCAST 0x20000000 #define DRXDAP_FASI_CLEARCRC 0x80000000 #define DRXDAP_FASI_SINGLE_MASTER 0xC0000000 #define DRXDAP_FASI_MULTI_MASTER 0x40000000 -#define DRXDAP_FASI_SMM_SWITCH 0x40000000 /* single/multi master switch */ +#define DRXDAP_FASI_SMM_SWITCH 0x40000000 /* single/multi master switch */ #define DRXDAP_FASI_MODEFLAGS 0xC0000000 #define DRXDAP_FASI_FLAGS 0xF0000000 @@ -259,10 +257,7 @@ extern DRXAccessFunc_t drxDapFASIFunct_g; #define DRXDAP_FASI_LONG_FORMAT( addr ) (((addr)& 0xFC30FF80)!=0) #define DRXDAP_FASI_OFFSET_TOO_LARGE( addr ) (((addr)& 0x00008000)!=0) - #ifdef __cplusplus } #endif - - -#endif /* __DRX_DAP_FASI_H__ */ +#endif /* __DRX_DAP_FASI_H__ */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c index 84c7dd4..2d27110 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c @@ -119,14 +119,17 @@ STRUCTURES ------------------------------------------------------------------------------*/ /** \brief Structure of the microcode block headers */ typedef struct { - u32_t addr; /**< Destination address of the data in this block */ - u16_t size; /**< Size of the block data following this header counted in + u32_t addr; + /**< Destination address of the data in this block */ + u16_t size; + /**< Size of the block data following this header counted in 16 bits words */ - u16_t flags; /**< Flags for this data block: + u16_t flags; + /**< Flags for this data block: - bit[0]= CRC on/off - bit[1]= compression on/off - bit[15..2]=reserved */ - u16_t CRC; /**< CRC value of the data block, only valid if CRC flag is + u16_t CRC;/**< CRC value of the data block, only valid if CRC flag is set. */ } DRXUCodeBlockHdr_t, *pDRXUCodeBlockHdr_t; @@ -144,33 +147,30 @@ FUNCTIONS /* Prototype of default scanning function */ static DRXStatus_t -ScanFunctionDefault( void *scanContext, - DRXScanCommand_t scanCommand, - pDRXChannel_t scanChannel, - pBool_t getNextChannel ); +ScanFunctionDefault(void *scanContext, + DRXScanCommand_t scanCommand, + pDRXChannel_t scanChannel, pBool_t getNextChannel); /** * \brief Get pointer to scanning function. * \param demod: Pointer to demodulator instance. * \return DRXScanFunc_t. */ -static DRXScanFunc_t -GetScanFunction( pDRXDemodInstance_t demod ) +static DRXScanFunc_t GetScanFunction(pDRXDemodInstance_t demod) { - pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t)(NULL); - DRXScanFunc_t scanFunc = (DRXScanFunc_t)(NULL); - - /* get scan function from common attributes */ - commonAttr = (pDRXCommonAttr_t)demod->myCommonAttr; - scanFunc = commonAttr->scanFunction; - - if ( scanFunc != NULL ) - { - /* return device-specific scan function if it's not NULL */ - return scanFunc; - } - /* otherwise return default scan function in core driver */ - return &ScanFunctionDefault; + pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); + DRXScanFunc_t scanFunc = (DRXScanFunc_t) (NULL); + + /* get scan function from common attributes */ + commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; + scanFunc = commonAttr->scanFunction; + + if (scanFunc != NULL) { + /* return device-specific scan function if it's not NULL */ + return scanFunc; + } + /* otherwise return default scan function in core driver */ + return &ScanFunctionDefault; } /** @@ -179,21 +179,19 @@ GetScanFunction( pDRXDemodInstance_t demod ) * \param scanContext: Context Pointer. * \return DRXScanFunc_t. */ -void *GetScanContext( pDRXDemodInstance_t demod, - void *scanContext) +void *GetScanContext(pDRXDemodInstance_t demod, void *scanContext) { - pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t)(NULL); + pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); - /* get scan function from common attributes */ - commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; - scanContext = commonAttr->scanContext; + /* get scan function from common attributes */ + commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; + scanContext = commonAttr->scanContext; - if ( scanContext == NULL ) - { - scanContext = (void *) demod; - } + if (scanContext == NULL) { + scanContext = (void *)demod; + } - return scanContext; + return scanContext; } /** @@ -214,59 +212,50 @@ void *GetScanContext( pDRXDemodInstance_t demod, * In case DRX_NEVER_LOCK is returned the poll-wait will be aborted. * */ -static DRXStatus_t -ScanWaitForLock( pDRXDemodInstance_t demod, - pBool_t isLocked ) +static DRXStatus_t ScanWaitForLock(pDRXDemodInstance_t demod, pBool_t isLocked) { - Bool_t doneWaiting = FALSE; - DRXLockStatus_t lockState = DRX_NOT_LOCKED; - DRXLockStatus_t desiredLockState = DRX_NOT_LOCKED; - u32_t timeoutValue = 0; - u32_t startTimeLockStage = 0; - u32_t currentTime = 0; - u32_t timerValue = 0; - - *isLocked = FALSE; - timeoutValue = (u32_t) demod->myCommonAttr->scanDemodLockTimeout; - desiredLockState = demod->myCommonAttr->scanDesiredLock; - startTimeLockStage = DRXBSP_HST_Clock(); - - /* Start polling loop, checking for lock & timeout */ - while ( doneWaiting == FALSE ) - { - - if ( DRX_Ctrl( demod, DRX_CTRL_LOCK_STATUS, &lockState ) != DRX_STS_OK ) - { - return DRX_STS_ERROR; - } - currentTime = DRXBSP_HST_Clock(); - - timerValue = currentTime - startTimeLockStage; - if ( lockState >= desiredLockState ) - { - *isLocked = TRUE; - doneWaiting = TRUE; - } /* if ( lockState >= desiredLockState ) .. */ - else if ( lockState == DRX_NEVER_LOCK ) - { - doneWaiting = TRUE; - } /* if ( lockState == DRX_NEVER_LOCK ) .. */ - else if ( timerValue > timeoutValue ) - { - /* lockState == DRX_NOT_LOCKED and timeout */ - doneWaiting = TRUE; - } - else - { - if ( DRXBSP_HST_Sleep( 10 ) != DRX_STS_OK ) - { - return DRX_STS_ERROR; - } - } /* if ( timerValue > timeoutValue ) .. */ - - } /* while */ - - return DRX_STS_OK; + Bool_t doneWaiting = FALSE; + DRXLockStatus_t lockState = DRX_NOT_LOCKED; + DRXLockStatus_t desiredLockState = DRX_NOT_LOCKED; + u32_t timeoutValue = 0; + u32_t startTimeLockStage = 0; + u32_t currentTime = 0; + u32_t timerValue = 0; + + *isLocked = FALSE; + timeoutValue = (u32_t) demod->myCommonAttr->scanDemodLockTimeout; + desiredLockState = demod->myCommonAttr->scanDesiredLock; + startTimeLockStage = DRXBSP_HST_Clock(); + + /* Start polling loop, checking for lock & timeout */ + while (doneWaiting == FALSE) { + + if (DRX_Ctrl(demod, DRX_CTRL_LOCK_STATUS, &lockState) != + DRX_STS_OK) { + return DRX_STS_ERROR; + } + currentTime = DRXBSP_HST_Clock(); + + timerValue = currentTime - startTimeLockStage; + if (lockState >= desiredLockState) { + *isLocked = TRUE; + doneWaiting = TRUE; + } /* if ( lockState >= desiredLockState ) .. */ + else if (lockState == DRX_NEVER_LOCK) { + doneWaiting = TRUE; + } /* if ( lockState == DRX_NEVER_LOCK ) .. */ + else if (timerValue > timeoutValue) { + /* lockState == DRX_NOT_LOCKED and timeout */ + doneWaiting = TRUE; + } else { + if (DRXBSP_HST_Sleep(10) != DRX_STS_OK) { + return DRX_STS_ERROR; + } + } /* if ( timerValue > timeoutValue ) .. */ + + } /* while */ + + return DRX_STS_OK; } /*============================================================================*/ @@ -285,73 +274,66 @@ ScanWaitForLock( pDRXDemodInstance_t demod, * */ static DRXStatus_t -ScanPrepareNextScan ( pDRXDemodInstance_t demod, - DRXFrequency_t skip ) +ScanPrepareNextScan(pDRXDemodInstance_t demod, DRXFrequency_t skip) { - pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t)(NULL); - u16_t tableIndex = 0; - u16_t frequencyPlanSize = 0; - pDRXFrequencyPlan_t frequencyPlan = (pDRXFrequencyPlan_t)(NULL); - DRXFrequency_t nextFrequency = 0; - DRXFrequency_t tunerMinFrequency = 0; - DRXFrequency_t tunerMaxFrequency = 0; - - commonAttr = (pDRXCommonAttr_t)demod->myCommonAttr; - tableIndex = commonAttr->scanFreqPlanIndex; - frequencyPlan = commonAttr->scanParam->frequencyPlan; - nextFrequency = commonAttr->scanNextFrequency; - tunerMinFrequency = commonAttr->tunerMinFreqRF; - tunerMaxFrequency = commonAttr->tunerMaxFreqRF; - - do - { - /* Search next frequency to scan */ - - /* always take at least one step */ - (commonAttr->scanChannelsScanned) ++; - nextFrequency += frequencyPlan[tableIndex].step; - skip -= frequencyPlan[tableIndex].step; - - /* and then as many steps necessary to exceed 'skip' - without exceeding end of the band */ - while ( ( skip > 0 ) && - ( nextFrequency <= frequencyPlan[tableIndex].last ) ) - { - (commonAttr->scanChannelsScanned) ++; - nextFrequency += frequencyPlan[tableIndex].step; - skip -= frequencyPlan[tableIndex].step; - } - /* reset skip, in case we move to the next band later */ - skip = 0; - - if ( nextFrequency > frequencyPlan[tableIndex].last ) - { - /* reached end of this band */ - tableIndex++; - frequencyPlanSize = commonAttr->scanParam->frequencyPlanSize; - if ( tableIndex >= frequencyPlanSize ) - { - /* reached end of frequency plan */ - commonAttr->scanReady = TRUE; - } - else - { - nextFrequency = frequencyPlan[tableIndex].first; - } - } - if ( nextFrequency > (tunerMaxFrequency) ) - { - /* reached end of tuner range */ - commonAttr->scanReady = TRUE; - } - } while( ( nextFrequency < tunerMinFrequency ) && - ( commonAttr->scanReady == FALSE ) ); - - /* Store new values */ - commonAttr->scanFreqPlanIndex = tableIndex; - commonAttr->scanNextFrequency = nextFrequency; - - return DRX_STS_OK; + pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); + u16_t tableIndex = 0; + u16_t frequencyPlanSize = 0; + pDRXFrequencyPlan_t frequencyPlan = (pDRXFrequencyPlan_t) (NULL); + DRXFrequency_t nextFrequency = 0; + DRXFrequency_t tunerMinFrequency = 0; + DRXFrequency_t tunerMaxFrequency = 0; + + commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; + tableIndex = commonAttr->scanFreqPlanIndex; + frequencyPlan = commonAttr->scanParam->frequencyPlan; + nextFrequency = commonAttr->scanNextFrequency; + tunerMinFrequency = commonAttr->tunerMinFreqRF; + tunerMaxFrequency = commonAttr->tunerMaxFreqRF; + + do { + /* Search next frequency to scan */ + + /* always take at least one step */ + (commonAttr->scanChannelsScanned)++; + nextFrequency += frequencyPlan[tableIndex].step; + skip -= frequencyPlan[tableIndex].step; + + /* and then as many steps necessary to exceed 'skip' + without exceeding end of the band */ + while ((skip > 0) && + (nextFrequency <= frequencyPlan[tableIndex].last)) { + (commonAttr->scanChannelsScanned)++; + nextFrequency += frequencyPlan[tableIndex].step; + skip -= frequencyPlan[tableIndex].step; + } + /* reset skip, in case we move to the next band later */ + skip = 0; + + if (nextFrequency > frequencyPlan[tableIndex].last) { + /* reached end of this band */ + tableIndex++; + frequencyPlanSize = + commonAttr->scanParam->frequencyPlanSize; + if (tableIndex >= frequencyPlanSize) { + /* reached end of frequency plan */ + commonAttr->scanReady = TRUE; + } else { + nextFrequency = frequencyPlan[tableIndex].first; + } + } + if (nextFrequency > (tunerMaxFrequency)) { + /* reached end of tuner range */ + commonAttr->scanReady = TRUE; + } + } while ((nextFrequency < tunerMinFrequency) && + (commonAttr->scanReady == FALSE)); + + /* Store new values */ + commonAttr->scanFreqPlanIndex = tableIndex; + commonAttr->scanNextFrequency = nextFrequency; + + return DRX_STS_OK; } /*============================================================================*/ @@ -373,47 +355,42 @@ ScanPrepareNextScan ( pDRXDemodInstance_t demod, * scanChannel and getNextChannel will be NULL for INIT and STOP. */ static DRXStatus_t -ScanFunctionDefault ( void *scanContext, - DRXScanCommand_t scanCommand, - pDRXChannel_t scanChannel, - pBool_t getNextChannel ) +ScanFunctionDefault(void *scanContext, + DRXScanCommand_t scanCommand, + pDRXChannel_t scanChannel, pBool_t getNextChannel) { - pDRXDemodInstance_t demod = NULL; - DRXStatus_t status = DRX_STS_ERROR; - Bool_t isLocked = FALSE; - - demod = (pDRXDemodInstance_t) scanContext; - - if ( scanCommand != DRX_SCAN_COMMAND_NEXT ) - { - /* just return OK if not doing "scan next" */ - return DRX_STS_OK; - } - - *getNextChannel = FALSE; - - status = DRX_Ctrl ( demod, DRX_CTRL_SET_CHANNEL, scanChannel ); - if ( status != DRX_STS_OK ) - { - return (status); - } - - status = ScanWaitForLock ( demod, &isLocked ); - if ( status != DRX_STS_OK ) - { - return status; - } - - /* done with this channel, move to next one */ - *getNextChannel = TRUE; - - if ( isLocked == FALSE ) - { - /* no channel found */ - return DRX_STS_BUSY; - } - /* channel found */ - return DRX_STS_OK; + pDRXDemodInstance_t demod = NULL; + DRXStatus_t status = DRX_STS_ERROR; + Bool_t isLocked = FALSE; + + demod = (pDRXDemodInstance_t) scanContext; + + if (scanCommand != DRX_SCAN_COMMAND_NEXT) { + /* just return OK if not doing "scan next" */ + return DRX_STS_OK; + } + + *getNextChannel = FALSE; + + status = DRX_Ctrl(demod, DRX_CTRL_SET_CHANNEL, scanChannel); + if (status != DRX_STS_OK) { + return (status); + } + + status = ScanWaitForLock(demod, &isLocked); + if (status != DRX_STS_OK) { + return status; + } + + /* done with this channel, move to next one */ + *getNextChannel = TRUE; + + if (isLocked == FALSE) { + /* no channel found */ + return DRX_STS_BUSY; + } + /* channel found */ + return DRX_STS_OK; } /*============================================================================*/ @@ -436,150 +413,133 @@ ScanFunctionDefault ( void *scanContext, * */ static DRXStatus_t -CtrlScanInit( pDRXDemodInstance_t demod, - pDRXScanParam_t scanParam ) +CtrlScanInit(pDRXDemodInstance_t demod, pDRXScanParam_t scanParam) { - DRXStatus_t status = DRX_STS_ERROR; - pDRXCommonAttr_t commonAttr =(pDRXCommonAttr_t)(NULL); - DRXFrequency_t maxTunerFreq = 0; - DRXFrequency_t minTunerFreq = 0; - u16_t nrChannelsInPlan = 0; - u16_t i = 0; - void *scanContext = NULL; - - commonAttr = (pDRXCommonAttr_t)demod->myCommonAttr; - commonAttr->scanActive = TRUE; - - /* invalidate a previous SCAN_INIT */ - commonAttr->scanParam = (pDRXScanParam_t)(NULL); - commonAttr->scanNextFrequency = 0; - - /* Check parameters */ - if ( ( ( demod->myTuner == NULL ) && - ( scanParam->numTries !=1) ) || - - ( scanParam == NULL) || - ( scanParam->numTries == 0) || - ( scanParam->frequencyPlan == NULL) || - ( scanParam->frequencyPlanSize == 0 ) - ) - { - commonAttr->scanActive = FALSE; - return DRX_STS_INVALID_ARG; - } - - /* Check frequency plan contents */ - maxTunerFreq = commonAttr->tunerMaxFreqRF; - minTunerFreq = commonAttr->tunerMinFreqRF; - for( i = 0; i < (scanParam->frequencyPlanSize); i++ ) - { - DRXFrequency_t width = 0; - DRXFrequency_t step = scanParam->frequencyPlan[i].step; - DRXFrequency_t firstFreq = scanParam->frequencyPlan[i].first; - DRXFrequency_t lastFreq = scanParam->frequencyPlan[i].last; - DRXFrequency_t minFreq = 0; - DRXFrequency_t maxFreq = 0; - - if ( step <= 0 ) - { - /* Step must be positive and non-zero */ - commonAttr->scanActive = FALSE; - return DRX_STS_INVALID_ARG; - } - - if ( firstFreq > lastFreq ) - { - /* First center frequency is higher than last center frequency */ - commonAttr->scanActive = FALSE; - return DRX_STS_INVALID_ARG; - } - - width = lastFreq - firstFreq; - - if ( ( width % step ) != 0 ) - { - /* Difference between last and first center frequency is not - an integer number of steps */ - commonAttr->scanActive = FALSE; - return DRX_STS_INVALID_ARG; - } - - /* Check if frequency plan entry intersects with tuner range */ - if ( lastFreq >= minTunerFreq ) - { - if ( firstFreq <= maxTunerFreq ) - { - if ( firstFreq >= minTunerFreq ) - { - minFreq = firstFreq; - } - else - { - DRXFrequency_t n = 0; - - n = ( minTunerFreq - firstFreq ) / step; - if ( ( ( minTunerFreq - firstFreq ) % step ) != 0 ) - { - n++; - } - minFreq = firstFreq + n*step; - } - - if ( lastFreq <= maxTunerFreq ) - { - maxFreq = lastFreq; - } - else - { - DRXFrequency_t n=0; - - n=( lastFreq - maxTunerFreq )/step; - if ( (( lastFreq - maxTunerFreq )%step) !=0 ) - { - n++; - } - maxFreq = lastFreq - n*step; - } - } - } - - /* Keep track of total number of channels within tuner range - in this frequency plan. */ - if ( (minFreq !=0 ) && ( maxFreq != 0 ) ) - { - nrChannelsInPlan += (u16_t)( ( ( maxFreq-minFreq ) / step ) +1 ); - - /* Determine first frequency (within tuner range) to scan */ - if ( commonAttr->scanNextFrequency == 0 ) - { - commonAttr->scanNextFrequency = minFreq; - commonAttr->scanFreqPlanIndex = i; - } - } - - }/* for ( ... ) */ - - if ( nrChannelsInPlan == 0 ) - { - /* Tuner range and frequency plan ranges do not overlap */ - commonAttr->scanActive = FALSE; - return DRX_STS_ERROR; - } - - /* Store parameters */ - commonAttr->scanReady = FALSE; - commonAttr->scanMaxChannels = nrChannelsInPlan; - commonAttr->scanChannelsScanned = 0; - commonAttr->scanParam = scanParam; /* SCAN_NEXT is now allowed */ - - scanContext = GetScanContext(demod, scanContext); - - status = (*(GetScanFunction( demod ))) - ( scanContext, DRX_SCAN_COMMAND_INIT, NULL, NULL ); - - commonAttr->scanActive = FALSE; - - return DRX_STS_OK; + DRXStatus_t status = DRX_STS_ERROR; + pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); + DRXFrequency_t maxTunerFreq = 0; + DRXFrequency_t minTunerFreq = 0; + u16_t nrChannelsInPlan = 0; + u16_t i = 0; + void *scanContext = NULL; + + commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; + commonAttr->scanActive = TRUE; + + /* invalidate a previous SCAN_INIT */ + commonAttr->scanParam = (pDRXScanParam_t) (NULL); + commonAttr->scanNextFrequency = 0; + + /* Check parameters */ + if (((demod->myTuner == NULL) && + (scanParam->numTries != 1)) || + (scanParam == NULL) || + (scanParam->numTries == 0) || + (scanParam->frequencyPlan == NULL) || + (scanParam->frequencyPlanSize == 0) + ) { + commonAttr->scanActive = FALSE; + return DRX_STS_INVALID_ARG; + } + + /* Check frequency plan contents */ + maxTunerFreq = commonAttr->tunerMaxFreqRF; + minTunerFreq = commonAttr->tunerMinFreqRF; + for (i = 0; i < (scanParam->frequencyPlanSize); i++) { + DRXFrequency_t width = 0; + DRXFrequency_t step = scanParam->frequencyPlan[i].step; + DRXFrequency_t firstFreq = scanParam->frequencyPlan[i].first; + DRXFrequency_t lastFreq = scanParam->frequencyPlan[i].last; + DRXFrequency_t minFreq = 0; + DRXFrequency_t maxFreq = 0; + + if (step <= 0) { + /* Step must be positive and non-zero */ + commonAttr->scanActive = FALSE; + return DRX_STS_INVALID_ARG; + } + + if (firstFreq > lastFreq) { + /* First center frequency is higher than last center frequency */ + commonAttr->scanActive = FALSE; + return DRX_STS_INVALID_ARG; + } + + width = lastFreq - firstFreq; + + if ((width % step) != 0) { + /* Difference between last and first center frequency is not + an integer number of steps */ + commonAttr->scanActive = FALSE; + return DRX_STS_INVALID_ARG; + } + + /* Check if frequency plan entry intersects with tuner range */ + if (lastFreq >= minTunerFreq) { + if (firstFreq <= maxTunerFreq) { + if (firstFreq >= minTunerFreq) { + minFreq = firstFreq; + } else { + DRXFrequency_t n = 0; + + n = (minTunerFreq - firstFreq) / step; + if (((minTunerFreq - + firstFreq) % step) != 0) { + n++; + } + minFreq = firstFreq + n * step; + } + + if (lastFreq <= maxTunerFreq) { + maxFreq = lastFreq; + } else { + DRXFrequency_t n = 0; + + n = (lastFreq - maxTunerFreq) / step; + if (((lastFreq - + maxTunerFreq) % step) != 0) { + n++; + } + maxFreq = lastFreq - n * step; + } + } + } + + /* Keep track of total number of channels within tuner range + in this frequency plan. */ + if ((minFreq != 0) && (maxFreq != 0)) { + nrChannelsInPlan += + (u16_t) (((maxFreq - minFreq) / step) + 1); + + /* Determine first frequency (within tuner range) to scan */ + if (commonAttr->scanNextFrequency == 0) { + commonAttr->scanNextFrequency = minFreq; + commonAttr->scanFreqPlanIndex = i; + } + } + + } /* for ( ... ) */ + + if (nrChannelsInPlan == 0) { + /* Tuner range and frequency plan ranges do not overlap */ + commonAttr->scanActive = FALSE; + return DRX_STS_ERROR; + } + + /* Store parameters */ + commonAttr->scanReady = FALSE; + commonAttr->scanMaxChannels = nrChannelsInPlan; + commonAttr->scanChannelsScanned = 0; + commonAttr->scanParam = scanParam; /* SCAN_NEXT is now allowed */ + + scanContext = GetScanContext(demod, scanContext); + + status = (*(GetScanFunction(demod))) + (scanContext, DRX_SCAN_COMMAND_INIT, NULL, NULL); + + commonAttr->scanActive = FALSE; + + return DRX_STS_OK; } /*============================================================================*/ @@ -592,36 +552,34 @@ CtrlScanInit( pDRXDemodInstance_t demod, * \retval DRX_STS_ERROR: Something went wrong. * \retval DRX_STS_INVALID_ARG: Wrong parameters. */ -static DRXStatus_t -CtrlScanStop( pDRXDemodInstance_t demod ) +static DRXStatus_t CtrlScanStop(pDRXDemodInstance_t demod) { - DRXStatus_t status = DRX_STS_ERROR; - pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); - void *scanContext = NULL; + DRXStatus_t status = DRX_STS_ERROR; + pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); + void *scanContext = NULL; - commonAttr = (pDRXCommonAttr_t)demod->myCommonAttr; - commonAttr->scanActive = TRUE; + commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; + commonAttr->scanActive = TRUE; - if ( ( commonAttr->scanParam == NULL ) || - ( commonAttr->scanMaxChannels == 0 ) ) - { - /* Scan was not running, just return OK */ - commonAttr->scanActive = FALSE; - return DRX_STS_OK; - } + if ((commonAttr->scanParam == NULL) || + (commonAttr->scanMaxChannels == 0)) { + /* Scan was not running, just return OK */ + commonAttr->scanActive = FALSE; + return DRX_STS_OK; + } - /* Call default or device-specific scanning stop function */ - scanContext = GetScanContext(demod, scanContext); + /* Call default or device-specific scanning stop function */ + scanContext = GetScanContext(demod, scanContext); - status = (*(GetScanFunction( demod ))) - ( scanContext, DRX_SCAN_COMMAND_STOP, NULL, NULL ); + status = (*(GetScanFunction(demod))) + (scanContext, DRX_SCAN_COMMAND_STOP, NULL, NULL); - /* All done, invalidate scan-init */ - commonAttr->scanParam = NULL; - commonAttr->scanMaxChannels = 0; - commonAttr->scanActive = FALSE; + /* All done, invalidate scan-init */ + commonAttr->scanParam = NULL; + commonAttr->scanMaxChannels = 0; + commonAttr->scanActive = FALSE; - return status; + return status; } /*============================================================================*/ @@ -644,120 +602,113 @@ CtrlScanStop( pDRXDemodInstance_t demod ) * Progress indication will run from 0 upto DRX_SCAN_MAX_PROGRESS during scan. * */ -static DRXStatus_t -CtrlScanNext ( pDRXDemodInstance_t demod, - pu16_t scanProgress ) +static DRXStatus_t CtrlScanNext(pDRXDemodInstance_t demod, pu16_t scanProgress) { - pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t)(NULL); - pBool_t scanReady = (pBool_t)(NULL); - u16_t maxProgress = DRX_SCAN_MAX_PROGRESS; - u32_t numTries = 0; - u32_t i = 0; - - commonAttr = (pDRXCommonAttr_t)demod->myCommonAttr; - - /* Check scan parameters */ - if ( scanProgress == NULL ) - { - commonAttr->scanActive = FALSE; - return DRX_STS_INVALID_ARG; - } - - *scanProgress = 0; - commonAttr->scanActive = TRUE; - if ( ( commonAttr->scanParam == NULL) || - ( commonAttr->scanMaxChannels == 0 ) ) - { - /* CtrlScanInit() was not called succesfully before CtrlScanNext() */ - commonAttr->scanActive = FALSE; - return DRX_STS_ERROR; - } - - *scanProgress = (u16_t)( ( ( commonAttr->scanChannelsScanned)* - ( (u32_t)(maxProgress) ) ) / - ( commonAttr->scanMaxChannels ) ); - - /* Scan */ - numTries = commonAttr->scanParam->numTries; - scanReady = &(commonAttr->scanReady); - - for ( i = 0; ( (i < numTries) && ( (*scanReady) == FALSE) ); i++) - { - DRXChannel_t scanChannel = { 0 }; - DRXStatus_t status = DRX_STS_ERROR; - pDRXFrequencyPlan_t freqPlan = (pDRXFrequencyPlan_t) (NULL); - Bool_t nextChannel = FALSE; - void *scanContext = NULL; - - /* Next channel to scan */ - freqPlan = - &(commonAttr->scanParam->frequencyPlan[commonAttr->scanFreqPlanIndex]); - scanChannel.frequency = commonAttr->scanNextFrequency; - scanChannel.bandwidth = freqPlan->bandwidth; - scanChannel.mirror = DRX_MIRROR_AUTO; - scanChannel.constellation = DRX_CONSTELLATION_AUTO; - scanChannel.hierarchy = DRX_HIERARCHY_AUTO; - scanChannel.priority = DRX_PRIORITY_HIGH; - scanChannel.coderate = DRX_CODERATE_AUTO; - scanChannel.guard = DRX_GUARD_AUTO; - scanChannel.fftmode = DRX_FFTMODE_AUTO; - scanChannel.classification = DRX_CLASSIFICATION_AUTO; - scanChannel.symbolrate = 0; - scanChannel.interleavemode = DRX_INTERLEAVEMODE_AUTO; - scanChannel.ldpc = DRX_LDPC_AUTO; - scanChannel.carrier = DRX_CARRIER_AUTO; - scanChannel.framemode = DRX_FRAMEMODE_AUTO; - scanChannel.pilot = DRX_PILOT_AUTO; - - /* Call default or device-specific scanning function */ - scanContext = GetScanContext(demod, scanContext); - - status = (*(GetScanFunction( demod ))) - ( scanContext,DRX_SCAN_COMMAND_NEXT,&scanChannel,&nextChannel ); - - /* Proceed to next channel if requested */ - if ( nextChannel == TRUE ) - { - DRXStatus_t nextStatus = DRX_STS_ERROR; - DRXFrequency_t skip = 0; - - if ( status == DRX_STS_OK ) - { - /* a channel was found, so skip some frequency steps */ - skip = commonAttr->scanParam->skip; - } - nextStatus = ScanPrepareNextScan( demod, skip ); - - /* keep track of progress */ - *scanProgress = (u16_t)(((commonAttr->scanChannelsScanned)* - ((u32_t)(maxProgress)))/ - (commonAttr->scanMaxChannels)); - - if ( nextStatus != DRX_STS_OK ) - { - commonAttr->scanActive = FALSE; - return (nextStatus); - } - } - if ( status != DRX_STS_BUSY ) - { - /* channel found or error */ - commonAttr->scanActive = FALSE; - return status; - } - } /* for ( i = 0; i < ( ... numTries); i++) */ - - if ( (*scanReady) == TRUE ) - { - /* End of scan reached: call stop-scan, ignore any error */ - CtrlScanStop( demod ); - commonAttr->scanActive = FALSE; - return (DRX_STS_READY); - } - - commonAttr->scanActive = FALSE; - - return DRX_STS_BUSY; + pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); + pBool_t scanReady = (pBool_t) (NULL); + u16_t maxProgress = DRX_SCAN_MAX_PROGRESS; + u32_t numTries = 0; + u32_t i = 0; + + commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; + + /* Check scan parameters */ + if (scanProgress == NULL) { + commonAttr->scanActive = FALSE; + return DRX_STS_INVALID_ARG; + } + + *scanProgress = 0; + commonAttr->scanActive = TRUE; + if ((commonAttr->scanParam == NULL) || + (commonAttr->scanMaxChannels == 0)) { + /* CtrlScanInit() was not called succesfully before CtrlScanNext() */ + commonAttr->scanActive = FALSE; + return DRX_STS_ERROR; + } + + *scanProgress = (u16_t) (((commonAttr->scanChannelsScanned) * + ((u32_t) (maxProgress))) / + (commonAttr->scanMaxChannels)); + + /* Scan */ + numTries = commonAttr->scanParam->numTries; + scanReady = &(commonAttr->scanReady); + + for (i = 0; ((i < numTries) && ((*scanReady) == FALSE)); i++) { + DRXChannel_t scanChannel = { 0 }; + DRXStatus_t status = DRX_STS_ERROR; + pDRXFrequencyPlan_t freqPlan = (pDRXFrequencyPlan_t) (NULL); + Bool_t nextChannel = FALSE; + void *scanContext = NULL; + + /* Next channel to scan */ + freqPlan = + &(commonAttr->scanParam-> + frequencyPlan[commonAttr->scanFreqPlanIndex]); + scanChannel.frequency = commonAttr->scanNextFrequency; + scanChannel.bandwidth = freqPlan->bandwidth; + scanChannel.mirror = DRX_MIRROR_AUTO; + scanChannel.constellation = DRX_CONSTELLATION_AUTO; + scanChannel.hierarchy = DRX_HIERARCHY_AUTO; + scanChannel.priority = DRX_PRIORITY_HIGH; + scanChannel.coderate = DRX_CODERATE_AUTO; + scanChannel.guard = DRX_GUARD_AUTO; + scanChannel.fftmode = DRX_FFTMODE_AUTO; + scanChannel.classification = DRX_CLASSIFICATION_AUTO; + scanChannel.symbolrate = 0; + scanChannel.interleavemode = DRX_INTERLEAVEMODE_AUTO; + scanChannel.ldpc = DRX_LDPC_AUTO; + scanChannel.carrier = DRX_CARRIER_AUTO; + scanChannel.framemode = DRX_FRAMEMODE_AUTO; + scanChannel.pilot = DRX_PILOT_AUTO; + + /* Call default or device-specific scanning function */ + scanContext = GetScanContext(demod, scanContext); + + status = (*(GetScanFunction(demod))) + (scanContext, DRX_SCAN_COMMAND_NEXT, &scanChannel, + &nextChannel); + + /* Proceed to next channel if requested */ + if (nextChannel == TRUE) { + DRXStatus_t nextStatus = DRX_STS_ERROR; + DRXFrequency_t skip = 0; + + if (status == DRX_STS_OK) { + /* a channel was found, so skip some frequency steps */ + skip = commonAttr->scanParam->skip; + } + nextStatus = ScanPrepareNextScan(demod, skip); + + /* keep track of progress */ + *scanProgress = + (u16_t) (((commonAttr->scanChannelsScanned) * + ((u32_t) (maxProgress))) / + (commonAttr->scanMaxChannels)); + + if (nextStatus != DRX_STS_OK) { + commonAttr->scanActive = FALSE; + return (nextStatus); + } + } + if (status != DRX_STS_BUSY) { + /* channel found or error */ + commonAttr->scanActive = FALSE; + return status; + } + } /* for ( i = 0; i < ( ... numTries); i++) */ + + if ((*scanReady) == TRUE) { + /* End of scan reached: call stop-scan, ignore any error */ + CtrlScanStop(demod); + commonAttr->scanActive = FALSE; + return (DRX_STS_READY); + } + + commonAttr->scanActive = FALSE; + + return DRX_STS_BUSY; } #endif /* #ifndef DRX_EXCLUDE_SCAN */ @@ -778,117 +729,103 @@ CtrlScanNext ( pDRXDemodInstance_t demod, * */ static DRXStatus_t -CtrlProgramTuner( pDRXDemodInstance_t demod, - pDRXChannel_t channel ) +CtrlProgramTuner(pDRXDemodInstance_t demod, pDRXChannel_t channel) { - pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t)(NULL); - DRXStandard_t standard = DRX_STANDARD_UNKNOWN; - TUNERMode_t tunerMode = 0; - DRXStatus_t status = DRX_STS_ERROR; - DRXFrequency_t ifFrequency = 0; - Bool_t tunerSlowMode = FALSE; - - /* can't tune without a tuner */ - if ( demod->myTuner == NULL ) - { - return DRX_STS_INVALID_ARG; - } - - commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; - - /* select analog or digital tuner mode based on current standard */ - if ( DRX_Ctrl( demod, DRX_CTRL_GET_STANDARD, &standard ) != DRX_STS_OK ) - { - return DRX_STS_ERROR; - } - - if ( DRX_ISATVSTD( standard ) ) - { - tunerMode |= TUNER_MODE_ANALOG; - } - else /* note: also for unknown standard */ - { - tunerMode |= TUNER_MODE_DIGITAL; - } - - /* select tuner bandwidth */ - switch ( channel->bandwidth ) - { - case DRX_BANDWIDTH_6MHZ: - tunerMode |= TUNER_MODE_6MHZ; - break; - case DRX_BANDWIDTH_7MHZ: - tunerMode |= TUNER_MODE_7MHZ; - break; - case DRX_BANDWIDTH_8MHZ: - tunerMode |= TUNER_MODE_8MHZ; - break; - default: /* note: also for unknown bandwidth */ - return DRX_STS_INVALID_ARG; - } - - DRX_GET_TUNERSLOWMODE (demod, tunerSlowMode); - - /* select fast (switch) or slow (lock) tuner mode */ - if ( tunerSlowMode ) - { - tunerMode |= TUNER_MODE_LOCK; - } - else - { - tunerMode |= TUNER_MODE_SWITCH; - } - - if ( commonAttr->tunerPortNr == 1 ) - { - Bool_t bridgeClosed = TRUE; - DRXStatus_t statusBridge = DRX_STS_ERROR; - - statusBridge = DRX_Ctrl( demod, DRX_CTRL_I2C_BRIDGE, &bridgeClosed ); - if ( statusBridge != DRX_STS_OK ) - { - return statusBridge; - } - } - - status = DRXBSP_TUNER_SetFrequency( demod->myTuner, - tunerMode, - channel->frequency ); - - /* attempt restoring bridge before checking status of SetFrequency */ - if ( commonAttr->tunerPortNr == 1 ) - { - Bool_t bridgeClosed = FALSE; - DRXStatus_t statusBridge = DRX_STS_ERROR; - - statusBridge = DRX_Ctrl( demod, DRX_CTRL_I2C_BRIDGE, &bridgeClosed ); - if ( statusBridge != DRX_STS_OK ) - { - return statusBridge; - } - } - - /* now check status of DRXBSP_TUNER_SetFrequency */ - if ( status != DRX_STS_OK ) - { - return status; - } - - /* get actual RF and IF frequencies from tuner */ - status = DRXBSP_TUNER_GetFrequency( demod->myTuner, - tunerMode, - &(channel->frequency), - &(ifFrequency) ); - if ( status != DRX_STS_OK ) - { - return status; - } - - /* update common attributes with information available from this function; - TODO: check if this is required and safe */ - DRX_SET_INTERMEDIATEFREQ( demod, ifFrequency ); - - return DRX_STS_OK; + pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); + DRXStandard_t standard = DRX_STANDARD_UNKNOWN; + TUNERMode_t tunerMode = 0; + DRXStatus_t status = DRX_STS_ERROR; + DRXFrequency_t ifFrequency = 0; + Bool_t tunerSlowMode = FALSE; + + /* can't tune without a tuner */ + if (demod->myTuner == NULL) { + return DRX_STS_INVALID_ARG; + } + + commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; + + /* select analog or digital tuner mode based on current standard */ + if (DRX_Ctrl(demod, DRX_CTRL_GET_STANDARD, &standard) != DRX_STS_OK) { + return DRX_STS_ERROR; + } + + if (DRX_ISATVSTD(standard)) { + tunerMode |= TUNER_MODE_ANALOG; + } else { /* note: also for unknown standard */ + + tunerMode |= TUNER_MODE_DIGITAL; + } + + /* select tuner bandwidth */ + switch (channel->bandwidth) { + case DRX_BANDWIDTH_6MHZ: + tunerMode |= TUNER_MODE_6MHZ; + break; + case DRX_BANDWIDTH_7MHZ: + tunerMode |= TUNER_MODE_7MHZ; + break; + case DRX_BANDWIDTH_8MHZ: + tunerMode |= TUNER_MODE_8MHZ; + break; + default: /* note: also for unknown bandwidth */ + return DRX_STS_INVALID_ARG; + } + + DRX_GET_TUNERSLOWMODE(demod, tunerSlowMode); + + /* select fast (switch) or slow (lock) tuner mode */ + if (tunerSlowMode) { + tunerMode |= TUNER_MODE_LOCK; + } else { + tunerMode |= TUNER_MODE_SWITCH; + } + + if (commonAttr->tunerPortNr == 1) { + Bool_t bridgeClosed = TRUE; + DRXStatus_t statusBridge = DRX_STS_ERROR; + + statusBridge = + DRX_Ctrl(demod, DRX_CTRL_I2C_BRIDGE, &bridgeClosed); + if (statusBridge != DRX_STS_OK) { + return statusBridge; + } + } + + status = DRXBSP_TUNER_SetFrequency(demod->myTuner, + tunerMode, channel->frequency); + + /* attempt restoring bridge before checking status of SetFrequency */ + if (commonAttr->tunerPortNr == 1) { + Bool_t bridgeClosed = FALSE; + DRXStatus_t statusBridge = DRX_STS_ERROR; + + statusBridge = + DRX_Ctrl(demod, DRX_CTRL_I2C_BRIDGE, &bridgeClosed); + if (statusBridge != DRX_STS_OK) { + return statusBridge; + } + } + + /* now check status of DRXBSP_TUNER_SetFrequency */ + if (status != DRX_STS_OK) { + return status; + } + + /* get actual RF and IF frequencies from tuner */ + status = DRXBSP_TUNER_GetFrequency(demod->myTuner, + tunerMode, + &(channel->frequency), + &(ifFrequency)); + if (status != DRX_STS_OK) { + return status; + } + + /* update common attributes with information available from this function; + TODO: check if this is required and safe */ + DRX_SET_INTERMEDIATEFREQ(demod, ifFrequency); + + return DRX_STS_OK; } /*============================================================================*/ @@ -903,41 +840,40 @@ CtrlProgramTuner( pDRXDemodInstance_t demod, * \retval DRX_STS_INVALID_ARG: Wrong parameters. * */ -DRXStatus_t CtrlDumpRegisters( pDRXDemodInstance_t demod, - pDRXRegDump_t registers ) +DRXStatus_t CtrlDumpRegisters(pDRXDemodInstance_t demod, + pDRXRegDump_t registers) { - u16_t i = 0; - - if ( registers == NULL ) - { - /* registers not supplied */ - return DRX_STS_INVALID_ARG; - } - - /* start dumping registers */ - while ( registers[i].address != 0 ) - { - DRXStatus_t status = DRX_STS_ERROR; - u16_t value = 0; - u32_t data = 0; - - status = demod->myAccessFunct->readReg16Func( - demod->myI2CDevAddr, registers[i].address, &value, 0 ); - - data = (u32_t)value; - - if ( status != DRX_STS_OK ) - { - /* no breakouts; - depending on device ID, some HW blocks might not be available */ - data |= ( (u32_t)status ) << 16; - } - registers[i].data = data; - i++; - } - - /* all done, all OK (any errors are saved inside data) */ - return DRX_STS_OK; + u16_t i = 0; + + if (registers == NULL) { + /* registers not supplied */ + return DRX_STS_INVALID_ARG; + } + + /* start dumping registers */ + while (registers[i].address != 0) { + DRXStatus_t status = DRX_STS_ERROR; + u16_t value = 0; + u32_t data = 0; + + status = + demod->myAccessFunct->readReg16Func(demod->myI2CDevAddr, + registers[i].address, + &value, 0); + + data = (u32_t) value; + + if (status != DRX_STS_OK) { + /* no breakouts; + depending on device ID, some HW blocks might not be available */ + data |= ((u32_t) status) << 16; + } + registers[i].data = data; + i++; + } + + /* all done, all OK (any errors are saved inside data) */ + return DRX_STS_OK; } /*============================================================================*/ @@ -955,18 +891,17 @@ DRXStatus_t CtrlDumpRegisters( pDRXDemodInstance_t demod, * host and the data contained in the microcode image file. * */ -static u16_t -UCodeRead16( pu8_t addr) +static u16_t UCodeRead16(pu8_t addr) { - /* Works fo any host processor */ + /* Works fo any host processor */ - u16_t word=0; + u16_t word = 0; - word = ((u16_t)addr[0]); - word <<= 8; - word |=((u16_t)addr[1]); + word = ((u16_t) addr[0]); + word <<= 8; + word |= ((u16_t) addr[1]); - return word; + return word; } /*============================================================================*/ @@ -980,22 +915,21 @@ UCodeRead16( pu8_t addr) * host and the data contained in the microcode image file. * */ -static u32_t -UCodeRead32( pu8_t addr) +static u32_t UCodeRead32(pu8_t addr) { - /* Works fo any host processor */ + /* Works fo any host processor */ - u32_t word=0; + u32_t word = 0; - word = ((u16_t)addr[0]); - word <<= 8; - word |= ((u16_t)addr[1]); - word <<= 8; - word |= ((u16_t)addr[2]); - word <<= 8; - word |= ((u16_t)addr[3]); + word = ((u16_t) addr[0]); + word <<= 8; + word |= ((u16_t) addr[1]); + word <<= 8; + word |= ((u16_t) addr[2]); + word <<= 8; + word |= ((u16_t) addr[3]); - return word ; + return word; } /*============================================================================*/ @@ -1006,30 +940,26 @@ UCodeRead32( pu8_t addr) * \param nrWords: Size of microcode block (number of 16 bits words). * \return u16_t The computed CRC residu. */ -static u16_t -UCodeComputeCRC (pu8_t blockData, u16_t nrWords) +static u16_t UCodeComputeCRC(pu8_t blockData, u16_t nrWords) { - u16_t i = 0; - u16_t j = 0; - u32_t CRCWord = 0; - u32_t carry = 0; - - while ( i < nrWords ) - { - CRCWord |= (u32_t) UCodeRead16(blockData); - for (j = 0; j < 16; j++) - { - CRCWord <<= 1; - if (carry != 0) - { - CRCWord ^= 0x80050000UL; - } - carry = CRCWord & 0x80000000UL; - } - i++; - blockData+=(sizeof(u16_t)); - } - return ((u16_t) (CRCWord >> 16)); + u16_t i = 0; + u16_t j = 0; + u32_t CRCWord = 0; + u32_t carry = 0; + + while (i < nrWords) { + CRCWord |= (u32_t) UCodeRead16(blockData); + for (j = 0; j < 16; j++) { + CRCWord <<= 1; + if (carry != 0) { + CRCWord ^= 0x80050000UL; + } + carry = CRCWord & 0x80000000UL; + } + i++; + blockData += (sizeof(u16_t)); + } + return ((u16_t) (CRCWord >> 16)); } /*============================================================================*/ @@ -1053,213 +983,213 @@ UCodeComputeCRC (pu8_t blockData, u16_t nrWords) * - Provided image is corrupt */ static DRXStatus_t -CtrlUCode( pDRXDemodInstance_t demod, - pDRXUCodeInfo_t mcInfo, - DRXUCodeAction_t action) +CtrlUCode(pDRXDemodInstance_t demod, + pDRXUCodeInfo_t mcInfo, DRXUCodeAction_t action) { - DRXStatus_t rc; - u16_t i = 0; - u16_t mcNrOfBlks = 0; - u16_t mcMagicWord = 0; - pu8_t mcData = (pu8_t)(NULL); - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)(NULL); - - devAddr = demod -> myI2CDevAddr; - - /* Check arguments */ - if ( ( mcInfo == NULL ) || - ( mcInfo->mcData == NULL ) ) - { - return DRX_STS_INVALID_ARG; - } - - mcData = mcInfo->mcData; - - /* Check data */ - mcMagicWord = UCodeRead16( mcData ); - mcData += sizeof( u16_t ); - mcNrOfBlks = UCodeRead16( mcData ); - mcData += sizeof( u16_t ); - - if ( ( mcMagicWord != DRX_UCODE_MAGIC_WORD ) || - ( mcNrOfBlks == 0 ) ) - { - /* wrong endianess or wrong data ? */ - return DRX_STS_INVALID_ARG; - } - - /* Scan microcode blocks first for version info if uploading */ - if (action == UCODE_UPLOAD) - { - /* Clear version block */ - DRX_SET_MCVERTYPE (demod, 0); - DRX_SET_MCDEV (demod, 0); - DRX_SET_MCVERSION (demod, 0); - DRX_SET_MCPATCH (demod, 0); - for (i = 0; i < mcNrOfBlks; i++) - { - DRXUCodeBlockHdr_t blockHdr; - - /* Process block header */ - blockHdr.addr = UCodeRead32( mcData ); - mcData += sizeof(u32_t); - blockHdr.size = UCodeRead16( mcData ); - mcData += sizeof(u16_t); - blockHdr.flags = UCodeRead16( mcData ); - mcData += sizeof(u16_t); - blockHdr.CRC = UCodeRead16( mcData ); - mcData += sizeof(u16_t); - - if (blockHdr.flags & 0x8) - { - /* Aux block. Check type */ - pu8_t auxblk = mcInfo->mcData + blockHdr.addr; - u16_t auxtype = UCodeRead16 (auxblk); - if (DRX_ISMCVERTYPE (auxtype)) - { - DRX_SET_MCVERTYPE (demod, UCodeRead16 (auxblk)); - auxblk += sizeof (u16_t); - DRX_SET_MCDEV (demod, UCodeRead32 (auxblk)); - auxblk += sizeof (u32_t); - DRX_SET_MCVERSION (demod, UCodeRead32 (auxblk)); - auxblk += sizeof (u32_t); - DRX_SET_MCPATCH (demod, UCodeRead32 (auxblk)); - } - } - - /* Next block */ - mcData += blockHdr.size * sizeof (u16_t); - } - - /* After scanning, validate the microcode. - It is also valid if no validation control exists. - */ - rc = DRX_Ctrl (demod, DRX_CTRL_VALIDATE_UCODE, NULL); - if (rc != DRX_STS_OK && rc != DRX_STS_FUNC_NOT_AVAILABLE) - { - return rc; - } - - /* Restore data pointer */ - mcData = mcInfo->mcData + 2 * sizeof( u16_t ); - } - - /* Process microcode blocks */ - for( i = 0 ; i 0x7FFF ) || - ( ( ( blockHdr.flags & DRX_UCODE_CRC_FLAG ) != 0 ) && - ( blockHdr.CRC != UCodeComputeCRC ( mcData, blockHdr.size) ) ) - ) - { - /* Wrong data ! */ - return DRX_STS_INVALID_ARG; - } - - mcBlockNrBytes = blockHdr.size * ((u16_t)sizeof( u16_t )); - - if ( blockHdr.size != 0 ) - { - /* Perform the desired action */ - switch ( action ) { + DRXStatus_t rc; + u16_t i = 0; + u16_t mcNrOfBlks = 0; + u16_t mcMagicWord = 0; + pu8_t mcData = (pu8_t) (NULL); + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) (NULL); + + devAddr = demod->myI2CDevAddr; + + /* Check arguments */ + if ((mcInfo == NULL) || (mcInfo->mcData == NULL)) { + return DRX_STS_INVALID_ARG; + } + + mcData = mcInfo->mcData; + + /* Check data */ + mcMagicWord = UCodeRead16(mcData); + mcData += sizeof(u16_t); + mcNrOfBlks = UCodeRead16(mcData); + mcData += sizeof(u16_t); + + if ((mcMagicWord != DRX_UCODE_MAGIC_WORD) || (mcNrOfBlks == 0)) { + /* wrong endianess or wrong data ? */ + return DRX_STS_INVALID_ARG; + } + + /* Scan microcode blocks first for version info if uploading */ + if (action == UCODE_UPLOAD) { + /* Clear version block */ + DRX_SET_MCVERTYPE(demod, 0); + DRX_SET_MCDEV(demod, 0); + DRX_SET_MCVERSION(demod, 0); + DRX_SET_MCPATCH(demod, 0); + for (i = 0; i < mcNrOfBlks; i++) { + DRXUCodeBlockHdr_t blockHdr; + + /* Process block header */ + blockHdr.addr = UCodeRead32(mcData); + mcData += sizeof(u32_t); + blockHdr.size = UCodeRead16(mcData); + mcData += sizeof(u16_t); + blockHdr.flags = UCodeRead16(mcData); + mcData += sizeof(u16_t); + blockHdr.CRC = UCodeRead16(mcData); + mcData += sizeof(u16_t); + + if (blockHdr.flags & 0x8) { + /* Aux block. Check type */ + pu8_t auxblk = mcInfo->mcData + blockHdr.addr; + u16_t auxtype = UCodeRead16(auxblk); + if (DRX_ISMCVERTYPE(auxtype)) { + DRX_SET_MCVERTYPE(demod, + UCodeRead16(auxblk)); + auxblk += sizeof(u16_t); + DRX_SET_MCDEV(demod, + UCodeRead32(auxblk)); + auxblk += sizeof(u32_t); + DRX_SET_MCVERSION(demod, + UCodeRead32(auxblk)); + auxblk += sizeof(u32_t); + DRX_SET_MCPATCH(demod, + UCodeRead32(auxblk)); + } + } + + /* Next block */ + mcData += blockHdr.size * sizeof(u16_t); + } + + /* After scanning, validate the microcode. + It is also valid if no validation control exists. + */ + rc = DRX_Ctrl(demod, DRX_CTRL_VALIDATE_UCODE, NULL); + if (rc != DRX_STS_OK && rc != DRX_STS_FUNC_NOT_AVAILABLE) { + return rc; + } + + /* Restore data pointer */ + mcData = mcInfo->mcData + 2 * sizeof(u16_t); + } + + /* Process microcode blocks */ + for (i = 0; i < mcNrOfBlks; i++) { + DRXUCodeBlockHdr_t blockHdr; + u16_t mcBlockNrBytes = 0; + + /* Process block header */ + blockHdr.addr = UCodeRead32(mcData); + mcData += sizeof(u32_t); + blockHdr.size = UCodeRead16(mcData); + mcData += sizeof(u16_t); + blockHdr.flags = UCodeRead16(mcData); + mcData += sizeof(u16_t); + blockHdr.CRC = UCodeRead16(mcData); + mcData += sizeof(u16_t); + + /* Check block header on: + - data larger than 64Kb + - if CRC enabled check CRC + */ + if ((blockHdr.size > 0x7FFF) || + (((blockHdr.flags & DRX_UCODE_CRC_FLAG) != 0) && + (blockHdr.CRC != UCodeComputeCRC(mcData, blockHdr.size))) + ) { + /* Wrong data ! */ + return DRX_STS_INVALID_ARG; + } + + mcBlockNrBytes = blockHdr.size * ((u16_t) sizeof(u16_t)); + + if (blockHdr.size != 0) { + /* Perform the desired action */ + switch (action) { /*================================================================*/ - case UCODE_UPLOAD : - { - /* Upload microcode */ - if ( demod->myAccessFunct->writeBlockFunc( - devAddr, - (DRXaddr_t) blockHdr.addr, - mcBlockNrBytes, - mcData, - 0x0000) != DRX_STS_OK) - { - return (DRX_STS_ERROR); - } /* if */ - }; - break; + case UCODE_UPLOAD: + { + /* Upload microcode */ + if (demod->myAccessFunct-> + writeBlockFunc(devAddr, + (DRXaddr_t) blockHdr. + addr, mcBlockNrBytes, + mcData, + 0x0000) != + DRX_STS_OK) { + return (DRX_STS_ERROR); + } /* if */ + }; + break; /*================================================================*/ - case UCODE_VERIFY : - { - int result = 0; - u8_t mcDataBuffer[DRX_UCODE_MAX_BUF_SIZE]; - u32_t bytesToCompare=0; - u32_t bytesLeftToCompare=0; - DRXaddr_t currAddr = (DRXaddr_t)0; - pu8_t currPtr =NULL; - - bytesLeftToCompare = mcBlockNrBytes; - currAddr = blockHdr.addr; - currPtr = mcData; - - while( bytesLeftToCompare != 0 ) - { - if (bytesLeftToCompare > ( (u32_t)DRX_UCODE_MAX_BUF_SIZE) ) - { - bytesToCompare = ( (u32_t)DRX_UCODE_MAX_BUF_SIZE ); - } - else - { - bytesToCompare = bytesLeftToCompare; - } - - if ( demod->myAccessFunct->readBlockFunc( - devAddr, - currAddr, - (u16_t)bytesToCompare, - (pu8_t)mcDataBuffer, - 0x0000) != DRX_STS_OK) - { - return (DRX_STS_ERROR); - } - - result = DRXBSP_HST_Memcmp( currPtr, - mcDataBuffer, - bytesToCompare); - - if ( result != 0 ) - { - return DRX_STS_ERROR; - } - - currAddr += ((DRXaddr_t)(bytesToCompare/2)); - currPtr = &(currPtr[bytesToCompare]); - bytesLeftToCompare -= ((u32_t)bytesToCompare); - } /* while( bytesToCompare > DRX_UCODE_MAX_BUF_SIZE ) */ - }; - break; + case UCODE_VERIFY: + { + int result = 0; + u8_t mcDataBuffer + [DRX_UCODE_MAX_BUF_SIZE]; + u32_t bytesToCompare = 0; + u32_t bytesLeftToCompare = 0; + DRXaddr_t currAddr = (DRXaddr_t) 0; + pu8_t currPtr = NULL; + + bytesLeftToCompare = mcBlockNrBytes; + currAddr = blockHdr.addr; + currPtr = mcData; + + while (bytesLeftToCompare != 0) { + if (bytesLeftToCompare > + ((u32_t) + DRX_UCODE_MAX_BUF_SIZE)) { + bytesToCompare = + ((u32_t) + DRX_UCODE_MAX_BUF_SIZE); + } else { + bytesToCompare = + bytesLeftToCompare; + } + + if (demod->myAccessFunct-> + readBlockFunc(devAddr, + currAddr, + (u16_t) + bytesToCompare, + (pu8_t) + mcDataBuffer, + 0x0000) != + DRX_STS_OK) { + return (DRX_STS_ERROR); + } + + result = + DRXBSP_HST_Memcmp(currPtr, + mcDataBuffer, + bytesToCompare); + + if (result != 0) { + return DRX_STS_ERROR; + } + + currAddr += + ((DRXaddr_t) + (bytesToCompare / 2)); + currPtr = + &(currPtr[bytesToCompare]); + bytesLeftToCompare -= + ((u32_t) bytesToCompare); + } /* while( bytesToCompare > DRX_UCODE_MAX_BUF_SIZE ) */ + }; + break; /*================================================================*/ - default: - return DRX_STS_INVALID_ARG; - break; + default: + return DRX_STS_INVALID_ARG; + break; - } /* switch ( action ) */ - } /* if (blockHdr.size != 0 ) */ + } /* switch ( action ) */ + } - /* Next block */ - mcData += mcBlockNrBytes; + /* if (blockHdr.size != 0 ) */ + /* Next block */ + mcData += mcBlockNrBytes; - } /* for( i = 0 ; imyDemodFunct->ctrlFunc))( - demod, - DRX_CTRL_VERSION, - (void *) &demodVersionList ); - - /* Always fill in the information of the driver SW . */ - drxDriverCoreVersion.moduleType = DRX_MODULE_DRIVERCORE; - drxDriverCoreVersion.moduleName = drxDriverCoreModuleName; - drxDriverCoreVersion.vMajor = VERSION_MAJOR; - drxDriverCoreVersion.vMinor = VERSION_MINOR; - drxDriverCoreVersion.vPatch = VERSION_PATCH; - drxDriverCoreVersion.vString = drxDriverCoreVersionText; - - drxDriverCoreVersionList.version = &drxDriverCoreVersion; - drxDriverCoreVersionList.next = (pDRXVersionList_t)(NULL); - - if ( ( returnStatus == DRX_STS_OK ) && ( demodVersionList != NULL ) ) - { - /* Append versioninfo from driver to versioninfo from demod */ - /* Return version info in "bottom-up" order. This way, multiple - devices can be handled without using malloc. */ - pDRXVersionList_t currentListElement = demodVersionList; - while ( currentListElement->next != NULL ) - { - currentListElement = currentListElement->next; - } - currentListElement->next = &drxDriverCoreVersionList; - - *versionList = demodVersionList; - } - else - { - /* Just return versioninfo from driver */ - *versionList = &drxDriverCoreVersionList; - } - - return DRX_STS_OK; + static char drxDriverCoreModuleName[] = "Core driver"; + static char drxDriverCoreVersionText[] = + DRX_VERSIONSTRING(VERSION_MAJOR, VERSION_MINOR, VERSION_PATCH); + + static DRXVersion_t drxDriverCoreVersion; + static DRXVersionList_t drxDriverCoreVersionList; + + pDRXVersionList_t demodVersionList = (pDRXVersionList_t) (NULL); + DRXStatus_t returnStatus = DRX_STS_ERROR; + + /* Check arguments */ + if (versionList == NULL) { + return DRX_STS_INVALID_ARG; + } + + /* Get version info list from demod */ + returnStatus = (*(demod->myDemodFunct->ctrlFunc)) (demod, + DRX_CTRL_VERSION, + (void *) + &demodVersionList); + + /* Always fill in the information of the driver SW . */ + drxDriverCoreVersion.moduleType = DRX_MODULE_DRIVERCORE; + drxDriverCoreVersion.moduleName = drxDriverCoreModuleName; + drxDriverCoreVersion.vMajor = VERSION_MAJOR; + drxDriverCoreVersion.vMinor = VERSION_MINOR; + drxDriverCoreVersion.vPatch = VERSION_PATCH; + drxDriverCoreVersion.vString = drxDriverCoreVersionText; + + drxDriverCoreVersionList.version = &drxDriverCoreVersion; + drxDriverCoreVersionList.next = (pDRXVersionList_t) (NULL); + + if ((returnStatus == DRX_STS_OK) && (demodVersionList != NULL)) { + /* Append versioninfo from driver to versioninfo from demod */ + /* Return version info in "bottom-up" order. This way, multiple + devices can be handled without using malloc. */ + pDRXVersionList_t currentListElement = demodVersionList; + while (currentListElement->next != NULL) { + currentListElement = currentListElement->next; + } + currentListElement->next = &drxDriverCoreVersionList; + + *versionList = demodVersionList; + } else { + /* Just return versioninfo from driver */ + *versionList = &drxDriverCoreVersionList; + } + + return DRX_STS_OK; } /*============================================================================*/ @@ -1338,8 +1262,6 @@ CtrlVersion( pDRXDemodInstance_t demod, /*============================================================================*/ /*============================================================================*/ - - /** * \brief This function is obsolete. * \param demods: Don't care, parameter is ignored. @@ -1350,10 +1272,9 @@ CtrlVersion( pDRXDemodInstance_t demod, * */ -DRXStatus_t -DRX_Init( pDRXDemodInstance_t demods[] ) +DRXStatus_t DRX_Init(pDRXDemodInstance_t demods[]) { - return DRX_STS_OK; + return DRX_STS_OK; } /*============================================================================*/ @@ -1367,10 +1288,9 @@ DRX_Init( pDRXDemodInstance_t demods[] ) * */ -DRXStatus_t -DRX_Term( void ) +DRXStatus_t DRX_Term(void) { - return DRX_STS_OK; + return DRX_STS_OK; } /*============================================================================*/ @@ -1386,29 +1306,26 @@ DRX_Term( void ) * */ -DRXStatus_t -DRX_Open(pDRXDemodInstance_t demod) +DRXStatus_t DRX_Open(pDRXDemodInstance_t demod) { - DRXStatus_t status = DRX_STS_OK; - - if ( ( demod == NULL ) || - ( demod->myDemodFunct == NULL ) || - ( demod->myCommonAttr == NULL ) || - ( demod->myExtAttr == NULL ) || - ( demod->myI2CDevAddr == NULL ) || - ( demod->myCommonAttr->isOpened == TRUE )) - { - return (DRX_STS_INVALID_ARG); - } - - status = (*(demod->myDemodFunct->openFunc))( demod ); - - if ( status == DRX_STS_OK ) - { - demod->myCommonAttr->isOpened = TRUE; - } - - return status; + DRXStatus_t status = DRX_STS_OK; + + if ((demod == NULL) || + (demod->myDemodFunct == NULL) || + (demod->myCommonAttr == NULL) || + (demod->myExtAttr == NULL) || + (demod->myI2CDevAddr == NULL) || + (demod->myCommonAttr->isOpened == TRUE)) { + return (DRX_STS_INVALID_ARG); + } + + status = (*(demod->myDemodFunct->openFunc)) (demod); + + if (status == DRX_STS_OK) { + demod->myCommonAttr->isOpened = TRUE; + } + + return status; } /*============================================================================*/ @@ -1426,26 +1343,24 @@ DRX_Open(pDRXDemodInstance_t demod) * Put device into sleep mode. */ -DRXStatus_t -DRX_Close(pDRXDemodInstance_t demod) +DRXStatus_t DRX_Close(pDRXDemodInstance_t demod) { - DRXStatus_t status = DRX_STS_OK; + DRXStatus_t status = DRX_STS_OK; - if ( ( demod == NULL ) || - ( demod->myDemodFunct == NULL ) || - ( demod->myCommonAttr == NULL ) || - ( demod->myExtAttr == NULL ) || - ( demod->myI2CDevAddr == NULL ) || - ( demod->myCommonAttr->isOpened == FALSE )) - { - return DRX_STS_INVALID_ARG; - } + if ((demod == NULL) || + (demod->myDemodFunct == NULL) || + (demod->myCommonAttr == NULL) || + (demod->myExtAttr == NULL) || + (demod->myI2CDevAddr == NULL) || + (demod->myCommonAttr->isOpened == FALSE)) { + return DRX_STS_INVALID_ARG; + } - status = (*(demod->myDemodFunct->closeFunc))( demod ); + status = (*(demod->myDemodFunct->closeFunc)) (demod); - DRX_SET_ISOPENED (demod, FALSE); + DRX_SET_ISOPENED(demod, FALSE); - return status; + return status; } /*============================================================================*/ @@ -1471,130 +1386,125 @@ DRX_Close(pDRXDemodInstance_t demod) DRXStatus_t DRX_Ctrl(pDRXDemodInstance_t demod, DRXCtrlIndex_t ctrl, void *ctrlData) { - DRXStatus_t status = DRX_STS_ERROR; - - if ( ( demod == NULL ) || - ( demod->myDemodFunct == NULL ) || - ( demod->myCommonAttr == NULL ) || - ( demod->myExtAttr == NULL ) || - ( demod->myI2CDevAddr == NULL ) - ) - { - return (DRX_STS_INVALID_ARG); - } - - if ( ( ( demod->myCommonAttr->isOpened == FALSE ) && - ( ctrl != DRX_CTRL_PROBE_DEVICE ) && - ( ctrl != DRX_CTRL_VERSION) ) - ) - { - return (DRX_STS_INVALID_ARG); - } - - if ( ( DRX_ISPOWERDOWNMODE( demod->myCommonAttr->currentPowerMode ) && - ( ctrl != DRX_CTRL_POWER_MODE ) && - ( ctrl != DRX_CTRL_PROBE_DEVICE ) && - ( ctrl != DRX_CTRL_NOP ) && - ( ctrl != DRX_CTRL_VERSION) - ) - ) - { - return DRX_STS_FUNC_NOT_AVAILABLE; - } - - /* Fixed control functions */ - switch ( ctrl ) { + DRXStatus_t status = DRX_STS_ERROR; + + if ((demod == NULL) || + (demod->myDemodFunct == NULL) || + (demod->myCommonAttr == NULL) || + (demod->myExtAttr == NULL) || (demod->myI2CDevAddr == NULL) + ) { + return (DRX_STS_INVALID_ARG); + } + + if (((demod->myCommonAttr->isOpened == FALSE) && + (ctrl != DRX_CTRL_PROBE_DEVICE) && (ctrl != DRX_CTRL_VERSION)) + ) { + return (DRX_STS_INVALID_ARG); + } + + if ((DRX_ISPOWERDOWNMODE(demod->myCommonAttr->currentPowerMode) && + (ctrl != DRX_CTRL_POWER_MODE) && + (ctrl != DRX_CTRL_PROBE_DEVICE) && + (ctrl != DRX_CTRL_NOP) && (ctrl != DRX_CTRL_VERSION) + ) + ) { + return DRX_STS_FUNC_NOT_AVAILABLE; + } + + /* Fixed control functions */ + switch (ctrl) { /*======================================================================*/ - case DRX_CTRL_NOP: - /* No operation */ - return DRX_STS_OK; - break; + case DRX_CTRL_NOP: + /* No operation */ + return DRX_STS_OK; + break; /*======================================================================*/ - case DRX_CTRL_VERSION: - return CtrlVersion( demod, (pDRXVersionList_t *) ctrlData ); - break; + case DRX_CTRL_VERSION: + return CtrlVersion(demod, (pDRXVersionList_t *) ctrlData); + break; /*======================================================================*/ - default : - /* Do nothing */ - break; - } - - /* Virtual functions */ - /* First try calling function from derived class */ - status = (*(demod->myDemodFunct->ctrlFunc))( demod, ctrl, ctrlData ); - if (status == DRX_STS_FUNC_NOT_AVAILABLE) - { - /* Now try calling a the base class function */ - switch ( ctrl ) { + default: + /* Do nothing */ + break; + } + + /* Virtual functions */ + /* First try calling function from derived class */ + status = (*(demod->myDemodFunct->ctrlFunc)) (demod, ctrl, ctrlData); + if (status == DRX_STS_FUNC_NOT_AVAILABLE) { + /* Now try calling a the base class function */ + switch (ctrl) { /*===================================================================*/ - case DRX_CTRL_LOAD_UCODE: - return CtrlUCode ( demod, - (pDRXUCodeInfo_t) ctrlData, - UCODE_UPLOAD ); - break; + case DRX_CTRL_LOAD_UCODE: + return CtrlUCode(demod, + (pDRXUCodeInfo_t) ctrlData, + UCODE_UPLOAD); + break; /*===================================================================*/ - case DRX_CTRL_VERIFY_UCODE: - { - return CtrlUCode ( demod, - (pDRXUCodeInfo_t) ctrlData, - UCODE_VERIFY); - } - break; + case DRX_CTRL_VERIFY_UCODE: + { + return CtrlUCode(demod, + (pDRXUCodeInfo_t) ctrlData, + UCODE_VERIFY); + } + break; #ifndef DRX_EXCLUDE_SCAN /*===================================================================*/ - case DRX_CTRL_SCAN_INIT: - { - return CtrlScanInit( demod, (pDRXScanParam_t) ctrlData ); - } - break; + case DRX_CTRL_SCAN_INIT: + { + return CtrlScanInit(demod, + (pDRXScanParam_t) ctrlData); + } + break; /*===================================================================*/ - case DRX_CTRL_SCAN_NEXT: - { - return CtrlScanNext( demod, (pu16_t) ctrlData ); - } - break; + case DRX_CTRL_SCAN_NEXT: + { + return CtrlScanNext(demod, (pu16_t) ctrlData); + } + break; /*===================================================================*/ - case DRX_CTRL_SCAN_STOP: - { - return CtrlScanStop( demod ); - } - break; + case DRX_CTRL_SCAN_STOP: + { + return CtrlScanStop(demod); + } + break; #endif /* #ifndef DRX_EXCLUDE_SCAN */ /*===================================================================*/ - case DRX_CTRL_PROGRAM_TUNER: - { - return CtrlProgramTuner( demod, (pDRXChannel_t) ctrlData ); - } - break; + case DRX_CTRL_PROGRAM_TUNER: + { + return CtrlProgramTuner(demod, + (pDRXChannel_t) + ctrlData); + } + break; /*===================================================================*/ - case DRX_CTRL_DUMP_REGISTERS: - { - return CtrlDumpRegisters( demod, (pDRXRegDump_t) ctrlData ); - } - break; + case DRX_CTRL_DUMP_REGISTERS: + { + return CtrlDumpRegisters(demod, + (pDRXRegDump_t) + ctrlData); + } + break; /*===================================================================*/ - default : - return DRX_STS_FUNC_NOT_AVAILABLE; - } - } - else - { - return (status); - } - - return DRX_STS_OK; + default: + return DRX_STS_FUNC_NOT_AVAILABLE; + } + } else { + return (status); + } + + return DRX_STS_OK; } - /*============================================================================*/ /* END OF FILE */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h index 0533344..712ffd5 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h @@ -140,7 +140,6 @@ DEFINES #define DRX_AUTO (255) #endif - /************** * * This section describes flag definitions for the device capbilities. @@ -295,258 +294,292 @@ ENUM * \enum DRXStandard_t * \brief Modulation standards. */ -typedef enum { - DRX_STANDARD_DVBT = 0, /**< Terrestrial DVB-T. */ - DRX_STANDARD_8VSB, /**< Terrestrial 8VSB. */ - DRX_STANDARD_NTSC, /**< Terrestrial\Cable analog NTSC. */ - DRX_STANDARD_PAL_SECAM_BG, /**< Terrestrial analog PAL/SECAM B/G */ - DRX_STANDARD_PAL_SECAM_DK, /**< Terrestrial analog PAL/SECAM D/K */ - DRX_STANDARD_PAL_SECAM_I, /**< Terrestrial analog PAL/SECAM I */ - DRX_STANDARD_PAL_SECAM_L, /**< Terrestrial analog PAL/SECAM L + typedef enum { + DRX_STANDARD_DVBT = 0, /**< Terrestrial DVB-T. */ + DRX_STANDARD_8VSB, /**< Terrestrial 8VSB. */ + DRX_STANDARD_NTSC, /**< Terrestrial\Cable analog NTSC. */ + DRX_STANDARD_PAL_SECAM_BG, + /**< Terrestrial analog PAL/SECAM B/G */ + DRX_STANDARD_PAL_SECAM_DK, + /**< Terrestrial analog PAL/SECAM D/K */ + DRX_STANDARD_PAL_SECAM_I, + /**< Terrestrial analog PAL/SECAM I */ + DRX_STANDARD_PAL_SECAM_L, + /**< Terrestrial analog PAL/SECAM L with negative modulation */ - DRX_STANDARD_PAL_SECAM_LP, /**< Terrestrial analog PAL/SECAM L + DRX_STANDARD_PAL_SECAM_LP, + /**< Terrestrial analog PAL/SECAM L with positive modulation */ - DRX_STANDARD_ITU_A, /**< Cable ITU ANNEX A. */ - DRX_STANDARD_ITU_B, /**< Cable ITU ANNEX B. */ - DRX_STANDARD_ITU_C, /**< Cable ITU ANNEX C. */ - DRX_STANDARD_ITU_D, /**< Cable ITU ANNEX D. */ - DRX_STANDARD_FM, /**< Terrestrial\Cable FM radio */ - DRX_STANDARD_DTMB, /**< Terrestrial DTMB standard (China)*/ - DRX_STANDARD_UNKNOWN = DRX_UNKNOWN, /**< Standard unknown. */ - DRX_STANDARD_AUTO = DRX_AUTO /**< Autodetect standard. */ -} DRXStandard_t, *pDRXStandard_t; + DRX_STANDARD_ITU_A, /**< Cable ITU ANNEX A. */ + DRX_STANDARD_ITU_B, /**< Cable ITU ANNEX B. */ + DRX_STANDARD_ITU_C, /**< Cable ITU ANNEX C. */ + DRX_STANDARD_ITU_D, /**< Cable ITU ANNEX D. */ + DRX_STANDARD_FM, /**< Terrestrial\Cable FM radio */ + DRX_STANDARD_DTMB, /**< Terrestrial DTMB standard (China)*/ + DRX_STANDARD_UNKNOWN = DRX_UNKNOWN, + /**< Standard unknown. */ + DRX_STANDARD_AUTO = DRX_AUTO + /**< Autodetect standard. */ + } DRXStandard_t, *pDRXStandard_t; /** * \enum DRXStandard_t * \brief Modulation sub-standards. */ -typedef enum { - DRX_SUBSTANDARD_MAIN = 0, /**< Main subvariant of standard */ - DRX_SUBSTANDARD_ATV_BG_SCANDINAVIA, - DRX_SUBSTANDARD_ATV_DK_POLAND, - DRX_SUBSTANDARD_ATV_DK_CHINA, - DRX_SUBSTANDARD_UNKNOWN = DRX_UNKNOWN, /**< Sub-standard unknown. */ - DRX_SUBSTANDARD_AUTO = DRX_AUTO /**< Auto (default) sub-standard */ -} DRXSubstandard_t, *pDRXSubstandard_t; + typedef enum { + DRX_SUBSTANDARD_MAIN = 0, /**< Main subvariant of standard */ + DRX_SUBSTANDARD_ATV_BG_SCANDINAVIA, + DRX_SUBSTANDARD_ATV_DK_POLAND, + DRX_SUBSTANDARD_ATV_DK_CHINA, + DRX_SUBSTANDARD_UNKNOWN = DRX_UNKNOWN, + /**< Sub-standard unknown. */ + DRX_SUBSTANDARD_AUTO = DRX_AUTO + /**< Auto (default) sub-standard */ + } DRXSubstandard_t, *pDRXSubstandard_t; /** * \enum DRXBandwidth_t * \brief Channel bandwidth or channel spacing. */ -typedef enum { - DRX_BANDWIDTH_8MHZ = 0, /**< Bandwidth 8 MHz. */ - DRX_BANDWIDTH_7MHZ, /**< Bandwidth 7 MHz. */ - DRX_BANDWIDTH_6MHZ, /**< Bandwidth 6 MHz. */ - DRX_BANDWIDTH_UNKNOWN = DRX_UNKNOWN, /**< Bandwidth unknown. */ - DRX_BANDWIDTH_AUTO = DRX_AUTO /**< Auto Set Bandwidth */ -} DRXBandwidth_t, *pDRXBandwidth_t; + typedef enum { + DRX_BANDWIDTH_8MHZ = 0, /**< Bandwidth 8 MHz. */ + DRX_BANDWIDTH_7MHZ, /**< Bandwidth 7 MHz. */ + DRX_BANDWIDTH_6MHZ, /**< Bandwidth 6 MHz. */ + DRX_BANDWIDTH_UNKNOWN = DRX_UNKNOWN, + /**< Bandwidth unknown. */ + DRX_BANDWIDTH_AUTO = DRX_AUTO + /**< Auto Set Bandwidth */ + } DRXBandwidth_t, *pDRXBandwidth_t; /** * \enum DRXMirror_t * \brief Indicate if channel spectrum is mirrored or not. */ -typedef enum { - DRX_MIRROR_NO = 0, /**< Spectrum is not mirrored. */ - DRX_MIRROR_YES, /**< Spectrum is mirrored. */ - DRX_MIRROR_UNKNOWN = DRX_UNKNOWN, /**< Unknown if spectrum is mirrored. */ - DRX_MIRROR_AUTO = DRX_AUTO /**< Autodetect if spectrum is mirrored. */ -} DRXMirror_t, *pDRXMirror_t; + typedef enum { + DRX_MIRROR_NO = 0, /**< Spectrum is not mirrored. */ + DRX_MIRROR_YES, /**< Spectrum is mirrored. */ + DRX_MIRROR_UNKNOWN = DRX_UNKNOWN, + /**< Unknown if spectrum is mirrored. */ + DRX_MIRROR_AUTO = DRX_AUTO + /**< Autodetect if spectrum is mirrored. */ + } DRXMirror_t, *pDRXMirror_t; /** * \enum DRXConstellation_t * \brief Constellation type of the channel. */ -typedef enum { - DRX_CONSTELLATION_BPSK = 0, /**< Modulation is BPSK. */ - DRX_CONSTELLATION_QPSK, /**< Constellation is QPSK. */ - DRX_CONSTELLATION_PSK8, /**< Constellation is PSK8. */ - DRX_CONSTELLATION_QAM16, /**< Constellation is QAM16. */ - DRX_CONSTELLATION_QAM32, /**< Constellation is QAM32. */ - DRX_CONSTELLATION_QAM64, /**< Constellation is QAM64. */ - DRX_CONSTELLATION_QAM128, /**< Constellation is QAM128. */ - DRX_CONSTELLATION_QAM256, /**< Constellation is QAM256. */ - DRX_CONSTELLATION_QAM512, /**< Constellation is QAM512. */ - DRX_CONSTELLATION_QAM1024, /**< Constellation is QAM1024. */ - DRX_CONSTELLATION_QPSK_NR, /**< Constellation is QPSK_NR */ - DRX_CONSTELLATION_UNKNOWN = DRX_UNKNOWN, /**< Constellation unknown. */ - DRX_CONSTELLATION_AUTO = DRX_AUTO /**< Autodetect constellation. */ -} DRXConstellation_t, *pDRXConstellation_t; + typedef enum { + DRX_CONSTELLATION_BPSK = 0, /**< Modulation is BPSK. */ + DRX_CONSTELLATION_QPSK, /**< Constellation is QPSK. */ + DRX_CONSTELLATION_PSK8, /**< Constellation is PSK8. */ + DRX_CONSTELLATION_QAM16, /**< Constellation is QAM16. */ + DRX_CONSTELLATION_QAM32, /**< Constellation is QAM32. */ + DRX_CONSTELLATION_QAM64, /**< Constellation is QAM64. */ + DRX_CONSTELLATION_QAM128, /**< Constellation is QAM128. */ + DRX_CONSTELLATION_QAM256, /**< Constellation is QAM256. */ + DRX_CONSTELLATION_QAM512, /**< Constellation is QAM512. */ + DRX_CONSTELLATION_QAM1024, /**< Constellation is QAM1024. */ + DRX_CONSTELLATION_QPSK_NR, /**< Constellation is QPSK_NR */ + DRX_CONSTELLATION_UNKNOWN = DRX_UNKNOWN, + /**< Constellation unknown. */ + DRX_CONSTELLATION_AUTO = DRX_AUTO + /**< Autodetect constellation. */ + } DRXConstellation_t, *pDRXConstellation_t; /** * \enum DRXHierarchy_t * \brief Hierarchy of the channel. */ -typedef enum { - DRX_HIERARCHY_NONE = 0, /**< None hierarchical channel. */ - DRX_HIERARCHY_ALPHA1, /**< Hierarchical channel, alpha=1. */ - DRX_HIERARCHY_ALPHA2, /**< Hierarchical channel, alpha=2. */ - DRX_HIERARCHY_ALPHA4, /**< Hierarchical channel, alpha=4. */ - DRX_HIERARCHY_UNKNOWN = DRX_UNKNOWN, /**< Hierarchy unknown. */ - DRX_HIERARCHY_AUTO = DRX_AUTO /**< Autodetect hierarchy. */ -} DRXHierarchy_t, *pDRXHierarchy_t; + typedef enum { + DRX_HIERARCHY_NONE = 0, /**< None hierarchical channel. */ + DRX_HIERARCHY_ALPHA1, /**< Hierarchical channel, alpha=1. */ + DRX_HIERARCHY_ALPHA2, /**< Hierarchical channel, alpha=2. */ + DRX_HIERARCHY_ALPHA4, /**< Hierarchical channel, alpha=4. */ + DRX_HIERARCHY_UNKNOWN = DRX_UNKNOWN, + /**< Hierarchy unknown. */ + DRX_HIERARCHY_AUTO = DRX_AUTO + /**< Autodetect hierarchy. */ + } DRXHierarchy_t, *pDRXHierarchy_t; /** * \enum DRXPriority_t * \brief Channel priority in case of hierarchical transmission. */ -typedef enum { - DRX_PRIORITY_LOW = 0, /**< Low priority channel. */ - DRX_PRIORITY_HIGH, /**< High priority channel. */ - DRX_PRIORITY_UNKNOWN = DRX_UNKNOWN /**< Priority unknown. */ -} DRXPriority_t, *pDRXPriority_t; + typedef enum { + DRX_PRIORITY_LOW = 0, /**< Low priority channel. */ + DRX_PRIORITY_HIGH, /**< High priority channel. */ + DRX_PRIORITY_UNKNOWN = DRX_UNKNOWN + /**< Priority unknown. */ + } DRXPriority_t, *pDRXPriority_t; /** * \enum DRXCoderate_t * \brief Channel priority in case of hierarchical transmission. */ -typedef enum { - DRX_CODERATE_1DIV2 = 0, /**< Code rate 1/2nd. */ - DRX_CODERATE_2DIV3, /**< Code rate 2/3nd. */ - DRX_CODERATE_3DIV4, /**< Code rate 3/4nd. */ - DRX_CODERATE_5DIV6, /**< Code rate 5/6nd. */ - DRX_CODERATE_7DIV8, /**< Code rate 7/8nd. */ - DRX_CODERATE_UNKNOWN = DRX_UNKNOWN, /**< Code rate unknown. */ - DRX_CODERATE_AUTO = DRX_AUTO /**< Autodetect code rate. */ -} DRXCoderate_t, *pDRXCoderate_t; + typedef enum { + DRX_CODERATE_1DIV2 = 0, /**< Code rate 1/2nd. */ + DRX_CODERATE_2DIV3, /**< Code rate 2/3nd. */ + DRX_CODERATE_3DIV4, /**< Code rate 3/4nd. */ + DRX_CODERATE_5DIV6, /**< Code rate 5/6nd. */ + DRX_CODERATE_7DIV8, /**< Code rate 7/8nd. */ + DRX_CODERATE_UNKNOWN = DRX_UNKNOWN, + /**< Code rate unknown. */ + DRX_CODERATE_AUTO = DRX_AUTO + /**< Autodetect code rate. */ + } DRXCoderate_t, *pDRXCoderate_t; /** * \enum DRXGuard_t * \brief Guard interval of a channel. */ -typedef enum { - DRX_GUARD_1DIV32 = 0, /**< Guard interval 1/32nd. */ - DRX_GUARD_1DIV16, /**< Guard interval 1/16th. */ - DRX_GUARD_1DIV8, /**< Guard interval 1/8th. */ - DRX_GUARD_1DIV4, /**< Guard interval 1/4th. */ - DRX_GUARD_UNKNOWN = DRX_UNKNOWN, /**< Guard interval unknown. */ - DRX_GUARD_AUTO = DRX_AUTO /**< Autodetect guard interval. */ -} DRXGuard_t, *pDRXGuard_t; + typedef enum { + DRX_GUARD_1DIV32 = 0, /**< Guard interval 1/32nd. */ + DRX_GUARD_1DIV16, /**< Guard interval 1/16th. */ + DRX_GUARD_1DIV8, /**< Guard interval 1/8th. */ + DRX_GUARD_1DIV4, /**< Guard interval 1/4th. */ + DRX_GUARD_UNKNOWN = DRX_UNKNOWN, + /**< Guard interval unknown. */ + DRX_GUARD_AUTO = DRX_AUTO + /**< Autodetect guard interval. */ + } DRXGuard_t, *pDRXGuard_t; /** * \enum DRXFftmode_t * \brief FFT mode. */ -typedef enum { - DRX_FFTMODE_2K = 0, /**< 2K FFT mode. */ - DRX_FFTMODE_4K, /**< 4K FFT mode. */ - DRX_FFTMODE_8K, /**< 8K FFT mode. */ - DRX_FFTMODE_UNKNOWN = DRX_UNKNOWN, /**< FFT mode unknown. */ - DRX_FFTMODE_AUTO = DRX_AUTO /**< Autodetect FFT mode. */ -} DRXFftmode_t, *pDRXFftmode_t; + typedef enum { + DRX_FFTMODE_2K = 0, /**< 2K FFT mode. */ + DRX_FFTMODE_4K, /**< 4K FFT mode. */ + DRX_FFTMODE_8K, /**< 8K FFT mode. */ + DRX_FFTMODE_UNKNOWN = DRX_UNKNOWN, + /**< FFT mode unknown. */ + DRX_FFTMODE_AUTO = DRX_AUTO + /**< Autodetect FFT mode. */ + } DRXFftmode_t, *pDRXFftmode_t; /** * \enum DRXClassification_t * \brief Channel classification. */ -typedef enum { - DRX_CLASSIFICATION_GAUSS = 0, /**< Gaussion noise. */ - DRX_CLASSIFICATION_HVY_GAUSS, /**< Heavy Gaussion noise. */ - DRX_CLASSIFICATION_COCHANNEL, /**< Co-channel. */ - DRX_CLASSIFICATION_STATIC, /**< Static echo. */ - DRX_CLASSIFICATION_MOVING, /**< Moving echo. */ - DRX_CLASSIFICATION_ZERODB, /**< Zero dB echo. */ - DRX_CLASSIFICATION_UNKNOWN = DRX_UNKNOWN, /**< Unknown classification */ - DRX_CLASSIFICATION_AUTO = DRX_AUTO /**< Autodetect classification. */ -} DRXClassification_t, *pDRXClassification_t; + typedef enum { + DRX_CLASSIFICATION_GAUSS = 0, /**< Gaussion noise. */ + DRX_CLASSIFICATION_HVY_GAUSS, /**< Heavy Gaussion noise. */ + DRX_CLASSIFICATION_COCHANNEL, /**< Co-channel. */ + DRX_CLASSIFICATION_STATIC, /**< Static echo. */ + DRX_CLASSIFICATION_MOVING, /**< Moving echo. */ + DRX_CLASSIFICATION_ZERODB, /**< Zero dB echo. */ + DRX_CLASSIFICATION_UNKNOWN = DRX_UNKNOWN, + /**< Unknown classification */ + DRX_CLASSIFICATION_AUTO = DRX_AUTO + /**< Autodetect classification. */ + } DRXClassification_t, *pDRXClassification_t; /** * /enum DRXInterleaveModes_t * /brief Interleave modes */ -typedef enum { - DRX_INTERLEAVEMODE_I128_J1 = 0, - DRX_INTERLEAVEMODE_I128_J1_V2, - DRX_INTERLEAVEMODE_I128_J2, - DRX_INTERLEAVEMODE_I64_J2, - DRX_INTERLEAVEMODE_I128_J3, - DRX_INTERLEAVEMODE_I32_J4, - DRX_INTERLEAVEMODE_I128_J4, - DRX_INTERLEAVEMODE_I16_J8, - DRX_INTERLEAVEMODE_I128_J5, - DRX_INTERLEAVEMODE_I8_J16, - DRX_INTERLEAVEMODE_I128_J6, - DRX_INTERLEAVEMODE_RESERVED_11, - DRX_INTERLEAVEMODE_I128_J7, - DRX_INTERLEAVEMODE_RESERVED_13, - DRX_INTERLEAVEMODE_I128_J8, - DRX_INTERLEAVEMODE_RESERVED_15, - DRX_INTERLEAVEMODE_I12_J17, - DRX_INTERLEAVEMODE_I5_J4, - DRX_INTERLEAVEMODE_B52_M240, - DRX_INTERLEAVEMODE_B52_M720, - DRX_INTERLEAVEMODE_B52_M48, - DRX_INTERLEAVEMODE_B52_M0, - DRX_INTERLEAVEMODE_UNKNOWN = DRX_UNKNOWN, /**< Unknown interleave mode */ - DRX_INTERLEAVEMODE_AUTO = DRX_AUTO /**< Autodetect interleave mode */ -} DRXInterleaveModes_t, *pDRXInterleaveModes_t; + typedef enum { + DRX_INTERLEAVEMODE_I128_J1 = 0, + DRX_INTERLEAVEMODE_I128_J1_V2, + DRX_INTERLEAVEMODE_I128_J2, + DRX_INTERLEAVEMODE_I64_J2, + DRX_INTERLEAVEMODE_I128_J3, + DRX_INTERLEAVEMODE_I32_J4, + DRX_INTERLEAVEMODE_I128_J4, + DRX_INTERLEAVEMODE_I16_J8, + DRX_INTERLEAVEMODE_I128_J5, + DRX_INTERLEAVEMODE_I8_J16, + DRX_INTERLEAVEMODE_I128_J6, + DRX_INTERLEAVEMODE_RESERVED_11, + DRX_INTERLEAVEMODE_I128_J7, + DRX_INTERLEAVEMODE_RESERVED_13, + DRX_INTERLEAVEMODE_I128_J8, + DRX_INTERLEAVEMODE_RESERVED_15, + DRX_INTERLEAVEMODE_I12_J17, + DRX_INTERLEAVEMODE_I5_J4, + DRX_INTERLEAVEMODE_B52_M240, + DRX_INTERLEAVEMODE_B52_M720, + DRX_INTERLEAVEMODE_B52_M48, + DRX_INTERLEAVEMODE_B52_M0, + DRX_INTERLEAVEMODE_UNKNOWN = DRX_UNKNOWN, + /**< Unknown interleave mode */ + DRX_INTERLEAVEMODE_AUTO = DRX_AUTO + /**< Autodetect interleave mode */ + } DRXInterleaveModes_t, *pDRXInterleaveModes_t; /** * \enum DRXCarrier_t * \brief Channel Carrier Mode. */ -typedef enum { - DRX_CARRIER_MULTI = 0, /**< Multi carrier mode */ - DRX_CARRIER_SINGLE, /**< Single carrier mode */ - DRX_CARRIER_UNKNOWN = DRX_UNKNOWN, /**< Carrier mode unknown. */ - DRX_CARRIER_AUTO = DRX_AUTO /**< Autodetect carrier mode */ -} DRXCarrier_t, *pDRXCarrier_t; + typedef enum { + DRX_CARRIER_MULTI = 0, /**< Multi carrier mode */ + DRX_CARRIER_SINGLE, /**< Single carrier mode */ + DRX_CARRIER_UNKNOWN = DRX_UNKNOWN, + /**< Carrier mode unknown. */ + DRX_CARRIER_AUTO = DRX_AUTO /**< Autodetect carrier mode */ + } DRXCarrier_t, *pDRXCarrier_t; /** * \enum DRXFramemode_t * \brief Channel Frame Mode. */ -typedef enum { - DRX_FRAMEMODE_420 = 0, /**< 420 with variable PN */ - DRX_FRAMEMODE_595, /**< 595 */ - DRX_FRAMEMODE_945, /**< 945 with variable PN */ - DRX_FRAMEMODE_420_FIXED_PN, /**< 420 with fixed PN */ - DRX_FRAMEMODE_945_FIXED_PN, /**< 945 with fixed PN */ - DRX_FRAMEMODE_UNKNOWN = DRX_UNKNOWN, /**< Frame mode unknown. */ - DRX_FRAMEMODE_AUTO = DRX_AUTO /**< Autodetect frame mode */ -} DRXFramemode_t, *pDRXFramemode_t; + typedef enum { + DRX_FRAMEMODE_420 = 0, /**< 420 with variable PN */ + DRX_FRAMEMODE_595, /**< 595 */ + DRX_FRAMEMODE_945, /**< 945 with variable PN */ + DRX_FRAMEMODE_420_FIXED_PN, + /**< 420 with fixed PN */ + DRX_FRAMEMODE_945_FIXED_PN, + /**< 945 with fixed PN */ + DRX_FRAMEMODE_UNKNOWN = DRX_UNKNOWN, + /**< Frame mode unknown. */ + DRX_FRAMEMODE_AUTO = DRX_AUTO + /**< Autodetect frame mode */ + } DRXFramemode_t, *pDRXFramemode_t; /** * \enum DRXTPSFrame_t * \brief Frame number in current super-frame. */ -typedef enum { - DRX_TPS_FRAME1 = 0, /**< TPS frame 1. */ - DRX_TPS_FRAME2, /**< TPS frame 2. */ - DRX_TPS_FRAME3, /**< TPS frame 3. */ - DRX_TPS_FRAME4, /**< TPS frame 4. */ - DRX_TPS_FRAME_UNKNOWN = DRX_UNKNOWN /**< TPS frame unknown. */ -} DRXTPSFrame_t, *pDRXTPSFrame_t; + typedef enum { + DRX_TPS_FRAME1 = 0, /**< TPS frame 1. */ + DRX_TPS_FRAME2, /**< TPS frame 2. */ + DRX_TPS_FRAME3, /**< TPS frame 3. */ + DRX_TPS_FRAME4, /**< TPS frame 4. */ + DRX_TPS_FRAME_UNKNOWN = DRX_UNKNOWN + /**< TPS frame unknown. */ + } DRXTPSFrame_t, *pDRXTPSFrame_t; /** * \enum DRXLDPC_t * \brief TPS LDPC . */ -typedef enum { - DRX_LDPC_0_4 = 0, /**< LDPC 0.4 */ - DRX_LDPC_0_6, /**< LDPC 0.6 */ - DRX_LDPC_0_8, /**< LDPC 0.8 */ - DRX_LDPC_UNKNOWN = DRX_UNKNOWN, /**< LDPC unknown. */ - DRX_LDPC_AUTO = DRX_AUTO /**< Autodetect LDPC */ -} DRXLDPC_t, *pDRXLDPC_t; + typedef enum { + DRX_LDPC_0_4 = 0, /**< LDPC 0.4 */ + DRX_LDPC_0_6, /**< LDPC 0.6 */ + DRX_LDPC_0_8, /**< LDPC 0.8 */ + DRX_LDPC_UNKNOWN = DRX_UNKNOWN, + /**< LDPC unknown. */ + DRX_LDPC_AUTO = DRX_AUTO /**< Autodetect LDPC */ + } DRXLDPC_t, *pDRXLDPC_t; /** * \enum DRXPilotMode_t * \brief Pilot modes in DTMB. */ -typedef enum { - DRX_PILOT_ON = 0, /**< Pilot On */ - DRX_PILOT_OFF, /**< Pilot Off */ - DRX_PILOT_UNKNOWN = DRX_UNKNOWN, /**< Pilot unknown. */ - DRX_PILOT_AUTO = DRX_AUTO /**< Autodetect Pilot */ -} DRXPilotMode_t, *pDRXPilotMode_t; - - + typedef enum { + DRX_PILOT_ON = 0, /**< Pilot On */ + DRX_PILOT_OFF, /**< Pilot Off */ + DRX_PILOT_UNKNOWN = DRX_UNKNOWN, + /**< Pilot unknown. */ + DRX_PILOT_AUTO = DRX_AUTO /**< Autodetect Pilot */ + } DRXPilotMode_t, *pDRXPilotMode_t; /** * \enum DRXCtrlIndex_t * \brief Indices of the control functions. */ -typedef u32_t DRXCtrlIndex_t, *pDRXCtrlIndex_t; + typedef u32_t DRXCtrlIndex_t, *pDRXCtrlIndex_t; #ifndef DRX_CTRL_BASE #define DRX_CTRL_BASE ((DRXCtrlIndex_t)0) @@ -583,14 +616,14 @@ typedef u32_t DRXCtrlIndex_t, *pDRXCtrlIndex_t; #define DRX_CTRL_I2C_READWRITE ( DRX_CTRL_BASE + 27)/**< Read/write I2C */ #define DRX_CTRL_PROGRAM_TUNER ( DRX_CTRL_BASE + 28)/**< Program tuner */ - /* Professional */ + /* Professional */ #define DRX_CTRL_MB_CFG ( DRX_CTRL_BASE + 29) /**< */ #define DRX_CTRL_MB_READ ( DRX_CTRL_BASE + 30) /**< */ #define DRX_CTRL_MB_WRITE ( DRX_CTRL_BASE + 31) /**< */ #define DRX_CTRL_MB_CONSTEL ( DRX_CTRL_BASE + 32) /**< */ #define DRX_CTRL_MB_MER ( DRX_CTRL_BASE + 33) /**< */ - /* Misc */ + /* Misc */ #define DRX_CTRL_UIO_CFG DRX_CTRL_SET_UIO_CFG /**< Configure UIO */ #define DRX_CTRL_SET_UIO_CFG ( DRX_CTRL_BASE + 34) /**< Configure UIO */ #define DRX_CTRL_GET_UIO_CFG ( DRX_CTRL_BASE + 35) /**< Configure UIO */ @@ -603,18 +636,19 @@ typedef u32_t DRXCtrlIndex_t, *pDRXCtrlIndex_t; #define DRX_CTRL_VALIDATE_UCODE ( DRX_CTRL_BASE + 42) /**< Validate ucode */ #define DRX_CTRL_DUMP_REGISTERS ( DRX_CTRL_BASE + 43) /**< Dump registers */ -#define DRX_CTRL_MAX ( DRX_CTRL_BASE + 44) /* never to be used */ +#define DRX_CTRL_MAX ( DRX_CTRL_BASE + 44) /* never to be used */ /** * \enum DRXUCodeAction_t * \brief Used to indicate if firmware has to be uploaded or verified. */ -typedef enum { - UCODE_UPLOAD, /**< Upload the microcode image to device */ - UCODE_VERIFY /**< Compare microcode image with code on device */ -} DRXUCodeAction_t, *pDRXUCodeAction_t; - + typedef enum { + UCODE_UPLOAD, + /**< Upload the microcode image to device */ + UCODE_VERIFY + /**< Compare microcode image with code on device */ + } DRXUCodeAction_t, *pDRXUCodeAction_t; /** * \enum DRXLockStatus_t @@ -622,60 +656,71 @@ typedef enum { * * The generic lock states have device dependent semantics. */ -typedef enum{ - DRX_NEVER_LOCK = 0, /**< Device will never lock on this signal */ - DRX_NOT_LOCKED, /**< Device has no lock at all */ - DRX_LOCK_STATE_1, /**< Generic lock state */ - DRX_LOCK_STATE_2, /**< Generic lock state */ - DRX_LOCK_STATE_3, /**< Generic lock state */ - DRX_LOCK_STATE_4, /**< Generic lock state */ - DRX_LOCK_STATE_5, /**< Generic lock state */ - DRX_LOCK_STATE_6, /**< Generic lock state */ - DRX_LOCK_STATE_7, /**< Generic lock state */ - DRX_LOCK_STATE_8, /**< Generic lock state */ - DRX_LOCK_STATE_9, /**< Generic lock state */ - DRX_LOCKED /**< Device is in lock */ -} DRXLockStatus_t, *pDRXLockStatus_t; + typedef enum { + DRX_NEVER_LOCK = 0, + /**< Device will never lock on this signal */ + DRX_NOT_LOCKED, + /**< Device has no lock at all */ + DRX_LOCK_STATE_1, + /**< Generic lock state */ + DRX_LOCK_STATE_2, + /**< Generic lock state */ + DRX_LOCK_STATE_3, + /**< Generic lock state */ + DRX_LOCK_STATE_4, + /**< Generic lock state */ + DRX_LOCK_STATE_5, + /**< Generic lock state */ + DRX_LOCK_STATE_6, + /**< Generic lock state */ + DRX_LOCK_STATE_7, + /**< Generic lock state */ + DRX_LOCK_STATE_8, + /**< Generic lock state */ + DRX_LOCK_STATE_9, + /**< Generic lock state */ + DRX_LOCKED /**< Device is in lock */ + } DRXLockStatus_t, *pDRXLockStatus_t; /** * \enum DRXUIO_t * \brief Used to address a User IO (UIO). */ -typedef enum{ - DRX_UIO1 , - DRX_UIO2 , - DRX_UIO3 , - DRX_UIO4 , - DRX_UIO5 , - DRX_UIO6 , - DRX_UIO7 , - DRX_UIO8 , - DRX_UIO9 , - DRX_UIO10 , - DRX_UIO11 , - DRX_UIO12 , - DRX_UIO13 , - DRX_UIO14 , - DRX_UIO15 , - DRX_UIO16 , - DRX_UIO17 , - DRX_UIO18 , - DRX_UIO19 , - DRX_UIO20 , - DRX_UIO21 , - DRX_UIO22 , - DRX_UIO23 , - DRX_UIO24 , - DRX_UIO25 , - DRX_UIO26 , - DRX_UIO27 , - DRX_UIO28 , - DRX_UIO29 , - DRX_UIO30 , - DRX_UIO31 , - DRX_UIO32 , - DRX_UIO_MAX = DRX_UIO32 -} DRXUIO_t, *pDRXUIO_t; + typedef enum { + DRX_UIO1, + DRX_UIO2, + DRX_UIO3, + DRX_UIO4, + DRX_UIO5, + DRX_UIO6, + DRX_UIO7, + DRX_UIO8, + DRX_UIO9, + DRX_UIO10, + DRX_UIO11, + DRX_UIO12, + DRX_UIO13, + DRX_UIO14, + DRX_UIO15, + DRX_UIO16, + DRX_UIO17, + DRX_UIO18, + DRX_UIO19, + DRX_UIO20, + DRX_UIO21, + DRX_UIO22, + DRX_UIO23, + DRX_UIO24, + DRX_UIO25, + DRX_UIO26, + DRX_UIO27, + DRX_UIO28, + DRX_UIO29, + DRX_UIO30, + DRX_UIO31, + DRX_UIO32, + DRX_UIO_MAX = DRX_UIO32 + } DRXUIO_t, *pDRXUIO_t; /** * \enum DRXUIOMode_t @@ -686,17 +731,26 @@ typedef enum{ * To be backward compatible DRX_UIO_MODE_FIRMWARE is equivalent to * DRX_UIO_MODE_FIRMWARE0. */ -typedef enum{ - DRX_UIO_MODE_DISABLE = 0x01, /**< not used, pin is configured as input */ - DRX_UIO_MODE_READWRITE = 0x02, /**< used for read/write by application */ - DRX_UIO_MODE_FIRMWARE = 0x04, /**< controlled by firmware, function 0 */ - DRX_UIO_MODE_FIRMWARE0 = DRX_UIO_MODE_FIRMWARE , /**< same as above */ - DRX_UIO_MODE_FIRMWARE1 = 0x08, /**< controlled by firmware, function 1 */ - DRX_UIO_MODE_FIRMWARE2 = 0x10, /**< controlled by firmware, function 2 */ - DRX_UIO_MODE_FIRMWARE3 = 0x20, /**< controlled by firmware, function 3 */ - DRX_UIO_MODE_FIRMWARE4 = 0x40, /**< controlled by firmware, function 4 */ - DRX_UIO_MODE_FIRMWARE5 = 0x80 /**< controlled by firmware, function 5 */ -} DRXUIOMode_t, *pDRXUIOMode_t; + typedef enum { + DRX_UIO_MODE_DISABLE = 0x01, + /**< not used, pin is configured as input */ + DRX_UIO_MODE_READWRITE = 0x02, + /**< used for read/write by application */ + DRX_UIO_MODE_FIRMWARE = 0x04, + /**< controlled by firmware, function 0 */ + DRX_UIO_MODE_FIRMWARE0 = DRX_UIO_MODE_FIRMWARE, + /**< same as above */ + DRX_UIO_MODE_FIRMWARE1 = 0x08, + /**< controlled by firmware, function 1 */ + DRX_UIO_MODE_FIRMWARE2 = 0x10, + /**< controlled by firmware, function 2 */ + DRX_UIO_MODE_FIRMWARE3 = 0x20, + /**< controlled by firmware, function 3 */ + DRX_UIO_MODE_FIRMWARE4 = 0x40, + /**< controlled by firmware, function 4 */ + DRX_UIO_MODE_FIRMWARE5 = 0x80 + /**< controlled by firmware, function 5 */ + } DRXUIOMode_t, *pDRXUIOMode_t; /** * \enum DRXOOBDownstreamStandard_t @@ -704,12 +758,14 @@ typedef enum{ * * Based on ANSI 55-1 and 55-2 */ -typedef enum { - DRX_OOB_MODE_A = 0, /**< ANSI 55-1 */ - DRX_OOB_MODE_B_GRADE_A, /**< ANSI 55-2 A */ - DRX_OOB_MODE_B_GRADE_B /**< ANSI 55-2 B */ -} DRXOOBDownstreamStandard_t, *pDRXOOBDownstreamStandard_t; - + typedef enum { + DRX_OOB_MODE_A = 0, + /**< ANSI 55-1 */ + DRX_OOB_MODE_B_GRADE_A, + /**< ANSI 55-2 A */ + DRX_OOB_MODE_B_GRADE_B + /**< ANSI 55-2 B */ + } DRXOOBDownstreamStandard_t, *pDRXOOBDownstreamStandard_t; /*------------------------------------------------------------------------- STRUCTS @@ -725,31 +781,31 @@ STRUCTS * \enum DRXCfgType_t * \brief Generic configuration function identifiers. */ -typedef u32_t DRXCfgType_t, *pDRXCfgType_t; + typedef u32_t DRXCfgType_t, *pDRXCfgType_t; #ifndef DRX_CFG_BASE #define DRX_CFG_BASE ((DRXCfgType_t)0) #endif -#define DRX_CFG_MPEG_OUTPUT ( DRX_CFG_BASE + 0) /* MPEG TS output */ -#define DRX_CFG_PKTERR ( DRX_CFG_BASE + 1) /* Packet Error */ -#define DRX_CFG_SYMCLK_OFFS ( DRX_CFG_BASE + 2) /* Symbol Clk Offset */ -#define DRX_CFG_SMA ( DRX_CFG_BASE + 3) /* Smart Antenna */ -#define DRX_CFG_PINSAFE ( DRX_CFG_BASE + 4) /* Pin safe mode */ -#define DRX_CFG_SUBSTANDARD ( DRX_CFG_BASE + 5) /* substandard */ -#define DRX_CFG_AUD_VOLUME ( DRX_CFG_BASE + 6) /* volume */ -#define DRX_CFG_AUD_RDS ( DRX_CFG_BASE + 7) /* rds */ -#define DRX_CFG_AUD_AUTOSOUND ( DRX_CFG_BASE + 8) /* ASS & ASC */ -#define DRX_CFG_AUD_ASS_THRES ( DRX_CFG_BASE + 9) /* ASS Thresholds */ -#define DRX_CFG_AUD_DEVIATION ( DRX_CFG_BASE + 10) /* Deviation */ -#define DRX_CFG_AUD_PRESCALE ( DRX_CFG_BASE + 11) /* Prescale */ -#define DRX_CFG_AUD_MIXER ( DRX_CFG_BASE + 12) /* Mixer */ -#define DRX_CFG_AUD_AVSYNC ( DRX_CFG_BASE + 13) /* AVSync */ -#define DRX_CFG_AUD_CARRIER ( DRX_CFG_BASE + 14) /* Audio carriers */ -#define DRX_CFG_I2S_OUTPUT ( DRX_CFG_BASE + 15) /* I2S output */ -#define DRX_CFG_ATV_STANDARD ( DRX_CFG_BASE + 16) /* ATV standard */ -#define DRX_CFG_SQI_SPEED ( DRX_CFG_BASE + 17) /* SQI speed */ -#define DRX_CTRL_CFG_MAX ( DRX_CFG_BASE + 18) /* never to be used */ +#define DRX_CFG_MPEG_OUTPUT ( DRX_CFG_BASE + 0) /* MPEG TS output */ +#define DRX_CFG_PKTERR ( DRX_CFG_BASE + 1) /* Packet Error */ +#define DRX_CFG_SYMCLK_OFFS ( DRX_CFG_BASE + 2) /* Symbol Clk Offset */ +#define DRX_CFG_SMA ( DRX_CFG_BASE + 3) /* Smart Antenna */ +#define DRX_CFG_PINSAFE ( DRX_CFG_BASE + 4) /* Pin safe mode */ +#define DRX_CFG_SUBSTANDARD ( DRX_CFG_BASE + 5) /* substandard */ +#define DRX_CFG_AUD_VOLUME ( DRX_CFG_BASE + 6) /* volume */ +#define DRX_CFG_AUD_RDS ( DRX_CFG_BASE + 7) /* rds */ +#define DRX_CFG_AUD_AUTOSOUND ( DRX_CFG_BASE + 8) /* ASS & ASC */ +#define DRX_CFG_AUD_ASS_THRES ( DRX_CFG_BASE + 9) /* ASS Thresholds */ +#define DRX_CFG_AUD_DEVIATION ( DRX_CFG_BASE + 10) /* Deviation */ +#define DRX_CFG_AUD_PRESCALE ( DRX_CFG_BASE + 11) /* Prescale */ +#define DRX_CFG_AUD_MIXER ( DRX_CFG_BASE + 12) /* Mixer */ +#define DRX_CFG_AUD_AVSYNC ( DRX_CFG_BASE + 13) /* AVSync */ +#define DRX_CFG_AUD_CARRIER ( DRX_CFG_BASE + 14) /* Audio carriers */ +#define DRX_CFG_I2S_OUTPUT ( DRX_CFG_BASE + 15) /* I2S output */ +#define DRX_CFG_ATV_STANDARD ( DRX_CFG_BASE + 16) /* ATV standard */ +#define DRX_CFG_SQI_SPEED ( DRX_CFG_BASE + 17) /* SQI speed */ +#define DRX_CTRL_CFG_MAX ( DRX_CFG_BASE + 18) /* never to be used */ #define DRX_CFG_PINS_SAFE_MODE DRX_CFG_PINSAFE /*============================================================================*/ @@ -764,10 +820,12 @@ typedef u32_t DRXCfgType_t, *pDRXCfgType_t; * * Used by DRX_CTRL_LOAD_UCODE and DRX_CTRL_VERIFY_UCODE */ -typedef struct { - pu8_t mcData; /**< Pointer to microcode image. */ - u16_t mcSize; /**< Microcode image size. */ -} DRXUCodeInfo_t, *pDRXUCodeInfo_t; + typedef struct { + pu8_t mcData; + /**< Pointer to microcode image. */ + u16_t mcSize; + /**< Microcode image size. */ + } DRXUCodeInfo_t, *pDRXUCodeInfo_t; /** * \struct DRXMcVersionRec_t @@ -788,12 +846,12 @@ typedef struct { */ #define AUX_VER_RECORD 0x8000 -typedef struct { - u16_t auxType; /* type of aux data - 0x8000 for version record */ - u32_t mcDevType; /* device type, based on JTAG ID */ - u32_t mcVersion; /* version of microcode */ - u32_t mcBaseVersion; /* in case of patch: the original microcode version */ -} DRXMcVersionRec_t, *pDRXMcVersionRec_t; + typedef struct { + u16_t auxType; /* type of aux data - 0x8000 for version record */ + u32_t mcDevType; /* device type, based on JTAG ID */ + u32_t mcVersion; /* version of microcode */ + u32_t mcBaseVersion; /* in case of patch: the original microcode version */ + } DRXMcVersionRec_t, *pDRXMcVersionRec_t; /*========================================*/ @@ -803,14 +861,16 @@ typedef struct { * * Used by DRX_CTRL_LOAD_FILTER */ -typedef struct { - pu8_t dataRe; /**< pointer to coefficients for RE */ - pu8_t dataIm; /**< pointer to coefficients for IM */ - u16_t sizeRe; /**< size of coefficients for RE */ - u16_t sizeIm; /**< size of coefficients for IM */ -} DRXFilterInfo_t, *pDRXFilterInfo_t; - - + typedef struct { + pu8_t dataRe; + /**< pointer to coefficients for RE */ + pu8_t dataIm; + /**< pointer to coefficients for IM */ + u16_t sizeRe; + /**< size of coefficients for RE */ + u16_t sizeIm; + /**< size of coefficients for IM */ + } DRXFilterInfo_t, *pDRXFilterInfo_t; /*========================================*/ @@ -822,24 +882,32 @@ typedef struct { * Only certain fields need to be used for a specfic standard. * */ -typedef struct { - DRXFrequency_t frequency; /**< frequency in kHz */ - DRXBandwidth_t bandwidth; /**< bandwidth */ - DRXMirror_t mirror; /**< mirrored or not on RF */ - DRXConstellation_t constellation; /**< constellation */ - DRXHierarchy_t hierarchy; /**< hierarchy */ - DRXPriority_t priority; /**< priority */ - DRXCoderate_t coderate; /**< coderate */ - DRXGuard_t guard; /**< guard interval */ - DRXFftmode_t fftmode; /**< fftmode */ - DRXClassification_t classification; /**< classification */ - DRXSymbolrate_t symbolrate; /**< symbolrate in symbols/sec */ - DRXInterleaveModes_t interleavemode; /**< interleaveMode QAM */ - DRXLDPC_t ldpc; /**< ldpc */ - DRXCarrier_t carrier; /**< carrier */ - DRXFramemode_t framemode; /**< frame mode */ - DRXPilotMode_t pilot; /**< pilot mode */ -} DRXChannel_t, *pDRXChannel_t; + typedef struct { + DRXFrequency_t frequency; + /**< frequency in kHz */ + DRXBandwidth_t bandwidth; + /**< bandwidth */ + DRXMirror_t mirror; /**< mirrored or not on RF */ + DRXConstellation_t constellation; + /**< constellation */ + DRXHierarchy_t hierarchy; + /**< hierarchy */ + DRXPriority_t priority; /**< priority */ + DRXCoderate_t coderate; /**< coderate */ + DRXGuard_t guard; /**< guard interval */ + DRXFftmode_t fftmode; /**< fftmode */ + DRXClassification_t classification; + /**< classification */ + DRXSymbolrate_t symbolrate; + /**< symbolrate in symbols/sec */ + DRXInterleaveModes_t interleavemode; + /**< interleaveMode QAM */ + DRXLDPC_t ldpc; /**< ldpc */ + DRXCarrier_t carrier; /**< carrier */ + DRXFramemode_t framemode; + /**< frame mode */ + DRXPilotMode_t pilot; /**< pilot mode */ + } DRXChannel_t, *pDRXChannel_t; /*========================================*/ @@ -849,25 +917,31 @@ typedef struct { * * Used by DRX_CTRL_SIG_QUALITY. */ -typedef struct { - u16_t MER; /**< in steps of 0.1 dB */ - u32_t preViterbiBER ; /**< in steps of 1/scaleFactorBER */ - u32_t postViterbiBER ; /**< in steps of 1/scaleFactorBER */ - u32_t scaleFactorBER; /**< scale factor for BER */ - u16_t packetError ; /**< number of packet errors */ - u32_t postReedSolomonBER ; /**< in steps of 1/scaleFactorBER */ - u32_t preLdpcBER; /**< in steps of 1/scaleFactorBER */ - u32_t averIter; /**< in steps of 0.01 */ - u16_t indicator; /**< indicative signal quality low=0..100=high */ -}DRXSigQuality_t, *pDRXSigQuality_t; - - -typedef enum { - DRX_SQI_SPEED_FAST = 0, - DRX_SQI_SPEED_MEDIUM, - DRX_SQI_SPEED_SLOW, - DRX_SQI_SPEED_UNKNOWN = DRX_UNKNOWN -} DRXCfgSqiSpeed_t, *pDRXCfgSqiSpeed_t; + typedef struct { + u16_t MER; /**< in steps of 0.1 dB */ + u32_t preViterbiBER; + /**< in steps of 1/scaleFactorBER */ + u32_t postViterbiBER; + /**< in steps of 1/scaleFactorBER */ + u32_t scaleFactorBER; + /**< scale factor for BER */ + u16_t packetError; + /**< number of packet errors */ + u32_t postReedSolomonBER; + /**< in steps of 1/scaleFactorBER */ + u32_t preLdpcBER; + /**< in steps of 1/scaleFactorBER */ + u32_t averIter;/**< in steps of 0.01 */ + u16_t indicator; + /**< indicative signal quality low=0..100=high */ + } DRXSigQuality_t, *pDRXSigQuality_t; + + typedef enum { + DRX_SQI_SPEED_FAST = 0, + DRX_SQI_SPEED_MEDIUM, + DRX_SQI_SPEED_SLOW, + DRX_SQI_SPEED_UNKNOWN = DRX_UNKNOWN + } DRXCfgSqiSpeed_t, *pDRXCfgSqiSpeed_t; /*========================================*/ @@ -877,11 +951,12 @@ typedef enum { * * Used by DRX_CTRL_CONSTEL. */ -typedef struct { - s16_t im; /**< Imaginary part. */ - s16_t re; /**< Real part. */ -} DRXComplex_t, *pDRXComplex_t; - + typedef struct { + s16_t im; + /**< Imaginary part. */ + s16_t re; + /**< Real part. */ + } DRXComplex_t, *pDRXComplex_t; /*========================================*/ @@ -891,16 +966,22 @@ typedef struct { * * Used by DRX_CTRL_SCAN_INIT. */ -typedef struct { - DRXFrequency_t first; /**< First centre frequency in this band */ - DRXFrequency_t last; /**< Last centre frequency in this band */ - DRXFrequency_t step; /**< Stepping frequency in this band */ - DRXBandwidth_t bandwidth; /**< Bandwidth within this frequency band */ - u16_t chNumber; /**< First channel number in this band, or first + typedef struct { + DRXFrequency_t first; + /**< First centre frequency in this band */ + DRXFrequency_t last; + /**< Last centre frequency in this band */ + DRXFrequency_t step; + /**< Stepping frequency in this band */ + DRXBandwidth_t bandwidth; + /**< Bandwidth within this frequency band */ + u16_t chNumber; + /**< First channel number in this band, or first index in chNames */ - char **chNames; /**< Optional list of channel names in this + char **chNames; + /**< Optional list of channel names in this band */ -} DRXFrequencyPlan_t, *pDRXFrequencyPlan_t; + } DRXFrequencyPlan_t, *pDRXFrequencyPlan_t; /*========================================*/ @@ -910,11 +991,11 @@ typedef struct { * * Used by frequency_plan.h */ -typedef struct{ - pDRXFrequencyPlan_t freqPlan; - int freqPlanSize; - char *freqPlanName; -}DRXFrequencyPlanInfo_t, *pDRXFrequencyPlanInfo_t; + typedef struct { + pDRXFrequencyPlan_t freqPlan; + int freqPlanSize; + char *freqPlanName; + } DRXFrequencyPlanInfo_t, *pDRXFrequencyPlanInfo_t; /*========================================*/ @@ -922,14 +1003,15 @@ typedef struct{ * /struct DRXScanDataQam_t * QAM specific scanning variables */ -typedef struct { - pu32_t symbolrate; /**< list of symbolrates to scan */ - u16_t symbolrateSize; /**< size of symbolrate array */ - pDRXConstellation_t constellation; /**< list of constellations */ - u16_t constellationSize; /**< size of constellation array */ - u16_t ifAgcThreshold; /**< thresholf for IF-AGC based + typedef struct { + pu32_t symbolrate; /**< list of symbolrates to scan */ + u16_t symbolrateSize; /**< size of symbolrate array */ + pDRXConstellation_t constellation; + /**< list of constellations */ + u16_t constellationSize; /**< size of constellation array */ + u16_t ifAgcThreshold; /**< thresholf for IF-AGC based scanning filter */ -} DRXScanDataQam_t, *pDRXScanDataQam_t; + } DRXScanDataQam_t, *pDRXScanDataQam_t; /*========================================*/ @@ -937,9 +1019,10 @@ typedef struct { * /struct DRXScanDataAtv_t * ATV specific scanning variables */ -typedef struct { - s16_t svrThreshold; /**< threshold of Sound/Video ratio in 0.1dB steps */ -} DRXScanDataAtv_t, *pDRXScanDataAtv_t; + typedef struct { + s16_t svrThreshold; + /**< threshold of Sound/Video ratio in 0.1dB steps */ + } DRXScanDataAtv_t, *pDRXScanDataAtv_t; /*========================================*/ @@ -949,14 +1032,15 @@ typedef struct { * * Used by DRX_CTRL_SCAN_INIT. */ -typedef struct { - pDRXFrequencyPlan_t frequencyPlan; /**< Frequency plan (array)*/ - u16_t frequencyPlanSize; /**< Number of bands */ - u32_t numTries; /**< Max channels tried */ - DRXFrequency_t skip; /**< Minimum frequency step to take + typedef struct { + pDRXFrequencyPlan_t frequencyPlan; + /**< Frequency plan (array)*/ + u16_t frequencyPlanSize; /**< Number of bands */ + u32_t numTries; /**< Max channels tried */ + DRXFrequency_t skip; /**< Minimum frequency step to take after a channel is found */ - void *extParams; /**< Standard specific params */ -} DRXScanParam_t, *pDRXScanParam_t; + void *extParams; /**< Standard specific params */ + } DRXScanParam_t, *pDRXScanParam_t; /*========================================*/ @@ -964,21 +1048,21 @@ typedef struct { * \brief Scan commands. * Used by scanning algorithms. */ -typedef enum { - DRX_SCAN_COMMAND_INIT = 0, /**< Initialize scanning */ - DRX_SCAN_COMMAND_NEXT, /**< Next scan */ - DRX_SCAN_COMMAND_STOP /**< Stop scanning */ -}DRXScanCommand_t, *pDRXScanCommand_t; + typedef enum { + DRX_SCAN_COMMAND_INIT = 0,/**< Initialize scanning */ + DRX_SCAN_COMMAND_NEXT, /**< Next scan */ + DRX_SCAN_COMMAND_STOP /**< Stop scanning */ + } DRXScanCommand_t, *pDRXScanCommand_t; /*========================================*/ /** * \brief Inner scan function prototype. */ -typedef DRXStatus_t (*DRXScanFunc_t) (void* scanContext, - DRXScanCommand_t scanCommand, - pDRXChannel_t scanChannel, - pBool_t getNextChannel ); + typedef DRXStatus_t(*DRXScanFunc_t) (void *scanContext, + DRXScanCommand_t scanCommand, + pDRXChannel_t scanChannel, + pBool_t getNextChannel); /*========================================*/ @@ -988,17 +1072,21 @@ typedef DRXStatus_t (*DRXScanFunc_t) (void* scanContext, * * Used by DRX_CTRL_TPS_INFO. */ -typedef struct { - DRXFftmode_t fftmode; /**< Fft mode */ - DRXGuard_t guard; /**< Guard interval */ - DRXConstellation_t constellation; /**< Constellation */ - DRXHierarchy_t hierarchy; /**< Hierarchy */ - DRXCoderate_t highCoderate; /**< High code rate */ - DRXCoderate_t lowCoderate; /**< Low cod rate */ - DRXTPSFrame_t frame; /**< Tps frame */ - u8_t length; /**< Length */ - u16_t cellId; /**< Cell id */ -}DRXTPSInfo_t, *pDRXTPSInfo_t; + typedef struct { + DRXFftmode_t fftmode; /**< Fft mode */ + DRXGuard_t guard; /**< Guard interval */ + DRXConstellation_t constellation; + /**< Constellation */ + DRXHierarchy_t hierarchy; + /**< Hierarchy */ + DRXCoderate_t highCoderate; + /**< High code rate */ + DRXCoderate_t lowCoderate; + /**< Low cod rate */ + DRXTPSFrame_t frame; /**< Tps frame */ + u8_t length; /**< Length */ + u16_t cellId; /**< Cell id */ + } DRXTPSInfo_t, *pDRXTPSInfo_t; /*========================================*/ @@ -1007,27 +1095,45 @@ typedef struct { * * Used by DRX_CTRL_SET_POWER_MODE. */ -typedef enum { - DRX_POWER_UP = 0, /**< Generic , Power Up Mode */ - DRX_POWER_MODE_1, /**< Device specific , Power Up Mode */ - DRX_POWER_MODE_2, /**< Device specific , Power Up Mode */ - DRX_POWER_MODE_3, /**< Device specific , Power Up Mode */ - DRX_POWER_MODE_4, /**< Device specific , Power Up Mode */ - DRX_POWER_MODE_5, /**< Device specific , Power Up Mode */ - DRX_POWER_MODE_6, /**< Device specific , Power Up Mode */ - DRX_POWER_MODE_7, /**< Device specific , Power Up Mode */ - DRX_POWER_MODE_8, /**< Device specific , Power Up Mode */ - - DRX_POWER_MODE_9, /**< Device specific , Power Down Mode */ - DRX_POWER_MODE_10, /**< Device specific , Power Down Mode */ - DRX_POWER_MODE_11, /**< Device specific , Power Down Mode */ - DRX_POWER_MODE_12, /**< Device specific , Power Down Mode */ - DRX_POWER_MODE_13, /**< Device specific , Power Down Mode */ - DRX_POWER_MODE_14, /**< Device specific , Power Down Mode */ - DRX_POWER_MODE_15, /**< Device specific , Power Down Mode */ - DRX_POWER_MODE_16, /**< Device specific , Power Down Mode */ - DRX_POWER_DOWN = 255 /**< Generic , Power Down Mode */ -}DRXPowerMode_t, *pDRXPowerMode_t; + typedef enum { + DRX_POWER_UP = 0, + /**< Generic , Power Up Mode */ + DRX_POWER_MODE_1, + /**< Device specific , Power Up Mode */ + DRX_POWER_MODE_2, + /**< Device specific , Power Up Mode */ + DRX_POWER_MODE_3, + /**< Device specific , Power Up Mode */ + DRX_POWER_MODE_4, + /**< Device specific , Power Up Mode */ + DRX_POWER_MODE_5, + /**< Device specific , Power Up Mode */ + DRX_POWER_MODE_6, + /**< Device specific , Power Up Mode */ + DRX_POWER_MODE_7, + /**< Device specific , Power Up Mode */ + DRX_POWER_MODE_8, + /**< Device specific , Power Up Mode */ + + DRX_POWER_MODE_9, + /**< Device specific , Power Down Mode */ + DRX_POWER_MODE_10, + /**< Device specific , Power Down Mode */ + DRX_POWER_MODE_11, + /**< Device specific , Power Down Mode */ + DRX_POWER_MODE_12, + /**< Device specific , Power Down Mode */ + DRX_POWER_MODE_13, + /**< Device specific , Power Down Mode */ + DRX_POWER_MODE_14, + /**< Device specific , Power Down Mode */ + DRX_POWER_MODE_15, + /**< Device specific , Power Down Mode */ + DRX_POWER_MODE_16, + /**< Device specific , Power Down Mode */ + DRX_POWER_DOWN = 255 + /**< Generic , Power Down Mode */ + } DRXPowerMode_t, *pDRXPowerMode_t; /*========================================*/ @@ -1037,18 +1143,17 @@ typedef enum { * * Used by DRX_CTRL_VERSION. */ -typedef enum { - DRX_MODULE_DEVICE, - DRX_MODULE_MICROCODE, - DRX_MODULE_DRIVERCORE, - DRX_MODULE_DEVICEDRIVER, - DRX_MODULE_DAP, - DRX_MODULE_BSP_I2C, - DRX_MODULE_BSP_TUNER, - DRX_MODULE_BSP_HOST, - DRX_MODULE_UNKNOWN -} DRXModule_t, *pDRXModule_t; - + typedef enum { + DRX_MODULE_DEVICE, + DRX_MODULE_MICROCODE, + DRX_MODULE_DRIVERCORE, + DRX_MODULE_DEVICEDRIVER, + DRX_MODULE_DAP, + DRX_MODULE_BSP_I2C, + DRX_MODULE_BSP_TUNER, + DRX_MODULE_BSP_HOST, + DRX_MODULE_UNKNOWN + } DRXModule_t, *pDRXModule_t; /** * \enum DRXVersion_t @@ -1056,14 +1161,16 @@ typedef enum { * * Used by DRX_CTRL_VERSION. */ -typedef struct { - DRXModule_t moduleType; /**< Type identifier of the module */ - char *moduleName; /**< Name or description of module */ - u16_t vMajor; /**< Major version number */ - u16_t vMinor; /**< Minor version number */ - u16_t vPatch; /**< Patch version number */ - char *vString; /**< Version as text string */ -} DRXVersion_t, *pDRXVersion_t; + typedef struct { + DRXModule_t moduleType; + /**< Type identifier of the module */ + char *moduleName; + /**< Name or description of module */ + u16_t vMajor; /**< Major version number */ + u16_t vMinor; /**< Minor version number */ + u16_t vPatch; /**< Patch version number */ + char *vString; /**< Version as text string */ + } DRXVersion_t, *pDRXVersion_t; /** * \enum DRXVersionList_t @@ -1071,10 +1178,11 @@ typedef struct { * * Used by DRX_CTRL_VERSION. */ -typedef struct DRXVersionList_s { - pDRXVersion_t version; /**< Version information */ - struct DRXVersionList_s *next; /**< Next list element */ -} DRXVersionList_t, *pDRXVersionList_t; + typedef struct DRXVersionList_s { + pDRXVersion_t version;/**< Version information */ + struct DRXVersionList_s *next; + /**< Next list element */ + } DRXVersionList_t, *pDRXVersionList_t; /*========================================*/ @@ -1083,10 +1191,12 @@ typedef struct DRXVersionList_s { * * Used by DRX_CTRL_UIO_CFG. */ -typedef struct { - DRXUIO_t uio; /**< UIO identifier */ - DRXUIOMode_t mode; /**< UIO operational mode */ -} DRXUIOCfg_t, *pDRXUIOCfg_t; + typedef struct { + DRXUIO_t uio; + /**< UIO identifier */ + DRXUIOMode_t mode; + /**< UIO operational mode */ + } DRXUIOCfg_t, *pDRXUIOCfg_t; /*========================================*/ @@ -1095,10 +1205,12 @@ typedef struct { * * Used by DRX_CTRL_UIO_READ and DRX_CTRL_UIO_WRITE. */ -typedef struct { - DRXUIO_t uio; /**< UIO identifier */ - Bool_t value; /**< UIO value (TRUE=1, FALSE=0) */ -} DRXUIOData_t, *pDRXUIOData_t; + typedef struct { + DRXUIO_t uio; + /**< UIO identifier */ + Bool_t value; + /**< UIO value (TRUE=1, FALSE=0) */ + } DRXUIOData_t, *pDRXUIOData_t; /*========================================*/ @@ -1107,13 +1219,13 @@ typedef struct { * * Used by DRX_CTRL_SET_OOB. */ -typedef struct { - DRXFrequency_t frequency; /**< Frequency in kHz */ - DRXOOBDownstreamStandard_t standard; /**< OOB standard */ - Bool_t spectrumInverted; /**< If TRUE, then spectrum + typedef struct { + DRXFrequency_t frequency; /**< Frequency in kHz */ + DRXOOBDownstreamStandard_t standard; + /**< OOB standard */ + Bool_t spectrumInverted; /**< If TRUE, then spectrum is inverted */ -} DRXOOB_t, *pDRXOOB_t; - + } DRXOOB_t, *pDRXOOB_t; /*========================================*/ @@ -1122,13 +1234,12 @@ typedef struct { * * Used by DRX_CTRL_GET_OOB. */ -typedef struct { - DRXFrequency_t frequency; /**< Frequency in Khz */ - DRXLockStatus_t lock; /**< Lock status */ - u32_t mer; /**< MER */ - s32_t symbolRateOffset; /**< Symbolrate offset in ppm */ -} DRXOOBStatus_t, *pDRXOOBStatus_t; - + typedef struct { + DRXFrequency_t frequency; /**< Frequency in Khz */ + DRXLockStatus_t lock; /**< Lock status */ + u32_t mer; /**< MER */ + s32_t symbolRateOffset; /**< Symbolrate offset in ppm */ + } DRXOOBStatus_t, *pDRXOOBStatus_t; /*========================================*/ @@ -1138,10 +1249,12 @@ typedef struct { * Used by DRX_CTRL_SET_CFG and DRX_CTRL_GET_CFG. * A sort of nested DRX_Ctrl() functionality for device specific controls. */ -typedef struct { - DRXCfgType_t cfgType ; /**< Function identifier */ - void* cfgData ; /**< Function data */ -} DRXCfg_t, *pDRXCfg_t; + typedef struct { + DRXCfgType_t cfgType; + /**< Function identifier */ + void *cfgData; + /**< Function data */ + } DRXCfg_t, *pDRXCfg_t; /*========================================*/ @@ -1150,11 +1263,10 @@ typedef struct { * MStart width [nr MCLK cycles] for serial MPEG output. */ -typedef enum { - DRX_MPEG_STR_WIDTH_1, - DRX_MPEG_STR_WIDTH_8 -} DRXMPEGStrWidth_t, *pDRXMPEGStrWidth_t; - + typedef enum { + DRX_MPEG_STR_WIDTH_1, + DRX_MPEG_STR_WIDTH_8 + } DRXMPEGStrWidth_t, *pDRXMPEGStrWidth_t; /* CTRL CFG MPEG ouput */ /** @@ -1165,44 +1277,45 @@ typedef enum { * DRX_CTRL_GET_CFG. */ -typedef struct { - Bool_t enableMPEGOutput; /**< If TRUE, enable MPEG output */ - Bool_t insertRSByte; /**< If TRUE, insert RS byte */ - Bool_t enableParallel; /**< If TRUE, parallel out otherwise + typedef struct { + Bool_t enableMPEGOutput;/**< If TRUE, enable MPEG output */ + Bool_t insertRSByte; /**< If TRUE, insert RS byte */ + Bool_t enableParallel; /**< If TRUE, parallel out otherwise serial */ - Bool_t invertDATA; /**< If TRUE, invert DATA signals */ - Bool_t invertERR; /**< If TRUE, invert ERR signal */ - Bool_t invertSTR; /**< If TRUE, invert STR signals */ - Bool_t invertVAL; /**< If TRUE, invert VAL signals */ - Bool_t invertCLK; /**< If TRUE, invert CLK signals */ - Bool_t staticCLK; /**< If TRUE, static MPEG clockrate + Bool_t invertDATA; /**< If TRUE, invert DATA signals */ + Bool_t invertERR; /**< If TRUE, invert ERR signal */ + Bool_t invertSTR; /**< If TRUE, invert STR signals */ + Bool_t invertVAL; /**< If TRUE, invert VAL signals */ + Bool_t invertCLK; /**< If TRUE, invert CLK signals */ + Bool_t staticCLK; /**< If TRUE, static MPEG clockrate will be used, otherwise clockrate will adapt to the bitrate of the TS */ - u32_t bitrate; /**< Maximum bitrate in b/s in case + u32_t bitrate; /**< Maximum bitrate in b/s in case static clockrate is selected */ - DRXMPEGStrWidth_t widthSTR; /**< MPEG start width */ -} DRXCfgMPEGOutput_t, *pDRXCfgMPEGOutput_t; + DRXMPEGStrWidth_t widthSTR; + /**< MPEG start width */ + } DRXCfgMPEGOutput_t, *pDRXCfgMPEGOutput_t; /* CTRL CFG SMA */ /** * /struct DRXCfgSMAIO_t * smart antenna i/o. */ -typedef enum DRXCfgSMAIO_t { - DRX_SMA_OUTPUT = 0, - DRX_SMA_INPUT -} DRXCfgSMAIO_t, *pDRXCfgSMAIO_t; + typedef enum DRXCfgSMAIO_t { + DRX_SMA_OUTPUT = 0, + DRX_SMA_INPUT + } DRXCfgSMAIO_t, *pDRXCfgSMAIO_t; /** * /struct DRXCfgSMA_t * Set smart antenna. */ -typedef struct { - DRXCfgSMAIO_t io; - u16_t ctrlData; - Bool_t smartAntInverted; -} DRXCfgSMA_t, *pDRXCfgSMA_t; + typedef struct { + DRXCfgSMAIO_t io; + u16_t ctrlData; + Bool_t smartAntInverted; + } DRXCfgSMA_t, *pDRXCfgSMA_t; /*========================================*/ @@ -1214,15 +1327,17 @@ typedef struct { * If portNr is equal to primairy portNr BSPI2C will be used. * */ -typedef struct { - u16_t portNr; /**< I2C port number */ - pI2CDeviceAddr_t wDevAddr; /**< Write device address */ - u16_t wCount; /**< Size of write data in bytes */ - pu8_t wData; /**< Pointer to write data */ - pI2CDeviceAddr_t rDevAddr; /**< Read device address */ - u16_t rCount; /**< Size of data to read in bytes */ - pu8_t rData; /**< Pointer to read buffer */ -} DRXI2CData_t, *pDRXI2CData_t; + typedef struct { + u16_t portNr; /**< I2C port number */ + pI2CDeviceAddr_t wDevAddr; + /**< Write device address */ + u16_t wCount; /**< Size of write data in bytes */ + pu8_t wData; /**< Pointer to write data */ + pI2CDeviceAddr_t rDevAddr; + /**< Read device address */ + u16_t rCount; /**< Size of data to read in bytes */ + pu8_t rData; /**< Pointer to read buffer */ + } DRXI2CData_t, *pDRXI2CData_t; /*========================================*/ @@ -1232,50 +1347,59 @@ typedef struct { * * Used by DRX_CTRL_SET_AUD. */ -typedef enum { - DRX_AUD_STANDARD_BTSC, /**< set BTSC standard (USA) */ - DRX_AUD_STANDARD_A2, /**< set A2-Korea FM Stereo */ - DRX_AUD_STANDARD_EIAJ, /**< set to Japanese FM Stereo */ - DRX_AUD_STANDARD_FM_STEREO, /**< set to FM-Stereo Radio */ - DRX_AUD_STANDARD_M_MONO, /**< for 4.5 MHz mono detected */ - DRX_AUD_STANDARD_D_K_MONO, /**< for 6.5 MHz mono detected */ - DRX_AUD_STANDARD_BG_FM, /**< set BG_FM standard */ - DRX_AUD_STANDARD_D_K1, /**< set D_K1 standard */ - DRX_AUD_STANDARD_D_K2, /**< set D_K2 standard */ - DRX_AUD_STANDARD_D_K3, /**< set D_K3 standard */ - DRX_AUD_STANDARD_BG_NICAM_FM, /**< set BG_NICAM_FM standard */ - DRX_AUD_STANDARD_L_NICAM_AM, /**< set L_NICAM_AM standard */ - DRX_AUD_STANDARD_I_NICAM_FM, /**< set I_NICAM_FM standard */ - DRX_AUD_STANDARD_D_K_NICAM_FM, /**< set D_K_NICAM_FM standard */ - DRX_AUD_STANDARD_NOT_READY, /**< used to detect audio standard */ - DRX_AUD_STANDARD_AUTO = DRX_AUTO, /**< Automatic Standard Detection */ - DRX_AUD_STANDARD_UNKNOWN = DRX_UNKNOWN /**< used as auto and for readback */ -} DRXAudStandard_t, *pDRXAudStandard_t; + typedef enum { + DRX_AUD_STANDARD_BTSC, /**< set BTSC standard (USA) */ + DRX_AUD_STANDARD_A2, /**< set A2-Korea FM Stereo */ + DRX_AUD_STANDARD_EIAJ, /**< set to Japanese FM Stereo */ + DRX_AUD_STANDARD_FM_STEREO,/**< set to FM-Stereo Radio */ + DRX_AUD_STANDARD_M_MONO, /**< for 4.5 MHz mono detected */ + DRX_AUD_STANDARD_D_K_MONO, /**< for 6.5 MHz mono detected */ + DRX_AUD_STANDARD_BG_FM, /**< set BG_FM standard */ + DRX_AUD_STANDARD_D_K1, /**< set D_K1 standard */ + DRX_AUD_STANDARD_D_K2, /**< set D_K2 standard */ + DRX_AUD_STANDARD_D_K3, /**< set D_K3 standard */ + DRX_AUD_STANDARD_BG_NICAM_FM, + /**< set BG_NICAM_FM standard */ + DRX_AUD_STANDARD_L_NICAM_AM, + /**< set L_NICAM_AM standard */ + DRX_AUD_STANDARD_I_NICAM_FM, + /**< set I_NICAM_FM standard */ + DRX_AUD_STANDARD_D_K_NICAM_FM, + /**< set D_K_NICAM_FM standard */ + DRX_AUD_STANDARD_NOT_READY,/**< used to detect audio standard */ + DRX_AUD_STANDARD_AUTO = DRX_AUTO, + /**< Automatic Standard Detection */ + DRX_AUD_STANDARD_UNKNOWN = DRX_UNKNOWN + /**< used as auto and for readback */ + } DRXAudStandard_t, *pDRXAudStandard_t; /* CTRL_AUD_GET_STATUS - DRXAudStatus_t */ /** * \enum DRXAudNICAMStatus_t * \brief Status of NICAM carrier. */ -typedef enum { - DRX_AUD_NICAM_DETECTED = 0, /**< NICAM carrier detected */ - DRX_AUD_NICAM_NOT_DETECTED, /**< NICAM carrier not detected */ - DRX_AUD_NICAM_BAD /**< NICAM carrier bad quality */ -} DRXAudNICAMStatus_t, *pDRXAudNICAMStatus_t; + typedef enum { + DRX_AUD_NICAM_DETECTED = 0, + /**< NICAM carrier detected */ + DRX_AUD_NICAM_NOT_DETECTED, + /**< NICAM carrier not detected */ + DRX_AUD_NICAM_BAD /**< NICAM carrier bad quality */ + } DRXAudNICAMStatus_t, *pDRXAudNICAMStatus_t; /** * \struct DRXAudStatus_t * \brief Audio status characteristics. */ -typedef struct { - Bool_t stereo; /**< stereo detection */ - Bool_t carrierA; /**< carrier A detected */ - Bool_t carrierB; /**< carrier B detected */ - Bool_t sap; /**< sap / bilingual detection */ - Bool_t rds; /**< RDS data array present */ - DRXAudNICAMStatus_t nicamStatus; /**< status of NICAM carrier */ - s8_t fmIdent; /**< FM Identification value */ -} DRXAudStatus_t, *pDRXAudStatus_t; + typedef struct { + Bool_t stereo; /**< stereo detection */ + Bool_t carrierA; /**< carrier A detected */ + Bool_t carrierB; /**< carrier B detected */ + Bool_t sap; /**< sap / bilingual detection */ + Bool_t rds; /**< RDS data array present */ + DRXAudNICAMStatus_t nicamStatus; + /**< status of NICAM carrier */ + s8_t fmIdent; /**< FM Identification value */ + } DRXAudStatus_t, *pDRXAudStatus_t; /* CTRL_AUD_READ_RDS - DRXRDSdata_t */ @@ -1283,110 +1407,114 @@ typedef struct { * \struct DRXRDSdata_t * \brief Raw RDS data array. */ -typedef struct { - Bool_t valid; /**< RDS data validation */ - u16_t data[18]; /**< data from one RDS data array */ -} DRXCfgAudRDS_t, *pDRXCfgAudRDS_t; + typedef struct { + Bool_t valid; /**< RDS data validation */ + u16_t data[18]; /**< data from one RDS data array */ + } DRXCfgAudRDS_t, *pDRXCfgAudRDS_t; /* DRX_CFG_AUD_VOLUME - DRXCfgAudVolume_t - set/get */ /** * \enum DRXAudAVCDecayTime_t * \brief Automatic volume control configuration. */ -typedef enum { - DRX_AUD_AVC_OFF, /**< Automatic volume control off */ - DRX_AUD_AVC_DECAYTIME_8S, /**< level volume in 8 seconds */ - DRX_AUD_AVC_DECAYTIME_4S, /**< level volume in 4 seconds */ - DRX_AUD_AVC_DECAYTIME_2S, /**< level volume in 2 seconds */ - DRX_AUD_AVC_DECAYTIME_20MS /**< level volume in 20 millisec */ -} DRXAudAVCMode_t, *pDRXAudAVCMode_t; + typedef enum { + DRX_AUD_AVC_OFF, /**< Automatic volume control off */ + DRX_AUD_AVC_DECAYTIME_8S, /**< level volume in 8 seconds */ + DRX_AUD_AVC_DECAYTIME_4S, /**< level volume in 4 seconds */ + DRX_AUD_AVC_DECAYTIME_2S, /**< level volume in 2 seconds */ + DRX_AUD_AVC_DECAYTIME_20MS/**< level volume in 20 millisec */ + } DRXAudAVCMode_t, *pDRXAudAVCMode_t; /** * /enum DRXAudMaxAVCGain_t * /brief Automatic volume control max gain in audio baseband. */ -typedef enum { - DRX_AUD_AVC_MAX_GAIN_0DB, /**< maximum AVC gain 0 dB */ - DRX_AUD_AVC_MAX_GAIN_6DB, /**< maximum AVC gain 6 dB */ - DRX_AUD_AVC_MAX_GAIN_12DB /**< maximum AVC gain 12 dB */ -} DRXAudAVCMaxGain_t, *pDRXAudAVCMaxGain_t; + typedef enum { + DRX_AUD_AVC_MAX_GAIN_0DB, /**< maximum AVC gain 0 dB */ + DRX_AUD_AVC_MAX_GAIN_6DB, /**< maximum AVC gain 6 dB */ + DRX_AUD_AVC_MAX_GAIN_12DB /**< maximum AVC gain 12 dB */ + } DRXAudAVCMaxGain_t, *pDRXAudAVCMaxGain_t; /** * /enum DRXAudMaxAVCAtten_t * /brief Automatic volume control max attenuation in audio baseband. */ -typedef enum { - DRX_AUD_AVC_MAX_ATTEN_12DB, /**< maximum AVC attenuation 12 dB */ - DRX_AUD_AVC_MAX_ATTEN_18DB, /**< maximum AVC attenuation 18 dB */ - DRX_AUD_AVC_MAX_ATTEN_24DB /**< maximum AVC attenuation 24 dB */ -} DRXAudAVCMaxAtten_t, *pDRXAudAVCMaxAtten_t; + typedef enum { + DRX_AUD_AVC_MAX_ATTEN_12DB, + /**< maximum AVC attenuation 12 dB */ + DRX_AUD_AVC_MAX_ATTEN_18DB, + /**< maximum AVC attenuation 18 dB */ + DRX_AUD_AVC_MAX_ATTEN_24DB/**< maximum AVC attenuation 24 dB */ + } DRXAudAVCMaxAtten_t, *pDRXAudAVCMaxAtten_t; /** * \struct DRXCfgAudVolume_t * \brief Audio volume configuration. */ -typedef struct { - Bool_t mute; /**< mute overrides volume setting */ - s16_t volume; /**< volume, range -114 to 12 dB */ - DRXAudAVCMode_t avcMode; /**< AVC auto volume control mode */ - u16_t avcRefLevel; /**< AVC reference level */ - DRXAudAVCMaxGain_t avcMaxGain; /**< AVC max gain selection */ - DRXAudAVCMaxAtten_t avcMaxAtten; /**< AVC max attenuation selection */ - s16_t strengthLeft; /**< quasi-peak, left speaker */ - s16_t strengthRight; /**< quasi-peak, right speaker */ -} DRXCfgAudVolume_t, *pDRXCfgAudVolume_t; + typedef struct { + Bool_t mute; /**< mute overrides volume setting */ + s16_t volume; /**< volume, range -114 to 12 dB */ + DRXAudAVCMode_t avcMode; /**< AVC auto volume control mode */ + u16_t avcRefLevel; /**< AVC reference level */ + DRXAudAVCMaxGain_t avcMaxGain; + /**< AVC max gain selection */ + DRXAudAVCMaxAtten_t avcMaxAtten; + /**< AVC max attenuation selection */ + s16_t strengthLeft; /**< quasi-peak, left speaker */ + s16_t strengthRight; /**< quasi-peak, right speaker */ + } DRXCfgAudVolume_t, *pDRXCfgAudVolume_t; /* DRX_CFG_I2S_OUTPUT - DRXCfgI2SOutput_t - set/get */ /** * \enum DRXI2SMode_t * \brief I2S output mode. */ -typedef enum { - DRX_I2S_MODE_MASTER, /**< I2S is in master mode */ - DRX_I2S_MODE_SLAVE /**< I2S is in slave mode */ -} DRXI2SMode_t, *pDRXI2SMode_t; + typedef enum { + DRX_I2S_MODE_MASTER, /**< I2S is in master mode */ + DRX_I2S_MODE_SLAVE /**< I2S is in slave mode */ + } DRXI2SMode_t, *pDRXI2SMode_t; /** * \enum DRXI2SWordLength_t * \brief Width of I2S data. */ -typedef enum { - DRX_I2S_WORDLENGTH_32 = 0, /**< I2S data is 32 bit wide */ - DRX_I2S_WORDLENGTH_16 = 1 /**< I2S data is 16 bit wide */ -} DRXI2SWordLength_t, *pDRXI2SWordLength_t; + typedef enum { + DRX_I2S_WORDLENGTH_32 = 0,/**< I2S data is 32 bit wide */ + DRX_I2S_WORDLENGTH_16 = 1 /**< I2S data is 16 bit wide */ + } DRXI2SWordLength_t, *pDRXI2SWordLength_t; /** * \enum DRXI2SFormat_t * \brief Data wordstrobe alignment for I2S. */ -typedef enum { - DRX_I2S_FORMAT_WS_WITH_DATA, /**< I2S data and wordstrobe are aligned */ - DRX_I2S_FORMAT_WS_ADVANCED /**< I2S data one cycle after wordstrobe */ -} DRXI2SFormat_t, *pDRXI2SFormat_t; + typedef enum { + DRX_I2S_FORMAT_WS_WITH_DATA, + /**< I2S data and wordstrobe are aligned */ + DRX_I2S_FORMAT_WS_ADVANCED + /**< I2S data one cycle after wordstrobe */ + } DRXI2SFormat_t, *pDRXI2SFormat_t; /** * \enum DRXI2SPolarity_t * \brief Polarity of I2S data. */ -typedef enum { - DRX_I2S_POLARITY_RIGHT, /**< wordstrobe - right high, left low */ - DRX_I2S_POLARITY_LEFT /**< wordstrobe - right low, left high */ -} DRXI2SPolarity_t, *pDRXI2SPolarity_t; - - + typedef enum { + DRX_I2S_POLARITY_RIGHT,/**< wordstrobe - right high, left low */ + DRX_I2S_POLARITY_LEFT /**< wordstrobe - right low, left high */ + } DRXI2SPolarity_t, *pDRXI2SPolarity_t; /** * \struct DRXCfgI2SOutput_t * \brief I2S output configuration. */ -typedef struct { - Bool_t outputEnable; /**< I2S output enable */ - u32_t frequency; /**< range from 8000-48000 Hz */ - DRXI2SMode_t mode; /**< I2S mode, master or slave */ - DRXI2SWordLength_t wordLength; /**< I2S wordlength, 16 or 32 bits */ - DRXI2SPolarity_t polarity; /**< I2S wordstrobe polarity */ - DRXI2SFormat_t format; /**< I2S wordstrobe delay to data */ -} DRXCfgI2SOutput_t, *pDRXCfgI2SOutput_t; - + typedef struct { + Bool_t outputEnable; /**< I2S output enable */ + u32_t frequency; /**< range from 8000-48000 Hz */ + DRXI2SMode_t mode; /**< I2S mode, master or slave */ + DRXI2SWordLength_t wordLength; + /**< I2S wordlength, 16 or 32 bits */ + DRXI2SPolarity_t polarity;/**< I2S wordstrobe polarity */ + DRXI2SFormat_t format; /**< I2S wordstrobe delay to data */ + } DRXCfgI2SOutput_t, *pDRXCfgI2SOutput_t; /* ------------------------------expert interface-----------------------------*/ /** @@ -1394,119 +1522,119 @@ typedef struct { * setting for FM-Deemphasis in audio demodulator. * */ -typedef enum { - DRX_AUD_FM_DEEMPH_50US, - DRX_AUD_FM_DEEMPH_75US, - DRX_AUD_FM_DEEMPH_OFF -} DRXAudFMDeemphasis_t, *pDRXAudFMDeemphasis_t; + typedef enum { + DRX_AUD_FM_DEEMPH_50US, + DRX_AUD_FM_DEEMPH_75US, + DRX_AUD_FM_DEEMPH_OFF + } DRXAudFMDeemphasis_t, *pDRXAudFMDeemphasis_t; /** * /enum DRXAudDeviation_t * setting for deviation mode in audio demodulator. * */ -typedef enum { - DRX_AUD_DEVIATION_NORMAL, - DRX_AUD_DEVIATION_HIGH -} DRXCfgAudDeviation_t, *pDRXCfgAudDeviation_t; + typedef enum { + DRX_AUD_DEVIATION_NORMAL, + DRX_AUD_DEVIATION_HIGH + } DRXCfgAudDeviation_t, *pDRXCfgAudDeviation_t; /** * /enum DRXNoCarrierOption_t * setting for carrier, mute/noise. * */ -typedef enum { - DRX_NO_CARRIER_MUTE, - DRX_NO_CARRIER_NOISE -} DRXNoCarrierOption_t, *pDRXNoCarrierOption_t; - + typedef enum { + DRX_NO_CARRIER_MUTE, + DRX_NO_CARRIER_NOISE + } DRXNoCarrierOption_t, *pDRXNoCarrierOption_t; /** * \enum DRXAudAutoSound_t * \brief Automatic Sound */ -typedef enum { - DRX_AUD_AUTO_SOUND_OFF = 0, - DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON, - DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_OFF -} DRXCfgAudAutoSound_t, *pDRXCfgAudAutoSound_t; + typedef enum { + DRX_AUD_AUTO_SOUND_OFF = 0, + DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON, + DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_OFF + } DRXCfgAudAutoSound_t, *pDRXCfgAudAutoSound_t; /** * \enum DRXAudASSThres_t * \brief Automatic Sound Select Thresholds */ -typedef struct { - u16_t a2; /* A2 Threshold for ASS configuration */ - u16_t btsc; /* BTSC Threshold for ASS configuration */ - u16_t nicam; /* Nicam Threshold for ASS configuration */ -} DRXCfgAudASSThres_t, *pDRXCfgAudASSThres_t; + typedef struct { + u16_t a2; /* A2 Threshold for ASS configuration */ + u16_t btsc; /* BTSC Threshold for ASS configuration */ + u16_t nicam; /* Nicam Threshold for ASS configuration */ + } DRXCfgAudASSThres_t, *pDRXCfgAudASSThres_t; /** * \struct DRXAudCarrier_t * \brief Carrier detection related parameters */ -typedef struct { - u16_t thres; /* carrier detetcion threshold for primary carrier (A) */ - DRXNoCarrierOption_t opt; /* Mute or noise at no carrier detection (A) */ - DRXFrequency_t shift; /* DC level of incoming signal (A) */ - DRXFrequency_t dco; /* frequency adjustment (A) */ -} DRXAudCarrier_t, *pDRXCfgAudCarrier_t; + typedef struct { + u16_t thres; /* carrier detetcion threshold for primary carrier (A) */ + DRXNoCarrierOption_t opt; /* Mute or noise at no carrier detection (A) */ + DRXFrequency_t shift; /* DC level of incoming signal (A) */ + DRXFrequency_t dco; /* frequency adjustment (A) */ + } DRXAudCarrier_t, *pDRXCfgAudCarrier_t; /** * \struct DRXCfgAudCarriers_t * \brief combining carrier A & B to one struct */ -typedef struct { - DRXAudCarrier_t a; - DRXAudCarrier_t b; -} DRXCfgAudCarriers_t, *pDRXCfgAudCarriers_t; + typedef struct { + DRXAudCarrier_t a; + DRXAudCarrier_t b; + } DRXCfgAudCarriers_t, *pDRXCfgAudCarriers_t; /** * /enum DRXAudI2SSrc_t * Selection of audio source */ -typedef enum { - DRX_AUD_SRC_MONO, - DRX_AUD_SRC_STEREO_OR_AB, - DRX_AUD_SRC_STEREO_OR_A, - DRX_AUD_SRC_STEREO_OR_B -} DRXAudI2SSrc_t, *pDRXAudI2SSrc_t; - + typedef enum { + DRX_AUD_SRC_MONO, + DRX_AUD_SRC_STEREO_OR_AB, + DRX_AUD_SRC_STEREO_OR_A, + DRX_AUD_SRC_STEREO_OR_B + } DRXAudI2SSrc_t, *pDRXAudI2SSrc_t; /** * \enum DRXAudI2SMatrix_t * \brief Used for selecting I2S output. */ -typedef enum { - DRX_AUD_I2S_MATRIX_A_MONO, /**< A sound only, stereo or mono */ - DRX_AUD_I2S_MATRIX_B_MONO, /**< B sound only, stereo or mono */ - DRX_AUD_I2S_MATRIX_STEREO, /**< A+B sound, transparant */ - DRX_AUD_I2S_MATRIX_MONO /**< A+B mixed to mono sum, (L+R)/2 */ -} DRXAudI2SMatrix_t, *pDRXAudI2SMatrix_t; - + typedef enum { + DRX_AUD_I2S_MATRIX_A_MONO, + /**< A sound only, stereo or mono */ + DRX_AUD_I2S_MATRIX_B_MONO, + /**< B sound only, stereo or mono */ + DRX_AUD_I2S_MATRIX_STEREO, + /**< A+B sound, transparant */ + DRX_AUD_I2S_MATRIX_MONO /**< A+B mixed to mono sum, (L+R)/2 */ + } DRXAudI2SMatrix_t, *pDRXAudI2SMatrix_t; /** * /enum DRXAudFMMatrix_t * setting for FM-Matrix in audio demodulator. * */ -typedef enum { - DRX_AUD_FM_MATRIX_NO_MATRIX, - DRX_AUD_FM_MATRIX_GERMAN, - DRX_AUD_FM_MATRIX_KOREAN, - DRX_AUD_FM_MATRIX_SOUND_A, - DRX_AUD_FM_MATRIX_SOUND_B -} DRXAudFMMatrix_t, *pDRXAudFMMatrix_t; + typedef enum { + DRX_AUD_FM_MATRIX_NO_MATRIX, + DRX_AUD_FM_MATRIX_GERMAN, + DRX_AUD_FM_MATRIX_KOREAN, + DRX_AUD_FM_MATRIX_SOUND_A, + DRX_AUD_FM_MATRIX_SOUND_B + } DRXAudFMMatrix_t, *pDRXAudFMMatrix_t; /** * \struct DRXAudMatrices_t * \brief Mixer settings */ -typedef struct { - DRXAudI2SSrc_t sourceI2S; - DRXAudI2SMatrix_t matrixI2S; - DRXAudFMMatrix_t matrixFm; -} DRXCfgAudMixer_t, *pDRXCfgAudMixer_t; + typedef struct { + DRXAudI2SSrc_t sourceI2S; + DRXAudI2SMatrix_t matrixI2S; + DRXAudFMMatrix_t matrixFm; + } DRXCfgAudMixer_t, *pDRXCfgAudMixer_t; /** * \enum DRXI2SVidSync_t @@ -1514,77 +1642,76 @@ typedef struct { * AUTO_1 and AUTO_2 are for automatic video standard detection with preference * for NTSC or Monochrome, because the frequencies are too close (59.94 & 60 Hz) */ -typedef enum { - DRX_AUD_AVSYNC_OFF, /**< audio/video synchronization is off */ - DRX_AUD_AVSYNC_NTSC, /**< it is an NTSC system */ - DRX_AUD_AVSYNC_MONOCHROME, /**< it is a MONOCHROME system */ - DRX_AUD_AVSYNC_PAL_SECAM /**< it is a PAL/SECAM system */ -} DRXCfgAudAVSync_t, *pDRXCfgAudAVSync_t; + typedef enum { + DRX_AUD_AVSYNC_OFF,/**< audio/video synchronization is off */ + DRX_AUD_AVSYNC_NTSC, + /**< it is an NTSC system */ + DRX_AUD_AVSYNC_MONOCHROME, + /**< it is a MONOCHROME system */ + DRX_AUD_AVSYNC_PAL_SECAM + /**< it is a PAL/SECAM system */ + } DRXCfgAudAVSync_t, *pDRXCfgAudAVSync_t; /** * \struct DRXCfgAudPrescale_t * \brief Prescalers */ -typedef struct { - u16_t fmDeviation; - s16_t nicamGain; -} DRXCfgAudPrescale_t, *pDRXCfgAudPrescale_t; + typedef struct { + u16_t fmDeviation; + s16_t nicamGain; + } DRXCfgAudPrescale_t, *pDRXCfgAudPrescale_t; /** * \struct DRXAudBeep_t * \brief Beep */ -typedef struct { - s16_t volume; /* dB */ - u16_t frequency; /* Hz */ - Bool_t mute; -} DRXAudBeep_t, *pDRXAudBeep_t; - + typedef struct { + s16_t volume; /* dB */ + u16_t frequency; /* Hz */ + Bool_t mute; + } DRXAudBeep_t, *pDRXAudBeep_t; /** * \enum DRXAudBtscDetect_t * \brief BTSC detetcion mode */ -typedef enum { - DRX_BTSC_STEREO, - DRX_BTSC_MONO_AND_SAP -} DRXAudBtscDetect_t, *pDRXAudBtscDetect_t; + typedef enum { + DRX_BTSC_STEREO, + DRX_BTSC_MONO_AND_SAP + } DRXAudBtscDetect_t, *pDRXAudBtscDetect_t; /** * \struct DRXAudData_t * \brief Audio data structure */ -typedef struct -{ - /* audio storage */ - Bool_t audioIsActive; - DRXAudStandard_t audioStandard; - DRXCfgI2SOutput_t i2sdata; - DRXCfgAudVolume_t volume; - DRXCfgAudAutoSound_t autoSound; - DRXCfgAudASSThres_t assThresholds; - DRXCfgAudCarriers_t carriers; - DRXCfgAudMixer_t mixer; - DRXCfgAudDeviation_t deviation; - DRXCfgAudAVSync_t avSync; - DRXCfgAudPrescale_t prescale; - DRXAudFMDeemphasis_t deemph; - DRXAudBtscDetect_t btscDetect; - /* rds */ - u16_t rdsDataCounter; - Bool_t rdsDataPresent; -} DRXAudData_t, *pDRXAudData_t; - + typedef struct { + /* audio storage */ + Bool_t audioIsActive; + DRXAudStandard_t audioStandard; + DRXCfgI2SOutput_t i2sdata; + DRXCfgAudVolume_t volume; + DRXCfgAudAutoSound_t autoSound; + DRXCfgAudASSThres_t assThresholds; + DRXCfgAudCarriers_t carriers; + DRXCfgAudMixer_t mixer; + DRXCfgAudDeviation_t deviation; + DRXCfgAudAVSync_t avSync; + DRXCfgAudPrescale_t prescale; + DRXAudFMDeemphasis_t deemph; + DRXAudBtscDetect_t btscDetect; + /* rds */ + u16_t rdsDataCounter; + Bool_t rdsDataPresent; + } DRXAudData_t, *pDRXAudData_t; /** * \enum DRXQamLockRange_t * \brief QAM lock range mode */ -typedef enum -{ - DRX_QAM_LOCKRANGE_NORMAL, - DRX_QAM_LOCKRANGE_EXTENDED -}DRXQamLockRange_t, *pDRXQamLockRange_t; + typedef enum { + DRX_QAM_LOCKRANGE_NORMAL, + DRX_QAM_LOCKRANGE_EXTENDED + } DRXQamLockRange_t, *pDRXQamLockRange_t; /*============================================================================*/ /*============================================================================*/ @@ -1593,119 +1720,108 @@ typedef enum /*============================================================================*/ /* Address on device */ -typedef u32_t DRXaddr_t, *pDRXaddr_t; + typedef u32_t DRXaddr_t, *pDRXaddr_t; /* Protocol specific flags */ -typedef u32_t DRXflags_t, *pDRXflags_t; + typedef u32_t DRXflags_t, *pDRXflags_t; /* Write block of data to device */ -typedef DRXStatus_t (*DRXWriteBlockFunc_t) ( - pI2CDeviceAddr_t devAddr, /* address of I2C device */ - DRXaddr_t addr, /* address of register/memory */ - u16_t datasize, /* size of data in bytes */ - pu8_t data, /* data to send */ - DRXflags_t flags); + typedef DRXStatus_t(*DRXWriteBlockFunc_t) (pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register/memory */ + u16_t datasize, /* size of data in bytes */ + pu8_t data, /* data to send */ + DRXflags_t flags); /* Read block of data from device */ -typedef DRXStatus_t (*DRXReadBlockFunc_t) ( - pI2CDeviceAddr_t devAddr, /* address of I2C device */ - DRXaddr_t addr, /* address of register/memory */ - u16_t datasize, /* size of data in bytes */ - pu8_t data, /* receive buffer */ - DRXflags_t flags); + typedef DRXStatus_t(*DRXReadBlockFunc_t) (pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register/memory */ + u16_t datasize, /* size of data in bytes */ + pu8_t data, /* receive buffer */ + DRXflags_t flags); /* Write 8-bits value to device */ -typedef DRXStatus_t (*DRXWriteReg8Func_t) ( - pI2CDeviceAddr_t devAddr, /* address of I2C device */ - DRXaddr_t addr, /* address of register/memory */ - u8_t data, /* data to send */ - DRXflags_t flags); + typedef DRXStatus_t(*DRXWriteReg8Func_t) (pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register/memory */ + u8_t data, /* data to send */ + DRXflags_t flags); /* Read 8-bits value to device */ -typedef DRXStatus_t (*DRXReadReg8Func_t) ( - pI2CDeviceAddr_t devAddr, /* address of I2C device */ - DRXaddr_t addr, /* address of register/memory */ - pu8_t data, /* receive buffer */ - DRXflags_t flags); + typedef DRXStatus_t(*DRXReadReg8Func_t) (pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register/memory */ + pu8_t data, /* receive buffer */ + DRXflags_t flags); /* Read modify write 8-bits value to device */ -typedef DRXStatus_t (*DRXReadModifyWriteReg8Func_t) ( - pI2CDeviceAddr_t devAddr, /* address of I2C device */ - DRXaddr_t waddr, /* write address of register */ - DRXaddr_t raddr, /* read address of register */ - u8_t wdata, /* data to write */ - pu8_t rdata); /* data to read */ + typedef DRXStatus_t(*DRXReadModifyWriteReg8Func_t) (pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t waddr, /* write address of register */ + DRXaddr_t raddr, /* read address of register */ + u8_t wdata, /* data to write */ + pu8_t rdata); /* data to read */ /* Write 16-bits value to device */ -typedef DRXStatus_t (*DRXWriteReg16Func_t) ( - pI2CDeviceAddr_t devAddr, /* address of I2C device */ - DRXaddr_t addr, /* address of register/memory */ - u16_t data, /* data to send */ - DRXflags_t flags); + typedef DRXStatus_t(*DRXWriteReg16Func_t) (pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register/memory */ + u16_t data, /* data to send */ + DRXflags_t flags); /* Read 16-bits value to device */ -typedef DRXStatus_t (*DRXReadReg16Func_t) ( - pI2CDeviceAddr_t devAddr, /* address of I2C device */ - DRXaddr_t addr, /* address of register/memory */ - pu16_t data, /* receive buffer */ - DRXflags_t flags); + typedef DRXStatus_t(*DRXReadReg16Func_t) (pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register/memory */ + pu16_t data, /* receive buffer */ + DRXflags_t flags); /* Read modify write 16-bits value to device */ -typedef DRXStatus_t (*DRXReadModifyWriteReg16Func_t) ( - pI2CDeviceAddr_t devAddr, /* address of I2C device */ - DRXaddr_t waddr, /* write address of register */ - DRXaddr_t raddr, /* read address of register */ - u16_t wdata, /* data to write */ - pu16_t rdata); /* data to read */ + typedef DRXStatus_t(*DRXReadModifyWriteReg16Func_t) (pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t waddr, /* write address of register */ + DRXaddr_t raddr, /* read address of register */ + u16_t wdata, /* data to write */ + pu16_t rdata); /* data to read */ /* Write 32-bits value to device */ -typedef DRXStatus_t (*DRXWriteReg32Func_t) ( - pI2CDeviceAddr_t devAddr, /* address of I2C device */ - DRXaddr_t addr, /* address of register/memory */ - u32_t data, /* data to send */ - DRXflags_t flags); + typedef DRXStatus_t(*DRXWriteReg32Func_t) (pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register/memory */ + u32_t data, /* data to send */ + DRXflags_t flags); /* Read 32-bits value to device */ -typedef DRXStatus_t (*DRXReadReg32Func_t) ( - pI2CDeviceAddr_t devAddr, /* address of I2C device */ - DRXaddr_t addr, /* address of register/memory */ - pu32_t data, /* receive buffer */ - DRXflags_t flags); + typedef DRXStatus_t(*DRXReadReg32Func_t) (pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register/memory */ + pu32_t data, /* receive buffer */ + DRXflags_t flags); /* Read modify write 32-bits value to device */ -typedef DRXStatus_t (*DRXReadModifyWriteReg32Func_t) ( - pI2CDeviceAddr_t devAddr, /* address of I2C device */ - DRXaddr_t waddr, /* write address of register */ - DRXaddr_t raddr, /* read address of register */ - u32_t wdata, /* data to write */ - pu32_t rdata); /* data to read */ + typedef DRXStatus_t(*DRXReadModifyWriteReg32Func_t) (pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t waddr, /* write address of register */ + DRXaddr_t raddr, /* read address of register */ + u32_t wdata, /* data to write */ + pu32_t rdata); /* data to read */ /** * \struct DRXAccessFunc_t * \brief Interface to an access protocol. */ -typedef struct { - pDRXVersion_t protocolVersion; - DRXWriteBlockFunc_t writeBlockFunc; - DRXReadBlockFunc_t readBlockFunc; - DRXWriteReg8Func_t writeReg8Func; - DRXReadReg8Func_t readReg8Func; - DRXReadModifyWriteReg8Func_t readModifyWriteReg8Func; - DRXWriteReg16Func_t writeReg16Func; - DRXReadReg16Func_t readReg16Func; - DRXReadModifyWriteReg16Func_t readModifyWriteReg16Func; - DRXWriteReg32Func_t writeReg32Func; - DRXReadReg32Func_t readReg32Func; - DRXReadModifyWriteReg32Func_t readModifyWriteReg32Func; -} DRXAccessFunc_t, *pDRXAccessFunc_t; + typedef struct { + pDRXVersion_t protocolVersion; + DRXWriteBlockFunc_t writeBlockFunc; + DRXReadBlockFunc_t readBlockFunc; + DRXWriteReg8Func_t writeReg8Func; + DRXReadReg8Func_t readReg8Func; + DRXReadModifyWriteReg8Func_t readModifyWriteReg8Func; + DRXWriteReg16Func_t writeReg16Func; + DRXReadReg16Func_t readReg16Func; + DRXReadModifyWriteReg16Func_t readModifyWriteReg16Func; + DRXWriteReg32Func_t writeReg32Func; + DRXReadReg32Func_t readReg32Func; + DRXReadModifyWriteReg32Func_t readModifyWriteReg32Func; + } DRXAccessFunc_t, *pDRXAccessFunc_t; /* Register address and data for register dump function */ -typedef struct { + typedef struct { - DRXaddr_t address; - u32_t data; + DRXaddr_t address; + u32_t data; -} DRXRegDump_t, *pDRXRegDump_t ; + } DRXRegDump_t, *pDRXRegDump_t; /*============================================================================*/ /*============================================================================*/ @@ -1717,103 +1833,128 @@ typedef struct { * \struct DRXCommonAttr_t * \brief Set of common attributes, shared by all DRX devices. */ -typedef struct { - /* Microcode (firmware) attributes */ - pu8_t microcode; /**< Pointer to microcode image. */ - u16_t microcodeSize; /**< Size of microcode image in bytes. */ - Bool_t verifyMicrocode; /**< Use microcode verify or not. */ - DRXMcVersionRec_t mcversion; /**< Version record of microcode from file */ - - /* Clocks and tuner attributes */ - DRXFrequency_t intermediateFreq; /**< IF,if tuner instance not used. (kHz)*/ - DRXFrequency_t sysClockFreq; /**< Systemclock frequency. (kHz) */ - DRXFrequency_t oscClockFreq; /**< Oscillator clock frequency. (kHz) */ - s16_t oscClockDeviation; /**< Oscillator clock deviation. (ppm) */ - Bool_t mirrorFreqSpect; /**< Mirror IF frequency spectrum or not.*/ - - /* Initial MPEG output attributes */ - DRXCfgMPEGOutput_t mpegCfg; /**< MPEG configuration */ - - Bool_t isOpened; /**< if TRUE instance is already opened. */ - - /* Channel scan */ - pDRXScanParam_t scanParam; /**< scan parameters */ - u16_t scanFreqPlanIndex; /**< next index in freq plan */ - DRXFrequency_t scanNextFrequency; /**< next freq to scan */ - Bool_t scanReady; /**< scan ready flag */ - u32_t scanMaxChannels; /**< number of channels in freqplan */ - u32_t scanChannelsScanned; /**< number of channels scanned */ - /* Channel scan - inner loop: demod related */ - DRXScanFunc_t scanFunction; /**< function to check channel */ - /* Channel scan - inner loop: SYSObj related */ - void* scanContext; /**< Context Pointer of SYSObj */ - /* Channel scan - parameters for default DTV scan function in core driver */ - u16_t scanDemodLockTimeout; /**< millisecs to wait for lock */ - DRXLockStatus_t scanDesiredLock; /**< lock requirement for channel found */ - /* scanActive can be used by SetChannel to decide how to program the tuner, - fast or slow (but stable). Usually fast during scan. */ - Bool_t scanActive; /**< TRUE when scan routines are active */ - - /* Power management */ - DRXPowerMode_t currentPowerMode; /**< current power management mode */ - - /* Tuner */ - u8_t tunerPortNr; /**< nr of I2C port to wich tuner is */ - DRXFrequency_t tunerMinFreqRF; /**< minimum RF input frequency, in kHz */ - DRXFrequency_t tunerMaxFreqRF; /**< maximum RF input frequency, in kHz */ - Bool_t tunerRfAgcPol; /**< if TRUE invert RF AGC polarity */ - Bool_t tunerIfAgcPol; /**< if TRUE invert IF AGC polarity */ - Bool_t tunerSlowMode; /**< if TRUE invert IF AGC polarity */ - - DRXChannel_t currentChannel; /**< current channel parameters */ - DRXStandard_t currentStandard; /**< current standard selection */ - DRXStandard_t prevStandard; /**< previous standard selection */ - DRXStandard_t diCacheStandard; /**< standard in DI cache if available */ - Bool_t useBootloader; /**< use bootloader in open */ - u32_t capabilities; /**< capabilities flags */ - u32_t productId; /**< product ID inc. metal fix number */ - -} DRXCommonAttr_t, *pDRXCommonAttr_t; - + typedef struct { + /* Microcode (firmware) attributes */ + pu8_t microcode; /**< Pointer to microcode image. */ + u16_t microcodeSize; + /**< Size of microcode image in bytes. */ + Bool_t verifyMicrocode; + /**< Use microcode verify or not. */ + DRXMcVersionRec_t mcversion; + /**< Version record of microcode from file */ + + /* Clocks and tuner attributes */ + DRXFrequency_t intermediateFreq; + /**< IF,if tuner instance not used. (kHz)*/ + DRXFrequency_t sysClockFreq; + /**< Systemclock frequency. (kHz) */ + DRXFrequency_t oscClockFreq; + /**< Oscillator clock frequency. (kHz) */ + s16_t oscClockDeviation; + /**< Oscillator clock deviation. (ppm) */ + Bool_t mirrorFreqSpect; + /**< Mirror IF frequency spectrum or not.*/ + + /* Initial MPEG output attributes */ + DRXCfgMPEGOutput_t mpegCfg; + /**< MPEG configuration */ + + Bool_t isOpened; /**< if TRUE instance is already opened. */ + + /* Channel scan */ + pDRXScanParam_t scanParam; + /**< scan parameters */ + u16_t scanFreqPlanIndex; + /**< next index in freq plan */ + DRXFrequency_t scanNextFrequency; + /**< next freq to scan */ + Bool_t scanReady; /**< scan ready flag */ + u32_t scanMaxChannels;/**< number of channels in freqplan */ + u32_t scanChannelsScanned; + /**< number of channels scanned */ + /* Channel scan - inner loop: demod related */ + DRXScanFunc_t scanFunction; + /**< function to check channel */ + /* Channel scan - inner loop: SYSObj related */ + void *scanContext; /**< Context Pointer of SYSObj */ + /* Channel scan - parameters for default DTV scan function in core driver */ + u16_t scanDemodLockTimeout; + /**< millisecs to wait for lock */ + DRXLockStatus_t scanDesiredLock; + /**< lock requirement for channel found */ + /* scanActive can be used by SetChannel to decide how to program the tuner, + fast or slow (but stable). Usually fast during scan. */ + Bool_t scanActive; /**< TRUE when scan routines are active */ + + /* Power management */ + DRXPowerMode_t currentPowerMode; + /**< current power management mode */ + + /* Tuner */ + u8_t tunerPortNr; /**< nr of I2C port to wich tuner is */ + DRXFrequency_t tunerMinFreqRF; + /**< minimum RF input frequency, in kHz */ + DRXFrequency_t tunerMaxFreqRF; + /**< maximum RF input frequency, in kHz */ + Bool_t tunerRfAgcPol; /**< if TRUE invert RF AGC polarity */ + Bool_t tunerIfAgcPol; /**< if TRUE invert IF AGC polarity */ + Bool_t tunerSlowMode; /**< if TRUE invert IF AGC polarity */ + + DRXChannel_t currentChannel; + /**< current channel parameters */ + DRXStandard_t currentStandard; + /**< current standard selection */ + DRXStandard_t prevStandard; + /**< previous standard selection */ + DRXStandard_t diCacheStandard; + /**< standard in DI cache if available */ + Bool_t useBootloader; /**< use bootloader in open */ + u32_t capabilities; /**< capabilities flags */ + u32_t productId; /**< product ID inc. metal fix number */ + + } DRXCommonAttr_t, *pDRXCommonAttr_t; /* * Generic functions for DRX devices. */ -typedef struct DRXDemodInstance_s *pDRXDemodInstance_t; + typedef struct DRXDemodInstance_s *pDRXDemodInstance_t; -typedef DRXStatus_t (*DRXOpenFunc_t) (pDRXDemodInstance_t demod); -typedef DRXStatus_t (*DRXCloseFunc_t) (pDRXDemodInstance_t demod); -typedef DRXStatus_t (*DRXCtrlFunc_t) (pDRXDemodInstance_t demod, - DRXCtrlIndex_t ctrl, - void *ctrlData); + typedef DRXStatus_t(*DRXOpenFunc_t) (pDRXDemodInstance_t demod); + typedef DRXStatus_t(*DRXCloseFunc_t) (pDRXDemodInstance_t demod); + typedef DRXStatus_t(*DRXCtrlFunc_t) (pDRXDemodInstance_t demod, + DRXCtrlIndex_t ctrl, + void *ctrlData); /** * \struct DRXDemodFunc_t * \brief A stucture containing all functions of a demodulator. */ -typedef struct { - u32_t typeId; /**< Device type identifier. */ - DRXOpenFunc_t openFunc; /**< Pointer to Open() function. */ - DRXCloseFunc_t closeFunc; /**< Pointer to Close() function. */ - DRXCtrlFunc_t ctrlFunc; /**< Pointer to Ctrl() function. */ -} DRXDemodFunc_t, *pDRXDemodFunc_t; + typedef struct { + u32_t typeId; /**< Device type identifier. */ + DRXOpenFunc_t openFunc; /**< Pointer to Open() function. */ + DRXCloseFunc_t closeFunc;/**< Pointer to Close() function. */ + DRXCtrlFunc_t ctrlFunc; /**< Pointer to Ctrl() function. */ + } DRXDemodFunc_t, *pDRXDemodFunc_t; /** * \struct DRXDemodInstance_t * \brief Top structure of demodulator instance. */ -typedef struct DRXDemodInstance_s { - /* type specific demodulator data */ - pDRXDemodFunc_t myDemodFunct; /**< demodulator functions */ - pDRXAccessFunc_t myAccessFunct; /**< data access protocol functions */ - pTUNERInstance_t myTuner; /**< tuner instance,if NULL then baseband */ - pI2CDeviceAddr_t myI2CDevAddr; /**< i2c address and device identifier */ - pDRXCommonAttr_t myCommonAttr; /**< common DRX attributes */ - void* myExtAttr; /**< device specific attributes */ - /* generic demodulator data */ -} DRXDemodInstance_t; - - + typedef struct DRXDemodInstance_s { + /* type specific demodulator data */ + pDRXDemodFunc_t myDemodFunct; + /**< demodulator functions */ + pDRXAccessFunc_t myAccessFunct; + /**< data access protocol functions */ + pTUNERInstance_t myTuner; + /**< tuner instance,if NULL then baseband */ + pI2CDeviceAddr_t myI2CDevAddr; + /**< i2c address and device identifier */ + pDRXCommonAttr_t myCommonAttr; + /**< common DRX attributes */ + void *myExtAttr; /**< device specific attributes */ + /* generic demodulator data */ + } DRXDemodInstance_t; /*------------------------------------------------------------------------- MACROS @@ -2097,7 +2238,6 @@ Conversion from enum values to human readable form. Access macros -------------------------------------------------------------------------*/ - /** * \brief Create a compilable reference to the microcode attribute * \param d pointer to demod instance @@ -2494,7 +2634,6 @@ Access macros } \ } while ( 0 ) - /* Configuration functions for usage by Access (XS) Macros */ #ifndef DRX_XS_CFG_BASE @@ -2522,7 +2661,6 @@ Access macros #define DRX_GET_QAM_LOCKRANGE( d, x ) DRX_ACCESSMACRO_GET( (d), (x), \ DRX_XS_CFG_QAM_LOCKRANGE, DRXQamLockRange_t, DRX_UNKNOWN ) - /** * \brief Macro to check if std is an ATV standard * \retval TRUE std is an ATV standard @@ -2560,24 +2698,20 @@ Access macros */ #define DRX_ISDVBTSTD( std ) ( (std) == DRX_STANDARD_DVBT ) - - - /*------------------------------------------------------------------------- Exported FUNCTIONS -------------------------------------------------------------------------*/ -DRXStatus_t DRX_Init( pDRXDemodInstance_t demods[] ); + DRXStatus_t DRX_Init(pDRXDemodInstance_t demods[]); -DRXStatus_t DRX_Term( void ); + DRXStatus_t DRX_Term(void); -DRXStatus_t DRX_Open(pDRXDemodInstance_t demod); + DRXStatus_t DRX_Open(pDRXDemodInstance_t demod); -DRXStatus_t DRX_Close(pDRXDemodInstance_t demod); + DRXStatus_t DRX_Close(pDRXDemodInstance_t demod); -DRXStatus_t DRX_Ctrl(pDRXDemodInstance_t demod, - DRXCtrlIndex_t ctrl, - void *ctrlData); + DRXStatus_t DRX_Ctrl(pDRXDemodInstance_t demod, + DRXCtrlIndex_t ctrl, void *ctrlData); /*------------------------------------------------------------------------- THE END @@ -2585,4 +2719,4 @@ THE END #ifdef __cplusplus } #endif -#endif /* __DRXDRIVER_H__ */ +#endif /* __DRXDRIVER_H__ */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver_version.h b/drivers/media/dvb-frontends/drx39xyj/drx_driver_version.h index fd2b278..dda9398 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver_version.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver_version.h @@ -53,10 +53,9 @@ extern "C" { #ifdef _REGISTERTABLE_ #include -extern RegisterTable_t drx_driver_version[]; -extern RegisterTableInfo_t drx_driver_version_info[]; -#endif /* _REGISTERTABLE_ */ - + extern RegisterTable_t drx_driver_version[]; + extern RegisterTableInfo_t drx_driver_version_info[]; +#endif /* _REGISTERTABLE_ */ /* *============================================================================== @@ -73,9 +72,7 @@ extern RegisterTableInfo_t drx_driver_version_info[]; #ifdef __cplusplus } #endif - -#endif /* __DRX_DRIVER_VERSION__H__ */ - +#endif /* __DRX_DRIVER_VERSION__H__ */ /* * End of file (drx_driver_version.h) ******************************************************************************* diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index b4c70ac..ddfde42 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -47,7 +47,6 @@ INCLUDE FILES #include "drxj_options.h" #endif - /*============================================================================*/ /*=== DEFINES ================================================================*/ /*============================================================================*/ @@ -280,30 +279,30 @@ DEFINES * \brief SCU */ #define DRX_SCU_READY 0 -#define DRXJ_MAX_WAITTIME 100 /* ms */ -#define FEC_RS_MEASUREMENT_PERIOD 12894 /* 1 sec */ -#define FEC_RS_MEASUREMENT_PRESCALE 1 /* n sec */ +#define DRXJ_MAX_WAITTIME 100 /* ms */ +#define FEC_RS_MEASUREMENT_PERIOD 12894 /* 1 sec */ +#define FEC_RS_MEASUREMENT_PRESCALE 1 /* n sec */ /** * \def DRX_AUD_MAX_DEVIATION * \brief Needed for calculation of prescale feature in AUD */ #ifndef DRXJ_AUD_MAX_FM_DEVIATION -#define DRXJ_AUD_MAX_FM_DEVIATION 100 /* kHz */ +#define DRXJ_AUD_MAX_FM_DEVIATION 100 /* kHz */ #endif /** * \brief Needed for calculation of NICAM prescale feature in AUD */ #ifndef DRXJ_AUD_MAX_NICAM_PRESCALE -#define DRXJ_AUD_MAX_NICAM_PRESCALE (9) /* dB */ +#define DRXJ_AUD_MAX_NICAM_PRESCALE (9) /* dB */ #endif /** * \brief Needed for calculation of NICAM prescale feature in AUD */ #ifndef DRXJ_AUD_MAX_WAITTIME -#define DRXJ_AUD_MAX_WAITTIME 250 /* ms */ +#define DRXJ_AUD_MAX_WAITTIME 250 /* ms */ #endif /* ATV config changed flags */ @@ -448,17 +447,16 @@ DEFINES * \brief Needed for calculation of prescale feature in AUD */ #ifndef DRX_AUD_MAX_FM_DEVIATION -#define DRX_AUD_MAX_FM_DEVIATION (100) /* kHz */ +#define DRX_AUD_MAX_FM_DEVIATION (100) /* kHz */ #endif /** * \brief Needed for calculation of NICAM prescale feature in AUD */ #ifndef DRX_AUD_MAX_NICAM_PRESCALE -#define DRX_AUD_MAX_NICAM_PRESCALE (9) /* dB */ +#define DRX_AUD_MAX_NICAM_PRESCALE (9) /* dB */ #endif - /*============================================================================*/ /* Values for I2S Master/Slave pin configurations */ #define SIO_PDR_I2S_CL_CFG_MODE__MASTER 0x0004 @@ -588,11 +586,10 @@ DEFINES /*----------------------------------------------------------------------------- STATIC VARIABLES ----------------------------------------------------------------------------*/ -DRXStatus_t DRXJ_Open ( pDRXDemodInstance_t demod ); -DRXStatus_t DRXJ_Close ( pDRXDemodInstance_t demod); -DRXStatus_t DRXJ_Ctrl ( pDRXDemodInstance_t demod, - DRXCtrlIndex_t ctrl, - void *ctrlData); +DRXStatus_t DRXJ_Open(pDRXDemodInstance_t demod); +DRXStatus_t DRXJ_Close(pDRXDemodInstance_t demod); +DRXStatus_t DRXJ_Ctrl(pDRXDemodInstance_t demod, + DRXCtrlIndex_t ctrl, void *ctrlData); /*----------------------------------------------------------------------------- GLOBAL VARIABLES @@ -601,170 +598,146 @@ GLOBAL VARIABLES * DRXJ DAP structures */ -static DRXStatus_t DRXJ_DAP_ReadBlock ( - pI2CDeviceAddr_t devAddr, - DRXaddr_t addr, - u16_t datasize, - pu8_t data, - DRXflags_t flags); - -static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg8 ( - pI2CDeviceAddr_t devAddr, - DRXaddr_t waddr, - DRXaddr_t raddr, - u8_t wdata, - pu8_t rdata); - -static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg16 ( - pI2CDeviceAddr_t devAddr, - DRXaddr_t waddr, - DRXaddr_t raddr, - u16_t wdata, - pu16_t rdata); - -static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg32 ( - pI2CDeviceAddr_t devAddr, - DRXaddr_t waddr, - DRXaddr_t raddr, - u32_t wdata, - pu32_t rdata); - -static DRXStatus_t DRXJ_DAP_ReadReg8 ( - pI2CDeviceAddr_t devAddr, - DRXaddr_t addr, - pu8_t data, - DRXflags_t flags); - -static DRXStatus_t DRXJ_DAP_ReadReg16 ( - pI2CDeviceAddr_t devAddr, - DRXaddr_t addr, - pu16_t data, - DRXflags_t flags); - -static DRXStatus_t DRXJ_DAP_ReadReg32 ( - pI2CDeviceAddr_t devAddr, - DRXaddr_t addr, - pu32_t data, - DRXflags_t flags); - -static DRXStatus_t DRXJ_DAP_WriteBlock ( - pI2CDeviceAddr_t devAddr, - DRXaddr_t addr, - u16_t datasize, - pu8_t data, - DRXflags_t flags); - -static DRXStatus_t DRXJ_DAP_WriteReg8 ( - pI2CDeviceAddr_t devAddr, - DRXaddr_t addr, - u8_t data, - DRXflags_t flags); - -static DRXStatus_t DRXJ_DAP_WriteReg16 ( - pI2CDeviceAddr_t devAddr, - DRXaddr_t addr, - u16_t data, - DRXflags_t flags); - -static DRXStatus_t DRXJ_DAP_WriteReg32 ( - pI2CDeviceAddr_t devAddr, - DRXaddr_t addr, - u32_t data, - DRXflags_t flags); +static DRXStatus_t DRXJ_DAP_ReadBlock(pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + u16_t datasize, + pu8_t data, DRXflags_t flags); + +static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg8(pI2CDeviceAddr_t devAddr, + DRXaddr_t waddr, + DRXaddr_t raddr, + u8_t wdata, pu8_t rdata); + +static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg16(pI2CDeviceAddr_t devAddr, + DRXaddr_t waddr, + DRXaddr_t raddr, + u16_t wdata, pu16_t rdata); + +static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg32(pI2CDeviceAddr_t devAddr, + DRXaddr_t waddr, + DRXaddr_t raddr, + u32_t wdata, pu32_t rdata); + +static DRXStatus_t DRXJ_DAP_ReadReg8(pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + pu8_t data, DRXflags_t flags); + +static DRXStatus_t DRXJ_DAP_ReadReg16(pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + pu16_t data, DRXflags_t flags); + +static DRXStatus_t DRXJ_DAP_ReadReg32(pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + pu32_t data, DRXflags_t flags); + +static DRXStatus_t DRXJ_DAP_WriteBlock(pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + u16_t datasize, + pu8_t data, DRXflags_t flags); + +static DRXStatus_t DRXJ_DAP_WriteReg8(pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + u8_t data, DRXflags_t flags); + +static DRXStatus_t DRXJ_DAP_WriteReg16(pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + u16_t data, DRXflags_t flags); + +static DRXStatus_t DRXJ_DAP_WriteReg32(pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + u32_t data, DRXflags_t flags); /* The version structure of this protocol implementation */ -char drxDapDRXJModuleName[] = "DRXJ Data Access Protocol"; +char drxDapDRXJModuleName[] = "DRXJ Data Access Protocol"; char drxDapDRXJVersionText[] = "0.0.0"; DRXVersion_t drxDapDRXJVersion = { - DRX_MODULE_DAP, /**< type identifier of the module */ - drxDapDRXJModuleName, /**< name or description of module */ + DRX_MODULE_DAP, /**< type identifier of the module */ + drxDapDRXJModuleName, /**< name or description of module */ - 0, /**< major version number */ - 0, /**< minor version number */ - 0, /**< patch version number */ - drxDapDRXJVersionText /**< version as text string */ + 0, /**< major version number */ + 0, /**< minor version number */ + 0, /**< patch version number */ + drxDapDRXJVersionText /**< version as text string */ }; /* The structure containing the protocol interface */ DRXAccessFunc_t drxDapDRXJFunct_g = { - &drxDapDRXJVersion, - DRXJ_DAP_WriteBlock, /* Supported */ - DRXJ_DAP_ReadBlock, /* Supported */ - DRXJ_DAP_WriteReg8, /* Not supported */ - DRXJ_DAP_ReadReg8, /* Not supported */ - DRXJ_DAP_ReadModifyWriteReg8, /* Not supported */ - DRXJ_DAP_WriteReg16, /* Supported */ - DRXJ_DAP_ReadReg16, /* Supported */ - DRXJ_DAP_ReadModifyWriteReg16, /* Supported */ - DRXJ_DAP_WriteReg32, /* Supported */ - DRXJ_DAP_ReadReg32, /* Supported */ - DRXJ_DAP_ReadModifyWriteReg32, /* Not supported */ + &drxDapDRXJVersion, + DRXJ_DAP_WriteBlock, /* Supported */ + DRXJ_DAP_ReadBlock, /* Supported */ + DRXJ_DAP_WriteReg8, /* Not supported */ + DRXJ_DAP_ReadReg8, /* Not supported */ + DRXJ_DAP_ReadModifyWriteReg8, /* Not supported */ + DRXJ_DAP_WriteReg16, /* Supported */ + DRXJ_DAP_ReadReg16, /* Supported */ + DRXJ_DAP_ReadModifyWriteReg16, /* Supported */ + DRXJ_DAP_WriteReg32, /* Supported */ + DRXJ_DAP_ReadReg32, /* Supported */ + DRXJ_DAP_ReadModifyWriteReg32, /* Not supported */ }; /** * /var DRXJ_Func_g * /brief The driver functions of the drxj */ -DRXDemodFunc_t DRXJFunctions_g = -{ - DRXJ_TYPE_ID, - DRXJ_Open, - DRXJ_Close, - DRXJ_Ctrl +DRXDemodFunc_t DRXJFunctions_g = { + DRXJ_TYPE_ID, + DRXJ_Open, + DRXJ_Close, + DRXJ_Ctrl }; -DRXJData_t DRXJData_g = -{ - FALSE, /* hasLNA : TRUE if LNA (aka PGA) present */ - FALSE, /* hasOOB : TRUE if OOB supported */ - FALSE, /* hasNTSC: TRUE if NTSC supported */ - FALSE, /* hasBTSC: TRUE if BTSC supported */ - FALSE, /* hasSMATX: TRUE if SMA_TX pin is available */ - FALSE, /* hasSMARX: TRUE if SMA_RX pin is available */ - FALSE, /* hasGPIO : TRUE if GPIO pin is available */ - FALSE, /* hasIRQN : TRUE if IRQN pin is available */ - 0, /* mfx A1/A2/A... */ - - /* tuner settings */ - FALSE, /* tuner mirrors RF signal */ - /* standard/channel settings */ - DRX_STANDARD_UNKNOWN, /* current standard */ - DRX_CONSTELLATION_AUTO, /* constellation */ - 0, /* frequency in KHz */ - DRX_BANDWIDTH_UNKNOWN, /* currBandwidth */ - DRX_MIRROR_NO, /* mirror */ - - /* signal quality information: */ - /* default values taken from the QAM Programming guide */ - /* fecBitsDesired should not be less than 4000000 */ - 4000000, /* fecBitsDesired */ - 5, /* fecVdPlen */ - 4, /* qamVdPrescale */ - 0xFFFF, /* qamVDPeriod */ - 204*8, /* fecRsPlen annex A */ - 1, /* fecRsPrescale */ - FEC_RS_MEASUREMENT_PERIOD,/* fecRsPeriod */ - TRUE, /* resetPktErrAcc */ - 0, /* pktErrAccStart */ - - /* HI configuration */ - 0, /* HICfgTimingDiv */ - 0, /* HICfgBridgeDelay */ - 0, /* HICfgWakeUpKey */ - 0, /* HICfgCtrl */ - 0, /* HICfgTimeout */ - /* UIO configuartion */ - DRX_UIO_MODE_DISABLE, /* uioSmaRxMode */ - DRX_UIO_MODE_DISABLE, /* uioSmaTxMode */ - DRX_UIO_MODE_DISABLE, /* uioASELMode */ - DRX_UIO_MODE_DISABLE, /* uioIRQNMode */ - /* FS setting */ - 0UL, /* iqmFsRateOfs */ - FALSE, /* posImage */ - /* RC setting */ - 0UL, /* iqmRcRateOfs */ - /* AUD information */ +DRXJData_t DRXJData_g = { + FALSE, /* hasLNA : TRUE if LNA (aka PGA) present */ + FALSE, /* hasOOB : TRUE if OOB supported */ + FALSE, /* hasNTSC: TRUE if NTSC supported */ + FALSE, /* hasBTSC: TRUE if BTSC supported */ + FALSE, /* hasSMATX: TRUE if SMA_TX pin is available */ + FALSE, /* hasSMARX: TRUE if SMA_RX pin is available */ + FALSE, /* hasGPIO : TRUE if GPIO pin is available */ + FALSE, /* hasIRQN : TRUE if IRQN pin is available */ + 0, /* mfx A1/A2/A... */ + + /* tuner settings */ + FALSE, /* tuner mirrors RF signal */ + /* standard/channel settings */ + DRX_STANDARD_UNKNOWN, /* current standard */ + DRX_CONSTELLATION_AUTO, /* constellation */ + 0, /* frequency in KHz */ + DRX_BANDWIDTH_UNKNOWN, /* currBandwidth */ + DRX_MIRROR_NO, /* mirror */ + + /* signal quality information: */ + /* default values taken from the QAM Programming guide */ + /* fecBitsDesired should not be less than 4000000 */ + 4000000, /* fecBitsDesired */ + 5, /* fecVdPlen */ + 4, /* qamVdPrescale */ + 0xFFFF, /* qamVDPeriod */ + 204 * 8, /* fecRsPlen annex A */ + 1, /* fecRsPrescale */ + FEC_RS_MEASUREMENT_PERIOD, /* fecRsPeriod */ + TRUE, /* resetPktErrAcc */ + 0, /* pktErrAccStart */ + + /* HI configuration */ + 0, /* HICfgTimingDiv */ + 0, /* HICfgBridgeDelay */ + 0, /* HICfgWakeUpKey */ + 0, /* HICfgCtrl */ + 0, /* HICfgTimeout */ + /* UIO configuartion */ + DRX_UIO_MODE_DISABLE, /* uioSmaRxMode */ + DRX_UIO_MODE_DISABLE, /* uioSmaTxMode */ + DRX_UIO_MODE_DISABLE, /* uioASELMode */ + DRX_UIO_MODE_DISABLE, /* uioIRQNMode */ + /* FS setting */ + 0UL, /* iqmFsRateOfs */ + FALSE, /* posImage */ + /* RC setting */ + 0UL, /* iqmRcRateOfs */ + /* AUD information */ /* FALSE, * flagSetAUDdone */ /* FALSE, * detectedRDS */ /* TRUE, * flagASDRequest */ @@ -775,207 +748,201 @@ DRXJData_t DRXJData_g = /*#ifdef DRXJ_SPLIT_UCODE_UPLOAD FALSE, * flagAudMcUploaded */ /*#endif * DRXJ_SPLIT_UCODE_UPLOAD */ - /* ATV configuartion */ - 0UL, /* flags cfg changes */ - /* shadow of ATV_TOP_EQU0__A */ - {-5, - ATV_TOP_EQU0_EQU_C0_FM, - ATV_TOP_EQU0_EQU_C0_L, - ATV_TOP_EQU0_EQU_C0_LP, - ATV_TOP_EQU0_EQU_C0_BG, - ATV_TOP_EQU0_EQU_C0_DK, - ATV_TOP_EQU0_EQU_C0_I - }, - /* shadow of ATV_TOP_EQU1__A */ - {-50, - ATV_TOP_EQU1_EQU_C1_FM, - ATV_TOP_EQU1_EQU_C1_L, - ATV_TOP_EQU1_EQU_C1_LP, - ATV_TOP_EQU1_EQU_C1_BG, - ATV_TOP_EQU1_EQU_C1_DK, - ATV_TOP_EQU1_EQU_C1_I - }, - /* shadow of ATV_TOP_EQU2__A */ - {210, - ATV_TOP_EQU2_EQU_C2_FM, - ATV_TOP_EQU2_EQU_C2_L, - ATV_TOP_EQU2_EQU_C2_LP, - ATV_TOP_EQU2_EQU_C2_BG, - ATV_TOP_EQU2_EQU_C2_DK, - ATV_TOP_EQU2_EQU_C2_I - }, - /* shadow of ATV_TOP_EQU3__A */ - {-160, - ATV_TOP_EQU3_EQU_C3_FM, - ATV_TOP_EQU3_EQU_C3_L, - ATV_TOP_EQU3_EQU_C3_LP, - ATV_TOP_EQU3_EQU_C3_BG, - ATV_TOP_EQU3_EQU_C3_DK, - ATV_TOP_EQU3_EQU_C3_I - }, - FALSE, /* flag: TRUE=bypass */ - ATV_TOP_VID_PEAK__PRE, /* shadow of ATV_TOP_VID_PEAK__A */ - ATV_TOP_NOISE_TH__PRE, /* shadow of ATV_TOP_NOISE_TH__A */ - TRUE, /* flag CVBS ouput enable */ - FALSE, /* flag SIF ouput enable */ - DRXJ_SIF_ATTENUATION_0DB, /* current SIF att setting */ - { /* qamRfAgcCfg */ - DRX_STANDARD_ITU_B, /* standard */ - DRX_AGC_CTRL_AUTO, /* ctrlMode */ - 0, /* outputLevel */ - 0, /* minOutputLevel */ - 0xFFFF, /* maxOutputLevel */ - 0x0000, /* speed */ - 0x0000, /* top */ - 0x0000 /* c.o.c. */ - }, - { /* qamIfAgcCfg */ - DRX_STANDARD_ITU_B, /* standard */ - DRX_AGC_CTRL_AUTO, /* ctrlMode */ - 0, /* outputLevel */ - 0, /* minOutputLevel */ - 0xFFFF, /* maxOutputLevel */ - 0x0000, /* speed */ - 0x0000, /* top (don't care) */ - 0x0000 /* c.o.c. (don't care) */ - }, - { /* vsbRfAgcCfg */ - DRX_STANDARD_8VSB, /* standard */ - DRX_AGC_CTRL_AUTO, /* ctrlMode */ - 0, /* outputLevel */ - 0, /* minOutputLevel */ - 0xFFFF, /* maxOutputLevel */ - 0x0000, /* speed */ - 0x0000, /* top (don't care) */ - 0x0000 /* c.o.c. (don't care) */ - }, - { /* vsbIfAgcCfg */ - DRX_STANDARD_8VSB, /* standard */ - DRX_AGC_CTRL_AUTO, /* ctrlMode */ - 0, /* outputLevel */ - 0, /* minOutputLevel */ - 0xFFFF, /* maxOutputLevel */ - 0x0000, /* speed */ - 0x0000, /* top (don't care) */ - 0x0000 /* c.o.c. (don't care) */ - }, - 0, /* qamPgaCfg */ - 0, /* vsbPgaCfg */ - { /* qamPreSawCfg */ - DRX_STANDARD_ITU_B, /* standard */ - 0, /* reference */ - FALSE /* usePreSaw */ - }, - { /* vsbPreSawCfg */ - DRX_STANDARD_8VSB, /* standard */ - 0, /* reference */ - FALSE /* usePreSaw */ - }, - - /* Version information */ + /* ATV configuartion */ + 0UL, /* flags cfg changes */ + /* shadow of ATV_TOP_EQU0__A */ + {-5, + ATV_TOP_EQU0_EQU_C0_FM, + ATV_TOP_EQU0_EQU_C0_L, + ATV_TOP_EQU0_EQU_C0_LP, + ATV_TOP_EQU0_EQU_C0_BG, + ATV_TOP_EQU0_EQU_C0_DK, + ATV_TOP_EQU0_EQU_C0_I}, + /* shadow of ATV_TOP_EQU1__A */ + {-50, + ATV_TOP_EQU1_EQU_C1_FM, + ATV_TOP_EQU1_EQU_C1_L, + ATV_TOP_EQU1_EQU_C1_LP, + ATV_TOP_EQU1_EQU_C1_BG, + ATV_TOP_EQU1_EQU_C1_DK, + ATV_TOP_EQU1_EQU_C1_I}, + /* shadow of ATV_TOP_EQU2__A */ + {210, + ATV_TOP_EQU2_EQU_C2_FM, + ATV_TOP_EQU2_EQU_C2_L, + ATV_TOP_EQU2_EQU_C2_LP, + ATV_TOP_EQU2_EQU_C2_BG, + ATV_TOP_EQU2_EQU_C2_DK, + ATV_TOP_EQU2_EQU_C2_I}, + /* shadow of ATV_TOP_EQU3__A */ + {-160, + ATV_TOP_EQU3_EQU_C3_FM, + ATV_TOP_EQU3_EQU_C3_L, + ATV_TOP_EQU3_EQU_C3_LP, + ATV_TOP_EQU3_EQU_C3_BG, + ATV_TOP_EQU3_EQU_C3_DK, + ATV_TOP_EQU3_EQU_C3_I}, + FALSE, /* flag: TRUE=bypass */ + ATV_TOP_VID_PEAK__PRE, /* shadow of ATV_TOP_VID_PEAK__A */ + ATV_TOP_NOISE_TH__PRE, /* shadow of ATV_TOP_NOISE_TH__A */ + TRUE, /* flag CVBS ouput enable */ + FALSE, /* flag SIF ouput enable */ + DRXJ_SIF_ATTENUATION_0DB, /* current SIF att setting */ + { /* qamRfAgcCfg */ + DRX_STANDARD_ITU_B, /* standard */ + DRX_AGC_CTRL_AUTO, /* ctrlMode */ + 0, /* outputLevel */ + 0, /* minOutputLevel */ + 0xFFFF, /* maxOutputLevel */ + 0x0000, /* speed */ + 0x0000, /* top */ + 0x0000 /* c.o.c. */ + }, + { /* qamIfAgcCfg */ + DRX_STANDARD_ITU_B, /* standard */ + DRX_AGC_CTRL_AUTO, /* ctrlMode */ + 0, /* outputLevel */ + 0, /* minOutputLevel */ + 0xFFFF, /* maxOutputLevel */ + 0x0000, /* speed */ + 0x0000, /* top (don't care) */ + 0x0000 /* c.o.c. (don't care) */ + }, + { /* vsbRfAgcCfg */ + DRX_STANDARD_8VSB, /* standard */ + DRX_AGC_CTRL_AUTO, /* ctrlMode */ + 0, /* outputLevel */ + 0, /* minOutputLevel */ + 0xFFFF, /* maxOutputLevel */ + 0x0000, /* speed */ + 0x0000, /* top (don't care) */ + 0x0000 /* c.o.c. (don't care) */ + }, + { /* vsbIfAgcCfg */ + DRX_STANDARD_8VSB, /* standard */ + DRX_AGC_CTRL_AUTO, /* ctrlMode */ + 0, /* outputLevel */ + 0, /* minOutputLevel */ + 0xFFFF, /* maxOutputLevel */ + 0x0000, /* speed */ + 0x0000, /* top (don't care) */ + 0x0000 /* c.o.c. (don't care) */ + }, + 0, /* qamPgaCfg */ + 0, /* vsbPgaCfg */ + { /* qamPreSawCfg */ + DRX_STANDARD_ITU_B, /* standard */ + 0, /* reference */ + FALSE /* usePreSaw */ + }, + { /* vsbPreSawCfg */ + DRX_STANDARD_8VSB, /* standard */ + 0, /* reference */ + FALSE /* usePreSaw */ + }, + + /* Version information */ #ifndef _CH_ - { - "01234567890", /* human readable version microcode */ - "01234567890" /* human readable version device specific code */ - }, - { - { /* DRXVersion_t for microcode */ - DRX_MODULE_UNKNOWN, - (char*)(NULL), - 0, - 0, - 0, - (char*)(NULL) - }, - { /* DRXVersion_t for device specific code */ - DRX_MODULE_UNKNOWN, - (char*)(NULL), - 0, - 0, - 0, - (char*)(NULL) - } - }, - { - { /* DRXVersionList_t for microcode */ - (pDRXVersion_t)(NULL), - (pDRXVersionList_t)(NULL) - }, - { /* DRXVersionList_t for device specific code */ - (pDRXVersion_t)(NULL), - (pDRXVersionList_t)(NULL) - } - }, + { + "01234567890", /* human readable version microcode */ + "01234567890" /* human readable version device specific code */ + }, + { + { /* DRXVersion_t for microcode */ + DRX_MODULE_UNKNOWN, + (char *)(NULL), + 0, + 0, + 0, + (char *)(NULL) + }, + { /* DRXVersion_t for device specific code */ + DRX_MODULE_UNKNOWN, + (char *)(NULL), + 0, + 0, + 0, + (char *)(NULL) + } + }, + { + { /* DRXVersionList_t for microcode */ + (pDRXVersion_t) (NULL), + (pDRXVersionList_t) (NULL) + }, + { /* DRXVersionList_t for device specific code */ + (pDRXVersion_t) (NULL), + (pDRXVersionList_t) (NULL) + } + }, #endif - FALSE, /* smartAntInverted */ - /* Tracking filter setting for OOB */ - { - 12000, - 9300, - 6600, - 5280, - 3700, - 3000, - 2000, - 0 - }, - FALSE, /* oobPowerOn */ - 0, /* mpegTsStaticBitrate */ - FALSE, /* disableTEIhandling */ - FALSE, /* bitReverseMpegOutout */ - DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO, /* mpegOutputClockRate */ - DRXJ_MPEG_START_WIDTH_1CLKCYC, /* mpegStartWidth */ - - /* Pre SAW & Agc configuration for ATV */ - { - DRX_STANDARD_NTSC, /* standard */ - 7, /* reference */ - TRUE /* usePreSaw */ - }, - { /* ATV RF-AGC */ - DRX_STANDARD_NTSC, /* standard */ - DRX_AGC_CTRL_AUTO, /* ctrlMode */ - 0, /* outputLevel */ - 0, /* minOutputLevel (d.c.) */ - 0, /* maxOutputLevel (d.c.) */ - 3, /* speed */ - 9500, /* top */ - 4000 /* cut-off current */ - }, - { /* ATV IF-AGC */ - DRX_STANDARD_NTSC, /* standard */ - DRX_AGC_CTRL_AUTO, /* ctrlMode */ - 0, /* outputLevel */ - 0, /* minOutputLevel (d.c.) */ - 0, /* maxOutputLevel (d.c.) */ - 3, /* speed */ - 2400, /* top */ - 0 /* c.o.c. (d.c.) */ - }, - 140, /* ATV PGA config */ - 0, /* currSymbolRate */ - - FALSE, /* pdrSafeMode */ - SIO_PDR_GPIO_CFG__PRE, /* pdrSafeRestoreValGpio */ - SIO_PDR_VSYNC_CFG__PRE, /* pdrSafeRestoreValVSync */ - SIO_PDR_SMA_RX_CFG__PRE, /* pdrSafeRestoreValSmaRx */ - SIO_PDR_SMA_TX_CFG__PRE, /* pdrSafeRestoreValSmaTx */ - - 4, /* oobPreSaw */ - DRXJ_OOB_LO_POW_MINUS10DB, /* oobLoPow */ - { - FALSE /* audData, only first member */ - }, + FALSE, /* smartAntInverted */ + /* Tracking filter setting for OOB */ + { + 12000, + 9300, + 6600, + 5280, + 3700, + 3000, + 2000, + 0}, + FALSE, /* oobPowerOn */ + 0, /* mpegTsStaticBitrate */ + FALSE, /* disableTEIhandling */ + FALSE, /* bitReverseMpegOutout */ + DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO, /* mpegOutputClockRate */ + DRXJ_MPEG_START_WIDTH_1CLKCYC, /* mpegStartWidth */ + + /* Pre SAW & Agc configuration for ATV */ + { + DRX_STANDARD_NTSC, /* standard */ + 7, /* reference */ + TRUE /* usePreSaw */ + }, + { /* ATV RF-AGC */ + DRX_STANDARD_NTSC, /* standard */ + DRX_AGC_CTRL_AUTO, /* ctrlMode */ + 0, /* outputLevel */ + 0, /* minOutputLevel (d.c.) */ + 0, /* maxOutputLevel (d.c.) */ + 3, /* speed */ + 9500, /* top */ + 4000 /* cut-off current */ + }, + { /* ATV IF-AGC */ + DRX_STANDARD_NTSC, /* standard */ + DRX_AGC_CTRL_AUTO, /* ctrlMode */ + 0, /* outputLevel */ + 0, /* minOutputLevel (d.c.) */ + 0, /* maxOutputLevel (d.c.) */ + 3, /* speed */ + 2400, /* top */ + 0 /* c.o.c. (d.c.) */ + }, + 140, /* ATV PGA config */ + 0, /* currSymbolRate */ + + FALSE, /* pdrSafeMode */ + SIO_PDR_GPIO_CFG__PRE, /* pdrSafeRestoreValGpio */ + SIO_PDR_VSYNC_CFG__PRE, /* pdrSafeRestoreValVSync */ + SIO_PDR_SMA_RX_CFG__PRE, /* pdrSafeRestoreValSmaRx */ + SIO_PDR_SMA_TX_CFG__PRE, /* pdrSafeRestoreValSmaTx */ + + 4, /* oobPreSaw */ + DRXJ_OOB_LO_POW_MINUS10DB, /* oobLoPow */ + { + FALSE /* audData, only first member */ + }, }; - /** * \var DRXJDefaultAddr_g * \brief Default I2C address and device identifier. */ I2CDeviceAddr_t DRXJDefaultAddr_g = { - DRXJ_DEF_I2C_ADDR, /* i2c address */ - DRXJ_DEF_DEMOD_DEV_ID /* device id */ + DRXJ_DEF_I2C_ADDR, /* i2c address */ + DRXJ_DEF_DEMOD_DEV_ID /* device id */ }; /** @@ -983,73 +950,71 @@ I2CDeviceAddr_t DRXJDefaultAddr_g = { * \brief Default common attributes of a drxj demodulator instance. */ DRXCommonAttr_t DRXJDefaultCommAttr_g = { - (pu8_t)NULL, /* ucode ptr */ - 0, /* ucode size */ - TRUE, /* ucode verify switch */ - { 0 }, /* version record */ - - 44000, /* IF in kHz in case no tuner instance is used */ - (151875-0), /* system clock frequency in kHz */ - 0, /* oscillator frequency kHz */ - 0, /* oscillator deviation in ppm, signed */ - FALSE, /* If TRUE mirror frequency spectrum */ - { - /* MPEG output configuration */ - TRUE, /* If TRUE, enable MPEG ouput */ - FALSE, /* If TRUE, insert RS byte */ - TRUE, /* If TRUE, parallel out otherwise serial */ - FALSE, /* If TRUE, invert DATA signals */ - FALSE, /* If TRUE, invert ERR signal */ - FALSE, /* If TRUE, invert STR signals */ - FALSE, /* If TRUE, invert VAL signals */ - FALSE, /* If TRUE, invert CLK signals */ - TRUE, /* If TRUE, static MPEG clockrate will - be used, otherwise clockrate will - adapt to the bitrate of the TS */ - 19392658UL, /* Maximum bitrate in b/s in case - static clockrate is selected */ - DRX_MPEG_STR_WIDTH_1 /* MPEG Start width in clock cycles */ - }, - /* Initilisations below can be ommited, they require no user input and - are initialy 0, NULL or FALSE. The compiler will initialize them to these - values when ommited. */ - FALSE, /* isOpened */ - - /* SCAN */ - NULL, /* no scan params yet */ - 0, /* current scan index */ - 0, /* next scan frequency */ - FALSE, /* scan ready flag */ - 0, /* max channels to scan */ - 0, /* nr of channels scanned */ - NULL, /* default scan function */ - NULL, /* default context pointer */ - 0, /* millisec to wait for demod lock */ - DRXJ_DEMOD_LOCK, /* desired lock */ - FALSE, - - /* Power management */ - DRX_POWER_UP, - - /* Tuner */ - 1, /* nr of I2C port to wich tuner is */ - 0L, /* minimum RF input frequency, in kHz */ - 0L, /* maximum RF input frequency, in kHz */ - FALSE, /* Rf Agc Polarity */ - FALSE, /* If Agc Polarity */ - FALSE, /* tuner slow mode */ - - - { /* current channel (all 0) */ - 0UL /* channel.frequency */ - }, - DRX_STANDARD_UNKNOWN, /* current standard */ - DRX_STANDARD_UNKNOWN, /* previous standard */ - DRX_STANDARD_UNKNOWN, /* diCacheStandard */ - FALSE, /* useBootloader */ - 0UL, /* capabilities */ - 0 /* mfx */ - + (pu8_t) NULL, /* ucode ptr */ + 0, /* ucode size */ + TRUE, /* ucode verify switch */ + {0}, /* version record */ + + 44000, /* IF in kHz in case no tuner instance is used */ + (151875 - 0), /* system clock frequency in kHz */ + 0, /* oscillator frequency kHz */ + 0, /* oscillator deviation in ppm, signed */ + FALSE, /* If TRUE mirror frequency spectrum */ + { + /* MPEG output configuration */ + TRUE, /* If TRUE, enable MPEG ouput */ + FALSE, /* If TRUE, insert RS byte */ + TRUE, /* If TRUE, parallel out otherwise serial */ + FALSE, /* If TRUE, invert DATA signals */ + FALSE, /* If TRUE, invert ERR signal */ + FALSE, /* If TRUE, invert STR signals */ + FALSE, /* If TRUE, invert VAL signals */ + FALSE, /* If TRUE, invert CLK signals */ + TRUE, /* If TRUE, static MPEG clockrate will + be used, otherwise clockrate will + adapt to the bitrate of the TS */ + 19392658UL, /* Maximum bitrate in b/s in case + static clockrate is selected */ + DRX_MPEG_STR_WIDTH_1 /* MPEG Start width in clock cycles */ + }, + /* Initilisations below can be ommited, they require no user input and + are initialy 0, NULL or FALSE. The compiler will initialize them to these + values when ommited. */ + FALSE, /* isOpened */ + + /* SCAN */ + NULL, /* no scan params yet */ + 0, /* current scan index */ + 0, /* next scan frequency */ + FALSE, /* scan ready flag */ + 0, /* max channels to scan */ + 0, /* nr of channels scanned */ + NULL, /* default scan function */ + NULL, /* default context pointer */ + 0, /* millisec to wait for demod lock */ + DRXJ_DEMOD_LOCK, /* desired lock */ + FALSE, + + /* Power management */ + DRX_POWER_UP, + + /* Tuner */ + 1, /* nr of I2C port to wich tuner is */ + 0L, /* minimum RF input frequency, in kHz */ + 0L, /* maximum RF input frequency, in kHz */ + FALSE, /* Rf Agc Polarity */ + FALSE, /* If Agc Polarity */ + FALSE, /* tuner slow mode */ + + { /* current channel (all 0) */ + 0UL /* channel.frequency */ + }, + DRX_STANDARD_UNKNOWN, /* current standard */ + DRX_STANDARD_UNKNOWN, /* previous standard */ + DRX_STANDARD_UNKNOWN, /* diCacheStandard */ + FALSE, /* useBootloader */ + 0UL, /* capabilities */ + 0 /* mfx */ }; /** @@ -1057,12 +1022,12 @@ DRXCommonAttr_t DRXJDefaultCommAttr_g = { * \brief Default drxj demodulator instance. */ DRXDemodInstance_t DRXJDefaultDemod_g = { - &DRXJFunctions_g, /* demod functions */ - &DRXJ_DAP, /* data access protocol functions */ - NULL, /* tuner instance */ - &DRXJDefaultAddr_g, /* i2c address & device id */ - &DRXJDefaultCommAttr_g, /* demod common attributes */ - &DRXJData_g /* demod device specific attributes */ + &DRXJFunctions_g, /* demod functions */ + &DRXJ_DAP, /* data access protocol functions */ + NULL, /* tuner instance */ + &DRXJDefaultAddr_g, /* i2c address & device id */ + &DRXJDefaultCommAttr_g, /* demod common attributes */ + &DRXJData_g /* demod device specific attributes */ }; /** @@ -1071,96 +1036,94 @@ DRXDemodInstance_t DRXJDefaultDemod_g = { * This structure is DRXK specific. * */ -DRXAudData_t DRXJDefaultAudData_g = -{ - FALSE, /* audioIsActive */ - DRX_AUD_STANDARD_AUTO, /* audioStandard */ +DRXAudData_t DRXJDefaultAudData_g = { + FALSE, /* audioIsActive */ + DRX_AUD_STANDARD_AUTO, /* audioStandard */ - /* i2sdata */ - { - FALSE, /* outputEnable */ - 48000, /* frequency */ - DRX_I2S_MODE_MASTER, /* mode */ - DRX_I2S_WORDLENGTH_32, /* wordLength */ - DRX_I2S_POLARITY_RIGHT, /* polarity */ - DRX_I2S_FORMAT_WS_WITH_DATA /* format */ - }, - /* volume */ - { - TRUE, /* mute; */ - 0, /* volume */ - DRX_AUD_AVC_OFF , /* avcMode */ - 0, /* avcRefLevel */ - DRX_AUD_AVC_MAX_GAIN_12DB, /* avcMaxGain */ - DRX_AUD_AVC_MAX_ATTEN_24DB, /* avcMaxAtten */ - 0, /* strengthLeft */ - 0 /* strengthRight */ - }, - DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON,/* autoSound */ - /* assThresholds */ - { - 440, /* A2 */ - 12, /* BTSC */ - 700, /* NICAM */ - }, - /* carrier */ - { - /* a */ - { - 42, /* thres */ - DRX_NO_CARRIER_NOISE, /* opt */ - 0, /* shift */ - 0 /* dco */ - }, - /* b */ - { - 42, /* thres */ - DRX_NO_CARRIER_MUTE, /* opt */ - 0, /* shift */ - 0 /* dco */ - }, - - }, - /* mixer */ - { - DRX_AUD_SRC_STEREO_OR_A, /* sourceI2S */ - DRX_AUD_I2S_MATRIX_STEREO, /* matrixI2S */ - DRX_AUD_FM_MATRIX_SOUND_A /* matrixFm */ - }, - DRX_AUD_DEVIATION_NORMAL, /* deviation */ - DRX_AUD_AVSYNC_OFF, /* avSync */ - - /* prescale */ - { - DRX_AUD_MAX_FM_DEVIATION, /* fmDeviation */ - DRX_AUD_MAX_NICAM_PRESCALE /* nicamGain */ - }, - DRX_AUD_FM_DEEMPH_75US, /* deemph */ - DRX_BTSC_STEREO, /* btscDetect */ - 0, /* rdsDataCounter */ - FALSE /* rdsDataPresent */ + /* i2sdata */ + { + FALSE, /* outputEnable */ + 48000, /* frequency */ + DRX_I2S_MODE_MASTER, /* mode */ + DRX_I2S_WORDLENGTH_32, /* wordLength */ + DRX_I2S_POLARITY_RIGHT, /* polarity */ + DRX_I2S_FORMAT_WS_WITH_DATA /* format */ + }, + /* volume */ + { + TRUE, /* mute; */ + 0, /* volume */ + DRX_AUD_AVC_OFF, /* avcMode */ + 0, /* avcRefLevel */ + DRX_AUD_AVC_MAX_GAIN_12DB, /* avcMaxGain */ + DRX_AUD_AVC_MAX_ATTEN_24DB, /* avcMaxAtten */ + 0, /* strengthLeft */ + 0 /* strengthRight */ + }, + DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON, /* autoSound */ + /* assThresholds */ + { + 440, /* A2 */ + 12, /* BTSC */ + 700, /* NICAM */ + }, + /* carrier */ + { + /* a */ + { + 42, /* thres */ + DRX_NO_CARRIER_NOISE, /* opt */ + 0, /* shift */ + 0 /* dco */ + }, + /* b */ + { + 42, /* thres */ + DRX_NO_CARRIER_MUTE, /* opt */ + 0, /* shift */ + 0 /* dco */ + }, + + }, + /* mixer */ + { + DRX_AUD_SRC_STEREO_OR_A, /* sourceI2S */ + DRX_AUD_I2S_MATRIX_STEREO, /* matrixI2S */ + DRX_AUD_FM_MATRIX_SOUND_A /* matrixFm */ + }, + DRX_AUD_DEVIATION_NORMAL, /* deviation */ + DRX_AUD_AVSYNC_OFF, /* avSync */ + + /* prescale */ + { + DRX_AUD_MAX_FM_DEVIATION, /* fmDeviation */ + DRX_AUD_MAX_NICAM_PRESCALE /* nicamGain */ + }, + DRX_AUD_FM_DEEMPH_75US, /* deemph */ + DRX_BTSC_STEREO, /* btscDetect */ + 0, /* rdsDataCounter */ + FALSE /* rdsDataPresent */ }; - /*----------------------------------------------------------------------------- STRUCTURES ----------------------------------------------------------------------------*/ typedef struct { - u16_t eqMSE; - u8_t eqMode; - u8_t eqCtrl; - u8_t eqStat; + u16_t eqMSE; + u8_t eqMode; + u8_t eqCtrl; + u8_t eqStat; } DRXJEQStat_t, *pDRXJEQStat_t; /* HI command */ typedef struct { - u16_t cmd; - u16_t param1; - u16_t param2; - u16_t param3; - u16_t param4; - u16_t param5; - u16_t param6; + u16_t cmd; + u16_t param1; + u16_t param2; + u16_t param3; + u16_t param4; + u16_t param5; + u16_t param6; } DRXJHiCmd_t, *pDRXJHiCmd_t; #ifdef DRXJ_SPLIT_UCODE_UPLOAD @@ -1169,12 +1132,12 @@ typedef struct { /*============================================================================*/ typedef struct { - u32_t addr; - u16_t size; - u16_t flags; /* bit[15..2]=reserved, - bit[1]= compression on/off - bit[0]= CRC on/off */ - u16_t CRC; + u32_t addr; + u16_t size; + u16_t flags; /* bit[15..2]=reserved, + bit[1]= compression on/off + bit[0]= CRC on/off */ + u16_t CRC; } DRXUCodeBlockHdr_t, *pDRXUCodeBlockHdr_t; #endif /* DRXJ_SPLIT_UCODE_UPLOAD */ @@ -1184,42 +1147,34 @@ FUNCTIONS /* Some prototypes */ static DRXStatus_t HICommand(const pI2CDeviceAddr_t devAddr, - const pDRXJHiCmd_t cmd, - pu16_t result); + const pDRXJHiCmd_t cmd, pu16_t result); static DRXStatus_t -CtrlLockStatus( pDRXDemodInstance_t demod, - pDRXLockStatus_t lockStat ); +CtrlLockStatus(pDRXDemodInstance_t demod, pDRXLockStatus_t lockStat); static DRXStatus_t -CtrlPowerMode( pDRXDemodInstance_t demod, - pDRXPowerMode_t mode ); +CtrlPowerMode(pDRXDemodInstance_t demod, pDRXPowerMode_t mode); -static DRXStatus_t -PowerDownAud( pDRXDemodInstance_t demod ); +static DRXStatus_t PowerDownAud(pDRXDemodInstance_t demod); #ifndef DRXJ_DIGITAL_ONLY -static DRXStatus_t -PowerUpAud( pDRXDemodInstance_t demod, - Bool_t setStandard ); +static DRXStatus_t PowerUpAud(pDRXDemodInstance_t demod, Bool_t setStandard); #endif static DRXStatus_t -AUDCtrlSetStandard ( pDRXDemodInstance_t demod, - pDRXAudStandard_t standard ); +AUDCtrlSetStandard(pDRXDemodInstance_t demod, pDRXAudStandard_t standard); static DRXStatus_t -CtrlSetCfgPreSaw ( pDRXDemodInstance_t demod, pDRXJCfgPreSaw_t preSaw ); +CtrlSetCfgPreSaw(pDRXDemodInstance_t demod, pDRXJCfgPreSaw_t preSaw); static DRXStatus_t -CtrlSetCfgAfeGain ( pDRXDemodInstance_t demod, pDRXJCfgAfeGain_t afeGain ); +CtrlSetCfgAfeGain(pDRXDemodInstance_t demod, pDRXJCfgAfeGain_t afeGain); #ifdef DRXJ_SPLIT_UCODE_UPLOAD static DRXStatus_t -CtrlUCodeUpload( pDRXDemodInstance_t demod, - pDRXUCodeInfo_t mcInfo, - DRXUCodeAction_t action, - Bool_t audioMCUpload ); +CtrlUCodeUpload(pDRXDemodInstance_t demod, + pDRXUCodeInfo_t mcInfo, + DRXUCodeAction_t action, Bool_t audioMCUpload); #endif /* DRXJ_SPLIT_UCODE_UPLOAD */ /*============================================================================*/ @@ -1271,45 +1226,51 @@ CtrlUCodeUpload( pDRXDemodInstance_t demod, #define DRX_IS_BOOTH_NEGATIVE(__a) (((__a) & (1 << (sizeof (u32_t) * 8 - 1))) != 0) -static void Mult32(u32_t a, u32_t b, pu32_t h, pu32_t l) -{ - unsigned int i; - *h = *l = 0; - - /* n/2 iterations; shift operand a left two bits after each iteration. */ - /* This automatically appends a zero to the operand for the last iteration. */ - for (i = 0; i < sizeof (a) * 8; i += 2, a = a << 2) - { - /* Shift result left two bits */ - *h = (*h << 2) + (*l >> (sizeof (*l) * 8 - 2)); - *l = (*l << 2); - - /* Take the first three bits of operand a for the Booth conversion: */ - /* 0, 7: do nothing */ - /* 1, 2: add b */ - /* 3 : add 2b */ - /* 4 : subtract 2b */ - /* 5, 6: subtract b */ - switch (a >> (sizeof (a) * 8 - 3)) - { - case 3: - *l += b; - *h = *h - DRX_IS_BOOTH_NEGATIVE (b) + (*l < b); - case 1: - case 2: - *l += b; - *h = *h - DRX_IS_BOOTH_NEGATIVE (b) + (*l < b); - break; - case 4: - *l -= b; - *h = *h - !DRX_IS_BOOTH_NEGATIVE (b) + !b + (*l < ((u32_t) (-((s32_t)b))) ); - case 5: - case 6: - *l -= b; - *h = *h - !DRX_IS_BOOTH_NEGATIVE (b) + !b + (*l < ((u32_t) (-((s32_t)b))) ); - break; +static void Mult32(u32_t a, u32_t b, pu32_t h, pu32_t l) +{ + unsigned int i; + *h = *l = 0; + + /* n/2 iterations; shift operand a left two bits after each iteration. */ + /* This automatically appends a zero to the operand for the last iteration. */ + for (i = 0; i < sizeof(a) * 8; i += 2, a = a << 2) { + /* Shift result left two bits */ + *h = (*h << 2) + (*l >> (sizeof(*l) * 8 - 2)); + *l = (*l << 2); + + /* Take the first three bits of operand a for the Booth conversion: */ + /* 0, 7: do nothing */ + /* 1, 2: add b */ + /* 3 : add 2b */ + /* 4 : subtract 2b */ + /* 5, 6: subtract b */ + switch (a >> (sizeof(a) * 8 - 3)) { + case 3: + *l += b; + *h = *h - DRX_IS_BOOTH_NEGATIVE(b) + (*l < b); + case 1: + case 2: + *l += b; + *h = *h - DRX_IS_BOOTH_NEGATIVE(b) + (*l < b); + break; + case 4: + *l -= b; + *h = *h - !DRX_IS_BOOTH_NEGATIVE(b) + !b + (*l < + ((u32_t) + (- + ((s32_t) + b)))); + case 5: + case 6: + *l -= b; + *h = *h - !DRX_IS_BOOTH_NEGATIVE(b) + !b + (*l < + ((u32_t) + (- + ((s32_t) + b)))); + break; + } } - } } /*============================================================================*/ @@ -1336,23 +1297,24 @@ static void Mult32(u32_t a, u32_t b, pu32_t h, pu32_t l) */ static u32_t Frac28(u32_t N, u32_t D) { - int i=0; - u32_t Q1=0; - u32_t R0=0; - - R0 = (N%D)<<4; /* 32-28 == 4 shifts possible at max */ - Q1 = N/D; /* integer part, only the 4 least significant bits - will be visible in the result */ - - /* division using radix 16, 7 nibbles in the result */ - for (i=0; i<7; i++) { - Q1 = (Q1 << 4) | R0/D; - R0 = (R0%D)<<4; - } - /* rounding */ - if ((R0>>3) >= D) Q1++; - - return Q1; + int i = 0; + u32_t Q1 = 0; + u32_t R0 = 0; + + R0 = (N % D) << 4; /* 32-28 == 4 shifts possible at max */ + Q1 = N / D; /* integer part, only the 4 least significant bits + will be visible in the result */ + + /* division using radix 16, 7 nibbles in the result */ + for (i = 0; i < 7; i++) { + Q1 = (Q1 << 4) | R0 / D; + R0 = (R0 % D) << 4; + } + /* rounding */ + if ((R0 >> 3) >= D) + Q1++; + + return Q1; } /** @@ -1371,98 +1333,99 @@ static u32_t Frac28(u32_t N, u32_t D) * where y = 2^k and 1<= (x/y) < 2 */ -static u32_t Log10Times100( u32_t x) +static u32_t Log10Times100(u32_t x) { - static const u8_t scale=15; - static const u8_t indexWidth=5; - /* - log2lut[n] = (1<0 ; k--) - { - if (x & (((u32_t)1)<>= 1; - } - } - /* - Now x has binary point between bit[scale] and bit[scale-1] - and 1.0 <= x < 2.0 */ - - /* correction for divison: log(x) = log(x/y)+log(y) */ - y = k * ( ( ((u32_t)1) << scale ) * 200 ); - - /* remove integer part */ - x &= ((((u32_t)1) << scale)-1); - /* get index */ - i = (u8_t) (x >> (scale -indexWidth)); - /* compute delta (x-a) */ - d = x & ((((u32_t)1) << (scale-indexWidth))-1); - /* compute log, multiplication ( d* (.. )) must be within range ! */ - y += log2lut[i] + (( d*( log2lut[i+1]-log2lut[i] ))>>(scale-indexWidth)); - /* Conver to log10() */ - y /= 108853; /* (log2(10) << scale) */ - r = (y>>1); - /* rounding */ - if (y&((u32_t)1)) r++; - - return (r); + static const u8_t scale = 15; + static const u8_t indexWidth = 5; + /* + log2lut[n] = (1< 0; k--) { + if (x & (((u32_t) 1) << scale)) + break; + x <<= 1; + } + } else { + for (k = scale; k < 31; k++) { + if ((x & (((u32_t) (-1)) << (scale + 1))) == 0) + break; + x >>= 1; + } + } + /* + Now x has binary point between bit[scale] and bit[scale-1] + and 1.0 <= x < 2.0 */ + + /* correction for divison: log(x) = log(x/y)+log(y) */ + y = k * ((((u32_t) 1) << scale) * 200); + + /* remove integer part */ + x &= ((((u32_t) 1) << scale) - 1); + /* get index */ + i = (u8_t) (x >> (scale - indexWidth)); + /* compute delta (x-a) */ + d = x & ((((u32_t) 1) << (scale - indexWidth)) - 1); + /* compute log, multiplication ( d* (.. )) must be within range ! */ + y += log2lut[i] + + ((d * (log2lut[i + 1] - log2lut[i])) >> (scale - indexWidth)); + /* Conver to log10() */ + y /= 108853; /* (log2(10) << scale) */ + r = (y >> 1); + /* rounding */ + if (y & ((u32_t) 1)) + r++; + + return (r); } @@ -1476,30 +1439,29 @@ static u32_t Log10Times100( u32_t x) * * No check on D=0! */ -static u32_t FracTimes1e6( u32_t N, u32_t D) +static u32_t FracTimes1e6(u32_t N, u32_t D) { - u32_t remainder = 0; - u32_t frac = 0; - - /* - frac = (N * 1000000) / D - To let it fit in a 32 bits computation: - frac = (N * (1000000 >> 4)) / (D >> 4) - This would result in a problem in case D < 16 (div by 0). - So we do it more elaborate as shown below. - */ - frac = ( ((u32_t)N) * (1000000 >> 4) ) / D ; - frac <<= 4 ; - remainder = ( ((u32_t)N) * (1000000 >> 4) ) % D ; - remainder <<= 4; - frac += remainder / D; - remainder = remainder % D ; - if( (remainder * 2) > D ) - { - frac++; - } + u32_t remainder = 0; + u32_t frac = 0; - return ( frac ); + /* + frac = (N * 1000000) / D + To let it fit in a 32 bits computation: + frac = (N * (1000000 >> 4)) / (D >> 4) + This would result in a problem in case D < 16 (div by 0). + So we do it more elaborate as shown below. + */ + frac = (((u32_t) N) * (1000000 >> 4)) / D; + frac <<= 4; + remainder = (((u32_t) N) * (1000000 >> 4)) % D; + remainder <<= 4; + frac += remainder / D; + remainder = remainder % D; + if ((remainder * 2) > D) { + frac++; + } + + return (frac); } /*============================================================================*/ @@ -1510,43 +1472,41 @@ static u32_t FracTimes1e6( u32_t N, u32_t D) * \return u32_t Gainfactor in 0.01 resolution * */ -static u32_t dB2LinTimes100( u32_t GdB ) +static u32_t dB2LinTimes100(u32_t GdB) { - u32_t result = 0; - u32_t nr6dBSteps = 0; - u32_t remainder = 0; - u32_t remainderFac = 0; - - /* start with factors 2 (6.02dB) */ - nr6dBSteps = GdB * 1000UL / 60206UL; - if ( nr6dBSteps > 17 ) - { - /* Result max overflow if > log2( maxu32 / 2e4 ) ~= 17.7 */ - return MAX_U32; - } - result = (1< 17) { + /* Result max overflow if > log2( maxu32 / 2e4 ) ~= 17.7 */ + return MAX_U32; + } + result = (1 << nr6dBSteps); + + /* calculate remaining factor, + poly approximation of 10^(GdB/200): - y = 1E-04x2 + 0.0106x + 1.0026 + y = 1E-04x2 + 0.0106x + 1.0026 - max deviation < 0.005 for range x = [0 ... 60] - */ - remainder = ( ( GdB * 1000UL ) % 60206UL ) / 1000UL; - /* using 1e-4 for poly calculation */ - remainderFac = 1 * remainder * remainder; - remainderFac += 106 * remainder; - remainderFac += 10026; + max deviation < 0.005 for range x = [0 ... 60] + */ + remainder = ((GdB * 1000UL) % 60206UL) / 1000UL; + /* using 1e-4 for poly calculation */ + remainderFac = 1 * remainder * remainder; + remainderFac += 106 * remainder; + remainderFac += 10026; - /* multiply by remaining factor */ - result *= remainderFac; + /* multiply by remaining factor */ + result *= remainderFac; - /* conversion from 1e-4 to 1e-2 */ - return ( (result + 50 ) / 100); + /* conversion from 1e-4 to 1e-2 */ + return ((result + 50) / 100); } - #ifndef DRXJ_DIGITAL_ONLY #define FRAC_FLOOR 0 #define FRAC_CEIL 1 @@ -1562,60 +1522,50 @@ static u32_t dB2LinTimes100( u32_t GdB ) * * If D=0 returns 0 */ -static u32_t Frac( u32_t N, u32_t D, u16_t RC ) +static u32_t Frac(u32_t N, u32_t D, u16_t RC) { - u32_t remainder = 0; - u32_t frac = 0; - u16_t bitCnt = 32; + u32_t remainder = 0; + u32_t frac = 0; + u16_t bitCnt = 32; - if ( D == 0 ) - { - frac = 0; - remainder = 0; + if (D == 0) { + frac = 0; + remainder = 0; - return ( frac ); - } + return (frac); + } - if ( D > N ) - { - frac = 0; - remainder = N; - } - else - { - remainder = 0; - frac = N; - while ( bitCnt-- > 0 ) - { - remainder <<= 1; - remainder |= ( ( frac & 0x80000000 ) >> 31 ); - frac <<= 1; - if ( remainder < D ) - { - frac &= 0xFFFFFFFE; - } - else - { - remainder -= D; - frac |= 0x1; - } - } - - /* result correction if needed */ - if ( ( RC == FRAC_CEIL ) && ( remainder != 0 ) ) - { - /* ceil the result */ - /*(remainder is not zero -> value behind decimal point exists) */ - frac++; - } - if ( ( RC == FRAC_ROUND ) && ( remainder >= D>>1 ) ) - { - /* remainder is bigger from D/2 -> round the result */ - frac++; - } - } - - return ( frac ); + if (D > N) { + frac = 0; + remainder = N; + } else { + remainder = 0; + frac = N; + while (bitCnt-- > 0) { + remainder <<= 1; + remainder |= ((frac & 0x80000000) >> 31); + frac <<= 1; + if (remainder < D) { + frac &= 0xFFFFFFFE; + } else { + remainder -= D; + frac |= 0x1; + } + } + + /* result correction if needed */ + if ((RC == FRAC_CEIL) && (remainder != 0)) { + /* ceil the result */ + /*(remainder is not zero -> value behind decimal point exists) */ + frac++; + } + if ((RC == FRAC_ROUND) && (remainder >= D >> 1)) { + /* remainder is bigger from D/2 -> round the result */ + frac++; + } + } + + return (frac); } #endif @@ -1627,18 +1577,17 @@ static u32_t Frac( u32_t N, u32_t D, u16_t RC ) * \brief Read a 16 bits word, expect big endian data. * \return u16_t The data read. */ -static u16_t -UCodeRead16( pu8_t addr) +static u16_t UCodeRead16(pu8_t addr) { - /* Works fo any host processor */ + /* Works fo any host processor */ - u16_t word=0; + u16_t word = 0; - word = ((u16_t)addr[0]); - word <<= 8; - word |=((u16_t)addr[1]); + word = ((u16_t) addr[0]); + word <<= 8; + word |= ((u16_t) addr[1]); - return ( word ); + return (word); } /*============================================================================*/ @@ -1648,22 +1597,21 @@ UCodeRead16( pu8_t addr) * \brief Read a 32 bits word, expect big endian data. * \return u32_t The data read. */ -static u32_t -UCodeRead32( pu8_t addr) +static u32_t UCodeRead32(pu8_t addr) { - /* Works fo any host processor */ + /* Works fo any host processor */ - u32_t word=0; + u32_t word = 0; - word = ((u16_t)addr[0]); - word <<= 8; - word |= ((u16_t)addr[1]); - word <<= 8; - word |= ((u16_t)addr[2]); - word <<= 8; - word |= ((u16_t)addr[3]); + word = ((u16_t) addr[0]); + word <<= 8; + word |= ((u16_t) addr[1]); + word <<= 8; + word |= ((u16_t) addr[2]); + word <<= 8; + word |= ((u16_t) addr[3]); - return ( word ); + return (word); } /*============================================================================*/ @@ -1675,27 +1623,25 @@ UCodeRead32( pu8_t addr) * \param nrWords Size of microcode block (number of 16 bits words). * \return u16_t The computed CRC residu. */ -static u16_t -UCodeComputeCRC (pu8_t blockData, u16_t nrWords) -{ - u16_t i = 0; - u16_t j = 0; - u32_t CRCWord=0; - u32_t carry=0; - - while (i < nrWords) { - CRCWord |= (u32_t) UCodeRead16(blockData); - for (j = 0; j < 16; j++) - { - CRCWord <<= 1; - if (carry != 0) - CRCWord ^= 0x80050000UL; - carry = CRCWord & 0x80000000UL; - } - i++; - blockData+=(sizeof(u16_t)); - } - return ((u16_t) (CRCWord >> 16)); +static u16_t UCodeComputeCRC(pu8_t blockData, u16_t nrWords) +{ + u16_t i = 0; + u16_t j = 0; + u32_t CRCWord = 0; + u32_t carry = 0; + + while (i < nrWords) { + CRCWord |= (u32_t) UCodeRead16(blockData); + for (j = 0; j < 16; j++) { + CRCWord <<= 1; + if (carry != 0) + CRCWord ^= 0x80050000UL; + carry = CRCWord & 0x80000000UL; + } + i++; + blockData += (sizeof(u16_t)); + } + return ((u16_t) (CRCWord >> 16)); } #endif /* DRXJ_SPLIT_UCODE_UPLOAD */ @@ -1704,17 +1650,17 @@ UCodeComputeCRC (pu8_t blockData, u16_t nrWords) * and rounded. For calc used formula: 16*10^(prescaleGain[dB]/20). * */ -static const u16_t NicamPrescTableVal[43] = { 1,1,1,1,2,2,2,2,3,3,3,4,4, - 5,5,6,6,7,8,9,10,11,13,14,16, - 18,20,23,25,28,32,36,40,45, - 51,57,64,71,80,90,101,113,127 - }; +static const u16_t NicamPrescTableVal[43] = + { 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, + 5, 5, 6, 6, 7, 8, 9, 10, 11, 13, 14, 16, + 18, 20, 23, 25, 28, 32, 36, 40, 45, + 51, 57, 64, 71, 80, 90, 101, 113, 127 +}; /*============================================================================*/ /*== END HELPER FUNCTIONS ==*/ /*============================================================================*/ - /*============================================================================*/ /*============================================================================*/ /*== DRXJ DAP FUNCTIONS ==*/ @@ -1734,12 +1680,11 @@ static const u16_t NicamPrescTableVal[43] = { 1,1,1,1,2,2,2,2,3,3,3,4,4, registers will have undefined behaviour. Flags (RMW, CRC reset, broadcast single/multi master) will be ignored. - TODO: check ignoring single/multimaster is ok for AUD access ? */ #define DRXJ_ISAUDWRITE( addr ) (((((addr)>>16)&1)==1)?TRUE:FALSE) -#define DRXJ_DAP_AUDTRIF_TIMEOUT 80 /* millisec */ +#define DRXJ_DAP_AUDTRIF_TIMEOUT 80 /* millisec */ /*============================================================================*/ /** @@ -1752,50 +1697,40 @@ static const u16_t NicamPrescTableVal[43] = { 1,1,1,1,2,2,2,2,3,3,3,4,4, * */ static -Bool_t IsHandledByAudTrIf( DRXaddr_t addr ) +Bool_t IsHandledByAudTrIf(DRXaddr_t addr) { - Bool_t retval = FALSE; + Bool_t retval = FALSE; - if ( (DRXDAP_FASI_ADDR2BLOCK( addr ) == 4) && - ( DRXDAP_FASI_ADDR2BANK( addr) > 1 ) && - ( DRXDAP_FASI_ADDR2BANK( addr) < 6 ) ) - { - retval=TRUE; - } + if ((DRXDAP_FASI_ADDR2BLOCK(addr) == 4) && + (DRXDAP_FASI_ADDR2BANK(addr) > 1) && + (DRXDAP_FASI_ADDR2BANK(addr) < 6)) { + retval = TRUE; + } - return (retval); + return (retval); } /*============================================================================*/ -static DRXStatus_t DRXJ_DAP_ReadBlock ( - pI2CDeviceAddr_t devAddr, - DRXaddr_t addr, - u16_t datasize, - pu8_t data, - DRXflags_t flags) +static DRXStatus_t DRXJ_DAP_ReadBlock(pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + u16_t datasize, + pu8_t data, DRXflags_t flags) { - return drxDapFASIFunct_g.readBlockFunc( devAddr, - addr, - datasize, - data, - flags); + return drxDapFASIFunct_g.readBlockFunc(devAddr, + addr, datasize, data, flags); } /*============================================================================*/ -static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg8 ( - pI2CDeviceAddr_t devAddr, - DRXaddr_t waddr, - DRXaddr_t raddr, - u8_t wdata, - pu8_t rdata) +static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg8(pI2CDeviceAddr_t devAddr, + DRXaddr_t waddr, + DRXaddr_t raddr, + u8_t wdata, pu8_t rdata) { - return drxDapFASIFunct_g.readModifyWriteReg8Func( devAddr, - waddr, - raddr, - wdata, - rdata); + return drxDapFASIFunct_g.readModifyWriteReg8Func(devAddr, + waddr, + raddr, wdata, rdata); } /*============================================================================*/ @@ -1821,103 +1756,81 @@ static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg8 ( /* TODO correct define should be #if ( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 ) See comments DRXJ_DAP_ReadModifyWriteReg16 */ #if ( DRXDAPFASI_LONG_ADDR_ALLOWED == 0 ) -static DRXStatus_t DRXJ_DAP_RMWriteReg16Short ( - pI2CDeviceAddr_t devAddr, - DRXaddr_t waddr, - DRXaddr_t raddr, - u16_t wdata, - pu16_t rdata) +static DRXStatus_t DRXJ_DAP_RMWriteReg16Short(pI2CDeviceAddr_t devAddr, + DRXaddr_t waddr, + DRXaddr_t raddr, + u16_t wdata, pu16_t rdata) { - DRXStatus_t rc; - - if (rdata == NULL) - { - return DRX_STS_INVALID_ARG; - } - - /* Set RMW flag */ - rc = drxDapFASIFunct_g.writeReg16Func (devAddr, - SIO_HI_RA_RAM_S0_FLG_ACC__A, - SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__M, - 0x0000); - if (rc == DRX_STS_OK) - { - /* Write new data: triggers RMW */ - rc = drxDapFASIFunct_g.writeReg16Func (devAddr, waddr, wdata, 0x0000 ); - } - if (rc == DRX_STS_OK) - { - /* Read old data */ - rc = drxDapFASIFunct_g.readReg16Func (devAddr, raddr, rdata, 0x0000 ); - } - if (rc == DRX_STS_OK) - { - /* Reset RMW flag */ - rc = drxDapFASIFunct_g.writeReg16Func (devAddr, + DRXStatus_t rc; + + if (rdata == NULL) { + return DRX_STS_INVALID_ARG; + } + + /* Set RMW flag */ + rc = drxDapFASIFunct_g.writeReg16Func(devAddr, SIO_HI_RA_RAM_S0_FLG_ACC__A, - 0, + SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__M, 0x0000); - } + if (rc == DRX_STS_OK) { + /* Write new data: triggers RMW */ + rc = drxDapFASIFunct_g.writeReg16Func(devAddr, waddr, wdata, + 0x0000); + } + if (rc == DRX_STS_OK) { + /* Read old data */ + rc = drxDapFASIFunct_g.readReg16Func(devAddr, raddr, rdata, + 0x0000); + } + if (rc == DRX_STS_OK) { + /* Reset RMW flag */ + rc = drxDapFASIFunct_g.writeReg16Func(devAddr, + SIO_HI_RA_RAM_S0_FLG_ACC__A, + 0, 0x0000); + } - return rc; + return rc; } #endif /*============================================================================*/ -static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg16 ( - pI2CDeviceAddr_t devAddr, - DRXaddr_t waddr, - DRXaddr_t raddr, - u16_t wdata, - pu16_t rdata) +static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg16(pI2CDeviceAddr_t devAddr, + DRXaddr_t waddr, + DRXaddr_t raddr, + u16_t wdata, pu16_t rdata) { - /* TODO: correct short/long addressing format decision, - now long format has higher prio then short because short also - needs virt bnks (not impl yet) for certain audio registers */ + /* TODO: correct short/long addressing format decision, + now long format has higher prio then short because short also + needs virt bnks (not impl yet) for certain audio registers */ #if ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 ) - return drxDapFASIFunct_g.readModifyWriteReg16Func( devAddr, - waddr, - raddr, - wdata, - rdata); + return drxDapFASIFunct_g.readModifyWriteReg16Func(devAddr, + waddr, + raddr, wdata, rdata); #else - return DRXJ_DAP_RMWriteReg16Short( devAddr, - waddr, - raddr, - wdata, - rdata); + return DRXJ_DAP_RMWriteReg16Short(devAddr, waddr, raddr, wdata, rdata); #endif } /*============================================================================*/ -static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg32 ( - pI2CDeviceAddr_t devAddr, - DRXaddr_t waddr, - DRXaddr_t raddr, - u32_t wdata, - pu32_t rdata) +static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg32(pI2CDeviceAddr_t devAddr, + DRXaddr_t waddr, + DRXaddr_t raddr, + u32_t wdata, pu32_t rdata) { - return drxDapFASIFunct_g.readModifyWriteReg32Func( devAddr, - waddr, - raddr, - wdata, - rdata); + return drxDapFASIFunct_g.readModifyWriteReg32Func(devAddr, + waddr, + raddr, wdata, rdata); } /*============================================================================*/ -static DRXStatus_t DRXJ_DAP_ReadReg8 ( - pI2CDeviceAddr_t devAddr, - DRXaddr_t addr, - pu8_t data, - DRXflags_t flags) +static DRXStatus_t DRXJ_DAP_ReadReg8(pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + pu8_t data, DRXflags_t flags) { - return drxDapFASIFunct_g.readReg8Func( devAddr, - addr, - data, - flags); + return drxDapFASIFunct_g.readReg8Func(devAddr, addr, data, flags); } /*============================================================================*/ @@ -1935,169 +1848,134 @@ static DRXStatus_t DRXJ_DAP_ReadReg8 ( * 16 bits register read access via audio token ring interface. * */ -static DRXStatus_t DRXJ_DAP_ReadAudReg16 ( - pI2CDeviceAddr_t devAddr, - DRXaddr_t addr, - pu16_t data) -{ - u32_t startTimer = 0; - u32_t currentTimer = 0; - u32_t deltaTimer = 0; - u16_t trStatus = 0; - DRXStatus_t stat = DRX_STS_ERROR; - - /* No read possible for bank 3, return with error */ - if ( DRXDAP_FASI_ADDR2BANK(addr) == 3 ) - { - stat=DRX_STS_INVALID_ARG; - } else { - const DRXaddr_t writeBit = ((DRXaddr_t)1)<<16; - - /* Force reset write bit */ - addr &= (~writeBit); - - /* Set up read */ - startTimer = DRXBSP_HST_Clock(); - do { - /* RMW to aud TR IF until request is granted or timeout */ - stat = DRXJ_DAP_ReadModifyWriteReg16( devAddr, - addr, - SIO_HI_RA_RAM_S0_RMWBUF__A, - 0x0000, - &trStatus); - - if ( stat != DRX_STS_OK ) - { - break; - }; - - currentTimer = DRXBSP_HST_Clock(); - deltaTimer = currentTimer - startTimer; - if ( deltaTimer > DRXJ_DAP_AUDTRIF_TIMEOUT ) - { - stat = DRX_STS_ERROR; - break; - }; - - } while ( ( ( trStatus & AUD_TOP_TR_CTR_FIFO_LOCK__M ) == - AUD_TOP_TR_CTR_FIFO_LOCK_LOCKED ) || - ( ( trStatus & AUD_TOP_TR_CTR_FIFO_FULL__M ) == - AUD_TOP_TR_CTR_FIFO_FULL_FULL ) ); - } /* if ( DRXDAP_FASI_ADDR2BANK(addr)!=3 ) */ - - /* Wait for read ready status or timeout */ - if ( stat == DRX_STS_OK ) - { - startTimer = DRXBSP_HST_Clock(); - - while ( ( trStatus & AUD_TOP_TR_CTR_FIFO_RD_RDY__M) != - AUD_TOP_TR_CTR_FIFO_RD_RDY_READY) - { - stat = DRXJ_DAP_ReadReg16( devAddr, - AUD_TOP_TR_CTR__A, - &trStatus, - 0x0000); - if ( stat != DRX_STS_OK ) - { - break; - }; +static DRXStatus_t DRXJ_DAP_ReadAudReg16(pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, pu16_t data) +{ + u32_t startTimer = 0; + u32_t currentTimer = 0; + u32_t deltaTimer = 0; + u16_t trStatus = 0; + DRXStatus_t stat = DRX_STS_ERROR; + + /* No read possible for bank 3, return with error */ + if (DRXDAP_FASI_ADDR2BANK(addr) == 3) { + stat = DRX_STS_INVALID_ARG; + } else { + const DRXaddr_t writeBit = ((DRXaddr_t) 1) << 16; + + /* Force reset write bit */ + addr &= (~writeBit); + + /* Set up read */ + startTimer = DRXBSP_HST_Clock(); + do { + /* RMW to aud TR IF until request is granted or timeout */ + stat = DRXJ_DAP_ReadModifyWriteReg16(devAddr, + addr, + SIO_HI_RA_RAM_S0_RMWBUF__A, + 0x0000, &trStatus); + + if (stat != DRX_STS_OK) { + break; + }; + + currentTimer = DRXBSP_HST_Clock(); + deltaTimer = currentTimer - startTimer; + if (deltaTimer > DRXJ_DAP_AUDTRIF_TIMEOUT) { + stat = DRX_STS_ERROR; + break; + }; + + } while (((trStatus & AUD_TOP_TR_CTR_FIFO_LOCK__M) == + AUD_TOP_TR_CTR_FIFO_LOCK_LOCKED) || + ((trStatus & AUD_TOP_TR_CTR_FIFO_FULL__M) == + AUD_TOP_TR_CTR_FIFO_FULL_FULL)); + } /* if ( DRXDAP_FASI_ADDR2BANK(addr)!=3 ) */ + + /* Wait for read ready status or timeout */ + if (stat == DRX_STS_OK) { + startTimer = DRXBSP_HST_Clock(); + + while ((trStatus & AUD_TOP_TR_CTR_FIFO_RD_RDY__M) != + AUD_TOP_TR_CTR_FIFO_RD_RDY_READY) { + stat = DRXJ_DAP_ReadReg16(devAddr, + AUD_TOP_TR_CTR__A, + &trStatus, 0x0000); + if (stat != DRX_STS_OK) { + break; + }; + + currentTimer = DRXBSP_HST_Clock(); + deltaTimer = currentTimer - startTimer; + if (deltaTimer > DRXJ_DAP_AUDTRIF_TIMEOUT) { + stat = DRX_STS_ERROR; + break; + }; + } /* while ( ... ) */ + } - currentTimer = DRXBSP_HST_Clock(); - deltaTimer = currentTimer - startTimer; - if ( deltaTimer > DRXJ_DAP_AUDTRIF_TIMEOUT ) - { - stat = DRX_STS_ERROR; - break; - }; - } /* while ( ... ) */ - } /* if { stat == DRX_STS_OK ) */ - - /* Read value */ - if ( stat == DRX_STS_OK ) - { - stat = DRXJ_DAP_ReadModifyWriteReg16( devAddr, - AUD_TOP_TR_RD_REG__A, - SIO_HI_RA_RAM_S0_RMWBUF__A, - 0x0000, - data); - } /* if { stat == DRX_STS_OK ) */ - - return stat; + /* if { stat == DRX_STS_OK ) */ + /* Read value */ + if (stat == DRX_STS_OK) { + stat = DRXJ_DAP_ReadModifyWriteReg16(devAddr, + AUD_TOP_TR_RD_REG__A, + SIO_HI_RA_RAM_S0_RMWBUF__A, + 0x0000, data); + } + /* if { stat == DRX_STS_OK ) */ + return stat; } /*============================================================================*/ -static DRXStatus_t DRXJ_DAP_ReadReg16 ( - pI2CDeviceAddr_t devAddr, - DRXaddr_t addr, - pu16_t data, - DRXflags_t flags) +static DRXStatus_t DRXJ_DAP_ReadReg16(pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + pu16_t data, DRXflags_t flags) { - DRXStatus_t stat = DRX_STS_ERROR; + DRXStatus_t stat = DRX_STS_ERROR; - /* Check param */ - if ( ( devAddr == NULL ) || ( data == NULL ) ) - { - return DRX_STS_INVALID_ARG; - } + /* Check param */ + if ((devAddr == NULL) || (data == NULL)) { + return DRX_STS_INVALID_ARG; + } - if ( IsHandledByAudTrIf(addr) ) - { - stat = DRXJ_DAP_ReadAudReg16 (devAddr, - addr, - data); - } else { - stat = drxDapFASIFunct_g.readReg16Func( devAddr, - addr, - data, - flags); - } - - return stat; + if (IsHandledByAudTrIf(addr)) { + stat = DRXJ_DAP_ReadAudReg16(devAddr, addr, data); + } else { + stat = drxDapFASIFunct_g.readReg16Func(devAddr, + addr, data, flags); + } + + return stat; } /*============================================================================*/ -static DRXStatus_t DRXJ_DAP_ReadReg32 ( - pI2CDeviceAddr_t devAddr, - DRXaddr_t addr, - pu32_t data, - DRXflags_t flags) +static DRXStatus_t DRXJ_DAP_ReadReg32(pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + pu32_t data, DRXflags_t flags) { - return drxDapFASIFunct_g.readReg32Func( devAddr, - addr, - data, - flags); + return drxDapFASIFunct_g.readReg32Func(devAddr, addr, data, flags); } /*============================================================================*/ -static DRXStatus_t DRXJ_DAP_WriteBlock ( - pI2CDeviceAddr_t devAddr, - DRXaddr_t addr, - u16_t datasize, - pu8_t data, - DRXflags_t flags) +static DRXStatus_t DRXJ_DAP_WriteBlock(pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + u16_t datasize, + pu8_t data, DRXflags_t flags) { - return drxDapFASIFunct_g.writeBlockFunc( devAddr, - addr, - datasize, - data, - flags); + return drxDapFASIFunct_g.writeBlockFunc(devAddr, + addr, datasize, data, flags); } /*============================================================================*/ -static DRXStatus_t DRXJ_DAP_WriteReg8 ( - pI2CDeviceAddr_t devAddr, - DRXaddr_t addr, - u8_t data, - DRXflags_t flags) +static DRXStatus_t DRXJ_DAP_WriteReg8(pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + u8_t data, DRXflags_t flags) { - return drxDapFASIFunct_g.writeReg8Func( devAddr, - addr, - data, - flags); + return drxDapFASIFunct_g.writeReg8Func(devAddr, addr, data, flags); } /*============================================================================*/ @@ -2115,101 +1993,81 @@ static DRXStatus_t DRXJ_DAP_WriteReg8 ( * 16 bits register write access via audio token ring interface. * */ -static DRXStatus_t DRXJ_DAP_WriteAudReg16 ( - pI2CDeviceAddr_t devAddr, - DRXaddr_t addr, - u16_t data) +static DRXStatus_t DRXJ_DAP_WriteAudReg16(pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, u16_t data) { - DRXStatus_t stat = DRX_STS_ERROR; + DRXStatus_t stat = DRX_STS_ERROR; - /* No write possible for bank 2, return with error */ - if ( DRXDAP_FASI_ADDR2BANK(addr) == 2 ) - { - stat=DRX_STS_INVALID_ARG; - } else { - u32_t startTimer = 0; - u32_t currentTimer = 0; - u32_t deltaTimer = 0; - u16_t trStatus = 0; - const DRXaddr_t writeBit = ((DRXaddr_t)1)<<16; - - /* Force write bit */ - addr |= writeBit; - startTimer = DRXBSP_HST_Clock(); - do { - /* RMW to aud TR IF until request is granted or timeout */ - stat = DRXJ_DAP_ReadModifyWriteReg16( devAddr, - addr, - SIO_HI_RA_RAM_S0_RMWBUF__A, - data, - &trStatus); - if ( stat != DRX_STS_OK ) - { - break; - }; + /* No write possible for bank 2, return with error */ + if (DRXDAP_FASI_ADDR2BANK(addr) == 2) { + stat = DRX_STS_INVALID_ARG; + } else { + u32_t startTimer = 0; + u32_t currentTimer = 0; + u32_t deltaTimer = 0; + u16_t trStatus = 0; + const DRXaddr_t writeBit = ((DRXaddr_t) 1) << 16; - currentTimer = DRXBSP_HST_Clock(); - deltaTimer = currentTimer - startTimer; - if ( deltaTimer > DRXJ_DAP_AUDTRIF_TIMEOUT ) - { - stat = DRX_STS_ERROR; - break; - }; + /* Force write bit */ + addr |= writeBit; + startTimer = DRXBSP_HST_Clock(); + do { + /* RMW to aud TR IF until request is granted or timeout */ + stat = DRXJ_DAP_ReadModifyWriteReg16(devAddr, + addr, + SIO_HI_RA_RAM_S0_RMWBUF__A, + data, &trStatus); + if (stat != DRX_STS_OK) { + break; + }; - } while ( ( ( trStatus & AUD_TOP_TR_CTR_FIFO_LOCK__M ) == - AUD_TOP_TR_CTR_FIFO_LOCK_LOCKED ) || - ( ( trStatus & AUD_TOP_TR_CTR_FIFO_FULL__M ) == - AUD_TOP_TR_CTR_FIFO_FULL_FULL ) ); + currentTimer = DRXBSP_HST_Clock(); + deltaTimer = currentTimer - startTimer; + if (deltaTimer > DRXJ_DAP_AUDTRIF_TIMEOUT) { + stat = DRX_STS_ERROR; + break; + }; - } /* if ( DRXDAP_FASI_ADDR2BANK(addr)!=2 ) */ + } while (((trStatus & AUD_TOP_TR_CTR_FIFO_LOCK__M) == + AUD_TOP_TR_CTR_FIFO_LOCK_LOCKED) || + ((trStatus & AUD_TOP_TR_CTR_FIFO_FULL__M) == + AUD_TOP_TR_CTR_FIFO_FULL_FULL)); - return stat; + } /* if ( DRXDAP_FASI_ADDR2BANK(addr)!=2 ) */ + + return stat; } /*============================================================================*/ -static DRXStatus_t DRXJ_DAP_WriteReg16 ( - pI2CDeviceAddr_t devAddr, - DRXaddr_t addr, - u16_t data, - DRXflags_t flags) +static DRXStatus_t DRXJ_DAP_WriteReg16(pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + u16_t data, DRXflags_t flags) { - DRXStatus_t stat=DRX_STS_ERROR; + DRXStatus_t stat = DRX_STS_ERROR; - /* Check param */ - if ( devAddr == NULL ) - { - return DRX_STS_INVALID_ARG; - } + /* Check param */ + if (devAddr == NULL) { + return DRX_STS_INVALID_ARG; + } + if (IsHandledByAudTrIf(addr)) { + stat = DRXJ_DAP_WriteAudReg16(devAddr, addr, data); + } else { + stat = drxDapFASIFunct_g.writeReg16Func(devAddr, + addr, data, flags); + } - if ( IsHandledByAudTrIf(addr) ) - { - stat = DRXJ_DAP_WriteAudReg16 (devAddr, - addr, - data); - } else { - stat = drxDapFASIFunct_g.writeReg16Func( devAddr, - addr, - data, - flags); - } - - return stat; + return stat; } /*============================================================================*/ -static DRXStatus_t DRXJ_DAP_WriteReg32 ( - pI2CDeviceAddr_t devAddr, - DRXaddr_t addr, - u32_t data, - DRXflags_t flags) +static DRXStatus_t DRXJ_DAP_WriteReg32(pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + u32_t data, DRXflags_t flags) { - return drxDapFASIFunct_g.writeReg32Func( devAddr, - addr, - data, - flags); + return drxDapFASIFunct_g.writeReg32Func(devAddr, addr, data, flags); } /*============================================================================*/ @@ -2236,76 +2094,70 @@ static DRXStatus_t DRXJ_DAP_WriteReg32 ( * */ static -DRXStatus_t DRXJ_DAP_AtomicReadWriteBlock ( - pI2CDeviceAddr_t devAddr, - DRXaddr_t addr, - u16_t datasize, - pu8_t data, - Bool_t readFlag) -{ - DRXJHiCmd_t hiCmd; - - u16_t word; - u16_t dummy=0; - u16_t i=0; - - /* Parameter check */ - if ( ( data == NULL ) || - ( devAddr == NULL ) || - ( (datasize%2)!= 0 ) || - ( (datasize/2) > 8 ) - ) - { - return (DRX_STS_INVALID_ARG); - } - - /* Set up HI parameters to read or write n bytes */ - hiCmd.cmd = SIO_HI_RA_RAM_CMD_ATOMIC_COPY; - hiCmd.param1 = - (u16_t)(( DRXDAP_FASI_ADDR2BLOCK( DRXJ_HI_ATOMIC_BUF_START ) << 6 ) + - DRXDAP_FASI_ADDR2BANK( DRXJ_HI_ATOMIC_BUF_START ) ); - hiCmd.param2 = (u16_t)DRXDAP_FASI_ADDR2OFFSET( DRXJ_HI_ATOMIC_BUF_START ); - hiCmd.param3 = (u16_t)((datasize/2) - 1); - if ( readFlag == FALSE ) - { - hiCmd.param3 |= DRXJ_HI_ATOMIC_WRITE; - } else { - hiCmd.param3 |= DRXJ_HI_ATOMIC_READ; - } - hiCmd.param4 = (u16_t) ( ( DRXDAP_FASI_ADDR2BLOCK(addr) << 6 ) + - DRXDAP_FASI_ADDR2BANK(addr) ); - hiCmd.param5 = (u16_t)DRXDAP_FASI_ADDR2OFFSET(addr); - - if ( readFlag == FALSE ) - { - /* write data to buffer */ - for (i = 0; i < (datasize/2); i++) - { - - - word = ((u16_t)data[2*i]); - word += (((u16_t)data[(2*i)+1])<<8); - DRXJ_DAP_WriteReg16 (devAddr, (DRXJ_HI_ATOMIC_BUF_START + i), word, 0); - } - } +DRXStatus_t DRXJ_DAP_AtomicReadWriteBlock(pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + u16_t datasize, + pu8_t data, Bool_t readFlag) +{ + DRXJHiCmd_t hiCmd; + + u16_t word; + u16_t dummy = 0; + u16_t i = 0; + + /* Parameter check */ + if ((data == NULL) || + (devAddr == NULL) || ((datasize % 2) != 0) || ((datasize / 2) > 8) + ) { + return (DRX_STS_INVALID_ARG); + } - CHK_ERROR( HICommand( devAddr, &hiCmd, &dummy) ); + /* Set up HI parameters to read or write n bytes */ + hiCmd.cmd = SIO_HI_RA_RAM_CMD_ATOMIC_COPY; + hiCmd.param1 = + (u16_t) ((DRXDAP_FASI_ADDR2BLOCK(DRXJ_HI_ATOMIC_BUF_START) << 6) + + DRXDAP_FASI_ADDR2BANK(DRXJ_HI_ATOMIC_BUF_START)); + hiCmd.param2 = + (u16_t) DRXDAP_FASI_ADDR2OFFSET(DRXJ_HI_ATOMIC_BUF_START); + hiCmd.param3 = (u16_t) ((datasize / 2) - 1); + if (readFlag == FALSE) { + hiCmd.param3 |= DRXJ_HI_ATOMIC_WRITE; + } else { + hiCmd.param3 |= DRXJ_HI_ATOMIC_READ; + } + hiCmd.param4 = (u16_t) ((DRXDAP_FASI_ADDR2BLOCK(addr) << 6) + + DRXDAP_FASI_ADDR2BANK(addr)); + hiCmd.param5 = (u16_t) DRXDAP_FASI_ADDR2OFFSET(addr); + + if (readFlag == FALSE) { + /* write data to buffer */ + for (i = 0; i < (datasize / 2); i++) { + + word = ((u16_t) data[2 * i]); + word += (((u16_t) data[(2 * i) + 1]) << 8); + DRXJ_DAP_WriteReg16(devAddr, + (DRXJ_HI_ATOMIC_BUF_START + i), + word, 0); + } + } - if ( readFlag == TRUE ) - { - /* read data from buffer */ - for (i = 0; i < (datasize/2); i++) - { - DRXJ_DAP_ReadReg16 (devAddr, (DRXJ_HI_ATOMIC_BUF_START + i), &word, 0); - data[2*i] = (u8_t) (word & 0xFF); - data[(2*i) + 1] = (u8_t) (word >> 8 ); - } - } + CHK_ERROR(HICommand(devAddr, &hiCmd, &dummy)); + + if (readFlag == TRUE) { + /* read data from buffer */ + for (i = 0; i < (datasize / 2); i++) { + DRXJ_DAP_ReadReg16(devAddr, + (DRXJ_HI_ATOMIC_BUF_START + i), + &word, 0); + data[2 * i] = (u8_t) (word & 0xFF); + data[(2 * i) + 1] = (u8_t) (word >> 8); + } + } - return DRX_STS_OK; + return DRX_STS_OK; - rw_error: - return (DRX_STS_ERROR); +rw_error: + return (DRX_STS_ERROR); } @@ -2316,41 +2168,36 @@ DRXStatus_t DRXJ_DAP_AtomicReadWriteBlock ( * \brief Atomic read of 32 bits words */ static -DRXStatus_t DRXJ_DAP_AtomicReadReg32 ( - pI2CDeviceAddr_t devAddr, - DRXaddr_t addr, - pu32_t data, - DRXflags_t flags) +DRXStatus_t DRXJ_DAP_AtomicReadReg32(pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + pu32_t data, DRXflags_t flags) { - u8_t buf[sizeof (*data)]; - DRXStatus_t rc = DRX_STS_ERROR; - u32_t word = 0; + u8_t buf[sizeof(*data)]; + DRXStatus_t rc = DRX_STS_ERROR; + u32_t word = 0; - if (!data) - { - return DRX_STS_INVALID_ARG; - } + if (!data) { + return DRX_STS_INVALID_ARG; + } - rc = DRXJ_DAP_AtomicReadWriteBlock ( devAddr, addr, - sizeof (*data), buf, TRUE); + rc = DRXJ_DAP_AtomicReadWriteBlock(devAddr, addr, + sizeof(*data), buf, TRUE); - word = (u32_t)buf[3]; - word <<= 8; - word |= (u32_t)buf[2]; - word <<= 8; - word |= (u32_t)buf[1]; - word <<= 8; - word |= (u32_t)buf[0]; + word = (u32_t) buf[3]; + word <<= 8; + word |= (u32_t) buf[2]; + word <<= 8; + word |= (u32_t) buf[1]; + word <<= 8; + word |= (u32_t) buf[0]; - *data = word; + *data = word; - return rc; + return rc; } - /*============================================================================*/ - /*============================================================================*/ /*== END DRXJ DAP FUNCTIONS ==*/ /*============================================================================*/ @@ -2372,32 +2219,31 @@ DRXStatus_t DRXJ_DAP_AtomicReadReg32 ( * enable/disable should not need re-configuration of the HI. * */ -static DRXStatus_t -HICfgCommand(const pDRXDemodInstance_t demod) +static DRXStatus_t HICfgCommand(const pDRXDemodInstance_t demod) { - pDRXJData_t extAttr = (pDRXJData_t)(NULL); - DRXJHiCmd_t hiCmd; - u16_t result=0; + pDRXJData_t extAttr = (pDRXJData_t) (NULL); + DRXJHiCmd_t hiCmd; + u16_t result = 0; - extAttr = (pDRXJData_t)demod -> myExtAttr; + extAttr = (pDRXJData_t) demod->myExtAttr; - hiCmd.cmd = SIO_HI_RA_RAM_CMD_CONFIG; - hiCmd.param1 = SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY; - hiCmd.param2 = extAttr -> HICfgTimingDiv; - hiCmd.param3 = extAttr -> HICfgBridgeDelay; - hiCmd.param4 = extAttr -> HICfgWakeUpKey; - hiCmd.param5 = extAttr -> HICfgCtrl; - hiCmd.param6 = extAttr -> HICfgTransmit; + hiCmd.cmd = SIO_HI_RA_RAM_CMD_CONFIG; + hiCmd.param1 = SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY; + hiCmd.param2 = extAttr->HICfgTimingDiv; + hiCmd.param3 = extAttr->HICfgBridgeDelay; + hiCmd.param4 = extAttr->HICfgWakeUpKey; + hiCmd.param5 = extAttr->HICfgCtrl; + hiCmd.param6 = extAttr->HICfgTransmit; - CHK_ERROR( HICommand( demod -> myI2CDevAddr, &hiCmd, &result) ); + CHK_ERROR(HICommand(demod->myI2CDevAddr, &hiCmd, &result)); - /* Reset power down flag (set one call only) */ - extAttr -> HICfgCtrl &= (~(SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ)); + /* Reset power down flag (set one call only) */ + extAttr->HICfgCtrl &= (~(SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ)); - return (DRX_STS_OK); + return (DRX_STS_OK); - rw_error: - return (DRX_STS_ERROR); +rw_error: + return (DRX_STS_ERROR); } /** @@ -2412,73 +2258,67 @@ HICfgCommand(const pDRXDemodInstance_t demod) * */ static DRXStatus_t -HICommand(const pI2CDeviceAddr_t devAddr, - const pDRXJHiCmd_t cmd, - pu16_t result) +HICommand(const pI2CDeviceAddr_t devAddr, const pDRXJHiCmd_t cmd, pu16_t result) { - u16_t waitCmd=0; - u16_t nrRetries = 0; - Bool_t powerdown_cmd = FALSE; - - - /* Write parameters */ - switch ( cmd->cmd ) { - - case SIO_HI_RA_RAM_CMD_CONFIG: - case SIO_HI_RA_RAM_CMD_ATOMIC_COPY: - WR16(devAddr, SIO_HI_RA_RAM_PAR_6__A, cmd->param6); - WR16(devAddr, SIO_HI_RA_RAM_PAR_5__A, cmd->param5); - WR16(devAddr, SIO_HI_RA_RAM_PAR_4__A, cmd->param4); - WR16(devAddr, SIO_HI_RA_RAM_PAR_3__A, cmd->param3); - /* fallthrough */ - case SIO_HI_RA_RAM_CMD_BRDCTRL: - WR16(devAddr, SIO_HI_RA_RAM_PAR_2__A, cmd->param2); - WR16(devAddr, SIO_HI_RA_RAM_PAR_1__A, cmd->param1); - /* fallthrough */ - case SIO_HI_RA_RAM_CMD_NULL: - /* No parameters */ - break; - - default: - return (DRX_STS_INVALID_ARG); - break; - } - - /* Write command */ - WR16(devAddr, SIO_HI_RA_RAM_CMD__A, cmd->cmd); - - if ( (cmd->cmd) == SIO_HI_RA_RAM_CMD_RESET ) - { - /* Allow for HI to reset */ - DRXBSP_HST_Sleep(1); - } - - /* Detect power down to ommit reading result */ - powerdown_cmd = (Bool_t)( ( cmd->cmd == SIO_HI_RA_RAM_CMD_CONFIG ) && - ( ((cmd->param5) & SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) == - SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ ) ); - if ( powerdown_cmd == FALSE ) - { - /* Wait until command rdy */ - do - { - nrRetries++; - if ( nrRetries > DRXJ_MAX_RETRIES ) - { - goto rw_error; - }; + u16_t waitCmd = 0; + u16_t nrRetries = 0; + Bool_t powerdown_cmd = FALSE; - RR16(devAddr, SIO_HI_RA_RAM_CMD__A, &waitCmd); - } while ( waitCmd != 0 ); + /* Write parameters */ + switch (cmd->cmd) { - /* Read result */ - RR16(devAddr, SIO_HI_RA_RAM_RES__A, result); + case SIO_HI_RA_RAM_CMD_CONFIG: + case SIO_HI_RA_RAM_CMD_ATOMIC_COPY: + WR16(devAddr, SIO_HI_RA_RAM_PAR_6__A, cmd->param6); + WR16(devAddr, SIO_HI_RA_RAM_PAR_5__A, cmd->param5); + WR16(devAddr, SIO_HI_RA_RAM_PAR_4__A, cmd->param4); + WR16(devAddr, SIO_HI_RA_RAM_PAR_3__A, cmd->param3); + /* fallthrough */ + case SIO_HI_RA_RAM_CMD_BRDCTRL: + WR16(devAddr, SIO_HI_RA_RAM_PAR_2__A, cmd->param2); + WR16(devAddr, SIO_HI_RA_RAM_PAR_1__A, cmd->param1); + /* fallthrough */ + case SIO_HI_RA_RAM_CMD_NULL: + /* No parameters */ + break; - } /* if ( powerdown_cmd == TRUE ) */ + default: + return (DRX_STS_INVALID_ARG); + break; + } + + /* Write command */ + WR16(devAddr, SIO_HI_RA_RAM_CMD__A, cmd->cmd); + + if ((cmd->cmd) == SIO_HI_RA_RAM_CMD_RESET) { + /* Allow for HI to reset */ + DRXBSP_HST_Sleep(1); + } - return (DRX_STS_OK); + /* Detect power down to ommit reading result */ + powerdown_cmd = (Bool_t) ((cmd->cmd == SIO_HI_RA_RAM_CMD_CONFIG) && + (((cmd-> + param5) & SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) + == SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ)); + if (powerdown_cmd == FALSE) { + /* Wait until command rdy */ + do { + nrRetries++; + if (nrRetries > DRXJ_MAX_RETRIES) { + goto rw_error; + }; + + RR16(devAddr, SIO_HI_RA_RAM_CMD__A, &waitCmd); + } while (waitCmd != 0); + + /* Read result */ + RR16(devAddr, SIO_HI_RA_RAM_RES__A, result); + + } + /* if ( powerdown_cmd == TRUE ) */ + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /** @@ -2494,59 +2334,56 @@ rw_error: * bridging is controlled. * */ -static DRXStatus_t -InitHI( const pDRXDemodInstance_t demod ) +static DRXStatus_t InitHI(const pDRXDemodInstance_t demod) { - pDRXJData_t extAttr =(pDRXJData_t)(NULL); - pDRXCommonAttr_t commonAttr =(pDRXCommonAttr_t)(NULL); - pI2CDeviceAddr_t devAddr =(pI2CDeviceAddr_t)(NULL); - - extAttr = (pDRXJData_t) demod -> myExtAttr; - commonAttr = (pDRXCommonAttr_t) demod -> myCommonAttr; - devAddr = demod -> myI2CDevAddr; - - /* PATCH for bug 5003, HI ucode v3.1.0 */ - WR16( devAddr, 0x4301D7, 0x801 ); - - /* Timing div, 250ns/Psys */ - /* Timing div, = ( delay (nano seconds) * sysclk (kHz) )/ 1000 */ - extAttr -> HICfgTimingDiv = - (u16_t)((commonAttr->sysClockFreq/1000)* HI_I2C_DELAY)/1000 ; - /* Clipping */ - if ( (extAttr -> HICfgTimingDiv) > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M ) - { - extAttr -> HICfgTimingDiv = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M; - } - /* Bridge delay, uses oscilator clock */ - /* Delay = ( delay (nano seconds) * oscclk (kHz) )/ 1000 */ - /* SDA brdige delay */ - extAttr -> HICfgBridgeDelay = - (u16_t)((commonAttr->oscClockFreq/1000)* HI_I2C_BRIDGE_DELAY)/1000 ; - /* Clipping */ - if ( (extAttr -> HICfgBridgeDelay) > SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M ) - { - extAttr -> HICfgBridgeDelay = SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M; - } - /* SCL bridge delay, same as SDA for now */ - extAttr -> HICfgBridgeDelay += ((extAttr -> HICfgBridgeDelay)<< - SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B); - /* Wakeup key, setting the read flag (as suggest in the documentation) does - not always result into a working solution (barebones worked VI2C failed). - Not setting the bit works in all cases . */ - extAttr -> HICfgWakeUpKey = DRXJ_WAKE_UP_KEY; - /* port/bridge/power down ctrl */ - extAttr -> HICfgCtrl = ( SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE ); - /* transit mode time out delay and watch dog divider */ - extAttr ->HICfgTransmit = SIO_HI_RA_RAM_PAR_6__PRE; - - CHK_ERROR( HICfgCommand( demod ) ); - - return (DRX_STS_OK); - - rw_error: - return (DRX_STS_ERROR); -} + pDRXJData_t extAttr = (pDRXJData_t) (NULL); + pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) (NULL); + + extAttr = (pDRXJData_t) demod->myExtAttr; + commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; + devAddr = demod->myI2CDevAddr; + + /* PATCH for bug 5003, HI ucode v3.1.0 */ + WR16(devAddr, 0x4301D7, 0x801); + /* Timing div, 250ns/Psys */ + /* Timing div, = ( delay (nano seconds) * sysclk (kHz) )/ 1000 */ + extAttr->HICfgTimingDiv = + (u16_t) ((commonAttr->sysClockFreq / 1000) * HI_I2C_DELAY) / 1000; + /* Clipping */ + if ((extAttr->HICfgTimingDiv) > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M) { + extAttr->HICfgTimingDiv = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M; + } + /* Bridge delay, uses oscilator clock */ + /* Delay = ( delay (nano seconds) * oscclk (kHz) )/ 1000 */ + /* SDA brdige delay */ + extAttr->HICfgBridgeDelay = + (u16_t) ((commonAttr->oscClockFreq / 1000) * HI_I2C_BRIDGE_DELAY) / + 1000; + /* Clipping */ + if ((extAttr->HICfgBridgeDelay) > SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) { + extAttr->HICfgBridgeDelay = SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M; + } + /* SCL bridge delay, same as SDA for now */ + extAttr->HICfgBridgeDelay += ((extAttr->HICfgBridgeDelay) << + SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B); + /* Wakeup key, setting the read flag (as suggest in the documentation) does + not always result into a working solution (barebones worked VI2C failed). + Not setting the bit works in all cases . */ + extAttr->HICfgWakeUpKey = DRXJ_WAKE_UP_KEY; + /* port/bridge/power down ctrl */ + extAttr->HICfgCtrl = (SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE); + /* transit mode time out delay and watch dog divider */ + extAttr->HICfgTransmit = SIO_HI_RA_RAM_PAR_6__PRE; + + CHK_ERROR(HICfgCommand(demod)); + + return (DRX_STS_OK); + +rw_error: + return (DRX_STS_ERROR); +} /*============================================================================*/ /*== END HOST INTERFACE FUNCTIONS ==*/ @@ -2574,171 +2411,167 @@ InitHI( const pDRXDemodInstance_t demod ) * * extAttr->hasOOB * */ -static DRXStatus_t -GetDeviceCapabilities( pDRXDemodInstance_t demod ) +static DRXStatus_t GetDeviceCapabilities(pDRXDemodInstance_t demod) { - pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t)(NULL); - pDRXJData_t extAttr = (pDRXJData_t)NULL; - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)(NULL); - u16_t sioPdrOhwCfg = 0; - u32_t sioTopJtagidLo = 0; - u16_t bid = 0; - - commonAttr = (pDRXCommonAttr_t) demod -> myCommonAttr; - extAttr = (pDRXJData_t) demod -> myExtAttr; - devAddr = demod -> myI2CDevAddr; - - WR16 ( devAddr, SIO_TOP_COMM_KEY__A , SIO_TOP_COMM_KEY_KEY); - RR16 ( devAddr, SIO_PDR_OHW_CFG__A , &sioPdrOhwCfg); - WR16 ( devAddr, SIO_TOP_COMM_KEY__A , SIO_TOP_COMM_KEY__PRE); - - switch ( (sioPdrOhwCfg & SIO_PDR_OHW_CFG_FREF_SEL__M ) ) - { - case 0: - /* ignore (bypass ?)*/ - break; - case 1: - /* 27 MHz */ - commonAttr->oscClockFreq = 27000; - break; - case 2: - /* 20.25 MHz */ - commonAttr->oscClockFreq = 20250; - break; - case 3: - /* 4 MHz */ - commonAttr->oscClockFreq = 4000; - break; - default: - return (DRX_STS_ERROR); - } - - /* - Determine device capabilities - Based on pinning v47 - */ - RR32( devAddr, SIO_TOP_JTAGID_LO__A , &sioTopJtagidLo); - extAttr->mfx = (u8_t)((sioTopJtagidLo>>29)&0xF) ; - - switch ((sioTopJtagidLo>>12)&0xFF) - { - case 0x31: - WR16( devAddr, SIO_TOP_COMM_KEY__A , SIO_TOP_COMM_KEY_KEY); - RR16( devAddr, SIO_PDR_UIO_IN_HI__A , &bid); - bid = (bid >> 10) & 0xf; - WR16( devAddr, SIO_TOP_COMM_KEY__A , SIO_TOP_COMM_KEY__PRE); - - extAttr->hasLNA = TRUE; - extAttr->hasNTSC = FALSE; - extAttr->hasBTSC = FALSE; - extAttr->hasOOB = FALSE; - extAttr->hasSMATX = TRUE; - extAttr->hasSMARX = FALSE; - extAttr->hasGPIO = FALSE; - extAttr->hasIRQN = FALSE; - break; - case 0x33: - extAttr->hasLNA = FALSE; - extAttr->hasNTSC = FALSE; - extAttr->hasBTSC = FALSE; - extAttr->hasOOB = FALSE; - extAttr->hasSMATX = TRUE; - extAttr->hasSMARX = FALSE; - extAttr->hasGPIO = FALSE; - extAttr->hasIRQN = FALSE; - break; - case 0x45: - extAttr->hasLNA = TRUE; - extAttr->hasNTSC = TRUE; - extAttr->hasBTSC = FALSE; - extAttr->hasOOB = FALSE; - extAttr->hasSMATX = TRUE; - extAttr->hasSMARX = TRUE; - extAttr->hasGPIO = TRUE; - extAttr->hasIRQN = FALSE; - break; - case 0x46: - extAttr->hasLNA = FALSE; - extAttr->hasNTSC = TRUE; - extAttr->hasBTSC = FALSE; - extAttr->hasOOB = FALSE; - extAttr->hasSMATX = TRUE; - extAttr->hasSMARX = TRUE; - extAttr->hasGPIO = TRUE; - extAttr->hasIRQN = FALSE; - break; - case 0x41: - extAttr->hasLNA = TRUE; - extAttr->hasNTSC = TRUE; - extAttr->hasBTSC = TRUE; - extAttr->hasOOB = FALSE; - extAttr->hasSMATX = TRUE; - extAttr->hasSMARX = TRUE; - extAttr->hasGPIO = TRUE; - extAttr->hasIRQN = FALSE; - break; - case 0x43: - extAttr->hasLNA = FALSE; - extAttr->hasNTSC = TRUE; - extAttr->hasBTSC = TRUE; - extAttr->hasOOB = FALSE; - extAttr->hasSMATX = TRUE; - extAttr->hasSMARX = TRUE; - extAttr->hasGPIO = TRUE; - extAttr->hasIRQN = FALSE; - break; - case 0x32: - extAttr->hasLNA = TRUE; - extAttr->hasNTSC = FALSE; - extAttr->hasBTSC = FALSE; - extAttr->hasOOB = TRUE; - extAttr->hasSMATX = TRUE; - extAttr->hasSMARX = TRUE; - extAttr->hasGPIO = TRUE; - extAttr->hasIRQN = TRUE; - break; - case 0x34: - extAttr->hasLNA = FALSE; - extAttr->hasNTSC = TRUE; - extAttr->hasBTSC = TRUE; - extAttr->hasOOB = TRUE; - extAttr->hasSMATX = TRUE; - extAttr->hasSMARX = TRUE; - extAttr->hasGPIO = TRUE; - extAttr->hasIRQN = TRUE; - break; - case 0x42: - extAttr->hasLNA = TRUE ; - extAttr->hasNTSC = TRUE ; - extAttr->hasBTSC = TRUE ; - extAttr->hasOOB = TRUE ; - extAttr->hasSMATX = TRUE; - extAttr->hasSMARX = TRUE; - extAttr->hasGPIO = TRUE; - extAttr->hasIRQN = TRUE; - break; - case 0x44: - extAttr->hasLNA = FALSE; - extAttr->hasNTSC = TRUE; - extAttr->hasBTSC = TRUE; - extAttr->hasOOB = TRUE; - extAttr->hasSMATX = TRUE; - extAttr->hasSMARX = TRUE; - extAttr->hasGPIO = TRUE; - extAttr->hasIRQN = TRUE; - break; - default: - /* Unknown device variant */ - return (DRX_STS_ERROR); - break; - } - - return (DRX_STS_OK); + pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); + pDRXJData_t extAttr = (pDRXJData_t) NULL; + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) (NULL); + u16_t sioPdrOhwCfg = 0; + u32_t sioTopJtagidLo = 0; + u16_t bid = 0; + + commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; + extAttr = (pDRXJData_t) demod->myExtAttr; + devAddr = demod->myI2CDevAddr; + + WR16(devAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); + RR16(devAddr, SIO_PDR_OHW_CFG__A, &sioPdrOhwCfg); + WR16(devAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE); + + switch ((sioPdrOhwCfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) { + case 0: + /* ignore (bypass ?) */ + break; + case 1: + /* 27 MHz */ + commonAttr->oscClockFreq = 27000; + break; + case 2: + /* 20.25 MHz */ + commonAttr->oscClockFreq = 20250; + break; + case 3: + /* 4 MHz */ + commonAttr->oscClockFreq = 4000; + break; + default: + return (DRX_STS_ERROR); + } + + /* + Determine device capabilities + Based on pinning v47 + */ + RR32(devAddr, SIO_TOP_JTAGID_LO__A, &sioTopJtagidLo); + extAttr->mfx = (u8_t) ((sioTopJtagidLo >> 29) & 0xF); + + switch ((sioTopJtagidLo >> 12) & 0xFF) { + case 0x31: + WR16(devAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); + RR16(devAddr, SIO_PDR_UIO_IN_HI__A, &bid); + bid = (bid >> 10) & 0xf; + WR16(devAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE); + + extAttr->hasLNA = TRUE; + extAttr->hasNTSC = FALSE; + extAttr->hasBTSC = FALSE; + extAttr->hasOOB = FALSE; + extAttr->hasSMATX = TRUE; + extAttr->hasSMARX = FALSE; + extAttr->hasGPIO = FALSE; + extAttr->hasIRQN = FALSE; + break; + case 0x33: + extAttr->hasLNA = FALSE; + extAttr->hasNTSC = FALSE; + extAttr->hasBTSC = FALSE; + extAttr->hasOOB = FALSE; + extAttr->hasSMATX = TRUE; + extAttr->hasSMARX = FALSE; + extAttr->hasGPIO = FALSE; + extAttr->hasIRQN = FALSE; + break; + case 0x45: + extAttr->hasLNA = TRUE; + extAttr->hasNTSC = TRUE; + extAttr->hasBTSC = FALSE; + extAttr->hasOOB = FALSE; + extAttr->hasSMATX = TRUE; + extAttr->hasSMARX = TRUE; + extAttr->hasGPIO = TRUE; + extAttr->hasIRQN = FALSE; + break; + case 0x46: + extAttr->hasLNA = FALSE; + extAttr->hasNTSC = TRUE; + extAttr->hasBTSC = FALSE; + extAttr->hasOOB = FALSE; + extAttr->hasSMATX = TRUE; + extAttr->hasSMARX = TRUE; + extAttr->hasGPIO = TRUE; + extAttr->hasIRQN = FALSE; + break; + case 0x41: + extAttr->hasLNA = TRUE; + extAttr->hasNTSC = TRUE; + extAttr->hasBTSC = TRUE; + extAttr->hasOOB = FALSE; + extAttr->hasSMATX = TRUE; + extAttr->hasSMARX = TRUE; + extAttr->hasGPIO = TRUE; + extAttr->hasIRQN = FALSE; + break; + case 0x43: + extAttr->hasLNA = FALSE; + extAttr->hasNTSC = TRUE; + extAttr->hasBTSC = TRUE; + extAttr->hasOOB = FALSE; + extAttr->hasSMATX = TRUE; + extAttr->hasSMARX = TRUE; + extAttr->hasGPIO = TRUE; + extAttr->hasIRQN = FALSE; + break; + case 0x32: + extAttr->hasLNA = TRUE; + extAttr->hasNTSC = FALSE; + extAttr->hasBTSC = FALSE; + extAttr->hasOOB = TRUE; + extAttr->hasSMATX = TRUE; + extAttr->hasSMARX = TRUE; + extAttr->hasGPIO = TRUE; + extAttr->hasIRQN = TRUE; + break; + case 0x34: + extAttr->hasLNA = FALSE; + extAttr->hasNTSC = TRUE; + extAttr->hasBTSC = TRUE; + extAttr->hasOOB = TRUE; + extAttr->hasSMATX = TRUE; + extAttr->hasSMARX = TRUE; + extAttr->hasGPIO = TRUE; + extAttr->hasIRQN = TRUE; + break; + case 0x42: + extAttr->hasLNA = TRUE; + extAttr->hasNTSC = TRUE; + extAttr->hasBTSC = TRUE; + extAttr->hasOOB = TRUE; + extAttr->hasSMATX = TRUE; + extAttr->hasSMARX = TRUE; + extAttr->hasGPIO = TRUE; + extAttr->hasIRQN = TRUE; + break; + case 0x44: + extAttr->hasLNA = FALSE; + extAttr->hasNTSC = TRUE; + extAttr->hasBTSC = TRUE; + extAttr->hasOOB = TRUE; + extAttr->hasSMATX = TRUE; + extAttr->hasSMARX = TRUE; + extAttr->hasGPIO = TRUE; + extAttr->hasIRQN = TRUE; + break; + default: + /* Unknown device variant */ + return (DRX_STS_ERROR); + break; + } + + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } - /** * \fn DRXStatus_t PowerUpDevice() * \brief Power up device. @@ -2753,42 +2586,40 @@ rw_error: #define DRXJ_MAX_RETRIES_POWERUP 10 #endif -static DRXStatus_t -PowerUpDevice( pDRXDemodInstance_t demod ) -{ - pI2CDeviceAddr_t devAddr =(pI2CDeviceAddr_t)(NULL); - u8_t data = 0 ; - u16_t retryCount = 0; - I2CDeviceAddr_t wakeUpAddr; - - devAddr = demod->myI2CDevAddr; - wakeUpAddr.i2cAddr = DRXJ_WAKE_UP_KEY; - wakeUpAddr.i2cDevId = devAddr->i2cDevId; - wakeUpAddr.userData = devAddr->userData; - /* CHK_ERROR macro not used, I2C access may fail in this case: no ack - dummy write must be used to wake uop device, dummy read must be used to - reset HI state machine (avoiding actual writes) */ - do - { - data = 0; - DRXBSP_I2C_WriteRead( &wakeUpAddr, 1, &data, - (pI2CDeviceAddr_t)(NULL), 0, (pu8_t)(NULL) ); - DRXBSP_HST_Sleep(10); - retryCount++ ; - }while ( (DRXBSP_I2C_WriteRead( (pI2CDeviceAddr_t)(NULL), 0, (pu8_t)(NULL), - devAddr, 1, &data ) - != DRX_STS_OK ) && - (retryCount < DRXJ_MAX_RETRIES_POWERUP) ); - - /* Need some recovery time .... */ - DRXBSP_HST_Sleep(10); - - if ( retryCount == DRXJ_MAX_RETRIES_POWERUP ) - { - return (DRX_STS_ERROR); - } +static DRXStatus_t PowerUpDevice(pDRXDemodInstance_t demod) +{ + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) (NULL); + u8_t data = 0; + u16_t retryCount = 0; + I2CDeviceAddr_t wakeUpAddr; + + devAddr = demod->myI2CDevAddr; + wakeUpAddr.i2cAddr = DRXJ_WAKE_UP_KEY; + wakeUpAddr.i2cDevId = devAddr->i2cDevId; + wakeUpAddr.userData = devAddr->userData; + /* CHK_ERROR macro not used, I2C access may fail in this case: no ack + dummy write must be used to wake uop device, dummy read must be used to + reset HI state machine (avoiding actual writes) */ + do { + data = 0; + DRXBSP_I2C_WriteRead(&wakeUpAddr, 1, &data, + (pI2CDeviceAddr_t) (NULL), 0, + (pu8_t) (NULL)); + DRXBSP_HST_Sleep(10); + retryCount++; + } while ((DRXBSP_I2C_WriteRead + ((pI2CDeviceAddr_t) (NULL), 0, (pu8_t) (NULL), devAddr, 1, + &data) + != DRX_STS_OK) && (retryCount < DRXJ_MAX_RETRIES_POWERUP)); + + /* Need some recovery time .... */ + DRXBSP_HST_Sleep(10); + + if (retryCount == DRXJ_MAX_RETRIES_POWERUP) { + return (DRX_STS_ERROR); + } - return (DRX_STS_OK); + return (DRX_STS_OK); } /*----------------------------------------------------------------------------*/ @@ -2805,407 +2636,393 @@ PowerUpDevice( pDRXDemodInstance_t demod ) * */ static DRXStatus_t -CtrlSetCfgMPEGOutput( pDRXDemodInstance_t demod, - pDRXCfgMPEGOutput_t cfgData ) -{ - pI2CDeviceAddr_t devAddr =(pI2CDeviceAddr_t)(NULL); - pDRXJData_t extAttr =(pDRXJData_t)(NULL); - pDRXCommonAttr_t commonAttr =(pDRXCommonAttr_t)(NULL); - u16_t fecOcRegMode = 0; - u16_t fecOcRegIprMode = 0; - u16_t fecOcRegIprInvert = 0; - u32_t maxBitRate = 0; - u32_t rcnRate = 0; - u32_t nrBits = 0; - u16_t sioPdrMdCfg = 0; - /* data mask for the output data byte */ - u16_t InvertDataMask = FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M | - FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M | - FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M | - FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M; - /* check arguments */ - if (( demod == NULL ) || - ( cfgData == NULL )) - { - return (DRX_STS_INVALID_ARG); - } - - devAddr = demod -> myI2CDevAddr; - extAttr = (pDRXJData_t) demod -> myExtAttr; - commonAttr = (pDRXCommonAttr_t) demod -> myCommonAttr; +CtrlSetCfgMPEGOutput(pDRXDemodInstance_t demod, pDRXCfgMPEGOutput_t cfgData) +{ + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) (NULL); + pDRXJData_t extAttr = (pDRXJData_t) (NULL); + pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); + u16_t fecOcRegMode = 0; + u16_t fecOcRegIprMode = 0; + u16_t fecOcRegIprInvert = 0; + u32_t maxBitRate = 0; + u32_t rcnRate = 0; + u32_t nrBits = 0; + u16_t sioPdrMdCfg = 0; + /* data mask for the output data byte */ + u16_t InvertDataMask = + FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M | + FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M | + FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M | + FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M; + /* check arguments */ + if ((demod == NULL) || (cfgData == NULL)) { + return (DRX_STS_INVALID_ARG); + } - if ( cfgData->enableMPEGOutput == TRUE ) - { - /* quick and dirty patch to set MPEG incase current std is not - producing MPEG */ - switch ( extAttr->standard ) - { - case DRX_STANDARD_8VSB: - case DRX_STANDARD_ITU_A: - case DRX_STANDARD_ITU_B: - case DRX_STANDARD_ITU_C: - break; - default: - /* not an MPEG producing std, just store MPEG cfg */ - commonAttr->mpegCfg.enableMPEGOutput = cfgData->enableMPEGOutput; - commonAttr->mpegCfg.insertRSByte = cfgData->insertRSByte; - commonAttr->mpegCfg.enableParallel = cfgData->enableParallel; - commonAttr->mpegCfg.invertDATA = cfgData->invertDATA; - commonAttr->mpegCfg.invertERR = cfgData->invertERR; - commonAttr->mpegCfg.invertSTR = cfgData->invertSTR; - commonAttr->mpegCfg.invertVAL = cfgData->invertVAL; - commonAttr->mpegCfg.invertCLK = cfgData->invertCLK; - commonAttr->mpegCfg.staticCLK = cfgData->staticCLK; - commonAttr->mpegCfg.bitrate = cfgData->bitrate; - return (DRX_STS_OK); - } - - WR16( devAddr, FEC_OC_OCR_INVERT__A, 0); - switch (extAttr->standard) - { - case DRX_STANDARD_8VSB: - WR16( devAddr, FEC_OC_FCT_USAGE__A, 7 ); /* 2048 bytes fifo ram */ - WR16( devAddr, FEC_OC_TMD_CTL_UPD_RATE__A, 10); - WR16( devAddr, FEC_OC_TMD_INT_UPD_RATE__A, 10); - WR16( devAddr, FEC_OC_AVR_PARM_A__A, 5); - WR16( devAddr, FEC_OC_AVR_PARM_B__A, 7); - WR16( devAddr, FEC_OC_RCN_GAIN__A, 10); - /* Low Water Mark for synchronization */ - WR16( devAddr, FEC_OC_SNC_LWM__A, 3 ); - /* High Water Mark for synchronization */ - WR16( devAddr, FEC_OC_SNC_HWM__A, 5 ); - break; - case DRX_STANDARD_ITU_A: - case DRX_STANDARD_ITU_C: - switch ( extAttr->constellation ) - { - case DRX_CONSTELLATION_QAM256: - nrBits = 8; - break; - case DRX_CONSTELLATION_QAM128: - nrBits = 7; - break; - case DRX_CONSTELLATION_QAM64: - nrBits = 6; - break; - case DRX_CONSTELLATION_QAM32: - nrBits = 5; - break; - case DRX_CONSTELLATION_QAM16: - nrBits = 4; - break; - default: - return (DRX_STS_ERROR); - } /* extAttr->constellation */ - /* maxBitRate = symbolRate * nrBits * coef */ - /* coef = 188/204 */ - maxBitRate = ( extAttr->currSymbolRate / 8 ) * nrBits * 188; - /* pass through b/c Annex A/c need following settings */ - case DRX_STANDARD_ITU_B: - WR16( devAddr, FEC_OC_FCT_USAGE__A, FEC_OC_FCT_USAGE__PRE); - WR16( devAddr, FEC_OC_TMD_CTL_UPD_RATE__A, FEC_OC_TMD_CTL_UPD_RATE__PRE); - WR16( devAddr, FEC_OC_TMD_INT_UPD_RATE__A, 5); - WR16( devAddr, FEC_OC_AVR_PARM_A__A, FEC_OC_AVR_PARM_A__PRE); - WR16( devAddr, FEC_OC_AVR_PARM_B__A, FEC_OC_AVR_PARM_B__PRE); - if (cfgData->staticCLK == TRUE) - { - WR16( devAddr, FEC_OC_RCN_GAIN__A, 0xD ); - } - else - { - WR16( devAddr, FEC_OC_RCN_GAIN__A, FEC_OC_RCN_GAIN__PRE ); - } - WR16( devAddr, FEC_OC_SNC_LWM__A, 2); - WR16( devAddr, FEC_OC_SNC_HWM__A, 12); - break; - default: - break; - }/* swtich (standard) */ - - /* Check insertion of the Reed-Solomon parity bytes */ - RR16( devAddr, FEC_OC_MODE__A , &fecOcRegMode ); - RR16( devAddr, FEC_OC_IPR_MODE__A, &fecOcRegIprMode ); - if ( cfgData->insertRSByte == TRUE ) - { - /* enable parity symbol forward */ - fecOcRegMode |= FEC_OC_MODE_PARITY__M; - /* MVAL disable during parity bytes */ - fecOcRegIprMode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M; - switch ( extAttr->standard ) - { - case DRX_STANDARD_8VSB: - rcnRate = 0x004854D3; - break; - case DRX_STANDARD_ITU_B: - fecOcRegMode |= FEC_OC_MODE_TRANSPARENT__M; - switch ( extAttr->constellation ) - { - case DRX_CONSTELLATION_QAM256: - rcnRate = 0x008945E7; - break; - case DRX_CONSTELLATION_QAM64: - rcnRate = 0x005F64D4; - break; - default: - return (DRX_STS_ERROR); - } - break; - case DRX_STANDARD_ITU_A: - case DRX_STANDARD_ITU_C: - /* insertRSByte = TRUE -> coef = 188/188 -> 1, RS bits are in MPEG output */ - rcnRate = ( Frac28 ( maxBitRate, ( u32_t )( commonAttr->sysClockFreq / 8 ) ) ) / 188; - break; - default: - return (DRX_STS_ERROR); - } /* extAttr->standard */ - } - else /* insertRSByte == FALSE */ - { - /* disable parity symbol forward */ - fecOcRegMode &= (~FEC_OC_MODE_PARITY__M); - /* MVAL enable during parity bytes */ - fecOcRegIprMode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M); - switch ( extAttr->standard ) - { - case DRX_STANDARD_8VSB: - rcnRate = 0x0041605C; - break; - case DRX_STANDARD_ITU_B: - fecOcRegMode &= (~FEC_OC_MODE_TRANSPARENT__M); - switch ( extAttr->constellation ) - { - case DRX_CONSTELLATION_QAM256: - rcnRate = 0x0082D6A0; - break; - case DRX_CONSTELLATION_QAM64: - rcnRate = 0x005AEC1A; - break; - default: - return (DRX_STS_ERROR); - } - break; - case DRX_STANDARD_ITU_A: - case DRX_STANDARD_ITU_C: - /* insertRSByte = FALSE -> coef = 188/204, RS bits not in MPEG output */ - rcnRate = ( Frac28 ( maxBitRate, ( u32_t )( commonAttr->sysClockFreq / 8 ) ) ) / 204; - break; - default: - return (DRX_STS_ERROR); - } /* extAttr->standard */ - } - - if ( cfgData->enableParallel == TRUE ) - { /* MPEG data output is paralel -> clear ipr_mode[0] */ - fecOcRegIprMode &= (~(FEC_OC_IPR_MODE_SERIAL__M)); - } - else - { /* MPEG data output is serial -> set ipr_mode[0] */ - fecOcRegIprMode |= FEC_OC_IPR_MODE_SERIAL__M; - } - - /* Control slective inversion of output bits */ - if ( cfgData->invertDATA == TRUE ) - { - fecOcRegIprInvert |= InvertDataMask; - } - else - { - fecOcRegIprInvert &= (~(InvertDataMask)); - } - - if ( cfgData->invertERR == TRUE ) - { - fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MERR__M; - } - else - { - fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MERR__M)); - } - - if ( cfgData->invertSTR == TRUE ) - { - fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MSTRT__M; - } - else - { - fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MSTRT__M)); - } - - if ( cfgData->invertVAL == TRUE ) - { - fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MVAL__M; - } - else - { - fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MVAL__M)); - } - - if ( cfgData->invertCLK == TRUE ) - { - fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MCLK__M; - } - else - { - fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MCLK__M)); - } - - if ( cfgData->staticCLK == TRUE ) /* Static mode */ - { - u32_t dtoRate = 0; - u32_t bitRate = 0; - u16_t fecOcDtoBurstLen = 0; - u16_t fecOcDtoPeriod = 0; - - fecOcDtoBurstLen = FEC_OC_DTO_BURST_LEN__PRE; - - switch ( extAttr->standard ) - { - case DRX_STANDARD_8VSB: - fecOcDtoPeriod = 4; - if ( cfgData->insertRSByte == TRUE ) - { - fecOcDtoBurstLen = 208; - } - break; - case DRX_STANDARD_ITU_A: - { - u32_t symbolRateTh = 6400000; - if ( cfgData->insertRSByte == TRUE ) - { - fecOcDtoBurstLen = 204; - symbolRateTh = 5900000; - } - if ( extAttr->currSymbolRate >= symbolRateTh) - { - fecOcDtoPeriod = 0; - } - else - { - fecOcDtoPeriod = 1; - } - } - break; - case DRX_STANDARD_ITU_B: - fecOcDtoPeriod = 1; - if ( cfgData->insertRSByte == TRUE ) - { - fecOcDtoBurstLen = 128; - } - break; - case DRX_STANDARD_ITU_C: - fecOcDtoPeriod = 1; - if ( cfgData->insertRSByte == TRUE ) - { - fecOcDtoBurstLen = 204; - } - break; - default: - return (DRX_STS_ERROR); - } - bitRate = commonAttr->sysClockFreq * 1000 / (fecOcDtoPeriod + 2); - dtoRate = Frac28(bitRate, commonAttr->sysClockFreq * 1000 ); - dtoRate >>= 3; - WR16 ( devAddr, FEC_OC_DTO_RATE_HI__A, (u16_t) ((dtoRate >> 16) & FEC_OC_DTO_RATE_HI__M) ); - WR16 ( devAddr, FEC_OC_DTO_RATE_LO__A, (u16_t) (dtoRate & FEC_OC_DTO_RATE_LO_RATE_LO__M) ); - WR16 ( devAddr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M | FEC_OC_DTO_MODE_OFFSET_ENABLE__M ); - WR16 ( devAddr, FEC_OC_FCT_MODE__A, FEC_OC_FCT_MODE_RAT_ENA__M | FEC_OC_FCT_MODE_VIRT_ENA__M ); - WR16 ( devAddr, FEC_OC_DTO_BURST_LEN__A, fecOcDtoBurstLen ); - if ( extAttr->mpegOutputClockRate != DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO ) - fecOcDtoPeriod = extAttr->mpegOutputClockRate - 1; - WR16 ( devAddr, FEC_OC_DTO_PERIOD__A, fecOcDtoPeriod ); - } - else /* Dynamic mode */ - { - WR16 ( devAddr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M ); - WR16 ( devAddr, FEC_OC_FCT_MODE__A, 0 ); - } - - WR32 ( devAddr, FEC_OC_RCN_CTL_RATE_LO__A, rcnRate ); - - /* Write appropriate registers with requested configuration */ - WR16 ( devAddr, FEC_OC_MODE__A, fecOcRegMode ); - WR16 ( devAddr, FEC_OC_IPR_MODE__A, fecOcRegIprMode ); - WR16 ( devAddr, FEC_OC_IPR_INVERT__A, fecOcRegIprInvert ); - - /* enabling for both parallel and serial now */ - /* Write magic word to enable pdr reg write */ - WR16 ( devAddr, SIO_TOP_COMM_KEY__A, 0xFABA); - /* Set MPEG TS pads to outputmode */ - WR16 ( devAddr, SIO_PDR_MSTRT_CFG__A, 0x0013); - WR16 ( devAddr, SIO_PDR_MERR_CFG__A, 0x0013); - WR16 ( devAddr, SIO_PDR_MCLK_CFG__A, + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; + commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; + + if (cfgData->enableMPEGOutput == TRUE) { + /* quick and dirty patch to set MPEG incase current std is not + producing MPEG */ + switch (extAttr->standard) { + case DRX_STANDARD_8VSB: + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: + break; + default: + /* not an MPEG producing std, just store MPEG cfg */ + commonAttr->mpegCfg.enableMPEGOutput = + cfgData->enableMPEGOutput; + commonAttr->mpegCfg.insertRSByte = + cfgData->insertRSByte; + commonAttr->mpegCfg.enableParallel = + cfgData->enableParallel; + commonAttr->mpegCfg.invertDATA = cfgData->invertDATA; + commonAttr->mpegCfg.invertERR = cfgData->invertERR; + commonAttr->mpegCfg.invertSTR = cfgData->invertSTR; + commonAttr->mpegCfg.invertVAL = cfgData->invertVAL; + commonAttr->mpegCfg.invertCLK = cfgData->invertCLK; + commonAttr->mpegCfg.staticCLK = cfgData->staticCLK; + commonAttr->mpegCfg.bitrate = cfgData->bitrate; + return (DRX_STS_OK); + } + + WR16(devAddr, FEC_OC_OCR_INVERT__A, 0); + switch (extAttr->standard) { + case DRX_STANDARD_8VSB: + WR16(devAddr, FEC_OC_FCT_USAGE__A, 7); /* 2048 bytes fifo ram */ + WR16(devAddr, FEC_OC_TMD_CTL_UPD_RATE__A, 10); + WR16(devAddr, FEC_OC_TMD_INT_UPD_RATE__A, 10); + WR16(devAddr, FEC_OC_AVR_PARM_A__A, 5); + WR16(devAddr, FEC_OC_AVR_PARM_B__A, 7); + WR16(devAddr, FEC_OC_RCN_GAIN__A, 10); + /* Low Water Mark for synchronization */ + WR16(devAddr, FEC_OC_SNC_LWM__A, 3); + /* High Water Mark for synchronization */ + WR16(devAddr, FEC_OC_SNC_HWM__A, 5); + break; + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_C: + switch (extAttr->constellation) { + case DRX_CONSTELLATION_QAM256: + nrBits = 8; + break; + case DRX_CONSTELLATION_QAM128: + nrBits = 7; + break; + case DRX_CONSTELLATION_QAM64: + nrBits = 6; + break; + case DRX_CONSTELLATION_QAM32: + nrBits = 5; + break; + case DRX_CONSTELLATION_QAM16: + nrBits = 4; + break; + default: + return (DRX_STS_ERROR); + } /* extAttr->constellation */ + /* maxBitRate = symbolRate * nrBits * coef */ + /* coef = 188/204 */ + maxBitRate = + (extAttr->currSymbolRate / 8) * nrBits * 188; + /* pass through b/c Annex A/c need following settings */ + case DRX_STANDARD_ITU_B: + WR16(devAddr, FEC_OC_FCT_USAGE__A, + FEC_OC_FCT_USAGE__PRE); + WR16(devAddr, FEC_OC_TMD_CTL_UPD_RATE__A, + FEC_OC_TMD_CTL_UPD_RATE__PRE); + WR16(devAddr, FEC_OC_TMD_INT_UPD_RATE__A, 5); + WR16(devAddr, FEC_OC_AVR_PARM_A__A, + FEC_OC_AVR_PARM_A__PRE); + WR16(devAddr, FEC_OC_AVR_PARM_B__A, + FEC_OC_AVR_PARM_B__PRE); + if (cfgData->staticCLK == TRUE) { + WR16(devAddr, FEC_OC_RCN_GAIN__A, 0xD); + } else { + WR16(devAddr, FEC_OC_RCN_GAIN__A, + FEC_OC_RCN_GAIN__PRE); + } + WR16(devAddr, FEC_OC_SNC_LWM__A, 2); + WR16(devAddr, FEC_OC_SNC_HWM__A, 12); + break; + default: + break; + } /* swtich (standard) */ + + /* Check insertion of the Reed-Solomon parity bytes */ + RR16(devAddr, FEC_OC_MODE__A, &fecOcRegMode); + RR16(devAddr, FEC_OC_IPR_MODE__A, &fecOcRegIprMode); + if (cfgData->insertRSByte == TRUE) { + /* enable parity symbol forward */ + fecOcRegMode |= FEC_OC_MODE_PARITY__M; + /* MVAL disable during parity bytes */ + fecOcRegIprMode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M; + switch (extAttr->standard) { + case DRX_STANDARD_8VSB: + rcnRate = 0x004854D3; + break; + case DRX_STANDARD_ITU_B: + fecOcRegMode |= FEC_OC_MODE_TRANSPARENT__M; + switch (extAttr->constellation) { + case DRX_CONSTELLATION_QAM256: + rcnRate = 0x008945E7; + break; + case DRX_CONSTELLATION_QAM64: + rcnRate = 0x005F64D4; + break; + default: + return (DRX_STS_ERROR); + } + break; + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_C: + /* insertRSByte = TRUE -> coef = 188/188 -> 1, RS bits are in MPEG output */ + rcnRate = + (Frac28 + (maxBitRate, + (u32_t) (commonAttr->sysClockFreq / 8))) / + 188; + break; + default: + return (DRX_STS_ERROR); + } /* extAttr->standard */ + } else { /* insertRSByte == FALSE */ + + /* disable parity symbol forward */ + fecOcRegMode &= (~FEC_OC_MODE_PARITY__M); + /* MVAL enable during parity bytes */ + fecOcRegIprMode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M); + switch (extAttr->standard) { + case DRX_STANDARD_8VSB: + rcnRate = 0x0041605C; + break; + case DRX_STANDARD_ITU_B: + fecOcRegMode &= (~FEC_OC_MODE_TRANSPARENT__M); + switch (extAttr->constellation) { + case DRX_CONSTELLATION_QAM256: + rcnRate = 0x0082D6A0; + break; + case DRX_CONSTELLATION_QAM64: + rcnRate = 0x005AEC1A; + break; + default: + return (DRX_STS_ERROR); + } + break; + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_C: + /* insertRSByte = FALSE -> coef = 188/204, RS bits not in MPEG output */ + rcnRate = + (Frac28 + (maxBitRate, + (u32_t) (commonAttr->sysClockFreq / 8))) / + 204; + break; + default: + return (DRX_STS_ERROR); + } /* extAttr->standard */ + } + + if (cfgData->enableParallel == TRUE) { /* MPEG data output is paralel -> clear ipr_mode[0] */ + fecOcRegIprMode &= (~(FEC_OC_IPR_MODE_SERIAL__M)); + } else { /* MPEG data output is serial -> set ipr_mode[0] */ + fecOcRegIprMode |= FEC_OC_IPR_MODE_SERIAL__M; + } + + /* Control slective inversion of output bits */ + if (cfgData->invertDATA == TRUE) { + fecOcRegIprInvert |= InvertDataMask; + } else { + fecOcRegIprInvert &= (~(InvertDataMask)); + } + + if (cfgData->invertERR == TRUE) { + fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MERR__M; + } else { + fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MERR__M)); + } + + if (cfgData->invertSTR == TRUE) { + fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MSTRT__M; + } else { + fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MSTRT__M)); + } + + if (cfgData->invertVAL == TRUE) { + fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MVAL__M; + } else { + fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MVAL__M)); + } + + if (cfgData->invertCLK == TRUE) { + fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MCLK__M; + } else { + fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MCLK__M)); + } + + if (cfgData->staticCLK == TRUE) { /* Static mode */ + u32_t dtoRate = 0; + u32_t bitRate = 0; + u16_t fecOcDtoBurstLen = 0; + u16_t fecOcDtoPeriod = 0; + + fecOcDtoBurstLen = FEC_OC_DTO_BURST_LEN__PRE; + + switch (extAttr->standard) { + case DRX_STANDARD_8VSB: + fecOcDtoPeriod = 4; + if (cfgData->insertRSByte == TRUE) { + fecOcDtoBurstLen = 208; + } + break; + case DRX_STANDARD_ITU_A: + { + u32_t symbolRateTh = 6400000; + if (cfgData->insertRSByte == TRUE) { + fecOcDtoBurstLen = 204; + symbolRateTh = 5900000; + } + if (extAttr->currSymbolRate >= + symbolRateTh) { + fecOcDtoPeriod = 0; + } else { + fecOcDtoPeriod = 1; + } + } + break; + case DRX_STANDARD_ITU_B: + fecOcDtoPeriod = 1; + if (cfgData->insertRSByte == TRUE) { + fecOcDtoBurstLen = 128; + } + break; + case DRX_STANDARD_ITU_C: + fecOcDtoPeriod = 1; + if (cfgData->insertRSByte == TRUE) { + fecOcDtoBurstLen = 204; + } + break; + default: + return (DRX_STS_ERROR); + } + bitRate = + commonAttr->sysClockFreq * 1000 / (fecOcDtoPeriod + + 2); + dtoRate = + Frac28(bitRate, commonAttr->sysClockFreq * 1000); + dtoRate >>= 3; + WR16(devAddr, FEC_OC_DTO_RATE_HI__A, + (u16_t) ((dtoRate >> 16) & FEC_OC_DTO_RATE_HI__M)); + WR16(devAddr, FEC_OC_DTO_RATE_LO__A, + (u16_t) (dtoRate & FEC_OC_DTO_RATE_LO_RATE_LO__M)); + WR16(devAddr, FEC_OC_DTO_MODE__A, + FEC_OC_DTO_MODE_DYNAMIC__M | + FEC_OC_DTO_MODE_OFFSET_ENABLE__M); + WR16(devAddr, FEC_OC_FCT_MODE__A, + FEC_OC_FCT_MODE_RAT_ENA__M | + FEC_OC_FCT_MODE_VIRT_ENA__M); + WR16(devAddr, FEC_OC_DTO_BURST_LEN__A, + fecOcDtoBurstLen); + if (extAttr->mpegOutputClockRate != + DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO) + fecOcDtoPeriod = + extAttr->mpegOutputClockRate - 1; + WR16(devAddr, FEC_OC_DTO_PERIOD__A, fecOcDtoPeriod); + } else { /* Dynamic mode */ + + WR16(devAddr, FEC_OC_DTO_MODE__A, + FEC_OC_DTO_MODE_DYNAMIC__M); + WR16(devAddr, FEC_OC_FCT_MODE__A, 0); + } + + WR32(devAddr, FEC_OC_RCN_CTL_RATE_LO__A, rcnRate); + + /* Write appropriate registers with requested configuration */ + WR16(devAddr, FEC_OC_MODE__A, fecOcRegMode); + WR16(devAddr, FEC_OC_IPR_MODE__A, fecOcRegIprMode); + WR16(devAddr, FEC_OC_IPR_INVERT__A, fecOcRegIprInvert); + + /* enabling for both parallel and serial now */ + /* Write magic word to enable pdr reg write */ + WR16(devAddr, SIO_TOP_COMM_KEY__A, 0xFABA); + /* Set MPEG TS pads to outputmode */ + WR16(devAddr, SIO_PDR_MSTRT_CFG__A, 0x0013); + WR16(devAddr, SIO_PDR_MERR_CFG__A, 0x0013); + WR16(devAddr, SIO_PDR_MCLK_CFG__A, MPEG_OUTPUT_CLK_DRIVE_STRENGTH << SIO_PDR_MCLK_CFG_DRIVE__B - | 0x03 << SIO_PDR_MCLK_CFG_MODE__B ); - WR16 ( devAddr, SIO_PDR_MVAL_CFG__A, 0x0013); - sioPdrMdCfg = MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH << SIO_PDR_MD0_CFG_DRIVE__B - |0x03 << SIO_PDR_MD0_CFG_MODE__B; - WR16 ( devAddr, SIO_PDR_MD0_CFG__A, sioPdrMdCfg); - if ( cfgData->enableParallel == TRUE ) - { /* MPEG data output is paralel -> set MD1 to MD7 to output mode */ - sioPdrMdCfg = MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH << SIO_PDR_MD0_CFG_DRIVE__B - |0x03 << SIO_PDR_MD0_CFG_MODE__B; - WR16 ( devAddr, SIO_PDR_MD0_CFG__A, sioPdrMdCfg); - WR16 ( devAddr, SIO_PDR_MD1_CFG__A, sioPdrMdCfg); - WR16 ( devAddr, SIO_PDR_MD2_CFG__A, sioPdrMdCfg); - WR16 ( devAddr, SIO_PDR_MD3_CFG__A, sioPdrMdCfg); - WR16 ( devAddr, SIO_PDR_MD4_CFG__A, sioPdrMdCfg); - WR16 ( devAddr, SIO_PDR_MD5_CFG__A, sioPdrMdCfg); - WR16 ( devAddr, SIO_PDR_MD6_CFG__A, sioPdrMdCfg); - WR16 ( devAddr, SIO_PDR_MD7_CFG__A, sioPdrMdCfg); - } - else - { /* MPEG data output is serial -> set MD1 to MD7 to tri-state */ - WR16 ( devAddr, SIO_PDR_MD1_CFG__A, 0x0000); - WR16 ( devAddr, SIO_PDR_MD2_CFG__A, 0x0000); - WR16 ( devAddr, SIO_PDR_MD3_CFG__A, 0x0000); - WR16 ( devAddr, SIO_PDR_MD4_CFG__A, 0x0000); - WR16 ( devAddr, SIO_PDR_MD5_CFG__A, 0x0000); - WR16 ( devAddr, SIO_PDR_MD6_CFG__A, 0x0000); - WR16 ( devAddr, SIO_PDR_MD7_CFG__A, 0x0000); - } - /* Enable Monitor Bus output over MPEG pads and ctl input */ - WR16 ( devAddr, SIO_PDR_MON_CFG__A, 0x0000); - /* Write nomagic word to enable pdr reg write */ - WR16 ( devAddr, SIO_TOP_COMM_KEY__A, 0x0000); - } - else - { - /* Write magic word to enable pdr reg write */ - WR16 ( devAddr, SIO_TOP_COMM_KEY__A , 0xFABA); - /* Set MPEG TS pads to inputmode */ - WR16 ( devAddr, SIO_PDR_MSTRT_CFG__A , 0x0000); - WR16 ( devAddr, SIO_PDR_MERR_CFG__A , 0x0000); - WR16 ( devAddr, SIO_PDR_MCLK_CFG__A , 0x0000); - WR16 ( devAddr, SIO_PDR_MVAL_CFG__A , 0x0000); - WR16 ( devAddr, SIO_PDR_MD0_CFG__A , 0x0000); - WR16 ( devAddr, SIO_PDR_MD1_CFG__A , 0x0000); - WR16 ( devAddr, SIO_PDR_MD2_CFG__A , 0x0000); - WR16 ( devAddr, SIO_PDR_MD3_CFG__A , 0x0000); - WR16 ( devAddr, SIO_PDR_MD4_CFG__A , 0x0000); - WR16 ( devAddr, SIO_PDR_MD5_CFG__A , 0x0000); - WR16 ( devAddr, SIO_PDR_MD6_CFG__A , 0x0000); - WR16 ( devAddr, SIO_PDR_MD7_CFG__A , 0x0000); - /* Enable Monitor Bus output over MPEG pads and ctl input */ - WR16 ( devAddr, SIO_PDR_MON_CFG__A , 0x0000); - /* Write nomagic word to enable pdr reg write */ - WR16 ( devAddr, SIO_TOP_COMM_KEY__A , 0x0000); - } - - /* save values for restore after re-acquire */ - commonAttr->mpegCfg.enableMPEGOutput = cfgData->enableMPEGOutput; - commonAttr->mpegCfg.insertRSByte = cfgData->insertRSByte; - commonAttr->mpegCfg.enableParallel = cfgData->enableParallel; - commonAttr->mpegCfg.invertDATA = cfgData->invertDATA; - commonAttr->mpegCfg.invertERR = cfgData->invertERR; - commonAttr->mpegCfg.invertSTR = cfgData->invertSTR; - commonAttr->mpegCfg.invertVAL = cfgData->invertVAL; - commonAttr->mpegCfg.invertCLK = cfgData->invertCLK; - commonAttr->mpegCfg.staticCLK = cfgData->staticCLK; - commonAttr->mpegCfg.bitrate = cfgData->bitrate; - - return (DRX_STS_OK); + | 0x03 << SIO_PDR_MCLK_CFG_MODE__B); + WR16(devAddr, SIO_PDR_MVAL_CFG__A, 0x0013); + sioPdrMdCfg = + MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH << + SIO_PDR_MD0_CFG_DRIVE__B | 0x03 << SIO_PDR_MD0_CFG_MODE__B; + WR16(devAddr, SIO_PDR_MD0_CFG__A, sioPdrMdCfg); + if (cfgData->enableParallel == TRUE) { /* MPEG data output is paralel -> set MD1 to MD7 to output mode */ + sioPdrMdCfg = + MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH << + SIO_PDR_MD0_CFG_DRIVE__B | 0x03 << + SIO_PDR_MD0_CFG_MODE__B; + WR16(devAddr, SIO_PDR_MD0_CFG__A, sioPdrMdCfg); + WR16(devAddr, SIO_PDR_MD1_CFG__A, sioPdrMdCfg); + WR16(devAddr, SIO_PDR_MD2_CFG__A, sioPdrMdCfg); + WR16(devAddr, SIO_PDR_MD3_CFG__A, sioPdrMdCfg); + WR16(devAddr, SIO_PDR_MD4_CFG__A, sioPdrMdCfg); + WR16(devAddr, SIO_PDR_MD5_CFG__A, sioPdrMdCfg); + WR16(devAddr, SIO_PDR_MD6_CFG__A, sioPdrMdCfg); + WR16(devAddr, SIO_PDR_MD7_CFG__A, sioPdrMdCfg); + } else { /* MPEG data output is serial -> set MD1 to MD7 to tri-state */ + WR16(devAddr, SIO_PDR_MD1_CFG__A, 0x0000); + WR16(devAddr, SIO_PDR_MD2_CFG__A, 0x0000); + WR16(devAddr, SIO_PDR_MD3_CFG__A, 0x0000); + WR16(devAddr, SIO_PDR_MD4_CFG__A, 0x0000); + WR16(devAddr, SIO_PDR_MD5_CFG__A, 0x0000); + WR16(devAddr, SIO_PDR_MD6_CFG__A, 0x0000); + WR16(devAddr, SIO_PDR_MD7_CFG__A, 0x0000); + } + /* Enable Monitor Bus output over MPEG pads and ctl input */ + WR16(devAddr, SIO_PDR_MON_CFG__A, 0x0000); + /* Write nomagic word to enable pdr reg write */ + WR16(devAddr, SIO_TOP_COMM_KEY__A, 0x0000); + } else { + /* Write magic word to enable pdr reg write */ + WR16(devAddr, SIO_TOP_COMM_KEY__A, 0xFABA); + /* Set MPEG TS pads to inputmode */ + WR16(devAddr, SIO_PDR_MSTRT_CFG__A, 0x0000); + WR16(devAddr, SIO_PDR_MERR_CFG__A, 0x0000); + WR16(devAddr, SIO_PDR_MCLK_CFG__A, 0x0000); + WR16(devAddr, SIO_PDR_MVAL_CFG__A, 0x0000); + WR16(devAddr, SIO_PDR_MD0_CFG__A, 0x0000); + WR16(devAddr, SIO_PDR_MD1_CFG__A, 0x0000); + WR16(devAddr, SIO_PDR_MD2_CFG__A, 0x0000); + WR16(devAddr, SIO_PDR_MD3_CFG__A, 0x0000); + WR16(devAddr, SIO_PDR_MD4_CFG__A, 0x0000); + WR16(devAddr, SIO_PDR_MD5_CFG__A, 0x0000); + WR16(devAddr, SIO_PDR_MD6_CFG__A, 0x0000); + WR16(devAddr, SIO_PDR_MD7_CFG__A, 0x0000); + /* Enable Monitor Bus output over MPEG pads and ctl input */ + WR16(devAddr, SIO_PDR_MON_CFG__A, 0x0000); + /* Write nomagic word to enable pdr reg write */ + WR16(devAddr, SIO_TOP_COMM_KEY__A, 0x0000); + } + + /* save values for restore after re-acquire */ + commonAttr->mpegCfg.enableMPEGOutput = cfgData->enableMPEGOutput; + commonAttr->mpegCfg.insertRSByte = cfgData->insertRSByte; + commonAttr->mpegCfg.enableParallel = cfgData->enableParallel; + commonAttr->mpegCfg.invertDATA = cfgData->invertDATA; + commonAttr->mpegCfg.invertERR = cfgData->invertERR; + commonAttr->mpegCfg.invertSTR = cfgData->invertSTR; + commonAttr->mpegCfg.invertVAL = cfgData->invertVAL; + commonAttr->mpegCfg.invertCLK = cfgData->invertCLK; + commonAttr->mpegCfg.staticCLK = cfgData->staticCLK; + commonAttr->mpegCfg.bitrate = cfgData->bitrate; + + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /*----------------------------------------------------------------------------*/ @@ -3221,46 +3038,44 @@ rw_error: * */ static DRXStatus_t -CtrlGetCfgMPEGOutput( pDRXDemodInstance_t demod, - pDRXCfgMPEGOutput_t cfgData ) +CtrlGetCfgMPEGOutput(pDRXDemodInstance_t demod, pDRXCfgMPEGOutput_t cfgData) { - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)(NULL); - pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t)(NULL); - DRXLockStatus_t lockStatus = DRX_NOT_LOCKED; - u32_t rateReg = 0; - u32_t data64Hi = 0; - u32_t data64Lo = 0; - - if( cfgData == NULL ) - { - return (DRX_STS_INVALID_ARG); - } - devAddr = demod->myI2CDevAddr; - commonAttr = demod->myCommonAttr; - - cfgData->enableMPEGOutput = commonAttr->mpegCfg.enableMPEGOutput; - cfgData->insertRSByte = commonAttr->mpegCfg.insertRSByte; - cfgData->enableParallel = commonAttr->mpegCfg.enableParallel; - cfgData->invertDATA = commonAttr->mpegCfg.invertDATA; - cfgData->invertERR = commonAttr->mpegCfg.invertERR; - cfgData->invertSTR = commonAttr->mpegCfg.invertSTR; - cfgData->invertVAL = commonAttr->mpegCfg.invertVAL; - cfgData->invertCLK = commonAttr->mpegCfg.invertCLK; - cfgData->staticCLK = commonAttr->mpegCfg.staticCLK; - cfgData->bitrate = 0; - - CHK_ERROR( CtrlLockStatus( demod, &lockStatus) ); - if ( (lockStatus == DRX_LOCKED) ) - { - RR32 (devAddr, FEC_OC_RCN_DYN_RATE_LO__A, &rateReg); - /* Frcn_rate = rateReg * Fsys / 2 ^ 25 */ - Mult32 ( rateReg, commonAttr->sysClockFreq * 1000, &data64Hi, &data64Lo ); - cfgData->bitrate = (data64Hi << 7) | (data64Lo >> 25); - } + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) (NULL); + pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); + DRXLockStatus_t lockStatus = DRX_NOT_LOCKED; + u32_t rateReg = 0; + u32_t data64Hi = 0; + u32_t data64Lo = 0; + + if (cfgData == NULL) { + return (DRX_STS_INVALID_ARG); + } + devAddr = demod->myI2CDevAddr; + commonAttr = demod->myCommonAttr; + + cfgData->enableMPEGOutput = commonAttr->mpegCfg.enableMPEGOutput; + cfgData->insertRSByte = commonAttr->mpegCfg.insertRSByte; + cfgData->enableParallel = commonAttr->mpegCfg.enableParallel; + cfgData->invertDATA = commonAttr->mpegCfg.invertDATA; + cfgData->invertERR = commonAttr->mpegCfg.invertERR; + cfgData->invertSTR = commonAttr->mpegCfg.invertSTR; + cfgData->invertVAL = commonAttr->mpegCfg.invertVAL; + cfgData->invertCLK = commonAttr->mpegCfg.invertCLK; + cfgData->staticCLK = commonAttr->mpegCfg.staticCLK; + cfgData->bitrate = 0; + + CHK_ERROR(CtrlLockStatus(demod, &lockStatus)); + if ((lockStatus == DRX_LOCKED)) { + RR32(devAddr, FEC_OC_RCN_DYN_RATE_LO__A, &rateReg); + /* Frcn_rate = rateReg * Fsys / 2 ^ 25 */ + Mult32(rateReg, commonAttr->sysClockFreq * 1000, &data64Hi, + &data64Lo); + cfgData->bitrate = (data64Hi << 7) | (data64Lo >> 25); + } - return (DRX_STS_OK); + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /*----------------------------------------------------------------------------*/ @@ -3280,44 +3095,42 @@ rw_error: * This routine should be called during a set channel of QAM/VSB * */ -static DRXStatus_t -SetMPEGTEIHandling( pDRXDemodInstance_t demod ) +static DRXStatus_t SetMPEGTEIHandling(pDRXDemodInstance_t demod) { - pDRXJData_t extAttr = (pDRXJData_t)(NULL); - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)(NULL); - u16_t fecOcDprMode = 0; - u16_t fecOcSncMode = 0; - u16_t fecOcEmsMode = 0; - - devAddr = demod -> myI2CDevAddr; - extAttr = (pDRXJData_t) demod -> myExtAttr; - - RR16( devAddr, FEC_OC_DPR_MODE__A, &fecOcDprMode ); - RR16( devAddr, FEC_OC_SNC_MODE__A, &fecOcSncMode ); - RR16( devAddr, FEC_OC_EMS_MODE__A, &fecOcEmsMode ); - - /* reset to default, allow TEI bit to be changed */ - fecOcDprMode &= (~FEC_OC_DPR_MODE_ERR_DISABLE__M); - fecOcSncMode &= (~(FEC_OC_SNC_MODE_ERROR_CTL__M | - FEC_OC_SNC_MODE_CORR_DISABLE__M)); - fecOcEmsMode &= (~FEC_OC_EMS_MODE_MODE__M); - - if ( extAttr->disableTEIhandling == TRUE ) - { - /* do not change TEI bit */ - fecOcDprMode |= FEC_OC_DPR_MODE_ERR_DISABLE__M; - fecOcSncMode |= FEC_OC_SNC_MODE_CORR_DISABLE__M | - ( (0x2)<<(FEC_OC_SNC_MODE_ERROR_CTL__B)); - fecOcEmsMode |= ((0x01)<<(FEC_OC_EMS_MODE_MODE__B)); - } - - WR16( devAddr, FEC_OC_DPR_MODE__A, fecOcDprMode ); - WR16( devAddr, FEC_OC_SNC_MODE__A, fecOcSncMode ); - WR16( devAddr, FEC_OC_EMS_MODE__A, fecOcEmsMode ); - - return (DRX_STS_OK); + pDRXJData_t extAttr = (pDRXJData_t) (NULL); + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) (NULL); + u16_t fecOcDprMode = 0; + u16_t fecOcSncMode = 0; + u16_t fecOcEmsMode = 0; + + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; + + RR16(devAddr, FEC_OC_DPR_MODE__A, &fecOcDprMode); + RR16(devAddr, FEC_OC_SNC_MODE__A, &fecOcSncMode); + RR16(devAddr, FEC_OC_EMS_MODE__A, &fecOcEmsMode); + + /* reset to default, allow TEI bit to be changed */ + fecOcDprMode &= (~FEC_OC_DPR_MODE_ERR_DISABLE__M); + fecOcSncMode &= (~(FEC_OC_SNC_MODE_ERROR_CTL__M | + FEC_OC_SNC_MODE_CORR_DISABLE__M)); + fecOcEmsMode &= (~FEC_OC_EMS_MODE_MODE__M); + + if (extAttr->disableTEIhandling == TRUE) { + /* do not change TEI bit */ + fecOcDprMode |= FEC_OC_DPR_MODE_ERR_DISABLE__M; + fecOcSncMode |= FEC_OC_SNC_MODE_CORR_DISABLE__M | + ((0x2) << (FEC_OC_SNC_MODE_ERROR_CTL__B)); + fecOcEmsMode |= ((0x01) << (FEC_OC_EMS_MODE_MODE__B)); + } + + WR16(devAddr, FEC_OC_DPR_MODE__A, fecOcDprMode); + WR16(devAddr, FEC_OC_SNC_MODE__A, fecOcSncMode); + WR16(devAddr, FEC_OC_EMS_MODE__A, fecOcEmsMode); + + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /*----------------------------------------------------------------------------*/ @@ -3330,32 +3143,30 @@ rw_error: * This routine should be called during a set channel of QAM/VSB * */ -static DRXStatus_t -BitReverseMPEGOutput ( pDRXDemodInstance_t demod ) +static DRXStatus_t BitReverseMPEGOutput(pDRXDemodInstance_t demod) { - pDRXJData_t extAttr = (pDRXJData_t)(NULL); - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)(NULL); - u16_t fecOcIprMode = 0; + pDRXJData_t extAttr = (pDRXJData_t) (NULL); + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) (NULL); + u16_t fecOcIprMode = 0; - devAddr = demod -> myI2CDevAddr; - extAttr = (pDRXJData_t) demod -> myExtAttr; + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; - RR16( devAddr, FEC_OC_IPR_MODE__A, &fecOcIprMode ); + RR16(devAddr, FEC_OC_IPR_MODE__A, &fecOcIprMode); - /* reset to default (normal bit order) */ - fecOcIprMode &= (~FEC_OC_IPR_MODE_REVERSE_ORDER__M); + /* reset to default (normal bit order) */ + fecOcIprMode &= (~FEC_OC_IPR_MODE_REVERSE_ORDER__M); - if ( extAttr->bitReverseMpegOutout == TRUE) - { - /* reverse bit order */ - fecOcIprMode |= FEC_OC_IPR_MODE_REVERSE_ORDER__M; - } + if (extAttr->bitReverseMpegOutout == TRUE) { + /* reverse bit order */ + fecOcIprMode |= FEC_OC_IPR_MODE_REVERSE_ORDER__M; + } - WR16( devAddr, FEC_OC_IPR_MODE__A, fecOcIprMode ); + WR16(devAddr, FEC_OC_IPR_MODE__A, fecOcIprMode); - return (DRX_STS_OK); + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /*----------------------------------------------------------------------------*/ @@ -3368,23 +3179,22 @@ rw_error: * This routine should be called during a set channel of QAM/VSB * */ -static DRXStatus_t -SetMPEGOutputClockRate ( pDRXDemodInstance_t demod ) +static DRXStatus_t SetMPEGOutputClockRate(pDRXDemodInstance_t demod) { - pDRXJData_t extAttr = (pDRXJData_t)(NULL); - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)(NULL); + pDRXJData_t extAttr = (pDRXJData_t) (NULL); + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) (NULL); - devAddr = demod -> myI2CDevAddr; - extAttr = (pDRXJData_t) demod -> myExtAttr; + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; - if ( extAttr->mpegOutputClockRate != DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO ) - { - WR16 ( devAddr, FEC_OC_DTO_PERIOD__A, extAttr->mpegOutputClockRate - 1 ); - } + if (extAttr->mpegOutputClockRate != DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO) { + WR16(devAddr, FEC_OC_DTO_PERIOD__A, + extAttr->mpegOutputClockRate - 1); + } - return (DRX_STS_OK); + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /*----------------------------------------------------------------------------*/ @@ -3397,32 +3207,30 @@ rw_error: * This routine should be called during a set channel of QAM/VSB * */ -static DRXStatus_t -SetMPEGStartWidth ( pDRXDemodInstance_t demod ) +static DRXStatus_t SetMPEGStartWidth(pDRXDemodInstance_t demod) { - pDRXJData_t extAttr = (pDRXJData_t)(NULL); - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)(NULL); - u16_t fecOcCommMb = 0; - pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) NULL; + pDRXJData_t extAttr = (pDRXJData_t) (NULL); + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) (NULL); + u16_t fecOcCommMb = 0; + pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) NULL; - devAddr = demod -> myI2CDevAddr; - extAttr = (pDRXJData_t) demod -> myExtAttr; - commonAttr = demod->myCommonAttr; + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; + commonAttr = demod->myCommonAttr; - if ((commonAttr->mpegCfg.staticCLK == TRUE) && (commonAttr->mpegCfg.enableParallel == FALSE)) - { - RR16 ( devAddr, FEC_OC_COMM_MB__A, &fecOcCommMb ); - fecOcCommMb &= ~FEC_OC_COMM_MB_CTL_ON; - if ( extAttr->mpegStartWidth == DRXJ_MPEG_START_WIDTH_8CLKCYC ) - { - fecOcCommMb |= FEC_OC_COMM_MB_CTL_ON; - } - WR16 ( devAddr, FEC_OC_COMM_MB__A, fecOcCommMb); - } - - return (DRX_STS_OK); + if ((commonAttr->mpegCfg.staticCLK == TRUE) + && (commonAttr->mpegCfg.enableParallel == FALSE)) { + RR16(devAddr, FEC_OC_COMM_MB__A, &fecOcCommMb); + fecOcCommMb &= ~FEC_OC_COMM_MB_CTL_ON; + if (extAttr->mpegStartWidth == DRXJ_MPEG_START_WIDTH_8CLKCYC) { + fecOcCommMb |= FEC_OC_COMM_MB_CTL_ON; + } + WR16(devAddr, FEC_OC_COMM_MB__A, fecOcCommMb); + } + + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /*----------------------------------------------------------------------------*/ @@ -3438,41 +3246,39 @@ rw_error: * */ static DRXStatus_t -CtrlSetCfgMpegOutputMisc( - pDRXDemodInstance_t demod, - pDRXJCfgMpegOutputMisc_t cfgData ) +CtrlSetCfgMpegOutputMisc(pDRXDemodInstance_t demod, + pDRXJCfgMpegOutputMisc_t cfgData) { - pDRXJData_t extAttr = (pDRXJData_t)(NULL); + pDRXJData_t extAttr = (pDRXJData_t) (NULL); - if(cfgData == NULL) - { - return (DRX_STS_INVALID_ARG); - } - - extAttr = (pDRXJData_t) demod -> myExtAttr; - - /* - Set disable TEI bit handling flag. - TEI must be left untouched by device in case of BER measurements using - external equipment that is unable to ignore the TEI bit in the TS. - Default will FALSE (enable TEI bit handling). - Reverse output bit order. Default is FALSE (msb on MD7 (parallel) or out first (serial)). - Set clock rate. Default is auto that is derived from symbol rate. - The flags and values will also be used to set registers during a set channel. - */ - extAttr->disableTEIhandling = cfgData->disableTEIHandling; - extAttr->bitReverseMpegOutout = cfgData->bitReverseMpegOutout; - extAttr->mpegOutputClockRate = cfgData->mpegOutputClockRate; - extAttr->mpegStartWidth = cfgData->mpegStartWidth; - /* Don't care what the active standard is, activate setting immediatly */ - CHK_ERROR ( SetMPEGTEIHandling( demod ) ); - CHK_ERROR ( BitReverseMPEGOutput( demod ) ); - CHK_ERROR ( SetMPEGOutputClockRate( demod ) ); - CHK_ERROR ( SetMPEGStartWidth ( demod ) ); - - return (DRX_STS_OK); + if (cfgData == NULL) { + return (DRX_STS_INVALID_ARG); + } + + extAttr = (pDRXJData_t) demod->myExtAttr; + + /* + Set disable TEI bit handling flag. + TEI must be left untouched by device in case of BER measurements using + external equipment that is unable to ignore the TEI bit in the TS. + Default will FALSE (enable TEI bit handling). + Reverse output bit order. Default is FALSE (msb on MD7 (parallel) or out first (serial)). + Set clock rate. Default is auto that is derived from symbol rate. + The flags and values will also be used to set registers during a set channel. + */ + extAttr->disableTEIhandling = cfgData->disableTEIHandling; + extAttr->bitReverseMpegOutout = cfgData->bitReverseMpegOutout; + extAttr->mpegOutputClockRate = cfgData->mpegOutputClockRate; + extAttr->mpegStartWidth = cfgData->mpegStartWidth; + /* Don't care what the active standard is, activate setting immediatly */ + CHK_ERROR(SetMPEGTEIHandling(demod)); + CHK_ERROR(BitReverseMPEGOutput(demod)); + CHK_ERROR(SetMPEGOutputClockRate(demod)); + CHK_ERROR(SetMPEGStartWidth(demod)); + + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /*----------------------------------------------------------------------------*/ @@ -3490,35 +3296,31 @@ rw_error: * */ static DRXStatus_t -CtrlGetCfgMpegOutputMisc( - pDRXDemodInstance_t demod, - pDRXJCfgMpegOutputMisc_t cfgData ) +CtrlGetCfgMpegOutputMisc(pDRXDemodInstance_t demod, + pDRXJCfgMpegOutputMisc_t cfgData) { - pDRXJData_t extAttr = (pDRXJData_t)(NULL); - u16_t data = 0; + pDRXJData_t extAttr = (pDRXJData_t) (NULL); + u16_t data = 0; - if(cfgData == NULL) - { - return (DRX_STS_INVALID_ARG); - } - - extAttr = (pDRXJData_t) demod -> myExtAttr; - cfgData->disableTEIHandling = extAttr->disableTEIhandling; - cfgData->bitReverseMpegOutout = extAttr->bitReverseMpegOutout; - cfgData->mpegStartWidth = extAttr->mpegStartWidth; - if (extAttr->mpegOutputClockRate != DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO) - { - cfgData->mpegOutputClockRate = extAttr->mpegOutputClockRate; - } - else - { - RR16 ( demod->myI2CDevAddr, FEC_OC_DTO_PERIOD__A, &data ); - cfgData->mpegOutputClockRate = (DRXJMpegOutputClockRate_t) (data + 1); - } + if (cfgData == NULL) { + return (DRX_STS_INVALID_ARG); + } - return (DRX_STS_OK); + extAttr = (pDRXJData_t) demod->myExtAttr; + cfgData->disableTEIHandling = extAttr->disableTEIhandling; + cfgData->bitReverseMpegOutout = extAttr->bitReverseMpegOutout; + cfgData->mpegStartWidth = extAttr->mpegStartWidth; + if (extAttr->mpegOutputClockRate != DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO) { + cfgData->mpegOutputClockRate = extAttr->mpegOutputClockRate; + } else { + RR16(demod->myI2CDevAddr, FEC_OC_DTO_PERIOD__A, &data); + cfgData->mpegOutputClockRate = + (DRXJMpegOutputClockRate_t) (data + 1); + } + + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /*----------------------------------------------------------------------------*/ @@ -3536,29 +3338,28 @@ rw_error: * */ static DRXStatus_t -CtrlGetCfgHwCfg( pDRXDemodInstance_t demod, - pDRXJCfgHwCfg_t cfgData ) +CtrlGetCfgHwCfg(pDRXDemodInstance_t demod, pDRXJCfgHwCfg_t cfgData) { - u16_t data = 0; - pDRXJData_t extAttr = (pDRXJData_t)(NULL); + u16_t data = 0; + pDRXJData_t extAttr = (pDRXJData_t) (NULL); - if(cfgData == NULL) - { - return (DRX_STS_INVALID_ARG); - } + if (cfgData == NULL) { + return (DRX_STS_INVALID_ARG); + } - extAttr = (pDRXJData_t) demod -> myExtAttr; - WR16 ( demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, 0xFABA); - RR16 ( demod->myI2CDevAddr, SIO_PDR_OHW_CFG__A, &data ); - WR16 ( demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, 0x0000); + extAttr = (pDRXJData_t) demod->myExtAttr; + WR16(demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, 0xFABA); + RR16(demod->myI2CDevAddr, SIO_PDR_OHW_CFG__A, &data); + WR16(demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, 0x0000); - cfgData->i2cSpeed = (DRXJI2CSpeed_t)((data >> 6) & 0x1); - cfgData->xtalFreq = (DRXJXtalFreq_t)(data & 0x3); + cfgData->i2cSpeed = (DRXJI2CSpeed_t) ((data >> 6) & 0x1); + cfgData->xtalFreq = (DRXJXtalFreq_t) (data & 0x3); - return (DRX_STS_OK); - rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); } + /*----------------------------------------------------------------------------*/ /* miscellaneous configuartions - end */ /*----------------------------------------------------------------------------*/ @@ -3573,115 +3374,109 @@ CtrlGetCfgHwCfg( pDRXDemodInstance_t demod, * \param UIOCfg Pointer to a configuration setting for a certain UIO. * \return DRXStatus_t. */ -static DRXStatus_t -CtrlSetUIOCfg( pDRXDemodInstance_t demod, pDRXUIOCfg_t UIOCfg ) +static DRXStatus_t CtrlSetUIOCfg(pDRXDemodInstance_t demod, pDRXUIOCfg_t UIOCfg) { - pDRXJData_t extAttr = (pDRXJData_t)(NULL); + pDRXJData_t extAttr = (pDRXJData_t) (NULL); - if (( UIOCfg == NULL ) || ( demod == NULL )) - { - return DRX_STS_INVALID_ARG; - } - extAttr = (pDRXJData_t)demod -> myExtAttr; + if ((UIOCfg == NULL) || (demod == NULL)) { + return DRX_STS_INVALID_ARG; + } + extAttr = (pDRXJData_t) demod->myExtAttr; - /* Write magic word to enable pdr reg write */ - WR16( demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY ); - switch ( UIOCfg->uio ) { + /* Write magic word to enable pdr reg write */ + WR16(demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); + switch (UIOCfg->uio) { /*====================================================================*/ - case DRX_UIO1 : - /* DRX_UIO1: SMA_TX UIO-1 */ - if (extAttr->hasSMATX != TRUE) - return DRX_STS_ERROR; - switch ( UIOCfg->mode ) - { - case DRX_UIO_MODE_FIRMWARE_SMA: /* falltrough */ - case DRX_UIO_MODE_FIRMWARE_SAW: /* falltrough */ - case DRX_UIO_MODE_READWRITE: - extAttr->uioSmaTxMode = UIOCfg->mode; - break; - case DRX_UIO_MODE_DISABLE: - extAttr->uioSmaTxMode = UIOCfg->mode; - /* pad configuration register is set 0 - input mode */ - WR16( demod->myI2CDevAddr, SIO_PDR_SMA_TX_CFG__A, 0 ); - break; - default: - return DRX_STS_INVALID_ARG; - } /* switch ( UIOCfg->mode ) */ - break; + case DRX_UIO1: + /* DRX_UIO1: SMA_TX UIO-1 */ + if (extAttr->hasSMATX != TRUE) + return DRX_STS_ERROR; + switch (UIOCfg->mode) { + case DRX_UIO_MODE_FIRMWARE_SMA: /* falltrough */ + case DRX_UIO_MODE_FIRMWARE_SAW: /* falltrough */ + case DRX_UIO_MODE_READWRITE: + extAttr->uioSmaTxMode = UIOCfg->mode; + break; + case DRX_UIO_MODE_DISABLE: + extAttr->uioSmaTxMode = UIOCfg->mode; + /* pad configuration register is set 0 - input mode */ + WR16(demod->myI2CDevAddr, SIO_PDR_SMA_TX_CFG__A, 0); + break; + default: + return DRX_STS_INVALID_ARG; + } /* switch ( UIOCfg->mode ) */ + break; /*====================================================================*/ - case DRX_UIO2 : - /* DRX_UIO2: SMA_RX UIO-2 */ - if (extAttr->hasSMARX != TRUE) - return DRX_STS_ERROR; - switch ( UIOCfg->mode ) - { - case DRX_UIO_MODE_FIRMWARE0: /* falltrough */ - case DRX_UIO_MODE_READWRITE: - extAttr->uioSmaRxMode = UIOCfg->mode; - break; - case DRX_UIO_MODE_DISABLE: - extAttr->uioSmaRxMode = UIOCfg->mode; - /* pad configuration register is set 0 - input mode */ - WR16( demod->myI2CDevAddr, SIO_PDR_SMA_RX_CFG__A, 0 ); - break; - default: - return DRX_STS_INVALID_ARG; - break; - } /* switch ( UIOCfg->mode ) */ - break; + case DRX_UIO2: + /* DRX_UIO2: SMA_RX UIO-2 */ + if (extAttr->hasSMARX != TRUE) + return DRX_STS_ERROR; + switch (UIOCfg->mode) { + case DRX_UIO_MODE_FIRMWARE0: /* falltrough */ + case DRX_UIO_MODE_READWRITE: + extAttr->uioSmaRxMode = UIOCfg->mode; + break; + case DRX_UIO_MODE_DISABLE: + extAttr->uioSmaRxMode = UIOCfg->mode; + /* pad configuration register is set 0 - input mode */ + WR16(demod->myI2CDevAddr, SIO_PDR_SMA_RX_CFG__A, 0); + break; + default: + return DRX_STS_INVALID_ARG; + break; + } /* switch ( UIOCfg->mode ) */ + break; /*====================================================================*/ - case DRX_UIO3 : - /* DRX_UIO3: GPIO UIO-3 */ - if (extAttr->hasGPIO != TRUE) - return DRX_STS_ERROR; - switch ( UIOCfg->mode ) - { - case DRX_UIO_MODE_FIRMWARE0: /* falltrough */ - case DRX_UIO_MODE_READWRITE: - extAttr->uioGPIOMode = UIOCfg->mode; - break; - case DRX_UIO_MODE_DISABLE: - extAttr->uioGPIOMode = UIOCfg->mode; - /* pad configuration register is set 0 - input mode */ - WR16( demod->myI2CDevAddr, SIO_PDR_GPIO_CFG__A, 0 ); - break; - default: - return DRX_STS_INVALID_ARG; - break; - } /* switch ( UIOCfg->mode ) */ - break; + case DRX_UIO3: + /* DRX_UIO3: GPIO UIO-3 */ + if (extAttr->hasGPIO != TRUE) + return DRX_STS_ERROR; + switch (UIOCfg->mode) { + case DRX_UIO_MODE_FIRMWARE0: /* falltrough */ + case DRX_UIO_MODE_READWRITE: + extAttr->uioGPIOMode = UIOCfg->mode; + break; + case DRX_UIO_MODE_DISABLE: + extAttr->uioGPIOMode = UIOCfg->mode; + /* pad configuration register is set 0 - input mode */ + WR16(demod->myI2CDevAddr, SIO_PDR_GPIO_CFG__A, 0); + break; + default: + return DRX_STS_INVALID_ARG; + break; + } /* switch ( UIOCfg->mode ) */ + break; /*====================================================================*/ - case DRX_UIO4 : - /* DRX_UIO4: IRQN UIO-4 */ - if (extAttr->hasIRQN != TRUE) - return DRX_STS_ERROR; - switch ( UIOCfg->mode ) - { - case DRX_UIO_MODE_READWRITE: - extAttr->uioIRQNMode = UIOCfg->mode; - break; - case DRX_UIO_MODE_DISABLE: - /* pad configuration register is set 0 - input mode */ - WR16( demod->myI2CDevAddr, SIO_PDR_IRQN_CFG__A, 0 ); - extAttr->uioIRQNMode = UIOCfg->mode; - break; - case DRX_UIO_MODE_FIRMWARE0: /* falltrough */ - default: - return DRX_STS_INVALID_ARG; - break; - } /* switch ( UIOCfg->mode ) */ - break; + case DRX_UIO4: + /* DRX_UIO4: IRQN UIO-4 */ + if (extAttr->hasIRQN != TRUE) + return DRX_STS_ERROR; + switch (UIOCfg->mode) { + case DRX_UIO_MODE_READWRITE: + extAttr->uioIRQNMode = UIOCfg->mode; + break; + case DRX_UIO_MODE_DISABLE: + /* pad configuration register is set 0 - input mode */ + WR16(demod->myI2CDevAddr, SIO_PDR_IRQN_CFG__A, 0); + extAttr->uioIRQNMode = UIOCfg->mode; + break; + case DRX_UIO_MODE_FIRMWARE0: /* falltrough */ + default: + return DRX_STS_INVALID_ARG; + break; + } /* switch ( UIOCfg->mode ) */ + break; /*====================================================================*/ - default: - return DRX_STS_INVALID_ARG; - } /* switch ( UIOCfg->uio ) */ + default: + return DRX_STS_INVALID_ARG; + } /* switch ( UIOCfg->uio ) */ - /* Write magic word to disable pdr reg write */ - WR16 ( demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, 0x0000); + /* Write magic word to disable pdr reg write */ + WR16(demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, 0x0000); - return (DRX_STS_OK); - rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); } /*============================================================================*/ @@ -3692,45 +3487,40 @@ CtrlSetUIOCfg( pDRXDemodInstance_t demod, pDRXUIOCfg_t UIOCfg ) * \param UIOCfg Pointer to a configuration setting for a certain UIO. * \return DRXStatus_t. */ -static DRXStatus_t -CtrlGetUIOCfg( pDRXDemodInstance_t demod, pDRXUIOCfg_t UIOCfg ) +static DRXStatus_t CtrlGetUIOCfg(pDRXDemodInstance_t demod, pDRXUIOCfg_t UIOCfg) { - pDRXJData_t extAttr = (pDRXJData_t) NULL; - pDRXUIOMode_t UIOMode[4] = {NULL}; - pBool_t UIOAvailable[4] = {NULL}; + pDRXJData_t extAttr = (pDRXJData_t) NULL; + pDRXUIOMode_t UIOMode[4] = { NULL }; + pBool_t UIOAvailable[4] = { NULL }; - extAttr = demod->myExtAttr; + extAttr = demod->myExtAttr; - UIOMode[DRX_UIO1] = &extAttr->uioSmaTxMode; - UIOMode[DRX_UIO2] = &extAttr->uioSmaRxMode; - UIOMode[DRX_UIO3] = &extAttr->uioGPIOMode; - UIOMode[DRX_UIO4] = &extAttr->uioIRQNMode; + UIOMode[DRX_UIO1] = &extAttr->uioSmaTxMode; + UIOMode[DRX_UIO2] = &extAttr->uioSmaRxMode; + UIOMode[DRX_UIO3] = &extAttr->uioGPIOMode; + UIOMode[DRX_UIO4] = &extAttr->uioIRQNMode; - UIOAvailable[DRX_UIO1] = &extAttr->hasSMATX; - UIOAvailable[DRX_UIO2] = &extAttr->hasSMARX; - UIOAvailable[DRX_UIO3] = &extAttr->hasGPIO; - UIOAvailable[DRX_UIO4] = &extAttr->hasIRQN; + UIOAvailable[DRX_UIO1] = &extAttr->hasSMATX; + UIOAvailable[DRX_UIO2] = &extAttr->hasSMARX; + UIOAvailable[DRX_UIO3] = &extAttr->hasGPIO; + UIOAvailable[DRX_UIO4] = &extAttr->hasIRQN; - if ( UIOCfg == NULL ) - { - return DRX_STS_INVALID_ARG; - } + if (UIOCfg == NULL) { + return DRX_STS_INVALID_ARG; + } - if ( ( UIOCfg->uio > DRX_UIO4 ) || - ( UIOCfg->uio < DRX_UIO1 ) ) - { - return DRX_STS_INVALID_ARG; - } + if ((UIOCfg->uio > DRX_UIO4) || (UIOCfg->uio < DRX_UIO1)) { + return DRX_STS_INVALID_ARG; + } - if( *UIOAvailable[UIOCfg->uio] == FALSE ) - { - return DRX_STS_ERROR; - } + if (*UIOAvailable[UIOCfg->uio] == FALSE) { + return DRX_STS_ERROR; + } - UIOCfg->mode = *UIOMode[ UIOCfg->uio ]; + UIOCfg->mode = *UIOMode[UIOCfg->uio]; - return DRX_STS_OK; + return DRX_STS_OK; } /** @@ -3741,155 +3531,144 @@ CtrlGetUIOCfg( pDRXDemodInstance_t demod, pDRXUIOCfg_t UIOCfg ) * \return DRXStatus_t. */ static DRXStatus_t -CtrlUIOWrite( pDRXDemodInstance_t demod, - pDRXUIOData_t UIOData) +CtrlUIOWrite(pDRXDemodInstance_t demod, pDRXUIOData_t UIOData) { - pDRXJData_t extAttr = (pDRXJData_t)(NULL); - u16_t pinCfgValue = 0; - u16_t value = 0; + pDRXJData_t extAttr = (pDRXJData_t) (NULL); + u16_t pinCfgValue = 0; + u16_t value = 0; - if (( UIOData == NULL ) || ( demod == NULL )) - { - return DRX_STS_INVALID_ARG; - } + if ((UIOData == NULL) || (demod == NULL)) { + return DRX_STS_INVALID_ARG; + } - extAttr = (pDRXJData_t)demod -> myExtAttr; + extAttr = (pDRXJData_t) demod->myExtAttr; - /* Write magic word to enable pdr reg write */ - WR16( demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY ); - switch ( UIOData->uio ) { + /* Write magic word to enable pdr reg write */ + WR16(demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); + switch (UIOData->uio) { /*====================================================================*/ - case DRX_UIO1: - /* DRX_UIO1: SMA_TX UIO-1 */ - if (extAttr->hasSMATX != TRUE) - return DRX_STS_ERROR; - if ( ( extAttr->uioSmaTxMode != DRX_UIO_MODE_READWRITE ) - && ( extAttr->uioSmaTxMode != DRX_UIO_MODE_FIRMWARE_SAW ) ) - { - return DRX_STS_ERROR; - } - pinCfgValue = 0; - /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ - pinCfgValue |= 0x0113; - /* io_pad_cfg_mode output mode is drive always */ - /* io_pad_cfg_drive is set to power 2 (23 mA) */ - - /* write to io pad configuration register - output mode */ - WR16( demod->myI2CDevAddr, SIO_PDR_SMA_TX_CFG__A, pinCfgValue ); - - /* use corresponding bit in io data output registar */ - RR16( demod->myI2CDevAddr, SIO_PDR_UIO_OUT_LO__A, &value ); - if (UIOData->value == FALSE) - { - value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */ - } else { - value |= 0x8000; /* write one to 15th bit - 1st UIO */ - } - /* write back to io data output register */ - WR16( demod->myI2CDevAddr, SIO_PDR_UIO_OUT_LO__A, value ); - break; + case DRX_UIO1: + /* DRX_UIO1: SMA_TX UIO-1 */ + if (extAttr->hasSMATX != TRUE) + return DRX_STS_ERROR; + if ((extAttr->uioSmaTxMode != DRX_UIO_MODE_READWRITE) + && (extAttr->uioSmaTxMode != DRX_UIO_MODE_FIRMWARE_SAW)) { + return DRX_STS_ERROR; + } + pinCfgValue = 0; + /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ + pinCfgValue |= 0x0113; + /* io_pad_cfg_mode output mode is drive always */ + /* io_pad_cfg_drive is set to power 2 (23 mA) */ + + /* write to io pad configuration register - output mode */ + WR16(demod->myI2CDevAddr, SIO_PDR_SMA_TX_CFG__A, pinCfgValue); + + /* use corresponding bit in io data output registar */ + RR16(demod->myI2CDevAddr, SIO_PDR_UIO_OUT_LO__A, &value); + if (UIOData->value == FALSE) { + value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */ + } else { + value |= 0x8000; /* write one to 15th bit - 1st UIO */ + } + /* write back to io data output register */ + WR16(demod->myI2CDevAddr, SIO_PDR_UIO_OUT_LO__A, value); + break; /*======================================================================*/ - case DRX_UIO2: - /* DRX_UIO2: SMA_RX UIO-2 */ - if (extAttr->hasSMARX != TRUE) - return DRX_STS_ERROR; - if ( extAttr->uioSmaRxMode != DRX_UIO_MODE_READWRITE ) - { - return DRX_STS_ERROR; - } - pinCfgValue = 0; - /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ - pinCfgValue |= 0x0113; - /* io_pad_cfg_mode output mode is drive always */ - /* io_pad_cfg_drive is set to power 2 (23 mA) */ - - /* write to io pad configuration register - output mode */ - WR16( demod->myI2CDevAddr, SIO_PDR_SMA_RX_CFG__A, pinCfgValue ); - - /* use corresponding bit in io data output registar */ - RR16( demod->myI2CDevAddr, SIO_PDR_UIO_OUT_LO__A, &value ); - if (UIOData->value == FALSE) - { - value &= 0xBFFF; /* write zero to 14th bit - 2nd UIO */ - } else { - value |= 0x4000; /* write one to 14th bit - 2nd UIO */ - } - /* write back to io data output register */ - WR16( demod->myI2CDevAddr, SIO_PDR_UIO_OUT_LO__A, value ); - break; + case DRX_UIO2: + /* DRX_UIO2: SMA_RX UIO-2 */ + if (extAttr->hasSMARX != TRUE) + return DRX_STS_ERROR; + if (extAttr->uioSmaRxMode != DRX_UIO_MODE_READWRITE) { + return DRX_STS_ERROR; + } + pinCfgValue = 0; + /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ + pinCfgValue |= 0x0113; + /* io_pad_cfg_mode output mode is drive always */ + /* io_pad_cfg_drive is set to power 2 (23 mA) */ + + /* write to io pad configuration register - output mode */ + WR16(demod->myI2CDevAddr, SIO_PDR_SMA_RX_CFG__A, pinCfgValue); + + /* use corresponding bit in io data output registar */ + RR16(demod->myI2CDevAddr, SIO_PDR_UIO_OUT_LO__A, &value); + if (UIOData->value == FALSE) { + value &= 0xBFFF; /* write zero to 14th bit - 2nd UIO */ + } else { + value |= 0x4000; /* write one to 14th bit - 2nd UIO */ + } + /* write back to io data output register */ + WR16(demod->myI2CDevAddr, SIO_PDR_UIO_OUT_LO__A, value); + break; /*====================================================================*/ - case DRX_UIO3: - /* DRX_UIO3: ASEL UIO-3 */ - if (extAttr->hasGPIO != TRUE) - return DRX_STS_ERROR; - if ( extAttr->uioGPIOMode != DRX_UIO_MODE_READWRITE ) - { - return DRX_STS_ERROR; - } - pinCfgValue = 0; - /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ - pinCfgValue |= 0x0113; - /* io_pad_cfg_mode output mode is drive always */ - /* io_pad_cfg_drive is set to power 2 (23 mA) */ - - /* write to io pad configuration register - output mode */ - WR16( demod->myI2CDevAddr, SIO_PDR_GPIO_CFG__A, pinCfgValue ); - - /* use corresponding bit in io data output registar */ - RR16( demod->myI2CDevAddr, SIO_PDR_UIO_OUT_HI__A, &value ); - if (UIOData->value == FALSE) - { - value &= 0xFFFB; /* write zero to 2nd bit - 3rd UIO */ - } else { - value |= 0x0004; /* write one to 2nd bit - 3rd UIO */ - } - /* write back to io data output register */ - WR16( demod->myI2CDevAddr, SIO_PDR_UIO_OUT_HI__A, value ); - break; + case DRX_UIO3: + /* DRX_UIO3: ASEL UIO-3 */ + if (extAttr->hasGPIO != TRUE) + return DRX_STS_ERROR; + if (extAttr->uioGPIOMode != DRX_UIO_MODE_READWRITE) { + return DRX_STS_ERROR; + } + pinCfgValue = 0; + /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ + pinCfgValue |= 0x0113; + /* io_pad_cfg_mode output mode is drive always */ + /* io_pad_cfg_drive is set to power 2 (23 mA) */ + + /* write to io pad configuration register - output mode */ + WR16(demod->myI2CDevAddr, SIO_PDR_GPIO_CFG__A, pinCfgValue); + + /* use corresponding bit in io data output registar */ + RR16(demod->myI2CDevAddr, SIO_PDR_UIO_OUT_HI__A, &value); + if (UIOData->value == FALSE) { + value &= 0xFFFB; /* write zero to 2nd bit - 3rd UIO */ + } else { + value |= 0x0004; /* write one to 2nd bit - 3rd UIO */ + } + /* write back to io data output register */ + WR16(demod->myI2CDevAddr, SIO_PDR_UIO_OUT_HI__A, value); + break; /*=====================================================================*/ - case DRX_UIO4: - /* DRX_UIO4: IRQN UIO-4 */ - if (extAttr->hasIRQN != TRUE) - return DRX_STS_ERROR; - - if ( extAttr->uioIRQNMode != DRX_UIO_MODE_READWRITE ) - { - return DRX_STS_ERROR; - } - pinCfgValue = 0; - /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ - pinCfgValue |= 0x0113; - /* io_pad_cfg_mode output mode is drive always */ - /* io_pad_cfg_drive is set to power 2 (23 mA) */ - - /* write to io pad configuration register - output mode */ - WR16( demod->myI2CDevAddr, SIO_PDR_IRQN_CFG__A, pinCfgValue ); - - /* use corresponding bit in io data output registar */ - RR16( demod->myI2CDevAddr, SIO_PDR_UIO_OUT_LO__A, &value ); - if (UIOData->value == FALSE) - { - value &= 0xEFFF; /* write zero to 12th bit - 4th UIO */ - } else { - value |= 0x1000; /* write one to 12th bit - 4th UIO */ - } - /* write back to io data output register */ - WR16( demod->myI2CDevAddr, SIO_PDR_UIO_OUT_LO__A, value ); - break; + case DRX_UIO4: + /* DRX_UIO4: IRQN UIO-4 */ + if (extAttr->hasIRQN != TRUE) + return DRX_STS_ERROR; + + if (extAttr->uioIRQNMode != DRX_UIO_MODE_READWRITE) { + return DRX_STS_ERROR; + } + pinCfgValue = 0; + /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ + pinCfgValue |= 0x0113; + /* io_pad_cfg_mode output mode is drive always */ + /* io_pad_cfg_drive is set to power 2 (23 mA) */ + + /* write to io pad configuration register - output mode */ + WR16(demod->myI2CDevAddr, SIO_PDR_IRQN_CFG__A, pinCfgValue); + + /* use corresponding bit in io data output registar */ + RR16(demod->myI2CDevAddr, SIO_PDR_UIO_OUT_LO__A, &value); + if (UIOData->value == FALSE) { + value &= 0xEFFF; /* write zero to 12th bit - 4th UIO */ + } else { + value |= 0x1000; /* write one to 12th bit - 4th UIO */ + } + /* write back to io data output register */ + WR16(demod->myI2CDevAddr, SIO_PDR_UIO_OUT_LO__A, value); + break; /*=====================================================================*/ - default: - return DRX_STS_INVALID_ARG; - } /* switch ( UIOData->uio ) */ + default: + return DRX_STS_INVALID_ARG; + } /* switch ( UIOData->uio ) */ - /* Write magic word to disable pdr reg write */ - WR16 ( demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, 0x0000); + /* Write magic word to disable pdr reg write */ + WR16(demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, 0x0000); - return (DRX_STS_OK); - rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); } - /** *\fn DRXStatus_t CtrlUIORead *\brief Read from a UIO. @@ -3897,147 +3676,137 @@ CtrlUIOWrite( pDRXDemodInstance_t demod, * \param UIOData Pointer to data container for a certain UIO. * \return DRXStatus_t. */ -static DRXStatus_t -CtrlUIORead( pDRXDemodInstance_t demod, - pDRXUIOData_t UIOData) +static DRXStatus_t CtrlUIORead(pDRXDemodInstance_t demod, pDRXUIOData_t UIOData) { - pDRXJData_t extAttr = (pDRXJData_t)(NULL); - u16_t pinCfgValue = 0; - u16_t value = 0; + pDRXJData_t extAttr = (pDRXJData_t) (NULL); + u16_t pinCfgValue = 0; + u16_t value = 0; - if (( UIOData == NULL ) || ( demod == NULL )) - { - return DRX_STS_INVALID_ARG; - } + if ((UIOData == NULL) || (demod == NULL)) { + return DRX_STS_INVALID_ARG; + } - extAttr = (pDRXJData_t)demod -> myExtAttr; + extAttr = (pDRXJData_t) demod->myExtAttr; - /* Write magic word to enable pdr reg write */ - WR16( demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY ); - switch ( UIOData->uio ) { + /* Write magic word to enable pdr reg write */ + WR16(demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); + switch (UIOData->uio) { /*====================================================================*/ - case DRX_UIO1: - /* DRX_UIO1: SMA_TX UIO-1 */ - if (extAttr->hasSMATX != TRUE) - return DRX_STS_ERROR; - - if ( extAttr->uioSmaTxMode != DRX_UIO_MODE_READWRITE ) - { - return DRX_STS_ERROR; - } - pinCfgValue = 0; - /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ - pinCfgValue |= 0x0110; - /* io_pad_cfg_mode output mode is drive always */ - /* io_pad_cfg_drive is set to power 2 (23 mA) */ - - /* write to io pad configuration register - input mode */ - WR16( demod->myI2CDevAddr, SIO_PDR_SMA_TX_CFG__A, pinCfgValue ); - - RR16( demod->myI2CDevAddr, SIO_PDR_UIO_IN_LO__A, &value ); - if ( (value & 0x8000) != 0 ) /* check 15th bit - 1st UIO */ - { - UIOData->value = TRUE; - } else { - UIOData->value = FALSE; - } - break; + case DRX_UIO1: + /* DRX_UIO1: SMA_TX UIO-1 */ + if (extAttr->hasSMATX != TRUE) + return DRX_STS_ERROR; + + if (extAttr->uioSmaTxMode != DRX_UIO_MODE_READWRITE) { + return DRX_STS_ERROR; + } + pinCfgValue = 0; + /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ + pinCfgValue |= 0x0110; + /* io_pad_cfg_mode output mode is drive always */ + /* io_pad_cfg_drive is set to power 2 (23 mA) */ + + /* write to io pad configuration register - input mode */ + WR16(demod->myI2CDevAddr, SIO_PDR_SMA_TX_CFG__A, pinCfgValue); + + RR16(demod->myI2CDevAddr, SIO_PDR_UIO_IN_LO__A, &value); + if ((value & 0x8000) != 0) { /* check 15th bit - 1st UIO */ + UIOData->value = TRUE; + } else { + UIOData->value = FALSE; + } + break; /*======================================================================*/ - case DRX_UIO2: - /* DRX_UIO2: SMA_RX UIO-2 */ - if (extAttr->hasSMARX != TRUE) - return DRX_STS_ERROR; - - if ( extAttr->uioSmaRxMode != DRX_UIO_MODE_READWRITE ) - { - return DRX_STS_ERROR; - } - pinCfgValue = 0; - /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ - pinCfgValue |= 0x0110; - /* io_pad_cfg_mode output mode is drive always */ - /* io_pad_cfg_drive is set to power 2 (23 mA) */ - - /* write to io pad configuration register - input mode */ - WR16( demod->myI2CDevAddr, SIO_PDR_SMA_RX_CFG__A, pinCfgValue ); - - RR16( demod->myI2CDevAddr, SIO_PDR_UIO_IN_LO__A, &value ); - - if ( (value & 0x4000) != 0 ) /* check 14th bit - 2nd UIO */ - { - UIOData->value = TRUE; - } else { - UIOData->value = FALSE; - } - break; + case DRX_UIO2: + /* DRX_UIO2: SMA_RX UIO-2 */ + if (extAttr->hasSMARX != TRUE) + return DRX_STS_ERROR; + + if (extAttr->uioSmaRxMode != DRX_UIO_MODE_READWRITE) { + return DRX_STS_ERROR; + } + pinCfgValue = 0; + /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ + pinCfgValue |= 0x0110; + /* io_pad_cfg_mode output mode is drive always */ + /* io_pad_cfg_drive is set to power 2 (23 mA) */ + + /* write to io pad configuration register - input mode */ + WR16(demod->myI2CDevAddr, SIO_PDR_SMA_RX_CFG__A, pinCfgValue); + + RR16(demod->myI2CDevAddr, SIO_PDR_UIO_IN_LO__A, &value); + + if ((value & 0x4000) != 0) { /* check 14th bit - 2nd UIO */ + UIOData->value = TRUE; + } else { + UIOData->value = FALSE; + } + break; /*=====================================================================*/ - case DRX_UIO3: - /* DRX_UIO3: GPIO UIO-3 */ - if (extAttr->hasGPIO != TRUE) - return DRX_STS_ERROR; - - if ( extAttr->uioGPIOMode != DRX_UIO_MODE_READWRITE ) - { - return DRX_STS_ERROR; - } - pinCfgValue = 0; - /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ - pinCfgValue |= 0x0110; - /* io_pad_cfg_mode output mode is drive always */ - /* io_pad_cfg_drive is set to power 2 (23 mA) */ - - /* write to io pad configuration register - input mode */ - WR16( demod->myI2CDevAddr, SIO_PDR_GPIO_CFG__A, pinCfgValue ); - - /* read io input data registar */ - RR16( demod->myI2CDevAddr, SIO_PDR_UIO_IN_HI__A, &value ); - if ( (value & 0x0004) != 0 ) /* check 2nd bit - 3rd UIO */ - { - UIOData->value = TRUE; - } else { - UIOData->value = FALSE; - } - break; + case DRX_UIO3: + /* DRX_UIO3: GPIO UIO-3 */ + if (extAttr->hasGPIO != TRUE) + return DRX_STS_ERROR; + + if (extAttr->uioGPIOMode != DRX_UIO_MODE_READWRITE) { + return DRX_STS_ERROR; + } + pinCfgValue = 0; + /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ + pinCfgValue |= 0x0110; + /* io_pad_cfg_mode output mode is drive always */ + /* io_pad_cfg_drive is set to power 2 (23 mA) */ + + /* write to io pad configuration register - input mode */ + WR16(demod->myI2CDevAddr, SIO_PDR_GPIO_CFG__A, pinCfgValue); + + /* read io input data registar */ + RR16(demod->myI2CDevAddr, SIO_PDR_UIO_IN_HI__A, &value); + if ((value & 0x0004) != 0) { /* check 2nd bit - 3rd UIO */ + UIOData->value = TRUE; + } else { + UIOData->value = FALSE; + } + break; /*=====================================================================*/ - case DRX_UIO4: - /* DRX_UIO4: IRQN UIO-4 */ - if (extAttr->hasIRQN != TRUE) - return DRX_STS_ERROR; - - if ( extAttr->uioIRQNMode != DRX_UIO_MODE_READWRITE ) - { - return DRX_STS_ERROR; - } - pinCfgValue = 0; - /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ - pinCfgValue |= 0x0110; - /* io_pad_cfg_mode output mode is drive always */ - /* io_pad_cfg_drive is set to power 2 (23 mA) */ - - /* write to io pad configuration register - input mode */ - WR16( demod->myI2CDevAddr, SIO_PDR_IRQN_CFG__A, pinCfgValue ); - - /* read io input data registar */ - RR16( demod->myI2CDevAddr, SIO_PDR_UIO_IN_LO__A, &value ); - if ( (value & 0x1000) != 0 ) /* check 12th bit - 4th UIO */ - { - UIOData->value = TRUE; - } else { - UIOData->value = FALSE; - } - break; + case DRX_UIO4: + /* DRX_UIO4: IRQN UIO-4 */ + if (extAttr->hasIRQN != TRUE) + return DRX_STS_ERROR; + + if (extAttr->uioIRQNMode != DRX_UIO_MODE_READWRITE) { + return DRX_STS_ERROR; + } + pinCfgValue = 0; + /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ + pinCfgValue |= 0x0110; + /* io_pad_cfg_mode output mode is drive always */ + /* io_pad_cfg_drive is set to power 2 (23 mA) */ + + /* write to io pad configuration register - input mode */ + WR16(demod->myI2CDevAddr, SIO_PDR_IRQN_CFG__A, pinCfgValue); + + /* read io input data registar */ + RR16(demod->myI2CDevAddr, SIO_PDR_UIO_IN_LO__A, &value); + if ((value & 0x1000) != 0) { /* check 12th bit - 4th UIO */ + UIOData->value = TRUE; + } else { + UIOData->value = FALSE; + } + break; /*====================================================================*/ - default: - return DRX_STS_INVALID_ARG; - } /* switch ( UIOData->uio ) */ + default: + return DRX_STS_INVALID_ARG; + } /* switch ( UIOData->uio ) */ - /* Write magic word to disable pdr reg write */ - WR16 ( demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, 0x0000); + /* Write magic word to disable pdr reg write */ + WR16(demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, 0x0000); - return (DRX_STS_OK); - rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); } + /*---------------------------------------------------------------------------*/ /* UIO Configuration Functions - end */ /*---------------------------------------------------------------------------*/ @@ -4054,31 +3823,27 @@ CtrlUIORead( pDRXDemodInstance_t demod, */ static DRXStatus_t -CtrlI2CBridge( pDRXDemodInstance_t demod, - pBool_t bridgeClosed ) +CtrlI2CBridge(pDRXDemodInstance_t demod, pBool_t bridgeClosed) { - DRXJHiCmd_t hiCmd; - u16_t result = 0; + DRXJHiCmd_t hiCmd; + u16_t result = 0; - /* check arguments */ - if (bridgeClosed == NULL ) - { - return (DRX_STS_INVALID_ARG); - } + /* check arguments */ + if (bridgeClosed == NULL) { + return (DRX_STS_INVALID_ARG); + } - hiCmd.cmd = SIO_HI_RA_RAM_CMD_BRDCTRL; - hiCmd.param1 = SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY; - if (*bridgeClosed == TRUE) - { - hiCmd.param2 = SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED; - } - else - { - hiCmd.param2 = SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN; - } + hiCmd.cmd = SIO_HI_RA_RAM_CMD_BRDCTRL; + hiCmd.param1 = SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY; + if (*bridgeClosed == TRUE) { + hiCmd.param2 = SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED; + } else { + hiCmd.param2 = SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN; + } - return HICommand( demod -> myI2CDevAddr, &hiCmd, &result); + return HICommand(demod->myI2CDevAddr, &hiCmd, &result); } + /*----------------------------------------------------------------------------*/ /* I2C Bridge Functions - end */ /*----------------------------------------------------------------------------*/ @@ -4093,41 +3858,40 @@ CtrlI2CBridge( pDRXDemodInstance_t demod, * \return DRXStatus_t. * */ -static DRXStatus_t -SmartAntInit(pDRXDemodInstance_t demod) +static DRXStatus_t SmartAntInit(pDRXDemodInstance_t demod) { - u16_t data = 0; - pDRXJData_t extAttr = NULL; - pI2CDeviceAddr_t devAddr = NULL; - DRXUIOCfg_t UIOCfg = {DRX_UIO1, DRX_UIO_MODE_FIRMWARE_SMA}; - - devAddr = demod -> myI2CDevAddr; - extAttr = (pDRXJData_t) demod -> myExtAttr; - - /* Write magic word to enable pdr reg write */ - WR16( demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY ); - /* init smart antenna */ - RR16( devAddr, SIO_SA_TX_COMMAND__A, &data ); - if (extAttr->smartAntInverted) - WR16( devAddr, SIO_SA_TX_COMMAND__A, - (data | SIO_SA_TX_COMMAND_TX_INVERT__M ) - | SIO_SA_TX_COMMAND_TX_ENABLE__M ); - else - WR16( devAddr, SIO_SA_TX_COMMAND__A, - (data & (~SIO_SA_TX_COMMAND_TX_INVERT__M)) - | SIO_SA_TX_COMMAND_TX_ENABLE__M ); - - /* config SMA_TX pin to smart antenna mode*/ - CHK_ERROR( CtrlSetUIOCfg( demod, &UIOCfg ) ); - WR16( demod->myI2CDevAddr, SIO_PDR_SMA_TX_CFG__A, 0x13 ); - WR16( demod->myI2CDevAddr, SIO_PDR_SMA_TX_GPIO_FNC__A, 0x03 ); - - /* Write magic word to disable pdr reg write */ - WR16( demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, 0x0000 ); - - return ( DRX_STS_OK ); + u16_t data = 0; + pDRXJData_t extAttr = NULL; + pI2CDeviceAddr_t devAddr = NULL; + DRXUIOCfg_t UIOCfg = { DRX_UIO1, DRX_UIO_MODE_FIRMWARE_SMA }; + + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; + + /* Write magic word to enable pdr reg write */ + WR16(demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); + /* init smart antenna */ + RR16(devAddr, SIO_SA_TX_COMMAND__A, &data); + if (extAttr->smartAntInverted) + WR16(devAddr, SIO_SA_TX_COMMAND__A, + (data | SIO_SA_TX_COMMAND_TX_INVERT__M) + | SIO_SA_TX_COMMAND_TX_ENABLE__M); + else + WR16(devAddr, SIO_SA_TX_COMMAND__A, + (data & (~SIO_SA_TX_COMMAND_TX_INVERT__M)) + | SIO_SA_TX_COMMAND_TX_ENABLE__M); + + /* config SMA_TX pin to smart antenna mode */ + CHK_ERROR(CtrlSetUIOCfg(demod, &UIOCfg)); + WR16(demod->myI2CDevAddr, SIO_PDR_SMA_TX_CFG__A, 0x13); + WR16(demod->myI2CDevAddr, SIO_PDR_SMA_TX_GPIO_FNC__A, 0x03); + + /* Write magic word to disable pdr reg write */ + WR16(demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, 0x0000); + + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /** @@ -4138,196 +3902,185 @@ rw_error: * */ static DRXStatus_t -CtrlSetCfgSmartAnt ( pDRXDemodInstance_t demod, pDRXJCfgSmartAnt_t smartAnt ) +CtrlSetCfgSmartAnt(pDRXDemodInstance_t demod, pDRXJCfgSmartAnt_t smartAnt) { - pDRXJData_t extAttr = NULL; - pI2CDeviceAddr_t devAddr = NULL; - u16_t data = 0; - u32_t startTime = 0; - static Bool_t bitInverted = FALSE; + pDRXJData_t extAttr = NULL; + pI2CDeviceAddr_t devAddr = NULL; + u16_t data = 0; + u32_t startTime = 0; + static Bool_t bitInverted = FALSE; - devAddr = demod -> myI2CDevAddr; - extAttr = (pDRXJData_t)demod->myExtAttr; + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; - /* check arguments */ - if ( smartAnt == NULL ) - { - return (DRX_STS_INVALID_ARG); - } + /* check arguments */ + if (smartAnt == NULL) { + return (DRX_STS_INVALID_ARG); + } - if ( bitInverted != extAttr->smartAntInverted - || extAttr->uioSmaTxMode != DRX_UIO_MODE_FIRMWARE_SMA) - { - CHK_ERROR(SmartAntInit(demod)); - bitInverted = extAttr->smartAntInverted; - } + if (bitInverted != extAttr->smartAntInverted + || extAttr->uioSmaTxMode != DRX_UIO_MODE_FIRMWARE_SMA) { + CHK_ERROR(SmartAntInit(demod)); + bitInverted = extAttr->smartAntInverted; + } - /* Write magic word to enable pdr reg write */ - WR16( demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY ); + /* Write magic word to enable pdr reg write */ + WR16(demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); + + switch (smartAnt->io) { + case DRXJ_SMT_ANT_OUTPUT: + /* enable Tx if Mode B (input) is supported */ + /* + RR16( devAddr, SIO_SA_TX_COMMAND__A, &data ); + WR16( devAddr, SIO_SA_TX_COMMAND__A, data | SIO_SA_TX_COMMAND_TX_ENABLE__M ); + */ + startTime = DRXBSP_HST_Clock(); + do { + RR16(devAddr, SIO_SA_TX_STATUS__A, &data); + } while ((data & SIO_SA_TX_STATUS_BUSY__M) + && ((DRXBSP_HST_Clock() - startTime) < + DRXJ_MAX_WAITTIME)); + + if (data & SIO_SA_TX_STATUS_BUSY__M) { + return (DRX_STS_ERROR); + } + + /* write to smart antenna configuration register */ + WR16(devAddr, SIO_SA_TX_DATA0__A, 0x9200 + | ((smartAnt->ctrlData & 0x0001) << 8) + | ((smartAnt->ctrlData & 0x0002) << 10) + | ((smartAnt->ctrlData & 0x0004) << 12) + ); + WR16(devAddr, SIO_SA_TX_DATA1__A, 0x4924 + | ((smartAnt->ctrlData & 0x0008) >> 2) + | ((smartAnt->ctrlData & 0x0010)) + | ((smartAnt->ctrlData & 0x0020) << 2) + | ((smartAnt->ctrlData & 0x0040) << 4) + | ((smartAnt->ctrlData & 0x0080) << 6) + ); + WR16(devAddr, SIO_SA_TX_DATA2__A, 0x2492 + | ((smartAnt->ctrlData & 0x0100) >> 8) + | ((smartAnt->ctrlData & 0x0200) >> 6) + | ((smartAnt->ctrlData & 0x0400) >> 4) + | ((smartAnt->ctrlData & 0x0800) >> 2) + | ((smartAnt->ctrlData & 0x1000)) + | ((smartAnt->ctrlData & 0x2000) << 2) + ); + WR16(devAddr, SIO_SA_TX_DATA3__A, 0xff8d); + + /* trigger the sending */ + WR16(devAddr, SIO_SA_TX_LENGTH__A, 56); + + break; + case DRXJ_SMT_ANT_INPUT: + /* disable Tx if Mode B (input) is supported */ + /* + RR16( devAddr, SIO_SA_TX_COMMAND__A, &data ); + WR16( devAddr, SIO_SA_TX_COMMAND__A, data & (~SIO_SA_TX_COMMAND_TX_ENABLE__M) ); + */ + default: + return (DRX_STS_INVALID_ARG); + } + /* Write magic word to enable pdr reg write */ + WR16(demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, 0x0000); - switch (smartAnt->io) - { - case DRXJ_SMT_ANT_OUTPUT: - /* enable Tx if Mode B (input) is supported */ - /* - RR16( devAddr, SIO_SA_TX_COMMAND__A, &data ); - WR16( devAddr, SIO_SA_TX_COMMAND__A, data | SIO_SA_TX_COMMAND_TX_ENABLE__M ); - */ - startTime = DRXBSP_HST_Clock(); - do{ - RR16( devAddr, SIO_SA_TX_STATUS__A, &data ); - } while ( (data & SIO_SA_TX_STATUS_BUSY__M) && ( (DRXBSP_HST_Clock() - startTime) < DRXJ_MAX_WAITTIME ) ); - - if ( data & SIO_SA_TX_STATUS_BUSY__M ) - { - return (DRX_STS_ERROR); - } - - /* write to smart antenna configuration register */ - WR16( devAddr, SIO_SA_TX_DATA0__A, 0x9200 - | ((smartAnt->ctrlData & 0x0001) << 8) - | ((smartAnt->ctrlData & 0x0002) << 10) - | ((smartAnt->ctrlData & 0x0004) << 12) - ); - WR16( devAddr, SIO_SA_TX_DATA1__A, 0x4924 - | ((smartAnt->ctrlData & 0x0008) >> 2) - | ((smartAnt->ctrlData & 0x0010) ) - | ((smartAnt->ctrlData & 0x0020) << 2) - | ((smartAnt->ctrlData & 0x0040) << 4) - | ((smartAnt->ctrlData & 0x0080) << 6) - ); - WR16( devAddr, SIO_SA_TX_DATA2__A, 0x2492 - | ((smartAnt->ctrlData & 0x0100) >> 8) - | ((smartAnt->ctrlData & 0x0200) >> 6) - | ((smartAnt->ctrlData & 0x0400) >> 4) - | ((smartAnt->ctrlData & 0x0800) >> 2) - | ((smartAnt->ctrlData & 0x1000) ) - | ((smartAnt->ctrlData & 0x2000) << 2) - ); - WR16( devAddr, SIO_SA_TX_DATA3__A, 0xff8d ); - - /* trigger the sending */ - WR16( devAddr, SIO_SA_TX_LENGTH__A, 56 ); - - break; - case DRXJ_SMT_ANT_INPUT: - /* disable Tx if Mode B (input) is supported */ - /* - RR16( devAddr, SIO_SA_TX_COMMAND__A, &data ); - WR16( devAddr, SIO_SA_TX_COMMAND__A, data & (~SIO_SA_TX_COMMAND_TX_ENABLE__M) ); - */ - default: - return (DRX_STS_INVALID_ARG); - } - /* Write magic word to enable pdr reg write */ - WR16( demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, 0x0000 ); - - return ( DRX_STS_OK ); + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } -static DRXStatus_t -SCUCommand( pI2CDeviceAddr_t devAddr, pDRXJSCUCmd_t cmd ) +static DRXStatus_t SCUCommand(pI2CDeviceAddr_t devAddr, pDRXJSCUCmd_t cmd) { - u16_t curCmd = 0; - u32_t startTime = 0; + u16_t curCmd = 0; + u32_t startTime = 0; - /* Check param */ - if ( cmd == NULL ) - return (DRX_STS_INVALID_ARG); + /* Check param */ + if (cmd == NULL) + return (DRX_STS_INVALID_ARG); - /* Wait until SCU command interface is ready to receive command */ - RR16( devAddr, SCU_RAM_COMMAND__A, &curCmd ); - if ( curCmd != DRX_SCU_READY ) - { - return (DRX_STS_ERROR); - } + /* Wait until SCU command interface is ready to receive command */ + RR16(devAddr, SCU_RAM_COMMAND__A, &curCmd); + if (curCmd != DRX_SCU_READY) { + return (DRX_STS_ERROR); + } - switch ( cmd->parameterLen ) - { - case 5: - WR16( devAddr, SCU_RAM_PARAM_4__A , *(cmd->parameter + 4)); /* fallthrough */ - case 4: - WR16( devAddr, SCU_RAM_PARAM_3__A , *(cmd->parameter + 3)); /* fallthrough */ - case 3: - WR16( devAddr, SCU_RAM_PARAM_2__A , *(cmd->parameter + 2)); /* fallthrough */ - case 2: - WR16( devAddr, SCU_RAM_PARAM_1__A , *(cmd->parameter + 1)); /* fallthrough */ - case 1: - WR16( devAddr, SCU_RAM_PARAM_0__A , *(cmd->parameter + 0)); /* fallthrough */ - case 0: - /* do nothing */ - break; - default: - /* this number of parameters is not supported */ - return (DRX_STS_ERROR); - } - WR16( devAddr, SCU_RAM_COMMAND__A, cmd->command ); - - /* Wait until SCU has processed command */ - startTime = DRXBSP_HST_Clock(); - do{ - RR16( devAddr, SCU_RAM_COMMAND__A, &curCmd ); - } while ( ! ( curCmd == DRX_SCU_READY ) && ( (DRXBSP_HST_Clock() - startTime) < DRXJ_MAX_WAITTIME ) ); - - if ( curCmd != DRX_SCU_READY ) - { - return (DRX_STS_ERROR); - } + switch (cmd->parameterLen) { + case 5: + WR16(devAddr, SCU_RAM_PARAM_4__A, *(cmd->parameter + 4)); /* fallthrough */ + case 4: + WR16(devAddr, SCU_RAM_PARAM_3__A, *(cmd->parameter + 3)); /* fallthrough */ + case 3: + WR16(devAddr, SCU_RAM_PARAM_2__A, *(cmd->parameter + 2)); /* fallthrough */ + case 2: + WR16(devAddr, SCU_RAM_PARAM_1__A, *(cmd->parameter + 1)); /* fallthrough */ + case 1: + WR16(devAddr, SCU_RAM_PARAM_0__A, *(cmd->parameter + 0)); /* fallthrough */ + case 0: + /* do nothing */ + break; + default: + /* this number of parameters is not supported */ + return (DRX_STS_ERROR); + } + WR16(devAddr, SCU_RAM_COMMAND__A, cmd->command); - /* read results */ - if ( (cmd->resultLen > 0) && (cmd->result != NULL) ) - { - s16_t err; - - switch ( cmd->resultLen ) - { - case 4: - RR16( devAddr, SCU_RAM_PARAM_3__A , cmd->result + 3); /* fallthrough */ - case 3: - RR16( devAddr, SCU_RAM_PARAM_2__A , cmd->result + 2); /* fallthrough */ - case 2: - RR16( devAddr, SCU_RAM_PARAM_1__A , cmd->result + 1); /* fallthrough */ - case 1: - RR16( devAddr, SCU_RAM_PARAM_0__A , cmd->result + 0); /* fallthrough */ - case 0: - /* do nothing */ - break; - default: - /* this number of parameters is not supported */ - return (DRX_STS_ERROR); - } - - - /* Check if an error was reported by SCU */ - err = cmd->result[0]; - - /* check a few fixed error codes */ - if ( ( err == (s16_t)SCU_RAM_PARAM_0_RESULT_UNKSTD ) - || ( err == (s16_t)SCU_RAM_PARAM_0_RESULT_UNKCMD ) - || ( err == (s16_t)SCU_RAM_PARAM_0_RESULT_INVPAR ) - || ( err == (s16_t)SCU_RAM_PARAM_0_RESULT_SIZE ) - ) - { - return DRX_STS_INVALID_ARG; - } - /* here it is assumed that negative means error, and positive no error */ - else if ( err < 0 ) - { - return DRX_STS_ERROR; - } - else - { - return DRX_STS_OK; - } - } - - return (DRX_STS_OK); - - rw_error: - return (DRX_STS_ERROR); + /* Wait until SCU has processed command */ + startTime = DRXBSP_HST_Clock(); + do { + RR16(devAddr, SCU_RAM_COMMAND__A, &curCmd); + } while (!(curCmd == DRX_SCU_READY) + && ((DRXBSP_HST_Clock() - startTime) < DRXJ_MAX_WAITTIME)); + + if (curCmd != DRX_SCU_READY) { + return (DRX_STS_ERROR); + } + + /* read results */ + if ((cmd->resultLen > 0) && (cmd->result != NULL)) { + s16_t err; + + switch (cmd->resultLen) { + case 4: + RR16(devAddr, SCU_RAM_PARAM_3__A, cmd->result + 3); /* fallthrough */ + case 3: + RR16(devAddr, SCU_RAM_PARAM_2__A, cmd->result + 2); /* fallthrough */ + case 2: + RR16(devAddr, SCU_RAM_PARAM_1__A, cmd->result + 1); /* fallthrough */ + case 1: + RR16(devAddr, SCU_RAM_PARAM_0__A, cmd->result + 0); /* fallthrough */ + case 0: + /* do nothing */ + break; + default: + /* this number of parameters is not supported */ + return (DRX_STS_ERROR); + } + + /* Check if an error was reported by SCU */ + err = cmd->result[0]; + + /* check a few fixed error codes */ + if ((err == (s16_t) SCU_RAM_PARAM_0_RESULT_UNKSTD) + || (err == (s16_t) SCU_RAM_PARAM_0_RESULT_UNKCMD) + || (err == (s16_t) SCU_RAM_PARAM_0_RESULT_INVPAR) + || (err == (s16_t) SCU_RAM_PARAM_0_RESULT_SIZE) + ) { + return DRX_STS_INVALID_ARG; + } + /* here it is assumed that negative means error, and positive no error */ + else if (err < 0) { + return DRX_STS_ERROR; + } else { + return DRX_STS_OK; + } + } + + return (DRX_STS_OK); + +rw_error: + return (DRX_STS_ERROR); } + /** * \fn DRXStatus_t DRXJ_DAP_SCUAtomicReadWriteBlock() * \brief Basic access routine for SCU atomic read or write access @@ -4342,65 +4095,57 @@ SCUCommand( pI2CDeviceAddr_t devAddr, pDRXJSCUCmd_t cmd ) */ #define ADDR_AT_SCU_SPACE(x) ((x - 0x82E000) * 2) static -DRXStatus_t DRXJ_DAP_SCU_AtomicReadWriteBlock ( - pI2CDeviceAddr_t devAddr, - DRXaddr_t addr, - u16_t datasize, /* max 30 bytes because the limit of SCU parameter */ - pu8_t data, - Bool_t readFlag) -{ - DRXJSCUCmd_t scuCmd; - u16_t setParamParameters[15]; - u16_t cmdResult[15]; - - /* Parameter check */ - if ( ( data == NULL ) || - ( devAddr == NULL ) || - ( (datasize%2)!= 0 ) || - ( (datasize/2) > 16 ) - ) - { - return (DRX_STS_INVALID_ARG); - } +DRXStatus_t DRXJ_DAP_SCU_AtomicReadWriteBlock(pI2CDeviceAddr_t devAddr, DRXaddr_t addr, u16_t datasize, /* max 30 bytes because the limit of SCU parameter */ + pu8_t data, Bool_t readFlag) +{ + DRXJSCUCmd_t scuCmd; + u16_t setParamParameters[15]; + u16_t cmdResult[15]; + + /* Parameter check */ + if ((data == NULL) || + (devAddr == NULL) || ((datasize % 2) != 0) || ((datasize / 2) > 16) + ) { + return (DRX_STS_INVALID_ARG); + } - setParamParameters[1] = (u16_t)ADDR_AT_SCU_SPACE (addr); - if (readFlag) /* read */ - { - setParamParameters[0] = ((~(0x0080)) & datasize); - scuCmd.parameterLen = 2; - scuCmd.resultLen = datasize/2 + 2; - } else { - int i = 0; - - setParamParameters[0] = 0x0080 | datasize; - for (i = 0; i < (datasize/2); i++) - { - setParamParameters[i+2] = (data[2*i] | (data[(2*i)+1]<<8)); - } - scuCmd.parameterLen = datasize / 2 + 2; - scuCmd.resultLen = 1; - } - - scuCmd.command = SCU_RAM_COMMAND_STANDARD_TOP | SCU_RAM_COMMAND_CMD_AUX_SCU_ATOMIC_ACCESS; - scuCmd.result = cmdResult; - scuCmd.parameter = setParamParameters; - CHK_ERROR( SCUCommand( devAddr, &scuCmd ) ); - - if ( readFlag==TRUE ) - { - int i = 0; - /* read data from buffer */ - for (i = 0; i < (datasize/2); i++) - { - data[2*i] = (u8_t) (scuCmd.result[i+2] & 0xFF); - data[(2*i) + 1] = (u8_t) (scuCmd.result[i+2] >> 8 ); - } - } + setParamParameters[1] = (u16_t) ADDR_AT_SCU_SPACE(addr); + if (readFlag) { /* read */ + setParamParameters[0] = ((~(0x0080)) & datasize); + scuCmd.parameterLen = 2; + scuCmd.resultLen = datasize / 2 + 2; + } else { + int i = 0; + + setParamParameters[0] = 0x0080 | datasize; + for (i = 0; i < (datasize / 2); i++) { + setParamParameters[i + 2] = + (data[2 * i] | (data[(2 * i) + 1] << 8)); + } + scuCmd.parameterLen = datasize / 2 + 2; + scuCmd.resultLen = 1; + } + + scuCmd.command = + SCU_RAM_COMMAND_STANDARD_TOP | + SCU_RAM_COMMAND_CMD_AUX_SCU_ATOMIC_ACCESS; + scuCmd.result = cmdResult; + scuCmd.parameter = setParamParameters; + CHK_ERROR(SCUCommand(devAddr, &scuCmd)); + + if (readFlag == TRUE) { + int i = 0; + /* read data from buffer */ + for (i = 0; i < (datasize / 2); i++) { + data[2 * i] = (u8_t) (scuCmd.result[i + 2] & 0xFF); + data[(2 * i) + 1] = (u8_t) (scuCmd.result[i + 2] >> 8); + } + } - return DRX_STS_OK; + return DRX_STS_OK; - rw_error: - return (DRX_STS_ERROR); +rw_error: + return (DRX_STS_ERROR); } @@ -4411,76 +4156,68 @@ DRXStatus_t DRXJ_DAP_SCU_AtomicReadWriteBlock ( * \brief Atomic read of 16 bits words */ static -DRXStatus_t DRXJ_DAP_SCU_AtomicReadReg16 ( - pI2CDeviceAddr_t devAddr, - DRXaddr_t addr, - pu16_t data, - DRXflags_t flags) +DRXStatus_t DRXJ_DAP_SCU_AtomicReadReg16(pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + pu16_t data, DRXflags_t flags) { - u8_t buf[2]; - DRXStatus_t rc = DRX_STS_ERROR; - u16_t word = 0; + u8_t buf[2]; + DRXStatus_t rc = DRX_STS_ERROR; + u16_t word = 0; - if (!data) - { - return DRX_STS_INVALID_ARG; - } + if (!data) { + return DRX_STS_INVALID_ARG; + } - rc = DRXJ_DAP_SCU_AtomicReadWriteBlock ( devAddr, addr, - 2, buf, TRUE); + rc = DRXJ_DAP_SCU_AtomicReadWriteBlock(devAddr, addr, 2, buf, TRUE); - word = (u16_t)(buf[0] + (buf[1] << 8)); + word = (u16_t) (buf[0] + (buf[1] << 8)); - *data = word; + *data = word; - return rc; + return rc; } + /*============================================================================*/ /** * \fn DRXStatus_t DRXJ_DAP_SCU_AtomicWriteReg16() * \brief Atomic read of 16 bits words */ static -DRXStatus_t DRXJ_DAP_SCU_AtomicWriteReg16 ( - pI2CDeviceAddr_t devAddr, - DRXaddr_t addr, - u16_t data, - DRXflags_t flags) +DRXStatus_t DRXJ_DAP_SCU_AtomicWriteReg16(pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + u16_t data, DRXflags_t flags) { - u8_t buf[2]; - DRXStatus_t rc = DRX_STS_ERROR; + u8_t buf[2]; + DRXStatus_t rc = DRX_STS_ERROR; - buf[0] = (u8_t) (data & 0xff); - buf[1] = (u8_t) ((data >> 8) & 0xff); + buf[0] = (u8_t) (data & 0xff); + buf[1] = (u8_t) ((data >> 8) & 0xff); - rc = DRXJ_DAP_SCU_AtomicReadWriteBlock ( devAddr, addr, - 2, buf, FALSE); + rc = DRXJ_DAP_SCU_AtomicReadWriteBlock(devAddr, addr, 2, buf, FALSE); - return rc; + return rc; } static DRXStatus_t -CtrlI2CWriteRead( pDRXDemodInstance_t demod, - pDRXI2CData_t i2cData ) +CtrlI2CWriteRead(pDRXDemodInstance_t demod, pDRXI2CData_t i2cData) { - return (DRX_STS_FUNC_NOT_AVAILABLE); + return (DRX_STS_FUNC_NOT_AVAILABLE); } DRXStatus_t -TunerI2CWriteRead( pTUNERInstance_t tuner, - pI2CDeviceAddr_t wDevAddr, - u16_t wCount, - pu8_t wData, - pI2CDeviceAddr_t rDevAddr, - u16_t rCount, - pu8_t rData) +TunerI2CWriteRead(pTUNERInstance_t tuner, + pI2CDeviceAddr_t wDevAddr, + u16_t wCount, + pu8_t wData, + pI2CDeviceAddr_t rDevAddr, u16_t rCount, pu8_t rData) { - pDRXDemodInstance_t demod; - DRXI2CData_t i2cData = { 2, wDevAddr, wCount, wData, rDevAddr, rCount, rData }; + pDRXDemodInstance_t demod; + DRXI2CData_t i2cData = + { 2, wDevAddr, wCount, wData, rDevAddr, rCount, rData }; - demod = (pDRXDemodInstance_t) (tuner->myCommonAttr->myUserData); + demod = (pDRXDemodInstance_t) (tuner->myCommonAttr->myUserData); - return ( CtrlI2CWriteRead( demod, &i2cData ) ); + return (CtrlI2CWriteRead(demod, &i2cData)); } /* -------------------------------------------------------------------------- */ @@ -4493,42 +4230,37 @@ TunerI2CWriteRead( pTUNERInstance_t tuner, * \retval DRX_STS_ERROR Failure: I2C error * */ -static DRXStatus_t -ADCSyncMeasurement( pDRXDemodInstance_t demod, - pu16_t count ) +static DRXStatus_t ADCSyncMeasurement(pDRXDemodInstance_t demod, pu16_t count) { - u16_t data = 0; - pI2CDeviceAddr_t devAddr = NULL; + u16_t data = 0; + pI2CDeviceAddr_t devAddr = NULL; - devAddr = demod -> myI2CDevAddr; + devAddr = demod->myI2CDevAddr; - /* Start measurement */ - WR16( devAddr, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE); - WR16( devAddr, IQM_AF_START_LOCK__A, 1); + /* Start measurement */ + WR16(devAddr, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE); + WR16(devAddr, IQM_AF_START_LOCK__A, 1); - /* Wait at least 3*128*(1/sysclk) <<< 1 millisec */ - CHK_ERROR( DRXBSP_HST_Sleep(1)); + /* Wait at least 3*128*(1/sysclk) <<< 1 millisec */ + CHK_ERROR(DRXBSP_HST_Sleep(1)); - *count = 0; - RR16( devAddr, IQM_AF_PHASE0__A, &data); - if ( data == 127 ) - { - *count = *count+1; - } - RR16( devAddr, IQM_AF_PHASE1__A, &data); - if ( data == 127 ) - { - *count = *count+1; - } - RR16( devAddr, IQM_AF_PHASE2__A, &data); - if ( data == 127 ) - { - *count = *count+1; - } + *count = 0; + RR16(devAddr, IQM_AF_PHASE0__A, &data); + if (data == 127) { + *count = *count + 1; + } + RR16(devAddr, IQM_AF_PHASE1__A, &data); + if (data == 127) { + *count = *count + 1; + } + RR16(devAddr, IQM_AF_PHASE2__A, &data); + if (data == 127) { + *count = *count + 1; + } - return (DRX_STS_OK); + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /** @@ -4543,38 +4275,35 @@ rw_error: * */ -static DRXStatus_t -ADCSynchronization( pDRXDemodInstance_t demod ) +static DRXStatus_t ADCSynchronization(pDRXDemodInstance_t demod) { - u16_t count = 0; - pI2CDeviceAddr_t devAddr = NULL; + u16_t count = 0; + pI2CDeviceAddr_t devAddr = NULL; - devAddr = demod -> myI2CDevAddr; + devAddr = demod->myI2CDevAddr; - CHK_ERROR( ADCSyncMeasurement( demod, &count )); + CHK_ERROR(ADCSyncMeasurement(demod, &count)); - if (count==1) - { - /* Try sampling on a diffrent edge */ - u16_t clkNeg = 0; + if (count == 1) { + /* Try sampling on a diffrent edge */ + u16_t clkNeg = 0; - RR16( devAddr, IQM_AF_CLKNEG__A, &clkNeg); + RR16(devAddr, IQM_AF_CLKNEG__A, &clkNeg); - clkNeg ^= IQM_AF_CLKNEG_CLKNEGDATA__M; - WR16( devAddr, IQM_AF_CLKNEG__A, clkNeg); + clkNeg ^= IQM_AF_CLKNEG_CLKNEGDATA__M; + WR16(devAddr, IQM_AF_CLKNEG__A, clkNeg); - CHK_ERROR( ADCSyncMeasurement( demod, &count )); - } + CHK_ERROR(ADCSyncMeasurement(demod, &count)); + } - if ( count < 2 ) - { - /* TODO: implement fallback scenarios */ - return (DRX_STS_ERROR); - } + if (count < 2) { + /* TODO: implement fallback scenarios */ + return (DRX_STS_ERROR); + } - return (DRX_STS_OK); + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /** @@ -4583,46 +4312,42 @@ rw_error: * \param active * \return DRXStatus_t. */ -static DRXStatus_t -IQMSetAf ( pDRXDemodInstance_t demod, Bool_t active ) +static DRXStatus_t IQMSetAf(pDRXDemodInstance_t demod, Bool_t active) { - u16_t data = 0; - pI2CDeviceAddr_t devAddr = NULL; - pDRXJData_t extAttr = NULL; + u16_t data = 0; + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; - extAttr = (pDRXJData_t)demod->myExtAttr; - devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; + devAddr = demod->myI2CDevAddr; - /* Configure IQM */ - RR16( devAddr, IQM_AF_STDBY__A , &data ); - if( !active ) - { - data &= ((~IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE) - & (~IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE) - & (~IQM_AF_STDBY_STDBY_PD_A2_ACTIVE) - & (~IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE) - & (~IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE) - ); - } else /* active */ - { - data |= (IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE - | IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE - | IQM_AF_STDBY_STDBY_PD_A2_ACTIVE - | IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE - | IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE - ); - } - WR16( devAddr, IQM_AF_STDBY__A , data ); - - return (DRX_STS_OK); + /* Configure IQM */ + RR16(devAddr, IQM_AF_STDBY__A, &data); + if (!active) { + data &= ((~IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE) + & (~IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE) + & (~IQM_AF_STDBY_STDBY_PD_A2_ACTIVE) + & (~IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE) + & (~IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE) + ); + } else { /* active */ + + data |= (IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE + | IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE + | IQM_AF_STDBY_STDBY_PD_A2_ACTIVE + | IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE + | IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE); + } + WR16(devAddr, IQM_AF_STDBY__A, data); + + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /* -------------------------------------------------------------------------- */ static DRXStatus_t -CtrlSetCfgATVOutput( pDRXDemodInstance_t demod , - pDRXJCfgAtvOutput_t outputCfg ); +CtrlSetCfgATVOutput(pDRXDemodInstance_t demod, pDRXJCfgAtvOutput_t outputCfg); /** * \brief set configuration of pin-safe mode @@ -4631,115 +4356,121 @@ CtrlSetCfgATVOutput( pDRXDemodInstance_t demod , * \return DRXStatus_t. */ static DRXStatus_t -CtrlSetCfgPdrSafeMode ( pDRXDemodInstance_t demod, - pBool_t enable ) +CtrlSetCfgPdrSafeMode(pDRXDemodInstance_t demod, pBool_t enable) { - pDRXJData_t extAttr = (pDRXJData_t) NULL; - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) NULL; - pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) NULL; - - if ( enable == NULL) - { - return (DRX_STS_INVALID_ARG); - } + pDRXJData_t extAttr = (pDRXJData_t) NULL; + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) NULL; + pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) NULL; - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; - commonAttr = demod->myCommonAttr; - - /* Write magic word to enable pdr reg write */ - WR16( devAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY ); - - if ( *enable == TRUE ) - { - Bool_t bridgeEnabled = FALSE; - - /* MPEG pins to input */ - WR16 ( devAddr, SIO_PDR_MSTRT_CFG__A, DRXJ_PIN_SAFE_MODE ); - WR16 ( devAddr, SIO_PDR_MERR_CFG__A, DRXJ_PIN_SAFE_MODE ); - WR16 ( devAddr, SIO_PDR_MCLK_CFG__A, DRXJ_PIN_SAFE_MODE ); - WR16 ( devAddr, SIO_PDR_MVAL_CFG__A, DRXJ_PIN_SAFE_MODE ); - WR16 ( devAddr, SIO_PDR_MD0_CFG__A, DRXJ_PIN_SAFE_MODE ); - WR16 ( devAddr, SIO_PDR_MD1_CFG__A, DRXJ_PIN_SAFE_MODE ); - WR16 ( devAddr, SIO_PDR_MD2_CFG__A, DRXJ_PIN_SAFE_MODE ); - WR16 ( devAddr, SIO_PDR_MD3_CFG__A, DRXJ_PIN_SAFE_MODE ); - WR16 ( devAddr, SIO_PDR_MD4_CFG__A, DRXJ_PIN_SAFE_MODE ); - WR16 ( devAddr, SIO_PDR_MD5_CFG__A, DRXJ_PIN_SAFE_MODE ); - WR16 ( devAddr, SIO_PDR_MD6_CFG__A, DRXJ_PIN_SAFE_MODE ); - WR16 ( devAddr, SIO_PDR_MD7_CFG__A, DRXJ_PIN_SAFE_MODE ); - - /* PD_I2C_SDA2 Bridge off, Port2 Inactive - PD_I2C_SCL2 Bridge off, Port2 Inactive */ - CHK_ERROR( CtrlI2CBridge( demod, &bridgeEnabled ) ); - WR16 ( devAddr, SIO_PDR_I2C_SDA2_CFG__A, DRXJ_PIN_SAFE_MODE ); - WR16 ( devAddr, SIO_PDR_I2C_SCL2_CFG__A, DRXJ_PIN_SAFE_MODE ); - - /* PD_GPIO Store and set to input - PD_VSYNC Store and set to input - PD_SMA_RX Store and set to input - PD_SMA_TX Store and set to input */ - RR16 ( devAddr, SIO_PDR_GPIO_CFG__A, &extAttr->pdrSafeRestoreValGpio ); - RR16 ( devAddr, SIO_PDR_VSYNC_CFG__A, &extAttr->pdrSafeRestoreValVSync ); - RR16 ( devAddr, SIO_PDR_SMA_RX_CFG__A, &extAttr->pdrSafeRestoreValSmaRx ); - RR16 ( devAddr, SIO_PDR_SMA_TX_CFG__A, &extAttr->pdrSafeRestoreValSmaTx ); - WR16 ( devAddr, SIO_PDR_GPIO_CFG__A, DRXJ_PIN_SAFE_MODE ); - WR16 ( devAddr, SIO_PDR_VSYNC_CFG__A, DRXJ_PIN_SAFE_MODE ); - WR16 ( devAddr, SIO_PDR_SMA_RX_CFG__A, DRXJ_PIN_SAFE_MODE ); - WR16 ( devAddr, SIO_PDR_SMA_TX_CFG__A, DRXJ_PIN_SAFE_MODE ); - - /* PD_RF_AGC Analog DAC outputs, cannot be set to input or tristate! - PD_IF_AGC Analog DAC outputs, cannot be set to input or tristate! */ - CHK_ERROR( IQMSetAf ( demod, FALSE ) ); - - /* PD_CVBS Analog DAC output, standby mode - PD_SIF Analog DAC output, standby mode */ - WR16 ( devAddr, ATV_TOP_STDBY__A, ( ATV_TOP_STDBY_SIF_STDBY_STANDBY & - (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE) ) ); - - /* PD_I2S_CL Input - PD_I2S_DA Input - PD_I2S_WS Input */ - WR16 ( devAddr, SIO_PDR_I2S_CL_CFG__A, DRXJ_PIN_SAFE_MODE ); - WR16 ( devAddr, SIO_PDR_I2S_DA_CFG__A, DRXJ_PIN_SAFE_MODE ); - WR16 ( devAddr, SIO_PDR_I2S_WS_CFG__A, DRXJ_PIN_SAFE_MODE ); - } - else - { - /* No need to restore MPEG pins; - is done in SetStandard/SetChannel */ - - /* PD_I2C_SDA2 Port2 active - PD_I2C_SCL2 Port2 active */ - WR16 ( devAddr, SIO_PDR_I2C_SDA2_CFG__A, SIO_PDR_I2C_SDA2_CFG__PRE ); - WR16 ( devAddr, SIO_PDR_I2C_SCL2_CFG__A, SIO_PDR_I2C_SCL2_CFG__PRE ); - - /* PD_GPIO Restore - PD_VSYNC Restore - PD_SMA_RX Restore - PD_SMA_TX Restore */ - WR16 ( devAddr, SIO_PDR_GPIO_CFG__A, extAttr->pdrSafeRestoreValGpio ); - WR16 ( devAddr, SIO_PDR_VSYNC_CFG__A, extAttr->pdrSafeRestoreValVSync ); - WR16 ( devAddr, SIO_PDR_SMA_RX_CFG__A, extAttr->pdrSafeRestoreValSmaRx ); - WR16 ( devAddr, SIO_PDR_SMA_TX_CFG__A, extAttr->pdrSafeRestoreValSmaTx ); - - /* PD_RF_AGC, PD_IF_AGC - No need to restore; will be restored in SetStandard/SetChannel */ - - /* PD_CVBS, PD_SIF - No need to restore; will be restored in SetStandard/SetChannel */ + if (enable == NULL) { + return (DRX_STS_INVALID_ARG); + } - /* PD_I2S_CL, PD_I2S_DA, PD_I2S_WS - Should be restored via DRX_CTRL_SET_AUD */ - } + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; + commonAttr = demod->myCommonAttr; + + /* Write magic word to enable pdr reg write */ + WR16(devAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); + + if (*enable == TRUE) { + Bool_t bridgeEnabled = FALSE; + + /* MPEG pins to input */ + WR16(devAddr, SIO_PDR_MSTRT_CFG__A, DRXJ_PIN_SAFE_MODE); + WR16(devAddr, SIO_PDR_MERR_CFG__A, DRXJ_PIN_SAFE_MODE); + WR16(devAddr, SIO_PDR_MCLK_CFG__A, DRXJ_PIN_SAFE_MODE); + WR16(devAddr, SIO_PDR_MVAL_CFG__A, DRXJ_PIN_SAFE_MODE); + WR16(devAddr, SIO_PDR_MD0_CFG__A, DRXJ_PIN_SAFE_MODE); + WR16(devAddr, SIO_PDR_MD1_CFG__A, DRXJ_PIN_SAFE_MODE); + WR16(devAddr, SIO_PDR_MD2_CFG__A, DRXJ_PIN_SAFE_MODE); + WR16(devAddr, SIO_PDR_MD3_CFG__A, DRXJ_PIN_SAFE_MODE); + WR16(devAddr, SIO_PDR_MD4_CFG__A, DRXJ_PIN_SAFE_MODE); + WR16(devAddr, SIO_PDR_MD5_CFG__A, DRXJ_PIN_SAFE_MODE); + WR16(devAddr, SIO_PDR_MD6_CFG__A, DRXJ_PIN_SAFE_MODE); + WR16(devAddr, SIO_PDR_MD7_CFG__A, DRXJ_PIN_SAFE_MODE); + + /* PD_I2C_SDA2 Bridge off, Port2 Inactive + PD_I2C_SCL2 Bridge off, Port2 Inactive */ + CHK_ERROR(CtrlI2CBridge(demod, &bridgeEnabled)); + WR16(devAddr, SIO_PDR_I2C_SDA2_CFG__A, DRXJ_PIN_SAFE_MODE); + WR16(devAddr, SIO_PDR_I2C_SCL2_CFG__A, DRXJ_PIN_SAFE_MODE); + + /* PD_GPIO Store and set to input + PD_VSYNC Store and set to input + PD_SMA_RX Store and set to input + PD_SMA_TX Store and set to input */ + RR16(devAddr, SIO_PDR_GPIO_CFG__A, + &extAttr->pdrSafeRestoreValGpio); + RR16(devAddr, SIO_PDR_VSYNC_CFG__A, + &extAttr->pdrSafeRestoreValVSync); + RR16(devAddr, SIO_PDR_SMA_RX_CFG__A, + &extAttr->pdrSafeRestoreValSmaRx); + RR16(devAddr, SIO_PDR_SMA_TX_CFG__A, + &extAttr->pdrSafeRestoreValSmaTx); + WR16(devAddr, SIO_PDR_GPIO_CFG__A, DRXJ_PIN_SAFE_MODE); + WR16(devAddr, SIO_PDR_VSYNC_CFG__A, DRXJ_PIN_SAFE_MODE); + WR16(devAddr, SIO_PDR_SMA_RX_CFG__A, DRXJ_PIN_SAFE_MODE); + WR16(devAddr, SIO_PDR_SMA_TX_CFG__A, DRXJ_PIN_SAFE_MODE); + + /* PD_RF_AGC Analog DAC outputs, cannot be set to input or tristate! + PD_IF_AGC Analog DAC outputs, cannot be set to input or tristate! */ + CHK_ERROR(IQMSetAf(demod, FALSE)); + + /* PD_CVBS Analog DAC output, standby mode + PD_SIF Analog DAC output, standby mode */ + WR16(devAddr, ATV_TOP_STDBY__A, + (ATV_TOP_STDBY_SIF_STDBY_STANDBY & + (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE))); + + /* PD_I2S_CL Input + PD_I2S_DA Input + PD_I2S_WS Input */ + WR16(devAddr, SIO_PDR_I2S_CL_CFG__A, DRXJ_PIN_SAFE_MODE); + WR16(devAddr, SIO_PDR_I2S_DA_CFG__A, DRXJ_PIN_SAFE_MODE); + WR16(devAddr, SIO_PDR_I2S_WS_CFG__A, DRXJ_PIN_SAFE_MODE); + } else { + /* No need to restore MPEG pins; + is done in SetStandard/SetChannel */ + + /* PD_I2C_SDA2 Port2 active + PD_I2C_SCL2 Port2 active */ + WR16(devAddr, SIO_PDR_I2C_SDA2_CFG__A, + SIO_PDR_I2C_SDA2_CFG__PRE); + WR16(devAddr, SIO_PDR_I2C_SCL2_CFG__A, + SIO_PDR_I2C_SCL2_CFG__PRE); + + /* PD_GPIO Restore + PD_VSYNC Restore + PD_SMA_RX Restore + PD_SMA_TX Restore */ + WR16(devAddr, SIO_PDR_GPIO_CFG__A, + extAttr->pdrSafeRestoreValGpio); + WR16(devAddr, SIO_PDR_VSYNC_CFG__A, + extAttr->pdrSafeRestoreValVSync); + WR16(devAddr, SIO_PDR_SMA_RX_CFG__A, + extAttr->pdrSafeRestoreValSmaRx); + WR16(devAddr, SIO_PDR_SMA_TX_CFG__A, + extAttr->pdrSafeRestoreValSmaTx); + + /* PD_RF_AGC, PD_IF_AGC + No need to restore; will be restored in SetStandard/SetChannel */ + + /* PD_CVBS, PD_SIF + No need to restore; will be restored in SetStandard/SetChannel */ + + /* PD_I2S_CL, PD_I2S_DA, PD_I2S_WS + Should be restored via DRX_CTRL_SET_AUD */ + } - /* Write magic word to disable pdr reg write */ - WR16 ( devAddr, SIO_TOP_COMM_KEY__A, 0x0000 ); - extAttr->pdrSafeMode = *enable; + /* Write magic word to disable pdr reg write */ + WR16(devAddr, SIO_TOP_COMM_KEY__A, 0x0000); + extAttr->pdrSafeMode = *enable; - return (DRX_STS_OK); + return (DRX_STS_OK); - rw_error: - return (DRX_STS_ERROR); +rw_error: + return (DRX_STS_ERROR); } /* -------------------------------------------------------------------------- */ @@ -4751,20 +4482,18 @@ CtrlSetCfgPdrSafeMode ( pDRXDemodInstance_t demod, * \return DRXStatus_t. */ static DRXStatus_t -CtrlGetCfgPdrSafeMode ( pDRXDemodInstance_t demod, - pBool_t enabled ) +CtrlGetCfgPdrSafeMode(pDRXDemodInstance_t demod, pBool_t enabled) { - pDRXJData_t extAttr = (pDRXJData_t) NULL; + pDRXJData_t extAttr = (pDRXJData_t) NULL; - if ( enabled == NULL ) - { - return (DRX_STS_INVALID_ARG); - } + if (enabled == NULL) { + return (DRX_STS_INVALID_ARG); + } - extAttr = (pDRXJData_t) demod->myExtAttr; - *enabled = extAttr->pdrSafeMode; + extAttr = (pDRXJData_t) demod->myExtAttr; + *enabled = extAttr->pdrSafeMode; - return (DRX_STS_OK); + return (DRX_STS_OK); } /** @@ -4772,41 +4501,36 @@ CtrlGetCfgPdrSafeMode ( pDRXDemodInstance_t demod, * \param demod Demodulator instance. * \return DRXStatus_t. */ -static DRXStatus_t -CtrlValidateUCode (pDRXDemodInstance_t demod) +static DRXStatus_t CtrlValidateUCode(pDRXDemodInstance_t demod) { - u32_t mcDev, mcPatch; - u16_t verType; - - /* Check device. - * Disallow microcode if: - * - MC has version record AND - * - device ID in version record is not 0 AND - * - product ID in version record's device ID does not - * match DRXJ1 product IDs - 0x393 or 0x394 - */ - DRX_GET_MCVERTYPE (demod, verType); - DRX_GET_MCDEV (demod, mcDev); - DRX_GET_MCPATCH (demod, mcPatch); - - if (DRX_ISMCVERTYPE (verType)) - { - if ((mcDev != 0) && - (((mcDev >> 16) & 0xFFF) != 0x393) && - (((mcDev >> 16) & 0xFFF) != 0x394)) - { - /* Microcode is marked for another device - error */ - return DRX_STS_INVALID_ARG; - } - else if (mcPatch != 0) - { - /* Patch not allowed because there is no ROM */ - return DRX_STS_INVALID_ARG; - } - } - - /* Everything else: OK */ - return DRX_STS_OK; + u32_t mcDev, mcPatch; + u16_t verType; + + /* Check device. + * Disallow microcode if: + * - MC has version record AND + * - device ID in version record is not 0 AND + * - product ID in version record's device ID does not + * match DRXJ1 product IDs - 0x393 or 0x394 + */ + DRX_GET_MCVERTYPE(demod, verType); + DRX_GET_MCDEV(demod, mcDev); + DRX_GET_MCPATCH(demod, mcPatch); + + if (DRX_ISMCVERTYPE(verType)) { + if ((mcDev != 0) && + (((mcDev >> 16) & 0xFFF) != 0x393) && + (((mcDev >> 16) & 0xFFF) != 0x394)) { + /* Microcode is marked for another device - error */ + return DRX_STS_INVALID_ARG; + } else if (mcPatch != 0) { + /* Patch not allowed because there is no ROM */ + return DRX_STS_INVALID_ARG; + } + } + + /* Everything else: OK */ + return DRX_STS_OK; } /*============================================================================*/ @@ -4825,207 +4549,203 @@ CtrlValidateUCode (pDRXDemodInstance_t demod) * \param channel pointer to channel data. * \return DRXStatus_t. */ -static DRXStatus_t -InitAGC ( pDRXDemodInstance_t demod ) -{ - pI2CDeviceAddr_t devAddr = NULL; - pDRXCommonAttr_t commonAttr = NULL; - pDRXJData_t extAttr = NULL; - pDRXJCfgAgc_t pAgcRfSettings = NULL; - pDRXJCfgAgc_t pAgcIfSettings = NULL; - u16_t IngainTgtMax = 0; - u16_t clpDirTo = 0; - u16_t snsSumMax = 0; - u16_t clpSumMax = 0; - u16_t snsDirTo = 0; - u16_t kiInnergainMin = 0; - u16_t agcKi = 0; - u16_t kiMax = 0; - u16_t ifIaccuHiTgtMin = 0; - u16_t data = 0; - u16_t agcKiDgain = 0; - u16_t kiMin = 0; - u16_t clpCtrlMode = 0; - u16_t agcRf = 0; - u16_t agcIf = 0; - devAddr = demod->myI2CDevAddr; - commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; - extAttr = (pDRXJData_t)demod->myExtAttr; - - switch (extAttr->standard) - { - case DRX_STANDARD_8VSB : - clpSumMax = 1023; - clpDirTo = (u16_t)(-9); - snsSumMax = 1023; - snsDirTo = (u16_t)(-9); - kiInnergainMin = (u16_t)(-32768); - kiMax = 0x032C; - agcKiDgain = 0xC; - ifIaccuHiTgtMin = 2047; - kiMin = 0x0117; - IngainTgtMax = 16383; - clpCtrlMode = 0; - WR16( devAddr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff ); - WR16( devAddr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0 ); - WR16( devAddr, SCU_RAM_AGC_CLP_SUM__A, 0 ); - WR16( devAddr, SCU_RAM_AGC_CLP_CYCCNT__A, 0 ); - WR16( devAddr, SCU_RAM_AGC_CLP_DIR_WD__A, 0 ); - WR16( devAddr, SCU_RAM_AGC_CLP_DIR_STP__A, 1 ); - WR16( devAddr, SCU_RAM_AGC_SNS_SUM__A, 0 ); - WR16( devAddr, SCU_RAM_AGC_SNS_CYCCNT__A, 0 ); - WR16( devAddr, SCU_RAM_AGC_SNS_DIR_WD__A, 0 ); - WR16( devAddr, SCU_RAM_AGC_SNS_DIR_STP__A, 1 ); - WR16( devAddr, SCU_RAM_AGC_INGAIN__A, 1024 ); - WR16( devAddr, SCU_RAM_VSB_AGC_POW_TGT__A, 22600 ); - WR16( devAddr, SCU_RAM_AGC_INGAIN_TGT__A, 13200 ); - pAgcIfSettings = &(extAttr->vsbIfAgcCfg); - pAgcRfSettings = &(extAttr->vsbRfAgcCfg); - break; +static DRXStatus_t InitAGC(pDRXDemodInstance_t demod) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXCommonAttr_t commonAttr = NULL; + pDRXJData_t extAttr = NULL; + pDRXJCfgAgc_t pAgcRfSettings = NULL; + pDRXJCfgAgc_t pAgcIfSettings = NULL; + u16_t IngainTgtMax = 0; + u16_t clpDirTo = 0; + u16_t snsSumMax = 0; + u16_t clpSumMax = 0; + u16_t snsDirTo = 0; + u16_t kiInnergainMin = 0; + u16_t agcKi = 0; + u16_t kiMax = 0; + u16_t ifIaccuHiTgtMin = 0; + u16_t data = 0; + u16_t agcKiDgain = 0; + u16_t kiMin = 0; + u16_t clpCtrlMode = 0; + u16_t agcRf = 0; + u16_t agcIf = 0; + devAddr = demod->myI2CDevAddr; + commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; + extAttr = (pDRXJData_t) demod->myExtAttr; + + switch (extAttr->standard) { + case DRX_STANDARD_8VSB: + clpSumMax = 1023; + clpDirTo = (u16_t) (-9); + snsSumMax = 1023; + snsDirTo = (u16_t) (-9); + kiInnergainMin = (u16_t) (-32768); + kiMax = 0x032C; + agcKiDgain = 0xC; + ifIaccuHiTgtMin = 2047; + kiMin = 0x0117; + IngainTgtMax = 16383; + clpCtrlMode = 0; + WR16(devAddr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff); + WR16(devAddr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0); + WR16(devAddr, SCU_RAM_AGC_CLP_SUM__A, 0); + WR16(devAddr, SCU_RAM_AGC_CLP_CYCCNT__A, 0); + WR16(devAddr, SCU_RAM_AGC_CLP_DIR_WD__A, 0); + WR16(devAddr, SCU_RAM_AGC_CLP_DIR_STP__A, 1); + WR16(devAddr, SCU_RAM_AGC_SNS_SUM__A, 0); + WR16(devAddr, SCU_RAM_AGC_SNS_CYCCNT__A, 0); + WR16(devAddr, SCU_RAM_AGC_SNS_DIR_WD__A, 0); + WR16(devAddr, SCU_RAM_AGC_SNS_DIR_STP__A, 1); + WR16(devAddr, SCU_RAM_AGC_INGAIN__A, 1024); + WR16(devAddr, SCU_RAM_VSB_AGC_POW_TGT__A, 22600); + WR16(devAddr, SCU_RAM_AGC_INGAIN_TGT__A, 13200); + pAgcIfSettings = &(extAttr->vsbIfAgcCfg); + pAgcRfSettings = &(extAttr->vsbRfAgcCfg); + break; #ifndef DRXJ_VSB_ONLY - case DRX_STANDARD_ITU_A: - case DRX_STANDARD_ITU_C: - case DRX_STANDARD_ITU_B: - IngainTgtMax = 5119; - clpSumMax = 1023; - clpDirTo = (u16_t)(-5); - snsSumMax = 127; - snsDirTo = (u16_t)(-3); - kiInnergainMin = 0; - kiMax = 0x0657; - ifIaccuHiTgtMin = 2047; - agcKiDgain = 0x7; - kiMin = 0x0117; - clpCtrlMode = 0; - WR16( devAddr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff ); - WR16( devAddr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0 ); - WR16( devAddr, SCU_RAM_AGC_CLP_SUM__A, 0 ); - WR16( devAddr, SCU_RAM_AGC_CLP_CYCCNT__A, 0 ); - WR16( devAddr, SCU_RAM_AGC_CLP_DIR_WD__A, 0 ); - WR16( devAddr, SCU_RAM_AGC_CLP_DIR_STP__A, 1 ); - WR16( devAddr, SCU_RAM_AGC_SNS_SUM__A, 0 ); - WR16( devAddr, SCU_RAM_AGC_SNS_CYCCNT__A, 0 ); - WR16( devAddr, SCU_RAM_AGC_SNS_DIR_WD__A, 0 ); - WR16( devAddr, SCU_RAM_AGC_SNS_DIR_STP__A, 1 ); - pAgcIfSettings = &(extAttr->qamIfAgcCfg); - pAgcRfSettings = &(extAttr->qamRfAgcCfg); - WR16( devAddr, SCU_RAM_AGC_INGAIN_TGT__A, pAgcIfSettings->top ); - - RR16( devAddr, SCU_RAM_AGC_KI__A, &agcKi ); - agcKi &= 0xf000; - WR16( devAddr, SCU_RAM_AGC_KI__A, agcKi ); - break; + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_C: + case DRX_STANDARD_ITU_B: + IngainTgtMax = 5119; + clpSumMax = 1023; + clpDirTo = (u16_t) (-5); + snsSumMax = 127; + snsDirTo = (u16_t) (-3); + kiInnergainMin = 0; + kiMax = 0x0657; + ifIaccuHiTgtMin = 2047; + agcKiDgain = 0x7; + kiMin = 0x0117; + clpCtrlMode = 0; + WR16(devAddr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff); + WR16(devAddr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0); + WR16(devAddr, SCU_RAM_AGC_CLP_SUM__A, 0); + WR16(devAddr, SCU_RAM_AGC_CLP_CYCCNT__A, 0); + WR16(devAddr, SCU_RAM_AGC_CLP_DIR_WD__A, 0); + WR16(devAddr, SCU_RAM_AGC_CLP_DIR_STP__A, 1); + WR16(devAddr, SCU_RAM_AGC_SNS_SUM__A, 0); + WR16(devAddr, SCU_RAM_AGC_SNS_CYCCNT__A, 0); + WR16(devAddr, SCU_RAM_AGC_SNS_DIR_WD__A, 0); + WR16(devAddr, SCU_RAM_AGC_SNS_DIR_STP__A, 1); + pAgcIfSettings = &(extAttr->qamIfAgcCfg); + pAgcRfSettings = &(extAttr->qamRfAgcCfg); + WR16(devAddr, SCU_RAM_AGC_INGAIN_TGT__A, pAgcIfSettings->top); + + RR16(devAddr, SCU_RAM_AGC_KI__A, &agcKi); + agcKi &= 0xf000; + WR16(devAddr, SCU_RAM_AGC_KI__A, agcKi); + break; #endif #ifndef DRXJ_DIGITAL_ONLY - case DRX_STANDARD_FM: - clpSumMax = 1023; - snsSumMax = 1023; - kiInnergainMin = (u16_t)(-32768); - ifIaccuHiTgtMin = 2047; - agcKiDgain = 0x7; - kiMin = 0x0225; - kiMax = 0x0547; - clpDirTo = (u16_t)(-9); - snsDirTo = (u16_t)(-9); - IngainTgtMax = 9000; - clpCtrlMode = 1; - pAgcIfSettings = &(extAttr->atvIfAgcCfg); - pAgcRfSettings = &(extAttr->atvRfAgcCfg); - WR16( devAddr, SCU_RAM_AGC_INGAIN_TGT__A, pAgcIfSettings->top ); - break; - case DRX_STANDARD_NTSC: - case DRX_STANDARD_PAL_SECAM_BG: - case DRX_STANDARD_PAL_SECAM_DK: - case DRX_STANDARD_PAL_SECAM_I : - clpSumMax = 1023; - snsSumMax = 1023; - kiInnergainMin = (u16_t)(-32768); - ifIaccuHiTgtMin = 2047; - agcKiDgain = 0x7; - kiMin = 0x0225; - kiMax = 0x0547; - clpDirTo = (u16_t)(-9); - IngainTgtMax = 9000; - pAgcIfSettings = &(extAttr->atvIfAgcCfg); - pAgcRfSettings = &(extAttr->atvRfAgcCfg); - snsDirTo = (u16_t)(-9); - clpCtrlMode = 1; - WR16( devAddr, SCU_RAM_AGC_INGAIN_TGT__A, pAgcIfSettings->top ); - break; - case DRX_STANDARD_PAL_SECAM_L : - case DRX_STANDARD_PAL_SECAM_LP: - clpSumMax = 1023; - snsSumMax = 1023; - kiInnergainMin = (u16_t)(-32768); - ifIaccuHiTgtMin = 2047; - agcKiDgain = 0x7; - kiMin = 0x0225; - kiMax = 0x0547; - clpDirTo = (u16_t)(-9); - snsDirTo = (u16_t)(-9); - IngainTgtMax = 9000; - clpCtrlMode = 1; - pAgcIfSettings = &(extAttr->atvIfAgcCfg); - pAgcRfSettings = &(extAttr->atvRfAgcCfg); - WR16( devAddr, SCU_RAM_AGC_INGAIN_TGT__A, pAgcIfSettings->top ); - break; + case DRX_STANDARD_FM: + clpSumMax = 1023; + snsSumMax = 1023; + kiInnergainMin = (u16_t) (-32768); + ifIaccuHiTgtMin = 2047; + agcKiDgain = 0x7; + kiMin = 0x0225; + kiMax = 0x0547; + clpDirTo = (u16_t) (-9); + snsDirTo = (u16_t) (-9); + IngainTgtMax = 9000; + clpCtrlMode = 1; + pAgcIfSettings = &(extAttr->atvIfAgcCfg); + pAgcRfSettings = &(extAttr->atvRfAgcCfg); + WR16(devAddr, SCU_RAM_AGC_INGAIN_TGT__A, pAgcIfSettings->top); + break; + case DRX_STANDARD_NTSC: + case DRX_STANDARD_PAL_SECAM_BG: + case DRX_STANDARD_PAL_SECAM_DK: + case DRX_STANDARD_PAL_SECAM_I: + clpSumMax = 1023; + snsSumMax = 1023; + kiInnergainMin = (u16_t) (-32768); + ifIaccuHiTgtMin = 2047; + agcKiDgain = 0x7; + kiMin = 0x0225; + kiMax = 0x0547; + clpDirTo = (u16_t) (-9); + IngainTgtMax = 9000; + pAgcIfSettings = &(extAttr->atvIfAgcCfg); + pAgcRfSettings = &(extAttr->atvRfAgcCfg); + snsDirTo = (u16_t) (-9); + clpCtrlMode = 1; + WR16(devAddr, SCU_RAM_AGC_INGAIN_TGT__A, pAgcIfSettings->top); + break; + case DRX_STANDARD_PAL_SECAM_L: + case DRX_STANDARD_PAL_SECAM_LP: + clpSumMax = 1023; + snsSumMax = 1023; + kiInnergainMin = (u16_t) (-32768); + ifIaccuHiTgtMin = 2047; + agcKiDgain = 0x7; + kiMin = 0x0225; + kiMax = 0x0547; + clpDirTo = (u16_t) (-9); + snsDirTo = (u16_t) (-9); + IngainTgtMax = 9000; + clpCtrlMode = 1; + pAgcIfSettings = &(extAttr->atvIfAgcCfg); + pAgcRfSettings = &(extAttr->atvRfAgcCfg); + WR16(devAddr, SCU_RAM_AGC_INGAIN_TGT__A, pAgcIfSettings->top); + break; #endif - default: - return ( DRX_STS_INVALID_ARG ); - } - - /* for new AGC interface */ - WR16( devAddr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, pAgcIfSettings->top ); - WR16( devAddr, SCU_RAM_AGC_INGAIN__A, pAgcIfSettings->top ); /* Gain fed from inner to outer AGC */ - WR16( devAddr, SCU_RAM_AGC_INGAIN_TGT_MAX__A, IngainTgtMax ); - WR16( devAddr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, ifIaccuHiTgtMin ); - WR16( devAddr, SCU_RAM_AGC_IF_IACCU_HI__A, 0 ); /* set to pAgcSettings->top before */ - WR16( devAddr, SCU_RAM_AGC_IF_IACCU_LO__A, 0 ); - WR16( devAddr, SCU_RAM_AGC_RF_IACCU_HI__A, 0 ); - WR16( devAddr, SCU_RAM_AGC_RF_IACCU_LO__A, 0 ); - WR16( devAddr, SCU_RAM_AGC_RF_MAX__A, 32767 ); - WR16( devAddr, SCU_RAM_AGC_CLP_SUM_MAX__A, clpSumMax ); - WR16( devAddr, SCU_RAM_AGC_SNS_SUM_MAX__A, snsSumMax ); - WR16( devAddr, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, kiInnergainMin ); - WR16( devAddr, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50 ); - WR16( devAddr, SCU_RAM_AGC_KI_CYCLEN__A, 500 ); - WR16( devAddr, SCU_RAM_AGC_SNS_CYCLEN__A, 500 ); - WR16( devAddr, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20 ); - WR16( devAddr, SCU_RAM_AGC_KI_MIN__A, kiMin ); - WR16( devAddr, SCU_RAM_AGC_KI_MAX__A, kiMax ); - WR16( devAddr, SCU_RAM_AGC_KI_RED__A, 0 ); - WR16( devAddr, SCU_RAM_AGC_CLP_SUM_MIN__A, 8 ); - WR16( devAddr, SCU_RAM_AGC_CLP_CYCLEN__A, 500 ); - WR16( devAddr, SCU_RAM_AGC_CLP_DIR_TO__A, clpDirTo ); - WR16( devAddr, SCU_RAM_AGC_SNS_SUM_MIN__A, 8 ); - WR16( devAddr, SCU_RAM_AGC_SNS_DIR_TO__A, snsDirTo ); - WR16( devAddr, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, 50 ); - WR16( devAddr, SCU_RAM_AGC_CLP_CTRL_MODE__A, clpCtrlMode ); - - agcRf = 0x800 + pAgcRfSettings->cutOffCurrent; - if ( commonAttr->tunerRfAgcPol == TRUE ) - { - agcRf = 0x87ff - agcRf; - } + default: + return (DRX_STS_INVALID_ARG); + } - agcIf = 0x800; - if ( commonAttr->tunerIfAgcPol == TRUE ) - { - agcRf = 0x87ff - agcRf; - } + /* for new AGC interface */ + WR16(devAddr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, pAgcIfSettings->top); + WR16(devAddr, SCU_RAM_AGC_INGAIN__A, pAgcIfSettings->top); /* Gain fed from inner to outer AGC */ + WR16(devAddr, SCU_RAM_AGC_INGAIN_TGT_MAX__A, IngainTgtMax); + WR16(devAddr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, ifIaccuHiTgtMin); + WR16(devAddr, SCU_RAM_AGC_IF_IACCU_HI__A, 0); /* set to pAgcSettings->top before */ + WR16(devAddr, SCU_RAM_AGC_IF_IACCU_LO__A, 0); + WR16(devAddr, SCU_RAM_AGC_RF_IACCU_HI__A, 0); + WR16(devAddr, SCU_RAM_AGC_RF_IACCU_LO__A, 0); + WR16(devAddr, SCU_RAM_AGC_RF_MAX__A, 32767); + WR16(devAddr, SCU_RAM_AGC_CLP_SUM_MAX__A, clpSumMax); + WR16(devAddr, SCU_RAM_AGC_SNS_SUM_MAX__A, snsSumMax); + WR16(devAddr, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, kiInnergainMin); + WR16(devAddr, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50); + WR16(devAddr, SCU_RAM_AGC_KI_CYCLEN__A, 500); + WR16(devAddr, SCU_RAM_AGC_SNS_CYCLEN__A, 500); + WR16(devAddr, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20); + WR16(devAddr, SCU_RAM_AGC_KI_MIN__A, kiMin); + WR16(devAddr, SCU_RAM_AGC_KI_MAX__A, kiMax); + WR16(devAddr, SCU_RAM_AGC_KI_RED__A, 0); + WR16(devAddr, SCU_RAM_AGC_CLP_SUM_MIN__A, 8); + WR16(devAddr, SCU_RAM_AGC_CLP_CYCLEN__A, 500); + WR16(devAddr, SCU_RAM_AGC_CLP_DIR_TO__A, clpDirTo); + WR16(devAddr, SCU_RAM_AGC_SNS_SUM_MIN__A, 8); + WR16(devAddr, SCU_RAM_AGC_SNS_DIR_TO__A, snsDirTo); + WR16(devAddr, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, 50); + WR16(devAddr, SCU_RAM_AGC_CLP_CTRL_MODE__A, clpCtrlMode); + + agcRf = 0x800 + pAgcRfSettings->cutOffCurrent; + if (commonAttr->tunerRfAgcPol == TRUE) { + agcRf = 0x87ff - agcRf; + } + + agcIf = 0x800; + if (commonAttr->tunerIfAgcPol == TRUE) { + agcRf = 0x87ff - agcRf; + } - WR16( devAddr, IQM_AF_AGC_RF__A, agcRf ); - WR16( devAddr, IQM_AF_AGC_IF__A, agcIf ); + WR16(devAddr, IQM_AF_AGC_RF__A, agcRf); + WR16(devAddr, IQM_AF_AGC_IF__A, agcIf); - /* Set/restore Ki DGAIN factor */ - RR16( devAddr, SCU_RAM_AGC_KI__A, &data ); - data &= ~SCU_RAM_AGC_KI_DGAIN__M; - data |= ( agcKiDgain << SCU_RAM_AGC_KI_DGAIN__B ); - WR16( devAddr, SCU_RAM_AGC_KI__A, data ); + /* Set/restore Ki DGAIN factor */ + RR16(devAddr, SCU_RAM_AGC_KI__A, &data); + data &= ~SCU_RAM_AGC_KI_DGAIN__M; + data |= (agcKiDgain << SCU_RAM_AGC_KI_DGAIN__B); + WR16(devAddr, SCU_RAM_AGC_KI__A, data); - return (DRX_STS_OK); + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /** @@ -5037,99 +4757,97 @@ rw_error: * \return DRXStatus_t. */ static DRXStatus_t -SetFrequency ( pDRXDemodInstance_t demod, - pDRXChannel_t channel, - DRXFrequency_t tunerFreqOffset - ) -{ - pI2CDeviceAddr_t devAddr = NULL; - pDRXCommonAttr_t commonAttr = NULL; - DRXFrequency_t samplingFrequency = 0; - DRXFrequency_t frequencyShift = 0; - DRXFrequency_t ifFreqActual = 0; - DRXFrequency_t rfFreqResidual = 0; - DRXFrequency_t adcFreq = 0; - DRXFrequency_t intermediateFreq = 0; - u32_t iqmFsRateOfs = 0; - pDRXJData_t extAttr = NULL; - Bool_t adcFlip = TRUE; - Bool_t selectPosImage = FALSE; - Bool_t rfMirror = FALSE; - Bool_t tunerMirror = TRUE; - Bool_t imageToSelect = TRUE; - DRXFrequency_t fmFrequencyShift = 0; - - devAddr = demod -> myI2CDevAddr; - commonAttr = (pDRXCommonAttr_t) demod -> myCommonAttr; - extAttr = (pDRXJData_t)demod->myExtAttr; - rfFreqResidual = -1 * tunerFreqOffset; - rfMirror = (extAttr->mirror == DRX_MIRROR_YES)?TRUE:FALSE; - tunerMirror = demod->myCommonAttr->mirrorFreqSpect?FALSE:TRUE; - /* - Program frequency shifter - No need to account for mirroring on RF - */ - switch (extAttr->standard) - { - case DRX_STANDARD_ITU_A: /* fallthrough */ - case DRX_STANDARD_ITU_C: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_LP: /* fallthrough */ - case DRX_STANDARD_8VSB: - selectPosImage = TRUE; - break; - case DRX_STANDARD_FM: - /* After IQM FS sound carrier must appear at 4 Mhz in spect. - Sound carrier is already 3Mhz above centre frequency due - to tuner setting so now add an extra shift of 1MHz... */ - fmFrequencyShift = 1000; - case DRX_STANDARD_ITU_B: /* fallthrough */ - case DRX_STANDARD_NTSC: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_L: - selectPosImage = FALSE; - break; - default: - return ( DRX_STS_INVALID_ARG ); - } - intermediateFreq = demod->myCommonAttr->intermediateFreq; - samplingFrequency = demod->myCommonAttr->sysClockFreq/3; - if ( tunerMirror == TRUE ) - { - /* tuner doesn't mirror */ - ifFreqActual = intermediateFreq + rfFreqResidual + fmFrequencyShift; - } else { - /* tuner mirrors */ - ifFreqActual = intermediateFreq - rfFreqResidual - fmFrequencyShift; - } - if ( ifFreqActual > samplingFrequency / 2) - { - /* adc mirrors */ - adcFreq = samplingFrequency - ifFreqActual; - adcFlip = TRUE; - } else { - /* adc doesn't mirror */ - adcFreq = ifFreqActual; - adcFlip = FALSE; - } - - frequencyShift = adcFreq; - imageToSelect = (Bool_t)(rfMirror ^ tunerMirror ^ adcFlip ^ selectPosImage); - iqmFsRateOfs = Frac28(frequencyShift,samplingFrequency); - - if (imageToSelect) - iqmFsRateOfs = ~iqmFsRateOfs + 1; - - /* Program frequency shifter with tuner offset compensation */ - /* frequencyShift += tunerFreqOffset; TODO */ - WR32( devAddr, IQM_FS_RATE_OFS_LO__A , iqmFsRateOfs ); - extAttr->iqmFsRateOfs = iqmFsRateOfs; - extAttr->posImage = (Bool_t)(rfMirror ^ tunerMirror ^ selectPosImage); - - return (DRX_STS_OK); +SetFrequency(pDRXDemodInstance_t demod, + pDRXChannel_t channel, DRXFrequency_t tunerFreqOffset) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXCommonAttr_t commonAttr = NULL; + DRXFrequency_t samplingFrequency = 0; + DRXFrequency_t frequencyShift = 0; + DRXFrequency_t ifFreqActual = 0; + DRXFrequency_t rfFreqResidual = 0; + DRXFrequency_t adcFreq = 0; + DRXFrequency_t intermediateFreq = 0; + u32_t iqmFsRateOfs = 0; + pDRXJData_t extAttr = NULL; + Bool_t adcFlip = TRUE; + Bool_t selectPosImage = FALSE; + Bool_t rfMirror = FALSE; + Bool_t tunerMirror = TRUE; + Bool_t imageToSelect = TRUE; + DRXFrequency_t fmFrequencyShift = 0; + + devAddr = demod->myI2CDevAddr; + commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; + extAttr = (pDRXJData_t) demod->myExtAttr; + rfFreqResidual = -1 * tunerFreqOffset; + rfMirror = (extAttr->mirror == DRX_MIRROR_YES) ? TRUE : FALSE; + tunerMirror = demod->myCommonAttr->mirrorFreqSpect ? FALSE : TRUE; + /* + Program frequency shifter + No need to account for mirroring on RF + */ + switch (extAttr->standard) { + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_C: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_LP: /* fallthrough */ + case DRX_STANDARD_8VSB: + selectPosImage = TRUE; + break; + case DRX_STANDARD_FM: + /* After IQM FS sound carrier must appear at 4 Mhz in spect. + Sound carrier is already 3Mhz above centre frequency due + to tuner setting so now add an extra shift of 1MHz... */ + fmFrequencyShift = 1000; + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_NTSC: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_L: + selectPosImage = FALSE; + break; + default: + return (DRX_STS_INVALID_ARG); + } + intermediateFreq = demod->myCommonAttr->intermediateFreq; + samplingFrequency = demod->myCommonAttr->sysClockFreq / 3; + if (tunerMirror == TRUE) { + /* tuner doesn't mirror */ + ifFreqActual = + intermediateFreq + rfFreqResidual + fmFrequencyShift; + } else { + /* tuner mirrors */ + ifFreqActual = + intermediateFreq - rfFreqResidual - fmFrequencyShift; + } + if (ifFreqActual > samplingFrequency / 2) { + /* adc mirrors */ + adcFreq = samplingFrequency - ifFreqActual; + adcFlip = TRUE; + } else { + /* adc doesn't mirror */ + adcFreq = ifFreqActual; + adcFlip = FALSE; + } + + frequencyShift = adcFreq; + imageToSelect = + (Bool_t) (rfMirror ^ tunerMirror ^ adcFlip ^ selectPosImage); + iqmFsRateOfs = Frac28(frequencyShift, samplingFrequency); + + if (imageToSelect) + iqmFsRateOfs = ~iqmFsRateOfs + 1; + + /* Program frequency shifter with tuner offset compensation */ + /* frequencyShift += tunerFreqOffset; TODO */ + WR32(devAddr, IQM_FS_RATE_OFS_LO__A, iqmFsRateOfs); + extAttr->iqmFsRateOfs = iqmFsRateOfs; + extAttr->posImage = (Bool_t) (rfMirror ^ tunerMirror ^ selectPosImage); + + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /** @@ -5147,58 +4865,52 @@ rw_error: #define DRXJ_RFAGC_MAX 0x3fff #define DRXJ_RFAGC_MIN 0x800 -static DRXStatus_t -GetSigStrength( pDRXDemodInstance_t demod, - pu16_t sigStrength ) -{ - u16_t rfGain = 0; - u16_t ifGain = 0; - u16_t ifAgcSns = 0; - u16_t ifAgcTop = 0; - u16_t rfAgcMax = 0; - u16_t rfAgcMin = 0; - pDRXJData_t extAttr = NULL; - pI2CDeviceAddr_t devAddr = NULL; - - extAttr = (pDRXJData_t)demod->myExtAttr; - devAddr = demod -> myI2CDevAddr; - - RR16( devAddr, IQM_AF_AGC_IF__A, &ifGain ); - ifGain &= IQM_AF_AGC_IF__M; - RR16( devAddr, IQM_AF_AGC_RF__A, &rfGain ); - rfGain &= IQM_AF_AGC_RF__M; - - ifAgcSns = DRXJ_AGC_SNS; - ifAgcTop = DRXJ_AGC_TOP; - rfAgcMax = DRXJ_RFAGC_MAX; - rfAgcMin = DRXJ_RFAGC_MIN; - - if (ifGain > ifAgcTop) - { - if (rfGain > rfAgcMax) - *sigStrength = 100; - else if (rfGain > rfAgcMin) - { - CHK_ZERO (rfAgcMax - rfAgcMin); - *sigStrength = 75 + 25 * (rfGain - rfAgcMin) / (rfAgcMax - rfAgcMin); - } - else - *sigStrength = 75; - } - else if (ifGain > ifAgcSns) - { - CHK_ZERO(ifAgcTop - ifAgcSns); - *sigStrength = 20 + 55* (ifGain - ifAgcSns)/ (ifAgcTop - ifAgcSns); - } - else - { - CHK_ZERO (ifAgcSns); - *sigStrength = (20 * ifGain / ifAgcSns); - } +static DRXStatus_t GetSigStrength(pDRXDemodInstance_t demod, pu16_t sigStrength) +{ + u16_t rfGain = 0; + u16_t ifGain = 0; + u16_t ifAgcSns = 0; + u16_t ifAgcTop = 0; + u16_t rfAgcMax = 0; + u16_t rfAgcMin = 0; + pDRXJData_t extAttr = NULL; + pI2CDeviceAddr_t devAddr = NULL; + + extAttr = (pDRXJData_t) demod->myExtAttr; + devAddr = demod->myI2CDevAddr; + + RR16(devAddr, IQM_AF_AGC_IF__A, &ifGain); + ifGain &= IQM_AF_AGC_IF__M; + RR16(devAddr, IQM_AF_AGC_RF__A, &rfGain); + rfGain &= IQM_AF_AGC_RF__M; + + ifAgcSns = DRXJ_AGC_SNS; + ifAgcTop = DRXJ_AGC_TOP; + rfAgcMax = DRXJ_RFAGC_MAX; + rfAgcMin = DRXJ_RFAGC_MIN; + + if (ifGain > ifAgcTop) { + if (rfGain > rfAgcMax) + *sigStrength = 100; + else if (rfGain > rfAgcMin) { + CHK_ZERO(rfAgcMax - rfAgcMin); + *sigStrength = + 75 + 25 * (rfGain - rfAgcMin) / (rfAgcMax - + rfAgcMin); + } else + *sigStrength = 75; + } else if (ifGain > ifAgcSns) { + CHK_ZERO(ifAgcTop - ifAgcSns); + *sigStrength = + 20 + 55 * (ifGain - ifAgcSns) / (ifAgcTop - ifAgcSns); + } else { + CHK_ZERO(ifAgcSns); + *sigStrength = (20 * ifGain / ifAgcSns); + } - return (DRX_STS_OK); + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /** @@ -5212,42 +4924,36 @@ rw_error: * \retval DRX_STS_ERROR Erroneous data, sigStrength contains invalid data. */ #ifdef DRXJ_SIGNAL_ACCUM_ERR -static DRXStatus_t -GetAccPktErr( pDRXDemodInstance_t demod, - pu16_t packetErr ) -{ - static u16_t pktErr = 0; - static u16_t lastPktErr = 0; - u16_t data = 0; - pDRXJData_t extAttr = NULL; - pI2CDeviceAddr_t devAddr = NULL; - - extAttr = (pDRXJData_t)demod->myExtAttr; - devAddr = demod -> myI2CDevAddr; - - RR16( devAddr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, &data ); - if ( extAttr->resetPktErrAcc == TRUE ) - { - lastPktErr = data; - pktErr = 0; - extAttr->resetPktErrAcc = FALSE; - } +static DRXStatus_t GetAccPktErr(pDRXDemodInstance_t demod, pu16_t packetErr) +{ + static u16_t pktErr = 0; + static u16_t lastPktErr = 0; + u16_t data = 0; + pDRXJData_t extAttr = NULL; + pI2CDeviceAddr_t devAddr = NULL; + + extAttr = (pDRXJData_t) demod->myExtAttr; + devAddr = demod->myI2CDevAddr; + + RR16(devAddr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, &data); + if (extAttr->resetPktErrAcc == TRUE) { + lastPktErr = data; + pktErr = 0; + extAttr->resetPktErrAcc = FALSE; + } - if (data < lastPktErr) - { - pktErr += 0xffff - lastPktErr; - pktErr += data; - } - else - { - pktErr += (data - lastPktErr); - } - *packetErr = pktErr; - lastPktErr = data; + if (data < lastPktErr) { + pktErr += 0xffff - lastPktErr; + pktErr += data; + } else { + pktErr += (data - lastPktErr); + } + *packetErr = pktErr; + lastPktErr = data; - return (DRX_STS_OK); + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } #endif @@ -5259,22 +4965,21 @@ rw_error: * \retval DRX_STS_OK. * \retval DRX_STS_ERROR Erroneous data. */ -static DRXStatus_t -CtrlSetCfgResetPktErr( pDRXDemodInstance_t demod ) +static DRXStatus_t CtrlSetCfgResetPktErr(pDRXDemodInstance_t demod) { #ifdef DRXJ_SIGNAL_ACCUM_ERR - pDRXJData_t extAttr = NULL; - u16_t packetError = 0; + pDRXJData_t extAttr = NULL; + u16_t packetError = 0; - extAttr = (pDRXJData_t)demod->myExtAttr; - extAttr->resetPktErrAcc = TRUE; - /* call to reset counter */ - CHK_ERROR (GetAccPktErr (demod, &packetError)); + extAttr = (pDRXJData_t) demod->myExtAttr; + extAttr->resetPktErrAcc = TRUE; + /* call to reset counter */ + CHK_ERROR(GetAccPktErr(demod, &packetError)); - return (DRX_STS_OK); + return (DRX_STS_OK); rw_error: #endif - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /** @@ -5282,33 +4987,37 @@ rw_error: * \brief Get symbol rate offset in QAM & 8VSB mode * \return Error code */ -static DRXStatus_t -GetSTRFreqOffset( pDRXDemodInstance_t demod, - s32_t *STRFreq - ) +static DRXStatus_t GetSTRFreqOffset(pDRXDemodInstance_t demod, s32_t * STRFreq) { - u32_t symbolFrequencyRatio = 0; - u32_t symbolNomFrequencyRatio = 0; + u32_t symbolFrequencyRatio = 0; + u32_t symbolNomFrequencyRatio = 0; - DRXStandard_t standard = DRX_STANDARD_UNKNOWN; - pI2CDeviceAddr_t devAddr = NULL; - pDRXJData_t extAttr = NULL; + DRXStandard_t standard = DRX_STANDARD_UNKNOWN; + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; - devAddr = demod -> myI2CDevAddr; - extAttr = (pDRXJData_t)demod->myExtAttr; - standard = extAttr->standard; + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; + standard = extAttr->standard; - ARR32( devAddr, IQM_RC_RATE_LO__A, &symbolFrequencyRatio ); - symbolNomFrequencyRatio = extAttr->iqmRcRateOfs; + ARR32(devAddr, IQM_RC_RATE_LO__A, &symbolFrequencyRatio); + symbolNomFrequencyRatio = extAttr->iqmRcRateOfs; - if ( symbolFrequencyRatio > symbolNomFrequencyRatio ) - *STRFreq = -1 * FracTimes1e6( ( symbolFrequencyRatio - symbolNomFrequencyRatio ), (symbolFrequencyRatio + (1 << 23)) ); - else - *STRFreq = FracTimes1e6( ( symbolNomFrequencyRatio - symbolFrequencyRatio ), (symbolFrequencyRatio + (1 << 23)) ); + if (symbolFrequencyRatio > symbolNomFrequencyRatio) + *STRFreq = + -1 * + FracTimes1e6((symbolFrequencyRatio - + symbolNomFrequencyRatio), + (symbolFrequencyRatio + (1 << 23))); + else + *STRFreq = + FracTimes1e6((symbolNomFrequencyRatio - + symbolFrequencyRatio), + (symbolFrequencyRatio + (1 << 23))); - return (DRX_STS_OK); + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /** @@ -5316,55 +5025,51 @@ rw_error: * \brief Get the value of CTLFreq in QAM & ATSC mode * \return Error code */ -static DRXStatus_t -GetCTLFreqOffset ( pDRXDemodInstance_t demod, - s32_t *CTLFreq - ) -{ - DRXFrequency_t samplingFrequency = 0; - s32_t currentFrequency = 0; - s32_t nominalFrequency = 0; - s32_t carrierFrequencyShift = 0; - s32_t sign = 1; - u32_t data64Hi = 0; - u32_t data64Lo = 0; - pDRXJData_t extAttr = NULL; - pDRXCommonAttr_t commonAttr = NULL; - pI2CDeviceAddr_t devAddr = NULL; - - devAddr = demod -> myI2CDevAddr; - extAttr = (pDRXJData_t)demod->myExtAttr; - commonAttr = (pDRXCommonAttr_t) demod -> myCommonAttr; - - samplingFrequency = commonAttr->sysClockFreq/3; - - /* both registers are sign extended */ - nominalFrequency = extAttr->iqmFsRateOfs; - ARR32( devAddr, IQM_FS_RATE_LO__A, (pu32_t) ¤tFrequency ); - - if ( extAttr->posImage == TRUE ) - { - /* negative image */ - carrierFrequencyShift = nominalFrequency - currentFrequency; - } else { - /* positive image */ - carrierFrequencyShift = currentFrequency - nominalFrequency; - } - - /* carrier Frequency Shift In Hz */ - if (carrierFrequencyShift < 0) - { - sign = -1; - carrierFrequencyShift *= sign; - } +static DRXStatus_t GetCTLFreqOffset(pDRXDemodInstance_t demod, s32_t * CTLFreq) +{ + DRXFrequency_t samplingFrequency = 0; + s32_t currentFrequency = 0; + s32_t nominalFrequency = 0; + s32_t carrierFrequencyShift = 0; + s32_t sign = 1; + u32_t data64Hi = 0; + u32_t data64Lo = 0; + pDRXJData_t extAttr = NULL; + pDRXCommonAttr_t commonAttr = NULL; + pI2CDeviceAddr_t devAddr = NULL; + + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; + commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; + + samplingFrequency = commonAttr->sysClockFreq / 3; + + /* both registers are sign extended */ + nominalFrequency = extAttr->iqmFsRateOfs; + ARR32(devAddr, IQM_FS_RATE_LO__A, (pu32_t) & currentFrequency); + + if (extAttr->posImage == TRUE) { + /* negative image */ + carrierFrequencyShift = nominalFrequency - currentFrequency; + } else { + /* positive image */ + carrierFrequencyShift = currentFrequency - nominalFrequency; + } + + /* carrier Frequency Shift In Hz */ + if (carrierFrequencyShift < 0) { + sign = -1; + carrierFrequencyShift *= sign; + } - /* *CTLFreq = carrierFrequencyShift * 50.625e6 / (1 << 28); */ - Mult32 ( carrierFrequencyShift, samplingFrequency, &data64Hi, &data64Lo ); - *CTLFreq = (s32_t)((((data64Lo >> 28) & 0xf) | (data64Hi << 4)) * sign); + /* *CTLFreq = carrierFrequencyShift * 50.625e6 / (1 << 28); */ + Mult32(carrierFrequencyShift, samplingFrequency, &data64Hi, &data64Lo); + *CTLFreq = + (s32_t) ((((data64Lo >> 28) & 0xf) | (data64Hi << 4)) * sign); - return (DRX_STS_OK); + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /*============================================================================*/ @@ -5377,174 +5082,174 @@ rw_error: * \return DRXStatus_t. */ static DRXStatus_t -SetAgcRf ( pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings, Bool_t atomic ) +SetAgcRf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings, Bool_t atomic) { - pI2CDeviceAddr_t devAddr = NULL; - pDRXJData_t extAttr = NULL; - pDRXJCfgAgc_t pAgcSettings = NULL; - pDRXCommonAttr_t commonAttr = NULL; - DRXWriteReg16Func_t ScuWr16 = NULL; - DRXReadReg16Func_t ScuRr16 = NULL; - - commonAttr = (pDRXCommonAttr_t) demod -> myCommonAttr; - devAddr = demod -> myI2CDevAddr; - extAttr = (pDRXJData_t)demod->myExtAttr; - - if (atomic) - { - ScuRr16 = DRXJ_DAP_SCU_AtomicReadReg16; - ScuWr16 = DRXJ_DAP_SCU_AtomicWriteReg16; - } - else - { - ScuRr16 = DRXJ_DAP.readReg16Func; - ScuWr16 = DRXJ_DAP.writeReg16Func; - } - - /* Configure AGC only if standard is currently active*/ - if ( ( extAttr->standard == agcSettings->standard ) || - ( DRXJ_ISQAMSTD( extAttr->standard ) && - DRXJ_ISQAMSTD( agcSettings->standard ) ) || - ( DRXJ_ISATVSTD( extAttr->standard ) && - DRXJ_ISATVSTD( agcSettings->standard ) ) ) - { - u16_t data = 0; - - switch ( agcSettings->ctrlMode ) - { - case DRX_AGC_CTRL_AUTO: - - /* Enable RF AGC DAC */ - RR16( devAddr, IQM_AF_STDBY__A , &data ); - data |= IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE; - WR16( devAddr, IQM_AF_STDBY__A, data ); - - /* Enable SCU RF AGC loop */ - CHK_ERROR((*ScuRr16)( devAddr, SCU_RAM_AGC_KI__A, &data, 0 )); - data &= ~SCU_RAM_AGC_KI_RF__M; - if ( extAttr->standard == DRX_STANDARD_8VSB ) - { - data |= ( 2 << SCU_RAM_AGC_KI_RF__B ); - } - else if (DRXJ_ISQAMSTD( extAttr->standard )) - { - data |= ( 5 << SCU_RAM_AGC_KI_RF__B ); - } - else - { - data |= ( 4 << SCU_RAM_AGC_KI_RF__B ); - } - - if (commonAttr->tunerRfAgcPol) - { - data |= SCU_RAM_AGC_KI_INV_RF_POL__M; - } - else - { - data &= ~SCU_RAM_AGC_KI_INV_RF_POL__M; - } - CHK_ERROR((*ScuWr16)( devAddr, SCU_RAM_AGC_KI__A, data, 0 )); - - /* Set speed ( using complementary reduction value ) */ - CHK_ERROR((*ScuRr16)( devAddr, SCU_RAM_AGC_KI_RED__A , &data, 0 )); - data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M; - CHK_ERROR((*ScuWr16)( devAddr, SCU_RAM_AGC_KI_RED__A , - (~(agcSettings->speed << SCU_RAM_AGC_KI_RED_RAGC_RED__B) - & SCU_RAM_AGC_KI_RED_RAGC_RED__M ) - | data, 0 )); - - if (agcSettings->standard == DRX_STANDARD_8VSB) - pAgcSettings = &(extAttr->vsbIfAgcCfg); - else if (DRXJ_ISQAMSTD( agcSettings->standard )) - pAgcSettings = &(extAttr->qamIfAgcCfg); - else if (DRXJ_ISATVSTD( agcSettings->standard )) - pAgcSettings = &(extAttr->atvIfAgcCfg); - else - return (DRX_STS_INVALID_ARG); - - /* Set TOP, only if IF-AGC is in AUTO mode */ - if ( pAgcSettings->ctrlMode == DRX_AGC_CTRL_AUTO) - { - CHK_ERROR((*ScuWr16)( devAddr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, - agcSettings->top, 0 )); - CHK_ERROR((*ScuWr16)( devAddr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, - agcSettings->top, 0 )); - } - - /* Cut-Off current */ - CHK_ERROR((*ScuWr16)( devAddr, SCU_RAM_AGC_RF_IACCU_HI_CO__A, - agcSettings->cutOffCurrent, 0 )); - break; - case DRX_AGC_CTRL_USER: - - /* Enable RF AGC DAC */ - RR16( devAddr, IQM_AF_STDBY__A , &data ); - data |= IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE; - WR16( devAddr, IQM_AF_STDBY__A , data ); - - /* Disable SCU RF AGC loop */ - CHK_ERROR((*ScuRr16)( devAddr, SCU_RAM_AGC_KI__A, &data, 0 )); - data &= ~SCU_RAM_AGC_KI_RF__M; - if (commonAttr->tunerRfAgcPol) - { - data |= SCU_RAM_AGC_KI_INV_RF_POL__M; - } - else - { - data &= ~SCU_RAM_AGC_KI_INV_RF_POL__M; - } - CHK_ERROR((*ScuWr16)( devAddr, SCU_RAM_AGC_KI__A, data, 0 )); - - /* Write value to output pin */ - CHK_ERROR((*ScuWr16)( devAddr, SCU_RAM_AGC_RF_IACCU_HI__A, agcSettings->outputLevel, 0 )); - break; - case DRX_AGC_CTRL_OFF: - - /* Disable RF AGC DAC */ - RR16( devAddr, IQM_AF_STDBY__A , &data ); - data &= (~IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE); - WR16( devAddr, IQM_AF_STDBY__A , data ); - - /* Disable SCU RF AGC loop */ - CHK_ERROR((*ScuRr16)( devAddr, SCU_RAM_AGC_KI__A, &data, 0 )); - data &= ~SCU_RAM_AGC_KI_RF__M; - CHK_ERROR((*ScuWr16)( devAddr, SCU_RAM_AGC_KI__A, data, 0 )); - break; - default: - return (DRX_STS_INVALID_ARG); - } /* switch ( agcsettings->ctrlMode ) */ - } - - /* Store rf agc settings */ - switch ( agcSettings->standard){ - case DRX_STANDARD_8VSB: - extAttr->vsbRfAgcCfg = *agcSettings; - break; + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + pDRXJCfgAgc_t pAgcSettings = NULL; + pDRXCommonAttr_t commonAttr = NULL; + DRXWriteReg16Func_t ScuWr16 = NULL; + DRXReadReg16Func_t ScuRr16 = NULL; + + commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; + + if (atomic) { + ScuRr16 = DRXJ_DAP_SCU_AtomicReadReg16; + ScuWr16 = DRXJ_DAP_SCU_AtomicWriteReg16; + } else { + ScuRr16 = DRXJ_DAP.readReg16Func; + ScuWr16 = DRXJ_DAP.writeReg16Func; + } + + /* Configure AGC only if standard is currently active */ + if ((extAttr->standard == agcSettings->standard) || + (DRXJ_ISQAMSTD(extAttr->standard) && + DRXJ_ISQAMSTD(agcSettings->standard)) || + (DRXJ_ISATVSTD(extAttr->standard) && + DRXJ_ISATVSTD(agcSettings->standard))) { + u16_t data = 0; + + switch (agcSettings->ctrlMode) { + case DRX_AGC_CTRL_AUTO: + + /* Enable RF AGC DAC */ + RR16(devAddr, IQM_AF_STDBY__A, &data); + data |= IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE; + WR16(devAddr, IQM_AF_STDBY__A, data); + + /* Enable SCU RF AGC loop */ + CHK_ERROR((*ScuRr16) + (devAddr, SCU_RAM_AGC_KI__A, &data, 0)); + data &= ~SCU_RAM_AGC_KI_RF__M; + if (extAttr->standard == DRX_STANDARD_8VSB) { + data |= (2 << SCU_RAM_AGC_KI_RF__B); + } else if (DRXJ_ISQAMSTD(extAttr->standard)) { + data |= (5 << SCU_RAM_AGC_KI_RF__B); + } else { + data |= (4 << SCU_RAM_AGC_KI_RF__B); + } + + if (commonAttr->tunerRfAgcPol) { + data |= SCU_RAM_AGC_KI_INV_RF_POL__M; + } else { + data &= ~SCU_RAM_AGC_KI_INV_RF_POL__M; + } + CHK_ERROR((*ScuWr16) + (devAddr, SCU_RAM_AGC_KI__A, data, 0)); + + /* Set speed ( using complementary reduction value ) */ + CHK_ERROR((*ScuRr16) + (devAddr, SCU_RAM_AGC_KI_RED__A, &data, 0)); + data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M; + CHK_ERROR((*ScuWr16) (devAddr, SCU_RAM_AGC_KI_RED__A, + (~ + (agcSettings-> + speed << + SCU_RAM_AGC_KI_RED_RAGC_RED__B) +& SCU_RAM_AGC_KI_RED_RAGC_RED__M) + | data, 0)); + + if (agcSettings->standard == DRX_STANDARD_8VSB) + pAgcSettings = &(extAttr->vsbIfAgcCfg); + else if (DRXJ_ISQAMSTD(agcSettings->standard)) + pAgcSettings = &(extAttr->qamIfAgcCfg); + else if (DRXJ_ISATVSTD(agcSettings->standard)) + pAgcSettings = &(extAttr->atvIfAgcCfg); + else + return (DRX_STS_INVALID_ARG); + + /* Set TOP, only if IF-AGC is in AUTO mode */ + if (pAgcSettings->ctrlMode == DRX_AGC_CTRL_AUTO) { + CHK_ERROR((*ScuWr16) + (devAddr, + SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, + agcSettings->top, 0)); + CHK_ERROR((*ScuWr16) + (devAddr, + SCU_RAM_AGC_IF_IACCU_HI_TGT__A, + agcSettings->top, 0)); + } + + /* Cut-Off current */ + CHK_ERROR((*ScuWr16) + (devAddr, SCU_RAM_AGC_RF_IACCU_HI_CO__A, + agcSettings->cutOffCurrent, 0)); + break; + case DRX_AGC_CTRL_USER: + + /* Enable RF AGC DAC */ + RR16(devAddr, IQM_AF_STDBY__A, &data); + data |= IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE; + WR16(devAddr, IQM_AF_STDBY__A, data); + + /* Disable SCU RF AGC loop */ + CHK_ERROR((*ScuRr16) + (devAddr, SCU_RAM_AGC_KI__A, &data, 0)); + data &= ~SCU_RAM_AGC_KI_RF__M; + if (commonAttr->tunerRfAgcPol) { + data |= SCU_RAM_AGC_KI_INV_RF_POL__M; + } else { + data &= ~SCU_RAM_AGC_KI_INV_RF_POL__M; + } + CHK_ERROR((*ScuWr16) + (devAddr, SCU_RAM_AGC_KI__A, data, 0)); + + /* Write value to output pin */ + CHK_ERROR((*ScuWr16) + (devAddr, SCU_RAM_AGC_RF_IACCU_HI__A, + agcSettings->outputLevel, 0)); + break; + case DRX_AGC_CTRL_OFF: + + /* Disable RF AGC DAC */ + RR16(devAddr, IQM_AF_STDBY__A, &data); + data &= (~IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE); + WR16(devAddr, IQM_AF_STDBY__A, data); + + /* Disable SCU RF AGC loop */ + CHK_ERROR((*ScuRr16) + (devAddr, SCU_RAM_AGC_KI__A, &data, 0)); + data &= ~SCU_RAM_AGC_KI_RF__M; + CHK_ERROR((*ScuWr16) + (devAddr, SCU_RAM_AGC_KI__A, data, 0)); + break; + default: + return (DRX_STS_INVALID_ARG); + } /* switch ( agcsettings->ctrlMode ) */ + } + + /* Store rf agc settings */ + switch (agcSettings->standard) { + case DRX_STANDARD_8VSB: + extAttr->vsbRfAgcCfg = *agcSettings; + break; #ifndef DRXJ_VSB_ONLY - case DRX_STANDARD_ITU_A: - case DRX_STANDARD_ITU_B: - case DRX_STANDARD_ITU_C: - extAttr->qamRfAgcCfg = *agcSettings; - break; + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: + extAttr->qamRfAgcCfg = *agcSettings; + break; #endif #ifndef DRXJ_DIGITAL_ONLY - case DRX_STANDARD_PAL_SECAM_BG: - case DRX_STANDARD_PAL_SECAM_DK: - case DRX_STANDARD_PAL_SECAM_I: - case DRX_STANDARD_PAL_SECAM_L: - case DRX_STANDARD_PAL_SECAM_LP: - case DRX_STANDARD_NTSC: - case DRX_STANDARD_FM: - extAttr->atvRfAgcCfg = *agcSettings; - break; + case DRX_STANDARD_PAL_SECAM_BG: + case DRX_STANDARD_PAL_SECAM_DK: + case DRX_STANDARD_PAL_SECAM_I: + case DRX_STANDARD_PAL_SECAM_L: + case DRX_STANDARD_PAL_SECAM_LP: + case DRX_STANDARD_NTSC: + case DRX_STANDARD_FM: + extAttr->atvRfAgcCfg = *agcSettings; + break; #endif - default: - return (DRX_STS_ERROR); - } + default: + return (DRX_STS_ERROR); + } - return (DRX_STS_OK); + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /** @@ -5555,58 +5260,57 @@ rw_error: * \return DRXStatus_t. */ static DRXStatus_t -GetAgcRf ( pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings ) +GetAgcRf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings) { - pI2CDeviceAddr_t devAddr = NULL; - pDRXJData_t extAttr = NULL; - DRXStandard_t standard = DRX_STANDARD_UNKNOWN; - - devAddr = demod -> myI2CDevAddr; - extAttr = (pDRXJData_t)demod->myExtAttr; - - /* Return stored AGC settings */ - standard = agcSettings->standard; - switch ( agcSettings->standard){ - case DRX_STANDARD_8VSB: - *agcSettings = extAttr->vsbRfAgcCfg; - break; + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + DRXStandard_t standard = DRX_STANDARD_UNKNOWN; + + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; + + /* Return stored AGC settings */ + standard = agcSettings->standard; + switch (agcSettings->standard) { + case DRX_STANDARD_8VSB: + *agcSettings = extAttr->vsbRfAgcCfg; + break; #ifndef DRXJ_VSB_ONLY - case DRX_STANDARD_ITU_A: - case DRX_STANDARD_ITU_B: - case DRX_STANDARD_ITU_C: - *agcSettings = extAttr->qamRfAgcCfg; - break; + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: + *agcSettings = extAttr->qamRfAgcCfg; + break; #endif #ifndef DRXJ_DIGITAL_ONLY - case DRX_STANDARD_PAL_SECAM_BG: - case DRX_STANDARD_PAL_SECAM_DK: - case DRX_STANDARD_PAL_SECAM_I: - case DRX_STANDARD_PAL_SECAM_L: - case DRX_STANDARD_PAL_SECAM_LP: - case DRX_STANDARD_NTSC: - case DRX_STANDARD_FM: - *agcSettings = extAttr->atvRfAgcCfg; - break; + case DRX_STANDARD_PAL_SECAM_BG: + case DRX_STANDARD_PAL_SECAM_DK: + case DRX_STANDARD_PAL_SECAM_I: + case DRX_STANDARD_PAL_SECAM_L: + case DRX_STANDARD_PAL_SECAM_LP: + case DRX_STANDARD_NTSC: + case DRX_STANDARD_FM: + *agcSettings = extAttr->atvRfAgcCfg; + break; #endif - default: - return (DRX_STS_ERROR); - } - agcSettings->standard = standard; - - /* Get AGC output only if standard is currently active. */ - if ( ( extAttr->standard == agcSettings->standard ) || - ( DRXJ_ISQAMSTD( extAttr->standard ) && - DRXJ_ISQAMSTD( agcSettings->standard ) ) || - ( DRXJ_ISATVSTD( extAttr->standard ) && - DRXJ_ISATVSTD( agcSettings->standard ) ) ) - { - SARR16( devAddr, SCU_RAM_AGC_RF_IACCU_HI__A, - &(agcSettings->outputLevel)); - } + default: + return (DRX_STS_ERROR); + } + agcSettings->standard = standard; + + /* Get AGC output only if standard is currently active. */ + if ((extAttr->standard == agcSettings->standard) || + (DRXJ_ISQAMSTD(extAttr->standard) && + DRXJ_ISQAMSTD(agcSettings->standard)) || + (DRXJ_ISATVSTD(extAttr->standard) && + DRXJ_ISATVSTD(agcSettings->standard))) { + SARR16(devAddr, SCU_RAM_AGC_RF_IACCU_HI__A, + &(agcSettings->outputLevel)); + } - return (DRX_STS_OK); + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /** @@ -5617,186 +5321,187 @@ rw_error: * \return DRXStatus_t. */ static DRXStatus_t -SetAgcIf ( pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings, Bool_t atomic ) +SetAgcIf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings, Bool_t atomic) { - pI2CDeviceAddr_t devAddr = NULL; - pDRXJData_t extAttr = NULL; - pDRXJCfgAgc_t pAgcSettings = NULL; - pDRXCommonAttr_t commonAttr = NULL; - DRXWriteReg16Func_t ScuWr16 = NULL; - DRXReadReg16Func_t ScuRr16 = NULL; - - commonAttr = (pDRXCommonAttr_t) demod -> myCommonAttr; - devAddr = demod -> myI2CDevAddr; - extAttr = (pDRXJData_t)demod->myExtAttr; - - if (atomic) - { - ScuRr16 = DRXJ_DAP_SCU_AtomicReadReg16; - ScuWr16 = DRXJ_DAP_SCU_AtomicWriteReg16; - } - else - { - ScuRr16 = DRXJ_DAP.readReg16Func; - ScuWr16 = DRXJ_DAP.writeReg16Func; - } - - /* Configure AGC only if standard is currently active*/ - if ( ( extAttr->standard == agcSettings->standard ) || - ( DRXJ_ISQAMSTD( extAttr->standard ) && - DRXJ_ISQAMSTD( agcSettings->standard ) ) || - ( DRXJ_ISATVSTD( extAttr->standard ) && - DRXJ_ISATVSTD( agcSettings->standard ) ) ) - { - u16_t data = 0; - - switch ( agcSettings->ctrlMode ) - { - case DRX_AGC_CTRL_AUTO: - /* Enable IF AGC DAC */ - RR16( devAddr, IQM_AF_STDBY__A , &data ); - data |= IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE; - WR16( devAddr, IQM_AF_STDBY__A , data ); - - /* Enable SCU IF AGC loop */ - CHK_ERROR((*ScuRr16)( devAddr, SCU_RAM_AGC_KI__A, &data, 0 )); - data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M; - data &= ~SCU_RAM_AGC_KI_IF__M; - if ( extAttr->standard == DRX_STANDARD_8VSB ) - { - data |= (3 << SCU_RAM_AGC_KI_IF__B ); - } - else if (DRXJ_ISQAMSTD( extAttr->standard )) - { - data |= (6 << SCU_RAM_AGC_KI_IF__B ); - } - else - { - data |= ( 5 << SCU_RAM_AGC_KI_IF__B ); - } - - if (commonAttr->tunerIfAgcPol) - { - data |= SCU_RAM_AGC_KI_INV_IF_POL__M; - } - else - { - data &= ~SCU_RAM_AGC_KI_INV_IF_POL__M; - } - CHK_ERROR((*ScuWr16)( devAddr, SCU_RAM_AGC_KI__A, data, 0 )); - - /* Set speed (using complementary reduction value) */ - CHK_ERROR((*ScuRr16)( devAddr, SCU_RAM_AGC_KI_RED__A , &data, 0 )); - data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M; - CHK_ERROR((*ScuWr16)( devAddr, SCU_RAM_AGC_KI_RED__A , - (~(agcSettings->speed << SCU_RAM_AGC_KI_RED_IAGC_RED__B) - & SCU_RAM_AGC_KI_RED_IAGC_RED__M ) - | data, 0 )); - - if (agcSettings->standard == DRX_STANDARD_8VSB) - pAgcSettings = &(extAttr->vsbRfAgcCfg); - else if (DRXJ_ISQAMSTD( agcSettings->standard )) - pAgcSettings = &(extAttr->qamRfAgcCfg); - else if (DRXJ_ISATVSTD( agcSettings->standard )) - pAgcSettings = &(extAttr->atvRfAgcCfg); - else - return (DRX_STS_INVALID_ARG); - - /* Restore TOP */ - if ( pAgcSettings->ctrlMode == DRX_AGC_CTRL_AUTO) - { - CHK_ERROR((*ScuWr16)( devAddr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, - pAgcSettings->top, 0 )); - CHK_ERROR((*ScuWr16)( devAddr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, - pAgcSettings->top, 0 )); - } - else - { - CHK_ERROR((*ScuWr16)( devAddr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, 0, 0 )); - CHK_ERROR((*ScuWr16)( devAddr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, 0, 0 )); - } - break; - - case DRX_AGC_CTRL_USER: - - /* Enable IF AGC DAC */ - RR16( devAddr, IQM_AF_STDBY__A , &data ); - data |= IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE; - WR16( devAddr, IQM_AF_STDBY__A , data ); - - /* Disable SCU IF AGC loop */ - CHK_ERROR((*ScuRr16)( devAddr, SCU_RAM_AGC_KI__A, &data, 0 )); - data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M; - data |= SCU_RAM_AGC_KI_IF_AGC_DISABLE__M; - if (commonAttr->tunerIfAgcPol) - { - data |= SCU_RAM_AGC_KI_INV_IF_POL__M; - } - else - { - data &= ~SCU_RAM_AGC_KI_INV_IF_POL__M; - } - CHK_ERROR((*ScuWr16)( devAddr, SCU_RAM_AGC_KI__A, data, 0 )); - - /* Write value to output pin */ - CHK_ERROR((*ScuWr16)( devAddr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, - agcSettings->outputLevel, 0 )); - break; - - case DRX_AGC_CTRL_OFF: - - /* Disable If AGC DAC */ - RR16( devAddr, IQM_AF_STDBY__A , &data ); - data &= (~IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE); - WR16( devAddr, IQM_AF_STDBY__A , data ); - - /* Disable SCU IF AGC loop */ - CHK_ERROR((*ScuRr16)( devAddr, SCU_RAM_AGC_KI__A, &data, 0 )); - data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M; - data |= SCU_RAM_AGC_KI_IF_AGC_DISABLE__M; - CHK_ERROR((*ScuWr16)( devAddr, SCU_RAM_AGC_KI__A, data, 0 )); - break; - default: - return (DRX_STS_INVALID_ARG); - } /* switch ( agcsettings->ctrlMode ) */ - - /* always set the top to support configurations without if-loop */ - CHK_ERROR((*ScuWr16)( devAddr, - SCU_RAM_AGC_INGAIN_TGT_MIN__A, - agcSettings->top, - 0 ) ); - } - - /* Store if agc settings */ - switch ( agcSettings->standard){ - case DRX_STANDARD_8VSB: - extAttr->vsbIfAgcCfg = *agcSettings; - break; + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + pDRXJCfgAgc_t pAgcSettings = NULL; + pDRXCommonAttr_t commonAttr = NULL; + DRXWriteReg16Func_t ScuWr16 = NULL; + DRXReadReg16Func_t ScuRr16 = NULL; + + commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; + + if (atomic) { + ScuRr16 = DRXJ_DAP_SCU_AtomicReadReg16; + ScuWr16 = DRXJ_DAP_SCU_AtomicWriteReg16; + } else { + ScuRr16 = DRXJ_DAP.readReg16Func; + ScuWr16 = DRXJ_DAP.writeReg16Func; + } + + /* Configure AGC only if standard is currently active */ + if ((extAttr->standard == agcSettings->standard) || + (DRXJ_ISQAMSTD(extAttr->standard) && + DRXJ_ISQAMSTD(agcSettings->standard)) || + (DRXJ_ISATVSTD(extAttr->standard) && + DRXJ_ISATVSTD(agcSettings->standard))) { + u16_t data = 0; + + switch (agcSettings->ctrlMode) { + case DRX_AGC_CTRL_AUTO: + /* Enable IF AGC DAC */ + RR16(devAddr, IQM_AF_STDBY__A, &data); + data |= IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE; + WR16(devAddr, IQM_AF_STDBY__A, data); + + /* Enable SCU IF AGC loop */ + CHK_ERROR((*ScuRr16) + (devAddr, SCU_RAM_AGC_KI__A, &data, 0)); + data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M; + data &= ~SCU_RAM_AGC_KI_IF__M; + if (extAttr->standard == DRX_STANDARD_8VSB) { + data |= (3 << SCU_RAM_AGC_KI_IF__B); + } else if (DRXJ_ISQAMSTD(extAttr->standard)) { + data |= (6 << SCU_RAM_AGC_KI_IF__B); + } else { + data |= (5 << SCU_RAM_AGC_KI_IF__B); + } + + if (commonAttr->tunerIfAgcPol) { + data |= SCU_RAM_AGC_KI_INV_IF_POL__M; + } else { + data &= ~SCU_RAM_AGC_KI_INV_IF_POL__M; + } + CHK_ERROR((*ScuWr16) + (devAddr, SCU_RAM_AGC_KI__A, data, 0)); + + /* Set speed (using complementary reduction value) */ + CHK_ERROR((*ScuRr16) + (devAddr, SCU_RAM_AGC_KI_RED__A, &data, 0)); + data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M; + CHK_ERROR((*ScuWr16) (devAddr, SCU_RAM_AGC_KI_RED__A, + (~ + (agcSettings-> + speed << + SCU_RAM_AGC_KI_RED_IAGC_RED__B) +& SCU_RAM_AGC_KI_RED_IAGC_RED__M) + | data, 0)); + + if (agcSettings->standard == DRX_STANDARD_8VSB) + pAgcSettings = &(extAttr->vsbRfAgcCfg); + else if (DRXJ_ISQAMSTD(agcSettings->standard)) + pAgcSettings = &(extAttr->qamRfAgcCfg); + else if (DRXJ_ISATVSTD(agcSettings->standard)) + pAgcSettings = &(extAttr->atvRfAgcCfg); + else + return (DRX_STS_INVALID_ARG); + + /* Restore TOP */ + if (pAgcSettings->ctrlMode == DRX_AGC_CTRL_AUTO) { + CHK_ERROR((*ScuWr16) + (devAddr, + SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, + pAgcSettings->top, 0)); + CHK_ERROR((*ScuWr16) + (devAddr, + SCU_RAM_AGC_IF_IACCU_HI_TGT__A, + pAgcSettings->top, 0)); + } else { + CHK_ERROR((*ScuWr16) + (devAddr, + SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, + 0, 0)); + CHK_ERROR((*ScuWr16) + (devAddr, + SCU_RAM_AGC_IF_IACCU_HI_TGT__A, 0, + 0)); + } + break; + + case DRX_AGC_CTRL_USER: + + /* Enable IF AGC DAC */ + RR16(devAddr, IQM_AF_STDBY__A, &data); + data |= IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE; + WR16(devAddr, IQM_AF_STDBY__A, data); + + /* Disable SCU IF AGC loop */ + CHK_ERROR((*ScuRr16) + (devAddr, SCU_RAM_AGC_KI__A, &data, 0)); + data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M; + data |= SCU_RAM_AGC_KI_IF_AGC_DISABLE__M; + if (commonAttr->tunerIfAgcPol) { + data |= SCU_RAM_AGC_KI_INV_IF_POL__M; + } else { + data &= ~SCU_RAM_AGC_KI_INV_IF_POL__M; + } + CHK_ERROR((*ScuWr16) + (devAddr, SCU_RAM_AGC_KI__A, data, 0)); + + /* Write value to output pin */ + CHK_ERROR((*ScuWr16) + (devAddr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, + agcSettings->outputLevel, 0)); + break; + + case DRX_AGC_CTRL_OFF: + + /* Disable If AGC DAC */ + RR16(devAddr, IQM_AF_STDBY__A, &data); + data &= (~IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE); + WR16(devAddr, IQM_AF_STDBY__A, data); + + /* Disable SCU IF AGC loop */ + CHK_ERROR((*ScuRr16) + (devAddr, SCU_RAM_AGC_KI__A, &data, 0)); + data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M; + data |= SCU_RAM_AGC_KI_IF_AGC_DISABLE__M; + CHK_ERROR((*ScuWr16) + (devAddr, SCU_RAM_AGC_KI__A, data, 0)); + break; + default: + return (DRX_STS_INVALID_ARG); + } /* switch ( agcsettings->ctrlMode ) */ + + /* always set the top to support configurations without if-loop */ + CHK_ERROR((*ScuWr16) (devAddr, + SCU_RAM_AGC_INGAIN_TGT_MIN__A, + agcSettings->top, 0)); + } + + /* Store if agc settings */ + switch (agcSettings->standard) { + case DRX_STANDARD_8VSB: + extAttr->vsbIfAgcCfg = *agcSettings; + break; #ifndef DRXJ_VSB_ONLY - case DRX_STANDARD_ITU_A: - case DRX_STANDARD_ITU_B: - case DRX_STANDARD_ITU_C: - extAttr->qamIfAgcCfg = *agcSettings; - break; + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: + extAttr->qamIfAgcCfg = *agcSettings; + break; #endif #ifndef DRXJ_DIGITAL_ONLY - case DRX_STANDARD_PAL_SECAM_BG: - case DRX_STANDARD_PAL_SECAM_DK: - case DRX_STANDARD_PAL_SECAM_I: - case DRX_STANDARD_PAL_SECAM_L: - case DRX_STANDARD_PAL_SECAM_LP: - case DRX_STANDARD_NTSC: - case DRX_STANDARD_FM: - extAttr->atvIfAgcCfg = *agcSettings; - break; + case DRX_STANDARD_PAL_SECAM_BG: + case DRX_STANDARD_PAL_SECAM_DK: + case DRX_STANDARD_PAL_SECAM_I: + case DRX_STANDARD_PAL_SECAM_L: + case DRX_STANDARD_PAL_SECAM_LP: + case DRX_STANDARD_NTSC: + case DRX_STANDARD_FM: + extAttr->atvIfAgcCfg = *agcSettings; + break; #endif - default: - return (DRX_STS_ERROR); - } + default: + return (DRX_STS_ERROR); + } - return (DRX_STS_OK); + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /** @@ -5807,59 +5512,58 @@ rw_error: * \return DRXStatus_t. */ static DRXStatus_t -GetAgcIf ( pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings ) +GetAgcIf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings) { - pI2CDeviceAddr_t devAddr = NULL; - pDRXJData_t extAttr = NULL; - DRXStandard_t standard = DRX_STANDARD_UNKNOWN; - - devAddr = demod -> myI2CDevAddr; - extAttr = (pDRXJData_t)demod->myExtAttr; - - /* Return stored ATV AGC settings */ - standard = agcSettings->standard; - switch ( agcSettings->standard){ - case DRX_STANDARD_8VSB: - *agcSettings = extAttr->vsbIfAgcCfg; - break; + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + DRXStandard_t standard = DRX_STANDARD_UNKNOWN; + + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; + + /* Return stored ATV AGC settings */ + standard = agcSettings->standard; + switch (agcSettings->standard) { + case DRX_STANDARD_8VSB: + *agcSettings = extAttr->vsbIfAgcCfg; + break; #ifndef DRXJ_VSB_ONLY - case DRX_STANDARD_ITU_A: - case DRX_STANDARD_ITU_B: - case DRX_STANDARD_ITU_C: - *agcSettings = extAttr->qamIfAgcCfg; - break; + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: + *agcSettings = extAttr->qamIfAgcCfg; + break; #endif #ifndef DRXJ_DIGITAL_ONLY - case DRX_STANDARD_PAL_SECAM_BG: - case DRX_STANDARD_PAL_SECAM_DK: - case DRX_STANDARD_PAL_SECAM_I: - case DRX_STANDARD_PAL_SECAM_L: - case DRX_STANDARD_PAL_SECAM_LP: - case DRX_STANDARD_NTSC: - case DRX_STANDARD_FM: - *agcSettings = extAttr->atvIfAgcCfg; - break; + case DRX_STANDARD_PAL_SECAM_BG: + case DRX_STANDARD_PAL_SECAM_DK: + case DRX_STANDARD_PAL_SECAM_I: + case DRX_STANDARD_PAL_SECAM_L: + case DRX_STANDARD_PAL_SECAM_LP: + case DRX_STANDARD_NTSC: + case DRX_STANDARD_FM: + *agcSettings = extAttr->atvIfAgcCfg; + break; #endif - default: - return (DRX_STS_ERROR); - } - agcSettings->standard = standard; - - /* Get AGC output only if standard is currently active */ - if ( ( extAttr->standard == agcSettings->standard ) || - ( DRXJ_ISQAMSTD( extAttr->standard ) && - DRXJ_ISQAMSTD( agcSettings->standard ) ) || - ( DRXJ_ISATVSTD( extAttr->standard ) && - DRXJ_ISATVSTD( agcSettings->standard ) ) ) - { - /* read output level */ - SARR16( devAddr, SCU_RAM_AGC_IF_IACCU_HI__A, - &(agcSettings->outputLevel) ); - } + default: + return (DRX_STS_ERROR); + } + agcSettings->standard = standard; + + /* Get AGC output only if standard is currently active */ + if ((extAttr->standard == agcSettings->standard) || + (DRXJ_ISQAMSTD(extAttr->standard) && + DRXJ_ISQAMSTD(agcSettings->standard)) || + (DRXJ_ISATVSTD(extAttr->standard) && + DRXJ_ISATVSTD(agcSettings->standard))) { + /* read output level */ + SARR16(devAddr, SCU_RAM_AGC_IF_IACCU_HI__A, + &(agcSettings->outputLevel)); + } - return (DRX_STS_OK); + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /** @@ -5869,39 +5573,35 @@ rw_error: * \param active * \return DRXStatus_t. */ -static DRXStatus_t -SetIqmAf ( pDRXDemodInstance_t demod, Bool_t active ) +static DRXStatus_t SetIqmAf(pDRXDemodInstance_t demod, Bool_t active) { - u16_t data = 0; - pI2CDeviceAddr_t devAddr = NULL; + u16_t data = 0; + pI2CDeviceAddr_t devAddr = NULL; - devAddr = demod -> myI2CDevAddr; + devAddr = demod->myI2CDevAddr; - /* Configure IQM */ - RR16( devAddr, IQM_AF_STDBY__A , &data ); - if( !active ) - { - data &= ((~IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE) - & (~IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE) - & (~IQM_AF_STDBY_STDBY_PD_A2_ACTIVE) - & (~IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE) - & (~IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE) - ); - } - else /* active */ - { - data |= (IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE - | IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE - | IQM_AF_STDBY_STDBY_PD_A2_ACTIVE - | IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE - | IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE - ); - } - WR16( devAddr, IQM_AF_STDBY__A , data ); - - return (DRX_STS_OK); + /* Configure IQM */ + RR16(devAddr, IQM_AF_STDBY__A, &data); + if (!active) { + data &= ((~IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE) + & (~IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE) + & (~IQM_AF_STDBY_STDBY_PD_A2_ACTIVE) + & (~IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE) + & (~IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE) + ); + } else { /* active */ + + data |= (IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE + | IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE + | IQM_AF_STDBY_STDBY_PD_A2_ACTIVE + | IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE + | IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE); + } + WR16(devAddr, IQM_AF_STDBY__A, data); + + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /*============================================================================*/ @@ -5914,7 +5614,6 @@ rw_error: /*============================================================================*/ /*============================================================================*/ - /** * \fn DRXStatus_t PowerDownVSB () * \brief Powr down QAM related blocks. @@ -5922,265 +5621,262 @@ rw_error: * \param channel pointer to channel data. * \return DRXStatus_t. */ -static DRXStatus_t -PowerDownVSB( pDRXDemodInstance_t demod, Bool_t primary ) -{ - pI2CDeviceAddr_t devAddr = NULL; - DRXJSCUCmd_t cmdSCU = { /* command */ 0, - /* parameterLen */ 0, - /* resultLen */ 0, - /* *parameter */ NULL, - /* *result */ NULL }; - u16_t cmdResult = 0; - pDRXJData_t extAttr = NULL; - DRXCfgMPEGOutput_t cfgMPEGOutput; - - devAddr = demod -> myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; - /* - STOP demodulator - reset of FEC and VSB HW - */ - cmdSCU.command = SCU_RAM_COMMAND_STANDARD_VSB | - SCU_RAM_COMMAND_CMD_DEMOD_STOP; - cmdSCU.parameterLen = 0; - cmdSCU.resultLen = 1; - cmdSCU.parameter = NULL; - cmdSCU.result = &cmdResult; - CHK_ERROR( SCUCommand( devAddr, &cmdSCU ) ); - - /* stop all comm_exec */ - WR16( devAddr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP ); - WR16( devAddr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP ); - if (primary == TRUE) - { - WR16( devAddr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP ); - CHK_ERROR( SetIqmAf( demod, FALSE ) ); - } - else - { - WR16( devAddr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP ); - WR16( devAddr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP ); - WR16( devAddr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP ); - WR16( devAddr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP ); - WR16( devAddr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP ); - } +static DRXStatus_t PowerDownVSB(pDRXDemodInstance_t demod, Bool_t primary) +{ + pI2CDeviceAddr_t devAddr = NULL; + DRXJSCUCmd_t cmdSCU = { /* command */ 0, + /* parameterLen */ 0, + /* resultLen */ 0, + /* *parameter */ NULL, + /* *result */ NULL + }; + u16_t cmdResult = 0; + pDRXJData_t extAttr = NULL; + DRXCfgMPEGOutput_t cfgMPEGOutput; + + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; + /* + STOP demodulator + reset of FEC and VSB HW + */ + cmdSCU.command = SCU_RAM_COMMAND_STANDARD_VSB | + SCU_RAM_COMMAND_CMD_DEMOD_STOP; + cmdSCU.parameterLen = 0; + cmdSCU.resultLen = 1; + cmdSCU.parameter = NULL; + cmdSCU.result = &cmdResult; + CHK_ERROR(SCUCommand(devAddr, &cmdSCU)); + + /* stop all comm_exec */ + WR16(devAddr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP); + WR16(devAddr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP); + if (primary == TRUE) { + WR16(devAddr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP); + CHK_ERROR(SetIqmAf(demod, FALSE)); + } else { + WR16(devAddr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP); + WR16(devAddr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP); + WR16(devAddr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP); + WR16(devAddr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP); + WR16(devAddr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP); + } - cfgMPEGOutput.enableMPEGOutput = FALSE; - CHK_ERROR( CtrlSetCfgMPEGOutput( demod, &cfgMPEGOutput) ); + cfgMPEGOutput.enableMPEGOutput = FALSE; + CHK_ERROR(CtrlSetCfgMPEGOutput(demod, &cfgMPEGOutput)); - return (DRX_STS_OK); + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } + /** * \fn DRXStatus_t SetVSBLeakNGain () * \brief Set ATSC demod. * \param demod instance of demodulator. * \return DRXStatus_t. */ -static DRXStatus_t -SetVSBLeakNGain ( pDRXDemodInstance_t demod ) -{ - pI2CDeviceAddr_t devAddr = NULL; - - const u8_t vsb_ffe_leak_gain_ram0[]= { - DRXJ_16TO8( 0x8 ), /* FFETRAINLKRATIO1 */ - DRXJ_16TO8( 0x8 ), /* FFETRAINLKRATIO2 */ - DRXJ_16TO8( 0x8 ), /* FFETRAINLKRATIO3 */ - DRXJ_16TO8( 0xf ), /* FFETRAINLKRATIO4 */ - DRXJ_16TO8( 0xf ), /* FFETRAINLKRATIO5 */ - DRXJ_16TO8( 0xf ), /* FFETRAINLKRATIO6 */ - DRXJ_16TO8( 0xf ), /* FFETRAINLKRATIO7 */ - DRXJ_16TO8( 0xf ), /* FFETRAINLKRATIO8 */ - DRXJ_16TO8( 0xf ), /* FFETRAINLKRATIO9 */ - DRXJ_16TO8( 0x8 ), /* FFETRAINLKRATIO10 */ - DRXJ_16TO8( 0x8 ), /* FFETRAINLKRATIO11 */ - DRXJ_16TO8( 0x8 ), /* FFETRAINLKRATIO12 */ - DRXJ_16TO8( 0x10 ), /* FFERCA1TRAINLKRATIO1 */ - DRXJ_16TO8( 0x10 ), /* FFERCA1TRAINLKRATIO2 */ - DRXJ_16TO8( 0x10 ), /* FFERCA1TRAINLKRATIO3 */ - DRXJ_16TO8( 0x20 ), /* FFERCA1TRAINLKRATIO4 */ - DRXJ_16TO8( 0x20 ), /* FFERCA1TRAINLKRATIO5 */ - DRXJ_16TO8( 0x20 ), /* FFERCA1TRAINLKRATIO6 */ - DRXJ_16TO8( 0x20 ), /* FFERCA1TRAINLKRATIO7 */ - DRXJ_16TO8( 0x20 ), /* FFERCA1TRAINLKRATIO8 */ - DRXJ_16TO8( 0x20 ), /* FFERCA1TRAINLKRATIO9 */ - DRXJ_16TO8( 0x10 ), /* FFERCA1TRAINLKRATIO10 */ - DRXJ_16TO8( 0x10 ), /* FFERCA1TRAINLKRATIO11 */ - DRXJ_16TO8( 0x10 ), /* FFERCA1TRAINLKRATIO12 */ - DRXJ_16TO8( 0x10 ), /* FFERCA1DATALKRATIO1 */ - DRXJ_16TO8( 0x10 ), /* FFERCA1DATALKRATIO2 */ - DRXJ_16TO8( 0x10 ), /* FFERCA1DATALKRATIO3 */ - DRXJ_16TO8( 0x20 ), /* FFERCA1DATALKRATIO4 */ - DRXJ_16TO8( 0x20 ), /* FFERCA1DATALKRATIO5 */ - DRXJ_16TO8( 0x20 ), /* FFERCA1DATALKRATIO6 */ - DRXJ_16TO8( 0x20 ), /* FFERCA1DATALKRATIO7 */ - DRXJ_16TO8( 0x20 ), /* FFERCA1DATALKRATIO8 */ - DRXJ_16TO8( 0x20 ), /* FFERCA1DATALKRATIO9 */ - DRXJ_16TO8( 0x10 ), /* FFERCA1DATALKRATIO10 */ - DRXJ_16TO8( 0x10 ), /* FFERCA1DATALKRATIO11 */ - DRXJ_16TO8( 0x10 ), /* FFERCA1DATALKRATIO12 */ - DRXJ_16TO8( 0x10 ), /* FFERCA2TRAINLKRATIO1 */ - DRXJ_16TO8( 0x10 ), /* FFERCA2TRAINLKRATIO2 */ - DRXJ_16TO8( 0x10 ), /* FFERCA2TRAINLKRATIO3 */ - DRXJ_16TO8( 0x20 ), /* FFERCA2TRAINLKRATIO4 */ - DRXJ_16TO8( 0x20 ), /* FFERCA2TRAINLKRATIO5 */ - DRXJ_16TO8( 0x20 ), /* FFERCA2TRAINLKRATIO6 */ - DRXJ_16TO8( 0x20 ), /* FFERCA2TRAINLKRATIO7 */ - DRXJ_16TO8( 0x20 ), /* FFERCA2TRAINLKRATIO8 */ - DRXJ_16TO8( 0x20 ), /* FFERCA2TRAINLKRATIO9 */ - DRXJ_16TO8( 0x10 ), /* FFERCA2TRAINLKRATIO10 */ - DRXJ_16TO8( 0x10 ), /* FFERCA2TRAINLKRATIO11 */ - DRXJ_16TO8( 0x10 ), /* FFERCA2TRAINLKRATIO12 */ - DRXJ_16TO8( 0x10 ), /* FFERCA2DATALKRATIO1 */ - DRXJ_16TO8( 0x10 ), /* FFERCA2DATALKRATIO2 */ - DRXJ_16TO8( 0x10 ), /* FFERCA2DATALKRATIO3 */ - DRXJ_16TO8( 0x20 ), /* FFERCA2DATALKRATIO4 */ - DRXJ_16TO8( 0x20 ), /* FFERCA2DATALKRATIO5 */ - DRXJ_16TO8( 0x20 ), /* FFERCA2DATALKRATIO6 */ - DRXJ_16TO8( 0x20 ), /* FFERCA2DATALKRATIO7 */ - DRXJ_16TO8( 0x20 ), /* FFERCA2DATALKRATIO8 */ - DRXJ_16TO8( 0x20 ), /* FFERCA2DATALKRATIO9 */ - DRXJ_16TO8( 0x10 ), /* FFERCA2DATALKRATIO10 */ - DRXJ_16TO8( 0x10 ), /* FFERCA2DATALKRATIO11 */ - DRXJ_16TO8( 0x10 ), /* FFERCA2DATALKRATIO12 */ - DRXJ_16TO8( 0x07 ), /* FFEDDM1TRAINLKRATIO1 */ - DRXJ_16TO8( 0x07 ), /* FFEDDM1TRAINLKRATIO2 */ - DRXJ_16TO8( 0x07 ), /* FFEDDM1TRAINLKRATIO3 */ - DRXJ_16TO8( 0x0e ), /* FFEDDM1TRAINLKRATIO4 */ - DRXJ_16TO8( 0x0e ), /* FFEDDM1TRAINLKRATIO5 */ - DRXJ_16TO8( 0x0e ), /* FFEDDM1TRAINLKRATIO6 */ - DRXJ_16TO8( 0x0e ), /* FFEDDM1TRAINLKRATIO7 */ - DRXJ_16TO8( 0x0e ), /* FFEDDM1TRAINLKRATIO8 */ - DRXJ_16TO8( 0x0e ), /* FFEDDM1TRAINLKRATIO9 */ - DRXJ_16TO8( 0x07 ), /* FFEDDM1TRAINLKRATIO10 */ - DRXJ_16TO8( 0x07 ), /* FFEDDM1TRAINLKRATIO11 */ - DRXJ_16TO8( 0x07 ), /* FFEDDM1TRAINLKRATIO12 */ - DRXJ_16TO8( 0x07 ), /* FFEDDM1DATALKRATIO1 */ - DRXJ_16TO8( 0x07 ), /* FFEDDM1DATALKRATIO2 */ - DRXJ_16TO8( 0x07 ), /* FFEDDM1DATALKRATIO3 */ - DRXJ_16TO8( 0x0e ), /* FFEDDM1DATALKRATIO4 */ - DRXJ_16TO8( 0x0e ), /* FFEDDM1DATALKRATIO5 */ - DRXJ_16TO8( 0x0e ), /* FFEDDM1DATALKRATIO6 */ - DRXJ_16TO8( 0x0e ), /* FFEDDM1DATALKRATIO7 */ - DRXJ_16TO8( 0x0e ), /* FFEDDM1DATALKRATIO8 */ - DRXJ_16TO8( 0x0e ), /* FFEDDM1DATALKRATIO9 */ - DRXJ_16TO8( 0x07 ), /* FFEDDM1DATALKRATIO10 */ - DRXJ_16TO8( 0x07 ), /* FFEDDM1DATALKRATIO11 */ - DRXJ_16TO8( 0x07 ), /* FFEDDM1DATALKRATIO12 */ - DRXJ_16TO8( 0x06 ), /* FFEDDM2TRAINLKRATIO1 */ - DRXJ_16TO8( 0x06 ), /* FFEDDM2TRAINLKRATIO2 */ - DRXJ_16TO8( 0x06 ), /* FFEDDM2TRAINLKRATIO3 */ - DRXJ_16TO8( 0x0c ), /* FFEDDM2TRAINLKRATIO4 */ - DRXJ_16TO8( 0x0c ), /* FFEDDM2TRAINLKRATIO5 */ - DRXJ_16TO8( 0x0c ), /* FFEDDM2TRAINLKRATIO6 */ - DRXJ_16TO8( 0x0c ), /* FFEDDM2TRAINLKRATIO7 */ - DRXJ_16TO8( 0x0c ), /* FFEDDM2TRAINLKRATIO8 */ - DRXJ_16TO8( 0x0c ), /* FFEDDM2TRAINLKRATIO9 */ - DRXJ_16TO8( 0x06 ), /* FFEDDM2TRAINLKRATIO10 */ - DRXJ_16TO8( 0x06 ), /* FFEDDM2TRAINLKRATIO11 */ - DRXJ_16TO8( 0x06 ), /* FFEDDM2TRAINLKRATIO12 */ - DRXJ_16TO8( 0x06 ), /* FFEDDM2DATALKRATIO1 */ - DRXJ_16TO8( 0x06 ), /* FFEDDM2DATALKRATIO2 */ - DRXJ_16TO8( 0x06 ), /* FFEDDM2DATALKRATIO3 */ - DRXJ_16TO8( 0x0c ), /* FFEDDM2DATALKRATIO4 */ - DRXJ_16TO8( 0x0c ), /* FFEDDM2DATALKRATIO5 */ - DRXJ_16TO8( 0x0c ), /* FFEDDM2DATALKRATIO6 */ - DRXJ_16TO8( 0x0c ), /* FFEDDM2DATALKRATIO7 */ - DRXJ_16TO8( 0x0c ), /* FFEDDM2DATALKRATIO8 */ - DRXJ_16TO8( 0x0c ), /* FFEDDM2DATALKRATIO9 */ - DRXJ_16TO8( 0x06 ), /* FFEDDM2DATALKRATIO10 */ - DRXJ_16TO8( 0x06 ), /* FFEDDM2DATALKRATIO11 */ - DRXJ_16TO8( 0x06 ), /* FFEDDM2DATALKRATIO12 */ - DRXJ_16TO8( 0x2020 ), /* FIRTRAINGAIN1 */ - DRXJ_16TO8( 0x2020 ), /* FIRTRAINGAIN2 */ - DRXJ_16TO8( 0x2020 ), /* FIRTRAINGAIN3 */ - DRXJ_16TO8( 0x4040 ), /* FIRTRAINGAIN4 */ - DRXJ_16TO8( 0x4040 ), /* FIRTRAINGAIN5 */ - DRXJ_16TO8( 0x4040 ), /* FIRTRAINGAIN6 */ - DRXJ_16TO8( 0x4040 ), /* FIRTRAINGAIN7 */ - DRXJ_16TO8( 0x4040 ), /* FIRTRAINGAIN8 */ - DRXJ_16TO8( 0x4040 ), /* FIRTRAINGAIN9 */ - DRXJ_16TO8( 0x2020 ), /* FIRTRAINGAIN10 */ - DRXJ_16TO8( 0x2020 ), /* FIRTRAINGAIN11 */ - DRXJ_16TO8( 0x2020 ), /* FIRTRAINGAIN12 */ - DRXJ_16TO8( 0x0808 ), /* FIRRCA1GAIN1 */ - DRXJ_16TO8( 0x0808 ), /* FIRRCA1GAIN2 */ - DRXJ_16TO8( 0x0808 ), /* FIRRCA1GAIN3 */ - DRXJ_16TO8( 0x1010 ), /* FIRRCA1GAIN4 */ - DRXJ_16TO8( 0x1010 ), /* FIRRCA1GAIN5 */ - DRXJ_16TO8( 0x1010 ), /* FIRRCA1GAIN6 */ - DRXJ_16TO8( 0x1010 ), /* FIRRCA1GAIN7 */ - DRXJ_16TO8( 0x1010 ) /* FIRRCA1GAIN8 */ - }; - - const u8_t vsb_ffe_leak_gain_ram1[]= { - DRXJ_16TO8( 0x1010 ), /* FIRRCA1GAIN9 */ - DRXJ_16TO8( 0x0808 ), /* FIRRCA1GAIN10 */ - DRXJ_16TO8( 0x0808 ), /* FIRRCA1GAIN11 */ - DRXJ_16TO8( 0x0808 ), /* FIRRCA1GAIN12 */ - DRXJ_16TO8( 0x0808 ), /* FIRRCA2GAIN1 */ - DRXJ_16TO8( 0x0808 ), /* FIRRCA2GAIN2 */ - DRXJ_16TO8( 0x0808 ), /* FIRRCA2GAIN3 */ - DRXJ_16TO8( 0x1010 ), /* FIRRCA2GAIN4 */ - DRXJ_16TO8( 0x1010 ), /* FIRRCA2GAIN5 */ - DRXJ_16TO8( 0x1010 ), /* FIRRCA2GAIN6 */ - DRXJ_16TO8( 0x1010 ), /* FIRRCA2GAIN7 */ - DRXJ_16TO8( 0x1010 ), /* FIRRCA2GAIN8 */ - DRXJ_16TO8( 0x1010 ), /* FIRRCA2GAIN9 */ - DRXJ_16TO8( 0x0808 ), /* FIRRCA2GAIN10 */ - DRXJ_16TO8( 0x0808 ), /* FIRRCA2GAIN11 */ - DRXJ_16TO8( 0x0808 ), /* FIRRCA2GAIN12 */ - DRXJ_16TO8( 0x0303 ), /* FIRDDM1GAIN1 */ - DRXJ_16TO8( 0x0303 ), /* FIRDDM1GAIN2 */ - DRXJ_16TO8( 0x0303 ), /* FIRDDM1GAIN3 */ - DRXJ_16TO8( 0x0606 ), /* FIRDDM1GAIN4 */ - DRXJ_16TO8( 0x0606 ), /* FIRDDM1GAIN5 */ - DRXJ_16TO8( 0x0606 ), /* FIRDDM1GAIN6 */ - DRXJ_16TO8( 0x0606 ), /* FIRDDM1GAIN7 */ - DRXJ_16TO8( 0x0606 ), /* FIRDDM1GAIN8 */ - DRXJ_16TO8( 0x0606 ), /* FIRDDM1GAIN9 */ - DRXJ_16TO8( 0x0303 ), /* FIRDDM1GAIN10 */ - DRXJ_16TO8( 0x0303 ), /* FIRDDM1GAIN11 */ - DRXJ_16TO8( 0x0303 ), /* FIRDDM1GAIN12 */ - DRXJ_16TO8( 0x0303 ), /* FIRDDM2GAIN1 */ - DRXJ_16TO8( 0x0303 ), /* FIRDDM2GAIN2 */ - DRXJ_16TO8( 0x0303 ), /* FIRDDM2GAIN3 */ - DRXJ_16TO8( 0x0505 ), /* FIRDDM2GAIN4 */ - DRXJ_16TO8( 0x0505 ), /* FIRDDM2GAIN5 */ - DRXJ_16TO8( 0x0505 ), /* FIRDDM2GAIN6 */ - DRXJ_16TO8( 0x0505 ), /* FIRDDM2GAIN7 */ - DRXJ_16TO8( 0x0505 ), /* FIRDDM2GAIN8 */ - DRXJ_16TO8( 0x0505 ), /* FIRDDM2GAIN9 */ - DRXJ_16TO8( 0x0303 ), /* FIRDDM2GAIN10 */ - DRXJ_16TO8( 0x0303 ), /* FIRDDM2GAIN11 */ - DRXJ_16TO8( 0x0303 ), /* FIRDDM2GAIN12 */ - DRXJ_16TO8( 0x001f ), /* DFETRAINLKRATIO */ - DRXJ_16TO8( 0x01ff ), /* DFERCA1TRAINLKRATIO */ - DRXJ_16TO8( 0x01ff ), /* DFERCA1DATALKRATIO */ - DRXJ_16TO8( 0x004f ), /* DFERCA2TRAINLKRATIO */ - DRXJ_16TO8( 0x004f ), /* DFERCA2DATALKRATIO */ - DRXJ_16TO8( 0x01ff ), /* DFEDDM1TRAINLKRATIO */ - DRXJ_16TO8( 0x01ff ), /* DFEDDM1DATALKRATIO */ - DRXJ_16TO8( 0x0352 ), /* DFEDDM2TRAINLKRATIO */ - DRXJ_16TO8( 0x0352 ), /* DFEDDM2DATALKRATIO */ - DRXJ_16TO8( 0x0000 ), /* DFETRAINGAIN */ - DRXJ_16TO8( 0x2020 ), /* DFERCA1GAIN */ - DRXJ_16TO8( 0x1010 ), /* DFERCA2GAIN */ - DRXJ_16TO8( 0x1818 ), /* DFEDDM1GAIN */ - DRXJ_16TO8( 0x1212 ) /* DFEDDM2GAIN */ - }; - - devAddr = demod -> myI2CDevAddr; - WRB ( devAddr, VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__A, - sizeof(vsb_ffe_leak_gain_ram0), ((pu8_t)vsb_ffe_leak_gain_ram0) ); - WRB ( devAddr, VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__A, - sizeof(vsb_ffe_leak_gain_ram1), ((pu8_t)vsb_ffe_leak_gain_ram1) ); - - return (DRX_STS_OK); +static DRXStatus_t SetVSBLeakNGain(pDRXDemodInstance_t demod) +{ + pI2CDeviceAddr_t devAddr = NULL; + + const u8_t vsb_ffe_leak_gain_ram0[] = { + DRXJ_16TO8(0x8), /* FFETRAINLKRATIO1 */ + DRXJ_16TO8(0x8), /* FFETRAINLKRATIO2 */ + DRXJ_16TO8(0x8), /* FFETRAINLKRATIO3 */ + DRXJ_16TO8(0xf), /* FFETRAINLKRATIO4 */ + DRXJ_16TO8(0xf), /* FFETRAINLKRATIO5 */ + DRXJ_16TO8(0xf), /* FFETRAINLKRATIO6 */ + DRXJ_16TO8(0xf), /* FFETRAINLKRATIO7 */ + DRXJ_16TO8(0xf), /* FFETRAINLKRATIO8 */ + DRXJ_16TO8(0xf), /* FFETRAINLKRATIO9 */ + DRXJ_16TO8(0x8), /* FFETRAINLKRATIO10 */ + DRXJ_16TO8(0x8), /* FFETRAINLKRATIO11 */ + DRXJ_16TO8(0x8), /* FFETRAINLKRATIO12 */ + DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO1 */ + DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO2 */ + DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO3 */ + DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO4 */ + DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO5 */ + DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO6 */ + DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO7 */ + DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO8 */ + DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO9 */ + DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO10 */ + DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO11 */ + DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO12 */ + DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO1 */ + DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO2 */ + DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO3 */ + DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO4 */ + DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO5 */ + DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO6 */ + DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO7 */ + DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO8 */ + DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO9 */ + DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO10 */ + DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO11 */ + DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO12 */ + DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO1 */ + DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO2 */ + DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO3 */ + DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO4 */ + DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO5 */ + DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO6 */ + DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO7 */ + DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO8 */ + DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO9 */ + DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO10 */ + DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO11 */ + DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO12 */ + DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO1 */ + DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO2 */ + DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO3 */ + DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO4 */ + DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO5 */ + DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO6 */ + DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO7 */ + DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO8 */ + DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO9 */ + DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO10 */ + DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO11 */ + DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO12 */ + DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO1 */ + DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO2 */ + DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO3 */ + DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO4 */ + DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO5 */ + DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO6 */ + DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO7 */ + DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO8 */ + DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO9 */ + DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO10 */ + DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO11 */ + DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO12 */ + DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO1 */ + DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO2 */ + DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO3 */ + DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO4 */ + DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO5 */ + DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO6 */ + DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO7 */ + DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO8 */ + DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO9 */ + DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO10 */ + DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO11 */ + DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO12 */ + DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO1 */ + DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO2 */ + DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO3 */ + DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO4 */ + DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO5 */ + DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO6 */ + DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO7 */ + DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO8 */ + DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO9 */ + DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO10 */ + DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO11 */ + DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO12 */ + DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO1 */ + DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO2 */ + DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO3 */ + DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO4 */ + DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO5 */ + DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO6 */ + DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO7 */ + DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO8 */ + DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO9 */ + DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO10 */ + DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO11 */ + DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO12 */ + DRXJ_16TO8(0x2020), /* FIRTRAINGAIN1 */ + DRXJ_16TO8(0x2020), /* FIRTRAINGAIN2 */ + DRXJ_16TO8(0x2020), /* FIRTRAINGAIN3 */ + DRXJ_16TO8(0x4040), /* FIRTRAINGAIN4 */ + DRXJ_16TO8(0x4040), /* FIRTRAINGAIN5 */ + DRXJ_16TO8(0x4040), /* FIRTRAINGAIN6 */ + DRXJ_16TO8(0x4040), /* FIRTRAINGAIN7 */ + DRXJ_16TO8(0x4040), /* FIRTRAINGAIN8 */ + DRXJ_16TO8(0x4040), /* FIRTRAINGAIN9 */ + DRXJ_16TO8(0x2020), /* FIRTRAINGAIN10 */ + DRXJ_16TO8(0x2020), /* FIRTRAINGAIN11 */ + DRXJ_16TO8(0x2020), /* FIRTRAINGAIN12 */ + DRXJ_16TO8(0x0808), /* FIRRCA1GAIN1 */ + DRXJ_16TO8(0x0808), /* FIRRCA1GAIN2 */ + DRXJ_16TO8(0x0808), /* FIRRCA1GAIN3 */ + DRXJ_16TO8(0x1010), /* FIRRCA1GAIN4 */ + DRXJ_16TO8(0x1010), /* FIRRCA1GAIN5 */ + DRXJ_16TO8(0x1010), /* FIRRCA1GAIN6 */ + DRXJ_16TO8(0x1010), /* FIRRCA1GAIN7 */ + DRXJ_16TO8(0x1010) /* FIRRCA1GAIN8 */ + }; + + const u8_t vsb_ffe_leak_gain_ram1[] = { + DRXJ_16TO8(0x1010), /* FIRRCA1GAIN9 */ + DRXJ_16TO8(0x0808), /* FIRRCA1GAIN10 */ + DRXJ_16TO8(0x0808), /* FIRRCA1GAIN11 */ + DRXJ_16TO8(0x0808), /* FIRRCA1GAIN12 */ + DRXJ_16TO8(0x0808), /* FIRRCA2GAIN1 */ + DRXJ_16TO8(0x0808), /* FIRRCA2GAIN2 */ + DRXJ_16TO8(0x0808), /* FIRRCA2GAIN3 */ + DRXJ_16TO8(0x1010), /* FIRRCA2GAIN4 */ + DRXJ_16TO8(0x1010), /* FIRRCA2GAIN5 */ + DRXJ_16TO8(0x1010), /* FIRRCA2GAIN6 */ + DRXJ_16TO8(0x1010), /* FIRRCA2GAIN7 */ + DRXJ_16TO8(0x1010), /* FIRRCA2GAIN8 */ + DRXJ_16TO8(0x1010), /* FIRRCA2GAIN9 */ + DRXJ_16TO8(0x0808), /* FIRRCA2GAIN10 */ + DRXJ_16TO8(0x0808), /* FIRRCA2GAIN11 */ + DRXJ_16TO8(0x0808), /* FIRRCA2GAIN12 */ + DRXJ_16TO8(0x0303), /* FIRDDM1GAIN1 */ + DRXJ_16TO8(0x0303), /* FIRDDM1GAIN2 */ + DRXJ_16TO8(0x0303), /* FIRDDM1GAIN3 */ + DRXJ_16TO8(0x0606), /* FIRDDM1GAIN4 */ + DRXJ_16TO8(0x0606), /* FIRDDM1GAIN5 */ + DRXJ_16TO8(0x0606), /* FIRDDM1GAIN6 */ + DRXJ_16TO8(0x0606), /* FIRDDM1GAIN7 */ + DRXJ_16TO8(0x0606), /* FIRDDM1GAIN8 */ + DRXJ_16TO8(0x0606), /* FIRDDM1GAIN9 */ + DRXJ_16TO8(0x0303), /* FIRDDM1GAIN10 */ + DRXJ_16TO8(0x0303), /* FIRDDM1GAIN11 */ + DRXJ_16TO8(0x0303), /* FIRDDM1GAIN12 */ + DRXJ_16TO8(0x0303), /* FIRDDM2GAIN1 */ + DRXJ_16TO8(0x0303), /* FIRDDM2GAIN2 */ + DRXJ_16TO8(0x0303), /* FIRDDM2GAIN3 */ + DRXJ_16TO8(0x0505), /* FIRDDM2GAIN4 */ + DRXJ_16TO8(0x0505), /* FIRDDM2GAIN5 */ + DRXJ_16TO8(0x0505), /* FIRDDM2GAIN6 */ + DRXJ_16TO8(0x0505), /* FIRDDM2GAIN7 */ + DRXJ_16TO8(0x0505), /* FIRDDM2GAIN8 */ + DRXJ_16TO8(0x0505), /* FIRDDM2GAIN9 */ + DRXJ_16TO8(0x0303), /* FIRDDM2GAIN10 */ + DRXJ_16TO8(0x0303), /* FIRDDM2GAIN11 */ + DRXJ_16TO8(0x0303), /* FIRDDM2GAIN12 */ + DRXJ_16TO8(0x001f), /* DFETRAINLKRATIO */ + DRXJ_16TO8(0x01ff), /* DFERCA1TRAINLKRATIO */ + DRXJ_16TO8(0x01ff), /* DFERCA1DATALKRATIO */ + DRXJ_16TO8(0x004f), /* DFERCA2TRAINLKRATIO */ + DRXJ_16TO8(0x004f), /* DFERCA2DATALKRATIO */ + DRXJ_16TO8(0x01ff), /* DFEDDM1TRAINLKRATIO */ + DRXJ_16TO8(0x01ff), /* DFEDDM1DATALKRATIO */ + DRXJ_16TO8(0x0352), /* DFEDDM2TRAINLKRATIO */ + DRXJ_16TO8(0x0352), /* DFEDDM2DATALKRATIO */ + DRXJ_16TO8(0x0000), /* DFETRAINGAIN */ + DRXJ_16TO8(0x2020), /* DFERCA1GAIN */ + DRXJ_16TO8(0x1010), /* DFERCA2GAIN */ + DRXJ_16TO8(0x1818), /* DFEDDM1GAIN */ + DRXJ_16TO8(0x1212) /* DFEDDM2GAIN */ + }; + + devAddr = demod->myI2CDevAddr; + WRB(devAddr, VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__A, + sizeof(vsb_ffe_leak_gain_ram0), ((pu8_t) vsb_ffe_leak_gain_ram0)); + WRB(devAddr, VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__A, + sizeof(vsb_ffe_leak_gain_ram1), ((pu8_t) vsb_ffe_leak_gain_ram1)); + + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /** @@ -6190,215 +5886,218 @@ rw_error: * \return DRXStatus_t. * */ -static DRXStatus_t -SetVSB ( pDRXDemodInstance_t demod ) -{ - pI2CDeviceAddr_t devAddr = NULL; - u16_t cmdResult = 0; - u16_t cmdParam = 0; - pDRXCommonAttr_t commonAttr = NULL; - DRXJSCUCmd_t cmdSCU; - pDRXJData_t extAttr = NULL; - const u8_t vsb_taps_re[]= { - DRXJ_16TO8( -2 ), /* re0 */ - DRXJ_16TO8( 4 ), /* re1 */ - DRXJ_16TO8( 1 ), /* re2 */ - DRXJ_16TO8( -4 ), /* re3 */ - DRXJ_16TO8( 1 ), /* re4 */ - DRXJ_16TO8( 4 ), /* re5 */ - DRXJ_16TO8( -3 ), /* re6 */ - DRXJ_16TO8( -3 ), /* re7 */ - DRXJ_16TO8( 6 ), /* re8 */ - DRXJ_16TO8( 1 ), /* re9 */ - DRXJ_16TO8( -9 ), /* re10 */ - DRXJ_16TO8( 3 ), /* re11 */ - DRXJ_16TO8( 12 ), /* re12 */ - DRXJ_16TO8( -9 ), /* re13 */ - DRXJ_16TO8( -15 ), /* re14 */ - DRXJ_16TO8( 17 ), /* re15 */ - DRXJ_16TO8( 19 ), /* re16 */ - DRXJ_16TO8( -29 ), /* re17 */ - DRXJ_16TO8( -22 ), /* re18 */ - DRXJ_16TO8( 45 ), /* re19 */ - DRXJ_16TO8( 25 ), /* re20 */ - DRXJ_16TO8( -70 ), /* re21 */ - DRXJ_16TO8( -28 ), /* re22 */ - DRXJ_16TO8( 111 ), /* re23 */ - DRXJ_16TO8( 30 ), /* re24 */ - DRXJ_16TO8( -201 ), /* re25 */ - DRXJ_16TO8( -31 ), /* re26 */ - DRXJ_16TO8( 629 ) /* re27 */ - }; - - devAddr = demod -> myI2CDevAddr; - commonAttr = (pDRXCommonAttr_t) demod -> myCommonAttr; - extAttr = (pDRXJData_t)demod->myExtAttr; - - /* stop all comm_exec */ - WR16( devAddr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP ); - WR16( devAddr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP ); - WR16( devAddr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP ); - WR16( devAddr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP ); - WR16( devAddr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP ); - WR16( devAddr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP ); - WR16( devAddr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP ); - - /* reset demodulator */ - cmdSCU.command = SCU_RAM_COMMAND_STANDARD_VSB - | SCU_RAM_COMMAND_CMD_DEMOD_RESET; - cmdSCU.parameterLen = 0; - cmdSCU.resultLen = 1; - cmdSCU.parameter = NULL; - cmdSCU.result = &cmdResult; - CHK_ERROR( SCUCommand( devAddr, &cmdSCU ) ); - - WR16( devAddr, IQM_AF_DCF_BYPASS__A, 1 ); - WR16( devAddr, IQM_FS_ADJ_SEL__A, IQM_FS_ADJ_SEL_B_VSB ); - WR16( devAddr, IQM_RC_ADJ_SEL__A, IQM_RC_ADJ_SEL_B_VSB ); - extAttr->iqmRcRateOfs = 0x00AD0D79; - WR32( devAddr, IQM_RC_RATE_OFS_LO__A, extAttr->iqmRcRateOfs ); - WR16( devAddr, VSB_TOP_CFAGC_GAINSHIFT__A, 4); - WR16( devAddr, VSB_TOP_CYGN1TRK__A, 1); - - WR16( devAddr, IQM_RC_CROUT_ENA__A, 1 ); - WR16( devAddr, IQM_RC_STRETCH__A, 28 ); - WR16( devAddr, IQM_RT_ACTIVE__A, 0 ); - WR16( devAddr, IQM_CF_SYMMETRIC__A, 0 ); - WR16( devAddr, IQM_CF_MIDTAP__A, 3 ); - WR16( devAddr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_VSB__M ); - WR16( devAddr, IQM_CF_SCALE__A, 1393 ); - WR16( devAddr, IQM_CF_SCALE_SH__A, 0 ); - WR16( devAddr, IQM_CF_POW_MEAS_LEN__A, 1); - - WRB ( devAddr, IQM_CF_TAP_RE0__A, sizeof(vsb_taps_re), ((pu8_t)vsb_taps_re) ); - WRB ( devAddr, IQM_CF_TAP_IM0__A, sizeof(vsb_taps_re), ((pu8_t)vsb_taps_re) ); - - WR16( devAddr, VSB_TOP_BNTHRESH__A, 330 ); /* set higher threshold */ - WR16( devAddr, VSB_TOP_CLPLASTNUM__A, 90 ); /* burst detection on */ - WR16( devAddr, VSB_TOP_SNRTH_RCA1__A, 0x0042 ); /* drop thresholds by 1 dB */ - WR16( devAddr, VSB_TOP_SNRTH_RCA2__A, 0x0053 ); /* drop thresholds by 2 dB */ - WR16( devAddr, VSB_TOP_EQCTRL__A, 0x1 ); /* cma on */ - WR16( devAddr, SCU_RAM_GPIO__A, 0 ); /* GPIO */ - - /* Initialize the FEC Subsystem */ - WR16( devAddr, FEC_TOP_ANNEX__A, FEC_TOP_ANNEX_D ); - { - u16_t fecOcSncMode = 0; - RR16( devAddr, FEC_OC_SNC_MODE__A, &fecOcSncMode ); - /* output data even when not locked */ - WR16( devAddr, FEC_OC_SNC_MODE__A, fecOcSncMode | FEC_OC_SNC_MODE_UNLOCK_ENABLE__M ); - } - - /* set clip */ - WR16( devAddr, IQM_AF_CLP_LEN__A, 0); - WR16( devAddr, IQM_AF_CLP_TH__A, 470); - WR16( devAddr, IQM_AF_SNS_LEN__A, 0); - WR16( devAddr, VSB_TOP_SNRTH_PT__A, 0xD4 ); - /* no transparent, no A&C framing; parity is set in mpegoutput*/ - { - u16_t fecOcRegMode = 0; - RR16 ( devAddr, FEC_OC_MODE__A , &fecOcRegMode ); - WR16( devAddr, FEC_OC_MODE__A, fecOcRegMode & - (~(FEC_OC_MODE_TRANSPARENT__M - | FEC_OC_MODE_CLEAR__M - | FEC_OC_MODE_RETAIN_FRAMING__M) - ) ); - } - - WR16( devAddr, FEC_DI_TIMEOUT_LO__A, 0 ); /* timeout counter for restarting */ - WR16( devAddr, FEC_DI_TIMEOUT_HI__A, 3 ); - WR16( devAddr, FEC_RS_MODE__A, 0 ); /* bypass disabled */ - /* initialize RS packet error measurement parameters */ - WR16( devAddr, FEC_RS_MEASUREMENT_PERIOD__A, FEC_RS_MEASUREMENT_PERIOD ); - WR16( devAddr, FEC_RS_MEASUREMENT_PRESCALE__A, FEC_RS_MEASUREMENT_PRESCALE ); - - /* init measurement period of MER/SER */ - WR16( devAddr, VSB_TOP_MEASUREMENT_PERIOD__A, VSB_TOP_MEASUREMENT_PERIOD ); - WR32( devAddr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0 ); - WR16( devAddr, SCU_RAM_FEC_MEAS_COUNT__A, 0 ); - WR16( devAddr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0 ); - - WR16( devAddr, VSB_TOP_CKGN1TRK__A, 128 ); - /* B-Input to ADC, PGA+filter in standby */ - if ( extAttr->hasLNA == FALSE ) - { - WR16( devAddr, IQM_AF_AMUX__A, 0x02); - }; +static DRXStatus_t SetVSB(pDRXDemodInstance_t demod) +{ + pI2CDeviceAddr_t devAddr = NULL; + u16_t cmdResult = 0; + u16_t cmdParam = 0; + pDRXCommonAttr_t commonAttr = NULL; + DRXJSCUCmd_t cmdSCU; + pDRXJData_t extAttr = NULL; + const u8_t vsb_taps_re[] = { + DRXJ_16TO8(-2), /* re0 */ + DRXJ_16TO8(4), /* re1 */ + DRXJ_16TO8(1), /* re2 */ + DRXJ_16TO8(-4), /* re3 */ + DRXJ_16TO8(1), /* re4 */ + DRXJ_16TO8(4), /* re5 */ + DRXJ_16TO8(-3), /* re6 */ + DRXJ_16TO8(-3), /* re7 */ + DRXJ_16TO8(6), /* re8 */ + DRXJ_16TO8(1), /* re9 */ + DRXJ_16TO8(-9), /* re10 */ + DRXJ_16TO8(3), /* re11 */ + DRXJ_16TO8(12), /* re12 */ + DRXJ_16TO8(-9), /* re13 */ + DRXJ_16TO8(-15), /* re14 */ + DRXJ_16TO8(17), /* re15 */ + DRXJ_16TO8(19), /* re16 */ + DRXJ_16TO8(-29), /* re17 */ + DRXJ_16TO8(-22), /* re18 */ + DRXJ_16TO8(45), /* re19 */ + DRXJ_16TO8(25), /* re20 */ + DRXJ_16TO8(-70), /* re21 */ + DRXJ_16TO8(-28), /* re22 */ + DRXJ_16TO8(111), /* re23 */ + DRXJ_16TO8(30), /* re24 */ + DRXJ_16TO8(-201), /* re25 */ + DRXJ_16TO8(-31), /* re26 */ + DRXJ_16TO8(629) /* re27 */ + }; + + devAddr = demod->myI2CDevAddr; + commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; + extAttr = (pDRXJData_t) demod->myExtAttr; + + /* stop all comm_exec */ + WR16(devAddr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP); + WR16(devAddr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP); + WR16(devAddr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP); + WR16(devAddr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP); + WR16(devAddr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP); + WR16(devAddr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP); + WR16(devAddr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP); + + /* reset demodulator */ + cmdSCU.command = SCU_RAM_COMMAND_STANDARD_VSB + | SCU_RAM_COMMAND_CMD_DEMOD_RESET; + cmdSCU.parameterLen = 0; + cmdSCU.resultLen = 1; + cmdSCU.parameter = NULL; + cmdSCU.result = &cmdResult; + CHK_ERROR(SCUCommand(devAddr, &cmdSCU)); + + WR16(devAddr, IQM_AF_DCF_BYPASS__A, 1); + WR16(devAddr, IQM_FS_ADJ_SEL__A, IQM_FS_ADJ_SEL_B_VSB); + WR16(devAddr, IQM_RC_ADJ_SEL__A, IQM_RC_ADJ_SEL_B_VSB); + extAttr->iqmRcRateOfs = 0x00AD0D79; + WR32(devAddr, IQM_RC_RATE_OFS_LO__A, extAttr->iqmRcRateOfs); + WR16(devAddr, VSB_TOP_CFAGC_GAINSHIFT__A, 4); + WR16(devAddr, VSB_TOP_CYGN1TRK__A, 1); + + WR16(devAddr, IQM_RC_CROUT_ENA__A, 1); + WR16(devAddr, IQM_RC_STRETCH__A, 28); + WR16(devAddr, IQM_RT_ACTIVE__A, 0); + WR16(devAddr, IQM_CF_SYMMETRIC__A, 0); + WR16(devAddr, IQM_CF_MIDTAP__A, 3); + WR16(devAddr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_VSB__M); + WR16(devAddr, IQM_CF_SCALE__A, 1393); + WR16(devAddr, IQM_CF_SCALE_SH__A, 0); + WR16(devAddr, IQM_CF_POW_MEAS_LEN__A, 1); + + WRB(devAddr, IQM_CF_TAP_RE0__A, sizeof(vsb_taps_re), + ((pu8_t) vsb_taps_re)); + WRB(devAddr, IQM_CF_TAP_IM0__A, sizeof(vsb_taps_re), + ((pu8_t) vsb_taps_re)); + + WR16(devAddr, VSB_TOP_BNTHRESH__A, 330); /* set higher threshold */ + WR16(devAddr, VSB_TOP_CLPLASTNUM__A, 90); /* burst detection on */ + WR16(devAddr, VSB_TOP_SNRTH_RCA1__A, 0x0042); /* drop thresholds by 1 dB */ + WR16(devAddr, VSB_TOP_SNRTH_RCA2__A, 0x0053); /* drop thresholds by 2 dB */ + WR16(devAddr, VSB_TOP_EQCTRL__A, 0x1); /* cma on */ + WR16(devAddr, SCU_RAM_GPIO__A, 0); /* GPIO */ + + /* Initialize the FEC Subsystem */ + WR16(devAddr, FEC_TOP_ANNEX__A, FEC_TOP_ANNEX_D); + { + u16_t fecOcSncMode = 0; + RR16(devAddr, FEC_OC_SNC_MODE__A, &fecOcSncMode); + /* output data even when not locked */ + WR16(devAddr, FEC_OC_SNC_MODE__A, + fecOcSncMode | FEC_OC_SNC_MODE_UNLOCK_ENABLE__M); + } - /* turn on IQMAF. It has to be in front of setAgc**() */ - CHK_ERROR( SetIqmAf( demod, TRUE ) ); - CHK_ERROR(ADCSynchronization (demod)); + /* set clip */ + WR16(devAddr, IQM_AF_CLP_LEN__A, 0); + WR16(devAddr, IQM_AF_CLP_TH__A, 470); + WR16(devAddr, IQM_AF_SNS_LEN__A, 0); + WR16(devAddr, VSB_TOP_SNRTH_PT__A, 0xD4); + /* no transparent, no A&C framing; parity is set in mpegoutput */ + { + u16_t fecOcRegMode = 0; + RR16(devAddr, FEC_OC_MODE__A, &fecOcRegMode); + WR16(devAddr, FEC_OC_MODE__A, fecOcRegMode & + (~(FEC_OC_MODE_TRANSPARENT__M + | FEC_OC_MODE_CLEAR__M | FEC_OC_MODE_RETAIN_FRAMING__M) + )); + } - CHK_ERROR( InitAGC( demod ) ); - CHK_ERROR( SetAgcIf( demod, &(extAttr->vsbIfAgcCfg), FALSE ) ); - CHK_ERROR( SetAgcRf( demod, &(extAttr->vsbRfAgcCfg), FALSE ) ); - { - /* TODO fix this, store a DRXJCfgAfeGain_t structure in DRXJData_t instead - of only the gain */ - DRXJCfgAfeGain_t vsbPgaCfg = { DRX_STANDARD_8VSB, 0 }; - - vsbPgaCfg.gain = extAttr->vsbPgaCfg; - CHK_ERROR( CtrlSetCfgAfeGain( demod, &vsbPgaCfg ) ); - } - CHK_ERROR( CtrlSetCfgPreSaw( demod, &(extAttr->vsbPreSawCfg)) ); - - /* Mpeg output has to be in front of FEC active */ - CHK_ERROR ( SetMPEGTEIHandling ( demod )); - CHK_ERROR ( BitReverseMPEGOutput( demod ) ); - CHK_ERROR ( SetMPEGStartWidth ( demod ) ); - { - /* TODO: move to setStandard after hardware reset value problem is solved */ - /* Configure initial MPEG output */ - DRXCfgMPEGOutput_t cfgMPEGOutput; - cfgMPEGOutput.enableMPEGOutput = TRUE; - cfgMPEGOutput.insertRSByte = commonAttr->mpegCfg.insertRSByte; - cfgMPEGOutput.enableParallel = commonAttr->mpegCfg.enableParallel; - cfgMPEGOutput.invertDATA = commonAttr->mpegCfg.invertDATA; - cfgMPEGOutput.invertERR = commonAttr->mpegCfg.invertERR; - cfgMPEGOutput.invertSTR = commonAttr->mpegCfg.invertSTR; - cfgMPEGOutput.invertVAL = commonAttr->mpegCfg.invertVAL; - cfgMPEGOutput.invertCLK = commonAttr->mpegCfg.invertCLK; - cfgMPEGOutput.staticCLK = commonAttr->mpegCfg.staticCLK; - cfgMPEGOutput.bitrate = commonAttr->mpegCfg.bitrate; - CHK_ERROR( CtrlSetCfgMPEGOutput( demod, &cfgMPEGOutput) ); - } - - /* TBD: what parameters should be set */ - cmdParam = 0x00; /* Default mode AGC on, etc */ - cmdSCU.command = SCU_RAM_COMMAND_STANDARD_VSB - | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM; - cmdSCU.parameterLen = 1; - cmdSCU.resultLen = 1; - cmdSCU.parameter = &cmdParam; - cmdSCU.result = &cmdResult; - CHK_ERROR( SCUCommand( devAddr, &cmdSCU ) ); - - WR16(devAddr, VSB_TOP_BEAGC_GAINSHIFT__A, 0x0004 ); - WR16(devAddr, VSB_TOP_SNRTH_PT__A, 0x00D2 ); - WR16(devAddr, VSB_TOP_SYSSMTRNCTRL__A, VSB_TOP_SYSSMTRNCTRL__PRE - |VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__M ); - WR16(devAddr, VSB_TOP_BEDETCTRL__A, 0x142 ); - WR16(devAddr, VSB_TOP_LBAGCREFLVL__A, 640 ); - WR16(devAddr, VSB_TOP_CYGN1ACQ__A, 4 ); - WR16(devAddr, VSB_TOP_CYGN1TRK__A, 2 ); - WR16(devAddr, VSB_TOP_CYGN2TRK__A, 3 ); - - /* start demodulator */ - cmdSCU.command = SCU_RAM_COMMAND_STANDARD_VSB - | SCU_RAM_COMMAND_CMD_DEMOD_START; - cmdSCU.parameterLen = 0; - cmdSCU.resultLen = 1; - cmdSCU.parameter = NULL; - cmdSCU.result = &cmdResult; - CHK_ERROR( SCUCommand( devAddr, &cmdSCU ) ); - - WR16(devAddr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE ); - WR16(devAddr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_ACTIVE ); - WR16(devAddr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE ); - - return (DRX_STS_OK); + WR16(devAddr, FEC_DI_TIMEOUT_LO__A, 0); /* timeout counter for restarting */ + WR16(devAddr, FEC_DI_TIMEOUT_HI__A, 3); + WR16(devAddr, FEC_RS_MODE__A, 0); /* bypass disabled */ + /* initialize RS packet error measurement parameters */ + WR16(devAddr, FEC_RS_MEASUREMENT_PERIOD__A, FEC_RS_MEASUREMENT_PERIOD); + WR16(devAddr, FEC_RS_MEASUREMENT_PRESCALE__A, + FEC_RS_MEASUREMENT_PRESCALE); + + /* init measurement period of MER/SER */ + WR16(devAddr, VSB_TOP_MEASUREMENT_PERIOD__A, + VSB_TOP_MEASUREMENT_PERIOD); + WR32(devAddr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0); + WR16(devAddr, SCU_RAM_FEC_MEAS_COUNT__A, 0); + WR16(devAddr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0); + + WR16(devAddr, VSB_TOP_CKGN1TRK__A, 128); + /* B-Input to ADC, PGA+filter in standby */ + if (extAttr->hasLNA == FALSE) { + WR16(devAddr, IQM_AF_AMUX__A, 0x02); + }; + + /* turn on IQMAF. It has to be in front of setAgc**() */ + CHK_ERROR(SetIqmAf(demod, TRUE)); + CHK_ERROR(ADCSynchronization(demod)); + + CHK_ERROR(InitAGC(demod)); + CHK_ERROR(SetAgcIf(demod, &(extAttr->vsbIfAgcCfg), FALSE)); + CHK_ERROR(SetAgcRf(demod, &(extAttr->vsbRfAgcCfg), FALSE)); + { + /* TODO fix this, store a DRXJCfgAfeGain_t structure in DRXJData_t instead + of only the gain */ + DRXJCfgAfeGain_t vsbPgaCfg = { DRX_STANDARD_8VSB, 0 }; + + vsbPgaCfg.gain = extAttr->vsbPgaCfg; + CHK_ERROR(CtrlSetCfgAfeGain(demod, &vsbPgaCfg)); + } + CHK_ERROR(CtrlSetCfgPreSaw(demod, &(extAttr->vsbPreSawCfg))); + + /* Mpeg output has to be in front of FEC active */ + CHK_ERROR(SetMPEGTEIHandling(demod)); + CHK_ERROR(BitReverseMPEGOutput(demod)); + CHK_ERROR(SetMPEGStartWidth(demod)); + { + /* TODO: move to setStandard after hardware reset value problem is solved */ + /* Configure initial MPEG output */ + DRXCfgMPEGOutput_t cfgMPEGOutput; + cfgMPEGOutput.enableMPEGOutput = TRUE; + cfgMPEGOutput.insertRSByte = commonAttr->mpegCfg.insertRSByte; + cfgMPEGOutput.enableParallel = + commonAttr->mpegCfg.enableParallel; + cfgMPEGOutput.invertDATA = commonAttr->mpegCfg.invertDATA; + cfgMPEGOutput.invertERR = commonAttr->mpegCfg.invertERR; + cfgMPEGOutput.invertSTR = commonAttr->mpegCfg.invertSTR; + cfgMPEGOutput.invertVAL = commonAttr->mpegCfg.invertVAL; + cfgMPEGOutput.invertCLK = commonAttr->mpegCfg.invertCLK; + cfgMPEGOutput.staticCLK = commonAttr->mpegCfg.staticCLK; + cfgMPEGOutput.bitrate = commonAttr->mpegCfg.bitrate; + CHK_ERROR(CtrlSetCfgMPEGOutput(demod, &cfgMPEGOutput)); + } + + /* TBD: what parameters should be set */ + cmdParam = 0x00; /* Default mode AGC on, etc */ + cmdSCU.command = SCU_RAM_COMMAND_STANDARD_VSB + | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM; + cmdSCU.parameterLen = 1; + cmdSCU.resultLen = 1; + cmdSCU.parameter = &cmdParam; + cmdSCU.result = &cmdResult; + CHK_ERROR(SCUCommand(devAddr, &cmdSCU)); + + WR16(devAddr, VSB_TOP_BEAGC_GAINSHIFT__A, 0x0004); + WR16(devAddr, VSB_TOP_SNRTH_PT__A, 0x00D2); + WR16(devAddr, VSB_TOP_SYSSMTRNCTRL__A, VSB_TOP_SYSSMTRNCTRL__PRE + | VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__M); + WR16(devAddr, VSB_TOP_BEDETCTRL__A, 0x142); + WR16(devAddr, VSB_TOP_LBAGCREFLVL__A, 640); + WR16(devAddr, VSB_TOP_CYGN1ACQ__A, 4); + WR16(devAddr, VSB_TOP_CYGN1TRK__A, 2); + WR16(devAddr, VSB_TOP_CYGN2TRK__A, 3); + + /* start demodulator */ + cmdSCU.command = SCU_RAM_COMMAND_STANDARD_VSB + | SCU_RAM_COMMAND_CMD_DEMOD_START; + cmdSCU.parameterLen = 0; + cmdSCU.resultLen = 1; + cmdSCU.parameter = NULL; + cmdSCU.result = &cmdResult; + CHK_ERROR(SCUCommand(devAddr, &cmdSCU)); + + WR16(devAddr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE); + WR16(devAddr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_ACTIVE); + WR16(devAddr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE); + + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /** @@ -6406,30 +6105,30 @@ rw_error: * \brief Get the values of packet error in 8VSB mode * \return Error code */ -static DRXStatus_t -GetVSBPostRSPckErr(pI2CDeviceAddr_t devAddr, pu16_t pckErrs) -{ - u16_t data = 0; - u16_t period = 0; - u16_t prescale = 0; - u16_t packetErrorsMant = 0; - u16_t packetErrorsExp = 0; - - RR16(devAddr, FEC_RS_NR_FAILURES__A, &data ); - packetErrorsMant = data & FEC_RS_NR_FAILURES_FIXED_MANT__M; - packetErrorsExp = (data & FEC_RS_NR_FAILURES_EXP__M) - >> FEC_RS_NR_FAILURES_EXP__B; - period = FEC_RS_MEASUREMENT_PERIOD; - prescale = FEC_RS_MEASUREMENT_PRESCALE; - /* packet error rate = (error packet number) per second */ - /* 77.3 us is time for per packet */ - CHK_ZERO (period * prescale); - *pckErrs = (u16_t)FracTimes1e6(packetErrorsMant * (1 << packetErrorsExp), - (period * prescale * 77)); - - return (DRX_STS_OK); +static DRXStatus_t GetVSBPostRSPckErr(pI2CDeviceAddr_t devAddr, pu16_t pckErrs) +{ + u16_t data = 0; + u16_t period = 0; + u16_t prescale = 0; + u16_t packetErrorsMant = 0; + u16_t packetErrorsExp = 0; + + RR16(devAddr, FEC_RS_NR_FAILURES__A, &data); + packetErrorsMant = data & FEC_RS_NR_FAILURES_FIXED_MANT__M; + packetErrorsExp = (data & FEC_RS_NR_FAILURES_EXP__M) + >> FEC_RS_NR_FAILURES_EXP__B; + period = FEC_RS_MEASUREMENT_PERIOD; + prescale = FEC_RS_MEASUREMENT_PRESCALE; + /* packet error rate = (error packet number) per second */ + /* 77.3 us is time for per packet */ + CHK_ZERO(period * prescale); + *pckErrs = + (u16_t) FracTimes1e6(packetErrorsMant * (1 << packetErrorsExp), + (period * prescale * 77)); + + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /** @@ -6437,35 +6136,37 @@ rw_error: * \brief Get the values of ber in VSB mode * \return Error code */ -static DRXStatus_t -GetVSBpostViterbiBer(pI2CDeviceAddr_t devAddr, pu32_t ber) -{ - u16_t data = 0; - u16_t period = 0; - u16_t prescale = 0; - u16_t bitErrorsMant = 0; - u16_t bitErrorsExp = 0; - - RR16 ( devAddr, FEC_RS_NR_BIT_ERRORS__A, &data ); - period = FEC_RS_MEASUREMENT_PERIOD; - prescale = FEC_RS_MEASUREMENT_PRESCALE; - - bitErrorsMant = data & FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M; - bitErrorsExp = (data & FEC_RS_NR_BIT_ERRORS_EXP__M) - >> FEC_RS_NR_BIT_ERRORS_EXP__B; - - if ( ((bitErrorsMant << bitErrorsExp) >> 3) > 68700) - *ber = 26570; - else - { - CHK_ZERO (period * prescale); - *ber = FracTimes1e6(bitErrorsMant << ((bitErrorsExp > 2)? (bitErrorsExp - 3):bitErrorsExp), - period * prescale * 207 * ((bitErrorsExp > 2)?1:8) ); - } +static DRXStatus_t GetVSBpostViterbiBer(pI2CDeviceAddr_t devAddr, pu32_t ber) +{ + u16_t data = 0; + u16_t period = 0; + u16_t prescale = 0; + u16_t bitErrorsMant = 0; + u16_t bitErrorsExp = 0; + + RR16(devAddr, FEC_RS_NR_BIT_ERRORS__A, &data); + period = FEC_RS_MEASUREMENT_PERIOD; + prescale = FEC_RS_MEASUREMENT_PRESCALE; + + bitErrorsMant = data & FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M; + bitErrorsExp = (data & FEC_RS_NR_BIT_ERRORS_EXP__M) + >> FEC_RS_NR_BIT_ERRORS_EXP__B; + + if (((bitErrorsMant << bitErrorsExp) >> 3) > 68700) + *ber = 26570; + else { + CHK_ZERO(period * prescale); + *ber = + FracTimes1e6(bitErrorsMant << + ((bitErrorsExp > + 2) ? (bitErrorsExp - 3) : bitErrorsExp), + period * prescale * 207 * + ((bitErrorsExp > 2) ? 1 : 8)); + } - return (DRX_STS_OK); + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /** @@ -6473,17 +6174,18 @@ rw_error: * \brief Get the values of ber in VSB mode * \return Error code */ -static DRXStatus_t -GetVSBpreViterbiBer(pI2CDeviceAddr_t devAddr, pu32_t ber) +static DRXStatus_t GetVSBpreViterbiBer(pI2CDeviceAddr_t devAddr, pu32_t ber) { - u16_t data = 0; + u16_t data = 0; - RR16 ( devAddr, VSB_TOP_NR_SYM_ERRS__A, &data ); - *ber = FracTimes1e6( data, VSB_TOP_MEASUREMENT_PERIOD * SYMBOLS_PER_SEGMENT ); + RR16(devAddr, VSB_TOP_NR_SYM_ERRS__A, &data); + *ber = + FracTimes1e6(data, + VSB_TOP_MEASUREMENT_PERIOD * SYMBOLS_PER_SEGMENT); - return (DRX_STS_OK); + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /** @@ -6491,30 +6193,29 @@ rw_error: * \brief Get the values of ber in VSB mode * \return Error code */ -static DRXStatus_t -GetVSBSymbErr(pI2CDeviceAddr_t devAddr, pu32_t ser) +static DRXStatus_t GetVSBSymbErr(pI2CDeviceAddr_t devAddr, pu32_t ser) { - u16_t data = 0; - u16_t period = 0; - u16_t prescale = 0; - u16_t symbErrorsMant = 0; - u16_t symbErrorsExp = 0; + u16_t data = 0; + u16_t period = 0; + u16_t prescale = 0; + u16_t symbErrorsMant = 0; + u16_t symbErrorsExp = 0; - RR16 ( devAddr, FEC_RS_NR_SYMBOL_ERRORS__A, &data ); - period = FEC_RS_MEASUREMENT_PERIOD; - prescale = FEC_RS_MEASUREMENT_PRESCALE; + RR16(devAddr, FEC_RS_NR_SYMBOL_ERRORS__A, &data); + period = FEC_RS_MEASUREMENT_PERIOD; + prescale = FEC_RS_MEASUREMENT_PRESCALE; - symbErrorsMant = data & FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__M; - symbErrorsExp = (data & FEC_RS_NR_SYMBOL_ERRORS_EXP__M) - >> FEC_RS_NR_SYMBOL_ERRORS_EXP__B; + symbErrorsMant = data & FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__M; + symbErrorsExp = (data & FEC_RS_NR_SYMBOL_ERRORS_EXP__M) + >> FEC_RS_NR_SYMBOL_ERRORS_EXP__B; - CHK_ZERO (period * prescale); - *ser = (u32_t)FracTimes1e6((symbErrorsMant << symbErrorsExp) * 1000, - (period * prescale * 77318)); + CHK_ZERO(period * prescale); + *ser = (u32_t) FracTimes1e6((symbErrorsMant << symbErrorsExp) * 1000, + (period * prescale * 77318)); - return (DRX_STS_OK); + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /** @@ -6522,17 +6223,17 @@ rw_error: * \brief Get the values of MER * \return Error code */ -static DRXStatus_t -GetVSBMER (pI2CDeviceAddr_t devAddr, pu16_t mer) +static DRXStatus_t GetVSBMER(pI2CDeviceAddr_t devAddr, pu16_t mer) { - u16_t dataHi = 0; + u16_t dataHi = 0; - RR16( devAddr, VSB_TOP_ERR_ENERGY_H__A, &dataHi ); - *mer = (u16_t)(Log10Times100( 21504 ) - Log10Times100( (dataHi << 6) / 52 )); + RR16(devAddr, VSB_TOP_ERR_ENERGY_H__A, &dataHi); + *mer = + (u16_t) (Log10Times100(21504) - Log10Times100((dataHi << 6) / 52)); - return (DRX_STS_OK); + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /*============================================================================*/ @@ -6545,53 +6246,53 @@ rw_error: * \return DRXStatus_t. */ static DRXStatus_t -CtrlGetVSBConstel( pDRXDemodInstance_t demod, - pDRXComplex_t complexNr ) +CtrlGetVSBConstel(pDRXDemodInstance_t demod, pDRXComplex_t complexNr) { - pI2CDeviceAddr_t devAddr = NULL; /**< device address */ - u16_t vsbTopCommMb = 0; /**< VSB SL MB configuration */ - u16_t vsbTopCommMbInit = 0; /**< VSB SL MB intial configuration */ - u16_t re = 0; /**< constellation Re part */ - u32_t data = 0; - - /* read device info */ - devAddr = demod -> myI2CDevAddr; - - /* TODO: */ - /* Monitor bus grabbing is an open external interface issue */ - /* Needs to be checked when external interface PG is updated */ - - /* Configure MB (Monitor bus) */ - RR16( devAddr, VSB_TOP_COMM_MB__A, &vsbTopCommMbInit ); - /* set observe flag & MB mux */ - vsbTopCommMb = (vsbTopCommMbInit | - VSB_TOP_COMM_MB_OBS_OBS_ON | - VSB_TOP_COMM_MB_MUX_OBS_VSB_TCMEQ_2 ); - WR16( devAddr, VSB_TOP_COMM_MB__A, vsbTopCommMb ); - - /* Enable MB grabber in the FEC OC */ - WR16( devAddr, FEC_OC_OCR_MODE__A, FEC_OC_OCR_MODE_GRAB_ENABLE__M ); - - /* Disable MB grabber in the FEC OC */ - WR16( devAddr, FEC_OC_OCR_MODE__A, 0x0 ); - - /* read data */ - RR32( devAddr, FEC_OC_OCR_GRAB_RD1__A, &data ); - re = (u16_t)(((data >> 10) & 0x300 ) | ((data >> 2) & 0xff)); - if (re & 0x0200) - { - re |= 0xfc00; - } - complexNr->re = re; - complexNr->im = 0; + pI2CDeviceAddr_t devAddr = NULL; + /**< device address */ + u16_t vsbTopCommMb = 0; /**< VSB SL MB configuration */ + u16_t vsbTopCommMbInit = 0; /**< VSB SL MB intial configuration */ + u16_t re = 0; /**< constellation Re part */ + u32_t data = 0; + + /* read device info */ + devAddr = demod->myI2CDevAddr; + + /* TODO: */ + /* Monitor bus grabbing is an open external interface issue */ + /* Needs to be checked when external interface PG is updated */ + + /* Configure MB (Monitor bus) */ + RR16(devAddr, VSB_TOP_COMM_MB__A, &vsbTopCommMbInit); + /* set observe flag & MB mux */ + vsbTopCommMb = (vsbTopCommMbInit | + VSB_TOP_COMM_MB_OBS_OBS_ON | + VSB_TOP_COMM_MB_MUX_OBS_VSB_TCMEQ_2); + WR16(devAddr, VSB_TOP_COMM_MB__A, vsbTopCommMb); + + /* Enable MB grabber in the FEC OC */ + WR16(devAddr, FEC_OC_OCR_MODE__A, FEC_OC_OCR_MODE_GRAB_ENABLE__M); + + /* Disable MB grabber in the FEC OC */ + WR16(devAddr, FEC_OC_OCR_MODE__A, 0x0); + + /* read data */ + RR32(devAddr, FEC_OC_OCR_GRAB_RD1__A, &data); + re = (u16_t) (((data >> 10) & 0x300) | ((data >> 2) & 0xff)); + if (re & 0x0200) { + re |= 0xfc00; + } + complexNr->re = re; + complexNr->im = 0; - /* Restore MB (Monitor bus) */ - WR16( devAddr, VSB_TOP_COMM_MB__A, vsbTopCommMbInit ); + /* Restore MB (Monitor bus) */ + WR16(devAddr, VSB_TOP_COMM_MB__A, vsbTopCommMbInit); - return (DRX_STS_OK); - rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); } + /*============================================================================*/ /*== END 8VSB DATAPATH FUNCTIONS ==*/ /*============================================================================*/ @@ -6609,58 +6310,55 @@ CtrlGetVSBConstel( pDRXDemodInstance_t demod, * \param channel pointer to channel data. * \return DRXStatus_t. */ -static DRXStatus_t -PowerDownQAM( pDRXDemodInstance_t demod, Bool_t primary ) +static DRXStatus_t PowerDownQAM(pDRXDemodInstance_t demod, Bool_t primary) { - DRXJSCUCmd_t cmdSCU = { /* command */ 0, - /* parameterLen */ 0, - /* resultLen */ 0, - /* *parameter */ NULL, - /* *result */ NULL }; - u16_t cmdResult = 0; - pI2CDeviceAddr_t devAddr = NULL; - pDRXJData_t extAttr = NULL; - DRXCfgMPEGOutput_t cfgMPEGOutput; - - devAddr = demod -> myI2CDevAddr; - extAttr = (pDRXJData_t)demod->myExtAttr; - - /* - STOP demodulator - resets IQM, QAM and FEC HW blocks - */ - /* stop all comm_exec */ - WR16( devAddr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP); - WR16( devAddr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP); - - cmdSCU.command = SCU_RAM_COMMAND_STANDARD_QAM | - SCU_RAM_COMMAND_CMD_DEMOD_STOP; - cmdSCU.parameterLen = 0; - cmdSCU.resultLen = 1; - cmdSCU.parameter = NULL; - cmdSCU.result = &cmdResult; - CHK_ERROR( SCUCommand( devAddr, &cmdSCU ) ); - - if (primary == TRUE) - { - WR16( devAddr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP ); - CHK_ERROR( SetIqmAf( demod, FALSE ) ); - } - else - { - WR16( devAddr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP ); - WR16( devAddr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP ); - WR16( devAddr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP ); - WR16( devAddr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP ); - WR16( devAddr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP ); - } + DRXJSCUCmd_t cmdSCU = { /* command */ 0, + /* parameterLen */ 0, + /* resultLen */ 0, + /* *parameter */ NULL, + /* *result */ NULL + }; + u16_t cmdResult = 0; + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + DRXCfgMPEGOutput_t cfgMPEGOutput; + + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; - cfgMPEGOutput.enableMPEGOutput = FALSE; - CHK_ERROR( CtrlSetCfgMPEGOutput( demod, &cfgMPEGOutput) ); + /* + STOP demodulator + resets IQM, QAM and FEC HW blocks + */ + /* stop all comm_exec */ + WR16(devAddr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP); + WR16(devAddr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP); + + cmdSCU.command = SCU_RAM_COMMAND_STANDARD_QAM | + SCU_RAM_COMMAND_CMD_DEMOD_STOP; + cmdSCU.parameterLen = 0; + cmdSCU.resultLen = 1; + cmdSCU.parameter = NULL; + cmdSCU.result = &cmdResult; + CHK_ERROR(SCUCommand(devAddr, &cmdSCU)); + + if (primary == TRUE) { + WR16(devAddr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP); + CHK_ERROR(SetIqmAf(demod, FALSE)); + } else { + WR16(devAddr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP); + WR16(devAddr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP); + WR16(devAddr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP); + WR16(devAddr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP); + WR16(devAddr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP); + } + + cfgMPEGOutput.enableMPEGOutput = FALSE; + CHK_ERROR(CtrlSetCfgMPEGOutput(demod, &cfgMPEGOutput)); - return (DRX_STS_OK); + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /*============================================================================*/ @@ -6683,159 +6381,158 @@ rw_error: */ #ifndef DRXJ_VSB_ONLY static DRXStatus_t -SetQAMMeasurement ( pDRXDemodInstance_t demod, - DRXConstellation_t constellation, - u32_t symbolRate ) -{ - pI2CDeviceAddr_t devAddr = NULL; /* device address for I2C writes */ - pDRXJData_t extAttr = NULL; /* Global data container for DRXJ specif data */ - u32_t fecBitsDesired = 0; /* BER accounting period */ - u16_t fecRsPlen = 0; /* defines RS BER measurement period */ - u16_t fecRsPrescale = 0; /* ReedSolomon Measurement Prescale */ - u32_t fecRsPeriod = 0; /* Value for corresponding I2C register */ - u32_t fecRsBitCnt = 0; /* Actual precise amount of bits */ - u32_t fecOcSncFailPeriod = 0; /* Value for corresponding I2C register */ - u32_t qamVdPeriod = 0; /* Value for corresponding I2C register */ - u32_t qamVdBitCnt = 0; /* Actual precise amount of bits */ - u16_t fecVdPlen = 0; /* no of trellis symbols: VD SER measur period */ - u16_t qamVdPrescale = 0; /* Viterbi Measurement Prescale */ - - devAddr = demod -> myI2CDevAddr; - extAttr = (pDRXJData_t)demod->myExtAttr; - - fecBitsDesired = extAttr->fecBitsDesired; - fecRsPrescale = extAttr->fecRsPrescale; - - switch ( constellation ) { - case DRX_CONSTELLATION_QAM16: - fecBitsDesired = 4 * symbolRate; - break; - case DRX_CONSTELLATION_QAM32: - fecBitsDesired = 5 * symbolRate; - break; - case DRX_CONSTELLATION_QAM64: - fecBitsDesired = 6 * symbolRate; - break; - case DRX_CONSTELLATION_QAM128: - fecBitsDesired = 7 * symbolRate; - break; - case DRX_CONSTELLATION_QAM256: - fecBitsDesired = 8 * symbolRate; - break; - default: - return (DRX_STS_INVALID_ARG); - } - - /* Parameters for Reed-Solomon Decoder */ - /* fecrs_period = (int)ceil(FEC_BITS_DESIRED/(fecrs_prescale*plen)) */ - /* rs_bit_cnt = fecrs_period*fecrs_prescale*plen */ - /* result is within 32 bit arithmetic -> */ - /* no need for mult or frac functions */ - - /* TODO: use constant instead of calculation and remove the fecRsPlen in extAttr */ - switch ( extAttr->standard ) - { - case DRX_STANDARD_ITU_A: - case DRX_STANDARD_ITU_C: - fecRsPlen = 204 * 8; - break; - case DRX_STANDARD_ITU_B: - fecRsPlen = 128 * 7; - break; - default: - return (DRX_STS_INVALID_ARG); - } - - extAttr->fecRsPlen = fecRsPlen; /* for getSigQual */ - fecRsBitCnt = fecRsPrescale * fecRsPlen; /* temp storage */ - CHK_ZERO (fecRsBitCnt); - fecRsPeriod = fecBitsDesired / fecRsBitCnt + 1; /* ceil */ - if (extAttr->standard != DRX_STANDARD_ITU_B) - fecOcSncFailPeriod = fecRsPeriod; - - /* limit to max 16 bit value (I2C register width) if needed */ - if ( fecRsPeriod > 0xFFFF ) - fecRsPeriod = 0xFFFF; - - /* write corresponding registers */ - switch ( extAttr->standard ) - { - case DRX_STANDARD_ITU_A: - case DRX_STANDARD_ITU_C: - break; - case DRX_STANDARD_ITU_B: - switch ( constellation ) { - case DRX_CONSTELLATION_QAM64: - fecRsPeriod = 31581; - fecOcSncFailPeriod = 17932; - break; - case DRX_CONSTELLATION_QAM256: - fecRsPeriod = 45446; - fecOcSncFailPeriod = 25805; - break; - default: - return (DRX_STS_INVALID_ARG); - } - break; - default: - return (DRX_STS_INVALID_ARG); - } - - WR16 ( devAddr, FEC_OC_SNC_FAIL_PERIOD__A , ( u16_t ) fecOcSncFailPeriod ); - WR16 ( devAddr, FEC_RS_MEASUREMENT_PERIOD__A , ( u16_t ) fecRsPeriod ); - WR16 ( devAddr, FEC_RS_MEASUREMENT_PRESCALE__A , fecRsPrescale ); - extAttr->fecRsPeriod = (u16_t) fecRsPeriod; - extAttr->fecRsPrescale = fecRsPrescale; - WR32( devAddr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0 ); - WR16( devAddr, SCU_RAM_FEC_MEAS_COUNT__A, 0 ); - WR16( devAddr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0 ); - - if (extAttr->standard == DRX_STANDARD_ITU_B) - { - /* Parameters for Viterbi Decoder */ - /* qamvd_period = (int)ceil(FEC_BITS_DESIRED/ */ - /* (qamvd_prescale*plen*(qam_constellation+1))) */ - /* vd_bit_cnt = qamvd_period*qamvd_prescale*plen */ - /* result is within 32 bit arithmetic -> */ - /* no need for mult or frac functions */ - - /* a(8 bit) * b(8 bit) = 16 bit result => Mult32 not needed */ - fecVdPlen = extAttr->fecVdPlen; - qamVdPrescale = extAttr->qamVdPrescale; - qamVdBitCnt = qamVdPrescale * fecVdPlen; /* temp storage */ - - switch ( constellation ) { - case DRX_CONSTELLATION_QAM64: - /* a(16 bit) * b(4 bit) = 20 bit result => Mult32 not needed */ - qamVdPeriod = qamVdBitCnt * ( QAM_TOP_CONSTELLATION_QAM64 + 1 ) - * ( QAM_TOP_CONSTELLATION_QAM64 + 1 ); - break; - case DRX_CONSTELLATION_QAM256: - /* a(16 bit) * b(5 bit) = 21 bit result => Mult32 not needed */ - qamVdPeriod = qamVdBitCnt * ( QAM_TOP_CONSTELLATION_QAM256 + 1 ) - * ( QAM_TOP_CONSTELLATION_QAM256 + 1 ); - break; - default: - return (DRX_STS_INVALID_ARG); - } - CHK_ZERO (qamVdPeriod); - qamVdPeriod = fecBitsDesired / qamVdPeriod; - /* limit to max 16 bit value (I2C register width) if needed */ - if ( qamVdPeriod > 0xFFFF ) - qamVdPeriod = 0xFFFF; - - /* a(16 bit) * b(16 bit) = 32 bit result => Mult32 not needed */ - qamVdBitCnt *= qamVdPeriod; - - WR16 ( devAddr, QAM_VD_MEASUREMENT_PERIOD__A , ( u16_t ) qamVdPeriod ); - WR16 ( devAddr, QAM_VD_MEASUREMENT_PRESCALE__A , qamVdPrescale ); - extAttr->qamVdPeriod = (u16_t) qamVdPeriod; - extAttr->qamVdPrescale = qamVdPrescale; - } - - return (DRX_STS_OK); +SetQAMMeasurement(pDRXDemodInstance_t demod, + DRXConstellation_t constellation, u32_t symbolRate) +{ + pI2CDeviceAddr_t devAddr = NULL; /* device address for I2C writes */ + pDRXJData_t extAttr = NULL; /* Global data container for DRXJ specif data */ + u32_t fecBitsDesired = 0; /* BER accounting period */ + u16_t fecRsPlen = 0; /* defines RS BER measurement period */ + u16_t fecRsPrescale = 0; /* ReedSolomon Measurement Prescale */ + u32_t fecRsPeriod = 0; /* Value for corresponding I2C register */ + u32_t fecRsBitCnt = 0; /* Actual precise amount of bits */ + u32_t fecOcSncFailPeriod = 0; /* Value for corresponding I2C register */ + u32_t qamVdPeriod = 0; /* Value for corresponding I2C register */ + u32_t qamVdBitCnt = 0; /* Actual precise amount of bits */ + u16_t fecVdPlen = 0; /* no of trellis symbols: VD SER measur period */ + u16_t qamVdPrescale = 0; /* Viterbi Measurement Prescale */ + + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; + + fecBitsDesired = extAttr->fecBitsDesired; + fecRsPrescale = extAttr->fecRsPrescale; + + switch (constellation) { + case DRX_CONSTELLATION_QAM16: + fecBitsDesired = 4 * symbolRate; + break; + case DRX_CONSTELLATION_QAM32: + fecBitsDesired = 5 * symbolRate; + break; + case DRX_CONSTELLATION_QAM64: + fecBitsDesired = 6 * symbolRate; + break; + case DRX_CONSTELLATION_QAM128: + fecBitsDesired = 7 * symbolRate; + break; + case DRX_CONSTELLATION_QAM256: + fecBitsDesired = 8 * symbolRate; + break; + default: + return (DRX_STS_INVALID_ARG); + } + + /* Parameters for Reed-Solomon Decoder */ + /* fecrs_period = (int)ceil(FEC_BITS_DESIRED/(fecrs_prescale*plen)) */ + /* rs_bit_cnt = fecrs_period*fecrs_prescale*plen */ + /* result is within 32 bit arithmetic -> */ + /* no need for mult or frac functions */ + + /* TODO: use constant instead of calculation and remove the fecRsPlen in extAttr */ + switch (extAttr->standard) { + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_C: + fecRsPlen = 204 * 8; + break; + case DRX_STANDARD_ITU_B: + fecRsPlen = 128 * 7; + break; + default: + return (DRX_STS_INVALID_ARG); + } + + extAttr->fecRsPlen = fecRsPlen; /* for getSigQual */ + fecRsBitCnt = fecRsPrescale * fecRsPlen; /* temp storage */ + CHK_ZERO(fecRsBitCnt); + fecRsPeriod = fecBitsDesired / fecRsBitCnt + 1; /* ceil */ + if (extAttr->standard != DRX_STANDARD_ITU_B) + fecOcSncFailPeriod = fecRsPeriod; + + /* limit to max 16 bit value (I2C register width) if needed */ + if (fecRsPeriod > 0xFFFF) + fecRsPeriod = 0xFFFF; + + /* write corresponding registers */ + switch (extAttr->standard) { + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_C: + break; + case DRX_STANDARD_ITU_B: + switch (constellation) { + case DRX_CONSTELLATION_QAM64: + fecRsPeriod = 31581; + fecOcSncFailPeriod = 17932; + break; + case DRX_CONSTELLATION_QAM256: + fecRsPeriod = 45446; + fecOcSncFailPeriod = 25805; + break; + default: + return (DRX_STS_INVALID_ARG); + } + break; + default: + return (DRX_STS_INVALID_ARG); + } + + WR16(devAddr, FEC_OC_SNC_FAIL_PERIOD__A, (u16_t) fecOcSncFailPeriod); + WR16(devAddr, FEC_RS_MEASUREMENT_PERIOD__A, (u16_t) fecRsPeriod); + WR16(devAddr, FEC_RS_MEASUREMENT_PRESCALE__A, fecRsPrescale); + extAttr->fecRsPeriod = (u16_t) fecRsPeriod; + extAttr->fecRsPrescale = fecRsPrescale; + WR32(devAddr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0); + WR16(devAddr, SCU_RAM_FEC_MEAS_COUNT__A, 0); + WR16(devAddr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0); + + if (extAttr->standard == DRX_STANDARD_ITU_B) { + /* Parameters for Viterbi Decoder */ + /* qamvd_period = (int)ceil(FEC_BITS_DESIRED/ */ + /* (qamvd_prescale*plen*(qam_constellation+1))) */ + /* vd_bit_cnt = qamvd_period*qamvd_prescale*plen */ + /* result is within 32 bit arithmetic -> */ + /* no need for mult or frac functions */ + + /* a(8 bit) * b(8 bit) = 16 bit result => Mult32 not needed */ + fecVdPlen = extAttr->fecVdPlen; + qamVdPrescale = extAttr->qamVdPrescale; + qamVdBitCnt = qamVdPrescale * fecVdPlen; /* temp storage */ + + switch (constellation) { + case DRX_CONSTELLATION_QAM64: + /* a(16 bit) * b(4 bit) = 20 bit result => Mult32 not needed */ + qamVdPeriod = + qamVdBitCnt * (QAM_TOP_CONSTELLATION_QAM64 + 1) + * (QAM_TOP_CONSTELLATION_QAM64 + 1); + break; + case DRX_CONSTELLATION_QAM256: + /* a(16 bit) * b(5 bit) = 21 bit result => Mult32 not needed */ + qamVdPeriod = + qamVdBitCnt * (QAM_TOP_CONSTELLATION_QAM256 + 1) + * (QAM_TOP_CONSTELLATION_QAM256 + 1); + break; + default: + return (DRX_STS_INVALID_ARG); + } + CHK_ZERO(qamVdPeriod); + qamVdPeriod = fecBitsDesired / qamVdPeriod; + /* limit to max 16 bit value (I2C register width) if needed */ + if (qamVdPeriod > 0xFFFF) + qamVdPeriod = 0xFFFF; + + /* a(16 bit) * b(16 bit) = 32 bit result => Mult32 not needed */ + qamVdBitCnt *= qamVdPeriod; + + WR16(devAddr, QAM_VD_MEASUREMENT_PERIOD__A, + (u16_t) qamVdPeriod); + WR16(devAddr, QAM_VD_MEASUREMENT_PRESCALE__A, qamVdPrescale); + extAttr->qamVdPeriod = (u16_t) qamVdPeriod; + extAttr->qamVdPrescale = qamVdPrescale; + } + + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /*============================================================================*/ @@ -6846,75 +6543,76 @@ rw_error: * \param demod instance of demod. * \return DRXStatus_t. */ -static DRXStatus_t -SetQAM16 ( pDRXDemodInstance_t demod ) -{ - pI2CDeviceAddr_t devAddr = demod -> myI2CDevAddr; - const u8_t qamDqQualFun[]= { - DRXJ_16TO8( 2 ), /* fun0 */ - DRXJ_16TO8( 2 ), /* fun1 */ - DRXJ_16TO8( 2 ), /* fun2 */ - DRXJ_16TO8( 2 ), /* fun3 */ - DRXJ_16TO8( 3 ), /* fun4 */ - DRXJ_16TO8( 3 ), /* fun5 */ - }; - const u8_t qamEqCmaRad[]= { - DRXJ_16TO8( 13517 ), /* RAD0 */ - DRXJ_16TO8( 13517 ), /* RAD1 */ - DRXJ_16TO8( 13517 ), /* RAD2 */ - DRXJ_16TO8( 13517 ), /* RAD3 */ - DRXJ_16TO8( 13517 ), /* RAD4 */ - DRXJ_16TO8( 13517 ), /* RAD5 */ - }; - - WRB ( devAddr, QAM_DQ_QUAL_FUN0__A, sizeof(qamDqQualFun), ((pu8_t)qamDqQualFun) ); - WRB ( devAddr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qamEqCmaRad), ((pu8_t)qamEqCmaRad) ); - - WR16 ( devAddr, SCU_RAM_QAM_FSM_RTH__A, 140); - WR16 ( devAddr, SCU_RAM_QAM_FSM_FTH__A, 50); - WR16 ( devAddr, SCU_RAM_QAM_FSM_PTH__A, 120); - WR16 ( devAddr, SCU_RAM_QAM_FSM_QTH__A, 230); - WR16 ( devAddr, SCU_RAM_QAM_FSM_CTH__A, 95); - WR16 ( devAddr, SCU_RAM_QAM_FSM_MTH__A, 105); - - WR16 ( devAddr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); - WR16 ( devAddr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56); - WR16 ( devAddr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3); - - WR16 ( devAddr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 16 ); - WR16 ( devAddr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 220); - WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 25 ); - WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 6 ); - WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16_t)(-24) ); - WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16_t)(-65)); - WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16_t)(-127)); - - WR16 ( devAddr, SCU_RAM_QAM_LC_CA_FINE__A, 15); - WR16 ( devAddr, SCU_RAM_QAM_LC_CA_COARSE__A, 40); - WR16 ( devAddr, SCU_RAM_QAM_LC_CP_FINE__A, 2); - WR16 ( devAddr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20); - WR16 ( devAddr, SCU_RAM_QAM_LC_CP_COARSE__A, 255); - WR16 ( devAddr, SCU_RAM_QAM_LC_CI_FINE__A, 2); - WR16 ( devAddr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10); - WR16 ( devAddr, SCU_RAM_QAM_LC_CI_COARSE__A, 50); - WR16 ( devAddr, SCU_RAM_QAM_LC_EP_FINE__A, 12); - WR16 ( devAddr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); - WR16 ( devAddr, SCU_RAM_QAM_LC_EP_COARSE__A, 24); - WR16 ( devAddr, SCU_RAM_QAM_LC_EI_FINE__A, 12); - WR16 ( devAddr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); - WR16 ( devAddr, SCU_RAM_QAM_LC_EI_COARSE__A, 16); - WR16 ( devAddr, SCU_RAM_QAM_LC_CF_FINE__A, 16); - WR16 ( devAddr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32); - WR16 ( devAddr, SCU_RAM_QAM_LC_CF_COARSE__A, 240); - WR16 ( devAddr, SCU_RAM_QAM_LC_CF1_FINE__A, 5); - WR16 ( devAddr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15); - WR16 ( devAddr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32); - - WR16 ( devAddr, SCU_RAM_QAM_SL_SIG_POWER__A, 40960); - - return (DRX_STS_OK); +static DRXStatus_t SetQAM16(pDRXDemodInstance_t demod) +{ + pI2CDeviceAddr_t devAddr = demod->myI2CDevAddr; + const u8_t qamDqQualFun[] = { + DRXJ_16TO8(2), /* fun0 */ + DRXJ_16TO8(2), /* fun1 */ + DRXJ_16TO8(2), /* fun2 */ + DRXJ_16TO8(2), /* fun3 */ + DRXJ_16TO8(3), /* fun4 */ + DRXJ_16TO8(3), /* fun5 */ + }; + const u8_t qamEqCmaRad[] = { + DRXJ_16TO8(13517), /* RAD0 */ + DRXJ_16TO8(13517), /* RAD1 */ + DRXJ_16TO8(13517), /* RAD2 */ + DRXJ_16TO8(13517), /* RAD3 */ + DRXJ_16TO8(13517), /* RAD4 */ + DRXJ_16TO8(13517), /* RAD5 */ + }; + + WRB(devAddr, QAM_DQ_QUAL_FUN0__A, sizeof(qamDqQualFun), + ((pu8_t) qamDqQualFun)); + WRB(devAddr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qamEqCmaRad), + ((pu8_t) qamEqCmaRad)); + + WR16(devAddr, SCU_RAM_QAM_FSM_RTH__A, 140); + WR16(devAddr, SCU_RAM_QAM_FSM_FTH__A, 50); + WR16(devAddr, SCU_RAM_QAM_FSM_PTH__A, 120); + WR16(devAddr, SCU_RAM_QAM_FSM_QTH__A, 230); + WR16(devAddr, SCU_RAM_QAM_FSM_CTH__A, 95); + WR16(devAddr, SCU_RAM_QAM_FSM_MTH__A, 105); + + WR16(devAddr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); + WR16(devAddr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56); + WR16(devAddr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3); + + WR16(devAddr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 16); + WR16(devAddr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 220); + WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 25); + WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 6); + WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16_t) (-24)); + WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16_t) (-65)); + WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16_t) (-127)); + + WR16(devAddr, SCU_RAM_QAM_LC_CA_FINE__A, 15); + WR16(devAddr, SCU_RAM_QAM_LC_CA_COARSE__A, 40); + WR16(devAddr, SCU_RAM_QAM_LC_CP_FINE__A, 2); + WR16(devAddr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20); + WR16(devAddr, SCU_RAM_QAM_LC_CP_COARSE__A, 255); + WR16(devAddr, SCU_RAM_QAM_LC_CI_FINE__A, 2); + WR16(devAddr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10); + WR16(devAddr, SCU_RAM_QAM_LC_CI_COARSE__A, 50); + WR16(devAddr, SCU_RAM_QAM_LC_EP_FINE__A, 12); + WR16(devAddr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); + WR16(devAddr, SCU_RAM_QAM_LC_EP_COARSE__A, 24); + WR16(devAddr, SCU_RAM_QAM_LC_EI_FINE__A, 12); + WR16(devAddr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); + WR16(devAddr, SCU_RAM_QAM_LC_EI_COARSE__A, 16); + WR16(devAddr, SCU_RAM_QAM_LC_CF_FINE__A, 16); + WR16(devAddr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32); + WR16(devAddr, SCU_RAM_QAM_LC_CF_COARSE__A, 240); + WR16(devAddr, SCU_RAM_QAM_LC_CF1_FINE__A, 5); + WR16(devAddr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15); + WR16(devAddr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32); + + WR16(devAddr, SCU_RAM_QAM_SL_SIG_POWER__A, 40960); + + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /*============================================================================*/ @@ -6925,75 +6623,76 @@ rw_error: * \param demod instance of demod. * \return DRXStatus_t. */ -static DRXStatus_t -SetQAM32 ( pDRXDemodInstance_t demod ) -{ - pI2CDeviceAddr_t devAddr = demod -> myI2CDevAddr; - const u8_t qamDqQualFun[]= { - DRXJ_16TO8( 3 ), /* fun0 */ - DRXJ_16TO8( 3 ), /* fun1 */ - DRXJ_16TO8( 3 ), /* fun2 */ - DRXJ_16TO8( 3 ), /* fun3 */ - DRXJ_16TO8( 4 ), /* fun4 */ - DRXJ_16TO8( 4 ), /* fun5 */ - }; - const u8_t qamEqCmaRad[]= { - DRXJ_16TO8( 6707 ), /* RAD0 */ - DRXJ_16TO8( 6707 ), /* RAD1 */ - DRXJ_16TO8( 6707 ), /* RAD2 */ - DRXJ_16TO8( 6707 ), /* RAD3 */ - DRXJ_16TO8( 6707 ), /* RAD4 */ - DRXJ_16TO8( 6707 ), /* RAD5 */ - }; - - WRB ( devAddr, QAM_DQ_QUAL_FUN0__A, sizeof(qamDqQualFun), ((pu8_t)qamDqQualFun) ); - WRB ( devAddr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qamEqCmaRad), ((pu8_t)qamEqCmaRad) ); - - WR16 ( devAddr, SCU_RAM_QAM_FSM_RTH__A, 90); - WR16 ( devAddr, SCU_RAM_QAM_FSM_FTH__A, 50); - WR16 ( devAddr, SCU_RAM_QAM_FSM_PTH__A, 100); - WR16 ( devAddr, SCU_RAM_QAM_FSM_QTH__A, 170); - WR16 ( devAddr, SCU_RAM_QAM_FSM_CTH__A, 80); - WR16 ( devAddr, SCU_RAM_QAM_FSM_MTH__A, 100); - - WR16 ( devAddr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); - WR16 ( devAddr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56); - WR16 ( devAddr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3); - - WR16 ( devAddr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12 ); - WR16 ( devAddr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 140); - WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16_t)(-8) ); - WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16_t)(-16) ); - WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16_t)(-26) ); - WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16_t)(-56)); - WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16_t)(-86)); - - WR16 ( devAddr, SCU_RAM_QAM_LC_CA_FINE__A, 15); - WR16 ( devAddr, SCU_RAM_QAM_LC_CA_COARSE__A, 40); - WR16 ( devAddr, SCU_RAM_QAM_LC_CP_FINE__A, 2); - WR16 ( devAddr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20); - WR16 ( devAddr, SCU_RAM_QAM_LC_CP_COARSE__A, 255); - WR16 ( devAddr, SCU_RAM_QAM_LC_CI_FINE__A, 2); - WR16 ( devAddr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10); - WR16 ( devAddr, SCU_RAM_QAM_LC_CI_COARSE__A, 50); - WR16 ( devAddr, SCU_RAM_QAM_LC_EP_FINE__A, 12); - WR16 ( devAddr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); - WR16 ( devAddr, SCU_RAM_QAM_LC_EP_COARSE__A, 24); - WR16 ( devAddr, SCU_RAM_QAM_LC_EI_FINE__A, 12); - WR16 ( devAddr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); - WR16 ( devAddr, SCU_RAM_QAM_LC_EI_COARSE__A, 16); - WR16 ( devAddr, SCU_RAM_QAM_LC_CF_FINE__A, 16); - WR16 ( devAddr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32); - WR16 ( devAddr, SCU_RAM_QAM_LC_CF_COARSE__A, 176); - WR16 ( devAddr, SCU_RAM_QAM_LC_CF1_FINE__A, 5); - WR16 ( devAddr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15); - WR16 ( devAddr, SCU_RAM_QAM_LC_CF1_COARSE__A, 8); - - WR16 ( devAddr, SCU_RAM_QAM_SL_SIG_POWER__A, 20480); - - return (DRX_STS_OK); +static DRXStatus_t SetQAM32(pDRXDemodInstance_t demod) +{ + pI2CDeviceAddr_t devAddr = demod->myI2CDevAddr; + const u8_t qamDqQualFun[] = { + DRXJ_16TO8(3), /* fun0 */ + DRXJ_16TO8(3), /* fun1 */ + DRXJ_16TO8(3), /* fun2 */ + DRXJ_16TO8(3), /* fun3 */ + DRXJ_16TO8(4), /* fun4 */ + DRXJ_16TO8(4), /* fun5 */ + }; + const u8_t qamEqCmaRad[] = { + DRXJ_16TO8(6707), /* RAD0 */ + DRXJ_16TO8(6707), /* RAD1 */ + DRXJ_16TO8(6707), /* RAD2 */ + DRXJ_16TO8(6707), /* RAD3 */ + DRXJ_16TO8(6707), /* RAD4 */ + DRXJ_16TO8(6707), /* RAD5 */ + }; + + WRB(devAddr, QAM_DQ_QUAL_FUN0__A, sizeof(qamDqQualFun), + ((pu8_t) qamDqQualFun)); + WRB(devAddr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qamEqCmaRad), + ((pu8_t) qamEqCmaRad)); + + WR16(devAddr, SCU_RAM_QAM_FSM_RTH__A, 90); + WR16(devAddr, SCU_RAM_QAM_FSM_FTH__A, 50); + WR16(devAddr, SCU_RAM_QAM_FSM_PTH__A, 100); + WR16(devAddr, SCU_RAM_QAM_FSM_QTH__A, 170); + WR16(devAddr, SCU_RAM_QAM_FSM_CTH__A, 80); + WR16(devAddr, SCU_RAM_QAM_FSM_MTH__A, 100); + + WR16(devAddr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); + WR16(devAddr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56); + WR16(devAddr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3); + + WR16(devAddr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12); + WR16(devAddr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 140); + WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16_t) (-8)); + WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16_t) (-16)); + WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16_t) (-26)); + WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16_t) (-56)); + WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16_t) (-86)); + + WR16(devAddr, SCU_RAM_QAM_LC_CA_FINE__A, 15); + WR16(devAddr, SCU_RAM_QAM_LC_CA_COARSE__A, 40); + WR16(devAddr, SCU_RAM_QAM_LC_CP_FINE__A, 2); + WR16(devAddr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20); + WR16(devAddr, SCU_RAM_QAM_LC_CP_COARSE__A, 255); + WR16(devAddr, SCU_RAM_QAM_LC_CI_FINE__A, 2); + WR16(devAddr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10); + WR16(devAddr, SCU_RAM_QAM_LC_CI_COARSE__A, 50); + WR16(devAddr, SCU_RAM_QAM_LC_EP_FINE__A, 12); + WR16(devAddr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); + WR16(devAddr, SCU_RAM_QAM_LC_EP_COARSE__A, 24); + WR16(devAddr, SCU_RAM_QAM_LC_EI_FINE__A, 12); + WR16(devAddr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); + WR16(devAddr, SCU_RAM_QAM_LC_EI_COARSE__A, 16); + WR16(devAddr, SCU_RAM_QAM_LC_CF_FINE__A, 16); + WR16(devAddr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32); + WR16(devAddr, SCU_RAM_QAM_LC_CF_COARSE__A, 176); + WR16(devAddr, SCU_RAM_QAM_LC_CF1_FINE__A, 5); + WR16(devAddr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15); + WR16(devAddr, SCU_RAM_QAM_LC_CF1_COARSE__A, 8); + + WR16(devAddr, SCU_RAM_QAM_SL_SIG_POWER__A, 20480); + + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /*============================================================================*/ @@ -7004,75 +6703,76 @@ rw_error: * \param demod instance of demod. * \return DRXStatus_t. */ -static DRXStatus_t -SetQAM64 ( pDRXDemodInstance_t demod ) -{ - pI2CDeviceAddr_t devAddr = demod -> myI2CDevAddr; - const u8_t qamDqQualFun[]= { /* this is hw reset value. no necessary to re-write */ - DRXJ_16TO8( 4 ), /* fun0 */ - DRXJ_16TO8( 4 ), /* fun1 */ - DRXJ_16TO8( 4 ), /* fun2 */ - DRXJ_16TO8( 4 ), /* fun3 */ - DRXJ_16TO8( 6 ), /* fun4 */ - DRXJ_16TO8( 6 ), /* fun5 */ - }; - const u8_t qamEqCmaRad[]= { - DRXJ_16TO8( 13336 ), /* RAD0 */ - DRXJ_16TO8( 12618 ), /* RAD1 */ - DRXJ_16TO8( 11988 ), /* RAD2 */ - DRXJ_16TO8( 13809 ), /* RAD3 */ - DRXJ_16TO8( 13809 ), /* RAD4 */ - DRXJ_16TO8( 15609 ), /* RAD5 */ - }; - - WRB ( devAddr, QAM_DQ_QUAL_FUN0__A, sizeof(qamDqQualFun), ((pu8_t)qamDqQualFun) ); - WRB ( devAddr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qamEqCmaRad), ((pu8_t)qamEqCmaRad) ); - - WR16 ( devAddr, SCU_RAM_QAM_FSM_RTH__A, 105); - WR16 ( devAddr, SCU_RAM_QAM_FSM_FTH__A, 60); - WR16 ( devAddr, SCU_RAM_QAM_FSM_PTH__A, 100); - WR16 ( devAddr, SCU_RAM_QAM_FSM_QTH__A, 195); - WR16 ( devAddr, SCU_RAM_QAM_FSM_CTH__A, 80); - WR16 ( devAddr, SCU_RAM_QAM_FSM_MTH__A, 84); - - WR16 ( devAddr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); - WR16 ( devAddr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32); - WR16 ( devAddr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3); - - WR16 ( devAddr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12 ); - WR16 ( devAddr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 141); - WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 7 ); - WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 0 ); - WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16_t)(-15)); - WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16_t)(-45)); - WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16_t)(-80)); - - WR16 ( devAddr, SCU_RAM_QAM_LC_CA_FINE__A, 15); - WR16 ( devAddr, SCU_RAM_QAM_LC_CA_COARSE__A, 40); - WR16 ( devAddr, SCU_RAM_QAM_LC_CP_FINE__A, 2); - WR16 ( devAddr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30); - WR16 ( devAddr, SCU_RAM_QAM_LC_CP_COARSE__A, 255); - WR16 ( devAddr, SCU_RAM_QAM_LC_CI_FINE__A, 2); - WR16 ( devAddr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 15); - WR16 ( devAddr, SCU_RAM_QAM_LC_CI_COARSE__A, 80); - WR16 ( devAddr, SCU_RAM_QAM_LC_EP_FINE__A, 12); - WR16 ( devAddr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); - WR16 ( devAddr, SCU_RAM_QAM_LC_EP_COARSE__A, 24); - WR16 ( devAddr, SCU_RAM_QAM_LC_EI_FINE__A, 12); - WR16 ( devAddr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); - WR16 ( devAddr, SCU_RAM_QAM_LC_EI_COARSE__A, 16); - WR16 ( devAddr, SCU_RAM_QAM_LC_CF_FINE__A, 16); - WR16 ( devAddr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48); - WR16 ( devAddr, SCU_RAM_QAM_LC_CF_COARSE__A, 160); - WR16 ( devAddr, SCU_RAM_QAM_LC_CF1_FINE__A, 5); - WR16 ( devAddr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15); - WR16 ( devAddr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32); - - WR16 ( devAddr, SCU_RAM_QAM_SL_SIG_POWER__A, 43008); - - return (DRX_STS_OK); +static DRXStatus_t SetQAM64(pDRXDemodInstance_t demod) +{ + pI2CDeviceAddr_t devAddr = demod->myI2CDevAddr; + const u8_t qamDqQualFun[] = { /* this is hw reset value. no necessary to re-write */ + DRXJ_16TO8(4), /* fun0 */ + DRXJ_16TO8(4), /* fun1 */ + DRXJ_16TO8(4), /* fun2 */ + DRXJ_16TO8(4), /* fun3 */ + DRXJ_16TO8(6), /* fun4 */ + DRXJ_16TO8(6), /* fun5 */ + }; + const u8_t qamEqCmaRad[] = { + DRXJ_16TO8(13336), /* RAD0 */ + DRXJ_16TO8(12618), /* RAD1 */ + DRXJ_16TO8(11988), /* RAD2 */ + DRXJ_16TO8(13809), /* RAD3 */ + DRXJ_16TO8(13809), /* RAD4 */ + DRXJ_16TO8(15609), /* RAD5 */ + }; + + WRB(devAddr, QAM_DQ_QUAL_FUN0__A, sizeof(qamDqQualFun), + ((pu8_t) qamDqQualFun)); + WRB(devAddr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qamEqCmaRad), + ((pu8_t) qamEqCmaRad)); + + WR16(devAddr, SCU_RAM_QAM_FSM_RTH__A, 105); + WR16(devAddr, SCU_RAM_QAM_FSM_FTH__A, 60); + WR16(devAddr, SCU_RAM_QAM_FSM_PTH__A, 100); + WR16(devAddr, SCU_RAM_QAM_FSM_QTH__A, 195); + WR16(devAddr, SCU_RAM_QAM_FSM_CTH__A, 80); + WR16(devAddr, SCU_RAM_QAM_FSM_MTH__A, 84); + + WR16(devAddr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); + WR16(devAddr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32); + WR16(devAddr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3); + + WR16(devAddr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12); + WR16(devAddr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 141); + WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 7); + WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 0); + WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16_t) (-15)); + WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16_t) (-45)); + WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16_t) (-80)); + + WR16(devAddr, SCU_RAM_QAM_LC_CA_FINE__A, 15); + WR16(devAddr, SCU_RAM_QAM_LC_CA_COARSE__A, 40); + WR16(devAddr, SCU_RAM_QAM_LC_CP_FINE__A, 2); + WR16(devAddr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30); + WR16(devAddr, SCU_RAM_QAM_LC_CP_COARSE__A, 255); + WR16(devAddr, SCU_RAM_QAM_LC_CI_FINE__A, 2); + WR16(devAddr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 15); + WR16(devAddr, SCU_RAM_QAM_LC_CI_COARSE__A, 80); + WR16(devAddr, SCU_RAM_QAM_LC_EP_FINE__A, 12); + WR16(devAddr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); + WR16(devAddr, SCU_RAM_QAM_LC_EP_COARSE__A, 24); + WR16(devAddr, SCU_RAM_QAM_LC_EI_FINE__A, 12); + WR16(devAddr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); + WR16(devAddr, SCU_RAM_QAM_LC_EI_COARSE__A, 16); + WR16(devAddr, SCU_RAM_QAM_LC_CF_FINE__A, 16); + WR16(devAddr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48); + WR16(devAddr, SCU_RAM_QAM_LC_CF_COARSE__A, 160); + WR16(devAddr, SCU_RAM_QAM_LC_CF1_FINE__A, 5); + WR16(devAddr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15); + WR16(devAddr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32); + + WR16(devAddr, SCU_RAM_QAM_SL_SIG_POWER__A, 43008); + + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /*============================================================================*/ @@ -7083,75 +6783,76 @@ rw_error: * \param demod: instance of demod. * \return DRXStatus_t. */ -static DRXStatus_t -SetQAM128( pDRXDemodInstance_t demod ) -{ - pI2CDeviceAddr_t devAddr = demod -> myI2CDevAddr; - const u8_t qamDqQualFun[]= { - DRXJ_16TO8( 6 ), /* fun0 */ - DRXJ_16TO8( 6 ), /* fun1 */ - DRXJ_16TO8( 6 ), /* fun2 */ - DRXJ_16TO8( 6 ), /* fun3 */ - DRXJ_16TO8( 9 ), /* fun4 */ - DRXJ_16TO8( 9 ), /* fun5 */ - }; - const u8_t qamEqCmaRad[]= { - DRXJ_16TO8( 6164 ), /* RAD0 */ - DRXJ_16TO8( 6598 ), /* RAD1 */ - DRXJ_16TO8( 6394 ), /* RAD2 */ - DRXJ_16TO8( 6409 ), /* RAD3 */ - DRXJ_16TO8( 6656 ), /* RAD4 */ - DRXJ_16TO8( 7238 ), /* RAD5 */ - }; - - WRB ( devAddr, QAM_DQ_QUAL_FUN0__A, sizeof(qamDqQualFun), ((pu8_t)qamDqQualFun) ); - WRB ( devAddr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qamEqCmaRad), ((pu8_t)qamEqCmaRad) ); - - WR16 ( devAddr, SCU_RAM_QAM_FSM_RTH__A, 50); - WR16 ( devAddr, SCU_RAM_QAM_FSM_FTH__A, 60); - WR16 ( devAddr, SCU_RAM_QAM_FSM_PTH__A, 100); - WR16 ( devAddr, SCU_RAM_QAM_FSM_QTH__A, 140); - WR16 ( devAddr, SCU_RAM_QAM_FSM_CTH__A, 80); - WR16 ( devAddr, SCU_RAM_QAM_FSM_MTH__A, 100); - - WR16 ( devAddr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); - WR16 ( devAddr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32); - WR16 ( devAddr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3); - - WR16 ( devAddr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8 ); - WR16 ( devAddr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 65 ); - WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 5 ); - WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 3 ); - WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16_t)(-1) ); - WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 12); - WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16_t)(-23)); - - WR16 ( devAddr, SCU_RAM_QAM_LC_CA_FINE__A, 15); - WR16 ( devAddr, SCU_RAM_QAM_LC_CA_COARSE__A, 40); - WR16 ( devAddr, SCU_RAM_QAM_LC_CP_FINE__A, 2); - WR16 ( devAddr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40); - WR16 ( devAddr, SCU_RAM_QAM_LC_CP_COARSE__A, 255); - WR16 ( devAddr, SCU_RAM_QAM_LC_CI_FINE__A, 2); - WR16 ( devAddr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20); - WR16 ( devAddr, SCU_RAM_QAM_LC_CI_COARSE__A, 80); - WR16 ( devAddr, SCU_RAM_QAM_LC_EP_FINE__A, 12); - WR16 ( devAddr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); - WR16 ( devAddr, SCU_RAM_QAM_LC_EP_COARSE__A, 24); - WR16 ( devAddr, SCU_RAM_QAM_LC_EI_FINE__A, 12); - WR16 ( devAddr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); - WR16 ( devAddr, SCU_RAM_QAM_LC_EI_COARSE__A, 16); - WR16 ( devAddr, SCU_RAM_QAM_LC_CF_FINE__A, 16); - WR16 ( devAddr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32); - WR16 ( devAddr, SCU_RAM_QAM_LC_CF_COARSE__A, 144); - WR16 ( devAddr, SCU_RAM_QAM_LC_CF1_FINE__A, 5); - WR16 ( devAddr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15); - WR16 ( devAddr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16); - - WR16 ( devAddr, SCU_RAM_QAM_SL_SIG_POWER__A, 20992); - - return (DRX_STS_OK); +static DRXStatus_t SetQAM128(pDRXDemodInstance_t demod) +{ + pI2CDeviceAddr_t devAddr = demod->myI2CDevAddr; + const u8_t qamDqQualFun[] = { + DRXJ_16TO8(6), /* fun0 */ + DRXJ_16TO8(6), /* fun1 */ + DRXJ_16TO8(6), /* fun2 */ + DRXJ_16TO8(6), /* fun3 */ + DRXJ_16TO8(9), /* fun4 */ + DRXJ_16TO8(9), /* fun5 */ + }; + const u8_t qamEqCmaRad[] = { + DRXJ_16TO8(6164), /* RAD0 */ + DRXJ_16TO8(6598), /* RAD1 */ + DRXJ_16TO8(6394), /* RAD2 */ + DRXJ_16TO8(6409), /* RAD3 */ + DRXJ_16TO8(6656), /* RAD4 */ + DRXJ_16TO8(7238), /* RAD5 */ + }; + + WRB(devAddr, QAM_DQ_QUAL_FUN0__A, sizeof(qamDqQualFun), + ((pu8_t) qamDqQualFun)); + WRB(devAddr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qamEqCmaRad), + ((pu8_t) qamEqCmaRad)); + + WR16(devAddr, SCU_RAM_QAM_FSM_RTH__A, 50); + WR16(devAddr, SCU_RAM_QAM_FSM_FTH__A, 60); + WR16(devAddr, SCU_RAM_QAM_FSM_PTH__A, 100); + WR16(devAddr, SCU_RAM_QAM_FSM_QTH__A, 140); + WR16(devAddr, SCU_RAM_QAM_FSM_CTH__A, 80); + WR16(devAddr, SCU_RAM_QAM_FSM_MTH__A, 100); + + WR16(devAddr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); + WR16(devAddr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32); + WR16(devAddr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3); + + WR16(devAddr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8); + WR16(devAddr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 65); + WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 5); + WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 3); + WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16_t) (-1)); + WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 12); + WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16_t) (-23)); + + WR16(devAddr, SCU_RAM_QAM_LC_CA_FINE__A, 15); + WR16(devAddr, SCU_RAM_QAM_LC_CA_COARSE__A, 40); + WR16(devAddr, SCU_RAM_QAM_LC_CP_FINE__A, 2); + WR16(devAddr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40); + WR16(devAddr, SCU_RAM_QAM_LC_CP_COARSE__A, 255); + WR16(devAddr, SCU_RAM_QAM_LC_CI_FINE__A, 2); + WR16(devAddr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20); + WR16(devAddr, SCU_RAM_QAM_LC_CI_COARSE__A, 80); + WR16(devAddr, SCU_RAM_QAM_LC_EP_FINE__A, 12); + WR16(devAddr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); + WR16(devAddr, SCU_RAM_QAM_LC_EP_COARSE__A, 24); + WR16(devAddr, SCU_RAM_QAM_LC_EI_FINE__A, 12); + WR16(devAddr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); + WR16(devAddr, SCU_RAM_QAM_LC_EI_COARSE__A, 16); + WR16(devAddr, SCU_RAM_QAM_LC_CF_FINE__A, 16); + WR16(devAddr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32); + WR16(devAddr, SCU_RAM_QAM_LC_CF_COARSE__A, 144); + WR16(devAddr, SCU_RAM_QAM_LC_CF1_FINE__A, 5); + WR16(devAddr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15); + WR16(devAddr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16); + + WR16(devAddr, SCU_RAM_QAM_SL_SIG_POWER__A, 20992); + + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /*============================================================================*/ @@ -7162,75 +6863,76 @@ rw_error: * \param demod: instance of demod. * \return DRXStatus_t. */ -static DRXStatus_t -SetQAM256( pDRXDemodInstance_t demod ) -{ - pI2CDeviceAddr_t devAddr = demod -> myI2CDevAddr; - const u8_t qamDqQualFun[]= { - DRXJ_16TO8( 8 ), /* fun0 */ - DRXJ_16TO8( 8 ), /* fun1 */ - DRXJ_16TO8( 8 ), /* fun2 */ - DRXJ_16TO8( 8 ), /* fun3 */ - DRXJ_16TO8( 12 ), /* fun4 */ - DRXJ_16TO8( 12 ), /* fun5 */ - }; - const u8_t qamEqCmaRad[]= { - DRXJ_16TO8( 12345 ), /* RAD0 */ - DRXJ_16TO8( 12345 ), /* RAD1 */ - DRXJ_16TO8( 13626 ), /* RAD2 */ - DRXJ_16TO8( 12931 ), /* RAD3 */ - DRXJ_16TO8( 14719 ), /* RAD4 */ - DRXJ_16TO8( 15356 ), /* RAD5 */ - }; - - WRB ( devAddr, QAM_DQ_QUAL_FUN0__A, sizeof(qamDqQualFun), ((pu8_t)qamDqQualFun) ); - WRB ( devAddr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qamEqCmaRad), ((pu8_t)qamEqCmaRad) ); - - WR16 ( devAddr, SCU_RAM_QAM_FSM_RTH__A, 50); - WR16 ( devAddr, SCU_RAM_QAM_FSM_FTH__A, 60); - WR16 ( devAddr, SCU_RAM_QAM_FSM_PTH__A, 100); - WR16 ( devAddr, SCU_RAM_QAM_FSM_QTH__A, 150); - WR16 ( devAddr, SCU_RAM_QAM_FSM_CTH__A, 80); - WR16 ( devAddr, SCU_RAM_QAM_FSM_MTH__A, 110); - - WR16 ( devAddr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); - WR16 ( devAddr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 16); - WR16 ( devAddr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3); - - WR16 ( devAddr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8); - WR16 ( devAddr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 74); - WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 18); - WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 13); - WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, 7); - WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 0); - WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16_t)(-8)); - - WR16 ( devAddr, SCU_RAM_QAM_LC_CA_FINE__A, 15); - WR16 ( devAddr, SCU_RAM_QAM_LC_CA_COARSE__A, 40); - WR16 ( devAddr, SCU_RAM_QAM_LC_CP_FINE__A, 2); - WR16 ( devAddr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50); - WR16 ( devAddr, SCU_RAM_QAM_LC_CP_COARSE__A, 255); - WR16 ( devAddr, SCU_RAM_QAM_LC_CI_FINE__A, 2); - WR16 ( devAddr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 25); - WR16 ( devAddr, SCU_RAM_QAM_LC_CI_COARSE__A, 80); - WR16 ( devAddr, SCU_RAM_QAM_LC_EP_FINE__A, 12); - WR16 ( devAddr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); - WR16 ( devAddr, SCU_RAM_QAM_LC_EP_COARSE__A, 24); - WR16 ( devAddr, SCU_RAM_QAM_LC_EI_FINE__A, 12); - WR16 ( devAddr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); - WR16 ( devAddr, SCU_RAM_QAM_LC_EI_COARSE__A, 16); - WR16 ( devAddr, SCU_RAM_QAM_LC_CF_FINE__A, 16); - WR16 ( devAddr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48); - WR16 ( devAddr, SCU_RAM_QAM_LC_CF_COARSE__A, 80); - WR16 ( devAddr, SCU_RAM_QAM_LC_CF1_FINE__A, 5); - WR16 ( devAddr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15); - WR16 ( devAddr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16); - - WR16 ( devAddr, SCU_RAM_QAM_SL_SIG_POWER__A, 43520); - - return (DRX_STS_OK); +static DRXStatus_t SetQAM256(pDRXDemodInstance_t demod) +{ + pI2CDeviceAddr_t devAddr = demod->myI2CDevAddr; + const u8_t qamDqQualFun[] = { + DRXJ_16TO8(8), /* fun0 */ + DRXJ_16TO8(8), /* fun1 */ + DRXJ_16TO8(8), /* fun2 */ + DRXJ_16TO8(8), /* fun3 */ + DRXJ_16TO8(12), /* fun4 */ + DRXJ_16TO8(12), /* fun5 */ + }; + const u8_t qamEqCmaRad[] = { + DRXJ_16TO8(12345), /* RAD0 */ + DRXJ_16TO8(12345), /* RAD1 */ + DRXJ_16TO8(13626), /* RAD2 */ + DRXJ_16TO8(12931), /* RAD3 */ + DRXJ_16TO8(14719), /* RAD4 */ + DRXJ_16TO8(15356), /* RAD5 */ + }; + + WRB(devAddr, QAM_DQ_QUAL_FUN0__A, sizeof(qamDqQualFun), + ((pu8_t) qamDqQualFun)); + WRB(devAddr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qamEqCmaRad), + ((pu8_t) qamEqCmaRad)); + + WR16(devAddr, SCU_RAM_QAM_FSM_RTH__A, 50); + WR16(devAddr, SCU_RAM_QAM_FSM_FTH__A, 60); + WR16(devAddr, SCU_RAM_QAM_FSM_PTH__A, 100); + WR16(devAddr, SCU_RAM_QAM_FSM_QTH__A, 150); + WR16(devAddr, SCU_RAM_QAM_FSM_CTH__A, 80); + WR16(devAddr, SCU_RAM_QAM_FSM_MTH__A, 110); + + WR16(devAddr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); + WR16(devAddr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 16); + WR16(devAddr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3); + + WR16(devAddr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8); + WR16(devAddr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 74); + WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 18); + WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 13); + WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, 7); + WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 0); + WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16_t) (-8)); + + WR16(devAddr, SCU_RAM_QAM_LC_CA_FINE__A, 15); + WR16(devAddr, SCU_RAM_QAM_LC_CA_COARSE__A, 40); + WR16(devAddr, SCU_RAM_QAM_LC_CP_FINE__A, 2); + WR16(devAddr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50); + WR16(devAddr, SCU_RAM_QAM_LC_CP_COARSE__A, 255); + WR16(devAddr, SCU_RAM_QAM_LC_CI_FINE__A, 2); + WR16(devAddr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 25); + WR16(devAddr, SCU_RAM_QAM_LC_CI_COARSE__A, 80); + WR16(devAddr, SCU_RAM_QAM_LC_EP_FINE__A, 12); + WR16(devAddr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); + WR16(devAddr, SCU_RAM_QAM_LC_EP_COARSE__A, 24); + WR16(devAddr, SCU_RAM_QAM_LC_EI_FINE__A, 12); + WR16(devAddr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); + WR16(devAddr, SCU_RAM_QAM_LC_EI_COARSE__A, 16); + WR16(devAddr, SCU_RAM_QAM_LC_CF_FINE__A, 16); + WR16(devAddr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48); + WR16(devAddr, SCU_RAM_QAM_LC_CF_COARSE__A, 80); + WR16(devAddr, SCU_RAM_QAM_LC_CF1_FINE__A, 5); + WR16(devAddr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15); + WR16(devAddr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16); + + WR16(devAddr, SCU_RAM_QAM_SL_SIG_POWER__A, 43520); + + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /*============================================================================*/ @@ -7246,566 +6948,550 @@ rw_error: * \return DRXStatus_t. */ static DRXStatus_t -SetQAM( pDRXDemodInstance_t demod, - pDRXChannel_t channel, - DRXFrequency_t tunerFreqOffset, - u32_t op - ) -{ - pI2CDeviceAddr_t devAddr = NULL; - pDRXJData_t extAttr = NULL; - pDRXCommonAttr_t commonAttr = NULL; - u16_t cmdResult = 0; - u32_t adcFrequency = 0; - u32_t iqmRcRate = 0; - u16_t lcSymbolFreq = 0; - u16_t iqmRcStretch = 0; - u16_t setEnvParameters = 0; - u16_t setParamParameters[2] = {0}; - DRXJSCUCmd_t cmdSCU = { /* command */ 0, - /* parameterLen */ 0, - /* resultLen */ 0, - /* parameter */ NULL, - /* result */ NULL }; - const u8_t qamA_taps[]= { - DRXJ_16TO8( -1 ), /* re0 */ - DRXJ_16TO8( 1 ), /* re1 */ - DRXJ_16TO8( 1 ), /* re2 */ - DRXJ_16TO8( -1 ), /* re3 */ - DRXJ_16TO8( -1 ), /* re4 */ - DRXJ_16TO8( 2 ), /* re5 */ - DRXJ_16TO8( 1 ), /* re6 */ - DRXJ_16TO8( -2 ), /* re7 */ - DRXJ_16TO8( 0 ), /* re8 */ - DRXJ_16TO8( 3 ), /* re9 */ - DRXJ_16TO8( -1 ), /* re10 */ - DRXJ_16TO8( -3 ), /* re11 */ - DRXJ_16TO8( 4 ), /* re12 */ - DRXJ_16TO8( 1 ), /* re13 */ - DRXJ_16TO8( -8 ), /* re14 */ - DRXJ_16TO8( 4 ), /* re15 */ - DRXJ_16TO8( 13 ), /* re16 */ - DRXJ_16TO8( -13 ), /* re17 */ - DRXJ_16TO8( -19 ), /* re18 */ - DRXJ_16TO8( 28 ), /* re19 */ - DRXJ_16TO8( 25 ), /* re20 */ - DRXJ_16TO8( -53 ), /* re21 */ - DRXJ_16TO8( -31 ), /* re22 */ - DRXJ_16TO8( 96 ), /* re23 */ - DRXJ_16TO8( 37 ), /* re24 */ - DRXJ_16TO8( -190 ), /* re25 */ - DRXJ_16TO8( -40 ), /* re26 */ - DRXJ_16TO8( 619 ) /* re27 */ - }; - const u8_t qamB64_taps[]= { - DRXJ_16TO8( 0 ), /* re0 */ - DRXJ_16TO8( -2 ), /* re1 */ - DRXJ_16TO8( 1 ), /* re2 */ - DRXJ_16TO8( 2 ), /* re3 */ - DRXJ_16TO8( -2 ), /* re4 */ - DRXJ_16TO8( 0 ), /* re5 */ - DRXJ_16TO8( 4 ), /* re6 */ - DRXJ_16TO8( -2 ), /* re7 */ - DRXJ_16TO8( -4 ), /* re8 */ - DRXJ_16TO8( 4 ), /* re9 */ - DRXJ_16TO8( 3 ), /* re10 */ - DRXJ_16TO8( -6 ), /* re11 */ - DRXJ_16TO8( 0 ), /* re12 */ - DRXJ_16TO8( 6 ), /* re13 */ - DRXJ_16TO8( -5 ), /* re14 */ - DRXJ_16TO8( -3 ), /* re15 */ - DRXJ_16TO8( 11 ), /* re16 */ - DRXJ_16TO8( -4 ), /* re17 */ - DRXJ_16TO8( -19 ), /* re18 */ - DRXJ_16TO8( 19 ), /* re19 */ - DRXJ_16TO8( 28 ), /* re20 */ - DRXJ_16TO8( -45 ), /* re21 */ - DRXJ_16TO8( -36 ), /* re22 */ - DRXJ_16TO8( 90 ), /* re23 */ - DRXJ_16TO8( 42 ), /* re24 */ - DRXJ_16TO8( -185 ), /* re25 */ - DRXJ_16TO8( -46 ), /* re26 */ - DRXJ_16TO8( 614 ) /* re27 */ - }; - const u8_t qamB256_taps[]= { - DRXJ_16TO8( -2 ), /* re0 */ - DRXJ_16TO8( 4 ), /* re1 */ - DRXJ_16TO8( 1 ), /* re2 */ - DRXJ_16TO8( -4 ), /* re3 */ - DRXJ_16TO8( 0 ), /* re4 */ - DRXJ_16TO8( 4 ), /* re5 */ - DRXJ_16TO8( -2 ), /* re6 */ - DRXJ_16TO8( -4 ), /* re7 */ - DRXJ_16TO8( 5 ), /* re8 */ - DRXJ_16TO8( 2 ), /* re9 */ - DRXJ_16TO8( -8 ), /* re10 */ - DRXJ_16TO8( 2 ), /* re11 */ - DRXJ_16TO8( 11 ), /* re12 */ - DRXJ_16TO8( -8 ), /* re13 */ - DRXJ_16TO8( -15 ), /* re14 */ - DRXJ_16TO8( 16 ), /* re15 */ - DRXJ_16TO8( 19 ), /* re16 */ - DRXJ_16TO8( -27 ), /* re17 */ - DRXJ_16TO8( -22 ), /* re18 */ - DRXJ_16TO8( 44 ), /* re19 */ - DRXJ_16TO8( 26 ), /* re20 */ - DRXJ_16TO8( -69 ), /* re21 */ - DRXJ_16TO8( -28 ), /* re22 */ - DRXJ_16TO8( 110 ), /* re23 */ - DRXJ_16TO8( 31 ), /* re24 */ - DRXJ_16TO8( -201 ), /* re25 */ - DRXJ_16TO8( -32 ), /* re26 */ - DRXJ_16TO8( 628 ) /* re27 */ - }; - const u8_t qamC_taps[]= { - DRXJ_16TO8( -3 ), /* re0 */ - DRXJ_16TO8( 3 ), /* re1 */ - DRXJ_16TO8( 2 ), /* re2 */ - DRXJ_16TO8( -4 ), /* re3 */ - DRXJ_16TO8( 0 ), /* re4 */ - DRXJ_16TO8( 4 ), /* re5 */ - DRXJ_16TO8( -1 ), /* re6 */ - DRXJ_16TO8( -4 ), /* re7 */ - DRXJ_16TO8( 3 ), /* re8 */ - DRXJ_16TO8( 3 ), /* re9 */ - DRXJ_16TO8( -5 ), /* re10 */ - DRXJ_16TO8( 0 ), /* re11 */ - DRXJ_16TO8( 9 ), /* re12 */ - DRXJ_16TO8( -4 ), /* re13 */ - DRXJ_16TO8( -12 ), /* re14 */ - DRXJ_16TO8( 10 ), /* re15 */ - DRXJ_16TO8( 16 ), /* re16 */ - DRXJ_16TO8( -21 ), /* re17 */ - DRXJ_16TO8( -20 ), /* re18 */ - DRXJ_16TO8( 37 ), /* re19 */ - DRXJ_16TO8( 25 ), /* re20 */ - DRXJ_16TO8( -62 ), /* re21 */ - DRXJ_16TO8( -28 ), /* re22 */ - DRXJ_16TO8( 105 ), /* re23 */ - DRXJ_16TO8( 31 ), /* re24 */ - DRXJ_16TO8( -197 ), /* re25 */ - DRXJ_16TO8( -33 ), /* re26 */ - DRXJ_16TO8( 626 ) /* re27 */ - }; - - devAddr = demod -> myI2CDevAddr; - extAttr = (pDRXJData_t)demod -> myExtAttr; - commonAttr = (pDRXCommonAttr_t) demod -> myCommonAttr; - - if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION )) - { - if ( extAttr->standard == DRX_STANDARD_ITU_B ) - { - switch ( channel->constellation ) - { - case DRX_CONSTELLATION_QAM256 : - iqmRcRate = 0x00AE3562; - lcSymbolFreq = QAM_LC_SYMBOL_FREQ_FREQ_QAM_B_256; - channel->symbolrate = 5360537; - iqmRcStretch = IQM_RC_STRETCH_QAM_B_256; - break; - case DRX_CONSTELLATION_QAM64 : - iqmRcRate = 0x00C05A0E; - lcSymbolFreq = 409; - channel->symbolrate = 5056941; - iqmRcStretch = IQM_RC_STRETCH_QAM_B_64; - break; - default : - return (DRX_STS_INVALID_ARG); - } - } - else - { - adcFrequency = ( commonAttr->sysClockFreq * 1000 ) / 3; - CHK_ZERO (channel->symbolrate); - iqmRcRate = ( adcFrequency / channel->symbolrate ) * ( 1 << 21 ) + - ( Frac28 ( ( adcFrequency % channel->symbolrate ), channel->symbolrate ) >> 7 ) - ( 1 << 23 ); - lcSymbolFreq = (u16_t)( Frac28 ( channel->symbolrate + (adcFrequency >> 13), adcFrequency ) >> 16 ); - if (lcSymbolFreq > 511) - lcSymbolFreq = 511; - - iqmRcStretch = 21; - } - - if( extAttr->standard == DRX_STANDARD_ITU_A ) - { - setEnvParameters = QAM_TOP_ANNEX_A; /* annex */ - setParamParameters[0] = channel->constellation; /* constellation */ - setParamParameters[1] = DRX_INTERLEAVEMODE_I12_J17; /* interleave mode */ - } - else if( extAttr->standard == DRX_STANDARD_ITU_B ) - { - setEnvParameters = QAM_TOP_ANNEX_B; /* annex */ - setParamParameters[0] = channel->constellation; /* constellation */ - setParamParameters[1] = channel->interleavemode; /* interleave mode */ - } - else if( extAttr->standard == DRX_STANDARD_ITU_C ) - { - setEnvParameters = QAM_TOP_ANNEX_C; /* annex */ - setParamParameters[0] = channel->constellation; /* constellation */ - setParamParameters[1] = DRX_INTERLEAVEMODE_I12_J17; /* interleave mode */ - } - else - { - return (DRX_STS_INVALID_ARG); - } - } - - if (op & QAM_SET_OP_ALL) - { - /* - STEP 1: reset demodulator - resets IQM, QAM and FEC HW blocks - resets SCU variables - */ - /* stop all comm_exec */ - WR16( devAddr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP ); - WR16( devAddr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP ); - WR16( devAddr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP ); - WR16( devAddr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP ); - WR16( devAddr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP ); - WR16( devAddr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP ); - WR16( devAddr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP ); - - cmdSCU.command = SCU_RAM_COMMAND_STANDARD_QAM | - SCU_RAM_COMMAND_CMD_DEMOD_RESET; - cmdSCU.parameterLen = 0; - cmdSCU.resultLen = 1; - cmdSCU.parameter = NULL; - cmdSCU.result = &cmdResult; - CHK_ERROR( SCUCommand( devAddr, &cmdSCU ) ); - } - - if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION )) - { - /* - STEP 2: configure demodulator - -set env - -set params (resets IQM,QAM,FEC HW; initializes some SCU variables ) - */ - cmdSCU.command = SCU_RAM_COMMAND_STANDARD_QAM | - SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV; - cmdSCU.parameterLen = 1; - cmdSCU.resultLen = 1; - cmdSCU.parameter = &setEnvParameters; - cmdSCU.result = &cmdResult; - CHK_ERROR( SCUCommand( devAddr, &cmdSCU ) ); - - cmdSCU.command = SCU_RAM_COMMAND_STANDARD_QAM | - SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM; - cmdSCU.parameterLen = 2; - cmdSCU.resultLen = 1; - cmdSCU.parameter = setParamParameters; - cmdSCU.result = &cmdResult; - CHK_ERROR( SCUCommand( devAddr, &cmdSCU ) ); - /* set symbol rate */ - WR32( devAddr, IQM_RC_RATE_OFS_LO__A, iqmRcRate ); - extAttr->iqmRcRateOfs = iqmRcRate; - CHK_ERROR( SetQAMMeasurement ( demod, channel->constellation, channel->symbolrate)); - } - /* STEP 3: enable the system in a mode where the ADC provides valid signal - setup constellation independent registers */ - /* from qam_cmd.py script (qam_driver_b)*/ - /* TODO: remove re-writes of HW reset values */ - if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_SPECTRUM )) - { - CHK_ERROR ( SetFrequency ( demod, channel, tunerFreqOffset ) ); - } +SetQAM(pDRXDemodInstance_t demod, + pDRXChannel_t channel, DRXFrequency_t tunerFreqOffset, u32_t op) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + pDRXCommonAttr_t commonAttr = NULL; + u16_t cmdResult = 0; + u32_t adcFrequency = 0; + u32_t iqmRcRate = 0; + u16_t lcSymbolFreq = 0; + u16_t iqmRcStretch = 0; + u16_t setEnvParameters = 0; + u16_t setParamParameters[2] = { 0 }; + DRXJSCUCmd_t cmdSCU = { /* command */ 0, + /* parameterLen */ 0, + /* resultLen */ 0, + /* parameter */ NULL, + /* result */ NULL + }; + const u8_t qamA_taps[] = { + DRXJ_16TO8(-1), /* re0 */ + DRXJ_16TO8(1), /* re1 */ + DRXJ_16TO8(1), /* re2 */ + DRXJ_16TO8(-1), /* re3 */ + DRXJ_16TO8(-1), /* re4 */ + DRXJ_16TO8(2), /* re5 */ + DRXJ_16TO8(1), /* re6 */ + DRXJ_16TO8(-2), /* re7 */ + DRXJ_16TO8(0), /* re8 */ + DRXJ_16TO8(3), /* re9 */ + DRXJ_16TO8(-1), /* re10 */ + DRXJ_16TO8(-3), /* re11 */ + DRXJ_16TO8(4), /* re12 */ + DRXJ_16TO8(1), /* re13 */ + DRXJ_16TO8(-8), /* re14 */ + DRXJ_16TO8(4), /* re15 */ + DRXJ_16TO8(13), /* re16 */ + DRXJ_16TO8(-13), /* re17 */ + DRXJ_16TO8(-19), /* re18 */ + DRXJ_16TO8(28), /* re19 */ + DRXJ_16TO8(25), /* re20 */ + DRXJ_16TO8(-53), /* re21 */ + DRXJ_16TO8(-31), /* re22 */ + DRXJ_16TO8(96), /* re23 */ + DRXJ_16TO8(37), /* re24 */ + DRXJ_16TO8(-190), /* re25 */ + DRXJ_16TO8(-40), /* re26 */ + DRXJ_16TO8(619) /* re27 */ + }; + const u8_t qamB64_taps[] = { + DRXJ_16TO8(0), /* re0 */ + DRXJ_16TO8(-2), /* re1 */ + DRXJ_16TO8(1), /* re2 */ + DRXJ_16TO8(2), /* re3 */ + DRXJ_16TO8(-2), /* re4 */ + DRXJ_16TO8(0), /* re5 */ + DRXJ_16TO8(4), /* re6 */ + DRXJ_16TO8(-2), /* re7 */ + DRXJ_16TO8(-4), /* re8 */ + DRXJ_16TO8(4), /* re9 */ + DRXJ_16TO8(3), /* re10 */ + DRXJ_16TO8(-6), /* re11 */ + DRXJ_16TO8(0), /* re12 */ + DRXJ_16TO8(6), /* re13 */ + DRXJ_16TO8(-5), /* re14 */ + DRXJ_16TO8(-3), /* re15 */ + DRXJ_16TO8(11), /* re16 */ + DRXJ_16TO8(-4), /* re17 */ + DRXJ_16TO8(-19), /* re18 */ + DRXJ_16TO8(19), /* re19 */ + DRXJ_16TO8(28), /* re20 */ + DRXJ_16TO8(-45), /* re21 */ + DRXJ_16TO8(-36), /* re22 */ + DRXJ_16TO8(90), /* re23 */ + DRXJ_16TO8(42), /* re24 */ + DRXJ_16TO8(-185), /* re25 */ + DRXJ_16TO8(-46), /* re26 */ + DRXJ_16TO8(614) /* re27 */ + }; + const u8_t qamB256_taps[] = { + DRXJ_16TO8(-2), /* re0 */ + DRXJ_16TO8(4), /* re1 */ + DRXJ_16TO8(1), /* re2 */ + DRXJ_16TO8(-4), /* re3 */ + DRXJ_16TO8(0), /* re4 */ + DRXJ_16TO8(4), /* re5 */ + DRXJ_16TO8(-2), /* re6 */ + DRXJ_16TO8(-4), /* re7 */ + DRXJ_16TO8(5), /* re8 */ + DRXJ_16TO8(2), /* re9 */ + DRXJ_16TO8(-8), /* re10 */ + DRXJ_16TO8(2), /* re11 */ + DRXJ_16TO8(11), /* re12 */ + DRXJ_16TO8(-8), /* re13 */ + DRXJ_16TO8(-15), /* re14 */ + DRXJ_16TO8(16), /* re15 */ + DRXJ_16TO8(19), /* re16 */ + DRXJ_16TO8(-27), /* re17 */ + DRXJ_16TO8(-22), /* re18 */ + DRXJ_16TO8(44), /* re19 */ + DRXJ_16TO8(26), /* re20 */ + DRXJ_16TO8(-69), /* re21 */ + DRXJ_16TO8(-28), /* re22 */ + DRXJ_16TO8(110), /* re23 */ + DRXJ_16TO8(31), /* re24 */ + DRXJ_16TO8(-201), /* re25 */ + DRXJ_16TO8(-32), /* re26 */ + DRXJ_16TO8(628) /* re27 */ + }; + const u8_t qamC_taps[] = { + DRXJ_16TO8(-3), /* re0 */ + DRXJ_16TO8(3), /* re1 */ + DRXJ_16TO8(2), /* re2 */ + DRXJ_16TO8(-4), /* re3 */ + DRXJ_16TO8(0), /* re4 */ + DRXJ_16TO8(4), /* re5 */ + DRXJ_16TO8(-1), /* re6 */ + DRXJ_16TO8(-4), /* re7 */ + DRXJ_16TO8(3), /* re8 */ + DRXJ_16TO8(3), /* re9 */ + DRXJ_16TO8(-5), /* re10 */ + DRXJ_16TO8(0), /* re11 */ + DRXJ_16TO8(9), /* re12 */ + DRXJ_16TO8(-4), /* re13 */ + DRXJ_16TO8(-12), /* re14 */ + DRXJ_16TO8(10), /* re15 */ + DRXJ_16TO8(16), /* re16 */ + DRXJ_16TO8(-21), /* re17 */ + DRXJ_16TO8(-20), /* re18 */ + DRXJ_16TO8(37), /* re19 */ + DRXJ_16TO8(25), /* re20 */ + DRXJ_16TO8(-62), /* re21 */ + DRXJ_16TO8(-28), /* re22 */ + DRXJ_16TO8(105), /* re23 */ + DRXJ_16TO8(31), /* re24 */ + DRXJ_16TO8(-197), /* re25 */ + DRXJ_16TO8(-33), /* re26 */ + DRXJ_16TO8(626) /* re27 */ + }; + + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; + commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; + + if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) { + if (extAttr->standard == DRX_STANDARD_ITU_B) { + switch (channel->constellation) { + case DRX_CONSTELLATION_QAM256: + iqmRcRate = 0x00AE3562; + lcSymbolFreq = + QAM_LC_SYMBOL_FREQ_FREQ_QAM_B_256; + channel->symbolrate = 5360537; + iqmRcStretch = IQM_RC_STRETCH_QAM_B_256; + break; + case DRX_CONSTELLATION_QAM64: + iqmRcRate = 0x00C05A0E; + lcSymbolFreq = 409; + channel->symbolrate = 5056941; + iqmRcStretch = IQM_RC_STRETCH_QAM_B_64; + break; + default: + return (DRX_STS_INVALID_ARG); + } + } else { + adcFrequency = (commonAttr->sysClockFreq * 1000) / 3; + CHK_ZERO(channel->symbolrate); + iqmRcRate = + (adcFrequency / channel->symbolrate) * (1 << 21) + + (Frac28 + ((adcFrequency % channel->symbolrate), + channel->symbolrate) >> 7) - (1 << 23); + lcSymbolFreq = + (u16_t) (Frac28 + (channel->symbolrate + + (adcFrequency >> 13), + adcFrequency) >> 16); + if (lcSymbolFreq > 511) + lcSymbolFreq = 511; + + iqmRcStretch = 21; + } + + if (extAttr->standard == DRX_STANDARD_ITU_A) { + setEnvParameters = QAM_TOP_ANNEX_A; /* annex */ + setParamParameters[0] = channel->constellation; /* constellation */ + setParamParameters[1] = DRX_INTERLEAVEMODE_I12_J17; /* interleave mode */ + } else if (extAttr->standard == DRX_STANDARD_ITU_B) { + setEnvParameters = QAM_TOP_ANNEX_B; /* annex */ + setParamParameters[0] = channel->constellation; /* constellation */ + setParamParameters[1] = channel->interleavemode; /* interleave mode */ + } else if (extAttr->standard == DRX_STANDARD_ITU_C) { + setEnvParameters = QAM_TOP_ANNEX_C; /* annex */ + setParamParameters[0] = channel->constellation; /* constellation */ + setParamParameters[1] = DRX_INTERLEAVEMODE_I12_J17; /* interleave mode */ + } else { + return (DRX_STS_INVALID_ARG); + } + } - if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION )) - { + if (op & QAM_SET_OP_ALL) { + /* + STEP 1: reset demodulator + resets IQM, QAM and FEC HW blocks + resets SCU variables + */ + /* stop all comm_exec */ + WR16(devAddr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP); + WR16(devAddr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP); + WR16(devAddr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP); + WR16(devAddr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP); + WR16(devAddr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP); + WR16(devAddr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP); + WR16(devAddr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP); + + cmdSCU.command = SCU_RAM_COMMAND_STANDARD_QAM | + SCU_RAM_COMMAND_CMD_DEMOD_RESET; + cmdSCU.parameterLen = 0; + cmdSCU.resultLen = 1; + cmdSCU.parameter = NULL; + cmdSCU.result = &cmdResult; + CHK_ERROR(SCUCommand(devAddr, &cmdSCU)); + } - WR16( devAddr, QAM_LC_SYMBOL_FREQ__A, lcSymbolFreq); - WR16( devAddr, IQM_RC_STRETCH__A, iqmRcStretch ); - } + if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) { + /* + STEP 2: configure demodulator + -set env + -set params (resets IQM,QAM,FEC HW; initializes some SCU variables ) + */ + cmdSCU.command = SCU_RAM_COMMAND_STANDARD_QAM | + SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV; + cmdSCU.parameterLen = 1; + cmdSCU.resultLen = 1; + cmdSCU.parameter = &setEnvParameters; + cmdSCU.result = &cmdResult; + CHK_ERROR(SCUCommand(devAddr, &cmdSCU)); + + cmdSCU.command = SCU_RAM_COMMAND_STANDARD_QAM | + SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM; + cmdSCU.parameterLen = 2; + cmdSCU.resultLen = 1; + cmdSCU.parameter = setParamParameters; + cmdSCU.result = &cmdResult; + CHK_ERROR(SCUCommand(devAddr, &cmdSCU)); + /* set symbol rate */ + WR32(devAddr, IQM_RC_RATE_OFS_LO__A, iqmRcRate); + extAttr->iqmRcRateOfs = iqmRcRate; + CHK_ERROR(SetQAMMeasurement + (demod, channel->constellation, channel->symbolrate)); + } + /* STEP 3: enable the system in a mode where the ADC provides valid signal + setup constellation independent registers */ + /* from qam_cmd.py script (qam_driver_b) */ + /* TODO: remove re-writes of HW reset values */ + if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_SPECTRUM)) { + CHK_ERROR(SetFrequency(demod, channel, tunerFreqOffset)); + } - if (op & QAM_SET_OP_ALL) - { - if (extAttr->hasLNA==FALSE) - { - WR16( devAddr, IQM_AF_AMUX__A, 0x02); - } - WR16( devAddr, IQM_CF_SYMMETRIC__A, 0 ); - WR16( devAddr, IQM_CF_MIDTAP__A, 3 ); - WR16( devAddr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_QAM__M ); - - WR16( devAddr, SCU_RAM_QAM_WR_RSV_0__A, 0x5f); /* scu temporary shut down agc */ - - WR16( devAddr, IQM_AF_SYNC_SEL__A, 3); - WR16( devAddr, IQM_AF_CLP_LEN__A, 0); - WR16( devAddr, IQM_AF_CLP_TH__A, 448); - WR16( devAddr, IQM_AF_SNS_LEN__A, 0); - WR16( devAddr, IQM_AF_PDREF__A, 4); - WR16( devAddr, IQM_AF_STDBY__A, 0x10); - WR16( devAddr, IQM_AF_PGA_GAIN__A, 11); - - WR16( devAddr, IQM_CF_POW_MEAS_LEN__A, 1); - WR16( devAddr, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE); /*! reset default val ! */ - - WR16( devAddr, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE); /*! reset default val ! */ - if( extAttr->standard == DRX_STANDARD_ITU_B ) - { - WR16( devAddr, QAM_SY_SYNC_LWM__A, QAM_SY_SYNC_LWM__PRE); /*! reset default val ! */ - WR16( devAddr, QAM_SY_SYNC_AWM__A, QAM_SY_SYNC_AWM__PRE); /*! reset default val ! */ - WR16( devAddr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE); /*! reset default val ! */ - } - else - { - switch ( channel->constellation ) { - case DRX_CONSTELLATION_QAM16: - case DRX_CONSTELLATION_QAM64: - case DRX_CONSTELLATION_QAM256: - WR16( devAddr, QAM_SY_SYNC_LWM__A, 0x03); - WR16( devAddr, QAM_SY_SYNC_AWM__A, 0x04); - WR16( devAddr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE); /*! reset default val ! */ - break; - case DRX_CONSTELLATION_QAM32: - case DRX_CONSTELLATION_QAM128: - WR16( devAddr, QAM_SY_SYNC_LWM__A, 0x03); - WR16( devAddr, QAM_SY_SYNC_AWM__A, 0x05); - WR16( devAddr, QAM_SY_SYNC_HWM__A, 0x06); - break; - default: - return (DRX_STS_ERROR); - } /* switch */ - } - - WR16( devAddr, QAM_LC_MODE__A, QAM_LC_MODE__PRE); /*! reset default val ! */ - WR16( devAddr, QAM_LC_RATE_LIMIT__A, 3); - WR16( devAddr, QAM_LC_LPF_FACTORP__A, 4); - WR16( devAddr, QAM_LC_LPF_FACTORI__A, 4); - WR16( devAddr, QAM_LC_MODE__A, 7); - WR16( devAddr, QAM_LC_QUAL_TAB0__A, 1); - WR16( devAddr, QAM_LC_QUAL_TAB1__A, 1); - WR16( devAddr, QAM_LC_QUAL_TAB2__A, 1); - WR16( devAddr, QAM_LC_QUAL_TAB3__A, 1); - WR16( devAddr, QAM_LC_QUAL_TAB4__A, 2); - WR16( devAddr, QAM_LC_QUAL_TAB5__A, 2); - WR16( devAddr, QAM_LC_QUAL_TAB6__A, 2); - WR16( devAddr, QAM_LC_QUAL_TAB8__A, 2); - WR16( devAddr, QAM_LC_QUAL_TAB9__A, 2); - WR16( devAddr, QAM_LC_QUAL_TAB10__A, 2); - WR16( devAddr, QAM_LC_QUAL_TAB12__A, 2); - WR16( devAddr, QAM_LC_QUAL_TAB15__A, 3); - WR16( devAddr, QAM_LC_QUAL_TAB16__A, 3); - WR16( devAddr, QAM_LC_QUAL_TAB20__A, 4); - WR16( devAddr, QAM_LC_QUAL_TAB25__A, 4); - - WR16( devAddr, IQM_FS_ADJ_SEL__A, 1); - WR16( devAddr, IQM_RC_ADJ_SEL__A, 1); - WR16( devAddr, IQM_CF_ADJ_SEL__A, 1); - WR16( devAddr, IQM_CF_POW_MEAS_LEN__A, 0); - WR16( devAddr, SCU_RAM_GPIO__A, 0 ); - - /* No more resets of the IQM, current standard correctly set => - now AGCs can be configured. */ - /* turn on IQMAF. It has to be in front of setAgc**() */ - CHK_ERROR( SetIqmAf( demod, TRUE ) ); - CHK_ERROR(ADCSynchronization (demod)); - - CHK_ERROR( InitAGC( demod ) ); - CHK_ERROR( SetAgcIf( demod, &(extAttr->qamIfAgcCfg), FALSE ) ); - CHK_ERROR( SetAgcRf( demod, &(extAttr->qamRfAgcCfg), FALSE ) ); - { - /* TODO fix this, store a DRXJCfgAfeGain_t structure in DRXJData_t instead - of only the gain */ - DRXJCfgAfeGain_t qamPgaCfg = { DRX_STANDARD_ITU_B, 0 }; - - qamPgaCfg.gain = extAttr->qamPgaCfg; - CHK_ERROR( CtrlSetCfgAfeGain( demod, &qamPgaCfg ) ); - } - CHK_ERROR( CtrlSetCfgPreSaw( demod, &(extAttr->qamPreSawCfg)) ); - } - - if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION )) - { - if( extAttr->standard == DRX_STANDARD_ITU_A ) - { - WRB ( devAddr, IQM_CF_TAP_RE0__A, sizeof(qamA_taps), ((pu8_t)qamA_taps) ); - WRB ( devAddr, IQM_CF_TAP_IM0__A, sizeof(qamA_taps), ((pu8_t)qamA_taps) ); - } - else if ( extAttr->standard == DRX_STANDARD_ITU_B ) - { - switch ( channel->constellation ) { - case DRX_CONSTELLATION_QAM64: - WRB ( devAddr, IQM_CF_TAP_RE0__A, sizeof(qamB64_taps), ((pu8_t)qamB64_taps) ); - WRB ( devAddr, IQM_CF_TAP_IM0__A, sizeof(qamB64_taps), ((pu8_t)qamB64_taps) ); - break; - case DRX_CONSTELLATION_QAM256: - WRB ( devAddr, IQM_CF_TAP_RE0__A, sizeof(qamB256_taps), ((pu8_t)qamB256_taps) ); - WRB ( devAddr, IQM_CF_TAP_IM0__A, sizeof(qamB256_taps), ((pu8_t)qamB256_taps) ); - break; - default: - return (DRX_STS_ERROR); - } - } - else if ( extAttr->standard == DRX_STANDARD_ITU_C ) - { - WRB ( devAddr, IQM_CF_TAP_RE0__A, sizeof(qamC_taps), ((pu8_t)qamC_taps) ); - WRB ( devAddr, IQM_CF_TAP_IM0__A, sizeof(qamC_taps), ((pu8_t)qamC_taps) ); - } - - /* SETP 4: constellation specific setup */ - switch ( channel->constellation ) { - case DRX_CONSTELLATION_QAM16: - CHK_ERROR(SetQAM16( demod )); - break; - case DRX_CONSTELLATION_QAM32: - CHK_ERROR(SetQAM32( demod )); - break; - case DRX_CONSTELLATION_QAM64: - CHK_ERROR(SetQAM64( demod )); - break; - case DRX_CONSTELLATION_QAM128: - CHK_ERROR(SetQAM128( demod )); - break; - case DRX_CONSTELLATION_QAM256: - CHK_ERROR(SetQAM256( demod )); - break; - default: - return (DRX_STS_ERROR); - } /* switch */ - } - - if ((op & QAM_SET_OP_ALL)) - { - WR16(devAddr, IQM_CF_SCALE_SH__A, 0 ); - - /* Mpeg output has to be in front of FEC active */ - CHK_ERROR ( SetMPEGTEIHandling( demod )); - CHK_ERROR ( BitReverseMPEGOutput( demod ) ); - CHK_ERROR ( SetMPEGStartWidth ( demod ) ); - { - /* TODO: move to setStandard after hardware reset value problem is solved */ - /* Configure initial MPEG output */ - DRXCfgMPEGOutput_t cfgMPEGOutput; - - cfgMPEGOutput.enableMPEGOutput = TRUE; - cfgMPEGOutput.insertRSByte = commonAttr->mpegCfg.insertRSByte; - cfgMPEGOutput.enableParallel = commonAttr->mpegCfg.enableParallel; - cfgMPEGOutput.invertDATA = commonAttr->mpegCfg.invertDATA; - cfgMPEGOutput.invertERR = commonAttr->mpegCfg.invertERR; - cfgMPEGOutput.invertSTR = commonAttr->mpegCfg.invertSTR; - cfgMPEGOutput.invertVAL = commonAttr->mpegCfg.invertVAL; - cfgMPEGOutput.invertCLK = commonAttr->mpegCfg.invertCLK; - cfgMPEGOutput.staticCLK = commonAttr->mpegCfg.staticCLK; - cfgMPEGOutput.bitrate = commonAttr->mpegCfg.bitrate; - CHK_ERROR( CtrlSetCfgMPEGOutput( demod, &cfgMPEGOutput) ); - } - } - - if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION )) - { + if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) { - /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */ - cmdSCU.command = SCU_RAM_COMMAND_STANDARD_QAM | - SCU_RAM_COMMAND_CMD_DEMOD_START; - cmdSCU.parameterLen = 0; - cmdSCU.resultLen = 1; - cmdSCU.parameter = NULL; - cmdSCU.result = &cmdResult; - CHK_ERROR( SCUCommand( devAddr, &cmdSCU ) ); - } - - WR16(devAddr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE ); - WR16(devAddr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE ); - WR16(devAddr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE ); - - return (DRX_STS_OK); -rw_error: - return (DRX_STS_ERROR); -} + WR16(devAddr, QAM_LC_SYMBOL_FREQ__A, lcSymbolFreq); + WR16(devAddr, IQM_RC_STRETCH__A, iqmRcStretch); + } -/*============================================================================*/ -static DRXStatus_t -CtrlGetQAMSigQuality( pDRXDemodInstance_t demod, - pDRXSigQuality_t sigQuality ); -static DRXStatus_t -qamFlipSpec ( pDRXDemodInstance_t demod, - pDRXChannel_t channel) -{ - u32_t iqmFsRateOfs = 0; - u32_t iqmFsRateLo = 0; - u16_t qamCtlEna = 0; - u16_t data = 0; - u16_t equMode = 0; - u16_t fsmState = 0; - int i = 0; - int ofsofs = 0; - pI2CDeviceAddr_t devAddr = NULL; - pDRXJData_t extAttr = NULL; - - devAddr = demod -> myI2CDevAddr; - extAttr = (pDRXJData_t)demod->myExtAttr; - - /* Silence the controlling of lc, equ, and the acquisition state machine */ - RR16( devAddr, SCU_RAM_QAM_CTL_ENA__A, &qamCtlEna ); - WR16( devAddr, SCU_RAM_QAM_CTL_ENA__A, qamCtlEna - & ~ ( SCU_RAM_QAM_CTL_ENA_ACQ__M - | SCU_RAM_QAM_CTL_ENA_EQU__M - | SCU_RAM_QAM_CTL_ENA_LC__M) ); - - /* freeze the frequency control loop */ - WR16( devAddr, QAM_LC_CF__A, 0); - WR16( devAddr, QAM_LC_CF1__A, 0); - - ARR32( devAddr, IQM_FS_RATE_OFS_LO__A , &iqmFsRateOfs ); - ARR32( devAddr, IQM_FS_RATE_LO__A, &iqmFsRateLo ); - ofsofs = iqmFsRateLo - iqmFsRateOfs; - iqmFsRateOfs = ~iqmFsRateOfs + 1; - iqmFsRateOfs -= 2 * ofsofs; - - /* freeze dq/fq updating */ - RR16( devAddr, QAM_DQ_MODE__A, &data); - data = (data & 0xfff9); - WR16( devAddr, QAM_DQ_MODE__A, data ); - WR16( devAddr, QAM_FQ_MODE__A, data ); - - /* lc_cp / _ci / _ca */ - WR16( devAddr, QAM_LC_CI__A, 0 ); - WR16( devAddr, QAM_LC_EP__A, 0 ); - WR16( devAddr, QAM_FQ_LA_FACTOR__A, 0 ); - - /* flip the spec */ - WR32( devAddr, IQM_FS_RATE_OFS_LO__A , iqmFsRateOfs ); - extAttr->iqmFsRateOfs = iqmFsRateOfs; - extAttr->posImage = (extAttr->posImage)?FALSE:TRUE; - - /* freeze dq/fq updating */ - RR16( devAddr, QAM_DQ_MODE__A, &data); - equMode = data; - data = (data & 0xfff9); - WR16( devAddr, QAM_DQ_MODE__A, data ); - WR16( devAddr, QAM_FQ_MODE__A, data ); - - for ( i = 0; i < 28; i++) - { - RR16( devAddr, QAM_DQ_TAP_IM_EL0__A + (2 * i), &data); - WR16( devAddr, QAM_DQ_TAP_IM_EL0__A + (2 * i), -data); - } + if (op & QAM_SET_OP_ALL) { + if (extAttr->hasLNA == FALSE) { + WR16(devAddr, IQM_AF_AMUX__A, 0x02); + } + WR16(devAddr, IQM_CF_SYMMETRIC__A, 0); + WR16(devAddr, IQM_CF_MIDTAP__A, 3); + WR16(devAddr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_QAM__M); + + WR16(devAddr, SCU_RAM_QAM_WR_RSV_0__A, 0x5f); /* scu temporary shut down agc */ + + WR16(devAddr, IQM_AF_SYNC_SEL__A, 3); + WR16(devAddr, IQM_AF_CLP_LEN__A, 0); + WR16(devAddr, IQM_AF_CLP_TH__A, 448); + WR16(devAddr, IQM_AF_SNS_LEN__A, 0); + WR16(devAddr, IQM_AF_PDREF__A, 4); + WR16(devAddr, IQM_AF_STDBY__A, 0x10); + WR16(devAddr, IQM_AF_PGA_GAIN__A, 11); + + WR16(devAddr, IQM_CF_POW_MEAS_LEN__A, 1); + WR16(devAddr, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE); /*! reset default val ! */ + + WR16(devAddr, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE); /*! reset default val ! */ + if (extAttr->standard == DRX_STANDARD_ITU_B) { + WR16(devAddr, QAM_SY_SYNC_LWM__A, QAM_SY_SYNC_LWM__PRE); /*! reset default val ! */ + WR16(devAddr, QAM_SY_SYNC_AWM__A, QAM_SY_SYNC_AWM__PRE); /*! reset default val ! */ + WR16(devAddr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE); /*! reset default val ! */ + } else { + switch (channel->constellation) { + case DRX_CONSTELLATION_QAM16: + case DRX_CONSTELLATION_QAM64: + case DRX_CONSTELLATION_QAM256: + WR16(devAddr, QAM_SY_SYNC_LWM__A, 0x03); + WR16(devAddr, QAM_SY_SYNC_AWM__A, 0x04); + WR16(devAddr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE); /*! reset default val ! */ + break; + case DRX_CONSTELLATION_QAM32: + case DRX_CONSTELLATION_QAM128: + WR16(devAddr, QAM_SY_SYNC_LWM__A, 0x03); + WR16(devAddr, QAM_SY_SYNC_AWM__A, 0x05); + WR16(devAddr, QAM_SY_SYNC_HWM__A, 0x06); + break; + default: + return (DRX_STS_ERROR); + } /* switch */ + } + + WR16(devAddr, QAM_LC_MODE__A, QAM_LC_MODE__PRE); /*! reset default val ! */ + WR16(devAddr, QAM_LC_RATE_LIMIT__A, 3); + WR16(devAddr, QAM_LC_LPF_FACTORP__A, 4); + WR16(devAddr, QAM_LC_LPF_FACTORI__A, 4); + WR16(devAddr, QAM_LC_MODE__A, 7); + WR16(devAddr, QAM_LC_QUAL_TAB0__A, 1); + WR16(devAddr, QAM_LC_QUAL_TAB1__A, 1); + WR16(devAddr, QAM_LC_QUAL_TAB2__A, 1); + WR16(devAddr, QAM_LC_QUAL_TAB3__A, 1); + WR16(devAddr, QAM_LC_QUAL_TAB4__A, 2); + WR16(devAddr, QAM_LC_QUAL_TAB5__A, 2); + WR16(devAddr, QAM_LC_QUAL_TAB6__A, 2); + WR16(devAddr, QAM_LC_QUAL_TAB8__A, 2); + WR16(devAddr, QAM_LC_QUAL_TAB9__A, 2); + WR16(devAddr, QAM_LC_QUAL_TAB10__A, 2); + WR16(devAddr, QAM_LC_QUAL_TAB12__A, 2); + WR16(devAddr, QAM_LC_QUAL_TAB15__A, 3); + WR16(devAddr, QAM_LC_QUAL_TAB16__A, 3); + WR16(devAddr, QAM_LC_QUAL_TAB20__A, 4); + WR16(devAddr, QAM_LC_QUAL_TAB25__A, 4); + + WR16(devAddr, IQM_FS_ADJ_SEL__A, 1); + WR16(devAddr, IQM_RC_ADJ_SEL__A, 1); + WR16(devAddr, IQM_CF_ADJ_SEL__A, 1); + WR16(devAddr, IQM_CF_POW_MEAS_LEN__A, 0); + WR16(devAddr, SCU_RAM_GPIO__A, 0); + + /* No more resets of the IQM, current standard correctly set => + now AGCs can be configured. */ + /* turn on IQMAF. It has to be in front of setAgc**() */ + CHK_ERROR(SetIqmAf(demod, TRUE)); + CHK_ERROR(ADCSynchronization(demod)); + + CHK_ERROR(InitAGC(demod)); + CHK_ERROR(SetAgcIf(demod, &(extAttr->qamIfAgcCfg), FALSE)); + CHK_ERROR(SetAgcRf(demod, &(extAttr->qamRfAgcCfg), FALSE)); + { + /* TODO fix this, store a DRXJCfgAfeGain_t structure in DRXJData_t instead + of only the gain */ + DRXJCfgAfeGain_t qamPgaCfg = { DRX_STANDARD_ITU_B, 0 }; + + qamPgaCfg.gain = extAttr->qamPgaCfg; + CHK_ERROR(CtrlSetCfgAfeGain(demod, &qamPgaCfg)); + } + CHK_ERROR(CtrlSetCfgPreSaw(demod, &(extAttr->qamPreSawCfg))); + } - for ( i = 0; i < 24; i++) - { - RR16( devAddr, QAM_FQ_TAP_IM_EL0__A + (2 * i), &data); - WR16( devAddr, QAM_FQ_TAP_IM_EL0__A + (2 * i), -data); - } + if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) { + if (extAttr->standard == DRX_STANDARD_ITU_A) { + WRB(devAddr, IQM_CF_TAP_RE0__A, sizeof(qamA_taps), + ((pu8_t) qamA_taps)); + WRB(devAddr, IQM_CF_TAP_IM0__A, sizeof(qamA_taps), + ((pu8_t) qamA_taps)); + } else if (extAttr->standard == DRX_STANDARD_ITU_B) { + switch (channel->constellation) { + case DRX_CONSTELLATION_QAM64: + WRB(devAddr, IQM_CF_TAP_RE0__A, + sizeof(qamB64_taps), ((pu8_t) qamB64_taps)); + WRB(devAddr, IQM_CF_TAP_IM0__A, + sizeof(qamB64_taps), ((pu8_t) qamB64_taps)); + break; + case DRX_CONSTELLATION_QAM256: + WRB(devAddr, IQM_CF_TAP_RE0__A, + sizeof(qamB256_taps), + ((pu8_t) qamB256_taps)); + WRB(devAddr, IQM_CF_TAP_IM0__A, + sizeof(qamB256_taps), + ((pu8_t) qamB256_taps)); + break; + default: + return (DRX_STS_ERROR); + } + } else if (extAttr->standard == DRX_STANDARD_ITU_C) { + WRB(devAddr, IQM_CF_TAP_RE0__A, sizeof(qamC_taps), + ((pu8_t) qamC_taps)); + WRB(devAddr, IQM_CF_TAP_IM0__A, sizeof(qamC_taps), + ((pu8_t) qamC_taps)); + } + + /* SETP 4: constellation specific setup */ + switch (channel->constellation) { + case DRX_CONSTELLATION_QAM16: + CHK_ERROR(SetQAM16(demod)); + break; + case DRX_CONSTELLATION_QAM32: + CHK_ERROR(SetQAM32(demod)); + break; + case DRX_CONSTELLATION_QAM64: + CHK_ERROR(SetQAM64(demod)); + break; + case DRX_CONSTELLATION_QAM128: + CHK_ERROR(SetQAM128(demod)); + break; + case DRX_CONSTELLATION_QAM256: + CHK_ERROR(SetQAM256(demod)); + break; + default: + return (DRX_STS_ERROR); + } /* switch */ + } - data = equMode; - WR16( devAddr, QAM_DQ_MODE__A, data ); - WR16( devAddr, QAM_FQ_MODE__A, data ); + if ((op & QAM_SET_OP_ALL)) { + WR16(devAddr, IQM_CF_SCALE_SH__A, 0); + + /* Mpeg output has to be in front of FEC active */ + CHK_ERROR(SetMPEGTEIHandling(demod)); + CHK_ERROR(BitReverseMPEGOutput(demod)); + CHK_ERROR(SetMPEGStartWidth(demod)); + { + /* TODO: move to setStandard after hardware reset value problem is solved */ + /* Configure initial MPEG output */ + DRXCfgMPEGOutput_t cfgMPEGOutput; + + cfgMPEGOutput.enableMPEGOutput = TRUE; + cfgMPEGOutput.insertRSByte = + commonAttr->mpegCfg.insertRSByte; + cfgMPEGOutput.enableParallel = + commonAttr->mpegCfg.enableParallel; + cfgMPEGOutput.invertDATA = + commonAttr->mpegCfg.invertDATA; + cfgMPEGOutput.invertERR = commonAttr->mpegCfg.invertERR; + cfgMPEGOutput.invertSTR = commonAttr->mpegCfg.invertSTR; + cfgMPEGOutput.invertVAL = commonAttr->mpegCfg.invertVAL; + cfgMPEGOutput.invertCLK = commonAttr->mpegCfg.invertCLK; + cfgMPEGOutput.staticCLK = commonAttr->mpegCfg.staticCLK; + cfgMPEGOutput.bitrate = commonAttr->mpegCfg.bitrate; + CHK_ERROR(CtrlSetCfgMPEGOutput(demod, &cfgMPEGOutput)); + } + } - WR16( devAddr, SCU_RAM_QAM_FSM_STATE_TGT__A, 4 ); + if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) { - i = 0; - while ( (fsmState != 4) && (i++ < 100) ) - { - RR16( devAddr, SCU_RAM_QAM_FSM_STATE__A, &fsmState ); - } - WR16( devAddr, SCU_RAM_QAM_CTL_ENA__A, (qamCtlEna | 0x0016) ); + /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */ + cmdSCU.command = SCU_RAM_COMMAND_STANDARD_QAM | + SCU_RAM_COMMAND_CMD_DEMOD_START; + cmdSCU.parameterLen = 0; + cmdSCU.resultLen = 1; + cmdSCU.parameter = NULL; + cmdSCU.result = &cmdResult; + CHK_ERROR(SCUCommand(devAddr, &cmdSCU)); + } + + WR16(devAddr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE); + WR16(devAddr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE); + WR16(devAddr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================*/ +static DRXStatus_t +CtrlGetQAMSigQuality(pDRXDemodInstance_t demod, pDRXSigQuality_t sigQuality); +static DRXStatus_t qamFlipSpec(pDRXDemodInstance_t demod, pDRXChannel_t channel) +{ + u32_t iqmFsRateOfs = 0; + u32_t iqmFsRateLo = 0; + u16_t qamCtlEna = 0; + u16_t data = 0; + u16_t equMode = 0; + u16_t fsmState = 0; + int i = 0; + int ofsofs = 0; + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; + + /* Silence the controlling of lc, equ, and the acquisition state machine */ + RR16(devAddr, SCU_RAM_QAM_CTL_ENA__A, &qamCtlEna); + WR16(devAddr, SCU_RAM_QAM_CTL_ENA__A, qamCtlEna + & ~(SCU_RAM_QAM_CTL_ENA_ACQ__M + | SCU_RAM_QAM_CTL_ENA_EQU__M | SCU_RAM_QAM_CTL_ENA_LC__M)); + + /* freeze the frequency control loop */ + WR16(devAddr, QAM_LC_CF__A, 0); + WR16(devAddr, QAM_LC_CF1__A, 0); + + ARR32(devAddr, IQM_FS_RATE_OFS_LO__A, &iqmFsRateOfs); + ARR32(devAddr, IQM_FS_RATE_LO__A, &iqmFsRateLo); + ofsofs = iqmFsRateLo - iqmFsRateOfs; + iqmFsRateOfs = ~iqmFsRateOfs + 1; + iqmFsRateOfs -= 2 * ofsofs; + + /* freeze dq/fq updating */ + RR16(devAddr, QAM_DQ_MODE__A, &data); + data = (data & 0xfff9); + WR16(devAddr, QAM_DQ_MODE__A, data); + WR16(devAddr, QAM_FQ_MODE__A, data); + + /* lc_cp / _ci / _ca */ + WR16(devAddr, QAM_LC_CI__A, 0); + WR16(devAddr, QAM_LC_EP__A, 0); + WR16(devAddr, QAM_FQ_LA_FACTOR__A, 0); + + /* flip the spec */ + WR32(devAddr, IQM_FS_RATE_OFS_LO__A, iqmFsRateOfs); + extAttr->iqmFsRateOfs = iqmFsRateOfs; + extAttr->posImage = (extAttr->posImage) ? FALSE : TRUE; + + /* freeze dq/fq updating */ + RR16(devAddr, QAM_DQ_MODE__A, &data); + equMode = data; + data = (data & 0xfff9); + WR16(devAddr, QAM_DQ_MODE__A, data); + WR16(devAddr, QAM_FQ_MODE__A, data); + + for (i = 0; i < 28; i++) { + RR16(devAddr, QAM_DQ_TAP_IM_EL0__A + (2 * i), &data); + WR16(devAddr, QAM_DQ_TAP_IM_EL0__A + (2 * i), -data); + } + + for (i = 0; i < 24; i++) { + RR16(devAddr, QAM_FQ_TAP_IM_EL0__A + (2 * i), &data); + WR16(devAddr, QAM_FQ_TAP_IM_EL0__A + (2 * i), -data); + } + + data = equMode; + WR16(devAddr, QAM_DQ_MODE__A, data); + WR16(devAddr, QAM_FQ_MODE__A, data); + + WR16(devAddr, SCU_RAM_QAM_FSM_STATE_TGT__A, 4); - return (DRX_STS_OK); + i = 0; + while ((fsmState != 4) && (i++ < 100)) { + RR16(devAddr, SCU_RAM_QAM_FSM_STATE__A, &fsmState); + } + WR16(devAddr, SCU_RAM_QAM_CTL_ENA__A, (qamCtlEna | 0x0016)); + + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } @@ -7823,104 +7509,108 @@ rw_error: * \return DRXStatus_t. */ static DRXStatus_t -QAM64Auto( pDRXDemodInstance_t demod, - pDRXChannel_t channel, - DRXFrequency_t tunerFreqOffset, - pDRXLockStatus_t lockStatus - ) -{ - DRXSigQuality_t sigQuality; - u16_t data = 0; - u32_t state = NO_LOCK; - u32_t startTime = 0; - u32_t dLockedTime= 0; - pDRXJData_t extAttr = NULL; - u32_t timeoutOfs = 0; - - /* external attributes for storing aquired channel constellation */ - extAttr = (pDRXJData_t)demod -> myExtAttr; - *lockStatus = DRX_NOT_LOCKED; - startTime = DRXBSP_HST_Clock(); - state = NO_LOCK; - do - { - CHK_ERROR( CtrlLockStatus(demod, lockStatus) ); - - switch (state) - { - case NO_LOCK: - if ( *lockStatus == DRXJ_DEMOD_LOCK ) - { - CHK_ERROR ( CtrlGetQAMSigQuality ( demod, &sigQuality ) ); - if (sigQuality.MER > 208) - { - state = DEMOD_LOCKED; - /* some delay to see if fec_lock possible TODO find the right value */ - timeoutOfs += DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME; /* see something, waiting longer */ - dLockedTime = DRXBSP_HST_Clock(); - } - } - break; - case DEMOD_LOCKED: - if ((*lockStatus == DRXJ_DEMOD_LOCK) && /* still demod_lock in 150ms*/ - ((DRXBSP_HST_Clock() - dLockedTime) > DRXJ_QAM_FEC_LOCK_WAITTIME)) - { - RR16( demod->myI2CDevAddr, QAM_SY_TIMEOUT__A, &data ); - WR16( demod->myI2CDevAddr, QAM_SY_TIMEOUT__A, data | 0x1 ); - state = SYNC_FLIPPED; - DRXBSP_HST_Sleep(10); - } - break; - case SYNC_FLIPPED: - if (*lockStatus == DRXJ_DEMOD_LOCK) - { - if (channel->mirror == DRX_MIRROR_AUTO) - { - /* flip sync pattern back */ - RR16( demod->myI2CDevAddr, QAM_SY_TIMEOUT__A, &data ); - WR16( demod->myI2CDevAddr, QAM_SY_TIMEOUT__A, data & 0xFFFE ); - /* flip spectrum */ - extAttr->mirror = DRX_MIRROR_YES; - CHK_ERROR ( qamFlipSpec ( demod, channel ) ); - state = SPEC_MIRRORED; - /* reset timer TODO: still need 500ms? */ - startTime = dLockedTime = DRXBSP_HST_Clock(); - timeoutOfs = 0; - } - else /* no need to wait lock */ - { - startTime = DRXBSP_HST_Clock() - DRXJ_QAM_MAX_WAITTIME - timeoutOfs; - } - } - break; - case SPEC_MIRRORED: - if ((*lockStatus == DRXJ_DEMOD_LOCK) && /* still demod_lock in 150ms*/ - ((DRXBSP_HST_Clock() - dLockedTime) > DRXJ_QAM_FEC_LOCK_WAITTIME)) - { - CHK_ERROR ( CtrlGetQAMSigQuality ( demod, &sigQuality ) ); - if (sigQuality.MER > 208) - { - RR16( demod->myI2CDevAddr, QAM_SY_TIMEOUT__A, &data ); - WR16( demod->myI2CDevAddr, QAM_SY_TIMEOUT__A, data | 0x1 ); - /* no need to wait lock */ - startTime = DRXBSP_HST_Clock() - DRXJ_QAM_MAX_WAITTIME - timeoutOfs; - } - } - break; - default: - break; - } - DRXBSP_HST_Sleep(10); - } while - ( ( *lockStatus != DRX_LOCKED ) && - ( *lockStatus != DRX_NEVER_LOCK ) && - ( (DRXBSP_HST_Clock() - startTime) < (DRXJ_QAM_MAX_WAITTIME + timeoutOfs)) - ); - /* Returning control to apllication ... */ - - return (DRX_STS_OK); +QAM64Auto(pDRXDemodInstance_t demod, + pDRXChannel_t channel, + DRXFrequency_t tunerFreqOffset, pDRXLockStatus_t lockStatus) +{ + DRXSigQuality_t sigQuality; + u16_t data = 0; + u32_t state = NO_LOCK; + u32_t startTime = 0; + u32_t dLockedTime = 0; + pDRXJData_t extAttr = NULL; + u32_t timeoutOfs = 0; + + /* external attributes for storing aquired channel constellation */ + extAttr = (pDRXJData_t) demod->myExtAttr; + *lockStatus = DRX_NOT_LOCKED; + startTime = DRXBSP_HST_Clock(); + state = NO_LOCK; + do { + CHK_ERROR(CtrlLockStatus(demod, lockStatus)); + + switch (state) { + case NO_LOCK: + if (*lockStatus == DRXJ_DEMOD_LOCK) { + CHK_ERROR(CtrlGetQAMSigQuality + (demod, &sigQuality)); + if (sigQuality.MER > 208) { + state = DEMOD_LOCKED; + /* some delay to see if fec_lock possible TODO find the right value */ + timeoutOfs += DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME; /* see something, waiting longer */ + dLockedTime = DRXBSP_HST_Clock(); + } + } + break; + case DEMOD_LOCKED: + if ((*lockStatus == DRXJ_DEMOD_LOCK) && /* still demod_lock in 150ms */ + ((DRXBSP_HST_Clock() - dLockedTime) > + DRXJ_QAM_FEC_LOCK_WAITTIME)) { + RR16(demod->myI2CDevAddr, QAM_SY_TIMEOUT__A, + &data); + WR16(demod->myI2CDevAddr, QAM_SY_TIMEOUT__A, + data | 0x1); + state = SYNC_FLIPPED; + DRXBSP_HST_Sleep(10); + } + break; + case SYNC_FLIPPED: + if (*lockStatus == DRXJ_DEMOD_LOCK) { + if (channel->mirror == DRX_MIRROR_AUTO) { + /* flip sync pattern back */ + RR16(demod->myI2CDevAddr, + QAM_SY_TIMEOUT__A, &data); + WR16(demod->myI2CDevAddr, + QAM_SY_TIMEOUT__A, data & 0xFFFE); + /* flip spectrum */ + extAttr->mirror = DRX_MIRROR_YES; + CHK_ERROR(qamFlipSpec(demod, channel)); + state = SPEC_MIRRORED; + /* reset timer TODO: still need 500ms? */ + startTime = dLockedTime = + DRXBSP_HST_Clock(); + timeoutOfs = 0; + } else { /* no need to wait lock */ + + startTime = + DRXBSP_HST_Clock() - + DRXJ_QAM_MAX_WAITTIME - timeoutOfs; + } + } + break; + case SPEC_MIRRORED: + if ((*lockStatus == DRXJ_DEMOD_LOCK) && /* still demod_lock in 150ms */ + ((DRXBSP_HST_Clock() - dLockedTime) > + DRXJ_QAM_FEC_LOCK_WAITTIME)) { + CHK_ERROR(CtrlGetQAMSigQuality + (demod, &sigQuality)); + if (sigQuality.MER > 208) { + RR16(demod->myI2CDevAddr, + QAM_SY_TIMEOUT__A, &data); + WR16(demod->myI2CDevAddr, + QAM_SY_TIMEOUT__A, data | 0x1); + /* no need to wait lock */ + startTime = + DRXBSP_HST_Clock() - + DRXJ_QAM_MAX_WAITTIME - timeoutOfs; + } + } + break; + default: + break; + } + DRXBSP_HST_Sleep(10); + } while + ((*lockStatus != DRX_LOCKED) && + (*lockStatus != DRX_NEVER_LOCK) && + ((DRXBSP_HST_Clock() - startTime) < + (DRXJ_QAM_MAX_WAITTIME + timeoutOfs)) + ); + /* Returning control to apllication ... */ + + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /** @@ -7933,70 +7623,65 @@ rw_error: * \return DRXStatus_t. */ static DRXStatus_t -QAM256Auto( pDRXDemodInstance_t demod, - pDRXChannel_t channel, - DRXFrequency_t tunerFreqOffset, - pDRXLockStatus_t lockStatus - ) -{ - DRXSigQuality_t sigQuality; - u32_t state = NO_LOCK; - u32_t startTime = 0; - u32_t dLockedTime= 0; - pDRXJData_t extAttr = NULL; - u32_t timeoutOfs = DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME; - - /* external attributes for storing aquired channel constellation */ - extAttr = (pDRXJData_t)demod -> myExtAttr; - *lockStatus = DRX_NOT_LOCKED; - startTime = DRXBSP_HST_Clock(); - state = NO_LOCK; - do - { - CHK_ERROR( CtrlLockStatus( demod, lockStatus) ); - switch (state) - { - case NO_LOCK: - if ( *lockStatus == DRXJ_DEMOD_LOCK ) - { - CHK_ERROR ( CtrlGetQAMSigQuality ( demod, &sigQuality ) ); - if (sigQuality.MER > 268) - { - state = DEMOD_LOCKED; - timeoutOfs += DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME; /* see something, wait longer */ - dLockedTime = DRXBSP_HST_Clock(); - } - } - break; - case DEMOD_LOCKED: - if ( *lockStatus == DRXJ_DEMOD_LOCK ) - { - if ((channel->mirror == DRX_MIRROR_AUTO) && - ((DRXBSP_HST_Clock() - dLockedTime) > DRXJ_QAM_FEC_LOCK_WAITTIME)) - { - extAttr->mirror = DRX_MIRROR_YES; - CHK_ERROR ( qamFlipSpec ( demod, channel ) ); - state = SPEC_MIRRORED; - /* reset timer TODO: still need 300ms? */ - startTime = DRXBSP_HST_Clock(); - timeoutOfs = - DRXJ_QAM_MAX_WAITTIME / 2; - } - } - break; - case SPEC_MIRRORED: - break; - default: - break; - } - DRXBSP_HST_Sleep(10); - } while - ( ( *lockStatus < DRX_LOCKED ) && - ( *lockStatus != DRX_NEVER_LOCK ) && - ( (DRXBSP_HST_Clock() - startTime) < (DRXJ_QAM_MAX_WAITTIME + timeoutOfs)) ); - - return (DRX_STS_OK); +QAM256Auto(pDRXDemodInstance_t demod, + pDRXChannel_t channel, + DRXFrequency_t tunerFreqOffset, pDRXLockStatus_t lockStatus) +{ + DRXSigQuality_t sigQuality; + u32_t state = NO_LOCK; + u32_t startTime = 0; + u32_t dLockedTime = 0; + pDRXJData_t extAttr = NULL; + u32_t timeoutOfs = DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME; + + /* external attributes for storing aquired channel constellation */ + extAttr = (pDRXJData_t) demod->myExtAttr; + *lockStatus = DRX_NOT_LOCKED; + startTime = DRXBSP_HST_Clock(); + state = NO_LOCK; + do { + CHK_ERROR(CtrlLockStatus(demod, lockStatus)); + switch (state) { + case NO_LOCK: + if (*lockStatus == DRXJ_DEMOD_LOCK) { + CHK_ERROR(CtrlGetQAMSigQuality + (demod, &sigQuality)); + if (sigQuality.MER > 268) { + state = DEMOD_LOCKED; + timeoutOfs += DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME; /* see something, wait longer */ + dLockedTime = DRXBSP_HST_Clock(); + } + } + break; + case DEMOD_LOCKED: + if (*lockStatus == DRXJ_DEMOD_LOCK) { + if ((channel->mirror == DRX_MIRROR_AUTO) && + ((DRXBSP_HST_Clock() - dLockedTime) > + DRXJ_QAM_FEC_LOCK_WAITTIME)) { + extAttr->mirror = DRX_MIRROR_YES; + CHK_ERROR(qamFlipSpec(demod, channel)); + state = SPEC_MIRRORED; + /* reset timer TODO: still need 300ms? */ + startTime = DRXBSP_HST_Clock(); + timeoutOfs = -DRXJ_QAM_MAX_WAITTIME / 2; + } + } + break; + case SPEC_MIRRORED: + break; + default: + break; + } + DRXBSP_HST_Sleep(10); + } while + ((*lockStatus < DRX_LOCKED) && + (*lockStatus != DRX_NEVER_LOCK) && + ((DRXBSP_HST_Clock() - startTime) < + (DRXJ_QAM_MAX_WAITTIME + timeoutOfs))); + + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /** @@ -8007,135 +7692,143 @@ rw_error: * \return DRXStatus_t. */ static DRXStatus_t -SetQAMChannel( pDRXDemodInstance_t demod, - pDRXChannel_t channel, - DRXFrequency_t tunerFreqOffset - ) -{ - DRXLockStatus_t lockStatus = DRX_NOT_LOCKED; - pDRXJData_t extAttr = NULL; - Bool_t autoFlag = FALSE; - - /* external attributes for storing aquired channel constellation */ - extAttr = (pDRXJData_t)demod->myExtAttr; - - /* set QAM channel constellation */ - switch ( channel->constellation ) { - case DRX_CONSTELLATION_QAM16 : - case DRX_CONSTELLATION_QAM32 : - case DRX_CONSTELLATION_QAM64 : - case DRX_CONSTELLATION_QAM128 : - case DRX_CONSTELLATION_QAM256 : - extAttr->constellation = channel->constellation; - if (channel->mirror == DRX_MIRROR_AUTO) - { - extAttr->mirror = DRX_MIRROR_NO; - } - else - { - extAttr->mirror = channel->mirror; - } - CHK_ERROR ( SetQAM( demod, channel, tunerFreqOffset, QAM_SET_OP_ALL) ); - - if ( (extAttr->standard == DRX_STANDARD_ITU_B) && - (channel->constellation == DRX_CONSTELLATION_QAM64) ) - { - CHK_ERROR ( QAM64Auto( demod, channel, tunerFreqOffset, &lockStatus)); - } +SetQAMChannel(pDRXDemodInstance_t demod, + pDRXChannel_t channel, DRXFrequency_t tunerFreqOffset) +{ + DRXLockStatus_t lockStatus = DRX_NOT_LOCKED; + pDRXJData_t extAttr = NULL; + Bool_t autoFlag = FALSE; + + /* external attributes for storing aquired channel constellation */ + extAttr = (pDRXJData_t) demod->myExtAttr; + + /* set QAM channel constellation */ + switch (channel->constellation) { + case DRX_CONSTELLATION_QAM16: + case DRX_CONSTELLATION_QAM32: + case DRX_CONSTELLATION_QAM64: + case DRX_CONSTELLATION_QAM128: + case DRX_CONSTELLATION_QAM256: + extAttr->constellation = channel->constellation; + if (channel->mirror == DRX_MIRROR_AUTO) { + extAttr->mirror = DRX_MIRROR_NO; + } else { + extAttr->mirror = channel->mirror; + } + CHK_ERROR(SetQAM + (demod, channel, tunerFreqOffset, QAM_SET_OP_ALL)); + + if ((extAttr->standard == DRX_STANDARD_ITU_B) && + (channel->constellation == DRX_CONSTELLATION_QAM64)) { + CHK_ERROR(QAM64Auto + (demod, channel, tunerFreqOffset, + &lockStatus)); + } + + if ((extAttr->standard == DRX_STANDARD_ITU_B) && + (channel->mirror == DRX_MIRROR_AUTO) && + (channel->constellation == DRX_CONSTELLATION_QAM256)) { + CHK_ERROR(QAM256Auto + (demod, channel, tunerFreqOffset, + &lockStatus)); + } + break; + case DRX_CONSTELLATION_AUTO: /* for channel scan */ + if (extAttr->standard == DRX_STANDARD_ITU_B) { + autoFlag = TRUE; + /* try to lock default QAM constellation: QAM64 */ + channel->constellation = DRX_CONSTELLATION_QAM256; + extAttr->constellation = DRX_CONSTELLATION_QAM256; + if (channel->mirror == DRX_MIRROR_AUTO) { + extAttr->mirror = DRX_MIRROR_NO; + } else { + extAttr->mirror = channel->mirror; + } + CHK_ERROR(SetQAM + (demod, channel, tunerFreqOffset, + QAM_SET_OP_ALL)); + CHK_ERROR(QAM256Auto + (demod, channel, tunerFreqOffset, + &lockStatus)); + + if (lockStatus < DRX_LOCKED) { + /* QAM254 not locked -> try to lock QAM64 constellation */ + channel->constellation = + DRX_CONSTELLATION_QAM64; + extAttr->constellation = + DRX_CONSTELLATION_QAM64; + if (channel->mirror == DRX_MIRROR_AUTO) { + extAttr->mirror = DRX_MIRROR_NO; + } else { + extAttr->mirror = channel->mirror; + } + { + u16_t qamCtlEna = 0; + RR16(demod->myI2CDevAddr, + SCU_RAM_QAM_CTL_ENA__A, + &qamCtlEna); + WR16(demod->myI2CDevAddr, + SCU_RAM_QAM_CTL_ENA__A, + qamCtlEna & + ~SCU_RAM_QAM_CTL_ENA_ACQ__M); + WR16(demod->myI2CDevAddr, SCU_RAM_QAM_FSM_STATE_TGT__A, 0x2); /* force to rate hunting */ + + CHK_ERROR(SetQAM + (demod, channel, + tunerFreqOffset, + QAM_SET_OP_CONSTELLATION)); + WR16(demod->myI2CDevAddr, + SCU_RAM_QAM_CTL_ENA__A, qamCtlEna); + } + CHK_ERROR(QAM64Auto + (demod, channel, tunerFreqOffset, + &lockStatus)); + } + channel->constellation = DRX_CONSTELLATION_AUTO; + } else if (extAttr->standard == DRX_STANDARD_ITU_C) { + channel->constellation = DRX_CONSTELLATION_QAM64; + extAttr->constellation = DRX_CONSTELLATION_QAM64; + autoFlag = TRUE; + + if (channel->mirror == DRX_MIRROR_AUTO) { + extAttr->mirror = DRX_MIRROR_NO; + } else { + extAttr->mirror = channel->mirror; + } + { + u16_t qamCtlEna = 0; + RR16(demod->myI2CDevAddr, + SCU_RAM_QAM_CTL_ENA__A, &qamCtlEna); + WR16(demod->myI2CDevAddr, + SCU_RAM_QAM_CTL_ENA__A, + qamCtlEna & ~SCU_RAM_QAM_CTL_ENA_ACQ__M); + WR16(demod->myI2CDevAddr, SCU_RAM_QAM_FSM_STATE_TGT__A, 0x2); /* force to rate hunting */ + + CHK_ERROR(SetQAM + (demod, channel, tunerFreqOffset, + QAM_SET_OP_CONSTELLATION)); + WR16(demod->myI2CDevAddr, + SCU_RAM_QAM_CTL_ENA__A, qamCtlEna); + } + CHK_ERROR(QAM64Auto + (demod, channel, tunerFreqOffset, + &lockStatus)); + channel->constellation = DRX_CONSTELLATION_AUTO; + } else { + channel->constellation = DRX_CONSTELLATION_AUTO; + return (DRX_STS_INVALID_ARG); + } + break; + default: + return (DRX_STS_INVALID_ARG); + } - if ( (extAttr->standard == DRX_STANDARD_ITU_B) && - (channel->mirror == DRX_MIRROR_AUTO) && - (channel->constellation == DRX_CONSTELLATION_QAM256) ) - { - CHK_ERROR ( QAM256Auto( demod, channel, tunerFreqOffset, &lockStatus)); - } - break; - case DRX_CONSTELLATION_AUTO: /* for channel scan */ - if ( extAttr->standard == DRX_STANDARD_ITU_B ) - { - autoFlag = TRUE; - /* try to lock default QAM constellation: QAM64 */ - channel->constellation = DRX_CONSTELLATION_QAM256; - extAttr->constellation = DRX_CONSTELLATION_QAM256; - if (channel->mirror == DRX_MIRROR_AUTO) - { - extAttr->mirror = DRX_MIRROR_NO; - } - else - { - extAttr->mirror = channel->mirror; - } - CHK_ERROR ( SetQAM( demod, channel, tunerFreqOffset, QAM_SET_OP_ALL ) ); - CHK_ERROR ( QAM256Auto( demod, channel, tunerFreqOffset, &lockStatus )); - - if ( lockStatus < DRX_LOCKED ) - { - /* QAM254 not locked -> try to lock QAM64 constellation */ - channel->constellation = DRX_CONSTELLATION_QAM64; - extAttr->constellation = DRX_CONSTELLATION_QAM64; - if (channel->mirror == DRX_MIRROR_AUTO) - { - extAttr->mirror = DRX_MIRROR_NO; - } - else - { - extAttr->mirror = channel->mirror; - } - { - u16_t qamCtlEna = 0; - RR16( demod->myI2CDevAddr, SCU_RAM_QAM_CTL_ENA__A, &qamCtlEna ); - WR16( demod->myI2CDevAddr, SCU_RAM_QAM_CTL_ENA__A, qamCtlEna & ~SCU_RAM_QAM_CTL_ENA_ACQ__M ); - WR16( demod->myI2CDevAddr, SCU_RAM_QAM_FSM_STATE_TGT__A, 0x2 ); /* force to rate hunting */ - - CHK_ERROR ( SetQAM( demod, channel, tunerFreqOffset, QAM_SET_OP_CONSTELLATION) ); - WR16( demod->myI2CDevAddr, SCU_RAM_QAM_CTL_ENA__A, qamCtlEna ); - } - CHK_ERROR ( QAM64Auto( demod, channel, tunerFreqOffset, &lockStatus )); - } - channel->constellation = DRX_CONSTELLATION_AUTO; - } - else if ( extAttr->standard == DRX_STANDARD_ITU_C ) - { - channel->constellation = DRX_CONSTELLATION_QAM64; - extAttr->constellation = DRX_CONSTELLATION_QAM64; - autoFlag = TRUE; - - if (channel->mirror == DRX_MIRROR_AUTO) - { - extAttr->mirror = DRX_MIRROR_NO; - } - else - { - extAttr->mirror = channel->mirror; - } - { - u16_t qamCtlEna = 0; - RR16( demod->myI2CDevAddr, SCU_RAM_QAM_CTL_ENA__A, &qamCtlEna ); - WR16( demod->myI2CDevAddr, SCU_RAM_QAM_CTL_ENA__A, qamCtlEna & ~SCU_RAM_QAM_CTL_ENA_ACQ__M ); - WR16( demod->myI2CDevAddr, SCU_RAM_QAM_FSM_STATE_TGT__A, 0x2 ); /* force to rate hunting */ - - CHK_ERROR ( SetQAM( demod, channel, tunerFreqOffset, QAM_SET_OP_CONSTELLATION) ); - WR16( demod->myI2CDevAddr, SCU_RAM_QAM_CTL_ENA__A, qamCtlEna ); - } - CHK_ERROR ( QAM64Auto( demod, channel, tunerFreqOffset, &lockStatus )); - channel->constellation = DRX_CONSTELLATION_AUTO; - } - else - { - channel->constellation = DRX_CONSTELLATION_AUTO; - return (DRX_STS_INVALID_ARG); - } - break; - default: - return (DRX_STS_INVALID_ARG); - } - - return (DRX_STS_OK); + return (DRX_STS_OK); rw_error: - /* restore starting value */ - if (autoFlag) - channel->constellation = DRX_CONSTELLATION_AUTO; - return (DRX_STS_ERROR); + /* restore starting value */ + if (autoFlag) + channel->constellation = DRX_CONSTELLATION_AUTO; + return (DRX_STS_ERROR); } /*============================================================================*/ @@ -8149,45 +7842,43 @@ rw_error: * */ static DRXStatus_t -GetQAMRSErrCount(pI2CDeviceAddr_t devAddr, pDRXJRSErrors_t RSErrors) +GetQAMRSErrCount(pI2CDeviceAddr_t devAddr, pDRXJRSErrors_t RSErrors) { - u16_t nrBitErrors = 0, - nrSymbolErrors = 0, - nrPacketErrors = 0, - nrFailures = 0, - nrSncParFailCount = 0; - - /* check arguments */ - if ( devAddr == NULL ) - { - return (DRX_STS_INVALID_ARG); - } - - /* all reported errors are received in the */ - /* most recently finished measurment period */ - /* no of pre RS bit errors */ - RR16( devAddr, FEC_RS_NR_BIT_ERRORS__A, &nrBitErrors ); - /* no of symbol errors */ - RR16( devAddr, FEC_RS_NR_SYMBOL_ERRORS__A, &nrSymbolErrors ); - /* no of packet errors */ - RR16( devAddr, FEC_RS_NR_PACKET_ERRORS__A, &nrPacketErrors ); - /* no of failures to decode */ - RR16( devAddr, FEC_RS_NR_FAILURES__A, &nrFailures ); - /* no of post RS bit erros */ - RR16( devAddr, FEC_OC_SNC_FAIL_COUNT__A, &nrSncParFailCount ); - /* TODO: NOTE */ - /* These register values are fetched in non-atomic fashion */ - /* It is possible that the read values contain unrelated information */ - - RSErrors->nrBitErrors = nrBitErrors & FEC_RS_NR_BIT_ERRORS__M; - RSErrors->nrSymbolErrors = nrSymbolErrors & FEC_RS_NR_SYMBOL_ERRORS__M; - RSErrors->nrPacketErrors = nrPacketErrors & FEC_RS_NR_PACKET_ERRORS__M; - RSErrors->nrFailures = nrFailures & FEC_RS_NR_FAILURES__M; - RSErrors->nrSncParFailCount = nrSncParFailCount & FEC_OC_SNC_FAIL_COUNT__M; - - return (DRX_STS_OK); + u16_t nrBitErrors = 0, + nrSymbolErrors = 0, + nrPacketErrors = 0, nrFailures = 0, nrSncParFailCount = 0; + + /* check arguments */ + if (devAddr == NULL) { + return (DRX_STS_INVALID_ARG); + } + + /* all reported errors are received in the */ + /* most recently finished measurment period */ + /* no of pre RS bit errors */ + RR16(devAddr, FEC_RS_NR_BIT_ERRORS__A, &nrBitErrors); + /* no of symbol errors */ + RR16(devAddr, FEC_RS_NR_SYMBOL_ERRORS__A, &nrSymbolErrors); + /* no of packet errors */ + RR16(devAddr, FEC_RS_NR_PACKET_ERRORS__A, &nrPacketErrors); + /* no of failures to decode */ + RR16(devAddr, FEC_RS_NR_FAILURES__A, &nrFailures); + /* no of post RS bit erros */ + RR16(devAddr, FEC_OC_SNC_FAIL_COUNT__A, &nrSncParFailCount); + /* TODO: NOTE */ + /* These register values are fetched in non-atomic fashion */ + /* It is possible that the read values contain unrelated information */ + + RSErrors->nrBitErrors = nrBitErrors & FEC_RS_NR_BIT_ERRORS__M; + RSErrors->nrSymbolErrors = nrSymbolErrors & FEC_RS_NR_SYMBOL_ERRORS__M; + RSErrors->nrPacketErrors = nrPacketErrors & FEC_RS_NR_PACKET_ERRORS__M; + RSErrors->nrFailures = nrFailures & FEC_RS_NR_FAILURES__M; + RSErrors->nrSncParFailCount = + nrSncParFailCount & FEC_OC_SNC_FAIL_COUNT__M; + + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /*============================================================================*/ @@ -8205,185 +7896,177 @@ rw_error: * Pre-condition: Device must be started and in lock. */ static DRXStatus_t -CtrlGetQAMSigQuality( pDRXDemodInstance_t demod, - pDRXSigQuality_t sigQuality ) -{ - pI2CDeviceAddr_t devAddr = NULL; - pDRXJData_t extAttr = NULL; - DRXConstellation_t constellation = DRX_CONSTELLATION_UNKNOWN; - DRXJRSErrors_t measuredRSErrors = { 0, 0, 0, 0, 0 }; - - u32_t preBitErrRS = 0; /* pre RedSolomon Bit Error Rate */ - u32_t postBitErrRS = 0; /* post RedSolomon Bit Error Rate */ - u32_t pktErrs = 0; /* no of packet errors in RS */ - u16_t qamSlErrPower = 0; /* accumulated error between raw and sliced symbols */ - u16_t qsymErrVD = 0; /* quadrature symbol errors in QAM_VD */ - u16_t fecOcPeriod = 0; /* SNC sync failure measurement period */ - u16_t fecRsPrescale = 0; /* ReedSolomon Measurement Prescale */ - u16_t fecRsPeriod = 0; /* Value for corresponding I2C register */ - /* calculation constants */ - u32_t rsBitCnt = 0; /* RedSolomon Bit Count */ - u32_t qamSlSigPower = 0; /* used for MER, depends of QAM constellation */ - /* intermediate results */ - u32_t e = 0; /* exponent value used for QAM BER/SER */ - u32_t m = 0; /* mantisa value used for QAM BER/SER */ - u32_t berCnt = 0; /* BER count */ - /* signal quality info */ - u32_t qamSlMer = 0; /* QAM MER */ - u32_t qamPreRSBer = 0; /* Pre RedSolomon BER */ - u32_t qamPostRSBer = 0; /* Post RedSolomon BER */ - u32_t qamVDSer = 0; /* ViterbiDecoder SER */ - u16_t qamVdPrescale = 0; /* Viterbi Measurement Prescale */ - u16_t qamVdPeriod = 0; /* Viterbi Measurement period */ - u32_t vdBitCnt = 0; /* ViterbiDecoder Bit Count */ - - /* get device basic information */ - devAddr = demod -> myI2CDevAddr; - extAttr = (pDRXJData_t)demod->myExtAttr; - constellation = extAttr->constellation; - - /* read the physical registers */ - /* Get the RS error data */ - CHK_ERROR ( GetQAMRSErrCount ( devAddr, &measuredRSErrors ) ); - /* get the register value needed for MER */ - RR16( devAddr, QAM_SL_ERR_POWER__A, &qamSlErrPower ); - /* get the register value needed for post RS BER */ - RR16 ( devAddr, FEC_OC_SNC_FAIL_PERIOD__A, &fecOcPeriod ); - - /* get constants needed for signal quality calculation */ - fecRsPeriod = extAttr->fecRsPeriod; - fecRsPrescale = extAttr->fecRsPrescale; - rsBitCnt = fecRsPeriod * fecRsPrescale * extAttr->fecRsPlen; - qamVdPeriod = extAttr->qamVdPeriod; - qamVdPrescale = extAttr->qamVdPrescale; - vdBitCnt = qamVdPeriod * qamVdPrescale * extAttr->fecVdPlen; - - /* DRXJ_QAM_SL_SIG_POWER_QAMxxx * 4 */ - switch ( constellation ) - { - case DRX_CONSTELLATION_QAM16: - qamSlSigPower = DRXJ_QAM_SL_SIG_POWER_QAM16 << 2; - break; - case DRX_CONSTELLATION_QAM32: - qamSlSigPower = DRXJ_QAM_SL_SIG_POWER_QAM32 << 2; - break; - case DRX_CONSTELLATION_QAM64: - qamSlSigPower = DRXJ_QAM_SL_SIG_POWER_QAM64 << 2; - break; - case DRX_CONSTELLATION_QAM128: - qamSlSigPower = DRXJ_QAM_SL_SIG_POWER_QAM128 << 2; - break; - case DRX_CONSTELLATION_QAM256: - qamSlSigPower = DRXJ_QAM_SL_SIG_POWER_QAM256 << 2; - break; - default: - return (DRX_STS_ERROR); - } - - /* ------------------------------ */ - /* MER Calculation */ - /* ------------------------------ */ - /* MER is good if it is above 27.5 for QAM256 or 21.5 for QAM64 */ - - /* 10.0*log10(qam_sl_sig_power * 4.0 / qam_sl_err_power); */ - if ( qamSlErrPower == 0 ) - qamSlMer = 0; - else - qamSlMer = Log10Times100( qamSlSigPower ) - Log10Times100( ( u32_t ) qamSlErrPower ); - - - /* ----------------------------------------- */ - /* Pre Viterbi Symbol Error Rate Calculation */ - /* ----------------------------------------- */ - /* pre viterbi SER is good if it is bellow 0.025 */ - - /* get the register value */ - /* no of quadrature symbol errors */ - RR16( devAddr, QAM_VD_NR_QSYM_ERRORS__A , &qsymErrVD ); - /* Extract the Exponent and the Mantisa */ - /* of number of quadrature symbol errors */ - e = ( qsymErrVD & QAM_VD_NR_QSYM_ERRORS_EXP__M ) >> - QAM_VD_NR_QSYM_ERRORS_EXP__B; - m = ( qsymErrVD & QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__M ) >> - QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__B; - - if ( (m << e) >> 3 > 549752 ) /* the max of FracTimes1e6 */ - { - qamVDSer = 500000; /* clip BER 0.5 */ - } - else - { - qamVDSer = FracTimes1e6(m << ((e > 2)? (e - 3):e), vdBitCnt * ((e > 2)?1:8) / 8 ); - } - - /* --------------------------------------- */ - /* pre and post RedSolomon BER Calculation */ - /* --------------------------------------- */ - /* pre RS BER is good if it is below 3.5e-4 */ +CtrlGetQAMSigQuality(pDRXDemodInstance_t demod, pDRXSigQuality_t sigQuality) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + DRXConstellation_t constellation = DRX_CONSTELLATION_UNKNOWN; + DRXJRSErrors_t measuredRSErrors = { 0, 0, 0, 0, 0 }; + + u32_t preBitErrRS = 0; /* pre RedSolomon Bit Error Rate */ + u32_t postBitErrRS = 0; /* post RedSolomon Bit Error Rate */ + u32_t pktErrs = 0; /* no of packet errors in RS */ + u16_t qamSlErrPower = 0; /* accumulated error between raw and sliced symbols */ + u16_t qsymErrVD = 0; /* quadrature symbol errors in QAM_VD */ + u16_t fecOcPeriod = 0; /* SNC sync failure measurement period */ + u16_t fecRsPrescale = 0; /* ReedSolomon Measurement Prescale */ + u16_t fecRsPeriod = 0; /* Value for corresponding I2C register */ + /* calculation constants */ + u32_t rsBitCnt = 0; /* RedSolomon Bit Count */ + u32_t qamSlSigPower = 0; /* used for MER, depends of QAM constellation */ + /* intermediate results */ + u32_t e = 0; /* exponent value used for QAM BER/SER */ + u32_t m = 0; /* mantisa value used for QAM BER/SER */ + u32_t berCnt = 0; /* BER count */ + /* signal quality info */ + u32_t qamSlMer = 0; /* QAM MER */ + u32_t qamPreRSBer = 0; /* Pre RedSolomon BER */ + u32_t qamPostRSBer = 0; /* Post RedSolomon BER */ + u32_t qamVDSer = 0; /* ViterbiDecoder SER */ + u16_t qamVdPrescale = 0; /* Viterbi Measurement Prescale */ + u16_t qamVdPeriod = 0; /* Viterbi Measurement period */ + u32_t vdBitCnt = 0; /* ViterbiDecoder Bit Count */ + + /* get device basic information */ + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; + constellation = extAttr->constellation; + + /* read the physical registers */ + /* Get the RS error data */ + CHK_ERROR(GetQAMRSErrCount(devAddr, &measuredRSErrors)); + /* get the register value needed for MER */ + RR16(devAddr, QAM_SL_ERR_POWER__A, &qamSlErrPower); + /* get the register value needed for post RS BER */ + RR16(devAddr, FEC_OC_SNC_FAIL_PERIOD__A, &fecOcPeriod); + + /* get constants needed for signal quality calculation */ + fecRsPeriod = extAttr->fecRsPeriod; + fecRsPrescale = extAttr->fecRsPrescale; + rsBitCnt = fecRsPeriod * fecRsPrescale * extAttr->fecRsPlen; + qamVdPeriod = extAttr->qamVdPeriod; + qamVdPrescale = extAttr->qamVdPrescale; + vdBitCnt = qamVdPeriod * qamVdPrescale * extAttr->fecVdPlen; + + /* DRXJ_QAM_SL_SIG_POWER_QAMxxx * 4 */ + switch (constellation) { + case DRX_CONSTELLATION_QAM16: + qamSlSigPower = DRXJ_QAM_SL_SIG_POWER_QAM16 << 2; + break; + case DRX_CONSTELLATION_QAM32: + qamSlSigPower = DRXJ_QAM_SL_SIG_POWER_QAM32 << 2; + break; + case DRX_CONSTELLATION_QAM64: + qamSlSigPower = DRXJ_QAM_SL_SIG_POWER_QAM64 << 2; + break; + case DRX_CONSTELLATION_QAM128: + qamSlSigPower = DRXJ_QAM_SL_SIG_POWER_QAM128 << 2; + break; + case DRX_CONSTELLATION_QAM256: + qamSlSigPower = DRXJ_QAM_SL_SIG_POWER_QAM256 << 2; + break; + default: + return (DRX_STS_ERROR); + } - /* get the register values */ - preBitErrRS = ( u32_t ) measuredRSErrors.nrBitErrors; - pktErrs = postBitErrRS = ( u32_t ) measuredRSErrors.nrSncParFailCount; + /* ------------------------------ */ + /* MER Calculation */ + /* ------------------------------ */ + /* MER is good if it is above 27.5 for QAM256 or 21.5 for QAM64 */ + + /* 10.0*log10(qam_sl_sig_power * 4.0 / qam_sl_err_power); */ + if (qamSlErrPower == 0) + qamSlMer = 0; + else + qamSlMer = + Log10Times100(qamSlSigPower) - + Log10Times100((u32_t) qamSlErrPower); + + /* ----------------------------------------- */ + /* Pre Viterbi Symbol Error Rate Calculation */ + /* ----------------------------------------- */ + /* pre viterbi SER is good if it is bellow 0.025 */ + + /* get the register value */ + /* no of quadrature symbol errors */ + RR16(devAddr, QAM_VD_NR_QSYM_ERRORS__A, &qsymErrVD); + /* Extract the Exponent and the Mantisa */ + /* of number of quadrature symbol errors */ + e = (qsymErrVD & QAM_VD_NR_QSYM_ERRORS_EXP__M) >> + QAM_VD_NR_QSYM_ERRORS_EXP__B; + m = (qsymErrVD & QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__M) >> + QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__B; + + if ((m << e) >> 3 > 549752) { /* the max of FracTimes1e6 */ + qamVDSer = 500000; /* clip BER 0.5 */ + } else { + qamVDSer = + FracTimes1e6(m << ((e > 2) ? (e - 3) : e), + vdBitCnt * ((e > 2) ? 1 : 8) / 8); + } - /* Extract the Exponent and the Mantisa of the */ - /* pre Reed-Solomon bit error count */ - e = ( preBitErrRS & FEC_RS_NR_BIT_ERRORS_EXP__M ) >> - FEC_RS_NR_BIT_ERRORS_EXP__B; - m = ( preBitErrRS & FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M ) >> - FEC_RS_NR_BIT_ERRORS_FIXED_MANT__B; + /* --------------------------------------- */ + /* pre and post RedSolomon BER Calculation */ + /* --------------------------------------- */ + /* pre RS BER is good if it is below 3.5e-4 */ + + /* get the register values */ + preBitErrRS = (u32_t) measuredRSErrors.nrBitErrors; + pktErrs = postBitErrRS = (u32_t) measuredRSErrors.nrSncParFailCount; + + /* Extract the Exponent and the Mantisa of the */ + /* pre Reed-Solomon bit error count */ + e = (preBitErrRS & FEC_RS_NR_BIT_ERRORS_EXP__M) >> + FEC_RS_NR_BIT_ERRORS_EXP__B; + m = (preBitErrRS & FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M) >> + FEC_RS_NR_BIT_ERRORS_FIXED_MANT__B; + + berCnt = m << e; + + /*qamPreRSBer = FracTimes1e6( berCnt, rsBitCnt ); */ + if (m > (rsBitCnt >> (e + 1)) || (rsBitCnt >> e) == 0) { + qamPreRSBer = 500000; /* clip BER 0.5 */ + } else { + qamPreRSBer = FracTimes1e6(m, rsBitCnt >> e); + } - berCnt = m << e; + /* post RS BER = 1000000* (11.17 * FEC_OC_SNC_FAIL_COUNT__A) / */ + /* (1504.0 * FEC_OC_SNC_FAIL_PERIOD__A) */ + /* + => c = (1000000*100*11.17)/1504 = + post RS BER = (( c* FEC_OC_SNC_FAIL_COUNT__A) / + (100 * FEC_OC_SNC_FAIL_PERIOD__A) + *100 and /100 is for more precision. + => (20 bits * 12 bits) /(16 bits * 7 bits) => safe in 32 bits computation - /*qamPreRSBer = FracTimes1e6( berCnt, rsBitCnt ); */ - if ( m > (rsBitCnt >> (e + 1)) || (rsBitCnt >> e) == 0 ) - { - qamPreRSBer = 500000; /* clip BER 0.5 */ - } - else - { - qamPreRSBer = FracTimes1e6(m, rsBitCnt >> e ); - } - - /* post RS BER = 1000000* (11.17 * FEC_OC_SNC_FAIL_COUNT__A) / */ - /* (1504.0 * FEC_OC_SNC_FAIL_PERIOD__A) */ - /* - => c = (1000000*100*11.17)/1504 = - post RS BER = (( c* FEC_OC_SNC_FAIL_COUNT__A) / - (100 * FEC_OC_SNC_FAIL_PERIOD__A) - *100 and /100 is for more precision. - => (20 bits * 12 bits) /(16 bits * 7 bits) => safe in 32 bits computation - - Precision errors still possible. - */ - e = postBitErrRS * 742686; - m = fecOcPeriod * 100; - if ( fecOcPeriod == 0 ) - qamPostRSBer = 0xFFFFFFFF; - else - qamPostRSBer = e/m; - - /* fill signal quality data structure */ - sigQuality->MER = ( ( u16_t ) qamSlMer ); - if (extAttr->standard == DRX_STANDARD_ITU_B) - { - sigQuality->preViterbiBER = qamVDSer; - } - else - { - sigQuality->preViterbiBER = qamPreRSBer; - } - sigQuality->postViterbiBER = qamPreRSBer; - sigQuality->postReedSolomonBER = qamPostRSBer; - sigQuality->scaleFactorBER = ( ( u32_t ) 1000000 ); + Precision errors still possible. + */ + e = postBitErrRS * 742686; + m = fecOcPeriod * 100; + if (fecOcPeriod == 0) + qamPostRSBer = 0xFFFFFFFF; + else + qamPostRSBer = e / m; + + /* fill signal quality data structure */ + sigQuality->MER = ((u16_t) qamSlMer); + if (extAttr->standard == DRX_STANDARD_ITU_B) { + sigQuality->preViterbiBER = qamVDSer; + } else { + sigQuality->preViterbiBER = qamPreRSBer; + } + sigQuality->postViterbiBER = qamPreRSBer; + sigQuality->postReedSolomonBER = qamPostRSBer; + sigQuality->scaleFactorBER = ((u32_t) 1000000); #ifdef DRXJ_SIGNAL_ACCUM_ERR - CHK_ERROR (GetAccPktErr (demod, &sigQuality->packetError)); + CHK_ERROR(GetAccPktErr(demod, &sigQuality->packetError)); #else - sigQuality->packetError = ( ( u16_t ) pktErrs ); + sigQuality->packetError = ((u16_t) pktErrs); #endif - return (DRX_STS_OK); - rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); } /** @@ -8395,77 +8078,77 @@ CtrlGetQAMSigQuality( pDRXDemodInstance_t demod, * \return DRXStatus_t. */ static DRXStatus_t -CtrlGetQAMConstel( pDRXDemodInstance_t demod, - pDRXComplex_t complexNr ) -{ - u16_t fecOcOcrMode = 0; /**< FEC OCR grabber configuration */ - u16_t qamSlCommMb = 0; /**< QAM SL MB configuration */ - u16_t qamSlCommMbInit = 0; /**< QAM SL MB intial configuration */ - u16_t im = 0; /**< constellation Im part */ - u16_t re = 0; /**< constellation Re part */ - u32_t data = 0; - pI2CDeviceAddr_t devAddr = NULL; /**< device address */ - - /* read device info */ - devAddr = demod -> myI2CDevAddr; - - /* TODO: */ - /* Monitor bus grabbing is an open external interface issue */ - /* Needs to be checked when external interface PG is updated */ - - /* Configure MB (Monitor bus) */ - RR16( devAddr, QAM_SL_COMM_MB__A, &qamSlCommMbInit ); - /* set observe flag & MB mux */ - qamSlCommMb = qamSlCommMbInit & (~ ( QAM_SL_COMM_MB_OBS__M + - QAM_SL_COMM_MB_MUX_OBS__M ) ); - qamSlCommMb |= ( QAM_SL_COMM_MB_OBS_ON + - QAM_SL_COMM_MB_MUX_OBS_CONST_CORR ); - WR16( devAddr, QAM_SL_COMM_MB__A, qamSlCommMb ); - - /* Enable MB grabber in the FEC OC */ - fecOcOcrMode = ( /* output select: observe bus */ - ( FEC_OC_OCR_MODE_MB_SELECT__M & - ( 0x0 << FEC_OC_OCR_MODE_MB_SELECT__B ) ) | - /* grabber enable: on */ - ( FEC_OC_OCR_MODE_GRAB_ENABLE__M & - ( 0x1 << FEC_OC_OCR_MODE_GRAB_ENABLE__B ) ) | - /* grabber select: observe bus */ - ( FEC_OC_OCR_MODE_GRAB_SELECT__M & - ( 0x0 << FEC_OC_OCR_MODE_GRAB_SELECT__B ) ) | - /* grabber mode: continuous */ - ( FEC_OC_OCR_MODE_GRAB_COUNTED__M & - ( 0x0 << FEC_OC_OCR_MODE_GRAB_COUNTED__B ) ) ); - WR16( devAddr, FEC_OC_OCR_MODE__A, fecOcOcrMode ); - - /* Disable MB grabber in the FEC OC */ - WR16( devAddr, FEC_OC_OCR_MODE__A, 0x00 ); - - /* read data */ - RR32( devAddr, FEC_OC_OCR_GRAB_RD0__A, &data ); - re = (u16_t)(data & FEC_OC_OCR_GRAB_RD0__M); - im = (u16_t)((data >> 16) & FEC_OC_OCR_GRAB_RD1__M); - - /* TODO: */ - /* interpret data (re & im) according to the Monitor bus mapping ?? */ - - /* sign extension, 10th bit is sign bit */ - if ( (re & 0x0200) == 0x0200 ) - { - re |= 0xFC00; - } - if ( (im & 0x0200) == 0x0200 ) - { - im |= 0xFC00; - } - complexNr->re = ( ( s16_t ) re ) ; - complexNr->im = ( ( s16_t ) im ) ; +CtrlGetQAMConstel(pDRXDemodInstance_t demod, pDRXComplex_t complexNr) +{ + u16_t fecOcOcrMode = 0; + /**< FEC OCR grabber configuration */ + u16_t qamSlCommMb = 0;/**< QAM SL MB configuration */ + u16_t qamSlCommMbInit = 0; + /**< QAM SL MB intial configuration */ + u16_t im = 0; /**< constellation Im part */ + u16_t re = 0; /**< constellation Re part */ + u32_t data = 0; + pI2CDeviceAddr_t devAddr = NULL; + /**< device address */ + + /* read device info */ + devAddr = demod->myI2CDevAddr; + + /* TODO: */ + /* Monitor bus grabbing is an open external interface issue */ + /* Needs to be checked when external interface PG is updated */ + + /* Configure MB (Monitor bus) */ + RR16(devAddr, QAM_SL_COMM_MB__A, &qamSlCommMbInit); + /* set observe flag & MB mux */ + qamSlCommMb = qamSlCommMbInit & (~(QAM_SL_COMM_MB_OBS__M + + QAM_SL_COMM_MB_MUX_OBS__M)); + qamSlCommMb |= (QAM_SL_COMM_MB_OBS_ON + + QAM_SL_COMM_MB_MUX_OBS_CONST_CORR); + WR16(devAddr, QAM_SL_COMM_MB__A, qamSlCommMb); + + /* Enable MB grabber in the FEC OC */ + fecOcOcrMode = ( /* output select: observe bus */ + (FEC_OC_OCR_MODE_MB_SELECT__M & + (0x0 << FEC_OC_OCR_MODE_MB_SELECT__B)) | + /* grabber enable: on */ + (FEC_OC_OCR_MODE_GRAB_ENABLE__M & + (0x1 << FEC_OC_OCR_MODE_GRAB_ENABLE__B)) | + /* grabber select: observe bus */ + (FEC_OC_OCR_MODE_GRAB_SELECT__M & + (0x0 << FEC_OC_OCR_MODE_GRAB_SELECT__B)) | + /* grabber mode: continuous */ + (FEC_OC_OCR_MODE_GRAB_COUNTED__M & + (0x0 << FEC_OC_OCR_MODE_GRAB_COUNTED__B))); + WR16(devAddr, FEC_OC_OCR_MODE__A, fecOcOcrMode); + + /* Disable MB grabber in the FEC OC */ + WR16(devAddr, FEC_OC_OCR_MODE__A, 0x00); + + /* read data */ + RR32(devAddr, FEC_OC_OCR_GRAB_RD0__A, &data); + re = (u16_t) (data & FEC_OC_OCR_GRAB_RD0__M); + im = (u16_t) ((data >> 16) & FEC_OC_OCR_GRAB_RD1__M); + + /* TODO: */ + /* interpret data (re & im) according to the Monitor bus mapping ?? */ + + /* sign extension, 10th bit is sign bit */ + if ((re & 0x0200) == 0x0200) { + re |= 0xFC00; + } + if ((im & 0x0200) == 0x0200) { + im |= 0xFC00; + } + complexNr->re = ((s16_t) re); + complexNr->im = ((s16_t) im); - /* Restore MB (Monitor bus) */ - WR16( devAddr, QAM_SL_COMM_MB__A, qamSlCommMbInit ); + /* Restore MB (Monitor bus) */ + WR16(devAddr, QAM_SL_COMM_MB__A, qamSlCommMbInit); - return (DRX_STS_OK); - rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); } #endif /* #ifndef DRXJ_VSB_ONLY */ @@ -8542,39 +8225,37 @@ CtrlGetQAMConstel( pDRXDemodInstance_t demod, * \return DRXStatus_t. * */ -static DRXStatus_t -AtvEquCoefIndex( DRXStandard_t standard, int *index) -{ - switch(standard) - { - case DRX_STANDARD_PAL_SECAM_BG: - *index=(int)DRXJ_COEF_IDX_BG; - break; - case DRX_STANDARD_PAL_SECAM_DK: - *index=(int)DRXJ_COEF_IDX_DK; - break; - case DRX_STANDARD_PAL_SECAM_I: - *index=(int)DRXJ_COEF_IDX_I; - break; - case DRX_STANDARD_PAL_SECAM_L: - *index=(int)DRXJ_COEF_IDX_L; - break; - case DRX_STANDARD_PAL_SECAM_LP: - *index=(int)DRXJ_COEF_IDX_LP; - break; - case DRX_STANDARD_NTSC: - *index=(int)DRXJ_COEF_IDX_MN; - break; - case DRX_STANDARD_FM: - *index=(int)DRXJ_COEF_IDX_FM; - break; - default: - *index=(int)DRXJ_COEF_IDX_MN; /* still return a valid index */ - return DRX_STS_ERROR; - break; - } - - return DRX_STS_OK; +static DRXStatus_t AtvEquCoefIndex(DRXStandard_t standard, int *index) +{ + switch (standard) { + case DRX_STANDARD_PAL_SECAM_BG: + *index = (int)DRXJ_COEF_IDX_BG; + break; + case DRX_STANDARD_PAL_SECAM_DK: + *index = (int)DRXJ_COEF_IDX_DK; + break; + case DRX_STANDARD_PAL_SECAM_I: + *index = (int)DRXJ_COEF_IDX_I; + break; + case DRX_STANDARD_PAL_SECAM_L: + *index = (int)DRXJ_COEF_IDX_L; + break; + case DRX_STANDARD_PAL_SECAM_LP: + *index = (int)DRXJ_COEF_IDX_LP; + break; + case DRX_STANDARD_NTSC: + *index = (int)DRXJ_COEF_IDX_MN; + break; + case DRX_STANDARD_FM: + *index = (int)DRXJ_COEF_IDX_FM; + break; + default: + *index = (int)DRXJ_COEF_IDX_MN; /* still return a valid index */ + return DRX_STS_ERROR; + break; + } + + return DRX_STS_OK; } /* -------------------------------------------------------------------------- */ @@ -8587,112 +8268,102 @@ AtvEquCoefIndex( DRXStandard_t standard, int *index) * */ static DRXStatus_t -AtvUpdateConfig( pDRXDemodInstance_t demod, - Bool_t forceUpdate ) +AtvUpdateConfig(pDRXDemodInstance_t demod, Bool_t forceUpdate) { - pI2CDeviceAddr_t devAddr = NULL; - pDRXJData_t extAttr = NULL; + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; - devAddr = demod -> myI2CDevAddr; - extAttr = (pDRXJData_t)demod->myExtAttr; + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; - /* equalizer coefficients */ - if ( forceUpdate || - ((extAttr->atvCfgChangedFlags & DRXJ_ATV_CHANGED_COEF) != 0) ) - { - int index=0; + /* equalizer coefficients */ + if (forceUpdate || + ((extAttr->atvCfgChangedFlags & DRXJ_ATV_CHANGED_COEF) != 0)) { + int index = 0; - CHK_ERROR(AtvEquCoefIndex( extAttr->standard, &index )); - WR16( devAddr, ATV_TOP_EQU0__A, extAttr->atvTopEqu0[index] ); - WR16( devAddr, ATV_TOP_EQU1__A, extAttr->atvTopEqu1[index] ); - WR16( devAddr, ATV_TOP_EQU2__A, extAttr->atvTopEqu2[index] ); - WR16( devAddr, ATV_TOP_EQU3__A, extAttr->atvTopEqu3[index] ); - } + CHK_ERROR(AtvEquCoefIndex(extAttr->standard, &index)); + WR16(devAddr, ATV_TOP_EQU0__A, extAttr->atvTopEqu0[index]); + WR16(devAddr, ATV_TOP_EQU1__A, extAttr->atvTopEqu1[index]); + WR16(devAddr, ATV_TOP_EQU2__A, extAttr->atvTopEqu2[index]); + WR16(devAddr, ATV_TOP_EQU3__A, extAttr->atvTopEqu3[index]); + } - /* bypass fast carrier recovery */ - if ( forceUpdate ) - { - u16_t data=0; - - RR16( devAddr, IQM_RT_ROT_BP__A, &data ); - data &= (~((u16_t)IQM_RT_ROT_BP_ROT_OFF__M)); - if (extAttr->phaseCorrectionBypass) - { - data |= IQM_RT_ROT_BP_ROT_OFF_OFF; - } else { - data |= IQM_RT_ROT_BP_ROT_OFF_ACTIVE; - } - WR16( devAddr, IQM_RT_ROT_BP__A, data ); - } - - /* peak filter setting */ - if ( forceUpdate || - ((extAttr->atvCfgChangedFlags & DRXJ_ATV_CHANGED_PEAK_FLT) != 0) ) - { - WR16( devAddr, ATV_TOP_VID_PEAK__A, extAttr->atvTopVidPeak ); - } + /* bypass fast carrier recovery */ + if (forceUpdate) { + u16_t data = 0; + + RR16(devAddr, IQM_RT_ROT_BP__A, &data); + data &= (~((u16_t) IQM_RT_ROT_BP_ROT_OFF__M)); + if (extAttr->phaseCorrectionBypass) { + data |= IQM_RT_ROT_BP_ROT_OFF_OFF; + } else { + data |= IQM_RT_ROT_BP_ROT_OFF_ACTIVE; + } + WR16(devAddr, IQM_RT_ROT_BP__A, data); + } - /* noise filter setting */ - if ( forceUpdate || - ((extAttr->atvCfgChangedFlags & DRXJ_ATV_CHANGED_NOISE_FLT) != 0) ) - { - WR16( devAddr, ATV_TOP_NOISE_TH__A, extAttr->atvTopNoiseTh ); - } + /* peak filter setting */ + if (forceUpdate || + ((extAttr->atvCfgChangedFlags & DRXJ_ATV_CHANGED_PEAK_FLT) != 0)) { + WR16(devAddr, ATV_TOP_VID_PEAK__A, extAttr->atvTopVidPeak); + } - /* SIF attenuation */ - if ( forceUpdate || - ((extAttr->atvCfgChangedFlags & DRXJ_ATV_CHANGED_SIF_ATT) != 0) ) - { - u16_t attenuation=0; - - switch( extAttr->sifAttenuation ){ - case DRXJ_SIF_ATTENUATION_0DB: - attenuation = ATV_TOP_AF_SIF_ATT_0DB; - break; - case DRXJ_SIF_ATTENUATION_3DB: - attenuation = ATV_TOP_AF_SIF_ATT_M3DB; - break; - case DRXJ_SIF_ATTENUATION_6DB: - attenuation = ATV_TOP_AF_SIF_ATT_M6DB; - break; - case DRXJ_SIF_ATTENUATION_9DB: - attenuation = ATV_TOP_AF_SIF_ATT_M9DB; - break; - default: - return DRX_STS_ERROR; - break; - } - WR16( devAddr, ATV_TOP_AF_SIF_ATT__A, attenuation ); - } - - /* SIF & CVBS enable */ - if ( forceUpdate || - ((extAttr->atvCfgChangedFlags & DRXJ_ATV_CHANGED_OUTPUT) != 0) ) - { - u16_t data = 0; - - RR16( devAddr, ATV_TOP_STDBY__A, &data ); - if ( extAttr->enableCVBSOutput ) - { - data |=ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE; - } else { - data &= (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE); - } - - if ( extAttr->enableSIFOutput ) - { - data &= (~ATV_TOP_STDBY_SIF_STDBY_STANDBY); - } else { - data |= ATV_TOP_STDBY_SIF_STDBY_STANDBY; - } - WR16( devAddr, ATV_TOP_STDBY__A, data ); - } - - extAttr->atvCfgChangedFlags = 0; - - return (DRX_STS_OK); + /* noise filter setting */ + if (forceUpdate || + ((extAttr->atvCfgChangedFlags & DRXJ_ATV_CHANGED_NOISE_FLT) != 0)) { + WR16(devAddr, ATV_TOP_NOISE_TH__A, extAttr->atvTopNoiseTh); + } + + /* SIF attenuation */ + if (forceUpdate || + ((extAttr->atvCfgChangedFlags & DRXJ_ATV_CHANGED_SIF_ATT) != 0)) { + u16_t attenuation = 0; + + switch (extAttr->sifAttenuation) { + case DRXJ_SIF_ATTENUATION_0DB: + attenuation = ATV_TOP_AF_SIF_ATT_0DB; + break; + case DRXJ_SIF_ATTENUATION_3DB: + attenuation = ATV_TOP_AF_SIF_ATT_M3DB; + break; + case DRXJ_SIF_ATTENUATION_6DB: + attenuation = ATV_TOP_AF_SIF_ATT_M6DB; + break; + case DRXJ_SIF_ATTENUATION_9DB: + attenuation = ATV_TOP_AF_SIF_ATT_M9DB; + break; + default: + return DRX_STS_ERROR; + break; + } + WR16(devAddr, ATV_TOP_AF_SIF_ATT__A, attenuation); + } + + /* SIF & CVBS enable */ + if (forceUpdate || + ((extAttr->atvCfgChangedFlags & DRXJ_ATV_CHANGED_OUTPUT) != 0)) { + u16_t data = 0; + + RR16(devAddr, ATV_TOP_STDBY__A, &data); + if (extAttr->enableCVBSOutput) { + data |= ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE; + } else { + data &= (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE); + } + + if (extAttr->enableSIFOutput) { + data &= (~ATV_TOP_STDBY_SIF_STDBY_STANDBY); + } else { + data |= ATV_TOP_STDBY_SIF_STDBY_STANDBY; + } + WR16(devAddr, ATV_TOP_STDBY__A, data); + } + + extAttr->atvCfgChangedFlags = 0; + + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /* -------------------------------------------------------------------------- */ @@ -8705,56 +8376,50 @@ rw_error: * */ static DRXStatus_t -CtrlSetCfgATVOutput( pDRXDemodInstance_t demod, - pDRXJCfgAtvOutput_t outputCfg ) +CtrlSetCfgATVOutput(pDRXDemodInstance_t demod, pDRXJCfgAtvOutput_t outputCfg) { - pDRXJData_t extAttr = NULL; + pDRXJData_t extAttr = NULL; - /* Check arguments */ - if ( outputCfg == NULL ) - { - return (DRX_STS_INVALID_ARG); - } + /* Check arguments */ + if (outputCfg == NULL) { + return (DRX_STS_INVALID_ARG); + } - extAttr = (pDRXJData_t)demod->myExtAttr; - if ( outputCfg->enableSIFOutput ) - { - switch( outputCfg->sifAttenuation ){ - case DRXJ_SIF_ATTENUATION_0DB: /* fallthrough */ - case DRXJ_SIF_ATTENUATION_3DB: /* fallthrough */ - case DRXJ_SIF_ATTENUATION_6DB: /* fallthrough */ - case DRXJ_SIF_ATTENUATION_9DB: - /* Do nothing */ - break; - default: - return DRX_STS_INVALID_ARG; - break; - } - - if(extAttr->sifAttenuation != outputCfg->sifAttenuation ) - { - extAttr->sifAttenuation = outputCfg->sifAttenuation; - extAttr->atvCfgChangedFlags |= DRXJ_ATV_CHANGED_SIF_ATT; - } - } - - if ( extAttr->enableCVBSOutput != outputCfg->enableCVBSOutput ) - { - extAttr->enableCVBSOutput = outputCfg->enableCVBSOutput; - extAttr->atvCfgChangedFlags |= DRXJ_ATV_CHANGED_OUTPUT; - } + extAttr = (pDRXJData_t) demod->myExtAttr; + if (outputCfg->enableSIFOutput) { + switch (outputCfg->sifAttenuation) { + case DRXJ_SIF_ATTENUATION_0DB: /* fallthrough */ + case DRXJ_SIF_ATTENUATION_3DB: /* fallthrough */ + case DRXJ_SIF_ATTENUATION_6DB: /* fallthrough */ + case DRXJ_SIF_ATTENUATION_9DB: + /* Do nothing */ + break; + default: + return DRX_STS_INVALID_ARG; + break; + } + + if (extAttr->sifAttenuation != outputCfg->sifAttenuation) { + extAttr->sifAttenuation = outputCfg->sifAttenuation; + extAttr->atvCfgChangedFlags |= DRXJ_ATV_CHANGED_SIF_ATT; + } + } + + if (extAttr->enableCVBSOutput != outputCfg->enableCVBSOutput) { + extAttr->enableCVBSOutput = outputCfg->enableCVBSOutput; + extAttr->atvCfgChangedFlags |= DRXJ_ATV_CHANGED_OUTPUT; + } - if ( extAttr->enableSIFOutput != outputCfg->enableSIFOutput ) - { - extAttr->enableSIFOutput = outputCfg->enableSIFOutput; - extAttr->atvCfgChangedFlags |= DRXJ_ATV_CHANGED_OUTPUT; - } + if (extAttr->enableSIFOutput != outputCfg->enableSIFOutput) { + extAttr->enableSIFOutput = outputCfg->enableSIFOutput; + extAttr->atvCfgChangedFlags |= DRXJ_ATV_CHANGED_OUTPUT; + } - CHK_ERROR( AtvUpdateConfig(demod, FALSE) ); + CHK_ERROR(AtvUpdateConfig(demod, FALSE)); - return (DRX_STS_OK); + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /* -------------------------------------------------------------------------- */ @@ -8768,46 +8433,43 @@ rw_error: * */ static DRXStatus_t -CtrlSetCfgAtvEquCoef( pDRXDemodInstance_t demod , - pDRXJCfgAtvEquCoef_t coef) +CtrlSetCfgAtvEquCoef(pDRXDemodInstance_t demod, pDRXJCfgAtvEquCoef_t coef) { - pDRXJData_t extAttr = NULL; - int index; + pDRXJData_t extAttr = NULL; + int index; - extAttr = (pDRXJData_t)demod->myExtAttr; + extAttr = (pDRXJData_t) demod->myExtAttr; - /* current standard needs to be an ATV standard */ - if (!DRXJ_ISATVSTD(extAttr->standard )) - { - return DRX_STS_ERROR; - } - - /* Check arguments */ - if ( ( coef == NULL ) || - ( coef->coef0 > (ATV_TOP_EQU0_EQU_C0__M / 2) ) || - ( coef->coef1 > (ATV_TOP_EQU1_EQU_C1__M / 2) ) || - ( coef->coef2 > (ATV_TOP_EQU2_EQU_C2__M / 2) ) || - ( coef->coef3 > (ATV_TOP_EQU3_EQU_C3__M / 2) ) || - ( coef->coef0 < ((s16_t)~(ATV_TOP_EQU0_EQU_C0__M >> 1)) ) || - ( coef->coef1 < ((s16_t)~(ATV_TOP_EQU1_EQU_C1__M >> 1)) ) || - ( coef->coef2 < ((s16_t)~(ATV_TOP_EQU2_EQU_C2__M >> 1)) ) || - ( coef->coef3 < ((s16_t)~(ATV_TOP_EQU3_EQU_C3__M >> 1)) ) ) - { - return (DRX_STS_INVALID_ARG); - } + /* current standard needs to be an ATV standard */ + if (!DRXJ_ISATVSTD(extAttr->standard)) { + return DRX_STS_ERROR; + } + + /* Check arguments */ + if ((coef == NULL) || + (coef->coef0 > (ATV_TOP_EQU0_EQU_C0__M / 2)) || + (coef->coef1 > (ATV_TOP_EQU1_EQU_C1__M / 2)) || + (coef->coef2 > (ATV_TOP_EQU2_EQU_C2__M / 2)) || + (coef->coef3 > (ATV_TOP_EQU3_EQU_C3__M / 2)) || + (coef->coef0 < ((s16_t) ~ (ATV_TOP_EQU0_EQU_C0__M >> 1))) || + (coef->coef1 < ((s16_t) ~ (ATV_TOP_EQU1_EQU_C1__M >> 1))) || + (coef->coef2 < ((s16_t) ~ (ATV_TOP_EQU2_EQU_C2__M >> 1))) || + (coef->coef3 < ((s16_t) ~ (ATV_TOP_EQU3_EQU_C3__M >> 1)))) { + return (DRX_STS_INVALID_ARG); + } - CHK_ERROR(AtvEquCoefIndex( extAttr->standard, &index )); - extAttr->atvTopEqu0[index] = coef->coef0; - extAttr->atvTopEqu1[index] = coef->coef1; - extAttr->atvTopEqu2[index] = coef->coef2; - extAttr->atvTopEqu3[index] = coef->coef3; - extAttr->atvCfgChangedFlags |= DRXJ_ATV_CHANGED_COEF; + CHK_ERROR(AtvEquCoefIndex(extAttr->standard, &index)); + extAttr->atvTopEqu0[index] = coef->coef0; + extAttr->atvTopEqu1[index] = coef->coef1; + extAttr->atvTopEqu2[index] = coef->coef2; + extAttr->atvTopEqu3[index] = coef->coef3; + extAttr->atvCfgChangedFlags |= DRXJ_ATV_CHANGED_COEF; - CHK_ERROR( AtvUpdateConfig(demod, FALSE) ); + CHK_ERROR(AtvUpdateConfig(demod, FALSE)); - return (DRX_STS_OK); + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /* -------------------------------------------------------------------------- */ @@ -8825,35 +8487,32 @@ rw_error: * */ static DRXStatus_t -CtrlGetCfgAtvEquCoef( pDRXDemodInstance_t demod , - pDRXJCfgAtvEquCoef_t coef) +CtrlGetCfgAtvEquCoef(pDRXDemodInstance_t demod, pDRXJCfgAtvEquCoef_t coef) { - pDRXJData_t extAttr = NULL; - int index=0; + pDRXJData_t extAttr = NULL; + int index = 0; - extAttr = (pDRXJData_t)demod->myExtAttr; + extAttr = (pDRXJData_t) demod->myExtAttr; - /* current standard needs to be an ATV standard */ - if (!DRXJ_ISATVSTD(extAttr->standard )) - { - return DRX_STS_ERROR; - } + /* current standard needs to be an ATV standard */ + if (!DRXJ_ISATVSTD(extAttr->standard)) { + return DRX_STS_ERROR; + } - /* Check arguments */ - if ( coef == NULL ) - { - return DRX_STS_INVALID_ARG; - } + /* Check arguments */ + if (coef == NULL) { + return DRX_STS_INVALID_ARG; + } - CHK_ERROR(AtvEquCoefIndex( extAttr->standard, &index )); - coef->coef0 = extAttr->atvTopEqu0[index]; - coef->coef1 = extAttr->atvTopEqu1[index]; - coef->coef2 = extAttr->atvTopEqu2[index]; - coef->coef3 = extAttr->atvTopEqu3[index]; + CHK_ERROR(AtvEquCoefIndex(extAttr->standard, &index)); + coef->coef0 = extAttr->atvTopEqu0[index]; + coef->coef1 = extAttr->atvTopEqu1[index]; + coef->coef2 = extAttr->atvTopEqu2[index]; + coef->coef3 = extAttr->atvTopEqu3[index]; - return (DRX_STS_OK); + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /* -------------------------------------------------------------------------- */ @@ -8866,39 +8525,35 @@ rw_error: * */ static DRXStatus_t -CtrlSetCfgAtvMisc( pDRXDemodInstance_t demod , - pDRXJCfgAtvMisc_t settings ) +CtrlSetCfgAtvMisc(pDRXDemodInstance_t demod, pDRXJCfgAtvMisc_t settings) { - pDRXJData_t extAttr = NULL; + pDRXJData_t extAttr = NULL; - /* Check arguments */ - if ( ( settings == NULL ) || - ((settings->peakFilter) < (s16_t)(-8) ) || - ((settings->peakFilter) > (s16_t)(15) ) || - ((settings->noiseFilter) > 15 ) ) - { - return (DRX_STS_INVALID_ARG); - } /* if */ - - extAttr = (pDRXJData_t)demod->myExtAttr; + /* Check arguments */ + if ((settings == NULL) || + ((settings->peakFilter) < (s16_t) (-8)) || + ((settings->peakFilter) > (s16_t) (15)) || + ((settings->noiseFilter) > 15)) { + return (DRX_STS_INVALID_ARG); + } + /* if */ + extAttr = (pDRXJData_t) demod->myExtAttr; - if ( settings->peakFilter != extAttr->atvTopVidPeak ) - { - extAttr->atvTopVidPeak = settings->peakFilter; - extAttr->atvCfgChangedFlags |= DRXJ_ATV_CHANGED_PEAK_FLT; - } + if (settings->peakFilter != extAttr->atvTopVidPeak) { + extAttr->atvTopVidPeak = settings->peakFilter; + extAttr->atvCfgChangedFlags |= DRXJ_ATV_CHANGED_PEAK_FLT; + } - if ( settings->noiseFilter != extAttr->atvTopNoiseTh ) - { - extAttr->atvTopNoiseTh = settings->noiseFilter; - extAttr->atvCfgChangedFlags |= DRXJ_ATV_CHANGED_NOISE_FLT; - } + if (settings->noiseFilter != extAttr->atvTopNoiseTh) { + extAttr->atvTopNoiseTh = settings->noiseFilter; + extAttr->atvCfgChangedFlags |= DRXJ_ATV_CHANGED_NOISE_FLT; + } - CHK_ERROR( AtvUpdateConfig(demod, FALSE) ); + CHK_ERROR(AtvUpdateConfig(demod, FALSE)); - return (DRX_STS_OK); + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /* -------------------------------------------------------------------------- */ @@ -8915,23 +8570,21 @@ rw_error: * regitsers. */ static DRXStatus_t -CtrlGetCfgAtvMisc( pDRXDemodInstance_t demod , - pDRXJCfgAtvMisc_t settings ) +CtrlGetCfgAtvMisc(pDRXDemodInstance_t demod, pDRXJCfgAtvMisc_t settings) { - pDRXJData_t extAttr = NULL; + pDRXJData_t extAttr = NULL; - /* Check arguments */ - if ( settings == NULL ) - { - return DRX_STS_INVALID_ARG; - } + /* Check arguments */ + if (settings == NULL) { + return DRX_STS_INVALID_ARG; + } - extAttr = (pDRXJData_t)demod->myExtAttr; + extAttr = (pDRXJData_t) demod->myExtAttr; - settings->peakFilter = extAttr->atvTopVidPeak ; - settings->noiseFilter = extAttr->atvTopNoiseTh ; + settings->peakFilter = extAttr->atvTopVidPeak; + settings->noiseFilter = extAttr->atvTopNoiseTh; - return (DRX_STS_OK); + return (DRX_STS_OK); } /* -------------------------------------------------------------------------- */ @@ -8946,37 +8599,33 @@ CtrlGetCfgAtvMisc( pDRXDemodInstance_t demod , * */ static DRXStatus_t -CtrlGetCfgAtvOutput( pDRXDemodInstance_t demod , - pDRXJCfgAtvOutput_t outputCfg ) +CtrlGetCfgAtvOutput(pDRXDemodInstance_t demod, pDRXJCfgAtvOutput_t outputCfg) { - u16_t data = 0; + u16_t data = 0; - /* Check arguments */ - if ( outputCfg == NULL ) - { - return DRX_STS_INVALID_ARG; - } + /* Check arguments */ + if (outputCfg == NULL) { + return DRX_STS_INVALID_ARG; + } - RR16( demod->myI2CDevAddr, ATV_TOP_STDBY__A, &data ); - if ( data & ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE ) - { - outputCfg->enableCVBSOutput = TRUE; - } else { - outputCfg->enableCVBSOutput = FALSE; - } + RR16(demod->myI2CDevAddr, ATV_TOP_STDBY__A, &data); + if (data & ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE) { + outputCfg->enableCVBSOutput = TRUE; + } else { + outputCfg->enableCVBSOutput = FALSE; + } - if ( data & ATV_TOP_STDBY_SIF_STDBY_STANDBY ) - { - outputCfg->enableSIFOutput = FALSE; - } else { - outputCfg->enableSIFOutput = TRUE; - RR16( demod->myI2CDevAddr, ATV_TOP_AF_SIF_ATT__A, &data ); - outputCfg->sifAttenuation = (DRXJSIFAttenuation_t) data; - } - - return (DRX_STS_OK); + if (data & ATV_TOP_STDBY_SIF_STDBY_STANDBY) { + outputCfg->enableSIFOutput = FALSE; + } else { + outputCfg->enableSIFOutput = TRUE; + RR16(demod->myI2CDevAddr, ATV_TOP_AF_SIF_ATT__A, &data); + outputCfg->sifAttenuation = (DRXJSIFAttenuation_t) data; + } + + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /* -------------------------------------------------------------------------- */ @@ -8989,101 +8638,96 @@ rw_error: * */ static DRXStatus_t -CtrlGetCfgAtvAgcStatus( pDRXDemodInstance_t demod , - pDRXJCfgAtvAgcStatus_t agcStatus ) +CtrlGetCfgAtvAgcStatus(pDRXDemodInstance_t demod, + pDRXJCfgAtvAgcStatus_t agcStatus) { - pI2CDeviceAddr_t devAddr = NULL; - pDRXJData_t extAttr = NULL; - u16_t data = 0; - u32_t tmp = 0; + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + u16_t data = 0; + u32_t tmp = 0; - /* Check arguments */ - if ( agcStatus == NULL ) - { - return DRX_STS_INVALID_ARG; - } - - devAddr = demod -> myI2CDevAddr; - extAttr = (pDRXJData_t)demod->myExtAttr; - - /* - RFgain = (IQM_AF_AGC_RF__A * 26.75)/1000 (uA) - = ((IQM_AF_AGC_RF__A * 27) - (0.25*IQM_AF_AGC_RF__A))/1000 - - IQM_AF_AGC_RF__A * 27 is 20 bits worst case. - */ - RR16( devAddr, IQM_AF_AGC_RF__A, &data ); - tmp = ((u32_t)data) * 27 - ((u32_t)(data>>2)); /* nA */ - agcStatus->rfAgcGain = (u16_t)(tmp/1000) ; /* uA */ - /* rounding */ - if ( tmp%1000 >= 500 ) - { - (agcStatus->rfAgcGain)++; - } - - /* - IFgain = (IQM_AF_AGC_IF__A * 26.75)/1000 (uA) - = ((IQM_AF_AGC_IF__A * 27) - (0.25*IQM_AF_AGC_IF__A))/1000 - - IQM_AF_AGC_IF__A * 27 is 20 bits worst case. - */ - RR16( devAddr, IQM_AF_AGC_IF__A, &data ); - tmp = ((u32_t)data) * 27 - ((u32_t)(data>>2)); /* nA */ - agcStatus->ifAgcGain = (u16_t)(tmp/1000) ; /* uA */ - /* rounding */ - if ( tmp%1000 >= 500 ) - { - (agcStatus->ifAgcGain)++; - } - - /* - videoGain = (ATV_TOP_SFR_VID_GAIN__A/16 -150)* 0.05 (dB) - = (ATV_TOP_SFR_VID_GAIN__A/16 -150)/20 (dB) - = 10*(ATV_TOP_SFR_VID_GAIN__A/16 -150)/20 (in 0.1 dB) - = (ATV_TOP_SFR_VID_GAIN__A/16 -150)/2 (in 0.1 dB) - = (ATV_TOP_SFR_VID_GAIN__A/32) - 75 (in 0.1 dB) - */ - - SARR16( devAddr, SCU_RAM_ATV_VID_GAIN_HI__A , &data ); - /* dividing by 32 inclusive rounding */ - data >>=4; - if ((data & 1) !=0 ) - { - data++; - } - data >>= 1; - agcStatus->videoAgcGain = ((s16_t)data)-75; /* 0.1 dB */ - - /* - audioGain = (SCU_RAM_ATV_SIF_GAIN__A -8)* 0.05 (dB) - = (SCU_RAM_ATV_SIF_GAIN__A -8)/20 (dB) - = 10*(SCU_RAM_ATV_SIF_GAIN__A -8)/20 (in 0.1 dB) - = (SCU_RAM_ATV_SIF_GAIN__A -8)/2 (in 0.1 dB) - = (SCU_RAM_ATV_SIF_GAIN__A/2) - 4 (in 0.1 dB) - */ - - SARR16( devAddr, SCU_RAM_ATV_SIF_GAIN__A, &data ); - data &= SCU_RAM_ATV_SIF_GAIN__M; - /* dividing by 2 inclusive rounding */ - if ((data & 1) !=0 ) - { - data++; - } - data >>= 1; - agcStatus->audioAgcGain = ((s16_t)data)-4; /* 0.1 dB */ - - /* Loop gain's */ - SARR16( devAddr, SCU_RAM_AGC_KI__A, &data ); - agcStatus->videoAgcLoopGain = - ( (data & SCU_RAM_AGC_KI_DGAIN__M)>>SCU_RAM_AGC_KI_DGAIN__B) ; - agcStatus->rfAgcLoopGain = - ( (data & SCU_RAM_AGC_KI_RF__M)>>SCU_RAM_AGC_KI_RF__B) ; - agcStatus->ifAgcLoopGain = - ( (data & SCU_RAM_AGC_KI_IF__M)>>SCU_RAM_AGC_KI_IF__B) ; - - return (DRX_STS_OK); + /* Check arguments */ + if (agcStatus == NULL) { + return DRX_STS_INVALID_ARG; + } + + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; + + /* + RFgain = (IQM_AF_AGC_RF__A * 26.75)/1000 (uA) + = ((IQM_AF_AGC_RF__A * 27) - (0.25*IQM_AF_AGC_RF__A))/1000 + + IQM_AF_AGC_RF__A * 27 is 20 bits worst case. + */ + RR16(devAddr, IQM_AF_AGC_RF__A, &data); + tmp = ((u32_t) data) * 27 - ((u32_t) (data >> 2)); /* nA */ + agcStatus->rfAgcGain = (u16_t) (tmp / 1000); /* uA */ + /* rounding */ + if (tmp % 1000 >= 500) { + (agcStatus->rfAgcGain)++; + } + + /* + IFgain = (IQM_AF_AGC_IF__A * 26.75)/1000 (uA) + = ((IQM_AF_AGC_IF__A * 27) - (0.25*IQM_AF_AGC_IF__A))/1000 + + IQM_AF_AGC_IF__A * 27 is 20 bits worst case. + */ + RR16(devAddr, IQM_AF_AGC_IF__A, &data); + tmp = ((u32_t) data) * 27 - ((u32_t) (data >> 2)); /* nA */ + agcStatus->ifAgcGain = (u16_t) (tmp / 1000); /* uA */ + /* rounding */ + if (tmp % 1000 >= 500) { + (agcStatus->ifAgcGain)++; + } + + /* + videoGain = (ATV_TOP_SFR_VID_GAIN__A/16 -150)* 0.05 (dB) + = (ATV_TOP_SFR_VID_GAIN__A/16 -150)/20 (dB) + = 10*(ATV_TOP_SFR_VID_GAIN__A/16 -150)/20 (in 0.1 dB) + = (ATV_TOP_SFR_VID_GAIN__A/16 -150)/2 (in 0.1 dB) + = (ATV_TOP_SFR_VID_GAIN__A/32) - 75 (in 0.1 dB) + */ + + SARR16(devAddr, SCU_RAM_ATV_VID_GAIN_HI__A, &data); + /* dividing by 32 inclusive rounding */ + data >>= 4; + if ((data & 1) != 0) { + data++; + } + data >>= 1; + agcStatus->videoAgcGain = ((s16_t) data) - 75; /* 0.1 dB */ + + /* + audioGain = (SCU_RAM_ATV_SIF_GAIN__A -8)* 0.05 (dB) + = (SCU_RAM_ATV_SIF_GAIN__A -8)/20 (dB) + = 10*(SCU_RAM_ATV_SIF_GAIN__A -8)/20 (in 0.1 dB) + = (SCU_RAM_ATV_SIF_GAIN__A -8)/2 (in 0.1 dB) + = (SCU_RAM_ATV_SIF_GAIN__A/2) - 4 (in 0.1 dB) + */ + + SARR16(devAddr, SCU_RAM_ATV_SIF_GAIN__A, &data); + data &= SCU_RAM_ATV_SIF_GAIN__M; + /* dividing by 2 inclusive rounding */ + if ((data & 1) != 0) { + data++; + } + data >>= 1; + agcStatus->audioAgcGain = ((s16_t) data) - 4; /* 0.1 dB */ + + /* Loop gain's */ + SARR16(devAddr, SCU_RAM_AGC_KI__A, &data); + agcStatus->videoAgcLoopGain = + ((data & SCU_RAM_AGC_KI_DGAIN__M) >> SCU_RAM_AGC_KI_DGAIN__B); + agcStatus->rfAgcLoopGain = + ((data & SCU_RAM_AGC_KI_RF__M) >> SCU_RAM_AGC_KI_RF__B); + agcStatus->ifAgcLoopGain = + ((data & SCU_RAM_AGC_KI_IF__M) >> SCU_RAM_AGC_KI_IF__B); + + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /* -------------------------------------------------------------------------- */ @@ -9098,31 +8742,29 @@ rw_error: * * Starts ATV and IQM * * AUdio already started during standard init for ATV. */ -static DRXStatus_t -PowerUpATV( pDRXDemodInstance_t demod , DRXStandard_t standard ) +static DRXStatus_t PowerUpATV(pDRXDemodInstance_t demod, DRXStandard_t standard) { - pI2CDeviceAddr_t devAddr = NULL; - pDRXJData_t extAttr = NULL; - + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; - devAddr = demod -> myI2CDevAddr; - extAttr = (pDRXJData_t)demod->myExtAttr; + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; - /* ATV NTSC */ - WR16( devAddr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_ACTIVE ); - /* turn on IQM_AF */ - CHK_ERROR( SetIqmAf( demod, TRUE ) ); - CHK_ERROR(ADCSynchronization (demod)); + /* ATV NTSC */ + WR16(devAddr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_ACTIVE); + /* turn on IQM_AF */ + CHK_ERROR(SetIqmAf(demod, TRUE)); + CHK_ERROR(ADCSynchronization(demod)); - WR16( devAddr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE ); + WR16(devAddr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE); - /* Audio, already done during set standard */ + /* Audio, already done during set standard */ - return (DRX_STS_OK); + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } -#endif /* #ifndef DRXJ_DIGITAL_ONLY */ +#endif /* #ifndef DRXJ_DIGITAL_ONLY */ /* -------------------------------------------------------------------------- */ @@ -9138,52 +8780,50 @@ rw_error: * Calls audio power down */ static DRXStatus_t -PowerDownATV( pDRXDemodInstance_t demod , DRXStandard_t standard, Bool_t primary ) -{ - pI2CDeviceAddr_t devAddr = NULL; - DRXJSCUCmd_t cmdSCU = { /* command */ 0, - /* parameterLen */ 0, - /* resultLen */ 0, - /* *parameter */ NULL, - /* *result */ NULL }; - u16_t cmdResult = 0; - pDRXJData_t extAttr = NULL; - - devAddr = demod -> myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; - /* ATV NTSC */ - - /* Stop ATV SCU (will reset ATV and IQM hardware */ - cmdSCU.command = SCU_RAM_COMMAND_STANDARD_ATV | - SCU_RAM_COMMAND_CMD_DEMOD_STOP; - cmdSCU.parameterLen = 0; - cmdSCU.resultLen = 1; - cmdSCU.parameter = NULL; - cmdSCU.result = &cmdResult; - CHK_ERROR( SCUCommand( devAddr, &cmdSCU ) ); - /* Disable ATV outputs (ATV reset enables CVBS, undo this) */ - WR16 ( devAddr, ATV_TOP_STDBY__A, ( ATV_TOP_STDBY_SIF_STDBY_STANDBY & - (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE) ) ); - - WR16( devAddr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_STOP); - if (primary == TRUE) - { - WR16( devAddr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP ); - CHK_ERROR( SetIqmAf( demod, FALSE ) ); - } - else - { - WR16( devAddr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP ); - WR16( devAddr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP ); - WR16( devAddr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP ); - WR16( devAddr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP ); - WR16( devAddr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP ); - } - CHK_ERROR( PowerDownAud(demod) ); - - return (DRX_STS_OK); +PowerDownATV(pDRXDemodInstance_t demod, DRXStandard_t standard, Bool_t primary) +{ + pI2CDeviceAddr_t devAddr = NULL; + DRXJSCUCmd_t cmdSCU = { /* command */ 0, + /* parameterLen */ 0, + /* resultLen */ 0, + /* *parameter */ NULL, + /* *result */ NULL + }; + u16_t cmdResult = 0; + pDRXJData_t extAttr = NULL; + + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; + /* ATV NTSC */ + + /* Stop ATV SCU (will reset ATV and IQM hardware */ + cmdSCU.command = SCU_RAM_COMMAND_STANDARD_ATV | + SCU_RAM_COMMAND_CMD_DEMOD_STOP; + cmdSCU.parameterLen = 0; + cmdSCU.resultLen = 1; + cmdSCU.parameter = NULL; + cmdSCU.result = &cmdResult; + CHK_ERROR(SCUCommand(devAddr, &cmdSCU)); + /* Disable ATV outputs (ATV reset enables CVBS, undo this) */ + WR16(devAddr, ATV_TOP_STDBY__A, (ATV_TOP_STDBY_SIF_STDBY_STANDBY & + (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE))); + + WR16(devAddr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_STOP); + if (primary == TRUE) { + WR16(devAddr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP); + CHK_ERROR(SetIqmAf(demod, FALSE)); + } else { + WR16(devAddr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP); + WR16(devAddr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP); + WR16(devAddr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP); + WR16(devAddr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP); + WR16(devAddr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP); + } + CHK_ERROR(PowerDownAud(demod)); + + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /* -------------------------------------------------------------------------- */ @@ -9199,9 +8839,9 @@ rw_error: * */ #ifndef DRXJ_DIGITAL_ONLY -#define SCU_RAM_ATV_ENABLE_IIR_WA__A 0x831F6D /* TODO remove after done with reg import */ +#define SCU_RAM_ATV_ENABLE_IIR_WA__A 0x831F6D /* TODO remove after done with reg import */ static DRXStatus_t -SetATVStandard( pDRXDemodInstance_t demod , pDRXStandard_t standard ) +SetATVStandard(pDRXDemodInstance_t demod, pDRXStandard_t standard) { /* TODO: enable alternative for tap settings via external file @@ -9219,594 +8859,584 @@ switch DRXJ_ATV_COEF_FILE="customer_coefs.c.inc". Still to check if this will work; DRXJ_16TO8 macro may cause trouble ? */ - const u8_t ntsc_taps_re[]= { - DRXJ_16TO8(-12 ), /* re0 */ - DRXJ_16TO8(-9 ), /* re1 */ - DRXJ_16TO8( 9 ), /* re2 */ - DRXJ_16TO8( 19 ), /* re3 */ - DRXJ_16TO8(-4 ), /* re4 */ - DRXJ_16TO8(-24 ), /* re5 */ - DRXJ_16TO8(-6 ), /* re6 */ - DRXJ_16TO8( 16 ), /* re7 */ - DRXJ_16TO8( 6 ), /* re8 */ - DRXJ_16TO8(-16 ), /* re9 */ - DRXJ_16TO8(-5 ), /* re10 */ - DRXJ_16TO8( 13 ), /* re11 */ - DRXJ_16TO8(-2 ), /* re12 */ - DRXJ_16TO8(-20 ), /* re13 */ - DRXJ_16TO8( 4 ), /* re14 */ - DRXJ_16TO8( 25 ), /* re15 */ - DRXJ_16TO8(-6 ), /* re16 */ - DRXJ_16TO8(-36 ), /* re17 */ - DRXJ_16TO8( 2 ), /* re18 */ - DRXJ_16TO8( 38 ), /* re19 */ - DRXJ_16TO8(-10 ), /* re20 */ - DRXJ_16TO8(-48 ), /* re21 */ - DRXJ_16TO8( 35 ), /* re22 */ - DRXJ_16TO8( 94 ), /* re23 */ - DRXJ_16TO8(-59 ), /* re24 */ - DRXJ_16TO8(-217 ), /* re25 */ - DRXJ_16TO8( 50 ), /* re26 */ - DRXJ_16TO8( 679 ) /* re27 */ - }; - const u8_t ntsc_taps_im[]= { - DRXJ_16TO8( 11 ), /* im0 */ - DRXJ_16TO8( 1 ), /* im1 */ - DRXJ_16TO8(-10 ), /* im2 */ - DRXJ_16TO8( 2 ), /* im3 */ - DRXJ_16TO8( 24 ), /* im4 */ - DRXJ_16TO8( 21 ), /* im5 */ - DRXJ_16TO8( 1 ), /* im6 */ - DRXJ_16TO8(-4 ), /* im7 */ - DRXJ_16TO8( 7 ), /* im8 */ - DRXJ_16TO8( 14 ), /* im9 */ - DRXJ_16TO8( 27 ), /* im10 */ - DRXJ_16TO8( 42 ), /* im11 */ - DRXJ_16TO8( 22 ), /* im12 */ - DRXJ_16TO8(-20 ), /* im13 */ - DRXJ_16TO8( 2 ), /* im14 */ - DRXJ_16TO8( 98 ), /* im15 */ - DRXJ_16TO8( 122 ), /* im16 */ - DRXJ_16TO8( 0 ), /* im17 */ - DRXJ_16TO8(-85 ), /* im18 */ - DRXJ_16TO8( 51 ), /* im19 */ - DRXJ_16TO8( 247 ), /* im20 */ - DRXJ_16TO8( 192 ), /* im21 */ - DRXJ_16TO8(-55 ), /* im22 */ - DRXJ_16TO8(-95 ), /* im23 */ - DRXJ_16TO8( 217 ), /* im24 */ - DRXJ_16TO8( 544 ), /* im25 */ - DRXJ_16TO8( 553 ), /* im26 */ - DRXJ_16TO8( 302 ) /* im27 */ - }; - const u8_t bg_taps_re[]= { - DRXJ_16TO8(-18 ), /* re0 */ - DRXJ_16TO8( 18 ), /* re1 */ - DRXJ_16TO8( 19 ), /* re2 */ - DRXJ_16TO8(-26 ), /* re3 */ - DRXJ_16TO8(-20 ), /* re4 */ - DRXJ_16TO8( 36 ), /* re5 */ - DRXJ_16TO8( 5 ), /* re6 */ - DRXJ_16TO8(-51 ), /* re7 */ - DRXJ_16TO8( 15 ), /* re8 */ - DRXJ_16TO8( 45 ), /* re9 */ - DRXJ_16TO8(-46 ), /* re10 */ - DRXJ_16TO8(-24 ), /* re11 */ - DRXJ_16TO8( 71 ), /* re12 */ - DRXJ_16TO8(-17 ), /* re13 */ - DRXJ_16TO8(-83 ), /* re14 */ - DRXJ_16TO8( 74 ), /* re15 */ - DRXJ_16TO8( 75 ), /* re16 */ - DRXJ_16TO8(-134 ), /* re17 */ - DRXJ_16TO8(-40 ), /* re18 */ - DRXJ_16TO8( 191 ), /* re19 */ - DRXJ_16TO8(-11 ), /* re20 */ - DRXJ_16TO8(-233 ), /* re21 */ - DRXJ_16TO8( 74 ), /* re22 */ - DRXJ_16TO8( 271 ), /* re23 */ - DRXJ_16TO8(-132 ), /* re24 */ - DRXJ_16TO8(-341 ), /* re25 */ - DRXJ_16TO8( 172 ), /* re26 */ - DRXJ_16TO8( 801 ) /* re27 */ - }; - const u8_t bg_taps_im[]= { - DRXJ_16TO8(-24 ), /* im0 */ - DRXJ_16TO8(-10 ), /* im1 */ - DRXJ_16TO8( 9 ), /* im2 */ - DRXJ_16TO8(-5 ), /* im3 */ - DRXJ_16TO8(-51 ), /* im4 */ - DRXJ_16TO8(-17 ), /* im5 */ - DRXJ_16TO8( 31 ), /* im6 */ - DRXJ_16TO8(-48 ), /* im7 */ - DRXJ_16TO8(-95 ), /* im8 */ - DRXJ_16TO8( 25 ), /* im9 */ - DRXJ_16TO8( 37 ), /* im10 */ - DRXJ_16TO8(-123 ), /* im11 */ - DRXJ_16TO8(-77 ), /* im12 */ - DRXJ_16TO8( 94 ), /* im13 */ - DRXJ_16TO8(-10 ), /* im14 */ - DRXJ_16TO8(-149 ), /* im15 */ - DRXJ_16TO8( 10 ), /* im16 */ - DRXJ_16TO8( 108 ), /* im17 */ - DRXJ_16TO8(-49 ), /* im18 */ - DRXJ_16TO8(-59 ), /* im19 */ - DRXJ_16TO8( 90 ), /* im20 */ - DRXJ_16TO8( 73 ), /* im21 */ - DRXJ_16TO8( 55 ), /* im22 */ - DRXJ_16TO8( 148 ), /* im23 */ - DRXJ_16TO8( 86 ), /* im24 */ - DRXJ_16TO8( 146 ), /* im25 */ - DRXJ_16TO8( 687 ), /* im26 */ - DRXJ_16TO8( 877 ) /* im27 */ - }; - const u8_t dk_i_l_lp_taps_re[]= { - DRXJ_16TO8(-23 ), /* re0 */ - DRXJ_16TO8( 9 ), /* re1 */ - DRXJ_16TO8( 16 ), /* re2 */ - DRXJ_16TO8(-26 ), /* re3 */ - DRXJ_16TO8(-3 ), /* re4 */ - DRXJ_16TO8( 13 ), /* re5 */ - DRXJ_16TO8(-19 ), /* re6 */ - DRXJ_16TO8(-3 ), /* re7 */ - DRXJ_16TO8( 13 ), /* re8 */ - DRXJ_16TO8(-26 ), /* re9 */ - DRXJ_16TO8(-4 ), /* re10 */ - DRXJ_16TO8( 28 ), /* re11 */ - DRXJ_16TO8(-15 ), /* re12 */ - DRXJ_16TO8(-14 ), /* re13 */ - DRXJ_16TO8( 10 ), /* re14 */ - DRXJ_16TO8( 1 ), /* re15 */ - DRXJ_16TO8( 39 ), /* re16 */ - DRXJ_16TO8(-18 ), /* re17 */ - DRXJ_16TO8(-90 ), /* re18 */ - DRXJ_16TO8( 109 ), /* re19 */ - DRXJ_16TO8( 113 ), /* re20 */ - DRXJ_16TO8(-235 ), /* re21 */ - DRXJ_16TO8(-49 ), /* re22 */ - DRXJ_16TO8( 359 ), /* re23 */ - DRXJ_16TO8(-79 ), /* re24 */ - DRXJ_16TO8(-459 ), /* re25 */ - DRXJ_16TO8( 206 ), /* re26 */ - DRXJ_16TO8( 894 ) /* re27 */ - }; - const u8_t dk_i_l_lp_taps_im[]= { - DRXJ_16TO8(-8 ), /* im0 */ - DRXJ_16TO8(-20 ), /* im1 */ - DRXJ_16TO8( 17 ), /* im2 */ - DRXJ_16TO8(-14 ), /* im3 */ - DRXJ_16TO8(-52 ), /* im4 */ - DRXJ_16TO8( 4 ), /* im5 */ - DRXJ_16TO8( 9 ), /* im6 */ - DRXJ_16TO8(-62 ), /* im7 */ - DRXJ_16TO8(-47 ), /* im8 */ - DRXJ_16TO8( 0 ), /* im9 */ - DRXJ_16TO8(-20 ), /* im10 */ - DRXJ_16TO8(-48 ), /* im11 */ - DRXJ_16TO8(-65 ), /* im12 */ - DRXJ_16TO8(-23 ), /* im13 */ - DRXJ_16TO8( 44 ), /* im14 */ - DRXJ_16TO8(-60 ), /* im15 */ - DRXJ_16TO8(-113 ), /* im16 */ - DRXJ_16TO8( 92 ), /* im17 */ - DRXJ_16TO8( 81 ), /* im18 */ - DRXJ_16TO8(-125 ), /* im19 */ - DRXJ_16TO8( 28 ), /* im20 */ - DRXJ_16TO8( 182 ), /* im21 */ - DRXJ_16TO8( 35 ), /* im22 */ - DRXJ_16TO8( 94 ), /* im23 */ - DRXJ_16TO8( 180 ), /* im24 */ - DRXJ_16TO8( 134 ), /* im25 */ - DRXJ_16TO8( 657 ), /* im26 */ - DRXJ_16TO8( 1023 ) /* im27 */ - }; - const u8_t fm_taps_re[]= { - DRXJ_16TO8( 0 ), /* re0 */ - DRXJ_16TO8( 0 ), /* re1 */ - DRXJ_16TO8( 0 ), /* re2 */ - DRXJ_16TO8( 0 ), /* re3 */ - DRXJ_16TO8( 0 ), /* re4 */ - DRXJ_16TO8( 0 ), /* re5 */ - DRXJ_16TO8( 0 ), /* re6 */ - DRXJ_16TO8( 0 ), /* re7 */ - DRXJ_16TO8( 0 ), /* re8 */ - DRXJ_16TO8( 0 ), /* re9 */ - DRXJ_16TO8( 0 ), /* re10 */ - DRXJ_16TO8( 0 ), /* re11 */ - DRXJ_16TO8( 0 ), /* re12 */ - DRXJ_16TO8( 0 ), /* re13 */ - DRXJ_16TO8( 0 ), /* re14 */ - DRXJ_16TO8( 0 ), /* re15 */ - DRXJ_16TO8( 0 ), /* re16 */ - DRXJ_16TO8( 0 ), /* re17 */ - DRXJ_16TO8( 0 ), /* re18 */ - DRXJ_16TO8( 0 ), /* re19 */ - DRXJ_16TO8( 0 ), /* re20 */ - DRXJ_16TO8( 0 ), /* re21 */ - DRXJ_16TO8( 0 ), /* re22 */ - DRXJ_16TO8( 0 ), /* re23 */ - DRXJ_16TO8( 0 ), /* re24 */ - DRXJ_16TO8( 0 ), /* re25 */ - DRXJ_16TO8( 0 ), /* re26 */ - DRXJ_16TO8( 0 ) /* re27 */ - }; - const u8_t fm_taps_im[]= { - DRXJ_16TO8(-6 ), /* im0 */ - DRXJ_16TO8( 2 ), /* im1 */ - DRXJ_16TO8( 14 ), /* im2 */ - DRXJ_16TO8(-38 ), /* im3 */ - DRXJ_16TO8( 58 ), /* im4 */ - DRXJ_16TO8(-62 ), /* im5 */ - DRXJ_16TO8( 42 ), /* im6 */ - DRXJ_16TO8( 0 ), /* im7 */ - DRXJ_16TO8(-45 ), /* im8 */ - DRXJ_16TO8( 73 ), /* im9 */ - DRXJ_16TO8(-65 ), /* im10 */ - DRXJ_16TO8( 23 ), /* im11 */ - DRXJ_16TO8( 34 ), /* im12 */ - DRXJ_16TO8(-77 ), /* im13 */ - DRXJ_16TO8( 80 ), /* im14 */ - DRXJ_16TO8(-39 ), /* im15 */ - DRXJ_16TO8(-25 ), /* im16 */ - DRXJ_16TO8( 78 ), /* im17 */ - DRXJ_16TO8(-90 ), /* im18 */ - DRXJ_16TO8( 52 ), /* im19 */ - DRXJ_16TO8( 16 ), /* im20 */ - DRXJ_16TO8(-77 ), /* im21 */ - DRXJ_16TO8( 97 ), /* im22 */ - DRXJ_16TO8(-62 ), /* im23 */ - DRXJ_16TO8(-8 ), /* im24 */ - DRXJ_16TO8( 75 ), /* im25 */ - DRXJ_16TO8(-100 ), /* im26 */ - DRXJ_16TO8( 70 ) /* im27 */ - }; - - pI2CDeviceAddr_t devAddr = NULL; - DRXJSCUCmd_t cmdSCU = { /* command */ 0, - /* parameterLen */ 0, - /* resultLen */ 0, - /* *parameter */ NULL, - /* *result */ NULL }; - u16_t cmdResult = 0; - u16_t cmdParam = 0; + const u8_t ntsc_taps_re[] = { + DRXJ_16TO8(-12), /* re0 */ + DRXJ_16TO8(-9), /* re1 */ + DRXJ_16TO8(9), /* re2 */ + DRXJ_16TO8(19), /* re3 */ + DRXJ_16TO8(-4), /* re4 */ + DRXJ_16TO8(-24), /* re5 */ + DRXJ_16TO8(-6), /* re6 */ + DRXJ_16TO8(16), /* re7 */ + DRXJ_16TO8(6), /* re8 */ + DRXJ_16TO8(-16), /* re9 */ + DRXJ_16TO8(-5), /* re10 */ + DRXJ_16TO8(13), /* re11 */ + DRXJ_16TO8(-2), /* re12 */ + DRXJ_16TO8(-20), /* re13 */ + DRXJ_16TO8(4), /* re14 */ + DRXJ_16TO8(25), /* re15 */ + DRXJ_16TO8(-6), /* re16 */ + DRXJ_16TO8(-36), /* re17 */ + DRXJ_16TO8(2), /* re18 */ + DRXJ_16TO8(38), /* re19 */ + DRXJ_16TO8(-10), /* re20 */ + DRXJ_16TO8(-48), /* re21 */ + DRXJ_16TO8(35), /* re22 */ + DRXJ_16TO8(94), /* re23 */ + DRXJ_16TO8(-59), /* re24 */ + DRXJ_16TO8(-217), /* re25 */ + DRXJ_16TO8(50), /* re26 */ + DRXJ_16TO8(679) /* re27 */ + }; + const u8_t ntsc_taps_im[] = { + DRXJ_16TO8(11), /* im0 */ + DRXJ_16TO8(1), /* im1 */ + DRXJ_16TO8(-10), /* im2 */ + DRXJ_16TO8(2), /* im3 */ + DRXJ_16TO8(24), /* im4 */ + DRXJ_16TO8(21), /* im5 */ + DRXJ_16TO8(1), /* im6 */ + DRXJ_16TO8(-4), /* im7 */ + DRXJ_16TO8(7), /* im8 */ + DRXJ_16TO8(14), /* im9 */ + DRXJ_16TO8(27), /* im10 */ + DRXJ_16TO8(42), /* im11 */ + DRXJ_16TO8(22), /* im12 */ + DRXJ_16TO8(-20), /* im13 */ + DRXJ_16TO8(2), /* im14 */ + DRXJ_16TO8(98), /* im15 */ + DRXJ_16TO8(122), /* im16 */ + DRXJ_16TO8(0), /* im17 */ + DRXJ_16TO8(-85), /* im18 */ + DRXJ_16TO8(51), /* im19 */ + DRXJ_16TO8(247), /* im20 */ + DRXJ_16TO8(192), /* im21 */ + DRXJ_16TO8(-55), /* im22 */ + DRXJ_16TO8(-95), /* im23 */ + DRXJ_16TO8(217), /* im24 */ + DRXJ_16TO8(544), /* im25 */ + DRXJ_16TO8(553), /* im26 */ + DRXJ_16TO8(302) /* im27 */ + }; + const u8_t bg_taps_re[] = { + DRXJ_16TO8(-18), /* re0 */ + DRXJ_16TO8(18), /* re1 */ + DRXJ_16TO8(19), /* re2 */ + DRXJ_16TO8(-26), /* re3 */ + DRXJ_16TO8(-20), /* re4 */ + DRXJ_16TO8(36), /* re5 */ + DRXJ_16TO8(5), /* re6 */ + DRXJ_16TO8(-51), /* re7 */ + DRXJ_16TO8(15), /* re8 */ + DRXJ_16TO8(45), /* re9 */ + DRXJ_16TO8(-46), /* re10 */ + DRXJ_16TO8(-24), /* re11 */ + DRXJ_16TO8(71), /* re12 */ + DRXJ_16TO8(-17), /* re13 */ + DRXJ_16TO8(-83), /* re14 */ + DRXJ_16TO8(74), /* re15 */ + DRXJ_16TO8(75), /* re16 */ + DRXJ_16TO8(-134), /* re17 */ + DRXJ_16TO8(-40), /* re18 */ + DRXJ_16TO8(191), /* re19 */ + DRXJ_16TO8(-11), /* re20 */ + DRXJ_16TO8(-233), /* re21 */ + DRXJ_16TO8(74), /* re22 */ + DRXJ_16TO8(271), /* re23 */ + DRXJ_16TO8(-132), /* re24 */ + DRXJ_16TO8(-341), /* re25 */ + DRXJ_16TO8(172), /* re26 */ + DRXJ_16TO8(801) /* re27 */ + }; + const u8_t bg_taps_im[] = { + DRXJ_16TO8(-24), /* im0 */ + DRXJ_16TO8(-10), /* im1 */ + DRXJ_16TO8(9), /* im2 */ + DRXJ_16TO8(-5), /* im3 */ + DRXJ_16TO8(-51), /* im4 */ + DRXJ_16TO8(-17), /* im5 */ + DRXJ_16TO8(31), /* im6 */ + DRXJ_16TO8(-48), /* im7 */ + DRXJ_16TO8(-95), /* im8 */ + DRXJ_16TO8(25), /* im9 */ + DRXJ_16TO8(37), /* im10 */ + DRXJ_16TO8(-123), /* im11 */ + DRXJ_16TO8(-77), /* im12 */ + DRXJ_16TO8(94), /* im13 */ + DRXJ_16TO8(-10), /* im14 */ + DRXJ_16TO8(-149), /* im15 */ + DRXJ_16TO8(10), /* im16 */ + DRXJ_16TO8(108), /* im17 */ + DRXJ_16TO8(-49), /* im18 */ + DRXJ_16TO8(-59), /* im19 */ + DRXJ_16TO8(90), /* im20 */ + DRXJ_16TO8(73), /* im21 */ + DRXJ_16TO8(55), /* im22 */ + DRXJ_16TO8(148), /* im23 */ + DRXJ_16TO8(86), /* im24 */ + DRXJ_16TO8(146), /* im25 */ + DRXJ_16TO8(687), /* im26 */ + DRXJ_16TO8(877) /* im27 */ + }; + const u8_t dk_i_l_lp_taps_re[] = { + DRXJ_16TO8(-23), /* re0 */ + DRXJ_16TO8(9), /* re1 */ + DRXJ_16TO8(16), /* re2 */ + DRXJ_16TO8(-26), /* re3 */ + DRXJ_16TO8(-3), /* re4 */ + DRXJ_16TO8(13), /* re5 */ + DRXJ_16TO8(-19), /* re6 */ + DRXJ_16TO8(-3), /* re7 */ + DRXJ_16TO8(13), /* re8 */ + DRXJ_16TO8(-26), /* re9 */ + DRXJ_16TO8(-4), /* re10 */ + DRXJ_16TO8(28), /* re11 */ + DRXJ_16TO8(-15), /* re12 */ + DRXJ_16TO8(-14), /* re13 */ + DRXJ_16TO8(10), /* re14 */ + DRXJ_16TO8(1), /* re15 */ + DRXJ_16TO8(39), /* re16 */ + DRXJ_16TO8(-18), /* re17 */ + DRXJ_16TO8(-90), /* re18 */ + DRXJ_16TO8(109), /* re19 */ + DRXJ_16TO8(113), /* re20 */ + DRXJ_16TO8(-235), /* re21 */ + DRXJ_16TO8(-49), /* re22 */ + DRXJ_16TO8(359), /* re23 */ + DRXJ_16TO8(-79), /* re24 */ + DRXJ_16TO8(-459), /* re25 */ + DRXJ_16TO8(206), /* re26 */ + DRXJ_16TO8(894) /* re27 */ + }; + const u8_t dk_i_l_lp_taps_im[] = { + DRXJ_16TO8(-8), /* im0 */ + DRXJ_16TO8(-20), /* im1 */ + DRXJ_16TO8(17), /* im2 */ + DRXJ_16TO8(-14), /* im3 */ + DRXJ_16TO8(-52), /* im4 */ + DRXJ_16TO8(4), /* im5 */ + DRXJ_16TO8(9), /* im6 */ + DRXJ_16TO8(-62), /* im7 */ + DRXJ_16TO8(-47), /* im8 */ + DRXJ_16TO8(0), /* im9 */ + DRXJ_16TO8(-20), /* im10 */ + DRXJ_16TO8(-48), /* im11 */ + DRXJ_16TO8(-65), /* im12 */ + DRXJ_16TO8(-23), /* im13 */ + DRXJ_16TO8(44), /* im14 */ + DRXJ_16TO8(-60), /* im15 */ + DRXJ_16TO8(-113), /* im16 */ + DRXJ_16TO8(92), /* im17 */ + DRXJ_16TO8(81), /* im18 */ + DRXJ_16TO8(-125), /* im19 */ + DRXJ_16TO8(28), /* im20 */ + DRXJ_16TO8(182), /* im21 */ + DRXJ_16TO8(35), /* im22 */ + DRXJ_16TO8(94), /* im23 */ + DRXJ_16TO8(180), /* im24 */ + DRXJ_16TO8(134), /* im25 */ + DRXJ_16TO8(657), /* im26 */ + DRXJ_16TO8(1023) /* im27 */ + }; + const u8_t fm_taps_re[] = { + DRXJ_16TO8(0), /* re0 */ + DRXJ_16TO8(0), /* re1 */ + DRXJ_16TO8(0), /* re2 */ + DRXJ_16TO8(0), /* re3 */ + DRXJ_16TO8(0), /* re4 */ + DRXJ_16TO8(0), /* re5 */ + DRXJ_16TO8(0), /* re6 */ + DRXJ_16TO8(0), /* re7 */ + DRXJ_16TO8(0), /* re8 */ + DRXJ_16TO8(0), /* re9 */ + DRXJ_16TO8(0), /* re10 */ + DRXJ_16TO8(0), /* re11 */ + DRXJ_16TO8(0), /* re12 */ + DRXJ_16TO8(0), /* re13 */ + DRXJ_16TO8(0), /* re14 */ + DRXJ_16TO8(0), /* re15 */ + DRXJ_16TO8(0), /* re16 */ + DRXJ_16TO8(0), /* re17 */ + DRXJ_16TO8(0), /* re18 */ + DRXJ_16TO8(0), /* re19 */ + DRXJ_16TO8(0), /* re20 */ + DRXJ_16TO8(0), /* re21 */ + DRXJ_16TO8(0), /* re22 */ + DRXJ_16TO8(0), /* re23 */ + DRXJ_16TO8(0), /* re24 */ + DRXJ_16TO8(0), /* re25 */ + DRXJ_16TO8(0), /* re26 */ + DRXJ_16TO8(0) /* re27 */ + }; + const u8_t fm_taps_im[] = { + DRXJ_16TO8(-6), /* im0 */ + DRXJ_16TO8(2), /* im1 */ + DRXJ_16TO8(14), /* im2 */ + DRXJ_16TO8(-38), /* im3 */ + DRXJ_16TO8(58), /* im4 */ + DRXJ_16TO8(-62), /* im5 */ + DRXJ_16TO8(42), /* im6 */ + DRXJ_16TO8(0), /* im7 */ + DRXJ_16TO8(-45), /* im8 */ + DRXJ_16TO8(73), /* im9 */ + DRXJ_16TO8(-65), /* im10 */ + DRXJ_16TO8(23), /* im11 */ + DRXJ_16TO8(34), /* im12 */ + DRXJ_16TO8(-77), /* im13 */ + DRXJ_16TO8(80), /* im14 */ + DRXJ_16TO8(-39), /* im15 */ + DRXJ_16TO8(-25), /* im16 */ + DRXJ_16TO8(78), /* im17 */ + DRXJ_16TO8(-90), /* im18 */ + DRXJ_16TO8(52), /* im19 */ + DRXJ_16TO8(16), /* im20 */ + DRXJ_16TO8(-77), /* im21 */ + DRXJ_16TO8(97), /* im22 */ + DRXJ_16TO8(-62), /* im23 */ + DRXJ_16TO8(-8), /* im24 */ + DRXJ_16TO8(75), /* im25 */ + DRXJ_16TO8(-100), /* im26 */ + DRXJ_16TO8(70) /* im27 */ + }; + + pI2CDeviceAddr_t devAddr = NULL; + DRXJSCUCmd_t cmdSCU = { /* command */ 0, + /* parameterLen */ 0, + /* resultLen */ 0, + /* *parameter */ NULL, + /* *result */ NULL + }; + u16_t cmdResult = 0; + u16_t cmdParam = 0; #ifdef DRXJ_SPLIT_UCODE_UPLOAD - DRXUCodeInfo_t ucodeInfo; - pDRXCommonAttr_t commonAttr = NULL; + DRXUCodeInfo_t ucodeInfo; + pDRXCommonAttr_t commonAttr = NULL; #endif /* DRXJ_SPLIT_UCODE_UPLOAD */ - pDRXJData_t extAttr = NULL; + pDRXJData_t extAttr = NULL; - extAttr = (pDRXJData_t)demod->myExtAttr; - devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; + devAddr = demod->myI2CDevAddr; #ifdef DRXJ_SPLIT_UCODE_UPLOAD - commonAttr = demod -> myCommonAttr; + commonAttr = demod->myCommonAttr; - /* Check if audio microcode is already uploaded */ - if ( !( extAttr->flagAudMcUploaded ) ) - { - ucodeInfo.mcData = commonAttr->microcode; - ucodeInfo.mcSize = commonAttr->microcodeSize; + /* Check if audio microcode is already uploaded */ + if (!(extAttr->flagAudMcUploaded)) { + ucodeInfo.mcData = commonAttr->microcode; + ucodeInfo.mcSize = commonAttr->microcodeSize; - /* Upload only audio microcode */ - CHK_ERROR ( CtrlUCodeUpload( demod, &ucodeInfo, UCODE_UPLOAD, TRUE ) ); + /* Upload only audio microcode */ + CHK_ERROR(CtrlUCodeUpload + (demod, &ucodeInfo, UCODE_UPLOAD, TRUE)); - if ( commonAttr->verifyMicrocode == TRUE ) - { - CHK_ERROR( CtrlUCodeUpload( demod, &ucodeInfo, UCODE_VERIFY, TRUE ) ); - } + if (commonAttr->verifyMicrocode == TRUE) { + CHK_ERROR(CtrlUCodeUpload + (demod, &ucodeInfo, UCODE_VERIFY, TRUE)); + } - /* Prevent uploading audio microcode again */ - extAttr->flagAudMcUploaded = TRUE; - } + /* Prevent uploading audio microcode again */ + extAttr->flagAudMcUploaded = TRUE; + } #endif /* DRXJ_SPLIT_UCODE_UPLOAD */ - WR16( devAddr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_STOP ); - WR16( devAddr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP ); - WR16( devAddr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP ); - WR16( devAddr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP ); - WR16( devAddr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP ); - WR16( devAddr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP ); - /* Reset ATV SCU */ - cmdSCU.command = SCU_RAM_COMMAND_STANDARD_ATV | - SCU_RAM_COMMAND_CMD_DEMOD_RESET; - cmdSCU.parameterLen = 0; - cmdSCU.resultLen = 1; - cmdSCU.parameter = NULL; - cmdSCU.result = &cmdResult; - CHK_ERROR( SCUCommand( devAddr, &cmdSCU ) ); - - WR16( devAddr, ATV_TOP_MOD_CONTROL__A, ATV_TOP_MOD_CONTROL__PRE ); - - /* TODO remove AUTO/OFF patches after ucode fix. */ - switch ( *standard ) - { - case DRX_STANDARD_NTSC: - /* NTSC */ - cmdParam = SCU_RAM_ATV_STANDARD_STANDARD_MN; - - WR16( devAddr, IQM_RT_LO_INCR__A , IQM_RT_LO_INCR_MN ); - WR16( devAddr, IQM_CF_MIDTAP__A , IQM_CF_MIDTAP_RE__M ); - WRB ( devAddr, IQM_CF_TAP_RE0__A , sizeof(ntsc_taps_re) , - ((pu8_t)ntsc_taps_re) ); - WRB ( devAddr, IQM_CF_TAP_IM0__A , sizeof(ntsc_taps_im) , - ((pu8_t)ntsc_taps_im) ); - - WR16( devAddr, ATV_TOP_CR_AMP_TH__A , ATV_TOP_CR_AMP_TH_MN ); - WR16( devAddr, ATV_TOP_CR_CONT__A , - ( ATV_TOP_CR_CONT_CR_P_MN | - ATV_TOP_CR_CONT_CR_D_MN | - ATV_TOP_CR_CONT_CR_I_MN ) ); - WR16( devAddr, ATV_TOP_CR_OVM_TH__A , ATV_TOP_CR_OVM_TH_MN ); - WR16( devAddr, ATV_TOP_STD__A , (ATV_TOP_STD_MODE_MN | - ATV_TOP_STD_VID_POL_MN ) ); - WR16( devAddr, ATV_TOP_VID_AMP__A , ATV_TOP_VID_AMP_MN ); - - WR16( devAddr, SCU_RAM_ATV_AGC_MODE__A, - ( SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM | - SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE ) ); - WR16( devAddr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000 ); - WR16( devAddr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000 ); - WR16( devAddr, SCU_RAM_ATV_AMS_MAX_REF__A, - SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_BG_MN); - extAttr->phaseCorrectionBypass = FALSE; - extAttr->enableCVBSOutput = TRUE; - break; - case DRX_STANDARD_FM: - /* FM */ - cmdParam = SCU_RAM_ATV_STANDARD_STANDARD_FM; - - WR16( devAddr, IQM_RT_LO_INCR__A , 2994 ); - WR16( devAddr, IQM_CF_MIDTAP__A , 0 ); - WRB ( devAddr, IQM_CF_TAP_RE0__A , sizeof(fm_taps_re) , - ((pu8_t)fm_taps_re) ); - WRB ( devAddr, IQM_CF_TAP_IM0__A , sizeof(fm_taps_im) , - ((pu8_t)fm_taps_im) ); - WR16( devAddr, ATV_TOP_STD__A , (ATV_TOP_STD_MODE_FM | - ATV_TOP_STD_VID_POL_FM ) ); - WR16( devAddr, ATV_TOP_MOD_CONTROL__A, 0 ); - WR16( devAddr, ATV_TOP_CR_CONT__A , 0 ); - - WR16( devAddr, SCU_RAM_ATV_AGC_MODE__A , - ( SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW | - SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM )); - WR16( devAddr, IQM_RT_ROT_BP__A, IQM_RT_ROT_BP_ROT_OFF_OFF ); - extAttr->phaseCorrectionBypass = TRUE; - extAttr->enableCVBSOutput = FALSE; - break; - case DRX_STANDARD_PAL_SECAM_BG: - /* PAL/SECAM B/G */ - cmdParam = SCU_RAM_ATV_STANDARD_STANDARD_B; - - WR16( devAddr, IQM_RT_LO_INCR__A , 1820 );/* TODO check with IS */ - WR16( devAddr, IQM_CF_MIDTAP__A , IQM_CF_MIDTAP_RE__M ); - WRB ( devAddr, IQM_CF_TAP_RE0__A , sizeof(bg_taps_re) , - ((pu8_t)bg_taps_re) ); - WRB ( devAddr, IQM_CF_TAP_IM0__A , sizeof(bg_taps_im) , - ((pu8_t)bg_taps_im) ); - WR16( devAddr, ATV_TOP_VID_AMP__A , ATV_TOP_VID_AMP_BG ); - WR16( devAddr, ATV_TOP_CR_AMP_TH__A, ATV_TOP_CR_AMP_TH_BG ); - WR16( devAddr, ATV_TOP_CR_CONT__A , - ( ATV_TOP_CR_CONT_CR_P_BG | - ATV_TOP_CR_CONT_CR_D_BG | - ATV_TOP_CR_CONT_CR_I_BG ) ); - WR16( devAddr, ATV_TOP_CR_OVM_TH__A , ATV_TOP_CR_OVM_TH_BG ); - WR16( devAddr, ATV_TOP_STD__A , (ATV_TOP_STD_MODE_BG | - ATV_TOP_STD_VID_POL_BG ) ); - WR16( devAddr, SCU_RAM_ATV_AGC_MODE__A , - ( SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM | - SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE ) ); - WR16( devAddr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000 ); - WR16( devAddr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000 ); - WR16( devAddr, SCU_RAM_ATV_AMS_MAX_REF__A, - SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_BG_MN); - extAttr->phaseCorrectionBypass = FALSE; - extAttr->atvIfAgcCfg.ctrlMode = DRX_AGC_CTRL_AUTO; - extAttr->enableCVBSOutput = TRUE; - break; - case DRX_STANDARD_PAL_SECAM_DK: - /* PAL/SECAM D/K */ - cmdParam = SCU_RAM_ATV_STANDARD_STANDARD_DK; - - WR16( devAddr, IQM_RT_LO_INCR__A , 2225 );/* TODO check with IS */ - WR16( devAddr, IQM_CF_MIDTAP__A , IQM_CF_MIDTAP_RE__M ); - WRB ( devAddr, IQM_CF_TAP_RE0__A , sizeof(dk_i_l_lp_taps_re) , - ((pu8_t)dk_i_l_lp_taps_re) ); - WRB ( devAddr, IQM_CF_TAP_IM0__A , sizeof(dk_i_l_lp_taps_im) , - ((pu8_t)dk_i_l_lp_taps_im) ); - WR16( devAddr, ATV_TOP_CR_AMP_TH__A , ATV_TOP_CR_AMP_TH_DK ); - WR16( devAddr, ATV_TOP_VID_AMP__A , ATV_TOP_VID_AMP_DK ); - WR16( devAddr, ATV_TOP_CR_CONT__A , - ( ATV_TOP_CR_CONT_CR_P_DK | - ATV_TOP_CR_CONT_CR_D_DK | - ATV_TOP_CR_CONT_CR_I_DK ) ); - WR16( devAddr, ATV_TOP_CR_OVM_TH__A , ATV_TOP_CR_OVM_TH_DK ); - WR16( devAddr, ATV_TOP_STD__A , (ATV_TOP_STD_MODE_DK | - ATV_TOP_STD_VID_POL_DK ) ); - WR16( devAddr, SCU_RAM_ATV_AGC_MODE__A , - ( SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM | - SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE ) ); - WR16( devAddr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000 ); - WR16( devAddr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000 ); - WR16( devAddr, SCU_RAM_ATV_AMS_MAX_REF__A, - SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_DK); - extAttr->phaseCorrectionBypass = FALSE; - extAttr->atvIfAgcCfg.ctrlMode =DRX_AGC_CTRL_AUTO; - extAttr->enableCVBSOutput = TRUE; - break; - case DRX_STANDARD_PAL_SECAM_I: - /* PAL/SECAM I */ - cmdParam = SCU_RAM_ATV_STANDARD_STANDARD_I; - - WR16( devAddr, IQM_RT_LO_INCR__A , 2225 );/* TODO check with IS */ - WR16( devAddr, IQM_CF_MIDTAP__A , IQM_CF_MIDTAP_RE__M ); - WRB ( devAddr, IQM_CF_TAP_RE0__A , sizeof(dk_i_l_lp_taps_re) , - ((pu8_t)dk_i_l_lp_taps_re) ); - WRB ( devAddr, IQM_CF_TAP_IM0__A , sizeof(dk_i_l_lp_taps_im) , - ((pu8_t)dk_i_l_lp_taps_im) ); - WR16( devAddr, ATV_TOP_CR_AMP_TH__A , ATV_TOP_CR_AMP_TH_I ); - WR16( devAddr, ATV_TOP_VID_AMP__A , ATV_TOP_VID_AMP_I ); - WR16( devAddr, ATV_TOP_CR_CONT__A , - ( ATV_TOP_CR_CONT_CR_P_I | - ATV_TOP_CR_CONT_CR_D_I | - ATV_TOP_CR_CONT_CR_I_I ) ); - WR16( devAddr, ATV_TOP_CR_OVM_TH__A , ATV_TOP_CR_OVM_TH_I ); - WR16( devAddr, ATV_TOP_STD__A , (ATV_TOP_STD_MODE_I | - ATV_TOP_STD_VID_POL_I ) ); - WR16( devAddr, SCU_RAM_ATV_AGC_MODE__A , - ( SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM | - SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE ) ); - WR16( devAddr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000 ); - WR16( devAddr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000 ); - WR16( devAddr, SCU_RAM_ATV_AMS_MAX_REF__A, - SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_I); - extAttr->phaseCorrectionBypass = FALSE; - extAttr->atvIfAgcCfg.ctrlMode = DRX_AGC_CTRL_AUTO; - extAttr->enableCVBSOutput = TRUE; - break; - case DRX_STANDARD_PAL_SECAM_L: - /* PAL/SECAM L with negative modulation */ - cmdParam = SCU_RAM_ATV_STANDARD_STANDARD_L; - - WR16( devAddr, IQM_RT_LO_INCR__A , 2225 ); /* TODO check with IS */ - WR16( devAddr, ATV_TOP_VID_AMP__A , ATV_TOP_VID_AMP_L ); - WR16( devAddr, IQM_CF_MIDTAP__A , IQM_CF_MIDTAP_RE__M ); - WRB ( devAddr, IQM_CF_TAP_RE0__A , sizeof(dk_i_l_lp_taps_re) , - ((pu8_t)dk_i_l_lp_taps_re) ); - WRB ( devAddr, IQM_CF_TAP_IM0__A , sizeof(dk_i_l_lp_taps_im) , - ((pu8_t)dk_i_l_lp_taps_im) ); - WR16( devAddr, ATV_TOP_CR_AMP_TH__A , 0x2 ); /* TODO check with IS */ - WR16( devAddr, ATV_TOP_CR_CONT__A , - ( ATV_TOP_CR_CONT_CR_P_L | - ATV_TOP_CR_CONT_CR_D_L | - ATV_TOP_CR_CONT_CR_I_L ) ); - WR16( devAddr, ATV_TOP_CR_OVM_TH__A , ATV_TOP_CR_OVM_TH_L ); - WR16( devAddr, ATV_TOP_STD__A , (ATV_TOP_STD_MODE_L | - ATV_TOP_STD_VID_POL_L ) ); - WR16( devAddr, SCU_RAM_ATV_AGC_MODE__A , - ( SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_AM | - SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_ENABLE | - SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW ) ); - WR16( devAddr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000 ); - WR16( devAddr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000 ); - WR16( devAddr, SCU_RAM_ATV_AMS_MAX_REF__A, - SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_LLP); - extAttr->phaseCorrectionBypass = FALSE; - extAttr->atvIfAgcCfg.ctrlMode = DRX_AGC_CTRL_USER; - extAttr->atvIfAgcCfg.outputLevel = extAttr->atvRfAgcCfg.top; - extAttr->enableCVBSOutput = TRUE; - break; - case DRX_STANDARD_PAL_SECAM_LP: - /* PAL/SECAM L with positive modulation */ - cmdParam = SCU_RAM_ATV_STANDARD_STANDARD_LP; - - WR16( devAddr, ATV_TOP_VID_AMP__A , ATV_TOP_VID_AMP_LP ); - WR16( devAddr, IQM_RT_LO_INCR__A , 2225 ); /* TODO check with IS */ - WR16( devAddr, IQM_CF_MIDTAP__A , IQM_CF_MIDTAP_RE__M ); - WRB ( devAddr, IQM_CF_TAP_RE0__A , sizeof(dk_i_l_lp_taps_re) , - ((pu8_t)dk_i_l_lp_taps_re) ); - WRB ( devAddr, IQM_CF_TAP_IM0__A , sizeof(dk_i_l_lp_taps_im) , - ((pu8_t)dk_i_l_lp_taps_im) ); - WR16( devAddr, ATV_TOP_CR_AMP_TH__A , 0x2 ); /* TODO check with IS */ - WR16( devAddr, ATV_TOP_CR_CONT__A , - ( ATV_TOP_CR_CONT_CR_P_LP | - ATV_TOP_CR_CONT_CR_D_LP | - ATV_TOP_CR_CONT_CR_I_LP ) ); - WR16( devAddr, ATV_TOP_CR_OVM_TH__A , ATV_TOP_CR_OVM_TH_LP ); - WR16( devAddr, ATV_TOP_STD__A , (ATV_TOP_STD_MODE_LP | - ATV_TOP_STD_VID_POL_LP ) ); - WR16( devAddr, SCU_RAM_ATV_AGC_MODE__A , - ( SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_AM | - SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_ENABLE | - SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW ) ); - WR16( devAddr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000 ); - WR16( devAddr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000 ); - WR16( devAddr, SCU_RAM_ATV_AMS_MAX_REF__A, - SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_LLP); - extAttr->phaseCorrectionBypass = FALSE; - extAttr->atvIfAgcCfg.ctrlMode = DRX_AGC_CTRL_USER; - extAttr->atvIfAgcCfg.outputLevel = extAttr->atvRfAgcCfg.top; - extAttr->enableCVBSOutput = TRUE; - break; - default: - return ( DRX_STS_ERROR ); - } - - /* Common initializations FM & NTSC & B/G & D/K & I & L & LP */ - if (extAttr->hasLNA == FALSE) - { - WR16( devAddr, IQM_AF_AMUX__A, 0x01); - } - - WR16( devAddr, SCU_RAM_ATV_STANDARD__A , 0x002 ); - WR16( devAddr, IQM_AF_CLP_LEN__A , IQM_AF_CLP_LEN_ATV ); - WR16( devAddr, IQM_AF_CLP_TH__A , IQM_AF_CLP_TH_ATV ); - WR16( devAddr, IQM_AF_SNS_LEN__A , IQM_AF_SNS_LEN_ATV ); - CHK_ERROR( CtrlSetCfgPreSaw( demod, &(extAttr->atvPreSawCfg)) ); - WR16( devAddr, IQM_AF_AGC_IF__A , 10248 ); - - extAttr->iqmRcRateOfs = 0x00200000L; - WR32( devAddr, IQM_RC_RATE_OFS_LO__A , extAttr->iqmRcRateOfs ); - WR16( devAddr, IQM_RC_ADJ_SEL__A , IQM_RC_ADJ_SEL_B_OFF ); - WR16( devAddr, IQM_RC_STRETCH__A , IQM_RC_STRETCH_ATV ); - - WR16( devAddr, IQM_RT_ACTIVE__A , IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_ON | - IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_ON ); - - WR16( devAddr, IQM_CF_OUT_ENA__A , IQM_CF_OUT_ENA_ATV__M ); - WR16( devAddr, IQM_CF_SYMMETRIC__A , IQM_CF_SYMMETRIC_IM__M ); - /* default: SIF in standby */ - WR16( devAddr, ATV_TOP_SYNC_SLICE__A , ATV_TOP_SYNC_SLICE_MN ); - WR16( devAddr, ATV_TOP_MOD_ACCU__A , ATV_TOP_MOD_ACCU__PRE ); - - WR16( devAddr, SCU_RAM_ATV_SIF_GAIN__A , 0x080 ); - WR16( devAddr, SCU_RAM_ATV_FAGC_TH_RED__A , 10 ); - WR16( devAddr, SCU_RAM_ATV_AAGC_CNT__A , 7 ); - WR16( devAddr, SCU_RAM_ATV_NAGC_KI_MIN__A , 0x0225 ); - WR16( devAddr, SCU_RAM_ATV_NAGC_KI_MAX__A , 0x0547 ); - WR16( devAddr, SCU_RAM_ATV_KI_CHANGE_TH__A , 20 ); - WR16( devAddr, SCU_RAM_ATV_LOCK__A , 0 ); - - WR16( devAddr, IQM_RT_DELAY__A , IQM_RT_DELAY__PRE ); - WR16( devAddr, SCU_RAM_ATV_BPC_KI_MIN__A , 531 ); - WR16( devAddr, SCU_RAM_ATV_PAGC_KI_MIN__A, 1061 ); - WR16( devAddr, SCU_RAM_ATV_BP_REF_MIN__A , 100 ); - WR16( devAddr, SCU_RAM_ATV_BP_REF_MAX__A , 260 ); - WR16( devAddr, SCU_RAM_ATV_BP_LVL__A , 0 ); - WR16( devAddr, SCU_RAM_ATV_AMS_MAX__A , 0 ); - WR16( devAddr, SCU_RAM_ATV_AMS_MIN__A , 2047 ); - WR16( devAddr, SCU_RAM_GPIO__A , 0 ); - - /* Override reset values with current shadow settings */ - CHK_ERROR( AtvUpdateConfig( demod, TRUE) ); - - /* Configure/restore AGC settings */ - CHK_ERROR( InitAGC( demod ) ); - CHK_ERROR( SetAgcIf( demod, &(extAttr->atvIfAgcCfg), FALSE ) ); - CHK_ERROR( SetAgcRf( demod, &(extAttr->atvRfAgcCfg), FALSE ) ); - CHK_ERROR( CtrlSetCfgPreSaw( demod, &(extAttr->atvPreSawCfg)) ); - - /* Set SCU ATV substandard,assuming this doesn't require running ATV block */ - cmdSCU.command = SCU_RAM_COMMAND_STANDARD_ATV | - SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV; - cmdSCU.parameterLen = 1; - cmdSCU.resultLen = 1; - cmdSCU.parameter = &cmdParam; - cmdSCU.result = &cmdResult; - CHK_ERROR( SCUCommand( devAddr, &cmdSCU ) ); - - /* turn the analog work around on/off (must after set_env b/c it is set in mc)*/ - if ( extAttr->mfx == 0x03 ) - { - WR16( devAddr, SCU_RAM_ATV_ENABLE_IIR_WA__A, 0 ); - } - else - { - WR16( devAddr, SCU_RAM_ATV_ENABLE_IIR_WA__A, 1 ); - WR16( devAddr, SCU_RAM_ATV_IIR_CRIT__A , 225 ); - } + WR16(devAddr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_STOP); + WR16(devAddr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP); + WR16(devAddr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP); + WR16(devAddr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP); + WR16(devAddr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP); + WR16(devAddr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP); + /* Reset ATV SCU */ + cmdSCU.command = SCU_RAM_COMMAND_STANDARD_ATV | + SCU_RAM_COMMAND_CMD_DEMOD_RESET; + cmdSCU.parameterLen = 0; + cmdSCU.resultLen = 1; + cmdSCU.parameter = NULL; + cmdSCU.result = &cmdResult; + CHK_ERROR(SCUCommand(devAddr, &cmdSCU)); + + WR16(devAddr, ATV_TOP_MOD_CONTROL__A, ATV_TOP_MOD_CONTROL__PRE); + + /* TODO remove AUTO/OFF patches after ucode fix. */ + switch (*standard) { + case DRX_STANDARD_NTSC: + /* NTSC */ + cmdParam = SCU_RAM_ATV_STANDARD_STANDARD_MN; + + WR16(devAddr, IQM_RT_LO_INCR__A, IQM_RT_LO_INCR_MN); + WR16(devAddr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M); + WRB(devAddr, IQM_CF_TAP_RE0__A, sizeof(ntsc_taps_re), + ((pu8_t) ntsc_taps_re)); + WRB(devAddr, IQM_CF_TAP_IM0__A, sizeof(ntsc_taps_im), + ((pu8_t) ntsc_taps_im)); + + WR16(devAddr, ATV_TOP_CR_AMP_TH__A, ATV_TOP_CR_AMP_TH_MN); + WR16(devAddr, ATV_TOP_CR_CONT__A, + (ATV_TOP_CR_CONT_CR_P_MN | + ATV_TOP_CR_CONT_CR_D_MN | ATV_TOP_CR_CONT_CR_I_MN)); + WR16(devAddr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_MN); + WR16(devAddr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_MN | + ATV_TOP_STD_VID_POL_MN)); + WR16(devAddr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_MN); + + WR16(devAddr, SCU_RAM_ATV_AGC_MODE__A, + (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM | + SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE)); + WR16(devAddr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000); + WR16(devAddr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000); + WR16(devAddr, SCU_RAM_ATV_AMS_MAX_REF__A, + SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_BG_MN); + extAttr->phaseCorrectionBypass = FALSE; + extAttr->enableCVBSOutput = TRUE; + break; + case DRX_STANDARD_FM: + /* FM */ + cmdParam = SCU_RAM_ATV_STANDARD_STANDARD_FM; + + WR16(devAddr, IQM_RT_LO_INCR__A, 2994); + WR16(devAddr, IQM_CF_MIDTAP__A, 0); + WRB(devAddr, IQM_CF_TAP_RE0__A, sizeof(fm_taps_re), + ((pu8_t) fm_taps_re)); + WRB(devAddr, IQM_CF_TAP_IM0__A, sizeof(fm_taps_im), + ((pu8_t) fm_taps_im)); + WR16(devAddr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_FM | + ATV_TOP_STD_VID_POL_FM)); + WR16(devAddr, ATV_TOP_MOD_CONTROL__A, 0); + WR16(devAddr, ATV_TOP_CR_CONT__A, 0); + + WR16(devAddr, SCU_RAM_ATV_AGC_MODE__A, + (SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW | + SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM)); + WR16(devAddr, IQM_RT_ROT_BP__A, IQM_RT_ROT_BP_ROT_OFF_OFF); + extAttr->phaseCorrectionBypass = TRUE; + extAttr->enableCVBSOutput = FALSE; + break; + case DRX_STANDARD_PAL_SECAM_BG: + /* PAL/SECAM B/G */ + cmdParam = SCU_RAM_ATV_STANDARD_STANDARD_B; + + WR16(devAddr, IQM_RT_LO_INCR__A, 1820); /* TODO check with IS */ + WR16(devAddr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M); + WRB(devAddr, IQM_CF_TAP_RE0__A, sizeof(bg_taps_re), + ((pu8_t) bg_taps_re)); + WRB(devAddr, IQM_CF_TAP_IM0__A, sizeof(bg_taps_im), + ((pu8_t) bg_taps_im)); + WR16(devAddr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_BG); + WR16(devAddr, ATV_TOP_CR_AMP_TH__A, ATV_TOP_CR_AMP_TH_BG); + WR16(devAddr, ATV_TOP_CR_CONT__A, + (ATV_TOP_CR_CONT_CR_P_BG | + ATV_TOP_CR_CONT_CR_D_BG | ATV_TOP_CR_CONT_CR_I_BG)); + WR16(devAddr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_BG); + WR16(devAddr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_BG | + ATV_TOP_STD_VID_POL_BG)); + WR16(devAddr, SCU_RAM_ATV_AGC_MODE__A, + (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM | + SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE)); + WR16(devAddr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000); + WR16(devAddr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000); + WR16(devAddr, SCU_RAM_ATV_AMS_MAX_REF__A, + SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_BG_MN); + extAttr->phaseCorrectionBypass = FALSE; + extAttr->atvIfAgcCfg.ctrlMode = DRX_AGC_CTRL_AUTO; + extAttr->enableCVBSOutput = TRUE; + break; + case DRX_STANDARD_PAL_SECAM_DK: + /* PAL/SECAM D/K */ + cmdParam = SCU_RAM_ATV_STANDARD_STANDARD_DK; + + WR16(devAddr, IQM_RT_LO_INCR__A, 2225); /* TODO check with IS */ + WR16(devAddr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M); + WRB(devAddr, IQM_CF_TAP_RE0__A, sizeof(dk_i_l_lp_taps_re), + ((pu8_t) dk_i_l_lp_taps_re)); + WRB(devAddr, IQM_CF_TAP_IM0__A, sizeof(dk_i_l_lp_taps_im), + ((pu8_t) dk_i_l_lp_taps_im)); + WR16(devAddr, ATV_TOP_CR_AMP_TH__A, ATV_TOP_CR_AMP_TH_DK); + WR16(devAddr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_DK); + WR16(devAddr, ATV_TOP_CR_CONT__A, + (ATV_TOP_CR_CONT_CR_P_DK | + ATV_TOP_CR_CONT_CR_D_DK | ATV_TOP_CR_CONT_CR_I_DK)); + WR16(devAddr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_DK); + WR16(devAddr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_DK | + ATV_TOP_STD_VID_POL_DK)); + WR16(devAddr, SCU_RAM_ATV_AGC_MODE__A, + (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM | + SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE)); + WR16(devAddr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000); + WR16(devAddr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000); + WR16(devAddr, SCU_RAM_ATV_AMS_MAX_REF__A, + SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_DK); + extAttr->phaseCorrectionBypass = FALSE; + extAttr->atvIfAgcCfg.ctrlMode = DRX_AGC_CTRL_AUTO; + extAttr->enableCVBSOutput = TRUE; + break; + case DRX_STANDARD_PAL_SECAM_I: + /* PAL/SECAM I */ + cmdParam = SCU_RAM_ATV_STANDARD_STANDARD_I; + + WR16(devAddr, IQM_RT_LO_INCR__A, 2225); /* TODO check with IS */ + WR16(devAddr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M); + WRB(devAddr, IQM_CF_TAP_RE0__A, sizeof(dk_i_l_lp_taps_re), + ((pu8_t) dk_i_l_lp_taps_re)); + WRB(devAddr, IQM_CF_TAP_IM0__A, sizeof(dk_i_l_lp_taps_im), + ((pu8_t) dk_i_l_lp_taps_im)); + WR16(devAddr, ATV_TOP_CR_AMP_TH__A, ATV_TOP_CR_AMP_TH_I); + WR16(devAddr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_I); + WR16(devAddr, ATV_TOP_CR_CONT__A, + (ATV_TOP_CR_CONT_CR_P_I | + ATV_TOP_CR_CONT_CR_D_I | ATV_TOP_CR_CONT_CR_I_I)); + WR16(devAddr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_I); + WR16(devAddr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_I | + ATV_TOP_STD_VID_POL_I)); + WR16(devAddr, SCU_RAM_ATV_AGC_MODE__A, + (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM | + SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE)); + WR16(devAddr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000); + WR16(devAddr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000); + WR16(devAddr, SCU_RAM_ATV_AMS_MAX_REF__A, + SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_I); + extAttr->phaseCorrectionBypass = FALSE; + extAttr->atvIfAgcCfg.ctrlMode = DRX_AGC_CTRL_AUTO; + extAttr->enableCVBSOutput = TRUE; + break; + case DRX_STANDARD_PAL_SECAM_L: + /* PAL/SECAM L with negative modulation */ + cmdParam = SCU_RAM_ATV_STANDARD_STANDARD_L; + + WR16(devAddr, IQM_RT_LO_INCR__A, 2225); /* TODO check with IS */ + WR16(devAddr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_L); + WR16(devAddr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M); + WRB(devAddr, IQM_CF_TAP_RE0__A, sizeof(dk_i_l_lp_taps_re), + ((pu8_t) dk_i_l_lp_taps_re)); + WRB(devAddr, IQM_CF_TAP_IM0__A, sizeof(dk_i_l_lp_taps_im), + ((pu8_t) dk_i_l_lp_taps_im)); + WR16(devAddr, ATV_TOP_CR_AMP_TH__A, 0x2); /* TODO check with IS */ + WR16(devAddr, ATV_TOP_CR_CONT__A, + (ATV_TOP_CR_CONT_CR_P_L | + ATV_TOP_CR_CONT_CR_D_L | ATV_TOP_CR_CONT_CR_I_L)); + WR16(devAddr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_L); + WR16(devAddr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_L | + ATV_TOP_STD_VID_POL_L)); + WR16(devAddr, SCU_RAM_ATV_AGC_MODE__A, + (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_AM | + SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_ENABLE | + SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW)); + WR16(devAddr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000); + WR16(devAddr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000); + WR16(devAddr, SCU_RAM_ATV_AMS_MAX_REF__A, + SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_LLP); + extAttr->phaseCorrectionBypass = FALSE; + extAttr->atvIfAgcCfg.ctrlMode = DRX_AGC_CTRL_USER; + extAttr->atvIfAgcCfg.outputLevel = extAttr->atvRfAgcCfg.top; + extAttr->enableCVBSOutput = TRUE; + break; + case DRX_STANDARD_PAL_SECAM_LP: + /* PAL/SECAM L with positive modulation */ + cmdParam = SCU_RAM_ATV_STANDARD_STANDARD_LP; + + WR16(devAddr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_LP); + WR16(devAddr, IQM_RT_LO_INCR__A, 2225); /* TODO check with IS */ + WR16(devAddr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M); + WRB(devAddr, IQM_CF_TAP_RE0__A, sizeof(dk_i_l_lp_taps_re), + ((pu8_t) dk_i_l_lp_taps_re)); + WRB(devAddr, IQM_CF_TAP_IM0__A, sizeof(dk_i_l_lp_taps_im), + ((pu8_t) dk_i_l_lp_taps_im)); + WR16(devAddr, ATV_TOP_CR_AMP_TH__A, 0x2); /* TODO check with IS */ + WR16(devAddr, ATV_TOP_CR_CONT__A, + (ATV_TOP_CR_CONT_CR_P_LP | + ATV_TOP_CR_CONT_CR_D_LP | ATV_TOP_CR_CONT_CR_I_LP)); + WR16(devAddr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_LP); + WR16(devAddr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_LP | + ATV_TOP_STD_VID_POL_LP)); + WR16(devAddr, SCU_RAM_ATV_AGC_MODE__A, + (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_AM | + SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_ENABLE | + SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW)); + WR16(devAddr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000); + WR16(devAddr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000); + WR16(devAddr, SCU_RAM_ATV_AMS_MAX_REF__A, + SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_LLP); + extAttr->phaseCorrectionBypass = FALSE; + extAttr->atvIfAgcCfg.ctrlMode = DRX_AGC_CTRL_USER; + extAttr->atvIfAgcCfg.outputLevel = extAttr->atvRfAgcCfg.top; + extAttr->enableCVBSOutput = TRUE; + break; + default: + return (DRX_STS_ERROR); + } - return (DRX_STS_OK); + /* Common initializations FM & NTSC & B/G & D/K & I & L & LP */ + if (extAttr->hasLNA == FALSE) { + WR16(devAddr, IQM_AF_AMUX__A, 0x01); + } + + WR16(devAddr, SCU_RAM_ATV_STANDARD__A, 0x002); + WR16(devAddr, IQM_AF_CLP_LEN__A, IQM_AF_CLP_LEN_ATV); + WR16(devAddr, IQM_AF_CLP_TH__A, IQM_AF_CLP_TH_ATV); + WR16(devAddr, IQM_AF_SNS_LEN__A, IQM_AF_SNS_LEN_ATV); + CHK_ERROR(CtrlSetCfgPreSaw(demod, &(extAttr->atvPreSawCfg))); + WR16(devAddr, IQM_AF_AGC_IF__A, 10248); + + extAttr->iqmRcRateOfs = 0x00200000L; + WR32(devAddr, IQM_RC_RATE_OFS_LO__A, extAttr->iqmRcRateOfs); + WR16(devAddr, IQM_RC_ADJ_SEL__A, IQM_RC_ADJ_SEL_B_OFF); + WR16(devAddr, IQM_RC_STRETCH__A, IQM_RC_STRETCH_ATV); + + WR16(devAddr, IQM_RT_ACTIVE__A, IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_ON | + IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_ON); + + WR16(devAddr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_ATV__M); + WR16(devAddr, IQM_CF_SYMMETRIC__A, IQM_CF_SYMMETRIC_IM__M); + /* default: SIF in standby */ + WR16(devAddr, ATV_TOP_SYNC_SLICE__A, ATV_TOP_SYNC_SLICE_MN); + WR16(devAddr, ATV_TOP_MOD_ACCU__A, ATV_TOP_MOD_ACCU__PRE); + + WR16(devAddr, SCU_RAM_ATV_SIF_GAIN__A, 0x080); + WR16(devAddr, SCU_RAM_ATV_FAGC_TH_RED__A, 10); + WR16(devAddr, SCU_RAM_ATV_AAGC_CNT__A, 7); + WR16(devAddr, SCU_RAM_ATV_NAGC_KI_MIN__A, 0x0225); + WR16(devAddr, SCU_RAM_ATV_NAGC_KI_MAX__A, 0x0547); + WR16(devAddr, SCU_RAM_ATV_KI_CHANGE_TH__A, 20); + WR16(devAddr, SCU_RAM_ATV_LOCK__A, 0); + + WR16(devAddr, IQM_RT_DELAY__A, IQM_RT_DELAY__PRE); + WR16(devAddr, SCU_RAM_ATV_BPC_KI_MIN__A, 531); + WR16(devAddr, SCU_RAM_ATV_PAGC_KI_MIN__A, 1061); + WR16(devAddr, SCU_RAM_ATV_BP_REF_MIN__A, 100); + WR16(devAddr, SCU_RAM_ATV_BP_REF_MAX__A, 260); + WR16(devAddr, SCU_RAM_ATV_BP_LVL__A, 0); + WR16(devAddr, SCU_RAM_ATV_AMS_MAX__A, 0); + WR16(devAddr, SCU_RAM_ATV_AMS_MIN__A, 2047); + WR16(devAddr, SCU_RAM_GPIO__A, 0); + + /* Override reset values with current shadow settings */ + CHK_ERROR(AtvUpdateConfig(demod, TRUE)); + + /* Configure/restore AGC settings */ + CHK_ERROR(InitAGC(demod)); + CHK_ERROR(SetAgcIf(demod, &(extAttr->atvIfAgcCfg), FALSE)); + CHK_ERROR(SetAgcRf(demod, &(extAttr->atvRfAgcCfg), FALSE)); + CHK_ERROR(CtrlSetCfgPreSaw(demod, &(extAttr->atvPreSawCfg))); + + /* Set SCU ATV substandard,assuming this doesn't require running ATV block */ + cmdSCU.command = SCU_RAM_COMMAND_STANDARD_ATV | + SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV; + cmdSCU.parameterLen = 1; + cmdSCU.resultLen = 1; + cmdSCU.parameter = &cmdParam; + cmdSCU.result = &cmdResult; + CHK_ERROR(SCUCommand(devAddr, &cmdSCU)); + + /* turn the analog work around on/off (must after set_env b/c it is set in mc) */ + if (extAttr->mfx == 0x03) { + WR16(devAddr, SCU_RAM_ATV_ENABLE_IIR_WA__A, 0); + } else { + WR16(devAddr, SCU_RAM_ATV_ENABLE_IIR_WA__A, 1); + WR16(devAddr, SCU_RAM_ATV_IIR_CRIT__A, 225); + } + + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } #endif @@ -9826,56 +9456,53 @@ rw_error: * */ static DRXStatus_t -SetATVChannel( pDRXDemodInstance_t demod, - DRXFrequency_t tunerFreqOffset, - pDRXChannel_t channel, - DRXStandard_t standard ) +SetATVChannel(pDRXDemodInstance_t demod, + DRXFrequency_t tunerFreqOffset, + pDRXChannel_t channel, DRXStandard_t standard) { - DRXJSCUCmd_t cmdSCU = {/* command */ 0, - /* parameterLen */ 0, - /* resultLen */ 0, - /* parameter */ NULL, - /* result */ NULL }; - u16_t cmdResult = 0; - pDRXJData_t extAttr = NULL; - pI2CDeviceAddr_t devAddr = NULL; - - devAddr = demod -> myI2CDevAddr; - extAttr = (pDRXJData_t)demod->myExtAttr; - - /* - Program frequency shifter - No need to account for mirroring on RF - */ - if (channel->mirror == DRX_MIRROR_AUTO) - { - extAttr->mirror = DRX_MIRROR_NO; - } - else - { - extAttr->mirror = channel->mirror; - } + DRXJSCUCmd_t cmdSCU = { /* command */ 0, + /* parameterLen */ 0, + /* resultLen */ 0, + /* parameter */ NULL, + /* result */ NULL + }; + u16_t cmdResult = 0; + pDRXJData_t extAttr = NULL; + pI2CDeviceAddr_t devAddr = NULL; + + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; + + /* + Program frequency shifter + No need to account for mirroring on RF + */ + if (channel->mirror == DRX_MIRROR_AUTO) { + extAttr->mirror = DRX_MIRROR_NO; + } else { + extAttr->mirror = channel->mirror; + } - CHK_ERROR ( SetFrequency ( demod, channel, tunerFreqOffset ) ); - WR16(devAddr, ATV_TOP_CR_FREQ__A, ATV_TOP_CR_FREQ__PRE); + CHK_ERROR(SetFrequency(demod, channel, tunerFreqOffset)); + WR16(devAddr, ATV_TOP_CR_FREQ__A, ATV_TOP_CR_FREQ__PRE); - /* Start ATV SCU */ - cmdSCU.command = SCU_RAM_COMMAND_STANDARD_ATV | - SCU_RAM_COMMAND_CMD_DEMOD_START; - cmdSCU.parameterLen = 0; - cmdSCU.resultLen = 1; - cmdSCU.parameter = NULL; - cmdSCU.result = &cmdResult; - CHK_ERROR( SCUCommand( devAddr, &cmdSCU ) ); + /* Start ATV SCU */ + cmdSCU.command = SCU_RAM_COMMAND_STANDARD_ATV | + SCU_RAM_COMMAND_CMD_DEMOD_START; + cmdSCU.parameterLen = 0; + cmdSCU.resultLen = 1; + cmdSCU.parameter = NULL; + cmdSCU.result = &cmdResult; + CHK_ERROR(SCUCommand(devAddr, &cmdSCU)); /* if ( (extAttr->standard == DRX_STANDARD_FM) && (extAttr->flagSetAUDdone == TRUE) ) { extAttr->detectedRDS = (Bool_t)FALSE; }*/ - return (DRX_STS_OK); + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } #endif @@ -9896,72 +9523,70 @@ rw_error: */ #ifndef DRXJ_DIGITAL_ONLY static DRXStatus_t -GetATVChannel( pDRXDemodInstance_t demod, - pDRXChannel_t channel, - DRXStandard_t standard ) -{ - DRXFrequency_t offset = 0; - pI2CDeviceAddr_t devAddr = NULL; - pDRXJData_t extAttr = NULL; - - devAddr = demod -> myI2CDevAddr; - extAttr = (pDRXJData_t)demod->myExtAttr; - - /* Bandwidth */ - channel->bandwidth = ((pDRXJData_t)demod -> myExtAttr)->currBandwidth; - - switch ( standard ) - { - case DRX_STANDARD_NTSC: - case DRX_STANDARD_PAL_SECAM_BG: - case DRX_STANDARD_PAL_SECAM_DK: - case DRX_STANDARD_PAL_SECAM_I: - case DRX_STANDARD_PAL_SECAM_L: - { - u16_t measuredOffset=0; - - /* get measured frequency offset */ - RR16(devAddr, ATV_TOP_CR_FREQ__A, &measuredOffset); - /* Signed 8 bit register => sign extension needed */ - if ( (measuredOffset & 0x0080) != 0) - { - /* sign extension */ - measuredOffset |= 0xFF80; - } - offset+= (DRXFrequency_t)( ((s16_t)measuredOffset)*10); - break; - } - case DRX_STANDARD_PAL_SECAM_LP: - { - u16_t measuredOffset=0; - - /* get measured frequency offset */ - RR16(devAddr, ATV_TOP_CR_FREQ__A, &measuredOffset); - /* Signed 8 bit register => sign extension needed */ - if ( (measuredOffset & 0x0080) != 0) - { - /* sign extension */ - measuredOffset |= 0xFF80; - } - offset-= (DRXFrequency_t)( ((s16_t)measuredOffset)*10); - } - break; - case DRX_STANDARD_FM: - /* TODO: compute offset using AUD_DSP_RD_FM_DC_LEVEL_A__A and - AUD_DSP_RD_FM_DC_LEVEL_B__A. For now leave frequency as is. - */ - /* No bandwidth know for FM */ - channel->bandwidth = DRX_BANDWIDTH_UNKNOWN; - break; - default: - return ( DRX_STS_ERROR ); - } +GetATVChannel(pDRXDemodInstance_t demod, + pDRXChannel_t channel, DRXStandard_t standard) +{ + DRXFrequency_t offset = 0; + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; + + /* Bandwidth */ + channel->bandwidth = ((pDRXJData_t) demod->myExtAttr)->currBandwidth; + + switch (standard) { + case DRX_STANDARD_NTSC: + case DRX_STANDARD_PAL_SECAM_BG: + case DRX_STANDARD_PAL_SECAM_DK: + case DRX_STANDARD_PAL_SECAM_I: + case DRX_STANDARD_PAL_SECAM_L: + { + u16_t measuredOffset = 0; + + /* get measured frequency offset */ + RR16(devAddr, ATV_TOP_CR_FREQ__A, &measuredOffset); + /* Signed 8 bit register => sign extension needed */ + if ((measuredOffset & 0x0080) != 0) { + /* sign extension */ + measuredOffset |= 0xFF80; + } + offset += + (DRXFrequency_t) (((s16_t) measuredOffset) * 10); + break; + } + case DRX_STANDARD_PAL_SECAM_LP: + { + u16_t measuredOffset = 0; + + /* get measured frequency offset */ + RR16(devAddr, ATV_TOP_CR_FREQ__A, &measuredOffset); + /* Signed 8 bit register => sign extension needed */ + if ((measuredOffset & 0x0080) != 0) { + /* sign extension */ + measuredOffset |= 0xFF80; + } + offset -= + (DRXFrequency_t) (((s16_t) measuredOffset) * 10); + } + break; + case DRX_STANDARD_FM: + /* TODO: compute offset using AUD_DSP_RD_FM_DC_LEVEL_A__A and + AUD_DSP_RD_FM_DC_LEVEL_B__A. For now leave frequency as is. + */ + /* No bandwidth know for FM */ + channel->bandwidth = DRX_BANDWIDTH_UNKNOWN; + break; + default: + return (DRX_STS_ERROR); + } - channel->frequency -= offset; + channel->frequency -= offset; - return (DRX_STS_OK); + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /* -------------------------------------------------------------------------- */ @@ -9985,97 +9610,100 @@ rw_error: * is not used ? */ static DRXStatus_t -GetAtvSigStrength( pDRXDemodInstance_t demod, - pu16_t sigStrength ) -{ - pI2CDeviceAddr_t devAddr = NULL; - pDRXJData_t extAttr = NULL; - - /* All weights must add up to 100 (%) - TODO: change weights when IF ctrl is available */ - u32_t digitalWeight = 50; /* 0 .. 100 */ - u32_t rfWeight = 50; /* 0 .. 100 */ - u32_t ifWeight = 0; /* 0 .. 100 */ - - u16_t digitalCurrGain = 0; - u32_t digitalMaxGain = 0; - u32_t digitalMinGain = 0; - u16_t rfCurrGain = 0; - u32_t rfMaxGain = 0x800; /* taken from ucode */ - u32_t rfMinGain = 0x7fff; - u16_t ifCurrGain = 0; - u32_t ifMaxGain = 0x800; /* taken from ucode */ - u32_t ifMinGain = 0x7fff; - - u32_t digitalStrength = 0; /* 0.. 100 */ - u32_t rfStrength = 0; /* 0.. 100 */ - u32_t ifStrength = 0; /* 0.. 100 */ - - devAddr = demod -> myI2CDevAddr; - extAttr = (pDRXJData_t)demod->myExtAttr; - - *sigStrength = 0; - - switch( extAttr->standard ) - { - case DRX_STANDARD_PAL_SECAM_BG : /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_DK : /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_I : /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_L : /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_LP : /* fallthrough */ - case DRX_STANDARD_NTSC: - SARR16(devAddr, SCU_RAM_ATV_VID_GAIN_HI__A, &digitalCurrGain); - digitalMaxGain = 22512; /* taken from ucode */ - digitalMinGain = 2400; /* taken from ucode */ - break; - case DRX_STANDARD_FM: - SARR16(devAddr, SCU_RAM_ATV_SIF_GAIN__A, &digitalCurrGain); - digitalMaxGain = 0x4ff; /* taken from ucode */ - digitalMinGain = 0; /* taken from ucode */ - break; - default: - return (DRX_STS_ERROR); - break; - } - RR16(devAddr, IQM_AF_AGC_RF__A, &rfCurrGain); - RR16(devAddr, IQM_AF_AGC_IF__A, &ifCurrGain); - - /* clipping */ - if ( digitalCurrGain >= digitalMaxGain ) digitalCurrGain = (u16_t)digitalMaxGain; - if ( digitalCurrGain <= digitalMinGain ) digitalCurrGain = (u16_t)digitalMinGain; - if ( ifCurrGain <= ifMaxGain ) ifCurrGain = (u16_t)ifMaxGain; - if ( ifCurrGain >= ifMinGain ) ifCurrGain = (u16_t)ifMinGain; - if ( rfCurrGain <= rfMaxGain ) rfCurrGain = (u16_t)rfMaxGain; - if ( rfCurrGain >= rfMinGain ) rfCurrGain = (u16_t)rfMinGain; - - /* TODO: use SCU_RAM_ATV_RAGC_HR__A to shift max and min in case - of clipping at ADC */ - - /* Compute signal strength (in %) per "gain domain" */ - - /* Digital gain */ - /* TODO: ADC clipping not handled */ - digitalStrength = ( 100 *(digitalMaxGain-(u32_t)digitalCurrGain) )/ - (digitalMaxGain -digitalMinGain); - - /* TODO: IF gain not implemented yet in microcode, check after impl. */ - ifStrength = ( 100 *((u32_t)ifCurrGain-ifMaxGain) )/ - ( ifMinGain - ifMaxGain ); - - /* Rf gain */ - /* TODO: ADC clipping not handled */ - rfStrength = ( 100 *((u32_t)rfCurrGain-rfMaxGain) )/ - ( rfMinGain - rfMaxGain ); - - /* Compute a weighted signal strength (in %) */ - *sigStrength = (u16_t) (digitalWeight*digitalStrength + - rfWeight*rfStrength + - ifWeight*ifStrength); - *sigStrength /= 100; - - return (DRX_STS_OK); - rw_error: - return (DRX_STS_ERROR); +GetAtvSigStrength(pDRXDemodInstance_t demod, pu16_t sigStrength) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + + /* All weights must add up to 100 (%) + TODO: change weights when IF ctrl is available */ + u32_t digitalWeight = 50; /* 0 .. 100 */ + u32_t rfWeight = 50; /* 0 .. 100 */ + u32_t ifWeight = 0; /* 0 .. 100 */ + + u16_t digitalCurrGain = 0; + u32_t digitalMaxGain = 0; + u32_t digitalMinGain = 0; + u16_t rfCurrGain = 0; + u32_t rfMaxGain = 0x800; /* taken from ucode */ + u32_t rfMinGain = 0x7fff; + u16_t ifCurrGain = 0; + u32_t ifMaxGain = 0x800; /* taken from ucode */ + u32_t ifMinGain = 0x7fff; + + u32_t digitalStrength = 0; /* 0.. 100 */ + u32_t rfStrength = 0; /* 0.. 100 */ + u32_t ifStrength = 0; /* 0.. 100 */ + + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; + + *sigStrength = 0; + + switch (extAttr->standard) { + case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_LP: /* fallthrough */ + case DRX_STANDARD_NTSC: + SARR16(devAddr, SCU_RAM_ATV_VID_GAIN_HI__A, &digitalCurrGain); + digitalMaxGain = 22512; /* taken from ucode */ + digitalMinGain = 2400; /* taken from ucode */ + break; + case DRX_STANDARD_FM: + SARR16(devAddr, SCU_RAM_ATV_SIF_GAIN__A, &digitalCurrGain); + digitalMaxGain = 0x4ff; /* taken from ucode */ + digitalMinGain = 0; /* taken from ucode */ + break; + default: + return (DRX_STS_ERROR); + break; + } + RR16(devAddr, IQM_AF_AGC_RF__A, &rfCurrGain); + RR16(devAddr, IQM_AF_AGC_IF__A, &ifCurrGain); + + /* clipping */ + if (digitalCurrGain >= digitalMaxGain) + digitalCurrGain = (u16_t) digitalMaxGain; + if (digitalCurrGain <= digitalMinGain) + digitalCurrGain = (u16_t) digitalMinGain; + if (ifCurrGain <= ifMaxGain) + ifCurrGain = (u16_t) ifMaxGain; + if (ifCurrGain >= ifMinGain) + ifCurrGain = (u16_t) ifMinGain; + if (rfCurrGain <= rfMaxGain) + rfCurrGain = (u16_t) rfMaxGain; + if (rfCurrGain >= rfMinGain) + rfCurrGain = (u16_t) rfMinGain; + + /* TODO: use SCU_RAM_ATV_RAGC_HR__A to shift max and min in case + of clipping at ADC */ + + /* Compute signal strength (in %) per "gain domain" */ + + /* Digital gain */ + /* TODO: ADC clipping not handled */ + digitalStrength = (100 * (digitalMaxGain - (u32_t) digitalCurrGain)) / + (digitalMaxGain - digitalMinGain); + + /* TODO: IF gain not implemented yet in microcode, check after impl. */ + ifStrength = (100 * ((u32_t) ifCurrGain - ifMaxGain)) / + (ifMinGain - ifMaxGain); + + /* Rf gain */ + /* TODO: ADC clipping not handled */ + rfStrength = (100 * ((u32_t) rfCurrGain - rfMaxGain)) / + (rfMinGain - rfMaxGain); + + /* Compute a weighted signal strength (in %) */ + *sigStrength = (u16_t) (digitalWeight * digitalStrength + + rfWeight * rfStrength + ifWeight * ifStrength); + *sigStrength /= 100; + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); } /* -------------------------------------------------------------------------- */ @@ -10091,46 +9719,44 @@ GetAtvSigStrength( pDRXDemodInstance_t demod, * */ static DRXStatus_t -AtvSigQuality( pDRXDemodInstance_t demod, - pDRXSigQuality_t sigQuality ) +AtvSigQuality(pDRXDemodInstance_t demod, pDRXSigQuality_t sigQuality) { - pI2CDeviceAddr_t devAddr = NULL; - u16_t qualityIndicator = 0; - - devAddr = demod -> myI2CDevAddr; - - /* defined values for fields not used */ - sigQuality->MER = 0; - sigQuality->preViterbiBER = 0; - sigQuality->postViterbiBER = 0; - sigQuality->scaleFactorBER = 1; - sigQuality->packetError = 0; - sigQuality->postReedSolomonBER = 0; - - /* - Mapping: - 0x000..0x080: strong signal => 80% .. 100% - 0x080..0x700: weak signal => 30% .. 80% - 0x700..0x7ff: no signal => 0% .. 30% - */ - - SARR16( devAddr, SCU_RAM_ATV_CR_LOCK__A, &qualityIndicator ); - qualityIndicator &= SCU_RAM_ATV_CR_LOCK_CR_LOCK__M; - if ( qualityIndicator <= 0x80 ) - { - sigQuality->indicator = 80 + ( (20*(0x80-qualityIndicator))/0x80); - } else if ( qualityIndicator <= 0x700 ) - { - sigQuality->indicator = 30 + - ( (50*(0x700-qualityIndicator))/(0x700-0x81)); - } else { - sigQuality->indicator = - (30*(0x7FF-qualityIndicator))/(0x7FF-0x701); - } - - return (DRX_STS_OK); - rw_error: - return (DRX_STS_ERROR); + pI2CDeviceAddr_t devAddr = NULL; + u16_t qualityIndicator = 0; + + devAddr = demod->myI2CDevAddr; + + /* defined values for fields not used */ + sigQuality->MER = 0; + sigQuality->preViterbiBER = 0; + sigQuality->postViterbiBER = 0; + sigQuality->scaleFactorBER = 1; + sigQuality->packetError = 0; + sigQuality->postReedSolomonBER = 0; + + /* + Mapping: + 0x000..0x080: strong signal => 80% .. 100% + 0x080..0x700: weak signal => 30% .. 80% + 0x700..0x7ff: no signal => 0% .. 30% + */ + + SARR16(devAddr, SCU_RAM_ATV_CR_LOCK__A, &qualityIndicator); + qualityIndicator &= SCU_RAM_ATV_CR_LOCK_CR_LOCK__M; + if (qualityIndicator <= 0x80) { + sigQuality->indicator = + 80 + ((20 * (0x80 - qualityIndicator)) / 0x80); + } else if (qualityIndicator <= 0x700) { + sigQuality->indicator = 30 + + ((50 * (0x700 - qualityIndicator)) / (0x700 - 0x81)); + } else { + sigQuality->indicator = + (30 * (0x7FF - qualityIndicator)) / (0x7FF - 0x701); + } + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); } #endif /* DRXJ_DIGITAL_ONLY */ @@ -10151,28 +9777,25 @@ AtvSigQuality( pDRXDemodInstance_t demod, * \return DRXStatus_t. * */ -static DRXStatus_t -PowerUpAud( pDRXDemodInstance_t demod, - Bool_t setStandard) +static DRXStatus_t PowerUpAud(pDRXDemodInstance_t demod, Bool_t setStandard) { - DRXAudStandard_t audStandard = DRX_AUD_STANDARD_AUTO; - pI2CDeviceAddr_t devAddr = NULL; + DRXAudStandard_t audStandard = DRX_AUD_STANDARD_AUTO; + pI2CDeviceAddr_t devAddr = NULL; - devAddr = demod->myI2CDevAddr; + devAddr = demod->myI2CDevAddr; - WR16( devAddr, AUD_TOP_COMM_EXEC__A, AUD_TOP_COMM_EXEC_ACTIVE); - /* setup TR interface: R/W mode, fifosize=8 */ - WR16( devAddr, AUD_TOP_TR_MDE__A, 8); - WR16( devAddr, AUD_COMM_EXEC__A, AUD_COMM_EXEC_ACTIVE); + WR16(devAddr, AUD_TOP_COMM_EXEC__A, AUD_TOP_COMM_EXEC_ACTIVE); + /* setup TR interface: R/W mode, fifosize=8 */ + WR16(devAddr, AUD_TOP_TR_MDE__A, 8); + WR16(devAddr, AUD_COMM_EXEC__A, AUD_COMM_EXEC_ACTIVE); - if ( setStandard == TRUE ) - { - CHK_ERROR( AUDCtrlSetStandard ( demod, &audStandard ) ); - } + if (setStandard == TRUE) { + CHK_ERROR(AUDCtrlSetStandard(demod, &audStandard)); + } - return DRX_STS_OK; + return DRX_STS_OK; rw_error: - return DRX_STS_ERROR; + return DRX_STS_ERROR; } /*============================================================================*/ @@ -10183,23 +9806,23 @@ rw_error: * \return DRXStatus_t. * */ -static DRXStatus_t -PowerDownAud( pDRXDemodInstance_t demod ) +static DRXStatus_t PowerDownAud(pDRXDemodInstance_t demod) { - pI2CDeviceAddr_t devAddr = NULL; - pDRXJData_t extAttr = NULL; + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; - devAddr = (pI2CDeviceAddr_t)demod->myI2CDevAddr; - extAttr = (pDRXJData_t)demod->myExtAttr; + devAddr = (pI2CDeviceAddr_t) demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; - WR16( devAddr, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP ); + WR16(devAddr, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP); - extAttr->audData.audioIsActive = FALSE; + extAttr->audData.audioIsActive = FALSE; - return DRX_STS_OK; + return DRX_STS_OK; rw_error: - return DRX_STS_ERROR; + return DRX_STS_ERROR; } + /*============================================================================*/ /** * \brief Get Modus data from audio RAM @@ -10208,44 +9831,40 @@ rw_error: * \return DRXStatus_t. * */ -static DRXStatus_t -AUDGetModus ( pDRXDemodInstance_t demod, - pu16_t modus ) +static DRXStatus_t AUDGetModus(pDRXDemodInstance_t demod, pu16_t modus) { - pI2CDeviceAddr_t devAddr = NULL; - pDRXJData_t extAttr = NULL; + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; - u16_t rModus = 0; - u16_t rModusHi = 0; - u16_t rModusLo = 0; + u16_t rModus = 0; + u16_t rModusHi = 0; + u16_t rModusLo = 0; - if ( modus == NULL ) - { - return DRX_STS_INVALID_ARG; - } + if (modus == NULL) { + return DRX_STS_INVALID_ARG; + } - devAddr = (pI2CDeviceAddr_t)demod->myI2CDevAddr; - extAttr = (pDRXJData_t)demod->myExtAttr; + devAddr = (pI2CDeviceAddr_t) demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; - /* power up */ - if ( extAttr->audData.audioIsActive == FALSE ) - { - CHK_ERROR ( PowerUpAud( demod , TRUE ) ); - extAttr->audData.audioIsActive = TRUE; - } + /* power up */ + if (extAttr->audData.audioIsActive == FALSE) { + CHK_ERROR(PowerUpAud(demod, TRUE)); + extAttr->audData.audioIsActive = TRUE; + } - /* Modus register is combined in to RAM location */ - RR16( devAddr, AUD_DEM_RAM_MODUS_HI__A, &rModusHi ); - RR16( devAddr, AUD_DEM_RAM_MODUS_LO__A, &rModusLo ); + /* Modus register is combined in to RAM location */ + RR16(devAddr, AUD_DEM_RAM_MODUS_HI__A, &rModusHi); + RR16(devAddr, AUD_DEM_RAM_MODUS_LO__A, &rModusLo); - rModus = ( (rModusHi << 12 ) & AUD_DEM_RAM_MODUS_HI__M) - | ((( rModusLo & AUD_DEM_RAM_MODUS_LO__M) )); + rModus = ((rModusHi << 12) & AUD_DEM_RAM_MODUS_HI__M) + | (((rModusLo & AUD_DEM_RAM_MODUS_LO__M))); - *modus = rModus; + *modus = rModus; - return DRX_STS_OK; + return DRX_STS_OK; rw_error: - return DRX_STS_ERROR; + return DRX_STS_ERROR; } @@ -10258,75 +9877,65 @@ rw_error: * */ static DRXStatus_t -AUDCtrlGetCfgRDS ( pDRXDemodInstance_t demod, - pDRXCfgAudRDS_t status ) +AUDCtrlGetCfgRDS(pDRXDemodInstance_t demod, pDRXCfgAudRDS_t status) { - pI2CDeviceAddr_t addr = NULL; - pDRXJData_t extAttr = NULL; + pI2CDeviceAddr_t addr = NULL; + pDRXJData_t extAttr = NULL; - u16_t rRDSArrayCntInit = 0; - u16_t rRDSArrayCntCheck = 0; - u16_t rRDSData = 0; - u16_t RDSDataCnt = 0; + u16_t rRDSArrayCntInit = 0; + u16_t rRDSArrayCntCheck = 0; + u16_t rRDSData = 0; + u16_t RDSDataCnt = 0; - addr = (pI2CDeviceAddr_t)demod->myI2CDevAddr; - extAttr = (pDRXJData_t)demod->myExtAttr; + addr = (pI2CDeviceAddr_t) demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; + if (status == NULL) { + return DRX_STS_INVALID_ARG; + } - if ( status == NULL ) - { - return DRX_STS_INVALID_ARG; - } + /* power up */ + if (extAttr->audData.audioIsActive == FALSE) { + CHK_ERROR(PowerUpAud(demod, TRUE)); + extAttr->audData.audioIsActive = TRUE; + } - /* power up */ - if ( extAttr->audData.audioIsActive == FALSE ) - { - CHK_ERROR ( PowerUpAud( demod , TRUE ) ); - extAttr->audData.audioIsActive = TRUE; - } + status->valid = FALSE; - status->valid = FALSE; + RR16(addr, AUD_DEM_RD_RDS_ARRAY_CNT__A, &rRDSArrayCntInit); - RR16( addr, AUD_DEM_RD_RDS_ARRAY_CNT__A, &rRDSArrayCntInit); + if (rRDSArrayCntInit == + AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT_RDS_DATA_NOT_VALID) { + /* invalid data */ + return DRX_STS_OK; + } - if ( rRDSArrayCntInit == - AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT_RDS_DATA_NOT_VALID ) - { - /* invalid data */ - return DRX_STS_OK; - } + if (extAttr->audData.rdsDataCounter == rRDSArrayCntInit) { + /* no new data */ + return DRX_STS_OK; + } - if ( extAttr->audData.rdsDataCounter == rRDSArrayCntInit) - { - /* no new data */ - return DRX_STS_OK; - } - - /* RDS is detected, as long as FM radio is selected assume - RDS will be available */ - extAttr->audData.rdsDataPresent = TRUE; - - /* new data */ - /* read the data */ - for ( RDSDataCnt = 0; - RDSDataCnt < AUD_RDS_ARRAY_SIZE; - RDSDataCnt++) - { - RR16 ( addr, AUD_DEM_RD_RDS_DATA__A, &rRDSData ); - status->data[RDSDataCnt] = rRDSData; - } + /* RDS is detected, as long as FM radio is selected assume + RDS will be available */ + extAttr->audData.rdsDataPresent = TRUE; + + /* new data */ + /* read the data */ + for (RDSDataCnt = 0; RDSDataCnt < AUD_RDS_ARRAY_SIZE; RDSDataCnt++) { + RR16(addr, AUD_DEM_RD_RDS_DATA__A, &rRDSData); + status->data[RDSDataCnt] = rRDSData; + } - RR16( addr, AUD_DEM_RD_RDS_ARRAY_CNT__A, &rRDSArrayCntCheck); + RR16(addr, AUD_DEM_RD_RDS_ARRAY_CNT__A, &rRDSArrayCntCheck); - if ( rRDSArrayCntCheck == rRDSArrayCntInit ) - { - status->valid = TRUE; - extAttr->audData.rdsDataCounter = rRDSArrayCntCheck; - } + if (rRDSArrayCntCheck == rRDSArrayCntInit) { + status->valid = TRUE; + extAttr->audData.rdsDataCounter = rRDSArrayCntCheck; + } - return DRX_STS_OK; + return DRX_STS_OK; rw_error: - return DRX_STS_ERROR; + return DRX_STS_ERROR; } /*============================================================================*/ @@ -10338,87 +9947,75 @@ rw_error: * */ static DRXStatus_t -AUDCtrlGetCarrierDetectStatus ( pDRXDemodInstance_t demod, - pDRXAudStatus_t status ) +AUDCtrlGetCarrierDetectStatus(pDRXDemodInstance_t demod, pDRXAudStatus_t status) { - pDRXJData_t extAttr = NULL; - pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + pI2CDeviceAddr_t devAddr = NULL; - u16_t rData = 0; + u16_t rData = 0; - if ( status == NULL) - { - return DRX_STS_INVALID_ARG; - } + if (status == NULL) { + return DRX_STS_INVALID_ARG; + } - devAddr = (pI2CDeviceAddr_t)demod->myI2CDevAddr; - extAttr = (pDRXJData_t)demod->myExtAttr; + devAddr = (pI2CDeviceAddr_t) demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; - /* power up */ - if ( extAttr->audData.audioIsActive == FALSE ) - { - CHK_ERROR ( PowerUpAud( demod , TRUE ) ); - extAttr->audData.audioIsActive = TRUE; - } - - /* initialize the variables */ - status->carrierA = FALSE; - status->carrierB = FALSE; - status->nicamStatus = DRX_AUD_NICAM_NOT_DETECTED; - status->sap = FALSE; - status->stereo = FALSE; - - /* read stereo sound mode indication */ - RR16( devAddr, AUD_DEM_RD_STATUS__A, &rData ); - - /* carrier a detected */ - if ( (rData & AUD_DEM_RD_STATUS_STAT_CARR_A__M ) == - AUD_DEM_RD_STATUS_STAT_CARR_A_DETECTED ) - { - status->carrierA = TRUE; - } + /* power up */ + if (extAttr->audData.audioIsActive == FALSE) { + CHK_ERROR(PowerUpAud(demod, TRUE)); + extAttr->audData.audioIsActive = TRUE; + } - /* carrier b detected */ - if ( (rData & AUD_DEM_RD_STATUS_STAT_CARR_B__M ) == - AUD_DEM_RD_STATUS_STAT_CARR_B_DETECTED ) - { - status->carrierB = TRUE; - } - /* nicam detected */ - if ( (rData & AUD_DEM_RD_STATUS_STAT_NICAM__M) == - AUD_DEM_RD_STATUS_STAT_NICAM_NICAM_DETECTED) - { - if ((rData & AUD_DEM_RD_STATUS_BAD_NICAM__M) == - AUD_DEM_RD_STATUS_BAD_NICAM_OK) - { - status->nicamStatus = DRX_AUD_NICAM_DETECTED; - } - else - { - status->nicamStatus = DRX_AUD_NICAM_BAD; - } - } - - /* audio mode bilingual or SAP detected */ - if ( (rData & AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__M) == - AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP_SAP) - { - status->sap = TRUE; - } + /* initialize the variables */ + status->carrierA = FALSE; + status->carrierB = FALSE; + status->nicamStatus = DRX_AUD_NICAM_NOT_DETECTED; + status->sap = FALSE; + status->stereo = FALSE; - /* stereo detected */ - if ( (rData & AUD_DEM_RD_STATUS_STAT_STEREO__M) == - AUD_DEM_RD_STATUS_STAT_STEREO_STEREO) - { - status->stereo = TRUE; - } + /* read stereo sound mode indication */ + RR16(devAddr, AUD_DEM_RD_STATUS__A, &rData); - return DRX_STS_OK; + /* carrier a detected */ + if ((rData & AUD_DEM_RD_STATUS_STAT_CARR_A__M) == + AUD_DEM_RD_STATUS_STAT_CARR_A_DETECTED) { + status->carrierA = TRUE; + } + + /* carrier b detected */ + if ((rData & AUD_DEM_RD_STATUS_STAT_CARR_B__M) == + AUD_DEM_RD_STATUS_STAT_CARR_B_DETECTED) { + status->carrierB = TRUE; + } + /* nicam detected */ + if ((rData & AUD_DEM_RD_STATUS_STAT_NICAM__M) == + AUD_DEM_RD_STATUS_STAT_NICAM_NICAM_DETECTED) { + if ((rData & AUD_DEM_RD_STATUS_BAD_NICAM__M) == + AUD_DEM_RD_STATUS_BAD_NICAM_OK) { + status->nicamStatus = DRX_AUD_NICAM_DETECTED; + } else { + status->nicamStatus = DRX_AUD_NICAM_BAD; + } + } + + /* audio mode bilingual or SAP detected */ + if ((rData & AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__M) == + AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP_SAP) { + status->sap = TRUE; + } + + /* stereo detected */ + if ((rData & AUD_DEM_RD_STATUS_STAT_STEREO__M) == + AUD_DEM_RD_STATUS_STAT_STEREO_STEREO) { + status->stereo = TRUE; + } + + return DRX_STS_OK; rw_error: - return DRX_STS_ERROR; + return DRX_STS_ERROR; } - /*============================================================================*/ /** * \brief Get the current audio status parameters @@ -10428,38 +10025,36 @@ rw_error: * */ static DRXStatus_t -AUDCtrlGetStatus ( pDRXDemodInstance_t demod, - pDRXAudStatus_t status ) +AUDCtrlGetStatus(pDRXDemodInstance_t demod, pDRXAudStatus_t status) { - pDRXJData_t extAttr = NULL; - pI2CDeviceAddr_t devAddr = NULL; - DRXCfgAudRDS_t rds = { FALSE, {0} }; - u16_t rData = 0; + pDRXJData_t extAttr = NULL; + pI2CDeviceAddr_t devAddr = NULL; + DRXCfgAudRDS_t rds = { FALSE, {0} }; + u16_t rData = 0; - if ( status == NULL) - { - return DRX_STS_INVALID_ARG; - } + if (status == NULL) { + return DRX_STS_INVALID_ARG; + } - devAddr = (pI2CDeviceAddr_t)demod->myI2CDevAddr; - extAttr = (pDRXJData_t)demod->myExtAttr; + devAddr = (pI2CDeviceAddr_t) demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; - /* carrier detection */ - CHK_ERROR ( AUDCtrlGetCarrierDetectStatus ( demod, status ) ); + /* carrier detection */ + CHK_ERROR(AUDCtrlGetCarrierDetectStatus(demod, status)); - /* rds data */ - status->rds = FALSE; - CHK_ERROR ( AUDCtrlGetCfgRDS ( demod, &rds ) ); - status->rds = extAttr->audData.rdsDataPresent; + /* rds data */ + status->rds = FALSE; + CHK_ERROR(AUDCtrlGetCfgRDS(demod, &rds)); + status->rds = extAttr->audData.rdsDataPresent; - /* fmIdent */ - RR16( devAddr, AUD_DSP_RD_FM_IDENT_VALUE__A, &rData); - rData >>= AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__B; - status->fmIdent = (s8_t)rData; + /* fmIdent */ + RR16(devAddr, AUD_DSP_RD_FM_IDENT_VALUE__A, &rData); + rData >>= AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__B; + status->fmIdent = (s8_t) rData; - return DRX_STS_OK; + return DRX_STS_OK; rw_error: - return DRX_STS_ERROR; + return DRX_STS_ERROR; } /*============================================================================*/ @@ -10471,147 +10066,131 @@ rw_error: * */ static DRXStatus_t -AUDCtrlGetCfgVolume ( pDRXDemodInstance_t demod, - pDRXCfgAudVolume_t volume ) +AUDCtrlGetCfgVolume(pDRXDemodInstance_t demod, pDRXCfgAudVolume_t volume) { - pI2CDeviceAddr_t devAddr = NULL; - pDRXJData_t extAttr = NULL; + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; - u16_t rVolume = 0; - u16_t rAVC = 0; - u16_t rStrengthLeft = 0; - u16_t rStrengthRight = 0; + u16_t rVolume = 0; + u16_t rAVC = 0; + u16_t rStrengthLeft = 0; + u16_t rStrengthRight = 0; - if ( volume == NULL ) - { - return DRX_STS_INVALID_ARG; - } + if (volume == NULL) { + return DRX_STS_INVALID_ARG; + } - devAddr = (pI2CDeviceAddr_t)demod->myI2CDevAddr; - extAttr = (pDRXJData_t)demod->myExtAttr; + devAddr = (pI2CDeviceAddr_t) demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; - /* power up */ - if ( extAttr->audData.audioIsActive == FALSE ) - { - CHK_ERROR ( PowerUpAud( demod , TRUE ) ); - extAttr->audData.audioIsActive = TRUE; - } - - /* volume */ - volume->mute = extAttr->audData.volume.mute; - RR16( devAddr, AUD_DSP_WR_VOLUME__A, &rVolume ); - if ( rVolume == 0 ) - { - volume->mute = TRUE; - volume->volume = extAttr->audData.volume.volume; - } - else - { - volume->mute = FALSE; - volume->volume = ( ( rVolume & AUD_DSP_WR_VOLUME_VOL_MAIN__M ) >> - AUD_DSP_WR_VOLUME_VOL_MAIN__B ) - - AUD_VOLUME_ZERO_DB; - if ( volume->volume < AUD_VOLUME_DB_MIN ) - { - volume->volume = AUD_VOLUME_DB_MIN; - } - if ( volume->volume > AUD_VOLUME_DB_MAX ) - { - volume->volume = AUD_VOLUME_DB_MAX; - } - } - - /* automatic volume control */ - RR16( devAddr, AUD_DSP_WR_AVC__A, &rAVC ); - - if( ( rAVC & AUD_DSP_WR_AVC_AVC_ON__M) == - AUD_DSP_WR_AVC_AVC_ON_OFF ) + /* power up */ + if (extAttr->audData.audioIsActive == FALSE) { + CHK_ERROR(PowerUpAud(demod, TRUE)); + extAttr->audData.audioIsActive = TRUE; + } - { - volume->avcMode = DRX_AUD_AVC_OFF; - } - else - { - switch ( rAVC & AUD_DSP_WR_AVC_AVC_DECAY__M ) - { - case AUD_DSP_WR_AVC_AVC_DECAY_20_MSEC: - volume->avcMode = DRX_AUD_AVC_DECAYTIME_20MS; - break; - case AUD_DSP_WR_AVC_AVC_DECAY_8_SEC: - volume->avcMode = DRX_AUD_AVC_DECAYTIME_8S; - break; - case AUD_DSP_WR_AVC_AVC_DECAY_4_SEC: - volume->avcMode = DRX_AUD_AVC_DECAYTIME_4S; - break; - case AUD_DSP_WR_AVC_AVC_DECAY_2_SEC: - volume->avcMode = DRX_AUD_AVC_DECAYTIME_2S; - break; - default: - return DRX_STS_ERROR; - break; - } - } - - /* max attenuation */ - switch ( rAVC & AUD_DSP_WR_AVC_AVC_MAX_ATT__M ) - { - case AUD_DSP_WR_AVC_AVC_MAX_ATT_12DB: - volume->avcMaxAtten = DRX_AUD_AVC_MAX_ATTEN_12DB; - break; - case AUD_DSP_WR_AVC_AVC_MAX_ATT_18DB: - volume->avcMaxAtten = DRX_AUD_AVC_MAX_ATTEN_18DB; - break; - case AUD_DSP_WR_AVC_AVC_MAX_ATT_24DB: - volume->avcMaxAtten = DRX_AUD_AVC_MAX_ATTEN_24DB; - break; - default: - return DRX_STS_ERROR; - break; - } - - /* max gain */ - switch ( rAVC & AUD_DSP_WR_AVC_AVC_MAX_GAIN__M ) - { - case AUD_DSP_WR_AVC_AVC_MAX_GAIN_0DB: - volume->avcMaxGain = DRX_AUD_AVC_MAX_GAIN_0DB; - break; - case AUD_DSP_WR_AVC_AVC_MAX_GAIN_6DB: - volume->avcMaxGain = DRX_AUD_AVC_MAX_GAIN_6DB; - break; - case AUD_DSP_WR_AVC_AVC_MAX_GAIN_12DB: - volume->avcMaxGain = DRX_AUD_AVC_MAX_GAIN_12DB; - break; - default: - return DRX_STS_ERROR; - break; - } - - /* reference level */ - volume->avcRefLevel = (u16_t)( ( rAVC & AUD_DSP_WR_AVC_AVC_REF_LEV__M) >> - AUD_DSP_WR_AVC_AVC_REF_LEV__B ); - - /* read qpeak registers and calculate strength of left and right carrier */ - /* quasi peaks formula: QP(dB) = 20 * log( AUD_DSP_RD_QPEAKx / Q(0dB) */ - /* Q(0dB) represents QP value of 0dB (hex value 0x4000) */ - /* left carrier */ - - /* QP vaues */ - /* left carrier */ - RR16 (devAddr, AUD_DSP_RD_QPEAK_L__A, &rStrengthLeft); - volume->strengthLeft = ( ( (s16_t) Log10Times100 ( rStrengthLeft ) ) - - AUD_CARRIER_STRENGTH_QP_0DB_LOG10T100 ) / 5; - - /* right carrier */ - RR16 (devAddr, AUD_DSP_RD_QPEAK_R__A, &rStrengthRight); - volume->strengthRight = ( ( (s16_t) Log10Times100 ( rStrengthRight ) ) - - AUD_CARRIER_STRENGTH_QP_0DB_LOG10T100 ) / 5; - - return DRX_STS_OK; + /* volume */ + volume->mute = extAttr->audData.volume.mute; + RR16(devAddr, AUD_DSP_WR_VOLUME__A, &rVolume); + if (rVolume == 0) { + volume->mute = TRUE; + volume->volume = extAttr->audData.volume.volume; + } else { + volume->mute = FALSE; + volume->volume = ((rVolume & AUD_DSP_WR_VOLUME_VOL_MAIN__M) >> + AUD_DSP_WR_VOLUME_VOL_MAIN__B) - + AUD_VOLUME_ZERO_DB; + if (volume->volume < AUD_VOLUME_DB_MIN) { + volume->volume = AUD_VOLUME_DB_MIN; + } + if (volume->volume > AUD_VOLUME_DB_MAX) { + volume->volume = AUD_VOLUME_DB_MAX; + } + } + + /* automatic volume control */ + RR16(devAddr, AUD_DSP_WR_AVC__A, &rAVC); + + if ((rAVC & AUD_DSP_WR_AVC_AVC_ON__M) == AUD_DSP_WR_AVC_AVC_ON_OFF) + { + volume->avcMode = DRX_AUD_AVC_OFF; + } else { + switch (rAVC & AUD_DSP_WR_AVC_AVC_DECAY__M) { + case AUD_DSP_WR_AVC_AVC_DECAY_20_MSEC: + volume->avcMode = DRX_AUD_AVC_DECAYTIME_20MS; + break; + case AUD_DSP_WR_AVC_AVC_DECAY_8_SEC: + volume->avcMode = DRX_AUD_AVC_DECAYTIME_8S; + break; + case AUD_DSP_WR_AVC_AVC_DECAY_4_SEC: + volume->avcMode = DRX_AUD_AVC_DECAYTIME_4S; + break; + case AUD_DSP_WR_AVC_AVC_DECAY_2_SEC: + volume->avcMode = DRX_AUD_AVC_DECAYTIME_2S; + break; + default: + return DRX_STS_ERROR; + break; + } + } + + /* max attenuation */ + switch (rAVC & AUD_DSP_WR_AVC_AVC_MAX_ATT__M) { + case AUD_DSP_WR_AVC_AVC_MAX_ATT_12DB: + volume->avcMaxAtten = DRX_AUD_AVC_MAX_ATTEN_12DB; + break; + case AUD_DSP_WR_AVC_AVC_MAX_ATT_18DB: + volume->avcMaxAtten = DRX_AUD_AVC_MAX_ATTEN_18DB; + break; + case AUD_DSP_WR_AVC_AVC_MAX_ATT_24DB: + volume->avcMaxAtten = DRX_AUD_AVC_MAX_ATTEN_24DB; + break; + default: + return DRX_STS_ERROR; + break; + } + + /* max gain */ + switch (rAVC & AUD_DSP_WR_AVC_AVC_MAX_GAIN__M) { + case AUD_DSP_WR_AVC_AVC_MAX_GAIN_0DB: + volume->avcMaxGain = DRX_AUD_AVC_MAX_GAIN_0DB; + break; + case AUD_DSP_WR_AVC_AVC_MAX_GAIN_6DB: + volume->avcMaxGain = DRX_AUD_AVC_MAX_GAIN_6DB; + break; + case AUD_DSP_WR_AVC_AVC_MAX_GAIN_12DB: + volume->avcMaxGain = DRX_AUD_AVC_MAX_GAIN_12DB; + break; + default: + return DRX_STS_ERROR; + break; + } + + /* reference level */ + volume->avcRefLevel = (u16_t) ((rAVC & AUD_DSP_WR_AVC_AVC_REF_LEV__M) >> + AUD_DSP_WR_AVC_AVC_REF_LEV__B); + + /* read qpeak registers and calculate strength of left and right carrier */ + /* quasi peaks formula: QP(dB) = 20 * log( AUD_DSP_RD_QPEAKx / Q(0dB) */ + /* Q(0dB) represents QP value of 0dB (hex value 0x4000) */ + /* left carrier */ + + /* QP vaues */ + /* left carrier */ + RR16(devAddr, AUD_DSP_RD_QPEAK_L__A, &rStrengthLeft); + volume->strengthLeft = (((s16_t) Log10Times100(rStrengthLeft)) - + AUD_CARRIER_STRENGTH_QP_0DB_LOG10T100) / 5; + + /* right carrier */ + RR16(devAddr, AUD_DSP_RD_QPEAK_R__A, &rStrengthRight); + volume->strengthRight = (((s16_t) Log10Times100(rStrengthRight)) - + AUD_CARRIER_STRENGTH_QP_0DB_LOG10T100) / 5; + + return DRX_STS_OK; rw_error: - return DRX_STS_ERROR; + return DRX_STS_ERROR; } - /*============================================================================*/ /** * \brief Set the current volume settings @@ -10621,148 +10200,132 @@ rw_error: * */ static DRXStatus_t -AUDCtrlSetCfgVolume ( pDRXDemodInstance_t demod, - pDRXCfgAudVolume_t volume ) +AUDCtrlSetCfgVolume(pDRXDemodInstance_t demod, pDRXCfgAudVolume_t volume) { - pI2CDeviceAddr_t devAddr = NULL; - pDRXJData_t extAttr = NULL; - - u16_t wVolume = 0; - u16_t wAVC = 0; + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + u16_t wVolume = 0; + u16_t wAVC = 0; - if ( volume == NULL ) - { - return DRX_STS_INVALID_ARG; - } + if (volume == NULL) { + return DRX_STS_INVALID_ARG; + } - devAddr = (pI2CDeviceAddr_t)demod->myI2CDevAddr; - extAttr = (pDRXJData_t)demod->myExtAttr; + devAddr = (pI2CDeviceAddr_t) demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; - /* power up */ - if ( extAttr->audData.audioIsActive == FALSE ) - { - CHK_ERROR ( PowerUpAud( demod , TRUE ) ); - extAttr->audData.audioIsActive = TRUE; - } - - /* volume */ - /* volume range from -60 to 12 (expressed in dB) */ - if ( ( volume->volume < AUD_VOLUME_DB_MIN ) || - ( volume->volume > AUD_VOLUME_DB_MAX ) ) - { - return DRX_STS_INVALID_ARG; - } + /* power up */ + if (extAttr->audData.audioIsActive == FALSE) { + CHK_ERROR(PowerUpAud(demod, TRUE)); + extAttr->audData.audioIsActive = TRUE; + } - RR16( devAddr, AUD_DSP_WR_VOLUME__A, &wVolume ); + /* volume */ + /* volume range from -60 to 12 (expressed in dB) */ + if ((volume->volume < AUD_VOLUME_DB_MIN) || + (volume->volume > AUD_VOLUME_DB_MAX)) { + return DRX_STS_INVALID_ARG; + } - /* clear the volume mask */ - wVolume &= (u16_t)~AUD_DSP_WR_VOLUME_VOL_MAIN__M; - if ( volume->mute == TRUE ) - { - /* mute */ - /* mute overrules volume */ - wVolume |= (u16_t) ( 0 ); + RR16(devAddr, AUD_DSP_WR_VOLUME__A, &wVolume); - } - else - { - wVolume |= (u16_t) ( ( volume->volume + AUD_VOLUME_ZERO_DB ) << - AUD_DSP_WR_VOLUME_VOL_MAIN__B ); - } + /* clear the volume mask */ + wVolume &= (u16_t) ~ AUD_DSP_WR_VOLUME_VOL_MAIN__M; + if (volume->mute == TRUE) { + /* mute */ + /* mute overrules volume */ + wVolume |= (u16_t) (0); - WR16( devAddr, AUD_DSP_WR_VOLUME__A, wVolume ); + } else { + wVolume |= (u16_t) ((volume->volume + AUD_VOLUME_ZERO_DB) << + AUD_DSP_WR_VOLUME_VOL_MAIN__B); + } - /* automatic volume control */ - RR16( devAddr, AUD_DSP_WR_AVC__A, &wAVC ); + WR16(devAddr, AUD_DSP_WR_VOLUME__A, wVolume); + + /* automatic volume control */ + RR16(devAddr, AUD_DSP_WR_AVC__A, &wAVC); + + /* clear masks that require writing */ + wAVC &= (u16_t) ~ AUD_DSP_WR_AVC_AVC_ON__M; + wAVC &= (u16_t) ~ AUD_DSP_WR_AVC_AVC_DECAY__M; + + if (volume->avcMode == DRX_AUD_AVC_OFF) { + wAVC |= (AUD_DSP_WR_AVC_AVC_ON_OFF); + } else { + + wAVC |= (AUD_DSP_WR_AVC_AVC_ON_ON); + + /* avc decay */ + switch (volume->avcMode) { + case DRX_AUD_AVC_DECAYTIME_20MS: + wAVC |= AUD_DSP_WR_AVC_AVC_DECAY_20_MSEC; + break; + case DRX_AUD_AVC_DECAYTIME_8S: + wAVC |= AUD_DSP_WR_AVC_AVC_DECAY_8_SEC; + break; + case DRX_AUD_AVC_DECAYTIME_4S: + wAVC |= AUD_DSP_WR_AVC_AVC_DECAY_4_SEC; + break; + case DRX_AUD_AVC_DECAYTIME_2S: + wAVC |= AUD_DSP_WR_AVC_AVC_DECAY_2_SEC; + break; + default: + return DRX_STS_INVALID_ARG; + } + } - /* clear masks that require writing */ - wAVC &= (u16_t) ~AUD_DSP_WR_AVC_AVC_ON__M; - wAVC &= (u16_t) ~AUD_DSP_WR_AVC_AVC_DECAY__M; + /* max attenuation */ + wAVC &= (u16_t) ~ AUD_DSP_WR_AVC_AVC_MAX_ATT__M; + switch (volume->avcMaxAtten) { + case DRX_AUD_AVC_MAX_ATTEN_12DB: + wAVC |= AUD_DSP_WR_AVC_AVC_MAX_ATT_12DB; + break; + case DRX_AUD_AVC_MAX_ATTEN_18DB: + wAVC |= AUD_DSP_WR_AVC_AVC_MAX_ATT_18DB; + break; + case DRX_AUD_AVC_MAX_ATTEN_24DB: + wAVC |= AUD_DSP_WR_AVC_AVC_MAX_ATT_24DB; + break; + default: + return DRX_STS_INVALID_ARG; + } - if ( volume->avcMode == DRX_AUD_AVC_OFF ) - { - wAVC |= ( AUD_DSP_WR_AVC_AVC_ON_OFF ); - } - else - { + /* max gain */ + wAVC &= (u16_t) ~ AUD_DSP_WR_AVC_AVC_MAX_GAIN__M; + switch (volume->avcMaxGain) { + case DRX_AUD_AVC_MAX_GAIN_0DB: + wAVC |= AUD_DSP_WR_AVC_AVC_MAX_GAIN_0DB; + break; + case DRX_AUD_AVC_MAX_GAIN_6DB: + wAVC |= AUD_DSP_WR_AVC_AVC_MAX_GAIN_6DB; + break; + case DRX_AUD_AVC_MAX_GAIN_12DB: + wAVC |= AUD_DSP_WR_AVC_AVC_MAX_GAIN_12DB; + break; + default: + return DRX_STS_INVALID_ARG; + } - wAVC |= ( AUD_DSP_WR_AVC_AVC_ON_ON ); - - /* avc decay */ - switch ( volume->avcMode ) - { - case DRX_AUD_AVC_DECAYTIME_20MS: - wAVC |= AUD_DSP_WR_AVC_AVC_DECAY_20_MSEC; - break; - case DRX_AUD_AVC_DECAYTIME_8S: - wAVC |= AUD_DSP_WR_AVC_AVC_DECAY_8_SEC; - break; - case DRX_AUD_AVC_DECAYTIME_4S: - wAVC |= AUD_DSP_WR_AVC_AVC_DECAY_4_SEC; - break; - case DRX_AUD_AVC_DECAYTIME_2S: - wAVC |= AUD_DSP_WR_AVC_AVC_DECAY_2_SEC; - break; - default: - return DRX_STS_INVALID_ARG; - } - } - - /* max attenuation */ - wAVC &= (u16_t) ~AUD_DSP_WR_AVC_AVC_MAX_ATT__M; - switch ( volume->avcMaxAtten ) - { - case DRX_AUD_AVC_MAX_ATTEN_12DB: - wAVC |= AUD_DSP_WR_AVC_AVC_MAX_ATT_12DB; - break; - case DRX_AUD_AVC_MAX_ATTEN_18DB: - wAVC |= AUD_DSP_WR_AVC_AVC_MAX_ATT_18DB; - break; - case DRX_AUD_AVC_MAX_ATTEN_24DB: - wAVC |= AUD_DSP_WR_AVC_AVC_MAX_ATT_24DB; - break; - default: - return DRX_STS_INVALID_ARG; - } - - /* max gain */ - wAVC &= (u16_t) ~AUD_DSP_WR_AVC_AVC_MAX_GAIN__M; - switch ( volume->avcMaxGain ) - { - case DRX_AUD_AVC_MAX_GAIN_0DB: - wAVC |= AUD_DSP_WR_AVC_AVC_MAX_GAIN_0DB; - break; - case DRX_AUD_AVC_MAX_GAIN_6DB: - wAVC |= AUD_DSP_WR_AVC_AVC_MAX_GAIN_6DB; - break; - case DRX_AUD_AVC_MAX_GAIN_12DB: - wAVC |= AUD_DSP_WR_AVC_AVC_MAX_GAIN_12DB; - break; - default: - return DRX_STS_INVALID_ARG; - } - - /* avc reference level */ - if ( volume->avcRefLevel > AUD_MAX_AVC_REF_LEVEL ) - { - return DRX_STS_INVALID_ARG; - } + /* avc reference level */ + if (volume->avcRefLevel > AUD_MAX_AVC_REF_LEVEL) { + return DRX_STS_INVALID_ARG; + } - wAVC &= (u16_t)~AUD_DSP_WR_AVC_AVC_REF_LEV__M; - wAVC |= (u16_t)( volume->avcRefLevel << AUD_DSP_WR_AVC_AVC_REF_LEV__B ); + wAVC &= (u16_t) ~ AUD_DSP_WR_AVC_AVC_REF_LEV__M; + wAVC |= (u16_t) (volume->avcRefLevel << AUD_DSP_WR_AVC_AVC_REF_LEV__B); - WR16( devAddr, AUD_DSP_WR_AVC__A, wAVC ); + WR16(devAddr, AUD_DSP_WR_AVC__A, wAVC); - /* all done, store config in data structure */ - extAttr->audData.volume = *volume; + /* all done, store config in data structure */ + extAttr->audData.volume = *volume; - return DRX_STS_OK; + return DRX_STS_OK; rw_error: - return DRX_STS_ERROR; + return DRX_STS_ERROR; } - /*============================================================================*/ /** * \brief Get the I2S settings @@ -10772,112 +10335,98 @@ rw_error: * */ static DRXStatus_t -AUDCtrlGetCfgOutputI2S ( pDRXDemodInstance_t demod, - pDRXCfgI2SOutput_t output ) +AUDCtrlGetCfgOutputI2S(pDRXDemodInstance_t demod, pDRXCfgI2SOutput_t output) { - pI2CDeviceAddr_t devAddr = NULL; - pDRXJData_t extAttr = NULL; + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; - u16_t wI2SConfig = 0; - u16_t rI2SFreq = 0; + u16_t wI2SConfig = 0; + u16_t rI2SFreq = 0; - if ( output == NULL ) - { - return DRX_STS_INVALID_ARG; - } + if (output == NULL) { + return DRX_STS_INVALID_ARG; + } - devAddr = (pI2CDeviceAddr_t)demod->myI2CDevAddr; - extAttr = (pDRXJData_t)demod->myExtAttr; + devAddr = (pI2CDeviceAddr_t) demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; - /* power up */ - if ( extAttr->audData.audioIsActive == FALSE ) - { - CHK_ERROR ( PowerUpAud( demod , TRUE ) ); - extAttr->audData.audioIsActive = TRUE; - } + /* power up */ + if (extAttr->audData.audioIsActive == FALSE) { + CHK_ERROR(PowerUpAud(demod, TRUE)); + extAttr->audData.audioIsActive = TRUE; + } - RR16( devAddr, AUD_DEM_RAM_I2S_CONFIG2__A, &wI2SConfig ); - RR16( devAddr, AUD_DSP_WR_I2S_OUT_FS__A, &rI2SFreq ); + RR16(devAddr, AUD_DEM_RAM_I2S_CONFIG2__A, &wI2SConfig); + RR16(devAddr, AUD_DSP_WR_I2S_OUT_FS__A, &rI2SFreq); + + /* I2S mode */ + switch (wI2SConfig & AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__M) { + case AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST_MASTER: + output->mode = DRX_I2S_MODE_MASTER; + break; + case AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST_SLAVE: + output->mode = DRX_I2S_MODE_SLAVE; + break; + default: + return DRX_STS_ERROR; + } - /* I2S mode */ - switch ( wI2SConfig & AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__M ) - { - case AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST_MASTER: - output->mode = DRX_I2S_MODE_MASTER; - break; - case AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST_SLAVE: - output->mode = DRX_I2S_MODE_SLAVE; - break; - default: - return DRX_STS_ERROR; - } - - /* I2S format */ - switch ( wI2SConfig & AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__M ) - { - case AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE_DELAY: - output->format = DRX_I2S_FORMAT_WS_ADVANCED; - break; - case AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE_NO_DELAY: - output->format = DRX_I2S_FORMAT_WS_WITH_DATA; - break; - default: - return DRX_STS_ERROR; - } - - /* I2S word length */ - switch ( wI2SConfig & AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__M ) - { - case AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_16: - output->wordLength = DRX_I2S_WORDLENGTH_16; - break; - case AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_32: - output->wordLength = DRX_I2S_WORDLENGTH_32; - break; - default: - return DRX_STS_ERROR; - } - - /* I2S polarity */ - switch ( wI2SConfig & AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__M ) - { - case AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL_LEFT_HIGH: - output->polarity = DRX_I2S_POLARITY_LEFT; - break; - case AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL_LEFT_LOW: - output->polarity = DRX_I2S_POLARITY_RIGHT; - break; - default: - return DRX_STS_ERROR; - } - - /* I2S output enabled */ - if ( ( wI2SConfig & AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__M ) - == AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_ENABLE ) - { - output->outputEnable = TRUE; - } - else - { - output->outputEnable = FALSE; - } + /* I2S format */ + switch (wI2SConfig & AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__M) { + case AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE_DELAY: + output->format = DRX_I2S_FORMAT_WS_ADVANCED; + break; + case AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE_NO_DELAY: + output->format = DRX_I2S_FORMAT_WS_WITH_DATA; + break; + default: + return DRX_STS_ERROR; + } - if ( rI2SFreq > 0 ) - { - output->frequency = 6144UL * 48000 / rI2SFreq; - if ( output->wordLength == DRX_I2S_WORDLENGTH_16 ) - { - output->frequency *= 2; - } - } - else - { - output->frequency = AUD_I2S_FREQUENCY_MAX; - } + /* I2S word length */ + switch (wI2SConfig & AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__M) { + case AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_16: + output->wordLength = DRX_I2S_WORDLENGTH_16; + break; + case AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_32: + output->wordLength = DRX_I2S_WORDLENGTH_32; + break; + default: + return DRX_STS_ERROR; + } - return DRX_STS_OK; + /* I2S polarity */ + switch (wI2SConfig & AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__M) { + case AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL_LEFT_HIGH: + output->polarity = DRX_I2S_POLARITY_LEFT; + break; + case AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL_LEFT_LOW: + output->polarity = DRX_I2S_POLARITY_RIGHT; + break; + default: + return DRX_STS_ERROR; + } + + /* I2S output enabled */ + if ((wI2SConfig & AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__M) + == AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_ENABLE) { + output->outputEnable = TRUE; + } else { + output->outputEnable = FALSE; + } + + if (rI2SFreq > 0) { + output->frequency = 6144UL * 48000 / rI2SFreq; + if (output->wordLength == DRX_I2S_WORDLENGTH_16) { + output->frequency *= 2; + } + } else { + output->frequency = AUD_I2S_FREQUENCY_MAX; + } + + return DRX_STS_OK; rw_error: - return DRX_STS_ERROR; + return DRX_STS_ERROR; } /*============================================================================*/ @@ -10889,165 +10438,149 @@ rw_error: * */ static DRXStatus_t -AUDCtrlSetCfgOutputI2S ( pDRXDemodInstance_t demod, - pDRXCfgI2SOutput_t output ) +AUDCtrlSetCfgOutputI2S(pDRXDemodInstance_t demod, pDRXCfgI2SOutput_t output) { - pI2CDeviceAddr_t devAddr = NULL; - pDRXJData_t extAttr = NULL; + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; - u16_t wI2SConfig = 0; - u16_t wI2SPadsDataDa = 0; - u16_t wI2SPadsDataCl = 0; - u16_t wI2SPadsDataWs = 0; - u32_t wI2SFreq = 0; + u16_t wI2SConfig = 0; + u16_t wI2SPadsDataDa = 0; + u16_t wI2SPadsDataCl = 0; + u16_t wI2SPadsDataWs = 0; + u32_t wI2SFreq = 0; - if ( output == NULL ) - { - return DRX_STS_INVALID_ARG; - } + if (output == NULL) { + return DRX_STS_INVALID_ARG; + } - devAddr = (pI2CDeviceAddr_t)demod->myI2CDevAddr; - extAttr = (pDRXJData_t)demod->myExtAttr; + devAddr = (pI2CDeviceAddr_t) demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; - /* power up */ - if ( extAttr->audData.audioIsActive == FALSE ) - { - CHK_ERROR ( PowerUpAud( demod , TRUE ) ); - extAttr->audData.audioIsActive = TRUE; - } + /* power up */ + if (extAttr->audData.audioIsActive == FALSE) { + CHK_ERROR(PowerUpAud(demod, TRUE)); + extAttr->audData.audioIsActive = TRUE; + } - RR16( devAddr, AUD_DEM_RAM_I2S_CONFIG2__A, &wI2SConfig ); + RR16(devAddr, AUD_DEM_RAM_I2S_CONFIG2__A, &wI2SConfig); - /* I2S mode */ - wI2SConfig &= (u16_t)~AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__M; + /* I2S mode */ + wI2SConfig &= (u16_t) ~ AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__M; - switch ( output->mode ) - { - case DRX_I2S_MODE_MASTER: - wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST_MASTER; - break; - case DRX_I2S_MODE_SLAVE: - wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST_SLAVE; - break; - default: - return DRX_STS_INVALID_ARG; - } - - /* I2S format */ - wI2SConfig &= (u16_t)~AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__M; - - switch ( output->format ) - { - case DRX_I2S_FORMAT_WS_ADVANCED: - wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE_DELAY; - break; - case DRX_I2S_FORMAT_WS_WITH_DATA: - wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE_NO_DELAY; - break; - default: - return DRX_STS_INVALID_ARG; - } - - /* I2S word length */ - wI2SConfig &= (u16_t)~AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__M; - - switch ( output->wordLength ) - { - case DRX_I2S_WORDLENGTH_16: - wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_16; - break; - case DRX_I2S_WORDLENGTH_32: - wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_32; - break; - default: - return DRX_STS_INVALID_ARG; - } - - /* I2S polarity */ - wI2SConfig &= (u16_t)~AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__M; - switch ( output->polarity ) - { - case DRX_I2S_POLARITY_LEFT: - wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL_LEFT_HIGH; - break; - case DRX_I2S_POLARITY_RIGHT: - wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL_LEFT_LOW; - break; - default: - return DRX_STS_INVALID_ARG; - } - - /* I2S output enabled */ - wI2SConfig &= (u16_t)~AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__M; - if ( output->outputEnable == TRUE ) - { - wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_ENABLE; - } - else - { - wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_DISABLE; - } + switch (output->mode) { + case DRX_I2S_MODE_MASTER: + wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST_MASTER; + break; + case DRX_I2S_MODE_SLAVE: + wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST_SLAVE; + break; + default: + return DRX_STS_INVALID_ARG; + } - /* - I2S frequency + /* I2S format */ + wI2SConfig &= (u16_t) ~ AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__M; + + switch (output->format) { + case DRX_I2S_FORMAT_WS_ADVANCED: + wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE_DELAY; + break; + case DRX_I2S_FORMAT_WS_WITH_DATA: + wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE_NO_DELAY; + break; + default: + return DRX_STS_INVALID_ARG; + } - wI2SFreq = 6144 * 48000 * nrbits / ( 32 * frequency ) + /* I2S word length */ + wI2SConfig &= (u16_t) ~ AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__M; + + switch (output->wordLength) { + case DRX_I2S_WORDLENGTH_16: + wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_16; + break; + case DRX_I2S_WORDLENGTH_32: + wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_32; + break; + default: + return DRX_STS_INVALID_ARG; + } - 16bit: 6144 * 48000 / ( 2 * freq ) = ( 6144 * 48000 / freq ) / 2 - 32bit: 6144 * 48000 / freq = ( 6144 * 48000 / freq ) - */ - if ( ( output->frequency > AUD_I2S_FREQUENCY_MAX ) || - output->frequency < AUD_I2S_FREQUENCY_MIN ) - { - return DRX_STS_INVALID_ARG; - } + /* I2S polarity */ + wI2SConfig &= (u16_t) ~ AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__M; + switch (output->polarity) { + case DRX_I2S_POLARITY_LEFT: + wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL_LEFT_HIGH; + break; + case DRX_I2S_POLARITY_RIGHT: + wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL_LEFT_LOW; + break; + default: + return DRX_STS_INVALID_ARG; + } + + /* I2S output enabled */ + wI2SConfig &= (u16_t) ~ AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__M; + if (output->outputEnable == TRUE) { + wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_ENABLE; + } else { + wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_DISABLE; + } - wI2SFreq = (6144UL * 48000UL) + (output->frequency >> 1); - wI2SFreq /= output->frequency; + /* + I2S frequency - if ( output->wordLength == DRX_I2S_WORDLENGTH_16 ) - { - wI2SFreq *= 2; - } + wI2SFreq = 6144 * 48000 * nrbits / ( 32 * frequency ) - WR16( devAddr, AUD_DEM_WR_I2S_CONFIG2__A, wI2SConfig ); - WR16( devAddr, AUD_DSP_WR_I2S_OUT_FS__A, (u16_t) wI2SFreq ); + 16bit: 6144 * 48000 / ( 2 * freq ) = ( 6144 * 48000 / freq ) / 2 + 32bit: 6144 * 48000 / freq = ( 6144 * 48000 / freq ) + */ + if ((output->frequency > AUD_I2S_FREQUENCY_MAX) || + output->frequency < AUD_I2S_FREQUENCY_MIN) { + return DRX_STS_INVALID_ARG; + } - /* configure I2S output pads for master or slave mode */ - WR16( devAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY ); + wI2SFreq = (6144UL * 48000UL) + (output->frequency >> 1); + wI2SFreq /= output->frequency; - if (output->mode == DRX_I2S_MODE_MASTER) - { - wI2SPadsDataDa = SIO_PDR_I2S_DA_CFG_MODE__MASTER | - SIO_PDR_I2S_DA_CFG_DRIVE__MASTER; - wI2SPadsDataCl = SIO_PDR_I2S_CL_CFG_MODE__MASTER | - SIO_PDR_I2S_CL_CFG_DRIVE__MASTER; - wI2SPadsDataWs = SIO_PDR_I2S_WS_CFG_MODE__MASTER | - SIO_PDR_I2S_WS_CFG_DRIVE__MASTER; - } - else - { - wI2SPadsDataDa = SIO_PDR_I2S_DA_CFG_MODE__SLAVE | - SIO_PDR_I2S_DA_CFG_DRIVE__SLAVE; - wI2SPadsDataCl = SIO_PDR_I2S_CL_CFG_MODE__SLAVE | - SIO_PDR_I2S_CL_CFG_DRIVE__SLAVE; - wI2SPadsDataWs = SIO_PDR_I2S_WS_CFG_MODE__SLAVE | - SIO_PDR_I2S_WS_CFG_DRIVE__SLAVE; - } + if (output->wordLength == DRX_I2S_WORDLENGTH_16) { + wI2SFreq *= 2; + } - WR16( devAddr, SIO_PDR_I2S_DA_CFG__A, wI2SPadsDataDa ); - WR16( devAddr, SIO_PDR_I2S_CL_CFG__A, wI2SPadsDataCl ); - WR16( devAddr, SIO_PDR_I2S_WS_CFG__A, wI2SPadsDataWs ); + WR16(devAddr, AUD_DEM_WR_I2S_CONFIG2__A, wI2SConfig); + WR16(devAddr, AUD_DSP_WR_I2S_OUT_FS__A, (u16_t) wI2SFreq); + + /* configure I2S output pads for master or slave mode */ + WR16(devAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); + + if (output->mode == DRX_I2S_MODE_MASTER) { + wI2SPadsDataDa = SIO_PDR_I2S_DA_CFG_MODE__MASTER | + SIO_PDR_I2S_DA_CFG_DRIVE__MASTER; + wI2SPadsDataCl = SIO_PDR_I2S_CL_CFG_MODE__MASTER | + SIO_PDR_I2S_CL_CFG_DRIVE__MASTER; + wI2SPadsDataWs = SIO_PDR_I2S_WS_CFG_MODE__MASTER | + SIO_PDR_I2S_WS_CFG_DRIVE__MASTER; + } else { + wI2SPadsDataDa = SIO_PDR_I2S_DA_CFG_MODE__SLAVE | + SIO_PDR_I2S_DA_CFG_DRIVE__SLAVE; + wI2SPadsDataCl = SIO_PDR_I2S_CL_CFG_MODE__SLAVE | + SIO_PDR_I2S_CL_CFG_DRIVE__SLAVE; + wI2SPadsDataWs = SIO_PDR_I2S_WS_CFG_MODE__SLAVE | + SIO_PDR_I2S_WS_CFG_DRIVE__SLAVE; + } - WR16( devAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE ); + WR16(devAddr, SIO_PDR_I2S_DA_CFG__A, wI2SPadsDataDa); + WR16(devAddr, SIO_PDR_I2S_CL_CFG__A, wI2SPadsDataCl); + WR16(devAddr, SIO_PDR_I2S_WS_CFG__A, wI2SPadsDataWs); + WR16(devAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE); - /* all done, store config in data structure */ - extAttr->audData.i2sdata = *output; + /* all done, store config in data structure */ + extAttr->audData.i2sdata = *output; - return DRX_STS_OK; + return DRX_STS_OK; rw_error: - return DRX_STS_ERROR; + return DRX_STS_ERROR; } /*============================================================================*/ @@ -11060,57 +10593,53 @@ rw_error: * */ static DRXStatus_t -AUDCtrlGetCfgAutoSound ( pDRXDemodInstance_t demod, - pDRXCfgAudAutoSound_t autoSound ) +AUDCtrlGetCfgAutoSound(pDRXDemodInstance_t demod, + pDRXCfgAudAutoSound_t autoSound) { - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)NULL; - pDRXJData_t extAttr = (pDRXJData_t)NULL; + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) NULL; + pDRXJData_t extAttr = (pDRXJData_t) NULL; - u16_t rModus = 0; + u16_t rModus = 0; - if ( autoSound == NULL ) - { - return DRX_STS_INVALID_ARG; - } + if (autoSound == NULL) { + return DRX_STS_INVALID_ARG; + } - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t)demod->myExtAttr; + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; - /* power up */ - if ( extAttr->audData.audioIsActive == FALSE ) - { - CHK_ERROR ( PowerUpAud( demod , TRUE ) ); - extAttr->audData.audioIsActive = TRUE; - } + /* power up */ + if (extAttr->audData.audioIsActive == FALSE) { + CHK_ERROR(PowerUpAud(demod, TRUE)); + extAttr->audData.audioIsActive = TRUE; + } - CHK_ERROR ( AUDGetModus ( demod, &rModus )); + CHK_ERROR(AUDGetModus(demod, &rModus)); + + switch (rModus & (AUD_DEM_WR_MODUS_MOD_ASS__M | + AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__M)) { + case AUD_DEM_WR_MODUS_MOD_ASS_OFF | AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_DISABLED: + case AUD_DEM_WR_MODUS_MOD_ASS_OFF | AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_ENABLED: + *autoSound = + DRX_AUD_AUTO_SOUND_OFF; + break; + case AUD_DEM_WR_MODUS_MOD_ASS_ON | AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_ENABLED: + *autoSound = + DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON; + break; + case AUD_DEM_WR_MODUS_MOD_ASS_ON | AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_DISABLED: + *autoSound = + DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_OFF; + break; + default: + return DRX_STS_ERROR; + } - switch ( rModus & ( AUD_DEM_WR_MODUS_MOD_ASS__M | - AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__M ) ) - { - case AUD_DEM_WR_MODUS_MOD_ASS_OFF | - AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_DISABLED: - case AUD_DEM_WR_MODUS_MOD_ASS_OFF | - AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_ENABLED: - *autoSound = DRX_AUD_AUTO_SOUND_OFF; - break; - case AUD_DEM_WR_MODUS_MOD_ASS_ON | - AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_ENABLED: - *autoSound = DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON; - break; - case AUD_DEM_WR_MODUS_MOD_ASS_ON | - AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_DISABLED: - *autoSound = DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_OFF; - break; - default: - return DRX_STS_ERROR; - } - - - return DRX_STS_OK; + return DRX_STS_OK; rw_error: - return DRX_STS_ERROR; + return DRX_STS_ERROR; } + /*============================================================================*/ /** * \brief Set the Automatic Standard Select (ASS) @@ -11121,66 +10650,61 @@ rw_error: * */ static DRXStatus_t -AUDCtrSetlCfgAutoSound ( pDRXDemodInstance_t demod, - pDRXCfgAudAutoSound_t autoSound ) +AUDCtrSetlCfgAutoSound(pDRXDemodInstance_t demod, + pDRXCfgAudAutoSound_t autoSound) { - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)NULL; - pDRXJData_t extAttr = (pDRXJData_t)NULL; - - u16_t rModus = 0; - u16_t wModus = 0; - - if ( autoSound == NULL ) - { - return DRX_STS_INVALID_ARG; - } + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) NULL; + pDRXJData_t extAttr = (pDRXJData_t) NULL; - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t)demod->myExtAttr; + u16_t rModus = 0; + u16_t wModus = 0; - /* power up */ - if ( extAttr->audData.audioIsActive == FALSE ) - { - CHK_ERROR ( PowerUpAud( demod , TRUE ) ); - extAttr->audData.audioIsActive = TRUE; - } + if (autoSound == NULL) { + return DRX_STS_INVALID_ARG; + } + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; - CHK_ERROR ( AUDGetModus ( demod, &rModus )); + /* power up */ + if (extAttr->audData.audioIsActive == FALSE) { + CHK_ERROR(PowerUpAud(demod, TRUE)); + extAttr->audData.audioIsActive = TRUE; + } - wModus = rModus; - /* clear ASS & ASC bits */ - wModus &= (u16_t)~AUD_DEM_WR_MODUS_MOD_ASS__M; - wModus &= (u16_t)~AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__M; + CHK_ERROR(AUDGetModus(demod, &rModus)); + + wModus = rModus; + /* clear ASS & ASC bits */ + wModus &= (u16_t) ~ AUD_DEM_WR_MODUS_MOD_ASS__M; + wModus &= (u16_t) ~ AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__M; + + switch (*autoSound) { + case DRX_AUD_AUTO_SOUND_OFF: + wModus |= AUD_DEM_WR_MODUS_MOD_ASS_OFF; + wModus |= AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_DISABLED; + break; + case DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON: + wModus |= AUD_DEM_WR_MODUS_MOD_ASS_ON; + wModus |= AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_ENABLED; + break; + case DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_OFF: + wModus |= AUD_DEM_WR_MODUS_MOD_ASS_ON; + wModus |= AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_DISABLED; + break; + default: + return DRX_STS_INVALID_ARG; + } - switch ( *autoSound ) - { - case DRX_AUD_AUTO_SOUND_OFF: - wModus |= AUD_DEM_WR_MODUS_MOD_ASS_OFF; - wModus |= AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_DISABLED; - break; - case DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON: - wModus |= AUD_DEM_WR_MODUS_MOD_ASS_ON; - wModus |= AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_ENABLED; - break; - case DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_OFF: - wModus |= AUD_DEM_WR_MODUS_MOD_ASS_ON; - wModus |= AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_DISABLED; - break; - default: - return DRX_STS_INVALID_ARG; - } - - if ( wModus != rModus ) - { - WR16( devAddr, AUD_DEM_WR_MODUS__A, wModus ); - } - /* copy to data structure */ - extAttr->audData.autoSound = *autoSound; + if (wModus != rModus) { + WR16(devAddr, AUD_DEM_WR_MODUS__A, wModus); + } + /* copy to data structure */ + extAttr->audData.autoSound = *autoSound; - return DRX_STS_OK; + return DRX_STS_OK; rw_error: - return DRX_STS_ERROR; + return DRX_STS_ERROR; } /*============================================================================*/ @@ -11192,43 +10716,39 @@ rw_error: * */ static DRXStatus_t -AUDCtrlGetCfgASSThres ( pDRXDemodInstance_t demod, - pDRXCfgAudASSThres_t thres ) +AUDCtrlGetCfgASSThres(pDRXDemodInstance_t demod, pDRXCfgAudASSThres_t thres) { - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)NULL; - pDRXJData_t extAttr = (pDRXJData_t)NULL; - - u16_t thresA2 = 0; - u16_t thresBtsc = 0; - u16_t thresNicam = 0; + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) NULL; + pDRXJData_t extAttr = (pDRXJData_t) NULL; - if ( thres == NULL ) - { - return DRX_STS_INVALID_ARG; - } + u16_t thresA2 = 0; + u16_t thresBtsc = 0; + u16_t thresNicam = 0; - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t)demod->myExtAttr; + if (thres == NULL) { + return DRX_STS_INVALID_ARG; + } - /* power up */ - if ( extAttr->audData.audioIsActive == FALSE ) - { - CHK_ERROR ( PowerUpAud( demod , TRUE ) ); - extAttr->audData.audioIsActive = TRUE; - } + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; - RR16( devAddr , AUD_DEM_RAM_A2_THRSHLD__A, &thresA2 ); - RR16( devAddr , AUD_DEM_RAM_BTSC_THRSHLD__A, &thresBtsc ); - RR16( devAddr , AUD_DEM_RAM_NICAM_THRSHLD__A, &thresNicam ); + /* power up */ + if (extAttr->audData.audioIsActive == FALSE) { + CHK_ERROR(PowerUpAud(demod, TRUE)); + extAttr->audData.audioIsActive = TRUE; + } - thres->a2 = thresA2; - thres->btsc = thresBtsc; - thres->nicam = thresNicam; + RR16(devAddr, AUD_DEM_RAM_A2_THRSHLD__A, &thresA2); + RR16(devAddr, AUD_DEM_RAM_BTSC_THRSHLD__A, &thresBtsc); + RR16(devAddr, AUD_DEM_RAM_NICAM_THRSHLD__A, &thresNicam); + thres->a2 = thresA2; + thres->btsc = thresBtsc; + thres->nicam = thresNicam; - return DRX_STS_OK; + return DRX_STS_OK; rw_error: - return DRX_STS_ERROR; + return DRX_STS_ERROR; } /*============================================================================*/ @@ -11240,37 +10760,34 @@ rw_error: * */ static DRXStatus_t -AUDCtrlSetCfgASSThres ( pDRXDemodInstance_t demod, - pDRXCfgAudASSThres_t thres ) +AUDCtrlSetCfgASSThres(pDRXDemodInstance_t demod, pDRXCfgAudASSThres_t thres) { - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)NULL; - pDRXJData_t extAttr = (pDRXJData_t)NULL; + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) NULL; + pDRXJData_t extAttr = (pDRXJData_t) NULL; - if ( thres == NULL ) - { - return DRX_STS_INVALID_ARG; - } + if (thres == NULL) { + return DRX_STS_INVALID_ARG; + } - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t)demod->myExtAttr; + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; - /* power up */ - if ( extAttr->audData.audioIsActive == FALSE ) - { - CHK_ERROR ( PowerUpAud( demod , TRUE ) ); - extAttr->audData.audioIsActive = TRUE; - } + /* power up */ + if (extAttr->audData.audioIsActive == FALSE) { + CHK_ERROR(PowerUpAud(demod, TRUE)); + extAttr->audData.audioIsActive = TRUE; + } - WR16( devAddr , AUD_DEM_WR_A2_THRSHLD__A, thres->a2 ); - WR16( devAddr , AUD_DEM_WR_BTSC_THRSHLD__A, thres->btsc ); - WR16( devAddr , AUD_DEM_WR_NICAM_THRSHLD__A, thres->nicam ); + WR16(devAddr, AUD_DEM_WR_A2_THRSHLD__A, thres->a2); + WR16(devAddr, AUD_DEM_WR_BTSC_THRSHLD__A, thres->btsc); + WR16(devAddr, AUD_DEM_WR_NICAM_THRSHLD__A, thres->nicam); - /* update DRXK data structure with hardware values */ - extAttr->audData.assThresholds = *thres; + /* update DRXK data structure with hardware values */ + extAttr->audData.assThresholds = *thres; - return DRX_STS_OK; + return DRX_STS_OK; rw_error: - return DRX_STS_ERROR; + return DRX_STS_ERROR; } /*============================================================================*/ @@ -11282,105 +10799,100 @@ rw_error: * */ static DRXStatus_t -AUDCtrlGetCfgCarrier ( pDRXDemodInstance_t demod, - pDRXCfgAudCarriers_t carriers ) +AUDCtrlGetCfgCarrier(pDRXDemodInstance_t demod, pDRXCfgAudCarriers_t carriers) { - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)NULL; - pDRXJData_t extAttr = (pDRXJData_t)NULL; + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) NULL; + pDRXJData_t extAttr = (pDRXJData_t) NULL; - u16_t wModus = 0; + u16_t wModus = 0; - u16_t dcoAHi = 0; - u16_t dcoALo = 0; - u16_t dcoBHi = 0; - u16_t dcoBLo = 0; + u16_t dcoAHi = 0; + u16_t dcoALo = 0; + u16_t dcoBHi = 0; + u16_t dcoBLo = 0; - u32_t valA = 0; - u32_t valB = 0; + u32_t valA = 0; + u32_t valB = 0; - u16_t dcLvlA = 0; - u16_t dcLvlB = 0; + u16_t dcLvlA = 0; + u16_t dcLvlB = 0; - u16_t cmThesA = 0; - u16_t cmThesB = 0; + u16_t cmThesA = 0; + u16_t cmThesB = 0; - if ( carriers == NULL ) - { - return DRX_STS_INVALID_ARG; - } + if (carriers == NULL) { + return DRX_STS_INVALID_ARG; + } - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t)demod->myExtAttr; + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; - /* power up */ - if ( extAttr->audData.audioIsActive == FALSE ) - { - CHK_ERROR ( PowerUpAud( demod , TRUE ) ); - extAttr->audData.audioIsActive = TRUE; - } + /* power up */ + if (extAttr->audData.audioIsActive == FALSE) { + CHK_ERROR(PowerUpAud(demod, TRUE)); + extAttr->audData.audioIsActive = TRUE; + } - CHK_ERROR ( AUDGetModus ( demod, &wModus )); + CHK_ERROR(AUDGetModus(demod, &wModus)); + + /* Behaviour of primary audio channel */ + switch (wModus & (AUD_DEM_WR_MODUS_MOD_CM_A__M)) { + case AUD_DEM_WR_MODUS_MOD_CM_A_MUTE: + carriers->a.opt = DRX_NO_CARRIER_MUTE; + break; + case AUD_DEM_WR_MODUS_MOD_CM_A_NOISE: + carriers->a.opt = DRX_NO_CARRIER_NOISE; + break; + default: + return DRX_STS_ERROR; + break; + } - /* Behaviour of primary audio channel */ - switch ( wModus & ( AUD_DEM_WR_MODUS_MOD_CM_A__M) ) - { - case AUD_DEM_WR_MODUS_MOD_CM_A_MUTE: - carriers->a.opt = DRX_NO_CARRIER_MUTE; - break; - case AUD_DEM_WR_MODUS_MOD_CM_A_NOISE: - carriers->a.opt = DRX_NO_CARRIER_NOISE; - break; - default: - return DRX_STS_ERROR; - break; - } - - /* Behaviour of secondary audio channel */ - switch ( wModus & ( AUD_DEM_WR_MODUS_MOD_CM_B__M) ) - { - case AUD_DEM_WR_MODUS_MOD_CM_B_MUTE: - carriers->b.opt = DRX_NO_CARRIER_MUTE; - break; - case AUD_DEM_WR_MODUS_MOD_CM_B_NOISE: - carriers->b.opt = DRX_NO_CARRIER_NOISE; - break; - default: - return DRX_STS_ERROR; - break; - } - - /* frequency adjustment for primary & secondary audio channel */ - RR16( devAddr, AUD_DEM_RAM_DCO_A_HI__A, &dcoAHi ); - RR16( devAddr, AUD_DEM_RAM_DCO_A_LO__A, &dcoALo ); - RR16( devAddr, AUD_DEM_RAM_DCO_B_HI__A, &dcoBHi ); - RR16( devAddr, AUD_DEM_RAM_DCO_B_LO__A, &dcoBLo ); - - valA = ( ( (u32_t) dcoAHi) << 12 ) | ( (u32_t) dcoALo & 0xFFF ); - valB = ( ( (u32_t) dcoBHi) << 12 ) | ( (u32_t) dcoBLo & 0xFFF ); - - /* Multiply by 20250 * 1>>24 ~= 2 / 1657 */ - carriers->a.dco = DRX_S24TODRXFREQ( valA ) * 2L / 1657L; - carriers->b.dco = DRX_S24TODRXFREQ( valB ) * 2L / 1657L; - - /* DC level of the incoming FM signal on the primary - & seconday sound channel */ - RR16( devAddr, AUD_DSP_RD_FM_DC_LEVEL_A__A, &dcLvlA ); - RR16( devAddr, AUD_DSP_RD_FM_DC_LEVEL_B__A, &dcLvlB ); - - /* offset (kHz) = (dcLvl / 322) */ - carriers->a.shift = ( DRX_U16TODRXFREQ( dcLvlA ) / 322L ); - carriers->b.shift = ( DRX_U16TODRXFREQ( dcLvlB ) / 322L ); - - /* Carrier detetcion threshold for primary & secondary channel */ - RR16( devAddr, AUD_DEM_RAM_CM_A_THRSHLD__A, &cmThesA); - RR16( devAddr, AUD_DEM_RAM_CM_B_THRSHLD__A, &cmThesB); - - carriers->a.thres = cmThesA; - carriers->b.thres = cmThesB; - - return DRX_STS_OK; + /* Behaviour of secondary audio channel */ + switch (wModus & (AUD_DEM_WR_MODUS_MOD_CM_B__M)) { + case AUD_DEM_WR_MODUS_MOD_CM_B_MUTE: + carriers->b.opt = DRX_NO_CARRIER_MUTE; + break; + case AUD_DEM_WR_MODUS_MOD_CM_B_NOISE: + carriers->b.opt = DRX_NO_CARRIER_NOISE; + break; + default: + return DRX_STS_ERROR; + break; + } + + /* frequency adjustment for primary & secondary audio channel */ + RR16(devAddr, AUD_DEM_RAM_DCO_A_HI__A, &dcoAHi); + RR16(devAddr, AUD_DEM_RAM_DCO_A_LO__A, &dcoALo); + RR16(devAddr, AUD_DEM_RAM_DCO_B_HI__A, &dcoBHi); + RR16(devAddr, AUD_DEM_RAM_DCO_B_LO__A, &dcoBLo); + + valA = (((u32_t) dcoAHi) << 12) | ((u32_t) dcoALo & 0xFFF); + valB = (((u32_t) dcoBHi) << 12) | ((u32_t) dcoBLo & 0xFFF); + + /* Multiply by 20250 * 1>>24 ~= 2 / 1657 */ + carriers->a.dco = DRX_S24TODRXFREQ(valA) * 2L / 1657L; + carriers->b.dco = DRX_S24TODRXFREQ(valB) * 2L / 1657L; + + /* DC level of the incoming FM signal on the primary + & seconday sound channel */ + RR16(devAddr, AUD_DSP_RD_FM_DC_LEVEL_A__A, &dcLvlA); + RR16(devAddr, AUD_DSP_RD_FM_DC_LEVEL_B__A, &dcLvlB); + + /* offset (kHz) = (dcLvl / 322) */ + carriers->a.shift = (DRX_U16TODRXFREQ(dcLvlA) / 322L); + carriers->b.shift = (DRX_U16TODRXFREQ(dcLvlB) / 322L); + + /* Carrier detetcion threshold for primary & secondary channel */ + RR16(devAddr, AUD_DEM_RAM_CM_A_THRSHLD__A, &cmThesA); + RR16(devAddr, AUD_DEM_RAM_CM_B_THRSHLD__A, &cmThesB); + + carriers->a.thres = cmThesA; + carriers->b.thres = cmThesB; + + return DRX_STS_OK; rw_error: - return DRX_STS_ERROR; + return DRX_STS_ERROR; } /*============================================================================*/ @@ -11392,103 +10904,95 @@ rw_error: * */ static DRXStatus_t -AUDCtrlSetCfgCarrier ( pDRXDemodInstance_t demod, - pDRXCfgAudCarriers_t carriers ) +AUDCtrlSetCfgCarrier(pDRXDemodInstance_t demod, pDRXCfgAudCarriers_t carriers) { - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)NULL; - pDRXJData_t extAttr = (pDRXJData_t)NULL; + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) NULL; + pDRXJData_t extAttr = (pDRXJData_t) NULL; - u16_t wModus = 0; - u16_t rModus = 0; + u16_t wModus = 0; + u16_t rModus = 0; - u16_t dcoAHi = 0; - u16_t dcoALo = 0; - u16_t dcoBHi = 0; - u16_t dcoBLo = 0; + u16_t dcoAHi = 0; + u16_t dcoALo = 0; + u16_t dcoBHi = 0; + u16_t dcoBLo = 0; - s32_t valA = 0; - s32_t valB = 0; + s32_t valA = 0; + s32_t valB = 0; - if ( carriers == NULL ) - { - return DRX_STS_INVALID_ARG; - } - - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t)demod->myExtAttr; + if (carriers == NULL) { + return DRX_STS_INVALID_ARG; + } - /* power up */ - if ( extAttr->audData.audioIsActive == FALSE ) - { - CHK_ERROR ( PowerUpAud( demod , TRUE ) ); - extAttr->audData.audioIsActive = TRUE; - } + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; + /* power up */ + if (extAttr->audData.audioIsActive == FALSE) { + CHK_ERROR(PowerUpAud(demod, TRUE)); + extAttr->audData.audioIsActive = TRUE; + } - CHK_ERROR ( AUDGetModus ( demod, &rModus )); + CHK_ERROR(AUDGetModus(demod, &rModus)); + + wModus = rModus; + wModus &= (u16_t) ~ AUD_DEM_WR_MODUS_MOD_CM_A__M; + /* Behaviour of primary audio channel */ + switch (carriers->a.opt) { + case DRX_NO_CARRIER_MUTE: + wModus |= AUD_DEM_WR_MODUS_MOD_CM_A_MUTE; + break; + case DRX_NO_CARRIER_NOISE: + wModus |= AUD_DEM_WR_MODUS_MOD_CM_A_NOISE; + break; + default: + return DRX_STS_INVALID_ARG; + break; + } + /* Behaviour of secondary audio channel */ + wModus &= (u16_t) ~ AUD_DEM_WR_MODUS_MOD_CM_B__M; + switch (carriers->b.opt) { + case DRX_NO_CARRIER_MUTE: + wModus |= AUD_DEM_WR_MODUS_MOD_CM_B_MUTE; + break; + case DRX_NO_CARRIER_NOISE: + wModus |= AUD_DEM_WR_MODUS_MOD_CM_B_NOISE; + break; + default: + return DRX_STS_INVALID_ARG; + break; + } - wModus = rModus; - wModus &= (u16_t)~AUD_DEM_WR_MODUS_MOD_CM_A__M; - /* Behaviour of primary audio channel */ - switch ( carriers->a.opt ) - { - case DRX_NO_CARRIER_MUTE: - wModus |= AUD_DEM_WR_MODUS_MOD_CM_A_MUTE; - break; - case DRX_NO_CARRIER_NOISE: - wModus |= AUD_DEM_WR_MODUS_MOD_CM_A_NOISE; - break; - default: - return DRX_STS_INVALID_ARG; - break; - } - - /* Behaviour of secondary audio channel */ - wModus &= (u16_t)~AUD_DEM_WR_MODUS_MOD_CM_B__M; - switch ( carriers->b.opt ) - { - case DRX_NO_CARRIER_MUTE: - wModus |= AUD_DEM_WR_MODUS_MOD_CM_B_MUTE; - break; - case DRX_NO_CARRIER_NOISE: - wModus |= AUD_DEM_WR_MODUS_MOD_CM_B_NOISE; - break; - default: - return DRX_STS_INVALID_ARG; - break; - } - - /* now update the modus register */ - if ( wModus != rModus) - { - WR16( devAddr, AUD_DEM_WR_MODUS__A, wModus ); - } + /* now update the modus register */ + if (wModus != rModus) { + WR16(devAddr, AUD_DEM_WR_MODUS__A, wModus); + } - /* frequency adjustment for primary & secondary audio channel */ - valA = (s32_t) ( ( carriers->a.dco ) * 1657L / 2); - valB = (s32_t) ( ( carriers->b.dco ) * 1657L / 2); + /* frequency adjustment for primary & secondary audio channel */ + valA = (s32_t) ((carriers->a.dco) * 1657L / 2); + valB = (s32_t) ((carriers->b.dco) * 1657L / 2); - dcoAHi = (u16_t) ( ( valA >> 12 ) & 0xFFF ); - dcoALo = (u16_t) ( valA & 0xFFF ); - dcoBHi = (u16_t) ( ( valB >> 12 ) & 0xFFF ); - dcoBLo = (u16_t) ( valB & 0xFFF ); + dcoAHi = (u16_t) ((valA >> 12) & 0xFFF); + dcoALo = (u16_t) (valA & 0xFFF); + dcoBHi = (u16_t) ((valB >> 12) & 0xFFF); + dcoBLo = (u16_t) (valB & 0xFFF); - WR16( devAddr, AUD_DEM_WR_DCO_A_HI__A, dcoAHi ); - WR16( devAddr, AUD_DEM_WR_DCO_A_LO__A, dcoALo ); - WR16( devAddr, AUD_DEM_WR_DCO_B_HI__A, dcoBHi ); - WR16( devAddr, AUD_DEM_WR_DCO_B_LO__A, dcoBLo ); + WR16(devAddr, AUD_DEM_WR_DCO_A_HI__A, dcoAHi); + WR16(devAddr, AUD_DEM_WR_DCO_A_LO__A, dcoALo); + WR16(devAddr, AUD_DEM_WR_DCO_B_HI__A, dcoBHi); + WR16(devAddr, AUD_DEM_WR_DCO_B_LO__A, dcoBLo); - /* Carrier detetcion threshold for primary & secondary channel */ - WR16( devAddr, AUD_DEM_WR_CM_A_THRSHLD__A, carriers->a.thres); - WR16( devAddr, AUD_DEM_WR_CM_B_THRSHLD__A, carriers->b.thres); + /* Carrier detetcion threshold for primary & secondary channel */ + WR16(devAddr, AUD_DEM_WR_CM_A_THRSHLD__A, carriers->a.thres); + WR16(devAddr, AUD_DEM_WR_CM_B_THRSHLD__A, carriers->b.thres); - /* update DRXK data structure */ - extAttr->audData.carriers = *carriers; + /* update DRXK data structure */ + extAttr->audData.carriers = *carriers; - return DRX_STS_OK; + return DRX_STS_OK; rw_error: - return DRX_STS_ERROR; + return DRX_STS_ERROR; } /*============================================================================*/ @@ -11500,96 +11004,90 @@ rw_error: * */ static DRXStatus_t -AUDCtrlGetCfgMixer ( pDRXDemodInstance_t demod, - pDRXCfgAudMixer_t mixer ) +AUDCtrlGetCfgMixer(pDRXDemodInstance_t demod, pDRXCfgAudMixer_t mixer) { - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)NULL; - pDRXJData_t extAttr = (pDRXJData_t)NULL; + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) NULL; + pDRXJData_t extAttr = (pDRXJData_t) NULL; - u16_t srcI2SMatr = 0; - u16_t fmMatr = 0; + u16_t srcI2SMatr = 0; + u16_t fmMatr = 0; - if ( mixer == NULL ) - { - return DRX_STS_INVALID_ARG; - } + if (mixer == NULL) { + return DRX_STS_INVALID_ARG; + } - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t)demod->myExtAttr; + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; - /* power up */ - if ( extAttr->audData.audioIsActive == FALSE ) - { - CHK_ERROR ( PowerUpAud( demod , TRUE ) ); - extAttr->audData.audioIsActive = TRUE; - } + /* power up */ + if (extAttr->audData.audioIsActive == FALSE) { + CHK_ERROR(PowerUpAud(demod, TRUE)); + extAttr->audData.audioIsActive = TRUE; + } + + /* Source Selctor */ + RR16(devAddr, AUD_DSP_WR_SRC_I2S_MATR__A, &srcI2SMatr); + + switch (srcI2SMatr & AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__M) { + case AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_MONO: + mixer->sourceI2S = DRX_AUD_SRC_MONO; + break; + case AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_AB: + mixer->sourceI2S = DRX_AUD_SRC_STEREO_OR_AB; + break; + case AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_A: + mixer->sourceI2S = DRX_AUD_SRC_STEREO_OR_A; + break; + case AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_B: + mixer->sourceI2S = DRX_AUD_SRC_STEREO_OR_B; + break; + default: + return DRX_STS_ERROR; + } - /* Source Selctor */ - RR16( devAddr, AUD_DSP_WR_SRC_I2S_MATR__A, &srcI2SMatr); + /* Matrix */ + switch (srcI2SMatr & AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__M) { + case AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_MONO: + mixer->matrixI2S = DRX_AUD_I2S_MATRIX_MONO; + break; + case AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_STEREO: + mixer->matrixI2S = DRX_AUD_I2S_MATRIX_STEREO; + break; + case AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_SOUND_A: + mixer->matrixI2S = DRX_AUD_I2S_MATRIX_A_MONO; + break; + case AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_SOUND_B: + mixer->matrixI2S = DRX_AUD_I2S_MATRIX_B_MONO; + break; + default: + return DRX_STS_ERROR; + } - switch ( srcI2SMatr & AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__M ) - { - case AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_MONO: - mixer->sourceI2S = DRX_AUD_SRC_MONO; - break; - case AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_AB: - mixer->sourceI2S = DRX_AUD_SRC_STEREO_OR_AB; - break; - case AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_A: - mixer->sourceI2S = DRX_AUD_SRC_STEREO_OR_A; - break; - case AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_B: - mixer->sourceI2S = DRX_AUD_SRC_STEREO_OR_B; - break; - default: - return DRX_STS_ERROR; - } - - /* Matrix */ - switch ( srcI2SMatr & AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__M ) - { - case AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_MONO: - mixer->matrixI2S = DRX_AUD_I2S_MATRIX_MONO; - break; - case AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_STEREO: - mixer->matrixI2S = DRX_AUD_I2S_MATRIX_STEREO; - break; - case AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_SOUND_A: - mixer->matrixI2S = DRX_AUD_I2S_MATRIX_A_MONO; - break; - case AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_SOUND_B: - mixer->matrixI2S = DRX_AUD_I2S_MATRIX_B_MONO; - break; - default: - return DRX_STS_ERROR; - } - - /* FM Matrix */ - RR16( devAddr, AUD_DEM_WR_FM_MATRIX__A, &fmMatr ); - switch ( fmMatr & AUD_DEM_WR_FM_MATRIX__M ) - { - case AUD_DEM_WR_FM_MATRIX_NO_MATRIX: - mixer->matrixFm = DRX_AUD_FM_MATRIX_NO_MATRIX; - break; - case AUD_DEM_WR_FM_MATRIX_GERMAN_MATRIX: - mixer->matrixFm = DRX_AUD_FM_MATRIX_GERMAN; - break; - case AUD_DEM_WR_FM_MATRIX_KOREAN_MATRIX: - mixer->matrixFm = DRX_AUD_FM_MATRIX_KOREAN; - break; - case AUD_DEM_WR_FM_MATRIX_SOUND_A: - mixer->matrixFm = DRX_AUD_FM_MATRIX_SOUND_A; - break; - case AUD_DEM_WR_FM_MATRIX_SOUND_B: - mixer->matrixFm = DRX_AUD_FM_MATRIX_SOUND_B; - break; - default: - return DRX_STS_ERROR; - } - - return DRX_STS_OK; + /* FM Matrix */ + RR16(devAddr, AUD_DEM_WR_FM_MATRIX__A, &fmMatr); + switch (fmMatr & AUD_DEM_WR_FM_MATRIX__M) { + case AUD_DEM_WR_FM_MATRIX_NO_MATRIX: + mixer->matrixFm = DRX_AUD_FM_MATRIX_NO_MATRIX; + break; + case AUD_DEM_WR_FM_MATRIX_GERMAN_MATRIX: + mixer->matrixFm = DRX_AUD_FM_MATRIX_GERMAN; + break; + case AUD_DEM_WR_FM_MATRIX_KOREAN_MATRIX: + mixer->matrixFm = DRX_AUD_FM_MATRIX_KOREAN; + break; + case AUD_DEM_WR_FM_MATRIX_SOUND_A: + mixer->matrixFm = DRX_AUD_FM_MATRIX_SOUND_A; + break; + case AUD_DEM_WR_FM_MATRIX_SOUND_B: + mixer->matrixFm = DRX_AUD_FM_MATRIX_SOUND_B; + break; + default: + return DRX_STS_ERROR; + } + + return DRX_STS_OK; rw_error: - return DRX_STS_ERROR; + return DRX_STS_ERROR; } /*============================================================================*/ @@ -11601,110 +11099,103 @@ rw_error: * */ static DRXStatus_t -AUDCtrlSetCfgMixer ( pDRXDemodInstance_t demod, - pDRXCfgAudMixer_t mixer ) - { - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)NULL; - pDRXJData_t extAttr = (pDRXJData_t)NULL; +AUDCtrlSetCfgMixer(pDRXDemodInstance_t demod, pDRXCfgAudMixer_t mixer) +{ + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) NULL; + pDRXJData_t extAttr = (pDRXJData_t) NULL; - u16_t srcI2SMatr = 0; - u16_t fmMatr = 0; + u16_t srcI2SMatr = 0; + u16_t fmMatr = 0; - if ( mixer == NULL ) - { - return DRX_STS_INVALID_ARG; - } + if (mixer == NULL) { + return DRX_STS_INVALID_ARG; + } - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t)demod->myExtAttr; + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; - /* power up */ - if ( extAttr->audData.audioIsActive == FALSE ) - { - CHK_ERROR ( PowerUpAud( demod , TRUE ) ); - extAttr->audData.audioIsActive = TRUE; - } + /* power up */ + if (extAttr->audData.audioIsActive == FALSE) { + CHK_ERROR(PowerUpAud(demod, TRUE)); + extAttr->audData.audioIsActive = TRUE; + } - /* Source Selctor */ - RR16( devAddr, AUD_DSP_WR_SRC_I2S_MATR__A, &srcI2SMatr); - srcI2SMatr &= (u16_t)~AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__M; + /* Source Selctor */ + RR16(devAddr, AUD_DSP_WR_SRC_I2S_MATR__A, &srcI2SMatr); + srcI2SMatr &= (u16_t) ~ AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__M; + + switch (mixer->sourceI2S) { + case DRX_AUD_SRC_MONO: + srcI2SMatr |= AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_MONO; + break; + case DRX_AUD_SRC_STEREO_OR_AB: + srcI2SMatr |= AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_AB; + break; + case DRX_AUD_SRC_STEREO_OR_A: + srcI2SMatr |= AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_A; + break; + case DRX_AUD_SRC_STEREO_OR_B: + srcI2SMatr |= AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_B; + break; + default: + return DRX_STS_INVALID_ARG; + } - switch (mixer->sourceI2S) - { - case DRX_AUD_SRC_MONO: - srcI2SMatr |= AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_MONO; - break; - case DRX_AUD_SRC_STEREO_OR_AB: - srcI2SMatr |= AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_AB; - break; - case DRX_AUD_SRC_STEREO_OR_A: - srcI2SMatr |= AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_A; - break; - case DRX_AUD_SRC_STEREO_OR_B: - srcI2SMatr |= AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_B; - break; - default: - return DRX_STS_INVALID_ARG; - } - - /* Matrix */ - srcI2SMatr &= (u16_t)~AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__M; - switch (mixer->matrixI2S) - { - case DRX_AUD_I2S_MATRIX_MONO: - srcI2SMatr |= AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_MONO; - break; - case DRX_AUD_I2S_MATRIX_STEREO: - srcI2SMatr |= AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_STEREO ; - break; - case DRX_AUD_I2S_MATRIX_A_MONO: - srcI2SMatr |= AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_SOUND_A; - break; - case DRX_AUD_I2S_MATRIX_B_MONO: - srcI2SMatr |= AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_SOUND_B; - break; - default: - return DRX_STS_INVALID_ARG; - } - /* write the result */ - WR16( devAddr, AUD_DSP_WR_SRC_I2S_MATR__A, srcI2SMatr); - - /* FM Matrix */ - RR16( devAddr, AUD_DEM_WR_FM_MATRIX__A, &fmMatr ); - fmMatr &= (u16_t)~AUD_DEM_WR_FM_MATRIX__M; - switch (mixer->matrixFm) - { - case DRX_AUD_FM_MATRIX_NO_MATRIX: - fmMatr |= AUD_DEM_WR_FM_MATRIX_NO_MATRIX; - break; - case DRX_AUD_FM_MATRIX_GERMAN: - fmMatr |= AUD_DEM_WR_FM_MATRIX_GERMAN_MATRIX; - break; - case DRX_AUD_FM_MATRIX_KOREAN: - fmMatr |= AUD_DEM_WR_FM_MATRIX_KOREAN_MATRIX; - break; - case DRX_AUD_FM_MATRIX_SOUND_A: - fmMatr |= AUD_DEM_WR_FM_MATRIX_SOUND_A; - break; - case DRX_AUD_FM_MATRIX_SOUND_B: - fmMatr |= AUD_DEM_WR_FM_MATRIX_SOUND_B; - break; - default: - return DRX_STS_INVALID_ARG; - } - - /* Only write if ASS is off */ - if ( extAttr->audData.autoSound == DRX_AUD_AUTO_SOUND_OFF ) - { - WR16( devAddr, AUD_DEM_WR_FM_MATRIX__A, fmMatr ); - } + /* Matrix */ + srcI2SMatr &= (u16_t) ~ AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__M; + switch (mixer->matrixI2S) { + case DRX_AUD_I2S_MATRIX_MONO: + srcI2SMatr |= AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_MONO; + break; + case DRX_AUD_I2S_MATRIX_STEREO: + srcI2SMatr |= AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_STEREO; + break; + case DRX_AUD_I2S_MATRIX_A_MONO: + srcI2SMatr |= AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_SOUND_A; + break; + case DRX_AUD_I2S_MATRIX_B_MONO: + srcI2SMatr |= AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_SOUND_B; + break; + default: + return DRX_STS_INVALID_ARG; + } + /* write the result */ + WR16(devAddr, AUD_DSP_WR_SRC_I2S_MATR__A, srcI2SMatr); + + /* FM Matrix */ + RR16(devAddr, AUD_DEM_WR_FM_MATRIX__A, &fmMatr); + fmMatr &= (u16_t) ~ AUD_DEM_WR_FM_MATRIX__M; + switch (mixer->matrixFm) { + case DRX_AUD_FM_MATRIX_NO_MATRIX: + fmMatr |= AUD_DEM_WR_FM_MATRIX_NO_MATRIX; + break; + case DRX_AUD_FM_MATRIX_GERMAN: + fmMatr |= AUD_DEM_WR_FM_MATRIX_GERMAN_MATRIX; + break; + case DRX_AUD_FM_MATRIX_KOREAN: + fmMatr |= AUD_DEM_WR_FM_MATRIX_KOREAN_MATRIX; + break; + case DRX_AUD_FM_MATRIX_SOUND_A: + fmMatr |= AUD_DEM_WR_FM_MATRIX_SOUND_A; + break; + case DRX_AUD_FM_MATRIX_SOUND_B: + fmMatr |= AUD_DEM_WR_FM_MATRIX_SOUND_B; + break; + default: + return DRX_STS_INVALID_ARG; + } + + /* Only write if ASS is off */ + if (extAttr->audData.autoSound == DRX_AUD_AUTO_SOUND_OFF) { + WR16(devAddr, AUD_DEM_WR_FM_MATRIX__A, fmMatr); + } - /* update the data structure with hardware state */ - extAttr->audData.mixer = *mixer; + /* update the data structure with hardware state */ + extAttr->audData.mixer = *mixer; - return DRX_STS_OK; + return DRX_STS_OK; rw_error: - return DRX_STS_ERROR; + return DRX_STS_ERROR; } /*============================================================================*/ @@ -11716,67 +11207,60 @@ rw_error: * */ static DRXStatus_t -AUDCtrlSetCfgAVSync ( pDRXDemodInstance_t demod, - pDRXCfgAudAVSync_t avSync ) +AUDCtrlSetCfgAVSync(pDRXDemodInstance_t demod, pDRXCfgAudAVSync_t avSync) { - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)NULL; - pDRXJData_t extAttr = (pDRXJData_t)NULL; + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) NULL; + pDRXJData_t extAttr = (pDRXJData_t) NULL; - u16_t wAudVidSync = 0; + u16_t wAudVidSync = 0; - if ( avSync == NULL ) - { - return DRX_STS_INVALID_ARG; - } + if (avSync == NULL) { + return DRX_STS_INVALID_ARG; + } - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t)demod->myExtAttr; + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; - /* power up */ - if ( extAttr->audData.audioIsActive == FALSE ) - { - CHK_ERROR ( PowerUpAud( demod , TRUE ) ); - extAttr->audData.audioIsActive = TRUE; - } + /* power up */ + if (extAttr->audData.audioIsActive == FALSE) { + CHK_ERROR(PowerUpAud(demod, TRUE)); + extAttr->audData.audioIsActive = TRUE; + } - /* audio/video synchronisation */ - RR16( devAddr, AUD_DSP_WR_AV_SYNC__A, &wAudVidSync ); + /* audio/video synchronisation */ + RR16(devAddr, AUD_DSP_WR_AV_SYNC__A, &wAudVidSync); - wAudVidSync &= (u16_t)~AUD_DSP_WR_AV_SYNC_AV_ON__M; + wAudVidSync &= (u16_t) ~ AUD_DSP_WR_AV_SYNC_AV_ON__M; - if ( *avSync == DRX_AUD_AVSYNC_OFF ) - { - wAudVidSync |= AUD_DSP_WR_AV_SYNC_AV_ON_DISABLE; - } - else - { - wAudVidSync |= AUD_DSP_WR_AV_SYNC_AV_ON_ENABLE; - } + if (*avSync == DRX_AUD_AVSYNC_OFF) { + wAudVidSync |= AUD_DSP_WR_AV_SYNC_AV_ON_DISABLE; + } else { + wAudVidSync |= AUD_DSP_WR_AV_SYNC_AV_ON_ENABLE; + } - wAudVidSync &= (u16_t)~AUD_DSP_WR_AV_SYNC_AV_STD_SEL__M; + wAudVidSync &= (u16_t) ~ AUD_DSP_WR_AV_SYNC_AV_STD_SEL__M; + + switch (*avSync) { + case DRX_AUD_AVSYNC_NTSC: + wAudVidSync |= AUD_DSP_WR_AV_SYNC_AV_STD_SEL_NTSC; + break; + case DRX_AUD_AVSYNC_MONOCHROME: + wAudVidSync |= AUD_DSP_WR_AV_SYNC_AV_STD_SEL_MONOCHROME; + break; + case DRX_AUD_AVSYNC_PAL_SECAM: + wAudVidSync |= AUD_DSP_WR_AV_SYNC_AV_STD_SEL_PAL_SECAM; + break; + case DRX_AUD_AVSYNC_OFF: + /* OK */ + break; + default: + return DRX_STS_INVALID_ARG; + } - switch ( *avSync ) - { - case DRX_AUD_AVSYNC_NTSC: - wAudVidSync |= AUD_DSP_WR_AV_SYNC_AV_STD_SEL_NTSC; - break; - case DRX_AUD_AVSYNC_MONOCHROME: - wAudVidSync |= AUD_DSP_WR_AV_SYNC_AV_STD_SEL_MONOCHROME; - break; - case DRX_AUD_AVSYNC_PAL_SECAM: - wAudVidSync |= AUD_DSP_WR_AV_SYNC_AV_STD_SEL_PAL_SECAM; - break; - case DRX_AUD_AVSYNC_OFF: - /* OK */ - break; - default: - return DRX_STS_INVALID_ARG; - } - - WR16( devAddr, AUD_DSP_WR_AV_SYNC__A, wAudVidSync ); - return DRX_STS_OK; + WR16(devAddr, AUD_DSP_WR_AV_SYNC__A, wAudVidSync); + return DRX_STS_OK; rw_error: - return DRX_STS_ERROR; + return DRX_STS_ERROR; } /*============================================================================*/ @@ -11788,57 +11272,52 @@ rw_error: * */ static DRXStatus_t -AUDCtrlGetCfgAVSync ( pDRXDemodInstance_t demod, - pDRXCfgAudAVSync_t avSync ) +AUDCtrlGetCfgAVSync(pDRXDemodInstance_t demod, pDRXCfgAudAVSync_t avSync) { - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)NULL; - pDRXJData_t extAttr = (pDRXJData_t)NULL; + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) NULL; + pDRXJData_t extAttr = (pDRXJData_t) NULL; - u16_t wAudVidSync = 0; + u16_t wAudVidSync = 0; - if ( avSync == NULL ) - { - return DRX_STS_INVALID_ARG; - } + if (avSync == NULL) { + return DRX_STS_INVALID_ARG; + } - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t)demod->myExtAttr; + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; - /* power up */ - if ( extAttr->audData.audioIsActive == FALSE ) - { - CHK_ERROR ( PowerUpAud( demod , TRUE ) ); - extAttr->audData.audioIsActive = TRUE; - } + /* power up */ + if (extAttr->audData.audioIsActive == FALSE) { + CHK_ERROR(PowerUpAud(demod, TRUE)); + extAttr->audData.audioIsActive = TRUE; + } - /* audio/video synchronisation */ - RR16( devAddr, AUD_DSP_WR_AV_SYNC__A, &wAudVidSync ); + /* audio/video synchronisation */ + RR16(devAddr, AUD_DSP_WR_AV_SYNC__A, &wAudVidSync); - if ( ( wAudVidSync & AUD_DSP_WR_AV_SYNC_AV_ON__M ) == - AUD_DSP_WR_AV_SYNC_AV_ON_DISABLE ) - { - *avSync = DRX_AUD_AVSYNC_OFF; - return DRX_STS_OK; - } + if ((wAudVidSync & AUD_DSP_WR_AV_SYNC_AV_ON__M) == + AUD_DSP_WR_AV_SYNC_AV_ON_DISABLE) { + *avSync = DRX_AUD_AVSYNC_OFF; + return DRX_STS_OK; + } - switch ( wAudVidSync & AUD_DSP_WR_AV_SYNC_AV_STD_SEL__M ) - { - case AUD_DSP_WR_AV_SYNC_AV_STD_SEL_NTSC: - *avSync = DRX_AUD_AVSYNC_NTSC; - break; - case AUD_DSP_WR_AV_SYNC_AV_STD_SEL_MONOCHROME: - *avSync = DRX_AUD_AVSYNC_MONOCHROME; - break; - case AUD_DSP_WR_AV_SYNC_AV_STD_SEL_PAL_SECAM: - *avSync = DRX_AUD_AVSYNC_PAL_SECAM; - break; - default: - return DRX_STS_ERROR; - } - - return DRX_STS_OK; + switch (wAudVidSync & AUD_DSP_WR_AV_SYNC_AV_STD_SEL__M) { + case AUD_DSP_WR_AV_SYNC_AV_STD_SEL_NTSC: + *avSync = DRX_AUD_AVSYNC_NTSC; + break; + case AUD_DSP_WR_AV_SYNC_AV_STD_SEL_MONOCHROME: + *avSync = DRX_AUD_AVSYNC_MONOCHROME; + break; + case AUD_DSP_WR_AV_SYNC_AV_STD_SEL_PAL_SECAM: + *avSync = DRX_AUD_AVSYNC_PAL_SECAM; + break; + default: + return DRX_STS_ERROR; + } + + return DRX_STS_OK; rw_error: - return DRX_STS_ERROR; + return DRX_STS_ERROR; } /*============================================================================*/ @@ -11850,40 +11329,36 @@ rw_error: * */ static DRXStatus_t -AUDCtrlGetCfgDev ( pDRXDemodInstance_t demod, - pDRXCfgAudDeviation_t dev ) +AUDCtrlGetCfgDev(pDRXDemodInstance_t demod, pDRXCfgAudDeviation_t dev) { - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)NULL; - pDRXJData_t extAttr = (pDRXJData_t)NULL; + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) NULL; + pDRXJData_t extAttr = (pDRXJData_t) NULL; - u16_t rModus = 0; + u16_t rModus = 0; + if (dev == NULL) { + return DRX_STS_INVALID_ARG; + } - if ( dev == NULL ) - { - return DRX_STS_INVALID_ARG; - } + extAttr = (pDRXJData_t) demod->myExtAttr; + devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t)demod->myExtAttr; - devAddr = demod->myI2CDevAddr; + CHK_ERROR(AUDGetModus(demod, &rModus)); - CHK_ERROR ( AUDGetModus ( demod, &rModus )); + switch (rModus & AUD_DEM_WR_MODUS_MOD_HDEV_A__M) { + case AUD_DEM_WR_MODUS_MOD_HDEV_A_NORMAL: + *dev = DRX_AUD_DEVIATION_NORMAL; + break; + case AUD_DEM_WR_MODUS_MOD_HDEV_A_HIGH_DEVIATION: + *dev = DRX_AUD_DEVIATION_HIGH; + break; + default: + return DRX_STS_ERROR; + } - switch ( rModus & AUD_DEM_WR_MODUS_MOD_HDEV_A__M) - { - case AUD_DEM_WR_MODUS_MOD_HDEV_A_NORMAL: - *dev = DRX_AUD_DEVIATION_NORMAL; - break; - case AUD_DEM_WR_MODUS_MOD_HDEV_A_HIGH_DEVIATION: - *dev = DRX_AUD_DEVIATION_HIGH; - break; - default: - return DRX_STS_ERROR; - } - - return DRX_STS_OK; + return DRX_STS_OK; rw_error: - return DRX_STS_ERROR; + return DRX_STS_ERROR; } /*============================================================================*/ @@ -11895,55 +11370,50 @@ rw_error: * */ static DRXStatus_t -AUDCtrlSetCfgDev ( pDRXDemodInstance_t demod, - pDRXCfgAudDeviation_t dev ) +AUDCtrlSetCfgDev(pDRXDemodInstance_t demod, pDRXCfgAudDeviation_t dev) { - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)NULL; - pDRXJData_t extAttr = (pDRXJData_t)NULL; + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) NULL; + pDRXJData_t extAttr = (pDRXJData_t) NULL; - u16_t wModus = 0; - u16_t rModus = 0; + u16_t wModus = 0; + u16_t rModus = 0; - if ( dev == NULL ) - { - return DRX_STS_INVALID_ARG; - } + if (dev == NULL) { + return DRX_STS_INVALID_ARG; + } - extAttr = (pDRXJData_t)demod->myExtAttr; - devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; + devAddr = demod->myI2CDevAddr; - CHK_ERROR ( AUDGetModus ( demod, &rModus )); + CHK_ERROR(AUDGetModus(demod, &rModus)); - wModus = rModus; + wModus = rModus; - wModus &= (u16_t)~AUD_DEM_WR_MODUS_MOD_HDEV_A__M; + wModus &= (u16_t) ~ AUD_DEM_WR_MODUS_MOD_HDEV_A__M; - switch ( *dev ) - { - case DRX_AUD_DEVIATION_NORMAL: - wModus |= AUD_DEM_WR_MODUS_MOD_HDEV_A_NORMAL; - break; - case DRX_AUD_DEVIATION_HIGH: - wModus |= AUD_DEM_WR_MODUS_MOD_HDEV_A_HIGH_DEVIATION; - break; - default: - return DRX_STS_INVALID_ARG; - } - - /* now update the modus register */ - if ( wModus != rModus) - { - WR16( devAddr, AUD_DEM_WR_MODUS__A, wModus ); - } - /* store in drxk data struct */ - extAttr->audData.deviation = *dev; + switch (*dev) { + case DRX_AUD_DEVIATION_NORMAL: + wModus |= AUD_DEM_WR_MODUS_MOD_HDEV_A_NORMAL; + break; + case DRX_AUD_DEVIATION_HIGH: + wModus |= AUD_DEM_WR_MODUS_MOD_HDEV_A_HIGH_DEVIATION; + break; + default: + return DRX_STS_INVALID_ARG; + } - return DRX_STS_OK; + /* now update the modus register */ + if (wModus != rModus) { + WR16(devAddr, AUD_DEM_WR_MODUS__A, wModus); + } + /* store in drxk data struct */ + extAttr->audData.deviation = *dev; + + return DRX_STS_OK; rw_error: - return DRX_STS_ERROR; + return DRX_STS_ERROR; } - /*============================================================================*/ /** * \brief Get Prescaler settings @@ -11953,84 +11423,72 @@ rw_error: * */ static DRXStatus_t -AUDCtrlGetCfgPrescale( pDRXDemodInstance_t demod, - pDRXCfgAudPrescale_t presc ) +AUDCtrlGetCfgPrescale(pDRXDemodInstance_t demod, pDRXCfgAudPrescale_t presc) { - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)NULL; - pDRXJData_t extAttr = (pDRXJData_t)NULL; - - u16_t rMaxFMDeviation = 0; - u16_t rNicamPrescaler = 0; - - if ( presc == NULL ) - { - return DRX_STS_INVALID_ARG; - } - - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t)demod->myExtAttr; - - /* power up */ - if ( extAttr->audData.audioIsActive == FALSE ) - { - CHK_ERROR ( PowerUpAud( demod , TRUE ) ); - extAttr->audData.audioIsActive = TRUE; - } + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) NULL; + pDRXJData_t extAttr = (pDRXJData_t) NULL; - /* read register data */ - RR16( devAddr, AUD_DSP_WR_NICAM_PRESC__A, &rNicamPrescaler ); - RR16( devAddr, AUD_DSP_WR_FM_PRESC__A, &rMaxFMDeviation ); + u16_t rMaxFMDeviation = 0; + u16_t rNicamPrescaler = 0; - /* calculate max FM deviation */ - rMaxFMDeviation >>= AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__B; - if ( rMaxFMDeviation > 0 ) - { - presc->fmDeviation = 3600UL + (rMaxFMDeviation >> 1); - presc->fmDeviation /= rMaxFMDeviation; - } - else - { - presc->fmDeviation = 380; /* kHz */ - } + if (presc == NULL) { + return DRX_STS_INVALID_ARG; + } - /* calculate NICAM gain from pre-scaler */ - /* - nicamGain = 20 * ( log10( preScaler / 16) ) - = ( 100log10( preScaler ) - 100log10( 16 ) ) / 5 + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; - because Log10Times100() cannot return negative numbers - = ( 100log10( 10 * preScaler ) - 100log10( 10 * 16) ) / 5 + /* power up */ + if (extAttr->audData.audioIsActive == FALSE) { + CHK_ERROR(PowerUpAud(demod, TRUE)); + extAttr->audData.audioIsActive = TRUE; + } + /* read register data */ + RR16(devAddr, AUD_DSP_WR_NICAM_PRESC__A, &rNicamPrescaler); + RR16(devAddr, AUD_DSP_WR_FM_PRESC__A, &rMaxFMDeviation); + + /* calculate max FM deviation */ + rMaxFMDeviation >>= AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__B; + if (rMaxFMDeviation > 0) { + presc->fmDeviation = 3600UL + (rMaxFMDeviation >> 1); + presc->fmDeviation /= rMaxFMDeviation; + } else { + presc->fmDeviation = 380; /* kHz */ + } - for 0.1dB resolution: + /* calculate NICAM gain from pre-scaler */ + /* + nicamGain = 20 * ( log10( preScaler / 16) ) + = ( 100log10( preScaler ) - 100log10( 16 ) ) / 5 - nicamGain = 200 * ( log10( preScaler / 16) ) - = 2 * ( 100log10( 10 * preScaler ) - 100log10( 10 * 16) ) - = ( 100log10( 10 * preScaler^2 ) - 100log10( 10 * 16^2 ) ) + because Log10Times100() cannot return negative numbers + = ( 100log10( 10 * preScaler ) - 100log10( 10 * 16) ) / 5 + for 0.1dB resolution: - */ - rNicamPrescaler >>= 8; - if ( rNicamPrescaler <= 1 ) - { - presc->nicamGain = -241; - } - else - { + nicamGain = 200 * ( log10( preScaler / 16) ) + = 2 * ( 100log10( 10 * preScaler ) - 100log10( 10 * 16) ) + = ( 100log10( 10 * preScaler^2 ) - 100log10( 10 * 16^2 ) ) - presc->nicamGain = (s16_t)( ( (s32_t) - ( Log10Times100( 10 * rNicamPrescaler * - rNicamPrescaler ) ) - - (s32_t) - ( Log10Times100( 10 * 16 * 16 ) ) ) ); - } + */ + rNicamPrescaler >>= 8; + if (rNicamPrescaler <= 1) { + presc->nicamGain = -241; + } else { + + presc->nicamGain = (s16_t) (((s32_t) + (Log10Times100 + (10 * rNicamPrescaler * + rNicamPrescaler)) - (s32_t) + (Log10Times100(10 * 16 * 16)))); + } - return DRX_STS_OK; + return DRX_STS_OK; rw_error: - return DRX_STS_ERROR; + return DRX_STS_ERROR; } - /*============================================================================*/ /** * \brief Set Prescaler settings @@ -12040,50 +11498,47 @@ rw_error: * */ static DRXStatus_t -AUDCtrlSetCfgPrescale( pDRXDemodInstance_t demod, - pDRXCfgAudPrescale_t presc ) +AUDCtrlSetCfgPrescale(pDRXDemodInstance_t demod, pDRXCfgAudPrescale_t presc) { - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)NULL; - pDRXJData_t extAttr = (pDRXJData_t)NULL; + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) NULL; + pDRXJData_t extAttr = (pDRXJData_t) NULL; - u16_t wMaxFMDeviation = 0; - u16_t nicamPrescaler; + u16_t wMaxFMDeviation = 0; + u16_t nicamPrescaler; - if ( presc == NULL ) - { - return DRX_STS_INVALID_ARG; - } + if (presc == NULL) { + return DRX_STS_INVALID_ARG; + } - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t)demod->myExtAttr; + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; - /* power up */ - if ( extAttr->audData.audioIsActive == FALSE ) - { - CHK_ERROR ( PowerUpAud( demod , TRUE ) ); - extAttr->audData.audioIsActive = TRUE; - } - - /* setting of max FM deviation */ - wMaxFMDeviation = (u16_t)(Frac (3600UL, presc->fmDeviation, 0)); - wMaxFMDeviation <<= AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__B; - if ( wMaxFMDeviation >= AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_28_KHZ_FM_DEVIATION ) - { - wMaxFMDeviation = AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_28_KHZ_FM_DEVIATION; - } + /* power up */ + if (extAttr->audData.audioIsActive == FALSE) { + CHK_ERROR(PowerUpAud(demod, TRUE)); + extAttr->audData.audioIsActive = TRUE; + } - /* NICAM Prescaler */ - if( ( presc->nicamGain >= -241) && ( presc->nicamGain <= 180) ) - { - /* calculation + /* setting of max FM deviation */ + wMaxFMDeviation = (u16_t) (Frac(3600UL, presc->fmDeviation, 0)); + wMaxFMDeviation <<= AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__B; + if (wMaxFMDeviation >= + AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_28_KHZ_FM_DEVIATION) { + wMaxFMDeviation = + AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_28_KHZ_FM_DEVIATION; + } - prescaler = 16 * 10^( GdB / 20 ) + /* NICAM Prescaler */ + if ((presc->nicamGain >= -241) && (presc->nicamGain <= 180)) { + /* calculation - minval of GdB = -20*log( 16 ) = -24.1dB + prescaler = 16 * 10^( GdB / 20 ) - negative numbers not allowed for dB2LinTimes100, so + minval of GdB = -20*log( 16 ) = -24.1dB - prescaler = 16 * 10^( GdB / 20 ) + negative numbers not allowed for dB2LinTimes100, so + + prescaler = 16 * 10^( GdB / 20 ) = 10^( (GdB / 20) + log10(16) ) = 10^( (GdB + 20log10(16)) / 20 ) @@ -12091,33 +11546,30 @@ AUDCtrlSetCfgPrescale( pDRXDemodInstance_t demod, = 10^( G0.1dB + 200log10(16)) / 200 ) - */ - nicamPrescaler = (u16_t) - ( ( dB2LinTimes100( presc->nicamGain + 241UL ) + 50UL ) / 100UL ); + */ + nicamPrescaler = (u16_t) + ((dB2LinTimes100(presc->nicamGain + 241UL) + 50UL) / 100UL); - /* clip result */ - if ( nicamPrescaler > 127 ) - { - nicamPrescaler = 127; - } + /* clip result */ + if (nicamPrescaler > 127) { + nicamPrescaler = 127; + } - /* shift before writing to register */ - nicamPrescaler <<= 8; - } - else - { - return(DRX_STS_INVALID_ARG); - } - /* end of setting NICAM Prescaler */ + /* shift before writing to register */ + nicamPrescaler <<= 8; + } else { + return (DRX_STS_INVALID_ARG); + } + /* end of setting NICAM Prescaler */ - WR16( devAddr, AUD_DSP_WR_NICAM_PRESC__A, nicamPrescaler ); - WR16( devAddr, AUD_DSP_WR_FM_PRESC__A, wMaxFMDeviation ); + WR16(devAddr, AUD_DSP_WR_NICAM_PRESC__A, nicamPrescaler); + WR16(devAddr, AUD_DSP_WR_FM_PRESC__A, wMaxFMDeviation); - extAttr->audData.prescale = *presc; + extAttr->audData.prescale = *presc; - return DRX_STS_OK; + return DRX_STS_OK; rw_error: - return DRX_STS_ERROR; + return DRX_STS_ERROR; } /*============================================================================*/ @@ -12128,64 +11580,54 @@ rw_error: * \return DRXStatus_t. * */ -static DRXStatus_t -AUDCtrlBeep ( pDRXDemodInstance_t demod, - pDRXAudBeep_t beep ) +static DRXStatus_t AUDCtrlBeep(pDRXDemodInstance_t demod, pDRXAudBeep_t beep) { - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)NULL; - pDRXJData_t extAttr = (pDRXJData_t)NULL; - - u16_t theBeep = 0; - u16_t volume = 0; - u32_t frequency = 0; - + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) NULL; + pDRXJData_t extAttr = (pDRXJData_t) NULL; - if ( beep == NULL ) - { - return DRX_STS_INVALID_ARG; - } + u16_t theBeep = 0; + u16_t volume = 0; + u32_t frequency = 0; - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t)demod->myExtAttr; + if (beep == NULL) { + return DRX_STS_INVALID_ARG; + } - /* power up */ - if ( extAttr->audData.audioIsActive == FALSE ) - { - CHK_ERROR ( PowerUpAud( demod , TRUE ) ); - extAttr->audData.audioIsActive = TRUE; - } + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; - if (( beep->volume > 0 ) || ( beep->volume < -127 )) - { - return DRX_STS_INVALID_ARG; - } + /* power up */ + if (extAttr->audData.audioIsActive == FALSE) { + CHK_ERROR(PowerUpAud(demod, TRUE)); + extAttr->audData.audioIsActive = TRUE; + } - if ( beep->frequency > 3000 ) - { - return DRX_STS_INVALID_ARG; - } + if ((beep->volume > 0) || (beep->volume < -127)) { + return DRX_STS_INVALID_ARG; + } - volume = (u16_t)beep->volume + 127; - theBeep |= volume << AUD_DSP_WR_BEEPER_BEEP_VOLUME__B; + if (beep->frequency > 3000) { + return DRX_STS_INVALID_ARG; + } + volume = (u16_t) beep->volume + 127; + theBeep |= volume << AUD_DSP_WR_BEEPER_BEEP_VOLUME__B; - frequency = ( (u32_t) beep->frequency ) * 23 / 500 ; - if ( frequency > AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__M ) - { - frequency = AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__M; - } - theBeep |= (u16_t) frequency; + frequency = ((u32_t) beep->frequency) * 23 / 500; + if (frequency > AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__M) { + frequency = AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__M; + } + theBeep |= (u16_t) frequency; - if ( beep->mute == TRUE ) - { - theBeep = 0; - } + if (beep->mute == TRUE) { + theBeep = 0; + } - WR16( devAddr, AUD_DSP_WR_BEEPER__A, theBeep); + WR16(devAddr, AUD_DSP_WR_BEEPER__A, theBeep); - return DRX_STS_OK; + return DRX_STS_OK; rw_error: - return DRX_STS_ERROR; + return DRX_STS_ERROR; } /*============================================================================*/ @@ -12197,202 +11639,173 @@ rw_error: * */ static DRXStatus_t -AUDCtrlSetStandard ( pDRXDemodInstance_t demod, - pDRXAudStandard_t standard ) +AUDCtrlSetStandard(pDRXDemodInstance_t demod, pDRXAudStandard_t standard) { - pI2CDeviceAddr_t devAddr = NULL; - pDRXJData_t extAttr = NULL; - DRXStandard_t currentStandard = DRX_STANDARD_UNKNOWN; - - u16_t wStandard = 0; - u16_t wModus = 0; - u16_t rModus = 0; - - Bool_t muteBuffer = FALSE; - s16_t volumeBuffer = 0; - u16_t wVolume = 0; - - if ( standard == NULL ) - { - return DRX_STS_INVALID_ARG; - } + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + DRXStandard_t currentStandard = DRX_STANDARD_UNKNOWN; - devAddr = (pI2CDeviceAddr_t)demod->myI2CDevAddr; - extAttr = (pDRXJData_t)demod->myExtAttr; - - /* power up */ - if ( extAttr->audData.audioIsActive == FALSE ) - { - CHK_ERROR ( PowerUpAud( demod , FALSE ) ); - extAttr->audData.audioIsActive = TRUE; - } - - - /* reset RDS data availability flag */ - extAttr->audData.rdsDataPresent = FALSE; + u16_t wStandard = 0; + u16_t wModus = 0; + u16_t rModus = 0; + Bool_t muteBuffer = FALSE; + s16_t volumeBuffer = 0; + u16_t wVolume = 0; - /* we need to mute from here to avoid noise during standard switching */ - muteBuffer = extAttr->audData.volume.mute; - volumeBuffer = extAttr->audData.volume.volume; - - extAttr->audData.volume.mute = TRUE; - /* restore data structure from DRX ExtAttr, call volume first to mute */ - CHK_ERROR ( AUDCtrlSetCfgVolume - ( demod, &extAttr->audData.volume ) ); - CHK_ERROR ( AUDCtrlSetCfgCarrier - ( demod, &extAttr->audData.carriers ) ); - CHK_ERROR ( AUDCtrlSetCfgASSThres - ( demod, &extAttr->audData.assThresholds ) ); - CHK_ERROR ( AUDCtrSetlCfgAutoSound - ( demod, &extAttr->audData.autoSound ) ); - CHK_ERROR ( AUDCtrlSetCfgMixer - ( demod, &extAttr->audData.mixer ) ); - CHK_ERROR ( AUDCtrlSetCfgAVSync - ( demod, &extAttr->audData.avSync ) ); - CHK_ERROR ( AUDCtrlSetCfgOutputI2S - ( demod, &extAttr->audData.i2sdata ) ); + if (standard == NULL) { + return DRX_STS_INVALID_ARG; + } - /* get prescaler from presets */ - CHK_ERROR ( AUDCtrlSetCfgPrescale - ( demod, &extAttr->audData.prescale) ); + devAddr = (pI2CDeviceAddr_t) demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; - CHK_ERROR ( AUDGetModus ( demod, &rModus )); + /* power up */ + if (extAttr->audData.audioIsActive == FALSE) { + CHK_ERROR(PowerUpAud(demod, FALSE)); + extAttr->audData.audioIsActive = TRUE; + } - wModus = rModus; + /* reset RDS data availability flag */ + extAttr->audData.rdsDataPresent = FALSE; + + /* we need to mute from here to avoid noise during standard switching */ + muteBuffer = extAttr->audData.volume.mute; + volumeBuffer = extAttr->audData.volume.volume; + + extAttr->audData.volume.mute = TRUE; + /* restore data structure from DRX ExtAttr, call volume first to mute */ + CHK_ERROR(AUDCtrlSetCfgVolume(demod, &extAttr->audData.volume)); + CHK_ERROR(AUDCtrlSetCfgCarrier(demod, &extAttr->audData.carriers)); + CHK_ERROR(AUDCtrlSetCfgASSThres + (demod, &extAttr->audData.assThresholds)); + CHK_ERROR(AUDCtrSetlCfgAutoSound(demod, &extAttr->audData.autoSound)); + CHK_ERROR(AUDCtrlSetCfgMixer(demod, &extAttr->audData.mixer)); + CHK_ERROR(AUDCtrlSetCfgAVSync(demod, &extAttr->audData.avSync)); + CHK_ERROR(AUDCtrlSetCfgOutputI2S(demod, &extAttr->audData.i2sdata)); + + /* get prescaler from presets */ + CHK_ERROR(AUDCtrlSetCfgPrescale(demod, &extAttr->audData.prescale)); + + CHK_ERROR(AUDGetModus(demod, &rModus)); + + wModus = rModus; + + switch (*standard) { + case DRX_AUD_STANDARD_AUTO: + wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_AUTO; + break; + case DRX_AUD_STANDARD_BTSC: + wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_BTSC_STEREO; + if (extAttr->audData.btscDetect == DRX_BTSC_MONO_AND_SAP) { + wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_BTSC_SAP; + } + break; + case DRX_AUD_STANDARD_A2: + wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_M_KOREA; + break; + case DRX_AUD_STANDARD_EIAJ: + wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_EIA_J; + break; + case DRX_AUD_STANDARD_FM_STEREO: + wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_FM_RADIO; + break; + case DRX_AUD_STANDARD_BG_FM: + wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_BG_FM; + break; + case DRX_AUD_STANDARD_D_K1: + wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K1; + break; + case DRX_AUD_STANDARD_D_K2: + wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K2; + break; + case DRX_AUD_STANDARD_D_K3: + wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K3; + break; + case DRX_AUD_STANDARD_BG_NICAM_FM: + wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_BG_NICAM_FM; + break; + case DRX_AUD_STANDARD_L_NICAM_AM: + wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_L_NICAM_AM; + break; + case DRX_AUD_STANDARD_I_NICAM_FM: + wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_I_NICAM_FM; + break; + case DRX_AUD_STANDARD_D_K_NICAM_FM: + wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K_NICAM_FM; + break; + case DRX_AUD_STANDARD_UNKNOWN: + wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_AUTO; + break; + default: + return DRX_STS_ERROR; + } - switch ( *standard ) - { - case DRX_AUD_STANDARD_AUTO: - wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_AUTO; - break; - case DRX_AUD_STANDARD_BTSC: - wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_BTSC_STEREO; - if (extAttr->audData.btscDetect == DRX_BTSC_MONO_AND_SAP) - { - wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_BTSC_SAP; - } - break; - case DRX_AUD_STANDARD_A2: - wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_M_KOREA; - break; - case DRX_AUD_STANDARD_EIAJ: - wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_EIA_J; - break; - case DRX_AUD_STANDARD_FM_STEREO: - wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_FM_RADIO; - break; - case DRX_AUD_STANDARD_BG_FM: - wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_BG_FM; - break; - case DRX_AUD_STANDARD_D_K1: - wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K1; - break; - case DRX_AUD_STANDARD_D_K2: - wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K2; - break; - case DRX_AUD_STANDARD_D_K3: - wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K3; - break; - case DRX_AUD_STANDARD_BG_NICAM_FM: - wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_BG_NICAM_FM; - break; - case DRX_AUD_STANDARD_L_NICAM_AM: - wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_L_NICAM_AM; - break; - case DRX_AUD_STANDARD_I_NICAM_FM: - wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_I_NICAM_FM; - break; - case DRX_AUD_STANDARD_D_K_NICAM_FM: - wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K_NICAM_FM; - break; - case DRX_AUD_STANDARD_UNKNOWN: - wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_AUTO; - break; - default: - return DRX_STS_ERROR; - } - - if ( *standard == DRX_AUD_STANDARD_AUTO ) - { - /* we need the current standard here */ - currentStandard = extAttr->standard; + if (*standard == DRX_AUD_STANDARD_AUTO) { + /* we need the current standard here */ + currentStandard = extAttr->standard; + wModus &= (u16_t) ~ AUD_DEM_WR_MODUS_MOD_6_5MHZ__M; - wModus &= (u16_t)~AUD_DEM_WR_MODUS_MOD_6_5MHZ__M; + if ((currentStandard == DRX_STANDARD_PAL_SECAM_L) || + (currentStandard == DRX_STANDARD_PAL_SECAM_LP)) { + wModus |= (AUD_DEM_WR_MODUS_MOD_6_5MHZ_SECAM); + } else { + wModus |= (AUD_DEM_WR_MODUS_MOD_6_5MHZ_D_K); + } - if ( ( currentStandard == DRX_STANDARD_PAL_SECAM_L ) || - ( currentStandard == DRX_STANDARD_PAL_SECAM_LP ) ) - { - wModus |= (AUD_DEM_WR_MODUS_MOD_6_5MHZ_SECAM); - } - else - { - wModus |= (AUD_DEM_WR_MODUS_MOD_6_5MHZ_D_K); - } + wModus &= (u16_t) ~ AUD_DEM_WR_MODUS_MOD_4_5MHZ__M; + if (currentStandard == DRX_STANDARD_NTSC) { + wModus |= (AUD_DEM_WR_MODUS_MOD_4_5MHZ_M_BTSC); - wModus &= (u16_t)~AUD_DEM_WR_MODUS_MOD_4_5MHZ__M; - if ( currentStandard == DRX_STANDARD_NTSC ) - { - wModus |= ( AUD_DEM_WR_MODUS_MOD_4_5MHZ_M_BTSC); + } else { /* non USA, ignore standard M to save time */ - } - else /* non USA, ignore standard M to save time */ - { - wModus |= ( AUD_DEM_WR_MODUS_MOD_4_5MHZ_CHROMA); - } + wModus |= (AUD_DEM_WR_MODUS_MOD_4_5MHZ_CHROMA); + } + } - } + wModus &= (u16_t) ~ AUD_DEM_WR_MODUS_MOD_FMRADIO__M; - wModus &= (u16_t)~AUD_DEM_WR_MODUS_MOD_FMRADIO__M; + /* just get hardcoded deemphasis and activate here */ + if (extAttr->audData.deemph == DRX_AUD_FM_DEEMPH_50US) { + wModus |= (AUD_DEM_WR_MODUS_MOD_FMRADIO_EU_50U); + } else { + wModus |= (AUD_DEM_WR_MODUS_MOD_FMRADIO_US_75U); + } - /* just get hardcoded deemphasis and activate here */ - if ( extAttr->audData.deemph == DRX_AUD_FM_DEEMPH_50US ) - { - wModus |= ( AUD_DEM_WR_MODUS_MOD_FMRADIO_EU_50U); - } - else - { - wModus |= ( AUD_DEM_WR_MODUS_MOD_FMRADIO_US_75U); - } + wModus &= (u16_t) ~ AUD_DEM_WR_MODUS_MOD_BTSC__M; + if (extAttr->audData.btscDetect == DRX_BTSC_STEREO) { + wModus |= (AUD_DEM_WR_MODUS_MOD_BTSC_BTSC_STEREO); + } else { /* DRX_BTSC_MONO_AND_SAP */ - wModus &= (u16_t)~AUD_DEM_WR_MODUS_MOD_BTSC__M; - if( extAttr->audData.btscDetect == DRX_BTSC_STEREO ) - { - wModus |= ( AUD_DEM_WR_MODUS_MOD_BTSC_BTSC_STEREO); - } - else /* DRX_BTSC_MONO_AND_SAP */ - { - wModus |= ( AUD_DEM_WR_MODUS_MOD_BTSC_BTSC_SAP); - } + wModus |= (AUD_DEM_WR_MODUS_MOD_BTSC_BTSC_SAP); + } - if ( wModus != rModus) - { - WR16( devAddr, AUD_DEM_WR_MODUS__A, wModus ); - } + if (wModus != rModus) { + WR16(devAddr, AUD_DEM_WR_MODUS__A, wModus); + } - WR16( devAddr, AUD_DEM_WR_STANDARD_SEL__A, wStandard ); + WR16(devAddr, AUD_DEM_WR_STANDARD_SEL__A, wStandard); /**************************************************************************/ - /* NOT calling AUDCtrlSetCfgVolume to avoid interfering standard */ - /* detection, need to keep things very minimal here, but keep audio */ - /* buffers intact */ + /* NOT calling AUDCtrlSetCfgVolume to avoid interfering standard */ + /* detection, need to keep things very minimal here, but keep audio */ + /* buffers intact */ /**************************************************************************/ - extAttr->audData.volume.mute = muteBuffer; - if ( extAttr->audData.volume.mute == FALSE ) - { - wVolume |= (u16_t) ( ( volumeBuffer + AUD_VOLUME_ZERO_DB ) << - AUD_DSP_WR_VOLUME_VOL_MAIN__B ); - WR16( devAddr, AUD_DSP_WR_VOLUME__A, wVolume ); - } + extAttr->audData.volume.mute = muteBuffer; + if (extAttr->audData.volume.mute == FALSE) { + wVolume |= (u16_t) ((volumeBuffer + AUD_VOLUME_ZERO_DB) << + AUD_DSP_WR_VOLUME_VOL_MAIN__B); + WR16(devAddr, AUD_DSP_WR_VOLUME__A, wVolume); + } - /* write standard selected */ - extAttr->audData.audioStandard = *standard; + /* write standard selected */ + extAttr->audData.audioStandard = *standard; - return DRX_STS_OK; + return DRX_STS_OK; rw_error: - return DRX_STS_ERROR; + return DRX_STS_ERROR; } /*============================================================================*/ @@ -12404,111 +11817,104 @@ rw_error: * */ static DRXStatus_t -AUDCtrlGetStandard ( pDRXDemodInstance_t demod, - pDRXAudStandard_t standard ) +AUDCtrlGetStandard(pDRXDemodInstance_t demod, pDRXAudStandard_t standard) { - pI2CDeviceAddr_t devAddr = NULL; - pDRXJData_t extAttr = NULL; + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; - u16_t rData = 0; + u16_t rData = 0; - if ( standard == NULL ) - { - return DRX_STS_INVALID_ARG; - } + if (standard == NULL) { + return DRX_STS_INVALID_ARG; + } - extAttr = (pDRXJData_t)demod->myExtAttr; - devAddr = (pI2CDeviceAddr_t)demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; + devAddr = (pI2CDeviceAddr_t) demod->myI2CDevAddr; - /* power up */ - if ( extAttr->audData.audioIsActive == FALSE ) - { - CHK_ERROR ( PowerUpAud( demod , TRUE ) ); - extAttr->audData.audioIsActive = TRUE; - } + /* power up */ + if (extAttr->audData.audioIsActive == FALSE) { + CHK_ERROR(PowerUpAud(demod, TRUE)); + extAttr->audData.audioIsActive = TRUE; + } - *standard = DRX_AUD_STANDARD_UNKNOWN; + *standard = DRX_AUD_STANDARD_UNKNOWN; - RR16( devAddr, AUD_DEM_RD_STANDARD_RES__A, &rData ); + RR16(devAddr, AUD_DEM_RD_STANDARD_RES__A, &rData); - /* return OK if the detection is not ready yet */ - if ( rData >= - AUD_DEM_RD_STANDARD_RES_STD_RESULT_DETECTION_STILL_ACTIVE ) - { - *standard = DRX_AUD_STANDARD_NOT_READY; - return DRX_STS_OK; - } + /* return OK if the detection is not ready yet */ + if (rData >= AUD_DEM_RD_STANDARD_RES_STD_RESULT_DETECTION_STILL_ACTIVE) { + *standard = DRX_AUD_STANDARD_NOT_READY; + return DRX_STS_OK; + } - /* detection done, return correct standard */ - switch ( rData ) - { - /* no standard detected */ - case AUD_DEM_RD_STANDARD_RES_STD_RESULT_NO_SOUND_STANDARD: - *standard = DRX_AUD_STANDARD_UNKNOWN; - break; - /* standard is KOREA(A2) */ - case AUD_DEM_RD_STANDARD_RES_STD_RESULT_NTSC_M_DUAL_CARRIER_FM: - *standard = DRX_AUD_STANDARD_A2; - break; - /* standard is EIA-J (Japan) */ - case AUD_DEM_RD_STANDARD_RES_STD_RESULT_NTSC_EIA_J: - *standard = DRX_AUD_STANDARD_EIAJ; - break; - /* standard is BTSC-stereo */ - case AUD_DEM_RD_STANDARD_RES_STD_RESULT_BTSC_STEREO: - *standard = DRX_AUD_STANDARD_BTSC; - break; - /* standard is BTSC-mono (SAP) */ - case AUD_DEM_RD_STANDARD_RES_STD_RESULT_BTSC_MONO_SAP: - *standard = DRX_AUD_STANDARD_BTSC; - break; - /* standard is FM radio */ - case AUD_DEM_RD_STANDARD_RES_STD_RESULT_FM_RADIO: - *standard = DRX_AUD_STANDARD_FM_STEREO; - break; - /* standard is BG FM */ - case AUD_DEM_RD_STANDARD_RES_STD_RESULT_B_G_DUAL_CARRIER_FM: - *standard = DRX_AUD_STANDARD_BG_FM; - break; - /* standard is DK-1 FM */ - case AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K1_DUAL_CARRIER_FM: - *standard = DRX_AUD_STANDARD_D_K1; - break; - /* standard is DK-2 FM */ - case AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K2_DUAL_CARRIER_FM: - *standard = DRX_AUD_STANDARD_D_K2; - break; - /* standard is DK-3 FM */ - case AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K3_DUAL_CARRIER_FM: - *standard = DRX_AUD_STANDARD_D_K3; - break; - /* standard is BG-NICAM FM */ - case AUD_DEM_RD_STANDARD_RES_STD_RESULT_B_G_NICAM_FM: - *standard = DRX_AUD_STANDARD_BG_NICAM_FM; - break; - /* standard is L-NICAM AM */ - case AUD_DEM_RD_STANDARD_RES_STD_RESULT_L_NICAM_AM: - *standard = DRX_AUD_STANDARD_L_NICAM_AM; - break; - /* standard is I-NICAM FM */ - case AUD_DEM_RD_STANDARD_RES_STD_RESULT_I_NICAM_FM: - *standard = DRX_AUD_STANDARD_I_NICAM_FM; - break; - /* standard is DK-NICAM FM */ - case AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K_NICAM_FM: - *standard = DRX_AUD_STANDARD_D_K_NICAM_FM; - break; - default: - *standard = DRX_AUD_STANDARD_UNKNOWN; - } - - return DRX_STS_OK; + /* detection done, return correct standard */ + switch (rData) { + /* no standard detected */ + case AUD_DEM_RD_STANDARD_RES_STD_RESULT_NO_SOUND_STANDARD: + *standard = DRX_AUD_STANDARD_UNKNOWN; + break; + /* standard is KOREA(A2) */ + case AUD_DEM_RD_STANDARD_RES_STD_RESULT_NTSC_M_DUAL_CARRIER_FM: + *standard = DRX_AUD_STANDARD_A2; + break; + /* standard is EIA-J (Japan) */ + case AUD_DEM_RD_STANDARD_RES_STD_RESULT_NTSC_EIA_J: + *standard = DRX_AUD_STANDARD_EIAJ; + break; + /* standard is BTSC-stereo */ + case AUD_DEM_RD_STANDARD_RES_STD_RESULT_BTSC_STEREO: + *standard = DRX_AUD_STANDARD_BTSC; + break; + /* standard is BTSC-mono (SAP) */ + case AUD_DEM_RD_STANDARD_RES_STD_RESULT_BTSC_MONO_SAP: + *standard = DRX_AUD_STANDARD_BTSC; + break; + /* standard is FM radio */ + case AUD_DEM_RD_STANDARD_RES_STD_RESULT_FM_RADIO: + *standard = DRX_AUD_STANDARD_FM_STEREO; + break; + /* standard is BG FM */ + case AUD_DEM_RD_STANDARD_RES_STD_RESULT_B_G_DUAL_CARRIER_FM: + *standard = DRX_AUD_STANDARD_BG_FM; + break; + /* standard is DK-1 FM */ + case AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K1_DUAL_CARRIER_FM: + *standard = DRX_AUD_STANDARD_D_K1; + break; + /* standard is DK-2 FM */ + case AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K2_DUAL_CARRIER_FM: + *standard = DRX_AUD_STANDARD_D_K2; + break; + /* standard is DK-3 FM */ + case AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K3_DUAL_CARRIER_FM: + *standard = DRX_AUD_STANDARD_D_K3; + break; + /* standard is BG-NICAM FM */ + case AUD_DEM_RD_STANDARD_RES_STD_RESULT_B_G_NICAM_FM: + *standard = DRX_AUD_STANDARD_BG_NICAM_FM; + break; + /* standard is L-NICAM AM */ + case AUD_DEM_RD_STANDARD_RES_STD_RESULT_L_NICAM_AM: + *standard = DRX_AUD_STANDARD_L_NICAM_AM; + break; + /* standard is I-NICAM FM */ + case AUD_DEM_RD_STANDARD_RES_STD_RESULT_I_NICAM_FM: + *standard = DRX_AUD_STANDARD_I_NICAM_FM; + break; + /* standard is DK-NICAM FM */ + case AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K_NICAM_FM: + *standard = DRX_AUD_STANDARD_D_K_NICAM_FM; + break; + default: + *standard = DRX_AUD_STANDARD_UNKNOWN; + } + + return DRX_STS_OK; rw_error: - return DRX_STS_ERROR; + return DRX_STS_ERROR; } - /*============================================================================*/ /** * \brief Retreive lock status in case of FM standard @@ -12518,27 +11924,24 @@ rw_error: * */ static DRXStatus_t -FmLockStatus( pDRXDemodInstance_t demod, - pDRXLockStatus_t lockStat ) +FmLockStatus(pDRXDemodInstance_t demod, pDRXLockStatus_t lockStat) { - DRXAudStatus_t status; + DRXAudStatus_t status; - /* Check detection of audio carriers */ - CHK_ERROR( AUDCtrlGetCarrierDetectStatus ( demod, &status ) ); + /* Check detection of audio carriers */ + CHK_ERROR(AUDCtrlGetCarrierDetectStatus(demod, &status)); - /* locked if either primary or secondary carrier is detected */ - if ( ( status.carrierA == TRUE ) || - ( status.carrierB == TRUE ) ) - { - *lockStat = DRX_LOCKED; - } else { - *lockStat = DRX_NOT_LOCKED; - } + /* locked if either primary or secondary carrier is detected */ + if ((status.carrierA == TRUE) || (status.carrierB == TRUE)) { + *lockStat = DRX_LOCKED; + } else { + *lockStat = DRX_NOT_LOCKED; + } - return (DRX_STS_OK); + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /*============================================================================*/ @@ -12553,28 +11956,25 @@ rw_error: * */ static DRXStatus_t -FmSigQuality( pDRXDemodInstance_t demod, - pDRXSigQuality_t sigQuality ) +FmSigQuality(pDRXDemodInstance_t demod, pDRXSigQuality_t sigQuality) { - DRXLockStatus_t lockStatus = DRX_NOT_LOCKED; + DRXLockStatus_t lockStatus = DRX_NOT_LOCKED; - CHK_ERROR( FmLockStatus( demod, &lockStatus ) ); - if ( lockStatus == DRX_LOCKED ) - { - sigQuality->indicator = 100; - } else { - sigQuality->indicator = 0; - } + CHK_ERROR(FmLockStatus(demod, &lockStatus)); + if (lockStatus == DRX_LOCKED) { + sigQuality->indicator = 100; + } else { + sigQuality->indicator = 0; + } - return (DRX_STS_OK); + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } #endif - /*===========================================================================*/ /*== END AUDIO DATAPATH FUNCTIONS ==*/ /*===========================================================================*/ @@ -12596,59 +11996,48 @@ rw_error: * */ static DRXStatus_t -GetOOBLockStatus( pDRXDemodInstance_t demod, - pI2CDeviceAddr_t devAddr, - pDRXLockStatus_t oobLock ) +GetOOBLockStatus(pDRXDemodInstance_t demod, + pI2CDeviceAddr_t devAddr, pDRXLockStatus_t oobLock) { - DRXJSCUCmd_t scuCmd; - u16_t cmdResult[2]; - u16_t OOBLockState; + DRXJSCUCmd_t scuCmd; + u16_t cmdResult[2]; + u16_t OOBLockState; - *oobLock = DRX_NOT_LOCKED; + *oobLock = DRX_NOT_LOCKED; - scuCmd.command = SCU_RAM_COMMAND_STANDARD_OOB | - SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK; - scuCmd.resultLen = 2; - scuCmd.result = cmdResult; - scuCmd.parameterLen = 0; + scuCmd.command = SCU_RAM_COMMAND_STANDARD_OOB | + SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK; + scuCmd.resultLen = 2; + scuCmd.result = cmdResult; + scuCmd.parameterLen = 0; - CHK_ERROR( SCUCommand( devAddr, &scuCmd ) ); + CHK_ERROR(SCUCommand(devAddr, &scuCmd)); - if ( scuCmd.result[1] < 0x4000 ) - { - /* 0x00 NOT LOCKED */ - *oobLock = DRX_NOT_LOCKED; - } - else if ( scuCmd.result[1] < 0x8000 ) - { - /* 0x40 DEMOD LOCKED */ - *oobLock = DRXJ_OOB_SYNC_LOCK; - } - else if ( scuCmd.result[1] < 0xC000 ) - { - /* 0x80 DEMOD + OOB LOCKED (system lock) */ - OOBLockState = scuCmd.result[1] & 0x00FF; - - if(OOBLockState & 0x0008) - { - *oobLock = DRXJ_OOB_SYNC_LOCK; - } - else if ((OOBLockState & 0x0002) && (OOBLockState & 0x0001)) - { - *oobLock = DRXJ_OOB_AGC_LOCK; - } - } - else - { - /* 0xC0 NEVER LOCKED (system will never be able to lock to the signal) */ - *oobLock = DRX_NEVER_LOCK; - } + if (scuCmd.result[1] < 0x4000) { + /* 0x00 NOT LOCKED */ + *oobLock = DRX_NOT_LOCKED; + } else if (scuCmd.result[1] < 0x8000) { + /* 0x40 DEMOD LOCKED */ + *oobLock = DRXJ_OOB_SYNC_LOCK; + } else if (scuCmd.result[1] < 0xC000) { + /* 0x80 DEMOD + OOB LOCKED (system lock) */ + OOBLockState = scuCmd.result[1] & 0x00FF; + + if (OOBLockState & 0x0008) { + *oobLock = DRXJ_OOB_SYNC_LOCK; + } else if ((OOBLockState & 0x0002) && (OOBLockState & 0x0001)) { + *oobLock = DRXJ_OOB_AGC_LOCK; + } + } else { + /* 0xC0 NEVER LOCKED (system will never be able to lock to the signal) */ + *oobLock = DRX_NEVER_LOCK; + } - /* *oobLock = scuCmd.result[1]; */ + /* *oobLock = scuCmd.result[1]; */ - return (DRX_STS_OK); + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /** @@ -12662,7 +12051,7 @@ rw_error: * */ static DRXStatus_t -GetOOBSymbolRateOffset( pI2CDeviceAddr_t devAddr, ps32_t SymbolRateOffset ) +GetOOBSymbolRateOffset(pI2CDeviceAddr_t devAddr, ps32_t SymbolRateOffset) { /* offset = -{(timingOffset/2^19)*(symbolRate/12,656250MHz)}*10^6 [ppm] */ /* offset = -{(timingOffset/2^19)*(symbolRate/12656250)}*10^6 [ppm] */ @@ -12675,63 +12064,61 @@ GetOOBSymbolRateOffset( pI2CDeviceAddr_t devAddr, ps32_t SymbolRateOffset ) /* trim 12656250/15625 = 810 */ /* offset = -{(timingOffset*(symbolRate * 2^-5))/(2^8*810)} [ppm] */ /* offset = -[(symbolRate * 2^-5)*(timingOffset)/(2^8)]/810 [ppm] */ - s32_t timingOffset = 0; - u32_t unsignedTimingOffset = 0; - s32_t divisionFactor = 810; - u16_t data = 0; - u32_t symbolRate = 0; - Bool_t negative = FALSE; - - *SymbolRateOffset = 0; - /* read data rate */ - SARR16( devAddr, SCU_RAM_ORX_RF_RX_DATA_RATE__A, &data ); - switch(data & SCU_RAM_ORX_RF_RX_DATA_RATE__M) - { - case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC: - case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC: - case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC_ALT: - case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC_ALT: - symbolRate = 1024000;/* bps */ - break; - case SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_REGSPEC: - case SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_INVSPEC: - symbolRate = 772000;/* bps */ - break; - case SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_REGSPEC: - case SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_INVSPEC: - symbolRate = 1544000;/* bps */ - break; - default: - return (DRX_STS_ERROR); - } - - RR16( devAddr, ORX_CON_CTI_DTI_R__A, &data ); - /* convert data to positive and keep information about sign */ - if((data & 0x8000) == 0x8000){ - if(data == 0x8000) - unsignedTimingOffset = 32768; - else - unsignedTimingOffset = 0x00007FFF & (u32_t)(-data); - negative = TRUE; - } - else - unsignedTimingOffset = (u32_t)data; - - symbolRate = symbolRate >> 5; - unsignedTimingOffset = ( unsignedTimingOffset * symbolRate ); - unsignedTimingOffset = Frac( unsignedTimingOffset, 256, FRAC_ROUND ); - unsignedTimingOffset = Frac( unsignedTimingOffset, - divisionFactor, FRAC_ROUND ); - if(negative) - timingOffset = (s32_t)unsignedTimingOffset; - else - timingOffset = -(s32_t)unsignedTimingOffset; - - *SymbolRateOffset = timingOffset; - - return (DRX_STS_OK); + s32_t timingOffset = 0; + u32_t unsignedTimingOffset = 0; + s32_t divisionFactor = 810; + u16_t data = 0; + u32_t symbolRate = 0; + Bool_t negative = FALSE; + + *SymbolRateOffset = 0; + /* read data rate */ + SARR16(devAddr, SCU_RAM_ORX_RF_RX_DATA_RATE__A, &data); + switch (data & SCU_RAM_ORX_RF_RX_DATA_RATE__M) { + case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC: + case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC: + case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC_ALT: + case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC_ALT: + symbolRate = 1024000; /* bps */ + break; + case SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_REGSPEC: + case SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_INVSPEC: + symbolRate = 772000; /* bps */ + break; + case SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_REGSPEC: + case SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_INVSPEC: + symbolRate = 1544000; /* bps */ + break; + default: + return (DRX_STS_ERROR); + } + + RR16(devAddr, ORX_CON_CTI_DTI_R__A, &data); + /* convert data to positive and keep information about sign */ + if ((data & 0x8000) == 0x8000) { + if (data == 0x8000) + unsignedTimingOffset = 32768; + else + unsignedTimingOffset = 0x00007FFF & (u32_t) (-data); + negative = TRUE; + } else + unsignedTimingOffset = (u32_t) data; + + symbolRate = symbolRate >> 5; + unsignedTimingOffset = (unsignedTimingOffset * symbolRate); + unsignedTimingOffset = Frac(unsignedTimingOffset, 256, FRAC_ROUND); + unsignedTimingOffset = Frac(unsignedTimingOffset, + divisionFactor, FRAC_ROUND); + if (negative) + timingOffset = (s32_t) unsignedTimingOffset; + else + timingOffset = -(s32_t) unsignedTimingOffset; + + *SymbolRateOffset = timingOffset; + + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /** @@ -12745,99 +12132,96 @@ rw_error: * */ static DRXStatus_t -GetOOBFreqOffset( pDRXDemodInstance_t demod, pDRXFrequency_t freqOffset ) +GetOOBFreqOffset(pDRXDemodInstance_t demod, pDRXFrequency_t freqOffset) { - u16_t data = 0; - u16_t rot = 0; - u16_t symbolRateReg = 0; - u32_t symbolRate = 0; - s32_t coarseFreqOffset = 0; - s32_t fineFreqOffset = 0; - s32_t fineSign = 1; - s32_t coarseSign = 1; - u32_t data64Hi = 0; - u32_t data64Lo = 0; - u32_t tempFreqOffset = 0; - pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t)(NULL); - pI2CDeviceAddr_t devAddr = NULL; - - /* check arguments */ - if ( ( demod == NULL ) || - ( freqOffset == NULL ) ) - { - return DRX_STS_INVALID_ARG; - } + u16_t data = 0; + u16_t rot = 0; + u16_t symbolRateReg = 0; + u32_t symbolRate = 0; + s32_t coarseFreqOffset = 0; + s32_t fineFreqOffset = 0; + s32_t fineSign = 1; + s32_t coarseSign = 1; + u32_t data64Hi = 0; + u32_t data64Lo = 0; + u32_t tempFreqOffset = 0; + pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); + pI2CDeviceAddr_t devAddr = NULL; + + /* check arguments */ + if ((demod == NULL) || (freqOffset == NULL)) { + return DRX_STS_INVALID_ARG; + } - devAddr = demod -> myI2CDevAddr; - commonAttr = (pDRXCommonAttr_t) demod -> myCommonAttr; + devAddr = demod->myI2CDevAddr; + commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; - *freqOffset = 0; + *freqOffset = 0; - /* read sign (spectrum inversion) */ - RR16( devAddr, ORX_FWP_IQM_FRQ_W__A, &rot ); + /* read sign (spectrum inversion) */ + RR16(devAddr, ORX_FWP_IQM_FRQ_W__A, &rot); - /* read frequency offset */ - SARR16( devAddr, SCU_RAM_ORX_FRQ_OFFSET__A, &data ); - /* find COARSE frequency offset */ - /* coarseFreqOffset = ( 25312500Hz*FRQ_OFFSET >> 21 ); */ - if (data & 0x8000) - { - data = (0xffff - data + 1); - coarseSign = -1; - } - Mult32 ( data, (commonAttr->sysClockFreq * 1000)/6, &data64Hi, &data64Lo ); - tempFreqOffset = (((data64Lo >> 21) & 0x7ff) | (data64Hi << 11)); - - /* get value in KHz */ - coarseFreqOffset = coarseSign * Frac( tempFreqOffset, 1000, FRAC_ROUND ); /* KHz */ - /* read data rate */ - SARR16( devAddr, SCU_RAM_ORX_RF_RX_DATA_RATE__A, &symbolRateReg ); - switch(symbolRateReg & SCU_RAM_ORX_RF_RX_DATA_RATE__M) - { - case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC: - case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC: - case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC_ALT: - case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC_ALT: - symbolRate = 1024000; - break; - case SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_REGSPEC: - case SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_INVSPEC: - symbolRate = 772000; - break; - case SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_REGSPEC: - case SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_INVSPEC: - symbolRate = 1544000; - break; - default: - return (DRX_STS_ERROR); - } - - /* find FINE frequency offset */ - /* fineFreqOffset = ( (CORRECTION_VALUE*symbolRate) >> 18 ); */ - RR16( devAddr, ORX_CON_CPH_FRQ_R__A, &data ); - /* at least 5 MSB are 0 so first divide with 2^5 without information loss*/ - fineFreqOffset = ( symbolRate >> 5 ); - if (data & 0x8000) - { - fineFreqOffset *= 0xffff - data + 1; /* Hz */ - fineSign = -1; - } else { - fineFreqOffset *= data; /* Hz */ - } - /* Left to divide with 8192 (2^13) */ - fineFreqOffset = Frac( fineFreqOffset, 8192, FRAC_ROUND ); - /* and to divide with 1000 to get KHz*/ - fineFreqOffset = fineSign * Frac( fineFreqOffset, 1000, FRAC_ROUND ); /* KHz */ - - if ( (rot & 0x8000) == 0x8000 ) - *freqOffset = -(coarseFreqOffset + fineFreqOffset); - else - *freqOffset = (coarseFreqOffset + fineFreqOffset); - - return (DRX_STS_OK); + /* read frequency offset */ + SARR16(devAddr, SCU_RAM_ORX_FRQ_OFFSET__A, &data); + /* find COARSE frequency offset */ + /* coarseFreqOffset = ( 25312500Hz*FRQ_OFFSET >> 21 ); */ + if (data & 0x8000) { + data = (0xffff - data + 1); + coarseSign = -1; + } + Mult32(data, (commonAttr->sysClockFreq * 1000) / 6, &data64Hi, + &data64Lo); + tempFreqOffset = (((data64Lo >> 21) & 0x7ff) | (data64Hi << 11)); + + /* get value in KHz */ + coarseFreqOffset = coarseSign * Frac(tempFreqOffset, 1000, FRAC_ROUND); /* KHz */ + /* read data rate */ + SARR16(devAddr, SCU_RAM_ORX_RF_RX_DATA_RATE__A, &symbolRateReg); + switch (symbolRateReg & SCU_RAM_ORX_RF_RX_DATA_RATE__M) { + case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC: + case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC: + case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC_ALT: + case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC_ALT: + symbolRate = 1024000; + break; + case SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_REGSPEC: + case SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_INVSPEC: + symbolRate = 772000; + break; + case SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_REGSPEC: + case SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_INVSPEC: + symbolRate = 1544000; + break; + default: + return (DRX_STS_ERROR); + } + + /* find FINE frequency offset */ + /* fineFreqOffset = ( (CORRECTION_VALUE*symbolRate) >> 18 ); */ + RR16(devAddr, ORX_CON_CPH_FRQ_R__A, &data); + /* at least 5 MSB are 0 so first divide with 2^5 without information loss */ + fineFreqOffset = (symbolRate >> 5); + if (data & 0x8000) { + fineFreqOffset *= 0xffff - data + 1; /* Hz */ + fineSign = -1; + } else { + fineFreqOffset *= data; /* Hz */ + } + /* Left to divide with 8192 (2^13) */ + fineFreqOffset = Frac(fineFreqOffset, 8192, FRAC_ROUND); + /* and to divide with 1000 to get KHz */ + fineFreqOffset = fineSign * Frac(fineFreqOffset, 1000, FRAC_ROUND); /* KHz */ + + if ((rot & 0x8000) == 0x8000) + *freqOffset = -(coarseFreqOffset + fineFreqOffset); + else + *freqOffset = (coarseFreqOffset + fineFreqOffset); + + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } + /** * \fn DRXStatus_t GetOOBFrequency () * \brief Get OOB frequency (Unit:KHz). @@ -12849,29 +12233,30 @@ rw_error: * */ static DRXStatus_t -GetOOBFrequency( pDRXDemodInstance_t demod, pDRXFrequency_t frequency ) +GetOOBFrequency(pDRXDemodInstance_t demod, pDRXFrequency_t frequency) { - u16_t data = 0; - DRXFrequency_t freqOffset = 0; - DRXFrequency_t freq = 0; - pI2CDeviceAddr_t devAddr = NULL; + u16_t data = 0; + DRXFrequency_t freqOffset = 0; + DRXFrequency_t freq = 0; + pI2CDeviceAddr_t devAddr = NULL; - devAddr = demod -> myI2CDevAddr; + devAddr = demod->myI2CDevAddr; - *frequency = 0;/* KHz */ + *frequency = 0; /* KHz */ - SARR16( devAddr, SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__A, &data ); + SARR16(devAddr, SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__A, &data); - freq = (DRXFrequency_t)((DRXFrequency_t)data * 50 + 50000L); + freq = (DRXFrequency_t) ((DRXFrequency_t) data * 50 + 50000L); - CHK_ERROR ( GetOOBFreqOffset ( demod, &freqOffset ) ); + CHK_ERROR(GetOOBFreqOffset(demod, &freqOffset)); - *frequency = freq + freqOffset; + *frequency = freq + freqOffset; - return (DRX_STS_OK); + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } + /** * \fn DRXStatus_t GetOOBMER () * \brief Get OOB MER. @@ -12882,139 +12267,137 @@ rw_error: * Gets OOB MER. Table for MER is in Programming guide. * */ -static DRXStatus_t -GetOOBMER( pI2CDeviceAddr_t devAddr, pu32_t mer ) +static DRXStatus_t GetOOBMER(pI2CDeviceAddr_t devAddr, pu32_t mer) { - u16_t data = 0; + u16_t data = 0; - *mer = 0; - /* READ MER */ - RR16( devAddr, ORX_EQU_MER_MER_R__A, &data ); - switch (data) - { - case 0:/* fall through */ - case 1: - *mer = 39; - break; - case 2: - *mer = 33; - break; - case 3: - *mer = 29; - break; - case 4: - *mer = 27; - break; - case 5: - *mer = 25; - break; - case 6: - *mer = 23; - break; - case 7: - *mer = 22; - break; - case 8: - *mer = 21; - break; - case 9: - *mer = 20; - break; - case 10: - *mer = 19; - break; - case 11: - *mer = 18; - break; - case 12: - *mer = 17; - break; - case 13:/* fall through */ - case 14: - *mer = 16; - break; - case 15:/* fall through */ - case 16: - *mer = 15; - break; - case 17:/* fall through */ - case 18: - *mer = 14; - break; - case 19:/* fall through */ - case 20: - *mer = 13; - break; - case 21:/* fall through */ - case 22: - *mer = 12; - break; - case 23:/* fall through */ - case 24:/* fall through */ - case 25: - *mer = 11; - break; - case 26:/* fall through */ - case 27:/* fall through */ - case 28: - *mer = 10; - break; - case 29:/* fall through */ - case 30:/* fall through */ - case 31:/* fall through */ - case 32: - *mer = 9; - break; - case 33:/* fall through */ - case 34:/* fall through */ - case 35:/* fall through */ - case 36: - *mer = 8; - break; - case 37:/* fall through */ - case 38:/* fall through */ - case 39:/* fall through */ - case 40: - *mer = 7; - break; - case 41:/* fall through */ - case 42:/* fall through */ - case 43:/* fall through */ - case 44:/* fall through */ - case 45: - *mer = 6; - break; - case 46:/* fall through */ - case 47:/* fall through */ - case 48:/* fall through */ - case 49:/* fall through */ - case 50:/* fall through */ - *mer = 5; - break; - case 51:/* fall through */ - case 52:/* fall through */ - case 53:/* fall through */ - case 54:/* fall through */ - case 55:/* fall through */ - case 56:/* fall through */ - case 57: - *mer = 4; - break; - case 58:/* fall through */ - case 59:/* fall through */ - case 60:/* fall through */ - case 61:/* fall through */ - case 62:/* fall through */ - case 63: - *mer = 0; - break; - default: - *mer = 0; - break; - } - return (DRX_STS_OK); + *mer = 0; + /* READ MER */ + RR16(devAddr, ORX_EQU_MER_MER_R__A, &data); + switch (data) { + case 0: /* fall through */ + case 1: + *mer = 39; + break; + case 2: + *mer = 33; + break; + case 3: + *mer = 29; + break; + case 4: + *mer = 27; + break; + case 5: + *mer = 25; + break; + case 6: + *mer = 23; + break; + case 7: + *mer = 22; + break; + case 8: + *mer = 21; + break; + case 9: + *mer = 20; + break; + case 10: + *mer = 19; + break; + case 11: + *mer = 18; + break; + case 12: + *mer = 17; + break; + case 13: /* fall through */ + case 14: + *mer = 16; + break; + case 15: /* fall through */ + case 16: + *mer = 15; + break; + case 17: /* fall through */ + case 18: + *mer = 14; + break; + case 19: /* fall through */ + case 20: + *mer = 13; + break; + case 21: /* fall through */ + case 22: + *mer = 12; + break; + case 23: /* fall through */ + case 24: /* fall through */ + case 25: + *mer = 11; + break; + case 26: /* fall through */ + case 27: /* fall through */ + case 28: + *mer = 10; + break; + case 29: /* fall through */ + case 30: /* fall through */ + case 31: /* fall through */ + case 32: + *mer = 9; + break; + case 33: /* fall through */ + case 34: /* fall through */ + case 35: /* fall through */ + case 36: + *mer = 8; + break; + case 37: /* fall through */ + case 38: /* fall through */ + case 39: /* fall through */ + case 40: + *mer = 7; + break; + case 41: /* fall through */ + case 42: /* fall through */ + case 43: /* fall through */ + case 44: /* fall through */ + case 45: + *mer = 6; + break; + case 46: /* fall through */ + case 47: /* fall through */ + case 48: /* fall through */ + case 49: /* fall through */ + case 50: /* fall through */ + *mer = 5; + break; + case 51: /* fall through */ + case 52: /* fall through */ + case 53: /* fall through */ + case 54: /* fall through */ + case 55: /* fall through */ + case 56: /* fall through */ + case 57: + *mer = 4; + break; + case 58: /* fall through */ + case 59: /* fall through */ + case 60: /* fall through */ + case 61: /* fall through */ + case 62: /* fall through */ + case 63: + *mer = 0; + break; + default: + *mer = 0; + break; + } + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } #endif /*#ifndef DRXJ_DIGITAL_ONLY */ @@ -13025,47 +12408,43 @@ rw_error: * \param active * \return DRXStatus_t. */ -static DRXStatus_t -SetOrxNsuAox ( pDRXDemodInstance_t demod, Bool_t active ) -{ - u16_t data = 0; - pI2CDeviceAddr_t devAddr = NULL; - pDRXJData_t extAttr = NULL; - - extAttr = (pDRXJData_t)demod->myExtAttr; - devAddr = demod -> myI2CDevAddr; +static DRXStatus_t SetOrxNsuAox(pDRXDemodInstance_t demod, Bool_t active) +{ + u16_t data = 0; + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + + extAttr = (pDRXJData_t) demod->myExtAttr; + devAddr = demod->myI2CDevAddr; + + /* Configure NSU_AOX */ + RR16(devAddr, ORX_NSU_AOX_STDBY_W__A, &data); + if (!active) { + data &= ((~ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON) + & (~ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON) + & (~ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON) + & (~ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON) + & (~ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON) + & (~ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON) + & (~ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON) + & (~ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON) + ); + } else { /* active */ + + data |= (ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON + | ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON + | ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON + | ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON + | ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON + | ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON + | ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON + | ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON); + } + WR16(devAddr, ORX_NSU_AOX_STDBY_W__A, data); - /* Configure NSU_AOX */ - RR16( devAddr, ORX_NSU_AOX_STDBY_W__A , &data ); - if( !active ) - { - data &= ((~ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON) - & (~ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON) - & (~ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON) - & (~ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON) - & (~ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON) - & (~ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON) - & (~ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON) - & (~ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON) - ); - } - else /* active */ - { - data |= (ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON - | ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON - | ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON - | ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON - | ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON - | ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON - | ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON - | ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON - ); - } - WR16( devAddr, ORX_NSU_AOX_STDBY_W__A , data ); - - return (DRX_STS_OK); + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /** @@ -13085,274 +12464,281 @@ rw_error: */ /* Nyquist filter impulse response */ -#define IMPULSE_COSINE_ALPHA_0_3 {-3,-4,-1, 6,10, 7,-5,-20,-25,-10,29,79,123,140} /*sqrt raised-cosine filter with alpha=0.3 */ -#define IMPULSE_COSINE_ALPHA_0_5 { 2, 0,-2,-2, 2, 5, 2,-10,-20,-14,20,74,125,145} /*sqrt raised-cosine filter with alpha=0.5 */ -#define IMPULSE_COSINE_ALPHA_RO_0_5 { 0, 0, 1, 2, 3, 0,-7,-15,-16, 0,34,77,114,128} /*full raised-cosine filter with alpha=0.5 (receiver only) */ +#define IMPULSE_COSINE_ALPHA_0_3 {-3,-4,-1, 6,10, 7,-5,-20,-25,-10,29,79,123,140} /*sqrt raised-cosine filter with alpha=0.3 */ +#define IMPULSE_COSINE_ALPHA_0_5 { 2, 0,-2,-2, 2, 5, 2,-10,-20,-14,20,74,125,145} /*sqrt raised-cosine filter with alpha=0.5 */ +#define IMPULSE_COSINE_ALPHA_RO_0_5 { 0, 0, 1, 2, 3, 0,-7,-15,-16, 0,34,77,114,128} /*full raised-cosine filter with alpha=0.5 (receiver only) */ /* Coefficients for the nyquist fitler (total: 27 taps) */ #define NYQFILTERLEN 27 -static DRXStatus_t -CtrlSetOOB( pDRXDemodInstance_t demod, pDRXOOB_t oobParam ) +static DRXStatus_t CtrlSetOOB(pDRXDemodInstance_t demod, pDRXOOB_t oobParam) { #ifndef DRXJ_DIGITAL_ONLY - DRXOOBDownstreamStandard_t standard = DRX_OOB_MODE_A; - DRXFrequency_t freq = 0; /* KHz */ - pI2CDeviceAddr_t devAddr = NULL; - pDRXJData_t extAttr = NULL; - u16_t i = 0; - Bool_t mirrorFreqSpectOOB = FALSE; - u16_t trkFilterValue = 0; - DRXJSCUCmd_t scuCmd; - u16_t setParamParameters[3]; - u16_t cmdResult[2] = {0, 0}; - s16_t NyquistCoeffs[4][(NYQFILTERLEN+1)/2] = - { - IMPULSE_COSINE_ALPHA_0_3, /* Target Mode 0 */ - IMPULSE_COSINE_ALPHA_0_3, /* Target Mode 1 */ - IMPULSE_COSINE_ALPHA_0_5, /* Target Mode 2 */ - IMPULSE_COSINE_ALPHA_RO_0_5 /* Target Mode 3 */ - }; - u8_t mode_val[4] = {2, 2, 0, 1}; - u8_t PFICoeffs[4][6] = - { - {DRXJ_16TO8(-92), DRXJ_16TO8(-108), DRXJ_16TO8(100) }, /* TARGET_MODE = 0: PFI_A = -23/32; PFI_B = -54/32; PFI_C = 25/32; fg = 0.5 MHz (Att=26dB) */ - {DRXJ_16TO8(-64), DRXJ_16TO8(-80), DRXJ_16TO8(80) }, /* TARGET_MODE = 1: PFI_A = -16/32; PFI_B = -40/32; PFI_C = 20/32; fg = 1.0 MHz (Att=28dB) */ - {DRXJ_16TO8(-80), DRXJ_16TO8(-98), DRXJ_16TO8(92) }, /* TARGET_MODE = 2, 3: PFI_A = -20/32; PFI_B = -49/32; PFI_C = 23/32; fg = 0.8 MHz (Att=25dB) */ - {DRXJ_16TO8(-80), DRXJ_16TO8(-98), DRXJ_16TO8(92) } /* TARGET_MODE = 2, 3: PFI_A = -20/32; PFI_B = -49/32; PFI_C = 23/32; fg = 0.8 MHz (Att=25dB) */ - }; - u16_t mode_index; - - devAddr = demod -> myI2CDevAddr; - extAttr = (pDRXJData_t)demod -> myExtAttr; - mirrorFreqSpectOOB = extAttr->mirrorFreqSpectOOB; - - /* Check parameters */ - if (oobParam == NULL) - { - /* power off oob module */ - scuCmd.command = SCU_RAM_COMMAND_STANDARD_OOB - | SCU_RAM_COMMAND_CMD_DEMOD_STOP; - scuCmd.parameterLen = 0; - scuCmd.resultLen = 1; - scuCmd.result = cmdResult; - CHK_ERROR( SCUCommand( devAddr, &scuCmd ) ); - CHK_ERROR( SetOrxNsuAox( demod, FALSE ) ); - WR16 ( devAddr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP); - - extAttr->oobPowerOn = FALSE; - return (DRX_STS_OK); - } - - standard = oobParam->standard; - - freq = oobParam->frequency; - if ((freq < 70000) || (freq > 130000)) - return (DRX_STS_ERROR); - freq = (freq - 50000) / 50; + DRXOOBDownstreamStandard_t standard = DRX_OOB_MODE_A; + DRXFrequency_t freq = 0; /* KHz */ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + u16_t i = 0; + Bool_t mirrorFreqSpectOOB = FALSE; + u16_t trkFilterValue = 0; + DRXJSCUCmd_t scuCmd; + u16_t setParamParameters[3]; + u16_t cmdResult[2] = { 0, 0 }; + s16_t NyquistCoeffs[4][(NYQFILTERLEN + 1) / 2] = { + IMPULSE_COSINE_ALPHA_0_3, /* Target Mode 0 */ + IMPULSE_COSINE_ALPHA_0_3, /* Target Mode 1 */ + IMPULSE_COSINE_ALPHA_0_5, /* Target Mode 2 */ + IMPULSE_COSINE_ALPHA_RO_0_5 /* Target Mode 3 */ + }; + u8_t mode_val[4] = { 2, 2, 0, 1 }; + u8_t PFICoeffs[4][6] = { + {DRXJ_16TO8(-92), DRXJ_16TO8(-108), DRXJ_16TO8(100)}, /* TARGET_MODE = 0: PFI_A = -23/32; PFI_B = -54/32; PFI_C = 25/32; fg = 0.5 MHz (Att=26dB) */ + {DRXJ_16TO8(-64), DRXJ_16TO8(-80), DRXJ_16TO8(80)}, /* TARGET_MODE = 1: PFI_A = -16/32; PFI_B = -40/32; PFI_C = 20/32; fg = 1.0 MHz (Att=28dB) */ + {DRXJ_16TO8(-80), DRXJ_16TO8(-98), DRXJ_16TO8(92)}, /* TARGET_MODE = 2, 3: PFI_A = -20/32; PFI_B = -49/32; PFI_C = 23/32; fg = 0.8 MHz (Att=25dB) */ + {DRXJ_16TO8(-80), DRXJ_16TO8(-98), DRXJ_16TO8(92)} /* TARGET_MODE = 2, 3: PFI_A = -20/32; PFI_B = -49/32; PFI_C = 23/32; fg = 0.8 MHz (Att=25dB) */ + }; + u16_t mode_index; + + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; + mirrorFreqSpectOOB = extAttr->mirrorFreqSpectOOB; + + /* Check parameters */ + if (oobParam == NULL) { + /* power off oob module */ + scuCmd.command = SCU_RAM_COMMAND_STANDARD_OOB + | SCU_RAM_COMMAND_CMD_DEMOD_STOP; + scuCmd.parameterLen = 0; + scuCmd.resultLen = 1; + scuCmd.result = cmdResult; + CHK_ERROR(SCUCommand(devAddr, &scuCmd)); + CHK_ERROR(SetOrxNsuAox(demod, FALSE)); + WR16(devAddr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP); + + extAttr->oobPowerOn = FALSE; + return (DRX_STS_OK); + } - { - u16_t index = 0; - u16_t remainder = 0; - pu16_t trkFiltercfg = extAttr->oobTrkFilterCfg; + standard = oobParam->standard; - index = (u16_t)((freq - 400) / 200); - remainder = (u16_t)((freq - 400) % 200); - trkFilterValue = trkFiltercfg[index] - (trkFiltercfg[index] - trkFiltercfg[index + 1])/10 - * remainder / 20; - } + freq = oobParam->frequency; + if ((freq < 70000) || (freq > 130000)) + return (DRX_STS_ERROR); + freq = (freq - 50000) / 50; + { + u16_t index = 0; + u16_t remainder = 0; + pu16_t trkFiltercfg = extAttr->oobTrkFilterCfg; + + index = (u16_t) ((freq - 400) / 200); + remainder = (u16_t) ((freq - 400) % 200); + trkFilterValue = + trkFiltercfg[index] - (trkFiltercfg[index] - + trkFiltercfg[index + + 1]) / 10 * remainder / + 20; + } /*********/ - /* Stop */ + /* Stop */ /*********/ - WR16 ( devAddr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP); - scuCmd.command = SCU_RAM_COMMAND_STANDARD_OOB - | SCU_RAM_COMMAND_CMD_DEMOD_STOP; - scuCmd.parameterLen = 0; - scuCmd.resultLen = 1; - scuCmd.result = cmdResult; - CHK_ERROR( SCUCommand( devAddr, &scuCmd ) ); + WR16(devAddr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP); + scuCmd.command = SCU_RAM_COMMAND_STANDARD_OOB + | SCU_RAM_COMMAND_CMD_DEMOD_STOP; + scuCmd.parameterLen = 0; + scuCmd.resultLen = 1; + scuCmd.result = cmdResult; + CHK_ERROR(SCUCommand(devAddr, &scuCmd)); /*********/ - /* Reset */ + /* Reset */ /*********/ - scuCmd.command = SCU_RAM_COMMAND_STANDARD_OOB - | SCU_RAM_COMMAND_CMD_DEMOD_RESET; - scuCmd.parameterLen = 0; - scuCmd.resultLen = 1; - scuCmd.result = cmdResult; - CHK_ERROR( SCUCommand( devAddr, &scuCmd ) ); + scuCmd.command = SCU_RAM_COMMAND_STANDARD_OOB + | SCU_RAM_COMMAND_CMD_DEMOD_RESET; + scuCmd.parameterLen = 0; + scuCmd.resultLen = 1; + scuCmd.result = cmdResult; + CHK_ERROR(SCUCommand(devAddr, &scuCmd)); /***********/ - /* SET_ENV */ + /* SET_ENV */ /***********/ - /* set frequency, spectrum inversion and data rate */ - scuCmd.command = SCU_RAM_COMMAND_STANDARD_OOB - | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV; - scuCmd.parameterLen = 3; - /* 1-data rate;2-frequency */ - switch ( oobParam->standard ) - { - case DRX_OOB_MODE_A: - if( - /* signal is transmitted inverted */ - ( (oobParam->spectrumInverted == TRUE) & - /* and tuner is not mirroring the signal */ - (mirrorFreqSpectOOB == FALSE) ) | - /* or */ - /* signal is transmitted noninverted */ - ( (oobParam->spectrumInverted == FALSE) & - /* and tuner is mirroring the signal */ - (mirrorFreqSpectOOB == TRUE) ) - ) - setParamParameters[0] = SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC; - else - setParamParameters[0] = SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC; - break; - case DRX_OOB_MODE_B_GRADE_A: - if( - /* signal is transmitted inverted */ - ( (oobParam->spectrumInverted == TRUE) & - /* and tuner is not mirroring the signal */ - (mirrorFreqSpectOOB == FALSE) ) | - /* or */ - /* signal is transmitted noninverted */ - ( (oobParam->spectrumInverted == FALSE) & - /* and tuner is mirroring the signal */ - (mirrorFreqSpectOOB == TRUE) ) - ) - setParamParameters[0] = SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_INVSPEC; - else - setParamParameters[0] = SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_REGSPEC; - break; - case DRX_OOB_MODE_B_GRADE_B: - default: - if( - /* signal is transmitted inverted */ - ( (oobParam->spectrumInverted == TRUE) & - /* and tuner is not mirroring the signal */ - (mirrorFreqSpectOOB == FALSE) ) | - /* or */ - /* signal is transmitted noninverted */ - ( (oobParam->spectrumInverted == FALSE) & - /* and tuner is mirroring the signal */ - (mirrorFreqSpectOOB == TRUE) ) - ) - setParamParameters[0] = SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_INVSPEC; - else - setParamParameters[0] = SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_REGSPEC; - break; - } - setParamParameters[1] = ( u16_t )( freq & 0xFFFF ); - setParamParameters[2] = trkFilterValue; - scuCmd.parameter = setParamParameters; - scuCmd.resultLen = 1; - scuCmd.result = cmdResult; - mode_index = mode_val[(setParamParameters[0] & 0xC0) >> 6]; - CHK_ERROR( SCUCommand( devAddr, &scuCmd ) ); - - WR16 ( devAddr, SIO_TOP_COMM_KEY__A, 0xFABA); /* Write magic word to enable pdr reg write */ - WR16 ( devAddr, SIO_PDR_OOB_CRX_CFG__A, - OOB_CRX_DRIVE_STRENGTH << SIO_PDR_OOB_CRX_CFG_DRIVE__B - | 0x03 << SIO_PDR_OOB_CRX_CFG_MODE__B ); - WR16 ( devAddr, SIO_PDR_OOB_DRX_CFG__A, - OOB_DRX_DRIVE_STRENGTH << SIO_PDR_OOB_DRX_CFG_DRIVE__B - | 0x03 << SIO_PDR_OOB_DRX_CFG_MODE__B ); - WR16 ( devAddr, SIO_TOP_COMM_KEY__A, 0x0000); /* Write magic word to disable pdr reg write */ - - WR16 ( devAddr, ORX_TOP_COMM_KEY__A, 0); - WR16 ( devAddr, ORX_FWP_AAG_LEN_W__A, 16000); - WR16 ( devAddr, ORX_FWP_AAG_THR_W__A, 40); - - /* ddc */ - WR16( devAddr, ORX_DDC_OFO_SET_W__A, ORX_DDC_OFO_SET_W__PRE); - - /* nsu */ - WR16( devAddr, ORX_NSU_AOX_LOPOW_W__A, extAttr->oobLoPow); - - /* initialization for target mode */ - WR16( devAddr, SCU_RAM_ORX_TARGET_MODE__A, SCU_RAM_ORX_TARGET_MODE_2048KBPS_SQRT); - WR16( devAddr, SCU_RAM_ORX_FREQ_GAIN_CORR__A, SCU_RAM_ORX_FREQ_GAIN_CORR_2048KBPS); - - /* Reset bits for timing and freq. recovery */ - WR16( devAddr, SCU_RAM_ORX_RST_CPH__A, 0x0001); - WR16( devAddr, SCU_RAM_ORX_RST_CTI__A, 0x0002); - WR16( devAddr, SCU_RAM_ORX_RST_KRN__A, 0x0004); - WR16( devAddr, SCU_RAM_ORX_RST_KRP__A, 0x0008); - - /* AGN_LOCK = {2048>>3, -2048, 8, -8, 0, 1}; */ - WR16( devAddr, SCU_RAM_ORX_AGN_LOCK_TH__A, 2048>>3); - WR16( devAddr, SCU_RAM_ORX_AGN_LOCK_TOTH__A, (u16_t) (-2048)); - WR16( devAddr, SCU_RAM_ORX_AGN_ONLOCK_TTH__A, 8); - WR16( devAddr, SCU_RAM_ORX_AGN_UNLOCK_TTH__A, (u16_t)(-8)); - WR16( devAddr, SCU_RAM_ORX_AGN_LOCK_MASK__A, 1); - - /* DGN_LOCK = {10, -2048, 8, -8, 0, 1<<1}; */ - WR16( devAddr, SCU_RAM_ORX_DGN_LOCK_TH__A, 10); - WR16( devAddr, SCU_RAM_ORX_DGN_LOCK_TOTH__A, (u16_t)(-2048)); - WR16( devAddr, SCU_RAM_ORX_DGN_ONLOCK_TTH__A, 8); - WR16( devAddr, SCU_RAM_ORX_DGN_UNLOCK_TTH__A, (u16_t)(-8)); - WR16( devAddr, SCU_RAM_ORX_DGN_LOCK_MASK__A, 1<<1); - - /* FRQ_LOCK = {15,-2048, 8, -8, 0, 1<<2}; */ - WR16( devAddr, SCU_RAM_ORX_FRQ_LOCK_TH__A, 17); - WR16( devAddr, SCU_RAM_ORX_FRQ_LOCK_TOTH__A, (u16_t)(-2048)); - WR16( devAddr, SCU_RAM_ORX_FRQ_ONLOCK_TTH__A, 8); - WR16( devAddr, SCU_RAM_ORX_FRQ_UNLOCK_TTH__A, (u16_t)(-8)); - WR16( devAddr, SCU_RAM_ORX_FRQ_LOCK_MASK__A, 1<<2); - - /* PHA_LOCK = {5000, -2048, 8, -8, 0, 1<<3}; */ - WR16( devAddr, SCU_RAM_ORX_PHA_LOCK_TH__A, 3000); - WR16( devAddr, SCU_RAM_ORX_PHA_LOCK_TOTH__A, (u16_t)(-2048)); - WR16( devAddr, SCU_RAM_ORX_PHA_ONLOCK_TTH__A, 8); - WR16( devAddr, SCU_RAM_ORX_PHA_UNLOCK_TTH__A, (u16_t)(-8)); - WR16( devAddr, SCU_RAM_ORX_PHA_LOCK_MASK__A, 1<<3); - - /* TIM_LOCK = {300, -2048, 8, -8, 0, 1<<4}; */ - WR16( devAddr, SCU_RAM_ORX_TIM_LOCK_TH__A, 400); - WR16( devAddr, SCU_RAM_ORX_TIM_LOCK_TOTH__A, (u16_t)(-2048)); - WR16( devAddr, SCU_RAM_ORX_TIM_ONLOCK_TTH__A, 8); - WR16( devAddr, SCU_RAM_ORX_TIM_UNLOCK_TTH__A, (u16_t)(-8)); - WR16( devAddr, SCU_RAM_ORX_TIM_LOCK_MASK__A, 1<<4); - - /* EQU_LOCK = {20, -2048, 8, -8, 0, 1<<5}; */ - WR16( devAddr, SCU_RAM_ORX_EQU_LOCK_TH__A, 20); - WR16( devAddr, SCU_RAM_ORX_EQU_LOCK_TOTH__A, (u16_t)(-2048)); - WR16( devAddr, SCU_RAM_ORX_EQU_ONLOCK_TTH__A, 4); - WR16( devAddr, SCU_RAM_ORX_EQU_UNLOCK_TTH__A, (u16_t)(-4)); - WR16( devAddr, SCU_RAM_ORX_EQU_LOCK_MASK__A, 1<<5); - - /* PRE-Filter coefficients (PFI) */ - WRB( devAddr, ORX_FWP_PFI_A_W__A, sizeof(PFICoeffs[mode_index]), ((pu8_t)PFICoeffs[mode_index])); - WR16( devAddr, ORX_TOP_MDE_W__A, mode_index); - - /* NYQUIST-Filter coefficients (NYQ) */ - for (i = 0; i < (NYQFILTERLEN + 1) / 2; i++) - { - WR16( devAddr, ORX_FWP_NYQ_ADR_W__A, i); - WR16( devAddr, ORX_FWP_NYQ_COF_RW__A, NyquistCoeffs[mode_index][i]); - } - WR16( devAddr, ORX_FWP_NYQ_ADR_W__A, 31); - WR16 ( devAddr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_ACTIVE); + /* set frequency, spectrum inversion and data rate */ + scuCmd.command = SCU_RAM_COMMAND_STANDARD_OOB + | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV; + scuCmd.parameterLen = 3; + /* 1-data rate;2-frequency */ + switch (oobParam->standard) { + case DRX_OOB_MODE_A: + if ( + /* signal is transmitted inverted */ + ((oobParam->spectrumInverted == TRUE) & + /* and tuner is not mirroring the signal */ + (mirrorFreqSpectOOB == FALSE)) | + /* or */ + /* signal is transmitted noninverted */ + ((oobParam->spectrumInverted == FALSE) & + /* and tuner is mirroring the signal */ + (mirrorFreqSpectOOB == TRUE)) + ) + setParamParameters[0] = + SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC; + else + setParamParameters[0] = + SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC; + break; + case DRX_OOB_MODE_B_GRADE_A: + if ( + /* signal is transmitted inverted */ + ((oobParam->spectrumInverted == TRUE) & + /* and tuner is not mirroring the signal */ + (mirrorFreqSpectOOB == FALSE)) | + /* or */ + /* signal is transmitted noninverted */ + ((oobParam->spectrumInverted == FALSE) & + /* and tuner is mirroring the signal */ + (mirrorFreqSpectOOB == TRUE)) + ) + setParamParameters[0] = + SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_INVSPEC; + else + setParamParameters[0] = + SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_REGSPEC; + break; + case DRX_OOB_MODE_B_GRADE_B: + default: + if ( + /* signal is transmitted inverted */ + ((oobParam->spectrumInverted == TRUE) & + /* and tuner is not mirroring the signal */ + (mirrorFreqSpectOOB == FALSE)) | + /* or */ + /* signal is transmitted noninverted */ + ((oobParam->spectrumInverted == FALSE) & + /* and tuner is mirroring the signal */ + (mirrorFreqSpectOOB == TRUE)) + ) + setParamParameters[0] = + SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_INVSPEC; + else + setParamParameters[0] = + SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_REGSPEC; + break; + } + setParamParameters[1] = (u16_t) (freq & 0xFFFF); + setParamParameters[2] = trkFilterValue; + scuCmd.parameter = setParamParameters; + scuCmd.resultLen = 1; + scuCmd.result = cmdResult; + mode_index = mode_val[(setParamParameters[0] & 0xC0) >> 6]; + CHK_ERROR(SCUCommand(devAddr, &scuCmd)); + + WR16(devAddr, SIO_TOP_COMM_KEY__A, 0xFABA); /* Write magic word to enable pdr reg write */ + WR16(devAddr, SIO_PDR_OOB_CRX_CFG__A, + OOB_CRX_DRIVE_STRENGTH << SIO_PDR_OOB_CRX_CFG_DRIVE__B + | 0x03 << SIO_PDR_OOB_CRX_CFG_MODE__B); + WR16(devAddr, SIO_PDR_OOB_DRX_CFG__A, + OOB_DRX_DRIVE_STRENGTH << SIO_PDR_OOB_DRX_CFG_DRIVE__B + | 0x03 << SIO_PDR_OOB_DRX_CFG_MODE__B); + WR16(devAddr, SIO_TOP_COMM_KEY__A, 0x0000); /* Write magic word to disable pdr reg write */ + + WR16(devAddr, ORX_TOP_COMM_KEY__A, 0); + WR16(devAddr, ORX_FWP_AAG_LEN_W__A, 16000); + WR16(devAddr, ORX_FWP_AAG_THR_W__A, 40); + + /* ddc */ + WR16(devAddr, ORX_DDC_OFO_SET_W__A, ORX_DDC_OFO_SET_W__PRE); + + /* nsu */ + WR16(devAddr, ORX_NSU_AOX_LOPOW_W__A, extAttr->oobLoPow); + + /* initialization for target mode */ + WR16(devAddr, SCU_RAM_ORX_TARGET_MODE__A, + SCU_RAM_ORX_TARGET_MODE_2048KBPS_SQRT); + WR16(devAddr, SCU_RAM_ORX_FREQ_GAIN_CORR__A, + SCU_RAM_ORX_FREQ_GAIN_CORR_2048KBPS); + + /* Reset bits for timing and freq. recovery */ + WR16(devAddr, SCU_RAM_ORX_RST_CPH__A, 0x0001); + WR16(devAddr, SCU_RAM_ORX_RST_CTI__A, 0x0002); + WR16(devAddr, SCU_RAM_ORX_RST_KRN__A, 0x0004); + WR16(devAddr, SCU_RAM_ORX_RST_KRP__A, 0x0008); + + /* AGN_LOCK = {2048>>3, -2048, 8, -8, 0, 1}; */ + WR16(devAddr, SCU_RAM_ORX_AGN_LOCK_TH__A, 2048 >> 3); + WR16(devAddr, SCU_RAM_ORX_AGN_LOCK_TOTH__A, (u16_t) (-2048)); + WR16(devAddr, SCU_RAM_ORX_AGN_ONLOCK_TTH__A, 8); + WR16(devAddr, SCU_RAM_ORX_AGN_UNLOCK_TTH__A, (u16_t) (-8)); + WR16(devAddr, SCU_RAM_ORX_AGN_LOCK_MASK__A, 1); + + /* DGN_LOCK = {10, -2048, 8, -8, 0, 1<<1}; */ + WR16(devAddr, SCU_RAM_ORX_DGN_LOCK_TH__A, 10); + WR16(devAddr, SCU_RAM_ORX_DGN_LOCK_TOTH__A, (u16_t) (-2048)); + WR16(devAddr, SCU_RAM_ORX_DGN_ONLOCK_TTH__A, 8); + WR16(devAddr, SCU_RAM_ORX_DGN_UNLOCK_TTH__A, (u16_t) (-8)); + WR16(devAddr, SCU_RAM_ORX_DGN_LOCK_MASK__A, 1 << 1); + + /* FRQ_LOCK = {15,-2048, 8, -8, 0, 1<<2}; */ + WR16(devAddr, SCU_RAM_ORX_FRQ_LOCK_TH__A, 17); + WR16(devAddr, SCU_RAM_ORX_FRQ_LOCK_TOTH__A, (u16_t) (-2048)); + WR16(devAddr, SCU_RAM_ORX_FRQ_ONLOCK_TTH__A, 8); + WR16(devAddr, SCU_RAM_ORX_FRQ_UNLOCK_TTH__A, (u16_t) (-8)); + WR16(devAddr, SCU_RAM_ORX_FRQ_LOCK_MASK__A, 1 << 2); + + /* PHA_LOCK = {5000, -2048, 8, -8, 0, 1<<3}; */ + WR16(devAddr, SCU_RAM_ORX_PHA_LOCK_TH__A, 3000); + WR16(devAddr, SCU_RAM_ORX_PHA_LOCK_TOTH__A, (u16_t) (-2048)); + WR16(devAddr, SCU_RAM_ORX_PHA_ONLOCK_TTH__A, 8); + WR16(devAddr, SCU_RAM_ORX_PHA_UNLOCK_TTH__A, (u16_t) (-8)); + WR16(devAddr, SCU_RAM_ORX_PHA_LOCK_MASK__A, 1 << 3); + + /* TIM_LOCK = {300, -2048, 8, -8, 0, 1<<4}; */ + WR16(devAddr, SCU_RAM_ORX_TIM_LOCK_TH__A, 400); + WR16(devAddr, SCU_RAM_ORX_TIM_LOCK_TOTH__A, (u16_t) (-2048)); + WR16(devAddr, SCU_RAM_ORX_TIM_ONLOCK_TTH__A, 8); + WR16(devAddr, SCU_RAM_ORX_TIM_UNLOCK_TTH__A, (u16_t) (-8)); + WR16(devAddr, SCU_RAM_ORX_TIM_LOCK_MASK__A, 1 << 4); + + /* EQU_LOCK = {20, -2048, 8, -8, 0, 1<<5}; */ + WR16(devAddr, SCU_RAM_ORX_EQU_LOCK_TH__A, 20); + WR16(devAddr, SCU_RAM_ORX_EQU_LOCK_TOTH__A, (u16_t) (-2048)); + WR16(devAddr, SCU_RAM_ORX_EQU_ONLOCK_TTH__A, 4); + WR16(devAddr, SCU_RAM_ORX_EQU_UNLOCK_TTH__A, (u16_t) (-4)); + WR16(devAddr, SCU_RAM_ORX_EQU_LOCK_MASK__A, 1 << 5); + + /* PRE-Filter coefficients (PFI) */ + WRB(devAddr, ORX_FWP_PFI_A_W__A, sizeof(PFICoeffs[mode_index]), + ((pu8_t) PFICoeffs[mode_index])); + WR16(devAddr, ORX_TOP_MDE_W__A, mode_index); + + /* NYQUIST-Filter coefficients (NYQ) */ + for (i = 0; i < (NYQFILTERLEN + 1) / 2; i++) { + WR16(devAddr, ORX_FWP_NYQ_ADR_W__A, i); + WR16(devAddr, ORX_FWP_NYQ_COF_RW__A, + NyquistCoeffs[mode_index][i]); + } + WR16(devAddr, ORX_FWP_NYQ_ADR_W__A, 31); + WR16(devAddr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_ACTIVE); /*********/ - /* Start */ + /* Start */ /*********/ - scuCmd.command = SCU_RAM_COMMAND_STANDARD_OOB - | SCU_RAM_COMMAND_CMD_DEMOD_START; - scuCmd.parameterLen = 0; - scuCmd.resultLen = 1; - scuCmd.result = cmdResult; - CHK_ERROR( SCUCommand( devAddr, &scuCmd ) ); + scuCmd.command = SCU_RAM_COMMAND_STANDARD_OOB + | SCU_RAM_COMMAND_CMD_DEMOD_START; + scuCmd.parameterLen = 0; + scuCmd.resultLen = 1; + scuCmd.result = cmdResult; + CHK_ERROR(SCUCommand(devAddr, &scuCmd)); - CHK_ERROR( SetOrxNsuAox( demod, TRUE ) ); - WR16( devAddr, ORX_NSU_AOX_STHR_W__A, extAttr->oobPreSaw ); + CHK_ERROR(SetOrxNsuAox(demod, TRUE)); + WR16(devAddr, ORX_NSU_AOX_STHR_W__A, extAttr->oobPreSaw); - extAttr->oobPowerOn = TRUE; + extAttr->oobPowerOn = TRUE; - return (DRX_STS_OK); + return (DRX_STS_OK); rw_error: #endif - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } + /** * \fn DRXStatus_t CtrlGetOOB() * \brief Set modulation standard to be used. @@ -13361,40 +12747,40 @@ rw_error: * \return DRXStatus_t. */ static DRXStatus_t -CtrlGetOOB( pDRXDemodInstance_t demod, pDRXOOBStatus_t oobStatus ) +CtrlGetOOB(pDRXDemodInstance_t demod, pDRXOOBStatus_t oobStatus) { #ifndef DRXJ_DIGITAL_ONLY - pI2CDeviceAddr_t devAddr = NULL; - pDRXJData_t extAttr = NULL; - u16_t data = 0; + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + u16_t data = 0; - devAddr = demod -> myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; - /* check arguments */ - if ( oobStatus == NULL ) - { - return (DRX_STS_INVALID_ARG); - } + /* check arguments */ + if (oobStatus == NULL) { + return (DRX_STS_INVALID_ARG); + } - if ( extAttr->oobPowerOn == FALSE) - return (DRX_STS_ERROR); + if (extAttr->oobPowerOn == FALSE) + return (DRX_STS_ERROR); - RR16 ( devAddr, ORX_DDC_OFO_SET_W__A, &data); - RR16 ( devAddr, ORX_NSU_TUN_RFGAIN_W__A, &data); - RR16 ( devAddr, ORX_FWP_AAG_THR_W__A, &data); - SARR16 ( devAddr, SCU_RAM_ORX_DGN_KI__A, &data); - RR16 ( devAddr, ORX_FWP_SRC_DGN_W__A, &data); + RR16(devAddr, ORX_DDC_OFO_SET_W__A, &data); + RR16(devAddr, ORX_NSU_TUN_RFGAIN_W__A, &data); + RR16(devAddr, ORX_FWP_AAG_THR_W__A, &data); + SARR16(devAddr, SCU_RAM_ORX_DGN_KI__A, &data); + RR16(devAddr, ORX_FWP_SRC_DGN_W__A, &data); - CHK_ERROR ( GetOOBLockStatus ( demod, devAddr, &oobStatus->lock )); - CHK_ERROR ( GetOOBFrequency ( demod, &oobStatus->frequency )); - CHK_ERROR ( GetOOBMER ( devAddr, &oobStatus->mer )); - CHK_ERROR ( GetOOBSymbolRateOffset ( devAddr, &oobStatus->symbolRateOffset )); + CHK_ERROR(GetOOBLockStatus(demod, devAddr, &oobStatus->lock)); + CHK_ERROR(GetOOBFrequency(demod, &oobStatus->frequency)); + CHK_ERROR(GetOOBMER(devAddr, &oobStatus->mer)); + CHK_ERROR(GetOOBSymbolRateOffset + (devAddr, &oobStatus->symbolRateOffset)); - return (DRX_STS_OK); + return (DRX_STS_OK); rw_error: #endif - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /** @@ -13405,23 +12791,22 @@ rw_error: */ #ifndef DRXJ_DIGITAL_ONLY static DRXStatus_t -CtrlSetCfgOOBPreSAW( pDRXDemodInstance_t demod, pu16_t cfgData ) +CtrlSetCfgOOBPreSAW(pDRXDemodInstance_t demod, pu16_t cfgData) { - pI2CDeviceAddr_t devAddr = NULL; - pDRXJData_t extAttr = NULL; + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; - if(cfgData == NULL) - { - return (DRX_STS_INVALID_ARG); - } - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t)demod->myExtAttr; - - WR16( devAddr, ORX_NSU_AOX_STHR_W__A, *cfgData ); - extAttr->oobPreSaw = *cfgData; - return (DRX_STS_OK); + if (cfgData == NULL) { + return (DRX_STS_INVALID_ARG); + } + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; + + WR16(devAddr, ORX_NSU_AOX_STHR_W__A, *cfgData); + extAttr->oobPreSaw = *cfgData; + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } #endif @@ -13433,19 +12818,18 @@ rw_error: */ #ifndef DRXJ_DIGITAL_ONLY static DRXStatus_t -CtrlGetCfgOOBPreSAW( pDRXDemodInstance_t demod, pu16_t cfgData ) +CtrlGetCfgOOBPreSAW(pDRXDemodInstance_t demod, pu16_t cfgData) { - pDRXJData_t extAttr = NULL; + pDRXJData_t extAttr = NULL; - if(cfgData == NULL) - { - return (DRX_STS_INVALID_ARG); - } - extAttr = (pDRXJData_t)demod->myExtAttr; + if (cfgData == NULL) { + return (DRX_STS_INVALID_ARG); + } + extAttr = (pDRXJData_t) demod->myExtAttr; - *cfgData = extAttr->oobPreSaw; + *cfgData = extAttr->oobPreSaw; - return (DRX_STS_OK); + return (DRX_STS_OK); } #endif @@ -13457,23 +12841,22 @@ CtrlGetCfgOOBPreSAW( pDRXDemodInstance_t demod, pu16_t cfgData ) */ #ifndef DRXJ_DIGITAL_ONLY static DRXStatus_t -CtrlSetCfgOOBLoPower( pDRXDemodInstance_t demod, pDRXJCfgOobLoPower_t cfgData ) +CtrlSetCfgOOBLoPower(pDRXDemodInstance_t demod, pDRXJCfgOobLoPower_t cfgData) { - pI2CDeviceAddr_t devAddr = NULL; - pDRXJData_t extAttr = NULL; + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; - if(cfgData == NULL) - { - return (DRX_STS_INVALID_ARG); - } - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t)demod->myExtAttr; - - WR16( devAddr, ORX_NSU_AOX_LOPOW_W__A, *cfgData ); - extAttr->oobLoPow = *cfgData; - return (DRX_STS_OK); + if (cfgData == NULL) { + return (DRX_STS_INVALID_ARG); + } + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; + + WR16(devAddr, ORX_NSU_AOX_LOPOW_W__A, *cfgData); + extAttr->oobLoPow = *cfgData; + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } #endif @@ -13485,19 +12868,18 @@ rw_error: */ #ifndef DRXJ_DIGITAL_ONLY static DRXStatus_t -CtrlGetCfgOOBLoPower( pDRXDemodInstance_t demod, pDRXJCfgOobLoPower_t cfgData ) +CtrlGetCfgOOBLoPower(pDRXDemodInstance_t demod, pDRXJCfgOobLoPower_t cfgData) { - pDRXJData_t extAttr = NULL; + pDRXJData_t extAttr = NULL; - if(cfgData == NULL) - { - return (DRX_STS_INVALID_ARG); - } - extAttr = (pDRXJData_t)demod->myExtAttr; + if (cfgData == NULL) { + return (DRX_STS_INVALID_ARG); + } + extAttr = (pDRXJData_t) demod->myExtAttr; - *cfgData = extAttr->oobLoPow; + *cfgData = extAttr->oobLoPow; - return (DRX_STS_OK); + return (DRX_STS_OK); } #endif /*============================================================================*/ @@ -13523,412 +12905,375 @@ CtrlGetCfgOOBLoPower( pDRXDemodInstance_t demod, pDRXJCfgOobLoPower_t cfgData ) * */ static DRXStatus_t -CtrlSetChannel( pDRXDemodInstance_t demod, - pDRXChannel_t channel ) +CtrlSetChannel(pDRXDemodInstance_t demod, pDRXChannel_t channel) { - DRXFrequency_t tunerSetFreq = 0; - DRXFrequency_t tunerGetFreq = 0; - DRXFrequency_t tunerFreqOffset = 0; - DRXFrequency_t intermediateFreq = 0; - pDRXJData_t extAttr = NULL; - pI2CDeviceAddr_t devAddr = NULL; - DRXStandard_t standard = DRX_STANDARD_UNKNOWN; - TUNERMode_t tunerMode = 0; - pDRXCommonAttr_t commonAttr = NULL; - Bool_t bridgeClosed = FALSE; + DRXFrequency_t tunerSetFreq = 0; + DRXFrequency_t tunerGetFreq = 0; + DRXFrequency_t tunerFreqOffset = 0; + DRXFrequency_t intermediateFreq = 0; + pDRXJData_t extAttr = NULL; + pI2CDeviceAddr_t devAddr = NULL; + DRXStandard_t standard = DRX_STANDARD_UNKNOWN; + TUNERMode_t tunerMode = 0; + pDRXCommonAttr_t commonAttr = NULL; + Bool_t bridgeClosed = FALSE; #ifndef DRXJ_VSB_ONLY - u32_t minSymbolRate = 0; - u32_t maxSymbolRate = 0; - int bandwidthTemp = 0; - int bandwidth = 0; + u32_t minSymbolRate = 0; + u32_t maxSymbolRate = 0; + int bandwidthTemp = 0; + int bandwidth = 0; #endif /*== check arguments ======================================================*/ - if ( ( demod == NULL ) || - ( channel == NULL ) ) - { - return DRX_STS_INVALID_ARG; - } + if ((demod == NULL) || (channel == NULL)) { + return DRX_STS_INVALID_ARG; + } - commonAttr = (pDRXCommonAttr_t) demod -> myCommonAttr; - devAddr = demod -> myI2CDevAddr; - extAttr = (pDRXJData_t)demod -> myExtAttr; - standard = extAttr->standard; + commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; + standard = extAttr->standard; - /* check valid standards */ - switch ( standard ) - { - case DRX_STANDARD_8VSB: + /* check valid standards */ + switch (standard) { + case DRX_STANDARD_8VSB: #ifndef DRXJ_VSB_ONLY - case DRX_STANDARD_ITU_A: - case DRX_STANDARD_ITU_B: - case DRX_STANDARD_ITU_C: + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: #endif /* DRXJ_VSB_ONLY */ #ifndef DRXJ_DIGITAL_ONLY - case DRX_STANDARD_NTSC: - case DRX_STANDARD_FM: - case DRX_STANDARD_PAL_SECAM_BG: - case DRX_STANDARD_PAL_SECAM_DK: - case DRX_STANDARD_PAL_SECAM_I: - case DRX_STANDARD_PAL_SECAM_L: - case DRX_STANDARD_PAL_SECAM_LP: + case DRX_STANDARD_NTSC: + case DRX_STANDARD_FM: + case DRX_STANDARD_PAL_SECAM_BG: + case DRX_STANDARD_PAL_SECAM_DK: + case DRX_STANDARD_PAL_SECAM_I: + case DRX_STANDARD_PAL_SECAM_L: + case DRX_STANDARD_PAL_SECAM_LP: #endif /* DRXJ_DIGITAL_ONLY */ - break; - case DRX_STANDARD_UNKNOWN: - default: - return (DRX_STS_INVALID_ARG); - } - - /* check bandwidth QAM annex B, NTSC and 8VSB */ - if ( ( standard == DRX_STANDARD_ITU_B ) || - ( standard == DRX_STANDARD_8VSB ) || - ( standard == DRX_STANDARD_NTSC ) ) - { - switch ( channel->bandwidth ) { - case DRX_BANDWIDTH_6MHZ : - case DRX_BANDWIDTH_UNKNOWN : /* fall through */ - channel->bandwidth = DRX_BANDWIDTH_6MHZ; - break; - case DRX_BANDWIDTH_8MHZ : /* fall through */ - case DRX_BANDWIDTH_7MHZ : /* fall through */ - default : - return (DRX_STS_INVALID_ARG); - } - } + break; + case DRX_STANDARD_UNKNOWN: + default: + return (DRX_STS_INVALID_ARG); + } + /* check bandwidth QAM annex B, NTSC and 8VSB */ + if ((standard == DRX_STANDARD_ITU_B) || + (standard == DRX_STANDARD_8VSB) || + (standard == DRX_STANDARD_NTSC)) { + switch (channel->bandwidth) { + case DRX_BANDWIDTH_6MHZ: + case DRX_BANDWIDTH_UNKNOWN: /* fall through */ + channel->bandwidth = DRX_BANDWIDTH_6MHZ; + break; + case DRX_BANDWIDTH_8MHZ: /* fall through */ + case DRX_BANDWIDTH_7MHZ: /* fall through */ + default: + return (DRX_STS_INVALID_ARG); + } + } #ifndef DRXJ_DIGITAL_ONLY - if ( standard == DRX_STANDARD_PAL_SECAM_BG ) - { - switch ( channel->bandwidth ) - { - case DRX_BANDWIDTH_7MHZ : /* fall through */ - case DRX_BANDWIDTH_8MHZ : - /* ok */ - break; - case DRX_BANDWIDTH_6MHZ : /* fall through */ - case DRX_BANDWIDTH_UNKNOWN : /* fall through */ - default : - return (DRX_STS_INVALID_ARG); - } - } - /* check bandwidth PAL/SECAM */ - if ( ( standard == DRX_STANDARD_PAL_SECAM_BG ) || - ( standard == DRX_STANDARD_PAL_SECAM_DK ) || - ( standard == DRX_STANDARD_PAL_SECAM_I ) || - ( standard == DRX_STANDARD_PAL_SECAM_L ) || - ( standard == DRX_STANDARD_PAL_SECAM_LP ) ) - { - switch ( channel->bandwidth ) - { - case DRX_BANDWIDTH_8MHZ : - case DRX_BANDWIDTH_UNKNOWN : /* fall through */ - channel->bandwidth = DRX_BANDWIDTH_8MHZ; - break; - case DRX_BANDWIDTH_6MHZ : /* fall through */ - case DRX_BANDWIDTH_7MHZ : /* fall through */ - default : - return (DRX_STS_INVALID_ARG); - } - } + if (standard == DRX_STANDARD_PAL_SECAM_BG) { + switch (channel->bandwidth) { + case DRX_BANDWIDTH_7MHZ: /* fall through */ + case DRX_BANDWIDTH_8MHZ: + /* ok */ + break; + case DRX_BANDWIDTH_6MHZ: /* fall through */ + case DRX_BANDWIDTH_UNKNOWN: /* fall through */ + default: + return (DRX_STS_INVALID_ARG); + } + } + /* check bandwidth PAL/SECAM */ + if ((standard == DRX_STANDARD_PAL_SECAM_BG) || + (standard == DRX_STANDARD_PAL_SECAM_DK) || + (standard == DRX_STANDARD_PAL_SECAM_I) || + (standard == DRX_STANDARD_PAL_SECAM_L) || + (standard == DRX_STANDARD_PAL_SECAM_LP)) { + switch (channel->bandwidth) { + case DRX_BANDWIDTH_8MHZ: + case DRX_BANDWIDTH_UNKNOWN: /* fall through */ + channel->bandwidth = DRX_BANDWIDTH_8MHZ; + break; + case DRX_BANDWIDTH_6MHZ: /* fall through */ + case DRX_BANDWIDTH_7MHZ: /* fall through */ + default: + return (DRX_STS_INVALID_ARG); + } + } #endif - /* For QAM annex A and annex C: - -check symbolrate and constellation - -derive bandwidth from symbolrate (input bandwidth is ignored) - */ + /* For QAM annex A and annex C: + -check symbolrate and constellation + -derive bandwidth from symbolrate (input bandwidth is ignored) + */ #ifndef DRXJ_VSB_ONLY - if( ( standard == DRX_STANDARD_ITU_A ) || - ( standard == DRX_STANDARD_ITU_C ) ) - { - DRXUIOCfg_t UIOCfg = {DRX_UIO1, DRX_UIO_MODE_FIRMWARE_SAW}; - int bwRolloffFactor = 0; - - bwRolloffFactor = (standard == DRX_STANDARD_ITU_A)?115:113; - minSymbolRate = DRXJ_QAM_SYMBOLRATE_MIN; - maxSymbolRate = DRXJ_QAM_SYMBOLRATE_MAX; - /* config SMA_TX pin to SAW switch mode*/ - CHK_ERROR( CtrlSetUIOCfg( demod, &UIOCfg ) ); - - if ( channel->symbolrate < minSymbolRate || - channel->symbolrate > maxSymbolRate ) - { - return ( DRX_STS_INVALID_ARG ); - } - - switch ( channel->constellation ) { - case DRX_CONSTELLATION_QAM16 : /* fall through */ - case DRX_CONSTELLATION_QAM32 : /* fall through */ - case DRX_CONSTELLATION_QAM64 : /* fall through */ - case DRX_CONSTELLATION_QAM128 : /* fall through */ - case DRX_CONSTELLATION_QAM256 : - bandwidthTemp = channel->symbolrate * bwRolloffFactor; - bandwidth = bandwidthTemp / 100; - - if( ( bandwidthTemp % 100 ) >= 50 ) - { - bandwidth++; - } - - if( bandwidth <= 6100000 ) - { - channel->bandwidth = DRX_BANDWIDTH_6MHZ; - } - else if( ( bandwidth > 6100000 ) && ( bandwidth <= 7100000 ) ) - { - channel->bandwidth = DRX_BANDWIDTH_7MHZ; - } - else if( bandwidth > 7100000 ) - { - channel->bandwidth = DRX_BANDWIDTH_8MHZ; - } - break; - default: - return (DRX_STS_INVALID_ARG); - } - } - - /* For QAM annex B: - -check constellation - */ - if ( standard == DRX_STANDARD_ITU_B ) - { - switch ( channel->constellation ) { - case DRX_CONSTELLATION_AUTO : - case DRX_CONSTELLATION_QAM256 : - case DRX_CONSTELLATION_QAM64 : - break; - default : - return (DRX_STS_INVALID_ARG); - } - - switch (channel->interleavemode) - { - case DRX_INTERLEAVEMODE_I128_J1: - case DRX_INTERLEAVEMODE_I128_J1_V2: - case DRX_INTERLEAVEMODE_I128_J2: - case DRX_INTERLEAVEMODE_I64_J2: - case DRX_INTERLEAVEMODE_I128_J3: - case DRX_INTERLEAVEMODE_I32_J4: - case DRX_INTERLEAVEMODE_I128_J4: - case DRX_INTERLEAVEMODE_I16_J8: - case DRX_INTERLEAVEMODE_I128_J5: - case DRX_INTERLEAVEMODE_I8_J16: - case DRX_INTERLEAVEMODE_I128_J6: - case DRX_INTERLEAVEMODE_I128_J7: - case DRX_INTERLEAVEMODE_I128_J8: - case DRX_INTERLEAVEMODE_I12_J17: - case DRX_INTERLEAVEMODE_I5_J4: - case DRX_INTERLEAVEMODE_B52_M240: - case DRX_INTERLEAVEMODE_B52_M720: - case DRX_INTERLEAVEMODE_UNKNOWN: - case DRX_INTERLEAVEMODE_AUTO: - break; - default: - return (DRX_STS_INVALID_ARG); - } - } - - if ( (extAttr->uioSmaTxMode) == DRX_UIO_MODE_FIRMWARE_SAW ) - { - /* SAW SW, user UIO is used for switchable SAW */ - DRXUIOData_t uio1 = { DRX_UIO1, FALSE }; - - switch ( channel->bandwidth ) - { - case DRX_BANDWIDTH_8MHZ: - uio1.value = TRUE; - break; - case DRX_BANDWIDTH_7MHZ: - uio1.value = FALSE; - break; - case DRX_BANDWIDTH_6MHZ: - uio1.value = FALSE; - break; - case DRX_BANDWIDTH_UNKNOWN: - default: - return (DRX_STS_INVALID_ARG); - } - - CHK_ERROR( CtrlUIOWrite( demod, &uio1 ) ); - } + if ((standard == DRX_STANDARD_ITU_A) || + (standard == DRX_STANDARD_ITU_C)) { + DRXUIOCfg_t UIOCfg = { DRX_UIO1, DRX_UIO_MODE_FIRMWARE_SAW }; + int bwRolloffFactor = 0; + + bwRolloffFactor = (standard == DRX_STANDARD_ITU_A) ? 115 : 113; + minSymbolRate = DRXJ_QAM_SYMBOLRATE_MIN; + maxSymbolRate = DRXJ_QAM_SYMBOLRATE_MAX; + /* config SMA_TX pin to SAW switch mode */ + CHK_ERROR(CtrlSetUIOCfg(demod, &UIOCfg)); + + if (channel->symbolrate < minSymbolRate || + channel->symbolrate > maxSymbolRate) { + return (DRX_STS_INVALID_ARG); + } + + switch (channel->constellation) { + case DRX_CONSTELLATION_QAM16: /* fall through */ + case DRX_CONSTELLATION_QAM32: /* fall through */ + case DRX_CONSTELLATION_QAM64: /* fall through */ + case DRX_CONSTELLATION_QAM128: /* fall through */ + case DRX_CONSTELLATION_QAM256: + bandwidthTemp = channel->symbolrate * bwRolloffFactor; + bandwidth = bandwidthTemp / 100; + + if ((bandwidthTemp % 100) >= 50) { + bandwidth++; + } + + if (bandwidth <= 6100000) { + channel->bandwidth = DRX_BANDWIDTH_6MHZ; + } else if ((bandwidth > 6100000) + && (bandwidth <= 7100000)) { + channel->bandwidth = DRX_BANDWIDTH_7MHZ; + } else if (bandwidth > 7100000) { + channel->bandwidth = DRX_BANDWIDTH_8MHZ; + } + break; + default: + return (DRX_STS_INVALID_ARG); + } + } + + /* For QAM annex B: + -check constellation + */ + if (standard == DRX_STANDARD_ITU_B) { + switch (channel->constellation) { + case DRX_CONSTELLATION_AUTO: + case DRX_CONSTELLATION_QAM256: + case DRX_CONSTELLATION_QAM64: + break; + default: + return (DRX_STS_INVALID_ARG); + } + + switch (channel->interleavemode) { + case DRX_INTERLEAVEMODE_I128_J1: + case DRX_INTERLEAVEMODE_I128_J1_V2: + case DRX_INTERLEAVEMODE_I128_J2: + case DRX_INTERLEAVEMODE_I64_J2: + case DRX_INTERLEAVEMODE_I128_J3: + case DRX_INTERLEAVEMODE_I32_J4: + case DRX_INTERLEAVEMODE_I128_J4: + case DRX_INTERLEAVEMODE_I16_J8: + case DRX_INTERLEAVEMODE_I128_J5: + case DRX_INTERLEAVEMODE_I8_J16: + case DRX_INTERLEAVEMODE_I128_J6: + case DRX_INTERLEAVEMODE_I128_J7: + case DRX_INTERLEAVEMODE_I128_J8: + case DRX_INTERLEAVEMODE_I12_J17: + case DRX_INTERLEAVEMODE_I5_J4: + case DRX_INTERLEAVEMODE_B52_M240: + case DRX_INTERLEAVEMODE_B52_M720: + case DRX_INTERLEAVEMODE_UNKNOWN: + case DRX_INTERLEAVEMODE_AUTO: + break; + default: + return (DRX_STS_INVALID_ARG); + } + } + + if ((extAttr->uioSmaTxMode) == DRX_UIO_MODE_FIRMWARE_SAW) { + /* SAW SW, user UIO is used for switchable SAW */ + DRXUIOData_t uio1 = { DRX_UIO1, FALSE }; + + switch (channel->bandwidth) { + case DRX_BANDWIDTH_8MHZ: + uio1.value = TRUE; + break; + case DRX_BANDWIDTH_7MHZ: + uio1.value = FALSE; + break; + case DRX_BANDWIDTH_6MHZ: + uio1.value = FALSE; + break; + case DRX_BANDWIDTH_UNKNOWN: + default: + return (DRX_STS_INVALID_ARG); + } + + CHK_ERROR(CtrlUIOWrite(demod, &uio1)); + } #endif /* DRXJ_VSB_ONLY */ - WR16( devAddr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); + WR16(devAddr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); /*== Tune, fast mode ======================================================*/ - if ( demod->myTuner != NULL ) - { - /* Determine tuner mode and freq to tune to ... */ - switch ( standard ) { + if (demod->myTuner != NULL) { + /* Determine tuner mode and freq to tune to ... */ + switch (standard) { #ifndef DRXJ_DIGITAL_ONLY - case DRX_STANDARD_NTSC: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_LP: - /* expecting center frequency, not picture carrier so no - conversion .... */ - tunerMode |= TUNER_MODE_ANALOG; - tunerSetFreq = channel->frequency; - break; - case DRX_STANDARD_FM: - /* center frequency (equals sound carrier) as input, - tune to edge of SAW */ - tunerMode |= TUNER_MODE_ANALOG; - tunerSetFreq = channel->frequency + DRXJ_FM_CARRIER_FREQ_OFFSET; - break; + case DRX_STANDARD_NTSC: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_LP: + /* expecting center frequency, not picture carrier so no + conversion .... */ + tunerMode |= TUNER_MODE_ANALOG; + tunerSetFreq = channel->frequency; + break; + case DRX_STANDARD_FM: + /* center frequency (equals sound carrier) as input, + tune to edge of SAW */ + tunerMode |= TUNER_MODE_ANALOG; + tunerSetFreq = + channel->frequency + DRXJ_FM_CARRIER_FREQ_OFFSET; + break; #endif - case DRX_STANDARD_8VSB: /* fallthrough */ + case DRX_STANDARD_8VSB: /* fallthrough */ #ifndef DRXJ_VSB_ONLY - case DRX_STANDARD_ITU_A: /* fallthrough */ - case DRX_STANDARD_ITU_B: /* fallthrough */ - case DRX_STANDARD_ITU_C: + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: #endif - tunerMode |= TUNER_MODE_DIGITAL; - tunerSetFreq = channel->frequency; - break; - case DRX_STANDARD_UNKNOWN: - default: - return (DRX_STS_ERROR); - } /* switch(standard) */ - - tunerMode |= TUNER_MODE_SWITCH; - switch ( channel->bandwidth ) { - case DRX_BANDWIDTH_8MHZ : - tunerMode |= TUNER_MODE_8MHZ; - break; - case DRX_BANDWIDTH_7MHZ : - tunerMode |= TUNER_MODE_7MHZ; - break; - case DRX_BANDWIDTH_6MHZ : - tunerMode |= TUNER_MODE_6MHZ; - break; - default: - /* TODO: for FM which bandwidth to use ? - also check offset from centre frequency ? - For now using 6MHz. - */ - tunerMode |= TUNER_MODE_6MHZ; - break; - /* return (DRX_STS_INVALID_ARG); */ - } - - /* store bandwidth for GetChannel() */ - extAttr->currBandwidth = channel->bandwidth; - extAttr->currSymbolRate = channel->symbolrate; - extAttr->frequency = tunerSetFreq; - if ( commonAttr->tunerPortNr == 1 ) - { - /* close tuner bridge */ - bridgeClosed = TRUE; - CHK_ERROR( CtrlI2CBridge( demod, &bridgeClosed ) ); - /* set tuner frequency */ - } - - CHK_ERROR( DRXBSP_TUNER_SetFrequency( demod->myTuner, - tunerMode, - tunerSetFreq ) ); - if ( commonAttr->tunerPortNr == 1 ) - { - /* open tuner bridge */ - bridgeClosed = FALSE; - CHK_ERROR( CtrlI2CBridge( demod, &bridgeClosed ) ); - } - - /* Get actual frequency set by tuner and compute offset */ - CHK_ERROR( DRXBSP_TUNER_GetFrequency( demod->myTuner, - 0, - &tunerGetFreq, - &intermediateFreq ) ); - tunerFreqOffset = tunerGetFreq - tunerSetFreq; - commonAttr->intermediateFreq = intermediateFreq; - } - else - { - /* no tuner instance defined, use fixed intermediate frequency */ - tunerFreqOffset = 0; - intermediateFreq = demod->myCommonAttr->intermediateFreq; - } /* if ( demod->myTuner != NULL ) */ + tunerMode |= TUNER_MODE_DIGITAL; + tunerSetFreq = channel->frequency; + break; + case DRX_STANDARD_UNKNOWN: + default: + return (DRX_STS_ERROR); + } /* switch(standard) */ + + tunerMode |= TUNER_MODE_SWITCH; + switch (channel->bandwidth) { + case DRX_BANDWIDTH_8MHZ: + tunerMode |= TUNER_MODE_8MHZ; + break; + case DRX_BANDWIDTH_7MHZ: + tunerMode |= TUNER_MODE_7MHZ; + break; + case DRX_BANDWIDTH_6MHZ: + tunerMode |= TUNER_MODE_6MHZ; + break; + default: + /* TODO: for FM which bandwidth to use ? + also check offset from centre frequency ? + For now using 6MHz. + */ + tunerMode |= TUNER_MODE_6MHZ; + break; + /* return (DRX_STS_INVALID_ARG); */ + } + + /* store bandwidth for GetChannel() */ + extAttr->currBandwidth = channel->bandwidth; + extAttr->currSymbolRate = channel->symbolrate; + extAttr->frequency = tunerSetFreq; + if (commonAttr->tunerPortNr == 1) { + /* close tuner bridge */ + bridgeClosed = TRUE; + CHK_ERROR(CtrlI2CBridge(demod, &bridgeClosed)); + /* set tuner frequency */ + } + + CHK_ERROR(DRXBSP_TUNER_SetFrequency(demod->myTuner, + tunerMode, tunerSetFreq)); + if (commonAttr->tunerPortNr == 1) { + /* open tuner bridge */ + bridgeClosed = FALSE; + CHK_ERROR(CtrlI2CBridge(demod, &bridgeClosed)); + } + + /* Get actual frequency set by tuner and compute offset */ + CHK_ERROR(DRXBSP_TUNER_GetFrequency(demod->myTuner, + 0, + &tunerGetFreq, + &intermediateFreq)); + tunerFreqOffset = tunerGetFreq - tunerSetFreq; + commonAttr->intermediateFreq = intermediateFreq; + } else { + /* no tuner instance defined, use fixed intermediate frequency */ + tunerFreqOffset = 0; + intermediateFreq = demod->myCommonAttr->intermediateFreq; + } /* if ( demod->myTuner != NULL ) */ /*== Setup demod for specific standard ====================================*/ - switch ( standard ) { - case DRX_STANDARD_8VSB: - if (channel->mirror == DRX_MIRROR_AUTO) - { - extAttr->mirror = DRX_MIRROR_NO; - } - else - { - extAttr->mirror = channel->mirror; - } - CHK_ERROR ( SetVSB(demod) ); - CHK_ERROR ( SetFrequency ( demod, channel, tunerFreqOffset ) ); - break; + switch (standard) { + case DRX_STANDARD_8VSB: + if (channel->mirror == DRX_MIRROR_AUTO) { + extAttr->mirror = DRX_MIRROR_NO; + } else { + extAttr->mirror = channel->mirror; + } + CHK_ERROR(SetVSB(demod)); + CHK_ERROR(SetFrequency(demod, channel, tunerFreqOffset)); + break; #ifndef DRXJ_DIGITAL_ONLY - case DRX_STANDARD_NTSC: /* fallthrough */ - case DRX_STANDARD_FM: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_LP: - if (channel->mirror == DRX_MIRROR_AUTO) - { - extAttr->mirror = DRX_MIRROR_NO; - } - else - { - extAttr->mirror = channel->mirror; - } - CHK_ERROR ( SetATVChannel( demod, - tunerFreqOffset, - channel, - standard ) ); - break; + case DRX_STANDARD_NTSC: /* fallthrough */ + case DRX_STANDARD_FM: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_LP: + if (channel->mirror == DRX_MIRROR_AUTO) { + extAttr->mirror = DRX_MIRROR_NO; + } else { + extAttr->mirror = channel->mirror; + } + CHK_ERROR(SetATVChannel(demod, + tunerFreqOffset, channel, standard)); + break; #endif #ifndef DRXJ_VSB_ONLY - case DRX_STANDARD_ITU_A: /* fallthrough */ - case DRX_STANDARD_ITU_B: /* fallthrough */ - case DRX_STANDARD_ITU_C: - CHK_ERROR ( SetQAMChannel( demod, channel, tunerFreqOffset ) ); - break; + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: + CHK_ERROR(SetQAMChannel(demod, channel, tunerFreqOffset)); + break; #endif - case DRX_STANDARD_UNKNOWN: - default: - return (DRX_STS_ERROR); - } + case DRX_STANDARD_UNKNOWN: + default: + return (DRX_STS_ERROR); + } /*== Re-tune, slow mode ===================================================*/ - if ( demod->myTuner != NULL ) - { - /* tune to slow mode */ - tunerMode &= ~TUNER_MODE_SWITCH; - tunerMode |= TUNER_MODE_LOCK; - - if ( commonAttr->tunerPortNr == 1 ) - { - /* close tuner bridge */ - bridgeClosed = TRUE; - CHK_ERROR( CtrlI2CBridge( demod, &bridgeClosed ) ); - } - - /* set tuner frequency*/ - CHK_ERROR( DRXBSP_TUNER_SetFrequency( demod->myTuner, - tunerMode, - tunerSetFreq ) ); - if ( commonAttr->tunerPortNr == 1 ) - { - /* open tuner bridge */ - bridgeClosed = FALSE; - CHK_ERROR( CtrlI2CBridge( demod, &bridgeClosed ) ); - } - } /* if ( demod->myTuner !=NULL ) */ - - /* flag the packet error counter reset */ - extAttr->resetPktErrAcc = TRUE; - - return (DRX_STS_OK); + if (demod->myTuner != NULL) { + /* tune to slow mode */ + tunerMode &= ~TUNER_MODE_SWITCH; + tunerMode |= TUNER_MODE_LOCK; + + if (commonAttr->tunerPortNr == 1) { + /* close tuner bridge */ + bridgeClosed = TRUE; + CHK_ERROR(CtrlI2CBridge(demod, &bridgeClosed)); + } + + /* set tuner frequency */ + CHK_ERROR(DRXBSP_TUNER_SetFrequency(demod->myTuner, + tunerMode, tunerSetFreq)); + if (commonAttr->tunerPortNr == 1) { + /* open tuner bridge */ + bridgeClosed = FALSE; + CHK_ERROR(CtrlI2CBridge(demod, &bridgeClosed)); + } + } + + /* if ( demod->myTuner !=NULL ) */ + /* flag the packet error counter reset */ + extAttr->resetPktErrAcc = TRUE; + + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /*============================================================================= @@ -13942,216 +13287,212 @@ rw_error: * \return DRXStatus_t. */ static DRXStatus_t -CtrlGetChannel( pDRXDemodInstance_t demod, - pDRXChannel_t channel ) +CtrlGetChannel(pDRXDemodInstance_t demod, pDRXChannel_t channel) { - pI2CDeviceAddr_t devAddr = NULL; - pDRXJData_t extAttr = NULL; - DRXLockStatus_t lockStatus = DRX_NOT_LOCKED; - DRXStandard_t standard = DRX_STANDARD_UNKNOWN; - pDRXCommonAttr_t commonAttr = NULL; - DRXFrequency_t intermediateFreq = 0; - s32_t CTLFreqOffset = 0; - u32_t iqmRcRateLo = 0; - u32_t adcFrequency = 0; + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + DRXLockStatus_t lockStatus = DRX_NOT_LOCKED; + DRXStandard_t standard = DRX_STANDARD_UNKNOWN; + pDRXCommonAttr_t commonAttr = NULL; + DRXFrequency_t intermediateFreq = 0; + s32_t CTLFreqOffset = 0; + u32_t iqmRcRateLo = 0; + u32_t adcFrequency = 0; #ifndef DRXJ_VSB_ONLY - int bandwidthTemp = 0; - int bandwidth = 0; + int bandwidthTemp = 0; + int bandwidth = 0; #endif - /* check arguments */ - if ( ( demod == NULL ) || - ( channel == NULL ) ) - { - return DRX_STS_INVALID_ARG; - } - - devAddr = demod -> myI2CDevAddr; - extAttr = (pDRXJData_t)demod -> myExtAttr; - standard = extAttr->standard; - commonAttr = (pDRXCommonAttr_t) demod -> myCommonAttr; - - /* initialize channel fields */ - channel->mirror = DRX_MIRROR_UNKNOWN; - channel->hierarchy = DRX_HIERARCHY_UNKNOWN; - channel->priority = DRX_PRIORITY_UNKNOWN; - channel->coderate = DRX_CODERATE_UNKNOWN; - channel->guard = DRX_GUARD_UNKNOWN; - channel->fftmode = DRX_FFTMODE_UNKNOWN; - channel->classification = DRX_CLASSIFICATION_UNKNOWN; - channel->bandwidth = DRX_BANDWIDTH_UNKNOWN; - channel->constellation = DRX_CONSTELLATION_UNKNOWN; - channel->symbolrate = 0; - channel->interleavemode = DRX_INTERLEAVEMODE_UNKNOWN; - channel->carrier = DRX_CARRIER_UNKNOWN; - channel->framemode = DRX_FRAMEMODE_UNKNOWN; -/* channel->interleaver = DRX_INTERLEAVER_UNKNOWN;*/ - channel->ldpc = DRX_LDPC_UNKNOWN; + /* check arguments */ + if ((demod == NULL) || (channel == NULL)) { + return DRX_STS_INVALID_ARG; + } - if ( demod->myTuner != NULL ) - { - DRXFrequency_t tunerFreqOffset = 0; - Bool_t tunerMirror = commonAttr->mirrorFreqSpect?FALSE:TRUE; - - /* Get frequency from tuner */ - CHK_ERROR( DRXBSP_TUNER_GetFrequency( demod->myTuner, - 0, - &(channel->frequency), - &intermediateFreq ) ); - tunerFreqOffset = channel->frequency - extAttr->frequency; - if ( tunerMirror == TRUE ) - { - /* positive image */ - channel->frequency += tunerFreqOffset; - } else { - /* negative image */ - channel->frequency -= tunerFreqOffset; - } - - /* Handle sound carrier offset in RF domain */ - if ( standard == DRX_STANDARD_FM ) - { - channel->frequency -= DRXJ_FM_CARRIER_FREQ_OFFSET; - } - } - else - { - intermediateFreq = commonAttr->intermediateFreq; - } + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; + standard = extAttr->standard; + commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; + + /* initialize channel fields */ + channel->mirror = DRX_MIRROR_UNKNOWN; + channel->hierarchy = DRX_HIERARCHY_UNKNOWN; + channel->priority = DRX_PRIORITY_UNKNOWN; + channel->coderate = DRX_CODERATE_UNKNOWN; + channel->guard = DRX_GUARD_UNKNOWN; + channel->fftmode = DRX_FFTMODE_UNKNOWN; + channel->classification = DRX_CLASSIFICATION_UNKNOWN; + channel->bandwidth = DRX_BANDWIDTH_UNKNOWN; + channel->constellation = DRX_CONSTELLATION_UNKNOWN; + channel->symbolrate = 0; + channel->interleavemode = DRX_INTERLEAVEMODE_UNKNOWN; + channel->carrier = DRX_CARRIER_UNKNOWN; + channel->framemode = DRX_FRAMEMODE_UNKNOWN; +/* channel->interleaver = DRX_INTERLEAVER_UNKNOWN;*/ + channel->ldpc = DRX_LDPC_UNKNOWN; + + if (demod->myTuner != NULL) { + DRXFrequency_t tunerFreqOffset = 0; + Bool_t tunerMirror = commonAttr->mirrorFreqSpect ? FALSE : TRUE; + + /* Get frequency from tuner */ + CHK_ERROR(DRXBSP_TUNER_GetFrequency(demod->myTuner, + 0, + &(channel->frequency), + &intermediateFreq)); + tunerFreqOffset = channel->frequency - extAttr->frequency; + if (tunerMirror == TRUE) { + /* positive image */ + channel->frequency += tunerFreqOffset; + } else { + /* negative image */ + channel->frequency -= tunerFreqOffset; + } + + /* Handle sound carrier offset in RF domain */ + if (standard == DRX_STANDARD_FM) { + channel->frequency -= DRXJ_FM_CARRIER_FREQ_OFFSET; + } + } else { + intermediateFreq = commonAttr->intermediateFreq; + } - /* check lock status */ - CHK_ERROR( CtrlLockStatus( demod, &lockStatus) ); - if ( (lockStatus == DRX_LOCKED) || (lockStatus == DRXJ_DEMOD_LOCK) ) - { - ARR32( devAddr, IQM_RC_RATE_LO__A, &iqmRcRateLo ); - adcFrequency = ( commonAttr->sysClockFreq * 1000 ) / 3; - - channel->symbolrate = Frac28(adcFrequency, (iqmRcRateLo + (1<<23))) >> 7; - - switch ( standard ) - { - case DRX_STANDARD_8VSB: - channel->bandwidth = DRX_BANDWIDTH_6MHZ; - /* get the channel frequency */ - CHK_ERROR( GetCTLFreqOffset ( demod, &CTLFreqOffset ) ); - channel->frequency -= CTLFreqOffset; - /* get the channel constellation */ - channel->constellation = DRX_CONSTELLATION_AUTO; - break; + /* check lock status */ + CHK_ERROR(CtrlLockStatus(demod, &lockStatus)); + if ((lockStatus == DRX_LOCKED) || (lockStatus == DRXJ_DEMOD_LOCK)) { + ARR32(devAddr, IQM_RC_RATE_LO__A, &iqmRcRateLo); + adcFrequency = (commonAttr->sysClockFreq * 1000) / 3; + + channel->symbolrate = + Frac28(adcFrequency, (iqmRcRateLo + (1 << 23))) >> 7; + + switch (standard) { + case DRX_STANDARD_8VSB: + channel->bandwidth = DRX_BANDWIDTH_6MHZ; + /* get the channel frequency */ + CHK_ERROR(GetCTLFreqOffset(demod, &CTLFreqOffset)); + channel->frequency -= CTLFreqOffset; + /* get the channel constellation */ + channel->constellation = DRX_CONSTELLATION_AUTO; + break; #ifndef DRXJ_VSB_ONLY - case DRX_STANDARD_ITU_A: - case DRX_STANDARD_ITU_B: - case DRX_STANDARD_ITU_C: - { - /* get the channel frequency */ - CHK_ERROR( GetCTLFreqOffset ( demod, &CTLFreqOffset ) ); - channel->frequency -= CTLFreqOffset; - - if (standard == DRX_STANDARD_ITU_B) - { - channel->bandwidth = DRX_BANDWIDTH_6MHZ; - } - else - { - /* annex A & C */ - - u32_t rollOff=113; /* default annex C */ - - if ( standard==DRX_STANDARD_ITU_A) - { - rollOff=115; - } - - bandwidthTemp = channel->symbolrate * rollOff; - bandwidth = bandwidthTemp / 100; - - if( ( bandwidthTemp % 100 ) >= 50 ) - { - bandwidth++; - } - - if( bandwidth <= 6000000 ) - { - channel->bandwidth = DRX_BANDWIDTH_6MHZ; - } - else if( ( bandwidth > 6000000 ) && ( bandwidth <= 7000000 ) ) - { - channel->bandwidth = DRX_BANDWIDTH_7MHZ; - } - else if( bandwidth > 7000000 ) - { - channel->bandwidth = DRX_BANDWIDTH_8MHZ; - } - } /* if (standard == DRX_STANDARD_ITU_B) */ - - { - DRXJSCUCmd_t cmdSCU = { /* command */ 0, - /* parameterLen */ 0, - /* resultLen */ 0, - /* parameter */ NULL, - /* result */ NULL }; - u16_t cmdResult[3] = { 0, 0, 0 }; - - cmdSCU.command = SCU_RAM_COMMAND_STANDARD_QAM | - SCU_RAM_COMMAND_CMD_DEMOD_GET_PARAM; - cmdSCU.parameterLen = 0; - cmdSCU.resultLen = 3; - cmdSCU.parameter = NULL; - cmdSCU.result = cmdResult; - CHK_ERROR( SCUCommand( devAddr, &cmdSCU ) ); - - channel->interleavemode = (DRXInterleaveModes_t)(cmdSCU.result[2]); - } - - switch ( extAttr->constellation ) - { - case DRX_CONSTELLATION_QAM256: - channel->constellation = DRX_CONSTELLATION_QAM256; - break; - case DRX_CONSTELLATION_QAM128: - channel->constellation = DRX_CONSTELLATION_QAM128; - break; - case DRX_CONSTELLATION_QAM64: - channel->constellation = DRX_CONSTELLATION_QAM64; - break; - case DRX_CONSTELLATION_QAM32: - channel->constellation = DRX_CONSTELLATION_QAM32; - break; - case DRX_CONSTELLATION_QAM16: - channel->constellation = DRX_CONSTELLATION_QAM16; - break; - default: - channel->constellation = DRX_CONSTELLATION_UNKNOWN; - return (DRX_STS_ERROR); - } - } - break; + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: + { + /* get the channel frequency */ + CHK_ERROR(GetCTLFreqOffset + (demod, &CTLFreqOffset)); + channel->frequency -= CTLFreqOffset; + + if (standard == DRX_STANDARD_ITU_B) { + channel->bandwidth = DRX_BANDWIDTH_6MHZ; + } else { + /* annex A & C */ + + u32_t rollOff = 113; /* default annex C */ + + if (standard == DRX_STANDARD_ITU_A) { + rollOff = 115; + } + + bandwidthTemp = + channel->symbolrate * rollOff; + bandwidth = bandwidthTemp / 100; + + if ((bandwidthTemp % 100) >= 50) { + bandwidth++; + } + + if (bandwidth <= 6000000) { + channel->bandwidth = + DRX_BANDWIDTH_6MHZ; + } else if ((bandwidth > 6000000) + && (bandwidth <= 7000000)) { + channel->bandwidth = + DRX_BANDWIDTH_7MHZ; + } else if (bandwidth > 7000000) { + channel->bandwidth = + DRX_BANDWIDTH_8MHZ; + } + } /* if (standard == DRX_STANDARD_ITU_B) */ + + { + DRXJSCUCmd_t cmdSCU = + { /* command */ 0, + /* parameterLen */ 0, + /* resultLen */ 0, + /* parameter */ NULL, + /* result */ NULL + }; + u16_t cmdResult[3] = { 0, 0, 0 }; + + cmdSCU.command = + SCU_RAM_COMMAND_STANDARD_QAM | + SCU_RAM_COMMAND_CMD_DEMOD_GET_PARAM; + cmdSCU.parameterLen = 0; + cmdSCU.resultLen = 3; + cmdSCU.parameter = NULL; + cmdSCU.result = cmdResult; + CHK_ERROR(SCUCommand(devAddr, &cmdSCU)); + + channel->interleavemode = + (DRXInterleaveModes_t) (cmdSCU. + result[2]); + } + + switch (extAttr->constellation) { + case DRX_CONSTELLATION_QAM256: + channel->constellation = + DRX_CONSTELLATION_QAM256; + break; + case DRX_CONSTELLATION_QAM128: + channel->constellation = + DRX_CONSTELLATION_QAM128; + break; + case DRX_CONSTELLATION_QAM64: + channel->constellation = + DRX_CONSTELLATION_QAM64; + break; + case DRX_CONSTELLATION_QAM32: + channel->constellation = + DRX_CONSTELLATION_QAM32; + break; + case DRX_CONSTELLATION_QAM16: + channel->constellation = + DRX_CONSTELLATION_QAM16; + break; + default: + channel->constellation = + DRX_CONSTELLATION_UNKNOWN; + return (DRX_STS_ERROR); + } + } + break; #endif #ifndef DRXJ_DIGITAL_ONLY - case DRX_STANDARD_NTSC: /* fall trough */ - case DRX_STANDARD_PAL_SECAM_BG: - case DRX_STANDARD_PAL_SECAM_DK: - case DRX_STANDARD_PAL_SECAM_I: - case DRX_STANDARD_PAL_SECAM_L: - case DRX_STANDARD_PAL_SECAM_LP: - case DRX_STANDARD_FM: - CHK_ERROR( GetATVChannel(demod, channel, standard)); - break; + case DRX_STANDARD_NTSC: /* fall trough */ + case DRX_STANDARD_PAL_SECAM_BG: + case DRX_STANDARD_PAL_SECAM_DK: + case DRX_STANDARD_PAL_SECAM_I: + case DRX_STANDARD_PAL_SECAM_L: + case DRX_STANDARD_PAL_SECAM_LP: + case DRX_STANDARD_FM: + CHK_ERROR(GetATVChannel(demod, channel, standard)); + break; #endif - case DRX_STANDARD_UNKNOWN: /* fall trough */ - default: - return (DRX_STS_ERROR); - } /* switch ( standard ) */ - - if (lockStatus == DRX_LOCKED) - { - channel->mirror = extAttr->mirror; - } - } /* if ( lockStatus == DRX_LOCKED ) */ - - return (DRX_STS_OK); + case DRX_STANDARD_UNKNOWN: /* fall trough */ + default: + return (DRX_STS_ERROR); + } /* switch ( standard ) */ + + if (lockStatus == DRX_LOCKED) { + channel->mirror = extAttr->mirror; + } + } + /* if ( lockStatus == DRX_LOCKED ) */ + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /*============================================================================= @@ -14159,43 +13500,32 @@ rw_error: ===========================================================================*/ static u16_t -mer2indicator ( - u16_t mer, - u16_t minMer, - u16_t thresholdMer, - u16_t maxMer) -{ - u16_t indicator = 0; - - if ( mer < minMer ) - { - indicator = 0; - } - else if ( mer < thresholdMer ) - { - if ((thresholdMer - minMer) != 0) - { - indicator = 25 * (mer - minMer) / (thresholdMer - minMer); - } - } - else if ( mer < maxMer ) - { - if ((maxMer - thresholdMer) != 0) - { - indicator = 25 + 75 * (mer - thresholdMer) / (maxMer - thresholdMer); - } - else - { - indicator = 25; - } - } - else - { - indicator = 100; - } +mer2indicator(u16_t mer, u16_t minMer, u16_t thresholdMer, u16_t maxMer) +{ + u16_t indicator = 0; + + if (mer < minMer) { + indicator = 0; + } else if (mer < thresholdMer) { + if ((thresholdMer - minMer) != 0) { + indicator = + 25 * (mer - minMer) / (thresholdMer - minMer); + } + } else if (mer < maxMer) { + if ((maxMer - thresholdMer) != 0) { + indicator = + 25 + 75 * (mer - thresholdMer) / (maxMer - + thresholdMer); + } else { + indicator = 25; + } + } else { + indicator = 100; + } - return indicator; + return indicator; } + /** * \fn DRXStatus_t CtrlSigQuality() * \brief Retreive signal quality form device. @@ -14208,127 +13538,127 @@ mer2indicator ( */ static DRXStatus_t -CtrlSigQuality( pDRXDemodInstance_t demod, - pDRXSigQuality_t sigQuality ) +CtrlSigQuality(pDRXDemodInstance_t demod, pDRXSigQuality_t sigQuality) { - pI2CDeviceAddr_t devAddr = NULL; - pDRXJData_t extAttr = NULL; - DRXStandard_t standard = DRX_STANDARD_UNKNOWN; - DRXLockStatus_t lockStatus = DRX_NOT_LOCKED; - u16_t minMer = 0; - u16_t maxMer = 0; - u16_t thresholdMer = 0; - - /* Check arguments */ - if (( sigQuality == NULL ) || - ( demod == NULL )) - { - return (DRX_STS_INVALID_ARG); - } + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + DRXStandard_t standard = DRX_STANDARD_UNKNOWN; + DRXLockStatus_t lockStatus = DRX_NOT_LOCKED; + u16_t minMer = 0; + u16_t maxMer = 0; + u16_t thresholdMer = 0; + + /* Check arguments */ + if ((sigQuality == NULL) || (demod == NULL)) { + return (DRX_STS_INVALID_ARG); + } - extAttr = (pDRXJData_t)demod->myExtAttr; - standard = extAttr->standard; + extAttr = (pDRXJData_t) demod->myExtAttr; + standard = extAttr->standard; - /* get basic information */ - devAddr = demod -> myI2CDevAddr; - CHK_ERROR( CtrlLockStatus( demod, &lockStatus) ); - switch ( standard ) { - case DRX_STANDARD_8VSB: + /* get basic information */ + devAddr = demod->myI2CDevAddr; + CHK_ERROR(CtrlLockStatus(demod, &lockStatus)); + switch (standard) { + case DRX_STANDARD_8VSB: #ifdef DRXJ_SIGNAL_ACCUM_ERR - CHK_ERROR (GetAccPktErr (demod, &sigQuality->packetError)); + CHK_ERROR(GetAccPktErr(demod, &sigQuality->packetError)); #else - CHK_ERROR (GetVSBPostRSPckErr (devAddr, &sigQuality->packetError)); + CHK_ERROR(GetVSBPostRSPckErr + (devAddr, &sigQuality->packetError)); #endif - if ( lockStatus != DRXJ_DEMOD_LOCK && lockStatus != DRX_LOCKED ) - { - sigQuality->postViterbiBER = 500000; - sigQuality->MER = 20; - sigQuality->preViterbiBER = 0; - } else { - /* PostViterbi is compute in steps of 10^(-6) */ - CHK_ERROR (GetVSBpreViterbiBer (devAddr, &sigQuality->preViterbiBER)); - CHK_ERROR (GetVSBpostViterbiBer (devAddr, &sigQuality->postViterbiBER)); - CHK_ERROR (GetVSBMER (devAddr, &sigQuality->MER)); - } - minMer = 20; - maxMer = 360; - thresholdMer = 145; - sigQuality->postReedSolomonBER = 0; - sigQuality->scaleFactorBER = 1000000; - sigQuality->indicator = mer2indicator (sigQuality->MER, minMer, thresholdMer, maxMer); - break; + if (lockStatus != DRXJ_DEMOD_LOCK && lockStatus != DRX_LOCKED) { + sigQuality->postViterbiBER = 500000; + sigQuality->MER = 20; + sigQuality->preViterbiBER = 0; + } else { + /* PostViterbi is compute in steps of 10^(-6) */ + CHK_ERROR(GetVSBpreViterbiBer + (devAddr, &sigQuality->preViterbiBER)); + CHK_ERROR(GetVSBpostViterbiBer + (devAddr, &sigQuality->postViterbiBER)); + CHK_ERROR(GetVSBMER(devAddr, &sigQuality->MER)); + } + minMer = 20; + maxMer = 360; + thresholdMer = 145; + sigQuality->postReedSolomonBER = 0; + sigQuality->scaleFactorBER = 1000000; + sigQuality->indicator = + mer2indicator(sigQuality->MER, minMer, thresholdMer, + maxMer); + break; #ifndef DRXJ_VSB_ONLY - case DRX_STANDARD_ITU_A: - case DRX_STANDARD_ITU_B: - case DRX_STANDARD_ITU_C: - CHK_ERROR ( CtrlGetQAMSigQuality ( demod, sigQuality ) ); - if ( lockStatus != DRXJ_DEMOD_LOCK && lockStatus != DRX_LOCKED ) - { - switch ( extAttr->constellation ) - { - case DRX_CONSTELLATION_QAM256: - sigQuality->MER = 210; - break; - case DRX_CONSTELLATION_QAM128: - sigQuality->MER = 180; - break; - case DRX_CONSTELLATION_QAM64: - sigQuality->MER = 150; - break; - case DRX_CONSTELLATION_QAM32: - sigQuality->MER = 120; - break; - case DRX_CONSTELLATION_QAM16: - sigQuality->MER = 90; - break; - default: - sigQuality->MER = 0; - return (DRX_STS_ERROR); - } - } - - switch ( extAttr->constellation ) - { - case DRX_CONSTELLATION_QAM256: - minMer = 210; - thresholdMer = 270; - maxMer = 380; - break; - case DRX_CONSTELLATION_QAM64: - minMer = 150; - thresholdMer = 210; - maxMer = 380; - break; - case DRX_CONSTELLATION_QAM128: - case DRX_CONSTELLATION_QAM32: - case DRX_CONSTELLATION_QAM16: - break; - default: - return (DRX_STS_ERROR); - } - sigQuality->indicator = mer2indicator (sigQuality->MER, minMer, thresholdMer, maxMer); - break; + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: + CHK_ERROR(CtrlGetQAMSigQuality(demod, sigQuality)); + if (lockStatus != DRXJ_DEMOD_LOCK && lockStatus != DRX_LOCKED) { + switch (extAttr->constellation) { + case DRX_CONSTELLATION_QAM256: + sigQuality->MER = 210; + break; + case DRX_CONSTELLATION_QAM128: + sigQuality->MER = 180; + break; + case DRX_CONSTELLATION_QAM64: + sigQuality->MER = 150; + break; + case DRX_CONSTELLATION_QAM32: + sigQuality->MER = 120; + break; + case DRX_CONSTELLATION_QAM16: + sigQuality->MER = 90; + break; + default: + sigQuality->MER = 0; + return (DRX_STS_ERROR); + } + } + + switch (extAttr->constellation) { + case DRX_CONSTELLATION_QAM256: + minMer = 210; + thresholdMer = 270; + maxMer = 380; + break; + case DRX_CONSTELLATION_QAM64: + minMer = 150; + thresholdMer = 210; + maxMer = 380; + break; + case DRX_CONSTELLATION_QAM128: + case DRX_CONSTELLATION_QAM32: + case DRX_CONSTELLATION_QAM16: + break; + default: + return (DRX_STS_ERROR); + } + sigQuality->indicator = + mer2indicator(sigQuality->MER, minMer, thresholdMer, + maxMer); + break; #endif #ifndef DRXJ_DIGITAL_ONLY - case DRX_STANDARD_PAL_SECAM_BG: - case DRX_STANDARD_PAL_SECAM_DK: - case DRX_STANDARD_PAL_SECAM_I: - case DRX_STANDARD_PAL_SECAM_L: - case DRX_STANDARD_PAL_SECAM_LP: - case DRX_STANDARD_NTSC: - CHK_ERROR ( AtvSigQuality ( demod, sigQuality ) ); - break; - case DRX_STANDARD_FM: - CHK_ERROR ( FmSigQuality ( demod, sigQuality ) ); - break; + case DRX_STANDARD_PAL_SECAM_BG: + case DRX_STANDARD_PAL_SECAM_DK: + case DRX_STANDARD_PAL_SECAM_I: + case DRX_STANDARD_PAL_SECAM_L: + case DRX_STANDARD_PAL_SECAM_LP: + case DRX_STANDARD_NTSC: + CHK_ERROR(AtvSigQuality(demod, sigQuality)); + break; + case DRX_STANDARD_FM: + CHK_ERROR(FmSigQuality(demod, sigQuality)); + break; #endif - default: - return (DRX_STS_ERROR); - } + default: + return (DRX_STS_ERROR); + } - return (DRX_STS_OK); + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /*============================================================================*/ @@ -14342,98 +13672,90 @@ rw_error: * */ static DRXStatus_t -CtrlLockStatus( pDRXDemodInstance_t demod, - pDRXLockStatus_t lockStat ) +CtrlLockStatus(pDRXDemodInstance_t demod, pDRXLockStatus_t lockStat) { - DRXStandard_t standard = DRX_STANDARD_UNKNOWN; - pDRXJData_t extAttr = NULL; - pI2CDeviceAddr_t devAddr = NULL; - DRXJSCUCmd_t cmdSCU = { /* command */ 0, - /* parameterLen */ 0, - /* resultLen */ 0, - /* *parameter */ NULL, - /* *result */ NULL }; - u16_t cmdResult[2] = { 0, 0 }; - u16_t demodLock = SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_DEMOD_LOCKED; - - /* check arguments */ - if ( ( demod == NULL ) || - ( lockStat == NULL ) ) - { - return (DRX_STS_INVALID_ARG); - } - - devAddr = demod -> myI2CDevAddr; - extAttr = (pDRXJData_t)demod->myExtAttr; - standard = extAttr->standard; - - *lockStat = DRX_NOT_LOCKED; - - /* define the SCU command code */ - switch ( standard ) { - case DRX_STANDARD_8VSB: - cmdSCU.command = SCU_RAM_COMMAND_STANDARD_VSB | - SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK; - demodLock |= 0x6; - break; + DRXStandard_t standard = DRX_STANDARD_UNKNOWN; + pDRXJData_t extAttr = NULL; + pI2CDeviceAddr_t devAddr = NULL; + DRXJSCUCmd_t cmdSCU = { /* command */ 0, + /* parameterLen */ 0, + /* resultLen */ 0, + /* *parameter */ NULL, + /* *result */ NULL + }; + u16_t cmdResult[2] = { 0, 0 }; + u16_t demodLock = SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_DEMOD_LOCKED; + + /* check arguments */ + if ((demod == NULL) || (lockStat == NULL)) { + return (DRX_STS_INVALID_ARG); + } + + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; + standard = extAttr->standard; + + *lockStat = DRX_NOT_LOCKED; + + /* define the SCU command code */ + switch (standard) { + case DRX_STANDARD_8VSB: + cmdSCU.command = SCU_RAM_COMMAND_STANDARD_VSB | + SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK; + demodLock |= 0x6; + break; #ifndef DRXJ_VSB_ONLY - case DRX_STANDARD_ITU_A: - case DRX_STANDARD_ITU_B: - case DRX_STANDARD_ITU_C: - cmdSCU.command = SCU_RAM_COMMAND_STANDARD_QAM | - SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK; - break; + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: + cmdSCU.command = SCU_RAM_COMMAND_STANDARD_QAM | + SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK; + break; #endif #ifndef DRXJ_DIGITAL_ONLY - case DRX_STANDARD_NTSC: - case DRX_STANDARD_PAL_SECAM_BG: - case DRX_STANDARD_PAL_SECAM_DK: - case DRX_STANDARD_PAL_SECAM_I: - case DRX_STANDARD_PAL_SECAM_L: - case DRX_STANDARD_PAL_SECAM_LP: - cmdSCU.command = SCU_RAM_COMMAND_STANDARD_ATV | - SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK; - break; - case DRX_STANDARD_FM: - return FmLockStatus( demod, lockStat); + case DRX_STANDARD_NTSC: + case DRX_STANDARD_PAL_SECAM_BG: + case DRX_STANDARD_PAL_SECAM_DK: + case DRX_STANDARD_PAL_SECAM_I: + case DRX_STANDARD_PAL_SECAM_L: + case DRX_STANDARD_PAL_SECAM_LP: + cmdSCU.command = SCU_RAM_COMMAND_STANDARD_ATV | + SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK; + break; + case DRX_STANDARD_FM: + return FmLockStatus(demod, lockStat); #endif - case DRX_STANDARD_UNKNOWN: /* fallthrough */ - default: - return (DRX_STS_ERROR); - } - - /* define the SCU command paramters and execute the command */ - cmdSCU.parameterLen = 0; - cmdSCU.resultLen = 2; - cmdSCU.parameter = NULL; - cmdSCU.result = cmdResult; - CHK_ERROR( SCUCommand( devAddr, &cmdSCU ) ); - - /* set the lock status */ - if ( cmdSCU.result[1] < demodLock ) - { - /* 0x0000 NOT LOCKED */ - *lockStat = DRX_NOT_LOCKED; - } - else if ( cmdSCU.result[1] < SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_LOCKED ) - { - *lockStat = DRXJ_DEMOD_LOCK; - } - else if ( cmdSCU.result[1] < SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NEVER_LOCK ) - { - /* 0x8000 DEMOD + FEC LOCKED (system lock) */ - *lockStat = DRX_LOCKED; - } - else - { - /* 0xC000 NEVER LOCKED */ - /* (system will never be able to lock to the signal) */ - *lockStat = DRX_NEVER_LOCK; - } + case DRX_STANDARD_UNKNOWN: /* fallthrough */ + default: + return (DRX_STS_ERROR); + } + + /* define the SCU command paramters and execute the command */ + cmdSCU.parameterLen = 0; + cmdSCU.resultLen = 2; + cmdSCU.parameter = NULL; + cmdSCU.result = cmdResult; + CHK_ERROR(SCUCommand(devAddr, &cmdSCU)); + + /* set the lock status */ + if (cmdSCU.result[1] < demodLock) { + /* 0x0000 NOT LOCKED */ + *lockStat = DRX_NOT_LOCKED; + } else if (cmdSCU.result[1] < SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_LOCKED) { + *lockStat = DRXJ_DEMOD_LOCK; + } else if (cmdSCU.result[1] < + SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NEVER_LOCK) { + /* 0x8000 DEMOD + FEC LOCKED (system lock) */ + *lockStat = DRX_LOCKED; + } else { + /* 0xC000 NEVER LOCKED */ + /* (system will never be able to lock to the signal) */ + *lockStat = DRX_NEVER_LOCK; + } - return (DRX_STS_OK); + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /*============================================================================*/ @@ -14447,41 +13769,39 @@ rw_error: * \return DRXStatus_t. */ static DRXStatus_t -CtrlConstel( pDRXDemodInstance_t demod, - pDRXComplex_t complexNr ) +CtrlConstel(pDRXDemodInstance_t demod, pDRXComplex_t complexNr) { - DRXStandard_t standard = DRX_STANDARD_UNKNOWN; /**< active standard */ + DRXStandard_t standard = DRX_STANDARD_UNKNOWN; + /**< active standard */ - /* check arguments */ - if ( ( demod == NULL ) || - ( complexNr == NULL ) ) - { - return (DRX_STS_INVALID_ARG); - } + /* check arguments */ + if ((demod == NULL) || (complexNr == NULL)) { + return (DRX_STS_INVALID_ARG); + } - /* read device info */ - standard = ((pDRXJData_t)demod->myExtAttr)->standard; + /* read device info */ + standard = ((pDRXJData_t) demod->myExtAttr)->standard; - /* Read constellation point */ - switch ( standard ) { - case DRX_STANDARD_8VSB: - CHK_ERROR( CtrlGetVSBConstel( demod, complexNr ) ); - break; + /* Read constellation point */ + switch (standard) { + case DRX_STANDARD_8VSB: + CHK_ERROR(CtrlGetVSBConstel(demod, complexNr)); + break; #ifndef DRXJ_VSB_ONLY - case DRX_STANDARD_ITU_A: /* fallthrough */ - case DRX_STANDARD_ITU_B: /* fallthrough */ - case DRX_STANDARD_ITU_C: - CHK_ERROR( CtrlGetQAMConstel( demod, complexNr ) ); - break; + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: + CHK_ERROR(CtrlGetQAMConstel(demod, complexNr)); + break; #endif - case DRX_STANDARD_UNKNOWN: - default: - return (DRX_STS_ERROR); - } - - return (DRX_STS_OK); - rw_error: - return (DRX_STS_ERROR); + case DRX_STANDARD_UNKNOWN: + default: + return (DRX_STS_ERROR); + } + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); } /*============================================================================*/ @@ -14497,96 +13817,92 @@ CtrlConstel( pDRXDemodInstance_t demod, * */ static DRXStatus_t -CtrlSetStandard( pDRXDemodInstance_t demod, pDRXStandard_t standard ) +CtrlSetStandard(pDRXDemodInstance_t demod, pDRXStandard_t standard) { - pDRXJData_t extAttr = NULL; - DRXStandard_t prevStandard; + pDRXJData_t extAttr = NULL; + DRXStandard_t prevStandard; - /* check arguments */ - if (( standard == NULL ) || - ( demod == NULL )) - { - return (DRX_STS_INVALID_ARG); - } + /* check arguments */ + if ((standard == NULL) || (demod == NULL)) { + return (DRX_STS_INVALID_ARG); + } - extAttr = (pDRXJData_t)demod->myExtAttr; - prevStandard=extAttr->standard; + extAttr = (pDRXJData_t) demod->myExtAttr; + prevStandard = extAttr->standard; - /* - Stop and power down previous standard - */ - switch ( prevStandard ) - { + /* + Stop and power down previous standard + */ + switch (prevStandard) { #ifndef DRXJ_VSB_ONLY - case DRX_STANDARD_ITU_A: /* fallthrough */ - case DRX_STANDARD_ITU_B: /* fallthrough */ - case DRX_STANDARD_ITU_C: - CHK_ERROR( PowerDownQAM(demod, FALSE) ); - break; + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: + CHK_ERROR(PowerDownQAM(demod, FALSE)); + break; #endif - case DRX_STANDARD_8VSB: - CHK_ERROR( PowerDownVSB(demod, FALSE) ); - break; + case DRX_STANDARD_8VSB: + CHK_ERROR(PowerDownVSB(demod, FALSE)); + break; #ifndef DRXJ_DIGITAL_ONLY - case DRX_STANDARD_NTSC: /* fallthrough */ - case DRX_STANDARD_FM: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_LP: - CHK_ERROR( PowerDownATV( demod, prevStandard, FALSE )); - break; + case DRX_STANDARD_NTSC: /* fallthrough */ + case DRX_STANDARD_FM: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_LP: + CHK_ERROR(PowerDownATV(demod, prevStandard, FALSE)); + break; #endif - case DRX_STANDARD_UNKNOWN: - /* Do nothing */ - break; - case DRX_STANDARD_AUTO: /* fallthrough */ - default: - return ( DRX_STS_INVALID_ARG ); - } - - /* - Initialize channel independent registers - Power up new standard - */ - extAttr->standard=*standard; - - switch ( *standard ) - { + case DRX_STANDARD_UNKNOWN: + /* Do nothing */ + break; + case DRX_STANDARD_AUTO: /* fallthrough */ + default: + return (DRX_STS_INVALID_ARG); + } + + /* + Initialize channel independent registers + Power up new standard + */ + extAttr->standard = *standard; + + switch (*standard) { #ifndef DRXJ_VSB_ONLY - case DRX_STANDARD_ITU_A: /* fallthrough */ - case DRX_STANDARD_ITU_B: /* fallthrough */ - case DRX_STANDARD_ITU_C: - DUMMY_READ(); - break; + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: + DUMMY_READ(); + break; #endif - case DRX_STANDARD_8VSB: - CHK_ERROR(SetVSBLeakNGain(demod)); - break; + case DRX_STANDARD_8VSB: + CHK_ERROR(SetVSBLeakNGain(demod)); + break; #ifndef DRXJ_DIGITAL_ONLY - case DRX_STANDARD_NTSC: /* fallthrough */ - case DRX_STANDARD_FM: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_LP: - CHK_ERROR( SetATVStandard( demod, standard )); - CHK_ERROR( PowerUpATV( demod, *standard )); - break; + case DRX_STANDARD_NTSC: /* fallthrough */ + case DRX_STANDARD_FM: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_LP: + CHK_ERROR(SetATVStandard(demod, standard)); + CHK_ERROR(PowerUpATV(demod, *standard)); + break; #endif - default: - extAttr->standard=DRX_STANDARD_UNKNOWN; - return ( DRX_STS_INVALID_ARG ); - break; - } + default: + extAttr->standard = DRX_STANDARD_UNKNOWN; + return (DRX_STS_INVALID_ARG); + break; + } - return (DRX_STS_OK); + return (DRX_STS_OK); rw_error: - /* Don't know what the standard is now ... try again */ - extAttr->standard=DRX_STANDARD_UNKNOWN; - return (DRX_STS_ERROR); + /* Don't know what the standard is now ... try again */ + extAttr->standard = DRX_STANDARD_UNKNOWN; + return (DRX_STS_ERROR); } /*============================================================================*/ @@ -14601,22 +13917,21 @@ rw_error: * */ static DRXStatus_t -CtrlGetStandard( pDRXDemodInstance_t demod, pDRXStandard_t standard ) +CtrlGetStandard(pDRXDemodInstance_t demod, pDRXStandard_t standard) { - pDRXJData_t extAttr = NULL; - extAttr = (pDRXJData_t)demod->myExtAttr; + pDRXJData_t extAttr = NULL; + extAttr = (pDRXJData_t) demod->myExtAttr; - /* check arguments */ - if ( standard == NULL ) - { - return (DRX_STS_INVALID_ARG); - } - (*standard) = extAttr->standard; - DUMMY_READ(); + /* check arguments */ + if (standard == NULL) { + return (DRX_STS_INVALID_ARG); + } + (*standard) = extAttr->standard; + DUMMY_READ(); - return ( DRX_STS_OK ); + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /*============================================================================*/ @@ -14629,42 +13944,41 @@ rw_error: * */ static DRXStatus_t -CtrlGetCfgSymbolClockOffset ( pDRXDemodInstance_t demod, - ps32_t rateOffset ) +CtrlGetCfgSymbolClockOffset(pDRXDemodInstance_t demod, ps32_t rateOffset) { - DRXStandard_t standard = DRX_STANDARD_UNKNOWN; - pI2CDeviceAddr_t devAddr = NULL; - pDRXJData_t extAttr = NULL; + DRXStandard_t standard = DRX_STANDARD_UNKNOWN; + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; - /* check arguments */ - if ( rateOffset == NULL ) - { - return (DRX_STS_INVALID_ARG); - } + /* check arguments */ + if (rateOffset == NULL) { + return (DRX_STS_INVALID_ARG); + } - devAddr = demod -> myI2CDevAddr; - extAttr = (pDRXJData_t)demod->myExtAttr; - standard = extAttr->standard; + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; + standard = extAttr->standard; - switch ( standard ) { - case DRX_STANDARD_8VSB: /* fallthrough */ + switch (standard) { + case DRX_STANDARD_8VSB: /* fallthrough */ #ifndef DRXJ_VSB_ONLY - case DRX_STANDARD_ITU_A: /* fallthrough */ - case DRX_STANDARD_ITU_B: /* fallthrough */ - case DRX_STANDARD_ITU_C: + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: #endif - CHK_ERROR ( GetSTRFreqOffset ( demod, rateOffset )); - break; - case DRX_STANDARD_NTSC: - case DRX_STANDARD_UNKNOWN: - default: - return (DRX_STS_INVALID_ARG); - } - - return ( DRX_STS_OK ); + CHK_ERROR(GetSTRFreqOffset(demod, rateOffset)); + break; + case DRX_STANDARD_NTSC: + case DRX_STANDARD_UNKNOWN: + default: + return (DRX_STS_INVALID_ARG); + } + + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } + /*============================================================================*/ /** @@ -14680,118 +13994,109 @@ rw_error: * */ static DRXStatus_t -CtrlPowerMode( pDRXDemodInstance_t demod, - pDRXPowerMode_t mode ) +CtrlPowerMode(pDRXDemodInstance_t demod, pDRXPowerMode_t mode) { - pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t)NULL; - pDRXJData_t extAttr = (pDRXJData_t)NULL; - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)NULL; - u16_t sioCcPwdMode = 0; + pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) NULL; + pDRXJData_t extAttr = (pDRXJData_t) NULL; + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) NULL; + u16_t sioCcPwdMode = 0; - commonAttr = (pDRXCommonAttr_t)demod -> myCommonAttr; - extAttr = (pDRXJData_t)demod->myExtAttr; - devAddr = demod -> myI2CDevAddr; + commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; + extAttr = (pDRXJData_t) demod->myExtAttr; + devAddr = demod->myI2CDevAddr; - /* Check arguments */ - if ( mode == NULL ) - { - return (DRX_STS_INVALID_ARG); - } + /* Check arguments */ + if (mode == NULL) { + return (DRX_STS_INVALID_ARG); + } - /* If already in requested power mode, do nothing */ - if ( commonAttr->currentPowerMode == *mode ) - { - return (DRX_STS_OK); - } + /* If already in requested power mode, do nothing */ + if (commonAttr->currentPowerMode == *mode) { + return (DRX_STS_OK); + } - switch ( *mode ) - { - case DRX_POWER_UP: - case DRXJ_POWER_DOWN_MAIN_PATH: - sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_NONE; - break; - case DRXJ_POWER_DOWN_CORE: - sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_CLOCK; - break; - case DRXJ_POWER_DOWN_PLL: - sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_PLL; - break; - case DRX_POWER_DOWN: - sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OSC; - break; - default: - /* Unknow sleep mode */ - return (DRX_STS_INVALID_ARG); - break; - } - - - /* Check if device needs to be powered up */ - if ( ( commonAttr->currentPowerMode != DRX_POWER_UP ) ) - { - CHK_ERROR(PowerUpDevice(demod)); - } + switch (*mode) { + case DRX_POWER_UP: + case DRXJ_POWER_DOWN_MAIN_PATH: + sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_NONE; + break; + case DRXJ_POWER_DOWN_CORE: + sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_CLOCK; + break; + case DRXJ_POWER_DOWN_PLL: + sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_PLL; + break; + case DRX_POWER_DOWN: + sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OSC; + break; + default: + /* Unknow sleep mode */ + return (DRX_STS_INVALID_ARG); + break; + } - if ( ( *mode == DRX_POWER_UP ) ) - { - /* Restore analog & pin configuartion */ - } else { - /* Power down to requested mode */ - /* Backup some register settings */ - /* Set pins with possible pull-ups connected to them in input mode */ - /* Analog power down */ - /* ADC power down */ - /* Power down device */ - /* stop all comm_exec */ - /* - Stop and power down previous standard - */ - - switch ( extAttr->standard ) - { - case DRX_STANDARD_ITU_A: - case DRX_STANDARD_ITU_B: - case DRX_STANDARD_ITU_C: - CHK_ERROR( PowerDownQAM(demod, TRUE) ); - break; - case DRX_STANDARD_8VSB: - CHK_ERROR( PowerDownVSB(demod, TRUE) ); - break; - case DRX_STANDARD_PAL_SECAM_BG : /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_DK : /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_I : /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_L : /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_LP : /* fallthrough */ - case DRX_STANDARD_NTSC: /* fallthrough */ - case DRX_STANDARD_FM: - CHK_ERROR( PowerDownATV( demod, extAttr->standard, TRUE )); - break; - case DRX_STANDARD_UNKNOWN: - /* Do nothing */ - break; - case DRX_STANDARD_AUTO: /* fallthrough */ - default: - return ( DRX_STS_ERROR ); - } - - if (*mode != DRXJ_POWER_DOWN_MAIN_PATH) - { - WR16( devAddr, SIO_CC_PWD_MODE__A, sioCcPwdMode); - WR16( devAddr, SIO_CC_UPDATE__A , SIO_CC_UPDATE_KEY); - - /* Initialize HI, wakeup key especially before put IC to sleep */ - CHK_ERROR(InitHI(demod) ); - - extAttr -> HICfgCtrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; - CHK_ERROR( HICfgCommand( demod ) ); - } - } - - commonAttr->currentPowerMode = *mode; - - return ( DRX_STS_OK ); + /* Check if device needs to be powered up */ + if ((commonAttr->currentPowerMode != DRX_POWER_UP)) { + CHK_ERROR(PowerUpDevice(demod)); + } + + if ((*mode == DRX_POWER_UP)) { + /* Restore analog & pin configuartion */ + } else { + /* Power down to requested mode */ + /* Backup some register settings */ + /* Set pins with possible pull-ups connected to them in input mode */ + /* Analog power down */ + /* ADC power down */ + /* Power down device */ + /* stop all comm_exec */ + /* + Stop and power down previous standard + */ + + switch (extAttr->standard) { + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: + CHK_ERROR(PowerDownQAM(demod, TRUE)); + break; + case DRX_STANDARD_8VSB: + CHK_ERROR(PowerDownVSB(demod, TRUE)); + break; + case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_LP: /* fallthrough */ + case DRX_STANDARD_NTSC: /* fallthrough */ + case DRX_STANDARD_FM: + CHK_ERROR(PowerDownATV(demod, extAttr->standard, TRUE)); + break; + case DRX_STANDARD_UNKNOWN: + /* Do nothing */ + break; + case DRX_STANDARD_AUTO: /* fallthrough */ + default: + return (DRX_STS_ERROR); + } + + if (*mode != DRXJ_POWER_DOWN_MAIN_PATH) { + WR16(devAddr, SIO_CC_PWD_MODE__A, sioCcPwdMode); + WR16(devAddr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); + + /* Initialize HI, wakeup key especially before put IC to sleep */ + CHK_ERROR(InitHI(demod)); + + extAttr->HICfgCtrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; + CHK_ERROR(HICfgCommand(demod)); + } + } + + commonAttr->currentPowerMode = *mode; + + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /*============================================================================*/ @@ -14817,150 +14122,139 @@ rw_error: * */ static DRXStatus_t -CtrlVersion( pDRXDemodInstance_t demod, - pDRXVersionList_t *versionList ) -{ - pDRXJData_t extAttr = (pDRXJData_t) (NULL); - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) (NULL); - pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t)(NULL); - u16_t ucodeMajorMinor = 0; /* BCD Ma:Ma:Ma:Mi */ - u16_t ucodePatch = 0; /* BCD Pa:Pa:Pa:Pa */ - u16_t major = 0; - u16_t minor = 0; - u16_t patch = 0; - u16_t idx = 0; - u32_t jtag = 0; - u16_t subtype = 0; - u16_t mfx = 0; - u16_t bid = 0; - u16_t key = 0; - - static char ucodeName[] = "Microcode"; - static char deviceName[] = "Device"; - - devAddr = demod -> myI2CDevAddr; - extAttr = (pDRXJData_t)demod -> myExtAttr; - commonAttr = (pDRXCommonAttr_t)demod->myCommonAttr; - - /* Microcode version ****************************************/ - - extAttr->vVersion[0].moduleType = DRX_MODULE_MICROCODE; - extAttr->vVersion[0].moduleName = ucodeName; - extAttr->vVersion[0].vString = extAttr->vText[0]; - - if ( commonAttr->isOpened == TRUE ) - { - SARR16( devAddr, SCU_RAM_VERSION_HI__A, &ucodeMajorMinor ); - SARR16( devAddr, SCU_RAM_VERSION_LO__A, &ucodePatch ); - - /* Translate BCD to numbers and string */ - /* TODO: The most significant Ma and Pa will be ignored, check with spec */ - minor = (ucodeMajorMinor & 0xF); - ucodeMajorMinor >>= 4; - major = (ucodeMajorMinor & 0xF); - ucodeMajorMinor >>= 4; - major += (10* (ucodeMajorMinor & 0xF)); - patch = (ucodePatch & 0xF); - ucodePatch >>= 4; - patch += (10*(ucodePatch & 0xF)); - ucodePatch >>= 4; - patch += (100*(ucodePatch & 0xF)); - } - else - { - /* No microcode uploaded, No Rom existed, set version to 0.0.0 */ - patch = 0; - minor = 0; - major = 0; - } - extAttr->vVersion[0].vMajor = major; - extAttr->vVersion[0].vMinor = minor; - extAttr->vVersion[0].vPatch = patch; - - if ( major/10 != 0 ) - { - extAttr->vVersion[0].vString[idx++] = ((char)(major/10))+'0'; - major %= 10; - } - extAttr->vVersion[0].vString[idx++] = ((char)major)+'0'; - extAttr->vVersion[0].vString[idx++] = '.'; - extAttr->vVersion[0].vString[idx++] = ((char)minor)+'0'; - extAttr->vVersion[0].vString[idx++] = '.'; - if ( patch/100 != 0 ) - { - extAttr->vVersion[0].vString[idx++] = ((char)(patch/100))+'0'; - patch %= 100; - } - if ( patch/10 != 0 ) - { - extAttr->vVersion[0].vString[idx++] = ((char)(patch/10))+'0'; - patch %= 10; - } - extAttr->vVersion[0].vString[idx++] = ((char)patch)+'0'; - extAttr->vVersion[0].vString[idx] = '\0'; - - extAttr->vListElements[0].version = &(extAttr->vVersion[0]); - extAttr->vListElements[0].next = &(extAttr->vListElements[1]); - - - /* Device version ****************************************/ - /* Check device id */ - RR16( devAddr, SIO_TOP_COMM_KEY__A , &key); - WR16( devAddr, SIO_TOP_COMM_KEY__A , 0xFABA); - RR32( devAddr, SIO_TOP_JTAGID_LO__A , &jtag ); - RR16( devAddr, SIO_PDR_UIO_IN_HI__A , &bid); - WR16( devAddr, SIO_TOP_COMM_KEY__A , key); - - extAttr->vVersion[1].moduleType = DRX_MODULE_DEVICE; - extAttr->vVersion[1].moduleName = deviceName; - extAttr->vVersion[1].vString = extAttr->vText[1]; - extAttr->vVersion[1].vString[0] = 'D'; - extAttr->vVersion[1].vString[1] = 'R'; - extAttr->vVersion[1].vString[2] = 'X'; - extAttr->vVersion[1].vString[3] = '3'; - extAttr->vVersion[1].vString[4] = '9'; - extAttr->vVersion[1].vString[7] = 'J'; - extAttr->vVersion[1].vString[8] = ':'; - extAttr->vVersion[1].vString[11] = '\0'; - - /* DRX39xxJ type Ax */ - /* TODO semantics of mfx and spin are unclear */ - subtype = (u16_t)((jtag>>12)&0xFF); - mfx = (u16_t)(jtag>>29); - extAttr->vVersion[1].vMinor = 1; - if (mfx == 0x03) - { - extAttr->vVersion[1].vPatch = mfx+2; - } - else - { - extAttr->vVersion[1].vPatch = mfx+1; - } - extAttr->vVersion[1].vString[6] = ((char)(subtype&0xF))+'0'; - extAttr->vVersion[1].vMajor = (subtype & 0x0F); - subtype>>=4; - extAttr->vVersion[1].vString[5] = ((char)(subtype&0xF))+'0'; - extAttr->vVersion[1].vMajor += 10*subtype; - extAttr->vVersion[1].vString[9] = 'A'; - if (mfx == 0x03) - { - extAttr->vVersion[1].vString[10] = ((char)(mfx&0xF)) + '2' ; - } - else - { - extAttr->vVersion[1].vString[10] = ((char)(mfx&0xF)) + '1' ; - } +CtrlVersion(pDRXDemodInstance_t demod, pDRXVersionList_t * versionList) +{ + pDRXJData_t extAttr = (pDRXJData_t) (NULL); + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) (NULL); + pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); + u16_t ucodeMajorMinor = 0; /* BCD Ma:Ma:Ma:Mi */ + u16_t ucodePatch = 0; /* BCD Pa:Pa:Pa:Pa */ + u16_t major = 0; + u16_t minor = 0; + u16_t patch = 0; + u16_t idx = 0; + u32_t jtag = 0; + u16_t subtype = 0; + u16_t mfx = 0; + u16_t bid = 0; + u16_t key = 0; + + static char ucodeName[] = "Microcode"; + static char deviceName[] = "Device"; + + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; + commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; + + /* Microcode version *************************************** */ + + extAttr->vVersion[0].moduleType = DRX_MODULE_MICROCODE; + extAttr->vVersion[0].moduleName = ucodeName; + extAttr->vVersion[0].vString = extAttr->vText[0]; + + if (commonAttr->isOpened == TRUE) { + SARR16(devAddr, SCU_RAM_VERSION_HI__A, &ucodeMajorMinor); + SARR16(devAddr, SCU_RAM_VERSION_LO__A, &ucodePatch); + + /* Translate BCD to numbers and string */ + /* TODO: The most significant Ma and Pa will be ignored, check with spec */ + minor = (ucodeMajorMinor & 0xF); + ucodeMajorMinor >>= 4; + major = (ucodeMajorMinor & 0xF); + ucodeMajorMinor >>= 4; + major += (10 * (ucodeMajorMinor & 0xF)); + patch = (ucodePatch & 0xF); + ucodePatch >>= 4; + patch += (10 * (ucodePatch & 0xF)); + ucodePatch >>= 4; + patch += (100 * (ucodePatch & 0xF)); + } else { + /* No microcode uploaded, No Rom existed, set version to 0.0.0 */ + patch = 0; + minor = 0; + major = 0; + } + extAttr->vVersion[0].vMajor = major; + extAttr->vVersion[0].vMinor = minor; + extAttr->vVersion[0].vPatch = patch; + + if (major / 10 != 0) { + extAttr->vVersion[0].vString[idx++] = + ((char)(major / 10)) + '0'; + major %= 10; + } + extAttr->vVersion[0].vString[idx++] = ((char)major) + '0'; + extAttr->vVersion[0].vString[idx++] = '.'; + extAttr->vVersion[0].vString[idx++] = ((char)minor) + '0'; + extAttr->vVersion[0].vString[idx++] = '.'; + if (patch / 100 != 0) { + extAttr->vVersion[0].vString[idx++] = + ((char)(patch / 100)) + '0'; + patch %= 100; + } + if (patch / 10 != 0) { + extAttr->vVersion[0].vString[idx++] = + ((char)(patch / 10)) + '0'; + patch %= 10; + } + extAttr->vVersion[0].vString[idx++] = ((char)patch) + '0'; + extAttr->vVersion[0].vString[idx] = '\0'; + + extAttr->vListElements[0].version = &(extAttr->vVersion[0]); + extAttr->vListElements[0].next = &(extAttr->vListElements[1]); + + /* Device version *************************************** */ + /* Check device id */ + RR16(devAddr, SIO_TOP_COMM_KEY__A, &key); + WR16(devAddr, SIO_TOP_COMM_KEY__A, 0xFABA); + RR32(devAddr, SIO_TOP_JTAGID_LO__A, &jtag); + RR16(devAddr, SIO_PDR_UIO_IN_HI__A, &bid); + WR16(devAddr, SIO_TOP_COMM_KEY__A, key); + + extAttr->vVersion[1].moduleType = DRX_MODULE_DEVICE; + extAttr->vVersion[1].moduleName = deviceName; + extAttr->vVersion[1].vString = extAttr->vText[1]; + extAttr->vVersion[1].vString[0] = 'D'; + extAttr->vVersion[1].vString[1] = 'R'; + extAttr->vVersion[1].vString[2] = 'X'; + extAttr->vVersion[1].vString[3] = '3'; + extAttr->vVersion[1].vString[4] = '9'; + extAttr->vVersion[1].vString[7] = 'J'; + extAttr->vVersion[1].vString[8] = ':'; + extAttr->vVersion[1].vString[11] = '\0'; + + /* DRX39xxJ type Ax */ + /* TODO semantics of mfx and spin are unclear */ + subtype = (u16_t) ((jtag >> 12) & 0xFF); + mfx = (u16_t) (jtag >> 29); + extAttr->vVersion[1].vMinor = 1; + if (mfx == 0x03) { + extAttr->vVersion[1].vPatch = mfx + 2; + } else { + extAttr->vVersion[1].vPatch = mfx + 1; + } + extAttr->vVersion[1].vString[6] = ((char)(subtype & 0xF)) + '0'; + extAttr->vVersion[1].vMajor = (subtype & 0x0F); + subtype >>= 4; + extAttr->vVersion[1].vString[5] = ((char)(subtype & 0xF)) + '0'; + extAttr->vVersion[1].vMajor += 10 * subtype; + extAttr->vVersion[1].vString[9] = 'A'; + if (mfx == 0x03) { + extAttr->vVersion[1].vString[10] = ((char)(mfx & 0xF)) + '2'; + } else { + extAttr->vVersion[1].vString[10] = ((char)(mfx & 0xF)) + '1'; + } - extAttr->vListElements[1].version = &(extAttr->vVersion[1]); - extAttr->vListElements[1].next = (pDRXVersionList_t)(NULL); + extAttr->vListElements[1].version = &(extAttr->vVersion[1]); + extAttr->vListElements[1].next = (pDRXVersionList_t) (NULL); - *versionList = &(extAttr->vListElements[0]); + *versionList = &(extAttr->vListElements[0]); - return ( DRX_STS_OK ); + return (DRX_STS_OK); - rw_error: - *versionList = (pDRXVersionList_t)(NULL); - return (DRX_STS_ERROR); +rw_error: + *versionList = (pDRXVersionList_t) (NULL); + return (DRX_STS_ERROR); } @@ -14978,77 +14272,70 @@ CtrlVersion( pDRXDemodInstance_t demod, * */ -static DRXStatus_t -CtrlProbeDevice( pDRXDemodInstance_t demod ) -{ - DRXPowerMode_t orgPowerMode = DRX_POWER_UP; - DRXStatus_t retStatus = DRX_STS_OK; - pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t)(NULL); - - commonAttr = (pDRXCommonAttr_t)demod -> myCommonAttr; - - if ( commonAttr->isOpened == FALSE || commonAttr->currentPowerMode != DRX_POWER_UP) - { - pI2CDeviceAddr_t devAddr = NULL; - DRXPowerMode_t powerMode = DRX_POWER_UP; - u32_t jtag = 0; - - devAddr = demod -> myI2CDevAddr; - - /* Remeber original power mode */ - orgPowerMode = commonAttr->currentPowerMode; - - if(demod->myCommonAttr->isOpened == FALSE) - { - CHK_ERROR(PowerUpDevice(demod)); - commonAttr->currentPowerMode = DRX_POWER_UP; - } - else - { - /* Wake-up device, feedback from device */ - CHK_ERROR( CtrlPowerMode( demod, &powerMode )); - } - /* Initialize HI, wakeup key especially */ - CHK_ERROR(InitHI(demod) ); - - /* Check device id */ - RR32( devAddr, SIO_TOP_JTAGID_LO__A , &jtag); - jtag = (jtag>>12) & 0xFFFF; - switch ( jtag ) - { - case 0x3931: /* fallthrough */ - case 0x3932: /* fallthrough */ - case 0x3933: /* fallthrough */ - case 0x3934: /* fallthrough */ - case 0x3941: /* fallthrough */ - case 0x3942: /* fallthrough */ - case 0x3943: /* fallthrough */ - case 0x3944: /* fallthrough */ - case 0x3945: /* fallthrough */ - case 0x3946: - /* ok , do nothing */ - break; - default: - retStatus = DRX_STS_ERROR; - break; - } - - /* Device was not opened, return to orginal powermode, - feedback from device */ - CHK_ERROR( CtrlPowerMode( demod, &orgPowerMode )); - } - else - { - /* dummy read to make this function fail in case device - suddenly disappears after a succesful DRX_Open */ - DUMMY_READ(); - } +static DRXStatus_t CtrlProbeDevice(pDRXDemodInstance_t demod) +{ + DRXPowerMode_t orgPowerMode = DRX_POWER_UP; + DRXStatus_t retStatus = DRX_STS_OK; + pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); + + commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; + + if (commonAttr->isOpened == FALSE + || commonAttr->currentPowerMode != DRX_POWER_UP) { + pI2CDeviceAddr_t devAddr = NULL; + DRXPowerMode_t powerMode = DRX_POWER_UP; + u32_t jtag = 0; + + devAddr = demod->myI2CDevAddr; + + /* Remeber original power mode */ + orgPowerMode = commonAttr->currentPowerMode; + + if (demod->myCommonAttr->isOpened == FALSE) { + CHK_ERROR(PowerUpDevice(demod)); + commonAttr->currentPowerMode = DRX_POWER_UP; + } else { + /* Wake-up device, feedback from device */ + CHK_ERROR(CtrlPowerMode(demod, &powerMode)); + } + /* Initialize HI, wakeup key especially */ + CHK_ERROR(InitHI(demod)); + + /* Check device id */ + RR32(devAddr, SIO_TOP_JTAGID_LO__A, &jtag); + jtag = (jtag >> 12) & 0xFFFF; + switch (jtag) { + case 0x3931: /* fallthrough */ + case 0x3932: /* fallthrough */ + case 0x3933: /* fallthrough */ + case 0x3934: /* fallthrough */ + case 0x3941: /* fallthrough */ + case 0x3942: /* fallthrough */ + case 0x3943: /* fallthrough */ + case 0x3944: /* fallthrough */ + case 0x3945: /* fallthrough */ + case 0x3946: + /* ok , do nothing */ + break; + default: + retStatus = DRX_STS_ERROR; + break; + } + + /* Device was not opened, return to orginal powermode, + feedback from device */ + CHK_ERROR(CtrlPowerMode(demod, &orgPowerMode)); + } else { + /* dummy read to make this function fail in case device + suddenly disappears after a succesful DRX_Open */ + DUMMY_READ(); + } - return ( retStatus ); + return (retStatus); - rw_error: - commonAttr->currentPowerMode=orgPowerMode; - return (DRX_STS_ERROR); +rw_error: + commonAttr->currentPowerMode = orgPowerMode; + return (DRX_STS_ERROR); } #ifdef DRXJ_SPLIT_UCODE_UPLOAD @@ -15062,14 +14349,12 @@ CtrlProbeDevice( pDRXDemodInstance_t demod ) FALSE if MC block not Audio * \return Bool_t. */ -Bool_t IsMCBlockAudio( u32_t addr ) +Bool_t IsMCBlockAudio(u32_t addr) { - if ( ( addr == AUD_XFP_PRAM_4K__A ) || - ( addr == AUD_XDFP_PRAM_4K__A ) ) - { - return ( TRUE ); - } - return ( FALSE ); + if ((addr == AUD_XFP_PRAM_4K__A) || (addr == AUD_XDFP_PRAM_4K__A)) { + return (TRUE); + } + return (FALSE); } /*============================================================================*/ @@ -15085,165 +14370,167 @@ Bool_t IsMCBlockAudio( u32_t addr ) * \return DRXStatus_t. */ static DRXStatus_t -CtrlUCodeUpload( pDRXDemodInstance_t demod, - pDRXUCodeInfo_t mcInfo, - DRXUCodeAction_t action, - Bool_t uploadAudioMC ) +CtrlUCodeUpload(pDRXDemodInstance_t demod, + pDRXUCodeInfo_t mcInfo, + DRXUCodeAction_t action, Bool_t uploadAudioMC) { - u16_t i = 0; - u16_t mcNrOfBlks = 0; - u16_t mcMagicWord = 0; - pu8_t mcData = (pu8_t)(NULL); - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)(NULL); - pDRXJData_t extAttr = (pDRXJData_t)(NULL); - - devAddr = demod -> myI2CDevAddr; - extAttr = (pDRXJData_t)demod -> myExtAttr; - - /* Check arguments */ - if ( ( mcInfo == NULL ) || - ( mcInfo->mcData == NULL ) || - ( mcInfo->mcSize == 0 ) ) - { - return DRX_STS_INVALID_ARG; - } + u16_t i = 0; + u16_t mcNrOfBlks = 0; + u16_t mcMagicWord = 0; + pu8_t mcData = (pu8_t) (NULL); + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) (NULL); + pDRXJData_t extAttr = (pDRXJData_t) (NULL); - mcData = mcInfo->mcData; + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; - /* Check data */ - mcMagicWord = UCodeRead16( mcData ); - mcData += sizeof( u16_t ); - mcNrOfBlks = UCodeRead16( mcData ); - mcData += sizeof( u16_t ); - - if ( ( mcMagicWord != DRXJ_UCODE_MAGIC_WORD ) || - ( mcNrOfBlks == 0 ) ) - { - /* wrong endianess or wrong data ? */ - return DRX_STS_INVALID_ARG; - } + /* Check arguments */ + if ((mcInfo == NULL) || + (mcInfo->mcData == NULL) || (mcInfo->mcSize == 0)) { + return DRX_STS_INVALID_ARG; + } - /* Process microcode blocks */ - for( i = 0 ; i 0x7FFF ) || - ( (( blockHdr.flags & DRXJ_UCODE_CRC_FLAG ) != 0) && - ( blockHdr.CRC != UCodeComputeCRC( mcData, blockHdr.size)) ) - ) - { - /* Wrong data ! */ - return DRX_STS_INVALID_ARG; - } - - mcBlockNrBytes = blockHdr.size * sizeof(u16_t); - - /* Perform the desired action */ - /* Check which part of MC need to be uploaded - Audio or not Audio */ - if( IsMCBlockAudio( blockHdr.addr ) == uploadAudioMC ) - { - switch ( action ) { - /*===================================================================*/ - case UCODE_UPLOAD : - { - /* Upload microcode */ - if ( demod->myAccessFunct->writeBlockFunc( - devAddr, - (DRXaddr_t) blockHdr.addr, - mcBlockNrBytes, - mcData, - 0x0000) != DRX_STS_OK) - { - return (DRX_STS_ERROR); - } - }; - break; + mcData = mcInfo->mcData; - /*===================================================================*/ - case UCODE_VERIFY : - { - int result = 0; - u8_t mcDataBuffer[DRXJ_UCODE_MAX_BUF_SIZE]; - u32_t bytesToCompare=0; - u32_t bytesLeftToCompare=0; - DRXaddr_t currAddr = (DRXaddr_t)0; - pu8_t currPtr =NULL; - - bytesLeftToCompare = mcBlockNrBytes; - currAddr = blockHdr.addr; - currPtr = mcData; - - while( bytesLeftToCompare != 0 ) - { - if (bytesLeftToCompare > ((u32_t)DRXJ_UCODE_MAX_BUF_SIZE) ) - { - bytesToCompare = ((u32_t)DRXJ_UCODE_MAX_BUF_SIZE); - } else { - bytesToCompare = bytesLeftToCompare; - } - - if ( demod->myAccessFunct->readBlockFunc( - devAddr, - currAddr, - (u16_t)bytesToCompare, - (pu8_t)mcDataBuffer, - 0x0000) != DRX_STS_OK) - { - return (DRX_STS_ERROR); - } + /* Check data */ + mcMagicWord = UCodeRead16(mcData); + mcData += sizeof(u16_t); + mcNrOfBlks = UCodeRead16(mcData); + mcData += sizeof(u16_t); - result = DRXBSP_HST_Memcmp( currPtr, - mcDataBuffer, - bytesToCompare); + if ((mcMagicWord != DRXJ_UCODE_MAGIC_WORD) || (mcNrOfBlks == 0)) { + /* wrong endianess or wrong data ? */ + return DRX_STS_INVALID_ARG; + } - if ( result != 0 ) - { - return (DRX_STS_ERROR); - }; + /* Process microcode blocks */ + for (i = 0; i < mcNrOfBlks; i++) { + DRXUCodeBlockHdr_t blockHdr; + u16_t mcBlockNrBytes = 0; + + /* Process block header */ + blockHdr.addr = UCodeRead32(mcData); + mcData += sizeof(u32_t); + blockHdr.size = UCodeRead16(mcData); + mcData += sizeof(u16_t); + blockHdr.flags = UCodeRead16(mcData); + mcData += sizeof(u16_t); + blockHdr.CRC = UCodeRead16(mcData); + mcData += sizeof(u16_t); + + /* Check block header on: + - no data + - data larger then 64Kb + - if CRC enabled check CRC + */ + if ((blockHdr.size == 0) || + (blockHdr.size > 0x7FFF) || + (((blockHdr.flags & DRXJ_UCODE_CRC_FLAG) != 0) && + (blockHdr.CRC != UCodeComputeCRC(mcData, blockHdr.size))) + ) { + /* Wrong data ! */ + return DRX_STS_INVALID_ARG; + } + + mcBlockNrBytes = blockHdr.size * sizeof(u16_t); + + /* Perform the desired action */ + /* Check which part of MC need to be uploaded - Audio or not Audio */ + if (IsMCBlockAudio(blockHdr.addr) == uploadAudioMC) { + switch (action) { + /*===================================================================*/ + case UCODE_UPLOAD: + { + /* Upload microcode */ + if (demod->myAccessFunct-> + writeBlockFunc(devAddr, + (DRXaddr_t) blockHdr. + addr, mcBlockNrBytes, + mcData, + 0x0000) != + DRX_STS_OK) { + return (DRX_STS_ERROR); + } + }; + break; - currAddr += ((DRXaddr_t)(bytesToCompare/2)); - currPtr = &(currPtr[bytesToCompare]); - bytesLeftToCompare -= ((u32_t)bytesToCompare); - } /* while( bytesToCompare > DRXJ_UCODE_MAX_BUF_SIZE ) */ - }; - break; + /*===================================================================*/ + case UCODE_VERIFY: + { + int result = 0; + u8_t mcDataBuffer + [DRXJ_UCODE_MAX_BUF_SIZE]; + u32_t bytesToCompare = 0; + u32_t bytesLeftToCompare = 0; + DRXaddr_t currAddr = (DRXaddr_t) 0; + pu8_t currPtr = NULL; + + bytesLeftToCompare = mcBlockNrBytes; + currAddr = blockHdr.addr; + currPtr = mcData; + + while (bytesLeftToCompare != 0) { + if (bytesLeftToCompare > + ((u32_t) + DRXJ_UCODE_MAX_BUF_SIZE)) { + bytesToCompare = + ((u32_t) + DRXJ_UCODE_MAX_BUF_SIZE); + } else { + bytesToCompare = + bytesLeftToCompare; + } + + if (demod->myAccessFunct-> + readBlockFunc(devAddr, + currAddr, + (u16_t) + bytesToCompare, + (pu8_t) + mcDataBuffer, + 0x0000) != + DRX_STS_OK) { + return (DRX_STS_ERROR); + } + + result = + DRXBSP_HST_Memcmp(currPtr, + mcDataBuffer, + bytesToCompare); + + if (result != 0) { + return (DRX_STS_ERROR); + }; + + currAddr += + ((DRXaddr_t) + (bytesToCompare / 2)); + currPtr = + &(currPtr[bytesToCompare]); + bytesLeftToCompare -= + ((u32_t) bytesToCompare); + } /* while( bytesToCompare > DRXJ_UCODE_MAX_BUF_SIZE ) */ + }; + break; /*===================================================================*/ - default: - return DRX_STS_INVALID_ARG; - break; + default: + return DRX_STS_INVALID_ARG; + break; - } /* switch ( action ) */ - } /* if( IsMCBlockAudio( blockHdr.addr ) == uploadAudioMC ) */ + } /* switch ( action ) */ + } - /* Next block */ - mcData += mcBlockNrBytes; - } /* for( i = 0 ; iflagAudMcUploaded = FALSE; - } + if (uploadAudioMC == FALSE) { + extAttr->flagAudMcUploaded = FALSE; + } - return (DRX_STS_OK); + return (DRX_STS_OK); } #endif /* DRXJ_SPLIT_UCODE_UPLOAD */ @@ -15264,54 +14551,51 @@ CtrlUCodeUpload( pDRXDemodInstance_t demod, */ static DRXStatus_t -CtrlSigStrength( pDRXDemodInstance_t demod, - pu16_t sigStrength ) +CtrlSigStrength(pDRXDemodInstance_t demod, pu16_t sigStrength) { - pDRXJData_t extAttr = NULL; - DRXStandard_t standard = DRX_STANDARD_UNKNOWN; + pDRXJData_t extAttr = NULL; + DRXStandard_t standard = DRX_STANDARD_UNKNOWN; - /* Check arguments */ - if ( ( sigStrength == NULL ) || - ( demod == NULL ) ) - { - return (DRX_STS_INVALID_ARG); - } + /* Check arguments */ + if ((sigStrength == NULL) || (demod == NULL)) { + return (DRX_STS_INVALID_ARG); + } - extAttr = (pDRXJData_t)demod->myExtAttr; - standard = extAttr->standard; - *sigStrength = 0; + extAttr = (pDRXJData_t) demod->myExtAttr; + standard = extAttr->standard; + *sigStrength = 0; - /* Signal strength indication for each standard */ - switch ( standard ) { - case DRX_STANDARD_8VSB: /* fallthrough */ + /* Signal strength indication for each standard */ + switch (standard) { + case DRX_STANDARD_8VSB: /* fallthrough */ #ifndef DRXJ_VSB_ONLY - case DRX_STANDARD_ITU_A: /* fallthrough */ - case DRX_STANDARD_ITU_B: /* fallthrough */ - case DRX_STANDARD_ITU_C: + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: #endif - CHK_ERROR( GetSigStrength( demod, sigStrength ) ); - break; + CHK_ERROR(GetSigStrength(demod, sigStrength)); + break; #ifndef DRXJ_DIGITAL_ONLY - case DRX_STANDARD_PAL_SECAM_BG : /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_DK : /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_I : /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_L : /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_LP : /* fallthrough */ - case DRX_STANDARD_NTSC: /* fallthrough */ - case DRX_STANDARD_FM: - CHK_ERROR( GetAtvSigStrength( demod, sigStrength ) ); - break; + case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_LP: /* fallthrough */ + case DRX_STANDARD_NTSC: /* fallthrough */ + case DRX_STANDARD_FM: + CHK_ERROR(GetAtvSigStrength(demod, sigStrength)); + break; #endif - case DRX_STANDARD_UNKNOWN: /* fallthrough */ - default: - return (DRX_STS_INVALID_ARG); - } - - /* TODO */ - /* find out if signal strength is calculated in the same way for all standards */ - return (DRX_STS_OK); - rw_error: - return (DRX_STS_ERROR); + case DRX_STANDARD_UNKNOWN: /* fallthrough */ + default: + return (DRX_STS_INVALID_ARG); + } + + /* TODO */ + /* find out if signal strength is calculated in the same way for all standards */ + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); } /*============================================================================*/ @@ -15324,48 +14608,47 @@ CtrlSigStrength( pDRXDemodInstance_t demod, */ #ifndef DRXJ_DIGITAL_ONLY static DRXStatus_t -CtrlGetCfgOOBMisc ( pDRXDemodInstance_t demod, pDRXJCfgOOBMisc_t misc ) +CtrlGetCfgOOBMisc(pDRXDemodInstance_t demod, pDRXJCfgOOBMisc_t misc) { - pI2CDeviceAddr_t devAddr = NULL; - u16_t lock = 0U; - u16_t state = 0U; - u16_t data = 0U; - u16_t digitalAGCMant = 0U; - u16_t digitalAGCExp = 0U; - - /* check arguments */ - if ( misc == NULL ) - { - return (DRX_STS_INVALID_ARG); - } - devAddr = demod -> myI2CDevAddr; - - /* TODO */ - /* check if the same registers are used for all standards (QAM/VSB/ATV) */ - RR16( devAddr, ORX_NSU_TUN_IFGAIN_W__A, &misc->agc.IFAGC ); - RR16( devAddr, ORX_NSU_TUN_RFGAIN_W__A, &misc->agc.RFAGC ); - RR16( devAddr, ORX_FWP_SRC_DGN_W__A, &data ); - - digitalAGCMant = data & ORX_FWP_SRC_DGN_W_MANT__M; - digitalAGCExp = (data & ORX_FWP_SRC_DGN_W_EXP__M) - >> ORX_FWP_SRC_DGN_W_EXP__B; - misc->agc.DigitalAGC = digitalAGCMant << digitalAGCExp; - - SARR16( devAddr, SCU_RAM_ORX_SCU_LOCK__A, &lock ); - - misc->anaGainLock = ((lock & 0x0001)?TRUE:FALSE); - misc->digGainLock = ((lock & 0x0002)?TRUE:FALSE); - misc->freqLock = ((lock & 0x0004)?TRUE:FALSE); - misc->phaseLock = ((lock & 0x0008)?TRUE:FALSE); - misc->symTimingLock = ((lock & 0x0010)?TRUE:FALSE); - misc->eqLock = ((lock & 0x0020)?TRUE:FALSE); - - SARR16( devAddr, SCU_RAM_ORX_SCU_STATE__A, &state ); - misc->state = (state>>8) & 0xff; - - return ( DRX_STS_OK ); + pI2CDeviceAddr_t devAddr = NULL; + u16_t lock = 0U; + u16_t state = 0U; + u16_t data = 0U; + u16_t digitalAGCMant = 0U; + u16_t digitalAGCExp = 0U; + + /* check arguments */ + if (misc == NULL) { + return (DRX_STS_INVALID_ARG); + } + devAddr = demod->myI2CDevAddr; + + /* TODO */ + /* check if the same registers are used for all standards (QAM/VSB/ATV) */ + RR16(devAddr, ORX_NSU_TUN_IFGAIN_W__A, &misc->agc.IFAGC); + RR16(devAddr, ORX_NSU_TUN_RFGAIN_W__A, &misc->agc.RFAGC); + RR16(devAddr, ORX_FWP_SRC_DGN_W__A, &data); + + digitalAGCMant = data & ORX_FWP_SRC_DGN_W_MANT__M; + digitalAGCExp = (data & ORX_FWP_SRC_DGN_W_EXP__M) + >> ORX_FWP_SRC_DGN_W_EXP__B; + misc->agc.DigitalAGC = digitalAGCMant << digitalAGCExp; + + SARR16(devAddr, SCU_RAM_ORX_SCU_LOCK__A, &lock); + + misc->anaGainLock = ((lock & 0x0001) ? TRUE : FALSE); + misc->digGainLock = ((lock & 0x0002) ? TRUE : FALSE); + misc->freqLock = ((lock & 0x0004) ? TRUE : FALSE); + misc->phaseLock = ((lock & 0x0008) ? TRUE : FALSE); + misc->symTimingLock = ((lock & 0x0010) ? TRUE : FALSE); + misc->eqLock = ((lock & 0x0020) ? TRUE : FALSE); + + SARR16(devAddr, SCU_RAM_ORX_SCU_STATE__A, &state); + misc->state = (state >> 8) & 0xff; + + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } #endif @@ -15377,23 +14660,23 @@ rw_error: * */ static DRXStatus_t -CtrlGetCfgVSBMisc ( pDRXDemodInstance_t demod, pDRXJCfgVSBMisc_t misc ) +CtrlGetCfgVSBMisc(pDRXDemodInstance_t demod, pDRXJCfgVSBMisc_t misc) { - pI2CDeviceAddr_t devAddr = NULL; + pI2CDeviceAddr_t devAddr = NULL; - /* check arguments */ - if ( misc == NULL ) - { - return (DRX_STS_INVALID_ARG); - } - devAddr = demod -> myI2CDevAddr; + /* check arguments */ + if (misc == NULL) { + return (DRX_STS_INVALID_ARG); + } + devAddr = demod->myI2CDevAddr; - CHK_ERROR(GetVSBSymbErr(devAddr, &misc->symbError)); + CHK_ERROR(GetVSBSymbErr(devAddr, &misc->symbError)); - return ( DRX_STS_OK ); + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } + /*============================================================================*/ /** @@ -15408,47 +14691,46 @@ rw_error: * */ static DRXStatus_t -CtrlSetCfgAgcIf ( pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings ) +CtrlSetCfgAgcIf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings) { - /* check arguments */ - if ( agcSettings == NULL ) - { - return ( DRX_STS_INVALID_ARG ); - } - - switch ( agcSettings->ctrlMode ) { - case DRX_AGC_CTRL_AUTO: /* fallthrough */ - case DRX_AGC_CTRL_USER: /* fallthrough */ - case DRX_AGC_CTRL_OFF: /* fallthrough */ - break; - default: - return ( DRX_STS_INVALID_ARG ); - } - - /* Distpatch */ - switch ( agcSettings->standard ) { - case DRX_STANDARD_8VSB: /* fallthrough */ + /* check arguments */ + if (agcSettings == NULL) { + return (DRX_STS_INVALID_ARG); + } + + switch (agcSettings->ctrlMode) { + case DRX_AGC_CTRL_AUTO: /* fallthrough */ + case DRX_AGC_CTRL_USER: /* fallthrough */ + case DRX_AGC_CTRL_OFF: /* fallthrough */ + break; + default: + return (DRX_STS_INVALID_ARG); + } + + /* Distpatch */ + switch (agcSettings->standard) { + case DRX_STANDARD_8VSB: /* fallthrough */ #ifndef DRXJ_VSB_ONLY - case DRX_STANDARD_ITU_A: /* fallthrough */ - case DRX_STANDARD_ITU_B: /* fallthrough */ - case DRX_STANDARD_ITU_C: + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: #endif #ifndef DRXJ_DIGITAL_ONLY - case DRX_STANDARD_PAL_SECAM_BG : /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_DK : /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_I : /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_L : /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_LP : /* fallthrough */ - case DRX_STANDARD_NTSC: /* fallthrough */ - case DRX_STANDARD_FM: + case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_LP: /* fallthrough */ + case DRX_STANDARD_NTSC: /* fallthrough */ + case DRX_STANDARD_FM: #endif - return SetAgcIf ( demod, agcSettings, TRUE); - case DRX_STANDARD_UNKNOWN: - default: - return ( DRX_STS_INVALID_ARG ); - } + return SetAgcIf(demod, agcSettings, TRUE); + case DRX_STANDARD_UNKNOWN: + default: + return (DRX_STS_INVALID_ARG); + } - return ( DRX_STS_OK ); + return (DRX_STS_OK); } /*============================================================================*/ @@ -15465,38 +14747,37 @@ CtrlSetCfgAgcIf ( pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings ) * */ static DRXStatus_t -CtrlGetCfgAgcIf ( pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings ) +CtrlGetCfgAgcIf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings) { - /* check arguments */ - if ( agcSettings == NULL ) - { - return ( DRX_STS_INVALID_ARG ); - } + /* check arguments */ + if (agcSettings == NULL) { + return (DRX_STS_INVALID_ARG); + } - /* Distpatch */ - switch ( agcSettings->standard ) { - case DRX_STANDARD_8VSB: /* fallthrough */ + /* Distpatch */ + switch (agcSettings->standard) { + case DRX_STANDARD_8VSB: /* fallthrough */ #ifndef DRXJ_VSB_ONLY - case DRX_STANDARD_ITU_A: /* fallthrough */ - case DRX_STANDARD_ITU_B: /* fallthrough */ - case DRX_STANDARD_ITU_C: + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: #endif #ifndef DRXJ_DIGITAL_ONLY - case DRX_STANDARD_PAL_SECAM_BG : /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_DK : /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_I : /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_L : /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_LP : /* fallthrough */ - case DRX_STANDARD_NTSC: /* fallthrough */ - case DRX_STANDARD_FM: + case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_LP: /* fallthrough */ + case DRX_STANDARD_NTSC: /* fallthrough */ + case DRX_STANDARD_FM: #endif - return GetAgcIf ( demod, agcSettings); - case DRX_STANDARD_UNKNOWN: - default: - return ( DRX_STS_INVALID_ARG ); - } + return GetAgcIf(demod, agcSettings); + case DRX_STANDARD_UNKNOWN: + default: + return (DRX_STS_INVALID_ARG); + } - return ( DRX_STS_OK ); + return (DRX_STS_OK); } /*============================================================================*/ @@ -15513,47 +14794,46 @@ CtrlGetCfgAgcIf ( pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings ) * */ static DRXStatus_t -CtrlSetCfgAgcRf ( pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings ) +CtrlSetCfgAgcRf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings) { - /* check arguments */ - if ( agcSettings == NULL ) - { - return ( DRX_STS_INVALID_ARG ); - } - - switch ( agcSettings->ctrlMode ) { - case DRX_AGC_CTRL_AUTO: /* fallthrough */ - case DRX_AGC_CTRL_USER: /* fallthrough */ - case DRX_AGC_CTRL_OFF: - break; - default: - return ( DRX_STS_INVALID_ARG ); - } - - /* Distpatch */ - switch ( agcSettings->standard ) { - case DRX_STANDARD_8VSB: /* fallthrough */ + /* check arguments */ + if (agcSettings == NULL) { + return (DRX_STS_INVALID_ARG); + } + + switch (agcSettings->ctrlMode) { + case DRX_AGC_CTRL_AUTO: /* fallthrough */ + case DRX_AGC_CTRL_USER: /* fallthrough */ + case DRX_AGC_CTRL_OFF: + break; + default: + return (DRX_STS_INVALID_ARG); + } + + /* Distpatch */ + switch (agcSettings->standard) { + case DRX_STANDARD_8VSB: /* fallthrough */ #ifndef DRXJ_VSB_ONLY - case DRX_STANDARD_ITU_A: /* fallthrough */ - case DRX_STANDARD_ITU_B: /* fallthrough */ - case DRX_STANDARD_ITU_C: + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: #endif #ifndef DRXJ_DIGITAL_ONLY - case DRX_STANDARD_PAL_SECAM_BG : /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_DK : /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_I : /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_L : /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_LP : /* fallthrough */ - case DRX_STANDARD_NTSC: /* fallthrough */ - case DRX_STANDARD_FM: + case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_LP: /* fallthrough */ + case DRX_STANDARD_NTSC: /* fallthrough */ + case DRX_STANDARD_FM: #endif - return SetAgcRf ( demod, agcSettings, TRUE); - case DRX_STANDARD_UNKNOWN: - default: - return ( DRX_STS_INVALID_ARG ); - } + return SetAgcRf(demod, agcSettings, TRUE); + case DRX_STANDARD_UNKNOWN: + default: + return (DRX_STS_INVALID_ARG); + } - return ( DRX_STS_OK ); + return (DRX_STS_OK); } /*============================================================================*/ @@ -15570,41 +14850,39 @@ CtrlSetCfgAgcRf ( pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings ) * */ static DRXStatus_t -CtrlGetCfgAgcRf ( pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings ) +CtrlGetCfgAgcRf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings) { - /* check arguments */ - if ( agcSettings == NULL ) - { - return ( DRX_STS_INVALID_ARG ); - } + /* check arguments */ + if (agcSettings == NULL) { + return (DRX_STS_INVALID_ARG); + } - /* Distpatch */ - switch ( agcSettings->standard ) { - case DRX_STANDARD_8VSB: /* fallthrough */ + /* Distpatch */ + switch (agcSettings->standard) { + case DRX_STANDARD_8VSB: /* fallthrough */ #ifndef DRXJ_VSB_ONLY - case DRX_STANDARD_ITU_A: /* fallthrough */ - case DRX_STANDARD_ITU_B: /* fallthrough */ - case DRX_STANDARD_ITU_C: + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: #endif #ifndef DRXJ_DIGITAL_ONLY - case DRX_STANDARD_PAL_SECAM_BG : /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_DK : /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_I : /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_L : /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_LP : /* fallthrough */ - case DRX_STANDARD_NTSC: /* fallthrough */ - case DRX_STANDARD_FM: + case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_LP: /* fallthrough */ + case DRX_STANDARD_NTSC: /* fallthrough */ + case DRX_STANDARD_FM: #endif - return GetAgcRf ( demod, agcSettings); - case DRX_STANDARD_UNKNOWN: - default: - return ( DRX_STS_INVALID_ARG ); - } + return GetAgcRf(demod, agcSettings); + case DRX_STANDARD_UNKNOWN: + default: + return (DRX_STS_INVALID_ARG); + } - return ( DRX_STS_OK ); + return (DRX_STS_OK); } - /*============================================================================*/ /** @@ -15619,78 +14897,73 @@ CtrlGetCfgAgcRf ( pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings ) * */ static DRXStatus_t -CtrlGetCfgAgcInternal ( pDRXDemodInstance_t demod, pu16_t agcInternal ) +CtrlGetCfgAgcInternal(pDRXDemodInstance_t demod, pu16_t agcInternal) { - pI2CDeviceAddr_t devAddr = NULL; - DRXLockStatus_t lockStatus = DRX_NOT_LOCKED; - pDRXJData_t extAttr = NULL; - u16_t iqmCfScaleSh = 0; - u16_t iqmCfPower = 0; - u16_t iqmCfAmp = 0; - u16_t iqmCfGain = 0; - - /* check arguments */ - if ( agcInternal == NULL ) - { - return ( DRX_STS_INVALID_ARG ); - } - devAddr = demod -> myI2CDevAddr; - extAttr = (pDRXJData_t)demod->myExtAttr; + pI2CDeviceAddr_t devAddr = NULL; + DRXLockStatus_t lockStatus = DRX_NOT_LOCKED; + pDRXJData_t extAttr = NULL; + u16_t iqmCfScaleSh = 0; + u16_t iqmCfPower = 0; + u16_t iqmCfAmp = 0; + u16_t iqmCfGain = 0; - CHK_ERROR( CtrlLockStatus( demod, &lockStatus) ); - if ( lockStatus != DRXJ_DEMOD_LOCK && lockStatus != DRX_LOCKED ) - { - *agcInternal = 0; - return DRX_STS_OK; - } - - /* Distpatch */ - switch ( extAttr->standard ) { - case DRX_STANDARD_8VSB: - iqmCfGain = 57; - break; + /* check arguments */ + if (agcInternal == NULL) { + return (DRX_STS_INVALID_ARG); + } + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; + + CHK_ERROR(CtrlLockStatus(demod, &lockStatus)); + if (lockStatus != DRXJ_DEMOD_LOCK && lockStatus != DRX_LOCKED) { + *agcInternal = 0; + return DRX_STS_OK; + } + + /* Distpatch */ + switch (extAttr->standard) { + case DRX_STANDARD_8VSB: + iqmCfGain = 57; + break; #ifndef DRXJ_VSB_ONLY - case DRX_STANDARD_ITU_A: - case DRX_STANDARD_ITU_B: - case DRX_STANDARD_ITU_C: - switch ( extAttr->constellation ) - { - case DRX_CONSTELLATION_QAM256: - case DRX_CONSTELLATION_QAM128: - case DRX_CONSTELLATION_QAM32: - case DRX_CONSTELLATION_QAM16: - iqmCfGain = 57; - break; - case DRX_CONSTELLATION_QAM64: - iqmCfGain = 56; - break; - default: - return (DRX_STS_ERROR); - } - break; + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: + switch (extAttr->constellation) { + case DRX_CONSTELLATION_QAM256: + case DRX_CONSTELLATION_QAM128: + case DRX_CONSTELLATION_QAM32: + case DRX_CONSTELLATION_QAM16: + iqmCfGain = 57; + break; + case DRX_CONSTELLATION_QAM64: + iqmCfGain = 56; + break; + default: + return (DRX_STS_ERROR); + } + break; #endif - default: - return ( DRX_STS_INVALID_ARG ); - } - - RR16( devAddr, IQM_CF_POW__A, &iqmCfPower); - RR16( devAddr, IQM_CF_SCALE_SH__A, &iqmCfScaleSh); - RR16( devAddr, IQM_CF_AMP__A, &iqmCfAmp); - /* IQM_CF_PWR_CORRECTION_dB = 3; - P5dB =10*log10(IQM_CF_POW)+12-6*9-IQM_CF_PWR_CORRECTION_dB; */ - /* P4dB = P5dB -20*log10(IQM_CF_AMP)-6*10 - -IQM_CF_Gain_dB-18+6*(27-IQM_CF_SCALE_SH*2-10) - +6*7+10*log10(1+0.115/4); */ - /* PadcdB = P4dB +3 -6 +60; dBmV */ - *agcInternal = (u16_t) ( Log10Times100 (iqmCfPower) - - 2 * Log10Times100 (iqmCfAmp) - - iqmCfGain - - 120 * iqmCfScaleSh - + 781 ); - - return ( DRX_STS_OK ); + default: + return (DRX_STS_INVALID_ARG); + } + + RR16(devAddr, IQM_CF_POW__A, &iqmCfPower); + RR16(devAddr, IQM_CF_SCALE_SH__A, &iqmCfScaleSh); + RR16(devAddr, IQM_CF_AMP__A, &iqmCfAmp); + /* IQM_CF_PWR_CORRECTION_dB = 3; + P5dB =10*log10(IQM_CF_POW)+12-6*9-IQM_CF_PWR_CORRECTION_dB; */ + /* P4dB = P5dB -20*log10(IQM_CF_AMP)-6*10 + -IQM_CF_Gain_dB-18+6*(27-IQM_CF_SCALE_SH*2-10) + +6*7+10*log10(1+0.115/4); */ + /* PadcdB = P4dB +3 -6 +60; dBmV */ + *agcInternal = (u16_t) (Log10Times100(iqmCfPower) + - 2 * Log10Times100(iqmCfAmp) + - iqmCfGain - 120 * iqmCfScaleSh + 781); + + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /*============================================================================*/ @@ -15707,62 +14980,59 @@ rw_error: * */ static DRXStatus_t -CtrlSetCfgPreSaw ( pDRXDemodInstance_t demod, pDRXJCfgPreSaw_t preSaw ) +CtrlSetCfgPreSaw(pDRXDemodInstance_t demod, pDRXJCfgPreSaw_t preSaw) { - pI2CDeviceAddr_t devAddr = NULL; - pDRXJData_t extAttr = NULL; + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; - devAddr = demod -> myI2CDevAddr; - extAttr = (pDRXJData_t)demod->myExtAttr; + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; - /* check arguments */ - if ( ( preSaw == NULL ) || - ( preSaw->reference > IQM_AF_PDREF__M ) - ) - { - return ( DRX_STS_INVALID_ARG ); - } - - /* Only if standard is currently active*/ - if ( ( extAttr->standard == preSaw->standard ) || - ( DRXJ_ISQAMSTD( extAttr->standard ) && - DRXJ_ISQAMSTD( preSaw->standard ) ) || - ( DRXJ_ISATVSTD( extAttr->standard ) && - DRXJ_ISATVSTD( preSaw->standard ) ) ) - { - WR16( devAddr, IQM_AF_PDREF__A , preSaw->reference); - } - - /* Store pre-saw settings */ - switch ( preSaw->standard){ - case DRX_STANDARD_8VSB: - extAttr->vsbPreSawCfg = *preSaw; - break; + /* check arguments */ + if ((preSaw == NULL) || (preSaw->reference > IQM_AF_PDREF__M) + ) { + return (DRX_STS_INVALID_ARG); + } + + /* Only if standard is currently active */ + if ((extAttr->standard == preSaw->standard) || + (DRXJ_ISQAMSTD(extAttr->standard) && + DRXJ_ISQAMSTD(preSaw->standard)) || + (DRXJ_ISATVSTD(extAttr->standard) && + DRXJ_ISATVSTD(preSaw->standard))) { + WR16(devAddr, IQM_AF_PDREF__A, preSaw->reference); + } + + /* Store pre-saw settings */ + switch (preSaw->standard) { + case DRX_STANDARD_8VSB: + extAttr->vsbPreSawCfg = *preSaw; + break; #ifndef DRXJ_VSB_ONLY - case DRX_STANDARD_ITU_A: /* fallthrough */ - case DRX_STANDARD_ITU_B: /* fallthrough */ - case DRX_STANDARD_ITU_C: - extAttr->qamPreSawCfg = *preSaw; - break; + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: + extAttr->qamPreSawCfg = *preSaw; + break; #endif #ifndef DRXJ_DIGITAL_ONLY - case DRX_STANDARD_PAL_SECAM_BG : /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_DK : /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_I : /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_L : /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_LP : /* fallthrough */ - case DRX_STANDARD_NTSC: /* fallthrough */ - case DRX_STANDARD_FM: - extAttr->atvPreSawCfg = *preSaw; - break; + case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_LP: /* fallthrough */ + case DRX_STANDARD_NTSC: /* fallthrough */ + case DRX_STANDARD_FM: + extAttr->atvPreSawCfg = *preSaw; + break; #endif - default: - return (DRX_STS_INVALID_ARG); - } + default: + return (DRX_STS_INVALID_ARG); + } - return ( DRX_STS_OK ); + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /*============================================================================*/ @@ -15779,67 +15049,66 @@ rw_error: * */ static DRXStatus_t -CtrlSetCfgAfeGain ( pDRXDemodInstance_t demod, pDRXJCfgAfeGain_t afeGain ) +CtrlSetCfgAfeGain(pDRXDemodInstance_t demod, pDRXJCfgAfeGain_t afeGain) { - pI2CDeviceAddr_t devAddr = NULL; - pDRXJData_t extAttr = NULL; - u8_t gain = 0; + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + u8_t gain = 0; - /* check arguments */ - if ( afeGain == NULL ) - { - return (DRX_STS_INVALID_ARG); - } + /* check arguments */ + if (afeGain == NULL) { + return (DRX_STS_INVALID_ARG); + } - devAddr = demod -> myI2CDevAddr; - extAttr = (pDRXJData_t)demod->myExtAttr; + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; - switch ( afeGain->standard){ - case DRX_STANDARD_8VSB: /* fallthrough */ + switch (afeGain->standard) { + case DRX_STANDARD_8VSB: /* fallthrough */ #ifndef DRXJ_VSB_ONLY - case DRX_STANDARD_ITU_A: /* fallthrough */ - case DRX_STANDARD_ITU_B: /* fallthrough */ - case DRX_STANDARD_ITU_C: + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: #endif - /* Do nothing */ - break; - default: - return (DRX_STS_INVALID_ARG); - } + /* Do nothing */ + break; + default: + return (DRX_STS_INVALID_ARG); + } - /* TODO PGA gain is also written by microcode (at least by QAM and VSB) + /* TODO PGA gain is also written by microcode (at least by QAM and VSB) So I (PJ) think interface requires choice between auto, user mode */ - if (afeGain->gain >= 329) - gain = 15; - else if (afeGain->gain <= 147) - gain = 0; - else - gain = (afeGain->gain - 140 + 6) / 13; - - /* Only if standard is currently active*/ - if( extAttr->standard == afeGain->standard ) - WR16( devAddr, IQM_AF_PGA_GAIN__A, gain); - - /* Store AFE Gain settings */ - switch ( afeGain->standard){ - case DRX_STANDARD_8VSB: - extAttr->vsbPgaCfg = gain * 13 + 140; - break; + if (afeGain->gain >= 329) + gain = 15; + else if (afeGain->gain <= 147) + gain = 0; + else + gain = (afeGain->gain - 140 + 6) / 13; + + /* Only if standard is currently active */ + if (extAttr->standard == afeGain->standard) + WR16(devAddr, IQM_AF_PGA_GAIN__A, gain); + + /* Store AFE Gain settings */ + switch (afeGain->standard) { + case DRX_STANDARD_8VSB: + extAttr->vsbPgaCfg = gain * 13 + 140; + break; #ifndef DRXJ_VSB_ONLY - case DRX_STANDARD_ITU_A: /* fallthrough */ - case DRX_STANDARD_ITU_B: /* fallthrough */ - case DRX_STANDARD_ITU_C: - extAttr->qamPgaCfg = gain * 13 + 140; - break; + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: + extAttr->qamPgaCfg = gain * 13 + 140; + break; #endif - default: - return (DRX_STS_ERROR); - } + default: + return (DRX_STS_ERROR); + } - return ( DRX_STS_OK ); + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /*============================================================================*/ @@ -15856,51 +15125,50 @@ rw_error: * */ static DRXStatus_t -CtrlGetCfgPreSaw ( pDRXDemodInstance_t demod, pDRXJCfgPreSaw_t preSaw ) +CtrlGetCfgPreSaw(pDRXDemodInstance_t demod, pDRXJCfgPreSaw_t preSaw) { - pI2CDeviceAddr_t devAddr = NULL; - pDRXJData_t extAttr = NULL; + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; - /* check arguments */ - if ( preSaw == NULL ) - { - return ( DRX_STS_INVALID_ARG ); - } + /* check arguments */ + if (preSaw == NULL) { + return (DRX_STS_INVALID_ARG); + } - devAddr = demod -> myI2CDevAddr; - extAttr = (pDRXJData_t)demod->myExtAttr; + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; - switch ( preSaw->standard ){ - case DRX_STANDARD_8VSB: - *preSaw = extAttr->vsbPreSawCfg; - break; + switch (preSaw->standard) { + case DRX_STANDARD_8VSB: + *preSaw = extAttr->vsbPreSawCfg; + break; #ifndef DRXJ_VSB_ONLY - case DRX_STANDARD_ITU_A: /* fallthrough */ - case DRX_STANDARD_ITU_B: /* fallthrough */ - case DRX_STANDARD_ITU_C: - *preSaw = extAttr->qamPreSawCfg; - break; + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: + *preSaw = extAttr->qamPreSawCfg; + break; #endif #ifndef DRXJ_DIGITAL_ONLY - case DRX_STANDARD_PAL_SECAM_BG : /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_DK : /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_I : /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_L : /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_LP : /* fallthrough */ - case DRX_STANDARD_NTSC: - extAttr->atvPreSawCfg.standard = DRX_STANDARD_NTSC; - *preSaw = extAttr->atvPreSawCfg; - break; - case DRX_STANDARD_FM: - extAttr->atvPreSawCfg.standard = DRX_STANDARD_FM; - *preSaw = extAttr->atvPreSawCfg; - break; + case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_LP: /* fallthrough */ + case DRX_STANDARD_NTSC: + extAttr->atvPreSawCfg.standard = DRX_STANDARD_NTSC; + *preSaw = extAttr->atvPreSawCfg; + break; + case DRX_STANDARD_FM: + extAttr->atvPreSawCfg.standard = DRX_STANDARD_FM; + *preSaw = extAttr->atvPreSawCfg; + break; #endif - default: - return (DRX_STS_INVALID_ARG); - } + default: + return (DRX_STS_INVALID_ARG); + } - return ( DRX_STS_OK ); + return (DRX_STS_OK); } /*============================================================================*/ @@ -15917,36 +15185,35 @@ CtrlGetCfgPreSaw ( pDRXDemodInstance_t demod, pDRXJCfgPreSaw_t preSaw ) * */ static DRXStatus_t -CtrlGetCfgAfeGain ( pDRXDemodInstance_t demod, pDRXJCfgAfeGain_t afeGain ) +CtrlGetCfgAfeGain(pDRXDemodInstance_t demod, pDRXJCfgAfeGain_t afeGain) { - pI2CDeviceAddr_t devAddr = NULL; - pDRXJData_t extAttr = NULL; + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; - /* check arguments */ - if ( afeGain == NULL ) - { - return ( DRX_STS_INVALID_ARG ); - } + /* check arguments */ + if (afeGain == NULL) { + return (DRX_STS_INVALID_ARG); + } - devAddr = demod -> myI2CDevAddr; - extAttr = (pDRXJData_t)demod->myExtAttr; + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; - switch ( afeGain->standard){ - case DRX_STANDARD_8VSB: - afeGain->gain = extAttr->vsbPgaCfg; - break; + switch (afeGain->standard) { + case DRX_STANDARD_8VSB: + afeGain->gain = extAttr->vsbPgaCfg; + break; #ifndef DRXJ_VSB_ONLY - case DRX_STANDARD_ITU_A: /* fallthrough */ - case DRX_STANDARD_ITU_B: /* fallthrough */ - case DRX_STANDARD_ITU_C: - afeGain->gain = extAttr->qamPgaCfg; - break; + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: + afeGain->gain = extAttr->qamPgaCfg; + break; #endif - default: - return (DRX_STS_INVALID_ARG); - } + default: + return (DRX_STS_INVALID_ARG); + } - return ( DRX_STS_OK ); + return (DRX_STS_OK); } /*============================================================================*/ @@ -15963,20 +15230,20 @@ CtrlGetCfgAfeGain ( pDRXDemodInstance_t demod, pDRXJCfgAfeGain_t afeGain ) * */ static DRXStatus_t -CtrlGetFecMeasSeqCount ( pDRXDemodInstance_t demod, pu16_t fecMeasSeqCount) +CtrlGetFecMeasSeqCount(pDRXDemodInstance_t demod, pu16_t fecMeasSeqCount) { - /* check arguments */ - if ( fecMeasSeqCount == NULL ) - { - return ( DRX_STS_INVALID_ARG ); - } + /* check arguments */ + if (fecMeasSeqCount == NULL) { + return (DRX_STS_INVALID_ARG); + } - RR16 ( demod->myI2CDevAddr, SCU_RAM_FEC_MEAS_COUNT__A, fecMeasSeqCount ); + RR16(demod->myI2CDevAddr, SCU_RAM_FEC_MEAS_COUNT__A, fecMeasSeqCount); - return (DRX_STS_OK); + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } + /*============================================================================*/ /** @@ -15991,18 +15258,18 @@ rw_error: * */ static DRXStatus_t -CtrlGetAccumCrRSCwErr ( pDRXDemodInstance_t demod, pu32_t accumCrRsCWErr) +CtrlGetAccumCrRSCwErr(pDRXDemodInstance_t demod, pu32_t accumCrRsCWErr) { - if(accumCrRsCWErr == NULL) - { - return (DRX_STS_INVALID_ARG); - } + if (accumCrRsCWErr == NULL) { + return (DRX_STS_INVALID_ARG); + } - RR32 ( demod->myI2CDevAddr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, accumCrRsCWErr ); + RR32(demod->myI2CDevAddr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, + accumCrRsCWErr); - return (DRX_STS_OK); + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /** @@ -16013,90 +15280,102 @@ rw_error: * \return DRXStatus_t. */ -static DRXStatus_t -CtrlSetCfg( pDRXDemodInstance_t demod, - pDRXCfg_t config ) +static DRXStatus_t CtrlSetCfg(pDRXDemodInstance_t demod, pDRXCfg_t config) { - if ( config == NULL ) - { - return (DRX_STS_INVALID_ARG); - } + if (config == NULL) { + return (DRX_STS_INVALID_ARG); + } - DUMMY_READ(); - switch ( config->cfgType ) - { - case DRX_CFG_MPEG_OUTPUT: - return CtrlSetCfgMPEGOutput( demod, (pDRXCfgMPEGOutput_t) config->cfgData ); - case DRX_CFG_PINS_SAFE_MODE: - return CtrlSetCfgPdrSafeMode( demod, (pBool_t) config->cfgData ); - case DRXJ_CFG_AGC_RF: - return CtrlSetCfgAgcRf ( demod, (pDRXJCfgAgc_t) config->cfgData ); - case DRXJ_CFG_AGC_IF: - return CtrlSetCfgAgcIf ( demod, (pDRXJCfgAgc_t) config->cfgData ); - case DRXJ_CFG_PRE_SAW: - return CtrlSetCfgPreSaw ( demod, (pDRXJCfgPreSaw_t) config->cfgData ); - case DRXJ_CFG_AFE_GAIN: - return CtrlSetCfgAfeGain ( demod, (pDRXJCfgAfeGain_t) config->cfgData ); - case DRXJ_CFG_SMART_ANT: - return CtrlSetCfgSmartAnt ( demod, (pDRXJCfgSmartAnt_t)(config->cfgData) ); - case DRXJ_CFG_RESET_PACKET_ERR: - return CtrlSetCfgResetPktErr ( demod ); + DUMMY_READ(); + switch (config->cfgType) { + case DRX_CFG_MPEG_OUTPUT: + return CtrlSetCfgMPEGOutput(demod, + (pDRXCfgMPEGOutput_t) config-> + cfgData); + case DRX_CFG_PINS_SAFE_MODE: + return CtrlSetCfgPdrSafeMode(demod, (pBool_t) config->cfgData); + case DRXJ_CFG_AGC_RF: + return CtrlSetCfgAgcRf(demod, (pDRXJCfgAgc_t) config->cfgData); + case DRXJ_CFG_AGC_IF: + return CtrlSetCfgAgcIf(demod, (pDRXJCfgAgc_t) config->cfgData); + case DRXJ_CFG_PRE_SAW: + return CtrlSetCfgPreSaw(demod, + (pDRXJCfgPreSaw_t) config->cfgData); + case DRXJ_CFG_AFE_GAIN: + return CtrlSetCfgAfeGain(demod, + (pDRXJCfgAfeGain_t) config->cfgData); + case DRXJ_CFG_SMART_ANT: + return CtrlSetCfgSmartAnt(demod, + (pDRXJCfgSmartAnt_t) (config-> + cfgData)); + case DRXJ_CFG_RESET_PACKET_ERR: + return CtrlSetCfgResetPktErr(demod); #ifndef DRXJ_DIGITAL_ONLY - case DRXJ_CFG_OOB_PRE_SAW: - return CtrlSetCfgOOBPreSAW ( demod, (pu16_t)(config->cfgData) ); - case DRXJ_CFG_OOB_LO_POW: - return CtrlSetCfgOOBLoPower ( demod, (pDRXJCfgOobLoPower_t)(config->cfgData) ); - case DRXJ_CFG_ATV_MISC: - return CtrlSetCfgAtvMisc( demod, (pDRXJCfgAtvMisc_t) config->cfgData ); - case DRXJ_CFG_ATV_EQU_COEF: - return CtrlSetCfgAtvEquCoef( demod, - (pDRXJCfgAtvEquCoef_t) config->cfgData ); - case DRXJ_CFG_ATV_OUTPUT: - return CtrlSetCfgATVOutput( demod, - (pDRXJCfgAtvOutput_t) config->cfgData ); + case DRXJ_CFG_OOB_PRE_SAW: + return CtrlSetCfgOOBPreSAW(demod, (pu16_t) (config->cfgData)); + case DRXJ_CFG_OOB_LO_POW: + return CtrlSetCfgOOBLoPower(demod, + (pDRXJCfgOobLoPower_t) (config-> + cfgData)); + case DRXJ_CFG_ATV_MISC: + return CtrlSetCfgAtvMisc(demod, + (pDRXJCfgAtvMisc_t) config->cfgData); + case DRXJ_CFG_ATV_EQU_COEF: + return CtrlSetCfgAtvEquCoef(demod, + (pDRXJCfgAtvEquCoef_t) config-> + cfgData); + case DRXJ_CFG_ATV_OUTPUT: + return CtrlSetCfgATVOutput(demod, + (pDRXJCfgAtvOutput_t) config-> + cfgData); #endif - case DRXJ_CFG_MPEG_OUTPUT_MISC: - return CtrlSetCfgMpegOutputMisc( demod, - (pDRXJCfgMpegOutputMisc_t) config->cfgData ); + case DRXJ_CFG_MPEG_OUTPUT_MISC: + return CtrlSetCfgMpegOutputMisc(demod, + (pDRXJCfgMpegOutputMisc_t) + config->cfgData); #ifndef DRXJ_EXCLUDE_AUDIO - case DRX_CFG_AUD_VOLUME: - return AUDCtrlSetCfgVolume( demod, - (pDRXCfgAudVolume_t)config->cfgData ); - case DRX_CFG_I2S_OUTPUT: - return AUDCtrlSetCfgOutputI2S( demod, - (pDRXCfgI2SOutput_t)config->cfgData ); - case DRX_CFG_AUD_AUTOSOUND: - return AUDCtrSetlCfgAutoSound( demod, - (pDRXCfgAudAutoSound_t) - config->cfgData); - case DRX_CFG_AUD_ASS_THRES: - return AUDCtrlSetCfgASSThres( demod, - (pDRXCfgAudASSThres_t) + case DRX_CFG_AUD_VOLUME: + return AUDCtrlSetCfgVolume(demod, + (pDRXCfgAudVolume_t) config-> + cfgData); + case DRX_CFG_I2S_OUTPUT: + return AUDCtrlSetCfgOutputI2S(demod, + (pDRXCfgI2SOutput_t) config-> + cfgData); + case DRX_CFG_AUD_AUTOSOUND: + return AUDCtrSetlCfgAutoSound(demod, (pDRXCfgAudAutoSound_t) + config->cfgData); + case DRX_CFG_AUD_ASS_THRES: + return AUDCtrlSetCfgASSThres(demod, (pDRXCfgAudASSThres_t) config->cfgData); - case DRX_CFG_AUD_CARRIER: - return AUDCtrlSetCfgCarrier( demod, - (pDRXCfgAudCarriers_t)config->cfgData); - case DRX_CFG_AUD_DEVIATION: - return AUDCtrlSetCfgDev( demod, - (pDRXCfgAudDeviation_t)config->cfgData); - case DRX_CFG_AUD_PRESCALE: - return AUDCtrlSetCfgPrescale( demod, - (pDRXCfgAudPrescale_t)config->cfgData); - case DRX_CFG_AUD_MIXER: - return AUDCtrlSetCfgMixer( demod, - (pDRXCfgAudMixer_t)config->cfgData); - case DRX_CFG_AUD_AVSYNC: - return AUDCtrlSetCfgAVSync( demod, - (pDRXCfgAudAVSync_t)config->cfgData); + case DRX_CFG_AUD_CARRIER: + return AUDCtrlSetCfgCarrier(demod, + (pDRXCfgAudCarriers_t) config-> + cfgData); + case DRX_CFG_AUD_DEVIATION: + return AUDCtrlSetCfgDev(demod, + (pDRXCfgAudDeviation_t) config-> + cfgData); + case DRX_CFG_AUD_PRESCALE: + return AUDCtrlSetCfgPrescale(demod, + (pDRXCfgAudPrescale_t) config-> + cfgData); + case DRX_CFG_AUD_MIXER: + return AUDCtrlSetCfgMixer(demod, + (pDRXCfgAudMixer_t) config->cfgData); + case DRX_CFG_AUD_AVSYNC: + return AUDCtrlSetCfgAVSync(demod, + (pDRXCfgAudAVSync_t) config-> + cfgData); #endif - default: - return (DRX_STS_INVALID_ARG); - } + default: + return (DRX_STS_INVALID_ARG); + } - return (DRX_STS_OK); + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /*============================================================================*/ @@ -16109,108 +15388,125 @@ rw_error: * \return DRXStatus_t. */ -static DRXStatus_t -CtrlGetCfg( pDRXDemodInstance_t demod, - pDRXCfg_t config ) +static DRXStatus_t CtrlGetCfg(pDRXDemodInstance_t demod, pDRXCfg_t config) { - if ( config == NULL ) - { - return (DRX_STS_INVALID_ARG); - } - - DUMMY_READ(); + if (config == NULL) { + return (DRX_STS_INVALID_ARG); + } - switch ( config->cfgType ) - { - case DRX_CFG_MPEG_OUTPUT: - return CtrlGetCfgMPEGOutput( demod, - (pDRXCfgMPEGOutput_t) config->cfgData ); - case DRX_CFG_PINS_SAFE_MODE: - return CtrlGetCfgPdrSafeMode( demod, (pBool_t) config->cfgData ); - case DRXJ_CFG_AGC_RF: - return CtrlGetCfgAgcRf ( demod, (pDRXJCfgAgc_t) config->cfgData ); - case DRXJ_CFG_AGC_IF: - return CtrlGetCfgAgcIf ( demod, (pDRXJCfgAgc_t) config->cfgData ); - case DRXJ_CFG_AGC_INTERNAL: - return CtrlGetCfgAgcInternal ( demod, (pu16_t) config->cfgData ); - case DRXJ_CFG_PRE_SAW: - return CtrlGetCfgPreSaw ( demod, (pDRXJCfgPreSaw_t) config->cfgData ); - case DRXJ_CFG_AFE_GAIN: - return CtrlGetCfgAfeGain ( demod, (pDRXJCfgAfeGain_t) config->cfgData ); - case DRXJ_CFG_ACCUM_CR_RS_CW_ERR: - return CtrlGetAccumCrRSCwErr ( demod, (pu32_t) config->cfgData ); - case DRXJ_CFG_FEC_MERS_SEQ_COUNT: - return CtrlGetFecMeasSeqCount ( demod, (pu16_t) config->cfgData ); - case DRXJ_CFG_VSB_MISC: - return CtrlGetCfgVSBMisc ( demod, (pDRXJCfgVSBMisc_t) config->cfgData ); - case DRXJ_CFG_SYMBOL_CLK_OFFSET: - return CtrlGetCfgSymbolClockOffset ( demod, (ps32_t) config->cfgData ); + DUMMY_READ(); + + switch (config->cfgType) { + case DRX_CFG_MPEG_OUTPUT: + return CtrlGetCfgMPEGOutput(demod, + (pDRXCfgMPEGOutput_t) config-> + cfgData); + case DRX_CFG_PINS_SAFE_MODE: + return CtrlGetCfgPdrSafeMode(demod, (pBool_t) config->cfgData); + case DRXJ_CFG_AGC_RF: + return CtrlGetCfgAgcRf(demod, (pDRXJCfgAgc_t) config->cfgData); + case DRXJ_CFG_AGC_IF: + return CtrlGetCfgAgcIf(demod, (pDRXJCfgAgc_t) config->cfgData); + case DRXJ_CFG_AGC_INTERNAL: + return CtrlGetCfgAgcInternal(demod, (pu16_t) config->cfgData); + case DRXJ_CFG_PRE_SAW: + return CtrlGetCfgPreSaw(demod, + (pDRXJCfgPreSaw_t) config->cfgData); + case DRXJ_CFG_AFE_GAIN: + return CtrlGetCfgAfeGain(demod, + (pDRXJCfgAfeGain_t) config->cfgData); + case DRXJ_CFG_ACCUM_CR_RS_CW_ERR: + return CtrlGetAccumCrRSCwErr(demod, (pu32_t) config->cfgData); + case DRXJ_CFG_FEC_MERS_SEQ_COUNT: + return CtrlGetFecMeasSeqCount(demod, (pu16_t) config->cfgData); + case DRXJ_CFG_VSB_MISC: + return CtrlGetCfgVSBMisc(demod, + (pDRXJCfgVSBMisc_t) config->cfgData); + case DRXJ_CFG_SYMBOL_CLK_OFFSET: + return CtrlGetCfgSymbolClockOffset(demod, + (ps32_t) config->cfgData); #ifndef DRXJ_DIGITAL_ONLY - case DRXJ_CFG_OOB_MISC: - return CtrlGetCfgOOBMisc ( demod, (pDRXJCfgOOBMisc_t) config->cfgData ); - case DRXJ_CFG_OOB_PRE_SAW: - return CtrlGetCfgOOBPreSAW ( demod, (pu16_t)(config->cfgData) ); - case DRXJ_CFG_OOB_LO_POW: - return CtrlGetCfgOOBLoPower ( demod, (pDRXJCfgOobLoPower_t)(config->cfgData) ); - case DRXJ_CFG_ATV_EQU_COEF: - return CtrlGetCfgAtvEquCoef( demod, - (pDRXJCfgAtvEquCoef_t) config->cfgData ); - case DRXJ_CFG_ATV_MISC: - return CtrlGetCfgAtvMisc( demod, (pDRXJCfgAtvMisc_t) config->cfgData ); - case DRXJ_CFG_ATV_OUTPUT: - return CtrlGetCfgAtvOutput( demod, - (pDRXJCfgAtvOutput_t) config->cfgData ); - case DRXJ_CFG_ATV_AGC_STATUS: - return CtrlGetCfgAtvAgcStatus( demod, - (pDRXJCfgAtvAgcStatus_t) config->cfgData ); + case DRXJ_CFG_OOB_MISC: + return CtrlGetCfgOOBMisc(demod, + (pDRXJCfgOOBMisc_t) config->cfgData); + case DRXJ_CFG_OOB_PRE_SAW: + return CtrlGetCfgOOBPreSAW(demod, (pu16_t) (config->cfgData)); + case DRXJ_CFG_OOB_LO_POW: + return CtrlGetCfgOOBLoPower(demod, + (pDRXJCfgOobLoPower_t) (config-> + cfgData)); + case DRXJ_CFG_ATV_EQU_COEF: + return CtrlGetCfgAtvEquCoef(demod, + (pDRXJCfgAtvEquCoef_t) config-> + cfgData); + case DRXJ_CFG_ATV_MISC: + return CtrlGetCfgAtvMisc(demod, + (pDRXJCfgAtvMisc_t) config->cfgData); + case DRXJ_CFG_ATV_OUTPUT: + return CtrlGetCfgAtvOutput(demod, + (pDRXJCfgAtvOutput_t) config-> + cfgData); + case DRXJ_CFG_ATV_AGC_STATUS: + return CtrlGetCfgAtvAgcStatus(demod, + (pDRXJCfgAtvAgcStatus_t) config-> + cfgData); #endif - case DRXJ_CFG_MPEG_OUTPUT_MISC: - return CtrlGetCfgMpegOutputMisc( demod, - (pDRXJCfgMpegOutputMisc_t) config->cfgData ); - case DRXJ_CFG_HW_CFG: - return CtrlGetCfgHwCfg( demod, - (pDRXJCfgHwCfg_t) config->cfgData ); + case DRXJ_CFG_MPEG_OUTPUT_MISC: + return CtrlGetCfgMpegOutputMisc(demod, + (pDRXJCfgMpegOutputMisc_t) + config->cfgData); + case DRXJ_CFG_HW_CFG: + return CtrlGetCfgHwCfg(demod, + (pDRXJCfgHwCfg_t) config->cfgData); #ifndef DRXJ_EXCLUDE_AUDIO - case DRX_CFG_AUD_VOLUME: - return AUDCtrlGetCfgVolume ( demod, - (pDRXCfgAudVolume_t)config->cfgData ); - case DRX_CFG_I2S_OUTPUT: - return AUDCtrlGetCfgOutputI2S ( demod, - (pDRXCfgI2SOutput_t)config->cfgData ); - - case DRX_CFG_AUD_RDS: - return AUDCtrlGetCfgRDS ( demod, - (pDRXCfgAudRDS_t)config->cfgData ); - case DRX_CFG_AUD_AUTOSOUND: - return AUDCtrlGetCfgAutoSound ( demod, - (pDRXCfgAudAutoSound_t)config->cfgData); - case DRX_CFG_AUD_ASS_THRES: - return AUDCtrlGetCfgASSThres ( demod, - (pDRXCfgAudASSThres_t)config->cfgData); - case DRX_CFG_AUD_CARRIER: - return AUDCtrlGetCfgCarrier ( demod, - (pDRXCfgAudCarriers_t)config->cfgData); - case DRX_CFG_AUD_DEVIATION: - return AUDCtrlGetCfgDev ( demod, - (pDRXCfgAudDeviation_t)config->cfgData); - case DRX_CFG_AUD_PRESCALE: - return AUDCtrlGetCfgPrescale ( demod, - (pDRXCfgAudPrescale_t)config->cfgData); - case DRX_CFG_AUD_MIXER: - return AUDCtrlGetCfgMixer ( demod, - (pDRXCfgAudMixer_t)config->cfgData); - case DRX_CFG_AUD_AVSYNC: - return AUDCtrlGetCfgAVSync ( demod, - (pDRXCfgAudAVSync_t)config->cfgData); + case DRX_CFG_AUD_VOLUME: + return AUDCtrlGetCfgVolume(demod, + (pDRXCfgAudVolume_t) config-> + cfgData); + case DRX_CFG_I2S_OUTPUT: + return AUDCtrlGetCfgOutputI2S(demod, + (pDRXCfgI2SOutput_t) config-> + cfgData); + + case DRX_CFG_AUD_RDS: + return AUDCtrlGetCfgRDS(demod, + (pDRXCfgAudRDS_t) config->cfgData); + case DRX_CFG_AUD_AUTOSOUND: + return AUDCtrlGetCfgAutoSound(demod, + (pDRXCfgAudAutoSound_t) config-> + cfgData); + case DRX_CFG_AUD_ASS_THRES: + return AUDCtrlGetCfgASSThres(demod, + (pDRXCfgAudASSThres_t) config-> + cfgData); + case DRX_CFG_AUD_CARRIER: + return AUDCtrlGetCfgCarrier(demod, + (pDRXCfgAudCarriers_t) config-> + cfgData); + case DRX_CFG_AUD_DEVIATION: + return AUDCtrlGetCfgDev(demod, + (pDRXCfgAudDeviation_t) config-> + cfgData); + case DRX_CFG_AUD_PRESCALE: + return AUDCtrlGetCfgPrescale(demod, + (pDRXCfgAudPrescale_t) config-> + cfgData); + case DRX_CFG_AUD_MIXER: + return AUDCtrlGetCfgMixer(demod, + (pDRXCfgAudMixer_t) config->cfgData); + case DRX_CFG_AUD_AVSYNC: + return AUDCtrlGetCfgAVSync(demod, + (pDRXCfgAudAVSync_t) config-> + cfgData); #endif - default: - return (DRX_STS_INVALID_ARG); - } + default: + return (DRX_STS_INVALID_ARG); + } - return (DRX_STS_OK); + return (DRX_STS_OK); rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /*============================================================================= @@ -16225,216 +15521,214 @@ rw_error: * rely on SCU or AUD ucode to be present. * */ -DRXStatus_t -DRXJ_Open(pDRXDemodInstance_t demod) +DRXStatus_t DRXJ_Open(pDRXDemodInstance_t demod) { - pI2CDeviceAddr_t devAddr = NULL; - pDRXJData_t extAttr = NULL; - pDRXCommonAttr_t commonAttr = NULL; - u32_t driverVersion = 0; - DRXUCodeInfo_t ucodeInfo; - DRXCfgMPEGOutput_t cfgMPEGOutput; - - /* Check arguments */ - if (demod -> myExtAttr == NULL ) - { - return ( DRX_STS_INVALID_ARG); - } + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + pDRXCommonAttr_t commonAttr = NULL; + u32_t driverVersion = 0; + DRXUCodeInfo_t ucodeInfo; + DRXCfgMPEGOutput_t cfgMPEGOutput; + + /* Check arguments */ + if (demod->myExtAttr == NULL) { + return (DRX_STS_INVALID_ARG); + } - devAddr = demod -> myI2CDevAddr; - extAttr = (pDRXJData_t) demod -> myExtAttr; - commonAttr = (pDRXCommonAttr_t) demod -> myCommonAttr; + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; + commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; - CHK_ERROR(PowerUpDevice(demod)); - commonAttr->currentPowerMode = DRX_POWER_UP; + CHK_ERROR(PowerUpDevice(demod)); + commonAttr->currentPowerMode = DRX_POWER_UP; - /* has to be in front of setIqmAf and setOrxNsuAox */ - CHK_ERROR(GetDeviceCapabilities(demod)); + /* has to be in front of setIqmAf and setOrxNsuAox */ + CHK_ERROR(GetDeviceCapabilities(demod)); - /* Soft reset of sys- and osc-clockdomain */ - WR16( devAddr, SIO_CC_SOFT_RST__A, ( SIO_CC_SOFT_RST_SYS__M | - SIO_CC_SOFT_RST_OSC__M ) ); - WR16( devAddr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); - CHK_ERROR( DRXBSP_HST_Sleep(1) ); + /* Soft reset of sys- and osc-clockdomain */ + WR16(devAddr, SIO_CC_SOFT_RST__A, (SIO_CC_SOFT_RST_SYS__M | + SIO_CC_SOFT_RST_OSC__M)); + WR16(devAddr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); + CHK_ERROR(DRXBSP_HST_Sleep(1)); - /* TODO first make sure that everything keeps working before enabling this */ - /* PowerDownAnalogBlocks() */ - WR16( devAddr, ATV_TOP_STDBY__A, (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE) - |ATV_TOP_STDBY_SIF_STDBY_STANDBY ); + /* TODO first make sure that everything keeps working before enabling this */ + /* PowerDownAnalogBlocks() */ + WR16(devAddr, ATV_TOP_STDBY__A, (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE) + | ATV_TOP_STDBY_SIF_STDBY_STANDBY); - CHK_ERROR( SetIqmAf( demod, FALSE ) ); - CHK_ERROR( SetOrxNsuAox( demod, FALSE ) ); + CHK_ERROR(SetIqmAf(demod, FALSE)); + CHK_ERROR(SetOrxNsuAox(demod, FALSE)); - CHK_ERROR(InitHI(demod) ); + CHK_ERROR(InitHI(demod)); - /* disable mpegoutput pins */ - cfgMPEGOutput.enableMPEGOutput = FALSE; - CHK_ERROR( CtrlSetCfgMPEGOutput( demod, &cfgMPEGOutput) ); - /* Stop AUD Inform SetAudio it will need to do all setting */ - CHK_ERROR( PowerDownAud(demod) ); - /* Stop SCU */ - WR16( devAddr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP); + /* disable mpegoutput pins */ + cfgMPEGOutput.enableMPEGOutput = FALSE; + CHK_ERROR(CtrlSetCfgMPEGOutput(demod, &cfgMPEGOutput)); + /* Stop AUD Inform SetAudio it will need to do all setting */ + CHK_ERROR(PowerDownAud(demod)); + /* Stop SCU */ + WR16(devAddr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP); - /* Upload microcode */ - if ( commonAttr->microcode != NULL ) - { - /* Dirty trick to use common ucode upload & verify, - pretend device is already open */ - commonAttr->isOpened = TRUE; - ucodeInfo.mcData = commonAttr->microcode; - ucodeInfo.mcSize = commonAttr->microcodeSize; + /* Upload microcode */ + if (commonAttr->microcode != NULL) { + /* Dirty trick to use common ucode upload & verify, + pretend device is already open */ + commonAttr->isOpened = TRUE; + ucodeInfo.mcData = commonAttr->microcode; + ucodeInfo.mcSize = commonAttr->microcodeSize; #ifdef DRXJ_SPLIT_UCODE_UPLOAD - /* Upload microcode without audio part */ - CHK_ERROR( CtrlUCodeUpload( demod, &ucodeInfo, UCODE_UPLOAD, FALSE ) ); + /* Upload microcode without audio part */ + CHK_ERROR(CtrlUCodeUpload + (demod, &ucodeInfo, UCODE_UPLOAD, FALSE)); #else - CHK_ERROR( DRX_Ctrl( demod, DRX_CTRL_LOAD_UCODE, &ucodeInfo) ); + CHK_ERROR(DRX_Ctrl(demod, DRX_CTRL_LOAD_UCODE, &ucodeInfo)); #endif /* DRXJ_SPLIT_UCODE_UPLOAD */ - if ( commonAttr->verifyMicrocode == TRUE ) - { + if (commonAttr->verifyMicrocode == TRUE) { #ifdef DRXJ_SPLIT_UCODE_UPLOAD - CHK_ERROR( CtrlUCodeUpload( demod, &ucodeInfo, UCODE_VERIFY, FALSE ) ); + CHK_ERROR(CtrlUCodeUpload + (demod, &ucodeInfo, UCODE_VERIFY, FALSE)); #else - CHK_ERROR( DRX_Ctrl ( demod, DRX_CTRL_VERIFY_UCODE, &ucodeInfo) ); + CHK_ERROR(DRX_Ctrl + (demod, DRX_CTRL_VERIFY_UCODE, &ucodeInfo)); #endif /* DRXJ_SPLIT_UCODE_UPLOAD */ - } - commonAttr->isOpened = FALSE; - } + } + commonAttr->isOpened = FALSE; + } - /* Run SCU for a little while to initialize microcode version numbers */ - WR16( devAddr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); + /* Run SCU for a little while to initialize microcode version numbers */ + WR16(devAddr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); - /* Open tuner instance */ - if ( demod->myTuner != NULL ) - { - demod->myTuner->myCommonAttr->myUserData = (void *)demod; - - if ( commonAttr->tunerPortNr == 1 ) - { - Bool_t bridgeClosed = TRUE; - CHK_ERROR( CtrlI2CBridge( demod, &bridgeClosed ) ); - } - - CHK_ERROR( DRXBSP_TUNER_Open( demod -> myTuner ) ); - - if ( commonAttr->tunerPortNr == 1 ) - { - Bool_t bridgeClosed = FALSE; - CHK_ERROR( CtrlI2CBridge( demod, &bridgeClosed ) ); - } - commonAttr->tunerMinFreqRF = ((demod->myTuner)->myCommonAttr->minFreqRF); - commonAttr->tunerMaxFreqRF = ((demod->myTuner)->myCommonAttr->maxFreqRF); - } - - /* Initialize scan timeout */ - commonAttr -> scanDemodLockTimeout = DRXJ_SCAN_TIMEOUT; - commonAttr -> scanDesiredLock = DRX_LOCKED; - - /* Initialize default AFE configuartion for QAM */ - if (extAttr->hasLNA) - { - /* IF AGC off, PGA active */ + /* Open tuner instance */ + if (demod->myTuner != NULL) { + demod->myTuner->myCommonAttr->myUserData = (void *)demod; + + if (commonAttr->tunerPortNr == 1) { + Bool_t bridgeClosed = TRUE; + CHK_ERROR(CtrlI2CBridge(demod, &bridgeClosed)); + } + + CHK_ERROR(DRXBSP_TUNER_Open(demod->myTuner)); + + if (commonAttr->tunerPortNr == 1) { + Bool_t bridgeClosed = FALSE; + CHK_ERROR(CtrlI2CBridge(demod, &bridgeClosed)); + } + commonAttr->tunerMinFreqRF = + ((demod->myTuner)->myCommonAttr->minFreqRF); + commonAttr->tunerMaxFreqRF = + ((demod->myTuner)->myCommonAttr->maxFreqRF); + } + + /* Initialize scan timeout */ + commonAttr->scanDemodLockTimeout = DRXJ_SCAN_TIMEOUT; + commonAttr->scanDesiredLock = DRX_LOCKED; + + /* Initialize default AFE configuartion for QAM */ + if (extAttr->hasLNA) { + /* IF AGC off, PGA active */ #ifndef DRXJ_VSB_ONLY - extAttr->qamIfAgcCfg.standard = DRX_STANDARD_ITU_B; - extAttr->qamIfAgcCfg.ctrlMode = DRX_AGC_CTRL_OFF; - extAttr->qamPgaCfg = 140+(11*13); + extAttr->qamIfAgcCfg.standard = DRX_STANDARD_ITU_B; + extAttr->qamIfAgcCfg.ctrlMode = DRX_AGC_CTRL_OFF; + extAttr->qamPgaCfg = 140 + (11 * 13); #endif - extAttr->vsbIfAgcCfg.standard = DRX_STANDARD_8VSB; - extAttr->vsbIfAgcCfg.ctrlMode = DRX_AGC_CTRL_OFF; - extAttr->vsbPgaCfg = 140+(11*13); - } else { - /* IF AGC on, PGA not active */ + extAttr->vsbIfAgcCfg.standard = DRX_STANDARD_8VSB; + extAttr->vsbIfAgcCfg.ctrlMode = DRX_AGC_CTRL_OFF; + extAttr->vsbPgaCfg = 140 + (11 * 13); + } else { + /* IF AGC on, PGA not active */ #ifndef DRXJ_VSB_ONLY - extAttr->qamIfAgcCfg.standard = DRX_STANDARD_ITU_B; - extAttr->qamIfAgcCfg.ctrlMode = DRX_AGC_CTRL_AUTO; - extAttr->qamIfAgcCfg.minOutputLevel = 0; - extAttr->qamIfAgcCfg.maxOutputLevel = 0x7FFF; - extAttr->qamIfAgcCfg.speed = 3; - extAttr->qamIfAgcCfg.top = 1297; - extAttr->qamPgaCfg = 140; + extAttr->qamIfAgcCfg.standard = DRX_STANDARD_ITU_B; + extAttr->qamIfAgcCfg.ctrlMode = DRX_AGC_CTRL_AUTO; + extAttr->qamIfAgcCfg.minOutputLevel = 0; + extAttr->qamIfAgcCfg.maxOutputLevel = 0x7FFF; + extAttr->qamIfAgcCfg.speed = 3; + extAttr->qamIfAgcCfg.top = 1297; + extAttr->qamPgaCfg = 140; #endif - extAttr->vsbIfAgcCfg.standard = DRX_STANDARD_8VSB; - extAttr->vsbIfAgcCfg.ctrlMode = DRX_AGC_CTRL_AUTO; - extAttr->vsbIfAgcCfg.minOutputLevel = 0; - extAttr->vsbIfAgcCfg.maxOutputLevel = 0x7FFF; - extAttr->vsbIfAgcCfg.speed = 3; - extAttr->vsbIfAgcCfg.top = 1024; - extAttr->vsbPgaCfg = 140; - } - /* TODO: remove minOutputLevel and maxOutputLevel for both QAM and VSB after */ - /* mc has not used them */ + extAttr->vsbIfAgcCfg.standard = DRX_STANDARD_8VSB; + extAttr->vsbIfAgcCfg.ctrlMode = DRX_AGC_CTRL_AUTO; + extAttr->vsbIfAgcCfg.minOutputLevel = 0; + extAttr->vsbIfAgcCfg.maxOutputLevel = 0x7FFF; + extAttr->vsbIfAgcCfg.speed = 3; + extAttr->vsbIfAgcCfg.top = 1024; + extAttr->vsbPgaCfg = 140; + } + /* TODO: remove minOutputLevel and maxOutputLevel for both QAM and VSB after */ + /* mc has not used them */ #ifndef DRXJ_VSB_ONLY - extAttr->qamRfAgcCfg.standard = DRX_STANDARD_ITU_B; - extAttr->qamRfAgcCfg.ctrlMode = DRX_AGC_CTRL_AUTO; - extAttr->qamRfAgcCfg.minOutputLevel = 0; - extAttr->qamRfAgcCfg.maxOutputLevel = 0x7FFF; - extAttr->qamRfAgcCfg.speed = 3; - extAttr->qamRfAgcCfg.top = 9500; - extAttr->qamRfAgcCfg.cutOffCurrent = 4000; - extAttr->qamPreSawCfg.standard = DRX_STANDARD_ITU_B; - extAttr->qamPreSawCfg.reference = 0x07; - extAttr->qamPreSawCfg.usePreSaw = TRUE; + extAttr->qamRfAgcCfg.standard = DRX_STANDARD_ITU_B; + extAttr->qamRfAgcCfg.ctrlMode = DRX_AGC_CTRL_AUTO; + extAttr->qamRfAgcCfg.minOutputLevel = 0; + extAttr->qamRfAgcCfg.maxOutputLevel = 0x7FFF; + extAttr->qamRfAgcCfg.speed = 3; + extAttr->qamRfAgcCfg.top = 9500; + extAttr->qamRfAgcCfg.cutOffCurrent = 4000; + extAttr->qamPreSawCfg.standard = DRX_STANDARD_ITU_B; + extAttr->qamPreSawCfg.reference = 0x07; + extAttr->qamPreSawCfg.usePreSaw = TRUE; #endif - /* Initialize default AFE configuartion for VSB */ - extAttr->vsbRfAgcCfg.standard = DRX_STANDARD_8VSB; - extAttr->vsbRfAgcCfg.ctrlMode = DRX_AGC_CTRL_AUTO; - extAttr->vsbRfAgcCfg.minOutputLevel = 0; - extAttr->vsbRfAgcCfg.maxOutputLevel = 0x7FFF; - extAttr->vsbRfAgcCfg.speed = 3; - extAttr->vsbRfAgcCfg.top = 9500; - extAttr->vsbRfAgcCfg.cutOffCurrent = 4000; - extAttr->vsbPreSawCfg.standard = DRX_STANDARD_8VSB; - extAttr->vsbPreSawCfg.reference = 0x07; - extAttr->vsbPreSawCfg.usePreSaw = TRUE; + /* Initialize default AFE configuartion for VSB */ + extAttr->vsbRfAgcCfg.standard = DRX_STANDARD_8VSB; + extAttr->vsbRfAgcCfg.ctrlMode = DRX_AGC_CTRL_AUTO; + extAttr->vsbRfAgcCfg.minOutputLevel = 0; + extAttr->vsbRfAgcCfg.maxOutputLevel = 0x7FFF; + extAttr->vsbRfAgcCfg.speed = 3; + extAttr->vsbRfAgcCfg.top = 9500; + extAttr->vsbRfAgcCfg.cutOffCurrent = 4000; + extAttr->vsbPreSawCfg.standard = DRX_STANDARD_8VSB; + extAttr->vsbPreSawCfg.reference = 0x07; + extAttr->vsbPreSawCfg.usePreSaw = TRUE; #ifndef DRXJ_DIGITAL_ONLY - /* Initialize default AFE configuartion for ATV */ - extAttr->atvRfAgcCfg.standard = DRX_STANDARD_NTSC; - extAttr->atvRfAgcCfg.ctrlMode = DRX_AGC_CTRL_AUTO; - extAttr->atvRfAgcCfg.top = 9500; - extAttr->atvRfAgcCfg.cutOffCurrent = 4000; - extAttr->atvRfAgcCfg.speed = 3; - extAttr->atvIfAgcCfg.standard = DRX_STANDARD_NTSC; - extAttr->atvIfAgcCfg.ctrlMode = DRX_AGC_CTRL_AUTO; - extAttr->atvIfAgcCfg.speed = 3; - extAttr->atvIfAgcCfg.top = 2400; - extAttr->atvPreSawCfg.reference = 0x0007; - extAttr->atvPreSawCfg.usePreSaw = TRUE; - extAttr->atvPreSawCfg.standard = DRX_STANDARD_NTSC; + /* Initialize default AFE configuartion for ATV */ + extAttr->atvRfAgcCfg.standard = DRX_STANDARD_NTSC; + extAttr->atvRfAgcCfg.ctrlMode = DRX_AGC_CTRL_AUTO; + extAttr->atvRfAgcCfg.top = 9500; + extAttr->atvRfAgcCfg.cutOffCurrent = 4000; + extAttr->atvRfAgcCfg.speed = 3; + extAttr->atvIfAgcCfg.standard = DRX_STANDARD_NTSC; + extAttr->atvIfAgcCfg.ctrlMode = DRX_AGC_CTRL_AUTO; + extAttr->atvIfAgcCfg.speed = 3; + extAttr->atvIfAgcCfg.top = 2400; + extAttr->atvPreSawCfg.reference = 0x0007; + extAttr->atvPreSawCfg.usePreSaw = TRUE; + extAttr->atvPreSawCfg.standard = DRX_STANDARD_NTSC; #endif - extAttr->standard=DRX_STANDARD_UNKNOWN; - - CHK_ERROR(SmartAntInit(demod)); - - /* Stamp driver version number in SCU data RAM in BCD code - Done to enable field application engineers to retreive drxdriver version - via I2C from SCU RAM - */ - driverVersion = (VERSION_MAJOR/100) % 10; - driverVersion <<= 4; - driverVersion += (VERSION_MAJOR/10) % 10; - driverVersion <<= 4; - driverVersion += (VERSION_MAJOR%10); - driverVersion <<= 4; - driverVersion += (VERSION_MINOR%10); - driverVersion <<= 4; - driverVersion += (VERSION_PATCH/1000) % 10; - driverVersion <<= 4; - driverVersion += (VERSION_PATCH/100) % 10; - driverVersion <<= 4; - driverVersion += (VERSION_PATCH/10) % 10; - driverVersion <<= 4; - driverVersion += (VERSION_PATCH%10); - WR16(devAddr, SCU_RAM_DRIVER_VER_HI__A, (u16_t)(driverVersion>>16) ); - WR16(devAddr, SCU_RAM_DRIVER_VER_LO__A, (u16_t)(driverVersion&0xFFFF) ); - - /* refresh the audio data structure with default */ - extAttr->audData = DRXJDefaultAudData_g; - - return ( DRX_STS_OK ); + extAttr->standard = DRX_STANDARD_UNKNOWN; + + CHK_ERROR(SmartAntInit(demod)); + + /* Stamp driver version number in SCU data RAM in BCD code + Done to enable field application engineers to retreive drxdriver version + via I2C from SCU RAM + */ + driverVersion = (VERSION_MAJOR / 100) % 10; + driverVersion <<= 4; + driverVersion += (VERSION_MAJOR / 10) % 10; + driverVersion <<= 4; + driverVersion += (VERSION_MAJOR % 10); + driverVersion <<= 4; + driverVersion += (VERSION_MINOR % 10); + driverVersion <<= 4; + driverVersion += (VERSION_PATCH / 1000) % 10; + driverVersion <<= 4; + driverVersion += (VERSION_PATCH / 100) % 10; + driverVersion <<= 4; + driverVersion += (VERSION_PATCH / 10) % 10; + driverVersion <<= 4; + driverVersion += (VERSION_PATCH % 10); + WR16(devAddr, SCU_RAM_DRIVER_VER_HI__A, (u16_t) (driverVersion >> 16)); + WR16(devAddr, SCU_RAM_DRIVER_VER_LO__A, + (u16_t) (driverVersion & 0xFFFF)); + + /* refresh the audio data structure with default */ + extAttr->audData = DRXJDefaultAudData_g; + + return (DRX_STS_OK); rw_error: - commonAttr->isOpened = FALSE; - return (DRX_STS_ERROR); + commonAttr->isOpened = FALSE; + return (DRX_STS_ERROR); } /*============================================================================*/ @@ -16444,44 +15738,40 @@ rw_error: * \return Status_t Return status. * */ -DRXStatus_t -DRXJ_Close(pDRXDemodInstance_t demod) +DRXStatus_t DRXJ_Close(pDRXDemodInstance_t demod) { - pI2CDeviceAddr_t devAddr =NULL; - pDRXJData_t extAttr =NULL; - pDRXCommonAttr_t commonAttr =NULL; - DRXPowerMode_t powerMode =DRX_POWER_UP; + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + pDRXCommonAttr_t commonAttr = NULL; + DRXPowerMode_t powerMode = DRX_POWER_UP; - commonAttr = (pDRXCommonAttr_t) demod -> myCommonAttr; - devAddr = demod -> myI2CDevAddr; - extAttr = (pDRXJData_t) demod -> myExtAttr; + commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; - /* power up */ - CHK_ERROR( CtrlPowerMode( demod, &powerMode )); + /* power up */ + CHK_ERROR(CtrlPowerMode(demod, &powerMode)); - if ( demod->myTuner != NULL ) - { - /* Check if bridge is used */ - if ( commonAttr->tunerPortNr == 1 ) - { - Bool_t bridgeClosed = TRUE; - CHK_ERROR( CtrlI2CBridge( demod, &bridgeClosed ) ); - } - CHK_ERROR( DRXBSP_TUNER_Close( demod -> myTuner ) ); - if ( commonAttr->tunerPortNr == 1 ) - { - Bool_t bridgeClosed = FALSE; - CHK_ERROR( CtrlI2CBridge( demod, &bridgeClosed ) ); - } - }; - - WR16( devAddr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); - powerMode =DRX_POWER_DOWN; - CHK_ERROR( CtrlPowerMode( demod, &powerMode )); - - return DRX_STS_OK; + if (demod->myTuner != NULL) { + /* Check if bridge is used */ + if (commonAttr->tunerPortNr == 1) { + Bool_t bridgeClosed = TRUE; + CHK_ERROR(CtrlI2CBridge(demod, &bridgeClosed)); + } + CHK_ERROR(DRXBSP_TUNER_Close(demod->myTuner)); + if (commonAttr->tunerPortNr == 1) { + Bool_t bridgeClosed = FALSE; + CHK_ERROR(CtrlI2CBridge(demod, &bridgeClosed)); + } + }; + + WR16(devAddr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); + powerMode = DRX_POWER_DOWN; + CHK_ERROR(CtrlPowerMode(demod, &powerMode)); + + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return (DRX_STS_ERROR); } /*============================================================================*/ @@ -16491,187 +15781,194 @@ rw_error: * \return Status_t Return status. */ DRXStatus_t -DRXJ_Ctrl(pDRXDemodInstance_t demod, DRXCtrlIndex_t ctrl, - void *ctrlData) +DRXJ_Ctrl(pDRXDemodInstance_t demod, DRXCtrlIndex_t ctrl, void *ctrlData) { - switch ( ctrl ) { + switch (ctrl) { /*======================================================================*/ - case DRX_CTRL_SET_CHANNEL: - { - return CtrlSetChannel ( demod, - (pDRXChannel_t) ctrlData ); - } - break; + case DRX_CTRL_SET_CHANNEL: + { + return CtrlSetChannel(demod, (pDRXChannel_t) ctrlData); + } + break; /*======================================================================*/ - case DRX_CTRL_GET_CHANNEL: - { - return CtrlGetChannel ( demod, - (pDRXChannel_t) ctrlData ); - } - break; + case DRX_CTRL_GET_CHANNEL: + { + return CtrlGetChannel(demod, (pDRXChannel_t) ctrlData); + } + break; /*======================================================================*/ - case DRX_CTRL_SIG_QUALITY: - { - return CtrlSigQuality ( demod, - (pDRXSigQuality_t) ctrlData); - } - break; + case DRX_CTRL_SIG_QUALITY: + { + return CtrlSigQuality(demod, + (pDRXSigQuality_t) ctrlData); + } + break; /*======================================================================*/ - case DRX_CTRL_SIG_STRENGTH: - { - return CtrlSigStrength ( demod, - (pu16_t) ctrlData); - } - break; + case DRX_CTRL_SIG_STRENGTH: + { + return CtrlSigStrength(demod, (pu16_t) ctrlData); + } + break; /*======================================================================*/ - case DRX_CTRL_CONSTEL: - { - return CtrlConstel ( demod, - (pDRXComplex_t) ctrlData); - } - break; + case DRX_CTRL_CONSTEL: + { + return CtrlConstel(demod, (pDRXComplex_t) ctrlData); + } + break; /*======================================================================*/ - case DRX_CTRL_SET_CFG: - { - return CtrlSetCfg ( demod, - (pDRXCfg_t) ctrlData); - } - break; + case DRX_CTRL_SET_CFG: + { + return CtrlSetCfg(demod, (pDRXCfg_t) ctrlData); + } + break; /*======================================================================*/ - case DRX_CTRL_GET_CFG: - { - return CtrlGetCfg ( demod, (pDRXCfg_t) ctrlData); - } - break; + case DRX_CTRL_GET_CFG: + { + return CtrlGetCfg(demod, (pDRXCfg_t) ctrlData); + } + break; /*======================================================================*/ - case DRX_CTRL_I2C_BRIDGE: - { - return CtrlI2CBridge( demod, (pBool_t) ctrlData ); - } - break; + case DRX_CTRL_I2C_BRIDGE: + { + return CtrlI2CBridge(demod, (pBool_t) ctrlData); + } + break; /*======================================================================*/ - case DRX_CTRL_LOCK_STATUS: - { - return CtrlLockStatus( demod, (pDRXLockStatus_t) ctrlData ); - } - break; + case DRX_CTRL_LOCK_STATUS: + { + return CtrlLockStatus(demod, + (pDRXLockStatus_t) ctrlData); + } + break; /*======================================================================*/ - case DRX_CTRL_SET_STANDARD: - { - return CtrlSetStandard( demod, (pDRXStandard_t) ctrlData ); - } - break; + case DRX_CTRL_SET_STANDARD: + { + return CtrlSetStandard(demod, + (pDRXStandard_t) ctrlData); + } + break; /*======================================================================*/ - case DRX_CTRL_GET_STANDARD: - { - return CtrlGetStandard( demod, (pDRXStandard_t) ctrlData ); - } - break; + case DRX_CTRL_GET_STANDARD: + { + return CtrlGetStandard(demod, + (pDRXStandard_t) ctrlData); + } + break; /*======================================================================*/ - case DRX_CTRL_POWER_MODE: - { - return CtrlPowerMode( demod, (pDRXPowerMode_t) ctrlData ); - } - break; + case DRX_CTRL_POWER_MODE: + { + return CtrlPowerMode(demod, (pDRXPowerMode_t) ctrlData); + } + break; /*======================================================================*/ - case DRX_CTRL_VERSION: - { - return CtrlVersion( demod, (pDRXVersionList_t *) ctrlData ); - } - break; + case DRX_CTRL_VERSION: + { + return CtrlVersion(demod, + (pDRXVersionList_t *) ctrlData); + } + break; /*======================================================================*/ - case DRX_CTRL_PROBE_DEVICE: - { - return CtrlProbeDevice( demod ); - } - break; + case DRX_CTRL_PROBE_DEVICE: + { + return CtrlProbeDevice(demod); + } + break; /*======================================================================*/ - case DRX_CTRL_SET_OOB: - { - return CtrlSetOOB( demod, (pDRXOOB_t) ctrlData ); - } - break; + case DRX_CTRL_SET_OOB: + { + return CtrlSetOOB(demod, (pDRXOOB_t) ctrlData); + } + break; /*======================================================================*/ - case DRX_CTRL_GET_OOB: - { - return CtrlGetOOB( demod, (pDRXOOBStatus_t) ctrlData ); - } - break; + case DRX_CTRL_GET_OOB: + { + return CtrlGetOOB(demod, (pDRXOOBStatus_t) ctrlData); + } + break; /*======================================================================*/ - case DRX_CTRL_SET_UIO_CFG: - { - return CtrlSetUIOCfg( demod, (pDRXUIOCfg_t) ctrlData ); - } - break; + case DRX_CTRL_SET_UIO_CFG: + { + return CtrlSetUIOCfg(demod, (pDRXUIOCfg_t) ctrlData); + } + break; /*======================================================================*/ - case DRX_CTRL_GET_UIO_CFG: - { - return CtrlGetUIOCfg( demod, (pDRXUIOCfg_t) ctrlData ); - } - break; + case DRX_CTRL_GET_UIO_CFG: + { + return CtrlGetUIOCfg(demod, (pDRXUIOCfg_t) ctrlData); + } + break; /*======================================================================*/ - case DRX_CTRL_UIO_READ: - { - return CtrlUIORead( demod, (pDRXUIOData_t) ctrlData ); - } - break; + case DRX_CTRL_UIO_READ: + { + return CtrlUIORead(demod, (pDRXUIOData_t) ctrlData); + } + break; /*======================================================================*/ - case DRX_CTRL_UIO_WRITE: - { - return CtrlUIOWrite( demod, (pDRXUIOData_t) ctrlData ); - } - break; + case DRX_CTRL_UIO_WRITE: + { + return CtrlUIOWrite(demod, (pDRXUIOData_t) ctrlData); + } + break; /*======================================================================*/ - case DRX_CTRL_AUD_SET_STANDARD: - { - return AUDCtrlSetStandard( demod, (pDRXAudStandard_t) ctrlData ); - } - break; + case DRX_CTRL_AUD_SET_STANDARD: + { + return AUDCtrlSetStandard(demod, + (pDRXAudStandard_t) ctrlData); + } + break; /*======================================================================*/ - case DRX_CTRL_AUD_GET_STANDARD: - { - return AUDCtrlGetStandard( demod, (pDRXAudStandard_t) ctrlData ); - } - break; + case DRX_CTRL_AUD_GET_STANDARD: + { + return AUDCtrlGetStandard(demod, + (pDRXAudStandard_t) ctrlData); + } + break; /*======================================================================*/ - case DRX_CTRL_AUD_GET_STATUS: - { - return AUDCtrlGetStatus( demod, (pDRXAudStatus_t) ctrlData ); - } - break; + case DRX_CTRL_AUD_GET_STATUS: + { + return AUDCtrlGetStatus(demod, + (pDRXAudStatus_t) ctrlData); + } + break; /*======================================================================*/ - case DRX_CTRL_AUD_BEEP: - { - return AUDCtrlBeep( demod, (pDRXAudBeep_t) ctrlData ); - } - break; + case DRX_CTRL_AUD_BEEP: + { + return AUDCtrlBeep(demod, (pDRXAudBeep_t) ctrlData); + } + break; /*======================================================================*/ - case DRX_CTRL_I2C_READWRITE: - { - return CtrlI2CWriteRead( demod, (pDRXI2CData_t) ctrlData ); - } - break; + case DRX_CTRL_I2C_READWRITE: + { + return CtrlI2CWriteRead(demod, + (pDRXI2CData_t) ctrlData); + } + break; #ifdef DRXJ_SPLIT_UCODE_UPLOAD - case DRX_CTRL_LOAD_UCODE: - { - return CtrlUCodeUpload( demod, (pDRXUCodeInfo_t) ctrlData, UCODE_UPLOAD, FALSE ); - } - break; - case DRX_CTRL_VERIFY_UCODE: - { - return CtrlUCodeUpload( demod, (pDRXUCodeInfo_t) ctrlData, UCODE_VERIFY, FALSE ); - } - break; + case DRX_CTRL_LOAD_UCODE: + { + return CtrlUCodeUpload(demod, + (pDRXUCodeInfo_t) ctrlData, + UCODE_UPLOAD, FALSE); + } + break; + case DRX_CTRL_VERIFY_UCODE: + { + return CtrlUCodeUpload(demod, + (pDRXUCodeInfo_t) ctrlData, + UCODE_VERIFY, FALSE); + } + break; #endif /* DRXJ_SPLIT_UCODE_UPLOAD */ - case DRX_CTRL_VALIDATE_UCODE: - { - return CtrlValidateUCode (demod); - } - break; - default: - return (DRX_STS_FUNC_NOT_AVAILABLE); - } - return (DRX_STS_OK); + case DRX_CTRL_VALIDATE_UCODE: + { + return CtrlValidateUCode(demod); + } + break; + default: + return (DRX_STS_FUNC_NOT_AVAILABLE); + } + return (DRX_STS_OK); } + /* END OF FILE */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.h b/drivers/media/dvb-frontends/drx39xyj/drxj.h index cb6cc3f..b9e51b4 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.h +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.h @@ -55,8 +55,8 @@ extern "C" { cannot be done with short addr only in multi master mode. */ #if ((DRXDAP_SINGLE_MASTER==0)&&(DRXDAPFASI_LONG_ADDR_ALLOWED==0)) #error "Multi master mode and short addressing only is an illegal combination" -*; /* Generate a fatal compiler error to make sure it stops here, - this is necesarry because not all compilers stop after a #error. */ + *; /* Generate a fatal compiler error to make sure it stops here, + this is necesarry because not all compilers stop after a #error. */ #endif /*------------------------------------------------------------------------- @@ -74,14 +74,18 @@ TYPEDEFS /*============================================================================*/ /*============================================================================*/ -typedef struct { - u16_t command; /**< Command number */ - u16_t parameterLen; /**< Data length in byte */ - u16_t resultLen; /**< result length in byte */ - u16_t *parameter; /**< General purpous param */ - u16_t *result; /**< General purpous param */ -} DRXJSCUCmd_t, *pDRXJSCUCmd_t; - + typedef struct { + u16_t command; + /**< Command number */ + u16_t parameterLen; + /**< Data length in byte */ + u16_t resultLen; + /**< result length in byte */ + u16_t *parameter; + /**< General purpous param */ + u16_t *result; + /**< General purpous param */ + } DRXJSCUCmd_t, *pDRXJSCUCmd_t; /*============================================================================*/ /*============================================================================*/ @@ -93,8 +97,8 @@ typedef struct { #define DRXJ_DEMOD_LOCK (DRX_LOCK_STATE_1) /* OOB lock states */ -#define DRXJ_OOB_AGC_LOCK (DRX_LOCK_STATE_1) /* analog gain control lock */ -#define DRXJ_OOB_SYNC_LOCK (DRX_LOCK_STATE_2) /* digital gain control lock */ +#define DRXJ_OOB_AGC_LOCK (DRX_LOCK_STATE_1) /* analog gain control lock */ +#define DRXJ_OOB_SYNC_LOCK (DRX_LOCK_STATE_2) /* digital gain control lock */ /* Intermediate powermodes for DRXJ */ #define DRXJ_POWER_DOWN_MAIN_PATH DRX_POWER_MODE_8 @@ -107,62 +111,61 @@ typedef struct { /*#define DRX_CTRL_BASE (0x0000)*/ #define DRXJ_CTRL_CFG_BASE (0x1000) -typedef enum { - DRXJ_CFG_AGC_RF = DRXJ_CTRL_CFG_BASE, - DRXJ_CFG_AGC_IF, - DRXJ_CFG_AGC_INTERNAL, - DRXJ_CFG_PRE_SAW, - DRXJ_CFG_AFE_GAIN, - DRXJ_CFG_SYMBOL_CLK_OFFSET, - DRXJ_CFG_ACCUM_CR_RS_CW_ERR, - DRXJ_CFG_FEC_MERS_SEQ_COUNT, - DRXJ_CFG_OOB_MISC, - DRXJ_CFG_SMART_ANT, - DRXJ_CFG_OOB_PRE_SAW, - DRXJ_CFG_VSB_MISC, - DRXJ_CFG_RESET_PACKET_ERR, - - /* ATV (FM) */ - DRXJ_CFG_ATV_OUTPUT, /* also for FM (SIF control) but not likely */ - DRXJ_CFG_ATV_MISC, - DRXJ_CFG_ATV_EQU_COEF, - DRXJ_CFG_ATV_AGC_STATUS, /* also for FM ( IF,RF, audioAGC ) */ - - DRXJ_CFG_MPEG_OUTPUT_MISC, - DRXJ_CFG_HW_CFG, - DRXJ_CFG_OOB_LO_POW, - - DRXJ_CFG_MAX /* dummy, never to be used */ - -} DRXJCfgType_t, *pDRXJCfgType_t; + typedef enum { + DRXJ_CFG_AGC_RF = DRXJ_CTRL_CFG_BASE, + DRXJ_CFG_AGC_IF, + DRXJ_CFG_AGC_INTERNAL, + DRXJ_CFG_PRE_SAW, + DRXJ_CFG_AFE_GAIN, + DRXJ_CFG_SYMBOL_CLK_OFFSET, + DRXJ_CFG_ACCUM_CR_RS_CW_ERR, + DRXJ_CFG_FEC_MERS_SEQ_COUNT, + DRXJ_CFG_OOB_MISC, + DRXJ_CFG_SMART_ANT, + DRXJ_CFG_OOB_PRE_SAW, + DRXJ_CFG_VSB_MISC, + DRXJ_CFG_RESET_PACKET_ERR, + + /* ATV (FM) */ + DRXJ_CFG_ATV_OUTPUT, /* also for FM (SIF control) but not likely */ + DRXJ_CFG_ATV_MISC, + DRXJ_CFG_ATV_EQU_COEF, + DRXJ_CFG_ATV_AGC_STATUS, /* also for FM ( IF,RF, audioAGC ) */ + + DRXJ_CFG_MPEG_OUTPUT_MISC, + DRXJ_CFG_HW_CFG, + DRXJ_CFG_OOB_LO_POW, + + DRXJ_CFG_MAX /* dummy, never to be used */ + } DRXJCfgType_t, *pDRXJCfgType_t; /** * /struct DRXJCfgSmartAntIO_t * smart antenna i/o. */ -typedef enum DRXJCfgSmartAntIO_t { - DRXJ_SMT_ANT_OUTPUT = 0, - DRXJ_SMT_ANT_INPUT -} DRXJCfgSmartAntIO_t, *pDRXJCfgSmartAntIO_t; + typedef enum DRXJCfgSmartAntIO_t { + DRXJ_SMT_ANT_OUTPUT = 0, + DRXJ_SMT_ANT_INPUT + } DRXJCfgSmartAntIO_t, *pDRXJCfgSmartAntIO_t; /** * /struct DRXJCfgSmartAnt_t * Set smart antenna. */ -typedef struct { - DRXJCfgSmartAntIO_t io; - u16_t ctrlData; -} DRXJCfgSmartAnt_t, *pDRXJCfgSmartAnt_t; + typedef struct { + DRXJCfgSmartAntIO_t io; + u16_t ctrlData; + } DRXJCfgSmartAnt_t, *pDRXJCfgSmartAnt_t; /** * /struct DRXJAGCSTATUS_t * AGC status information from the DRXJ-IQM-AF. */ -typedef struct { - u16_t IFAGC; - u16_t RFAGC; - u16_t DigitalAGC; -}DRXJAgcStatus_t, *pDRXJAgcStatus_t; + typedef struct { + u16_t IFAGC; + u16_t RFAGC; + u16_t DigitalAGC; + } DRXJAgcStatus_t, *pDRXJAgcStatus_t; /* DRXJ_CFG_AGC_RF, DRXJ_CFG_AGC_IF */ @@ -170,27 +173,27 @@ typedef struct { * /struct DRXJAgcCtrlMode_t * Available AGCs modes in the DRXJ. */ -typedef enum { - DRX_AGC_CTRL_AUTO = 0, - DRX_AGC_CTRL_USER, - DRX_AGC_CTRL_OFF -} DRXJAgcCtrlMode_t, *pDRXJAgcCtrlMode_t; + typedef enum { + DRX_AGC_CTRL_AUTO = 0, + DRX_AGC_CTRL_USER, + DRX_AGC_CTRL_OFF + } DRXJAgcCtrlMode_t, *pDRXJAgcCtrlMode_t; /** * /struct DRXJCfgAgc_t * Generic interface for all AGCs present on the DRXJ. */ -typedef struct { - DRXStandard_t standard; /* standard for which these settings apply */ - DRXJAgcCtrlMode_t ctrlMode; /* off, user, auto */ - u16_t outputLevel; /* range dependent on AGC */ - u16_t minOutputLevel; /* range dependent on AGC */ - u16_t maxOutputLevel; /* range dependent on AGC */ - u16_t speed; /* range dependent on AGC */ - u16_t top; /* rf-agc take over point */ - u16_t cutOffCurrent; /* rf-agc is accelerated if output current - is below cut-off current */ -}DRXJCfgAgc_t, *pDRXJCfgAgc_t; + typedef struct { + DRXStandard_t standard; /* standard for which these settings apply */ + DRXJAgcCtrlMode_t ctrlMode; /* off, user, auto */ + u16_t outputLevel; /* range dependent on AGC */ + u16_t minOutputLevel; /* range dependent on AGC */ + u16_t maxOutputLevel; /* range dependent on AGC */ + u16_t speed; /* range dependent on AGC */ + u16_t top; /* rf-agc take over point */ + u16_t cutOffCurrent; /* rf-agc is accelerated if output current + is below cut-off current */ + } DRXJCfgAgc_t, *pDRXJCfgAgc_t; /* DRXJ_CFG_PRE_SAW */ @@ -198,11 +201,11 @@ typedef struct { * /struct DRXJCfgPreSaw_t * Interface to configure pre SAW sense. */ -typedef struct { - DRXStandard_t standard; /* standard to which these settings apply */ - u16_t reference; /* pre SAW reference value, range 0 .. 31 */ - Bool_t usePreSaw; /* TRUE algorithms must use pre SAW sense */ -} DRXJCfgPreSaw_t, *pDRXJCfgPreSaw_t; + typedef struct { + DRXStandard_t standard; /* standard to which these settings apply */ + u16_t reference; /* pre SAW reference value, range 0 .. 31 */ + Bool_t usePreSaw; /* TRUE algorithms must use pre SAW sense */ + } DRXJCfgPreSaw_t, *pDRXJCfgPreSaw_t; /* DRXJ_CFG_AFE_GAIN */ @@ -210,10 +213,10 @@ typedef struct { * /struct DRXJCfgAfeGain_t * Interface to configure gain of AFE (LNA + PGA). */ -typedef struct { - DRXStandard_t standard; /* standard to which these settings apply */ - u16_t gain; /* gain in 0.1 dB steps, DRXJ range 140 .. 335 */ -} DRXJCfgAfeGain_t, *pDRXJCfgAfeGain_t; + typedef struct { + DRXStandard_t standard; /* standard to which these settings apply */ + u16_t gain; /* gain in 0.1 dB steps, DRXJ range 140 .. 335 */ + } DRXJCfgAfeGain_t, *pDRXJCfgAfeGain_t; /** * /struct DRXJRSErrors_t @@ -222,46 +225,52 @@ typedef struct { * Container for errors that are received in the most recently finished measurment period * */ -typedef struct { - u16_t nrBitErrors; /**< no of pre RS bit errors */ - u16_t nrSymbolErrors; /**< no of pre RS symbol errors */ - u16_t nrPacketErrors; /**< no of pre RS packet errors */ - u16_t nrFailures; /**< no of post RS failures to decode */ - u16_t nrSncParFailCount; /**< no of post RS bit erros */ -} DRXJRSErrors_t, *pDRXJRSErrors_t; + typedef struct { + u16_t nrBitErrors; + /**< no of pre RS bit errors */ + u16_t nrSymbolErrors; + /**< no of pre RS symbol errors */ + u16_t nrPacketErrors; + /**< no of pre RS packet errors */ + u16_t nrFailures; + /**< no of post RS failures to decode */ + u16_t nrSncParFailCount; + /**< no of post RS bit erros */ + } DRXJRSErrors_t, *pDRXJRSErrors_t; /** * /struct DRXJCfgVSBMisc_t * symbol error rate */ -typedef struct{ - u32_t symbError; /**< symbol error rate sps */ -}DRXJCfgVSBMisc_t, *pDRXJCfgVSBMisc_t; + typedef struct { + u32_t symbError; + /**< symbol error rate sps */ + } DRXJCfgVSBMisc_t, *pDRXJCfgVSBMisc_t; /** * /enum DRXJMpegOutputClockRate_t * Mpeg output clock rate. * */ -typedef enum { - DRXJ_MPEG_START_WIDTH_1CLKCYC, - DRXJ_MPEG_START_WIDTH_8CLKCYC -} DRXJMpegStartWidth_t, *pDRXJMpegStartWidth_t; + typedef enum { + DRXJ_MPEG_START_WIDTH_1CLKCYC, + DRXJ_MPEG_START_WIDTH_8CLKCYC + } DRXJMpegStartWidth_t, *pDRXJMpegStartWidth_t; /** * /enum DRXJMpegOutputClockRate_t * Mpeg output clock rate. * */ -typedef enum { - DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO, - DRXJ_MPEGOUTPUT_CLOCK_RATE_75973K, - DRXJ_MPEGOUTPUT_CLOCK_RATE_50625K, - DRXJ_MPEGOUTPUT_CLOCK_RATE_37968K, - DRXJ_MPEGOUTPUT_CLOCK_RATE_30375K, - DRXJ_MPEGOUTPUT_CLOCK_RATE_25313K, - DRXJ_MPEGOUTPUT_CLOCK_RATE_21696K -} DRXJMpegOutputClockRate_t, *pDRXJMpegOutputClockRate_t; + typedef enum { + DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO, + DRXJ_MPEGOUTPUT_CLOCK_RATE_75973K, + DRXJ_MPEGOUTPUT_CLOCK_RATE_50625K, + DRXJ_MPEGOUTPUT_CLOCK_RATE_37968K, + DRXJ_MPEGOUTPUT_CLOCK_RATE_30375K, + DRXJ_MPEGOUTPUT_CLOCK_RATE_25313K, + DRXJ_MPEGOUTPUT_CLOCK_RATE_21696K + } DRXJMpegOutputClockRate_t, *pDRXJMpegOutputClockRate_t; /** * /struct DRXJCfgMisc_t @@ -269,49 +278,52 @@ typedef enum { * reverse MPEG output bit order * set MPEG output clock rate */ -typedef struct{ - Bool_t disableTEIHandling; /**< if TRUE pass (not change) TEI bit */ - Bool_t bitReverseMpegOutout; /**< if TRUE, parallel: msb on MD0; serial: lsb out first */ - DRXJMpegOutputClockRate_t mpegOutputClockRate; /**< set MPEG output clock rate that overwirtes the derived one from symbol rate */ - DRXJMpegStartWidth_t mpegStartWidth; /**< set MPEG output start width */ -}DRXJCfgMpegOutputMisc_t, *pDRXJCfgMpegOutputMisc_t; + typedef struct { + Bool_t disableTEIHandling; /**< if TRUE pass (not change) TEI bit */ + Bool_t bitReverseMpegOutout; /**< if TRUE, parallel: msb on MD0; serial: lsb out first */ + DRXJMpegOutputClockRate_t mpegOutputClockRate; + /**< set MPEG output clock rate that overwirtes the derived one from symbol rate */ + DRXJMpegStartWidth_t mpegStartWidth; /**< set MPEG output start width */ + } DRXJCfgMpegOutputMisc_t, *pDRXJCfgMpegOutputMisc_t; /** * /enum DRXJXtalFreq_t * Supported external crystal reference frequency. */ -typedef enum{ - DRXJ_XTAL_FREQ_RSVD, - DRXJ_XTAL_FREQ_27MHZ, - DRXJ_XTAL_FREQ_20P25MHZ, - DRXJ_XTAL_FREQ_4MHZ -}DRXJXtalFreq_t, *pDRXJXtalFreq_t; + typedef enum { + DRXJ_XTAL_FREQ_RSVD, + DRXJ_XTAL_FREQ_27MHZ, + DRXJ_XTAL_FREQ_20P25MHZ, + DRXJ_XTAL_FREQ_4MHZ + } DRXJXtalFreq_t, *pDRXJXtalFreq_t; /** * /enum DRXJXtalFreq_t * Supported external crystal reference frequency. */ -typedef enum{ - DRXJ_I2C_SPEED_400KBPS, - DRXJ_I2C_SPEED_100KBPS -}DRXJI2CSpeed_t, *pDRXJI2CSpeed_t; + typedef enum { + DRXJ_I2C_SPEED_400KBPS, + DRXJ_I2C_SPEED_100KBPS + } DRXJI2CSpeed_t, *pDRXJI2CSpeed_t; /** * /struct DRXJCfgHwCfg_t * Get hw configuration, such as crystal reference frequency, I2C speed, etc... */ -typedef struct{ - DRXJXtalFreq_t xtalFreq; /**< crystal reference frequency */ - DRXJI2CSpeed_t i2cSpeed; /**< 100 or 400 kbps */ -}DRXJCfgHwCfg_t, *pDRXJCfgHwCfg_t; + typedef struct { + DRXJXtalFreq_t xtalFreq; + /**< crystal reference frequency */ + DRXJI2CSpeed_t i2cSpeed; + /**< 100 or 400 kbps */ + } DRXJCfgHwCfg_t, *pDRXJCfgHwCfg_t; /* * DRXJ_CFG_ATV_MISC */ -typedef struct{ - s16_t peakFilter; /* -8 .. 15 */ - u16_t noiseFilter; /* 0 .. 15 */ -}DRXJCfgAtvMisc_t, *pDRXJCfgAtvMisc_t; + typedef struct { + s16_t peakFilter; /* -8 .. 15 */ + u16_t noiseFilter; /* 0 .. 15 */ + } DRXJCfgAtvMisc_t, *pDRXJCfgAtvMisc_t; /* * DRXJCfgOOBMisc_t @@ -327,51 +339,51 @@ typedef struct{ #define DRXJ_OOB_STATE_EQT_HUNT 0x30 #define DRXJ_OOB_STATE_SYNC 0x40 -typedef struct{ - DRXJAgcStatus_t agc; - Bool_t eqLock; - Bool_t symTimingLock; - Bool_t phaseLock; - Bool_t freqLock; - Bool_t digGainLock; - Bool_t anaGainLock; - u8_t state; -}DRXJCfgOOBMisc_t, *pDRXJCfgOOBMisc_t; + typedef struct { + DRXJAgcStatus_t agc; + Bool_t eqLock; + Bool_t symTimingLock; + Bool_t phaseLock; + Bool_t freqLock; + Bool_t digGainLock; + Bool_t anaGainLock; + u8_t state; + } DRXJCfgOOBMisc_t, *pDRXJCfgOOBMisc_t; /* * Index of in array of coef */ -typedef enum { - DRXJ_OOB_LO_POW_MINUS0DB = 0, - DRXJ_OOB_LO_POW_MINUS5DB, - DRXJ_OOB_LO_POW_MINUS10DB, - DRXJ_OOB_LO_POW_MINUS15DB, - DRXJ_OOB_LO_POW_MAX -} DRXJCfgOobLoPower_t, *pDRXJCfgOobLoPower_t; + typedef enum { + DRXJ_OOB_LO_POW_MINUS0DB = 0, + DRXJ_OOB_LO_POW_MINUS5DB, + DRXJ_OOB_LO_POW_MINUS10DB, + DRXJ_OOB_LO_POW_MINUS15DB, + DRXJ_OOB_LO_POW_MAX + } DRXJCfgOobLoPower_t, *pDRXJCfgOobLoPower_t; /* * DRXJ_CFG_ATV_EQU_COEF */ -typedef struct { - s16_t coef0; /* -256 .. 255 */ - s16_t coef1; /* -256 .. 255 */ - s16_t coef2; /* -256 .. 255 */ - s16_t coef3; /* -256 .. 255 */ -} DRXJCfgAtvEquCoef_t, *pDRXJCfgAtvEquCoef_t; + typedef struct { + s16_t coef0; /* -256 .. 255 */ + s16_t coef1; /* -256 .. 255 */ + s16_t coef2; /* -256 .. 255 */ + s16_t coef3; /* -256 .. 255 */ + } DRXJCfgAtvEquCoef_t, *pDRXJCfgAtvEquCoef_t; /* * Index of in array of coef */ -typedef enum { - DRXJ_COEF_IDX_MN = 0, - DRXJ_COEF_IDX_FM , - DRXJ_COEF_IDX_L , - DRXJ_COEF_IDX_LP , - DRXJ_COEF_IDX_BG , - DRXJ_COEF_IDX_DK , - DRXJ_COEF_IDX_I , - DRXJ_COEF_IDX_MAX -} DRXJCoefArrayIndex_t, *pDRXJCoefArrayIndex_t; + typedef enum { + DRXJ_COEF_IDX_MN = 0, + DRXJ_COEF_IDX_FM, + DRXJ_COEF_IDX_L, + DRXJ_COEF_IDX_LP, + DRXJ_COEF_IDX_BG, + DRXJ_COEF_IDX_DK, + DRXJ_COEF_IDX_I, + DRXJ_COEF_IDX_MAX + } DRXJCoefArrayIndex_t, *pDRXJCoefArrayIndex_t; /* * DRXJ_CFG_ATV_OUTPUT @@ -382,37 +394,37 @@ typedef enum { * Attenuation setting for SIF AGC. * */ -typedef enum { - DRXJ_SIF_ATTENUATION_0DB, - DRXJ_SIF_ATTENUATION_3DB, - DRXJ_SIF_ATTENUATION_6DB, - DRXJ_SIF_ATTENUATION_9DB -} DRXJSIFAttenuation_t, *pDRXJSIFAttenuation_t; + typedef enum { + DRXJ_SIF_ATTENUATION_0DB, + DRXJ_SIF_ATTENUATION_3DB, + DRXJ_SIF_ATTENUATION_6DB, + DRXJ_SIF_ATTENUATION_9DB + } DRXJSIFAttenuation_t, *pDRXJSIFAttenuation_t; /** * /struct DRXJCfgAtvOutput_t * SIF attenuation setting. * */ -typedef struct { - Bool_t enableCVBSOutput; /* TRUE= enabled */ - Bool_t enableSIFOutput; /* TRUE= enabled */ - DRXJSIFAttenuation_t sifAttenuation; -} DRXJCfgAtvOutput_t, *pDRXJCfgAtvOutput_t; + typedef struct { + Bool_t enableCVBSOutput; /* TRUE= enabled */ + Bool_t enableSIFOutput; /* TRUE= enabled */ + DRXJSIFAttenuation_t sifAttenuation; + } DRXJCfgAtvOutput_t, *pDRXJCfgAtvOutput_t; /* DRXJ_CFG_ATV_AGC_STATUS (get only) */ /* TODO : AFE interface not yet finished, subject to change */ -typedef struct { - u16_t rfAgcGain ; /* 0 .. 877 uA */ - u16_t ifAgcGain ; /* 0 .. 877 uA */ - s16_t videoAgcGain ; /* -75 .. 1972 in 0.1 dB steps */ - s16_t audioAgcGain ; /* -4 .. 1020 in 0.1 dB steps */ - u16_t rfAgcLoopGain ; /* 0 .. 7 */ - u16_t ifAgcLoopGain ; /* 0 .. 7 */ - u16_t videoAgcLoopGain; /* 0 .. 7 */ -} DRXJCfgAtvAgcStatus_t, *pDRXJCfgAtvAgcStatus_t; + typedef struct { + u16_t rfAgcGain; /* 0 .. 877 uA */ + u16_t ifAgcGain; /* 0 .. 877 uA */ + s16_t videoAgcGain; /* -75 .. 1972 in 0.1 dB steps */ + s16_t audioAgcGain; /* -4 .. 1020 in 0.1 dB steps */ + u16_t rfAgcLoopGain; /* 0 .. 7 */ + u16_t ifAgcLoopGain; /* 0 .. 7 */ + u16_t videoAgcLoopGain; /* 0 .. 7 */ + } DRXJCfgAtvAgcStatus_t, *pDRXJCfgAtvAgcStatus_t; /*============================================================================*/ /*============================================================================*/ @@ -433,129 +445,136 @@ typedef struct { * Global data container for DRXJ specific data. * */ -typedef struct { - /* device capabilties (determined during DRX_Open()) */ - Bool_t hasLNA; /**< TRUE if LNA (aka PGA) present */ - Bool_t hasOOB; /**< TRUE if OOB supported */ - Bool_t hasNTSC; /**< TRUE if NTSC supported */ - Bool_t hasBTSC; /**< TRUE if BTSC supported */ - Bool_t hasSMATX; /**< TRUE if mat_tx is available */ - Bool_t hasSMARX; /**< TRUE if mat_rx is available */ - Bool_t hasGPIO; /**< TRUE if GPIO is available */ - Bool_t hasIRQN; /**< TRUE if IRQN is available */ - /* A1/A2/A... */ - u8_t mfx; /**< metal fix */ - - /* tuner settings */ - Bool_t mirrorFreqSpectOOB; /**< tuner inversion (TRUE = tuner mirrors the signal */ - - /* standard/channel settings */ - DRXStandard_t standard; /**< current standard information */ - DRXConstellation_t constellation; /**< current constellation */ - DRXFrequency_t frequency; /**< center signal frequency in KHz */ - DRXBandwidth_t currBandwidth; /**< current channel bandwidth */ - DRXMirror_t mirror; /**< current channel mirror */ - - /* signal quality information */ - u32_t fecBitsDesired; /**< BER accounting period */ - u16_t fecVdPlen; /**< no of trellis symbols: VD SER measurement period */ - u16_t qamVdPrescale; /**< Viterbi Measurement Prescale */ - u16_t qamVdPeriod; /**< Viterbi Measurement period */ - u16_t fecRsPlen; /**< defines RS BER measurement period */ - u16_t fecRsPrescale; /**< ReedSolomon Measurement Prescale */ - u16_t fecRsPeriod; /**< ReedSolomon Measurement period */ - Bool_t resetPktErrAcc; /**< Set a flag to reset accumulated packet error */ - u16_t pktErrAccStart; /**< Set a flag to reset accumulated packet error */ - - /* HI configuration */ - u16_t HICfgTimingDiv; /**< HI Configure() parameter 2 */ - u16_t HICfgBridgeDelay; /**< HI Configure() parameter 3 */ - u16_t HICfgWakeUpKey; /**< HI Configure() parameter 4 */ - u16_t HICfgCtrl; /**< HI Configure() parameter 5 */ - u16_t HICfgTransmit; /**< HI Configure() parameter 6 */ - - /* UIO configuartion */ - DRXUIOMode_t uioSmaRxMode; /**< current mode of SmaRx pin */ - DRXUIOMode_t uioSmaTxMode; /**< current mode of SmaTx pin */ - DRXUIOMode_t uioGPIOMode; /**< current mode of ASEL pin */ - DRXUIOMode_t uioIRQNMode; /**< current mode of IRQN pin */ - - /* IQM fs frequecy shift and inversion */ - u32_t iqmFsRateOfs; /**< frequency shifter setting after setchannel */ - Bool_t posImage; /**< Ture: positive image */ - /* IQM RC frequecy shift */ - u32_t iqmRcRateOfs; /**< frequency shifter setting after setchannel */ - - /* ATV configuartion */ - u32_t atvCfgChangedFlags; /**< flag: flags cfg changes */ - s16_t atvTopEqu0[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU0__A */ - s16_t atvTopEqu1[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU1__A */ - s16_t atvTopEqu2[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU2__A */ - s16_t atvTopEqu3[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU3__A */ - Bool_t phaseCorrectionBypass; /**< flag: TRUE=bypass */ - s16_t atvTopVidPeak; /**< shadow of ATV_TOP_VID_PEAK__A */ - u16_t atvTopNoiseTh; /**< shadow of ATV_TOP_NOISE_TH__A */ - Bool_t enableCVBSOutput; /**< flag CVBS ouput enable */ - Bool_t enableSIFOutput; /**< flag SIF ouput enable */ - DRXJSIFAttenuation_t - sifAttenuation; /**< current SIF att setting */ - /* Agc configuration for QAM and VSB */ - DRXJCfgAgc_t qamRfAgcCfg; /**< qam RF AGC config */ - DRXJCfgAgc_t qamIfAgcCfg; /**< qam IF AGC config */ - DRXJCfgAgc_t vsbRfAgcCfg; /**< vsb RF AGC config */ - DRXJCfgAgc_t vsbIfAgcCfg; /**< vsb IF AGC config */ - - /* PGA gain configuration for QAM and VSB */ - u16_t qamPgaCfg; /**< qam PGA config */ - u16_t vsbPgaCfg; /**< vsb PGA config */ - - /* Pre SAW configuration for QAM and VSB */ - DRXJCfgPreSaw_t qamPreSawCfg; /**< qam pre SAW config */ - DRXJCfgPreSaw_t vsbPreSawCfg; /**< qam pre SAW config */ - - /* Version information */ - char vText[2][12]; /**< allocated text versions */ - DRXVersion_t vVersion[2]; /**< allocated versions structs */ - DRXVersionList_t vListElements[2]; /**< allocated version list */ - - /* smart antenna configuration */ - Bool_t smartAntInverted; - - /* Tracking filter setting for OOB */ - u16_t oobTrkFilterCfg[8]; - Bool_t oobPowerOn; - - /* MPEG static bitrate setting */ - u32_t mpegTsStaticBitrate; /**< bitrate static MPEG output */ - Bool_t disableTEIhandling; /**< MPEG TS TEI handling */ - Bool_t bitReverseMpegOutout; /**< MPEG output bit order */ - DRXJMpegOutputClockRate_t - mpegOutputClockRate; /**< MPEG output clock rate */ - DRXJMpegStartWidth_t - mpegStartWidth; /**< MPEG Start width */ - - /* Pre SAW & Agc configuration for ATV */ - DRXJCfgPreSaw_t atvPreSawCfg; /**< atv pre SAW config */ - DRXJCfgAgc_t atvRfAgcCfg; /**< atv RF AGC config */ - DRXJCfgAgc_t atvIfAgcCfg; /**< atv IF AGC config */ - u16_t atvPgaCfg; /**< atv pga config */ - - u32_t currSymbolRate; - - /* pin-safe mode */ - Bool_t pdrSafeMode; /**< PDR safe mode activated */ - u16_t pdrSafeRestoreValGpio; - u16_t pdrSafeRestoreValVSync; - u16_t pdrSafeRestoreValSmaRx; - u16_t pdrSafeRestoreValSmaTx; - - /* OOB pre-saw value */ - u16_t oobPreSaw; - DRXJCfgOobLoPower_t oobLoPow; - - DRXAudData_t audData; /**< audio storage */ - -} DRXJData_t, *pDRXJData_t; + typedef struct { + /* device capabilties (determined during DRX_Open()) */ + Bool_t hasLNA; /**< TRUE if LNA (aka PGA) present */ + Bool_t hasOOB; /**< TRUE if OOB supported */ + Bool_t hasNTSC; /**< TRUE if NTSC supported */ + Bool_t hasBTSC; /**< TRUE if BTSC supported */ + Bool_t hasSMATX; /**< TRUE if mat_tx is available */ + Bool_t hasSMARX; /**< TRUE if mat_rx is available */ + Bool_t hasGPIO; /**< TRUE if GPIO is available */ + Bool_t hasIRQN; /**< TRUE if IRQN is available */ + /* A1/A2/A... */ + u8_t mfx; /**< metal fix */ + + /* tuner settings */ + Bool_t mirrorFreqSpectOOB;/**< tuner inversion (TRUE = tuner mirrors the signal */ + + /* standard/channel settings */ + DRXStandard_t standard; /**< current standard information */ + DRXConstellation_t constellation; + /**< current constellation */ + DRXFrequency_t frequency; /**< center signal frequency in KHz */ + DRXBandwidth_t currBandwidth; + /**< current channel bandwidth */ + DRXMirror_t mirror; /**< current channel mirror */ + + /* signal quality information */ + u32_t fecBitsDesired; /**< BER accounting period */ + u16_t fecVdPlen; /**< no of trellis symbols: VD SER measurement period */ + u16_t qamVdPrescale; /**< Viterbi Measurement Prescale */ + u16_t qamVdPeriod; /**< Viterbi Measurement period */ + u16_t fecRsPlen; /**< defines RS BER measurement period */ + u16_t fecRsPrescale; /**< ReedSolomon Measurement Prescale */ + u16_t fecRsPeriod; /**< ReedSolomon Measurement period */ + Bool_t resetPktErrAcc; /**< Set a flag to reset accumulated packet error */ + u16_t pktErrAccStart; /**< Set a flag to reset accumulated packet error */ + + /* HI configuration */ + u16_t HICfgTimingDiv; /**< HI Configure() parameter 2 */ + u16_t HICfgBridgeDelay; /**< HI Configure() parameter 3 */ + u16_t HICfgWakeUpKey; /**< HI Configure() parameter 4 */ + u16_t HICfgCtrl; /**< HI Configure() parameter 5 */ + u16_t HICfgTransmit; /**< HI Configure() parameter 6 */ + + /* UIO configuartion */ + DRXUIOMode_t uioSmaRxMode;/**< current mode of SmaRx pin */ + DRXUIOMode_t uioSmaTxMode;/**< current mode of SmaTx pin */ + DRXUIOMode_t uioGPIOMode; /**< current mode of ASEL pin */ + DRXUIOMode_t uioIRQNMode; /**< current mode of IRQN pin */ + + /* IQM fs frequecy shift and inversion */ + u32_t iqmFsRateOfs; /**< frequency shifter setting after setchannel */ + Bool_t posImage; /**< Ture: positive image */ + /* IQM RC frequecy shift */ + u32_t iqmRcRateOfs; /**< frequency shifter setting after setchannel */ + + /* ATV configuartion */ + u32_t atvCfgChangedFlags; /**< flag: flags cfg changes */ + s16_t atvTopEqu0[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU0__A */ + s16_t atvTopEqu1[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU1__A */ + s16_t atvTopEqu2[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU2__A */ + s16_t atvTopEqu3[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU3__A */ + Bool_t phaseCorrectionBypass;/**< flag: TRUE=bypass */ + s16_t atvTopVidPeak; /**< shadow of ATV_TOP_VID_PEAK__A */ + u16_t atvTopNoiseTh; /**< shadow of ATV_TOP_NOISE_TH__A */ + Bool_t enableCVBSOutput; /**< flag CVBS ouput enable */ + Bool_t enableSIFOutput; /**< flag SIF ouput enable */ + DRXJSIFAttenuation_t sifAttenuation; + /**< current SIF att setting */ + /* Agc configuration for QAM and VSB */ + DRXJCfgAgc_t qamRfAgcCfg; /**< qam RF AGC config */ + DRXJCfgAgc_t qamIfAgcCfg; /**< qam IF AGC config */ + DRXJCfgAgc_t vsbRfAgcCfg; /**< vsb RF AGC config */ + DRXJCfgAgc_t vsbIfAgcCfg; /**< vsb IF AGC config */ + + /* PGA gain configuration for QAM and VSB */ + u16_t qamPgaCfg; /**< qam PGA config */ + u16_t vsbPgaCfg; /**< vsb PGA config */ + + /* Pre SAW configuration for QAM and VSB */ + DRXJCfgPreSaw_t qamPreSawCfg; + /**< qam pre SAW config */ + DRXJCfgPreSaw_t vsbPreSawCfg; + /**< qam pre SAW config */ + + /* Version information */ + char vText[2][12]; /**< allocated text versions */ + DRXVersion_t vVersion[2]; /**< allocated versions structs */ + DRXVersionList_t vListElements[2]; + /**< allocated version list */ + + /* smart antenna configuration */ + Bool_t smartAntInverted; + + /* Tracking filter setting for OOB */ + u16_t oobTrkFilterCfg[8]; + Bool_t oobPowerOn; + + /* MPEG static bitrate setting */ + u32_t mpegTsStaticBitrate; /**< bitrate static MPEG output */ + Bool_t disableTEIhandling; /**< MPEG TS TEI handling */ + Bool_t bitReverseMpegOutout;/**< MPEG output bit order */ + DRXJMpegOutputClockRate_t mpegOutputClockRate; + /**< MPEG output clock rate */ + DRXJMpegStartWidth_t mpegStartWidth; + /**< MPEG Start width */ + + /* Pre SAW & Agc configuration for ATV */ + DRXJCfgPreSaw_t atvPreSawCfg; + /**< atv pre SAW config */ + DRXJCfgAgc_t atvRfAgcCfg; /**< atv RF AGC config */ + DRXJCfgAgc_t atvIfAgcCfg; /**< atv IF AGC config */ + u16_t atvPgaCfg; /**< atv pga config */ + + u32_t currSymbolRate; + + /* pin-safe mode */ + Bool_t pdrSafeMode; /**< PDR safe mode activated */ + u16_t pdrSafeRestoreValGpio; + u16_t pdrSafeRestoreValVSync; + u16_t pdrSafeRestoreValSmaRx; + u16_t pdrSafeRestoreValSmaTx; + + /* OOB pre-saw value */ + u16_t oobPreSaw; + DRXJCfgOobLoPower_t oobLoPow; + + DRXAudData_t audData; + /**< audio storage */ + + } DRXJData_t, *pDRXJData_t; /*------------------------------------------------------------------------- Access MACROS @@ -595,7 +614,6 @@ Access MACROS DRXJ_ATTR_BTSC_DETECT( d ) = (x); \ } while(0) - /*------------------------------------------------------------------------- DEFINES -------------------------------------------------------------------------*/ @@ -705,21 +723,20 @@ STRUCTS Exported FUNCTIONS -------------------------------------------------------------------------*/ -extern DRXStatus_t DRXJ_Open(pDRXDemodInstance_t demod); -extern DRXStatus_t DRXJ_Close(pDRXDemodInstance_t demod); -extern DRXStatus_t DRXJ_Ctrl(pDRXDemodInstance_t demod, - DRXCtrlIndex_t ctrl, - void *ctrlData); + extern DRXStatus_t DRXJ_Open(pDRXDemodInstance_t demod); + extern DRXStatus_t DRXJ_Close(pDRXDemodInstance_t demod); + extern DRXStatus_t DRXJ_Ctrl(pDRXDemodInstance_t demod, + DRXCtrlIndex_t ctrl, void *ctrlData); /*------------------------------------------------------------------------- Exported GLOBAL VARIABLES -------------------------------------------------------------------------*/ -extern DRXAccessFunc_t drxDapDRXJFunct_g; -extern DRXDemodFunc_t DRXJFunctions_g; -extern DRXJData_t DRXJData_g; -extern I2CDeviceAddr_t DRXJDefaultAddr_g; -extern DRXCommonAttr_t DRXJDefaultCommAttr_g; -extern DRXDemodInstance_t DRXJDefaultDemod_g; + extern DRXAccessFunc_t drxDapDRXJFunct_g; + extern DRXDemodFunc_t DRXJFunctions_g; + extern DRXJData_t DRXJData_g; + extern I2CDeviceAddr_t DRXJDefaultAddr_g; + extern DRXCommonAttr_t DRXJDefaultCommAttr_g; + extern DRXDemodInstance_t DRXJDefaultDemod_g; /*------------------------------------------------------------------------- THE END @@ -727,4 +744,4 @@ THE END #ifdef __cplusplus } #endif -#endif /* __DRXJ_H__ */ +#endif /* __DRXJ_H__ */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj_map.h b/drivers/media/dvb-frontends/drx39xyj/drxj_map.h index 35ecaae..8fad1e5 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj_map.h +++ b/drivers/media/dvb-frontends/drx39xyj/drxj_map.h @@ -53,15 +53,10 @@ extern "C" { #ifdef _REGISTERTABLE_ #include -extern RegisterTable_t drxj_map[]; -extern RegisterTableInfo_t drxj_map_info[]; + extern RegisterTable_t drxj_map[]; + extern RegisterTableInfo_t drxj_map_info[]; #endif - - - - - #define ATV_COMM_EXEC__A 0xC00000 #define ATV_COMM_EXEC__W 2 #define ATV_COMM_EXEC__M 0x3 @@ -108,8 +103,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define ATV_COMM_KEY_MIN 0x0 #define ATV_COMM_KEY_MAX 0xFFFF - - #define ATV_TOP_COMM_EXEC__A 0xC10000 #define ATV_TOP_COMM_EXEC__W 2 #define ATV_TOP_COMM_EXEC__M 0x3 @@ -168,7 +161,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define ATV_TOP_COMM_MB_MUX_OBS_SIF2025_O 0x1C0 #define ATV_TOP_COMM_MB_MUX_OBS_POST_S 0x200 - #define ATV_TOP_COMM_INT_REQ__A 0xC10003 #define ATV_TOP_COMM_INT_REQ__W 16 #define ATV_TOP_COMM_INT_REQ__M 0xFFFF @@ -246,7 +238,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define ATV_TOP_COMM_KEY_KEY_MIN 0x0 #define ATV_TOP_COMM_KEY_KEY_MAX 0xFFFF - #define ATV_TOP_CR_AMP_TH__A 0xC10010 #define ATV_TOP_CR_AMP_TH__W 8 #define ATV_TOP_CR_AMP_TH__M 0xFF @@ -279,7 +270,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define ATV_TOP_CR_CONT_CR_I_MN 0x80 #define ATV_TOP_CR_CONT_CR_I_FM 0x0 - #define ATV_TOP_CR_OVM_TH__A 0xC10012 #define ATV_TOP_CR_OVM_TH__W 8 #define ATV_TOP_CR_OVM_TH__M 0xFF @@ -287,7 +277,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define ATV_TOP_CR_OVM_TH_MN 0xA0 #define ATV_TOP_CR_OVM_TH_FM 0x0 - #define ATV_TOP_NOISE_TH__A 0xC10013 #define ATV_TOP_NOISE_TH__W 4 #define ATV_TOP_NOISE_TH__M 0xF @@ -338,7 +327,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define ATV_TOP_EQU3_EQU_C3__PRE 0x160 #define ATV_TOP_EQU3_EQU_C3_MN 0x60 - #define ATV_TOP_ROT_MODE__A 0xC10018 #define ATV_TOP_ROT_MODE__W 1 #define ATV_TOP_ROT_MODE__M 0x1 @@ -398,7 +386,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define ATV_TOP_STD_VID_POL_NEG 0x0 #define ATV_TOP_STD_VID_POL_POS 0x2 - #define ATV_TOP_VID_AMP__A 0xC1001B #define ATV_TOP_VID_AMP__W 12 #define ATV_TOP_VID_AMP__M 0xFFF @@ -406,7 +393,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define ATV_TOP_VID_AMP_MN 0x380 #define ATV_TOP_VID_AMP_FM 0x0 - #define ATV_TOP_VID_PEAK__A 0xC1001C #define ATV_TOP_VID_PEAK__W 5 #define ATV_TOP_VID_PEAK__M 0x1F @@ -418,14 +404,12 @@ extern RegisterTableInfo_t drxj_map_info[]; #define ATV_TOP_FAGC_TH__PRE 0x2B2 #define ATV_TOP_FAGC_TH_MN 0x2B2 - #define ATV_TOP_SYNC_SLICE__A 0xC1001E #define ATV_TOP_SYNC_SLICE__W 11 #define ATV_TOP_SYNC_SLICE__M 0x7FF #define ATV_TOP_SYNC_SLICE__PRE 0x243 #define ATV_TOP_SYNC_SLICE_MN 0x243 - #define ATV_TOP_SIF_GAIN__A 0xC1001F #define ATV_TOP_SIF_GAIN__W 11 #define ATV_TOP_SIF_GAIN__M 0x7FF @@ -481,7 +465,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE 0x2 #define ATV_TOP_STDBY_CVBS_STDBY_A2_STANDBY 0x0 - #define ATV_TOP_OVERRIDE_SFR__A 0xC10026 #define ATV_TOP_OVERRIDE_SFR__W 1 #define ATV_TOP_OVERRIDE_SFR__M 0x1 @@ -489,7 +472,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define ATV_TOP_OVERRIDE_SFR_ACTIVE 0x0 #define ATV_TOP_OVERRIDE_SFR_OVERRIDE 0x1 - #define ATV_TOP_SFR_VID_GAIN__A 0xC10027 #define ATV_TOP_SFR_VID_GAIN__W 16 #define ATV_TOP_SFR_VID_GAIN__M 0xFFFF @@ -544,8 +526,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define ATV_TOP_OUT_CONF_SIF_DAC_BR_NORMAL 0x0 #define ATV_TOP_OUT_CONF_SIF_DAC_BR_BITREVERSED 0x10 - - #define ATV_AFT_COMM_EXEC__A 0xFF0000 #define ATV_AFT_COMM_EXEC__W 2 #define ATV_AFT_COMM_EXEC__M 0x3 @@ -554,16 +534,11 @@ extern RegisterTableInfo_t drxj_map_info[]; #define ATV_AFT_COMM_EXEC_ACTIVE 0x1 #define ATV_AFT_COMM_EXEC_HOLD 0x2 - #define ATV_AFT_TST__A 0xFF0010 #define ATV_AFT_TST__W 4 #define ATV_AFT_TST__M 0xF #define ATV_AFT_TST__PRE 0x0 - - - - #define AUD_COMM_EXEC__A 0x1000000 #define AUD_COMM_EXEC__W 2 #define AUD_COMM_EXEC__M 0x3 @@ -576,8 +551,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define AUD_COMM_MB__M 0xFFFF #define AUD_COMM_MB__PRE 0x0 - - #define AUD_TOP_COMM_EXEC__A 0x1010000 #define AUD_TOP_COMM_EXEC__W 2 #define AUD_TOP_COMM_EXEC__M 0x3 @@ -694,14 +667,11 @@ extern RegisterTableInfo_t drxj_map_info[]; #define AUD_TOP_TR_TIMER_CYCLES__M 0xFFFF #define AUD_TOP_TR_TIMER_CYCLES__PRE 0x0 - #define AUD_TOP_DEMOD_TBO_SEL__A 0x1010014 #define AUD_TOP_DEMOD_TBO_SEL__W 5 #define AUD_TOP_DEMOD_TBO_SEL__M 0x1F #define AUD_TOP_DEMOD_TBO_SEL__PRE 0x0 - - #define AUD_DEM_WR_MODUS__A 0x1030030 #define AUD_DEM_WR_MODUS__W 16 #define AUD_DEM_WR_MODUS__M 0xFFFF @@ -803,8 +773,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define AUD_DEM_WR_STANDARD_SEL_STD_SEL_EIA_J 0x30 #define AUD_DEM_WR_STANDARD_SEL_STD_SEL_FM_RADIO 0x40 - - #define AUD_DEM_RD_STANDARD_RES__A 0x102007E #define AUD_DEM_RD_STANDARD_RES__W 16 #define AUD_DEM_RD_STANDARD_RES__M 0xFFFF @@ -902,14 +870,11 @@ extern RegisterTableInfo_t drxj_map_info[]; #define AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT__PRE 0x0 #define AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT_RDS_DATA_NOT_VALID 0xFFF - #define AUD_DEM_RD_RDS_DATA__A 0x1020210 #define AUD_DEM_RD_RDS_DATA__W 12 #define AUD_DEM_RD_RDS_DATA__M 0xFFF #define AUD_DEM_RD_RDS_DATA__PRE 0x0 - - #define AUD_DSP_WR_FM_PRESC__A 0x105000E #define AUD_DSP_WR_FM_PRESC__W 16 #define AUD_DSP_WR_FM_PRESC__M 0xFFFF @@ -927,7 +892,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_180_KHZ_FM_DEVIATION 0x1300 #define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_380_KHZ_FM_DEVIATION 0x900 - #define AUD_DSP_WR_NICAM_PRESC__A 0x1050010 #define AUD_DSP_WR_NICAM_PRESC__W 16 #define AUD_DSP_WR_NICAM_PRESC__M 0xFFFF @@ -1030,9 +994,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define AUD_DSP_WR_QPEAK_MAT_QP_STEREO 0x20 #define AUD_DSP_WR_QPEAK_MAT_QP_MONO 0x30 - - - #define AUD_DSP_RD_QPEAK_L__A 0x1040019 #define AUD_DSP_RD_QPEAK_L__W 16 #define AUD_DSP_RD_QPEAK_L__M 0xFFFF @@ -1043,8 +1004,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define AUD_DSP_RD_QPEAK_R__M 0xFFFF #define AUD_DSP_RD_QPEAK_R__PRE 0x0 - - #define AUD_DSP_WR_BEEPER__A 0x1050014 #define AUD_DSP_WR_BEEPER__W 16 #define AUD_DSP_WR_BEEPER__M 0xFFFF @@ -1060,8 +1019,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__M 0x7F #define AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__PRE 0x0 - - #define AUD_DEM_WR_I2S_CONFIG2__A 0x1030050 #define AUD_DEM_WR_I2S_CONFIG2__W 16 #define AUD_DEM_WR_I2S_CONFIG2__M 0xFFFF @@ -1109,8 +1066,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_32 0x0 #define AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_16 0x1 - - #define AUD_DSP_WR_I2S_OUT_FS__A 0x105002A #define AUD_DSP_WR_I2S_OUT_FS__W 16 #define AUD_DSP_WR_I2S_OUT_FS__M 0xFFFF @@ -1149,8 +1104,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define AUD_DSP_WR_AV_SYNC_AV_STD_SEL_NTSC 0x2 #define AUD_DSP_WR_AV_SYNC_AV_STD_SEL_MONOCHROME 0x3 - - #define AUD_DSP_RD_STATUS2__A 0x104007B #define AUD_DSP_RD_STATUS2__W 16 #define AUD_DSP_RD_STATUS2__M 0xFFFF @@ -1183,9 +1136,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define AUD_DSP_RD_XFP_FW_FP_FW_REV__M 0xFFFF #define AUD_DSP_RD_XFP_FW_FP_FW_REV__PRE 0x42 - - - #define AUD_DEM_WR_DCO_B_HI__A 0x103009B #define AUD_DEM_WR_DCO_B_HI__W 16 #define AUD_DEM_WR_DCO_B_HI__M 0xFFFF @@ -1255,8 +1205,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define AUD_DEM_WR_CM_B_THRSHLD_CM_B_THLD__M 0xFFF #define AUD_DEM_WR_CM_B_THRSHLD_CM_B_THLD__PRE 0x2A - - #define AUD_DEM_RD_NIC_C_AD_BITS__A 0x1020023 #define AUD_DEM_RD_NIC_C_AD_BITS__W 16 #define AUD_DEM_RD_NIC_C_AD_BITS__M 0xFFFF @@ -1314,9 +1262,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define AUD_DEM_RD_NIC_ERROR_RATE_ERROR_RATE__M 0xFFF #define AUD_DEM_RD_NIC_ERROR_RATE_ERROR_RATE__PRE 0x0 - - - #define AUD_DEM_WR_FM_DEEMPH__A 0x103000F #define AUD_DEM_WR_FM_DEEMPH__W 16 #define AUD_DEM_WR_FM_DEEMPH__M 0xFFFF @@ -1325,7 +1270,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define AUD_DEM_WR_FM_DEEMPH_75US 0x1 #define AUD_DEM_WR_FM_DEEMPH_OFF 0x3F - #define AUD_DEM_WR_FM_MATRIX__A 0x103006F #define AUD_DEM_WR_FM_MATRIX__W 16 #define AUD_DEM_WR_FM_MATRIX__M 0xFFFF @@ -1336,8 +1280,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define AUD_DEM_WR_FM_MATRIX_SOUND_A 0x3 #define AUD_DEM_WR_FM_MATRIX_SOUND_B 0x4 - - #define AUD_DSP_RD_FM_IDENT_VALUE__A 0x1040018 #define AUD_DSP_RD_FM_IDENT_VALUE__W 16 #define AUD_DSP_RD_FM_IDENT_VALUE__M 0xFFFF @@ -1368,8 +1310,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define AUD_DSP_RD_FM_DC_LEVEL_B_FM_DC_LEV_B__M 0xFFFF #define AUD_DSP_RD_FM_DC_LEVEL_B_FM_DC_LEV_B__PRE 0x0 - - #define AUD_DEM_WR_FM_DC_NOTCH_SW__A 0x1030017 #define AUD_DEM_WR_FM_DC_NOTCH_SW__W 16 #define AUD_DEM_WR_FM_DC_NOTCH_SW__M 0xFFFF @@ -1382,9 +1322,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW_ON 0x0 #define AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW_OFF 0x3F - - - #define AUD_DSP_WR_SYNC_OUT__A 0x1050026 #define AUD_DSP_WR_SYNC_OUT__W 16 #define AUD_DSP_WR_SYNC_OUT__M 0xFFFF @@ -1392,8 +1329,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define AUD_DSP_WR_SYNC_OUT_OFF 0x0 #define AUD_DSP_WR_SYNC_OUT_SYNCHRONOUS 0x1 - - #define AUD_XFP_DRAM_1K__A 0x1060000 #define AUD_XFP_DRAM_1K__W 16 #define AUD_XFP_DRAM_1K__M 0xFFFF @@ -1403,8 +1338,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define AUD_XFP_DRAM_1K_D__M 0xFFFF #define AUD_XFP_DRAM_1K_D__PRE 0x0 - - #define AUD_XFP_PRAM_4K__A 0x1070000 #define AUD_XFP_PRAM_4K__W 16 #define AUD_XFP_PRAM_4K__M 0xFFFF @@ -1414,8 +1347,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define AUD_XFP_PRAM_4K_D__M 0xFFFF #define AUD_XFP_PRAM_4K_D__PRE 0x0 - - #define AUD_XDFP_DRAM_1K__A 0x1080000 #define AUD_XDFP_DRAM_1K__W 16 #define AUD_XDFP_DRAM_1K__M 0xFFFF @@ -1425,8 +1356,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define AUD_XDFP_DRAM_1K_D__M 0xFFFF #define AUD_XDFP_DRAM_1K_D__PRE 0x0 - - #define AUD_XDFP_PRAM_4K__A 0x1090000 #define AUD_XDFP_PRAM_4K__W 16 #define AUD_XDFP_PRAM_4K__M 0xFFFF @@ -1436,10 +1365,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define AUD_XDFP_PRAM_4K_D__M 0xFFFF #define AUD_XDFP_PRAM_4K_D__PRE 0x0 - - - - #define FEC_COMM_EXEC__A 0x2400000 #define FEC_COMM_EXEC__W 2 #define FEC_COMM_EXEC__M 0x3 @@ -1482,8 +1407,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define FEC_COMM_INT_STM__M 0xFFFF #define FEC_COMM_INT_STM__PRE 0x0 - - #define FEC_TOP_COMM_EXEC__A 0x2410000 #define FEC_TOP_COMM_EXEC__W 2 #define FEC_TOP_COMM_EXEC__M 0x3 @@ -1492,7 +1415,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define FEC_TOP_COMM_EXEC_ACTIVE 0x1 #define FEC_TOP_COMM_EXEC_HOLD 0x2 - #define FEC_TOP_ANNEX__A 0x2410010 #define FEC_TOP_ANNEX__W 2 #define FEC_TOP_ANNEX__M 0x3 @@ -1502,8 +1424,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define FEC_TOP_ANNEX_C 0x2 #define FEC_TOP_ANNEX_D 0x3 - - #define FEC_DI_COMM_EXEC__A 0x2420000 #define FEC_DI_COMM_EXEC__W 2 #define FEC_DI_COMM_EXEC__M 0x3 @@ -1574,7 +1494,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define FEC_DI_COMM_INT_STM_TIMEOUT_INT__M 0x2 #define FEC_DI_COMM_INT_STM_TIMEOUT_INT__PRE 0x0 - #define FEC_DI_STATUS__A 0x2420010 #define FEC_DI_STATUS__W 1 #define FEC_DI_STATUS__M 0x1 @@ -1599,7 +1518,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define FEC_DI_MODE_IGNORE_TIMEOUT__M 0x4 #define FEC_DI_MODE_IGNORE_TIMEOUT__PRE 0x0 - #define FEC_DI_CONTROL_WORD__A 0x2420012 #define FEC_DI_CONTROL_WORD__W 4 #define FEC_DI_CONTROL_WORD__M 0xF @@ -1620,8 +1538,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define FEC_DI_TIMEOUT_HI__M 0xFF #define FEC_DI_TIMEOUT_HI__PRE 0xA - - #define FEC_RS_COMM_EXEC__A 0x2430000 #define FEC_RS_COMM_EXEC__W 2 #define FEC_RS_COMM_EXEC__M 0x3 @@ -1786,8 +1702,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define FEC_RS_NR_FAILURES_EXP__M 0xF000 #define FEC_RS_NR_FAILURES_EXP__PRE 0x0 - - #define FEC_OC_COMM_EXEC__A 0x2440000 #define FEC_OC_COMM_EXEC__W 2 #define FEC_OC_COMM_EXEC__M 0x3 @@ -2001,7 +1915,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define FEC_OC_DPR_MODE_NOSYNC_ENABLE__M 0x2 #define FEC_OC_DPR_MODE_NOSYNC_ENABLE__PRE 0x0 - #define FEC_OC_DPR_UNLOCK__A 0x2440013 #define FEC_OC_DPR_UNLOCK__W 1 #define FEC_OC_DPR_UNLOCK__M 0x1 @@ -2026,7 +1939,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define FEC_OC_DTO_MODE_OFFSET_ENABLE__M 0x4 #define FEC_OC_DTO_MODE_OFFSET_ENABLE__PRE 0x0 - #define FEC_OC_DTO_PERIOD__A 0x2440015 #define FEC_OC_DTO_PERIOD__W 8 #define FEC_OC_DTO_PERIOD__M 0xFF @@ -2701,22 +2613,12 @@ extern RegisterTableInfo_t drxj_map_info[]; #define FEC_OC_OCR_GRAB_RD5_DATA__M 0x3FF #define FEC_OC_OCR_GRAB_RD5_DATA__PRE 0x0 - - #define FEC_DI_RAM__A 0x2450000 - - #define FEC_RS_RAM__A 0x2460000 - - #define FEC_OC_RAM__A 0x2470000 - - - - #define IQM_COMM_EXEC__A 0x1800000 #define IQM_COMM_EXEC__W 2 #define IQM_COMM_EXEC__M 0x3 @@ -2757,8 +2659,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define IQM_COMM_INT_STM__M 0xFFFF #define IQM_COMM_INT_STM__PRE 0x0 - - #define IQM_FS_COMM_EXEC__A 0x1820000 #define IQM_FS_COMM_EXEC__W 2 #define IQM_FS_COMM_EXEC__M 0x3 @@ -2809,8 +2709,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define IQM_FS_ADJ_SEL_QAM 0x1 #define IQM_FS_ADJ_SEL_VSB 0x2 - - #define IQM_FD_COMM_EXEC__A 0x1830000 #define IQM_FD_COMM_EXEC__W 2 #define IQM_FD_COMM_EXEC__M 0x3 @@ -2836,8 +2734,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define IQM_FD_COMM_MB_OBS_OBS_OFF 0x0 #define IQM_FD_COMM_MB_OBS_OBS_ON 0x2 - - #define IQM_RC_COMM_EXEC__A 0x1840000 #define IQM_RC_COMM_EXEC__W 2 #define IQM_RC_COMM_EXEC__M 0x3 @@ -2898,7 +2794,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define IQM_RC_CROUT_ENA_ENA__M 0x1 #define IQM_RC_CROUT_ENA_ENA__PRE 0x0 - #define IQM_RC_STRETCH__A 0x1840016 #define IQM_RC_STRETCH__W 5 #define IQM_RC_STRETCH__M 0x1F @@ -2907,8 +2802,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define IQM_RC_STRETCH_QAM_B_256 0x1C #define IQM_RC_STRETCH_ATV 0xF - - #define IQM_RT_COMM_EXEC__A 0x1850000 #define IQM_RT_COMM_EXEC__W 2 #define IQM_RT_COMM_EXEC__M 0x3 @@ -2953,7 +2846,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_OFF 0x0 #define IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_ON 0x2 - #define IQM_RT_LO_INCR__A 0x1850011 #define IQM_RT_LO_INCR__W 12 #define IQM_RT_LO_INCR__M 0xFFF @@ -2978,7 +2870,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define IQM_RT_ROT_BP_ROT_BPF__M 0x2 #define IQM_RT_ROT_BP_ROT_BPF__PRE 0x0 - #define IQM_RT_LP_BP__A 0x1850013 #define IQM_RT_LP_BP__W 1 #define IQM_RT_LP_BP__M 0x1 @@ -2989,8 +2880,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define IQM_RT_DELAY__M 0x7F #define IQM_RT_DELAY__PRE 0x45 - - #define IQM_CF_COMM_EXEC__A 0x1860000 #define IQM_CF_COMM_EXEC__W 2 #define IQM_CF_COMM_EXEC__M 0x3 @@ -3097,7 +2986,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define IQM_CF_OUT_ENA_VSB__M 0x4 #define IQM_CF_OUT_ENA_VSB__PRE 0x0 - #define IQM_CF_ADJ_SEL__A 0x1860013 #define IQM_CF_ADJ_SEL__W 2 #define IQM_CF_ADJ_SEL__M 0x3 @@ -3353,8 +3241,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define IQM_CF_TAP_IM27__M 0x7FF #define IQM_CF_TAP_IM27__PRE 0x2 - - #define IQM_AF_COMM_EXEC__A 0x1870000 #define IQM_AF_COMM_EXEC__W 2 #define IQM_AF_COMM_EXEC__M 0x3 @@ -3441,7 +3327,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define IQM_AF_COMM_INT_STM_SNS_INT_STA__M 0x2 #define IQM_AF_COMM_INT_STM_SNS_INT_STA__PRE 0x0 - #define IQM_AF_FDB_SEL__A 0x1870010 #define IQM_AF_FDB_SEL__W 1 #define IQM_AF_FDB_SEL__M 0x1 @@ -3470,7 +3355,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS 0x0 #define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG 0x2 - #define IQM_AF_MON_IN_MUX__A 0x1870013 #define IQM_AF_MON_IN_MUX__W 2 #define IQM_AF_MON_IN_MUX__M 0x3 @@ -3573,7 +3457,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define IQM_AF_ADC_CONF_BITREVERSE_NSSR_RFAGC_DAC_NORMAL 0x0 #define IQM_AF_ADC_CONF_BITREVERSE_NSSR_RFAGC_DAC_BITREVERSED 0x8 - #define IQM_AF_CLP_CLIP__A 0x1870022 #define IQM_AF_CLP_CLIP__W 16 #define IQM_AF_CLP_CLIP__M 0xFFFF @@ -3587,7 +3470,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define IQM_AF_CLP_LEN_QAM_B_256 0x400 #define IQM_AF_CLP_LEN_ATV 0x0 - #define IQM_AF_CLP_TH__A 0x1870024 #define IQM_AF_CLP_TH__W 9 #define IQM_AF_CLP_TH__M 0x1FF @@ -3596,7 +3478,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define IQM_AF_CLP_TH_QAM_B_256 0x80 #define IQM_AF_CLP_TH_ATV 0x1C0 - #define IQM_AF_DCF_BYPASS__A 0x1870025 #define IQM_AF_DCF_BYPASS__W 1 #define IQM_AF_DCF_BYPASS__M 0x1 @@ -3604,7 +3485,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define IQM_AF_DCF_BYPASS_ACTIVE 0x0 #define IQM_AF_DCF_BYPASS_BYPASS 0x1 - #define IQM_AF_SNS_LEN__A 0x1870026 #define IQM_AF_SNS_LEN__W 16 #define IQM_AF_SNS_LEN__M 0xFFFF @@ -3613,7 +3493,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define IQM_AF_SNS_LEN_QAM_B_256 0x400 #define IQM_AF_SNS_LEN_ATV 0x0 - #define IQM_AF_SNS_SENSE__A 0x1870027 #define IQM_AF_SNS_SENSE__W 16 #define IQM_AF_SNS_SENSE__M 0xFFFF @@ -3699,7 +3578,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE 0x20 #define IQM_AF_STDBY_STDBY_TAGC_RF_A2_STANDBY 0x0 - #define IQM_AF_AMUX__A 0x187002D #define IQM_AF_AMUX__W 2 #define IQM_AF_AMUX__M 0x3 @@ -3710,8 +3588,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define IQM_AF_TST_AFEMAIN__M 0xFF #define IQM_AF_TST_AFEMAIN__PRE 0x0 - - #define IQM_RT_RAM__A 0x1880000 #define IQM_RT_RAM_DLY__B 0 @@ -3719,10 +3595,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define IQM_RT_RAM_DLY__M 0x1FFF #define IQM_RT_RAM_DLY__PRE 0x0 - - - - #define ORX_COMM_EXEC__A 0x2000000 #define ORX_COMM_EXEC__W 2 #define ORX_COMM_EXEC__M 0x3 @@ -3764,7 +3636,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define ORX_COMM_INT_REQ_NSU_REQ__M 0x10 #define ORX_COMM_INT_REQ_NSU_REQ__PRE 0x0 - #define ORX_COMM_INT_STA__A 0x2000005 #define ORX_COMM_INT_STA__W 16 #define ORX_COMM_INT_STA__M 0xFFFF @@ -3778,8 +3649,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define ORX_COMM_INT_STM__M 0xFFFF #define ORX_COMM_INT_STM__PRE 0x0 - - #define ORX_TOP_COMM_EXEC__A 0x2010000 #define ORX_TOP_COMM_EXEC__W 2 #define ORX_TOP_COMM_EXEC__M 0x3 @@ -3788,7 +3657,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define ORX_TOP_COMM_EXEC_ACTIVE 0x1 #define ORX_TOP_COMM_EXEC_HOLD 0x2 - #define ORX_TOP_COMM_KEY__A 0x201000F #define ORX_TOP_COMM_KEY__W 16 #define ORX_TOP_COMM_KEY__M 0xFFFF @@ -3827,8 +3695,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define ORX_TOP_AIF_CTRL_W_INV_MSB_NO_MSB_INVERSION_ADC 0x0 #define ORX_TOP_AIF_CTRL_W_INV_MSB_MSB_INVERSION_ADC 0x4 - - #define ORX_FWP_COMM_EXEC__A 0x2020000 #define ORX_FWP_COMM_EXEC__W 2 #define ORX_FWP_COMM_EXEC__M 0x3 @@ -3864,7 +3730,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define ORX_FWP_COMM_MB_OBS_MUX__M 0xE0 #define ORX_FWP_COMM_MB_OBS_MUX__PRE 0x0 - #define ORX_FWP_AAG_LEN_W__A 0x2020010 #define ORX_FWP_AAG_LEN_W__W 16 #define ORX_FWP_AAG_LEN_W__M 0xFFFF @@ -3893,7 +3758,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define ORX_FWP_PFI_A_W_RATE_1544KBPS 0xA4 #define ORX_FWP_PFI_A_W_RATE_3088KBPS 0xC0 - #define ORX_FWP_PFI_B_W__A 0x2020015 #define ORX_FWP_PFI_B_W__W 8 #define ORX_FWP_PFI_B_W__M 0xFF @@ -3902,7 +3766,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define ORX_FWP_PFI_B_W_RATE_1544KBPS 0x94 #define ORX_FWP_PFI_B_W_RATE_3088KBPS 0xB0 - #define ORX_FWP_PFI_C_W__A 0x2020016 #define ORX_FWP_PFI_C_W__W 8 #define ORX_FWP_PFI_C_W__M 0xFF @@ -3911,7 +3774,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define ORX_FWP_PFI_C_W_RATE_1544KBPS 0x64 #define ORX_FWP_PFI_C_W_RATE_3088KBPS 0x50 - #define ORX_FWP_KR1_AMP_R__A 0x2020017 #define ORX_FWP_KR1_AMP_R__W 9 #define ORX_FWP_KR1_AMP_R__M 0x1FF @@ -3936,7 +3798,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define ORX_FWP_SRC_DGN_W_EXP__M 0xF000 #define ORX_FWP_SRC_DGN_W_EXP__PRE 0x0 - #define ORX_FWP_NYQ_ADR_W__A 0x202001A #define ORX_FWP_NYQ_ADR_W__W 5 #define ORX_FWP_NYQ_ADR_W__M 0x1F @@ -3952,8 +3813,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define ORX_FWP_IQM_FRQ_W__M 0xFFFF #define ORX_FWP_IQM_FRQ_W__PRE 0x4301 - - #define ORX_EQU_COMM_EXEC__A 0x2030000 #define ORX_EQU_COMM_EXEC__W 2 #define ORX_EQU_COMM_EXEC__M 0x3 @@ -4034,7 +3893,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define ORX_EQU_COMM_INT_STM_FBF_READ__M 0x2 #define ORX_EQU_COMM_INT_STM_FBF_READ__PRE 0x0 - #define ORX_EQU_FFF_SCL_W__A 0x2030010 #define ORX_EQU_FFF_SCL_W__W 1 #define ORX_EQU_FFF_SCL_W__M 0x1 @@ -4042,7 +3900,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define ORX_EQU_FFF_SCL_W_SCALE_GAIN_1 0x0 #define ORX_EQU_FFF_SCL_W_SCALE_GAIN_2 0x1 - #define ORX_EQU_FFF_UPD_W__A 0x2030011 #define ORX_EQU_FFF_UPD_W__W 1 #define ORX_EQU_FFF_UPD_W__M 0x1 @@ -4050,7 +3907,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define ORX_EQU_FFF_UPD_W_NO_UPDATE 0x0 #define ORX_EQU_FFF_UPD_W_LMS_UPDATE 0x1 - #define ORX_EQU_FFF_STP_W__A 0x2030012 #define ORX_EQU_FFF_STP_W__W 3 #define ORX_EQU_FFF_STP_W__M 0x7 @@ -4183,7 +4039,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define ORX_EQU_MXB_SEL_W_UNDECIDED_SYMBOLS 0x0 #define ORX_EQU_MXB_SEL_W_DECIDED_SYMBOLS 0x1 - #define ORX_EQU_FBF_UPD_W__A 0x203002C #define ORX_EQU_FBF_UPD_W__W 1 #define ORX_EQU_FBF_UPD_W__M 0x1 @@ -4191,7 +4046,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define ORX_EQU_FBF_UPD_W_NO_UPDATE 0x0 #define ORX_EQU_FBF_UPD_W_LMS_UPDATE 0x1 - #define ORX_EQU_FBF_STP_W__A 0x203002D #define ORX_EQU_FBF_STP_W__W 3 #define ORX_EQU_FBF_STP_W__M 0x7 @@ -4274,7 +4128,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define ORX_EQU_ERR_SEL_W_CMA_ERROR 0x0 #define ORX_EQU_ERR_SEL_W_DDA_ERROR 0x1 - #define ORX_EQU_ERR_TIS_W__A 0x203003D #define ORX_EQU_ERR_TIS_W__W 1 #define ORX_EQU_ERR_TIS_W__M 0x1 @@ -4282,7 +4135,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define ORX_EQU_ERR_TIS_W_CMA_SIGNALS 0x0 #define ORX_EQU_ERR_TIS_W_DDA_SIGNALS 0x1 - #define ORX_EQU_ERR_EDI_R__A 0x203003E #define ORX_EQU_ERR_EDI_R__W 5 #define ORX_EQU_ERR_EDI_R__M 0x1F @@ -4318,8 +4170,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define ORX_EQU_SYN_LEN_W__M 0xFFFF #define ORX_EQU_SYN_LEN_W__PRE 0x0 - - #define ORX_DDC_COMM_EXEC__A 0x2040000 #define ORX_DDC_COMM_EXEC__W 2 #define ORX_DDC_COMM_EXEC__M 0x3 @@ -4435,8 +4285,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define ORX_DDC_OFO_SET_W_DISABLE__M 0x8000 #define ORX_DDC_OFO_SET_W_DISABLE__PRE 0x0 - - #define ORX_CON_COMM_EXEC__A 0x2050000 #define ORX_CON_COMM_EXEC__W 2 #define ORX_CON_COMM_EXEC__M 0x3 @@ -4480,7 +4328,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define ORX_CON_RST_W_KRP__M 0x8 #define ORX_CON_RST_W_KRP__PRE 0x0 - #define ORX_CON_CPH_PHI_R__A 0x2050012 #define ORX_CON_CPH_PHI_R__W 16 #define ORX_CON_CPH_PHI_R__M 0xFFFF @@ -4540,7 +4387,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define ORX_CON_CPH_WLC_W_WLIM__M 0xF0 #define ORX_CON_CPH_WLC_W_WLIM__PRE 0x80 - #define ORX_CON_CPH_DLY_W__A 0x205001A #define ORX_CON_CPH_DLY_W__W 3 #define ORX_CON_CPH_DLY_W__M 0x7 @@ -4586,8 +4432,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define ORX_CON_CTI_TAT_W__M 0xF #define ORX_CON_CTI_TAT_W__PRE 0x3 - - #define ORX_NSU_COMM_EXEC__A 0x2060000 #define ORX_NSU_COMM_EXEC__W 2 #define ORX_NSU_COMM_EXEC__M 0x3 @@ -4673,7 +4517,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_OFF 0x0 #define ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON 0x80 - #define ORX_NSU_AOX_LOFRQ_W__A 0x2060011 #define ORX_NSU_AOX_LOFRQ_W__W 16 #define ORX_NSU_AOX_LOFRQ_W__M 0xFFFF @@ -4698,7 +4541,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define ORX_NSU_AOX_LOMDE_W_PLL_DIV__M 0xC000 #define ORX_NSU_AOX_LOMDE_W_PLL_DIV__PRE 0x0 - #define ORX_NSU_AOX_LOPOW_W__A 0x2060013 #define ORX_NSU_AOX_LOPOW_W__W 2 #define ORX_NSU_AOX_LOPOW_W__M 0x3 @@ -4708,7 +4550,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define ORX_NSU_AOX_LOPOW_W_POWER_MINUS10DB 0x2 #define ORX_NSU_AOX_LOPOW_W_POWER_MINUS15DB 0x3 - #define ORX_NSU_AOX_STHR_W__A 0x2060014 #define ORX_NSU_AOX_STHR_W__W 5 #define ORX_NSU_AOX_STHR_W__M 0x1F @@ -4748,8 +4589,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS2_BP__M 0x4 #define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS2_BP__PRE 0x0 - - #define ORX_TST_COMM_EXEC__A 0x23F0000 #define ORX_TST_COMM_EXEC__W 2 #define ORX_TST_COMM_EXEC__M 0x3 @@ -4758,16 +4597,11 @@ extern RegisterTableInfo_t drxj_map_info[]; #define ORX_TST_COMM_EXEC_ACTIVE 0x1 #define ORX_TST_COMM_EXEC_HOLD 0x2 - #define ORX_TST_AOX_TST_W__A 0x23F0010 #define ORX_TST_AOX_TST_W__W 8 #define ORX_TST_AOX_TST_W__M 0xFF #define ORX_TST_AOX_TST_W__PRE 0x0 - - - - #define QAM_COMM_EXEC__A 0x1400000 #define QAM_COMM_EXEC__W 2 #define QAM_COMM_EXEC__M 0x3 @@ -4818,8 +4652,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define QAM_COMM_INT_STM__M 0xFFFF #define QAM_COMM_INT_STM__PRE 0x0 - - #define QAM_TOP_COMM_EXEC__A 0x1410000 #define QAM_TOP_COMM_EXEC__W 2 #define QAM_TOP_COMM_EXEC__M 0x3 @@ -4828,7 +4660,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define QAM_TOP_COMM_EXEC_ACTIVE 0x1 #define QAM_TOP_COMM_EXEC_HOLD 0x2 - #define QAM_TOP_ANNEX__A 0x1410010 #define QAM_TOP_ANNEX__W 2 #define QAM_TOP_ANNEX__M 0x3 @@ -4838,7 +4669,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define QAM_TOP_ANNEX_C 0x2 #define QAM_TOP_ANNEX_D 0x3 - #define QAM_TOP_CONSTELLATION__A 0x1410011 #define QAM_TOP_CONSTELLATION__W 3 #define QAM_TOP_CONSTELLATION__M 0x7 @@ -4852,8 +4682,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define QAM_TOP_CONSTELLATION_QAM128 0x6 #define QAM_TOP_CONSTELLATION_QAM256 0x7 - - #define QAM_FQ_COMM_EXEC__A 0x1420000 #define QAM_FQ_COMM_EXEC__W 2 #define QAM_FQ_COMM_EXEC__M 0x3 @@ -4885,7 +4713,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define QAM_FQ_MODE_TAPDRAIN__PRE 0x0 #define QAM_FQ_MODE_TAPDRAIN_DRAIN 0x4 - #define QAM_FQ_MU_FACTOR__A 0x1420011 #define QAM_FQ_MU_FACTOR__W 3 #define QAM_FQ_MU_FACTOR__M 0x7 @@ -5395,8 +5222,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define QAM_FQ_TAP_IM_EL23_TAP__M 0xFFF #define QAM_FQ_TAP_IM_EL23_TAP__PRE 0x2 - - #define QAM_SL_COMM_EXEC__A 0x1430000 #define QAM_SL_COMM_EXEC__W 2 #define QAM_SL_COMM_EXEC__M 0x3 @@ -5529,7 +5354,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define QAM_SL_MODE_TILT_COMP__M 0x400 #define QAM_SL_MODE_TILT_COMP__PRE 0x0 - #define QAM_SL_K_FACTOR__A 0x1430011 #define QAM_SL_K_FACTOR__W 4 #define QAM_SL_K_FACTOR__M 0xF @@ -5559,7 +5383,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define QAM_SL_MEDIAN_FAST__M 0x2000 #define QAM_SL_MEDIAN_FAST__PRE 0x0 - #define QAM_SL_ALPHA__A 0x1430013 #define QAM_SL_ALPHA__W 3 #define QAM_SL_ALPHA__M 0x7 @@ -5589,14 +5412,11 @@ extern RegisterTableInfo_t drxj_map_info[]; #define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__M 0x3FF #define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__PRE 0x0 - #define QAM_SL_ERR_POWER__A 0x1430017 #define QAM_SL_ERR_POWER__W 16 #define QAM_SL_ERR_POWER__M 0xFFFF #define QAM_SL_ERR_POWER__PRE 0x0 - - #define QAM_DQ_COMM_EXEC__A 0x1440000 #define QAM_DQ_COMM_EXEC__W 2 #define QAM_DQ_COMM_EXEC__M 0x3 @@ -5637,7 +5457,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define QAM_DQ_MODE_FB_DFB 0x10 #define QAM_DQ_MODE_FB_TRELLIS 0x18 - #define QAM_DQ_MU_FACTOR__A 0x1440011 #define QAM_DQ_MU_FACTOR__W 3 #define QAM_DQ_MU_FACTOR__M 0x7 @@ -6311,8 +6130,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define QAM_DQ_TAP_IM_EL27_TAP__M 0xFFF #define QAM_DQ_TAP_IM_EL27_TAP__PRE 0x2 - - #define QAM_LC_COMM_EXEC__A 0x1450000 #define QAM_LC_COMM_EXEC__W 2 #define QAM_LC_COMM_EXEC__M 0x3 @@ -6768,8 +6585,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define QAM_LC_PHASE_ERROR_SIZE__M 0x3FF #define QAM_LC_PHASE_ERROR_SIZE__PRE 0x0 - - #define QAM_VD_COMM_EXEC__A 0x1460000 #define QAM_VD_COMM_EXEC__W 2 #define QAM_VD_COMM_EXEC__M 0x3 @@ -6890,7 +6705,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define QAM_VD_TRACEBACK_DEPTH_LENGTH__M 0x1F #define QAM_VD_TRACEBACK_DEPTH_LENGTH__PRE 0x10 - #define QAM_VD_UNLOCK__A 0x1460015 #define QAM_VD_UNLOCK__W 1 #define QAM_VD_UNLOCK__M 0x1 @@ -6970,8 +6784,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define QAM_VD_RELOCK_COUNT_COUNT__M 0xFF #define QAM_VD_RELOCK_COUNT_COUNT__PRE 0x0 - - #define QAM_SY_COMM_EXEC__A 0x1470000 #define QAM_SY_COMM_EXEC__W 2 #define QAM_SY_COMM_EXEC__M 0x3 @@ -7078,7 +6890,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define QAM_SY_STATUS_SYNC_STATE__M 0x3 #define QAM_SY_STATUS_SYNC_STATE__PRE 0x0 - #define QAM_SY_TIMEOUT__A 0x1470011 #define QAM_SY_TIMEOUT__W 16 #define QAM_SY_TIMEOUT__M 0xFFFF @@ -7113,22 +6924,12 @@ extern RegisterTableInfo_t drxj_map_info[]; #define QAM_SY_CONTROL_WORD_CTRL_WORD__M 0xF #define QAM_SY_CONTROL_WORD_CTRL_WORD__PRE 0x0 - - #define QAM_VD_ISS_RAM__A 0x1480000 - - #define QAM_VD_QSS_RAM__A 0x1490000 - - #define QAM_VD_SYM_RAM__A 0x14A0000 - - - - #define SCU_COMM_EXEC__A 0x800000 #define SCU_COMM_EXEC__W 2 #define SCU_COMM_EXEC__M 0x3 @@ -7147,8 +6948,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define SCU_COMM_STATE_COMM_STATE__M 0xFFFF #define SCU_COMM_STATE_COMM_STATE__PRE 0x0 - - #define SCU_TOP_COMM_EXEC__A 0x810000 #define SCU_TOP_COMM_EXEC__W 2 #define SCU_TOP_COMM_EXEC__M 0x3 @@ -7157,7 +6956,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define SCU_TOP_COMM_EXEC_ACTIVE 0x1 #define SCU_TOP_COMM_EXEC_HOLD 0x2 - #define SCU_TOP_COMM_STATE__A 0x810001 #define SCU_TOP_COMM_STATE__W 16 #define SCU_TOP_COMM_STATE__M 0xFFFF @@ -7181,8 +6979,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define SCU_TOP_MWAIT_CTR_READY_DIS_NMI_ON 0x0 #define SCU_TOP_MWAIT_CTR_READY_DIS_NMI_OFF 0x2 - - #define SCU_LOW_RAM__A 0x820000 #define SCU_LOW_RAM_LOW__B 0 @@ -7190,8 +6986,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define SCU_LOW_RAM_LOW__M 0xFFFF #define SCU_LOW_RAM_LOW__PRE 0x0 - - #define SCU_HIGH_RAM__A 0x830000 #define SCU_HIGH_RAM_HIGH__B 0 @@ -7199,11 +6993,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define SCU_HIGH_RAM_HIGH__M 0xFFFF #define SCU_HIGH_RAM_HIGH__PRE 0x0 - - - - - #define SCU_RAM_AGC_RF_MAX__A 0x831E96 #define SCU_RAM_AGC_RF_MAX__W 15 #define SCU_RAM_AGC_RF_MAX__M 0x7FFF @@ -7293,7 +7082,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define SCU_RAM_AGC_KI_RED_IAGC_RED__M 0x30 #define SCU_RAM_AGC_KI_RED_IAGC_RED__PRE 0x0 - #define SCU_RAM_AGC_KI_INNERGAIN_MIN__A 0x831E9F #define SCU_RAM_AGC_KI_INNERGAIN_MIN__W 16 #define SCU_RAM_AGC_KI_INNERGAIN_MIN__M 0xFFFF @@ -7353,7 +7141,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define SCU_RAM_AGC_KI_MAX_IF__M 0xF00 #define SCU_RAM_AGC_KI_MAX_IF__PRE 0x0 - #define SCU_RAM_AGC_CLP_SUM__A 0x831EA5 #define SCU_RAM_AGC_CLP_SUM__W 16 #define SCU_RAM_AGC_CLP_SUM__M 0xFFFF @@ -7561,7 +7348,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC_DEC_DISABLE 0x0 #define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC_DEC_ENABLE 0x4 - #define SCU_RAM_AGC_KI_MIN_RFGAIN__A 0x831EC9 #define SCU_RAM_AGC_KI_MIN_RFGAIN__W 16 #define SCU_RAM_AGC_KI_MIN_RFGAIN__M 0xFFFF @@ -7918,7 +7704,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__M 0xFFF #define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__PRE 0x0 - #define SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__A 0x831F01 #define SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__W 16 #define SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__M 0xFFFF @@ -7937,7 +7722,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_REGSPEC 0xC0 #define SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_INVSPEC 0xC1 - #define SCU_RAM_ORX_SCU_STATE__A 0x831F03 #define SCU_RAM_ORX_SCU_STATE__W 8 #define SCU_RAM_ORX_SCU_STATE__M 0xFF @@ -7953,7 +7737,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define SCU_RAM_ORX_SCU_STATE_EQT_HUNT 0x30 #define SCU_RAM_ORX_SCU_STATE_SYNC 0x40 - #define SCU_RAM_ORX_SCU_LOCK__A 0x831F04 #define SCU_RAM_ORX_SCU_LOCK__W 16 #define SCU_RAM_ORX_SCU_LOCK__M 0xFFFF @@ -7968,7 +7751,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define SCU_RAM_ORX_TARGET_MODE_2048KBPS_SQRT 0x2 #define SCU_RAM_ORX_TARGET_MODE_2048KBPS_RO 0x3 - #define SCU_RAM_ORX_MER_MIN_DB__A 0x831F06 #define SCU_RAM_ORX_MER_MIN_DB__W 8 #define SCU_RAM_ORX_MER_MIN_DB__M 0xFF @@ -8117,7 +7899,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define SCU_RAM_ORX_FREQ_GAIN_CORR_2048KBPS 0x80 #define SCU_RAM_ORX_FREQ_GAIN_CORR_3088KBPS 0xC0 - #define SCU_RAM_ORX_FRQ_OFFSET__A 0x831F23 #define SCU_RAM_ORX_FRQ_OFFSET__W 16 #define SCU_RAM_ORX_FRQ_OFFSET__M 0xFFFF @@ -8432,7 +8213,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP_MWA_ENABLE 0x0 #define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP_MWA_DISABLE 0x80 - #define SCU_RAM_ATV_RSV_01__A 0x831F4E #define SCU_RAM_ATV_RSV_01__W 16 #define SCU_RAM_ATV_RSV_01__M 0xFFFF @@ -8496,7 +8276,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define SCU_RAM_ATV_ACT_AMI_ACT_AMI__M 0x7FF #define SCU_RAM_ATV_ACT_AMI_ACT_AMI__PRE 0x0 - #define SCU_RAM_ATV_RSV_05__A 0x831F56 #define SCU_RAM_ATV_RSV_05__W 16 #define SCU_RAM_ATV_RSV_05__M 0xFFFF @@ -8556,7 +8335,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__M 0xFF #define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__PRE 0x0 - #define SCU_RAM_ATV_RSV_13__A 0x831F60 #define SCU_RAM_ATV_RSV_13__W 16 #define SCU_RAM_ATV_RSV_13__M 0xFFFF @@ -8596,7 +8374,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__M 0x7FF #define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__PRE 0x0 - #define SCU_RAM_ATV_RSV_17__A 0x831F66 #define SCU_RAM_ATV_RSV_17__W 16 #define SCU_RAM_ATV_RSV_17__M 0xFFFF @@ -10086,7 +9863,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON_OFF 0x0 #define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON_ON 0x2 - #define SCU_RAM_VSB_NOTCH_THRESHOLD__A 0x831FD8 #define SCU_RAM_VSB_NOTCH_THRESHOLD__W 16 #define SCU_RAM_VSB_NOTCH_THRESHOLD__M 0xFFFF @@ -10271,7 +10047,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_LOCKED 0x8000 #define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NEVER_LOCK 0xC000 - #define SCU_RAM_PARAM_0__A 0x831FFC #define SCU_RAM_PARAM_0__W 16 #define SCU_RAM_PARAM_0__M 0xFFFF @@ -10294,7 +10069,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define SCU_RAM_PARAM_0_RESULT_INVPAR 0xFFFD #define SCU_RAM_PARAM_0_RESULT_SIZE 0xFFFC - #define SCU_RAM_COMMAND__A 0x831FFD #define SCU_RAM_COMMAND__W 16 #define SCU_RAM_COMMAND__M 0xFFFF @@ -10385,10 +10159,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define SCU_RAM_VERSION_LO_VER_PATCH_N1__M 0xF #define SCU_RAM_VERSION_LO_VER_PATCH_N1__PRE 0x0 - - - - #define SIO_COMM_EXEC__A 0x400000 #define SIO_COMM_EXEC__W 2 #define SIO_COMM_EXEC__M 0x3 @@ -10433,8 +10203,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define SIO_COMM_INT_STM__M 0xFFFF #define SIO_COMM_INT_STM__PRE 0x0 - - #define SIO_TOP_COMM_EXEC__A 0x410000 #define SIO_TOP_COMM_EXEC__W 2 #define SIO_TOP_COMM_EXEC__M 0x3 @@ -10443,14 +10211,12 @@ extern RegisterTableInfo_t drxj_map_info[]; #define SIO_TOP_COMM_EXEC_ACTIVE 0x1 #define SIO_TOP_COMM_EXEC_HOLD 0x2 - #define SIO_TOP_COMM_KEY__A 0x41000F #define SIO_TOP_COMM_KEY__W 16 #define SIO_TOP_COMM_KEY__M 0xFFFF #define SIO_TOP_COMM_KEY__PRE 0x0 #define SIO_TOP_COMM_KEY_KEY 0xFABA - #define SIO_TOP_JTAGID_LO__A 0x410012 #define SIO_TOP_JTAGID_LO__W 16 #define SIO_TOP_JTAGID_LO__M 0xFFFF @@ -10461,9 +10227,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define SIO_TOP_JTAGID_HI__M 0xFFFF #define SIO_TOP_JTAGID_HI__PRE 0x0 - - - #define SIO_HI_RA_RAM_S0_FLG_SMM__A 0x420010 #define SIO_HI_RA_RAM_S0_FLG_SMM__W 1 #define SIO_HI_RA_RAM_S0_FLG_SMM__M 0x1 @@ -10533,7 +10296,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__M 0xFFFF #define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__PRE 0x0 - #define SIO_HI_RA_RAM_S0_CRC__A 0x420017 #define SIO_HI_RA_RAM_S0_CRC__W 16 #define SIO_HI_RA_RAM_S0_CRC__M 0xFFFF @@ -10638,7 +10400,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__M 0xFFFF #define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__PRE 0x0 - #define SIO_HI_RA_RAM_S1_CRC__A 0x420027 #define SIO_HI_RA_RAM_S1_CRC__W 16 #define SIO_HI_RA_RAM_S1_CRC__M 0xFFFF @@ -10924,7 +10685,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00 #define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500 - #define SIO_HI_RA_RAM_AB_TEMP__A 0x42006E #define SIO_HI_RA_RAM_AB_TEMP__W 16 #define SIO_HI_RA_RAM_AB_TEMP__M 0xFFFF @@ -10970,7 +10730,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__M 0xFFFF #define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__PRE 0x0 - #define SIO_HI_RA_RAM_VB_ENTRY1__A 0x420072 #define SIO_HI_RA_RAM_VB_ENTRY1__W 16 #define SIO_HI_RA_RAM_VB_ENTRY1__M 0xFFFF @@ -10985,7 +10744,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__M 0xFFFF #define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__PRE 0x0 - #define SIO_HI_RA_RAM_VB_ENTRY2__A 0x420074 #define SIO_HI_RA_RAM_VB_ENTRY2__W 16 #define SIO_HI_RA_RAM_VB_ENTRY2__M 0xFFFF @@ -11000,7 +10758,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__M 0xFFFF #define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__PRE 0x0 - #define SIO_HI_RA_RAM_VB_ENTRY3__A 0x420076 #define SIO_HI_RA_RAM_VB_ENTRY3__W 16 #define SIO_HI_RA_RAM_VB_ENTRY3__M 0xFFFF @@ -11015,7 +10772,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__M 0xFFFF #define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__PRE 0x0 - #define SIO_HI_RA_RAM_VB_ENTRY4__A 0x420078 #define SIO_HI_RA_RAM_VB_ENTRY4__W 16 #define SIO_HI_RA_RAM_VB_ENTRY4__M 0xFFFF @@ -11030,7 +10786,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__M 0xFFFF #define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__PRE 0x0 - #define SIO_HI_RA_RAM_VB_ENTRY5__A 0x42007A #define SIO_HI_RA_RAM_VB_ENTRY5__W 16 #define SIO_HI_RA_RAM_VB_ENTRY5__M 0xFFFF @@ -11045,7 +10800,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__M 0xFFFF #define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__PRE 0x0 - #define SIO_HI_RA_RAM_VB_ENTRY6__A 0x42007C #define SIO_HI_RA_RAM_VB_ENTRY6__W 16 #define SIO_HI_RA_RAM_VB_ENTRY6__M 0xFFFF @@ -11060,7 +10814,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__M 0xFFFF #define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__PRE 0x0 - #define SIO_HI_RA_RAM_VB_ENTRY7__A 0x42007E #define SIO_HI_RA_RAM_VB_ENTRY7__W 16 #define SIO_HI_RA_RAM_VB_ENTRY7__M 0xFFFF @@ -11075,8 +10828,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__M 0xFFFF #define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__PRE 0x0 - - #define SIO_HI_IF_RAM_TRP_BPT_0__A 0x430000 #define SIO_HI_IF_RAM_TRP_BPT_0__W 12 #define SIO_HI_IF_RAM_TRP_BPT_0__M 0xFFF @@ -11098,8 +10849,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define SIO_HI_IF_RAM_FUN_BASE__M 0xFFF #define SIO_HI_IF_RAM_FUN_BASE__PRE 0x0 - - #define SIO_HI_IF_COMM_EXEC__A 0x440000 #define SIO_HI_IF_COMM_EXEC__W 2 #define SIO_HI_IF_COMM_EXEC__M 0x3 @@ -11109,7 +10858,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define SIO_HI_IF_COMM_EXEC_HOLD 0x2 #define SIO_HI_IF_COMM_EXEC_STEP 0x3 - #define SIO_HI_IF_COMM_STATE__A 0x440001 #define SIO_HI_IF_COMM_STATE__W 10 #define SIO_HI_IF_COMM_STATE__M 0x3FF @@ -11203,8 +10951,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define SIO_HI_IF_BPT_ADDR__M 0x3FF #define SIO_HI_IF_BPT_ADDR__PRE 0x2 - - #define SIO_CC_COMM_EXEC__A 0x450000 #define SIO_CC_COMM_EXEC__W 2 #define SIO_CC_COMM_EXEC__M 0x3 @@ -11240,7 +10986,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define SIO_CC_PLL_MODE_BYPASS_OFF 0x10 #define SIO_CC_PLL_MODE_BYPASS_ON 0x20 - #define SIO_CC_PLL_TEST__A 0x450011 #define SIO_CC_PLL_TEST__W 8 #define SIO_CC_PLL_TEST__M 0xFF @@ -11299,15 +11044,12 @@ extern RegisterTableInfo_t drxj_map_info[]; #define SIO_CC_SOFT_RST_OSC__M 0x2 #define SIO_CC_SOFT_RST_OSC__PRE 0x0 - #define SIO_CC_UPDATE__A 0x450017 #define SIO_CC_UPDATE__W 16 #define SIO_CC_UPDATE__M 0xFFFF #define SIO_CC_UPDATE__PRE 0x0 #define SIO_CC_UPDATE_KEY 0xFABA - - #define SIO_SA_COMM_EXEC__A 0x460000 #define SIO_SA_COMM_EXEC__W 2 #define SIO_SA_COMM_EXEC__M 0x3 @@ -11486,8 +11228,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define SIO_SA_RX_STATUS_BUFF_FULL__M 0x2 #define SIO_SA_RX_STATUS_BUFF_FULL__PRE 0x0 - - #define SIO_PDR_COMM_EXEC__A 0x7F0000 #define SIO_PDR_COMM_EXEC__W 2 #define SIO_PDR_COMM_EXEC__M 0x3 @@ -12308,11 +12048,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define SIO_PDR_SMA_TX_GPIO_FNC_SEL__M 0x3 #define SIO_PDR_SMA_TX_GPIO_FNC_SEL__PRE 0x0 - - - - - #define VSB_COMM_EXEC__A 0x1C00000 #define VSB_COMM_EXEC__W 2 #define VSB_COMM_EXEC__M 0x3 @@ -12321,7 +12056,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define VSB_COMM_EXEC_ACTIVE 0x1 #define VSB_COMM_EXEC_HOLD 0x2 - #define VSB_COMM_MB__A 0x1C00002 #define VSB_COMM_MB__W 16 #define VSB_COMM_MB__M 0xFFFF @@ -12336,7 +12070,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define VSB_COMM_INT_REQ_TOP_INT_REQ__M 0x1 #define VSB_COMM_INT_REQ_TOP_INT_REQ__PRE 0x0 - #define VSB_COMM_INT_STA__A 0x1C00005 #define VSB_COMM_INT_STA__W 16 #define VSB_COMM_INT_STA__M 0xFFFF @@ -12352,9 +12085,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define VSB_COMM_INT_STM__M 0xFFFF #define VSB_COMM_INT_STM__PRE 0x0 - - - #define VSB_TOP_COMM_EXEC__A 0x1C10000 #define VSB_TOP_COMM_EXEC__W 2 #define VSB_TOP_COMM_EXEC__M 0x3 @@ -12401,7 +12131,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define VSB_TOP_COMM_MB_MUX_OBS_VSB_DFE_1 0x1C0 #define VSB_TOP_COMM_MB_MUX_OBS_VSB_DFE_2 0x200 - #define VSB_TOP_COMM_INT_REQ__A 0x1C10003 #define VSB_TOP_COMM_INT_REQ__W 1 #define VSB_TOP_COMM_INT_REQ__M 0x1 @@ -12511,7 +12240,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define VSB_TOP_COMM_INT_STM_MERSER_STM__M 0x20 #define VSB_TOP_COMM_INT_STM_MERSER_STM__PRE 0x0 - #define VSB_TOP_CKGN1ACQ__A 0x1C10010 #define VSB_TOP_CKGN1ACQ__W 8 #define VSB_TOP_CKGN1ACQ__M 0xFF @@ -12591,7 +12319,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define VSB_TOP_SYNCCTRLWORD_AGCIGNOREFS__M 0x10 #define VSB_TOP_SYNCCTRLWORD_AGCIGNOREFS__PRE 0x0 - #define VSB_TOP_MAINSMUP__A 0x1C1001B #define VSB_TOP_MAINSMUP__W 8 #define VSB_TOP_MAINSMUP__M 0xFF @@ -12776,7 +12503,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define VSB_TOP_SMALL_NOTCH_CONTROL_SOFT_RESET__M 0x80 #define VSB_TOP_SMALL_NOTCH_CONTROL_SOFT_RESET__PRE 0x0 - #define VSB_TOP_TAPREADCYC__A 0x1C10025 #define VSB_TOP_TAPREADCYC__W 9 #define VSB_TOP_TAPREADCYC__M 0x1FF @@ -12826,7 +12552,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define VSB_TOP_LOCKSTATUS_DDMON__M 0x40 #define VSB_TOP_LOCKSTATUS_DDMON__PRE 0x0 - #define VSB_TOP_CTST__A 0x1C1002B #define VSB_TOP_CTST__W 4 #define VSB_TOP_CTST__M 0xF @@ -13481,7 +13206,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define VSB_TOP_PREEQAGCCTRL_PREEQAGCFRZ__M 0x10 #define VSB_TOP_PREEQAGCCTRL_PREEQAGCFRZ__PRE 0x10 - #define VSB_TOP_PREEQAGCPWRREFLVLHI__A 0x1C1003A #define VSB_TOP_PREEQAGCPWRREFLVLHI__W 8 #define VSB_TOP_PREEQAGCPWRREFLVLHI__M 0xFF @@ -13536,7 +13260,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define VSB_TOP_BEDETCTRL_BYPASS_DMP__M 0x100 #define VSB_TOP_BEDETCTRL_BYPASS_DMP__PRE 0x100 - #define VSB_TOP_LBAGCREFLVL__A 0x1C1003E #define VSB_TOP_LBAGCREFLVL__W 12 #define VSB_TOP_LBAGCREFLVL__M 0xFFF @@ -13621,7 +13344,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define VSB_TOP_AGC_TRUNCCTRL_TRUNC_EN__M 0x8 #define VSB_TOP_AGC_TRUNCCTRL_TRUNC_EN__PRE 0x8 - #define VSB_TOP_BEAGC_DEADZONEINIT__A 0x1C1004C #define VSB_TOP_BEAGC_DEADZONEINIT__W 8 #define VSB_TOP_BEAGC_DEADZONEINIT__M 0xFF @@ -13647,7 +13369,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define VSB_TOP_BEAGC_REGINIT_BEAGC_RST__M 0x4000 #define VSB_TOP_BEAGC_REGINIT_BEAGC_RST__PRE 0x0 - #define VSB_TOP_BEAGC_SCALE__A 0x1C10050 #define VSB_TOP_BEAGC_SCALE__W 14 #define VSB_TOP_BEAGC_SCALE__M 0x3FFF @@ -13678,7 +13399,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define VSB_TOP_CFAGC_REGINIT_CFAGC_RST__M 0x4000 #define VSB_TOP_CFAGC_REGINIT_CFAGC_RST__PRE 0x0 - #define VSB_TOP_CFAGC_SCALE__A 0x1C10055 #define VSB_TOP_CFAGC_SCALE__W 14 #define VSB_TOP_CFAGC_SCALE__M 0x3FFF @@ -13768,7 +13488,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define VSB_TOP_PARAOWCTRL_PARAOWEN__M 0x40 #define VSB_TOP_PARAOWCTRL_PARAOWEN__PRE 0x0 - #define VSB_TOP_CURRENTSEGLOCAT__A 0x1C10065 #define VSB_TOP_CURRENTSEGLOCAT__W 10 #define VSB_TOP_CURRENTSEGLOCAT__M 0x3FF @@ -13863,7 +13582,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define VSB_TOP_PHASELOCKCTRL_IQSWITCH__M 0x40 #define VSB_TOP_PHASELOCKCTRL_IQSWITCH__PRE 0x0 - #define VSB_TOP_DLOCKACCUM__A 0x1C10071 #define VSB_TOP_DLOCKACCUM__W 16 #define VSB_TOP_DLOCKACCUM__M 0xFFFF @@ -13889,9 +13607,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define VSB_TOP_DCRMVACUMQ__M 0x3FF #define VSB_TOP_DCRMVACUMQ__PRE 0x0 - - - #define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__A 0x1C20000 #define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__W 12 #define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__M 0xFFF @@ -14611,8 +14326,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1DATAGAIN8__M 0x7F00 #define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1DATAGAIN8__PRE 0x0 - - #define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__A 0x1C30000 #define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__W 15 #define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__M 0x7FFF @@ -15213,7 +14926,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2DATAGAIN12__M 0x7F00 #define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2DATAGAIN12__PRE 0x0 - #define VSB_SYSCTRL_RAM1_DFETRAINLKRATIO__A 0x1C30028 #define VSB_SYSCTRL_RAM1_DFETRAINLKRATIO__W 12 #define VSB_SYSCTRL_RAM1_DFETRAINLKRATIO__M 0xFFF @@ -15323,8 +15035,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2DATAGAIN__M 0x7F00 #define VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2DATAGAIN__PRE 0x0 - - #define VSB_TCMEQ_RAM__A 0x1C40000 #define VSB_TCMEQ_RAM_TCMEQ_RAM__B 0 @@ -15332,8 +15042,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define VSB_TCMEQ_RAM_TCMEQ_RAM__M 0xFFFF #define VSB_TCMEQ_RAM_TCMEQ_RAM__PRE 0x0 - - #define VSB_FCPRE_RAM__A 0x1C50000 #define VSB_FCPRE_RAM_FCPRE_RAM__B 0 @@ -15341,8 +15049,6 @@ extern RegisterTableInfo_t drxj_map_info[]; #define VSB_FCPRE_RAM_FCPRE_RAM__M 0xFFFF #define VSB_FCPRE_RAM_FCPRE_RAM__PRE 0x0 - - #define VSB_EQTAP_RAM__A 0x1C60000 #define VSB_EQTAP_RAM_EQTAP_RAM__B 0 @@ -15353,5 +15059,4 @@ extern RegisterTableInfo_t drxj_map_info[]; #ifdef __cplusplus } #endif - #endif diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj_mc.h b/drivers/media/dvb-frontends/drx39xyj/drxj_mc.h index cecc31d..52a3cc3 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj_mc.h +++ b/drivers/media/dvb-frontends/drx39xyj/drxj_mc.h @@ -44,3896 +44,7786 @@ #define DRXJ_MC_MAIN ((pu8_t) drxj_mc_main_g) const u8_t drxj_mc_main_g[] = { -0x48, 0x4c, 0x00, 0x06, 0x00, 0x00, 0xf3, 0x10, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x01, 0x07, -0x00, 0x00, 0x1f, 0xf0, 0x00, 0x01, 0xdd, 0x81, 0x00, 0x40, 0x0a, 0x00, 0xa4, 0x00, 0x00, 0x00, -0x03, 0x00, 0x2c, 0x16, 0xa4, 0x00, 0x00, 0x00, 0xfe, 0x01, 0xef, 0xff, 0xc8, 0x00, 0x00, 0x00, -0x03, 0x00, 0x0c, 0xa6, 0x27, 0x00, 0x00, 0x00, 0x51, 0x90, 0x08, 0x05, 0xff, 0x00, 0x00, 0x00, -0xa4, 0x81, 0x0c, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x9f, 0x3d, 0x0b, 0x00, 0xa4, 0x00, 0x00, 0x00, -0x9d, 0x35, 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0x00, 0xd3, 0x40, 0x3a, 0x34, 0xc8, 0x00, 0x00, 0x00, -0x55, 0x41, 0x4a, 0x11, 0xa4, 0x00, 0x00, 0x00, 0x35, 0x02, 0x0c, 0x00, 0xa4, 0x00, 0x00, 0x00, -0xa0, 0x41, 0x3a, 0x09, 0xf0, 0x00, 0x00, 0x00, 0xdb, 0x87, 0xed, 0x22, 0xd0, 0x00, 0x00, 0x00, -0x9d, 0x40, 0xca, 0x19, 0xa4, 0x00, 0x00, 0x00, 0x00, 0x40, 0x0c, 0x00, 0xf0, 0x00, 0x00, 0x00, -0x00, 0x08, 0x1a, 0x26, 0xd0, 0x00, 0x00, 0x00, 0x00, 0x40, 0x0c, 0x40, 0x11, 0x00, 0x00, 0x00, -0x00, 0x08, 0x0a, 0x40, 0x21, 0x00, 0x00, 0x00, 0x20, 0x80, 0x3c, 0x09, 0xf0, 0x00, 0x00, 0x00, -0x30, 0x81, 0x3c, 0x1b, 0xa4, 0x00, 0x00, 0x00, 0xe1, 0x68, 0x05, 0x00, 0xf0, 0x00, 0x00, 0x00, -0x00, 0x60, 0x13, 0x4d, 0xd0, 0x00, 0x00, 0x00, 0x4b, 0x02, 0x7d, 0x06, 0x81, 0x00, 0x00, 0x00, -0x20, 0x00, 0xaf, 0x24, 0xd0, 0x00, 0x00, 0x00, 0x03, 0x00, 0x9d, 0x24, 0xd0, 0x00, 0x00, 0x00, -0x25, 0x00, 0x6d, 0x05, 0xf0, 0x00, 0x00, 0x00, 0xa3, 0x00, 0x1f, 0xff, 0xd7, 0x00, 0x00, 0x00, -0x37, 0x69, 0x53, 0x08, 0xe8, 0x00, 0x00, 0x00, 0xa1, 0x41, 0x0a, 0x3a, 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+44,1396 @@ #define DRXJ_MC_VSB ((pu8_t) drxj_mc_vsb_g) const u8_t drxj_mc_vsb_g[] = { -0x48, 0x4c, 0x00, 0x03, 0x00, 0x00, 0x2b, 0x62, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x82, -0x00, 0x00, 0x15, 0x9e, 0x00, 0x01, 0x92, 0x3b, 0x2a, 0x02, 0xe4, 0xf8, 0x7f, 0x90, 0xf0, 0xf8, -0xf0, 0xa3, 0x02, 0x22, 0xa6, 0x15, 0x23, 0x7f, 0x71, 0x7e, 0x29, 0x12, 0x90, 0x61, 0x19, 0x7b, -0xf0, 0xef, 0xd0, 0xc0, 0xaf, 0xa2, 0xd1, 0x92, 0xaf, 0xc2, 0x28, 0x12, 0x90, 0xb6, 0x19, 0x7b, -0xfd, 0xe0, 0x4d, 0xef, 0x90, 0xff, 0xf6, 0x7f, 0xf0, 0xee, 0xef, 0xa3, 0xa2, 0xf0, 0x92, 0xd1, -0xd0, 0xaf, 0xe4, 0xd0, 0x7f, 0x90, 0xf0, 0xf8, 0xf0, 0xa3, 0xe4, 0x22, 0x7f, 0x90, 0xf0, 0xf8, -0xf0, 0xa3, 0x02, 0x22, 0x70, 0x09, 0x00, 0x22, 0x00, 0x00, 0x02, 0x00, 0x00, 0x28, 0x7a, 0x90, -0xe0, 0xfa, 0xa3, 0xfe, 0xff, 0xe0, 0x30, 0x7d, 0x94, 0x7c, 0x29, 0x12, 0x90, 0xa5, 0xfc, 0x7a, -0xfe, 0xe0, 0xe0, 0xa3, 0x7d, 0xff, 0x7c, 0x31, 0x12, 0x94, 0xa5, 0x29, 0x7b, 0x90, 0xe0, 0x01, -0x7e, 0xff, 0x7d, 0x00, 0x7c, 0x2e, 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__DRXJ_MC_VSB_H__ */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsbqam.h b/drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsbqam.h index 2eda7b8..480eb7e 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsbqam.h +++ b/drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsbqam.h @@ -45,1393 +45,2780 @@ #define DRXJ_MC_VSBQAM ((pu8_t) drxj_mc_vsbqam_g) const u8_t drxj_mc_vsbqam_g[] = { -0x48, 0x4c, 0x00, 0x04, 0x00, 0x00, 0x56, 0xa0, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x82, -0x00, 0x00, 0x20, 0x00, 0x00, 0x01, 0xc4, 0x4d, 0x55, 0x02, 0xe4, 0xee, 0x7f, 0x90, 0xf0, 0xf8, -0xf0, 0xa3, 0x02, 0x22, 0x4b, 0x23, 0xd0, 0xc0, 0xaf, 0xa2, 0xd1, 0x92, 0xaf, 0xc2, 0xa8, 0x53, -0x53, 0xfb, 0xef, 0xa9, 0xaa, 0x53, 0x53, 0xf7, 0xf7, 0xab, 0xd1, 0xa2, 0xaf, 0x92, 0xd0, 0xd0, -0x04, 0x7f, 0x25, 0x12, 0x12, 0x01, 0xd2, 0x55, 0x61, 0xc2, 0x13, 0xc2, 0x90, 0xe4, 0x95, 0x7f, -0x90, 0xf0, 0x8c, 0x7a, 0x90, 0xf0, 0xf8, 0x7f, 0xa3, 0xf0, 0x22, 0xf0, 0x3b, 0x12, 0xc2, 0xe0, -0x22, 0x58, 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0xf0, 0x22, 0xf0, 0x90, 0xe4, 0xf8, 0x7f, 0xa3, 0xf0, 0x22, 0xf0, + 0x90, 0xe4, 0xf8, 0x7f, + 0xa3, 0xf0, 0x22, 0xf0, 0x90, 0xe4, 0xf8, 0x7f, 0xa3, 0xf0, 0x22, 0xf0, + 0x90, 0xe4, 0xf8, 0x7f, + 0xa3, 0xf0, 0x22, 0xf0, 0x90, 0xe4, 0xf8, 0x7f, 0xa3, 0xf0, 0x22, 0xf0, + 0x90, 0xe4, 0xf8, 0x7f, + 0xa3, 0xf0, 0x22, 0xf0, 0x90, 0xe4, 0xf8, 0x7f, 0xa3, 0xf0, 0x22, 0xf0, + 0x00, 0x02, 0x02, 0x4a, + 0xef, 0x52, 0x00, 0x83, 0x1f, 0xfe, 0x00, 0x02, 0x00, 0x01, 0xe8, 0x03, + 0x10, 0x00, 0x08, 0x00, + 0x80, 0x00, 0x03, 0x94, 0x00, 0xd9, 0x00, 0x10, 0x00, 0x08, 0x00, 0x00, + 0x00, 0x00 }; #endif /* __DRXJ_MC_VSBQAM_H__ */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj_options.h b/drivers/media/dvb-frontends/drx39xyj/drxj_options.h index 64ed170..f390286 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj_options.h +++ b/drivers/media/dvb-frontends/drx39xyj/drxj_options.h @@ -62,4 +62,4 @@ THE END #ifdef __cplusplus } #endif -#endif /* __DRXJ_OPTIONS_H__ */ +#endif /* __DRXJ_OPTIONS_H__ */ -- cgit v1.1 From 3fc954a1e9e9dc5be844aa2151c407f89b7475ff Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 20 Mar 2012 00:09:53 -0300 Subject: [media] drx-j: Fix compilation and un-comment it There were some DVB internal API changes, since this driver were written. Change it to work with the new API. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/Kconfig | 1 - drivers/media/dvb-frontends/drx39xyj/Makefile | 3 +++ drivers/media/dvb-frontends/drx39xyj/drx39xxj.c | 16 ++++------------ drivers/media/usb/em28xx/Kconfig | 1 + 4 files changed, 8 insertions(+), 13 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/Kconfig b/drivers/media/dvb-frontends/drx39xyj/Kconfig index 5bcf6b4..15628eb 100644 --- a/drivers/media/dvb-frontends/drx39xyj/Kconfig +++ b/drivers/media/dvb-frontends/drx39xyj/Kconfig @@ -2,7 +2,6 @@ config DVB_DRX39XYJ tristate "Micronas DRX-J demodulator" depends on DVB_CORE && I2C default m if DVB_FE_CUSTOMISE - depends on BROKEN help An ATSC 8VSB and QAM64/256 tuner module. Say Y when you want to support this frontend. diff --git a/drivers/media/dvb-frontends/drx39xyj/Makefile b/drivers/media/dvb-frontends/drx39xyj/Makefile index b44dc37..f84c5d8 100644 --- a/drivers/media/dvb-frontends/drx39xyj/Makefile +++ b/drivers/media/dvb-frontends/drx39xyj/Makefile @@ -1,3 +1,6 @@ drx39xyj-objs := drx39xxj.o drx_driver.o drx39xxj_dummy.o drxj.o drx_dap_fasi.o obj-$(CONFIG_DVB_DRX39XYJ) += drx39xyj.o + +ccflags-y += -I$(srctree)/drivers/media/dvb-core/ +ccflags-y += -I$(srctree)/drivers/media/tuners/ diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c index 6c8c845..7f9cff1 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c @@ -175,18 +175,12 @@ static int drx39xxj_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks) return 0; } -static int drx39xxj_get_frontend(struct dvb_frontend *fe, - struct dvb_frontend_parameters *p) -{ - return 0; -} - -static int drx39xxj_set_frontend(struct dvb_frontend *fe, - struct dvb_frontend_parameters *p) +static int drx39xxj_set_frontend(struct dvb_frontend *fe) { #ifdef DJH_DEBUG int i; #endif + struct dtv_frontend_properties *p = &fe->dtv_property_cache; struct drx39xxj_state *state = fe->demodulator_priv; DRXDemodInstance_t *demod = state->demod; DRXStandard_t standard = DRX_STANDARD_8VSB; @@ -217,7 +211,7 @@ static int drx39xxj_set_frontend(struct dvb_frontend *fe, if (fe->ops.tuner_ops.set_params) { if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 1); - fe->ops.tuner_ops.set_params(fe, p); + fe->ops.tuner_ops.set_params(fe); if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0); } @@ -426,10 +420,9 @@ error: } static struct dvb_frontend_ops drx39xxj_ops = { - + .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B }, .info = { .name = "Micronas DRX39xxj family Frontend", - .type = FE_ATSC | FE_QAM, .frequency_stepsize = 62500, .frequency_min = 51000000, .frequency_max = 858000000, @@ -439,7 +432,6 @@ static struct dvb_frontend_ops drx39xxj_ops = { .i2c_gate_ctrl = drx39xxj_i2c_gate_ctrl, .sleep = drx39xxj_sleep, .set_frontend = drx39xxj_set_frontend, - .get_frontend = drx39xxj_get_frontend, .get_tune_settings = drx39xxj_get_tune_settings, .read_status = drx39xxj_read_status, .read_ber = drx39xxj_read_ber, diff --git a/drivers/media/usb/em28xx/Kconfig b/drivers/media/usb/em28xx/Kconfig index a1fccf3..7fb0287 100644 --- a/drivers/media/usb/em28xx/Kconfig +++ b/drivers/media/usb/em28xx/Kconfig @@ -55,6 +55,7 @@ config VIDEO_EM28XX_DVB select MEDIA_TUNER_TDA18271 if MEDIA_SUBDRV_AUTOSELECT select DVB_M88DS3103 if MEDIA_SUBDRV_AUTOSELECT select MEDIA_TUNER_M88TS2022 if MEDIA_SUBDRV_AUTOSELECT + select DVB_DRX39XYJ if MEDIA_SUBDRV_AUTOSELECT ---help--- This adds support for DVB cards based on the Empiatech em28xx chips. -- cgit v1.1 From c7db16ae19f004ddd052e3273f519f023358fba8 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 20 Mar 2012 00:16:54 -0300 Subject: [media] drx-j: Fix CodingStyle Make checkpatch.pl happy. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h | 36 +++------------- drivers/media/dvb-frontends/drx39xyj/drx39xxj.c | 55 +++++++++++++------------ 2 files changed, 35 insertions(+), 56 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h b/drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h index 982fc6b..d712602 100644 --- a/drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h +++ b/drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h @@ -42,6 +42,8 @@ * */ +#include + #ifndef __BSPI2C_H__ #define __BSPI2C_H__ /*------------------------------------------------------------------------------ @@ -49,29 +51,9 @@ INCLUDES ------------------------------------------------------------------------------*/ #include "bsp_types.h" -#ifdef __cplusplus -extern "C" { -#endif /*------------------------------------------------------------------------------ TYPEDEFS ------------------------------------------------------------------------------*/ -/** -* \typedef I2Caddr_t -* \brief I2C device address (7-bit or 10-bit) -*/ - typedef u16_t I2Caddr_t; - -/** -* \typedef I2CdevId_t -* \brief Device identifier. -* -* The device ID can be useful if several devices share an I2C address, -* or if multiple I2C busses are used. -* It can be used to control a "switch" selecting the correct device and/or -* I2C bus. -* -*/ - typedef u16_t I2CdevId_t; /** * \struct _I2CDeviceAddr_t @@ -81,10 +63,10 @@ TYPEDEFS * The userData pointer can be used for application specific purposes. * */ - struct _I2CDeviceAddr_t { - I2Caddr_t i2cAddr; + struct I2CDeviceAddr_t { + u16 i2cAddr; /**< The I2C address of the device. */ - I2CdevId_t i2cDevId; + u16 i2cDevId; /**< The device identifier. */ void *userData; /**< User data pointer */ @@ -97,7 +79,7 @@ TYPEDEFS * This structure contains the I2C address and the device ID. * */ - typedef struct _I2CDeviceAddr_t I2CDeviceAddr_t; + typedef struct I2CDeviceAddr_t I2CDeviceAddr_t; /** * \typedef pI2CDeviceAddr_t @@ -205,10 +187,4 @@ Exported FUNCTIONS */ extern int DRX_I2C_Error_g; -/*------------------------------------------------------------------------------ -THE END -------------------------------------------------------------------------------*/ -#ifdef __cplusplus -} -#endif #endif /* __BSPI2C_H__ */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c index 7f9cff1..95ffc98 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c @@ -46,7 +46,7 @@ static int drx39xxj_set_powerstate(struct dvb_frontend *fe, int enable) result = DRX_Ctrl(demod, DRX_CTRL_POWER_MODE, &powerMode); if (result != DRX_STS_OK) { - printk("Power state change failed\n"); + printk(KERN_ERR "Power state change failed\n"); return 0; } @@ -54,7 +54,7 @@ static int drx39xxj_set_powerstate(struct dvb_frontend *fe, int enable) return 0; } -static int drx39xxj_read_status(struct dvb_frontend *fe, fe_status_t * status) +static int drx39xxj_read_status(struct dvb_frontend *fe, fe_status_t *status) { struct drx39xxj_state *state = fe->demodulator_priv; DRXDemodInstance_t *demod = state->demod; @@ -65,14 +65,14 @@ static int drx39xxj_read_status(struct dvb_frontend *fe, fe_status_t * status) result = DRX_Ctrl(demod, DRX_CTRL_LOCK_STATUS, &lock_status); if (result != DRX_STS_OK) { - printk("drx39xxj: could not get lock status!\n"); + printk(KERN_ERR "drx39xxj: could not get lock status!\n"); *status = 0; } switch (lock_status) { case DRX_NEVER_LOCK: *status = 0; - printk("drx says NEVER_LOCK\n"); + printk(KERN_ERR "drx says NEVER_LOCK\n"); break; case DRX_NOT_LOCKED: *status = 0; @@ -95,13 +95,13 @@ static int drx39xxj_read_status(struct dvb_frontend *fe, fe_status_t * status) | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK; break; default: - printk("Lock state unknown %d\n", lock_status); + printk(KERN_ERR "Lock state unknown %d\n", lock_status); } return 0; } -static int drx39xxj_read_ber(struct dvb_frontend *fe, u32 * ber) +static int drx39xxj_read_ber(struct dvb_frontend *fe, u32 *ber) { struct drx39xxj_state *state = fe->demodulator_priv; DRXDemodInstance_t *demod = state->demod; @@ -110,7 +110,7 @@ static int drx39xxj_read_ber(struct dvb_frontend *fe, u32 * ber) result = DRX_Ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); if (result != DRX_STS_OK) { - printk("drx39xxj: could not get ber!\n"); + printk(KERN_ERR "drx39xxj: could not get ber!\n"); *ber = 0; return 0; } @@ -120,7 +120,7 @@ static int drx39xxj_read_ber(struct dvb_frontend *fe, u32 * ber) } static int drx39xxj_read_signal_strength(struct dvb_frontend *fe, - u16 * strength) + u16 *strength) { struct drx39xxj_state *state = fe->demodulator_priv; DRXDemodInstance_t *demod = state->demod; @@ -129,7 +129,7 @@ static int drx39xxj_read_signal_strength(struct dvb_frontend *fe, result = DRX_Ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); if (result != DRX_STS_OK) { - printk("drx39xxj: could not get signal strength!\n"); + printk(KERN_ERR "drx39xxj: could not get signal strength!\n"); *strength = 0; return 0; } @@ -139,7 +139,7 @@ static int drx39xxj_read_signal_strength(struct dvb_frontend *fe, return 0; } -static int drx39xxj_read_snr(struct dvb_frontend *fe, u16 * snr) +static int drx39xxj_read_snr(struct dvb_frontend *fe, u16 *snr) { struct drx39xxj_state *state = fe->demodulator_priv; DRXDemodInstance_t *demod = state->demod; @@ -148,7 +148,7 @@ static int drx39xxj_read_snr(struct dvb_frontend *fe, u16 * snr) result = DRX_Ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); if (result != DRX_STS_OK) { - printk("drx39xxj: could not read snr!\n"); + printk(KERN_ERR "drx39xxj: could not read snr!\n"); *snr = 0; return 0; } @@ -157,7 +157,7 @@ static int drx39xxj_read_snr(struct dvb_frontend *fe, u16 * snr) return 0; } -static int drx39xxj_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks) +static int drx39xxj_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) { struct drx39xxj_state *state = fe->demodulator_priv; DRXDemodInstance_t *demod = state->demod; @@ -166,7 +166,7 @@ static int drx39xxj_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks) result = DRX_Ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); if (result != DRX_STS_OK) { - printk("drx39xxj: could not get uc blocks!\n"); + printk(KERN_ERR "drx39xxj: could not get uc blocks!\n"); *ucblocks = 0; return 0; } @@ -220,7 +220,8 @@ static int drx39xxj_set_frontend(struct dvb_frontend *fe) /* Set the standard (will be powered up if necessary */ result = DRX_Ctrl(demod, DRX_CTRL_SET_STANDARD, &standard); if (result != DRX_STS_OK) { - printk("Failed to set standard! result=%02x\n", result); + printk(KERN_ERR "Failed to set standard! result=%02x\n", + result); return -EINVAL; } state->powered_up = 1; @@ -236,22 +237,22 @@ static int drx39xxj_set_frontend(struct dvb_frontend *fe) /* program channel */ result = DRX_Ctrl(demod, DRX_CTRL_SET_CHANNEL, &channel); if (result != DRX_STS_OK) { - printk("Failed to set channel!\n"); + printk(KERN_ERR "Failed to set channel!\n"); return -EINVAL; } - // Just for giggles, let's shut off the LNA again.... + /* Just for giggles, let's shut off the LNA again.... */ uioData.uio = DRX_UIO1; uioData.value = FALSE; result = DRX_Ctrl(demod, DRX_CTRL_UIO_WRITE, &uioData); if (result != DRX_STS_OK) { - printk("Failed to disable LNA!\n"); + printk(KERN_ERR "Failed to disable LNA!\n"); return 0; } #ifdef DJH_DEBUG for (i = 0; i < 2000; i++) { fe_status_t status; drx39xxj_read_status(fe, &status); - printk("i=%d status=%d\n", i, status); + printk(KERN_DBG "i=%d status=%d\n", i, status); msleep(100); i += 100; } @@ -274,7 +275,7 @@ static int drx39xxj_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) DRXStatus_t result; #ifdef DJH_DEBUG - printk("i2c gate call: enable=%d state=%d\n", enable, + printk(KERN_DBG "i2c gate call: enable=%d state=%d\n", enable, state->i2c_gate_open); #endif @@ -290,7 +291,8 @@ static int drx39xxj_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) result = DRX_Ctrl(demod, DRX_CTRL_I2C_BRIDGE, &i2c_gate_state); if (result != DRX_STS_OK) { - printk("drx39xxj: could not open i2c gate [%d]\n", result); + printk(KERN_ERR "drx39xxj: could not open i2c gate [%d]\n", + result); dump_stack(); } else { state->i2c_gate_open = enable; @@ -368,7 +370,9 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) memcpy(demod->myCommonAttr, &DRXJDefaultCommAttr_g, sizeof(DRXCommonAttr_t)); demod->myCommonAttr->microcode = DRXJ_MC_MAIN; - // demod->myCommonAttr->verifyMicrocode = FALSE; +#if 0 + demod->myCommonAttr->verifyMicrocode = FALSE; +#endif demod->myCommonAttr->verifyMicrocode = TRUE; demod->myCommonAttr->intermediateFreq = 5000; @@ -381,7 +385,7 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) result = DRX_Open(demod); if (result != DRX_STS_OK) { - printk("DRX open failed! Aborting\n"); + printk(KERN_ERR "DRX open failed! Aborting\n"); kfree(state); return NULL; } @@ -392,7 +396,7 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) /* Configure user-I/O #3: enable read/write */ result = DRX_Ctrl(demod, DRX_CTRL_UIO_CFG, &uioCfg); if (result != DRX_STS_OK) { - printk("Failed to setup LNA GPIO!\n"); + printk(KERN_ERR "Failed to setup LNA GPIO!\n"); return NULL; } @@ -400,7 +404,7 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) uioData.value = FALSE; result = DRX_Ctrl(demod, DRX_CTRL_UIO_WRITE, &uioData); if (result != DRX_STS_OK) { - printk("Failed to disable LNA!\n"); + printk(KERN_ERR "Failed to disable LNA!\n"); return NULL; } @@ -418,6 +422,7 @@ error: kfree(demod); return NULL; } +EXPORT_SYMBOL(drx39xxj_attach); static struct dvb_frontend_ops drx39xxj_ops = { .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B }, @@ -444,5 +449,3 @@ static struct dvb_frontend_ops drx39xxj_ops = { MODULE_DESCRIPTION("Micronas DRX39xxj Frontend"); MODULE_AUTHOR("Devin Heitmueller"); MODULE_LICENSE("GPL"); - -EXPORT_SYMBOL(drx39xxj_attach); -- cgit v1.1 From 5b223b390d0b6a58921ebd024f5161315ba316df Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 20 Mar 2012 00:33:46 -0300 Subject: [media] drx-j: get rid of the typedefs on bsp_i2c.h Most of the hard work here were done by this small script: for i in *; do sed s,pI2CDeviceAddr_t,"struct i2c_device_addr *",g <$i >a && mv a $i; done for i in *; do sed s,I2CDeviceAddr_t,"struct i2c_device_addr",g <$i >a && mv a $i; done Only bsp_i2c.h were added by hand. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h | 71 +---- drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h | 10 +- drivers/media/dvb-frontends/drx39xyj/drx39xxj.c | 6 +- .../media/dvb-frontends/drx39xyj/drx39xxj_dummy.c | 4 +- .../media/dvb-frontends/drx39xyj/drx_dap_fasi.c | 62 ++-- drivers/media/dvb-frontends/drx39xyj/drx_driver.c | 2 +- drivers/media/dvb-frontends/drx39xyj/drx_driver.h | 28 +- drivers/media/dvb-frontends/drx39xyj/drxj.c | 334 ++++++++++----------- drivers/media/dvb-frontends/drx39xyj/drxj.h | 2 +- 9 files changed, 238 insertions(+), 281 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h b/drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h index d712602..ec2467b 100644 --- a/drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h +++ b/drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h @@ -46,54 +46,19 @@ #ifndef __BSPI2C_H__ #define __BSPI2C_H__ -/*------------------------------------------------------------------------------ -INCLUDES -------------------------------------------------------------------------------*/ -#include "bsp_types.h" - -/*------------------------------------------------------------------------------ -TYPEDEFS -------------------------------------------------------------------------------*/ - -/** -* \struct _I2CDeviceAddr_t -* \brief I2C device parameters. -* -* This structure contains the I2C address, the device ID and a userData pointer. -* The userData pointer can be used for application specific purposes. -* -*/ - struct I2CDeviceAddr_t { - u16 i2cAddr; - /**< The I2C address of the device. */ - u16 i2cDevId; - /**< The device identifier. */ - void *userData; - /**< User data pointer */ - }; - -/** -* \typedef I2CDeviceAddr_t -* \brief I2C device parameters. -* -* This structure contains the I2C address and the device ID. -* -*/ - typedef struct I2CDeviceAddr_t I2CDeviceAddr_t; -/** -* \typedef pI2CDeviceAddr_t -* \brief Pointer to I2C device parameters. -*/ - typedef I2CDeviceAddr_t *pI2CDeviceAddr_t; +#include "bsp_types.h" -/*------------------------------------------------------------------------------ -DEFINES -------------------------------------------------------------------------------*/ +/* + * This structure contains the I2C address, the device ID and a userData pointer. + * The userData pointer can be used for application specific purposes. + */ +struct i2c_device_addr { + u16 i2cAddr; /* The I2C address of the device. */ + u16 i2cDevId; /* The device identifier. */ + void *userData; /* User data pointer */ +}; -/*------------------------------------------------------------------------------ -MACROS -------------------------------------------------------------------------------*/ /** * \def IS_I2C_10BIT( addr ) @@ -107,14 +72,6 @@ MACROS (((addr) & 0xF8) == 0xF0) /*------------------------------------------------------------------------------ -ENUM -------------------------------------------------------------------------------*/ - -/*------------------------------------------------------------------------------ -STRUCTS -------------------------------------------------------------------------------*/ - -/*------------------------------------------------------------------------------ Exported FUNCTIONS ------------------------------------------------------------------------------*/ @@ -137,10 +94,10 @@ Exported FUNCTIONS DRXStatus_t DRXBSP_I2C_Term(void); /** -* \fn DRXStatus_t DRXBSP_I2C_WriteRead( pI2CDeviceAddr_t wDevAddr, +* \fn DRXStatus_t DRXBSP_I2C_WriteRead( struct i2c_device_addr *wDevAddr, * u16_t wCount, * pu8_t wData, -* pI2CDeviceAddr_t rDevAddr, +* struct i2c_device_addr *rDevAddr, * u16_t rCount, * pu8_t rData) * \brief Read and/or write count bytes from I2C bus, store them in data[]. @@ -166,10 +123,10 @@ Exported FUNCTIONS * The device ID can be useful if several devices share an I2C address. * It can be used to control a "switch" on the I2C bus to the correct device. */ - DRXStatus_t DRXBSP_I2C_WriteRead(pI2CDeviceAddr_t wDevAddr, + DRXStatus_t DRXBSP_I2C_WriteRead(struct i2c_device_addr *wDevAddr, u16_t wCount, pu8_t wData, - pI2CDeviceAddr_t rDevAddr, + struct i2c_device_addr *rDevAddr, u16_t rCount, pu8_t rData); /** diff --git a/drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h b/drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h index 6a92a68..1491358 100644 --- a/drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h +++ b/drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h @@ -138,10 +138,10 @@ TYPEDEFS lockStat); typedef DRXStatus_t(*TUNERi2cWriteReadFunc_t) (pTUNERInstance_t tuner, - pI2CDeviceAddr_t + struct i2c_device_addr * wDevAddr, u16_t wCount, pu8_t wData, - pI2CDeviceAddr_t + struct i2c_device_addr * rDevAddr, u16_t rCount, pu8_t rData); @@ -157,7 +157,7 @@ TYPEDEFS typedef struct TUNERInstance_s { - I2CDeviceAddr_t myI2CDevAddr; + struct i2c_device_addr myI2CDevAddr; pTUNERCommonAttr_t myCommonAttr; void *myExtAttr; pTUNERFunc_t myFunct; @@ -193,10 +193,10 @@ Exported FUNCTIONS pTUNERLockStatus_t lockStat); DRXStatus_t DRXBSP_TUNER_DefaultI2CWriteRead(pTUNERInstance_t tuner, - pI2CDeviceAddr_t wDevAddr, + struct i2c_device_addr *wDevAddr, u16_t wCount, pu8_t wData, - pI2CDeviceAddr_t rDevAddr, + struct i2c_device_addr *rDevAddr, u16_t rCount, pu8_t rData); /*------------------------------------------------------------------------------ diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c index 95ffc98..1ccb992 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c @@ -327,7 +327,7 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) { struct drx39xxj_state *state = NULL; - I2CDeviceAddr_t *demodAddr = NULL; + struct i2c_device_addr *demodAddr = NULL; DRXCommonAttr_t *demodCommAttr = NULL; DRXJData_t *demodExtAttr = NULL; DRXDemodInstance_t *demod = NULL; @@ -344,7 +344,7 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) if (demod == NULL) goto error; - demodAddr = kmalloc(sizeof(I2CDeviceAddr_t), GFP_KERNEL); + demodAddr = kmalloc(sizeof(struct i2c_device_addr), GFP_KERNEL); if (demodAddr == NULL) goto error; @@ -364,7 +364,7 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) demod->myI2CDevAddr = demodAddr; memcpy(demod->myI2CDevAddr, &DRXJDefaultAddr_g, - sizeof(I2CDeviceAddr_t)); + sizeof(struct i2c_device_addr)); demod->myI2CDevAddr->userData = state; demod->myCommonAttr = demodCommAttr; memcpy(demod->myCommonAttr, &DRXJDefaultCommAttr_g, diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c b/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c index 37967b2..73fa63a 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c @@ -60,10 +60,10 @@ void *DRXBSP_HST_Memcpy(void *to, void *from, u32_t n) return (memcpy(to, from, (size_t) n)); } -DRXStatus_t DRXBSP_I2C_WriteRead(pI2CDeviceAddr_t wDevAddr, +DRXStatus_t DRXBSP_I2C_WriteRead(struct i2c_device_addr *wDevAddr, u16_t wCount, pu8_t wData, - pI2CDeviceAddr_t rDevAddr, + struct i2c_device_addr *rDevAddr, u16_t rCount, pu8_t rData) { struct drx39xxj_state *state; diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c index a4d3ed3..472581e 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c @@ -55,61 +55,61 @@ /*============================================================================*/ /* Function prototypes */ -static DRXStatus_t DRXDAP_FASI_WriteBlock(pI2CDeviceAddr_t devAddr, /* address of I2C device */ +static DRXStatus_t DRXDAP_FASI_WriteBlock(struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register/memory */ u16_t datasize, /* size of data */ pu8_t data, /* data to send */ DRXflags_t flags); /* special device flags */ -static DRXStatus_t DRXDAP_FASI_ReadBlock(pI2CDeviceAddr_t devAddr, /* address of I2C device */ +static DRXStatus_t DRXDAP_FASI_ReadBlock(struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register/memory */ u16_t datasize, /* size of data */ pu8_t data, /* data to send */ DRXflags_t flags); /* special device flags */ -static DRXStatus_t DRXDAP_FASI_WriteReg8(pI2CDeviceAddr_t devAddr, /* address of I2C device */ +static DRXStatus_t DRXDAP_FASI_WriteReg8(struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register */ u8_t data, /* data to write */ DRXflags_t flags); /* special device flags */ -static DRXStatus_t DRXDAP_FASI_ReadReg8(pI2CDeviceAddr_t devAddr, /* address of I2C device */ +static DRXStatus_t DRXDAP_FASI_ReadReg8(struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register */ pu8_t data, /* buffer to receive data */ DRXflags_t flags); /* special device flags */ -static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg8(pI2CDeviceAddr_t devAddr, /* address of I2C device */ +static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg8(struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t waddr, /* address of register */ DRXaddr_t raddr, /* address to read back from */ u8_t datain, /* data to send */ pu8_t dataout); /* data to receive back */ -static DRXStatus_t DRXDAP_FASI_WriteReg16(pI2CDeviceAddr_t devAddr, /* address of I2C device */ +static DRXStatus_t DRXDAP_FASI_WriteReg16(struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register */ u16_t data, /* data to write */ DRXflags_t flags); /* special device flags */ -static DRXStatus_t DRXDAP_FASI_ReadReg16(pI2CDeviceAddr_t devAddr, /* address of I2C device */ +static DRXStatus_t DRXDAP_FASI_ReadReg16(struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register */ pu16_t data, /* buffer to receive data */ DRXflags_t flags); /* special device flags */ -static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg16(pI2CDeviceAddr_t devAddr, /* address of I2C device */ +static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg16(struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t waddr, /* address of register */ DRXaddr_t raddr, /* address to read back from */ u16_t datain, /* data to send */ pu16_t dataout); /* data to receive back */ -static DRXStatus_t DRXDAP_FASI_WriteReg32(pI2CDeviceAddr_t devAddr, /* address of I2C device */ +static DRXStatus_t DRXDAP_FASI_WriteReg32(struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register */ u32_t data, /* data to write */ DRXflags_t flags); /* special device flags */ -static DRXStatus_t DRXDAP_FASI_ReadReg32(pI2CDeviceAddr_t devAddr, /* address of I2C device */ +static DRXStatus_t DRXDAP_FASI_ReadReg32(struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register */ pu32_t data, /* buffer to receive data */ DRXflags_t flags); /* special device flags */ -static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg32(pI2CDeviceAddr_t devAddr, /* address of I2C device */ +static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg32(struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t waddr, /* address of register */ DRXaddr_t raddr, /* address to read back from */ u32_t datain, /* data to send */ @@ -149,7 +149,7 @@ DRXAccessFunc_t drxDapFASIFunct_g = { /* Functions not supported by protocol*/ -static DRXStatus_t DRXDAP_FASI_WriteReg8(pI2CDeviceAddr_t devAddr, /* address of I2C device */ +static DRXStatus_t DRXDAP_FASI_WriteReg8(struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register */ u8_t data, /* data to write */ DRXflags_t flags) @@ -157,7 +157,7 @@ static DRXStatus_t DRXDAP_FASI_WriteReg8(pI2CDeviceAddr_t devAddr, /* address of return DRX_STS_ERROR; } -static DRXStatus_t DRXDAP_FASI_ReadReg8(pI2CDeviceAddr_t devAddr, /* address of I2C device */ +static DRXStatus_t DRXDAP_FASI_ReadReg8(struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register */ pu8_t data, /* buffer to receive data */ DRXflags_t flags) @@ -165,7 +165,7 @@ static DRXStatus_t DRXDAP_FASI_ReadReg8(pI2CDeviceAddr_t devAddr, /* address of return DRX_STS_ERROR; } -static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg8(pI2CDeviceAddr_t devAddr, /* address of I2C device */ +static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg8(struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t waddr, /* address of register */ DRXaddr_t raddr, /* address to read back from */ u8_t datain, /* data to send */ @@ -174,7 +174,7 @@ static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg8(pI2CDeviceAddr_t devAddr, /* return DRX_STS_ERROR; } -static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg32(pI2CDeviceAddr_t devAddr, /* address of I2C device */ +static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg32(struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t waddr, /* address of register */ DRXaddr_t raddr, /* address to read back from */ u32_t datain, /* data to send */ @@ -188,7 +188,7 @@ static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg32(pI2CDeviceAddr_t devAddr, /* /****************************** * * DRXStatus_t DRXDAP_FASI_ReadBlock ( -* pI2CDeviceAddr_t devAddr, -- address of I2C device +* struct i2c_device_addr *devAddr, -- address of I2C device * DRXaddr_t addr, -- address of chip register/memory * u16_t datasize, -- number of bytes to read * pu8_t data, -- data to receive @@ -210,7 +210,7 @@ static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg32(pI2CDeviceAddr_t devAddr, /* * ******************************/ -static DRXStatus_t DRXDAP_FASI_ReadBlock(pI2CDeviceAddr_t devAddr, +static DRXStatus_t DRXDAP_FASI_ReadBlock(struct i2c_device_addr *devAddr, DRXaddr_t addr, u16_t datasize, pu8_t data, DRXflags_t flags) @@ -303,7 +303,7 @@ static DRXStatus_t DRXDAP_FASI_ReadBlock(pI2CDeviceAddr_t devAddr, /****************************** * * DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg16 ( -* pI2CDeviceAddr_t devAddr, -- address of I2C device +* struct i2c_device_addr *devAddr, -- address of I2C device * DRXaddr_t waddr, -- address of chip register/memory * DRXaddr_t raddr, -- chip address to read back from * u16_t wdata, -- data to send @@ -325,7 +325,7 @@ static DRXStatus_t DRXDAP_FASI_ReadBlock(pI2CDeviceAddr_t devAddr, * ******************************/ -static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg16(pI2CDeviceAddr_t devAddr, +static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg16(struct i2c_device_addr *devAddr, DRXaddr_t waddr, DRXaddr_t raddr, u16_t wdata, pu16_t rdata) @@ -349,7 +349,7 @@ static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg16(pI2CDeviceAddr_t devAddr, /****************************** * * DRXStatus_t DRXDAP_FASI_ReadReg16 ( -* pI2CDeviceAddr_t devAddr, -- address of I2C device +* struct i2c_device_addr *devAddr, -- address of I2C device * DRXaddr_t addr, -- address of chip register/memory * pu16_t data, -- data to receive * DRXflags_t flags) -- special device flags @@ -364,7 +364,7 @@ static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg16(pI2CDeviceAddr_t devAddr, * ******************************/ -static DRXStatus_t DRXDAP_FASI_ReadReg16(pI2CDeviceAddr_t devAddr, +static DRXStatus_t DRXDAP_FASI_ReadReg16(struct i2c_device_addr *devAddr, DRXaddr_t addr, pu16_t data, DRXflags_t flags) { @@ -382,7 +382,7 @@ static DRXStatus_t DRXDAP_FASI_ReadReg16(pI2CDeviceAddr_t devAddr, /****************************** * * DRXStatus_t DRXDAP_FASI_ReadReg32 ( -* pI2CDeviceAddr_t devAddr, -- address of I2C device +* struct i2c_device_addr *devAddr, -- address of I2C device * DRXaddr_t addr, -- address of chip register/memory * pu32_t data, -- data to receive * DRXflags_t flags) -- special device flags @@ -397,7 +397,7 @@ static DRXStatus_t DRXDAP_FASI_ReadReg16(pI2CDeviceAddr_t devAddr, * ******************************/ -static DRXStatus_t DRXDAP_FASI_ReadReg32(pI2CDeviceAddr_t devAddr, +static DRXStatus_t DRXDAP_FASI_ReadReg32(struct i2c_device_addr *devAddr, DRXaddr_t addr, pu32_t data, DRXflags_t flags) { @@ -417,7 +417,7 @@ static DRXStatus_t DRXDAP_FASI_ReadReg32(pI2CDeviceAddr_t devAddr, /****************************** * * DRXStatus_t DRXDAP_FASI_WriteBlock ( -* pI2CDeviceAddr_t devAddr, -- address of I2C device +* struct i2c_device_addr *devAddr, -- address of I2C device * DRXaddr_t addr, -- address of chip register/memory * u16_t datasize, -- number of bytes to read * pu8_t data, -- data to receive @@ -436,7 +436,7 @@ static DRXStatus_t DRXDAP_FASI_ReadReg32(pI2CDeviceAddr_t devAddr, * ******************************/ -static DRXStatus_t DRXDAP_FASI_WriteBlock(pI2CDeviceAddr_t devAddr, +static DRXStatus_t DRXDAP_FASI_WriteBlock(struct i2c_device_addr *devAddr, DRXaddr_t addr, u16_t datasize, pu8_t data, DRXflags_t flags) @@ -526,7 +526,7 @@ static DRXStatus_t DRXDAP_FASI_WriteBlock(pI2CDeviceAddr_t devAddr, st = DRXBSP_I2C_WriteRead(devAddr, (u16_t) (bufx), buf, - (pI2CDeviceAddr_t) (NULL), + (struct i2c_device_addr *) (NULL), 0, (pu8_t) (NULL)); if ((st != DRX_STS_OK) && (firstErr == DRX_STS_OK)) { @@ -543,7 +543,7 @@ static DRXStatus_t DRXDAP_FASI_WriteBlock(pI2CDeviceAddr_t devAddr, st = DRXBSP_I2C_WriteRead(devAddr, (u16_t) (bufx + todo), buf, - (pI2CDeviceAddr_t) (NULL), + (struct i2c_device_addr *) (NULL), 0, (pu8_t) (NULL)); if ((st != DRX_STS_OK) && (firstErr == DRX_STS_OK)) { @@ -561,7 +561,7 @@ static DRXStatus_t DRXDAP_FASI_WriteBlock(pI2CDeviceAddr_t devAddr, /****************************** * * DRXStatus_t DRXDAP_FASI_WriteReg16 ( -* pI2CDeviceAddr_t devAddr, -- address of I2C device +* struct i2c_device_addr *devAddr, -- address of I2C device * DRXaddr_t addr, -- address of chip register/memory * u16_t data, -- data to send * DRXflags_t flags) -- special device flags @@ -575,7 +575,7 @@ static DRXStatus_t DRXDAP_FASI_WriteBlock(pI2CDeviceAddr_t devAddr, * ******************************/ -static DRXStatus_t DRXDAP_FASI_WriteReg16(pI2CDeviceAddr_t devAddr, +static DRXStatus_t DRXDAP_FASI_WriteReg16(struct i2c_device_addr *devAddr, DRXaddr_t addr, u16_t data, DRXflags_t flags) { @@ -590,7 +590,7 @@ static DRXStatus_t DRXDAP_FASI_WriteReg16(pI2CDeviceAddr_t devAddr, /****************************** * * DRXStatus_t DRXDAP_FASI_WriteReg32 ( -* pI2CDeviceAddr_t devAddr, -- address of I2C device +* struct i2c_device_addr *devAddr, -- address of I2C device * DRXaddr_t addr, -- address of chip register/memory * u32_t data, -- data to send * DRXflags_t flags) -- special device flags @@ -604,7 +604,7 @@ static DRXStatus_t DRXDAP_FASI_WriteReg16(pI2CDeviceAddr_t devAddr, * ******************************/ -static DRXStatus_t DRXDAP_FASI_WriteReg32(pI2CDeviceAddr_t devAddr, +static DRXStatus_t DRXDAP_FASI_WriteReg32(struct i2c_device_addr *devAddr, DRXaddr_t addr, u32_t data, DRXflags_t flags) { diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c index 2d27110..3a782d6 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c @@ -991,7 +991,7 @@ CtrlUCode(pDRXDemodInstance_t demod, u16_t mcNrOfBlks = 0; u16_t mcMagicWord = 0; pu8_t mcData = (pu8_t) (NULL); - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) (NULL); + struct i2c_device_addr *devAddr = (struct i2c_device_addr *) (NULL); devAddr = demod->myI2CDevAddr; diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h index 712ffd5..c88c064 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h @@ -1329,11 +1329,11 @@ STRUCTS */ typedef struct { u16_t portNr; /**< I2C port number */ - pI2CDeviceAddr_t wDevAddr; + struct i2c_device_addr *wDevAddr; /**< Write device address */ u16_t wCount; /**< Size of write data in bytes */ pu8_t wData; /**< Pointer to write data */ - pI2CDeviceAddr_t rDevAddr; + struct i2c_device_addr *rDevAddr; /**< Read device address */ u16_t rCount; /**< Size of data to read in bytes */ pu8_t rData; /**< Pointer to read buffer */ @@ -1726,71 +1726,71 @@ STRUCTS typedef u32_t DRXflags_t, *pDRXflags_t; /* Write block of data to device */ - typedef DRXStatus_t(*DRXWriteBlockFunc_t) (pI2CDeviceAddr_t devAddr, /* address of I2C device */ + typedef DRXStatus_t(*DRXWriteBlockFunc_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register/memory */ u16_t datasize, /* size of data in bytes */ pu8_t data, /* data to send */ DRXflags_t flags); /* Read block of data from device */ - typedef DRXStatus_t(*DRXReadBlockFunc_t) (pI2CDeviceAddr_t devAddr, /* address of I2C device */ + typedef DRXStatus_t(*DRXReadBlockFunc_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register/memory */ u16_t datasize, /* size of data in bytes */ pu8_t data, /* receive buffer */ DRXflags_t flags); /* Write 8-bits value to device */ - typedef DRXStatus_t(*DRXWriteReg8Func_t) (pI2CDeviceAddr_t devAddr, /* address of I2C device */ + typedef DRXStatus_t(*DRXWriteReg8Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register/memory */ u8_t data, /* data to send */ DRXflags_t flags); /* Read 8-bits value to device */ - typedef DRXStatus_t(*DRXReadReg8Func_t) (pI2CDeviceAddr_t devAddr, /* address of I2C device */ + typedef DRXStatus_t(*DRXReadReg8Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register/memory */ pu8_t data, /* receive buffer */ DRXflags_t flags); /* Read modify write 8-bits value to device */ - typedef DRXStatus_t(*DRXReadModifyWriteReg8Func_t) (pI2CDeviceAddr_t devAddr, /* address of I2C device */ + typedef DRXStatus_t(*DRXReadModifyWriteReg8Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t waddr, /* write address of register */ DRXaddr_t raddr, /* read address of register */ u8_t wdata, /* data to write */ pu8_t rdata); /* data to read */ /* Write 16-bits value to device */ - typedef DRXStatus_t(*DRXWriteReg16Func_t) (pI2CDeviceAddr_t devAddr, /* address of I2C device */ + typedef DRXStatus_t(*DRXWriteReg16Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register/memory */ u16_t data, /* data to send */ DRXflags_t flags); /* Read 16-bits value to device */ - typedef DRXStatus_t(*DRXReadReg16Func_t) (pI2CDeviceAddr_t devAddr, /* address of I2C device */ + typedef DRXStatus_t(*DRXReadReg16Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register/memory */ pu16_t data, /* receive buffer */ DRXflags_t flags); /* Read modify write 16-bits value to device */ - typedef DRXStatus_t(*DRXReadModifyWriteReg16Func_t) (pI2CDeviceAddr_t devAddr, /* address of I2C device */ + typedef DRXStatus_t(*DRXReadModifyWriteReg16Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t waddr, /* write address of register */ DRXaddr_t raddr, /* read address of register */ u16_t wdata, /* data to write */ pu16_t rdata); /* data to read */ /* Write 32-bits value to device */ - typedef DRXStatus_t(*DRXWriteReg32Func_t) (pI2CDeviceAddr_t devAddr, /* address of I2C device */ + typedef DRXStatus_t(*DRXWriteReg32Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register/memory */ u32_t data, /* data to send */ DRXflags_t flags); /* Read 32-bits value to device */ - typedef DRXStatus_t(*DRXReadReg32Func_t) (pI2CDeviceAddr_t devAddr, /* address of I2C device */ + typedef DRXStatus_t(*DRXReadReg32Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register/memory */ pu32_t data, /* receive buffer */ DRXflags_t flags); /* Read modify write 32-bits value to device */ - typedef DRXStatus_t(*DRXReadModifyWriteReg32Func_t) (pI2CDeviceAddr_t devAddr, /* address of I2C device */ + typedef DRXStatus_t(*DRXReadModifyWriteReg32Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t waddr, /* write address of register */ DRXaddr_t raddr, /* read address of register */ u32_t wdata, /* data to write */ @@ -1948,7 +1948,7 @@ STRUCTS /**< data access protocol functions */ pTUNERInstance_t myTuner; /**< tuner instance,if NULL then baseband */ - pI2CDeviceAddr_t myI2CDevAddr; + struct i2c_device_addr *myI2CDevAddr; /**< i2c address and device identifier */ pDRXCommonAttr_t myCommonAttr; /**< common DRX attributes */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index ddfde42..84f4e18 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -598,52 +598,52 @@ GLOBAL VARIABLES * DRXJ DAP structures */ -static DRXStatus_t DRXJ_DAP_ReadBlock(pI2CDeviceAddr_t devAddr, +static DRXStatus_t DRXJ_DAP_ReadBlock(struct i2c_device_addr *devAddr, DRXaddr_t addr, u16_t datasize, pu8_t data, DRXflags_t flags); -static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg8(pI2CDeviceAddr_t devAddr, +static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg8(struct i2c_device_addr *devAddr, DRXaddr_t waddr, DRXaddr_t raddr, u8_t wdata, pu8_t rdata); -static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg16(pI2CDeviceAddr_t devAddr, +static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg16(struct i2c_device_addr *devAddr, DRXaddr_t waddr, DRXaddr_t raddr, u16_t wdata, pu16_t rdata); -static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg32(pI2CDeviceAddr_t devAddr, +static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg32(struct i2c_device_addr *devAddr, DRXaddr_t waddr, DRXaddr_t raddr, u32_t wdata, pu32_t rdata); -static DRXStatus_t DRXJ_DAP_ReadReg8(pI2CDeviceAddr_t devAddr, +static DRXStatus_t DRXJ_DAP_ReadReg8(struct i2c_device_addr *devAddr, DRXaddr_t addr, pu8_t data, DRXflags_t flags); -static DRXStatus_t DRXJ_DAP_ReadReg16(pI2CDeviceAddr_t devAddr, +static DRXStatus_t DRXJ_DAP_ReadReg16(struct i2c_device_addr *devAddr, DRXaddr_t addr, pu16_t data, DRXflags_t flags); -static DRXStatus_t DRXJ_DAP_ReadReg32(pI2CDeviceAddr_t devAddr, +static DRXStatus_t DRXJ_DAP_ReadReg32(struct i2c_device_addr *devAddr, DRXaddr_t addr, pu32_t data, DRXflags_t flags); -static DRXStatus_t DRXJ_DAP_WriteBlock(pI2CDeviceAddr_t devAddr, +static DRXStatus_t DRXJ_DAP_WriteBlock(struct i2c_device_addr *devAddr, DRXaddr_t addr, u16_t datasize, pu8_t data, DRXflags_t flags); -static DRXStatus_t DRXJ_DAP_WriteReg8(pI2CDeviceAddr_t devAddr, +static DRXStatus_t DRXJ_DAP_WriteReg8(struct i2c_device_addr *devAddr, DRXaddr_t addr, u8_t data, DRXflags_t flags); -static DRXStatus_t DRXJ_DAP_WriteReg16(pI2CDeviceAddr_t devAddr, +static DRXStatus_t DRXJ_DAP_WriteReg16(struct i2c_device_addr *devAddr, DRXaddr_t addr, u16_t data, DRXflags_t flags); -static DRXStatus_t DRXJ_DAP_WriteReg32(pI2CDeviceAddr_t devAddr, +static DRXStatus_t DRXJ_DAP_WriteReg32(struct i2c_device_addr *devAddr, DRXaddr_t addr, u32_t data, DRXflags_t flags); @@ -940,7 +940,7 @@ DRXJData_t DRXJData_g = { * \var DRXJDefaultAddr_g * \brief Default I2C address and device identifier. */ -I2CDeviceAddr_t DRXJDefaultAddr_g = { +struct i2c_device_addr DRXJDefaultAddr_g = { DRXJ_DEF_I2C_ADDR, /* i2c address */ DRXJ_DEF_DEMOD_DEV_ID /* device id */ }; @@ -1146,7 +1146,7 @@ FUNCTIONS ----------------------------------------------------------------------------*/ /* Some prototypes */ static DRXStatus_t -HICommand(const pI2CDeviceAddr_t devAddr, +HICommand(const struct i2c_device_addr *devAddr, const pDRXJHiCmd_t cmd, pu16_t result); static DRXStatus_t @@ -1712,7 +1712,7 @@ Bool_t IsHandledByAudTrIf(DRXaddr_t addr) /*============================================================================*/ -static DRXStatus_t DRXJ_DAP_ReadBlock(pI2CDeviceAddr_t devAddr, +static DRXStatus_t DRXJ_DAP_ReadBlock(struct i2c_device_addr *devAddr, DRXaddr_t addr, u16_t datasize, pu8_t data, DRXflags_t flags) @@ -1723,7 +1723,7 @@ static DRXStatus_t DRXJ_DAP_ReadBlock(pI2CDeviceAddr_t devAddr, /*============================================================================*/ -static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg8(pI2CDeviceAddr_t devAddr, +static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg8(struct i2c_device_addr *devAddr, DRXaddr_t waddr, DRXaddr_t raddr, u8_t wdata, pu8_t rdata) @@ -1756,7 +1756,7 @@ static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg8(pI2CDeviceAddr_t devAddr, /* TODO correct define should be #if ( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 ) See comments DRXJ_DAP_ReadModifyWriteReg16 */ #if ( DRXDAPFASI_LONG_ADDR_ALLOWED == 0 ) -static DRXStatus_t DRXJ_DAP_RMWriteReg16Short(pI2CDeviceAddr_t devAddr, +static DRXStatus_t DRXJ_DAP_RMWriteReg16Short(struct i2c_device_addr *devAddr, DRXaddr_t waddr, DRXaddr_t raddr, u16_t wdata, pu16_t rdata) @@ -1795,7 +1795,7 @@ static DRXStatus_t DRXJ_DAP_RMWriteReg16Short(pI2CDeviceAddr_t devAddr, /*============================================================================*/ -static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg16(pI2CDeviceAddr_t devAddr, +static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg16(struct i2c_device_addr *devAddr, DRXaddr_t waddr, DRXaddr_t raddr, u16_t wdata, pu16_t rdata) @@ -1814,7 +1814,7 @@ static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg16(pI2CDeviceAddr_t devAddr, /*============================================================================*/ -static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg32(pI2CDeviceAddr_t devAddr, +static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg32(struct i2c_device_addr *devAddr, DRXaddr_t waddr, DRXaddr_t raddr, u32_t wdata, pu32_t rdata) @@ -1826,7 +1826,7 @@ static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg32(pI2CDeviceAddr_t devAddr, /*============================================================================*/ -static DRXStatus_t DRXJ_DAP_ReadReg8(pI2CDeviceAddr_t devAddr, +static DRXStatus_t DRXJ_DAP_ReadReg8(struct i2c_device_addr *devAddr, DRXaddr_t addr, pu8_t data, DRXflags_t flags) { @@ -1848,7 +1848,7 @@ static DRXStatus_t DRXJ_DAP_ReadReg8(pI2CDeviceAddr_t devAddr, * 16 bits register read access via audio token ring interface. * */ -static DRXStatus_t DRXJ_DAP_ReadAudReg16(pI2CDeviceAddr_t devAddr, +static DRXStatus_t DRXJ_DAP_ReadAudReg16(struct i2c_device_addr *devAddr, DRXaddr_t addr, pu16_t data) { u32_t startTimer = 0; @@ -1928,7 +1928,7 @@ static DRXStatus_t DRXJ_DAP_ReadAudReg16(pI2CDeviceAddr_t devAddr, /*============================================================================*/ -static DRXStatus_t DRXJ_DAP_ReadReg16(pI2CDeviceAddr_t devAddr, +static DRXStatus_t DRXJ_DAP_ReadReg16(struct i2c_device_addr *devAddr, DRXaddr_t addr, pu16_t data, DRXflags_t flags) { @@ -1951,7 +1951,7 @@ static DRXStatus_t DRXJ_DAP_ReadReg16(pI2CDeviceAddr_t devAddr, /*============================================================================*/ -static DRXStatus_t DRXJ_DAP_ReadReg32(pI2CDeviceAddr_t devAddr, +static DRXStatus_t DRXJ_DAP_ReadReg32(struct i2c_device_addr *devAddr, DRXaddr_t addr, pu32_t data, DRXflags_t flags) { @@ -1960,7 +1960,7 @@ static DRXStatus_t DRXJ_DAP_ReadReg32(pI2CDeviceAddr_t devAddr, /*============================================================================*/ -static DRXStatus_t DRXJ_DAP_WriteBlock(pI2CDeviceAddr_t devAddr, +static DRXStatus_t DRXJ_DAP_WriteBlock(struct i2c_device_addr *devAddr, DRXaddr_t addr, u16_t datasize, pu8_t data, DRXflags_t flags) @@ -1971,7 +1971,7 @@ static DRXStatus_t DRXJ_DAP_WriteBlock(pI2CDeviceAddr_t devAddr, /*============================================================================*/ -static DRXStatus_t DRXJ_DAP_WriteReg8(pI2CDeviceAddr_t devAddr, +static DRXStatus_t DRXJ_DAP_WriteReg8(struct i2c_device_addr *devAddr, DRXaddr_t addr, u8_t data, DRXflags_t flags) { @@ -1993,7 +1993,7 @@ static DRXStatus_t DRXJ_DAP_WriteReg8(pI2CDeviceAddr_t devAddr, * 16 bits register write access via audio token ring interface. * */ -static DRXStatus_t DRXJ_DAP_WriteAudReg16(pI2CDeviceAddr_t devAddr, +static DRXStatus_t DRXJ_DAP_WriteAudReg16(struct i2c_device_addr *devAddr, DRXaddr_t addr, u16_t data) { DRXStatus_t stat = DRX_STS_ERROR; @@ -2040,7 +2040,7 @@ static DRXStatus_t DRXJ_DAP_WriteAudReg16(pI2CDeviceAddr_t devAddr, /*============================================================================*/ -static DRXStatus_t DRXJ_DAP_WriteReg16(pI2CDeviceAddr_t devAddr, +static DRXStatus_t DRXJ_DAP_WriteReg16(struct i2c_device_addr *devAddr, DRXaddr_t addr, u16_t data, DRXflags_t flags) { @@ -2063,7 +2063,7 @@ static DRXStatus_t DRXJ_DAP_WriteReg16(pI2CDeviceAddr_t devAddr, /*============================================================================*/ -static DRXStatus_t DRXJ_DAP_WriteReg32(pI2CDeviceAddr_t devAddr, +static DRXStatus_t DRXJ_DAP_WriteReg32(struct i2c_device_addr *devAddr, DRXaddr_t addr, u32_t data, DRXflags_t flags) { @@ -2094,7 +2094,7 @@ static DRXStatus_t DRXJ_DAP_WriteReg32(pI2CDeviceAddr_t devAddr, * */ static -DRXStatus_t DRXJ_DAP_AtomicReadWriteBlock(pI2CDeviceAddr_t devAddr, +DRXStatus_t DRXJ_DAP_AtomicReadWriteBlock(struct i2c_device_addr *devAddr, DRXaddr_t addr, u16_t datasize, pu8_t data, Bool_t readFlag) @@ -2168,7 +2168,7 @@ rw_error: * \brief Atomic read of 32 bits words */ static -DRXStatus_t DRXJ_DAP_AtomicReadReg32(pI2CDeviceAddr_t devAddr, +DRXStatus_t DRXJ_DAP_AtomicReadReg32(struct i2c_device_addr *devAddr, DRXaddr_t addr, pu32_t data, DRXflags_t flags) { @@ -2258,7 +2258,7 @@ rw_error: * */ static DRXStatus_t -HICommand(const pI2CDeviceAddr_t devAddr, const pDRXJHiCmd_t cmd, pu16_t result) +HICommand(const struct i2c_device_addr *devAddr, const pDRXJHiCmd_t cmd, pu16_t result) { u16_t waitCmd = 0; u16_t nrRetries = 0; @@ -2338,7 +2338,7 @@ static DRXStatus_t InitHI(const pDRXDemodInstance_t demod) { pDRXJData_t extAttr = (pDRXJData_t) (NULL); pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) (NULL); + struct i2c_device_addr *devAddr = (struct i2c_device_addr *) (NULL); extAttr = (pDRXJData_t) demod->myExtAttr; commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; @@ -2415,7 +2415,7 @@ static DRXStatus_t GetDeviceCapabilities(pDRXDemodInstance_t demod) { pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); pDRXJData_t extAttr = (pDRXJData_t) NULL; - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) (NULL); + struct i2c_device_addr *devAddr = (struct i2c_device_addr *) (NULL); u16_t sioPdrOhwCfg = 0; u32_t sioTopJtagidLo = 0; u16_t bid = 0; @@ -2588,10 +2588,10 @@ rw_error: static DRXStatus_t PowerUpDevice(pDRXDemodInstance_t demod) { - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) (NULL); + struct i2c_device_addr *devAddr = (struct i2c_device_addr *) (NULL); u8_t data = 0; u16_t retryCount = 0; - I2CDeviceAddr_t wakeUpAddr; + struct i2c_device_addr wakeUpAddr; devAddr = demod->myI2CDevAddr; wakeUpAddr.i2cAddr = DRXJ_WAKE_UP_KEY; @@ -2603,12 +2603,12 @@ static DRXStatus_t PowerUpDevice(pDRXDemodInstance_t demod) do { data = 0; DRXBSP_I2C_WriteRead(&wakeUpAddr, 1, &data, - (pI2CDeviceAddr_t) (NULL), 0, + (struct i2c_device_addr *) (NULL), 0, (pu8_t) (NULL)); DRXBSP_HST_Sleep(10); retryCount++; } while ((DRXBSP_I2C_WriteRead - ((pI2CDeviceAddr_t) (NULL), 0, (pu8_t) (NULL), devAddr, 1, + ((struct i2c_device_addr *) (NULL), 0, (pu8_t) (NULL), devAddr, 1, &data) != DRX_STS_OK) && (retryCount < DRXJ_MAX_RETRIES_POWERUP)); @@ -2638,7 +2638,7 @@ static DRXStatus_t PowerUpDevice(pDRXDemodInstance_t demod) static DRXStatus_t CtrlSetCfgMPEGOutput(pDRXDemodInstance_t demod, pDRXCfgMPEGOutput_t cfgData) { - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) (NULL); + struct i2c_device_addr *devAddr = (struct i2c_device_addr *) (NULL); pDRXJData_t extAttr = (pDRXJData_t) (NULL); pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); u16_t fecOcRegMode = 0; @@ -3040,7 +3040,7 @@ rw_error: static DRXStatus_t CtrlGetCfgMPEGOutput(pDRXDemodInstance_t demod, pDRXCfgMPEGOutput_t cfgData) { - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) (NULL); + struct i2c_device_addr *devAddr = (struct i2c_device_addr *) (NULL); pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); DRXLockStatus_t lockStatus = DRX_NOT_LOCKED; u32_t rateReg = 0; @@ -3098,7 +3098,7 @@ rw_error: static DRXStatus_t SetMPEGTEIHandling(pDRXDemodInstance_t demod) { pDRXJData_t extAttr = (pDRXJData_t) (NULL); - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) (NULL); + struct i2c_device_addr *devAddr = (struct i2c_device_addr *) (NULL); u16_t fecOcDprMode = 0; u16_t fecOcSncMode = 0; u16_t fecOcEmsMode = 0; @@ -3146,7 +3146,7 @@ rw_error: static DRXStatus_t BitReverseMPEGOutput(pDRXDemodInstance_t demod) { pDRXJData_t extAttr = (pDRXJData_t) (NULL); - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) (NULL); + struct i2c_device_addr *devAddr = (struct i2c_device_addr *) (NULL); u16_t fecOcIprMode = 0; devAddr = demod->myI2CDevAddr; @@ -3182,7 +3182,7 @@ rw_error: static DRXStatus_t SetMPEGOutputClockRate(pDRXDemodInstance_t demod) { pDRXJData_t extAttr = (pDRXJData_t) (NULL); - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) (NULL); + struct i2c_device_addr *devAddr = (struct i2c_device_addr *) (NULL); devAddr = demod->myI2CDevAddr; extAttr = (pDRXJData_t) demod->myExtAttr; @@ -3210,7 +3210,7 @@ rw_error: static DRXStatus_t SetMPEGStartWidth(pDRXDemodInstance_t demod) { pDRXJData_t extAttr = (pDRXJData_t) (NULL); - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) (NULL); + struct i2c_device_addr *devAddr = (struct i2c_device_addr *) (NULL); u16_t fecOcCommMb = 0; pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) NULL; @@ -3862,7 +3862,7 @@ static DRXStatus_t SmartAntInit(pDRXDemodInstance_t demod) { u16_t data = 0; pDRXJData_t extAttr = NULL; - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; DRXUIOCfg_t UIOCfg = { DRX_UIO1, DRX_UIO_MODE_FIRMWARE_SMA }; devAddr = demod->myI2CDevAddr; @@ -3905,7 +3905,7 @@ static DRXStatus_t CtrlSetCfgSmartAnt(pDRXDemodInstance_t demod, pDRXJCfgSmartAnt_t smartAnt) { pDRXJData_t extAttr = NULL; - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; u16_t data = 0; u32_t startTime = 0; static Bool_t bitInverted = FALSE; @@ -3989,7 +3989,7 @@ rw_error: return (DRX_STS_ERROR); } -static DRXStatus_t SCUCommand(pI2CDeviceAddr_t devAddr, pDRXJSCUCmd_t cmd) +static DRXStatus_t SCUCommand(struct i2c_device_addr *devAddr, pDRXJSCUCmd_t cmd) { u16_t curCmd = 0; u32_t startTime = 0; @@ -4095,7 +4095,7 @@ rw_error: */ #define ADDR_AT_SCU_SPACE(x) ((x - 0x82E000) * 2) static -DRXStatus_t DRXJ_DAP_SCU_AtomicReadWriteBlock(pI2CDeviceAddr_t devAddr, DRXaddr_t addr, u16_t datasize, /* max 30 bytes because the limit of SCU parameter */ +DRXStatus_t DRXJ_DAP_SCU_AtomicReadWriteBlock(struct i2c_device_addr *devAddr, DRXaddr_t addr, u16_t datasize, /* max 30 bytes because the limit of SCU parameter */ pu8_t data, Bool_t readFlag) { DRXJSCUCmd_t scuCmd; @@ -4156,7 +4156,7 @@ rw_error: * \brief Atomic read of 16 bits words */ static -DRXStatus_t DRXJ_DAP_SCU_AtomicReadReg16(pI2CDeviceAddr_t devAddr, +DRXStatus_t DRXJ_DAP_SCU_AtomicReadReg16(struct i2c_device_addr *devAddr, DRXaddr_t addr, pu16_t data, DRXflags_t flags) { @@ -4183,7 +4183,7 @@ DRXStatus_t DRXJ_DAP_SCU_AtomicReadReg16(pI2CDeviceAddr_t devAddr, * \brief Atomic read of 16 bits words */ static -DRXStatus_t DRXJ_DAP_SCU_AtomicWriteReg16(pI2CDeviceAddr_t devAddr, +DRXStatus_t DRXJ_DAP_SCU_AtomicWriteReg16(struct i2c_device_addr *devAddr, DRXaddr_t addr, u16_t data, DRXflags_t flags) { @@ -4206,10 +4206,10 @@ CtrlI2CWriteRead(pDRXDemodInstance_t demod, pDRXI2CData_t i2cData) DRXStatus_t TunerI2CWriteRead(pTUNERInstance_t tuner, - pI2CDeviceAddr_t wDevAddr, + struct i2c_device_addr *wDevAddr, u16_t wCount, pu8_t wData, - pI2CDeviceAddr_t rDevAddr, u16_t rCount, pu8_t rData) + struct i2c_device_addr *rDevAddr, u16_t rCount, pu8_t rData) { pDRXDemodInstance_t demod; DRXI2CData_t i2cData = @@ -4233,7 +4233,7 @@ TunerI2CWriteRead(pTUNERInstance_t tuner, static DRXStatus_t ADCSyncMeasurement(pDRXDemodInstance_t demod, pu16_t count) { u16_t data = 0; - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; devAddr = demod->myI2CDevAddr; @@ -4278,7 +4278,7 @@ rw_error: static DRXStatus_t ADCSynchronization(pDRXDemodInstance_t demod) { u16_t count = 0; - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; devAddr = demod->myI2CDevAddr; @@ -4315,7 +4315,7 @@ rw_error: static DRXStatus_t IQMSetAf(pDRXDemodInstance_t demod, Bool_t active) { u16_t data = 0; - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; extAttr = (pDRXJData_t) demod->myExtAttr; @@ -4359,7 +4359,7 @@ static DRXStatus_t CtrlSetCfgPdrSafeMode(pDRXDemodInstance_t demod, pBool_t enable) { pDRXJData_t extAttr = (pDRXJData_t) NULL; - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) NULL; + struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) NULL; if (enable == NULL) { @@ -4551,7 +4551,7 @@ static DRXStatus_t CtrlValidateUCode(pDRXDemodInstance_t demod) */ static DRXStatus_t InitAGC(pDRXDemodInstance_t demod) { - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; pDRXCommonAttr_t commonAttr = NULL; pDRXJData_t extAttr = NULL; pDRXJCfgAgc_t pAgcRfSettings = NULL; @@ -4760,7 +4760,7 @@ static DRXStatus_t SetFrequency(pDRXDemodInstance_t demod, pDRXChannel_t channel, DRXFrequency_t tunerFreqOffset) { - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; pDRXCommonAttr_t commonAttr = NULL; DRXFrequency_t samplingFrequency = 0; DRXFrequency_t frequencyShift = 0; @@ -4874,7 +4874,7 @@ static DRXStatus_t GetSigStrength(pDRXDemodInstance_t demod, pu16_t sigStrength) u16_t rfAgcMax = 0; u16_t rfAgcMin = 0; pDRXJData_t extAttr = NULL; - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; extAttr = (pDRXJData_t) demod->myExtAttr; devAddr = demod->myI2CDevAddr; @@ -4930,7 +4930,7 @@ static DRXStatus_t GetAccPktErr(pDRXDemodInstance_t demod, pu16_t packetErr) static u16_t lastPktErr = 0; u16_t data = 0; pDRXJData_t extAttr = NULL; - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; extAttr = (pDRXJData_t) demod->myExtAttr; devAddr = demod->myI2CDevAddr; @@ -4993,7 +4993,7 @@ static DRXStatus_t GetSTRFreqOffset(pDRXDemodInstance_t demod, s32_t * STRFreq) u32_t symbolNomFrequencyRatio = 0; DRXStandard_t standard = DRX_STANDARD_UNKNOWN; - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; devAddr = demod->myI2CDevAddr; @@ -5036,7 +5036,7 @@ static DRXStatus_t GetCTLFreqOffset(pDRXDemodInstance_t demod, s32_t * CTLFreq) u32_t data64Lo = 0; pDRXJData_t extAttr = NULL; pDRXCommonAttr_t commonAttr = NULL; - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; devAddr = demod->myI2CDevAddr; extAttr = (pDRXJData_t) demod->myExtAttr; @@ -5084,7 +5084,7 @@ rw_error: static DRXStatus_t SetAgcRf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings, Bool_t atomic) { - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; pDRXJCfgAgc_t pAgcSettings = NULL; pDRXCommonAttr_t commonAttr = NULL; @@ -5262,7 +5262,7 @@ rw_error: static DRXStatus_t GetAgcRf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings) { - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; DRXStandard_t standard = DRX_STANDARD_UNKNOWN; @@ -5323,7 +5323,7 @@ rw_error: static DRXStatus_t SetAgcIf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings, Bool_t atomic) { - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; pDRXJCfgAgc_t pAgcSettings = NULL; pDRXCommonAttr_t commonAttr = NULL; @@ -5514,7 +5514,7 @@ rw_error: static DRXStatus_t GetAgcIf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings) { - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; DRXStandard_t standard = DRX_STANDARD_UNKNOWN; @@ -5576,7 +5576,7 @@ rw_error: static DRXStatus_t SetIqmAf(pDRXDemodInstance_t demod, Bool_t active) { u16_t data = 0; - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; devAddr = demod->myI2CDevAddr; @@ -5623,7 +5623,7 @@ rw_error: */ static DRXStatus_t PowerDownVSB(pDRXDemodInstance_t demod, Bool_t primary) { - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; DRXJSCUCmd_t cmdSCU = { /* command */ 0, /* parameterLen */ 0, /* resultLen */ 0, @@ -5678,7 +5678,7 @@ rw_error: */ static DRXStatus_t SetVSBLeakNGain(pDRXDemodInstance_t demod) { - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; const u8_t vsb_ffe_leak_gain_ram0[] = { DRXJ_16TO8(0x8), /* FFETRAINLKRATIO1 */ @@ -5888,7 +5888,7 @@ rw_error: */ static DRXStatus_t SetVSB(pDRXDemodInstance_t demod) { - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; u16_t cmdResult = 0; u16_t cmdParam = 0; pDRXCommonAttr_t commonAttr = NULL; @@ -6101,11 +6101,11 @@ rw_error: } /** -* \fn static short GetVSBPostRSPckErr(pI2CDeviceAddr_t devAddr, pu16_t PckErrs) +* \fn static short GetVSBPostRSPckErr(struct i2c_device_addr * devAddr, pu16_t PckErrs) * \brief Get the values of packet error in 8VSB mode * \return Error code */ -static DRXStatus_t GetVSBPostRSPckErr(pI2CDeviceAddr_t devAddr, pu16_t pckErrs) +static DRXStatus_t GetVSBPostRSPckErr(struct i2c_device_addr *devAddr, pu16_t pckErrs) { u16_t data = 0; u16_t period = 0; @@ -6132,11 +6132,11 @@ rw_error: } /** -* \fn static short GetVSBBer(pI2CDeviceAddr_t devAddr, pu32_t ber) +* \fn static short GetVSBBer(struct i2c_device_addr * devAddr, pu32_t ber) * \brief Get the values of ber in VSB mode * \return Error code */ -static DRXStatus_t GetVSBpostViterbiBer(pI2CDeviceAddr_t devAddr, pu32_t ber) +static DRXStatus_t GetVSBpostViterbiBer(struct i2c_device_addr *devAddr, pu32_t ber) { u16_t data = 0; u16_t period = 0; @@ -6170,11 +6170,11 @@ rw_error: } /** -* \fn static short GetVSBpreViterbiBer(pI2CDeviceAddr_t devAddr, pu32_t ber) +* \fn static short GetVSBpreViterbiBer(struct i2c_device_addr * devAddr, pu32_t ber) * \brief Get the values of ber in VSB mode * \return Error code */ -static DRXStatus_t GetVSBpreViterbiBer(pI2CDeviceAddr_t devAddr, pu32_t ber) +static DRXStatus_t GetVSBpreViterbiBer(struct i2c_device_addr *devAddr, pu32_t ber) { u16_t data = 0; @@ -6189,11 +6189,11 @@ rw_error: } /** -* \fn static short GetVSBSymbErr(pI2CDeviceAddr_t devAddr, pu32_t ber) +* \fn static short GetVSBSymbErr(struct i2c_device_addr * devAddr, pu32_t ber) * \brief Get the values of ber in VSB mode * \return Error code */ -static DRXStatus_t GetVSBSymbErr(pI2CDeviceAddr_t devAddr, pu32_t ser) +static DRXStatus_t GetVSBSymbErr(struct i2c_device_addr *devAddr, pu32_t ser) { u16_t data = 0; u16_t period = 0; @@ -6219,11 +6219,11 @@ rw_error: } /** -* \fn static DRXStatus_t GetVSBMER(pI2CDeviceAddr_t devAddr, pu16_t mer) +* \fn static DRXStatus_t GetVSBMER(struct i2c_device_addr * devAddr, pu16_t mer) * \brief Get the values of MER * \return Error code */ -static DRXStatus_t GetVSBMER(pI2CDeviceAddr_t devAddr, pu16_t mer) +static DRXStatus_t GetVSBMER(struct i2c_device_addr *devAddr, pu16_t mer) { u16_t dataHi = 0; @@ -6248,7 +6248,7 @@ rw_error: static DRXStatus_t CtrlGetVSBConstel(pDRXDemodInstance_t demod, pDRXComplex_t complexNr) { - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; /**< device address */ u16_t vsbTopCommMb = 0; /**< VSB SL MB configuration */ u16_t vsbTopCommMbInit = 0; /**< VSB SL MB intial configuration */ @@ -6319,7 +6319,7 @@ static DRXStatus_t PowerDownQAM(pDRXDemodInstance_t demod, Bool_t primary) /* *result */ NULL }; u16_t cmdResult = 0; - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; DRXCfgMPEGOutput_t cfgMPEGOutput; @@ -6384,7 +6384,7 @@ static DRXStatus_t SetQAMMeasurement(pDRXDemodInstance_t demod, DRXConstellation_t constellation, u32_t symbolRate) { - pI2CDeviceAddr_t devAddr = NULL; /* device address for I2C writes */ + struct i2c_device_addr *devAddr = NULL; /* device address for I2C writes */ pDRXJData_t extAttr = NULL; /* Global data container for DRXJ specif data */ u32_t fecBitsDesired = 0; /* BER accounting period */ u16_t fecRsPlen = 0; /* defines RS BER measurement period */ @@ -6545,7 +6545,7 @@ rw_error: */ static DRXStatus_t SetQAM16(pDRXDemodInstance_t demod) { - pI2CDeviceAddr_t devAddr = demod->myI2CDevAddr; + struct i2c_device_addr *devAddr = demod->myI2CDevAddr; const u8_t qamDqQualFun[] = { DRXJ_16TO8(2), /* fun0 */ DRXJ_16TO8(2), /* fun1 */ @@ -6625,7 +6625,7 @@ rw_error: */ static DRXStatus_t SetQAM32(pDRXDemodInstance_t demod) { - pI2CDeviceAddr_t devAddr = demod->myI2CDevAddr; + struct i2c_device_addr *devAddr = demod->myI2CDevAddr; const u8_t qamDqQualFun[] = { DRXJ_16TO8(3), /* fun0 */ DRXJ_16TO8(3), /* fun1 */ @@ -6705,7 +6705,7 @@ rw_error: */ static DRXStatus_t SetQAM64(pDRXDemodInstance_t demod) { - pI2CDeviceAddr_t devAddr = demod->myI2CDevAddr; + struct i2c_device_addr *devAddr = demod->myI2CDevAddr; const u8_t qamDqQualFun[] = { /* this is hw reset value. no necessary to re-write */ DRXJ_16TO8(4), /* fun0 */ DRXJ_16TO8(4), /* fun1 */ @@ -6785,7 +6785,7 @@ rw_error: */ static DRXStatus_t SetQAM128(pDRXDemodInstance_t demod) { - pI2CDeviceAddr_t devAddr = demod->myI2CDevAddr; + struct i2c_device_addr *devAddr = demod->myI2CDevAddr; const u8_t qamDqQualFun[] = { DRXJ_16TO8(6), /* fun0 */ DRXJ_16TO8(6), /* fun1 */ @@ -6865,7 +6865,7 @@ rw_error: */ static DRXStatus_t SetQAM256(pDRXDemodInstance_t demod) { - pI2CDeviceAddr_t devAddr = demod->myI2CDevAddr; + struct i2c_device_addr *devAddr = demod->myI2CDevAddr; const u8_t qamDqQualFun[] = { DRXJ_16TO8(8), /* fun0 */ DRXJ_16TO8(8), /* fun1 */ @@ -6951,7 +6951,7 @@ static DRXStatus_t SetQAM(pDRXDemodInstance_t demod, pDRXChannel_t channel, DRXFrequency_t tunerFreqOffset, u32_t op) { - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; pDRXCommonAttr_t commonAttr = NULL; u16_t cmdResult = 0; @@ -7422,7 +7422,7 @@ static DRXStatus_t qamFlipSpec(pDRXDemodInstance_t demod, pDRXChannel_t channel) u16_t fsmState = 0; int i = 0; int ofsofs = 0; - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; devAddr = demod->myI2CDevAddr; @@ -7834,7 +7834,7 @@ rw_error: /*============================================================================*/ /** -* \fn static short GetQAMRSErrCount(pI2CDeviceAddr_t devAddr) +* \fn static short GetQAMRSErrCount(struct i2c_device_addr * devAddr) * \brief Get RS error count in QAM mode (used for post RS BER calculation) * \return Error code * @@ -7842,7 +7842,7 @@ rw_error: * */ static DRXStatus_t -GetQAMRSErrCount(pI2CDeviceAddr_t devAddr, pDRXJRSErrors_t RSErrors) +GetQAMRSErrCount(struct i2c_device_addr *devAddr, pDRXJRSErrors_t RSErrors) { u16_t nrBitErrors = 0, nrSymbolErrors = 0, @@ -7898,7 +7898,7 @@ rw_error: static DRXStatus_t CtrlGetQAMSigQuality(pDRXDemodInstance_t demod, pDRXSigQuality_t sigQuality) { - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; DRXConstellation_t constellation = DRX_CONSTELLATION_UNKNOWN; DRXJRSErrors_t measuredRSErrors = { 0, 0, 0, 0, 0 }; @@ -8088,7 +8088,7 @@ CtrlGetQAMConstel(pDRXDemodInstance_t demod, pDRXComplex_t complexNr) u16_t im = 0; /**< constellation Im part */ u16_t re = 0; /**< constellation Re part */ u32_t data = 0; - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; /**< device address */ /* read device info */ @@ -8270,7 +8270,7 @@ static DRXStatus_t AtvEquCoefIndex(DRXStandard_t standard, int *index) static DRXStatus_t AtvUpdateConfig(pDRXDemodInstance_t demod, Bool_t forceUpdate) { - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; devAddr = demod->myI2CDevAddr; @@ -8641,7 +8641,7 @@ static DRXStatus_t CtrlGetCfgAtvAgcStatus(pDRXDemodInstance_t demod, pDRXJCfgAtvAgcStatus_t agcStatus) { - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; u16_t data = 0; u32_t tmp = 0; @@ -8744,7 +8744,7 @@ rw_error: */ static DRXStatus_t PowerUpATV(pDRXDemodInstance_t demod, DRXStandard_t standard) { - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; devAddr = demod->myI2CDevAddr; @@ -8782,7 +8782,7 @@ rw_error: static DRXStatus_t PowerDownATV(pDRXDemodInstance_t demod, DRXStandard_t standard, Bool_t primary) { - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; DRXJSCUCmd_t cmdSCU = { /* command */ 0, /* parameterLen */ 0, /* resultLen */ 0, @@ -9100,7 +9100,7 @@ trouble ? DRXJ_16TO8(70) /* im27 */ }; - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; DRXJSCUCmd_t cmdSCU = { /* command */ 0, /* parameterLen */ 0, /* resultLen */ 0, @@ -9468,7 +9468,7 @@ SetATVChannel(pDRXDemodInstance_t demod, }; u16_t cmdResult = 0; pDRXJData_t extAttr = NULL; - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; devAddr = demod->myI2CDevAddr; extAttr = (pDRXJData_t) demod->myExtAttr; @@ -9527,7 +9527,7 @@ GetATVChannel(pDRXDemodInstance_t demod, pDRXChannel_t channel, DRXStandard_t standard) { DRXFrequency_t offset = 0; - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; devAddr = demod->myI2CDevAddr; @@ -9612,7 +9612,7 @@ rw_error: static DRXStatus_t GetAtvSigStrength(pDRXDemodInstance_t demod, pu16_t sigStrength) { - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; /* All weights must add up to 100 (%) @@ -9721,7 +9721,7 @@ rw_error: static DRXStatus_t AtvSigQuality(pDRXDemodInstance_t demod, pDRXSigQuality_t sigQuality) { - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; u16_t qualityIndicator = 0; devAddr = demod->myI2CDevAddr; @@ -9780,7 +9780,7 @@ rw_error: static DRXStatus_t PowerUpAud(pDRXDemodInstance_t demod, Bool_t setStandard) { DRXAudStandard_t audStandard = DRX_AUD_STANDARD_AUTO; - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; devAddr = demod->myI2CDevAddr; @@ -9808,10 +9808,10 @@ rw_error: */ static DRXStatus_t PowerDownAud(pDRXDemodInstance_t demod) { - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; - devAddr = (pI2CDeviceAddr_t) demod->myI2CDevAddr; + devAddr = (struct i2c_device_addr *) demod->myI2CDevAddr; extAttr = (pDRXJData_t) demod->myExtAttr; WR16(devAddr, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP); @@ -9833,7 +9833,7 @@ rw_error: */ static DRXStatus_t AUDGetModus(pDRXDemodInstance_t demod, pu16_t modus) { - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; u16_t rModus = 0; @@ -9844,7 +9844,7 @@ static DRXStatus_t AUDGetModus(pDRXDemodInstance_t demod, pu16_t modus) return DRX_STS_INVALID_ARG; } - devAddr = (pI2CDeviceAddr_t) demod->myI2CDevAddr; + devAddr = (struct i2c_device_addr *) demod->myI2CDevAddr; extAttr = (pDRXJData_t) demod->myExtAttr; /* power up */ @@ -9879,7 +9879,7 @@ rw_error: static DRXStatus_t AUDCtrlGetCfgRDS(pDRXDemodInstance_t demod, pDRXCfgAudRDS_t status) { - pI2CDeviceAddr_t addr = NULL; + struct i2c_device_addr *addr = NULL; pDRXJData_t extAttr = NULL; u16_t rRDSArrayCntInit = 0; @@ -9887,7 +9887,7 @@ AUDCtrlGetCfgRDS(pDRXDemodInstance_t demod, pDRXCfgAudRDS_t status) u16_t rRDSData = 0; u16_t RDSDataCnt = 0; - addr = (pI2CDeviceAddr_t) demod->myI2CDevAddr; + addr = (struct i2c_device_addr *) demod->myI2CDevAddr; extAttr = (pDRXJData_t) demod->myExtAttr; if (status == NULL) { @@ -9950,7 +9950,7 @@ static DRXStatus_t AUDCtrlGetCarrierDetectStatus(pDRXDemodInstance_t demod, pDRXAudStatus_t status) { pDRXJData_t extAttr = NULL; - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; u16_t rData = 0; @@ -9958,7 +9958,7 @@ AUDCtrlGetCarrierDetectStatus(pDRXDemodInstance_t demod, pDRXAudStatus_t status) return DRX_STS_INVALID_ARG; } - devAddr = (pI2CDeviceAddr_t) demod->myI2CDevAddr; + devAddr = (struct i2c_device_addr *) demod->myI2CDevAddr; extAttr = (pDRXJData_t) demod->myExtAttr; /* power up */ @@ -10028,7 +10028,7 @@ static DRXStatus_t AUDCtrlGetStatus(pDRXDemodInstance_t demod, pDRXAudStatus_t status) { pDRXJData_t extAttr = NULL; - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; DRXCfgAudRDS_t rds = { FALSE, {0} }; u16_t rData = 0; @@ -10036,7 +10036,7 @@ AUDCtrlGetStatus(pDRXDemodInstance_t demod, pDRXAudStatus_t status) return DRX_STS_INVALID_ARG; } - devAddr = (pI2CDeviceAddr_t) demod->myI2CDevAddr; + devAddr = (struct i2c_device_addr *) demod->myI2CDevAddr; extAttr = (pDRXJData_t) demod->myExtAttr; /* carrier detection */ @@ -10068,7 +10068,7 @@ rw_error: static DRXStatus_t AUDCtrlGetCfgVolume(pDRXDemodInstance_t demod, pDRXCfgAudVolume_t volume) { - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; u16_t rVolume = 0; @@ -10080,7 +10080,7 @@ AUDCtrlGetCfgVolume(pDRXDemodInstance_t demod, pDRXCfgAudVolume_t volume) return DRX_STS_INVALID_ARG; } - devAddr = (pI2CDeviceAddr_t) demod->myI2CDevAddr; + devAddr = (struct i2c_device_addr *) demod->myI2CDevAddr; extAttr = (pDRXJData_t) demod->myExtAttr; /* power up */ @@ -10202,7 +10202,7 @@ rw_error: static DRXStatus_t AUDCtrlSetCfgVolume(pDRXDemodInstance_t demod, pDRXCfgAudVolume_t volume) { - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; u16_t wVolume = 0; @@ -10212,7 +10212,7 @@ AUDCtrlSetCfgVolume(pDRXDemodInstance_t demod, pDRXCfgAudVolume_t volume) return DRX_STS_INVALID_ARG; } - devAddr = (pI2CDeviceAddr_t) demod->myI2CDevAddr; + devAddr = (struct i2c_device_addr *) demod->myI2CDevAddr; extAttr = (pDRXJData_t) demod->myExtAttr; /* power up */ @@ -10337,7 +10337,7 @@ rw_error: static DRXStatus_t AUDCtrlGetCfgOutputI2S(pDRXDemodInstance_t demod, pDRXCfgI2SOutput_t output) { - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; u16_t wI2SConfig = 0; @@ -10347,7 +10347,7 @@ AUDCtrlGetCfgOutputI2S(pDRXDemodInstance_t demod, pDRXCfgI2SOutput_t output) return DRX_STS_INVALID_ARG; } - devAddr = (pI2CDeviceAddr_t) demod->myI2CDevAddr; + devAddr = (struct i2c_device_addr *) demod->myI2CDevAddr; extAttr = (pDRXJData_t) demod->myExtAttr; /* power up */ @@ -10440,7 +10440,7 @@ rw_error: static DRXStatus_t AUDCtrlSetCfgOutputI2S(pDRXDemodInstance_t demod, pDRXCfgI2SOutput_t output) { - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; u16_t wI2SConfig = 0; @@ -10453,7 +10453,7 @@ AUDCtrlSetCfgOutputI2S(pDRXDemodInstance_t demod, pDRXCfgI2SOutput_t output) return DRX_STS_INVALID_ARG; } - devAddr = (pI2CDeviceAddr_t) demod->myI2CDevAddr; + devAddr = (struct i2c_device_addr *) demod->myI2CDevAddr; extAttr = (pDRXJData_t) demod->myExtAttr; /* power up */ @@ -10596,7 +10596,7 @@ static DRXStatus_t AUDCtrlGetCfgAutoSound(pDRXDemodInstance_t demod, pDRXCfgAudAutoSound_t autoSound) { - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) NULL; + struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; pDRXJData_t extAttr = (pDRXJData_t) NULL; u16_t rModus = 0; @@ -10653,7 +10653,7 @@ static DRXStatus_t AUDCtrSetlCfgAutoSound(pDRXDemodInstance_t demod, pDRXCfgAudAutoSound_t autoSound) { - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) NULL; + struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; pDRXJData_t extAttr = (pDRXJData_t) NULL; u16_t rModus = 0; @@ -10718,7 +10718,7 @@ rw_error: static DRXStatus_t AUDCtrlGetCfgASSThres(pDRXDemodInstance_t demod, pDRXCfgAudASSThres_t thres) { - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) NULL; + struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; pDRXJData_t extAttr = (pDRXJData_t) NULL; u16_t thresA2 = 0; @@ -10762,7 +10762,7 @@ rw_error: static DRXStatus_t AUDCtrlSetCfgASSThres(pDRXDemodInstance_t demod, pDRXCfgAudASSThres_t thres) { - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) NULL; + struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; pDRXJData_t extAttr = (pDRXJData_t) NULL; if (thres == NULL) { @@ -10801,7 +10801,7 @@ rw_error: static DRXStatus_t AUDCtrlGetCfgCarrier(pDRXDemodInstance_t demod, pDRXCfgAudCarriers_t carriers) { - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) NULL; + struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; pDRXJData_t extAttr = (pDRXJData_t) NULL; u16_t wModus = 0; @@ -10906,7 +10906,7 @@ rw_error: static DRXStatus_t AUDCtrlSetCfgCarrier(pDRXDemodInstance_t demod, pDRXCfgAudCarriers_t carriers) { - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) NULL; + struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; pDRXJData_t extAttr = (pDRXJData_t) NULL; u16_t wModus = 0; @@ -11006,7 +11006,7 @@ rw_error: static DRXStatus_t AUDCtrlGetCfgMixer(pDRXDemodInstance_t demod, pDRXCfgAudMixer_t mixer) { - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) NULL; + struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; pDRXJData_t extAttr = (pDRXJData_t) NULL; u16_t srcI2SMatr = 0; @@ -11101,7 +11101,7 @@ rw_error: static DRXStatus_t AUDCtrlSetCfgMixer(pDRXDemodInstance_t demod, pDRXCfgAudMixer_t mixer) { - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) NULL; + struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; pDRXJData_t extAttr = (pDRXJData_t) NULL; u16_t srcI2SMatr = 0; @@ -11209,7 +11209,7 @@ rw_error: static DRXStatus_t AUDCtrlSetCfgAVSync(pDRXDemodInstance_t demod, pDRXCfgAudAVSync_t avSync) { - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) NULL; + struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; pDRXJData_t extAttr = (pDRXJData_t) NULL; u16_t wAudVidSync = 0; @@ -11274,7 +11274,7 @@ rw_error: static DRXStatus_t AUDCtrlGetCfgAVSync(pDRXDemodInstance_t demod, pDRXCfgAudAVSync_t avSync) { - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) NULL; + struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; pDRXJData_t extAttr = (pDRXJData_t) NULL; u16_t wAudVidSync = 0; @@ -11331,7 +11331,7 @@ rw_error: static DRXStatus_t AUDCtrlGetCfgDev(pDRXDemodInstance_t demod, pDRXCfgAudDeviation_t dev) { - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) NULL; + struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; pDRXJData_t extAttr = (pDRXJData_t) NULL; u16_t rModus = 0; @@ -11372,7 +11372,7 @@ rw_error: static DRXStatus_t AUDCtrlSetCfgDev(pDRXDemodInstance_t demod, pDRXCfgAudDeviation_t dev) { - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) NULL; + struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; pDRXJData_t extAttr = (pDRXJData_t) NULL; u16_t wModus = 0; @@ -11425,7 +11425,7 @@ rw_error: static DRXStatus_t AUDCtrlGetCfgPrescale(pDRXDemodInstance_t demod, pDRXCfgAudPrescale_t presc) { - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) NULL; + struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; pDRXJData_t extAttr = (pDRXJData_t) NULL; u16_t rMaxFMDeviation = 0; @@ -11500,7 +11500,7 @@ rw_error: static DRXStatus_t AUDCtrlSetCfgPrescale(pDRXDemodInstance_t demod, pDRXCfgAudPrescale_t presc) { - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) NULL; + struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; pDRXJData_t extAttr = (pDRXJData_t) NULL; u16_t wMaxFMDeviation = 0; @@ -11582,7 +11582,7 @@ rw_error: */ static DRXStatus_t AUDCtrlBeep(pDRXDemodInstance_t demod, pDRXAudBeep_t beep) { - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) NULL; + struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; pDRXJData_t extAttr = (pDRXJData_t) NULL; u16_t theBeep = 0; @@ -11641,7 +11641,7 @@ rw_error: static DRXStatus_t AUDCtrlSetStandard(pDRXDemodInstance_t demod, pDRXAudStandard_t standard) { - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; DRXStandard_t currentStandard = DRX_STANDARD_UNKNOWN; @@ -11657,7 +11657,7 @@ AUDCtrlSetStandard(pDRXDemodInstance_t demod, pDRXAudStandard_t standard) return DRX_STS_INVALID_ARG; } - devAddr = (pI2CDeviceAddr_t) demod->myI2CDevAddr; + devAddr = (struct i2c_device_addr *) demod->myI2CDevAddr; extAttr = (pDRXJData_t) demod->myExtAttr; /* power up */ @@ -11819,7 +11819,7 @@ rw_error: static DRXStatus_t AUDCtrlGetStandard(pDRXDemodInstance_t demod, pDRXAudStandard_t standard) { - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; u16_t rData = 0; @@ -11829,7 +11829,7 @@ AUDCtrlGetStandard(pDRXDemodInstance_t demod, pDRXAudStandard_t standard) } extAttr = (pDRXJData_t) demod->myExtAttr; - devAddr = (pI2CDeviceAddr_t) demod->myI2CDevAddr; + devAddr = (struct i2c_device_addr *) demod->myI2CDevAddr; /* power up */ if (extAttr->audData.audioIsActive == FALSE) { @@ -11997,7 +11997,7 @@ rw_error: */ static DRXStatus_t GetOOBLockStatus(pDRXDemodInstance_t demod, - pI2CDeviceAddr_t devAddr, pDRXLockStatus_t oobLock) + struct i2c_device_addr *devAddr, pDRXLockStatus_t oobLock) { DRXJSCUCmd_t scuCmd; u16_t cmdResult[2]; @@ -12051,7 +12051,7 @@ rw_error: * */ static DRXStatus_t -GetOOBSymbolRateOffset(pI2CDeviceAddr_t devAddr, ps32_t SymbolRateOffset) +GetOOBSymbolRateOffset(struct i2c_device_addr *devAddr, ps32_t SymbolRateOffset) { /* offset = -{(timingOffset/2^19)*(symbolRate/12,656250MHz)}*10^6 [ppm] */ /* offset = -{(timingOffset/2^19)*(symbolRate/12656250)}*10^6 [ppm] */ @@ -12146,7 +12146,7 @@ GetOOBFreqOffset(pDRXDemodInstance_t demod, pDRXFrequency_t freqOffset) u32_t data64Lo = 0; u32_t tempFreqOffset = 0; pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; /* check arguments */ if ((demod == NULL) || (freqOffset == NULL)) { @@ -12238,7 +12238,7 @@ GetOOBFrequency(pDRXDemodInstance_t demod, pDRXFrequency_t frequency) u16_t data = 0; DRXFrequency_t freqOffset = 0; DRXFrequency_t freq = 0; - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; devAddr = demod->myI2CDevAddr; @@ -12267,7 +12267,7 @@ rw_error: * Gets OOB MER. Table for MER is in Programming guide. * */ -static DRXStatus_t GetOOBMER(pI2CDeviceAddr_t devAddr, pu32_t mer) +static DRXStatus_t GetOOBMER(struct i2c_device_addr *devAddr, pu32_t mer) { u16_t data = 0; @@ -12411,7 +12411,7 @@ rw_error: static DRXStatus_t SetOrxNsuAox(pDRXDemodInstance_t demod, Bool_t active) { u16_t data = 0; - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; extAttr = (pDRXJData_t) demod->myExtAttr; @@ -12476,7 +12476,7 @@ static DRXStatus_t CtrlSetOOB(pDRXDemodInstance_t demod, pDRXOOB_t oobParam) #ifndef DRXJ_DIGITAL_ONLY DRXOOBDownstreamStandard_t standard = DRX_OOB_MODE_A; DRXFrequency_t freq = 0; /* KHz */ - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; u16_t i = 0; Bool_t mirrorFreqSpectOOB = FALSE; @@ -12750,7 +12750,7 @@ static DRXStatus_t CtrlGetOOB(pDRXDemodInstance_t demod, pDRXOOBStatus_t oobStatus) { #ifndef DRXJ_DIGITAL_ONLY - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; u16_t data = 0; @@ -12793,7 +12793,7 @@ rw_error: static DRXStatus_t CtrlSetCfgOOBPreSAW(pDRXDemodInstance_t demod, pu16_t cfgData) { - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; if (cfgData == NULL) { @@ -12843,7 +12843,7 @@ CtrlGetCfgOOBPreSAW(pDRXDemodInstance_t demod, pu16_t cfgData) static DRXStatus_t CtrlSetCfgOOBLoPower(pDRXDemodInstance_t demod, pDRXJCfgOobLoPower_t cfgData) { - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; if (cfgData == NULL) { @@ -12913,7 +12913,7 @@ CtrlSetChannel(pDRXDemodInstance_t demod, pDRXChannel_t channel) DRXFrequency_t tunerFreqOffset = 0; DRXFrequency_t intermediateFreq = 0; pDRXJData_t extAttr = NULL; - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; DRXStandard_t standard = DRX_STANDARD_UNKNOWN; TUNERMode_t tunerMode = 0; pDRXCommonAttr_t commonAttr = NULL; @@ -13289,7 +13289,7 @@ rw_error: static DRXStatus_t CtrlGetChannel(pDRXDemodInstance_t demod, pDRXChannel_t channel) { - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; DRXLockStatus_t lockStatus = DRX_NOT_LOCKED; DRXStandard_t standard = DRX_STANDARD_UNKNOWN; @@ -13540,7 +13540,7 @@ mer2indicator(u16_t mer, u16_t minMer, u16_t thresholdMer, u16_t maxMer) static DRXStatus_t CtrlSigQuality(pDRXDemodInstance_t demod, pDRXSigQuality_t sigQuality) { - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; DRXStandard_t standard = DRX_STANDARD_UNKNOWN; DRXLockStatus_t lockStatus = DRX_NOT_LOCKED; @@ -13676,7 +13676,7 @@ CtrlLockStatus(pDRXDemodInstance_t demod, pDRXLockStatus_t lockStat) { DRXStandard_t standard = DRX_STANDARD_UNKNOWN; pDRXJData_t extAttr = NULL; - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; DRXJSCUCmd_t cmdSCU = { /* command */ 0, /* parameterLen */ 0, /* resultLen */ 0, @@ -13947,7 +13947,7 @@ static DRXStatus_t CtrlGetCfgSymbolClockOffset(pDRXDemodInstance_t demod, ps32_t rateOffset) { DRXStandard_t standard = DRX_STANDARD_UNKNOWN; - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; /* check arguments */ @@ -13998,7 +13998,7 @@ CtrlPowerMode(pDRXDemodInstance_t demod, pDRXPowerMode_t mode) { pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) NULL; pDRXJData_t extAttr = (pDRXJData_t) NULL; - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) NULL; + struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; u16_t sioCcPwdMode = 0; commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; @@ -14125,7 +14125,7 @@ static DRXStatus_t CtrlVersion(pDRXDemodInstance_t demod, pDRXVersionList_t * versionList) { pDRXJData_t extAttr = (pDRXJData_t) (NULL); - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) (NULL); + struct i2c_device_addr *devAddr = (struct i2c_device_addr *) (NULL); pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); u16_t ucodeMajorMinor = 0; /* BCD Ma:Ma:Ma:Mi */ u16_t ucodePatch = 0; /* BCD Pa:Pa:Pa:Pa */ @@ -14282,7 +14282,7 @@ static DRXStatus_t CtrlProbeDevice(pDRXDemodInstance_t demod) if (commonAttr->isOpened == FALSE || commonAttr->currentPowerMode != DRX_POWER_UP) { - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; DRXPowerMode_t powerMode = DRX_POWER_UP; u32_t jtag = 0; @@ -14378,7 +14378,7 @@ CtrlUCodeUpload(pDRXDemodInstance_t demod, u16_t mcNrOfBlks = 0; u16_t mcMagicWord = 0; pu8_t mcData = (pu8_t) (NULL); - pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) (NULL); + struct i2c_device_addr *devAddr = (struct i2c_device_addr *) (NULL); pDRXJData_t extAttr = (pDRXJData_t) (NULL); devAddr = demod->myI2CDevAddr; @@ -14610,7 +14610,7 @@ rw_error: static DRXStatus_t CtrlGetCfgOOBMisc(pDRXDemodInstance_t demod, pDRXJCfgOOBMisc_t misc) { - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; u16_t lock = 0U; u16_t state = 0U; u16_t data = 0U; @@ -14662,7 +14662,7 @@ rw_error: static DRXStatus_t CtrlGetCfgVSBMisc(pDRXDemodInstance_t demod, pDRXJCfgVSBMisc_t misc) { - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; /* check arguments */ if (misc == NULL) { @@ -14899,7 +14899,7 @@ CtrlGetCfgAgcRf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings) static DRXStatus_t CtrlGetCfgAgcInternal(pDRXDemodInstance_t demod, pu16_t agcInternal) { - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; DRXLockStatus_t lockStatus = DRX_NOT_LOCKED; pDRXJData_t extAttr = NULL; u16_t iqmCfScaleSh = 0; @@ -14982,7 +14982,7 @@ rw_error: static DRXStatus_t CtrlSetCfgPreSaw(pDRXDemodInstance_t demod, pDRXJCfgPreSaw_t preSaw) { - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; devAddr = demod->myI2CDevAddr; @@ -15051,7 +15051,7 @@ rw_error: static DRXStatus_t CtrlSetCfgAfeGain(pDRXDemodInstance_t demod, pDRXJCfgAfeGain_t afeGain) { - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; u8_t gain = 0; @@ -15127,7 +15127,7 @@ rw_error: static DRXStatus_t CtrlGetCfgPreSaw(pDRXDemodInstance_t demod, pDRXJCfgPreSaw_t preSaw) { - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; /* check arguments */ @@ -15187,7 +15187,7 @@ CtrlGetCfgPreSaw(pDRXDemodInstance_t demod, pDRXJCfgPreSaw_t preSaw) static DRXStatus_t CtrlGetCfgAfeGain(pDRXDemodInstance_t demod, pDRXJCfgAfeGain_t afeGain) { - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; /* check arguments */ @@ -15523,7 +15523,7 @@ rw_error: */ DRXStatus_t DRXJ_Open(pDRXDemodInstance_t demod) { - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; pDRXCommonAttr_t commonAttr = NULL; u32_t driverVersion = 0; @@ -15740,7 +15740,7 @@ rw_error: */ DRXStatus_t DRXJ_Close(pDRXDemodInstance_t demod) { - pI2CDeviceAddr_t devAddr = NULL; + struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; pDRXCommonAttr_t commonAttr = NULL; DRXPowerMode_t powerMode = DRX_POWER_UP; diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.h b/drivers/media/dvb-frontends/drx39xyj/drxj.h index b9e51b4..dbd27da 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.h +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.h @@ -734,7 +734,7 @@ Exported GLOBAL VARIABLES extern DRXAccessFunc_t drxDapDRXJFunct_g; extern DRXDemodFunc_t DRXJFunctions_g; extern DRXJData_t DRXJData_g; - extern I2CDeviceAddr_t DRXJDefaultAddr_g; + extern struct i2c_device_addr DRXJDefaultAddr_g; extern DRXCommonAttr_t DRXJDefaultCommAttr_g; extern DRXDemodInstance_t DRXJDefaultDemod_g; -- cgit v1.1 From bab3fccac9f48da1b979c27ed7d4a331589a64b2 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 20 Mar 2012 00:38:10 -0300 Subject: [media] drx-j: remove the "const" annotate on HICommand() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit After removing the typedef, it is now clear that HICommand() were abusing of a var that was expecting to be constant: drivers/media/dvb-frontends/drx39xyj/drxj.c: In function ‘HICommand’: drivers/media/dvb-frontends/drx39xyj/drxj.c:2272:3: warning: passing argument 1 of ‘drxDapDRXJFunct_g.writeReg16Func’ discards ‘const’ qualifier from pointer target type [enabled by default] drivers/media/dvb-frontends/drx39xyj/drxj.c:2272:3: note: expected ‘struct i2c_device_addr *’ but argument is of type ‘const struct i2c_device_addr *’ drivers/media/dvb-frontends/drx39xyj/drxj.c:2273:3: warning: passing argument 1 of ‘drxDapDRXJFunct_g.writeReg16Func’ discards ‘const’ qualifier from pointer target type [enabled by default] drivers/media/dvb-frontends/drx39xyj/drxj.c:2273:3: note: expected ‘struct i2c_device_addr *’ but argument is of type ‘const struct i2c_device_addr *’ drivers/media/dvb-frontends/drx39xyj/drxj.c:2274:3: warning: passing argument 1 of ‘drxDapDRXJFunct_g.writeReg16Func’ discards ‘const’ qualifier from pointer target type [enabled by default] drivers/media/dvb-frontends/drx39xyj/drxj.c:2274:3: note: expected ‘struct i2c_device_addr *’ but argument is of type ‘const struct i2c_device_addr *’ drivers/media/dvb-frontends/drx39xyj/drxj.c:2275:3: warning: passing argument 1 of ‘drxDapDRXJFunct_g.writeReg16Func’ discards ‘const’ qualifier from pointer target type [enabled by default] drivers/media/dvb-frontends/drx39xyj/drxj.c:2275:3: note: expected ‘struct i2c_device_addr *’ but argument is of type ‘const struct i2c_device_addr *’ drivers/media/dvb-frontends/drx39xyj/drxj.c:2278:3: warning: passing argument 1 of ‘drxDapDRXJFunct_g.writeReg16Func’ discards ‘const’ qualifier from pointer target type [enabled by default] drivers/media/dvb-frontends/drx39xyj/drxj.c:2278:3: note: expected ‘struct i2c_device_addr *’ but argument is of type ‘const struct i2c_device_addr *’ drivers/media/dvb-frontends/drx39xyj/drxj.c:2279:3: warning: passing argument 1 of ‘drxDapDRXJFunct_g.writeReg16Func’ discards ‘const’ qualifier from pointer target type [enabled by default] drivers/media/dvb-frontends/drx39xyj/drxj.c:2279:3: note: expected ‘struct i2c_device_addr *’ but argument is of type ‘const struct i2c_device_addr *’ drivers/media/dvb-frontends/drx39xyj/drxj.c:2291:2: warning: passing argument 1 of ‘drxDapDRXJFunct_g.writeReg16Func’ discards ‘const’ qualifier from pointer target type [enabled by default] drivers/media/dvb-frontends/drx39xyj/drxj.c:2291:2: note: expected ‘struct i2c_device_addr *’ but argument is of type ‘const struct i2c_device_addr *’ drivers/media/dvb-frontends/drx39xyj/drxj.c:2311:4: warning: passing argument 1 of ‘drxDapDRXJFunct_g.readReg16Func’ discards ‘const’ qualifier from pointer target type [enabled by default] drivers/media/dvb-frontends/drx39xyj/drxj.c:2311:4: note: expected ‘struct i2c_device_addr *’ but argument is of type ‘const struct i2c_device_addr *’ drivers/media/dvb-frontends/drx39xyj/drxj.c:2315:3: warning: passing argument 1 of ‘drxDapDRXJFunct_g.readReg16Func’ discards ‘const’ qualifier from pointer target type [enabled by default] drivers/media/dvb-frontends/drx39xyj/drxj.c:2315:3: note: expected ‘struct i2c_device_addr *’ but argument is of type ‘const struct i2c_device_addr *’ Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drxj.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index 84f4e18..a41b2a9 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -1146,7 +1146,7 @@ FUNCTIONS ----------------------------------------------------------------------------*/ /* Some prototypes */ static DRXStatus_t -HICommand(const struct i2c_device_addr *devAddr, +HICommand(struct i2c_device_addr *devAddr, const pDRXJHiCmd_t cmd, pu16_t result); static DRXStatus_t @@ -2258,7 +2258,7 @@ rw_error: * */ static DRXStatus_t -HICommand(const struct i2c_device_addr *devAddr, const pDRXJHiCmd_t cmd, pu16_t result) +HICommand(struct i2c_device_addr *devAddr, const pDRXJHiCmd_t cmd, pu16_t result) { u16_t waitCmd = 0; u16_t nrRetries = 0; -- cgit v1.1 From 43a431e4b2244b25a51b0a5900e894c2a4764ff6 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 20 Mar 2012 00:49:45 -0300 Subject: [media] drx-j: get rid of the integer typedefs Patch created using this small script: for j in 8 16 32; do for i in *; do sed s,pu${j}_t,"u$j *",g <$i >a && mv a $i; done; done for j in 8 16 32; do for i in *; do sed s,ps${j}_t,"s$j *",g <$i >a && mv a $i; done; done for j in 8 16 32; do for i in *; do sed s,s${j}_t,"s$j",g <$i >a && mv a $i; done; done for j in 8 16 32; do for i in *; do sed s,u${j}_t,"u$j",g <$i >a && mv a $i; done; done and fixing the bsp_types.h header. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/bsp_host.h | 8 +- drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h | 16 +- drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h | 24 +- drivers/media/dvb-frontends/drx39xyj/bsp_types.h | 98 +- .../media/dvb-frontends/drx39xyj/drx39xxj_dummy.c | 14 +- .../media/dvb-frontends/drx39xyj/drx_dap_fasi.c | 164 +- drivers/media/dvb-frontends/drx39xyj/drx_driver.c | 164 +- drivers/media/dvb-frontends/drx39xyj/drx_driver.h | 194 +-- drivers/media/dvb-frontends/drx39xyj/drxj.c | 1616 ++++++++++---------- drivers/media/dvb-frontends/drx39xyj/drxj.h | 142 +- drivers/media/dvb-frontends/drx39xyj/drxj_mc.h | 4 +- drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsb.h | 4 +- .../media/dvb-frontends/drx39xyj/drxj_mc_vsbqam.h | 4 +- 13 files changed, 1182 insertions(+), 1270 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/bsp_host.h b/drivers/media/dvb-frontends/drx39xyj/bsp_host.h index 5a2dd5f..0ce94df 100644 --- a/drivers/media/dvb-frontends/drx39xyj/bsp_host.h +++ b/drivers/media/dvb-frontends/drx39xyj/bsp_host.h @@ -61,13 +61,13 @@ Exported FUNCTIONS DRXStatus_t DRXBSP_HST_Term(void); - void *DRXBSP_HST_Memcpy(void *to, void *from, u32_t n); + void *DRXBSP_HST_Memcpy(void *to, void *from, u32 n); - int DRXBSP_HST_Memcmp(void *s1, void *s2, u32_t n); + int DRXBSP_HST_Memcmp(void *s1, void *s2, u32 n); - u32_t DRXBSP_HST_Clock(void); + u32 DRXBSP_HST_Clock(void); - DRXStatus_t DRXBSP_HST_Sleep(u32_t n); + DRXStatus_t DRXBSP_HST_Sleep(u32 n); /*------------------------------------------------------------------------- THE END diff --git a/drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h b/drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h index ec2467b..64ebef3 100644 --- a/drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h +++ b/drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h @@ -42,8 +42,6 @@ * */ -#include - #ifndef __BSPI2C_H__ #define __BSPI2C_H__ @@ -95,11 +93,11 @@ Exported FUNCTIONS /** * \fn DRXStatus_t DRXBSP_I2C_WriteRead( struct i2c_device_addr *wDevAddr, -* u16_t wCount, -* pu8_t wData, +* u16 wCount, +* u8 *wData, * struct i2c_device_addr *rDevAddr, -* u16_t rCount, -* pu8_t rData) +* u16 rCount, +* u8 *rData) * \brief Read and/or write count bytes from I2C bus, store them in data[]. * \param wDevAddr The device i2c address and the device ID to write to * \param wCount The number of bytes to write @@ -124,10 +122,10 @@ Exported FUNCTIONS * It can be used to control a "switch" on the I2C bus to the correct device. */ DRXStatus_t DRXBSP_I2C_WriteRead(struct i2c_device_addr *wDevAddr, - u16_t wCount, - pu8_t wData, + u16 wCount, + u8 *wData, struct i2c_device_addr *rDevAddr, - u16_t rCount, pu8_t rData); + u16 rCount, u8 *rData); /** * \fn DRXBSP_I2C_ErrorText() diff --git a/drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h b/drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h index 1491358..12676de 100644 --- a/drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h +++ b/drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h @@ -79,8 +79,8 @@ DEFINES TYPEDEFS ------------------------------------------------------------------------------*/ - typedef u32_t TUNERMode_t; - typedef pu32_t pTUNERMode_t; + typedef u32 TUNERMode_t; + typedef u32 *pTUNERMode_t; typedef char *TUNERSubMode_t; /* description of submode */ typedef TUNERSubMode_t *pTUNERSubMode_t; @@ -97,9 +97,9 @@ TYPEDEFS DRXFrequency_t minFreqRF; /* Lowest RF input frequency, in kHz */ DRXFrequency_t maxFreqRF; /* Highest RF input frequency, in kHz */ - u8_t subMode; /* Index to sub-mode in use */ + u8 subMode; /* Index to sub-mode in use */ pTUNERSubMode_t subModeDescriptions; /* Pointer to description of sub-modes */ - u8_t subModes; /* Number of available sub-modes */ + u8 subModes; /* Number of available sub-modes */ /* The following fields will be either 0, NULL or FALSE and do not need initialisation */ @@ -109,7 +109,7 @@ TYPEDEFS DRXFrequency_t IFfrequency; /* only valid if programmed */ void *myUserData; /* pointer to associated demod instance */ - u16_t myCapabilities; /* value for storing application flags */ + u16 myCapabilities; /* value for storing application flags */ } TUNERCommonAttr_t, *pTUNERCommonAttr_t; @@ -139,11 +139,11 @@ TYPEDEFS typedef DRXStatus_t(*TUNERi2cWriteReadFunc_t) (pTUNERInstance_t tuner, struct i2c_device_addr * - wDevAddr, u16_t wCount, - pu8_t wData, + wDevAddr, u16 wCount, + u8 *wData, struct i2c_device_addr * - rDevAddr, u16_t rCount, - pu8_t rData); + rDevAddr, u16 rCount, + u8 *rData); typedef struct { TUNEROpenFunc_t openFunc; @@ -194,10 +194,10 @@ Exported FUNCTIONS DRXStatus_t DRXBSP_TUNER_DefaultI2CWriteRead(pTUNERInstance_t tuner, struct i2c_device_addr *wDevAddr, - u16_t wCount, - pu8_t wData, + u16 wCount, + u8 *wData, struct i2c_device_addr *rDevAddr, - u16_t rCount, pu8_t rData); + u16 rCount, u8 *rData); /*------------------------------------------------------------------------------ THE END diff --git a/drivers/media/dvb-frontends/drx39xyj/bsp_types.h b/drivers/media/dvb-frontends/drx39xyj/bsp_types.h index e10a79b..2f5a2ba9 100644 --- a/drivers/media/dvb-frontends/drx39xyj/bsp_types.h +++ b/drivers/media/dvb-frontends/drx39xyj/bsp_types.h @@ -39,6 +39,8 @@ * */ +#include + #ifndef __BSP_TYPES_H__ #define __BSP_TYPES_H__ /*------------------------------------------------------------------------- @@ -53,98 +55,10 @@ TYPEDEFS -------------------------------------------------------------------------*/ /** -* \typedef unsigned char u8_t -* \brief type definition of an unsigned 8 bits integer -*/ - typedef unsigned char u8_t; -/** -* \typedef char s8_t -* \brief type definition of a signed 8 bits integer -*/ - typedef char s8_t; -/** -* \typedef unsigned short u16_t *pu16_t -* \brief type definition of an unsigned 16 bits integer -*/ - typedef unsigned short u16_t; -/** -* \typedef short s16_t -* \brief type definition of a signed 16 bits integer -*/ - typedef short s16_t; -/** -* \typedef unsigned long u32_t -* \brief type definition of an unsigned 32 bits integer -*/ - typedef unsigned long u32_t; -/** -* \typedef long s32_t -* \brief type definition of a signed 32 bits integer -*/ - typedef long s32_t; -/* -* \typedef struct ... u64_t -* \brief type definition of an usigned 64 bits integer -*/ - typedef struct { - u32_t MSLW; - u32_t LSLW; - } u64_t; -/* -* \typedef struct ... i64_t -* \brief type definition of a signed 64 bits integer -*/ - typedef struct { - s32_t MSLW; - u32_t LSLW; - } s64_t; - -/** -* \typedef u8_t *pu8_t -* \brief type definition of pointer to an unsigned 8 bits integer -*/ - typedef u8_t *pu8_t; -/** -* \typedef s8_t *ps8_t -* \brief type definition of pointer to a signed 8 bits integer -*/ - typedef s8_t *ps8_t; -/** -* \typedef u16_t *pu16_t -* \brief type definition of pointer to an unsigned 16 bits integer -*/ - typedef u16_t *pu16_t; -/** -* \typedef s16_t *ps16_t -* \brief type definition of pointer to a signed 16 bits integer -*/ - typedef s16_t *ps16_t; -/** -* \typedef u32_t *pu32_t -* \brief type definition of pointer to an unsigned 32 bits integer -*/ - typedef u32_t *pu32_t; -/** -* \typedef s32_t *ps32_t -* \brief type definition of pointer to a signed 32 bits integer -*/ - typedef s32_t *ps32_t; -/** -* \typedef u64_t *pu64_t -* \brief type definition of pointer to an usigned 64 bits integer -*/ - typedef u64_t *pu64_t; -/** -* \typedef s64_t *ps64_t -* \brief type definition of pointer to a signed 64 bits integer -*/ - typedef s64_t *ps64_t; - -/** -* \typedef s32_t DRXFrequency_t +* \typedef s32 DRXFrequency_t * \brief type definition of frequency */ - typedef s32_t DRXFrequency_t; + typedef s32 DRXFrequency_t; /** * \typedef DRXFrequency_t *pDRXFrequency_t @@ -153,10 +67,10 @@ TYPEDEFS typedef DRXFrequency_t *pDRXFrequency_t; /** -* \typedef u32_t DRXSymbolrate_t +* \typedef u32 DRXSymbolrate_t * \brief type definition of symbol rate */ - typedef u32_t DRXSymbolrate_t; + typedef u32 DRXSymbolrate_t; /** * \typedef DRXSymbolrate_t *pDRXSymbolrate_t diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c b/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c index 73fa63a..35cef0f 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c @@ -39,32 +39,32 @@ DRXBSP_TUNER_GetFrequency(pTUNERInstance_t tuner, return DRX_STS_OK; } -DRXStatus_t DRXBSP_HST_Sleep(u32_t n) +DRXStatus_t DRXBSP_HST_Sleep(u32 n) { msleep(n); return DRX_STS_OK; } -u32_t DRXBSP_HST_Clock(void) +u32 DRXBSP_HST_Clock(void) { return jiffies_to_msecs(jiffies); } -int DRXBSP_HST_Memcmp(void *s1, void *s2, u32_t n) +int DRXBSP_HST_Memcmp(void *s1, void *s2, u32 n) { return (memcmp(s1, s2, (size_t) n)); } -void *DRXBSP_HST_Memcpy(void *to, void *from, u32_t n) +void *DRXBSP_HST_Memcpy(void *to, void *from, u32 n) { return (memcpy(to, from, (size_t) n)); } DRXStatus_t DRXBSP_I2C_WriteRead(struct i2c_device_addr *wDevAddr, - u16_t wCount, - pu8_t wData, + u16 wCount, + u8 *wData, struct i2c_device_addr *rDevAddr, - u16_t rCount, pu8_t rData) + u16 rCount, u8 *rData) { struct drx39xxj_state *state; struct i2c_msg msg[2]; diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c index 472581e..5bf4771 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c @@ -57,63 +57,63 @@ /* Function prototypes */ static DRXStatus_t DRXDAP_FASI_WriteBlock(struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register/memory */ - u16_t datasize, /* size of data */ - pu8_t data, /* data to send */ + u16 datasize, /* size of data */ + u8 *data, /* data to send */ DRXflags_t flags); /* special device flags */ static DRXStatus_t DRXDAP_FASI_ReadBlock(struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register/memory */ - u16_t datasize, /* size of data */ - pu8_t data, /* data to send */ + u16 datasize, /* size of data */ + u8 *data, /* data to send */ DRXflags_t flags); /* special device flags */ static DRXStatus_t DRXDAP_FASI_WriteReg8(struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register */ - u8_t data, /* data to write */ + u8 data, /* data to write */ DRXflags_t flags); /* special device flags */ static DRXStatus_t DRXDAP_FASI_ReadReg8(struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register */ - pu8_t data, /* buffer to receive data */ + u8 *data, /* buffer to receive data */ DRXflags_t flags); /* special device flags */ static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg8(struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t waddr, /* address of register */ DRXaddr_t raddr, /* address to read back from */ - u8_t datain, /* data to send */ - pu8_t dataout); /* data to receive back */ + u8 datain, /* data to send */ + u8 *dataout); /* data to receive back */ static DRXStatus_t DRXDAP_FASI_WriteReg16(struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register */ - u16_t data, /* data to write */ + u16 data, /* data to write */ DRXflags_t flags); /* special device flags */ static DRXStatus_t DRXDAP_FASI_ReadReg16(struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register */ - pu16_t data, /* buffer to receive data */ + u16 *data, /* buffer to receive data */ DRXflags_t flags); /* special device flags */ static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg16(struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t waddr, /* address of register */ DRXaddr_t raddr, /* address to read back from */ - u16_t datain, /* data to send */ - pu16_t dataout); /* data to receive back */ + u16 datain, /* data to send */ + u16 *dataout); /* data to receive back */ static DRXStatus_t DRXDAP_FASI_WriteReg32(struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register */ - u32_t data, /* data to write */ + u32 data, /* data to write */ DRXflags_t flags); /* special device flags */ static DRXStatus_t DRXDAP_FASI_ReadReg32(struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register */ - pu32_t data, /* buffer to receive data */ + u32 *data, /* buffer to receive data */ DRXflags_t flags); /* special device flags */ static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg32(struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t waddr, /* address of register */ DRXaddr_t raddr, /* address to read back from */ - u32_t datain, /* data to send */ - pu32_t dataout); /* data to receive back */ + u32 datain, /* data to send */ + u32 *dataout); /* data to receive back */ /* The version structure of this protocol implementation */ char drxDapFASIModuleName[] = "FASI Data Access Protocol"; @@ -151,7 +151,7 @@ DRXAccessFunc_t drxDapFASIFunct_g = { static DRXStatus_t DRXDAP_FASI_WriteReg8(struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register */ - u8_t data, /* data to write */ + u8 data, /* data to write */ DRXflags_t flags) { /* special device flags */ return DRX_STS_ERROR; @@ -159,7 +159,7 @@ static DRXStatus_t DRXDAP_FASI_WriteReg8(struct i2c_device_addr *devAddr, /* add static DRXStatus_t DRXDAP_FASI_ReadReg8(struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register */ - pu8_t data, /* buffer to receive data */ + u8 *data, /* buffer to receive data */ DRXflags_t flags) { /* special device flags */ return DRX_STS_ERROR; @@ -168,8 +168,8 @@ static DRXStatus_t DRXDAP_FASI_ReadReg8(struct i2c_device_addr *devAddr, /* addr static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg8(struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t waddr, /* address of register */ DRXaddr_t raddr, /* address to read back from */ - u8_t datain, /* data to send */ - pu8_t dataout) + u8 datain, /* data to send */ + u8 *dataout) { /* data to receive back */ return DRX_STS_ERROR; } @@ -177,8 +177,8 @@ static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg8(struct i2c_device_addr *devAd static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg32(struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t waddr, /* address of register */ DRXaddr_t raddr, /* address to read back from */ - u32_t datain, /* data to send */ - pu32_t dataout) + u32 datain, /* data to send */ + u32 *dataout) { /* data to receive back */ return DRX_STS_ERROR; } @@ -190,8 +190,8 @@ static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg32(struct i2c_device_addr *devA * DRXStatus_t DRXDAP_FASI_ReadBlock ( * struct i2c_device_addr *devAddr, -- address of I2C device * DRXaddr_t addr, -- address of chip register/memory -* u16_t datasize, -- number of bytes to read -* pu8_t data, -- data to receive +* u16 datasize, -- number of bytes to read +* u8 *data, -- data to receive * DRXflags_t flags) -- special device flags * * Read block data from chip address. Because the chip is word oriented, @@ -212,13 +212,13 @@ static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg32(struct i2c_device_addr *devA static DRXStatus_t DRXDAP_FASI_ReadBlock(struct i2c_device_addr *devAddr, DRXaddr_t addr, - u16_t datasize, - pu8_t data, DRXflags_t flags) + u16 datasize, + u8 *data, DRXflags_t flags) { - u8_t buf[4]; - u16_t bufx; + u8 buf[4]; + u16 bufx; DRXStatus_t rc; - u16_t overheadSize = 0; + u16 overheadSize = 0; /* Check parameters ******************************************************* */ if (devAddr == NULL) { @@ -244,7 +244,7 @@ static DRXStatus_t DRXDAP_FASI_ReadBlock(struct i2c_device_addr *devAddr, /* Read block from I2C **************************************************** */ do { - u16_t todo = (datasize < DRXDAP_MAX_RCHUNKSIZE ? + u16 todo = (datasize < DRXDAP_MAX_RCHUNKSIZE ? datasize : DRXDAP_MAX_RCHUNKSIZE); bufx = 0; @@ -258,19 +258,19 @@ static DRXStatus_t DRXDAP_FASI_ReadBlock(struct i2c_device_addr *devAddr, if (DRXDAP_FASI_LONG_FORMAT(addr)) { #endif #if ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 ) - buf[bufx++] = (u8_t) (((addr << 1) & 0xFF) | 0x01); - buf[bufx++] = (u8_t) ((addr >> 16) & 0xFF); - buf[bufx++] = (u8_t) ((addr >> 24) & 0xFF); - buf[bufx++] = (u8_t) ((addr >> 7) & 0xFF); + buf[bufx++] = (u8) (((addr << 1) & 0xFF) | 0x01); + buf[bufx++] = (u8) ((addr >> 16) & 0xFF); + buf[bufx++] = (u8) ((addr >> 24) & 0xFF); + buf[bufx++] = (u8) ((addr >> 7) & 0xFF); #endif #if ( ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 ) && \ ( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 ) ) } else { #endif #if ( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 ) - buf[bufx++] = (u8_t) ((addr << 1) & 0xFF); + buf[bufx++] = (u8) ((addr << 1) & 0xFF); buf[bufx++] = - (u8_t) (((addr >> 16) & 0x0F) | + (u8) (((addr >> 16) & 0x0F) | ((addr >> 18) & 0xF0)); #endif #if ( ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 ) && \ @@ -306,8 +306,8 @@ static DRXStatus_t DRXDAP_FASI_ReadBlock(struct i2c_device_addr *devAddr, * struct i2c_device_addr *devAddr, -- address of I2C device * DRXaddr_t waddr, -- address of chip register/memory * DRXaddr_t raddr, -- chip address to read back from -* u16_t wdata, -- data to send -* pu16_t rdata) -- data to receive back +* u16 wdata, -- data to send +* u16 *rdata) -- data to receive back * * Write 16-bit data, then read back the original contents of that location. * Requires long addressing format to be allowed. @@ -328,7 +328,7 @@ static DRXStatus_t DRXDAP_FASI_ReadBlock(struct i2c_device_addr *devAddr, static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg16(struct i2c_device_addr *devAddr, DRXaddr_t waddr, DRXaddr_t raddr, - u16_t wdata, pu16_t rdata) + u16 wdata, u16 *rdata) { DRXStatus_t rc = DRX_STS_ERROR; @@ -351,7 +351,7 @@ static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg16(struct i2c_device_addr *devA * DRXStatus_t DRXDAP_FASI_ReadReg16 ( * struct i2c_device_addr *devAddr, -- address of I2C device * DRXaddr_t addr, -- address of chip register/memory -* pu16_t data, -- data to receive +* u16 *data, -- data to receive * DRXflags_t flags) -- special device flags * * Read one 16-bit register or memory location. The data received back is @@ -366,16 +366,16 @@ static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg16(struct i2c_device_addr *devA static DRXStatus_t DRXDAP_FASI_ReadReg16(struct i2c_device_addr *devAddr, DRXaddr_t addr, - pu16_t data, DRXflags_t flags) + u16 *data, DRXflags_t flags) { - u8_t buf[sizeof(*data)]; + u8 buf[sizeof(*data)]; DRXStatus_t rc; if (!data) { return DRX_STS_INVALID_ARG; } rc = DRXDAP_FASI_ReadBlock(devAddr, addr, sizeof(*data), buf, flags); - *data = buf[0] + (((u16_t) buf[1]) << 8); + *data = buf[0] + (((u16) buf[1]) << 8); return rc; } @@ -384,7 +384,7 @@ static DRXStatus_t DRXDAP_FASI_ReadReg16(struct i2c_device_addr *devAddr, * DRXStatus_t DRXDAP_FASI_ReadReg32 ( * struct i2c_device_addr *devAddr, -- address of I2C device * DRXaddr_t addr, -- address of chip register/memory -* pu32_t data, -- data to receive +* u32 *data, -- data to receive * DRXflags_t flags) -- special device flags * * Read one 32-bit register or memory location. The data received back is @@ -399,18 +399,18 @@ static DRXStatus_t DRXDAP_FASI_ReadReg16(struct i2c_device_addr *devAddr, static DRXStatus_t DRXDAP_FASI_ReadReg32(struct i2c_device_addr *devAddr, DRXaddr_t addr, - pu32_t data, DRXflags_t flags) + u32 *data, DRXflags_t flags) { - u8_t buf[sizeof(*data)]; + u8 buf[sizeof(*data)]; DRXStatus_t rc; if (!data) { return DRX_STS_INVALID_ARG; } rc = DRXDAP_FASI_ReadBlock(devAddr, addr, sizeof(*data), buf, flags); - *data = (((u32_t) buf[0]) << 0) + - (((u32_t) buf[1]) << 8) + - (((u32_t) buf[2]) << 16) + (((u32_t) buf[3]) << 24); + *data = (((u32) buf[0]) << 0) + + (((u32) buf[1]) << 8) + + (((u32) buf[2]) << 16) + (((u32) buf[3]) << 24); return rc; } @@ -419,8 +419,8 @@ static DRXStatus_t DRXDAP_FASI_ReadReg32(struct i2c_device_addr *devAddr, * DRXStatus_t DRXDAP_FASI_WriteBlock ( * struct i2c_device_addr *devAddr, -- address of I2C device * DRXaddr_t addr, -- address of chip register/memory -* u16_t datasize, -- number of bytes to read -* pu8_t data, -- data to receive +* u16 datasize, -- number of bytes to read +* u8 *data, -- data to receive * DRXflags_t flags) -- special device flags * * Write block data to chip address. Because the chip is word oriented, @@ -438,14 +438,14 @@ static DRXStatus_t DRXDAP_FASI_ReadReg32(struct i2c_device_addr *devAddr, static DRXStatus_t DRXDAP_FASI_WriteBlock(struct i2c_device_addr *devAddr, DRXaddr_t addr, - u16_t datasize, - pu8_t data, DRXflags_t flags) + u16 datasize, + u8 *data, DRXflags_t flags) { - u8_t buf[DRXDAP_MAX_WCHUNKSIZE]; + u8 buf[DRXDAP_MAX_WCHUNKSIZE]; DRXStatus_t st = DRX_STS_ERROR; DRXStatus_t firstErr = DRX_STS_OK; - u16_t overheadSize = 0; - u16_t blockSize = 0; + u16 overheadSize = 0; + u16 blockSize = 0; /* Check parameters ******************************************************* */ if (devAddr == NULL) { @@ -472,8 +472,8 @@ static DRXStatus_t DRXDAP_FASI_WriteBlock(struct i2c_device_addr *devAddr, /* Write block to I2C ***************************************************** */ blockSize = ((DRXDAP_MAX_WCHUNKSIZE) - overheadSize) & ~1; do { - u16_t todo = 0; - u16_t bufx = 0; + u16 todo = 0; + u16 bufx = 0; /* Buffer device address */ addr &= ~DRXDAP_FASI_FLAGS; @@ -484,19 +484,19 @@ static DRXStatus_t DRXDAP_FASI_WriteBlock(struct i2c_device_addr *devAddr, if (DRXDAP_FASI_LONG_FORMAT(addr)) { #endif #if ( (DRXDAPFASI_LONG_ADDR_ALLOWED)==1 ) - buf[bufx++] = (u8_t) (((addr << 1) & 0xFF) | 0x01); - buf[bufx++] = (u8_t) ((addr >> 16) & 0xFF); - buf[bufx++] = (u8_t) ((addr >> 24) & 0xFF); - buf[bufx++] = (u8_t) ((addr >> 7) & 0xFF); + buf[bufx++] = (u8) (((addr << 1) & 0xFF) | 0x01); + buf[bufx++] = (u8) ((addr >> 16) & 0xFF); + buf[bufx++] = (u8) ((addr >> 24) & 0xFF); + buf[bufx++] = (u8) ((addr >> 7) & 0xFF); #endif #if ( ( (DRXDAPFASI_LONG_ADDR_ALLOWED)==1 ) && \ ( (DRXDAPFASI_SHORT_ADDR_ALLOWED)==1 ) ) } else { #endif #if ( (DRXDAPFASI_SHORT_ADDR_ALLOWED)==1 ) - buf[bufx++] = (u8_t) ((addr << 1) & 0xFF); + buf[bufx++] = (u8) ((addr << 1) & 0xFF); buf[bufx++] = - (u8_t) (((addr >> 16) & 0x0F) | + (u8) (((addr >> 16) & 0x0F) | ((addr >> 18) & 0xF0)); #endif #if ( ( (DRXDAPFASI_LONG_ADDR_ALLOWED)==1 ) && \ @@ -514,8 +514,8 @@ static DRXStatus_t DRXDAP_FASI_WriteBlock(struct i2c_device_addr *devAddr, */ todo = (blockSize < datasize ? blockSize : datasize); if (todo == 0) { - u16_t overheadSizeI2cAddr = 0; - u16_t dataBlockSize = 0; + u16 overheadSizeI2cAddr = 0; + u16 dataBlockSize = 0; overheadSizeI2cAddr = (IS_I2C_10BIT(devAddr->i2cAddr) ? 2 : 1); @@ -524,10 +524,10 @@ static DRXStatus_t DRXDAP_FASI_WriteBlock(struct i2c_device_addr *devAddr, /* write device address */ st = DRXBSP_I2C_WriteRead(devAddr, - (u16_t) (bufx), + (u16) (bufx), buf, (struct i2c_device_addr *) (NULL), - 0, (pu8_t) (NULL)); + 0, (u8 *) (NULL)); if ((st != DRX_STS_OK) && (firstErr == DRX_STS_OK)) { /* at the end, return the first error encountered */ @@ -541,10 +541,10 @@ static DRXStatus_t DRXDAP_FASI_WriteBlock(struct i2c_device_addr *devAddr, DRXBSP_HST_Memcpy(&buf[bufx], data, todo); /* write (address if can do and) data */ st = DRXBSP_I2C_WriteRead(devAddr, - (u16_t) (bufx + todo), + (u16) (bufx + todo), buf, (struct i2c_device_addr *) (NULL), - 0, (pu8_t) (NULL)); + 0, (u8 *) (NULL)); if ((st != DRX_STS_OK) && (firstErr == DRX_STS_OK)) { /* at the end, return the first error encountered */ @@ -563,7 +563,7 @@ static DRXStatus_t DRXDAP_FASI_WriteBlock(struct i2c_device_addr *devAddr, * DRXStatus_t DRXDAP_FASI_WriteReg16 ( * struct i2c_device_addr *devAddr, -- address of I2C device * DRXaddr_t addr, -- address of chip register/memory -* u16_t data, -- data to send +* u16 data, -- data to send * DRXflags_t flags) -- special device flags * * Write one 16-bit register or memory location. The data being written is @@ -577,12 +577,12 @@ static DRXStatus_t DRXDAP_FASI_WriteBlock(struct i2c_device_addr *devAddr, static DRXStatus_t DRXDAP_FASI_WriteReg16(struct i2c_device_addr *devAddr, DRXaddr_t addr, - u16_t data, DRXflags_t flags) + u16 data, DRXflags_t flags) { - u8_t buf[sizeof(data)]; + u8 buf[sizeof(data)]; - buf[0] = (u8_t) ((data >> 0) & 0xFF); - buf[1] = (u8_t) ((data >> 8) & 0xFF); + buf[0] = (u8) ((data >> 0) & 0xFF); + buf[1] = (u8) ((data >> 8) & 0xFF); return DRXDAP_FASI_WriteBlock(devAddr, addr, sizeof(data), buf, flags); } @@ -592,7 +592,7 @@ static DRXStatus_t DRXDAP_FASI_WriteReg16(struct i2c_device_addr *devAddr, * DRXStatus_t DRXDAP_FASI_WriteReg32 ( * struct i2c_device_addr *devAddr, -- address of I2C device * DRXaddr_t addr, -- address of chip register/memory -* u32_t data, -- data to send +* u32 data, -- data to send * DRXflags_t flags) -- special device flags * * Write one 32-bit register or memory location. The data being written is @@ -606,14 +606,14 @@ static DRXStatus_t DRXDAP_FASI_WriteReg16(struct i2c_device_addr *devAddr, static DRXStatus_t DRXDAP_FASI_WriteReg32(struct i2c_device_addr *devAddr, DRXaddr_t addr, - u32_t data, DRXflags_t flags) + u32 data, DRXflags_t flags) { - u8_t buf[sizeof(data)]; + u8 buf[sizeof(data)]; - buf[0] = (u8_t) ((data >> 0) & 0xFF); - buf[1] = (u8_t) ((data >> 8) & 0xFF); - buf[2] = (u8_t) ((data >> 16) & 0xFF); - buf[3] = (u8_t) ((data >> 24) & 0xFF); + buf[0] = (u8) ((data >> 0) & 0xFF); + buf[1] = (u8) ((data >> 8) & 0xFF); + buf[2] = (u8) ((data >> 16) & 0xFF); + buf[3] = (u8) ((data >> 24) & 0xFF); return DRXDAP_FASI_WriteBlock(devAddr, addr, sizeof(data), buf, flags); } diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c index 3a782d6..ea43f14 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c @@ -60,7 +60,7 @@ DEFINES /** \brief Magic word for checking correct Endianess of microcode data. */ #ifndef DRX_UCODE_MAGIC_WORD -#define DRX_UCODE_MAGIC_WORD ((((u16_t)'H')<<8)+((u16_t)'L')) +#define DRX_UCODE_MAGIC_WORD ((((u16)'H')<<8)+((u16)'L')) #endif /** \brief CRC flag in ucode header, flags field. */ @@ -119,17 +119,17 @@ STRUCTURES ------------------------------------------------------------------------------*/ /** \brief Structure of the microcode block headers */ typedef struct { - u32_t addr; + u32 addr; /**< Destination address of the data in this block */ - u16_t size; + u16 size; /**< Size of the block data following this header counted in 16 bits words */ - u16_t flags; + u16 flags; /**< Flags for this data block: - bit[0]= CRC on/off - bit[1]= compression on/off - bit[15..2]=reserved */ - u16_t CRC;/**< CRC value of the data block, only valid if CRC flag is + u16 CRC;/**< CRC value of the data block, only valid if CRC flag is set. */ } DRXUCodeBlockHdr_t, *pDRXUCodeBlockHdr_t; @@ -217,13 +217,13 @@ static DRXStatus_t ScanWaitForLock(pDRXDemodInstance_t demod, pBool_t isLocked) Bool_t doneWaiting = FALSE; DRXLockStatus_t lockState = DRX_NOT_LOCKED; DRXLockStatus_t desiredLockState = DRX_NOT_LOCKED; - u32_t timeoutValue = 0; - u32_t startTimeLockStage = 0; - u32_t currentTime = 0; - u32_t timerValue = 0; + u32 timeoutValue = 0; + u32 startTimeLockStage = 0; + u32 currentTime = 0; + u32 timerValue = 0; *isLocked = FALSE; - timeoutValue = (u32_t) demod->myCommonAttr->scanDemodLockTimeout; + timeoutValue = (u32) demod->myCommonAttr->scanDemodLockTimeout; desiredLockState = demod->myCommonAttr->scanDesiredLock; startTimeLockStage = DRXBSP_HST_Clock(); @@ -277,8 +277,8 @@ static DRXStatus_t ScanPrepareNextScan(pDRXDemodInstance_t demod, DRXFrequency_t skip) { pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); - u16_t tableIndex = 0; - u16_t frequencyPlanSize = 0; + u16 tableIndex = 0; + u16 frequencyPlanSize = 0; pDRXFrequencyPlan_t frequencyPlan = (pDRXFrequencyPlan_t) (NULL); DRXFrequency_t nextFrequency = 0; DRXFrequency_t tunerMinFrequency = 0; @@ -419,8 +419,8 @@ CtrlScanInit(pDRXDemodInstance_t demod, pDRXScanParam_t scanParam) pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); DRXFrequency_t maxTunerFreq = 0; DRXFrequency_t minTunerFreq = 0; - u16_t nrChannelsInPlan = 0; - u16_t i = 0; + u16 nrChannelsInPlan = 0; + u16 i = 0; void *scanContext = NULL; commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; @@ -509,7 +509,7 @@ CtrlScanInit(pDRXDemodInstance_t demod, pDRXScanParam_t scanParam) in this frequency plan. */ if ((minFreq != 0) && (maxFreq != 0)) { nrChannelsInPlan += - (u16_t) (((maxFreq - minFreq) / step) + 1); + (u16) (((maxFreq - minFreq) / step) + 1); /* Determine first frequency (within tuner range) to scan */ if (commonAttr->scanNextFrequency == 0) { @@ -602,13 +602,13 @@ static DRXStatus_t CtrlScanStop(pDRXDemodInstance_t demod) * Progress indication will run from 0 upto DRX_SCAN_MAX_PROGRESS during scan. * */ -static DRXStatus_t CtrlScanNext(pDRXDemodInstance_t demod, pu16_t scanProgress) +static DRXStatus_t CtrlScanNext(pDRXDemodInstance_t demod, u16 *scanProgress) { pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); pBool_t scanReady = (pBool_t) (NULL); - u16_t maxProgress = DRX_SCAN_MAX_PROGRESS; - u32_t numTries = 0; - u32_t i = 0; + u16 maxProgress = DRX_SCAN_MAX_PROGRESS; + u32 numTries = 0; + u32 i = 0; commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; @@ -627,8 +627,8 @@ static DRXStatus_t CtrlScanNext(pDRXDemodInstance_t demod, pu16_t scanProgress) return DRX_STS_ERROR; } - *scanProgress = (u16_t) (((commonAttr->scanChannelsScanned) * - ((u32_t) (maxProgress))) / + *scanProgress = (u16) (((commonAttr->scanChannelsScanned) * + ((u32) (maxProgress))) / (commonAttr->scanMaxChannels)); /* Scan */ @@ -683,8 +683,8 @@ static DRXStatus_t CtrlScanNext(pDRXDemodInstance_t demod, pu16_t scanProgress) /* keep track of progress */ *scanProgress = - (u16_t) (((commonAttr->scanChannelsScanned) * - ((u32_t) (maxProgress))) / + (u16) (((commonAttr->scanChannelsScanned) * + ((u32) (maxProgress))) / (commonAttr->scanMaxChannels)); if (nextStatus != DRX_STS_OK) { @@ -843,7 +843,7 @@ CtrlProgramTuner(pDRXDemodInstance_t demod, pDRXChannel_t channel) DRXStatus_t CtrlDumpRegisters(pDRXDemodInstance_t demod, pDRXRegDump_t registers) { - u16_t i = 0; + u16 i = 0; if (registers == NULL) { /* registers not supplied */ @@ -853,20 +853,20 @@ DRXStatus_t CtrlDumpRegisters(pDRXDemodInstance_t demod, /* start dumping registers */ while (registers[i].address != 0) { DRXStatus_t status = DRX_STS_ERROR; - u16_t value = 0; - u32_t data = 0; + u16 value = 0; + u32 data = 0; status = demod->myAccessFunct->readReg16Func(demod->myI2CDevAddr, registers[i].address, &value, 0); - data = (u32_t) value; + data = (u32) value; if (status != DRX_STS_OK) { /* no breakouts; depending on device ID, some HW blocks might not be available */ - data |= ((u32_t) status) << 16; + data |= ((u32) status) << 16; } registers[i].data = data; i++; @@ -885,21 +885,21 @@ DRXStatus_t CtrlDumpRegisters(pDRXDemodInstance_t demod, /** * \brief Read a 16 bits word, expects big endian data. * \param addr: Pointer to memory from which to read the 16 bits word. -* \return u16_t The data read. +* \return u16 The data read. * * This function takes care of the possible difference in endianness between the * host and the data contained in the microcode image file. * */ -static u16_t UCodeRead16(pu8_t addr) +static u16 UCodeRead16(u8 *addr) { /* Works fo any host processor */ - u16_t word = 0; + u16 word = 0; - word = ((u16_t) addr[0]); + word = ((u16) addr[0]); word <<= 8; - word |= ((u16_t) addr[1]); + word |= ((u16) addr[1]); return word; } @@ -909,25 +909,25 @@ static u16_t UCodeRead16(pu8_t addr) /** * \brief Read a 32 bits word, expects big endian data. * \param addr: Pointer to memory from which to read the 32 bits word. -* \return u32_t The data read. +* \return u32 The data read. * * This function takes care of the possible difference in endianness between the * host and the data contained in the microcode image file. * */ -static u32_t UCodeRead32(pu8_t addr) +static u32 UCodeRead32(u8 *addr) { /* Works fo any host processor */ - u32_t word = 0; + u32 word = 0; - word = ((u16_t) addr[0]); + word = ((u16) addr[0]); word <<= 8; - word |= ((u16_t) addr[1]); + word |= ((u16) addr[1]); word <<= 8; - word |= ((u16_t) addr[2]); + word |= ((u16) addr[2]); word <<= 8; - word |= ((u16_t) addr[3]); + word |= ((u16) addr[3]); return word; } @@ -938,17 +938,17 @@ static u32_t UCodeRead32(pu8_t addr) * \brief Compute CRC of block of microcode data. * \param blockData: Pointer to microcode data. * \param nrWords: Size of microcode block (number of 16 bits words). -* \return u16_t The computed CRC residu. +* \return u16 The computed CRC residu. */ -static u16_t UCodeComputeCRC(pu8_t blockData, u16_t nrWords) +static u16 UCodeComputeCRC(u8 *blockData, u16 nrWords) { - u16_t i = 0; - u16_t j = 0; - u32_t CRCWord = 0; - u32_t carry = 0; + u16 i = 0; + u16 j = 0; + u32 CRCWord = 0; + u32 carry = 0; while (i < nrWords) { - CRCWord |= (u32_t) UCodeRead16(blockData); + CRCWord |= (u32) UCodeRead16(blockData); for (j = 0; j < 16; j++) { CRCWord <<= 1; if (carry != 0) { @@ -957,9 +957,9 @@ static u16_t UCodeComputeCRC(pu8_t blockData, u16_t nrWords) carry = CRCWord & 0x80000000UL; } i++; - blockData += (sizeof(u16_t)); + blockData += (sizeof(u16)); } - return ((u16_t) (CRCWord >> 16)); + return ((u16) (CRCWord >> 16)); } /*============================================================================*/ @@ -987,10 +987,10 @@ CtrlUCode(pDRXDemodInstance_t demod, pDRXUCodeInfo_t mcInfo, DRXUCodeAction_t action) { DRXStatus_t rc; - u16_t i = 0; - u16_t mcNrOfBlks = 0; - u16_t mcMagicWord = 0; - pu8_t mcData = (pu8_t) (NULL); + u16 i = 0; + u16 mcNrOfBlks = 0; + u16 mcMagicWord = 0; + u8 *mcData = (u8 *) (NULL); struct i2c_device_addr *devAddr = (struct i2c_device_addr *) (NULL); devAddr = demod->myI2CDevAddr; @@ -1004,9 +1004,9 @@ CtrlUCode(pDRXDemodInstance_t demod, /* Check data */ mcMagicWord = UCodeRead16(mcData); - mcData += sizeof(u16_t); + mcData += sizeof(u16); mcNrOfBlks = UCodeRead16(mcData); - mcData += sizeof(u16_t); + mcData += sizeof(u16); if ((mcMagicWord != DRX_UCODE_MAGIC_WORD) || (mcNrOfBlks == 0)) { /* wrong endianess or wrong data ? */ @@ -1025,35 +1025,35 @@ CtrlUCode(pDRXDemodInstance_t demod, /* Process block header */ blockHdr.addr = UCodeRead32(mcData); - mcData += sizeof(u32_t); + mcData += sizeof(u32); blockHdr.size = UCodeRead16(mcData); - mcData += sizeof(u16_t); + mcData += sizeof(u16); blockHdr.flags = UCodeRead16(mcData); - mcData += sizeof(u16_t); + mcData += sizeof(u16); blockHdr.CRC = UCodeRead16(mcData); - mcData += sizeof(u16_t); + mcData += sizeof(u16); if (blockHdr.flags & 0x8) { /* Aux block. Check type */ - pu8_t auxblk = mcInfo->mcData + blockHdr.addr; - u16_t auxtype = UCodeRead16(auxblk); + u8 *auxblk = mcInfo->mcData + blockHdr.addr; + u16 auxtype = UCodeRead16(auxblk); if (DRX_ISMCVERTYPE(auxtype)) { DRX_SET_MCVERTYPE(demod, UCodeRead16(auxblk)); - auxblk += sizeof(u16_t); + auxblk += sizeof(u16); DRX_SET_MCDEV(demod, UCodeRead32(auxblk)); - auxblk += sizeof(u32_t); + auxblk += sizeof(u32); DRX_SET_MCVERSION(demod, UCodeRead32(auxblk)); - auxblk += sizeof(u32_t); + auxblk += sizeof(u32); DRX_SET_MCPATCH(demod, UCodeRead32(auxblk)); } } /* Next block */ - mcData += blockHdr.size * sizeof(u16_t); + mcData += blockHdr.size * sizeof(u16); } /* After scanning, validate the microcode. @@ -1065,23 +1065,23 @@ CtrlUCode(pDRXDemodInstance_t demod, } /* Restore data pointer */ - mcData = mcInfo->mcData + 2 * sizeof(u16_t); + mcData = mcInfo->mcData + 2 * sizeof(u16); } /* Process microcode blocks */ for (i = 0; i < mcNrOfBlks; i++) { DRXUCodeBlockHdr_t blockHdr; - u16_t mcBlockNrBytes = 0; + u16 mcBlockNrBytes = 0; /* Process block header */ blockHdr.addr = UCodeRead32(mcData); - mcData += sizeof(u32_t); + mcData += sizeof(u32); blockHdr.size = UCodeRead16(mcData); - mcData += sizeof(u16_t); + mcData += sizeof(u16); blockHdr.flags = UCodeRead16(mcData); - mcData += sizeof(u16_t); + mcData += sizeof(u16); blockHdr.CRC = UCodeRead16(mcData); - mcData += sizeof(u16_t); + mcData += sizeof(u16); /* Check block header on: - data larger than 64Kb @@ -1095,7 +1095,7 @@ CtrlUCode(pDRXDemodInstance_t demod, return DRX_STS_INVALID_ARG; } - mcBlockNrBytes = blockHdr.size * ((u16_t) sizeof(u16_t)); + mcBlockNrBytes = blockHdr.size * ((u16) sizeof(u16)); if (blockHdr.size != 0) { /* Perform the desired action */ @@ -1120,12 +1120,12 @@ CtrlUCode(pDRXDemodInstance_t demod, case UCODE_VERIFY: { int result = 0; - u8_t mcDataBuffer + u8 mcDataBuffer [DRX_UCODE_MAX_BUF_SIZE]; - u32_t bytesToCompare = 0; - u32_t bytesLeftToCompare = 0; + u32 bytesToCompare = 0; + u32 bytesLeftToCompare = 0; DRXaddr_t currAddr = (DRXaddr_t) 0; - pu8_t currPtr = NULL; + u8 *currPtr = NULL; bytesLeftToCompare = mcBlockNrBytes; currAddr = blockHdr.addr; @@ -1133,10 +1133,10 @@ CtrlUCode(pDRXDemodInstance_t demod, while (bytesLeftToCompare != 0) { if (bytesLeftToCompare > - ((u32_t) + ((u32) DRX_UCODE_MAX_BUF_SIZE)) { bytesToCompare = - ((u32_t) + ((u32) DRX_UCODE_MAX_BUF_SIZE); } else { bytesToCompare = @@ -1146,9 +1146,9 @@ CtrlUCode(pDRXDemodInstance_t demod, if (demod->myAccessFunct-> readBlockFunc(devAddr, currAddr, - (u16_t) + (u16) bytesToCompare, - (pu8_t) + (u8 *) mcDataBuffer, 0x0000) != DRX_STS_OK) { @@ -1170,7 +1170,7 @@ CtrlUCode(pDRXDemodInstance_t demod, currPtr = &(currPtr[bytesToCompare]); bytesLeftToCompare -= - ((u32_t) bytesToCompare); + ((u32) bytesToCompare); } /* while( bytesToCompare > DRX_UCODE_MAX_BUF_SIZE ) */ }; break; @@ -1464,7 +1464,7 @@ DRX_Ctrl(pDRXDemodInstance_t demod, DRXCtrlIndex_t ctrl, void *ctrlData) /*===================================================================*/ case DRX_CTRL_SCAN_NEXT: { - return CtrlScanNext(demod, (pu16_t) ctrlData); + return CtrlScanNext(demod, (u16 *) ctrlData); } break; diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h index c88c064..8f0f2ed 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h @@ -262,20 +262,20 @@ MACROS * The macro takes care of the required byte order in a 16 bits word. * x->lowbyte(x), highbyte(x) */ -#define DRX_16TO8( x ) ((u8_t) (((u16_t)x) &0xFF)), \ - ((u8_t)((((u16_t)x)>>8)&0xFF)) +#define DRX_16TO8( x ) ((u8) (((u16)x) &0xFF)), \ + ((u8)((((u16)x)>>8)&0xFF)) /** * \brief Macro to sign extend signed 9 bit value to signed 16 bit value */ -#define DRX_S9TOS16(x) ((((u16_t)x)&0x100 )?((s16_t)((u16_t)(x)|0xFF00)):(x)) +#define DRX_S9TOS16(x) ((((u16)x)&0x100 )?((s16)((u16)(x)|0xFF00)):(x)) /** * \brief Macro to sign extend signed 9 bit value to signed 16 bit value */ -#define DRX_S24TODRXFREQ(x) ( ( ( (u32_t) x ) & 0x00800000UL ) ? \ +#define DRX_S24TODRXFREQ(x) ( ( ( (u32) x ) & 0x00800000UL ) ? \ ( (DRXFrequency_t) \ - ( ( (u32_t) x ) | 0xFF000000 ) ) : \ + ( ( (u32) x ) | 0xFF000000 ) ) : \ ( (DRXFrequency_t) x ) ) /** @@ -283,7 +283,7 @@ MACROS */ #define DRX_U16TODRXFREQ(x) ( ( x & 0x8000 ) ? \ ( (DRXFrequency_t) \ - ( ( (u32_t) x ) | 0xFFFF0000 ) ) : \ + ( ( (u32) x ) | 0xFFFF0000 ) ) : \ ( (DRXFrequency_t) x ) ) /*------------------------------------------------------------------------- @@ -579,7 +579,7 @@ ENUM * \enum DRXCtrlIndex_t * \brief Indices of the control functions. */ - typedef u32_t DRXCtrlIndex_t, *pDRXCtrlIndex_t; + typedef u32 DRXCtrlIndex_t, *pDRXCtrlIndex_t; #ifndef DRX_CTRL_BASE #define DRX_CTRL_BASE ((DRXCtrlIndex_t)0) @@ -781,7 +781,7 @@ STRUCTS * \enum DRXCfgType_t * \brief Generic configuration function identifiers. */ - typedef u32_t DRXCfgType_t, *pDRXCfgType_t; + typedef u32 DRXCfgType_t, *pDRXCfgType_t; #ifndef DRX_CFG_BASE #define DRX_CFG_BASE ((DRXCfgType_t)0) @@ -821,9 +821,9 @@ STRUCTS * Used by DRX_CTRL_LOAD_UCODE and DRX_CTRL_VERIFY_UCODE */ typedef struct { - pu8_t mcData; + u8 *mcData; /**< Pointer to microcode image. */ - u16_t mcSize; + u16 mcSize; /**< Microcode image size. */ } DRXUCodeInfo_t, *pDRXUCodeInfo_t; @@ -847,10 +847,10 @@ STRUCTS #define AUX_VER_RECORD 0x8000 typedef struct { - u16_t auxType; /* type of aux data - 0x8000 for version record */ - u32_t mcDevType; /* device type, based on JTAG ID */ - u32_t mcVersion; /* version of microcode */ - u32_t mcBaseVersion; /* in case of patch: the original microcode version */ + u16 auxType; /* type of aux data - 0x8000 for version record */ + u32 mcDevType; /* device type, based on JTAG ID */ + u32 mcVersion; /* version of microcode */ + u32 mcBaseVersion; /* in case of patch: the original microcode version */ } DRXMcVersionRec_t, *pDRXMcVersionRec_t; /*========================================*/ @@ -862,13 +862,13 @@ STRUCTS * Used by DRX_CTRL_LOAD_FILTER */ typedef struct { - pu8_t dataRe; + u8 *dataRe; /**< pointer to coefficients for RE */ - pu8_t dataIm; + u8 *dataIm; /**< pointer to coefficients for IM */ - u16_t sizeRe; + u16 sizeRe; /**< size of coefficients for RE */ - u16_t sizeIm; + u16 sizeIm; /**< size of coefficients for IM */ } DRXFilterInfo_t, *pDRXFilterInfo_t; @@ -918,21 +918,21 @@ STRUCTS * Used by DRX_CTRL_SIG_QUALITY. */ typedef struct { - u16_t MER; /**< in steps of 0.1 dB */ - u32_t preViterbiBER; + u16 MER; /**< in steps of 0.1 dB */ + u32 preViterbiBER; /**< in steps of 1/scaleFactorBER */ - u32_t postViterbiBER; + u32 postViterbiBER; /**< in steps of 1/scaleFactorBER */ - u32_t scaleFactorBER; + u32 scaleFactorBER; /**< scale factor for BER */ - u16_t packetError; + u16 packetError; /**< number of packet errors */ - u32_t postReedSolomonBER; + u32 postReedSolomonBER; /**< in steps of 1/scaleFactorBER */ - u32_t preLdpcBER; + u32 preLdpcBER; /**< in steps of 1/scaleFactorBER */ - u32_t averIter;/**< in steps of 0.01 */ - u16_t indicator; + u32 averIter;/**< in steps of 0.01 */ + u16 indicator; /**< indicative signal quality low=0..100=high */ } DRXSigQuality_t, *pDRXSigQuality_t; @@ -952,9 +952,9 @@ STRUCTS * Used by DRX_CTRL_CONSTEL. */ typedef struct { - s16_t im; + s16 im; /**< Imaginary part. */ - s16_t re; + s16 re; /**< Real part. */ } DRXComplex_t, *pDRXComplex_t; @@ -975,7 +975,7 @@ STRUCTS /**< Stepping frequency in this band */ DRXBandwidth_t bandwidth; /**< Bandwidth within this frequency band */ - u16_t chNumber; + u16 chNumber; /**< First channel number in this band, or first index in chNames */ char **chNames; @@ -1004,12 +1004,12 @@ STRUCTS * QAM specific scanning variables */ typedef struct { - pu32_t symbolrate; /**< list of symbolrates to scan */ - u16_t symbolrateSize; /**< size of symbolrate array */ + u32 *symbolrate; /**< list of symbolrates to scan */ + u16 symbolrateSize; /**< size of symbolrate array */ pDRXConstellation_t constellation; /**< list of constellations */ - u16_t constellationSize; /**< size of constellation array */ - u16_t ifAgcThreshold; /**< thresholf for IF-AGC based + u16 constellationSize; /**< size of constellation array */ + u16 ifAgcThreshold; /**< thresholf for IF-AGC based scanning filter */ } DRXScanDataQam_t, *pDRXScanDataQam_t; @@ -1020,7 +1020,7 @@ STRUCTS * ATV specific scanning variables */ typedef struct { - s16_t svrThreshold; + s16 svrThreshold; /**< threshold of Sound/Video ratio in 0.1dB steps */ } DRXScanDataAtv_t, *pDRXScanDataAtv_t; @@ -1035,8 +1035,8 @@ STRUCTS typedef struct { pDRXFrequencyPlan_t frequencyPlan; /**< Frequency plan (array)*/ - u16_t frequencyPlanSize; /**< Number of bands */ - u32_t numTries; /**< Max channels tried */ + u16 frequencyPlanSize; /**< Number of bands */ + u32 numTries; /**< Max channels tried */ DRXFrequency_t skip; /**< Minimum frequency step to take after a channel is found */ void *extParams; /**< Standard specific params */ @@ -1084,8 +1084,8 @@ STRUCTS DRXCoderate_t lowCoderate; /**< Low cod rate */ DRXTPSFrame_t frame; /**< Tps frame */ - u8_t length; /**< Length */ - u16_t cellId; /**< Cell id */ + u8 length; /**< Length */ + u16 cellId; /**< Cell id */ } DRXTPSInfo_t, *pDRXTPSInfo_t; /*========================================*/ @@ -1166,9 +1166,9 @@ STRUCTS /**< Type identifier of the module */ char *moduleName; /**< Name or description of module */ - u16_t vMajor; /**< Major version number */ - u16_t vMinor; /**< Minor version number */ - u16_t vPatch; /**< Patch version number */ + u16 vMajor; /**< Major version number */ + u16 vMinor; /**< Minor version number */ + u16 vPatch; /**< Patch version number */ char *vString; /**< Version as text string */ } DRXVersion_t, *pDRXVersion_t; @@ -1237,8 +1237,8 @@ STRUCTS typedef struct { DRXFrequency_t frequency; /**< Frequency in Khz */ DRXLockStatus_t lock; /**< Lock status */ - u32_t mer; /**< MER */ - s32_t symbolRateOffset; /**< Symbolrate offset in ppm */ + u32 mer; /**< MER */ + s32 symbolRateOffset; /**< Symbolrate offset in ppm */ } DRXOOBStatus_t, *pDRXOOBStatus_t; /*========================================*/ @@ -1291,7 +1291,7 @@ STRUCTS will be used, otherwise clockrate will adapt to the bitrate of the TS */ - u32_t bitrate; /**< Maximum bitrate in b/s in case + u32 bitrate; /**< Maximum bitrate in b/s in case static clockrate is selected */ DRXMPEGStrWidth_t widthSTR; /**< MPEG start width */ @@ -1313,7 +1313,7 @@ STRUCTS */ typedef struct { DRXCfgSMAIO_t io; - u16_t ctrlData; + u16 ctrlData; Bool_t smartAntInverted; } DRXCfgSMA_t, *pDRXCfgSMA_t; @@ -1328,15 +1328,15 @@ STRUCTS * */ typedef struct { - u16_t portNr; /**< I2C port number */ + u16 portNr; /**< I2C port number */ struct i2c_device_addr *wDevAddr; /**< Write device address */ - u16_t wCount; /**< Size of write data in bytes */ - pu8_t wData; /**< Pointer to write data */ + u16 wCount; /**< Size of write data in bytes */ + u8 *wData; /**< Pointer to write data */ struct i2c_device_addr *rDevAddr; /**< Read device address */ - u16_t rCount; /**< Size of data to read in bytes */ - pu8_t rData; /**< Pointer to read buffer */ + u16 rCount; /**< Size of data to read in bytes */ + u8 *rData; /**< Pointer to read buffer */ } DRXI2CData_t, *pDRXI2CData_t; /*========================================*/ @@ -1398,7 +1398,7 @@ STRUCTS Bool_t rds; /**< RDS data array present */ DRXAudNICAMStatus_t nicamStatus; /**< status of NICAM carrier */ - s8_t fmIdent; /**< FM Identification value */ + s8 fmIdent; /**< FM Identification value */ } DRXAudStatus_t, *pDRXAudStatus_t; /* CTRL_AUD_READ_RDS - DRXRDSdata_t */ @@ -1409,7 +1409,7 @@ STRUCTS */ typedef struct { Bool_t valid; /**< RDS data validation */ - u16_t data[18]; /**< data from one RDS data array */ + u16 data[18]; /**< data from one RDS data array */ } DRXCfgAudRDS_t, *pDRXCfgAudRDS_t; /* DRX_CFG_AUD_VOLUME - DRXCfgAudVolume_t - set/get */ @@ -1452,15 +1452,15 @@ STRUCTS */ typedef struct { Bool_t mute; /**< mute overrides volume setting */ - s16_t volume; /**< volume, range -114 to 12 dB */ + s16 volume; /**< volume, range -114 to 12 dB */ DRXAudAVCMode_t avcMode; /**< AVC auto volume control mode */ - u16_t avcRefLevel; /**< AVC reference level */ + u16 avcRefLevel; /**< AVC reference level */ DRXAudAVCMaxGain_t avcMaxGain; /**< AVC max gain selection */ DRXAudAVCMaxAtten_t avcMaxAtten; /**< AVC max attenuation selection */ - s16_t strengthLeft; /**< quasi-peak, left speaker */ - s16_t strengthRight; /**< quasi-peak, right speaker */ + s16 strengthLeft; /**< quasi-peak, left speaker */ + s16 strengthRight; /**< quasi-peak, right speaker */ } DRXCfgAudVolume_t, *pDRXCfgAudVolume_t; /* DRX_CFG_I2S_OUTPUT - DRXCfgI2SOutput_t - set/get */ @@ -1508,7 +1508,7 @@ STRUCTS */ typedef struct { Bool_t outputEnable; /**< I2S output enable */ - u32_t frequency; /**< range from 8000-48000 Hz */ + u32 frequency; /**< range from 8000-48000 Hz */ DRXI2SMode_t mode; /**< I2S mode, master or slave */ DRXI2SWordLength_t wordLength; /**< I2S wordlength, 16 or 32 bits */ @@ -1563,9 +1563,9 @@ STRUCTS * \brief Automatic Sound Select Thresholds */ typedef struct { - u16_t a2; /* A2 Threshold for ASS configuration */ - u16_t btsc; /* BTSC Threshold for ASS configuration */ - u16_t nicam; /* Nicam Threshold for ASS configuration */ + u16 a2; /* A2 Threshold for ASS configuration */ + u16 btsc; /* BTSC Threshold for ASS configuration */ + u16 nicam; /* Nicam Threshold for ASS configuration */ } DRXCfgAudASSThres_t, *pDRXCfgAudASSThres_t; /** @@ -1573,7 +1573,7 @@ STRUCTS * \brief Carrier detection related parameters */ typedef struct { - u16_t thres; /* carrier detetcion threshold for primary carrier (A) */ + u16 thres; /* carrier detetcion threshold for primary carrier (A) */ DRXNoCarrierOption_t opt; /* Mute or noise at no carrier detection (A) */ DRXFrequency_t shift; /* DC level of incoming signal (A) */ DRXFrequency_t dco; /* frequency adjustment (A) */ @@ -1657,8 +1657,8 @@ STRUCTS * \brief Prescalers */ typedef struct { - u16_t fmDeviation; - s16_t nicamGain; + u16 fmDeviation; + s16 nicamGain; } DRXCfgAudPrescale_t, *pDRXCfgAudPrescale_t; /** @@ -1666,8 +1666,8 @@ STRUCTS * \brief Beep */ typedef struct { - s16_t volume; /* dB */ - u16_t frequency; /* Hz */ + s16 volume; /* dB */ + u16 frequency; /* Hz */ Bool_t mute; } DRXAudBeep_t, *pDRXAudBeep_t; @@ -1700,7 +1700,7 @@ STRUCTS DRXAudFMDeemphasis_t deemph; DRXAudBtscDetect_t btscDetect; /* rds */ - u16_t rdsDataCounter; + u16 rdsDataCounter; Bool_t rdsDataPresent; } DRXAudData_t, *pDRXAudData_t; @@ -1720,81 +1720,81 @@ STRUCTS /*============================================================================*/ /* Address on device */ - typedef u32_t DRXaddr_t, *pDRXaddr_t; + typedef u32 DRXaddr_t, *pDRXaddr_t; /* Protocol specific flags */ - typedef u32_t DRXflags_t, *pDRXflags_t; + typedef u32 DRXflags_t, *pDRXflags_t; /* Write block of data to device */ typedef DRXStatus_t(*DRXWriteBlockFunc_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register/memory */ - u16_t datasize, /* size of data in bytes */ - pu8_t data, /* data to send */ + u16 datasize, /* size of data in bytes */ + u8 *data, /* data to send */ DRXflags_t flags); /* Read block of data from device */ typedef DRXStatus_t(*DRXReadBlockFunc_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register/memory */ - u16_t datasize, /* size of data in bytes */ - pu8_t data, /* receive buffer */ + u16 datasize, /* size of data in bytes */ + u8 *data, /* receive buffer */ DRXflags_t flags); /* Write 8-bits value to device */ typedef DRXStatus_t(*DRXWriteReg8Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register/memory */ - u8_t data, /* data to send */ + u8 data, /* data to send */ DRXflags_t flags); /* Read 8-bits value to device */ typedef DRXStatus_t(*DRXReadReg8Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register/memory */ - pu8_t data, /* receive buffer */ + u8 *data, /* receive buffer */ DRXflags_t flags); /* Read modify write 8-bits value to device */ typedef DRXStatus_t(*DRXReadModifyWriteReg8Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t waddr, /* write address of register */ DRXaddr_t raddr, /* read address of register */ - u8_t wdata, /* data to write */ - pu8_t rdata); /* data to read */ + u8 wdata, /* data to write */ + u8 *rdata); /* data to read */ /* Write 16-bits value to device */ typedef DRXStatus_t(*DRXWriteReg16Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register/memory */ - u16_t data, /* data to send */ + u16 data, /* data to send */ DRXflags_t flags); /* Read 16-bits value to device */ typedef DRXStatus_t(*DRXReadReg16Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register/memory */ - pu16_t data, /* receive buffer */ + u16 *data, /* receive buffer */ DRXflags_t flags); /* Read modify write 16-bits value to device */ typedef DRXStatus_t(*DRXReadModifyWriteReg16Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t waddr, /* write address of register */ DRXaddr_t raddr, /* read address of register */ - u16_t wdata, /* data to write */ - pu16_t rdata); /* data to read */ + u16 wdata, /* data to write */ + u16 *rdata); /* data to read */ /* Write 32-bits value to device */ typedef DRXStatus_t(*DRXWriteReg32Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register/memory */ - u32_t data, /* data to send */ + u32 data, /* data to send */ DRXflags_t flags); /* Read 32-bits value to device */ typedef DRXStatus_t(*DRXReadReg32Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register/memory */ - pu32_t data, /* receive buffer */ + u32 *data, /* receive buffer */ DRXflags_t flags); /* Read modify write 32-bits value to device */ typedef DRXStatus_t(*DRXReadModifyWriteReg32Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t waddr, /* write address of register */ DRXaddr_t raddr, /* read address of register */ - u32_t wdata, /* data to write */ - pu32_t rdata); /* data to read */ + u32 wdata, /* data to write */ + u32 *rdata); /* data to read */ /** * \struct DRXAccessFunc_t @@ -1819,7 +1819,7 @@ STRUCTS typedef struct { DRXaddr_t address; - u32_t data; + u32 data; } DRXRegDump_t, *pDRXRegDump_t; @@ -1835,8 +1835,8 @@ STRUCTS */ typedef struct { /* Microcode (firmware) attributes */ - pu8_t microcode; /**< Pointer to microcode image. */ - u16_t microcodeSize; + u8 *microcode; /**< Pointer to microcode image. */ + u16 microcodeSize; /**< Size of microcode image in bytes. */ Bool_t verifyMicrocode; /**< Use microcode verify or not. */ @@ -1850,7 +1850,7 @@ STRUCTS /**< Systemclock frequency. (kHz) */ DRXFrequency_t oscClockFreq; /**< Oscillator clock frequency. (kHz) */ - s16_t oscClockDeviation; + s16 oscClockDeviation; /**< Oscillator clock deviation. (ppm) */ Bool_t mirrorFreqSpect; /**< Mirror IF frequency spectrum or not.*/ @@ -1864,13 +1864,13 @@ STRUCTS /* Channel scan */ pDRXScanParam_t scanParam; /**< scan parameters */ - u16_t scanFreqPlanIndex; + u16 scanFreqPlanIndex; /**< next index in freq plan */ DRXFrequency_t scanNextFrequency; /**< next freq to scan */ Bool_t scanReady; /**< scan ready flag */ - u32_t scanMaxChannels;/**< number of channels in freqplan */ - u32_t scanChannelsScanned; + u32 scanMaxChannels;/**< number of channels in freqplan */ + u32 scanChannelsScanned; /**< number of channels scanned */ /* Channel scan - inner loop: demod related */ DRXScanFunc_t scanFunction; @@ -1878,7 +1878,7 @@ STRUCTS /* Channel scan - inner loop: SYSObj related */ void *scanContext; /**< Context Pointer of SYSObj */ /* Channel scan - parameters for default DTV scan function in core driver */ - u16_t scanDemodLockTimeout; + u16 scanDemodLockTimeout; /**< millisecs to wait for lock */ DRXLockStatus_t scanDesiredLock; /**< lock requirement for channel found */ @@ -1891,7 +1891,7 @@ STRUCTS /**< current power management mode */ /* Tuner */ - u8_t tunerPortNr; /**< nr of I2C port to wich tuner is */ + u8 tunerPortNr; /**< nr of I2C port to wich tuner is */ DRXFrequency_t tunerMinFreqRF; /**< minimum RF input frequency, in kHz */ DRXFrequency_t tunerMaxFreqRF; @@ -1909,8 +1909,8 @@ STRUCTS DRXStandard_t diCacheStandard; /**< standard in DI cache if available */ Bool_t useBootloader; /**< use bootloader in open */ - u32_t capabilities; /**< capabilities flags */ - u32_t productId; /**< product ID inc. metal fix number */ + u32 capabilities; /**< capabilities flags */ + u32 productId; /**< product ID inc. metal fix number */ } DRXCommonAttr_t, *pDRXCommonAttr_t; @@ -1930,7 +1930,7 @@ STRUCTS * \brief A stucture containing all functions of a demodulator. */ typedef struct { - u32_t typeId; /**< Device type identifier. */ + u32 typeId; /**< Device type identifier. */ DRXOpenFunc_t openFunc; /**< Pointer to Open() function. */ DRXCloseFunc_t closeFunc;/**< Pointer to Close() function. */ DRXCtrlFunc_t ctrlFunc; /**< Pointer to Ctrl() function. */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index a41b2a9..b79154f 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -52,10 +52,10 @@ INCLUDE FILES /*============================================================================*/ /** -* \brief Maximum u32_t value. +* \brief Maximum u32 value. */ #ifndef MAX_U32 -#define MAX_U32 ((u32_t) (0xFFFFFFFFL)) +#define MAX_U32 ((u32) (0xFFFFFFFFL)) #endif /* Customer configurable hardware settings, etc */ @@ -328,7 +328,7 @@ DEFINES */ #ifndef DRXJ_UCODE_MAGIC_WORD -#define DRXJ_UCODE_MAGIC_WORD ((((u16_t)'H')<<8)+((u16_t)'L')) +#define DRXJ_UCODE_MAGIC_WORD ((((u16)'H')<<8)+((u16)'L')) #endif /** @@ -504,7 +504,7 @@ DEFINES #define DUMMY_READ() \ do{ \ - u16_t dummy; \ + u16 dummy; \ RR16( demod->myI2CDevAddr, SCU_RAM_VERSION_HI__A, &dummy ); \ } while (0) @@ -544,14 +544,14 @@ DEFINES * The macro takes care of the required byte order in a 16 bits word. * x -> lowbyte(x), highbyte(x) */ -#define DRXJ_16TO8( x ) ((u8_t) (((u16_t)x) &0xFF)), \ - ((u8_t)((((u16_t)x)>>8)&0xFF)) +#define DRXJ_16TO8( x ) ((u8) (((u16)x) &0xFF)), \ + ((u8)((((u16)x)>>8)&0xFF)) /** * This macro is used to convert byte array to 16 bit register value for block read. * Block read speed up I2C traffic between host and demod. * The macro takes care of the required byte order in a 16 bits word. */ -#define DRXJ_8TO16( x ) ((u16_t) (x[0] | (x[1] << 8))) +#define DRXJ_8TO16( x ) ((u16) (x[0] | (x[1] << 8))) /*============================================================================*/ /*=== MISC DEFINES ===========================================================*/ @@ -600,52 +600,52 @@ GLOBAL VARIABLES static DRXStatus_t DRXJ_DAP_ReadBlock(struct i2c_device_addr *devAddr, DRXaddr_t addr, - u16_t datasize, - pu8_t data, DRXflags_t flags); + u16 datasize, + u8 *data, DRXflags_t flags); static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg8(struct i2c_device_addr *devAddr, DRXaddr_t waddr, DRXaddr_t raddr, - u8_t wdata, pu8_t rdata); + u8 wdata, u8 *rdata); static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg16(struct i2c_device_addr *devAddr, DRXaddr_t waddr, DRXaddr_t raddr, - u16_t wdata, pu16_t rdata); + u16 wdata, u16 *rdata); static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg32(struct i2c_device_addr *devAddr, DRXaddr_t waddr, DRXaddr_t raddr, - u32_t wdata, pu32_t rdata); + u32 wdata, u32 *rdata); static DRXStatus_t DRXJ_DAP_ReadReg8(struct i2c_device_addr *devAddr, DRXaddr_t addr, - pu8_t data, DRXflags_t flags); + u8 *data, DRXflags_t flags); static DRXStatus_t DRXJ_DAP_ReadReg16(struct i2c_device_addr *devAddr, DRXaddr_t addr, - pu16_t data, DRXflags_t flags); + u16 *data, DRXflags_t flags); static DRXStatus_t DRXJ_DAP_ReadReg32(struct i2c_device_addr *devAddr, DRXaddr_t addr, - pu32_t data, DRXflags_t flags); + u32 *data, DRXflags_t flags); static DRXStatus_t DRXJ_DAP_WriteBlock(struct i2c_device_addr *devAddr, DRXaddr_t addr, - u16_t datasize, - pu8_t data, DRXflags_t flags); + u16 datasize, + u8 *data, DRXflags_t flags); static DRXStatus_t DRXJ_DAP_WriteReg8(struct i2c_device_addr *devAddr, DRXaddr_t addr, - u8_t data, DRXflags_t flags); + u8 data, DRXflags_t flags); static DRXStatus_t DRXJ_DAP_WriteReg16(struct i2c_device_addr *devAddr, DRXaddr_t addr, - u16_t data, DRXflags_t flags); + u16 data, DRXflags_t flags); static DRXStatus_t DRXJ_DAP_WriteReg32(struct i2c_device_addr *devAddr, DRXaddr_t addr, - u32_t data, DRXflags_t flags); + u32 data, DRXflags_t flags); /* The version structure of this protocol implementation */ char drxDapDRXJModuleName[] = "DRXJ Data Access Protocol"; @@ -743,7 +743,7 @@ DRXJData_t DRXJData_g = { /* TRUE, * flagASDRequest */ /* FALSE, * flagHDevClear */ /* FALSE, * flagHDevSet */ -/* (u16_t) 0xFFF, * rdsLastCount */ +/* (u16) 0xFFF, * rdsLastCount */ /*#ifdef DRXJ_SPLIT_UCODE_UPLOAD FALSE, * flagAudMcUploaded */ @@ -950,7 +950,7 @@ struct i2c_device_addr DRXJDefaultAddr_g = { * \brief Default common attributes of a drxj demodulator instance. */ DRXCommonAttr_t DRXJDefaultCommAttr_g = { - (pu8_t) NULL, /* ucode ptr */ + (u8 *) NULL, /* ucode ptr */ 0, /* ucode size */ TRUE, /* ucode verify switch */ {0}, /* version record */ @@ -1109,21 +1109,21 @@ DRXAudData_t DRXJDefaultAudData_g = { STRUCTURES ----------------------------------------------------------------------------*/ typedef struct { - u16_t eqMSE; - u8_t eqMode; - u8_t eqCtrl; - u8_t eqStat; + u16 eqMSE; + u8 eqMode; + u8 eqCtrl; + u8 eqStat; } DRXJEQStat_t, *pDRXJEQStat_t; /* HI command */ typedef struct { - u16_t cmd; - u16_t param1; - u16_t param2; - u16_t param3; - u16_t param4; - u16_t param5; - u16_t param6; + u16 cmd; + u16 param1; + u16 param2; + u16 param3; + u16 param4; + u16 param5; + u16 param6; } DRXJHiCmd_t, *pDRXJHiCmd_t; #ifdef DRXJ_SPLIT_UCODE_UPLOAD @@ -1132,12 +1132,12 @@ typedef struct { /*============================================================================*/ typedef struct { - u32_t addr; - u16_t size; - u16_t flags; /* bit[15..2]=reserved, + u32 addr; + u16 size; + u16 flags; /* bit[15..2]=reserved, bit[1]= compression on/off bit[0]= CRC on/off */ - u16_t CRC; + u16 CRC; } DRXUCodeBlockHdr_t, *pDRXUCodeBlockHdr_t; #endif /* DRXJ_SPLIT_UCODE_UPLOAD */ @@ -1147,7 +1147,7 @@ FUNCTIONS /* Some prototypes */ static DRXStatus_t HICommand(struct i2c_device_addr *devAddr, - const pDRXJHiCmd_t cmd, pu16_t result); + const pDRXJHiCmd_t cmd, u16 *result); static DRXStatus_t CtrlLockStatus(pDRXDemodInstance_t demod, pDRXLockStatus_t lockStat); @@ -1184,7 +1184,7 @@ CtrlUCodeUpload(pDRXDemodInstance_t demod, /*============================================================================*/ /** -* \fn void Mult32(u32_t a, u32_t b, pu32_t h, pu32_t l) +* \fn void Mult32(u32 a, u32 b, u32 *h, u32 *l) * \brief 32bitsx32bits signed multiplication * \param a 32 bits multiplicant, typecast from signed to unisgned * \param b 32 bits multiplier, typecast from signed to unisgned @@ -1224,9 +1224,9 @@ CtrlUCodeUpload(pDRXDemodInstance_t demod, * */ -#define DRX_IS_BOOTH_NEGATIVE(__a) (((__a) & (1 << (sizeof (u32_t) * 8 - 1))) != 0) +#define DRX_IS_BOOTH_NEGATIVE(__a) (((__a) & (1 << (sizeof (u32) * 8 - 1))) != 0) -static void Mult32(u32_t a, u32_t b, pu32_t h, pu32_t l) +static void Mult32(u32 a, u32 b, u32 *h, u32 *l) { unsigned int i; *h = *l = 0; @@ -1256,17 +1256,17 @@ static void Mult32(u32_t a, u32_t b, pu32_t h, pu32_t l) case 4: *l -= b; *h = *h - !DRX_IS_BOOTH_NEGATIVE(b) + !b + (*l < - ((u32_t) + ((u32) (- - ((s32_t) + ((s32) b)))); case 5: case 6: *l -= b; *h = *h - !DRX_IS_BOOTH_NEGATIVE(b) + !b + (*l < - ((u32_t) + ((u32) (- - ((s32_t) + ((s32) b)))); break; } @@ -1276,7 +1276,7 @@ static void Mult32(u32_t a, u32_t b, pu32_t h, pu32_t l) /*============================================================================*/ /* -* \fn u32_t Frac28(u32_t N, u32_t D) +* \fn u32 Frac28(u32 N, u32 D) * \brief Compute: (1<<28)*N/D * \param N 32 bits * \param D 32 bits @@ -1295,11 +1295,11 @@ static void Mult32(u32_t a, u32_t b, pu32_t h, pu32_t l) * D: 0...(1<<28)-1 * Q: 0...(1<<32)-1 */ -static u32_t Frac28(u32_t N, u32_t D) +static u32 Frac28(u32 N, u32 D) { int i = 0; - u32_t Q1 = 0; - u32_t R0 = 0; + u32 Q1 = 0; + u32 R0 = 0; R0 = (N % D) << 4; /* 32-28 == 4 shifts possible at max */ Q1 = N / D; /* integer part, only the 4 least significant bits @@ -1318,7 +1318,7 @@ static u32_t Frac28(u32_t N, u32_t D) } /** -* \fn u32_t Log10Times100( u32_t x) +* \fn u32 Log10Times100( u32 x) * \brief Compute: 100*log10(x) * \param x 32 bits * \return 100*log10(x) @@ -1333,16 +1333,16 @@ static u32_t Frac28(u32_t N, u32_t D) * where y = 2^k and 1<= (x/y) < 2 */ -static u32_t Log10Times100(u32_t x) +static u32 Log10Times100(u32 x) { - static const u8_t scale = 15; - static const u8_t indexWidth = 5; + static const u8 scale = 15; + static const u8 indexWidth = 5; /* log2lut[n] = (1< 0; k--) { - if (x & (((u32_t) 1) << scale)) + if (x & (((u32) 1) << scale)) break; x <<= 1; } } else { for (k = scale; k < 31; k++) { - if ((x & (((u32_t) (-1)) << (scale + 1))) == 0) + if ((x & (((u32) (-1)) << (scale + 1))) == 0) break; x >>= 1; } @@ -1407,14 +1407,14 @@ static u32_t Log10Times100(u32_t x) and 1.0 <= x < 2.0 */ /* correction for divison: log(x) = log(x/y)+log(y) */ - y = k * ((((u32_t) 1) << scale) * 200); + y = k * ((((u32) 1) << scale) * 200); /* remove integer part */ - x &= ((((u32_t) 1) << scale) - 1); + x &= ((((u32) 1) << scale) - 1); /* get index */ - i = (u8_t) (x >> (scale - indexWidth)); + i = (u8) (x >> (scale - indexWidth)); /* compute delta (x-a) */ - d = x & ((((u32_t) 1) << (scale - indexWidth)) - 1); + d = x & ((((u32) 1) << (scale - indexWidth)) - 1); /* compute log, multiplication ( d* (.. )) must be within range ! */ y += log2lut[i] + ((d * (log2lut[i + 1] - log2lut[i])) >> (scale - indexWidth)); @@ -1422,7 +1422,7 @@ static u32_t Log10Times100(u32_t x) y /= 108853; /* (log2(10) << scale) */ r = (y >> 1); /* rounding */ - if (y & ((u32_t) 1)) + if (y & ((u32) 1)) r++; return (r); @@ -1430,19 +1430,19 @@ static u32_t Log10Times100(u32_t x) } /** -* \fn u32_t FracTimes1e6( u16_t N, u32_t D) +* \fn u32 FracTimes1e6( u16 N, u32 D) * \brief Compute: (N/D) * 1000000. * \param N nominator 16-bits. * \param D denominator 32-bits. -* \return u32_t +* \return u32 * \retval ((N/D) * 1000000), 32 bits * * No check on D=0! */ -static u32_t FracTimes1e6(u32_t N, u32_t D) +static u32 FracTimes1e6(u32 N, u32 D) { - u32_t remainder = 0; - u32_t frac = 0; + u32 remainder = 0; + u32 frac = 0; /* frac = (N * 1000000) / D @@ -1451,9 +1451,9 @@ static u32_t FracTimes1e6(u32_t N, u32_t D) This would result in a problem in case D < 16 (div by 0). So we do it more elaborate as shown below. */ - frac = (((u32_t) N) * (1000000 >> 4)) / D; + frac = (((u32) N) * (1000000 >> 4)) / D; frac <<= 4; - remainder = (((u32_t) N) * (1000000 >> 4)) % D; + remainder = (((u32) N) * (1000000 >> 4)) % D; remainder <<= 4; frac += remainder / D; remainder = remainder % D; @@ -1468,16 +1468,16 @@ static u32_t FracTimes1e6(u32_t N, u32_t D) /** * \brief Compute: 100 * 10^( GdB / 200 ). -* \param u32_t GdB Gain in 0.1dB -* \return u32_t Gainfactor in 0.01 resolution +* \param u32 GdB Gain in 0.1dB +* \return u32 Gainfactor in 0.01 resolution * */ -static u32_t dB2LinTimes100(u32_t GdB) +static u32 dB2LinTimes100(u32 GdB) { - u32_t result = 0; - u32_t nr6dBSteps = 0; - u32_t remainder = 0; - u32_t remainderFac = 0; + u32 result = 0; + u32 nr6dBSteps = 0; + u32 remainder = 0; + u32 remainderFac = 0; /* start with factors 2 (6.02dB) */ nr6dBSteps = GdB * 1000UL / 60206UL; @@ -1512,21 +1512,21 @@ static u32_t dB2LinTimes100(u32_t GdB) #define FRAC_CEIL 1 #define FRAC_ROUND 2 /** -* \fn u32_t Frac( u32_t N, u32_t D, u16_t RC ) +* \fn u32 Frac( u32 N, u32 D, u16 RC ) * \brief Compute: N/D. * \param N nominator 32-bits. * \param D denominator 32-bits. * \param RC-result correction: 0-floor; 1-ceil; 2-round -* \return u32_t +* \return u32 * \retval N/D, 32 bits * * If D=0 returns 0 */ -static u32_t Frac(u32_t N, u32_t D, u16_t RC) +static u32 Frac(u32 N, u32 D, u16 RC) { - u32_t remainder = 0; - u32_t frac = 0; - u16_t bitCnt = 32; + u32 remainder = 0; + u32 frac = 0; + u16 bitCnt = 32; if (D == 0) { frac = 0; @@ -1573,19 +1573,19 @@ static u32_t Frac(u32_t N, u32_t D, u16_t RC) /*============================================================================*/ /** -* \fn u16_t UCodeRead16( pu8_t addr) +* \fn u16 UCodeRead16( u8 *addr) * \brief Read a 16 bits word, expect big endian data. -* \return u16_t The data read. +* \return u16 The data read. */ -static u16_t UCodeRead16(pu8_t addr) +static u16 UCodeRead16(u8 *addr) { /* Works fo any host processor */ - u16_t word = 0; + u16 word = 0; - word = ((u16_t) addr[0]); + word = ((u16) addr[0]); word <<= 8; - word |= ((u16_t) addr[1]); + word |= ((u16) addr[1]); return (word); } @@ -1593,23 +1593,23 @@ static u16_t UCodeRead16(pu8_t addr) /*============================================================================*/ /** -* \fn u32_t UCodeRead32( pu8_t addr) +* \fn u32 UCodeRead32( u8 *addr) * \brief Read a 32 bits word, expect big endian data. -* \return u32_t The data read. +* \return u32 The data read. */ -static u32_t UCodeRead32(pu8_t addr) +static u32 UCodeRead32(u8 *addr) { /* Works fo any host processor */ - u32_t word = 0; + u32 word = 0; - word = ((u16_t) addr[0]); + word = ((u16) addr[0]); word <<= 8; - word |= ((u16_t) addr[1]); + word |= ((u16) addr[1]); word <<= 8; - word |= ((u16_t) addr[2]); + word |= ((u16) addr[2]); word <<= 8; - word |= ((u16_t) addr[3]); + word |= ((u16) addr[3]); return (word); } @@ -1617,21 +1617,21 @@ static u32_t UCodeRead32(pu8_t addr) /*============================================================================*/ /** -* \fn u16_t UCodeComputeCRC (pu8_t blockData, u16_t nrWords) +* \fn u16 UCodeComputeCRC (u8 *blockData, u16 nrWords) * \brief Compute CRC of block of microcode data. * \param blockData Pointer to microcode data. * \param nrWords Size of microcode block (number of 16 bits words). -* \return u16_t The computed CRC residu. +* \return u16 The computed CRC residu. */ -static u16_t UCodeComputeCRC(pu8_t blockData, u16_t nrWords) +static u16 UCodeComputeCRC(u8 *blockData, u16 nrWords) { - u16_t i = 0; - u16_t j = 0; - u32_t CRCWord = 0; - u32_t carry = 0; + u16 i = 0; + u16 j = 0; + u32 CRCWord = 0; + u32 carry = 0; while (i < nrWords) { - CRCWord |= (u32_t) UCodeRead16(blockData); + CRCWord |= (u32) UCodeRead16(blockData); for (j = 0; j < 16; j++) { CRCWord <<= 1; if (carry != 0) @@ -1639,9 +1639,9 @@ static u16_t UCodeComputeCRC(pu8_t blockData, u16_t nrWords) carry = CRCWord & 0x80000000UL; } i++; - blockData += (sizeof(u16_t)); + blockData += (sizeof(u16)); } - return ((u16_t) (CRCWord >> 16)); + return ((u16) (CRCWord >> 16)); } #endif /* DRXJ_SPLIT_UCODE_UPLOAD */ @@ -1650,7 +1650,7 @@ static u16_t UCodeComputeCRC(pu8_t blockData, u16_t nrWords) * and rounded. For calc used formula: 16*10^(prescaleGain[dB]/20). * */ -static const u16_t NicamPrescTableVal[43] = +static const u16 NicamPrescTableVal[43] = { 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 7, 8, 9, 10, 11, 13, 14, 16, 18, 20, 23, 25, 28, 32, 36, 40, 45, @@ -1714,8 +1714,8 @@ Bool_t IsHandledByAudTrIf(DRXaddr_t addr) static DRXStatus_t DRXJ_DAP_ReadBlock(struct i2c_device_addr *devAddr, DRXaddr_t addr, - u16_t datasize, - pu8_t data, DRXflags_t flags) + u16 datasize, + u8 *data, DRXflags_t flags) { return drxDapFASIFunct_g.readBlockFunc(devAddr, addr, datasize, data, flags); @@ -1726,7 +1726,7 @@ static DRXStatus_t DRXJ_DAP_ReadBlock(struct i2c_device_addr *devAddr, static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg8(struct i2c_device_addr *devAddr, DRXaddr_t waddr, DRXaddr_t raddr, - u8_t wdata, pu8_t rdata) + u8 wdata, u8 *rdata) { return drxDapFASIFunct_g.readModifyWriteReg8Func(devAddr, waddr, @@ -1759,7 +1759,7 @@ static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg8(struct i2c_device_addr *devAddr, static DRXStatus_t DRXJ_DAP_RMWriteReg16Short(struct i2c_device_addr *devAddr, DRXaddr_t waddr, DRXaddr_t raddr, - u16_t wdata, pu16_t rdata) + u16 wdata, u16 *rdata) { DRXStatus_t rc; @@ -1798,7 +1798,7 @@ static DRXStatus_t DRXJ_DAP_RMWriteReg16Short(struct i2c_device_addr *devAddr, static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg16(struct i2c_device_addr *devAddr, DRXaddr_t waddr, DRXaddr_t raddr, - u16_t wdata, pu16_t rdata) + u16 wdata, u16 *rdata) { /* TODO: correct short/long addressing format decision, now long format has higher prio then short because short also @@ -1817,7 +1817,7 @@ static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg16(struct i2c_device_addr *devAddr static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg32(struct i2c_device_addr *devAddr, DRXaddr_t waddr, DRXaddr_t raddr, - u32_t wdata, pu32_t rdata) + u32 wdata, u32 *rdata) { return drxDapFASIFunct_g.readModifyWriteReg32Func(devAddr, waddr, @@ -1828,7 +1828,7 @@ static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg32(struct i2c_device_addr *devAddr static DRXStatus_t DRXJ_DAP_ReadReg8(struct i2c_device_addr *devAddr, DRXaddr_t addr, - pu8_t data, DRXflags_t flags) + u8 *data, DRXflags_t flags) { return drxDapFASIFunct_g.readReg8Func(devAddr, addr, data, flags); } @@ -1849,12 +1849,12 @@ static DRXStatus_t DRXJ_DAP_ReadReg8(struct i2c_device_addr *devAddr, * */ static DRXStatus_t DRXJ_DAP_ReadAudReg16(struct i2c_device_addr *devAddr, - DRXaddr_t addr, pu16_t data) + DRXaddr_t addr, u16 *data) { - u32_t startTimer = 0; - u32_t currentTimer = 0; - u32_t deltaTimer = 0; - u16_t trStatus = 0; + u32 startTimer = 0; + u32 currentTimer = 0; + u32 deltaTimer = 0; + u16 trStatus = 0; DRXStatus_t stat = DRX_STS_ERROR; /* No read possible for bank 3, return with error */ @@ -1930,7 +1930,7 @@ static DRXStatus_t DRXJ_DAP_ReadAudReg16(struct i2c_device_addr *devAddr, static DRXStatus_t DRXJ_DAP_ReadReg16(struct i2c_device_addr *devAddr, DRXaddr_t addr, - pu16_t data, DRXflags_t flags) + u16 *data, DRXflags_t flags) { DRXStatus_t stat = DRX_STS_ERROR; @@ -1953,7 +1953,7 @@ static DRXStatus_t DRXJ_DAP_ReadReg16(struct i2c_device_addr *devAddr, static DRXStatus_t DRXJ_DAP_ReadReg32(struct i2c_device_addr *devAddr, DRXaddr_t addr, - pu32_t data, DRXflags_t flags) + u32 *data, DRXflags_t flags) { return drxDapFASIFunct_g.readReg32Func(devAddr, addr, data, flags); } @@ -1962,8 +1962,8 @@ static DRXStatus_t DRXJ_DAP_ReadReg32(struct i2c_device_addr *devAddr, static DRXStatus_t DRXJ_DAP_WriteBlock(struct i2c_device_addr *devAddr, DRXaddr_t addr, - u16_t datasize, - pu8_t data, DRXflags_t flags) + u16 datasize, + u8 *data, DRXflags_t flags) { return drxDapFASIFunct_g.writeBlockFunc(devAddr, addr, datasize, data, flags); @@ -1973,7 +1973,7 @@ static DRXStatus_t DRXJ_DAP_WriteBlock(struct i2c_device_addr *devAddr, static DRXStatus_t DRXJ_DAP_WriteReg8(struct i2c_device_addr *devAddr, DRXaddr_t addr, - u8_t data, DRXflags_t flags) + u8 data, DRXflags_t flags) { return drxDapFASIFunct_g.writeReg8Func(devAddr, addr, data, flags); } @@ -1994,7 +1994,7 @@ static DRXStatus_t DRXJ_DAP_WriteReg8(struct i2c_device_addr *devAddr, * */ static DRXStatus_t DRXJ_DAP_WriteAudReg16(struct i2c_device_addr *devAddr, - DRXaddr_t addr, u16_t data) + DRXaddr_t addr, u16 data) { DRXStatus_t stat = DRX_STS_ERROR; @@ -2002,10 +2002,10 @@ static DRXStatus_t DRXJ_DAP_WriteAudReg16(struct i2c_device_addr *devAddr, if (DRXDAP_FASI_ADDR2BANK(addr) == 2) { stat = DRX_STS_INVALID_ARG; } else { - u32_t startTimer = 0; - u32_t currentTimer = 0; - u32_t deltaTimer = 0; - u16_t trStatus = 0; + u32 startTimer = 0; + u32 currentTimer = 0; + u32 deltaTimer = 0; + u16 trStatus = 0; const DRXaddr_t writeBit = ((DRXaddr_t) 1) << 16; /* Force write bit */ @@ -2042,7 +2042,7 @@ static DRXStatus_t DRXJ_DAP_WriteAudReg16(struct i2c_device_addr *devAddr, static DRXStatus_t DRXJ_DAP_WriteReg16(struct i2c_device_addr *devAddr, DRXaddr_t addr, - u16_t data, DRXflags_t flags) + u16 data, DRXflags_t flags) { DRXStatus_t stat = DRX_STS_ERROR; @@ -2065,7 +2065,7 @@ static DRXStatus_t DRXJ_DAP_WriteReg16(struct i2c_device_addr *devAddr, static DRXStatus_t DRXJ_DAP_WriteReg32(struct i2c_device_addr *devAddr, DRXaddr_t addr, - u32_t data, DRXflags_t flags) + u32 data, DRXflags_t flags) { return drxDapFASIFunct_g.writeReg32Func(devAddr, addr, data, flags); } @@ -2096,14 +2096,14 @@ static DRXStatus_t DRXJ_DAP_WriteReg32(struct i2c_device_addr *devAddr, static DRXStatus_t DRXJ_DAP_AtomicReadWriteBlock(struct i2c_device_addr *devAddr, DRXaddr_t addr, - u16_t datasize, - pu8_t data, Bool_t readFlag) + u16 datasize, + u8 *data, Bool_t readFlag) { DRXJHiCmd_t hiCmd; - u16_t word; - u16_t dummy = 0; - u16_t i = 0; + u16 word; + u16 dummy = 0; + u16 i = 0; /* Parameter check */ if ((data == NULL) || @@ -2115,26 +2115,26 @@ DRXStatus_t DRXJ_DAP_AtomicReadWriteBlock(struct i2c_device_addr *devAddr, /* Set up HI parameters to read or write n bytes */ hiCmd.cmd = SIO_HI_RA_RAM_CMD_ATOMIC_COPY; hiCmd.param1 = - (u16_t) ((DRXDAP_FASI_ADDR2BLOCK(DRXJ_HI_ATOMIC_BUF_START) << 6) + + (u16) ((DRXDAP_FASI_ADDR2BLOCK(DRXJ_HI_ATOMIC_BUF_START) << 6) + DRXDAP_FASI_ADDR2BANK(DRXJ_HI_ATOMIC_BUF_START)); hiCmd.param2 = - (u16_t) DRXDAP_FASI_ADDR2OFFSET(DRXJ_HI_ATOMIC_BUF_START); - hiCmd.param3 = (u16_t) ((datasize / 2) - 1); + (u16) DRXDAP_FASI_ADDR2OFFSET(DRXJ_HI_ATOMIC_BUF_START); + hiCmd.param3 = (u16) ((datasize / 2) - 1); if (readFlag == FALSE) { hiCmd.param3 |= DRXJ_HI_ATOMIC_WRITE; } else { hiCmd.param3 |= DRXJ_HI_ATOMIC_READ; } - hiCmd.param4 = (u16_t) ((DRXDAP_FASI_ADDR2BLOCK(addr) << 6) + + hiCmd.param4 = (u16) ((DRXDAP_FASI_ADDR2BLOCK(addr) << 6) + DRXDAP_FASI_ADDR2BANK(addr)); - hiCmd.param5 = (u16_t) DRXDAP_FASI_ADDR2OFFSET(addr); + hiCmd.param5 = (u16) DRXDAP_FASI_ADDR2OFFSET(addr); if (readFlag == FALSE) { /* write data to buffer */ for (i = 0; i < (datasize / 2); i++) { - word = ((u16_t) data[2 * i]); - word += (((u16_t) data[(2 * i) + 1]) << 8); + word = ((u16) data[2 * i]); + word += (((u16) data[(2 * i) + 1]) << 8); DRXJ_DAP_WriteReg16(devAddr, (DRXJ_HI_ATOMIC_BUF_START + i), word, 0); @@ -2149,8 +2149,8 @@ DRXStatus_t DRXJ_DAP_AtomicReadWriteBlock(struct i2c_device_addr *devAddr, DRXJ_DAP_ReadReg16(devAddr, (DRXJ_HI_ATOMIC_BUF_START + i), &word, 0); - data[2 * i] = (u8_t) (word & 0xFF); - data[(2 * i) + 1] = (u8_t) (word >> 8); + data[2 * i] = (u8) (word & 0xFF); + data[(2 * i) + 1] = (u8) (word >> 8); } } @@ -2170,11 +2170,11 @@ rw_error: static DRXStatus_t DRXJ_DAP_AtomicReadReg32(struct i2c_device_addr *devAddr, DRXaddr_t addr, - pu32_t data, DRXflags_t flags) + u32 *data, DRXflags_t flags) { - u8_t buf[sizeof(*data)]; + u8 buf[sizeof(*data)]; DRXStatus_t rc = DRX_STS_ERROR; - u32_t word = 0; + u32 word = 0; if (!data) { return DRX_STS_INVALID_ARG; @@ -2183,13 +2183,13 @@ DRXStatus_t DRXJ_DAP_AtomicReadReg32(struct i2c_device_addr *devAddr, rc = DRXJ_DAP_AtomicReadWriteBlock(devAddr, addr, sizeof(*data), buf, TRUE); - word = (u32_t) buf[3]; + word = (u32) buf[3]; word <<= 8; - word |= (u32_t) buf[2]; + word |= (u32) buf[2]; word <<= 8; - word |= (u32_t) buf[1]; + word |= (u32) buf[1]; word <<= 8; - word |= (u32_t) buf[0]; + word |= (u32) buf[0]; *data = word; @@ -2223,7 +2223,7 @@ static DRXStatus_t HICfgCommand(const pDRXDemodInstance_t demod) { pDRXJData_t extAttr = (pDRXJData_t) (NULL); DRXJHiCmd_t hiCmd; - u16_t result = 0; + u16 result = 0; extAttr = (pDRXJData_t) demod->myExtAttr; @@ -2258,10 +2258,10 @@ rw_error: * */ static DRXStatus_t -HICommand(struct i2c_device_addr *devAddr, const pDRXJHiCmd_t cmd, pu16_t result) +HICommand(struct i2c_device_addr *devAddr, const pDRXJHiCmd_t cmd, u16 *result) { - u16_t waitCmd = 0; - u16_t nrRetries = 0; + u16 waitCmd = 0; + u16 nrRetries = 0; Bool_t powerdown_cmd = FALSE; /* Write parameters */ @@ -2350,7 +2350,7 @@ static DRXStatus_t InitHI(const pDRXDemodInstance_t demod) /* Timing div, 250ns/Psys */ /* Timing div, = ( delay (nano seconds) * sysclk (kHz) )/ 1000 */ extAttr->HICfgTimingDiv = - (u16_t) ((commonAttr->sysClockFreq / 1000) * HI_I2C_DELAY) / 1000; + (u16) ((commonAttr->sysClockFreq / 1000) * HI_I2C_DELAY) / 1000; /* Clipping */ if ((extAttr->HICfgTimingDiv) > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M) { extAttr->HICfgTimingDiv = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M; @@ -2359,7 +2359,7 @@ static DRXStatus_t InitHI(const pDRXDemodInstance_t demod) /* Delay = ( delay (nano seconds) * oscclk (kHz) )/ 1000 */ /* SDA brdige delay */ extAttr->HICfgBridgeDelay = - (u16_t) ((commonAttr->oscClockFreq / 1000) * HI_I2C_BRIDGE_DELAY) / + (u16) ((commonAttr->oscClockFreq / 1000) * HI_I2C_BRIDGE_DELAY) / 1000; /* Clipping */ if ((extAttr->HICfgBridgeDelay) > SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) { @@ -2416,9 +2416,9 @@ static DRXStatus_t GetDeviceCapabilities(pDRXDemodInstance_t demod) pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); pDRXJData_t extAttr = (pDRXJData_t) NULL; struct i2c_device_addr *devAddr = (struct i2c_device_addr *) (NULL); - u16_t sioPdrOhwCfg = 0; - u32_t sioTopJtagidLo = 0; - u16_t bid = 0; + u16 sioPdrOhwCfg = 0; + u32 sioTopJtagidLo = 0; + u16 bid = 0; commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; extAttr = (pDRXJData_t) demod->myExtAttr; @@ -2453,7 +2453,7 @@ static DRXStatus_t GetDeviceCapabilities(pDRXDemodInstance_t demod) Based on pinning v47 */ RR32(devAddr, SIO_TOP_JTAGID_LO__A, &sioTopJtagidLo); - extAttr->mfx = (u8_t) ((sioTopJtagidLo >> 29) & 0xF); + extAttr->mfx = (u8) ((sioTopJtagidLo >> 29) & 0xF); switch ((sioTopJtagidLo >> 12) & 0xFF) { case 0x31: @@ -2589,8 +2589,8 @@ rw_error: static DRXStatus_t PowerUpDevice(pDRXDemodInstance_t demod) { struct i2c_device_addr *devAddr = (struct i2c_device_addr *) (NULL); - u8_t data = 0; - u16_t retryCount = 0; + u8 data = 0; + u16 retryCount = 0; struct i2c_device_addr wakeUpAddr; devAddr = demod->myI2CDevAddr; @@ -2604,11 +2604,11 @@ static DRXStatus_t PowerUpDevice(pDRXDemodInstance_t demod) data = 0; DRXBSP_I2C_WriteRead(&wakeUpAddr, 1, &data, (struct i2c_device_addr *) (NULL), 0, - (pu8_t) (NULL)); + (u8 *) (NULL)); DRXBSP_HST_Sleep(10); retryCount++; } while ((DRXBSP_I2C_WriteRead - ((struct i2c_device_addr *) (NULL), 0, (pu8_t) (NULL), devAddr, 1, + ((struct i2c_device_addr *) (NULL), 0, (u8 *) (NULL), devAddr, 1, &data) != DRX_STS_OK) && (retryCount < DRXJ_MAX_RETRIES_POWERUP)); @@ -2641,15 +2641,15 @@ CtrlSetCfgMPEGOutput(pDRXDemodInstance_t demod, pDRXCfgMPEGOutput_t cfgData) struct i2c_device_addr *devAddr = (struct i2c_device_addr *) (NULL); pDRXJData_t extAttr = (pDRXJData_t) (NULL); pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); - u16_t fecOcRegMode = 0; - u16_t fecOcRegIprMode = 0; - u16_t fecOcRegIprInvert = 0; - u32_t maxBitRate = 0; - u32_t rcnRate = 0; - u32_t nrBits = 0; - u16_t sioPdrMdCfg = 0; + u16 fecOcRegMode = 0; + u16 fecOcRegIprMode = 0; + u16 fecOcRegIprInvert = 0; + u32 maxBitRate = 0; + u32 rcnRate = 0; + u32 nrBits = 0; + u16 sioPdrMdCfg = 0; /* data mask for the output data byte */ - u16_t InvertDataMask = + u16 InvertDataMask = FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M | FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M | FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M | @@ -2784,7 +2784,7 @@ CtrlSetCfgMPEGOutput(pDRXDemodInstance_t demod, pDRXCfgMPEGOutput_t cfgData) rcnRate = (Frac28 (maxBitRate, - (u32_t) (commonAttr->sysClockFreq / 8))) / + (u32) (commonAttr->sysClockFreq / 8))) / 188; break; default: @@ -2819,7 +2819,7 @@ CtrlSetCfgMPEGOutput(pDRXDemodInstance_t demod, pDRXCfgMPEGOutput_t cfgData) rcnRate = (Frac28 (maxBitRate, - (u32_t) (commonAttr->sysClockFreq / 8))) / + (u32) (commonAttr->sysClockFreq / 8))) / 204; break; default: @@ -2865,10 +2865,10 @@ CtrlSetCfgMPEGOutput(pDRXDemodInstance_t demod, pDRXCfgMPEGOutput_t cfgData) } if (cfgData->staticCLK == TRUE) { /* Static mode */ - u32_t dtoRate = 0; - u32_t bitRate = 0; - u16_t fecOcDtoBurstLen = 0; - u16_t fecOcDtoPeriod = 0; + u32 dtoRate = 0; + u32 bitRate = 0; + u16 fecOcDtoBurstLen = 0; + u16 fecOcDtoPeriod = 0; fecOcDtoBurstLen = FEC_OC_DTO_BURST_LEN__PRE; @@ -2881,7 +2881,7 @@ CtrlSetCfgMPEGOutput(pDRXDemodInstance_t demod, pDRXCfgMPEGOutput_t cfgData) break; case DRX_STANDARD_ITU_A: { - u32_t symbolRateTh = 6400000; + u32 symbolRateTh = 6400000; if (cfgData->insertRSByte == TRUE) { fecOcDtoBurstLen = 204; symbolRateTh = 5900000; @@ -2916,9 +2916,9 @@ CtrlSetCfgMPEGOutput(pDRXDemodInstance_t demod, pDRXCfgMPEGOutput_t cfgData) Frac28(bitRate, commonAttr->sysClockFreq * 1000); dtoRate >>= 3; WR16(devAddr, FEC_OC_DTO_RATE_HI__A, - (u16_t) ((dtoRate >> 16) & FEC_OC_DTO_RATE_HI__M)); + (u16) ((dtoRate >> 16) & FEC_OC_DTO_RATE_HI__M)); WR16(devAddr, FEC_OC_DTO_RATE_LO__A, - (u16_t) (dtoRate & FEC_OC_DTO_RATE_LO_RATE_LO__M)); + (u16) (dtoRate & FEC_OC_DTO_RATE_LO_RATE_LO__M)); WR16(devAddr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M | FEC_OC_DTO_MODE_OFFSET_ENABLE__M); @@ -3043,9 +3043,9 @@ CtrlGetCfgMPEGOutput(pDRXDemodInstance_t demod, pDRXCfgMPEGOutput_t cfgData) struct i2c_device_addr *devAddr = (struct i2c_device_addr *) (NULL); pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); DRXLockStatus_t lockStatus = DRX_NOT_LOCKED; - u32_t rateReg = 0; - u32_t data64Hi = 0; - u32_t data64Lo = 0; + u32 rateReg = 0; + u32 data64Hi = 0; + u32 data64Lo = 0; if (cfgData == NULL) { return (DRX_STS_INVALID_ARG); @@ -3099,9 +3099,9 @@ static DRXStatus_t SetMPEGTEIHandling(pDRXDemodInstance_t demod) { pDRXJData_t extAttr = (pDRXJData_t) (NULL); struct i2c_device_addr *devAddr = (struct i2c_device_addr *) (NULL); - u16_t fecOcDprMode = 0; - u16_t fecOcSncMode = 0; - u16_t fecOcEmsMode = 0; + u16 fecOcDprMode = 0; + u16 fecOcSncMode = 0; + u16 fecOcEmsMode = 0; devAddr = demod->myI2CDevAddr; extAttr = (pDRXJData_t) demod->myExtAttr; @@ -3147,7 +3147,7 @@ static DRXStatus_t BitReverseMPEGOutput(pDRXDemodInstance_t demod) { pDRXJData_t extAttr = (pDRXJData_t) (NULL); struct i2c_device_addr *devAddr = (struct i2c_device_addr *) (NULL); - u16_t fecOcIprMode = 0; + u16 fecOcIprMode = 0; devAddr = demod->myI2CDevAddr; extAttr = (pDRXJData_t) demod->myExtAttr; @@ -3211,7 +3211,7 @@ static DRXStatus_t SetMPEGStartWidth(pDRXDemodInstance_t demod) { pDRXJData_t extAttr = (pDRXJData_t) (NULL); struct i2c_device_addr *devAddr = (struct i2c_device_addr *) (NULL); - u16_t fecOcCommMb = 0; + u16 fecOcCommMb = 0; pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) NULL; devAddr = demod->myI2CDevAddr; @@ -3300,7 +3300,7 @@ CtrlGetCfgMpegOutputMisc(pDRXDemodInstance_t demod, pDRXJCfgMpegOutputMisc_t cfgData) { pDRXJData_t extAttr = (pDRXJData_t) (NULL); - u16_t data = 0; + u16 data = 0; if (cfgData == NULL) { return (DRX_STS_INVALID_ARG); @@ -3340,7 +3340,7 @@ rw_error: static DRXStatus_t CtrlGetCfgHwCfg(pDRXDemodInstance_t demod, pDRXJCfgHwCfg_t cfgData) { - u16_t data = 0; + u16 data = 0; pDRXJData_t extAttr = (pDRXJData_t) (NULL); if (cfgData == NULL) { @@ -3534,8 +3534,8 @@ static DRXStatus_t CtrlUIOWrite(pDRXDemodInstance_t demod, pDRXUIOData_t UIOData) { pDRXJData_t extAttr = (pDRXJData_t) (NULL); - u16_t pinCfgValue = 0; - u16_t value = 0; + u16 pinCfgValue = 0; + u16 value = 0; if ((UIOData == NULL) || (demod == NULL)) { return DRX_STS_INVALID_ARG; @@ -3679,8 +3679,8 @@ rw_error: static DRXStatus_t CtrlUIORead(pDRXDemodInstance_t demod, pDRXUIOData_t UIOData) { pDRXJData_t extAttr = (pDRXJData_t) (NULL); - u16_t pinCfgValue = 0; - u16_t value = 0; + u16 pinCfgValue = 0; + u16 value = 0; if ((UIOData == NULL) || (demod == NULL)) { return DRX_STS_INVALID_ARG; @@ -3826,7 +3826,7 @@ static DRXStatus_t CtrlI2CBridge(pDRXDemodInstance_t demod, pBool_t bridgeClosed) { DRXJHiCmd_t hiCmd; - u16_t result = 0; + u16 result = 0; /* check arguments */ if (bridgeClosed == NULL) { @@ -3860,7 +3860,7 @@ CtrlI2CBridge(pDRXDemodInstance_t demod, pBool_t bridgeClosed) */ static DRXStatus_t SmartAntInit(pDRXDemodInstance_t demod) { - u16_t data = 0; + u16 data = 0; pDRXJData_t extAttr = NULL; struct i2c_device_addr *devAddr = NULL; DRXUIOCfg_t UIOCfg = { DRX_UIO1, DRX_UIO_MODE_FIRMWARE_SMA }; @@ -3906,8 +3906,8 @@ CtrlSetCfgSmartAnt(pDRXDemodInstance_t demod, pDRXJCfgSmartAnt_t smartAnt) { pDRXJData_t extAttr = NULL; struct i2c_device_addr *devAddr = NULL; - u16_t data = 0; - u32_t startTime = 0; + u16 data = 0; + u32 startTime = 0; static Bool_t bitInverted = FALSE; devAddr = demod->myI2CDevAddr; @@ -3991,8 +3991,8 @@ rw_error: static DRXStatus_t SCUCommand(struct i2c_device_addr *devAddr, pDRXJSCUCmd_t cmd) { - u16_t curCmd = 0; - u32_t startTime = 0; + u16 curCmd = 0; + u32 startTime = 0; /* Check param */ if (cmd == NULL) @@ -4037,7 +4037,7 @@ static DRXStatus_t SCUCommand(struct i2c_device_addr *devAddr, pDRXJSCUCmd_t cmd /* read results */ if ((cmd->resultLen > 0) && (cmd->result != NULL)) { - s16_t err; + s16 err; switch (cmd->resultLen) { case 4: @@ -4060,10 +4060,10 @@ static DRXStatus_t SCUCommand(struct i2c_device_addr *devAddr, pDRXJSCUCmd_t cmd err = cmd->result[0]; /* check a few fixed error codes */ - if ((err == (s16_t) SCU_RAM_PARAM_0_RESULT_UNKSTD) - || (err == (s16_t) SCU_RAM_PARAM_0_RESULT_UNKCMD) - || (err == (s16_t) SCU_RAM_PARAM_0_RESULT_INVPAR) - || (err == (s16_t) SCU_RAM_PARAM_0_RESULT_SIZE) + if ((err == (s16) SCU_RAM_PARAM_0_RESULT_UNKSTD) + || (err == (s16) SCU_RAM_PARAM_0_RESULT_UNKCMD) + || (err == (s16) SCU_RAM_PARAM_0_RESULT_INVPAR) + || (err == (s16) SCU_RAM_PARAM_0_RESULT_SIZE) ) { return DRX_STS_INVALID_ARG; } @@ -4095,12 +4095,12 @@ rw_error: */ #define ADDR_AT_SCU_SPACE(x) ((x - 0x82E000) * 2) static -DRXStatus_t DRXJ_DAP_SCU_AtomicReadWriteBlock(struct i2c_device_addr *devAddr, DRXaddr_t addr, u16_t datasize, /* max 30 bytes because the limit of SCU parameter */ - pu8_t data, Bool_t readFlag) +DRXStatus_t DRXJ_DAP_SCU_AtomicReadWriteBlock(struct i2c_device_addr *devAddr, DRXaddr_t addr, u16 datasize, /* max 30 bytes because the limit of SCU parameter */ + u8 *data, Bool_t readFlag) { DRXJSCUCmd_t scuCmd; - u16_t setParamParameters[15]; - u16_t cmdResult[15]; + u16 setParamParameters[15]; + u16 cmdResult[15]; /* Parameter check */ if ((data == NULL) || @@ -4109,7 +4109,7 @@ DRXStatus_t DRXJ_DAP_SCU_AtomicReadWriteBlock(struct i2c_device_addr *devAddr, D return (DRX_STS_INVALID_ARG); } - setParamParameters[1] = (u16_t) ADDR_AT_SCU_SPACE(addr); + setParamParameters[1] = (u16) ADDR_AT_SCU_SPACE(addr); if (readFlag) { /* read */ setParamParameters[0] = ((~(0x0080)) & datasize); scuCmd.parameterLen = 2; @@ -4137,8 +4137,8 @@ DRXStatus_t DRXJ_DAP_SCU_AtomicReadWriteBlock(struct i2c_device_addr *devAddr, D int i = 0; /* read data from buffer */ for (i = 0; i < (datasize / 2); i++) { - data[2 * i] = (u8_t) (scuCmd.result[i + 2] & 0xFF); - data[(2 * i) + 1] = (u8_t) (scuCmd.result[i + 2] >> 8); + data[2 * i] = (u8) (scuCmd.result[i + 2] & 0xFF); + data[(2 * i) + 1] = (u8) (scuCmd.result[i + 2] >> 8); } } @@ -4158,11 +4158,11 @@ rw_error: static DRXStatus_t DRXJ_DAP_SCU_AtomicReadReg16(struct i2c_device_addr *devAddr, DRXaddr_t addr, - pu16_t data, DRXflags_t flags) + u16 *data, DRXflags_t flags) { - u8_t buf[2]; + u8 buf[2]; DRXStatus_t rc = DRX_STS_ERROR; - u16_t word = 0; + u16 word = 0; if (!data) { return DRX_STS_INVALID_ARG; @@ -4170,7 +4170,7 @@ DRXStatus_t DRXJ_DAP_SCU_AtomicReadReg16(struct i2c_device_addr *devAddr, rc = DRXJ_DAP_SCU_AtomicReadWriteBlock(devAddr, addr, 2, buf, TRUE); - word = (u16_t) (buf[0] + (buf[1] << 8)); + word = (u16) (buf[0] + (buf[1] << 8)); *data = word; @@ -4185,13 +4185,13 @@ DRXStatus_t DRXJ_DAP_SCU_AtomicReadReg16(struct i2c_device_addr *devAddr, static DRXStatus_t DRXJ_DAP_SCU_AtomicWriteReg16(struct i2c_device_addr *devAddr, DRXaddr_t addr, - u16_t data, DRXflags_t flags) + u16 data, DRXflags_t flags) { - u8_t buf[2]; + u8 buf[2]; DRXStatus_t rc = DRX_STS_ERROR; - buf[0] = (u8_t) (data & 0xff); - buf[1] = (u8_t) ((data >> 8) & 0xff); + buf[0] = (u8) (data & 0xff); + buf[1] = (u8) ((data >> 8) & 0xff); rc = DRXJ_DAP_SCU_AtomicReadWriteBlock(devAddr, addr, 2, buf, FALSE); @@ -4207,9 +4207,9 @@ CtrlI2CWriteRead(pDRXDemodInstance_t demod, pDRXI2CData_t i2cData) DRXStatus_t TunerI2CWriteRead(pTUNERInstance_t tuner, struct i2c_device_addr *wDevAddr, - u16_t wCount, - pu8_t wData, - struct i2c_device_addr *rDevAddr, u16_t rCount, pu8_t rData) + u16 wCount, + u8 *wData, + struct i2c_device_addr *rDevAddr, u16 rCount, u8 *rData) { pDRXDemodInstance_t demod; DRXI2CData_t i2cData = @@ -4230,9 +4230,9 @@ TunerI2CWriteRead(pTUNERInstance_t tuner, * \retval DRX_STS_ERROR Failure: I2C error * */ -static DRXStatus_t ADCSyncMeasurement(pDRXDemodInstance_t demod, pu16_t count) +static DRXStatus_t ADCSyncMeasurement(pDRXDemodInstance_t demod, u16 *count) { - u16_t data = 0; + u16 data = 0; struct i2c_device_addr *devAddr = NULL; devAddr = demod->myI2CDevAddr; @@ -4277,7 +4277,7 @@ rw_error: static DRXStatus_t ADCSynchronization(pDRXDemodInstance_t demod) { - u16_t count = 0; + u16 count = 0; struct i2c_device_addr *devAddr = NULL; devAddr = demod->myI2CDevAddr; @@ -4286,7 +4286,7 @@ static DRXStatus_t ADCSynchronization(pDRXDemodInstance_t demod) if (count == 1) { /* Try sampling on a diffrent edge */ - u16_t clkNeg = 0; + u16 clkNeg = 0; RR16(devAddr, IQM_AF_CLKNEG__A, &clkNeg); @@ -4314,7 +4314,7 @@ rw_error: */ static DRXStatus_t IQMSetAf(pDRXDemodInstance_t demod, Bool_t active) { - u16_t data = 0; + u16 data = 0; struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; @@ -4503,8 +4503,8 @@ CtrlGetCfgPdrSafeMode(pDRXDemodInstance_t demod, pBool_t enabled) */ static DRXStatus_t CtrlValidateUCode(pDRXDemodInstance_t demod) { - u32_t mcDev, mcPatch; - u16_t verType; + u32 mcDev, mcPatch; + u16 verType; /* Check device. * Disallow microcode if: @@ -4556,21 +4556,21 @@ static DRXStatus_t InitAGC(pDRXDemodInstance_t demod) pDRXJData_t extAttr = NULL; pDRXJCfgAgc_t pAgcRfSettings = NULL; pDRXJCfgAgc_t pAgcIfSettings = NULL; - u16_t IngainTgtMax = 0; - u16_t clpDirTo = 0; - u16_t snsSumMax = 0; - u16_t clpSumMax = 0; - u16_t snsDirTo = 0; - u16_t kiInnergainMin = 0; - u16_t agcKi = 0; - u16_t kiMax = 0; - u16_t ifIaccuHiTgtMin = 0; - u16_t data = 0; - u16_t agcKiDgain = 0; - u16_t kiMin = 0; - u16_t clpCtrlMode = 0; - u16_t agcRf = 0; - u16_t agcIf = 0; + u16 IngainTgtMax = 0; + u16 clpDirTo = 0; + u16 snsSumMax = 0; + u16 clpSumMax = 0; + u16 snsDirTo = 0; + u16 kiInnergainMin = 0; + u16 agcKi = 0; + u16 kiMax = 0; + u16 ifIaccuHiTgtMin = 0; + u16 data = 0; + u16 agcKiDgain = 0; + u16 kiMin = 0; + u16 clpCtrlMode = 0; + u16 agcRf = 0; + u16 agcIf = 0; devAddr = demod->myI2CDevAddr; commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; extAttr = (pDRXJData_t) demod->myExtAttr; @@ -4578,10 +4578,10 @@ static DRXStatus_t InitAGC(pDRXDemodInstance_t demod) switch (extAttr->standard) { case DRX_STANDARD_8VSB: clpSumMax = 1023; - clpDirTo = (u16_t) (-9); + clpDirTo = (u16) (-9); snsSumMax = 1023; - snsDirTo = (u16_t) (-9); - kiInnergainMin = (u16_t) (-32768); + snsDirTo = (u16) (-9); + kiInnergainMin = (u16) (-32768); kiMax = 0x032C; agcKiDgain = 0xC; ifIaccuHiTgtMin = 2047; @@ -4610,9 +4610,9 @@ static DRXStatus_t InitAGC(pDRXDemodInstance_t demod) case DRX_STANDARD_ITU_B: IngainTgtMax = 5119; clpSumMax = 1023; - clpDirTo = (u16_t) (-5); + clpDirTo = (u16) (-5); snsSumMax = 127; - snsDirTo = (u16_t) (-3); + snsDirTo = (u16) (-3); kiInnergainMin = 0; kiMax = 0x0657; ifIaccuHiTgtMin = 2047; @@ -4642,13 +4642,13 @@ static DRXStatus_t InitAGC(pDRXDemodInstance_t demod) case DRX_STANDARD_FM: clpSumMax = 1023; snsSumMax = 1023; - kiInnergainMin = (u16_t) (-32768); + kiInnergainMin = (u16) (-32768); ifIaccuHiTgtMin = 2047; agcKiDgain = 0x7; kiMin = 0x0225; kiMax = 0x0547; - clpDirTo = (u16_t) (-9); - snsDirTo = (u16_t) (-9); + clpDirTo = (u16) (-9); + snsDirTo = (u16) (-9); IngainTgtMax = 9000; clpCtrlMode = 1; pAgcIfSettings = &(extAttr->atvIfAgcCfg); @@ -4661,16 +4661,16 @@ static DRXStatus_t InitAGC(pDRXDemodInstance_t demod) case DRX_STANDARD_PAL_SECAM_I: clpSumMax = 1023; snsSumMax = 1023; - kiInnergainMin = (u16_t) (-32768); + kiInnergainMin = (u16) (-32768); ifIaccuHiTgtMin = 2047; agcKiDgain = 0x7; kiMin = 0x0225; kiMax = 0x0547; - clpDirTo = (u16_t) (-9); + clpDirTo = (u16) (-9); IngainTgtMax = 9000; pAgcIfSettings = &(extAttr->atvIfAgcCfg); pAgcRfSettings = &(extAttr->atvRfAgcCfg); - snsDirTo = (u16_t) (-9); + snsDirTo = (u16) (-9); clpCtrlMode = 1; WR16(devAddr, SCU_RAM_AGC_INGAIN_TGT__A, pAgcIfSettings->top); break; @@ -4678,13 +4678,13 @@ static DRXStatus_t InitAGC(pDRXDemodInstance_t demod) case DRX_STANDARD_PAL_SECAM_LP: clpSumMax = 1023; snsSumMax = 1023; - kiInnergainMin = (u16_t) (-32768); + kiInnergainMin = (u16) (-32768); ifIaccuHiTgtMin = 2047; agcKiDgain = 0x7; kiMin = 0x0225; kiMax = 0x0547; - clpDirTo = (u16_t) (-9); - snsDirTo = (u16_t) (-9); + clpDirTo = (u16) (-9); + snsDirTo = (u16) (-9); IngainTgtMax = 9000; clpCtrlMode = 1; pAgcIfSettings = &(extAttr->atvIfAgcCfg); @@ -4768,7 +4768,7 @@ SetFrequency(pDRXDemodInstance_t demod, DRXFrequency_t rfFreqResidual = 0; DRXFrequency_t adcFreq = 0; DRXFrequency_t intermediateFreq = 0; - u32_t iqmFsRateOfs = 0; + u32 iqmFsRateOfs = 0; pDRXJData_t extAttr = NULL; Bool_t adcFlip = TRUE; Bool_t selectPosImage = FALSE; @@ -4865,14 +4865,14 @@ rw_error: #define DRXJ_RFAGC_MAX 0x3fff #define DRXJ_RFAGC_MIN 0x800 -static DRXStatus_t GetSigStrength(pDRXDemodInstance_t demod, pu16_t sigStrength) +static DRXStatus_t GetSigStrength(pDRXDemodInstance_t demod, u16 *sigStrength) { - u16_t rfGain = 0; - u16_t ifGain = 0; - u16_t ifAgcSns = 0; - u16_t ifAgcTop = 0; - u16_t rfAgcMax = 0; - u16_t rfAgcMin = 0; + u16 rfGain = 0; + u16 ifGain = 0; + u16 ifAgcSns = 0; + u16 ifAgcTop = 0; + u16 rfAgcMax = 0; + u16 rfAgcMin = 0; pDRXJData_t extAttr = NULL; struct i2c_device_addr *devAddr = NULL; @@ -4924,11 +4924,11 @@ rw_error: * \retval DRX_STS_ERROR Erroneous data, sigStrength contains invalid data. */ #ifdef DRXJ_SIGNAL_ACCUM_ERR -static DRXStatus_t GetAccPktErr(pDRXDemodInstance_t demod, pu16_t packetErr) +static DRXStatus_t GetAccPktErr(pDRXDemodInstance_t demod, u16 *packetErr) { - static u16_t pktErr = 0; - static u16_t lastPktErr = 0; - u16_t data = 0; + static u16 pktErr = 0; + static u16 lastPktErr = 0; + u16 data = 0; pDRXJData_t extAttr = NULL; struct i2c_device_addr *devAddr = NULL; @@ -4969,7 +4969,7 @@ static DRXStatus_t CtrlSetCfgResetPktErr(pDRXDemodInstance_t demod) { #ifdef DRXJ_SIGNAL_ACCUM_ERR pDRXJData_t extAttr = NULL; - u16_t packetError = 0; + u16 packetError = 0; extAttr = (pDRXJData_t) demod->myExtAttr; extAttr->resetPktErrAcc = TRUE; @@ -4987,10 +4987,10 @@ rw_error: * \brief Get symbol rate offset in QAM & 8VSB mode * \return Error code */ -static DRXStatus_t GetSTRFreqOffset(pDRXDemodInstance_t demod, s32_t * STRFreq) +static DRXStatus_t GetSTRFreqOffset(pDRXDemodInstance_t demod, s32 *STRFreq) { - u32_t symbolFrequencyRatio = 0; - u32_t symbolNomFrequencyRatio = 0; + u32 symbolFrequencyRatio = 0; + u32 symbolNomFrequencyRatio = 0; DRXStandard_t standard = DRX_STANDARD_UNKNOWN; struct i2c_device_addr *devAddr = NULL; @@ -5025,15 +5025,15 @@ rw_error: * \brief Get the value of CTLFreq in QAM & ATSC mode * \return Error code */ -static DRXStatus_t GetCTLFreqOffset(pDRXDemodInstance_t demod, s32_t * CTLFreq) +static DRXStatus_t GetCTLFreqOffset(pDRXDemodInstance_t demod, s32 *CTLFreq) { DRXFrequency_t samplingFrequency = 0; - s32_t currentFrequency = 0; - s32_t nominalFrequency = 0; - s32_t carrierFrequencyShift = 0; - s32_t sign = 1; - u32_t data64Hi = 0; - u32_t data64Lo = 0; + s32 currentFrequency = 0; + s32 nominalFrequency = 0; + s32 carrierFrequencyShift = 0; + s32 sign = 1; + u32 data64Hi = 0; + u32 data64Lo = 0; pDRXJData_t extAttr = NULL; pDRXCommonAttr_t commonAttr = NULL; struct i2c_device_addr *devAddr = NULL; @@ -5046,7 +5046,7 @@ static DRXStatus_t GetCTLFreqOffset(pDRXDemodInstance_t demod, s32_t * CTLFreq) /* both registers are sign extended */ nominalFrequency = extAttr->iqmFsRateOfs; - ARR32(devAddr, IQM_FS_RATE_LO__A, (pu32_t) & currentFrequency); + ARR32(devAddr, IQM_FS_RATE_LO__A, (u32 *) & currentFrequency); if (extAttr->posImage == TRUE) { /* negative image */ @@ -5065,7 +5065,7 @@ static DRXStatus_t GetCTLFreqOffset(pDRXDemodInstance_t demod, s32_t * CTLFreq) /* *CTLFreq = carrierFrequencyShift * 50.625e6 / (1 << 28); */ Mult32(carrierFrequencyShift, samplingFrequency, &data64Hi, &data64Lo); *CTLFreq = - (s32_t) ((((data64Lo >> 28) & 0xf) | (data64Hi << 4)) * sign); + (s32) ((((data64Lo >> 28) & 0xf) | (data64Hi << 4)) * sign); return (DRX_STS_OK); rw_error: @@ -5109,7 +5109,7 @@ SetAgcRf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings, Bool_t atomic) DRXJ_ISQAMSTD(agcSettings->standard)) || (DRXJ_ISATVSTD(extAttr->standard) && DRXJ_ISATVSTD(agcSettings->standard))) { - u16_t data = 0; + u16 data = 0; switch (agcSettings->ctrlMode) { case DRX_AGC_CTRL_AUTO: @@ -5348,7 +5348,7 @@ SetAgcIf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings, Bool_t atomic) DRXJ_ISQAMSTD(agcSettings->standard)) || (DRXJ_ISATVSTD(extAttr->standard) && DRXJ_ISATVSTD(agcSettings->standard))) { - u16_t data = 0; + u16 data = 0; switch (agcSettings->ctrlMode) { case DRX_AGC_CTRL_AUTO: @@ -5575,7 +5575,7 @@ rw_error: */ static DRXStatus_t SetIqmAf(pDRXDemodInstance_t demod, Bool_t active) { - u16_t data = 0; + u16 data = 0; struct i2c_device_addr *devAddr = NULL; devAddr = demod->myI2CDevAddr; @@ -5630,7 +5630,7 @@ static DRXStatus_t PowerDownVSB(pDRXDemodInstance_t demod, Bool_t primary) /* *parameter */ NULL, /* *result */ NULL }; - u16_t cmdResult = 0; + u16 cmdResult = 0; pDRXJData_t extAttr = NULL; DRXCfgMPEGOutput_t cfgMPEGOutput; @@ -5680,7 +5680,7 @@ static DRXStatus_t SetVSBLeakNGain(pDRXDemodInstance_t demod) { struct i2c_device_addr *devAddr = NULL; - const u8_t vsb_ffe_leak_gain_ram0[] = { + const u8 vsb_ffe_leak_gain_ram0[] = { DRXJ_16TO8(0x8), /* FFETRAINLKRATIO1 */ DRXJ_16TO8(0x8), /* FFETRAINLKRATIO2 */ DRXJ_16TO8(0x8), /* FFETRAINLKRATIO3 */ @@ -5811,7 +5811,7 @@ static DRXStatus_t SetVSBLeakNGain(pDRXDemodInstance_t demod) DRXJ_16TO8(0x1010) /* FIRRCA1GAIN8 */ }; - const u8_t vsb_ffe_leak_gain_ram1[] = { + const u8 vsb_ffe_leak_gain_ram1[] = { DRXJ_16TO8(0x1010), /* FIRRCA1GAIN9 */ DRXJ_16TO8(0x0808), /* FIRRCA1GAIN10 */ DRXJ_16TO8(0x0808), /* FIRRCA1GAIN11 */ @@ -5870,9 +5870,9 @@ static DRXStatus_t SetVSBLeakNGain(pDRXDemodInstance_t demod) devAddr = demod->myI2CDevAddr; WRB(devAddr, VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__A, - sizeof(vsb_ffe_leak_gain_ram0), ((pu8_t) vsb_ffe_leak_gain_ram0)); + sizeof(vsb_ffe_leak_gain_ram0), ((u8 *) vsb_ffe_leak_gain_ram0)); WRB(devAddr, VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__A, - sizeof(vsb_ffe_leak_gain_ram1), ((pu8_t) vsb_ffe_leak_gain_ram1)); + sizeof(vsb_ffe_leak_gain_ram1), ((u8 *) vsb_ffe_leak_gain_ram1)); return (DRX_STS_OK); rw_error: @@ -5889,12 +5889,12 @@ rw_error: static DRXStatus_t SetVSB(pDRXDemodInstance_t demod) { struct i2c_device_addr *devAddr = NULL; - u16_t cmdResult = 0; - u16_t cmdParam = 0; + u16 cmdResult = 0; + u16 cmdParam = 0; pDRXCommonAttr_t commonAttr = NULL; DRXJSCUCmd_t cmdSCU; pDRXJData_t extAttr = NULL; - const u8_t vsb_taps_re[] = { + const u8 vsb_taps_re[] = { DRXJ_16TO8(-2), /* re0 */ DRXJ_16TO8(4), /* re1 */ DRXJ_16TO8(1), /* re2 */ @@ -5966,9 +5966,9 @@ static DRXStatus_t SetVSB(pDRXDemodInstance_t demod) WR16(devAddr, IQM_CF_POW_MEAS_LEN__A, 1); WRB(devAddr, IQM_CF_TAP_RE0__A, sizeof(vsb_taps_re), - ((pu8_t) vsb_taps_re)); + ((u8 *) vsb_taps_re)); WRB(devAddr, IQM_CF_TAP_IM0__A, sizeof(vsb_taps_re), - ((pu8_t) vsb_taps_re)); + ((u8 *) vsb_taps_re)); WR16(devAddr, VSB_TOP_BNTHRESH__A, 330); /* set higher threshold */ WR16(devAddr, VSB_TOP_CLPLASTNUM__A, 90); /* burst detection on */ @@ -5980,7 +5980,7 @@ static DRXStatus_t SetVSB(pDRXDemodInstance_t demod) /* Initialize the FEC Subsystem */ WR16(devAddr, FEC_TOP_ANNEX__A, FEC_TOP_ANNEX_D); { - u16_t fecOcSncMode = 0; + u16 fecOcSncMode = 0; RR16(devAddr, FEC_OC_SNC_MODE__A, &fecOcSncMode); /* output data even when not locked */ WR16(devAddr, FEC_OC_SNC_MODE__A, @@ -5994,7 +5994,7 @@ static DRXStatus_t SetVSB(pDRXDemodInstance_t demod) WR16(devAddr, VSB_TOP_SNRTH_PT__A, 0xD4); /* no transparent, no A&C framing; parity is set in mpegoutput */ { - u16_t fecOcRegMode = 0; + u16 fecOcRegMode = 0; RR16(devAddr, FEC_OC_MODE__A, &fecOcRegMode); WR16(devAddr, FEC_OC_MODE__A, fecOcRegMode & (~(FEC_OC_MODE_TRANSPARENT__M @@ -6101,17 +6101,17 @@ rw_error: } /** -* \fn static short GetVSBPostRSPckErr(struct i2c_device_addr * devAddr, pu16_t PckErrs) +* \fn static short GetVSBPostRSPckErr(struct i2c_device_addr * devAddr, u16 *PckErrs) * \brief Get the values of packet error in 8VSB mode * \return Error code */ -static DRXStatus_t GetVSBPostRSPckErr(struct i2c_device_addr *devAddr, pu16_t pckErrs) +static DRXStatus_t GetVSBPostRSPckErr(struct i2c_device_addr *devAddr, u16 *pckErrs) { - u16_t data = 0; - u16_t period = 0; - u16_t prescale = 0; - u16_t packetErrorsMant = 0; - u16_t packetErrorsExp = 0; + u16 data = 0; + u16 period = 0; + u16 prescale = 0; + u16 packetErrorsMant = 0; + u16 packetErrorsExp = 0; RR16(devAddr, FEC_RS_NR_FAILURES__A, &data); packetErrorsMant = data & FEC_RS_NR_FAILURES_FIXED_MANT__M; @@ -6123,7 +6123,7 @@ static DRXStatus_t GetVSBPostRSPckErr(struct i2c_device_addr *devAddr, pu16_t pc /* 77.3 us is time for per packet */ CHK_ZERO(period * prescale); *pckErrs = - (u16_t) FracTimes1e6(packetErrorsMant * (1 << packetErrorsExp), + (u16) FracTimes1e6(packetErrorsMant * (1 << packetErrorsExp), (period * prescale * 77)); return (DRX_STS_OK); @@ -6132,17 +6132,17 @@ rw_error: } /** -* \fn static short GetVSBBer(struct i2c_device_addr * devAddr, pu32_t ber) +* \fn static short GetVSBBer(struct i2c_device_addr * devAddr, u32 *ber) * \brief Get the values of ber in VSB mode * \return Error code */ -static DRXStatus_t GetVSBpostViterbiBer(struct i2c_device_addr *devAddr, pu32_t ber) +static DRXStatus_t GetVSBpostViterbiBer(struct i2c_device_addr *devAddr, u32 *ber) { - u16_t data = 0; - u16_t period = 0; - u16_t prescale = 0; - u16_t bitErrorsMant = 0; - u16_t bitErrorsExp = 0; + u16 data = 0; + u16 period = 0; + u16 prescale = 0; + u16 bitErrorsMant = 0; + u16 bitErrorsExp = 0; RR16(devAddr, FEC_RS_NR_BIT_ERRORS__A, &data); period = FEC_RS_MEASUREMENT_PERIOD; @@ -6170,13 +6170,13 @@ rw_error: } /** -* \fn static short GetVSBpreViterbiBer(struct i2c_device_addr * devAddr, pu32_t ber) +* \fn static short GetVSBpreViterbiBer(struct i2c_device_addr * devAddr, u32 *ber) * \brief Get the values of ber in VSB mode * \return Error code */ -static DRXStatus_t GetVSBpreViterbiBer(struct i2c_device_addr *devAddr, pu32_t ber) +static DRXStatus_t GetVSBpreViterbiBer(struct i2c_device_addr *devAddr, u32 *ber) { - u16_t data = 0; + u16 data = 0; RR16(devAddr, VSB_TOP_NR_SYM_ERRS__A, &data); *ber = @@ -6189,17 +6189,17 @@ rw_error: } /** -* \fn static short GetVSBSymbErr(struct i2c_device_addr * devAddr, pu32_t ber) +* \fn static short GetVSBSymbErr(struct i2c_device_addr * devAddr, u32 *ber) * \brief Get the values of ber in VSB mode * \return Error code */ -static DRXStatus_t GetVSBSymbErr(struct i2c_device_addr *devAddr, pu32_t ser) +static DRXStatus_t GetVSBSymbErr(struct i2c_device_addr *devAddr, u32 *ser) { - u16_t data = 0; - u16_t period = 0; - u16_t prescale = 0; - u16_t symbErrorsMant = 0; - u16_t symbErrorsExp = 0; + u16 data = 0; + u16 period = 0; + u16 prescale = 0; + u16 symbErrorsMant = 0; + u16 symbErrorsExp = 0; RR16(devAddr, FEC_RS_NR_SYMBOL_ERRORS__A, &data); period = FEC_RS_MEASUREMENT_PERIOD; @@ -6210,7 +6210,7 @@ static DRXStatus_t GetVSBSymbErr(struct i2c_device_addr *devAddr, pu32_t ser) >> FEC_RS_NR_SYMBOL_ERRORS_EXP__B; CHK_ZERO(period * prescale); - *ser = (u32_t) FracTimes1e6((symbErrorsMant << symbErrorsExp) * 1000, + *ser = (u32) FracTimes1e6((symbErrorsMant << symbErrorsExp) * 1000, (period * prescale * 77318)); return (DRX_STS_OK); @@ -6219,17 +6219,17 @@ rw_error: } /** -* \fn static DRXStatus_t GetVSBMER(struct i2c_device_addr * devAddr, pu16_t mer) +* \fn static DRXStatus_t GetVSBMER(struct i2c_device_addr * devAddr, u16 *mer) * \brief Get the values of MER * \return Error code */ -static DRXStatus_t GetVSBMER(struct i2c_device_addr *devAddr, pu16_t mer) +static DRXStatus_t GetVSBMER(struct i2c_device_addr *devAddr, u16 *mer) { - u16_t dataHi = 0; + u16 dataHi = 0; RR16(devAddr, VSB_TOP_ERR_ENERGY_H__A, &dataHi); *mer = - (u16_t) (Log10Times100(21504) - Log10Times100((dataHi << 6) / 52)); + (u16) (Log10Times100(21504) - Log10Times100((dataHi << 6) / 52)); return (DRX_STS_OK); rw_error: @@ -6250,10 +6250,10 @@ CtrlGetVSBConstel(pDRXDemodInstance_t demod, pDRXComplex_t complexNr) { struct i2c_device_addr *devAddr = NULL; /**< device address */ - u16_t vsbTopCommMb = 0; /**< VSB SL MB configuration */ - u16_t vsbTopCommMbInit = 0; /**< VSB SL MB intial configuration */ - u16_t re = 0; /**< constellation Re part */ - u32_t data = 0; + u16 vsbTopCommMb = 0; /**< VSB SL MB configuration */ + u16 vsbTopCommMbInit = 0; /**< VSB SL MB intial configuration */ + u16 re = 0; /**< constellation Re part */ + u32 data = 0; /* read device info */ devAddr = demod->myI2CDevAddr; @@ -6278,7 +6278,7 @@ CtrlGetVSBConstel(pDRXDemodInstance_t demod, pDRXComplex_t complexNr) /* read data */ RR32(devAddr, FEC_OC_OCR_GRAB_RD1__A, &data); - re = (u16_t) (((data >> 10) & 0x300) | ((data >> 2) & 0xff)); + re = (u16) (((data >> 10) & 0x300) | ((data >> 2) & 0xff)); if (re & 0x0200) { re |= 0xfc00; } @@ -6318,7 +6318,7 @@ static DRXStatus_t PowerDownQAM(pDRXDemodInstance_t demod, Bool_t primary) /* *parameter */ NULL, /* *result */ NULL }; - u16_t cmdResult = 0; + u16 cmdResult = 0; struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; DRXCfgMPEGOutput_t cfgMPEGOutput; @@ -6382,20 +6382,20 @@ rw_error: #ifndef DRXJ_VSB_ONLY static DRXStatus_t SetQAMMeasurement(pDRXDemodInstance_t demod, - DRXConstellation_t constellation, u32_t symbolRate) + DRXConstellation_t constellation, u32 symbolRate) { struct i2c_device_addr *devAddr = NULL; /* device address for I2C writes */ pDRXJData_t extAttr = NULL; /* Global data container for DRXJ specif data */ - u32_t fecBitsDesired = 0; /* BER accounting period */ - u16_t fecRsPlen = 0; /* defines RS BER measurement period */ - u16_t fecRsPrescale = 0; /* ReedSolomon Measurement Prescale */ - u32_t fecRsPeriod = 0; /* Value for corresponding I2C register */ - u32_t fecRsBitCnt = 0; /* Actual precise amount of bits */ - u32_t fecOcSncFailPeriod = 0; /* Value for corresponding I2C register */ - u32_t qamVdPeriod = 0; /* Value for corresponding I2C register */ - u32_t qamVdBitCnt = 0; /* Actual precise amount of bits */ - u16_t fecVdPlen = 0; /* no of trellis symbols: VD SER measur period */ - u16_t qamVdPrescale = 0; /* Viterbi Measurement Prescale */ + u32 fecBitsDesired = 0; /* BER accounting period */ + u16 fecRsPlen = 0; /* defines RS BER measurement period */ + u16 fecRsPrescale = 0; /* ReedSolomon Measurement Prescale */ + u32 fecRsPeriod = 0; /* Value for corresponding I2C register */ + u32 fecRsBitCnt = 0; /* Actual precise amount of bits */ + u32 fecOcSncFailPeriod = 0; /* Value for corresponding I2C register */ + u32 qamVdPeriod = 0; /* Value for corresponding I2C register */ + u32 qamVdBitCnt = 0; /* Actual precise amount of bits */ + u16 fecVdPlen = 0; /* no of trellis symbols: VD SER measur period */ + u16 qamVdPrescale = 0; /* Viterbi Measurement Prescale */ devAddr = demod->myI2CDevAddr; extAttr = (pDRXJData_t) demod->myExtAttr; @@ -6476,10 +6476,10 @@ SetQAMMeasurement(pDRXDemodInstance_t demod, return (DRX_STS_INVALID_ARG); } - WR16(devAddr, FEC_OC_SNC_FAIL_PERIOD__A, (u16_t) fecOcSncFailPeriod); - WR16(devAddr, FEC_RS_MEASUREMENT_PERIOD__A, (u16_t) fecRsPeriod); + WR16(devAddr, FEC_OC_SNC_FAIL_PERIOD__A, (u16) fecOcSncFailPeriod); + WR16(devAddr, FEC_RS_MEASUREMENT_PERIOD__A, (u16) fecRsPeriod); WR16(devAddr, FEC_RS_MEASUREMENT_PRESCALE__A, fecRsPrescale); - extAttr->fecRsPeriod = (u16_t) fecRsPeriod; + extAttr->fecRsPeriod = (u16) fecRsPeriod; extAttr->fecRsPrescale = fecRsPrescale; WR32(devAddr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0); WR16(devAddr, SCU_RAM_FEC_MEAS_COUNT__A, 0); @@ -6524,9 +6524,9 @@ SetQAMMeasurement(pDRXDemodInstance_t demod, qamVdBitCnt *= qamVdPeriod; WR16(devAddr, QAM_VD_MEASUREMENT_PERIOD__A, - (u16_t) qamVdPeriod); + (u16) qamVdPeriod); WR16(devAddr, QAM_VD_MEASUREMENT_PRESCALE__A, qamVdPrescale); - extAttr->qamVdPeriod = (u16_t) qamVdPeriod; + extAttr->qamVdPeriod = (u16) qamVdPeriod; extAttr->qamVdPrescale = qamVdPrescale; } @@ -6546,7 +6546,7 @@ rw_error: static DRXStatus_t SetQAM16(pDRXDemodInstance_t demod) { struct i2c_device_addr *devAddr = demod->myI2CDevAddr; - const u8_t qamDqQualFun[] = { + const u8 qamDqQualFun[] = { DRXJ_16TO8(2), /* fun0 */ DRXJ_16TO8(2), /* fun1 */ DRXJ_16TO8(2), /* fun2 */ @@ -6554,7 +6554,7 @@ static DRXStatus_t SetQAM16(pDRXDemodInstance_t demod) DRXJ_16TO8(3), /* fun4 */ DRXJ_16TO8(3), /* fun5 */ }; - const u8_t qamEqCmaRad[] = { + const u8 qamEqCmaRad[] = { DRXJ_16TO8(13517), /* RAD0 */ DRXJ_16TO8(13517), /* RAD1 */ DRXJ_16TO8(13517), /* RAD2 */ @@ -6564,9 +6564,9 @@ static DRXStatus_t SetQAM16(pDRXDemodInstance_t demod) }; WRB(devAddr, QAM_DQ_QUAL_FUN0__A, sizeof(qamDqQualFun), - ((pu8_t) qamDqQualFun)); + ((u8 *) qamDqQualFun)); WRB(devAddr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qamEqCmaRad), - ((pu8_t) qamEqCmaRad)); + ((u8 *) qamEqCmaRad)); WR16(devAddr, SCU_RAM_QAM_FSM_RTH__A, 140); WR16(devAddr, SCU_RAM_QAM_FSM_FTH__A, 50); @@ -6583,9 +6583,9 @@ static DRXStatus_t SetQAM16(pDRXDemodInstance_t demod) WR16(devAddr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 220); WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 25); WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 6); - WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16_t) (-24)); - WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16_t) (-65)); - WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16_t) (-127)); + WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) (-24)); + WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) (-65)); + WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) (-127)); WR16(devAddr, SCU_RAM_QAM_LC_CA_FINE__A, 15); WR16(devAddr, SCU_RAM_QAM_LC_CA_COARSE__A, 40); @@ -6626,7 +6626,7 @@ rw_error: static DRXStatus_t SetQAM32(pDRXDemodInstance_t demod) { struct i2c_device_addr *devAddr = demod->myI2CDevAddr; - const u8_t qamDqQualFun[] = { + const u8 qamDqQualFun[] = { DRXJ_16TO8(3), /* fun0 */ DRXJ_16TO8(3), /* fun1 */ DRXJ_16TO8(3), /* fun2 */ @@ -6634,7 +6634,7 @@ static DRXStatus_t SetQAM32(pDRXDemodInstance_t demod) DRXJ_16TO8(4), /* fun4 */ DRXJ_16TO8(4), /* fun5 */ }; - const u8_t qamEqCmaRad[] = { + const u8 qamEqCmaRad[] = { DRXJ_16TO8(6707), /* RAD0 */ DRXJ_16TO8(6707), /* RAD1 */ DRXJ_16TO8(6707), /* RAD2 */ @@ -6644,9 +6644,9 @@ static DRXStatus_t SetQAM32(pDRXDemodInstance_t demod) }; WRB(devAddr, QAM_DQ_QUAL_FUN0__A, sizeof(qamDqQualFun), - ((pu8_t) qamDqQualFun)); + ((u8 *) qamDqQualFun)); WRB(devAddr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qamEqCmaRad), - ((pu8_t) qamEqCmaRad)); + ((u8 *) qamEqCmaRad)); WR16(devAddr, SCU_RAM_QAM_FSM_RTH__A, 90); WR16(devAddr, SCU_RAM_QAM_FSM_FTH__A, 50); @@ -6661,11 +6661,11 @@ static DRXStatus_t SetQAM32(pDRXDemodInstance_t demod) WR16(devAddr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12); WR16(devAddr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 140); - WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16_t) (-8)); - WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16_t) (-16)); - WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16_t) (-26)); - WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16_t) (-56)); - WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16_t) (-86)); + WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) (-8)); + WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) (-16)); + WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) (-26)); + WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) (-56)); + WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) (-86)); WR16(devAddr, SCU_RAM_QAM_LC_CA_FINE__A, 15); WR16(devAddr, SCU_RAM_QAM_LC_CA_COARSE__A, 40); @@ -6706,7 +6706,7 @@ rw_error: static DRXStatus_t SetQAM64(pDRXDemodInstance_t demod) { struct i2c_device_addr *devAddr = demod->myI2CDevAddr; - const u8_t qamDqQualFun[] = { /* this is hw reset value. no necessary to re-write */ + const u8 qamDqQualFun[] = { /* this is hw reset value. no necessary to re-write */ DRXJ_16TO8(4), /* fun0 */ DRXJ_16TO8(4), /* fun1 */ DRXJ_16TO8(4), /* fun2 */ @@ -6714,7 +6714,7 @@ static DRXStatus_t SetQAM64(pDRXDemodInstance_t demod) DRXJ_16TO8(6), /* fun4 */ DRXJ_16TO8(6), /* fun5 */ }; - const u8_t qamEqCmaRad[] = { + const u8 qamEqCmaRad[] = { DRXJ_16TO8(13336), /* RAD0 */ DRXJ_16TO8(12618), /* RAD1 */ DRXJ_16TO8(11988), /* RAD2 */ @@ -6724,9 +6724,9 @@ static DRXStatus_t SetQAM64(pDRXDemodInstance_t demod) }; WRB(devAddr, QAM_DQ_QUAL_FUN0__A, sizeof(qamDqQualFun), - ((pu8_t) qamDqQualFun)); + ((u8 *) qamDqQualFun)); WRB(devAddr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qamEqCmaRad), - ((pu8_t) qamEqCmaRad)); + ((u8 *) qamEqCmaRad)); WR16(devAddr, SCU_RAM_QAM_FSM_RTH__A, 105); WR16(devAddr, SCU_RAM_QAM_FSM_FTH__A, 60); @@ -6743,9 +6743,9 @@ static DRXStatus_t SetQAM64(pDRXDemodInstance_t demod) WR16(devAddr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 141); WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 7); WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 0); - WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16_t) (-15)); - WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16_t) (-45)); - WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16_t) (-80)); + WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) (-15)); + WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) (-45)); + WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) (-80)); WR16(devAddr, SCU_RAM_QAM_LC_CA_FINE__A, 15); WR16(devAddr, SCU_RAM_QAM_LC_CA_COARSE__A, 40); @@ -6786,7 +6786,7 @@ rw_error: static DRXStatus_t SetQAM128(pDRXDemodInstance_t demod) { struct i2c_device_addr *devAddr = demod->myI2CDevAddr; - const u8_t qamDqQualFun[] = { + const u8 qamDqQualFun[] = { DRXJ_16TO8(6), /* fun0 */ DRXJ_16TO8(6), /* fun1 */ DRXJ_16TO8(6), /* fun2 */ @@ -6794,7 +6794,7 @@ static DRXStatus_t SetQAM128(pDRXDemodInstance_t demod) DRXJ_16TO8(9), /* fun4 */ DRXJ_16TO8(9), /* fun5 */ }; - const u8_t qamEqCmaRad[] = { + const u8 qamEqCmaRad[] = { DRXJ_16TO8(6164), /* RAD0 */ DRXJ_16TO8(6598), /* RAD1 */ DRXJ_16TO8(6394), /* RAD2 */ @@ -6804,9 +6804,9 @@ static DRXStatus_t SetQAM128(pDRXDemodInstance_t demod) }; WRB(devAddr, QAM_DQ_QUAL_FUN0__A, sizeof(qamDqQualFun), - ((pu8_t) qamDqQualFun)); + ((u8 *) qamDqQualFun)); WRB(devAddr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qamEqCmaRad), - ((pu8_t) qamEqCmaRad)); + ((u8 *) qamEqCmaRad)); WR16(devAddr, SCU_RAM_QAM_FSM_RTH__A, 50); WR16(devAddr, SCU_RAM_QAM_FSM_FTH__A, 60); @@ -6823,9 +6823,9 @@ static DRXStatus_t SetQAM128(pDRXDemodInstance_t demod) WR16(devAddr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 65); WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 5); WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 3); - WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16_t) (-1)); + WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) (-1)); WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 12); - WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16_t) (-23)); + WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) (-23)); WR16(devAddr, SCU_RAM_QAM_LC_CA_FINE__A, 15); WR16(devAddr, SCU_RAM_QAM_LC_CA_COARSE__A, 40); @@ -6866,7 +6866,7 @@ rw_error: static DRXStatus_t SetQAM256(pDRXDemodInstance_t demod) { struct i2c_device_addr *devAddr = demod->myI2CDevAddr; - const u8_t qamDqQualFun[] = { + const u8 qamDqQualFun[] = { DRXJ_16TO8(8), /* fun0 */ DRXJ_16TO8(8), /* fun1 */ DRXJ_16TO8(8), /* fun2 */ @@ -6874,7 +6874,7 @@ static DRXStatus_t SetQAM256(pDRXDemodInstance_t demod) DRXJ_16TO8(12), /* fun4 */ DRXJ_16TO8(12), /* fun5 */ }; - const u8_t qamEqCmaRad[] = { + const u8 qamEqCmaRad[] = { DRXJ_16TO8(12345), /* RAD0 */ DRXJ_16TO8(12345), /* RAD1 */ DRXJ_16TO8(13626), /* RAD2 */ @@ -6884,9 +6884,9 @@ static DRXStatus_t SetQAM256(pDRXDemodInstance_t demod) }; WRB(devAddr, QAM_DQ_QUAL_FUN0__A, sizeof(qamDqQualFun), - ((pu8_t) qamDqQualFun)); + ((u8 *) qamDqQualFun)); WRB(devAddr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qamEqCmaRad), - ((pu8_t) qamEqCmaRad)); + ((u8 *) qamEqCmaRad)); WR16(devAddr, SCU_RAM_QAM_FSM_RTH__A, 50); WR16(devAddr, SCU_RAM_QAM_FSM_FTH__A, 60); @@ -6905,7 +6905,7 @@ static DRXStatus_t SetQAM256(pDRXDemodInstance_t demod) WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 13); WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, 7); WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 0); - WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16_t) (-8)); + WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) (-8)); WR16(devAddr, SCU_RAM_QAM_LC_CA_FINE__A, 15); WR16(devAddr, SCU_RAM_QAM_LC_CA_COARSE__A, 40); @@ -6949,25 +6949,25 @@ rw_error: */ static DRXStatus_t SetQAM(pDRXDemodInstance_t demod, - pDRXChannel_t channel, DRXFrequency_t tunerFreqOffset, u32_t op) + pDRXChannel_t channel, DRXFrequency_t tunerFreqOffset, u32 op) { struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; pDRXCommonAttr_t commonAttr = NULL; - u16_t cmdResult = 0; - u32_t adcFrequency = 0; - u32_t iqmRcRate = 0; - u16_t lcSymbolFreq = 0; - u16_t iqmRcStretch = 0; - u16_t setEnvParameters = 0; - u16_t setParamParameters[2] = { 0 }; + u16 cmdResult = 0; + u32 adcFrequency = 0; + u32 iqmRcRate = 0; + u16 lcSymbolFreq = 0; + u16 iqmRcStretch = 0; + u16 setEnvParameters = 0; + u16 setParamParameters[2] = { 0 }; DRXJSCUCmd_t cmdSCU = { /* command */ 0, /* parameterLen */ 0, /* resultLen */ 0, /* parameter */ NULL, /* result */ NULL }; - const u8_t qamA_taps[] = { + const u8 qamA_taps[] = { DRXJ_16TO8(-1), /* re0 */ DRXJ_16TO8(1), /* re1 */ DRXJ_16TO8(1), /* re2 */ @@ -6997,7 +6997,7 @@ SetQAM(pDRXDemodInstance_t demod, DRXJ_16TO8(-40), /* re26 */ DRXJ_16TO8(619) /* re27 */ }; - const u8_t qamB64_taps[] = { + const u8 qamB64_taps[] = { DRXJ_16TO8(0), /* re0 */ DRXJ_16TO8(-2), /* re1 */ DRXJ_16TO8(1), /* re2 */ @@ -7027,7 +7027,7 @@ SetQAM(pDRXDemodInstance_t demod, DRXJ_16TO8(-46), /* re26 */ DRXJ_16TO8(614) /* re27 */ }; - const u8_t qamB256_taps[] = { + const u8 qamB256_taps[] = { DRXJ_16TO8(-2), /* re0 */ DRXJ_16TO8(4), /* re1 */ DRXJ_16TO8(1), /* re2 */ @@ -7057,7 +7057,7 @@ SetQAM(pDRXDemodInstance_t demod, DRXJ_16TO8(-32), /* re26 */ DRXJ_16TO8(628) /* re27 */ }; - const u8_t qamC_taps[] = { + const u8 qamC_taps[] = { DRXJ_16TO8(-3), /* re0 */ DRXJ_16TO8(3), /* re1 */ DRXJ_16TO8(2), /* re2 */ @@ -7120,7 +7120,7 @@ SetQAM(pDRXDemodInstance_t demod, ((adcFrequency % channel->symbolrate), channel->symbolrate) >> 7) - (1 << 23); lcSymbolFreq = - (u16_t) (Frac28 + (u16) (Frac28 (channel->symbolrate + (adcFrequency >> 13), adcFrequency) >> 16); @@ -7308,33 +7308,33 @@ SetQAM(pDRXDemodInstance_t demod, if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) { if (extAttr->standard == DRX_STANDARD_ITU_A) { WRB(devAddr, IQM_CF_TAP_RE0__A, sizeof(qamA_taps), - ((pu8_t) qamA_taps)); + ((u8 *) qamA_taps)); WRB(devAddr, IQM_CF_TAP_IM0__A, sizeof(qamA_taps), - ((pu8_t) qamA_taps)); + ((u8 *) qamA_taps)); } else if (extAttr->standard == DRX_STANDARD_ITU_B) { switch (channel->constellation) { case DRX_CONSTELLATION_QAM64: WRB(devAddr, IQM_CF_TAP_RE0__A, - sizeof(qamB64_taps), ((pu8_t) qamB64_taps)); + sizeof(qamB64_taps), ((u8 *) qamB64_taps)); WRB(devAddr, IQM_CF_TAP_IM0__A, - sizeof(qamB64_taps), ((pu8_t) qamB64_taps)); + sizeof(qamB64_taps), ((u8 *) qamB64_taps)); break; case DRX_CONSTELLATION_QAM256: WRB(devAddr, IQM_CF_TAP_RE0__A, sizeof(qamB256_taps), - ((pu8_t) qamB256_taps)); + ((u8 *) qamB256_taps)); WRB(devAddr, IQM_CF_TAP_IM0__A, sizeof(qamB256_taps), - ((pu8_t) qamB256_taps)); + ((u8 *) qamB256_taps)); break; default: return (DRX_STS_ERROR); } } else if (extAttr->standard == DRX_STANDARD_ITU_C) { WRB(devAddr, IQM_CF_TAP_RE0__A, sizeof(qamC_taps), - ((pu8_t) qamC_taps)); + ((u8 *) qamC_taps)); WRB(devAddr, IQM_CF_TAP_IM0__A, sizeof(qamC_taps), - ((pu8_t) qamC_taps)); + ((u8 *) qamC_taps)); } /* SETP 4: constellation specific setup */ @@ -7414,12 +7414,12 @@ static DRXStatus_t CtrlGetQAMSigQuality(pDRXDemodInstance_t demod, pDRXSigQuality_t sigQuality); static DRXStatus_t qamFlipSpec(pDRXDemodInstance_t demod, pDRXChannel_t channel) { - u32_t iqmFsRateOfs = 0; - u32_t iqmFsRateLo = 0; - u16_t qamCtlEna = 0; - u16_t data = 0; - u16_t equMode = 0; - u16_t fsmState = 0; + u32 iqmFsRateOfs = 0; + u32 iqmFsRateLo = 0; + u16 qamCtlEna = 0; + u16 data = 0; + u16 equMode = 0; + u16 fsmState = 0; int i = 0; int ofsofs = 0; struct i2c_device_addr *devAddr = NULL; @@ -7514,12 +7514,12 @@ QAM64Auto(pDRXDemodInstance_t demod, DRXFrequency_t tunerFreqOffset, pDRXLockStatus_t lockStatus) { DRXSigQuality_t sigQuality; - u16_t data = 0; - u32_t state = NO_LOCK; - u32_t startTime = 0; - u32_t dLockedTime = 0; + u16 data = 0; + u32 state = NO_LOCK; + u32 startTime = 0; + u32 dLockedTime = 0; pDRXJData_t extAttr = NULL; - u32_t timeoutOfs = 0; + u32 timeoutOfs = 0; /* external attributes for storing aquired channel constellation */ extAttr = (pDRXJData_t) demod->myExtAttr; @@ -7628,11 +7628,11 @@ QAM256Auto(pDRXDemodInstance_t demod, DRXFrequency_t tunerFreqOffset, pDRXLockStatus_t lockStatus) { DRXSigQuality_t sigQuality; - u32_t state = NO_LOCK; - u32_t startTime = 0; - u32_t dLockedTime = 0; + u32 state = NO_LOCK; + u32 startTime = 0; + u32 dLockedTime = 0; pDRXJData_t extAttr = NULL; - u32_t timeoutOfs = DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME; + u32 timeoutOfs = DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME; /* external attributes for storing aquired channel constellation */ extAttr = (pDRXJData_t) demod->myExtAttr; @@ -7763,7 +7763,7 @@ SetQAMChannel(pDRXDemodInstance_t demod, extAttr->mirror = channel->mirror; } { - u16_t qamCtlEna = 0; + u16 qamCtlEna = 0; RR16(demod->myI2CDevAddr, SCU_RAM_QAM_CTL_ENA__A, &qamCtlEna); @@ -7796,7 +7796,7 @@ SetQAMChannel(pDRXDemodInstance_t demod, extAttr->mirror = channel->mirror; } { - u16_t qamCtlEna = 0; + u16 qamCtlEna = 0; RR16(demod->myI2CDevAddr, SCU_RAM_QAM_CTL_ENA__A, &qamCtlEna); WR16(demod->myI2CDevAddr, @@ -7844,7 +7844,7 @@ rw_error: static DRXStatus_t GetQAMRSErrCount(struct i2c_device_addr *devAddr, pDRXJRSErrors_t RSErrors) { - u16_t nrBitErrors = 0, + u16 nrBitErrors = 0, nrSymbolErrors = 0, nrPacketErrors = 0, nrFailures = 0, nrSncParFailCount = 0; @@ -7903,29 +7903,29 @@ CtrlGetQAMSigQuality(pDRXDemodInstance_t demod, pDRXSigQuality_t sigQuality) DRXConstellation_t constellation = DRX_CONSTELLATION_UNKNOWN; DRXJRSErrors_t measuredRSErrors = { 0, 0, 0, 0, 0 }; - u32_t preBitErrRS = 0; /* pre RedSolomon Bit Error Rate */ - u32_t postBitErrRS = 0; /* post RedSolomon Bit Error Rate */ - u32_t pktErrs = 0; /* no of packet errors in RS */ - u16_t qamSlErrPower = 0; /* accumulated error between raw and sliced symbols */ - u16_t qsymErrVD = 0; /* quadrature symbol errors in QAM_VD */ - u16_t fecOcPeriod = 0; /* SNC sync failure measurement period */ - u16_t fecRsPrescale = 0; /* ReedSolomon Measurement Prescale */ - u16_t fecRsPeriod = 0; /* Value for corresponding I2C register */ + u32 preBitErrRS = 0; /* pre RedSolomon Bit Error Rate */ + u32 postBitErrRS = 0; /* post RedSolomon Bit Error Rate */ + u32 pktErrs = 0; /* no of packet errors in RS */ + u16 qamSlErrPower = 0; /* accumulated error between raw and sliced symbols */ + u16 qsymErrVD = 0; /* quadrature symbol errors in QAM_VD */ + u16 fecOcPeriod = 0; /* SNC sync failure measurement period */ + u16 fecRsPrescale = 0; /* ReedSolomon Measurement Prescale */ + u16 fecRsPeriod = 0; /* Value for corresponding I2C register */ /* calculation constants */ - u32_t rsBitCnt = 0; /* RedSolomon Bit Count */ - u32_t qamSlSigPower = 0; /* used for MER, depends of QAM constellation */ + u32 rsBitCnt = 0; /* RedSolomon Bit Count */ + u32 qamSlSigPower = 0; /* used for MER, depends of QAM constellation */ /* intermediate results */ - u32_t e = 0; /* exponent value used for QAM BER/SER */ - u32_t m = 0; /* mantisa value used for QAM BER/SER */ - u32_t berCnt = 0; /* BER count */ + u32 e = 0; /* exponent value used for QAM BER/SER */ + u32 m = 0; /* mantisa value used for QAM BER/SER */ + u32 berCnt = 0; /* BER count */ /* signal quality info */ - u32_t qamSlMer = 0; /* QAM MER */ - u32_t qamPreRSBer = 0; /* Pre RedSolomon BER */ - u32_t qamPostRSBer = 0; /* Post RedSolomon BER */ - u32_t qamVDSer = 0; /* ViterbiDecoder SER */ - u16_t qamVdPrescale = 0; /* Viterbi Measurement Prescale */ - u16_t qamVdPeriod = 0; /* Viterbi Measurement period */ - u32_t vdBitCnt = 0; /* ViterbiDecoder Bit Count */ + u32 qamSlMer = 0; /* QAM MER */ + u32 qamPreRSBer = 0; /* Pre RedSolomon BER */ + u32 qamPostRSBer = 0; /* Post RedSolomon BER */ + u32 qamVDSer = 0; /* ViterbiDecoder SER */ + u16 qamVdPrescale = 0; /* Viterbi Measurement Prescale */ + u16 qamVdPeriod = 0; /* Viterbi Measurement period */ + u32 vdBitCnt = 0; /* ViterbiDecoder Bit Count */ /* get device basic information */ devAddr = demod->myI2CDevAddr; @@ -7980,7 +7980,7 @@ CtrlGetQAMSigQuality(pDRXDemodInstance_t demod, pDRXSigQuality_t sigQuality) else qamSlMer = Log10Times100(qamSlSigPower) - - Log10Times100((u32_t) qamSlErrPower); + Log10Times100((u32) qamSlErrPower); /* ----------------------------------------- */ /* Pre Viterbi Symbol Error Rate Calculation */ @@ -8011,8 +8011,8 @@ CtrlGetQAMSigQuality(pDRXDemodInstance_t demod, pDRXSigQuality_t sigQuality) /* pre RS BER is good if it is below 3.5e-4 */ /* get the register values */ - preBitErrRS = (u32_t) measuredRSErrors.nrBitErrors; - pktErrs = postBitErrRS = (u32_t) measuredRSErrors.nrSncParFailCount; + preBitErrRS = (u32) measuredRSErrors.nrBitErrors; + pktErrs = postBitErrRS = (u32) measuredRSErrors.nrSncParFailCount; /* Extract the Exponent and the Mantisa of the */ /* pre Reed-Solomon bit error count */ @@ -8049,7 +8049,7 @@ CtrlGetQAMSigQuality(pDRXDemodInstance_t demod, pDRXSigQuality_t sigQuality) qamPostRSBer = e / m; /* fill signal quality data structure */ - sigQuality->MER = ((u16_t) qamSlMer); + sigQuality->MER = ((u16) qamSlMer); if (extAttr->standard == DRX_STANDARD_ITU_B) { sigQuality->preViterbiBER = qamVDSer; } else { @@ -8057,11 +8057,11 @@ CtrlGetQAMSigQuality(pDRXDemodInstance_t demod, pDRXSigQuality_t sigQuality) } sigQuality->postViterbiBER = qamPreRSBer; sigQuality->postReedSolomonBER = qamPostRSBer; - sigQuality->scaleFactorBER = ((u32_t) 1000000); + sigQuality->scaleFactorBER = ((u32) 1000000); #ifdef DRXJ_SIGNAL_ACCUM_ERR CHK_ERROR(GetAccPktErr(demod, &sigQuality->packetError)); #else - sigQuality->packetError = ((u16_t) pktErrs); + sigQuality->packetError = ((u16) pktErrs); #endif return (DRX_STS_OK); @@ -8080,14 +8080,14 @@ rw_error: static DRXStatus_t CtrlGetQAMConstel(pDRXDemodInstance_t demod, pDRXComplex_t complexNr) { - u16_t fecOcOcrMode = 0; + u16 fecOcOcrMode = 0; /**< FEC OCR grabber configuration */ - u16_t qamSlCommMb = 0;/**< QAM SL MB configuration */ - u16_t qamSlCommMbInit = 0; + u16 qamSlCommMb = 0;/**< QAM SL MB configuration */ + u16 qamSlCommMbInit = 0; /**< QAM SL MB intial configuration */ - u16_t im = 0; /**< constellation Im part */ - u16_t re = 0; /**< constellation Re part */ - u32_t data = 0; + u16 im = 0; /**< constellation Im part */ + u16 re = 0; /**< constellation Re part */ + u32 data = 0; struct i2c_device_addr *devAddr = NULL; /**< device address */ @@ -8127,8 +8127,8 @@ CtrlGetQAMConstel(pDRXDemodInstance_t demod, pDRXComplex_t complexNr) /* read data */ RR32(devAddr, FEC_OC_OCR_GRAB_RD0__A, &data); - re = (u16_t) (data & FEC_OC_OCR_GRAB_RD0__M); - im = (u16_t) ((data >> 16) & FEC_OC_OCR_GRAB_RD1__M); + re = (u16) (data & FEC_OC_OCR_GRAB_RD0__M); + im = (u16) ((data >> 16) & FEC_OC_OCR_GRAB_RD1__M); /* TODO: */ /* interpret data (re & im) according to the Monitor bus mapping ?? */ @@ -8140,8 +8140,8 @@ CtrlGetQAMConstel(pDRXDemodInstance_t demod, pDRXComplex_t complexNr) if ((im & 0x0200) == 0x0200) { im |= 0xFC00; } - complexNr->re = ((s16_t) re); - complexNr->im = ((s16_t) im); + complexNr->re = ((s16) re); + complexNr->im = ((s16) im); /* Restore MB (Monitor bus) */ WR16(devAddr, QAM_SL_COMM_MB__A, qamSlCommMbInit); @@ -8290,10 +8290,10 @@ AtvUpdateConfig(pDRXDemodInstance_t demod, Bool_t forceUpdate) /* bypass fast carrier recovery */ if (forceUpdate) { - u16_t data = 0; + u16 data = 0; RR16(devAddr, IQM_RT_ROT_BP__A, &data); - data &= (~((u16_t) IQM_RT_ROT_BP_ROT_OFF__M)); + data &= (~((u16) IQM_RT_ROT_BP_ROT_OFF__M)); if (extAttr->phaseCorrectionBypass) { data |= IQM_RT_ROT_BP_ROT_OFF_OFF; } else { @@ -8317,7 +8317,7 @@ AtvUpdateConfig(pDRXDemodInstance_t demod, Bool_t forceUpdate) /* SIF attenuation */ if (forceUpdate || ((extAttr->atvCfgChangedFlags & DRXJ_ATV_CHANGED_SIF_ATT) != 0)) { - u16_t attenuation = 0; + u16 attenuation = 0; switch (extAttr->sifAttenuation) { case DRXJ_SIF_ATTENUATION_0DB: @@ -8342,7 +8342,7 @@ AtvUpdateConfig(pDRXDemodInstance_t demod, Bool_t forceUpdate) /* SIF & CVBS enable */ if (forceUpdate || ((extAttr->atvCfgChangedFlags & DRXJ_ATV_CHANGED_OUTPUT) != 0)) { - u16_t data = 0; + u16 data = 0; RR16(devAddr, ATV_TOP_STDBY__A, &data); if (extAttr->enableCVBSOutput) { @@ -8451,10 +8451,10 @@ CtrlSetCfgAtvEquCoef(pDRXDemodInstance_t demod, pDRXJCfgAtvEquCoef_t coef) (coef->coef1 > (ATV_TOP_EQU1_EQU_C1__M / 2)) || (coef->coef2 > (ATV_TOP_EQU2_EQU_C2__M / 2)) || (coef->coef3 > (ATV_TOP_EQU3_EQU_C3__M / 2)) || - (coef->coef0 < ((s16_t) ~ (ATV_TOP_EQU0_EQU_C0__M >> 1))) || - (coef->coef1 < ((s16_t) ~ (ATV_TOP_EQU1_EQU_C1__M >> 1))) || - (coef->coef2 < ((s16_t) ~ (ATV_TOP_EQU2_EQU_C2__M >> 1))) || - (coef->coef3 < ((s16_t) ~ (ATV_TOP_EQU3_EQU_C3__M >> 1)))) { + (coef->coef0 < ((s16) ~ (ATV_TOP_EQU0_EQU_C0__M >> 1))) || + (coef->coef1 < ((s16) ~ (ATV_TOP_EQU1_EQU_C1__M >> 1))) || + (coef->coef2 < ((s16) ~ (ATV_TOP_EQU2_EQU_C2__M >> 1))) || + (coef->coef3 < ((s16) ~ (ATV_TOP_EQU3_EQU_C3__M >> 1)))) { return (DRX_STS_INVALID_ARG); } @@ -8531,8 +8531,8 @@ CtrlSetCfgAtvMisc(pDRXDemodInstance_t demod, pDRXJCfgAtvMisc_t settings) /* Check arguments */ if ((settings == NULL) || - ((settings->peakFilter) < (s16_t) (-8)) || - ((settings->peakFilter) > (s16_t) (15)) || + ((settings->peakFilter) < (s16) (-8)) || + ((settings->peakFilter) > (s16) (15)) || ((settings->noiseFilter) > 15)) { return (DRX_STS_INVALID_ARG); } @@ -8601,7 +8601,7 @@ CtrlGetCfgAtvMisc(pDRXDemodInstance_t demod, pDRXJCfgAtvMisc_t settings) static DRXStatus_t CtrlGetCfgAtvOutput(pDRXDemodInstance_t demod, pDRXJCfgAtvOutput_t outputCfg) { - u16_t data = 0; + u16 data = 0; /* Check arguments */ if (outputCfg == NULL) { @@ -8643,8 +8643,8 @@ CtrlGetCfgAtvAgcStatus(pDRXDemodInstance_t demod, { struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; - u16_t data = 0; - u32_t tmp = 0; + u16 data = 0; + u32 tmp = 0; /* Check arguments */ if (agcStatus == NULL) { @@ -8661,8 +8661,8 @@ CtrlGetCfgAtvAgcStatus(pDRXDemodInstance_t demod, IQM_AF_AGC_RF__A * 27 is 20 bits worst case. */ RR16(devAddr, IQM_AF_AGC_RF__A, &data); - tmp = ((u32_t) data) * 27 - ((u32_t) (data >> 2)); /* nA */ - agcStatus->rfAgcGain = (u16_t) (tmp / 1000); /* uA */ + tmp = ((u32) data) * 27 - ((u32) (data >> 2)); /* nA */ + agcStatus->rfAgcGain = (u16) (tmp / 1000); /* uA */ /* rounding */ if (tmp % 1000 >= 500) { (agcStatus->rfAgcGain)++; @@ -8675,8 +8675,8 @@ CtrlGetCfgAtvAgcStatus(pDRXDemodInstance_t demod, IQM_AF_AGC_IF__A * 27 is 20 bits worst case. */ RR16(devAddr, IQM_AF_AGC_IF__A, &data); - tmp = ((u32_t) data) * 27 - ((u32_t) (data >> 2)); /* nA */ - agcStatus->ifAgcGain = (u16_t) (tmp / 1000); /* uA */ + tmp = ((u32) data) * 27 - ((u32) (data >> 2)); /* nA */ + agcStatus->ifAgcGain = (u16) (tmp / 1000); /* uA */ /* rounding */ if (tmp % 1000 >= 500) { (agcStatus->ifAgcGain)++; @@ -8697,7 +8697,7 @@ CtrlGetCfgAtvAgcStatus(pDRXDemodInstance_t demod, data++; } data >>= 1; - agcStatus->videoAgcGain = ((s16_t) data) - 75; /* 0.1 dB */ + agcStatus->videoAgcGain = ((s16) data) - 75; /* 0.1 dB */ /* audioGain = (SCU_RAM_ATV_SIF_GAIN__A -8)* 0.05 (dB) @@ -8714,7 +8714,7 @@ CtrlGetCfgAtvAgcStatus(pDRXDemodInstance_t demod, data++; } data >>= 1; - agcStatus->audioAgcGain = ((s16_t) data) - 4; /* 0.1 dB */ + agcStatus->audioAgcGain = ((s16) data) - 4; /* 0.1 dB */ /* Loop gain's */ SARR16(devAddr, SCU_RAM_AGC_KI__A, &data); @@ -8789,7 +8789,7 @@ PowerDownATV(pDRXDemodInstance_t demod, DRXStandard_t standard, Bool_t primary) /* *parameter */ NULL, /* *result */ NULL }; - u16_t cmdResult = 0; + u16 cmdResult = 0; pDRXJData_t extAttr = NULL; devAddr = demod->myI2CDevAddr; @@ -8859,7 +8859,7 @@ switch DRXJ_ATV_COEF_FILE="customer_coefs.c.inc". Still to check if this will work; DRXJ_16TO8 macro may cause trouble ? */ - const u8_t ntsc_taps_re[] = { + const u8 ntsc_taps_re[] = { DRXJ_16TO8(-12), /* re0 */ DRXJ_16TO8(-9), /* re1 */ DRXJ_16TO8(9), /* re2 */ @@ -8889,7 +8889,7 @@ trouble ? DRXJ_16TO8(50), /* re26 */ DRXJ_16TO8(679) /* re27 */ }; - const u8_t ntsc_taps_im[] = { + const u8 ntsc_taps_im[] = { DRXJ_16TO8(11), /* im0 */ DRXJ_16TO8(1), /* im1 */ DRXJ_16TO8(-10), /* im2 */ @@ -8919,7 +8919,7 @@ trouble ? DRXJ_16TO8(553), /* im26 */ DRXJ_16TO8(302) /* im27 */ }; - const u8_t bg_taps_re[] = { + const u8 bg_taps_re[] = { DRXJ_16TO8(-18), /* re0 */ DRXJ_16TO8(18), /* re1 */ DRXJ_16TO8(19), /* re2 */ @@ -8949,7 +8949,7 @@ trouble ? DRXJ_16TO8(172), /* re26 */ DRXJ_16TO8(801) /* re27 */ }; - const u8_t bg_taps_im[] = { + const u8 bg_taps_im[] = { DRXJ_16TO8(-24), /* im0 */ DRXJ_16TO8(-10), /* im1 */ DRXJ_16TO8(9), /* im2 */ @@ -8979,7 +8979,7 @@ trouble ? DRXJ_16TO8(687), /* im26 */ DRXJ_16TO8(877) /* im27 */ }; - const u8_t dk_i_l_lp_taps_re[] = { + const u8 dk_i_l_lp_taps_re[] = { DRXJ_16TO8(-23), /* re0 */ DRXJ_16TO8(9), /* re1 */ DRXJ_16TO8(16), /* re2 */ @@ -9009,7 +9009,7 @@ trouble ? DRXJ_16TO8(206), /* re26 */ DRXJ_16TO8(894) /* re27 */ }; - const u8_t dk_i_l_lp_taps_im[] = { + const u8 dk_i_l_lp_taps_im[] = { DRXJ_16TO8(-8), /* im0 */ DRXJ_16TO8(-20), /* im1 */ DRXJ_16TO8(17), /* im2 */ @@ -9039,7 +9039,7 @@ trouble ? DRXJ_16TO8(657), /* im26 */ DRXJ_16TO8(1023) /* im27 */ }; - const u8_t fm_taps_re[] = { + const u8 fm_taps_re[] = { DRXJ_16TO8(0), /* re0 */ DRXJ_16TO8(0), /* re1 */ DRXJ_16TO8(0), /* re2 */ @@ -9069,7 +9069,7 @@ trouble ? DRXJ_16TO8(0), /* re26 */ DRXJ_16TO8(0) /* re27 */ }; - const u8_t fm_taps_im[] = { + const u8 fm_taps_im[] = { DRXJ_16TO8(-6), /* im0 */ DRXJ_16TO8(2), /* im1 */ DRXJ_16TO8(14), /* im2 */ @@ -9107,8 +9107,8 @@ trouble ? /* *parameter */ NULL, /* *result */ NULL }; - u16_t cmdResult = 0; - u16_t cmdParam = 0; + u16 cmdResult = 0; + u16 cmdParam = 0; #ifdef DRXJ_SPLIT_UCODE_UPLOAD DRXUCodeInfo_t ucodeInfo; pDRXCommonAttr_t commonAttr = NULL; @@ -9166,9 +9166,9 @@ trouble ? WR16(devAddr, IQM_RT_LO_INCR__A, IQM_RT_LO_INCR_MN); WR16(devAddr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M); WRB(devAddr, IQM_CF_TAP_RE0__A, sizeof(ntsc_taps_re), - ((pu8_t) ntsc_taps_re)); + ((u8 *) ntsc_taps_re)); WRB(devAddr, IQM_CF_TAP_IM0__A, sizeof(ntsc_taps_im), - ((pu8_t) ntsc_taps_im)); + ((u8 *) ntsc_taps_im)); WR16(devAddr, ATV_TOP_CR_AMP_TH__A, ATV_TOP_CR_AMP_TH_MN); WR16(devAddr, ATV_TOP_CR_CONT__A, @@ -9196,9 +9196,9 @@ trouble ? WR16(devAddr, IQM_RT_LO_INCR__A, 2994); WR16(devAddr, IQM_CF_MIDTAP__A, 0); WRB(devAddr, IQM_CF_TAP_RE0__A, sizeof(fm_taps_re), - ((pu8_t) fm_taps_re)); + ((u8 *) fm_taps_re)); WRB(devAddr, IQM_CF_TAP_IM0__A, sizeof(fm_taps_im), - ((pu8_t) fm_taps_im)); + ((u8 *) fm_taps_im)); WR16(devAddr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_FM | ATV_TOP_STD_VID_POL_FM)); WR16(devAddr, ATV_TOP_MOD_CONTROL__A, 0); @@ -9218,9 +9218,9 @@ trouble ? WR16(devAddr, IQM_RT_LO_INCR__A, 1820); /* TODO check with IS */ WR16(devAddr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M); WRB(devAddr, IQM_CF_TAP_RE0__A, sizeof(bg_taps_re), - ((pu8_t) bg_taps_re)); + ((u8 *) bg_taps_re)); WRB(devAddr, IQM_CF_TAP_IM0__A, sizeof(bg_taps_im), - ((pu8_t) bg_taps_im)); + ((u8 *) bg_taps_im)); WR16(devAddr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_BG); WR16(devAddr, ATV_TOP_CR_AMP_TH__A, ATV_TOP_CR_AMP_TH_BG); WR16(devAddr, ATV_TOP_CR_CONT__A, @@ -9247,9 +9247,9 @@ trouble ? WR16(devAddr, IQM_RT_LO_INCR__A, 2225); /* TODO check with IS */ WR16(devAddr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M); WRB(devAddr, IQM_CF_TAP_RE0__A, sizeof(dk_i_l_lp_taps_re), - ((pu8_t) dk_i_l_lp_taps_re)); + ((u8 *) dk_i_l_lp_taps_re)); WRB(devAddr, IQM_CF_TAP_IM0__A, sizeof(dk_i_l_lp_taps_im), - ((pu8_t) dk_i_l_lp_taps_im)); + ((u8 *) dk_i_l_lp_taps_im)); WR16(devAddr, ATV_TOP_CR_AMP_TH__A, ATV_TOP_CR_AMP_TH_DK); WR16(devAddr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_DK); WR16(devAddr, ATV_TOP_CR_CONT__A, @@ -9276,9 +9276,9 @@ trouble ? WR16(devAddr, IQM_RT_LO_INCR__A, 2225); /* TODO check with IS */ WR16(devAddr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M); WRB(devAddr, IQM_CF_TAP_RE0__A, sizeof(dk_i_l_lp_taps_re), - ((pu8_t) dk_i_l_lp_taps_re)); + ((u8 *) dk_i_l_lp_taps_re)); WRB(devAddr, IQM_CF_TAP_IM0__A, sizeof(dk_i_l_lp_taps_im), - ((pu8_t) dk_i_l_lp_taps_im)); + ((u8 *) dk_i_l_lp_taps_im)); WR16(devAddr, ATV_TOP_CR_AMP_TH__A, ATV_TOP_CR_AMP_TH_I); WR16(devAddr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_I); WR16(devAddr, ATV_TOP_CR_CONT__A, @@ -9306,9 +9306,9 @@ trouble ? WR16(devAddr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_L); WR16(devAddr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M); WRB(devAddr, IQM_CF_TAP_RE0__A, sizeof(dk_i_l_lp_taps_re), - ((pu8_t) dk_i_l_lp_taps_re)); + ((u8 *) dk_i_l_lp_taps_re)); WRB(devAddr, IQM_CF_TAP_IM0__A, sizeof(dk_i_l_lp_taps_im), - ((pu8_t) dk_i_l_lp_taps_im)); + ((u8 *) dk_i_l_lp_taps_im)); WR16(devAddr, ATV_TOP_CR_AMP_TH__A, 0x2); /* TODO check with IS */ WR16(devAddr, ATV_TOP_CR_CONT__A, (ATV_TOP_CR_CONT_CR_P_L | @@ -9337,9 +9337,9 @@ trouble ? WR16(devAddr, IQM_RT_LO_INCR__A, 2225); /* TODO check with IS */ WR16(devAddr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M); WRB(devAddr, IQM_CF_TAP_RE0__A, sizeof(dk_i_l_lp_taps_re), - ((pu8_t) dk_i_l_lp_taps_re)); + ((u8 *) dk_i_l_lp_taps_re)); WRB(devAddr, IQM_CF_TAP_IM0__A, sizeof(dk_i_l_lp_taps_im), - ((pu8_t) dk_i_l_lp_taps_im)); + ((u8 *) dk_i_l_lp_taps_im)); WR16(devAddr, ATV_TOP_CR_AMP_TH__A, 0x2); /* TODO check with IS */ WR16(devAddr, ATV_TOP_CR_CONT__A, (ATV_TOP_CR_CONT_CR_P_LP | @@ -9466,7 +9466,7 @@ SetATVChannel(pDRXDemodInstance_t demod, /* parameter */ NULL, /* result */ NULL }; - u16_t cmdResult = 0; + u16 cmdResult = 0; pDRXJData_t extAttr = NULL; struct i2c_device_addr *devAddr = NULL; @@ -9543,7 +9543,7 @@ GetATVChannel(pDRXDemodInstance_t demod, case DRX_STANDARD_PAL_SECAM_I: case DRX_STANDARD_PAL_SECAM_L: { - u16_t measuredOffset = 0; + u16 measuredOffset = 0; /* get measured frequency offset */ RR16(devAddr, ATV_TOP_CR_FREQ__A, &measuredOffset); @@ -9553,12 +9553,12 @@ GetATVChannel(pDRXDemodInstance_t demod, measuredOffset |= 0xFF80; } offset += - (DRXFrequency_t) (((s16_t) measuredOffset) * 10); + (DRXFrequency_t) (((s16) measuredOffset) * 10); break; } case DRX_STANDARD_PAL_SECAM_LP: { - u16_t measuredOffset = 0; + u16 measuredOffset = 0; /* get measured frequency offset */ RR16(devAddr, ATV_TOP_CR_FREQ__A, &measuredOffset); @@ -9568,7 +9568,7 @@ GetATVChannel(pDRXDemodInstance_t demod, measuredOffset |= 0xFF80; } offset -= - (DRXFrequency_t) (((s16_t) measuredOffset) * 10); + (DRXFrequency_t) (((s16) measuredOffset) * 10); } break; case DRX_STANDARD_FM: @@ -9610,30 +9610,30 @@ rw_error: * is not used ? */ static DRXStatus_t -GetAtvSigStrength(pDRXDemodInstance_t demod, pu16_t sigStrength) +GetAtvSigStrength(pDRXDemodInstance_t demod, u16 *sigStrength) { struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; /* All weights must add up to 100 (%) TODO: change weights when IF ctrl is available */ - u32_t digitalWeight = 50; /* 0 .. 100 */ - u32_t rfWeight = 50; /* 0 .. 100 */ - u32_t ifWeight = 0; /* 0 .. 100 */ - - u16_t digitalCurrGain = 0; - u32_t digitalMaxGain = 0; - u32_t digitalMinGain = 0; - u16_t rfCurrGain = 0; - u32_t rfMaxGain = 0x800; /* taken from ucode */ - u32_t rfMinGain = 0x7fff; - u16_t ifCurrGain = 0; - u32_t ifMaxGain = 0x800; /* taken from ucode */ - u32_t ifMinGain = 0x7fff; - - u32_t digitalStrength = 0; /* 0.. 100 */ - u32_t rfStrength = 0; /* 0.. 100 */ - u32_t ifStrength = 0; /* 0.. 100 */ + u32 digitalWeight = 50; /* 0 .. 100 */ + u32 rfWeight = 50; /* 0 .. 100 */ + u32 ifWeight = 0; /* 0 .. 100 */ + + u16 digitalCurrGain = 0; + u32 digitalMaxGain = 0; + u32 digitalMinGain = 0; + u16 rfCurrGain = 0; + u32 rfMaxGain = 0x800; /* taken from ucode */ + u32 rfMinGain = 0x7fff; + u16 ifCurrGain = 0; + u32 ifMaxGain = 0x800; /* taken from ucode */ + u32 ifMinGain = 0x7fff; + + u32 digitalStrength = 0; /* 0.. 100 */ + u32 rfStrength = 0; /* 0.. 100 */ + u32 ifStrength = 0; /* 0.. 100 */ devAddr = demod->myI2CDevAddr; extAttr = (pDRXJData_t) demod->myExtAttr; @@ -9665,17 +9665,17 @@ GetAtvSigStrength(pDRXDemodInstance_t demod, pu16_t sigStrength) /* clipping */ if (digitalCurrGain >= digitalMaxGain) - digitalCurrGain = (u16_t) digitalMaxGain; + digitalCurrGain = (u16) digitalMaxGain; if (digitalCurrGain <= digitalMinGain) - digitalCurrGain = (u16_t) digitalMinGain; + digitalCurrGain = (u16) digitalMinGain; if (ifCurrGain <= ifMaxGain) - ifCurrGain = (u16_t) ifMaxGain; + ifCurrGain = (u16) ifMaxGain; if (ifCurrGain >= ifMinGain) - ifCurrGain = (u16_t) ifMinGain; + ifCurrGain = (u16) ifMinGain; if (rfCurrGain <= rfMaxGain) - rfCurrGain = (u16_t) rfMaxGain; + rfCurrGain = (u16) rfMaxGain; if (rfCurrGain >= rfMinGain) - rfCurrGain = (u16_t) rfMinGain; + rfCurrGain = (u16) rfMinGain; /* TODO: use SCU_RAM_ATV_RAGC_HR__A to shift max and min in case of clipping at ADC */ @@ -9684,20 +9684,20 @@ GetAtvSigStrength(pDRXDemodInstance_t demod, pu16_t sigStrength) /* Digital gain */ /* TODO: ADC clipping not handled */ - digitalStrength = (100 * (digitalMaxGain - (u32_t) digitalCurrGain)) / + digitalStrength = (100 * (digitalMaxGain - (u32) digitalCurrGain)) / (digitalMaxGain - digitalMinGain); /* TODO: IF gain not implemented yet in microcode, check after impl. */ - ifStrength = (100 * ((u32_t) ifCurrGain - ifMaxGain)) / + ifStrength = (100 * ((u32) ifCurrGain - ifMaxGain)) / (ifMinGain - ifMaxGain); /* Rf gain */ /* TODO: ADC clipping not handled */ - rfStrength = (100 * ((u32_t) rfCurrGain - rfMaxGain)) / + rfStrength = (100 * ((u32) rfCurrGain - rfMaxGain)) / (rfMinGain - rfMaxGain); /* Compute a weighted signal strength (in %) */ - *sigStrength = (u16_t) (digitalWeight * digitalStrength + + *sigStrength = (u16) (digitalWeight * digitalStrength + rfWeight * rfStrength + ifWeight * ifStrength); *sigStrength /= 100; @@ -9722,7 +9722,7 @@ static DRXStatus_t AtvSigQuality(pDRXDemodInstance_t demod, pDRXSigQuality_t sigQuality) { struct i2c_device_addr *devAddr = NULL; - u16_t qualityIndicator = 0; + u16 qualityIndicator = 0; devAddr = demod->myI2CDevAddr; @@ -9831,14 +9831,14 @@ rw_error: * \return DRXStatus_t. * */ -static DRXStatus_t AUDGetModus(pDRXDemodInstance_t demod, pu16_t modus) +static DRXStatus_t AUDGetModus(pDRXDemodInstance_t demod, u16 *modus) { struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; - u16_t rModus = 0; - u16_t rModusHi = 0; - u16_t rModusLo = 0; + u16 rModus = 0; + u16 rModusHi = 0; + u16 rModusLo = 0; if (modus == NULL) { return DRX_STS_INVALID_ARG; @@ -9882,10 +9882,10 @@ AUDCtrlGetCfgRDS(pDRXDemodInstance_t demod, pDRXCfgAudRDS_t status) struct i2c_device_addr *addr = NULL; pDRXJData_t extAttr = NULL; - u16_t rRDSArrayCntInit = 0; - u16_t rRDSArrayCntCheck = 0; - u16_t rRDSData = 0; - u16_t RDSDataCnt = 0; + u16 rRDSArrayCntInit = 0; + u16 rRDSArrayCntCheck = 0; + u16 rRDSData = 0; + u16 RDSDataCnt = 0; addr = (struct i2c_device_addr *) demod->myI2CDevAddr; extAttr = (pDRXJData_t) demod->myExtAttr; @@ -9952,7 +9952,7 @@ AUDCtrlGetCarrierDetectStatus(pDRXDemodInstance_t demod, pDRXAudStatus_t status) pDRXJData_t extAttr = NULL; struct i2c_device_addr *devAddr = NULL; - u16_t rData = 0; + u16 rData = 0; if (status == NULL) { return DRX_STS_INVALID_ARG; @@ -10030,7 +10030,7 @@ AUDCtrlGetStatus(pDRXDemodInstance_t demod, pDRXAudStatus_t status) pDRXJData_t extAttr = NULL; struct i2c_device_addr *devAddr = NULL; DRXCfgAudRDS_t rds = { FALSE, {0} }; - u16_t rData = 0; + u16 rData = 0; if (status == NULL) { return DRX_STS_INVALID_ARG; @@ -10050,7 +10050,7 @@ AUDCtrlGetStatus(pDRXDemodInstance_t demod, pDRXAudStatus_t status) /* fmIdent */ RR16(devAddr, AUD_DSP_RD_FM_IDENT_VALUE__A, &rData); rData >>= AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__B; - status->fmIdent = (s8_t) rData; + status->fmIdent = (s8) rData; return DRX_STS_OK; rw_error: @@ -10071,10 +10071,10 @@ AUDCtrlGetCfgVolume(pDRXDemodInstance_t demod, pDRXCfgAudVolume_t volume) struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; - u16_t rVolume = 0; - u16_t rAVC = 0; - u16_t rStrengthLeft = 0; - u16_t rStrengthRight = 0; + u16 rVolume = 0; + u16 rAVC = 0; + u16 rStrengthLeft = 0; + u16 rStrengthRight = 0; if (volume == NULL) { return DRX_STS_INVALID_ARG; @@ -10167,7 +10167,7 @@ AUDCtrlGetCfgVolume(pDRXDemodInstance_t demod, pDRXCfgAudVolume_t volume) } /* reference level */ - volume->avcRefLevel = (u16_t) ((rAVC & AUD_DSP_WR_AVC_AVC_REF_LEV__M) >> + volume->avcRefLevel = (u16) ((rAVC & AUD_DSP_WR_AVC_AVC_REF_LEV__M) >> AUD_DSP_WR_AVC_AVC_REF_LEV__B); /* read qpeak registers and calculate strength of left and right carrier */ @@ -10178,12 +10178,12 @@ AUDCtrlGetCfgVolume(pDRXDemodInstance_t demod, pDRXCfgAudVolume_t volume) /* QP vaues */ /* left carrier */ RR16(devAddr, AUD_DSP_RD_QPEAK_L__A, &rStrengthLeft); - volume->strengthLeft = (((s16_t) Log10Times100(rStrengthLeft)) - + volume->strengthLeft = (((s16) Log10Times100(rStrengthLeft)) - AUD_CARRIER_STRENGTH_QP_0DB_LOG10T100) / 5; /* right carrier */ RR16(devAddr, AUD_DSP_RD_QPEAK_R__A, &rStrengthRight); - volume->strengthRight = (((s16_t) Log10Times100(rStrengthRight)) - + volume->strengthRight = (((s16) Log10Times100(rStrengthRight)) - AUD_CARRIER_STRENGTH_QP_0DB_LOG10T100) / 5; return DRX_STS_OK; @@ -10205,8 +10205,8 @@ AUDCtrlSetCfgVolume(pDRXDemodInstance_t demod, pDRXCfgAudVolume_t volume) struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; - u16_t wVolume = 0; - u16_t wAVC = 0; + u16 wVolume = 0; + u16 wAVC = 0; if (volume == NULL) { return DRX_STS_INVALID_ARG; @@ -10231,14 +10231,14 @@ AUDCtrlSetCfgVolume(pDRXDemodInstance_t demod, pDRXCfgAudVolume_t volume) RR16(devAddr, AUD_DSP_WR_VOLUME__A, &wVolume); /* clear the volume mask */ - wVolume &= (u16_t) ~ AUD_DSP_WR_VOLUME_VOL_MAIN__M; + wVolume &= (u16) ~ AUD_DSP_WR_VOLUME_VOL_MAIN__M; if (volume->mute == TRUE) { /* mute */ /* mute overrules volume */ - wVolume |= (u16_t) (0); + wVolume |= (u16) (0); } else { - wVolume |= (u16_t) ((volume->volume + AUD_VOLUME_ZERO_DB) << + wVolume |= (u16) ((volume->volume + AUD_VOLUME_ZERO_DB) << AUD_DSP_WR_VOLUME_VOL_MAIN__B); } @@ -10248,8 +10248,8 @@ AUDCtrlSetCfgVolume(pDRXDemodInstance_t demod, pDRXCfgAudVolume_t volume) RR16(devAddr, AUD_DSP_WR_AVC__A, &wAVC); /* clear masks that require writing */ - wAVC &= (u16_t) ~ AUD_DSP_WR_AVC_AVC_ON__M; - wAVC &= (u16_t) ~ AUD_DSP_WR_AVC_AVC_DECAY__M; + wAVC &= (u16) ~ AUD_DSP_WR_AVC_AVC_ON__M; + wAVC &= (u16) ~ AUD_DSP_WR_AVC_AVC_DECAY__M; if (volume->avcMode == DRX_AUD_AVC_OFF) { wAVC |= (AUD_DSP_WR_AVC_AVC_ON_OFF); @@ -10277,7 +10277,7 @@ AUDCtrlSetCfgVolume(pDRXDemodInstance_t demod, pDRXCfgAudVolume_t volume) } /* max attenuation */ - wAVC &= (u16_t) ~ AUD_DSP_WR_AVC_AVC_MAX_ATT__M; + wAVC &= (u16) ~ AUD_DSP_WR_AVC_AVC_MAX_ATT__M; switch (volume->avcMaxAtten) { case DRX_AUD_AVC_MAX_ATTEN_12DB: wAVC |= AUD_DSP_WR_AVC_AVC_MAX_ATT_12DB; @@ -10293,7 +10293,7 @@ AUDCtrlSetCfgVolume(pDRXDemodInstance_t demod, pDRXCfgAudVolume_t volume) } /* max gain */ - wAVC &= (u16_t) ~ AUD_DSP_WR_AVC_AVC_MAX_GAIN__M; + wAVC &= (u16) ~ AUD_DSP_WR_AVC_AVC_MAX_GAIN__M; switch (volume->avcMaxGain) { case DRX_AUD_AVC_MAX_GAIN_0DB: wAVC |= AUD_DSP_WR_AVC_AVC_MAX_GAIN_0DB; @@ -10313,8 +10313,8 @@ AUDCtrlSetCfgVolume(pDRXDemodInstance_t demod, pDRXCfgAudVolume_t volume) return DRX_STS_INVALID_ARG; } - wAVC &= (u16_t) ~ AUD_DSP_WR_AVC_AVC_REF_LEV__M; - wAVC |= (u16_t) (volume->avcRefLevel << AUD_DSP_WR_AVC_AVC_REF_LEV__B); + wAVC &= (u16) ~ AUD_DSP_WR_AVC_AVC_REF_LEV__M; + wAVC |= (u16) (volume->avcRefLevel << AUD_DSP_WR_AVC_AVC_REF_LEV__B); WR16(devAddr, AUD_DSP_WR_AVC__A, wAVC); @@ -10340,8 +10340,8 @@ AUDCtrlGetCfgOutputI2S(pDRXDemodInstance_t demod, pDRXCfgI2SOutput_t output) struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; - u16_t wI2SConfig = 0; - u16_t rI2SFreq = 0; + u16 wI2SConfig = 0; + u16 rI2SFreq = 0; if (output == NULL) { return DRX_STS_INVALID_ARG; @@ -10443,11 +10443,11 @@ AUDCtrlSetCfgOutputI2S(pDRXDemodInstance_t demod, pDRXCfgI2SOutput_t output) struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; - u16_t wI2SConfig = 0; - u16_t wI2SPadsDataDa = 0; - u16_t wI2SPadsDataCl = 0; - u16_t wI2SPadsDataWs = 0; - u32_t wI2SFreq = 0; + u16 wI2SConfig = 0; + u16 wI2SPadsDataDa = 0; + u16 wI2SPadsDataCl = 0; + u16 wI2SPadsDataWs = 0; + u32 wI2SFreq = 0; if (output == NULL) { return DRX_STS_INVALID_ARG; @@ -10465,7 +10465,7 @@ AUDCtrlSetCfgOutputI2S(pDRXDemodInstance_t demod, pDRXCfgI2SOutput_t output) RR16(devAddr, AUD_DEM_RAM_I2S_CONFIG2__A, &wI2SConfig); /* I2S mode */ - wI2SConfig &= (u16_t) ~ AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__M; + wI2SConfig &= (u16) ~ AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__M; switch (output->mode) { case DRX_I2S_MODE_MASTER: @@ -10479,7 +10479,7 @@ AUDCtrlSetCfgOutputI2S(pDRXDemodInstance_t demod, pDRXCfgI2SOutput_t output) } /* I2S format */ - wI2SConfig &= (u16_t) ~ AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__M; + wI2SConfig &= (u16) ~ AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__M; switch (output->format) { case DRX_I2S_FORMAT_WS_ADVANCED: @@ -10493,7 +10493,7 @@ AUDCtrlSetCfgOutputI2S(pDRXDemodInstance_t demod, pDRXCfgI2SOutput_t output) } /* I2S word length */ - wI2SConfig &= (u16_t) ~ AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__M; + wI2SConfig &= (u16) ~ AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__M; switch (output->wordLength) { case DRX_I2S_WORDLENGTH_16: @@ -10507,7 +10507,7 @@ AUDCtrlSetCfgOutputI2S(pDRXDemodInstance_t demod, pDRXCfgI2SOutput_t output) } /* I2S polarity */ - wI2SConfig &= (u16_t) ~ AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__M; + wI2SConfig &= (u16) ~ AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__M; switch (output->polarity) { case DRX_I2S_POLARITY_LEFT: wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL_LEFT_HIGH; @@ -10520,7 +10520,7 @@ AUDCtrlSetCfgOutputI2S(pDRXDemodInstance_t demod, pDRXCfgI2SOutput_t output) } /* I2S output enabled */ - wI2SConfig &= (u16_t) ~ AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__M; + wI2SConfig &= (u16) ~ AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__M; if (output->outputEnable == TRUE) { wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_ENABLE; } else { @@ -10548,7 +10548,7 @@ AUDCtrlSetCfgOutputI2S(pDRXDemodInstance_t demod, pDRXCfgI2SOutput_t output) } WR16(devAddr, AUD_DEM_WR_I2S_CONFIG2__A, wI2SConfig); - WR16(devAddr, AUD_DSP_WR_I2S_OUT_FS__A, (u16_t) wI2SFreq); + WR16(devAddr, AUD_DSP_WR_I2S_OUT_FS__A, (u16) wI2SFreq); /* configure I2S output pads for master or slave mode */ WR16(devAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); @@ -10599,7 +10599,7 @@ AUDCtrlGetCfgAutoSound(pDRXDemodInstance_t demod, struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; pDRXJData_t extAttr = (pDRXJData_t) NULL; - u16_t rModus = 0; + u16 rModus = 0; if (autoSound == NULL) { return DRX_STS_INVALID_ARG; @@ -10656,8 +10656,8 @@ AUDCtrSetlCfgAutoSound(pDRXDemodInstance_t demod, struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; pDRXJData_t extAttr = (pDRXJData_t) NULL; - u16_t rModus = 0; - u16_t wModus = 0; + u16 rModus = 0; + u16 wModus = 0; if (autoSound == NULL) { return DRX_STS_INVALID_ARG; @@ -10676,8 +10676,8 @@ AUDCtrSetlCfgAutoSound(pDRXDemodInstance_t demod, wModus = rModus; /* clear ASS & ASC bits */ - wModus &= (u16_t) ~ AUD_DEM_WR_MODUS_MOD_ASS__M; - wModus &= (u16_t) ~ AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__M; + wModus &= (u16) ~ AUD_DEM_WR_MODUS_MOD_ASS__M; + wModus &= (u16) ~ AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__M; switch (*autoSound) { case DRX_AUD_AUTO_SOUND_OFF: @@ -10721,9 +10721,9 @@ AUDCtrlGetCfgASSThres(pDRXDemodInstance_t demod, pDRXCfgAudASSThres_t thres) struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; pDRXJData_t extAttr = (pDRXJData_t) NULL; - u16_t thresA2 = 0; - u16_t thresBtsc = 0; - u16_t thresNicam = 0; + u16 thresA2 = 0; + u16 thresBtsc = 0; + u16 thresNicam = 0; if (thres == NULL) { return DRX_STS_INVALID_ARG; @@ -10804,21 +10804,21 @@ AUDCtrlGetCfgCarrier(pDRXDemodInstance_t demod, pDRXCfgAudCarriers_t carriers) struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; pDRXJData_t extAttr = (pDRXJData_t) NULL; - u16_t wModus = 0; + u16 wModus = 0; - u16_t dcoAHi = 0; - u16_t dcoALo = 0; - u16_t dcoBHi = 0; - u16_t dcoBLo = 0; + u16 dcoAHi = 0; + u16 dcoALo = 0; + u16 dcoBHi = 0; + u16 dcoBLo = 0; - u32_t valA = 0; - u32_t valB = 0; + u32 valA = 0; + u32 valB = 0; - u16_t dcLvlA = 0; - u16_t dcLvlB = 0; + u16 dcLvlA = 0; + u16 dcLvlB = 0; - u16_t cmThesA = 0; - u16_t cmThesB = 0; + u16 cmThesA = 0; + u16 cmThesB = 0; if (carriers == NULL) { return DRX_STS_INVALID_ARG; @@ -10867,8 +10867,8 @@ AUDCtrlGetCfgCarrier(pDRXDemodInstance_t demod, pDRXCfgAudCarriers_t carriers) RR16(devAddr, AUD_DEM_RAM_DCO_B_HI__A, &dcoBHi); RR16(devAddr, AUD_DEM_RAM_DCO_B_LO__A, &dcoBLo); - valA = (((u32_t) dcoAHi) << 12) | ((u32_t) dcoALo & 0xFFF); - valB = (((u32_t) dcoBHi) << 12) | ((u32_t) dcoBLo & 0xFFF); + valA = (((u32) dcoAHi) << 12) | ((u32) dcoALo & 0xFFF); + valB = (((u32) dcoBHi) << 12) | ((u32) dcoBLo & 0xFFF); /* Multiply by 20250 * 1>>24 ~= 2 / 1657 */ carriers->a.dco = DRX_S24TODRXFREQ(valA) * 2L / 1657L; @@ -10909,16 +10909,16 @@ AUDCtrlSetCfgCarrier(pDRXDemodInstance_t demod, pDRXCfgAudCarriers_t carriers) struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; pDRXJData_t extAttr = (pDRXJData_t) NULL; - u16_t wModus = 0; - u16_t rModus = 0; + u16 wModus = 0; + u16 rModus = 0; - u16_t dcoAHi = 0; - u16_t dcoALo = 0; - u16_t dcoBHi = 0; - u16_t dcoBLo = 0; + u16 dcoAHi = 0; + u16 dcoALo = 0; + u16 dcoBHi = 0; + u16 dcoBLo = 0; - s32_t valA = 0; - s32_t valB = 0; + s32 valA = 0; + s32 valB = 0; if (carriers == NULL) { return DRX_STS_INVALID_ARG; @@ -10936,7 +10936,7 @@ AUDCtrlSetCfgCarrier(pDRXDemodInstance_t demod, pDRXCfgAudCarriers_t carriers) CHK_ERROR(AUDGetModus(demod, &rModus)); wModus = rModus; - wModus &= (u16_t) ~ AUD_DEM_WR_MODUS_MOD_CM_A__M; + wModus &= (u16) ~ AUD_DEM_WR_MODUS_MOD_CM_A__M; /* Behaviour of primary audio channel */ switch (carriers->a.opt) { case DRX_NO_CARRIER_MUTE: @@ -10951,7 +10951,7 @@ AUDCtrlSetCfgCarrier(pDRXDemodInstance_t demod, pDRXCfgAudCarriers_t carriers) } /* Behaviour of secondary audio channel */ - wModus &= (u16_t) ~ AUD_DEM_WR_MODUS_MOD_CM_B__M; + wModus &= (u16) ~ AUD_DEM_WR_MODUS_MOD_CM_B__M; switch (carriers->b.opt) { case DRX_NO_CARRIER_MUTE: wModus |= AUD_DEM_WR_MODUS_MOD_CM_B_MUTE; @@ -10970,13 +10970,13 @@ AUDCtrlSetCfgCarrier(pDRXDemodInstance_t demod, pDRXCfgAudCarriers_t carriers) } /* frequency adjustment for primary & secondary audio channel */ - valA = (s32_t) ((carriers->a.dco) * 1657L / 2); - valB = (s32_t) ((carriers->b.dco) * 1657L / 2); + valA = (s32) ((carriers->a.dco) * 1657L / 2); + valB = (s32) ((carriers->b.dco) * 1657L / 2); - dcoAHi = (u16_t) ((valA >> 12) & 0xFFF); - dcoALo = (u16_t) (valA & 0xFFF); - dcoBHi = (u16_t) ((valB >> 12) & 0xFFF); - dcoBLo = (u16_t) (valB & 0xFFF); + dcoAHi = (u16) ((valA >> 12) & 0xFFF); + dcoALo = (u16) (valA & 0xFFF); + dcoBHi = (u16) ((valB >> 12) & 0xFFF); + dcoBLo = (u16) (valB & 0xFFF); WR16(devAddr, AUD_DEM_WR_DCO_A_HI__A, dcoAHi); WR16(devAddr, AUD_DEM_WR_DCO_A_LO__A, dcoALo); @@ -11009,8 +11009,8 @@ AUDCtrlGetCfgMixer(pDRXDemodInstance_t demod, pDRXCfgAudMixer_t mixer) struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; pDRXJData_t extAttr = (pDRXJData_t) NULL; - u16_t srcI2SMatr = 0; - u16_t fmMatr = 0; + u16 srcI2SMatr = 0; + u16 fmMatr = 0; if (mixer == NULL) { return DRX_STS_INVALID_ARG; @@ -11104,8 +11104,8 @@ AUDCtrlSetCfgMixer(pDRXDemodInstance_t demod, pDRXCfgAudMixer_t mixer) struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; pDRXJData_t extAttr = (pDRXJData_t) NULL; - u16_t srcI2SMatr = 0; - u16_t fmMatr = 0; + u16 srcI2SMatr = 0; + u16 fmMatr = 0; if (mixer == NULL) { return DRX_STS_INVALID_ARG; @@ -11122,7 +11122,7 @@ AUDCtrlSetCfgMixer(pDRXDemodInstance_t demod, pDRXCfgAudMixer_t mixer) /* Source Selctor */ RR16(devAddr, AUD_DSP_WR_SRC_I2S_MATR__A, &srcI2SMatr); - srcI2SMatr &= (u16_t) ~ AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__M; + srcI2SMatr &= (u16) ~ AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__M; switch (mixer->sourceI2S) { case DRX_AUD_SRC_MONO: @@ -11142,7 +11142,7 @@ AUDCtrlSetCfgMixer(pDRXDemodInstance_t demod, pDRXCfgAudMixer_t mixer) } /* Matrix */ - srcI2SMatr &= (u16_t) ~ AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__M; + srcI2SMatr &= (u16) ~ AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__M; switch (mixer->matrixI2S) { case DRX_AUD_I2S_MATRIX_MONO: srcI2SMatr |= AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_MONO; @@ -11164,7 +11164,7 @@ AUDCtrlSetCfgMixer(pDRXDemodInstance_t demod, pDRXCfgAudMixer_t mixer) /* FM Matrix */ RR16(devAddr, AUD_DEM_WR_FM_MATRIX__A, &fmMatr); - fmMatr &= (u16_t) ~ AUD_DEM_WR_FM_MATRIX__M; + fmMatr &= (u16) ~ AUD_DEM_WR_FM_MATRIX__M; switch (mixer->matrixFm) { case DRX_AUD_FM_MATRIX_NO_MATRIX: fmMatr |= AUD_DEM_WR_FM_MATRIX_NO_MATRIX; @@ -11212,7 +11212,7 @@ AUDCtrlSetCfgAVSync(pDRXDemodInstance_t demod, pDRXCfgAudAVSync_t avSync) struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; pDRXJData_t extAttr = (pDRXJData_t) NULL; - u16_t wAudVidSync = 0; + u16 wAudVidSync = 0; if (avSync == NULL) { return DRX_STS_INVALID_ARG; @@ -11230,7 +11230,7 @@ AUDCtrlSetCfgAVSync(pDRXDemodInstance_t demod, pDRXCfgAudAVSync_t avSync) /* audio/video synchronisation */ RR16(devAddr, AUD_DSP_WR_AV_SYNC__A, &wAudVidSync); - wAudVidSync &= (u16_t) ~ AUD_DSP_WR_AV_SYNC_AV_ON__M; + wAudVidSync &= (u16) ~ AUD_DSP_WR_AV_SYNC_AV_ON__M; if (*avSync == DRX_AUD_AVSYNC_OFF) { wAudVidSync |= AUD_DSP_WR_AV_SYNC_AV_ON_DISABLE; @@ -11238,7 +11238,7 @@ AUDCtrlSetCfgAVSync(pDRXDemodInstance_t demod, pDRXCfgAudAVSync_t avSync) wAudVidSync |= AUD_DSP_WR_AV_SYNC_AV_ON_ENABLE; } - wAudVidSync &= (u16_t) ~ AUD_DSP_WR_AV_SYNC_AV_STD_SEL__M; + wAudVidSync &= (u16) ~ AUD_DSP_WR_AV_SYNC_AV_STD_SEL__M; switch (*avSync) { case DRX_AUD_AVSYNC_NTSC: @@ -11277,7 +11277,7 @@ AUDCtrlGetCfgAVSync(pDRXDemodInstance_t demod, pDRXCfgAudAVSync_t avSync) struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; pDRXJData_t extAttr = (pDRXJData_t) NULL; - u16_t wAudVidSync = 0; + u16 wAudVidSync = 0; if (avSync == NULL) { return DRX_STS_INVALID_ARG; @@ -11334,7 +11334,7 @@ AUDCtrlGetCfgDev(pDRXDemodInstance_t demod, pDRXCfgAudDeviation_t dev) struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; pDRXJData_t extAttr = (pDRXJData_t) NULL; - u16_t rModus = 0; + u16 rModus = 0; if (dev == NULL) { return DRX_STS_INVALID_ARG; @@ -11375,8 +11375,8 @@ AUDCtrlSetCfgDev(pDRXDemodInstance_t demod, pDRXCfgAudDeviation_t dev) struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; pDRXJData_t extAttr = (pDRXJData_t) NULL; - u16_t wModus = 0; - u16_t rModus = 0; + u16 wModus = 0; + u16 rModus = 0; if (dev == NULL) { return DRX_STS_INVALID_ARG; @@ -11389,7 +11389,7 @@ AUDCtrlSetCfgDev(pDRXDemodInstance_t demod, pDRXCfgAudDeviation_t dev) wModus = rModus; - wModus &= (u16_t) ~ AUD_DEM_WR_MODUS_MOD_HDEV_A__M; + wModus &= (u16) ~ AUD_DEM_WR_MODUS_MOD_HDEV_A__M; switch (*dev) { case DRX_AUD_DEVIATION_NORMAL: @@ -11428,8 +11428,8 @@ AUDCtrlGetCfgPrescale(pDRXDemodInstance_t demod, pDRXCfgAudPrescale_t presc) struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; pDRXJData_t extAttr = (pDRXJData_t) NULL; - u16_t rMaxFMDeviation = 0; - u16_t rNicamPrescaler = 0; + u16 rMaxFMDeviation = 0; + u16 rNicamPrescaler = 0; if (presc == NULL) { return DRX_STS_INVALID_ARG; @@ -11477,10 +11477,10 @@ AUDCtrlGetCfgPrescale(pDRXDemodInstance_t demod, pDRXCfgAudPrescale_t presc) presc->nicamGain = -241; } else { - presc->nicamGain = (s16_t) (((s32_t) + presc->nicamGain = (s16) (((s32) (Log10Times100 (10 * rNicamPrescaler * - rNicamPrescaler)) - (s32_t) + rNicamPrescaler)) - (s32) (Log10Times100(10 * 16 * 16)))); } @@ -11503,8 +11503,8 @@ AUDCtrlSetCfgPrescale(pDRXDemodInstance_t demod, pDRXCfgAudPrescale_t presc) struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; pDRXJData_t extAttr = (pDRXJData_t) NULL; - u16_t wMaxFMDeviation = 0; - u16_t nicamPrescaler; + u16 wMaxFMDeviation = 0; + u16 nicamPrescaler; if (presc == NULL) { return DRX_STS_INVALID_ARG; @@ -11520,7 +11520,7 @@ AUDCtrlSetCfgPrescale(pDRXDemodInstance_t demod, pDRXCfgAudPrescale_t presc) } /* setting of max FM deviation */ - wMaxFMDeviation = (u16_t) (Frac(3600UL, presc->fmDeviation, 0)); + wMaxFMDeviation = (u16) (Frac(3600UL, presc->fmDeviation, 0)); wMaxFMDeviation <<= AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__B; if (wMaxFMDeviation >= AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_28_KHZ_FM_DEVIATION) { @@ -11547,7 +11547,7 @@ AUDCtrlSetCfgPrescale(pDRXDemodInstance_t demod, pDRXCfgAudPrescale_t presc) = 10^( G0.1dB + 200log10(16)) / 200 ) */ - nicamPrescaler = (u16_t) + nicamPrescaler = (u16) ((dB2LinTimes100(presc->nicamGain + 241UL) + 50UL) / 100UL); /* clip result */ @@ -11585,9 +11585,9 @@ static DRXStatus_t AUDCtrlBeep(pDRXDemodInstance_t demod, pDRXAudBeep_t beep) struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; pDRXJData_t extAttr = (pDRXJData_t) NULL; - u16_t theBeep = 0; - u16_t volume = 0; - u32_t frequency = 0; + u16 theBeep = 0; + u16 volume = 0; + u32 frequency = 0; if (beep == NULL) { return DRX_STS_INVALID_ARG; @@ -11610,14 +11610,14 @@ static DRXStatus_t AUDCtrlBeep(pDRXDemodInstance_t demod, pDRXAudBeep_t beep) return DRX_STS_INVALID_ARG; } - volume = (u16_t) beep->volume + 127; + volume = (u16) beep->volume + 127; theBeep |= volume << AUD_DSP_WR_BEEPER_BEEP_VOLUME__B; - frequency = ((u32_t) beep->frequency) * 23 / 500; + frequency = ((u32) beep->frequency) * 23 / 500; if (frequency > AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__M) { frequency = AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__M; } - theBeep |= (u16_t) frequency; + theBeep |= (u16) frequency; if (beep->mute == TRUE) { theBeep = 0; @@ -11645,13 +11645,13 @@ AUDCtrlSetStandard(pDRXDemodInstance_t demod, pDRXAudStandard_t standard) pDRXJData_t extAttr = NULL; DRXStandard_t currentStandard = DRX_STANDARD_UNKNOWN; - u16_t wStandard = 0; - u16_t wModus = 0; - u16_t rModus = 0; + u16 wStandard = 0; + u16 wModus = 0; + u16 rModus = 0; Bool_t muteBuffer = FALSE; - s16_t volumeBuffer = 0; - u16_t wVolume = 0; + s16 volumeBuffer = 0; + u16 wVolume = 0; if (standard == NULL) { return DRX_STS_INVALID_ARG; @@ -11745,7 +11745,7 @@ AUDCtrlSetStandard(pDRXDemodInstance_t demod, pDRXAudStandard_t standard) /* we need the current standard here */ currentStandard = extAttr->standard; - wModus &= (u16_t) ~ AUD_DEM_WR_MODUS_MOD_6_5MHZ__M; + wModus &= (u16) ~ AUD_DEM_WR_MODUS_MOD_6_5MHZ__M; if ((currentStandard == DRX_STANDARD_PAL_SECAM_L) || (currentStandard == DRX_STANDARD_PAL_SECAM_LP)) { @@ -11754,7 +11754,7 @@ AUDCtrlSetStandard(pDRXDemodInstance_t demod, pDRXAudStandard_t standard) wModus |= (AUD_DEM_WR_MODUS_MOD_6_5MHZ_D_K); } - wModus &= (u16_t) ~ AUD_DEM_WR_MODUS_MOD_4_5MHZ__M; + wModus &= (u16) ~ AUD_DEM_WR_MODUS_MOD_4_5MHZ__M; if (currentStandard == DRX_STANDARD_NTSC) { wModus |= (AUD_DEM_WR_MODUS_MOD_4_5MHZ_M_BTSC); @@ -11765,7 +11765,7 @@ AUDCtrlSetStandard(pDRXDemodInstance_t demod, pDRXAudStandard_t standard) } - wModus &= (u16_t) ~ AUD_DEM_WR_MODUS_MOD_FMRADIO__M; + wModus &= (u16) ~ AUD_DEM_WR_MODUS_MOD_FMRADIO__M; /* just get hardcoded deemphasis and activate here */ if (extAttr->audData.deemph == DRX_AUD_FM_DEEMPH_50US) { @@ -11774,7 +11774,7 @@ AUDCtrlSetStandard(pDRXDemodInstance_t demod, pDRXAudStandard_t standard) wModus |= (AUD_DEM_WR_MODUS_MOD_FMRADIO_US_75U); } - wModus &= (u16_t) ~ AUD_DEM_WR_MODUS_MOD_BTSC__M; + wModus &= (u16) ~ AUD_DEM_WR_MODUS_MOD_BTSC__M; if (extAttr->audData.btscDetect == DRX_BTSC_STEREO) { wModus |= (AUD_DEM_WR_MODUS_MOD_BTSC_BTSC_STEREO); } else { /* DRX_BTSC_MONO_AND_SAP */ @@ -11795,7 +11795,7 @@ AUDCtrlSetStandard(pDRXDemodInstance_t demod, pDRXAudStandard_t standard) /**************************************************************************/ extAttr->audData.volume.mute = muteBuffer; if (extAttr->audData.volume.mute == FALSE) { - wVolume |= (u16_t) ((volumeBuffer + AUD_VOLUME_ZERO_DB) << + wVolume |= (u16) ((volumeBuffer + AUD_VOLUME_ZERO_DB) << AUD_DSP_WR_VOLUME_VOL_MAIN__B); WR16(devAddr, AUD_DSP_WR_VOLUME__A, wVolume); } @@ -11822,7 +11822,7 @@ AUDCtrlGetStandard(pDRXDemodInstance_t demod, pDRXAudStandard_t standard) struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; - u16_t rData = 0; + u16 rData = 0; if (standard == NULL) { return DRX_STS_INVALID_ARG; @@ -12000,8 +12000,8 @@ GetOOBLockStatus(pDRXDemodInstance_t demod, struct i2c_device_addr *devAddr, pDRXLockStatus_t oobLock) { DRXJSCUCmd_t scuCmd; - u16_t cmdResult[2]; - u16_t OOBLockState; + u16 cmdResult[2]; + u16 OOBLockState; *oobLock = DRX_NOT_LOCKED; @@ -12051,7 +12051,7 @@ rw_error: * */ static DRXStatus_t -GetOOBSymbolRateOffset(struct i2c_device_addr *devAddr, ps32_t SymbolRateOffset) +GetOOBSymbolRateOffset(struct i2c_device_addr *devAddr, s32 *SymbolRateOffset) { /* offset = -{(timingOffset/2^19)*(symbolRate/12,656250MHz)}*10^6 [ppm] */ /* offset = -{(timingOffset/2^19)*(symbolRate/12656250)}*10^6 [ppm] */ @@ -12064,11 +12064,11 @@ GetOOBSymbolRateOffset(struct i2c_device_addr *devAddr, ps32_t SymbolRateOffset) /* trim 12656250/15625 = 810 */ /* offset = -{(timingOffset*(symbolRate * 2^-5))/(2^8*810)} [ppm] */ /* offset = -[(symbolRate * 2^-5)*(timingOffset)/(2^8)]/810 [ppm] */ - s32_t timingOffset = 0; - u32_t unsignedTimingOffset = 0; - s32_t divisionFactor = 810; - u16_t data = 0; - u32_t symbolRate = 0; + s32 timingOffset = 0; + u32 unsignedTimingOffset = 0; + s32 divisionFactor = 810; + u16 data = 0; + u32 symbolRate = 0; Bool_t negative = FALSE; *SymbolRateOffset = 0; @@ -12099,10 +12099,10 @@ GetOOBSymbolRateOffset(struct i2c_device_addr *devAddr, ps32_t SymbolRateOffset) if (data == 0x8000) unsignedTimingOffset = 32768; else - unsignedTimingOffset = 0x00007FFF & (u32_t) (-data); + unsignedTimingOffset = 0x00007FFF & (u32) (-data); negative = TRUE; } else - unsignedTimingOffset = (u32_t) data; + unsignedTimingOffset = (u32) data; symbolRate = symbolRate >> 5; unsignedTimingOffset = (unsignedTimingOffset * symbolRate); @@ -12110,9 +12110,9 @@ GetOOBSymbolRateOffset(struct i2c_device_addr *devAddr, ps32_t SymbolRateOffset) unsignedTimingOffset = Frac(unsignedTimingOffset, divisionFactor, FRAC_ROUND); if (negative) - timingOffset = (s32_t) unsignedTimingOffset; + timingOffset = (s32) unsignedTimingOffset; else - timingOffset = -(s32_t) unsignedTimingOffset; + timingOffset = -(s32) unsignedTimingOffset; *SymbolRateOffset = timingOffset; @@ -12134,17 +12134,17 @@ rw_error: static DRXStatus_t GetOOBFreqOffset(pDRXDemodInstance_t demod, pDRXFrequency_t freqOffset) { - u16_t data = 0; - u16_t rot = 0; - u16_t symbolRateReg = 0; - u32_t symbolRate = 0; - s32_t coarseFreqOffset = 0; - s32_t fineFreqOffset = 0; - s32_t fineSign = 1; - s32_t coarseSign = 1; - u32_t data64Hi = 0; - u32_t data64Lo = 0; - u32_t tempFreqOffset = 0; + u16 data = 0; + u16 rot = 0; + u16 symbolRateReg = 0; + u32 symbolRate = 0; + s32 coarseFreqOffset = 0; + s32 fineFreqOffset = 0; + s32 fineSign = 1; + s32 coarseSign = 1; + u32 data64Hi = 0; + u32 data64Lo = 0; + u32 tempFreqOffset = 0; pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); struct i2c_device_addr *devAddr = NULL; @@ -12235,7 +12235,7 @@ rw_error: static DRXStatus_t GetOOBFrequency(pDRXDemodInstance_t demod, pDRXFrequency_t frequency) { - u16_t data = 0; + u16 data = 0; DRXFrequency_t freqOffset = 0; DRXFrequency_t freq = 0; struct i2c_device_addr *devAddr = NULL; @@ -12267,9 +12267,9 @@ rw_error: * Gets OOB MER. Table for MER is in Programming guide. * */ -static DRXStatus_t GetOOBMER(struct i2c_device_addr *devAddr, pu32_t mer) +static DRXStatus_t GetOOBMER(struct i2c_device_addr *devAddr, u32 *mer) { - u16_t data = 0; + u16 data = 0; *mer = 0; /* READ MER */ @@ -12410,7 +12410,7 @@ rw_error: */ static DRXStatus_t SetOrxNsuAox(pDRXDemodInstance_t demod, Bool_t active) { - u16_t data = 0; + u16 data = 0; struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; @@ -12478,26 +12478,26 @@ static DRXStatus_t CtrlSetOOB(pDRXDemodInstance_t demod, pDRXOOB_t oobParam) DRXFrequency_t freq = 0; /* KHz */ struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; - u16_t i = 0; + u16 i = 0; Bool_t mirrorFreqSpectOOB = FALSE; - u16_t trkFilterValue = 0; + u16 trkFilterValue = 0; DRXJSCUCmd_t scuCmd; - u16_t setParamParameters[3]; - u16_t cmdResult[2] = { 0, 0 }; - s16_t NyquistCoeffs[4][(NYQFILTERLEN + 1) / 2] = { + u16 setParamParameters[3]; + u16 cmdResult[2] = { 0, 0 }; + s16 NyquistCoeffs[4][(NYQFILTERLEN + 1) / 2] = { IMPULSE_COSINE_ALPHA_0_3, /* Target Mode 0 */ IMPULSE_COSINE_ALPHA_0_3, /* Target Mode 1 */ IMPULSE_COSINE_ALPHA_0_5, /* Target Mode 2 */ IMPULSE_COSINE_ALPHA_RO_0_5 /* Target Mode 3 */ }; - u8_t mode_val[4] = { 2, 2, 0, 1 }; - u8_t PFICoeffs[4][6] = { + u8 mode_val[4] = { 2, 2, 0, 1 }; + u8 PFICoeffs[4][6] = { {DRXJ_16TO8(-92), DRXJ_16TO8(-108), DRXJ_16TO8(100)}, /* TARGET_MODE = 0: PFI_A = -23/32; PFI_B = -54/32; PFI_C = 25/32; fg = 0.5 MHz (Att=26dB) */ {DRXJ_16TO8(-64), DRXJ_16TO8(-80), DRXJ_16TO8(80)}, /* TARGET_MODE = 1: PFI_A = -16/32; PFI_B = -40/32; PFI_C = 20/32; fg = 1.0 MHz (Att=28dB) */ {DRXJ_16TO8(-80), DRXJ_16TO8(-98), DRXJ_16TO8(92)}, /* TARGET_MODE = 2, 3: PFI_A = -20/32; PFI_B = -49/32; PFI_C = 23/32; fg = 0.8 MHz (Att=25dB) */ {DRXJ_16TO8(-80), DRXJ_16TO8(-98), DRXJ_16TO8(92)} /* TARGET_MODE = 2, 3: PFI_A = -20/32; PFI_B = -49/32; PFI_C = 23/32; fg = 0.8 MHz (Att=25dB) */ }; - u16_t mode_index; + u16 mode_index; devAddr = demod->myI2CDevAddr; extAttr = (pDRXJData_t) demod->myExtAttr; @@ -12527,12 +12527,12 @@ static DRXStatus_t CtrlSetOOB(pDRXDemodInstance_t demod, pDRXOOB_t oobParam) freq = (freq - 50000) / 50; { - u16_t index = 0; - u16_t remainder = 0; - pu16_t trkFiltercfg = extAttr->oobTrkFilterCfg; + u16 index = 0; + u16 remainder = 0; + u16 *trkFiltercfg = extAttr->oobTrkFilterCfg; - index = (u16_t) ((freq - 400) / 200); - remainder = (u16_t) ((freq - 400) % 200); + index = (u16) ((freq - 400) / 200); + remainder = (u16) ((freq - 400) % 200); trkFilterValue = trkFiltercfg[index] - (trkFiltercfg[index] - trkFiltercfg[index + @@ -12624,7 +12624,7 @@ static DRXStatus_t CtrlSetOOB(pDRXDemodInstance_t demod, pDRXOOB_t oobParam) SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_REGSPEC; break; } - setParamParameters[1] = (u16_t) (freq & 0xFFFF); + setParamParameters[1] = (u16) (freq & 0xFFFF); setParamParameters[2] = trkFilterValue; scuCmd.parameter = setParamParameters; scuCmd.resultLen = 1; @@ -12665,49 +12665,49 @@ static DRXStatus_t CtrlSetOOB(pDRXDemodInstance_t demod, pDRXOOB_t oobParam) /* AGN_LOCK = {2048>>3, -2048, 8, -8, 0, 1}; */ WR16(devAddr, SCU_RAM_ORX_AGN_LOCK_TH__A, 2048 >> 3); - WR16(devAddr, SCU_RAM_ORX_AGN_LOCK_TOTH__A, (u16_t) (-2048)); + WR16(devAddr, SCU_RAM_ORX_AGN_LOCK_TOTH__A, (u16) (-2048)); WR16(devAddr, SCU_RAM_ORX_AGN_ONLOCK_TTH__A, 8); - WR16(devAddr, SCU_RAM_ORX_AGN_UNLOCK_TTH__A, (u16_t) (-8)); + WR16(devAddr, SCU_RAM_ORX_AGN_UNLOCK_TTH__A, (u16) (-8)); WR16(devAddr, SCU_RAM_ORX_AGN_LOCK_MASK__A, 1); /* DGN_LOCK = {10, -2048, 8, -8, 0, 1<<1}; */ WR16(devAddr, SCU_RAM_ORX_DGN_LOCK_TH__A, 10); - WR16(devAddr, SCU_RAM_ORX_DGN_LOCK_TOTH__A, (u16_t) (-2048)); + WR16(devAddr, SCU_RAM_ORX_DGN_LOCK_TOTH__A, (u16) (-2048)); WR16(devAddr, SCU_RAM_ORX_DGN_ONLOCK_TTH__A, 8); - WR16(devAddr, SCU_RAM_ORX_DGN_UNLOCK_TTH__A, (u16_t) (-8)); + WR16(devAddr, SCU_RAM_ORX_DGN_UNLOCK_TTH__A, (u16) (-8)); WR16(devAddr, SCU_RAM_ORX_DGN_LOCK_MASK__A, 1 << 1); /* FRQ_LOCK = {15,-2048, 8, -8, 0, 1<<2}; */ WR16(devAddr, SCU_RAM_ORX_FRQ_LOCK_TH__A, 17); - WR16(devAddr, SCU_RAM_ORX_FRQ_LOCK_TOTH__A, (u16_t) (-2048)); + WR16(devAddr, SCU_RAM_ORX_FRQ_LOCK_TOTH__A, (u16) (-2048)); WR16(devAddr, SCU_RAM_ORX_FRQ_ONLOCK_TTH__A, 8); - WR16(devAddr, SCU_RAM_ORX_FRQ_UNLOCK_TTH__A, (u16_t) (-8)); + WR16(devAddr, SCU_RAM_ORX_FRQ_UNLOCK_TTH__A, (u16) (-8)); WR16(devAddr, SCU_RAM_ORX_FRQ_LOCK_MASK__A, 1 << 2); /* PHA_LOCK = {5000, -2048, 8, -8, 0, 1<<3}; */ WR16(devAddr, SCU_RAM_ORX_PHA_LOCK_TH__A, 3000); - WR16(devAddr, SCU_RAM_ORX_PHA_LOCK_TOTH__A, (u16_t) (-2048)); + WR16(devAddr, SCU_RAM_ORX_PHA_LOCK_TOTH__A, (u16) (-2048)); WR16(devAddr, SCU_RAM_ORX_PHA_ONLOCK_TTH__A, 8); - WR16(devAddr, SCU_RAM_ORX_PHA_UNLOCK_TTH__A, (u16_t) (-8)); + WR16(devAddr, SCU_RAM_ORX_PHA_UNLOCK_TTH__A, (u16) (-8)); WR16(devAddr, SCU_RAM_ORX_PHA_LOCK_MASK__A, 1 << 3); /* TIM_LOCK = {300, -2048, 8, -8, 0, 1<<4}; */ WR16(devAddr, SCU_RAM_ORX_TIM_LOCK_TH__A, 400); - WR16(devAddr, SCU_RAM_ORX_TIM_LOCK_TOTH__A, (u16_t) (-2048)); + WR16(devAddr, SCU_RAM_ORX_TIM_LOCK_TOTH__A, (u16) (-2048)); WR16(devAddr, SCU_RAM_ORX_TIM_ONLOCK_TTH__A, 8); - WR16(devAddr, SCU_RAM_ORX_TIM_UNLOCK_TTH__A, (u16_t) (-8)); + WR16(devAddr, SCU_RAM_ORX_TIM_UNLOCK_TTH__A, (u16) (-8)); WR16(devAddr, SCU_RAM_ORX_TIM_LOCK_MASK__A, 1 << 4); /* EQU_LOCK = {20, -2048, 8, -8, 0, 1<<5}; */ WR16(devAddr, SCU_RAM_ORX_EQU_LOCK_TH__A, 20); - WR16(devAddr, SCU_RAM_ORX_EQU_LOCK_TOTH__A, (u16_t) (-2048)); + WR16(devAddr, SCU_RAM_ORX_EQU_LOCK_TOTH__A, (u16) (-2048)); WR16(devAddr, SCU_RAM_ORX_EQU_ONLOCK_TTH__A, 4); - WR16(devAddr, SCU_RAM_ORX_EQU_UNLOCK_TTH__A, (u16_t) (-4)); + WR16(devAddr, SCU_RAM_ORX_EQU_UNLOCK_TTH__A, (u16) (-4)); WR16(devAddr, SCU_RAM_ORX_EQU_LOCK_MASK__A, 1 << 5); /* PRE-Filter coefficients (PFI) */ WRB(devAddr, ORX_FWP_PFI_A_W__A, sizeof(PFICoeffs[mode_index]), - ((pu8_t) PFICoeffs[mode_index])); + ((u8 *) PFICoeffs[mode_index])); WR16(devAddr, ORX_TOP_MDE_W__A, mode_index); /* NYQUIST-Filter coefficients (NYQ) */ @@ -12752,7 +12752,7 @@ CtrlGetOOB(pDRXDemodInstance_t demod, pDRXOOBStatus_t oobStatus) #ifndef DRXJ_DIGITAL_ONLY struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; - u16_t data = 0; + u16 data = 0; devAddr = demod->myI2CDevAddr; extAttr = (pDRXJData_t) demod->myExtAttr; @@ -12791,7 +12791,7 @@ rw_error: */ #ifndef DRXJ_DIGITAL_ONLY static DRXStatus_t -CtrlSetCfgOOBPreSAW(pDRXDemodInstance_t demod, pu16_t cfgData) +CtrlSetCfgOOBPreSAW(pDRXDemodInstance_t demod, u16 *cfgData) { struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; @@ -12818,7 +12818,7 @@ rw_error: */ #ifndef DRXJ_DIGITAL_ONLY static DRXStatus_t -CtrlGetCfgOOBPreSAW(pDRXDemodInstance_t demod, pu16_t cfgData) +CtrlGetCfgOOBPreSAW(pDRXDemodInstance_t demod, u16 *cfgData) { pDRXJData_t extAttr = NULL; @@ -12919,8 +12919,8 @@ CtrlSetChannel(pDRXDemodInstance_t demod, pDRXChannel_t channel) pDRXCommonAttr_t commonAttr = NULL; Bool_t bridgeClosed = FALSE; #ifndef DRXJ_VSB_ONLY - u32_t minSymbolRate = 0; - u32_t maxSymbolRate = 0; + u32 minSymbolRate = 0; + u32 maxSymbolRate = 0; int bandwidthTemp = 0; int bandwidth = 0; #endif @@ -13295,9 +13295,9 @@ CtrlGetChannel(pDRXDemodInstance_t demod, pDRXChannel_t channel) DRXStandard_t standard = DRX_STANDARD_UNKNOWN; pDRXCommonAttr_t commonAttr = NULL; DRXFrequency_t intermediateFreq = 0; - s32_t CTLFreqOffset = 0; - u32_t iqmRcRateLo = 0; - u32_t adcFrequency = 0; + s32 CTLFreqOffset = 0; + u32 iqmRcRateLo = 0; + u32 adcFrequency = 0; #ifndef DRXJ_VSB_ONLY int bandwidthTemp = 0; int bandwidth = 0; @@ -13389,7 +13389,7 @@ CtrlGetChannel(pDRXDemodInstance_t demod, pDRXChannel_t channel) } else { /* annex A & C */ - u32_t rollOff = 113; /* default annex C */ + u32 rollOff = 113; /* default annex C */ if (standard == DRX_STANDARD_ITU_A) { rollOff = 115; @@ -13424,7 +13424,7 @@ CtrlGetChannel(pDRXDemodInstance_t demod, pDRXChannel_t channel) /* parameter */ NULL, /* result */ NULL }; - u16_t cmdResult[3] = { 0, 0, 0 }; + u16 cmdResult[3] = { 0, 0, 0 }; cmdSCU.command = SCU_RAM_COMMAND_STANDARD_QAM | @@ -13499,10 +13499,10 @@ rw_error: ===== SigQuality() ========================================================== ===========================================================================*/ -static u16_t -mer2indicator(u16_t mer, u16_t minMer, u16_t thresholdMer, u16_t maxMer) +static u16 +mer2indicator(u16 mer, u16 minMer, u16 thresholdMer, u16 maxMer) { - u16_t indicator = 0; + u16 indicator = 0; if (mer < minMer) { indicator = 0; @@ -13544,9 +13544,9 @@ CtrlSigQuality(pDRXDemodInstance_t demod, pDRXSigQuality_t sigQuality) pDRXJData_t extAttr = NULL; DRXStandard_t standard = DRX_STANDARD_UNKNOWN; DRXLockStatus_t lockStatus = DRX_NOT_LOCKED; - u16_t minMer = 0; - u16_t maxMer = 0; - u16_t thresholdMer = 0; + u16 minMer = 0; + u16 maxMer = 0; + u16 thresholdMer = 0; /* Check arguments */ if ((sigQuality == NULL) || (demod == NULL)) { @@ -13683,8 +13683,8 @@ CtrlLockStatus(pDRXDemodInstance_t demod, pDRXLockStatus_t lockStat) /* *parameter */ NULL, /* *result */ NULL }; - u16_t cmdResult[2] = { 0, 0 }; - u16_t demodLock = SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_DEMOD_LOCKED; + u16 cmdResult[2] = { 0, 0 }; + u16 demodLock = SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_DEMOD_LOCKED; /* check arguments */ if ((demod == NULL) || (lockStat == NULL)) { @@ -13939,12 +13939,12 @@ rw_error: /** * \fn DRXStatus_t CtrlGetCfgSymbolClockOffset() * \brief Get frequency offsets of STR. -* \param pointer to s32_t. +* \param pointer to s32. * \return DRXStatus_t. * */ static DRXStatus_t -CtrlGetCfgSymbolClockOffset(pDRXDemodInstance_t demod, ps32_t rateOffset) +CtrlGetCfgSymbolClockOffset(pDRXDemodInstance_t demod, s32 *rateOffset) { DRXStandard_t standard = DRX_STANDARD_UNKNOWN; struct i2c_device_addr *devAddr = NULL; @@ -13999,7 +13999,7 @@ CtrlPowerMode(pDRXDemodInstance_t demod, pDRXPowerMode_t mode) pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) NULL; pDRXJData_t extAttr = (pDRXJData_t) NULL; struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; - u16_t sioCcPwdMode = 0; + u16 sioCcPwdMode = 0; commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; extAttr = (pDRXJData_t) demod->myExtAttr; @@ -14127,17 +14127,17 @@ CtrlVersion(pDRXDemodInstance_t demod, pDRXVersionList_t * versionList) pDRXJData_t extAttr = (pDRXJData_t) (NULL); struct i2c_device_addr *devAddr = (struct i2c_device_addr *) (NULL); pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); - u16_t ucodeMajorMinor = 0; /* BCD Ma:Ma:Ma:Mi */ - u16_t ucodePatch = 0; /* BCD Pa:Pa:Pa:Pa */ - u16_t major = 0; - u16_t minor = 0; - u16_t patch = 0; - u16_t idx = 0; - u32_t jtag = 0; - u16_t subtype = 0; - u16_t mfx = 0; - u16_t bid = 0; - u16_t key = 0; + u16 ucodeMajorMinor = 0; /* BCD Ma:Ma:Ma:Mi */ + u16 ucodePatch = 0; /* BCD Pa:Pa:Pa:Pa */ + u16 major = 0; + u16 minor = 0; + u16 patch = 0; + u16 idx = 0; + u32 jtag = 0; + u16 subtype = 0; + u16 mfx = 0; + u16 bid = 0; + u16 key = 0; static char ucodeName[] = "Microcode"; static char deviceName[] = "Device"; @@ -14225,8 +14225,8 @@ CtrlVersion(pDRXDemodInstance_t demod, pDRXVersionList_t * versionList) /* DRX39xxJ type Ax */ /* TODO semantics of mfx and spin are unclear */ - subtype = (u16_t) ((jtag >> 12) & 0xFF); - mfx = (u16_t) (jtag >> 29); + subtype = (u16) ((jtag >> 12) & 0xFF); + mfx = (u16) (jtag >> 29); extAttr->vVersion[1].vMinor = 1; if (mfx == 0x03) { extAttr->vVersion[1].vPatch = mfx + 2; @@ -14284,7 +14284,7 @@ static DRXStatus_t CtrlProbeDevice(pDRXDemodInstance_t demod) || commonAttr->currentPowerMode != DRX_POWER_UP) { struct i2c_device_addr *devAddr = NULL; DRXPowerMode_t powerMode = DRX_POWER_UP; - u32_t jtag = 0; + u32 jtag = 0; devAddr = demod->myI2CDevAddr; @@ -14349,7 +14349,7 @@ rw_error: FALSE if MC block not Audio * \return Bool_t. */ -Bool_t IsMCBlockAudio(u32_t addr) +Bool_t IsMCBlockAudio(u32 addr) { if ((addr == AUD_XFP_PRAM_4K__A) || (addr == AUD_XDFP_PRAM_4K__A)) { return (TRUE); @@ -14374,10 +14374,10 @@ CtrlUCodeUpload(pDRXDemodInstance_t demod, pDRXUCodeInfo_t mcInfo, DRXUCodeAction_t action, Bool_t uploadAudioMC) { - u16_t i = 0; - u16_t mcNrOfBlks = 0; - u16_t mcMagicWord = 0; - pu8_t mcData = (pu8_t) (NULL); + u16 i = 0; + u16 mcNrOfBlks = 0; + u16 mcMagicWord = 0; + u8 *mcData = (u8 *) (NULL); struct i2c_device_addr *devAddr = (struct i2c_device_addr *) (NULL); pDRXJData_t extAttr = (pDRXJData_t) (NULL); @@ -14394,9 +14394,9 @@ CtrlUCodeUpload(pDRXDemodInstance_t demod, /* Check data */ mcMagicWord = UCodeRead16(mcData); - mcData += sizeof(u16_t); + mcData += sizeof(u16); mcNrOfBlks = UCodeRead16(mcData); - mcData += sizeof(u16_t); + mcData += sizeof(u16); if ((mcMagicWord != DRXJ_UCODE_MAGIC_WORD) || (mcNrOfBlks == 0)) { /* wrong endianess or wrong data ? */ @@ -14406,17 +14406,17 @@ CtrlUCodeUpload(pDRXDemodInstance_t demod, /* Process microcode blocks */ for (i = 0; i < mcNrOfBlks; i++) { DRXUCodeBlockHdr_t blockHdr; - u16_t mcBlockNrBytes = 0; + u16 mcBlockNrBytes = 0; /* Process block header */ blockHdr.addr = UCodeRead32(mcData); - mcData += sizeof(u32_t); + mcData += sizeof(u32); blockHdr.size = UCodeRead16(mcData); - mcData += sizeof(u16_t); + mcData += sizeof(u16); blockHdr.flags = UCodeRead16(mcData); - mcData += sizeof(u16_t); + mcData += sizeof(u16); blockHdr.CRC = UCodeRead16(mcData); - mcData += sizeof(u16_t); + mcData += sizeof(u16); /* Check block header on: - no data @@ -14432,7 +14432,7 @@ CtrlUCodeUpload(pDRXDemodInstance_t demod, return DRX_STS_INVALID_ARG; } - mcBlockNrBytes = blockHdr.size * sizeof(u16_t); + mcBlockNrBytes = blockHdr.size * sizeof(u16); /* Perform the desired action */ /* Check which part of MC need to be uploaded - Audio or not Audio */ @@ -14458,12 +14458,12 @@ CtrlUCodeUpload(pDRXDemodInstance_t demod, case UCODE_VERIFY: { int result = 0; - u8_t mcDataBuffer + u8 mcDataBuffer [DRXJ_UCODE_MAX_BUF_SIZE]; - u32_t bytesToCompare = 0; - u32_t bytesLeftToCompare = 0; + u32 bytesToCompare = 0; + u32 bytesLeftToCompare = 0; DRXaddr_t currAddr = (DRXaddr_t) 0; - pu8_t currPtr = NULL; + u8 *currPtr = NULL; bytesLeftToCompare = mcBlockNrBytes; currAddr = blockHdr.addr; @@ -14471,10 +14471,10 @@ CtrlUCodeUpload(pDRXDemodInstance_t demod, while (bytesLeftToCompare != 0) { if (bytesLeftToCompare > - ((u32_t) + ((u32) DRXJ_UCODE_MAX_BUF_SIZE)) { bytesToCompare = - ((u32_t) + ((u32) DRXJ_UCODE_MAX_BUF_SIZE); } else { bytesToCompare = @@ -14484,9 +14484,9 @@ CtrlUCodeUpload(pDRXDemodInstance_t demod, if (demod->myAccessFunct-> readBlockFunc(devAddr, currAddr, - (u16_t) + (u16) bytesToCompare, - (pu8_t) + (u8 *) mcDataBuffer, 0x0000) != DRX_STS_OK) { @@ -14508,7 +14508,7 @@ CtrlUCodeUpload(pDRXDemodInstance_t demod, currPtr = &(currPtr[bytesToCompare]); bytesLeftToCompare -= - ((u32_t) bytesToCompare); + ((u32) bytesToCompare); } /* while( bytesToCompare > DRXJ_UCODE_MAX_BUF_SIZE ) */ }; break; @@ -14551,7 +14551,7 @@ CtrlUCodeUpload(pDRXDemodInstance_t demod, */ static DRXStatus_t -CtrlSigStrength(pDRXDemodInstance_t demod, pu16_t sigStrength) +CtrlSigStrength(pDRXDemodInstance_t demod, u16 *sigStrength) { pDRXJData_t extAttr = NULL; DRXStandard_t standard = DRX_STANDARD_UNKNOWN; @@ -14611,11 +14611,11 @@ static DRXStatus_t CtrlGetCfgOOBMisc(pDRXDemodInstance_t demod, pDRXJCfgOOBMisc_t misc) { struct i2c_device_addr *devAddr = NULL; - u16_t lock = 0U; - u16_t state = 0U; - u16_t data = 0U; - u16_t digitalAGCMant = 0U; - u16_t digitalAGCExp = 0U; + u16 lock = 0U; + u16 state = 0U; + u16 data = 0U; + u16 digitalAGCMant = 0U; + u16 digitalAGCExp = 0U; /* check arguments */ if (misc == NULL) { @@ -14889,7 +14889,7 @@ CtrlGetCfgAgcRf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings) * \fn DRXStatus_t CtrlGetCfgAgcInternal() * \brief Retrieve internal AGC value. * \param demod demod instance -* \param u16_t +* \param u16 * \return DRXStatus_t. * * Check arguments @@ -14897,15 +14897,15 @@ CtrlGetCfgAgcRf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings) * */ static DRXStatus_t -CtrlGetCfgAgcInternal(pDRXDemodInstance_t demod, pu16_t agcInternal) +CtrlGetCfgAgcInternal(pDRXDemodInstance_t demod, u16 *agcInternal) { struct i2c_device_addr *devAddr = NULL; DRXLockStatus_t lockStatus = DRX_NOT_LOCKED; pDRXJData_t extAttr = NULL; - u16_t iqmCfScaleSh = 0; - u16_t iqmCfPower = 0; - u16_t iqmCfAmp = 0; - u16_t iqmCfGain = 0; + u16 iqmCfScaleSh = 0; + u16 iqmCfPower = 0; + u16 iqmCfAmp = 0; + u16 iqmCfGain = 0; /* check arguments */ if (agcInternal == NULL) { @@ -14957,7 +14957,7 @@ CtrlGetCfgAgcInternal(pDRXDemodInstance_t demod, pu16_t agcInternal) -IQM_CF_Gain_dB-18+6*(27-IQM_CF_SCALE_SH*2-10) +6*7+10*log10(1+0.115/4); */ /* PadcdB = P4dB +3 -6 +60; dBmV */ - *agcInternal = (u16_t) (Log10Times100(iqmCfPower) + *agcInternal = (u16) (Log10Times100(iqmCfPower) - 2 * Log10Times100(iqmCfAmp) - iqmCfGain - 120 * iqmCfScaleSh + 781); @@ -14972,7 +14972,7 @@ rw_error: * \fn DRXStatus_t CtrlSetCfgPreSaw() * \brief Set Pre-saw reference. * \param demod demod instance -* \param pu16_t +* \param u16 * * \return DRXStatus_t. * * Check arguments @@ -15041,7 +15041,7 @@ rw_error: * \fn DRXStatus_t CtrlSetCfgAfeGain() * \brief Set AFE Gain. * \param demod demod instance -* \param pu16_t +* \param u16 * * \return DRXStatus_t. * * Check arguments @@ -15053,7 +15053,7 @@ CtrlSetCfgAfeGain(pDRXDemodInstance_t demod, pDRXJCfgAfeGain_t afeGain) { struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; - u8_t gain = 0; + u8 gain = 0; /* check arguments */ if (afeGain == NULL) { @@ -15117,7 +15117,7 @@ rw_error: * \fn DRXStatus_t CtrlGetCfgPreSaw() * \brief Get Pre-saw reference setting. * \param demod demod instance -* \param pu16_t +* \param u16 * * \return DRXStatus_t. * * Check arguments @@ -15177,7 +15177,7 @@ CtrlGetCfgPreSaw(pDRXDemodInstance_t demod, pDRXJCfgPreSaw_t preSaw) * \fn DRXStatus_t CtrlGetCfgAfeGain() * \brief Get AFE Gain. * \param demod demod instance -* \param pu16_t +* \param u16 * * \return DRXStatus_t. * * Check arguments @@ -15222,7 +15222,7 @@ CtrlGetCfgAfeGain(pDRXDemodInstance_t demod, pDRXJCfgAfeGain_t afeGain) * \fn DRXStatus_t CtrlGetFecMeasSeqCount() * \brief Get FEC measurement sequnce number. * \param demod demod instance -* \param pu16_t +* \param u16 * * \return DRXStatus_t. * * Check arguments @@ -15230,7 +15230,7 @@ CtrlGetCfgAfeGain(pDRXDemodInstance_t demod, pDRXJCfgAfeGain_t afeGain) * */ static DRXStatus_t -CtrlGetFecMeasSeqCount(pDRXDemodInstance_t demod, pu16_t fecMeasSeqCount) +CtrlGetFecMeasSeqCount(pDRXDemodInstance_t demod, u16 *fecMeasSeqCount) { /* check arguments */ if (fecMeasSeqCount == NULL) { @@ -15250,7 +15250,7 @@ rw_error: * \fn DRXStatus_t CtrlGetAccumCrRSCwErr() * \brief Get accumulative corrected RS codeword number. * \param demod demod instance -* \param pu32_t +* \param u32 * * \return DRXStatus_t. * * Check arguments @@ -15258,7 +15258,7 @@ rw_error: * */ static DRXStatus_t -CtrlGetAccumCrRSCwErr(pDRXDemodInstance_t demod, pu32_t accumCrRsCWErr) +CtrlGetAccumCrRSCwErr(pDRXDemodInstance_t demod, u32 *accumCrRsCWErr) { if (accumCrRsCWErr == NULL) { return (DRX_STS_INVALID_ARG); @@ -15312,7 +15312,7 @@ static DRXStatus_t CtrlSetCfg(pDRXDemodInstance_t demod, pDRXCfg_t config) return CtrlSetCfgResetPktErr(demod); #ifndef DRXJ_DIGITAL_ONLY case DRXJ_CFG_OOB_PRE_SAW: - return CtrlSetCfgOOBPreSAW(demod, (pu16_t) (config->cfgData)); + return CtrlSetCfgOOBPreSAW(demod, (u16 *) (config->cfgData)); case DRXJ_CFG_OOB_LO_POW: return CtrlSetCfgOOBLoPower(demod, (pDRXJCfgOobLoPower_t) (config-> @@ -15408,7 +15408,7 @@ static DRXStatus_t CtrlGetCfg(pDRXDemodInstance_t demod, pDRXCfg_t config) case DRXJ_CFG_AGC_IF: return CtrlGetCfgAgcIf(demod, (pDRXJCfgAgc_t) config->cfgData); case DRXJ_CFG_AGC_INTERNAL: - return CtrlGetCfgAgcInternal(demod, (pu16_t) config->cfgData); + return CtrlGetCfgAgcInternal(demod, (u16 *) config->cfgData); case DRXJ_CFG_PRE_SAW: return CtrlGetCfgPreSaw(demod, (pDRXJCfgPreSaw_t) config->cfgData); @@ -15416,21 +15416,21 @@ static DRXStatus_t CtrlGetCfg(pDRXDemodInstance_t demod, pDRXCfg_t config) return CtrlGetCfgAfeGain(demod, (pDRXJCfgAfeGain_t) config->cfgData); case DRXJ_CFG_ACCUM_CR_RS_CW_ERR: - return CtrlGetAccumCrRSCwErr(demod, (pu32_t) config->cfgData); + return CtrlGetAccumCrRSCwErr(demod, (u32 *) config->cfgData); case DRXJ_CFG_FEC_MERS_SEQ_COUNT: - return CtrlGetFecMeasSeqCount(demod, (pu16_t) config->cfgData); + return CtrlGetFecMeasSeqCount(demod, (u16 *) config->cfgData); case DRXJ_CFG_VSB_MISC: return CtrlGetCfgVSBMisc(demod, (pDRXJCfgVSBMisc_t) config->cfgData); case DRXJ_CFG_SYMBOL_CLK_OFFSET: return CtrlGetCfgSymbolClockOffset(demod, - (ps32_t) config->cfgData); + (s32 *) config->cfgData); #ifndef DRXJ_DIGITAL_ONLY case DRXJ_CFG_OOB_MISC: return CtrlGetCfgOOBMisc(demod, (pDRXJCfgOOBMisc_t) config->cfgData); case DRXJ_CFG_OOB_PRE_SAW: - return CtrlGetCfgOOBPreSAW(demod, (pu16_t) (config->cfgData)); + return CtrlGetCfgOOBPreSAW(demod, (u16 *) (config->cfgData)); case DRXJ_CFG_OOB_LO_POW: return CtrlGetCfgOOBLoPower(demod, (pDRXJCfgOobLoPower_t) (config-> @@ -15526,7 +15526,7 @@ DRXStatus_t DRXJ_Open(pDRXDemodInstance_t demod) struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; pDRXCommonAttr_t commonAttr = NULL; - u32_t driverVersion = 0; + u32 driverVersion = 0; DRXUCodeInfo_t ucodeInfo; DRXCfgMPEGOutput_t cfgMPEGOutput; @@ -15718,9 +15718,9 @@ DRXStatus_t DRXJ_Open(pDRXDemodInstance_t demod) driverVersion += (VERSION_PATCH / 10) % 10; driverVersion <<= 4; driverVersion += (VERSION_PATCH % 10); - WR16(devAddr, SCU_RAM_DRIVER_VER_HI__A, (u16_t) (driverVersion >> 16)); + WR16(devAddr, SCU_RAM_DRIVER_VER_HI__A, (u16) (driverVersion >> 16)); WR16(devAddr, SCU_RAM_DRIVER_VER_LO__A, - (u16_t) (driverVersion & 0xFFFF)); + (u16) (driverVersion & 0xFFFF)); /* refresh the audio data structure with default */ extAttr->audData = DRXJDefaultAudData_g; @@ -15806,7 +15806,7 @@ DRXJ_Ctrl(pDRXDemodInstance_t demod, DRXCtrlIndex_t ctrl, void *ctrlData) /*======================================================================*/ case DRX_CTRL_SIG_STRENGTH: { - return CtrlSigStrength(demod, (pu16_t) ctrlData); + return CtrlSigStrength(demod, (u16 *) ctrlData); } break; /*======================================================================*/ diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.h b/drivers/media/dvb-frontends/drx39xyj/drxj.h index dbd27da..29b6450 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.h +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.h @@ -75,15 +75,15 @@ TYPEDEFS /*============================================================================*/ typedef struct { - u16_t command; + u16 command; /**< Command number */ - u16_t parameterLen; + u16 parameterLen; /**< Data length in byte */ - u16_t resultLen; + u16 resultLen; /**< result length in byte */ - u16_t *parameter; + u16 *parameter; /**< General purpous param */ - u16_t *result; + u16 *result; /**< General purpous param */ } DRXJSCUCmd_t, *pDRXJSCUCmd_t; @@ -154,7 +154,7 @@ TYPEDEFS */ typedef struct { DRXJCfgSmartAntIO_t io; - u16_t ctrlData; + u16 ctrlData; } DRXJCfgSmartAnt_t, *pDRXJCfgSmartAnt_t; /** @@ -162,9 +162,9 @@ TYPEDEFS * AGC status information from the DRXJ-IQM-AF. */ typedef struct { - u16_t IFAGC; - u16_t RFAGC; - u16_t DigitalAGC; + u16 IFAGC; + u16 RFAGC; + u16 DigitalAGC; } DRXJAgcStatus_t, *pDRXJAgcStatus_t; /* DRXJ_CFG_AGC_RF, DRXJ_CFG_AGC_IF */ @@ -186,12 +186,12 @@ TYPEDEFS typedef struct { DRXStandard_t standard; /* standard for which these settings apply */ DRXJAgcCtrlMode_t ctrlMode; /* off, user, auto */ - u16_t outputLevel; /* range dependent on AGC */ - u16_t minOutputLevel; /* range dependent on AGC */ - u16_t maxOutputLevel; /* range dependent on AGC */ - u16_t speed; /* range dependent on AGC */ - u16_t top; /* rf-agc take over point */ - u16_t cutOffCurrent; /* rf-agc is accelerated if output current + u16 outputLevel; /* range dependent on AGC */ + u16 minOutputLevel; /* range dependent on AGC */ + u16 maxOutputLevel; /* range dependent on AGC */ + u16 speed; /* range dependent on AGC */ + u16 top; /* rf-agc take over point */ + u16 cutOffCurrent; /* rf-agc is accelerated if output current is below cut-off current */ } DRXJCfgAgc_t, *pDRXJCfgAgc_t; @@ -203,7 +203,7 @@ TYPEDEFS */ typedef struct { DRXStandard_t standard; /* standard to which these settings apply */ - u16_t reference; /* pre SAW reference value, range 0 .. 31 */ + u16 reference; /* pre SAW reference value, range 0 .. 31 */ Bool_t usePreSaw; /* TRUE algorithms must use pre SAW sense */ } DRXJCfgPreSaw_t, *pDRXJCfgPreSaw_t; @@ -215,7 +215,7 @@ TYPEDEFS */ typedef struct { DRXStandard_t standard; /* standard to which these settings apply */ - u16_t gain; /* gain in 0.1 dB steps, DRXJ range 140 .. 335 */ + u16 gain; /* gain in 0.1 dB steps, DRXJ range 140 .. 335 */ } DRXJCfgAfeGain_t, *pDRXJCfgAfeGain_t; /** @@ -226,15 +226,15 @@ TYPEDEFS * */ typedef struct { - u16_t nrBitErrors; + u16 nrBitErrors; /**< no of pre RS bit errors */ - u16_t nrSymbolErrors; + u16 nrSymbolErrors; /**< no of pre RS symbol errors */ - u16_t nrPacketErrors; + u16 nrPacketErrors; /**< no of pre RS packet errors */ - u16_t nrFailures; + u16 nrFailures; /**< no of post RS failures to decode */ - u16_t nrSncParFailCount; + u16 nrSncParFailCount; /**< no of post RS bit erros */ } DRXJRSErrors_t, *pDRXJRSErrors_t; @@ -243,7 +243,7 @@ TYPEDEFS * symbol error rate */ typedef struct { - u32_t symbError; + u32 symbError; /**< symbol error rate sps */ } DRXJCfgVSBMisc_t, *pDRXJCfgVSBMisc_t; @@ -321,8 +321,8 @@ TYPEDEFS * DRXJ_CFG_ATV_MISC */ typedef struct { - s16_t peakFilter; /* -8 .. 15 */ - u16_t noiseFilter; /* 0 .. 15 */ + s16 peakFilter; /* -8 .. 15 */ + u16 noiseFilter; /* 0 .. 15 */ } DRXJCfgAtvMisc_t, *pDRXJCfgAtvMisc_t; /* @@ -347,7 +347,7 @@ TYPEDEFS Bool_t freqLock; Bool_t digGainLock; Bool_t anaGainLock; - u8_t state; + u8 state; } DRXJCfgOOBMisc_t, *pDRXJCfgOOBMisc_t; /* @@ -365,10 +365,10 @@ TYPEDEFS * DRXJ_CFG_ATV_EQU_COEF */ typedef struct { - s16_t coef0; /* -256 .. 255 */ - s16_t coef1; /* -256 .. 255 */ - s16_t coef2; /* -256 .. 255 */ - s16_t coef3; /* -256 .. 255 */ + s16 coef0; /* -256 .. 255 */ + s16 coef1; /* -256 .. 255 */ + s16 coef2; /* -256 .. 255 */ + s16 coef3; /* -256 .. 255 */ } DRXJCfgAtvEquCoef_t, *pDRXJCfgAtvEquCoef_t; /* @@ -417,13 +417,13 @@ TYPEDEFS */ /* TODO : AFE interface not yet finished, subject to change */ typedef struct { - u16_t rfAgcGain; /* 0 .. 877 uA */ - u16_t ifAgcGain; /* 0 .. 877 uA */ - s16_t videoAgcGain; /* -75 .. 1972 in 0.1 dB steps */ - s16_t audioAgcGain; /* -4 .. 1020 in 0.1 dB steps */ - u16_t rfAgcLoopGain; /* 0 .. 7 */ - u16_t ifAgcLoopGain; /* 0 .. 7 */ - u16_t videoAgcLoopGain; /* 0 .. 7 */ + u16 rfAgcGain; /* 0 .. 877 uA */ + u16 ifAgcGain; /* 0 .. 877 uA */ + s16 videoAgcGain; /* -75 .. 1972 in 0.1 dB steps */ + s16 audioAgcGain; /* -4 .. 1020 in 0.1 dB steps */ + u16 rfAgcLoopGain; /* 0 .. 7 */ + u16 ifAgcLoopGain; /* 0 .. 7 */ + u16 videoAgcLoopGain; /* 0 .. 7 */ } DRXJCfgAtvAgcStatus_t, *pDRXJCfgAtvAgcStatus_t; /*============================================================================*/ @@ -456,7 +456,7 @@ TYPEDEFS Bool_t hasGPIO; /**< TRUE if GPIO is available */ Bool_t hasIRQN; /**< TRUE if IRQN is available */ /* A1/A2/A... */ - u8_t mfx; /**< metal fix */ + u8 mfx; /**< metal fix */ /* tuner settings */ Bool_t mirrorFreqSpectOOB;/**< tuner inversion (TRUE = tuner mirrors the signal */ @@ -471,22 +471,22 @@ TYPEDEFS DRXMirror_t mirror; /**< current channel mirror */ /* signal quality information */ - u32_t fecBitsDesired; /**< BER accounting period */ - u16_t fecVdPlen; /**< no of trellis symbols: VD SER measurement period */ - u16_t qamVdPrescale; /**< Viterbi Measurement Prescale */ - u16_t qamVdPeriod; /**< Viterbi Measurement period */ - u16_t fecRsPlen; /**< defines RS BER measurement period */ - u16_t fecRsPrescale; /**< ReedSolomon Measurement Prescale */ - u16_t fecRsPeriod; /**< ReedSolomon Measurement period */ + u32 fecBitsDesired; /**< BER accounting period */ + u16 fecVdPlen; /**< no of trellis symbols: VD SER measurement period */ + u16 qamVdPrescale; /**< Viterbi Measurement Prescale */ + u16 qamVdPeriod; /**< Viterbi Measurement period */ + u16 fecRsPlen; /**< defines RS BER measurement period */ + u16 fecRsPrescale; /**< ReedSolomon Measurement Prescale */ + u16 fecRsPeriod; /**< ReedSolomon Measurement period */ Bool_t resetPktErrAcc; /**< Set a flag to reset accumulated packet error */ - u16_t pktErrAccStart; /**< Set a flag to reset accumulated packet error */ + u16 pktErrAccStart; /**< Set a flag to reset accumulated packet error */ /* HI configuration */ - u16_t HICfgTimingDiv; /**< HI Configure() parameter 2 */ - u16_t HICfgBridgeDelay; /**< HI Configure() parameter 3 */ - u16_t HICfgWakeUpKey; /**< HI Configure() parameter 4 */ - u16_t HICfgCtrl; /**< HI Configure() parameter 5 */ - u16_t HICfgTransmit; /**< HI Configure() parameter 6 */ + u16 HICfgTimingDiv; /**< HI Configure() parameter 2 */ + u16 HICfgBridgeDelay; /**< HI Configure() parameter 3 */ + u16 HICfgWakeUpKey; /**< HI Configure() parameter 4 */ + u16 HICfgCtrl; /**< HI Configure() parameter 5 */ + u16 HICfgTransmit; /**< HI Configure() parameter 6 */ /* UIO configuartion */ DRXUIOMode_t uioSmaRxMode;/**< current mode of SmaRx pin */ @@ -495,20 +495,20 @@ TYPEDEFS DRXUIOMode_t uioIRQNMode; /**< current mode of IRQN pin */ /* IQM fs frequecy shift and inversion */ - u32_t iqmFsRateOfs; /**< frequency shifter setting after setchannel */ + u32 iqmFsRateOfs; /**< frequency shifter setting after setchannel */ Bool_t posImage; /**< Ture: positive image */ /* IQM RC frequecy shift */ - u32_t iqmRcRateOfs; /**< frequency shifter setting after setchannel */ + u32 iqmRcRateOfs; /**< frequency shifter setting after setchannel */ /* ATV configuartion */ - u32_t atvCfgChangedFlags; /**< flag: flags cfg changes */ - s16_t atvTopEqu0[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU0__A */ - s16_t atvTopEqu1[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU1__A */ - s16_t atvTopEqu2[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU2__A */ - s16_t atvTopEqu3[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU3__A */ + u32 atvCfgChangedFlags; /**< flag: flags cfg changes */ + s16 atvTopEqu0[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU0__A */ + s16 atvTopEqu1[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU1__A */ + s16 atvTopEqu2[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU2__A */ + s16 atvTopEqu3[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU3__A */ Bool_t phaseCorrectionBypass;/**< flag: TRUE=bypass */ - s16_t atvTopVidPeak; /**< shadow of ATV_TOP_VID_PEAK__A */ - u16_t atvTopNoiseTh; /**< shadow of ATV_TOP_NOISE_TH__A */ + s16 atvTopVidPeak; /**< shadow of ATV_TOP_VID_PEAK__A */ + u16 atvTopNoiseTh; /**< shadow of ATV_TOP_NOISE_TH__A */ Bool_t enableCVBSOutput; /**< flag CVBS ouput enable */ Bool_t enableSIFOutput; /**< flag SIF ouput enable */ DRXJSIFAttenuation_t sifAttenuation; @@ -520,8 +520,8 @@ TYPEDEFS DRXJCfgAgc_t vsbIfAgcCfg; /**< vsb IF AGC config */ /* PGA gain configuration for QAM and VSB */ - u16_t qamPgaCfg; /**< qam PGA config */ - u16_t vsbPgaCfg; /**< vsb PGA config */ + u16 qamPgaCfg; /**< qam PGA config */ + u16 vsbPgaCfg; /**< vsb PGA config */ /* Pre SAW configuration for QAM and VSB */ DRXJCfgPreSaw_t qamPreSawCfg; @@ -539,11 +539,11 @@ TYPEDEFS Bool_t smartAntInverted; /* Tracking filter setting for OOB */ - u16_t oobTrkFilterCfg[8]; + u16 oobTrkFilterCfg[8]; Bool_t oobPowerOn; /* MPEG static bitrate setting */ - u32_t mpegTsStaticBitrate; /**< bitrate static MPEG output */ + u32 mpegTsStaticBitrate; /**< bitrate static MPEG output */ Bool_t disableTEIhandling; /**< MPEG TS TEI handling */ Bool_t bitReverseMpegOutout;/**< MPEG output bit order */ DRXJMpegOutputClockRate_t mpegOutputClockRate; @@ -556,19 +556,19 @@ TYPEDEFS /**< atv pre SAW config */ DRXJCfgAgc_t atvRfAgcCfg; /**< atv RF AGC config */ DRXJCfgAgc_t atvIfAgcCfg; /**< atv IF AGC config */ - u16_t atvPgaCfg; /**< atv pga config */ + u16 atvPgaCfg; /**< atv pga config */ - u32_t currSymbolRate; + u32 currSymbolRate; /* pin-safe mode */ Bool_t pdrSafeMode; /**< PDR safe mode activated */ - u16_t pdrSafeRestoreValGpio; - u16_t pdrSafeRestoreValVSync; - u16_t pdrSafeRestoreValSmaRx; - u16_t pdrSafeRestoreValSmaTx; + u16 pdrSafeRestoreValGpio; + u16 pdrSafeRestoreValVSync; + u16 pdrSafeRestoreValSmaRx; + u16 pdrSafeRestoreValSmaTx; /* OOB pre-saw value */ - u16_t oobPreSaw; + u16 oobPreSaw; DRXJCfgOobLoPower_t oobLoPow; DRXAudData_t audData; diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj_mc.h b/drivers/media/dvb-frontends/drx39xyj/drxj_mc.h index 52a3cc3..16f7a9f 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj_mc.h +++ b/drivers/media/dvb-frontends/drx39xyj/drxj_mc.h @@ -41,9 +41,9 @@ #ifndef __DRXJ_MC_MAIN_H__ #define __DRXJ_MC_MAIN_H__ -#define DRXJ_MC_MAIN ((pu8_t) drxj_mc_main_g) +#define DRXJ_MC_MAIN ((u8 *) drxj_mc_main_g) -const u8_t drxj_mc_main_g[] = { +const u8 drxj_mc_main_g[] = { 0x48, 0x4c, 0x00, 0x06, 0x00, 0x00, 0xf3, 0x10, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x01, 0x07, 0x00, 0x00, 0x1f, 0xf0, 0x00, 0x01, 0xdd, 0x81, 0x00, 0x40, 0x0a, 0x00, diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsb.h b/drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsb.h index 20f3fe6..211323591 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsb.h +++ b/drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsb.h @@ -41,9 +41,9 @@ #ifndef __DRXJ_MC_VSB_H__ #define __DRXJ_MC_VSB_H__ -#define DRXJ_MC_VSB ((pu8_t) drxj_mc_vsb_g) +#define DRXJ_MC_VSB ((u8 *) drxj_mc_vsb_g) -const u8_t drxj_mc_vsb_g[] = { +const u8 drxj_mc_vsb_g[] = { 0x48, 0x4c, 0x00, 0x03, 0x00, 0x00, 0x2b, 0x62, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00, 0x15, 0x9e, 0x00, 0x01, 0x92, 0x3b, 0x2a, 0x02, 0xe4, 0xf8, diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsbqam.h b/drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsbqam.h index 480eb7e..9996c69 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsbqam.h +++ b/drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsbqam.h @@ -42,9 +42,9 @@ #ifndef __DRXJ_MC_VSBQAM_H__ #define __DRXJ_MC_VSBQAM_H__ -#define DRXJ_MC_VSBQAM ((pu8_t) drxj_mc_vsbqam_g) +#define DRXJ_MC_VSBQAM ((u8 *) drxj_mc_vsbqam_g) -const u8_t drxj_mc_vsbqam_g[] = { +const u8 drxj_mc_vsbqam_g[] = { 0x48, 0x4c, 0x00, 0x04, 0x00, 0x00, 0x56, 0xa0, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00, 0x20, 0x00, 0x00, 0x01, 0xc4, 0x4d, 0x55, 0x02, 0xe4, 0xee, -- cgit v1.1 From 73f7065be6f31080d92ceec14c69b76b9f7b705c Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 20 Mar 2012 00:59:03 -0300 Subject: [media] drx-j: get rid of the other typedefs at bsp_types.h Most of the work were done by those small scripts: for i in *; do sed s,pDRXFrequency_t,"s32 *",g <$i >a && mv a $i; done for i in *; do sed s,DRXFrequency_t,"s32",g <$i >a && mv a $i; done for i in *; do sed s,pDRXSymbolrate_t,"u32 *",g <$i >a && mv a $i; done for i in *; do sed s,DRXSymbolrate_t,"u32",g <$i >a && mv a $i; done for i in *; do sed s,FALSE,false,g <$i >a && mv a $i; done for i in *; do sed s,TRUE,true,g <$i >a && mv a $i; done for i in *; do sed s,Bool_t,bool,g <$i >a && mv a $i; done for i in *; do sed s,pbool,"bool *",g <$i >a && mv a $i; done The only remaining things there are the return values. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h | 24 +- drivers/media/dvb-frontends/drx39xyj/bsp_types.h | 87 -- drivers/media/dvb-frontends/drx39xyj/drx39xxj.c | 14 +- .../media/dvb-frontends/drx39xyj/drx39xxj_dummy.c | 6 +- drivers/media/dvb-frontends/drx39xyj/drx_driver.c | 130 +-- drivers/media/dvb-frontends/drx39xyj/drx_driver.h | 146 +-- drivers/media/dvb-frontends/drx39xyj/drxj.c | 1002 ++++++++++---------- drivers/media/dvb-frontends/drx39xyj/drxj.h | 72 +- drivers/media/dvb-frontends/drx39xyj/drxj_map.h | 8 +- 9 files changed, 701 insertions(+), 788 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h b/drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h index 12676de..2028506 100644 --- a/drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h +++ b/drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h @@ -94,19 +94,19 @@ TYPEDEFS typedef struct { char *name; /* Tuner brand & type name */ - DRXFrequency_t minFreqRF; /* Lowest RF input frequency, in kHz */ - DRXFrequency_t maxFreqRF; /* Highest RF input frequency, in kHz */ + s32 minFreqRF; /* Lowest RF input frequency, in kHz */ + s32 maxFreqRF; /* Highest RF input frequency, in kHz */ u8 subMode; /* Index to sub-mode in use */ pTUNERSubMode_t subModeDescriptions; /* Pointer to description of sub-modes */ u8 subModes; /* Number of available sub-modes */ - /* The following fields will be either 0, NULL or FALSE and do not need + /* The following fields will be either 0, NULL or false and do not need initialisation */ void *selfCheck; /* gives proof of initialization */ - Bool_t programmed; /* only valid if selfCheck is OK */ - DRXFrequency_t RFfrequency; /* only valid if programmed */ - DRXFrequency_t IFfrequency; /* only valid if programmed */ + bool programmed; /* only valid if selfCheck is OK */ + s32 RFfrequency; /* only valid if programmed */ + s32 IFfrequency; /* only valid if programmed */ void *myUserData; /* pointer to associated demod instance */ u16 myCapabilities; /* value for storing application flags */ @@ -123,14 +123,14 @@ TYPEDEFS typedef DRXStatus_t(*TUNERSetFrequencyFunc_t) (pTUNERInstance_t tuner, TUNERMode_t mode, - DRXFrequency_t + s32 frequency); typedef DRXStatus_t(*TUNERGetFrequencyFunc_t) (pTUNERInstance_t tuner, TUNERMode_t mode, - pDRXFrequency_t + s32 * RFfrequency, - pDRXFrequency_t + s32 * IFfrequency); typedef DRXStatus_t(*TUNERLockStatusFunc_t) (pTUNERInstance_t tuner, @@ -182,12 +182,12 @@ Exported FUNCTIONS DRXStatus_t DRXBSP_TUNER_SetFrequency(pTUNERInstance_t tuner, TUNERMode_t mode, - DRXFrequency_t frequency); + s32 frequency); DRXStatus_t DRXBSP_TUNER_GetFrequency(pTUNERInstance_t tuner, TUNERMode_t mode, - pDRXFrequency_t RFfrequency, - pDRXFrequency_t IFfrequency); + s32 *RFfrequency, + s32 *IFfrequency); DRXStatus_t DRXBSP_TUNER_LockStatus(pTUNERInstance_t tuner, pTUNERLockStatus_t lockStat); diff --git a/drivers/media/dvb-frontends/drx39xyj/bsp_types.h b/drivers/media/dvb-frontends/drx39xyj/bsp_types.h index 2f5a2ba9..c65a475 100644 --- a/drivers/media/dvb-frontends/drx39xyj/bsp_types.h +++ b/drivers/media/dvb-frontends/drx39xyj/bsp_types.h @@ -28,88 +28,15 @@ POSSIBILITY OF SUCH DAMAGE. */ -/** -* \file $Id: bsp_types.h,v 1.5 2009/08/06 12:55:57 carlo Exp $ -* -* \brief General type definitions for board support packages -* -* This file contains type definitions that are needed for almost any -* board support package. -* The definitions are host and project independent. -* -*/ - #include #ifndef __BSP_TYPES_H__ #define __BSP_TYPES_H__ -/*------------------------------------------------------------------------- -INCLUDES --------------------------------------------------------------------------*/ - -#ifdef __cplusplus -extern "C" { -#endif -/*------------------------------------------------------------------------- -TYPEDEFS --------------------------------------------------------------------------*/ - -/** -* \typedef s32 DRXFrequency_t -* \brief type definition of frequency -*/ - typedef s32 DRXFrequency_t; - -/** -* \typedef DRXFrequency_t *pDRXFrequency_t -* \brief type definition of a pointer to a frequency -*/ - typedef DRXFrequency_t *pDRXFrequency_t; - -/** -* \typedef u32 DRXSymbolrate_t -* \brief type definition of symbol rate -*/ - typedef u32 DRXSymbolrate_t; - -/** -* \typedef DRXSymbolrate_t *pDRXSymbolrate_t -* \brief type definition of a pointer to a symbol rate -*/ - typedef DRXSymbolrate_t *pDRXSymbolrate_t; - -/*------------------------------------------------------------------------- -DEFINES --------------------------------------------------------------------------*/ -/** -* \def NULL -* \brief Define NULL for target. -*/ -#ifndef NULL -#define NULL (0) -#endif /*------------------------------------------------------------------------- ENUM -------------------------------------------------------------------------*/ -/* -* Boolean datatype. Only define if not already defined TRUE or FALSE. -*/ -#if defined (TRUE) || defined (FALSE) - typedef int Bool_t; -#else -/** -* \enum Bool_t -* \brief Boolean type -*/ - typedef enum { - FALSE = 0, - TRUE - } Bool_t; -#endif - typedef Bool_t *pBool_t; - /** * \enum DRXStatus_t * \brief Various return statusses @@ -125,18 +52,4 @@ ENUM /**< unavailable functionality */ } DRXStatus_t, *pDRXStatus_t; -/*------------------------------------------------------------------------- -STRUCTS --------------------------------------------------------------------------*/ - -/** -Exported FUNCTIONS --------------------------------------------------------------------------*/ - -/*------------------------------------------------------------------------- -THE END --------------------------------------------------------------------------*/ -#ifdef __cplusplus -} -#endif #endif /* __BSP_TYPES_H__ */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c index 1ccb992..bce41f4b 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c @@ -242,7 +242,7 @@ static int drx39xxj_set_frontend(struct dvb_frontend *fe) } /* Just for giggles, let's shut off the LNA again.... */ uioData.uio = DRX_UIO1; - uioData.value = FALSE; + uioData.value = false; result = DRX_Ctrl(demod, DRX_CTRL_UIO_WRITE, &uioData); if (result != DRX_STS_OK) { printk(KERN_ERR "Failed to disable LNA!\n"); @@ -271,7 +271,7 @@ static int drx39xxj_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) { struct drx39xxj_state *state = fe->demodulator_priv; DRXDemodInstance_t *demod = state->demod; - Bool_t i2c_gate_state; + bool i2c_gate_state; DRXStatus_t result; #ifdef DJH_DEBUG @@ -280,9 +280,9 @@ static int drx39xxj_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) #endif if (enable) - i2c_gate_state = TRUE; + i2c_gate_state = true; else - i2c_gate_state = FALSE; + i2c_gate_state = false; if (state->i2c_gate_open == enable) { /* We're already in the desired state */ @@ -371,9 +371,9 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) sizeof(DRXCommonAttr_t)); demod->myCommonAttr->microcode = DRXJ_MC_MAIN; #if 0 - demod->myCommonAttr->verifyMicrocode = FALSE; + demod->myCommonAttr->verifyMicrocode = false; #endif - demod->myCommonAttr->verifyMicrocode = TRUE; + demod->myCommonAttr->verifyMicrocode = true; demod->myCommonAttr->intermediateFreq = 5000; demod->myExtAttr = demodExtAttr; @@ -401,7 +401,7 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) } uioData.uio = DRX_UIO1; - uioData.value = FALSE; + uioData.value = false; result = DRX_Ctrl(demod, DRX_CTRL_UIO_WRITE, &uioData); if (result != DRX_STS_OK) { printk(KERN_ERR "Failed to disable LNA!\n"); diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c b/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c index 35cef0f..854823e 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c @@ -25,7 +25,7 @@ DRXStatus_t DRXBSP_TUNER_Close(pTUNERInstance_t tuner) DRXStatus_t DRXBSP_TUNER_SetFrequency(pTUNERInstance_t tuner, TUNERMode_t mode, - DRXFrequency_t centerFrequency) + s32 centerFrequency) { return DRX_STS_OK; } @@ -33,8 +33,8 @@ DRXStatus_t DRXBSP_TUNER_SetFrequency(pTUNERInstance_t tuner, DRXStatus_t DRXBSP_TUNER_GetFrequency(pTUNERInstance_t tuner, TUNERMode_t mode, - pDRXFrequency_t RFfrequency, - pDRXFrequency_t IFfrequency) + s32 *RFfrequency, + s32 *IFfrequency) { return DRX_STS_OK; } diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c index ea43f14..1d554f2 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c @@ -149,7 +149,7 @@ FUNCTIONS static DRXStatus_t ScanFunctionDefault(void *scanContext, DRXScanCommand_t scanCommand, - pDRXChannel_t scanChannel, pBool_t getNextChannel); + pDRXChannel_t scanChannel, bool * getNextChannel); /** * \brief Get pointer to scanning function. @@ -212,9 +212,9 @@ void *GetScanContext(pDRXDemodInstance_t demod, void *scanContext) * In case DRX_NEVER_LOCK is returned the poll-wait will be aborted. * */ -static DRXStatus_t ScanWaitForLock(pDRXDemodInstance_t demod, pBool_t isLocked) +static DRXStatus_t ScanWaitForLock(pDRXDemodInstance_t demod, bool * isLocked) { - Bool_t doneWaiting = FALSE; + bool doneWaiting = false; DRXLockStatus_t lockState = DRX_NOT_LOCKED; DRXLockStatus_t desiredLockState = DRX_NOT_LOCKED; u32 timeoutValue = 0; @@ -222,13 +222,13 @@ static DRXStatus_t ScanWaitForLock(pDRXDemodInstance_t demod, pBool_t isLocked) u32 currentTime = 0; u32 timerValue = 0; - *isLocked = FALSE; + *isLocked = false; timeoutValue = (u32) demod->myCommonAttr->scanDemodLockTimeout; desiredLockState = demod->myCommonAttr->scanDesiredLock; startTimeLockStage = DRXBSP_HST_Clock(); /* Start polling loop, checking for lock & timeout */ - while (doneWaiting == FALSE) { + while (doneWaiting == false) { if (DRX_Ctrl(demod, DRX_CTRL_LOCK_STATUS, &lockState) != DRX_STS_OK) { @@ -238,15 +238,15 @@ static DRXStatus_t ScanWaitForLock(pDRXDemodInstance_t demod, pBool_t isLocked) timerValue = currentTime - startTimeLockStage; if (lockState >= desiredLockState) { - *isLocked = TRUE; - doneWaiting = TRUE; + *isLocked = true; + doneWaiting = true; } /* if ( lockState >= desiredLockState ) .. */ else if (lockState == DRX_NEVER_LOCK) { - doneWaiting = TRUE; + doneWaiting = true; } /* if ( lockState == DRX_NEVER_LOCK ) .. */ else if (timerValue > timeoutValue) { /* lockState == DRX_NOT_LOCKED and timeout */ - doneWaiting = TRUE; + doneWaiting = true; } else { if (DRXBSP_HST_Sleep(10) != DRX_STS_OK) { return DRX_STS_ERROR; @@ -274,15 +274,15 @@ static DRXStatus_t ScanWaitForLock(pDRXDemodInstance_t demod, pBool_t isLocked) * */ static DRXStatus_t -ScanPrepareNextScan(pDRXDemodInstance_t demod, DRXFrequency_t skip) +ScanPrepareNextScan(pDRXDemodInstance_t demod, s32 skip) { pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); u16 tableIndex = 0; u16 frequencyPlanSize = 0; pDRXFrequencyPlan_t frequencyPlan = (pDRXFrequencyPlan_t) (NULL); - DRXFrequency_t nextFrequency = 0; - DRXFrequency_t tunerMinFrequency = 0; - DRXFrequency_t tunerMaxFrequency = 0; + s32 nextFrequency = 0; + s32 tunerMinFrequency = 0; + s32 tunerMaxFrequency = 0; commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; tableIndex = commonAttr->scanFreqPlanIndex; @@ -317,17 +317,17 @@ ScanPrepareNextScan(pDRXDemodInstance_t demod, DRXFrequency_t skip) commonAttr->scanParam->frequencyPlanSize; if (tableIndex >= frequencyPlanSize) { /* reached end of frequency plan */ - commonAttr->scanReady = TRUE; + commonAttr->scanReady = true; } else { nextFrequency = frequencyPlan[tableIndex].first; } } if (nextFrequency > (tunerMaxFrequency)) { /* reached end of tuner range */ - commonAttr->scanReady = TRUE; + commonAttr->scanReady = true; } } while ((nextFrequency < tunerMinFrequency) && - (commonAttr->scanReady == FALSE)); + (commonAttr->scanReady == false)); /* Store new values */ commonAttr->scanFreqPlanIndex = tableIndex; @@ -344,7 +344,7 @@ ScanPrepareNextScan(pDRXDemodInstance_t demod, DRXFrequency_t skip) * \param demod: Pointer to demodulator instance. * \param scanCommand: Scanning command: INIT, NEXT or STOP. * \param scanChannel: Channel to check: frequency and bandwidth, others AUTO -* \param getNextChannel: Return TRUE if next frequency is desired at next call +* \param getNextChannel: Return true if next frequency is desired at next call * * \return DRXStatus_t. * \retval DRX_STS_OK: Channel found, DRX_CTRL_GET_CHANNEL can be used @@ -357,11 +357,11 @@ ScanPrepareNextScan(pDRXDemodInstance_t demod, DRXFrequency_t skip) static DRXStatus_t ScanFunctionDefault(void *scanContext, DRXScanCommand_t scanCommand, - pDRXChannel_t scanChannel, pBool_t getNextChannel) + pDRXChannel_t scanChannel, bool * getNextChannel) { pDRXDemodInstance_t demod = NULL; DRXStatus_t status = DRX_STS_ERROR; - Bool_t isLocked = FALSE; + bool isLocked = false; demod = (pDRXDemodInstance_t) scanContext; @@ -370,7 +370,7 @@ ScanFunctionDefault(void *scanContext, return DRX_STS_OK; } - *getNextChannel = FALSE; + *getNextChannel = false; status = DRX_Ctrl(demod, DRX_CTRL_SET_CHANNEL, scanChannel); if (status != DRX_STS_OK) { @@ -383,9 +383,9 @@ ScanFunctionDefault(void *scanContext, } /* done with this channel, move to next one */ - *getNextChannel = TRUE; + *getNextChannel = true; - if (isLocked == FALSE) { + if (isLocked == false) { /* no channel found */ return DRX_STS_BUSY; } @@ -417,14 +417,14 @@ CtrlScanInit(pDRXDemodInstance_t demod, pDRXScanParam_t scanParam) { DRXStatus_t status = DRX_STS_ERROR; pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); - DRXFrequency_t maxTunerFreq = 0; - DRXFrequency_t minTunerFreq = 0; + s32 maxTunerFreq = 0; + s32 minTunerFreq = 0; u16 nrChannelsInPlan = 0; u16 i = 0; void *scanContext = NULL; commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; - commonAttr->scanActive = TRUE; + commonAttr->scanActive = true; /* invalidate a previous SCAN_INIT */ commonAttr->scanParam = (pDRXScanParam_t) (NULL); @@ -438,7 +438,7 @@ CtrlScanInit(pDRXDemodInstance_t demod, pDRXScanParam_t scanParam) (scanParam->frequencyPlan == NULL) || (scanParam->frequencyPlanSize == 0) ) { - commonAttr->scanActive = FALSE; + commonAttr->scanActive = false; return DRX_STS_INVALID_ARG; } @@ -446,22 +446,22 @@ CtrlScanInit(pDRXDemodInstance_t demod, pDRXScanParam_t scanParam) maxTunerFreq = commonAttr->tunerMaxFreqRF; minTunerFreq = commonAttr->tunerMinFreqRF; for (i = 0; i < (scanParam->frequencyPlanSize); i++) { - DRXFrequency_t width = 0; - DRXFrequency_t step = scanParam->frequencyPlan[i].step; - DRXFrequency_t firstFreq = scanParam->frequencyPlan[i].first; - DRXFrequency_t lastFreq = scanParam->frequencyPlan[i].last; - DRXFrequency_t minFreq = 0; - DRXFrequency_t maxFreq = 0; + s32 width = 0; + s32 step = scanParam->frequencyPlan[i].step; + s32 firstFreq = scanParam->frequencyPlan[i].first; + s32 lastFreq = scanParam->frequencyPlan[i].last; + s32 minFreq = 0; + s32 maxFreq = 0; if (step <= 0) { /* Step must be positive and non-zero */ - commonAttr->scanActive = FALSE; + commonAttr->scanActive = false; return DRX_STS_INVALID_ARG; } if (firstFreq > lastFreq) { /* First center frequency is higher than last center frequency */ - commonAttr->scanActive = FALSE; + commonAttr->scanActive = false; return DRX_STS_INVALID_ARG; } @@ -470,7 +470,7 @@ CtrlScanInit(pDRXDemodInstance_t demod, pDRXScanParam_t scanParam) if ((width % step) != 0) { /* Difference between last and first center frequency is not an integer number of steps */ - commonAttr->scanActive = FALSE; + commonAttr->scanActive = false; return DRX_STS_INVALID_ARG; } @@ -480,7 +480,7 @@ CtrlScanInit(pDRXDemodInstance_t demod, pDRXScanParam_t scanParam) if (firstFreq >= minTunerFreq) { minFreq = firstFreq; } else { - DRXFrequency_t n = 0; + s32 n = 0; n = (minTunerFreq - firstFreq) / step; if (((minTunerFreq - @@ -493,7 +493,7 @@ CtrlScanInit(pDRXDemodInstance_t demod, pDRXScanParam_t scanParam) if (lastFreq <= maxTunerFreq) { maxFreq = lastFreq; } else { - DRXFrequency_t n = 0; + s32 n = 0; n = (lastFreq - maxTunerFreq) / step; if (((lastFreq - @@ -522,12 +522,12 @@ CtrlScanInit(pDRXDemodInstance_t demod, pDRXScanParam_t scanParam) if (nrChannelsInPlan == 0) { /* Tuner range and frequency plan ranges do not overlap */ - commonAttr->scanActive = FALSE; + commonAttr->scanActive = false; return DRX_STS_ERROR; } /* Store parameters */ - commonAttr->scanReady = FALSE; + commonAttr->scanReady = false; commonAttr->scanMaxChannels = nrChannelsInPlan; commonAttr->scanChannelsScanned = 0; commonAttr->scanParam = scanParam; /* SCAN_NEXT is now allowed */ @@ -537,7 +537,7 @@ CtrlScanInit(pDRXDemodInstance_t demod, pDRXScanParam_t scanParam) status = (*(GetScanFunction(demod))) (scanContext, DRX_SCAN_COMMAND_INIT, NULL, NULL); - commonAttr->scanActive = FALSE; + commonAttr->scanActive = false; return DRX_STS_OK; } @@ -559,12 +559,12 @@ static DRXStatus_t CtrlScanStop(pDRXDemodInstance_t demod) void *scanContext = NULL; commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; - commonAttr->scanActive = TRUE; + commonAttr->scanActive = true; if ((commonAttr->scanParam == NULL) || (commonAttr->scanMaxChannels == 0)) { /* Scan was not running, just return OK */ - commonAttr->scanActive = FALSE; + commonAttr->scanActive = false; return DRX_STS_OK; } @@ -577,7 +577,7 @@ static DRXStatus_t CtrlScanStop(pDRXDemodInstance_t demod) /* All done, invalidate scan-init */ commonAttr->scanParam = NULL; commonAttr->scanMaxChannels = 0; - commonAttr->scanActive = FALSE; + commonAttr->scanActive = false; return status; } @@ -605,7 +605,7 @@ static DRXStatus_t CtrlScanStop(pDRXDemodInstance_t demod) static DRXStatus_t CtrlScanNext(pDRXDemodInstance_t demod, u16 *scanProgress) { pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); - pBool_t scanReady = (pBool_t) (NULL); + bool * scanReady = (bool *) (NULL); u16 maxProgress = DRX_SCAN_MAX_PROGRESS; u32 numTries = 0; u32 i = 0; @@ -614,16 +614,16 @@ static DRXStatus_t CtrlScanNext(pDRXDemodInstance_t demod, u16 *scanProgress) /* Check scan parameters */ if (scanProgress == NULL) { - commonAttr->scanActive = FALSE; + commonAttr->scanActive = false; return DRX_STS_INVALID_ARG; } *scanProgress = 0; - commonAttr->scanActive = TRUE; + commonAttr->scanActive = true; if ((commonAttr->scanParam == NULL) || (commonAttr->scanMaxChannels == 0)) { /* CtrlScanInit() was not called succesfully before CtrlScanNext() */ - commonAttr->scanActive = FALSE; + commonAttr->scanActive = false; return DRX_STS_ERROR; } @@ -635,11 +635,11 @@ static DRXStatus_t CtrlScanNext(pDRXDemodInstance_t demod, u16 *scanProgress) numTries = commonAttr->scanParam->numTries; scanReady = &(commonAttr->scanReady); - for (i = 0; ((i < numTries) && ((*scanReady) == FALSE)); i++) { + for (i = 0; ((i < numTries) && ((*scanReady) == false)); i++) { DRXChannel_t scanChannel = { 0 }; DRXStatus_t status = DRX_STS_ERROR; pDRXFrequencyPlan_t freqPlan = (pDRXFrequencyPlan_t) (NULL); - Bool_t nextChannel = FALSE; + bool nextChannel = false; void *scanContext = NULL; /* Next channel to scan */ @@ -671,9 +671,9 @@ static DRXStatus_t CtrlScanNext(pDRXDemodInstance_t demod, u16 *scanProgress) &nextChannel); /* Proceed to next channel if requested */ - if (nextChannel == TRUE) { + if (nextChannel == true) { DRXStatus_t nextStatus = DRX_STS_ERROR; - DRXFrequency_t skip = 0; + s32 skip = 0; if (status == DRX_STS_OK) { /* a channel was found, so skip some frequency steps */ @@ -688,25 +688,25 @@ static DRXStatus_t CtrlScanNext(pDRXDemodInstance_t demod, u16 *scanProgress) (commonAttr->scanMaxChannels)); if (nextStatus != DRX_STS_OK) { - commonAttr->scanActive = FALSE; + commonAttr->scanActive = false; return (nextStatus); } } if (status != DRX_STS_BUSY) { /* channel found or error */ - commonAttr->scanActive = FALSE; + commonAttr->scanActive = false; return status; } } /* for ( i = 0; i < ( ... numTries); i++) */ - if ((*scanReady) == TRUE) { + if ((*scanReady) == true) { /* End of scan reached: call stop-scan, ignore any error */ CtrlScanStop(demod); - commonAttr->scanActive = FALSE; + commonAttr->scanActive = false; return (DRX_STS_READY); } - commonAttr->scanActive = FALSE; + commonAttr->scanActive = false; return DRX_STS_BUSY; } @@ -735,8 +735,8 @@ CtrlProgramTuner(pDRXDemodInstance_t demod, pDRXChannel_t channel) DRXStandard_t standard = DRX_STANDARD_UNKNOWN; TUNERMode_t tunerMode = 0; DRXStatus_t status = DRX_STS_ERROR; - DRXFrequency_t ifFrequency = 0; - Bool_t tunerSlowMode = FALSE; + s32 ifFrequency = 0; + bool tunerSlowMode = false; /* can't tune without a tuner */ if (demod->myTuner == NULL) { @@ -782,7 +782,7 @@ CtrlProgramTuner(pDRXDemodInstance_t demod, pDRXChannel_t channel) } if (commonAttr->tunerPortNr == 1) { - Bool_t bridgeClosed = TRUE; + bool bridgeClosed = true; DRXStatus_t statusBridge = DRX_STS_ERROR; statusBridge = @@ -797,7 +797,7 @@ CtrlProgramTuner(pDRXDemodInstance_t demod, pDRXChannel_t channel) /* attempt restoring bridge before checking status of SetFrequency */ if (commonAttr->tunerPortNr == 1) { - Bool_t bridgeClosed = FALSE; + bool bridgeClosed = false; DRXStatus_t statusBridge = DRX_STS_ERROR; statusBridge = @@ -1315,14 +1315,14 @@ DRXStatus_t DRX_Open(pDRXDemodInstance_t demod) (demod->myCommonAttr == NULL) || (demod->myExtAttr == NULL) || (demod->myI2CDevAddr == NULL) || - (demod->myCommonAttr->isOpened == TRUE)) { + (demod->myCommonAttr->isOpened == true)) { return (DRX_STS_INVALID_ARG); } status = (*(demod->myDemodFunct->openFunc)) (demod); if (status == DRX_STS_OK) { - demod->myCommonAttr->isOpened = TRUE; + demod->myCommonAttr->isOpened = true; } return status; @@ -1352,13 +1352,13 @@ DRXStatus_t DRX_Close(pDRXDemodInstance_t demod) (demod->myCommonAttr == NULL) || (demod->myExtAttr == NULL) || (demod->myI2CDevAddr == NULL) || - (demod->myCommonAttr->isOpened == FALSE)) { + (demod->myCommonAttr->isOpened == false)) { return DRX_STS_INVALID_ARG; } status = (*(demod->myDemodFunct->closeFunc)) (demod); - DRX_SET_ISOPENED(demod, FALSE); + DRX_SET_ISOPENED(demod, false); return status; } @@ -1396,7 +1396,7 @@ DRX_Ctrl(pDRXDemodInstance_t demod, DRXCtrlIndex_t ctrl, void *ctrlData) return (DRX_STS_INVALID_ARG); } - if (((demod->myCommonAttr->isOpened == FALSE) && + if (((demod->myCommonAttr->isOpened == false) && (ctrl != DRX_CTRL_PROBE_DEVICE) && (ctrl != DRX_CTRL_VERSION)) ) { return (DRX_STS_INVALID_ARG); diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h index 8f0f2ed..12e7770 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h @@ -274,17 +274,17 @@ MACROS * \brief Macro to sign extend signed 9 bit value to signed 16 bit value */ #define DRX_S24TODRXFREQ(x) ( ( ( (u32) x ) & 0x00800000UL ) ? \ - ( (DRXFrequency_t) \ + ( (s32) \ ( ( (u32) x ) | 0xFF000000 ) ) : \ - ( (DRXFrequency_t) x ) ) + ( (s32) x ) ) /** -* \brief Macro to convert 16 bit register value to a DRXFrequency_t +* \brief Macro to convert 16 bit register value to a s32 */ #define DRX_U16TODRXFREQ(x) ( ( x & 0x8000 ) ? \ - ( (DRXFrequency_t) \ + ( (s32) \ ( ( (u32) x ) | 0xFFFF0000 ) ) : \ - ( (DRXFrequency_t) x ) ) + ( (s32) x ) ) /*------------------------------------------------------------------------- ENUM @@ -883,7 +883,7 @@ STRUCTS * */ typedef struct { - DRXFrequency_t frequency; + s32 frequency; /**< frequency in kHz */ DRXBandwidth_t bandwidth; /**< bandwidth */ @@ -898,7 +898,7 @@ STRUCTS DRXFftmode_t fftmode; /**< fftmode */ DRXClassification_t classification; /**< classification */ - DRXSymbolrate_t symbolrate; + u32 symbolrate; /**< symbolrate in symbols/sec */ DRXInterleaveModes_t interleavemode; /**< interleaveMode QAM */ @@ -967,11 +967,11 @@ STRUCTS * Used by DRX_CTRL_SCAN_INIT. */ typedef struct { - DRXFrequency_t first; + s32 first; /**< First centre frequency in this band */ - DRXFrequency_t last; + s32 last; /**< Last centre frequency in this band */ - DRXFrequency_t step; + s32 step; /**< Stepping frequency in this band */ DRXBandwidth_t bandwidth; /**< Bandwidth within this frequency band */ @@ -1037,7 +1037,7 @@ STRUCTS /**< Frequency plan (array)*/ u16 frequencyPlanSize; /**< Number of bands */ u32 numTries; /**< Max channels tried */ - DRXFrequency_t skip; /**< Minimum frequency step to take + s32 skip; /**< Minimum frequency step to take after a channel is found */ void *extParams; /**< Standard specific params */ } DRXScanParam_t, *pDRXScanParam_t; @@ -1062,7 +1062,7 @@ STRUCTS typedef DRXStatus_t(*DRXScanFunc_t) (void *scanContext, DRXScanCommand_t scanCommand, pDRXChannel_t scanChannel, - pBool_t getNextChannel); + bool * getNextChannel); /*========================================*/ @@ -1208,8 +1208,8 @@ STRUCTS typedef struct { DRXUIO_t uio; /**< UIO identifier */ - Bool_t value; - /**< UIO value (TRUE=1, FALSE=0) */ + bool value; + /**< UIO value (true=1, false=0) */ } DRXUIOData_t, *pDRXUIOData_t; /*========================================*/ @@ -1220,10 +1220,10 @@ STRUCTS * Used by DRX_CTRL_SET_OOB. */ typedef struct { - DRXFrequency_t frequency; /**< Frequency in kHz */ + s32 frequency; /**< Frequency in kHz */ DRXOOBDownstreamStandard_t standard; /**< OOB standard */ - Bool_t spectrumInverted; /**< If TRUE, then spectrum + bool spectrumInverted; /**< If true, then spectrum is inverted */ } DRXOOB_t, *pDRXOOB_t; @@ -1235,7 +1235,7 @@ STRUCTS * Used by DRX_CTRL_GET_OOB. */ typedef struct { - DRXFrequency_t frequency; /**< Frequency in Khz */ + s32 frequency; /**< Frequency in Khz */ DRXLockStatus_t lock; /**< Lock status */ u32 mer; /**< MER */ s32 symbolRateOffset; /**< Symbolrate offset in ppm */ @@ -1278,16 +1278,16 @@ STRUCTS */ typedef struct { - Bool_t enableMPEGOutput;/**< If TRUE, enable MPEG output */ - Bool_t insertRSByte; /**< If TRUE, insert RS byte */ - Bool_t enableParallel; /**< If TRUE, parallel out otherwise + bool enableMPEGOutput;/**< If true, enable MPEG output */ + bool insertRSByte; /**< If true, insert RS byte */ + bool enableParallel; /**< If true, parallel out otherwise serial */ - Bool_t invertDATA; /**< If TRUE, invert DATA signals */ - Bool_t invertERR; /**< If TRUE, invert ERR signal */ - Bool_t invertSTR; /**< If TRUE, invert STR signals */ - Bool_t invertVAL; /**< If TRUE, invert VAL signals */ - Bool_t invertCLK; /**< If TRUE, invert CLK signals */ - Bool_t staticCLK; /**< If TRUE, static MPEG clockrate + bool invertDATA; /**< If true, invert DATA signals */ + bool invertERR; /**< If true, invert ERR signal */ + bool invertSTR; /**< If true, invert STR signals */ + bool invertVAL; /**< If true, invert VAL signals */ + bool invertCLK; /**< If true, invert CLK signals */ + bool staticCLK; /**< If true, static MPEG clockrate will be used, otherwise clockrate will adapt to the bitrate of the TS */ @@ -1314,7 +1314,7 @@ STRUCTS typedef struct { DRXCfgSMAIO_t io; u16 ctrlData; - Bool_t smartAntInverted; + bool smartAntInverted; } DRXCfgSMA_t, *pDRXCfgSMA_t; /*========================================*/ @@ -1391,11 +1391,11 @@ STRUCTS * \brief Audio status characteristics. */ typedef struct { - Bool_t stereo; /**< stereo detection */ - Bool_t carrierA; /**< carrier A detected */ - Bool_t carrierB; /**< carrier B detected */ - Bool_t sap; /**< sap / bilingual detection */ - Bool_t rds; /**< RDS data array present */ + bool stereo; /**< stereo detection */ + bool carrierA; /**< carrier A detected */ + bool carrierB; /**< carrier B detected */ + bool sap; /**< sap / bilingual detection */ + bool rds; /**< RDS data array present */ DRXAudNICAMStatus_t nicamStatus; /**< status of NICAM carrier */ s8 fmIdent; /**< FM Identification value */ @@ -1408,7 +1408,7 @@ STRUCTS * \brief Raw RDS data array. */ typedef struct { - Bool_t valid; /**< RDS data validation */ + bool valid; /**< RDS data validation */ u16 data[18]; /**< data from one RDS data array */ } DRXCfgAudRDS_t, *pDRXCfgAudRDS_t; @@ -1451,7 +1451,7 @@ STRUCTS * \brief Audio volume configuration. */ typedef struct { - Bool_t mute; /**< mute overrides volume setting */ + bool mute; /**< mute overrides volume setting */ s16 volume; /**< volume, range -114 to 12 dB */ DRXAudAVCMode_t avcMode; /**< AVC auto volume control mode */ u16 avcRefLevel; /**< AVC reference level */ @@ -1507,7 +1507,7 @@ STRUCTS * \brief I2S output configuration. */ typedef struct { - Bool_t outputEnable; /**< I2S output enable */ + bool outputEnable; /**< I2S output enable */ u32 frequency; /**< range from 8000-48000 Hz */ DRXI2SMode_t mode; /**< I2S mode, master or slave */ DRXI2SWordLength_t wordLength; @@ -1575,8 +1575,8 @@ STRUCTS typedef struct { u16 thres; /* carrier detetcion threshold for primary carrier (A) */ DRXNoCarrierOption_t opt; /* Mute or noise at no carrier detection (A) */ - DRXFrequency_t shift; /* DC level of incoming signal (A) */ - DRXFrequency_t dco; /* frequency adjustment (A) */ + s32 shift; /* DC level of incoming signal (A) */ + s32 dco; /* frequency adjustment (A) */ } DRXAudCarrier_t, *pDRXCfgAudCarrier_t; /** @@ -1668,7 +1668,7 @@ STRUCTS typedef struct { s16 volume; /* dB */ u16 frequency; /* Hz */ - Bool_t mute; + bool mute; } DRXAudBeep_t, *pDRXAudBeep_t; /** @@ -1686,7 +1686,7 @@ STRUCTS */ typedef struct { /* audio storage */ - Bool_t audioIsActive; + bool audioIsActive; DRXAudStandard_t audioStandard; DRXCfgI2SOutput_t i2sdata; DRXCfgAudVolume_t volume; @@ -1701,7 +1701,7 @@ STRUCTS DRXAudBtscDetect_t btscDetect; /* rds */ u16 rdsDataCounter; - Bool_t rdsDataPresent; + bool rdsDataPresent; } DRXAudData_t, *pDRXAudData_t; /** @@ -1838,37 +1838,37 @@ STRUCTS u8 *microcode; /**< Pointer to microcode image. */ u16 microcodeSize; /**< Size of microcode image in bytes. */ - Bool_t verifyMicrocode; + bool verifyMicrocode; /**< Use microcode verify or not. */ DRXMcVersionRec_t mcversion; /**< Version record of microcode from file */ /* Clocks and tuner attributes */ - DRXFrequency_t intermediateFreq; + s32 intermediateFreq; /**< IF,if tuner instance not used. (kHz)*/ - DRXFrequency_t sysClockFreq; + s32 sysClockFreq; /**< Systemclock frequency. (kHz) */ - DRXFrequency_t oscClockFreq; + s32 oscClockFreq; /**< Oscillator clock frequency. (kHz) */ s16 oscClockDeviation; /**< Oscillator clock deviation. (ppm) */ - Bool_t mirrorFreqSpect; + bool mirrorFreqSpect; /**< Mirror IF frequency spectrum or not.*/ /* Initial MPEG output attributes */ DRXCfgMPEGOutput_t mpegCfg; /**< MPEG configuration */ - Bool_t isOpened; /**< if TRUE instance is already opened. */ + bool isOpened; /**< if true instance is already opened. */ /* Channel scan */ pDRXScanParam_t scanParam; /**< scan parameters */ u16 scanFreqPlanIndex; /**< next index in freq plan */ - DRXFrequency_t scanNextFrequency; + s32 scanNextFrequency; /**< next freq to scan */ - Bool_t scanReady; /**< scan ready flag */ + bool scanReady; /**< scan ready flag */ u32 scanMaxChannels;/**< number of channels in freqplan */ u32 scanChannelsScanned; /**< number of channels scanned */ @@ -1884,7 +1884,7 @@ STRUCTS /**< lock requirement for channel found */ /* scanActive can be used by SetChannel to decide how to program the tuner, fast or slow (but stable). Usually fast during scan. */ - Bool_t scanActive; /**< TRUE when scan routines are active */ + bool scanActive; /**< true when scan routines are active */ /* Power management */ DRXPowerMode_t currentPowerMode; @@ -1892,13 +1892,13 @@ STRUCTS /* Tuner */ u8 tunerPortNr; /**< nr of I2C port to wich tuner is */ - DRXFrequency_t tunerMinFreqRF; + s32 tunerMinFreqRF; /**< minimum RF input frequency, in kHz */ - DRXFrequency_t tunerMaxFreqRF; + s32 tunerMaxFreqRF; /**< maximum RF input frequency, in kHz */ - Bool_t tunerRfAgcPol; /**< if TRUE invert RF AGC polarity */ - Bool_t tunerIfAgcPol; /**< if TRUE invert IF AGC polarity */ - Bool_t tunerSlowMode; /**< if TRUE invert IF AGC polarity */ + bool tunerRfAgcPol; /**< if true invert RF AGC polarity */ + bool tunerIfAgcPol; /**< if true invert IF AGC polarity */ + bool tunerSlowMode; /**< if true invert IF AGC polarity */ DRXChannel_t currentChannel; /**< current channel parameters */ @@ -1908,7 +1908,7 @@ STRUCTS /**< previous standard selection */ DRXStandard_t diCacheStandard; /**< standard in DI cache if available */ - Bool_t useBootloader; /**< use bootloader in open */ + bool useBootloader; /**< use bootloader in open */ u32 capabilities; /**< capabilities flags */ u32 productId; /**< product ID inc. metal fix number */ @@ -2204,23 +2204,23 @@ Conversion from enum values to human readable form. ( x == DRX_AUD_STANDARD_UNKNOWN ) ? "Unknown" : \ "(Invalid)" ) #define DRX_STR_AUD_STEREO(x) ( \ - ( x == TRUE ) ? "Stereo" : \ - ( x == FALSE ) ? "Mono" : \ + ( x == true ) ? "Stereo" : \ + ( x == false ) ? "Mono" : \ "(Invalid)" ) #define DRX_STR_AUD_SAP(x) ( \ - ( x == TRUE ) ? "Present" : \ - ( x == FALSE ) ? "Not present" : \ + ( x == true ) ? "Present" : \ + ( x == false ) ? "Not present" : \ "(Invalid)" ) #define DRX_STR_AUD_CARRIER(x) ( \ - ( x == TRUE ) ? "Present" : \ - ( x == FALSE ) ? "Not present" : \ + ( x == true ) ? "Present" : \ + ( x == false ) ? "Not present" : \ "(Invalid)" ) #define DRX_STR_AUD_RDS(x) ( \ - ( x == TRUE ) ? "Available" : \ - ( x == FALSE ) ? "Not Available" : \ + ( x == true ) ? "Available" : \ + ( x == false ) ? "Not Available" : \ "(Invalid)" ) #define DRX_STR_AUD_NICAM_STATUS(x) ( \ @@ -2230,8 +2230,8 @@ Conversion from enum values to human readable form. "(Invalid)" ) #define DRX_STR_RDS_VALID(x) ( \ - ( x == TRUE ) ? "Valid" : \ - ( x == FALSE ) ? "Not Valid" : \ + ( x == true ) ? "Valid" : \ + ( x == false ) ? "Not Valid" : \ "(Invalid)" ) /*------------------------------------------------------------------------- @@ -2663,8 +2663,8 @@ Access macros /** * \brief Macro to check if std is an ATV standard -* \retval TRUE std is an ATV standard -* \retval FALSE std is an ATV standard +* \retval true std is an ATV standard +* \retval false std is an ATV standard */ #define DRX_ISATVSTD( std ) ( ( (std) == DRX_STANDARD_PAL_SECAM_BG ) || \ ( (std) == DRX_STANDARD_PAL_SECAM_DK ) || \ @@ -2676,8 +2676,8 @@ Access macros /** * \brief Macro to check if std is an QAM standard -* \retval TRUE std is an QAM standards -* \retval FALSE std is an QAM standards +* \retval true std is an QAM standards +* \retval false std is an QAM standards */ #define DRX_ISQAMSTD( std ) ( ( (std) == DRX_STANDARD_ITU_A ) || \ ( (std) == DRX_STANDARD_ITU_B ) || \ @@ -2686,15 +2686,15 @@ Access macros /** * \brief Macro to check if std is VSB standard -* \retval TRUE std is VSB standard -* \retval FALSE std is not VSB standard +* \retval true std is VSB standard +* \retval false std is not VSB standard */ #define DRX_ISVSBSTD( std ) ( (std) == DRX_STANDARD_8VSB ) /** * \brief Macro to check if std is DVBT standard -* \retval TRUE std is DVBT standard -* \retval FALSE std is not DVBT standard +* \retval true std is DVBT standard +* \retval false std is not DVBT standard */ #define DRX_ISDVBTSTD( std ) ( (std) == DRX_STANDARD_DVBT ) diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index b79154f..384b869 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -689,18 +689,18 @@ DRXDemodFunc_t DRXJFunctions_g = { }; DRXJData_t DRXJData_g = { - FALSE, /* hasLNA : TRUE if LNA (aka PGA) present */ - FALSE, /* hasOOB : TRUE if OOB supported */ - FALSE, /* hasNTSC: TRUE if NTSC supported */ - FALSE, /* hasBTSC: TRUE if BTSC supported */ - FALSE, /* hasSMATX: TRUE if SMA_TX pin is available */ - FALSE, /* hasSMARX: TRUE if SMA_RX pin is available */ - FALSE, /* hasGPIO : TRUE if GPIO pin is available */ - FALSE, /* hasIRQN : TRUE if IRQN pin is available */ + false, /* hasLNA : true if LNA (aka PGA) present */ + false, /* hasOOB : true if OOB supported */ + false, /* hasNTSC: true if NTSC supported */ + false, /* hasBTSC: true if BTSC supported */ + false, /* hasSMATX: true if SMA_TX pin is available */ + false, /* hasSMARX: true if SMA_RX pin is available */ + false, /* hasGPIO : true if GPIO pin is available */ + false, /* hasIRQN : true if IRQN pin is available */ 0, /* mfx A1/A2/A... */ /* tuner settings */ - FALSE, /* tuner mirrors RF signal */ + false, /* tuner mirrors RF signal */ /* standard/channel settings */ DRX_STANDARD_UNKNOWN, /* current standard */ DRX_CONSTELLATION_AUTO, /* constellation */ @@ -718,7 +718,7 @@ DRXJData_t DRXJData_g = { 204 * 8, /* fecRsPlen annex A */ 1, /* fecRsPrescale */ FEC_RS_MEASUREMENT_PERIOD, /* fecRsPeriod */ - TRUE, /* resetPktErrAcc */ + true, /* resetPktErrAcc */ 0, /* pktErrAccStart */ /* HI configuration */ @@ -734,19 +734,19 @@ DRXJData_t DRXJData_g = { DRX_UIO_MODE_DISABLE, /* uioIRQNMode */ /* FS setting */ 0UL, /* iqmFsRateOfs */ - FALSE, /* posImage */ + false, /* posImage */ /* RC setting */ 0UL, /* iqmRcRateOfs */ /* AUD information */ -/* FALSE, * flagSetAUDdone */ -/* FALSE, * detectedRDS */ -/* TRUE, * flagASDRequest */ -/* FALSE, * flagHDevClear */ -/* FALSE, * flagHDevSet */ +/* false, * flagSetAUDdone */ +/* false, * detectedRDS */ +/* true, * flagASDRequest */ +/* false, * flagHDevClear */ +/* false, * flagHDevSet */ /* (u16) 0xFFF, * rdsLastCount */ /*#ifdef DRXJ_SPLIT_UCODE_UPLOAD - FALSE, * flagAudMcUploaded */ + false, * flagAudMcUploaded */ /*#endif * DRXJ_SPLIT_UCODE_UPLOAD */ /* ATV configuartion */ 0UL, /* flags cfg changes */ @@ -782,11 +782,11 @@ DRXJData_t DRXJData_g = { ATV_TOP_EQU3_EQU_C3_BG, ATV_TOP_EQU3_EQU_C3_DK, ATV_TOP_EQU3_EQU_C3_I}, - FALSE, /* flag: TRUE=bypass */ + false, /* flag: true=bypass */ ATV_TOP_VID_PEAK__PRE, /* shadow of ATV_TOP_VID_PEAK__A */ ATV_TOP_NOISE_TH__PRE, /* shadow of ATV_TOP_NOISE_TH__A */ - TRUE, /* flag CVBS ouput enable */ - FALSE, /* flag SIF ouput enable */ + true, /* flag CVBS ouput enable */ + false, /* flag SIF ouput enable */ DRXJ_SIF_ATTENUATION_0DB, /* current SIF att setting */ { /* qamRfAgcCfg */ DRX_STANDARD_ITU_B, /* standard */ @@ -833,12 +833,12 @@ DRXJData_t DRXJData_g = { { /* qamPreSawCfg */ DRX_STANDARD_ITU_B, /* standard */ 0, /* reference */ - FALSE /* usePreSaw */ + false /* usePreSaw */ }, { /* vsbPreSawCfg */ DRX_STANDARD_8VSB, /* standard */ 0, /* reference */ - FALSE /* usePreSaw */ + false /* usePreSaw */ }, /* Version information */ @@ -876,7 +876,7 @@ DRXJData_t DRXJData_g = { } }, #endif - FALSE, /* smartAntInverted */ + false, /* smartAntInverted */ /* Tracking filter setting for OOB */ { 12000, @@ -887,10 +887,10 @@ DRXJData_t DRXJData_g = { 3000, 2000, 0}, - FALSE, /* oobPowerOn */ + false, /* oobPowerOn */ 0, /* mpegTsStaticBitrate */ - FALSE, /* disableTEIhandling */ - FALSE, /* bitReverseMpegOutout */ + false, /* disableTEIhandling */ + false, /* bitReverseMpegOutout */ DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO, /* mpegOutputClockRate */ DRXJ_MPEG_START_WIDTH_1CLKCYC, /* mpegStartWidth */ @@ -898,7 +898,7 @@ DRXJData_t DRXJData_g = { { DRX_STANDARD_NTSC, /* standard */ 7, /* reference */ - TRUE /* usePreSaw */ + true /* usePreSaw */ }, { /* ATV RF-AGC */ DRX_STANDARD_NTSC, /* standard */ @@ -923,7 +923,7 @@ DRXJData_t DRXJData_g = { 140, /* ATV PGA config */ 0, /* currSymbolRate */ - FALSE, /* pdrSafeMode */ + false, /* pdrSafeMode */ SIO_PDR_GPIO_CFG__PRE, /* pdrSafeRestoreValGpio */ SIO_PDR_VSYNC_CFG__PRE, /* pdrSafeRestoreValVSync */ SIO_PDR_SMA_RX_CFG__PRE, /* pdrSafeRestoreValSmaRx */ @@ -932,7 +932,7 @@ DRXJData_t DRXJData_g = { 4, /* oobPreSaw */ DRXJ_OOB_LO_POW_MINUS10DB, /* oobLoPow */ { - FALSE /* audData, only first member */ + false /* audData, only first member */ }, }; @@ -952,25 +952,25 @@ struct i2c_device_addr DRXJDefaultAddr_g = { DRXCommonAttr_t DRXJDefaultCommAttr_g = { (u8 *) NULL, /* ucode ptr */ 0, /* ucode size */ - TRUE, /* ucode verify switch */ + true, /* ucode verify switch */ {0}, /* version record */ 44000, /* IF in kHz in case no tuner instance is used */ (151875 - 0), /* system clock frequency in kHz */ 0, /* oscillator frequency kHz */ 0, /* oscillator deviation in ppm, signed */ - FALSE, /* If TRUE mirror frequency spectrum */ + false, /* If true mirror frequency spectrum */ { /* MPEG output configuration */ - TRUE, /* If TRUE, enable MPEG ouput */ - FALSE, /* If TRUE, insert RS byte */ - TRUE, /* If TRUE, parallel out otherwise serial */ - FALSE, /* If TRUE, invert DATA signals */ - FALSE, /* If TRUE, invert ERR signal */ - FALSE, /* If TRUE, invert STR signals */ - FALSE, /* If TRUE, invert VAL signals */ - FALSE, /* If TRUE, invert CLK signals */ - TRUE, /* If TRUE, static MPEG clockrate will + true, /* If true, enable MPEG ouput */ + false, /* If true, insert RS byte */ + true, /* If true, parallel out otherwise serial */ + false, /* If true, invert DATA signals */ + false, /* If true, invert ERR signal */ + false, /* If true, invert STR signals */ + false, /* If true, invert VAL signals */ + false, /* If true, invert CLK signals */ + true, /* If true, static MPEG clockrate will be used, otherwise clockrate will adapt to the bitrate of the TS */ 19392658UL, /* Maximum bitrate in b/s in case @@ -978,22 +978,22 @@ DRXCommonAttr_t DRXJDefaultCommAttr_g = { DRX_MPEG_STR_WIDTH_1 /* MPEG Start width in clock cycles */ }, /* Initilisations below can be ommited, they require no user input and - are initialy 0, NULL or FALSE. The compiler will initialize them to these + are initialy 0, NULL or false. The compiler will initialize them to these values when ommited. */ - FALSE, /* isOpened */ + false, /* isOpened */ /* SCAN */ NULL, /* no scan params yet */ 0, /* current scan index */ 0, /* next scan frequency */ - FALSE, /* scan ready flag */ + false, /* scan ready flag */ 0, /* max channels to scan */ 0, /* nr of channels scanned */ NULL, /* default scan function */ NULL, /* default context pointer */ 0, /* millisec to wait for demod lock */ DRXJ_DEMOD_LOCK, /* desired lock */ - FALSE, + false, /* Power management */ DRX_POWER_UP, @@ -1002,9 +1002,9 @@ DRXCommonAttr_t DRXJDefaultCommAttr_g = { 1, /* nr of I2C port to wich tuner is */ 0L, /* minimum RF input frequency, in kHz */ 0L, /* maximum RF input frequency, in kHz */ - FALSE, /* Rf Agc Polarity */ - FALSE, /* If Agc Polarity */ - FALSE, /* tuner slow mode */ + false, /* Rf Agc Polarity */ + false, /* If Agc Polarity */ + false, /* tuner slow mode */ { /* current channel (all 0) */ 0UL /* channel.frequency */ @@ -1012,7 +1012,7 @@ DRXCommonAttr_t DRXJDefaultCommAttr_g = { DRX_STANDARD_UNKNOWN, /* current standard */ DRX_STANDARD_UNKNOWN, /* previous standard */ DRX_STANDARD_UNKNOWN, /* diCacheStandard */ - FALSE, /* useBootloader */ + false, /* useBootloader */ 0UL, /* capabilities */ 0 /* mfx */ }; @@ -1037,12 +1037,12 @@ DRXDemodInstance_t DRXJDefaultDemod_g = { * */ DRXAudData_t DRXJDefaultAudData_g = { - FALSE, /* audioIsActive */ + false, /* audioIsActive */ DRX_AUD_STANDARD_AUTO, /* audioStandard */ /* i2sdata */ { - FALSE, /* outputEnable */ + false, /* outputEnable */ 48000, /* frequency */ DRX_I2S_MODE_MASTER, /* mode */ DRX_I2S_WORDLENGTH_32, /* wordLength */ @@ -1051,7 +1051,7 @@ DRXAudData_t DRXJDefaultAudData_g = { }, /* volume */ { - TRUE, /* mute; */ + true, /* mute; */ 0, /* volume */ DRX_AUD_AVC_OFF, /* avcMode */ 0, /* avcRefLevel */ @@ -1102,7 +1102,7 @@ DRXAudData_t DRXJDefaultAudData_g = { DRX_AUD_FM_DEEMPH_75US, /* deemph */ DRX_BTSC_STEREO, /* btscDetect */ 0, /* rdsDataCounter */ - FALSE /* rdsDataPresent */ + false /* rdsDataPresent */ }; /*----------------------------------------------------------------------------- @@ -1158,7 +1158,7 @@ CtrlPowerMode(pDRXDemodInstance_t demod, pDRXPowerMode_t mode); static DRXStatus_t PowerDownAud(pDRXDemodInstance_t demod); #ifndef DRXJ_DIGITAL_ONLY -static DRXStatus_t PowerUpAud(pDRXDemodInstance_t demod, Bool_t setStandard); +static DRXStatus_t PowerUpAud(pDRXDemodInstance_t demod, bool setStandard); #endif static DRXStatus_t @@ -1174,7 +1174,7 @@ CtrlSetCfgAfeGain(pDRXDemodInstance_t demod, pDRXJCfgAfeGain_t afeGain); static DRXStatus_t CtrlUCodeUpload(pDRXDemodInstance_t demod, pDRXUCodeInfo_t mcInfo, - DRXUCodeAction_t action, Bool_t audioMCUpload); + DRXUCodeAction_t action, bool audioMCUpload); #endif /* DRXJ_SPLIT_UCODE_UPLOAD */ /*============================================================================*/ @@ -1683,28 +1683,28 @@ static const u16 NicamPrescTableVal[43] = TODO: check ignoring single/multimaster is ok for AUD access ? */ -#define DRXJ_ISAUDWRITE( addr ) (((((addr)>>16)&1)==1)?TRUE:FALSE) +#define DRXJ_ISAUDWRITE( addr ) (((((addr)>>16)&1)==1)?true:false) #define DRXJ_DAP_AUDTRIF_TIMEOUT 80 /* millisec */ /*============================================================================*/ /** -* \fn Bool_t IsHandledByAudTrIf( DRXaddr_t addr ) +* \fn bool IsHandledByAudTrIf( DRXaddr_t addr ) * \brief Check if this address is handled by the audio token ring interface. * \param addr -* \return Bool_t -* \retval TRUE Yes, handled by audio token ring interface -* \retval FALSE No, not handled by audio token ring interface +* \return bool +* \retval true Yes, handled by audio token ring interface +* \retval false No, not handled by audio token ring interface * */ static -Bool_t IsHandledByAudTrIf(DRXaddr_t addr) +bool IsHandledByAudTrIf(DRXaddr_t addr) { - Bool_t retval = FALSE; + bool retval = false; if ((DRXDAP_FASI_ADDR2BLOCK(addr) == 4) && (DRXDAP_FASI_ADDR2BANK(addr) > 1) && (DRXDAP_FASI_ADDR2BANK(addr) < 6)) { - retval = TRUE; + retval = true; } return (retval); @@ -2097,7 +2097,7 @@ static DRXStatus_t DRXJ_DAP_AtomicReadWriteBlock(struct i2c_device_addr *devAddr, DRXaddr_t addr, u16 datasize, - u8 *data, Bool_t readFlag) + u8 *data, bool readFlag) { DRXJHiCmd_t hiCmd; @@ -2120,7 +2120,7 @@ DRXStatus_t DRXJ_DAP_AtomicReadWriteBlock(struct i2c_device_addr *devAddr, hiCmd.param2 = (u16) DRXDAP_FASI_ADDR2OFFSET(DRXJ_HI_ATOMIC_BUF_START); hiCmd.param3 = (u16) ((datasize / 2) - 1); - if (readFlag == FALSE) { + if (readFlag == false) { hiCmd.param3 |= DRXJ_HI_ATOMIC_WRITE; } else { hiCmd.param3 |= DRXJ_HI_ATOMIC_READ; @@ -2129,7 +2129,7 @@ DRXStatus_t DRXJ_DAP_AtomicReadWriteBlock(struct i2c_device_addr *devAddr, DRXDAP_FASI_ADDR2BANK(addr)); hiCmd.param5 = (u16) DRXDAP_FASI_ADDR2OFFSET(addr); - if (readFlag == FALSE) { + if (readFlag == false) { /* write data to buffer */ for (i = 0; i < (datasize / 2); i++) { @@ -2143,7 +2143,7 @@ DRXStatus_t DRXJ_DAP_AtomicReadWriteBlock(struct i2c_device_addr *devAddr, CHK_ERROR(HICommand(devAddr, &hiCmd, &dummy)); - if (readFlag == TRUE) { + if (readFlag == true) { /* read data from buffer */ for (i = 0; i < (datasize / 2); i++) { DRXJ_DAP_ReadReg16(devAddr, @@ -2181,7 +2181,7 @@ DRXStatus_t DRXJ_DAP_AtomicReadReg32(struct i2c_device_addr *devAddr, } rc = DRXJ_DAP_AtomicReadWriteBlock(devAddr, addr, - sizeof(*data), buf, TRUE); + sizeof(*data), buf, true); word = (u32) buf[3]; word <<= 8; @@ -2262,7 +2262,7 @@ HICommand(struct i2c_device_addr *devAddr, const pDRXJHiCmd_t cmd, u16 *result) { u16 waitCmd = 0; u16 nrRetries = 0; - Bool_t powerdown_cmd = FALSE; + bool powerdown_cmd = false; /* Write parameters */ switch (cmd->cmd) { @@ -2296,11 +2296,11 @@ HICommand(struct i2c_device_addr *devAddr, const pDRXJHiCmd_t cmd, u16 *result) } /* Detect power down to ommit reading result */ - powerdown_cmd = (Bool_t) ((cmd->cmd == SIO_HI_RA_RAM_CMD_CONFIG) && + powerdown_cmd = (bool) ((cmd->cmd == SIO_HI_RA_RAM_CMD_CONFIG) && (((cmd-> param5) & SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) == SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ)); - if (powerdown_cmd == FALSE) { + if (powerdown_cmd == false) { /* Wait until command rdy */ do { nrRetries++; @@ -2315,7 +2315,7 @@ HICommand(struct i2c_device_addr *devAddr, const pDRXJHiCmd_t cmd, u16 *result) RR16(devAddr, SIO_HI_RA_RAM_RES__A, result); } - /* if ( powerdown_cmd == TRUE ) */ + /* if ( powerdown_cmd == true ) */ return (DRX_STS_OK); rw_error: return (DRX_STS_ERROR); @@ -2462,104 +2462,104 @@ static DRXStatus_t GetDeviceCapabilities(pDRXDemodInstance_t demod) bid = (bid >> 10) & 0xf; WR16(devAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE); - extAttr->hasLNA = TRUE; - extAttr->hasNTSC = FALSE; - extAttr->hasBTSC = FALSE; - extAttr->hasOOB = FALSE; - extAttr->hasSMATX = TRUE; - extAttr->hasSMARX = FALSE; - extAttr->hasGPIO = FALSE; - extAttr->hasIRQN = FALSE; + extAttr->hasLNA = true; + extAttr->hasNTSC = false; + extAttr->hasBTSC = false; + extAttr->hasOOB = false; + extAttr->hasSMATX = true; + extAttr->hasSMARX = false; + extAttr->hasGPIO = false; + extAttr->hasIRQN = false; break; case 0x33: - extAttr->hasLNA = FALSE; - extAttr->hasNTSC = FALSE; - extAttr->hasBTSC = FALSE; - extAttr->hasOOB = FALSE; - extAttr->hasSMATX = TRUE; - extAttr->hasSMARX = FALSE; - extAttr->hasGPIO = FALSE; - extAttr->hasIRQN = FALSE; + extAttr->hasLNA = false; + extAttr->hasNTSC = false; + extAttr->hasBTSC = false; + extAttr->hasOOB = false; + extAttr->hasSMATX = true; + extAttr->hasSMARX = false; + extAttr->hasGPIO = false; + extAttr->hasIRQN = false; break; case 0x45: - extAttr->hasLNA = TRUE; - extAttr->hasNTSC = TRUE; - extAttr->hasBTSC = FALSE; - extAttr->hasOOB = FALSE; - extAttr->hasSMATX = TRUE; - extAttr->hasSMARX = TRUE; - extAttr->hasGPIO = TRUE; - extAttr->hasIRQN = FALSE; + extAttr->hasLNA = true; + extAttr->hasNTSC = true; + extAttr->hasBTSC = false; + extAttr->hasOOB = false; + extAttr->hasSMATX = true; + extAttr->hasSMARX = true; + extAttr->hasGPIO = true; + extAttr->hasIRQN = false; break; case 0x46: - extAttr->hasLNA = FALSE; - extAttr->hasNTSC = TRUE; - extAttr->hasBTSC = FALSE; - extAttr->hasOOB = FALSE; - extAttr->hasSMATX = TRUE; - extAttr->hasSMARX = TRUE; - extAttr->hasGPIO = TRUE; - extAttr->hasIRQN = FALSE; + extAttr->hasLNA = false; + extAttr->hasNTSC = true; + extAttr->hasBTSC = false; + extAttr->hasOOB = false; + extAttr->hasSMATX = true; + extAttr->hasSMARX = true; + extAttr->hasGPIO = true; + extAttr->hasIRQN = false; break; case 0x41: - extAttr->hasLNA = TRUE; - extAttr->hasNTSC = TRUE; - extAttr->hasBTSC = TRUE; - extAttr->hasOOB = FALSE; - extAttr->hasSMATX = TRUE; - extAttr->hasSMARX = TRUE; - extAttr->hasGPIO = TRUE; - extAttr->hasIRQN = FALSE; + extAttr->hasLNA = true; + extAttr->hasNTSC = true; + extAttr->hasBTSC = true; + extAttr->hasOOB = false; + extAttr->hasSMATX = true; + extAttr->hasSMARX = true; + extAttr->hasGPIO = true; + extAttr->hasIRQN = false; break; case 0x43: - extAttr->hasLNA = FALSE; - extAttr->hasNTSC = TRUE; - extAttr->hasBTSC = TRUE; - extAttr->hasOOB = FALSE; - extAttr->hasSMATX = TRUE; - extAttr->hasSMARX = TRUE; - extAttr->hasGPIO = TRUE; - extAttr->hasIRQN = FALSE; + extAttr->hasLNA = false; + extAttr->hasNTSC = true; + extAttr->hasBTSC = true; + extAttr->hasOOB = false; + extAttr->hasSMATX = true; + extAttr->hasSMARX = true; + extAttr->hasGPIO = true; + extAttr->hasIRQN = false; break; case 0x32: - extAttr->hasLNA = TRUE; - extAttr->hasNTSC = FALSE; - extAttr->hasBTSC = FALSE; - extAttr->hasOOB = TRUE; - extAttr->hasSMATX = TRUE; - extAttr->hasSMARX = TRUE; - extAttr->hasGPIO = TRUE; - extAttr->hasIRQN = TRUE; + extAttr->hasLNA = true; + extAttr->hasNTSC = false; + extAttr->hasBTSC = false; + extAttr->hasOOB = true; + extAttr->hasSMATX = true; + extAttr->hasSMARX = true; + extAttr->hasGPIO = true; + extAttr->hasIRQN = true; break; case 0x34: - extAttr->hasLNA = FALSE; - extAttr->hasNTSC = TRUE; - extAttr->hasBTSC = TRUE; - extAttr->hasOOB = TRUE; - extAttr->hasSMATX = TRUE; - extAttr->hasSMARX = TRUE; - extAttr->hasGPIO = TRUE; - extAttr->hasIRQN = TRUE; + extAttr->hasLNA = false; + extAttr->hasNTSC = true; + extAttr->hasBTSC = true; + extAttr->hasOOB = true; + extAttr->hasSMATX = true; + extAttr->hasSMARX = true; + extAttr->hasGPIO = true; + extAttr->hasIRQN = true; break; case 0x42: - extAttr->hasLNA = TRUE; - extAttr->hasNTSC = TRUE; - extAttr->hasBTSC = TRUE; - extAttr->hasOOB = TRUE; - extAttr->hasSMATX = TRUE; - extAttr->hasSMARX = TRUE; - extAttr->hasGPIO = TRUE; - extAttr->hasIRQN = TRUE; + extAttr->hasLNA = true; + extAttr->hasNTSC = true; + extAttr->hasBTSC = true; + extAttr->hasOOB = true; + extAttr->hasSMATX = true; + extAttr->hasSMARX = true; + extAttr->hasGPIO = true; + extAttr->hasIRQN = true; break; case 0x44: - extAttr->hasLNA = FALSE; - extAttr->hasNTSC = TRUE; - extAttr->hasBTSC = TRUE; - extAttr->hasOOB = TRUE; - extAttr->hasSMATX = TRUE; - extAttr->hasSMARX = TRUE; - extAttr->hasGPIO = TRUE; - extAttr->hasIRQN = TRUE; + extAttr->hasLNA = false; + extAttr->hasNTSC = true; + extAttr->hasBTSC = true; + extAttr->hasOOB = true; + extAttr->hasSMATX = true; + extAttr->hasSMARX = true; + extAttr->hasGPIO = true; + extAttr->hasIRQN = true; break; default: /* Unknown device variant */ @@ -2663,7 +2663,7 @@ CtrlSetCfgMPEGOutput(pDRXDemodInstance_t demod, pDRXCfgMPEGOutput_t cfgData) extAttr = (pDRXJData_t) demod->myExtAttr; commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; - if (cfgData->enableMPEGOutput == TRUE) { + if (cfgData->enableMPEGOutput == true) { /* quick and dirty patch to set MPEG incase current std is not producing MPEG */ switch (extAttr->standard) { @@ -2740,7 +2740,7 @@ CtrlSetCfgMPEGOutput(pDRXDemodInstance_t demod, pDRXCfgMPEGOutput_t cfgData) FEC_OC_AVR_PARM_A__PRE); WR16(devAddr, FEC_OC_AVR_PARM_B__A, FEC_OC_AVR_PARM_B__PRE); - if (cfgData->staticCLK == TRUE) { + if (cfgData->staticCLK == true) { WR16(devAddr, FEC_OC_RCN_GAIN__A, 0xD); } else { WR16(devAddr, FEC_OC_RCN_GAIN__A, @@ -2756,7 +2756,7 @@ CtrlSetCfgMPEGOutput(pDRXDemodInstance_t demod, pDRXCfgMPEGOutput_t cfgData) /* Check insertion of the Reed-Solomon parity bytes */ RR16(devAddr, FEC_OC_MODE__A, &fecOcRegMode); RR16(devAddr, FEC_OC_IPR_MODE__A, &fecOcRegIprMode); - if (cfgData->insertRSByte == TRUE) { + if (cfgData->insertRSByte == true) { /* enable parity symbol forward */ fecOcRegMode |= FEC_OC_MODE_PARITY__M; /* MVAL disable during parity bytes */ @@ -2780,7 +2780,7 @@ CtrlSetCfgMPEGOutput(pDRXDemodInstance_t demod, pDRXCfgMPEGOutput_t cfgData) break; case DRX_STANDARD_ITU_A: case DRX_STANDARD_ITU_C: - /* insertRSByte = TRUE -> coef = 188/188 -> 1, RS bits are in MPEG output */ + /* insertRSByte = true -> coef = 188/188 -> 1, RS bits are in MPEG output */ rcnRate = (Frac28 (maxBitRate, @@ -2790,7 +2790,7 @@ CtrlSetCfgMPEGOutput(pDRXDemodInstance_t demod, pDRXCfgMPEGOutput_t cfgData) default: return (DRX_STS_ERROR); } /* extAttr->standard */ - } else { /* insertRSByte == FALSE */ + } else { /* insertRSByte == false */ /* disable parity symbol forward */ fecOcRegMode &= (~FEC_OC_MODE_PARITY__M); @@ -2815,7 +2815,7 @@ CtrlSetCfgMPEGOutput(pDRXDemodInstance_t demod, pDRXCfgMPEGOutput_t cfgData) break; case DRX_STANDARD_ITU_A: case DRX_STANDARD_ITU_C: - /* insertRSByte = FALSE -> coef = 188/204, RS bits not in MPEG output */ + /* insertRSByte = false -> coef = 188/204, RS bits not in MPEG output */ rcnRate = (Frac28 (maxBitRate, @@ -2827,44 +2827,44 @@ CtrlSetCfgMPEGOutput(pDRXDemodInstance_t demod, pDRXCfgMPEGOutput_t cfgData) } /* extAttr->standard */ } - if (cfgData->enableParallel == TRUE) { /* MPEG data output is paralel -> clear ipr_mode[0] */ + if (cfgData->enableParallel == true) { /* MPEG data output is paralel -> clear ipr_mode[0] */ fecOcRegIprMode &= (~(FEC_OC_IPR_MODE_SERIAL__M)); } else { /* MPEG data output is serial -> set ipr_mode[0] */ fecOcRegIprMode |= FEC_OC_IPR_MODE_SERIAL__M; } /* Control slective inversion of output bits */ - if (cfgData->invertDATA == TRUE) { + if (cfgData->invertDATA == true) { fecOcRegIprInvert |= InvertDataMask; } else { fecOcRegIprInvert &= (~(InvertDataMask)); } - if (cfgData->invertERR == TRUE) { + if (cfgData->invertERR == true) { fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MERR__M; } else { fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MERR__M)); } - if (cfgData->invertSTR == TRUE) { + if (cfgData->invertSTR == true) { fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MSTRT__M; } else { fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MSTRT__M)); } - if (cfgData->invertVAL == TRUE) { + if (cfgData->invertVAL == true) { fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MVAL__M; } else { fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MVAL__M)); } - if (cfgData->invertCLK == TRUE) { + if (cfgData->invertCLK == true) { fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MCLK__M; } else { fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MCLK__M)); } - if (cfgData->staticCLK == TRUE) { /* Static mode */ + if (cfgData->staticCLK == true) { /* Static mode */ u32 dtoRate = 0; u32 bitRate = 0; u16 fecOcDtoBurstLen = 0; @@ -2875,14 +2875,14 @@ CtrlSetCfgMPEGOutput(pDRXDemodInstance_t demod, pDRXCfgMPEGOutput_t cfgData) switch (extAttr->standard) { case DRX_STANDARD_8VSB: fecOcDtoPeriod = 4; - if (cfgData->insertRSByte == TRUE) { + if (cfgData->insertRSByte == true) { fecOcDtoBurstLen = 208; } break; case DRX_STANDARD_ITU_A: { u32 symbolRateTh = 6400000; - if (cfgData->insertRSByte == TRUE) { + if (cfgData->insertRSByte == true) { fecOcDtoBurstLen = 204; symbolRateTh = 5900000; } @@ -2896,13 +2896,13 @@ CtrlSetCfgMPEGOutput(pDRXDemodInstance_t demod, pDRXCfgMPEGOutput_t cfgData) break; case DRX_STANDARD_ITU_B: fecOcDtoPeriod = 1; - if (cfgData->insertRSByte == TRUE) { + if (cfgData->insertRSByte == true) { fecOcDtoBurstLen = 128; } break; case DRX_STANDARD_ITU_C: fecOcDtoPeriod = 1; - if (cfgData->insertRSByte == TRUE) { + if (cfgData->insertRSByte == true) { fecOcDtoBurstLen = 204; } break; @@ -2960,7 +2960,7 @@ CtrlSetCfgMPEGOutput(pDRXDemodInstance_t demod, pDRXCfgMPEGOutput_t cfgData) MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH << SIO_PDR_MD0_CFG_DRIVE__B | 0x03 << SIO_PDR_MD0_CFG_MODE__B; WR16(devAddr, SIO_PDR_MD0_CFG__A, sioPdrMdCfg); - if (cfgData->enableParallel == TRUE) { /* MPEG data output is paralel -> set MD1 to MD7 to output mode */ + if (cfgData->enableParallel == true) { /* MPEG data output is paralel -> set MD1 to MD7 to output mode */ sioPdrMdCfg = MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH << SIO_PDR_MD0_CFG_DRIVE__B | 0x03 << @@ -3116,7 +3116,7 @@ static DRXStatus_t SetMPEGTEIHandling(pDRXDemodInstance_t demod) FEC_OC_SNC_MODE_CORR_DISABLE__M)); fecOcEmsMode &= (~FEC_OC_EMS_MODE_MODE__M); - if (extAttr->disableTEIhandling == TRUE) { + if (extAttr->disableTEIhandling == true) { /* do not change TEI bit */ fecOcDprMode |= FEC_OC_DPR_MODE_ERR_DISABLE__M; fecOcSncMode |= FEC_OC_SNC_MODE_CORR_DISABLE__M | @@ -3157,7 +3157,7 @@ static DRXStatus_t BitReverseMPEGOutput(pDRXDemodInstance_t demod) /* reset to default (normal bit order) */ fecOcIprMode &= (~FEC_OC_IPR_MODE_REVERSE_ORDER__M); - if (extAttr->bitReverseMpegOutout == TRUE) { + if (extAttr->bitReverseMpegOutout == true) { /* reverse bit order */ fecOcIprMode |= FEC_OC_IPR_MODE_REVERSE_ORDER__M; } @@ -3218,8 +3218,8 @@ static DRXStatus_t SetMPEGStartWidth(pDRXDemodInstance_t demod) extAttr = (pDRXJData_t) demod->myExtAttr; commonAttr = demod->myCommonAttr; - if ((commonAttr->mpegCfg.staticCLK == TRUE) - && (commonAttr->mpegCfg.enableParallel == FALSE)) { + if ((commonAttr->mpegCfg.staticCLK == true) + && (commonAttr->mpegCfg.enableParallel == false)) { RR16(devAddr, FEC_OC_COMM_MB__A, &fecOcCommMb); fecOcCommMb &= ~FEC_OC_COMM_MB_CTL_ON; if (extAttr->mpegStartWidth == DRXJ_MPEG_START_WIDTH_8CLKCYC) { @@ -3261,8 +3261,8 @@ CtrlSetCfgMpegOutputMisc(pDRXDemodInstance_t demod, Set disable TEI bit handling flag. TEI must be left untouched by device in case of BER measurements using external equipment that is unable to ignore the TEI bit in the TS. - Default will FALSE (enable TEI bit handling). - Reverse output bit order. Default is FALSE (msb on MD7 (parallel) or out first (serial)). + Default will false (enable TEI bit handling). + Reverse output bit order. Default is false (msb on MD7 (parallel) or out first (serial)). Set clock rate. Default is auto that is derived from symbol rate. The flags and values will also be used to set registers during a set channel. */ @@ -3389,7 +3389,7 @@ static DRXStatus_t CtrlSetUIOCfg(pDRXDemodInstance_t demod, pDRXUIOCfg_t UIOCfg) /*====================================================================*/ case DRX_UIO1: /* DRX_UIO1: SMA_TX UIO-1 */ - if (extAttr->hasSMATX != TRUE) + if (extAttr->hasSMATX != true) return DRX_STS_ERROR; switch (UIOCfg->mode) { case DRX_UIO_MODE_FIRMWARE_SMA: /* falltrough */ @@ -3409,7 +3409,7 @@ static DRXStatus_t CtrlSetUIOCfg(pDRXDemodInstance_t demod, pDRXUIOCfg_t UIOCfg) /*====================================================================*/ case DRX_UIO2: /* DRX_UIO2: SMA_RX UIO-2 */ - if (extAttr->hasSMARX != TRUE) + if (extAttr->hasSMARX != true) return DRX_STS_ERROR; switch (UIOCfg->mode) { case DRX_UIO_MODE_FIRMWARE0: /* falltrough */ @@ -3429,7 +3429,7 @@ static DRXStatus_t CtrlSetUIOCfg(pDRXDemodInstance_t demod, pDRXUIOCfg_t UIOCfg) /*====================================================================*/ case DRX_UIO3: /* DRX_UIO3: GPIO UIO-3 */ - if (extAttr->hasGPIO != TRUE) + if (extAttr->hasGPIO != true) return DRX_STS_ERROR; switch (UIOCfg->mode) { case DRX_UIO_MODE_FIRMWARE0: /* falltrough */ @@ -3449,7 +3449,7 @@ static DRXStatus_t CtrlSetUIOCfg(pDRXDemodInstance_t demod, pDRXUIOCfg_t UIOCfg) /*====================================================================*/ case DRX_UIO4: /* DRX_UIO4: IRQN UIO-4 */ - if (extAttr->hasIRQN != TRUE) + if (extAttr->hasIRQN != true) return DRX_STS_ERROR; switch (UIOCfg->mode) { case DRX_UIO_MODE_READWRITE: @@ -3492,7 +3492,7 @@ static DRXStatus_t CtrlGetUIOCfg(pDRXDemodInstance_t demod, pDRXUIOCfg_t UIOCfg) pDRXJData_t extAttr = (pDRXJData_t) NULL; pDRXUIOMode_t UIOMode[4] = { NULL }; - pBool_t UIOAvailable[4] = { NULL }; + bool * UIOAvailable[4] = { NULL }; extAttr = demod->myExtAttr; @@ -3514,7 +3514,7 @@ static DRXStatus_t CtrlGetUIOCfg(pDRXDemodInstance_t demod, pDRXUIOCfg_t UIOCfg) return DRX_STS_INVALID_ARG; } - if (*UIOAvailable[UIOCfg->uio] == FALSE) { + if (*UIOAvailable[UIOCfg->uio] == false) { return DRX_STS_ERROR; } @@ -3549,7 +3549,7 @@ CtrlUIOWrite(pDRXDemodInstance_t demod, pDRXUIOData_t UIOData) /*====================================================================*/ case DRX_UIO1: /* DRX_UIO1: SMA_TX UIO-1 */ - if (extAttr->hasSMATX != TRUE) + if (extAttr->hasSMATX != true) return DRX_STS_ERROR; if ((extAttr->uioSmaTxMode != DRX_UIO_MODE_READWRITE) && (extAttr->uioSmaTxMode != DRX_UIO_MODE_FIRMWARE_SAW)) { @@ -3566,7 +3566,7 @@ CtrlUIOWrite(pDRXDemodInstance_t demod, pDRXUIOData_t UIOData) /* use corresponding bit in io data output registar */ RR16(demod->myI2CDevAddr, SIO_PDR_UIO_OUT_LO__A, &value); - if (UIOData->value == FALSE) { + if (UIOData->value == false) { value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */ } else { value |= 0x8000; /* write one to 15th bit - 1st UIO */ @@ -3577,7 +3577,7 @@ CtrlUIOWrite(pDRXDemodInstance_t demod, pDRXUIOData_t UIOData) /*======================================================================*/ case DRX_UIO2: /* DRX_UIO2: SMA_RX UIO-2 */ - if (extAttr->hasSMARX != TRUE) + if (extAttr->hasSMARX != true) return DRX_STS_ERROR; if (extAttr->uioSmaRxMode != DRX_UIO_MODE_READWRITE) { return DRX_STS_ERROR; @@ -3593,7 +3593,7 @@ CtrlUIOWrite(pDRXDemodInstance_t demod, pDRXUIOData_t UIOData) /* use corresponding bit in io data output registar */ RR16(demod->myI2CDevAddr, SIO_PDR_UIO_OUT_LO__A, &value); - if (UIOData->value == FALSE) { + if (UIOData->value == false) { value &= 0xBFFF; /* write zero to 14th bit - 2nd UIO */ } else { value |= 0x4000; /* write one to 14th bit - 2nd UIO */ @@ -3604,7 +3604,7 @@ CtrlUIOWrite(pDRXDemodInstance_t demod, pDRXUIOData_t UIOData) /*====================================================================*/ case DRX_UIO3: /* DRX_UIO3: ASEL UIO-3 */ - if (extAttr->hasGPIO != TRUE) + if (extAttr->hasGPIO != true) return DRX_STS_ERROR; if (extAttr->uioGPIOMode != DRX_UIO_MODE_READWRITE) { return DRX_STS_ERROR; @@ -3620,7 +3620,7 @@ CtrlUIOWrite(pDRXDemodInstance_t demod, pDRXUIOData_t UIOData) /* use corresponding bit in io data output registar */ RR16(demod->myI2CDevAddr, SIO_PDR_UIO_OUT_HI__A, &value); - if (UIOData->value == FALSE) { + if (UIOData->value == false) { value &= 0xFFFB; /* write zero to 2nd bit - 3rd UIO */ } else { value |= 0x0004; /* write one to 2nd bit - 3rd UIO */ @@ -3631,7 +3631,7 @@ CtrlUIOWrite(pDRXDemodInstance_t demod, pDRXUIOData_t UIOData) /*=====================================================================*/ case DRX_UIO4: /* DRX_UIO4: IRQN UIO-4 */ - if (extAttr->hasIRQN != TRUE) + if (extAttr->hasIRQN != true) return DRX_STS_ERROR; if (extAttr->uioIRQNMode != DRX_UIO_MODE_READWRITE) { @@ -3648,7 +3648,7 @@ CtrlUIOWrite(pDRXDemodInstance_t demod, pDRXUIOData_t UIOData) /* use corresponding bit in io data output registar */ RR16(demod->myI2CDevAddr, SIO_PDR_UIO_OUT_LO__A, &value); - if (UIOData->value == FALSE) { + if (UIOData->value == false) { value &= 0xEFFF; /* write zero to 12th bit - 4th UIO */ } else { value |= 0x1000; /* write one to 12th bit - 4th UIO */ @@ -3694,7 +3694,7 @@ static DRXStatus_t CtrlUIORead(pDRXDemodInstance_t demod, pDRXUIOData_t UIOData) /*====================================================================*/ case DRX_UIO1: /* DRX_UIO1: SMA_TX UIO-1 */ - if (extAttr->hasSMATX != TRUE) + if (extAttr->hasSMATX != true) return DRX_STS_ERROR; if (extAttr->uioSmaTxMode != DRX_UIO_MODE_READWRITE) { @@ -3711,15 +3711,15 @@ static DRXStatus_t CtrlUIORead(pDRXDemodInstance_t demod, pDRXUIOData_t UIOData) RR16(demod->myI2CDevAddr, SIO_PDR_UIO_IN_LO__A, &value); if ((value & 0x8000) != 0) { /* check 15th bit - 1st UIO */ - UIOData->value = TRUE; + UIOData->value = true; } else { - UIOData->value = FALSE; + UIOData->value = false; } break; /*======================================================================*/ case DRX_UIO2: /* DRX_UIO2: SMA_RX UIO-2 */ - if (extAttr->hasSMARX != TRUE) + if (extAttr->hasSMARX != true) return DRX_STS_ERROR; if (extAttr->uioSmaRxMode != DRX_UIO_MODE_READWRITE) { @@ -3737,15 +3737,15 @@ static DRXStatus_t CtrlUIORead(pDRXDemodInstance_t demod, pDRXUIOData_t UIOData) RR16(demod->myI2CDevAddr, SIO_PDR_UIO_IN_LO__A, &value); if ((value & 0x4000) != 0) { /* check 14th bit - 2nd UIO */ - UIOData->value = TRUE; + UIOData->value = true; } else { - UIOData->value = FALSE; + UIOData->value = false; } break; /*=====================================================================*/ case DRX_UIO3: /* DRX_UIO3: GPIO UIO-3 */ - if (extAttr->hasGPIO != TRUE) + if (extAttr->hasGPIO != true) return DRX_STS_ERROR; if (extAttr->uioGPIOMode != DRX_UIO_MODE_READWRITE) { @@ -3763,15 +3763,15 @@ static DRXStatus_t CtrlUIORead(pDRXDemodInstance_t demod, pDRXUIOData_t UIOData) /* read io input data registar */ RR16(demod->myI2CDevAddr, SIO_PDR_UIO_IN_HI__A, &value); if ((value & 0x0004) != 0) { /* check 2nd bit - 3rd UIO */ - UIOData->value = TRUE; + UIOData->value = true; } else { - UIOData->value = FALSE; + UIOData->value = false; } break; /*=====================================================================*/ case DRX_UIO4: /* DRX_UIO4: IRQN UIO-4 */ - if (extAttr->hasIRQN != TRUE) + if (extAttr->hasIRQN != true) return DRX_STS_ERROR; if (extAttr->uioIRQNMode != DRX_UIO_MODE_READWRITE) { @@ -3789,9 +3789,9 @@ static DRXStatus_t CtrlUIORead(pDRXDemodInstance_t demod, pDRXUIOData_t UIOData) /* read io input data registar */ RR16(demod->myI2CDevAddr, SIO_PDR_UIO_IN_LO__A, &value); if ((value & 0x1000) != 0) { /* check 12th bit - 4th UIO */ - UIOData->value = TRUE; + UIOData->value = true; } else { - UIOData->value = FALSE; + UIOData->value = false; } break; /*====================================================================*/ @@ -3823,7 +3823,7 @@ rw_error: */ static DRXStatus_t -CtrlI2CBridge(pDRXDemodInstance_t demod, pBool_t bridgeClosed) +CtrlI2CBridge(pDRXDemodInstance_t demod, bool * bridgeClosed) { DRXJHiCmd_t hiCmd; u16 result = 0; @@ -3835,7 +3835,7 @@ CtrlI2CBridge(pDRXDemodInstance_t demod, pBool_t bridgeClosed) hiCmd.cmd = SIO_HI_RA_RAM_CMD_BRDCTRL; hiCmd.param1 = SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY; - if (*bridgeClosed == TRUE) { + if (*bridgeClosed == true) { hiCmd.param2 = SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED; } else { hiCmd.param2 = SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN; @@ -3908,7 +3908,7 @@ CtrlSetCfgSmartAnt(pDRXDemodInstance_t demod, pDRXJCfgSmartAnt_t smartAnt) struct i2c_device_addr *devAddr = NULL; u16 data = 0; u32 startTime = 0; - static Bool_t bitInverted = FALSE; + static bool bitInverted = false; devAddr = demod->myI2CDevAddr; extAttr = (pDRXJData_t) demod->myExtAttr; @@ -4096,7 +4096,7 @@ rw_error: #define ADDR_AT_SCU_SPACE(x) ((x - 0x82E000) * 2) static DRXStatus_t DRXJ_DAP_SCU_AtomicReadWriteBlock(struct i2c_device_addr *devAddr, DRXaddr_t addr, u16 datasize, /* max 30 bytes because the limit of SCU parameter */ - u8 *data, Bool_t readFlag) + u8 *data, bool readFlag) { DRXJSCUCmd_t scuCmd; u16 setParamParameters[15]; @@ -4133,7 +4133,7 @@ DRXStatus_t DRXJ_DAP_SCU_AtomicReadWriteBlock(struct i2c_device_addr *devAddr, D scuCmd.parameter = setParamParameters; CHK_ERROR(SCUCommand(devAddr, &scuCmd)); - if (readFlag == TRUE) { + if (readFlag == true) { int i = 0; /* read data from buffer */ for (i = 0; i < (datasize / 2); i++) { @@ -4168,7 +4168,7 @@ DRXStatus_t DRXJ_DAP_SCU_AtomicReadReg16(struct i2c_device_addr *devAddr, return DRX_STS_INVALID_ARG; } - rc = DRXJ_DAP_SCU_AtomicReadWriteBlock(devAddr, addr, 2, buf, TRUE); + rc = DRXJ_DAP_SCU_AtomicReadWriteBlock(devAddr, addr, 2, buf, true); word = (u16) (buf[0] + (buf[1] << 8)); @@ -4193,7 +4193,7 @@ DRXStatus_t DRXJ_DAP_SCU_AtomicWriteReg16(struct i2c_device_addr *devAddr, buf[0] = (u8) (data & 0xff); buf[1] = (u8) ((data >> 8) & 0xff); - rc = DRXJ_DAP_SCU_AtomicReadWriteBlock(devAddr, addr, 2, buf, FALSE); + rc = DRXJ_DAP_SCU_AtomicReadWriteBlock(devAddr, addr, 2, buf, false); return rc; } @@ -4312,7 +4312,7 @@ rw_error: * \param active * \return DRXStatus_t. */ -static DRXStatus_t IQMSetAf(pDRXDemodInstance_t demod, Bool_t active) +static DRXStatus_t IQMSetAf(pDRXDemodInstance_t demod, bool active) { u16 data = 0; struct i2c_device_addr *devAddr = NULL; @@ -4352,11 +4352,11 @@ CtrlSetCfgATVOutput(pDRXDemodInstance_t demod, pDRXJCfgAtvOutput_t outputCfg); /** * \brief set configuration of pin-safe mode * \param demod instance of demodulator. -* \param enable boolean; TRUE: activate pin-safe mode, FALSE: de-activate p.s.m. +* \param enable boolean; true: activate pin-safe mode, false: de-activate p.s.m. * \return DRXStatus_t. */ static DRXStatus_t -CtrlSetCfgPdrSafeMode(pDRXDemodInstance_t demod, pBool_t enable) +CtrlSetCfgPdrSafeMode(pDRXDemodInstance_t demod, bool * enable) { pDRXJData_t extAttr = (pDRXJData_t) NULL; struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; @@ -4373,8 +4373,8 @@ CtrlSetCfgPdrSafeMode(pDRXDemodInstance_t demod, pBool_t enable) /* Write magic word to enable pdr reg write */ WR16(devAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); - if (*enable == TRUE) { - Bool_t bridgeEnabled = FALSE; + if (*enable == true) { + bool bridgeEnabled = false; /* MPEG pins to input */ WR16(devAddr, SIO_PDR_MSTRT_CFG__A, DRXJ_PIN_SAFE_MODE); @@ -4415,7 +4415,7 @@ CtrlSetCfgPdrSafeMode(pDRXDemodInstance_t demod, pBool_t enable) /* PD_RF_AGC Analog DAC outputs, cannot be set to input or tristate! PD_IF_AGC Analog DAC outputs, cannot be set to input or tristate! */ - CHK_ERROR(IQMSetAf(demod, FALSE)); + CHK_ERROR(IQMSetAf(demod, false)); /* PD_CVBS Analog DAC output, standby mode PD_SIF Analog DAC output, standby mode */ @@ -4482,7 +4482,7 @@ rw_error: * \return DRXStatus_t. */ static DRXStatus_t -CtrlGetCfgPdrSafeMode(pDRXDemodInstance_t demod, pBool_t enabled) +CtrlGetCfgPdrSafeMode(pDRXDemodInstance_t demod, bool * enabled) { pDRXJData_t extAttr = (pDRXJData_t) NULL; @@ -4725,12 +4725,12 @@ static DRXStatus_t InitAGC(pDRXDemodInstance_t demod) WR16(devAddr, SCU_RAM_AGC_CLP_CTRL_MODE__A, clpCtrlMode); agcRf = 0x800 + pAgcRfSettings->cutOffCurrent; - if (commonAttr->tunerRfAgcPol == TRUE) { + if (commonAttr->tunerRfAgcPol == true) { agcRf = 0x87ff - agcRf; } agcIf = 0x800; - if (commonAttr->tunerIfAgcPol == TRUE) { + if (commonAttr->tunerIfAgcPol == true) { agcRf = 0x87ff - agcRf; } @@ -4758,31 +4758,31 @@ rw_error: */ static DRXStatus_t SetFrequency(pDRXDemodInstance_t demod, - pDRXChannel_t channel, DRXFrequency_t tunerFreqOffset) + pDRXChannel_t channel, s32 tunerFreqOffset) { struct i2c_device_addr *devAddr = NULL; pDRXCommonAttr_t commonAttr = NULL; - DRXFrequency_t samplingFrequency = 0; - DRXFrequency_t frequencyShift = 0; - DRXFrequency_t ifFreqActual = 0; - DRXFrequency_t rfFreqResidual = 0; - DRXFrequency_t adcFreq = 0; - DRXFrequency_t intermediateFreq = 0; + s32 samplingFrequency = 0; + s32 frequencyShift = 0; + s32 ifFreqActual = 0; + s32 rfFreqResidual = 0; + s32 adcFreq = 0; + s32 intermediateFreq = 0; u32 iqmFsRateOfs = 0; pDRXJData_t extAttr = NULL; - Bool_t adcFlip = TRUE; - Bool_t selectPosImage = FALSE; - Bool_t rfMirror = FALSE; - Bool_t tunerMirror = TRUE; - Bool_t imageToSelect = TRUE; - DRXFrequency_t fmFrequencyShift = 0; + bool adcFlip = true; + bool selectPosImage = false; + bool rfMirror = false; + bool tunerMirror = true; + bool imageToSelect = true; + s32 fmFrequencyShift = 0; devAddr = demod->myI2CDevAddr; commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; extAttr = (pDRXJData_t) demod->myExtAttr; rfFreqResidual = -1 * tunerFreqOffset; - rfMirror = (extAttr->mirror == DRX_MIRROR_YES) ? TRUE : FALSE; - tunerMirror = demod->myCommonAttr->mirrorFreqSpect ? FALSE : TRUE; + rfMirror = (extAttr->mirror == DRX_MIRROR_YES) ? true : false; + tunerMirror = demod->myCommonAttr->mirrorFreqSpect ? false : true; /* Program frequency shifter No need to account for mirroring on RF @@ -4792,7 +4792,7 @@ SetFrequency(pDRXDemodInstance_t demod, case DRX_STANDARD_ITU_C: /* fallthrough */ case DRX_STANDARD_PAL_SECAM_LP: /* fallthrough */ case DRX_STANDARD_8VSB: - selectPosImage = TRUE; + selectPosImage = true; break; case DRX_STANDARD_FM: /* After IQM FS sound carrier must appear at 4 Mhz in spect. @@ -4805,14 +4805,14 @@ SetFrequency(pDRXDemodInstance_t demod, case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ case DRX_STANDARD_PAL_SECAM_L: - selectPosImage = FALSE; + selectPosImage = false; break; default: return (DRX_STS_INVALID_ARG); } intermediateFreq = demod->myCommonAttr->intermediateFreq; samplingFrequency = demod->myCommonAttr->sysClockFreq / 3; - if (tunerMirror == TRUE) { + if (tunerMirror == true) { /* tuner doesn't mirror */ ifFreqActual = intermediateFreq + rfFreqResidual + fmFrequencyShift; @@ -4824,16 +4824,16 @@ SetFrequency(pDRXDemodInstance_t demod, if (ifFreqActual > samplingFrequency / 2) { /* adc mirrors */ adcFreq = samplingFrequency - ifFreqActual; - adcFlip = TRUE; + adcFlip = true; } else { /* adc doesn't mirror */ adcFreq = ifFreqActual; - adcFlip = FALSE; + adcFlip = false; } frequencyShift = adcFreq; imageToSelect = - (Bool_t) (rfMirror ^ tunerMirror ^ adcFlip ^ selectPosImage); + (bool) (rfMirror ^ tunerMirror ^ adcFlip ^ selectPosImage); iqmFsRateOfs = Frac28(frequencyShift, samplingFrequency); if (imageToSelect) @@ -4843,7 +4843,7 @@ SetFrequency(pDRXDemodInstance_t demod, /* frequencyShift += tunerFreqOffset; TODO */ WR32(devAddr, IQM_FS_RATE_OFS_LO__A, iqmFsRateOfs); extAttr->iqmFsRateOfs = iqmFsRateOfs; - extAttr->posImage = (Bool_t) (rfMirror ^ tunerMirror ^ selectPosImage); + extAttr->posImage = (bool) (rfMirror ^ tunerMirror ^ selectPosImage); return (DRX_STS_OK); rw_error: @@ -4936,10 +4936,10 @@ static DRXStatus_t GetAccPktErr(pDRXDemodInstance_t demod, u16 *packetErr) devAddr = demod->myI2CDevAddr; RR16(devAddr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, &data); - if (extAttr->resetPktErrAcc == TRUE) { + if (extAttr->resetPktErrAcc == true) { lastPktErr = data; pktErr = 0; - extAttr->resetPktErrAcc = FALSE; + extAttr->resetPktErrAcc = false; } if (data < lastPktErr) { @@ -4972,7 +4972,7 @@ static DRXStatus_t CtrlSetCfgResetPktErr(pDRXDemodInstance_t demod) u16 packetError = 0; extAttr = (pDRXJData_t) demod->myExtAttr; - extAttr->resetPktErrAcc = TRUE; + extAttr->resetPktErrAcc = true; /* call to reset counter */ CHK_ERROR(GetAccPktErr(demod, &packetError)); @@ -5027,7 +5027,7 @@ rw_error: */ static DRXStatus_t GetCTLFreqOffset(pDRXDemodInstance_t demod, s32 *CTLFreq) { - DRXFrequency_t samplingFrequency = 0; + s32 samplingFrequency = 0; s32 currentFrequency = 0; s32 nominalFrequency = 0; s32 carrierFrequencyShift = 0; @@ -5048,7 +5048,7 @@ static DRXStatus_t GetCTLFreqOffset(pDRXDemodInstance_t demod, s32 *CTLFreq) nominalFrequency = extAttr->iqmFsRateOfs; ARR32(devAddr, IQM_FS_RATE_LO__A, (u32 *) & currentFrequency); - if (extAttr->posImage == TRUE) { + if (extAttr->posImage == true) { /* negative image */ carrierFrequencyShift = nominalFrequency - currentFrequency; } else { @@ -5082,7 +5082,7 @@ rw_error: * \return DRXStatus_t. */ static DRXStatus_t -SetAgcRf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings, Bool_t atomic) +SetAgcRf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings, bool atomic) { struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; @@ -5321,7 +5321,7 @@ rw_error: * \return DRXStatus_t. */ static DRXStatus_t -SetAgcIf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings, Bool_t atomic) +SetAgcIf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings, bool atomic) { struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; @@ -5573,7 +5573,7 @@ rw_error: * \param active * \return DRXStatus_t. */ -static DRXStatus_t SetIqmAf(pDRXDemodInstance_t demod, Bool_t active) +static DRXStatus_t SetIqmAf(pDRXDemodInstance_t demod, bool active) { u16 data = 0; struct i2c_device_addr *devAddr = NULL; @@ -5621,7 +5621,7 @@ rw_error: * \param channel pointer to channel data. * \return DRXStatus_t. */ -static DRXStatus_t PowerDownVSB(pDRXDemodInstance_t demod, Bool_t primary) +static DRXStatus_t PowerDownVSB(pDRXDemodInstance_t demod, bool primary) { struct i2c_device_addr *devAddr = NULL; DRXJSCUCmd_t cmdSCU = { /* command */ 0, @@ -5651,9 +5651,9 @@ static DRXStatus_t PowerDownVSB(pDRXDemodInstance_t demod, Bool_t primary) /* stop all comm_exec */ WR16(devAddr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP); WR16(devAddr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP); - if (primary == TRUE) { + if (primary == true) { WR16(devAddr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP); - CHK_ERROR(SetIqmAf(demod, FALSE)); + CHK_ERROR(SetIqmAf(demod, false)); } else { WR16(devAddr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP); WR16(devAddr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP); @@ -5662,7 +5662,7 @@ static DRXStatus_t PowerDownVSB(pDRXDemodInstance_t demod, Bool_t primary) WR16(devAddr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP); } - cfgMPEGOutput.enableMPEGOutput = FALSE; + cfgMPEGOutput.enableMPEGOutput = false; CHK_ERROR(CtrlSetCfgMPEGOutput(demod, &cfgMPEGOutput)); return (DRX_STS_OK); @@ -6019,17 +6019,17 @@ static DRXStatus_t SetVSB(pDRXDemodInstance_t demod) WR16(devAddr, VSB_TOP_CKGN1TRK__A, 128); /* B-Input to ADC, PGA+filter in standby */ - if (extAttr->hasLNA == FALSE) { + if (extAttr->hasLNA == false) { WR16(devAddr, IQM_AF_AMUX__A, 0x02); }; /* turn on IQMAF. It has to be in front of setAgc**() */ - CHK_ERROR(SetIqmAf(demod, TRUE)); + CHK_ERROR(SetIqmAf(demod, true)); CHK_ERROR(ADCSynchronization(demod)); CHK_ERROR(InitAGC(demod)); - CHK_ERROR(SetAgcIf(demod, &(extAttr->vsbIfAgcCfg), FALSE)); - CHK_ERROR(SetAgcRf(demod, &(extAttr->vsbRfAgcCfg), FALSE)); + CHK_ERROR(SetAgcIf(demod, &(extAttr->vsbIfAgcCfg), false)); + CHK_ERROR(SetAgcRf(demod, &(extAttr->vsbRfAgcCfg), false)); { /* TODO fix this, store a DRXJCfgAfeGain_t structure in DRXJData_t instead of only the gain */ @@ -6048,7 +6048,7 @@ static DRXStatus_t SetVSB(pDRXDemodInstance_t demod) /* TODO: move to setStandard after hardware reset value problem is solved */ /* Configure initial MPEG output */ DRXCfgMPEGOutput_t cfgMPEGOutput; - cfgMPEGOutput.enableMPEGOutput = TRUE; + cfgMPEGOutput.enableMPEGOutput = true; cfgMPEGOutput.insertRSByte = commonAttr->mpegCfg.insertRSByte; cfgMPEGOutput.enableParallel = commonAttr->mpegCfg.enableParallel; @@ -6310,7 +6310,7 @@ rw_error: * \param channel pointer to channel data. * \return DRXStatus_t. */ -static DRXStatus_t PowerDownQAM(pDRXDemodInstance_t demod, Bool_t primary) +static DRXStatus_t PowerDownQAM(pDRXDemodInstance_t demod, bool primary) { DRXJSCUCmd_t cmdSCU = { /* command */ 0, /* parameterLen */ 0, @@ -6342,9 +6342,9 @@ static DRXStatus_t PowerDownQAM(pDRXDemodInstance_t demod, Bool_t primary) cmdSCU.result = &cmdResult; CHK_ERROR(SCUCommand(devAddr, &cmdSCU)); - if (primary == TRUE) { + if (primary == true) { WR16(devAddr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP); - CHK_ERROR(SetIqmAf(demod, FALSE)); + CHK_ERROR(SetIqmAf(demod, false)); } else { WR16(devAddr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP); WR16(devAddr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP); @@ -6353,7 +6353,7 @@ static DRXStatus_t PowerDownQAM(pDRXDemodInstance_t demod, Bool_t primary) WR16(devAddr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP); } - cfgMPEGOutput.enableMPEGOutput = FALSE; + cfgMPEGOutput.enableMPEGOutput = false; CHK_ERROR(CtrlSetCfgMPEGOutput(demod, &cfgMPEGOutput)); return (DRX_STS_OK); @@ -6949,7 +6949,7 @@ rw_error: */ static DRXStatus_t SetQAM(pDRXDemodInstance_t demod, - pDRXChannel_t channel, DRXFrequency_t tunerFreqOffset, u32 op) + pDRXChannel_t channel, s32 tunerFreqOffset, u32 op) { struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; @@ -7213,7 +7213,7 @@ SetQAM(pDRXDemodInstance_t demod, } if (op & QAM_SET_OP_ALL) { - if (extAttr->hasLNA == FALSE) { + if (extAttr->hasLNA == false) { WR16(devAddr, IQM_AF_AMUX__A, 0x02); } WR16(devAddr, IQM_CF_SYMMETRIC__A, 0); @@ -7288,12 +7288,12 @@ SetQAM(pDRXDemodInstance_t demod, /* No more resets of the IQM, current standard correctly set => now AGCs can be configured. */ /* turn on IQMAF. It has to be in front of setAgc**() */ - CHK_ERROR(SetIqmAf(demod, TRUE)); + CHK_ERROR(SetIqmAf(demod, true)); CHK_ERROR(ADCSynchronization(demod)); CHK_ERROR(InitAGC(demod)); - CHK_ERROR(SetAgcIf(demod, &(extAttr->qamIfAgcCfg), FALSE)); - CHK_ERROR(SetAgcRf(demod, &(extAttr->qamRfAgcCfg), FALSE)); + CHK_ERROR(SetAgcIf(demod, &(extAttr->qamIfAgcCfg), false)); + CHK_ERROR(SetAgcRf(demod, &(extAttr->qamRfAgcCfg), false)); { /* TODO fix this, store a DRXJCfgAfeGain_t structure in DRXJData_t instead of only the gain */ @@ -7371,7 +7371,7 @@ SetQAM(pDRXDemodInstance_t demod, /* Configure initial MPEG output */ DRXCfgMPEGOutput_t cfgMPEGOutput; - cfgMPEGOutput.enableMPEGOutput = TRUE; + cfgMPEGOutput.enableMPEGOutput = true; cfgMPEGOutput.insertRSByte = commonAttr->mpegCfg.insertRSByte; cfgMPEGOutput.enableParallel = @@ -7458,7 +7458,7 @@ static DRXStatus_t qamFlipSpec(pDRXDemodInstance_t demod, pDRXChannel_t channel) /* flip the spec */ WR32(devAddr, IQM_FS_RATE_OFS_LO__A, iqmFsRateOfs); extAttr->iqmFsRateOfs = iqmFsRateOfs; - extAttr->posImage = (extAttr->posImage) ? FALSE : TRUE; + extAttr->posImage = (extAttr->posImage) ? false : true; /* freeze dq/fq updating */ RR16(devAddr, QAM_DQ_MODE__A, &data); @@ -7511,7 +7511,7 @@ rw_error: static DRXStatus_t QAM64Auto(pDRXDemodInstance_t demod, pDRXChannel_t channel, - DRXFrequency_t tunerFreqOffset, pDRXLockStatus_t lockStatus) + s32 tunerFreqOffset, pDRXLockStatus_t lockStatus) { DRXSigQuality_t sigQuality; u16 data = 0; @@ -7625,7 +7625,7 @@ rw_error: static DRXStatus_t QAM256Auto(pDRXDemodInstance_t demod, pDRXChannel_t channel, - DRXFrequency_t tunerFreqOffset, pDRXLockStatus_t lockStatus) + s32 tunerFreqOffset, pDRXLockStatus_t lockStatus) { DRXSigQuality_t sigQuality; u32 state = NO_LOCK; @@ -7693,11 +7693,11 @@ rw_error: */ static DRXStatus_t SetQAMChannel(pDRXDemodInstance_t demod, - pDRXChannel_t channel, DRXFrequency_t tunerFreqOffset) + pDRXChannel_t channel, s32 tunerFreqOffset) { DRXLockStatus_t lockStatus = DRX_NOT_LOCKED; pDRXJData_t extAttr = NULL; - Bool_t autoFlag = FALSE; + bool autoFlag = false; /* external attributes for storing aquired channel constellation */ extAttr = (pDRXJData_t) demod->myExtAttr; @@ -7735,7 +7735,7 @@ SetQAMChannel(pDRXDemodInstance_t demod, break; case DRX_CONSTELLATION_AUTO: /* for channel scan */ if (extAttr->standard == DRX_STANDARD_ITU_B) { - autoFlag = TRUE; + autoFlag = true; /* try to lock default QAM constellation: QAM64 */ channel->constellation = DRX_CONSTELLATION_QAM256; extAttr->constellation = DRX_CONSTELLATION_QAM256; @@ -7788,7 +7788,7 @@ SetQAMChannel(pDRXDemodInstance_t demod, } else if (extAttr->standard == DRX_STANDARD_ITU_C) { channel->constellation = DRX_CONSTELLATION_QAM64; extAttr->constellation = DRX_CONSTELLATION_QAM64; - autoFlag = TRUE; + autoFlag = true; if (channel->mirror == DRX_MIRROR_AUTO) { extAttr->mirror = DRX_MIRROR_NO; @@ -8268,7 +8268,7 @@ static DRXStatus_t AtvEquCoefIndex(DRXStandard_t standard, int *index) * */ static DRXStatus_t -AtvUpdateConfig(pDRXDemodInstance_t demod, Bool_t forceUpdate) +AtvUpdateConfig(pDRXDemodInstance_t demod, bool forceUpdate) { struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; @@ -8415,7 +8415,7 @@ CtrlSetCfgATVOutput(pDRXDemodInstance_t demod, pDRXJCfgAtvOutput_t outputCfg) extAttr->atvCfgChangedFlags |= DRXJ_ATV_CHANGED_OUTPUT; } - CHK_ERROR(AtvUpdateConfig(demod, FALSE)); + CHK_ERROR(AtvUpdateConfig(demod, false)); return (DRX_STS_OK); rw_error: @@ -8465,7 +8465,7 @@ CtrlSetCfgAtvEquCoef(pDRXDemodInstance_t demod, pDRXJCfgAtvEquCoef_t coef) extAttr->atvTopEqu3[index] = coef->coef3; extAttr->atvCfgChangedFlags |= DRXJ_ATV_CHANGED_COEF; - CHK_ERROR(AtvUpdateConfig(demod, FALSE)); + CHK_ERROR(AtvUpdateConfig(demod, false)); return (DRX_STS_OK); rw_error: @@ -8549,7 +8549,7 @@ CtrlSetCfgAtvMisc(pDRXDemodInstance_t demod, pDRXJCfgAtvMisc_t settings) extAttr->atvCfgChangedFlags |= DRXJ_ATV_CHANGED_NOISE_FLT; } - CHK_ERROR(AtvUpdateConfig(demod, FALSE)); + CHK_ERROR(AtvUpdateConfig(demod, false)); return (DRX_STS_OK); rw_error: @@ -8610,15 +8610,15 @@ CtrlGetCfgAtvOutput(pDRXDemodInstance_t demod, pDRXJCfgAtvOutput_t outputCfg) RR16(demod->myI2CDevAddr, ATV_TOP_STDBY__A, &data); if (data & ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE) { - outputCfg->enableCVBSOutput = TRUE; + outputCfg->enableCVBSOutput = true; } else { - outputCfg->enableCVBSOutput = FALSE; + outputCfg->enableCVBSOutput = false; } if (data & ATV_TOP_STDBY_SIF_STDBY_STANDBY) { - outputCfg->enableSIFOutput = FALSE; + outputCfg->enableSIFOutput = false; } else { - outputCfg->enableSIFOutput = TRUE; + outputCfg->enableSIFOutput = true; RR16(demod->myI2CDevAddr, ATV_TOP_AF_SIF_ATT__A, &data); outputCfg->sifAttenuation = (DRXJSIFAttenuation_t) data; } @@ -8753,7 +8753,7 @@ static DRXStatus_t PowerUpATV(pDRXDemodInstance_t demod, DRXStandard_t standard) /* ATV NTSC */ WR16(devAddr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_ACTIVE); /* turn on IQM_AF */ - CHK_ERROR(SetIqmAf(demod, TRUE)); + CHK_ERROR(SetIqmAf(demod, true)); CHK_ERROR(ADCSynchronization(demod)); WR16(devAddr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE); @@ -8780,7 +8780,7 @@ rw_error: * Calls audio power down */ static DRXStatus_t -PowerDownATV(pDRXDemodInstance_t demod, DRXStandard_t standard, Bool_t primary) +PowerDownATV(pDRXDemodInstance_t demod, DRXStandard_t standard, bool primary) { struct i2c_device_addr *devAddr = NULL; DRXJSCUCmd_t cmdSCU = { /* command */ 0, @@ -8809,9 +8809,9 @@ PowerDownATV(pDRXDemodInstance_t demod, DRXStandard_t standard, Bool_t primary) (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE))); WR16(devAddr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_STOP); - if (primary == TRUE) { + if (primary == true) { WR16(devAddr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP); - CHK_ERROR(SetIqmAf(demod, FALSE)); + CHK_ERROR(SetIqmAf(demod, false)); } else { WR16(devAddr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP); WR16(devAddr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP); @@ -9128,15 +9128,15 @@ trouble ? /* Upload only audio microcode */ CHK_ERROR(CtrlUCodeUpload - (demod, &ucodeInfo, UCODE_UPLOAD, TRUE)); + (demod, &ucodeInfo, UCODE_UPLOAD, true)); - if (commonAttr->verifyMicrocode == TRUE) { + if (commonAttr->verifyMicrocode == true) { CHK_ERROR(CtrlUCodeUpload - (demod, &ucodeInfo, UCODE_VERIFY, TRUE)); + (demod, &ucodeInfo, UCODE_VERIFY, true)); } /* Prevent uploading audio microcode again */ - extAttr->flagAudMcUploaded = TRUE; + extAttr->flagAudMcUploaded = true; } #endif /* DRXJ_SPLIT_UCODE_UPLOAD */ @@ -9186,8 +9186,8 @@ trouble ? WR16(devAddr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000); WR16(devAddr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_BG_MN); - extAttr->phaseCorrectionBypass = FALSE; - extAttr->enableCVBSOutput = TRUE; + extAttr->phaseCorrectionBypass = false; + extAttr->enableCVBSOutput = true; break; case DRX_STANDARD_FM: /* FM */ @@ -9208,8 +9208,8 @@ trouble ? (SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW | SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM)); WR16(devAddr, IQM_RT_ROT_BP__A, IQM_RT_ROT_BP_ROT_OFF_OFF); - extAttr->phaseCorrectionBypass = TRUE; - extAttr->enableCVBSOutput = FALSE; + extAttr->phaseCorrectionBypass = true; + extAttr->enableCVBSOutput = false; break; case DRX_STANDARD_PAL_SECAM_BG: /* PAL/SECAM B/G */ @@ -9236,9 +9236,9 @@ trouble ? WR16(devAddr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000); WR16(devAddr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_BG_MN); - extAttr->phaseCorrectionBypass = FALSE; + extAttr->phaseCorrectionBypass = false; extAttr->atvIfAgcCfg.ctrlMode = DRX_AGC_CTRL_AUTO; - extAttr->enableCVBSOutput = TRUE; + extAttr->enableCVBSOutput = true; break; case DRX_STANDARD_PAL_SECAM_DK: /* PAL/SECAM D/K */ @@ -9265,9 +9265,9 @@ trouble ? WR16(devAddr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000); WR16(devAddr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_DK); - extAttr->phaseCorrectionBypass = FALSE; + extAttr->phaseCorrectionBypass = false; extAttr->atvIfAgcCfg.ctrlMode = DRX_AGC_CTRL_AUTO; - extAttr->enableCVBSOutput = TRUE; + extAttr->enableCVBSOutput = true; break; case DRX_STANDARD_PAL_SECAM_I: /* PAL/SECAM I */ @@ -9294,9 +9294,9 @@ trouble ? WR16(devAddr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000); WR16(devAddr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_I); - extAttr->phaseCorrectionBypass = FALSE; + extAttr->phaseCorrectionBypass = false; extAttr->atvIfAgcCfg.ctrlMode = DRX_AGC_CTRL_AUTO; - extAttr->enableCVBSOutput = TRUE; + extAttr->enableCVBSOutput = true; break; case DRX_STANDARD_PAL_SECAM_L: /* PAL/SECAM L with negative modulation */ @@ -9324,10 +9324,10 @@ trouble ? WR16(devAddr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000); WR16(devAddr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_LLP); - extAttr->phaseCorrectionBypass = FALSE; + extAttr->phaseCorrectionBypass = false; extAttr->atvIfAgcCfg.ctrlMode = DRX_AGC_CTRL_USER; extAttr->atvIfAgcCfg.outputLevel = extAttr->atvRfAgcCfg.top; - extAttr->enableCVBSOutput = TRUE; + extAttr->enableCVBSOutput = true; break; case DRX_STANDARD_PAL_SECAM_LP: /* PAL/SECAM L with positive modulation */ @@ -9355,17 +9355,17 @@ trouble ? WR16(devAddr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000); WR16(devAddr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_LLP); - extAttr->phaseCorrectionBypass = FALSE; + extAttr->phaseCorrectionBypass = false; extAttr->atvIfAgcCfg.ctrlMode = DRX_AGC_CTRL_USER; extAttr->atvIfAgcCfg.outputLevel = extAttr->atvRfAgcCfg.top; - extAttr->enableCVBSOutput = TRUE; + extAttr->enableCVBSOutput = true; break; default: return (DRX_STS_ERROR); } /* Common initializations FM & NTSC & B/G & D/K & I & L & LP */ - if (extAttr->hasLNA == FALSE) { + if (extAttr->hasLNA == false) { WR16(devAddr, IQM_AF_AMUX__A, 0x01); } @@ -9409,12 +9409,12 @@ trouble ? WR16(devAddr, SCU_RAM_GPIO__A, 0); /* Override reset values with current shadow settings */ - CHK_ERROR(AtvUpdateConfig(demod, TRUE)); + CHK_ERROR(AtvUpdateConfig(demod, true)); /* Configure/restore AGC settings */ CHK_ERROR(InitAGC(demod)); - CHK_ERROR(SetAgcIf(demod, &(extAttr->atvIfAgcCfg), FALSE)); - CHK_ERROR(SetAgcRf(demod, &(extAttr->atvRfAgcCfg), FALSE)); + CHK_ERROR(SetAgcIf(demod, &(extAttr->atvIfAgcCfg), false)); + CHK_ERROR(SetAgcRf(demod, &(extAttr->atvRfAgcCfg), false)); CHK_ERROR(CtrlSetCfgPreSaw(demod, &(extAttr->atvPreSawCfg))); /* Set SCU ATV substandard,assuming this doesn't require running ATV block */ @@ -9457,7 +9457,7 @@ rw_error: */ static DRXStatus_t SetATVChannel(pDRXDemodInstance_t demod, - DRXFrequency_t tunerFreqOffset, + s32 tunerFreqOffset, pDRXChannel_t channel, DRXStandard_t standard) { DRXJSCUCmd_t cmdSCU = { /* command */ 0, @@ -9495,9 +9495,9 @@ SetATVChannel(pDRXDemodInstance_t demod, cmdSCU.result = &cmdResult; CHK_ERROR(SCUCommand(devAddr, &cmdSCU)); -/* if ( (extAttr->standard == DRX_STANDARD_FM) && (extAttr->flagSetAUDdone == TRUE) ) +/* if ( (extAttr->standard == DRX_STANDARD_FM) && (extAttr->flagSetAUDdone == true) ) { - extAttr->detectedRDS = (Bool_t)FALSE; + extAttr->detectedRDS = (bool)false; }*/ return (DRX_STS_OK); @@ -9526,7 +9526,7 @@ static DRXStatus_t GetATVChannel(pDRXDemodInstance_t demod, pDRXChannel_t channel, DRXStandard_t standard) { - DRXFrequency_t offset = 0; + s32 offset = 0; struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; @@ -9553,7 +9553,7 @@ GetATVChannel(pDRXDemodInstance_t demod, measuredOffset |= 0xFF80; } offset += - (DRXFrequency_t) (((s16) measuredOffset) * 10); + (s32) (((s16) measuredOffset) * 10); break; } case DRX_STANDARD_PAL_SECAM_LP: @@ -9568,7 +9568,7 @@ GetATVChannel(pDRXDemodInstance_t demod, measuredOffset |= 0xFF80; } offset -= - (DRXFrequency_t) (((s16) measuredOffset) * 10); + (s32) (((s16) measuredOffset) * 10); } break; case DRX_STANDARD_FM: @@ -9777,7 +9777,7 @@ rw_error: * \return DRXStatus_t. * */ -static DRXStatus_t PowerUpAud(pDRXDemodInstance_t demod, Bool_t setStandard) +static DRXStatus_t PowerUpAud(pDRXDemodInstance_t demod, bool setStandard) { DRXAudStandard_t audStandard = DRX_AUD_STANDARD_AUTO; struct i2c_device_addr *devAddr = NULL; @@ -9789,7 +9789,7 @@ static DRXStatus_t PowerUpAud(pDRXDemodInstance_t demod, Bool_t setStandard) WR16(devAddr, AUD_TOP_TR_MDE__A, 8); WR16(devAddr, AUD_COMM_EXEC__A, AUD_COMM_EXEC_ACTIVE); - if (setStandard == TRUE) { + if (setStandard == true) { CHK_ERROR(AUDCtrlSetStandard(demod, &audStandard)); } @@ -9816,7 +9816,7 @@ static DRXStatus_t PowerDownAud(pDRXDemodInstance_t demod) WR16(devAddr, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP); - extAttr->audData.audioIsActive = FALSE; + extAttr->audData.audioIsActive = false; return DRX_STS_OK; rw_error: @@ -9848,9 +9848,9 @@ static DRXStatus_t AUDGetModus(pDRXDemodInstance_t demod, u16 *modus) extAttr = (pDRXJData_t) demod->myExtAttr; /* power up */ - if (extAttr->audData.audioIsActive == FALSE) { - CHK_ERROR(PowerUpAud(demod, TRUE)); - extAttr->audData.audioIsActive = TRUE; + if (extAttr->audData.audioIsActive == false) { + CHK_ERROR(PowerUpAud(demod, true)); + extAttr->audData.audioIsActive = true; } /* Modus register is combined in to RAM location */ @@ -9895,12 +9895,12 @@ AUDCtrlGetCfgRDS(pDRXDemodInstance_t demod, pDRXCfgAudRDS_t status) } /* power up */ - if (extAttr->audData.audioIsActive == FALSE) { - CHK_ERROR(PowerUpAud(demod, TRUE)); - extAttr->audData.audioIsActive = TRUE; + if (extAttr->audData.audioIsActive == false) { + CHK_ERROR(PowerUpAud(demod, true)); + extAttr->audData.audioIsActive = true; } - status->valid = FALSE; + status->valid = false; RR16(addr, AUD_DEM_RD_RDS_ARRAY_CNT__A, &rRDSArrayCntInit); @@ -9917,7 +9917,7 @@ AUDCtrlGetCfgRDS(pDRXDemodInstance_t demod, pDRXCfgAudRDS_t status) /* RDS is detected, as long as FM radio is selected assume RDS will be available */ - extAttr->audData.rdsDataPresent = TRUE; + extAttr->audData.rdsDataPresent = true; /* new data */ /* read the data */ @@ -9929,7 +9929,7 @@ AUDCtrlGetCfgRDS(pDRXDemodInstance_t demod, pDRXCfgAudRDS_t status) RR16(addr, AUD_DEM_RD_RDS_ARRAY_CNT__A, &rRDSArrayCntCheck); if (rRDSArrayCntCheck == rRDSArrayCntInit) { - status->valid = TRUE; + status->valid = true; extAttr->audData.rdsDataCounter = rRDSArrayCntCheck; } @@ -9962,17 +9962,17 @@ AUDCtrlGetCarrierDetectStatus(pDRXDemodInstance_t demod, pDRXAudStatus_t status) extAttr = (pDRXJData_t) demod->myExtAttr; /* power up */ - if (extAttr->audData.audioIsActive == FALSE) { - CHK_ERROR(PowerUpAud(demod, TRUE)); - extAttr->audData.audioIsActive = TRUE; + if (extAttr->audData.audioIsActive == false) { + CHK_ERROR(PowerUpAud(demod, true)); + extAttr->audData.audioIsActive = true; } /* initialize the variables */ - status->carrierA = FALSE; - status->carrierB = FALSE; + status->carrierA = false; + status->carrierB = false; status->nicamStatus = DRX_AUD_NICAM_NOT_DETECTED; - status->sap = FALSE; - status->stereo = FALSE; + status->sap = false; + status->stereo = false; /* read stereo sound mode indication */ RR16(devAddr, AUD_DEM_RD_STATUS__A, &rData); @@ -9980,13 +9980,13 @@ AUDCtrlGetCarrierDetectStatus(pDRXDemodInstance_t demod, pDRXAudStatus_t status) /* carrier a detected */ if ((rData & AUD_DEM_RD_STATUS_STAT_CARR_A__M) == AUD_DEM_RD_STATUS_STAT_CARR_A_DETECTED) { - status->carrierA = TRUE; + status->carrierA = true; } /* carrier b detected */ if ((rData & AUD_DEM_RD_STATUS_STAT_CARR_B__M) == AUD_DEM_RD_STATUS_STAT_CARR_B_DETECTED) { - status->carrierB = TRUE; + status->carrierB = true; } /* nicam detected */ if ((rData & AUD_DEM_RD_STATUS_STAT_NICAM__M) == @@ -10002,13 +10002,13 @@ AUDCtrlGetCarrierDetectStatus(pDRXDemodInstance_t demod, pDRXAudStatus_t status) /* audio mode bilingual or SAP detected */ if ((rData & AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__M) == AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP_SAP) { - status->sap = TRUE; + status->sap = true; } /* stereo detected */ if ((rData & AUD_DEM_RD_STATUS_STAT_STEREO__M) == AUD_DEM_RD_STATUS_STAT_STEREO_STEREO) { - status->stereo = TRUE; + status->stereo = true; } return DRX_STS_OK; @@ -10029,7 +10029,7 @@ AUDCtrlGetStatus(pDRXDemodInstance_t demod, pDRXAudStatus_t status) { pDRXJData_t extAttr = NULL; struct i2c_device_addr *devAddr = NULL; - DRXCfgAudRDS_t rds = { FALSE, {0} }; + DRXCfgAudRDS_t rds = { false, {0} }; u16 rData = 0; if (status == NULL) { @@ -10043,7 +10043,7 @@ AUDCtrlGetStatus(pDRXDemodInstance_t demod, pDRXAudStatus_t status) CHK_ERROR(AUDCtrlGetCarrierDetectStatus(demod, status)); /* rds data */ - status->rds = FALSE; + status->rds = false; CHK_ERROR(AUDCtrlGetCfgRDS(demod, &rds)); status->rds = extAttr->audData.rdsDataPresent; @@ -10084,19 +10084,19 @@ AUDCtrlGetCfgVolume(pDRXDemodInstance_t demod, pDRXCfgAudVolume_t volume) extAttr = (pDRXJData_t) demod->myExtAttr; /* power up */ - if (extAttr->audData.audioIsActive == FALSE) { - CHK_ERROR(PowerUpAud(demod, TRUE)); - extAttr->audData.audioIsActive = TRUE; + if (extAttr->audData.audioIsActive == false) { + CHK_ERROR(PowerUpAud(demod, true)); + extAttr->audData.audioIsActive = true; } /* volume */ volume->mute = extAttr->audData.volume.mute; RR16(devAddr, AUD_DSP_WR_VOLUME__A, &rVolume); if (rVolume == 0) { - volume->mute = TRUE; + volume->mute = true; volume->volume = extAttr->audData.volume.volume; } else { - volume->mute = FALSE; + volume->mute = false; volume->volume = ((rVolume & AUD_DSP_WR_VOLUME_VOL_MAIN__M) >> AUD_DSP_WR_VOLUME_VOL_MAIN__B) - AUD_VOLUME_ZERO_DB; @@ -10216,9 +10216,9 @@ AUDCtrlSetCfgVolume(pDRXDemodInstance_t demod, pDRXCfgAudVolume_t volume) extAttr = (pDRXJData_t) demod->myExtAttr; /* power up */ - if (extAttr->audData.audioIsActive == FALSE) { - CHK_ERROR(PowerUpAud(demod, TRUE)); - extAttr->audData.audioIsActive = TRUE; + if (extAttr->audData.audioIsActive == false) { + CHK_ERROR(PowerUpAud(demod, true)); + extAttr->audData.audioIsActive = true; } /* volume */ @@ -10232,7 +10232,7 @@ AUDCtrlSetCfgVolume(pDRXDemodInstance_t demod, pDRXCfgAudVolume_t volume) /* clear the volume mask */ wVolume &= (u16) ~ AUD_DSP_WR_VOLUME_VOL_MAIN__M; - if (volume->mute == TRUE) { + if (volume->mute == true) { /* mute */ /* mute overrules volume */ wVolume |= (u16) (0); @@ -10351,9 +10351,9 @@ AUDCtrlGetCfgOutputI2S(pDRXDemodInstance_t demod, pDRXCfgI2SOutput_t output) extAttr = (pDRXJData_t) demod->myExtAttr; /* power up */ - if (extAttr->audData.audioIsActive == FALSE) { - CHK_ERROR(PowerUpAud(demod, TRUE)); - extAttr->audData.audioIsActive = TRUE; + if (extAttr->audData.audioIsActive == false) { + CHK_ERROR(PowerUpAud(demod, true)); + extAttr->audData.audioIsActive = true; } RR16(devAddr, AUD_DEM_RAM_I2S_CONFIG2__A, &wI2SConfig); @@ -10410,9 +10410,9 @@ AUDCtrlGetCfgOutputI2S(pDRXDemodInstance_t demod, pDRXCfgI2SOutput_t output) /* I2S output enabled */ if ((wI2SConfig & AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__M) == AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_ENABLE) { - output->outputEnable = TRUE; + output->outputEnable = true; } else { - output->outputEnable = FALSE; + output->outputEnable = false; } if (rI2SFreq > 0) { @@ -10457,9 +10457,9 @@ AUDCtrlSetCfgOutputI2S(pDRXDemodInstance_t demod, pDRXCfgI2SOutput_t output) extAttr = (pDRXJData_t) demod->myExtAttr; /* power up */ - if (extAttr->audData.audioIsActive == FALSE) { - CHK_ERROR(PowerUpAud(demod, TRUE)); - extAttr->audData.audioIsActive = TRUE; + if (extAttr->audData.audioIsActive == false) { + CHK_ERROR(PowerUpAud(demod, true)); + extAttr->audData.audioIsActive = true; } RR16(devAddr, AUD_DEM_RAM_I2S_CONFIG2__A, &wI2SConfig); @@ -10521,7 +10521,7 @@ AUDCtrlSetCfgOutputI2S(pDRXDemodInstance_t demod, pDRXCfgI2SOutput_t output) /* I2S output enabled */ wI2SConfig &= (u16) ~ AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__M; - if (output->outputEnable == TRUE) { + if (output->outputEnable == true) { wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_ENABLE; } else { wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_DISABLE; @@ -10609,9 +10609,9 @@ AUDCtrlGetCfgAutoSound(pDRXDemodInstance_t demod, extAttr = (pDRXJData_t) demod->myExtAttr; /* power up */ - if (extAttr->audData.audioIsActive == FALSE) { - CHK_ERROR(PowerUpAud(demod, TRUE)); - extAttr->audData.audioIsActive = TRUE; + if (extAttr->audData.audioIsActive == false) { + CHK_ERROR(PowerUpAud(demod, true)); + extAttr->audData.audioIsActive = true; } CHK_ERROR(AUDGetModus(demod, &rModus)); @@ -10667,9 +10667,9 @@ AUDCtrSetlCfgAutoSound(pDRXDemodInstance_t demod, extAttr = (pDRXJData_t) demod->myExtAttr; /* power up */ - if (extAttr->audData.audioIsActive == FALSE) { - CHK_ERROR(PowerUpAud(demod, TRUE)); - extAttr->audData.audioIsActive = TRUE; + if (extAttr->audData.audioIsActive == false) { + CHK_ERROR(PowerUpAud(demod, true)); + extAttr->audData.audioIsActive = true; } CHK_ERROR(AUDGetModus(demod, &rModus)); @@ -10733,9 +10733,9 @@ AUDCtrlGetCfgASSThres(pDRXDemodInstance_t demod, pDRXCfgAudASSThres_t thres) extAttr = (pDRXJData_t) demod->myExtAttr; /* power up */ - if (extAttr->audData.audioIsActive == FALSE) { - CHK_ERROR(PowerUpAud(demod, TRUE)); - extAttr->audData.audioIsActive = TRUE; + if (extAttr->audData.audioIsActive == false) { + CHK_ERROR(PowerUpAud(demod, true)); + extAttr->audData.audioIsActive = true; } RR16(devAddr, AUD_DEM_RAM_A2_THRSHLD__A, &thresA2); @@ -10773,9 +10773,9 @@ AUDCtrlSetCfgASSThres(pDRXDemodInstance_t demod, pDRXCfgAudASSThres_t thres) extAttr = (pDRXJData_t) demod->myExtAttr; /* power up */ - if (extAttr->audData.audioIsActive == FALSE) { - CHK_ERROR(PowerUpAud(demod, TRUE)); - extAttr->audData.audioIsActive = TRUE; + if (extAttr->audData.audioIsActive == false) { + CHK_ERROR(PowerUpAud(demod, true)); + extAttr->audData.audioIsActive = true; } WR16(devAddr, AUD_DEM_WR_A2_THRSHLD__A, thres->a2); @@ -10828,9 +10828,9 @@ AUDCtrlGetCfgCarrier(pDRXDemodInstance_t demod, pDRXCfgAudCarriers_t carriers) extAttr = (pDRXJData_t) demod->myExtAttr; /* power up */ - if (extAttr->audData.audioIsActive == FALSE) { - CHK_ERROR(PowerUpAud(demod, TRUE)); - extAttr->audData.audioIsActive = TRUE; + if (extAttr->audData.audioIsActive == false) { + CHK_ERROR(PowerUpAud(demod, true)); + extAttr->audData.audioIsActive = true; } CHK_ERROR(AUDGetModus(demod, &wModus)); @@ -10928,9 +10928,9 @@ AUDCtrlSetCfgCarrier(pDRXDemodInstance_t demod, pDRXCfgAudCarriers_t carriers) extAttr = (pDRXJData_t) demod->myExtAttr; /* power up */ - if (extAttr->audData.audioIsActive == FALSE) { - CHK_ERROR(PowerUpAud(demod, TRUE)); - extAttr->audData.audioIsActive = TRUE; + if (extAttr->audData.audioIsActive == false) { + CHK_ERROR(PowerUpAud(demod, true)); + extAttr->audData.audioIsActive = true; } CHK_ERROR(AUDGetModus(demod, &rModus)); @@ -11020,9 +11020,9 @@ AUDCtrlGetCfgMixer(pDRXDemodInstance_t demod, pDRXCfgAudMixer_t mixer) extAttr = (pDRXJData_t) demod->myExtAttr; /* power up */ - if (extAttr->audData.audioIsActive == FALSE) { - CHK_ERROR(PowerUpAud(demod, TRUE)); - extAttr->audData.audioIsActive = TRUE; + if (extAttr->audData.audioIsActive == false) { + CHK_ERROR(PowerUpAud(demod, true)); + extAttr->audData.audioIsActive = true; } /* Source Selctor */ @@ -11115,9 +11115,9 @@ AUDCtrlSetCfgMixer(pDRXDemodInstance_t demod, pDRXCfgAudMixer_t mixer) extAttr = (pDRXJData_t) demod->myExtAttr; /* power up */ - if (extAttr->audData.audioIsActive == FALSE) { - CHK_ERROR(PowerUpAud(demod, TRUE)); - extAttr->audData.audioIsActive = TRUE; + if (extAttr->audData.audioIsActive == false) { + CHK_ERROR(PowerUpAud(demod, true)); + extAttr->audData.audioIsActive = true; } /* Source Selctor */ @@ -11222,9 +11222,9 @@ AUDCtrlSetCfgAVSync(pDRXDemodInstance_t demod, pDRXCfgAudAVSync_t avSync) extAttr = (pDRXJData_t) demod->myExtAttr; /* power up */ - if (extAttr->audData.audioIsActive == FALSE) { - CHK_ERROR(PowerUpAud(demod, TRUE)); - extAttr->audData.audioIsActive = TRUE; + if (extAttr->audData.audioIsActive == false) { + CHK_ERROR(PowerUpAud(demod, true)); + extAttr->audData.audioIsActive = true; } /* audio/video synchronisation */ @@ -11287,9 +11287,9 @@ AUDCtrlGetCfgAVSync(pDRXDemodInstance_t demod, pDRXCfgAudAVSync_t avSync) extAttr = (pDRXJData_t) demod->myExtAttr; /* power up */ - if (extAttr->audData.audioIsActive == FALSE) { - CHK_ERROR(PowerUpAud(demod, TRUE)); - extAttr->audData.audioIsActive = TRUE; + if (extAttr->audData.audioIsActive == false) { + CHK_ERROR(PowerUpAud(demod, true)); + extAttr->audData.audioIsActive = true; } /* audio/video synchronisation */ @@ -11439,9 +11439,9 @@ AUDCtrlGetCfgPrescale(pDRXDemodInstance_t demod, pDRXCfgAudPrescale_t presc) extAttr = (pDRXJData_t) demod->myExtAttr; /* power up */ - if (extAttr->audData.audioIsActive == FALSE) { - CHK_ERROR(PowerUpAud(demod, TRUE)); - extAttr->audData.audioIsActive = TRUE; + if (extAttr->audData.audioIsActive == false) { + CHK_ERROR(PowerUpAud(demod, true)); + extAttr->audData.audioIsActive = true; } /* read register data */ @@ -11514,9 +11514,9 @@ AUDCtrlSetCfgPrescale(pDRXDemodInstance_t demod, pDRXCfgAudPrescale_t presc) extAttr = (pDRXJData_t) demod->myExtAttr; /* power up */ - if (extAttr->audData.audioIsActive == FALSE) { - CHK_ERROR(PowerUpAud(demod, TRUE)); - extAttr->audData.audioIsActive = TRUE; + if (extAttr->audData.audioIsActive == false) { + CHK_ERROR(PowerUpAud(demod, true)); + extAttr->audData.audioIsActive = true; } /* setting of max FM deviation */ @@ -11597,9 +11597,9 @@ static DRXStatus_t AUDCtrlBeep(pDRXDemodInstance_t demod, pDRXAudBeep_t beep) extAttr = (pDRXJData_t) demod->myExtAttr; /* power up */ - if (extAttr->audData.audioIsActive == FALSE) { - CHK_ERROR(PowerUpAud(demod, TRUE)); - extAttr->audData.audioIsActive = TRUE; + if (extAttr->audData.audioIsActive == false) { + CHK_ERROR(PowerUpAud(demod, true)); + extAttr->audData.audioIsActive = true; } if ((beep->volume > 0) || (beep->volume < -127)) { @@ -11619,7 +11619,7 @@ static DRXStatus_t AUDCtrlBeep(pDRXDemodInstance_t demod, pDRXAudBeep_t beep) } theBeep |= (u16) frequency; - if (beep->mute == TRUE) { + if (beep->mute == true) { theBeep = 0; } @@ -11649,7 +11649,7 @@ AUDCtrlSetStandard(pDRXDemodInstance_t demod, pDRXAudStandard_t standard) u16 wModus = 0; u16 rModus = 0; - Bool_t muteBuffer = FALSE; + bool muteBuffer = false; s16 volumeBuffer = 0; u16 wVolume = 0; @@ -11661,19 +11661,19 @@ AUDCtrlSetStandard(pDRXDemodInstance_t demod, pDRXAudStandard_t standard) extAttr = (pDRXJData_t) demod->myExtAttr; /* power up */ - if (extAttr->audData.audioIsActive == FALSE) { - CHK_ERROR(PowerUpAud(demod, FALSE)); - extAttr->audData.audioIsActive = TRUE; + if (extAttr->audData.audioIsActive == false) { + CHK_ERROR(PowerUpAud(demod, false)); + extAttr->audData.audioIsActive = true; } /* reset RDS data availability flag */ - extAttr->audData.rdsDataPresent = FALSE; + extAttr->audData.rdsDataPresent = false; /* we need to mute from here to avoid noise during standard switching */ muteBuffer = extAttr->audData.volume.mute; volumeBuffer = extAttr->audData.volume.volume; - extAttr->audData.volume.mute = TRUE; + extAttr->audData.volume.mute = true; /* restore data structure from DRX ExtAttr, call volume first to mute */ CHK_ERROR(AUDCtrlSetCfgVolume(demod, &extAttr->audData.volume)); CHK_ERROR(AUDCtrlSetCfgCarrier(demod, &extAttr->audData.carriers)); @@ -11794,7 +11794,7 @@ AUDCtrlSetStandard(pDRXDemodInstance_t demod, pDRXAudStandard_t standard) /* buffers intact */ /**************************************************************************/ extAttr->audData.volume.mute = muteBuffer; - if (extAttr->audData.volume.mute == FALSE) { + if (extAttr->audData.volume.mute == false) { wVolume |= (u16) ((volumeBuffer + AUD_VOLUME_ZERO_DB) << AUD_DSP_WR_VOLUME_VOL_MAIN__B); WR16(devAddr, AUD_DSP_WR_VOLUME__A, wVolume); @@ -11832,9 +11832,9 @@ AUDCtrlGetStandard(pDRXDemodInstance_t demod, pDRXAudStandard_t standard) devAddr = (struct i2c_device_addr *) demod->myI2CDevAddr; /* power up */ - if (extAttr->audData.audioIsActive == FALSE) { - CHK_ERROR(PowerUpAud(demod, TRUE)); - extAttr->audData.audioIsActive = TRUE; + if (extAttr->audData.audioIsActive == false) { + CHK_ERROR(PowerUpAud(demod, true)); + extAttr->audData.audioIsActive = true; } *standard = DRX_AUD_STANDARD_UNKNOWN; @@ -11932,7 +11932,7 @@ FmLockStatus(pDRXDemodInstance_t demod, pDRXLockStatus_t lockStat) CHK_ERROR(AUDCtrlGetCarrierDetectStatus(demod, &status)); /* locked if either primary or secondary carrier is detected */ - if ((status.carrierA == TRUE) || (status.carrierB == TRUE)) { + if ((status.carrierA == true) || (status.carrierB == true)) { *lockStat = DRX_LOCKED; } else { *lockStat = DRX_NOT_LOCKED; @@ -12069,7 +12069,7 @@ GetOOBSymbolRateOffset(struct i2c_device_addr *devAddr, s32 *SymbolRateOffset) s32 divisionFactor = 810; u16 data = 0; u32 symbolRate = 0; - Bool_t negative = FALSE; + bool negative = false; *SymbolRateOffset = 0; /* read data rate */ @@ -12100,7 +12100,7 @@ GetOOBSymbolRateOffset(struct i2c_device_addr *devAddr, s32 *SymbolRateOffset) unsignedTimingOffset = 32768; else unsignedTimingOffset = 0x00007FFF & (u32) (-data); - negative = TRUE; + negative = true; } else unsignedTimingOffset = (u32) data; @@ -12132,7 +12132,7 @@ rw_error: * */ static DRXStatus_t -GetOOBFreqOffset(pDRXDemodInstance_t demod, pDRXFrequency_t freqOffset) +GetOOBFreqOffset(pDRXDemodInstance_t demod, s32 *freqOffset) { u16 data = 0; u16 rot = 0; @@ -12233,11 +12233,11 @@ rw_error: * */ static DRXStatus_t -GetOOBFrequency(pDRXDemodInstance_t demod, pDRXFrequency_t frequency) +GetOOBFrequency(pDRXDemodInstance_t demod, s32 *frequency) { u16 data = 0; - DRXFrequency_t freqOffset = 0; - DRXFrequency_t freq = 0; + s32 freqOffset = 0; + s32 freq = 0; struct i2c_device_addr *devAddr = NULL; devAddr = demod->myI2CDevAddr; @@ -12246,7 +12246,7 @@ GetOOBFrequency(pDRXDemodInstance_t demod, pDRXFrequency_t frequency) SARR16(devAddr, SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__A, &data); - freq = (DRXFrequency_t) ((DRXFrequency_t) data * 50 + 50000L); + freq = (s32) ((s32) data * 50 + 50000L); CHK_ERROR(GetOOBFreqOffset(demod, &freqOffset)); @@ -12408,7 +12408,7 @@ rw_error: * \param active * \return DRXStatus_t. */ -static DRXStatus_t SetOrxNsuAox(pDRXDemodInstance_t demod, Bool_t active) +static DRXStatus_t SetOrxNsuAox(pDRXDemodInstance_t demod, bool active) { u16 data = 0; struct i2c_device_addr *devAddr = NULL; @@ -12475,11 +12475,11 @@ static DRXStatus_t CtrlSetOOB(pDRXDemodInstance_t demod, pDRXOOB_t oobParam) { #ifndef DRXJ_DIGITAL_ONLY DRXOOBDownstreamStandard_t standard = DRX_OOB_MODE_A; - DRXFrequency_t freq = 0; /* KHz */ + s32 freq = 0; /* KHz */ struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; u16 i = 0; - Bool_t mirrorFreqSpectOOB = FALSE; + bool mirrorFreqSpectOOB = false; u16 trkFilterValue = 0; DRXJSCUCmd_t scuCmd; u16 setParamParameters[3]; @@ -12512,10 +12512,10 @@ static DRXStatus_t CtrlSetOOB(pDRXDemodInstance_t demod, pDRXOOB_t oobParam) scuCmd.resultLen = 1; scuCmd.result = cmdResult; CHK_ERROR(SCUCommand(devAddr, &scuCmd)); - CHK_ERROR(SetOrxNsuAox(demod, FALSE)); + CHK_ERROR(SetOrxNsuAox(demod, false)); WR16(devAddr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP); - extAttr->oobPowerOn = FALSE; + extAttr->oobPowerOn = false; return (DRX_STS_OK); } @@ -12571,14 +12571,14 @@ static DRXStatus_t CtrlSetOOB(pDRXDemodInstance_t demod, pDRXOOB_t oobParam) case DRX_OOB_MODE_A: if ( /* signal is transmitted inverted */ - ((oobParam->spectrumInverted == TRUE) & + ((oobParam->spectrumInverted == true) & /* and tuner is not mirroring the signal */ - (mirrorFreqSpectOOB == FALSE)) | + (mirrorFreqSpectOOB == false)) | /* or */ /* signal is transmitted noninverted */ - ((oobParam->spectrumInverted == FALSE) & + ((oobParam->spectrumInverted == false) & /* and tuner is mirroring the signal */ - (mirrorFreqSpectOOB == TRUE)) + (mirrorFreqSpectOOB == true)) ) setParamParameters[0] = SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC; @@ -12589,14 +12589,14 @@ static DRXStatus_t CtrlSetOOB(pDRXDemodInstance_t demod, pDRXOOB_t oobParam) case DRX_OOB_MODE_B_GRADE_A: if ( /* signal is transmitted inverted */ - ((oobParam->spectrumInverted == TRUE) & + ((oobParam->spectrumInverted == true) & /* and tuner is not mirroring the signal */ - (mirrorFreqSpectOOB == FALSE)) | + (mirrorFreqSpectOOB == false)) | /* or */ /* signal is transmitted noninverted */ - ((oobParam->spectrumInverted == FALSE) & + ((oobParam->spectrumInverted == false) & /* and tuner is mirroring the signal */ - (mirrorFreqSpectOOB == TRUE)) + (mirrorFreqSpectOOB == true)) ) setParamParameters[0] = SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_INVSPEC; @@ -12608,14 +12608,14 @@ static DRXStatus_t CtrlSetOOB(pDRXDemodInstance_t demod, pDRXOOB_t oobParam) default: if ( /* signal is transmitted inverted */ - ((oobParam->spectrumInverted == TRUE) & + ((oobParam->spectrumInverted == true) & /* and tuner is not mirroring the signal */ - (mirrorFreqSpectOOB == FALSE)) | + (mirrorFreqSpectOOB == false)) | /* or */ /* signal is transmitted noninverted */ - ((oobParam->spectrumInverted == FALSE) & + ((oobParam->spectrumInverted == false) & /* and tuner is mirroring the signal */ - (mirrorFreqSpectOOB == TRUE)) + (mirrorFreqSpectOOB == true)) ) setParamParameters[0] = SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_INVSPEC; @@ -12728,10 +12728,10 @@ static DRXStatus_t CtrlSetOOB(pDRXDemodInstance_t demod, pDRXOOB_t oobParam) scuCmd.result = cmdResult; CHK_ERROR(SCUCommand(devAddr, &scuCmd)); - CHK_ERROR(SetOrxNsuAox(demod, TRUE)); + CHK_ERROR(SetOrxNsuAox(demod, true)); WR16(devAddr, ORX_NSU_AOX_STHR_W__A, extAttr->oobPreSaw); - extAttr->oobPowerOn = TRUE; + extAttr->oobPowerOn = true; return (DRX_STS_OK); rw_error: @@ -12762,7 +12762,7 @@ CtrlGetOOB(pDRXDemodInstance_t demod, pDRXOOBStatus_t oobStatus) return (DRX_STS_INVALID_ARG); } - if (extAttr->oobPowerOn == FALSE) + if (extAttr->oobPowerOn == false) return (DRX_STS_ERROR); RR16(devAddr, ORX_DDC_OFO_SET_W__A, &data); @@ -12908,16 +12908,16 @@ static DRXStatus_t CtrlSetChannel(pDRXDemodInstance_t demod, pDRXChannel_t channel) { - DRXFrequency_t tunerSetFreq = 0; - DRXFrequency_t tunerGetFreq = 0; - DRXFrequency_t tunerFreqOffset = 0; - DRXFrequency_t intermediateFreq = 0; + s32 tunerSetFreq = 0; + s32 tunerGetFreq = 0; + s32 tunerFreqOffset = 0; + s32 intermediateFreq = 0; pDRXJData_t extAttr = NULL; struct i2c_device_addr *devAddr = NULL; DRXStandard_t standard = DRX_STANDARD_UNKNOWN; TUNERMode_t tunerMode = 0; pDRXCommonAttr_t commonAttr = NULL; - Bool_t bridgeClosed = FALSE; + bool bridgeClosed = false; #ifndef DRXJ_VSB_ONLY u32 minSymbolRate = 0; u32 maxSymbolRate = 0; @@ -13093,17 +13093,17 @@ CtrlSetChannel(pDRXDemodInstance_t demod, pDRXChannel_t channel) if ((extAttr->uioSmaTxMode) == DRX_UIO_MODE_FIRMWARE_SAW) { /* SAW SW, user UIO is used for switchable SAW */ - DRXUIOData_t uio1 = { DRX_UIO1, FALSE }; + DRXUIOData_t uio1 = { DRX_UIO1, false }; switch (channel->bandwidth) { case DRX_BANDWIDTH_8MHZ: - uio1.value = TRUE; + uio1.value = true; break; case DRX_BANDWIDTH_7MHZ: - uio1.value = FALSE; + uio1.value = false; break; case DRX_BANDWIDTH_6MHZ: - uio1.value = FALSE; + uio1.value = false; break; case DRX_BANDWIDTH_UNKNOWN: default: @@ -13179,7 +13179,7 @@ CtrlSetChannel(pDRXDemodInstance_t demod, pDRXChannel_t channel) extAttr->frequency = tunerSetFreq; if (commonAttr->tunerPortNr == 1) { /* close tuner bridge */ - bridgeClosed = TRUE; + bridgeClosed = true; CHK_ERROR(CtrlI2CBridge(demod, &bridgeClosed)); /* set tuner frequency */ } @@ -13188,7 +13188,7 @@ CtrlSetChannel(pDRXDemodInstance_t demod, pDRXChannel_t channel) tunerMode, tunerSetFreq)); if (commonAttr->tunerPortNr == 1) { /* open tuner bridge */ - bridgeClosed = FALSE; + bridgeClosed = false; CHK_ERROR(CtrlI2CBridge(demod, &bridgeClosed)); } @@ -13253,7 +13253,7 @@ CtrlSetChannel(pDRXDemodInstance_t demod, pDRXChannel_t channel) if (commonAttr->tunerPortNr == 1) { /* close tuner bridge */ - bridgeClosed = TRUE; + bridgeClosed = true; CHK_ERROR(CtrlI2CBridge(demod, &bridgeClosed)); } @@ -13262,14 +13262,14 @@ CtrlSetChannel(pDRXDemodInstance_t demod, pDRXChannel_t channel) tunerMode, tunerSetFreq)); if (commonAttr->tunerPortNr == 1) { /* open tuner bridge */ - bridgeClosed = FALSE; + bridgeClosed = false; CHK_ERROR(CtrlI2CBridge(demod, &bridgeClosed)); } } /* if ( demod->myTuner !=NULL ) */ /* flag the packet error counter reset */ - extAttr->resetPktErrAcc = TRUE; + extAttr->resetPktErrAcc = true; return (DRX_STS_OK); rw_error: @@ -13294,7 +13294,7 @@ CtrlGetChannel(pDRXDemodInstance_t demod, pDRXChannel_t channel) DRXLockStatus_t lockStatus = DRX_NOT_LOCKED; DRXStandard_t standard = DRX_STANDARD_UNKNOWN; pDRXCommonAttr_t commonAttr = NULL; - DRXFrequency_t intermediateFreq = 0; + s32 intermediateFreq = 0; s32 CTLFreqOffset = 0; u32 iqmRcRateLo = 0; u32 adcFrequency = 0; @@ -13331,8 +13331,8 @@ CtrlGetChannel(pDRXDemodInstance_t demod, pDRXChannel_t channel) channel->ldpc = DRX_LDPC_UNKNOWN; if (demod->myTuner != NULL) { - DRXFrequency_t tunerFreqOffset = 0; - Bool_t tunerMirror = commonAttr->mirrorFreqSpect ? FALSE : TRUE; + s32 tunerFreqOffset = 0; + bool tunerMirror = commonAttr->mirrorFreqSpect ? false : true; /* Get frequency from tuner */ CHK_ERROR(DRXBSP_TUNER_GetFrequency(demod->myTuner, @@ -13340,7 +13340,7 @@ CtrlGetChannel(pDRXDemodInstance_t demod, pDRXChannel_t channel) &(channel->frequency), &intermediateFreq)); tunerFreqOffset = channel->frequency - extAttr->frequency; - if (tunerMirror == TRUE) { + if (tunerMirror == true) { /* positive image */ channel->frequency += tunerFreqOffset; } else { @@ -13838,11 +13838,11 @@ CtrlSetStandard(pDRXDemodInstance_t demod, pDRXStandard_t standard) case DRX_STANDARD_ITU_A: /* fallthrough */ case DRX_STANDARD_ITU_B: /* fallthrough */ case DRX_STANDARD_ITU_C: - CHK_ERROR(PowerDownQAM(demod, FALSE)); + CHK_ERROR(PowerDownQAM(demod, false)); break; #endif case DRX_STANDARD_8VSB: - CHK_ERROR(PowerDownVSB(demod, FALSE)); + CHK_ERROR(PowerDownVSB(demod, false)); break; #ifndef DRXJ_DIGITAL_ONLY case DRX_STANDARD_NTSC: /* fallthrough */ @@ -13852,7 +13852,7 @@ CtrlSetStandard(pDRXDemodInstance_t demod, pDRXStandard_t standard) case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */ case DRX_STANDARD_PAL_SECAM_LP: - CHK_ERROR(PowerDownATV(demod, prevStandard, FALSE)); + CHK_ERROR(PowerDownATV(demod, prevStandard, false)); break; #endif case DRX_STANDARD_UNKNOWN: @@ -14058,10 +14058,10 @@ CtrlPowerMode(pDRXDemodInstance_t demod, pDRXPowerMode_t mode) case DRX_STANDARD_ITU_A: case DRX_STANDARD_ITU_B: case DRX_STANDARD_ITU_C: - CHK_ERROR(PowerDownQAM(demod, TRUE)); + CHK_ERROR(PowerDownQAM(demod, true)); break; case DRX_STANDARD_8VSB: - CHK_ERROR(PowerDownVSB(demod, TRUE)); + CHK_ERROR(PowerDownVSB(demod, true)); break; case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ @@ -14070,7 +14070,7 @@ CtrlPowerMode(pDRXDemodInstance_t demod, pDRXPowerMode_t mode) case DRX_STANDARD_PAL_SECAM_LP: /* fallthrough */ case DRX_STANDARD_NTSC: /* fallthrough */ case DRX_STANDARD_FM: - CHK_ERROR(PowerDownATV(demod, extAttr->standard, TRUE)); + CHK_ERROR(PowerDownATV(demod, extAttr->standard, true)); break; case DRX_STANDARD_UNKNOWN: /* Do nothing */ @@ -14152,7 +14152,7 @@ CtrlVersion(pDRXDemodInstance_t demod, pDRXVersionList_t * versionList) extAttr->vVersion[0].moduleName = ucodeName; extAttr->vVersion[0].vString = extAttr->vText[0]; - if (commonAttr->isOpened == TRUE) { + if (commonAttr->isOpened == true) { SARR16(devAddr, SCU_RAM_VERSION_HI__A, &ucodeMajorMinor); SARR16(devAddr, SCU_RAM_VERSION_LO__A, &ucodePatch); @@ -14280,7 +14280,7 @@ static DRXStatus_t CtrlProbeDevice(pDRXDemodInstance_t demod) commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; - if (commonAttr->isOpened == FALSE + if (commonAttr->isOpened == false || commonAttr->currentPowerMode != DRX_POWER_UP) { struct i2c_device_addr *devAddr = NULL; DRXPowerMode_t powerMode = DRX_POWER_UP; @@ -14291,7 +14291,7 @@ static DRXStatus_t CtrlProbeDevice(pDRXDemodInstance_t demod) /* Remeber original power mode */ orgPowerMode = commonAttr->currentPowerMode; - if (demod->myCommonAttr->isOpened == FALSE) { + if (demod->myCommonAttr->isOpened == false) { CHK_ERROR(PowerUpDevice(demod)); commonAttr->currentPowerMode = DRX_POWER_UP; } else { @@ -14345,16 +14345,16 @@ rw_error: * \fn DRXStatus_t IsMCBlockAudio() * \brief Check if MC block is Audio or not Audio. * \param addr Pointer to demodulator instance. -* \param audioUpload TRUE if MC block is Audio - FALSE if MC block not Audio -* \return Bool_t. +* \param audioUpload true if MC block is Audio + false if MC block not Audio +* \return bool. */ -Bool_t IsMCBlockAudio(u32 addr) +bool IsMCBlockAudio(u32 addr) { if ((addr == AUD_XFP_PRAM_4K__A) || (addr == AUD_XDFP_PRAM_4K__A)) { - return (TRUE); + return (true); } - return (FALSE); + return (false); } /*============================================================================*/ @@ -14365,14 +14365,14 @@ Bool_t IsMCBlockAudio(u32 addr) * \param demod Pointer to demodulator instance. * \param mcInfo Pointer to information about microcode data. * \param action Either UCODE_UPLOAD or UCODE_VERIFY. -* \param uploadAudioMC TRUE if Audio MC need to be uploaded. - FALSE if !Audio MC need to be uploaded. +* \param uploadAudioMC true if Audio MC need to be uploaded. + false if !Audio MC need to be uploaded. * \return DRXStatus_t. */ static DRXStatus_t CtrlUCodeUpload(pDRXDemodInstance_t demod, pDRXUCodeInfo_t mcInfo, - DRXUCodeAction_t action, Bool_t uploadAudioMC) + DRXUCodeAction_t action, bool uploadAudioMC) { u16 i = 0; u16 mcNrOfBlks = 0; @@ -14526,8 +14526,8 @@ CtrlUCodeUpload(pDRXDemodInstance_t demod, mcData += mcBlockNrBytes; } /* for( i = 0 ; iflagAudMcUploaded = FALSE; + if (uploadAudioMC == false) { + extAttr->flagAudMcUploaded = false; } return (DRX_STS_OK); @@ -14636,12 +14636,12 @@ CtrlGetCfgOOBMisc(pDRXDemodInstance_t demod, pDRXJCfgOOBMisc_t misc) SARR16(devAddr, SCU_RAM_ORX_SCU_LOCK__A, &lock); - misc->anaGainLock = ((lock & 0x0001) ? TRUE : FALSE); - misc->digGainLock = ((lock & 0x0002) ? TRUE : FALSE); - misc->freqLock = ((lock & 0x0004) ? TRUE : FALSE); - misc->phaseLock = ((lock & 0x0008) ? TRUE : FALSE); - misc->symTimingLock = ((lock & 0x0010) ? TRUE : FALSE); - misc->eqLock = ((lock & 0x0020) ? TRUE : FALSE); + misc->anaGainLock = ((lock & 0x0001) ? true : false); + misc->digGainLock = ((lock & 0x0002) ? true : false); + misc->freqLock = ((lock & 0x0004) ? true : false); + misc->phaseLock = ((lock & 0x0008) ? true : false); + misc->symTimingLock = ((lock & 0x0010) ? true : false); + misc->eqLock = ((lock & 0x0020) ? true : false); SARR16(devAddr, SCU_RAM_ORX_SCU_STATE__A, &state); misc->state = (state >> 8) & 0xff; @@ -14724,7 +14724,7 @@ CtrlSetCfgAgcIf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings) case DRX_STANDARD_NTSC: /* fallthrough */ case DRX_STANDARD_FM: #endif - return SetAgcIf(demod, agcSettings, TRUE); + return SetAgcIf(demod, agcSettings, true); case DRX_STANDARD_UNKNOWN: default: return (DRX_STS_INVALID_ARG); @@ -14827,7 +14827,7 @@ CtrlSetCfgAgcRf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings) case DRX_STANDARD_NTSC: /* fallthrough */ case DRX_STANDARD_FM: #endif - return SetAgcRf(demod, agcSettings, TRUE); + return SetAgcRf(demod, agcSettings, true); case DRX_STANDARD_UNKNOWN: default: return (DRX_STS_INVALID_ARG); @@ -15293,7 +15293,7 @@ static DRXStatus_t CtrlSetCfg(pDRXDemodInstance_t demod, pDRXCfg_t config) (pDRXCfgMPEGOutput_t) config-> cfgData); case DRX_CFG_PINS_SAFE_MODE: - return CtrlSetCfgPdrSafeMode(demod, (pBool_t) config->cfgData); + return CtrlSetCfgPdrSafeMode(demod, (bool *) config->cfgData); case DRXJ_CFG_AGC_RF: return CtrlSetCfgAgcRf(demod, (pDRXJCfgAgc_t) config->cfgData); case DRXJ_CFG_AGC_IF: @@ -15402,7 +15402,7 @@ static DRXStatus_t CtrlGetCfg(pDRXDemodInstance_t demod, pDRXCfg_t config) (pDRXCfgMPEGOutput_t) config-> cfgData); case DRX_CFG_PINS_SAFE_MODE: - return CtrlGetCfgPdrSafeMode(demod, (pBool_t) config->cfgData); + return CtrlGetCfgPdrSafeMode(demod, (bool *) config->cfgData); case DRXJ_CFG_AGC_RF: return CtrlGetCfgAgcRf(demod, (pDRXJCfgAgc_t) config->cfgData); case DRXJ_CFG_AGC_IF: @@ -15556,13 +15556,13 @@ DRXStatus_t DRXJ_Open(pDRXDemodInstance_t demod) WR16(devAddr, ATV_TOP_STDBY__A, (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE) | ATV_TOP_STDBY_SIF_STDBY_STANDBY); - CHK_ERROR(SetIqmAf(demod, FALSE)); - CHK_ERROR(SetOrxNsuAox(demod, FALSE)); + CHK_ERROR(SetIqmAf(demod, false)); + CHK_ERROR(SetOrxNsuAox(demod, false)); CHK_ERROR(InitHI(demod)); /* disable mpegoutput pins */ - cfgMPEGOutput.enableMPEGOutput = FALSE; + cfgMPEGOutput.enableMPEGOutput = false; CHK_ERROR(CtrlSetCfgMPEGOutput(demod, &cfgMPEGOutput)); /* Stop AUD Inform SetAudio it will need to do all setting */ CHK_ERROR(PowerDownAud(demod)); @@ -15573,27 +15573,27 @@ DRXStatus_t DRXJ_Open(pDRXDemodInstance_t demod) if (commonAttr->microcode != NULL) { /* Dirty trick to use common ucode upload & verify, pretend device is already open */ - commonAttr->isOpened = TRUE; + commonAttr->isOpened = true; ucodeInfo.mcData = commonAttr->microcode; ucodeInfo.mcSize = commonAttr->microcodeSize; #ifdef DRXJ_SPLIT_UCODE_UPLOAD /* Upload microcode without audio part */ CHK_ERROR(CtrlUCodeUpload - (demod, &ucodeInfo, UCODE_UPLOAD, FALSE)); + (demod, &ucodeInfo, UCODE_UPLOAD, false)); #else CHK_ERROR(DRX_Ctrl(demod, DRX_CTRL_LOAD_UCODE, &ucodeInfo)); #endif /* DRXJ_SPLIT_UCODE_UPLOAD */ - if (commonAttr->verifyMicrocode == TRUE) { + if (commonAttr->verifyMicrocode == true) { #ifdef DRXJ_SPLIT_UCODE_UPLOAD CHK_ERROR(CtrlUCodeUpload - (demod, &ucodeInfo, UCODE_VERIFY, FALSE)); + (demod, &ucodeInfo, UCODE_VERIFY, false)); #else CHK_ERROR(DRX_Ctrl (demod, DRX_CTRL_VERIFY_UCODE, &ucodeInfo)); #endif /* DRXJ_SPLIT_UCODE_UPLOAD */ } - commonAttr->isOpened = FALSE; + commonAttr->isOpened = false; } /* Run SCU for a little while to initialize microcode version numbers */ @@ -15604,14 +15604,14 @@ DRXStatus_t DRXJ_Open(pDRXDemodInstance_t demod) demod->myTuner->myCommonAttr->myUserData = (void *)demod; if (commonAttr->tunerPortNr == 1) { - Bool_t bridgeClosed = TRUE; + bool bridgeClosed = true; CHK_ERROR(CtrlI2CBridge(demod, &bridgeClosed)); } CHK_ERROR(DRXBSP_TUNER_Open(demod->myTuner)); if (commonAttr->tunerPortNr == 1) { - Bool_t bridgeClosed = FALSE; + bool bridgeClosed = false; CHK_ERROR(CtrlI2CBridge(demod, &bridgeClosed)); } commonAttr->tunerMinFreqRF = @@ -15666,7 +15666,7 @@ DRXStatus_t DRXJ_Open(pDRXDemodInstance_t demod) extAttr->qamRfAgcCfg.cutOffCurrent = 4000; extAttr->qamPreSawCfg.standard = DRX_STANDARD_ITU_B; extAttr->qamPreSawCfg.reference = 0x07; - extAttr->qamPreSawCfg.usePreSaw = TRUE; + extAttr->qamPreSawCfg.usePreSaw = true; #endif /* Initialize default AFE configuartion for VSB */ extAttr->vsbRfAgcCfg.standard = DRX_STANDARD_8VSB; @@ -15678,7 +15678,7 @@ DRXStatus_t DRXJ_Open(pDRXDemodInstance_t demod) extAttr->vsbRfAgcCfg.cutOffCurrent = 4000; extAttr->vsbPreSawCfg.standard = DRX_STANDARD_8VSB; extAttr->vsbPreSawCfg.reference = 0x07; - extAttr->vsbPreSawCfg.usePreSaw = TRUE; + extAttr->vsbPreSawCfg.usePreSaw = true; #ifndef DRXJ_DIGITAL_ONLY /* Initialize default AFE configuartion for ATV */ @@ -15692,7 +15692,7 @@ DRXStatus_t DRXJ_Open(pDRXDemodInstance_t demod) extAttr->atvIfAgcCfg.speed = 3; extAttr->atvIfAgcCfg.top = 2400; extAttr->atvPreSawCfg.reference = 0x0007; - extAttr->atvPreSawCfg.usePreSaw = TRUE; + extAttr->atvPreSawCfg.usePreSaw = true; extAttr->atvPreSawCfg.standard = DRX_STANDARD_NTSC; #endif extAttr->standard = DRX_STANDARD_UNKNOWN; @@ -15727,7 +15727,7 @@ DRXStatus_t DRXJ_Open(pDRXDemodInstance_t demod) return (DRX_STS_OK); rw_error: - commonAttr->isOpened = FALSE; + commonAttr->isOpened = false; return (DRX_STS_ERROR); } @@ -15755,12 +15755,12 @@ DRXStatus_t DRXJ_Close(pDRXDemodInstance_t demod) if (demod->myTuner != NULL) { /* Check if bridge is used */ if (commonAttr->tunerPortNr == 1) { - Bool_t bridgeClosed = TRUE; + bool bridgeClosed = true; CHK_ERROR(CtrlI2CBridge(demod, &bridgeClosed)); } CHK_ERROR(DRXBSP_TUNER_Close(demod->myTuner)); if (commonAttr->tunerPortNr == 1) { - Bool_t bridgeClosed = FALSE; + bool bridgeClosed = false; CHK_ERROR(CtrlI2CBridge(demod, &bridgeClosed)); } }; @@ -15830,7 +15830,7 @@ DRXJ_Ctrl(pDRXDemodInstance_t demod, DRXCtrlIndex_t ctrl, void *ctrlData) /*======================================================================*/ case DRX_CTRL_I2C_BRIDGE: { - return CtrlI2CBridge(demod, (pBool_t) ctrlData); + return CtrlI2CBridge(demod, (bool *) ctrlData); } break; /*======================================================================*/ @@ -15949,14 +15949,14 @@ DRXJ_Ctrl(pDRXDemodInstance_t demod, DRXCtrlIndex_t ctrl, void *ctrlData) { return CtrlUCodeUpload(demod, (pDRXUCodeInfo_t) ctrlData, - UCODE_UPLOAD, FALSE); + UCODE_UPLOAD, false); } break; case DRX_CTRL_VERIFY_UCODE: { return CtrlUCodeUpload(demod, (pDRXUCodeInfo_t) ctrlData, - UCODE_VERIFY, FALSE); + UCODE_VERIFY, false); } break; #endif /* DRXJ_SPLIT_UCODE_UPLOAD */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.h b/drivers/media/dvb-frontends/drx39xyj/drxj.h index 29b6450..87a8f2c 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.h +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.h @@ -204,7 +204,7 @@ TYPEDEFS typedef struct { DRXStandard_t standard; /* standard to which these settings apply */ u16 reference; /* pre SAW reference value, range 0 .. 31 */ - Bool_t usePreSaw; /* TRUE algorithms must use pre SAW sense */ + bool usePreSaw; /* true algorithms must use pre SAW sense */ } DRXJCfgPreSaw_t, *pDRXJCfgPreSaw_t; /* DRXJ_CFG_AFE_GAIN */ @@ -279,8 +279,8 @@ TYPEDEFS * set MPEG output clock rate */ typedef struct { - Bool_t disableTEIHandling; /**< if TRUE pass (not change) TEI bit */ - Bool_t bitReverseMpegOutout; /**< if TRUE, parallel: msb on MD0; serial: lsb out first */ + bool disableTEIHandling; /**< if true pass (not change) TEI bit */ + bool bitReverseMpegOutout; /**< if true, parallel: msb on MD0; serial: lsb out first */ DRXJMpegOutputClockRate_t mpegOutputClockRate; /**< set MPEG output clock rate that overwirtes the derived one from symbol rate */ DRXJMpegStartWidth_t mpegStartWidth; /**< set MPEG output start width */ @@ -341,12 +341,12 @@ TYPEDEFS typedef struct { DRXJAgcStatus_t agc; - Bool_t eqLock; - Bool_t symTimingLock; - Bool_t phaseLock; - Bool_t freqLock; - Bool_t digGainLock; - Bool_t anaGainLock; + bool eqLock; + bool symTimingLock; + bool phaseLock; + bool freqLock; + bool digGainLock; + bool anaGainLock; u8 state; } DRXJCfgOOBMisc_t, *pDRXJCfgOOBMisc_t; @@ -407,8 +407,8 @@ TYPEDEFS * */ typedef struct { - Bool_t enableCVBSOutput; /* TRUE= enabled */ - Bool_t enableSIFOutput; /* TRUE= enabled */ + bool enableCVBSOutput; /* true= enabled */ + bool enableSIFOutput; /* true= enabled */ DRXJSIFAttenuation_t sifAttenuation; } DRXJCfgAtvOutput_t, *pDRXJCfgAtvOutput_t; @@ -447,25 +447,25 @@ TYPEDEFS */ typedef struct { /* device capabilties (determined during DRX_Open()) */ - Bool_t hasLNA; /**< TRUE if LNA (aka PGA) present */ - Bool_t hasOOB; /**< TRUE if OOB supported */ - Bool_t hasNTSC; /**< TRUE if NTSC supported */ - Bool_t hasBTSC; /**< TRUE if BTSC supported */ - Bool_t hasSMATX; /**< TRUE if mat_tx is available */ - Bool_t hasSMARX; /**< TRUE if mat_rx is available */ - Bool_t hasGPIO; /**< TRUE if GPIO is available */ - Bool_t hasIRQN; /**< TRUE if IRQN is available */ + bool hasLNA; /**< true if LNA (aka PGA) present */ + bool hasOOB; /**< true if OOB supported */ + bool hasNTSC; /**< true if NTSC supported */ + bool hasBTSC; /**< true if BTSC supported */ + bool hasSMATX; /**< true if mat_tx is available */ + bool hasSMARX; /**< true if mat_rx is available */ + bool hasGPIO; /**< true if GPIO is available */ + bool hasIRQN; /**< true if IRQN is available */ /* A1/A2/A... */ u8 mfx; /**< metal fix */ /* tuner settings */ - Bool_t mirrorFreqSpectOOB;/**< tuner inversion (TRUE = tuner mirrors the signal */ + bool mirrorFreqSpectOOB;/**< tuner inversion (true = tuner mirrors the signal */ /* standard/channel settings */ DRXStandard_t standard; /**< current standard information */ DRXConstellation_t constellation; /**< current constellation */ - DRXFrequency_t frequency; /**< center signal frequency in KHz */ + s32 frequency; /**< center signal frequency in KHz */ DRXBandwidth_t currBandwidth; /**< current channel bandwidth */ DRXMirror_t mirror; /**< current channel mirror */ @@ -478,7 +478,7 @@ TYPEDEFS u16 fecRsPlen; /**< defines RS BER measurement period */ u16 fecRsPrescale; /**< ReedSolomon Measurement Prescale */ u16 fecRsPeriod; /**< ReedSolomon Measurement period */ - Bool_t resetPktErrAcc; /**< Set a flag to reset accumulated packet error */ + bool resetPktErrAcc; /**< Set a flag to reset accumulated packet error */ u16 pktErrAccStart; /**< Set a flag to reset accumulated packet error */ /* HI configuration */ @@ -496,7 +496,7 @@ TYPEDEFS /* IQM fs frequecy shift and inversion */ u32 iqmFsRateOfs; /**< frequency shifter setting after setchannel */ - Bool_t posImage; /**< Ture: positive image */ + bool posImage; /**< Ture: positive image */ /* IQM RC frequecy shift */ u32 iqmRcRateOfs; /**< frequency shifter setting after setchannel */ @@ -506,11 +506,11 @@ TYPEDEFS s16 atvTopEqu1[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU1__A */ s16 atvTopEqu2[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU2__A */ s16 atvTopEqu3[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU3__A */ - Bool_t phaseCorrectionBypass;/**< flag: TRUE=bypass */ + bool phaseCorrectionBypass;/**< flag: true=bypass */ s16 atvTopVidPeak; /**< shadow of ATV_TOP_VID_PEAK__A */ u16 atvTopNoiseTh; /**< shadow of ATV_TOP_NOISE_TH__A */ - Bool_t enableCVBSOutput; /**< flag CVBS ouput enable */ - Bool_t enableSIFOutput; /**< flag SIF ouput enable */ + bool enableCVBSOutput; /**< flag CVBS ouput enable */ + bool enableSIFOutput; /**< flag SIF ouput enable */ DRXJSIFAttenuation_t sifAttenuation; /**< current SIF att setting */ /* Agc configuration for QAM and VSB */ @@ -536,16 +536,16 @@ TYPEDEFS /**< allocated version list */ /* smart antenna configuration */ - Bool_t smartAntInverted; + bool smartAntInverted; /* Tracking filter setting for OOB */ u16 oobTrkFilterCfg[8]; - Bool_t oobPowerOn; + bool oobPowerOn; /* MPEG static bitrate setting */ u32 mpegTsStaticBitrate; /**< bitrate static MPEG output */ - Bool_t disableTEIhandling; /**< MPEG TS TEI handling */ - Bool_t bitReverseMpegOutout;/**< MPEG output bit order */ + bool disableTEIhandling; /**< MPEG TS TEI handling */ + bool bitReverseMpegOutout;/**< MPEG output bit order */ DRXJMpegOutputClockRate_t mpegOutputClockRate; /**< MPEG output clock rate */ DRXJMpegStartWidth_t mpegStartWidth; @@ -561,7 +561,7 @@ TYPEDEFS u32 currSymbolRate; /* pin-safe mode */ - Bool_t pdrSafeMode; /**< PDR safe mode activated */ + bool pdrSafeMode; /**< PDR safe mode activated */ u16 pdrSafeRestoreValGpio; u16 pdrSafeRestoreValVSync; u16 pdrSafeRestoreValSmaRx; @@ -631,7 +631,7 @@ DEFINES * Fcentre = Fpc + DRXJ_NTSC_CARRIER_FREQ_OFFSET * */ -#define DRXJ_NTSC_CARRIER_FREQ_OFFSET ((DRXFrequency_t)(1750)) +#define DRXJ_NTSC_CARRIER_FREQ_OFFSET ((s32)(1750)) /** * \def DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET @@ -647,7 +647,7 @@ DEFINES * care of this. * */ -#define DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET ((DRXFrequency_t)(2375)) +#define DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET ((s32)(2375)) /** * \def DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET @@ -663,7 +663,7 @@ DEFINES * care of this. * */ -#define DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET ((DRXFrequency_t)(2775)) +#define DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET ((s32)(2775)) /** * \def DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET @@ -678,7 +678,7 @@ DEFINES * In case the tuner module is NOT used the application programmer must take * care of this. */ -#define DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET ((DRXFrequency_t)(-3255)) +#define DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET ((s32)(-3255)) /** * \def DRXJ_FM_CARRIER_FREQ_OFFSET @@ -694,7 +694,7 @@ DEFINES * Ffm = Fsc + DRXJ_FM_CARRIER_FREQ_OFFSET * */ -#define DRXJ_FM_CARRIER_FREQ_OFFSET ((DRXFrequency_t)(-3000)) +#define DRXJ_FM_CARRIER_FREQ_OFFSET ((s32)(-3000)) /* Revision types -------------------------------------------------------*/ diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj_map.h b/drivers/media/dvb-frontends/drx39xyj/drxj_map.h index 8fad1e5..3ffc7b0 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj_map.h +++ b/drivers/media/dvb-frontends/drx39xyj/drxj_map.h @@ -7331,8 +7331,8 @@ extern "C" { #define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__W 1 #define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__M 0x1 #define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__PRE 0x0 -#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW_FALSE 0x0 -#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW_TRUE 0x1 +#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW_false 0x0 +#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW_true 0x1 #define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__B 1 #define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__W 1 @@ -8130,8 +8130,8 @@ extern "C" { #define SCU_RAM_ATV_DETECT_DETECT__W 1 #define SCU_RAM_ATV_DETECT_DETECT__M 0x1 #define SCU_RAM_ATV_DETECT_DETECT__PRE 0x0 -#define SCU_RAM_ATV_DETECT_DETECT_FALSE 0x0 -#define SCU_RAM_ATV_DETECT_DETECT_TRUE 0x1 +#define SCU_RAM_ATV_DETECT_DETECT_false 0x0 +#define SCU_RAM_ATV_DETECT_DETECT_true 0x1 #define SCU_RAM_ATV_DETECT_TH__A 0x831F4A #define SCU_RAM_ATV_DETECT_TH__W 8 -- cgit v1.1 From 6c1d56c5cb2271567e60a9a94e4d3591d3043ef2 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 20 Mar 2012 01:13:25 -0300 Subject: [media] drx-j: get rid of the bsp*.h headers Move them into drx_driver.h That makes easier to cleanup further what's there at the headers. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/bsp_host.h | 78 ------- drivers/media/dvb-frontends/drx39xyj/bsp_types.h | 55 ----- drivers/media/dvb-frontends/drx39xyj/drx39xxj.c | 2 - .../media/dvb-frontends/drx39xyj/drx39xxj_dummy.c | 2 - .../media/dvb-frontends/drx39xyj/drx_dap_fasi.c | 2 +- drivers/media/dvb-frontends/drx39xyj/drx_driver.c | 1 - drivers/media/dvb-frontends/drx39xyj/drx_driver.h | 252 ++++++++++++++++++++- 7 files changed, 249 insertions(+), 143 deletions(-) delete mode 100644 drivers/media/dvb-frontends/drx39xyj/bsp_host.h delete mode 100644 drivers/media/dvb-frontends/drx39xyj/bsp_types.h diff --git a/drivers/media/dvb-frontends/drx39xyj/bsp_host.h b/drivers/media/dvb-frontends/drx39xyj/bsp_host.h deleted file mode 100644 index 0ce94df..0000000 --- a/drivers/media/dvb-frontends/drx39xyj/bsp_host.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - * Neither the name of Trident Microsystems nor Hauppauge Computer Works - nor the names of its contributors may be used to endorse or promote - products derived from this software without specific prior written - permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. -*/ - -/** -* \file $Id: bsp_host.h,v 1.3 2009/07/07 14:20:30 justin Exp $ -* -* \brief Host and OS dependent type definitions, macro's and functions -* -*/ - -#ifndef __DRXBSP_HOST_H__ -#define __DRXBSP_HOST_H__ -/*------------------------------------------------------------------------- -INCLUDES --------------------------------------------------------------------------*/ -#include "bsp_types.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/*------------------------------------------------------------------------- -TYPEDEFS --------------------------------------------------------------------------*/ - -/*------------------------------------------------------------------------- -DEFINES --------------------------------------------------------------------------*/ - -/*------------------------------------------------------------------------- -Exported FUNCTIONS --------------------------------------------------------------------------*/ - DRXStatus_t DRXBSP_HST_Init(void); - - DRXStatus_t DRXBSP_HST_Term(void); - - void *DRXBSP_HST_Memcpy(void *to, void *from, u32 n); - - int DRXBSP_HST_Memcmp(void *s1, void *s2, u32 n); - - u32 DRXBSP_HST_Clock(void); - - DRXStatus_t DRXBSP_HST_Sleep(u32 n); - -/*------------------------------------------------------------------------- -THE END --------------------------------------------------------------------------*/ -#ifdef __cplusplus -} -#endif -#endif /* __DRXBSP_HOST_H__ */ diff --git a/drivers/media/dvb-frontends/drx39xyj/bsp_types.h b/drivers/media/dvb-frontends/drx39xyj/bsp_types.h deleted file mode 100644 index c65a475..0000000 --- a/drivers/media/dvb-frontends/drx39xyj/bsp_types.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - * Neither the name of Trident Microsystems nor Hauppauge Computer Works - nor the names of its contributors may be used to endorse or promote - products derived from this software without specific prior written - permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. -*/ - -#include - -#ifndef __BSP_TYPES_H__ -#define __BSP_TYPES_H__ - -/*------------------------------------------------------------------------- -ENUM --------------------------------------------------------------------------*/ - -/** -* \enum DRXStatus_t -* \brief Various return statusses -*/ - typedef enum { - DRX_STS_READY = 3, /**< device/service is ready */ - DRX_STS_BUSY = 2, /**< device/service is busy */ - DRX_STS_OK = 1, /**< everything is OK */ - DRX_STS_INVALID_ARG = -1, - /**< invalid arguments */ - DRX_STS_ERROR = -2, /**< general error */ - DRX_STS_FUNC_NOT_AVAILABLE = -3 - /**< unavailable functionality */ - } DRXStatus_t, *pDRXStatus_t; - -#endif /* __BSP_TYPES_H__ */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c index bce41f4b..d68b34b 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c @@ -27,8 +27,6 @@ #include "dvb_frontend.h" #include "drx39xxj.h" #include "drx_driver.h" -#include "bsp_types.h" -#include "bsp_tuner.h" #include "drxj_mc.h" #include "drxj.h" diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c b/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c index 854823e..5471263 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c @@ -8,8 +8,6 @@ #include #include "drx_driver.h" -#include "bsp_types.h" -#include "bsp_tuner.h" #include "drx39xxj.h" /* Dummy function to satisfy drxj.c */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c index 5bf4771..9bea12e 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c @@ -50,7 +50,7 @@ *******************************************************************************/ #include "drx_dap_fasi.h" -#include "bsp_host.h" /* for DRXBSP_HST_Memcpy() */ +#include "drx_driver.h" /* for DRXBSP_HST_Memcpy() */ /*============================================================================*/ diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c index 1d554f2..19aa546 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c @@ -39,7 +39,6 @@ INCLUDE FILES ------------------------------------------------------------------------------*/ #include "drx_driver.h" -#include "bsp_host.h" #define VERSION_FIXED 0 #if VERSION_FIXED diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h index 12e7770..752b2b3 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h @@ -36,13 +36,257 @@ */ #ifndef __DRXDRIVER_H__ #define __DRXDRIVER_H__ + +#include /*------------------------------------------------------------------------- INCLUDES -------------------------------------------------------------------------*/ -#include "bsp_types.h" -#include "bsp_i2c.h" -#include "bsp_tuner.h" -#include "bsp_host.h" + +typedef enum { + DRX_STS_READY = 3, /**< device/service is ready */ + DRX_STS_BUSY = 2, /**< device/service is busy */ + DRX_STS_OK = 1, /**< everything is OK */ + DRX_STS_INVALID_ARG = -1, + /**< invalid arguments */ + DRX_STS_ERROR = -2, /**< general error */ + DRX_STS_FUNC_NOT_AVAILABLE = -3 + /**< unavailable functionality */ +} DRXStatus_t, *pDRXStatus_t; + +/* + * This structure contains the I2C address, the device ID and a userData pointer. + * The userData pointer can be used for application specific purposes. + */ +struct i2c_device_addr { + u16 i2cAddr; /* The I2C address of the device. */ + u16 i2cDevId; /* The device identifier. */ + void *userData; /* User data pointer */ +}; + +/** +* \def IS_I2C_10BIT( addr ) +* \brief Determine if I2C address 'addr' is a 10 bits address or not. +* \param addr The I2C address. +* \return int. +* \retval 0 if address is not a 10 bits I2C address. +* \retval 1 if address is a 10 bits I2C address. +*/ +#define IS_I2C_10BIT(addr) \ + (((addr) & 0xF8) == 0xF0) + +/*------------------------------------------------------------------------------ +Exported FUNCTIONS +------------------------------------------------------------------------------*/ + +/** +* \fn DRXBSP_I2C_Init() +* \brief Initialize I2C communication module. +* \return DRXStatus_t Return status. +* \retval DRX_STS_OK Initialization successful. +* \retval DRX_STS_ERROR Initialization failed. +*/ +DRXStatus_t DRXBSP_I2C_Init(void); + +/** +* \fn DRXBSP_I2C_Term() +* \brief Terminate I2C communication module. +* \return DRXStatus_t Return status. +* \retval DRX_STS_OK Termination successful. +* \retval DRX_STS_ERROR Termination failed. +*/ +DRXStatus_t DRXBSP_I2C_Term(void); + +/** +* \fn DRXStatus_t DRXBSP_I2C_WriteRead( struct i2c_device_addr *wDevAddr, +* u16 wCount, +* u8 * wData, +* struct i2c_device_addr *rDevAddr, +* u16 rCount, +* u8 * rData) +* \brief Read and/or write count bytes from I2C bus, store them in data[]. +* \param wDevAddr The device i2c address and the device ID to write to +* \param wCount The number of bytes to write +* \param wData The array to write the data to +* \param rDevAddr The device i2c address and the device ID to read from +* \param rCount The number of bytes to read +* \param rData The array to read the data from +* \return DRXStatus_t Return status. +* \retval DRX_STS_OK Succes. +* \retval DRX_STS_ERROR Failure. +* \retval DRX_STS_INVALID_ARG Parameter 'wcount' is not zero but parameter +* 'wdata' contains NULL. +* Idem for 'rcount' and 'rdata'. +* Both wDevAddr and rDevAddr are NULL. +* +* This function must implement an atomic write and/or read action on the I2C bus +* No other process may use the I2C bus when this function is executing. +* The critical section of this function runs from and including the I2C +* write, up to and including the I2C read action. +* +* The device ID can be useful if several devices share an I2C address. +* It can be used to control a "switch" on the I2C bus to the correct device. +*/ +DRXStatus_t DRXBSP_I2C_WriteRead(struct i2c_device_addr *wDevAddr, + u16 wCount, + u8 * wData, + struct i2c_device_addr *rDevAddr, + u16 rCount, u8 * rData); + +/** +* \fn DRXBSP_I2C_ErrorText() +* \brief Returns a human readable error. +* Counter part of numerical DRX_I2C_Error_g. +* +* \return char* Pointer to human readable error text. +*/ +char *DRXBSP_I2C_ErrorText(void); + +/** +* \var DRX_I2C_Error_g; +* \brief I2C specific error codes, platform dependent. +*/ +extern int DRX_I2C_Error_g; + +#define TUNER_MODE_SUB0 0x0001 /* for sub-mode (e.g. RF-AGC setting) */ +#define TUNER_MODE_SUB1 0x0002 /* for sub-mode (e.g. RF-AGC setting) */ +#define TUNER_MODE_SUB2 0x0004 /* for sub-mode (e.g. RF-AGC setting) */ +#define TUNER_MODE_SUB3 0x0008 /* for sub-mode (e.g. RF-AGC setting) */ +#define TUNER_MODE_SUB4 0x0010 /* for sub-mode (e.g. RF-AGC setting) */ +#define TUNER_MODE_SUB5 0x0020 /* for sub-mode (e.g. RF-AGC setting) */ +#define TUNER_MODE_SUB6 0x0040 /* for sub-mode (e.g. RF-AGC setting) */ +#define TUNER_MODE_SUB7 0x0080 /* for sub-mode (e.g. RF-AGC setting) */ + +#define TUNER_MODE_DIGITAL 0x0100 /* for digital channel (e.g. DVB-T) */ +#define TUNER_MODE_ANALOG 0x0200 /* for analog channel (e.g. PAL) */ +#define TUNER_MODE_SWITCH 0x0400 /* during channel switch & scanning */ +#define TUNER_MODE_LOCK 0x0800 /* after tuner has locked */ +#define TUNER_MODE_6MHZ 0x1000 /* for 6MHz bandwidth channels */ +#define TUNER_MODE_7MHZ 0x2000 /* for 7MHz bandwidth channels */ +#define TUNER_MODE_8MHZ 0x4000 /* for 8MHz bandwidth channels */ + +#define TUNER_MODE_SUB_MAX 8 +#define TUNER_MODE_SUBALL ( TUNER_MODE_SUB0 | TUNER_MODE_SUB1 | \ + TUNER_MODE_SUB2 | TUNER_MODE_SUB3 | \ + TUNER_MODE_SUB4 | TUNER_MODE_SUB5 | \ + TUNER_MODE_SUB6 | TUNER_MODE_SUB7 ) + +typedef u32 TUNERMode_t; +typedef u32 * pTUNERMode_t; + +typedef char *TUNERSubMode_t; /* description of submode */ +typedef TUNERSubMode_t *pTUNERSubMode_t; + +typedef enum { + + TUNER_LOCKED, + TUNER_NOT_LOCKED +} TUNERLockStatus_t, *pTUNERLockStatus_t; + +typedef struct { + + char *name; /* Tuner brand & type name */ + s32 minFreqRF; /* Lowest RF input frequency, in kHz */ + s32 maxFreqRF; /* Highest RF input frequency, in kHz */ + + u8 subMode; /* Index to sub-mode in use */ + pTUNERSubMode_t subModeDescriptions; /* Pointer to description of sub-modes */ + u8 subModes; /* Number of available sub-modes */ + + /* The following fields will be either 0, NULL or false and do not need + initialisation */ + void *selfCheck; /* gives proof of initialization */ + bool programmed; /* only valid if selfCheck is OK */ + s32 RFfrequency; /* only valid if programmed */ + s32 IFfrequency; /* only valid if programmed */ + + void *myUserData; /* pointer to associated demod instance */ + u16 myCapabilities; /* value for storing application flags */ + +} TUNERCommonAttr_t, *pTUNERCommonAttr_t; + +typedef struct TUNERInstance_s *pTUNERInstance_t; + +typedef DRXStatus_t(*TUNEROpenFunc_t) (pTUNERInstance_t tuner); +typedef DRXStatus_t(*TUNERCloseFunc_t) (pTUNERInstance_t tuner); + +typedef DRXStatus_t(*TUNERSetFrequencyFunc_t) (pTUNERInstance_t tuner, + TUNERMode_t mode, + s32 + frequency); + +typedef DRXStatus_t(*TUNERGetFrequencyFunc_t) (pTUNERInstance_t tuner, + TUNERMode_t mode, + s32 * + RFfrequency, + s32 * + IFfrequency); + +typedef DRXStatus_t(*TUNERLockStatusFunc_t) (pTUNERInstance_t tuner, + pTUNERLockStatus_t + lockStat); + +typedef DRXStatus_t(*TUNERi2cWriteReadFunc_t) (pTUNERInstance_t tuner, + struct i2c_device_addr * + wDevAddr, u16 wCount, + u8 * wData, + struct i2c_device_addr * + rDevAddr, u16 rCount, + u8 * rData); + +typedef struct { + TUNEROpenFunc_t openFunc; + TUNERCloseFunc_t closeFunc; + TUNERSetFrequencyFunc_t setFrequencyFunc; + TUNERGetFrequencyFunc_t getFrequencyFunc; + TUNERLockStatusFunc_t lockStatusFunc; + TUNERi2cWriteReadFunc_t i2cWriteReadFunc; + +} TUNERFunc_t, *pTUNERFunc_t; + +typedef struct TUNERInstance_s { + + struct i2c_device_addr myI2CDevAddr; + pTUNERCommonAttr_t myCommonAttr; + void *myExtAttr; + pTUNERFunc_t myFunct; + +} TUNERInstance_t; + +DRXStatus_t DRXBSP_TUNER_Open(pTUNERInstance_t tuner); + +DRXStatus_t DRXBSP_TUNER_Close(pTUNERInstance_t tuner); + +DRXStatus_t DRXBSP_TUNER_SetFrequency(pTUNERInstance_t tuner, + TUNERMode_t mode, + s32 frequency); + +DRXStatus_t DRXBSP_TUNER_GetFrequency(pTUNERInstance_t tuner, + TUNERMode_t mode, + s32 * RFfrequency, + s32 * IFfrequency); + +DRXStatus_t DRXBSP_TUNER_LockStatus(pTUNERInstance_t tuner, + pTUNERLockStatus_t lockStat); + +DRXStatus_t DRXBSP_TUNER_DefaultI2CWriteRead(pTUNERInstance_t tuner, + struct i2c_device_addr *wDevAddr, + u16 wCount, + u8 * wData, + struct i2c_device_addr *rDevAddr, + u16 rCount, u8 * rData); + +DRXStatus_t DRXBSP_HST_Init(void); + +DRXStatus_t DRXBSP_HST_Term(void); + +void *DRXBSP_HST_Memcpy(void *to, void *from, u32 n); + +int DRXBSP_HST_Memcmp(void *s1, void *s2, u32 n); + +u32 DRXBSP_HST_Clock(void); + +DRXStatus_t DRXBSP_HST_Sleep(u32 n); + #ifdef __cplusplus extern "C" { -- cgit v1.1 From 61263c751bafaecb3a23a7f9db05db9addc5f0f6 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 20 Mar 2012 01:18:02 -0300 Subject: [media] drx-j: get rid of most of the typedefs There are lots of typedefs there. Let's get rid of them. Most of the work here is due to this small script: if [ "$3" == "" ]; then echo "usage: $0 type DRXName drx_name" fi t=$1; f=$2; g=$3 for i in *.[ch]; do sed s,"p${f}_t","$t $g *",g <$i >a && mv a $i && \ sed s,"${f}_t","$t $g",g <$i >a && mv a $i done Just kept there the function typedefs, as those are still useful. Yet, all those tuner_ops can likely be just removed on a latter cleanup patch. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drx39xxj.c | 20 +- drivers/media/dvb-frontends/drx39xyj/drx39xxj.h | 2 +- .../media/dvb-frontends/drx39xyj/drx39xxj_dummy.c | 18 +- .../media/dvb-frontends/drx39xyj/drx_dap_fasi.c | 70 +- drivers/media/dvb-frontends/drx39xyj/drx_driver.c | 96 +- drivers/media/dvb-frontends/drx39xyj/drx_driver.h | 664 +++++++------- drivers/media/dvb-frontends/drx39xyj/drxj.c | 974 ++++++++++----------- drivers/media/dvb-frontends/drx39xyj/drxj.h | 22 +- 8 files changed, 918 insertions(+), 948 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c index d68b34b..414d152 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c @@ -34,7 +34,7 @@ static int drx39xxj_set_powerstate(struct dvb_frontend *fe, int enable) { struct drx39xxj_state *state = fe->demodulator_priv; DRXDemodInstance_t *demod = state->demod; - DRXStatus_t result; + int result; DRXPowerMode_t powerMode; if (enable) @@ -56,7 +56,7 @@ static int drx39xxj_read_status(struct dvb_frontend *fe, fe_status_t *status) { struct drx39xxj_state *state = fe->demodulator_priv; DRXDemodInstance_t *demod = state->demod; - DRXStatus_t result; + int result; DRXLockStatus_t lock_status; *status = 0; @@ -103,7 +103,7 @@ static int drx39xxj_read_ber(struct dvb_frontend *fe, u32 *ber) { struct drx39xxj_state *state = fe->demodulator_priv; DRXDemodInstance_t *demod = state->demod; - DRXStatus_t result; + int result; DRXSigQuality_t sig_quality; result = DRX_Ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); @@ -122,7 +122,7 @@ static int drx39xxj_read_signal_strength(struct dvb_frontend *fe, { struct drx39xxj_state *state = fe->demodulator_priv; DRXDemodInstance_t *demod = state->demod; - DRXStatus_t result; + int result; DRXSigQuality_t sig_quality; result = DRX_Ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); @@ -141,7 +141,7 @@ static int drx39xxj_read_snr(struct dvb_frontend *fe, u16 *snr) { struct drx39xxj_state *state = fe->demodulator_priv; DRXDemodInstance_t *demod = state->demod; - DRXStatus_t result; + int result; DRXSigQuality_t sig_quality; result = DRX_Ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); @@ -159,7 +159,7 @@ static int drx39xxj_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) { struct drx39xxj_state *state = fe->demodulator_priv; DRXDemodInstance_t *demod = state->demod; - DRXStatus_t result; + int result; DRXSigQuality_t sig_quality; result = DRX_Ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); @@ -181,9 +181,9 @@ static int drx39xxj_set_frontend(struct dvb_frontend *fe) struct dtv_frontend_properties *p = &fe->dtv_property_cache; struct drx39xxj_state *state = fe->demodulator_priv; DRXDemodInstance_t *demod = state->demod; - DRXStandard_t standard = DRX_STANDARD_8VSB; + enum drx_standard standard = DRX_STANDARD_8VSB; DRXChannel_t channel; - DRXStatus_t result; + int result; DRXUIOData_t uioData; DRXChannel_t defChannel = { /* frequency */ 0, /* bandwidth */ DRX_BANDWIDTH_6MHZ, @@ -270,7 +270,7 @@ static int drx39xxj_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) struct drx39xxj_state *state = fe->demodulator_priv; DRXDemodInstance_t *demod = state->demod; bool i2c_gate_state; - DRXStatus_t result; + int result; #ifdef DJH_DEBUG printk(KERN_DBG "i2c gate call: enable=%d state=%d\n", enable, @@ -331,7 +331,7 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) DRXDemodInstance_t *demod = NULL; DRXUIOCfg_t uioCfg; DRXUIOData_t uioData; - DRXStatus_t result; + int result; /* allocate memory for the internal state */ state = kmalloc(sizeof(struct drx39xxj_state), GFP_KERNEL); diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h index 467b390..1f0b30b 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h @@ -29,7 +29,7 @@ struct drx39xxj_state { struct i2c_adapter *i2c; DRXDemodInstance_t *demod; - DRXStandard_t current_standard; + enum drx_standard current_standard; struct dvb_frontend frontend; int powered_up:1; unsigned int i2c_gate_open:1; diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c b/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c index 5471263..ff6e334 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c @@ -11,33 +11,33 @@ #include "drx39xxj.h" /* Dummy function to satisfy drxj.c */ -DRXStatus_t DRXBSP_TUNER_Open(pTUNERInstance_t tuner) +int DRXBSP_TUNER_Open(struct tuner_instance *tuner) { return DRX_STS_OK; } -DRXStatus_t DRXBSP_TUNER_Close(pTUNERInstance_t tuner) +int DRXBSP_TUNER_Close(struct tuner_instance *tuner) { return DRX_STS_OK; } -DRXStatus_t DRXBSP_TUNER_SetFrequency(pTUNERInstance_t tuner, - TUNERMode_t mode, +int DRXBSP_TUNER_SetFrequency(struct tuner_instance *tuner, + u32 mode, s32 centerFrequency) { return DRX_STS_OK; } -DRXStatus_t -DRXBSP_TUNER_GetFrequency(pTUNERInstance_t tuner, - TUNERMode_t mode, +int +DRXBSP_TUNER_GetFrequency(struct tuner_instance *tuner, + u32 mode, s32 *RFfrequency, s32 *IFfrequency) { return DRX_STS_OK; } -DRXStatus_t DRXBSP_HST_Sleep(u32 n) +int DRXBSP_HST_Sleep(u32 n) { msleep(n); return DRX_STS_OK; @@ -58,7 +58,7 @@ void *DRXBSP_HST_Memcpy(void *to, void *from, u32 n) return (memcpy(to, from, (size_t) n)); } -DRXStatus_t DRXBSP_I2C_WriteRead(struct i2c_device_addr *wDevAddr, +int DRXBSP_I2C_WriteRead(struct i2c_device_addr *wDevAddr, u16 wCount, u8 *wData, struct i2c_device_addr *rDevAddr, diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c index 9bea12e..479db94 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c @@ -55,61 +55,61 @@ /*============================================================================*/ /* Function prototypes */ -static DRXStatus_t DRXDAP_FASI_WriteBlock(struct i2c_device_addr *devAddr, /* address of I2C device */ +static int DRXDAP_FASI_WriteBlock(struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register/memory */ u16 datasize, /* size of data */ u8 *data, /* data to send */ DRXflags_t flags); /* special device flags */ -static DRXStatus_t DRXDAP_FASI_ReadBlock(struct i2c_device_addr *devAddr, /* address of I2C device */ +static int DRXDAP_FASI_ReadBlock(struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register/memory */ u16 datasize, /* size of data */ u8 *data, /* data to send */ DRXflags_t flags); /* special device flags */ -static DRXStatus_t DRXDAP_FASI_WriteReg8(struct i2c_device_addr *devAddr, /* address of I2C device */ +static int DRXDAP_FASI_WriteReg8(struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register */ u8 data, /* data to write */ DRXflags_t flags); /* special device flags */ -static DRXStatus_t DRXDAP_FASI_ReadReg8(struct i2c_device_addr *devAddr, /* address of I2C device */ +static int DRXDAP_FASI_ReadReg8(struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register */ u8 *data, /* buffer to receive data */ DRXflags_t flags); /* special device flags */ -static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg8(struct i2c_device_addr *devAddr, /* address of I2C device */ +static int DRXDAP_FASI_ReadModifyWriteReg8(struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t waddr, /* address of register */ DRXaddr_t raddr, /* address to read back from */ u8 datain, /* data to send */ u8 *dataout); /* data to receive back */ -static DRXStatus_t DRXDAP_FASI_WriteReg16(struct i2c_device_addr *devAddr, /* address of I2C device */ +static int DRXDAP_FASI_WriteReg16(struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register */ u16 data, /* data to write */ DRXflags_t flags); /* special device flags */ -static DRXStatus_t DRXDAP_FASI_ReadReg16(struct i2c_device_addr *devAddr, /* address of I2C device */ +static int DRXDAP_FASI_ReadReg16(struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register */ u16 *data, /* buffer to receive data */ DRXflags_t flags); /* special device flags */ -static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg16(struct i2c_device_addr *devAddr, /* address of I2C device */ +static int DRXDAP_FASI_ReadModifyWriteReg16(struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t waddr, /* address of register */ DRXaddr_t raddr, /* address to read back from */ u16 datain, /* data to send */ u16 *dataout); /* data to receive back */ -static DRXStatus_t DRXDAP_FASI_WriteReg32(struct i2c_device_addr *devAddr, /* address of I2C device */ +static int DRXDAP_FASI_WriteReg32(struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register */ u32 data, /* data to write */ DRXflags_t flags); /* special device flags */ -static DRXStatus_t DRXDAP_FASI_ReadReg32(struct i2c_device_addr *devAddr, /* address of I2C device */ +static int DRXDAP_FASI_ReadReg32(struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register */ u32 *data, /* buffer to receive data */ DRXflags_t flags); /* special device flags */ -static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg32(struct i2c_device_addr *devAddr, /* address of I2C device */ +static int DRXDAP_FASI_ReadModifyWriteReg32(struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t waddr, /* address of register */ DRXaddr_t raddr, /* address to read back from */ u32 datain, /* data to send */ @@ -149,7 +149,7 @@ DRXAccessFunc_t drxDapFASIFunct_g = { /* Functions not supported by protocol*/ -static DRXStatus_t DRXDAP_FASI_WriteReg8(struct i2c_device_addr *devAddr, /* address of I2C device */ +static int DRXDAP_FASI_WriteReg8(struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register */ u8 data, /* data to write */ DRXflags_t flags) @@ -157,7 +157,7 @@ static DRXStatus_t DRXDAP_FASI_WriteReg8(struct i2c_device_addr *devAddr, /* add return DRX_STS_ERROR; } -static DRXStatus_t DRXDAP_FASI_ReadReg8(struct i2c_device_addr *devAddr, /* address of I2C device */ +static int DRXDAP_FASI_ReadReg8(struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register */ u8 *data, /* buffer to receive data */ DRXflags_t flags) @@ -165,7 +165,7 @@ static DRXStatus_t DRXDAP_FASI_ReadReg8(struct i2c_device_addr *devAddr, /* addr return DRX_STS_ERROR; } -static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg8(struct i2c_device_addr *devAddr, /* address of I2C device */ +static int DRXDAP_FASI_ReadModifyWriteReg8(struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t waddr, /* address of register */ DRXaddr_t raddr, /* address to read back from */ u8 datain, /* data to send */ @@ -174,7 +174,7 @@ static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg8(struct i2c_device_addr *devAd return DRX_STS_ERROR; } -static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg32(struct i2c_device_addr *devAddr, /* address of I2C device */ +static int DRXDAP_FASI_ReadModifyWriteReg32(struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t waddr, /* address of register */ DRXaddr_t raddr, /* address to read back from */ u32 datain, /* data to send */ @@ -187,7 +187,7 @@ static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg32(struct i2c_device_addr *devA /****************************** * -* DRXStatus_t DRXDAP_FASI_ReadBlock ( +* int DRXDAP_FASI_ReadBlock ( * struct i2c_device_addr *devAddr, -- address of I2C device * DRXaddr_t addr, -- address of chip register/memory * u16 datasize, -- number of bytes to read @@ -210,14 +210,14 @@ static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg32(struct i2c_device_addr *devA * ******************************/ -static DRXStatus_t DRXDAP_FASI_ReadBlock(struct i2c_device_addr *devAddr, +static int DRXDAP_FASI_ReadBlock(struct i2c_device_addr *devAddr, DRXaddr_t addr, u16 datasize, u8 *data, DRXflags_t flags) { u8 buf[4]; u16 bufx; - DRXStatus_t rc; + int rc; u16 overheadSize = 0; /* Check parameters ******************************************************* */ @@ -302,7 +302,7 @@ static DRXStatus_t DRXDAP_FASI_ReadBlock(struct i2c_device_addr *devAddr, /****************************** * -* DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg16 ( +* int DRXDAP_FASI_ReadModifyWriteReg16 ( * struct i2c_device_addr *devAddr, -- address of I2C device * DRXaddr_t waddr, -- address of chip register/memory * DRXaddr_t raddr, -- chip address to read back from @@ -325,12 +325,12 @@ static DRXStatus_t DRXDAP_FASI_ReadBlock(struct i2c_device_addr *devAddr, * ******************************/ -static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg16(struct i2c_device_addr *devAddr, +static int DRXDAP_FASI_ReadModifyWriteReg16(struct i2c_device_addr *devAddr, DRXaddr_t waddr, DRXaddr_t raddr, u16 wdata, u16 *rdata) { - DRXStatus_t rc = DRX_STS_ERROR; + int rc = DRX_STS_ERROR; #if ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 ) if (rdata == NULL) { @@ -348,7 +348,7 @@ static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg16(struct i2c_device_addr *devA /****************************** * -* DRXStatus_t DRXDAP_FASI_ReadReg16 ( +* int DRXDAP_FASI_ReadReg16 ( * struct i2c_device_addr *devAddr, -- address of I2C device * DRXaddr_t addr, -- address of chip register/memory * u16 *data, -- data to receive @@ -364,12 +364,12 @@ static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg16(struct i2c_device_addr *devA * ******************************/ -static DRXStatus_t DRXDAP_FASI_ReadReg16(struct i2c_device_addr *devAddr, +static int DRXDAP_FASI_ReadReg16(struct i2c_device_addr *devAddr, DRXaddr_t addr, u16 *data, DRXflags_t flags) { u8 buf[sizeof(*data)]; - DRXStatus_t rc; + int rc; if (!data) { return DRX_STS_INVALID_ARG; @@ -381,7 +381,7 @@ static DRXStatus_t DRXDAP_FASI_ReadReg16(struct i2c_device_addr *devAddr, /****************************** * -* DRXStatus_t DRXDAP_FASI_ReadReg32 ( +* int DRXDAP_FASI_ReadReg32 ( * struct i2c_device_addr *devAddr, -- address of I2C device * DRXaddr_t addr, -- address of chip register/memory * u32 *data, -- data to receive @@ -397,12 +397,12 @@ static DRXStatus_t DRXDAP_FASI_ReadReg16(struct i2c_device_addr *devAddr, * ******************************/ -static DRXStatus_t DRXDAP_FASI_ReadReg32(struct i2c_device_addr *devAddr, +static int DRXDAP_FASI_ReadReg32(struct i2c_device_addr *devAddr, DRXaddr_t addr, u32 *data, DRXflags_t flags) { u8 buf[sizeof(*data)]; - DRXStatus_t rc; + int rc; if (!data) { return DRX_STS_INVALID_ARG; @@ -416,7 +416,7 @@ static DRXStatus_t DRXDAP_FASI_ReadReg32(struct i2c_device_addr *devAddr, /****************************** * -* DRXStatus_t DRXDAP_FASI_WriteBlock ( +* int DRXDAP_FASI_WriteBlock ( * struct i2c_device_addr *devAddr, -- address of I2C device * DRXaddr_t addr, -- address of chip register/memory * u16 datasize, -- number of bytes to read @@ -436,14 +436,14 @@ static DRXStatus_t DRXDAP_FASI_ReadReg32(struct i2c_device_addr *devAddr, * ******************************/ -static DRXStatus_t DRXDAP_FASI_WriteBlock(struct i2c_device_addr *devAddr, +static int DRXDAP_FASI_WriteBlock(struct i2c_device_addr *devAddr, DRXaddr_t addr, u16 datasize, u8 *data, DRXflags_t flags) { u8 buf[DRXDAP_MAX_WCHUNKSIZE]; - DRXStatus_t st = DRX_STS_ERROR; - DRXStatus_t firstErr = DRX_STS_OK; + int st = DRX_STS_ERROR; + int firstErr = DRX_STS_OK; u16 overheadSize = 0; u16 blockSize = 0; @@ -560,7 +560,7 @@ static DRXStatus_t DRXDAP_FASI_WriteBlock(struct i2c_device_addr *devAddr, /****************************** * -* DRXStatus_t DRXDAP_FASI_WriteReg16 ( +* int DRXDAP_FASI_WriteReg16 ( * struct i2c_device_addr *devAddr, -- address of I2C device * DRXaddr_t addr, -- address of chip register/memory * u16 data, -- data to send @@ -575,7 +575,7 @@ static DRXStatus_t DRXDAP_FASI_WriteBlock(struct i2c_device_addr *devAddr, * ******************************/ -static DRXStatus_t DRXDAP_FASI_WriteReg16(struct i2c_device_addr *devAddr, +static int DRXDAP_FASI_WriteReg16(struct i2c_device_addr *devAddr, DRXaddr_t addr, u16 data, DRXflags_t flags) { @@ -589,7 +589,7 @@ static DRXStatus_t DRXDAP_FASI_WriteReg16(struct i2c_device_addr *devAddr, /****************************** * -* DRXStatus_t DRXDAP_FASI_WriteReg32 ( +* int DRXDAP_FASI_WriteReg32 ( * struct i2c_device_addr *devAddr, -- address of I2C device * DRXaddr_t addr, -- address of chip register/memory * u32 data, -- data to send @@ -604,7 +604,7 @@ static DRXStatus_t DRXDAP_FASI_WriteReg16(struct i2c_device_addr *devAddr, * ******************************/ -static DRXStatus_t DRXDAP_FASI_WriteReg32(struct i2c_device_addr *devAddr, +static int DRXDAP_FASI_WriteReg32(struct i2c_device_addr *devAddr, DRXaddr_t addr, u32 data, DRXflags_t flags) { diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c index 19aa546..d33f9ce 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c @@ -145,7 +145,7 @@ FUNCTIONS #ifndef DRX_EXCLUDE_SCAN /* Prototype of default scanning function */ -static DRXStatus_t +static int ScanFunctionDefault(void *scanContext, DRXScanCommand_t scanCommand, pDRXChannel_t scanChannel, bool * getNextChannel); @@ -197,7 +197,7 @@ void *GetScanContext(pDRXDemodInstance_t demod, void *scanContext) * \brief Wait for lock while scanning. * \param demod: Pointer to demodulator instance. * \param lockStat: Pointer to bool indicating if end result is lock or not. -* \return DRXStatus_t. +* \return int. * \retval DRX_STS_OK: Success * \retval DRX_STS_ERROR: I2C failure or bsp function failure. * @@ -211,7 +211,7 @@ void *GetScanContext(pDRXDemodInstance_t demod, void *scanContext) * In case DRX_NEVER_LOCK is returned the poll-wait will be aborted. * */ -static DRXStatus_t ScanWaitForLock(pDRXDemodInstance_t demod, bool * isLocked) +static int ScanWaitForLock(pDRXDemodInstance_t demod, bool * isLocked) { bool doneWaiting = false; DRXLockStatus_t lockState = DRX_NOT_LOCKED; @@ -263,7 +263,7 @@ static DRXStatus_t ScanWaitForLock(pDRXDemodInstance_t demod, bool * isLocked) * \brief Determine next frequency to scan. * \param demod: Pointer to demodulator instance. * \param skip : Minimum frequency step to take. -* \return DRXStatus_t. +* \return int. * \retval DRX_STS_OK: Succes. * \retval DRX_STS_INVALID_ARG: Invalid frequency plan. * @@ -272,7 +272,7 @@ static DRXStatus_t ScanWaitForLock(pDRXDemodInstance_t demod, bool * isLocked) * Check if scan is ready. * */ -static DRXStatus_t +static int ScanPrepareNextScan(pDRXDemodInstance_t demod, s32 skip) { pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); @@ -345,7 +345,7 @@ ScanPrepareNextScan(pDRXDemodInstance_t demod, s32 skip) * \param scanChannel: Channel to check: frequency and bandwidth, others AUTO * \param getNextChannel: Return true if next frequency is desired at next call * -* \return DRXStatus_t. +* \return int. * \retval DRX_STS_OK: Channel found, DRX_CTRL_GET_CHANNEL can be used * to retrieve channel parameters. * \retval DRX_STS_BUSY: Channel not found (yet). @@ -353,13 +353,13 @@ ScanPrepareNextScan(pDRXDemodInstance_t demod, s32 skip) * * scanChannel and getNextChannel will be NULL for INIT and STOP. */ -static DRXStatus_t +static int ScanFunctionDefault(void *scanContext, DRXScanCommand_t scanCommand, pDRXChannel_t scanChannel, bool * getNextChannel) { pDRXDemodInstance_t demod = NULL; - DRXStatus_t status = DRX_STS_ERROR; + int status = DRX_STS_ERROR; bool isLocked = false; demod = (pDRXDemodInstance_t) scanContext; @@ -398,7 +398,7 @@ ScanFunctionDefault(void *scanContext, * \brief Initialize for channel scan. * \param demod: Pointer to demodulator instance. * \param scanParam: Pointer to scan parameters. -* \return DRXStatus_t. +* \return int. * \retval DRX_STS_OK: Initialized for scan. * \retval DRX_STS_ERROR: No overlap between frequency plan and tuner * range. @@ -411,10 +411,10 @@ ScanFunctionDefault(void *scanContext, * center frequency of the frequency plan that is within the tuner range. * */ -static DRXStatus_t +static int CtrlScanInit(pDRXDemodInstance_t demod, pDRXScanParam_t scanParam) { - DRXStatus_t status = DRX_STS_ERROR; + int status = DRX_STS_ERROR; pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); s32 maxTunerFreq = 0; s32 minTunerFreq = 0; @@ -546,14 +546,14 @@ CtrlScanInit(pDRXDemodInstance_t demod, pDRXScanParam_t scanParam) /** * \brief Stop scanning. * \param demod: Pointer to demodulator instance. -* \return DRXStatus_t. +* \return int. * \retval DRX_STS_OK: Scan stopped. * \retval DRX_STS_ERROR: Something went wrong. * \retval DRX_STS_INVALID_ARG: Wrong parameters. */ -static DRXStatus_t CtrlScanStop(pDRXDemodInstance_t demod) +static int CtrlScanStop(pDRXDemodInstance_t demod) { - DRXStatus_t status = DRX_STS_ERROR; + int status = DRX_STS_ERROR; pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); void *scanContext = NULL; @@ -587,7 +587,7 @@ static DRXStatus_t CtrlScanStop(pDRXDemodInstance_t demod) * \brief Scan for next channel. * \param demod: Pointer to demodulator instance. * \param scanProgress: Pointer to scan progress. -* \return DRXStatus_t. +* \return int. * \retval DRX_STS_OK: Channel found, DRX_CTRL_GET_CHANNEL can be used * to retrieve channel parameters. * \retval DRX_STS_BUSY: Tried part of the channels, as specified in @@ -601,7 +601,7 @@ static DRXStatus_t CtrlScanStop(pDRXDemodInstance_t demod) * Progress indication will run from 0 upto DRX_SCAN_MAX_PROGRESS during scan. * */ -static DRXStatus_t CtrlScanNext(pDRXDemodInstance_t demod, u16 *scanProgress) +static int CtrlScanNext(pDRXDemodInstance_t demod, u16 *scanProgress) { pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); bool * scanReady = (bool *) (NULL); @@ -636,7 +636,7 @@ static DRXStatus_t CtrlScanNext(pDRXDemodInstance_t demod, u16 *scanProgress) for (i = 0; ((i < numTries) && ((*scanReady) == false)); i++) { DRXChannel_t scanChannel = { 0 }; - DRXStatus_t status = DRX_STS_ERROR; + int status = DRX_STS_ERROR; pDRXFrequencyPlan_t freqPlan = (pDRXFrequencyPlan_t) (NULL); bool nextChannel = false; void *scanContext = NULL; @@ -671,7 +671,7 @@ static DRXStatus_t CtrlScanNext(pDRXDemodInstance_t demod, u16 *scanProgress) /* Proceed to next channel if requested */ if (nextChannel == true) { - DRXStatus_t nextStatus = DRX_STS_ERROR; + int nextStatus = DRX_STS_ERROR; s32 skip = 0; if (status == DRX_STS_OK) { @@ -718,7 +718,7 @@ static DRXStatus_t CtrlScanNext(pDRXDemodInstance_t demod, u16 *scanProgress) * \brief Program tuner. * \param demod: Pointer to demodulator instance. * \param tunerChannel: Pointer to tuning parameters. -* \return DRXStatus_t. +* \return int. * \retval DRX_STS_OK: Tuner programmed successfully. * \retval DRX_STS_ERROR: Something went wrong. * \retval DRX_STS_INVALID_ARG: Wrong parameters. @@ -727,13 +727,13 @@ static DRXStatus_t CtrlScanNext(pDRXDemodInstance_t demod, u16 *scanProgress) * but also returns the actual RF and IF frequency from the tuner. * */ -static DRXStatus_t +static int CtrlProgramTuner(pDRXDemodInstance_t demod, pDRXChannel_t channel) { pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); - DRXStandard_t standard = DRX_STANDARD_UNKNOWN; - TUNERMode_t tunerMode = 0; - DRXStatus_t status = DRX_STS_ERROR; + enum drx_standard standard = DRX_STANDARD_UNKNOWN; + u32 tunerMode = 0; + int status = DRX_STS_ERROR; s32 ifFrequency = 0; bool tunerSlowMode = false; @@ -782,7 +782,7 @@ CtrlProgramTuner(pDRXDemodInstance_t demod, pDRXChannel_t channel) if (commonAttr->tunerPortNr == 1) { bool bridgeClosed = true; - DRXStatus_t statusBridge = DRX_STS_ERROR; + int statusBridge = DRX_STS_ERROR; statusBridge = DRX_Ctrl(demod, DRX_CTRL_I2C_BRIDGE, &bridgeClosed); @@ -797,7 +797,7 @@ CtrlProgramTuner(pDRXDemodInstance_t demod, pDRXChannel_t channel) /* attempt restoring bridge before checking status of SetFrequency */ if (commonAttr->tunerPortNr == 1) { bool bridgeClosed = false; - DRXStatus_t statusBridge = DRX_STS_ERROR; + int statusBridge = DRX_STS_ERROR; statusBridge = DRX_Ctrl(demod, DRX_CTRL_I2C_BRIDGE, &bridgeClosed); @@ -833,13 +833,13 @@ CtrlProgramTuner(pDRXDemodInstance_t demod, pDRXChannel_t channel) * \brief function to do a register dump. * \param demod: Pointer to demodulator instance. * \param registers: Registers to dump. -* \return DRXStatus_t. +* \return int. * \retval DRX_STS_OK: Dump executed successfully. * \retval DRX_STS_ERROR: Something went wrong. * \retval DRX_STS_INVALID_ARG: Wrong parameters. * */ -DRXStatus_t CtrlDumpRegisters(pDRXDemodInstance_t demod, +int CtrlDumpRegisters(pDRXDemodInstance_t demod, pDRXRegDump_t registers) { u16 i = 0; @@ -851,7 +851,7 @@ DRXStatus_t CtrlDumpRegisters(pDRXDemodInstance_t demod, /* start dumping registers */ while (registers[i].address != 0) { - DRXStatus_t status = DRX_STS_ERROR; + int status = DRX_STS_ERROR; u16 value = 0; u32 data = 0; @@ -968,7 +968,7 @@ static u16 UCodeComputeCRC(u8 *blockData, u16 nrWords) * \param devAddr: Address of device. * \param mcInfo: Pointer to information about microcode data. * \param action: Either UCODE_UPLOAD or UCODE_VERIFY -* \return DRXStatus_t. +* \return int. * \retval DRX_STS_OK: * - In case of UCODE_UPLOAD: code is successfully uploaded. * - In case of UCODE_VERIFY: image on device is equal to @@ -981,11 +981,11 @@ static u16 UCodeComputeCRC(u8 *blockData, u16 nrWords) * - Invalid arguments. * - Provided image is corrupt */ -static DRXStatus_t +static int CtrlUCode(pDRXDemodInstance_t demod, pDRXUCodeInfo_t mcInfo, DRXUCodeAction_t action) { - DRXStatus_t rc; + int rc; u16 i = 0; u16 mcNrOfBlks = 0; u16 mcMagicWord = 0; @@ -1197,11 +1197,11 @@ CtrlUCode(pDRXDemodInstance_t demod, * \brief Build list of version information. * \param demod: A pointer to a demodulator instance. * \param versionList: Pointer to linked list of versions. -* \return DRXStatus_t. +* \return int. * \retval DRX_STS_OK: Version information stored in versionList * \retval DRX_STS_INVALID_ARG: Invalid arguments. */ -static DRXStatus_t +static int CtrlVersion(pDRXDemodInstance_t demod, pDRXVersionList_t * versionList) { static char drxDriverCoreModuleName[] = "Core driver"; @@ -1212,7 +1212,7 @@ CtrlVersion(pDRXDemodInstance_t demod, pDRXVersionList_t * versionList) static DRXVersionList_t drxDriverCoreVersionList; pDRXVersionList_t demodVersionList = (pDRXVersionList_t) (NULL); - DRXStatus_t returnStatus = DRX_STS_ERROR; + int returnStatus = DRX_STS_ERROR; /* Check arguments */ if (versionList == NULL) { @@ -1264,14 +1264,14 @@ CtrlVersion(pDRXDemodInstance_t demod, pDRXVersionList_t * versionList) /** * \brief This function is obsolete. * \param demods: Don't care, parameter is ignored. -* \return DRXStatus_t Return status. +* \return int Return status. * \retval DRX_STS_OK: Initialization completed. * * This function is obsolete, prototype available for backward compatability. * */ -DRXStatus_t DRX_Init(pDRXDemodInstance_t demods[]) +int DRX_Init(pDRXDemodInstance_t demods[]) { return DRX_STS_OK; } @@ -1280,14 +1280,14 @@ DRXStatus_t DRX_Init(pDRXDemodInstance_t demods[]) /** * \brief This function is obsolete. -* \return DRXStatus_t Return status. +* \return int Return status. * \retval DRX_STS_OK: Terminated driver successful. * * This function is obsolete, prototype available for backward compatability. * */ -DRXStatus_t DRX_Term(void) +int DRX_Term(void) { return DRX_STS_OK; } @@ -1297,7 +1297,7 @@ DRXStatus_t DRX_Term(void) /** * \brief Open a demodulator instance. * \param demod: A pointer to a demodulator instance. -* \return DRXStatus_t Return status. +* \return int Return status. * \retval DRX_STS_OK: Opened demod instance with succes. * \retval DRX_STS_ERROR: Driver not initialized or unable to initialize * demod. @@ -1305,9 +1305,9 @@ DRXStatus_t DRX_Term(void) * */ -DRXStatus_t DRX_Open(pDRXDemodInstance_t demod) +int DRX_Open(pDRXDemodInstance_t demod) { - DRXStatus_t status = DRX_STS_OK; + int status = DRX_STS_OK; if ((demod == NULL) || (demod->myDemodFunct == NULL) || @@ -1332,7 +1332,7 @@ DRXStatus_t DRX_Open(pDRXDemodInstance_t demod) /** * \brief Close device. * \param demod: A pointer to a demodulator instance. -* \return DRXStatus_t Return status. +* \return int Return status. * \retval DRX_STS_OK: Closed demod instance with succes. * \retval DRX_STS_ERROR: Driver not initialized or error during close * demod. @@ -1342,9 +1342,9 @@ DRXStatus_t DRX_Open(pDRXDemodInstance_t demod) * Put device into sleep mode. */ -DRXStatus_t DRX_Close(pDRXDemodInstance_t demod) +int DRX_Close(pDRXDemodInstance_t demod) { - DRXStatus_t status = DRX_STS_OK; + int status = DRX_STS_OK; if ((demod == NULL) || (demod->myDemodFunct == NULL) || @@ -1369,7 +1369,7 @@ DRXStatus_t DRX_Close(pDRXDemodInstance_t demod) * \param demod: A pointer to a demodulator instance. * \param ctrl: Reference to desired control function. * \param ctrlData: Pointer to data structure for control function. -* \return DRXStatus_t Return status. +* \return int Return status. * \retval DRX_STS_OK: Control function completed successfully. * \retval DRX_STS_ERROR: Driver not initialized or error during * control demod. @@ -1382,10 +1382,10 @@ DRXStatus_t DRX_Close(pDRXDemodInstance_t demod) * */ -DRXStatus_t -DRX_Ctrl(pDRXDemodInstance_t demod, DRXCtrlIndex_t ctrl, void *ctrlData) +int +DRX_Ctrl(pDRXDemodInstance_t demod, u32 ctrl, void *ctrlData) { - DRXStatus_t status = DRX_STS_ERROR; + int status = DRX_STS_ERROR; if ((demod == NULL) || (demod->myDemodFunct == NULL) || diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h index 752b2b3..1e906b8 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h @@ -42,7 +42,7 @@ INCLUDES -------------------------------------------------------------------------*/ -typedef enum { +enum DRXStatus { DRX_STS_READY = 3, /**< device/service is ready */ DRX_STS_BUSY = 2, /**< device/service is busy */ DRX_STS_OK = 1, /**< everything is OK */ @@ -51,7 +51,7 @@ typedef enum { DRX_STS_ERROR = -2, /**< general error */ DRX_STS_FUNC_NOT_AVAILABLE = -3 /**< unavailable functionality */ -} DRXStatus_t, *pDRXStatus_t; +}; /* * This structure contains the I2C address, the device ID and a userData pointer. @@ -81,23 +81,23 @@ Exported FUNCTIONS /** * \fn DRXBSP_I2C_Init() * \brief Initialize I2C communication module. -* \return DRXStatus_t Return status. +* \return int Return status. * \retval DRX_STS_OK Initialization successful. * \retval DRX_STS_ERROR Initialization failed. */ -DRXStatus_t DRXBSP_I2C_Init(void); +int DRXBSP_I2C_Init(void); /** * \fn DRXBSP_I2C_Term() * \brief Terminate I2C communication module. -* \return DRXStatus_t Return status. +* \return int Return status. * \retval DRX_STS_OK Termination successful. * \retval DRX_STS_ERROR Termination failed. */ -DRXStatus_t DRXBSP_I2C_Term(void); +int DRXBSP_I2C_Term(void); /** -* \fn DRXStatus_t DRXBSP_I2C_WriteRead( struct i2c_device_addr *wDevAddr, +* \fn int DRXBSP_I2C_WriteRead( struct i2c_device_addr *wDevAddr, * u16 wCount, * u8 * wData, * struct i2c_device_addr *rDevAddr, @@ -110,7 +110,7 @@ DRXStatus_t DRXBSP_I2C_Term(void); * \param rDevAddr The device i2c address and the device ID to read from * \param rCount The number of bytes to read * \param rData The array to read the data from -* \return DRXStatus_t Return status. +* \return int Return status. * \retval DRX_STS_OK Succes. * \retval DRX_STS_ERROR Failure. * \retval DRX_STS_INVALID_ARG Parameter 'wcount' is not zero but parameter @@ -126,7 +126,7 @@ DRXStatus_t DRXBSP_I2C_Term(void); * The device ID can be useful if several devices share an I2C address. * It can be used to control a "switch" on the I2C bus to the correct device. */ -DRXStatus_t DRXBSP_I2C_WriteRead(struct i2c_device_addr *wDevAddr, +int DRXBSP_I2C_WriteRead(struct i2c_device_addr *wDevAddr, u16 wCount, u8 * wData, struct i2c_device_addr *rDevAddr, @@ -170,26 +170,19 @@ extern int DRX_I2C_Error_g; TUNER_MODE_SUB4 | TUNER_MODE_SUB5 | \ TUNER_MODE_SUB6 | TUNER_MODE_SUB7 ) -typedef u32 TUNERMode_t; -typedef u32 * pTUNERMode_t; - -typedef char *TUNERSubMode_t; /* description of submode */ -typedef TUNERSubMode_t *pTUNERSubMode_t; - -typedef enum { +enum tuner_lock_status { TUNER_LOCKED, TUNER_NOT_LOCKED -} TUNERLockStatus_t, *pTUNERLockStatus_t; - -typedef struct { +}; +struct tuner_common { char *name; /* Tuner brand & type name */ s32 minFreqRF; /* Lowest RF input frequency, in kHz */ s32 maxFreqRF; /* Highest RF input frequency, in kHz */ u8 subMode; /* Index to sub-mode in use */ - pTUNERSubMode_t subModeDescriptions; /* Pointer to description of sub-modes */ + char *** subModeDescriptions; /* Pointer to description of sub-modes */ u8 subModes; /* Number of available sub-modes */ /* The following fields will be either 0, NULL or false and do not need @@ -201,31 +194,30 @@ typedef struct { void *myUserData; /* pointer to associated demod instance */ u16 myCapabilities; /* value for storing application flags */ +}; -} TUNERCommonAttr_t, *pTUNERCommonAttr_t; - -typedef struct TUNERInstance_s *pTUNERInstance_t; +struct tuner_instance; -typedef DRXStatus_t(*TUNEROpenFunc_t) (pTUNERInstance_t tuner); -typedef DRXStatus_t(*TUNERCloseFunc_t) (pTUNERInstance_t tuner); +typedef int(*TUNEROpenFunc_t) (struct tuner_instance *tuner); +typedef int(*TUNERCloseFunc_t) (struct tuner_instance *tuner); -typedef DRXStatus_t(*TUNERSetFrequencyFunc_t) (pTUNERInstance_t tuner, - TUNERMode_t mode, +typedef int(*TUNERSetFrequencyFunc_t) (struct tuner_instance *tuner, + u32 mode, s32 frequency); -typedef DRXStatus_t(*TUNERGetFrequencyFunc_t) (pTUNERInstance_t tuner, - TUNERMode_t mode, +typedef int(*TUNERGetFrequencyFunc_t) (struct tuner_instance *tuner, + u32 mode, s32 * RFfrequency, s32 * IFfrequency); -typedef DRXStatus_t(*TUNERLockStatusFunc_t) (pTUNERInstance_t tuner, - pTUNERLockStatus_t +typedef int(*TUNERLockStatusFunc_t) (struct tuner_instance *tuner, + enum tuner_lock_status * lockStat); -typedef DRXStatus_t(*TUNERi2cWriteReadFunc_t) (pTUNERInstance_t tuner, +typedef int(*TUNERi2cWriteReadFunc_t) (struct tuner_instance *tuner, struct i2c_device_addr * wDevAddr, u16 wCount, u8 * wData, @@ -233,7 +225,7 @@ typedef DRXStatus_t(*TUNERi2cWriteReadFunc_t) (pTUNERInstance_t tuner, rDevAddr, u16 rCount, u8 * rData); -typedef struct { +struct tuner_ops { TUNEROpenFunc_t openFunc; TUNERCloseFunc_t closeFunc; TUNERSetFrequencyFunc_t setFrequencyFunc; @@ -241,43 +233,42 @@ typedef struct { TUNERLockStatusFunc_t lockStatusFunc; TUNERi2cWriteReadFunc_t i2cWriteReadFunc; -} TUNERFunc_t, *pTUNERFunc_t; - -typedef struct TUNERInstance_s { +}; +struct tuner_instance { struct i2c_device_addr myI2CDevAddr; - pTUNERCommonAttr_t myCommonAttr; + struct tuner_common * myCommonAttr; void *myExtAttr; - pTUNERFunc_t myFunct; + struct tuner_ops * myFunct; +}; -} TUNERInstance_t; -DRXStatus_t DRXBSP_TUNER_Open(pTUNERInstance_t tuner); +int DRXBSP_TUNER_Open(struct tuner_instance *tuner); -DRXStatus_t DRXBSP_TUNER_Close(pTUNERInstance_t tuner); +int DRXBSP_TUNER_Close(struct tuner_instance *tuner); -DRXStatus_t DRXBSP_TUNER_SetFrequency(pTUNERInstance_t tuner, - TUNERMode_t mode, +int DRXBSP_TUNER_SetFrequency(struct tuner_instance *tuner, + u32 mode, s32 frequency); -DRXStatus_t DRXBSP_TUNER_GetFrequency(pTUNERInstance_t tuner, - TUNERMode_t mode, +int DRXBSP_TUNER_GetFrequency(struct tuner_instance *tuner, + u32 mode, s32 * RFfrequency, s32 * IFfrequency); -DRXStatus_t DRXBSP_TUNER_LockStatus(pTUNERInstance_t tuner, - pTUNERLockStatus_t lockStat); +int DRXBSP_TUNER_LockStatus(struct tuner_instance *tuner, + enum tuner_lock_status * lockStat); -DRXStatus_t DRXBSP_TUNER_DefaultI2CWriteRead(pTUNERInstance_t tuner, +int DRXBSP_TUNER_DefaultI2CWriteRead(struct tuner_instance *tuner, struct i2c_device_addr *wDevAddr, u16 wCount, u8 * wData, struct i2c_device_addr *rDevAddr, u16 rCount, u8 * rData); -DRXStatus_t DRXBSP_HST_Init(void); +int DRXBSP_HST_Init(void); -DRXStatus_t DRXBSP_HST_Term(void); +int DRXBSP_HST_Term(void); void *DRXBSP_HST_Memcpy(void *to, void *from, u32 n); @@ -285,19 +276,9 @@ int DRXBSP_HST_Memcmp(void *s1, void *s2, u32 n); u32 DRXBSP_HST_Clock(void); -DRXStatus_t DRXBSP_HST_Sleep(u32 n); +int DRXBSP_HST_Sleep(u32 n); -#ifdef __cplusplus -extern "C" { -#endif -/*------------------------------------------------------------------------- -TYPEDEFS --------------------------------------------------------------------------*/ - -/*------------------------------------------------------------------------- -DEFINES --------------------------------------------------------------------------*/ /************** * @@ -535,132 +516,132 @@ ENUM -------------------------------------------------------------------------*/ /** -* \enum DRXStandard_t +* \enum enum drx_standard * \brief Modulation standards. */ - typedef enum { - DRX_STANDARD_DVBT = 0, /**< Terrestrial DVB-T. */ - DRX_STANDARD_8VSB, /**< Terrestrial 8VSB. */ - DRX_STANDARD_NTSC, /**< Terrestrial\Cable analog NTSC. */ - DRX_STANDARD_PAL_SECAM_BG, - /**< Terrestrial analog PAL/SECAM B/G */ - DRX_STANDARD_PAL_SECAM_DK, - /**< Terrestrial analog PAL/SECAM D/K */ - DRX_STANDARD_PAL_SECAM_I, - /**< Terrestrial analog PAL/SECAM I */ - DRX_STANDARD_PAL_SECAM_L, - /**< Terrestrial analog PAL/SECAM L - with negative modulation */ - DRX_STANDARD_PAL_SECAM_LP, - /**< Terrestrial analog PAL/SECAM L - with positive modulation */ - DRX_STANDARD_ITU_A, /**< Cable ITU ANNEX A. */ - DRX_STANDARD_ITU_B, /**< Cable ITU ANNEX B. */ - DRX_STANDARD_ITU_C, /**< Cable ITU ANNEX C. */ - DRX_STANDARD_ITU_D, /**< Cable ITU ANNEX D. */ - DRX_STANDARD_FM, /**< Terrestrial\Cable FM radio */ - DRX_STANDARD_DTMB, /**< Terrestrial DTMB standard (China)*/ - DRX_STANDARD_UNKNOWN = DRX_UNKNOWN, - /**< Standard unknown. */ - DRX_STANDARD_AUTO = DRX_AUTO - /**< Autodetect standard. */ - } DRXStandard_t, *pDRXStandard_t; - -/** -* \enum DRXStandard_t +enum drx_standard { + DRX_STANDARD_DVBT = 0, /**< Terrestrial DVB-T. */ + DRX_STANDARD_8VSB, /**< Terrestrial 8VSB. */ + DRX_STANDARD_NTSC, /**< Terrestrial\Cable analog NTSC. */ + DRX_STANDARD_PAL_SECAM_BG, + /**< Terrestrial analog PAL/SECAM B/G */ + DRX_STANDARD_PAL_SECAM_DK, + /**< Terrestrial analog PAL/SECAM D/K */ + DRX_STANDARD_PAL_SECAM_I, + /**< Terrestrial analog PAL/SECAM I */ + DRX_STANDARD_PAL_SECAM_L, + /**< Terrestrial analog PAL/SECAM L + with negative modulation */ + DRX_STANDARD_PAL_SECAM_LP, + /**< Terrestrial analog PAL/SECAM L + with positive modulation */ + DRX_STANDARD_ITU_A, /**< Cable ITU ANNEX A. */ + DRX_STANDARD_ITU_B, /**< Cable ITU ANNEX B. */ + DRX_STANDARD_ITU_C, /**< Cable ITU ANNEX C. */ + DRX_STANDARD_ITU_D, /**< Cable ITU ANNEX D. */ + DRX_STANDARD_FM, /**< Terrestrial\Cable FM radio */ + DRX_STANDARD_DTMB, /**< Terrestrial DTMB standard (China)*/ + DRX_STANDARD_UNKNOWN = DRX_UNKNOWN, + /**< Standard unknown. */ + DRX_STANDARD_AUTO = DRX_AUTO + /**< Autodetect standard. */ +}; + +/** +* \enum enum drx_standard * \brief Modulation sub-standards. */ - typedef enum { - DRX_SUBSTANDARD_MAIN = 0, /**< Main subvariant of standard */ - DRX_SUBSTANDARD_ATV_BG_SCANDINAVIA, - DRX_SUBSTANDARD_ATV_DK_POLAND, - DRX_SUBSTANDARD_ATV_DK_CHINA, - DRX_SUBSTANDARD_UNKNOWN = DRX_UNKNOWN, - /**< Sub-standard unknown. */ - DRX_SUBSTANDARD_AUTO = DRX_AUTO - /**< Auto (default) sub-standard */ - } DRXSubstandard_t, *pDRXSubstandard_t; - -/** -* \enum DRXBandwidth_t +enum drx_substandard { + DRX_SUBSTANDARD_MAIN = 0, /**< Main subvariant of standard */ + DRX_SUBSTANDARD_ATV_BG_SCANDINAVIA, + DRX_SUBSTANDARD_ATV_DK_POLAND, + DRX_SUBSTANDARD_ATV_DK_CHINA, + DRX_SUBSTANDARD_UNKNOWN = DRX_UNKNOWN, + /**< Sub-standard unknown. */ + DRX_SUBSTANDARD_AUTO = DRX_AUTO + /**< Auto (default) sub-standard */ +}; + +/** +* \enum enum drx_bandwidth * \brief Channel bandwidth or channel spacing. */ - typedef enum { - DRX_BANDWIDTH_8MHZ = 0, /**< Bandwidth 8 MHz. */ - DRX_BANDWIDTH_7MHZ, /**< Bandwidth 7 MHz. */ - DRX_BANDWIDTH_6MHZ, /**< Bandwidth 6 MHz. */ - DRX_BANDWIDTH_UNKNOWN = DRX_UNKNOWN, - /**< Bandwidth unknown. */ - DRX_BANDWIDTH_AUTO = DRX_AUTO - /**< Auto Set Bandwidth */ - } DRXBandwidth_t, *pDRXBandwidth_t; +enum drx_bandwidth { + DRX_BANDWIDTH_8MHZ = 0, /**< Bandwidth 8 MHz. */ + DRX_BANDWIDTH_7MHZ, /**< Bandwidth 7 MHz. */ + DRX_BANDWIDTH_6MHZ, /**< Bandwidth 6 MHz. */ + DRX_BANDWIDTH_UNKNOWN = DRX_UNKNOWN, + /**< Bandwidth unknown. */ + DRX_BANDWIDTH_AUTO = DRX_AUTO + /**< Auto Set Bandwidth */ +}; /** -* \enum DRXMirror_t +* \enum enum drx_mirror * \brief Indicate if channel spectrum is mirrored or not. */ - typedef enum { - DRX_MIRROR_NO = 0, /**< Spectrum is not mirrored. */ - DRX_MIRROR_YES, /**< Spectrum is mirrored. */ - DRX_MIRROR_UNKNOWN = DRX_UNKNOWN, - /**< Unknown if spectrum is mirrored. */ - DRX_MIRROR_AUTO = DRX_AUTO - /**< Autodetect if spectrum is mirrored. */ - } DRXMirror_t, *pDRXMirror_t; +enum drx_mirror{ + DRX_MIRROR_NO = 0, /**< Spectrum is not mirrored. */ + DRX_MIRROR_YES, /**< Spectrum is mirrored. */ + DRX_MIRROR_UNKNOWN = DRX_UNKNOWN, + /**< Unknown if spectrum is mirrored. */ + DRX_MIRROR_AUTO = DRX_AUTO + /**< Autodetect if spectrum is mirrored. */ +}; /** -* \enum DRXConstellation_t +* \enum enum drx_modulation * \brief Constellation type of the channel. */ - typedef enum { - DRX_CONSTELLATION_BPSK = 0, /**< Modulation is BPSK. */ - DRX_CONSTELLATION_QPSK, /**< Constellation is QPSK. */ - DRX_CONSTELLATION_PSK8, /**< Constellation is PSK8. */ - DRX_CONSTELLATION_QAM16, /**< Constellation is QAM16. */ - DRX_CONSTELLATION_QAM32, /**< Constellation is QAM32. */ - DRX_CONSTELLATION_QAM64, /**< Constellation is QAM64. */ - DRX_CONSTELLATION_QAM128, /**< Constellation is QAM128. */ - DRX_CONSTELLATION_QAM256, /**< Constellation is QAM256. */ - DRX_CONSTELLATION_QAM512, /**< Constellation is QAM512. */ - DRX_CONSTELLATION_QAM1024, /**< Constellation is QAM1024. */ - DRX_CONSTELLATION_QPSK_NR, /**< Constellation is QPSK_NR */ - DRX_CONSTELLATION_UNKNOWN = DRX_UNKNOWN, - /**< Constellation unknown. */ - DRX_CONSTELLATION_AUTO = DRX_AUTO - /**< Autodetect constellation. */ - } DRXConstellation_t, *pDRXConstellation_t; - -/** -* \enum DRXHierarchy_t +enum drx_modulation { + DRX_CONSTELLATION_BPSK = 0, /**< Modulation is BPSK. */ + DRX_CONSTELLATION_QPSK, /**< Constellation is QPSK. */ + DRX_CONSTELLATION_PSK8, /**< Constellation is PSK8. */ + DRX_CONSTELLATION_QAM16, /**< Constellation is QAM16. */ + DRX_CONSTELLATION_QAM32, /**< Constellation is QAM32. */ + DRX_CONSTELLATION_QAM64, /**< Constellation is QAM64. */ + DRX_CONSTELLATION_QAM128, /**< Constellation is QAM128. */ + DRX_CONSTELLATION_QAM256, /**< Constellation is QAM256. */ + DRX_CONSTELLATION_QAM512, /**< Constellation is QAM512. */ + DRX_CONSTELLATION_QAM1024, /**< Constellation is QAM1024. */ + DRX_CONSTELLATION_QPSK_NR, /**< Constellation is QPSK_NR */ + DRX_CONSTELLATION_UNKNOWN = DRX_UNKNOWN, + /**< Constellation unknown. */ + DRX_CONSTELLATION_AUTO = DRX_AUTO + /**< Autodetect constellation. */ +}; + +/** +* \enum enum drx_hierarchy * \brief Hierarchy of the channel. */ - typedef enum { - DRX_HIERARCHY_NONE = 0, /**< None hierarchical channel. */ - DRX_HIERARCHY_ALPHA1, /**< Hierarchical channel, alpha=1. */ - DRX_HIERARCHY_ALPHA2, /**< Hierarchical channel, alpha=2. */ - DRX_HIERARCHY_ALPHA4, /**< Hierarchical channel, alpha=4. */ - DRX_HIERARCHY_UNKNOWN = DRX_UNKNOWN, - /**< Hierarchy unknown. */ - DRX_HIERARCHY_AUTO = DRX_AUTO - /**< Autodetect hierarchy. */ - } DRXHierarchy_t, *pDRXHierarchy_t; - -/** -* \enum DRXPriority_t +enum drx_hierarchy { + DRX_HIERARCHY_NONE = 0, /**< None hierarchical channel. */ + DRX_HIERARCHY_ALPHA1, /**< Hierarchical channel, alpha=1. */ + DRX_HIERARCHY_ALPHA2, /**< Hierarchical channel, alpha=2. */ + DRX_HIERARCHY_ALPHA4, /**< Hierarchical channel, alpha=4. */ + DRX_HIERARCHY_UNKNOWN = DRX_UNKNOWN, + /**< Hierarchy unknown. */ + DRX_HIERARCHY_AUTO = DRX_AUTO + /**< Autodetect hierarchy. */ +}; + +/** +* \enum enum drx_priority * \brief Channel priority in case of hierarchical transmission. */ - typedef enum { - DRX_PRIORITY_LOW = 0, /**< Low priority channel. */ - DRX_PRIORITY_HIGH, /**< High priority channel. */ - DRX_PRIORITY_UNKNOWN = DRX_UNKNOWN - /**< Priority unknown. */ - } DRXPriority_t, *pDRXPriority_t; +enum drx_priority { + DRX_PRIORITY_LOW = 0, /**< Low priority channel. */ + DRX_PRIORITY_HIGH, /**< High priority channel. */ + DRX_PRIORITY_UNKNOWN = DRX_UNKNOWN + /**< Priority unknown. */ +}; /** -* \enum DRXCoderate_t +* \enum enum drx_coderate * \brief Channel priority in case of hierarchical transmission. */ - typedef enum { +enum drx_coderate{ DRX_CODERATE_1DIV2 = 0, /**< Code rate 1/2nd. */ DRX_CODERATE_2DIV3, /**< Code rate 2/3nd. */ DRX_CODERATE_3DIV4, /**< Code rate 3/4nd. */ @@ -670,164 +651,156 @@ ENUM /**< Code rate unknown. */ DRX_CODERATE_AUTO = DRX_AUTO /**< Autodetect code rate. */ - } DRXCoderate_t, *pDRXCoderate_t; +}; /** -* \enum DRXGuard_t +* \enum enum drx_guard * \brief Guard interval of a channel. */ - typedef enum { - DRX_GUARD_1DIV32 = 0, /**< Guard interval 1/32nd. */ - DRX_GUARD_1DIV16, /**< Guard interval 1/16th. */ - DRX_GUARD_1DIV8, /**< Guard interval 1/8th. */ - DRX_GUARD_1DIV4, /**< Guard interval 1/4th. */ - DRX_GUARD_UNKNOWN = DRX_UNKNOWN, - /**< Guard interval unknown. */ - DRX_GUARD_AUTO = DRX_AUTO - /**< Autodetect guard interval. */ - } DRXGuard_t, *pDRXGuard_t; - -/** -* \enum DRXFftmode_t +enum drx_guard { + DRX_GUARD_1DIV32 = 0, /**< Guard interval 1/32nd. */ + DRX_GUARD_1DIV16, /**< Guard interval 1/16th. */ + DRX_GUARD_1DIV8, /**< Guard interval 1/8th. */ + DRX_GUARD_1DIV4, /**< Guard interval 1/4th. */ + DRX_GUARD_UNKNOWN = DRX_UNKNOWN, + /**< Guard interval unknown. */ + DRX_GUARD_AUTO = DRX_AUTO + /**< Autodetect guard interval. */ +}; + +/** +* \enum enum drx_fft_mode * \brief FFT mode. */ - typedef enum { - DRX_FFTMODE_2K = 0, /**< 2K FFT mode. */ - DRX_FFTMODE_4K, /**< 4K FFT mode. */ - DRX_FFTMODE_8K, /**< 8K FFT mode. */ - DRX_FFTMODE_UNKNOWN = DRX_UNKNOWN, - /**< FFT mode unknown. */ - DRX_FFTMODE_AUTO = DRX_AUTO - /**< Autodetect FFT mode. */ - } DRXFftmode_t, *pDRXFftmode_t; +enum drx_fft_mode { + DRX_FFTMODE_2K = 0, /**< 2K FFT mode. */ + DRX_FFTMODE_4K, /**< 4K FFT mode. */ + DRX_FFTMODE_8K, /**< 8K FFT mode. */ + DRX_FFTMODE_UNKNOWN = DRX_UNKNOWN, + /**< FFT mode unknown. */ + DRX_FFTMODE_AUTO = DRX_AUTO + /**< Autodetect FFT mode. */ +}; /** -* \enum DRXClassification_t +* \enum enum drx_classification * \brief Channel classification. */ - typedef enum { - DRX_CLASSIFICATION_GAUSS = 0, /**< Gaussion noise. */ - DRX_CLASSIFICATION_HVY_GAUSS, /**< Heavy Gaussion noise. */ - DRX_CLASSIFICATION_COCHANNEL, /**< Co-channel. */ - DRX_CLASSIFICATION_STATIC, /**< Static echo. */ - DRX_CLASSIFICATION_MOVING, /**< Moving echo. */ - DRX_CLASSIFICATION_ZERODB, /**< Zero dB echo. */ - DRX_CLASSIFICATION_UNKNOWN = DRX_UNKNOWN, - /**< Unknown classification */ - DRX_CLASSIFICATION_AUTO = DRX_AUTO - /**< Autodetect classification. */ - } DRXClassification_t, *pDRXClassification_t; - -/** -* /enum DRXInterleaveModes_t +enum drx_classification { + DRX_CLASSIFICATION_GAUSS = 0, /**< Gaussion noise. */ + DRX_CLASSIFICATION_HVY_GAUSS, /**< Heavy Gaussion noise. */ + DRX_CLASSIFICATION_COCHANNEL, /**< Co-channel. */ + DRX_CLASSIFICATION_STATIC, /**< Static echo. */ + DRX_CLASSIFICATION_MOVING, /**< Moving echo. */ + DRX_CLASSIFICATION_ZERODB, /**< Zero dB echo. */ + DRX_CLASSIFICATION_UNKNOWN = DRX_UNKNOWN, + /**< Unknown classification */ + DRX_CLASSIFICATION_AUTO = DRX_AUTO + /**< Autodetect classification. */ +}; + +/** +* /enum enum drx_interleave_mode * /brief Interleave modes */ - typedef enum { - DRX_INTERLEAVEMODE_I128_J1 = 0, - DRX_INTERLEAVEMODE_I128_J1_V2, - DRX_INTERLEAVEMODE_I128_J2, - DRX_INTERLEAVEMODE_I64_J2, - DRX_INTERLEAVEMODE_I128_J3, - DRX_INTERLEAVEMODE_I32_J4, - DRX_INTERLEAVEMODE_I128_J4, - DRX_INTERLEAVEMODE_I16_J8, - DRX_INTERLEAVEMODE_I128_J5, - DRX_INTERLEAVEMODE_I8_J16, - DRX_INTERLEAVEMODE_I128_J6, - DRX_INTERLEAVEMODE_RESERVED_11, - DRX_INTERLEAVEMODE_I128_J7, - DRX_INTERLEAVEMODE_RESERVED_13, - DRX_INTERLEAVEMODE_I128_J8, - DRX_INTERLEAVEMODE_RESERVED_15, - DRX_INTERLEAVEMODE_I12_J17, - DRX_INTERLEAVEMODE_I5_J4, - DRX_INTERLEAVEMODE_B52_M240, - DRX_INTERLEAVEMODE_B52_M720, - DRX_INTERLEAVEMODE_B52_M48, - DRX_INTERLEAVEMODE_B52_M0, - DRX_INTERLEAVEMODE_UNKNOWN = DRX_UNKNOWN, - /**< Unknown interleave mode */ - DRX_INTERLEAVEMODE_AUTO = DRX_AUTO - /**< Autodetect interleave mode */ - } DRXInterleaveModes_t, *pDRXInterleaveModes_t; - -/** -* \enum DRXCarrier_t +enum drx_interleave_mode { + DRX_INTERLEAVEMODE_I128_J1 = 0, + DRX_INTERLEAVEMODE_I128_J1_V2, + DRX_INTERLEAVEMODE_I128_J2, + DRX_INTERLEAVEMODE_I64_J2, + DRX_INTERLEAVEMODE_I128_J3, + DRX_INTERLEAVEMODE_I32_J4, + DRX_INTERLEAVEMODE_I128_J4, + DRX_INTERLEAVEMODE_I16_J8, + DRX_INTERLEAVEMODE_I128_J5, + DRX_INTERLEAVEMODE_I8_J16, + DRX_INTERLEAVEMODE_I128_J6, + DRX_INTERLEAVEMODE_RESERVED_11, + DRX_INTERLEAVEMODE_I128_J7, + DRX_INTERLEAVEMODE_RESERVED_13, + DRX_INTERLEAVEMODE_I128_J8, + DRX_INTERLEAVEMODE_RESERVED_15, + DRX_INTERLEAVEMODE_I12_J17, + DRX_INTERLEAVEMODE_I5_J4, + DRX_INTERLEAVEMODE_B52_M240, + DRX_INTERLEAVEMODE_B52_M720, + DRX_INTERLEAVEMODE_B52_M48, + DRX_INTERLEAVEMODE_B52_M0, + DRX_INTERLEAVEMODE_UNKNOWN = DRX_UNKNOWN, + /**< Unknown interleave mode */ + DRX_INTERLEAVEMODE_AUTO = DRX_AUTO + /**< Autodetect interleave mode */ +}; + +/** +* \enum enum drx_carrier_mode * \brief Channel Carrier Mode. */ - typedef enum { - DRX_CARRIER_MULTI = 0, /**< Multi carrier mode */ - DRX_CARRIER_SINGLE, /**< Single carrier mode */ - DRX_CARRIER_UNKNOWN = DRX_UNKNOWN, - /**< Carrier mode unknown. */ - DRX_CARRIER_AUTO = DRX_AUTO /**< Autodetect carrier mode */ - } DRXCarrier_t, *pDRXCarrier_t; +enum drx_carrier_mode{ + DRX_CARRIER_MULTI = 0, /**< Multi carrier mode */ + DRX_CARRIER_SINGLE, /**< Single carrier mode */ + DRX_CARRIER_UNKNOWN = DRX_UNKNOWN, + /**< Carrier mode unknown. */ + DRX_CARRIER_AUTO = DRX_AUTO /**< Autodetect carrier mode */ +}; /** -* \enum DRXFramemode_t +* \enum enum drx_frame_mode * \brief Channel Frame Mode. */ - typedef enum { - DRX_FRAMEMODE_420 = 0, /**< 420 with variable PN */ - DRX_FRAMEMODE_595, /**< 595 */ - DRX_FRAMEMODE_945, /**< 945 with variable PN */ - DRX_FRAMEMODE_420_FIXED_PN, - /**< 420 with fixed PN */ - DRX_FRAMEMODE_945_FIXED_PN, - /**< 945 with fixed PN */ - DRX_FRAMEMODE_UNKNOWN = DRX_UNKNOWN, - /**< Frame mode unknown. */ - DRX_FRAMEMODE_AUTO = DRX_AUTO - /**< Autodetect frame mode */ - } DRXFramemode_t, *pDRXFramemode_t; - -/** -* \enum DRXTPSFrame_t +enum drx_frame_mode{ + DRX_FRAMEMODE_420 = 0, /**< 420 with variable PN */ + DRX_FRAMEMODE_595, /**< 595 */ + DRX_FRAMEMODE_945, /**< 945 with variable PN */ + DRX_FRAMEMODE_420_FIXED_PN, + /**< 420 with fixed PN */ + DRX_FRAMEMODE_945_FIXED_PN, + /**< 945 with fixed PN */ + DRX_FRAMEMODE_UNKNOWN = DRX_UNKNOWN, + /**< Frame mode unknown. */ + DRX_FRAMEMODE_AUTO = DRX_AUTO + /**< Autodetect frame mode */ +}; + +/** +* \enum enum drx_tps_frame * \brief Frame number in current super-frame. */ - typedef enum { - DRX_TPS_FRAME1 = 0, /**< TPS frame 1. */ - DRX_TPS_FRAME2, /**< TPS frame 2. */ - DRX_TPS_FRAME3, /**< TPS frame 3. */ - DRX_TPS_FRAME4, /**< TPS frame 4. */ - DRX_TPS_FRAME_UNKNOWN = DRX_UNKNOWN - /**< TPS frame unknown. */ - } DRXTPSFrame_t, *pDRXTPSFrame_t; +enum drx_tps_frame{ + DRX_TPS_FRAME1 = 0, /**< TPS frame 1. */ + DRX_TPS_FRAME2, /**< TPS frame 2. */ + DRX_TPS_FRAME3, /**< TPS frame 3. */ + DRX_TPS_FRAME4, /**< TPS frame 4. */ + DRX_TPS_FRAME_UNKNOWN = DRX_UNKNOWN + /**< TPS frame unknown. */ +}; /** -* \enum DRXLDPC_t +* \enum enum drx_ldpc * \brief TPS LDPC . */ - typedef enum { - DRX_LDPC_0_4 = 0, /**< LDPC 0.4 */ - DRX_LDPC_0_6, /**< LDPC 0.6 */ - DRX_LDPC_0_8, /**< LDPC 0.8 */ - DRX_LDPC_UNKNOWN = DRX_UNKNOWN, - /**< LDPC unknown. */ - DRX_LDPC_AUTO = DRX_AUTO /**< Autodetect LDPC */ - } DRXLDPC_t, *pDRXLDPC_t; +enum drx_ldpc{ + DRX_LDPC_0_4 = 0, /**< LDPC 0.4 */ + DRX_LDPC_0_6, /**< LDPC 0.6 */ + DRX_LDPC_0_8, /**< LDPC 0.8 */ + DRX_LDPC_UNKNOWN = DRX_UNKNOWN, + /**< LDPC unknown. */ + DRX_LDPC_AUTO = DRX_AUTO /**< Autodetect LDPC */ +}; /** -* \enum DRXPilotMode_t +* \enum enum drx_pilot_mode * \brief Pilot modes in DTMB. */ - typedef enum { - DRX_PILOT_ON = 0, /**< Pilot On */ - DRX_PILOT_OFF, /**< Pilot Off */ - DRX_PILOT_UNKNOWN = DRX_UNKNOWN, - /**< Pilot unknown. */ - DRX_PILOT_AUTO = DRX_AUTO /**< Autodetect Pilot */ - } DRXPilotMode_t, *pDRXPilotMode_t; - -/** -* \enum DRXCtrlIndex_t -* \brief Indices of the control functions. -*/ - typedef u32 DRXCtrlIndex_t, *pDRXCtrlIndex_t; +enum drx_pilot_mode{ + DRX_PILOT_ON = 0, /**< Pilot On */ + DRX_PILOT_OFF, /**< Pilot Off */ + DRX_PILOT_UNKNOWN = DRX_UNKNOWN, + /**< Pilot unknown. */ + DRX_PILOT_AUTO = DRX_AUTO /**< Autodetect Pilot */ +}; -#ifndef DRX_CTRL_BASE -#define DRX_CTRL_BASE ((DRXCtrlIndex_t)0) -#endif +#define DRX_CTRL_BASE ((u32)0) #define DRX_CTRL_NOP ( DRX_CTRL_BASE + 0)/**< No Operation */ #define DRX_CTRL_PROBE_DEVICE ( DRX_CTRL_BASE + 1)/**< Probe device */ @@ -1129,28 +1102,28 @@ STRUCTS typedef struct { s32 frequency; /**< frequency in kHz */ - DRXBandwidth_t bandwidth; + enum drx_bandwidth bandwidth; /**< bandwidth */ - DRXMirror_t mirror; /**< mirrored or not on RF */ - DRXConstellation_t constellation; + enum drx_mirror mirror; /**< mirrored or not on RF */ + enum drx_modulation constellation; /**< constellation */ - DRXHierarchy_t hierarchy; + enum drx_hierarchy hierarchy; /**< hierarchy */ - DRXPriority_t priority; /**< priority */ - DRXCoderate_t coderate; /**< coderate */ - DRXGuard_t guard; /**< guard interval */ - DRXFftmode_t fftmode; /**< fftmode */ - DRXClassification_t classification; + enum drx_priority priority; /**< priority */ + enum drx_coderate coderate; /**< coderate */ + enum drx_guard guard; /**< guard interval */ + enum drx_fft_mode fftmode; /**< fftmode */ + enum drx_classification classification; /**< classification */ u32 symbolrate; /**< symbolrate in symbols/sec */ - DRXInterleaveModes_t interleavemode; + enum drx_interleave_mode interleavemode; /**< interleaveMode QAM */ - DRXLDPC_t ldpc; /**< ldpc */ - DRXCarrier_t carrier; /**< carrier */ - DRXFramemode_t framemode; + enum drx_ldpc ldpc; /**< ldpc */ + enum drx_carrier_mode carrier; /**< carrier */ + enum drx_frame_mode framemode; /**< frame mode */ - DRXPilotMode_t pilot; /**< pilot mode */ + enum drx_pilot_mode pilot; /**< pilot mode */ } DRXChannel_t, *pDRXChannel_t; /*========================================*/ @@ -1217,7 +1190,7 @@ STRUCTS /**< Last centre frequency in this band */ s32 step; /**< Stepping frequency in this band */ - DRXBandwidth_t bandwidth; + enum drx_bandwidth bandwidth; /**< Bandwidth within this frequency band */ u16 chNumber; /**< First channel number in this band, or first @@ -1250,7 +1223,7 @@ STRUCTS typedef struct { u32 *symbolrate; /**< list of symbolrates to scan */ u16 symbolrateSize; /**< size of symbolrate array */ - pDRXConstellation_t constellation; + enum drx_modulation * constellation; /**< list of constellations */ u16 constellationSize; /**< size of constellation array */ u16 ifAgcThreshold; /**< thresholf for IF-AGC based @@ -1303,7 +1276,7 @@ STRUCTS /** * \brief Inner scan function prototype. */ - typedef DRXStatus_t(*DRXScanFunc_t) (void *scanContext, + typedef int(*DRXScanFunc_t) (void *scanContext, DRXScanCommand_t scanCommand, pDRXChannel_t scanChannel, bool * getNextChannel); @@ -1317,17 +1290,17 @@ STRUCTS * Used by DRX_CTRL_TPS_INFO. */ typedef struct { - DRXFftmode_t fftmode; /**< Fft mode */ - DRXGuard_t guard; /**< Guard interval */ - DRXConstellation_t constellation; + enum drx_fft_mode fftmode; /**< Fft mode */ + enum drx_guard guard; /**< Guard interval */ + enum drx_modulation constellation; /**< Constellation */ - DRXHierarchy_t hierarchy; + enum drx_hierarchy hierarchy; /**< Hierarchy */ - DRXCoderate_t highCoderate; + enum drx_coderate highCoderate; /**< High code rate */ - DRXCoderate_t lowCoderate; + enum drx_coderate lowCoderate; /**< Low cod rate */ - DRXTPSFrame_t frame; /**< Tps frame */ + enum drx_tps_frame frame; /**< Tps frame */ u8 length; /**< Length */ u16 cellId; /**< Cell id */ } DRXTPSInfo_t, *pDRXTPSInfo_t; @@ -1970,71 +1943,71 @@ STRUCTS typedef u32 DRXflags_t, *pDRXflags_t; /* Write block of data to device */ - typedef DRXStatus_t(*DRXWriteBlockFunc_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ + typedef int(*DRXWriteBlockFunc_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register/memory */ u16 datasize, /* size of data in bytes */ u8 *data, /* data to send */ DRXflags_t flags); /* Read block of data from device */ - typedef DRXStatus_t(*DRXReadBlockFunc_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ + typedef int(*DRXReadBlockFunc_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register/memory */ u16 datasize, /* size of data in bytes */ u8 *data, /* receive buffer */ DRXflags_t flags); /* Write 8-bits value to device */ - typedef DRXStatus_t(*DRXWriteReg8Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ + typedef int(*DRXWriteReg8Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register/memory */ u8 data, /* data to send */ DRXflags_t flags); /* Read 8-bits value to device */ - typedef DRXStatus_t(*DRXReadReg8Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ + typedef int(*DRXReadReg8Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register/memory */ u8 *data, /* receive buffer */ DRXflags_t flags); /* Read modify write 8-bits value to device */ - typedef DRXStatus_t(*DRXReadModifyWriteReg8Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ + typedef int(*DRXReadModifyWriteReg8Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t waddr, /* write address of register */ DRXaddr_t raddr, /* read address of register */ u8 wdata, /* data to write */ u8 *rdata); /* data to read */ /* Write 16-bits value to device */ - typedef DRXStatus_t(*DRXWriteReg16Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ + typedef int(*DRXWriteReg16Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register/memory */ u16 data, /* data to send */ DRXflags_t flags); /* Read 16-bits value to device */ - typedef DRXStatus_t(*DRXReadReg16Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ + typedef int(*DRXReadReg16Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register/memory */ u16 *data, /* receive buffer */ DRXflags_t flags); /* Read modify write 16-bits value to device */ - typedef DRXStatus_t(*DRXReadModifyWriteReg16Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ + typedef int(*DRXReadModifyWriteReg16Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t waddr, /* write address of register */ DRXaddr_t raddr, /* read address of register */ u16 wdata, /* data to write */ u16 *rdata); /* data to read */ /* Write 32-bits value to device */ - typedef DRXStatus_t(*DRXWriteReg32Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ + typedef int(*DRXWriteReg32Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register/memory */ u32 data, /* data to send */ DRXflags_t flags); /* Read 32-bits value to device */ - typedef DRXStatus_t(*DRXReadReg32Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ + typedef int(*DRXReadReg32Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t addr, /* address of register/memory */ u32 *data, /* receive buffer */ DRXflags_t flags); /* Read modify write 32-bits value to device */ - typedef DRXStatus_t(*DRXReadModifyWriteReg32Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ + typedef int(*DRXReadModifyWriteReg32Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ DRXaddr_t waddr, /* write address of register */ DRXaddr_t raddr, /* read address of register */ u32 wdata, /* data to write */ @@ -2146,11 +2119,11 @@ STRUCTS DRXChannel_t currentChannel; /**< current channel parameters */ - DRXStandard_t currentStandard; + enum drx_standard currentStandard; /**< current standard selection */ - DRXStandard_t prevStandard; + enum drx_standard prevStandard; /**< previous standard selection */ - DRXStandard_t diCacheStandard; + enum drx_standard diCacheStandard; /**< standard in DI cache if available */ bool useBootloader; /**< use bootloader in open */ u32 capabilities; /**< capabilities flags */ @@ -2163,10 +2136,10 @@ STRUCTS */ typedef struct DRXDemodInstance_s *pDRXDemodInstance_t; - typedef DRXStatus_t(*DRXOpenFunc_t) (pDRXDemodInstance_t demod); - typedef DRXStatus_t(*DRXCloseFunc_t) (pDRXDemodInstance_t demod); - typedef DRXStatus_t(*DRXCtrlFunc_t) (pDRXDemodInstance_t demod, - DRXCtrlIndex_t ctrl, + typedef int(*DRXOpenFunc_t) (pDRXDemodInstance_t demod); + typedef int(*DRXCloseFunc_t) (pDRXDemodInstance_t demod); + typedef int(*DRXCtrlFunc_t) (pDRXDemodInstance_t demod, + u32 ctrl, void *ctrlData); /** @@ -2190,7 +2163,7 @@ STRUCTS /**< demodulator functions */ pDRXAccessFunc_t myAccessFunct; /**< data access protocol functions */ - pTUNERInstance_t myTuner; + struct tuner_instance *myTuner; /**< tuner instance,if NULL then baseband */ struct i2c_device_addr *myI2CDevAddr; /**< i2c address and device identifier */ @@ -2865,7 +2838,7 @@ Access macros #define DRX_ACCESSMACRO_GET( demod, value, cfgName, dataType, errorValue ) \ do { \ - DRXStatus_t cfgStatus; \ + int cfgStatus; \ DRXCfg_t config; \ dataType cfgData; \ config.cfgType = cfgName; \ @@ -2946,21 +2919,18 @@ Access macros Exported FUNCTIONS -------------------------------------------------------------------------*/ - DRXStatus_t DRX_Init(pDRXDemodInstance_t demods[]); + int DRX_Init(pDRXDemodInstance_t demods[]); - DRXStatus_t DRX_Term(void); + int DRX_Term(void); - DRXStatus_t DRX_Open(pDRXDemodInstance_t demod); + int DRX_Open(pDRXDemodInstance_t demod); - DRXStatus_t DRX_Close(pDRXDemodInstance_t demod); + int DRX_Close(pDRXDemodInstance_t demod); - DRXStatus_t DRX_Ctrl(pDRXDemodInstance_t demod, - DRXCtrlIndex_t ctrl, void *ctrlData); + int DRX_Ctrl(pDRXDemodInstance_t demod, + u32 ctrl, void *ctrlData); /*------------------------------------------------------------------------- THE END -------------------------------------------------------------------------*/ -#ifdef __cplusplus -} -#endif #endif /* __DRXDRIVER_H__ */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index 384b869..c821206 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -586,10 +586,10 @@ DEFINES /*----------------------------------------------------------------------------- STATIC VARIABLES ----------------------------------------------------------------------------*/ -DRXStatus_t DRXJ_Open(pDRXDemodInstance_t demod); -DRXStatus_t DRXJ_Close(pDRXDemodInstance_t demod); -DRXStatus_t DRXJ_Ctrl(pDRXDemodInstance_t demod, - DRXCtrlIndex_t ctrl, void *ctrlData); +int DRXJ_Open(pDRXDemodInstance_t demod); +int DRXJ_Close(pDRXDemodInstance_t demod); +int DRXJ_Ctrl(pDRXDemodInstance_t demod, + u32 ctrl, void *ctrlData); /*----------------------------------------------------------------------------- GLOBAL VARIABLES @@ -598,52 +598,52 @@ GLOBAL VARIABLES * DRXJ DAP structures */ -static DRXStatus_t DRXJ_DAP_ReadBlock(struct i2c_device_addr *devAddr, +static int DRXJ_DAP_ReadBlock(struct i2c_device_addr *devAddr, DRXaddr_t addr, u16 datasize, u8 *data, DRXflags_t flags); -static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg8(struct i2c_device_addr *devAddr, +static int DRXJ_DAP_ReadModifyWriteReg8(struct i2c_device_addr *devAddr, DRXaddr_t waddr, DRXaddr_t raddr, u8 wdata, u8 *rdata); -static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg16(struct i2c_device_addr *devAddr, +static int DRXJ_DAP_ReadModifyWriteReg16(struct i2c_device_addr *devAddr, DRXaddr_t waddr, DRXaddr_t raddr, u16 wdata, u16 *rdata); -static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg32(struct i2c_device_addr *devAddr, +static int DRXJ_DAP_ReadModifyWriteReg32(struct i2c_device_addr *devAddr, DRXaddr_t waddr, DRXaddr_t raddr, u32 wdata, u32 *rdata); -static DRXStatus_t DRXJ_DAP_ReadReg8(struct i2c_device_addr *devAddr, +static int DRXJ_DAP_ReadReg8(struct i2c_device_addr *devAddr, DRXaddr_t addr, u8 *data, DRXflags_t flags); -static DRXStatus_t DRXJ_DAP_ReadReg16(struct i2c_device_addr *devAddr, +static int DRXJ_DAP_ReadReg16(struct i2c_device_addr *devAddr, DRXaddr_t addr, u16 *data, DRXflags_t flags); -static DRXStatus_t DRXJ_DAP_ReadReg32(struct i2c_device_addr *devAddr, +static int DRXJ_DAP_ReadReg32(struct i2c_device_addr *devAddr, DRXaddr_t addr, u32 *data, DRXflags_t flags); -static DRXStatus_t DRXJ_DAP_WriteBlock(struct i2c_device_addr *devAddr, +static int DRXJ_DAP_WriteBlock(struct i2c_device_addr *devAddr, DRXaddr_t addr, u16 datasize, u8 *data, DRXflags_t flags); -static DRXStatus_t DRXJ_DAP_WriteReg8(struct i2c_device_addr *devAddr, +static int DRXJ_DAP_WriteReg8(struct i2c_device_addr *devAddr, DRXaddr_t addr, u8 data, DRXflags_t flags); -static DRXStatus_t DRXJ_DAP_WriteReg16(struct i2c_device_addr *devAddr, +static int DRXJ_DAP_WriteReg16(struct i2c_device_addr *devAddr, DRXaddr_t addr, u16 data, DRXflags_t flags); -static DRXStatus_t DRXJ_DAP_WriteReg32(struct i2c_device_addr *devAddr, +static int DRXJ_DAP_WriteReg32(struct i2c_device_addr *devAddr, DRXaddr_t addr, u32 data, DRXflags_t flags); @@ -1145,33 +1145,33 @@ typedef struct { FUNCTIONS ----------------------------------------------------------------------------*/ /* Some prototypes */ -static DRXStatus_t +static int HICommand(struct i2c_device_addr *devAddr, const pDRXJHiCmd_t cmd, u16 *result); -static DRXStatus_t +static int CtrlLockStatus(pDRXDemodInstance_t demod, pDRXLockStatus_t lockStat); -static DRXStatus_t +static int CtrlPowerMode(pDRXDemodInstance_t demod, pDRXPowerMode_t mode); -static DRXStatus_t PowerDownAud(pDRXDemodInstance_t demod); +static int PowerDownAud(pDRXDemodInstance_t demod); #ifndef DRXJ_DIGITAL_ONLY -static DRXStatus_t PowerUpAud(pDRXDemodInstance_t demod, bool setStandard); +static int PowerUpAud(pDRXDemodInstance_t demod, bool setStandard); #endif -static DRXStatus_t +static int AUDCtrlSetStandard(pDRXDemodInstance_t demod, pDRXAudStandard_t standard); -static DRXStatus_t +static int CtrlSetCfgPreSaw(pDRXDemodInstance_t demod, pDRXJCfgPreSaw_t preSaw); -static DRXStatus_t +static int CtrlSetCfgAfeGain(pDRXDemodInstance_t demod, pDRXJCfgAfeGain_t afeGain); #ifdef DRXJ_SPLIT_UCODE_UPLOAD -static DRXStatus_t +static int CtrlUCodeUpload(pDRXDemodInstance_t demod, pDRXUCodeInfo_t mcInfo, DRXUCodeAction_t action, bool audioMCUpload); @@ -1712,7 +1712,7 @@ bool IsHandledByAudTrIf(DRXaddr_t addr) /*============================================================================*/ -static DRXStatus_t DRXJ_DAP_ReadBlock(struct i2c_device_addr *devAddr, +static int DRXJ_DAP_ReadBlock(struct i2c_device_addr *devAddr, DRXaddr_t addr, u16 datasize, u8 *data, DRXflags_t flags) @@ -1723,7 +1723,7 @@ static DRXStatus_t DRXJ_DAP_ReadBlock(struct i2c_device_addr *devAddr, /*============================================================================*/ -static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg8(struct i2c_device_addr *devAddr, +static int DRXJ_DAP_ReadModifyWriteReg8(struct i2c_device_addr *devAddr, DRXaddr_t waddr, DRXaddr_t raddr, u8 wdata, u8 *rdata) @@ -1736,14 +1736,14 @@ static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg8(struct i2c_device_addr *devAddr, /*============================================================================*/ /** -* \fn DRXStatus_t DRXJ_DAP_RMWriteReg16Short +* \fn int DRXJ_DAP_RMWriteReg16Short * \brief Read modify write 16 bits audio register using short format only. * \param devAddr * \param waddr Address to write to * \param raddr Address to read from (usually SIO_HI_RA_RAM_S0_RMWBUF__A) * \param wdata Data to write * \param rdata Buffer for data to read -* \return DRXStatus_t +* \return int * \retval DRX_STS_OK Succes * \retval DRX_STS_ERROR Timeout, I2C error, illegal bank * @@ -1756,12 +1756,12 @@ static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg8(struct i2c_device_addr *devAddr, /* TODO correct define should be #if ( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 ) See comments DRXJ_DAP_ReadModifyWriteReg16 */ #if ( DRXDAPFASI_LONG_ADDR_ALLOWED == 0 ) -static DRXStatus_t DRXJ_DAP_RMWriteReg16Short(struct i2c_device_addr *devAddr, +static int DRXJ_DAP_RMWriteReg16Short(struct i2c_device_addr *devAddr, DRXaddr_t waddr, DRXaddr_t raddr, u16 wdata, u16 *rdata) { - DRXStatus_t rc; + int rc; if (rdata == NULL) { return DRX_STS_INVALID_ARG; @@ -1795,7 +1795,7 @@ static DRXStatus_t DRXJ_DAP_RMWriteReg16Short(struct i2c_device_addr *devAddr, /*============================================================================*/ -static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg16(struct i2c_device_addr *devAddr, +static int DRXJ_DAP_ReadModifyWriteReg16(struct i2c_device_addr *devAddr, DRXaddr_t waddr, DRXaddr_t raddr, u16 wdata, u16 *rdata) @@ -1814,7 +1814,7 @@ static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg16(struct i2c_device_addr *devAddr /*============================================================================*/ -static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg32(struct i2c_device_addr *devAddr, +static int DRXJ_DAP_ReadModifyWriteReg32(struct i2c_device_addr *devAddr, DRXaddr_t waddr, DRXaddr_t raddr, u32 wdata, u32 *rdata) @@ -1826,7 +1826,7 @@ static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg32(struct i2c_device_addr *devAddr /*============================================================================*/ -static DRXStatus_t DRXJ_DAP_ReadReg8(struct i2c_device_addr *devAddr, +static int DRXJ_DAP_ReadReg8(struct i2c_device_addr *devAddr, DRXaddr_t addr, u8 *data, DRXflags_t flags) { @@ -1836,26 +1836,26 @@ static DRXStatus_t DRXJ_DAP_ReadReg8(struct i2c_device_addr *devAddr, /*============================================================================*/ /** -* \fn DRXStatus_t DRXJ_DAP_ReadAudReg16 +* \fn int DRXJ_DAP_ReadAudReg16 * \brief Read 16 bits audio register * \param devAddr * \param addr * \param data -* \return DRXStatus_t +* \return int * \retval DRX_STS_OK Succes * \retval DRX_STS_ERROR Timeout, I2C error, illegal bank * * 16 bits register read access via audio token ring interface. * */ -static DRXStatus_t DRXJ_DAP_ReadAudReg16(struct i2c_device_addr *devAddr, +static int DRXJ_DAP_ReadAudReg16(struct i2c_device_addr *devAddr, DRXaddr_t addr, u16 *data) { u32 startTimer = 0; u32 currentTimer = 0; u32 deltaTimer = 0; u16 trStatus = 0; - DRXStatus_t stat = DRX_STS_ERROR; + int stat = DRX_STS_ERROR; /* No read possible for bank 3, return with error */ if (DRXDAP_FASI_ADDR2BANK(addr) == 3) { @@ -1928,11 +1928,11 @@ static DRXStatus_t DRXJ_DAP_ReadAudReg16(struct i2c_device_addr *devAddr, /*============================================================================*/ -static DRXStatus_t DRXJ_DAP_ReadReg16(struct i2c_device_addr *devAddr, +static int DRXJ_DAP_ReadReg16(struct i2c_device_addr *devAddr, DRXaddr_t addr, u16 *data, DRXflags_t flags) { - DRXStatus_t stat = DRX_STS_ERROR; + int stat = DRX_STS_ERROR; /* Check param */ if ((devAddr == NULL) || (data == NULL)) { @@ -1951,7 +1951,7 @@ static DRXStatus_t DRXJ_DAP_ReadReg16(struct i2c_device_addr *devAddr, /*============================================================================*/ -static DRXStatus_t DRXJ_DAP_ReadReg32(struct i2c_device_addr *devAddr, +static int DRXJ_DAP_ReadReg32(struct i2c_device_addr *devAddr, DRXaddr_t addr, u32 *data, DRXflags_t flags) { @@ -1960,7 +1960,7 @@ static DRXStatus_t DRXJ_DAP_ReadReg32(struct i2c_device_addr *devAddr, /*============================================================================*/ -static DRXStatus_t DRXJ_DAP_WriteBlock(struct i2c_device_addr *devAddr, +static int DRXJ_DAP_WriteBlock(struct i2c_device_addr *devAddr, DRXaddr_t addr, u16 datasize, u8 *data, DRXflags_t flags) @@ -1971,7 +1971,7 @@ static DRXStatus_t DRXJ_DAP_WriteBlock(struct i2c_device_addr *devAddr, /*============================================================================*/ -static DRXStatus_t DRXJ_DAP_WriteReg8(struct i2c_device_addr *devAddr, +static int DRXJ_DAP_WriteReg8(struct i2c_device_addr *devAddr, DRXaddr_t addr, u8 data, DRXflags_t flags) { @@ -1981,22 +1981,22 @@ static DRXStatus_t DRXJ_DAP_WriteReg8(struct i2c_device_addr *devAddr, /*============================================================================*/ /** -* \fn DRXStatus_t DRXJ_DAP_WriteAudReg16 +* \fn int DRXJ_DAP_WriteAudReg16 * \brief Write 16 bits audio register * \param devAddr * \param addr * \param data -* \return DRXStatus_t +* \return int * \retval DRX_STS_OK Succes * \retval DRX_STS_ERROR Timeout, I2C error, illegal bank * * 16 bits register write access via audio token ring interface. * */ -static DRXStatus_t DRXJ_DAP_WriteAudReg16(struct i2c_device_addr *devAddr, +static int DRXJ_DAP_WriteAudReg16(struct i2c_device_addr *devAddr, DRXaddr_t addr, u16 data) { - DRXStatus_t stat = DRX_STS_ERROR; + int stat = DRX_STS_ERROR; /* No write possible for bank 2, return with error */ if (DRXDAP_FASI_ADDR2BANK(addr) == 2) { @@ -2040,11 +2040,11 @@ static DRXStatus_t DRXJ_DAP_WriteAudReg16(struct i2c_device_addr *devAddr, /*============================================================================*/ -static DRXStatus_t DRXJ_DAP_WriteReg16(struct i2c_device_addr *devAddr, +static int DRXJ_DAP_WriteReg16(struct i2c_device_addr *devAddr, DRXaddr_t addr, u16 data, DRXflags_t flags) { - DRXStatus_t stat = DRX_STS_ERROR; + int stat = DRX_STS_ERROR; /* Check param */ if (devAddr == NULL) { @@ -2063,7 +2063,7 @@ static DRXStatus_t DRXJ_DAP_WriteReg16(struct i2c_device_addr *devAddr, /*============================================================================*/ -static DRXStatus_t DRXJ_DAP_WriteReg32(struct i2c_device_addr *devAddr, +static int DRXJ_DAP_WriteReg32(struct i2c_device_addr *devAddr, DRXaddr_t addr, u32 data, DRXflags_t flags) { @@ -2082,19 +2082,19 @@ static DRXStatus_t DRXJ_DAP_WriteReg32(struct i2c_device_addr *devAddr, #define DRXJ_HI_ATOMIC_WRITE SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE /** -* \fn DRXStatus_t DRXJ_DAP_AtomicReadWriteBlock() +* \fn int DRXJ_DAP_AtomicReadWriteBlock() * \brief Basic access routine for atomic read or write access * \param devAddr pointer to i2c dev address * \param addr destination/source address * \param datasize size of data buffer in bytes * \param data pointer to data buffer -* \return DRXStatus_t +* \return int * \retval DRX_STS_OK Succes * \retval DRX_STS_ERROR Timeout, I2C error, illegal bank * */ static -DRXStatus_t DRXJ_DAP_AtomicReadWriteBlock(struct i2c_device_addr *devAddr, +int DRXJ_DAP_AtomicReadWriteBlock(struct i2c_device_addr *devAddr, DRXaddr_t addr, u16 datasize, u8 *data, bool readFlag) @@ -2164,16 +2164,16 @@ rw_error: /*============================================================================*/ /** -* \fn DRXStatus_t DRXJ_DAP_AtomicReadReg32() +* \fn int DRXJ_DAP_AtomicReadReg32() * \brief Atomic read of 32 bits words */ static -DRXStatus_t DRXJ_DAP_AtomicReadReg32(struct i2c_device_addr *devAddr, +int DRXJ_DAP_AtomicReadReg32(struct i2c_device_addr *devAddr, DRXaddr_t addr, u32 *data, DRXflags_t flags) { u8 buf[sizeof(*data)]; - DRXStatus_t rc = DRX_STS_ERROR; + int rc = DRX_STS_ERROR; u32 word = 0; if (!data) { @@ -2209,17 +2209,17 @@ DRXStatus_t DRXJ_DAP_AtomicReadReg32(struct i2c_device_addr *devAddr, /*============================================================================*/ /** -* \fn DRXStatus_t HICfgCommand() +* \fn int HICfgCommand() * \brief Configure HI with settings stored in the demod structure. * \param demod Demodulator. -* \return DRXStatus_t. +* \return int. * * This routine was created because to much orthogonal settings have * been put into one HI API function (configure). Especially the I2C bridge * enable/disable should not need re-configuration of the HI. * */ -static DRXStatus_t HICfgCommand(const pDRXDemodInstance_t demod) +static int HICfgCommand(const pDRXDemodInstance_t demod) { pDRXJData_t extAttr = (pDRXJData_t) (NULL); DRXJHiCmd_t hiCmd; @@ -2247,17 +2247,17 @@ rw_error: } /** -* \fn DRXStatus_t HICommand() +* \fn int HICommand() * \brief Configure HI with settings stored in the demod structure. * \param devAddr I2C address. * \param cmd HI command. * \param result HI command result. -* \return DRXStatus_t. +* \return int. * * Sends command to HI * */ -static DRXStatus_t +static int HICommand(struct i2c_device_addr *devAddr, const pDRXJHiCmd_t cmd, u16 *result) { u16 waitCmd = 0; @@ -2322,10 +2322,10 @@ rw_error: } /** -* \fn DRXStatus_t InitHI( const pDRXDemodInstance_t demod ) +* \fn int InitHI( const pDRXDemodInstance_t demod ) * \brief Initialise and configurate HI. * \param demod pointer to demod data. -* \return DRXStatus_t Return status. +* \return int Return status. * \retval DRX_STS_OK Success. * \retval DRX_STS_ERROR Failure. * @@ -2334,7 +2334,7 @@ rw_error: * bridging is controlled. * */ -static DRXStatus_t InitHI(const pDRXDemodInstance_t demod) +static int InitHI(const pDRXDemodInstance_t demod) { pDRXJData_t extAttr = (pDRXJData_t) (NULL); pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); @@ -2396,10 +2396,10 @@ rw_error: /*============================================================================*/ /** -* \fn DRXStatus_t GetDeviceCapabilities() +* \fn int GetDeviceCapabilities() * \brief Get and store device capabilities. * \param demod Pointer to demodulator instance. -* \return DRXStatus_t. +* \return int. * \return DRX_STS_OK Success * \retval DRX_STS_ERROR Failure * @@ -2411,7 +2411,7 @@ rw_error: * * extAttr->hasOOB * */ -static DRXStatus_t GetDeviceCapabilities(pDRXDemodInstance_t demod) +static int GetDeviceCapabilities(pDRXDemodInstance_t demod) { pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); pDRXJData_t extAttr = (pDRXJData_t) NULL; @@ -2573,10 +2573,10 @@ rw_error: } /** -* \fn DRXStatus_t PowerUpDevice() +* \fn int PowerUpDevice() * \brief Power up device. * \param demod Pointer to demodulator instance. -* \return DRXStatus_t. +* \return int. * \return DRX_STS_OK Success * \retval DRX_STS_ERROR Failure, I2C or max retries reached * @@ -2586,7 +2586,7 @@ rw_error: #define DRXJ_MAX_RETRIES_POWERUP 10 #endif -static DRXStatus_t PowerUpDevice(pDRXDemodInstance_t demod) +static int PowerUpDevice(pDRXDemodInstance_t demod) { struct i2c_device_addr *devAddr = (struct i2c_device_addr *) (NULL); u8 data = 0; @@ -2626,16 +2626,16 @@ static DRXStatus_t PowerUpDevice(pDRXDemodInstance_t demod) /* MPEG Output Configuration Functions - begin */ /*----------------------------------------------------------------------------*/ /** -* \fn DRXStatus_t CtrlSetCfgMPEGOutput() +* \fn int CtrlSetCfgMPEGOutput() * \brief Set MPEG output configuration of the device. * \param devmod Pointer to demodulator instance. * \param cfgData Pointer to mpeg output configuaration. -* \return DRXStatus_t. +* \return int. * * Configure MPEG output parameters. * */ -static DRXStatus_t +static int CtrlSetCfgMPEGOutput(pDRXDemodInstance_t demod, pDRXCfgMPEGOutput_t cfgData) { struct i2c_device_addr *devAddr = (struct i2c_device_addr *) (NULL); @@ -3028,16 +3028,16 @@ rw_error: /*----------------------------------------------------------------------------*/ /** -* \fn DRXStatus_t CtrlGetCfgMPEGOutput() +* \fn int CtrlGetCfgMPEGOutput() * \brief Get MPEG output configuration of the device. * \param devmod Pointer to demodulator instance. * \param cfgData Pointer to MPEG output configuaration struct. -* \return DRXStatus_t. +* \return int. * * Retrieve MPEG output configuartion. * */ -static DRXStatus_t +static int CtrlGetCfgMPEGOutput(pDRXDemodInstance_t demod, pDRXCfgMPEGOutput_t cfgData) { struct i2c_device_addr *devAddr = (struct i2c_device_addr *) (NULL); @@ -3087,15 +3087,15 @@ rw_error: /*----------------------------------------------------------------------------*/ /** -* \fn DRXStatus_t SetMPEGTEIHandling() +* \fn int SetMPEGTEIHandling() * \brief Activate MPEG TEI handling settings. * \param devmod Pointer to demodulator instance. -* \return DRXStatus_t. +* \return int. * * This routine should be called during a set channel of QAM/VSB * */ -static DRXStatus_t SetMPEGTEIHandling(pDRXDemodInstance_t demod) +static int SetMPEGTEIHandling(pDRXDemodInstance_t demod) { pDRXJData_t extAttr = (pDRXJData_t) (NULL); struct i2c_device_addr *devAddr = (struct i2c_device_addr *) (NULL); @@ -3135,15 +3135,15 @@ rw_error: /*----------------------------------------------------------------------------*/ /** -* \fn DRXStatus_t BitReverseMPEGOutput() +* \fn int BitReverseMPEGOutput() * \brief Set MPEG output bit-endian settings. * \param devmod Pointer to demodulator instance. -* \return DRXStatus_t. +* \return int. * * This routine should be called during a set channel of QAM/VSB * */ -static DRXStatus_t BitReverseMPEGOutput(pDRXDemodInstance_t demod) +static int BitReverseMPEGOutput(pDRXDemodInstance_t demod) { pDRXJData_t extAttr = (pDRXJData_t) (NULL); struct i2c_device_addr *devAddr = (struct i2c_device_addr *) (NULL); @@ -3171,15 +3171,15 @@ rw_error: /*----------------------------------------------------------------------------*/ /** -* \fn DRXStatus_t SetMPEGOutputClockRate() +* \fn int SetMPEGOutputClockRate() * \brief Set MPEG output clock rate. * \param devmod Pointer to demodulator instance. -* \return DRXStatus_t. +* \return int. * * This routine should be called during a set channel of QAM/VSB * */ -static DRXStatus_t SetMPEGOutputClockRate(pDRXDemodInstance_t demod) +static int SetMPEGOutputClockRate(pDRXDemodInstance_t demod) { pDRXJData_t extAttr = (pDRXJData_t) (NULL); struct i2c_device_addr *devAddr = (struct i2c_device_addr *) (NULL); @@ -3199,15 +3199,15 @@ rw_error: /*----------------------------------------------------------------------------*/ /** -* \fn DRXStatus_t SetMPEGStartWidth() +* \fn int SetMPEGStartWidth() * \brief Set MPEG start width. * \param devmod Pointer to demodulator instance. -* \return DRXStatus_t. +* \return int. * * This routine should be called during a set channel of QAM/VSB * */ -static DRXStatus_t SetMPEGStartWidth(pDRXDemodInstance_t demod) +static int SetMPEGStartWidth(pDRXDemodInstance_t demod) { pDRXJData_t extAttr = (pDRXJData_t) (NULL); struct i2c_device_addr *devAddr = (struct i2c_device_addr *) (NULL); @@ -3235,17 +3235,17 @@ rw_error: /*----------------------------------------------------------------------------*/ /** -* \fn DRXStatus_t CtrlSetCfgMpegOutputMisc() +* \fn int CtrlSetCfgMpegOutputMisc() * \brief Set miscellaneous configuartions * \param devmod Pointer to demodulator instance. * \param cfgData pDRXJCfgMisc_t -* \return DRXStatus_t. +* \return int. * * This routine can be used to set configuartion options that are DRXJ * specific and/or added to the requirements at a late stage. * */ -static DRXStatus_t +static int CtrlSetCfgMpegOutputMisc(pDRXDemodInstance_t demod, pDRXJCfgMpegOutputMisc_t cfgData) { @@ -3284,18 +3284,18 @@ rw_error: /*----------------------------------------------------------------------------*/ /** -* \fn DRXStatus_t CtrlGetCfgMpegOutputMisc() +* \fn int CtrlGetCfgMpegOutputMisc() * \brief Get miscellaneous configuartions. * \param devmod Pointer to demodulator instance. * \param cfgData Pointer to DRXJCfgMisc_t. -* \return DRXStatus_t. +* \return int. * * This routine can be used to retreive the current setting of the configuartion * options that are DRXJ specific and/or added to the requirements at a * late stage. * */ -static DRXStatus_t +static int CtrlGetCfgMpegOutputMisc(pDRXDemodInstance_t demod, pDRXJCfgMpegOutputMisc_t cfgData) { @@ -3326,18 +3326,18 @@ rw_error: /*----------------------------------------------------------------------------*/ /** -* \fn DRXStatus_t CtrlGetCfgHwCfg() +* \fn int CtrlGetCfgHwCfg() * \brief Get HW configuartions. * \param devmod Pointer to demodulator instance. * \param cfgData Pointer to Bool. -* \return DRXStatus_t. +* \return int. * * This routine can be used to retreive the current setting of the configuartion * options that are DRXJ specific and/or added to the requirements at a * late stage. * */ -static DRXStatus_t +static int CtrlGetCfgHwCfg(pDRXDemodInstance_t demod, pDRXJCfgHwCfg_t cfgData) { u16 data = 0; @@ -3368,13 +3368,13 @@ rw_error: /* UIO Configuration Functions - begin */ /*----------------------------------------------------------------------------*/ /** -* \fn DRXStatus_t CtrlSetUIOCfg() +* \fn int CtrlSetUIOCfg() * \brief Configure modus oprandi UIO. * \param demod Pointer to demodulator instance. * \param UIOCfg Pointer to a configuration setting for a certain UIO. -* \return DRXStatus_t. +* \return int. */ -static DRXStatus_t CtrlSetUIOCfg(pDRXDemodInstance_t demod, pDRXUIOCfg_t UIOCfg) +static int CtrlSetUIOCfg(pDRXDemodInstance_t demod, pDRXUIOCfg_t UIOCfg) { pDRXJData_t extAttr = (pDRXJData_t) (NULL); @@ -3481,13 +3481,13 @@ rw_error: /*============================================================================*/ /** -* \fn DRXStatus_t CtrlGetUIOCfg() +* \fn int CtrlGetUIOCfg() * \brief Get modus oprandi UIO. * \param demod Pointer to demodulator instance. * \param UIOCfg Pointer to a configuration setting for a certain UIO. -* \return DRXStatus_t. +* \return int. */ -static DRXStatus_t CtrlGetUIOCfg(pDRXDemodInstance_t demod, pDRXUIOCfg_t UIOCfg) +static int CtrlGetUIOCfg(pDRXDemodInstance_t demod, pDRXUIOCfg_t UIOCfg) { pDRXJData_t extAttr = (pDRXJData_t) NULL; @@ -3524,13 +3524,13 @@ static DRXStatus_t CtrlGetUIOCfg(pDRXDemodInstance_t demod, pDRXUIOCfg_t UIOCfg) } /** -* \fn DRXStatus_t CtrlUIOWrite() +* \fn int CtrlUIOWrite() * \brief Write to a UIO. * \param demod Pointer to demodulator instance. * \param UIOData Pointer to data container for a certain UIO. -* \return DRXStatus_t. +* \return int. */ -static DRXStatus_t +static int CtrlUIOWrite(pDRXDemodInstance_t demod, pDRXUIOData_t UIOData) { pDRXJData_t extAttr = (pDRXJData_t) (NULL); @@ -3670,13 +3670,13 @@ rw_error: } /** -*\fn DRXStatus_t CtrlUIORead +*\fn int CtrlUIORead *\brief Read from a UIO. * \param demod Pointer to demodulator instance. * \param UIOData Pointer to data container for a certain UIO. -* \return DRXStatus_t. +* \return int. */ -static DRXStatus_t CtrlUIORead(pDRXDemodInstance_t demod, pDRXUIOData_t UIOData) +static int CtrlUIORead(pDRXDemodInstance_t demod, pDRXUIOData_t UIOData) { pDRXJData_t extAttr = (pDRXJData_t) (NULL); u16 pinCfgValue = 0; @@ -3815,14 +3815,14 @@ rw_error: /* I2C Bridge Functions - begin */ /*----------------------------------------------------------------------------*/ /** -* \fn DRXStatus_t CtrlI2CBridge() +* \fn int CtrlI2CBridge() * \brief Open or close the I2C switch to tuner. * \param demod Pointer to demodulator instance. * \param bridgeClosed Pointer to bool indication if bridge is closed not. -* \return DRXStatus_t. +* \return int. */ -static DRXStatus_t +static int CtrlI2CBridge(pDRXDemodInstance_t demod, bool * bridgeClosed) { DRXJHiCmd_t hiCmd; @@ -3852,13 +3852,13 @@ CtrlI2CBridge(pDRXDemodInstance_t demod, bool * bridgeClosed) /* Smart antenna Functions - begin */ /*----------------------------------------------------------------------------*/ /** -* \fn DRXStatus_t SmartAntInit() +* \fn int SmartAntInit() * \brief Initialize Smart Antenna. * \param pointer to DRXDemodInstance_t. -* \return DRXStatus_t. +* \return int. * */ -static DRXStatus_t SmartAntInit(pDRXDemodInstance_t demod) +static int SmartAntInit(pDRXDemodInstance_t demod) { u16 data = 0; pDRXJData_t extAttr = NULL; @@ -3895,13 +3895,13 @@ rw_error: } /** -* \fn DRXStatus_t CtrlSetCfgSmartAnt() +* \fn int CtrlSetCfgSmartAnt() * \brief Set Smart Antenna. * \param pointer to DRXJCfgSmartAnt_t. -* \return DRXStatus_t. +* \return int. * */ -static DRXStatus_t +static int CtrlSetCfgSmartAnt(pDRXDemodInstance_t demod, pDRXJCfgSmartAnt_t smartAnt) { pDRXJData_t extAttr = NULL; @@ -3989,7 +3989,7 @@ rw_error: return (DRX_STS_ERROR); } -static DRXStatus_t SCUCommand(struct i2c_device_addr *devAddr, pDRXJSCUCmd_t cmd) +static int SCUCommand(struct i2c_device_addr *devAddr, pDRXJSCUCmd_t cmd) { u16 curCmd = 0; u32 startTime = 0; @@ -4082,20 +4082,20 @@ rw_error: } /** -* \fn DRXStatus_t DRXJ_DAP_SCUAtomicReadWriteBlock() +* \fn int DRXJ_DAP_SCUAtomicReadWriteBlock() * \brief Basic access routine for SCU atomic read or write access * \param devAddr pointer to i2c dev address * \param addr destination/source address * \param datasize size of data buffer in bytes * \param data pointer to data buffer -* \return DRXStatus_t +* \return int * \retval DRX_STS_OK Succes * \retval DRX_STS_ERROR Timeout, I2C error, illegal bank * */ #define ADDR_AT_SCU_SPACE(x) ((x - 0x82E000) * 2) static -DRXStatus_t DRXJ_DAP_SCU_AtomicReadWriteBlock(struct i2c_device_addr *devAddr, DRXaddr_t addr, u16 datasize, /* max 30 bytes because the limit of SCU parameter */ +int DRXJ_DAP_SCU_AtomicReadWriteBlock(struct i2c_device_addr *devAddr, DRXaddr_t addr, u16 datasize, /* max 30 bytes because the limit of SCU parameter */ u8 *data, bool readFlag) { DRXJSCUCmd_t scuCmd; @@ -4152,16 +4152,16 @@ rw_error: /*============================================================================*/ /** -* \fn DRXStatus_t DRXJ_DAP_AtomicReadReg16() +* \fn int DRXJ_DAP_AtomicReadReg16() * \brief Atomic read of 16 bits words */ static -DRXStatus_t DRXJ_DAP_SCU_AtomicReadReg16(struct i2c_device_addr *devAddr, +int DRXJ_DAP_SCU_AtomicReadReg16(struct i2c_device_addr *devAddr, DRXaddr_t addr, u16 *data, DRXflags_t flags) { u8 buf[2]; - DRXStatus_t rc = DRX_STS_ERROR; + int rc = DRX_STS_ERROR; u16 word = 0; if (!data) { @@ -4179,16 +4179,16 @@ DRXStatus_t DRXJ_DAP_SCU_AtomicReadReg16(struct i2c_device_addr *devAddr, /*============================================================================*/ /** -* \fn DRXStatus_t DRXJ_DAP_SCU_AtomicWriteReg16() +* \fn int DRXJ_DAP_SCU_AtomicWriteReg16() * \brief Atomic read of 16 bits words */ static -DRXStatus_t DRXJ_DAP_SCU_AtomicWriteReg16(struct i2c_device_addr *devAddr, +int DRXJ_DAP_SCU_AtomicWriteReg16(struct i2c_device_addr *devAddr, DRXaddr_t addr, u16 data, DRXflags_t flags) { u8 buf[2]; - DRXStatus_t rc = DRX_STS_ERROR; + int rc = DRX_STS_ERROR; buf[0] = (u8) (data & 0xff); buf[1] = (u8) ((data >> 8) & 0xff); @@ -4198,14 +4198,14 @@ DRXStatus_t DRXJ_DAP_SCU_AtomicWriteReg16(struct i2c_device_addr *devAddr, return rc; } -static DRXStatus_t +static int CtrlI2CWriteRead(pDRXDemodInstance_t demod, pDRXI2CData_t i2cData) { return (DRX_STS_FUNC_NOT_AVAILABLE); } -DRXStatus_t -TunerI2CWriteRead(pTUNERInstance_t tuner, +int +TunerI2CWriteRead(struct tuner_instance *tuner, struct i2c_device_addr *wDevAddr, u16 wCount, u8 *wData, @@ -4225,12 +4225,12 @@ TunerI2CWriteRead(pTUNERInstance_t tuner, * \brief Measure result of ADC synchronisation * \param demod demod instance * \param count (returned) count -* \return DRXStatus_t. +* \return int. * \retval DRX_STS_OK Success * \retval DRX_STS_ERROR Failure: I2C error * */ -static DRXStatus_t ADCSyncMeasurement(pDRXDemodInstance_t demod, u16 *count) +static int ADCSyncMeasurement(pDRXDemodInstance_t demod, u16 *count) { u16 data = 0; struct i2c_device_addr *devAddr = NULL; @@ -4266,7 +4266,7 @@ rw_error: /** * \brief Synchronize analog and digital clock domains * \param demod demod instance -* \return DRXStatus_t. +* \return int. * \retval DRX_STS_OK Success * \retval DRX_STS_ERROR Failure: I2C error or failure to synchronize * @@ -4275,7 +4275,7 @@ rw_error: * */ -static DRXStatus_t ADCSynchronization(pDRXDemodInstance_t demod) +static int ADCSynchronization(pDRXDemodInstance_t demod) { u16 count = 0; struct i2c_device_addr *devAddr = NULL; @@ -4310,9 +4310,9 @@ rw_error: * \brief Configure IQM AF registers * \param demod instance of demodulator. * \param active -* \return DRXStatus_t. +* \return int. */ -static DRXStatus_t IQMSetAf(pDRXDemodInstance_t demod, bool active) +static int IQMSetAf(pDRXDemodInstance_t demod, bool active) { u16 data = 0; struct i2c_device_addr *devAddr = NULL; @@ -4346,16 +4346,16 @@ rw_error: } /* -------------------------------------------------------------------------- */ -static DRXStatus_t +static int CtrlSetCfgATVOutput(pDRXDemodInstance_t demod, pDRXJCfgAtvOutput_t outputCfg); /** * \brief set configuration of pin-safe mode * \param demod instance of demodulator. * \param enable boolean; true: activate pin-safe mode, false: de-activate p.s.m. -* \return DRXStatus_t. +* \return int. */ -static DRXStatus_t +static int CtrlSetCfgPdrSafeMode(pDRXDemodInstance_t demod, bool * enable) { pDRXJData_t extAttr = (pDRXJData_t) NULL; @@ -4479,9 +4479,9 @@ rw_error: * \brief get configuration of pin-safe mode * \param demod instance of demodulator. * \param enable boolean indicating whether pin-safe mode is active -* \return DRXStatus_t. +* \return int. */ -static DRXStatus_t +static int CtrlGetCfgPdrSafeMode(pDRXDemodInstance_t demod, bool * enabled) { pDRXJData_t extAttr = (pDRXJData_t) NULL; @@ -4499,9 +4499,9 @@ CtrlGetCfgPdrSafeMode(pDRXDemodInstance_t demod, bool * enabled) /** * \brief Verifies whether microcode can be loaded. * \param demod Demodulator instance. -* \return DRXStatus_t. +* \return int. */ -static DRXStatus_t CtrlValidateUCode(pDRXDemodInstance_t demod) +static int CtrlValidateUCode(pDRXDemodInstance_t demod) { u32 mcDev, mcPatch; u16 verType; @@ -4543,13 +4543,13 @@ static DRXStatus_t CtrlValidateUCode(pDRXDemodInstance_t demod) /*============================================================================*/ /*============================================================================*/ /** -* \fn DRXStatus_t InitAGC () +* \fn int InitAGC () * \brief Initialize AGC for all standards. * \param demod instance of demodulator. * \param channel pointer to channel data. -* \return DRXStatus_t. +* \return int. */ -static DRXStatus_t InitAGC(pDRXDemodInstance_t demod) +static int InitAGC(pDRXDemodInstance_t demod) { struct i2c_device_addr *devAddr = NULL; pDRXCommonAttr_t commonAttr = NULL; @@ -4749,14 +4749,14 @@ rw_error: } /** -* \fn DRXStatus_t SetFrequency () +* \fn int SetFrequency () * \brief Set frequency shift. * \param demod instance of demodulator. * \param channel pointer to channel data. * \param tunerFreqOffset residual frequency from tuner. -* \return DRXStatus_t. +* \return int. */ -static DRXStatus_t +static int SetFrequency(pDRXDemodInstance_t demod, pDRXChannel_t channel, s32 tunerFreqOffset) { @@ -4851,11 +4851,11 @@ rw_error: } /** -* \fn DRXStatus_t GetSigStrength() +* \fn int GetSigStrength() * \brief Retrieve signal strength for VSB and QAM. * \param demod Pointer to demod instance * \param u16-t Pointer to signal strength data; range 0, .. , 100. -* \return DRXStatus_t. +* \return int. * \retval DRX_STS_OK sigStrength contains valid data. * \retval DRX_STS_INVALID_ARG sigStrength is NULL. * \retval DRX_STS_ERROR Erroneous data, sigStrength contains invalid data. @@ -4865,7 +4865,7 @@ rw_error: #define DRXJ_RFAGC_MAX 0x3fff #define DRXJ_RFAGC_MIN 0x800 -static DRXStatus_t GetSigStrength(pDRXDemodInstance_t demod, u16 *sigStrength) +static int GetSigStrength(pDRXDemodInstance_t demod, u16 *sigStrength) { u16 rfGain = 0; u16 ifGain = 0; @@ -4914,17 +4914,17 @@ rw_error: } /** -* \fn DRXStatus_t GetAccPktErr() +* \fn int GetAccPktErr() * \brief Retrieve signal strength for VSB and QAM. * \param demod Pointer to demod instance * \param packetErr Pointer to packet error -* \return DRXStatus_t. +* \return int. * \retval DRX_STS_OK sigStrength contains valid data. * \retval DRX_STS_INVALID_ARG sigStrength is NULL. * \retval DRX_STS_ERROR Erroneous data, sigStrength contains invalid data. */ #ifdef DRXJ_SIGNAL_ACCUM_ERR -static DRXStatus_t GetAccPktErr(pDRXDemodInstance_t demod, u16 *packetErr) +static int GetAccPktErr(pDRXDemodInstance_t demod, u16 *packetErr) { static u16 pktErr = 0; static u16 lastPktErr = 0; @@ -4958,14 +4958,14 @@ rw_error: #endif /** -* \fn DRXStatus_t ResetAccPktErr() +* \fn int ResetAccPktErr() * \brief Reset Accumulating packet error count. * \param demod Pointer to demod instance -* \return DRXStatus_t. +* \return int. * \retval DRX_STS_OK. * \retval DRX_STS_ERROR Erroneous data. */ -static DRXStatus_t CtrlSetCfgResetPktErr(pDRXDemodInstance_t demod) +static int CtrlSetCfgResetPktErr(pDRXDemodInstance_t demod) { #ifdef DRXJ_SIGNAL_ACCUM_ERR pDRXJData_t extAttr = NULL; @@ -4987,12 +4987,12 @@ rw_error: * \brief Get symbol rate offset in QAM & 8VSB mode * \return Error code */ -static DRXStatus_t GetSTRFreqOffset(pDRXDemodInstance_t demod, s32 *STRFreq) +static int GetSTRFreqOffset(pDRXDemodInstance_t demod, s32 *STRFreq) { u32 symbolFrequencyRatio = 0; u32 symbolNomFrequencyRatio = 0; - DRXStandard_t standard = DRX_STANDARD_UNKNOWN; + enum drx_standard standard = DRX_STANDARD_UNKNOWN; struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; @@ -5025,7 +5025,7 @@ rw_error: * \brief Get the value of CTLFreq in QAM & ATSC mode * \return Error code */ -static DRXStatus_t GetCTLFreqOffset(pDRXDemodInstance_t demod, s32 *CTLFreq) +static int GetCTLFreqOffset(pDRXDemodInstance_t demod, s32 *CTLFreq) { s32 samplingFrequency = 0; s32 currentFrequency = 0; @@ -5075,13 +5075,13 @@ rw_error: /*============================================================================*/ /** -* \fn DRXStatus_t SetAgcRf () +* \fn int SetAgcRf () * \brief Configure RF AGC * \param demod instance of demodulator. * \param agcSettings AGC configuration structure -* \return DRXStatus_t. +* \return int. */ -static DRXStatus_t +static int SetAgcRf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings, bool atomic) { struct i2c_device_addr *devAddr = NULL; @@ -5253,18 +5253,18 @@ rw_error: } /** -* \fn DRXStatus_t GetAgcRf () +* \fn int GetAgcRf () * \brief get configuration of RF AGC * \param demod instance of demodulator. * \param agcSettings AGC configuration structure -* \return DRXStatus_t. +* \return int. */ -static DRXStatus_t +static int GetAgcRf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings) { struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; - DRXStandard_t standard = DRX_STANDARD_UNKNOWN; + enum drx_standard standard = DRX_STANDARD_UNKNOWN; devAddr = demod->myI2CDevAddr; extAttr = (pDRXJData_t) demod->myExtAttr; @@ -5314,13 +5314,13 @@ rw_error: } /** -* \fn DRXStatus_t SetAgcIf () +* \fn int SetAgcIf () * \brief Configure If AGC * \param demod instance of demodulator. * \param agcSettings AGC configuration structure -* \return DRXStatus_t. +* \return int. */ -static DRXStatus_t +static int SetAgcIf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings, bool atomic) { struct i2c_device_addr *devAddr = NULL; @@ -5505,18 +5505,18 @@ rw_error: } /** -* \fn DRXStatus_t GetAgcIf () +* \fn int GetAgcIf () * \brief get configuration of If AGC * \param demod instance of demodulator. * \param agcSettings AGC configuration structure -* \return DRXStatus_t. +* \return int. */ -static DRXStatus_t +static int GetAgcIf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings) { struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; - DRXStandard_t standard = DRX_STANDARD_UNKNOWN; + enum drx_standard standard = DRX_STANDARD_UNKNOWN; devAddr = demod->myI2CDevAddr; extAttr = (pDRXJData_t) demod->myExtAttr; @@ -5567,13 +5567,13 @@ rw_error: } /** -* \fn DRXStatus_t SetIqmAf () +* \fn int SetIqmAf () * \brief Configure IQM AF registers * \param demod instance of demodulator. * \param active -* \return DRXStatus_t. +* \return int. */ -static DRXStatus_t SetIqmAf(pDRXDemodInstance_t demod, bool active) +static int SetIqmAf(pDRXDemodInstance_t demod, bool active) { u16 data = 0; struct i2c_device_addr *devAddr = NULL; @@ -5615,13 +5615,13 @@ rw_error: /*============================================================================*/ /** -* \fn DRXStatus_t PowerDownVSB () +* \fn int PowerDownVSB () * \brief Powr down QAM related blocks. * \param demod instance of demodulator. * \param channel pointer to channel data. -* \return DRXStatus_t. +* \return int. */ -static DRXStatus_t PowerDownVSB(pDRXDemodInstance_t demod, bool primary) +static int PowerDownVSB(pDRXDemodInstance_t demod, bool primary) { struct i2c_device_addr *devAddr = NULL; DRXJSCUCmd_t cmdSCU = { /* command */ 0, @@ -5671,12 +5671,12 @@ rw_error: } /** -* \fn DRXStatus_t SetVSBLeakNGain () +* \fn int SetVSBLeakNGain () * \brief Set ATSC demod. * \param demod instance of demodulator. -* \return DRXStatus_t. +* \return int. */ -static DRXStatus_t SetVSBLeakNGain(pDRXDemodInstance_t demod) +static int SetVSBLeakNGain(pDRXDemodInstance_t demod) { struct i2c_device_addr *devAddr = NULL; @@ -5880,13 +5880,13 @@ rw_error: } /** -* \fn DRXStatus_t SetVSB() +* \fn int SetVSB() * \brief Set 8VSB demod. * \param demod instance of demodulator. -* \return DRXStatus_t. +* \return int. * */ -static DRXStatus_t SetVSB(pDRXDemodInstance_t demod) +static int SetVSB(pDRXDemodInstance_t demod) { struct i2c_device_addr *devAddr = NULL; u16 cmdResult = 0; @@ -6105,7 +6105,7 @@ rw_error: * \brief Get the values of packet error in 8VSB mode * \return Error code */ -static DRXStatus_t GetVSBPostRSPckErr(struct i2c_device_addr *devAddr, u16 *pckErrs) +static int GetVSBPostRSPckErr(struct i2c_device_addr *devAddr, u16 *pckErrs) { u16 data = 0; u16 period = 0; @@ -6136,7 +6136,7 @@ rw_error: * \brief Get the values of ber in VSB mode * \return Error code */ -static DRXStatus_t GetVSBpostViterbiBer(struct i2c_device_addr *devAddr, u32 *ber) +static int GetVSBpostViterbiBer(struct i2c_device_addr *devAddr, u32 *ber) { u16 data = 0; u16 period = 0; @@ -6174,7 +6174,7 @@ rw_error: * \brief Get the values of ber in VSB mode * \return Error code */ -static DRXStatus_t GetVSBpreViterbiBer(struct i2c_device_addr *devAddr, u32 *ber) +static int GetVSBpreViterbiBer(struct i2c_device_addr *devAddr, u32 * ber) { u16 data = 0; @@ -6193,7 +6193,7 @@ rw_error: * \brief Get the values of ber in VSB mode * \return Error code */ -static DRXStatus_t GetVSBSymbErr(struct i2c_device_addr *devAddr, u32 *ser) +static int GetVSBSymbErr(struct i2c_device_addr *devAddr, u32 *ser) { u16 data = 0; u16 period = 0; @@ -6219,11 +6219,11 @@ rw_error: } /** -* \fn static DRXStatus_t GetVSBMER(struct i2c_device_addr * devAddr, u16 *mer) +* \fn static int GetVSBMER(struct i2c_device_addr *devAddr, u16 *mer) * \brief Get the values of MER * \return Error code */ -static DRXStatus_t GetVSBMER(struct i2c_device_addr *devAddr, u16 *mer) +static int GetVSBMER(struct i2c_device_addr *devAddr, u16 *mer) { u16 dataHi = 0; @@ -6238,14 +6238,14 @@ rw_error: /*============================================================================*/ /** -* \fn DRXStatus_t CtrlGetVSBConstel() +* \fn int CtrlGetVSBConstel() * \brief Retreive a VSB constellation point via I2C. * \param demod Pointer to demodulator instance. * \param complexNr Pointer to the structure in which to store the constellation point. -* \return DRXStatus_t. +* \return int. */ -static DRXStatus_t +static int CtrlGetVSBConstel(pDRXDemodInstance_t demod, pDRXComplex_t complexNr) { struct i2c_device_addr *devAddr = NULL; @@ -6304,13 +6304,13 @@ rw_error: /*============================================================================*/ /** -* \fn DRXStatus_t PowerDownQAM () +* \fn int PowerDownQAM () * \brief Powr down QAM related blocks. * \param demod instance of demodulator. * \param channel pointer to channel data. -* \return DRXStatus_t. +* \return int. */ -static DRXStatus_t PowerDownQAM(pDRXDemodInstance_t demod, bool primary) +static int PowerDownQAM(pDRXDemodInstance_t demod, bool primary) { DRXJSCUCmd_t cmdSCU = { /* command */ 0, /* parameterLen */ 0, @@ -6364,11 +6364,11 @@ rw_error: /*============================================================================*/ /** -* \fn DRXStatus_t SetQAMMeasurement () +* \fn int SetQAMMeasurement () * \brief Setup of the QAM Measuremnt intervals for signal quality * \param demod instance of demod. * \param constellation current constellation. -* \return DRXStatus_t. +* \return int. * * NOTE: * Take into account that for certain settings the errorcounters can overflow. @@ -6380,9 +6380,9 @@ rw_error: * */ #ifndef DRXJ_VSB_ONLY -static DRXStatus_t +static int SetQAMMeasurement(pDRXDemodInstance_t demod, - DRXConstellation_t constellation, u32 symbolRate) + enum drx_modulation constellation, u32 symbolRate) { struct i2c_device_addr *devAddr = NULL; /* device address for I2C writes */ pDRXJData_t extAttr = NULL; /* Global data container for DRXJ specif data */ @@ -6538,12 +6538,12 @@ rw_error: /*============================================================================*/ /** -* \fn DRXStatus_t SetQAM16 () +* \fn int SetQAM16 () * \brief QAM16 specific setup * \param demod instance of demod. -* \return DRXStatus_t. +* \return int. */ -static DRXStatus_t SetQAM16(pDRXDemodInstance_t demod) +static int SetQAM16(pDRXDemodInstance_t demod) { struct i2c_device_addr *devAddr = demod->myI2CDevAddr; const u8 qamDqQualFun[] = { @@ -6618,12 +6618,12 @@ rw_error: /*============================================================================*/ /** -* \fn DRXStatus_t SetQAM32 () +* \fn int SetQAM32 () * \brief QAM32 specific setup * \param demod instance of demod. -* \return DRXStatus_t. +* \return int. */ -static DRXStatus_t SetQAM32(pDRXDemodInstance_t demod) +static int SetQAM32(pDRXDemodInstance_t demod) { struct i2c_device_addr *devAddr = demod->myI2CDevAddr; const u8 qamDqQualFun[] = { @@ -6698,12 +6698,12 @@ rw_error: /*============================================================================*/ /** -* \fn DRXStatus_t SetQAM64 () +* \fn int SetQAM64 () * \brief QAM64 specific setup * \param demod instance of demod. -* \return DRXStatus_t. +* \return int. */ -static DRXStatus_t SetQAM64(pDRXDemodInstance_t demod) +static int SetQAM64(pDRXDemodInstance_t demod) { struct i2c_device_addr *devAddr = demod->myI2CDevAddr; const u8 qamDqQualFun[] = { /* this is hw reset value. no necessary to re-write */ @@ -6778,12 +6778,12 @@ rw_error: /*============================================================================*/ /** -* \fn DRXStatus_t SetQAM128 () +* \fn int SetQAM128 () * \brief QAM128 specific setup * \param demod: instance of demod. -* \return DRXStatus_t. +* \return int. */ -static DRXStatus_t SetQAM128(pDRXDemodInstance_t demod) +static int SetQAM128(pDRXDemodInstance_t demod) { struct i2c_device_addr *devAddr = demod->myI2CDevAddr; const u8 qamDqQualFun[] = { @@ -6858,12 +6858,12 @@ rw_error: /*============================================================================*/ /** -* \fn DRXStatus_t SetQAM256 () +* \fn int SetQAM256 () * \brief QAM256 specific setup * \param demod: instance of demod. -* \return DRXStatus_t. +* \return int. */ -static DRXStatus_t SetQAM256(pDRXDemodInstance_t demod) +static int SetQAM256(pDRXDemodInstance_t demod) { struct i2c_device_addr *devAddr = demod->myI2CDevAddr; const u8 qamDqQualFun[] = { @@ -6941,13 +6941,13 @@ rw_error: #define QAM_SET_OP_SPECTRUM 0X4 /** -* \fn DRXStatus_t SetQAM () +* \fn int SetQAM () * \brief Set QAM demod. * \param demod: instance of demod. * \param channel: pointer to channel data. -* \return DRXStatus_t. +* \return int. */ -static DRXStatus_t +static int SetQAM(pDRXDemodInstance_t demod, pDRXChannel_t channel, s32 tunerFreqOffset, u32 op) { @@ -7410,9 +7410,9 @@ rw_error: } /*============================================================================*/ -static DRXStatus_t +static int CtrlGetQAMSigQuality(pDRXDemodInstance_t demod, pDRXSigQuality_t sigQuality); -static DRXStatus_t qamFlipSpec(pDRXDemodInstance_t demod, pDRXChannel_t channel) +static int qamFlipSpec(pDRXDemodInstance_t demod, pDRXChannel_t channel) { u32 iqmFsRateOfs = 0; u32 iqmFsRateLo = 0; @@ -7500,15 +7500,15 @@ rw_error: #define SYNC_FLIPPED 0x2 #define SPEC_MIRRORED 0x4 /** -* \fn DRXStatus_t QAM64Auto () +* \fn int QAM64Auto () * \brief auto do sync pattern switching and mirroring. * \param demod: instance of demod. * \param channel: pointer to channel data. * \param tunerFreqOffset: tuner frequency offset. * \param lockStatus: pointer to lock status. -* \return DRXStatus_t. +* \return int. */ -static DRXStatus_t +static int QAM64Auto(pDRXDemodInstance_t demod, pDRXChannel_t channel, s32 tunerFreqOffset, pDRXLockStatus_t lockStatus) @@ -7614,15 +7614,15 @@ rw_error: } /** -* \fn DRXStatus_t QAM256Auto () +* \fn int QAM256Auto () * \brief auto do sync pattern switching and mirroring. * \param demod: instance of demod. * \param channel: pointer to channel data. * \param tunerFreqOffset: tuner frequency offset. * \param lockStatus: pointer to lock status. -* \return DRXStatus_t. +* \return int. */ -static DRXStatus_t +static int QAM256Auto(pDRXDemodInstance_t demod, pDRXChannel_t channel, s32 tunerFreqOffset, pDRXLockStatus_t lockStatus) @@ -7685,13 +7685,13 @@ rw_error: } /** -* \fn DRXStatus_t SetQAMChannel () +* \fn int SetQAMChannel () * \brief Set QAM channel according to the requested constellation. * \param demod: instance of demod. * \param channel: pointer to channel data. -* \return DRXStatus_t. +* \return int. */ -static DRXStatus_t +static int SetQAMChannel(pDRXDemodInstance_t demod, pDRXChannel_t channel, s32 tunerFreqOffset) { @@ -7841,7 +7841,7 @@ rw_error: * precondition: measurement period & measurement prescale must be set * */ -static DRXStatus_t +static int GetQAMRSErrCount(struct i2c_device_addr *devAddr, pDRXJRSErrors_t RSErrors) { u16 nrBitErrors = 0, @@ -7884,23 +7884,23 @@ rw_error: /*============================================================================*/ /** -* \fn DRXStatus_t CtrlGetQAMSigQuality() +* \fn int CtrlGetQAMSigQuality() * \brief Retreive QAM signal quality from device. * \param devmod Pointer to demodulator instance. * \param sigQuality Pointer to signal quality data. -* \return DRXStatus_t. +* \return int. * \retval DRX_STS_OK sigQuality contains valid data. * \retval DRX_STS_INVALID_ARG sigQuality is NULL. * \retval DRX_STS_ERROR Erroneous data, sigQuality contains invalid data. * Pre-condition: Device must be started and in lock. */ -static DRXStatus_t +static int CtrlGetQAMSigQuality(pDRXDemodInstance_t demod, pDRXSigQuality_t sigQuality) { struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; - DRXConstellation_t constellation = DRX_CONSTELLATION_UNKNOWN; + enum drx_modulation constellation = DRX_CONSTELLATION_UNKNOWN; DRXJRSErrors_t measuredRSErrors = { 0, 0, 0, 0, 0 }; u32 preBitErrRS = 0; /* pre RedSolomon Bit Error Rate */ @@ -8070,14 +8070,14 @@ rw_error: } /** -* \fn DRXStatus_t CtrlGetQAMConstel() +* \fn int CtrlGetQAMConstel() * \brief Retreive a QAM constellation point via I2C. * \param demod Pointer to demodulator instance. * \param complexNr Pointer to the structure in which to store the constellation point. -* \return DRXStatus_t. +* \return int. */ -static DRXStatus_t +static int CtrlGetQAMConstel(pDRXDemodInstance_t demod, pDRXComplex_t complexNr) { u16 fecOcOcrMode = 0; @@ -8222,10 +8222,10 @@ rw_error: * \brief Get array index for atv coef (extAttr->atvTopCoefX[index]) * \param standard * \param pointer to index -* \return DRXStatus_t. +* \return int. * */ -static DRXStatus_t AtvEquCoefIndex(DRXStandard_t standard, int *index) +static int AtvEquCoefIndex(enum drx_standard standard, int *index) { switch (standard) { case DRX_STANDARD_PAL_SECAM_BG: @@ -8260,14 +8260,14 @@ static DRXStatus_t AtvEquCoefIndex(DRXStandard_t standard, int *index) /* -------------------------------------------------------------------------- */ /** -* \fn DRXStatus_t AtvUpdateConfig () +* \fn int AtvUpdateConfig () * \brief Flush changes in ATV shadow registers to physical registers. * \param demod instance of demodulator * \param forceUpdate don't look at standard or change flags, flush all. -* \return DRXStatus_t. +* \return int. * */ -static DRXStatus_t +static int AtvUpdateConfig(pDRXDemodInstance_t demod, bool forceUpdate) { struct i2c_device_addr *devAddr = NULL; @@ -8368,14 +8368,14 @@ rw_error: /* -------------------------------------------------------------------------- */ /** -* \fn DRXStatus_t CtrlSetCfgATVOutput() +* \fn int CtrlSetCfgATVOutput() * \brief Configure ATV ouputs * \param demod instance of demodulator * \param outputCfg output configuaration -* \return DRXStatus_t. +* \return int. * */ -static DRXStatus_t +static int CtrlSetCfgATVOutput(pDRXDemodInstance_t demod, pDRXJCfgAtvOutput_t outputCfg) { pDRXJData_t extAttr = NULL; @@ -8425,14 +8425,14 @@ rw_error: /* -------------------------------------------------------------------------- */ #ifndef DRXJ_DIGITAL_ONLY /** -* \fn DRXStatus_t CtrlSetCfgAtvEquCoef() +* \fn int CtrlSetCfgAtvEquCoef() * \brief Set ATV equalizer coefficients * \param demod instance of demodulator * \param coef the equalizer coefficients -* \return DRXStatus_t. +* \return int. * */ -static DRXStatus_t +static int CtrlSetCfgAtvEquCoef(pDRXDemodInstance_t demod, pDRXJCfgAtvEquCoef_t coef) { pDRXJData_t extAttr = NULL; @@ -8474,11 +8474,11 @@ rw_error: /* -------------------------------------------------------------------------- */ /** -* \fn DRXStatus_t CtrlGetCfgAtvEquCoef() +* \fn int CtrlGetCfgAtvEquCoef() * \brief Get ATV equ coef settings * \param demod instance of demodulator * \param coef The ATV equ coefficients -* \return DRXStatus_t. +* \return int. * * The values are read from the shadow registers maintained by the drxdriver * If registers are manipulated outside of the drxdriver scope the reported @@ -8486,7 +8486,7 @@ rw_error: * regitsers. * */ -static DRXStatus_t +static int CtrlGetCfgAtvEquCoef(pDRXDemodInstance_t demod, pDRXJCfgAtvEquCoef_t coef) { pDRXJData_t extAttr = NULL; @@ -8517,14 +8517,14 @@ rw_error: /* -------------------------------------------------------------------------- */ /** -* \fn DRXStatus_t CtrlSetCfgAtvMisc() +* \fn int CtrlSetCfgAtvMisc() * \brief Set misc. settings for ATV. * \param demod instance of demodulator * \param -* \return DRXStatus_t. +* \return int. * */ -static DRXStatus_t +static int CtrlSetCfgAtvMisc(pDRXDemodInstance_t demod, pDRXJCfgAtvMisc_t settings) { pDRXJData_t extAttr = NULL; @@ -8558,18 +8558,18 @@ rw_error: /* -------------------------------------------------------------------------- */ /** -* \fn DRXStatus_t CtrlGetCfgAtvMisc() +* \fn int CtrlGetCfgAtvMisc() * \brief Get misc settings of ATV. * \param demod instance of demodulator * \param settings misc. ATV settings -* \return DRXStatus_t. +* \return int. * * The values are read from the shadow registers maintained by the drxdriver * If registers are manipulated outside of the drxdriver scope the reported * settings will not reflect these changes because of the use of shadow * regitsers. */ -static DRXStatus_t +static int CtrlGetCfgAtvMisc(pDRXDemodInstance_t demod, pDRXJCfgAtvMisc_t settings) { pDRXJData_t extAttr = NULL; @@ -8591,14 +8591,14 @@ CtrlGetCfgAtvMisc(pDRXDemodInstance_t demod, pDRXJCfgAtvMisc_t settings) /* -------------------------------------------------------------------------- */ /** -* \fn DRXStatus_t CtrlGetCfgAtvOutput() +* \fn int CtrlGetCfgAtvOutput() * \brief * \param demod instance of demodulator * \param outputCfg output configuaration -* \return DRXStatus_t. +* \return int. * */ -static DRXStatus_t +static int CtrlGetCfgAtvOutput(pDRXDemodInstance_t demod, pDRXJCfgAtvOutput_t outputCfg) { u16 data = 0; @@ -8630,14 +8630,14 @@ rw_error: /* -------------------------------------------------------------------------- */ /** -* \fn DRXStatus_t CtrlGetCfgAtvAgcStatus() +* \fn int CtrlGetCfgAtvAgcStatus() * \brief * \param demod instance of demodulator * \param agcStatus agc status -* \return DRXStatus_t. +* \return int. * */ -static DRXStatus_t +static int CtrlGetCfgAtvAgcStatus(pDRXDemodInstance_t demod, pDRXJCfgAtvAgcStatus_t agcStatus) { @@ -8733,16 +8733,16 @@ rw_error: /* -------------------------------------------------------------------------- */ /** -* \fn DRXStatus_t PowerUpATV () +* \fn int PowerUpATV () * \brief Power up ATV. * \param demod instance of demodulator * \param standard either NTSC or FM (sub strandard for ATV ) -* \return DRXStatus_t. +* \return int. * * * Starts ATV and IQM * * AUdio already started during standard init for ATV. */ -static DRXStatus_t PowerUpATV(pDRXDemodInstance_t demod, DRXStandard_t standard) +static int PowerUpATV(pDRXDemodInstance_t demod, enum drx_standard standard) { struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; @@ -8769,18 +8769,18 @@ rw_error: /* -------------------------------------------------------------------------- */ /** -* \fn DRXStatus_t PowerDownATV () +* \fn int PowerDownATV () * \brief Power down ATV. * \param demod instance of demodulator * \param standard either NTSC or FM (sub strandard for ATV ) -* \return DRXStatus_t. +* \return int. * * Stops and thus resets ATV and IQM block * SIF and CVBS ADC are powered down * Calls audio power down */ -static DRXStatus_t -PowerDownATV(pDRXDemodInstance_t demod, DRXStandard_t standard, bool primary) +static int +PowerDownATV(pDRXDemodInstance_t demod, enum drx_standard standard, bool primary) { struct i2c_device_addr *devAddr = NULL; DRXJSCUCmd_t cmdSCU = { /* command */ 0, @@ -8828,11 +8828,11 @@ rw_error: /* -------------------------------------------------------------------------- */ /** -* \fn DRXStatus_t SetATVStandard () +* \fn int SetATVStandard () * \brief Set up ATV demodulator. * \param demod instance of demodulator * \param standard either NTSC or FM (sub strandard for ATV ) -* \return DRXStatus_t. +* \return int. * * Init all channel independent registers. * Assuming that IQM, ATV and AUD blocks have been reset and are in STOP mode @@ -8840,8 +8840,8 @@ rw_error: */ #ifndef DRXJ_DIGITAL_ONLY #define SCU_RAM_ATV_ENABLE_IIR_WA__A 0x831F6D /* TODO remove after done with reg import */ -static DRXStatus_t -SetATVStandard(pDRXDemodInstance_t demod, pDRXStandard_t standard) +static int +SetATVStandard(pDRXDemodInstance_t demod, enum drx_standard * standard) { /* TODO: enable alternative for tap settings via external file @@ -9444,10 +9444,10 @@ rw_error: #ifndef DRXJ_DIGITAL_ONLY /** -* \fn DRXStatus_t SetATVChannel () +* \fn int SetATVChannel () * \brief Set ATV channel. * \param demod: instance of demod. -* \return DRXStatus_t. +* \return int. * * Not much needs to be done here, only start the SCU for NTSC/FM. * Mirrored channels are not expected in the RF domain, so IQM FS setting @@ -9455,10 +9455,10 @@ rw_error: * The channel->mirror parameter is therefor ignored. * */ -static DRXStatus_t +static int SetATVChannel(pDRXDemodInstance_t demod, s32 tunerFreqOffset, - pDRXChannel_t channel, DRXStandard_t standard) + pDRXChannel_t channel, enum drx_standard standard) { DRXJSCUCmd_t cmdSCU = { /* command */ 0, /* parameterLen */ 0, @@ -9509,12 +9509,12 @@ rw_error: /* -------------------------------------------------------------------------- */ /** -* \fn DRXStatus_t GetATVChannel () +* \fn int GetATVChannel () * \brief Set ATV channel. * \param demod: instance of demod. * \param channel: pointer to channel data. * \param standard: NTSC or FM. -* \return DRXStatus_t. +* \return int. * * Covers NTSC, PAL/SECAM - B/G, D/K, I, L, LP and FM. * Computes the frequency offset in te RF domain and adds it to @@ -9522,9 +9522,9 @@ rw_error: * */ #ifndef DRXJ_DIGITAL_ONLY -static DRXStatus_t +static int GetATVChannel(pDRXDemodInstance_t demod, - pDRXChannel_t channel, DRXStandard_t standard) + pDRXChannel_t channel, enum drx_standard standard) { s32 offset = 0; struct i2c_device_addr *devAddr = NULL; @@ -9591,11 +9591,11 @@ rw_error: /* -------------------------------------------------------------------------- */ /** -* \fn DRXStatus_t GetAtvSigStrength() +* \fn int GetAtvSigStrength() * \brief Retrieve signal strength for ATV & FM. * \param devmod Pointer to demodulator instance. * \param sigQuality Pointer to signal strength data; range 0, .. , 100. -* \return DRXStatus_t. +* \return int. * \retval DRX_STS_OK sigStrength contains valid data. * \retval DRX_STS_ERROR Erroneous data, sigStrength equals 0. * @@ -9609,7 +9609,7 @@ rw_error: * TODO: ? dynamically adapt weights in case RF and/or IF agc of drxj * is not used ? */ -static DRXStatus_t +static int GetAtvSigStrength(pDRXDemodInstance_t demod, u16 *sigStrength) { struct i2c_device_addr *devAddr = NULL; @@ -9708,17 +9708,17 @@ rw_error: /* -------------------------------------------------------------------------- */ /** -* \fn DRXStatus_t AtvSigQuality() +* \fn int AtvSigQuality() * \brief Retrieve signal quality indication for ATV. * \param devmod Pointer to demodulator instance. * \param sigQuality Pointer to signal quality structure. -* \return DRXStatus_t. +* \return int. * \retval DRX_STS_OK sigQuality contains valid data. * \retval DRX_STS_ERROR Erroneous data, sigQuality indicator equals 0. * * */ -static DRXStatus_t +static int AtvSigQuality(pDRXDemodInstance_t demod, pDRXSigQuality_t sigQuality) { struct i2c_device_addr *devAddr = NULL; @@ -9774,10 +9774,10 @@ rw_error: /* * \brief Power up AUD. * \param demod instance of demodulator -* \return DRXStatus_t. +* \return int. * */ -static DRXStatus_t PowerUpAud(pDRXDemodInstance_t demod, bool setStandard) +static int PowerUpAud(pDRXDemodInstance_t demod, bool setStandard) { DRXAudStandard_t audStandard = DRX_AUD_STANDARD_AUTO; struct i2c_device_addr *devAddr = NULL; @@ -9803,10 +9803,10 @@ rw_error: /** * \brief Power up AUD. * \param demod instance of demodulator -* \return DRXStatus_t. +* \return int. * */ -static DRXStatus_t PowerDownAud(pDRXDemodInstance_t demod) +static int PowerDownAud(pDRXDemodInstance_t demod) { struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; @@ -9828,10 +9828,10 @@ rw_error: * \brief Get Modus data from audio RAM * \param demod instance of demodulator * \param pointer to modus -* \return DRXStatus_t. +* \return int. * */ -static DRXStatus_t AUDGetModus(pDRXDemodInstance_t demod, u16 *modus) +static int AUDGetModus(pDRXDemodInstance_t demod, u16 *modus) { struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; @@ -9873,10 +9873,10 @@ rw_error: * \brief Get audio RDS dat * \param demod instance of demodulator * \param pointer to DRXCfgAudRDS_t -* \return DRXStatus_t. +* \return int. * */ -static DRXStatus_t +static int AUDCtrlGetCfgRDS(pDRXDemodInstance_t demod, pDRXCfgAudRDS_t status) { struct i2c_device_addr *addr = NULL; @@ -9943,10 +9943,10 @@ rw_error: * \brief Get the current audio carrier detection status * \param demod instance of demodulator * \param pointer to AUDCtrlGetStatus -* \return DRXStatus_t. +* \return int. * */ -static DRXStatus_t +static int AUDCtrlGetCarrierDetectStatus(pDRXDemodInstance_t demod, pDRXAudStatus_t status) { pDRXJData_t extAttr = NULL; @@ -10021,10 +10021,10 @@ rw_error: * \brief Get the current audio status parameters * \param demod instance of demodulator * \param pointer to AUDCtrlGetStatus -* \return DRXStatus_t. +* \return int. * */ -static DRXStatus_t +static int AUDCtrlGetStatus(pDRXDemodInstance_t demod, pDRXAudStatus_t status) { pDRXJData_t extAttr = NULL; @@ -10062,10 +10062,10 @@ rw_error: * \brief Get the current volume settings * \param demod instance of demodulator * \param pointer to DRXCfgAudVolume_t -* \return DRXStatus_t. +* \return int. * */ -static DRXStatus_t +static int AUDCtrlGetCfgVolume(pDRXDemodInstance_t demod, pDRXCfgAudVolume_t volume) { struct i2c_device_addr *devAddr = NULL; @@ -10196,10 +10196,10 @@ rw_error: * \brief Set the current volume settings * \param demod instance of demodulator * \param pointer to DRXCfgAudVolume_t -* \return DRXStatus_t. +* \return int. * */ -static DRXStatus_t +static int AUDCtrlSetCfgVolume(pDRXDemodInstance_t demod, pDRXCfgAudVolume_t volume) { struct i2c_device_addr *devAddr = NULL; @@ -10331,10 +10331,10 @@ rw_error: * \brief Get the I2S settings * \param demod instance of demodulator * \param pointer to DRXCfgI2SOutput_t -* \return DRXStatus_t. +* \return int. * */ -static DRXStatus_t +static int AUDCtrlGetCfgOutputI2S(pDRXDemodInstance_t demod, pDRXCfgI2SOutput_t output) { struct i2c_device_addr *devAddr = NULL; @@ -10434,10 +10434,10 @@ rw_error: * \brief Set the I2S settings * \param demod instance of demodulator * \param pointer to DRXCfgI2SOutput_t -* \return DRXStatus_t. +* \return int. * */ -static DRXStatus_t +static int AUDCtrlSetCfgOutputI2S(pDRXDemodInstance_t demod, pDRXCfgI2SOutput_t output) { struct i2c_device_addr *devAddr = NULL; @@ -10589,10 +10589,10 @@ rw_error: * and Automatic Sound Change (ASC) * \param demod instance of demodulator * \param pointer to pDRXAudAutoSound_t -* \return DRXStatus_t. +* \return int. * */ -static DRXStatus_t +static int AUDCtrlGetCfgAutoSound(pDRXDemodInstance_t demod, pDRXCfgAudAutoSound_t autoSound) { @@ -10646,10 +10646,10 @@ rw_error: * and Automatic Sound Change (ASC) * \param demod instance of demodulator * \param pointer to pDRXAudAutoSound_t -* \return DRXStatus_t. +* \return int. * */ -static DRXStatus_t +static int AUDCtrSetlCfgAutoSound(pDRXDemodInstance_t demod, pDRXCfgAudAutoSound_t autoSound) { @@ -10712,10 +10712,10 @@ rw_error: * \brief Get the Automatic Standard Select thresholds * \param demod instance of demodulator * \param pointer to pDRXAudASSThres_t -* \return DRXStatus_t. +* \return int. * */ -static DRXStatus_t +static int AUDCtrlGetCfgASSThres(pDRXDemodInstance_t demod, pDRXCfgAudASSThres_t thres) { struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; @@ -10756,10 +10756,10 @@ rw_error: * \brief Get the Automatic Standard Select thresholds * \param demod instance of demodulator * \param pointer to pDRXAudASSThres_t -* \return DRXStatus_t. +* \return int. * */ -static DRXStatus_t +static int AUDCtrlSetCfgASSThres(pDRXDemodInstance_t demod, pDRXCfgAudASSThres_t thres) { struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; @@ -10795,10 +10795,10 @@ rw_error: * \brief Get Audio Carrier settings * \param demod instance of demodulator * \param pointer to pDRXAudCarrier_t -* \return DRXStatus_t. +* \return int. * */ -static DRXStatus_t +static int AUDCtrlGetCfgCarrier(pDRXDemodInstance_t demod, pDRXCfgAudCarriers_t carriers) { struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; @@ -10900,10 +10900,10 @@ rw_error: * \brief Set Audio Carrier settings * \param demod instance of demodulator * \param pointer to pDRXAudCarrier_t -* \return DRXStatus_t. +* \return int. * */ -static DRXStatus_t +static int AUDCtrlSetCfgCarrier(pDRXDemodInstance_t demod, pDRXCfgAudCarriers_t carriers) { struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; @@ -11000,10 +11000,10 @@ rw_error: * \brief Get I2S Source, I2S matrix and FM matrix * \param demod instance of demodulator * \param pointer to pDRXAudmixer_t -* \return DRXStatus_t. +* \return int. * */ -static DRXStatus_t +static int AUDCtrlGetCfgMixer(pDRXDemodInstance_t demod, pDRXCfgAudMixer_t mixer) { struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; @@ -11095,10 +11095,10 @@ rw_error: * \brief Set I2S Source, I2S matrix and FM matrix * \param demod instance of demodulator * \param pointer to DRXAudmixer_t -* \return DRXStatus_t. +* \return int. * */ -static DRXStatus_t +static int AUDCtrlSetCfgMixer(pDRXDemodInstance_t demod, pDRXCfgAudMixer_t mixer) { struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; @@ -11203,10 +11203,10 @@ rw_error: * \brief Set AV Sync settings * \param demod instance of demodulator * \param pointer to DRXICfgAVSync_t -* \return DRXStatus_t. +* \return int. * */ -static DRXStatus_t +static int AUDCtrlSetCfgAVSync(pDRXDemodInstance_t demod, pDRXCfgAudAVSync_t avSync) { struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; @@ -11268,10 +11268,10 @@ rw_error: * \brief Get AV Sync settings * \param demod instance of demodulator * \param pointer to DRXICfgAVSync_t -* \return DRXStatus_t. +* \return int. * */ -static DRXStatus_t +static int AUDCtrlGetCfgAVSync(pDRXDemodInstance_t demod, pDRXCfgAudAVSync_t avSync) { struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; @@ -11325,10 +11325,10 @@ rw_error: * \brief Get deviation mode * \param demod instance of demodulator * \param pointer to DRXCfgAudDeviation_t -* \return DRXStatus_t. +* \return int. * */ -static DRXStatus_t +static int AUDCtrlGetCfgDev(pDRXDemodInstance_t demod, pDRXCfgAudDeviation_t dev) { struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; @@ -11366,10 +11366,10 @@ rw_error: * \brief Get deviation mode * \param demod instance of demodulator * \param pointer to DRXCfgAudDeviation_t -* \return DRXStatus_t. +* \return int. * */ -static DRXStatus_t +static int AUDCtrlSetCfgDev(pDRXDemodInstance_t demod, pDRXCfgAudDeviation_t dev) { struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; @@ -11419,10 +11419,10 @@ rw_error: * \brief Get Prescaler settings * \param demod instance of demodulator * \param pointer to DRXCfgAudPrescale_t -* \return DRXStatus_t. +* \return int. * */ -static DRXStatus_t +static int AUDCtrlGetCfgPrescale(pDRXDemodInstance_t demod, pDRXCfgAudPrescale_t presc) { struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; @@ -11494,10 +11494,10 @@ rw_error: * \brief Set Prescaler settings * \param demod instance of demodulator * \param pointer to DRXCfgAudPrescale_t -* \return DRXStatus_t. +* \return int. * */ -static DRXStatus_t +static int AUDCtrlSetCfgPrescale(pDRXDemodInstance_t demod, pDRXCfgAudPrescale_t presc) { struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; @@ -11577,10 +11577,10 @@ rw_error: * \brief Beep * \param demod instance of demodulator * \param pointer to DRXAudBeep_t -* \return DRXStatus_t. +* \return int. * */ -static DRXStatus_t AUDCtrlBeep(pDRXDemodInstance_t demod, pDRXAudBeep_t beep) +static int AUDCtrlBeep(pDRXDemodInstance_t demod, pDRXAudBeep_t beep) { struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; pDRXJData_t extAttr = (pDRXJData_t) NULL; @@ -11635,15 +11635,15 @@ rw_error: * \brief Set an audio standard * \param demod instance of demodulator * \param pointer to DRXAudStandard_t -* \return DRXStatus_t. +* \return int. * */ -static DRXStatus_t +static int AUDCtrlSetStandard(pDRXDemodInstance_t demod, pDRXAudStandard_t standard) { struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; - DRXStandard_t currentStandard = DRX_STANDARD_UNKNOWN; + enum drx_standard currentStandard = DRX_STANDARD_UNKNOWN; u16 wStandard = 0; u16 wModus = 0; @@ -11813,10 +11813,10 @@ rw_error: * \brief Get the current audio standard * \param demod instance of demodulator * \param pointer to DRXAudStandard_t -* \return DRXStatus_t. +* \return int. * */ -static DRXStatus_t +static int AUDCtrlGetStandard(pDRXDemodInstance_t demod, pDRXAudStandard_t standard) { struct i2c_device_addr *devAddr = NULL; @@ -11920,10 +11920,10 @@ rw_error: * \brief Retreive lock status in case of FM standard * \param demod instance of demodulator * \param pointer to lock status -* \return DRXStatus_t. +* \return int. * */ -static DRXStatus_t +static int FmLockStatus(pDRXDemodInstance_t demod, pDRXLockStatus_t lockStat) { DRXAudStatus_t status; @@ -11949,13 +11949,13 @@ rw_error: * \brief retreive signal quality in case of FM standard * \param demod instance of demodulator * \param pointer to signal quality -* \return DRXStatus_t. +* \return int. * * Only the quality indicator field is will be supplied. * This will either be 0% or 100%, nothing in between. * */ -static DRXStatus_t +static int FmSigQuality(pDRXDemodInstance_t demod, pDRXSigQuality_t sigQuality) { DRXLockStatus_t lockStatus = DRX_NOT_LOCKED; @@ -11986,16 +11986,16 @@ rw_error: /*============================================================================*/ #ifndef DRXJ_DIGITAL_ONLY /** -* \fn DRXStatus_t GetOOBLockStatus () +* \fn int GetOOBLockStatus () * \brief Get OOB lock status. * \param devAddr I2C address \ oobLock OOB lock status. -* \return DRXStatus_t. +* \return int. * * Gets OOB lock status * */ -static DRXStatus_t +static int GetOOBLockStatus(pDRXDemodInstance_t demod, struct i2c_device_addr *devAddr, pDRXLockStatus_t oobLock) { @@ -12041,16 +12041,16 @@ rw_error: } /** -* \fn DRXStatus_t GetOOBSymbolRateOffset () +* \fn int GetOOBSymbolRateOffset () * \brief Get OOB Symbol rate offset. Unit is [ppm] * \param devAddr I2C address * \ Symbol Rate Offset OOB parameter. -* \return DRXStatus_t. +* \return int. * * Gets OOB frequency offset * */ -static DRXStatus_t +static int GetOOBSymbolRateOffset(struct i2c_device_addr *devAddr, s32 *SymbolRateOffset) { /* offset = -{(timingOffset/2^19)*(symbolRate/12,656250MHz)}*10^6 [ppm] */ @@ -12122,16 +12122,16 @@ rw_error: } /** -* \fn DRXStatus_t GetOOBFreqOffset () +* \fn int GetOOBFreqOffset () * \brief Get OOB lock status. * \param devAddr I2C address * \ freqOffset OOB frequency offset. -* \return DRXStatus_t. +* \return int. * * Gets OOB frequency offset * */ -static DRXStatus_t +static int GetOOBFreqOffset(pDRXDemodInstance_t demod, s32 *freqOffset) { u16 data = 0; @@ -12223,16 +12223,16 @@ rw_error: } /** -* \fn DRXStatus_t GetOOBFrequency () +* \fn int GetOOBFrequency () * \brief Get OOB frequency (Unit:KHz). * \param devAddr I2C address * \ frequency OOB frequency parameters. -* \return DRXStatus_t. +* \return int. * * Gets OOB frequency * */ -static DRXStatus_t +static int GetOOBFrequency(pDRXDemodInstance_t demod, s32 *frequency) { u16 data = 0; @@ -12258,16 +12258,16 @@ rw_error: } /** -* \fn DRXStatus_t GetOOBMER () +* \fn int GetOOBMER () * \brief Get OOB MER. * \param devAddr I2C address \ MER OOB parameter in dB. -* \return DRXStatus_t. +* \return int. * * Gets OOB MER. Table for MER is in Programming guide. * */ -static DRXStatus_t GetOOBMER(struct i2c_device_addr *devAddr, u32 *mer) +static int GetOOBMER(struct i2c_device_addr *devAddr, u32 *mer) { u16 data = 0; @@ -12402,13 +12402,13 @@ rw_error: #endif /*#ifndef DRXJ_DIGITAL_ONLY */ /** -* \fn DRXStatus_t SetOrxNsuAox() +* \fn int SetOrxNsuAox() * \brief Configure OrxNsuAox for OOB * \param demod instance of demodulator. * \param active -* \return DRXStatus_t. +* \return int. */ -static DRXStatus_t SetOrxNsuAox(pDRXDemodInstance_t demod, bool active) +static int SetOrxNsuAox(pDRXDemodInstance_t demod, bool active) { u16 data = 0; struct i2c_device_addr *devAddr = NULL; @@ -12448,12 +12448,12 @@ rw_error: } /** -* \fn DRXStatus_t CtrlSetOOB() +* \fn int CtrlSetOOB() * \brief Set OOB channel to be used. * \param demod instance of demodulator * \param oobParam OOB parameters for channel setting. * \frequency should be in KHz -* \return DRXStatus_t. +* \return int. * * Accepts only. Returns error otherwise. * Demapper value is written after SCUCommand START @@ -12471,7 +12471,7 @@ rw_error: /* Coefficients for the nyquist fitler (total: 27 taps) */ #define NYQFILTERLEN 27 -static DRXStatus_t CtrlSetOOB(pDRXDemodInstance_t demod, pDRXOOB_t oobParam) +static int CtrlSetOOB(pDRXDemodInstance_t demod, pDRXOOB_t oobParam) { #ifndef DRXJ_DIGITAL_ONLY DRXOOBDownstreamStandard_t standard = DRX_OOB_MODE_A; @@ -12740,13 +12740,13 @@ rw_error: } /** -* \fn DRXStatus_t CtrlGetOOB() +* \fn int CtrlGetOOB() * \brief Set modulation standard to be used. * \param demod instance of demodulator * \param oobStatus OOB status parameters. -* \return DRXStatus_t. +* \return int. */ -static DRXStatus_t +static int CtrlGetOOB(pDRXDemodInstance_t demod, pDRXOOBStatus_t oobStatus) { #ifndef DRXJ_DIGITAL_ONLY @@ -12784,13 +12784,13 @@ rw_error: } /** -* \fn DRXStatus_t CtrlSetCfgOOBPreSAW() +* \fn int CtrlSetCfgOOBPreSAW() * \brief Configure PreSAW treshold value * \param cfgData Pointer to configuration parameter * \return Error code */ #ifndef DRXJ_DIGITAL_ONLY -static DRXStatus_t +static int CtrlSetCfgOOBPreSAW(pDRXDemodInstance_t demod, u16 *cfgData) { struct i2c_device_addr *devAddr = NULL; @@ -12811,13 +12811,13 @@ rw_error: #endif /** -* \fn DRXStatus_t CtrlGetCfgOOBPreSAW() +* \fn int CtrlGetCfgOOBPreSAW() * \brief Configure PreSAW treshold value * \param cfgData Pointer to configuration parameter * \return Error code */ #ifndef DRXJ_DIGITAL_ONLY -static DRXStatus_t +static int CtrlGetCfgOOBPreSAW(pDRXDemodInstance_t demod, u16 *cfgData) { pDRXJData_t extAttr = NULL; @@ -12834,13 +12834,13 @@ CtrlGetCfgOOBPreSAW(pDRXDemodInstance_t demod, u16 *cfgData) #endif /** -* \fn DRXStatus_t CtrlSetCfgOOBLoPower() +* \fn int CtrlSetCfgOOBLoPower() * \brief Configure LO Power value * \param cfgData Pointer to pDRXJCfgOobLoPower_t * \return Error code */ #ifndef DRXJ_DIGITAL_ONLY -static DRXStatus_t +static int CtrlSetCfgOOBLoPower(pDRXDemodInstance_t demod, pDRXJCfgOobLoPower_t cfgData) { struct i2c_device_addr *devAddr = NULL; @@ -12861,13 +12861,13 @@ rw_error: #endif /** -* \fn DRXStatus_t CtrlGetCfgOOBLoPower() +* \fn int CtrlGetCfgOOBLoPower() * \brief Configure LO Power value * \param cfgData Pointer to pDRXJCfgOobLoPower_t * \return Error code */ #ifndef DRXJ_DIGITAL_ONLY -static DRXStatus_t +static int CtrlGetCfgOOBLoPower(pDRXDemodInstance_t demod, pDRXJCfgOobLoPower_t cfgData) { pDRXJData_t extAttr = NULL; @@ -12894,17 +12894,17 @@ CtrlGetCfgOOBLoPower(pDRXDemodInstance_t demod, pDRXJCfgOobLoPower_t cfgData) ===== CtrlSetChannel() ========================================================== ===========================================================================*/ /** -* \fn DRXStatus_t CtrlSetChannel() +* \fn int CtrlSetChannel() * \brief Select a new transmission channel. * \param demod instance of demod. * \param channel Pointer to channel data. -* \return DRXStatus_t. +* \return int. * * In case the tuner module is not used and in case of NTSC/FM the pogrammer * must tune the tuner to the centre frequency of the NTSC/FM channel. * */ -static DRXStatus_t +static int CtrlSetChannel(pDRXDemodInstance_t demod, pDRXChannel_t channel) { @@ -12914,8 +12914,8 @@ CtrlSetChannel(pDRXDemodInstance_t demod, pDRXChannel_t channel) s32 intermediateFreq = 0; pDRXJData_t extAttr = NULL; struct i2c_device_addr *devAddr = NULL; - DRXStandard_t standard = DRX_STANDARD_UNKNOWN; - TUNERMode_t tunerMode = 0; + enum drx_standard standard = DRX_STANDARD_UNKNOWN; + u32 tunerMode = 0; pDRXCommonAttr_t commonAttr = NULL; bool bridgeClosed = false; #ifndef DRXJ_VSB_ONLY @@ -13280,19 +13280,19 @@ rw_error: ===== CtrlGetChannel() ========================================================== ===========================================================================*/ /** -* \fn DRXStatus_t CtrlGetChannel() +* \fn int CtrlGetChannel() * \brief Retreive parameters of current transmission channel. * \param demod Pointer to demod instance. * \param channel Pointer to channel data. -* \return DRXStatus_t. +* \return int. */ -static DRXStatus_t +static int CtrlGetChannel(pDRXDemodInstance_t demod, pDRXChannel_t channel) { struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; DRXLockStatus_t lockStatus = DRX_NOT_LOCKED; - DRXStandard_t standard = DRX_STANDARD_UNKNOWN; + enum drx_standard standard = DRX_STANDARD_UNKNOWN; pDRXCommonAttr_t commonAttr = NULL; s32 intermediateFreq = 0; s32 CTLFreqOffset = 0; @@ -13436,7 +13436,7 @@ CtrlGetChannel(pDRXDemodInstance_t demod, pDRXChannel_t channel) CHK_ERROR(SCUCommand(devAddr, &cmdSCU)); channel->interleavemode = - (DRXInterleaveModes_t) (cmdSCU. + (enum drx_interleave_mode) (cmdSCU. result[2]); } @@ -13527,22 +13527,22 @@ mer2indicator(u16 mer, u16 minMer, u16 thresholdMer, u16 maxMer) } /** -* \fn DRXStatus_t CtrlSigQuality() +* \fn int CtrlSigQuality() * \brief Retreive signal quality form device. * \param devmod Pointer to demodulator instance. * \param sigQuality Pointer to signal quality data. -* \return DRXStatus_t. +* \return int. * \retval DRX_STS_OK sigQuality contains valid data. * \retval DRX_STS_INVALID_ARG sigQuality is NULL. * \retval DRX_STS_ERROR Erroneous data, sigQuality contains invalid data. */ -static DRXStatus_t +static int CtrlSigQuality(pDRXDemodInstance_t demod, pDRXSigQuality_t sigQuality) { struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; - DRXStandard_t standard = DRX_STANDARD_UNKNOWN; + enum drx_standard standard = DRX_STANDARD_UNKNOWN; DRXLockStatus_t lockStatus = DRX_NOT_LOCKED; u16 minMer = 0; u16 maxMer = 0; @@ -13664,17 +13664,17 @@ rw_error: /*============================================================================*/ /** -* \fn DRXStatus_t CtrlLockStatus() +* \fn int CtrlLockStatus() * \brief Retreive lock status . * \param devAddr Pointer to demodulator device address. * \param lockStat Pointer to lock status structure. -* \return DRXStatus_t. +* \return int. * */ -static DRXStatus_t +static int CtrlLockStatus(pDRXDemodInstance_t demod, pDRXLockStatus_t lockStat) { - DRXStandard_t standard = DRX_STANDARD_UNKNOWN; + enum drx_standard standard = DRX_STANDARD_UNKNOWN; pDRXJData_t extAttr = NULL; struct i2c_device_addr *devAddr = NULL; DRXJSCUCmd_t cmdSCU = { /* command */ 0, @@ -13761,17 +13761,17 @@ rw_error: /*============================================================================*/ /** -* \fn DRXStatus_t CtrlConstel() +* \fn int CtrlConstel() * \brief Retreive a constellation point via I2C. * \param demod Pointer to demodulator instance. * \param complexNr Pointer to the structure in which to store the constellation point. -* \return DRXStatus_t. +* \return int. */ -static DRXStatus_t +static int CtrlConstel(pDRXDemodInstance_t demod, pDRXComplex_t complexNr) { - DRXStandard_t standard = DRX_STANDARD_UNKNOWN; + enum drx_standard standard = DRX_STANDARD_UNKNOWN; /**< active standard */ /* check arguments */ @@ -13807,20 +13807,20 @@ rw_error: /*============================================================================*/ /** -* \fn DRXStatus_t CtrlSetStandard() +* \fn int CtrlSetStandard() * \brief Set modulation standard to be used. * \param standard Modulation standard. -* \return DRXStatus_t. +* \return int. * * Setup stuff for the desired demodulation standard. * Disable and power down the previous selected demodulation standard * */ -static DRXStatus_t -CtrlSetStandard(pDRXDemodInstance_t demod, pDRXStandard_t standard) +static int +CtrlSetStandard(pDRXDemodInstance_t demod, enum drx_standard * standard) { pDRXJData_t extAttr = NULL; - DRXStandard_t prevStandard; + enum drx_standard prevStandard; /* check arguments */ if ((standard == NULL) || (demod == NULL)) { @@ -13908,16 +13908,16 @@ rw_error: /*============================================================================*/ /** -* \fn DRXStatus_t CtrlGetStandard() +* \fn int CtrlGetStandard() * \brief Get modulation standard currently used to demodulate. * \param standard Modulation standard. -* \return DRXStatus_t. +* \return int. * * Returns 8VSB, NTSC, QAM only. * */ -static DRXStatus_t -CtrlGetStandard(pDRXDemodInstance_t demod, pDRXStandard_t standard) +static int +CtrlGetStandard(pDRXDemodInstance_t demod, enum drx_standard * standard) { pDRXJData_t extAttr = NULL; extAttr = (pDRXJData_t) demod->myExtAttr; @@ -13937,16 +13937,16 @@ rw_error: /*============================================================================*/ /** -* \fn DRXStatus_t CtrlGetCfgSymbolClockOffset() +* \fn int CtrlGetCfgSymbolClockOffset() * \brief Get frequency offsets of STR. * \param pointer to s32. -* \return DRXStatus_t. +* \return int. * */ -static DRXStatus_t +static int CtrlGetCfgSymbolClockOffset(pDRXDemodInstance_t demod, s32 *rateOffset) { - DRXStandard_t standard = DRX_STANDARD_UNKNOWN; + enum drx_standard standard = DRX_STANDARD_UNKNOWN; struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; @@ -13982,18 +13982,18 @@ rw_error: /*============================================================================*/ /** -* \fn DRXStatus_t CtrlPowerMode() +* \fn int CtrlPowerMode() * \brief Set the power mode of the device to the specified power mode * \param demod Pointer to demodulator instance. * \param mode Pointer to new power mode. -* \return DRXStatus_t. +* \return int. * \retval DRX_STS_OK Success * \retval DRX_STS_ERROR I2C error or other failure * \retval DRX_STS_INVALID_ARG Invalid mode argument. * * */ -static DRXStatus_t +static int CtrlPowerMode(pDRXDemodInstance_t demod, pDRXPowerMode_t mode) { pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) NULL; @@ -14102,11 +14102,11 @@ rw_error: /*============================================================================*/ /** -* \fn DRXStatus_t CtrlVersion() +* \fn int CtrlVersion() * \brief Report version of microcode and if possible version of device * \param demod Pointer to demodulator instance. * \param versionList Pointer to pointer of linked list of versions. -* \return DRXStatus_t. +* \return int. * * Using static structures so no allocation of memory is needed. * Filling in all the fields each time, cause you don't know if they are @@ -14121,7 +14121,7 @@ rw_error: * DRX3933J B1 => number: 33.2.1 text: "DRX3933J:B1" * */ -static DRXStatus_t +static int CtrlVersion(pDRXDemodInstance_t demod, pDRXVersionList_t * versionList) { pDRXJData_t extAttr = (pDRXJData_t) (NULL); @@ -14261,10 +14261,10 @@ rw_error: /*============================================================================*/ /** -* \fn DRXStatus_t CtrlProbeDevice() +* \fn int CtrlProbeDevice() * \brief Probe device, check if it is present * \param demod Pointer to demodulator instance. -* \return DRXStatus_t. +* \return int. * \retval DRX_STS_OK a drx39xxj device has been detected. * \retval DRX_STS_ERROR no drx39xxj device detected. * @@ -14272,10 +14272,10 @@ rw_error: * */ -static DRXStatus_t CtrlProbeDevice(pDRXDemodInstance_t demod) +static int CtrlProbeDevice(pDRXDemodInstance_t demod) { DRXPowerMode_t orgPowerMode = DRX_POWER_UP; - DRXStatus_t retStatus = DRX_STS_OK; + int retStatus = DRX_STS_OK; pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; @@ -14342,7 +14342,7 @@ rw_error: /*============================================================================*/ /** -* \fn DRXStatus_t IsMCBlockAudio() +* \fn int IsMCBlockAudio() * \brief Check if MC block is Audio or not Audio. * \param addr Pointer to demodulator instance. * \param audioUpload true if MC block is Audio @@ -14360,16 +14360,16 @@ bool IsMCBlockAudio(u32 addr) /*============================================================================*/ /** -* \fn DRXStatus_t CtrlUCodeUpload() +* \fn int CtrlUCodeUpload() * \brief Handle Audio or !Audio part of microcode upload. * \param demod Pointer to demodulator instance. * \param mcInfo Pointer to information about microcode data. * \param action Either UCODE_UPLOAD or UCODE_VERIFY. * \param uploadAudioMC true if Audio MC need to be uploaded. false if !Audio MC need to be uploaded. -* \return DRXStatus_t. +* \return int. */ -static DRXStatus_t +static int CtrlUCodeUpload(pDRXDemodInstance_t demod, pDRXUCodeInfo_t mcInfo, DRXUCodeAction_t action, bool uploadAudioMC) @@ -14540,21 +14540,21 @@ CtrlUCodeUpload(pDRXDemodInstance_t demod, /*===== SigStrength() =========================================================*/ /** -* \fn DRXStatus_t CtrlSigStrength() +* \fn int CtrlSigStrength() * \brief Retrieve signal strength. * \param devmod Pointer to demodulator instance. * \param sigQuality Pointer to signal strength data; range 0, .. , 100. -* \return DRXStatus_t. +* \return int. * \retval DRX_STS_OK sigStrength contains valid data. * \retval DRX_STS_INVALID_ARG sigStrength is NULL. * \retval DRX_STS_ERROR Erroneous data, sigStrength contains invalid data. */ -static DRXStatus_t +static int CtrlSigStrength(pDRXDemodInstance_t demod, u16 *sigStrength) { pDRXJData_t extAttr = NULL; - DRXStandard_t standard = DRX_STANDARD_UNKNOWN; + enum drx_standard standard = DRX_STANDARD_UNKNOWN; /* Check arguments */ if ((sigStrength == NULL) || (demod == NULL)) { @@ -14600,14 +14600,14 @@ rw_error: /*============================================================================*/ /** -* \fn DRXStatus_t CtrlGetCfgOOBMisc() +* \fn int CtrlGetCfgOOBMisc() * \brief Get current state information of OOB. * \param pointer to DRXJCfgOOBMisc_t. -* \return DRXStatus_t. +* \return int. * */ #ifndef DRXJ_DIGITAL_ONLY -static DRXStatus_t +static int CtrlGetCfgOOBMisc(pDRXDemodInstance_t demod, pDRXJCfgOOBMisc_t misc) { struct i2c_device_addr *devAddr = NULL; @@ -14653,13 +14653,13 @@ rw_error: #endif /** -* \fn DRXStatus_t CtrlGetCfgVSBMisc() +* \fn int CtrlGetCfgVSBMisc() * \brief Get current state information of OOB. * \param pointer to DRXJCfgOOBMisc_t. -* \return DRXStatus_t. +* \return int. * */ -static DRXStatus_t +static int CtrlGetCfgVSBMisc(pDRXDemodInstance_t demod, pDRXJCfgVSBMisc_t misc) { struct i2c_device_addr *devAddr = NULL; @@ -14680,17 +14680,17 @@ rw_error: /*============================================================================*/ /** -* \fn DRXStatus_t CtrlSetCfgAgcIf() +* \fn int CtrlSetCfgAgcIf() * \brief Set IF AGC. * \param demod demod instance * \param agcSettings If agc configuration -* \return DRXStatus_t. +* \return int. * * Check arguments * Dispatch handling to standard specific function. * */ -static DRXStatus_t +static int CtrlSetCfgAgcIf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings) { /* check arguments */ @@ -14736,17 +14736,17 @@ CtrlSetCfgAgcIf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings) /*============================================================================*/ /** -* \fn DRXStatus_t CtrlGetCfgAgcIf() +* \fn int CtrlGetCfgAgcIf() * \brief Retrieve IF AGC settings. * \param demod demod instance * \param agcSettings If agc configuration -* \return DRXStatus_t. +* \return int. * * Check arguments * Dispatch handling to standard specific function. * */ -static DRXStatus_t +static int CtrlGetCfgAgcIf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings) { /* check arguments */ @@ -14783,17 +14783,17 @@ CtrlGetCfgAgcIf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings) /*============================================================================*/ /** -* \fn DRXStatus_t CtrlSetCfgAgcRf() +* \fn int CtrlSetCfgAgcRf() * \brief Set RF AGC. * \param demod demod instance * \param agcSettings rf agc configuration -* \return DRXStatus_t. +* \return int. * * Check arguments * Dispatch handling to standard specific function. * */ -static DRXStatus_t +static int CtrlSetCfgAgcRf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings) { /* check arguments */ @@ -14839,17 +14839,17 @@ CtrlSetCfgAgcRf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings) /*============================================================================*/ /** -* \fn DRXStatus_t CtrlGetCfgAgcRf() +* \fn int CtrlGetCfgAgcRf() * \brief Retrieve RF AGC settings. * \param demod demod instance * \param agcSettings Rf agc configuration -* \return DRXStatus_t. +* \return int. * * Check arguments * Dispatch handling to standard specific function. * */ -static DRXStatus_t +static int CtrlGetCfgAgcRf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings) { /* check arguments */ @@ -14886,17 +14886,17 @@ CtrlGetCfgAgcRf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings) /*============================================================================*/ /** -* \fn DRXStatus_t CtrlGetCfgAgcInternal() +* \fn int CtrlGetCfgAgcInternal() * \brief Retrieve internal AGC value. * \param demod demod instance * \param u16 -* \return DRXStatus_t. +* \return int. * * Check arguments * Dispatch handling to standard specific function. * */ -static DRXStatus_t +static int CtrlGetCfgAgcInternal(pDRXDemodInstance_t demod, u16 *agcInternal) { struct i2c_device_addr *devAddr = NULL; @@ -14969,17 +14969,17 @@ rw_error: /*============================================================================*/ /** -* \fn DRXStatus_t CtrlSetCfgPreSaw() +* \fn int CtrlSetCfgPreSaw() * \brief Set Pre-saw reference. * \param demod demod instance * \param u16 * -* \return DRXStatus_t. +* \return int. * * Check arguments * Dispatch handling to standard specific function. * */ -static DRXStatus_t +static int CtrlSetCfgPreSaw(pDRXDemodInstance_t demod, pDRXJCfgPreSaw_t preSaw) { struct i2c_device_addr *devAddr = NULL; @@ -15038,17 +15038,17 @@ rw_error: /*============================================================================*/ /** -* \fn DRXStatus_t CtrlSetCfgAfeGain() +* \fn int CtrlSetCfgAfeGain() * \brief Set AFE Gain. * \param demod demod instance * \param u16 * -* \return DRXStatus_t. +* \return int. * * Check arguments * Dispatch handling to standard specific function. * */ -static DRXStatus_t +static int CtrlSetCfgAfeGain(pDRXDemodInstance_t demod, pDRXJCfgAfeGain_t afeGain) { struct i2c_device_addr *devAddr = NULL; @@ -15114,17 +15114,17 @@ rw_error: /*============================================================================*/ /** -* \fn DRXStatus_t CtrlGetCfgPreSaw() +* \fn int CtrlGetCfgPreSaw() * \brief Get Pre-saw reference setting. * \param demod demod instance * \param u16 * -* \return DRXStatus_t. +* \return int. * * Check arguments * Dispatch handling to standard specific function. * */ -static DRXStatus_t +static int CtrlGetCfgPreSaw(pDRXDemodInstance_t demod, pDRXJCfgPreSaw_t preSaw) { struct i2c_device_addr *devAddr = NULL; @@ -15174,17 +15174,17 @@ CtrlGetCfgPreSaw(pDRXDemodInstance_t demod, pDRXJCfgPreSaw_t preSaw) /*============================================================================*/ /** -* \fn DRXStatus_t CtrlGetCfgAfeGain() +* \fn int CtrlGetCfgAfeGain() * \brief Get AFE Gain. * \param demod demod instance * \param u16 * -* \return DRXStatus_t. +* \return int. * * Check arguments * Dispatch handling to standard specific function. * */ -static DRXStatus_t +static int CtrlGetCfgAfeGain(pDRXDemodInstance_t demod, pDRXJCfgAfeGain_t afeGain) { struct i2c_device_addr *devAddr = NULL; @@ -15219,17 +15219,17 @@ CtrlGetCfgAfeGain(pDRXDemodInstance_t demod, pDRXJCfgAfeGain_t afeGain) /*============================================================================*/ /** -* \fn DRXStatus_t CtrlGetFecMeasSeqCount() +* \fn int CtrlGetFecMeasSeqCount() * \brief Get FEC measurement sequnce number. * \param demod demod instance * \param u16 * -* \return DRXStatus_t. +* \return int. * * Check arguments * Dispatch handling to standard specific function. * */ -static DRXStatus_t +static int CtrlGetFecMeasSeqCount(pDRXDemodInstance_t demod, u16 *fecMeasSeqCount) { /* check arguments */ @@ -15247,17 +15247,17 @@ rw_error: /*============================================================================*/ /** -* \fn DRXStatus_t CtrlGetAccumCrRSCwErr() +* \fn int CtrlGetAccumCrRSCwErr() * \brief Get accumulative corrected RS codeword number. * \param demod demod instance * \param u32 * -* \return DRXStatus_t. +* \return int. * * Check arguments * Dispatch handling to standard specific function. * */ -static DRXStatus_t +static int CtrlGetAccumCrRSCwErr(pDRXDemodInstance_t demod, u32 *accumCrRsCWErr) { if (accumCrRsCWErr == NULL) { @@ -15273,14 +15273,14 @@ rw_error: } /** -* \fn DRXStatus_t CtrlSetCfg() +* \fn int CtrlSetCfg() * \brief Set 'some' configuration of the device. * \param devmod Pointer to demodulator instance. * \param config Pointer to configuration parameters (type and data). -* \return DRXStatus_t. +* \return int. */ -static DRXStatus_t CtrlSetCfg(pDRXDemodInstance_t demod, pDRXCfg_t config) +static int CtrlSetCfg(pDRXDemodInstance_t demod, pDRXCfg_t config) { if (config == NULL) { return (DRX_STS_INVALID_ARG); @@ -15381,14 +15381,14 @@ rw_error: /*============================================================================*/ /** -* \fn DRXStatus_t CtrlGetCfg() +* \fn int CtrlGetCfg() * \brief Get 'some' configuration of the device. * \param devmod Pointer to demodulator instance. * \param config Pointer to configuration parameters (type and data). -* \return DRXStatus_t. +* \return int. */ -static DRXStatus_t CtrlGetCfg(pDRXDemodInstance_t demod, pDRXCfg_t config) +static int CtrlGetCfg(pDRXDemodInstance_t demod, pDRXCfg_t config) { if (config == NULL) { return (DRX_STS_INVALID_ARG); @@ -15521,7 +15521,7 @@ rw_error: * rely on SCU or AUD ucode to be present. * */ -DRXStatus_t DRXJ_Open(pDRXDemodInstance_t demod) +int DRXJ_Open(pDRXDemodInstance_t demod) { struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; @@ -15738,7 +15738,7 @@ rw_error: * \return Status_t Return status. * */ -DRXStatus_t DRXJ_Close(pDRXDemodInstance_t demod) +int DRXJ_Close(pDRXDemodInstance_t demod) { struct i2c_device_addr *devAddr = NULL; pDRXJData_t extAttr = NULL; @@ -15780,8 +15780,8 @@ rw_error: * \brief DRXJ specific control function * \return Status_t Return status. */ -DRXStatus_t -DRXJ_Ctrl(pDRXDemodInstance_t demod, DRXCtrlIndex_t ctrl, void *ctrlData) +int +DRXJ_Ctrl(pDRXDemodInstance_t demod, u32 ctrl, void *ctrlData) { switch (ctrl) { /*======================================================================*/ @@ -15844,14 +15844,14 @@ DRXJ_Ctrl(pDRXDemodInstance_t demod, DRXCtrlIndex_t ctrl, void *ctrlData) case DRX_CTRL_SET_STANDARD: { return CtrlSetStandard(demod, - (pDRXStandard_t) ctrlData); + (enum drx_standard *) ctrlData); } break; /*======================================================================*/ case DRX_CTRL_GET_STANDARD: { return CtrlGetStandard(demod, - (pDRXStandard_t) ctrlData); + (enum drx_standard *) ctrlData); } break; /*======================================================================*/ diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.h b/drivers/media/dvb-frontends/drx39xyj/drxj.h index 87a8f2c..47a0e3c 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.h +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.h @@ -184,7 +184,7 @@ TYPEDEFS * Generic interface for all AGCs present on the DRXJ. */ typedef struct { - DRXStandard_t standard; /* standard for which these settings apply */ + enum drx_standard standard; /* standard for which these settings apply */ DRXJAgcCtrlMode_t ctrlMode; /* off, user, auto */ u16 outputLevel; /* range dependent on AGC */ u16 minOutputLevel; /* range dependent on AGC */ @@ -202,7 +202,7 @@ TYPEDEFS * Interface to configure pre SAW sense. */ typedef struct { - DRXStandard_t standard; /* standard to which these settings apply */ + enum drx_standard standard; /* standard to which these settings apply */ u16 reference; /* pre SAW reference value, range 0 .. 31 */ bool usePreSaw; /* true algorithms must use pre SAW sense */ } DRXJCfgPreSaw_t, *pDRXJCfgPreSaw_t; @@ -214,7 +214,7 @@ TYPEDEFS * Interface to configure gain of AFE (LNA + PGA). */ typedef struct { - DRXStandard_t standard; /* standard to which these settings apply */ + enum drx_standard standard; /* standard to which these settings apply */ u16 gain; /* gain in 0.1 dB steps, DRXJ range 140 .. 335 */ } DRXJCfgAfeGain_t, *pDRXJCfgAfeGain_t; @@ -462,13 +462,13 @@ TYPEDEFS bool mirrorFreqSpectOOB;/**< tuner inversion (true = tuner mirrors the signal */ /* standard/channel settings */ - DRXStandard_t standard; /**< current standard information */ - DRXConstellation_t constellation; + enum drx_standard standard; /**< current standard information */ + enum drx_modulation constellation; /**< current constellation */ s32 frequency; /**< center signal frequency in KHz */ - DRXBandwidth_t currBandwidth; + enum drx_bandwidth currBandwidth; /**< current channel bandwidth */ - DRXMirror_t mirror; /**< current channel mirror */ + enum drx_mirror mirror; /**< current channel mirror */ /* signal quality information */ u32 fecBitsDesired; /**< BER accounting period */ @@ -723,10 +723,10 @@ STRUCTS Exported FUNCTIONS -------------------------------------------------------------------------*/ - extern DRXStatus_t DRXJ_Open(pDRXDemodInstance_t demod); - extern DRXStatus_t DRXJ_Close(pDRXDemodInstance_t demod); - extern DRXStatus_t DRXJ_Ctrl(pDRXDemodInstance_t demod, - DRXCtrlIndex_t ctrl, void *ctrlData); + extern int DRXJ_Open(pDRXDemodInstance_t demod); + extern int DRXJ_Close(pDRXDemodInstance_t demod); + extern int DRXJ_Ctrl(pDRXDemodInstance_t demod, + u32 ctrl, void *ctrlData); /*------------------------------------------------------------------------- Exported GLOBAL VARIABLES -- cgit v1.1 From dbe82e06138f3630027e2bc27a47c79f74693850 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Thu, 16 Jan 2014 10:43:00 -0300 Subject: [media] drx-j: fix whitespacing on pointer parmameters Patch generated with this script: for i in drivers/media/dvb-frontends/drx39xyj/*.[ch]; do perl -ne 's,(enum|struct|void|int|u32|u64|u16|u8|s8|s16|s32|s64)\s+(\S+)\s+\*[ ]+,\1 \2 *,g; print $_' <$i >a && mv a $i; done Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drx_driver.h | 8 ++++---- drivers/media/dvb-frontends/drx39xyj/drxj.c | 16 ++++++++-------- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h index 1e906b8..fddf491 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h @@ -237,9 +237,9 @@ struct tuner_ops { struct tuner_instance { struct i2c_device_addr myI2CDevAddr; - struct tuner_common * myCommonAttr; + struct tuner_common *myCommonAttr; void *myExtAttr; - struct tuner_ops * myFunct; + struct tuner_ops *myFunct; }; @@ -257,7 +257,7 @@ int DRXBSP_TUNER_GetFrequency(struct tuner_instance *tuner, s32 * IFfrequency); int DRXBSP_TUNER_LockStatus(struct tuner_instance *tuner, - enum tuner_lock_status * lockStat); + enum tuner_lock_status *lockStat); int DRXBSP_TUNER_DefaultI2CWriteRead(struct tuner_instance *tuner, struct i2c_device_addr *wDevAddr, @@ -1223,7 +1223,7 @@ STRUCTS typedef struct { u32 *symbolrate; /**< list of symbolrates to scan */ u16 symbolrateSize; /**< size of symbolrate array */ - enum drx_modulation * constellation; + enum drx_modulation *constellation; /**< list of constellations */ u16 constellationSize; /**< size of constellation array */ u16 ifAgcThreshold; /**< thresholf for IF-AGC based diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index c821206..c136226 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -6101,7 +6101,7 @@ rw_error: } /** -* \fn static short GetVSBPostRSPckErr(struct i2c_device_addr * devAddr, u16 *PckErrs) +* \fn static short GetVSBPostRSPckErr(struct i2c_device_addr *devAddr, u16 *PckErrs) * \brief Get the values of packet error in 8VSB mode * \return Error code */ @@ -6132,7 +6132,7 @@ rw_error: } /** -* \fn static short GetVSBBer(struct i2c_device_addr * devAddr, u32 *ber) +* \fn static short GetVSBBer(struct i2c_device_addr *devAddr, u32 *ber) * \brief Get the values of ber in VSB mode * \return Error code */ @@ -6170,7 +6170,7 @@ rw_error: } /** -* \fn static short GetVSBpreViterbiBer(struct i2c_device_addr * devAddr, u32 *ber) +* \fn static short GetVSBpreViterbiBer(struct i2c_device_addr *devAddr, u32 *ber) * \brief Get the values of ber in VSB mode * \return Error code */ @@ -6189,7 +6189,7 @@ rw_error: } /** -* \fn static short GetVSBSymbErr(struct i2c_device_addr * devAddr, u32 *ber) +* \fn static short GetVSBSymbErr(struct i2c_device_addr *devAddr, u32 *ber) * \brief Get the values of ber in VSB mode * \return Error code */ @@ -7834,7 +7834,7 @@ rw_error: /*============================================================================*/ /** -* \fn static short GetQAMRSErrCount(struct i2c_device_addr * devAddr) +* \fn static short GetQAMRSErrCount(struct i2c_device_addr *devAddr) * \brief Get RS error count in QAM mode (used for post RS BER calculation) * \return Error code * @@ -8841,7 +8841,7 @@ rw_error: #ifndef DRXJ_DIGITAL_ONLY #define SCU_RAM_ATV_ENABLE_IIR_WA__A 0x831F6D /* TODO remove after done with reg import */ static int -SetATVStandard(pDRXDemodInstance_t demod, enum drx_standard * standard) +SetATVStandard(pDRXDemodInstance_t demod, enum drx_standard *standard) { /* TODO: enable alternative for tap settings via external file @@ -13817,7 +13817,7 @@ rw_error: * */ static int -CtrlSetStandard(pDRXDemodInstance_t demod, enum drx_standard * standard) +CtrlSetStandard(pDRXDemodInstance_t demod, enum drx_standard *standard) { pDRXJData_t extAttr = NULL; enum drx_standard prevStandard; @@ -13917,7 +13917,7 @@ rw_error: * */ static int -CtrlGetStandard(pDRXDemodInstance_t demod, enum drx_standard * standard) +CtrlGetStandard(pDRXDemodInstance_t demod, enum drx_standard *standard) { pDRXJData_t extAttr = NULL; extAttr = (pDRXJData_t) demod->myExtAttr; -- cgit v1.1 From 7ef66759a3c45aa861133b8905d4f2de1a935f54 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Thu, 16 Jan 2014 11:08:15 -0300 Subject: [media] drx-j: Use checkpatch --fix to solve several issues Instead of manually fixing the issues, use the --fix experimental checkpatch. That solves a bunch of checkpatch issues. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h | 4 +- drivers/media/dvb-frontends/drx39xyj/drx39xxj.h | 2 +- .../media/dvb-frontends/drx39xyj/drx39xxj_dummy.c | 4 +- .../media/dvb-frontends/drx39xyj/drx_dap_fasi.c | 34 +- .../media/dvb-frontends/drx39xyj/drx_dap_fasi.h | 28 +- drivers/media/dvb-frontends/drx39xyj/drx_driver.c | 28 +- drivers/media/dvb-frontends/drx39xyj/drx_driver.h | 970 ++++++++++----------- drivers/media/dvb-frontends/drx39xyj/drxj.c | 200 ++--- drivers/media/dvb-frontends/drx39xyj/drxj.h | 28 +- 9 files changed, 649 insertions(+), 649 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h b/drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h index 2028506..3b9adf9 100644 --- a/drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h +++ b/drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h @@ -70,10 +70,10 @@ DEFINES #define TUNER_MODE_8MHZ 0x4000 /* for 8MHz bandwidth channels */ #define TUNER_MODE_SUB_MAX 8 -#define TUNER_MODE_SUBALL ( TUNER_MODE_SUB0 | TUNER_MODE_SUB1 | \ +#define TUNER_MODE_SUBALL (TUNER_MODE_SUB0 | TUNER_MODE_SUB1 | \ TUNER_MODE_SUB2 | TUNER_MODE_SUB3 | \ TUNER_MODE_SUB4 | TUNER_MODE_SUB5 | \ - TUNER_MODE_SUB6 | TUNER_MODE_SUB7 ) + TUNER_MODE_SUB6 | TUNER_MODE_SUB7) /*------------------------------------------------------------------------------ TYPEDEFS diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h index 1f0b30b..212aee8 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h @@ -37,4 +37,4 @@ struct drx39xxj_state { extern struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c); -#endif // DVB_DUMMY_FE_H +#endif /* DVB_DUMMY_FE_H */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c b/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c index ff6e334..7e3e00e 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c @@ -114,9 +114,9 @@ int DRXBSP_I2C_WriteRead(struct i2c_device_addr *wDevAddr, struct i2c_msg msg[2] = { {.addr = wDevAddr->i2cAddr, - .flags = 0,.buf = wData,.len = wCount}, + .flags = 0, .buf = wData, .len = wCount}, {.addr = rDevAddr->i2cAddr, - .flags = I2C_M_RD,.buf = rData,.len = rCount}, + .flags = I2C_M_RD, .buf = rData, .len = rCount}, }; printk("drx3933 i2c operation addr=%x i2c=%p, wc=%x rc=%x\n", diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c index 479db94..8ec9cc7 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c @@ -252,29 +252,29 @@ static int DRXDAP_FASI_ReadBlock(struct i2c_device_addr *devAddr, addr &= ~DRXDAP_FASI_FLAGS; addr |= flags; -#if ( ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 ) && \ - ( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 ) ) +#if (( DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && \ + (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1) ) /* short format address preferred but long format otherwise */ if (DRXDAP_FASI_LONG_FORMAT(addr)) { #endif -#if ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 ) +#if (DRXDAPFASI_LONG_ADDR_ALLOWED == 1) buf[bufx++] = (u8) (((addr << 1) & 0xFF) | 0x01); buf[bufx++] = (u8) ((addr >> 16) & 0xFF); buf[bufx++] = (u8) ((addr >> 24) & 0xFF); buf[bufx++] = (u8) ((addr >> 7) & 0xFF); #endif -#if ( ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 ) && \ - ( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 ) ) +#if (( DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && \ + (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1) ) } else { #endif -#if ( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 ) +#if (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1) buf[bufx++] = (u8) ((addr << 1) & 0xFF); buf[bufx++] = (u8) (((addr >> 16) & 0x0F) | ((addr >> 18) & 0xF0)); #endif -#if ( ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 ) && \ - ( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 ) ) +#if (( DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && \ + (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1) ) } #endif @@ -332,7 +332,7 @@ static int DRXDAP_FASI_ReadModifyWriteReg16(struct i2c_device_addr *devAddr, { int rc = DRX_STS_ERROR; -#if ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 ) +#if (DRXDAPFASI_LONG_ADDR_ALLOWED == 1) if (rdata == NULL) { return DRX_STS_INVALID_ARG; } @@ -478,29 +478,29 @@ static int DRXDAP_FASI_WriteBlock(struct i2c_device_addr *devAddr, /* Buffer device address */ addr &= ~DRXDAP_FASI_FLAGS; addr |= flags; -#if ( ( (DRXDAPFASI_LONG_ADDR_ALLOWED)==1 ) && \ - ( (DRXDAPFASI_SHORT_ADDR_ALLOWED)==1 ) ) +#if (( (DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && \ + ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1) ) /* short format address preferred but long format otherwise */ if (DRXDAP_FASI_LONG_FORMAT(addr)) { #endif -#if ( (DRXDAPFASI_LONG_ADDR_ALLOWED)==1 ) +#if ((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) buf[bufx++] = (u8) (((addr << 1) & 0xFF) | 0x01); buf[bufx++] = (u8) ((addr >> 16) & 0xFF); buf[bufx++] = (u8) ((addr >> 24) & 0xFF); buf[bufx++] = (u8) ((addr >> 7) & 0xFF); #endif -#if ( ( (DRXDAPFASI_LONG_ADDR_ALLOWED)==1 ) && \ - ( (DRXDAPFASI_SHORT_ADDR_ALLOWED)==1 ) ) +#if (( (DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && \ + ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1) ) } else { #endif -#if ( (DRXDAPFASI_SHORT_ADDR_ALLOWED)==1 ) +#if ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1) buf[bufx++] = (u8) ((addr << 1) & 0xFF); buf[bufx++] = (u8) (((addr >> 16) & 0x0F) | ((addr >> 18) & 0xF0)); #endif -#if ( ( (DRXDAPFASI_LONG_ADDR_ALLOWED)==1 ) && \ - ( (DRXDAPFASI_SHORT_ADDR_ALLOWED)==1 ) ) +#if (( (DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && \ + ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1) ) } #endif diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.h b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.h index 756f08d..5269657 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.h @@ -83,18 +83,18 @@ */ /* set default */ -#if !defined( DRXDAPFASI_LONG_ADDR_ALLOWED ) +#if !defined(DRXDAPFASI_LONG_ADDR_ALLOWED) #define DRXDAPFASI_LONG_ADDR_ALLOWED 1 #endif /* set default */ -#if !defined( DRXDAPFASI_SHORT_ADDR_ALLOWED ) +#if !defined(DRXDAPFASI_SHORT_ADDR_ALLOWED) #define DRXDAPFASI_SHORT_ADDR_ALLOWED 1 #endif /* check */ -#if ( ( DRXDAPFASI_LONG_ADDR_ALLOWED==0 ) && \ - ( DRXDAPFASI_SHORT_ADDR_ALLOWED==0 ) ) +#if (( DRXDAPFASI_LONG_ADDR_ALLOWED == 0) && \ + (DRXDAPFASI_SHORT_ADDR_ALLOWED == 0) ) #error At least one of short- or long-addressing format must be allowed. *; /* illegal statement to force compiler error */ #endif @@ -176,12 +176,12 @@ */ /* set default */ -#if !defined( DRXDAP_MAX_WCHUNKSIZE) +#if !defined(DRXDAP_MAX_WCHUNKSIZE) #define DRXDAP_MAX_WCHUNKSIZE 254 #endif /* check */ -#if ( (DRXDAPFASI_LONG_ADDR_ALLOWED==0)&&(DRXDAPFASI_SHORT_ADDR_ALLOWED==1) ) +#if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 0) && (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1)) #if DRXDAP_SINGLE_MASTER #define DRXDAP_MAX_WCHUNKSIZE_MIN 3 #else @@ -196,7 +196,7 @@ #endif #if DRXDAP_MAX_WCHUNKSIZE < DRXDAP_MAX_WCHUNKSIZE_MIN -#if ( (DRXDAPFASI_LONG_ADDR_ALLOWED==0)&&(DRXDAPFASI_SHORT_ADDR_ALLOWED==1) ) +#if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 0) && (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1)) #if DRXDAP_SINGLE_MASTER #error DRXDAP_MAX_WCHUNKSIZE must be at least 3 in single master mode *; /* illegal statement to force compiler error */ @@ -216,7 +216,7 @@ #endif /* set default */ -#if !defined( DRXDAP_MAX_RCHUNKSIZE) +#if !defined(DRXDAP_MAX_RCHUNKSIZE) #define DRXDAP_MAX_RCHUNKSIZE 254 #endif @@ -249,13 +249,13 @@ extern "C" { #define DRXDAP_FASI_MODEFLAGS 0xC0000000 #define DRXDAP_FASI_FLAGS 0xF0000000 -#define DRXDAP_FASI_ADDR2BLOCK( addr ) (((addr)>>22)&0x3F) -#define DRXDAP_FASI_ADDR2BANK( addr ) (((addr)>>16)&0x3F) -#define DRXDAP_FASI_ADDR2OFFSET( addr ) ((addr)&0x7FFF) +#define DRXDAP_FASI_ADDR2BLOCK(addr) (((addr)>>22)&0x3F) +#define DRXDAP_FASI_ADDR2BANK(addr) (((addr)>>16)&0x3F) +#define DRXDAP_FASI_ADDR2OFFSET(addr) ((addr)&0x7FFF) -#define DRXDAP_FASI_SHORT_FORMAT( addr ) (((addr)& 0xFC30FF80)==0) -#define DRXDAP_FASI_LONG_FORMAT( addr ) (((addr)& 0xFC30FF80)!=0) -#define DRXDAP_FASI_OFFSET_TOO_LARGE( addr ) (((addr)& 0x00008000)!=0) +#define DRXDAP_FASI_SHORT_FORMAT(addr) (((addr) & 0xFC30FF80) == 0) +#define DRXDAP_FASI_LONG_FORMAT(addr) (((addr) & 0xFC30FF80) != 0) +#define DRXDAP_FASI_OFFSET_TOO_LARGE(addr) (((addr) & 0x00008000) != 0) #ifdef __cplusplus } diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c index d33f9ce..c94fd35 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c @@ -99,15 +99,15 @@ DEFINES /*=== MACROS =================================================================*/ /*============================================================================*/ -#define DRX_ISPOWERDOWNMODE( mode ) ( ( mode == DRX_POWER_MODE_9 ) || \ - ( mode == DRX_POWER_MODE_10 ) || \ - ( mode == DRX_POWER_MODE_11 ) || \ - ( mode == DRX_POWER_MODE_12 ) || \ - ( mode == DRX_POWER_MODE_13 ) || \ - ( mode == DRX_POWER_MODE_14 ) || \ - ( mode == DRX_POWER_MODE_15 ) || \ - ( mode == DRX_POWER_MODE_16 ) || \ - ( mode == DRX_POWER_DOWN ) ) +#define DRX_ISPOWERDOWNMODE(mode) ( ( mode == DRX_POWER_MODE_9 ) || \ + (mode == DRX_POWER_MODE_10) || \ + (mode == DRX_POWER_MODE_11) || \ + (mode == DRX_POWER_MODE_12) || \ + (mode == DRX_POWER_MODE_13) || \ + (mode == DRX_POWER_MODE_14) || \ + (mode == DRX_POWER_MODE_15) || \ + (mode == DRX_POWER_MODE_16) || \ + (mode == DRX_POWER_DOWN) ) /*------------------------------------------------------------------------------ GLOBAL VARIABLES @@ -148,7 +148,7 @@ FUNCTIONS static int ScanFunctionDefault(void *scanContext, DRXScanCommand_t scanCommand, - pDRXChannel_t scanChannel, bool * getNextChannel); + pDRXChannel_t scanChannel, bool *getNextChannel); /** * \brief Get pointer to scanning function. @@ -211,7 +211,7 @@ void *GetScanContext(pDRXDemodInstance_t demod, void *scanContext) * In case DRX_NEVER_LOCK is returned the poll-wait will be aborted. * */ -static int ScanWaitForLock(pDRXDemodInstance_t demod, bool * isLocked) +static int ScanWaitForLock(pDRXDemodInstance_t demod, bool *isLocked) { bool doneWaiting = false; DRXLockStatus_t lockState = DRX_NOT_LOCKED; @@ -356,7 +356,7 @@ ScanPrepareNextScan(pDRXDemodInstance_t demod, s32 skip) static int ScanFunctionDefault(void *scanContext, DRXScanCommand_t scanCommand, - pDRXChannel_t scanChannel, bool * getNextChannel) + pDRXChannel_t scanChannel, bool *getNextChannel) { pDRXDemodInstance_t demod = NULL; int status = DRX_STS_ERROR; @@ -604,7 +604,7 @@ static int CtrlScanStop(pDRXDemodInstance_t demod) static int CtrlScanNext(pDRXDemodInstance_t demod, u16 *scanProgress) { pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); - bool * scanReady = (bool *) (NULL); + bool *scanReady = (bool *) (NULL); u16 maxProgress = DRX_SCAN_MAX_PROGRESS; u32 numTries = 0; u32 i = 0; @@ -1202,7 +1202,7 @@ CtrlUCode(pDRXDemodInstance_t demod, * \retval DRX_STS_INVALID_ARG: Invalid arguments. */ static int -CtrlVersion(pDRXDemodInstance_t demod, pDRXVersionList_t * versionList) +CtrlVersion(pDRXDemodInstance_t demod, pDRXVersionList_t *versionList) { static char drxDriverCoreModuleName[] = "Core driver"; static char drxDriverCoreVersionText[] = diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h index fddf491..0b0787f 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h @@ -128,9 +128,9 @@ int DRXBSP_I2C_Term(void); */ int DRXBSP_I2C_WriteRead(struct i2c_device_addr *wDevAddr, u16 wCount, - u8 * wData, + u8 *wData, struct i2c_device_addr *rDevAddr, - u16 rCount, u8 * rData); + u16 rCount, u8 *rData); /** * \fn DRXBSP_I2C_ErrorText() @@ -165,10 +165,10 @@ extern int DRX_I2C_Error_g; #define TUNER_MODE_8MHZ 0x4000 /* for 8MHz bandwidth channels */ #define TUNER_MODE_SUB_MAX 8 -#define TUNER_MODE_SUBALL ( TUNER_MODE_SUB0 | TUNER_MODE_SUB1 | \ +#define TUNER_MODE_SUBALL (TUNER_MODE_SUB0 | TUNER_MODE_SUB1 | \ TUNER_MODE_SUB2 | TUNER_MODE_SUB3 | \ TUNER_MODE_SUB4 | TUNER_MODE_SUB5 | \ - TUNER_MODE_SUB6 | TUNER_MODE_SUB7 ) + TUNER_MODE_SUB6 | TUNER_MODE_SUB7) enum tuner_lock_status { @@ -182,7 +182,7 @@ struct tuner_common { s32 maxFreqRF; /* Highest RF input frequency, in kHz */ u8 subMode; /* Index to sub-mode in use */ - char *** subModeDescriptions; /* Pointer to description of sub-modes */ + char ***subModeDescriptions; /* Pointer to description of sub-modes */ u8 subModes; /* Number of available sub-modes */ /* The following fields will be either 0, NULL or false and do not need @@ -220,10 +220,10 @@ typedef int(*TUNERLockStatusFunc_t) (struct tuner_instance *tuner, typedef int(*TUNERi2cWriteReadFunc_t) (struct tuner_instance *tuner, struct i2c_device_addr * wDevAddr, u16 wCount, - u8 * wData, + u8 *wData, struct i2c_device_addr * rDevAddr, u16 rCount, - u8 * rData); + u8 *rData); struct tuner_ops { TUNEROpenFunc_t openFunc; @@ -253,8 +253,8 @@ int DRXBSP_TUNER_SetFrequency(struct tuner_instance *tuner, int DRXBSP_TUNER_GetFrequency(struct tuner_instance *tuner, u32 mode, - s32 * RFfrequency, - s32 * IFfrequency); + s32 *RFfrequency, + s32 *IFfrequency); int DRXBSP_TUNER_LockStatus(struct tuner_instance *tuner, enum tuner_lock_status *lockStat); @@ -262,9 +262,9 @@ int DRXBSP_TUNER_LockStatus(struct tuner_instance *tuner, int DRXBSP_TUNER_DefaultI2CWriteRead(struct tuner_instance *tuner, struct i2c_device_addr *wDevAddr, u16 wCount, - u8 * wData, + u8 *wData, struct i2c_device_addr *rDevAddr, - u16 rCount, u8 * rData); + u16 rCount, u8 *rData); int DRXBSP_HST_Init(void); @@ -474,11 +474,11 @@ int DRXBSP_HST_Sleep(u32 n); MACROS -------------------------------------------------------------------------*/ /* Macros to stringify the version number */ -#define DRX_VERSIONSTRING( MAJOR, MINOR, PATCH ) \ +#define DRX_VERSIONSTRING(MAJOR, MINOR, PATCH) \ DRX_VERSIONSTRING_HELP(MAJOR)"." \ DRX_VERSIONSTRING_HELP(MINOR)"." \ DRX_VERSIONSTRING_HELP(PATCH) -#define DRX_VERSIONSTRING_HELP( NUM ) #NUM +#define DRX_VERSIONSTRING_HELP(NUM) #NUM /** * \brief Macro to create byte array elements from 16 bit integers. @@ -487,29 +487,29 @@ MACROS * The macro takes care of the required byte order in a 16 bits word. * x->lowbyte(x), highbyte(x) */ -#define DRX_16TO8( x ) ((u8) (((u16)x) &0xFF)), \ +#define DRX_16TO8(x) ((u8) (((u16)x) & 0xFF)), \ ((u8)((((u16)x)>>8)&0xFF)) /** * \brief Macro to sign extend signed 9 bit value to signed 16 bit value */ -#define DRX_S9TOS16(x) ((((u16)x)&0x100 )?((s16)((u16)(x)|0xFF00)):(x)) +#define DRX_S9TOS16(x) ((((u16)x)&0x100)?((s16)((u16)(x)|0xFF00)):(x)) /** * \brief Macro to sign extend signed 9 bit value to signed 16 bit value */ -#define DRX_S24TODRXFREQ(x) ( ( ( (u32) x ) & 0x00800000UL ) ? \ - ( (s32) \ - ( ( (u32) x ) | 0xFF000000 ) ) : \ - ( (s32) x ) ) +#define DRX_S24TODRXFREQ(x) (( ( (u32) x) & 0x00800000UL ) ? \ + ((s32) \ + (( (u32) x) | 0xFF000000 ) ) : \ + ((s32) x) ) /** * \brief Macro to convert 16 bit register value to a s32 */ -#define DRX_U16TODRXFREQ(x) ( ( x & 0x8000 ) ? \ - ( (s32) \ - ( ( (u32) x ) | 0xFFFF0000 ) ) : \ - ( (s32) x ) ) +#define DRX_U16TODRXFREQ(x) (( x & 0x8000) ? \ + ((s32) \ + (( (u32) x) | 0xFFFF0000 ) ) : \ + ((s32) x) ) /*------------------------------------------------------------------------- ENUM @@ -580,7 +580,7 @@ enum drx_bandwidth { * \enum enum drx_mirror * \brief Indicate if channel spectrum is mirrored or not. */ -enum drx_mirror{ +enum drx_mirror { DRX_MIRROR_NO = 0, /**< Spectrum is not mirrored. */ DRX_MIRROR_YES, /**< Spectrum is mirrored. */ DRX_MIRROR_UNKNOWN = DRX_UNKNOWN, @@ -641,7 +641,7 @@ enum drx_priority { * \enum enum drx_coderate * \brief Channel priority in case of hierarchical transmission. */ -enum drx_coderate{ +enum drx_coderate { DRX_CODERATE_1DIV2 = 0, /**< Code rate 1/2nd. */ DRX_CODERATE_2DIV3, /**< Code rate 2/3nd. */ DRX_CODERATE_3DIV4, /**< Code rate 3/4nd. */ @@ -736,7 +736,7 @@ enum drx_interleave_mode { * \enum enum drx_carrier_mode * \brief Channel Carrier Mode. */ -enum drx_carrier_mode{ +enum drx_carrier_mode { DRX_CARRIER_MULTI = 0, /**< Multi carrier mode */ DRX_CARRIER_SINGLE, /**< Single carrier mode */ DRX_CARRIER_UNKNOWN = DRX_UNKNOWN, @@ -748,7 +748,7 @@ enum drx_carrier_mode{ * \enum enum drx_frame_mode * \brief Channel Frame Mode. */ -enum drx_frame_mode{ +enum drx_frame_mode { DRX_FRAMEMODE_420 = 0, /**< 420 with variable PN */ DRX_FRAMEMODE_595, /**< 595 */ DRX_FRAMEMODE_945, /**< 945 with variable PN */ @@ -766,7 +766,7 @@ enum drx_frame_mode{ * \enum enum drx_tps_frame * \brief Frame number in current super-frame. */ -enum drx_tps_frame{ +enum drx_tps_frame { DRX_TPS_FRAME1 = 0, /**< TPS frame 1. */ DRX_TPS_FRAME2, /**< TPS frame 2. */ DRX_TPS_FRAME3, /**< TPS frame 3. */ @@ -779,7 +779,7 @@ enum drx_tps_frame{ * \enum enum drx_ldpc * \brief TPS LDPC . */ -enum drx_ldpc{ +enum drx_ldpc { DRX_LDPC_0_4 = 0, /**< LDPC 0.4 */ DRX_LDPC_0_6, /**< LDPC 0.6 */ DRX_LDPC_0_8, /**< LDPC 0.8 */ @@ -792,7 +792,7 @@ enum drx_ldpc{ * \enum enum drx_pilot_mode * \brief Pilot modes in DTMB. */ -enum drx_pilot_mode{ +enum drx_pilot_mode { DRX_PILOT_ON = 0, /**< Pilot On */ DRX_PILOT_OFF, /**< Pilot Off */ DRX_PILOT_UNKNOWN = DRX_UNKNOWN, @@ -802,58 +802,58 @@ enum drx_pilot_mode{ #define DRX_CTRL_BASE ((u32)0) -#define DRX_CTRL_NOP ( DRX_CTRL_BASE + 0)/**< No Operation */ -#define DRX_CTRL_PROBE_DEVICE ( DRX_CTRL_BASE + 1)/**< Probe device */ - -#define DRX_CTRL_LOAD_UCODE ( DRX_CTRL_BASE + 2)/**< Load microcode */ -#define DRX_CTRL_VERIFY_UCODE ( DRX_CTRL_BASE + 3)/**< Verify microcode */ -#define DRX_CTRL_SET_CHANNEL ( DRX_CTRL_BASE + 4)/**< Set channel */ -#define DRX_CTRL_GET_CHANNEL ( DRX_CTRL_BASE + 5)/**< Get channel */ -#define DRX_CTRL_LOCK_STATUS ( DRX_CTRL_BASE + 6)/**< Get lock status */ -#define DRX_CTRL_SIG_QUALITY ( DRX_CTRL_BASE + 7)/**< Get signal quality */ -#define DRX_CTRL_SIG_STRENGTH ( DRX_CTRL_BASE + 8)/**< Get signal strength*/ -#define DRX_CTRL_RF_POWER ( DRX_CTRL_BASE + 9)/**< Get RF power */ -#define DRX_CTRL_CONSTEL ( DRX_CTRL_BASE + 10)/**< Get constel point */ -#define DRX_CTRL_SCAN_INIT ( DRX_CTRL_BASE + 11)/**< Initialize scan */ -#define DRX_CTRL_SCAN_NEXT ( DRX_CTRL_BASE + 12)/**< Scan for next */ -#define DRX_CTRL_SCAN_STOP ( DRX_CTRL_BASE + 13)/**< Stop scan */ -#define DRX_CTRL_TPS_INFO ( DRX_CTRL_BASE + 14)/**< Get TPS info */ -#define DRX_CTRL_SET_CFG ( DRX_CTRL_BASE + 15)/**< Set configuration */ -#define DRX_CTRL_GET_CFG ( DRX_CTRL_BASE + 16)/**< Get configuration */ -#define DRX_CTRL_VERSION ( DRX_CTRL_BASE + 17)/**< Get version info */ -#define DRX_CTRL_I2C_BRIDGE ( DRX_CTRL_BASE + 18)/**< Open/close bridge */ -#define DRX_CTRL_SET_STANDARD ( DRX_CTRL_BASE + 19)/**< Set demod std */ -#define DRX_CTRL_GET_STANDARD ( DRX_CTRL_BASE + 20)/**< Get demod std */ -#define DRX_CTRL_SET_OOB ( DRX_CTRL_BASE + 21)/**< Set OOB param */ -#define DRX_CTRL_GET_OOB ( DRX_CTRL_BASE + 22)/**< Get OOB param */ +#define DRX_CTRL_NOP (DRX_CTRL_BASE + 0)/**< No Operation */ +#define DRX_CTRL_PROBE_DEVICE (DRX_CTRL_BASE + 1)/**< Probe device */ + +#define DRX_CTRL_LOAD_UCODE (DRX_CTRL_BASE + 2)/**< Load microcode */ +#define DRX_CTRL_VERIFY_UCODE (DRX_CTRL_BASE + 3)/**< Verify microcode */ +#define DRX_CTRL_SET_CHANNEL (DRX_CTRL_BASE + 4)/**< Set channel */ +#define DRX_CTRL_GET_CHANNEL (DRX_CTRL_BASE + 5)/**< Get channel */ +#define DRX_CTRL_LOCK_STATUS (DRX_CTRL_BASE + 6)/**< Get lock status */ +#define DRX_CTRL_SIG_QUALITY (DRX_CTRL_BASE + 7)/**< Get signal quality */ +#define DRX_CTRL_SIG_STRENGTH (DRX_CTRL_BASE + 8)/**< Get signal strength*/ +#define DRX_CTRL_RF_POWER (DRX_CTRL_BASE + 9)/**< Get RF power */ +#define DRX_CTRL_CONSTEL (DRX_CTRL_BASE + 10)/**< Get constel point */ +#define DRX_CTRL_SCAN_INIT (DRX_CTRL_BASE + 11)/**< Initialize scan */ +#define DRX_CTRL_SCAN_NEXT (DRX_CTRL_BASE + 12)/**< Scan for next */ +#define DRX_CTRL_SCAN_STOP (DRX_CTRL_BASE + 13)/**< Stop scan */ +#define DRX_CTRL_TPS_INFO (DRX_CTRL_BASE + 14)/**< Get TPS info */ +#define DRX_CTRL_SET_CFG (DRX_CTRL_BASE + 15)/**< Set configuration */ +#define DRX_CTRL_GET_CFG (DRX_CTRL_BASE + 16)/**< Get configuration */ +#define DRX_CTRL_VERSION (DRX_CTRL_BASE + 17)/**< Get version info */ +#define DRX_CTRL_I2C_BRIDGE (DRX_CTRL_BASE + 18)/**< Open/close bridge */ +#define DRX_CTRL_SET_STANDARD (DRX_CTRL_BASE + 19)/**< Set demod std */ +#define DRX_CTRL_GET_STANDARD (DRX_CTRL_BASE + 20)/**< Get demod std */ +#define DRX_CTRL_SET_OOB (DRX_CTRL_BASE + 21)/**< Set OOB param */ +#define DRX_CTRL_GET_OOB (DRX_CTRL_BASE + 22)/**< Get OOB param */ #define DRX_CTRL_AUD_SET_STANDARD (DRX_CTRL_BASE + 23)/**< Set audio param */ #define DRX_CTRL_AUD_GET_STANDARD (DRX_CTRL_BASE + 24)/**< Get audio param */ -#define DRX_CTRL_AUD_GET_STATUS ( DRX_CTRL_BASE + 25)/**< Read RDS */ -#define DRX_CTRL_AUD_BEEP ( DRX_CTRL_BASE + 26)/**< Read RDS */ -#define DRX_CTRL_I2C_READWRITE ( DRX_CTRL_BASE + 27)/**< Read/write I2C */ -#define DRX_CTRL_PROGRAM_TUNER ( DRX_CTRL_BASE + 28)/**< Program tuner */ +#define DRX_CTRL_AUD_GET_STATUS (DRX_CTRL_BASE + 25)/**< Read RDS */ +#define DRX_CTRL_AUD_BEEP (DRX_CTRL_BASE + 26)/**< Read RDS */ +#define DRX_CTRL_I2C_READWRITE (DRX_CTRL_BASE + 27)/**< Read/write I2C */ +#define DRX_CTRL_PROGRAM_TUNER (DRX_CTRL_BASE + 28)/**< Program tuner */ /* Professional */ -#define DRX_CTRL_MB_CFG ( DRX_CTRL_BASE + 29) /**< */ -#define DRX_CTRL_MB_READ ( DRX_CTRL_BASE + 30) /**< */ -#define DRX_CTRL_MB_WRITE ( DRX_CTRL_BASE + 31) /**< */ -#define DRX_CTRL_MB_CONSTEL ( DRX_CTRL_BASE + 32) /**< */ -#define DRX_CTRL_MB_MER ( DRX_CTRL_BASE + 33) /**< */ +#define DRX_CTRL_MB_CFG (DRX_CTRL_BASE + 29) /**< */ +#define DRX_CTRL_MB_READ (DRX_CTRL_BASE + 30) /**< */ +#define DRX_CTRL_MB_WRITE (DRX_CTRL_BASE + 31) /**< */ +#define DRX_CTRL_MB_CONSTEL (DRX_CTRL_BASE + 32) /**< */ +#define DRX_CTRL_MB_MER (DRX_CTRL_BASE + 33) /**< */ /* Misc */ #define DRX_CTRL_UIO_CFG DRX_CTRL_SET_UIO_CFG /**< Configure UIO */ -#define DRX_CTRL_SET_UIO_CFG ( DRX_CTRL_BASE + 34) /**< Configure UIO */ -#define DRX_CTRL_GET_UIO_CFG ( DRX_CTRL_BASE + 35) /**< Configure UIO */ -#define DRX_CTRL_UIO_READ ( DRX_CTRL_BASE + 36) /**< Read from UIO */ -#define DRX_CTRL_UIO_WRITE ( DRX_CTRL_BASE + 37) /**< Write to UIO */ -#define DRX_CTRL_READ_EVENTS ( DRX_CTRL_BASE + 38) /**< Read events */ -#define DRX_CTRL_HDL_EVENTS ( DRX_CTRL_BASE + 39) /**< Handle events */ -#define DRX_CTRL_POWER_MODE ( DRX_CTRL_BASE + 40) /**< Set power mode */ -#define DRX_CTRL_LOAD_FILTER ( DRX_CTRL_BASE + 41) /**< Load chan. filter */ -#define DRX_CTRL_VALIDATE_UCODE ( DRX_CTRL_BASE + 42) /**< Validate ucode */ -#define DRX_CTRL_DUMP_REGISTERS ( DRX_CTRL_BASE + 43) /**< Dump registers */ +#define DRX_CTRL_SET_UIO_CFG (DRX_CTRL_BASE + 34) /**< Configure UIO */ +#define DRX_CTRL_GET_UIO_CFG (DRX_CTRL_BASE + 35) /**< Configure UIO */ +#define DRX_CTRL_UIO_READ (DRX_CTRL_BASE + 36) /**< Read from UIO */ +#define DRX_CTRL_UIO_WRITE (DRX_CTRL_BASE + 37) /**< Write to UIO */ +#define DRX_CTRL_READ_EVENTS (DRX_CTRL_BASE + 38) /**< Read events */ +#define DRX_CTRL_HDL_EVENTS (DRX_CTRL_BASE + 39) /**< Handle events */ +#define DRX_CTRL_POWER_MODE (DRX_CTRL_BASE + 40) /**< Set power mode */ +#define DRX_CTRL_LOAD_FILTER (DRX_CTRL_BASE + 41) /**< Load chan. filter */ +#define DRX_CTRL_VALIDATE_UCODE (DRX_CTRL_BASE + 42) /**< Validate ucode */ +#define DRX_CTRL_DUMP_REGISTERS (DRX_CTRL_BASE + 43) /**< Dump registers */ -#define DRX_CTRL_MAX ( DRX_CTRL_BASE + 44) /* never to be used */ +#define DRX_CTRL_MAX (DRX_CTRL_BASE + 44) /* never to be used */ /** * \enum DRXUCodeAction_t @@ -1004,25 +1004,25 @@ STRUCTS #define DRX_CFG_BASE ((DRXCfgType_t)0) #endif -#define DRX_CFG_MPEG_OUTPUT ( DRX_CFG_BASE + 0) /* MPEG TS output */ -#define DRX_CFG_PKTERR ( DRX_CFG_BASE + 1) /* Packet Error */ -#define DRX_CFG_SYMCLK_OFFS ( DRX_CFG_BASE + 2) /* Symbol Clk Offset */ -#define DRX_CFG_SMA ( DRX_CFG_BASE + 3) /* Smart Antenna */ -#define DRX_CFG_PINSAFE ( DRX_CFG_BASE + 4) /* Pin safe mode */ -#define DRX_CFG_SUBSTANDARD ( DRX_CFG_BASE + 5) /* substandard */ -#define DRX_CFG_AUD_VOLUME ( DRX_CFG_BASE + 6) /* volume */ -#define DRX_CFG_AUD_RDS ( DRX_CFG_BASE + 7) /* rds */ -#define DRX_CFG_AUD_AUTOSOUND ( DRX_CFG_BASE + 8) /* ASS & ASC */ -#define DRX_CFG_AUD_ASS_THRES ( DRX_CFG_BASE + 9) /* ASS Thresholds */ -#define DRX_CFG_AUD_DEVIATION ( DRX_CFG_BASE + 10) /* Deviation */ -#define DRX_CFG_AUD_PRESCALE ( DRX_CFG_BASE + 11) /* Prescale */ -#define DRX_CFG_AUD_MIXER ( DRX_CFG_BASE + 12) /* Mixer */ -#define DRX_CFG_AUD_AVSYNC ( DRX_CFG_BASE + 13) /* AVSync */ -#define DRX_CFG_AUD_CARRIER ( DRX_CFG_BASE + 14) /* Audio carriers */ -#define DRX_CFG_I2S_OUTPUT ( DRX_CFG_BASE + 15) /* I2S output */ -#define DRX_CFG_ATV_STANDARD ( DRX_CFG_BASE + 16) /* ATV standard */ -#define DRX_CFG_SQI_SPEED ( DRX_CFG_BASE + 17) /* SQI speed */ -#define DRX_CTRL_CFG_MAX ( DRX_CFG_BASE + 18) /* never to be used */ +#define DRX_CFG_MPEG_OUTPUT (DRX_CFG_BASE + 0) /* MPEG TS output */ +#define DRX_CFG_PKTERR (DRX_CFG_BASE + 1) /* Packet Error */ +#define DRX_CFG_SYMCLK_OFFS (DRX_CFG_BASE + 2) /* Symbol Clk Offset */ +#define DRX_CFG_SMA (DRX_CFG_BASE + 3) /* Smart Antenna */ +#define DRX_CFG_PINSAFE (DRX_CFG_BASE + 4) /* Pin safe mode */ +#define DRX_CFG_SUBSTANDARD (DRX_CFG_BASE + 5) /* substandard */ +#define DRX_CFG_AUD_VOLUME (DRX_CFG_BASE + 6) /* volume */ +#define DRX_CFG_AUD_RDS (DRX_CFG_BASE + 7) /* rds */ +#define DRX_CFG_AUD_AUTOSOUND (DRX_CFG_BASE + 8) /* ASS & ASC */ +#define DRX_CFG_AUD_ASS_THRES (DRX_CFG_BASE + 9) /* ASS Thresholds */ +#define DRX_CFG_AUD_DEVIATION (DRX_CFG_BASE + 10) /* Deviation */ +#define DRX_CFG_AUD_PRESCALE (DRX_CFG_BASE + 11) /* Prescale */ +#define DRX_CFG_AUD_MIXER (DRX_CFG_BASE + 12) /* Mixer */ +#define DRX_CFG_AUD_AVSYNC (DRX_CFG_BASE + 13) /* AVSync */ +#define DRX_CFG_AUD_CARRIER (DRX_CFG_BASE + 14) /* Audio carriers */ +#define DRX_CFG_I2S_OUTPUT (DRX_CFG_BASE + 15) /* I2S output */ +#define DRX_CFG_ATV_STANDARD (DRX_CFG_BASE + 16) /* ATV standard */ +#define DRX_CFG_SQI_SPEED (DRX_CFG_BASE + 17) /* SQI speed */ +#define DRX_CTRL_CFG_MAX (DRX_CFG_BASE + 18) /* never to be used */ #define DRX_CFG_PINS_SAFE_MODE DRX_CFG_PINSAFE /*============================================================================*/ @@ -1279,7 +1279,7 @@ STRUCTS typedef int(*DRXScanFunc_t) (void *scanContext, DRXScanCommand_t scanCommand, pDRXChannel_t scanChannel, - bool * getNextChannel); + bool *getNextChannel); /*========================================*/ @@ -2181,275 +2181,275 @@ Conversion from enum values to human readable form. /* standard */ #define DRX_STR_STANDARD(x) ( \ - ( x == DRX_STANDARD_DVBT ) ? "DVB-T" : \ - ( x == DRX_STANDARD_8VSB ) ? "8VSB" : \ - ( x == DRX_STANDARD_NTSC ) ? "NTSC" : \ - ( x == DRX_STANDARD_PAL_SECAM_BG ) ? "PAL/SECAM B/G" : \ - ( x == DRX_STANDARD_PAL_SECAM_DK ) ? "PAL/SECAM D/K" : \ - ( x == DRX_STANDARD_PAL_SECAM_I ) ? "PAL/SECAM I" : \ - ( x == DRX_STANDARD_PAL_SECAM_L ) ? "PAL/SECAM L" : \ - ( x == DRX_STANDARD_PAL_SECAM_LP ) ? "PAL/SECAM LP" : \ - ( x == DRX_STANDARD_ITU_A ) ? "ITU-A" : \ - ( x == DRX_STANDARD_ITU_B ) ? "ITU-B" : \ - ( x == DRX_STANDARD_ITU_C ) ? "ITU-C" : \ - ( x == DRX_STANDARD_ITU_D ) ? "ITU-D" : \ - ( x == DRX_STANDARD_FM ) ? "FM" : \ - ( x == DRX_STANDARD_DTMB ) ? "DTMB" : \ - ( x == DRX_STANDARD_AUTO ) ? "Auto" : \ - ( x == DRX_STANDARD_UNKNOWN ) ? "Unknown" : \ - "(Invalid)" ) + (x == DRX_STANDARD_DVBT) ? "DVB-T" : \ + (x == DRX_STANDARD_8VSB) ? "8VSB" : \ + (x == DRX_STANDARD_NTSC) ? "NTSC" : \ + (x == DRX_STANDARD_PAL_SECAM_BG) ? "PAL/SECAM B/G" : \ + (x == DRX_STANDARD_PAL_SECAM_DK) ? "PAL/SECAM D/K" : \ + (x == DRX_STANDARD_PAL_SECAM_I) ? "PAL/SECAM I" : \ + (x == DRX_STANDARD_PAL_SECAM_L) ? "PAL/SECAM L" : \ + (x == DRX_STANDARD_PAL_SECAM_LP) ? "PAL/SECAM LP" : \ + (x == DRX_STANDARD_ITU_A) ? "ITU-A" : \ + (x == DRX_STANDARD_ITU_B) ? "ITU-B" : \ + (x == DRX_STANDARD_ITU_C) ? "ITU-C" : \ + (x == DRX_STANDARD_ITU_D) ? "ITU-D" : \ + (x == DRX_STANDARD_FM) ? "FM" : \ + (x == DRX_STANDARD_DTMB) ? "DTMB" : \ + (x == DRX_STANDARD_AUTO) ? "Auto" : \ + (x == DRX_STANDARD_UNKNOWN) ? "Unknown" : \ + "(Invalid)") /* channel */ #define DRX_STR_BANDWIDTH(x) ( \ - ( x == DRX_BANDWIDTH_8MHZ ) ? "8 MHz" : \ - ( x == DRX_BANDWIDTH_7MHZ ) ? "7 MHz" : \ - ( x == DRX_BANDWIDTH_6MHZ ) ? "6 MHz" : \ - ( x == DRX_BANDWIDTH_AUTO ) ? "Auto" : \ - ( x == DRX_BANDWIDTH_UNKNOWN ) ? "Unknown" : \ - "(Invalid)" ) + (x == DRX_BANDWIDTH_8MHZ) ? "8 MHz" : \ + (x == DRX_BANDWIDTH_7MHZ) ? "7 MHz" : \ + (x == DRX_BANDWIDTH_6MHZ) ? "6 MHz" : \ + (x == DRX_BANDWIDTH_AUTO) ? "Auto" : \ + (x == DRX_BANDWIDTH_UNKNOWN) ? "Unknown" : \ + "(Invalid)") #define DRX_STR_FFTMODE(x) ( \ - ( x == DRX_FFTMODE_2K ) ? "2k" : \ - ( x == DRX_FFTMODE_4K ) ? "4k" : \ - ( x == DRX_FFTMODE_8K ) ? "8k" : \ - ( x == DRX_FFTMODE_AUTO ) ? "Auto" : \ - ( x == DRX_FFTMODE_UNKNOWN ) ? "Unknown" : \ - "(Invalid)" ) + (x == DRX_FFTMODE_2K) ? "2k" : \ + (x == DRX_FFTMODE_4K) ? "4k" : \ + (x == DRX_FFTMODE_8K) ? "8k" : \ + (x == DRX_FFTMODE_AUTO) ? "Auto" : \ + (x == DRX_FFTMODE_UNKNOWN) ? "Unknown" : \ + "(Invalid)") #define DRX_STR_GUARD(x) ( \ - ( x == DRX_GUARD_1DIV32 ) ? "1/32nd" : \ - ( x == DRX_GUARD_1DIV16 ) ? "1/16th" : \ - ( x == DRX_GUARD_1DIV8 ) ? "1/8th" : \ - ( x == DRX_GUARD_1DIV4 ) ? "1/4th" : \ - ( x == DRX_GUARD_AUTO ) ? "Auto" : \ - ( x == DRX_GUARD_UNKNOWN ) ? "Unknown" : \ - "(Invalid)" ) + (x == DRX_GUARD_1DIV32) ? "1/32nd" : \ + (x == DRX_GUARD_1DIV16) ? "1/16th" : \ + (x == DRX_GUARD_1DIV8) ? "1/8th" : \ + (x == DRX_GUARD_1DIV4) ? "1/4th" : \ + (x == DRX_GUARD_AUTO) ? "Auto" : \ + (x == DRX_GUARD_UNKNOWN) ? "Unknown" : \ + "(Invalid)") #define DRX_STR_CONSTELLATION(x) ( \ - ( x == DRX_CONSTELLATION_BPSK ) ? "BPSK" : \ - ( x == DRX_CONSTELLATION_QPSK ) ? "QPSK" : \ - ( x == DRX_CONSTELLATION_PSK8 ) ? "PSK8" : \ - ( x == DRX_CONSTELLATION_QAM16 ) ? "QAM16" : \ - ( x == DRX_CONSTELLATION_QAM32 ) ? "QAM32" : \ - ( x == DRX_CONSTELLATION_QAM64 ) ? "QAM64" : \ - ( x == DRX_CONSTELLATION_QAM128 ) ? "QAM128" : \ - ( x == DRX_CONSTELLATION_QAM256 ) ? "QAM256" : \ - ( x == DRX_CONSTELLATION_QAM512 ) ? "QAM512" : \ - ( x == DRX_CONSTELLATION_QAM1024 ) ? "QAM1024" : \ - ( x == DRX_CONSTELLATION_QPSK_NR ) ? "QPSK_NR" : \ - ( x == DRX_CONSTELLATION_AUTO ) ? "Auto" : \ - ( x == DRX_CONSTELLATION_UNKNOWN ) ? "Unknown" : \ - "(Invalid)" ) + (x == DRX_CONSTELLATION_BPSK) ? "BPSK" : \ + (x == DRX_CONSTELLATION_QPSK) ? "QPSK" : \ + (x == DRX_CONSTELLATION_PSK8) ? "PSK8" : \ + (x == DRX_CONSTELLATION_QAM16) ? "QAM16" : \ + (x == DRX_CONSTELLATION_QAM32) ? "QAM32" : \ + (x == DRX_CONSTELLATION_QAM64) ? "QAM64" : \ + (x == DRX_CONSTELLATION_QAM128) ? "QAM128" : \ + (x == DRX_CONSTELLATION_QAM256) ? "QAM256" : \ + (x == DRX_CONSTELLATION_QAM512) ? "QAM512" : \ + (x == DRX_CONSTELLATION_QAM1024) ? "QAM1024" : \ + (x == DRX_CONSTELLATION_QPSK_NR) ? "QPSK_NR" : \ + (x == DRX_CONSTELLATION_AUTO) ? "Auto" : \ + (x == DRX_CONSTELLATION_UNKNOWN) ? "Unknown" : \ + "(Invalid)") #define DRX_STR_CODERATE(x) ( \ - ( x == DRX_CODERATE_1DIV2 ) ? "1/2nd" : \ - ( x == DRX_CODERATE_2DIV3 ) ? "2/3rd" : \ - ( x == DRX_CODERATE_3DIV4 ) ? "3/4th" : \ - ( x == DRX_CODERATE_5DIV6 ) ? "5/6th" : \ - ( x == DRX_CODERATE_7DIV8 ) ? "7/8th" : \ - ( x == DRX_CODERATE_AUTO ) ? "Auto" : \ - ( x == DRX_CODERATE_UNKNOWN ) ? "Unknown" : \ - "(Invalid)" ) + (x == DRX_CODERATE_1DIV2) ? "1/2nd" : \ + (x == DRX_CODERATE_2DIV3) ? "2/3rd" : \ + (x == DRX_CODERATE_3DIV4) ? "3/4th" : \ + (x == DRX_CODERATE_5DIV6) ? "5/6th" : \ + (x == DRX_CODERATE_7DIV8) ? "7/8th" : \ + (x == DRX_CODERATE_AUTO) ? "Auto" : \ + (x == DRX_CODERATE_UNKNOWN) ? "Unknown" : \ + "(Invalid)") #define DRX_STR_HIERARCHY(x) ( \ - ( x == DRX_HIERARCHY_NONE ) ? "None" : \ - ( x == DRX_HIERARCHY_ALPHA1 ) ? "Alpha=1" : \ - ( x == DRX_HIERARCHY_ALPHA2 ) ? "Alpha=2" : \ - ( x == DRX_HIERARCHY_ALPHA4 ) ? "Alpha=4" : \ - ( x == DRX_HIERARCHY_AUTO ) ? "Auto" : \ - ( x == DRX_HIERARCHY_UNKNOWN ) ? "Unknown" : \ - "(Invalid)" ) + (x == DRX_HIERARCHY_NONE) ? "None" : \ + (x == DRX_HIERARCHY_ALPHA1) ? "Alpha=1" : \ + (x == DRX_HIERARCHY_ALPHA2) ? "Alpha=2" : \ + (x == DRX_HIERARCHY_ALPHA4) ? "Alpha=4" : \ + (x == DRX_HIERARCHY_AUTO) ? "Auto" : \ + (x == DRX_HIERARCHY_UNKNOWN) ? "Unknown" : \ + "(Invalid)") #define DRX_STR_PRIORITY(x) ( \ - ( x == DRX_PRIORITY_LOW ) ? "Low" : \ - ( x == DRX_PRIORITY_HIGH ) ? "High" : \ - ( x == DRX_PRIORITY_UNKNOWN ) ? "Unknown" : \ - "(Invalid)" ) + (x == DRX_PRIORITY_LOW) ? "Low" : \ + (x == DRX_PRIORITY_HIGH) ? "High" : \ + (x == DRX_PRIORITY_UNKNOWN) ? "Unknown" : \ + "(Invalid)") #define DRX_STR_MIRROR(x) ( \ - ( x == DRX_MIRROR_NO ) ? "Normal" : \ - ( x == DRX_MIRROR_YES ) ? "Mirrored" : \ - ( x == DRX_MIRROR_AUTO ) ? "Auto" : \ - ( x == DRX_MIRROR_UNKNOWN ) ? "Unknown" : \ - "(Invalid)" ) + (x == DRX_MIRROR_NO) ? "Normal" : \ + (x == DRX_MIRROR_YES) ? "Mirrored" : \ + (x == DRX_MIRROR_AUTO) ? "Auto" : \ + (x == DRX_MIRROR_UNKNOWN) ? "Unknown" : \ + "(Invalid)") #define DRX_STR_CLASSIFICATION(x) ( \ - ( x == DRX_CLASSIFICATION_GAUSS ) ? "Gaussion" : \ - ( x == DRX_CLASSIFICATION_HVY_GAUSS ) ? "Heavy Gaussion" : \ - ( x == DRX_CLASSIFICATION_COCHANNEL ) ? "Co-channel" : \ - ( x == DRX_CLASSIFICATION_STATIC ) ? "Static echo" : \ - ( x == DRX_CLASSIFICATION_MOVING ) ? "Moving echo" : \ - ( x == DRX_CLASSIFICATION_ZERODB ) ? "Zero dB echo" : \ - ( x == DRX_CLASSIFICATION_UNKNOWN ) ? "Unknown" : \ - ( x == DRX_CLASSIFICATION_AUTO ) ? "Auto" : \ - "(Invalid)" ) + (x == DRX_CLASSIFICATION_GAUSS) ? "Gaussion" : \ + (x == DRX_CLASSIFICATION_HVY_GAUSS) ? "Heavy Gaussion" : \ + (x == DRX_CLASSIFICATION_COCHANNEL) ? "Co-channel" : \ + (x == DRX_CLASSIFICATION_STATIC) ? "Static echo" : \ + (x == DRX_CLASSIFICATION_MOVING) ? "Moving echo" : \ + (x == DRX_CLASSIFICATION_ZERODB) ? "Zero dB echo" : \ + (x == DRX_CLASSIFICATION_UNKNOWN) ? "Unknown" : \ + (x == DRX_CLASSIFICATION_AUTO) ? "Auto" : \ + "(Invalid)") #define DRX_STR_INTERLEAVEMODE(x) ( \ - ( x == DRX_INTERLEAVEMODE_I128_J1 ) ? "I128_J1" : \ - ( x == DRX_INTERLEAVEMODE_I128_J1_V2 ) ? "I128_J1_V2" : \ - ( x == DRX_INTERLEAVEMODE_I128_J2 ) ? "I128_J2" : \ - ( x == DRX_INTERLEAVEMODE_I64_J2 ) ? "I64_J2" : \ - ( x == DRX_INTERLEAVEMODE_I128_J3 ) ? "I128_J3" : \ - ( x == DRX_INTERLEAVEMODE_I32_J4 ) ? "I32_J4" : \ - ( x == DRX_INTERLEAVEMODE_I128_J4 ) ? "I128_J4" : \ - ( x == DRX_INTERLEAVEMODE_I16_J8 ) ? "I16_J8" : \ - ( x == DRX_INTERLEAVEMODE_I128_J5 ) ? "I128_J5" : \ - ( x == DRX_INTERLEAVEMODE_I8_J16 ) ? "I8_J16" : \ - ( x == DRX_INTERLEAVEMODE_I128_J6 ) ? "I128_J6" : \ - ( x == DRX_INTERLEAVEMODE_RESERVED_11 ) ? "Reserved 11" : \ - ( x == DRX_INTERLEAVEMODE_I128_J7 ) ? "I128_J7" : \ - ( x == DRX_INTERLEAVEMODE_RESERVED_13 ) ? "Reserved 13" : \ - ( x == DRX_INTERLEAVEMODE_I128_J8 ) ? "I128_J8" : \ - ( x == DRX_INTERLEAVEMODE_RESERVED_15 ) ? "Reserved 15" : \ - ( x == DRX_INTERLEAVEMODE_I12_J17 ) ? "I12_J17" : \ - ( x == DRX_INTERLEAVEMODE_I5_J4 ) ? "I5_J4" : \ - ( x == DRX_INTERLEAVEMODE_B52_M240 ) ? "B52_M240" : \ - ( x == DRX_INTERLEAVEMODE_B52_M720 ) ? "B52_M720" : \ - ( x == DRX_INTERLEAVEMODE_B52_M48 ) ? "B52_M48" : \ - ( x == DRX_INTERLEAVEMODE_B52_M0 ) ? "B52_M0" : \ - ( x == DRX_INTERLEAVEMODE_UNKNOWN ) ? "Unknown" : \ - ( x == DRX_INTERLEAVEMODE_AUTO ) ? "Auto" : \ - "(Invalid)" ) + (x == DRX_INTERLEAVEMODE_I128_J1) ? "I128_J1" : \ + (x == DRX_INTERLEAVEMODE_I128_J1_V2) ? "I128_J1_V2" : \ + (x == DRX_INTERLEAVEMODE_I128_J2) ? "I128_J2" : \ + (x == DRX_INTERLEAVEMODE_I64_J2) ? "I64_J2" : \ + (x == DRX_INTERLEAVEMODE_I128_J3) ? "I128_J3" : \ + (x == DRX_INTERLEAVEMODE_I32_J4) ? "I32_J4" : \ + (x == DRX_INTERLEAVEMODE_I128_J4) ? "I128_J4" : \ + (x == DRX_INTERLEAVEMODE_I16_J8) ? "I16_J8" : \ + (x == DRX_INTERLEAVEMODE_I128_J5) ? "I128_J5" : \ + (x == DRX_INTERLEAVEMODE_I8_J16) ? "I8_J16" : \ + (x == DRX_INTERLEAVEMODE_I128_J6) ? "I128_J6" : \ + (x == DRX_INTERLEAVEMODE_RESERVED_11) ? "Reserved 11" : \ + (x == DRX_INTERLEAVEMODE_I128_J7) ? "I128_J7" : \ + (x == DRX_INTERLEAVEMODE_RESERVED_13) ? "Reserved 13" : \ + (x == DRX_INTERLEAVEMODE_I128_J8) ? "I128_J8" : \ + (x == DRX_INTERLEAVEMODE_RESERVED_15) ? "Reserved 15" : \ + (x == DRX_INTERLEAVEMODE_I12_J17) ? "I12_J17" : \ + (x == DRX_INTERLEAVEMODE_I5_J4) ? "I5_J4" : \ + (x == DRX_INTERLEAVEMODE_B52_M240) ? "B52_M240" : \ + (x == DRX_INTERLEAVEMODE_B52_M720) ? "B52_M720" : \ + (x == DRX_INTERLEAVEMODE_B52_M48) ? "B52_M48" : \ + (x == DRX_INTERLEAVEMODE_B52_M0) ? "B52_M0" : \ + (x == DRX_INTERLEAVEMODE_UNKNOWN) ? "Unknown" : \ + (x == DRX_INTERLEAVEMODE_AUTO) ? "Auto" : \ + "(Invalid)") #define DRX_STR_LDPC(x) ( \ - ( x == DRX_LDPC_0_4 ) ? "0.4" : \ - ( x == DRX_LDPC_0_6 ) ? "0.6" : \ - ( x == DRX_LDPC_0_8 ) ? "0.8" : \ - ( x == DRX_LDPC_AUTO ) ? "Auto" : \ - ( x == DRX_LDPC_UNKNOWN ) ? "Unknown" : \ - "(Invalid)" ) + (x == DRX_LDPC_0_4) ? "0.4" : \ + (x == DRX_LDPC_0_6) ? "0.6" : \ + (x == DRX_LDPC_0_8) ? "0.8" : \ + (x == DRX_LDPC_AUTO) ? "Auto" : \ + (x == DRX_LDPC_UNKNOWN) ? "Unknown" : \ + "(Invalid)") #define DRX_STR_CARRIER(x) ( \ - ( x == DRX_CARRIER_MULTI ) ? "Multi" : \ - ( x == DRX_CARRIER_SINGLE ) ? "Single" : \ - ( x == DRX_CARRIER_AUTO ) ? "Auto" : \ - ( x == DRX_CARRIER_UNKNOWN ) ? "Unknown" : \ - "(Invalid)" ) + (x == DRX_CARRIER_MULTI) ? "Multi" : \ + (x == DRX_CARRIER_SINGLE) ? "Single" : \ + (x == DRX_CARRIER_AUTO) ? "Auto" : \ + (x == DRX_CARRIER_UNKNOWN) ? "Unknown" : \ + "(Invalid)") #define DRX_STR_FRAMEMODE(x) ( \ - ( x == DRX_FRAMEMODE_420 ) ? "420" : \ - ( x == DRX_FRAMEMODE_595 ) ? "595" : \ - ( x == DRX_FRAMEMODE_945 ) ? "945" : \ - ( x == DRX_FRAMEMODE_420_FIXED_PN ) ? "420 with fixed PN" : \ - ( x == DRX_FRAMEMODE_945_FIXED_PN ) ? "945 with fixed PN" : \ - ( x == DRX_FRAMEMODE_AUTO ) ? "Auto" : \ - ( x == DRX_FRAMEMODE_UNKNOWN ) ? "Unknown" : \ - "(Invalid)" ) + (x == DRX_FRAMEMODE_420) ? "420" : \ + (x == DRX_FRAMEMODE_595) ? "595" : \ + (x == DRX_FRAMEMODE_945) ? "945" : \ + (x == DRX_FRAMEMODE_420_FIXED_PN) ? "420 with fixed PN" : \ + (x == DRX_FRAMEMODE_945_FIXED_PN) ? "945 with fixed PN" : \ + (x == DRX_FRAMEMODE_AUTO) ? "Auto" : \ + (x == DRX_FRAMEMODE_UNKNOWN) ? "Unknown" : \ + "(Invalid)") #define DRX_STR_PILOT(x) ( \ - ( x == DRX_PILOT_ON ) ? "On" : \ - ( x == DRX_PILOT_OFF ) ? "Off" : \ - ( x == DRX_PILOT_AUTO ) ? "Auto" : \ - ( x == DRX_PILOT_UNKNOWN ) ? "Unknown" : \ - "(Invalid)" ) + (x == DRX_PILOT_ON) ? "On" : \ + (x == DRX_PILOT_OFF) ? "Off" : \ + (x == DRX_PILOT_AUTO) ? "Auto" : \ + (x == DRX_PILOT_UNKNOWN) ? "Unknown" : \ + "(Invalid)") /* TPS */ #define DRX_STR_TPS_FRAME(x) ( \ - ( x == DRX_TPS_FRAME1 ) ? "Frame1" : \ - ( x == DRX_TPS_FRAME2 ) ? "Frame2" : \ - ( x == DRX_TPS_FRAME3 ) ? "Frame3" : \ - ( x == DRX_TPS_FRAME4 ) ? "Frame4" : \ - ( x == DRX_TPS_FRAME_UNKNOWN ) ? "Unknown" : \ - "(Invalid)" ) + (x == DRX_TPS_FRAME1) ? "Frame1" : \ + (x == DRX_TPS_FRAME2) ? "Frame2" : \ + (x == DRX_TPS_FRAME3) ? "Frame3" : \ + (x == DRX_TPS_FRAME4) ? "Frame4" : \ + (x == DRX_TPS_FRAME_UNKNOWN) ? "Unknown" : \ + "(Invalid)") /* lock status */ #define DRX_STR_LOCKSTATUS(x) ( \ - ( x == DRX_NEVER_LOCK ) ? "Never" : \ - ( x == DRX_NOT_LOCKED ) ? "No" : \ - ( x == DRX_LOCKED ) ? "Locked" : \ - ( x == DRX_LOCK_STATE_1 ) ? "Lock state 1" : \ - ( x == DRX_LOCK_STATE_2 ) ? "Lock state 2" : \ - ( x == DRX_LOCK_STATE_3 ) ? "Lock state 3" : \ - ( x == DRX_LOCK_STATE_4 ) ? "Lock state 4" : \ - ( x == DRX_LOCK_STATE_5 ) ? "Lock state 5" : \ - ( x == DRX_LOCK_STATE_6 ) ? "Lock state 6" : \ - ( x == DRX_LOCK_STATE_7 ) ? "Lock state 7" : \ - ( x == DRX_LOCK_STATE_8 ) ? "Lock state 8" : \ - ( x == DRX_LOCK_STATE_9 ) ? "Lock state 9" : \ - "(Invalid)" ) + (x == DRX_NEVER_LOCK) ? "Never" : \ + (x == DRX_NOT_LOCKED) ? "No" : \ + (x == DRX_LOCKED) ? "Locked" : \ + (x == DRX_LOCK_STATE_1) ? "Lock state 1" : \ + (x == DRX_LOCK_STATE_2) ? "Lock state 2" : \ + (x == DRX_LOCK_STATE_3) ? "Lock state 3" : \ + (x == DRX_LOCK_STATE_4) ? "Lock state 4" : \ + (x == DRX_LOCK_STATE_5) ? "Lock state 5" : \ + (x == DRX_LOCK_STATE_6) ? "Lock state 6" : \ + (x == DRX_LOCK_STATE_7) ? "Lock state 7" : \ + (x == DRX_LOCK_STATE_8) ? "Lock state 8" : \ + (x == DRX_LOCK_STATE_9) ? "Lock state 9" : \ + "(Invalid)") /* version information , modules */ #define DRX_STR_MODULE(x) ( \ - ( x == DRX_MODULE_DEVICE ) ? "Device" : \ - ( x == DRX_MODULE_MICROCODE ) ? "Microcode" : \ - ( x == DRX_MODULE_DRIVERCORE ) ? "CoreDriver" : \ - ( x == DRX_MODULE_DEVICEDRIVER ) ? "DeviceDriver" : \ - ( x == DRX_MODULE_BSP_I2C ) ? "BSP I2C" : \ - ( x == DRX_MODULE_BSP_TUNER ) ? "BSP Tuner" : \ - ( x == DRX_MODULE_BSP_HOST ) ? "BSP Host" : \ - ( x == DRX_MODULE_DAP ) ? "Data Access Protocol" : \ - ( x == DRX_MODULE_UNKNOWN ) ? "Unknown" : \ - "(Invalid)" ) + (x == DRX_MODULE_DEVICE) ? "Device" : \ + (x == DRX_MODULE_MICROCODE) ? "Microcode" : \ + (x == DRX_MODULE_DRIVERCORE) ? "CoreDriver" : \ + (x == DRX_MODULE_DEVICEDRIVER) ? "DeviceDriver" : \ + (x == DRX_MODULE_BSP_I2C) ? "BSP I2C" : \ + (x == DRX_MODULE_BSP_TUNER) ? "BSP Tuner" : \ + (x == DRX_MODULE_BSP_HOST) ? "BSP Host" : \ + (x == DRX_MODULE_DAP) ? "Data Access Protocol" : \ + (x == DRX_MODULE_UNKNOWN) ? "Unknown" : \ + "(Invalid)") #define DRX_STR_POWER_MODE(x) ( \ - ( x == DRX_POWER_UP ) ? "DRX_POWER_UP " : \ - ( x == DRX_POWER_MODE_1 ) ? "DRX_POWER_MODE_1" : \ - ( x == DRX_POWER_MODE_2 ) ? "DRX_POWER_MODE_2" : \ - ( x == DRX_POWER_MODE_3 ) ? "DRX_POWER_MODE_3" : \ - ( x == DRX_POWER_MODE_4 ) ? "DRX_POWER_MODE_4" : \ - ( x == DRX_POWER_MODE_5 ) ? "DRX_POWER_MODE_5" : \ - ( x == DRX_POWER_MODE_6 ) ? "DRX_POWER_MODE_6" : \ - ( x == DRX_POWER_MODE_7 ) ? "DRX_POWER_MODE_7" : \ - ( x == DRX_POWER_MODE_8 ) ? "DRX_POWER_MODE_8" : \ - ( x == DRX_POWER_MODE_9 ) ? "DRX_POWER_MODE_9" : \ - ( x == DRX_POWER_MODE_10 ) ? "DRX_POWER_MODE_10" : \ - ( x == DRX_POWER_MODE_11 ) ? "DRX_POWER_MODE_11" : \ - ( x == DRX_POWER_MODE_12 ) ? "DRX_POWER_MODE_12" : \ - ( x == DRX_POWER_MODE_13 ) ? "DRX_POWER_MODE_13" : \ - ( x == DRX_POWER_MODE_14 ) ? "DRX_POWER_MODE_14" : \ - ( x == DRX_POWER_MODE_15 ) ? "DRX_POWER_MODE_15" : \ - ( x == DRX_POWER_MODE_16 ) ? "DRX_POWER_MODE_16" : \ - ( x == DRX_POWER_DOWN ) ? "DRX_POWER_DOWN " : \ - "(Invalid)" ) + (x == DRX_POWER_UP) ? "DRX_POWER_UP " : \ + (x == DRX_POWER_MODE_1) ? "DRX_POWER_MODE_1" : \ + (x == DRX_POWER_MODE_2) ? "DRX_POWER_MODE_2" : \ + (x == DRX_POWER_MODE_3) ? "DRX_POWER_MODE_3" : \ + (x == DRX_POWER_MODE_4) ? "DRX_POWER_MODE_4" : \ + (x == DRX_POWER_MODE_5) ? "DRX_POWER_MODE_5" : \ + (x == DRX_POWER_MODE_6) ? "DRX_POWER_MODE_6" : \ + (x == DRX_POWER_MODE_7) ? "DRX_POWER_MODE_7" : \ + (x == DRX_POWER_MODE_8) ? "DRX_POWER_MODE_8" : \ + (x == DRX_POWER_MODE_9) ? "DRX_POWER_MODE_9" : \ + (x == DRX_POWER_MODE_10) ? "DRX_POWER_MODE_10" : \ + (x == DRX_POWER_MODE_11) ? "DRX_POWER_MODE_11" : \ + (x == DRX_POWER_MODE_12) ? "DRX_POWER_MODE_12" : \ + (x == DRX_POWER_MODE_13) ? "DRX_POWER_MODE_13" : \ + (x == DRX_POWER_MODE_14) ? "DRX_POWER_MODE_14" : \ + (x == DRX_POWER_MODE_15) ? "DRX_POWER_MODE_15" : \ + (x == DRX_POWER_MODE_16) ? "DRX_POWER_MODE_16" : \ + (x == DRX_POWER_DOWN) ? "DRX_POWER_DOWN " : \ + "(Invalid)") #define DRX_STR_OOB_STANDARD(x) ( \ - ( x == DRX_OOB_MODE_A ) ? "ANSI 55-1 " : \ - ( x == DRX_OOB_MODE_B_GRADE_A ) ? "ANSI 55-2 A" : \ - ( x == DRX_OOB_MODE_B_GRADE_B ) ? "ANSI 55-2 B" : \ - "(Invalid)" ) + (x == DRX_OOB_MODE_A) ? "ANSI 55-1 " : \ + (x == DRX_OOB_MODE_B_GRADE_A) ? "ANSI 55-2 A" : \ + (x == DRX_OOB_MODE_B_GRADE_B) ? "ANSI 55-2 B" : \ + "(Invalid)") #define DRX_STR_AUD_STANDARD(x) ( \ - ( x == DRX_AUD_STANDARD_BTSC ) ? "BTSC" : \ - ( x == DRX_AUD_STANDARD_A2 ) ? "A2" : \ - ( x == DRX_AUD_STANDARD_EIAJ ) ? "EIAJ" : \ - ( x == DRX_AUD_STANDARD_FM_STEREO ) ? "FM Stereo" : \ - ( x == DRX_AUD_STANDARD_AUTO ) ? "Auto" : \ - ( x == DRX_AUD_STANDARD_M_MONO ) ? "M-Standard Mono" : \ - ( x == DRX_AUD_STANDARD_D_K_MONO ) ? "D/K Mono FM" : \ - ( x == DRX_AUD_STANDARD_BG_FM ) ? "B/G-Dual Carrier FM (A2)" : \ - ( x == DRX_AUD_STANDARD_D_K1 ) ? "D/K1-Dual Carrier FM" : \ - ( x == DRX_AUD_STANDARD_D_K2 ) ? "D/K2-Dual Carrier FM" : \ - ( x == DRX_AUD_STANDARD_D_K3 ) ? "D/K3-Dual Carrier FM" : \ - ( x == DRX_AUD_STANDARD_BG_NICAM_FM ) ? "B/G-NICAM-FM" : \ - ( x == DRX_AUD_STANDARD_L_NICAM_AM ) ? "L-NICAM-AM" : \ - ( x == DRX_AUD_STANDARD_I_NICAM_FM ) ? "I-NICAM-FM" : \ - ( x == DRX_AUD_STANDARD_D_K_NICAM_FM ) ? "D/K-NICAM-FM" : \ - ( x == DRX_AUD_STANDARD_UNKNOWN ) ? "Unknown" : \ - "(Invalid)" ) + (x == DRX_AUD_STANDARD_BTSC) ? "BTSC" : \ + (x == DRX_AUD_STANDARD_A2) ? "A2" : \ + (x == DRX_AUD_STANDARD_EIAJ) ? "EIAJ" : \ + (x == DRX_AUD_STANDARD_FM_STEREO) ? "FM Stereo" : \ + (x == DRX_AUD_STANDARD_AUTO) ? "Auto" : \ + (x == DRX_AUD_STANDARD_M_MONO) ? "M-Standard Mono" : \ + (x == DRX_AUD_STANDARD_D_K_MONO) ? "D/K Mono FM" : \ + (x == DRX_AUD_STANDARD_BG_FM) ? "B/G-Dual Carrier FM (A2)" : \ + (x == DRX_AUD_STANDARD_D_K1) ? "D/K1-Dual Carrier FM" : \ + (x == DRX_AUD_STANDARD_D_K2) ? "D/K2-Dual Carrier FM" : \ + (x == DRX_AUD_STANDARD_D_K3) ? "D/K3-Dual Carrier FM" : \ + (x == DRX_AUD_STANDARD_BG_NICAM_FM) ? "B/G-NICAM-FM" : \ + (x == DRX_AUD_STANDARD_L_NICAM_AM) ? "L-NICAM-AM" : \ + (x == DRX_AUD_STANDARD_I_NICAM_FM) ? "I-NICAM-FM" : \ + (x == DRX_AUD_STANDARD_D_K_NICAM_FM) ? "D/K-NICAM-FM" : \ + (x == DRX_AUD_STANDARD_UNKNOWN) ? "Unknown" : \ + "(Invalid)") #define DRX_STR_AUD_STEREO(x) ( \ - ( x == true ) ? "Stereo" : \ - ( x == false ) ? "Mono" : \ - "(Invalid)" ) + (x == true) ? "Stereo" : \ + (x == false) ? "Mono" : \ + "(Invalid)") #define DRX_STR_AUD_SAP(x) ( \ - ( x == true ) ? "Present" : \ - ( x == false ) ? "Not present" : \ - "(Invalid)" ) + (x == true) ? "Present" : \ + (x == false) ? "Not present" : \ + "(Invalid)") #define DRX_STR_AUD_CARRIER(x) ( \ - ( x == true ) ? "Present" : \ - ( x == false ) ? "Not present" : \ - "(Invalid)" ) + (x == true) ? "Present" : \ + (x == false) ? "Not present" : \ + "(Invalid)") #define DRX_STR_AUD_RDS(x) ( \ - ( x == true ) ? "Available" : \ - ( x == false ) ? "Not Available" : \ - "(Invalid)" ) + (x == true) ? "Available" : \ + (x == false) ? "Not Available" : \ + "(Invalid)") #define DRX_STR_AUD_NICAM_STATUS(x) ( \ - ( x == DRX_AUD_NICAM_DETECTED ) ? "Detected" : \ - ( x == DRX_AUD_NICAM_NOT_DETECTED ) ? "Not detected" : \ - ( x == DRX_AUD_NICAM_BAD ) ? "Bad" : \ - "(Invalid)" ) + (x == DRX_AUD_NICAM_DETECTED) ? "Detected" : \ + (x == DRX_AUD_NICAM_NOT_DETECTED) ? "Not detected" : \ + (x == DRX_AUD_NICAM_BAD) ? "Bad" : \ + "(Invalid)") #define DRX_STR_RDS_VALID(x) ( \ - ( x == true ) ? "Valid" : \ - ( x == false ) ? "Not Valid" : \ - "(Invalid)" ) + (x == true) ? "Valid" : \ + (x == false) ? "Not Valid" : \ + "(Invalid)") /*------------------------------------------------------------------------- Access macros @@ -2466,29 +2466,29 @@ Access macros * */ -#define DRX_ATTR_MCRECORD( d ) ((d)->myCommonAttr->mcversion) -#define DRX_ATTR_MIRRORFREQSPECT( d ) ((d)->myCommonAttr->mirrorFreqSpect) -#define DRX_ATTR_CURRENTPOWERMODE( d )((d)->myCommonAttr->currentPowerMode) -#define DRX_ATTR_ISOPENED( d ) ((d)->myCommonAttr->isOpened) -#define DRX_ATTR_USEBOOTLOADER( d ) ((d)->myCommonAttr->useBootloader) -#define DRX_ATTR_CURRENTSTANDARD( d ) ((d)->myCommonAttr->currentStandard) -#define DRX_ATTR_PREVSTANDARD( d ) ((d)->myCommonAttr->prevStandard) -#define DRX_ATTR_CACHESTANDARD( d ) ((d)->myCommonAttr->diCacheStandard) -#define DRX_ATTR_CURRENTCHANNEL( d ) ((d)->myCommonAttr->currentChannel) -#define DRX_ATTR_MICROCODE( d ) ((d)->myCommonAttr->microcode) -#define DRX_ATTR_MICROCODESIZE( d ) ((d)->myCommonAttr->microcodeSize) -#define DRX_ATTR_VERIFYMICROCODE( d ) ((d)->myCommonAttr->verifyMicrocode) -#define DRX_ATTR_CAPABILITIES( d ) ((d)->myCommonAttr->capabilities) -#define DRX_ATTR_PRODUCTID( d ) ((d)->myCommonAttr->productId) -#define DRX_ATTR_INTERMEDIATEFREQ( d) ((d)->myCommonAttr->intermediateFreq) -#define DRX_ATTR_SYSCLOCKFREQ( d) ((d)->myCommonAttr->sysClockFreq) -#define DRX_ATTR_TUNERRFAGCPOL( d ) ((d)->myCommonAttr->tunerRfAgcPol) -#define DRX_ATTR_TUNERIFAGCPOL( d) ((d)->myCommonAttr->tunerIfAgcPol) -#define DRX_ATTR_TUNERSLOWMODE( d) ((d)->myCommonAttr->tunerSlowMode) -#define DRX_ATTR_TUNERSPORTNR( d) ((d)->myCommonAttr->tunerPortNr) -#define DRX_ATTR_TUNER( d ) ((d)->myTuner) -#define DRX_ATTR_I2CADDR( d ) ((d)->myI2CDevAddr->i2cAddr) -#define DRX_ATTR_I2CDEVID( d ) ((d)->myI2CDevAddr->i2cDevId) +#define DRX_ATTR_MCRECORD(d) ((d)->myCommonAttr->mcversion) +#define DRX_ATTR_MIRRORFREQSPECT(d) ((d)->myCommonAttr->mirrorFreqSpect) +#define DRX_ATTR_CURRENTPOWERMODE(d)((d)->myCommonAttr->currentPowerMode) +#define DRX_ATTR_ISOPENED(d) ((d)->myCommonAttr->isOpened) +#define DRX_ATTR_USEBOOTLOADER(d) ((d)->myCommonAttr->useBootloader) +#define DRX_ATTR_CURRENTSTANDARD(d) ((d)->myCommonAttr->currentStandard) +#define DRX_ATTR_PREVSTANDARD(d) ((d)->myCommonAttr->prevStandard) +#define DRX_ATTR_CACHESTANDARD(d) ((d)->myCommonAttr->diCacheStandard) +#define DRX_ATTR_CURRENTCHANNEL(d) ((d)->myCommonAttr->currentChannel) +#define DRX_ATTR_MICROCODE(d) ((d)->myCommonAttr->microcode) +#define DRX_ATTR_MICROCODESIZE(d) ((d)->myCommonAttr->microcodeSize) +#define DRX_ATTR_VERIFYMICROCODE(d) ((d)->myCommonAttr->verifyMicrocode) +#define DRX_ATTR_CAPABILITIES(d) ((d)->myCommonAttr->capabilities) +#define DRX_ATTR_PRODUCTID(d) ((d)->myCommonAttr->productId) +#define DRX_ATTR_INTERMEDIATEFREQ(d) ((d)->myCommonAttr->intermediateFreq) +#define DRX_ATTR_SYSCLOCKFREQ(d) ((d)->myCommonAttr->sysClockFreq) +#define DRX_ATTR_TUNERRFAGCPOL(d) ((d)->myCommonAttr->tunerRfAgcPol) +#define DRX_ATTR_TUNERIFAGCPOL(d) ((d)->myCommonAttr->tunerIfAgcPol) +#define DRX_ATTR_TUNERSLOWMODE(d) ((d)->myCommonAttr->tunerSlowMode) +#define DRX_ATTR_TUNERSPORTNR(d) ((d)->myCommonAttr->tunerPortNr) +#define DRX_ATTR_TUNER(d) ((d)->myTuner) +#define DRX_ATTR_I2CADDR(d) ((d)->myI2CDevAddr->i2cAddr) +#define DRX_ATTR_I2CDEVID(d) ((d)->myI2CDevAddr->i2cDevId) /** * \brief Actual access macro's @@ -2502,72 +2502,72 @@ Access macros /**************************/ -#define DRX_SET_MIRRORFREQSPECT( d, x ) \ +#define DRX_SET_MIRRORFREQSPECT(d, x) \ do { \ - DRX_ATTR_MIRRORFREQSPECT( d ) = (x); \ - } while(0) + DRX_ATTR_MIRRORFREQSPECT(d) = (x); \ + } while (0) -#define DRX_GET_MIRRORFREQSPECT( d, x ) \ +#define DRX_GET_MIRRORFREQSPECT(d, x) \ do { \ - (x)=DRX_ATTR_MIRRORFREQSPECT( d ); \ - } while(0) + (x) = DRX_ATTR_MIRRORFREQSPECT(d); \ + } while (0) /**************************/ -#define DRX_SET_CURRENTPOWERMODE( d, x ) \ +#define DRX_SET_CURRENTPOWERMODE(d, x) \ do { \ - DRX_ATTR_CURRENTPOWERMODE( d ) = (x); \ - } while(0) + DRX_ATTR_CURRENTPOWERMODE(d) = (x); \ + } while (0) -#define DRX_GET_CURRENTPOWERMODE( d, x ) \ +#define DRX_GET_CURRENTPOWERMODE(d, x) \ do { \ - (x)=DRX_ATTR_CURRENTPOWERMODE( d ); \ - } while(0) + (x) = DRX_ATTR_CURRENTPOWERMODE(d); \ + } while (0) /**************************/ -#define DRX_SET_MICROCODE( d, x ) \ +#define DRX_SET_MICROCODE(d, x) \ do { \ - DRX_ATTR_MICROCODE( d ) = (x); \ - } while(0) + DRX_ATTR_MICROCODE(d) = (x); \ + } while (0) -#define DRX_GET_MICROCODE( d, x ) \ +#define DRX_GET_MICROCODE(d, x) \ do { \ - (x)=DRX_ATTR_MICROCODE( d ); \ - } while(0) + (x) = DRX_ATTR_MICROCODE(d); \ + } while (0) /**************************/ -#define DRX_SET_MICROCODESIZE( d, x ) \ +#define DRX_SET_MICROCODESIZE(d, x) \ do { \ DRX_ATTR_MICROCODESIZE(d) = (x); \ - } while(0) + } while (0) -#define DRX_GET_MICROCODESIZE( d, x ) \ +#define DRX_GET_MICROCODESIZE(d, x) \ do { \ - (x)=DRX_ATTR_MICROCODESIZE(d); \ - } while(0) + (x) = DRX_ATTR_MICROCODESIZE(d); \ + } while (0) /**************************/ -#define DRX_SET_VERIFYMICROCODE( d, x ) \ +#define DRX_SET_VERIFYMICROCODE(d, x) \ do { \ DRX_ATTR_VERIFYMICROCODE(d) = (x); \ - } while(0) + } while (0) -#define DRX_GET_VERIFYMICROCODE( d, x ) \ +#define DRX_GET_VERIFYMICROCODE(d, x) \ do { \ - (x)=DRX_ATTR_VERIFYMICROCODE(d); \ - } while(0) + (x) = DRX_ATTR_VERIFYMICROCODE(d); \ + } while (0) /**************************/ -#define DRX_SET_MCVERTYPE( d, x ) \ +#define DRX_SET_MCVERTYPE(d, x) \ do { \ DRX_ATTR_MCRECORD(d).auxType = (x); \ } while (0) -#define DRX_GET_MCVERTYPE( d, x ) \ +#define DRX_GET_MCVERTYPE(d, x) \ do { \ (x) = DRX_ATTR_MCRECORD(d).auxType; \ } while (0) @@ -2578,278 +2578,278 @@ Access macros /**************************/ -#define DRX_SET_MCDEV( d, x ) \ +#define DRX_SET_MCDEV(d, x) \ do { \ DRX_ATTR_MCRECORD(d).mcDevType = (x); \ } while (0) -#define DRX_GET_MCDEV( d, x ) \ +#define DRX_GET_MCDEV(d, x) \ do { \ (x) = DRX_ATTR_MCRECORD(d).mcDevType; \ } while (0) /**************************/ -#define DRX_SET_MCVERSION( d, x ) \ +#define DRX_SET_MCVERSION(d, x) \ do { \ DRX_ATTR_MCRECORD(d).mcVersion = (x); \ } while (0) -#define DRX_GET_MCVERSION( d, x ) \ +#define DRX_GET_MCVERSION(d, x) \ do { \ (x) = DRX_ATTR_MCRECORD(d).mcVersion; \ } while (0) /**************************/ -#define DRX_SET_MCPATCH( d, x ) \ +#define DRX_SET_MCPATCH(d, x) \ do { \ DRX_ATTR_MCRECORD(d).mcBaseVersion = (x); \ } while (0) -#define DRX_GET_MCPATCH( d, x ) \ +#define DRX_GET_MCPATCH(d, x) \ do { \ (x) = DRX_ATTR_MCRECORD(d).mcBaseVersion; \ } while (0) /**************************/ -#define DRX_SET_I2CADDR( d, x ) \ +#define DRX_SET_I2CADDR(d, x) \ do { \ DRX_ATTR_I2CADDR(d) = (x); \ - } while(0) + } while (0) -#define DRX_GET_I2CADDR( d, x ) \ +#define DRX_GET_I2CADDR(d, x) \ do { \ - (x)=DRX_ATTR_I2CADDR(d); \ - } while(0) + (x) = DRX_ATTR_I2CADDR(d); \ + } while (0) /**************************/ -#define DRX_SET_I2CDEVID( d, x ) \ +#define DRX_SET_I2CDEVID(d, x) \ do { \ DRX_ATTR_I2CDEVID(d) = (x); \ - } while(0) + } while (0) -#define DRX_GET_I2CDEVID( d, x ) \ +#define DRX_GET_I2CDEVID(d, x) \ do { \ - (x)=DRX_ATTR_I2CDEVID(d); \ - } while(0) + (x) = DRX_ATTR_I2CDEVID(d); \ + } while (0) /**************************/ -#define DRX_SET_USEBOOTLOADER( d, x ) \ +#define DRX_SET_USEBOOTLOADER(d, x) \ do { \ DRX_ATTR_USEBOOTLOADER(d) = (x); \ - } while(0) + } while (0) -#define DRX_GET_USEBOOTLOADER( d, x) \ +#define DRX_GET_USEBOOTLOADER(d, x) \ do { \ - (x)=DRX_ATTR_USEBOOTLOADER(d); \ - } while(0) + (x) = DRX_ATTR_USEBOOTLOADER(d); \ + } while (0) /**************************/ -#define DRX_SET_CURRENTSTANDARD( d, x ) \ +#define DRX_SET_CURRENTSTANDARD(d, x) \ do { \ DRX_ATTR_CURRENTSTANDARD(d) = (x); \ - } while(0) + } while (0) -#define DRX_GET_CURRENTSTANDARD( d, x) \ +#define DRX_GET_CURRENTSTANDARD(d, x) \ do { \ - (x)=DRX_ATTR_CURRENTSTANDARD(d); \ - } while(0) + (x) = DRX_ATTR_CURRENTSTANDARD(d); \ + } while (0) /**************************/ -#define DRX_SET_PREVSTANDARD( d, x ) \ +#define DRX_SET_PREVSTANDARD(d, x) \ do { \ DRX_ATTR_PREVSTANDARD(d) = (x); \ - } while(0) + } while (0) -#define DRX_GET_PREVSTANDARD( d, x) \ +#define DRX_GET_PREVSTANDARD(d, x) \ do { \ - (x)=DRX_ATTR_PREVSTANDARD(d); \ - } while(0) + (x) = DRX_ATTR_PREVSTANDARD(d); \ + } while (0) /**************************/ -#define DRX_SET_CACHESTANDARD( d, x ) \ +#define DRX_SET_CACHESTANDARD(d, x) \ do { \ DRX_ATTR_CACHESTANDARD(d) = (x); \ - } while(0) + } while (0) -#define DRX_GET_CACHESTANDARD( d, x) \ +#define DRX_GET_CACHESTANDARD(d, x) \ do { \ - (x)=DRX_ATTR_CACHESTANDARD(d); \ - } while(0) + (x) = DRX_ATTR_CACHESTANDARD(d); \ + } while (0) /**************************/ -#define DRX_SET_CURRENTCHANNEL( d, x ) \ +#define DRX_SET_CURRENTCHANNEL(d, x) \ do { \ DRX_ATTR_CURRENTCHANNEL(d) = (x); \ - } while(0) + } while (0) -#define DRX_GET_CURRENTCHANNEL( d, x) \ +#define DRX_GET_CURRENTCHANNEL(d, x) \ do { \ - (x)=DRX_ATTR_CURRENTCHANNEL(d); \ - } while(0) + (x) = DRX_ATTR_CURRENTCHANNEL(d); \ + } while (0) /**************************/ -#define DRX_SET_ISOPENED( d, x ) \ +#define DRX_SET_ISOPENED(d, x) \ do { \ DRX_ATTR_ISOPENED(d) = (x); \ - } while(0) + } while (0) -#define DRX_GET_ISOPENED( d, x) \ +#define DRX_GET_ISOPENED(d, x) \ do { \ (x) = DRX_ATTR_ISOPENED(d); \ - } while(0) + } while (0) /**************************/ -#define DRX_SET_TUNER( d, x ) \ +#define DRX_SET_TUNER(d, x) \ do { \ DRX_ATTR_TUNER(d) = (x); \ - } while(0) + } while (0) -#define DRX_GET_TUNER( d, x) \ +#define DRX_GET_TUNER(d, x) \ do { \ (x) = DRX_ATTR_TUNER(d); \ - } while(0) + } while (0) /**************************/ -#define DRX_SET_CAPABILITIES( d, x ) \ +#define DRX_SET_CAPABILITIES(d, x) \ do { \ DRX_ATTR_CAPABILITIES(d) = (x); \ - } while(0) + } while (0) -#define DRX_GET_CAPABILITIES( d, x) \ +#define DRX_GET_CAPABILITIES(d, x) \ do { \ (x) = DRX_ATTR_CAPABILITIES(d); \ - } while(0) + } while (0) /**************************/ -#define DRX_SET_PRODUCTID( d, x ) \ +#define DRX_SET_PRODUCTID(d, x) \ do { \ DRX_ATTR_PRODUCTID(d) |= (x << 4); \ - } while(0) + } while (0) -#define DRX_GET_PRODUCTID( d, x) \ +#define DRX_GET_PRODUCTID(d, x) \ do { \ (x) = (DRX_ATTR_PRODUCTID(d) >> 4); \ - } while(0) + } while (0) /**************************/ -#define DRX_SET_MFX( d, x ) \ +#define DRX_SET_MFX(d, x) \ do { \ DRX_ATTR_PRODUCTID(d) |= (x); \ - } while(0) + } while (0) -#define DRX_GET_MFX( d, x) \ +#define DRX_GET_MFX(d, x) \ do { \ (x) = (DRX_ATTR_PRODUCTID(d) & 0xF); \ - } while(0) + } while (0) /**************************/ -#define DRX_SET_INTERMEDIATEFREQ( d, x ) \ +#define DRX_SET_INTERMEDIATEFREQ(d, x) \ do { \ DRX_ATTR_INTERMEDIATEFREQ(d) = (x); \ - } while(0) + } while (0) -#define DRX_GET_INTERMEDIATEFREQ( d, x) \ +#define DRX_GET_INTERMEDIATEFREQ(d, x) \ do { \ (x) = DRX_ATTR_INTERMEDIATEFREQ(d); \ - } while(0) + } while (0) /**************************/ -#define DRX_SET_SYSCLOCKFREQ( d, x ) \ +#define DRX_SET_SYSCLOCKFREQ(d, x) \ do { \ DRX_ATTR_SYSCLOCKFREQ(d) = (x); \ - } while(0) + } while (0) -#define DRX_GET_SYSCLOCKFREQ( d, x) \ +#define DRX_GET_SYSCLOCKFREQ(d, x) \ do { \ (x) = DRX_ATTR_SYSCLOCKFREQ(d); \ - } while(0) + } while (0) /**************************/ -#define DRX_SET_TUNERRFAGCPOL( d, x ) \ +#define DRX_SET_TUNERRFAGCPOL(d, x) \ do { \ DRX_ATTR_TUNERRFAGCPOL(d) = (x); \ - } while(0) + } while (0) -#define DRX_GET_TUNERRFAGCPOL( d, x) \ +#define DRX_GET_TUNERRFAGCPOL(d, x) \ do { \ (x) = DRX_ATTR_TUNERRFAGCPOL(d); \ - } while(0) + } while (0) /**************************/ -#define DRX_SET_TUNERIFAGCPOL( d, x ) \ +#define DRX_SET_TUNERIFAGCPOL(d, x) \ do { \ DRX_ATTR_TUNERIFAGCPOL(d) = (x); \ - } while(0) + } while (0) -#define DRX_GET_TUNERIFAGCPOL( d, x) \ +#define DRX_GET_TUNERIFAGCPOL(d, x) \ do { \ (x) = DRX_ATTR_TUNERIFAGCPOL(d); \ - } while(0) + } while (0) /**************************/ -#define DRX_SET_TUNERSLOWMODE( d, x ) \ +#define DRX_SET_TUNERSLOWMODE(d, x) \ do { \ DRX_ATTR_TUNERSLOWMODE(d) = (x); \ - } while(0) + } while (0) -#define DRX_GET_TUNERSLOWMODE( d, x) \ +#define DRX_GET_TUNERSLOWMODE(d, x) \ do { \ (x) = DRX_ATTR_TUNERSLOWMODE(d); \ - } while(0) + } while (0) /**************************/ -#define DRX_SET_TUNERPORTNR( d, x ) \ +#define DRX_SET_TUNERPORTNR(d, x) \ do { \ DRX_ATTR_TUNERSPORTNR(d) = (x); \ - } while(0) + } while (0) /**************************/ /* Macros with device-specific handling are converted to CFG functions */ -#define DRX_ACCESSMACRO_SET( demod, value, cfgName, dataType ) \ +#define DRX_ACCESSMACRO_SET(demod, value, cfgName, dataType) \ do { \ DRXCfg_t config; \ dataType cfgData; \ config.cfgType = cfgName; \ config.cfgData = &cfgData; \ cfgData = value; \ - DRX_Ctrl( demod, DRX_CTRL_SET_CFG, &config ); \ - } while ( 0 ) + DRX_Ctrl(demod, DRX_CTRL_SET_CFG, &config); \ + } while (0) -#define DRX_ACCESSMACRO_GET( demod, value, cfgName, dataType, errorValue ) \ +#define DRX_ACCESSMACRO_GET(demod, value, cfgName, dataType, errorValue) \ do { \ int cfgStatus; \ DRXCfg_t config; \ dataType cfgData; \ config.cfgType = cfgName; \ config.cfgData = &cfgData; \ - cfgStatus = DRX_Ctrl( demod, DRX_CTRL_GET_CFG, &config ); \ - if ( cfgStatus == DRX_STS_OK ) { \ + cfgStatus = DRX_Ctrl(demod, DRX_CTRL_GET_CFG, &config); \ + if (cfgStatus == DRX_STS_OK) { \ value = cfgData; \ } else { \ value = (dataType)errorValue; \ } \ - } while ( 0 ) + } while (0) /* Configuration functions for usage by Access (XS) Macros */ @@ -2857,63 +2857,63 @@ Access macros #define DRX_XS_CFG_BASE (500) #endif -#define DRX_XS_CFG_PRESET ( DRX_XS_CFG_BASE + 0 ) -#define DRX_XS_CFG_AUD_BTSC_DETECT ( DRX_XS_CFG_BASE + 1 ) -#define DRX_XS_CFG_QAM_LOCKRANGE ( DRX_XS_CFG_BASE + 2 ) +#define DRX_XS_CFG_PRESET (DRX_XS_CFG_BASE + 0) +#define DRX_XS_CFG_AUD_BTSC_DETECT (DRX_XS_CFG_BASE + 1) +#define DRX_XS_CFG_QAM_LOCKRANGE (DRX_XS_CFG_BASE + 2) /* Access Macros with device-specific handling */ -#define DRX_SET_PRESET( d, x ) \ - DRX_ACCESSMACRO_SET( (d), (x), DRX_XS_CFG_PRESET, char* ) -#define DRX_GET_PRESET( d, x ) \ - DRX_ACCESSMACRO_GET( (d), (x), DRX_XS_CFG_PRESET, char*, "ERROR" ) +#define DRX_SET_PRESET(d, x) \ + DRX_ACCESSMACRO_SET((d), (x), DRX_XS_CFG_PRESET, char*) +#define DRX_GET_PRESET(d, x) \ + DRX_ACCESSMACRO_GET((d), (x), DRX_XS_CFG_PRESET, char*, "ERROR") -#define DRX_SET_AUD_BTSC_DETECT( d, x ) DRX_ACCESSMACRO_SET( (d), (x), \ - DRX_XS_CFG_AUD_BTSC_DETECT, DRXAudBtscDetect_t ) -#define DRX_GET_AUD_BTSC_DETECT( d, x ) DRX_ACCESSMACRO_GET( (d), (x), \ - DRX_XS_CFG_AUD_BTSC_DETECT, DRXAudBtscDetect_t, DRX_UNKNOWN ) +#define DRX_SET_AUD_BTSC_DETECT(d, x) DRX_ACCESSMACRO_SET( (d), (x), \ + DRX_XS_CFG_AUD_BTSC_DETECT, DRXAudBtscDetect_t) +#define DRX_GET_AUD_BTSC_DETECT(d, x) DRX_ACCESSMACRO_GET( (d), (x), \ + DRX_XS_CFG_AUD_BTSC_DETECT, DRXAudBtscDetect_t, DRX_UNKNOWN) -#define DRX_SET_QAM_LOCKRANGE( d, x ) DRX_ACCESSMACRO_SET( (d), (x), \ - DRX_XS_CFG_QAM_LOCKRANGE, DRXQamLockRange_t ) -#define DRX_GET_QAM_LOCKRANGE( d, x ) DRX_ACCESSMACRO_GET( (d), (x), \ - DRX_XS_CFG_QAM_LOCKRANGE, DRXQamLockRange_t, DRX_UNKNOWN ) +#define DRX_SET_QAM_LOCKRANGE(d, x) DRX_ACCESSMACRO_SET( (d), (x), \ + DRX_XS_CFG_QAM_LOCKRANGE, DRXQamLockRange_t) +#define DRX_GET_QAM_LOCKRANGE(d, x) DRX_ACCESSMACRO_GET( (d), (x), \ + DRX_XS_CFG_QAM_LOCKRANGE, DRXQamLockRange_t, DRX_UNKNOWN) /** * \brief Macro to check if std is an ATV standard * \retval true std is an ATV standard * \retval false std is an ATV standard */ -#define DRX_ISATVSTD( std ) ( ( (std) == DRX_STANDARD_PAL_SECAM_BG ) || \ - ( (std) == DRX_STANDARD_PAL_SECAM_DK ) || \ - ( (std) == DRX_STANDARD_PAL_SECAM_I ) || \ - ( (std) == DRX_STANDARD_PAL_SECAM_L ) || \ - ( (std) == DRX_STANDARD_PAL_SECAM_LP ) || \ - ( (std) == DRX_STANDARD_NTSC ) || \ - ( (std) == DRX_STANDARD_FM ) ) +#define DRX_ISATVSTD(std) ( ( (std) == DRX_STANDARD_PAL_SECAM_BG ) || \ + ((std) == DRX_STANDARD_PAL_SECAM_DK) || \ + ((std) == DRX_STANDARD_PAL_SECAM_I) || \ + ((std) == DRX_STANDARD_PAL_SECAM_L) || \ + ((std) == DRX_STANDARD_PAL_SECAM_LP) || \ + ((std) == DRX_STANDARD_NTSC) || \ + ((std) == DRX_STANDARD_FM) ) /** * \brief Macro to check if std is an QAM standard * \retval true std is an QAM standards * \retval false std is an QAM standards */ -#define DRX_ISQAMSTD( std ) ( ( (std) == DRX_STANDARD_ITU_A ) || \ - ( (std) == DRX_STANDARD_ITU_B ) || \ - ( (std) == DRX_STANDARD_ITU_C ) || \ - ( (std) == DRX_STANDARD_ITU_D )) +#define DRX_ISQAMSTD(std) ( ( (std) == DRX_STANDARD_ITU_A ) || \ + ((std) == DRX_STANDARD_ITU_B) || \ + ((std) == DRX_STANDARD_ITU_C) || \ + ((std) == DRX_STANDARD_ITU_D)) /** * \brief Macro to check if std is VSB standard * \retval true std is VSB standard * \retval false std is not VSB standard */ -#define DRX_ISVSBSTD( std ) ( (std) == DRX_STANDARD_8VSB ) +#define DRX_ISVSBSTD(std) ( (std) == DRX_STANDARD_8VSB ) /** * \brief Macro to check if std is DVBT standard * \retval true std is DVBT standard * \retval false std is not DVBT standard */ -#define DRX_ISDVBTSTD( std ) ( (std) == DRX_STANDARD_DVBT ) +#define DRX_ISDVBTSTD(std) ( (std) == DRX_STANDARD_DVBT ) /*------------------------------------------------------------------------- Exported FUNCTIONS diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index c136226..ff99a03 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -170,7 +170,7 @@ INCLUDE FILES #include "drx_driver_version.h" -//#define DRX_DEBUG +/* #define DRX_DEBUG */ #ifdef DRX_DEBUG #include #endif @@ -183,7 +183,7 @@ ENUMS DEFINES ----------------------------------------------------------------------------*/ #ifndef DRXJ_WAKE_UP_KEY -#define DRXJ_WAKE_UP_KEY (demod -> myI2CDevAddr -> i2cAddr) +#define DRXJ_WAKE_UP_KEY (demod->myI2CDevAddr->i2cAddr) #endif /** @@ -306,11 +306,11 @@ DEFINES #endif /* ATV config changed flags */ -#define DRXJ_ATV_CHANGED_COEF ( 0x00000001UL ) -#define DRXJ_ATV_CHANGED_PEAK_FLT ( 0x00000008UL ) -#define DRXJ_ATV_CHANGED_NOISE_FLT ( 0x00000010UL ) -#define DRXJ_ATV_CHANGED_OUTPUT ( 0x00000020UL ) -#define DRXJ_ATV_CHANGED_SIF_ATT ( 0x00000040UL ) +#define DRXJ_ATV_CHANGED_COEF (0x00000001UL) +#define DRXJ_ATV_CHANGED_PEAK_FLT (0x00000008UL) +#define DRXJ_ATV_CHANGED_NOISE_FLT (0x00000010UL) +#define DRXJ_ATV_CHANGED_OUTPUT (0x00000020UL) +#define DRXJ_ATV_CHANGED_SIF_ATT (0x00000040UL) /* UIO define */ #define DRX_UIO_MODE_FIRMWARE_SMA DRX_UIO_MODE_FIRMWARE0 @@ -424,7 +424,7 @@ DEFINES /** * \brief FM Matrix register fix */ -#ifdef AUD_DEM_WR_FM_MATRIX__A +#ifdef AUD_DEM_WR_FM_MATRIX__A #undef AUD_DEM_WR_FM_MATRIX__A #endif #define AUD_DEM_WR_FM_MATRIX__A 0x105006F @@ -480,63 +480,63 @@ DEFINES #ifdef DRXJDRIVER_DEBUG #include -#define CHK_ERROR( s ) \ - do{ \ - if ( (s) != DRX_STS_OK ) \ +#define CHK_ERROR(s) \ + do { \ + if ((s) != DRX_STS_OK) \ { \ fprintf(stderr, \ "ERROR[\n file : %s\n line : %d\n]\n", \ - __FILE__,__LINE__); \ + __FILE__, __LINE__); \ goto rw_error; }; \ } \ while (0 != 0) #else -#define CHK_ERROR( s ) \ - do{ \ - if ( (s) != DRX_STS_OK ) { goto rw_error; } \ +#define CHK_ERROR(s) \ + do { \ + if ((s) != DRX_STS_OK) { goto rw_error; } \ } while (0 != 0) #endif -#define CHK_ZERO( s ) \ - do{ \ - if ( (s) == 0 ) return DRX_STS_ERROR; \ +#define CHK_ZERO(s) \ + do { \ + if ((s) == 0) return DRX_STS_ERROR; \ } while (0) #define DUMMY_READ() \ - do{ \ + do { \ u16 dummy; \ - RR16( demod->myI2CDevAddr, SCU_RAM_VERSION_HI__A, &dummy ); \ + RR16(demod->myI2CDevAddr, SCU_RAM_VERSION_HI__A, &dummy); \ } while (0) -#define WR16( dev, addr, val) \ - CHK_ERROR( DRXJ_DAP.writeReg16Func( (dev), (addr), (val), 0 ) ) +#define WR16(dev, addr, val) \ + CHK_ERROR(DRXJ_DAP.writeReg16Func( (dev), (addr), (val), 0) ) -#define RR16( dev, addr, val) \ - CHK_ERROR( DRXJ_DAP.readReg16Func( (dev), (addr), (val), 0 ) ) +#define RR16(dev, addr, val) \ + CHK_ERROR(DRXJ_DAP.readReg16Func( (dev), (addr), (val), 0) ) -#define WR32( dev, addr, val) \ - CHK_ERROR( DRXJ_DAP.writeReg32Func( (dev), (addr), (val), 0 ) ) +#define WR32(dev, addr, val) \ + CHK_ERROR(DRXJ_DAP.writeReg32Func( (dev), (addr), (val), 0) ) -#define RR32( dev, addr, val) \ - CHK_ERROR( DRXJ_DAP.readReg32Func( (dev), (addr), (val), 0 ) ) +#define RR32(dev, addr, val) \ + CHK_ERROR(DRXJ_DAP.readReg32Func( (dev), (addr), (val), 0) ) -#define WRB( dev, addr, len, block ) \ - CHK_ERROR( DRXJ_DAP.writeBlockFunc( (dev), (addr), (len), (block), 0 ) ) +#define WRB(dev, addr, len, block) \ + CHK_ERROR(DRXJ_DAP.writeBlockFunc( (dev), (addr), (len), (block), 0) ) -#define RRB( dev, addr, len, block ) \ - CHK_ERROR( DRXJ_DAP.readBlockFunc( (dev), (addr), (len), (block), 0 ) ) +#define RRB(dev, addr, len, block) \ + CHK_ERROR(DRXJ_DAP.readBlockFunc( (dev), (addr), (len), (block), 0) ) -#define BCWR16( dev, addr, val ) \ - CHK_ERROR( DRXJ_DAP.writeReg16Func( (dev), (addr), (val), DRXDAP_FASI_BROADCAST ) ) +#define BCWR16(dev, addr, val) \ + CHK_ERROR(DRXJ_DAP.writeReg16Func( (dev), (addr), (val), DRXDAP_FASI_BROADCAST) ) -#define ARR32( dev, addr, val) \ - CHK_ERROR( DRXJ_DAP_AtomicReadReg32( (dev), (addr), (val), 0 ) ) +#define ARR32(dev, addr, val) \ + CHK_ERROR(DRXJ_DAP_AtomicReadReg32( (dev), (addr), (val), 0) ) -#define SARR16( dev, addr, val) \ - CHK_ERROR( DRXJ_DAP_SCU_AtomicReadReg16( (dev), (addr), (val), 0 ) ) +#define SARR16(dev, addr, val) \ + CHK_ERROR(DRXJ_DAP_SCU_AtomicReadReg16( (dev), (addr), (val), 0) ) -#define SAWR16( dev, addr, val) \ - CHK_ERROR( DRXJ_DAP_SCU_AtomicWriteReg16( (dev), (addr), (val), 0 ) ) +#define SAWR16(dev, addr, val) \ + CHK_ERROR(DRXJ_DAP_SCU_AtomicWriteReg16( (dev), (addr), (val), 0) ) /** * This macro is used to create byte arrays for block writes. @@ -544,14 +544,14 @@ DEFINES * The macro takes care of the required byte order in a 16 bits word. * x -> lowbyte(x), highbyte(x) */ -#define DRXJ_16TO8( x ) ((u8) (((u16)x) &0xFF)), \ +#define DRXJ_16TO8(x) ((u8) (((u16)x) & 0xFF)), \ ((u8)((((u16)x)>>8)&0xFF)) /** * This macro is used to convert byte array to 16 bit register value for block read. * Block read speed up I2C traffic between host and demod. * The macro takes care of the required byte order in a 16 bits word. */ -#define DRXJ_8TO16( x ) ((u16) (x[0] | (x[1] << 8))) +#define DRXJ_8TO16(x) ((u16) (x[0] | (x[1] << 8))) /*============================================================================*/ /*=== MISC DEFINES ===========================================================*/ @@ -570,18 +570,18 @@ DEFINES /*=== STANDARD RELATED MACROS ================================================*/ /*============================================================================*/ -#define DRXJ_ISATVSTD( std ) ( ( std == DRX_STANDARD_PAL_SECAM_BG ) || \ - ( std == DRX_STANDARD_PAL_SECAM_DK ) || \ - ( std == DRX_STANDARD_PAL_SECAM_I ) || \ - ( std == DRX_STANDARD_PAL_SECAM_L ) || \ - ( std == DRX_STANDARD_PAL_SECAM_LP ) || \ - ( std == DRX_STANDARD_NTSC ) || \ - ( std == DRX_STANDARD_FM ) ) +#define DRXJ_ISATVSTD(std) ( ( std == DRX_STANDARD_PAL_SECAM_BG ) || \ + (std == DRX_STANDARD_PAL_SECAM_DK) || \ + (std == DRX_STANDARD_PAL_SECAM_I) || \ + (std == DRX_STANDARD_PAL_SECAM_L) || \ + (std == DRX_STANDARD_PAL_SECAM_LP) || \ + (std == DRX_STANDARD_NTSC) || \ + (std == DRX_STANDARD_FM) ) -#define DRXJ_ISQAMSTD( std ) ( ( std == DRX_STANDARD_ITU_A ) || \ - ( std == DRX_STANDARD_ITU_B ) || \ - ( std == DRX_STANDARD_ITU_C ) || \ - ( std == DRX_STANDARD_ITU_D )) +#define DRXJ_ISQAMSTD(std) ( ( std == DRX_STANDARD_ITU_A ) || \ + (std == DRX_STANDARD_ITU_B) || \ + (std == DRX_STANDARD_ITU_C) || \ + (std == DRX_STANDARD_ITU_D)) /*----------------------------------------------------------------------------- STATIC VARIABLES @@ -1224,7 +1224,7 @@ CtrlUCodeUpload(pDRXDemodInstance_t demod, * */ -#define DRX_IS_BOOTH_NEGATIVE(__a) (((__a) & (1 << (sizeof (u32) * 8 - 1))) != 0) +#define DRX_IS_BOOTH_NEGATIVE(__a) (((__a) & (1 << (sizeof(u32) * 8 - 1))) != 0) static void Mult32(u32 a, u32 b, u32 *h, u32 *l) { @@ -1683,7 +1683,7 @@ static const u16 NicamPrescTableVal[43] = TODO: check ignoring single/multimaster is ok for AUD access ? */ -#define DRXJ_ISAUDWRITE( addr ) (((((addr)>>16)&1)==1)?true:false) +#define DRXJ_ISAUDWRITE(addr) (((((addr)>>16)&1) == 1)?true:false) #define DRXJ_DAP_AUDTRIF_TIMEOUT 80 /* millisec */ /*============================================================================*/ @@ -1755,7 +1755,7 @@ static int DRXJ_DAP_ReadModifyWriteReg8(struct i2c_device_addr *devAddr, /* TODO correct define should be #if ( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 ) See comments DRXJ_DAP_ReadModifyWriteReg16 */ -#if ( DRXDAPFASI_LONG_ADDR_ALLOWED == 0 ) +#if (DRXDAPFASI_LONG_ADDR_ALLOWED == 0) static int DRXJ_DAP_RMWriteReg16Short(struct i2c_device_addr *devAddr, DRXaddr_t waddr, DRXaddr_t raddr, @@ -1803,7 +1803,7 @@ static int DRXJ_DAP_ReadModifyWriteReg16(struct i2c_device_addr *devAddr, /* TODO: correct short/long addressing format decision, now long format has higher prio then short because short also needs virt bnks (not impl yet) for certain audio registers */ -#if ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 ) +#if (DRXDAPFASI_LONG_ADDR_ALLOWED == 1) return drxDapFASIFunct_g.readModifyWriteReg16Func(devAddr, waddr, raddr, wdata, rdata); @@ -3492,7 +3492,7 @@ static int CtrlGetUIOCfg(pDRXDemodInstance_t demod, pDRXUIOCfg_t UIOCfg) pDRXJData_t extAttr = (pDRXJData_t) NULL; pDRXUIOMode_t UIOMode[4] = { NULL }; - bool * UIOAvailable[4] = { NULL }; + bool *UIOAvailable[4] = { NULL }; extAttr = demod->myExtAttr; @@ -3823,7 +3823,7 @@ rw_error: */ static int -CtrlI2CBridge(pDRXDemodInstance_t demod, bool * bridgeClosed) +CtrlI2CBridge(pDRXDemodInstance_t demod, bool *bridgeClosed) { DRXJHiCmd_t hiCmd; u16 result = 0; @@ -3908,7 +3908,7 @@ CtrlSetCfgSmartAnt(pDRXDemodInstance_t demod, pDRXJCfgSmartAnt_t smartAnt) struct i2c_device_addr *devAddr = NULL; u16 data = 0; u32 startTime = 0; - static bool bitInverted = false; + static bool bitInverted; devAddr = demod->myI2CDevAddr; extAttr = (pDRXJData_t) demod->myExtAttr; @@ -4356,7 +4356,7 @@ CtrlSetCfgATVOutput(pDRXDemodInstance_t demod, pDRXJCfgAtvOutput_t outputCfg); * \return int. */ static int -CtrlSetCfgPdrSafeMode(pDRXDemodInstance_t demod, bool * enable) +CtrlSetCfgPdrSafeMode(pDRXDemodInstance_t demod, bool *enable) { pDRXJData_t extAttr = (pDRXJData_t) NULL; struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; @@ -4482,7 +4482,7 @@ rw_error: * \return int. */ static int -CtrlGetCfgPdrSafeMode(pDRXDemodInstance_t demod, bool * enabled) +CtrlGetCfgPdrSafeMode(pDRXDemodInstance_t demod, bool *enabled) { pDRXJData_t extAttr = (pDRXJData_t) NULL; @@ -4926,8 +4926,8 @@ rw_error: #ifdef DRXJ_SIGNAL_ACCUM_ERR static int GetAccPktErr(pDRXDemodInstance_t demod, u16 *packetErr) { - static u16 pktErr = 0; - static u16 lastPktErr = 0; + static u16 pktErr; + static u16 lastPktErr; u16 data = 0; pDRXJData_t extAttr = NULL; struct i2c_device_addr *devAddr = NULL; @@ -5046,7 +5046,7 @@ static int GetCTLFreqOffset(pDRXDemodInstance_t demod, s32 *CTLFreq) /* both registers are sign extended */ nominalFrequency = extAttr->iqmFsRateOfs; - ARR32(devAddr, IQM_FS_RATE_LO__A, (u32 *) & currentFrequency); + ARR32(devAddr, IQM_FS_RATE_LO__A, (u32 *) ¤tFrequency); if (extAttr->posImage == true) { /* negative image */ @@ -6174,7 +6174,7 @@ rw_error: * \brief Get the values of ber in VSB mode * \return Error code */ -static int GetVSBpreViterbiBer(struct i2c_device_addr *devAddr, u32 * ber) +static int GetVSBpreViterbiBer(struct i2c_device_addr *devAddr, u32 *ber) { u16 data = 0; @@ -8108,7 +8108,7 @@ CtrlGetQAMConstel(pDRXDemodInstance_t demod, pDRXComplex_t complexNr) WR16(devAddr, QAM_SL_COMM_MB__A, qamSlCommMb); /* Enable MB grabber in the FEC OC */ - fecOcOcrMode = ( /* output select: observe bus */ + fecOcOcrMode = (/* output select: observe bus */ (FEC_OC_OCR_MODE_MB_SELECT__M & (0x0 << FEC_OC_OCR_MODE_MB_SELECT__B)) | /* grabber enable: on */ @@ -8451,10 +8451,10 @@ CtrlSetCfgAtvEquCoef(pDRXDemodInstance_t demod, pDRXJCfgAtvEquCoef_t coef) (coef->coef1 > (ATV_TOP_EQU1_EQU_C1__M / 2)) || (coef->coef2 > (ATV_TOP_EQU2_EQU_C2__M / 2)) || (coef->coef3 > (ATV_TOP_EQU3_EQU_C3__M / 2)) || - (coef->coef0 < ((s16) ~ (ATV_TOP_EQU0_EQU_C0__M >> 1))) || - (coef->coef1 < ((s16) ~ (ATV_TOP_EQU1_EQU_C1__M >> 1))) || - (coef->coef2 < ((s16) ~ (ATV_TOP_EQU2_EQU_C2__M >> 1))) || - (coef->coef3 < ((s16) ~ (ATV_TOP_EQU3_EQU_C3__M >> 1)))) { + (coef->coef0 < ((s16) ~(ATV_TOP_EQU0_EQU_C0__M >> 1))) || + (coef->coef1 < ((s16) ~(ATV_TOP_EQU1_EQU_C1__M >> 1))) || + (coef->coef2 < ((s16) ~(ATV_TOP_EQU2_EQU_C2__M >> 1))) || + (coef->coef3 < ((s16) ~(ATV_TOP_EQU3_EQU_C3__M >> 1)))) { return (DRX_STS_INVALID_ARG); } @@ -10231,7 +10231,7 @@ AUDCtrlSetCfgVolume(pDRXDemodInstance_t demod, pDRXCfgAudVolume_t volume) RR16(devAddr, AUD_DSP_WR_VOLUME__A, &wVolume); /* clear the volume mask */ - wVolume &= (u16) ~ AUD_DSP_WR_VOLUME_VOL_MAIN__M; + wVolume &= (u16) ~AUD_DSP_WR_VOLUME_VOL_MAIN__M; if (volume->mute == true) { /* mute */ /* mute overrules volume */ @@ -10248,8 +10248,8 @@ AUDCtrlSetCfgVolume(pDRXDemodInstance_t demod, pDRXCfgAudVolume_t volume) RR16(devAddr, AUD_DSP_WR_AVC__A, &wAVC); /* clear masks that require writing */ - wAVC &= (u16) ~ AUD_DSP_WR_AVC_AVC_ON__M; - wAVC &= (u16) ~ AUD_DSP_WR_AVC_AVC_DECAY__M; + wAVC &= (u16) ~AUD_DSP_WR_AVC_AVC_ON__M; + wAVC &= (u16) ~AUD_DSP_WR_AVC_AVC_DECAY__M; if (volume->avcMode == DRX_AUD_AVC_OFF) { wAVC |= (AUD_DSP_WR_AVC_AVC_ON_OFF); @@ -10277,7 +10277,7 @@ AUDCtrlSetCfgVolume(pDRXDemodInstance_t demod, pDRXCfgAudVolume_t volume) } /* max attenuation */ - wAVC &= (u16) ~ AUD_DSP_WR_AVC_AVC_MAX_ATT__M; + wAVC &= (u16) ~AUD_DSP_WR_AVC_AVC_MAX_ATT__M; switch (volume->avcMaxAtten) { case DRX_AUD_AVC_MAX_ATTEN_12DB: wAVC |= AUD_DSP_WR_AVC_AVC_MAX_ATT_12DB; @@ -10293,7 +10293,7 @@ AUDCtrlSetCfgVolume(pDRXDemodInstance_t demod, pDRXCfgAudVolume_t volume) } /* max gain */ - wAVC &= (u16) ~ AUD_DSP_WR_AVC_AVC_MAX_GAIN__M; + wAVC &= (u16) ~AUD_DSP_WR_AVC_AVC_MAX_GAIN__M; switch (volume->avcMaxGain) { case DRX_AUD_AVC_MAX_GAIN_0DB: wAVC |= AUD_DSP_WR_AVC_AVC_MAX_GAIN_0DB; @@ -10313,7 +10313,7 @@ AUDCtrlSetCfgVolume(pDRXDemodInstance_t demod, pDRXCfgAudVolume_t volume) return DRX_STS_INVALID_ARG; } - wAVC &= (u16) ~ AUD_DSP_WR_AVC_AVC_REF_LEV__M; + wAVC &= (u16) ~AUD_DSP_WR_AVC_AVC_REF_LEV__M; wAVC |= (u16) (volume->avcRefLevel << AUD_DSP_WR_AVC_AVC_REF_LEV__B); WR16(devAddr, AUD_DSP_WR_AVC__A, wAVC); @@ -10465,7 +10465,7 @@ AUDCtrlSetCfgOutputI2S(pDRXDemodInstance_t demod, pDRXCfgI2SOutput_t output) RR16(devAddr, AUD_DEM_RAM_I2S_CONFIG2__A, &wI2SConfig); /* I2S mode */ - wI2SConfig &= (u16) ~ AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__M; + wI2SConfig &= (u16) ~AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__M; switch (output->mode) { case DRX_I2S_MODE_MASTER: @@ -10479,7 +10479,7 @@ AUDCtrlSetCfgOutputI2S(pDRXDemodInstance_t demod, pDRXCfgI2SOutput_t output) } /* I2S format */ - wI2SConfig &= (u16) ~ AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__M; + wI2SConfig &= (u16) ~AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__M; switch (output->format) { case DRX_I2S_FORMAT_WS_ADVANCED: @@ -10493,7 +10493,7 @@ AUDCtrlSetCfgOutputI2S(pDRXDemodInstance_t demod, pDRXCfgI2SOutput_t output) } /* I2S word length */ - wI2SConfig &= (u16) ~ AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__M; + wI2SConfig &= (u16) ~AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__M; switch (output->wordLength) { case DRX_I2S_WORDLENGTH_16: @@ -10507,7 +10507,7 @@ AUDCtrlSetCfgOutputI2S(pDRXDemodInstance_t demod, pDRXCfgI2SOutput_t output) } /* I2S polarity */ - wI2SConfig &= (u16) ~ AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__M; + wI2SConfig &= (u16) ~AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__M; switch (output->polarity) { case DRX_I2S_POLARITY_LEFT: wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL_LEFT_HIGH; @@ -10520,7 +10520,7 @@ AUDCtrlSetCfgOutputI2S(pDRXDemodInstance_t demod, pDRXCfgI2SOutput_t output) } /* I2S output enabled */ - wI2SConfig &= (u16) ~ AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__M; + wI2SConfig &= (u16) ~AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__M; if (output->outputEnable == true) { wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_ENABLE; } else { @@ -10676,8 +10676,8 @@ AUDCtrSetlCfgAutoSound(pDRXDemodInstance_t demod, wModus = rModus; /* clear ASS & ASC bits */ - wModus &= (u16) ~ AUD_DEM_WR_MODUS_MOD_ASS__M; - wModus &= (u16) ~ AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__M; + wModus &= (u16) ~AUD_DEM_WR_MODUS_MOD_ASS__M; + wModus &= (u16) ~AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__M; switch (*autoSound) { case DRX_AUD_AUTO_SOUND_OFF: @@ -10936,7 +10936,7 @@ AUDCtrlSetCfgCarrier(pDRXDemodInstance_t demod, pDRXCfgAudCarriers_t carriers) CHK_ERROR(AUDGetModus(demod, &rModus)); wModus = rModus; - wModus &= (u16) ~ AUD_DEM_WR_MODUS_MOD_CM_A__M; + wModus &= (u16) ~AUD_DEM_WR_MODUS_MOD_CM_A__M; /* Behaviour of primary audio channel */ switch (carriers->a.opt) { case DRX_NO_CARRIER_MUTE: @@ -10951,7 +10951,7 @@ AUDCtrlSetCfgCarrier(pDRXDemodInstance_t demod, pDRXCfgAudCarriers_t carriers) } /* Behaviour of secondary audio channel */ - wModus &= (u16) ~ AUD_DEM_WR_MODUS_MOD_CM_B__M; + wModus &= (u16) ~AUD_DEM_WR_MODUS_MOD_CM_B__M; switch (carriers->b.opt) { case DRX_NO_CARRIER_MUTE: wModus |= AUD_DEM_WR_MODUS_MOD_CM_B_MUTE; @@ -11122,7 +11122,7 @@ AUDCtrlSetCfgMixer(pDRXDemodInstance_t demod, pDRXCfgAudMixer_t mixer) /* Source Selctor */ RR16(devAddr, AUD_DSP_WR_SRC_I2S_MATR__A, &srcI2SMatr); - srcI2SMatr &= (u16) ~ AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__M; + srcI2SMatr &= (u16) ~AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__M; switch (mixer->sourceI2S) { case DRX_AUD_SRC_MONO: @@ -11142,7 +11142,7 @@ AUDCtrlSetCfgMixer(pDRXDemodInstance_t demod, pDRXCfgAudMixer_t mixer) } /* Matrix */ - srcI2SMatr &= (u16) ~ AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__M; + srcI2SMatr &= (u16) ~AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__M; switch (mixer->matrixI2S) { case DRX_AUD_I2S_MATRIX_MONO: srcI2SMatr |= AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_MONO; @@ -11164,7 +11164,7 @@ AUDCtrlSetCfgMixer(pDRXDemodInstance_t demod, pDRXCfgAudMixer_t mixer) /* FM Matrix */ RR16(devAddr, AUD_DEM_WR_FM_MATRIX__A, &fmMatr); - fmMatr &= (u16) ~ AUD_DEM_WR_FM_MATRIX__M; + fmMatr &= (u16) ~AUD_DEM_WR_FM_MATRIX__M; switch (mixer->matrixFm) { case DRX_AUD_FM_MATRIX_NO_MATRIX: fmMatr |= AUD_DEM_WR_FM_MATRIX_NO_MATRIX; @@ -11230,7 +11230,7 @@ AUDCtrlSetCfgAVSync(pDRXDemodInstance_t demod, pDRXCfgAudAVSync_t avSync) /* audio/video synchronisation */ RR16(devAddr, AUD_DSP_WR_AV_SYNC__A, &wAudVidSync); - wAudVidSync &= (u16) ~ AUD_DSP_WR_AV_SYNC_AV_ON__M; + wAudVidSync &= (u16) ~AUD_DSP_WR_AV_SYNC_AV_ON__M; if (*avSync == DRX_AUD_AVSYNC_OFF) { wAudVidSync |= AUD_DSP_WR_AV_SYNC_AV_ON_DISABLE; @@ -11238,7 +11238,7 @@ AUDCtrlSetCfgAVSync(pDRXDemodInstance_t demod, pDRXCfgAudAVSync_t avSync) wAudVidSync |= AUD_DSP_WR_AV_SYNC_AV_ON_ENABLE; } - wAudVidSync &= (u16) ~ AUD_DSP_WR_AV_SYNC_AV_STD_SEL__M; + wAudVidSync &= (u16) ~AUD_DSP_WR_AV_SYNC_AV_STD_SEL__M; switch (*avSync) { case DRX_AUD_AVSYNC_NTSC: @@ -11389,7 +11389,7 @@ AUDCtrlSetCfgDev(pDRXDemodInstance_t demod, pDRXCfgAudDeviation_t dev) wModus = rModus; - wModus &= (u16) ~ AUD_DEM_WR_MODUS_MOD_HDEV_A__M; + wModus &= (u16) ~AUD_DEM_WR_MODUS_MOD_HDEV_A__M; switch (*dev) { case DRX_AUD_DEVIATION_NORMAL: @@ -11745,7 +11745,7 @@ AUDCtrlSetStandard(pDRXDemodInstance_t demod, pDRXAudStandard_t standard) /* we need the current standard here */ currentStandard = extAttr->standard; - wModus &= (u16) ~ AUD_DEM_WR_MODUS_MOD_6_5MHZ__M; + wModus &= (u16) ~AUD_DEM_WR_MODUS_MOD_6_5MHZ__M; if ((currentStandard == DRX_STANDARD_PAL_SECAM_L) || (currentStandard == DRX_STANDARD_PAL_SECAM_LP)) { @@ -11754,7 +11754,7 @@ AUDCtrlSetStandard(pDRXDemodInstance_t demod, pDRXAudStandard_t standard) wModus |= (AUD_DEM_WR_MODUS_MOD_6_5MHZ_D_K); } - wModus &= (u16) ~ AUD_DEM_WR_MODUS_MOD_4_5MHZ__M; + wModus &= (u16) ~AUD_DEM_WR_MODUS_MOD_4_5MHZ__M; if (currentStandard == DRX_STANDARD_NTSC) { wModus |= (AUD_DEM_WR_MODUS_MOD_4_5MHZ_M_BTSC); @@ -11765,7 +11765,7 @@ AUDCtrlSetStandard(pDRXDemodInstance_t demod, pDRXAudStandard_t standard) } - wModus &= (u16) ~ AUD_DEM_WR_MODUS_MOD_FMRADIO__M; + wModus &= (u16) ~AUD_DEM_WR_MODUS_MOD_FMRADIO__M; /* just get hardcoded deemphasis and activate here */ if (extAttr->audData.deemph == DRX_AUD_FM_DEEMPH_50US) { @@ -11774,7 +11774,7 @@ AUDCtrlSetStandard(pDRXDemodInstance_t demod, pDRXAudStandard_t standard) wModus |= (AUD_DEM_WR_MODUS_MOD_FMRADIO_US_75U); } - wModus &= (u16) ~ AUD_DEM_WR_MODUS_MOD_BTSC__M; + wModus &= (u16) ~AUD_DEM_WR_MODUS_MOD_BTSC__M; if (extAttr->audData.btscDetect == DRX_BTSC_STEREO) { wModus |= (AUD_DEM_WR_MODUS_MOD_BTSC_BTSC_STEREO); } else { /* DRX_BTSC_MONO_AND_SAP */ @@ -12464,9 +12464,9 @@ rw_error: */ /* Nyquist filter impulse response */ -#define IMPULSE_COSINE_ALPHA_0_3 {-3,-4,-1, 6,10, 7,-5,-20,-25,-10,29,79,123,140} /*sqrt raised-cosine filter with alpha=0.3 */ -#define IMPULSE_COSINE_ALPHA_0_5 { 2, 0,-2,-2, 2, 5, 2,-10,-20,-14,20,74,125,145} /*sqrt raised-cosine filter with alpha=0.5 */ -#define IMPULSE_COSINE_ALPHA_RO_0_5 { 0, 0, 1, 2, 3, 0,-7,-15,-16, 0,34,77,114,128} /*full raised-cosine filter with alpha=0.5 (receiver only) */ +#define IMPULSE_COSINE_ALPHA_0_3 {-3, -4, -1, 6, 10, 7, -5, -20, -25, -10, 29, 79, 123, 140} /*sqrt raised-cosine filter with alpha=0.3 */ +#define IMPULSE_COSINE_ALPHA_0_5 { 2, 0, -2, -2, 2, 5, 2, -10, -20, -14, 20, 74, 125, 145} /*sqrt raised-cosine filter with alpha=0.5 */ +#define IMPULSE_COSINE_ALPHA_RO_0_5 { 0, 0, 1, 2, 3, 0, -7, -15, -16, 0, 34, 77, 114, 128} /*full raised-cosine filter with alpha=0.5 (receiver only) */ /* Coefficients for the nyquist fitler (total: 27 taps) */ #define NYQFILTERLEN 27 @@ -14122,7 +14122,7 @@ rw_error: * */ static int -CtrlVersion(pDRXDemodInstance_t demod, pDRXVersionList_t * versionList) +CtrlVersion(pDRXDemodInstance_t demod, pDRXVersionList_t *versionList) { pDRXJData_t extAttr = (pDRXJData_t) (NULL); struct i2c_device_addr *devAddr = (struct i2c_device_addr *) (NULL); diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.h b/drivers/media/dvb-frontends/drx39xyj/drxj.h index 47a0e3c..15b2bb0 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.h +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.h @@ -53,7 +53,7 @@ extern "C" { /* Multi master mode and short addr format only will not work. RMW, CRC reset, broadcast and switching back to single master mode cannot be done with short addr only in multi master mode. */ -#if ((DRXDAP_SINGLE_MASTER==0)&&(DRXDAPFASI_LONG_ADDR_ALLOWED==0)) +#if ((DRXDAP_SINGLE_MASTER == 0) && (DRXDAPFASI_LONG_ADDR_ALLOWED == 0)) #error "Multi master mode and short addressing only is an illegal combination" *; /* Generate a fatal compiler error to make sure it stops here, this is necesarry because not all compilers stop after a #error. */ @@ -590,7 +590,7 @@ Access MACROS * */ -#define DRXJ_ATTR_BTSC_DETECT( d ) \ +#define DRXJ_ATTR_BTSC_DETECT(d) \ (((pDRXJData_t)(d)->myExtAttr)->audData.btscDetect) /** @@ -604,15 +604,15 @@ Access MACROS * substituted by "direct-access-inline-code" or a function call. * */ -#define DRXJ_GET_BTSC_DETECT( d, x ) \ +#define DRXJ_GET_BTSC_DETECT(d, x) \ do { \ - (x) = DRXJ_ATTR_BTSC_DETECT(( d ); \ - } while(0) + (x) = DRXJ_ATTR_BTSC_DETECT((d); \ + } while (0) -#define DRXJ_SET_BTSC_DETECT( d, x ) \ +#define DRXJ_SET_BTSC_DETECT(d, x) \ do { \ - DRXJ_ATTR_BTSC_DETECT( d ) = (x); \ - } while(0) + DRXJ_ATTR_BTSC_DETECT(d) = (x); \ + } while (0) /*------------------------------------------------------------------------- DEFINES @@ -704,12 +704,12 @@ DEFINES /* Convert OOB lock status to string */ #define DRXJ_STR_OOB_LOCKSTATUS(x) ( \ - ( x == DRX_NEVER_LOCK ) ? "Never" : \ - ( x == DRX_NOT_LOCKED ) ? "No" : \ - ( x == DRX_LOCKED ) ? "Locked" : \ - ( x == DRX_LOCK_STATE_1 ) ? "AGC lock" : \ - ( x == DRX_LOCK_STATE_2 ) ? "sync lock" : \ - "(Invalid)" ) + (x == DRX_NEVER_LOCK) ? "Never" : \ + (x == DRX_NOT_LOCKED) ? "No" : \ + (x == DRX_LOCKED) ? "Locked" : \ + (x == DRX_LOCK_STATE_1) ? "AGC lock" : \ + (x == DRX_LOCK_STATE_2) ? "sync lock" : \ + "(Invalid)") /*------------------------------------------------------------------------- ENUM -- cgit v1.1 From 57afe2f0bb0cca758701679f141c9fa92a034415 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Thu, 16 Jan 2014 11:24:57 -0300 Subject: [media] drx-j: Don't use CamelCase There's no reason at all to use CamelCase here. Convert all of them to normal case. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h | 64 +- drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h | 122 +- drivers/media/dvb-frontends/drx39xyj/drx39xxj.c | 138 +- drivers/media/dvb-frontends/drx39xyj/drx39xxj.h | 2 +- .../media/dvb-frontends/drx39xyj/drx39xxj_dummy.c | 72 +- .../media/dvb-frontends/drx39xyj/drx_dap_fasi.c | 302 +- .../media/dvb-frontends/drx39xyj/drx_dap_fasi.h | 2 +- drivers/media/dvb-frontends/drx39xyj/drx_driver.c | 924 +- drivers/media/dvb-frontends/drx39xyj/drx_driver.h | 966 +- .../dvb-frontends/drx39xyj/drx_driver_version.h | 4 +- drivers/media/dvb-frontends/drx39xyj/drxj.c | 10746 +++++++++---------- drivers/media/dvb-frontends/drx39xyj/drxj.h | 342 +- drivers/media/dvb-frontends/drx39xyj/drxj_map.h | 4 +- 13 files changed, 6844 insertions(+), 6844 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h b/drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h index 64ebef3..dd2fc797 100644 --- a/drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h +++ b/drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h @@ -48,13 +48,13 @@ #include "bsp_types.h" /* - * This structure contains the I2C address, the device ID and a userData pointer. - * The userData pointer can be used for application specific purposes. + * This structure contains the I2C address, the device ID and a user_data pointer. + * The user_data pointer can be used for application specific purposes. */ struct i2c_device_addr { - u16 i2cAddr; /* The I2C address of the device. */ - u16 i2cDevId; /* The device identifier. */ - void *userData; /* User data pointer */ + u16 i2c_addr; /* The I2C address of the device. */ + u16 i2c_dev_id; /* The device identifier. */ + void *user_data; /* User data pointer */ }; @@ -74,44 +74,44 @@ Exported FUNCTIONS ------------------------------------------------------------------------------*/ /** -* \fn DRXBSP_I2C_Init() +* \fn drxbsp_i2c_init() * \brief Initialize I2C communication module. -* \return DRXStatus_t Return status. +* \return drx_status_t Return status. * \retval DRX_STS_OK Initialization successful. * \retval DRX_STS_ERROR Initialization failed. */ - DRXStatus_t DRXBSP_I2C_Init(void); + drx_status_t drxbsp_i2c_init(void); /** -* \fn DRXBSP_I2C_Term() +* \fn drxbsp_i2c_term() * \brief Terminate I2C communication module. -* \return DRXStatus_t Return status. +* \return drx_status_t Return status. * \retval DRX_STS_OK Termination successful. * \retval DRX_STS_ERROR Termination failed. */ - DRXStatus_t DRXBSP_I2C_Term(void); + drx_status_t drxbsp_i2c_term(void); /** -* \fn DRXStatus_t DRXBSP_I2C_WriteRead( struct i2c_device_addr *wDevAddr, -* u16 wCount, +* \fn drx_status_t drxbsp_i2c_write_read( struct i2c_device_addr *w_dev_addr, +* u16 w_count, * u8 *wData, -* struct i2c_device_addr *rDevAddr, -* u16 rCount, -* u8 *rData) +* struct i2c_device_addr *r_dev_addr, +* u16 r_count, +* u8 *r_data) * \brief Read and/or write count bytes from I2C bus, store them in data[]. -* \param wDevAddr The device i2c address and the device ID to write to -* \param wCount The number of bytes to write +* \param w_dev_addr The device i2c address and the device ID to write to +* \param w_count The number of bytes to write * \param wData The array to write the data to -* \param rDevAddr The device i2c address and the device ID to read from -* \param rCount The number of bytes to read -* \param rData The array to read the data from -* \return DRXStatus_t Return status. +* \param r_dev_addr The device i2c address and the device ID to read from +* \param r_count The number of bytes to read +* \param r_data The array to read the data from +* \return drx_status_t Return status. * \retval DRX_STS_OK Succes. * \retval DRX_STS_ERROR Failure. * \retval DRX_STS_INVALID_ARG Parameter 'wcount' is not zero but parameter * 'wdata' contains NULL. * Idem for 'rcount' and 'rdata'. -* Both wDevAddr and rDevAddr are NULL. +* Both w_dev_addr and r_dev_addr are NULL. * * This function must implement an atomic write and/or read action on the I2C bus * No other process may use the I2C bus when this function is executing. @@ -121,25 +121,25 @@ Exported FUNCTIONS * The device ID can be useful if several devices share an I2C address. * It can be used to control a "switch" on the I2C bus to the correct device. */ - DRXStatus_t DRXBSP_I2C_WriteRead(struct i2c_device_addr *wDevAddr, - u16 wCount, + drx_status_t drxbsp_i2c_write_read(struct i2c_device_addr *w_dev_addr, + u16 w_count, u8 *wData, - struct i2c_device_addr *rDevAddr, - u16 rCount, u8 *rData); + struct i2c_device_addr *r_dev_addr, + u16 r_count, u8 *r_data); /** -* \fn DRXBSP_I2C_ErrorText() +* \fn drxbsp_i2c_error_text() * \brief Returns a human readable error. -* Counter part of numerical DRX_I2C_Error_g. +* Counter part of numerical drx_i2c_error_g. * * \return char* Pointer to human readable error text. */ - char *DRXBSP_I2C_ErrorText(void); + char *drxbsp_i2c_error_text(void); /** -* \var DRX_I2C_Error_g; +* \var drx_i2c_error_g; * \brief I2C specific error codes, platform dependent. */ - extern int DRX_I2C_Error_g; + extern int drx_i2c_error_g; #endif /* __BSPI2C_H__ */ diff --git a/drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h b/drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h index 3b9adf9..0016ba7 100644 --- a/drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h +++ b/drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h @@ -79,90 +79,90 @@ DEFINES TYPEDEFS ------------------------------------------------------------------------------*/ - typedef u32 TUNERMode_t; - typedef u32 *pTUNERMode_t; + typedef u32 tuner_mode_t; + typedef u32 *ptuner_mode_t; - typedef char *TUNERSubMode_t; /* description of submode */ - typedef TUNERSubMode_t *pTUNERSubMode_t; + typedef char *tuner_sub_mode_t; /* description of submode */ + typedef tuner_sub_mode_t *ptuner_sub_mode_t; typedef enum { TUNER_LOCKED, TUNER_NOT_LOCKED - } TUNERLockStatus_t, *pTUNERLockStatus_t; + } tuner_lock_status_t, *ptuner_lock_status_t; typedef struct { char *name; /* Tuner brand & type name */ - s32 minFreqRF; /* Lowest RF input frequency, in kHz */ - s32 maxFreqRF; /* Highest RF input frequency, in kHz */ + s32 min_freq_rf; /* Lowest RF input frequency, in kHz */ + s32 max_freq_rf; /* Highest RF input frequency, in kHz */ - u8 subMode; /* Index to sub-mode in use */ - pTUNERSubMode_t subModeDescriptions; /* Pointer to description of sub-modes */ - u8 subModes; /* Number of available sub-modes */ + u8 sub_mode; /* Index to sub-mode in use */ + ptuner_sub_mode_t sub_modeDescriptions; /* Pointer to description of sub-modes */ + u8 sub_modes; /* Number of available sub-modes */ /* The following fields will be either 0, NULL or false and do not need initialisation */ - void *selfCheck; /* gives proof of initialization */ - bool programmed; /* only valid if selfCheck is OK */ - s32 RFfrequency; /* only valid if programmed */ - s32 IFfrequency; /* only valid if programmed */ + void *self_check; /* gives proof of initialization */ + bool programmed; /* only valid if self_check is OK */ + s32 r_ffrequency; /* only valid if programmed */ + s32 i_ffrequency; /* only valid if programmed */ - void *myUserData; /* pointer to associated demod instance */ - u16 myCapabilities; /* value for storing application flags */ + void *myUser_data; /* pointer to associated demod instance */ + u16 my_capabilities; /* value for storing application flags */ - } TUNERCommonAttr_t, *pTUNERCommonAttr_t; + } tuner_common_attr_t, *ptuner_common_attr_t; /* * Generic functions for DRX devices. */ - typedef struct TUNERInstance_s *pTUNERInstance_t; + typedef struct tuner_instance_s *p_tuner_instance_t; - typedef DRXStatus_t(*TUNEROpenFunc_t) (pTUNERInstance_t tuner); - typedef DRXStatus_t(*TUNERCloseFunc_t) (pTUNERInstance_t tuner); + typedef drx_status_t(*tuner_open_func_t) (p_tuner_instance_t tuner); + typedef drx_status_t(*tuner_close_func_t) (p_tuner_instance_t tuner); - typedef DRXStatus_t(*TUNERSetFrequencyFunc_t) (pTUNERInstance_t tuner, - TUNERMode_t mode, + typedef drx_status_t(*tuner_set_frequency_func_t) (p_tuner_instance_t tuner, + tuner_mode_t mode, s32 frequency); - typedef DRXStatus_t(*TUNERGetFrequencyFunc_t) (pTUNERInstance_t tuner, - TUNERMode_t mode, + typedef drx_status_t(*tuner_get_frequency_func_t) (p_tuner_instance_t tuner, + tuner_mode_t mode, s32 * - RFfrequency, + r_ffrequency, s32 * - IFfrequency); + i_ffrequency); - typedef DRXStatus_t(*TUNERLockStatusFunc_t) (pTUNERInstance_t tuner, - pTUNERLockStatus_t - lockStat); + typedef drx_status_t(*tuner_lock_status_func_t) (p_tuner_instance_t tuner, + ptuner_lock_status_t + lock_stat); - typedef DRXStatus_t(*TUNERi2cWriteReadFunc_t) (pTUNERInstance_t tuner, + typedef drx_status_t(*tune_ri2c_write_read_func_t) (p_tuner_instance_t tuner, struct i2c_device_addr * - wDevAddr, u16 wCount, + w_dev_addr, u16 w_count, u8 *wData, struct i2c_device_addr * - rDevAddr, u16 rCount, - u8 *rData); + r_dev_addr, u16 r_count, + u8 *r_data); typedef struct { - TUNEROpenFunc_t openFunc; - TUNERCloseFunc_t closeFunc; - TUNERSetFrequencyFunc_t setFrequencyFunc; - TUNERGetFrequencyFunc_t getFrequencyFunc; - TUNERLockStatusFunc_t lockStatusFunc; - TUNERi2cWriteReadFunc_t i2cWriteReadFunc; + tuner_open_func_t open_func; + tuner_close_func_t close_func; + tuner_set_frequency_func_t set_frequency_func; + tuner_get_frequency_func_t get_frequency_func; + tuner_lock_status_func_t lock_statusFunc; + tune_ri2c_write_read_func_t i2c_write_read_func; - } TUNERFunc_t, *pTUNERFunc_t; + } tuner_func_t, *ptuner_func_t; - typedef struct TUNERInstance_s { + typedef struct tuner_instance_s { - struct i2c_device_addr myI2CDevAddr; - pTUNERCommonAttr_t myCommonAttr; - void *myExtAttr; - pTUNERFunc_t myFunct; + struct i2c_device_addr my_i2c_dev_addr; + ptuner_common_attr_t my_common_attr; + void *my_ext_attr; + ptuner_func_t my_funct; - } TUNERInstance_t; + } tuner_instance_t; /*------------------------------------------------------------------------------ ENUM @@ -176,28 +176,28 @@ STRUCTS Exported FUNCTIONS ------------------------------------------------------------------------------*/ - DRXStatus_t DRXBSP_TUNER_Open(pTUNERInstance_t tuner); + drx_status_t drxbsp_tuner_open(p_tuner_instance_t tuner); - DRXStatus_t DRXBSP_TUNER_Close(pTUNERInstance_t tuner); + drx_status_t drxbsp_tuner_close(p_tuner_instance_t tuner); - DRXStatus_t DRXBSP_TUNER_SetFrequency(pTUNERInstance_t tuner, - TUNERMode_t mode, + drx_status_t drxbsp_tuner_set_frequency(p_tuner_instance_t tuner, + tuner_mode_t mode, s32 frequency); - DRXStatus_t DRXBSP_TUNER_GetFrequency(pTUNERInstance_t tuner, - TUNERMode_t mode, - s32 *RFfrequency, - s32 *IFfrequency); + drx_status_t drxbsp_tuner_get_frequency(p_tuner_instance_t tuner, + tuner_mode_t mode, + s32 *r_ffrequency, + s32 *i_ffrequency); - DRXStatus_t DRXBSP_TUNER_LockStatus(pTUNERInstance_t tuner, - pTUNERLockStatus_t lockStat); + drx_status_t drxbsp_tuner_lock_status(p_tuner_instance_t tuner, + ptuner_lock_status_t lock_stat); - DRXStatus_t DRXBSP_TUNER_DefaultI2CWriteRead(pTUNERInstance_t tuner, - struct i2c_device_addr *wDevAddr, - u16 wCount, + drx_status_t drxbsp_tuner_default_i2c_write_read(p_tuner_instance_t tuner, + struct i2c_device_addr *w_dev_addr, + u16 w_count, u8 *wData, - struct i2c_device_addr *rDevAddr, - u16 rCount, u8 *rData); + struct i2c_device_addr *r_dev_addr, + u16 r_count, u8 *r_data); /*------------------------------------------------------------------------------ THE END diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c index 414d152..d80ef7e 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c @@ -33,16 +33,16 @@ static int drx39xxj_set_powerstate(struct dvb_frontend *fe, int enable) { struct drx39xxj_state *state = fe->demodulator_priv; - DRXDemodInstance_t *demod = state->demod; + drx_demod_instance_t *demod = state->demod; int result; - DRXPowerMode_t powerMode; + drx_power_mode_t power_mode; if (enable) - powerMode = DRX_POWER_UP; + power_mode = DRX_POWER_UP; else - powerMode = DRX_POWER_DOWN; + power_mode = DRX_POWER_DOWN; - result = DRX_Ctrl(demod, DRX_CTRL_POWER_MODE, &powerMode); + result = drx_ctrl(demod, DRX_CTRL_POWER_MODE, &power_mode); if (result != DRX_STS_OK) { printk(KERN_ERR "Power state change failed\n"); return 0; @@ -55,13 +55,13 @@ static int drx39xxj_set_powerstate(struct dvb_frontend *fe, int enable) static int drx39xxj_read_status(struct dvb_frontend *fe, fe_status_t *status) { struct drx39xxj_state *state = fe->demodulator_priv; - DRXDemodInstance_t *demod = state->demod; + drx_demod_instance_t *demod = state->demod; int result; - DRXLockStatus_t lock_status; + drx_lock_status_t lock_status; *status = 0; - result = DRX_Ctrl(demod, DRX_CTRL_LOCK_STATUS, &lock_status); + result = drx_ctrl(demod, DRX_CTRL_LOCK_STATUS, &lock_status); if (result != DRX_STS_OK) { printk(KERN_ERR "drx39xxj: could not get lock status!\n"); *status = 0; @@ -102,18 +102,18 @@ static int drx39xxj_read_status(struct dvb_frontend *fe, fe_status_t *status) static int drx39xxj_read_ber(struct dvb_frontend *fe, u32 *ber) { struct drx39xxj_state *state = fe->demodulator_priv; - DRXDemodInstance_t *demod = state->demod; + drx_demod_instance_t *demod = state->demod; int result; - DRXSigQuality_t sig_quality; + drx_sig_quality_t sig_quality; - result = DRX_Ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); + result = drx_ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); if (result != DRX_STS_OK) { printk(KERN_ERR "drx39xxj: could not get ber!\n"); *ber = 0; return 0; } - *ber = sig_quality.postReedSolomonBER; + *ber = sig_quality.post_reed_solomon_ber; return 0; } @@ -121,11 +121,11 @@ static int drx39xxj_read_signal_strength(struct dvb_frontend *fe, u16 *strength) { struct drx39xxj_state *state = fe->demodulator_priv; - DRXDemodInstance_t *demod = state->demod; + drx_demod_instance_t *demod = state->demod; int result; - DRXSigQuality_t sig_quality; + drx_sig_quality_t sig_quality; - result = DRX_Ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); + result = drx_ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); if (result != DRX_STS_OK) { printk(KERN_ERR "drx39xxj: could not get signal strength!\n"); *strength = 0; @@ -140,11 +140,11 @@ static int drx39xxj_read_signal_strength(struct dvb_frontend *fe, static int drx39xxj_read_snr(struct dvb_frontend *fe, u16 *snr) { struct drx39xxj_state *state = fe->demodulator_priv; - DRXDemodInstance_t *demod = state->demod; + drx_demod_instance_t *demod = state->demod; int result; - DRXSigQuality_t sig_quality; + drx_sig_quality_t sig_quality; - result = DRX_Ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); + result = drx_ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); if (result != DRX_STS_OK) { printk(KERN_ERR "drx39xxj: could not read snr!\n"); *snr = 0; @@ -158,18 +158,18 @@ static int drx39xxj_read_snr(struct dvb_frontend *fe, u16 *snr) static int drx39xxj_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) { struct drx39xxj_state *state = fe->demodulator_priv; - DRXDemodInstance_t *demod = state->demod; + drx_demod_instance_t *demod = state->demod; int result; - DRXSigQuality_t sig_quality; + drx_sig_quality_t sig_quality; - result = DRX_Ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); + result = drx_ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); if (result != DRX_STS_OK) { printk(KERN_ERR "drx39xxj: could not get uc blocks!\n"); *ucblocks = 0; return 0; } - *ucblocks = sig_quality.packetError; + *ucblocks = sig_quality.packet_error; return 0; } @@ -180,12 +180,12 @@ static int drx39xxj_set_frontend(struct dvb_frontend *fe) #endif struct dtv_frontend_properties *p = &fe->dtv_property_cache; struct drx39xxj_state *state = fe->demodulator_priv; - DRXDemodInstance_t *demod = state->demod; + drx_demod_instance_t *demod = state->demod; enum drx_standard standard = DRX_STANDARD_8VSB; - DRXChannel_t channel; + drx_channel_t channel; int result; - DRXUIOData_t uioData; - DRXChannel_t defChannel = { /* frequency */ 0, + drxuio_data_t uio_data; + drx_channel_t def_channel = { /* frequency */ 0, /* bandwidth */ DRX_BANDWIDTH_6MHZ, /* mirror */ DRX_MIRROR_NO, /* constellation */ DRX_CONSTELLATION_AUTO, @@ -216,7 +216,7 @@ static int drx39xxj_set_frontend(struct dvb_frontend *fe) if (standard != state->current_standard || state->powered_up == 0) { /* Set the standard (will be powered up if necessary */ - result = DRX_Ctrl(demod, DRX_CTRL_SET_STANDARD, &standard); + result = drx_ctrl(demod, DRX_CTRL_SET_STANDARD, &standard); if (result != DRX_STS_OK) { printk(KERN_ERR "Failed to set standard! result=%02x\n", result); @@ -227,21 +227,21 @@ static int drx39xxj_set_frontend(struct dvb_frontend *fe) } /* set channel parameters */ - channel = defChannel; + channel = def_channel; channel.frequency = p->frequency / 1000; channel.bandwidth = DRX_BANDWIDTH_6MHZ; channel.constellation = DRX_CONSTELLATION_AUTO; /* program channel */ - result = DRX_Ctrl(demod, DRX_CTRL_SET_CHANNEL, &channel); + result = drx_ctrl(demod, DRX_CTRL_SET_CHANNEL, &channel); if (result != DRX_STS_OK) { printk(KERN_ERR "Failed to set channel!\n"); return -EINVAL; } /* Just for giggles, let's shut off the LNA again.... */ - uioData.uio = DRX_UIO1; - uioData.value = false; - result = DRX_Ctrl(demod, DRX_CTRL_UIO_WRITE, &uioData); + uio_data.uio = DRX_UIO1; + uio_data.value = false; + result = drx_ctrl(demod, DRX_CTRL_UIO_WRITE, &uio_data); if (result != DRX_STS_OK) { printk(KERN_ERR "Failed to disable LNA!\n"); return 0; @@ -268,7 +268,7 @@ static int drx39xxj_sleep(struct dvb_frontend *fe) static int drx39xxj_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) { struct drx39xxj_state *state = fe->demodulator_priv; - DRXDemodInstance_t *demod = state->demod; + drx_demod_instance_t *demod = state->demod; bool i2c_gate_state; int result; @@ -287,7 +287,7 @@ static int drx39xxj_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) return 0; } - result = DRX_Ctrl(demod, DRX_CTRL_I2C_BRIDGE, &i2c_gate_state); + result = drx_ctrl(demod, DRX_CTRL_I2C_BRIDGE, &i2c_gate_state); if (result != DRX_STS_OK) { printk(KERN_ERR "drx39xxj: could not open i2c gate [%d]\n", result); @@ -325,12 +325,12 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) { struct drx39xxj_state *state = NULL; - struct i2c_device_addr *demodAddr = NULL; - DRXCommonAttr_t *demodCommAttr = NULL; - DRXJData_t *demodExtAttr = NULL; - DRXDemodInstance_t *demod = NULL; - DRXUIOCfg_t uioCfg; - DRXUIOData_t uioData; + struct i2c_device_addr *demod_addr = NULL; + drx_common_attr_t *demod_comm_attr = NULL; + drxj_data_t *demod_ext_attr = NULL; + drx_demod_instance_t *demod = NULL; + drxuio_cfg_t uio_cfg; + drxuio_data_t uio_data; int result; /* allocate memory for the internal state */ @@ -338,50 +338,50 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) if (state == NULL) goto error; - demod = kmalloc(sizeof(DRXDemodInstance_t), GFP_KERNEL); + demod = kmalloc(sizeof(drx_demod_instance_t), GFP_KERNEL); if (demod == NULL) goto error; - demodAddr = kmalloc(sizeof(struct i2c_device_addr), GFP_KERNEL); - if (demodAddr == NULL) + demod_addr = kmalloc(sizeof(struct i2c_device_addr), GFP_KERNEL); + if (demod_addr == NULL) goto error; - demodCommAttr = kmalloc(sizeof(DRXCommonAttr_t), GFP_KERNEL); - if (demodCommAttr == NULL) + demod_comm_attr = kmalloc(sizeof(drx_common_attr_t), GFP_KERNEL); + if (demod_comm_attr == NULL) goto error; - demodExtAttr = kmalloc(sizeof(DRXJData_t), GFP_KERNEL); - if (demodExtAttr == NULL) + demod_ext_attr = kmalloc(sizeof(drxj_data_t), GFP_KERNEL); + if (demod_ext_attr == NULL) goto error; /* setup the state */ state->i2c = i2c; state->demod = demod; - memcpy(demod, &DRXJDefaultDemod_g, sizeof(DRXDemodInstance_t)); + memcpy(demod, &drxj_default_demod_g, sizeof(drx_demod_instance_t)); - demod->myI2CDevAddr = demodAddr; - memcpy(demod->myI2CDevAddr, &DRXJDefaultAddr_g, + demod->my_i2c_dev_addr = demod_addr; + memcpy(demod->my_i2c_dev_addr, &drxj_default_addr_g, sizeof(struct i2c_device_addr)); - demod->myI2CDevAddr->userData = state; - demod->myCommonAttr = demodCommAttr; - memcpy(demod->myCommonAttr, &DRXJDefaultCommAttr_g, - sizeof(DRXCommonAttr_t)); - demod->myCommonAttr->microcode = DRXJ_MC_MAIN; + demod->my_i2c_dev_addr->user_data = state; + demod->my_common_attr = demod_comm_attr; + memcpy(demod->my_common_attr, &drxj_default_comm_attr_g, + sizeof(drx_common_attr_t)); + demod->my_common_attr->microcode = DRXJ_MC_MAIN; #if 0 - demod->myCommonAttr->verifyMicrocode = false; + demod->my_common_attr->verify_microcode = false; #endif - demod->myCommonAttr->verifyMicrocode = true; - demod->myCommonAttr->intermediateFreq = 5000; + demod->my_common_attr->verify_microcode = true; + demod->my_common_attr->intermediate_freq = 5000; - demod->myExtAttr = demodExtAttr; - memcpy(demod->myExtAttr, &DRXJData_g, sizeof(DRXJData_t)); - ((DRXJData_t *) demod->myExtAttr)->uioSmaTxMode = + demod->my_ext_attr = demod_ext_attr; + memcpy(demod->my_ext_attr, &drxj_data_g, sizeof(drxj_data_t)); + ((drxj_data_t *) demod->my_ext_attr)->uio_sma_tx_mode = DRX_UIO_MODE_READWRITE; - demod->myTuner = NULL; + demod->my_tuner = NULL; - result = DRX_Open(demod); + result = drx_open(demod); if (result != DRX_STS_OK) { printk(KERN_ERR "DRX open failed! Aborting\n"); kfree(state); @@ -389,18 +389,18 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) } /* Turn off the LNA */ - uioCfg.uio = DRX_UIO1; - uioCfg.mode = DRX_UIO_MODE_READWRITE; + uio_cfg.uio = DRX_UIO1; + uio_cfg.mode = DRX_UIO_MODE_READWRITE; /* Configure user-I/O #3: enable read/write */ - result = DRX_Ctrl(demod, DRX_CTRL_UIO_CFG, &uioCfg); + result = drx_ctrl(demod, DRX_CTRL_UIO_CFG, &uio_cfg); if (result != DRX_STS_OK) { printk(KERN_ERR "Failed to setup LNA GPIO!\n"); return NULL; } - uioData.uio = DRX_UIO1; - uioData.value = false; - result = DRX_Ctrl(demod, DRX_CTRL_UIO_WRITE, &uioData); + uio_data.uio = DRX_UIO1; + uio_data.value = false; + result = drx_ctrl(demod, DRX_CTRL_UIO_WRITE, &uio_data); if (result != DRX_STS_OK) { printk(KERN_ERR "Failed to disable LNA!\n"); return NULL; diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h index 212aee8..30657c8 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h @@ -28,7 +28,7 @@ struct drx39xxj_state { struct i2c_adapter *i2c; - DRXDemodInstance_t *demod; + drx_demod_instance_t *demod; enum drx_standard current_standard; struct dvb_frontend frontend; int powered_up:1; diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c b/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c index 7e3e00e..61e04c6 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c @@ -11,90 +11,90 @@ #include "drx39xxj.h" /* Dummy function to satisfy drxj.c */ -int DRXBSP_TUNER_Open(struct tuner_instance *tuner) +int drxbsp_tuner_open(struct tuner_instance *tuner) { return DRX_STS_OK; } -int DRXBSP_TUNER_Close(struct tuner_instance *tuner) +int drxbsp_tuner_close(struct tuner_instance *tuner) { return DRX_STS_OK; } -int DRXBSP_TUNER_SetFrequency(struct tuner_instance *tuner, +int drxbsp_tuner_set_frequency(struct tuner_instance *tuner, u32 mode, - s32 centerFrequency) + s32 center_frequency) { return DRX_STS_OK; } int -DRXBSP_TUNER_GetFrequency(struct tuner_instance *tuner, +drxbsp_tuner_get_frequency(struct tuner_instance *tuner, u32 mode, - s32 *RFfrequency, - s32 *IFfrequency) + s32 *r_ffrequency, + s32 *i_ffrequency) { return DRX_STS_OK; } -int DRXBSP_HST_Sleep(u32 n) +int drxbsp_hst_sleep(u32 n) { msleep(n); return DRX_STS_OK; } -u32 DRXBSP_HST_Clock(void) +u32 drxbsp_hst_clock(void) { return jiffies_to_msecs(jiffies); } -int DRXBSP_HST_Memcmp(void *s1, void *s2, u32 n) +int drxbsp_hst_memcmp(void *s1, void *s2, u32 n) { return (memcmp(s1, s2, (size_t) n)); } -void *DRXBSP_HST_Memcpy(void *to, void *from, u32 n) +void *drxbsp_hst_memcpy(void *to, void *from, u32 n) { return (memcpy(to, from, (size_t) n)); } -int DRXBSP_I2C_WriteRead(struct i2c_device_addr *wDevAddr, - u16 wCount, +int drxbsp_i2c_write_read(struct i2c_device_addr *w_dev_addr, + u16 w_count, u8 *wData, - struct i2c_device_addr *rDevAddr, - u16 rCount, u8 *rData) + struct i2c_device_addr *r_dev_addr, + u16 r_count, u8 *r_data) { struct drx39xxj_state *state; struct i2c_msg msg[2]; unsigned int num_msgs; - if (wDevAddr == NULL) { + if (w_dev_addr == NULL) { /* Read only */ - state = rDevAddr->userData; - msg[0].addr = rDevAddr->i2cAddr >> 1; + state = r_dev_addr->user_data; + msg[0].addr = r_dev_addr->i2c_addr >> 1; msg[0].flags = I2C_M_RD; - msg[0].buf = rData; - msg[0].len = rCount; + msg[0].buf = r_data; + msg[0].len = r_count; num_msgs = 1; - } else if (rDevAddr == NULL) { + } else if (r_dev_addr == NULL) { /* Write only */ - state = wDevAddr->userData; - msg[0].addr = wDevAddr->i2cAddr >> 1; + state = w_dev_addr->user_data; + msg[0].addr = w_dev_addr->i2c_addr >> 1; msg[0].flags = 0; msg[0].buf = wData; - msg[0].len = wCount; + msg[0].len = w_count; num_msgs = 1; } else { /* Both write and read */ - state = wDevAddr->userData; - msg[0].addr = wDevAddr->i2cAddr >> 1; + state = w_dev_addr->user_data; + msg[0].addr = w_dev_addr->i2c_addr >> 1; msg[0].flags = 0; msg[0].buf = wData; - msg[0].len = wCount; - msg[1].addr = rDevAddr->i2cAddr >> 1; + msg[0].len = w_count; + msg[1].addr = r_dev_addr->i2c_addr >> 1; msg[1].flags = I2C_M_RD; - msg[1].buf = rData; - msg[1].len = rCount; + msg[1].buf = r_data; + msg[1].len = r_count; num_msgs = 2; } @@ -110,17 +110,17 @@ int DRXBSP_I2C_WriteRead(struct i2c_device_addr *wDevAddr, return DRX_STS_OK; #ifdef DJH_DEBUG - struct drx39xxj_state *state = wDevAddr->userData; + struct drx39xxj_state *state = w_dev_addr->user_data; struct i2c_msg msg[2] = { - {.addr = wDevAddr->i2cAddr, - .flags = 0, .buf = wData, .len = wCount}, - {.addr = rDevAddr->i2cAddr, - .flags = I2C_M_RD, .buf = rData, .len = rCount}, + {.addr = w_dev_addr->i2c_addr, + .flags = 0, .buf = wData, .len = w_count}, + {.addr = r_dev_addr->i2c_addr, + .flags = I2C_M_RD, .buf = r_data, .len = r_count}, }; printk("drx3933 i2c operation addr=%x i2c=%p, wc=%x rc=%x\n", - wDevAddr->i2cAddr, state->i2c, wCount, rCount); + w_dev_addr->i2c_addr, state->i2c, w_count, r_count); if (i2c_transfer(state->i2c, msg, 2) != 2) { printk(KERN_WARNING "drx3933: I2C write/read failed\n"); diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c index 8ec9cc7..71805b4 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c @@ -50,133 +50,133 @@ *******************************************************************************/ #include "drx_dap_fasi.h" -#include "drx_driver.h" /* for DRXBSP_HST_Memcpy() */ +#include "drx_driver.h" /* for drxbsp_hst_memcpy() */ /*============================================================================*/ /* Function prototypes */ -static int DRXDAP_FASI_WriteBlock(struct i2c_device_addr *devAddr, /* address of I2C device */ - DRXaddr_t addr, /* address of register/memory */ +static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr, /* address of I2C device */ + dr_xaddr_t addr, /* address of register/memory */ u16 datasize, /* size of data */ u8 *data, /* data to send */ - DRXflags_t flags); /* special device flags */ + dr_xflags_t flags); /* special device flags */ -static int DRXDAP_FASI_ReadBlock(struct i2c_device_addr *devAddr, /* address of I2C device */ - DRXaddr_t addr, /* address of register/memory */ +static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr, /* address of I2C device */ + dr_xaddr_t addr, /* address of register/memory */ u16 datasize, /* size of data */ u8 *data, /* data to send */ - DRXflags_t flags); /* special device flags */ + dr_xflags_t flags); /* special device flags */ -static int DRXDAP_FASI_WriteReg8(struct i2c_device_addr *devAddr, /* address of I2C device */ - DRXaddr_t addr, /* address of register */ +static int drxdap_fasi_write_reg8(struct i2c_device_addr *dev_addr, /* address of I2C device */ + dr_xaddr_t addr, /* address of register */ u8 data, /* data to write */ - DRXflags_t flags); /* special device flags */ + dr_xflags_t flags); /* special device flags */ -static int DRXDAP_FASI_ReadReg8(struct i2c_device_addr *devAddr, /* address of I2C device */ - DRXaddr_t addr, /* address of register */ +static int drxdap_fasi_read_reg8(struct i2c_device_addr *dev_addr, /* address of I2C device */ + dr_xaddr_t addr, /* address of register */ u8 *data, /* buffer to receive data */ - DRXflags_t flags); /* special device flags */ + dr_xflags_t flags); /* special device flags */ -static int DRXDAP_FASI_ReadModifyWriteReg8(struct i2c_device_addr *devAddr, /* address of I2C device */ - DRXaddr_t waddr, /* address of register */ - DRXaddr_t raddr, /* address to read back from */ +static int drxdap_fasi_read_modify_write_reg8(struct i2c_device_addr *dev_addr, /* address of I2C device */ + dr_xaddr_t waddr, /* address of register */ + dr_xaddr_t raddr, /* address to read back from */ u8 datain, /* data to send */ u8 *dataout); /* data to receive back */ -static int DRXDAP_FASI_WriteReg16(struct i2c_device_addr *devAddr, /* address of I2C device */ - DRXaddr_t addr, /* address of register */ +static int drxdap_fasi_write_reg16(struct i2c_device_addr *dev_addr, /* address of I2C device */ + dr_xaddr_t addr, /* address of register */ u16 data, /* data to write */ - DRXflags_t flags); /* special device flags */ + dr_xflags_t flags); /* special device flags */ -static int DRXDAP_FASI_ReadReg16(struct i2c_device_addr *devAddr, /* address of I2C device */ - DRXaddr_t addr, /* address of register */ +static int drxdap_fasi_read_reg16(struct i2c_device_addr *dev_addr, /* address of I2C device */ + dr_xaddr_t addr, /* address of register */ u16 *data, /* buffer to receive data */ - DRXflags_t flags); /* special device flags */ + dr_xflags_t flags); /* special device flags */ -static int DRXDAP_FASI_ReadModifyWriteReg16(struct i2c_device_addr *devAddr, /* address of I2C device */ - DRXaddr_t waddr, /* address of register */ - DRXaddr_t raddr, /* address to read back from */ +static int drxdap_fasi_read_modify_write_reg16(struct i2c_device_addr *dev_addr, /* address of I2C device */ + dr_xaddr_t waddr, /* address of register */ + dr_xaddr_t raddr, /* address to read back from */ u16 datain, /* data to send */ u16 *dataout); /* data to receive back */ -static int DRXDAP_FASI_WriteReg32(struct i2c_device_addr *devAddr, /* address of I2C device */ - DRXaddr_t addr, /* address of register */ +static int drxdap_fasi_write_reg32(struct i2c_device_addr *dev_addr, /* address of I2C device */ + dr_xaddr_t addr, /* address of register */ u32 data, /* data to write */ - DRXflags_t flags); /* special device flags */ + dr_xflags_t flags); /* special device flags */ -static int DRXDAP_FASI_ReadReg32(struct i2c_device_addr *devAddr, /* address of I2C device */ - DRXaddr_t addr, /* address of register */ +static int drxdap_fasi_read_reg32(struct i2c_device_addr *dev_addr, /* address of I2C device */ + dr_xaddr_t addr, /* address of register */ u32 *data, /* buffer to receive data */ - DRXflags_t flags); /* special device flags */ + dr_xflags_t flags); /* special device flags */ -static int DRXDAP_FASI_ReadModifyWriteReg32(struct i2c_device_addr *devAddr, /* address of I2C device */ - DRXaddr_t waddr, /* address of register */ - DRXaddr_t raddr, /* address to read back from */ +static int drxdap_fasi_read_modify_write_reg32(struct i2c_device_addr *dev_addr, /* address of I2C device */ + dr_xaddr_t waddr, /* address of register */ + dr_xaddr_t raddr, /* address to read back from */ u32 datain, /* data to send */ u32 *dataout); /* data to receive back */ /* The version structure of this protocol implementation */ -char drxDapFASIModuleName[] = "FASI Data Access Protocol"; -char drxDapFASIVersionText[] = ""; +char drx_dap_fasi_module_name[] = "FASI Data Access Protocol"; +char drx_dap_fasi_version_text[] = ""; -DRXVersion_t drxDapFASIVersion = { +drx_version_t drx_dap_fasi_version = { DRX_MODULE_DAP, /**< type identifier of the module */ - drxDapFASIModuleName, /**< name or description of module */ + drx_dap_fasi_module_name, /**< name or description of module */ 0, /**< major version number */ 0, /**< minor version number */ 0, /**< patch version number */ - drxDapFASIVersionText /**< version as text string */ + drx_dap_fasi_version_text /**< version as text string */ }; /* The structure containing the protocol interface */ -DRXAccessFunc_t drxDapFASIFunct_g = { - &drxDapFASIVersion, - DRXDAP_FASI_WriteBlock, /* Supported */ - DRXDAP_FASI_ReadBlock, /* Supported */ - DRXDAP_FASI_WriteReg8, /* Not supported */ - DRXDAP_FASI_ReadReg8, /* Not supported */ - DRXDAP_FASI_ReadModifyWriteReg8, /* Not supported */ - DRXDAP_FASI_WriteReg16, /* Supported */ - DRXDAP_FASI_ReadReg16, /* Supported */ - DRXDAP_FASI_ReadModifyWriteReg16, /* Supported */ - DRXDAP_FASI_WriteReg32, /* Supported */ - DRXDAP_FASI_ReadReg32, /* Supported */ - DRXDAP_FASI_ReadModifyWriteReg32 /* Not supported */ +drx_access_func_t drx_dap_fasi_funct_g = { + &drx_dap_fasi_version, + drxdap_fasi_write_block, /* Supported */ + drxdap_fasi_read_block, /* Supported */ + drxdap_fasi_write_reg8, /* Not supported */ + drxdap_fasi_read_reg8, /* Not supported */ + drxdap_fasi_read_modify_write_reg8, /* Not supported */ + drxdap_fasi_write_reg16, /* Supported */ + drxdap_fasi_read_reg16, /* Supported */ + drxdap_fasi_read_modify_write_reg16, /* Supported */ + drxdap_fasi_write_reg32, /* Supported */ + drxdap_fasi_read_reg32, /* Supported */ + drxdap_fasi_read_modify_write_reg32 /* Not supported */ }; /*============================================================================*/ /* Functions not supported by protocol*/ -static int DRXDAP_FASI_WriteReg8(struct i2c_device_addr *devAddr, /* address of I2C device */ - DRXaddr_t addr, /* address of register */ +static int drxdap_fasi_write_reg8(struct i2c_device_addr *dev_addr, /* address of I2C device */ + dr_xaddr_t addr, /* address of register */ u8 data, /* data to write */ - DRXflags_t flags) + dr_xflags_t flags) { /* special device flags */ return DRX_STS_ERROR; } -static int DRXDAP_FASI_ReadReg8(struct i2c_device_addr *devAddr, /* address of I2C device */ - DRXaddr_t addr, /* address of register */ +static int drxdap_fasi_read_reg8(struct i2c_device_addr *dev_addr, /* address of I2C device */ + dr_xaddr_t addr, /* address of register */ u8 *data, /* buffer to receive data */ - DRXflags_t flags) + dr_xflags_t flags) { /* special device flags */ return DRX_STS_ERROR; } -static int DRXDAP_FASI_ReadModifyWriteReg8(struct i2c_device_addr *devAddr, /* address of I2C device */ - DRXaddr_t waddr, /* address of register */ - DRXaddr_t raddr, /* address to read back from */ +static int drxdap_fasi_read_modify_write_reg8(struct i2c_device_addr *dev_addr, /* address of I2C device */ + dr_xaddr_t waddr, /* address of register */ + dr_xaddr_t raddr, /* address to read back from */ u8 datain, /* data to send */ u8 *dataout) { /* data to receive back */ return DRX_STS_ERROR; } -static int DRXDAP_FASI_ReadModifyWriteReg32(struct i2c_device_addr *devAddr, /* address of I2C device */ - DRXaddr_t waddr, /* address of register */ - DRXaddr_t raddr, /* address to read back from */ +static int drxdap_fasi_read_modify_write_reg32(struct i2c_device_addr *dev_addr, /* address of I2C device */ + dr_xaddr_t waddr, /* address of register */ + dr_xaddr_t raddr, /* address to read back from */ u32 datain, /* data to send */ u32 *dataout) { /* data to receive back */ @@ -187,12 +187,12 @@ static int DRXDAP_FASI_ReadModifyWriteReg32(struct i2c_device_addr *devAddr, /* /****************************** * -* int DRXDAP_FASI_ReadBlock ( -* struct i2c_device_addr *devAddr, -- address of I2C device -* DRXaddr_t addr, -- address of chip register/memory +* int drxdap_fasi_read_block ( +* struct i2c_device_addr *dev_addr, -- address of I2C device +* dr_xaddr_t addr, -- address of chip register/memory * u16 datasize, -- number of bytes to read * u8 *data, -- data to receive -* DRXflags_t flags) -- special device flags +* dr_xflags_t flags) -- special device flags * * Read block data from chip address. Because the chip is word oriented, * the number of bytes to read must be even. @@ -210,28 +210,28 @@ static int DRXDAP_FASI_ReadModifyWriteReg32(struct i2c_device_addr *devAddr, /* * ******************************/ -static int DRXDAP_FASI_ReadBlock(struct i2c_device_addr *devAddr, - DRXaddr_t addr, +static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr, + dr_xaddr_t addr, u16 datasize, - u8 *data, DRXflags_t flags) + u8 *data, dr_xflags_t flags) { u8 buf[4]; u16 bufx; int rc; - u16 overheadSize = 0; + u16 overhead_size = 0; /* Check parameters ******************************************************* */ - if (devAddr == NULL) { + if (dev_addr == NULL) { return DRX_STS_INVALID_ARG; } - overheadSize = (IS_I2C_10BIT(devAddr->i2cAddr) ? 2 : 1) + + overhead_size = (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1) + (DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2); if ((DRXDAP_FASI_OFFSET_TOO_LARGE(addr)) || ((!(DRXDAPFASI_LONG_ADDR_ALLOWED)) && DRXDAP_FASI_LONG_FORMAT(addr)) || - (overheadSize > (DRXDAP_MAX_WCHUNKSIZE)) || + (overhead_size > (DRXDAP_MAX_WCHUNKSIZE)) || ((datasize != 0) && (data == NULL)) || ((datasize & 1) == 1)) { return DRX_STS_INVALID_ARG; } @@ -283,13 +283,13 @@ static int DRXDAP_FASI_ReadBlock(struct i2c_device_addr *devAddr, * In single master mode, split the read and write actions. * No special action is needed for write chunks here. */ - rc = DRXBSP_I2C_WriteRead(devAddr, bufx, buf, 0, 0, 0); + rc = drxbsp_i2c_write_read(dev_addr, bufx, buf, 0, 0, 0); if (rc == DRX_STS_OK) { - rc = DRXBSP_I2C_WriteRead(0, 0, 0, devAddr, todo, data); + rc = drxbsp_i2c_write_read(0, 0, 0, dev_addr, todo, data); } #else /* In multi master mode, do everything in one RW action */ - rc = DRXBSP_I2C_WriteRead(devAddr, bufx, buf, devAddr, todo, + rc = drxbsp_i2c_write_read(dev_addr, bufx, buf, dev_addr, todo, data); #endif data += todo; @@ -302,10 +302,10 @@ static int DRXDAP_FASI_ReadBlock(struct i2c_device_addr *devAddr, /****************************** * -* int DRXDAP_FASI_ReadModifyWriteReg16 ( -* struct i2c_device_addr *devAddr, -- address of I2C device -* DRXaddr_t waddr, -- address of chip register/memory -* DRXaddr_t raddr, -- chip address to read back from +* int drxdap_fasi_read_modify_write_reg16 ( +* struct i2c_device_addr *dev_addr, -- address of I2C device +* dr_xaddr_t waddr, -- address of chip register/memory +* dr_xaddr_t raddr, -- chip address to read back from * u16 wdata, -- data to send * u16 *rdata) -- data to receive back * @@ -325,9 +325,9 @@ static int DRXDAP_FASI_ReadBlock(struct i2c_device_addr *devAddr, * ******************************/ -static int DRXDAP_FASI_ReadModifyWriteReg16(struct i2c_device_addr *devAddr, - DRXaddr_t waddr, - DRXaddr_t raddr, +static int drxdap_fasi_read_modify_write_reg16(struct i2c_device_addr *dev_addr, + dr_xaddr_t waddr, + dr_xaddr_t raddr, u16 wdata, u16 *rdata) { int rc = DRX_STS_ERROR; @@ -337,9 +337,9 @@ static int DRXDAP_FASI_ReadModifyWriteReg16(struct i2c_device_addr *devAddr, return DRX_STS_INVALID_ARG; } - rc = DRXDAP_FASI_WriteReg16(devAddr, waddr, wdata, DRXDAP_FASI_RMW); + rc = drxdap_fasi_write_reg16(dev_addr, waddr, wdata, DRXDAP_FASI_RMW); if (rc == DRX_STS_OK) { - rc = DRXDAP_FASI_ReadReg16(devAddr, raddr, rdata, 0); + rc = drxdap_fasi_read_reg16(dev_addr, raddr, rdata, 0); } #endif @@ -348,11 +348,11 @@ static int DRXDAP_FASI_ReadModifyWriteReg16(struct i2c_device_addr *devAddr, /****************************** * -* int DRXDAP_FASI_ReadReg16 ( -* struct i2c_device_addr *devAddr, -- address of I2C device -* DRXaddr_t addr, -- address of chip register/memory +* int drxdap_fasi_read_reg16 ( +* struct i2c_device_addr *dev_addr, -- address of I2C device +* dr_xaddr_t addr, -- address of chip register/memory * u16 *data, -- data to receive -* DRXflags_t flags) -- special device flags +* dr_xflags_t flags) -- special device flags * * Read one 16-bit register or memory location. The data received back is * converted back to the target platform's endianness. @@ -364,9 +364,9 @@ static int DRXDAP_FASI_ReadModifyWriteReg16(struct i2c_device_addr *devAddr, * ******************************/ -static int DRXDAP_FASI_ReadReg16(struct i2c_device_addr *devAddr, - DRXaddr_t addr, - u16 *data, DRXflags_t flags) +static int drxdap_fasi_read_reg16(struct i2c_device_addr *dev_addr, + dr_xaddr_t addr, + u16 *data, dr_xflags_t flags) { u8 buf[sizeof(*data)]; int rc; @@ -374,18 +374,18 @@ static int DRXDAP_FASI_ReadReg16(struct i2c_device_addr *devAddr, if (!data) { return DRX_STS_INVALID_ARG; } - rc = DRXDAP_FASI_ReadBlock(devAddr, addr, sizeof(*data), buf, flags); + rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags); *data = buf[0] + (((u16) buf[1]) << 8); return rc; } /****************************** * -* int DRXDAP_FASI_ReadReg32 ( -* struct i2c_device_addr *devAddr, -- address of I2C device -* DRXaddr_t addr, -- address of chip register/memory +* int drxdap_fasi_read_reg32 ( +* struct i2c_device_addr *dev_addr, -- address of I2C device +* dr_xaddr_t addr, -- address of chip register/memory * u32 *data, -- data to receive -* DRXflags_t flags) -- special device flags +* dr_xflags_t flags) -- special device flags * * Read one 32-bit register or memory location. The data received back is * converted back to the target platform's endianness. @@ -397,9 +397,9 @@ static int DRXDAP_FASI_ReadReg16(struct i2c_device_addr *devAddr, * ******************************/ -static int DRXDAP_FASI_ReadReg32(struct i2c_device_addr *devAddr, - DRXaddr_t addr, - u32 *data, DRXflags_t flags) +static int drxdap_fasi_read_reg32(struct i2c_device_addr *dev_addr, + dr_xaddr_t addr, + u32 *data, dr_xflags_t flags) { u8 buf[sizeof(*data)]; int rc; @@ -407,7 +407,7 @@ static int DRXDAP_FASI_ReadReg32(struct i2c_device_addr *devAddr, if (!data) { return DRX_STS_INVALID_ARG; } - rc = DRXDAP_FASI_ReadBlock(devAddr, addr, sizeof(*data), buf, flags); + rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags); *data = (((u32) buf[0]) << 0) + (((u32) buf[1]) << 8) + (((u32) buf[2]) << 16) + (((u32) buf[3]) << 24); @@ -416,12 +416,12 @@ static int DRXDAP_FASI_ReadReg32(struct i2c_device_addr *devAddr, /****************************** * -* int DRXDAP_FASI_WriteBlock ( -* struct i2c_device_addr *devAddr, -- address of I2C device -* DRXaddr_t addr, -- address of chip register/memory +* int drxdap_fasi_write_block ( +* struct i2c_device_addr *dev_addr, -- address of I2C device +* dr_xaddr_t addr, -- address of chip register/memory * u16 datasize, -- number of bytes to read * u8 *data, -- data to receive -* DRXflags_t flags) -- special device flags +* dr_xflags_t flags) -- special device flags * * Write block data to chip address. Because the chip is word oriented, * the number of bytes to write must be even. @@ -436,29 +436,29 @@ static int DRXDAP_FASI_ReadReg32(struct i2c_device_addr *devAddr, * ******************************/ -static int DRXDAP_FASI_WriteBlock(struct i2c_device_addr *devAddr, - DRXaddr_t addr, +static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr, + dr_xaddr_t addr, u16 datasize, - u8 *data, DRXflags_t flags) + u8 *data, dr_xflags_t flags) { u8 buf[DRXDAP_MAX_WCHUNKSIZE]; int st = DRX_STS_ERROR; - int firstErr = DRX_STS_OK; - u16 overheadSize = 0; - u16 blockSize = 0; + int first_err = DRX_STS_OK; + u16 overhead_size = 0; + u16 block_size = 0; /* Check parameters ******************************************************* */ - if (devAddr == NULL) { + if (dev_addr == NULL) { return DRX_STS_INVALID_ARG; } - overheadSize = (IS_I2C_10BIT(devAddr->i2cAddr) ? 2 : 1) + + overhead_size = (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1) + (DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2); if ((DRXDAP_FASI_OFFSET_TOO_LARGE(addr)) || ((!(DRXDAPFASI_LONG_ADDR_ALLOWED)) && DRXDAP_FASI_LONG_FORMAT(addr)) || - (overheadSize > (DRXDAP_MAX_WCHUNKSIZE)) || + (overhead_size > (DRXDAP_MAX_WCHUNKSIZE)) || ((datasize != 0) && (data == NULL)) || ((datasize & 1) == 1)) { return DRX_STS_INVALID_ARG; } @@ -470,7 +470,7 @@ static int DRXDAP_FASI_WriteBlock(struct i2c_device_addr *devAddr, #endif /* Write block to I2C ***************************************************** */ - blockSize = ((DRXDAP_MAX_WCHUNKSIZE) - overheadSize) & ~1; + block_size = ((DRXDAP_MAX_WCHUNKSIZE) - overhead_size) & ~1; do { u16 todo = 0; u16 bufx = 0; @@ -505,66 +505,66 @@ static int DRXDAP_FASI_WriteBlock(struct i2c_device_addr *devAddr, #endif /* - In single master mode blockSize can be 0. In such a case this I2C + In single master mode block_size can be 0. In such a case this I2C sequense will be visible: (1) write address {i2c addr, 4 bytes chip address} (2) write data {i2c addr, 4 bytes data } (3) write address (4) write data etc... Addres must be rewriten because HI is reset after data transport and expects an address. */ - todo = (blockSize < datasize ? blockSize : datasize); + todo = (block_size < datasize ? block_size : datasize); if (todo == 0) { - u16 overheadSizeI2cAddr = 0; - u16 dataBlockSize = 0; + u16 overhead_sizeI2cAddr = 0; + u16 data_block_size = 0; - overheadSizeI2cAddr = - (IS_I2C_10BIT(devAddr->i2cAddr) ? 2 : 1); - dataBlockSize = - (DRXDAP_MAX_WCHUNKSIZE - overheadSizeI2cAddr) & ~1; + overhead_sizeI2cAddr = + (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1); + data_block_size = + (DRXDAP_MAX_WCHUNKSIZE - overhead_sizeI2cAddr) & ~1; /* write device address */ - st = DRXBSP_I2C_WriteRead(devAddr, + st = drxbsp_i2c_write_read(dev_addr, (u16) (bufx), buf, (struct i2c_device_addr *) (NULL), 0, (u8 *) (NULL)); - if ((st != DRX_STS_OK) && (firstErr == DRX_STS_OK)) { + if ((st != DRX_STS_OK) && (first_err == DRX_STS_OK)) { /* at the end, return the first error encountered */ - firstErr = st; + first_err = st; } bufx = 0; todo = - (dataBlockSize < - datasize ? dataBlockSize : datasize); + (data_block_size < + datasize ? data_block_size : datasize); } - DRXBSP_HST_Memcpy(&buf[bufx], data, todo); + drxbsp_hst_memcpy(&buf[bufx], data, todo); /* write (address if can do and) data */ - st = DRXBSP_I2C_WriteRead(devAddr, + st = drxbsp_i2c_write_read(dev_addr, (u16) (bufx + todo), buf, (struct i2c_device_addr *) (NULL), 0, (u8 *) (NULL)); - if ((st != DRX_STS_OK) && (firstErr == DRX_STS_OK)) { + if ((st != DRX_STS_OK) && (first_err == DRX_STS_OK)) { /* at the end, return the first error encountered */ - firstErr = st; + first_err = st; } datasize -= todo; data += todo; addr += (todo >> 1); } while (datasize); - return firstErr; + return first_err; } /****************************** * -* int DRXDAP_FASI_WriteReg16 ( -* struct i2c_device_addr *devAddr, -- address of I2C device -* DRXaddr_t addr, -- address of chip register/memory +* int drxdap_fasi_write_reg16 ( +* struct i2c_device_addr *dev_addr, -- address of I2C device +* dr_xaddr_t addr, -- address of chip register/memory * u16 data, -- data to send -* DRXflags_t flags) -- special device flags +* dr_xflags_t flags) -- special device flags * * Write one 16-bit register or memory location. The data being written is * converted from the target platform's endianness to little endian. @@ -575,25 +575,25 @@ static int DRXDAP_FASI_WriteBlock(struct i2c_device_addr *devAddr, * ******************************/ -static int DRXDAP_FASI_WriteReg16(struct i2c_device_addr *devAddr, - DRXaddr_t addr, - u16 data, DRXflags_t flags) +static int drxdap_fasi_write_reg16(struct i2c_device_addr *dev_addr, + dr_xaddr_t addr, + u16 data, dr_xflags_t flags) { u8 buf[sizeof(data)]; buf[0] = (u8) ((data >> 0) & 0xFF); buf[1] = (u8) ((data >> 8) & 0xFF); - return DRXDAP_FASI_WriteBlock(devAddr, addr, sizeof(data), buf, flags); + return drxdap_fasi_write_block(dev_addr, addr, sizeof(data), buf, flags); } /****************************** * -* int DRXDAP_FASI_WriteReg32 ( -* struct i2c_device_addr *devAddr, -- address of I2C device -* DRXaddr_t addr, -- address of chip register/memory +* int drxdap_fasi_write_reg32 ( +* struct i2c_device_addr *dev_addr, -- address of I2C device +* dr_xaddr_t addr, -- address of chip register/memory * u32 data, -- data to send -* DRXflags_t flags) -- special device flags +* dr_xflags_t flags) -- special device flags * * Write one 32-bit register or memory location. The data being written is * converted from the target platform's endianness to little endian. @@ -604,9 +604,9 @@ static int DRXDAP_FASI_WriteReg16(struct i2c_device_addr *devAddr, * ******************************/ -static int DRXDAP_FASI_WriteReg32(struct i2c_device_addr *devAddr, - DRXaddr_t addr, - u32 data, DRXflags_t flags) +static int drxdap_fasi_write_reg32(struct i2c_device_addr *dev_addr, + dr_xaddr_t addr, + u32 data, dr_xflags_t flags) { u8 buf[sizeof(data)]; @@ -615,5 +615,5 @@ static int DRXDAP_FASI_WriteReg32(struct i2c_device_addr *devAddr, buf[2] = (u8) ((data >> 16) & 0xFF); buf[3] = (u8) ((data >> 24) & 0xFF); - return DRXDAP_FASI_WriteBlock(devAddr, addr, sizeof(data), buf, flags); + return drxdap_fasi_write_block(dev_addr, addr, sizeof(data), buf, flags); } diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.h b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.h index 5269657..4152d62 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.h @@ -238,7 +238,7 @@ extern "C" { #endif - extern DRXAccessFunc_t drxDapFASIFunct_g; + extern drx_access_func_t drx_dap_fasi_funct_g; #define DRXDAP_FASI_RMW 0x10000000 #define DRXDAP_FASI_BROADCAST 0x20000000 diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c index c94fd35..847e17a 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c @@ -130,7 +130,7 @@ typedef struct { - bit[15..2]=reserved */ u16 CRC;/**< CRC value of the data block, only valid if CRC flag is set. */ -} DRXUCodeBlockHdr_t, *pDRXUCodeBlockHdr_t; +} drxu_code_block_hdr_t, *pdrxu_code_block_hdr_t; /*------------------------------------------------------------------------------ FUNCTIONS @@ -146,57 +146,57 @@ FUNCTIONS /* Prototype of default scanning function */ static int -ScanFunctionDefault(void *scanContext, - DRXScanCommand_t scanCommand, - pDRXChannel_t scanChannel, bool *getNextChannel); +scan_function_default(void *scan_context, + drx_scan_command_t scan_command, + pdrx_channel_t scan_channel, bool *get_next_channel); /** * \brief Get pointer to scanning function. * \param demod: Pointer to demodulator instance. -* \return DRXScanFunc_t. +* \return drx_scan_func_t. */ -static DRXScanFunc_t GetScanFunction(pDRXDemodInstance_t demod) +static drx_scan_func_t get_scan_function(pdrx_demod_instance_t demod) { - pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); - DRXScanFunc_t scanFunc = (DRXScanFunc_t) (NULL); + pdrx_common_attr_t common_attr = (pdrx_common_attr_t) (NULL); + drx_scan_func_t scan_func = (drx_scan_func_t) (NULL); /* get scan function from common attributes */ - commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; - scanFunc = commonAttr->scanFunction; + common_attr = (pdrx_common_attr_t) demod->my_common_attr; + scan_func = common_attr->scan_function; - if (scanFunc != NULL) { + if (scan_func != NULL) { /* return device-specific scan function if it's not NULL */ - return scanFunc; + return scan_func; } /* otherwise return default scan function in core driver */ - return &ScanFunctionDefault; + return &scan_function_default; } /** * \brief Get Context pointer. * \param demod: Pointer to demodulator instance. -* \param scanContext: Context Pointer. -* \return DRXScanFunc_t. +* \param scan_context: Context Pointer. +* \return drx_scan_func_t. */ -void *GetScanContext(pDRXDemodInstance_t demod, void *scanContext) +void *get_scan_context(pdrx_demod_instance_t demod, void *scan_context) { - pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); + pdrx_common_attr_t common_attr = (pdrx_common_attr_t) (NULL); /* get scan function from common attributes */ - commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; - scanContext = commonAttr->scanContext; + common_attr = (pdrx_common_attr_t) demod->my_common_attr; + scan_context = common_attr->scan_context; - if (scanContext == NULL) { - scanContext = (void *)demod; + if (scan_context == NULL) { + scan_context = (void *)demod; } - return scanContext; + return scan_context; } /** * \brief Wait for lock while scanning. * \param demod: Pointer to demodulator instance. -* \param lockStat: Pointer to bool indicating if end result is lock or not. +* \param lock_stat: Pointer to bool indicating if end result is lock or not. * \return int. * \retval DRX_STS_OK: Success * \retval DRX_STS_ERROR: I2C failure or bsp function failure. @@ -211,46 +211,46 @@ void *GetScanContext(pDRXDemodInstance_t demod, void *scanContext) * In case DRX_NEVER_LOCK is returned the poll-wait will be aborted. * */ -static int ScanWaitForLock(pDRXDemodInstance_t demod, bool *isLocked) +static int scan_wait_for_lock(pdrx_demod_instance_t demod, bool *is_locked) { - bool doneWaiting = false; - DRXLockStatus_t lockState = DRX_NOT_LOCKED; - DRXLockStatus_t desiredLockState = DRX_NOT_LOCKED; - u32 timeoutValue = 0; - u32 startTimeLockStage = 0; - u32 currentTime = 0; - u32 timerValue = 0; - - *isLocked = false; - timeoutValue = (u32) demod->myCommonAttr->scanDemodLockTimeout; - desiredLockState = demod->myCommonAttr->scanDesiredLock; - startTimeLockStage = DRXBSP_HST_Clock(); + bool done_waiting = false; + drx_lock_status_t lock_state = DRX_NOT_LOCKED; + drx_lock_status_t desired_lock_state = DRX_NOT_LOCKED; + u32 timeout_value = 0; + u32 start_time_lock_stage = 0; + u32 current_time = 0; + u32 timer_value = 0; + + *is_locked = false; + timeout_value = (u32) demod->my_common_attr->scan_demod_lock_timeout; + desired_lock_state = demod->my_common_attr->scan_desired_lock; + start_time_lock_stage = drxbsp_hst_clock(); /* Start polling loop, checking for lock & timeout */ - while (doneWaiting == false) { + while (done_waiting == false) { - if (DRX_Ctrl(demod, DRX_CTRL_LOCK_STATUS, &lockState) != + if (drx_ctrl(demod, DRX_CTRL_LOCK_STATUS, &lock_state) != DRX_STS_OK) { return DRX_STS_ERROR; } - currentTime = DRXBSP_HST_Clock(); - - timerValue = currentTime - startTimeLockStage; - if (lockState >= desiredLockState) { - *isLocked = true; - doneWaiting = true; - } /* if ( lockState >= desiredLockState ) .. */ - else if (lockState == DRX_NEVER_LOCK) { - doneWaiting = true; - } /* if ( lockState == DRX_NEVER_LOCK ) .. */ - else if (timerValue > timeoutValue) { - /* lockState == DRX_NOT_LOCKED and timeout */ - doneWaiting = true; + current_time = drxbsp_hst_clock(); + + timer_value = current_time - start_time_lock_stage; + if (lock_state >= desired_lock_state) { + *is_locked = true; + done_waiting = true; + } /* if ( lock_state >= desired_lock_state ) .. */ + else if (lock_state == DRX_NEVER_LOCK) { + done_waiting = true; + } /* if ( lock_state == DRX_NEVER_LOCK ) .. */ + else if (timer_value > timeout_value) { + /* lock_state == DRX_NOT_LOCKED and timeout */ + done_waiting = true; } else { - if (DRXBSP_HST_Sleep(10) != DRX_STS_OK) { + if (drxbsp_hst_sleep(10) != DRX_STS_OK) { return DRX_STS_ERROR; } - } /* if ( timerValue > timeoutValue ) .. */ + } /* if ( timer_value > timeout_value ) .. */ } /* while */ @@ -267,70 +267,70 @@ static int ScanWaitForLock(pDRXDemodInstance_t demod, bool *isLocked) * \retval DRX_STS_OK: Succes. * \retval DRX_STS_INVALID_ARG: Invalid frequency plan. * -* Helper function for CtrlScanNext() function. +* Helper function for ctrl_scan_next() function. * Compute next frequency & index in frequency plan. * Check if scan is ready. * */ static int -ScanPrepareNextScan(pDRXDemodInstance_t demod, s32 skip) +scan_prepare_next_scan(pdrx_demod_instance_t demod, s32 skip) { - pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); - u16 tableIndex = 0; - u16 frequencyPlanSize = 0; - pDRXFrequencyPlan_t frequencyPlan = (pDRXFrequencyPlan_t) (NULL); - s32 nextFrequency = 0; - s32 tunerMinFrequency = 0; - s32 tunerMaxFrequency = 0; - - commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; - tableIndex = commonAttr->scanFreqPlanIndex; - frequencyPlan = commonAttr->scanParam->frequencyPlan; - nextFrequency = commonAttr->scanNextFrequency; - tunerMinFrequency = commonAttr->tunerMinFreqRF; - tunerMaxFrequency = commonAttr->tunerMaxFreqRF; + pdrx_common_attr_t common_attr = (pdrx_common_attr_t) (NULL); + u16 table_index = 0; + u16 frequency_plan_size = 0; + p_drx_frequency_plan_t frequency_plan = (p_drx_frequency_plan_t) (NULL); + s32 next_frequency = 0; + s32 tuner_min_frequency = 0; + s32 tuner_max_frequency = 0; + + common_attr = (pdrx_common_attr_t) demod->my_common_attr; + table_index = common_attr->scan_freq_plan_index; + frequency_plan = common_attr->scan_param->frequency_plan; + next_frequency = common_attr->scan_next_frequency; + tuner_min_frequency = common_attr->tuner_min_freq_rf; + tuner_max_frequency = common_attr->tuner_max_freq_rf; do { /* Search next frequency to scan */ /* always take at least one step */ - (commonAttr->scanChannelsScanned)++; - nextFrequency += frequencyPlan[tableIndex].step; - skip -= frequencyPlan[tableIndex].step; + (common_attr->scan_channelsScanned)++; + next_frequency += frequency_plan[table_index].step; + skip -= frequency_plan[table_index].step; /* and then as many steps necessary to exceed 'skip' without exceeding end of the band */ while ((skip > 0) && - (nextFrequency <= frequencyPlan[tableIndex].last)) { - (commonAttr->scanChannelsScanned)++; - nextFrequency += frequencyPlan[tableIndex].step; - skip -= frequencyPlan[tableIndex].step; + (next_frequency <= frequency_plan[table_index].last)) { + (common_attr->scan_channelsScanned)++; + next_frequency += frequency_plan[table_index].step; + skip -= frequency_plan[table_index].step; } /* reset skip, in case we move to the next band later */ skip = 0; - if (nextFrequency > frequencyPlan[tableIndex].last) { + if (next_frequency > frequency_plan[table_index].last) { /* reached end of this band */ - tableIndex++; - frequencyPlanSize = - commonAttr->scanParam->frequencyPlanSize; - if (tableIndex >= frequencyPlanSize) { + table_index++; + frequency_plan_size = + common_attr->scan_param->frequency_plan_size; + if (table_index >= frequency_plan_size) { /* reached end of frequency plan */ - commonAttr->scanReady = true; + common_attr->scan_ready = true; } else { - nextFrequency = frequencyPlan[tableIndex].first; + next_frequency = frequency_plan[table_index].first; } } - if (nextFrequency > (tunerMaxFrequency)) { + if (next_frequency > (tuner_max_frequency)) { /* reached end of tuner range */ - commonAttr->scanReady = true; + common_attr->scan_ready = true; } - } while ((nextFrequency < tunerMinFrequency) && - (commonAttr->scanReady == false)); + } while ((next_frequency < tuner_min_frequency) && + (common_attr->scan_ready == false)); /* Store new values */ - commonAttr->scanFreqPlanIndex = tableIndex; - commonAttr->scanNextFrequency = nextFrequency; + common_attr->scan_freq_plan_index = table_index; + common_attr->scan_next_frequency = next_frequency; return DRX_STS_OK; } @@ -341,9 +341,9 @@ ScanPrepareNextScan(pDRXDemodInstance_t demod, s32 skip) * \brief Default DTV scanning function. * * \param demod: Pointer to demodulator instance. -* \param scanCommand: Scanning command: INIT, NEXT or STOP. -* \param scanChannel: Channel to check: frequency and bandwidth, others AUTO -* \param getNextChannel: Return true if next frequency is desired at next call +* \param scan_command: Scanning command: INIT, NEXT or STOP. +* \param scan_channel: Channel to check: frequency and bandwidth, others AUTO +* \param get_next_channel: Return true if next frequency is desired at next call * * \return int. * \retval DRX_STS_OK: Channel found, DRX_CTRL_GET_CHANNEL can be used @@ -351,40 +351,40 @@ ScanPrepareNextScan(pDRXDemodInstance_t demod, s32 skip) * \retval DRX_STS_BUSY: Channel not found (yet). * \retval DRX_STS_ERROR: Something went wrong. * -* scanChannel and getNextChannel will be NULL for INIT and STOP. +* scan_channel and get_next_channel will be NULL for INIT and STOP. */ static int -ScanFunctionDefault(void *scanContext, - DRXScanCommand_t scanCommand, - pDRXChannel_t scanChannel, bool *getNextChannel) +scan_function_default(void *scan_context, + drx_scan_command_t scan_command, + pdrx_channel_t scan_channel, bool *get_next_channel) { - pDRXDemodInstance_t demod = NULL; + pdrx_demod_instance_t demod = NULL; int status = DRX_STS_ERROR; - bool isLocked = false; + bool is_locked = false; - demod = (pDRXDemodInstance_t) scanContext; + demod = (pdrx_demod_instance_t) scan_context; - if (scanCommand != DRX_SCAN_COMMAND_NEXT) { + if (scan_command != DRX_SCAN_COMMAND_NEXT) { /* just return OK if not doing "scan next" */ return DRX_STS_OK; } - *getNextChannel = false; + *get_next_channel = false; - status = DRX_Ctrl(demod, DRX_CTRL_SET_CHANNEL, scanChannel); + status = drx_ctrl(demod, DRX_CTRL_SET_CHANNEL, scan_channel); if (status != DRX_STS_OK) { return (status); } - status = ScanWaitForLock(demod, &isLocked); + status = scan_wait_for_lock(demod, &is_locked); if (status != DRX_STS_OK) { return status; } /* done with this channel, move to next one */ - *getNextChannel = true; + *get_next_channel = true; - if (isLocked == false) { + if (is_locked == false) { /* no channel found */ return DRX_STS_BUSY; } @@ -397,7 +397,7 @@ ScanFunctionDefault(void *scanContext, /** * \brief Initialize for channel scan. * \param demod: Pointer to demodulator instance. -* \param scanParam: Pointer to scan parameters. +* \param scan_param: Pointer to scan parameters. * \return int. * \retval DRX_STS_OK: Initialized for scan. * \retval DRX_STS_ERROR: No overlap between frequency plan and tuner @@ -412,131 +412,131 @@ ScanFunctionDefault(void *scanContext, * */ static int -CtrlScanInit(pDRXDemodInstance_t demod, pDRXScanParam_t scanParam) +ctrl_scan_init(pdrx_demod_instance_t demod, p_drx_scan_param_t scan_param) { int status = DRX_STS_ERROR; - pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); - s32 maxTunerFreq = 0; - s32 minTunerFreq = 0; - u16 nrChannelsInPlan = 0; + pdrx_common_attr_t common_attr = (pdrx_common_attr_t) (NULL); + s32 max_tuner_freq = 0; + s32 min_tuner_freq = 0; + u16 nr_channels_in_plan = 0; u16 i = 0; - void *scanContext = NULL; + void *scan_context = NULL; - commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; - commonAttr->scanActive = true; + common_attr = (pdrx_common_attr_t) demod->my_common_attr; + common_attr->scan_active = true; /* invalidate a previous SCAN_INIT */ - commonAttr->scanParam = (pDRXScanParam_t) (NULL); - commonAttr->scanNextFrequency = 0; + common_attr->scan_param = (p_drx_scan_param_t) (NULL); + common_attr->scan_next_frequency = 0; /* Check parameters */ - if (((demod->myTuner == NULL) && - (scanParam->numTries != 1)) || - (scanParam == NULL) || - (scanParam->numTries == 0) || - (scanParam->frequencyPlan == NULL) || - (scanParam->frequencyPlanSize == 0) + if (((demod->my_tuner == NULL) && + (scan_param->num_tries != 1)) || + (scan_param == NULL) || + (scan_param->num_tries == 0) || + (scan_param->frequency_plan == NULL) || + (scan_param->frequency_plan_size == 0) ) { - commonAttr->scanActive = false; + common_attr->scan_active = false; return DRX_STS_INVALID_ARG; } /* Check frequency plan contents */ - maxTunerFreq = commonAttr->tunerMaxFreqRF; - minTunerFreq = commonAttr->tunerMinFreqRF; - for (i = 0; i < (scanParam->frequencyPlanSize); i++) { + max_tuner_freq = common_attr->tuner_max_freq_rf; + min_tuner_freq = common_attr->tuner_min_freq_rf; + for (i = 0; i < (scan_param->frequency_plan_size); i++) { s32 width = 0; - s32 step = scanParam->frequencyPlan[i].step; - s32 firstFreq = scanParam->frequencyPlan[i].first; - s32 lastFreq = scanParam->frequencyPlan[i].last; - s32 minFreq = 0; - s32 maxFreq = 0; + s32 step = scan_param->frequency_plan[i].step; + s32 first_freq = scan_param->frequency_plan[i].first; + s32 last_freq = scan_param->frequency_plan[i].last; + s32 min_freq = 0; + s32 max_freq = 0; if (step <= 0) { /* Step must be positive and non-zero */ - commonAttr->scanActive = false; + common_attr->scan_active = false; return DRX_STS_INVALID_ARG; } - if (firstFreq > lastFreq) { + if (first_freq > last_freq) { /* First center frequency is higher than last center frequency */ - commonAttr->scanActive = false; + common_attr->scan_active = false; return DRX_STS_INVALID_ARG; } - width = lastFreq - firstFreq; + width = last_freq - first_freq; if ((width % step) != 0) { /* Difference between last and first center frequency is not an integer number of steps */ - commonAttr->scanActive = false; + common_attr->scan_active = false; return DRX_STS_INVALID_ARG; } /* Check if frequency plan entry intersects with tuner range */ - if (lastFreq >= minTunerFreq) { - if (firstFreq <= maxTunerFreq) { - if (firstFreq >= minTunerFreq) { - minFreq = firstFreq; + if (last_freq >= min_tuner_freq) { + if (first_freq <= max_tuner_freq) { + if (first_freq >= min_tuner_freq) { + min_freq = first_freq; } else { s32 n = 0; - n = (minTunerFreq - firstFreq) / step; - if (((minTunerFreq - - firstFreq) % step) != 0) { + n = (min_tuner_freq - first_freq) / step; + if (((min_tuner_freq - + first_freq) % step) != 0) { n++; } - minFreq = firstFreq + n * step; + min_freq = first_freq + n * step; } - if (lastFreq <= maxTunerFreq) { - maxFreq = lastFreq; + if (last_freq <= max_tuner_freq) { + max_freq = last_freq; } else { s32 n = 0; - n = (lastFreq - maxTunerFreq) / step; - if (((lastFreq - - maxTunerFreq) % step) != 0) { + n = (last_freq - max_tuner_freq) / step; + if (((last_freq - + max_tuner_freq) % step) != 0) { n++; } - maxFreq = lastFreq - n * step; + max_freq = last_freq - n * step; } } } /* Keep track of total number of channels within tuner range in this frequency plan. */ - if ((minFreq != 0) && (maxFreq != 0)) { - nrChannelsInPlan += - (u16) (((maxFreq - minFreq) / step) + 1); + if ((min_freq != 0) && (max_freq != 0)) { + nr_channels_in_plan += + (u16) (((max_freq - min_freq) / step) + 1); /* Determine first frequency (within tuner range) to scan */ - if (commonAttr->scanNextFrequency == 0) { - commonAttr->scanNextFrequency = minFreq; - commonAttr->scanFreqPlanIndex = i; + if (common_attr->scan_next_frequency == 0) { + common_attr->scan_next_frequency = min_freq; + common_attr->scan_freq_plan_index = i; } } } /* for ( ... ) */ - if (nrChannelsInPlan == 0) { + if (nr_channels_in_plan == 0) { /* Tuner range and frequency plan ranges do not overlap */ - commonAttr->scanActive = false; + common_attr->scan_active = false; return DRX_STS_ERROR; } /* Store parameters */ - commonAttr->scanReady = false; - commonAttr->scanMaxChannels = nrChannelsInPlan; - commonAttr->scanChannelsScanned = 0; - commonAttr->scanParam = scanParam; /* SCAN_NEXT is now allowed */ + common_attr->scan_ready = false; + common_attr->scan_max_channels = nr_channels_in_plan; + common_attr->scan_channelsScanned = 0; + common_attr->scan_param = scan_param; /* SCAN_NEXT is now allowed */ - scanContext = GetScanContext(demod, scanContext); + scan_context = get_scan_context(demod, scan_context); - status = (*(GetScanFunction(demod))) - (scanContext, DRX_SCAN_COMMAND_INIT, NULL, NULL); + status = (*(get_scan_function(demod))) + (scan_context, DRX_SCAN_COMMAND_INIT, NULL, NULL); - commonAttr->scanActive = false; + common_attr->scan_active = false; return DRX_STS_OK; } @@ -551,32 +551,32 @@ CtrlScanInit(pDRXDemodInstance_t demod, pDRXScanParam_t scanParam) * \retval DRX_STS_ERROR: Something went wrong. * \retval DRX_STS_INVALID_ARG: Wrong parameters. */ -static int CtrlScanStop(pDRXDemodInstance_t demod) +static int ctrl_scan_stop(pdrx_demod_instance_t demod) { int status = DRX_STS_ERROR; - pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); - void *scanContext = NULL; + pdrx_common_attr_t common_attr = (pdrx_common_attr_t) (NULL); + void *scan_context = NULL; - commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; - commonAttr->scanActive = true; + common_attr = (pdrx_common_attr_t) demod->my_common_attr; + common_attr->scan_active = true; - if ((commonAttr->scanParam == NULL) || - (commonAttr->scanMaxChannels == 0)) { + if ((common_attr->scan_param == NULL) || + (common_attr->scan_max_channels == 0)) { /* Scan was not running, just return OK */ - commonAttr->scanActive = false; + common_attr->scan_active = false; return DRX_STS_OK; } /* Call default or device-specific scanning stop function */ - scanContext = GetScanContext(demod, scanContext); + scan_context = get_scan_context(demod, scan_context); - status = (*(GetScanFunction(demod))) - (scanContext, DRX_SCAN_COMMAND_STOP, NULL, NULL); + status = (*(get_scan_function(demod))) + (scan_context, DRX_SCAN_COMMAND_STOP, NULL, NULL); /* All done, invalidate scan-init */ - commonAttr->scanParam = NULL; - commonAttr->scanMaxChannels = 0; - commonAttr->scanActive = false; + common_attr->scan_param = NULL; + common_attr->scan_max_channels = 0; + common_attr->scan_active = false; return status; } @@ -586,126 +586,126 @@ static int CtrlScanStop(pDRXDemodInstance_t demod) /** * \brief Scan for next channel. * \param demod: Pointer to demodulator instance. -* \param scanProgress: Pointer to scan progress. +* \param scan_progress: Pointer to scan progress. * \return int. * \retval DRX_STS_OK: Channel found, DRX_CTRL_GET_CHANNEL can be used * to retrieve channel parameters. * \retval DRX_STS_BUSY: Tried part of the channels, as specified in -* numTries field of scan parameters. At least one +* num_tries field of scan parameters. At least one * more call to DRX_CTRL_SCAN_NEXT is needed to * complete scanning. * \retval DRX_STS_READY: Reached end of scan range. * \retval DRX_STS_ERROR: Something went wrong. -* \retval DRX_STS_INVALID_ARG: Wrong parameters. The scanProgress may be NULL. +* \retval DRX_STS_INVALID_ARG: Wrong parameters. The scan_progress may be NULL. * * Progress indication will run from 0 upto DRX_SCAN_MAX_PROGRESS during scan. * */ -static int CtrlScanNext(pDRXDemodInstance_t demod, u16 *scanProgress) +static int ctrl_scan_next(pdrx_demod_instance_t demod, u16 *scan_progress) { - pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); - bool *scanReady = (bool *) (NULL); - u16 maxProgress = DRX_SCAN_MAX_PROGRESS; - u32 numTries = 0; + pdrx_common_attr_t common_attr = (pdrx_common_attr_t) (NULL); + bool *scan_ready = (bool *) (NULL); + u16 max_progress = DRX_SCAN_MAX_PROGRESS; + u32 num_tries = 0; u32 i = 0; - commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; + common_attr = (pdrx_common_attr_t) demod->my_common_attr; /* Check scan parameters */ - if (scanProgress == NULL) { - commonAttr->scanActive = false; + if (scan_progress == NULL) { + common_attr->scan_active = false; return DRX_STS_INVALID_ARG; } - *scanProgress = 0; - commonAttr->scanActive = true; - if ((commonAttr->scanParam == NULL) || - (commonAttr->scanMaxChannels == 0)) { - /* CtrlScanInit() was not called succesfully before CtrlScanNext() */ - commonAttr->scanActive = false; + *scan_progress = 0; + common_attr->scan_active = true; + if ((common_attr->scan_param == NULL) || + (common_attr->scan_max_channels == 0)) { + /* ctrl_scan_init() was not called succesfully before ctrl_scan_next() */ + common_attr->scan_active = false; return DRX_STS_ERROR; } - *scanProgress = (u16) (((commonAttr->scanChannelsScanned) * - ((u32) (maxProgress))) / - (commonAttr->scanMaxChannels)); + *scan_progress = (u16) (((common_attr->scan_channelsScanned) * + ((u32) (max_progress))) / + (common_attr->scan_max_channels)); /* Scan */ - numTries = commonAttr->scanParam->numTries; - scanReady = &(commonAttr->scanReady); + num_tries = common_attr->scan_param->num_tries; + scan_ready = &(common_attr->scan_ready); - for (i = 0; ((i < numTries) && ((*scanReady) == false)); i++) { - DRXChannel_t scanChannel = { 0 }; + for (i = 0; ((i < num_tries) && ((*scan_ready) == false)); i++) { + drx_channel_t scan_channel = { 0 }; int status = DRX_STS_ERROR; - pDRXFrequencyPlan_t freqPlan = (pDRXFrequencyPlan_t) (NULL); - bool nextChannel = false; - void *scanContext = NULL; + p_drx_frequency_plan_t freq_plan = (p_drx_frequency_plan_t) (NULL); + bool next_channel = false; + void *scan_context = NULL; /* Next channel to scan */ - freqPlan = - &(commonAttr->scanParam-> - frequencyPlan[commonAttr->scanFreqPlanIndex]); - scanChannel.frequency = commonAttr->scanNextFrequency; - scanChannel.bandwidth = freqPlan->bandwidth; - scanChannel.mirror = DRX_MIRROR_AUTO; - scanChannel.constellation = DRX_CONSTELLATION_AUTO; - scanChannel.hierarchy = DRX_HIERARCHY_AUTO; - scanChannel.priority = DRX_PRIORITY_HIGH; - scanChannel.coderate = DRX_CODERATE_AUTO; - scanChannel.guard = DRX_GUARD_AUTO; - scanChannel.fftmode = DRX_FFTMODE_AUTO; - scanChannel.classification = DRX_CLASSIFICATION_AUTO; - scanChannel.symbolrate = 0; - scanChannel.interleavemode = DRX_INTERLEAVEMODE_AUTO; - scanChannel.ldpc = DRX_LDPC_AUTO; - scanChannel.carrier = DRX_CARRIER_AUTO; - scanChannel.framemode = DRX_FRAMEMODE_AUTO; - scanChannel.pilot = DRX_PILOT_AUTO; + freq_plan = + &(common_attr->scan_param-> + frequency_plan[common_attr->scan_freq_plan_index]); + scan_channel.frequency = common_attr->scan_next_frequency; + scan_channel.bandwidth = freq_plan->bandwidth; + scan_channel.mirror = DRX_MIRROR_AUTO; + scan_channel.constellation = DRX_CONSTELLATION_AUTO; + scan_channel.hierarchy = DRX_HIERARCHY_AUTO; + scan_channel.priority = DRX_PRIORITY_HIGH; + scan_channel.coderate = DRX_CODERATE_AUTO; + scan_channel.guard = DRX_GUARD_AUTO; + scan_channel.fftmode = DRX_FFTMODE_AUTO; + scan_channel.classification = DRX_CLASSIFICATION_AUTO; + scan_channel.symbolrate = 0; + scan_channel.interleavemode = DRX_INTERLEAVEMODE_AUTO; + scan_channel.ldpc = DRX_LDPC_AUTO; + scan_channel.carrier = DRX_CARRIER_AUTO; + scan_channel.framemode = DRX_FRAMEMODE_AUTO; + scan_channel.pilot = DRX_PILOT_AUTO; /* Call default or device-specific scanning function */ - scanContext = GetScanContext(demod, scanContext); + scan_context = get_scan_context(demod, scan_context); - status = (*(GetScanFunction(demod))) - (scanContext, DRX_SCAN_COMMAND_NEXT, &scanChannel, - &nextChannel); + status = (*(get_scan_function(demod))) + (scan_context, DRX_SCAN_COMMAND_NEXT, &scan_channel, + &next_channel); /* Proceed to next channel if requested */ - if (nextChannel == true) { - int nextStatus = DRX_STS_ERROR; + if (next_channel == true) { + int next_status = DRX_STS_ERROR; s32 skip = 0; if (status == DRX_STS_OK) { /* a channel was found, so skip some frequency steps */ - skip = commonAttr->scanParam->skip; + skip = common_attr->scan_param->skip; } - nextStatus = ScanPrepareNextScan(demod, skip); + next_status = scan_prepare_next_scan(demod, skip); /* keep track of progress */ - *scanProgress = - (u16) (((commonAttr->scanChannelsScanned) * - ((u32) (maxProgress))) / - (commonAttr->scanMaxChannels)); - - if (nextStatus != DRX_STS_OK) { - commonAttr->scanActive = false; - return (nextStatus); + *scan_progress = + (u16) (((common_attr->scan_channelsScanned) * + ((u32) (max_progress))) / + (common_attr->scan_max_channels)); + + if (next_status != DRX_STS_OK) { + common_attr->scan_active = false; + return (next_status); } } if (status != DRX_STS_BUSY) { /* channel found or error */ - commonAttr->scanActive = false; + common_attr->scan_active = false; return status; } - } /* for ( i = 0; i < ( ... numTries); i++) */ + } /* for ( i = 0; i < ( ... num_tries); i++) */ - if ((*scanReady) == true) { + if ((*scan_ready) == true) { /* End of scan reached: call stop-scan, ignore any error */ - CtrlScanStop(demod); - commonAttr->scanActive = false; + ctrl_scan_stop(demod); + common_attr->scan_active = false; return (DRX_STS_READY); } - commonAttr->scanActive = false; + common_attr->scan_active = false; return DRX_STS_BUSY; } @@ -728,101 +728,101 @@ static int CtrlScanNext(pDRXDemodInstance_t demod, u16 *scanProgress) * */ static int -CtrlProgramTuner(pDRXDemodInstance_t demod, pDRXChannel_t channel) +ctrl_program_tuner(pdrx_demod_instance_t demod, pdrx_channel_t channel) { - pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); + pdrx_common_attr_t common_attr = (pdrx_common_attr_t) (NULL); enum drx_standard standard = DRX_STANDARD_UNKNOWN; - u32 tunerMode = 0; + u32 tuner_mode = 0; int status = DRX_STS_ERROR; - s32 ifFrequency = 0; - bool tunerSlowMode = false; + s32 if_frequency = 0; + bool tuner_slow_mode = false; /* can't tune without a tuner */ - if (demod->myTuner == NULL) { + if (demod->my_tuner == NULL) { return DRX_STS_INVALID_ARG; } - commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; + common_attr = (pdrx_common_attr_t) demod->my_common_attr; /* select analog or digital tuner mode based on current standard */ - if (DRX_Ctrl(demod, DRX_CTRL_GET_STANDARD, &standard) != DRX_STS_OK) { + if (drx_ctrl(demod, DRX_CTRL_GET_STANDARD, &standard) != DRX_STS_OK) { return DRX_STS_ERROR; } if (DRX_ISATVSTD(standard)) { - tunerMode |= TUNER_MODE_ANALOG; + tuner_mode |= TUNER_MODE_ANALOG; } else { /* note: also for unknown standard */ - tunerMode |= TUNER_MODE_DIGITAL; + tuner_mode |= TUNER_MODE_DIGITAL; } /* select tuner bandwidth */ switch (channel->bandwidth) { case DRX_BANDWIDTH_6MHZ: - tunerMode |= TUNER_MODE_6MHZ; + tuner_mode |= TUNER_MODE_6MHZ; break; case DRX_BANDWIDTH_7MHZ: - tunerMode |= TUNER_MODE_7MHZ; + tuner_mode |= TUNER_MODE_7MHZ; break; case DRX_BANDWIDTH_8MHZ: - tunerMode |= TUNER_MODE_8MHZ; + tuner_mode |= TUNER_MODE_8MHZ; break; default: /* note: also for unknown bandwidth */ return DRX_STS_INVALID_ARG; } - DRX_GET_TUNERSLOWMODE(demod, tunerSlowMode); + DRX_GET_TUNERSLOWMODE(demod, tuner_slow_mode); /* select fast (switch) or slow (lock) tuner mode */ - if (tunerSlowMode) { - tunerMode |= TUNER_MODE_LOCK; + if (tuner_slow_mode) { + tuner_mode |= TUNER_MODE_LOCK; } else { - tunerMode |= TUNER_MODE_SWITCH; + tuner_mode |= TUNER_MODE_SWITCH; } - if (commonAttr->tunerPortNr == 1) { - bool bridgeClosed = true; - int statusBridge = DRX_STS_ERROR; + if (common_attr->tuner_port_nr == 1) { + bool bridge_closed = true; + int status_bridge = DRX_STS_ERROR; - statusBridge = - DRX_Ctrl(demod, DRX_CTRL_I2C_BRIDGE, &bridgeClosed); - if (statusBridge != DRX_STS_OK) { - return statusBridge; + status_bridge = + drx_ctrl(demod, DRX_CTRL_I2C_BRIDGE, &bridge_closed); + if (status_bridge != DRX_STS_OK) { + return status_bridge; } } - status = DRXBSP_TUNER_SetFrequency(demod->myTuner, - tunerMode, channel->frequency); + status = drxbsp_tuner_set_frequency(demod->my_tuner, + tuner_mode, channel->frequency); - /* attempt restoring bridge before checking status of SetFrequency */ - if (commonAttr->tunerPortNr == 1) { - bool bridgeClosed = false; - int statusBridge = DRX_STS_ERROR; + /* attempt restoring bridge before checking status of set_frequency */ + if (common_attr->tuner_port_nr == 1) { + bool bridge_closed = false; + int status_bridge = DRX_STS_ERROR; - statusBridge = - DRX_Ctrl(demod, DRX_CTRL_I2C_BRIDGE, &bridgeClosed); - if (statusBridge != DRX_STS_OK) { - return statusBridge; + status_bridge = + drx_ctrl(demod, DRX_CTRL_I2C_BRIDGE, &bridge_closed); + if (status_bridge != DRX_STS_OK) { + return status_bridge; } } - /* now check status of DRXBSP_TUNER_SetFrequency */ + /* now check status of drxbsp_tuner_set_frequency */ if (status != DRX_STS_OK) { return status; } /* get actual RF and IF frequencies from tuner */ - status = DRXBSP_TUNER_GetFrequency(demod->myTuner, - tunerMode, + status = drxbsp_tuner_get_frequency(demod->my_tuner, + tuner_mode, &(channel->frequency), - &(ifFrequency)); + &(if_frequency)); if (status != DRX_STS_OK) { return status; } /* update common attributes with information available from this function; TODO: check if this is required and safe */ - DRX_SET_INTERMEDIATEFREQ(demod, ifFrequency); + DRX_SET_INTERMEDIATEFREQ(demod, if_frequency); return DRX_STS_OK; } @@ -839,8 +839,8 @@ CtrlProgramTuner(pDRXDemodInstance_t demod, pDRXChannel_t channel) * \retval DRX_STS_INVALID_ARG: Wrong parameters. * */ -int CtrlDumpRegisters(pDRXDemodInstance_t demod, - pDRXRegDump_t registers) +int ctrl_dump_registers(pdrx_demod_instance_t demod, + p_drx_reg_dump_t registers) { u16 i = 0; @@ -856,7 +856,7 @@ int CtrlDumpRegisters(pDRXDemodInstance_t demod, u32 data = 0; status = - demod->myAccessFunct->readReg16Func(demod->myI2CDevAddr, + demod->my_access_funct->read_reg16func(demod->my_i2c_dev_addr, registers[i].address, &value, 0); @@ -890,7 +890,7 @@ int CtrlDumpRegisters(pDRXDemodInstance_t demod, * host and the data contained in the microcode image file. * */ -static u16 UCodeRead16(u8 *addr) +static u16 u_code_read16(u8 *addr) { /* Works fo any host processor */ @@ -914,7 +914,7 @@ static u16 UCodeRead16(u8 *addr) * host and the data contained in the microcode image file. * */ -static u32 UCodeRead32(u8 *addr) +static u32 u_code_read32(u8 *addr) { /* Works fo any host processor */ @@ -935,38 +935,38 @@ static u32 UCodeRead32(u8 *addr) /** * \brief Compute CRC of block of microcode data. -* \param blockData: Pointer to microcode data. -* \param nrWords: Size of microcode block (number of 16 bits words). +* \param block_data: Pointer to microcode data. +* \param nr_words: Size of microcode block (number of 16 bits words). * \return u16 The computed CRC residu. */ -static u16 UCodeComputeCRC(u8 *blockData, u16 nrWords) +static u16 u_code_compute_crc(u8 *block_data, u16 nr_words) { u16 i = 0; u16 j = 0; - u32 CRCWord = 0; + u32 crc_word = 0; u32 carry = 0; - while (i < nrWords) { - CRCWord |= (u32) UCodeRead16(blockData); + while (i < nr_words) { + crc_word |= (u32) u_code_read16(block_data); for (j = 0; j < 16; j++) { - CRCWord <<= 1; + crc_word <<= 1; if (carry != 0) { - CRCWord ^= 0x80050000UL; + crc_word ^= 0x80050000UL; } - carry = CRCWord & 0x80000000UL; + carry = crc_word & 0x80000000UL; } i++; - blockData += (sizeof(u16)); + block_data += (sizeof(u16)); } - return ((u16) (CRCWord >> 16)); + return ((u16) (crc_word >> 16)); } /*============================================================================*/ /** * \brief Handle microcode upload or verify. -* \param devAddr: Address of device. -* \param mcInfo: Pointer to information about microcode data. +* \param dev_addr: Address of device. +* \param mc_info: Pointer to information about microcode data. * \param action: Either UCODE_UPLOAD or UCODE_VERIFY * \return int. * \retval DRX_STS_OK: @@ -982,32 +982,32 @@ static u16 UCodeComputeCRC(u8 *blockData, u16 nrWords) * - Provided image is corrupt */ static int -CtrlUCode(pDRXDemodInstance_t demod, - pDRXUCodeInfo_t mcInfo, DRXUCodeAction_t action) +ctrl_u_code(pdrx_demod_instance_t demod, + p_drxu_code_info_t mc_info, drxu_code_action_t action) { int rc; u16 i = 0; - u16 mcNrOfBlks = 0; - u16 mcMagicWord = 0; - u8 *mcData = (u8 *) (NULL); - struct i2c_device_addr *devAddr = (struct i2c_device_addr *) (NULL); + u16 mc_nr_of_blks = 0; + u16 mc_magic_word = 0; + u8 *mc_data = (u8 *) (NULL); + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) (NULL); - devAddr = demod->myI2CDevAddr; + dev_addr = demod->my_i2c_dev_addr; /* Check arguments */ - if ((mcInfo == NULL) || (mcInfo->mcData == NULL)) { + if ((mc_info == NULL) || (mc_info->mc_data == NULL)) { return DRX_STS_INVALID_ARG; } - mcData = mcInfo->mcData; + mc_data = mc_info->mc_data; /* Check data */ - mcMagicWord = UCodeRead16(mcData); - mcData += sizeof(u16); - mcNrOfBlks = UCodeRead16(mcData); - mcData += sizeof(u16); + mc_magic_word = u_code_read16(mc_data); + mc_data += sizeof(u16); + mc_nr_of_blks = u_code_read16(mc_data); + mc_data += sizeof(u16); - if ((mcMagicWord != DRX_UCODE_MAGIC_WORD) || (mcNrOfBlks == 0)) { + if ((mc_magic_word != DRX_UCODE_MAGIC_WORD) || (mc_nr_of_blks == 0)) { /* wrong endianess or wrong data ? */ return DRX_STS_INVALID_ARG; } @@ -1019,95 +1019,95 @@ CtrlUCode(pDRXDemodInstance_t demod, DRX_SET_MCDEV(demod, 0); DRX_SET_MCVERSION(demod, 0); DRX_SET_MCPATCH(demod, 0); - for (i = 0; i < mcNrOfBlks; i++) { - DRXUCodeBlockHdr_t blockHdr; + for (i = 0; i < mc_nr_of_blks; i++) { + drxu_code_block_hdr_t block_hdr; /* Process block header */ - blockHdr.addr = UCodeRead32(mcData); - mcData += sizeof(u32); - blockHdr.size = UCodeRead16(mcData); - mcData += sizeof(u16); - blockHdr.flags = UCodeRead16(mcData); - mcData += sizeof(u16); - blockHdr.CRC = UCodeRead16(mcData); - mcData += sizeof(u16); - - if (blockHdr.flags & 0x8) { + block_hdr.addr = u_code_read32(mc_data); + mc_data += sizeof(u32); + block_hdr.size = u_code_read16(mc_data); + mc_data += sizeof(u16); + block_hdr.flags = u_code_read16(mc_data); + mc_data += sizeof(u16); + block_hdr.CRC = u_code_read16(mc_data); + mc_data += sizeof(u16); + + if (block_hdr.flags & 0x8) { /* Aux block. Check type */ - u8 *auxblk = mcInfo->mcData + blockHdr.addr; - u16 auxtype = UCodeRead16(auxblk); + u8 *auxblk = mc_info->mc_data + block_hdr.addr; + u16 auxtype = u_code_read16(auxblk); if (DRX_ISMCVERTYPE(auxtype)) { DRX_SET_MCVERTYPE(demod, - UCodeRead16(auxblk)); + u_code_read16(auxblk)); auxblk += sizeof(u16); DRX_SET_MCDEV(demod, - UCodeRead32(auxblk)); + u_code_read32(auxblk)); auxblk += sizeof(u32); DRX_SET_MCVERSION(demod, - UCodeRead32(auxblk)); + u_code_read32(auxblk)); auxblk += sizeof(u32); DRX_SET_MCPATCH(demod, - UCodeRead32(auxblk)); + u_code_read32(auxblk)); } } /* Next block */ - mcData += blockHdr.size * sizeof(u16); + mc_data += block_hdr.size * sizeof(u16); } /* After scanning, validate the microcode. It is also valid if no validation control exists. */ - rc = DRX_Ctrl(demod, DRX_CTRL_VALIDATE_UCODE, NULL); + rc = drx_ctrl(demod, DRX_CTRL_VALIDATE_UCODE, NULL); if (rc != DRX_STS_OK && rc != DRX_STS_FUNC_NOT_AVAILABLE) { return rc; } /* Restore data pointer */ - mcData = mcInfo->mcData + 2 * sizeof(u16); + mc_data = mc_info->mc_data + 2 * sizeof(u16); } /* Process microcode blocks */ - for (i = 0; i < mcNrOfBlks; i++) { - DRXUCodeBlockHdr_t blockHdr; - u16 mcBlockNrBytes = 0; + for (i = 0; i < mc_nr_of_blks; i++) { + drxu_code_block_hdr_t block_hdr; + u16 mc_block_nr_bytes = 0; /* Process block header */ - blockHdr.addr = UCodeRead32(mcData); - mcData += sizeof(u32); - blockHdr.size = UCodeRead16(mcData); - mcData += sizeof(u16); - blockHdr.flags = UCodeRead16(mcData); - mcData += sizeof(u16); - blockHdr.CRC = UCodeRead16(mcData); - mcData += sizeof(u16); + block_hdr.addr = u_code_read32(mc_data); + mc_data += sizeof(u32); + block_hdr.size = u_code_read16(mc_data); + mc_data += sizeof(u16); + block_hdr.flags = u_code_read16(mc_data); + mc_data += sizeof(u16); + block_hdr.CRC = u_code_read16(mc_data); + mc_data += sizeof(u16); /* Check block header on: - data larger than 64Kb - if CRC enabled check CRC */ - if ((blockHdr.size > 0x7FFF) || - (((blockHdr.flags & DRX_UCODE_CRC_FLAG) != 0) && - (blockHdr.CRC != UCodeComputeCRC(mcData, blockHdr.size))) + if ((block_hdr.size > 0x7FFF) || + (((block_hdr.flags & DRX_UCODE_CRC_FLAG) != 0) && + (block_hdr.CRC != u_code_compute_crc(mc_data, block_hdr.size))) ) { /* Wrong data ! */ return DRX_STS_INVALID_ARG; } - mcBlockNrBytes = blockHdr.size * ((u16) sizeof(u16)); + mc_block_nr_bytes = block_hdr.size * ((u16) sizeof(u16)); - if (blockHdr.size != 0) { + if (block_hdr.size != 0) { /* Perform the desired action */ switch (action) { /*================================================================*/ case UCODE_UPLOAD: { /* Upload microcode */ - if (demod->myAccessFunct-> - writeBlockFunc(devAddr, - (DRXaddr_t) blockHdr. - addr, mcBlockNrBytes, - mcData, + if (demod->my_access_funct-> + write_block_func(dev_addr, + (dr_xaddr_t) block_hdr. + addr, mc_block_nr_bytes, + mc_data, 0x0000) != DRX_STS_OK) { return (DRX_STS_ERROR); @@ -1119,58 +1119,58 @@ CtrlUCode(pDRXDemodInstance_t demod, case UCODE_VERIFY: { int result = 0; - u8 mcDataBuffer + u8 mc_dataBuffer [DRX_UCODE_MAX_BUF_SIZE]; - u32 bytesToCompare = 0; - u32 bytesLeftToCompare = 0; - DRXaddr_t currAddr = (DRXaddr_t) 0; - u8 *currPtr = NULL; + u32 bytes_to_compare = 0; + u32 bytes_left_to_compare = 0; + dr_xaddr_t curr_addr = (dr_xaddr_t) 0; + u8 *curr_ptr = NULL; - bytesLeftToCompare = mcBlockNrBytes; - currAddr = blockHdr.addr; - currPtr = mcData; + bytes_left_to_compare = mc_block_nr_bytes; + curr_addr = block_hdr.addr; + curr_ptr = mc_data; - while (bytesLeftToCompare != 0) { - if (bytesLeftToCompare > + while (bytes_left_to_compare != 0) { + if (bytes_left_to_compare > ((u32) DRX_UCODE_MAX_BUF_SIZE)) { - bytesToCompare = + bytes_to_compare = ((u32) DRX_UCODE_MAX_BUF_SIZE); } else { - bytesToCompare = - bytesLeftToCompare; + bytes_to_compare = + bytes_left_to_compare; } - if (demod->myAccessFunct-> - readBlockFunc(devAddr, - currAddr, + if (demod->my_access_funct-> + read_block_func(dev_addr, + curr_addr, (u16) - bytesToCompare, + bytes_to_compare, (u8 *) - mcDataBuffer, + mc_dataBuffer, 0x0000) != DRX_STS_OK) { return (DRX_STS_ERROR); } result = - DRXBSP_HST_Memcmp(currPtr, - mcDataBuffer, - bytesToCompare); + drxbsp_hst_memcmp(curr_ptr, + mc_dataBuffer, + bytes_to_compare); if (result != 0) { return DRX_STS_ERROR; } - currAddr += - ((DRXaddr_t) - (bytesToCompare / 2)); - currPtr = - &(currPtr[bytesToCompare]); - bytesLeftToCompare -= - ((u32) bytesToCompare); - } /* while( bytesToCompare > DRX_UCODE_MAX_BUF_SIZE ) */ + curr_addr += + ((dr_xaddr_t) + (bytes_to_compare / 2)); + curr_ptr = + &(curr_ptr[bytes_to_compare]); + bytes_left_to_compare -= + ((u32) bytes_to_compare); + } /* while( bytes_to_compare > DRX_UCODE_MAX_BUF_SIZE ) */ }; break; @@ -1182,11 +1182,11 @@ CtrlUCode(pDRXDemodInstance_t demod, } /* switch ( action ) */ } - /* if (blockHdr.size != 0 ) */ + /* if (block_hdr.size != 0 ) */ /* Next block */ - mcData += mcBlockNrBytes; + mc_data += mc_block_nr_bytes; - } /* for( i = 0 ; imyDemodFunct->ctrlFunc)) (demod, + return_status = (*(demod->my_demod_funct->ctrl_func)) (demod, DRX_CTRL_VERSION, (void *) - &demodVersionList); + &demod_version_list); /* Always fill in the information of the driver SW . */ - drxDriverCoreVersion.moduleType = DRX_MODULE_DRIVERCORE; - drxDriverCoreVersion.moduleName = drxDriverCoreModuleName; - drxDriverCoreVersion.vMajor = VERSION_MAJOR; - drxDriverCoreVersion.vMinor = VERSION_MINOR; - drxDriverCoreVersion.vPatch = VERSION_PATCH; - drxDriverCoreVersion.vString = drxDriverCoreVersionText; + drx_driver_core_version.module_type = DRX_MODULE_DRIVERCORE; + drx_driver_core_version.module_name = drx_driver_core_module_name; + drx_driver_core_version.v_major = VERSION_MAJOR; + drx_driver_core_version.v_minor = VERSION_MINOR; + drx_driver_core_version.v_patch = VERSION_PATCH; + drx_driver_core_version.v_string = drx_driver_core_version_text; - drxDriverCoreVersionList.version = &drxDriverCoreVersion; - drxDriverCoreVersionList.next = (pDRXVersionList_t) (NULL); + drx_driver_core_versionList.version = &drx_driver_core_version; + drx_driver_core_versionList.next = (p_drx_version_list_t) (NULL); - if ((returnStatus == DRX_STS_OK) && (demodVersionList != NULL)) { + if ((return_status == DRX_STS_OK) && (demod_version_list != NULL)) { /* Append versioninfo from driver to versioninfo from demod */ /* Return version info in "bottom-up" order. This way, multiple devices can be handled without using malloc. */ - pDRXVersionList_t currentListElement = demodVersionList; - while (currentListElement->next != NULL) { - currentListElement = currentListElement->next; + p_drx_version_list_t current_list_element = demod_version_list; + while (current_list_element->next != NULL) { + current_list_element = current_list_element->next; } - currentListElement->next = &drxDriverCoreVersionList; + current_list_element->next = &drx_driver_core_versionList; - *versionList = demodVersionList; + *version_list = demod_version_list; } else { /* Just return versioninfo from driver */ - *versionList = &drxDriverCoreVersionList; + *version_list = &drx_driver_core_versionList; } return DRX_STS_OK; @@ -1271,7 +1271,7 @@ CtrlVersion(pDRXDemodInstance_t demod, pDRXVersionList_t *versionList) * */ -int DRX_Init(pDRXDemodInstance_t demods[]) +int drx_init(pdrx_demod_instance_t demods[]) { return DRX_STS_OK; } @@ -1287,7 +1287,7 @@ int DRX_Init(pDRXDemodInstance_t demods[]) * */ -int DRX_Term(void) +int drx_term(void) { return DRX_STS_OK; } @@ -1305,23 +1305,23 @@ int DRX_Term(void) * */ -int DRX_Open(pDRXDemodInstance_t demod) +int drx_open(pdrx_demod_instance_t demod) { int status = DRX_STS_OK; if ((demod == NULL) || - (demod->myDemodFunct == NULL) || - (demod->myCommonAttr == NULL) || - (demod->myExtAttr == NULL) || - (demod->myI2CDevAddr == NULL) || - (demod->myCommonAttr->isOpened == true)) { + (demod->my_demod_funct == NULL) || + (demod->my_common_attr == NULL) || + (demod->my_ext_attr == NULL) || + (demod->my_i2c_dev_addr == NULL) || + (demod->my_common_attr->is_opened == true)) { return (DRX_STS_INVALID_ARG); } - status = (*(demod->myDemodFunct->openFunc)) (demod); + status = (*(demod->my_demod_funct->open_func)) (demod); if (status == DRX_STS_OK) { - demod->myCommonAttr->isOpened = true; + demod->my_common_attr->is_opened = true; } return status; @@ -1342,20 +1342,20 @@ int DRX_Open(pDRXDemodInstance_t demod) * Put device into sleep mode. */ -int DRX_Close(pDRXDemodInstance_t demod) +int drx_close(pdrx_demod_instance_t demod) { int status = DRX_STS_OK; if ((demod == NULL) || - (demod->myDemodFunct == NULL) || - (demod->myCommonAttr == NULL) || - (demod->myExtAttr == NULL) || - (demod->myI2CDevAddr == NULL) || - (demod->myCommonAttr->isOpened == false)) { + (demod->my_demod_funct == NULL) || + (demod->my_common_attr == NULL) || + (demod->my_ext_attr == NULL) || + (demod->my_i2c_dev_addr == NULL) || + (demod->my_common_attr->is_opened == false)) { return DRX_STS_INVALID_ARG; } - status = (*(demod->myDemodFunct->closeFunc)) (demod); + status = (*(demod->my_demod_funct->close_func)) (demod); DRX_SET_ISOPENED(demod, false); @@ -1368,40 +1368,40 @@ int DRX_Close(pDRXDemodInstance_t demod) * \brief Control the device. * \param demod: A pointer to a demodulator instance. * \param ctrl: Reference to desired control function. -* \param ctrlData: Pointer to data structure for control function. +* \param ctrl_data: Pointer to data structure for control function. * \return int Return status. * \retval DRX_STS_OK: Control function completed successfully. * \retval DRX_STS_ERROR: Driver not initialized or error during * control demod. -* \retval DRX_STS_INVALID_ARG: Demod instance or ctrlData has invalid +* \retval DRX_STS_INVALID_ARG: Demod instance or ctrl_data has invalid * content. * \retval DRX_STS_FUNC_NOT_AVAILABLE: Specified control function is not * available. * -* Data needed or returned by the control function is stored in ctrlData. +* Data needed or returned by the control function is stored in ctrl_data. * */ int -DRX_Ctrl(pDRXDemodInstance_t demod, u32 ctrl, void *ctrlData) +drx_ctrl(pdrx_demod_instance_t demod, u32 ctrl, void *ctrl_data) { int status = DRX_STS_ERROR; if ((demod == NULL) || - (demod->myDemodFunct == NULL) || - (demod->myCommonAttr == NULL) || - (demod->myExtAttr == NULL) || (demod->myI2CDevAddr == NULL) + (demod->my_demod_funct == NULL) || + (demod->my_common_attr == NULL) || + (demod->my_ext_attr == NULL) || (demod->my_i2c_dev_addr == NULL) ) { return (DRX_STS_INVALID_ARG); } - if (((demod->myCommonAttr->isOpened == false) && + if (((demod->my_common_attr->is_opened == false) && (ctrl != DRX_CTRL_PROBE_DEVICE) && (ctrl != DRX_CTRL_VERSION)) ) { return (DRX_STS_INVALID_ARG); } - if ((DRX_ISPOWERDOWNMODE(demod->myCommonAttr->currentPowerMode) && + if ((DRX_ISPOWERDOWNMODE(demod->my_common_attr->current_power_mode) && (ctrl != DRX_CTRL_POWER_MODE) && (ctrl != DRX_CTRL_PROBE_DEVICE) && (ctrl != DRX_CTRL_NOP) && (ctrl != DRX_CTRL_VERSION) @@ -1420,7 +1420,7 @@ DRX_Ctrl(pDRXDemodInstance_t demod, u32 ctrl, void *ctrlData) /*======================================================================*/ case DRX_CTRL_VERSION: - return CtrlVersion(demod, (pDRXVersionList_t *) ctrlData); + return ctrl_version(demod, (p_drx_version_list_t *) ctrl_data); break; /*======================================================================*/ @@ -1431,22 +1431,22 @@ DRX_Ctrl(pDRXDemodInstance_t demod, u32 ctrl, void *ctrlData) /* Virtual functions */ /* First try calling function from derived class */ - status = (*(demod->myDemodFunct->ctrlFunc)) (demod, ctrl, ctrlData); + status = (*(demod->my_demod_funct->ctrl_func)) (demod, ctrl, ctrl_data); if (status == DRX_STS_FUNC_NOT_AVAILABLE) { /* Now try calling a the base class function */ switch (ctrl) { /*===================================================================*/ case DRX_CTRL_LOAD_UCODE: - return CtrlUCode(demod, - (pDRXUCodeInfo_t) ctrlData, + return ctrl_u_code(demod, + (p_drxu_code_info_t) ctrl_data, UCODE_UPLOAD); break; /*===================================================================*/ case DRX_CTRL_VERIFY_UCODE: { - return CtrlUCode(demod, - (pDRXUCodeInfo_t) ctrlData, + return ctrl_u_code(demod, + (p_drxu_code_info_t) ctrl_data, UCODE_VERIFY); } break; @@ -1455,22 +1455,22 @@ DRX_Ctrl(pDRXDemodInstance_t demod, u32 ctrl, void *ctrlData) /*===================================================================*/ case DRX_CTRL_SCAN_INIT: { - return CtrlScanInit(demod, - (pDRXScanParam_t) ctrlData); + return ctrl_scan_init(demod, + (p_drx_scan_param_t) ctrl_data); } break; /*===================================================================*/ case DRX_CTRL_SCAN_NEXT: { - return CtrlScanNext(demod, (u16 *) ctrlData); + return ctrl_scan_next(demod, (u16 *) ctrl_data); } break; /*===================================================================*/ case DRX_CTRL_SCAN_STOP: { - return CtrlScanStop(demod); + return ctrl_scan_stop(demod); } break; #endif /* #ifndef DRX_EXCLUDE_SCAN */ @@ -1478,18 +1478,18 @@ DRX_Ctrl(pDRXDemodInstance_t demod, u32 ctrl, void *ctrlData) /*===================================================================*/ case DRX_CTRL_PROGRAM_TUNER: { - return CtrlProgramTuner(demod, - (pDRXChannel_t) - ctrlData); + return ctrl_program_tuner(demod, + (pdrx_channel_t) + ctrl_data); } break; /*===================================================================*/ case DRX_CTRL_DUMP_REGISTERS: { - return CtrlDumpRegisters(demod, - (pDRXRegDump_t) - ctrlData); + return ctrl_dump_registers(demod, + (p_drx_reg_dump_t) + ctrl_data); } break; diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h index 0b0787f..f4a0411 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h @@ -42,7 +42,7 @@ INCLUDES -------------------------------------------------------------------------*/ -enum DRXStatus { +enum drx_status { DRX_STS_READY = 3, /**< device/service is ready */ DRX_STS_BUSY = 2, /**< device/service is busy */ DRX_STS_OK = 1, /**< everything is OK */ @@ -54,13 +54,13 @@ enum DRXStatus { }; /* - * This structure contains the I2C address, the device ID and a userData pointer. - * The userData pointer can be used for application specific purposes. + * This structure contains the I2C address, the device ID and a user_data pointer. + * The user_data pointer can be used for application specific purposes. */ struct i2c_device_addr { - u16 i2cAddr; /* The I2C address of the device. */ - u16 i2cDevId; /* The device identifier. */ - void *userData; /* User data pointer */ + u16 i2c_addr; /* The I2C address of the device. */ + u16 i2c_dev_id; /* The device identifier. */ + void *user_data; /* User data pointer */ }; /** @@ -79,44 +79,44 @@ Exported FUNCTIONS ------------------------------------------------------------------------------*/ /** -* \fn DRXBSP_I2C_Init() +* \fn drxbsp_i2c_init() * \brief Initialize I2C communication module. * \return int Return status. * \retval DRX_STS_OK Initialization successful. * \retval DRX_STS_ERROR Initialization failed. */ -int DRXBSP_I2C_Init(void); +int drxbsp_i2c_init(void); /** -* \fn DRXBSP_I2C_Term() +* \fn drxbsp_i2c_term() * \brief Terminate I2C communication module. * \return int Return status. * \retval DRX_STS_OK Termination successful. * \retval DRX_STS_ERROR Termination failed. */ -int DRXBSP_I2C_Term(void); +int drxbsp_i2c_term(void); /** -* \fn int DRXBSP_I2C_WriteRead( struct i2c_device_addr *wDevAddr, -* u16 wCount, +* \fn int drxbsp_i2c_write_read( struct i2c_device_addr *w_dev_addr, +* u16 w_count, * u8 * wData, -* struct i2c_device_addr *rDevAddr, -* u16 rCount, -* u8 * rData) +* struct i2c_device_addr *r_dev_addr, +* u16 r_count, +* u8 * r_data) * \brief Read and/or write count bytes from I2C bus, store them in data[]. -* \param wDevAddr The device i2c address and the device ID to write to -* \param wCount The number of bytes to write +* \param w_dev_addr The device i2c address and the device ID to write to +* \param w_count The number of bytes to write * \param wData The array to write the data to -* \param rDevAddr The device i2c address and the device ID to read from -* \param rCount The number of bytes to read -* \param rData The array to read the data from +* \param r_dev_addr The device i2c address and the device ID to read from +* \param r_count The number of bytes to read +* \param r_data The array to read the data from * \return int Return status. * \retval DRX_STS_OK Succes. * \retval DRX_STS_ERROR Failure. * \retval DRX_STS_INVALID_ARG Parameter 'wcount' is not zero but parameter * 'wdata' contains NULL. * Idem for 'rcount' and 'rdata'. -* Both wDevAddr and rDevAddr are NULL. +* Both w_dev_addr and r_dev_addr are NULL. * * This function must implement an atomic write and/or read action on the I2C bus * No other process may use the I2C bus when this function is executing. @@ -126,26 +126,26 @@ int DRXBSP_I2C_Term(void); * The device ID can be useful if several devices share an I2C address. * It can be used to control a "switch" on the I2C bus to the correct device. */ -int DRXBSP_I2C_WriteRead(struct i2c_device_addr *wDevAddr, - u16 wCount, +int drxbsp_i2c_write_read(struct i2c_device_addr *w_dev_addr, + u16 w_count, u8 *wData, - struct i2c_device_addr *rDevAddr, - u16 rCount, u8 *rData); + struct i2c_device_addr *r_dev_addr, + u16 r_count, u8 *r_data); /** -* \fn DRXBSP_I2C_ErrorText() +* \fn drxbsp_i2c_error_text() * \brief Returns a human readable error. -* Counter part of numerical DRX_I2C_Error_g. +* Counter part of numerical drx_i2c_error_g. * * \return char* Pointer to human readable error text. */ -char *DRXBSP_I2C_ErrorText(void); +char *drxbsp_i2c_error_text(void); /** -* \var DRX_I2C_Error_g; +* \var drx_i2c_error_g; * \brief I2C specific error codes, platform dependent. */ -extern int DRX_I2C_Error_g; +extern int drx_i2c_error_g; #define TUNER_MODE_SUB0 0x0001 /* for sub-mode (e.g. RF-AGC setting) */ #define TUNER_MODE_SUB1 0x0002 /* for sub-mode (e.g. RF-AGC setting) */ @@ -178,105 +178,105 @@ enum tuner_lock_status { struct tuner_common { char *name; /* Tuner brand & type name */ - s32 minFreqRF; /* Lowest RF input frequency, in kHz */ - s32 maxFreqRF; /* Highest RF input frequency, in kHz */ + s32 min_freq_rf; /* Lowest RF input frequency, in kHz */ + s32 max_freq_rf; /* Highest RF input frequency, in kHz */ - u8 subMode; /* Index to sub-mode in use */ - char ***subModeDescriptions; /* Pointer to description of sub-modes */ - u8 subModes; /* Number of available sub-modes */ + u8 sub_mode; /* Index to sub-mode in use */ + char ***sub_modeDescriptions; /* Pointer to description of sub-modes */ + u8 sub_modes; /* Number of available sub-modes */ /* The following fields will be either 0, NULL or false and do not need initialisation */ - void *selfCheck; /* gives proof of initialization */ - bool programmed; /* only valid if selfCheck is OK */ - s32 RFfrequency; /* only valid if programmed */ - s32 IFfrequency; /* only valid if programmed */ + void *self_check; /* gives proof of initialization */ + bool programmed; /* only valid if self_check is OK */ + s32 r_ffrequency; /* only valid if programmed */ + s32 i_ffrequency; /* only valid if programmed */ - void *myUserData; /* pointer to associated demod instance */ - u16 myCapabilities; /* value for storing application flags */ + void *myUser_data; /* pointer to associated demod instance */ + u16 my_capabilities; /* value for storing application flags */ }; struct tuner_instance; -typedef int(*TUNEROpenFunc_t) (struct tuner_instance *tuner); -typedef int(*TUNERCloseFunc_t) (struct tuner_instance *tuner); +typedef int(*tuner_open_func_t) (struct tuner_instance *tuner); +typedef int(*tuner_close_func_t) (struct tuner_instance *tuner); -typedef int(*TUNERSetFrequencyFunc_t) (struct tuner_instance *tuner, +typedef int(*tuner_set_frequency_func_t) (struct tuner_instance *tuner, u32 mode, s32 frequency); -typedef int(*TUNERGetFrequencyFunc_t) (struct tuner_instance *tuner, +typedef int(*tuner_get_frequency_func_t) (struct tuner_instance *tuner, u32 mode, s32 * - RFfrequency, + r_ffrequency, s32 * - IFfrequency); + i_ffrequency); -typedef int(*TUNERLockStatusFunc_t) (struct tuner_instance *tuner, +typedef int(*tuner_lock_status_func_t) (struct tuner_instance *tuner, enum tuner_lock_status * - lockStat); + lock_stat); -typedef int(*TUNERi2cWriteReadFunc_t) (struct tuner_instance *tuner, +typedef int(*tune_ri2c_write_read_func_t) (struct tuner_instance *tuner, struct i2c_device_addr * - wDevAddr, u16 wCount, + w_dev_addr, u16 w_count, u8 *wData, struct i2c_device_addr * - rDevAddr, u16 rCount, - u8 *rData); + r_dev_addr, u16 r_count, + u8 *r_data); struct tuner_ops { - TUNEROpenFunc_t openFunc; - TUNERCloseFunc_t closeFunc; - TUNERSetFrequencyFunc_t setFrequencyFunc; - TUNERGetFrequencyFunc_t getFrequencyFunc; - TUNERLockStatusFunc_t lockStatusFunc; - TUNERi2cWriteReadFunc_t i2cWriteReadFunc; + tuner_open_func_t open_func; + tuner_close_func_t close_func; + tuner_set_frequency_func_t set_frequency_func; + tuner_get_frequency_func_t get_frequency_func; + tuner_lock_status_func_t lock_statusFunc; + tune_ri2c_write_read_func_t i2c_write_read_func; }; struct tuner_instance { - struct i2c_device_addr myI2CDevAddr; - struct tuner_common *myCommonAttr; - void *myExtAttr; - struct tuner_ops *myFunct; + struct i2c_device_addr my_i2c_dev_addr; + struct tuner_common *my_common_attr; + void *my_ext_attr; + struct tuner_ops *my_funct; }; -int DRXBSP_TUNER_Open(struct tuner_instance *tuner); +int drxbsp_tuner_open(struct tuner_instance *tuner); -int DRXBSP_TUNER_Close(struct tuner_instance *tuner); +int drxbsp_tuner_close(struct tuner_instance *tuner); -int DRXBSP_TUNER_SetFrequency(struct tuner_instance *tuner, +int drxbsp_tuner_set_frequency(struct tuner_instance *tuner, u32 mode, s32 frequency); -int DRXBSP_TUNER_GetFrequency(struct tuner_instance *tuner, +int drxbsp_tuner_get_frequency(struct tuner_instance *tuner, u32 mode, - s32 *RFfrequency, - s32 *IFfrequency); + s32 *r_ffrequency, + s32 *i_ffrequency); -int DRXBSP_TUNER_LockStatus(struct tuner_instance *tuner, - enum tuner_lock_status *lockStat); +int drxbsp_tuner_lock_status(struct tuner_instance *tuner, + enum tuner_lock_status *lock_stat); -int DRXBSP_TUNER_DefaultI2CWriteRead(struct tuner_instance *tuner, - struct i2c_device_addr *wDevAddr, - u16 wCount, +int drxbsp_tuner_default_i2c_write_read(struct tuner_instance *tuner, + struct i2c_device_addr *w_dev_addr, + u16 w_count, u8 *wData, - struct i2c_device_addr *rDevAddr, - u16 rCount, u8 *rData); + struct i2c_device_addr *r_dev_addr, + u16 r_count, u8 *r_data); -int DRXBSP_HST_Init(void); +int drxbsp_hst_init(void); -int DRXBSP_HST_Term(void); +int drxbsp_hst_term(void); -void *DRXBSP_HST_Memcpy(void *to, void *from, u32 n); +void *drxbsp_hst_memcpy(void *to, void *from, u32 n); -int DRXBSP_HST_Memcmp(void *s1, void *s2, u32 n); +int drxbsp_hst_memcmp(void *s1, void *s2, u32 n); -u32 DRXBSP_HST_Clock(void); +u32 drxbsp_hst_clock(void); -int DRXBSP_HST_Sleep(u32 n); +int drxbsp_hst_sleep(u32 n); @@ -856,7 +856,7 @@ enum drx_pilot_mode { #define DRX_CTRL_MAX (DRX_CTRL_BASE + 44) /* never to be used */ /** -* \enum DRXUCodeAction_t +* \enum drxu_code_action_t * \brief Used to indicate if firmware has to be uploaded or verified. */ @@ -865,10 +865,10 @@ enum drx_pilot_mode { /**< Upload the microcode image to device */ UCODE_VERIFY /**< Compare microcode image with code on device */ - } DRXUCodeAction_t, *pDRXUCodeAction_t; + } drxu_code_action_t, *pdrxu_code_action_t; /** -* \enum DRXLockStatus_t +* \enum drx_lock_status_t * \brief Used to reflect current lock status of demodulator. * * The generic lock states have device dependent semantics. @@ -897,7 +897,7 @@ enum drx_pilot_mode { DRX_LOCK_STATE_9, /**< Generic lock state */ DRX_LOCKED /**< Device is in lock */ - } DRXLockStatus_t, *pDRXLockStatus_t; + } drx_lock_status_t, *pdrx_lock_status_t; /** * \enum DRXUIO_t @@ -937,10 +937,10 @@ enum drx_pilot_mode { DRX_UIO31, DRX_UIO32, DRX_UIO_MAX = DRX_UIO32 - } DRXUIO_t, *pDRXUIO_t; + } DRXUIO_t, *p_drxuio_t; /** -* \enum DRXUIOMode_t +* \enum drxuio_mode_t * \brief Used to configure the modus oprandi of a UIO. * * DRX_UIO_MODE_FIRMWARE is an old uio mode. @@ -967,10 +967,10 @@ enum drx_pilot_mode { /**< controlled by firmware, function 4 */ DRX_UIO_MODE_FIRMWARE5 = 0x80 /**< controlled by firmware, function 5 */ - } DRXUIOMode_t, *pDRXUIOMode_t; + } drxuio_mode_t, *pdrxuio_mode_t; /** -* \enum DRXOOBDownstreamStandard_t +* \enum drxoob_downstream_standard_t * \brief Used to select OOB standard. * * Based on ANSI 55-1 and 55-2 @@ -982,7 +982,7 @@ enum drx_pilot_mode { /**< ANSI 55-2 A */ DRX_OOB_MODE_B_GRADE_B /**< ANSI 55-2 B */ - } DRXOOBDownstreamStandard_t, *pDRXOOBDownstreamStandard_t; + } drxoob_downstream_standard_t, *pdrxoob_downstream_standard_t; /*------------------------------------------------------------------------- STRUCTS @@ -995,13 +995,13 @@ STRUCTS /*============================================================================*/ /** -* \enum DRXCfgType_t +* \enum drx_cfg_type_t * \brief Generic configuration function identifiers. */ - typedef u32 DRXCfgType_t, *pDRXCfgType_t; + typedef u32 drx_cfg_type_t, *pdrx_cfg_type_t; #ifndef DRX_CFG_BASE -#define DRX_CFG_BASE ((DRXCfgType_t)0) +#define DRX_CFG_BASE ((drx_cfg_type_t)0) #endif #define DRX_CFG_MPEG_OUTPUT (DRX_CFG_BASE + 0) /* MPEG TS output */ @@ -1032,20 +1032,20 @@ STRUCTS /*============================================================================*/ /** -* \struct DRXUCodeInfo_t +* \struct drxu_code_info_t * \brief Parameters for microcode upload and verfiy. * * Used by DRX_CTRL_LOAD_UCODE and DRX_CTRL_VERIFY_UCODE */ typedef struct { - u8 *mcData; + u8 *mc_data; /**< Pointer to microcode image. */ - u16 mcSize; + u16 mc_size; /**< Microcode image size. */ - } DRXUCodeInfo_t, *pDRXUCodeInfo_t; + } drxu_code_info_t, *p_drxu_code_info_t; /** -* \struct DRXMcVersionRec_t +* \struct drx_mc_version_rec_t * \brief Microcode version record * Version numbers are stored in BCD format, as usual: * o major number = bits 31-20 (first three nibbles of MSW) @@ -1056,43 +1056,43 @@ STRUCTS * JTAG ID, using everything except the bond ID and the metal fix. * * Special values: -* - mcDevType == 0 => any device allowed -* - mcBaseVersion == 0.0.0 => full microcode (mcVersion is the version) -* - mcBaseVersion != 0.0.0 => patch microcode, the base microcode version -* (mcVersion is the version) +* - mc_dev_type == 0 => any device allowed +* - mc_base_version == 0.0.0 => full microcode (mc_version is the version) +* - mc_base_version != 0.0.0 => patch microcode, the base microcode version +* (mc_version is the version) */ #define AUX_VER_RECORD 0x8000 typedef struct { - u16 auxType; /* type of aux data - 0x8000 for version record */ - u32 mcDevType; /* device type, based on JTAG ID */ - u32 mcVersion; /* version of microcode */ - u32 mcBaseVersion; /* in case of patch: the original microcode version */ - } DRXMcVersionRec_t, *pDRXMcVersionRec_t; + u16 aux_type; /* type of aux data - 0x8000 for version record */ + u32 mc_dev_type; /* device type, based on JTAG ID */ + u32 mc_version; /* version of microcode */ + u32 mc_base_version; /* in case of patch: the original microcode version */ + } drx_mc_version_rec_t, *pdrx_mc_version_rec_t; /*========================================*/ /** -* \struct DRXFilterInfo_t +* \struct drx_filter_info_t * \brief Parameters for loading filter coefficients * * Used by DRX_CTRL_LOAD_FILTER */ typedef struct { - u8 *dataRe; + u8 *data_re; /**< pointer to coefficients for RE */ - u8 *dataIm; + u8 *data_im; /**< pointer to coefficients for IM */ - u16 sizeRe; + u16 size_re; /**< size of coefficients for RE */ - u16 sizeIm; + u16 size_im; /**< size of coefficients for IM */ - } DRXFilterInfo_t, *pDRXFilterInfo_t; + } drx_filter_info_t, *pdrx_filter_info_t; /*========================================*/ /** -* \struct DRXChannel_t +* \struct drx_channel_t * \brief The set of parameters describing a single channel. * * Used by DRX_CTRL_SET_CHANNEL and DRX_CTRL_GET_CHANNEL. @@ -1124,46 +1124,46 @@ STRUCTS enum drx_frame_mode framemode; /**< frame mode */ enum drx_pilot_mode pilot; /**< pilot mode */ - } DRXChannel_t, *pDRXChannel_t; + } drx_channel_t, *pdrx_channel_t; /*========================================*/ /** -* \struct DRXSigQuality_t +* \struct drx_sig_quality_t * Signal quality metrics. * * Used by DRX_CTRL_SIG_QUALITY. */ typedef struct { u16 MER; /**< in steps of 0.1 dB */ - u32 preViterbiBER; - /**< in steps of 1/scaleFactorBER */ - u32 postViterbiBER; - /**< in steps of 1/scaleFactorBER */ - u32 scaleFactorBER; + u32 pre_viterbi_ber; + /**< in steps of 1/scale_factor_ber */ + u32 post_viterbi_ber; + /**< in steps of 1/scale_factor_ber */ + u32 scale_factor_ber; /**< scale factor for BER */ - u16 packetError; + u16 packet_error; /**< number of packet errors */ - u32 postReedSolomonBER; - /**< in steps of 1/scaleFactorBER */ - u32 preLdpcBER; - /**< in steps of 1/scaleFactorBER */ - u32 averIter;/**< in steps of 0.01 */ + u32 post_reed_solomon_ber; + /**< in steps of 1/scale_factor_ber */ + u32 pre_ldpc_ber; + /**< in steps of 1/scale_factor_ber */ + u32 aver_iter;/**< in steps of 0.01 */ u16 indicator; /**< indicative signal quality low=0..100=high */ - } DRXSigQuality_t, *pDRXSigQuality_t; + } drx_sig_quality_t, *pdrx_sig_quality_t; typedef enum { DRX_SQI_SPEED_FAST = 0, DRX_SQI_SPEED_MEDIUM, DRX_SQI_SPEED_SLOW, DRX_SQI_SPEED_UNKNOWN = DRX_UNKNOWN - } DRXCfgSqiSpeed_t, *pDRXCfgSqiSpeed_t; + } drx_cfg_sqi_speed_t, *pdrx_cfg_sqi_speed_t; /*========================================*/ /** -* \struct DRXComplex_t +* \struct drx_complex_t * A complex number. * * Used by DRX_CTRL_CONSTEL. @@ -1173,12 +1173,12 @@ STRUCTS /**< Imaginary part. */ s16 re; /**< Real part. */ - } DRXComplex_t, *pDRXComplex_t; + } drx_complex_t, *pdrx_complex_t; /*========================================*/ /** -* \struct DRXFrequencyPlan_t +* \struct drx_frequency_plan_t * Array element of a frequency plan. * * Used by DRX_CTRL_SCAN_INIT. @@ -1192,72 +1192,72 @@ STRUCTS /**< Stepping frequency in this band */ enum drx_bandwidth bandwidth; /**< Bandwidth within this frequency band */ - u16 chNumber; + u16 ch_number; /**< First channel number in this band, or first - index in chNames */ - char **chNames; + index in ch_names */ + char **ch_names; /**< Optional list of channel names in this band */ - } DRXFrequencyPlan_t, *pDRXFrequencyPlan_t; + } drx_frequency_plan_t, *p_drx_frequency_plan_t; /*========================================*/ /** -* \struct DRXFrequencyPlanInfo_t +* \struct drx_frequency_plan_info_t * Array element of a list of frequency plans. * * Used by frequency_plan.h */ typedef struct { - pDRXFrequencyPlan_t freqPlan; - int freqPlanSize; - char *freqPlanName; - } DRXFrequencyPlanInfo_t, *pDRXFrequencyPlanInfo_t; + p_drx_frequency_plan_t freq_plan; + int freq_planSize; + char *freq_planName; + } drx_frequency_plan_info_t, *pdrx_frequency_plan_info_t; /*========================================*/ /** -* /struct DRXScanDataQam_t +* /struct drx_scan_data_qam_t * QAM specific scanning variables */ typedef struct { u32 *symbolrate; /**< list of symbolrates to scan */ - u16 symbolrateSize; /**< size of symbolrate array */ + u16 symbolrate_size; /**< size of symbolrate array */ enum drx_modulation *constellation; /**< list of constellations */ - u16 constellationSize; /**< size of constellation array */ - u16 ifAgcThreshold; /**< thresholf for IF-AGC based + u16 constellation_size; /**< size of constellation array */ + u16 if_agc_threshold; /**< thresholf for IF-AGC based scanning filter */ - } DRXScanDataQam_t, *pDRXScanDataQam_t; + } drx_scan_data_qam_t, *pdrx_scan_data_qam_t; /*========================================*/ /** -* /struct DRXScanDataAtv_t +* /struct drx_scan_data_atv_t * ATV specific scanning variables */ typedef struct { - s16 svrThreshold; + s16 svr_threshold; /**< threshold of Sound/Video ratio in 0.1dB steps */ - } DRXScanDataAtv_t, *pDRXScanDataAtv_t; + } drx_scan_data_atv_t, *pdrx_scan_data_atv_t; /*========================================*/ /** -* \struct DRXScanParam_t +* \struct drx_scan_param_t * Parameters for channel scan. * * Used by DRX_CTRL_SCAN_INIT. */ typedef struct { - pDRXFrequencyPlan_t frequencyPlan; + p_drx_frequency_plan_t frequency_plan; /**< Frequency plan (array)*/ - u16 frequencyPlanSize; /**< Number of bands */ - u32 numTries; /**< Max channels tried */ + u16 frequency_plan_size; /**< Number of bands */ + u32 num_tries; /**< Max channels tried */ s32 skip; /**< Minimum frequency step to take after a channel is found */ - void *extParams; /**< Standard specific params */ - } DRXScanParam_t, *pDRXScanParam_t; + void *ext_params; /**< Standard specific params */ + } drx_scan_param_t, *p_drx_scan_param_t; /*========================================*/ @@ -1269,22 +1269,22 @@ STRUCTS DRX_SCAN_COMMAND_INIT = 0,/**< Initialize scanning */ DRX_SCAN_COMMAND_NEXT, /**< Next scan */ DRX_SCAN_COMMAND_STOP /**< Stop scanning */ - } DRXScanCommand_t, *pDRXScanCommand_t; + } drx_scan_command_t, *pdrx_scan_command_t; /*========================================*/ /** * \brief Inner scan function prototype. */ - typedef int(*DRXScanFunc_t) (void *scanContext, - DRXScanCommand_t scanCommand, - pDRXChannel_t scanChannel, - bool *getNextChannel); + typedef int(*drx_scan_func_t) (void *scan_context, + drx_scan_command_t scan_command, + pdrx_channel_t scan_channel, + bool *get_next_channel); /*========================================*/ /** -* \struct DRXTPSInfo_t +* \struct drxtps_info_t * TPS information, DVB-T specific. * * Used by DRX_CTRL_TPS_INFO. @@ -1296,14 +1296,14 @@ STRUCTS /**< Constellation */ enum drx_hierarchy hierarchy; /**< Hierarchy */ - enum drx_coderate highCoderate; + enum drx_coderate high_coderate; /**< High code rate */ - enum drx_coderate lowCoderate; + enum drx_coderate low_coderate; /**< Low cod rate */ enum drx_tps_frame frame; /**< Tps frame */ u8 length; /**< Length */ - u16 cellId; /**< Cell id */ - } DRXTPSInfo_t, *pDRXTPSInfo_t; + u16 cell_id; /**< Cell id */ + } drxtps_info_t, *pdrxtps_info_t; /*========================================*/ @@ -1350,12 +1350,12 @@ STRUCTS /**< Device specific , Power Down Mode */ DRX_POWER_DOWN = 255 /**< Generic , Power Down Mode */ - } DRXPowerMode_t, *pDRXPowerMode_t; + } drx_power_mode_t, *pdrx_power_mode_t; /*========================================*/ /** -* \enum DRXModule_t +* \enum drx_module_t * \brief Software module identification. * * Used by DRX_CTRL_VERSION. @@ -1370,36 +1370,36 @@ STRUCTS DRX_MODULE_BSP_TUNER, DRX_MODULE_BSP_HOST, DRX_MODULE_UNKNOWN - } DRXModule_t, *pDRXModule_t; + } drx_module_t, *pdrx_module_t; /** -* \enum DRXVersion_t +* \enum drx_version_t * \brief Version information of one software module. * * Used by DRX_CTRL_VERSION. */ typedef struct { - DRXModule_t moduleType; + drx_module_t module_type; /**< Type identifier of the module */ - char *moduleName; + char *module_name; /**< Name or description of module */ - u16 vMajor; /**< Major version number */ - u16 vMinor; /**< Minor version number */ - u16 vPatch; /**< Patch version number */ - char *vString; /**< Version as text string */ - } DRXVersion_t, *pDRXVersion_t; + u16 v_major; /**< Major version number */ + u16 v_minor; /**< Minor version number */ + u16 v_patch; /**< Patch version number */ + char *v_string; /**< Version as text string */ + } drx_version_t, *pdrx_version_t; /** -* \enum DRXVersionList_t +* \enum drx_version_list_t * \brief List element of NULL terminated, linked list for version information. * * Used by DRX_CTRL_VERSION. */ - typedef struct DRXVersionList_s { - pDRXVersion_t version;/**< Version information */ - struct DRXVersionList_s *next; + typedef struct drx_version_list_s { + pdrx_version_t version;/**< Version information */ + struct drx_version_list_s *next; /**< Next list element */ - } DRXVersionList_t, *pDRXVersionList_t; + } drx_version_list_t, *p_drx_version_list_t; /*========================================*/ @@ -1411,9 +1411,9 @@ STRUCTS typedef struct { DRXUIO_t uio; /**< UIO identifier */ - DRXUIOMode_t mode; + drxuio_mode_t mode; /**< UIO operational mode */ - } DRXUIOCfg_t, *pDRXUIOCfg_t; + } drxuio_cfg_t, *pdrxuio_cfg_t; /*========================================*/ @@ -1427,7 +1427,7 @@ STRUCTS /**< UIO identifier */ bool value; /**< UIO value (true=1, false=0) */ - } DRXUIOData_t, *pDRXUIOData_t; + } drxuio_data_t, *pdrxuio_data_t; /*========================================*/ @@ -1438,11 +1438,11 @@ STRUCTS */ typedef struct { s32 frequency; /**< Frequency in kHz */ - DRXOOBDownstreamStandard_t standard; + drxoob_downstream_standard_t standard; /**< OOB standard */ - bool spectrumInverted; /**< If true, then spectrum + bool spectrum_inverted; /**< If true, then spectrum is inverted */ - } DRXOOB_t, *pDRXOOB_t; + } DRXOOB_t, *p_drxoob_t; /*========================================*/ @@ -1453,10 +1453,10 @@ STRUCTS */ typedef struct { s32 frequency; /**< Frequency in Khz */ - DRXLockStatus_t lock; /**< Lock status */ + drx_lock_status_t lock; /**< Lock status */ u32 mer; /**< MER */ - s32 symbolRateOffset; /**< Symbolrate offset in ppm */ - } DRXOOBStatus_t, *pDRXOOBStatus_t; + s32 symbol_rate_offset; /**< Symbolrate offset in ppm */ + } drxoob_status_t, *pdrxoob_status_t; /*========================================*/ @@ -1464,14 +1464,14 @@ STRUCTS * \brief Device dependent configuration data. * * Used by DRX_CTRL_SET_CFG and DRX_CTRL_GET_CFG. -* A sort of nested DRX_Ctrl() functionality for device specific controls. +* A sort of nested drx_ctrl() functionality for device specific controls. */ typedef struct { - DRXCfgType_t cfgType; + drx_cfg_type_t cfg_type; /**< Function identifier */ - void *cfgData; + void *cfg_data; /**< Function data */ - } DRXCfg_t, *pDRXCfg_t; + } drx_cfg_t, *pdrx_cfg_t; /*========================================*/ @@ -1483,11 +1483,11 @@ STRUCTS typedef enum { DRX_MPEG_STR_WIDTH_1, DRX_MPEG_STR_WIDTH_8 - } DRXMPEGStrWidth_t, *pDRXMPEGStrWidth_t; + } drxmpeg_str_width_t, *pdrxmpeg_str_width_t; /* CTRL CFG MPEG ouput */ /** -* \struct DRXCfgMPEGOutput_t +* \struct drx_cfg_mpeg_output_t * \brief Configuartion parameters for MPEG output control. * * Used by DRX_CFG_MPEG_OUTPUT, in combination with DRX_CTRL_SET_CFG and @@ -1495,71 +1495,71 @@ STRUCTS */ typedef struct { - bool enableMPEGOutput;/**< If true, enable MPEG output */ - bool insertRSByte; /**< If true, insert RS byte */ - bool enableParallel; /**< If true, parallel out otherwise + bool enable_mpeg_output;/**< If true, enable MPEG output */ + bool insert_rs_byte; /**< If true, insert RS byte */ + bool enable_parallel; /**< If true, parallel out otherwise serial */ - bool invertDATA; /**< If true, invert DATA signals */ - bool invertERR; /**< If true, invert ERR signal */ - bool invertSTR; /**< If true, invert STR signals */ - bool invertVAL; /**< If true, invert VAL signals */ - bool invertCLK; /**< If true, invert CLK signals */ - bool staticCLK; /**< If true, static MPEG clockrate + bool invert_data; /**< If true, invert DATA signals */ + bool invert_err; /**< If true, invert ERR signal */ + bool invert_str; /**< If true, invert STR signals */ + bool invert_val; /**< If true, invert VAL signals */ + bool invert_clk; /**< If true, invert CLK signals */ + bool static_clk; /**< If true, static MPEG clockrate will be used, otherwise clockrate will adapt to the bitrate of the TS */ u32 bitrate; /**< Maximum bitrate in b/s in case static clockrate is selected */ - DRXMPEGStrWidth_t widthSTR; + drxmpeg_str_width_t width_str; /**< MPEG start width */ - } DRXCfgMPEGOutput_t, *pDRXCfgMPEGOutput_t; + } drx_cfg_mpeg_output_t, *pdrx_cfg_mpeg_output_t; /* CTRL CFG SMA */ /** -* /struct DRXCfgSMAIO_t +* /struct drx_cfg_smaio_t * smart antenna i/o. */ - typedef enum DRXCfgSMAIO_t { + typedef enum drx_cfg_smaio_t { DRX_SMA_OUTPUT = 0, DRX_SMA_INPUT - } DRXCfgSMAIO_t, *pDRXCfgSMAIO_t; + } drx_cfg_smaio_t, *pdrx_cfg_smaio_t; /** -* /struct DRXCfgSMA_t +* /struct drx_cfg_sma_t * Set smart antenna. */ typedef struct { - DRXCfgSMAIO_t io; - u16 ctrlData; - bool smartAntInverted; - } DRXCfgSMA_t, *pDRXCfgSMA_t; + drx_cfg_smaio_t io; + u16 ctrl_data; + bool smart_ant_inverted; + } drx_cfg_sma_t, *pdrx_cfg_sma_t; /*========================================*/ /** -* \struct DRXI2CData_t +* \struct drxi2c_data_t * \brief Data for I2C via 2nd or 3rd or etc I2C port. * * Used by DRX_CTRL_I2C_READWRITE. -* If portNr is equal to primairy portNr BSPI2C will be used. +* If port_nr is equal to primairy port_nr BSPI2C will be used. * */ typedef struct { - u16 portNr; /**< I2C port number */ - struct i2c_device_addr *wDevAddr; + u16 port_nr; /**< I2C port number */ + struct i2c_device_addr *w_dev_addr; /**< Write device address */ - u16 wCount; /**< Size of write data in bytes */ + u16 w_count; /**< Size of write data in bytes */ u8 *wData; /**< Pointer to write data */ - struct i2c_device_addr *rDevAddr; + struct i2c_device_addr *r_dev_addr; /**< Read device address */ - u16 rCount; /**< Size of data to read in bytes */ - u8 *rData; /**< Pointer to read buffer */ - } DRXI2CData_t, *pDRXI2CData_t; + u16 r_count; /**< Size of data to read in bytes */ + u8 *r_data; /**< Pointer to read buffer */ + } drxi2c_data_t, *pdrxi2c_data_t; /*========================================*/ /** -* \enum DRXAudStandard_t +* \enum drx_aud_standard_t * \brief Audio standard identifier. * * Used by DRX_CTRL_SET_AUD. @@ -1588,11 +1588,11 @@ STRUCTS /**< Automatic Standard Detection */ DRX_AUD_STANDARD_UNKNOWN = DRX_UNKNOWN /**< used as auto and for readback */ - } DRXAudStandard_t, *pDRXAudStandard_t; + } drx_aud_standard_t, *pdrx_aud_standard_t; -/* CTRL_AUD_GET_STATUS - DRXAudStatus_t */ +/* CTRL_AUD_GET_STATUS - drx_aud_status_t */ /** -* \enum DRXAudNICAMStatus_t +* \enum drx_aud_nicam_status_t * \brief Status of NICAM carrier. */ typedef enum { @@ -1601,22 +1601,22 @@ STRUCTS DRX_AUD_NICAM_NOT_DETECTED, /**< NICAM carrier not detected */ DRX_AUD_NICAM_BAD /**< NICAM carrier bad quality */ - } DRXAudNICAMStatus_t, *pDRXAudNICAMStatus_t; + } drx_aud_nicam_status_t, *pdrx_aud_nicam_status_t; /** -* \struct DRXAudStatus_t +* \struct drx_aud_status_t * \brief Audio status characteristics. */ typedef struct { bool stereo; /**< stereo detection */ - bool carrierA; /**< carrier A detected */ - bool carrierB; /**< carrier B detected */ + bool carrier_a; /**< carrier A detected */ + bool carrier_b; /**< carrier B detected */ bool sap; /**< sap / bilingual detection */ bool rds; /**< RDS data array present */ - DRXAudNICAMStatus_t nicamStatus; + drx_aud_nicam_status_t nicam_status; /**< status of NICAM carrier */ - s8 fmIdent; /**< FM Identification value */ - } DRXAudStatus_t, *pDRXAudStatus_t; + s8 fm_ident; /**< FM Identification value */ + } drx_aud_status_t, *pdrx_aud_status_t; /* CTRL_AUD_READ_RDS - DRXRDSdata_t */ @@ -1627,9 +1627,9 @@ STRUCTS typedef struct { bool valid; /**< RDS data validation */ u16 data[18]; /**< data from one RDS data array */ - } DRXCfgAudRDS_t, *pDRXCfgAudRDS_t; + } drx_cfg_aud_rds_t, *pdrx_cfg_aud_rds_t; -/* DRX_CFG_AUD_VOLUME - DRXCfgAudVolume_t - set/get */ +/* DRX_CFG_AUD_VOLUME - drx_cfg_aud_volume_t - set/get */ /** * \enum DRXAudAVCDecayTime_t * \brief Automatic volume control configuration. @@ -1640,7 +1640,7 @@ STRUCTS DRX_AUD_AVC_DECAYTIME_4S, /**< level volume in 4 seconds */ DRX_AUD_AVC_DECAYTIME_2S, /**< level volume in 2 seconds */ DRX_AUD_AVC_DECAYTIME_20MS/**< level volume in 20 millisec */ - } DRXAudAVCMode_t, *pDRXAudAVCMode_t; + } drx_aud_avc_mode_t, *pdrx_aud_avc_mode_t; /** * /enum DRXAudMaxAVCGain_t @@ -1650,7 +1650,7 @@ STRUCTS DRX_AUD_AVC_MAX_GAIN_0DB, /**< maximum AVC gain 0 dB */ DRX_AUD_AVC_MAX_GAIN_6DB, /**< maximum AVC gain 6 dB */ DRX_AUD_AVC_MAX_GAIN_12DB /**< maximum AVC gain 12 dB */ - } DRXAudAVCMaxGain_t, *pDRXAudAVCMaxGain_t; + } drx_aud_avc_max_gain_t, *pdrx_aud_avc_max_gain_t; /** * /enum DRXAudMaxAVCAtten_t @@ -1662,45 +1662,45 @@ STRUCTS DRX_AUD_AVC_MAX_ATTEN_18DB, /**< maximum AVC attenuation 18 dB */ DRX_AUD_AVC_MAX_ATTEN_24DB/**< maximum AVC attenuation 24 dB */ - } DRXAudAVCMaxAtten_t, *pDRXAudAVCMaxAtten_t; + } drx_aud_avc_max_atten_t, *pdrx_aud_avc_max_atten_t; /** -* \struct DRXCfgAudVolume_t +* \struct drx_cfg_aud_volume_t * \brief Audio volume configuration. */ typedef struct { bool mute; /**< mute overrides volume setting */ s16 volume; /**< volume, range -114 to 12 dB */ - DRXAudAVCMode_t avcMode; /**< AVC auto volume control mode */ - u16 avcRefLevel; /**< AVC reference level */ - DRXAudAVCMaxGain_t avcMaxGain; + drx_aud_avc_mode_t avc_mode; /**< AVC auto volume control mode */ + u16 avc_ref_level; /**< AVC reference level */ + drx_aud_avc_max_gain_t avc_max_gain; /**< AVC max gain selection */ - DRXAudAVCMaxAtten_t avcMaxAtten; + drx_aud_avc_max_atten_t avc_max_atten; /**< AVC max attenuation selection */ - s16 strengthLeft; /**< quasi-peak, left speaker */ - s16 strengthRight; /**< quasi-peak, right speaker */ - } DRXCfgAudVolume_t, *pDRXCfgAudVolume_t; + s16 strength_left; /**< quasi-peak, left speaker */ + s16 strength_right; /**< quasi-peak, right speaker */ + } drx_cfg_aud_volume_t, *pdrx_cfg_aud_volume_t; -/* DRX_CFG_I2S_OUTPUT - DRXCfgI2SOutput_t - set/get */ +/* DRX_CFG_I2S_OUTPUT - drx_cfg_i2s_output_t - set/get */ /** -* \enum DRXI2SMode_t +* \enum drxi2s_mode_t * \brief I2S output mode. */ typedef enum { DRX_I2S_MODE_MASTER, /**< I2S is in master mode */ DRX_I2S_MODE_SLAVE /**< I2S is in slave mode */ - } DRXI2SMode_t, *pDRXI2SMode_t; + } drxi2s_mode_t, *pdrxi2s_mode_t; /** -* \enum DRXI2SWordLength_t +* \enum drxi2s_word_length_t * \brief Width of I2S data. */ typedef enum { DRX_I2S_WORDLENGTH_32 = 0,/**< I2S data is 32 bit wide */ DRX_I2S_WORDLENGTH_16 = 1 /**< I2S data is 16 bit wide */ - } DRXI2SWordLength_t, *pDRXI2SWordLength_t; + } drxi2s_word_length_t, *pdrxi2s_word_length_t; /** -* \enum DRXI2SFormat_t +* \enum drxi2s_format_t * \brief Data wordstrobe alignment for I2S. */ typedef enum { @@ -1708,34 +1708,34 @@ STRUCTS /**< I2S data and wordstrobe are aligned */ DRX_I2S_FORMAT_WS_ADVANCED /**< I2S data one cycle after wordstrobe */ - } DRXI2SFormat_t, *pDRXI2SFormat_t; + } drxi2s_format_t, *pdrxi2s_format_t; /** -* \enum DRXI2SPolarity_t +* \enum drxi2s_polarity_t * \brief Polarity of I2S data. */ typedef enum { DRX_I2S_POLARITY_RIGHT,/**< wordstrobe - right high, left low */ DRX_I2S_POLARITY_LEFT /**< wordstrobe - right low, left high */ - } DRXI2SPolarity_t, *pDRXI2SPolarity_t; + } drxi2s_polarity_t, *pdrxi2s_polarity_t; /** -* \struct DRXCfgI2SOutput_t +* \struct drx_cfg_i2s_output_t * \brief I2S output configuration. */ typedef struct { - bool outputEnable; /**< I2S output enable */ + bool output_enable; /**< I2S output enable */ u32 frequency; /**< range from 8000-48000 Hz */ - DRXI2SMode_t mode; /**< I2S mode, master or slave */ - DRXI2SWordLength_t wordLength; + drxi2s_mode_t mode; /**< I2S mode, master or slave */ + drxi2s_word_length_t word_length; /**< I2S wordlength, 16 or 32 bits */ - DRXI2SPolarity_t polarity;/**< I2S wordstrobe polarity */ - DRXI2SFormat_t format; /**< I2S wordstrobe delay to data */ - } DRXCfgI2SOutput_t, *pDRXCfgI2SOutput_t; + drxi2s_polarity_t polarity;/**< I2S wordstrobe polarity */ + drxi2s_format_t format; /**< I2S wordstrobe delay to data */ + } drx_cfg_i2s_output_t, *pdrx_cfg_i2s_output_t; /* ------------------------------expert interface-----------------------------*/ /** -* /enum DRXAudFMDeemphasis_t +* /enum drx_aud_fm_deemphasis_t * setting for FM-Deemphasis in audio demodulator. * */ @@ -1743,7 +1743,7 @@ STRUCTS DRX_AUD_FM_DEEMPH_50US, DRX_AUD_FM_DEEMPH_75US, DRX_AUD_FM_DEEMPH_OFF - } DRXAudFMDeemphasis_t, *pDRXAudFMDeemphasis_t; + } drx_aud_fm_deemphasis_t, *pdrx_aud_fm_deemphasis_t; /** * /enum DRXAudDeviation_t @@ -1753,17 +1753,17 @@ STRUCTS typedef enum { DRX_AUD_DEVIATION_NORMAL, DRX_AUD_DEVIATION_HIGH - } DRXCfgAudDeviation_t, *pDRXCfgAudDeviation_t; + } drx_cfg_aud_deviation_t, *pdrx_cfg_aud_deviation_t; /** -* /enum DRXNoCarrierOption_t +* /enum drx_no_carrier_option_t * setting for carrier, mute/noise. * */ typedef enum { DRX_NO_CARRIER_MUTE, DRX_NO_CARRIER_NOISE - } DRXNoCarrierOption_t, *pDRXNoCarrierOption_t; + } drx_no_carrier_option_t, *pdrx_no_carrier_option_t; /** * \enum DRXAudAutoSound_t @@ -1773,7 +1773,7 @@ STRUCTS DRX_AUD_AUTO_SOUND_OFF = 0, DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON, DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_OFF - } DRXCfgAudAutoSound_t, *pDRXCfgAudAutoSound_t; + } drx_cfg_aud_auto_sound_t, *pdrx_cfg_aud_auto_sound_t; /** * \enum DRXAudASSThres_t @@ -1783,30 +1783,30 @@ STRUCTS u16 a2; /* A2 Threshold for ASS configuration */ u16 btsc; /* BTSC Threshold for ASS configuration */ u16 nicam; /* Nicam Threshold for ASS configuration */ - } DRXCfgAudASSThres_t, *pDRXCfgAudASSThres_t; + } drx_cfg_aud_ass_thres_t, *pdrx_cfg_aud_ass_thres_t; /** -* \struct DRXAudCarrier_t +* \struct drx_aud_carrier_t * \brief Carrier detection related parameters */ typedef struct { u16 thres; /* carrier detetcion threshold for primary carrier (A) */ - DRXNoCarrierOption_t opt; /* Mute or noise at no carrier detection (A) */ + drx_no_carrier_option_t opt; /* Mute or noise at no carrier detection (A) */ s32 shift; /* DC level of incoming signal (A) */ s32 dco; /* frequency adjustment (A) */ - } DRXAudCarrier_t, *pDRXCfgAudCarrier_t; + } drx_aud_carrier_t, *p_drx_cfg_aud_carrier_t; /** -* \struct DRXCfgAudCarriers_t +* \struct drx_cfg_aud_carriers_t * \brief combining carrier A & B to one struct */ typedef struct { - DRXAudCarrier_t a; - DRXAudCarrier_t b; - } DRXCfgAudCarriers_t, *pDRXCfgAudCarriers_t; + drx_aud_carrier_t a; + drx_aud_carrier_t b; + } drx_cfg_aud_carriers_t, *pdrx_cfg_aud_carriers_t; /** -* /enum DRXAudI2SSrc_t +* /enum drx_aud_i2s_src_t * Selection of audio source */ typedef enum { @@ -1814,10 +1814,10 @@ STRUCTS DRX_AUD_SRC_STEREO_OR_AB, DRX_AUD_SRC_STEREO_OR_A, DRX_AUD_SRC_STEREO_OR_B - } DRXAudI2SSrc_t, *pDRXAudI2SSrc_t; + } drx_aud_i2s_src_t, *pdrx_aud_i2s_src_t; /** -* \enum DRXAudI2SMatrix_t +* \enum drx_aud_i2s_matrix_t * \brief Used for selecting I2S output. */ typedef enum { @@ -1828,10 +1828,10 @@ STRUCTS DRX_AUD_I2S_MATRIX_STEREO, /**< A+B sound, transparant */ DRX_AUD_I2S_MATRIX_MONO /**< A+B mixed to mono sum, (L+R)/2 */ - } DRXAudI2SMatrix_t, *pDRXAudI2SMatrix_t; + } drx_aud_i2s_matrix_t, *pdrx_aud_i2s_matrix_t; /** -* /enum DRXAudFMMatrix_t +* /enum drx_aud_fm_matrix_t * setting for FM-Matrix in audio demodulator. * */ @@ -1841,17 +1841,17 @@ STRUCTS DRX_AUD_FM_MATRIX_KOREAN, DRX_AUD_FM_MATRIX_SOUND_A, DRX_AUD_FM_MATRIX_SOUND_B - } DRXAudFMMatrix_t, *pDRXAudFMMatrix_t; + } drx_aud_fm_matrix_t, *pdrx_aud_fm_matrix_t; /** * \struct DRXAudMatrices_t * \brief Mixer settings */ typedef struct { - DRXAudI2SSrc_t sourceI2S; - DRXAudI2SMatrix_t matrixI2S; - DRXAudFMMatrix_t matrixFm; - } DRXCfgAudMixer_t, *pDRXCfgAudMixer_t; + drx_aud_i2s_src_t source_i2s; + drx_aud_i2s_matrix_t matrix_i2s; + drx_aud_fm_matrix_t matrix_fm; + } drx_cfg_aud_mixer_t, *pdrx_cfg_aud_mixer_t; /** * \enum DRXI2SVidSync_t @@ -1867,68 +1867,68 @@ STRUCTS /**< it is a MONOCHROME system */ DRX_AUD_AVSYNC_PAL_SECAM /**< it is a PAL/SECAM system */ - } DRXCfgAudAVSync_t, *pDRXCfgAudAVSync_t; + } drx_cfg_aud_av_sync_t, *pdrx_cfg_aud_av_sync_t; /** -* \struct DRXCfgAudPrescale_t +* \struct drx_cfg_aud_prescale_t * \brief Prescalers */ typedef struct { - u16 fmDeviation; - s16 nicamGain; - } DRXCfgAudPrescale_t, *pDRXCfgAudPrescale_t; + u16 fm_deviation; + s16 nicam_gain; + } drx_cfg_aud_prescale_t, *pdrx_cfg_aud_prescale_t; /** -* \struct DRXAudBeep_t +* \struct drx_aud_beep_t * \brief Beep */ typedef struct { s16 volume; /* dB */ u16 frequency; /* Hz */ bool mute; - } DRXAudBeep_t, *pDRXAudBeep_t; + } drx_aud_beep_t, *pdrx_aud_beep_t; /** -* \enum DRXAudBtscDetect_t +* \enum drx_aud_btsc_detect_t * \brief BTSC detetcion mode */ typedef enum { DRX_BTSC_STEREO, DRX_BTSC_MONO_AND_SAP - } DRXAudBtscDetect_t, *pDRXAudBtscDetect_t; + } drx_aud_btsc_detect_t, *pdrx_aud_btsc_detect_t; /** -* \struct DRXAudData_t +* \struct drx_aud_data_t * \brief Audio data structure */ typedef struct { /* audio storage */ - bool audioIsActive; - DRXAudStandard_t audioStandard; - DRXCfgI2SOutput_t i2sdata; - DRXCfgAudVolume_t volume; - DRXCfgAudAutoSound_t autoSound; - DRXCfgAudASSThres_t assThresholds; - DRXCfgAudCarriers_t carriers; - DRXCfgAudMixer_t mixer; - DRXCfgAudDeviation_t deviation; - DRXCfgAudAVSync_t avSync; - DRXCfgAudPrescale_t prescale; - DRXAudFMDeemphasis_t deemph; - DRXAudBtscDetect_t btscDetect; + bool audio_is_active; + drx_aud_standard_t audio_standard; + drx_cfg_i2s_output_t i2sdata; + drx_cfg_aud_volume_t volume; + drx_cfg_aud_auto_sound_t auto_sound; + drx_cfg_aud_ass_thres_t ass_thresholds; + drx_cfg_aud_carriers_t carriers; + drx_cfg_aud_mixer_t mixer; + drx_cfg_aud_deviation_t deviation; + drx_cfg_aud_av_sync_t av_sync; + drx_cfg_aud_prescale_t prescale; + drx_aud_fm_deemphasis_t deemph; + drx_aud_btsc_detect_t btsc_detect; /* rds */ - u16 rdsDataCounter; - bool rdsDataPresent; - } DRXAudData_t, *pDRXAudData_t; + u16 rds_data_counter; + bool rds_data_present; + } drx_aud_data_t, *pdrx_aud_data_t; /** -* \enum DRXQamLockRange_t +* \enum drx_qam_lock_range_t * \brief QAM lock range mode */ typedef enum { DRX_QAM_LOCKRANGE_NORMAL, DRX_QAM_LOCKRANGE_EXTENDED - } DRXQamLockRange_t, *pDRXQamLockRange_t; + } drx_qam_lock_range_t, *pdrx_qam_lock_range_t; /*============================================================================*/ /*============================================================================*/ @@ -1937,108 +1937,108 @@ STRUCTS /*============================================================================*/ /* Address on device */ - typedef u32 DRXaddr_t, *pDRXaddr_t; + typedef u32 dr_xaddr_t, *pdr_xaddr_t; /* Protocol specific flags */ - typedef u32 DRXflags_t, *pDRXflags_t; + typedef u32 dr_xflags_t, *pdr_xflags_t; /* Write block of data to device */ - typedef int(*DRXWriteBlockFunc_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ - DRXaddr_t addr, /* address of register/memory */ + typedef int(*drx_write_block_func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ + dr_xaddr_t addr, /* address of register/memory */ u16 datasize, /* size of data in bytes */ u8 *data, /* data to send */ - DRXflags_t flags); + dr_xflags_t flags); /* Read block of data from device */ - typedef int(*DRXReadBlockFunc_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ - DRXaddr_t addr, /* address of register/memory */ + typedef int(*drx_read_block_func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ + dr_xaddr_t addr, /* address of register/memory */ u16 datasize, /* size of data in bytes */ u8 *data, /* receive buffer */ - DRXflags_t flags); + dr_xflags_t flags); /* Write 8-bits value to device */ - typedef int(*DRXWriteReg8Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ - DRXaddr_t addr, /* address of register/memory */ + typedef int(*drx_write_reg8func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ + dr_xaddr_t addr, /* address of register/memory */ u8 data, /* data to send */ - DRXflags_t flags); + dr_xflags_t flags); /* Read 8-bits value to device */ - typedef int(*DRXReadReg8Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ - DRXaddr_t addr, /* address of register/memory */ + typedef int(*drx_read_reg8func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ + dr_xaddr_t addr, /* address of register/memory */ u8 *data, /* receive buffer */ - DRXflags_t flags); + dr_xflags_t flags); /* Read modify write 8-bits value to device */ - typedef int(*DRXReadModifyWriteReg8Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ - DRXaddr_t waddr, /* write address of register */ - DRXaddr_t raddr, /* read address of register */ + typedef int(*drx_read_modify_write_reg8func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ + dr_xaddr_t waddr, /* write address of register */ + dr_xaddr_t raddr, /* read address of register */ u8 wdata, /* data to write */ u8 *rdata); /* data to read */ /* Write 16-bits value to device */ - typedef int(*DRXWriteReg16Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ - DRXaddr_t addr, /* address of register/memory */ + typedef int(*drx_write_reg16func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ + dr_xaddr_t addr, /* address of register/memory */ u16 data, /* data to send */ - DRXflags_t flags); + dr_xflags_t flags); /* Read 16-bits value to device */ - typedef int(*DRXReadReg16Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ - DRXaddr_t addr, /* address of register/memory */ + typedef int(*drx_read_reg16func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ + dr_xaddr_t addr, /* address of register/memory */ u16 *data, /* receive buffer */ - DRXflags_t flags); + dr_xflags_t flags); /* Read modify write 16-bits value to device */ - typedef int(*DRXReadModifyWriteReg16Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ - DRXaddr_t waddr, /* write address of register */ - DRXaddr_t raddr, /* read address of register */ + typedef int(*drx_read_modify_write_reg16func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ + dr_xaddr_t waddr, /* write address of register */ + dr_xaddr_t raddr, /* read address of register */ u16 wdata, /* data to write */ u16 *rdata); /* data to read */ /* Write 32-bits value to device */ - typedef int(*DRXWriteReg32Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ - DRXaddr_t addr, /* address of register/memory */ + typedef int(*drx_write_reg32func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ + dr_xaddr_t addr, /* address of register/memory */ u32 data, /* data to send */ - DRXflags_t flags); + dr_xflags_t flags); /* Read 32-bits value to device */ - typedef int(*DRXReadReg32Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ - DRXaddr_t addr, /* address of register/memory */ + typedef int(*drx_read_reg32func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ + dr_xaddr_t addr, /* address of register/memory */ u32 *data, /* receive buffer */ - DRXflags_t flags); + dr_xflags_t flags); /* Read modify write 32-bits value to device */ - typedef int(*DRXReadModifyWriteReg32Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */ - DRXaddr_t waddr, /* write address of register */ - DRXaddr_t raddr, /* read address of register */ + typedef int(*drx_read_modify_write_reg32func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ + dr_xaddr_t waddr, /* write address of register */ + dr_xaddr_t raddr, /* read address of register */ u32 wdata, /* data to write */ u32 *rdata); /* data to read */ /** -* \struct DRXAccessFunc_t +* \struct drx_access_func_t * \brief Interface to an access protocol. */ typedef struct { - pDRXVersion_t protocolVersion; - DRXWriteBlockFunc_t writeBlockFunc; - DRXReadBlockFunc_t readBlockFunc; - DRXWriteReg8Func_t writeReg8Func; - DRXReadReg8Func_t readReg8Func; - DRXReadModifyWriteReg8Func_t readModifyWriteReg8Func; - DRXWriteReg16Func_t writeReg16Func; - DRXReadReg16Func_t readReg16Func; - DRXReadModifyWriteReg16Func_t readModifyWriteReg16Func; - DRXWriteReg32Func_t writeReg32Func; - DRXReadReg32Func_t readReg32Func; - DRXReadModifyWriteReg32Func_t readModifyWriteReg32Func; - } DRXAccessFunc_t, *pDRXAccessFunc_t; + pdrx_version_t protocolVersion; + drx_write_block_func_t write_block_func; + drx_read_block_func_t read_block_func; + drx_write_reg8func_t write_reg8func; + drx_read_reg8func_t read_reg8func; + drx_read_modify_write_reg8func_t read_modify_write_reg8func; + drx_write_reg16func_t write_reg16func; + drx_read_reg16func_t read_reg16func; + drx_read_modify_write_reg16func_t read_modify_write_reg16func; + drx_write_reg32func_t write_reg32func; + drx_read_reg32func_t read_reg32func; + drx_read_modify_write_reg32func_t read_modify_write_reg32func; + } drx_access_func_t, *pdrx_access_func_t; /* Register address and data for register dump function */ typedef struct { - DRXaddr_t address; + dr_xaddr_t address; u32 data; - } DRXRegDump_t, *pDRXRegDump_t; + } drx_reg_dump_t, *p_drx_reg_dump_t; /*============================================================================*/ /*============================================================================*/ @@ -2047,131 +2047,131 @@ STRUCTS /*============================================================================*/ /** -* \struct DRXCommonAttr_t +* \struct drx_common_attr_t * \brief Set of common attributes, shared by all DRX devices. */ typedef struct { /* Microcode (firmware) attributes */ u8 *microcode; /**< Pointer to microcode image. */ - u16 microcodeSize; + u16 microcode_size; /**< Size of microcode image in bytes. */ - bool verifyMicrocode; + bool verify_microcode; /**< Use microcode verify or not. */ - DRXMcVersionRec_t mcversion; + drx_mc_version_rec_t mcversion; /**< Version record of microcode from file */ /* Clocks and tuner attributes */ - s32 intermediateFreq; + s32 intermediate_freq; /**< IF,if tuner instance not used. (kHz)*/ - s32 sysClockFreq; + s32 sys_clock_freq; /**< Systemclock frequency. (kHz) */ - s32 oscClockFreq; + s32 osc_clock_freq; /**< Oscillator clock frequency. (kHz) */ - s16 oscClockDeviation; + s16 osc_clock_deviation; /**< Oscillator clock deviation. (ppm) */ - bool mirrorFreqSpect; + bool mirror_freq_spect; /**< Mirror IF frequency spectrum or not.*/ /* Initial MPEG output attributes */ - DRXCfgMPEGOutput_t mpegCfg; + drx_cfg_mpeg_output_t mpeg_cfg; /**< MPEG configuration */ - bool isOpened; /**< if true instance is already opened. */ + bool is_opened; /**< if true instance is already opened. */ /* Channel scan */ - pDRXScanParam_t scanParam; + p_drx_scan_param_t scan_param; /**< scan parameters */ - u16 scanFreqPlanIndex; + u16 scan_freq_plan_index; /**< next index in freq plan */ - s32 scanNextFrequency; + s32 scan_next_frequency; /**< next freq to scan */ - bool scanReady; /**< scan ready flag */ - u32 scanMaxChannels;/**< number of channels in freqplan */ - u32 scanChannelsScanned; + bool scan_ready; /**< scan ready flag */ + u32 scan_max_channels;/**< number of channels in freqplan */ + u32 scan_channelsScanned; /**< number of channels scanned */ /* Channel scan - inner loop: demod related */ - DRXScanFunc_t scanFunction; + drx_scan_func_t scan_function; /**< function to check channel */ /* Channel scan - inner loop: SYSObj related */ - void *scanContext; /**< Context Pointer of SYSObj */ + void *scan_context; /**< Context Pointer of SYSObj */ /* Channel scan - parameters for default DTV scan function in core driver */ - u16 scanDemodLockTimeout; + u16 scan_demod_lock_timeout; /**< millisecs to wait for lock */ - DRXLockStatus_t scanDesiredLock; + drx_lock_status_t scan_desired_lock; /**< lock requirement for channel found */ - /* scanActive can be used by SetChannel to decide how to program the tuner, + /* scan_active can be used by SetChannel to decide how to program the tuner, fast or slow (but stable). Usually fast during scan. */ - bool scanActive; /**< true when scan routines are active */ + bool scan_active; /**< true when scan routines are active */ /* Power management */ - DRXPowerMode_t currentPowerMode; + drx_power_mode_t current_power_mode; /**< current power management mode */ /* Tuner */ - u8 tunerPortNr; /**< nr of I2C port to wich tuner is */ - s32 tunerMinFreqRF; + u8 tuner_port_nr; /**< nr of I2C port to wich tuner is */ + s32 tuner_min_freq_rf; /**< minimum RF input frequency, in kHz */ - s32 tunerMaxFreqRF; + s32 tuner_max_freq_rf; /**< maximum RF input frequency, in kHz */ - bool tunerRfAgcPol; /**< if true invert RF AGC polarity */ - bool tunerIfAgcPol; /**< if true invert IF AGC polarity */ - bool tunerSlowMode; /**< if true invert IF AGC polarity */ + bool tuner_rf_agc_pol; /**< if true invert RF AGC polarity */ + bool tuner_if_agc_pol; /**< if true invert IF AGC polarity */ + bool tuner_slow_mode; /**< if true invert IF AGC polarity */ - DRXChannel_t currentChannel; + drx_channel_t current_channel; /**< current channel parameters */ - enum drx_standard currentStandard; + enum drx_standard current_standard; /**< current standard selection */ - enum drx_standard prevStandard; + enum drx_standard prev_standard; /**< previous standard selection */ - enum drx_standard diCacheStandard; + enum drx_standard di_cache_standard; /**< standard in DI cache if available */ - bool useBootloader; /**< use bootloader in open */ + bool use_bootloader; /**< use bootloader in open */ u32 capabilities; /**< capabilities flags */ - u32 productId; /**< product ID inc. metal fix number */ + u32 product_id; /**< product ID inc. metal fix number */ - } DRXCommonAttr_t, *pDRXCommonAttr_t; + } drx_common_attr_t, *pdrx_common_attr_t; /* * Generic functions for DRX devices. */ - typedef struct DRXDemodInstance_s *pDRXDemodInstance_t; + typedef struct drx_demod_instance_s *pdrx_demod_instance_t; - typedef int(*DRXOpenFunc_t) (pDRXDemodInstance_t demod); - typedef int(*DRXCloseFunc_t) (pDRXDemodInstance_t demod); - typedef int(*DRXCtrlFunc_t) (pDRXDemodInstance_t demod, + typedef int(*drx_open_func_t) (pdrx_demod_instance_t demod); + typedef int(*drx_close_func_t) (pdrx_demod_instance_t demod); + typedef int(*drx_ctrl_func_t) (pdrx_demod_instance_t demod, u32 ctrl, - void *ctrlData); + void *ctrl_data); /** -* \struct DRXDemodFunc_t +* \struct drx_demod_func_t * \brief A stucture containing all functions of a demodulator. */ typedef struct { - u32 typeId; /**< Device type identifier. */ - DRXOpenFunc_t openFunc; /**< Pointer to Open() function. */ - DRXCloseFunc_t closeFunc;/**< Pointer to Close() function. */ - DRXCtrlFunc_t ctrlFunc; /**< Pointer to Ctrl() function. */ - } DRXDemodFunc_t, *pDRXDemodFunc_t; + u32 type_id; /**< Device type identifier. */ + drx_open_func_t open_func; /**< Pointer to Open() function. */ + drx_close_func_t close_func;/**< Pointer to Close() function. */ + drx_ctrl_func_t ctrl_func; /**< Pointer to Ctrl() function. */ + } drx_demod_func_t, *pdrx_demod_func_t; /** -* \struct DRXDemodInstance_t +* \struct drx_demod_instance_t * \brief Top structure of demodulator instance. */ - typedef struct DRXDemodInstance_s { + typedef struct drx_demod_instance_s { /* type specific demodulator data */ - pDRXDemodFunc_t myDemodFunct; + pdrx_demod_func_t my_demod_funct; /**< demodulator functions */ - pDRXAccessFunc_t myAccessFunct; + pdrx_access_func_t my_access_funct; /**< data access protocol functions */ - struct tuner_instance *myTuner; + struct tuner_instance *my_tuner; /**< tuner instance,if NULL then baseband */ - struct i2c_device_addr *myI2CDevAddr; + struct i2c_device_addr *my_i2c_dev_addr; /**< i2c address and device identifier */ - pDRXCommonAttr_t myCommonAttr; + pdrx_common_attr_t my_common_attr; /**< common DRX attributes */ - void *myExtAttr; /**< device specific attributes */ + void *my_ext_attr; /**< device specific attributes */ /* generic demodulator data */ - } DRXDemodInstance_t; + } drx_demod_instance_t; /*------------------------------------------------------------------------- MACROS @@ -2466,29 +2466,29 @@ Access macros * */ -#define DRX_ATTR_MCRECORD(d) ((d)->myCommonAttr->mcversion) -#define DRX_ATTR_MIRRORFREQSPECT(d) ((d)->myCommonAttr->mirrorFreqSpect) -#define DRX_ATTR_CURRENTPOWERMODE(d)((d)->myCommonAttr->currentPowerMode) -#define DRX_ATTR_ISOPENED(d) ((d)->myCommonAttr->isOpened) -#define DRX_ATTR_USEBOOTLOADER(d) ((d)->myCommonAttr->useBootloader) -#define DRX_ATTR_CURRENTSTANDARD(d) ((d)->myCommonAttr->currentStandard) -#define DRX_ATTR_PREVSTANDARD(d) ((d)->myCommonAttr->prevStandard) -#define DRX_ATTR_CACHESTANDARD(d) ((d)->myCommonAttr->diCacheStandard) -#define DRX_ATTR_CURRENTCHANNEL(d) ((d)->myCommonAttr->currentChannel) -#define DRX_ATTR_MICROCODE(d) ((d)->myCommonAttr->microcode) -#define DRX_ATTR_MICROCODESIZE(d) ((d)->myCommonAttr->microcodeSize) -#define DRX_ATTR_VERIFYMICROCODE(d) ((d)->myCommonAttr->verifyMicrocode) -#define DRX_ATTR_CAPABILITIES(d) ((d)->myCommonAttr->capabilities) -#define DRX_ATTR_PRODUCTID(d) ((d)->myCommonAttr->productId) -#define DRX_ATTR_INTERMEDIATEFREQ(d) ((d)->myCommonAttr->intermediateFreq) -#define DRX_ATTR_SYSCLOCKFREQ(d) ((d)->myCommonAttr->sysClockFreq) -#define DRX_ATTR_TUNERRFAGCPOL(d) ((d)->myCommonAttr->tunerRfAgcPol) -#define DRX_ATTR_TUNERIFAGCPOL(d) ((d)->myCommonAttr->tunerIfAgcPol) -#define DRX_ATTR_TUNERSLOWMODE(d) ((d)->myCommonAttr->tunerSlowMode) -#define DRX_ATTR_TUNERSPORTNR(d) ((d)->myCommonAttr->tunerPortNr) -#define DRX_ATTR_TUNER(d) ((d)->myTuner) -#define DRX_ATTR_I2CADDR(d) ((d)->myI2CDevAddr->i2cAddr) -#define DRX_ATTR_I2CDEVID(d) ((d)->myI2CDevAddr->i2cDevId) +#define DRX_ATTR_MCRECORD(d) ((d)->my_common_attr->mcversion) +#define DRX_ATTR_MIRRORFREQSPECT(d) ((d)->my_common_attr->mirror_freq_spect) +#define DRX_ATTR_CURRENTPOWERMODE(d)((d)->my_common_attr->current_power_mode) +#define DRX_ATTR_ISOPENED(d) ((d)->my_common_attr->is_opened) +#define DRX_ATTR_USEBOOTLOADER(d) ((d)->my_common_attr->use_bootloader) +#define DRX_ATTR_CURRENTSTANDARD(d) ((d)->my_common_attr->current_standard) +#define DRX_ATTR_PREVSTANDARD(d) ((d)->my_common_attr->prev_standard) +#define DRX_ATTR_CACHESTANDARD(d) ((d)->my_common_attr->di_cache_standard) +#define DRX_ATTR_CURRENTCHANNEL(d) ((d)->my_common_attr->current_channel) +#define DRX_ATTR_MICROCODE(d) ((d)->my_common_attr->microcode) +#define DRX_ATTR_MICROCODESIZE(d) ((d)->my_common_attr->microcode_size) +#define DRX_ATTR_VERIFYMICROCODE(d) ((d)->my_common_attr->verify_microcode) +#define DRX_ATTR_CAPABILITIES(d) ((d)->my_common_attr->capabilities) +#define DRX_ATTR_PRODUCTID(d) ((d)->my_common_attr->product_id) +#define DRX_ATTR_INTERMEDIATEFREQ(d) ((d)->my_common_attr->intermediate_freq) +#define DRX_ATTR_SYSCLOCKFREQ(d) ((d)->my_common_attr->sys_clock_freq) +#define DRX_ATTR_TUNERRFAGCPOL(d) ((d)->my_common_attr->tuner_rf_agc_pol) +#define DRX_ATTR_TUNERIFAGCPOL(d) ((d)->my_common_attr->tuner_if_agc_pol) +#define DRX_ATTR_TUNERSLOWMODE(d) ((d)->my_common_attr->tuner_slow_mode) +#define DRX_ATTR_TUNERSPORTNR(d) ((d)->my_common_attr->tuner_port_nr) +#define DRX_ATTR_TUNER(d) ((d)->my_tuner) +#define DRX_ATTR_I2CADDR(d) ((d)->my_i2c_dev_addr->i2c_addr) +#define DRX_ATTR_I2CDEVID(d) ((d)->my_i2c_dev_addr->i2c_dev_id) /** * \brief Actual access macro's @@ -2564,12 +2564,12 @@ Access macros #define DRX_SET_MCVERTYPE(d, x) \ do { \ - DRX_ATTR_MCRECORD(d).auxType = (x); \ + DRX_ATTR_MCRECORD(d).aux_type = (x); \ } while (0) #define DRX_GET_MCVERTYPE(d, x) \ do { \ - (x) = DRX_ATTR_MCRECORD(d).auxType; \ + (x) = DRX_ATTR_MCRECORD(d).aux_type; \ } while (0) /**************************/ @@ -2580,35 +2580,35 @@ Access macros #define DRX_SET_MCDEV(d, x) \ do { \ - DRX_ATTR_MCRECORD(d).mcDevType = (x); \ + DRX_ATTR_MCRECORD(d).mc_dev_type = (x); \ } while (0) #define DRX_GET_MCDEV(d, x) \ do { \ - (x) = DRX_ATTR_MCRECORD(d).mcDevType; \ + (x) = DRX_ATTR_MCRECORD(d).mc_dev_type; \ } while (0) /**************************/ #define DRX_SET_MCVERSION(d, x) \ do { \ - DRX_ATTR_MCRECORD(d).mcVersion = (x); \ + DRX_ATTR_MCRECORD(d).mc_version = (x); \ } while (0) #define DRX_GET_MCVERSION(d, x) \ do { \ - (x) = DRX_ATTR_MCRECORD(d).mcVersion; \ + (x) = DRX_ATTR_MCRECORD(d).mc_version; \ } while (0) /**************************/ #define DRX_SET_MCPATCH(d, x) \ do { \ - DRX_ATTR_MCRECORD(d).mcBaseVersion = (x); \ + DRX_ATTR_MCRECORD(d).mc_base_version = (x); \ } while (0) #define DRX_GET_MCPATCH(d, x) \ do { \ - (x) = DRX_ATTR_MCRECORD(d).mcBaseVersion; \ + (x) = DRX_ATTR_MCRECORD(d).mc_base_version; \ } while (0) /**************************/ @@ -2826,28 +2826,28 @@ Access macros /* Macros with device-specific handling are converted to CFG functions */ -#define DRX_ACCESSMACRO_SET(demod, value, cfgName, dataType) \ +#define DRX_ACCESSMACRO_SET(demod, value, cfg_name, data_type) \ do { \ - DRXCfg_t config; \ - dataType cfgData; \ - config.cfgType = cfgName; \ - config.cfgData = &cfgData; \ - cfgData = value; \ - DRX_Ctrl(demod, DRX_CTRL_SET_CFG, &config); \ + drx_cfg_t config; \ + data_type cfg_data; \ + config.cfg_type = cfg_name; \ + config.cfg_data = &cfg_data; \ + cfg_data = value; \ + drx_ctrl(demod, DRX_CTRL_SET_CFG, &config); \ } while (0) -#define DRX_ACCESSMACRO_GET(demod, value, cfgName, dataType, errorValue) \ +#define DRX_ACCESSMACRO_GET(demod, value, cfg_name, data_type, error_value) \ do { \ - int cfgStatus; \ - DRXCfg_t config; \ - dataType cfgData; \ - config.cfgType = cfgName; \ - config.cfgData = &cfgData; \ - cfgStatus = DRX_Ctrl(demod, DRX_CTRL_GET_CFG, &config); \ - if (cfgStatus == DRX_STS_OK) { \ - value = cfgData; \ + int cfg_status; \ + drx_cfg_t config; \ + data_type cfg_data; \ + config.cfg_type = cfg_name; \ + config.cfg_data = &cfg_data; \ + cfg_status = drx_ctrl(demod, DRX_CTRL_GET_CFG, &config); \ + if (cfg_status == DRX_STS_OK) { \ + value = cfg_data; \ } else { \ - value = (dataType)errorValue; \ + value = (data_type)error_value; \ } \ } while (0) @@ -2869,14 +2869,14 @@ Access macros DRX_ACCESSMACRO_GET((d), (x), DRX_XS_CFG_PRESET, char*, "ERROR") #define DRX_SET_AUD_BTSC_DETECT(d, x) DRX_ACCESSMACRO_SET( (d), (x), \ - DRX_XS_CFG_AUD_BTSC_DETECT, DRXAudBtscDetect_t) + DRX_XS_CFG_AUD_BTSC_DETECT, drx_aud_btsc_detect_t) #define DRX_GET_AUD_BTSC_DETECT(d, x) DRX_ACCESSMACRO_GET( (d), (x), \ - DRX_XS_CFG_AUD_BTSC_DETECT, DRXAudBtscDetect_t, DRX_UNKNOWN) + DRX_XS_CFG_AUD_BTSC_DETECT, drx_aud_btsc_detect_t, DRX_UNKNOWN) #define DRX_SET_QAM_LOCKRANGE(d, x) DRX_ACCESSMACRO_SET( (d), (x), \ - DRX_XS_CFG_QAM_LOCKRANGE, DRXQamLockRange_t) + DRX_XS_CFG_QAM_LOCKRANGE, drx_qam_lock_range_t) #define DRX_GET_QAM_LOCKRANGE(d, x) DRX_ACCESSMACRO_GET( (d), (x), \ - DRX_XS_CFG_QAM_LOCKRANGE, DRXQamLockRange_t, DRX_UNKNOWN) + DRX_XS_CFG_QAM_LOCKRANGE, drx_qam_lock_range_t, DRX_UNKNOWN) /** * \brief Macro to check if std is an ATV standard @@ -2919,16 +2919,16 @@ Access macros Exported FUNCTIONS -------------------------------------------------------------------------*/ - int DRX_Init(pDRXDemodInstance_t demods[]); + int drx_init(pdrx_demod_instance_t demods[]); - int DRX_Term(void); + int drx_term(void); - int DRX_Open(pDRXDemodInstance_t demod); + int drx_open(pdrx_demod_instance_t demod); - int DRX_Close(pDRXDemodInstance_t demod); + int drx_close(pdrx_demod_instance_t demod); - int DRX_Ctrl(pDRXDemodInstance_t demod, - u32 ctrl, void *ctrlData); + int drx_ctrl(pdrx_demod_instance_t demod, + u32 ctrl, void *ctrl_data); /*------------------------------------------------------------------------- THE END diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver_version.h b/drivers/media/dvb-frontends/drx39xyj/drx_driver_version.h index dda9398..07986bd 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver_version.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver_version.h @@ -53,8 +53,8 @@ extern "C" { #ifdef _REGISTERTABLE_ #include - extern RegisterTable_t drx_driver_version[]; - extern RegisterTableInfo_t drx_driver_version_info[]; + extern register_table_t drx_driver_version[]; + extern register_table_info_t drx_driver_version_info[]; #endif /* _REGISTERTABLE_ */ /* diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index ff99a03..3a63520 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -183,7 +183,7 @@ ENUMS DEFINES ----------------------------------------------------------------------------*/ #ifndef DRXJ_WAKE_UP_KEY -#define DRXJ_WAKE_UP_KEY (demod->myI2CDevAddr->i2cAddr) +#define DRXJ_WAKE_UP_KEY (demod->my_i2c_dev_addr->i2c_addr) #endif /** @@ -208,7 +208,7 @@ DEFINES * \def DRXJ_DAP * \brief Name of structure containing all data access protocol functions. */ -#define DRXJ_DAP drxDapDRXJFunct_g +#define DRXJ_DAP drx_dap_drxj_funct_g /** * \def HI_I2C_DELAY @@ -505,38 +505,38 @@ DEFINES #define DUMMY_READ() \ do { \ u16 dummy; \ - RR16(demod->myI2CDevAddr, SCU_RAM_VERSION_HI__A, &dummy); \ + RR16(demod->my_i2c_dev_addr, SCU_RAM_VERSION_HI__A, &dummy); \ } while (0) #define WR16(dev, addr, val) \ - CHK_ERROR(DRXJ_DAP.writeReg16Func( (dev), (addr), (val), 0) ) + CHK_ERROR(DRXJ_DAP.write_reg16func( (dev), (addr), (val), 0) ) #define RR16(dev, addr, val) \ - CHK_ERROR(DRXJ_DAP.readReg16Func( (dev), (addr), (val), 0) ) + CHK_ERROR(DRXJ_DAP.read_reg16func( (dev), (addr), (val), 0) ) #define WR32(dev, addr, val) \ - CHK_ERROR(DRXJ_DAP.writeReg32Func( (dev), (addr), (val), 0) ) + CHK_ERROR(DRXJ_DAP.write_reg32func( (dev), (addr), (val), 0) ) #define RR32(dev, addr, val) \ - CHK_ERROR(DRXJ_DAP.readReg32Func( (dev), (addr), (val), 0) ) + CHK_ERROR(DRXJ_DAP.read_reg32func( (dev), (addr), (val), 0) ) #define WRB(dev, addr, len, block) \ - CHK_ERROR(DRXJ_DAP.writeBlockFunc( (dev), (addr), (len), (block), 0) ) + CHK_ERROR(DRXJ_DAP.write_block_func( (dev), (addr), (len), (block), 0) ) #define RRB(dev, addr, len, block) \ - CHK_ERROR(DRXJ_DAP.readBlockFunc( (dev), (addr), (len), (block), 0) ) + CHK_ERROR(DRXJ_DAP.read_block_func( (dev), (addr), (len), (block), 0) ) #define BCWR16(dev, addr, val) \ - CHK_ERROR(DRXJ_DAP.writeReg16Func( (dev), (addr), (val), DRXDAP_FASI_BROADCAST) ) + CHK_ERROR(DRXJ_DAP.write_reg16func( (dev), (addr), (val), DRXDAP_FASI_BROADCAST) ) #define ARR32(dev, addr, val) \ - CHK_ERROR(DRXJ_DAP_AtomicReadReg32( (dev), (addr), (val), 0) ) + CHK_ERROR(drxj_dap_atomic_read_reg32( (dev), (addr), (val), 0) ) #define SARR16(dev, addr, val) \ - CHK_ERROR(DRXJ_DAP_SCU_AtomicReadReg16( (dev), (addr), (val), 0) ) + CHK_ERROR(drxj_dap_scu_atomic_read_reg16( (dev), (addr), (val), 0) ) #define SAWR16(dev, addr, val) \ - CHK_ERROR(DRXJ_DAP_SCU_AtomicWriteReg16( (dev), (addr), (val), 0) ) + CHK_ERROR(drxj_dap_scu_atomic_write_reg16( (dev), (addr), (val), 0) ) /** * This macro is used to create byte arrays for block writes. @@ -586,10 +586,10 @@ DEFINES /*----------------------------------------------------------------------------- STATIC VARIABLES ----------------------------------------------------------------------------*/ -int DRXJ_Open(pDRXDemodInstance_t demod); -int DRXJ_Close(pDRXDemodInstance_t demod); -int DRXJ_Ctrl(pDRXDemodInstance_t demod, - u32 ctrl, void *ctrlData); +int drxj_open(pdrx_demod_instance_t demod); +int drxj_close(pdrx_demod_instance_t demod); +int drxj_ctrl(pdrx_demod_instance_t demod, + u32 ctrl, void *ctrl_data); /*----------------------------------------------------------------------------- GLOBAL VARIABLES @@ -598,105 +598,105 @@ GLOBAL VARIABLES * DRXJ DAP structures */ -static int DRXJ_DAP_ReadBlock(struct i2c_device_addr *devAddr, - DRXaddr_t addr, +static int drxj_dap_read_block(struct i2c_device_addr *dev_addr, + dr_xaddr_t addr, u16 datasize, - u8 *data, DRXflags_t flags); + u8 *data, dr_xflags_t flags); -static int DRXJ_DAP_ReadModifyWriteReg8(struct i2c_device_addr *devAddr, - DRXaddr_t waddr, - DRXaddr_t raddr, +static int drxj_dap_read_modify_write_reg8(struct i2c_device_addr *dev_addr, + dr_xaddr_t waddr, + dr_xaddr_t raddr, u8 wdata, u8 *rdata); -static int DRXJ_DAP_ReadModifyWriteReg16(struct i2c_device_addr *devAddr, - DRXaddr_t waddr, - DRXaddr_t raddr, +static int drxj_dap_read_modify_write_reg16(struct i2c_device_addr *dev_addr, + dr_xaddr_t waddr, + dr_xaddr_t raddr, u16 wdata, u16 *rdata); -static int DRXJ_DAP_ReadModifyWriteReg32(struct i2c_device_addr *devAddr, - DRXaddr_t waddr, - DRXaddr_t raddr, +static int drxj_dap_read_modify_write_reg32(struct i2c_device_addr *dev_addr, + dr_xaddr_t waddr, + dr_xaddr_t raddr, u32 wdata, u32 *rdata); -static int DRXJ_DAP_ReadReg8(struct i2c_device_addr *devAddr, - DRXaddr_t addr, - u8 *data, DRXflags_t flags); +static int drxj_dap_read_reg8(struct i2c_device_addr *dev_addr, + dr_xaddr_t addr, + u8 *data, dr_xflags_t flags); -static int DRXJ_DAP_ReadReg16(struct i2c_device_addr *devAddr, - DRXaddr_t addr, - u16 *data, DRXflags_t flags); +static int drxj_dap_read_reg16(struct i2c_device_addr *dev_addr, + dr_xaddr_t addr, + u16 *data, dr_xflags_t flags); -static int DRXJ_DAP_ReadReg32(struct i2c_device_addr *devAddr, - DRXaddr_t addr, - u32 *data, DRXflags_t flags); +static int drxj_dap_read_reg32(struct i2c_device_addr *dev_addr, + dr_xaddr_t addr, + u32 *data, dr_xflags_t flags); -static int DRXJ_DAP_WriteBlock(struct i2c_device_addr *devAddr, - DRXaddr_t addr, +static int drxj_dap_write_block(struct i2c_device_addr *dev_addr, + dr_xaddr_t addr, u16 datasize, - u8 *data, DRXflags_t flags); + u8 *data, dr_xflags_t flags); -static int DRXJ_DAP_WriteReg8(struct i2c_device_addr *devAddr, - DRXaddr_t addr, - u8 data, DRXflags_t flags); +static int drxj_dap_write_reg8(struct i2c_device_addr *dev_addr, + dr_xaddr_t addr, + u8 data, dr_xflags_t flags); -static int DRXJ_DAP_WriteReg16(struct i2c_device_addr *devAddr, - DRXaddr_t addr, - u16 data, DRXflags_t flags); +static int drxj_dap_write_reg16(struct i2c_device_addr *dev_addr, + dr_xaddr_t addr, + u16 data, dr_xflags_t flags); -static int DRXJ_DAP_WriteReg32(struct i2c_device_addr *devAddr, - DRXaddr_t addr, - u32 data, DRXflags_t flags); +static int drxj_dap_write_reg32(struct i2c_device_addr *dev_addr, + dr_xaddr_t addr, + u32 data, dr_xflags_t flags); /* The version structure of this protocol implementation */ -char drxDapDRXJModuleName[] = "DRXJ Data Access Protocol"; -char drxDapDRXJVersionText[] = "0.0.0"; +char drx_dap_drxj_module_name[] = "DRXJ Data Access Protocol"; +char drx_dap_drxj_version_text[] = "0.0.0"; -DRXVersion_t drxDapDRXJVersion = { +drx_version_t drx_dap_drxj_version = { DRX_MODULE_DAP, /**< type identifier of the module */ - drxDapDRXJModuleName, /**< name or description of module */ + drx_dap_drxj_module_name, /**< name or description of module */ 0, /**< major version number */ 0, /**< minor version number */ 0, /**< patch version number */ - drxDapDRXJVersionText /**< version as text string */ + drx_dap_drxj_version_text /**< version as text string */ }; /* The structure containing the protocol interface */ -DRXAccessFunc_t drxDapDRXJFunct_g = { - &drxDapDRXJVersion, - DRXJ_DAP_WriteBlock, /* Supported */ - DRXJ_DAP_ReadBlock, /* Supported */ - DRXJ_DAP_WriteReg8, /* Not supported */ - DRXJ_DAP_ReadReg8, /* Not supported */ - DRXJ_DAP_ReadModifyWriteReg8, /* Not supported */ - DRXJ_DAP_WriteReg16, /* Supported */ - DRXJ_DAP_ReadReg16, /* Supported */ - DRXJ_DAP_ReadModifyWriteReg16, /* Supported */ - DRXJ_DAP_WriteReg32, /* Supported */ - DRXJ_DAP_ReadReg32, /* Supported */ - DRXJ_DAP_ReadModifyWriteReg32, /* Not supported */ +drx_access_func_t drx_dap_drxj_funct_g = { + &drx_dap_drxj_version, + drxj_dap_write_block, /* Supported */ + drxj_dap_read_block, /* Supported */ + drxj_dap_write_reg8, /* Not supported */ + drxj_dap_read_reg8, /* Not supported */ + drxj_dap_read_modify_write_reg8, /* Not supported */ + drxj_dap_write_reg16, /* Supported */ + drxj_dap_read_reg16, /* Supported */ + drxj_dap_read_modify_write_reg16, /* Supported */ + drxj_dap_write_reg32, /* Supported */ + drxj_dap_read_reg32, /* Supported */ + drxj_dap_read_modify_write_reg32, /* Not supported */ }; /** * /var DRXJ_Func_g * /brief The driver functions of the drxj */ -DRXDemodFunc_t DRXJFunctions_g = { +drx_demod_func_t drxj_functions_g = { DRXJ_TYPE_ID, - DRXJ_Open, - DRXJ_Close, - DRXJ_Ctrl + drxj_open, + drxj_close, + drxj_ctrl }; -DRXJData_t DRXJData_g = { - false, /* hasLNA : true if LNA (aka PGA) present */ - false, /* hasOOB : true if OOB supported */ - false, /* hasNTSC: true if NTSC supported */ - false, /* hasBTSC: true if BTSC supported */ - false, /* hasSMATX: true if SMA_TX pin is available */ - false, /* hasSMARX: true if SMA_RX pin is available */ - false, /* hasGPIO : true if GPIO pin is available */ - false, /* hasIRQN : true if IRQN pin is available */ +drxj_data_t drxj_data_g = { + false, /* has_lna : true if LNA (aka PGA) present */ + false, /* has_oob : true if OOB supported */ + false, /* has_ntsc: true if NTSC supported */ + false, /* has_btsc: true if BTSC supported */ + false, /* has_smatx: true if SMA_TX pin is available */ + false, /* has_smarx: true if SMA_RX pin is available */ + false, /* has_gpio : true if GPIO pin is available */ + false, /* has_irqn : true if IRQN pin is available */ 0, /* mfx A1/A2/A... */ /* tuner settings */ @@ -705,38 +705,38 @@ DRXJData_t DRXJData_g = { DRX_STANDARD_UNKNOWN, /* current standard */ DRX_CONSTELLATION_AUTO, /* constellation */ 0, /* frequency in KHz */ - DRX_BANDWIDTH_UNKNOWN, /* currBandwidth */ + DRX_BANDWIDTH_UNKNOWN, /* curr_bandwidth */ DRX_MIRROR_NO, /* mirror */ /* signal quality information: */ /* default values taken from the QAM Programming guide */ - /* fecBitsDesired should not be less than 4000000 */ - 4000000, /* fecBitsDesired */ - 5, /* fecVdPlen */ - 4, /* qamVdPrescale */ + /* fec_bits_desired should not be less than 4000000 */ + 4000000, /* fec_bits_desired */ + 5, /* fec_vd_plen */ + 4, /* qam_vd_prescale */ 0xFFFF, /* qamVDPeriod */ - 204 * 8, /* fecRsPlen annex A */ - 1, /* fecRsPrescale */ - FEC_RS_MEASUREMENT_PERIOD, /* fecRsPeriod */ - true, /* resetPktErrAcc */ - 0, /* pktErrAccStart */ + 204 * 8, /* fec_rs_plen annex A */ + 1, /* fec_rs_prescale */ + FEC_RS_MEASUREMENT_PERIOD, /* fec_rs_period */ + true, /* reset_pkt_err_acc */ + 0, /* pkt_errAccStart */ /* HI configuration */ - 0, /* HICfgTimingDiv */ - 0, /* HICfgBridgeDelay */ - 0, /* HICfgWakeUpKey */ - 0, /* HICfgCtrl */ + 0, /* hi_cfg_timing_div */ + 0, /* hi_cfg_bridge_delay */ + 0, /* hi_cfg_wake_up_key */ + 0, /* hi_cfg_ctrl */ 0, /* HICfgTimeout */ /* UIO configuartion */ - DRX_UIO_MODE_DISABLE, /* uioSmaRxMode */ - DRX_UIO_MODE_DISABLE, /* uioSmaTxMode */ + DRX_UIO_MODE_DISABLE, /* uio_sma_rx_mode */ + DRX_UIO_MODE_DISABLE, /* uio_sma_tx_mode */ DRX_UIO_MODE_DISABLE, /* uioASELMode */ - DRX_UIO_MODE_DISABLE, /* uioIRQNMode */ + DRX_UIO_MODE_DISABLE, /* uio_irqn_mode */ /* FS setting */ - 0UL, /* iqmFsRateOfs */ - false, /* posImage */ + 0UL, /* iqm_fs_rate_ofs */ + false, /* pos_image */ /* RC setting */ - 0UL, /* iqmRcRateOfs */ + 0UL, /* iqm_rc_rate_ofs */ /* AUD information */ /* false, * flagSetAUDdone */ /* false, * detectedRDS */ @@ -746,7 +746,7 @@ DRXJData_t DRXJData_g = { /* (u16) 0xFFF, * rdsLastCount */ /*#ifdef DRXJ_SPLIT_UCODE_UPLOAD - false, * flagAudMcUploaded */ + false, * flag_aud_mc_uploaded */ /*#endif * DRXJ_SPLIT_UCODE_UPLOAD */ /* ATV configuartion */ 0UL, /* flags cfg changes */ @@ -788,57 +788,57 @@ DRXJData_t DRXJData_g = { true, /* flag CVBS ouput enable */ false, /* flag SIF ouput enable */ DRXJ_SIF_ATTENUATION_0DB, /* current SIF att setting */ - { /* qamRfAgcCfg */ + { /* qam_rf_agc_cfg */ DRX_STANDARD_ITU_B, /* standard */ - DRX_AGC_CTRL_AUTO, /* ctrlMode */ - 0, /* outputLevel */ - 0, /* minOutputLevel */ - 0xFFFF, /* maxOutputLevel */ + DRX_AGC_CTRL_AUTO, /* ctrl_mode */ + 0, /* output_level */ + 0, /* min_output_level */ + 0xFFFF, /* max_output_level */ 0x0000, /* speed */ 0x0000, /* top */ 0x0000 /* c.o.c. */ }, - { /* qamIfAgcCfg */ + { /* qam_if_agc_cfg */ DRX_STANDARD_ITU_B, /* standard */ - DRX_AGC_CTRL_AUTO, /* ctrlMode */ - 0, /* outputLevel */ - 0, /* minOutputLevel */ - 0xFFFF, /* maxOutputLevel */ + DRX_AGC_CTRL_AUTO, /* ctrl_mode */ + 0, /* output_level */ + 0, /* min_output_level */ + 0xFFFF, /* max_output_level */ 0x0000, /* speed */ 0x0000, /* top (don't care) */ 0x0000 /* c.o.c. (don't care) */ }, - { /* vsbRfAgcCfg */ + { /* vsb_rf_agc_cfg */ DRX_STANDARD_8VSB, /* standard */ - DRX_AGC_CTRL_AUTO, /* ctrlMode */ - 0, /* outputLevel */ - 0, /* minOutputLevel */ - 0xFFFF, /* maxOutputLevel */ + DRX_AGC_CTRL_AUTO, /* ctrl_mode */ + 0, /* output_level */ + 0, /* min_output_level */ + 0xFFFF, /* max_output_level */ 0x0000, /* speed */ 0x0000, /* top (don't care) */ 0x0000 /* c.o.c. (don't care) */ }, - { /* vsbIfAgcCfg */ + { /* vsb_if_agc_cfg */ DRX_STANDARD_8VSB, /* standard */ - DRX_AGC_CTRL_AUTO, /* ctrlMode */ - 0, /* outputLevel */ - 0, /* minOutputLevel */ - 0xFFFF, /* maxOutputLevel */ + DRX_AGC_CTRL_AUTO, /* ctrl_mode */ + 0, /* output_level */ + 0, /* min_output_level */ + 0xFFFF, /* max_output_level */ 0x0000, /* speed */ 0x0000, /* top (don't care) */ 0x0000 /* c.o.c. (don't care) */ }, - 0, /* qamPgaCfg */ - 0, /* vsbPgaCfg */ - { /* qamPreSawCfg */ + 0, /* qam_pga_cfg */ + 0, /* vsb_pga_cfg */ + { /* qam_pre_saw_cfg */ DRX_STANDARD_ITU_B, /* standard */ 0, /* reference */ - false /* usePreSaw */ + false /* use_pre_saw */ }, - { /* vsbPreSawCfg */ + { /* vsb_pre_saw_cfg */ DRX_STANDARD_8VSB, /* standard */ 0, /* reference */ - false /* usePreSaw */ + false /* use_pre_saw */ }, /* Version information */ @@ -848,7 +848,7 @@ DRXJData_t DRXJData_g = { "01234567890" /* human readable version device specific code */ }, { - { /* DRXVersion_t for microcode */ + { /* drx_version_t for microcode */ DRX_MODULE_UNKNOWN, (char *)(NULL), 0, @@ -856,7 +856,7 @@ DRXJData_t DRXJData_g = { 0, (char *)(NULL) }, - { /* DRXVersion_t for device specific code */ + { /* drx_version_t for device specific code */ DRX_MODULE_UNKNOWN, (char *)(NULL), 0, @@ -866,17 +866,17 @@ DRXJData_t DRXJData_g = { } }, { - { /* DRXVersionList_t for microcode */ - (pDRXVersion_t) (NULL), - (pDRXVersionList_t) (NULL) + { /* drx_version_list_t for microcode */ + (pdrx_version_t) (NULL), + (p_drx_version_list_t) (NULL) }, - { /* DRXVersionList_t for device specific code */ - (pDRXVersion_t) (NULL), - (pDRXVersionList_t) (NULL) + { /* drx_version_list_t for device specific code */ + (pdrx_version_t) (NULL), + (p_drx_version_list_t) (NULL) } }, #endif - false, /* smartAntInverted */ + false, /* smart_ant_inverted */ /* Tracking filter setting for OOB */ { 12000, @@ -887,69 +887,69 @@ DRXJData_t DRXJData_g = { 3000, 2000, 0}, - false, /* oobPowerOn */ - 0, /* mpegTsStaticBitrate */ - false, /* disableTEIhandling */ - false, /* bitReverseMpegOutout */ - DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO, /* mpegOutputClockRate */ - DRXJ_MPEG_START_WIDTH_1CLKCYC, /* mpegStartWidth */ + false, /* oob_power_on */ + 0, /* mpeg_ts_static_bitrate */ + false, /* disable_te_ihandling */ + false, /* bit_reverse_mpeg_outout */ + DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO, /* mpeg_output_clock_rate */ + DRXJ_MPEG_START_WIDTH_1CLKCYC, /* mpeg_start_width */ /* Pre SAW & Agc configuration for ATV */ { DRX_STANDARD_NTSC, /* standard */ 7, /* reference */ - true /* usePreSaw */ + true /* use_pre_saw */ }, { /* ATV RF-AGC */ DRX_STANDARD_NTSC, /* standard */ - DRX_AGC_CTRL_AUTO, /* ctrlMode */ - 0, /* outputLevel */ - 0, /* minOutputLevel (d.c.) */ - 0, /* maxOutputLevel (d.c.) */ + DRX_AGC_CTRL_AUTO, /* ctrl_mode */ + 0, /* output_level */ + 0, /* min_output_level (d.c.) */ + 0, /* max_output_level (d.c.) */ 3, /* speed */ 9500, /* top */ 4000 /* cut-off current */ }, { /* ATV IF-AGC */ DRX_STANDARD_NTSC, /* standard */ - DRX_AGC_CTRL_AUTO, /* ctrlMode */ - 0, /* outputLevel */ - 0, /* minOutputLevel (d.c.) */ - 0, /* maxOutputLevel (d.c.) */ + DRX_AGC_CTRL_AUTO, /* ctrl_mode */ + 0, /* output_level */ + 0, /* min_output_level (d.c.) */ + 0, /* max_output_level (d.c.) */ 3, /* speed */ 2400, /* top */ 0 /* c.o.c. (d.c.) */ }, 140, /* ATV PGA config */ - 0, /* currSymbolRate */ + 0, /* curr_symbol_rate */ - false, /* pdrSafeMode */ - SIO_PDR_GPIO_CFG__PRE, /* pdrSafeRestoreValGpio */ - SIO_PDR_VSYNC_CFG__PRE, /* pdrSafeRestoreValVSync */ - SIO_PDR_SMA_RX_CFG__PRE, /* pdrSafeRestoreValSmaRx */ - SIO_PDR_SMA_TX_CFG__PRE, /* pdrSafeRestoreValSmaTx */ + false, /* pdr_safe_mode */ + SIO_PDR_GPIO_CFG__PRE, /* pdr_safe_restore_val_gpio */ + SIO_PDR_VSYNC_CFG__PRE, /* pdr_safe_restore_val_v_sync */ + SIO_PDR_SMA_RX_CFG__PRE, /* pdr_safe_restore_val_sma_rx */ + SIO_PDR_SMA_TX_CFG__PRE, /* pdr_safe_restore_val_sma_tx */ - 4, /* oobPreSaw */ - DRXJ_OOB_LO_POW_MINUS10DB, /* oobLoPow */ + 4, /* oob_pre_saw */ + DRXJ_OOB_LO_POW_MINUS10DB, /* oob_lo_pow */ { - false /* audData, only first member */ + false /* aud_data, only first member */ }, }; /** -* \var DRXJDefaultAddr_g +* \var drxj_default_addr_g * \brief Default I2C address and device identifier. */ -struct i2c_device_addr DRXJDefaultAddr_g = { +struct i2c_device_addr drxj_default_addr_g = { DRXJ_DEF_I2C_ADDR, /* i2c address */ DRXJ_DEF_DEMOD_DEV_ID /* device id */ }; /** -* \var DRXJDefaultCommAttr_g +* \var drxj_default_comm_attr_g * \brief Default common attributes of a drxj demodulator instance. */ -DRXCommonAttr_t DRXJDefaultCommAttr_g = { +drx_common_attr_t drxj_default_comm_attr_g = { (u8 *) NULL, /* ucode ptr */ 0, /* ucode size */ true, /* ucode verify switch */ @@ -980,7 +980,7 @@ DRXCommonAttr_t DRXJDefaultCommAttr_g = { /* Initilisations below can be ommited, they require no user input and are initialy 0, NULL or false. The compiler will initialize them to these values when ommited. */ - false, /* isOpened */ + false, /* is_opened */ /* SCAN */ NULL, /* no scan params yet */ @@ -1011,23 +1011,23 @@ DRXCommonAttr_t DRXJDefaultCommAttr_g = { }, DRX_STANDARD_UNKNOWN, /* current standard */ DRX_STANDARD_UNKNOWN, /* previous standard */ - DRX_STANDARD_UNKNOWN, /* diCacheStandard */ - false, /* useBootloader */ + DRX_STANDARD_UNKNOWN, /* di_cache_standard */ + false, /* use_bootloader */ 0UL, /* capabilities */ 0 /* mfx */ }; /** -* \var DRXJDefaultDemod_g +* \var drxj_default_demod_g * \brief Default drxj demodulator instance. */ -DRXDemodInstance_t DRXJDefaultDemod_g = { - &DRXJFunctions_g, /* demod functions */ +drx_demod_instance_t drxj_default_demod_g = { + &drxj_functions_g, /* demod functions */ &DRXJ_DAP, /* data access protocol functions */ NULL, /* tuner instance */ - &DRXJDefaultAddr_g, /* i2c address & device id */ - &DRXJDefaultCommAttr_g, /* demod common attributes */ - &DRXJData_g /* demod device specific attributes */ + &drxj_default_addr_g, /* i2c address & device id */ + &drxj_default_comm_attr_g, /* demod common attributes */ + &drxj_data_g /* demod device specific attributes */ }; /** @@ -1036,16 +1036,16 @@ DRXDemodInstance_t DRXJDefaultDemod_g = { * This structure is DRXK specific. * */ -DRXAudData_t DRXJDefaultAudData_g = { - false, /* audioIsActive */ - DRX_AUD_STANDARD_AUTO, /* audioStandard */ +drx_aud_data_t drxj_default_aud_data_g = { + false, /* audio_is_active */ + DRX_AUD_STANDARD_AUTO, /* audio_standard */ /* i2sdata */ { - false, /* outputEnable */ + false, /* output_enable */ 48000, /* frequency */ DRX_I2S_MODE_MASTER, /* mode */ - DRX_I2S_WORDLENGTH_32, /* wordLength */ + DRX_I2S_WORDLENGTH_32, /* word_length */ DRX_I2S_POLARITY_RIGHT, /* polarity */ DRX_I2S_FORMAT_WS_WITH_DATA /* format */ }, @@ -1053,15 +1053,15 @@ DRXAudData_t DRXJDefaultAudData_g = { { true, /* mute; */ 0, /* volume */ - DRX_AUD_AVC_OFF, /* avcMode */ - 0, /* avcRefLevel */ - DRX_AUD_AVC_MAX_GAIN_12DB, /* avcMaxGain */ - DRX_AUD_AVC_MAX_ATTEN_24DB, /* avcMaxAtten */ - 0, /* strengthLeft */ - 0 /* strengthRight */ + DRX_AUD_AVC_OFF, /* avc_mode */ + 0, /* avc_ref_level */ + DRX_AUD_AVC_MAX_GAIN_12DB, /* avc_max_gain */ + DRX_AUD_AVC_MAX_ATTEN_24DB, /* avc_max_atten */ + 0, /* strength_left */ + 0 /* strength_right */ }, - DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON, /* autoSound */ - /* assThresholds */ + DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON, /* auto_sound */ + /* ass_thresholds */ { 440, /* A2 */ 12, /* BTSC */ @@ -1087,33 +1087,33 @@ DRXAudData_t DRXJDefaultAudData_g = { }, /* mixer */ { - DRX_AUD_SRC_STEREO_OR_A, /* sourceI2S */ - DRX_AUD_I2S_MATRIX_STEREO, /* matrixI2S */ - DRX_AUD_FM_MATRIX_SOUND_A /* matrixFm */ + DRX_AUD_SRC_STEREO_OR_A, /* source_i2s */ + DRX_AUD_I2S_MATRIX_STEREO, /* matrix_i2s */ + DRX_AUD_FM_MATRIX_SOUND_A /* matrix_fm */ }, DRX_AUD_DEVIATION_NORMAL, /* deviation */ - DRX_AUD_AVSYNC_OFF, /* avSync */ + DRX_AUD_AVSYNC_OFF, /* av_sync */ /* prescale */ { - DRX_AUD_MAX_FM_DEVIATION, /* fmDeviation */ - DRX_AUD_MAX_NICAM_PRESCALE /* nicamGain */ + DRX_AUD_MAX_FM_DEVIATION, /* fm_deviation */ + DRX_AUD_MAX_NICAM_PRESCALE /* nicam_gain */ }, DRX_AUD_FM_DEEMPH_75US, /* deemph */ - DRX_BTSC_STEREO, /* btscDetect */ - 0, /* rdsDataCounter */ - false /* rdsDataPresent */ + DRX_BTSC_STEREO, /* btsc_detect */ + 0, /* rds_data_counter */ + false /* rds_data_present */ }; /*----------------------------------------------------------------------------- STRUCTURES ----------------------------------------------------------------------------*/ typedef struct { - u16 eqMSE; - u8 eqMode; - u8 eqCtrl; - u8 eqStat; -} DRXJEQStat_t, *pDRXJEQStat_t; + u16 eq_mse; + u8 eq_mode; + u8 eq_ctrl; + u8 eq_stat; +} drxjeq_stat_t, *pdrxjeq_stat_t; /* HI command */ typedef struct { @@ -1124,7 +1124,7 @@ typedef struct { u16 param4; u16 param5; u16 param6; -} DRXJHiCmd_t, *pDRXJHiCmd_t; +} drxj_hi_cmd_t, *pdrxj_hi_cmd_t; #ifdef DRXJ_SPLIT_UCODE_UPLOAD /*============================================================================*/ @@ -1138,7 +1138,7 @@ typedef struct { bit[1]= compression on/off bit[0]= CRC on/off */ u16 CRC; -} DRXUCodeBlockHdr_t, *pDRXUCodeBlockHdr_t; +} drxu_code_block_hdr_t, *pdrxu_code_block_hdr_t; #endif /* DRXJ_SPLIT_UCODE_UPLOAD */ /*----------------------------------------------------------------------------- @@ -1146,35 +1146,35 @@ FUNCTIONS ----------------------------------------------------------------------------*/ /* Some prototypes */ static int -HICommand(struct i2c_device_addr *devAddr, - const pDRXJHiCmd_t cmd, u16 *result); +hi_command(struct i2c_device_addr *dev_addr, + const pdrxj_hi_cmd_t cmd, u16 *result); static int -CtrlLockStatus(pDRXDemodInstance_t demod, pDRXLockStatus_t lockStat); +ctrl_lock_status(pdrx_demod_instance_t demod, pdrx_lock_status_t lock_stat); static int -CtrlPowerMode(pDRXDemodInstance_t demod, pDRXPowerMode_t mode); +ctrl_power_mode(pdrx_demod_instance_t demod, pdrx_power_mode_t mode); -static int PowerDownAud(pDRXDemodInstance_t demod); +static int power_down_aud(pdrx_demod_instance_t demod); #ifndef DRXJ_DIGITAL_ONLY -static int PowerUpAud(pDRXDemodInstance_t demod, bool setStandard); +static int power_up_aud(pdrx_demod_instance_t demod, bool set_standard); #endif static int -AUDCtrlSetStandard(pDRXDemodInstance_t demod, pDRXAudStandard_t standard); +aud_ctrl_set_standard(pdrx_demod_instance_t demod, pdrx_aud_standard_t standard); static int -CtrlSetCfgPreSaw(pDRXDemodInstance_t demod, pDRXJCfgPreSaw_t preSaw); +ctrl_set_cfg_pre_saw(pdrx_demod_instance_t demod, p_drxj_cfg_pre_saw_t pre_saw); static int -CtrlSetCfgAfeGain(pDRXDemodInstance_t demod, pDRXJCfgAfeGain_t afeGain); +ctrl_set_cfg_afe_gain(pdrx_demod_instance_t demod, p_drxj_cfg_afe_gain_t afe_gain); #ifdef DRXJ_SPLIT_UCODE_UPLOAD static int -CtrlUCodeUpload(pDRXDemodInstance_t demod, - pDRXUCodeInfo_t mcInfo, - DRXUCodeAction_t action, bool audioMCUpload); +ctrl_u_codeUpload(pdrx_demod_instance_t demod, + p_drxu_code_info_t mc_info, + drxu_code_action_t action, bool audio_mc_upload); #endif /* DRXJ_SPLIT_UCODE_UPLOAD */ /*============================================================================*/ @@ -1184,7 +1184,7 @@ CtrlUCodeUpload(pDRXDemodInstance_t demod, /*============================================================================*/ /** -* \fn void Mult32(u32 a, u32 b, u32 *h, u32 *l) +* \fn void mult32(u32 a, u32 b, u32 *h, u32 *l) * \brief 32bitsx32bits signed multiplication * \param a 32 bits multiplicant, typecast from signed to unisgned * \param b 32 bits multiplier, typecast from signed to unisgned @@ -1226,7 +1226,7 @@ CtrlUCodeUpload(pDRXDemodInstance_t demod, #define DRX_IS_BOOTH_NEGATIVE(__a) (((__a) & (1 << (sizeof(u32) * 8 - 1))) != 0) -static void Mult32(u32 a, u32 b, u32 *h, u32 *l) +static void mult32(u32 a, u32 b, u32 *h, u32 *l) { unsigned int i; *h = *l = 0; @@ -1276,7 +1276,7 @@ static void Mult32(u32 a, u32 b, u32 *h, u32 *l) /*============================================================================*/ /* -* \fn u32 Frac28(u32 N, u32 D) +* \fn u32 frac28(u32 N, u32 D) * \brief Compute: (1<<28)*N/D * \param N 32 bits * \param D 32 bits @@ -1284,7 +1284,7 @@ static void Mult32(u32 a, u32 b, u32 *h, u32 *l) * This function is used to avoid floating-point calculations as they may * not be present on the target platform. -* Frac28 performs an unsigned 28/28 bits division to 32-bit fixed point +* frac28 performs an unsigned 28/28 bits division to 32-bit fixed point * fraction used for setting the Frequency Shifter registers. * N and D can hold numbers up to width: 28-bits. * The 4 bits integer part and the 28 bits fractional part are calculated. @@ -1295,7 +1295,7 @@ static void Mult32(u32 a, u32 b, u32 *h, u32 *l) * D: 0...(1<<28)-1 * Q: 0...(1<<32)-1 */ -static u32 Frac28(u32 N, u32 D) +static u32 frac28(u32 N, u32 D) { int i = 0; u32 Q1 = 0; @@ -1318,7 +1318,7 @@ static u32 Frac28(u32 N, u32 D) } /** -* \fn u32 Log10Times100( u32 x) +* \fn u32 log1_times100( u32 x) * \brief Compute: 100*log10(x) * \param x 32 bits * \return 100*log10(x) @@ -1333,10 +1333,10 @@ static u32 Frac28(u32 N, u32 D) * where y = 2^k and 1<= (x/y) < 2 */ -static u32 Log10Times100(u32 x) +static u32 log1_times100(u32 x) { static const u8 scale = 15; - static const u8 indexWidth = 5; + static const u8 index_width = 5; /* log2lut[n] = (1<> (scale - indexWidth)); + i = (u8) (x >> (scale - index_width)); /* compute delta (x-a) */ - d = x & ((((u32) 1) << (scale - indexWidth)) - 1); + d = x & ((((u32) 1) << (scale - index_width)) - 1); /* compute log, multiplication ( d* (.. )) must be within range ! */ y += log2lut[i] + - ((d * (log2lut[i + 1] - log2lut[i])) >> (scale - indexWidth)); + ((d * (log2lut[i + 1] - log2lut[i])) >> (scale - index_width)); /* Conver to log10() */ y /= 108853; /* (log2(10) << scale) */ r = (y >> 1); @@ -1430,7 +1430,7 @@ static u32 Log10Times100(u32 x) } /** -* \fn u32 FracTimes1e6( u16 N, u32 D) +* \fn u32 frac_times1e6( u16 N, u32 D) * \brief Compute: (N/D) * 1000000. * \param N nominator 16-bits. * \param D denominator 32-bits. @@ -1439,7 +1439,7 @@ static u32 Log10Times100(u32 x) * * No check on D=0! */ -static u32 FracTimes1e6(u32 N, u32 D) +static u32 frac_times1e6(u32 N, u32 D) { u32 remainder = 0; u32 frac = 0; @@ -1467,41 +1467,41 @@ static u32 FracTimes1e6(u32 N, u32 D) /*============================================================================*/ /** -* \brief Compute: 100 * 10^( GdB / 200 ). -* \param u32 GdB Gain in 0.1dB +* \brief Compute: 100 * 10^( gd_b / 200 ). +* \param u32 gd_b Gain in 0.1dB * \return u32 Gainfactor in 0.01 resolution * */ -static u32 dB2LinTimes100(u32 GdB) +static u32 d_b2lin_times100(u32 gd_b) { u32 result = 0; - u32 nr6dBSteps = 0; + u32 nr6d_b_steps = 0; u32 remainder = 0; - u32 remainderFac = 0; + u32 remainder_fac = 0; /* start with factors 2 (6.02dB) */ - nr6dBSteps = GdB * 1000UL / 60206UL; - if (nr6dBSteps > 17) { + nr6d_b_steps = gd_b * 1000UL / 60206UL; + if (nr6d_b_steps > 17) { /* Result max overflow if > log2( maxu32 / 2e4 ) ~= 17.7 */ return MAX_U32; } - result = (1 << nr6dBSteps); + result = (1 << nr6d_b_steps); /* calculate remaining factor, - poly approximation of 10^(GdB/200): + poly approximation of 10^(gd_b/200): y = 1E-04x2 + 0.0106x + 1.0026 max deviation < 0.005 for range x = [0 ... 60] */ - remainder = ((GdB * 1000UL) % 60206UL) / 1000UL; + remainder = ((gd_b * 1000UL) % 60206UL) / 1000UL; /* using 1e-4 for poly calculation */ - remainderFac = 1 * remainder * remainder; - remainderFac += 106 * remainder; - remainderFac += 10026; + remainder_fac = 1 * remainder * remainder; + remainder_fac += 106 * remainder; + remainder_fac += 10026; /* multiply by remaining factor */ - result *= remainderFac; + result *= remainder_fac; /* conversion from 1e-4 to 1e-2 */ return ((result + 50) / 100); @@ -1512,7 +1512,7 @@ static u32 dB2LinTimes100(u32 GdB) #define FRAC_CEIL 1 #define FRAC_ROUND 2 /** -* \fn u32 Frac( u32 N, u32 D, u16 RC ) +* \fn u32 frac( u32 N, u32 D, u16 RC ) * \brief Compute: N/D. * \param N nominator 32-bits. * \param D denominator 32-bits. @@ -1522,11 +1522,11 @@ static u32 dB2LinTimes100(u32 GdB) * * If D=0 returns 0 */ -static u32 Frac(u32 N, u32 D, u16 RC) +static u32 frac(u32 N, u32 D, u16 RC) { u32 remainder = 0; u32 frac = 0; - u16 bitCnt = 32; + u16 bit_cnt = 32; if (D == 0) { frac = 0; @@ -1541,7 +1541,7 @@ static u32 Frac(u32 N, u32 D, u16 RC) } else { remainder = 0; frac = N; - while (bitCnt-- > 0) { + while (bit_cnt-- > 0) { remainder <<= 1; remainder |= ((frac & 0x80000000) >> 31); frac <<= 1; @@ -1573,11 +1573,11 @@ static u32 Frac(u32 N, u32 D, u16 RC) /*============================================================================*/ /** -* \fn u16 UCodeRead16( u8 *addr) +* \fn u16 u_code_read16( u8 *addr) * \brief Read a 16 bits word, expect big endian data. * \return u16 The data read. */ -static u16 UCodeRead16(u8 *addr) +static u16 u_code_read16(u8 *addr) { /* Works fo any host processor */ @@ -1593,11 +1593,11 @@ static u16 UCodeRead16(u8 *addr) /*============================================================================*/ /** -* \fn u32 UCodeRead32( u8 *addr) +* \fn u32 u_code_read32( u8 *addr) * \brief Read a 32 bits word, expect big endian data. * \return u32 The data read. */ -static u32 UCodeRead32(u8 *addr) +static u32 u_code_read32(u8 *addr) { /* Works fo any host processor */ @@ -1617,31 +1617,31 @@ static u32 UCodeRead32(u8 *addr) /*============================================================================*/ /** -* \fn u16 UCodeComputeCRC (u8 *blockData, u16 nrWords) +* \fn u16 u_code_compute_crc (u8 *block_data, u16 nr_words) * \brief Compute CRC of block of microcode data. -* \param blockData Pointer to microcode data. -* \param nrWords Size of microcode block (number of 16 bits words). +* \param block_data Pointer to microcode data. +* \param nr_words Size of microcode block (number of 16 bits words). * \return u16 The computed CRC residu. */ -static u16 UCodeComputeCRC(u8 *blockData, u16 nrWords) +static u16 u_code_compute_crc(u8 *block_data, u16 nr_words) { u16 i = 0; u16 j = 0; - u32 CRCWord = 0; + u32 crc_word = 0; u32 carry = 0; - while (i < nrWords) { - CRCWord |= (u32) UCodeRead16(blockData); + while (i < nr_words) { + crc_word |= (u32) u_code_read16(block_data); for (j = 0; j < 16; j++) { - CRCWord <<= 1; + crc_word <<= 1; if (carry != 0) - CRCWord ^= 0x80050000UL; - carry = CRCWord & 0x80000000UL; + crc_word ^= 0x80050000UL; + carry = crc_word & 0x80000000UL; } i++; - blockData += (sizeof(u16)); + block_data += (sizeof(u16)); } - return ((u16) (CRCWord >> 16)); + return ((u16) (crc_word >> 16)); } #endif /* DRXJ_SPLIT_UCODE_UPLOAD */ @@ -1650,7 +1650,7 @@ static u16 UCodeComputeCRC(u8 *blockData, u16 nrWords) * and rounded. For calc used formula: 16*10^(prescaleGain[dB]/20). * */ -static const u16 NicamPrescTableVal[43] = +static const u16 nicam_presc_table_val[43] = { 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 7, 8, 9, 10, 11, 13, 14, 16, 18, 20, 23, 25, 28, 32, 36, 40, 45, @@ -1688,7 +1688,7 @@ static const u16 NicamPrescTableVal[43] = /*============================================================================*/ /** -* \fn bool IsHandledByAudTrIf( DRXaddr_t addr ) +* \fn bool is_handled_by_aud_tr_if( dr_xaddr_t addr ) * \brief Check if this address is handled by the audio token ring interface. * \param addr * \return bool @@ -1697,7 +1697,7 @@ static const u16 NicamPrescTableVal[43] = * */ static -bool IsHandledByAudTrIf(DRXaddr_t addr) +bool is_handled_by_aud_tr_if(dr_xaddr_t addr) { bool retval = false; @@ -1712,23 +1712,23 @@ bool IsHandledByAudTrIf(DRXaddr_t addr) /*============================================================================*/ -static int DRXJ_DAP_ReadBlock(struct i2c_device_addr *devAddr, - DRXaddr_t addr, +static int drxj_dap_read_block(struct i2c_device_addr *dev_addr, + dr_xaddr_t addr, u16 datasize, - u8 *data, DRXflags_t flags) + u8 *data, dr_xflags_t flags) { - return drxDapFASIFunct_g.readBlockFunc(devAddr, + return drx_dap_fasi_funct_g.read_block_func(dev_addr, addr, datasize, data, flags); } /*============================================================================*/ -static int DRXJ_DAP_ReadModifyWriteReg8(struct i2c_device_addr *devAddr, - DRXaddr_t waddr, - DRXaddr_t raddr, +static int drxj_dap_read_modify_write_reg8(struct i2c_device_addr *dev_addr, + dr_xaddr_t waddr, + dr_xaddr_t raddr, u8 wdata, u8 *rdata) { - return drxDapFASIFunct_g.readModifyWriteReg8Func(devAddr, + return drx_dap_fasi_funct_g.read_modify_write_reg8func(dev_addr, waddr, raddr, wdata, rdata); } @@ -1736,9 +1736,9 @@ static int DRXJ_DAP_ReadModifyWriteReg8(struct i2c_device_addr *devAddr, /*============================================================================*/ /** -* \fn int DRXJ_DAP_RMWriteReg16Short +* \fn int drxj_dap_rm_write_reg16short * \brief Read modify write 16 bits audio register using short format only. -* \param devAddr +* \param dev_addr * \param waddr Address to write to * \param raddr Address to read from (usually SIO_HI_RA_RAM_S0_RMWBUF__A) * \param wdata Data to write @@ -1754,11 +1754,11 @@ static int DRXJ_DAP_ReadModifyWriteReg8(struct i2c_device_addr *devAddr, */ /* TODO correct define should be #if ( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 ) - See comments DRXJ_DAP_ReadModifyWriteReg16 */ + See comments drxj_dap_read_modify_write_reg16 */ #if (DRXDAPFASI_LONG_ADDR_ALLOWED == 0) -static int DRXJ_DAP_RMWriteReg16Short(struct i2c_device_addr *devAddr, - DRXaddr_t waddr, - DRXaddr_t raddr, +static int drxj_dap_rm_write_reg16short(struct i2c_device_addr *dev_addr, + dr_xaddr_t waddr, + dr_xaddr_t raddr, u16 wdata, u16 *rdata) { int rc; @@ -1768,23 +1768,23 @@ static int DRXJ_DAP_RMWriteReg16Short(struct i2c_device_addr *devAddr, } /* Set RMW flag */ - rc = drxDapFASIFunct_g.writeReg16Func(devAddr, + rc = drx_dap_fasi_funct_g.write_reg16func(dev_addr, SIO_HI_RA_RAM_S0_FLG_ACC__A, SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__M, 0x0000); if (rc == DRX_STS_OK) { /* Write new data: triggers RMW */ - rc = drxDapFASIFunct_g.writeReg16Func(devAddr, waddr, wdata, + rc = drx_dap_fasi_funct_g.write_reg16func(dev_addr, waddr, wdata, 0x0000); } if (rc == DRX_STS_OK) { /* Read old data */ - rc = drxDapFASIFunct_g.readReg16Func(devAddr, raddr, rdata, + rc = drx_dap_fasi_funct_g.read_reg16func(dev_addr, raddr, rdata, 0x0000); } if (rc == DRX_STS_OK) { /* Reset RMW flag */ - rc = drxDapFASIFunct_g.writeReg16Func(devAddr, + rc = drx_dap_fasi_funct_g.write_reg16func(dev_addr, SIO_HI_RA_RAM_S0_FLG_ACC__A, 0, 0x0000); } @@ -1795,50 +1795,50 @@ static int DRXJ_DAP_RMWriteReg16Short(struct i2c_device_addr *devAddr, /*============================================================================*/ -static int DRXJ_DAP_ReadModifyWriteReg16(struct i2c_device_addr *devAddr, - DRXaddr_t waddr, - DRXaddr_t raddr, +static int drxj_dap_read_modify_write_reg16(struct i2c_device_addr *dev_addr, + dr_xaddr_t waddr, + dr_xaddr_t raddr, u16 wdata, u16 *rdata) { /* TODO: correct short/long addressing format decision, now long format has higher prio then short because short also needs virt bnks (not impl yet) for certain audio registers */ #if (DRXDAPFASI_LONG_ADDR_ALLOWED == 1) - return drxDapFASIFunct_g.readModifyWriteReg16Func(devAddr, + return drx_dap_fasi_funct_g.read_modify_write_reg16func(dev_addr, waddr, raddr, wdata, rdata); #else - return DRXJ_DAP_RMWriteReg16Short(devAddr, waddr, raddr, wdata, rdata); + return drxj_dap_rm_write_reg16short(dev_addr, waddr, raddr, wdata, rdata); #endif } /*============================================================================*/ -static int DRXJ_DAP_ReadModifyWriteReg32(struct i2c_device_addr *devAddr, - DRXaddr_t waddr, - DRXaddr_t raddr, +static int drxj_dap_read_modify_write_reg32(struct i2c_device_addr *dev_addr, + dr_xaddr_t waddr, + dr_xaddr_t raddr, u32 wdata, u32 *rdata) { - return drxDapFASIFunct_g.readModifyWriteReg32Func(devAddr, + return drx_dap_fasi_funct_g.read_modify_write_reg32func(dev_addr, waddr, raddr, wdata, rdata); } /*============================================================================*/ -static int DRXJ_DAP_ReadReg8(struct i2c_device_addr *devAddr, - DRXaddr_t addr, - u8 *data, DRXflags_t flags) +static int drxj_dap_read_reg8(struct i2c_device_addr *dev_addr, + dr_xaddr_t addr, + u8 *data, dr_xflags_t flags) { - return drxDapFASIFunct_g.readReg8Func(devAddr, addr, data, flags); + return drx_dap_fasi_funct_g.read_reg8func(dev_addr, addr, data, flags); } /*============================================================================*/ /** -* \fn int DRXJ_DAP_ReadAudReg16 +* \fn int drxj_dap_read_aud_reg16 * \brief Read 16 bits audio register -* \param devAddr +* \param dev_addr * \param addr * \param data * \return int @@ -1848,66 +1848,66 @@ static int DRXJ_DAP_ReadReg8(struct i2c_device_addr *devAddr, * 16 bits register read access via audio token ring interface. * */ -static int DRXJ_DAP_ReadAudReg16(struct i2c_device_addr *devAddr, - DRXaddr_t addr, u16 *data) +static int drxj_dap_read_aud_reg16(struct i2c_device_addr *dev_addr, + dr_xaddr_t addr, u16 *data) { - u32 startTimer = 0; - u32 currentTimer = 0; - u32 deltaTimer = 0; - u16 trStatus = 0; + u32 start_timer = 0; + u32 current_timer = 0; + u32 delta_timer = 0; + u16 tr_status = 0; int stat = DRX_STS_ERROR; /* No read possible for bank 3, return with error */ if (DRXDAP_FASI_ADDR2BANK(addr) == 3) { stat = DRX_STS_INVALID_ARG; } else { - const DRXaddr_t writeBit = ((DRXaddr_t) 1) << 16; + const dr_xaddr_t write_bit = ((dr_xaddr_t) 1) << 16; /* Force reset write bit */ - addr &= (~writeBit); + addr &= (~write_bit); /* Set up read */ - startTimer = DRXBSP_HST_Clock(); + start_timer = drxbsp_hst_clock(); do { /* RMW to aud TR IF until request is granted or timeout */ - stat = DRXJ_DAP_ReadModifyWriteReg16(devAddr, + stat = drxj_dap_read_modify_write_reg16(dev_addr, addr, SIO_HI_RA_RAM_S0_RMWBUF__A, - 0x0000, &trStatus); + 0x0000, &tr_status); if (stat != DRX_STS_OK) { break; }; - currentTimer = DRXBSP_HST_Clock(); - deltaTimer = currentTimer - startTimer; - if (deltaTimer > DRXJ_DAP_AUDTRIF_TIMEOUT) { + current_timer = drxbsp_hst_clock(); + delta_timer = current_timer - start_timer; + if (delta_timer > DRXJ_DAP_AUDTRIF_TIMEOUT) { stat = DRX_STS_ERROR; break; }; - } while (((trStatus & AUD_TOP_TR_CTR_FIFO_LOCK__M) == + } while (((tr_status & AUD_TOP_TR_CTR_FIFO_LOCK__M) == AUD_TOP_TR_CTR_FIFO_LOCK_LOCKED) || - ((trStatus & AUD_TOP_TR_CTR_FIFO_FULL__M) == + ((tr_status & AUD_TOP_TR_CTR_FIFO_FULL__M) == AUD_TOP_TR_CTR_FIFO_FULL_FULL)); } /* if ( DRXDAP_FASI_ADDR2BANK(addr)!=3 ) */ /* Wait for read ready status or timeout */ if (stat == DRX_STS_OK) { - startTimer = DRXBSP_HST_Clock(); + start_timer = drxbsp_hst_clock(); - while ((trStatus & AUD_TOP_TR_CTR_FIFO_RD_RDY__M) != + while ((tr_status & AUD_TOP_TR_CTR_FIFO_RD_RDY__M) != AUD_TOP_TR_CTR_FIFO_RD_RDY_READY) { - stat = DRXJ_DAP_ReadReg16(devAddr, + stat = drxj_dap_read_reg16(dev_addr, AUD_TOP_TR_CTR__A, - &trStatus, 0x0000); + &tr_status, 0x0000); if (stat != DRX_STS_OK) { break; }; - currentTimer = DRXBSP_HST_Clock(); - deltaTimer = currentTimer - startTimer; - if (deltaTimer > DRXJ_DAP_AUDTRIF_TIMEOUT) { + current_timer = drxbsp_hst_clock(); + delta_timer = current_timer - start_timer; + if (delta_timer > DRXJ_DAP_AUDTRIF_TIMEOUT) { stat = DRX_STS_ERROR; break; }; @@ -1917,7 +1917,7 @@ static int DRXJ_DAP_ReadAudReg16(struct i2c_device_addr *devAddr, /* if { stat == DRX_STS_OK ) */ /* Read value */ if (stat == DRX_STS_OK) { - stat = DRXJ_DAP_ReadModifyWriteReg16(devAddr, + stat = drxj_dap_read_modify_write_reg16(dev_addr, AUD_TOP_TR_RD_REG__A, SIO_HI_RA_RAM_S0_RMWBUF__A, 0x0000, data); @@ -1928,21 +1928,21 @@ static int DRXJ_DAP_ReadAudReg16(struct i2c_device_addr *devAddr, /*============================================================================*/ -static int DRXJ_DAP_ReadReg16(struct i2c_device_addr *devAddr, - DRXaddr_t addr, - u16 *data, DRXflags_t flags) +static int drxj_dap_read_reg16(struct i2c_device_addr *dev_addr, + dr_xaddr_t addr, + u16 *data, dr_xflags_t flags) { int stat = DRX_STS_ERROR; /* Check param */ - if ((devAddr == NULL) || (data == NULL)) { + if ((dev_addr == NULL) || (data == NULL)) { return DRX_STS_INVALID_ARG; } - if (IsHandledByAudTrIf(addr)) { - stat = DRXJ_DAP_ReadAudReg16(devAddr, addr, data); + if (is_handled_by_aud_tr_if(addr)) { + stat = drxj_dap_read_aud_reg16(dev_addr, addr, data); } else { - stat = drxDapFASIFunct_g.readReg16Func(devAddr, + stat = drx_dap_fasi_funct_g.read_reg16func(dev_addr, addr, data, flags); } @@ -1951,39 +1951,39 @@ static int DRXJ_DAP_ReadReg16(struct i2c_device_addr *devAddr, /*============================================================================*/ -static int DRXJ_DAP_ReadReg32(struct i2c_device_addr *devAddr, - DRXaddr_t addr, - u32 *data, DRXflags_t flags) +static int drxj_dap_read_reg32(struct i2c_device_addr *dev_addr, + dr_xaddr_t addr, + u32 *data, dr_xflags_t flags) { - return drxDapFASIFunct_g.readReg32Func(devAddr, addr, data, flags); + return drx_dap_fasi_funct_g.read_reg32func(dev_addr, addr, data, flags); } /*============================================================================*/ -static int DRXJ_DAP_WriteBlock(struct i2c_device_addr *devAddr, - DRXaddr_t addr, +static int drxj_dap_write_block(struct i2c_device_addr *dev_addr, + dr_xaddr_t addr, u16 datasize, - u8 *data, DRXflags_t flags) + u8 *data, dr_xflags_t flags) { - return drxDapFASIFunct_g.writeBlockFunc(devAddr, + return drx_dap_fasi_funct_g.write_block_func(dev_addr, addr, datasize, data, flags); } /*============================================================================*/ -static int DRXJ_DAP_WriteReg8(struct i2c_device_addr *devAddr, - DRXaddr_t addr, - u8 data, DRXflags_t flags) +static int drxj_dap_write_reg8(struct i2c_device_addr *dev_addr, + dr_xaddr_t addr, + u8 data, dr_xflags_t flags) { - return drxDapFASIFunct_g.writeReg8Func(devAddr, addr, data, flags); + return drx_dap_fasi_funct_g.write_reg8func(dev_addr, addr, data, flags); } /*============================================================================*/ /** -* \fn int DRXJ_DAP_WriteAudReg16 +* \fn int drxj_dap_write_aud_reg16 * \brief Write 16 bits audio register -* \param devAddr +* \param dev_addr * \param addr * \param data * \return int @@ -1993,8 +1993,8 @@ static int DRXJ_DAP_WriteReg8(struct i2c_device_addr *devAddr, * 16 bits register write access via audio token ring interface. * */ -static int DRXJ_DAP_WriteAudReg16(struct i2c_device_addr *devAddr, - DRXaddr_t addr, u16 data) +static int drxj_dap_write_aud_reg16(struct i2c_device_addr *dev_addr, + dr_xaddr_t addr, u16 data) { int stat = DRX_STS_ERROR; @@ -2002,35 +2002,35 @@ static int DRXJ_DAP_WriteAudReg16(struct i2c_device_addr *devAddr, if (DRXDAP_FASI_ADDR2BANK(addr) == 2) { stat = DRX_STS_INVALID_ARG; } else { - u32 startTimer = 0; - u32 currentTimer = 0; - u32 deltaTimer = 0; - u16 trStatus = 0; - const DRXaddr_t writeBit = ((DRXaddr_t) 1) << 16; + u32 start_timer = 0; + u32 current_timer = 0; + u32 delta_timer = 0; + u16 tr_status = 0; + const dr_xaddr_t write_bit = ((dr_xaddr_t) 1) << 16; /* Force write bit */ - addr |= writeBit; - startTimer = DRXBSP_HST_Clock(); + addr |= write_bit; + start_timer = drxbsp_hst_clock(); do { /* RMW to aud TR IF until request is granted or timeout */ - stat = DRXJ_DAP_ReadModifyWriteReg16(devAddr, + stat = drxj_dap_read_modify_write_reg16(dev_addr, addr, SIO_HI_RA_RAM_S0_RMWBUF__A, - data, &trStatus); + data, &tr_status); if (stat != DRX_STS_OK) { break; }; - currentTimer = DRXBSP_HST_Clock(); - deltaTimer = currentTimer - startTimer; - if (deltaTimer > DRXJ_DAP_AUDTRIF_TIMEOUT) { + current_timer = drxbsp_hst_clock(); + delta_timer = current_timer - start_timer; + if (delta_timer > DRXJ_DAP_AUDTRIF_TIMEOUT) { stat = DRX_STS_ERROR; break; }; - } while (((trStatus & AUD_TOP_TR_CTR_FIFO_LOCK__M) == + } while (((tr_status & AUD_TOP_TR_CTR_FIFO_LOCK__M) == AUD_TOP_TR_CTR_FIFO_LOCK_LOCKED) || - ((trStatus & AUD_TOP_TR_CTR_FIFO_FULL__M) == + ((tr_status & AUD_TOP_TR_CTR_FIFO_FULL__M) == AUD_TOP_TR_CTR_FIFO_FULL_FULL)); } /* if ( DRXDAP_FASI_ADDR2BANK(addr)!=2 ) */ @@ -2040,21 +2040,21 @@ static int DRXJ_DAP_WriteAudReg16(struct i2c_device_addr *devAddr, /*============================================================================*/ -static int DRXJ_DAP_WriteReg16(struct i2c_device_addr *devAddr, - DRXaddr_t addr, - u16 data, DRXflags_t flags) +static int drxj_dap_write_reg16(struct i2c_device_addr *dev_addr, + dr_xaddr_t addr, + u16 data, dr_xflags_t flags) { int stat = DRX_STS_ERROR; /* Check param */ - if (devAddr == NULL) { + if (dev_addr == NULL) { return DRX_STS_INVALID_ARG; } - if (IsHandledByAudTrIf(addr)) { - stat = DRXJ_DAP_WriteAudReg16(devAddr, addr, data); + if (is_handled_by_aud_tr_if(addr)) { + stat = drxj_dap_write_aud_reg16(dev_addr, addr, data); } else { - stat = drxDapFASIFunct_g.writeReg16Func(devAddr, + stat = drx_dap_fasi_funct_g.write_reg16func(dev_addr, addr, data, flags); } @@ -2063,11 +2063,11 @@ static int DRXJ_DAP_WriteReg16(struct i2c_device_addr *devAddr, /*============================================================================*/ -static int DRXJ_DAP_WriteReg32(struct i2c_device_addr *devAddr, - DRXaddr_t addr, - u32 data, DRXflags_t flags) +static int drxj_dap_write_reg32(struct i2c_device_addr *dev_addr, + dr_xaddr_t addr, + u32 data, dr_xflags_t flags) { - return drxDapFASIFunct_g.writeReg32Func(devAddr, addr, data, flags); + return drx_dap_fasi_funct_g.write_reg32func(dev_addr, addr, data, flags); } /*============================================================================*/ @@ -2082,9 +2082,9 @@ static int DRXJ_DAP_WriteReg32(struct i2c_device_addr *devAddr, #define DRXJ_HI_ATOMIC_WRITE SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE /** -* \fn int DRXJ_DAP_AtomicReadWriteBlock() +* \fn int drxj_dap_atomic_read_write_block() * \brief Basic access routine for atomic read or write access -* \param devAddr pointer to i2c dev address +* \param dev_addr pointer to i2c dev address * \param addr destination/source address * \param datasize size of data buffer in bytes * \param data pointer to data buffer @@ -2094,12 +2094,12 @@ static int DRXJ_DAP_WriteReg32(struct i2c_device_addr *devAddr, * */ static -int DRXJ_DAP_AtomicReadWriteBlock(struct i2c_device_addr *devAddr, - DRXaddr_t addr, +int drxj_dap_atomic_read_write_block(struct i2c_device_addr *dev_addr, + dr_xaddr_t addr, u16 datasize, - u8 *data, bool readFlag) + u8 *data, bool read_flag) { - DRXJHiCmd_t hiCmd; + drxj_hi_cmd_t hi_cmd; u16 word; u16 dummy = 0; @@ -2107,46 +2107,46 @@ int DRXJ_DAP_AtomicReadWriteBlock(struct i2c_device_addr *devAddr, /* Parameter check */ if ((data == NULL) || - (devAddr == NULL) || ((datasize % 2) != 0) || ((datasize / 2) > 8) + (dev_addr == NULL) || ((datasize % 2) != 0) || ((datasize / 2) > 8) ) { return (DRX_STS_INVALID_ARG); } /* Set up HI parameters to read or write n bytes */ - hiCmd.cmd = SIO_HI_RA_RAM_CMD_ATOMIC_COPY; - hiCmd.param1 = + hi_cmd.cmd = SIO_HI_RA_RAM_CMD_ATOMIC_COPY; + hi_cmd.param1 = (u16) ((DRXDAP_FASI_ADDR2BLOCK(DRXJ_HI_ATOMIC_BUF_START) << 6) + DRXDAP_FASI_ADDR2BANK(DRXJ_HI_ATOMIC_BUF_START)); - hiCmd.param2 = + hi_cmd.param2 = (u16) DRXDAP_FASI_ADDR2OFFSET(DRXJ_HI_ATOMIC_BUF_START); - hiCmd.param3 = (u16) ((datasize / 2) - 1); - if (readFlag == false) { - hiCmd.param3 |= DRXJ_HI_ATOMIC_WRITE; + hi_cmd.param3 = (u16) ((datasize / 2) - 1); + if (read_flag == false) { + hi_cmd.param3 |= DRXJ_HI_ATOMIC_WRITE; } else { - hiCmd.param3 |= DRXJ_HI_ATOMIC_READ; + hi_cmd.param3 |= DRXJ_HI_ATOMIC_READ; } - hiCmd.param4 = (u16) ((DRXDAP_FASI_ADDR2BLOCK(addr) << 6) + + hi_cmd.param4 = (u16) ((DRXDAP_FASI_ADDR2BLOCK(addr) << 6) + DRXDAP_FASI_ADDR2BANK(addr)); - hiCmd.param5 = (u16) DRXDAP_FASI_ADDR2OFFSET(addr); + hi_cmd.param5 = (u16) DRXDAP_FASI_ADDR2OFFSET(addr); - if (readFlag == false) { + if (read_flag == false) { /* write data to buffer */ for (i = 0; i < (datasize / 2); i++) { word = ((u16) data[2 * i]); word += (((u16) data[(2 * i) + 1]) << 8); - DRXJ_DAP_WriteReg16(devAddr, + drxj_dap_write_reg16(dev_addr, (DRXJ_HI_ATOMIC_BUF_START + i), word, 0); } } - CHK_ERROR(HICommand(devAddr, &hiCmd, &dummy)); + CHK_ERROR(hi_command(dev_addr, &hi_cmd, &dummy)); - if (readFlag == true) { + if (read_flag == true) { /* read data from buffer */ for (i = 0; i < (datasize / 2); i++) { - DRXJ_DAP_ReadReg16(devAddr, + drxj_dap_read_reg16(dev_addr, (DRXJ_HI_ATOMIC_BUF_START + i), &word, 0); data[2 * i] = (u8) (word & 0xFF); @@ -2164,13 +2164,13 @@ rw_error: /*============================================================================*/ /** -* \fn int DRXJ_DAP_AtomicReadReg32() +* \fn int drxj_dap_atomic_read_reg32() * \brief Atomic read of 32 bits words */ static -int DRXJ_DAP_AtomicReadReg32(struct i2c_device_addr *devAddr, - DRXaddr_t addr, - u32 *data, DRXflags_t flags) +int drxj_dap_atomic_read_reg32(struct i2c_device_addr *dev_addr, + dr_xaddr_t addr, + u32 *data, dr_xflags_t flags) { u8 buf[sizeof(*data)]; int rc = DRX_STS_ERROR; @@ -2180,7 +2180,7 @@ int DRXJ_DAP_AtomicReadReg32(struct i2c_device_addr *devAddr, return DRX_STS_INVALID_ARG; } - rc = DRXJ_DAP_AtomicReadWriteBlock(devAddr, addr, + rc = drxj_dap_atomic_read_write_block(dev_addr, addr, sizeof(*data), buf, true); word = (u32) buf[3]; @@ -2209,7 +2209,7 @@ int DRXJ_DAP_AtomicReadReg32(struct i2c_device_addr *devAddr, /*============================================================================*/ /** -* \fn int HICfgCommand() +* \fn int hi_cfg_command() * \brief Configure HI with settings stored in the demod structure. * \param demod Demodulator. * \return int. @@ -2219,26 +2219,26 @@ int DRXJ_DAP_AtomicReadReg32(struct i2c_device_addr *devAddr, * enable/disable should not need re-configuration of the HI. * */ -static int HICfgCommand(const pDRXDemodInstance_t demod) +static int hi_cfg_command(const pdrx_demod_instance_t demod) { - pDRXJData_t extAttr = (pDRXJData_t) (NULL); - DRXJHiCmd_t hiCmd; + pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); + drxj_hi_cmd_t hi_cmd; u16 result = 0; - extAttr = (pDRXJData_t) demod->myExtAttr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; - hiCmd.cmd = SIO_HI_RA_RAM_CMD_CONFIG; - hiCmd.param1 = SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY; - hiCmd.param2 = extAttr->HICfgTimingDiv; - hiCmd.param3 = extAttr->HICfgBridgeDelay; - hiCmd.param4 = extAttr->HICfgWakeUpKey; - hiCmd.param5 = extAttr->HICfgCtrl; - hiCmd.param6 = extAttr->HICfgTransmit; + hi_cmd.cmd = SIO_HI_RA_RAM_CMD_CONFIG; + hi_cmd.param1 = SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY; + hi_cmd.param2 = ext_attr->hi_cfg_timing_div; + hi_cmd.param3 = ext_attr->hi_cfg_bridge_delay; + hi_cmd.param4 = ext_attr->hi_cfg_wake_up_key; + hi_cmd.param5 = ext_attr->hi_cfg_ctrl; + hi_cmd.param6 = ext_attr->hi_cfg_transmit; - CHK_ERROR(HICommand(demod->myI2CDevAddr, &hiCmd, &result)); + CHK_ERROR(hi_command(demod->my_i2c_dev_addr, &hi_cmd, &result)); /* Reset power down flag (set one call only) */ - extAttr->HICfgCtrl &= (~(SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ)); + ext_attr->hi_cfg_ctrl &= (~(SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ)); return (DRX_STS_OK); @@ -2247,9 +2247,9 @@ rw_error: } /** -* \fn int HICommand() +* \fn int hi_command() * \brief Configure HI with settings stored in the demod structure. -* \param devAddr I2C address. +* \param dev_addr I2C address. * \param cmd HI command. * \param result HI command result. * \return int. @@ -2258,10 +2258,10 @@ rw_error: * */ static int -HICommand(struct i2c_device_addr *devAddr, const pDRXJHiCmd_t cmd, u16 *result) +hi_command(struct i2c_device_addr *dev_addr, const pdrxj_hi_cmd_t cmd, u16 *result) { - u16 waitCmd = 0; - u16 nrRetries = 0; + u16 wait_cmd = 0; + u16 nr_retries = 0; bool powerdown_cmd = false; /* Write parameters */ @@ -2269,14 +2269,14 @@ HICommand(struct i2c_device_addr *devAddr, const pDRXJHiCmd_t cmd, u16 *result) case SIO_HI_RA_RAM_CMD_CONFIG: case SIO_HI_RA_RAM_CMD_ATOMIC_COPY: - WR16(devAddr, SIO_HI_RA_RAM_PAR_6__A, cmd->param6); - WR16(devAddr, SIO_HI_RA_RAM_PAR_5__A, cmd->param5); - WR16(devAddr, SIO_HI_RA_RAM_PAR_4__A, cmd->param4); - WR16(devAddr, SIO_HI_RA_RAM_PAR_3__A, cmd->param3); + WR16(dev_addr, SIO_HI_RA_RAM_PAR_6__A, cmd->param6); + WR16(dev_addr, SIO_HI_RA_RAM_PAR_5__A, cmd->param5); + WR16(dev_addr, SIO_HI_RA_RAM_PAR_4__A, cmd->param4); + WR16(dev_addr, SIO_HI_RA_RAM_PAR_3__A, cmd->param3); /* fallthrough */ case SIO_HI_RA_RAM_CMD_BRDCTRL: - WR16(devAddr, SIO_HI_RA_RAM_PAR_2__A, cmd->param2); - WR16(devAddr, SIO_HI_RA_RAM_PAR_1__A, cmd->param1); + WR16(dev_addr, SIO_HI_RA_RAM_PAR_2__A, cmd->param2); + WR16(dev_addr, SIO_HI_RA_RAM_PAR_1__A, cmd->param1); /* fallthrough */ case SIO_HI_RA_RAM_CMD_NULL: /* No parameters */ @@ -2288,11 +2288,11 @@ HICommand(struct i2c_device_addr *devAddr, const pDRXJHiCmd_t cmd, u16 *result) } /* Write command */ - WR16(devAddr, SIO_HI_RA_RAM_CMD__A, cmd->cmd); + WR16(dev_addr, SIO_HI_RA_RAM_CMD__A, cmd->cmd); if ((cmd->cmd) == SIO_HI_RA_RAM_CMD_RESET) { /* Allow for HI to reset */ - DRXBSP_HST_Sleep(1); + drxbsp_hst_sleep(1); } /* Detect power down to ommit reading result */ @@ -2303,16 +2303,16 @@ HICommand(struct i2c_device_addr *devAddr, const pDRXJHiCmd_t cmd, u16 *result) if (powerdown_cmd == false) { /* Wait until command rdy */ do { - nrRetries++; - if (nrRetries > DRXJ_MAX_RETRIES) { + nr_retries++; + if (nr_retries > DRXJ_MAX_RETRIES) { goto rw_error; }; - RR16(devAddr, SIO_HI_RA_RAM_CMD__A, &waitCmd); - } while (waitCmd != 0); + RR16(dev_addr, SIO_HI_RA_RAM_CMD__A, &wait_cmd); + } while (wait_cmd != 0); /* Read result */ - RR16(devAddr, SIO_HI_RA_RAM_RES__A, result); + RR16(dev_addr, SIO_HI_RA_RAM_RES__A, result); } /* if ( powerdown_cmd == true ) */ @@ -2322,7 +2322,7 @@ rw_error: } /** -* \fn int InitHI( const pDRXDemodInstance_t demod ) +* \fn int init_hi( const pdrx_demod_instance_t demod ) * \brief Initialise and configurate HI. * \param demod pointer to demod data. * \return int Return status. @@ -2334,50 +2334,50 @@ rw_error: * bridging is controlled. * */ -static int InitHI(const pDRXDemodInstance_t demod) +static int init_hi(const pdrx_demod_instance_t demod) { - pDRXJData_t extAttr = (pDRXJData_t) (NULL); - pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); - struct i2c_device_addr *devAddr = (struct i2c_device_addr *) (NULL); + pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); + pdrx_common_attr_t common_attr = (pdrx_common_attr_t) (NULL); + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) (NULL); - extAttr = (pDRXJData_t) demod->myExtAttr; - commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; - devAddr = demod->myI2CDevAddr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; + common_attr = (pdrx_common_attr_t) demod->my_common_attr; + dev_addr = demod->my_i2c_dev_addr; /* PATCH for bug 5003, HI ucode v3.1.0 */ - WR16(devAddr, 0x4301D7, 0x801); + WR16(dev_addr, 0x4301D7, 0x801); /* Timing div, 250ns/Psys */ /* Timing div, = ( delay (nano seconds) * sysclk (kHz) )/ 1000 */ - extAttr->HICfgTimingDiv = - (u16) ((commonAttr->sysClockFreq / 1000) * HI_I2C_DELAY) / 1000; + ext_attr->hi_cfg_timing_div = + (u16) ((common_attr->sys_clock_freq / 1000) * HI_I2C_DELAY) / 1000; /* Clipping */ - if ((extAttr->HICfgTimingDiv) > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M) { - extAttr->HICfgTimingDiv = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M; + if ((ext_attr->hi_cfg_timing_div) > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M) { + ext_attr->hi_cfg_timing_div = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M; } /* Bridge delay, uses oscilator clock */ /* Delay = ( delay (nano seconds) * oscclk (kHz) )/ 1000 */ /* SDA brdige delay */ - extAttr->HICfgBridgeDelay = - (u16) ((commonAttr->oscClockFreq / 1000) * HI_I2C_BRIDGE_DELAY) / + ext_attr->hi_cfg_bridge_delay = + (u16) ((common_attr->osc_clock_freq / 1000) * HI_I2C_BRIDGE_DELAY) / 1000; /* Clipping */ - if ((extAttr->HICfgBridgeDelay) > SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) { - extAttr->HICfgBridgeDelay = SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M; + if ((ext_attr->hi_cfg_bridge_delay) > SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) { + ext_attr->hi_cfg_bridge_delay = SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M; } /* SCL bridge delay, same as SDA for now */ - extAttr->HICfgBridgeDelay += ((extAttr->HICfgBridgeDelay) << + ext_attr->hi_cfg_bridge_delay += ((ext_attr->hi_cfg_bridge_delay) << SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B); /* Wakeup key, setting the read flag (as suggest in the documentation) does not always result into a working solution (barebones worked VI2C failed). Not setting the bit works in all cases . */ - extAttr->HICfgWakeUpKey = DRXJ_WAKE_UP_KEY; + ext_attr->hi_cfg_wake_up_key = DRXJ_WAKE_UP_KEY; /* port/bridge/power down ctrl */ - extAttr->HICfgCtrl = (SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE); + ext_attr->hi_cfg_ctrl = (SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE); /* transit mode time out delay and watch dog divider */ - extAttr->HICfgTransmit = SIO_HI_RA_RAM_PAR_6__PRE; + ext_attr->hi_cfg_transmit = SIO_HI_RA_RAM_PAR_6__PRE; - CHK_ERROR(HICfgCommand(demod)); + CHK_ERROR(hi_cfg_command(demod)); return (DRX_STS_OK); @@ -2396,7 +2396,7 @@ rw_error: /*============================================================================*/ /** -* \fn int GetDeviceCapabilities() +* \fn int get_device_capabilities() * \brief Get and store device capabilities. * \param demod Pointer to demodulator instance. * \return int. @@ -2404,45 +2404,45 @@ rw_error: * \retval DRX_STS_ERROR Failure * * Depending on pulldowns on MDx pins the following internals are set: -* * commonAttr->oscClockFreq -* * extAttr->hasLNA -* * extAttr->hasNTSC -* * extAttr->hasBTSC -* * extAttr->hasOOB +* * common_attr->osc_clock_freq +* * ext_attr->has_lna +* * ext_attr->has_ntsc +* * ext_attr->has_btsc +* * ext_attr->has_oob * */ -static int GetDeviceCapabilities(pDRXDemodInstance_t demod) +static int get_device_capabilities(pdrx_demod_instance_t demod) { - pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); - pDRXJData_t extAttr = (pDRXJData_t) NULL; - struct i2c_device_addr *devAddr = (struct i2c_device_addr *) (NULL); - u16 sioPdrOhwCfg = 0; - u32 sioTopJtagidLo = 0; + pdrx_common_attr_t common_attr = (pdrx_common_attr_t) (NULL); + pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) (NULL); + u16 sio_pdr_ohw_cfg = 0; + u32 sio_top_jtagid_lo = 0; u16 bid = 0; - commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; - extAttr = (pDRXJData_t) demod->myExtAttr; - devAddr = demod->myI2CDevAddr; + common_attr = (pdrx_common_attr_t) demod->my_common_attr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; + dev_addr = demod->my_i2c_dev_addr; - WR16(devAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); - RR16(devAddr, SIO_PDR_OHW_CFG__A, &sioPdrOhwCfg); - WR16(devAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE); + WR16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); + RR16(dev_addr, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg); + WR16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE); - switch ((sioPdrOhwCfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) { + switch ((sio_pdr_ohw_cfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) { case 0: /* ignore (bypass ?) */ break; case 1: /* 27 MHz */ - commonAttr->oscClockFreq = 27000; + common_attr->osc_clock_freq = 27000; break; case 2: /* 20.25 MHz */ - commonAttr->oscClockFreq = 20250; + common_attr->osc_clock_freq = 20250; break; case 3: /* 4 MHz */ - commonAttr->oscClockFreq = 4000; + common_attr->osc_clock_freq = 4000; break; default: return (DRX_STS_ERROR); @@ -2452,114 +2452,114 @@ static int GetDeviceCapabilities(pDRXDemodInstance_t demod) Determine device capabilities Based on pinning v47 */ - RR32(devAddr, SIO_TOP_JTAGID_LO__A, &sioTopJtagidLo); - extAttr->mfx = (u8) ((sioTopJtagidLo >> 29) & 0xF); + RR32(dev_addr, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo); + ext_attr->mfx = (u8) ((sio_top_jtagid_lo >> 29) & 0xF); - switch ((sioTopJtagidLo >> 12) & 0xFF) { + switch ((sio_top_jtagid_lo >> 12) & 0xFF) { case 0x31: - WR16(devAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); - RR16(devAddr, SIO_PDR_UIO_IN_HI__A, &bid); + WR16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); + RR16(dev_addr, SIO_PDR_UIO_IN_HI__A, &bid); bid = (bid >> 10) & 0xf; - WR16(devAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE); + WR16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE); - extAttr->hasLNA = true; - extAttr->hasNTSC = false; - extAttr->hasBTSC = false; - extAttr->hasOOB = false; - extAttr->hasSMATX = true; - extAttr->hasSMARX = false; - extAttr->hasGPIO = false; - extAttr->hasIRQN = false; + ext_attr->has_lna = true; + ext_attr->has_ntsc = false; + ext_attr->has_btsc = false; + ext_attr->has_oob = false; + ext_attr->has_smatx = true; + ext_attr->has_smarx = false; + ext_attr->has_gpio = false; + ext_attr->has_irqn = false; break; case 0x33: - extAttr->hasLNA = false; - extAttr->hasNTSC = false; - extAttr->hasBTSC = false; - extAttr->hasOOB = false; - extAttr->hasSMATX = true; - extAttr->hasSMARX = false; - extAttr->hasGPIO = false; - extAttr->hasIRQN = false; + ext_attr->has_lna = false; + ext_attr->has_ntsc = false; + ext_attr->has_btsc = false; + ext_attr->has_oob = false; + ext_attr->has_smatx = true; + ext_attr->has_smarx = false; + ext_attr->has_gpio = false; + ext_attr->has_irqn = false; break; case 0x45: - extAttr->hasLNA = true; - extAttr->hasNTSC = true; - extAttr->hasBTSC = false; - extAttr->hasOOB = false; - extAttr->hasSMATX = true; - extAttr->hasSMARX = true; - extAttr->hasGPIO = true; - extAttr->hasIRQN = false; + ext_attr->has_lna = true; + ext_attr->has_ntsc = true; + ext_attr->has_btsc = false; + ext_attr->has_oob = false; + ext_attr->has_smatx = true; + ext_attr->has_smarx = true; + ext_attr->has_gpio = true; + ext_attr->has_irqn = false; break; case 0x46: - extAttr->hasLNA = false; - extAttr->hasNTSC = true; - extAttr->hasBTSC = false; - extAttr->hasOOB = false; - extAttr->hasSMATX = true; - extAttr->hasSMARX = true; - extAttr->hasGPIO = true; - extAttr->hasIRQN = false; + ext_attr->has_lna = false; + ext_attr->has_ntsc = true; + ext_attr->has_btsc = false; + ext_attr->has_oob = false; + ext_attr->has_smatx = true; + ext_attr->has_smarx = true; + ext_attr->has_gpio = true; + ext_attr->has_irqn = false; break; case 0x41: - extAttr->hasLNA = true; - extAttr->hasNTSC = true; - extAttr->hasBTSC = true; - extAttr->hasOOB = false; - extAttr->hasSMATX = true; - extAttr->hasSMARX = true; - extAttr->hasGPIO = true; - extAttr->hasIRQN = false; + ext_attr->has_lna = true; + ext_attr->has_ntsc = true; + ext_attr->has_btsc = true; + ext_attr->has_oob = false; + ext_attr->has_smatx = true; + ext_attr->has_smarx = true; + ext_attr->has_gpio = true; + ext_attr->has_irqn = false; break; case 0x43: - extAttr->hasLNA = false; - extAttr->hasNTSC = true; - extAttr->hasBTSC = true; - extAttr->hasOOB = false; - extAttr->hasSMATX = true; - extAttr->hasSMARX = true; - extAttr->hasGPIO = true; - extAttr->hasIRQN = false; + ext_attr->has_lna = false; + ext_attr->has_ntsc = true; + ext_attr->has_btsc = true; + ext_attr->has_oob = false; + ext_attr->has_smatx = true; + ext_attr->has_smarx = true; + ext_attr->has_gpio = true; + ext_attr->has_irqn = false; break; case 0x32: - extAttr->hasLNA = true; - extAttr->hasNTSC = false; - extAttr->hasBTSC = false; - extAttr->hasOOB = true; - extAttr->hasSMATX = true; - extAttr->hasSMARX = true; - extAttr->hasGPIO = true; - extAttr->hasIRQN = true; + ext_attr->has_lna = true; + ext_attr->has_ntsc = false; + ext_attr->has_btsc = false; + ext_attr->has_oob = true; + ext_attr->has_smatx = true; + ext_attr->has_smarx = true; + ext_attr->has_gpio = true; + ext_attr->has_irqn = true; break; case 0x34: - extAttr->hasLNA = false; - extAttr->hasNTSC = true; - extAttr->hasBTSC = true; - extAttr->hasOOB = true; - extAttr->hasSMATX = true; - extAttr->hasSMARX = true; - extAttr->hasGPIO = true; - extAttr->hasIRQN = true; + ext_attr->has_lna = false; + ext_attr->has_ntsc = true; + ext_attr->has_btsc = true; + ext_attr->has_oob = true; + ext_attr->has_smatx = true; + ext_attr->has_smarx = true; + ext_attr->has_gpio = true; + ext_attr->has_irqn = true; break; case 0x42: - extAttr->hasLNA = true; - extAttr->hasNTSC = true; - extAttr->hasBTSC = true; - extAttr->hasOOB = true; - extAttr->hasSMATX = true; - extAttr->hasSMARX = true; - extAttr->hasGPIO = true; - extAttr->hasIRQN = true; + ext_attr->has_lna = true; + ext_attr->has_ntsc = true; + ext_attr->has_btsc = true; + ext_attr->has_oob = true; + ext_attr->has_smatx = true; + ext_attr->has_smarx = true; + ext_attr->has_gpio = true; + ext_attr->has_irqn = true; break; case 0x44: - extAttr->hasLNA = false; - extAttr->hasNTSC = true; - extAttr->hasBTSC = true; - extAttr->hasOOB = true; - extAttr->hasSMATX = true; - extAttr->hasSMARX = true; - extAttr->hasGPIO = true; - extAttr->hasIRQN = true; + ext_attr->has_lna = false; + ext_attr->has_ntsc = true; + ext_attr->has_btsc = true; + ext_attr->has_oob = true; + ext_attr->has_smatx = true; + ext_attr->has_smarx = true; + ext_attr->has_gpio = true; + ext_attr->has_irqn = true; break; default: /* Unknown device variant */ @@ -2573,7 +2573,7 @@ rw_error: } /** -* \fn int PowerUpDevice() +* \fn int power_up_device() * \brief Power up device. * \param demod Pointer to demodulator instance. * \return int. @@ -2586,36 +2586,36 @@ rw_error: #define DRXJ_MAX_RETRIES_POWERUP 10 #endif -static int PowerUpDevice(pDRXDemodInstance_t demod) +static int power_up_device(pdrx_demod_instance_t demod) { - struct i2c_device_addr *devAddr = (struct i2c_device_addr *) (NULL); + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) (NULL); u8 data = 0; - u16 retryCount = 0; - struct i2c_device_addr wakeUpAddr; + u16 retry_count = 0; + struct i2c_device_addr wake_up_addr; - devAddr = demod->myI2CDevAddr; - wakeUpAddr.i2cAddr = DRXJ_WAKE_UP_KEY; - wakeUpAddr.i2cDevId = devAddr->i2cDevId; - wakeUpAddr.userData = devAddr->userData; + dev_addr = demod->my_i2c_dev_addr; + wake_up_addr.i2c_addr = DRXJ_WAKE_UP_KEY; + wake_up_addr.i2c_dev_id = dev_addr->i2c_dev_id; + wake_up_addr.user_data = dev_addr->user_data; /* CHK_ERROR macro not used, I2C access may fail in this case: no ack dummy write must be used to wake uop device, dummy read must be used to reset HI state machine (avoiding actual writes) */ do { data = 0; - DRXBSP_I2C_WriteRead(&wakeUpAddr, 1, &data, + drxbsp_i2c_write_read(&wake_up_addr, 1, &data, (struct i2c_device_addr *) (NULL), 0, (u8 *) (NULL)); - DRXBSP_HST_Sleep(10); - retryCount++; - } while ((DRXBSP_I2C_WriteRead - ((struct i2c_device_addr *) (NULL), 0, (u8 *) (NULL), devAddr, 1, + drxbsp_hst_sleep(10); + retry_count++; + } while ((drxbsp_i2c_write_read + ((struct i2c_device_addr *) (NULL), 0, (u8 *) (NULL), dev_addr, 1, &data) - != DRX_STS_OK) && (retryCount < DRXJ_MAX_RETRIES_POWERUP)); + != DRX_STS_OK) && (retry_count < DRXJ_MAX_RETRIES_POWERUP)); /* Need some recovery time .... */ - DRXBSP_HST_Sleep(10); + drxbsp_hst_sleep(10); - if (retryCount == DRXJ_MAX_RETRIES_POWERUP) { + if (retry_count == DRXJ_MAX_RETRIES_POWERUP) { return (DRX_STS_ERROR); } @@ -2626,47 +2626,47 @@ static int PowerUpDevice(pDRXDemodInstance_t demod) /* MPEG Output Configuration Functions - begin */ /*----------------------------------------------------------------------------*/ /** -* \fn int CtrlSetCfgMPEGOutput() +* \fn int ctrl_set_cfg_mpeg_output() * \brief Set MPEG output configuration of the device. * \param devmod Pointer to demodulator instance. -* \param cfgData Pointer to mpeg output configuaration. +* \param cfg_data Pointer to mpeg output configuaration. * \return int. * * Configure MPEG output parameters. * */ static int -CtrlSetCfgMPEGOutput(pDRXDemodInstance_t demod, pDRXCfgMPEGOutput_t cfgData) -{ - struct i2c_device_addr *devAddr = (struct i2c_device_addr *) (NULL); - pDRXJData_t extAttr = (pDRXJData_t) (NULL); - pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); - u16 fecOcRegMode = 0; - u16 fecOcRegIprMode = 0; - u16 fecOcRegIprInvert = 0; - u32 maxBitRate = 0; - u32 rcnRate = 0; - u32 nrBits = 0; - u16 sioPdrMdCfg = 0; +ctrl_set_cfg_mpeg_output(pdrx_demod_instance_t demod, pdrx_cfg_mpeg_output_t cfg_data) +{ + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) (NULL); + pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); + pdrx_common_attr_t common_attr = (pdrx_common_attr_t) (NULL); + u16 fec_oc_reg_mode = 0; + u16 fec_oc_reg_ipr_mode = 0; + u16 fec_oc_reg_ipr_invert = 0; + u32 max_bit_rate = 0; + u32 rcn_rate = 0; + u32 nr_bits = 0; + u16 sio_pdr_md_cfg = 0; /* data mask for the output data byte */ - u16 InvertDataMask = + u16 invert_data_mask = FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M | FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M | FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M | FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M; /* check arguments */ - if ((demod == NULL) || (cfgData == NULL)) { + if ((demod == NULL) || (cfg_data == NULL)) { return (DRX_STS_INVALID_ARG); } - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; - commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; + common_attr = (pdrx_common_attr_t) demod->my_common_attr; - if (cfgData->enableMPEGOutput == true) { + if (cfg_data->enable_mpeg_output == true) { /* quick and dirty patch to set MPEG incase current std is not producing MPEG */ - switch (extAttr->standard) { + switch (ext_attr->standard) { case DRX_STANDARD_8VSB: case DRX_STANDARD_ITU_A: case DRX_STANDARD_ITU_B: @@ -2674,105 +2674,105 @@ CtrlSetCfgMPEGOutput(pDRXDemodInstance_t demod, pDRXCfgMPEGOutput_t cfgData) break; default: /* not an MPEG producing std, just store MPEG cfg */ - commonAttr->mpegCfg.enableMPEGOutput = - cfgData->enableMPEGOutput; - commonAttr->mpegCfg.insertRSByte = - cfgData->insertRSByte; - commonAttr->mpegCfg.enableParallel = - cfgData->enableParallel; - commonAttr->mpegCfg.invertDATA = cfgData->invertDATA; - commonAttr->mpegCfg.invertERR = cfgData->invertERR; - commonAttr->mpegCfg.invertSTR = cfgData->invertSTR; - commonAttr->mpegCfg.invertVAL = cfgData->invertVAL; - commonAttr->mpegCfg.invertCLK = cfgData->invertCLK; - commonAttr->mpegCfg.staticCLK = cfgData->staticCLK; - commonAttr->mpegCfg.bitrate = cfgData->bitrate; + common_attr->mpeg_cfg.enable_mpeg_output = + cfg_data->enable_mpeg_output; + common_attr->mpeg_cfg.insert_rs_byte = + cfg_data->insert_rs_byte; + common_attr->mpeg_cfg.enable_parallel = + cfg_data->enable_parallel; + common_attr->mpeg_cfg.invert_data = cfg_data->invert_data; + common_attr->mpeg_cfg.invert_err = cfg_data->invert_err; + common_attr->mpeg_cfg.invert_str = cfg_data->invert_str; + common_attr->mpeg_cfg.invert_val = cfg_data->invert_val; + common_attr->mpeg_cfg.invert_clk = cfg_data->invert_clk; + common_attr->mpeg_cfg.static_clk = cfg_data->static_clk; + common_attr->mpeg_cfg.bitrate = cfg_data->bitrate; return (DRX_STS_OK); } - WR16(devAddr, FEC_OC_OCR_INVERT__A, 0); - switch (extAttr->standard) { + WR16(dev_addr, FEC_OC_OCR_INVERT__A, 0); + switch (ext_attr->standard) { case DRX_STANDARD_8VSB: - WR16(devAddr, FEC_OC_FCT_USAGE__A, 7); /* 2048 bytes fifo ram */ - WR16(devAddr, FEC_OC_TMD_CTL_UPD_RATE__A, 10); - WR16(devAddr, FEC_OC_TMD_INT_UPD_RATE__A, 10); - WR16(devAddr, FEC_OC_AVR_PARM_A__A, 5); - WR16(devAddr, FEC_OC_AVR_PARM_B__A, 7); - WR16(devAddr, FEC_OC_RCN_GAIN__A, 10); + WR16(dev_addr, FEC_OC_FCT_USAGE__A, 7); /* 2048 bytes fifo ram */ + WR16(dev_addr, FEC_OC_TMD_CTL_UPD_RATE__A, 10); + WR16(dev_addr, FEC_OC_TMD_INT_UPD_RATE__A, 10); + WR16(dev_addr, FEC_OC_AVR_PARM_A__A, 5); + WR16(dev_addr, FEC_OC_AVR_PARM_B__A, 7); + WR16(dev_addr, FEC_OC_RCN_GAIN__A, 10); /* Low Water Mark for synchronization */ - WR16(devAddr, FEC_OC_SNC_LWM__A, 3); + WR16(dev_addr, FEC_OC_SNC_LWM__A, 3); /* High Water Mark for synchronization */ - WR16(devAddr, FEC_OC_SNC_HWM__A, 5); + WR16(dev_addr, FEC_OC_SNC_HWM__A, 5); break; case DRX_STANDARD_ITU_A: case DRX_STANDARD_ITU_C: - switch (extAttr->constellation) { + switch (ext_attr->constellation) { case DRX_CONSTELLATION_QAM256: - nrBits = 8; + nr_bits = 8; break; case DRX_CONSTELLATION_QAM128: - nrBits = 7; + nr_bits = 7; break; case DRX_CONSTELLATION_QAM64: - nrBits = 6; + nr_bits = 6; break; case DRX_CONSTELLATION_QAM32: - nrBits = 5; + nr_bits = 5; break; case DRX_CONSTELLATION_QAM16: - nrBits = 4; + nr_bits = 4; break; default: return (DRX_STS_ERROR); - } /* extAttr->constellation */ - /* maxBitRate = symbolRate * nrBits * coef */ + } /* ext_attr->constellation */ + /* max_bit_rate = symbol_rate * nr_bits * coef */ /* coef = 188/204 */ - maxBitRate = - (extAttr->currSymbolRate / 8) * nrBits * 188; + max_bit_rate = + (ext_attr->curr_symbol_rate / 8) * nr_bits * 188; /* pass through b/c Annex A/c need following settings */ case DRX_STANDARD_ITU_B: - WR16(devAddr, FEC_OC_FCT_USAGE__A, + WR16(dev_addr, FEC_OC_FCT_USAGE__A, FEC_OC_FCT_USAGE__PRE); - WR16(devAddr, FEC_OC_TMD_CTL_UPD_RATE__A, + WR16(dev_addr, FEC_OC_TMD_CTL_UPD_RATE__A, FEC_OC_TMD_CTL_UPD_RATE__PRE); - WR16(devAddr, FEC_OC_TMD_INT_UPD_RATE__A, 5); - WR16(devAddr, FEC_OC_AVR_PARM_A__A, + WR16(dev_addr, FEC_OC_TMD_INT_UPD_RATE__A, 5); + WR16(dev_addr, FEC_OC_AVR_PARM_A__A, FEC_OC_AVR_PARM_A__PRE); - WR16(devAddr, FEC_OC_AVR_PARM_B__A, + WR16(dev_addr, FEC_OC_AVR_PARM_B__A, FEC_OC_AVR_PARM_B__PRE); - if (cfgData->staticCLK == true) { - WR16(devAddr, FEC_OC_RCN_GAIN__A, 0xD); + if (cfg_data->static_clk == true) { + WR16(dev_addr, FEC_OC_RCN_GAIN__A, 0xD); } else { - WR16(devAddr, FEC_OC_RCN_GAIN__A, + WR16(dev_addr, FEC_OC_RCN_GAIN__A, FEC_OC_RCN_GAIN__PRE); } - WR16(devAddr, FEC_OC_SNC_LWM__A, 2); - WR16(devAddr, FEC_OC_SNC_HWM__A, 12); + WR16(dev_addr, FEC_OC_SNC_LWM__A, 2); + WR16(dev_addr, FEC_OC_SNC_HWM__A, 12); break; default: break; } /* swtich (standard) */ /* Check insertion of the Reed-Solomon parity bytes */ - RR16(devAddr, FEC_OC_MODE__A, &fecOcRegMode); - RR16(devAddr, FEC_OC_IPR_MODE__A, &fecOcRegIprMode); - if (cfgData->insertRSByte == true) { + RR16(dev_addr, FEC_OC_MODE__A, &fec_oc_reg_mode); + RR16(dev_addr, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode); + if (cfg_data->insert_rs_byte == true) { /* enable parity symbol forward */ - fecOcRegMode |= FEC_OC_MODE_PARITY__M; + fec_oc_reg_mode |= FEC_OC_MODE_PARITY__M; /* MVAL disable during parity bytes */ - fecOcRegIprMode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M; - switch (extAttr->standard) { + fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M; + switch (ext_attr->standard) { case DRX_STANDARD_8VSB: - rcnRate = 0x004854D3; + rcn_rate = 0x004854D3; break; case DRX_STANDARD_ITU_B: - fecOcRegMode |= FEC_OC_MODE_TRANSPARENT__M; - switch (extAttr->constellation) { + fec_oc_reg_mode |= FEC_OC_MODE_TRANSPARENT__M; + switch (ext_attr->constellation) { case DRX_CONSTELLATION_QAM256: - rcnRate = 0x008945E7; + rcn_rate = 0x008945E7; break; case DRX_CONSTELLATION_QAM64: - rcnRate = 0x005F64D4; + rcn_rate = 0x005F64D4; break; default: return (DRX_STS_ERROR); @@ -2780,34 +2780,34 @@ CtrlSetCfgMPEGOutput(pDRXDemodInstance_t demod, pDRXCfgMPEGOutput_t cfgData) break; case DRX_STANDARD_ITU_A: case DRX_STANDARD_ITU_C: - /* insertRSByte = true -> coef = 188/188 -> 1, RS bits are in MPEG output */ - rcnRate = - (Frac28 - (maxBitRate, - (u32) (commonAttr->sysClockFreq / 8))) / + /* insert_rs_byte = true -> coef = 188/188 -> 1, RS bits are in MPEG output */ + rcn_rate = + (frac28 + (max_bit_rate, + (u32) (common_attr->sys_clock_freq / 8))) / 188; break; default: return (DRX_STS_ERROR); - } /* extAttr->standard */ - } else { /* insertRSByte == false */ + } /* ext_attr->standard */ + } else { /* insert_rs_byte == false */ /* disable parity symbol forward */ - fecOcRegMode &= (~FEC_OC_MODE_PARITY__M); + fec_oc_reg_mode &= (~FEC_OC_MODE_PARITY__M); /* MVAL enable during parity bytes */ - fecOcRegIprMode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M); - switch (extAttr->standard) { + fec_oc_reg_ipr_mode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M); + switch (ext_attr->standard) { case DRX_STANDARD_8VSB: - rcnRate = 0x0041605C; + rcn_rate = 0x0041605C; break; case DRX_STANDARD_ITU_B: - fecOcRegMode &= (~FEC_OC_MODE_TRANSPARENT__M); - switch (extAttr->constellation) { + fec_oc_reg_mode &= (~FEC_OC_MODE_TRANSPARENT__M); + switch (ext_attr->constellation) { case DRX_CONSTELLATION_QAM256: - rcnRate = 0x0082D6A0; + rcn_rate = 0x0082D6A0; break; case DRX_CONSTELLATION_QAM64: - rcnRate = 0x005AEC1A; + rcn_rate = 0x005AEC1A; break; default: return (DRX_STS_ERROR); @@ -2815,210 +2815,210 @@ CtrlSetCfgMPEGOutput(pDRXDemodInstance_t demod, pDRXCfgMPEGOutput_t cfgData) break; case DRX_STANDARD_ITU_A: case DRX_STANDARD_ITU_C: - /* insertRSByte = false -> coef = 188/204, RS bits not in MPEG output */ - rcnRate = - (Frac28 - (maxBitRate, - (u32) (commonAttr->sysClockFreq / 8))) / + /* insert_rs_byte = false -> coef = 188/204, RS bits not in MPEG output */ + rcn_rate = + (frac28 + (max_bit_rate, + (u32) (common_attr->sys_clock_freq / 8))) / 204; break; default: return (DRX_STS_ERROR); - } /* extAttr->standard */ + } /* ext_attr->standard */ } - if (cfgData->enableParallel == true) { /* MPEG data output is paralel -> clear ipr_mode[0] */ - fecOcRegIprMode &= (~(FEC_OC_IPR_MODE_SERIAL__M)); + if (cfg_data->enable_parallel == true) { /* MPEG data output is paralel -> clear ipr_mode[0] */ + fec_oc_reg_ipr_mode &= (~(FEC_OC_IPR_MODE_SERIAL__M)); } else { /* MPEG data output is serial -> set ipr_mode[0] */ - fecOcRegIprMode |= FEC_OC_IPR_MODE_SERIAL__M; + fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_SERIAL__M; } /* Control slective inversion of output bits */ - if (cfgData->invertDATA == true) { - fecOcRegIprInvert |= InvertDataMask; + if (cfg_data->invert_data == true) { + fec_oc_reg_ipr_invert |= invert_data_mask; } else { - fecOcRegIprInvert &= (~(InvertDataMask)); + fec_oc_reg_ipr_invert &= (~(invert_data_mask)); } - if (cfgData->invertERR == true) { - fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MERR__M; + if (cfg_data->invert_err == true) { + fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MERR__M; } else { - fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MERR__M)); + fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MERR__M)); } - if (cfgData->invertSTR == true) { - fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MSTRT__M; + if (cfg_data->invert_str == true) { + fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MSTRT__M; } else { - fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MSTRT__M)); + fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MSTRT__M)); } - if (cfgData->invertVAL == true) { - fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MVAL__M; + if (cfg_data->invert_val == true) { + fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MVAL__M; } else { - fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MVAL__M)); + fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MVAL__M)); } - if (cfgData->invertCLK == true) { - fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MCLK__M; + if (cfg_data->invert_clk == true) { + fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MCLK__M; } else { - fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MCLK__M)); + fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MCLK__M)); } - if (cfgData->staticCLK == true) { /* Static mode */ - u32 dtoRate = 0; - u32 bitRate = 0; - u16 fecOcDtoBurstLen = 0; - u16 fecOcDtoPeriod = 0; + if (cfg_data->static_clk == true) { /* Static mode */ + u32 dto_rate = 0; + u32 bit_rate = 0; + u16 fec_oc_dto_burst_len = 0; + u16 fec_oc_dto_period = 0; - fecOcDtoBurstLen = FEC_OC_DTO_BURST_LEN__PRE; + fec_oc_dto_burst_len = FEC_OC_DTO_BURST_LEN__PRE; - switch (extAttr->standard) { + switch (ext_attr->standard) { case DRX_STANDARD_8VSB: - fecOcDtoPeriod = 4; - if (cfgData->insertRSByte == true) { - fecOcDtoBurstLen = 208; + fec_oc_dto_period = 4; + if (cfg_data->insert_rs_byte == true) { + fec_oc_dto_burst_len = 208; } break; case DRX_STANDARD_ITU_A: { - u32 symbolRateTh = 6400000; - if (cfgData->insertRSByte == true) { - fecOcDtoBurstLen = 204; - symbolRateTh = 5900000; + u32 symbol_rate_th = 6400000; + if (cfg_data->insert_rs_byte == true) { + fec_oc_dto_burst_len = 204; + symbol_rate_th = 5900000; } - if (extAttr->currSymbolRate >= - symbolRateTh) { - fecOcDtoPeriod = 0; + if (ext_attr->curr_symbol_rate >= + symbol_rate_th) { + fec_oc_dto_period = 0; } else { - fecOcDtoPeriod = 1; + fec_oc_dto_period = 1; } } break; case DRX_STANDARD_ITU_B: - fecOcDtoPeriod = 1; - if (cfgData->insertRSByte == true) { - fecOcDtoBurstLen = 128; + fec_oc_dto_period = 1; + if (cfg_data->insert_rs_byte == true) { + fec_oc_dto_burst_len = 128; } break; case DRX_STANDARD_ITU_C: - fecOcDtoPeriod = 1; - if (cfgData->insertRSByte == true) { - fecOcDtoBurstLen = 204; + fec_oc_dto_period = 1; + if (cfg_data->insert_rs_byte == true) { + fec_oc_dto_burst_len = 204; } break; default: return (DRX_STS_ERROR); } - bitRate = - commonAttr->sysClockFreq * 1000 / (fecOcDtoPeriod + + bit_rate = + common_attr->sys_clock_freq * 1000 / (fec_oc_dto_period + 2); - dtoRate = - Frac28(bitRate, commonAttr->sysClockFreq * 1000); - dtoRate >>= 3; - WR16(devAddr, FEC_OC_DTO_RATE_HI__A, - (u16) ((dtoRate >> 16) & FEC_OC_DTO_RATE_HI__M)); - WR16(devAddr, FEC_OC_DTO_RATE_LO__A, - (u16) (dtoRate & FEC_OC_DTO_RATE_LO_RATE_LO__M)); - WR16(devAddr, FEC_OC_DTO_MODE__A, + dto_rate = + frac28(bit_rate, common_attr->sys_clock_freq * 1000); + dto_rate >>= 3; + WR16(dev_addr, FEC_OC_DTO_RATE_HI__A, + (u16) ((dto_rate >> 16) & FEC_OC_DTO_RATE_HI__M)); + WR16(dev_addr, FEC_OC_DTO_RATE_LO__A, + (u16) (dto_rate & FEC_OC_DTO_RATE_LO_RATE_LO__M)); + WR16(dev_addr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M | FEC_OC_DTO_MODE_OFFSET_ENABLE__M); - WR16(devAddr, FEC_OC_FCT_MODE__A, + WR16(dev_addr, FEC_OC_FCT_MODE__A, FEC_OC_FCT_MODE_RAT_ENA__M | FEC_OC_FCT_MODE_VIRT_ENA__M); - WR16(devAddr, FEC_OC_DTO_BURST_LEN__A, - fecOcDtoBurstLen); - if (extAttr->mpegOutputClockRate != + WR16(dev_addr, FEC_OC_DTO_BURST_LEN__A, + fec_oc_dto_burst_len); + if (ext_attr->mpeg_output_clock_rate != DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO) - fecOcDtoPeriod = - extAttr->mpegOutputClockRate - 1; - WR16(devAddr, FEC_OC_DTO_PERIOD__A, fecOcDtoPeriod); + fec_oc_dto_period = + ext_attr->mpeg_output_clock_rate - 1; + WR16(dev_addr, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period); } else { /* Dynamic mode */ - WR16(devAddr, FEC_OC_DTO_MODE__A, + WR16(dev_addr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M); - WR16(devAddr, FEC_OC_FCT_MODE__A, 0); + WR16(dev_addr, FEC_OC_FCT_MODE__A, 0); } - WR32(devAddr, FEC_OC_RCN_CTL_RATE_LO__A, rcnRate); + WR32(dev_addr, FEC_OC_RCN_CTL_RATE_LO__A, rcn_rate); /* Write appropriate registers with requested configuration */ - WR16(devAddr, FEC_OC_MODE__A, fecOcRegMode); - WR16(devAddr, FEC_OC_IPR_MODE__A, fecOcRegIprMode); - WR16(devAddr, FEC_OC_IPR_INVERT__A, fecOcRegIprInvert); + WR16(dev_addr, FEC_OC_MODE__A, fec_oc_reg_mode); + WR16(dev_addr, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode); + WR16(dev_addr, FEC_OC_IPR_INVERT__A, fec_oc_reg_ipr_invert); /* enabling for both parallel and serial now */ /* Write magic word to enable pdr reg write */ - WR16(devAddr, SIO_TOP_COMM_KEY__A, 0xFABA); + WR16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA); /* Set MPEG TS pads to outputmode */ - WR16(devAddr, SIO_PDR_MSTRT_CFG__A, 0x0013); - WR16(devAddr, SIO_PDR_MERR_CFG__A, 0x0013); - WR16(devAddr, SIO_PDR_MCLK_CFG__A, + WR16(dev_addr, SIO_PDR_MSTRT_CFG__A, 0x0013); + WR16(dev_addr, SIO_PDR_MERR_CFG__A, 0x0013); + WR16(dev_addr, SIO_PDR_MCLK_CFG__A, MPEG_OUTPUT_CLK_DRIVE_STRENGTH << SIO_PDR_MCLK_CFG_DRIVE__B | 0x03 << SIO_PDR_MCLK_CFG_MODE__B); - WR16(devAddr, SIO_PDR_MVAL_CFG__A, 0x0013); - sioPdrMdCfg = + WR16(dev_addr, SIO_PDR_MVAL_CFG__A, 0x0013); + sio_pdr_md_cfg = MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH << SIO_PDR_MD0_CFG_DRIVE__B | 0x03 << SIO_PDR_MD0_CFG_MODE__B; - WR16(devAddr, SIO_PDR_MD0_CFG__A, sioPdrMdCfg); - if (cfgData->enableParallel == true) { /* MPEG data output is paralel -> set MD1 to MD7 to output mode */ - sioPdrMdCfg = + WR16(dev_addr, SIO_PDR_MD0_CFG__A, sio_pdr_md_cfg); + if (cfg_data->enable_parallel == true) { /* MPEG data output is paralel -> set MD1 to MD7 to output mode */ + sio_pdr_md_cfg = MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH << SIO_PDR_MD0_CFG_DRIVE__B | 0x03 << SIO_PDR_MD0_CFG_MODE__B; - WR16(devAddr, SIO_PDR_MD0_CFG__A, sioPdrMdCfg); - WR16(devAddr, SIO_PDR_MD1_CFG__A, sioPdrMdCfg); - WR16(devAddr, SIO_PDR_MD2_CFG__A, sioPdrMdCfg); - WR16(devAddr, SIO_PDR_MD3_CFG__A, sioPdrMdCfg); - WR16(devAddr, SIO_PDR_MD4_CFG__A, sioPdrMdCfg); - WR16(devAddr, SIO_PDR_MD5_CFG__A, sioPdrMdCfg); - WR16(devAddr, SIO_PDR_MD6_CFG__A, sioPdrMdCfg); - WR16(devAddr, SIO_PDR_MD7_CFG__A, sioPdrMdCfg); + WR16(dev_addr, SIO_PDR_MD0_CFG__A, sio_pdr_md_cfg); + WR16(dev_addr, SIO_PDR_MD1_CFG__A, sio_pdr_md_cfg); + WR16(dev_addr, SIO_PDR_MD2_CFG__A, sio_pdr_md_cfg); + WR16(dev_addr, SIO_PDR_MD3_CFG__A, sio_pdr_md_cfg); + WR16(dev_addr, SIO_PDR_MD4_CFG__A, sio_pdr_md_cfg); + WR16(dev_addr, SIO_PDR_MD5_CFG__A, sio_pdr_md_cfg); + WR16(dev_addr, SIO_PDR_MD6_CFG__A, sio_pdr_md_cfg); + WR16(dev_addr, SIO_PDR_MD7_CFG__A, sio_pdr_md_cfg); } else { /* MPEG data output is serial -> set MD1 to MD7 to tri-state */ - WR16(devAddr, SIO_PDR_MD1_CFG__A, 0x0000); - WR16(devAddr, SIO_PDR_MD2_CFG__A, 0x0000); - WR16(devAddr, SIO_PDR_MD3_CFG__A, 0x0000); - WR16(devAddr, SIO_PDR_MD4_CFG__A, 0x0000); - WR16(devAddr, SIO_PDR_MD5_CFG__A, 0x0000); - WR16(devAddr, SIO_PDR_MD6_CFG__A, 0x0000); - WR16(devAddr, SIO_PDR_MD7_CFG__A, 0x0000); + WR16(dev_addr, SIO_PDR_MD1_CFG__A, 0x0000); + WR16(dev_addr, SIO_PDR_MD2_CFG__A, 0x0000); + WR16(dev_addr, SIO_PDR_MD3_CFG__A, 0x0000); + WR16(dev_addr, SIO_PDR_MD4_CFG__A, 0x0000); + WR16(dev_addr, SIO_PDR_MD5_CFG__A, 0x0000); + WR16(dev_addr, SIO_PDR_MD6_CFG__A, 0x0000); + WR16(dev_addr, SIO_PDR_MD7_CFG__A, 0x0000); } /* Enable Monitor Bus output over MPEG pads and ctl input */ - WR16(devAddr, SIO_PDR_MON_CFG__A, 0x0000); + WR16(dev_addr, SIO_PDR_MON_CFG__A, 0x0000); /* Write nomagic word to enable pdr reg write */ - WR16(devAddr, SIO_TOP_COMM_KEY__A, 0x0000); + WR16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000); } else { /* Write magic word to enable pdr reg write */ - WR16(devAddr, SIO_TOP_COMM_KEY__A, 0xFABA); + WR16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA); /* Set MPEG TS pads to inputmode */ - WR16(devAddr, SIO_PDR_MSTRT_CFG__A, 0x0000); - WR16(devAddr, SIO_PDR_MERR_CFG__A, 0x0000); - WR16(devAddr, SIO_PDR_MCLK_CFG__A, 0x0000); - WR16(devAddr, SIO_PDR_MVAL_CFG__A, 0x0000); - WR16(devAddr, SIO_PDR_MD0_CFG__A, 0x0000); - WR16(devAddr, SIO_PDR_MD1_CFG__A, 0x0000); - WR16(devAddr, SIO_PDR_MD2_CFG__A, 0x0000); - WR16(devAddr, SIO_PDR_MD3_CFG__A, 0x0000); - WR16(devAddr, SIO_PDR_MD4_CFG__A, 0x0000); - WR16(devAddr, SIO_PDR_MD5_CFG__A, 0x0000); - WR16(devAddr, SIO_PDR_MD6_CFG__A, 0x0000); - WR16(devAddr, SIO_PDR_MD7_CFG__A, 0x0000); + WR16(dev_addr, SIO_PDR_MSTRT_CFG__A, 0x0000); + WR16(dev_addr, SIO_PDR_MERR_CFG__A, 0x0000); + WR16(dev_addr, SIO_PDR_MCLK_CFG__A, 0x0000); + WR16(dev_addr, SIO_PDR_MVAL_CFG__A, 0x0000); + WR16(dev_addr, SIO_PDR_MD0_CFG__A, 0x0000); + WR16(dev_addr, SIO_PDR_MD1_CFG__A, 0x0000); + WR16(dev_addr, SIO_PDR_MD2_CFG__A, 0x0000); + WR16(dev_addr, SIO_PDR_MD3_CFG__A, 0x0000); + WR16(dev_addr, SIO_PDR_MD4_CFG__A, 0x0000); + WR16(dev_addr, SIO_PDR_MD5_CFG__A, 0x0000); + WR16(dev_addr, SIO_PDR_MD6_CFG__A, 0x0000); + WR16(dev_addr, SIO_PDR_MD7_CFG__A, 0x0000); /* Enable Monitor Bus output over MPEG pads and ctl input */ - WR16(devAddr, SIO_PDR_MON_CFG__A, 0x0000); + WR16(dev_addr, SIO_PDR_MON_CFG__A, 0x0000); /* Write nomagic word to enable pdr reg write */ - WR16(devAddr, SIO_TOP_COMM_KEY__A, 0x0000); + WR16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000); } /* save values for restore after re-acquire */ - commonAttr->mpegCfg.enableMPEGOutput = cfgData->enableMPEGOutput; - commonAttr->mpegCfg.insertRSByte = cfgData->insertRSByte; - commonAttr->mpegCfg.enableParallel = cfgData->enableParallel; - commonAttr->mpegCfg.invertDATA = cfgData->invertDATA; - commonAttr->mpegCfg.invertERR = cfgData->invertERR; - commonAttr->mpegCfg.invertSTR = cfgData->invertSTR; - commonAttr->mpegCfg.invertVAL = cfgData->invertVAL; - commonAttr->mpegCfg.invertCLK = cfgData->invertCLK; - commonAttr->mpegCfg.staticCLK = cfgData->staticCLK; - commonAttr->mpegCfg.bitrate = cfgData->bitrate; + common_attr->mpeg_cfg.enable_mpeg_output = cfg_data->enable_mpeg_output; + common_attr->mpeg_cfg.insert_rs_byte = cfg_data->insert_rs_byte; + common_attr->mpeg_cfg.enable_parallel = cfg_data->enable_parallel; + common_attr->mpeg_cfg.invert_data = cfg_data->invert_data; + common_attr->mpeg_cfg.invert_err = cfg_data->invert_err; + common_attr->mpeg_cfg.invert_str = cfg_data->invert_str; + common_attr->mpeg_cfg.invert_val = cfg_data->invert_val; + common_attr->mpeg_cfg.invert_clk = cfg_data->invert_clk; + common_attr->mpeg_cfg.static_clk = cfg_data->static_clk; + common_attr->mpeg_cfg.bitrate = cfg_data->bitrate; return (DRX_STS_OK); rw_error: @@ -3028,49 +3028,49 @@ rw_error: /*----------------------------------------------------------------------------*/ /** -* \fn int CtrlGetCfgMPEGOutput() +* \fn int ctrl_get_cfg_mpeg_output() * \brief Get MPEG output configuration of the device. * \param devmod Pointer to demodulator instance. -* \param cfgData Pointer to MPEG output configuaration struct. +* \param cfg_data Pointer to MPEG output configuaration struct. * \return int. * * Retrieve MPEG output configuartion. * */ static int -CtrlGetCfgMPEGOutput(pDRXDemodInstance_t demod, pDRXCfgMPEGOutput_t cfgData) +ctrl_get_cfg_mpeg_output(pdrx_demod_instance_t demod, pdrx_cfg_mpeg_output_t cfg_data) { - struct i2c_device_addr *devAddr = (struct i2c_device_addr *) (NULL); - pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); - DRXLockStatus_t lockStatus = DRX_NOT_LOCKED; - u32 rateReg = 0; - u32 data64Hi = 0; - u32 data64Lo = 0; + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) (NULL); + pdrx_common_attr_t common_attr = (pdrx_common_attr_t) (NULL); + drx_lock_status_t lock_status = DRX_NOT_LOCKED; + u32 rate_reg = 0; + u32 data64hi = 0; + u32 data64lo = 0; - if (cfgData == NULL) { + if (cfg_data == NULL) { return (DRX_STS_INVALID_ARG); } - devAddr = demod->myI2CDevAddr; - commonAttr = demod->myCommonAttr; - - cfgData->enableMPEGOutput = commonAttr->mpegCfg.enableMPEGOutput; - cfgData->insertRSByte = commonAttr->mpegCfg.insertRSByte; - cfgData->enableParallel = commonAttr->mpegCfg.enableParallel; - cfgData->invertDATA = commonAttr->mpegCfg.invertDATA; - cfgData->invertERR = commonAttr->mpegCfg.invertERR; - cfgData->invertSTR = commonAttr->mpegCfg.invertSTR; - cfgData->invertVAL = commonAttr->mpegCfg.invertVAL; - cfgData->invertCLK = commonAttr->mpegCfg.invertCLK; - cfgData->staticCLK = commonAttr->mpegCfg.staticCLK; - cfgData->bitrate = 0; - - CHK_ERROR(CtrlLockStatus(demod, &lockStatus)); - if ((lockStatus == DRX_LOCKED)) { - RR32(devAddr, FEC_OC_RCN_DYN_RATE_LO__A, &rateReg); - /* Frcn_rate = rateReg * Fsys / 2 ^ 25 */ - Mult32(rateReg, commonAttr->sysClockFreq * 1000, &data64Hi, - &data64Lo); - cfgData->bitrate = (data64Hi << 7) | (data64Lo >> 25); + dev_addr = demod->my_i2c_dev_addr; + common_attr = demod->my_common_attr; + + cfg_data->enable_mpeg_output = common_attr->mpeg_cfg.enable_mpeg_output; + cfg_data->insert_rs_byte = common_attr->mpeg_cfg.insert_rs_byte; + cfg_data->enable_parallel = common_attr->mpeg_cfg.enable_parallel; + cfg_data->invert_data = common_attr->mpeg_cfg.invert_data; + cfg_data->invert_err = common_attr->mpeg_cfg.invert_err; + cfg_data->invert_str = common_attr->mpeg_cfg.invert_str; + cfg_data->invert_val = common_attr->mpeg_cfg.invert_val; + cfg_data->invert_clk = common_attr->mpeg_cfg.invert_clk; + cfg_data->static_clk = common_attr->mpeg_cfg.static_clk; + cfg_data->bitrate = 0; + + CHK_ERROR(ctrl_lock_status(demod, &lock_status)); + if ((lock_status == DRX_LOCKED)) { + RR32(dev_addr, FEC_OC_RCN_DYN_RATE_LO__A, &rate_reg); + /* Frcn_rate = rate_reg * Fsys / 2 ^ 25 */ + mult32(rate_reg, common_attr->sys_clock_freq * 1000, &data64hi, + &data64lo); + cfg_data->bitrate = (data64hi << 7) | (data64lo >> 25); } return (DRX_STS_OK); @@ -3087,7 +3087,7 @@ rw_error: /*----------------------------------------------------------------------------*/ /** -* \fn int SetMPEGTEIHandling() +* \fn int set_mpegtei_handling() * \brief Activate MPEG TEI handling settings. * \param devmod Pointer to demodulator instance. * \return int. @@ -3095,38 +3095,38 @@ rw_error: * This routine should be called during a set channel of QAM/VSB * */ -static int SetMPEGTEIHandling(pDRXDemodInstance_t demod) +static int set_mpegtei_handling(pdrx_demod_instance_t demod) { - pDRXJData_t extAttr = (pDRXJData_t) (NULL); - struct i2c_device_addr *devAddr = (struct i2c_device_addr *) (NULL); - u16 fecOcDprMode = 0; - u16 fecOcSncMode = 0; - u16 fecOcEmsMode = 0; + pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) (NULL); + u16 fec_oc_dpr_mode = 0; + u16 fec_oc_snc_mode = 0; + u16 fec_oc_ems_mode = 0; - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; - RR16(devAddr, FEC_OC_DPR_MODE__A, &fecOcDprMode); - RR16(devAddr, FEC_OC_SNC_MODE__A, &fecOcSncMode); - RR16(devAddr, FEC_OC_EMS_MODE__A, &fecOcEmsMode); + RR16(dev_addr, FEC_OC_DPR_MODE__A, &fec_oc_dpr_mode); + RR16(dev_addr, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode); + RR16(dev_addr, FEC_OC_EMS_MODE__A, &fec_oc_ems_mode); /* reset to default, allow TEI bit to be changed */ - fecOcDprMode &= (~FEC_OC_DPR_MODE_ERR_DISABLE__M); - fecOcSncMode &= (~(FEC_OC_SNC_MODE_ERROR_CTL__M | + fec_oc_dpr_mode &= (~FEC_OC_DPR_MODE_ERR_DISABLE__M); + fec_oc_snc_mode &= (~(FEC_OC_SNC_MODE_ERROR_CTL__M | FEC_OC_SNC_MODE_CORR_DISABLE__M)); - fecOcEmsMode &= (~FEC_OC_EMS_MODE_MODE__M); + fec_oc_ems_mode &= (~FEC_OC_EMS_MODE_MODE__M); - if (extAttr->disableTEIhandling == true) { + if (ext_attr->disable_te_ihandling == true) { /* do not change TEI bit */ - fecOcDprMode |= FEC_OC_DPR_MODE_ERR_DISABLE__M; - fecOcSncMode |= FEC_OC_SNC_MODE_CORR_DISABLE__M | + fec_oc_dpr_mode |= FEC_OC_DPR_MODE_ERR_DISABLE__M; + fec_oc_snc_mode |= FEC_OC_SNC_MODE_CORR_DISABLE__M | ((0x2) << (FEC_OC_SNC_MODE_ERROR_CTL__B)); - fecOcEmsMode |= ((0x01) << (FEC_OC_EMS_MODE_MODE__B)); + fec_oc_ems_mode |= ((0x01) << (FEC_OC_EMS_MODE_MODE__B)); } - WR16(devAddr, FEC_OC_DPR_MODE__A, fecOcDprMode); - WR16(devAddr, FEC_OC_SNC_MODE__A, fecOcSncMode); - WR16(devAddr, FEC_OC_EMS_MODE__A, fecOcEmsMode); + WR16(dev_addr, FEC_OC_DPR_MODE__A, fec_oc_dpr_mode); + WR16(dev_addr, FEC_OC_SNC_MODE__A, fec_oc_snc_mode); + WR16(dev_addr, FEC_OC_EMS_MODE__A, fec_oc_ems_mode); return (DRX_STS_OK); rw_error: @@ -3135,7 +3135,7 @@ rw_error: /*----------------------------------------------------------------------------*/ /** -* \fn int BitReverseMPEGOutput() +* \fn int bit_reverse_mpeg_output() * \brief Set MPEG output bit-endian settings. * \param devmod Pointer to demodulator instance. * \return int. @@ -3143,26 +3143,26 @@ rw_error: * This routine should be called during a set channel of QAM/VSB * */ -static int BitReverseMPEGOutput(pDRXDemodInstance_t demod) +static int bit_reverse_mpeg_output(pdrx_demod_instance_t demod) { - pDRXJData_t extAttr = (pDRXJData_t) (NULL); - struct i2c_device_addr *devAddr = (struct i2c_device_addr *) (NULL); - u16 fecOcIprMode = 0; + pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) (NULL); + u16 fec_oc_ipr_mode = 0; - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; - RR16(devAddr, FEC_OC_IPR_MODE__A, &fecOcIprMode); + RR16(dev_addr, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode); /* reset to default (normal bit order) */ - fecOcIprMode &= (~FEC_OC_IPR_MODE_REVERSE_ORDER__M); + fec_oc_ipr_mode &= (~FEC_OC_IPR_MODE_REVERSE_ORDER__M); - if (extAttr->bitReverseMpegOutout == true) { + if (ext_attr->bit_reverse_mpeg_outout == true) { /* reverse bit order */ - fecOcIprMode |= FEC_OC_IPR_MODE_REVERSE_ORDER__M; + fec_oc_ipr_mode |= FEC_OC_IPR_MODE_REVERSE_ORDER__M; } - WR16(devAddr, FEC_OC_IPR_MODE__A, fecOcIprMode); + WR16(dev_addr, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode); return (DRX_STS_OK); rw_error: @@ -3171,7 +3171,7 @@ rw_error: /*----------------------------------------------------------------------------*/ /** -* \fn int SetMPEGOutputClockRate() +* \fn int set_mpeg_output_clock_rate() * \brief Set MPEG output clock rate. * \param devmod Pointer to demodulator instance. * \return int. @@ -3179,17 +3179,17 @@ rw_error: * This routine should be called during a set channel of QAM/VSB * */ -static int SetMPEGOutputClockRate(pDRXDemodInstance_t demod) +static int set_mpeg_output_clock_rate(pdrx_demod_instance_t demod) { - pDRXJData_t extAttr = (pDRXJData_t) (NULL); - struct i2c_device_addr *devAddr = (struct i2c_device_addr *) (NULL); + pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) (NULL); - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; - if (extAttr->mpegOutputClockRate != DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO) { - WR16(devAddr, FEC_OC_DTO_PERIOD__A, - extAttr->mpegOutputClockRate - 1); + if (ext_attr->mpeg_output_clock_rate != DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO) { + WR16(dev_addr, FEC_OC_DTO_PERIOD__A, + ext_attr->mpeg_output_clock_rate - 1); } return (DRX_STS_OK); @@ -3199,7 +3199,7 @@ rw_error: /*----------------------------------------------------------------------------*/ /** -* \fn int SetMPEGStartWidth() +* \fn int set_mpeg_start_width() * \brief Set MPEG start width. * \param devmod Pointer to demodulator instance. * \return int. @@ -3207,25 +3207,25 @@ rw_error: * This routine should be called during a set channel of QAM/VSB * */ -static int SetMPEGStartWidth(pDRXDemodInstance_t demod) +static int set_mpeg_start_width(pdrx_demod_instance_t demod) { - pDRXJData_t extAttr = (pDRXJData_t) (NULL); - struct i2c_device_addr *devAddr = (struct i2c_device_addr *) (NULL); - u16 fecOcCommMb = 0; - pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) NULL; + pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) (NULL); + u16 fec_oc_comm_mb = 0; + pdrx_common_attr_t common_attr = (pdrx_common_attr_t) NULL; - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; - commonAttr = demod->myCommonAttr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; + common_attr = demod->my_common_attr; - if ((commonAttr->mpegCfg.staticCLK == true) - && (commonAttr->mpegCfg.enableParallel == false)) { - RR16(devAddr, FEC_OC_COMM_MB__A, &fecOcCommMb); - fecOcCommMb &= ~FEC_OC_COMM_MB_CTL_ON; - if (extAttr->mpegStartWidth == DRXJ_MPEG_START_WIDTH_8CLKCYC) { - fecOcCommMb |= FEC_OC_COMM_MB_CTL_ON; + if ((common_attr->mpeg_cfg.static_clk == true) + && (common_attr->mpeg_cfg.enable_parallel == false)) { + RR16(dev_addr, FEC_OC_COMM_MB__A, &fec_oc_comm_mb); + fec_oc_comm_mb &= ~FEC_OC_COMM_MB_CTL_ON; + if (ext_attr->mpeg_start_width == DRXJ_MPEG_START_WIDTH_8CLKCYC) { + fec_oc_comm_mb |= FEC_OC_COMM_MB_CTL_ON; } - WR16(devAddr, FEC_OC_COMM_MB__A, fecOcCommMb); + WR16(dev_addr, FEC_OC_COMM_MB__A, fec_oc_comm_mb); } return (DRX_STS_OK); @@ -3235,10 +3235,10 @@ rw_error: /*----------------------------------------------------------------------------*/ /** -* \fn int CtrlSetCfgMpegOutputMisc() +* \fn int ctrl_set_cfg_mpeg_output_misc() * \brief Set miscellaneous configuartions * \param devmod Pointer to demodulator instance. -* \param cfgData pDRXJCfgMisc_t +* \param cfg_data pDRXJCfgMisc_t * \return int. * * This routine can be used to set configuartion options that are DRXJ @@ -3246,16 +3246,16 @@ rw_error: * */ static int -CtrlSetCfgMpegOutputMisc(pDRXDemodInstance_t demod, - pDRXJCfgMpegOutputMisc_t cfgData) +ctrl_set_cfg_mpeg_output_misc(pdrx_demod_instance_t demod, + p_drxj_cfg_mpeg_output_misc_t cfg_data) { - pDRXJData_t extAttr = (pDRXJData_t) (NULL); + pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); - if (cfgData == NULL) { + if (cfg_data == NULL) { return (DRX_STS_INVALID_ARG); } - extAttr = (pDRXJData_t) demod->myExtAttr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* Set disable TEI bit handling flag. @@ -3266,15 +3266,15 @@ CtrlSetCfgMpegOutputMisc(pDRXDemodInstance_t demod, Set clock rate. Default is auto that is derived from symbol rate. The flags and values will also be used to set registers during a set channel. */ - extAttr->disableTEIhandling = cfgData->disableTEIHandling; - extAttr->bitReverseMpegOutout = cfgData->bitReverseMpegOutout; - extAttr->mpegOutputClockRate = cfgData->mpegOutputClockRate; - extAttr->mpegStartWidth = cfgData->mpegStartWidth; + ext_attr->disable_te_ihandling = cfg_data->disable_tei_handling; + ext_attr->bit_reverse_mpeg_outout = cfg_data->bit_reverse_mpeg_outout; + ext_attr->mpeg_output_clock_rate = cfg_data->mpeg_output_clock_rate; + ext_attr->mpeg_start_width = cfg_data->mpeg_start_width; /* Don't care what the active standard is, activate setting immediatly */ - CHK_ERROR(SetMPEGTEIHandling(demod)); - CHK_ERROR(BitReverseMPEGOutput(demod)); - CHK_ERROR(SetMPEGOutputClockRate(demod)); - CHK_ERROR(SetMPEGStartWidth(demod)); + CHK_ERROR(set_mpegtei_handling(demod)); + CHK_ERROR(bit_reverse_mpeg_output(demod)); + CHK_ERROR(set_mpeg_output_clock_rate(demod)); + CHK_ERROR(set_mpeg_start_width(demod)); return (DRX_STS_OK); rw_error: @@ -3284,10 +3284,10 @@ rw_error: /*----------------------------------------------------------------------------*/ /** -* \fn int CtrlGetCfgMpegOutputMisc() +* \fn int ctrl_get_cfg_mpeg_output_misc() * \brief Get miscellaneous configuartions. * \param devmod Pointer to demodulator instance. -* \param cfgData Pointer to DRXJCfgMisc_t. +* \param cfg_data Pointer to DRXJCfgMisc_t. * \return int. * * This routine can be used to retreive the current setting of the configuartion @@ -3296,26 +3296,26 @@ rw_error: * */ static int -CtrlGetCfgMpegOutputMisc(pDRXDemodInstance_t demod, - pDRXJCfgMpegOutputMisc_t cfgData) +ctrl_get_cfg_mpeg_output_misc(pdrx_demod_instance_t demod, + p_drxj_cfg_mpeg_output_misc_t cfg_data) { - pDRXJData_t extAttr = (pDRXJData_t) (NULL); + pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); u16 data = 0; - if (cfgData == NULL) { + if (cfg_data == NULL) { return (DRX_STS_INVALID_ARG); } - extAttr = (pDRXJData_t) demod->myExtAttr; - cfgData->disableTEIHandling = extAttr->disableTEIhandling; - cfgData->bitReverseMpegOutout = extAttr->bitReverseMpegOutout; - cfgData->mpegStartWidth = extAttr->mpegStartWidth; - if (extAttr->mpegOutputClockRate != DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO) { - cfgData->mpegOutputClockRate = extAttr->mpegOutputClockRate; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; + cfg_data->disable_tei_handling = ext_attr->disable_te_ihandling; + cfg_data->bit_reverse_mpeg_outout = ext_attr->bit_reverse_mpeg_outout; + cfg_data->mpeg_start_width = ext_attr->mpeg_start_width; + if (ext_attr->mpeg_output_clock_rate != DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO) { + cfg_data->mpeg_output_clock_rate = ext_attr->mpeg_output_clock_rate; } else { - RR16(demod->myI2CDevAddr, FEC_OC_DTO_PERIOD__A, &data); - cfgData->mpegOutputClockRate = - (DRXJMpegOutputClockRate_t) (data + 1); + RR16(demod->my_i2c_dev_addr, FEC_OC_DTO_PERIOD__A, &data); + cfg_data->mpeg_output_clock_rate = + (drxj_mpeg_output_clock_rate_t) (data + 1); } return (DRX_STS_OK); @@ -3326,10 +3326,10 @@ rw_error: /*----------------------------------------------------------------------------*/ /** -* \fn int CtrlGetCfgHwCfg() +* \fn int ctrl_get_cfg_hw_cfg() * \brief Get HW configuartions. * \param devmod Pointer to demodulator instance. -* \param cfgData Pointer to Bool. +* \param cfg_data Pointer to Bool. * \return int. * * This routine can be used to retreive the current setting of the configuartion @@ -3338,22 +3338,22 @@ rw_error: * */ static int -CtrlGetCfgHwCfg(pDRXDemodInstance_t demod, pDRXJCfgHwCfg_t cfgData) +ctrl_get_cfg_hw_cfg(pdrx_demod_instance_t demod, p_drxj_cfg_hw_cfg_t cfg_data) { u16 data = 0; - pDRXJData_t extAttr = (pDRXJData_t) (NULL); + pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); - if (cfgData == NULL) { + if (cfg_data == NULL) { return (DRX_STS_INVALID_ARG); } - extAttr = (pDRXJData_t) demod->myExtAttr; - WR16(demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, 0xFABA); - RR16(demod->myI2CDevAddr, SIO_PDR_OHW_CFG__A, &data); - WR16(demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, 0x0000); + ext_attr = (pdrxj_data_t) demod->my_ext_attr; + WR16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA); + RR16(demod->my_i2c_dev_addr, SIO_PDR_OHW_CFG__A, &data); + WR16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000); - cfgData->i2cSpeed = (DRXJI2CSpeed_t) ((data >> 6) & 0x1); - cfgData->xtalFreq = (DRXJXtalFreq_t) (data & 0x3); + cfg_data->i2c_speed = (drxji2c_speed_t) ((data >> 6) & 0x1); + cfg_data->xtal_freq = (drxj_xtal_freq_t) (data & 0x3); return (DRX_STS_OK); rw_error: @@ -3368,111 +3368,111 @@ rw_error: /* UIO Configuration Functions - begin */ /*----------------------------------------------------------------------------*/ /** -* \fn int CtrlSetUIOCfg() +* \fn int ctrl_set_uio_cfg() * \brief Configure modus oprandi UIO. * \param demod Pointer to demodulator instance. -* \param UIOCfg Pointer to a configuration setting for a certain UIO. +* \param uio_cfg Pointer to a configuration setting for a certain UIO. * \return int. */ -static int CtrlSetUIOCfg(pDRXDemodInstance_t demod, pDRXUIOCfg_t UIOCfg) +static int ctrl_set_uio_cfg(pdrx_demod_instance_t demod, pdrxuio_cfg_t uio_cfg) { - pDRXJData_t extAttr = (pDRXJData_t) (NULL); + pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); - if ((UIOCfg == NULL) || (demod == NULL)) { + if ((uio_cfg == NULL) || (demod == NULL)) { return DRX_STS_INVALID_ARG; } - extAttr = (pDRXJData_t) demod->myExtAttr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* Write magic word to enable pdr reg write */ - WR16(demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); - switch (UIOCfg->uio) { + WR16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); + switch (uio_cfg->uio) { /*====================================================================*/ case DRX_UIO1: /* DRX_UIO1: SMA_TX UIO-1 */ - if (extAttr->hasSMATX != true) + if (ext_attr->has_smatx != true) return DRX_STS_ERROR; - switch (UIOCfg->mode) { + switch (uio_cfg->mode) { case DRX_UIO_MODE_FIRMWARE_SMA: /* falltrough */ case DRX_UIO_MODE_FIRMWARE_SAW: /* falltrough */ case DRX_UIO_MODE_READWRITE: - extAttr->uioSmaTxMode = UIOCfg->mode; + ext_attr->uio_sma_tx_mode = uio_cfg->mode; break; case DRX_UIO_MODE_DISABLE: - extAttr->uioSmaTxMode = UIOCfg->mode; + ext_attr->uio_sma_tx_mode = uio_cfg->mode; /* pad configuration register is set 0 - input mode */ - WR16(demod->myI2CDevAddr, SIO_PDR_SMA_TX_CFG__A, 0); + WR16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0); break; default: return DRX_STS_INVALID_ARG; - } /* switch ( UIOCfg->mode ) */ + } /* switch ( uio_cfg->mode ) */ break; /*====================================================================*/ case DRX_UIO2: /* DRX_UIO2: SMA_RX UIO-2 */ - if (extAttr->hasSMARX != true) + if (ext_attr->has_smarx != true) return DRX_STS_ERROR; - switch (UIOCfg->mode) { + switch (uio_cfg->mode) { case DRX_UIO_MODE_FIRMWARE0: /* falltrough */ case DRX_UIO_MODE_READWRITE: - extAttr->uioSmaRxMode = UIOCfg->mode; + ext_attr->uio_sma_rx_mode = uio_cfg->mode; break; case DRX_UIO_MODE_DISABLE: - extAttr->uioSmaRxMode = UIOCfg->mode; + ext_attr->uio_sma_rx_mode = uio_cfg->mode; /* pad configuration register is set 0 - input mode */ - WR16(demod->myI2CDevAddr, SIO_PDR_SMA_RX_CFG__A, 0); + WR16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, 0); break; default: return DRX_STS_INVALID_ARG; break; - } /* switch ( UIOCfg->mode ) */ + } /* switch ( uio_cfg->mode ) */ break; /*====================================================================*/ case DRX_UIO3: /* DRX_UIO3: GPIO UIO-3 */ - if (extAttr->hasGPIO != true) + if (ext_attr->has_gpio != true) return DRX_STS_ERROR; - switch (UIOCfg->mode) { + switch (uio_cfg->mode) { case DRX_UIO_MODE_FIRMWARE0: /* falltrough */ case DRX_UIO_MODE_READWRITE: - extAttr->uioGPIOMode = UIOCfg->mode; + ext_attr->uio_gpio_mode = uio_cfg->mode; break; case DRX_UIO_MODE_DISABLE: - extAttr->uioGPIOMode = UIOCfg->mode; + ext_attr->uio_gpio_mode = uio_cfg->mode; /* pad configuration register is set 0 - input mode */ - WR16(demod->myI2CDevAddr, SIO_PDR_GPIO_CFG__A, 0); + WR16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, 0); break; default: return DRX_STS_INVALID_ARG; break; - } /* switch ( UIOCfg->mode ) */ + } /* switch ( uio_cfg->mode ) */ break; /*====================================================================*/ case DRX_UIO4: /* DRX_UIO4: IRQN UIO-4 */ - if (extAttr->hasIRQN != true) + if (ext_attr->has_irqn != true) return DRX_STS_ERROR; - switch (UIOCfg->mode) { + switch (uio_cfg->mode) { case DRX_UIO_MODE_READWRITE: - extAttr->uioIRQNMode = UIOCfg->mode; + ext_attr->uio_irqn_mode = uio_cfg->mode; break; case DRX_UIO_MODE_DISABLE: /* pad configuration register is set 0 - input mode */ - WR16(demod->myI2CDevAddr, SIO_PDR_IRQN_CFG__A, 0); - extAttr->uioIRQNMode = UIOCfg->mode; + WR16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, 0); + ext_attr->uio_irqn_mode = uio_cfg->mode; break; case DRX_UIO_MODE_FIRMWARE0: /* falltrough */ default: return DRX_STS_INVALID_ARG; break; - } /* switch ( UIOCfg->mode ) */ + } /* switch ( uio_cfg->mode ) */ break; /*====================================================================*/ default: return DRX_STS_INVALID_ARG; - } /* switch ( UIOCfg->uio ) */ + } /* switch ( uio_cfg->uio ) */ /* Write magic word to disable pdr reg write */ - WR16(demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, 0x0000); + WR16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000); return (DRX_STS_OK); rw_error: @@ -3481,188 +3481,188 @@ rw_error: /*============================================================================*/ /** -* \fn int CtrlGetUIOCfg() +* \fn int CtrlGetuio_cfg() * \brief Get modus oprandi UIO. * \param demod Pointer to demodulator instance. -* \param UIOCfg Pointer to a configuration setting for a certain UIO. +* \param uio_cfg Pointer to a configuration setting for a certain UIO. * \return int. */ -static int CtrlGetUIOCfg(pDRXDemodInstance_t demod, pDRXUIOCfg_t UIOCfg) +static int CtrlGetuio_cfg(pdrx_demod_instance_t demod, pdrxuio_cfg_t uio_cfg) { - pDRXJData_t extAttr = (pDRXJData_t) NULL; - pDRXUIOMode_t UIOMode[4] = { NULL }; - bool *UIOAvailable[4] = { NULL }; + pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; + pdrxuio_mode_t uio_mode[4] = { NULL }; + bool *uio_available[4] = { NULL }; - extAttr = demod->myExtAttr; + ext_attr = demod->my_ext_attr; - UIOMode[DRX_UIO1] = &extAttr->uioSmaTxMode; - UIOMode[DRX_UIO2] = &extAttr->uioSmaRxMode; - UIOMode[DRX_UIO3] = &extAttr->uioGPIOMode; - UIOMode[DRX_UIO4] = &extAttr->uioIRQNMode; + uio_mode[DRX_UIO1] = &ext_attr->uio_sma_tx_mode; + uio_mode[DRX_UIO2] = &ext_attr->uio_sma_rx_mode; + uio_mode[DRX_UIO3] = &ext_attr->uio_gpio_mode; + uio_mode[DRX_UIO4] = &ext_attr->uio_irqn_mode; - UIOAvailable[DRX_UIO1] = &extAttr->hasSMATX; - UIOAvailable[DRX_UIO2] = &extAttr->hasSMARX; - UIOAvailable[DRX_UIO3] = &extAttr->hasGPIO; - UIOAvailable[DRX_UIO4] = &extAttr->hasIRQN; + uio_available[DRX_UIO1] = &ext_attr->has_smatx; + uio_available[DRX_UIO2] = &ext_attr->has_smarx; + uio_available[DRX_UIO3] = &ext_attr->has_gpio; + uio_available[DRX_UIO4] = &ext_attr->has_irqn; - if (UIOCfg == NULL) { + if (uio_cfg == NULL) { return DRX_STS_INVALID_ARG; } - if ((UIOCfg->uio > DRX_UIO4) || (UIOCfg->uio < DRX_UIO1)) { + if ((uio_cfg->uio > DRX_UIO4) || (uio_cfg->uio < DRX_UIO1)) { return DRX_STS_INVALID_ARG; } - if (*UIOAvailable[UIOCfg->uio] == false) { + if (*uio_available[uio_cfg->uio] == false) { return DRX_STS_ERROR; } - UIOCfg->mode = *UIOMode[UIOCfg->uio]; + uio_cfg->mode = *uio_mode[uio_cfg->uio]; return DRX_STS_OK; } /** -* \fn int CtrlUIOWrite() +* \fn int ctrl_uio_write() * \brief Write to a UIO. * \param demod Pointer to demodulator instance. -* \param UIOData Pointer to data container for a certain UIO. +* \param uio_data Pointer to data container for a certain UIO. * \return int. */ static int -CtrlUIOWrite(pDRXDemodInstance_t demod, pDRXUIOData_t UIOData) +ctrl_uio_write(pdrx_demod_instance_t demod, pdrxuio_data_t uio_data) { - pDRXJData_t extAttr = (pDRXJData_t) (NULL); - u16 pinCfgValue = 0; + pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); + u16 pin_cfg_value = 0; u16 value = 0; - if ((UIOData == NULL) || (demod == NULL)) { + if ((uio_data == NULL) || (demod == NULL)) { return DRX_STS_INVALID_ARG; } - extAttr = (pDRXJData_t) demod->myExtAttr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* Write magic word to enable pdr reg write */ - WR16(demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); - switch (UIOData->uio) { + WR16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); + switch (uio_data->uio) { /*====================================================================*/ case DRX_UIO1: /* DRX_UIO1: SMA_TX UIO-1 */ - if (extAttr->hasSMATX != true) + if (ext_attr->has_smatx != true) return DRX_STS_ERROR; - if ((extAttr->uioSmaTxMode != DRX_UIO_MODE_READWRITE) - && (extAttr->uioSmaTxMode != DRX_UIO_MODE_FIRMWARE_SAW)) { + if ((ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_READWRITE) + && (ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_FIRMWARE_SAW)) { return DRX_STS_ERROR; } - pinCfgValue = 0; + pin_cfg_value = 0; /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ - pinCfgValue |= 0x0113; + pin_cfg_value |= 0x0113; /* io_pad_cfg_mode output mode is drive always */ /* io_pad_cfg_drive is set to power 2 (23 mA) */ /* write to io pad configuration register - output mode */ - WR16(demod->myI2CDevAddr, SIO_PDR_SMA_TX_CFG__A, pinCfgValue); + WR16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, pin_cfg_value); /* use corresponding bit in io data output registar */ - RR16(demod->myI2CDevAddr, SIO_PDR_UIO_OUT_LO__A, &value); - if (UIOData->value == false) { + RR16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value); + if (uio_data->value == false) { value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */ } else { value |= 0x8000; /* write one to 15th bit - 1st UIO */ } /* write back to io data output register */ - WR16(demod->myI2CDevAddr, SIO_PDR_UIO_OUT_LO__A, value); + WR16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value); break; /*======================================================================*/ case DRX_UIO2: /* DRX_UIO2: SMA_RX UIO-2 */ - if (extAttr->hasSMARX != true) + if (ext_attr->has_smarx != true) return DRX_STS_ERROR; - if (extAttr->uioSmaRxMode != DRX_UIO_MODE_READWRITE) { + if (ext_attr->uio_sma_rx_mode != DRX_UIO_MODE_READWRITE) { return DRX_STS_ERROR; } - pinCfgValue = 0; + pin_cfg_value = 0; /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ - pinCfgValue |= 0x0113; + pin_cfg_value |= 0x0113; /* io_pad_cfg_mode output mode is drive always */ /* io_pad_cfg_drive is set to power 2 (23 mA) */ /* write to io pad configuration register - output mode */ - WR16(demod->myI2CDevAddr, SIO_PDR_SMA_RX_CFG__A, pinCfgValue); + WR16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, pin_cfg_value); /* use corresponding bit in io data output registar */ - RR16(demod->myI2CDevAddr, SIO_PDR_UIO_OUT_LO__A, &value); - if (UIOData->value == false) { + RR16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value); + if (uio_data->value == false) { value &= 0xBFFF; /* write zero to 14th bit - 2nd UIO */ } else { value |= 0x4000; /* write one to 14th bit - 2nd UIO */ } /* write back to io data output register */ - WR16(demod->myI2CDevAddr, SIO_PDR_UIO_OUT_LO__A, value); + WR16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value); break; /*====================================================================*/ case DRX_UIO3: /* DRX_UIO3: ASEL UIO-3 */ - if (extAttr->hasGPIO != true) + if (ext_attr->has_gpio != true) return DRX_STS_ERROR; - if (extAttr->uioGPIOMode != DRX_UIO_MODE_READWRITE) { + if (ext_attr->uio_gpio_mode != DRX_UIO_MODE_READWRITE) { return DRX_STS_ERROR; } - pinCfgValue = 0; + pin_cfg_value = 0; /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ - pinCfgValue |= 0x0113; + pin_cfg_value |= 0x0113; /* io_pad_cfg_mode output mode is drive always */ /* io_pad_cfg_drive is set to power 2 (23 mA) */ /* write to io pad configuration register - output mode */ - WR16(demod->myI2CDevAddr, SIO_PDR_GPIO_CFG__A, pinCfgValue); + WR16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, pin_cfg_value); /* use corresponding bit in io data output registar */ - RR16(demod->myI2CDevAddr, SIO_PDR_UIO_OUT_HI__A, &value); - if (UIOData->value == false) { + RR16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, &value); + if (uio_data->value == false) { value &= 0xFFFB; /* write zero to 2nd bit - 3rd UIO */ } else { value |= 0x0004; /* write one to 2nd bit - 3rd UIO */ } /* write back to io data output register */ - WR16(demod->myI2CDevAddr, SIO_PDR_UIO_OUT_HI__A, value); + WR16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, value); break; /*=====================================================================*/ case DRX_UIO4: /* DRX_UIO4: IRQN UIO-4 */ - if (extAttr->hasIRQN != true) + if (ext_attr->has_irqn != true) return DRX_STS_ERROR; - if (extAttr->uioIRQNMode != DRX_UIO_MODE_READWRITE) { + if (ext_attr->uio_irqn_mode != DRX_UIO_MODE_READWRITE) { return DRX_STS_ERROR; } - pinCfgValue = 0; + pin_cfg_value = 0; /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ - pinCfgValue |= 0x0113; + pin_cfg_value |= 0x0113; /* io_pad_cfg_mode output mode is drive always */ /* io_pad_cfg_drive is set to power 2 (23 mA) */ /* write to io pad configuration register - output mode */ - WR16(demod->myI2CDevAddr, SIO_PDR_IRQN_CFG__A, pinCfgValue); + WR16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, pin_cfg_value); /* use corresponding bit in io data output registar */ - RR16(demod->myI2CDevAddr, SIO_PDR_UIO_OUT_LO__A, &value); - if (UIOData->value == false) { + RR16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value); + if (uio_data->value == false) { value &= 0xEFFF; /* write zero to 12th bit - 4th UIO */ } else { value |= 0x1000; /* write one to 12th bit - 4th UIO */ } /* write back to io data output register */ - WR16(demod->myI2CDevAddr, SIO_PDR_UIO_OUT_LO__A, value); + WR16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value); break; /*=====================================================================*/ default: return DRX_STS_INVALID_ARG; - } /* switch ( UIOData->uio ) */ + } /* switch ( uio_data->uio ) */ /* Write magic word to disable pdr reg write */ - WR16(demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, 0x0000); + WR16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000); return (DRX_STS_OK); rw_error: @@ -3670,137 +3670,137 @@ rw_error: } /** -*\fn int CtrlUIORead +*\fn int ctrl_uio_read *\brief Read from a UIO. * \param demod Pointer to demodulator instance. -* \param UIOData Pointer to data container for a certain UIO. +* \param uio_data Pointer to data container for a certain UIO. * \return int. */ -static int CtrlUIORead(pDRXDemodInstance_t demod, pDRXUIOData_t UIOData) +static int ctrl_uio_read(pdrx_demod_instance_t demod, pdrxuio_data_t uio_data) { - pDRXJData_t extAttr = (pDRXJData_t) (NULL); - u16 pinCfgValue = 0; + pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); + u16 pin_cfg_value = 0; u16 value = 0; - if ((UIOData == NULL) || (demod == NULL)) { + if ((uio_data == NULL) || (demod == NULL)) { return DRX_STS_INVALID_ARG; } - extAttr = (pDRXJData_t) demod->myExtAttr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* Write magic word to enable pdr reg write */ - WR16(demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); - switch (UIOData->uio) { + WR16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); + switch (uio_data->uio) { /*====================================================================*/ case DRX_UIO1: /* DRX_UIO1: SMA_TX UIO-1 */ - if (extAttr->hasSMATX != true) + if (ext_attr->has_smatx != true) return DRX_STS_ERROR; - if (extAttr->uioSmaTxMode != DRX_UIO_MODE_READWRITE) { + if (ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_READWRITE) { return DRX_STS_ERROR; } - pinCfgValue = 0; + pin_cfg_value = 0; /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ - pinCfgValue |= 0x0110; + pin_cfg_value |= 0x0110; /* io_pad_cfg_mode output mode is drive always */ /* io_pad_cfg_drive is set to power 2 (23 mA) */ /* write to io pad configuration register - input mode */ - WR16(demod->myI2CDevAddr, SIO_PDR_SMA_TX_CFG__A, pinCfgValue); + WR16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, pin_cfg_value); - RR16(demod->myI2CDevAddr, SIO_PDR_UIO_IN_LO__A, &value); + RR16(demod->my_i2c_dev_addr, SIO_PDR_UIO_IN_LO__A, &value); if ((value & 0x8000) != 0) { /* check 15th bit - 1st UIO */ - UIOData->value = true; + uio_data->value = true; } else { - UIOData->value = false; + uio_data->value = false; } break; /*======================================================================*/ case DRX_UIO2: /* DRX_UIO2: SMA_RX UIO-2 */ - if (extAttr->hasSMARX != true) + if (ext_attr->has_smarx != true) return DRX_STS_ERROR; - if (extAttr->uioSmaRxMode != DRX_UIO_MODE_READWRITE) { + if (ext_attr->uio_sma_rx_mode != DRX_UIO_MODE_READWRITE) { return DRX_STS_ERROR; } - pinCfgValue = 0; + pin_cfg_value = 0; /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ - pinCfgValue |= 0x0110; + pin_cfg_value |= 0x0110; /* io_pad_cfg_mode output mode is drive always */ /* io_pad_cfg_drive is set to power 2 (23 mA) */ /* write to io pad configuration register - input mode */ - WR16(demod->myI2CDevAddr, SIO_PDR_SMA_RX_CFG__A, pinCfgValue); + WR16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, pin_cfg_value); - RR16(demod->myI2CDevAddr, SIO_PDR_UIO_IN_LO__A, &value); + RR16(demod->my_i2c_dev_addr, SIO_PDR_UIO_IN_LO__A, &value); if ((value & 0x4000) != 0) { /* check 14th bit - 2nd UIO */ - UIOData->value = true; + uio_data->value = true; } else { - UIOData->value = false; + uio_data->value = false; } break; /*=====================================================================*/ case DRX_UIO3: /* DRX_UIO3: GPIO UIO-3 */ - if (extAttr->hasGPIO != true) + if (ext_attr->has_gpio != true) return DRX_STS_ERROR; - if (extAttr->uioGPIOMode != DRX_UIO_MODE_READWRITE) { + if (ext_attr->uio_gpio_mode != DRX_UIO_MODE_READWRITE) { return DRX_STS_ERROR; } - pinCfgValue = 0; + pin_cfg_value = 0; /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ - pinCfgValue |= 0x0110; + pin_cfg_value |= 0x0110; /* io_pad_cfg_mode output mode is drive always */ /* io_pad_cfg_drive is set to power 2 (23 mA) */ /* write to io pad configuration register - input mode */ - WR16(demod->myI2CDevAddr, SIO_PDR_GPIO_CFG__A, pinCfgValue); + WR16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, pin_cfg_value); /* read io input data registar */ - RR16(demod->myI2CDevAddr, SIO_PDR_UIO_IN_HI__A, &value); + RR16(demod->my_i2c_dev_addr, SIO_PDR_UIO_IN_HI__A, &value); if ((value & 0x0004) != 0) { /* check 2nd bit - 3rd UIO */ - UIOData->value = true; + uio_data->value = true; } else { - UIOData->value = false; + uio_data->value = false; } break; /*=====================================================================*/ case DRX_UIO4: /* DRX_UIO4: IRQN UIO-4 */ - if (extAttr->hasIRQN != true) + if (ext_attr->has_irqn != true) return DRX_STS_ERROR; - if (extAttr->uioIRQNMode != DRX_UIO_MODE_READWRITE) { + if (ext_attr->uio_irqn_mode != DRX_UIO_MODE_READWRITE) { return DRX_STS_ERROR; } - pinCfgValue = 0; + pin_cfg_value = 0; /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ - pinCfgValue |= 0x0110; + pin_cfg_value |= 0x0110; /* io_pad_cfg_mode output mode is drive always */ /* io_pad_cfg_drive is set to power 2 (23 mA) */ /* write to io pad configuration register - input mode */ - WR16(demod->myI2CDevAddr, SIO_PDR_IRQN_CFG__A, pinCfgValue); + WR16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, pin_cfg_value); /* read io input data registar */ - RR16(demod->myI2CDevAddr, SIO_PDR_UIO_IN_LO__A, &value); + RR16(demod->my_i2c_dev_addr, SIO_PDR_UIO_IN_LO__A, &value); if ((value & 0x1000) != 0) { /* check 12th bit - 4th UIO */ - UIOData->value = true; + uio_data->value = true; } else { - UIOData->value = false; + uio_data->value = false; } break; /*====================================================================*/ default: return DRX_STS_INVALID_ARG; - } /* switch ( UIOData->uio ) */ + } /* switch ( uio_data->uio ) */ /* Write magic word to disable pdr reg write */ - WR16(demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, 0x0000); + WR16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000); return (DRX_STS_OK); rw_error: @@ -3815,33 +3815,33 @@ rw_error: /* I2C Bridge Functions - begin */ /*----------------------------------------------------------------------------*/ /** -* \fn int CtrlI2CBridge() +* \fn int ctrl_i2c_bridge() * \brief Open or close the I2C switch to tuner. * \param demod Pointer to demodulator instance. -* \param bridgeClosed Pointer to bool indication if bridge is closed not. +* \param bridge_closed Pointer to bool indication if bridge is closed not. * \return int. */ static int -CtrlI2CBridge(pDRXDemodInstance_t demod, bool *bridgeClosed) +ctrl_i2c_bridge(pdrx_demod_instance_t demod, bool *bridge_closed) { - DRXJHiCmd_t hiCmd; + drxj_hi_cmd_t hi_cmd; u16 result = 0; /* check arguments */ - if (bridgeClosed == NULL) { + if (bridge_closed == NULL) { return (DRX_STS_INVALID_ARG); } - hiCmd.cmd = SIO_HI_RA_RAM_CMD_BRDCTRL; - hiCmd.param1 = SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY; - if (*bridgeClosed == true) { - hiCmd.param2 = SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED; + hi_cmd.cmd = SIO_HI_RA_RAM_CMD_BRDCTRL; + hi_cmd.param1 = SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY; + if (*bridge_closed == true) { + hi_cmd.param2 = SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED; } else { - hiCmd.param2 = SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN; + hi_cmd.param2 = SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN; } - return HICommand(demod->myI2CDevAddr, &hiCmd, &result); + return hi_command(demod->my_i2c_dev_addr, &hi_cmd, &result); } /*----------------------------------------------------------------------------*/ @@ -3852,42 +3852,42 @@ CtrlI2CBridge(pDRXDemodInstance_t demod, bool *bridgeClosed) /* Smart antenna Functions - begin */ /*----------------------------------------------------------------------------*/ /** -* \fn int SmartAntInit() +* \fn int smart_ant_init() * \brief Initialize Smart Antenna. -* \param pointer to DRXDemodInstance_t. +* \param pointer to drx_demod_instance_t. * \return int. * */ -static int SmartAntInit(pDRXDemodInstance_t demod) +static int smart_ant_init(pdrx_demod_instance_t demod) { u16 data = 0; - pDRXJData_t extAttr = NULL; - struct i2c_device_addr *devAddr = NULL; - DRXUIOCfg_t UIOCfg = { DRX_UIO1, DRX_UIO_MODE_FIRMWARE_SMA }; + pdrxj_data_t ext_attr = NULL; + struct i2c_device_addr *dev_addr = NULL; + drxuio_cfg_t uio_cfg = { DRX_UIO1, DRX_UIO_MODE_FIRMWARE_SMA }; - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* Write magic word to enable pdr reg write */ - WR16(demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); + WR16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); /* init smart antenna */ - RR16(devAddr, SIO_SA_TX_COMMAND__A, &data); - if (extAttr->smartAntInverted) - WR16(devAddr, SIO_SA_TX_COMMAND__A, + RR16(dev_addr, SIO_SA_TX_COMMAND__A, &data); + if (ext_attr->smart_ant_inverted) + WR16(dev_addr, SIO_SA_TX_COMMAND__A, (data | SIO_SA_TX_COMMAND_TX_INVERT__M) | SIO_SA_TX_COMMAND_TX_ENABLE__M); else - WR16(devAddr, SIO_SA_TX_COMMAND__A, + WR16(dev_addr, SIO_SA_TX_COMMAND__A, (data & (~SIO_SA_TX_COMMAND_TX_INVERT__M)) | SIO_SA_TX_COMMAND_TX_ENABLE__M); /* config SMA_TX pin to smart antenna mode */ - CHK_ERROR(CtrlSetUIOCfg(demod, &UIOCfg)); - WR16(demod->myI2CDevAddr, SIO_PDR_SMA_TX_CFG__A, 0x13); - WR16(demod->myI2CDevAddr, SIO_PDR_SMA_TX_GPIO_FNC__A, 0x03); + CHK_ERROR(ctrl_set_uio_cfg(demod, &uio_cfg)); + WR16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0x13); + WR16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_GPIO_FNC__A, 0x03); /* Write magic word to disable pdr reg write */ - WR16(demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, 0x0000); + WR16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000); return (DRX_STS_OK); rw_error: @@ -3895,50 +3895,50 @@ rw_error: } /** -* \fn int CtrlSetCfgSmartAnt() +* \fn int ctrl_set_cfg_smart_ant() * \brief Set Smart Antenna. -* \param pointer to DRXJCfgSmartAnt_t. +* \param pointer to drxj_cfg_smart_ant_t. * \return int. * */ static int -CtrlSetCfgSmartAnt(pDRXDemodInstance_t demod, pDRXJCfgSmartAnt_t smartAnt) +ctrl_set_cfg_smart_ant(pdrx_demod_instance_t demod, p_drxj_cfg_smart_ant_t smart_ant) { - pDRXJData_t extAttr = NULL; - struct i2c_device_addr *devAddr = NULL; + pdrxj_data_t ext_attr = NULL; + struct i2c_device_addr *dev_addr = NULL; u16 data = 0; - u32 startTime = 0; - static bool bitInverted; + u32 start_time = 0; + static bool bit_inverted; - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* check arguments */ - if (smartAnt == NULL) { + if (smart_ant == NULL) { return (DRX_STS_INVALID_ARG); } - if (bitInverted != extAttr->smartAntInverted - || extAttr->uioSmaTxMode != DRX_UIO_MODE_FIRMWARE_SMA) { - CHK_ERROR(SmartAntInit(demod)); - bitInverted = extAttr->smartAntInverted; + if (bit_inverted != ext_attr->smart_ant_inverted + || ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_FIRMWARE_SMA) { + CHK_ERROR(smart_ant_init(demod)); + bit_inverted = ext_attr->smart_ant_inverted; } /* Write magic word to enable pdr reg write */ - WR16(demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); + WR16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); - switch (smartAnt->io) { + switch (smart_ant->io) { case DRXJ_SMT_ANT_OUTPUT: /* enable Tx if Mode B (input) is supported */ /* - RR16( devAddr, SIO_SA_TX_COMMAND__A, &data ); - WR16( devAddr, SIO_SA_TX_COMMAND__A, data | SIO_SA_TX_COMMAND_TX_ENABLE__M ); + RR16( dev_addr, SIO_SA_TX_COMMAND__A, &data ); + WR16( dev_addr, SIO_SA_TX_COMMAND__A, data | SIO_SA_TX_COMMAND_TX_ENABLE__M ); */ - startTime = DRXBSP_HST_Clock(); + start_time = drxbsp_hst_clock(); do { - RR16(devAddr, SIO_SA_TX_STATUS__A, &data); + RR16(dev_addr, SIO_SA_TX_STATUS__A, &data); } while ((data & SIO_SA_TX_STATUS_BUSY__M) - && ((DRXBSP_HST_Clock() - startTime) < + && ((drxbsp_hst_clock() - start_time) < DRXJ_MAX_WAITTIME)); if (data & SIO_SA_TX_STATUS_BUSY__M) { @@ -3946,75 +3946,75 @@ CtrlSetCfgSmartAnt(pDRXDemodInstance_t demod, pDRXJCfgSmartAnt_t smartAnt) } /* write to smart antenna configuration register */ - WR16(devAddr, SIO_SA_TX_DATA0__A, 0x9200 - | ((smartAnt->ctrlData & 0x0001) << 8) - | ((smartAnt->ctrlData & 0x0002) << 10) - | ((smartAnt->ctrlData & 0x0004) << 12) + WR16(dev_addr, SIO_SA_TX_DATA0__A, 0x9200 + | ((smart_ant->ctrl_data & 0x0001) << 8) + | ((smart_ant->ctrl_data & 0x0002) << 10) + | ((smart_ant->ctrl_data & 0x0004) << 12) ); - WR16(devAddr, SIO_SA_TX_DATA1__A, 0x4924 - | ((smartAnt->ctrlData & 0x0008) >> 2) - | ((smartAnt->ctrlData & 0x0010)) - | ((smartAnt->ctrlData & 0x0020) << 2) - | ((smartAnt->ctrlData & 0x0040) << 4) - | ((smartAnt->ctrlData & 0x0080) << 6) + WR16(dev_addr, SIO_SA_TX_DATA1__A, 0x4924 + | ((smart_ant->ctrl_data & 0x0008) >> 2) + | ((smart_ant->ctrl_data & 0x0010)) + | ((smart_ant->ctrl_data & 0x0020) << 2) + | ((smart_ant->ctrl_data & 0x0040) << 4) + | ((smart_ant->ctrl_data & 0x0080) << 6) ); - WR16(devAddr, SIO_SA_TX_DATA2__A, 0x2492 - | ((smartAnt->ctrlData & 0x0100) >> 8) - | ((smartAnt->ctrlData & 0x0200) >> 6) - | ((smartAnt->ctrlData & 0x0400) >> 4) - | ((smartAnt->ctrlData & 0x0800) >> 2) - | ((smartAnt->ctrlData & 0x1000)) - | ((smartAnt->ctrlData & 0x2000) << 2) + WR16(dev_addr, SIO_SA_TX_DATA2__A, 0x2492 + | ((smart_ant->ctrl_data & 0x0100) >> 8) + | ((smart_ant->ctrl_data & 0x0200) >> 6) + | ((smart_ant->ctrl_data & 0x0400) >> 4) + | ((smart_ant->ctrl_data & 0x0800) >> 2) + | ((smart_ant->ctrl_data & 0x1000)) + | ((smart_ant->ctrl_data & 0x2000) << 2) ); - WR16(devAddr, SIO_SA_TX_DATA3__A, 0xff8d); + WR16(dev_addr, SIO_SA_TX_DATA3__A, 0xff8d); /* trigger the sending */ - WR16(devAddr, SIO_SA_TX_LENGTH__A, 56); + WR16(dev_addr, SIO_SA_TX_LENGTH__A, 56); break; case DRXJ_SMT_ANT_INPUT: /* disable Tx if Mode B (input) is supported */ /* - RR16( devAddr, SIO_SA_TX_COMMAND__A, &data ); - WR16( devAddr, SIO_SA_TX_COMMAND__A, data & (~SIO_SA_TX_COMMAND_TX_ENABLE__M) ); + RR16( dev_addr, SIO_SA_TX_COMMAND__A, &data ); + WR16( dev_addr, SIO_SA_TX_COMMAND__A, data & (~SIO_SA_TX_COMMAND_TX_ENABLE__M) ); */ default: return (DRX_STS_INVALID_ARG); } /* Write magic word to enable pdr reg write */ - WR16(demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, 0x0000); + WR16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000); return (DRX_STS_OK); rw_error: return (DRX_STS_ERROR); } -static int SCUCommand(struct i2c_device_addr *devAddr, pDRXJSCUCmd_t cmd) +static int scu_command(struct i2c_device_addr *dev_addr, p_drxjscu_cmd_t cmd) { - u16 curCmd = 0; - u32 startTime = 0; + u16 cur_cmd = 0; + u32 start_time = 0; /* Check param */ if (cmd == NULL) return (DRX_STS_INVALID_ARG); /* Wait until SCU command interface is ready to receive command */ - RR16(devAddr, SCU_RAM_COMMAND__A, &curCmd); - if (curCmd != DRX_SCU_READY) { + RR16(dev_addr, SCU_RAM_COMMAND__A, &cur_cmd); + if (cur_cmd != DRX_SCU_READY) { return (DRX_STS_ERROR); } - switch (cmd->parameterLen) { + switch (cmd->parameter_len) { case 5: - WR16(devAddr, SCU_RAM_PARAM_4__A, *(cmd->parameter + 4)); /* fallthrough */ + WR16(dev_addr, SCU_RAM_PARAM_4__A, *(cmd->parameter + 4)); /* fallthrough */ case 4: - WR16(devAddr, SCU_RAM_PARAM_3__A, *(cmd->parameter + 3)); /* fallthrough */ + WR16(dev_addr, SCU_RAM_PARAM_3__A, *(cmd->parameter + 3)); /* fallthrough */ case 3: - WR16(devAddr, SCU_RAM_PARAM_2__A, *(cmd->parameter + 2)); /* fallthrough */ + WR16(dev_addr, SCU_RAM_PARAM_2__A, *(cmd->parameter + 2)); /* fallthrough */ case 2: - WR16(devAddr, SCU_RAM_PARAM_1__A, *(cmd->parameter + 1)); /* fallthrough */ + WR16(dev_addr, SCU_RAM_PARAM_1__A, *(cmd->parameter + 1)); /* fallthrough */ case 1: - WR16(devAddr, SCU_RAM_PARAM_0__A, *(cmd->parameter + 0)); /* fallthrough */ + WR16(dev_addr, SCU_RAM_PARAM_0__A, *(cmd->parameter + 0)); /* fallthrough */ case 0: /* do nothing */ break; @@ -4022,32 +4022,32 @@ static int SCUCommand(struct i2c_device_addr *devAddr, pDRXJSCUCmd_t cmd) /* this number of parameters is not supported */ return (DRX_STS_ERROR); } - WR16(devAddr, SCU_RAM_COMMAND__A, cmd->command); + WR16(dev_addr, SCU_RAM_COMMAND__A, cmd->command); /* Wait until SCU has processed command */ - startTime = DRXBSP_HST_Clock(); + start_time = drxbsp_hst_clock(); do { - RR16(devAddr, SCU_RAM_COMMAND__A, &curCmd); - } while (!(curCmd == DRX_SCU_READY) - && ((DRXBSP_HST_Clock() - startTime) < DRXJ_MAX_WAITTIME)); + RR16(dev_addr, SCU_RAM_COMMAND__A, &cur_cmd); + } while (!(cur_cmd == DRX_SCU_READY) + && ((drxbsp_hst_clock() - start_time) < DRXJ_MAX_WAITTIME)); - if (curCmd != DRX_SCU_READY) { + if (cur_cmd != DRX_SCU_READY) { return (DRX_STS_ERROR); } /* read results */ - if ((cmd->resultLen > 0) && (cmd->result != NULL)) { + if ((cmd->result_len > 0) && (cmd->result != NULL)) { s16 err; - switch (cmd->resultLen) { + switch (cmd->result_len) { case 4: - RR16(devAddr, SCU_RAM_PARAM_3__A, cmd->result + 3); /* fallthrough */ + RR16(dev_addr, SCU_RAM_PARAM_3__A, cmd->result + 3); /* fallthrough */ case 3: - RR16(devAddr, SCU_RAM_PARAM_2__A, cmd->result + 2); /* fallthrough */ + RR16(dev_addr, SCU_RAM_PARAM_2__A, cmd->result + 2); /* fallthrough */ case 2: - RR16(devAddr, SCU_RAM_PARAM_1__A, cmd->result + 1); /* fallthrough */ + RR16(dev_addr, SCU_RAM_PARAM_1__A, cmd->result + 1); /* fallthrough */ case 1: - RR16(devAddr, SCU_RAM_PARAM_0__A, cmd->result + 0); /* fallthrough */ + RR16(dev_addr, SCU_RAM_PARAM_0__A, cmd->result + 0); /* fallthrough */ case 0: /* do nothing */ break; @@ -4084,7 +4084,7 @@ rw_error: /** * \fn int DRXJ_DAP_SCUAtomicReadWriteBlock() * \brief Basic access routine for SCU atomic read or write access -* \param devAddr pointer to i2c dev address +* \param dev_addr pointer to i2c dev address * \param addr destination/source address * \param datasize size of data buffer in bytes * \param data pointer to data buffer @@ -4095,50 +4095,50 @@ rw_error: */ #define ADDR_AT_SCU_SPACE(x) ((x - 0x82E000) * 2) static -int DRXJ_DAP_SCU_AtomicReadWriteBlock(struct i2c_device_addr *devAddr, DRXaddr_t addr, u16 datasize, /* max 30 bytes because the limit of SCU parameter */ - u8 *data, bool readFlag) +int drxj_dap_scu_atomic_read_write_block(struct i2c_device_addr *dev_addr, dr_xaddr_t addr, u16 datasize, /* max 30 bytes because the limit of SCU parameter */ + u8 *data, bool read_flag) { - DRXJSCUCmd_t scuCmd; - u16 setParamParameters[15]; - u16 cmdResult[15]; + drxjscu_cmd_t scu_cmd; + u16 set_param_parameters[15]; + u16 cmd_result[15]; /* Parameter check */ if ((data == NULL) || - (devAddr == NULL) || ((datasize % 2) != 0) || ((datasize / 2) > 16) + (dev_addr == NULL) || ((datasize % 2) != 0) || ((datasize / 2) > 16) ) { return (DRX_STS_INVALID_ARG); } - setParamParameters[1] = (u16) ADDR_AT_SCU_SPACE(addr); - if (readFlag) { /* read */ - setParamParameters[0] = ((~(0x0080)) & datasize); - scuCmd.parameterLen = 2; - scuCmd.resultLen = datasize / 2 + 2; + set_param_parameters[1] = (u16) ADDR_AT_SCU_SPACE(addr); + if (read_flag) { /* read */ + set_param_parameters[0] = ((~(0x0080)) & datasize); + scu_cmd.parameter_len = 2; + scu_cmd.result_len = datasize / 2 + 2; } else { int i = 0; - setParamParameters[0] = 0x0080 | datasize; + set_param_parameters[0] = 0x0080 | datasize; for (i = 0; i < (datasize / 2); i++) { - setParamParameters[i + 2] = + set_param_parameters[i + 2] = (data[2 * i] | (data[(2 * i) + 1] << 8)); } - scuCmd.parameterLen = datasize / 2 + 2; - scuCmd.resultLen = 1; + scu_cmd.parameter_len = datasize / 2 + 2; + scu_cmd.result_len = 1; } - scuCmd.command = + scu_cmd.command = SCU_RAM_COMMAND_STANDARD_TOP | SCU_RAM_COMMAND_CMD_AUX_SCU_ATOMIC_ACCESS; - scuCmd.result = cmdResult; - scuCmd.parameter = setParamParameters; - CHK_ERROR(SCUCommand(devAddr, &scuCmd)); + scu_cmd.result = cmd_result; + scu_cmd.parameter = set_param_parameters; + CHK_ERROR(scu_command(dev_addr, &scu_cmd)); - if (readFlag == true) { + if (read_flag == true) { int i = 0; /* read data from buffer */ for (i = 0; i < (datasize / 2); i++) { - data[2 * i] = (u8) (scuCmd.result[i + 2] & 0xFF); - data[(2 * i) + 1] = (u8) (scuCmd.result[i + 2] >> 8); + data[2 * i] = (u8) (scu_cmd.result[i + 2] & 0xFF); + data[(2 * i) + 1] = (u8) (scu_cmd.result[i + 2] >> 8); } } @@ -4156,9 +4156,9 @@ rw_error: * \brief Atomic read of 16 bits words */ static -int DRXJ_DAP_SCU_AtomicReadReg16(struct i2c_device_addr *devAddr, - DRXaddr_t addr, - u16 *data, DRXflags_t flags) +int drxj_dap_scu_atomic_read_reg16(struct i2c_device_addr *dev_addr, + dr_xaddr_t addr, + u16 *data, dr_xflags_t flags) { u8 buf[2]; int rc = DRX_STS_ERROR; @@ -4168,7 +4168,7 @@ int DRXJ_DAP_SCU_AtomicReadReg16(struct i2c_device_addr *devAddr, return DRX_STS_INVALID_ARG; } - rc = DRXJ_DAP_SCU_AtomicReadWriteBlock(devAddr, addr, 2, buf, true); + rc = drxj_dap_scu_atomic_read_write_block(dev_addr, addr, 2, buf, true); word = (u16) (buf[0] + (buf[1] << 8)); @@ -4179,13 +4179,13 @@ int DRXJ_DAP_SCU_AtomicReadReg16(struct i2c_device_addr *devAddr, /*============================================================================*/ /** -* \fn int DRXJ_DAP_SCU_AtomicWriteReg16() +* \fn int drxj_dap_scu_atomic_write_reg16() * \brief Atomic read of 16 bits words */ static -int DRXJ_DAP_SCU_AtomicWriteReg16(struct i2c_device_addr *devAddr, - DRXaddr_t addr, - u16 data, DRXflags_t flags) +int drxj_dap_scu_atomic_write_reg16(struct i2c_device_addr *dev_addr, + dr_xaddr_t addr, + u16 data, dr_xflags_t flags) { u8 buf[2]; int rc = DRX_STS_ERROR; @@ -4193,31 +4193,31 @@ int DRXJ_DAP_SCU_AtomicWriteReg16(struct i2c_device_addr *devAddr, buf[0] = (u8) (data & 0xff); buf[1] = (u8) ((data >> 8) & 0xff); - rc = DRXJ_DAP_SCU_AtomicReadWriteBlock(devAddr, addr, 2, buf, false); + rc = drxj_dap_scu_atomic_read_write_block(dev_addr, addr, 2, buf, false); return rc; } static int -CtrlI2CWriteRead(pDRXDemodInstance_t demod, pDRXI2CData_t i2cData) +ctrl_i2c_write_read(pdrx_demod_instance_t demod, pdrxi2c_data_t i2c_data) { return (DRX_STS_FUNC_NOT_AVAILABLE); } int -TunerI2CWriteRead(struct tuner_instance *tuner, - struct i2c_device_addr *wDevAddr, - u16 wCount, +tuner_i2c_write_read(struct tuner_instance *tuner, + struct i2c_device_addr *w_dev_addr, + u16 w_count, u8 *wData, - struct i2c_device_addr *rDevAddr, u16 rCount, u8 *rData) + struct i2c_device_addr *r_dev_addr, u16 r_count, u8 *r_data) { - pDRXDemodInstance_t demod; - DRXI2CData_t i2cData = - { 2, wDevAddr, wCount, wData, rDevAddr, rCount, rData }; + pdrx_demod_instance_t demod; + drxi2c_data_t i2c_data = + { 2, w_dev_addr, w_count, wData, r_dev_addr, r_count, r_data }; - demod = (pDRXDemodInstance_t) (tuner->myCommonAttr->myUserData); + demod = (pdrx_demod_instance_t) (tuner->my_common_attr->myUser_data); - return (CtrlI2CWriteRead(demod, &i2cData)); + return (ctrl_i2c_write_read(demod, &i2c_data)); } /* -------------------------------------------------------------------------- */ @@ -4230,30 +4230,30 @@ TunerI2CWriteRead(struct tuner_instance *tuner, * \retval DRX_STS_ERROR Failure: I2C error * */ -static int ADCSyncMeasurement(pDRXDemodInstance_t demod, u16 *count) +static int adc_sync_measurement(pdrx_demod_instance_t demod, u16 *count) { u16 data = 0; - struct i2c_device_addr *devAddr = NULL; + struct i2c_device_addr *dev_addr = NULL; - devAddr = demod->myI2CDevAddr; + dev_addr = demod->my_i2c_dev_addr; /* Start measurement */ - WR16(devAddr, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE); - WR16(devAddr, IQM_AF_START_LOCK__A, 1); + WR16(dev_addr, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE); + WR16(dev_addr, IQM_AF_START_LOCK__A, 1); /* Wait at least 3*128*(1/sysclk) <<< 1 millisec */ - CHK_ERROR(DRXBSP_HST_Sleep(1)); + CHK_ERROR(drxbsp_hst_sleep(1)); *count = 0; - RR16(devAddr, IQM_AF_PHASE0__A, &data); + RR16(dev_addr, IQM_AF_PHASE0__A, &data); if (data == 127) { *count = *count + 1; } - RR16(devAddr, IQM_AF_PHASE1__A, &data); + RR16(dev_addr, IQM_AF_PHASE1__A, &data); if (data == 127) { *count = *count + 1; } - RR16(devAddr, IQM_AF_PHASE2__A, &data); + RR16(dev_addr, IQM_AF_PHASE2__A, &data); if (data == 127) { *count = *count + 1; } @@ -4275,25 +4275,25 @@ rw_error: * */ -static int ADCSynchronization(pDRXDemodInstance_t demod) +static int adc_synchronization(pdrx_demod_instance_t demod) { u16 count = 0; - struct i2c_device_addr *devAddr = NULL; + struct i2c_device_addr *dev_addr = NULL; - devAddr = demod->myI2CDevAddr; + dev_addr = demod->my_i2c_dev_addr; - CHK_ERROR(ADCSyncMeasurement(demod, &count)); + CHK_ERROR(adc_sync_measurement(demod, &count)); if (count == 1) { /* Try sampling on a diffrent edge */ - u16 clkNeg = 0; + u16 clk_neg = 0; - RR16(devAddr, IQM_AF_CLKNEG__A, &clkNeg); + RR16(dev_addr, IQM_AF_CLKNEG__A, &clk_neg); - clkNeg ^= IQM_AF_CLKNEG_CLKNEGDATA__M; - WR16(devAddr, IQM_AF_CLKNEG__A, clkNeg); + clk_neg ^= IQM_AF_CLKNEG_CLKNEGDATA__M; + WR16(dev_addr, IQM_AF_CLKNEG__A, clk_neg); - CHK_ERROR(ADCSyncMeasurement(demod, &count)); + CHK_ERROR(adc_sync_measurement(demod, &count)); } if (count < 2) { @@ -4312,17 +4312,17 @@ rw_error: * \param active * \return int. */ -static int IQMSetAf(pDRXDemodInstance_t demod, bool active) +static int iqm_set_af(pdrx_demod_instance_t demod, bool active) { u16 data = 0; - struct i2c_device_addr *devAddr = NULL; - pDRXJData_t extAttr = NULL; + struct i2c_device_addr *dev_addr = NULL; + pdrxj_data_t ext_attr = NULL; - extAttr = (pDRXJData_t) demod->myExtAttr; - devAddr = demod->myI2CDevAddr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; + dev_addr = demod->my_i2c_dev_addr; /* Configure IQM */ - RR16(devAddr, IQM_AF_STDBY__A, &data); + RR16(dev_addr, IQM_AF_STDBY__A, &data); if (!active) { data &= ((~IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE) @@ -4338,7 +4338,7 @@ static int IQMSetAf(pDRXDemodInstance_t demod, bool active) | IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE | IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE); } - WR16(devAddr, IQM_AF_STDBY__A, data); + WR16(dev_addr, IQM_AF_STDBY__A, data); return (DRX_STS_OK); rw_error: @@ -4347,7 +4347,7 @@ rw_error: /* -------------------------------------------------------------------------- */ static int -CtrlSetCfgATVOutput(pDRXDemodInstance_t demod, pDRXJCfgAtvOutput_t outputCfg); +ctrl_set_cfg_atv_output(pdrx_demod_instance_t demod, p_drxj_cfg_atv_output_t output_cfg); /** * \brief set configuration of pin-safe mode @@ -4356,102 +4356,102 @@ CtrlSetCfgATVOutput(pDRXDemodInstance_t demod, pDRXJCfgAtvOutput_t outputCfg); * \return int. */ static int -CtrlSetCfgPdrSafeMode(pDRXDemodInstance_t demod, bool *enable) +ctrl_set_cfg_pdr_safe_mode(pdrx_demod_instance_t demod, bool *enable) { - pDRXJData_t extAttr = (pDRXJData_t) NULL; - struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; - pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) NULL; + pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) NULL; + pdrx_common_attr_t common_attr = (pdrx_common_attr_t) NULL; if (enable == NULL) { return (DRX_STS_INVALID_ARG); } - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; - commonAttr = demod->myCommonAttr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; + common_attr = demod->my_common_attr; /* Write magic word to enable pdr reg write */ - WR16(devAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); + WR16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); if (*enable == true) { - bool bridgeEnabled = false; + bool bridge_enabled = false; /* MPEG pins to input */ - WR16(devAddr, SIO_PDR_MSTRT_CFG__A, DRXJ_PIN_SAFE_MODE); - WR16(devAddr, SIO_PDR_MERR_CFG__A, DRXJ_PIN_SAFE_MODE); - WR16(devAddr, SIO_PDR_MCLK_CFG__A, DRXJ_PIN_SAFE_MODE); - WR16(devAddr, SIO_PDR_MVAL_CFG__A, DRXJ_PIN_SAFE_MODE); - WR16(devAddr, SIO_PDR_MD0_CFG__A, DRXJ_PIN_SAFE_MODE); - WR16(devAddr, SIO_PDR_MD1_CFG__A, DRXJ_PIN_SAFE_MODE); - WR16(devAddr, SIO_PDR_MD2_CFG__A, DRXJ_PIN_SAFE_MODE); - WR16(devAddr, SIO_PDR_MD3_CFG__A, DRXJ_PIN_SAFE_MODE); - WR16(devAddr, SIO_PDR_MD4_CFG__A, DRXJ_PIN_SAFE_MODE); - WR16(devAddr, SIO_PDR_MD5_CFG__A, DRXJ_PIN_SAFE_MODE); - WR16(devAddr, SIO_PDR_MD6_CFG__A, DRXJ_PIN_SAFE_MODE); - WR16(devAddr, SIO_PDR_MD7_CFG__A, DRXJ_PIN_SAFE_MODE); + WR16(dev_addr, SIO_PDR_MSTRT_CFG__A, DRXJ_PIN_SAFE_MODE); + WR16(dev_addr, SIO_PDR_MERR_CFG__A, DRXJ_PIN_SAFE_MODE); + WR16(dev_addr, SIO_PDR_MCLK_CFG__A, DRXJ_PIN_SAFE_MODE); + WR16(dev_addr, SIO_PDR_MVAL_CFG__A, DRXJ_PIN_SAFE_MODE); + WR16(dev_addr, SIO_PDR_MD0_CFG__A, DRXJ_PIN_SAFE_MODE); + WR16(dev_addr, SIO_PDR_MD1_CFG__A, DRXJ_PIN_SAFE_MODE); + WR16(dev_addr, SIO_PDR_MD2_CFG__A, DRXJ_PIN_SAFE_MODE); + WR16(dev_addr, SIO_PDR_MD3_CFG__A, DRXJ_PIN_SAFE_MODE); + WR16(dev_addr, SIO_PDR_MD4_CFG__A, DRXJ_PIN_SAFE_MODE); + WR16(dev_addr, SIO_PDR_MD5_CFG__A, DRXJ_PIN_SAFE_MODE); + WR16(dev_addr, SIO_PDR_MD6_CFG__A, DRXJ_PIN_SAFE_MODE); + WR16(dev_addr, SIO_PDR_MD7_CFG__A, DRXJ_PIN_SAFE_MODE); /* PD_I2C_SDA2 Bridge off, Port2 Inactive PD_I2C_SCL2 Bridge off, Port2 Inactive */ - CHK_ERROR(CtrlI2CBridge(demod, &bridgeEnabled)); - WR16(devAddr, SIO_PDR_I2C_SDA2_CFG__A, DRXJ_PIN_SAFE_MODE); - WR16(devAddr, SIO_PDR_I2C_SCL2_CFG__A, DRXJ_PIN_SAFE_MODE); + CHK_ERROR(ctrl_i2c_bridge(demod, &bridge_enabled)); + WR16(dev_addr, SIO_PDR_I2C_SDA2_CFG__A, DRXJ_PIN_SAFE_MODE); + WR16(dev_addr, SIO_PDR_I2C_SCL2_CFG__A, DRXJ_PIN_SAFE_MODE); /* PD_GPIO Store and set to input PD_VSYNC Store and set to input PD_SMA_RX Store and set to input PD_SMA_TX Store and set to input */ - RR16(devAddr, SIO_PDR_GPIO_CFG__A, - &extAttr->pdrSafeRestoreValGpio); - RR16(devAddr, SIO_PDR_VSYNC_CFG__A, - &extAttr->pdrSafeRestoreValVSync); - RR16(devAddr, SIO_PDR_SMA_RX_CFG__A, - &extAttr->pdrSafeRestoreValSmaRx); - RR16(devAddr, SIO_PDR_SMA_TX_CFG__A, - &extAttr->pdrSafeRestoreValSmaTx); - WR16(devAddr, SIO_PDR_GPIO_CFG__A, DRXJ_PIN_SAFE_MODE); - WR16(devAddr, SIO_PDR_VSYNC_CFG__A, DRXJ_PIN_SAFE_MODE); - WR16(devAddr, SIO_PDR_SMA_RX_CFG__A, DRXJ_PIN_SAFE_MODE); - WR16(devAddr, SIO_PDR_SMA_TX_CFG__A, DRXJ_PIN_SAFE_MODE); + RR16(dev_addr, SIO_PDR_GPIO_CFG__A, + &ext_attr->pdr_safe_restore_val_gpio); + RR16(dev_addr, SIO_PDR_VSYNC_CFG__A, + &ext_attr->pdr_safe_restore_val_v_sync); + RR16(dev_addr, SIO_PDR_SMA_RX_CFG__A, + &ext_attr->pdr_safe_restore_val_sma_rx); + RR16(dev_addr, SIO_PDR_SMA_TX_CFG__A, + &ext_attr->pdr_safe_restore_val_sma_tx); + WR16(dev_addr, SIO_PDR_GPIO_CFG__A, DRXJ_PIN_SAFE_MODE); + WR16(dev_addr, SIO_PDR_VSYNC_CFG__A, DRXJ_PIN_SAFE_MODE); + WR16(dev_addr, SIO_PDR_SMA_RX_CFG__A, DRXJ_PIN_SAFE_MODE); + WR16(dev_addr, SIO_PDR_SMA_TX_CFG__A, DRXJ_PIN_SAFE_MODE); /* PD_RF_AGC Analog DAC outputs, cannot be set to input or tristate! PD_IF_AGC Analog DAC outputs, cannot be set to input or tristate! */ - CHK_ERROR(IQMSetAf(demod, false)); + CHK_ERROR(iqm_set_af(demod, false)); /* PD_CVBS Analog DAC output, standby mode PD_SIF Analog DAC output, standby mode */ - WR16(devAddr, ATV_TOP_STDBY__A, + WR16(dev_addr, ATV_TOP_STDBY__A, (ATV_TOP_STDBY_SIF_STDBY_STANDBY & (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE))); /* PD_I2S_CL Input PD_I2S_DA Input PD_I2S_WS Input */ - WR16(devAddr, SIO_PDR_I2S_CL_CFG__A, DRXJ_PIN_SAFE_MODE); - WR16(devAddr, SIO_PDR_I2S_DA_CFG__A, DRXJ_PIN_SAFE_MODE); - WR16(devAddr, SIO_PDR_I2S_WS_CFG__A, DRXJ_PIN_SAFE_MODE); + WR16(dev_addr, SIO_PDR_I2S_CL_CFG__A, DRXJ_PIN_SAFE_MODE); + WR16(dev_addr, SIO_PDR_I2S_DA_CFG__A, DRXJ_PIN_SAFE_MODE); + WR16(dev_addr, SIO_PDR_I2S_WS_CFG__A, DRXJ_PIN_SAFE_MODE); } else { /* No need to restore MPEG pins; is done in SetStandard/SetChannel */ /* PD_I2C_SDA2 Port2 active PD_I2C_SCL2 Port2 active */ - WR16(devAddr, SIO_PDR_I2C_SDA2_CFG__A, + WR16(dev_addr, SIO_PDR_I2C_SDA2_CFG__A, SIO_PDR_I2C_SDA2_CFG__PRE); - WR16(devAddr, SIO_PDR_I2C_SCL2_CFG__A, + WR16(dev_addr, SIO_PDR_I2C_SCL2_CFG__A, SIO_PDR_I2C_SCL2_CFG__PRE); /* PD_GPIO Restore PD_VSYNC Restore PD_SMA_RX Restore PD_SMA_TX Restore */ - WR16(devAddr, SIO_PDR_GPIO_CFG__A, - extAttr->pdrSafeRestoreValGpio); - WR16(devAddr, SIO_PDR_VSYNC_CFG__A, - extAttr->pdrSafeRestoreValVSync); - WR16(devAddr, SIO_PDR_SMA_RX_CFG__A, - extAttr->pdrSafeRestoreValSmaRx); - WR16(devAddr, SIO_PDR_SMA_TX_CFG__A, - extAttr->pdrSafeRestoreValSmaTx); + WR16(dev_addr, SIO_PDR_GPIO_CFG__A, + ext_attr->pdr_safe_restore_val_gpio); + WR16(dev_addr, SIO_PDR_VSYNC_CFG__A, + ext_attr->pdr_safe_restore_val_v_sync); + WR16(dev_addr, SIO_PDR_SMA_RX_CFG__A, + ext_attr->pdr_safe_restore_val_sma_rx); + WR16(dev_addr, SIO_PDR_SMA_TX_CFG__A, + ext_attr->pdr_safe_restore_val_sma_tx); /* PD_RF_AGC, PD_IF_AGC No need to restore; will be restored in SetStandard/SetChannel */ @@ -4464,8 +4464,8 @@ CtrlSetCfgPdrSafeMode(pDRXDemodInstance_t demod, bool *enable) } /* Write magic word to disable pdr reg write */ - WR16(devAddr, SIO_TOP_COMM_KEY__A, 0x0000); - extAttr->pdrSafeMode = *enable; + WR16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000); + ext_attr->pdr_safe_mode = *enable; return (DRX_STS_OK); @@ -4482,16 +4482,16 @@ rw_error: * \return int. */ static int -CtrlGetCfgPdrSafeMode(pDRXDemodInstance_t demod, bool *enabled) +ctrl_get_cfg_pdr_safe_mode(pdrx_demod_instance_t demod, bool *enabled) { - pDRXJData_t extAttr = (pDRXJData_t) NULL; + pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; if (enabled == NULL) { return (DRX_STS_INVALID_ARG); } - extAttr = (pDRXJData_t) demod->myExtAttr; - *enabled = extAttr->pdrSafeMode; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; + *enabled = ext_attr->pdr_safe_mode; return (DRX_STS_OK); } @@ -4501,10 +4501,10 @@ CtrlGetCfgPdrSafeMode(pDRXDemodInstance_t demod, bool *enabled) * \param demod Demodulator instance. * \return int. */ -static int CtrlValidateUCode(pDRXDemodInstance_t demod) +static int ctrl_validate_u_code(pdrx_demod_instance_t demod) { - u32 mcDev, mcPatch; - u16 verType; + u32 mc_dev, mc_patch; + u16 ver_type; /* Check device. * Disallow microcode if: @@ -4513,17 +4513,17 @@ static int CtrlValidateUCode(pDRXDemodInstance_t demod) * - product ID in version record's device ID does not * match DRXJ1 product IDs - 0x393 or 0x394 */ - DRX_GET_MCVERTYPE(demod, verType); - DRX_GET_MCDEV(demod, mcDev); - DRX_GET_MCPATCH(demod, mcPatch); - - if (DRX_ISMCVERTYPE(verType)) { - if ((mcDev != 0) && - (((mcDev >> 16) & 0xFFF) != 0x393) && - (((mcDev >> 16) & 0xFFF) != 0x394)) { + DRX_GET_MCVERTYPE(demod, ver_type); + DRX_GET_MCDEV(demod, mc_dev); + DRX_GET_MCPATCH(demod, mc_patch); + + if (DRX_ISMCVERTYPE(ver_type)) { + if ((mc_dev != 0) && + (((mc_dev >> 16) & 0xFFF) != 0x393) && + (((mc_dev >> 16) & 0xFFF) != 0x394)) { /* Microcode is marked for another device - error */ return DRX_STS_INVALID_ARG; - } else if (mcPatch != 0) { + } else if (mc_patch != 0) { /* Patch not allowed because there is no ROM */ return DRX_STS_INVALID_ARG; } @@ -4543,153 +4543,153 @@ static int CtrlValidateUCode(pDRXDemodInstance_t demod) /*============================================================================*/ /*============================================================================*/ /** -* \fn int InitAGC () +* \fn int init_agc () * \brief Initialize AGC for all standards. * \param demod instance of demodulator. * \param channel pointer to channel data. * \return int. */ -static int InitAGC(pDRXDemodInstance_t demod) -{ - struct i2c_device_addr *devAddr = NULL; - pDRXCommonAttr_t commonAttr = NULL; - pDRXJData_t extAttr = NULL; - pDRXJCfgAgc_t pAgcRfSettings = NULL; - pDRXJCfgAgc_t pAgcIfSettings = NULL; - u16 IngainTgtMax = 0; - u16 clpDirTo = 0; - u16 snsSumMax = 0; - u16 clpSumMax = 0; - u16 snsDirTo = 0; - u16 kiInnergainMin = 0; - u16 agcKi = 0; - u16 kiMax = 0; - u16 ifIaccuHiTgtMin = 0; +static int init_agc(pdrx_demod_instance_t demod) +{ + struct i2c_device_addr *dev_addr = NULL; + pdrx_common_attr_t common_attr = NULL; + pdrxj_data_t ext_attr = NULL; + p_drxj_cfg_agc_t p_agc_rf_settings = NULL; + p_drxj_cfg_agc_t p_agc_if_settings = NULL; + u16 ingain_tgt_max = 0; + u16 clp_dir_to = 0; + u16 sns_sum_max = 0; + u16 clp_sum_max = 0; + u16 sns_dir_to = 0; + u16 ki_innergain_min = 0; + u16 agc_ki = 0; + u16 ki_max = 0; + u16 if_iaccu_hi_tgt_min = 0; u16 data = 0; - u16 agcKiDgain = 0; - u16 kiMin = 0; - u16 clpCtrlMode = 0; - u16 agcRf = 0; - u16 agcIf = 0; - devAddr = demod->myI2CDevAddr; - commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; - extAttr = (pDRXJData_t) demod->myExtAttr; - - switch (extAttr->standard) { + u16 agc_kiDgain = 0; + u16 ki_min = 0; + u16 clp_ctrl_mode = 0; + u16 agc_rf = 0; + u16 agc_if = 0; + dev_addr = demod->my_i2c_dev_addr; + common_attr = (pdrx_common_attr_t) demod->my_common_attr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; + + switch (ext_attr->standard) { case DRX_STANDARD_8VSB: - clpSumMax = 1023; - clpDirTo = (u16) (-9); - snsSumMax = 1023; - snsDirTo = (u16) (-9); - kiInnergainMin = (u16) (-32768); - kiMax = 0x032C; - agcKiDgain = 0xC; - ifIaccuHiTgtMin = 2047; - kiMin = 0x0117; - IngainTgtMax = 16383; - clpCtrlMode = 0; - WR16(devAddr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff); - WR16(devAddr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0); - WR16(devAddr, SCU_RAM_AGC_CLP_SUM__A, 0); - WR16(devAddr, SCU_RAM_AGC_CLP_CYCCNT__A, 0); - WR16(devAddr, SCU_RAM_AGC_CLP_DIR_WD__A, 0); - WR16(devAddr, SCU_RAM_AGC_CLP_DIR_STP__A, 1); - WR16(devAddr, SCU_RAM_AGC_SNS_SUM__A, 0); - WR16(devAddr, SCU_RAM_AGC_SNS_CYCCNT__A, 0); - WR16(devAddr, SCU_RAM_AGC_SNS_DIR_WD__A, 0); - WR16(devAddr, SCU_RAM_AGC_SNS_DIR_STP__A, 1); - WR16(devAddr, SCU_RAM_AGC_INGAIN__A, 1024); - WR16(devAddr, SCU_RAM_VSB_AGC_POW_TGT__A, 22600); - WR16(devAddr, SCU_RAM_AGC_INGAIN_TGT__A, 13200); - pAgcIfSettings = &(extAttr->vsbIfAgcCfg); - pAgcRfSettings = &(extAttr->vsbRfAgcCfg); + clp_sum_max = 1023; + clp_dir_to = (u16) (-9); + sns_sum_max = 1023; + sns_dir_to = (u16) (-9); + ki_innergain_min = (u16) (-32768); + ki_max = 0x032C; + agc_kiDgain = 0xC; + if_iaccu_hi_tgt_min = 2047; + ki_min = 0x0117; + ingain_tgt_max = 16383; + clp_ctrl_mode = 0; + WR16(dev_addr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff); + WR16(dev_addr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0); + WR16(dev_addr, SCU_RAM_AGC_CLP_SUM__A, 0); + WR16(dev_addr, SCU_RAM_AGC_CLP_CYCCNT__A, 0); + WR16(dev_addr, SCU_RAM_AGC_CLP_DIR_WD__A, 0); + WR16(dev_addr, SCU_RAM_AGC_CLP_DIR_STP__A, 1); + WR16(dev_addr, SCU_RAM_AGC_SNS_SUM__A, 0); + WR16(dev_addr, SCU_RAM_AGC_SNS_CYCCNT__A, 0); + WR16(dev_addr, SCU_RAM_AGC_SNS_DIR_WD__A, 0); + WR16(dev_addr, SCU_RAM_AGC_SNS_DIR_STP__A, 1); + WR16(dev_addr, SCU_RAM_AGC_INGAIN__A, 1024); + WR16(dev_addr, SCU_RAM_VSB_AGC_POW_TGT__A, 22600); + WR16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, 13200); + p_agc_if_settings = &(ext_attr->vsb_if_agc_cfg); + p_agc_rf_settings = &(ext_attr->vsb_rf_agc_cfg); break; #ifndef DRXJ_VSB_ONLY case DRX_STANDARD_ITU_A: case DRX_STANDARD_ITU_C: case DRX_STANDARD_ITU_B: - IngainTgtMax = 5119; - clpSumMax = 1023; - clpDirTo = (u16) (-5); - snsSumMax = 127; - snsDirTo = (u16) (-3); - kiInnergainMin = 0; - kiMax = 0x0657; - ifIaccuHiTgtMin = 2047; - agcKiDgain = 0x7; - kiMin = 0x0117; - clpCtrlMode = 0; - WR16(devAddr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff); - WR16(devAddr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0); - WR16(devAddr, SCU_RAM_AGC_CLP_SUM__A, 0); - WR16(devAddr, SCU_RAM_AGC_CLP_CYCCNT__A, 0); - WR16(devAddr, SCU_RAM_AGC_CLP_DIR_WD__A, 0); - WR16(devAddr, SCU_RAM_AGC_CLP_DIR_STP__A, 1); - WR16(devAddr, SCU_RAM_AGC_SNS_SUM__A, 0); - WR16(devAddr, SCU_RAM_AGC_SNS_CYCCNT__A, 0); - WR16(devAddr, SCU_RAM_AGC_SNS_DIR_WD__A, 0); - WR16(devAddr, SCU_RAM_AGC_SNS_DIR_STP__A, 1); - pAgcIfSettings = &(extAttr->qamIfAgcCfg); - pAgcRfSettings = &(extAttr->qamRfAgcCfg); - WR16(devAddr, SCU_RAM_AGC_INGAIN_TGT__A, pAgcIfSettings->top); - - RR16(devAddr, SCU_RAM_AGC_KI__A, &agcKi); - agcKi &= 0xf000; - WR16(devAddr, SCU_RAM_AGC_KI__A, agcKi); + ingain_tgt_max = 5119; + clp_sum_max = 1023; + clp_dir_to = (u16) (-5); + sns_sum_max = 127; + sns_dir_to = (u16) (-3); + ki_innergain_min = 0; + ki_max = 0x0657; + if_iaccu_hi_tgt_min = 2047; + agc_kiDgain = 0x7; + ki_min = 0x0117; + clp_ctrl_mode = 0; + WR16(dev_addr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff); + WR16(dev_addr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0); + WR16(dev_addr, SCU_RAM_AGC_CLP_SUM__A, 0); + WR16(dev_addr, SCU_RAM_AGC_CLP_CYCCNT__A, 0); + WR16(dev_addr, SCU_RAM_AGC_CLP_DIR_WD__A, 0); + WR16(dev_addr, SCU_RAM_AGC_CLP_DIR_STP__A, 1); + WR16(dev_addr, SCU_RAM_AGC_SNS_SUM__A, 0); + WR16(dev_addr, SCU_RAM_AGC_SNS_CYCCNT__A, 0); + WR16(dev_addr, SCU_RAM_AGC_SNS_DIR_WD__A, 0); + WR16(dev_addr, SCU_RAM_AGC_SNS_DIR_STP__A, 1); + p_agc_if_settings = &(ext_attr->qam_if_agc_cfg); + p_agc_rf_settings = &(ext_attr->qam_rf_agc_cfg); + WR16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, p_agc_if_settings->top); + + RR16(dev_addr, SCU_RAM_AGC_KI__A, &agc_ki); + agc_ki &= 0xf000; + WR16(dev_addr, SCU_RAM_AGC_KI__A, agc_ki); break; #endif #ifndef DRXJ_DIGITAL_ONLY case DRX_STANDARD_FM: - clpSumMax = 1023; - snsSumMax = 1023; - kiInnergainMin = (u16) (-32768); - ifIaccuHiTgtMin = 2047; - agcKiDgain = 0x7; - kiMin = 0x0225; - kiMax = 0x0547; - clpDirTo = (u16) (-9); - snsDirTo = (u16) (-9); - IngainTgtMax = 9000; - clpCtrlMode = 1; - pAgcIfSettings = &(extAttr->atvIfAgcCfg); - pAgcRfSettings = &(extAttr->atvRfAgcCfg); - WR16(devAddr, SCU_RAM_AGC_INGAIN_TGT__A, pAgcIfSettings->top); + clp_sum_max = 1023; + sns_sum_max = 1023; + ki_innergain_min = (u16) (-32768); + if_iaccu_hi_tgt_min = 2047; + agc_kiDgain = 0x7; + ki_min = 0x0225; + ki_max = 0x0547; + clp_dir_to = (u16) (-9); + sns_dir_to = (u16) (-9); + ingain_tgt_max = 9000; + clp_ctrl_mode = 1; + p_agc_if_settings = &(ext_attr->atv_if_agc_cfg); + p_agc_rf_settings = &(ext_attr->atv_rf_agc_cfg); + WR16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, p_agc_if_settings->top); break; case DRX_STANDARD_NTSC: case DRX_STANDARD_PAL_SECAM_BG: case DRX_STANDARD_PAL_SECAM_DK: case DRX_STANDARD_PAL_SECAM_I: - clpSumMax = 1023; - snsSumMax = 1023; - kiInnergainMin = (u16) (-32768); - ifIaccuHiTgtMin = 2047; - agcKiDgain = 0x7; - kiMin = 0x0225; - kiMax = 0x0547; - clpDirTo = (u16) (-9); - IngainTgtMax = 9000; - pAgcIfSettings = &(extAttr->atvIfAgcCfg); - pAgcRfSettings = &(extAttr->atvRfAgcCfg); - snsDirTo = (u16) (-9); - clpCtrlMode = 1; - WR16(devAddr, SCU_RAM_AGC_INGAIN_TGT__A, pAgcIfSettings->top); + clp_sum_max = 1023; + sns_sum_max = 1023; + ki_innergain_min = (u16) (-32768); + if_iaccu_hi_tgt_min = 2047; + agc_kiDgain = 0x7; + ki_min = 0x0225; + ki_max = 0x0547; + clp_dir_to = (u16) (-9); + ingain_tgt_max = 9000; + p_agc_if_settings = &(ext_attr->atv_if_agc_cfg); + p_agc_rf_settings = &(ext_attr->atv_rf_agc_cfg); + sns_dir_to = (u16) (-9); + clp_ctrl_mode = 1; + WR16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, p_agc_if_settings->top); break; case DRX_STANDARD_PAL_SECAM_L: case DRX_STANDARD_PAL_SECAM_LP: - clpSumMax = 1023; - snsSumMax = 1023; - kiInnergainMin = (u16) (-32768); - ifIaccuHiTgtMin = 2047; - agcKiDgain = 0x7; - kiMin = 0x0225; - kiMax = 0x0547; - clpDirTo = (u16) (-9); - snsDirTo = (u16) (-9); - IngainTgtMax = 9000; - clpCtrlMode = 1; - pAgcIfSettings = &(extAttr->atvIfAgcCfg); - pAgcRfSettings = &(extAttr->atvRfAgcCfg); - WR16(devAddr, SCU_RAM_AGC_INGAIN_TGT__A, pAgcIfSettings->top); + clp_sum_max = 1023; + sns_sum_max = 1023; + ki_innergain_min = (u16) (-32768); + if_iaccu_hi_tgt_min = 2047; + agc_kiDgain = 0x7; + ki_min = 0x0225; + ki_max = 0x0547; + clp_dir_to = (u16) (-9); + sns_dir_to = (u16) (-9); + ingain_tgt_max = 9000; + clp_ctrl_mode = 1; + p_agc_if_settings = &(ext_attr->atv_if_agc_cfg); + p_agc_rf_settings = &(ext_attr->atv_rf_agc_cfg); + WR16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, p_agc_if_settings->top); break; #endif default: @@ -4697,51 +4697,51 @@ static int InitAGC(pDRXDemodInstance_t demod) } /* for new AGC interface */ - WR16(devAddr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, pAgcIfSettings->top); - WR16(devAddr, SCU_RAM_AGC_INGAIN__A, pAgcIfSettings->top); /* Gain fed from inner to outer AGC */ - WR16(devAddr, SCU_RAM_AGC_INGAIN_TGT_MAX__A, IngainTgtMax); - WR16(devAddr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, ifIaccuHiTgtMin); - WR16(devAddr, SCU_RAM_AGC_IF_IACCU_HI__A, 0); /* set to pAgcSettings->top before */ - WR16(devAddr, SCU_RAM_AGC_IF_IACCU_LO__A, 0); - WR16(devAddr, SCU_RAM_AGC_RF_IACCU_HI__A, 0); - WR16(devAddr, SCU_RAM_AGC_RF_IACCU_LO__A, 0); - WR16(devAddr, SCU_RAM_AGC_RF_MAX__A, 32767); - WR16(devAddr, SCU_RAM_AGC_CLP_SUM_MAX__A, clpSumMax); - WR16(devAddr, SCU_RAM_AGC_SNS_SUM_MAX__A, snsSumMax); - WR16(devAddr, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, kiInnergainMin); - WR16(devAddr, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50); - WR16(devAddr, SCU_RAM_AGC_KI_CYCLEN__A, 500); - WR16(devAddr, SCU_RAM_AGC_SNS_CYCLEN__A, 500); - WR16(devAddr, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20); - WR16(devAddr, SCU_RAM_AGC_KI_MIN__A, kiMin); - WR16(devAddr, SCU_RAM_AGC_KI_MAX__A, kiMax); - WR16(devAddr, SCU_RAM_AGC_KI_RED__A, 0); - WR16(devAddr, SCU_RAM_AGC_CLP_SUM_MIN__A, 8); - WR16(devAddr, SCU_RAM_AGC_CLP_CYCLEN__A, 500); - WR16(devAddr, SCU_RAM_AGC_CLP_DIR_TO__A, clpDirTo); - WR16(devAddr, SCU_RAM_AGC_SNS_SUM_MIN__A, 8); - WR16(devAddr, SCU_RAM_AGC_SNS_DIR_TO__A, snsDirTo); - WR16(devAddr, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, 50); - WR16(devAddr, SCU_RAM_AGC_CLP_CTRL_MODE__A, clpCtrlMode); - - agcRf = 0x800 + pAgcRfSettings->cutOffCurrent; - if (commonAttr->tunerRfAgcPol == true) { - agcRf = 0x87ff - agcRf; - } - - agcIf = 0x800; - if (commonAttr->tunerIfAgcPol == true) { - agcRf = 0x87ff - agcRf; - } - - WR16(devAddr, IQM_AF_AGC_RF__A, agcRf); - WR16(devAddr, IQM_AF_AGC_IF__A, agcIf); + WR16(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_if_settings->top); + WR16(dev_addr, SCU_RAM_AGC_INGAIN__A, p_agc_if_settings->top); /* Gain fed from inner to outer AGC */ + WR16(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max); + WR16(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, if_iaccu_hi_tgt_min); + WR16(dev_addr, SCU_RAM_AGC_IF_IACCU_HI__A, 0); /* set to p_agc_settings->top before */ + WR16(dev_addr, SCU_RAM_AGC_IF_IACCU_LO__A, 0); + WR16(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, 0); + WR16(dev_addr, SCU_RAM_AGC_RF_IACCU_LO__A, 0); + WR16(dev_addr, SCU_RAM_AGC_RF_MAX__A, 32767); + WR16(dev_addr, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max); + WR16(dev_addr, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max); + WR16(dev_addr, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, ki_innergain_min); + WR16(dev_addr, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50); + WR16(dev_addr, SCU_RAM_AGC_KI_CYCLEN__A, 500); + WR16(dev_addr, SCU_RAM_AGC_SNS_CYCLEN__A, 500); + WR16(dev_addr, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20); + WR16(dev_addr, SCU_RAM_AGC_KI_MIN__A, ki_min); + WR16(dev_addr, SCU_RAM_AGC_KI_MAX__A, ki_max); + WR16(dev_addr, SCU_RAM_AGC_KI_RED__A, 0); + WR16(dev_addr, SCU_RAM_AGC_CLP_SUM_MIN__A, 8); + WR16(dev_addr, SCU_RAM_AGC_CLP_CYCLEN__A, 500); + WR16(dev_addr, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to); + WR16(dev_addr, SCU_RAM_AGC_SNS_SUM_MIN__A, 8); + WR16(dev_addr, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to); + WR16(dev_addr, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, 50); + WR16(dev_addr, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode); + + agc_rf = 0x800 + p_agc_rf_settings->cut_off_current; + if (common_attr->tuner_rf_agc_pol == true) { + agc_rf = 0x87ff - agc_rf; + } + + agc_if = 0x800; + if (common_attr->tuner_if_agc_pol == true) { + agc_rf = 0x87ff - agc_rf; + } + + WR16(dev_addr, IQM_AF_AGC_RF__A, agc_rf); + WR16(dev_addr, IQM_AF_AGC_IF__A, agc_if); /* Set/restore Ki DGAIN factor */ - RR16(devAddr, SCU_RAM_AGC_KI__A, &data); + RR16(dev_addr, SCU_RAM_AGC_KI__A, &data); data &= ~SCU_RAM_AGC_KI_DGAIN__M; - data |= (agcKiDgain << SCU_RAM_AGC_KI_DGAIN__B); - WR16(devAddr, SCU_RAM_AGC_KI__A, data); + data |= (agc_kiDgain << SCU_RAM_AGC_KI_DGAIN__B); + WR16(dev_addr, SCU_RAM_AGC_KI__A, data); return (DRX_STS_OK); rw_error: @@ -4749,101 +4749,101 @@ rw_error: } /** -* \fn int SetFrequency () +* \fn int set_frequency () * \brief Set frequency shift. * \param demod instance of demodulator. * \param channel pointer to channel data. -* \param tunerFreqOffset residual frequency from tuner. +* \param tuner_freq_offset residual frequency from tuner. * \return int. */ static int -SetFrequency(pDRXDemodInstance_t demod, - pDRXChannel_t channel, s32 tunerFreqOffset) -{ - struct i2c_device_addr *devAddr = NULL; - pDRXCommonAttr_t commonAttr = NULL; - s32 samplingFrequency = 0; - s32 frequencyShift = 0; - s32 ifFreqActual = 0; - s32 rfFreqResidual = 0; - s32 adcFreq = 0; - s32 intermediateFreq = 0; - u32 iqmFsRateOfs = 0; - pDRXJData_t extAttr = NULL; - bool adcFlip = true; - bool selectPosImage = false; - bool rfMirror = false; - bool tunerMirror = true; - bool imageToSelect = true; - s32 fmFrequencyShift = 0; - - devAddr = demod->myI2CDevAddr; - commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; - extAttr = (pDRXJData_t) demod->myExtAttr; - rfFreqResidual = -1 * tunerFreqOffset; - rfMirror = (extAttr->mirror == DRX_MIRROR_YES) ? true : false; - tunerMirror = demod->myCommonAttr->mirrorFreqSpect ? false : true; +set_frequency(pdrx_demod_instance_t demod, + pdrx_channel_t channel, s32 tuner_freq_offset) +{ + struct i2c_device_addr *dev_addr = NULL; + pdrx_common_attr_t common_attr = NULL; + s32 sampling_frequency = 0; + s32 frequency_shift = 0; + s32 if_freq_actual = 0; + s32 rf_freq_residual = 0; + s32 adc_freq = 0; + s32 intermediate_freq = 0; + u32 iqm_fs_rate_ofs = 0; + pdrxj_data_t ext_attr = NULL; + bool adc_flip = true; + bool select_pos_image = false; + bool rf_mirror = false; + bool tuner_mirror = true; + bool image_to_select = true; + s32 fm_frequency_shift = 0; + + dev_addr = demod->my_i2c_dev_addr; + common_attr = (pdrx_common_attr_t) demod->my_common_attr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; + rf_freq_residual = -1 * tuner_freq_offset; + rf_mirror = (ext_attr->mirror == DRX_MIRROR_YES) ? true : false; + tuner_mirror = demod->my_common_attr->mirror_freq_spect ? false : true; /* Program frequency shifter No need to account for mirroring on RF */ - switch (extAttr->standard) { + switch (ext_attr->standard) { case DRX_STANDARD_ITU_A: /* fallthrough */ case DRX_STANDARD_ITU_C: /* fallthrough */ case DRX_STANDARD_PAL_SECAM_LP: /* fallthrough */ case DRX_STANDARD_8VSB: - selectPosImage = true; + select_pos_image = true; break; case DRX_STANDARD_FM: /* After IQM FS sound carrier must appear at 4 Mhz in spect. Sound carrier is already 3Mhz above centre frequency due to tuner setting so now add an extra shift of 1MHz... */ - fmFrequencyShift = 1000; + fm_frequency_shift = 1000; case DRX_STANDARD_ITU_B: /* fallthrough */ case DRX_STANDARD_NTSC: /* fallthrough */ case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ case DRX_STANDARD_PAL_SECAM_L: - selectPosImage = false; + select_pos_image = false; break; default: return (DRX_STS_INVALID_ARG); } - intermediateFreq = demod->myCommonAttr->intermediateFreq; - samplingFrequency = demod->myCommonAttr->sysClockFreq / 3; - if (tunerMirror == true) { + intermediate_freq = demod->my_common_attr->intermediate_freq; + sampling_frequency = demod->my_common_attr->sys_clock_freq / 3; + if (tuner_mirror == true) { /* tuner doesn't mirror */ - ifFreqActual = - intermediateFreq + rfFreqResidual + fmFrequencyShift; + if_freq_actual = + intermediate_freq + rf_freq_residual + fm_frequency_shift; } else { /* tuner mirrors */ - ifFreqActual = - intermediateFreq - rfFreqResidual - fmFrequencyShift; + if_freq_actual = + intermediate_freq - rf_freq_residual - fm_frequency_shift; } - if (ifFreqActual > samplingFrequency / 2) { + if (if_freq_actual > sampling_frequency / 2) { /* adc mirrors */ - adcFreq = samplingFrequency - ifFreqActual; - adcFlip = true; + adc_freq = sampling_frequency - if_freq_actual; + adc_flip = true; } else { /* adc doesn't mirror */ - adcFreq = ifFreqActual; - adcFlip = false; + adc_freq = if_freq_actual; + adc_flip = false; } - frequencyShift = adcFreq; - imageToSelect = - (bool) (rfMirror ^ tunerMirror ^ adcFlip ^ selectPosImage); - iqmFsRateOfs = Frac28(frequencyShift, samplingFrequency); + frequency_shift = adc_freq; + image_to_select = + (bool) (rf_mirror ^ tuner_mirror ^ adc_flip ^ select_pos_image); + iqm_fs_rate_ofs = frac28(frequency_shift, sampling_frequency); - if (imageToSelect) - iqmFsRateOfs = ~iqmFsRateOfs + 1; + if (image_to_select) + iqm_fs_rate_ofs = ~iqm_fs_rate_ofs + 1; /* Program frequency shifter with tuner offset compensation */ - /* frequencyShift += tunerFreqOffset; TODO */ - WR32(devAddr, IQM_FS_RATE_OFS_LO__A, iqmFsRateOfs); - extAttr->iqmFsRateOfs = iqmFsRateOfs; - extAttr->posImage = (bool) (rfMirror ^ tunerMirror ^ selectPosImage); + /* frequency_shift += tuner_freq_offset; TODO */ + WR32(dev_addr, IQM_FS_RATE_OFS_LO__A, iqm_fs_rate_ofs); + ext_attr->iqm_fs_rate_ofs = iqm_fs_rate_ofs; + ext_attr->pos_image = (bool) (rf_mirror ^ tuner_mirror ^ select_pos_image); return (DRX_STS_OK); rw_error: @@ -4851,61 +4851,61 @@ rw_error: } /** -* \fn int GetSigStrength() +* \fn int get_sig_strength() * \brief Retrieve signal strength for VSB and QAM. * \param demod Pointer to demod instance * \param u16-t Pointer to signal strength data; range 0, .. , 100. * \return int. -* \retval DRX_STS_OK sigStrength contains valid data. -* \retval DRX_STS_INVALID_ARG sigStrength is NULL. -* \retval DRX_STS_ERROR Erroneous data, sigStrength contains invalid data. +* \retval DRX_STS_OK sig_strength contains valid data. +* \retval DRX_STS_INVALID_ARG sig_strength is NULL. +* \retval DRX_STS_ERROR Erroneous data, sig_strength contains invalid data. */ #define DRXJ_AGC_TOP 0x2800 #define DRXJ_AGC_SNS 0x1600 #define DRXJ_RFAGC_MAX 0x3fff #define DRXJ_RFAGC_MIN 0x800 -static int GetSigStrength(pDRXDemodInstance_t demod, u16 *sigStrength) -{ - u16 rfGain = 0; - u16 ifGain = 0; - u16 ifAgcSns = 0; - u16 ifAgcTop = 0; - u16 rfAgcMax = 0; - u16 rfAgcMin = 0; - pDRXJData_t extAttr = NULL; - struct i2c_device_addr *devAddr = NULL; - - extAttr = (pDRXJData_t) demod->myExtAttr; - devAddr = demod->myI2CDevAddr; - - RR16(devAddr, IQM_AF_AGC_IF__A, &ifGain); - ifGain &= IQM_AF_AGC_IF__M; - RR16(devAddr, IQM_AF_AGC_RF__A, &rfGain); - rfGain &= IQM_AF_AGC_RF__M; - - ifAgcSns = DRXJ_AGC_SNS; - ifAgcTop = DRXJ_AGC_TOP; - rfAgcMax = DRXJ_RFAGC_MAX; - rfAgcMin = DRXJ_RFAGC_MIN; - - if (ifGain > ifAgcTop) { - if (rfGain > rfAgcMax) - *sigStrength = 100; - else if (rfGain > rfAgcMin) { - CHK_ZERO(rfAgcMax - rfAgcMin); - *sigStrength = - 75 + 25 * (rfGain - rfAgcMin) / (rfAgcMax - - rfAgcMin); +static int get_sig_strength(pdrx_demod_instance_t demod, u16 *sig_strength) +{ + u16 rf_gain = 0; + u16 if_gain = 0; + u16 if_agc_sns = 0; + u16 if_agc_top = 0; + u16 rf_agc_max = 0; + u16 rf_agc_min = 0; + pdrxj_data_t ext_attr = NULL; + struct i2c_device_addr *dev_addr = NULL; + + ext_attr = (pdrxj_data_t) demod->my_ext_attr; + dev_addr = demod->my_i2c_dev_addr; + + RR16(dev_addr, IQM_AF_AGC_IF__A, &if_gain); + if_gain &= IQM_AF_AGC_IF__M; + RR16(dev_addr, IQM_AF_AGC_RF__A, &rf_gain); + rf_gain &= IQM_AF_AGC_RF__M; + + if_agc_sns = DRXJ_AGC_SNS; + if_agc_top = DRXJ_AGC_TOP; + rf_agc_max = DRXJ_RFAGC_MAX; + rf_agc_min = DRXJ_RFAGC_MIN; + + if (if_gain > if_agc_top) { + if (rf_gain > rf_agc_max) + *sig_strength = 100; + else if (rf_gain > rf_agc_min) { + CHK_ZERO(rf_agc_max - rf_agc_min); + *sig_strength = + 75 + 25 * (rf_gain - rf_agc_min) / (rf_agc_max - + rf_agc_min); } else - *sigStrength = 75; - } else if (ifGain > ifAgcSns) { - CHK_ZERO(ifAgcTop - ifAgcSns); - *sigStrength = - 20 + 55 * (ifGain - ifAgcSns) / (ifAgcTop - ifAgcSns); + *sig_strength = 75; + } else if (if_gain > if_agc_sns) { + CHK_ZERO(if_agc_top - if_agc_sns); + *sig_strength = + 20 + 55 * (if_gain - if_agc_sns) / (if_agc_top - if_agc_sns); } else { - CHK_ZERO(ifAgcSns); - *sigStrength = (20 * ifGain / ifAgcSns); + CHK_ZERO(if_agc_sns); + *sig_strength = (20 * if_gain / if_agc_sns); } return (DRX_STS_OK); @@ -4914,42 +4914,42 @@ rw_error: } /** -* \fn int GetAccPktErr() +* \fn int get_acc_pkt_err() * \brief Retrieve signal strength for VSB and QAM. * \param demod Pointer to demod instance -* \param packetErr Pointer to packet error +* \param packet_err Pointer to packet error * \return int. -* \retval DRX_STS_OK sigStrength contains valid data. -* \retval DRX_STS_INVALID_ARG sigStrength is NULL. -* \retval DRX_STS_ERROR Erroneous data, sigStrength contains invalid data. +* \retval DRX_STS_OK sig_strength contains valid data. +* \retval DRX_STS_INVALID_ARG sig_strength is NULL. +* \retval DRX_STS_ERROR Erroneous data, sig_strength contains invalid data. */ #ifdef DRXJ_SIGNAL_ACCUM_ERR -static int GetAccPktErr(pDRXDemodInstance_t demod, u16 *packetErr) +static int get_acc_pkt_err(pdrx_demod_instance_t demod, u16 *packet_err) { - static u16 pktErr; - static u16 lastPktErr; + static u16 pkt_err; + static u16 last_pkt_err; u16 data = 0; - pDRXJData_t extAttr = NULL; - struct i2c_device_addr *devAddr = NULL; + pdrxj_data_t ext_attr = NULL; + struct i2c_device_addr *dev_addr = NULL; - extAttr = (pDRXJData_t) demod->myExtAttr; - devAddr = demod->myI2CDevAddr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; + dev_addr = demod->my_i2c_dev_addr; - RR16(devAddr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, &data); - if (extAttr->resetPktErrAcc == true) { - lastPktErr = data; - pktErr = 0; - extAttr->resetPktErrAcc = false; + RR16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, &data); + if (ext_attr->reset_pkt_err_acc == true) { + last_pkt_err = data; + pkt_err = 0; + ext_attr->reset_pkt_err_acc = false; } - if (data < lastPktErr) { - pktErr += 0xffff - lastPktErr; - pktErr += data; + if (data < last_pkt_err) { + pkt_err += 0xffff - last_pkt_err; + pkt_err += data; } else { - pktErr += (data - lastPktErr); + pkt_err += (data - last_pkt_err); } - *packetErr = pktErr; - lastPktErr = data; + *packet_err = pkt_err; + last_pkt_err = data; return (DRX_STS_OK); rw_error: @@ -4965,16 +4965,16 @@ rw_error: * \retval DRX_STS_OK. * \retval DRX_STS_ERROR Erroneous data. */ -static int CtrlSetCfgResetPktErr(pDRXDemodInstance_t demod) +static int ctrl_set_cfg_reset_pkt_err(pdrx_demod_instance_t demod) { #ifdef DRXJ_SIGNAL_ACCUM_ERR - pDRXJData_t extAttr = NULL; - u16 packetError = 0; + pdrxj_data_t ext_attr = NULL; + u16 packet_error = 0; - extAttr = (pDRXJData_t) demod->myExtAttr; - extAttr->resetPktErrAcc = true; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr->reset_pkt_err_acc = true; /* call to reset counter */ - CHK_ERROR(GetAccPktErr(demod, &packetError)); + CHK_ERROR(get_acc_pkt_err(demod, &packet_error)); return (DRX_STS_OK); rw_error: @@ -4983,37 +4983,37 @@ rw_error: } /** -* \fn static short GetSTRFreqOffset() +* \fn static short get_str_freq_offset() * \brief Get symbol rate offset in QAM & 8VSB mode * \return Error code */ -static int GetSTRFreqOffset(pDRXDemodInstance_t demod, s32 *STRFreq) +static int get_str_freq_offset(pdrx_demod_instance_t demod, s32 *str_freq) { - u32 symbolFrequencyRatio = 0; - u32 symbolNomFrequencyRatio = 0; + u32 symbol_frequency_ratio = 0; + u32 symbol_nom_frequency_ratio = 0; enum drx_standard standard = DRX_STANDARD_UNKNOWN; - struct i2c_device_addr *devAddr = NULL; - pDRXJData_t extAttr = NULL; + struct i2c_device_addr *dev_addr = NULL; + pdrxj_data_t ext_attr = NULL; - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; - standard = extAttr->standard; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; + standard = ext_attr->standard; - ARR32(devAddr, IQM_RC_RATE_LO__A, &symbolFrequencyRatio); - symbolNomFrequencyRatio = extAttr->iqmRcRateOfs; + ARR32(dev_addr, IQM_RC_RATE_LO__A, &symbol_frequency_ratio); + symbol_nom_frequency_ratio = ext_attr->iqm_rc_rate_ofs; - if (symbolFrequencyRatio > symbolNomFrequencyRatio) - *STRFreq = + if (symbol_frequency_ratio > symbol_nom_frequency_ratio) + *str_freq = -1 * - FracTimes1e6((symbolFrequencyRatio - - symbolNomFrequencyRatio), - (symbolFrequencyRatio + (1 << 23))); + frac_times1e6((symbol_frequency_ratio - + symbol_nom_frequency_ratio), + (symbol_frequency_ratio + (1 << 23))); else - *STRFreq = - FracTimes1e6((symbolNomFrequencyRatio - - symbolFrequencyRatio), - (symbolFrequencyRatio + (1 << 23))); + *str_freq = + frac_times1e6((symbol_nom_frequency_ratio - + symbol_frequency_ratio), + (symbol_frequency_ratio + (1 << 23))); return (DRX_STS_OK); rw_error: @@ -5021,51 +5021,51 @@ rw_error: } /** -* \fn static short GetCTLFreqOffset -* \brief Get the value of CTLFreq in QAM & ATSC mode +* \fn static short get_ctl_freq_offset +* \brief Get the value of ctl_freq in QAM & ATSC mode * \return Error code */ -static int GetCTLFreqOffset(pDRXDemodInstance_t demod, s32 *CTLFreq) +static int get_ctl_freq_offset(pdrx_demod_instance_t demod, s32 *ctl_freq) { - s32 samplingFrequency = 0; - s32 currentFrequency = 0; - s32 nominalFrequency = 0; - s32 carrierFrequencyShift = 0; + s32 sampling_frequency = 0; + s32 current_frequency = 0; + s32 nominal_frequency = 0; + s32 carrier_frequency_shift = 0; s32 sign = 1; - u32 data64Hi = 0; - u32 data64Lo = 0; - pDRXJData_t extAttr = NULL; - pDRXCommonAttr_t commonAttr = NULL; - struct i2c_device_addr *devAddr = NULL; + u32 data64hi = 0; + u32 data64lo = 0; + pdrxj_data_t ext_attr = NULL; + pdrx_common_attr_t common_attr = NULL; + struct i2c_device_addr *dev_addr = NULL; - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; - commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; + common_attr = (pdrx_common_attr_t) demod->my_common_attr; - samplingFrequency = commonAttr->sysClockFreq / 3; + sampling_frequency = common_attr->sys_clock_freq / 3; /* both registers are sign extended */ - nominalFrequency = extAttr->iqmFsRateOfs; - ARR32(devAddr, IQM_FS_RATE_LO__A, (u32 *) ¤tFrequency); + nominal_frequency = ext_attr->iqm_fs_rate_ofs; + ARR32(dev_addr, IQM_FS_RATE_LO__A, (u32 *) ¤t_frequency); - if (extAttr->posImage == true) { + if (ext_attr->pos_image == true) { /* negative image */ - carrierFrequencyShift = nominalFrequency - currentFrequency; + carrier_frequency_shift = nominal_frequency - current_frequency; } else { /* positive image */ - carrierFrequencyShift = currentFrequency - nominalFrequency; + carrier_frequency_shift = current_frequency - nominal_frequency; } /* carrier Frequency Shift In Hz */ - if (carrierFrequencyShift < 0) { + if (carrier_frequency_shift < 0) { sign = -1; - carrierFrequencyShift *= sign; + carrier_frequency_shift *= sign; } - /* *CTLFreq = carrierFrequencyShift * 50.625e6 / (1 << 28); */ - Mult32(carrierFrequencyShift, samplingFrequency, &data64Hi, &data64Lo); - *CTLFreq = - (s32) ((((data64Lo >> 28) & 0xf) | (data64Hi << 4)) * sign); + /* *ctl_freq = carrier_frequency_shift * 50.625e6 / (1 << 28); */ + mult32(carrier_frequency_shift, sampling_frequency, &data64hi, &data64lo); + *ctl_freq = + (s32) ((((data64lo >> 28) & 0xf) | (data64hi << 4)) * sign); return (DRX_STS_OK); rw_error: @@ -5075,161 +5075,161 @@ rw_error: /*============================================================================*/ /** -* \fn int SetAgcRf () +* \fn int set_agc_rf () * \brief Configure RF AGC * \param demod instance of demodulator. -* \param agcSettings AGC configuration structure +* \param agc_settings AGC configuration structure * \return int. */ static int -SetAgcRf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings, bool atomic) +set_agc_rf(pdrx_demod_instance_t demod, p_drxj_cfg_agc_t agc_settings, bool atomic) { - struct i2c_device_addr *devAddr = NULL; - pDRXJData_t extAttr = NULL; - pDRXJCfgAgc_t pAgcSettings = NULL; - pDRXCommonAttr_t commonAttr = NULL; - DRXWriteReg16Func_t ScuWr16 = NULL; - DRXReadReg16Func_t ScuRr16 = NULL; + struct i2c_device_addr *dev_addr = NULL; + pdrxj_data_t ext_attr = NULL; + p_drxj_cfg_agc_t p_agc_settings = NULL; + pdrx_common_attr_t common_attr = NULL; + drx_write_reg16func_t scu_wr16 = NULL; + drx_read_reg16func_t scu_rr16 = NULL; - commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; + common_attr = (pdrx_common_attr_t) demod->my_common_attr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; if (atomic) { - ScuRr16 = DRXJ_DAP_SCU_AtomicReadReg16; - ScuWr16 = DRXJ_DAP_SCU_AtomicWriteReg16; + scu_rr16 = drxj_dap_scu_atomic_read_reg16; + scu_wr16 = drxj_dap_scu_atomic_write_reg16; } else { - ScuRr16 = DRXJ_DAP.readReg16Func; - ScuWr16 = DRXJ_DAP.writeReg16Func; + scu_rr16 = DRXJ_DAP.read_reg16func; + scu_wr16 = DRXJ_DAP.write_reg16func; } /* Configure AGC only if standard is currently active */ - if ((extAttr->standard == agcSettings->standard) || - (DRXJ_ISQAMSTD(extAttr->standard) && - DRXJ_ISQAMSTD(agcSettings->standard)) || - (DRXJ_ISATVSTD(extAttr->standard) && - DRXJ_ISATVSTD(agcSettings->standard))) { + if ((ext_attr->standard == agc_settings->standard) || + (DRXJ_ISQAMSTD(ext_attr->standard) && + DRXJ_ISQAMSTD(agc_settings->standard)) || + (DRXJ_ISATVSTD(ext_attr->standard) && + DRXJ_ISATVSTD(agc_settings->standard))) { u16 data = 0; - switch (agcSettings->ctrlMode) { + switch (agc_settings->ctrl_mode) { case DRX_AGC_CTRL_AUTO: /* Enable RF AGC DAC */ - RR16(devAddr, IQM_AF_STDBY__A, &data); + RR16(dev_addr, IQM_AF_STDBY__A, &data); data |= IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE; - WR16(devAddr, IQM_AF_STDBY__A, data); + WR16(dev_addr, IQM_AF_STDBY__A, data); /* Enable SCU RF AGC loop */ - CHK_ERROR((*ScuRr16) - (devAddr, SCU_RAM_AGC_KI__A, &data, 0)); + CHK_ERROR((*scu_rr16) + (dev_addr, SCU_RAM_AGC_KI__A, &data, 0)); data &= ~SCU_RAM_AGC_KI_RF__M; - if (extAttr->standard == DRX_STANDARD_8VSB) { + if (ext_attr->standard == DRX_STANDARD_8VSB) { data |= (2 << SCU_RAM_AGC_KI_RF__B); - } else if (DRXJ_ISQAMSTD(extAttr->standard)) { + } else if (DRXJ_ISQAMSTD(ext_attr->standard)) { data |= (5 << SCU_RAM_AGC_KI_RF__B); } else { data |= (4 << SCU_RAM_AGC_KI_RF__B); } - if (commonAttr->tunerRfAgcPol) { + if (common_attr->tuner_rf_agc_pol) { data |= SCU_RAM_AGC_KI_INV_RF_POL__M; } else { data &= ~SCU_RAM_AGC_KI_INV_RF_POL__M; } - CHK_ERROR((*ScuWr16) - (devAddr, SCU_RAM_AGC_KI__A, data, 0)); + CHK_ERROR((*scu_wr16) + (dev_addr, SCU_RAM_AGC_KI__A, data, 0)); /* Set speed ( using complementary reduction value ) */ - CHK_ERROR((*ScuRr16) - (devAddr, SCU_RAM_AGC_KI_RED__A, &data, 0)); + CHK_ERROR((*scu_rr16) + (dev_addr, SCU_RAM_AGC_KI_RED__A, &data, 0)); data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M; - CHK_ERROR((*ScuWr16) (devAddr, SCU_RAM_AGC_KI_RED__A, + CHK_ERROR((*scu_wr16) (dev_addr, SCU_RAM_AGC_KI_RED__A, (~ - (agcSettings-> + (agc_settings-> speed << SCU_RAM_AGC_KI_RED_RAGC_RED__B) & SCU_RAM_AGC_KI_RED_RAGC_RED__M) | data, 0)); - if (agcSettings->standard == DRX_STANDARD_8VSB) - pAgcSettings = &(extAttr->vsbIfAgcCfg); - else if (DRXJ_ISQAMSTD(agcSettings->standard)) - pAgcSettings = &(extAttr->qamIfAgcCfg); - else if (DRXJ_ISATVSTD(agcSettings->standard)) - pAgcSettings = &(extAttr->atvIfAgcCfg); + if (agc_settings->standard == DRX_STANDARD_8VSB) + p_agc_settings = &(ext_attr->vsb_if_agc_cfg); + else if (DRXJ_ISQAMSTD(agc_settings->standard)) + p_agc_settings = &(ext_attr->qam_if_agc_cfg); + else if (DRXJ_ISATVSTD(agc_settings->standard)) + p_agc_settings = &(ext_attr->atv_if_agc_cfg); else return (DRX_STS_INVALID_ARG); /* Set TOP, only if IF-AGC is in AUTO mode */ - if (pAgcSettings->ctrlMode == DRX_AGC_CTRL_AUTO) { - CHK_ERROR((*ScuWr16) - (devAddr, + if (p_agc_settings->ctrl_mode == DRX_AGC_CTRL_AUTO) { + CHK_ERROR((*scu_wr16) + (dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, - agcSettings->top, 0)); - CHK_ERROR((*ScuWr16) - (devAddr, + agc_settings->top, 0)); + CHK_ERROR((*scu_wr16) + (dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, - agcSettings->top, 0)); + agc_settings->top, 0)); } /* Cut-Off current */ - CHK_ERROR((*ScuWr16) - (devAddr, SCU_RAM_AGC_RF_IACCU_HI_CO__A, - agcSettings->cutOffCurrent, 0)); + CHK_ERROR((*scu_wr16) + (dev_addr, SCU_RAM_AGC_RF_IACCU_HI_CO__A, + agc_settings->cut_off_current, 0)); break; case DRX_AGC_CTRL_USER: /* Enable RF AGC DAC */ - RR16(devAddr, IQM_AF_STDBY__A, &data); + RR16(dev_addr, IQM_AF_STDBY__A, &data); data |= IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE; - WR16(devAddr, IQM_AF_STDBY__A, data); + WR16(dev_addr, IQM_AF_STDBY__A, data); /* Disable SCU RF AGC loop */ - CHK_ERROR((*ScuRr16) - (devAddr, SCU_RAM_AGC_KI__A, &data, 0)); + CHK_ERROR((*scu_rr16) + (dev_addr, SCU_RAM_AGC_KI__A, &data, 0)); data &= ~SCU_RAM_AGC_KI_RF__M; - if (commonAttr->tunerRfAgcPol) { + if (common_attr->tuner_rf_agc_pol) { data |= SCU_RAM_AGC_KI_INV_RF_POL__M; } else { data &= ~SCU_RAM_AGC_KI_INV_RF_POL__M; } - CHK_ERROR((*ScuWr16) - (devAddr, SCU_RAM_AGC_KI__A, data, 0)); + CHK_ERROR((*scu_wr16) + (dev_addr, SCU_RAM_AGC_KI__A, data, 0)); /* Write value to output pin */ - CHK_ERROR((*ScuWr16) - (devAddr, SCU_RAM_AGC_RF_IACCU_HI__A, - agcSettings->outputLevel, 0)); + CHK_ERROR((*scu_wr16) + (dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, + agc_settings->output_level, 0)); break; case DRX_AGC_CTRL_OFF: /* Disable RF AGC DAC */ - RR16(devAddr, IQM_AF_STDBY__A, &data); + RR16(dev_addr, IQM_AF_STDBY__A, &data); data &= (~IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE); - WR16(devAddr, IQM_AF_STDBY__A, data); + WR16(dev_addr, IQM_AF_STDBY__A, data); /* Disable SCU RF AGC loop */ - CHK_ERROR((*ScuRr16) - (devAddr, SCU_RAM_AGC_KI__A, &data, 0)); + CHK_ERROR((*scu_rr16) + (dev_addr, SCU_RAM_AGC_KI__A, &data, 0)); data &= ~SCU_RAM_AGC_KI_RF__M; - CHK_ERROR((*ScuWr16) - (devAddr, SCU_RAM_AGC_KI__A, data, 0)); + CHK_ERROR((*scu_wr16) + (dev_addr, SCU_RAM_AGC_KI__A, data, 0)); break; default: return (DRX_STS_INVALID_ARG); - } /* switch ( agcsettings->ctrlMode ) */ + } /* switch ( agcsettings->ctrl_mode ) */ } /* Store rf agc settings */ - switch (agcSettings->standard) { + switch (agc_settings->standard) { case DRX_STANDARD_8VSB: - extAttr->vsbRfAgcCfg = *agcSettings; + ext_attr->vsb_rf_agc_cfg = *agc_settings; break; #ifndef DRXJ_VSB_ONLY case DRX_STANDARD_ITU_A: case DRX_STANDARD_ITU_B: case DRX_STANDARD_ITU_C: - extAttr->qamRfAgcCfg = *agcSettings; + ext_attr->qam_rf_agc_cfg = *agc_settings; break; #endif #ifndef DRXJ_DIGITAL_ONLY @@ -5240,7 +5240,7 @@ SetAgcRf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings, bool atomic) case DRX_STANDARD_PAL_SECAM_LP: case DRX_STANDARD_NTSC: case DRX_STANDARD_FM: - extAttr->atvRfAgcCfg = *agcSettings; + ext_attr->atv_rf_agc_cfg = *agc_settings; break; #endif default: @@ -5253,33 +5253,33 @@ rw_error: } /** -* \fn int GetAgcRf () +* \fn int get_agc_rf () * \brief get configuration of RF AGC * \param demod instance of demodulator. -* \param agcSettings AGC configuration structure +* \param agc_settings AGC configuration structure * \return int. */ static int -GetAgcRf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings) +get_agc_rf(pdrx_demod_instance_t demod, p_drxj_cfg_agc_t agc_settings) { - struct i2c_device_addr *devAddr = NULL; - pDRXJData_t extAttr = NULL; + struct i2c_device_addr *dev_addr = NULL; + pdrxj_data_t ext_attr = NULL; enum drx_standard standard = DRX_STANDARD_UNKNOWN; - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* Return stored AGC settings */ - standard = agcSettings->standard; - switch (agcSettings->standard) { + standard = agc_settings->standard; + switch (agc_settings->standard) { case DRX_STANDARD_8VSB: - *agcSettings = extAttr->vsbRfAgcCfg; + *agc_settings = ext_attr->vsb_rf_agc_cfg; break; #ifndef DRXJ_VSB_ONLY case DRX_STANDARD_ITU_A: case DRX_STANDARD_ITU_B: case DRX_STANDARD_ITU_C: - *agcSettings = extAttr->qamRfAgcCfg; + *agc_settings = ext_attr->qam_rf_agc_cfg; break; #endif #ifndef DRXJ_DIGITAL_ONLY @@ -5290,22 +5290,22 @@ GetAgcRf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings) case DRX_STANDARD_PAL_SECAM_LP: case DRX_STANDARD_NTSC: case DRX_STANDARD_FM: - *agcSettings = extAttr->atvRfAgcCfg; + *agc_settings = ext_attr->atv_rf_agc_cfg; break; #endif default: return (DRX_STS_ERROR); } - agcSettings->standard = standard; + agc_settings->standard = standard; /* Get AGC output only if standard is currently active. */ - if ((extAttr->standard == agcSettings->standard) || - (DRXJ_ISQAMSTD(extAttr->standard) && - DRXJ_ISQAMSTD(agcSettings->standard)) || - (DRXJ_ISATVSTD(extAttr->standard) && - DRXJ_ISATVSTD(agcSettings->standard))) { - SARR16(devAddr, SCU_RAM_AGC_RF_IACCU_HI__A, - &(agcSettings->outputLevel)); + if ((ext_attr->standard == agc_settings->standard) || + (DRXJ_ISQAMSTD(ext_attr->standard) && + DRXJ_ISQAMSTD(agc_settings->standard)) || + (DRXJ_ISATVSTD(ext_attr->standard) && + DRXJ_ISATVSTD(agc_settings->standard))) { + SARR16(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, + &(agc_settings->output_level)); } return (DRX_STS_OK); @@ -5314,108 +5314,108 @@ rw_error: } /** -* \fn int SetAgcIf () +* \fn int set_agc_if () * \brief Configure If AGC * \param demod instance of demodulator. -* \param agcSettings AGC configuration structure +* \param agc_settings AGC configuration structure * \return int. */ static int -SetAgcIf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings, bool atomic) +set_agc_if(pdrx_demod_instance_t demod, p_drxj_cfg_agc_t agc_settings, bool atomic) { - struct i2c_device_addr *devAddr = NULL; - pDRXJData_t extAttr = NULL; - pDRXJCfgAgc_t pAgcSettings = NULL; - pDRXCommonAttr_t commonAttr = NULL; - DRXWriteReg16Func_t ScuWr16 = NULL; - DRXReadReg16Func_t ScuRr16 = NULL; + struct i2c_device_addr *dev_addr = NULL; + pdrxj_data_t ext_attr = NULL; + p_drxj_cfg_agc_t p_agc_settings = NULL; + pdrx_common_attr_t common_attr = NULL; + drx_write_reg16func_t scu_wr16 = NULL; + drx_read_reg16func_t scu_rr16 = NULL; - commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; + common_attr = (pdrx_common_attr_t) demod->my_common_attr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; if (atomic) { - ScuRr16 = DRXJ_DAP_SCU_AtomicReadReg16; - ScuWr16 = DRXJ_DAP_SCU_AtomicWriteReg16; + scu_rr16 = drxj_dap_scu_atomic_read_reg16; + scu_wr16 = drxj_dap_scu_atomic_write_reg16; } else { - ScuRr16 = DRXJ_DAP.readReg16Func; - ScuWr16 = DRXJ_DAP.writeReg16Func; + scu_rr16 = DRXJ_DAP.read_reg16func; + scu_wr16 = DRXJ_DAP.write_reg16func; } /* Configure AGC only if standard is currently active */ - if ((extAttr->standard == agcSettings->standard) || - (DRXJ_ISQAMSTD(extAttr->standard) && - DRXJ_ISQAMSTD(agcSettings->standard)) || - (DRXJ_ISATVSTD(extAttr->standard) && - DRXJ_ISATVSTD(agcSettings->standard))) { + if ((ext_attr->standard == agc_settings->standard) || + (DRXJ_ISQAMSTD(ext_attr->standard) && + DRXJ_ISQAMSTD(agc_settings->standard)) || + (DRXJ_ISATVSTD(ext_attr->standard) && + DRXJ_ISATVSTD(agc_settings->standard))) { u16 data = 0; - switch (agcSettings->ctrlMode) { + switch (agc_settings->ctrl_mode) { case DRX_AGC_CTRL_AUTO: /* Enable IF AGC DAC */ - RR16(devAddr, IQM_AF_STDBY__A, &data); + RR16(dev_addr, IQM_AF_STDBY__A, &data); data |= IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE; - WR16(devAddr, IQM_AF_STDBY__A, data); + WR16(dev_addr, IQM_AF_STDBY__A, data); /* Enable SCU IF AGC loop */ - CHK_ERROR((*ScuRr16) - (devAddr, SCU_RAM_AGC_KI__A, &data, 0)); + CHK_ERROR((*scu_rr16) + (dev_addr, SCU_RAM_AGC_KI__A, &data, 0)); data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M; data &= ~SCU_RAM_AGC_KI_IF__M; - if (extAttr->standard == DRX_STANDARD_8VSB) { + if (ext_attr->standard == DRX_STANDARD_8VSB) { data |= (3 << SCU_RAM_AGC_KI_IF__B); - } else if (DRXJ_ISQAMSTD(extAttr->standard)) { + } else if (DRXJ_ISQAMSTD(ext_attr->standard)) { data |= (6 << SCU_RAM_AGC_KI_IF__B); } else { data |= (5 << SCU_RAM_AGC_KI_IF__B); } - if (commonAttr->tunerIfAgcPol) { + if (common_attr->tuner_if_agc_pol) { data |= SCU_RAM_AGC_KI_INV_IF_POL__M; } else { data &= ~SCU_RAM_AGC_KI_INV_IF_POL__M; } - CHK_ERROR((*ScuWr16) - (devAddr, SCU_RAM_AGC_KI__A, data, 0)); + CHK_ERROR((*scu_wr16) + (dev_addr, SCU_RAM_AGC_KI__A, data, 0)); /* Set speed (using complementary reduction value) */ - CHK_ERROR((*ScuRr16) - (devAddr, SCU_RAM_AGC_KI_RED__A, &data, 0)); + CHK_ERROR((*scu_rr16) + (dev_addr, SCU_RAM_AGC_KI_RED__A, &data, 0)); data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M; - CHK_ERROR((*ScuWr16) (devAddr, SCU_RAM_AGC_KI_RED__A, + CHK_ERROR((*scu_wr16) (dev_addr, SCU_RAM_AGC_KI_RED__A, (~ - (agcSettings-> + (agc_settings-> speed << SCU_RAM_AGC_KI_RED_IAGC_RED__B) & SCU_RAM_AGC_KI_RED_IAGC_RED__M) | data, 0)); - if (agcSettings->standard == DRX_STANDARD_8VSB) - pAgcSettings = &(extAttr->vsbRfAgcCfg); - else if (DRXJ_ISQAMSTD(agcSettings->standard)) - pAgcSettings = &(extAttr->qamRfAgcCfg); - else if (DRXJ_ISATVSTD(agcSettings->standard)) - pAgcSettings = &(extAttr->atvRfAgcCfg); + if (agc_settings->standard == DRX_STANDARD_8VSB) + p_agc_settings = &(ext_attr->vsb_rf_agc_cfg); + else if (DRXJ_ISQAMSTD(agc_settings->standard)) + p_agc_settings = &(ext_attr->qam_rf_agc_cfg); + else if (DRXJ_ISATVSTD(agc_settings->standard)) + p_agc_settings = &(ext_attr->atv_rf_agc_cfg); else return (DRX_STS_INVALID_ARG); /* Restore TOP */ - if (pAgcSettings->ctrlMode == DRX_AGC_CTRL_AUTO) { - CHK_ERROR((*ScuWr16) - (devAddr, + if (p_agc_settings->ctrl_mode == DRX_AGC_CTRL_AUTO) { + CHK_ERROR((*scu_wr16) + (dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, - pAgcSettings->top, 0)); - CHK_ERROR((*ScuWr16) - (devAddr, + p_agc_settings->top, 0)); + CHK_ERROR((*scu_wr16) + (dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, - pAgcSettings->top, 0)); + p_agc_settings->top, 0)); } else { - CHK_ERROR((*ScuWr16) - (devAddr, + CHK_ERROR((*scu_wr16) + (dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, 0, 0)); - CHK_ERROR((*ScuWr16) - (devAddr, + CHK_ERROR((*scu_wr16) + (dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, 0, 0)); } @@ -5424,64 +5424,64 @@ SetAgcIf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings, bool atomic) case DRX_AGC_CTRL_USER: /* Enable IF AGC DAC */ - RR16(devAddr, IQM_AF_STDBY__A, &data); + RR16(dev_addr, IQM_AF_STDBY__A, &data); data |= IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE; - WR16(devAddr, IQM_AF_STDBY__A, data); + WR16(dev_addr, IQM_AF_STDBY__A, data); /* Disable SCU IF AGC loop */ - CHK_ERROR((*ScuRr16) - (devAddr, SCU_RAM_AGC_KI__A, &data, 0)); + CHK_ERROR((*scu_rr16) + (dev_addr, SCU_RAM_AGC_KI__A, &data, 0)); data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M; data |= SCU_RAM_AGC_KI_IF_AGC_DISABLE__M; - if (commonAttr->tunerIfAgcPol) { + if (common_attr->tuner_if_agc_pol) { data |= SCU_RAM_AGC_KI_INV_IF_POL__M; } else { data &= ~SCU_RAM_AGC_KI_INV_IF_POL__M; } - CHK_ERROR((*ScuWr16) - (devAddr, SCU_RAM_AGC_KI__A, data, 0)); + CHK_ERROR((*scu_wr16) + (dev_addr, SCU_RAM_AGC_KI__A, data, 0)); /* Write value to output pin */ - CHK_ERROR((*ScuWr16) - (devAddr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, - agcSettings->outputLevel, 0)); + CHK_ERROR((*scu_wr16) + (dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, + agc_settings->output_level, 0)); break; case DRX_AGC_CTRL_OFF: /* Disable If AGC DAC */ - RR16(devAddr, IQM_AF_STDBY__A, &data); + RR16(dev_addr, IQM_AF_STDBY__A, &data); data &= (~IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE); - WR16(devAddr, IQM_AF_STDBY__A, data); + WR16(dev_addr, IQM_AF_STDBY__A, data); /* Disable SCU IF AGC loop */ - CHK_ERROR((*ScuRr16) - (devAddr, SCU_RAM_AGC_KI__A, &data, 0)); + CHK_ERROR((*scu_rr16) + (dev_addr, SCU_RAM_AGC_KI__A, &data, 0)); data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M; data |= SCU_RAM_AGC_KI_IF_AGC_DISABLE__M; - CHK_ERROR((*ScuWr16) - (devAddr, SCU_RAM_AGC_KI__A, data, 0)); + CHK_ERROR((*scu_wr16) + (dev_addr, SCU_RAM_AGC_KI__A, data, 0)); break; default: return (DRX_STS_INVALID_ARG); - } /* switch ( agcsettings->ctrlMode ) */ + } /* switch ( agcsettings->ctrl_mode ) */ /* always set the top to support configurations without if-loop */ - CHK_ERROR((*ScuWr16) (devAddr, + CHK_ERROR((*scu_wr16) (dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, - agcSettings->top, 0)); + agc_settings->top, 0)); } /* Store if agc settings */ - switch (agcSettings->standard) { + switch (agc_settings->standard) { case DRX_STANDARD_8VSB: - extAttr->vsbIfAgcCfg = *agcSettings; + ext_attr->vsb_if_agc_cfg = *agc_settings; break; #ifndef DRXJ_VSB_ONLY case DRX_STANDARD_ITU_A: case DRX_STANDARD_ITU_B: case DRX_STANDARD_ITU_C: - extAttr->qamIfAgcCfg = *agcSettings; + ext_attr->qam_if_agc_cfg = *agc_settings; break; #endif #ifndef DRXJ_DIGITAL_ONLY @@ -5492,7 +5492,7 @@ SetAgcIf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings, bool atomic) case DRX_STANDARD_PAL_SECAM_LP: case DRX_STANDARD_NTSC: case DRX_STANDARD_FM: - extAttr->atvIfAgcCfg = *agcSettings; + ext_attr->atv_if_agc_cfg = *agc_settings; break; #endif default: @@ -5505,33 +5505,33 @@ rw_error: } /** -* \fn int GetAgcIf () +* \fn int get_agc_if () * \brief get configuration of If AGC * \param demod instance of demodulator. -* \param agcSettings AGC configuration structure +* \param agc_settings AGC configuration structure * \return int. */ static int -GetAgcIf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings) +get_agc_if(pdrx_demod_instance_t demod, p_drxj_cfg_agc_t agc_settings) { - struct i2c_device_addr *devAddr = NULL; - pDRXJData_t extAttr = NULL; + struct i2c_device_addr *dev_addr = NULL; + pdrxj_data_t ext_attr = NULL; enum drx_standard standard = DRX_STANDARD_UNKNOWN; - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* Return stored ATV AGC settings */ - standard = agcSettings->standard; - switch (agcSettings->standard) { + standard = agc_settings->standard; + switch (agc_settings->standard) { case DRX_STANDARD_8VSB: - *agcSettings = extAttr->vsbIfAgcCfg; + *agc_settings = ext_attr->vsb_if_agc_cfg; break; #ifndef DRXJ_VSB_ONLY case DRX_STANDARD_ITU_A: case DRX_STANDARD_ITU_B: case DRX_STANDARD_ITU_C: - *agcSettings = extAttr->qamIfAgcCfg; + *agc_settings = ext_attr->qam_if_agc_cfg; break; #endif #ifndef DRXJ_DIGITAL_ONLY @@ -5542,23 +5542,23 @@ GetAgcIf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings) case DRX_STANDARD_PAL_SECAM_LP: case DRX_STANDARD_NTSC: case DRX_STANDARD_FM: - *agcSettings = extAttr->atvIfAgcCfg; + *agc_settings = ext_attr->atv_if_agc_cfg; break; #endif default: return (DRX_STS_ERROR); } - agcSettings->standard = standard; + agc_settings->standard = standard; /* Get AGC output only if standard is currently active */ - if ((extAttr->standard == agcSettings->standard) || - (DRXJ_ISQAMSTD(extAttr->standard) && - DRXJ_ISQAMSTD(agcSettings->standard)) || - (DRXJ_ISATVSTD(extAttr->standard) && - DRXJ_ISATVSTD(agcSettings->standard))) { + if ((ext_attr->standard == agc_settings->standard) || + (DRXJ_ISQAMSTD(ext_attr->standard) && + DRXJ_ISQAMSTD(agc_settings->standard)) || + (DRXJ_ISATVSTD(ext_attr->standard) && + DRXJ_ISATVSTD(agc_settings->standard))) { /* read output level */ - SARR16(devAddr, SCU_RAM_AGC_IF_IACCU_HI__A, - &(agcSettings->outputLevel)); + SARR16(dev_addr, SCU_RAM_AGC_IF_IACCU_HI__A, + &(agc_settings->output_level)); } return (DRX_STS_OK); @@ -5567,21 +5567,21 @@ rw_error: } /** -* \fn int SetIqmAf () +* \fn int set_iqm_af () * \brief Configure IQM AF registers * \param demod instance of demodulator. * \param active * \return int. */ -static int SetIqmAf(pDRXDemodInstance_t demod, bool active) +static int set_iqm_af(pdrx_demod_instance_t demod, bool active) { u16 data = 0; - struct i2c_device_addr *devAddr = NULL; + struct i2c_device_addr *dev_addr = NULL; - devAddr = demod->myI2CDevAddr; + dev_addr = demod->my_i2c_dev_addr; /* Configure IQM */ - RR16(devAddr, IQM_AF_STDBY__A, &data); + RR16(dev_addr, IQM_AF_STDBY__A, &data); if (!active) { data &= ((~IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE) @@ -5597,7 +5597,7 @@ static int SetIqmAf(pDRXDemodInstance_t demod, bool active) | IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE | IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE); } - WR16(devAddr, IQM_AF_STDBY__A, data); + WR16(dev_addr, IQM_AF_STDBY__A, data); return (DRX_STS_OK); rw_error: @@ -5615,55 +5615,55 @@ rw_error: /*============================================================================*/ /** -* \fn int PowerDownVSB () +* \fn int power_down_vsb () * \brief Powr down QAM related blocks. * \param demod instance of demodulator. * \param channel pointer to channel data. * \return int. */ -static int PowerDownVSB(pDRXDemodInstance_t demod, bool primary) +static int power_down_vsb(pdrx_demod_instance_t demod, bool primary) { - struct i2c_device_addr *devAddr = NULL; - DRXJSCUCmd_t cmdSCU = { /* command */ 0, - /* parameterLen */ 0, - /* resultLen */ 0, + struct i2c_device_addr *dev_addr = NULL; + drxjscu_cmd_t cmd_scu = { /* command */ 0, + /* parameter_len */ 0, + /* result_len */ 0, /* *parameter */ NULL, /* *result */ NULL }; - u16 cmdResult = 0; - pDRXJData_t extAttr = NULL; - DRXCfgMPEGOutput_t cfgMPEGOutput; + u16 cmd_result = 0; + pdrxj_data_t ext_attr = NULL; + drx_cfg_mpeg_output_t cfg_mpeg_output; - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* STOP demodulator reset of FEC and VSB HW */ - cmdSCU.command = SCU_RAM_COMMAND_STANDARD_VSB | + cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB | SCU_RAM_COMMAND_CMD_DEMOD_STOP; - cmdSCU.parameterLen = 0; - cmdSCU.resultLen = 1; - cmdSCU.parameter = NULL; - cmdSCU.result = &cmdResult; - CHK_ERROR(SCUCommand(devAddr, &cmdSCU)); + cmd_scu.parameter_len = 0; + cmd_scu.result_len = 1; + cmd_scu.parameter = NULL; + cmd_scu.result = &cmd_result; + CHK_ERROR(scu_command(dev_addr, &cmd_scu)); /* stop all comm_exec */ - WR16(devAddr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP); - WR16(devAddr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP); + WR16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP); + WR16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP); if (primary == true) { - WR16(devAddr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP); - CHK_ERROR(SetIqmAf(demod, false)); + WR16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP); + CHK_ERROR(set_iqm_af(demod, false)); } else { - WR16(devAddr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP); - WR16(devAddr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP); - WR16(devAddr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP); - WR16(devAddr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP); - WR16(devAddr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP); + WR16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP); + WR16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP); + WR16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP); + WR16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP); + WR16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP); } - cfgMPEGOutput.enableMPEGOutput = false; - CHK_ERROR(CtrlSetCfgMPEGOutput(demod, &cfgMPEGOutput)); + cfg_mpeg_output.enable_mpeg_output = false; + CHK_ERROR(ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output)); return (DRX_STS_OK); rw_error: @@ -5671,14 +5671,14 @@ rw_error: } /** -* \fn int SetVSBLeakNGain () +* \fn int set_vsb_leak_n_gain () * \brief Set ATSC demod. * \param demod instance of demodulator. * \return int. */ -static int SetVSBLeakNGain(pDRXDemodInstance_t demod) +static int set_vsb_leak_n_gain(pdrx_demod_instance_t demod) { - struct i2c_device_addr *devAddr = NULL; + struct i2c_device_addr *dev_addr = NULL; const u8 vsb_ffe_leak_gain_ram0[] = { DRXJ_16TO8(0x8), /* FFETRAINLKRATIO1 */ @@ -5868,10 +5868,10 @@ static int SetVSBLeakNGain(pDRXDemodInstance_t demod) DRXJ_16TO8(0x1212) /* DFEDDM2GAIN */ }; - devAddr = demod->myI2CDevAddr; - WRB(devAddr, VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__A, + dev_addr = demod->my_i2c_dev_addr; + WRB(dev_addr, VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__A, sizeof(vsb_ffe_leak_gain_ram0), ((u8 *) vsb_ffe_leak_gain_ram0)); - WRB(devAddr, VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__A, + WRB(dev_addr, VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__A, sizeof(vsb_ffe_leak_gain_ram1), ((u8 *) vsb_ffe_leak_gain_ram1)); return (DRX_STS_OK); @@ -5880,20 +5880,20 @@ rw_error: } /** -* \fn int SetVSB() +* \fn int set_vsb() * \brief Set 8VSB demod. * \param demod instance of demodulator. * \return int. * */ -static int SetVSB(pDRXDemodInstance_t demod) +static int set_vsb(pdrx_demod_instance_t demod) { - struct i2c_device_addr *devAddr = NULL; - u16 cmdResult = 0; - u16 cmdParam = 0; - pDRXCommonAttr_t commonAttr = NULL; - DRXJSCUCmd_t cmdSCU; - pDRXJData_t extAttr = NULL; + struct i2c_device_addr *dev_addr = NULL; + u16 cmd_result = 0; + u16 cmd_param = 0; + pdrx_common_attr_t common_attr = NULL; + drxjscu_cmd_t cmd_scu; + pdrxj_data_t ext_attr = NULL; const u8 vsb_taps_re[] = { DRXJ_16TO8(-2), /* re0 */ DRXJ_16TO8(4), /* re1 */ @@ -5925,175 +5925,175 @@ static int SetVSB(pDRXDemodInstance_t demod) DRXJ_16TO8(629) /* re27 */ }; - devAddr = demod->myI2CDevAddr; - commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; - extAttr = (pDRXJData_t) demod->myExtAttr; + dev_addr = demod->my_i2c_dev_addr; + common_attr = (pdrx_common_attr_t) demod->my_common_attr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* stop all comm_exec */ - WR16(devAddr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP); - WR16(devAddr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP); - WR16(devAddr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP); - WR16(devAddr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP); - WR16(devAddr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP); - WR16(devAddr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP); - WR16(devAddr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP); + WR16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP); + WR16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP); + WR16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP); + WR16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP); + WR16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP); + WR16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP); + WR16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP); /* reset demodulator */ - cmdSCU.command = SCU_RAM_COMMAND_STANDARD_VSB + cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB | SCU_RAM_COMMAND_CMD_DEMOD_RESET; - cmdSCU.parameterLen = 0; - cmdSCU.resultLen = 1; - cmdSCU.parameter = NULL; - cmdSCU.result = &cmdResult; - CHK_ERROR(SCUCommand(devAddr, &cmdSCU)); - - WR16(devAddr, IQM_AF_DCF_BYPASS__A, 1); - WR16(devAddr, IQM_FS_ADJ_SEL__A, IQM_FS_ADJ_SEL_B_VSB); - WR16(devAddr, IQM_RC_ADJ_SEL__A, IQM_RC_ADJ_SEL_B_VSB); - extAttr->iqmRcRateOfs = 0x00AD0D79; - WR32(devAddr, IQM_RC_RATE_OFS_LO__A, extAttr->iqmRcRateOfs); - WR16(devAddr, VSB_TOP_CFAGC_GAINSHIFT__A, 4); - WR16(devAddr, VSB_TOP_CYGN1TRK__A, 1); - - WR16(devAddr, IQM_RC_CROUT_ENA__A, 1); - WR16(devAddr, IQM_RC_STRETCH__A, 28); - WR16(devAddr, IQM_RT_ACTIVE__A, 0); - WR16(devAddr, IQM_CF_SYMMETRIC__A, 0); - WR16(devAddr, IQM_CF_MIDTAP__A, 3); - WR16(devAddr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_VSB__M); - WR16(devAddr, IQM_CF_SCALE__A, 1393); - WR16(devAddr, IQM_CF_SCALE_SH__A, 0); - WR16(devAddr, IQM_CF_POW_MEAS_LEN__A, 1); - - WRB(devAddr, IQM_CF_TAP_RE0__A, sizeof(vsb_taps_re), + cmd_scu.parameter_len = 0; + cmd_scu.result_len = 1; + cmd_scu.parameter = NULL; + cmd_scu.result = &cmd_result; + CHK_ERROR(scu_command(dev_addr, &cmd_scu)); + + WR16(dev_addr, IQM_AF_DCF_BYPASS__A, 1); + WR16(dev_addr, IQM_FS_ADJ_SEL__A, IQM_FS_ADJ_SEL_B_VSB); + WR16(dev_addr, IQM_RC_ADJ_SEL__A, IQM_RC_ADJ_SEL_B_VSB); + ext_attr->iqm_rc_rate_ofs = 0x00AD0D79; + WR32(dev_addr, IQM_RC_RATE_OFS_LO__A, ext_attr->iqm_rc_rate_ofs); + WR16(dev_addr, VSB_TOP_CFAGC_GAINSHIFT__A, 4); + WR16(dev_addr, VSB_TOP_CYGN1TRK__A, 1); + + WR16(dev_addr, IQM_RC_CROUT_ENA__A, 1); + WR16(dev_addr, IQM_RC_STRETCH__A, 28); + WR16(dev_addr, IQM_RT_ACTIVE__A, 0); + WR16(dev_addr, IQM_CF_SYMMETRIC__A, 0); + WR16(dev_addr, IQM_CF_MIDTAP__A, 3); + WR16(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_VSB__M); + WR16(dev_addr, IQM_CF_SCALE__A, 1393); + WR16(dev_addr, IQM_CF_SCALE_SH__A, 0); + WR16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 1); + + WRB(dev_addr, IQM_CF_TAP_RE0__A, sizeof(vsb_taps_re), ((u8 *) vsb_taps_re)); - WRB(devAddr, IQM_CF_TAP_IM0__A, sizeof(vsb_taps_re), + WRB(dev_addr, IQM_CF_TAP_IM0__A, sizeof(vsb_taps_re), ((u8 *) vsb_taps_re)); - WR16(devAddr, VSB_TOP_BNTHRESH__A, 330); /* set higher threshold */ - WR16(devAddr, VSB_TOP_CLPLASTNUM__A, 90); /* burst detection on */ - WR16(devAddr, VSB_TOP_SNRTH_RCA1__A, 0x0042); /* drop thresholds by 1 dB */ - WR16(devAddr, VSB_TOP_SNRTH_RCA2__A, 0x0053); /* drop thresholds by 2 dB */ - WR16(devAddr, VSB_TOP_EQCTRL__A, 0x1); /* cma on */ - WR16(devAddr, SCU_RAM_GPIO__A, 0); /* GPIO */ + WR16(dev_addr, VSB_TOP_BNTHRESH__A, 330); /* set higher threshold */ + WR16(dev_addr, VSB_TOP_CLPLASTNUM__A, 90); /* burst detection on */ + WR16(dev_addr, VSB_TOP_SNRTH_RCA1__A, 0x0042); /* drop thresholds by 1 dB */ + WR16(dev_addr, VSB_TOP_SNRTH_RCA2__A, 0x0053); /* drop thresholds by 2 dB */ + WR16(dev_addr, VSB_TOP_EQCTRL__A, 0x1); /* cma on */ + WR16(dev_addr, SCU_RAM_GPIO__A, 0); /* GPIO */ /* Initialize the FEC Subsystem */ - WR16(devAddr, FEC_TOP_ANNEX__A, FEC_TOP_ANNEX_D); + WR16(dev_addr, FEC_TOP_ANNEX__A, FEC_TOP_ANNEX_D); { - u16 fecOcSncMode = 0; - RR16(devAddr, FEC_OC_SNC_MODE__A, &fecOcSncMode); + u16 fec_oc_snc_mode = 0; + RR16(dev_addr, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode); /* output data even when not locked */ - WR16(devAddr, FEC_OC_SNC_MODE__A, - fecOcSncMode | FEC_OC_SNC_MODE_UNLOCK_ENABLE__M); + WR16(dev_addr, FEC_OC_SNC_MODE__A, + fec_oc_snc_mode | FEC_OC_SNC_MODE_UNLOCK_ENABLE__M); } /* set clip */ - WR16(devAddr, IQM_AF_CLP_LEN__A, 0); - WR16(devAddr, IQM_AF_CLP_TH__A, 470); - WR16(devAddr, IQM_AF_SNS_LEN__A, 0); - WR16(devAddr, VSB_TOP_SNRTH_PT__A, 0xD4); + WR16(dev_addr, IQM_AF_CLP_LEN__A, 0); + WR16(dev_addr, IQM_AF_CLP_TH__A, 470); + WR16(dev_addr, IQM_AF_SNS_LEN__A, 0); + WR16(dev_addr, VSB_TOP_SNRTH_PT__A, 0xD4); /* no transparent, no A&C framing; parity is set in mpegoutput */ { - u16 fecOcRegMode = 0; - RR16(devAddr, FEC_OC_MODE__A, &fecOcRegMode); - WR16(devAddr, FEC_OC_MODE__A, fecOcRegMode & + u16 fec_oc_reg_mode = 0; + RR16(dev_addr, FEC_OC_MODE__A, &fec_oc_reg_mode); + WR16(dev_addr, FEC_OC_MODE__A, fec_oc_reg_mode & (~(FEC_OC_MODE_TRANSPARENT__M | FEC_OC_MODE_CLEAR__M | FEC_OC_MODE_RETAIN_FRAMING__M) )); } - WR16(devAddr, FEC_DI_TIMEOUT_LO__A, 0); /* timeout counter for restarting */ - WR16(devAddr, FEC_DI_TIMEOUT_HI__A, 3); - WR16(devAddr, FEC_RS_MODE__A, 0); /* bypass disabled */ + WR16(dev_addr, FEC_DI_TIMEOUT_LO__A, 0); /* timeout counter for restarting */ + WR16(dev_addr, FEC_DI_TIMEOUT_HI__A, 3); + WR16(dev_addr, FEC_RS_MODE__A, 0); /* bypass disabled */ /* initialize RS packet error measurement parameters */ - WR16(devAddr, FEC_RS_MEASUREMENT_PERIOD__A, FEC_RS_MEASUREMENT_PERIOD); - WR16(devAddr, FEC_RS_MEASUREMENT_PRESCALE__A, + WR16(dev_addr, FEC_RS_MEASUREMENT_PERIOD__A, FEC_RS_MEASUREMENT_PERIOD); + WR16(dev_addr, FEC_RS_MEASUREMENT_PRESCALE__A, FEC_RS_MEASUREMENT_PRESCALE); /* init measurement period of MER/SER */ - WR16(devAddr, VSB_TOP_MEASUREMENT_PERIOD__A, + WR16(dev_addr, VSB_TOP_MEASUREMENT_PERIOD__A, VSB_TOP_MEASUREMENT_PERIOD); - WR32(devAddr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0); - WR16(devAddr, SCU_RAM_FEC_MEAS_COUNT__A, 0); - WR16(devAddr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0); + WR32(dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0); + WR16(dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, 0); + WR16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0); - WR16(devAddr, VSB_TOP_CKGN1TRK__A, 128); + WR16(dev_addr, VSB_TOP_CKGN1TRK__A, 128); /* B-Input to ADC, PGA+filter in standby */ - if (extAttr->hasLNA == false) { - WR16(devAddr, IQM_AF_AMUX__A, 0x02); + if (ext_attr->has_lna == false) { + WR16(dev_addr, IQM_AF_AMUX__A, 0x02); }; /* turn on IQMAF. It has to be in front of setAgc**() */ - CHK_ERROR(SetIqmAf(demod, true)); - CHK_ERROR(ADCSynchronization(demod)); + CHK_ERROR(set_iqm_af(demod, true)); + CHK_ERROR(adc_synchronization(demod)); - CHK_ERROR(InitAGC(demod)); - CHK_ERROR(SetAgcIf(demod, &(extAttr->vsbIfAgcCfg), false)); - CHK_ERROR(SetAgcRf(demod, &(extAttr->vsbRfAgcCfg), false)); + CHK_ERROR(init_agc(demod)); + CHK_ERROR(set_agc_if(demod, &(ext_attr->vsb_if_agc_cfg), false)); + CHK_ERROR(set_agc_rf(demod, &(ext_attr->vsb_rf_agc_cfg), false)); { - /* TODO fix this, store a DRXJCfgAfeGain_t structure in DRXJData_t instead + /* TODO fix this, store a drxj_cfg_afe_gain_t structure in drxj_data_t instead of only the gain */ - DRXJCfgAfeGain_t vsbPgaCfg = { DRX_STANDARD_8VSB, 0 }; + drxj_cfg_afe_gain_t vsb_pga_cfg = { DRX_STANDARD_8VSB, 0 }; - vsbPgaCfg.gain = extAttr->vsbPgaCfg; - CHK_ERROR(CtrlSetCfgAfeGain(demod, &vsbPgaCfg)); + vsb_pga_cfg.gain = ext_attr->vsb_pga_cfg; + CHK_ERROR(ctrl_set_cfg_afe_gain(demod, &vsb_pga_cfg)); } - CHK_ERROR(CtrlSetCfgPreSaw(demod, &(extAttr->vsbPreSawCfg))); + CHK_ERROR(ctrl_set_cfg_pre_saw(demod, &(ext_attr->vsb_pre_saw_cfg))); /* Mpeg output has to be in front of FEC active */ - CHK_ERROR(SetMPEGTEIHandling(demod)); - CHK_ERROR(BitReverseMPEGOutput(demod)); - CHK_ERROR(SetMPEGStartWidth(demod)); + CHK_ERROR(set_mpegtei_handling(demod)); + CHK_ERROR(bit_reverse_mpeg_output(demod)); + CHK_ERROR(set_mpeg_start_width(demod)); { - /* TODO: move to setStandard after hardware reset value problem is solved */ + /* TODO: move to set_standard after hardware reset value problem is solved */ /* Configure initial MPEG output */ - DRXCfgMPEGOutput_t cfgMPEGOutput; - cfgMPEGOutput.enableMPEGOutput = true; - cfgMPEGOutput.insertRSByte = commonAttr->mpegCfg.insertRSByte; - cfgMPEGOutput.enableParallel = - commonAttr->mpegCfg.enableParallel; - cfgMPEGOutput.invertDATA = commonAttr->mpegCfg.invertDATA; - cfgMPEGOutput.invertERR = commonAttr->mpegCfg.invertERR; - cfgMPEGOutput.invertSTR = commonAttr->mpegCfg.invertSTR; - cfgMPEGOutput.invertVAL = commonAttr->mpegCfg.invertVAL; - cfgMPEGOutput.invertCLK = commonAttr->mpegCfg.invertCLK; - cfgMPEGOutput.staticCLK = commonAttr->mpegCfg.staticCLK; - cfgMPEGOutput.bitrate = commonAttr->mpegCfg.bitrate; - CHK_ERROR(CtrlSetCfgMPEGOutput(demod, &cfgMPEGOutput)); + drx_cfg_mpeg_output_t cfg_mpeg_output; + cfg_mpeg_output.enable_mpeg_output = true; + cfg_mpeg_output.insert_rs_byte = common_attr->mpeg_cfg.insert_rs_byte; + cfg_mpeg_output.enable_parallel = + common_attr->mpeg_cfg.enable_parallel; + cfg_mpeg_output.invert_data = common_attr->mpeg_cfg.invert_data; + cfg_mpeg_output.invert_err = common_attr->mpeg_cfg.invert_err; + cfg_mpeg_output.invert_str = common_attr->mpeg_cfg.invert_str; + cfg_mpeg_output.invert_val = common_attr->mpeg_cfg.invert_val; + cfg_mpeg_output.invert_clk = common_attr->mpeg_cfg.invert_clk; + cfg_mpeg_output.static_clk = common_attr->mpeg_cfg.static_clk; + cfg_mpeg_output.bitrate = common_attr->mpeg_cfg.bitrate; + CHK_ERROR(ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output)); } /* TBD: what parameters should be set */ - cmdParam = 0x00; /* Default mode AGC on, etc */ - cmdSCU.command = SCU_RAM_COMMAND_STANDARD_VSB + cmd_param = 0x00; /* Default mode AGC on, etc */ + cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM; - cmdSCU.parameterLen = 1; - cmdSCU.resultLen = 1; - cmdSCU.parameter = &cmdParam; - cmdSCU.result = &cmdResult; - CHK_ERROR(SCUCommand(devAddr, &cmdSCU)); - - WR16(devAddr, VSB_TOP_BEAGC_GAINSHIFT__A, 0x0004); - WR16(devAddr, VSB_TOP_SNRTH_PT__A, 0x00D2); - WR16(devAddr, VSB_TOP_SYSSMTRNCTRL__A, VSB_TOP_SYSSMTRNCTRL__PRE + cmd_scu.parameter_len = 1; + cmd_scu.result_len = 1; + cmd_scu.parameter = &cmd_param; + cmd_scu.result = &cmd_result; + CHK_ERROR(scu_command(dev_addr, &cmd_scu)); + + WR16(dev_addr, VSB_TOP_BEAGC_GAINSHIFT__A, 0x0004); + WR16(dev_addr, VSB_TOP_SNRTH_PT__A, 0x00D2); + WR16(dev_addr, VSB_TOP_SYSSMTRNCTRL__A, VSB_TOP_SYSSMTRNCTRL__PRE | VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__M); - WR16(devAddr, VSB_TOP_BEDETCTRL__A, 0x142); - WR16(devAddr, VSB_TOP_LBAGCREFLVL__A, 640); - WR16(devAddr, VSB_TOP_CYGN1ACQ__A, 4); - WR16(devAddr, VSB_TOP_CYGN1TRK__A, 2); - WR16(devAddr, VSB_TOP_CYGN2TRK__A, 3); + WR16(dev_addr, VSB_TOP_BEDETCTRL__A, 0x142); + WR16(dev_addr, VSB_TOP_LBAGCREFLVL__A, 640); + WR16(dev_addr, VSB_TOP_CYGN1ACQ__A, 4); + WR16(dev_addr, VSB_TOP_CYGN1TRK__A, 2); + WR16(dev_addr, VSB_TOP_CYGN2TRK__A, 3); /* start demodulator */ - cmdSCU.command = SCU_RAM_COMMAND_STANDARD_VSB + cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB | SCU_RAM_COMMAND_CMD_DEMOD_START; - cmdSCU.parameterLen = 0; - cmdSCU.resultLen = 1; - cmdSCU.parameter = NULL; - cmdSCU.result = &cmdResult; - CHK_ERROR(SCUCommand(devAddr, &cmdSCU)); + cmd_scu.parameter_len = 0; + cmd_scu.result_len = 1; + cmd_scu.parameter = NULL; + cmd_scu.result = &cmd_result; + CHK_ERROR(scu_command(dev_addr, &cmd_scu)); - WR16(devAddr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE); - WR16(devAddr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_ACTIVE); - WR16(devAddr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE); + WR16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE); + WR16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_ACTIVE); + WR16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE); return (DRX_STS_OK); rw_error: @@ -6101,29 +6101,29 @@ rw_error: } /** -* \fn static short GetVSBPostRSPckErr(struct i2c_device_addr *devAddr, u16 *PckErrs) +* \fn static short get_vsb_post_rs_pck_err(struct i2c_device_addr *dev_addr, u16 *PckErrs) * \brief Get the values of packet error in 8VSB mode * \return Error code */ -static int GetVSBPostRSPckErr(struct i2c_device_addr *devAddr, u16 *pckErrs) +static int get_vsb_post_rs_pck_err(struct i2c_device_addr *dev_addr, u16 *pck_errs) { u16 data = 0; u16 period = 0; u16 prescale = 0; - u16 packetErrorsMant = 0; - u16 packetErrorsExp = 0; + u16 packet_errorsMant = 0; + u16 packet_errorsExp = 0; - RR16(devAddr, FEC_RS_NR_FAILURES__A, &data); - packetErrorsMant = data & FEC_RS_NR_FAILURES_FIXED_MANT__M; - packetErrorsExp = (data & FEC_RS_NR_FAILURES_EXP__M) + RR16(dev_addr, FEC_RS_NR_FAILURES__A, &data); + packet_errorsMant = data & FEC_RS_NR_FAILURES_FIXED_MANT__M; + packet_errorsExp = (data & FEC_RS_NR_FAILURES_EXP__M) >> FEC_RS_NR_FAILURES_EXP__B; period = FEC_RS_MEASUREMENT_PERIOD; prescale = FEC_RS_MEASUREMENT_PRESCALE; /* packet error rate = (error packet number) per second */ /* 77.3 us is time for per packet */ CHK_ZERO(period * prescale); - *pckErrs = - (u16) FracTimes1e6(packetErrorsMant * (1 << packetErrorsExp), + *pck_errs = + (u16) frac_times1e6(packet_errorsMant * (1 << packet_errorsExp), (period * prescale * 77)); return (DRX_STS_OK); @@ -6132,36 +6132,36 @@ rw_error: } /** -* \fn static short GetVSBBer(struct i2c_device_addr *devAddr, u32 *ber) +* \fn static short GetVSBBer(struct i2c_device_addr *dev_addr, u32 *ber) * \brief Get the values of ber in VSB mode * \return Error code */ -static int GetVSBpostViterbiBer(struct i2c_device_addr *devAddr, u32 *ber) +static int get_vs_bpost_viterbi_ber(struct i2c_device_addr *dev_addr, u32 *ber) { u16 data = 0; u16 period = 0; u16 prescale = 0; - u16 bitErrorsMant = 0; - u16 bitErrorsExp = 0; + u16 bit_errors_mant = 0; + u16 bit_errors_exp = 0; - RR16(devAddr, FEC_RS_NR_BIT_ERRORS__A, &data); + RR16(dev_addr, FEC_RS_NR_BIT_ERRORS__A, &data); period = FEC_RS_MEASUREMENT_PERIOD; prescale = FEC_RS_MEASUREMENT_PRESCALE; - bitErrorsMant = data & FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M; - bitErrorsExp = (data & FEC_RS_NR_BIT_ERRORS_EXP__M) + bit_errors_mant = data & FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M; + bit_errors_exp = (data & FEC_RS_NR_BIT_ERRORS_EXP__M) >> FEC_RS_NR_BIT_ERRORS_EXP__B; - if (((bitErrorsMant << bitErrorsExp) >> 3) > 68700) + if (((bit_errors_mant << bit_errors_exp) >> 3) > 68700) *ber = 26570; else { CHK_ZERO(period * prescale); *ber = - FracTimes1e6(bitErrorsMant << - ((bitErrorsExp > - 2) ? (bitErrorsExp - 3) : bitErrorsExp), + frac_times1e6(bit_errors_mant << + ((bit_errors_exp > + 2) ? (bit_errors_exp - 3) : bit_errors_exp), period * prescale * 207 * - ((bitErrorsExp > 2) ? 1 : 8)); + ((bit_errors_exp > 2) ? 1 : 8)); } return (DRX_STS_OK); @@ -6170,17 +6170,17 @@ rw_error: } /** -* \fn static short GetVSBpreViterbiBer(struct i2c_device_addr *devAddr, u32 *ber) +* \fn static short get_vs_bpre_viterbi_ber(struct i2c_device_addr *dev_addr, u32 *ber) * \brief Get the values of ber in VSB mode * \return Error code */ -static int GetVSBpreViterbiBer(struct i2c_device_addr *devAddr, u32 *ber) +static int get_vs_bpre_viterbi_ber(struct i2c_device_addr *dev_addr, u32 *ber) { u16 data = 0; - RR16(devAddr, VSB_TOP_NR_SYM_ERRS__A, &data); + RR16(dev_addr, VSB_TOP_NR_SYM_ERRS__A, &data); *ber = - FracTimes1e6(data, + frac_times1e6(data, VSB_TOP_MEASUREMENT_PERIOD * SYMBOLS_PER_SEGMENT); return (DRX_STS_OK); @@ -6189,28 +6189,28 @@ rw_error: } /** -* \fn static short GetVSBSymbErr(struct i2c_device_addr *devAddr, u32 *ber) +* \fn static short get_vsb_symb_err(struct i2c_device_addr *dev_addr, u32 *ber) * \brief Get the values of ber in VSB mode * \return Error code */ -static int GetVSBSymbErr(struct i2c_device_addr *devAddr, u32 *ser) +static int get_vsb_symb_err(struct i2c_device_addr *dev_addr, u32 *ser) { u16 data = 0; u16 period = 0; u16 prescale = 0; - u16 symbErrorsMant = 0; - u16 symbErrorsExp = 0; + u16 symb_errors_mant = 0; + u16 symb_errors_exp = 0; - RR16(devAddr, FEC_RS_NR_SYMBOL_ERRORS__A, &data); + RR16(dev_addr, FEC_RS_NR_SYMBOL_ERRORS__A, &data); period = FEC_RS_MEASUREMENT_PERIOD; prescale = FEC_RS_MEASUREMENT_PRESCALE; - symbErrorsMant = data & FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__M; - symbErrorsExp = (data & FEC_RS_NR_SYMBOL_ERRORS_EXP__M) + symb_errors_mant = data & FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__M; + symb_errors_exp = (data & FEC_RS_NR_SYMBOL_ERRORS_EXP__M) >> FEC_RS_NR_SYMBOL_ERRORS_EXP__B; CHK_ZERO(period * prescale); - *ser = (u32) FracTimes1e6((symbErrorsMant << symbErrorsExp) * 1000, + *ser = (u32) frac_times1e6((symb_errors_mant << symb_errors_exp) * 1000, (period * prescale * 77318)); return (DRX_STS_OK); @@ -6219,17 +6219,17 @@ rw_error: } /** -* \fn static int GetVSBMER(struct i2c_device_addr *devAddr, u16 *mer) +* \fn static int get_vsbmer(struct i2c_device_addr *dev_addr, u16 *mer) * \brief Get the values of MER * \return Error code */ -static int GetVSBMER(struct i2c_device_addr *devAddr, u16 *mer) +static int get_vsbmer(struct i2c_device_addr *dev_addr, u16 *mer) { - u16 dataHi = 0; + u16 data_hi = 0; - RR16(devAddr, VSB_TOP_ERR_ENERGY_H__A, &dataHi); + RR16(dev_addr, VSB_TOP_ERR_ENERGY_H__A, &data_hi); *mer = - (u16) (Log10Times100(21504) - Log10Times100((dataHi << 6) / 52)); + (u16) (log1_times100(21504) - log1_times100((data_hi << 6) / 52)); return (DRX_STS_OK); rw_error: @@ -6238,55 +6238,55 @@ rw_error: /*============================================================================*/ /** -* \fn int CtrlGetVSBConstel() +* \fn int ctrl_get_vsb_constel() * \brief Retreive a VSB constellation point via I2C. * \param demod Pointer to demodulator instance. -* \param complexNr Pointer to the structure in which to store the +* \param complex_nr Pointer to the structure in which to store the constellation point. * \return int. */ static int -CtrlGetVSBConstel(pDRXDemodInstance_t demod, pDRXComplex_t complexNr) +ctrl_get_vsb_constel(pdrx_demod_instance_t demod, pdrx_complex_t complex_nr) { - struct i2c_device_addr *devAddr = NULL; + struct i2c_device_addr *dev_addr = NULL; /**< device address */ - u16 vsbTopCommMb = 0; /**< VSB SL MB configuration */ - u16 vsbTopCommMbInit = 0; /**< VSB SL MB intial configuration */ + u16 vsb_top_comm_mb = 0; /**< VSB SL MB configuration */ + u16 vsb_top_comm_mbInit = 0; /**< VSB SL MB intial configuration */ u16 re = 0; /**< constellation Re part */ u32 data = 0; /* read device info */ - devAddr = demod->myI2CDevAddr; + dev_addr = demod->my_i2c_dev_addr; /* TODO: */ /* Monitor bus grabbing is an open external interface issue */ /* Needs to be checked when external interface PG is updated */ /* Configure MB (Monitor bus) */ - RR16(devAddr, VSB_TOP_COMM_MB__A, &vsbTopCommMbInit); + RR16(dev_addr, VSB_TOP_COMM_MB__A, &vsb_top_comm_mbInit); /* set observe flag & MB mux */ - vsbTopCommMb = (vsbTopCommMbInit | + vsb_top_comm_mb = (vsb_top_comm_mbInit | VSB_TOP_COMM_MB_OBS_OBS_ON | VSB_TOP_COMM_MB_MUX_OBS_VSB_TCMEQ_2); - WR16(devAddr, VSB_TOP_COMM_MB__A, vsbTopCommMb); + WR16(dev_addr, VSB_TOP_COMM_MB__A, vsb_top_comm_mb); /* Enable MB grabber in the FEC OC */ - WR16(devAddr, FEC_OC_OCR_MODE__A, FEC_OC_OCR_MODE_GRAB_ENABLE__M); + WR16(dev_addr, FEC_OC_OCR_MODE__A, FEC_OC_OCR_MODE_GRAB_ENABLE__M); /* Disable MB grabber in the FEC OC */ - WR16(devAddr, FEC_OC_OCR_MODE__A, 0x0); + WR16(dev_addr, FEC_OC_OCR_MODE__A, 0x0); /* read data */ - RR32(devAddr, FEC_OC_OCR_GRAB_RD1__A, &data); + RR32(dev_addr, FEC_OC_OCR_GRAB_RD1__A, &data); re = (u16) (((data >> 10) & 0x300) | ((data >> 2) & 0xff)); if (re & 0x0200) { re |= 0xfc00; } - complexNr->re = re; - complexNr->im = 0; + complex_nr->re = re; + complex_nr->im = 0; /* Restore MB (Monitor bus) */ - WR16(devAddr, VSB_TOP_COMM_MB__A, vsbTopCommMbInit); + WR16(dev_addr, VSB_TOP_COMM_MB__A, vsb_top_comm_mbInit); return (DRX_STS_OK); rw_error: @@ -6304,57 +6304,57 @@ rw_error: /*============================================================================*/ /** -* \fn int PowerDownQAM () +* \fn int power_down_qam () * \brief Powr down QAM related blocks. * \param demod instance of demodulator. * \param channel pointer to channel data. * \return int. */ -static int PowerDownQAM(pDRXDemodInstance_t demod, bool primary) +static int power_down_qam(pdrx_demod_instance_t demod, bool primary) { - DRXJSCUCmd_t cmdSCU = { /* command */ 0, - /* parameterLen */ 0, - /* resultLen */ 0, + drxjscu_cmd_t cmd_scu = { /* command */ 0, + /* parameter_len */ 0, + /* result_len */ 0, /* *parameter */ NULL, /* *result */ NULL }; - u16 cmdResult = 0; - struct i2c_device_addr *devAddr = NULL; - pDRXJData_t extAttr = NULL; - DRXCfgMPEGOutput_t cfgMPEGOutput; + u16 cmd_result = 0; + struct i2c_device_addr *dev_addr = NULL; + pdrxj_data_t ext_attr = NULL; + drx_cfg_mpeg_output_t cfg_mpeg_output; - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* STOP demodulator resets IQM, QAM and FEC HW blocks */ /* stop all comm_exec */ - WR16(devAddr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP); - WR16(devAddr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP); + WR16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP); + WR16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP); - cmdSCU.command = SCU_RAM_COMMAND_STANDARD_QAM | + cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_STOP; - cmdSCU.parameterLen = 0; - cmdSCU.resultLen = 1; - cmdSCU.parameter = NULL; - cmdSCU.result = &cmdResult; - CHK_ERROR(SCUCommand(devAddr, &cmdSCU)); + cmd_scu.parameter_len = 0; + cmd_scu.result_len = 1; + cmd_scu.parameter = NULL; + cmd_scu.result = &cmd_result; + CHK_ERROR(scu_command(dev_addr, &cmd_scu)); if (primary == true) { - WR16(devAddr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP); - CHK_ERROR(SetIqmAf(demod, false)); + WR16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP); + CHK_ERROR(set_iqm_af(demod, false)); } else { - WR16(devAddr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP); - WR16(devAddr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP); - WR16(devAddr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP); - WR16(devAddr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP); - WR16(devAddr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP); + WR16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP); + WR16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP); + WR16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP); + WR16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP); + WR16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP); } - cfgMPEGOutput.enableMPEGOutput = false; - CHK_ERROR(CtrlSetCfgMPEGOutput(demod, &cfgMPEGOutput)); + cfg_mpeg_output.enable_mpeg_output = false; + CHK_ERROR(ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output)); return (DRX_STS_OK); rw_error: @@ -6364,7 +6364,7 @@ rw_error: /*============================================================================*/ /** -* \fn int SetQAMMeasurement () +* \fn int set_qam_measurement () * \brief Setup of the QAM Measuremnt intervals for signal quality * \param demod instance of demod. * \param constellation current constellation. @@ -6374,50 +6374,50 @@ rw_error: * Take into account that for certain settings the errorcounters can overflow. * The implementation does not check this. * -* TODO: overriding the extAttr->fecBitsDesired by constellation dependent -* constants to get a measurement period of approx. 1 sec. Remove fecBitsDesired +* TODO: overriding the ext_attr->fec_bits_desired by constellation dependent +* constants to get a measurement period of approx. 1 sec. Remove fec_bits_desired * field ? * */ #ifndef DRXJ_VSB_ONLY static int -SetQAMMeasurement(pDRXDemodInstance_t demod, - enum drx_modulation constellation, u32 symbolRate) -{ - struct i2c_device_addr *devAddr = NULL; /* device address for I2C writes */ - pDRXJData_t extAttr = NULL; /* Global data container for DRXJ specif data */ - u32 fecBitsDesired = 0; /* BER accounting period */ - u16 fecRsPlen = 0; /* defines RS BER measurement period */ - u16 fecRsPrescale = 0; /* ReedSolomon Measurement Prescale */ - u32 fecRsPeriod = 0; /* Value for corresponding I2C register */ - u32 fecRsBitCnt = 0; /* Actual precise amount of bits */ - u32 fecOcSncFailPeriod = 0; /* Value for corresponding I2C register */ - u32 qamVdPeriod = 0; /* Value for corresponding I2C register */ - u32 qamVdBitCnt = 0; /* Actual precise amount of bits */ - u16 fecVdPlen = 0; /* no of trellis symbols: VD SER measur period */ - u16 qamVdPrescale = 0; /* Viterbi Measurement Prescale */ - - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; - - fecBitsDesired = extAttr->fecBitsDesired; - fecRsPrescale = extAttr->fecRsPrescale; +set_qam_measurement(pdrx_demod_instance_t demod, + enum drx_modulation constellation, u32 symbol_rate) +{ + struct i2c_device_addr *dev_addr = NULL; /* device address for I2C writes */ + pdrxj_data_t ext_attr = NULL; /* Global data container for DRXJ specif data */ + u32 fec_bits_desired = 0; /* BER accounting period */ + u16 fec_rs_plen = 0; /* defines RS BER measurement period */ + u16 fec_rs_prescale = 0; /* ReedSolomon Measurement Prescale */ + u32 fec_rs_period = 0; /* Value for corresponding I2C register */ + u32 fec_rs_bit_cnt = 0; /* Actual precise amount of bits */ + u32 fec_oc_snc_fail_period = 0; /* Value for corresponding I2C register */ + u32 qam_vd_period = 0; /* Value for corresponding I2C register */ + u32 qam_vd_bit_cnt = 0; /* Actual precise amount of bits */ + u16 fec_vd_plen = 0; /* no of trellis symbols: VD SER measur period */ + u16 qam_vd_prescale = 0; /* Viterbi Measurement Prescale */ + + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; + + fec_bits_desired = ext_attr->fec_bits_desired; + fec_rs_prescale = ext_attr->fec_rs_prescale; switch (constellation) { case DRX_CONSTELLATION_QAM16: - fecBitsDesired = 4 * symbolRate; + fec_bits_desired = 4 * symbol_rate; break; case DRX_CONSTELLATION_QAM32: - fecBitsDesired = 5 * symbolRate; + fec_bits_desired = 5 * symbol_rate; break; case DRX_CONSTELLATION_QAM64: - fecBitsDesired = 6 * symbolRate; + fec_bits_desired = 6 * symbol_rate; break; case DRX_CONSTELLATION_QAM128: - fecBitsDesired = 7 * symbolRate; + fec_bits_desired = 7 * symbol_rate; break; case DRX_CONSTELLATION_QAM256: - fecBitsDesired = 8 * symbolRate; + fec_bits_desired = 8 * symbol_rate; break; default: return (DRX_STS_INVALID_ARG); @@ -6429,44 +6429,44 @@ SetQAMMeasurement(pDRXDemodInstance_t demod, /* result is within 32 bit arithmetic -> */ /* no need for mult or frac functions */ - /* TODO: use constant instead of calculation and remove the fecRsPlen in extAttr */ - switch (extAttr->standard) { + /* TODO: use constant instead of calculation and remove the fec_rs_plen in ext_attr */ + switch (ext_attr->standard) { case DRX_STANDARD_ITU_A: case DRX_STANDARD_ITU_C: - fecRsPlen = 204 * 8; + fec_rs_plen = 204 * 8; break; case DRX_STANDARD_ITU_B: - fecRsPlen = 128 * 7; + fec_rs_plen = 128 * 7; break; default: return (DRX_STS_INVALID_ARG); } - extAttr->fecRsPlen = fecRsPlen; /* for getSigQual */ - fecRsBitCnt = fecRsPrescale * fecRsPlen; /* temp storage */ - CHK_ZERO(fecRsBitCnt); - fecRsPeriod = fecBitsDesired / fecRsBitCnt + 1; /* ceil */ - if (extAttr->standard != DRX_STANDARD_ITU_B) - fecOcSncFailPeriod = fecRsPeriod; + ext_attr->fec_rs_plen = fec_rs_plen; /* for getSigQual */ + fec_rs_bit_cnt = fec_rs_prescale * fec_rs_plen; /* temp storage */ + CHK_ZERO(fec_rs_bit_cnt); + fec_rs_period = fec_bits_desired / fec_rs_bit_cnt + 1; /* ceil */ + if (ext_attr->standard != DRX_STANDARD_ITU_B) + fec_oc_snc_fail_period = fec_rs_period; /* limit to max 16 bit value (I2C register width) if needed */ - if (fecRsPeriod > 0xFFFF) - fecRsPeriod = 0xFFFF; + if (fec_rs_period > 0xFFFF) + fec_rs_period = 0xFFFF; /* write corresponding registers */ - switch (extAttr->standard) { + switch (ext_attr->standard) { case DRX_STANDARD_ITU_A: case DRX_STANDARD_ITU_C: break; case DRX_STANDARD_ITU_B: switch (constellation) { case DRX_CONSTELLATION_QAM64: - fecRsPeriod = 31581; - fecOcSncFailPeriod = 17932; + fec_rs_period = 31581; + fec_oc_snc_fail_period = 17932; break; case DRX_CONSTELLATION_QAM256: - fecRsPeriod = 45446; - fecOcSncFailPeriod = 25805; + fec_rs_period = 45446; + fec_oc_snc_fail_period = 25805; break; default: return (DRX_STS_INVALID_ARG); @@ -6476,16 +6476,16 @@ SetQAMMeasurement(pDRXDemodInstance_t demod, return (DRX_STS_INVALID_ARG); } - WR16(devAddr, FEC_OC_SNC_FAIL_PERIOD__A, (u16) fecOcSncFailPeriod); - WR16(devAddr, FEC_RS_MEASUREMENT_PERIOD__A, (u16) fecRsPeriod); - WR16(devAddr, FEC_RS_MEASUREMENT_PRESCALE__A, fecRsPrescale); - extAttr->fecRsPeriod = (u16) fecRsPeriod; - extAttr->fecRsPrescale = fecRsPrescale; - WR32(devAddr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0); - WR16(devAddr, SCU_RAM_FEC_MEAS_COUNT__A, 0); - WR16(devAddr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0); + WR16(dev_addr, FEC_OC_SNC_FAIL_PERIOD__A, (u16) fec_oc_snc_fail_period); + WR16(dev_addr, FEC_RS_MEASUREMENT_PERIOD__A, (u16) fec_rs_period); + WR16(dev_addr, FEC_RS_MEASUREMENT_PRESCALE__A, fec_rs_prescale); + ext_attr->fec_rs_period = (u16) fec_rs_period; + ext_attr->fec_rs_prescale = fec_rs_prescale; + WR32(dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0); + WR16(dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, 0); + WR16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0); - if (extAttr->standard == DRX_STANDARD_ITU_B) { + if (ext_attr->standard == DRX_STANDARD_ITU_B) { /* Parameters for Viterbi Decoder */ /* qamvd_period = (int)ceil(FEC_BITS_DESIRED/ */ /* (qamvd_prescale*plen*(qam_constellation+1))) */ @@ -6493,41 +6493,41 @@ SetQAMMeasurement(pDRXDemodInstance_t demod, /* result is within 32 bit arithmetic -> */ /* no need for mult or frac functions */ - /* a(8 bit) * b(8 bit) = 16 bit result => Mult32 not needed */ - fecVdPlen = extAttr->fecVdPlen; - qamVdPrescale = extAttr->qamVdPrescale; - qamVdBitCnt = qamVdPrescale * fecVdPlen; /* temp storage */ + /* a(8 bit) * b(8 bit) = 16 bit result => mult32 not needed */ + fec_vd_plen = ext_attr->fec_vd_plen; + qam_vd_prescale = ext_attr->qam_vd_prescale; + qam_vd_bit_cnt = qam_vd_prescale * fec_vd_plen; /* temp storage */ switch (constellation) { case DRX_CONSTELLATION_QAM64: - /* a(16 bit) * b(4 bit) = 20 bit result => Mult32 not needed */ - qamVdPeriod = - qamVdBitCnt * (QAM_TOP_CONSTELLATION_QAM64 + 1) + /* a(16 bit) * b(4 bit) = 20 bit result => mult32 not needed */ + qam_vd_period = + qam_vd_bit_cnt * (QAM_TOP_CONSTELLATION_QAM64 + 1) * (QAM_TOP_CONSTELLATION_QAM64 + 1); break; case DRX_CONSTELLATION_QAM256: - /* a(16 bit) * b(5 bit) = 21 bit result => Mult32 not needed */ - qamVdPeriod = - qamVdBitCnt * (QAM_TOP_CONSTELLATION_QAM256 + 1) + /* a(16 bit) * b(5 bit) = 21 bit result => mult32 not needed */ + qam_vd_period = + qam_vd_bit_cnt * (QAM_TOP_CONSTELLATION_QAM256 + 1) * (QAM_TOP_CONSTELLATION_QAM256 + 1); break; default: return (DRX_STS_INVALID_ARG); } - CHK_ZERO(qamVdPeriod); - qamVdPeriod = fecBitsDesired / qamVdPeriod; + CHK_ZERO(qam_vd_period); + qam_vd_period = fec_bits_desired / qam_vd_period; /* limit to max 16 bit value (I2C register width) if needed */ - if (qamVdPeriod > 0xFFFF) - qamVdPeriod = 0xFFFF; + if (qam_vd_period > 0xFFFF) + qam_vd_period = 0xFFFF; - /* a(16 bit) * b(16 bit) = 32 bit result => Mult32 not needed */ - qamVdBitCnt *= qamVdPeriod; + /* a(16 bit) * b(16 bit) = 32 bit result => mult32 not needed */ + qam_vd_bit_cnt *= qam_vd_period; - WR16(devAddr, QAM_VD_MEASUREMENT_PERIOD__A, - (u16) qamVdPeriod); - WR16(devAddr, QAM_VD_MEASUREMENT_PRESCALE__A, qamVdPrescale); - extAttr->qamVdPeriod = (u16) qamVdPeriod; - extAttr->qamVdPrescale = qamVdPrescale; + WR16(dev_addr, QAM_VD_MEASUREMENT_PERIOD__A, + (u16) qam_vd_period); + WR16(dev_addr, QAM_VD_MEASUREMENT_PRESCALE__A, qam_vd_prescale); + ext_attr->qam_vd_period = (u16) qam_vd_period; + ext_attr->qam_vd_prescale = qam_vd_prescale; } return (DRX_STS_OK); @@ -6538,15 +6538,15 @@ rw_error: /*============================================================================*/ /** -* \fn int SetQAM16 () +* \fn int set_qam16 () * \brief QAM16 specific setup * \param demod instance of demod. * \return int. */ -static int SetQAM16(pDRXDemodInstance_t demod) +static int set_qam16(pdrx_demod_instance_t demod) { - struct i2c_device_addr *devAddr = demod->myI2CDevAddr; - const u8 qamDqQualFun[] = { + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + const u8 qam_dq_qual_fun[] = { DRXJ_16TO8(2), /* fun0 */ DRXJ_16TO8(2), /* fun1 */ DRXJ_16TO8(2), /* fun2 */ @@ -6554,7 +6554,7 @@ static int SetQAM16(pDRXDemodInstance_t demod) DRXJ_16TO8(3), /* fun4 */ DRXJ_16TO8(3), /* fun5 */ }; - const u8 qamEqCmaRad[] = { + const u8 qam_eq_cma_rad[] = { DRXJ_16TO8(13517), /* RAD0 */ DRXJ_16TO8(13517), /* RAD1 */ DRXJ_16TO8(13517), /* RAD2 */ @@ -6563,52 +6563,52 @@ static int SetQAM16(pDRXDemodInstance_t demod) DRXJ_16TO8(13517), /* RAD5 */ }; - WRB(devAddr, QAM_DQ_QUAL_FUN0__A, sizeof(qamDqQualFun), - ((u8 *) qamDqQualFun)); - WRB(devAddr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qamEqCmaRad), - ((u8 *) qamEqCmaRad)); - - WR16(devAddr, SCU_RAM_QAM_FSM_RTH__A, 140); - WR16(devAddr, SCU_RAM_QAM_FSM_FTH__A, 50); - WR16(devAddr, SCU_RAM_QAM_FSM_PTH__A, 120); - WR16(devAddr, SCU_RAM_QAM_FSM_QTH__A, 230); - WR16(devAddr, SCU_RAM_QAM_FSM_CTH__A, 95); - WR16(devAddr, SCU_RAM_QAM_FSM_MTH__A, 105); - - WR16(devAddr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); - WR16(devAddr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56); - WR16(devAddr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3); - - WR16(devAddr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 16); - WR16(devAddr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 220); - WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 25); - WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 6); - WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) (-24)); - WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) (-65)); - WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) (-127)); - - WR16(devAddr, SCU_RAM_QAM_LC_CA_FINE__A, 15); - WR16(devAddr, SCU_RAM_QAM_LC_CA_COARSE__A, 40); - WR16(devAddr, SCU_RAM_QAM_LC_CP_FINE__A, 2); - WR16(devAddr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20); - WR16(devAddr, SCU_RAM_QAM_LC_CP_COARSE__A, 255); - WR16(devAddr, SCU_RAM_QAM_LC_CI_FINE__A, 2); - WR16(devAddr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10); - WR16(devAddr, SCU_RAM_QAM_LC_CI_COARSE__A, 50); - WR16(devAddr, SCU_RAM_QAM_LC_EP_FINE__A, 12); - WR16(devAddr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); - WR16(devAddr, SCU_RAM_QAM_LC_EP_COARSE__A, 24); - WR16(devAddr, SCU_RAM_QAM_LC_EI_FINE__A, 12); - WR16(devAddr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); - WR16(devAddr, SCU_RAM_QAM_LC_EI_COARSE__A, 16); - WR16(devAddr, SCU_RAM_QAM_LC_CF_FINE__A, 16); - WR16(devAddr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32); - WR16(devAddr, SCU_RAM_QAM_LC_CF_COARSE__A, 240); - WR16(devAddr, SCU_RAM_QAM_LC_CF1_FINE__A, 5); - WR16(devAddr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15); - WR16(devAddr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32); - - WR16(devAddr, SCU_RAM_QAM_SL_SIG_POWER__A, 40960); + WRB(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), + ((u8 *) qam_dq_qual_fun)); + WRB(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), + ((u8 *) qam_eq_cma_rad)); + + WR16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 140); + WR16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 50); + WR16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 120); + WR16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 230); + WR16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 95); + WR16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 105); + + WR16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); + WR16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56); + WR16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3); + + WR16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 16); + WR16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 220); + WR16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 25); + WR16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 6); + WR16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) (-24)); + WR16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) (-65)); + WR16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) (-127)); + + WR16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15); + WR16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40); + WR16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2); + WR16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20); + WR16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255); + WR16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2); + WR16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10); + WR16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 50); + WR16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12); + WR16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); + WR16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24); + WR16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12); + WR16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); + WR16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16); + WR16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16); + WR16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32); + WR16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 240); + WR16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5); + WR16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15); + WR16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32); + + WR16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 40960); return (DRX_STS_OK); rw_error: @@ -6618,15 +6618,15 @@ rw_error: /*============================================================================*/ /** -* \fn int SetQAM32 () +* \fn int set_qam32 () * \brief QAM32 specific setup * \param demod instance of demod. * \return int. */ -static int SetQAM32(pDRXDemodInstance_t demod) +static int set_qam32(pdrx_demod_instance_t demod) { - struct i2c_device_addr *devAddr = demod->myI2CDevAddr; - const u8 qamDqQualFun[] = { + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + const u8 qam_dq_qual_fun[] = { DRXJ_16TO8(3), /* fun0 */ DRXJ_16TO8(3), /* fun1 */ DRXJ_16TO8(3), /* fun2 */ @@ -6634,7 +6634,7 @@ static int SetQAM32(pDRXDemodInstance_t demod) DRXJ_16TO8(4), /* fun4 */ DRXJ_16TO8(4), /* fun5 */ }; - const u8 qamEqCmaRad[] = { + const u8 qam_eq_cma_rad[] = { DRXJ_16TO8(6707), /* RAD0 */ DRXJ_16TO8(6707), /* RAD1 */ DRXJ_16TO8(6707), /* RAD2 */ @@ -6643,52 +6643,52 @@ static int SetQAM32(pDRXDemodInstance_t demod) DRXJ_16TO8(6707), /* RAD5 */ }; - WRB(devAddr, QAM_DQ_QUAL_FUN0__A, sizeof(qamDqQualFun), - ((u8 *) qamDqQualFun)); - WRB(devAddr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qamEqCmaRad), - ((u8 *) qamEqCmaRad)); - - WR16(devAddr, SCU_RAM_QAM_FSM_RTH__A, 90); - WR16(devAddr, SCU_RAM_QAM_FSM_FTH__A, 50); - WR16(devAddr, SCU_RAM_QAM_FSM_PTH__A, 100); - WR16(devAddr, SCU_RAM_QAM_FSM_QTH__A, 170); - WR16(devAddr, SCU_RAM_QAM_FSM_CTH__A, 80); - WR16(devAddr, SCU_RAM_QAM_FSM_MTH__A, 100); - - WR16(devAddr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); - WR16(devAddr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56); - WR16(devAddr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3); - - WR16(devAddr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12); - WR16(devAddr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 140); - WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) (-8)); - WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) (-16)); - WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) (-26)); - WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) (-56)); - WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) (-86)); - - WR16(devAddr, SCU_RAM_QAM_LC_CA_FINE__A, 15); - WR16(devAddr, SCU_RAM_QAM_LC_CA_COARSE__A, 40); - WR16(devAddr, SCU_RAM_QAM_LC_CP_FINE__A, 2); - WR16(devAddr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20); - WR16(devAddr, SCU_RAM_QAM_LC_CP_COARSE__A, 255); - WR16(devAddr, SCU_RAM_QAM_LC_CI_FINE__A, 2); - WR16(devAddr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10); - WR16(devAddr, SCU_RAM_QAM_LC_CI_COARSE__A, 50); - WR16(devAddr, SCU_RAM_QAM_LC_EP_FINE__A, 12); - WR16(devAddr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); - WR16(devAddr, SCU_RAM_QAM_LC_EP_COARSE__A, 24); - WR16(devAddr, SCU_RAM_QAM_LC_EI_FINE__A, 12); - WR16(devAddr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); - WR16(devAddr, SCU_RAM_QAM_LC_EI_COARSE__A, 16); - WR16(devAddr, SCU_RAM_QAM_LC_CF_FINE__A, 16); - WR16(devAddr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32); - WR16(devAddr, SCU_RAM_QAM_LC_CF_COARSE__A, 176); - WR16(devAddr, SCU_RAM_QAM_LC_CF1_FINE__A, 5); - WR16(devAddr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15); - WR16(devAddr, SCU_RAM_QAM_LC_CF1_COARSE__A, 8); - - WR16(devAddr, SCU_RAM_QAM_SL_SIG_POWER__A, 20480); + WRB(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), + ((u8 *) qam_dq_qual_fun)); + WRB(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), + ((u8 *) qam_eq_cma_rad)); + + WR16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 90); + WR16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 50); + WR16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100); + WR16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 170); + WR16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80); + WR16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 100); + + WR16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); + WR16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56); + WR16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3); + + WR16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12); + WR16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 140); + WR16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) (-8)); + WR16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) (-16)); + WR16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) (-26)); + WR16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) (-56)); + WR16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) (-86)); + + WR16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15); + WR16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40); + WR16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2); + WR16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20); + WR16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255); + WR16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2); + WR16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10); + WR16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 50); + WR16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12); + WR16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); + WR16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24); + WR16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12); + WR16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); + WR16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16); + WR16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16); + WR16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32); + WR16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 176); + WR16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5); + WR16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15); + WR16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 8); + + WR16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 20480); return (DRX_STS_OK); rw_error: @@ -6698,15 +6698,15 @@ rw_error: /*============================================================================*/ /** -* \fn int SetQAM64 () +* \fn int set_qam64 () * \brief QAM64 specific setup * \param demod instance of demod. * \return int. */ -static int SetQAM64(pDRXDemodInstance_t demod) +static int set_qam64(pdrx_demod_instance_t demod) { - struct i2c_device_addr *devAddr = demod->myI2CDevAddr; - const u8 qamDqQualFun[] = { /* this is hw reset value. no necessary to re-write */ + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + const u8 qam_dq_qual_fun[] = { /* this is hw reset value. no necessary to re-write */ DRXJ_16TO8(4), /* fun0 */ DRXJ_16TO8(4), /* fun1 */ DRXJ_16TO8(4), /* fun2 */ @@ -6714,7 +6714,7 @@ static int SetQAM64(pDRXDemodInstance_t demod) DRXJ_16TO8(6), /* fun4 */ DRXJ_16TO8(6), /* fun5 */ }; - const u8 qamEqCmaRad[] = { + const u8 qam_eq_cma_rad[] = { DRXJ_16TO8(13336), /* RAD0 */ DRXJ_16TO8(12618), /* RAD1 */ DRXJ_16TO8(11988), /* RAD2 */ @@ -6723,52 +6723,52 @@ static int SetQAM64(pDRXDemodInstance_t demod) DRXJ_16TO8(15609), /* RAD5 */ }; - WRB(devAddr, QAM_DQ_QUAL_FUN0__A, sizeof(qamDqQualFun), - ((u8 *) qamDqQualFun)); - WRB(devAddr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qamEqCmaRad), - ((u8 *) qamEqCmaRad)); - - WR16(devAddr, SCU_RAM_QAM_FSM_RTH__A, 105); - WR16(devAddr, SCU_RAM_QAM_FSM_FTH__A, 60); - WR16(devAddr, SCU_RAM_QAM_FSM_PTH__A, 100); - WR16(devAddr, SCU_RAM_QAM_FSM_QTH__A, 195); - WR16(devAddr, SCU_RAM_QAM_FSM_CTH__A, 80); - WR16(devAddr, SCU_RAM_QAM_FSM_MTH__A, 84); - - WR16(devAddr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); - WR16(devAddr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32); - WR16(devAddr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3); - - WR16(devAddr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12); - WR16(devAddr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 141); - WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 7); - WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 0); - WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) (-15)); - WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) (-45)); - WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) (-80)); - - WR16(devAddr, SCU_RAM_QAM_LC_CA_FINE__A, 15); - WR16(devAddr, SCU_RAM_QAM_LC_CA_COARSE__A, 40); - WR16(devAddr, SCU_RAM_QAM_LC_CP_FINE__A, 2); - WR16(devAddr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30); - WR16(devAddr, SCU_RAM_QAM_LC_CP_COARSE__A, 255); - WR16(devAddr, SCU_RAM_QAM_LC_CI_FINE__A, 2); - WR16(devAddr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 15); - WR16(devAddr, SCU_RAM_QAM_LC_CI_COARSE__A, 80); - WR16(devAddr, SCU_RAM_QAM_LC_EP_FINE__A, 12); - WR16(devAddr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); - WR16(devAddr, SCU_RAM_QAM_LC_EP_COARSE__A, 24); - WR16(devAddr, SCU_RAM_QAM_LC_EI_FINE__A, 12); - WR16(devAddr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); - WR16(devAddr, SCU_RAM_QAM_LC_EI_COARSE__A, 16); - WR16(devAddr, SCU_RAM_QAM_LC_CF_FINE__A, 16); - WR16(devAddr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48); - WR16(devAddr, SCU_RAM_QAM_LC_CF_COARSE__A, 160); - WR16(devAddr, SCU_RAM_QAM_LC_CF1_FINE__A, 5); - WR16(devAddr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15); - WR16(devAddr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32); - - WR16(devAddr, SCU_RAM_QAM_SL_SIG_POWER__A, 43008); + WRB(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), + ((u8 *) qam_dq_qual_fun)); + WRB(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), + ((u8 *) qam_eq_cma_rad)); + + WR16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 105); + WR16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60); + WR16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100); + WR16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 195); + WR16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80); + WR16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 84); + + WR16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); + WR16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32); + WR16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3); + + WR16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12); + WR16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 141); + WR16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 7); + WR16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 0); + WR16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) (-15)); + WR16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) (-45)); + WR16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) (-80)); + + WR16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15); + WR16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40); + WR16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2); + WR16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30); + WR16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255); + WR16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2); + WR16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 15); + WR16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80); + WR16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12); + WR16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); + WR16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24); + WR16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12); + WR16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); + WR16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16); + WR16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16); + WR16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48); + WR16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 160); + WR16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5); + WR16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15); + WR16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32); + + WR16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 43008); return (DRX_STS_OK); rw_error: @@ -6778,15 +6778,15 @@ rw_error: /*============================================================================*/ /** -* \fn int SetQAM128 () +* \fn int set_qam128 () * \brief QAM128 specific setup * \param demod: instance of demod. * \return int. */ -static int SetQAM128(pDRXDemodInstance_t demod) +static int set_qam128(pdrx_demod_instance_t demod) { - struct i2c_device_addr *devAddr = demod->myI2CDevAddr; - const u8 qamDqQualFun[] = { + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + const u8 qam_dq_qual_fun[] = { DRXJ_16TO8(6), /* fun0 */ DRXJ_16TO8(6), /* fun1 */ DRXJ_16TO8(6), /* fun2 */ @@ -6794,7 +6794,7 @@ static int SetQAM128(pDRXDemodInstance_t demod) DRXJ_16TO8(9), /* fun4 */ DRXJ_16TO8(9), /* fun5 */ }; - const u8 qamEqCmaRad[] = { + const u8 qam_eq_cma_rad[] = { DRXJ_16TO8(6164), /* RAD0 */ DRXJ_16TO8(6598), /* RAD1 */ DRXJ_16TO8(6394), /* RAD2 */ @@ -6803,52 +6803,52 @@ static int SetQAM128(pDRXDemodInstance_t demod) DRXJ_16TO8(7238), /* RAD5 */ }; - WRB(devAddr, QAM_DQ_QUAL_FUN0__A, sizeof(qamDqQualFun), - ((u8 *) qamDqQualFun)); - WRB(devAddr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qamEqCmaRad), - ((u8 *) qamEqCmaRad)); - - WR16(devAddr, SCU_RAM_QAM_FSM_RTH__A, 50); - WR16(devAddr, SCU_RAM_QAM_FSM_FTH__A, 60); - WR16(devAddr, SCU_RAM_QAM_FSM_PTH__A, 100); - WR16(devAddr, SCU_RAM_QAM_FSM_QTH__A, 140); - WR16(devAddr, SCU_RAM_QAM_FSM_CTH__A, 80); - WR16(devAddr, SCU_RAM_QAM_FSM_MTH__A, 100); - - WR16(devAddr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); - WR16(devAddr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32); - WR16(devAddr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3); - - WR16(devAddr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8); - WR16(devAddr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 65); - WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 5); - WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 3); - WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) (-1)); - WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 12); - WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) (-23)); - - WR16(devAddr, SCU_RAM_QAM_LC_CA_FINE__A, 15); - WR16(devAddr, SCU_RAM_QAM_LC_CA_COARSE__A, 40); - WR16(devAddr, SCU_RAM_QAM_LC_CP_FINE__A, 2); - WR16(devAddr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40); - WR16(devAddr, SCU_RAM_QAM_LC_CP_COARSE__A, 255); - WR16(devAddr, SCU_RAM_QAM_LC_CI_FINE__A, 2); - WR16(devAddr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20); - WR16(devAddr, SCU_RAM_QAM_LC_CI_COARSE__A, 80); - WR16(devAddr, SCU_RAM_QAM_LC_EP_FINE__A, 12); - WR16(devAddr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); - WR16(devAddr, SCU_RAM_QAM_LC_EP_COARSE__A, 24); - WR16(devAddr, SCU_RAM_QAM_LC_EI_FINE__A, 12); - WR16(devAddr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); - WR16(devAddr, SCU_RAM_QAM_LC_EI_COARSE__A, 16); - WR16(devAddr, SCU_RAM_QAM_LC_CF_FINE__A, 16); - WR16(devAddr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32); - WR16(devAddr, SCU_RAM_QAM_LC_CF_COARSE__A, 144); - WR16(devAddr, SCU_RAM_QAM_LC_CF1_FINE__A, 5); - WR16(devAddr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15); - WR16(devAddr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16); - - WR16(devAddr, SCU_RAM_QAM_SL_SIG_POWER__A, 20992); + WRB(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), + ((u8 *) qam_dq_qual_fun)); + WRB(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), + ((u8 *) qam_eq_cma_rad)); + + WR16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 50); + WR16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60); + WR16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100); + WR16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 140); + WR16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80); + WR16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 100); + + WR16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); + WR16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32); + WR16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3); + + WR16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8); + WR16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 65); + WR16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 5); + WR16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 3); + WR16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) (-1)); + WR16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 12); + WR16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) (-23)); + + WR16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15); + WR16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40); + WR16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2); + WR16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40); + WR16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255); + WR16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2); + WR16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20); + WR16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80); + WR16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12); + WR16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); + WR16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24); + WR16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12); + WR16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); + WR16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16); + WR16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16); + WR16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32); + WR16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 144); + WR16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5); + WR16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15); + WR16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16); + + WR16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 20992); return (DRX_STS_OK); rw_error: @@ -6858,15 +6858,15 @@ rw_error: /*============================================================================*/ /** -* \fn int SetQAM256 () +* \fn int set_qam256 () * \brief QAM256 specific setup * \param demod: instance of demod. * \return int. */ -static int SetQAM256(pDRXDemodInstance_t demod) +static int set_qam256(pdrx_demod_instance_t demod) { - struct i2c_device_addr *devAddr = demod->myI2CDevAddr; - const u8 qamDqQualFun[] = { + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + const u8 qam_dq_qual_fun[] = { DRXJ_16TO8(8), /* fun0 */ DRXJ_16TO8(8), /* fun1 */ DRXJ_16TO8(8), /* fun2 */ @@ -6874,7 +6874,7 @@ static int SetQAM256(pDRXDemodInstance_t demod) DRXJ_16TO8(12), /* fun4 */ DRXJ_16TO8(12), /* fun5 */ }; - const u8 qamEqCmaRad[] = { + const u8 qam_eq_cma_rad[] = { DRXJ_16TO8(12345), /* RAD0 */ DRXJ_16TO8(12345), /* RAD1 */ DRXJ_16TO8(13626), /* RAD2 */ @@ -6883,52 +6883,52 @@ static int SetQAM256(pDRXDemodInstance_t demod) DRXJ_16TO8(15356), /* RAD5 */ }; - WRB(devAddr, QAM_DQ_QUAL_FUN0__A, sizeof(qamDqQualFun), - ((u8 *) qamDqQualFun)); - WRB(devAddr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qamEqCmaRad), - ((u8 *) qamEqCmaRad)); - - WR16(devAddr, SCU_RAM_QAM_FSM_RTH__A, 50); - WR16(devAddr, SCU_RAM_QAM_FSM_FTH__A, 60); - WR16(devAddr, SCU_RAM_QAM_FSM_PTH__A, 100); - WR16(devAddr, SCU_RAM_QAM_FSM_QTH__A, 150); - WR16(devAddr, SCU_RAM_QAM_FSM_CTH__A, 80); - WR16(devAddr, SCU_RAM_QAM_FSM_MTH__A, 110); - - WR16(devAddr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); - WR16(devAddr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 16); - WR16(devAddr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3); - - WR16(devAddr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8); - WR16(devAddr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 74); - WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 18); - WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 13); - WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, 7); - WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 0); - WR16(devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) (-8)); - - WR16(devAddr, SCU_RAM_QAM_LC_CA_FINE__A, 15); - WR16(devAddr, SCU_RAM_QAM_LC_CA_COARSE__A, 40); - WR16(devAddr, SCU_RAM_QAM_LC_CP_FINE__A, 2); - WR16(devAddr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50); - WR16(devAddr, SCU_RAM_QAM_LC_CP_COARSE__A, 255); - WR16(devAddr, SCU_RAM_QAM_LC_CI_FINE__A, 2); - WR16(devAddr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 25); - WR16(devAddr, SCU_RAM_QAM_LC_CI_COARSE__A, 80); - WR16(devAddr, SCU_RAM_QAM_LC_EP_FINE__A, 12); - WR16(devAddr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); - WR16(devAddr, SCU_RAM_QAM_LC_EP_COARSE__A, 24); - WR16(devAddr, SCU_RAM_QAM_LC_EI_FINE__A, 12); - WR16(devAddr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); - WR16(devAddr, SCU_RAM_QAM_LC_EI_COARSE__A, 16); - WR16(devAddr, SCU_RAM_QAM_LC_CF_FINE__A, 16); - WR16(devAddr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48); - WR16(devAddr, SCU_RAM_QAM_LC_CF_COARSE__A, 80); - WR16(devAddr, SCU_RAM_QAM_LC_CF1_FINE__A, 5); - WR16(devAddr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15); - WR16(devAddr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16); - - WR16(devAddr, SCU_RAM_QAM_SL_SIG_POWER__A, 43520); + WRB(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), + ((u8 *) qam_dq_qual_fun)); + WRB(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), + ((u8 *) qam_eq_cma_rad)); + + WR16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 50); + WR16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60); + WR16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100); + WR16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 150); + WR16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80); + WR16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 110); + + WR16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); + WR16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 16); + WR16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3); + + WR16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8); + WR16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 74); + WR16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 18); + WR16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 13); + WR16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, 7); + WR16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 0); + WR16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) (-8)); + + WR16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15); + WR16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40); + WR16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2); + WR16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50); + WR16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255); + WR16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2); + WR16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 25); + WR16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80); + WR16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12); + WR16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); + WR16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24); + WR16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12); + WR16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); + WR16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16); + WR16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16); + WR16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48); + WR16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 80); + WR16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5); + WR16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15); + WR16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16); + + WR16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 43520); return (DRX_STS_OK); rw_error: @@ -6941,33 +6941,33 @@ rw_error: #define QAM_SET_OP_SPECTRUM 0X4 /** -* \fn int SetQAM () +* \fn int set_qam () * \brief Set QAM demod. * \param demod: instance of demod. * \param channel: pointer to channel data. * \return int. */ static int -SetQAM(pDRXDemodInstance_t demod, - pDRXChannel_t channel, s32 tunerFreqOffset, u32 op) -{ - struct i2c_device_addr *devAddr = NULL; - pDRXJData_t extAttr = NULL; - pDRXCommonAttr_t commonAttr = NULL; - u16 cmdResult = 0; - u32 adcFrequency = 0; - u32 iqmRcRate = 0; - u16 lcSymbolFreq = 0; - u16 iqmRcStretch = 0; - u16 setEnvParameters = 0; - u16 setParamParameters[2] = { 0 }; - DRXJSCUCmd_t cmdSCU = { /* command */ 0, - /* parameterLen */ 0, - /* resultLen */ 0, +set_qam(pdrx_demod_instance_t demod, + pdrx_channel_t channel, s32 tuner_freq_offset, u32 op) +{ + struct i2c_device_addr *dev_addr = NULL; + pdrxj_data_t ext_attr = NULL; + pdrx_common_attr_t common_attr = NULL; + u16 cmd_result = 0; + u32 adc_frequency = 0; + u32 iqm_rc_rate = 0; + u16 lc_symbol_freq = 0; + u16 iqm_rc_stretch = 0; + u16 set_env_parameters = 0; + u16 set_param_parameters[2] = { 0 }; + drxjscu_cmd_t cmd_scu = { /* command */ 0, + /* parameter_len */ 0, + /* result_len */ 0, /* parameter */ NULL, /* result */ NULL }; - const u8 qamA_taps[] = { + const u8 qam_a_taps[] = { DRXJ_16TO8(-1), /* re0 */ DRXJ_16TO8(1), /* re1 */ DRXJ_16TO8(1), /* re2 */ @@ -6997,7 +6997,7 @@ SetQAM(pDRXDemodInstance_t demod, DRXJ_16TO8(-40), /* re26 */ DRXJ_16TO8(619) /* re27 */ }; - const u8 qamB64_taps[] = { + const u8 qam_b64_taps[] = { DRXJ_16TO8(0), /* re0 */ DRXJ_16TO8(-2), /* re1 */ DRXJ_16TO8(1), /* re2 */ @@ -7027,7 +7027,7 @@ SetQAM(pDRXDemodInstance_t demod, DRXJ_16TO8(-46), /* re26 */ DRXJ_16TO8(614) /* re27 */ }; - const u8 qamB256_taps[] = { + const u8 qam_b256_taps[] = { DRXJ_16TO8(-2), /* re0 */ DRXJ_16TO8(4), /* re1 */ DRXJ_16TO8(1), /* re2 */ @@ -7057,7 +7057,7 @@ SetQAM(pDRXDemodInstance_t demod, DRXJ_16TO8(-32), /* re26 */ DRXJ_16TO8(628) /* re27 */ }; - const u8 qamC_taps[] = { + const u8 qam_c_taps[] = { DRXJ_16TO8(-3), /* re0 */ DRXJ_16TO8(3), /* re1 */ DRXJ_16TO8(2), /* re2 */ @@ -7088,60 +7088,60 @@ SetQAM(pDRXDemodInstance_t demod, DRXJ_16TO8(626) /* re27 */ }; - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; - commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; + common_attr = (pdrx_common_attr_t) demod->my_common_attr; if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) { - if (extAttr->standard == DRX_STANDARD_ITU_B) { + if (ext_attr->standard == DRX_STANDARD_ITU_B) { switch (channel->constellation) { case DRX_CONSTELLATION_QAM256: - iqmRcRate = 0x00AE3562; - lcSymbolFreq = + iqm_rc_rate = 0x00AE3562; + lc_symbol_freq = QAM_LC_SYMBOL_FREQ_FREQ_QAM_B_256; channel->symbolrate = 5360537; - iqmRcStretch = IQM_RC_STRETCH_QAM_B_256; + iqm_rc_stretch = IQM_RC_STRETCH_QAM_B_256; break; case DRX_CONSTELLATION_QAM64: - iqmRcRate = 0x00C05A0E; - lcSymbolFreq = 409; + iqm_rc_rate = 0x00C05A0E; + lc_symbol_freq = 409; channel->symbolrate = 5056941; - iqmRcStretch = IQM_RC_STRETCH_QAM_B_64; + iqm_rc_stretch = IQM_RC_STRETCH_QAM_B_64; break; default: return (DRX_STS_INVALID_ARG); } } else { - adcFrequency = (commonAttr->sysClockFreq * 1000) / 3; + adc_frequency = (common_attr->sys_clock_freq * 1000) / 3; CHK_ZERO(channel->symbolrate); - iqmRcRate = - (adcFrequency / channel->symbolrate) * (1 << 21) + - (Frac28 - ((adcFrequency % channel->symbolrate), + iqm_rc_rate = + (adc_frequency / channel->symbolrate) * (1 << 21) + + (frac28 + ((adc_frequency % channel->symbolrate), channel->symbolrate) >> 7) - (1 << 23); - lcSymbolFreq = - (u16) (Frac28 + lc_symbol_freq = + (u16) (frac28 (channel->symbolrate + - (adcFrequency >> 13), - adcFrequency) >> 16); - if (lcSymbolFreq > 511) - lcSymbolFreq = 511; - - iqmRcStretch = 21; - } - - if (extAttr->standard == DRX_STANDARD_ITU_A) { - setEnvParameters = QAM_TOP_ANNEX_A; /* annex */ - setParamParameters[0] = channel->constellation; /* constellation */ - setParamParameters[1] = DRX_INTERLEAVEMODE_I12_J17; /* interleave mode */ - } else if (extAttr->standard == DRX_STANDARD_ITU_B) { - setEnvParameters = QAM_TOP_ANNEX_B; /* annex */ - setParamParameters[0] = channel->constellation; /* constellation */ - setParamParameters[1] = channel->interleavemode; /* interleave mode */ - } else if (extAttr->standard == DRX_STANDARD_ITU_C) { - setEnvParameters = QAM_TOP_ANNEX_C; /* annex */ - setParamParameters[0] = channel->constellation; /* constellation */ - setParamParameters[1] = DRX_INTERLEAVEMODE_I12_J17; /* interleave mode */ + (adc_frequency >> 13), + adc_frequency) >> 16); + if (lc_symbol_freq > 511) + lc_symbol_freq = 511; + + iqm_rc_stretch = 21; + } + + if (ext_attr->standard == DRX_STANDARD_ITU_A) { + set_env_parameters = QAM_TOP_ANNEX_A; /* annex */ + set_param_parameters[0] = channel->constellation; /* constellation */ + set_param_parameters[1] = DRX_INTERLEAVEMODE_I12_J17; /* interleave mode */ + } else if (ext_attr->standard == DRX_STANDARD_ITU_B) { + set_env_parameters = QAM_TOP_ANNEX_B; /* annex */ + set_param_parameters[0] = channel->constellation; /* constellation */ + set_param_parameters[1] = channel->interleavemode; /* interleave mode */ + } else if (ext_attr->standard == DRX_STANDARD_ITU_C) { + set_env_parameters = QAM_TOP_ANNEX_C; /* annex */ + set_param_parameters[0] = channel->constellation; /* constellation */ + set_param_parameters[1] = DRX_INTERLEAVEMODE_I12_J17; /* interleave mode */ } else { return (DRX_STS_INVALID_ARG); } @@ -7154,21 +7154,21 @@ SetQAM(pDRXDemodInstance_t demod, resets SCU variables */ /* stop all comm_exec */ - WR16(devAddr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP); - WR16(devAddr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP); - WR16(devAddr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP); - WR16(devAddr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP); - WR16(devAddr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP); - WR16(devAddr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP); - WR16(devAddr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP); - - cmdSCU.command = SCU_RAM_COMMAND_STANDARD_QAM | + WR16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP); + WR16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP); + WR16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP); + WR16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP); + WR16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP); + WR16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP); + WR16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP); + + cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_RESET; - cmdSCU.parameterLen = 0; - cmdSCU.resultLen = 1; - cmdSCU.parameter = NULL; - cmdSCU.result = &cmdResult; - CHK_ERROR(SCUCommand(devAddr, &cmdSCU)); + cmd_scu.parameter_len = 0; + cmd_scu.result_len = 1; + cmd_scu.parameter = NULL; + cmd_scu.result = &cmd_result; + CHK_ERROR(scu_command(dev_addr, &cmd_scu)); } if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) { @@ -7177,25 +7177,25 @@ SetQAM(pDRXDemodInstance_t demod, -set env -set params (resets IQM,QAM,FEC HW; initializes some SCU variables ) */ - cmdSCU.command = SCU_RAM_COMMAND_STANDARD_QAM | + cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV; - cmdSCU.parameterLen = 1; - cmdSCU.resultLen = 1; - cmdSCU.parameter = &setEnvParameters; - cmdSCU.result = &cmdResult; - CHK_ERROR(SCUCommand(devAddr, &cmdSCU)); + cmd_scu.parameter_len = 1; + cmd_scu.result_len = 1; + cmd_scu.parameter = &set_env_parameters; + cmd_scu.result = &cmd_result; + CHK_ERROR(scu_command(dev_addr, &cmd_scu)); - cmdSCU.command = SCU_RAM_COMMAND_STANDARD_QAM | + cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM; - cmdSCU.parameterLen = 2; - cmdSCU.resultLen = 1; - cmdSCU.parameter = setParamParameters; - cmdSCU.result = &cmdResult; - CHK_ERROR(SCUCommand(devAddr, &cmdSCU)); + cmd_scu.parameter_len = 2; + cmd_scu.result_len = 1; + cmd_scu.parameter = set_param_parameters; + cmd_scu.result = &cmd_result; + CHK_ERROR(scu_command(dev_addr, &cmd_scu)); /* set symbol rate */ - WR32(devAddr, IQM_RC_RATE_OFS_LO__A, iqmRcRate); - extAttr->iqmRcRateOfs = iqmRcRate; - CHK_ERROR(SetQAMMeasurement + WR32(dev_addr, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate); + ext_attr->iqm_rc_rate_ofs = iqm_rc_rate; + CHK_ERROR(set_qam_measurement (demod, channel->constellation, channel->symbolrate)); } /* STEP 3: enable the system in a mode where the ADC provides valid signal @@ -7203,156 +7203,156 @@ SetQAM(pDRXDemodInstance_t demod, /* from qam_cmd.py script (qam_driver_b) */ /* TODO: remove re-writes of HW reset values */ if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_SPECTRUM)) { - CHK_ERROR(SetFrequency(demod, channel, tunerFreqOffset)); + CHK_ERROR(set_frequency(demod, channel, tuner_freq_offset)); } if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) { - WR16(devAddr, QAM_LC_SYMBOL_FREQ__A, lcSymbolFreq); - WR16(devAddr, IQM_RC_STRETCH__A, iqmRcStretch); + WR16(dev_addr, QAM_LC_SYMBOL_FREQ__A, lc_symbol_freq); + WR16(dev_addr, IQM_RC_STRETCH__A, iqm_rc_stretch); } if (op & QAM_SET_OP_ALL) { - if (extAttr->hasLNA == false) { - WR16(devAddr, IQM_AF_AMUX__A, 0x02); - } - WR16(devAddr, IQM_CF_SYMMETRIC__A, 0); - WR16(devAddr, IQM_CF_MIDTAP__A, 3); - WR16(devAddr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_QAM__M); - - WR16(devAddr, SCU_RAM_QAM_WR_RSV_0__A, 0x5f); /* scu temporary shut down agc */ - - WR16(devAddr, IQM_AF_SYNC_SEL__A, 3); - WR16(devAddr, IQM_AF_CLP_LEN__A, 0); - WR16(devAddr, IQM_AF_CLP_TH__A, 448); - WR16(devAddr, IQM_AF_SNS_LEN__A, 0); - WR16(devAddr, IQM_AF_PDREF__A, 4); - WR16(devAddr, IQM_AF_STDBY__A, 0x10); - WR16(devAddr, IQM_AF_PGA_GAIN__A, 11); - - WR16(devAddr, IQM_CF_POW_MEAS_LEN__A, 1); - WR16(devAddr, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE); /*! reset default val ! */ - - WR16(devAddr, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE); /*! reset default val ! */ - if (extAttr->standard == DRX_STANDARD_ITU_B) { - WR16(devAddr, QAM_SY_SYNC_LWM__A, QAM_SY_SYNC_LWM__PRE); /*! reset default val ! */ - WR16(devAddr, QAM_SY_SYNC_AWM__A, QAM_SY_SYNC_AWM__PRE); /*! reset default val ! */ - WR16(devAddr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE); /*! reset default val ! */ + if (ext_attr->has_lna == false) { + WR16(dev_addr, IQM_AF_AMUX__A, 0x02); + } + WR16(dev_addr, IQM_CF_SYMMETRIC__A, 0); + WR16(dev_addr, IQM_CF_MIDTAP__A, 3); + WR16(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_QAM__M); + + WR16(dev_addr, SCU_RAM_QAM_WR_RSV_0__A, 0x5f); /* scu temporary shut down agc */ + + WR16(dev_addr, IQM_AF_SYNC_SEL__A, 3); + WR16(dev_addr, IQM_AF_CLP_LEN__A, 0); + WR16(dev_addr, IQM_AF_CLP_TH__A, 448); + WR16(dev_addr, IQM_AF_SNS_LEN__A, 0); + WR16(dev_addr, IQM_AF_PDREF__A, 4); + WR16(dev_addr, IQM_AF_STDBY__A, 0x10); + WR16(dev_addr, IQM_AF_PGA_GAIN__A, 11); + + WR16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 1); + WR16(dev_addr, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE); /*! reset default val ! */ + + WR16(dev_addr, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE); /*! reset default val ! */ + if (ext_attr->standard == DRX_STANDARD_ITU_B) { + WR16(dev_addr, QAM_SY_SYNC_LWM__A, QAM_SY_SYNC_LWM__PRE); /*! reset default val ! */ + WR16(dev_addr, QAM_SY_SYNC_AWM__A, QAM_SY_SYNC_AWM__PRE); /*! reset default val ! */ + WR16(dev_addr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE); /*! reset default val ! */ } else { switch (channel->constellation) { case DRX_CONSTELLATION_QAM16: case DRX_CONSTELLATION_QAM64: case DRX_CONSTELLATION_QAM256: - WR16(devAddr, QAM_SY_SYNC_LWM__A, 0x03); - WR16(devAddr, QAM_SY_SYNC_AWM__A, 0x04); - WR16(devAddr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE); /*! reset default val ! */ + WR16(dev_addr, QAM_SY_SYNC_LWM__A, 0x03); + WR16(dev_addr, QAM_SY_SYNC_AWM__A, 0x04); + WR16(dev_addr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE); /*! reset default val ! */ break; case DRX_CONSTELLATION_QAM32: case DRX_CONSTELLATION_QAM128: - WR16(devAddr, QAM_SY_SYNC_LWM__A, 0x03); - WR16(devAddr, QAM_SY_SYNC_AWM__A, 0x05); - WR16(devAddr, QAM_SY_SYNC_HWM__A, 0x06); + WR16(dev_addr, QAM_SY_SYNC_LWM__A, 0x03); + WR16(dev_addr, QAM_SY_SYNC_AWM__A, 0x05); + WR16(dev_addr, QAM_SY_SYNC_HWM__A, 0x06); break; default: return (DRX_STS_ERROR); } /* switch */ } - WR16(devAddr, QAM_LC_MODE__A, QAM_LC_MODE__PRE); /*! reset default val ! */ - WR16(devAddr, QAM_LC_RATE_LIMIT__A, 3); - WR16(devAddr, QAM_LC_LPF_FACTORP__A, 4); - WR16(devAddr, QAM_LC_LPF_FACTORI__A, 4); - WR16(devAddr, QAM_LC_MODE__A, 7); - WR16(devAddr, QAM_LC_QUAL_TAB0__A, 1); - WR16(devAddr, QAM_LC_QUAL_TAB1__A, 1); - WR16(devAddr, QAM_LC_QUAL_TAB2__A, 1); - WR16(devAddr, QAM_LC_QUAL_TAB3__A, 1); - WR16(devAddr, QAM_LC_QUAL_TAB4__A, 2); - WR16(devAddr, QAM_LC_QUAL_TAB5__A, 2); - WR16(devAddr, QAM_LC_QUAL_TAB6__A, 2); - WR16(devAddr, QAM_LC_QUAL_TAB8__A, 2); - WR16(devAddr, QAM_LC_QUAL_TAB9__A, 2); - WR16(devAddr, QAM_LC_QUAL_TAB10__A, 2); - WR16(devAddr, QAM_LC_QUAL_TAB12__A, 2); - WR16(devAddr, QAM_LC_QUAL_TAB15__A, 3); - WR16(devAddr, QAM_LC_QUAL_TAB16__A, 3); - WR16(devAddr, QAM_LC_QUAL_TAB20__A, 4); - WR16(devAddr, QAM_LC_QUAL_TAB25__A, 4); - - WR16(devAddr, IQM_FS_ADJ_SEL__A, 1); - WR16(devAddr, IQM_RC_ADJ_SEL__A, 1); - WR16(devAddr, IQM_CF_ADJ_SEL__A, 1); - WR16(devAddr, IQM_CF_POW_MEAS_LEN__A, 0); - WR16(devAddr, SCU_RAM_GPIO__A, 0); + WR16(dev_addr, QAM_LC_MODE__A, QAM_LC_MODE__PRE); /*! reset default val ! */ + WR16(dev_addr, QAM_LC_RATE_LIMIT__A, 3); + WR16(dev_addr, QAM_LC_LPF_FACTORP__A, 4); + WR16(dev_addr, QAM_LC_LPF_FACTORI__A, 4); + WR16(dev_addr, QAM_LC_MODE__A, 7); + WR16(dev_addr, QAM_LC_QUAL_TAB0__A, 1); + WR16(dev_addr, QAM_LC_QUAL_TAB1__A, 1); + WR16(dev_addr, QAM_LC_QUAL_TAB2__A, 1); + WR16(dev_addr, QAM_LC_QUAL_TAB3__A, 1); + WR16(dev_addr, QAM_LC_QUAL_TAB4__A, 2); + WR16(dev_addr, QAM_LC_QUAL_TAB5__A, 2); + WR16(dev_addr, QAM_LC_QUAL_TAB6__A, 2); + WR16(dev_addr, QAM_LC_QUAL_TAB8__A, 2); + WR16(dev_addr, QAM_LC_QUAL_TAB9__A, 2); + WR16(dev_addr, QAM_LC_QUAL_TAB10__A, 2); + WR16(dev_addr, QAM_LC_QUAL_TAB12__A, 2); + WR16(dev_addr, QAM_LC_QUAL_TAB15__A, 3); + WR16(dev_addr, QAM_LC_QUAL_TAB16__A, 3); + WR16(dev_addr, QAM_LC_QUAL_TAB20__A, 4); + WR16(dev_addr, QAM_LC_QUAL_TAB25__A, 4); + + WR16(dev_addr, IQM_FS_ADJ_SEL__A, 1); + WR16(dev_addr, IQM_RC_ADJ_SEL__A, 1); + WR16(dev_addr, IQM_CF_ADJ_SEL__A, 1); + WR16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 0); + WR16(dev_addr, SCU_RAM_GPIO__A, 0); /* No more resets of the IQM, current standard correctly set => now AGCs can be configured. */ /* turn on IQMAF. It has to be in front of setAgc**() */ - CHK_ERROR(SetIqmAf(demod, true)); - CHK_ERROR(ADCSynchronization(demod)); + CHK_ERROR(set_iqm_af(demod, true)); + CHK_ERROR(adc_synchronization(demod)); - CHK_ERROR(InitAGC(demod)); - CHK_ERROR(SetAgcIf(demod, &(extAttr->qamIfAgcCfg), false)); - CHK_ERROR(SetAgcRf(demod, &(extAttr->qamRfAgcCfg), false)); + CHK_ERROR(init_agc(demod)); + CHK_ERROR(set_agc_if(demod, &(ext_attr->qam_if_agc_cfg), false)); + CHK_ERROR(set_agc_rf(demod, &(ext_attr->qam_rf_agc_cfg), false)); { - /* TODO fix this, store a DRXJCfgAfeGain_t structure in DRXJData_t instead + /* TODO fix this, store a drxj_cfg_afe_gain_t structure in drxj_data_t instead of only the gain */ - DRXJCfgAfeGain_t qamPgaCfg = { DRX_STANDARD_ITU_B, 0 }; + drxj_cfg_afe_gain_t qam_pga_cfg = { DRX_STANDARD_ITU_B, 0 }; - qamPgaCfg.gain = extAttr->qamPgaCfg; - CHK_ERROR(CtrlSetCfgAfeGain(demod, &qamPgaCfg)); + qam_pga_cfg.gain = ext_attr->qam_pga_cfg; + CHK_ERROR(ctrl_set_cfg_afe_gain(demod, &qam_pga_cfg)); } - CHK_ERROR(CtrlSetCfgPreSaw(demod, &(extAttr->qamPreSawCfg))); + CHK_ERROR(ctrl_set_cfg_pre_saw(demod, &(ext_attr->qam_pre_saw_cfg))); } if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) { - if (extAttr->standard == DRX_STANDARD_ITU_A) { - WRB(devAddr, IQM_CF_TAP_RE0__A, sizeof(qamA_taps), - ((u8 *) qamA_taps)); - WRB(devAddr, IQM_CF_TAP_IM0__A, sizeof(qamA_taps), - ((u8 *) qamA_taps)); - } else if (extAttr->standard == DRX_STANDARD_ITU_B) { + if (ext_attr->standard == DRX_STANDARD_ITU_A) { + WRB(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_a_taps), + ((u8 *) qam_a_taps)); + WRB(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_a_taps), + ((u8 *) qam_a_taps)); + } else if (ext_attr->standard == DRX_STANDARD_ITU_B) { switch (channel->constellation) { case DRX_CONSTELLATION_QAM64: - WRB(devAddr, IQM_CF_TAP_RE0__A, - sizeof(qamB64_taps), ((u8 *) qamB64_taps)); - WRB(devAddr, IQM_CF_TAP_IM0__A, - sizeof(qamB64_taps), ((u8 *) qamB64_taps)); + WRB(dev_addr, IQM_CF_TAP_RE0__A, + sizeof(qam_b64_taps), ((u8 *) qam_b64_taps)); + WRB(dev_addr, IQM_CF_TAP_IM0__A, + sizeof(qam_b64_taps), ((u8 *) qam_b64_taps)); break; case DRX_CONSTELLATION_QAM256: - WRB(devAddr, IQM_CF_TAP_RE0__A, - sizeof(qamB256_taps), - ((u8 *) qamB256_taps)); - WRB(devAddr, IQM_CF_TAP_IM0__A, - sizeof(qamB256_taps), - ((u8 *) qamB256_taps)); + WRB(dev_addr, IQM_CF_TAP_RE0__A, + sizeof(qam_b256_taps), + ((u8 *) qam_b256_taps)); + WRB(dev_addr, IQM_CF_TAP_IM0__A, + sizeof(qam_b256_taps), + ((u8 *) qam_b256_taps)); break; default: return (DRX_STS_ERROR); } - } else if (extAttr->standard == DRX_STANDARD_ITU_C) { - WRB(devAddr, IQM_CF_TAP_RE0__A, sizeof(qamC_taps), - ((u8 *) qamC_taps)); - WRB(devAddr, IQM_CF_TAP_IM0__A, sizeof(qamC_taps), - ((u8 *) qamC_taps)); + } else if (ext_attr->standard == DRX_STANDARD_ITU_C) { + WRB(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_c_taps), + ((u8 *) qam_c_taps)); + WRB(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_c_taps), + ((u8 *) qam_c_taps)); } /* SETP 4: constellation specific setup */ switch (channel->constellation) { case DRX_CONSTELLATION_QAM16: - CHK_ERROR(SetQAM16(demod)); + CHK_ERROR(set_qam16(demod)); break; case DRX_CONSTELLATION_QAM32: - CHK_ERROR(SetQAM32(demod)); + CHK_ERROR(set_qam32(demod)); break; case DRX_CONSTELLATION_QAM64: - CHK_ERROR(SetQAM64(demod)); + CHK_ERROR(set_qam64(demod)); break; case DRX_CONSTELLATION_QAM128: - CHK_ERROR(SetQAM128(demod)); + CHK_ERROR(set_qam128(demod)); break; case DRX_CONSTELLATION_QAM256: - CHK_ERROR(SetQAM256(demod)); + CHK_ERROR(set_qam256(demod)); break; default: return (DRX_STS_ERROR); @@ -7360,49 +7360,49 @@ SetQAM(pDRXDemodInstance_t demod, } if ((op & QAM_SET_OP_ALL)) { - WR16(devAddr, IQM_CF_SCALE_SH__A, 0); + WR16(dev_addr, IQM_CF_SCALE_SH__A, 0); /* Mpeg output has to be in front of FEC active */ - CHK_ERROR(SetMPEGTEIHandling(demod)); - CHK_ERROR(BitReverseMPEGOutput(demod)); - CHK_ERROR(SetMPEGStartWidth(demod)); + CHK_ERROR(set_mpegtei_handling(demod)); + CHK_ERROR(bit_reverse_mpeg_output(demod)); + CHK_ERROR(set_mpeg_start_width(demod)); { - /* TODO: move to setStandard after hardware reset value problem is solved */ + /* TODO: move to set_standard after hardware reset value problem is solved */ /* Configure initial MPEG output */ - DRXCfgMPEGOutput_t cfgMPEGOutput; + drx_cfg_mpeg_output_t cfg_mpeg_output; - cfgMPEGOutput.enableMPEGOutput = true; - cfgMPEGOutput.insertRSByte = - commonAttr->mpegCfg.insertRSByte; - cfgMPEGOutput.enableParallel = - commonAttr->mpegCfg.enableParallel; - cfgMPEGOutput.invertDATA = - commonAttr->mpegCfg.invertDATA; - cfgMPEGOutput.invertERR = commonAttr->mpegCfg.invertERR; - cfgMPEGOutput.invertSTR = commonAttr->mpegCfg.invertSTR; - cfgMPEGOutput.invertVAL = commonAttr->mpegCfg.invertVAL; - cfgMPEGOutput.invertCLK = commonAttr->mpegCfg.invertCLK; - cfgMPEGOutput.staticCLK = commonAttr->mpegCfg.staticCLK; - cfgMPEGOutput.bitrate = commonAttr->mpegCfg.bitrate; - CHK_ERROR(CtrlSetCfgMPEGOutput(demod, &cfgMPEGOutput)); + cfg_mpeg_output.enable_mpeg_output = true; + cfg_mpeg_output.insert_rs_byte = + common_attr->mpeg_cfg.insert_rs_byte; + cfg_mpeg_output.enable_parallel = + common_attr->mpeg_cfg.enable_parallel; + cfg_mpeg_output.invert_data = + common_attr->mpeg_cfg.invert_data; + cfg_mpeg_output.invert_err = common_attr->mpeg_cfg.invert_err; + cfg_mpeg_output.invert_str = common_attr->mpeg_cfg.invert_str; + cfg_mpeg_output.invert_val = common_attr->mpeg_cfg.invert_val; + cfg_mpeg_output.invert_clk = common_attr->mpeg_cfg.invert_clk; + cfg_mpeg_output.static_clk = common_attr->mpeg_cfg.static_clk; + cfg_mpeg_output.bitrate = common_attr->mpeg_cfg.bitrate; + CHK_ERROR(ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output)); } } if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) { /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */ - cmdSCU.command = SCU_RAM_COMMAND_STANDARD_QAM | + cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_START; - cmdSCU.parameterLen = 0; - cmdSCU.resultLen = 1; - cmdSCU.parameter = NULL; - cmdSCU.result = &cmdResult; - CHK_ERROR(SCUCommand(devAddr, &cmdSCU)); + cmd_scu.parameter_len = 0; + cmd_scu.result_len = 1; + cmd_scu.parameter = NULL; + cmd_scu.result = &cmd_result; + CHK_ERROR(scu_command(dev_addr, &cmd_scu)); } - WR16(devAddr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE); - WR16(devAddr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE); - WR16(devAddr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE); + WR16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE); + WR16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE); + WR16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE); return (DRX_STS_OK); rw_error: @@ -7411,83 +7411,83 @@ rw_error: /*============================================================================*/ static int -CtrlGetQAMSigQuality(pDRXDemodInstance_t demod, pDRXSigQuality_t sigQuality); -static int qamFlipSpec(pDRXDemodInstance_t demod, pDRXChannel_t channel) +ctrl_get_qam_sig_quality(pdrx_demod_instance_t demod, pdrx_sig_quality_t sig_quality); +static int qam_flip_spec(pdrx_demod_instance_t demod, pdrx_channel_t channel) { - u32 iqmFsRateOfs = 0; - u32 iqmFsRateLo = 0; - u16 qamCtlEna = 0; + u32 iqm_fs_rate_ofs = 0; + u32 iqm_fs_rate_lo = 0; + u16 qam_ctl_ena = 0; u16 data = 0; - u16 equMode = 0; - u16 fsmState = 0; + u16 equ_mode = 0; + u16 fsm_state = 0; int i = 0; int ofsofs = 0; - struct i2c_device_addr *devAddr = NULL; - pDRXJData_t extAttr = NULL; + struct i2c_device_addr *dev_addr = NULL; + pdrxj_data_t ext_attr = NULL; - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* Silence the controlling of lc, equ, and the acquisition state machine */ - RR16(devAddr, SCU_RAM_QAM_CTL_ENA__A, &qamCtlEna); - WR16(devAddr, SCU_RAM_QAM_CTL_ENA__A, qamCtlEna + RR16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, &qam_ctl_ena); + WR16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, qam_ctl_ena & ~(SCU_RAM_QAM_CTL_ENA_ACQ__M | SCU_RAM_QAM_CTL_ENA_EQU__M | SCU_RAM_QAM_CTL_ENA_LC__M)); /* freeze the frequency control loop */ - WR16(devAddr, QAM_LC_CF__A, 0); - WR16(devAddr, QAM_LC_CF1__A, 0); + WR16(dev_addr, QAM_LC_CF__A, 0); + WR16(dev_addr, QAM_LC_CF1__A, 0); - ARR32(devAddr, IQM_FS_RATE_OFS_LO__A, &iqmFsRateOfs); - ARR32(devAddr, IQM_FS_RATE_LO__A, &iqmFsRateLo); - ofsofs = iqmFsRateLo - iqmFsRateOfs; - iqmFsRateOfs = ~iqmFsRateOfs + 1; - iqmFsRateOfs -= 2 * ofsofs; + ARR32(dev_addr, IQM_FS_RATE_OFS_LO__A, &iqm_fs_rate_ofs); + ARR32(dev_addr, IQM_FS_RATE_LO__A, &iqm_fs_rate_lo); + ofsofs = iqm_fs_rate_lo - iqm_fs_rate_ofs; + iqm_fs_rate_ofs = ~iqm_fs_rate_ofs + 1; + iqm_fs_rate_ofs -= 2 * ofsofs; /* freeze dq/fq updating */ - RR16(devAddr, QAM_DQ_MODE__A, &data); + RR16(dev_addr, QAM_DQ_MODE__A, &data); data = (data & 0xfff9); - WR16(devAddr, QAM_DQ_MODE__A, data); - WR16(devAddr, QAM_FQ_MODE__A, data); + WR16(dev_addr, QAM_DQ_MODE__A, data); + WR16(dev_addr, QAM_FQ_MODE__A, data); /* lc_cp / _ci / _ca */ - WR16(devAddr, QAM_LC_CI__A, 0); - WR16(devAddr, QAM_LC_EP__A, 0); - WR16(devAddr, QAM_FQ_LA_FACTOR__A, 0); + WR16(dev_addr, QAM_LC_CI__A, 0); + WR16(dev_addr, QAM_LC_EP__A, 0); + WR16(dev_addr, QAM_FQ_LA_FACTOR__A, 0); /* flip the spec */ - WR32(devAddr, IQM_FS_RATE_OFS_LO__A, iqmFsRateOfs); - extAttr->iqmFsRateOfs = iqmFsRateOfs; - extAttr->posImage = (extAttr->posImage) ? false : true; + WR32(dev_addr, IQM_FS_RATE_OFS_LO__A, iqm_fs_rate_ofs); + ext_attr->iqm_fs_rate_ofs = iqm_fs_rate_ofs; + ext_attr->pos_image = (ext_attr->pos_image) ? false : true; /* freeze dq/fq updating */ - RR16(devAddr, QAM_DQ_MODE__A, &data); - equMode = data; + RR16(dev_addr, QAM_DQ_MODE__A, &data); + equ_mode = data; data = (data & 0xfff9); - WR16(devAddr, QAM_DQ_MODE__A, data); - WR16(devAddr, QAM_FQ_MODE__A, data); + WR16(dev_addr, QAM_DQ_MODE__A, data); + WR16(dev_addr, QAM_FQ_MODE__A, data); for (i = 0; i < 28; i++) { - RR16(devAddr, QAM_DQ_TAP_IM_EL0__A + (2 * i), &data); - WR16(devAddr, QAM_DQ_TAP_IM_EL0__A + (2 * i), -data); + RR16(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), &data); + WR16(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), -data); } for (i = 0; i < 24; i++) { - RR16(devAddr, QAM_FQ_TAP_IM_EL0__A + (2 * i), &data); - WR16(devAddr, QAM_FQ_TAP_IM_EL0__A + (2 * i), -data); + RR16(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), &data); + WR16(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), -data); } - data = equMode; - WR16(devAddr, QAM_DQ_MODE__A, data); - WR16(devAddr, QAM_FQ_MODE__A, data); + data = equ_mode; + WR16(dev_addr, QAM_DQ_MODE__A, data); + WR16(dev_addr, QAM_FQ_MODE__A, data); - WR16(devAddr, SCU_RAM_QAM_FSM_STATE_TGT__A, 4); + WR16(dev_addr, SCU_RAM_QAM_FSM_STATE_TGT__A, 4); i = 0; - while ((fsmState != 4) && (i++ < 100)) { - RR16(devAddr, SCU_RAM_QAM_FSM_STATE__A, &fsmState); + while ((fsm_state != 4) && (i++ < 100)) { + RR16(dev_addr, SCU_RAM_QAM_FSM_STATE__A, &fsm_state); } - WR16(devAddr, SCU_RAM_QAM_CTL_ENA__A, (qamCtlEna | 0x0016)); + WR16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, (qam_ctl_ena | 0x0016)); return (DRX_STS_OK); rw_error: @@ -7500,111 +7500,111 @@ rw_error: #define SYNC_FLIPPED 0x2 #define SPEC_MIRRORED 0x4 /** -* \fn int QAM64Auto () +* \fn int qam64auto () * \brief auto do sync pattern switching and mirroring. * \param demod: instance of demod. * \param channel: pointer to channel data. -* \param tunerFreqOffset: tuner frequency offset. -* \param lockStatus: pointer to lock status. +* \param tuner_freq_offset: tuner frequency offset. +* \param lock_status: pointer to lock status. * \return int. */ static int -QAM64Auto(pDRXDemodInstance_t demod, - pDRXChannel_t channel, - s32 tunerFreqOffset, pDRXLockStatus_t lockStatus) +qam64auto(pdrx_demod_instance_t demod, + pdrx_channel_t channel, + s32 tuner_freq_offset, pdrx_lock_status_t lock_status) { - DRXSigQuality_t sigQuality; + drx_sig_quality_t sig_quality; u16 data = 0; u32 state = NO_LOCK; - u32 startTime = 0; - u32 dLockedTime = 0; - pDRXJData_t extAttr = NULL; - u32 timeoutOfs = 0; + u32 start_time = 0; + u32 d_locked_time = 0; + pdrxj_data_t ext_attr = NULL; + u32 timeout_ofs = 0; /* external attributes for storing aquired channel constellation */ - extAttr = (pDRXJData_t) demod->myExtAttr; - *lockStatus = DRX_NOT_LOCKED; - startTime = DRXBSP_HST_Clock(); + ext_attr = (pdrxj_data_t) demod->my_ext_attr; + *lock_status = DRX_NOT_LOCKED; + start_time = drxbsp_hst_clock(); state = NO_LOCK; do { - CHK_ERROR(CtrlLockStatus(demod, lockStatus)); + CHK_ERROR(ctrl_lock_status(demod, lock_status)); switch (state) { case NO_LOCK: - if (*lockStatus == DRXJ_DEMOD_LOCK) { - CHK_ERROR(CtrlGetQAMSigQuality - (demod, &sigQuality)); - if (sigQuality.MER > 208) { + if (*lock_status == DRXJ_DEMOD_LOCK) { + CHK_ERROR(ctrl_get_qam_sig_quality + (demod, &sig_quality)); + if (sig_quality.MER > 208) { state = DEMOD_LOCKED; /* some delay to see if fec_lock possible TODO find the right value */ - timeoutOfs += DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME; /* see something, waiting longer */ - dLockedTime = DRXBSP_HST_Clock(); + timeout_ofs += DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME; /* see something, waiting longer */ + d_locked_time = drxbsp_hst_clock(); } } break; case DEMOD_LOCKED: - if ((*lockStatus == DRXJ_DEMOD_LOCK) && /* still demod_lock in 150ms */ - ((DRXBSP_HST_Clock() - dLockedTime) > + if ((*lock_status == DRXJ_DEMOD_LOCK) && /* still demod_lock in 150ms */ + ((drxbsp_hst_clock() - d_locked_time) > DRXJ_QAM_FEC_LOCK_WAITTIME)) { - RR16(demod->myI2CDevAddr, QAM_SY_TIMEOUT__A, + RR16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data); - WR16(demod->myI2CDevAddr, QAM_SY_TIMEOUT__A, + WR16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1); state = SYNC_FLIPPED; - DRXBSP_HST_Sleep(10); + drxbsp_hst_sleep(10); } break; case SYNC_FLIPPED: - if (*lockStatus == DRXJ_DEMOD_LOCK) { + if (*lock_status == DRXJ_DEMOD_LOCK) { if (channel->mirror == DRX_MIRROR_AUTO) { /* flip sync pattern back */ - RR16(demod->myI2CDevAddr, + RR16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data); - WR16(demod->myI2CDevAddr, + WR16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data & 0xFFFE); /* flip spectrum */ - extAttr->mirror = DRX_MIRROR_YES; - CHK_ERROR(qamFlipSpec(demod, channel)); + ext_attr->mirror = DRX_MIRROR_YES; + CHK_ERROR(qam_flip_spec(demod, channel)); state = SPEC_MIRRORED; /* reset timer TODO: still need 500ms? */ - startTime = dLockedTime = - DRXBSP_HST_Clock(); - timeoutOfs = 0; + start_time = d_locked_time = + drxbsp_hst_clock(); + timeout_ofs = 0; } else { /* no need to wait lock */ - startTime = - DRXBSP_HST_Clock() - - DRXJ_QAM_MAX_WAITTIME - timeoutOfs; + start_time = + drxbsp_hst_clock() - + DRXJ_QAM_MAX_WAITTIME - timeout_ofs; } } break; case SPEC_MIRRORED: - if ((*lockStatus == DRXJ_DEMOD_LOCK) && /* still demod_lock in 150ms */ - ((DRXBSP_HST_Clock() - dLockedTime) > + if ((*lock_status == DRXJ_DEMOD_LOCK) && /* still demod_lock in 150ms */ + ((drxbsp_hst_clock() - d_locked_time) > DRXJ_QAM_FEC_LOCK_WAITTIME)) { - CHK_ERROR(CtrlGetQAMSigQuality - (demod, &sigQuality)); - if (sigQuality.MER > 208) { - RR16(demod->myI2CDevAddr, + CHK_ERROR(ctrl_get_qam_sig_quality + (demod, &sig_quality)); + if (sig_quality.MER > 208) { + RR16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data); - WR16(demod->myI2CDevAddr, + WR16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1); /* no need to wait lock */ - startTime = - DRXBSP_HST_Clock() - - DRXJ_QAM_MAX_WAITTIME - timeoutOfs; + start_time = + drxbsp_hst_clock() - + DRXJ_QAM_MAX_WAITTIME - timeout_ofs; } } break; default: break; } - DRXBSP_HST_Sleep(10); + drxbsp_hst_sleep(10); } while - ((*lockStatus != DRX_LOCKED) && - (*lockStatus != DRX_NEVER_LOCK) && - ((DRXBSP_HST_Clock() - startTime) < - (DRXJ_QAM_MAX_WAITTIME + timeoutOfs)) + ((*lock_status != DRX_LOCKED) && + (*lock_status != DRX_NEVER_LOCK) && + ((drxbsp_hst_clock() - start_time) < + (DRXJ_QAM_MAX_WAITTIME + timeout_ofs)) ); /* Returning control to apllication ... */ @@ -7614,56 +7614,56 @@ rw_error: } /** -* \fn int QAM256Auto () +* \fn int qam256auto () * \brief auto do sync pattern switching and mirroring. * \param demod: instance of demod. * \param channel: pointer to channel data. -* \param tunerFreqOffset: tuner frequency offset. -* \param lockStatus: pointer to lock status. +* \param tuner_freq_offset: tuner frequency offset. +* \param lock_status: pointer to lock status. * \return int. */ static int -QAM256Auto(pDRXDemodInstance_t demod, - pDRXChannel_t channel, - s32 tunerFreqOffset, pDRXLockStatus_t lockStatus) +qam256auto(pdrx_demod_instance_t demod, + pdrx_channel_t channel, + s32 tuner_freq_offset, pdrx_lock_status_t lock_status) { - DRXSigQuality_t sigQuality; + drx_sig_quality_t sig_quality; u32 state = NO_LOCK; - u32 startTime = 0; - u32 dLockedTime = 0; - pDRXJData_t extAttr = NULL; - u32 timeoutOfs = DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME; + u32 start_time = 0; + u32 d_locked_time = 0; + pdrxj_data_t ext_attr = NULL; + u32 timeout_ofs = DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME; /* external attributes for storing aquired channel constellation */ - extAttr = (pDRXJData_t) demod->myExtAttr; - *lockStatus = DRX_NOT_LOCKED; - startTime = DRXBSP_HST_Clock(); + ext_attr = (pdrxj_data_t) demod->my_ext_attr; + *lock_status = DRX_NOT_LOCKED; + start_time = drxbsp_hst_clock(); state = NO_LOCK; do { - CHK_ERROR(CtrlLockStatus(demod, lockStatus)); + CHK_ERROR(ctrl_lock_status(demod, lock_status)); switch (state) { case NO_LOCK: - if (*lockStatus == DRXJ_DEMOD_LOCK) { - CHK_ERROR(CtrlGetQAMSigQuality - (demod, &sigQuality)); - if (sigQuality.MER > 268) { + if (*lock_status == DRXJ_DEMOD_LOCK) { + CHK_ERROR(ctrl_get_qam_sig_quality + (demod, &sig_quality)); + if (sig_quality.MER > 268) { state = DEMOD_LOCKED; - timeoutOfs += DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME; /* see something, wait longer */ - dLockedTime = DRXBSP_HST_Clock(); + timeout_ofs += DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME; /* see something, wait longer */ + d_locked_time = drxbsp_hst_clock(); } } break; case DEMOD_LOCKED: - if (*lockStatus == DRXJ_DEMOD_LOCK) { + if (*lock_status == DRXJ_DEMOD_LOCK) { if ((channel->mirror == DRX_MIRROR_AUTO) && - ((DRXBSP_HST_Clock() - dLockedTime) > + ((drxbsp_hst_clock() - d_locked_time) > DRXJ_QAM_FEC_LOCK_WAITTIME)) { - extAttr->mirror = DRX_MIRROR_YES; - CHK_ERROR(qamFlipSpec(demod, channel)); + ext_attr->mirror = DRX_MIRROR_YES; + CHK_ERROR(qam_flip_spec(demod, channel)); state = SPEC_MIRRORED; /* reset timer TODO: still need 300ms? */ - startTime = DRXBSP_HST_Clock(); - timeoutOfs = -DRXJ_QAM_MAX_WAITTIME / 2; + start_time = drxbsp_hst_clock(); + timeout_ofs = -DRXJ_QAM_MAX_WAITTIME / 2; } } break; @@ -7672,12 +7672,12 @@ QAM256Auto(pDRXDemodInstance_t demod, default: break; } - DRXBSP_HST_Sleep(10); + drxbsp_hst_sleep(10); } while - ((*lockStatus < DRX_LOCKED) && - (*lockStatus != DRX_NEVER_LOCK) && - ((DRXBSP_HST_Clock() - startTime) < - (DRXJ_QAM_MAX_WAITTIME + timeoutOfs))); + ((*lock_status < DRX_LOCKED) && + (*lock_status != DRX_NEVER_LOCK) && + ((drxbsp_hst_clock() - start_time) < + (DRXJ_QAM_MAX_WAITTIME + timeout_ofs))); return (DRX_STS_OK); rw_error: @@ -7685,22 +7685,22 @@ rw_error: } /** -* \fn int SetQAMChannel () +* \fn int set_qamChannel () * \brief Set QAM channel according to the requested constellation. * \param demod: instance of demod. * \param channel: pointer to channel data. * \return int. */ static int -SetQAMChannel(pDRXDemodInstance_t demod, - pDRXChannel_t channel, s32 tunerFreqOffset) +set_qamChannel(pdrx_demod_instance_t demod, + pdrx_channel_t channel, s32 tuner_freq_offset) { - DRXLockStatus_t lockStatus = DRX_NOT_LOCKED; - pDRXJData_t extAttr = NULL; - bool autoFlag = false; + drx_lock_status_t lock_status = DRX_NOT_LOCKED; + pdrxj_data_t ext_attr = NULL; + bool auto_flag = false; /* external attributes for storing aquired channel constellation */ - extAttr = (pDRXJData_t) demod->myExtAttr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* set QAM channel constellation */ switch (channel->constellation) { @@ -7709,110 +7709,110 @@ SetQAMChannel(pDRXDemodInstance_t demod, case DRX_CONSTELLATION_QAM64: case DRX_CONSTELLATION_QAM128: case DRX_CONSTELLATION_QAM256: - extAttr->constellation = channel->constellation; + ext_attr->constellation = channel->constellation; if (channel->mirror == DRX_MIRROR_AUTO) { - extAttr->mirror = DRX_MIRROR_NO; + ext_attr->mirror = DRX_MIRROR_NO; } else { - extAttr->mirror = channel->mirror; + ext_attr->mirror = channel->mirror; } - CHK_ERROR(SetQAM - (demod, channel, tunerFreqOffset, QAM_SET_OP_ALL)); + CHK_ERROR(set_qam + (demod, channel, tuner_freq_offset, QAM_SET_OP_ALL)); - if ((extAttr->standard == DRX_STANDARD_ITU_B) && + if ((ext_attr->standard == DRX_STANDARD_ITU_B) && (channel->constellation == DRX_CONSTELLATION_QAM64)) { - CHK_ERROR(QAM64Auto - (demod, channel, tunerFreqOffset, - &lockStatus)); + CHK_ERROR(qam64auto + (demod, channel, tuner_freq_offset, + &lock_status)); } - if ((extAttr->standard == DRX_STANDARD_ITU_B) && + if ((ext_attr->standard == DRX_STANDARD_ITU_B) && (channel->mirror == DRX_MIRROR_AUTO) && (channel->constellation == DRX_CONSTELLATION_QAM256)) { - CHK_ERROR(QAM256Auto - (demod, channel, tunerFreqOffset, - &lockStatus)); + CHK_ERROR(qam256auto + (demod, channel, tuner_freq_offset, + &lock_status)); } break; case DRX_CONSTELLATION_AUTO: /* for channel scan */ - if (extAttr->standard == DRX_STANDARD_ITU_B) { - autoFlag = true; + if (ext_attr->standard == DRX_STANDARD_ITU_B) { + auto_flag = true; /* try to lock default QAM constellation: QAM64 */ channel->constellation = DRX_CONSTELLATION_QAM256; - extAttr->constellation = DRX_CONSTELLATION_QAM256; + ext_attr->constellation = DRX_CONSTELLATION_QAM256; if (channel->mirror == DRX_MIRROR_AUTO) { - extAttr->mirror = DRX_MIRROR_NO; + ext_attr->mirror = DRX_MIRROR_NO; } else { - extAttr->mirror = channel->mirror; + ext_attr->mirror = channel->mirror; } - CHK_ERROR(SetQAM - (demod, channel, tunerFreqOffset, + CHK_ERROR(set_qam + (demod, channel, tuner_freq_offset, QAM_SET_OP_ALL)); - CHK_ERROR(QAM256Auto - (demod, channel, tunerFreqOffset, - &lockStatus)); + CHK_ERROR(qam256auto + (demod, channel, tuner_freq_offset, + &lock_status)); - if (lockStatus < DRX_LOCKED) { + if (lock_status < DRX_LOCKED) { /* QAM254 not locked -> try to lock QAM64 constellation */ channel->constellation = DRX_CONSTELLATION_QAM64; - extAttr->constellation = + ext_attr->constellation = DRX_CONSTELLATION_QAM64; if (channel->mirror == DRX_MIRROR_AUTO) { - extAttr->mirror = DRX_MIRROR_NO; + ext_attr->mirror = DRX_MIRROR_NO; } else { - extAttr->mirror = channel->mirror; + ext_attr->mirror = channel->mirror; } { - u16 qamCtlEna = 0; - RR16(demod->myI2CDevAddr, + u16 qam_ctl_ena = 0; + RR16(demod->my_i2c_dev_addr, SCU_RAM_QAM_CTL_ENA__A, - &qamCtlEna); - WR16(demod->myI2CDevAddr, + &qam_ctl_ena); + WR16(demod->my_i2c_dev_addr, SCU_RAM_QAM_CTL_ENA__A, - qamCtlEna & + qam_ctl_ena & ~SCU_RAM_QAM_CTL_ENA_ACQ__M); - WR16(demod->myI2CDevAddr, SCU_RAM_QAM_FSM_STATE_TGT__A, 0x2); /* force to rate hunting */ + WR16(demod->my_i2c_dev_addr, SCU_RAM_QAM_FSM_STATE_TGT__A, 0x2); /* force to rate hunting */ - CHK_ERROR(SetQAM + CHK_ERROR(set_qam (demod, channel, - tunerFreqOffset, + tuner_freq_offset, QAM_SET_OP_CONSTELLATION)); - WR16(demod->myI2CDevAddr, - SCU_RAM_QAM_CTL_ENA__A, qamCtlEna); + WR16(demod->my_i2c_dev_addr, + SCU_RAM_QAM_CTL_ENA__A, qam_ctl_ena); } - CHK_ERROR(QAM64Auto - (demod, channel, tunerFreqOffset, - &lockStatus)); + CHK_ERROR(qam64auto + (demod, channel, tuner_freq_offset, + &lock_status)); } channel->constellation = DRX_CONSTELLATION_AUTO; - } else if (extAttr->standard == DRX_STANDARD_ITU_C) { + } else if (ext_attr->standard == DRX_STANDARD_ITU_C) { channel->constellation = DRX_CONSTELLATION_QAM64; - extAttr->constellation = DRX_CONSTELLATION_QAM64; - autoFlag = true; + ext_attr->constellation = DRX_CONSTELLATION_QAM64; + auto_flag = true; if (channel->mirror == DRX_MIRROR_AUTO) { - extAttr->mirror = DRX_MIRROR_NO; + ext_attr->mirror = DRX_MIRROR_NO; } else { - extAttr->mirror = channel->mirror; + ext_attr->mirror = channel->mirror; } { - u16 qamCtlEna = 0; - RR16(demod->myI2CDevAddr, - SCU_RAM_QAM_CTL_ENA__A, &qamCtlEna); - WR16(demod->myI2CDevAddr, + u16 qam_ctl_ena = 0; + RR16(demod->my_i2c_dev_addr, + SCU_RAM_QAM_CTL_ENA__A, &qam_ctl_ena); + WR16(demod->my_i2c_dev_addr, SCU_RAM_QAM_CTL_ENA__A, - qamCtlEna & ~SCU_RAM_QAM_CTL_ENA_ACQ__M); - WR16(demod->myI2CDevAddr, SCU_RAM_QAM_FSM_STATE_TGT__A, 0x2); /* force to rate hunting */ + qam_ctl_ena & ~SCU_RAM_QAM_CTL_ENA_ACQ__M); + WR16(demod->my_i2c_dev_addr, SCU_RAM_QAM_FSM_STATE_TGT__A, 0x2); /* force to rate hunting */ - CHK_ERROR(SetQAM - (demod, channel, tunerFreqOffset, + CHK_ERROR(set_qam + (demod, channel, tuner_freq_offset, QAM_SET_OP_CONSTELLATION)); - WR16(demod->myI2CDevAddr, - SCU_RAM_QAM_CTL_ENA__A, qamCtlEna); + WR16(demod->my_i2c_dev_addr, + SCU_RAM_QAM_CTL_ENA__A, qam_ctl_ena); } - CHK_ERROR(QAM64Auto - (demod, channel, tunerFreqOffset, - &lockStatus)); + CHK_ERROR(qam64auto + (demod, channel, tuner_freq_offset, + &lock_status)); channel->constellation = DRX_CONSTELLATION_AUTO; } else { channel->constellation = DRX_CONSTELLATION_AUTO; @@ -7826,7 +7826,7 @@ SetQAMChannel(pDRXDemodInstance_t demod, return (DRX_STS_OK); rw_error: /* restore starting value */ - if (autoFlag) + if (auto_flag) channel->constellation = DRX_CONSTELLATION_AUTO; return (DRX_STS_ERROR); } @@ -7834,7 +7834,7 @@ rw_error: /*============================================================================*/ /** -* \fn static short GetQAMRSErrCount(struct i2c_device_addr *devAddr) +* \fn static short GetQAMRSErr_count(struct i2c_device_addr *dev_addr) * \brief Get RS error count in QAM mode (used for post RS BER calculation) * \return Error code * @@ -7842,39 +7842,39 @@ rw_error: * */ static int -GetQAMRSErrCount(struct i2c_device_addr *devAddr, pDRXJRSErrors_t RSErrors) +GetQAMRSErr_count(struct i2c_device_addr *dev_addr, p_drxjrs_errors_t rs_errors) { - u16 nrBitErrors = 0, - nrSymbolErrors = 0, - nrPacketErrors = 0, nrFailures = 0, nrSncParFailCount = 0; + u16 nr_bit_errors = 0, + nr_symbol_errors = 0, + nr_packet_errors = 0, nr_failures = 0, nr_snc_par_fail_count = 0; /* check arguments */ - if (devAddr == NULL) { + if (dev_addr == NULL) { return (DRX_STS_INVALID_ARG); } /* all reported errors are received in the */ /* most recently finished measurment period */ /* no of pre RS bit errors */ - RR16(devAddr, FEC_RS_NR_BIT_ERRORS__A, &nrBitErrors); + RR16(dev_addr, FEC_RS_NR_BIT_ERRORS__A, &nr_bit_errors); /* no of symbol errors */ - RR16(devAddr, FEC_RS_NR_SYMBOL_ERRORS__A, &nrSymbolErrors); + RR16(dev_addr, FEC_RS_NR_SYMBOL_ERRORS__A, &nr_symbol_errors); /* no of packet errors */ - RR16(devAddr, FEC_RS_NR_PACKET_ERRORS__A, &nrPacketErrors); + RR16(dev_addr, FEC_RS_NR_PACKET_ERRORS__A, &nr_packet_errors); /* no of failures to decode */ - RR16(devAddr, FEC_RS_NR_FAILURES__A, &nrFailures); + RR16(dev_addr, FEC_RS_NR_FAILURES__A, &nr_failures); /* no of post RS bit erros */ - RR16(devAddr, FEC_OC_SNC_FAIL_COUNT__A, &nrSncParFailCount); + RR16(dev_addr, FEC_OC_SNC_FAIL_COUNT__A, &nr_snc_par_fail_count); /* TODO: NOTE */ /* These register values are fetched in non-atomic fashion */ /* It is possible that the read values contain unrelated information */ - RSErrors->nrBitErrors = nrBitErrors & FEC_RS_NR_BIT_ERRORS__M; - RSErrors->nrSymbolErrors = nrSymbolErrors & FEC_RS_NR_SYMBOL_ERRORS__M; - RSErrors->nrPacketErrors = nrPacketErrors & FEC_RS_NR_PACKET_ERRORS__M; - RSErrors->nrFailures = nrFailures & FEC_RS_NR_FAILURES__M; - RSErrors->nrSncParFailCount = - nrSncParFailCount & FEC_OC_SNC_FAIL_COUNT__M; + rs_errors->nr_bit_errors = nr_bit_errors & FEC_RS_NR_BIT_ERRORS__M; + rs_errors->nr_symbol_errors = nr_symbol_errors & FEC_RS_NR_SYMBOL_ERRORS__M; + rs_errors->nr_packet_errors = nr_packet_errors & FEC_RS_NR_PACKET_ERRORS__M; + rs_errors->nr_failures = nr_failures & FEC_RS_NR_FAILURES__M; + rs_errors->nr_snc_par_fail_count = + nr_snc_par_fail_count & FEC_OC_SNC_FAIL_COUNT__M; return (DRX_STS_OK); rw_error: @@ -7884,86 +7884,86 @@ rw_error: /*============================================================================*/ /** -* \fn int CtrlGetQAMSigQuality() +* \fn int ctrl_get_qam_sig_quality() * \brief Retreive QAM signal quality from device. * \param devmod Pointer to demodulator instance. -* \param sigQuality Pointer to signal quality data. +* \param sig_quality Pointer to signal quality data. * \return int. -* \retval DRX_STS_OK sigQuality contains valid data. -* \retval DRX_STS_INVALID_ARG sigQuality is NULL. -* \retval DRX_STS_ERROR Erroneous data, sigQuality contains invalid data. +* \retval DRX_STS_OK sig_quality contains valid data. +* \retval DRX_STS_INVALID_ARG sig_quality is NULL. +* \retval DRX_STS_ERROR Erroneous data, sig_quality contains invalid data. * Pre-condition: Device must be started and in lock. */ static int -CtrlGetQAMSigQuality(pDRXDemodInstance_t demod, pDRXSigQuality_t sigQuality) +ctrl_get_qam_sig_quality(pdrx_demod_instance_t demod, pdrx_sig_quality_t sig_quality) { - struct i2c_device_addr *devAddr = NULL; - pDRXJData_t extAttr = NULL; + struct i2c_device_addr *dev_addr = NULL; + pdrxj_data_t ext_attr = NULL; enum drx_modulation constellation = DRX_CONSTELLATION_UNKNOWN; - DRXJRSErrors_t measuredRSErrors = { 0, 0, 0, 0, 0 }; - - u32 preBitErrRS = 0; /* pre RedSolomon Bit Error Rate */ - u32 postBitErrRS = 0; /* post RedSolomon Bit Error Rate */ - u32 pktErrs = 0; /* no of packet errors in RS */ - u16 qamSlErrPower = 0; /* accumulated error between raw and sliced symbols */ - u16 qsymErrVD = 0; /* quadrature symbol errors in QAM_VD */ - u16 fecOcPeriod = 0; /* SNC sync failure measurement period */ - u16 fecRsPrescale = 0; /* ReedSolomon Measurement Prescale */ - u16 fecRsPeriod = 0; /* Value for corresponding I2C register */ + DRXJrs_errors_t measuredrs_errors = { 0, 0, 0, 0, 0 }; + + u32 pre_bit_err_rs = 0; /* pre RedSolomon Bit Error Rate */ + u32 post_bit_err_rs = 0; /* post RedSolomon Bit Error Rate */ + u32 pkt_errs = 0; /* no of packet errors in RS */ + u16 qam_sl_err_power = 0; /* accumulated error between raw and sliced symbols */ + u16 qsym_err_vd = 0; /* quadrature symbol errors in QAM_VD */ + u16 fec_oc_period = 0; /* SNC sync failure measurement period */ + u16 fec_rs_prescale = 0; /* ReedSolomon Measurement Prescale */ + u16 fec_rs_period = 0; /* Value for corresponding I2C register */ /* calculation constants */ - u32 rsBitCnt = 0; /* RedSolomon Bit Count */ - u32 qamSlSigPower = 0; /* used for MER, depends of QAM constellation */ + u32 rs_bit_cnt = 0; /* RedSolomon Bit Count */ + u32 qam_sl_sig_power = 0; /* used for MER, depends of QAM constellation */ /* intermediate results */ u32 e = 0; /* exponent value used for QAM BER/SER */ u32 m = 0; /* mantisa value used for QAM BER/SER */ - u32 berCnt = 0; /* BER count */ + u32 ber_cnt = 0; /* BER count */ /* signal quality info */ - u32 qamSlMer = 0; /* QAM MER */ - u32 qamPreRSBer = 0; /* Pre RedSolomon BER */ - u32 qamPostRSBer = 0; /* Post RedSolomon BER */ - u32 qamVDSer = 0; /* ViterbiDecoder SER */ - u16 qamVdPrescale = 0; /* Viterbi Measurement Prescale */ - u16 qamVdPeriod = 0; /* Viterbi Measurement period */ - u32 vdBitCnt = 0; /* ViterbiDecoder Bit Count */ + u32 qam_sl_mer = 0; /* QAM MER */ + u32 qam_pre_rs_ber = 0; /* Pre RedSolomon BER */ + u32 qam_post_rs_ber = 0; /* Post RedSolomon BER */ + u32 qam_vd_ser = 0; /* ViterbiDecoder SER */ + u16 qam_vd_prescale = 0; /* Viterbi Measurement Prescale */ + u16 qam_vd_period = 0; /* Viterbi Measurement period */ + u32 vd_bit_cnt = 0; /* ViterbiDecoder Bit Count */ /* get device basic information */ - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; - constellation = extAttr->constellation; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; + constellation = ext_attr->constellation; /* read the physical registers */ /* Get the RS error data */ - CHK_ERROR(GetQAMRSErrCount(devAddr, &measuredRSErrors)); + CHK_ERROR(GetQAMRSErr_count(dev_addr, &measuredrs_errors)); /* get the register value needed for MER */ - RR16(devAddr, QAM_SL_ERR_POWER__A, &qamSlErrPower); + RR16(dev_addr, QAM_SL_ERR_POWER__A, &qam_sl_err_power); /* get the register value needed for post RS BER */ - RR16(devAddr, FEC_OC_SNC_FAIL_PERIOD__A, &fecOcPeriod); + RR16(dev_addr, FEC_OC_SNC_FAIL_PERIOD__A, &fec_oc_period); /* get constants needed for signal quality calculation */ - fecRsPeriod = extAttr->fecRsPeriod; - fecRsPrescale = extAttr->fecRsPrescale; - rsBitCnt = fecRsPeriod * fecRsPrescale * extAttr->fecRsPlen; - qamVdPeriod = extAttr->qamVdPeriod; - qamVdPrescale = extAttr->qamVdPrescale; - vdBitCnt = qamVdPeriod * qamVdPrescale * extAttr->fecVdPlen; + fec_rs_period = ext_attr->fec_rs_period; + fec_rs_prescale = ext_attr->fec_rs_prescale; + rs_bit_cnt = fec_rs_period * fec_rs_prescale * ext_attr->fec_rs_plen; + qam_vd_period = ext_attr->qam_vd_period; + qam_vd_prescale = ext_attr->qam_vd_prescale; + vd_bit_cnt = qam_vd_period * qam_vd_prescale * ext_attr->fec_vd_plen; /* DRXJ_QAM_SL_SIG_POWER_QAMxxx * 4 */ switch (constellation) { case DRX_CONSTELLATION_QAM16: - qamSlSigPower = DRXJ_QAM_SL_SIG_POWER_QAM16 << 2; + qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM16 << 2; break; case DRX_CONSTELLATION_QAM32: - qamSlSigPower = DRXJ_QAM_SL_SIG_POWER_QAM32 << 2; + qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM32 << 2; break; case DRX_CONSTELLATION_QAM64: - qamSlSigPower = DRXJ_QAM_SL_SIG_POWER_QAM64 << 2; + qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM64 << 2; break; case DRX_CONSTELLATION_QAM128: - qamSlSigPower = DRXJ_QAM_SL_SIG_POWER_QAM128 << 2; + qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM128 << 2; break; case DRX_CONSTELLATION_QAM256: - qamSlSigPower = DRXJ_QAM_SL_SIG_POWER_QAM256 << 2; + qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM256 << 2; break; default: return (DRX_STS_ERROR); @@ -7975,12 +7975,12 @@ CtrlGetQAMSigQuality(pDRXDemodInstance_t demod, pDRXSigQuality_t sigQuality) /* MER is good if it is above 27.5 for QAM256 or 21.5 for QAM64 */ /* 10.0*log10(qam_sl_sig_power * 4.0 / qam_sl_err_power); */ - if (qamSlErrPower == 0) - qamSlMer = 0; + if (qam_sl_err_power == 0) + qam_sl_mer = 0; else - qamSlMer = - Log10Times100(qamSlSigPower) - - Log10Times100((u32) qamSlErrPower); + qam_sl_mer = + log1_times100(qam_sl_sig_power) - + log1_times100((u32) qam_sl_err_power); /* ----------------------------------------- */ /* Pre Viterbi Symbol Error Rate Calculation */ @@ -7989,20 +7989,20 @@ CtrlGetQAMSigQuality(pDRXDemodInstance_t demod, pDRXSigQuality_t sigQuality) /* get the register value */ /* no of quadrature symbol errors */ - RR16(devAddr, QAM_VD_NR_QSYM_ERRORS__A, &qsymErrVD); + RR16(dev_addr, QAM_VD_NR_QSYM_ERRORS__A, &qsym_err_vd); /* Extract the Exponent and the Mantisa */ /* of number of quadrature symbol errors */ - e = (qsymErrVD & QAM_VD_NR_QSYM_ERRORS_EXP__M) >> + e = (qsym_err_vd & QAM_VD_NR_QSYM_ERRORS_EXP__M) >> QAM_VD_NR_QSYM_ERRORS_EXP__B; - m = (qsymErrVD & QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__M) >> + m = (qsym_err_vd & QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__M) >> QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__B; - if ((m << e) >> 3 > 549752) { /* the max of FracTimes1e6 */ - qamVDSer = 500000; /* clip BER 0.5 */ + if ((m << e) >> 3 > 549752) { /* the max of frac_times1e6 */ + qam_vd_ser = 500000; /* clip BER 0.5 */ } else { - qamVDSer = - FracTimes1e6(m << ((e > 2) ? (e - 3) : e), - vdBitCnt * ((e > 2) ? 1 : 8) / 8); + qam_vd_ser = + frac_times1e6(m << ((e > 2) ? (e - 3) : e), + vd_bit_cnt * ((e > 2) ? 1 : 8) / 8); } /* --------------------------------------- */ @@ -8011,23 +8011,23 @@ CtrlGetQAMSigQuality(pDRXDemodInstance_t demod, pDRXSigQuality_t sigQuality) /* pre RS BER is good if it is below 3.5e-4 */ /* get the register values */ - preBitErrRS = (u32) measuredRSErrors.nrBitErrors; - pktErrs = postBitErrRS = (u32) measuredRSErrors.nrSncParFailCount; + pre_bit_err_rs = (u32) measuredrs_errors.nr_bit_errors; + pkt_errs = post_bit_err_rs = (u32) measuredrs_errors.nr_snc_par_fail_count; /* Extract the Exponent and the Mantisa of the */ /* pre Reed-Solomon bit error count */ - e = (preBitErrRS & FEC_RS_NR_BIT_ERRORS_EXP__M) >> + e = (pre_bit_err_rs & FEC_RS_NR_BIT_ERRORS_EXP__M) >> FEC_RS_NR_BIT_ERRORS_EXP__B; - m = (preBitErrRS & FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M) >> + m = (pre_bit_err_rs & FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M) >> FEC_RS_NR_BIT_ERRORS_FIXED_MANT__B; - berCnt = m << e; + ber_cnt = m << e; - /*qamPreRSBer = FracTimes1e6( berCnt, rsBitCnt ); */ - if (m > (rsBitCnt >> (e + 1)) || (rsBitCnt >> e) == 0) { - qamPreRSBer = 500000; /* clip BER 0.5 */ + /*qam_pre_rs_ber = frac_times1e6( ber_cnt, rs_bit_cnt ); */ + if (m > (rs_bit_cnt >> (e + 1)) || (rs_bit_cnt >> e) == 0) { + qam_pre_rs_ber = 500000; /* clip BER 0.5 */ } else { - qamPreRSBer = FracTimes1e6(m, rsBitCnt >> e); + qam_pre_rs_ber = frac_times1e6(m, rs_bit_cnt >> e); } /* post RS BER = 1000000* (11.17 * FEC_OC_SNC_FAIL_COUNT__A) / */ @@ -8041,27 +8041,27 @@ CtrlGetQAMSigQuality(pDRXDemodInstance_t demod, pDRXSigQuality_t sigQuality) Precision errors still possible. */ - e = postBitErrRS * 742686; - m = fecOcPeriod * 100; - if (fecOcPeriod == 0) - qamPostRSBer = 0xFFFFFFFF; + e = post_bit_err_rs * 742686; + m = fec_oc_period * 100; + if (fec_oc_period == 0) + qam_post_rs_ber = 0xFFFFFFFF; else - qamPostRSBer = e / m; + qam_post_rs_ber = e / m; /* fill signal quality data structure */ - sigQuality->MER = ((u16) qamSlMer); - if (extAttr->standard == DRX_STANDARD_ITU_B) { - sigQuality->preViterbiBER = qamVDSer; + sig_quality->MER = ((u16) qam_sl_mer); + if (ext_attr->standard == DRX_STANDARD_ITU_B) { + sig_quality->pre_viterbi_ber = qam_vd_ser; } else { - sigQuality->preViterbiBER = qamPreRSBer; + sig_quality->pre_viterbi_ber = qam_pre_rs_ber; } - sigQuality->postViterbiBER = qamPreRSBer; - sigQuality->postReedSolomonBER = qamPostRSBer; - sigQuality->scaleFactorBER = ((u32) 1000000); + sig_quality->post_viterbi_ber = qam_pre_rs_ber; + sig_quality->post_reed_solomon_ber = qam_post_rs_ber; + sig_quality->scale_factor_ber = ((u32) 1000000); #ifdef DRXJ_SIGNAL_ACCUM_ERR - CHK_ERROR(GetAccPktErr(demod, &sigQuality->packetError)); + CHK_ERROR(get_acc_pkt_err(demod, &sig_quality->packet_error)); #else - sigQuality->packetError = ((u16) pktErrs); + sig_quality->packet_error = ((u16) pkt_errs); #endif return (DRX_STS_OK); @@ -8070,45 +8070,45 @@ rw_error: } /** -* \fn int CtrlGetQAMConstel() +* \fn int ctrl_get_qam_constel() * \brief Retreive a QAM constellation point via I2C. * \param demod Pointer to demodulator instance. -* \param complexNr Pointer to the structure in which to store the +* \param complex_nr Pointer to the structure in which to store the constellation point. * \return int. */ static int -CtrlGetQAMConstel(pDRXDemodInstance_t demod, pDRXComplex_t complexNr) +ctrl_get_qam_constel(pdrx_demod_instance_t demod, pdrx_complex_t complex_nr) { - u16 fecOcOcrMode = 0; + u16 fec_oc_ocr_mode = 0; /**< FEC OCR grabber configuration */ - u16 qamSlCommMb = 0;/**< QAM SL MB configuration */ - u16 qamSlCommMbInit = 0; + u16 qam_sl_comm_mb = 0;/**< QAM SL MB configuration */ + u16 qam_sl_comm_mbInit = 0; /**< QAM SL MB intial configuration */ u16 im = 0; /**< constellation Im part */ u16 re = 0; /**< constellation Re part */ u32 data = 0; - struct i2c_device_addr *devAddr = NULL; + struct i2c_device_addr *dev_addr = NULL; /**< device address */ /* read device info */ - devAddr = demod->myI2CDevAddr; + dev_addr = demod->my_i2c_dev_addr; /* TODO: */ /* Monitor bus grabbing is an open external interface issue */ /* Needs to be checked when external interface PG is updated */ /* Configure MB (Monitor bus) */ - RR16(devAddr, QAM_SL_COMM_MB__A, &qamSlCommMbInit); + RR16(dev_addr, QAM_SL_COMM_MB__A, &qam_sl_comm_mbInit); /* set observe flag & MB mux */ - qamSlCommMb = qamSlCommMbInit & (~(QAM_SL_COMM_MB_OBS__M + + qam_sl_comm_mb = qam_sl_comm_mbInit & (~(QAM_SL_COMM_MB_OBS__M + QAM_SL_COMM_MB_MUX_OBS__M)); - qamSlCommMb |= (QAM_SL_COMM_MB_OBS_ON + + qam_sl_comm_mb |= (QAM_SL_COMM_MB_OBS_ON + QAM_SL_COMM_MB_MUX_OBS_CONST_CORR); - WR16(devAddr, QAM_SL_COMM_MB__A, qamSlCommMb); + WR16(dev_addr, QAM_SL_COMM_MB__A, qam_sl_comm_mb); /* Enable MB grabber in the FEC OC */ - fecOcOcrMode = (/* output select: observe bus */ + fec_oc_ocr_mode = (/* output select: observe bus */ (FEC_OC_OCR_MODE_MB_SELECT__M & (0x0 << FEC_OC_OCR_MODE_MB_SELECT__B)) | /* grabber enable: on */ @@ -8120,13 +8120,13 @@ CtrlGetQAMConstel(pDRXDemodInstance_t demod, pDRXComplex_t complexNr) /* grabber mode: continuous */ (FEC_OC_OCR_MODE_GRAB_COUNTED__M & (0x0 << FEC_OC_OCR_MODE_GRAB_COUNTED__B))); - WR16(devAddr, FEC_OC_OCR_MODE__A, fecOcOcrMode); + WR16(dev_addr, FEC_OC_OCR_MODE__A, fec_oc_ocr_mode); /* Disable MB grabber in the FEC OC */ - WR16(devAddr, FEC_OC_OCR_MODE__A, 0x00); + WR16(dev_addr, FEC_OC_OCR_MODE__A, 0x00); /* read data */ - RR32(devAddr, FEC_OC_OCR_GRAB_RD0__A, &data); + RR32(dev_addr, FEC_OC_OCR_GRAB_RD0__A, &data); re = (u16) (data & FEC_OC_OCR_GRAB_RD0__M); im = (u16) ((data >> 16) & FEC_OC_OCR_GRAB_RD1__M); @@ -8140,11 +8140,11 @@ CtrlGetQAMConstel(pDRXDemodInstance_t demod, pDRXComplex_t complexNr) if ((im & 0x0200) == 0x0200) { im |= 0xFC00; } - complexNr->re = ((s16) re); - complexNr->im = ((s16) im); + complex_nr->re = ((s16) re); + complex_nr->im = ((s16) im); /* Restore MB (Monitor bus) */ - WR16(devAddr, QAM_SL_COMM_MB__A, qamSlCommMbInit); + WR16(dev_addr, QAM_SL_COMM_MB__A, qam_sl_comm_mbInit); return (DRX_STS_OK); rw_error: @@ -8199,7 +8199,7 @@ rw_error: will reset most of these settings. To avoid that the end user apllication has to perform these settings each time the ATV or FM standards is selected the driver will shadow these settings. This enables the end user - to perform the settings only once after a DRX_Open(). The driver must + to perform the settings only once after a drx_open(). The driver must write the shadow settings to HW/SCU incase: ( setstandard FM/ATV) || ( settings have changed && FM/ATV standard is active) @@ -8219,13 +8219,13 @@ rw_error: /* -------------------------------------------------------------------------- */ /** -* \brief Get array index for atv coef (extAttr->atvTopCoefX[index]) +* \brief Get array index for atv coef (ext_attr->atvTopCoefX[index]) * \param standard * \param pointer to index * \return int. * */ -static int AtvEquCoefIndex(enum drx_standard standard, int *index) +static int atv_equ_coef_index(enum drx_standard standard, int *index) { switch (standard) { case DRX_STANDARD_PAL_SECAM_BG: @@ -8260,66 +8260,66 @@ static int AtvEquCoefIndex(enum drx_standard standard, int *index) /* -------------------------------------------------------------------------- */ /** -* \fn int AtvUpdateConfig () +* \fn int atv_update_config () * \brief Flush changes in ATV shadow registers to physical registers. * \param demod instance of demodulator -* \param forceUpdate don't look at standard or change flags, flush all. +* \param force_update don't look at standard or change flags, flush all. * \return int. * */ static int -AtvUpdateConfig(pDRXDemodInstance_t demod, bool forceUpdate) +atv_update_config(pdrx_demod_instance_t demod, bool force_update) { - struct i2c_device_addr *devAddr = NULL; - pDRXJData_t extAttr = NULL; + struct i2c_device_addr *dev_addr = NULL; + pdrxj_data_t ext_attr = NULL; - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* equalizer coefficients */ - if (forceUpdate || - ((extAttr->atvCfgChangedFlags & DRXJ_ATV_CHANGED_COEF) != 0)) { + if (force_update || + ((ext_attr->atv_cfg_changed_flags & DRXJ_ATV_CHANGED_COEF) != 0)) { int index = 0; - CHK_ERROR(AtvEquCoefIndex(extAttr->standard, &index)); - WR16(devAddr, ATV_TOP_EQU0__A, extAttr->atvTopEqu0[index]); - WR16(devAddr, ATV_TOP_EQU1__A, extAttr->atvTopEqu1[index]); - WR16(devAddr, ATV_TOP_EQU2__A, extAttr->atvTopEqu2[index]); - WR16(devAddr, ATV_TOP_EQU3__A, extAttr->atvTopEqu3[index]); + CHK_ERROR(atv_equ_coef_index(ext_attr->standard, &index)); + WR16(dev_addr, ATV_TOP_EQU0__A, ext_attr->atv_top_equ0[index]); + WR16(dev_addr, ATV_TOP_EQU1__A, ext_attr->atv_top_equ1[index]); + WR16(dev_addr, ATV_TOP_EQU2__A, ext_attr->atv_top_equ2[index]); + WR16(dev_addr, ATV_TOP_EQU3__A, ext_attr->atv_top_equ3[index]); } /* bypass fast carrier recovery */ - if (forceUpdate) { + if (force_update) { u16 data = 0; - RR16(devAddr, IQM_RT_ROT_BP__A, &data); + RR16(dev_addr, IQM_RT_ROT_BP__A, &data); data &= (~((u16) IQM_RT_ROT_BP_ROT_OFF__M)); - if (extAttr->phaseCorrectionBypass) { + if (ext_attr->phase_correction_bypass) { data |= IQM_RT_ROT_BP_ROT_OFF_OFF; } else { data |= IQM_RT_ROT_BP_ROT_OFF_ACTIVE; } - WR16(devAddr, IQM_RT_ROT_BP__A, data); + WR16(dev_addr, IQM_RT_ROT_BP__A, data); } /* peak filter setting */ - if (forceUpdate || - ((extAttr->atvCfgChangedFlags & DRXJ_ATV_CHANGED_PEAK_FLT) != 0)) { - WR16(devAddr, ATV_TOP_VID_PEAK__A, extAttr->atvTopVidPeak); + if (force_update || + ((ext_attr->atv_cfg_changed_flags & DRXJ_ATV_CHANGED_PEAK_FLT) != 0)) { + WR16(dev_addr, ATV_TOP_VID_PEAK__A, ext_attr->atv_top_vid_peak); } /* noise filter setting */ - if (forceUpdate || - ((extAttr->atvCfgChangedFlags & DRXJ_ATV_CHANGED_NOISE_FLT) != 0)) { - WR16(devAddr, ATV_TOP_NOISE_TH__A, extAttr->atvTopNoiseTh); + if (force_update || + ((ext_attr->atv_cfg_changed_flags & DRXJ_ATV_CHANGED_NOISE_FLT) != 0)) { + WR16(dev_addr, ATV_TOP_NOISE_TH__A, ext_attr->atv_top_noise_th); } /* SIF attenuation */ - if (forceUpdate || - ((extAttr->atvCfgChangedFlags & DRXJ_ATV_CHANGED_SIF_ATT) != 0)) { + if (force_update || + ((ext_attr->atv_cfg_changed_flags & DRXJ_ATV_CHANGED_SIF_ATT) != 0)) { u16 attenuation = 0; - switch (extAttr->sifAttenuation) { + switch (ext_attr->sif_attenuation) { case DRXJ_SIF_ATTENUATION_0DB: attenuation = ATV_TOP_AF_SIF_ATT_0DB; break; @@ -8336,30 +8336,30 @@ AtvUpdateConfig(pDRXDemodInstance_t demod, bool forceUpdate) return DRX_STS_ERROR; break; } - WR16(devAddr, ATV_TOP_AF_SIF_ATT__A, attenuation); + WR16(dev_addr, ATV_TOP_AF_SIF_ATT__A, attenuation); } /* SIF & CVBS enable */ - if (forceUpdate || - ((extAttr->atvCfgChangedFlags & DRXJ_ATV_CHANGED_OUTPUT) != 0)) { + if (force_update || + ((ext_attr->atv_cfg_changed_flags & DRXJ_ATV_CHANGED_OUTPUT) != 0)) { u16 data = 0; - RR16(devAddr, ATV_TOP_STDBY__A, &data); - if (extAttr->enableCVBSOutput) { + RR16(dev_addr, ATV_TOP_STDBY__A, &data); + if (ext_attr->enable_cvbs_output) { data |= ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE; } else { data &= (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE); } - if (extAttr->enableSIFOutput) { + if (ext_attr->enable_sif_output) { data &= (~ATV_TOP_STDBY_SIF_STDBY_STANDBY); } else { data |= ATV_TOP_STDBY_SIF_STDBY_STANDBY; } - WR16(devAddr, ATV_TOP_STDBY__A, data); + WR16(dev_addr, ATV_TOP_STDBY__A, data); } - extAttr->atvCfgChangedFlags = 0; + ext_attr->atv_cfg_changed_flags = 0; return (DRX_STS_OK); rw_error: @@ -8368,26 +8368,26 @@ rw_error: /* -------------------------------------------------------------------------- */ /** -* \fn int CtrlSetCfgATVOutput() +* \fn int ctrl_set_cfg_atv_output() * \brief Configure ATV ouputs * \param demod instance of demodulator -* \param outputCfg output configuaration +* \param output_cfg output configuaration * \return int. * */ static int -CtrlSetCfgATVOutput(pDRXDemodInstance_t demod, pDRXJCfgAtvOutput_t outputCfg) +ctrl_set_cfg_atv_output(pdrx_demod_instance_t demod, p_drxj_cfg_atv_output_t output_cfg) { - pDRXJData_t extAttr = NULL; + pdrxj_data_t ext_attr = NULL; /* Check arguments */ - if (outputCfg == NULL) { + if (output_cfg == NULL) { return (DRX_STS_INVALID_ARG); } - extAttr = (pDRXJData_t) demod->myExtAttr; - if (outputCfg->enableSIFOutput) { - switch (outputCfg->sifAttenuation) { + ext_attr = (pdrxj_data_t) demod->my_ext_attr; + if (output_cfg->enable_sif_output) { + switch (output_cfg->sif_attenuation) { case DRXJ_SIF_ATTENUATION_0DB: /* fallthrough */ case DRXJ_SIF_ATTENUATION_3DB: /* fallthrough */ case DRXJ_SIF_ATTENUATION_6DB: /* fallthrough */ @@ -8399,23 +8399,23 @@ CtrlSetCfgATVOutput(pDRXDemodInstance_t demod, pDRXJCfgAtvOutput_t outputCfg) break; } - if (extAttr->sifAttenuation != outputCfg->sifAttenuation) { - extAttr->sifAttenuation = outputCfg->sifAttenuation; - extAttr->atvCfgChangedFlags |= DRXJ_ATV_CHANGED_SIF_ATT; + if (ext_attr->sif_attenuation != output_cfg->sif_attenuation) { + ext_attr->sif_attenuation = output_cfg->sif_attenuation; + ext_attr->atv_cfg_changed_flags |= DRXJ_ATV_CHANGED_SIF_ATT; } } - if (extAttr->enableCVBSOutput != outputCfg->enableCVBSOutput) { - extAttr->enableCVBSOutput = outputCfg->enableCVBSOutput; - extAttr->atvCfgChangedFlags |= DRXJ_ATV_CHANGED_OUTPUT; + if (ext_attr->enable_cvbs_output != output_cfg->enable_cvbs_output) { + ext_attr->enable_cvbs_output = output_cfg->enable_cvbs_output; + ext_attr->atv_cfg_changed_flags |= DRXJ_ATV_CHANGED_OUTPUT; } - if (extAttr->enableSIFOutput != outputCfg->enableSIFOutput) { - extAttr->enableSIFOutput = outputCfg->enableSIFOutput; - extAttr->atvCfgChangedFlags |= DRXJ_ATV_CHANGED_OUTPUT; + if (ext_attr->enable_sif_output != output_cfg->enable_sif_output) { + ext_attr->enable_sif_output = output_cfg->enable_sif_output; + ext_attr->atv_cfg_changed_flags |= DRXJ_ATV_CHANGED_OUTPUT; } - CHK_ERROR(AtvUpdateConfig(demod, false)); + CHK_ERROR(atv_update_config(demod, false)); return (DRX_STS_OK); rw_error: @@ -8425,7 +8425,7 @@ rw_error: /* -------------------------------------------------------------------------- */ #ifndef DRXJ_DIGITAL_ONLY /** -* \fn int CtrlSetCfgAtvEquCoef() +* \fn int ctrl_set_cfg_atv_equ_coef() * \brief Set ATV equalizer coefficients * \param demod instance of demodulator * \param coef the equalizer coefficients @@ -8433,15 +8433,15 @@ rw_error: * */ static int -CtrlSetCfgAtvEquCoef(pDRXDemodInstance_t demod, pDRXJCfgAtvEquCoef_t coef) +ctrl_set_cfg_atv_equ_coef(pdrx_demod_instance_t demod, p_drxj_cfg_atv_equ_coef_t coef) { - pDRXJData_t extAttr = NULL; + pdrxj_data_t ext_attr = NULL; int index; - extAttr = (pDRXJData_t) demod->myExtAttr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* current standard needs to be an ATV standard */ - if (!DRXJ_ISATVSTD(extAttr->standard)) { + if (!DRXJ_ISATVSTD(ext_attr->standard)) { return DRX_STS_ERROR; } @@ -8458,14 +8458,14 @@ CtrlSetCfgAtvEquCoef(pDRXDemodInstance_t demod, pDRXJCfgAtvEquCoef_t coef) return (DRX_STS_INVALID_ARG); } - CHK_ERROR(AtvEquCoefIndex(extAttr->standard, &index)); - extAttr->atvTopEqu0[index] = coef->coef0; - extAttr->atvTopEqu1[index] = coef->coef1; - extAttr->atvTopEqu2[index] = coef->coef2; - extAttr->atvTopEqu3[index] = coef->coef3; - extAttr->atvCfgChangedFlags |= DRXJ_ATV_CHANGED_COEF; + CHK_ERROR(atv_equ_coef_index(ext_attr->standard, &index)); + ext_attr->atv_top_equ0[index] = coef->coef0; + ext_attr->atv_top_equ1[index] = coef->coef1; + ext_attr->atv_top_equ2[index] = coef->coef2; + ext_attr->atv_top_equ3[index] = coef->coef3; + ext_attr->atv_cfg_changed_flags |= DRXJ_ATV_CHANGED_COEF; - CHK_ERROR(AtvUpdateConfig(demod, false)); + CHK_ERROR(atv_update_config(demod, false)); return (DRX_STS_OK); rw_error: @@ -8474,7 +8474,7 @@ rw_error: /* -------------------------------------------------------------------------- */ /** -* \fn int CtrlGetCfgAtvEquCoef() +* \fn int ctrl_get_cfg_atv_equ_coef() * \brief Get ATV equ coef settings * \param demod instance of demodulator * \param coef The ATV equ coefficients @@ -8487,15 +8487,15 @@ rw_error: * */ static int -CtrlGetCfgAtvEquCoef(pDRXDemodInstance_t demod, pDRXJCfgAtvEquCoef_t coef) +ctrl_get_cfg_atv_equ_coef(pdrx_demod_instance_t demod, p_drxj_cfg_atv_equ_coef_t coef) { - pDRXJData_t extAttr = NULL; + pdrxj_data_t ext_attr = NULL; int index = 0; - extAttr = (pDRXJData_t) demod->myExtAttr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* current standard needs to be an ATV standard */ - if (!DRXJ_ISATVSTD(extAttr->standard)) { + if (!DRXJ_ISATVSTD(ext_attr->standard)) { return DRX_STS_ERROR; } @@ -8504,11 +8504,11 @@ CtrlGetCfgAtvEquCoef(pDRXDemodInstance_t demod, pDRXJCfgAtvEquCoef_t coef) return DRX_STS_INVALID_ARG; } - CHK_ERROR(AtvEquCoefIndex(extAttr->standard, &index)); - coef->coef0 = extAttr->atvTopEqu0[index]; - coef->coef1 = extAttr->atvTopEqu1[index]; - coef->coef2 = extAttr->atvTopEqu2[index]; - coef->coef3 = extAttr->atvTopEqu3[index]; + CHK_ERROR(atv_equ_coef_index(ext_attr->standard, &index)); + coef->coef0 = ext_attr->atv_top_equ0[index]; + coef->coef1 = ext_attr->atv_top_equ1[index]; + coef->coef2 = ext_attr->atv_top_equ2[index]; + coef->coef3 = ext_attr->atv_top_equ3[index]; return (DRX_STS_OK); rw_error: @@ -8517,7 +8517,7 @@ rw_error: /* -------------------------------------------------------------------------- */ /** -* \fn int CtrlSetCfgAtvMisc() +* \fn int ctrl_set_cfg_atv_misc() * \brief Set misc. settings for ATV. * \param demod instance of demodulator * \param @@ -8525,31 +8525,31 @@ rw_error: * */ static int -CtrlSetCfgAtvMisc(pDRXDemodInstance_t demod, pDRXJCfgAtvMisc_t settings) +ctrl_set_cfg_atv_misc(pdrx_demod_instance_t demod, p_drxj_cfg_atv_misc_t settings) { - pDRXJData_t extAttr = NULL; + pdrxj_data_t ext_attr = NULL; /* Check arguments */ if ((settings == NULL) || - ((settings->peakFilter) < (s16) (-8)) || - ((settings->peakFilter) > (s16) (15)) || - ((settings->noiseFilter) > 15)) { + ((settings->peak_filter) < (s16) (-8)) || + ((settings->peak_filter) > (s16) (15)) || + ((settings->noise_filter) > 15)) { return (DRX_STS_INVALID_ARG); } /* if */ - extAttr = (pDRXJData_t) demod->myExtAttr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; - if (settings->peakFilter != extAttr->atvTopVidPeak) { - extAttr->atvTopVidPeak = settings->peakFilter; - extAttr->atvCfgChangedFlags |= DRXJ_ATV_CHANGED_PEAK_FLT; + if (settings->peak_filter != ext_attr->atv_top_vid_peak) { + ext_attr->atv_top_vid_peak = settings->peak_filter; + ext_attr->atv_cfg_changed_flags |= DRXJ_ATV_CHANGED_PEAK_FLT; } - if (settings->noiseFilter != extAttr->atvTopNoiseTh) { - extAttr->atvTopNoiseTh = settings->noiseFilter; - extAttr->atvCfgChangedFlags |= DRXJ_ATV_CHANGED_NOISE_FLT; + if (settings->noise_filter != ext_attr->atv_top_noise_th) { + ext_attr->atv_top_noise_th = settings->noise_filter; + ext_attr->atv_cfg_changed_flags |= DRXJ_ATV_CHANGED_NOISE_FLT; } - CHK_ERROR(AtvUpdateConfig(demod, false)); + CHK_ERROR(atv_update_config(demod, false)); return (DRX_STS_OK); rw_error: @@ -8558,7 +8558,7 @@ rw_error: /* -------------------------------------------------------------------------- */ /** -* \fn int CtrlGetCfgAtvMisc() +* \fn int ctrl_get_cfg_atv_misc() * \brief Get misc settings of ATV. * \param demod instance of demodulator * \param settings misc. ATV settings @@ -8570,19 +8570,19 @@ rw_error: * regitsers. */ static int -CtrlGetCfgAtvMisc(pDRXDemodInstance_t demod, pDRXJCfgAtvMisc_t settings) +ctrl_get_cfg_atv_misc(pdrx_demod_instance_t demod, p_drxj_cfg_atv_misc_t settings) { - pDRXJData_t extAttr = NULL; + pdrxj_data_t ext_attr = NULL; /* Check arguments */ if (settings == NULL) { return DRX_STS_INVALID_ARG; } - extAttr = (pDRXJData_t) demod->myExtAttr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; - settings->peakFilter = extAttr->atvTopVidPeak; - settings->noiseFilter = extAttr->atvTopNoiseTh; + settings->peak_filter = ext_attr->atv_top_vid_peak; + settings->noise_filter = ext_attr->atv_top_noise_th; return (DRX_STS_OK); } @@ -8591,36 +8591,36 @@ CtrlGetCfgAtvMisc(pDRXDemodInstance_t demod, pDRXJCfgAtvMisc_t settings) /* -------------------------------------------------------------------------- */ /** -* \fn int CtrlGetCfgAtvOutput() +* \fn int ctrl_get_cfg_atv_output() * \brief * \param demod instance of demodulator -* \param outputCfg output configuaration +* \param output_cfg output configuaration * \return int. * */ static int -CtrlGetCfgAtvOutput(pDRXDemodInstance_t demod, pDRXJCfgAtvOutput_t outputCfg) +ctrl_get_cfg_atv_output(pdrx_demod_instance_t demod, p_drxj_cfg_atv_output_t output_cfg) { u16 data = 0; /* Check arguments */ - if (outputCfg == NULL) { + if (output_cfg == NULL) { return DRX_STS_INVALID_ARG; } - RR16(demod->myI2CDevAddr, ATV_TOP_STDBY__A, &data); + RR16(demod->my_i2c_dev_addr, ATV_TOP_STDBY__A, &data); if (data & ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE) { - outputCfg->enableCVBSOutput = true; + output_cfg->enable_cvbs_output = true; } else { - outputCfg->enableCVBSOutput = false; + output_cfg->enable_cvbs_output = false; } if (data & ATV_TOP_STDBY_SIF_STDBY_STANDBY) { - outputCfg->enableSIFOutput = false; + output_cfg->enable_sif_output = false; } else { - outputCfg->enableSIFOutput = true; - RR16(demod->myI2CDevAddr, ATV_TOP_AF_SIF_ATT__A, &data); - outputCfg->sifAttenuation = (DRXJSIFAttenuation_t) data; + output_cfg->enable_sif_output = true; + RR16(demod->my_i2c_dev_addr, ATV_TOP_AF_SIF_ATT__A, &data); + output_cfg->sif_attenuation = (drxjsif_attenuation_t) data; } return (DRX_STS_OK); @@ -8630,29 +8630,29 @@ rw_error: /* -------------------------------------------------------------------------- */ /** -* \fn int CtrlGetCfgAtvAgcStatus() +* \fn int ctrl_get_cfg_atv_agc_status() * \brief * \param demod instance of demodulator -* \param agcStatus agc status +* \param agc_status agc status * \return int. * */ static int -CtrlGetCfgAtvAgcStatus(pDRXDemodInstance_t demod, - pDRXJCfgAtvAgcStatus_t agcStatus) +ctrl_get_cfg_atv_agc_status(pdrx_demod_instance_t demod, + p_drxj_cfg_atv_agc_status_t agc_status) { - struct i2c_device_addr *devAddr = NULL; - pDRXJData_t extAttr = NULL; + struct i2c_device_addr *dev_addr = NULL; + pdrxj_data_t ext_attr = NULL; u16 data = 0; u32 tmp = 0; /* Check arguments */ - if (agcStatus == NULL) { + if (agc_status == NULL) { return DRX_STS_INVALID_ARG; } - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* RFgain = (IQM_AF_AGC_RF__A * 26.75)/1000 (uA) @@ -8660,12 +8660,12 @@ CtrlGetCfgAtvAgcStatus(pDRXDemodInstance_t demod, IQM_AF_AGC_RF__A * 27 is 20 bits worst case. */ - RR16(devAddr, IQM_AF_AGC_RF__A, &data); + RR16(dev_addr, IQM_AF_AGC_RF__A, &data); tmp = ((u32) data) * 27 - ((u32) (data >> 2)); /* nA */ - agcStatus->rfAgcGain = (u16) (tmp / 1000); /* uA */ + agc_status->rf_agc_gain = (u16) (tmp / 1000); /* uA */ /* rounding */ if (tmp % 1000 >= 500) { - (agcStatus->rfAgcGain)++; + (agc_status->rf_agc_gain)++; } /* @@ -8674,12 +8674,12 @@ CtrlGetCfgAtvAgcStatus(pDRXDemodInstance_t demod, IQM_AF_AGC_IF__A * 27 is 20 bits worst case. */ - RR16(devAddr, IQM_AF_AGC_IF__A, &data); + RR16(dev_addr, IQM_AF_AGC_IF__A, &data); tmp = ((u32) data) * 27 - ((u32) (data >> 2)); /* nA */ - agcStatus->ifAgcGain = (u16) (tmp / 1000); /* uA */ + agc_status->if_agc_gain = (u16) (tmp / 1000); /* uA */ /* rounding */ if (tmp % 1000 >= 500) { - (agcStatus->ifAgcGain)++; + (agc_status->if_agc_gain)++; } /* @@ -8690,14 +8690,14 @@ CtrlGetCfgAtvAgcStatus(pDRXDemodInstance_t demod, = (ATV_TOP_SFR_VID_GAIN__A/32) - 75 (in 0.1 dB) */ - SARR16(devAddr, SCU_RAM_ATV_VID_GAIN_HI__A, &data); + SARR16(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, &data); /* dividing by 32 inclusive rounding */ data >>= 4; if ((data & 1) != 0) { data++; } data >>= 1; - agcStatus->videoAgcGain = ((s16) data) - 75; /* 0.1 dB */ + agc_status->video_agc_gain = ((s16) data) - 75; /* 0.1 dB */ /* audioGain = (SCU_RAM_ATV_SIF_GAIN__A -8)* 0.05 (dB) @@ -8707,22 +8707,22 @@ CtrlGetCfgAtvAgcStatus(pDRXDemodInstance_t demod, = (SCU_RAM_ATV_SIF_GAIN__A/2) - 4 (in 0.1 dB) */ - SARR16(devAddr, SCU_RAM_ATV_SIF_GAIN__A, &data); + SARR16(dev_addr, SCU_RAM_ATV_SIF_GAIN__A, &data); data &= SCU_RAM_ATV_SIF_GAIN__M; /* dividing by 2 inclusive rounding */ if ((data & 1) != 0) { data++; } data >>= 1; - agcStatus->audioAgcGain = ((s16) data) - 4; /* 0.1 dB */ + agc_status->audio_agc_gain = ((s16) data) - 4; /* 0.1 dB */ /* Loop gain's */ - SARR16(devAddr, SCU_RAM_AGC_KI__A, &data); - agcStatus->videoAgcLoopGain = + SARR16(dev_addr, SCU_RAM_AGC_KI__A, &data); + agc_status->video_agc_loop_gain = ((data & SCU_RAM_AGC_KI_DGAIN__M) >> SCU_RAM_AGC_KI_DGAIN__B); - agcStatus->rfAgcLoopGain = + agc_status->rf_agc_loop_gain = ((data & SCU_RAM_AGC_KI_RF__M) >> SCU_RAM_AGC_KI_RF__B); - agcStatus->ifAgcLoopGain = + agc_status->if_agc_loop_gain = ((data & SCU_RAM_AGC_KI_IF__M) >> SCU_RAM_AGC_KI_IF__B); return (DRX_STS_OK); @@ -8733,7 +8733,7 @@ rw_error: /* -------------------------------------------------------------------------- */ /** -* \fn int PowerUpATV () +* \fn int power_up_atv () * \brief Power up ATV. * \param demod instance of demodulator * \param standard either NTSC or FM (sub strandard for ATV ) @@ -8742,21 +8742,21 @@ rw_error: * * Starts ATV and IQM * * AUdio already started during standard init for ATV. */ -static int PowerUpATV(pDRXDemodInstance_t demod, enum drx_standard standard) +static int power_up_atv(pdrx_demod_instance_t demod, enum drx_standard standard) { - struct i2c_device_addr *devAddr = NULL; - pDRXJData_t extAttr = NULL; + struct i2c_device_addr *dev_addr = NULL; + pdrxj_data_t ext_attr = NULL; - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* ATV NTSC */ - WR16(devAddr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_ACTIVE); + WR16(dev_addr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_ACTIVE); /* turn on IQM_AF */ - CHK_ERROR(SetIqmAf(demod, true)); - CHK_ERROR(ADCSynchronization(demod)); + CHK_ERROR(set_iqm_af(demod, true)); + CHK_ERROR(adc_synchronization(demod)); - WR16(devAddr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE); + WR16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE); /* Audio, already done during set standard */ @@ -8769,7 +8769,7 @@ rw_error: /* -------------------------------------------------------------------------- */ /** -* \fn int PowerDownATV () +* \fn int power_down_atv () * \brief Power down ATV. * \param demod instance of demodulator * \param standard either NTSC or FM (sub strandard for ATV ) @@ -8780,46 +8780,46 @@ rw_error: * Calls audio power down */ static int -PowerDownATV(pDRXDemodInstance_t demod, enum drx_standard standard, bool primary) +power_down_atv(pdrx_demod_instance_t demod, enum drx_standard standard, bool primary) { - struct i2c_device_addr *devAddr = NULL; - DRXJSCUCmd_t cmdSCU = { /* command */ 0, - /* parameterLen */ 0, - /* resultLen */ 0, + struct i2c_device_addr *dev_addr = NULL; + drxjscu_cmd_t cmd_scu = { /* command */ 0, + /* parameter_len */ 0, + /* result_len */ 0, /* *parameter */ NULL, /* *result */ NULL }; - u16 cmdResult = 0; - pDRXJData_t extAttr = NULL; + u16 cmd_result = 0; + pdrxj_data_t ext_attr = NULL; - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* ATV NTSC */ /* Stop ATV SCU (will reset ATV and IQM hardware */ - cmdSCU.command = SCU_RAM_COMMAND_STANDARD_ATV | + cmd_scu.command = SCU_RAM_COMMAND_STANDARD_ATV | SCU_RAM_COMMAND_CMD_DEMOD_STOP; - cmdSCU.parameterLen = 0; - cmdSCU.resultLen = 1; - cmdSCU.parameter = NULL; - cmdSCU.result = &cmdResult; - CHK_ERROR(SCUCommand(devAddr, &cmdSCU)); + cmd_scu.parameter_len = 0; + cmd_scu.result_len = 1; + cmd_scu.parameter = NULL; + cmd_scu.result = &cmd_result; + CHK_ERROR(scu_command(dev_addr, &cmd_scu)); /* Disable ATV outputs (ATV reset enables CVBS, undo this) */ - WR16(devAddr, ATV_TOP_STDBY__A, (ATV_TOP_STDBY_SIF_STDBY_STANDBY & + WR16(dev_addr, ATV_TOP_STDBY__A, (ATV_TOP_STDBY_SIF_STDBY_STANDBY & (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE))); - WR16(devAddr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_STOP); + WR16(dev_addr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_STOP); if (primary == true) { - WR16(devAddr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP); - CHK_ERROR(SetIqmAf(demod, false)); + WR16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP); + CHK_ERROR(set_iqm_af(demod, false)); } else { - WR16(devAddr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP); - WR16(devAddr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP); - WR16(devAddr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP); - WR16(devAddr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP); - WR16(devAddr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP); + WR16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP); + WR16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP); + WR16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP); + WR16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP); + WR16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP); } - CHK_ERROR(PowerDownAud(demod)); + CHK_ERROR(power_down_aud(demod)); return (DRX_STS_OK); rw_error: @@ -8828,7 +8828,7 @@ rw_error: /* -------------------------------------------------------------------------- */ /** -* \fn int SetATVStandard () +* \fn int set_atv_standard () * \brief Set up ATV demodulator. * \param demod instance of demodulator * \param standard either NTSC or FM (sub strandard for ATV ) @@ -8841,7 +8841,7 @@ rw_error: #ifndef DRXJ_DIGITAL_ONLY #define SCU_RAM_ATV_ENABLE_IIR_WA__A 0x831F6D /* TODO remove after done with reg import */ static int -SetATVStandard(pDRXDemodInstance_t demod, enum drx_standard *standard) +set_atv_standard(pdrx_demod_instance_t demod, enum drx_standard *standard) { /* TODO: enable alternative for tap settings via external file @@ -9100,338 +9100,338 @@ trouble ? DRXJ_16TO8(70) /* im27 */ }; - struct i2c_device_addr *devAddr = NULL; - DRXJSCUCmd_t cmdSCU = { /* command */ 0, - /* parameterLen */ 0, - /* resultLen */ 0, + struct i2c_device_addr *dev_addr = NULL; + drxjscu_cmd_t cmd_scu = { /* command */ 0, + /* parameter_len */ 0, + /* result_len */ 0, /* *parameter */ NULL, /* *result */ NULL }; - u16 cmdResult = 0; - u16 cmdParam = 0; + u16 cmd_result = 0; + u16 cmd_param = 0; #ifdef DRXJ_SPLIT_UCODE_UPLOAD - DRXUCodeInfo_t ucodeInfo; - pDRXCommonAttr_t commonAttr = NULL; + drxu_code_info_t ucode_info; + pdrx_common_attr_t common_attr = NULL; #endif /* DRXJ_SPLIT_UCODE_UPLOAD */ - pDRXJData_t extAttr = NULL; + pdrxj_data_t ext_attr = NULL; - extAttr = (pDRXJData_t) demod->myExtAttr; - devAddr = demod->myI2CDevAddr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; + dev_addr = demod->my_i2c_dev_addr; #ifdef DRXJ_SPLIT_UCODE_UPLOAD - commonAttr = demod->myCommonAttr; + common_attr = demod->my_common_attr; /* Check if audio microcode is already uploaded */ - if (!(extAttr->flagAudMcUploaded)) { - ucodeInfo.mcData = commonAttr->microcode; - ucodeInfo.mcSize = commonAttr->microcodeSize; + if (!(ext_attr->flag_aud_mc_uploaded)) { + ucode_info.mc_data = common_attr->microcode; + ucode_info.mc_size = common_attr->microcode_size; /* Upload only audio microcode */ - CHK_ERROR(CtrlUCodeUpload - (demod, &ucodeInfo, UCODE_UPLOAD, true)); + CHK_ERROR(ctrl_u_codeUpload + (demod, &ucode_info, UCODE_UPLOAD, true)); - if (commonAttr->verifyMicrocode == true) { - CHK_ERROR(CtrlUCodeUpload - (demod, &ucodeInfo, UCODE_VERIFY, true)); + if (common_attr->verify_microcode == true) { + CHK_ERROR(ctrl_u_codeUpload + (demod, &ucode_info, UCODE_VERIFY, true)); } /* Prevent uploading audio microcode again */ - extAttr->flagAudMcUploaded = true; + ext_attr->flag_aud_mc_uploaded = true; } #endif /* DRXJ_SPLIT_UCODE_UPLOAD */ - WR16(devAddr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_STOP); - WR16(devAddr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP); - WR16(devAddr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP); - WR16(devAddr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP); - WR16(devAddr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP); - WR16(devAddr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP); + WR16(dev_addr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_STOP); + WR16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP); + WR16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP); + WR16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP); + WR16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP); + WR16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP); /* Reset ATV SCU */ - cmdSCU.command = SCU_RAM_COMMAND_STANDARD_ATV | + cmd_scu.command = SCU_RAM_COMMAND_STANDARD_ATV | SCU_RAM_COMMAND_CMD_DEMOD_RESET; - cmdSCU.parameterLen = 0; - cmdSCU.resultLen = 1; - cmdSCU.parameter = NULL; - cmdSCU.result = &cmdResult; - CHK_ERROR(SCUCommand(devAddr, &cmdSCU)); + cmd_scu.parameter_len = 0; + cmd_scu.result_len = 1; + cmd_scu.parameter = NULL; + cmd_scu.result = &cmd_result; + CHK_ERROR(scu_command(dev_addr, &cmd_scu)); - WR16(devAddr, ATV_TOP_MOD_CONTROL__A, ATV_TOP_MOD_CONTROL__PRE); + WR16(dev_addr, ATV_TOP_MOD_CONTROL__A, ATV_TOP_MOD_CONTROL__PRE); /* TODO remove AUTO/OFF patches after ucode fix. */ switch (*standard) { case DRX_STANDARD_NTSC: /* NTSC */ - cmdParam = SCU_RAM_ATV_STANDARD_STANDARD_MN; + cmd_param = SCU_RAM_ATV_STANDARD_STANDARD_MN; - WR16(devAddr, IQM_RT_LO_INCR__A, IQM_RT_LO_INCR_MN); - WR16(devAddr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M); - WRB(devAddr, IQM_CF_TAP_RE0__A, sizeof(ntsc_taps_re), + WR16(dev_addr, IQM_RT_LO_INCR__A, IQM_RT_LO_INCR_MN); + WR16(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M); + WRB(dev_addr, IQM_CF_TAP_RE0__A, sizeof(ntsc_taps_re), ((u8 *) ntsc_taps_re)); - WRB(devAddr, IQM_CF_TAP_IM0__A, sizeof(ntsc_taps_im), + WRB(dev_addr, IQM_CF_TAP_IM0__A, sizeof(ntsc_taps_im), ((u8 *) ntsc_taps_im)); - WR16(devAddr, ATV_TOP_CR_AMP_TH__A, ATV_TOP_CR_AMP_TH_MN); - WR16(devAddr, ATV_TOP_CR_CONT__A, + WR16(dev_addr, ATV_TOP_CR_AMP_TH__A, ATV_TOP_CR_AMP_TH_MN); + WR16(dev_addr, ATV_TOP_CR_CONT__A, (ATV_TOP_CR_CONT_CR_P_MN | ATV_TOP_CR_CONT_CR_D_MN | ATV_TOP_CR_CONT_CR_I_MN)); - WR16(devAddr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_MN); - WR16(devAddr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_MN | + WR16(dev_addr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_MN); + WR16(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_MN | ATV_TOP_STD_VID_POL_MN)); - WR16(devAddr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_MN); + WR16(dev_addr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_MN); - WR16(devAddr, SCU_RAM_ATV_AGC_MODE__A, + WR16(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM | SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE)); - WR16(devAddr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000); - WR16(devAddr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000); - WR16(devAddr, SCU_RAM_ATV_AMS_MAX_REF__A, + WR16(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000); + WR16(dev_addr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000); + WR16(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_BG_MN); - extAttr->phaseCorrectionBypass = false; - extAttr->enableCVBSOutput = true; + ext_attr->phase_correction_bypass = false; + ext_attr->enable_cvbs_output = true; break; case DRX_STANDARD_FM: /* FM */ - cmdParam = SCU_RAM_ATV_STANDARD_STANDARD_FM; + cmd_param = SCU_RAM_ATV_STANDARD_STANDARD_FM; - WR16(devAddr, IQM_RT_LO_INCR__A, 2994); - WR16(devAddr, IQM_CF_MIDTAP__A, 0); - WRB(devAddr, IQM_CF_TAP_RE0__A, sizeof(fm_taps_re), + WR16(dev_addr, IQM_RT_LO_INCR__A, 2994); + WR16(dev_addr, IQM_CF_MIDTAP__A, 0); + WRB(dev_addr, IQM_CF_TAP_RE0__A, sizeof(fm_taps_re), ((u8 *) fm_taps_re)); - WRB(devAddr, IQM_CF_TAP_IM0__A, sizeof(fm_taps_im), + WRB(dev_addr, IQM_CF_TAP_IM0__A, sizeof(fm_taps_im), ((u8 *) fm_taps_im)); - WR16(devAddr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_FM | + WR16(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_FM | ATV_TOP_STD_VID_POL_FM)); - WR16(devAddr, ATV_TOP_MOD_CONTROL__A, 0); - WR16(devAddr, ATV_TOP_CR_CONT__A, 0); + WR16(dev_addr, ATV_TOP_MOD_CONTROL__A, 0); + WR16(dev_addr, ATV_TOP_CR_CONT__A, 0); - WR16(devAddr, SCU_RAM_ATV_AGC_MODE__A, + WR16(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW | SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM)); - WR16(devAddr, IQM_RT_ROT_BP__A, IQM_RT_ROT_BP_ROT_OFF_OFF); - extAttr->phaseCorrectionBypass = true; - extAttr->enableCVBSOutput = false; + WR16(dev_addr, IQM_RT_ROT_BP__A, IQM_RT_ROT_BP_ROT_OFF_OFF); + ext_attr->phase_correction_bypass = true; + ext_attr->enable_cvbs_output = false; break; case DRX_STANDARD_PAL_SECAM_BG: /* PAL/SECAM B/G */ - cmdParam = SCU_RAM_ATV_STANDARD_STANDARD_B; + cmd_param = SCU_RAM_ATV_STANDARD_STANDARD_B; - WR16(devAddr, IQM_RT_LO_INCR__A, 1820); /* TODO check with IS */ - WR16(devAddr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M); - WRB(devAddr, IQM_CF_TAP_RE0__A, sizeof(bg_taps_re), + WR16(dev_addr, IQM_RT_LO_INCR__A, 1820); /* TODO check with IS */ + WR16(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M); + WRB(dev_addr, IQM_CF_TAP_RE0__A, sizeof(bg_taps_re), ((u8 *) bg_taps_re)); - WRB(devAddr, IQM_CF_TAP_IM0__A, sizeof(bg_taps_im), + WRB(dev_addr, IQM_CF_TAP_IM0__A, sizeof(bg_taps_im), ((u8 *) bg_taps_im)); - WR16(devAddr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_BG); - WR16(devAddr, ATV_TOP_CR_AMP_TH__A, ATV_TOP_CR_AMP_TH_BG); - WR16(devAddr, ATV_TOP_CR_CONT__A, + WR16(dev_addr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_BG); + WR16(dev_addr, ATV_TOP_CR_AMP_TH__A, ATV_TOP_CR_AMP_TH_BG); + WR16(dev_addr, ATV_TOP_CR_CONT__A, (ATV_TOP_CR_CONT_CR_P_BG | ATV_TOP_CR_CONT_CR_D_BG | ATV_TOP_CR_CONT_CR_I_BG)); - WR16(devAddr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_BG); - WR16(devAddr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_BG | + WR16(dev_addr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_BG); + WR16(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_BG | ATV_TOP_STD_VID_POL_BG)); - WR16(devAddr, SCU_RAM_ATV_AGC_MODE__A, + WR16(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM | SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE)); - WR16(devAddr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000); - WR16(devAddr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000); - WR16(devAddr, SCU_RAM_ATV_AMS_MAX_REF__A, + WR16(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000); + WR16(dev_addr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000); + WR16(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_BG_MN); - extAttr->phaseCorrectionBypass = false; - extAttr->atvIfAgcCfg.ctrlMode = DRX_AGC_CTRL_AUTO; - extAttr->enableCVBSOutput = true; + ext_attr->phase_correction_bypass = false; + ext_attr->atv_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; + ext_attr->enable_cvbs_output = true; break; case DRX_STANDARD_PAL_SECAM_DK: /* PAL/SECAM D/K */ - cmdParam = SCU_RAM_ATV_STANDARD_STANDARD_DK; + cmd_param = SCU_RAM_ATV_STANDARD_STANDARD_DK; - WR16(devAddr, IQM_RT_LO_INCR__A, 2225); /* TODO check with IS */ - WR16(devAddr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M); - WRB(devAddr, IQM_CF_TAP_RE0__A, sizeof(dk_i_l_lp_taps_re), + WR16(dev_addr, IQM_RT_LO_INCR__A, 2225); /* TODO check with IS */ + WR16(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M); + WRB(dev_addr, IQM_CF_TAP_RE0__A, sizeof(dk_i_l_lp_taps_re), ((u8 *) dk_i_l_lp_taps_re)); - WRB(devAddr, IQM_CF_TAP_IM0__A, sizeof(dk_i_l_lp_taps_im), + WRB(dev_addr, IQM_CF_TAP_IM0__A, sizeof(dk_i_l_lp_taps_im), ((u8 *) dk_i_l_lp_taps_im)); - WR16(devAddr, ATV_TOP_CR_AMP_TH__A, ATV_TOP_CR_AMP_TH_DK); - WR16(devAddr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_DK); - WR16(devAddr, ATV_TOP_CR_CONT__A, + WR16(dev_addr, ATV_TOP_CR_AMP_TH__A, ATV_TOP_CR_AMP_TH_DK); + WR16(dev_addr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_DK); + WR16(dev_addr, ATV_TOP_CR_CONT__A, (ATV_TOP_CR_CONT_CR_P_DK | ATV_TOP_CR_CONT_CR_D_DK | ATV_TOP_CR_CONT_CR_I_DK)); - WR16(devAddr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_DK); - WR16(devAddr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_DK | + WR16(dev_addr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_DK); + WR16(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_DK | ATV_TOP_STD_VID_POL_DK)); - WR16(devAddr, SCU_RAM_ATV_AGC_MODE__A, + WR16(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM | SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE)); - WR16(devAddr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000); - WR16(devAddr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000); - WR16(devAddr, SCU_RAM_ATV_AMS_MAX_REF__A, + WR16(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000); + WR16(dev_addr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000); + WR16(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_DK); - extAttr->phaseCorrectionBypass = false; - extAttr->atvIfAgcCfg.ctrlMode = DRX_AGC_CTRL_AUTO; - extAttr->enableCVBSOutput = true; + ext_attr->phase_correction_bypass = false; + ext_attr->atv_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; + ext_attr->enable_cvbs_output = true; break; case DRX_STANDARD_PAL_SECAM_I: /* PAL/SECAM I */ - cmdParam = SCU_RAM_ATV_STANDARD_STANDARD_I; + cmd_param = SCU_RAM_ATV_STANDARD_STANDARD_I; - WR16(devAddr, IQM_RT_LO_INCR__A, 2225); /* TODO check with IS */ - WR16(devAddr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M); - WRB(devAddr, IQM_CF_TAP_RE0__A, sizeof(dk_i_l_lp_taps_re), + WR16(dev_addr, IQM_RT_LO_INCR__A, 2225); /* TODO check with IS */ + WR16(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M); + WRB(dev_addr, IQM_CF_TAP_RE0__A, sizeof(dk_i_l_lp_taps_re), ((u8 *) dk_i_l_lp_taps_re)); - WRB(devAddr, IQM_CF_TAP_IM0__A, sizeof(dk_i_l_lp_taps_im), + WRB(dev_addr, IQM_CF_TAP_IM0__A, sizeof(dk_i_l_lp_taps_im), ((u8 *) dk_i_l_lp_taps_im)); - WR16(devAddr, ATV_TOP_CR_AMP_TH__A, ATV_TOP_CR_AMP_TH_I); - WR16(devAddr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_I); - WR16(devAddr, ATV_TOP_CR_CONT__A, + WR16(dev_addr, ATV_TOP_CR_AMP_TH__A, ATV_TOP_CR_AMP_TH_I); + WR16(dev_addr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_I); + WR16(dev_addr, ATV_TOP_CR_CONT__A, (ATV_TOP_CR_CONT_CR_P_I | ATV_TOP_CR_CONT_CR_D_I | ATV_TOP_CR_CONT_CR_I_I)); - WR16(devAddr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_I); - WR16(devAddr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_I | + WR16(dev_addr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_I); + WR16(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_I | ATV_TOP_STD_VID_POL_I)); - WR16(devAddr, SCU_RAM_ATV_AGC_MODE__A, + WR16(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM | SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE)); - WR16(devAddr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000); - WR16(devAddr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000); - WR16(devAddr, SCU_RAM_ATV_AMS_MAX_REF__A, + WR16(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000); + WR16(dev_addr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000); + WR16(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_I); - extAttr->phaseCorrectionBypass = false; - extAttr->atvIfAgcCfg.ctrlMode = DRX_AGC_CTRL_AUTO; - extAttr->enableCVBSOutput = true; + ext_attr->phase_correction_bypass = false; + ext_attr->atv_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; + ext_attr->enable_cvbs_output = true; break; case DRX_STANDARD_PAL_SECAM_L: /* PAL/SECAM L with negative modulation */ - cmdParam = SCU_RAM_ATV_STANDARD_STANDARD_L; + cmd_param = SCU_RAM_ATV_STANDARD_STANDARD_L; - WR16(devAddr, IQM_RT_LO_INCR__A, 2225); /* TODO check with IS */ - WR16(devAddr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_L); - WR16(devAddr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M); - WRB(devAddr, IQM_CF_TAP_RE0__A, sizeof(dk_i_l_lp_taps_re), + WR16(dev_addr, IQM_RT_LO_INCR__A, 2225); /* TODO check with IS */ + WR16(dev_addr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_L); + WR16(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M); + WRB(dev_addr, IQM_CF_TAP_RE0__A, sizeof(dk_i_l_lp_taps_re), ((u8 *) dk_i_l_lp_taps_re)); - WRB(devAddr, IQM_CF_TAP_IM0__A, sizeof(dk_i_l_lp_taps_im), + WRB(dev_addr, IQM_CF_TAP_IM0__A, sizeof(dk_i_l_lp_taps_im), ((u8 *) dk_i_l_lp_taps_im)); - WR16(devAddr, ATV_TOP_CR_AMP_TH__A, 0x2); /* TODO check with IS */ - WR16(devAddr, ATV_TOP_CR_CONT__A, + WR16(dev_addr, ATV_TOP_CR_AMP_TH__A, 0x2); /* TODO check with IS */ + WR16(dev_addr, ATV_TOP_CR_CONT__A, (ATV_TOP_CR_CONT_CR_P_L | ATV_TOP_CR_CONT_CR_D_L | ATV_TOP_CR_CONT_CR_I_L)); - WR16(devAddr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_L); - WR16(devAddr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_L | + WR16(dev_addr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_L); + WR16(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_L | ATV_TOP_STD_VID_POL_L)); - WR16(devAddr, SCU_RAM_ATV_AGC_MODE__A, + WR16(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_AM | SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_ENABLE | SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW)); - WR16(devAddr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000); - WR16(devAddr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000); - WR16(devAddr, SCU_RAM_ATV_AMS_MAX_REF__A, + WR16(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000); + WR16(dev_addr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000); + WR16(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_LLP); - extAttr->phaseCorrectionBypass = false; - extAttr->atvIfAgcCfg.ctrlMode = DRX_AGC_CTRL_USER; - extAttr->atvIfAgcCfg.outputLevel = extAttr->atvRfAgcCfg.top; - extAttr->enableCVBSOutput = true; + ext_attr->phase_correction_bypass = false; + ext_attr->atv_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_USER; + ext_attr->atv_if_agc_cfg.output_level = ext_attr->atv_rf_agc_cfg.top; + ext_attr->enable_cvbs_output = true; break; case DRX_STANDARD_PAL_SECAM_LP: /* PAL/SECAM L with positive modulation */ - cmdParam = SCU_RAM_ATV_STANDARD_STANDARD_LP; + cmd_param = SCU_RAM_ATV_STANDARD_STANDARD_LP; - WR16(devAddr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_LP); - WR16(devAddr, IQM_RT_LO_INCR__A, 2225); /* TODO check with IS */ - WR16(devAddr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M); - WRB(devAddr, IQM_CF_TAP_RE0__A, sizeof(dk_i_l_lp_taps_re), + WR16(dev_addr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_LP); + WR16(dev_addr, IQM_RT_LO_INCR__A, 2225); /* TODO check with IS */ + WR16(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M); + WRB(dev_addr, IQM_CF_TAP_RE0__A, sizeof(dk_i_l_lp_taps_re), ((u8 *) dk_i_l_lp_taps_re)); - WRB(devAddr, IQM_CF_TAP_IM0__A, sizeof(dk_i_l_lp_taps_im), + WRB(dev_addr, IQM_CF_TAP_IM0__A, sizeof(dk_i_l_lp_taps_im), ((u8 *) dk_i_l_lp_taps_im)); - WR16(devAddr, ATV_TOP_CR_AMP_TH__A, 0x2); /* TODO check with IS */ - WR16(devAddr, ATV_TOP_CR_CONT__A, + WR16(dev_addr, ATV_TOP_CR_AMP_TH__A, 0x2); /* TODO check with IS */ + WR16(dev_addr, ATV_TOP_CR_CONT__A, (ATV_TOP_CR_CONT_CR_P_LP | ATV_TOP_CR_CONT_CR_D_LP | ATV_TOP_CR_CONT_CR_I_LP)); - WR16(devAddr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_LP); - WR16(devAddr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_LP | + WR16(dev_addr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_LP); + WR16(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_LP | ATV_TOP_STD_VID_POL_LP)); - WR16(devAddr, SCU_RAM_ATV_AGC_MODE__A, + WR16(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_AM | SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_ENABLE | SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW)); - WR16(devAddr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000); - WR16(devAddr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000); - WR16(devAddr, SCU_RAM_ATV_AMS_MAX_REF__A, + WR16(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000); + WR16(dev_addr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000); + WR16(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_LLP); - extAttr->phaseCorrectionBypass = false; - extAttr->atvIfAgcCfg.ctrlMode = DRX_AGC_CTRL_USER; - extAttr->atvIfAgcCfg.outputLevel = extAttr->atvRfAgcCfg.top; - extAttr->enableCVBSOutput = true; + ext_attr->phase_correction_bypass = false; + ext_attr->atv_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_USER; + ext_attr->atv_if_agc_cfg.output_level = ext_attr->atv_rf_agc_cfg.top; + ext_attr->enable_cvbs_output = true; break; default: return (DRX_STS_ERROR); } /* Common initializations FM & NTSC & B/G & D/K & I & L & LP */ - if (extAttr->hasLNA == false) { - WR16(devAddr, IQM_AF_AMUX__A, 0x01); + if (ext_attr->has_lna == false) { + WR16(dev_addr, IQM_AF_AMUX__A, 0x01); } - WR16(devAddr, SCU_RAM_ATV_STANDARD__A, 0x002); - WR16(devAddr, IQM_AF_CLP_LEN__A, IQM_AF_CLP_LEN_ATV); - WR16(devAddr, IQM_AF_CLP_TH__A, IQM_AF_CLP_TH_ATV); - WR16(devAddr, IQM_AF_SNS_LEN__A, IQM_AF_SNS_LEN_ATV); - CHK_ERROR(CtrlSetCfgPreSaw(demod, &(extAttr->atvPreSawCfg))); - WR16(devAddr, IQM_AF_AGC_IF__A, 10248); + WR16(dev_addr, SCU_RAM_ATV_STANDARD__A, 0x002); + WR16(dev_addr, IQM_AF_CLP_LEN__A, IQM_AF_CLP_LEN_ATV); + WR16(dev_addr, IQM_AF_CLP_TH__A, IQM_AF_CLP_TH_ATV); + WR16(dev_addr, IQM_AF_SNS_LEN__A, IQM_AF_SNS_LEN_ATV); + CHK_ERROR(ctrl_set_cfg_pre_saw(demod, &(ext_attr->atv_pre_saw_cfg))); + WR16(dev_addr, IQM_AF_AGC_IF__A, 10248); - extAttr->iqmRcRateOfs = 0x00200000L; - WR32(devAddr, IQM_RC_RATE_OFS_LO__A, extAttr->iqmRcRateOfs); - WR16(devAddr, IQM_RC_ADJ_SEL__A, IQM_RC_ADJ_SEL_B_OFF); - WR16(devAddr, IQM_RC_STRETCH__A, IQM_RC_STRETCH_ATV); + ext_attr->iqm_rc_rate_ofs = 0x00200000L; + WR32(dev_addr, IQM_RC_RATE_OFS_LO__A, ext_attr->iqm_rc_rate_ofs); + WR16(dev_addr, IQM_RC_ADJ_SEL__A, IQM_RC_ADJ_SEL_B_OFF); + WR16(dev_addr, IQM_RC_STRETCH__A, IQM_RC_STRETCH_ATV); - WR16(devAddr, IQM_RT_ACTIVE__A, IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_ON | + WR16(dev_addr, IQM_RT_ACTIVE__A, IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_ON | IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_ON); - WR16(devAddr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_ATV__M); - WR16(devAddr, IQM_CF_SYMMETRIC__A, IQM_CF_SYMMETRIC_IM__M); + WR16(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_ATV__M); + WR16(dev_addr, IQM_CF_SYMMETRIC__A, IQM_CF_SYMMETRIC_IM__M); /* default: SIF in standby */ - WR16(devAddr, ATV_TOP_SYNC_SLICE__A, ATV_TOP_SYNC_SLICE_MN); - WR16(devAddr, ATV_TOP_MOD_ACCU__A, ATV_TOP_MOD_ACCU__PRE); - - WR16(devAddr, SCU_RAM_ATV_SIF_GAIN__A, 0x080); - WR16(devAddr, SCU_RAM_ATV_FAGC_TH_RED__A, 10); - WR16(devAddr, SCU_RAM_ATV_AAGC_CNT__A, 7); - WR16(devAddr, SCU_RAM_ATV_NAGC_KI_MIN__A, 0x0225); - WR16(devAddr, SCU_RAM_ATV_NAGC_KI_MAX__A, 0x0547); - WR16(devAddr, SCU_RAM_ATV_KI_CHANGE_TH__A, 20); - WR16(devAddr, SCU_RAM_ATV_LOCK__A, 0); - - WR16(devAddr, IQM_RT_DELAY__A, IQM_RT_DELAY__PRE); - WR16(devAddr, SCU_RAM_ATV_BPC_KI_MIN__A, 531); - WR16(devAddr, SCU_RAM_ATV_PAGC_KI_MIN__A, 1061); - WR16(devAddr, SCU_RAM_ATV_BP_REF_MIN__A, 100); - WR16(devAddr, SCU_RAM_ATV_BP_REF_MAX__A, 260); - WR16(devAddr, SCU_RAM_ATV_BP_LVL__A, 0); - WR16(devAddr, SCU_RAM_ATV_AMS_MAX__A, 0); - WR16(devAddr, SCU_RAM_ATV_AMS_MIN__A, 2047); - WR16(devAddr, SCU_RAM_GPIO__A, 0); + WR16(dev_addr, ATV_TOP_SYNC_SLICE__A, ATV_TOP_SYNC_SLICE_MN); + WR16(dev_addr, ATV_TOP_MOD_ACCU__A, ATV_TOP_MOD_ACCU__PRE); + + WR16(dev_addr, SCU_RAM_ATV_SIF_GAIN__A, 0x080); + WR16(dev_addr, SCU_RAM_ATV_FAGC_TH_RED__A, 10); + WR16(dev_addr, SCU_RAM_ATV_AAGC_CNT__A, 7); + WR16(dev_addr, SCU_RAM_ATV_NAGC_KI_MIN__A, 0x0225); + WR16(dev_addr, SCU_RAM_ATV_NAGC_KI_MAX__A, 0x0547); + WR16(dev_addr, SCU_RAM_ATV_KI_CHANGE_TH__A, 20); + WR16(dev_addr, SCU_RAM_ATV_LOCK__A, 0); + + WR16(dev_addr, IQM_RT_DELAY__A, IQM_RT_DELAY__PRE); + WR16(dev_addr, SCU_RAM_ATV_BPC_KI_MIN__A, 531); + WR16(dev_addr, SCU_RAM_ATV_PAGC_KI_MIN__A, 1061); + WR16(dev_addr, SCU_RAM_ATV_BP_REF_MIN__A, 100); + WR16(dev_addr, SCU_RAM_ATV_BP_REF_MAX__A, 260); + WR16(dev_addr, SCU_RAM_ATV_BP_LVL__A, 0); + WR16(dev_addr, SCU_RAM_ATV_AMS_MAX__A, 0); + WR16(dev_addr, SCU_RAM_ATV_AMS_MIN__A, 2047); + WR16(dev_addr, SCU_RAM_GPIO__A, 0); /* Override reset values with current shadow settings */ - CHK_ERROR(AtvUpdateConfig(demod, true)); + CHK_ERROR(atv_update_config(demod, true)); /* Configure/restore AGC settings */ - CHK_ERROR(InitAGC(demod)); - CHK_ERROR(SetAgcIf(demod, &(extAttr->atvIfAgcCfg), false)); - CHK_ERROR(SetAgcRf(demod, &(extAttr->atvRfAgcCfg), false)); - CHK_ERROR(CtrlSetCfgPreSaw(demod, &(extAttr->atvPreSawCfg))); + CHK_ERROR(init_agc(demod)); + CHK_ERROR(set_agc_if(demod, &(ext_attr->atv_if_agc_cfg), false)); + CHK_ERROR(set_agc_rf(demod, &(ext_attr->atv_rf_agc_cfg), false)); + CHK_ERROR(ctrl_set_cfg_pre_saw(demod, &(ext_attr->atv_pre_saw_cfg))); /* Set SCU ATV substandard,assuming this doesn't require running ATV block */ - cmdSCU.command = SCU_RAM_COMMAND_STANDARD_ATV | + cmd_scu.command = SCU_RAM_COMMAND_STANDARD_ATV | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV; - cmdSCU.parameterLen = 1; - cmdSCU.resultLen = 1; - cmdSCU.parameter = &cmdParam; - cmdSCU.result = &cmdResult; - CHK_ERROR(SCUCommand(devAddr, &cmdSCU)); + cmd_scu.parameter_len = 1; + cmd_scu.result_len = 1; + cmd_scu.parameter = &cmd_param; + cmd_scu.result = &cmd_result; + CHK_ERROR(scu_command(dev_addr, &cmd_scu)); /* turn the analog work around on/off (must after set_env b/c it is set in mc) */ - if (extAttr->mfx == 0x03) { - WR16(devAddr, SCU_RAM_ATV_ENABLE_IIR_WA__A, 0); + if (ext_attr->mfx == 0x03) { + WR16(dev_addr, SCU_RAM_ATV_ENABLE_IIR_WA__A, 0); } else { - WR16(devAddr, SCU_RAM_ATV_ENABLE_IIR_WA__A, 1); - WR16(devAddr, SCU_RAM_ATV_IIR_CRIT__A, 225); + WR16(dev_addr, SCU_RAM_ATV_ENABLE_IIR_WA__A, 1); + WR16(dev_addr, SCU_RAM_ATV_IIR_CRIT__A, 225); } return (DRX_STS_OK); @@ -9444,7 +9444,7 @@ rw_error: #ifndef DRXJ_DIGITAL_ONLY /** -* \fn int SetATVChannel () +* \fn int set_atv_channel () * \brief Set ATV channel. * \param demod: instance of demod. * \return int. @@ -9456,48 +9456,48 @@ rw_error: * */ static int -SetATVChannel(pDRXDemodInstance_t demod, - s32 tunerFreqOffset, - pDRXChannel_t channel, enum drx_standard standard) +set_atv_channel(pdrx_demod_instance_t demod, + s32 tuner_freq_offset, + pdrx_channel_t channel, enum drx_standard standard) { - DRXJSCUCmd_t cmdSCU = { /* command */ 0, - /* parameterLen */ 0, - /* resultLen */ 0, + drxjscu_cmd_t cmd_scu = { /* command */ 0, + /* parameter_len */ 0, + /* result_len */ 0, /* parameter */ NULL, /* result */ NULL }; - u16 cmdResult = 0; - pDRXJData_t extAttr = NULL; - struct i2c_device_addr *devAddr = NULL; + u16 cmd_result = 0; + pdrxj_data_t ext_attr = NULL; + struct i2c_device_addr *dev_addr = NULL; - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* Program frequency shifter No need to account for mirroring on RF */ if (channel->mirror == DRX_MIRROR_AUTO) { - extAttr->mirror = DRX_MIRROR_NO; + ext_attr->mirror = DRX_MIRROR_NO; } else { - extAttr->mirror = channel->mirror; + ext_attr->mirror = channel->mirror; } - CHK_ERROR(SetFrequency(demod, channel, tunerFreqOffset)); - WR16(devAddr, ATV_TOP_CR_FREQ__A, ATV_TOP_CR_FREQ__PRE); + CHK_ERROR(set_frequency(demod, channel, tuner_freq_offset)); + WR16(dev_addr, ATV_TOP_CR_FREQ__A, ATV_TOP_CR_FREQ__PRE); /* Start ATV SCU */ - cmdSCU.command = SCU_RAM_COMMAND_STANDARD_ATV | + cmd_scu.command = SCU_RAM_COMMAND_STANDARD_ATV | SCU_RAM_COMMAND_CMD_DEMOD_START; - cmdSCU.parameterLen = 0; - cmdSCU.resultLen = 1; - cmdSCU.parameter = NULL; - cmdSCU.result = &cmdResult; - CHK_ERROR(SCUCommand(devAddr, &cmdSCU)); + cmd_scu.parameter_len = 0; + cmd_scu.result_len = 1; + cmd_scu.parameter = NULL; + cmd_scu.result = &cmd_result; + CHK_ERROR(scu_command(dev_addr, &cmd_scu)); -/* if ( (extAttr->standard == DRX_STANDARD_FM) && (extAttr->flagSetAUDdone == true) ) +/* if ( (ext_attr->standard == DRX_STANDARD_FM) && (ext_attr->flagSetAUDdone == true) ) { - extAttr->detectedRDS = (bool)false; + ext_attr->detectedRDS = (bool)false; }*/ return (DRX_STS_OK); @@ -9509,7 +9509,7 @@ rw_error: /* -------------------------------------------------------------------------- */ /** -* \fn int GetATVChannel () +* \fn int get_atv_channel () * \brief Set ATV channel. * \param demod: instance of demod. * \param channel: pointer to channel data. @@ -9523,18 +9523,18 @@ rw_error: */ #ifndef DRXJ_DIGITAL_ONLY static int -GetATVChannel(pDRXDemodInstance_t demod, - pDRXChannel_t channel, enum drx_standard standard) +get_atv_channel(pdrx_demod_instance_t demod, + pdrx_channel_t channel, enum drx_standard standard) { s32 offset = 0; - struct i2c_device_addr *devAddr = NULL; - pDRXJData_t extAttr = NULL; + struct i2c_device_addr *dev_addr = NULL; + pdrxj_data_t ext_attr = NULL; - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* Bandwidth */ - channel->bandwidth = ((pDRXJData_t) demod->myExtAttr)->currBandwidth; + channel->bandwidth = ((pdrxj_data_t) demod->my_ext_attr)->curr_bandwidth; switch (standard) { case DRX_STANDARD_NTSC: @@ -9543,32 +9543,32 @@ GetATVChannel(pDRXDemodInstance_t demod, case DRX_STANDARD_PAL_SECAM_I: case DRX_STANDARD_PAL_SECAM_L: { - u16 measuredOffset = 0; + u16 measured_offset = 0; /* get measured frequency offset */ - RR16(devAddr, ATV_TOP_CR_FREQ__A, &measuredOffset); + RR16(dev_addr, ATV_TOP_CR_FREQ__A, &measured_offset); /* Signed 8 bit register => sign extension needed */ - if ((measuredOffset & 0x0080) != 0) { + if ((measured_offset & 0x0080) != 0) { /* sign extension */ - measuredOffset |= 0xFF80; + measured_offset |= 0xFF80; } offset += - (s32) (((s16) measuredOffset) * 10); + (s32) (((s16) measured_offset) * 10); break; } case DRX_STANDARD_PAL_SECAM_LP: { - u16 measuredOffset = 0; + u16 measured_offset = 0; /* get measured frequency offset */ - RR16(devAddr, ATV_TOP_CR_FREQ__A, &measuredOffset); + RR16(dev_addr, ATV_TOP_CR_FREQ__A, &measured_offset); /* Signed 8 bit register => sign extension needed */ - if ((measuredOffset & 0x0080) != 0) { + if ((measured_offset & 0x0080) != 0) { /* sign extension */ - measuredOffset |= 0xFF80; + measured_offset |= 0xFF80; } offset -= - (s32) (((s16) measuredOffset) * 10); + (s32) (((s16) measured_offset) * 10); } break; case DRX_STANDARD_FM: @@ -9591,13 +9591,13 @@ rw_error: /* -------------------------------------------------------------------------- */ /** -* \fn int GetAtvSigStrength() +* \fn int get_atv_sig_strength() * \brief Retrieve signal strength for ATV & FM. * \param devmod Pointer to demodulator instance. -* \param sigQuality Pointer to signal strength data; range 0, .. , 100. +* \param sig_quality Pointer to signal strength data; range 0, .. , 100. * \return int. -* \retval DRX_STS_OK sigStrength contains valid data. -* \retval DRX_STS_ERROR Erroneous data, sigStrength equals 0. +* \retval DRX_STS_OK sig_strength contains valid data. +* \retval DRX_STS_ERROR Erroneous data, sig_strength equals 0. * * Taking into account: * * digital gain @@ -9610,72 +9610,72 @@ rw_error: * is not used ? */ static int -GetAtvSigStrength(pDRXDemodInstance_t demod, u16 *sigStrength) +get_atv_sig_strength(pdrx_demod_instance_t demod, u16 *sig_strength) { - struct i2c_device_addr *devAddr = NULL; - pDRXJData_t extAttr = NULL; + struct i2c_device_addr *dev_addr = NULL; + pdrxj_data_t ext_attr = NULL; /* All weights must add up to 100 (%) TODO: change weights when IF ctrl is available */ - u32 digitalWeight = 50; /* 0 .. 100 */ - u32 rfWeight = 50; /* 0 .. 100 */ - u32 ifWeight = 0; /* 0 .. 100 */ - - u16 digitalCurrGain = 0; - u32 digitalMaxGain = 0; - u32 digitalMinGain = 0; - u16 rfCurrGain = 0; - u32 rfMaxGain = 0x800; /* taken from ucode */ - u32 rfMinGain = 0x7fff; - u16 ifCurrGain = 0; - u32 ifMaxGain = 0x800; /* taken from ucode */ - u32 ifMinGain = 0x7fff; - - u32 digitalStrength = 0; /* 0.. 100 */ - u32 rfStrength = 0; /* 0.. 100 */ - u32 ifStrength = 0; /* 0.. 100 */ - - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; - - *sigStrength = 0; - - switch (extAttr->standard) { + u32 digital_weight = 50; /* 0 .. 100 */ + u32 rf_weight = 50; /* 0 .. 100 */ + u32 if_weight = 0; /* 0 .. 100 */ + + u16 digital_curr_gain = 0; + u32 digital_max_gain = 0; + u32 digital_min_gain = 0; + u16 rf_curr_gain = 0; + u32 rf_max_gain = 0x800; /* taken from ucode */ + u32 rf_min_gain = 0x7fff; + u16 if_curr_gain = 0; + u32 if_max_gain = 0x800; /* taken from ucode */ + u32 if_min_gain = 0x7fff; + + u32 digital_strength = 0; /* 0.. 100 */ + u32 rf_strength = 0; /* 0.. 100 */ + u32 if_strength = 0; /* 0.. 100 */ + + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; + + *sig_strength = 0; + + switch (ext_attr->standard) { case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */ case DRX_STANDARD_PAL_SECAM_LP: /* fallthrough */ case DRX_STANDARD_NTSC: - SARR16(devAddr, SCU_RAM_ATV_VID_GAIN_HI__A, &digitalCurrGain); - digitalMaxGain = 22512; /* taken from ucode */ - digitalMinGain = 2400; /* taken from ucode */ + SARR16(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, &digital_curr_gain); + digital_max_gain = 22512; /* taken from ucode */ + digital_min_gain = 2400; /* taken from ucode */ break; case DRX_STANDARD_FM: - SARR16(devAddr, SCU_RAM_ATV_SIF_GAIN__A, &digitalCurrGain); - digitalMaxGain = 0x4ff; /* taken from ucode */ - digitalMinGain = 0; /* taken from ucode */ + SARR16(dev_addr, SCU_RAM_ATV_SIF_GAIN__A, &digital_curr_gain); + digital_max_gain = 0x4ff; /* taken from ucode */ + digital_min_gain = 0; /* taken from ucode */ break; default: return (DRX_STS_ERROR); break; } - RR16(devAddr, IQM_AF_AGC_RF__A, &rfCurrGain); - RR16(devAddr, IQM_AF_AGC_IF__A, &ifCurrGain); + RR16(dev_addr, IQM_AF_AGC_RF__A, &rf_curr_gain); + RR16(dev_addr, IQM_AF_AGC_IF__A, &if_curr_gain); /* clipping */ - if (digitalCurrGain >= digitalMaxGain) - digitalCurrGain = (u16) digitalMaxGain; - if (digitalCurrGain <= digitalMinGain) - digitalCurrGain = (u16) digitalMinGain; - if (ifCurrGain <= ifMaxGain) - ifCurrGain = (u16) ifMaxGain; - if (ifCurrGain >= ifMinGain) - ifCurrGain = (u16) ifMinGain; - if (rfCurrGain <= rfMaxGain) - rfCurrGain = (u16) rfMaxGain; - if (rfCurrGain >= rfMinGain) - rfCurrGain = (u16) rfMinGain; + if (digital_curr_gain >= digital_max_gain) + digital_curr_gain = (u16) digital_max_gain; + if (digital_curr_gain <= digital_min_gain) + digital_curr_gain = (u16) digital_min_gain; + if (if_curr_gain <= if_max_gain) + if_curr_gain = (u16) if_max_gain; + if (if_curr_gain >= if_min_gain) + if_curr_gain = (u16) if_min_gain; + if (rf_curr_gain <= rf_max_gain) + rf_curr_gain = (u16) rf_max_gain; + if (rf_curr_gain >= rf_min_gain) + rf_curr_gain = (u16) rf_min_gain; /* TODO: use SCU_RAM_ATV_RAGC_HR__A to shift max and min in case of clipping at ADC */ @@ -9684,22 +9684,22 @@ GetAtvSigStrength(pDRXDemodInstance_t demod, u16 *sigStrength) /* Digital gain */ /* TODO: ADC clipping not handled */ - digitalStrength = (100 * (digitalMaxGain - (u32) digitalCurrGain)) / - (digitalMaxGain - digitalMinGain); + digital_strength = (100 * (digital_max_gain - (u32) digital_curr_gain)) / + (digital_max_gain - digital_min_gain); /* TODO: IF gain not implemented yet in microcode, check after impl. */ - ifStrength = (100 * ((u32) ifCurrGain - ifMaxGain)) / - (ifMinGain - ifMaxGain); + if_strength = (100 * ((u32) if_curr_gain - if_max_gain)) / + (if_min_gain - if_max_gain); /* Rf gain */ /* TODO: ADC clipping not handled */ - rfStrength = (100 * ((u32) rfCurrGain - rfMaxGain)) / - (rfMinGain - rfMaxGain); + rf_strength = (100 * ((u32) rf_curr_gain - rf_max_gain)) / + (rf_min_gain - rf_max_gain); /* Compute a weighted signal strength (in %) */ - *sigStrength = (u16) (digitalWeight * digitalStrength + - rfWeight * rfStrength + ifWeight * ifStrength); - *sigStrength /= 100; + *sig_strength = (u16) (digital_weight * digital_strength + + rf_weight * rf_strength + if_weight * if_strength); + *sig_strength /= 100; return (DRX_STS_OK); rw_error: @@ -9708,31 +9708,31 @@ rw_error: /* -------------------------------------------------------------------------- */ /** -* \fn int AtvSigQuality() +* \fn int atv_sig_quality() * \brief Retrieve signal quality indication for ATV. * \param devmod Pointer to demodulator instance. -* \param sigQuality Pointer to signal quality structure. +* \param sig_quality Pointer to signal quality structure. * \return int. -* \retval DRX_STS_OK sigQuality contains valid data. -* \retval DRX_STS_ERROR Erroneous data, sigQuality indicator equals 0. +* \retval DRX_STS_OK sig_quality contains valid data. +* \retval DRX_STS_ERROR Erroneous data, sig_quality indicator equals 0. * * */ static int -AtvSigQuality(pDRXDemodInstance_t demod, pDRXSigQuality_t sigQuality) +atv_sig_quality(pdrx_demod_instance_t demod, pdrx_sig_quality_t sig_quality) { - struct i2c_device_addr *devAddr = NULL; - u16 qualityIndicator = 0; + struct i2c_device_addr *dev_addr = NULL; + u16 quality_indicator = 0; - devAddr = demod->myI2CDevAddr; + dev_addr = demod->my_i2c_dev_addr; /* defined values for fields not used */ - sigQuality->MER = 0; - sigQuality->preViterbiBER = 0; - sigQuality->postViterbiBER = 0; - sigQuality->scaleFactorBER = 1; - sigQuality->packetError = 0; - sigQuality->postReedSolomonBER = 0; + sig_quality->MER = 0; + sig_quality->pre_viterbi_ber = 0; + sig_quality->post_viterbi_ber = 0; + sig_quality->scale_factor_ber = 1; + sig_quality->packet_error = 0; + sig_quality->post_reed_solomon_ber = 0; /* Mapping: @@ -9741,17 +9741,17 @@ AtvSigQuality(pDRXDemodInstance_t demod, pDRXSigQuality_t sigQuality) 0x700..0x7ff: no signal => 0% .. 30% */ - SARR16(devAddr, SCU_RAM_ATV_CR_LOCK__A, &qualityIndicator); - qualityIndicator &= SCU_RAM_ATV_CR_LOCK_CR_LOCK__M; - if (qualityIndicator <= 0x80) { - sigQuality->indicator = - 80 + ((20 * (0x80 - qualityIndicator)) / 0x80); - } else if (qualityIndicator <= 0x700) { - sigQuality->indicator = 30 + - ((50 * (0x700 - qualityIndicator)) / (0x700 - 0x81)); + SARR16(dev_addr, SCU_RAM_ATV_CR_LOCK__A, &quality_indicator); + quality_indicator &= SCU_RAM_ATV_CR_LOCK_CR_LOCK__M; + if (quality_indicator <= 0x80) { + sig_quality->indicator = + 80 + ((20 * (0x80 - quality_indicator)) / 0x80); + } else if (quality_indicator <= 0x700) { + sig_quality->indicator = 30 + + ((50 * (0x700 - quality_indicator)) / (0x700 - 0x81)); } else { - sigQuality->indicator = - (30 * (0x7FF - qualityIndicator)) / (0x7FF - 0x701); + sig_quality->indicator = + (30 * (0x7FF - quality_indicator)) / (0x7FF - 0x701); } return (DRX_STS_OK); @@ -9777,20 +9777,20 @@ rw_error: * \return int. * */ -static int PowerUpAud(pDRXDemodInstance_t demod, bool setStandard) +static int power_up_aud(pdrx_demod_instance_t demod, bool set_standard) { - DRXAudStandard_t audStandard = DRX_AUD_STANDARD_AUTO; - struct i2c_device_addr *devAddr = NULL; + drx_aud_standard_t aud_standard = DRX_AUD_STANDARD_AUTO; + struct i2c_device_addr *dev_addr = NULL; - devAddr = demod->myI2CDevAddr; + dev_addr = demod->my_i2c_dev_addr; - WR16(devAddr, AUD_TOP_COMM_EXEC__A, AUD_TOP_COMM_EXEC_ACTIVE); + WR16(dev_addr, AUD_TOP_COMM_EXEC__A, AUD_TOP_COMM_EXEC_ACTIVE); /* setup TR interface: R/W mode, fifosize=8 */ - WR16(devAddr, AUD_TOP_TR_MDE__A, 8); - WR16(devAddr, AUD_COMM_EXEC__A, AUD_COMM_EXEC_ACTIVE); + WR16(dev_addr, AUD_TOP_TR_MDE__A, 8); + WR16(dev_addr, AUD_COMM_EXEC__A, AUD_COMM_EXEC_ACTIVE); - if (setStandard == true) { - CHK_ERROR(AUDCtrlSetStandard(demod, &audStandard)); + if (set_standard == true) { + CHK_ERROR(aud_ctrl_set_standard(demod, &aud_standard)); } return DRX_STS_OK; @@ -9806,17 +9806,17 @@ rw_error: * \return int. * */ -static int PowerDownAud(pDRXDemodInstance_t demod) +static int power_down_aud(pdrx_demod_instance_t demod) { - struct i2c_device_addr *devAddr = NULL; - pDRXJData_t extAttr = NULL; + struct i2c_device_addr *dev_addr = NULL; + pdrxj_data_t ext_attr = NULL; - devAddr = (struct i2c_device_addr *) demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; + dev_addr = (struct i2c_device_addr *) demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; - WR16(devAddr, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP); + WR16(dev_addr, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP); - extAttr->audData.audioIsActive = false; + ext_attr->aud_data.audio_is_active = false; return DRX_STS_OK; rw_error: @@ -9831,36 +9831,36 @@ rw_error: * \return int. * */ -static int AUDGetModus(pDRXDemodInstance_t demod, u16 *modus) +static int aud_get_modus(pdrx_demod_instance_t demod, u16 *modus) { - struct i2c_device_addr *devAddr = NULL; - pDRXJData_t extAttr = NULL; + struct i2c_device_addr *dev_addr = NULL; + pdrxj_data_t ext_attr = NULL; - u16 rModus = 0; - u16 rModusHi = 0; - u16 rModusLo = 0; + u16 r_modus = 0; + u16 r_modusHi = 0; + u16 r_modusLo = 0; if (modus == NULL) { return DRX_STS_INVALID_ARG; } - devAddr = (struct i2c_device_addr *) demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; + dev_addr = (struct i2c_device_addr *) demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* power up */ - if (extAttr->audData.audioIsActive == false) { - CHK_ERROR(PowerUpAud(demod, true)); - extAttr->audData.audioIsActive = true; + if (ext_attr->aud_data.audio_is_active == false) { + CHK_ERROR(power_up_aud(demod, true)); + ext_attr->aud_data.audio_is_active = true; } /* Modus register is combined in to RAM location */ - RR16(devAddr, AUD_DEM_RAM_MODUS_HI__A, &rModusHi); - RR16(devAddr, AUD_DEM_RAM_MODUS_LO__A, &rModusLo); + RR16(dev_addr, AUD_DEM_RAM_MODUS_HI__A, &r_modusHi); + RR16(dev_addr, AUD_DEM_RAM_MODUS_LO__A, &r_modusLo); - rModus = ((rModusHi << 12) & AUD_DEM_RAM_MODUS_HI__M) - | (((rModusLo & AUD_DEM_RAM_MODUS_LO__M))); + r_modus = ((r_modusHi << 12) & AUD_DEM_RAM_MODUS_HI__M) + | (((r_modusLo & AUD_DEM_RAM_MODUS_LO__M))); - *modus = rModus; + *modus = r_modus; return DRX_STS_OK; rw_error: @@ -9872,65 +9872,65 @@ rw_error: /** * \brief Get audio RDS dat * \param demod instance of demodulator -* \param pointer to DRXCfgAudRDS_t +* \param pointer to drx_cfg_aud_rds_t * \return int. * */ static int -AUDCtrlGetCfgRDS(pDRXDemodInstance_t demod, pDRXCfgAudRDS_t status) +aud_ctrl_get_cfg_rds(pdrx_demod_instance_t demod, pdrx_cfg_aud_rds_t status) { struct i2c_device_addr *addr = NULL; - pDRXJData_t extAttr = NULL; + pdrxj_data_t ext_attr = NULL; - u16 rRDSArrayCntInit = 0; - u16 rRDSArrayCntCheck = 0; - u16 rRDSData = 0; - u16 RDSDataCnt = 0; + u16 r_rds_array_cnt_init = 0; + u16 r_rds_array_cnt_check = 0; + u16 r_rds_data = 0; + u16 rds_data_cnt = 0; - addr = (struct i2c_device_addr *) demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; + addr = (struct i2c_device_addr *) demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; if (status == NULL) { return DRX_STS_INVALID_ARG; } /* power up */ - if (extAttr->audData.audioIsActive == false) { - CHK_ERROR(PowerUpAud(demod, true)); - extAttr->audData.audioIsActive = true; + if (ext_attr->aud_data.audio_is_active == false) { + CHK_ERROR(power_up_aud(demod, true)); + ext_attr->aud_data.audio_is_active = true; } status->valid = false; - RR16(addr, AUD_DEM_RD_RDS_ARRAY_CNT__A, &rRDSArrayCntInit); + RR16(addr, AUD_DEM_RD_RDS_ARRAY_CNT__A, &r_rds_array_cnt_init); - if (rRDSArrayCntInit == + if (r_rds_array_cnt_init == AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT_RDS_DATA_NOT_VALID) { /* invalid data */ return DRX_STS_OK; } - if (extAttr->audData.rdsDataCounter == rRDSArrayCntInit) { + if (ext_attr->aud_data.rds_data_counter == r_rds_array_cnt_init) { /* no new data */ return DRX_STS_OK; } /* RDS is detected, as long as FM radio is selected assume RDS will be available */ - extAttr->audData.rdsDataPresent = true; + ext_attr->aud_data.rds_data_present = true; /* new data */ /* read the data */ - for (RDSDataCnt = 0; RDSDataCnt < AUD_RDS_ARRAY_SIZE; RDSDataCnt++) { - RR16(addr, AUD_DEM_RD_RDS_DATA__A, &rRDSData); - status->data[RDSDataCnt] = rRDSData; + for (rds_data_cnt = 0; rds_data_cnt < AUD_RDS_ARRAY_SIZE; rds_data_cnt++) { + RR16(addr, AUD_DEM_RD_RDS_DATA__A, &r_rds_data); + status->data[rds_data_cnt] = r_rds_data; } - RR16(addr, AUD_DEM_RD_RDS_ARRAY_CNT__A, &rRDSArrayCntCheck); + RR16(addr, AUD_DEM_RD_RDS_ARRAY_CNT__A, &r_rds_array_cnt_check); - if (rRDSArrayCntCheck == rRDSArrayCntInit) { + if (r_rds_array_cnt_check == r_rds_array_cnt_init) { status->valid = true; - extAttr->audData.rdsDataCounter = rRDSArrayCntCheck; + ext_attr->aud_data.rds_data_counter = r_rds_array_cnt_check; } return DRX_STS_OK; @@ -9942,71 +9942,71 @@ rw_error: /** * \brief Get the current audio carrier detection status * \param demod instance of demodulator -* \param pointer to AUDCtrlGetStatus +* \param pointer to aud_ctrl_get_status * \return int. * */ static int -AUDCtrlGetCarrierDetectStatus(pDRXDemodInstance_t demod, pDRXAudStatus_t status) +aud_ctrl_get_carrier_detect_status(pdrx_demod_instance_t demod, pdrx_aud_status_t status) { - pDRXJData_t extAttr = NULL; - struct i2c_device_addr *devAddr = NULL; + pdrxj_data_t ext_attr = NULL; + struct i2c_device_addr *dev_addr = NULL; - u16 rData = 0; + u16 r_data = 0; if (status == NULL) { return DRX_STS_INVALID_ARG; } - devAddr = (struct i2c_device_addr *) demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; + dev_addr = (struct i2c_device_addr *) demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* power up */ - if (extAttr->audData.audioIsActive == false) { - CHK_ERROR(PowerUpAud(demod, true)); - extAttr->audData.audioIsActive = true; + if (ext_attr->aud_data.audio_is_active == false) { + CHK_ERROR(power_up_aud(demod, true)); + ext_attr->aud_data.audio_is_active = true; } /* initialize the variables */ - status->carrierA = false; - status->carrierB = false; - status->nicamStatus = DRX_AUD_NICAM_NOT_DETECTED; + status->carrier_a = false; + status->carrier_b = false; + status->nicam_status = DRX_AUD_NICAM_NOT_DETECTED; status->sap = false; status->stereo = false; /* read stereo sound mode indication */ - RR16(devAddr, AUD_DEM_RD_STATUS__A, &rData); + RR16(dev_addr, AUD_DEM_RD_STATUS__A, &r_data); /* carrier a detected */ - if ((rData & AUD_DEM_RD_STATUS_STAT_CARR_A__M) == + if ((r_data & AUD_DEM_RD_STATUS_STAT_CARR_A__M) == AUD_DEM_RD_STATUS_STAT_CARR_A_DETECTED) { - status->carrierA = true; + status->carrier_a = true; } /* carrier b detected */ - if ((rData & AUD_DEM_RD_STATUS_STAT_CARR_B__M) == + if ((r_data & AUD_DEM_RD_STATUS_STAT_CARR_B__M) == AUD_DEM_RD_STATUS_STAT_CARR_B_DETECTED) { - status->carrierB = true; + status->carrier_b = true; } /* nicam detected */ - if ((rData & AUD_DEM_RD_STATUS_STAT_NICAM__M) == + if ((r_data & AUD_DEM_RD_STATUS_STAT_NICAM__M) == AUD_DEM_RD_STATUS_STAT_NICAM_NICAM_DETECTED) { - if ((rData & AUD_DEM_RD_STATUS_BAD_NICAM__M) == + if ((r_data & AUD_DEM_RD_STATUS_BAD_NICAM__M) == AUD_DEM_RD_STATUS_BAD_NICAM_OK) { - status->nicamStatus = DRX_AUD_NICAM_DETECTED; + status->nicam_status = DRX_AUD_NICAM_DETECTED; } else { - status->nicamStatus = DRX_AUD_NICAM_BAD; + status->nicam_status = DRX_AUD_NICAM_BAD; } } /* audio mode bilingual or SAP detected */ - if ((rData & AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__M) == + if ((r_data & AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__M) == AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP_SAP) { status->sap = true; } /* stereo detected */ - if ((rData & AUD_DEM_RD_STATUS_STAT_STEREO__M) == + if ((r_data & AUD_DEM_RD_STATUS_STAT_STEREO__M) == AUD_DEM_RD_STATUS_STAT_STEREO_STEREO) { status->stereo = true; } @@ -10020,37 +10020,37 @@ rw_error: /** * \brief Get the current audio status parameters * \param demod instance of demodulator -* \param pointer to AUDCtrlGetStatus +* \param pointer to aud_ctrl_get_status * \return int. * */ static int -AUDCtrlGetStatus(pDRXDemodInstance_t demod, pDRXAudStatus_t status) +aud_ctrl_get_status(pdrx_demod_instance_t demod, pdrx_aud_status_t status) { - pDRXJData_t extAttr = NULL; - struct i2c_device_addr *devAddr = NULL; - DRXCfgAudRDS_t rds = { false, {0} }; - u16 rData = 0; + pdrxj_data_t ext_attr = NULL; + struct i2c_device_addr *dev_addr = NULL; + drx_cfg_aud_rds_t rds = { false, {0} }; + u16 r_data = 0; if (status == NULL) { return DRX_STS_INVALID_ARG; } - devAddr = (struct i2c_device_addr *) demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; + dev_addr = (struct i2c_device_addr *) demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* carrier detection */ - CHK_ERROR(AUDCtrlGetCarrierDetectStatus(demod, status)); + CHK_ERROR(aud_ctrl_get_carrier_detect_status(demod, status)); /* rds data */ status->rds = false; - CHK_ERROR(AUDCtrlGetCfgRDS(demod, &rds)); - status->rds = extAttr->audData.rdsDataPresent; + CHK_ERROR(aud_ctrl_get_cfg_rds(demod, &rds)); + status->rds = ext_attr->aud_data.rds_data_present; - /* fmIdent */ - RR16(devAddr, AUD_DSP_RD_FM_IDENT_VALUE__A, &rData); - rData >>= AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__B; - status->fmIdent = (s8) rData; + /* fm_ident */ + RR16(dev_addr, AUD_DSP_RD_FM_IDENT_VALUE__A, &r_data); + r_data >>= AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__B; + status->fm_ident = (s8) r_data; return DRX_STS_OK; rw_error: @@ -10061,43 +10061,43 @@ rw_error: /** * \brief Get the current volume settings * \param demod instance of demodulator -* \param pointer to DRXCfgAudVolume_t +* \param pointer to drx_cfg_aud_volume_t * \return int. * */ static int -AUDCtrlGetCfgVolume(pDRXDemodInstance_t demod, pDRXCfgAudVolume_t volume) +aud_ctrl_get_cfg_volume(pdrx_demod_instance_t demod, pdrx_cfg_aud_volume_t volume) { - struct i2c_device_addr *devAddr = NULL; - pDRXJData_t extAttr = NULL; + struct i2c_device_addr *dev_addr = NULL; + pdrxj_data_t ext_attr = NULL; - u16 rVolume = 0; - u16 rAVC = 0; - u16 rStrengthLeft = 0; - u16 rStrengthRight = 0; + u16 r_volume = 0; + u16 r_avc = 0; + u16 r_strength_left = 0; + u16 r_strength_right = 0; if (volume == NULL) { return DRX_STS_INVALID_ARG; } - devAddr = (struct i2c_device_addr *) demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; + dev_addr = (struct i2c_device_addr *) demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* power up */ - if (extAttr->audData.audioIsActive == false) { - CHK_ERROR(PowerUpAud(demod, true)); - extAttr->audData.audioIsActive = true; + if (ext_attr->aud_data.audio_is_active == false) { + CHK_ERROR(power_up_aud(demod, true)); + ext_attr->aud_data.audio_is_active = true; } /* volume */ - volume->mute = extAttr->audData.volume.mute; - RR16(devAddr, AUD_DSP_WR_VOLUME__A, &rVolume); - if (rVolume == 0) { + volume->mute = ext_attr->aud_data.volume.mute; + RR16(dev_addr, AUD_DSP_WR_VOLUME__A, &r_volume); + if (r_volume == 0) { volume->mute = true; - volume->volume = extAttr->audData.volume.volume; + volume->volume = ext_attr->aud_data.volume.volume; } else { volume->mute = false; - volume->volume = ((rVolume & AUD_DSP_WR_VOLUME_VOL_MAIN__M) >> + volume->volume = ((r_volume & AUD_DSP_WR_VOLUME_VOL_MAIN__M) >> AUD_DSP_WR_VOLUME_VOL_MAIN__B) - AUD_VOLUME_ZERO_DB; if (volume->volume < AUD_VOLUME_DB_MIN) { @@ -10109,24 +10109,24 @@ AUDCtrlGetCfgVolume(pDRXDemodInstance_t demod, pDRXCfgAudVolume_t volume) } /* automatic volume control */ - RR16(devAddr, AUD_DSP_WR_AVC__A, &rAVC); + RR16(dev_addr, AUD_DSP_WR_AVC__A, &r_avc); - if ((rAVC & AUD_DSP_WR_AVC_AVC_ON__M) == AUD_DSP_WR_AVC_AVC_ON_OFF) + if ((r_avc & AUD_DSP_WR_AVC_AVC_ON__M) == AUD_DSP_WR_AVC_AVC_ON_OFF) { - volume->avcMode = DRX_AUD_AVC_OFF; + volume->avc_mode = DRX_AUD_AVC_OFF; } else { - switch (rAVC & AUD_DSP_WR_AVC_AVC_DECAY__M) { + switch (r_avc & AUD_DSP_WR_AVC_AVC_DECAY__M) { case AUD_DSP_WR_AVC_AVC_DECAY_20_MSEC: - volume->avcMode = DRX_AUD_AVC_DECAYTIME_20MS; + volume->avc_mode = DRX_AUD_AVC_DECAYTIME_20MS; break; case AUD_DSP_WR_AVC_AVC_DECAY_8_SEC: - volume->avcMode = DRX_AUD_AVC_DECAYTIME_8S; + volume->avc_mode = DRX_AUD_AVC_DECAYTIME_8S; break; case AUD_DSP_WR_AVC_AVC_DECAY_4_SEC: - volume->avcMode = DRX_AUD_AVC_DECAYTIME_4S; + volume->avc_mode = DRX_AUD_AVC_DECAYTIME_4S; break; case AUD_DSP_WR_AVC_AVC_DECAY_2_SEC: - volume->avcMode = DRX_AUD_AVC_DECAYTIME_2S; + volume->avc_mode = DRX_AUD_AVC_DECAYTIME_2S; break; default: return DRX_STS_ERROR; @@ -10135,15 +10135,15 @@ AUDCtrlGetCfgVolume(pDRXDemodInstance_t demod, pDRXCfgAudVolume_t volume) } /* max attenuation */ - switch (rAVC & AUD_DSP_WR_AVC_AVC_MAX_ATT__M) { + switch (r_avc & AUD_DSP_WR_AVC_AVC_MAX_ATT__M) { case AUD_DSP_WR_AVC_AVC_MAX_ATT_12DB: - volume->avcMaxAtten = DRX_AUD_AVC_MAX_ATTEN_12DB; + volume->avc_max_atten = DRX_AUD_AVC_MAX_ATTEN_12DB; break; case AUD_DSP_WR_AVC_AVC_MAX_ATT_18DB: - volume->avcMaxAtten = DRX_AUD_AVC_MAX_ATTEN_18DB; + volume->avc_max_atten = DRX_AUD_AVC_MAX_ATTEN_18DB; break; case AUD_DSP_WR_AVC_AVC_MAX_ATT_24DB: - volume->avcMaxAtten = DRX_AUD_AVC_MAX_ATTEN_24DB; + volume->avc_max_atten = DRX_AUD_AVC_MAX_ATTEN_24DB; break; default: return DRX_STS_ERROR; @@ -10151,15 +10151,15 @@ AUDCtrlGetCfgVolume(pDRXDemodInstance_t demod, pDRXCfgAudVolume_t volume) } /* max gain */ - switch (rAVC & AUD_DSP_WR_AVC_AVC_MAX_GAIN__M) { + switch (r_avc & AUD_DSP_WR_AVC_AVC_MAX_GAIN__M) { case AUD_DSP_WR_AVC_AVC_MAX_GAIN_0DB: - volume->avcMaxGain = DRX_AUD_AVC_MAX_GAIN_0DB; + volume->avc_max_gain = DRX_AUD_AVC_MAX_GAIN_0DB; break; case AUD_DSP_WR_AVC_AVC_MAX_GAIN_6DB: - volume->avcMaxGain = DRX_AUD_AVC_MAX_GAIN_6DB; + volume->avc_max_gain = DRX_AUD_AVC_MAX_GAIN_6DB; break; case AUD_DSP_WR_AVC_AVC_MAX_GAIN_12DB: - volume->avcMaxGain = DRX_AUD_AVC_MAX_GAIN_12DB; + volume->avc_max_gain = DRX_AUD_AVC_MAX_GAIN_12DB; break; default: return DRX_STS_ERROR; @@ -10167,7 +10167,7 @@ AUDCtrlGetCfgVolume(pDRXDemodInstance_t demod, pDRXCfgAudVolume_t volume) } /* reference level */ - volume->avcRefLevel = (u16) ((rAVC & AUD_DSP_WR_AVC_AVC_REF_LEV__M) >> + volume->avc_ref_level = (u16) ((r_avc & AUD_DSP_WR_AVC_AVC_REF_LEV__M) >> AUD_DSP_WR_AVC_AVC_REF_LEV__B); /* read qpeak registers and calculate strength of left and right carrier */ @@ -10177,13 +10177,13 @@ AUDCtrlGetCfgVolume(pDRXDemodInstance_t demod, pDRXCfgAudVolume_t volume) /* QP vaues */ /* left carrier */ - RR16(devAddr, AUD_DSP_RD_QPEAK_L__A, &rStrengthLeft); - volume->strengthLeft = (((s16) Log10Times100(rStrengthLeft)) - + RR16(dev_addr, AUD_DSP_RD_QPEAK_L__A, &r_strength_left); + volume->strength_left = (((s16) log1_times100(r_strength_left)) - AUD_CARRIER_STRENGTH_QP_0DB_LOG10T100) / 5; /* right carrier */ - RR16(devAddr, AUD_DSP_RD_QPEAK_R__A, &rStrengthRight); - volume->strengthRight = (((s16) Log10Times100(rStrengthRight)) - + RR16(dev_addr, AUD_DSP_RD_QPEAK_R__A, &r_strength_right); + volume->strength_right = (((s16) log1_times100(r_strength_right)) - AUD_CARRIER_STRENGTH_QP_0DB_LOG10T100) / 5; return DRX_STS_OK; @@ -10195,30 +10195,30 @@ rw_error: /** * \brief Set the current volume settings * \param demod instance of demodulator -* \param pointer to DRXCfgAudVolume_t +* \param pointer to drx_cfg_aud_volume_t * \return int. * */ static int -AUDCtrlSetCfgVolume(pDRXDemodInstance_t demod, pDRXCfgAudVolume_t volume) +aud_ctrl_set_cfg_volume(pdrx_demod_instance_t demod, pdrx_cfg_aud_volume_t volume) { - struct i2c_device_addr *devAddr = NULL; - pDRXJData_t extAttr = NULL; + struct i2c_device_addr *dev_addr = NULL; + pdrxj_data_t ext_attr = NULL; - u16 wVolume = 0; - u16 wAVC = 0; + u16 w_volume = 0; + u16 w_avc = 0; if (volume == NULL) { return DRX_STS_INVALID_ARG; } - devAddr = (struct i2c_device_addr *) demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; + dev_addr = (struct i2c_device_addr *) demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* power up */ - if (extAttr->audData.audioIsActive == false) { - CHK_ERROR(PowerUpAud(demod, true)); - extAttr->audData.audioIsActive = true; + if (ext_attr->aud_data.audio_is_active == false) { + CHK_ERROR(power_up_aud(demod, true)); + ext_attr->aud_data.audio_is_active = true; } /* volume */ @@ -10228,48 +10228,48 @@ AUDCtrlSetCfgVolume(pDRXDemodInstance_t demod, pDRXCfgAudVolume_t volume) return DRX_STS_INVALID_ARG; } - RR16(devAddr, AUD_DSP_WR_VOLUME__A, &wVolume); + RR16(dev_addr, AUD_DSP_WR_VOLUME__A, &w_volume); /* clear the volume mask */ - wVolume &= (u16) ~AUD_DSP_WR_VOLUME_VOL_MAIN__M; + w_volume &= (u16) ~AUD_DSP_WR_VOLUME_VOL_MAIN__M; if (volume->mute == true) { /* mute */ /* mute overrules volume */ - wVolume |= (u16) (0); + w_volume |= (u16) (0); } else { - wVolume |= (u16) ((volume->volume + AUD_VOLUME_ZERO_DB) << + w_volume |= (u16) ((volume->volume + AUD_VOLUME_ZERO_DB) << AUD_DSP_WR_VOLUME_VOL_MAIN__B); } - WR16(devAddr, AUD_DSP_WR_VOLUME__A, wVolume); + WR16(dev_addr, AUD_DSP_WR_VOLUME__A, w_volume); /* automatic volume control */ - RR16(devAddr, AUD_DSP_WR_AVC__A, &wAVC); + RR16(dev_addr, AUD_DSP_WR_AVC__A, &w_avc); /* clear masks that require writing */ - wAVC &= (u16) ~AUD_DSP_WR_AVC_AVC_ON__M; - wAVC &= (u16) ~AUD_DSP_WR_AVC_AVC_DECAY__M; + w_avc &= (u16) ~AUD_DSP_WR_AVC_AVC_ON__M; + w_avc &= (u16) ~AUD_DSP_WR_AVC_AVC_DECAY__M; - if (volume->avcMode == DRX_AUD_AVC_OFF) { - wAVC |= (AUD_DSP_WR_AVC_AVC_ON_OFF); + if (volume->avc_mode == DRX_AUD_AVC_OFF) { + w_avc |= (AUD_DSP_WR_AVC_AVC_ON_OFF); } else { - wAVC |= (AUD_DSP_WR_AVC_AVC_ON_ON); + w_avc |= (AUD_DSP_WR_AVC_AVC_ON_ON); /* avc decay */ - switch (volume->avcMode) { + switch (volume->avc_mode) { case DRX_AUD_AVC_DECAYTIME_20MS: - wAVC |= AUD_DSP_WR_AVC_AVC_DECAY_20_MSEC; + w_avc |= AUD_DSP_WR_AVC_AVC_DECAY_20_MSEC; break; case DRX_AUD_AVC_DECAYTIME_8S: - wAVC |= AUD_DSP_WR_AVC_AVC_DECAY_8_SEC; + w_avc |= AUD_DSP_WR_AVC_AVC_DECAY_8_SEC; break; case DRX_AUD_AVC_DECAYTIME_4S: - wAVC |= AUD_DSP_WR_AVC_AVC_DECAY_4_SEC; + w_avc |= AUD_DSP_WR_AVC_AVC_DECAY_4_SEC; break; case DRX_AUD_AVC_DECAYTIME_2S: - wAVC |= AUD_DSP_WR_AVC_AVC_DECAY_2_SEC; + w_avc |= AUD_DSP_WR_AVC_AVC_DECAY_2_SEC; break; default: return DRX_STS_INVALID_ARG; @@ -10277,49 +10277,49 @@ AUDCtrlSetCfgVolume(pDRXDemodInstance_t demod, pDRXCfgAudVolume_t volume) } /* max attenuation */ - wAVC &= (u16) ~AUD_DSP_WR_AVC_AVC_MAX_ATT__M; - switch (volume->avcMaxAtten) { + w_avc &= (u16) ~AUD_DSP_WR_AVC_AVC_MAX_ATT__M; + switch (volume->avc_max_atten) { case DRX_AUD_AVC_MAX_ATTEN_12DB: - wAVC |= AUD_DSP_WR_AVC_AVC_MAX_ATT_12DB; + w_avc |= AUD_DSP_WR_AVC_AVC_MAX_ATT_12DB; break; case DRX_AUD_AVC_MAX_ATTEN_18DB: - wAVC |= AUD_DSP_WR_AVC_AVC_MAX_ATT_18DB; + w_avc |= AUD_DSP_WR_AVC_AVC_MAX_ATT_18DB; break; case DRX_AUD_AVC_MAX_ATTEN_24DB: - wAVC |= AUD_DSP_WR_AVC_AVC_MAX_ATT_24DB; + w_avc |= AUD_DSP_WR_AVC_AVC_MAX_ATT_24DB; break; default: return DRX_STS_INVALID_ARG; } /* max gain */ - wAVC &= (u16) ~AUD_DSP_WR_AVC_AVC_MAX_GAIN__M; - switch (volume->avcMaxGain) { + w_avc &= (u16) ~AUD_DSP_WR_AVC_AVC_MAX_GAIN__M; + switch (volume->avc_max_gain) { case DRX_AUD_AVC_MAX_GAIN_0DB: - wAVC |= AUD_DSP_WR_AVC_AVC_MAX_GAIN_0DB; + w_avc |= AUD_DSP_WR_AVC_AVC_MAX_GAIN_0DB; break; case DRX_AUD_AVC_MAX_GAIN_6DB: - wAVC |= AUD_DSP_WR_AVC_AVC_MAX_GAIN_6DB; + w_avc |= AUD_DSP_WR_AVC_AVC_MAX_GAIN_6DB; break; case DRX_AUD_AVC_MAX_GAIN_12DB: - wAVC |= AUD_DSP_WR_AVC_AVC_MAX_GAIN_12DB; + w_avc |= AUD_DSP_WR_AVC_AVC_MAX_GAIN_12DB; break; default: return DRX_STS_INVALID_ARG; } /* avc reference level */ - if (volume->avcRefLevel > AUD_MAX_AVC_REF_LEVEL) { + if (volume->avc_ref_level > AUD_MAX_AVC_REF_LEVEL) { return DRX_STS_INVALID_ARG; } - wAVC &= (u16) ~AUD_DSP_WR_AVC_AVC_REF_LEV__M; - wAVC |= (u16) (volume->avcRefLevel << AUD_DSP_WR_AVC_AVC_REF_LEV__B); + w_avc &= (u16) ~AUD_DSP_WR_AVC_AVC_REF_LEV__M; + w_avc |= (u16) (volume->avc_ref_level << AUD_DSP_WR_AVC_AVC_REF_LEV__B); - WR16(devAddr, AUD_DSP_WR_AVC__A, wAVC); + WR16(dev_addr, AUD_DSP_WR_AVC__A, w_avc); /* all done, store config in data structure */ - extAttr->audData.volume = *volume; + ext_attr->aud_data.volume = *volume; return DRX_STS_OK; rw_error: @@ -10330,37 +10330,37 @@ rw_error: /** * \brief Get the I2S settings * \param demod instance of demodulator -* \param pointer to DRXCfgI2SOutput_t +* \param pointer to drx_cfg_i2s_output_t * \return int. * */ static int -AUDCtrlGetCfgOutputI2S(pDRXDemodInstance_t demod, pDRXCfgI2SOutput_t output) +aud_ctrl_get_cfg_output_i2s(pdrx_demod_instance_t demod, pdrx_cfg_i2s_output_t output) { - struct i2c_device_addr *devAddr = NULL; - pDRXJData_t extAttr = NULL; + struct i2c_device_addr *dev_addr = NULL; + pdrxj_data_t ext_attr = NULL; - u16 wI2SConfig = 0; - u16 rI2SFreq = 0; + u16 w_i2s_config = 0; + u16 r_i2s_freq = 0; if (output == NULL) { return DRX_STS_INVALID_ARG; } - devAddr = (struct i2c_device_addr *) demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; + dev_addr = (struct i2c_device_addr *) demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* power up */ - if (extAttr->audData.audioIsActive == false) { - CHK_ERROR(PowerUpAud(demod, true)); - extAttr->audData.audioIsActive = true; + if (ext_attr->aud_data.audio_is_active == false) { + CHK_ERROR(power_up_aud(demod, true)); + ext_attr->aud_data.audio_is_active = true; } - RR16(devAddr, AUD_DEM_RAM_I2S_CONFIG2__A, &wI2SConfig); - RR16(devAddr, AUD_DSP_WR_I2S_OUT_FS__A, &rI2SFreq); + RR16(dev_addr, AUD_DEM_RAM_I2S_CONFIG2__A, &w_i2s_config); + RR16(dev_addr, AUD_DSP_WR_I2S_OUT_FS__A, &r_i2s_freq); /* I2S mode */ - switch (wI2SConfig & AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__M) { + switch (w_i2s_config & AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__M) { case AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST_MASTER: output->mode = DRX_I2S_MODE_MASTER; break; @@ -10372,7 +10372,7 @@ AUDCtrlGetCfgOutputI2S(pDRXDemodInstance_t demod, pDRXCfgI2SOutput_t output) } /* I2S format */ - switch (wI2SConfig & AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__M) { + switch (w_i2s_config & AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__M) { case AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE_DELAY: output->format = DRX_I2S_FORMAT_WS_ADVANCED; break; @@ -10384,19 +10384,19 @@ AUDCtrlGetCfgOutputI2S(pDRXDemodInstance_t demod, pDRXCfgI2SOutput_t output) } /* I2S word length */ - switch (wI2SConfig & AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__M) { + switch (w_i2s_config & AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__M) { case AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_16: - output->wordLength = DRX_I2S_WORDLENGTH_16; + output->word_length = DRX_I2S_WORDLENGTH_16; break; case AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_32: - output->wordLength = DRX_I2S_WORDLENGTH_32; + output->word_length = DRX_I2S_WORDLENGTH_32; break; default: return DRX_STS_ERROR; } /* I2S polarity */ - switch (wI2SConfig & AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__M) { + switch (w_i2s_config & AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__M) { case AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL_LEFT_HIGH: output->polarity = DRX_I2S_POLARITY_LEFT; break; @@ -10408,16 +10408,16 @@ AUDCtrlGetCfgOutputI2S(pDRXDemodInstance_t demod, pDRXCfgI2SOutput_t output) } /* I2S output enabled */ - if ((wI2SConfig & AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__M) + if ((w_i2s_config & AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__M) == AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_ENABLE) { - output->outputEnable = true; + output->output_enable = true; } else { - output->outputEnable = false; + output->output_enable = false; } - if (rI2SFreq > 0) { - output->frequency = 6144UL * 48000 / rI2SFreq; - if (output->wordLength == DRX_I2S_WORDLENGTH_16) { + if (r_i2s_freq > 0) { + output->frequency = 6144UL * 48000 / r_i2s_freq; + if (output->word_length == DRX_I2S_WORDLENGTH_16) { output->frequency *= 2; } } else { @@ -10433,104 +10433,104 @@ rw_error: /** * \brief Set the I2S settings * \param demod instance of demodulator -* \param pointer to DRXCfgI2SOutput_t +* \param pointer to drx_cfg_i2s_output_t * \return int. * */ static int -AUDCtrlSetCfgOutputI2S(pDRXDemodInstance_t demod, pDRXCfgI2SOutput_t output) +aud_ctrl_set_cfg_output_i2s(pdrx_demod_instance_t demod, pdrx_cfg_i2s_output_t output) { - struct i2c_device_addr *devAddr = NULL; - pDRXJData_t extAttr = NULL; + struct i2c_device_addr *dev_addr = NULL; + pdrxj_data_t ext_attr = NULL; - u16 wI2SConfig = 0; - u16 wI2SPadsDataDa = 0; - u16 wI2SPadsDataCl = 0; - u16 wI2SPadsDataWs = 0; - u32 wI2SFreq = 0; + u16 w_i2s_config = 0; + u16 w_i2s_pads_data_da = 0; + u16 w_i2s_pads_data_cl = 0; + u16 w_i2s_pads_data_ws = 0; + u32 w_i2s_freq = 0; if (output == NULL) { return DRX_STS_INVALID_ARG; } - devAddr = (struct i2c_device_addr *) demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; + dev_addr = (struct i2c_device_addr *) demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* power up */ - if (extAttr->audData.audioIsActive == false) { - CHK_ERROR(PowerUpAud(demod, true)); - extAttr->audData.audioIsActive = true; + if (ext_attr->aud_data.audio_is_active == false) { + CHK_ERROR(power_up_aud(demod, true)); + ext_attr->aud_data.audio_is_active = true; } - RR16(devAddr, AUD_DEM_RAM_I2S_CONFIG2__A, &wI2SConfig); + RR16(dev_addr, AUD_DEM_RAM_I2S_CONFIG2__A, &w_i2s_config); /* I2S mode */ - wI2SConfig &= (u16) ~AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__M; + w_i2s_config &= (u16) ~AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__M; switch (output->mode) { case DRX_I2S_MODE_MASTER: - wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST_MASTER; + w_i2s_config |= AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST_MASTER; break; case DRX_I2S_MODE_SLAVE: - wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST_SLAVE; + w_i2s_config |= AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST_SLAVE; break; default: return DRX_STS_INVALID_ARG; } /* I2S format */ - wI2SConfig &= (u16) ~AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__M; + w_i2s_config &= (u16) ~AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__M; switch (output->format) { case DRX_I2S_FORMAT_WS_ADVANCED: - wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE_DELAY; + w_i2s_config |= AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE_DELAY; break; case DRX_I2S_FORMAT_WS_WITH_DATA: - wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE_NO_DELAY; + w_i2s_config |= AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE_NO_DELAY; break; default: return DRX_STS_INVALID_ARG; } /* I2S word length */ - wI2SConfig &= (u16) ~AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__M; + w_i2s_config &= (u16) ~AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__M; - switch (output->wordLength) { + switch (output->word_length) { case DRX_I2S_WORDLENGTH_16: - wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_16; + w_i2s_config |= AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_16; break; case DRX_I2S_WORDLENGTH_32: - wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_32; + w_i2s_config |= AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_32; break; default: return DRX_STS_INVALID_ARG; } /* I2S polarity */ - wI2SConfig &= (u16) ~AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__M; + w_i2s_config &= (u16) ~AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__M; switch (output->polarity) { case DRX_I2S_POLARITY_LEFT: - wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL_LEFT_HIGH; + w_i2s_config |= AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL_LEFT_HIGH; break; case DRX_I2S_POLARITY_RIGHT: - wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL_LEFT_LOW; + w_i2s_config |= AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL_LEFT_LOW; break; default: return DRX_STS_INVALID_ARG; } /* I2S output enabled */ - wI2SConfig &= (u16) ~AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__M; - if (output->outputEnable == true) { - wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_ENABLE; + w_i2s_config &= (u16) ~AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__M; + if (output->output_enable == true) { + w_i2s_config |= AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_ENABLE; } else { - wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_DISABLE; + w_i2s_config |= AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_DISABLE; } /* I2S frequency - wI2SFreq = 6144 * 48000 * nrbits / ( 32 * frequency ) + w_i2s_freq = 6144 * 48000 * nrbits / ( 32 * frequency ) 16bit: 6144 * 48000 / ( 2 * freq ) = ( 6144 * 48000 / freq ) / 2 32bit: 6144 * 48000 / freq = ( 6144 * 48000 / freq ) @@ -10540,43 +10540,43 @@ AUDCtrlSetCfgOutputI2S(pDRXDemodInstance_t demod, pDRXCfgI2SOutput_t output) return DRX_STS_INVALID_ARG; } - wI2SFreq = (6144UL * 48000UL) + (output->frequency >> 1); - wI2SFreq /= output->frequency; + w_i2s_freq = (6144UL * 48000UL) + (output->frequency >> 1); + w_i2s_freq /= output->frequency; - if (output->wordLength == DRX_I2S_WORDLENGTH_16) { - wI2SFreq *= 2; + if (output->word_length == DRX_I2S_WORDLENGTH_16) { + w_i2s_freq *= 2; } - WR16(devAddr, AUD_DEM_WR_I2S_CONFIG2__A, wI2SConfig); - WR16(devAddr, AUD_DSP_WR_I2S_OUT_FS__A, (u16) wI2SFreq); + WR16(dev_addr, AUD_DEM_WR_I2S_CONFIG2__A, w_i2s_config); + WR16(dev_addr, AUD_DSP_WR_I2S_OUT_FS__A, (u16) w_i2s_freq); /* configure I2S output pads for master or slave mode */ - WR16(devAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); + WR16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); if (output->mode == DRX_I2S_MODE_MASTER) { - wI2SPadsDataDa = SIO_PDR_I2S_DA_CFG_MODE__MASTER | + w_i2s_pads_data_da = SIO_PDR_I2S_DA_CFG_MODE__MASTER | SIO_PDR_I2S_DA_CFG_DRIVE__MASTER; - wI2SPadsDataCl = SIO_PDR_I2S_CL_CFG_MODE__MASTER | + w_i2s_pads_data_cl = SIO_PDR_I2S_CL_CFG_MODE__MASTER | SIO_PDR_I2S_CL_CFG_DRIVE__MASTER; - wI2SPadsDataWs = SIO_PDR_I2S_WS_CFG_MODE__MASTER | + w_i2s_pads_data_ws = SIO_PDR_I2S_WS_CFG_MODE__MASTER | SIO_PDR_I2S_WS_CFG_DRIVE__MASTER; } else { - wI2SPadsDataDa = SIO_PDR_I2S_DA_CFG_MODE__SLAVE | + w_i2s_pads_data_da = SIO_PDR_I2S_DA_CFG_MODE__SLAVE | SIO_PDR_I2S_DA_CFG_DRIVE__SLAVE; - wI2SPadsDataCl = SIO_PDR_I2S_CL_CFG_MODE__SLAVE | + w_i2s_pads_data_cl = SIO_PDR_I2S_CL_CFG_MODE__SLAVE | SIO_PDR_I2S_CL_CFG_DRIVE__SLAVE; - wI2SPadsDataWs = SIO_PDR_I2S_WS_CFG_MODE__SLAVE | + w_i2s_pads_data_ws = SIO_PDR_I2S_WS_CFG_MODE__SLAVE | SIO_PDR_I2S_WS_CFG_DRIVE__SLAVE; } - WR16(devAddr, SIO_PDR_I2S_DA_CFG__A, wI2SPadsDataDa); - WR16(devAddr, SIO_PDR_I2S_CL_CFG__A, wI2SPadsDataCl); - WR16(devAddr, SIO_PDR_I2S_WS_CFG__A, wI2SPadsDataWs); + WR16(dev_addr, SIO_PDR_I2S_DA_CFG__A, w_i2s_pads_data_da); + WR16(dev_addr, SIO_PDR_I2S_CL_CFG__A, w_i2s_pads_data_cl); + WR16(dev_addr, SIO_PDR_I2S_WS_CFG__A, w_i2s_pads_data_ws); - WR16(devAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE); + WR16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE); /* all done, store config in data structure */ - extAttr->audData.i2sdata = *output; + ext_attr->aud_data.i2sdata = *output; return DRX_STS_OK; rw_error: @@ -10593,42 +10593,42 @@ rw_error: * */ static int -AUDCtrlGetCfgAutoSound(pDRXDemodInstance_t demod, - pDRXCfgAudAutoSound_t autoSound) +aud_ctrl_get_cfg_auto_sound(pdrx_demod_instance_t demod, + pdrx_cfg_aud_auto_sound_t auto_sound) { - struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; - pDRXJData_t extAttr = (pDRXJData_t) NULL; + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) NULL; + pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; - u16 rModus = 0; + u16 r_modus = 0; - if (autoSound == NULL) { + if (auto_sound == NULL) { return DRX_STS_INVALID_ARG; } - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* power up */ - if (extAttr->audData.audioIsActive == false) { - CHK_ERROR(PowerUpAud(demod, true)); - extAttr->audData.audioIsActive = true; + if (ext_attr->aud_data.audio_is_active == false) { + CHK_ERROR(power_up_aud(demod, true)); + ext_attr->aud_data.audio_is_active = true; } - CHK_ERROR(AUDGetModus(demod, &rModus)); + CHK_ERROR(aud_get_modus(demod, &r_modus)); - switch (rModus & (AUD_DEM_WR_MODUS_MOD_ASS__M | + switch (r_modus & (AUD_DEM_WR_MODUS_MOD_ASS__M | AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__M)) { case AUD_DEM_WR_MODUS_MOD_ASS_OFF | AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_DISABLED: case AUD_DEM_WR_MODUS_MOD_ASS_OFF | AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_ENABLED: - *autoSound = + *auto_sound = DRX_AUD_AUTO_SOUND_OFF; break; case AUD_DEM_WR_MODUS_MOD_ASS_ON | AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_ENABLED: - *autoSound = + *auto_sound = DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON; break; case AUD_DEM_WR_MODUS_MOD_ASS_ON | AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_DISABLED: - *autoSound = + *auto_sound = DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_OFF; break; default: @@ -10650,57 +10650,57 @@ rw_error: * */ static int -AUDCtrSetlCfgAutoSound(pDRXDemodInstance_t demod, - pDRXCfgAudAutoSound_t autoSound) +aud_ctr_setl_cfg_auto_sound(pdrx_demod_instance_t demod, + pdrx_cfg_aud_auto_sound_t auto_sound) { - struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; - pDRXJData_t extAttr = (pDRXJData_t) NULL; + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) NULL; + pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; - u16 rModus = 0; - u16 wModus = 0; + u16 r_modus = 0; + u16 w_modus = 0; - if (autoSound == NULL) { + if (auto_sound == NULL) { return DRX_STS_INVALID_ARG; } - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* power up */ - if (extAttr->audData.audioIsActive == false) { - CHK_ERROR(PowerUpAud(demod, true)); - extAttr->audData.audioIsActive = true; + if (ext_attr->aud_data.audio_is_active == false) { + CHK_ERROR(power_up_aud(demod, true)); + ext_attr->aud_data.audio_is_active = true; } - CHK_ERROR(AUDGetModus(demod, &rModus)); + CHK_ERROR(aud_get_modus(demod, &r_modus)); - wModus = rModus; + w_modus = r_modus; /* clear ASS & ASC bits */ - wModus &= (u16) ~AUD_DEM_WR_MODUS_MOD_ASS__M; - wModus &= (u16) ~AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__M; + w_modus &= (u16) ~AUD_DEM_WR_MODUS_MOD_ASS__M; + w_modus &= (u16) ~AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__M; - switch (*autoSound) { + switch (*auto_sound) { case DRX_AUD_AUTO_SOUND_OFF: - wModus |= AUD_DEM_WR_MODUS_MOD_ASS_OFF; - wModus |= AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_DISABLED; + w_modus |= AUD_DEM_WR_MODUS_MOD_ASS_OFF; + w_modus |= AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_DISABLED; break; case DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON: - wModus |= AUD_DEM_WR_MODUS_MOD_ASS_ON; - wModus |= AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_ENABLED; + w_modus |= AUD_DEM_WR_MODUS_MOD_ASS_ON; + w_modus |= AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_ENABLED; break; case DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_OFF: - wModus |= AUD_DEM_WR_MODUS_MOD_ASS_ON; - wModus |= AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_DISABLED; + w_modus |= AUD_DEM_WR_MODUS_MOD_ASS_ON; + w_modus |= AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_DISABLED; break; default: return DRX_STS_INVALID_ARG; } - if (wModus != rModus) { - WR16(devAddr, AUD_DEM_WR_MODUS__A, wModus); + if (w_modus != r_modus) { + WR16(dev_addr, AUD_DEM_WR_MODUS__A, w_modus); } /* copy to data structure */ - extAttr->audData.autoSound = *autoSound; + ext_attr->aud_data.auto_sound = *auto_sound; return DRX_STS_OK; rw_error: @@ -10716,35 +10716,35 @@ rw_error: * */ static int -AUDCtrlGetCfgASSThres(pDRXDemodInstance_t demod, pDRXCfgAudASSThres_t thres) +aud_ctrl_get_cfg_ass_thres(pdrx_demod_instance_t demod, pdrx_cfg_aud_ass_thres_t thres) { - struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; - pDRXJData_t extAttr = (pDRXJData_t) NULL; + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) NULL; + pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; - u16 thresA2 = 0; - u16 thresBtsc = 0; - u16 thresNicam = 0; + u16 thres_a2 = 0; + u16 thres_btsc = 0; + u16 thres_nicam = 0; if (thres == NULL) { return DRX_STS_INVALID_ARG; } - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* power up */ - if (extAttr->audData.audioIsActive == false) { - CHK_ERROR(PowerUpAud(demod, true)); - extAttr->audData.audioIsActive = true; + if (ext_attr->aud_data.audio_is_active == false) { + CHK_ERROR(power_up_aud(demod, true)); + ext_attr->aud_data.audio_is_active = true; } - RR16(devAddr, AUD_DEM_RAM_A2_THRSHLD__A, &thresA2); - RR16(devAddr, AUD_DEM_RAM_BTSC_THRSHLD__A, &thresBtsc); - RR16(devAddr, AUD_DEM_RAM_NICAM_THRSHLD__A, &thresNicam); + RR16(dev_addr, AUD_DEM_RAM_A2_THRSHLD__A, &thres_a2); + RR16(dev_addr, AUD_DEM_RAM_BTSC_THRSHLD__A, &thres_btsc); + RR16(dev_addr, AUD_DEM_RAM_NICAM_THRSHLD__A, &thres_nicam); - thres->a2 = thresA2; - thres->btsc = thresBtsc; - thres->nicam = thresNicam; + thres->a2 = thres_a2; + thres->btsc = thres_btsc; + thres->nicam = thres_nicam; return DRX_STS_OK; rw_error: @@ -10760,30 +10760,30 @@ rw_error: * */ static int -AUDCtrlSetCfgASSThres(pDRXDemodInstance_t demod, pDRXCfgAudASSThres_t thres) +aud_ctrl_set_cfg_ass_thres(pdrx_demod_instance_t demod, pdrx_cfg_aud_ass_thres_t thres) { - struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; - pDRXJData_t extAttr = (pDRXJData_t) NULL; + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) NULL; + pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; if (thres == NULL) { return DRX_STS_INVALID_ARG; } - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* power up */ - if (extAttr->audData.audioIsActive == false) { - CHK_ERROR(PowerUpAud(demod, true)); - extAttr->audData.audioIsActive = true; + if (ext_attr->aud_data.audio_is_active == false) { + CHK_ERROR(power_up_aud(demod, true)); + ext_attr->aud_data.audio_is_active = true; } - WR16(devAddr, AUD_DEM_WR_A2_THRSHLD__A, thres->a2); - WR16(devAddr, AUD_DEM_WR_BTSC_THRSHLD__A, thres->btsc); - WR16(devAddr, AUD_DEM_WR_NICAM_THRSHLD__A, thres->nicam); + WR16(dev_addr, AUD_DEM_WR_A2_THRSHLD__A, thres->a2); + WR16(dev_addr, AUD_DEM_WR_BTSC_THRSHLD__A, thres->btsc); + WR16(dev_addr, AUD_DEM_WR_NICAM_THRSHLD__A, thres->nicam); /* update DRXK data structure with hardware values */ - extAttr->audData.assThresholds = *thres; + ext_attr->aud_data.ass_thresholds = *thres; return DRX_STS_OK; rw_error: @@ -10794,49 +10794,49 @@ rw_error: /** * \brief Get Audio Carrier settings * \param demod instance of demodulator -* \param pointer to pDRXAudCarrier_t +* \param pointer to pdrx_aud_carrier_t * \return int. * */ static int -AUDCtrlGetCfgCarrier(pDRXDemodInstance_t demod, pDRXCfgAudCarriers_t carriers) +aud_ctrl_get_cfg_carrier(pdrx_demod_instance_t demod, pdrx_cfg_aud_carriers_t carriers) { - struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; - pDRXJData_t extAttr = (pDRXJData_t) NULL; + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) NULL; + pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; - u16 wModus = 0; + u16 w_modus = 0; - u16 dcoAHi = 0; - u16 dcoALo = 0; - u16 dcoBHi = 0; - u16 dcoBLo = 0; + u16 dco_a_hi = 0; + u16 dco_a_lo = 0; + u16 dco_b_hi = 0; + u16 dco_b_lo = 0; u32 valA = 0; u32 valB = 0; - u16 dcLvlA = 0; - u16 dcLvlB = 0; + u16 dc_lvl_a = 0; + u16 dc_lvl_b = 0; - u16 cmThesA = 0; - u16 cmThesB = 0; + u16 cm_thes_a = 0; + u16 cm_thes_b = 0; if (carriers == NULL) { return DRX_STS_INVALID_ARG; } - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* power up */ - if (extAttr->audData.audioIsActive == false) { - CHK_ERROR(PowerUpAud(demod, true)); - extAttr->audData.audioIsActive = true; + if (ext_attr->aud_data.audio_is_active == false) { + CHK_ERROR(power_up_aud(demod, true)); + ext_attr->aud_data.audio_is_active = true; } - CHK_ERROR(AUDGetModus(demod, &wModus)); + CHK_ERROR(aud_get_modus(demod, &w_modus)); /* Behaviour of primary audio channel */ - switch (wModus & (AUD_DEM_WR_MODUS_MOD_CM_A__M)) { + switch (w_modus & (AUD_DEM_WR_MODUS_MOD_CM_A__M)) { case AUD_DEM_WR_MODUS_MOD_CM_A_MUTE: carriers->a.opt = DRX_NO_CARRIER_MUTE; break; @@ -10849,7 +10849,7 @@ AUDCtrlGetCfgCarrier(pDRXDemodInstance_t demod, pDRXCfgAudCarriers_t carriers) } /* Behaviour of secondary audio channel */ - switch (wModus & (AUD_DEM_WR_MODUS_MOD_CM_B__M)) { + switch (w_modus & (AUD_DEM_WR_MODUS_MOD_CM_B__M)) { case AUD_DEM_WR_MODUS_MOD_CM_B_MUTE: carriers->b.opt = DRX_NO_CARRIER_MUTE; break; @@ -10862,13 +10862,13 @@ AUDCtrlGetCfgCarrier(pDRXDemodInstance_t demod, pDRXCfgAudCarriers_t carriers) } /* frequency adjustment for primary & secondary audio channel */ - RR16(devAddr, AUD_DEM_RAM_DCO_A_HI__A, &dcoAHi); - RR16(devAddr, AUD_DEM_RAM_DCO_A_LO__A, &dcoALo); - RR16(devAddr, AUD_DEM_RAM_DCO_B_HI__A, &dcoBHi); - RR16(devAddr, AUD_DEM_RAM_DCO_B_LO__A, &dcoBLo); + RR16(dev_addr, AUD_DEM_RAM_DCO_A_HI__A, &dco_a_hi); + RR16(dev_addr, AUD_DEM_RAM_DCO_A_LO__A, &dco_a_lo); + RR16(dev_addr, AUD_DEM_RAM_DCO_B_HI__A, &dco_b_hi); + RR16(dev_addr, AUD_DEM_RAM_DCO_B_LO__A, &dco_b_lo); - valA = (((u32) dcoAHi) << 12) | ((u32) dcoALo & 0xFFF); - valB = (((u32) dcoBHi) << 12) | ((u32) dcoBLo & 0xFFF); + valA = (((u32) dco_a_hi) << 12) | ((u32) dco_a_lo & 0xFFF); + valB = (((u32) dco_b_hi) << 12) | ((u32) dco_b_lo & 0xFFF); /* Multiply by 20250 * 1>>24 ~= 2 / 1657 */ carriers->a.dco = DRX_S24TODRXFREQ(valA) * 2L / 1657L; @@ -10876,19 +10876,19 @@ AUDCtrlGetCfgCarrier(pDRXDemodInstance_t demod, pDRXCfgAudCarriers_t carriers) /* DC level of the incoming FM signal on the primary & seconday sound channel */ - RR16(devAddr, AUD_DSP_RD_FM_DC_LEVEL_A__A, &dcLvlA); - RR16(devAddr, AUD_DSP_RD_FM_DC_LEVEL_B__A, &dcLvlB); + RR16(dev_addr, AUD_DSP_RD_FM_DC_LEVEL_A__A, &dc_lvl_a); + RR16(dev_addr, AUD_DSP_RD_FM_DC_LEVEL_B__A, &dc_lvl_b); /* offset (kHz) = (dcLvl / 322) */ - carriers->a.shift = (DRX_U16TODRXFREQ(dcLvlA) / 322L); - carriers->b.shift = (DRX_U16TODRXFREQ(dcLvlB) / 322L); + carriers->a.shift = (DRX_U16TODRXFREQ(dc_lvl_a) / 322L); + carriers->b.shift = (DRX_U16TODRXFREQ(dc_lvl_b) / 322L); /* Carrier detetcion threshold for primary & secondary channel */ - RR16(devAddr, AUD_DEM_RAM_CM_A_THRSHLD__A, &cmThesA); - RR16(devAddr, AUD_DEM_RAM_CM_B_THRSHLD__A, &cmThesB); + RR16(dev_addr, AUD_DEM_RAM_CM_A_THRSHLD__A, &cm_thes_a); + RR16(dev_addr, AUD_DEM_RAM_CM_B_THRSHLD__A, &cm_thes_b); - carriers->a.thres = cmThesA; - carriers->b.thres = cmThesB; + carriers->a.thres = cm_thes_a; + carriers->b.thres = cm_thes_b; return DRX_STS_OK; rw_error: @@ -10899,23 +10899,23 @@ rw_error: /** * \brief Set Audio Carrier settings * \param demod instance of demodulator -* \param pointer to pDRXAudCarrier_t +* \param pointer to pdrx_aud_carrier_t * \return int. * */ static int -AUDCtrlSetCfgCarrier(pDRXDemodInstance_t demod, pDRXCfgAudCarriers_t carriers) +aud_ctrl_set_cfg_carrier(pdrx_demod_instance_t demod, pdrx_cfg_aud_carriers_t carriers) { - struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; - pDRXJData_t extAttr = (pDRXJData_t) NULL; + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) NULL; + pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; - u16 wModus = 0; - u16 rModus = 0; + u16 w_modus = 0; + u16 r_modus = 0; - u16 dcoAHi = 0; - u16 dcoALo = 0; - u16 dcoBHi = 0; - u16 dcoBLo = 0; + u16 dco_a_hi = 0; + u16 dco_a_lo = 0; + u16 dco_b_hi = 0; + u16 dco_b_lo = 0; s32 valA = 0; s32 valB = 0; @@ -10924,26 +10924,26 @@ AUDCtrlSetCfgCarrier(pDRXDemodInstance_t demod, pDRXCfgAudCarriers_t carriers) return DRX_STS_INVALID_ARG; } - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* power up */ - if (extAttr->audData.audioIsActive == false) { - CHK_ERROR(PowerUpAud(demod, true)); - extAttr->audData.audioIsActive = true; + if (ext_attr->aud_data.audio_is_active == false) { + CHK_ERROR(power_up_aud(demod, true)); + ext_attr->aud_data.audio_is_active = true; } - CHK_ERROR(AUDGetModus(demod, &rModus)); + CHK_ERROR(aud_get_modus(demod, &r_modus)); - wModus = rModus; - wModus &= (u16) ~AUD_DEM_WR_MODUS_MOD_CM_A__M; + w_modus = r_modus; + w_modus &= (u16) ~AUD_DEM_WR_MODUS_MOD_CM_A__M; /* Behaviour of primary audio channel */ switch (carriers->a.opt) { case DRX_NO_CARRIER_MUTE: - wModus |= AUD_DEM_WR_MODUS_MOD_CM_A_MUTE; + w_modus |= AUD_DEM_WR_MODUS_MOD_CM_A_MUTE; break; case DRX_NO_CARRIER_NOISE: - wModus |= AUD_DEM_WR_MODUS_MOD_CM_A_NOISE; + w_modus |= AUD_DEM_WR_MODUS_MOD_CM_A_NOISE; break; default: return DRX_STS_INVALID_ARG; @@ -10951,13 +10951,13 @@ AUDCtrlSetCfgCarrier(pDRXDemodInstance_t demod, pDRXCfgAudCarriers_t carriers) } /* Behaviour of secondary audio channel */ - wModus &= (u16) ~AUD_DEM_WR_MODUS_MOD_CM_B__M; + w_modus &= (u16) ~AUD_DEM_WR_MODUS_MOD_CM_B__M; switch (carriers->b.opt) { case DRX_NO_CARRIER_MUTE: - wModus |= AUD_DEM_WR_MODUS_MOD_CM_B_MUTE; + w_modus |= AUD_DEM_WR_MODUS_MOD_CM_B_MUTE; break; case DRX_NO_CARRIER_NOISE: - wModus |= AUD_DEM_WR_MODUS_MOD_CM_B_NOISE; + w_modus |= AUD_DEM_WR_MODUS_MOD_CM_B_NOISE; break; default: return DRX_STS_INVALID_ARG; @@ -10965,30 +10965,30 @@ AUDCtrlSetCfgCarrier(pDRXDemodInstance_t demod, pDRXCfgAudCarriers_t carriers) } /* now update the modus register */ - if (wModus != rModus) { - WR16(devAddr, AUD_DEM_WR_MODUS__A, wModus); + if (w_modus != r_modus) { + WR16(dev_addr, AUD_DEM_WR_MODUS__A, w_modus); } /* frequency adjustment for primary & secondary audio channel */ valA = (s32) ((carriers->a.dco) * 1657L / 2); valB = (s32) ((carriers->b.dco) * 1657L / 2); - dcoAHi = (u16) ((valA >> 12) & 0xFFF); - dcoALo = (u16) (valA & 0xFFF); - dcoBHi = (u16) ((valB >> 12) & 0xFFF); - dcoBLo = (u16) (valB & 0xFFF); + dco_a_hi = (u16) ((valA >> 12) & 0xFFF); + dco_a_lo = (u16) (valA & 0xFFF); + dco_b_hi = (u16) ((valB >> 12) & 0xFFF); + dco_b_lo = (u16) (valB & 0xFFF); - WR16(devAddr, AUD_DEM_WR_DCO_A_HI__A, dcoAHi); - WR16(devAddr, AUD_DEM_WR_DCO_A_LO__A, dcoALo); - WR16(devAddr, AUD_DEM_WR_DCO_B_HI__A, dcoBHi); - WR16(devAddr, AUD_DEM_WR_DCO_B_LO__A, dcoBLo); + WR16(dev_addr, AUD_DEM_WR_DCO_A_HI__A, dco_a_hi); + WR16(dev_addr, AUD_DEM_WR_DCO_A_LO__A, dco_a_lo); + WR16(dev_addr, AUD_DEM_WR_DCO_B_HI__A, dco_b_hi); + WR16(dev_addr, AUD_DEM_WR_DCO_B_LO__A, dco_b_lo); /* Carrier detetcion threshold for primary & secondary channel */ - WR16(devAddr, AUD_DEM_WR_CM_A_THRSHLD__A, carriers->a.thres); - WR16(devAddr, AUD_DEM_WR_CM_B_THRSHLD__A, carriers->b.thres); + WR16(dev_addr, AUD_DEM_WR_CM_A_THRSHLD__A, carriers->a.thres); + WR16(dev_addr, AUD_DEM_WR_CM_B_THRSHLD__A, carriers->b.thres); /* update DRXK data structure */ - extAttr->audData.carriers = *carriers; + ext_attr->aud_data.carriers = *carriers; return DRX_STS_OK; rw_error: @@ -11004,82 +11004,82 @@ rw_error: * */ static int -AUDCtrlGetCfgMixer(pDRXDemodInstance_t demod, pDRXCfgAudMixer_t mixer) +aud_ctrl_get_cfg_mixer(pdrx_demod_instance_t demod, pdrx_cfg_aud_mixer_t mixer) { - struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; - pDRXJData_t extAttr = (pDRXJData_t) NULL; + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) NULL; + pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; - u16 srcI2SMatr = 0; - u16 fmMatr = 0; + u16 src_i2s_matr = 0; + u16 fm_matr = 0; if (mixer == NULL) { return DRX_STS_INVALID_ARG; } - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* power up */ - if (extAttr->audData.audioIsActive == false) { - CHK_ERROR(PowerUpAud(demod, true)); - extAttr->audData.audioIsActive = true; + if (ext_attr->aud_data.audio_is_active == false) { + CHK_ERROR(power_up_aud(demod, true)); + ext_attr->aud_data.audio_is_active = true; } /* Source Selctor */ - RR16(devAddr, AUD_DSP_WR_SRC_I2S_MATR__A, &srcI2SMatr); + RR16(dev_addr, AUD_DSP_WR_SRC_I2S_MATR__A, &src_i2s_matr); - switch (srcI2SMatr & AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__M) { + switch (src_i2s_matr & AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__M) { case AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_MONO: - mixer->sourceI2S = DRX_AUD_SRC_MONO; + mixer->source_i2s = DRX_AUD_SRC_MONO; break; case AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_AB: - mixer->sourceI2S = DRX_AUD_SRC_STEREO_OR_AB; + mixer->source_i2s = DRX_AUD_SRC_STEREO_OR_AB; break; case AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_A: - mixer->sourceI2S = DRX_AUD_SRC_STEREO_OR_A; + mixer->source_i2s = DRX_AUD_SRC_STEREO_OR_A; break; case AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_B: - mixer->sourceI2S = DRX_AUD_SRC_STEREO_OR_B; + mixer->source_i2s = DRX_AUD_SRC_STEREO_OR_B; break; default: return DRX_STS_ERROR; } /* Matrix */ - switch (srcI2SMatr & AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__M) { + switch (src_i2s_matr & AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__M) { case AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_MONO: - mixer->matrixI2S = DRX_AUD_I2S_MATRIX_MONO; + mixer->matrix_i2s = DRX_AUD_I2S_MATRIX_MONO; break; case AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_STEREO: - mixer->matrixI2S = DRX_AUD_I2S_MATRIX_STEREO; + mixer->matrix_i2s = DRX_AUD_I2S_MATRIX_STEREO; break; case AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_SOUND_A: - mixer->matrixI2S = DRX_AUD_I2S_MATRIX_A_MONO; + mixer->matrix_i2s = DRX_AUD_I2S_MATRIX_A_MONO; break; case AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_SOUND_B: - mixer->matrixI2S = DRX_AUD_I2S_MATRIX_B_MONO; + mixer->matrix_i2s = DRX_AUD_I2S_MATRIX_B_MONO; break; default: return DRX_STS_ERROR; } /* FM Matrix */ - RR16(devAddr, AUD_DEM_WR_FM_MATRIX__A, &fmMatr); - switch (fmMatr & AUD_DEM_WR_FM_MATRIX__M) { + RR16(dev_addr, AUD_DEM_WR_FM_MATRIX__A, &fm_matr); + switch (fm_matr & AUD_DEM_WR_FM_MATRIX__M) { case AUD_DEM_WR_FM_MATRIX_NO_MATRIX: - mixer->matrixFm = DRX_AUD_FM_MATRIX_NO_MATRIX; + mixer->matrix_fm = DRX_AUD_FM_MATRIX_NO_MATRIX; break; case AUD_DEM_WR_FM_MATRIX_GERMAN_MATRIX: - mixer->matrixFm = DRX_AUD_FM_MATRIX_GERMAN; + mixer->matrix_fm = DRX_AUD_FM_MATRIX_GERMAN; break; case AUD_DEM_WR_FM_MATRIX_KOREAN_MATRIX: - mixer->matrixFm = DRX_AUD_FM_MATRIX_KOREAN; + mixer->matrix_fm = DRX_AUD_FM_MATRIX_KOREAN; break; case AUD_DEM_WR_FM_MATRIX_SOUND_A: - mixer->matrixFm = DRX_AUD_FM_MATRIX_SOUND_A; + mixer->matrix_fm = DRX_AUD_FM_MATRIX_SOUND_A; break; case AUD_DEM_WR_FM_MATRIX_SOUND_B: - mixer->matrixFm = DRX_AUD_FM_MATRIX_SOUND_B; + mixer->matrix_fm = DRX_AUD_FM_MATRIX_SOUND_B; break; default: return DRX_STS_ERROR; @@ -11099,99 +11099,99 @@ rw_error: * */ static int -AUDCtrlSetCfgMixer(pDRXDemodInstance_t demod, pDRXCfgAudMixer_t mixer) +aud_ctrl_set_cfg_mixer(pdrx_demod_instance_t demod, pdrx_cfg_aud_mixer_t mixer) { - struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; - pDRXJData_t extAttr = (pDRXJData_t) NULL; + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) NULL; + pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; - u16 srcI2SMatr = 0; - u16 fmMatr = 0; + u16 src_i2s_matr = 0; + u16 fm_matr = 0; if (mixer == NULL) { return DRX_STS_INVALID_ARG; } - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* power up */ - if (extAttr->audData.audioIsActive == false) { - CHK_ERROR(PowerUpAud(demod, true)); - extAttr->audData.audioIsActive = true; + if (ext_attr->aud_data.audio_is_active == false) { + CHK_ERROR(power_up_aud(demod, true)); + ext_attr->aud_data.audio_is_active = true; } /* Source Selctor */ - RR16(devAddr, AUD_DSP_WR_SRC_I2S_MATR__A, &srcI2SMatr); - srcI2SMatr &= (u16) ~AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__M; + RR16(dev_addr, AUD_DSP_WR_SRC_I2S_MATR__A, &src_i2s_matr); + src_i2s_matr &= (u16) ~AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__M; - switch (mixer->sourceI2S) { + switch (mixer->source_i2s) { case DRX_AUD_SRC_MONO: - srcI2SMatr |= AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_MONO; + src_i2s_matr |= AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_MONO; break; case DRX_AUD_SRC_STEREO_OR_AB: - srcI2SMatr |= AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_AB; + src_i2s_matr |= AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_AB; break; case DRX_AUD_SRC_STEREO_OR_A: - srcI2SMatr |= AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_A; + src_i2s_matr |= AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_A; break; case DRX_AUD_SRC_STEREO_OR_B: - srcI2SMatr |= AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_B; + src_i2s_matr |= AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_B; break; default: return DRX_STS_INVALID_ARG; } /* Matrix */ - srcI2SMatr &= (u16) ~AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__M; - switch (mixer->matrixI2S) { + src_i2s_matr &= (u16) ~AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__M; + switch (mixer->matrix_i2s) { case DRX_AUD_I2S_MATRIX_MONO: - srcI2SMatr |= AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_MONO; + src_i2s_matr |= AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_MONO; break; case DRX_AUD_I2S_MATRIX_STEREO: - srcI2SMatr |= AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_STEREO; + src_i2s_matr |= AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_STEREO; break; case DRX_AUD_I2S_MATRIX_A_MONO: - srcI2SMatr |= AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_SOUND_A; + src_i2s_matr |= AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_SOUND_A; break; case DRX_AUD_I2S_MATRIX_B_MONO: - srcI2SMatr |= AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_SOUND_B; + src_i2s_matr |= AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_SOUND_B; break; default: return DRX_STS_INVALID_ARG; } /* write the result */ - WR16(devAddr, AUD_DSP_WR_SRC_I2S_MATR__A, srcI2SMatr); + WR16(dev_addr, AUD_DSP_WR_SRC_I2S_MATR__A, src_i2s_matr); /* FM Matrix */ - RR16(devAddr, AUD_DEM_WR_FM_MATRIX__A, &fmMatr); - fmMatr &= (u16) ~AUD_DEM_WR_FM_MATRIX__M; - switch (mixer->matrixFm) { + RR16(dev_addr, AUD_DEM_WR_FM_MATRIX__A, &fm_matr); + fm_matr &= (u16) ~AUD_DEM_WR_FM_MATRIX__M; + switch (mixer->matrix_fm) { case DRX_AUD_FM_MATRIX_NO_MATRIX: - fmMatr |= AUD_DEM_WR_FM_MATRIX_NO_MATRIX; + fm_matr |= AUD_DEM_WR_FM_MATRIX_NO_MATRIX; break; case DRX_AUD_FM_MATRIX_GERMAN: - fmMatr |= AUD_DEM_WR_FM_MATRIX_GERMAN_MATRIX; + fm_matr |= AUD_DEM_WR_FM_MATRIX_GERMAN_MATRIX; break; case DRX_AUD_FM_MATRIX_KOREAN: - fmMatr |= AUD_DEM_WR_FM_MATRIX_KOREAN_MATRIX; + fm_matr |= AUD_DEM_WR_FM_MATRIX_KOREAN_MATRIX; break; case DRX_AUD_FM_MATRIX_SOUND_A: - fmMatr |= AUD_DEM_WR_FM_MATRIX_SOUND_A; + fm_matr |= AUD_DEM_WR_FM_MATRIX_SOUND_A; break; case DRX_AUD_FM_MATRIX_SOUND_B: - fmMatr |= AUD_DEM_WR_FM_MATRIX_SOUND_B; + fm_matr |= AUD_DEM_WR_FM_MATRIX_SOUND_B; break; default: return DRX_STS_INVALID_ARG; } /* Only write if ASS is off */ - if (extAttr->audData.autoSound == DRX_AUD_AUTO_SOUND_OFF) { - WR16(devAddr, AUD_DEM_WR_FM_MATRIX__A, fmMatr); + if (ext_attr->aud_data.auto_sound == DRX_AUD_AUTO_SOUND_OFF) { + WR16(dev_addr, AUD_DEM_WR_FM_MATRIX__A, fm_matr); } /* update the data structure with hardware state */ - extAttr->audData.mixer = *mixer; + ext_attr->aud_data.mixer = *mixer; return DRX_STS_OK; rw_error: @@ -11207,48 +11207,48 @@ rw_error: * */ static int -AUDCtrlSetCfgAVSync(pDRXDemodInstance_t demod, pDRXCfgAudAVSync_t avSync) +aud_ctrl_set_cfg_av_sync(pdrx_demod_instance_t demod, pdrx_cfg_aud_av_sync_t av_sync) { - struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; - pDRXJData_t extAttr = (pDRXJData_t) NULL; + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) NULL; + pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; - u16 wAudVidSync = 0; + u16 w_aud_vid_sync = 0; - if (avSync == NULL) { + if (av_sync == NULL) { return DRX_STS_INVALID_ARG; } - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* power up */ - if (extAttr->audData.audioIsActive == false) { - CHK_ERROR(PowerUpAud(demod, true)); - extAttr->audData.audioIsActive = true; + if (ext_attr->aud_data.audio_is_active == false) { + CHK_ERROR(power_up_aud(demod, true)); + ext_attr->aud_data.audio_is_active = true; } /* audio/video synchronisation */ - RR16(devAddr, AUD_DSP_WR_AV_SYNC__A, &wAudVidSync); + RR16(dev_addr, AUD_DSP_WR_AV_SYNC__A, &w_aud_vid_sync); - wAudVidSync &= (u16) ~AUD_DSP_WR_AV_SYNC_AV_ON__M; + w_aud_vid_sync &= (u16) ~AUD_DSP_WR_AV_SYNC_AV_ON__M; - if (*avSync == DRX_AUD_AVSYNC_OFF) { - wAudVidSync |= AUD_DSP_WR_AV_SYNC_AV_ON_DISABLE; + if (*av_sync == DRX_AUD_AVSYNC_OFF) { + w_aud_vid_sync |= AUD_DSP_WR_AV_SYNC_AV_ON_DISABLE; } else { - wAudVidSync |= AUD_DSP_WR_AV_SYNC_AV_ON_ENABLE; + w_aud_vid_sync |= AUD_DSP_WR_AV_SYNC_AV_ON_ENABLE; } - wAudVidSync &= (u16) ~AUD_DSP_WR_AV_SYNC_AV_STD_SEL__M; + w_aud_vid_sync &= (u16) ~AUD_DSP_WR_AV_SYNC_AV_STD_SEL__M; - switch (*avSync) { + switch (*av_sync) { case DRX_AUD_AVSYNC_NTSC: - wAudVidSync |= AUD_DSP_WR_AV_SYNC_AV_STD_SEL_NTSC; + w_aud_vid_sync |= AUD_DSP_WR_AV_SYNC_AV_STD_SEL_NTSC; break; case DRX_AUD_AVSYNC_MONOCHROME: - wAudVidSync |= AUD_DSP_WR_AV_SYNC_AV_STD_SEL_MONOCHROME; + w_aud_vid_sync |= AUD_DSP_WR_AV_SYNC_AV_STD_SEL_MONOCHROME; break; case DRX_AUD_AVSYNC_PAL_SECAM: - wAudVidSync |= AUD_DSP_WR_AV_SYNC_AV_STD_SEL_PAL_SECAM; + w_aud_vid_sync |= AUD_DSP_WR_AV_SYNC_AV_STD_SEL_PAL_SECAM; break; case DRX_AUD_AVSYNC_OFF: /* OK */ @@ -11257,7 +11257,7 @@ AUDCtrlSetCfgAVSync(pDRXDemodInstance_t demod, pDRXCfgAudAVSync_t avSync) return DRX_STS_INVALID_ARG; } - WR16(devAddr, AUD_DSP_WR_AV_SYNC__A, wAudVidSync); + WR16(dev_addr, AUD_DSP_WR_AV_SYNC__A, w_aud_vid_sync); return DRX_STS_OK; rw_error: return DRX_STS_ERROR; @@ -11272,44 +11272,44 @@ rw_error: * */ static int -AUDCtrlGetCfgAVSync(pDRXDemodInstance_t demod, pDRXCfgAudAVSync_t avSync) +aud_ctrl_get_cfg_av_sync(pdrx_demod_instance_t demod, pdrx_cfg_aud_av_sync_t av_sync) { - struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; - pDRXJData_t extAttr = (pDRXJData_t) NULL; + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) NULL; + pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; - u16 wAudVidSync = 0; + u16 w_aud_vid_sync = 0; - if (avSync == NULL) { + if (av_sync == NULL) { return DRX_STS_INVALID_ARG; } - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* power up */ - if (extAttr->audData.audioIsActive == false) { - CHK_ERROR(PowerUpAud(demod, true)); - extAttr->audData.audioIsActive = true; + if (ext_attr->aud_data.audio_is_active == false) { + CHK_ERROR(power_up_aud(demod, true)); + ext_attr->aud_data.audio_is_active = true; } /* audio/video synchronisation */ - RR16(devAddr, AUD_DSP_WR_AV_SYNC__A, &wAudVidSync); + RR16(dev_addr, AUD_DSP_WR_AV_SYNC__A, &w_aud_vid_sync); - if ((wAudVidSync & AUD_DSP_WR_AV_SYNC_AV_ON__M) == + if ((w_aud_vid_sync & AUD_DSP_WR_AV_SYNC_AV_ON__M) == AUD_DSP_WR_AV_SYNC_AV_ON_DISABLE) { - *avSync = DRX_AUD_AVSYNC_OFF; + *av_sync = DRX_AUD_AVSYNC_OFF; return DRX_STS_OK; } - switch (wAudVidSync & AUD_DSP_WR_AV_SYNC_AV_STD_SEL__M) { + switch (w_aud_vid_sync & AUD_DSP_WR_AV_SYNC_AV_STD_SEL__M) { case AUD_DSP_WR_AV_SYNC_AV_STD_SEL_NTSC: - *avSync = DRX_AUD_AVSYNC_NTSC; + *av_sync = DRX_AUD_AVSYNC_NTSC; break; case AUD_DSP_WR_AV_SYNC_AV_STD_SEL_MONOCHROME: - *avSync = DRX_AUD_AVSYNC_MONOCHROME; + *av_sync = DRX_AUD_AVSYNC_MONOCHROME; break; case AUD_DSP_WR_AV_SYNC_AV_STD_SEL_PAL_SECAM: - *avSync = DRX_AUD_AVSYNC_PAL_SECAM; + *av_sync = DRX_AUD_AVSYNC_PAL_SECAM; break; default: return DRX_STS_ERROR; @@ -11324,28 +11324,28 @@ rw_error: /** * \brief Get deviation mode * \param demod instance of demodulator -* \param pointer to DRXCfgAudDeviation_t +* \param pointer to drx_cfg_aud_deviation_t * \return int. * */ static int -AUDCtrlGetCfgDev(pDRXDemodInstance_t demod, pDRXCfgAudDeviation_t dev) +aud_ctrl_get_cfg_dev(pdrx_demod_instance_t demod, pdrx_cfg_aud_deviation_t dev) { - struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; - pDRXJData_t extAttr = (pDRXJData_t) NULL; + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) NULL; + pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; - u16 rModus = 0; + u16 r_modus = 0; if (dev == NULL) { return DRX_STS_INVALID_ARG; } - extAttr = (pDRXJData_t) demod->myExtAttr; - devAddr = demod->myI2CDevAddr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; + dev_addr = demod->my_i2c_dev_addr; - CHK_ERROR(AUDGetModus(demod, &rModus)); + CHK_ERROR(aud_get_modus(demod, &r_modus)); - switch (rModus & AUD_DEM_WR_MODUS_MOD_HDEV_A__M) { + switch (r_modus & AUD_DEM_WR_MODUS_MOD_HDEV_A__M) { case AUD_DEM_WR_MODUS_MOD_HDEV_A_NORMAL: *dev = DRX_AUD_DEVIATION_NORMAL; break; @@ -11365,49 +11365,49 @@ rw_error: /** * \brief Get deviation mode * \param demod instance of demodulator -* \param pointer to DRXCfgAudDeviation_t +* \param pointer to drx_cfg_aud_deviation_t * \return int. * */ static int -AUDCtrlSetCfgDev(pDRXDemodInstance_t demod, pDRXCfgAudDeviation_t dev) +aud_ctrl_set_cfg_dev(pdrx_demod_instance_t demod, pdrx_cfg_aud_deviation_t dev) { - struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; - pDRXJData_t extAttr = (pDRXJData_t) NULL; + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) NULL; + pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; - u16 wModus = 0; - u16 rModus = 0; + u16 w_modus = 0; + u16 r_modus = 0; if (dev == NULL) { return DRX_STS_INVALID_ARG; } - extAttr = (pDRXJData_t) demod->myExtAttr; - devAddr = demod->myI2CDevAddr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; + dev_addr = demod->my_i2c_dev_addr; - CHK_ERROR(AUDGetModus(demod, &rModus)); + CHK_ERROR(aud_get_modus(demod, &r_modus)); - wModus = rModus; + w_modus = r_modus; - wModus &= (u16) ~AUD_DEM_WR_MODUS_MOD_HDEV_A__M; + w_modus &= (u16) ~AUD_DEM_WR_MODUS_MOD_HDEV_A__M; switch (*dev) { case DRX_AUD_DEVIATION_NORMAL: - wModus |= AUD_DEM_WR_MODUS_MOD_HDEV_A_NORMAL; + w_modus |= AUD_DEM_WR_MODUS_MOD_HDEV_A_NORMAL; break; case DRX_AUD_DEVIATION_HIGH: - wModus |= AUD_DEM_WR_MODUS_MOD_HDEV_A_HIGH_DEVIATION; + w_modus |= AUD_DEM_WR_MODUS_MOD_HDEV_A_HIGH_DEVIATION; break; default: return DRX_STS_INVALID_ARG; } /* now update the modus register */ - if (wModus != rModus) { - WR16(devAddr, AUD_DEM_WR_MODUS__A, wModus); + if (w_modus != r_modus) { + WR16(dev_addr, AUD_DEM_WR_MODUS__A, w_modus); } /* store in drxk data struct */ - extAttr->audData.deviation = *dev; + ext_attr->aud_data.deviation = *dev; return DRX_STS_OK; rw_error: @@ -11418,70 +11418,70 @@ rw_error: /** * \brief Get Prescaler settings * \param demod instance of demodulator -* \param pointer to DRXCfgAudPrescale_t +* \param pointer to drx_cfg_aud_prescale_t * \return int. * */ static int -AUDCtrlGetCfgPrescale(pDRXDemodInstance_t demod, pDRXCfgAudPrescale_t presc) +aud_ctrl_get_cfg_prescale(pdrx_demod_instance_t demod, pdrx_cfg_aud_prescale_t presc) { - struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; - pDRXJData_t extAttr = (pDRXJData_t) NULL; + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) NULL; + pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; - u16 rMaxFMDeviation = 0; - u16 rNicamPrescaler = 0; + u16 r_max_fm_deviation = 0; + u16 r_nicam_prescaler = 0; if (presc == NULL) { return DRX_STS_INVALID_ARG; } - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* power up */ - if (extAttr->audData.audioIsActive == false) { - CHK_ERROR(PowerUpAud(demod, true)); - extAttr->audData.audioIsActive = true; + if (ext_attr->aud_data.audio_is_active == false) { + CHK_ERROR(power_up_aud(demod, true)); + ext_attr->aud_data.audio_is_active = true; } /* read register data */ - RR16(devAddr, AUD_DSP_WR_NICAM_PRESC__A, &rNicamPrescaler); - RR16(devAddr, AUD_DSP_WR_FM_PRESC__A, &rMaxFMDeviation); + RR16(dev_addr, AUD_DSP_WR_NICAM_PRESC__A, &r_nicam_prescaler); + RR16(dev_addr, AUD_DSP_WR_FM_PRESC__A, &r_max_fm_deviation); /* calculate max FM deviation */ - rMaxFMDeviation >>= AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__B; - if (rMaxFMDeviation > 0) { - presc->fmDeviation = 3600UL + (rMaxFMDeviation >> 1); - presc->fmDeviation /= rMaxFMDeviation; + r_max_fm_deviation >>= AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__B; + if (r_max_fm_deviation > 0) { + presc->fm_deviation = 3600UL + (r_max_fm_deviation >> 1); + presc->fm_deviation /= r_max_fm_deviation; } else { - presc->fmDeviation = 380; /* kHz */ + presc->fm_deviation = 380; /* kHz */ } /* calculate NICAM gain from pre-scaler */ /* - nicamGain = 20 * ( log10( preScaler / 16) ) + nicam_gain = 20 * ( log10( preScaler / 16) ) = ( 100log10( preScaler ) - 100log10( 16 ) ) / 5 - because Log10Times100() cannot return negative numbers + because log1_times100() cannot return negative numbers = ( 100log10( 10 * preScaler ) - 100log10( 10 * 16) ) / 5 for 0.1dB resolution: - nicamGain = 200 * ( log10( preScaler / 16) ) + nicam_gain = 200 * ( log10( preScaler / 16) ) = 2 * ( 100log10( 10 * preScaler ) - 100log10( 10 * 16) ) = ( 100log10( 10 * preScaler^2 ) - 100log10( 10 * 16^2 ) ) */ - rNicamPrescaler >>= 8; - if (rNicamPrescaler <= 1) { - presc->nicamGain = -241; + r_nicam_prescaler >>= 8; + if (r_nicam_prescaler <= 1) { + presc->nicam_gain = -241; } else { - presc->nicamGain = (s16) (((s32) - (Log10Times100 - (10 * rNicamPrescaler * - rNicamPrescaler)) - (s32) - (Log10Times100(10 * 16 * 16)))); + presc->nicam_gain = (s16) (((s32) + (log1_times100 + (10 * r_nicam_prescaler * + r_nicam_prescaler)) - (s32) + (log1_times100(10 * 16 * 16)))); } return DRX_STS_OK; @@ -11493,79 +11493,79 @@ rw_error: /** * \brief Set Prescaler settings * \param demod instance of demodulator -* \param pointer to DRXCfgAudPrescale_t +* \param pointer to drx_cfg_aud_prescale_t * \return int. * */ static int -AUDCtrlSetCfgPrescale(pDRXDemodInstance_t demod, pDRXCfgAudPrescale_t presc) +aud_ctrl_set_cfg_prescale(pdrx_demod_instance_t demod, pdrx_cfg_aud_prescale_t presc) { - struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; - pDRXJData_t extAttr = (pDRXJData_t) NULL; + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) NULL; + pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; - u16 wMaxFMDeviation = 0; - u16 nicamPrescaler; + u16 w_max_fm_deviation = 0; + u16 nicam_prescaler; if (presc == NULL) { return DRX_STS_INVALID_ARG; } - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* power up */ - if (extAttr->audData.audioIsActive == false) { - CHK_ERROR(PowerUpAud(demod, true)); - extAttr->audData.audioIsActive = true; + if (ext_attr->aud_data.audio_is_active == false) { + CHK_ERROR(power_up_aud(demod, true)); + ext_attr->aud_data.audio_is_active = true; } /* setting of max FM deviation */ - wMaxFMDeviation = (u16) (Frac(3600UL, presc->fmDeviation, 0)); - wMaxFMDeviation <<= AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__B; - if (wMaxFMDeviation >= + w_max_fm_deviation = (u16) (frac(3600UL, presc->fm_deviation, 0)); + w_max_fm_deviation <<= AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__B; + if (w_max_fm_deviation >= AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_28_KHZ_FM_DEVIATION) { - wMaxFMDeviation = + w_max_fm_deviation = AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_28_KHZ_FM_DEVIATION; } /* NICAM Prescaler */ - if ((presc->nicamGain >= -241) && (presc->nicamGain <= 180)) { + if ((presc->nicam_gain >= -241) && (presc->nicam_gain <= 180)) { /* calculation - prescaler = 16 * 10^( GdB / 20 ) + prescaler = 16 * 10^( gd_b / 20 ) - minval of GdB = -20*log( 16 ) = -24.1dB + minval of gd_b = -20*log( 16 ) = -24.1dB - negative numbers not allowed for dB2LinTimes100, so + negative numbers not allowed for d_b2lin_times100, so - prescaler = 16 * 10^( GdB / 20 ) - = 10^( (GdB / 20) + log10(16) ) - = 10^( (GdB + 20log10(16)) / 20 ) + prescaler = 16 * 10^( gd_b / 20 ) + = 10^( (gd_b / 20) + log10(16) ) + = 10^( (gd_b + 20log10(16)) / 20 ) in 0.1dB = 10^( G0.1dB + 200log10(16)) / 200 ) */ - nicamPrescaler = (u16) - ((dB2LinTimes100(presc->nicamGain + 241UL) + 50UL) / 100UL); + nicam_prescaler = (u16) + ((d_b2lin_times100(presc->nicam_gain + 241UL) + 50UL) / 100UL); /* clip result */ - if (nicamPrescaler > 127) { - nicamPrescaler = 127; + if (nicam_prescaler > 127) { + nicam_prescaler = 127; } /* shift before writing to register */ - nicamPrescaler <<= 8; + nicam_prescaler <<= 8; } else { return (DRX_STS_INVALID_ARG); } /* end of setting NICAM Prescaler */ - WR16(devAddr, AUD_DSP_WR_NICAM_PRESC__A, nicamPrescaler); - WR16(devAddr, AUD_DSP_WR_FM_PRESC__A, wMaxFMDeviation); + WR16(dev_addr, AUD_DSP_WR_NICAM_PRESC__A, nicam_prescaler); + WR16(dev_addr, AUD_DSP_WR_FM_PRESC__A, w_max_fm_deviation); - extAttr->audData.prescale = *presc; + ext_attr->aud_data.prescale = *presc; return DRX_STS_OK; rw_error: @@ -11576,16 +11576,16 @@ rw_error: /** * \brief Beep * \param demod instance of demodulator -* \param pointer to DRXAudBeep_t +* \param pointer to drx_aud_beep_t * \return int. * */ -static int AUDCtrlBeep(pDRXDemodInstance_t demod, pDRXAudBeep_t beep) +static int aud_ctrl_beep(pdrx_demod_instance_t demod, pdrx_aud_beep_t beep) { - struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; - pDRXJData_t extAttr = (pDRXJData_t) NULL; + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) NULL; + pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; - u16 theBeep = 0; + u16 the_beep = 0; u16 volume = 0; u32 frequency = 0; @@ -11593,13 +11593,13 @@ static int AUDCtrlBeep(pDRXDemodInstance_t demod, pDRXAudBeep_t beep) return DRX_STS_INVALID_ARG; } - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* power up */ - if (extAttr->audData.audioIsActive == false) { - CHK_ERROR(PowerUpAud(demod, true)); - extAttr->audData.audioIsActive = true; + if (ext_attr->aud_data.audio_is_active == false) { + CHK_ERROR(power_up_aud(demod, true)); + ext_attr->aud_data.audio_is_active = true; } if ((beep->volume > 0) || (beep->volume < -127)) { @@ -11611,19 +11611,19 @@ static int AUDCtrlBeep(pDRXDemodInstance_t demod, pDRXAudBeep_t beep) } volume = (u16) beep->volume + 127; - theBeep |= volume << AUD_DSP_WR_BEEPER_BEEP_VOLUME__B; + the_beep |= volume << AUD_DSP_WR_BEEPER_BEEP_VOLUME__B; frequency = ((u32) beep->frequency) * 23 / 500; if (frequency > AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__M) { frequency = AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__M; } - theBeep |= (u16) frequency; + the_beep |= (u16) frequency; if (beep->mute == true) { - theBeep = 0; + the_beep = 0; } - WR16(devAddr, AUD_DSP_WR_BEEPER__A, theBeep); + WR16(dev_addr, AUD_DSP_WR_BEEPER__A, the_beep); return DRX_STS_OK; rw_error: @@ -11634,108 +11634,108 @@ rw_error: /** * \brief Set an audio standard * \param demod instance of demodulator -* \param pointer to DRXAudStandard_t +* \param pointer to drx_aud_standard_t * \return int. * */ static int -AUDCtrlSetStandard(pDRXDemodInstance_t demod, pDRXAudStandard_t standard) +aud_ctrl_set_standard(pdrx_demod_instance_t demod, pdrx_aud_standard_t standard) { - struct i2c_device_addr *devAddr = NULL; - pDRXJData_t extAttr = NULL; - enum drx_standard currentStandard = DRX_STANDARD_UNKNOWN; + struct i2c_device_addr *dev_addr = NULL; + pdrxj_data_t ext_attr = NULL; + enum drx_standard current_standard = DRX_STANDARD_UNKNOWN; - u16 wStandard = 0; - u16 wModus = 0; - u16 rModus = 0; + u16 w_standard = 0; + u16 w_modus = 0; + u16 r_modus = 0; - bool muteBuffer = false; - s16 volumeBuffer = 0; - u16 wVolume = 0; + bool mute_buffer = false; + s16 volume_buffer = 0; + u16 w_volume = 0; if (standard == NULL) { return DRX_STS_INVALID_ARG; } - devAddr = (struct i2c_device_addr *) demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; + dev_addr = (struct i2c_device_addr *) demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* power up */ - if (extAttr->audData.audioIsActive == false) { - CHK_ERROR(PowerUpAud(demod, false)); - extAttr->audData.audioIsActive = true; + if (ext_attr->aud_data.audio_is_active == false) { + CHK_ERROR(power_up_aud(demod, false)); + ext_attr->aud_data.audio_is_active = true; } /* reset RDS data availability flag */ - extAttr->audData.rdsDataPresent = false; + ext_attr->aud_data.rds_data_present = false; /* we need to mute from here to avoid noise during standard switching */ - muteBuffer = extAttr->audData.volume.mute; - volumeBuffer = extAttr->audData.volume.volume; + mute_buffer = ext_attr->aud_data.volume.mute; + volume_buffer = ext_attr->aud_data.volume.volume; - extAttr->audData.volume.mute = true; + ext_attr->aud_data.volume.mute = true; /* restore data structure from DRX ExtAttr, call volume first to mute */ - CHK_ERROR(AUDCtrlSetCfgVolume(demod, &extAttr->audData.volume)); - CHK_ERROR(AUDCtrlSetCfgCarrier(demod, &extAttr->audData.carriers)); - CHK_ERROR(AUDCtrlSetCfgASSThres - (demod, &extAttr->audData.assThresholds)); - CHK_ERROR(AUDCtrSetlCfgAutoSound(demod, &extAttr->audData.autoSound)); - CHK_ERROR(AUDCtrlSetCfgMixer(demod, &extAttr->audData.mixer)); - CHK_ERROR(AUDCtrlSetCfgAVSync(demod, &extAttr->audData.avSync)); - CHK_ERROR(AUDCtrlSetCfgOutputI2S(demod, &extAttr->audData.i2sdata)); + CHK_ERROR(aud_ctrl_set_cfg_volume(demod, &ext_attr->aud_data.volume)); + CHK_ERROR(aud_ctrl_set_cfg_carrier(demod, &ext_attr->aud_data.carriers)); + CHK_ERROR(aud_ctrl_set_cfg_ass_thres + (demod, &ext_attr->aud_data.ass_thresholds)); + CHK_ERROR(aud_ctr_setl_cfg_auto_sound(demod, &ext_attr->aud_data.auto_sound)); + CHK_ERROR(aud_ctrl_set_cfg_mixer(demod, &ext_attr->aud_data.mixer)); + CHK_ERROR(aud_ctrl_set_cfg_av_sync(demod, &ext_attr->aud_data.av_sync)); + CHK_ERROR(aud_ctrl_set_cfg_output_i2s(demod, &ext_attr->aud_data.i2sdata)); /* get prescaler from presets */ - CHK_ERROR(AUDCtrlSetCfgPrescale(demod, &extAttr->audData.prescale)); + CHK_ERROR(aud_ctrl_set_cfg_prescale(demod, &ext_attr->aud_data.prescale)); - CHK_ERROR(AUDGetModus(demod, &rModus)); + CHK_ERROR(aud_get_modus(demod, &r_modus)); - wModus = rModus; + w_modus = r_modus; switch (*standard) { case DRX_AUD_STANDARD_AUTO: - wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_AUTO; + w_standard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_AUTO; break; case DRX_AUD_STANDARD_BTSC: - wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_BTSC_STEREO; - if (extAttr->audData.btscDetect == DRX_BTSC_MONO_AND_SAP) { - wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_BTSC_SAP; + w_standard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_BTSC_STEREO; + if (ext_attr->aud_data.btsc_detect == DRX_BTSC_MONO_AND_SAP) { + w_standard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_BTSC_SAP; } break; case DRX_AUD_STANDARD_A2: - wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_M_KOREA; + w_standard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_M_KOREA; break; case DRX_AUD_STANDARD_EIAJ: - wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_EIA_J; + w_standard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_EIA_J; break; case DRX_AUD_STANDARD_FM_STEREO: - wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_FM_RADIO; + w_standard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_FM_RADIO; break; case DRX_AUD_STANDARD_BG_FM: - wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_BG_FM; + w_standard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_BG_FM; break; case DRX_AUD_STANDARD_D_K1: - wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K1; + w_standard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K1; break; case DRX_AUD_STANDARD_D_K2: - wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K2; + w_standard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K2; break; case DRX_AUD_STANDARD_D_K3: - wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K3; + w_standard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K3; break; case DRX_AUD_STANDARD_BG_NICAM_FM: - wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_BG_NICAM_FM; + w_standard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_BG_NICAM_FM; break; case DRX_AUD_STANDARD_L_NICAM_AM: - wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_L_NICAM_AM; + w_standard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_L_NICAM_AM; break; case DRX_AUD_STANDARD_I_NICAM_FM: - wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_I_NICAM_FM; + w_standard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_I_NICAM_FM; break; case DRX_AUD_STANDARD_D_K_NICAM_FM: - wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K_NICAM_FM; + w_standard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K_NICAM_FM; break; case DRX_AUD_STANDARD_UNKNOWN: - wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_AUTO; + w_standard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_AUTO; break; default: return DRX_STS_ERROR; @@ -11743,65 +11743,65 @@ AUDCtrlSetStandard(pDRXDemodInstance_t demod, pDRXAudStandard_t standard) if (*standard == DRX_AUD_STANDARD_AUTO) { /* we need the current standard here */ - currentStandard = extAttr->standard; + current_standard = ext_attr->standard; - wModus &= (u16) ~AUD_DEM_WR_MODUS_MOD_6_5MHZ__M; + w_modus &= (u16) ~AUD_DEM_WR_MODUS_MOD_6_5MHZ__M; - if ((currentStandard == DRX_STANDARD_PAL_SECAM_L) || - (currentStandard == DRX_STANDARD_PAL_SECAM_LP)) { - wModus |= (AUD_DEM_WR_MODUS_MOD_6_5MHZ_SECAM); + if ((current_standard == DRX_STANDARD_PAL_SECAM_L) || + (current_standard == DRX_STANDARD_PAL_SECAM_LP)) { + w_modus |= (AUD_DEM_WR_MODUS_MOD_6_5MHZ_SECAM); } else { - wModus |= (AUD_DEM_WR_MODUS_MOD_6_5MHZ_D_K); + w_modus |= (AUD_DEM_WR_MODUS_MOD_6_5MHZ_D_K); } - wModus &= (u16) ~AUD_DEM_WR_MODUS_MOD_4_5MHZ__M; - if (currentStandard == DRX_STANDARD_NTSC) { - wModus |= (AUD_DEM_WR_MODUS_MOD_4_5MHZ_M_BTSC); + w_modus &= (u16) ~AUD_DEM_WR_MODUS_MOD_4_5MHZ__M; + if (current_standard == DRX_STANDARD_NTSC) { + w_modus |= (AUD_DEM_WR_MODUS_MOD_4_5MHZ_M_BTSC); } else { /* non USA, ignore standard M to save time */ - wModus |= (AUD_DEM_WR_MODUS_MOD_4_5MHZ_CHROMA); + w_modus |= (AUD_DEM_WR_MODUS_MOD_4_5MHZ_CHROMA); } } - wModus &= (u16) ~AUD_DEM_WR_MODUS_MOD_FMRADIO__M; + w_modus &= (u16) ~AUD_DEM_WR_MODUS_MOD_FMRADIO__M; /* just get hardcoded deemphasis and activate here */ - if (extAttr->audData.deemph == DRX_AUD_FM_DEEMPH_50US) { - wModus |= (AUD_DEM_WR_MODUS_MOD_FMRADIO_EU_50U); + if (ext_attr->aud_data.deemph == DRX_AUD_FM_DEEMPH_50US) { + w_modus |= (AUD_DEM_WR_MODUS_MOD_FMRADIO_EU_50U); } else { - wModus |= (AUD_DEM_WR_MODUS_MOD_FMRADIO_US_75U); + w_modus |= (AUD_DEM_WR_MODUS_MOD_FMRADIO_US_75U); } - wModus &= (u16) ~AUD_DEM_WR_MODUS_MOD_BTSC__M; - if (extAttr->audData.btscDetect == DRX_BTSC_STEREO) { - wModus |= (AUD_DEM_WR_MODUS_MOD_BTSC_BTSC_STEREO); + w_modus &= (u16) ~AUD_DEM_WR_MODUS_MOD_BTSC__M; + if (ext_attr->aud_data.btsc_detect == DRX_BTSC_STEREO) { + w_modus |= (AUD_DEM_WR_MODUS_MOD_BTSC_BTSC_STEREO); } else { /* DRX_BTSC_MONO_AND_SAP */ - wModus |= (AUD_DEM_WR_MODUS_MOD_BTSC_BTSC_SAP); + w_modus |= (AUD_DEM_WR_MODUS_MOD_BTSC_BTSC_SAP); } - if (wModus != rModus) { - WR16(devAddr, AUD_DEM_WR_MODUS__A, wModus); + if (w_modus != r_modus) { + WR16(dev_addr, AUD_DEM_WR_MODUS__A, w_modus); } - WR16(devAddr, AUD_DEM_WR_STANDARD_SEL__A, wStandard); + WR16(dev_addr, AUD_DEM_WR_STANDARD_SEL__A, w_standard); /**************************************************************************/ - /* NOT calling AUDCtrlSetCfgVolume to avoid interfering standard */ + /* NOT calling aud_ctrl_set_cfg_volume to avoid interfering standard */ /* detection, need to keep things very minimal here, but keep audio */ /* buffers intact */ /**************************************************************************/ - extAttr->audData.volume.mute = muteBuffer; - if (extAttr->audData.volume.mute == false) { - wVolume |= (u16) ((volumeBuffer + AUD_VOLUME_ZERO_DB) << + ext_attr->aud_data.volume.mute = mute_buffer; + if (ext_attr->aud_data.volume.mute == false) { + w_volume |= (u16) ((volume_buffer + AUD_VOLUME_ZERO_DB) << AUD_DSP_WR_VOLUME_VOL_MAIN__B); - WR16(devAddr, AUD_DSP_WR_VOLUME__A, wVolume); + WR16(dev_addr, AUD_DSP_WR_VOLUME__A, w_volume); } /* write standard selected */ - extAttr->audData.audioStandard = *standard; + ext_attr->aud_data.audio_standard = *standard; return DRX_STS_OK; rw_error: @@ -11812,43 +11812,43 @@ rw_error: /** * \brief Get the current audio standard * \param demod instance of demodulator -* \param pointer to DRXAudStandard_t +* \param pointer to drx_aud_standard_t * \return int. * */ static int -AUDCtrlGetStandard(pDRXDemodInstance_t demod, pDRXAudStandard_t standard) +aud_ctrl_get_standard(pdrx_demod_instance_t demod, pdrx_aud_standard_t standard) { - struct i2c_device_addr *devAddr = NULL; - pDRXJData_t extAttr = NULL; + struct i2c_device_addr *dev_addr = NULL; + pdrxj_data_t ext_attr = NULL; - u16 rData = 0; + u16 r_data = 0; if (standard == NULL) { return DRX_STS_INVALID_ARG; } - extAttr = (pDRXJData_t) demod->myExtAttr; - devAddr = (struct i2c_device_addr *) demod->myI2CDevAddr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; + dev_addr = (struct i2c_device_addr *) demod->my_i2c_dev_addr; /* power up */ - if (extAttr->audData.audioIsActive == false) { - CHK_ERROR(PowerUpAud(demod, true)); - extAttr->audData.audioIsActive = true; + if (ext_attr->aud_data.audio_is_active == false) { + CHK_ERROR(power_up_aud(demod, true)); + ext_attr->aud_data.audio_is_active = true; } *standard = DRX_AUD_STANDARD_UNKNOWN; - RR16(devAddr, AUD_DEM_RD_STANDARD_RES__A, &rData); + RR16(dev_addr, AUD_DEM_RD_STANDARD_RES__A, &r_data); /* return OK if the detection is not ready yet */ - if (rData >= AUD_DEM_RD_STANDARD_RES_STD_RESULT_DETECTION_STILL_ACTIVE) { + if (r_data >= AUD_DEM_RD_STANDARD_RES_STD_RESULT_DETECTION_STILL_ACTIVE) { *standard = DRX_AUD_STANDARD_NOT_READY; return DRX_STS_OK; } /* detection done, return correct standard */ - switch (rData) { + switch (r_data) { /* no standard detected */ case AUD_DEM_RD_STANDARD_RES_STD_RESULT_NO_SOUND_STANDARD: *standard = DRX_AUD_STANDARD_UNKNOWN; @@ -11924,18 +11924,18 @@ rw_error: * */ static int -FmLockStatus(pDRXDemodInstance_t demod, pDRXLockStatus_t lockStat) +fm_lock_status(pdrx_demod_instance_t demod, pdrx_lock_status_t lock_stat) { - DRXAudStatus_t status; + drx_aud_status_t status; /* Check detection of audio carriers */ - CHK_ERROR(AUDCtrlGetCarrierDetectStatus(demod, &status)); + CHK_ERROR(aud_ctrl_get_carrier_detect_status(demod, &status)); /* locked if either primary or secondary carrier is detected */ - if ((status.carrierA == true) || (status.carrierB == true)) { - *lockStat = DRX_LOCKED; + if ((status.carrier_a == true) || (status.carrier_b == true)) { + *lock_stat = DRX_LOCKED; } else { - *lockStat = DRX_NOT_LOCKED; + *lock_stat = DRX_NOT_LOCKED; } return (DRX_STS_OK); @@ -11956,15 +11956,15 @@ rw_error: * */ static int -FmSigQuality(pDRXDemodInstance_t demod, pDRXSigQuality_t sigQuality) +fm_sig_quality(pdrx_demod_instance_t demod, pdrx_sig_quality_t sig_quality) { - DRXLockStatus_t lockStatus = DRX_NOT_LOCKED; + drx_lock_status_t lock_status = DRX_NOT_LOCKED; - CHK_ERROR(FmLockStatus(demod, &lockStatus)); - if (lockStatus == DRX_LOCKED) { - sigQuality->indicator = 100; + CHK_ERROR(fm_lock_status(demod, &lock_status)); + if (lock_status == DRX_LOCKED) { + sig_quality->indicator = 100; } else { - sigQuality->indicator = 0; + sig_quality->indicator = 0; } return (DRX_STS_OK); @@ -11986,54 +11986,54 @@ rw_error: /*============================================================================*/ #ifndef DRXJ_DIGITAL_ONLY /** -* \fn int GetOOBLockStatus () +* \fn int get_oob_lock_status () * \brief Get OOB lock status. -* \param devAddr I2C address - \ oobLock OOB lock status. +* \param dev_addr I2C address + \ oob_lock OOB lock status. * \return int. * * Gets OOB lock status * */ static int -GetOOBLockStatus(pDRXDemodInstance_t demod, - struct i2c_device_addr *devAddr, pDRXLockStatus_t oobLock) +get_oob_lock_status(pdrx_demod_instance_t demod, + struct i2c_device_addr *dev_addr, pdrx_lock_status_t oob_lock) { - DRXJSCUCmd_t scuCmd; - u16 cmdResult[2]; - u16 OOBLockState; + drxjscu_cmd_t scu_cmd; + u16 cmd_result[2]; + u16 oob_lock_state; - *oobLock = DRX_NOT_LOCKED; + *oob_lock = DRX_NOT_LOCKED; - scuCmd.command = SCU_RAM_COMMAND_STANDARD_OOB | + scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB | SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK; - scuCmd.resultLen = 2; - scuCmd.result = cmdResult; - scuCmd.parameterLen = 0; + scu_cmd.result_len = 2; + scu_cmd.result = cmd_result; + scu_cmd.parameter_len = 0; - CHK_ERROR(SCUCommand(devAddr, &scuCmd)); + CHK_ERROR(scu_command(dev_addr, &scu_cmd)); - if (scuCmd.result[1] < 0x4000) { + if (scu_cmd.result[1] < 0x4000) { /* 0x00 NOT LOCKED */ - *oobLock = DRX_NOT_LOCKED; - } else if (scuCmd.result[1] < 0x8000) { + *oob_lock = DRX_NOT_LOCKED; + } else if (scu_cmd.result[1] < 0x8000) { /* 0x40 DEMOD LOCKED */ - *oobLock = DRXJ_OOB_SYNC_LOCK; - } else if (scuCmd.result[1] < 0xC000) { + *oob_lock = DRXJ_OOB_SYNC_LOCK; + } else if (scu_cmd.result[1] < 0xC000) { /* 0x80 DEMOD + OOB LOCKED (system lock) */ - OOBLockState = scuCmd.result[1] & 0x00FF; + oob_lock_state = scu_cmd.result[1] & 0x00FF; - if (OOBLockState & 0x0008) { - *oobLock = DRXJ_OOB_SYNC_LOCK; - } else if ((OOBLockState & 0x0002) && (OOBLockState & 0x0001)) { - *oobLock = DRXJ_OOB_AGC_LOCK; + if (oob_lock_state & 0x0008) { + *oob_lock = DRXJ_OOB_SYNC_LOCK; + } else if ((oob_lock_state & 0x0002) && (oob_lock_state & 0x0001)) { + *oob_lock = DRXJ_OOB_AGC_LOCK; } } else { /* 0xC0 NEVER LOCKED (system will never be able to lock to the signal) */ - *oobLock = DRX_NEVER_LOCK; + *oob_lock = DRX_NEVER_LOCK; } - /* *oobLock = scuCmd.result[1]; */ + /* *oob_lock = scu_cmd.result[1]; */ return (DRX_STS_OK); rw_error: @@ -12041,9 +12041,9 @@ rw_error: } /** -* \fn int GetOOBSymbolRateOffset () +* \fn int get_oob_symbol_rate_offset () * \brief Get OOB Symbol rate offset. Unit is [ppm] -* \param devAddr I2C address +* \param dev_addr I2C address * \ Symbol Rate Offset OOB parameter. * \return int. * @@ -12051,70 +12051,70 @@ rw_error: * */ static int -GetOOBSymbolRateOffset(struct i2c_device_addr *devAddr, s32 *SymbolRateOffset) +get_oob_symbol_rate_offset(struct i2c_device_addr *dev_addr, s32 *symbol_rate_offset) { -/* offset = -{(timingOffset/2^19)*(symbolRate/12,656250MHz)}*10^6 [ppm] */ -/* offset = -{(timingOffset/2^19)*(symbolRate/12656250)}*10^6 [ppm] */ +/* offset = -{(timing_offset/2^19)*(symbol_rate/12,656250MHz)}*10^6 [ppm] */ +/* offset = -{(timing_offset/2^19)*(symbol_rate/12656250)}*10^6 [ppm] */ /* after reconfiguration: */ -/* offset = -{(timingOffset*symbolRate)/(2^19*12656250)}*10^6 [ppm] */ +/* offset = -{(timing_offset*symbol_rate)/(2^19*12656250)}*10^6 [ppm] */ /* shift symbol rate left by 5 without lossing information */ -/* offset = -{(timingOffset*(symbolRate * 2^-5))/(2^14*12656250)}*10^6 [ppm]*/ +/* offset = -{(timing_offset*(symbol_rate * 2^-5))/(2^14*12656250)}*10^6 [ppm]*/ /* shift 10^6 left by 6 without loosing information */ -/* offset = -{(timingOffset*(symbolRate * 2^-5))/(2^8*12656250)}*15625 [ppm]*/ +/* offset = -{(timing_offset*(symbol_rate * 2^-5))/(2^8*12656250)}*15625 [ppm]*/ /* trim 12656250/15625 = 810 */ -/* offset = -{(timingOffset*(symbolRate * 2^-5))/(2^8*810)} [ppm] */ -/* offset = -[(symbolRate * 2^-5)*(timingOffset)/(2^8)]/810 [ppm] */ - s32 timingOffset = 0; - u32 unsignedTimingOffset = 0; - s32 divisionFactor = 810; +/* offset = -{(timing_offset*(symbol_rate * 2^-5))/(2^8*810)} [ppm] */ +/* offset = -[(symbol_rate * 2^-5)*(timing_offset)/(2^8)]/810 [ppm] */ + s32 timing_offset = 0; + u32 unsigned_timing_offset = 0; + s32 division_factor = 810; u16 data = 0; - u32 symbolRate = 0; + u32 symbol_rate = 0; bool negative = false; - *SymbolRateOffset = 0; + *symbol_rate_offset = 0; /* read data rate */ - SARR16(devAddr, SCU_RAM_ORX_RF_RX_DATA_RATE__A, &data); + SARR16(dev_addr, SCU_RAM_ORX_RF_RX_DATA_RATE__A, &data); switch (data & SCU_RAM_ORX_RF_RX_DATA_RATE__M) { case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC: case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC: case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC_ALT: case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC_ALT: - symbolRate = 1024000; /* bps */ + symbol_rate = 1024000; /* bps */ break; case SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_REGSPEC: case SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_INVSPEC: - symbolRate = 772000; /* bps */ + symbol_rate = 772000; /* bps */ break; case SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_REGSPEC: case SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_INVSPEC: - symbolRate = 1544000; /* bps */ + symbol_rate = 1544000; /* bps */ break; default: return (DRX_STS_ERROR); } - RR16(devAddr, ORX_CON_CTI_DTI_R__A, &data); + RR16(dev_addr, ORX_CON_CTI_DTI_R__A, &data); /* convert data to positive and keep information about sign */ if ((data & 0x8000) == 0x8000) { if (data == 0x8000) - unsignedTimingOffset = 32768; + unsigned_timing_offset = 32768; else - unsignedTimingOffset = 0x00007FFF & (u32) (-data); + unsigned_timing_offset = 0x00007FFF & (u32) (-data); negative = true; } else - unsignedTimingOffset = (u32) data; + unsigned_timing_offset = (u32) data; - symbolRate = symbolRate >> 5; - unsignedTimingOffset = (unsignedTimingOffset * symbolRate); - unsignedTimingOffset = Frac(unsignedTimingOffset, 256, FRAC_ROUND); - unsignedTimingOffset = Frac(unsignedTimingOffset, - divisionFactor, FRAC_ROUND); + symbol_rate = symbol_rate >> 5; + unsigned_timing_offset = (unsigned_timing_offset * symbol_rate); + unsigned_timing_offset = frac(unsigned_timing_offset, 256, FRAC_ROUND); + unsigned_timing_offset = frac(unsigned_timing_offset, + division_factor, FRAC_ROUND); if (negative) - timingOffset = (s32) unsignedTimingOffset; + timing_offset = (s32) unsigned_timing_offset; else - timingOffset = -(s32) unsignedTimingOffset; + timing_offset = -(s32) unsigned_timing_offset; - *SymbolRateOffset = timingOffset; + *symbol_rate_offset = timing_offset; return (DRX_STS_OK); rw_error: @@ -12122,100 +12122,100 @@ rw_error: } /** -* \fn int GetOOBFreqOffset () +* \fn int get_oob_freq_offset () * \brief Get OOB lock status. -* \param devAddr I2C address -* \ freqOffset OOB frequency offset. +* \param dev_addr I2C address +* \ freq_offset OOB frequency offset. * \return int. * * Gets OOB frequency offset * */ static int -GetOOBFreqOffset(pDRXDemodInstance_t demod, s32 *freqOffset) +get_oob_freq_offset(pdrx_demod_instance_t demod, s32 *freq_offset) { u16 data = 0; u16 rot = 0; - u16 symbolRateReg = 0; - u32 symbolRate = 0; - s32 coarseFreqOffset = 0; - s32 fineFreqOffset = 0; - s32 fineSign = 1; - s32 coarseSign = 1; - u32 data64Hi = 0; - u32 data64Lo = 0; - u32 tempFreqOffset = 0; - pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); - struct i2c_device_addr *devAddr = NULL; + u16 symbol_rateReg = 0; + u32 symbol_rate = 0; + s32 coarse_freq_offset = 0; + s32 fine_freq_offset = 0; + s32 fine_sign = 1; + s32 coarse_sign = 1; + u32 data64hi = 0; + u32 data64lo = 0; + u32 temp_freq_offset = 0; + pdrx_common_attr_t common_attr = (pdrx_common_attr_t) (NULL); + struct i2c_device_addr *dev_addr = NULL; /* check arguments */ - if ((demod == NULL) || (freqOffset == NULL)) { + if ((demod == NULL) || (freq_offset == NULL)) { return DRX_STS_INVALID_ARG; } - devAddr = demod->myI2CDevAddr; - commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; + dev_addr = demod->my_i2c_dev_addr; + common_attr = (pdrx_common_attr_t) demod->my_common_attr; - *freqOffset = 0; + *freq_offset = 0; /* read sign (spectrum inversion) */ - RR16(devAddr, ORX_FWP_IQM_FRQ_W__A, &rot); + RR16(dev_addr, ORX_FWP_IQM_FRQ_W__A, &rot); /* read frequency offset */ - SARR16(devAddr, SCU_RAM_ORX_FRQ_OFFSET__A, &data); + SARR16(dev_addr, SCU_RAM_ORX_FRQ_OFFSET__A, &data); /* find COARSE frequency offset */ - /* coarseFreqOffset = ( 25312500Hz*FRQ_OFFSET >> 21 ); */ + /* coarse_freq_offset = ( 25312500Hz*FRQ_OFFSET >> 21 ); */ if (data & 0x8000) { data = (0xffff - data + 1); - coarseSign = -1; + coarse_sign = -1; } - Mult32(data, (commonAttr->sysClockFreq * 1000) / 6, &data64Hi, - &data64Lo); - tempFreqOffset = (((data64Lo >> 21) & 0x7ff) | (data64Hi << 11)); + mult32(data, (common_attr->sys_clock_freq * 1000) / 6, &data64hi, + &data64lo); + temp_freq_offset = (((data64lo >> 21) & 0x7ff) | (data64hi << 11)); /* get value in KHz */ - coarseFreqOffset = coarseSign * Frac(tempFreqOffset, 1000, FRAC_ROUND); /* KHz */ + coarse_freq_offset = coarse_sign * frac(temp_freq_offset, 1000, FRAC_ROUND); /* KHz */ /* read data rate */ - SARR16(devAddr, SCU_RAM_ORX_RF_RX_DATA_RATE__A, &symbolRateReg); - switch (symbolRateReg & SCU_RAM_ORX_RF_RX_DATA_RATE__M) { + SARR16(dev_addr, SCU_RAM_ORX_RF_RX_DATA_RATE__A, &symbol_rateReg); + switch (symbol_rateReg & SCU_RAM_ORX_RF_RX_DATA_RATE__M) { case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC: case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC: case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC_ALT: case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC_ALT: - symbolRate = 1024000; + symbol_rate = 1024000; break; case SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_REGSPEC: case SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_INVSPEC: - symbolRate = 772000; + symbol_rate = 772000; break; case SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_REGSPEC: case SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_INVSPEC: - symbolRate = 1544000; + symbol_rate = 1544000; break; default: return (DRX_STS_ERROR); } /* find FINE frequency offset */ - /* fineFreqOffset = ( (CORRECTION_VALUE*symbolRate) >> 18 ); */ - RR16(devAddr, ORX_CON_CPH_FRQ_R__A, &data); + /* fine_freq_offset = ( (CORRECTION_VALUE*symbol_rate) >> 18 ); */ + RR16(dev_addr, ORX_CON_CPH_FRQ_R__A, &data); /* at least 5 MSB are 0 so first divide with 2^5 without information loss */ - fineFreqOffset = (symbolRate >> 5); + fine_freq_offset = (symbol_rate >> 5); if (data & 0x8000) { - fineFreqOffset *= 0xffff - data + 1; /* Hz */ - fineSign = -1; + fine_freq_offset *= 0xffff - data + 1; /* Hz */ + fine_sign = -1; } else { - fineFreqOffset *= data; /* Hz */ + fine_freq_offset *= data; /* Hz */ } /* Left to divide with 8192 (2^13) */ - fineFreqOffset = Frac(fineFreqOffset, 8192, FRAC_ROUND); + fine_freq_offset = frac(fine_freq_offset, 8192, FRAC_ROUND); /* and to divide with 1000 to get KHz */ - fineFreqOffset = fineSign * Frac(fineFreqOffset, 1000, FRAC_ROUND); /* KHz */ + fine_freq_offset = fine_sign * frac(fine_freq_offset, 1000, FRAC_ROUND); /* KHz */ if ((rot & 0x8000) == 0x8000) - *freqOffset = -(coarseFreqOffset + fineFreqOffset); + *freq_offset = -(coarse_freq_offset + fine_freq_offset); else - *freqOffset = (coarseFreqOffset + fineFreqOffset); + *freq_offset = (coarse_freq_offset + fine_freq_offset); return (DRX_STS_OK); rw_error: @@ -12223,9 +12223,9 @@ rw_error: } /** -* \fn int GetOOBFrequency () +* \fn int get_oob_frequency () * \brief Get OOB frequency (Unit:KHz). -* \param devAddr I2C address +* \param dev_addr I2C address * \ frequency OOB frequency parameters. * \return int. * @@ -12233,24 +12233,24 @@ rw_error: * */ static int -GetOOBFrequency(pDRXDemodInstance_t demod, s32 *frequency) +get_oob_frequency(pdrx_demod_instance_t demod, s32 *frequency) { u16 data = 0; - s32 freqOffset = 0; + s32 freq_offset = 0; s32 freq = 0; - struct i2c_device_addr *devAddr = NULL; + struct i2c_device_addr *dev_addr = NULL; - devAddr = demod->myI2CDevAddr; + dev_addr = demod->my_i2c_dev_addr; *frequency = 0; /* KHz */ - SARR16(devAddr, SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__A, &data); + SARR16(dev_addr, SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__A, &data); freq = (s32) ((s32) data * 50 + 50000L); - CHK_ERROR(GetOOBFreqOffset(demod, &freqOffset)); + CHK_ERROR(get_oob_freq_offset(demod, &freq_offset)); - *frequency = freq + freqOffset; + *frequency = freq + freq_offset; return (DRX_STS_OK); rw_error: @@ -12258,22 +12258,22 @@ rw_error: } /** -* \fn int GetOOBMER () +* \fn int get_oobmer () * \brief Get OOB MER. -* \param devAddr I2C address +* \param dev_addr I2C address \ MER OOB parameter in dB. * \return int. * * Gets OOB MER. Table for MER is in Programming guide. * */ -static int GetOOBMER(struct i2c_device_addr *devAddr, u32 *mer) +static int get_oobmer(struct i2c_device_addr *dev_addr, u32 *mer) { u16 data = 0; *mer = 0; /* READ MER */ - RR16(devAddr, ORX_EQU_MER_MER_R__A, &data); + RR16(dev_addr, ORX_EQU_MER_MER_R__A, &data); switch (data) { case 0: /* fall through */ case 1: @@ -12402,23 +12402,23 @@ rw_error: #endif /*#ifndef DRXJ_DIGITAL_ONLY */ /** -* \fn int SetOrxNsuAox() +* \fn int set_orx_nsu_aox() * \brief Configure OrxNsuAox for OOB * \param demod instance of demodulator. * \param active * \return int. */ -static int SetOrxNsuAox(pDRXDemodInstance_t demod, bool active) +static int set_orx_nsu_aox(pdrx_demod_instance_t demod, bool active) { u16 data = 0; - struct i2c_device_addr *devAddr = NULL; - pDRXJData_t extAttr = NULL; + struct i2c_device_addr *dev_addr = NULL; + pdrxj_data_t ext_attr = NULL; - extAttr = (pDRXJData_t) demod->myExtAttr; - devAddr = demod->myI2CDevAddr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; + dev_addr = demod->my_i2c_dev_addr; /* Configure NSU_AOX */ - RR16(devAddr, ORX_NSU_AOX_STDBY_W__A, &data); + RR16(dev_addr, ORX_NSU_AOX_STDBY_W__A, &data); if (!active) { data &= ((~ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON) @@ -12440,7 +12440,7 @@ static int SetOrxNsuAox(pDRXDemodInstance_t demod, bool active) | ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON); } - WR16(devAddr, ORX_NSU_AOX_STDBY_W__A, data); + WR16(dev_addr, ORX_NSU_AOX_STDBY_W__A, data); return (DRX_STS_OK); rw_error: @@ -12448,15 +12448,15 @@ rw_error: } /** -* \fn int CtrlSetOOB() +* \fn int ctrl_set_oob() * \brief Set OOB channel to be used. * \param demod instance of demodulator -* \param oobParam OOB parameters for channel setting. +* \param oob_param OOB parameters for channel setting. * \frequency should be in KHz * \return int. * * Accepts only. Returns error otherwise. -* Demapper value is written after SCUCommand START +* Demapper value is written after scu_command START * because START command causes COMM_EXEC transition * from 0 to 1 which causes all registers to be * overwritten with initial value @@ -12471,27 +12471,27 @@ rw_error: /* Coefficients for the nyquist fitler (total: 27 taps) */ #define NYQFILTERLEN 27 -static int CtrlSetOOB(pDRXDemodInstance_t demod, pDRXOOB_t oobParam) +static int ctrl_set_oob(pdrx_demod_instance_t demod, p_drxoob_t oob_param) { #ifndef DRXJ_DIGITAL_ONLY - DRXOOBDownstreamStandard_t standard = DRX_OOB_MODE_A; + drxoob_downstream_standard_t standard = DRX_OOB_MODE_A; s32 freq = 0; /* KHz */ - struct i2c_device_addr *devAddr = NULL; - pDRXJData_t extAttr = NULL; + struct i2c_device_addr *dev_addr = NULL; + pdrxj_data_t ext_attr = NULL; u16 i = 0; - bool mirrorFreqSpectOOB = false; - u16 trkFilterValue = 0; - DRXJSCUCmd_t scuCmd; - u16 setParamParameters[3]; - u16 cmdResult[2] = { 0, 0 }; - s16 NyquistCoeffs[4][(NYQFILTERLEN + 1) / 2] = { + bool mirror_freq_spectOOB = false; + u16 trk_filter_value = 0; + drxjscu_cmd_t scu_cmd; + u16 set_param_parameters[3]; + u16 cmd_result[2] = { 0, 0 }; + s16 nyquist_coeffs[4][(NYQFILTERLEN + 1) / 2] = { IMPULSE_COSINE_ALPHA_0_3, /* Target Mode 0 */ IMPULSE_COSINE_ALPHA_0_3, /* Target Mode 1 */ IMPULSE_COSINE_ALPHA_0_5, /* Target Mode 2 */ IMPULSE_COSINE_ALPHA_RO_0_5 /* Target Mode 3 */ }; u8 mode_val[4] = { 2, 2, 0, 1 }; - u8 PFICoeffs[4][6] = { + u8 pfi_coeffs[4][6] = { {DRXJ_16TO8(-92), DRXJ_16TO8(-108), DRXJ_16TO8(100)}, /* TARGET_MODE = 0: PFI_A = -23/32; PFI_B = -54/32; PFI_C = 25/32; fg = 0.5 MHz (Att=26dB) */ {DRXJ_16TO8(-64), DRXJ_16TO8(-80), DRXJ_16TO8(80)}, /* TARGET_MODE = 1: PFI_A = -16/32; PFI_B = -40/32; PFI_C = 20/32; fg = 1.0 MHz (Att=28dB) */ {DRXJ_16TO8(-80), DRXJ_16TO8(-98), DRXJ_16TO8(92)}, /* TARGET_MODE = 2, 3: PFI_A = -20/32; PFI_B = -49/32; PFI_C = 23/32; fg = 0.8 MHz (Att=25dB) */ @@ -12499,29 +12499,29 @@ static int CtrlSetOOB(pDRXDemodInstance_t demod, pDRXOOB_t oobParam) }; u16 mode_index; - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; - mirrorFreqSpectOOB = extAttr->mirrorFreqSpectOOB; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; + mirror_freq_spectOOB = ext_attr->mirror_freq_spectOOB; /* Check parameters */ - if (oobParam == NULL) { + if (oob_param == NULL) { /* power off oob module */ - scuCmd.command = SCU_RAM_COMMAND_STANDARD_OOB + scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB | SCU_RAM_COMMAND_CMD_DEMOD_STOP; - scuCmd.parameterLen = 0; - scuCmd.resultLen = 1; - scuCmd.result = cmdResult; - CHK_ERROR(SCUCommand(devAddr, &scuCmd)); - CHK_ERROR(SetOrxNsuAox(demod, false)); - WR16(devAddr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP); - - extAttr->oobPowerOn = false; + scu_cmd.parameter_len = 0; + scu_cmd.result_len = 1; + scu_cmd.result = cmd_result; + CHK_ERROR(scu_command(dev_addr, &scu_cmd)); + CHK_ERROR(set_orx_nsu_aox(demod, false)); + WR16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP); + + ext_attr->oob_power_on = false; return (DRX_STS_OK); } - standard = oobParam->standard; + standard = oob_param->standard; - freq = oobParam->frequency; + freq = oob_param->frequency; if ((freq < 70000) || (freq > 130000)) return (DRX_STS_ERROR); freq = (freq - 50000) / 50; @@ -12529,13 +12529,13 @@ static int CtrlSetOOB(pDRXDemodInstance_t demod, pDRXOOB_t oobParam) { u16 index = 0; u16 remainder = 0; - u16 *trkFiltercfg = extAttr->oobTrkFilterCfg; + u16 *trk_filtercfg = ext_attr->oob_trk_filter_cfg; index = (u16) ((freq - 400) / 200); remainder = (u16) ((freq - 400) % 200); - trkFilterValue = - trkFiltercfg[index] - (trkFiltercfg[index] - - trkFiltercfg[index + + trk_filter_value = + trk_filtercfg[index] - (trk_filtercfg[index] - + trk_filtercfg[index + 1]) / 10 * remainder / 20; } @@ -12543,195 +12543,195 @@ static int CtrlSetOOB(pDRXDemodInstance_t demod, pDRXOOB_t oobParam) /*********/ /* Stop */ /*********/ - WR16(devAddr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP); - scuCmd.command = SCU_RAM_COMMAND_STANDARD_OOB + WR16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP); + scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB | SCU_RAM_COMMAND_CMD_DEMOD_STOP; - scuCmd.parameterLen = 0; - scuCmd.resultLen = 1; - scuCmd.result = cmdResult; - CHK_ERROR(SCUCommand(devAddr, &scuCmd)); + scu_cmd.parameter_len = 0; + scu_cmd.result_len = 1; + scu_cmd.result = cmd_result; + CHK_ERROR(scu_command(dev_addr, &scu_cmd)); /*********/ /* Reset */ /*********/ - scuCmd.command = SCU_RAM_COMMAND_STANDARD_OOB + scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB | SCU_RAM_COMMAND_CMD_DEMOD_RESET; - scuCmd.parameterLen = 0; - scuCmd.resultLen = 1; - scuCmd.result = cmdResult; - CHK_ERROR(SCUCommand(devAddr, &scuCmd)); + scu_cmd.parameter_len = 0; + scu_cmd.result_len = 1; + scu_cmd.result = cmd_result; + CHK_ERROR(scu_command(dev_addr, &scu_cmd)); /***********/ /* SET_ENV */ /***********/ /* set frequency, spectrum inversion and data rate */ - scuCmd.command = SCU_RAM_COMMAND_STANDARD_OOB + scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV; - scuCmd.parameterLen = 3; + scu_cmd.parameter_len = 3; /* 1-data rate;2-frequency */ - switch (oobParam->standard) { + switch (oob_param->standard) { case DRX_OOB_MODE_A: if ( /* signal is transmitted inverted */ - ((oobParam->spectrumInverted == true) & + ((oob_param->spectrum_inverted == true) & /* and tuner is not mirroring the signal */ - (mirrorFreqSpectOOB == false)) | + (mirror_freq_spectOOB == false)) | /* or */ /* signal is transmitted noninverted */ - ((oobParam->spectrumInverted == false) & + ((oob_param->spectrum_inverted == false) & /* and tuner is mirroring the signal */ - (mirrorFreqSpectOOB == true)) + (mirror_freq_spectOOB == true)) ) - setParamParameters[0] = + set_param_parameters[0] = SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC; else - setParamParameters[0] = + set_param_parameters[0] = SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC; break; case DRX_OOB_MODE_B_GRADE_A: if ( /* signal is transmitted inverted */ - ((oobParam->spectrumInverted == true) & + ((oob_param->spectrum_inverted == true) & /* and tuner is not mirroring the signal */ - (mirrorFreqSpectOOB == false)) | + (mirror_freq_spectOOB == false)) | /* or */ /* signal is transmitted noninverted */ - ((oobParam->spectrumInverted == false) & + ((oob_param->spectrum_inverted == false) & /* and tuner is mirroring the signal */ - (mirrorFreqSpectOOB == true)) + (mirror_freq_spectOOB == true)) ) - setParamParameters[0] = + set_param_parameters[0] = SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_INVSPEC; else - setParamParameters[0] = + set_param_parameters[0] = SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_REGSPEC; break; case DRX_OOB_MODE_B_GRADE_B: default: if ( /* signal is transmitted inverted */ - ((oobParam->spectrumInverted == true) & + ((oob_param->spectrum_inverted == true) & /* and tuner is not mirroring the signal */ - (mirrorFreqSpectOOB == false)) | + (mirror_freq_spectOOB == false)) | /* or */ /* signal is transmitted noninverted */ - ((oobParam->spectrumInverted == false) & + ((oob_param->spectrum_inverted == false) & /* and tuner is mirroring the signal */ - (mirrorFreqSpectOOB == true)) + (mirror_freq_spectOOB == true)) ) - setParamParameters[0] = + set_param_parameters[0] = SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_INVSPEC; else - setParamParameters[0] = + set_param_parameters[0] = SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_REGSPEC; break; } - setParamParameters[1] = (u16) (freq & 0xFFFF); - setParamParameters[2] = trkFilterValue; - scuCmd.parameter = setParamParameters; - scuCmd.resultLen = 1; - scuCmd.result = cmdResult; - mode_index = mode_val[(setParamParameters[0] & 0xC0) >> 6]; - CHK_ERROR(SCUCommand(devAddr, &scuCmd)); + set_param_parameters[1] = (u16) (freq & 0xFFFF); + set_param_parameters[2] = trk_filter_value; + scu_cmd.parameter = set_param_parameters; + scu_cmd.result_len = 1; + scu_cmd.result = cmd_result; + mode_index = mode_val[(set_param_parameters[0] & 0xC0) >> 6]; + CHK_ERROR(scu_command(dev_addr, &scu_cmd)); - WR16(devAddr, SIO_TOP_COMM_KEY__A, 0xFABA); /* Write magic word to enable pdr reg write */ - WR16(devAddr, SIO_PDR_OOB_CRX_CFG__A, + WR16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA); /* Write magic word to enable pdr reg write */ + WR16(dev_addr, SIO_PDR_OOB_CRX_CFG__A, OOB_CRX_DRIVE_STRENGTH << SIO_PDR_OOB_CRX_CFG_DRIVE__B | 0x03 << SIO_PDR_OOB_CRX_CFG_MODE__B); - WR16(devAddr, SIO_PDR_OOB_DRX_CFG__A, + WR16(dev_addr, SIO_PDR_OOB_DRX_CFG__A, OOB_DRX_DRIVE_STRENGTH << SIO_PDR_OOB_DRX_CFG_DRIVE__B | 0x03 << SIO_PDR_OOB_DRX_CFG_MODE__B); - WR16(devAddr, SIO_TOP_COMM_KEY__A, 0x0000); /* Write magic word to disable pdr reg write */ + WR16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000); /* Write magic word to disable pdr reg write */ - WR16(devAddr, ORX_TOP_COMM_KEY__A, 0); - WR16(devAddr, ORX_FWP_AAG_LEN_W__A, 16000); - WR16(devAddr, ORX_FWP_AAG_THR_W__A, 40); + WR16(dev_addr, ORX_TOP_COMM_KEY__A, 0); + WR16(dev_addr, ORX_FWP_AAG_LEN_W__A, 16000); + WR16(dev_addr, ORX_FWP_AAG_THR_W__A, 40); /* ddc */ - WR16(devAddr, ORX_DDC_OFO_SET_W__A, ORX_DDC_OFO_SET_W__PRE); + WR16(dev_addr, ORX_DDC_OFO_SET_W__A, ORX_DDC_OFO_SET_W__PRE); /* nsu */ - WR16(devAddr, ORX_NSU_AOX_LOPOW_W__A, extAttr->oobLoPow); + WR16(dev_addr, ORX_NSU_AOX_LOPOW_W__A, ext_attr->oob_lo_pow); /* initialization for target mode */ - WR16(devAddr, SCU_RAM_ORX_TARGET_MODE__A, + WR16(dev_addr, SCU_RAM_ORX_TARGET_MODE__A, SCU_RAM_ORX_TARGET_MODE_2048KBPS_SQRT); - WR16(devAddr, SCU_RAM_ORX_FREQ_GAIN_CORR__A, + WR16(dev_addr, SCU_RAM_ORX_FREQ_GAIN_CORR__A, SCU_RAM_ORX_FREQ_GAIN_CORR_2048KBPS); /* Reset bits for timing and freq. recovery */ - WR16(devAddr, SCU_RAM_ORX_RST_CPH__A, 0x0001); - WR16(devAddr, SCU_RAM_ORX_RST_CTI__A, 0x0002); - WR16(devAddr, SCU_RAM_ORX_RST_KRN__A, 0x0004); - WR16(devAddr, SCU_RAM_ORX_RST_KRP__A, 0x0008); + WR16(dev_addr, SCU_RAM_ORX_RST_CPH__A, 0x0001); + WR16(dev_addr, SCU_RAM_ORX_RST_CTI__A, 0x0002); + WR16(dev_addr, SCU_RAM_ORX_RST_KRN__A, 0x0004); + WR16(dev_addr, SCU_RAM_ORX_RST_KRP__A, 0x0008); /* AGN_LOCK = {2048>>3, -2048, 8, -8, 0, 1}; */ - WR16(devAddr, SCU_RAM_ORX_AGN_LOCK_TH__A, 2048 >> 3); - WR16(devAddr, SCU_RAM_ORX_AGN_LOCK_TOTH__A, (u16) (-2048)); - WR16(devAddr, SCU_RAM_ORX_AGN_ONLOCK_TTH__A, 8); - WR16(devAddr, SCU_RAM_ORX_AGN_UNLOCK_TTH__A, (u16) (-8)); - WR16(devAddr, SCU_RAM_ORX_AGN_LOCK_MASK__A, 1); + WR16(dev_addr, SCU_RAM_ORX_AGN_LOCK_TH__A, 2048 >> 3); + WR16(dev_addr, SCU_RAM_ORX_AGN_LOCK_TOTH__A, (u16) (-2048)); + WR16(dev_addr, SCU_RAM_ORX_AGN_ONLOCK_TTH__A, 8); + WR16(dev_addr, SCU_RAM_ORX_AGN_UNLOCK_TTH__A, (u16) (-8)); + WR16(dev_addr, SCU_RAM_ORX_AGN_LOCK_MASK__A, 1); /* DGN_LOCK = {10, -2048, 8, -8, 0, 1<<1}; */ - WR16(devAddr, SCU_RAM_ORX_DGN_LOCK_TH__A, 10); - WR16(devAddr, SCU_RAM_ORX_DGN_LOCK_TOTH__A, (u16) (-2048)); - WR16(devAddr, SCU_RAM_ORX_DGN_ONLOCK_TTH__A, 8); - WR16(devAddr, SCU_RAM_ORX_DGN_UNLOCK_TTH__A, (u16) (-8)); - WR16(devAddr, SCU_RAM_ORX_DGN_LOCK_MASK__A, 1 << 1); + WR16(dev_addr, SCU_RAM_ORX_DGN_LOCK_TH__A, 10); + WR16(dev_addr, SCU_RAM_ORX_DGN_LOCK_TOTH__A, (u16) (-2048)); + WR16(dev_addr, SCU_RAM_ORX_DGN_ONLOCK_TTH__A, 8); + WR16(dev_addr, SCU_RAM_ORX_DGN_UNLOCK_TTH__A, (u16) (-8)); + WR16(dev_addr, SCU_RAM_ORX_DGN_LOCK_MASK__A, 1 << 1); /* FRQ_LOCK = {15,-2048, 8, -8, 0, 1<<2}; */ - WR16(devAddr, SCU_RAM_ORX_FRQ_LOCK_TH__A, 17); - WR16(devAddr, SCU_RAM_ORX_FRQ_LOCK_TOTH__A, (u16) (-2048)); - WR16(devAddr, SCU_RAM_ORX_FRQ_ONLOCK_TTH__A, 8); - WR16(devAddr, SCU_RAM_ORX_FRQ_UNLOCK_TTH__A, (u16) (-8)); - WR16(devAddr, SCU_RAM_ORX_FRQ_LOCK_MASK__A, 1 << 2); + WR16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TH__A, 17); + WR16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TOTH__A, (u16) (-2048)); + WR16(dev_addr, SCU_RAM_ORX_FRQ_ONLOCK_TTH__A, 8); + WR16(dev_addr, SCU_RAM_ORX_FRQ_UNLOCK_TTH__A, (u16) (-8)); + WR16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_MASK__A, 1 << 2); /* PHA_LOCK = {5000, -2048, 8, -8, 0, 1<<3}; */ - WR16(devAddr, SCU_RAM_ORX_PHA_LOCK_TH__A, 3000); - WR16(devAddr, SCU_RAM_ORX_PHA_LOCK_TOTH__A, (u16) (-2048)); - WR16(devAddr, SCU_RAM_ORX_PHA_ONLOCK_TTH__A, 8); - WR16(devAddr, SCU_RAM_ORX_PHA_UNLOCK_TTH__A, (u16) (-8)); - WR16(devAddr, SCU_RAM_ORX_PHA_LOCK_MASK__A, 1 << 3); + WR16(dev_addr, SCU_RAM_ORX_PHA_LOCK_TH__A, 3000); + WR16(dev_addr, SCU_RAM_ORX_PHA_LOCK_TOTH__A, (u16) (-2048)); + WR16(dev_addr, SCU_RAM_ORX_PHA_ONLOCK_TTH__A, 8); + WR16(dev_addr, SCU_RAM_ORX_PHA_UNLOCK_TTH__A, (u16) (-8)); + WR16(dev_addr, SCU_RAM_ORX_PHA_LOCK_MASK__A, 1 << 3); /* TIM_LOCK = {300, -2048, 8, -8, 0, 1<<4}; */ - WR16(devAddr, SCU_RAM_ORX_TIM_LOCK_TH__A, 400); - WR16(devAddr, SCU_RAM_ORX_TIM_LOCK_TOTH__A, (u16) (-2048)); - WR16(devAddr, SCU_RAM_ORX_TIM_ONLOCK_TTH__A, 8); - WR16(devAddr, SCU_RAM_ORX_TIM_UNLOCK_TTH__A, (u16) (-8)); - WR16(devAddr, SCU_RAM_ORX_TIM_LOCK_MASK__A, 1 << 4); + WR16(dev_addr, SCU_RAM_ORX_TIM_LOCK_TH__A, 400); + WR16(dev_addr, SCU_RAM_ORX_TIM_LOCK_TOTH__A, (u16) (-2048)); + WR16(dev_addr, SCU_RAM_ORX_TIM_ONLOCK_TTH__A, 8); + WR16(dev_addr, SCU_RAM_ORX_TIM_UNLOCK_TTH__A, (u16) (-8)); + WR16(dev_addr, SCU_RAM_ORX_TIM_LOCK_MASK__A, 1 << 4); /* EQU_LOCK = {20, -2048, 8, -8, 0, 1<<5}; */ - WR16(devAddr, SCU_RAM_ORX_EQU_LOCK_TH__A, 20); - WR16(devAddr, SCU_RAM_ORX_EQU_LOCK_TOTH__A, (u16) (-2048)); - WR16(devAddr, SCU_RAM_ORX_EQU_ONLOCK_TTH__A, 4); - WR16(devAddr, SCU_RAM_ORX_EQU_UNLOCK_TTH__A, (u16) (-4)); - WR16(devAddr, SCU_RAM_ORX_EQU_LOCK_MASK__A, 1 << 5); + WR16(dev_addr, SCU_RAM_ORX_EQU_LOCK_TH__A, 20); + WR16(dev_addr, SCU_RAM_ORX_EQU_LOCK_TOTH__A, (u16) (-2048)); + WR16(dev_addr, SCU_RAM_ORX_EQU_ONLOCK_TTH__A, 4); + WR16(dev_addr, SCU_RAM_ORX_EQU_UNLOCK_TTH__A, (u16) (-4)); + WR16(dev_addr, SCU_RAM_ORX_EQU_LOCK_MASK__A, 1 << 5); /* PRE-Filter coefficients (PFI) */ - WRB(devAddr, ORX_FWP_PFI_A_W__A, sizeof(PFICoeffs[mode_index]), - ((u8 *) PFICoeffs[mode_index])); - WR16(devAddr, ORX_TOP_MDE_W__A, mode_index); + WRB(dev_addr, ORX_FWP_PFI_A_W__A, sizeof(pfi_coeffs[mode_index]), + ((u8 *) pfi_coeffs[mode_index])); + WR16(dev_addr, ORX_TOP_MDE_W__A, mode_index); /* NYQUIST-Filter coefficients (NYQ) */ for (i = 0; i < (NYQFILTERLEN + 1) / 2; i++) { - WR16(devAddr, ORX_FWP_NYQ_ADR_W__A, i); - WR16(devAddr, ORX_FWP_NYQ_COF_RW__A, - NyquistCoeffs[mode_index][i]); + WR16(dev_addr, ORX_FWP_NYQ_ADR_W__A, i); + WR16(dev_addr, ORX_FWP_NYQ_COF_RW__A, + nyquist_coeffs[mode_index][i]); } - WR16(devAddr, ORX_FWP_NYQ_ADR_W__A, 31); - WR16(devAddr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_ACTIVE); + WR16(dev_addr, ORX_FWP_NYQ_ADR_W__A, 31); + WR16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_ACTIVE); /*********/ /* Start */ /*********/ - scuCmd.command = SCU_RAM_COMMAND_STANDARD_OOB + scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB | SCU_RAM_COMMAND_CMD_DEMOD_START; - scuCmd.parameterLen = 0; - scuCmd.resultLen = 1; - scuCmd.result = cmdResult; - CHK_ERROR(SCUCommand(devAddr, &scuCmd)); + scu_cmd.parameter_len = 0; + scu_cmd.result_len = 1; + scu_cmd.result = cmd_result; + CHK_ERROR(scu_command(dev_addr, &scu_cmd)); - CHK_ERROR(SetOrxNsuAox(demod, true)); - WR16(devAddr, ORX_NSU_AOX_STHR_W__A, extAttr->oobPreSaw); + CHK_ERROR(set_orx_nsu_aox(demod, true)); + WR16(dev_addr, ORX_NSU_AOX_STHR_W__A, ext_attr->oob_pre_saw); - extAttr->oobPowerOn = true; + ext_attr->oob_power_on = true; return (DRX_STS_OK); rw_error: @@ -12740,42 +12740,42 @@ rw_error: } /** -* \fn int CtrlGetOOB() +* \fn int ctrl_get_oob() * \brief Set modulation standard to be used. * \param demod instance of demodulator -* \param oobStatus OOB status parameters. +* \param oob_status OOB status parameters. * \return int. */ static int -CtrlGetOOB(pDRXDemodInstance_t demod, pDRXOOBStatus_t oobStatus) +ctrl_get_oob(pdrx_demod_instance_t demod, pdrxoob_status_t oob_status) { #ifndef DRXJ_DIGITAL_ONLY - struct i2c_device_addr *devAddr = NULL; - pDRXJData_t extAttr = NULL; + struct i2c_device_addr *dev_addr = NULL; + pdrxj_data_t ext_attr = NULL; u16 data = 0; - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* check arguments */ - if (oobStatus == NULL) { + if (oob_status == NULL) { return (DRX_STS_INVALID_ARG); } - if (extAttr->oobPowerOn == false) + if (ext_attr->oob_power_on == false) return (DRX_STS_ERROR); - RR16(devAddr, ORX_DDC_OFO_SET_W__A, &data); - RR16(devAddr, ORX_NSU_TUN_RFGAIN_W__A, &data); - RR16(devAddr, ORX_FWP_AAG_THR_W__A, &data); - SARR16(devAddr, SCU_RAM_ORX_DGN_KI__A, &data); - RR16(devAddr, ORX_FWP_SRC_DGN_W__A, &data); + RR16(dev_addr, ORX_DDC_OFO_SET_W__A, &data); + RR16(dev_addr, ORX_NSU_TUN_RFGAIN_W__A, &data); + RR16(dev_addr, ORX_FWP_AAG_THR_W__A, &data); + SARR16(dev_addr, SCU_RAM_ORX_DGN_KI__A, &data); + RR16(dev_addr, ORX_FWP_SRC_DGN_W__A, &data); - CHK_ERROR(GetOOBLockStatus(demod, devAddr, &oobStatus->lock)); - CHK_ERROR(GetOOBFrequency(demod, &oobStatus->frequency)); - CHK_ERROR(GetOOBMER(devAddr, &oobStatus->mer)); - CHK_ERROR(GetOOBSymbolRateOffset - (devAddr, &oobStatus->symbolRateOffset)); + CHK_ERROR(get_oob_lock_status(demod, dev_addr, &oob_status->lock)); + CHK_ERROR(get_oob_frequency(demod, &oob_status->frequency)); + CHK_ERROR(get_oobmer(dev_addr, &oob_status->mer)); + CHK_ERROR(get_oob_symbol_rate_offset + (dev_addr, &oob_status->symbol_rate_offset)); return (DRX_STS_OK); rw_error: @@ -12784,26 +12784,26 @@ rw_error: } /** -* \fn int CtrlSetCfgOOBPreSAW() +* \fn int ctrl_set_cfg_oob_pre_saw() * \brief Configure PreSAW treshold value -* \param cfgData Pointer to configuration parameter +* \param cfg_data Pointer to configuration parameter * \return Error code */ #ifndef DRXJ_DIGITAL_ONLY static int -CtrlSetCfgOOBPreSAW(pDRXDemodInstance_t demod, u16 *cfgData) +ctrl_set_cfg_oob_pre_saw(pdrx_demod_instance_t demod, u16 *cfg_data) { - struct i2c_device_addr *devAddr = NULL; - pDRXJData_t extAttr = NULL; + struct i2c_device_addr *dev_addr = NULL; + pdrxj_data_t ext_attr = NULL; - if (cfgData == NULL) { + if (cfg_data == NULL) { return (DRX_STS_INVALID_ARG); } - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; - WR16(devAddr, ORX_NSU_AOX_STHR_W__A, *cfgData); - extAttr->oobPreSaw = *cfgData; + WR16(dev_addr, ORX_NSU_AOX_STHR_W__A, *cfg_data); + ext_attr->oob_pre_saw = *cfg_data; return (DRX_STS_OK); rw_error: return (DRX_STS_ERROR); @@ -12811,49 +12811,49 @@ rw_error: #endif /** -* \fn int CtrlGetCfgOOBPreSAW() +* \fn int ctrl_get_cfg_oob_pre_saw() * \brief Configure PreSAW treshold value -* \param cfgData Pointer to configuration parameter +* \param cfg_data Pointer to configuration parameter * \return Error code */ #ifndef DRXJ_DIGITAL_ONLY static int -CtrlGetCfgOOBPreSAW(pDRXDemodInstance_t demod, u16 *cfgData) +ctrl_get_cfg_oob_pre_saw(pdrx_demod_instance_t demod, u16 *cfg_data) { - pDRXJData_t extAttr = NULL; + pdrxj_data_t ext_attr = NULL; - if (cfgData == NULL) { + if (cfg_data == NULL) { return (DRX_STS_INVALID_ARG); } - extAttr = (pDRXJData_t) demod->myExtAttr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; - *cfgData = extAttr->oobPreSaw; + *cfg_data = ext_attr->oob_pre_saw; return (DRX_STS_OK); } #endif /** -* \fn int CtrlSetCfgOOBLoPower() +* \fn int ctrl_set_cfg_oob_lo_power() * \brief Configure LO Power value -* \param cfgData Pointer to pDRXJCfgOobLoPower_t +* \param cfg_data Pointer to p_drxj_cfg_oob_lo_power_t * \return Error code */ #ifndef DRXJ_DIGITAL_ONLY static int -CtrlSetCfgOOBLoPower(pDRXDemodInstance_t demod, pDRXJCfgOobLoPower_t cfgData) +ctrl_set_cfg_oob_lo_power(pdrx_demod_instance_t demod, p_drxj_cfg_oob_lo_power_t cfg_data) { - struct i2c_device_addr *devAddr = NULL; - pDRXJData_t extAttr = NULL; + struct i2c_device_addr *dev_addr = NULL; + pdrxj_data_t ext_attr = NULL; - if (cfgData == NULL) { + if (cfg_data == NULL) { return (DRX_STS_INVALID_ARG); } - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; - WR16(devAddr, ORX_NSU_AOX_LOPOW_W__A, *cfgData); - extAttr->oobLoPow = *cfgData; + WR16(dev_addr, ORX_NSU_AOX_LOPOW_W__A, *cfg_data); + ext_attr->oob_lo_pow = *cfg_data; return (DRX_STS_OK); rw_error: return (DRX_STS_ERROR); @@ -12861,23 +12861,23 @@ rw_error: #endif /** -* \fn int CtrlGetCfgOOBLoPower() +* \fn int ctrl_get_cfg_oob_lo_power() * \brief Configure LO Power value -* \param cfgData Pointer to pDRXJCfgOobLoPower_t +* \param cfg_data Pointer to p_drxj_cfg_oob_lo_power_t * \return Error code */ #ifndef DRXJ_DIGITAL_ONLY static int -CtrlGetCfgOOBLoPower(pDRXDemodInstance_t demod, pDRXJCfgOobLoPower_t cfgData) +ctrl_get_cfg_oob_lo_power(pdrx_demod_instance_t demod, p_drxj_cfg_oob_lo_power_t cfg_data) { - pDRXJData_t extAttr = NULL; + pdrxj_data_t ext_attr = NULL; - if (cfgData == NULL) { + if (cfg_data == NULL) { return (DRX_STS_INVALID_ARG); } - extAttr = (pDRXJData_t) demod->myExtAttr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; - *cfgData = extAttr->oobLoPow; + *cfg_data = ext_attr->oob_lo_pow; return (DRX_STS_OK); } @@ -12891,10 +12891,10 @@ CtrlGetCfgOOBLoPower(pDRXDemodInstance_t demod, pDRXJCfgOobLoPower_t cfgData) ===========================================================================*/ /*============================================================================= - ===== CtrlSetChannel() ========================================================== + ===== ctrl_set_channel() ========================================================== ===========================================================================*/ /** -* \fn int CtrlSetChannel() +* \fn int ctrl_set_channel() * \brief Select a new transmission channel. * \param demod instance of demod. * \param channel Pointer to channel data. @@ -12905,23 +12905,23 @@ CtrlGetCfgOOBLoPower(pDRXDemodInstance_t demod, pDRXJCfgOobLoPower_t cfgData) * */ static int -CtrlSetChannel(pDRXDemodInstance_t demod, pDRXChannel_t channel) +ctrl_set_channel(pdrx_demod_instance_t demod, pdrx_channel_t channel) { - s32 tunerSetFreq = 0; - s32 tunerGetFreq = 0; - s32 tunerFreqOffset = 0; - s32 intermediateFreq = 0; - pDRXJData_t extAttr = NULL; - struct i2c_device_addr *devAddr = NULL; + s32 tuner_set_freq = 0; + s32 tuner_get_freq = 0; + s32 tuner_freq_offset = 0; + s32 intermediate_freq = 0; + pdrxj_data_t ext_attr = NULL; + struct i2c_device_addr *dev_addr = NULL; enum drx_standard standard = DRX_STANDARD_UNKNOWN; - u32 tunerMode = 0; - pDRXCommonAttr_t commonAttr = NULL; - bool bridgeClosed = false; + u32 tuner_mode = 0; + pdrx_common_attr_t common_attr = NULL; + bool bridge_closed = false; #ifndef DRXJ_VSB_ONLY - u32 minSymbolRate = 0; - u32 maxSymbolRate = 0; - int bandwidthTemp = 0; + u32 min_symbol_rate = 0; + u32 max_symbol_rate = 0; + int bandwidth_temp = 0; int bandwidth = 0; #endif /*== check arguments ======================================================*/ @@ -12929,10 +12929,10 @@ CtrlSetChannel(pDRXDemodInstance_t demod, pDRXChannel_t channel) return DRX_STS_INVALID_ARG; } - commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; - standard = extAttr->standard; + common_attr = (pdrx_common_attr_t) demod->my_common_attr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; + standard = ext_attr->standard; /* check valid standards */ switch (standard) { @@ -13011,17 +13011,17 @@ CtrlSetChannel(pDRXDemodInstance_t demod, pDRXChannel_t channel) #ifndef DRXJ_VSB_ONLY if ((standard == DRX_STANDARD_ITU_A) || (standard == DRX_STANDARD_ITU_C)) { - DRXUIOCfg_t UIOCfg = { DRX_UIO1, DRX_UIO_MODE_FIRMWARE_SAW }; - int bwRolloffFactor = 0; + drxuio_cfg_t uio_cfg = { DRX_UIO1, DRX_UIO_MODE_FIRMWARE_SAW }; + int bw_rolloff_factor = 0; - bwRolloffFactor = (standard == DRX_STANDARD_ITU_A) ? 115 : 113; - minSymbolRate = DRXJ_QAM_SYMBOLRATE_MIN; - maxSymbolRate = DRXJ_QAM_SYMBOLRATE_MAX; + bw_rolloff_factor = (standard == DRX_STANDARD_ITU_A) ? 115 : 113; + min_symbol_rate = DRXJ_QAM_SYMBOLRATE_MIN; + max_symbol_rate = DRXJ_QAM_SYMBOLRATE_MAX; /* config SMA_TX pin to SAW switch mode */ - CHK_ERROR(CtrlSetUIOCfg(demod, &UIOCfg)); + CHK_ERROR(ctrl_set_uio_cfg(demod, &uio_cfg)); - if (channel->symbolrate < minSymbolRate || - channel->symbolrate > maxSymbolRate) { + if (channel->symbolrate < min_symbol_rate || + channel->symbolrate > max_symbol_rate) { return (DRX_STS_INVALID_ARG); } @@ -13031,10 +13031,10 @@ CtrlSetChannel(pDRXDemodInstance_t demod, pDRXChannel_t channel) case DRX_CONSTELLATION_QAM64: /* fall through */ case DRX_CONSTELLATION_QAM128: /* fall through */ case DRX_CONSTELLATION_QAM256: - bandwidthTemp = channel->symbolrate * bwRolloffFactor; - bandwidth = bandwidthTemp / 100; + bandwidth_temp = channel->symbolrate * bw_rolloff_factor; + bandwidth = bandwidth_temp / 100; - if ((bandwidthTemp % 100) >= 50) { + if ((bandwidth_temp % 100) >= 50) { bandwidth++; } @@ -13091,9 +13091,9 @@ CtrlSetChannel(pDRXDemodInstance_t demod, pDRXChannel_t channel) } } - if ((extAttr->uioSmaTxMode) == DRX_UIO_MODE_FIRMWARE_SAW) { + if ((ext_attr->uio_sma_tx_mode) == DRX_UIO_MODE_FIRMWARE_SAW) { /* SAW SW, user UIO is used for switchable SAW */ - DRXUIOData_t uio1 = { DRX_UIO1, false }; + drxuio_data_t uio1 = { DRX_UIO1, false }; switch (channel->bandwidth) { case DRX_BANDWIDTH_8MHZ: @@ -13110,12 +13110,12 @@ CtrlSetChannel(pDRXDemodInstance_t demod, pDRXChannel_t channel) return (DRX_STS_INVALID_ARG); } - CHK_ERROR(CtrlUIOWrite(demod, &uio1)); + CHK_ERROR(ctrl_uio_write(demod, &uio1)); } #endif /* DRXJ_VSB_ONLY */ - WR16(devAddr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); + WR16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); /*== Tune, fast mode ======================================================*/ - if (demod->myTuner != NULL) { + if (demod->my_tuner != NULL) { /* Determine tuner mode and freq to tune to ... */ switch (standard) { #ifndef DRXJ_DIGITAL_ONLY @@ -13127,14 +13127,14 @@ CtrlSetChannel(pDRXDemodInstance_t demod, pDRXChannel_t channel) case DRX_STANDARD_PAL_SECAM_LP: /* expecting center frequency, not picture carrier so no conversion .... */ - tunerMode |= TUNER_MODE_ANALOG; - tunerSetFreq = channel->frequency; + tuner_mode |= TUNER_MODE_ANALOG; + tuner_set_freq = channel->frequency; break; case DRX_STANDARD_FM: /* center frequency (equals sound carrier) as input, tune to edge of SAW */ - tunerMode |= TUNER_MODE_ANALOG; - tunerSetFreq = + tuner_mode |= TUNER_MODE_ANALOG; + tuner_set_freq = channel->frequency + DRXJ_FM_CARRIER_FREQ_OFFSET; break; #endif @@ -13144,77 +13144,77 @@ CtrlSetChannel(pDRXDemodInstance_t demod, pDRXChannel_t channel) case DRX_STANDARD_ITU_B: /* fallthrough */ case DRX_STANDARD_ITU_C: #endif - tunerMode |= TUNER_MODE_DIGITAL; - tunerSetFreq = channel->frequency; + tuner_mode |= TUNER_MODE_DIGITAL; + tuner_set_freq = channel->frequency; break; case DRX_STANDARD_UNKNOWN: default: return (DRX_STS_ERROR); } /* switch(standard) */ - tunerMode |= TUNER_MODE_SWITCH; + tuner_mode |= TUNER_MODE_SWITCH; switch (channel->bandwidth) { case DRX_BANDWIDTH_8MHZ: - tunerMode |= TUNER_MODE_8MHZ; + tuner_mode |= TUNER_MODE_8MHZ; break; case DRX_BANDWIDTH_7MHZ: - tunerMode |= TUNER_MODE_7MHZ; + tuner_mode |= TUNER_MODE_7MHZ; break; case DRX_BANDWIDTH_6MHZ: - tunerMode |= TUNER_MODE_6MHZ; + tuner_mode |= TUNER_MODE_6MHZ; break; default: /* TODO: for FM which bandwidth to use ? also check offset from centre frequency ? For now using 6MHz. */ - tunerMode |= TUNER_MODE_6MHZ; + tuner_mode |= TUNER_MODE_6MHZ; break; /* return (DRX_STS_INVALID_ARG); */ } /* store bandwidth for GetChannel() */ - extAttr->currBandwidth = channel->bandwidth; - extAttr->currSymbolRate = channel->symbolrate; - extAttr->frequency = tunerSetFreq; - if (commonAttr->tunerPortNr == 1) { + ext_attr->curr_bandwidth = channel->bandwidth; + ext_attr->curr_symbol_rate = channel->symbolrate; + ext_attr->frequency = tuner_set_freq; + if (common_attr->tuner_port_nr == 1) { /* close tuner bridge */ - bridgeClosed = true; - CHK_ERROR(CtrlI2CBridge(demod, &bridgeClosed)); + bridge_closed = true; + CHK_ERROR(ctrl_i2c_bridge(demod, &bridge_closed)); /* set tuner frequency */ } - CHK_ERROR(DRXBSP_TUNER_SetFrequency(demod->myTuner, - tunerMode, tunerSetFreq)); - if (commonAttr->tunerPortNr == 1) { + CHK_ERROR(drxbsp_tuner_set_frequency(demod->my_tuner, + tuner_mode, tuner_set_freq)); + if (common_attr->tuner_port_nr == 1) { /* open tuner bridge */ - bridgeClosed = false; - CHK_ERROR(CtrlI2CBridge(demod, &bridgeClosed)); + bridge_closed = false; + CHK_ERROR(ctrl_i2c_bridge(demod, &bridge_closed)); } /* Get actual frequency set by tuner and compute offset */ - CHK_ERROR(DRXBSP_TUNER_GetFrequency(demod->myTuner, + CHK_ERROR(drxbsp_tuner_get_frequency(demod->my_tuner, 0, - &tunerGetFreq, - &intermediateFreq)); - tunerFreqOffset = tunerGetFreq - tunerSetFreq; - commonAttr->intermediateFreq = intermediateFreq; + &tuner_get_freq, + &intermediate_freq)); + tuner_freq_offset = tuner_get_freq - tuner_set_freq; + common_attr->intermediate_freq = intermediate_freq; } else { /* no tuner instance defined, use fixed intermediate frequency */ - tunerFreqOffset = 0; - intermediateFreq = demod->myCommonAttr->intermediateFreq; - } /* if ( demod->myTuner != NULL ) */ + tuner_freq_offset = 0; + intermediate_freq = demod->my_common_attr->intermediate_freq; + } /* if ( demod->my_tuner != NULL ) */ /*== Setup demod for specific standard ====================================*/ switch (standard) { case DRX_STANDARD_8VSB: if (channel->mirror == DRX_MIRROR_AUTO) { - extAttr->mirror = DRX_MIRROR_NO; + ext_attr->mirror = DRX_MIRROR_NO; } else { - extAttr->mirror = channel->mirror; + ext_attr->mirror = channel->mirror; } - CHK_ERROR(SetVSB(demod)); - CHK_ERROR(SetFrequency(demod, channel, tunerFreqOffset)); + CHK_ERROR(set_vsb(demod)); + CHK_ERROR(set_frequency(demod, channel, tuner_freq_offset)); break; #ifndef DRXJ_DIGITAL_ONLY case DRX_STANDARD_NTSC: /* fallthrough */ @@ -13225,19 +13225,19 @@ CtrlSetChannel(pDRXDemodInstance_t demod, pDRXChannel_t channel) case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */ case DRX_STANDARD_PAL_SECAM_LP: if (channel->mirror == DRX_MIRROR_AUTO) { - extAttr->mirror = DRX_MIRROR_NO; + ext_attr->mirror = DRX_MIRROR_NO; } else { - extAttr->mirror = channel->mirror; + ext_attr->mirror = channel->mirror; } - CHK_ERROR(SetATVChannel(demod, - tunerFreqOffset, channel, standard)); + CHK_ERROR(set_atv_channel(demod, + tuner_freq_offset, channel, standard)); break; #endif #ifndef DRXJ_VSB_ONLY case DRX_STANDARD_ITU_A: /* fallthrough */ case DRX_STANDARD_ITU_B: /* fallthrough */ case DRX_STANDARD_ITU_C: - CHK_ERROR(SetQAMChannel(demod, channel, tunerFreqOffset)); + CHK_ERROR(set_qamChannel(demod, channel, tuner_freq_offset)); break; #endif case DRX_STANDARD_UNKNOWN: @@ -13246,30 +13246,30 @@ CtrlSetChannel(pDRXDemodInstance_t demod, pDRXChannel_t channel) } /*== Re-tune, slow mode ===================================================*/ - if (demod->myTuner != NULL) { + if (demod->my_tuner != NULL) { /* tune to slow mode */ - tunerMode &= ~TUNER_MODE_SWITCH; - tunerMode |= TUNER_MODE_LOCK; + tuner_mode &= ~TUNER_MODE_SWITCH; + tuner_mode |= TUNER_MODE_LOCK; - if (commonAttr->tunerPortNr == 1) { + if (common_attr->tuner_port_nr == 1) { /* close tuner bridge */ - bridgeClosed = true; - CHK_ERROR(CtrlI2CBridge(demod, &bridgeClosed)); + bridge_closed = true; + CHK_ERROR(ctrl_i2c_bridge(demod, &bridge_closed)); } /* set tuner frequency */ - CHK_ERROR(DRXBSP_TUNER_SetFrequency(demod->myTuner, - tunerMode, tunerSetFreq)); - if (commonAttr->tunerPortNr == 1) { + CHK_ERROR(drxbsp_tuner_set_frequency(demod->my_tuner, + tuner_mode, tuner_set_freq)); + if (common_attr->tuner_port_nr == 1) { /* open tuner bridge */ - bridgeClosed = false; - CHK_ERROR(CtrlI2CBridge(demod, &bridgeClosed)); + bridge_closed = false; + CHK_ERROR(ctrl_i2c_bridge(demod, &bridge_closed)); } } - /* if ( demod->myTuner !=NULL ) */ + /* if ( demod->my_tuner !=NULL ) */ /* flag the packet error counter reset */ - extAttr->resetPktErrAcc = true; + ext_attr->reset_pkt_err_acc = true; return (DRX_STS_OK); rw_error: @@ -13277,29 +13277,29 @@ rw_error: } /*============================================================================= - ===== CtrlGetChannel() ========================================================== + ===== ctrl_get_channel() ========================================================== ===========================================================================*/ /** -* \fn int CtrlGetChannel() +* \fn int ctrl_get_channel() * \brief Retreive parameters of current transmission channel. * \param demod Pointer to demod instance. * \param channel Pointer to channel data. * \return int. */ static int -CtrlGetChannel(pDRXDemodInstance_t demod, pDRXChannel_t channel) +ctrl_get_channel(pdrx_demod_instance_t demod, pdrx_channel_t channel) { - struct i2c_device_addr *devAddr = NULL; - pDRXJData_t extAttr = NULL; - DRXLockStatus_t lockStatus = DRX_NOT_LOCKED; + struct i2c_device_addr *dev_addr = NULL; + pdrxj_data_t ext_attr = NULL; + drx_lock_status_t lock_status = DRX_NOT_LOCKED; enum drx_standard standard = DRX_STANDARD_UNKNOWN; - pDRXCommonAttr_t commonAttr = NULL; - s32 intermediateFreq = 0; - s32 CTLFreqOffset = 0; - u32 iqmRcRateLo = 0; - u32 adcFrequency = 0; + pdrx_common_attr_t common_attr = NULL; + s32 intermediate_freq = 0; + s32 ctl_freq_offset = 0; + u32 iqm_rc_rateLo = 0; + u32 adc_frequency = 0; #ifndef DRXJ_VSB_ONLY - int bandwidthTemp = 0; + int bandwidth_temp = 0; int bandwidth = 0; #endif @@ -13308,10 +13308,10 @@ CtrlGetChannel(pDRXDemodInstance_t demod, pDRXChannel_t channel) return DRX_STS_INVALID_ARG; } - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; - standard = extAttr->standard; - commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; + standard = ext_attr->standard; + common_attr = (pdrx_common_attr_t) demod->my_common_attr; /* initialize channel fields */ channel->mirror = DRX_MIRROR_UNKNOWN; @@ -13330,22 +13330,22 @@ CtrlGetChannel(pDRXDemodInstance_t demod, pDRXChannel_t channel) /* channel->interleaver = DRX_INTERLEAVER_UNKNOWN;*/ channel->ldpc = DRX_LDPC_UNKNOWN; - if (demod->myTuner != NULL) { - s32 tunerFreqOffset = 0; - bool tunerMirror = commonAttr->mirrorFreqSpect ? false : true; + if (demod->my_tuner != NULL) { + s32 tuner_freq_offset = 0; + bool tuner_mirror = common_attr->mirror_freq_spect ? false : true; /* Get frequency from tuner */ - CHK_ERROR(DRXBSP_TUNER_GetFrequency(demod->myTuner, + CHK_ERROR(drxbsp_tuner_get_frequency(demod->my_tuner, 0, &(channel->frequency), - &intermediateFreq)); - tunerFreqOffset = channel->frequency - extAttr->frequency; - if (tunerMirror == true) { + &intermediate_freq)); + tuner_freq_offset = channel->frequency - ext_attr->frequency; + if (tuner_mirror == true) { /* positive image */ - channel->frequency += tunerFreqOffset; + channel->frequency += tuner_freq_offset; } else { /* negative image */ - channel->frequency -= tunerFreqOffset; + channel->frequency -= tuner_freq_offset; } /* Handle sound carrier offset in RF domain */ @@ -13353,24 +13353,24 @@ CtrlGetChannel(pDRXDemodInstance_t demod, pDRXChannel_t channel) channel->frequency -= DRXJ_FM_CARRIER_FREQ_OFFSET; } } else { - intermediateFreq = commonAttr->intermediateFreq; + intermediate_freq = common_attr->intermediate_freq; } /* check lock status */ - CHK_ERROR(CtrlLockStatus(demod, &lockStatus)); - if ((lockStatus == DRX_LOCKED) || (lockStatus == DRXJ_DEMOD_LOCK)) { - ARR32(devAddr, IQM_RC_RATE_LO__A, &iqmRcRateLo); - adcFrequency = (commonAttr->sysClockFreq * 1000) / 3; + CHK_ERROR(ctrl_lock_status(demod, &lock_status)); + if ((lock_status == DRX_LOCKED) || (lock_status == DRXJ_DEMOD_LOCK)) { + ARR32(dev_addr, IQM_RC_RATE_LO__A, &iqm_rc_rateLo); + adc_frequency = (common_attr->sys_clock_freq * 1000) / 3; channel->symbolrate = - Frac28(adcFrequency, (iqmRcRateLo + (1 << 23))) >> 7; + frac28(adc_frequency, (iqm_rc_rateLo + (1 << 23))) >> 7; switch (standard) { case DRX_STANDARD_8VSB: channel->bandwidth = DRX_BANDWIDTH_6MHZ; /* get the channel frequency */ - CHK_ERROR(GetCTLFreqOffset(demod, &CTLFreqOffset)); - channel->frequency -= CTLFreqOffset; + CHK_ERROR(get_ctl_freq_offset(demod, &ctl_freq_offset)); + channel->frequency -= ctl_freq_offset; /* get the channel constellation */ channel->constellation = DRX_CONSTELLATION_AUTO; break; @@ -13380,26 +13380,26 @@ CtrlGetChannel(pDRXDemodInstance_t demod, pDRXChannel_t channel) case DRX_STANDARD_ITU_C: { /* get the channel frequency */ - CHK_ERROR(GetCTLFreqOffset - (demod, &CTLFreqOffset)); - channel->frequency -= CTLFreqOffset; + CHK_ERROR(get_ctl_freq_offset + (demod, &ctl_freq_offset)); + channel->frequency -= ctl_freq_offset; if (standard == DRX_STANDARD_ITU_B) { channel->bandwidth = DRX_BANDWIDTH_6MHZ; } else { /* annex A & C */ - u32 rollOff = 113; /* default annex C */ + u32 roll_off = 113; /* default annex C */ if (standard == DRX_STANDARD_ITU_A) { - rollOff = 115; + roll_off = 115; } - bandwidthTemp = - channel->symbolrate * rollOff; - bandwidth = bandwidthTemp / 100; + bandwidth_temp = + channel->symbolrate * roll_off; + bandwidth = bandwidth_temp / 100; - if ((bandwidthTemp % 100) >= 50) { + if ((bandwidth_temp % 100) >= 50) { bandwidth++; } @@ -13417,30 +13417,30 @@ CtrlGetChannel(pDRXDemodInstance_t demod, pDRXChannel_t channel) } /* if (standard == DRX_STANDARD_ITU_B) */ { - DRXJSCUCmd_t cmdSCU = + drxjscu_cmd_t cmd_scu = { /* command */ 0, - /* parameterLen */ 0, - /* resultLen */ 0, + /* parameter_len */ 0, + /* result_len */ 0, /* parameter */ NULL, /* result */ NULL }; - u16 cmdResult[3] = { 0, 0, 0 }; + u16 cmd_result[3] = { 0, 0, 0 }; - cmdSCU.command = + cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_GET_PARAM; - cmdSCU.parameterLen = 0; - cmdSCU.resultLen = 3; - cmdSCU.parameter = NULL; - cmdSCU.result = cmdResult; - CHK_ERROR(SCUCommand(devAddr, &cmdSCU)); + cmd_scu.parameter_len = 0; + cmd_scu.result_len = 3; + cmd_scu.parameter = NULL; + cmd_scu.result = cmd_result; + CHK_ERROR(scu_command(dev_addr, &cmd_scu)); channel->interleavemode = - (enum drx_interleave_mode) (cmdSCU. + (enum drx_interleave_mode) (cmd_scu. result[2]); } - switch (extAttr->constellation) { + switch (ext_attr->constellation) { case DRX_CONSTELLATION_QAM256: channel->constellation = DRX_CONSTELLATION_QAM256; @@ -13477,7 +13477,7 @@ CtrlGetChannel(pDRXDemodInstance_t demod, pDRXChannel_t channel) case DRX_STANDARD_PAL_SECAM_L: case DRX_STANDARD_PAL_SECAM_LP: case DRX_STANDARD_FM: - CHK_ERROR(GetATVChannel(demod, channel, standard)); + CHK_ERROR(get_atv_channel(demod, channel, standard)); break; #endif case DRX_STANDARD_UNKNOWN: /* fall trough */ @@ -13485,11 +13485,11 @@ CtrlGetChannel(pDRXDemodInstance_t demod, pDRXChannel_t channel) return (DRX_STS_ERROR); } /* switch ( standard ) */ - if (lockStatus == DRX_LOCKED) { - channel->mirror = extAttr->mirror; + if (lock_status == DRX_LOCKED) { + channel->mirror = ext_attr->mirror; } } - /* if ( lockStatus == DRX_LOCKED ) */ + /* if ( lock_status == DRX_LOCKED ) */ return (DRX_STS_OK); rw_error: return (DRX_STS_ERROR); @@ -13500,22 +13500,22 @@ rw_error: ===========================================================================*/ static u16 -mer2indicator(u16 mer, u16 minMer, u16 thresholdMer, u16 maxMer) +mer2indicator(u16 mer, u16 min_mer, u16 threshold_mer, u16 max_mer) { u16 indicator = 0; - if (mer < minMer) { + if (mer < min_mer) { indicator = 0; - } else if (mer < thresholdMer) { - if ((thresholdMer - minMer) != 0) { + } else if (mer < threshold_mer) { + if ((threshold_mer - min_mer) != 0) { indicator = - 25 * (mer - minMer) / (thresholdMer - minMer); + 25 * (mer - min_mer) / (threshold_mer - min_mer); } - } else if (mer < maxMer) { - if ((maxMer - thresholdMer) != 0) { + } else if (mer < max_mer) { + if ((max_mer - threshold_mer) != 0) { indicator = - 25 + 75 * (mer - thresholdMer) / (maxMer - - thresholdMer); + 25 + 75 * (mer - threshold_mer) / (max_mer - + threshold_mer); } else { indicator = 25; } @@ -13527,105 +13527,105 @@ mer2indicator(u16 mer, u16 minMer, u16 thresholdMer, u16 maxMer) } /** -* \fn int CtrlSigQuality() +* \fn int ctrl_sig_quality() * \brief Retreive signal quality form device. * \param devmod Pointer to demodulator instance. -* \param sigQuality Pointer to signal quality data. +* \param sig_quality Pointer to signal quality data. * \return int. -* \retval DRX_STS_OK sigQuality contains valid data. -* \retval DRX_STS_INVALID_ARG sigQuality is NULL. -* \retval DRX_STS_ERROR Erroneous data, sigQuality contains invalid data. +* \retval DRX_STS_OK sig_quality contains valid data. +* \retval DRX_STS_INVALID_ARG sig_quality is NULL. +* \retval DRX_STS_ERROR Erroneous data, sig_quality contains invalid data. */ static int -CtrlSigQuality(pDRXDemodInstance_t demod, pDRXSigQuality_t sigQuality) +ctrl_sig_quality(pdrx_demod_instance_t demod, pdrx_sig_quality_t sig_quality) { - struct i2c_device_addr *devAddr = NULL; - pDRXJData_t extAttr = NULL; + struct i2c_device_addr *dev_addr = NULL; + pdrxj_data_t ext_attr = NULL; enum drx_standard standard = DRX_STANDARD_UNKNOWN; - DRXLockStatus_t lockStatus = DRX_NOT_LOCKED; - u16 minMer = 0; - u16 maxMer = 0; - u16 thresholdMer = 0; + drx_lock_status_t lock_status = DRX_NOT_LOCKED; + u16 min_mer = 0; + u16 max_mer = 0; + u16 threshold_mer = 0; /* Check arguments */ - if ((sigQuality == NULL) || (demod == NULL)) { + if ((sig_quality == NULL) || (demod == NULL)) { return (DRX_STS_INVALID_ARG); } - extAttr = (pDRXJData_t) demod->myExtAttr; - standard = extAttr->standard; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; + standard = ext_attr->standard; /* get basic information */ - devAddr = demod->myI2CDevAddr; - CHK_ERROR(CtrlLockStatus(demod, &lockStatus)); + dev_addr = demod->my_i2c_dev_addr; + CHK_ERROR(ctrl_lock_status(demod, &lock_status)); switch (standard) { case DRX_STANDARD_8VSB: #ifdef DRXJ_SIGNAL_ACCUM_ERR - CHK_ERROR(GetAccPktErr(demod, &sigQuality->packetError)); + CHK_ERROR(get_acc_pkt_err(demod, &sig_quality->packet_error)); #else - CHK_ERROR(GetVSBPostRSPckErr - (devAddr, &sigQuality->packetError)); + CHK_ERROR(get_vsb_post_rs_pck_err + (dev_addr, &sig_quality->packet_error)); #endif - if (lockStatus != DRXJ_DEMOD_LOCK && lockStatus != DRX_LOCKED) { - sigQuality->postViterbiBER = 500000; - sigQuality->MER = 20; - sigQuality->preViterbiBER = 0; + if (lock_status != DRXJ_DEMOD_LOCK && lock_status != DRX_LOCKED) { + sig_quality->post_viterbi_ber = 500000; + sig_quality->MER = 20; + sig_quality->pre_viterbi_ber = 0; } else { /* PostViterbi is compute in steps of 10^(-6) */ - CHK_ERROR(GetVSBpreViterbiBer - (devAddr, &sigQuality->preViterbiBER)); - CHK_ERROR(GetVSBpostViterbiBer - (devAddr, &sigQuality->postViterbiBER)); - CHK_ERROR(GetVSBMER(devAddr, &sigQuality->MER)); - } - minMer = 20; - maxMer = 360; - thresholdMer = 145; - sigQuality->postReedSolomonBER = 0; - sigQuality->scaleFactorBER = 1000000; - sigQuality->indicator = - mer2indicator(sigQuality->MER, minMer, thresholdMer, - maxMer); + CHK_ERROR(get_vs_bpre_viterbi_ber + (dev_addr, &sig_quality->pre_viterbi_ber)); + CHK_ERROR(get_vs_bpost_viterbi_ber + (dev_addr, &sig_quality->post_viterbi_ber)); + CHK_ERROR(get_vsbmer(dev_addr, &sig_quality->MER)); + } + min_mer = 20; + max_mer = 360; + threshold_mer = 145; + sig_quality->post_reed_solomon_ber = 0; + sig_quality->scale_factor_ber = 1000000; + sig_quality->indicator = + mer2indicator(sig_quality->MER, min_mer, threshold_mer, + max_mer); break; #ifndef DRXJ_VSB_ONLY case DRX_STANDARD_ITU_A: case DRX_STANDARD_ITU_B: case DRX_STANDARD_ITU_C: - CHK_ERROR(CtrlGetQAMSigQuality(demod, sigQuality)); - if (lockStatus != DRXJ_DEMOD_LOCK && lockStatus != DRX_LOCKED) { - switch (extAttr->constellation) { + CHK_ERROR(ctrl_get_qam_sig_quality(demod, sig_quality)); + if (lock_status != DRXJ_DEMOD_LOCK && lock_status != DRX_LOCKED) { + switch (ext_attr->constellation) { case DRX_CONSTELLATION_QAM256: - sigQuality->MER = 210; + sig_quality->MER = 210; break; case DRX_CONSTELLATION_QAM128: - sigQuality->MER = 180; + sig_quality->MER = 180; break; case DRX_CONSTELLATION_QAM64: - sigQuality->MER = 150; + sig_quality->MER = 150; break; case DRX_CONSTELLATION_QAM32: - sigQuality->MER = 120; + sig_quality->MER = 120; break; case DRX_CONSTELLATION_QAM16: - sigQuality->MER = 90; + sig_quality->MER = 90; break; default: - sigQuality->MER = 0; + sig_quality->MER = 0; return (DRX_STS_ERROR); } } - switch (extAttr->constellation) { + switch (ext_attr->constellation) { case DRX_CONSTELLATION_QAM256: - minMer = 210; - thresholdMer = 270; - maxMer = 380; + min_mer = 210; + threshold_mer = 270; + max_mer = 380; break; case DRX_CONSTELLATION_QAM64: - minMer = 150; - thresholdMer = 210; - maxMer = 380; + min_mer = 150; + threshold_mer = 210; + max_mer = 380; break; case DRX_CONSTELLATION_QAM128: case DRX_CONSTELLATION_QAM32: @@ -13634,9 +13634,9 @@ CtrlSigQuality(pDRXDemodInstance_t demod, pDRXSigQuality_t sigQuality) default: return (DRX_STS_ERROR); } - sigQuality->indicator = - mer2indicator(sigQuality->MER, minMer, thresholdMer, - maxMer); + sig_quality->indicator = + mer2indicator(sig_quality->MER, min_mer, threshold_mer, + max_mer); break; #endif #ifndef DRXJ_DIGITAL_ONLY @@ -13646,10 +13646,10 @@ CtrlSigQuality(pDRXDemodInstance_t demod, pDRXSigQuality_t sigQuality) case DRX_STANDARD_PAL_SECAM_L: case DRX_STANDARD_PAL_SECAM_LP: case DRX_STANDARD_NTSC: - CHK_ERROR(AtvSigQuality(demod, sigQuality)); + CHK_ERROR(atv_sig_quality(demod, sig_quality)); break; case DRX_STANDARD_FM: - CHK_ERROR(FmSigQuality(demod, sigQuality)); + CHK_ERROR(fm_sig_quality(demod, sig_quality)); break; #endif default: @@ -13664,51 +13664,51 @@ rw_error: /*============================================================================*/ /** -* \fn int CtrlLockStatus() +* \fn int ctrl_lock_status() * \brief Retreive lock status . -* \param devAddr Pointer to demodulator device address. -* \param lockStat Pointer to lock status structure. +* \param dev_addr Pointer to demodulator device address. +* \param lock_stat Pointer to lock status structure. * \return int. * */ static int -CtrlLockStatus(pDRXDemodInstance_t demod, pDRXLockStatus_t lockStat) +ctrl_lock_status(pdrx_demod_instance_t demod, pdrx_lock_status_t lock_stat) { enum drx_standard standard = DRX_STANDARD_UNKNOWN; - pDRXJData_t extAttr = NULL; - struct i2c_device_addr *devAddr = NULL; - DRXJSCUCmd_t cmdSCU = { /* command */ 0, - /* parameterLen */ 0, - /* resultLen */ 0, + pdrxj_data_t ext_attr = NULL; + struct i2c_device_addr *dev_addr = NULL; + drxjscu_cmd_t cmd_scu = { /* command */ 0, + /* parameter_len */ 0, + /* result_len */ 0, /* *parameter */ NULL, /* *result */ NULL }; - u16 cmdResult[2] = { 0, 0 }; - u16 demodLock = SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_DEMOD_LOCKED; + u16 cmd_result[2] = { 0, 0 }; + u16 demod_lock = SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_DEMOD_LOCKED; /* check arguments */ - if ((demod == NULL) || (lockStat == NULL)) { + if ((demod == NULL) || (lock_stat == NULL)) { return (DRX_STS_INVALID_ARG); } - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; - standard = extAttr->standard; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; + standard = ext_attr->standard; - *lockStat = DRX_NOT_LOCKED; + *lock_stat = DRX_NOT_LOCKED; /* define the SCU command code */ switch (standard) { case DRX_STANDARD_8VSB: - cmdSCU.command = SCU_RAM_COMMAND_STANDARD_VSB | + cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB | SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK; - demodLock |= 0x6; + demod_lock |= 0x6; break; #ifndef DRXJ_VSB_ONLY case DRX_STANDARD_ITU_A: case DRX_STANDARD_ITU_B: case DRX_STANDARD_ITU_C: - cmdSCU.command = SCU_RAM_COMMAND_STANDARD_QAM | + cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK; break; #endif @@ -13719,11 +13719,11 @@ CtrlLockStatus(pDRXDemodInstance_t demod, pDRXLockStatus_t lockStat) case DRX_STANDARD_PAL_SECAM_I: case DRX_STANDARD_PAL_SECAM_L: case DRX_STANDARD_PAL_SECAM_LP: - cmdSCU.command = SCU_RAM_COMMAND_STANDARD_ATV | + cmd_scu.command = SCU_RAM_COMMAND_STANDARD_ATV | SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK; break; case DRX_STANDARD_FM: - return FmLockStatus(demod, lockStat); + return fm_lock_status(demod, lock_stat); #endif case DRX_STANDARD_UNKNOWN: /* fallthrough */ default: @@ -13731,26 +13731,26 @@ CtrlLockStatus(pDRXDemodInstance_t demod, pDRXLockStatus_t lockStat) } /* define the SCU command paramters and execute the command */ - cmdSCU.parameterLen = 0; - cmdSCU.resultLen = 2; - cmdSCU.parameter = NULL; - cmdSCU.result = cmdResult; - CHK_ERROR(SCUCommand(devAddr, &cmdSCU)); + cmd_scu.parameter_len = 0; + cmd_scu.result_len = 2; + cmd_scu.parameter = NULL; + cmd_scu.result = cmd_result; + CHK_ERROR(scu_command(dev_addr, &cmd_scu)); /* set the lock status */ - if (cmdSCU.result[1] < demodLock) { + if (cmd_scu.result[1] < demod_lock) { /* 0x0000 NOT LOCKED */ - *lockStat = DRX_NOT_LOCKED; - } else if (cmdSCU.result[1] < SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_LOCKED) { - *lockStat = DRXJ_DEMOD_LOCK; - } else if (cmdSCU.result[1] < + *lock_stat = DRX_NOT_LOCKED; + } else if (cmd_scu.result[1] < SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_LOCKED) { + *lock_stat = DRXJ_DEMOD_LOCK; + } else if (cmd_scu.result[1] < SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NEVER_LOCK) { /* 0x8000 DEMOD + FEC LOCKED (system lock) */ - *lockStat = DRX_LOCKED; + *lock_stat = DRX_LOCKED; } else { /* 0xC000 NEVER LOCKED */ /* (system will never be able to lock to the signal) */ - *lockStat = DRX_NEVER_LOCK; + *lock_stat = DRX_NEVER_LOCK; } return (DRX_STS_OK); @@ -13761,37 +13761,37 @@ rw_error: /*============================================================================*/ /** -* \fn int CtrlConstel() +* \fn int ctrl_constel() * \brief Retreive a constellation point via I2C. * \param demod Pointer to demodulator instance. -* \param complexNr Pointer to the structure in which to store the +* \param complex_nr Pointer to the structure in which to store the constellation point. * \return int. */ static int -CtrlConstel(pDRXDemodInstance_t demod, pDRXComplex_t complexNr) +ctrl_constel(pdrx_demod_instance_t demod, pdrx_complex_t complex_nr) { enum drx_standard standard = DRX_STANDARD_UNKNOWN; /**< active standard */ /* check arguments */ - if ((demod == NULL) || (complexNr == NULL)) { + if ((demod == NULL) || (complex_nr == NULL)) { return (DRX_STS_INVALID_ARG); } /* read device info */ - standard = ((pDRXJData_t) demod->myExtAttr)->standard; + standard = ((pdrxj_data_t) demod->my_ext_attr)->standard; /* Read constellation point */ switch (standard) { case DRX_STANDARD_8VSB: - CHK_ERROR(CtrlGetVSBConstel(demod, complexNr)); + CHK_ERROR(ctrl_get_vsb_constel(demod, complex_nr)); break; #ifndef DRXJ_VSB_ONLY case DRX_STANDARD_ITU_A: /* fallthrough */ case DRX_STANDARD_ITU_B: /* fallthrough */ case DRX_STANDARD_ITU_C: - CHK_ERROR(CtrlGetQAMConstel(demod, complexNr)); + CHK_ERROR(ctrl_get_qam_constel(demod, complex_nr)); break; #endif case DRX_STANDARD_UNKNOWN: @@ -13807,7 +13807,7 @@ rw_error: /*============================================================================*/ /** -* \fn int CtrlSetStandard() +* \fn int ctrl_set_standard() * \brief Set modulation standard to be used. * \param standard Modulation standard. * \return int. @@ -13817,32 +13817,32 @@ rw_error: * */ static int -CtrlSetStandard(pDRXDemodInstance_t demod, enum drx_standard *standard) +ctrl_set_standard(pdrx_demod_instance_t demod, enum drx_standard *standard) { - pDRXJData_t extAttr = NULL; - enum drx_standard prevStandard; + pdrxj_data_t ext_attr = NULL; + enum drx_standard prev_standard; /* check arguments */ if ((standard == NULL) || (demod == NULL)) { return (DRX_STS_INVALID_ARG); } - extAttr = (pDRXJData_t) demod->myExtAttr; - prevStandard = extAttr->standard; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; + prev_standard = ext_attr->standard; /* Stop and power down previous standard */ - switch (prevStandard) { + switch (prev_standard) { #ifndef DRXJ_VSB_ONLY case DRX_STANDARD_ITU_A: /* fallthrough */ case DRX_STANDARD_ITU_B: /* fallthrough */ case DRX_STANDARD_ITU_C: - CHK_ERROR(PowerDownQAM(demod, false)); + CHK_ERROR(power_down_qam(demod, false)); break; #endif case DRX_STANDARD_8VSB: - CHK_ERROR(PowerDownVSB(demod, false)); + CHK_ERROR(power_down_vsb(demod, false)); break; #ifndef DRXJ_DIGITAL_ONLY case DRX_STANDARD_NTSC: /* fallthrough */ @@ -13852,7 +13852,7 @@ CtrlSetStandard(pDRXDemodInstance_t demod, enum drx_standard *standard) case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */ case DRX_STANDARD_PAL_SECAM_LP: - CHK_ERROR(PowerDownATV(demod, prevStandard, false)); + CHK_ERROR(power_down_atv(demod, prev_standard, false)); break; #endif case DRX_STANDARD_UNKNOWN: @@ -13867,7 +13867,7 @@ CtrlSetStandard(pDRXDemodInstance_t demod, enum drx_standard *standard) Initialize channel independent registers Power up new standard */ - extAttr->standard = *standard; + ext_attr->standard = *standard; switch (*standard) { #ifndef DRXJ_VSB_ONLY @@ -13878,7 +13878,7 @@ CtrlSetStandard(pDRXDemodInstance_t demod, enum drx_standard *standard) break; #endif case DRX_STANDARD_8VSB: - CHK_ERROR(SetVSBLeakNGain(demod)); + CHK_ERROR(set_vsb_leak_n_gain(demod)); break; #ifndef DRXJ_DIGITAL_ONLY case DRX_STANDARD_NTSC: /* fallthrough */ @@ -13888,12 +13888,12 @@ CtrlSetStandard(pDRXDemodInstance_t demod, enum drx_standard *standard) case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */ case DRX_STANDARD_PAL_SECAM_LP: - CHK_ERROR(SetATVStandard(demod, standard)); - CHK_ERROR(PowerUpATV(demod, *standard)); + CHK_ERROR(set_atv_standard(demod, standard)); + CHK_ERROR(power_up_atv(demod, *standard)); break; #endif default: - extAttr->standard = DRX_STANDARD_UNKNOWN; + ext_attr->standard = DRX_STANDARD_UNKNOWN; return (DRX_STS_INVALID_ARG); break; } @@ -13901,14 +13901,14 @@ CtrlSetStandard(pDRXDemodInstance_t demod, enum drx_standard *standard) return (DRX_STS_OK); rw_error: /* Don't know what the standard is now ... try again */ - extAttr->standard = DRX_STANDARD_UNKNOWN; + ext_attr->standard = DRX_STANDARD_UNKNOWN; return (DRX_STS_ERROR); } /*============================================================================*/ /** -* \fn int CtrlGetStandard() +* \fn int ctrl_get_standard() * \brief Get modulation standard currently used to demodulate. * \param standard Modulation standard. * \return int. @@ -13917,16 +13917,16 @@ rw_error: * */ static int -CtrlGetStandard(pDRXDemodInstance_t demod, enum drx_standard *standard) +ctrl_get_standard(pdrx_demod_instance_t demod, enum drx_standard *standard) { - pDRXJData_t extAttr = NULL; - extAttr = (pDRXJData_t) demod->myExtAttr; + pdrxj_data_t ext_attr = NULL; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* check arguments */ if (standard == NULL) { return (DRX_STS_INVALID_ARG); } - (*standard) = extAttr->standard; + (*standard) = ext_attr->standard; DUMMY_READ(); return (DRX_STS_OK); @@ -13937,27 +13937,27 @@ rw_error: /*============================================================================*/ /** -* \fn int CtrlGetCfgSymbolClockOffset() +* \fn int ctrl_get_cfg_symbol_clock_offset() * \brief Get frequency offsets of STR. * \param pointer to s32. * \return int. * */ static int -CtrlGetCfgSymbolClockOffset(pDRXDemodInstance_t demod, s32 *rateOffset) +ctrl_get_cfg_symbol_clock_offset(pdrx_demod_instance_t demod, s32 *rate_offset) { enum drx_standard standard = DRX_STANDARD_UNKNOWN; - struct i2c_device_addr *devAddr = NULL; - pDRXJData_t extAttr = NULL; + struct i2c_device_addr *dev_addr = NULL; + pdrxj_data_t ext_attr = NULL; /* check arguments */ - if (rateOffset == NULL) { + if (rate_offset == NULL) { return (DRX_STS_INVALID_ARG); } - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; - standard = extAttr->standard; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; + standard = ext_attr->standard; switch (standard) { case DRX_STANDARD_8VSB: /* fallthrough */ @@ -13966,7 +13966,7 @@ CtrlGetCfgSymbolClockOffset(pDRXDemodInstance_t demod, s32 *rateOffset) case DRX_STANDARD_ITU_B: /* fallthrough */ case DRX_STANDARD_ITU_C: #endif - CHK_ERROR(GetSTRFreqOffset(demod, rateOffset)); + CHK_ERROR(get_str_freq_offset(demod, rate_offset)); break; case DRX_STANDARD_NTSC: case DRX_STANDARD_UNKNOWN: @@ -13982,7 +13982,7 @@ rw_error: /*============================================================================*/ /** -* \fn int CtrlPowerMode() +* \fn int ctrl_power_mode() * \brief Set the power mode of the device to the specified power mode * \param demod Pointer to demodulator instance. * \param mode Pointer to new power mode. @@ -13994,16 +13994,16 @@ rw_error: * */ static int -CtrlPowerMode(pDRXDemodInstance_t demod, pDRXPowerMode_t mode) +ctrl_power_mode(pdrx_demod_instance_t demod, pdrx_power_mode_t mode) { - pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) NULL; - pDRXJData_t extAttr = (pDRXJData_t) NULL; - struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL; - u16 sioCcPwdMode = 0; + pdrx_common_attr_t common_attr = (pdrx_common_attr_t) NULL; + pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) NULL; + u16 sio_cc_pwd_mode = 0; - commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; - extAttr = (pDRXJData_t) demod->myExtAttr; - devAddr = demod->myI2CDevAddr; + common_attr = (pdrx_common_attr_t) demod->my_common_attr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; + dev_addr = demod->my_i2c_dev_addr; /* Check arguments */ if (mode == NULL) { @@ -14011,23 +14011,23 @@ CtrlPowerMode(pDRXDemodInstance_t demod, pDRXPowerMode_t mode) } /* If already in requested power mode, do nothing */ - if (commonAttr->currentPowerMode == *mode) { + if (common_attr->current_power_mode == *mode) { return (DRX_STS_OK); } switch (*mode) { case DRX_POWER_UP: case DRXJ_POWER_DOWN_MAIN_PATH: - sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_NONE; + sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_NONE; break; case DRXJ_POWER_DOWN_CORE: - sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_CLOCK; + sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_CLOCK; break; case DRXJ_POWER_DOWN_PLL: - sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_PLL; + sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_PLL; break; case DRX_POWER_DOWN: - sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OSC; + sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_OSC; break; default: /* Unknow sleep mode */ @@ -14036,8 +14036,8 @@ CtrlPowerMode(pDRXDemodInstance_t demod, pDRXPowerMode_t mode) } /* Check if device needs to be powered up */ - if ((commonAttr->currentPowerMode != DRX_POWER_UP)) { - CHK_ERROR(PowerUpDevice(demod)); + if ((common_attr->current_power_mode != DRX_POWER_UP)) { + CHK_ERROR(power_up_device(demod)); } if ((*mode == DRX_POWER_UP)) { @@ -14054,14 +14054,14 @@ CtrlPowerMode(pDRXDemodInstance_t demod, pDRXPowerMode_t mode) Stop and power down previous standard */ - switch (extAttr->standard) { + switch (ext_attr->standard) { case DRX_STANDARD_ITU_A: case DRX_STANDARD_ITU_B: case DRX_STANDARD_ITU_C: - CHK_ERROR(PowerDownQAM(demod, true)); + CHK_ERROR(power_down_qam(demod, true)); break; case DRX_STANDARD_8VSB: - CHK_ERROR(PowerDownVSB(demod, true)); + CHK_ERROR(power_down_vsb(demod, true)); break; case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ @@ -14070,7 +14070,7 @@ CtrlPowerMode(pDRXDemodInstance_t demod, pDRXPowerMode_t mode) case DRX_STANDARD_PAL_SECAM_LP: /* fallthrough */ case DRX_STANDARD_NTSC: /* fallthrough */ case DRX_STANDARD_FM: - CHK_ERROR(PowerDownATV(demod, extAttr->standard, true)); + CHK_ERROR(power_down_atv(demod, ext_attr->standard, true)); break; case DRX_STANDARD_UNKNOWN: /* Do nothing */ @@ -14081,18 +14081,18 @@ CtrlPowerMode(pDRXDemodInstance_t demod, pDRXPowerMode_t mode) } if (*mode != DRXJ_POWER_DOWN_MAIN_PATH) { - WR16(devAddr, SIO_CC_PWD_MODE__A, sioCcPwdMode); - WR16(devAddr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); + WR16(dev_addr, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode); + WR16(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); /* Initialize HI, wakeup key especially before put IC to sleep */ - CHK_ERROR(InitHI(demod)); + CHK_ERROR(init_hi(demod)); - extAttr->HICfgCtrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; - CHK_ERROR(HICfgCommand(demod)); + ext_attr->hi_cfg_ctrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; + CHK_ERROR(hi_cfg_command(demod)); } } - commonAttr->currentPowerMode = *mode; + common_attr->current_power_mode = *mode; return (DRX_STS_OK); rw_error: @@ -14102,10 +14102,10 @@ rw_error: /*============================================================================*/ /** -* \fn int CtrlVersion() +* \fn int ctrl_version() * \brief Report version of microcode and if possible version of device * \param demod Pointer to demodulator instance. -* \param versionList Pointer to pointer of linked list of versions. +* \param version_list Pointer to pointer of linked list of versions. * \return int. * * Using static structures so no allocation of memory is needed. @@ -14122,13 +14122,13 @@ rw_error: * */ static int -CtrlVersion(pDRXDemodInstance_t demod, pDRXVersionList_t *versionList) +ctrl_version(pdrx_demod_instance_t demod, p_drx_version_list_t *version_list) { - pDRXJData_t extAttr = (pDRXJData_t) (NULL); - struct i2c_device_addr *devAddr = (struct i2c_device_addr *) (NULL); - pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); - u16 ucodeMajorMinor = 0; /* BCD Ma:Ma:Ma:Mi */ - u16 ucodePatch = 0; /* BCD Pa:Pa:Pa:Pa */ + pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) (NULL); + pdrx_common_attr_t common_attr = (pdrx_common_attr_t) (NULL); + u16 ucode_major_minor = 0; /* BCD Ma:Ma:Ma:Mi */ + u16 ucode_patch = 0; /* BCD Pa:Pa:Pa:Pa */ u16 major = 0; u16 minor = 0; u16 patch = 0; @@ -14139,121 +14139,121 @@ CtrlVersion(pDRXDemodInstance_t demod, pDRXVersionList_t *versionList) u16 bid = 0; u16 key = 0; - static char ucodeName[] = "Microcode"; - static char deviceName[] = "Device"; + static char ucode_name[] = "Microcode"; + static char device_name[] = "Device"; - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; - commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; + common_attr = (pdrx_common_attr_t) demod->my_common_attr; /* Microcode version *************************************** */ - extAttr->vVersion[0].moduleType = DRX_MODULE_MICROCODE; - extAttr->vVersion[0].moduleName = ucodeName; - extAttr->vVersion[0].vString = extAttr->vText[0]; + ext_attr->v_version[0].module_type = DRX_MODULE_MICROCODE; + ext_attr->v_version[0].module_name = ucode_name; + ext_attr->v_version[0].v_string = ext_attr->v_text[0]; - if (commonAttr->isOpened == true) { - SARR16(devAddr, SCU_RAM_VERSION_HI__A, &ucodeMajorMinor); - SARR16(devAddr, SCU_RAM_VERSION_LO__A, &ucodePatch); + if (common_attr->is_opened == true) { + SARR16(dev_addr, SCU_RAM_VERSION_HI__A, &ucode_major_minor); + SARR16(dev_addr, SCU_RAM_VERSION_LO__A, &ucode_patch); /* Translate BCD to numbers and string */ /* TODO: The most significant Ma and Pa will be ignored, check with spec */ - minor = (ucodeMajorMinor & 0xF); - ucodeMajorMinor >>= 4; - major = (ucodeMajorMinor & 0xF); - ucodeMajorMinor >>= 4; - major += (10 * (ucodeMajorMinor & 0xF)); - patch = (ucodePatch & 0xF); - ucodePatch >>= 4; - patch += (10 * (ucodePatch & 0xF)); - ucodePatch >>= 4; - patch += (100 * (ucodePatch & 0xF)); + minor = (ucode_major_minor & 0xF); + ucode_major_minor >>= 4; + major = (ucode_major_minor & 0xF); + ucode_major_minor >>= 4; + major += (10 * (ucode_major_minor & 0xF)); + patch = (ucode_patch & 0xF); + ucode_patch >>= 4; + patch += (10 * (ucode_patch & 0xF)); + ucode_patch >>= 4; + patch += (100 * (ucode_patch & 0xF)); } else { /* No microcode uploaded, No Rom existed, set version to 0.0.0 */ patch = 0; minor = 0; major = 0; } - extAttr->vVersion[0].vMajor = major; - extAttr->vVersion[0].vMinor = minor; - extAttr->vVersion[0].vPatch = patch; + ext_attr->v_version[0].v_major = major; + ext_attr->v_version[0].v_minor = minor; + ext_attr->v_version[0].v_patch = patch; if (major / 10 != 0) { - extAttr->vVersion[0].vString[idx++] = + ext_attr->v_version[0].v_string[idx++] = ((char)(major / 10)) + '0'; major %= 10; } - extAttr->vVersion[0].vString[idx++] = ((char)major) + '0'; - extAttr->vVersion[0].vString[idx++] = '.'; - extAttr->vVersion[0].vString[idx++] = ((char)minor) + '0'; - extAttr->vVersion[0].vString[idx++] = '.'; + ext_attr->v_version[0].v_string[idx++] = ((char)major) + '0'; + ext_attr->v_version[0].v_string[idx++] = '.'; + ext_attr->v_version[0].v_string[idx++] = ((char)minor) + '0'; + ext_attr->v_version[0].v_string[idx++] = '.'; if (patch / 100 != 0) { - extAttr->vVersion[0].vString[idx++] = + ext_attr->v_version[0].v_string[idx++] = ((char)(patch / 100)) + '0'; patch %= 100; } if (patch / 10 != 0) { - extAttr->vVersion[0].vString[idx++] = + ext_attr->v_version[0].v_string[idx++] = ((char)(patch / 10)) + '0'; patch %= 10; } - extAttr->vVersion[0].vString[idx++] = ((char)patch) + '0'; - extAttr->vVersion[0].vString[idx] = '\0'; + ext_attr->v_version[0].v_string[idx++] = ((char)patch) + '0'; + ext_attr->v_version[0].v_string[idx] = '\0'; - extAttr->vListElements[0].version = &(extAttr->vVersion[0]); - extAttr->vListElements[0].next = &(extAttr->vListElements[1]); + ext_attr->v_list_elements[0].version = &(ext_attr->v_version[0]); + ext_attr->v_list_elements[0].next = &(ext_attr->v_list_elements[1]); /* Device version *************************************** */ /* Check device id */ - RR16(devAddr, SIO_TOP_COMM_KEY__A, &key); - WR16(devAddr, SIO_TOP_COMM_KEY__A, 0xFABA); - RR32(devAddr, SIO_TOP_JTAGID_LO__A, &jtag); - RR16(devAddr, SIO_PDR_UIO_IN_HI__A, &bid); - WR16(devAddr, SIO_TOP_COMM_KEY__A, key); - - extAttr->vVersion[1].moduleType = DRX_MODULE_DEVICE; - extAttr->vVersion[1].moduleName = deviceName; - extAttr->vVersion[1].vString = extAttr->vText[1]; - extAttr->vVersion[1].vString[0] = 'D'; - extAttr->vVersion[1].vString[1] = 'R'; - extAttr->vVersion[1].vString[2] = 'X'; - extAttr->vVersion[1].vString[3] = '3'; - extAttr->vVersion[1].vString[4] = '9'; - extAttr->vVersion[1].vString[7] = 'J'; - extAttr->vVersion[1].vString[8] = ':'; - extAttr->vVersion[1].vString[11] = '\0'; + RR16(dev_addr, SIO_TOP_COMM_KEY__A, &key); + WR16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA); + RR32(dev_addr, SIO_TOP_JTAGID_LO__A, &jtag); + RR16(dev_addr, SIO_PDR_UIO_IN_HI__A, &bid); + WR16(dev_addr, SIO_TOP_COMM_KEY__A, key); + + ext_attr->v_version[1].module_type = DRX_MODULE_DEVICE; + ext_attr->v_version[1].module_name = device_name; + ext_attr->v_version[1].v_string = ext_attr->v_text[1]; + ext_attr->v_version[1].v_string[0] = 'D'; + ext_attr->v_version[1].v_string[1] = 'R'; + ext_attr->v_version[1].v_string[2] = 'X'; + ext_attr->v_version[1].v_string[3] = '3'; + ext_attr->v_version[1].v_string[4] = '9'; + ext_attr->v_version[1].v_string[7] = 'J'; + ext_attr->v_version[1].v_string[8] = ':'; + ext_attr->v_version[1].v_string[11] = '\0'; /* DRX39xxJ type Ax */ /* TODO semantics of mfx and spin are unclear */ subtype = (u16) ((jtag >> 12) & 0xFF); mfx = (u16) (jtag >> 29); - extAttr->vVersion[1].vMinor = 1; + ext_attr->v_version[1].v_minor = 1; if (mfx == 0x03) { - extAttr->vVersion[1].vPatch = mfx + 2; + ext_attr->v_version[1].v_patch = mfx + 2; } else { - extAttr->vVersion[1].vPatch = mfx + 1; + ext_attr->v_version[1].v_patch = mfx + 1; } - extAttr->vVersion[1].vString[6] = ((char)(subtype & 0xF)) + '0'; - extAttr->vVersion[1].vMajor = (subtype & 0x0F); + ext_attr->v_version[1].v_string[6] = ((char)(subtype & 0xF)) + '0'; + ext_attr->v_version[1].v_major = (subtype & 0x0F); subtype >>= 4; - extAttr->vVersion[1].vString[5] = ((char)(subtype & 0xF)) + '0'; - extAttr->vVersion[1].vMajor += 10 * subtype; - extAttr->vVersion[1].vString[9] = 'A'; + ext_attr->v_version[1].v_string[5] = ((char)(subtype & 0xF)) + '0'; + ext_attr->v_version[1].v_major += 10 * subtype; + ext_attr->v_version[1].v_string[9] = 'A'; if (mfx == 0x03) { - extAttr->vVersion[1].vString[10] = ((char)(mfx & 0xF)) + '2'; + ext_attr->v_version[1].v_string[10] = ((char)(mfx & 0xF)) + '2'; } else { - extAttr->vVersion[1].vString[10] = ((char)(mfx & 0xF)) + '1'; + ext_attr->v_version[1].v_string[10] = ((char)(mfx & 0xF)) + '1'; } - extAttr->vListElements[1].version = &(extAttr->vVersion[1]); - extAttr->vListElements[1].next = (pDRXVersionList_t) (NULL); + ext_attr->v_list_elements[1].version = &(ext_attr->v_version[1]); + ext_attr->v_list_elements[1].next = (p_drx_version_list_t) (NULL); - *versionList = &(extAttr->vListElements[0]); + *version_list = &(ext_attr->v_list_elements[0]); return (DRX_STS_OK); rw_error: - *versionList = (pDRXVersionList_t) (NULL); + *version_list = (p_drx_version_list_t) (NULL); return (DRX_STS_ERROR); } @@ -14261,7 +14261,7 @@ rw_error: /*============================================================================*/ /** -* \fn int CtrlProbeDevice() +* \fn int ctrl_probe_device() * \brief Probe device, check if it is present * \param demod Pointer to demodulator instance. * \return int. @@ -14272,37 +14272,37 @@ rw_error: * */ -static int CtrlProbeDevice(pDRXDemodInstance_t demod) +static int ctrl_probe_device(pdrx_demod_instance_t demod) { - DRXPowerMode_t orgPowerMode = DRX_POWER_UP; - int retStatus = DRX_STS_OK; - pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); + drx_power_mode_t org_power_mode = DRX_POWER_UP; + int ret_status = DRX_STS_OK; + pdrx_common_attr_t common_attr = (pdrx_common_attr_t) (NULL); - commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; + common_attr = (pdrx_common_attr_t) demod->my_common_attr; - if (commonAttr->isOpened == false - || commonAttr->currentPowerMode != DRX_POWER_UP) { - struct i2c_device_addr *devAddr = NULL; - DRXPowerMode_t powerMode = DRX_POWER_UP; + if (common_attr->is_opened == false + || common_attr->current_power_mode != DRX_POWER_UP) { + struct i2c_device_addr *dev_addr = NULL; + drx_power_mode_t power_mode = DRX_POWER_UP; u32 jtag = 0; - devAddr = demod->myI2CDevAddr; + dev_addr = demod->my_i2c_dev_addr; /* Remeber original power mode */ - orgPowerMode = commonAttr->currentPowerMode; + org_power_mode = common_attr->current_power_mode; - if (demod->myCommonAttr->isOpened == false) { - CHK_ERROR(PowerUpDevice(demod)); - commonAttr->currentPowerMode = DRX_POWER_UP; + if (demod->my_common_attr->is_opened == false) { + CHK_ERROR(power_up_device(demod)); + common_attr->current_power_mode = DRX_POWER_UP; } else { /* Wake-up device, feedback from device */ - CHK_ERROR(CtrlPowerMode(demod, &powerMode)); + CHK_ERROR(ctrl_power_mode(demod, &power_mode)); } /* Initialize HI, wakeup key especially */ - CHK_ERROR(InitHI(demod)); + CHK_ERROR(init_hi(demod)); /* Check device id */ - RR32(devAddr, SIO_TOP_JTAGID_LO__A, &jtag); + RR32(dev_addr, SIO_TOP_JTAGID_LO__A, &jtag); jtag = (jtag >> 12) & 0xFFFF; switch (jtag) { case 0x3931: /* fallthrough */ @@ -14318,23 +14318,23 @@ static int CtrlProbeDevice(pDRXDemodInstance_t demod) /* ok , do nothing */ break; default: - retStatus = DRX_STS_ERROR; + ret_status = DRX_STS_ERROR; break; } /* Device was not opened, return to orginal powermode, feedback from device */ - CHK_ERROR(CtrlPowerMode(demod, &orgPowerMode)); + CHK_ERROR(ctrl_power_mode(demod, &org_power_mode)); } else { /* dummy read to make this function fail in case device - suddenly disappears after a succesful DRX_Open */ + suddenly disappears after a succesful drx_open */ DUMMY_READ(); } - return (retStatus); + return (ret_status); rw_error: - commonAttr->currentPowerMode = orgPowerMode; + common_attr->current_power_mode = org_power_mode; return (DRX_STS_ERROR); } @@ -14342,14 +14342,14 @@ rw_error: /*============================================================================*/ /** -* \fn int IsMCBlockAudio() +* \fn int is_mc_block_audio() * \brief Check if MC block is Audio or not Audio. * \param addr Pointer to demodulator instance. * \param audioUpload true if MC block is Audio false if MC block not Audio * \return bool. */ -bool IsMCBlockAudio(u32 addr) +bool is_mc_block_audio(u32 addr) { if ((addr == AUD_XFP_PRAM_4K__A) || (addr == AUD_XDFP_PRAM_4K__A)) { return (true); @@ -14360,93 +14360,93 @@ bool IsMCBlockAudio(u32 addr) /*============================================================================*/ /** -* \fn int CtrlUCodeUpload() +* \fn int ctrl_u_codeUpload() * \brief Handle Audio or !Audio part of microcode upload. * \param demod Pointer to demodulator instance. -* \param mcInfo Pointer to information about microcode data. +* \param mc_info Pointer to information about microcode data. * \param action Either UCODE_UPLOAD or UCODE_VERIFY. -* \param uploadAudioMC true if Audio MC need to be uploaded. +* \param upload_audio_mc true if Audio MC need to be uploaded. false if !Audio MC need to be uploaded. * \return int. */ static int -CtrlUCodeUpload(pDRXDemodInstance_t demod, - pDRXUCodeInfo_t mcInfo, - DRXUCodeAction_t action, bool uploadAudioMC) +ctrl_u_codeUpload(pdrx_demod_instance_t demod, + p_drxu_code_info_t mc_info, + drxu_code_action_t action, bool upload_audio_mc) { u16 i = 0; - u16 mcNrOfBlks = 0; - u16 mcMagicWord = 0; - u8 *mcData = (u8 *) (NULL); - struct i2c_device_addr *devAddr = (struct i2c_device_addr *) (NULL); - pDRXJData_t extAttr = (pDRXJData_t) (NULL); + u16 mc_nr_of_blks = 0; + u16 mc_magic_word = 0; + u8 *mc_data = (u8 *) (NULL); + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) (NULL); + pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* Check arguments */ - if ((mcInfo == NULL) || - (mcInfo->mcData == NULL) || (mcInfo->mcSize == 0)) { + if ((mc_info == NULL) || + (mc_info->mc_data == NULL) || (mc_info->mc_size == 0)) { return DRX_STS_INVALID_ARG; } - mcData = mcInfo->mcData; + mc_data = mc_info->mc_data; /* Check data */ - mcMagicWord = UCodeRead16(mcData); - mcData += sizeof(u16); - mcNrOfBlks = UCodeRead16(mcData); - mcData += sizeof(u16); + mc_magic_word = u_code_read16(mc_data); + mc_data += sizeof(u16); + mc_nr_of_blks = u_code_read16(mc_data); + mc_data += sizeof(u16); - if ((mcMagicWord != DRXJ_UCODE_MAGIC_WORD) || (mcNrOfBlks == 0)) { + if ((mc_magic_word != DRXJ_UCODE_MAGIC_WORD) || (mc_nr_of_blks == 0)) { /* wrong endianess or wrong data ? */ return DRX_STS_INVALID_ARG; } /* Process microcode blocks */ - for (i = 0; i < mcNrOfBlks; i++) { - DRXUCodeBlockHdr_t blockHdr; - u16 mcBlockNrBytes = 0; + for (i = 0; i < mc_nr_of_blks; i++) { + drxu_code_block_hdr_t block_hdr; + u16 mc_block_nr_bytes = 0; /* Process block header */ - blockHdr.addr = UCodeRead32(mcData); - mcData += sizeof(u32); - blockHdr.size = UCodeRead16(mcData); - mcData += sizeof(u16); - blockHdr.flags = UCodeRead16(mcData); - mcData += sizeof(u16); - blockHdr.CRC = UCodeRead16(mcData); - mcData += sizeof(u16); + block_hdr.addr = u_code_read32(mc_data); + mc_data += sizeof(u32); + block_hdr.size = u_code_read16(mc_data); + mc_data += sizeof(u16); + block_hdr.flags = u_code_read16(mc_data); + mc_data += sizeof(u16); + block_hdr.CRC = u_code_read16(mc_data); + mc_data += sizeof(u16); /* Check block header on: - no data - data larger then 64Kb - if CRC enabled check CRC */ - if ((blockHdr.size == 0) || - (blockHdr.size > 0x7FFF) || - (((blockHdr.flags & DRXJ_UCODE_CRC_FLAG) != 0) && - (blockHdr.CRC != UCodeComputeCRC(mcData, blockHdr.size))) + if ((block_hdr.size == 0) || + (block_hdr.size > 0x7FFF) || + (((block_hdr.flags & DRXJ_UCODE_CRC_FLAG) != 0) && + (block_hdr.CRC != u_code_compute_crc(mc_data, block_hdr.size))) ) { /* Wrong data ! */ return DRX_STS_INVALID_ARG; } - mcBlockNrBytes = blockHdr.size * sizeof(u16); + mc_block_nr_bytes = block_hdr.size * sizeof(u16); /* Perform the desired action */ /* Check which part of MC need to be uploaded - Audio or not Audio */ - if (IsMCBlockAudio(blockHdr.addr) == uploadAudioMC) { + if (is_mc_block_audio(block_hdr.addr) == upload_audio_mc) { switch (action) { /*===================================================================*/ case UCODE_UPLOAD: { /* Upload microcode */ - if (demod->myAccessFunct-> - writeBlockFunc(devAddr, - (DRXaddr_t) blockHdr. - addr, mcBlockNrBytes, - mcData, + if (demod->my_access_funct-> + write_block_func(dev_addr, + (dr_xaddr_t) block_hdr. + addr, mc_block_nr_bytes, + mc_data, 0x0000) != DRX_STS_OK) { return (DRX_STS_ERROR); @@ -14458,58 +14458,58 @@ CtrlUCodeUpload(pDRXDemodInstance_t demod, case UCODE_VERIFY: { int result = 0; - u8 mcDataBuffer + u8 mc_dataBuffer [DRXJ_UCODE_MAX_BUF_SIZE]; - u32 bytesToCompare = 0; - u32 bytesLeftToCompare = 0; - DRXaddr_t currAddr = (DRXaddr_t) 0; - u8 *currPtr = NULL; + u32 bytes_to_compare = 0; + u32 bytes_left_to_compare = 0; + dr_xaddr_t curr_addr = (dr_xaddr_t) 0; + u8 *curr_ptr = NULL; - bytesLeftToCompare = mcBlockNrBytes; - currAddr = blockHdr.addr; - currPtr = mcData; + bytes_left_to_compare = mc_block_nr_bytes; + curr_addr = block_hdr.addr; + curr_ptr = mc_data; - while (bytesLeftToCompare != 0) { - if (bytesLeftToCompare > + while (bytes_left_to_compare != 0) { + if (bytes_left_to_compare > ((u32) DRXJ_UCODE_MAX_BUF_SIZE)) { - bytesToCompare = + bytes_to_compare = ((u32) DRXJ_UCODE_MAX_BUF_SIZE); } else { - bytesToCompare = - bytesLeftToCompare; + bytes_to_compare = + bytes_left_to_compare; } - if (demod->myAccessFunct-> - readBlockFunc(devAddr, - currAddr, + if (demod->my_access_funct-> + read_block_func(dev_addr, + curr_addr, (u16) - bytesToCompare, + bytes_to_compare, (u8 *) - mcDataBuffer, + mc_dataBuffer, 0x0000) != DRX_STS_OK) { return (DRX_STS_ERROR); } result = - DRXBSP_HST_Memcmp(currPtr, - mcDataBuffer, - bytesToCompare); + drxbsp_hst_memcmp(curr_ptr, + mc_dataBuffer, + bytes_to_compare); if (result != 0) { return (DRX_STS_ERROR); }; - currAddr += - ((DRXaddr_t) - (bytesToCompare / 2)); - currPtr = - &(currPtr[bytesToCompare]); - bytesLeftToCompare -= - ((u32) bytesToCompare); - } /* while( bytesToCompare > DRXJ_UCODE_MAX_BUF_SIZE ) */ + curr_addr += + ((dr_xaddr_t) + (bytes_to_compare / 2)); + curr_ptr = + &(curr_ptr[bytes_to_compare]); + bytes_left_to_compare -= + ((u32) bytes_to_compare); + } /* while( bytes_to_compare > DRXJ_UCODE_MAX_BUF_SIZE ) */ }; break; @@ -14521,13 +14521,13 @@ CtrlUCodeUpload(pDRXDemodInstance_t demod, } /* switch ( action ) */ } - /* if( IsMCBlockAudio( blockHdr.addr ) == uploadAudioMC ) */ + /* if( is_mc_block_audio( block_hdr.addr ) == upload_audio_mc ) */ /* Next block */ - mcData += mcBlockNrBytes; - } /* for( i = 0 ; iflagAudMcUploaded = false; + if (upload_audio_mc == false) { + ext_attr->flag_aud_mc_uploaded = false; } return (DRX_STS_OK); @@ -14540,30 +14540,30 @@ CtrlUCodeUpload(pDRXDemodInstance_t demod, /*===== SigStrength() =========================================================*/ /** -* \fn int CtrlSigStrength() +* \fn int ctrl_sig_strength() * \brief Retrieve signal strength. * \param devmod Pointer to demodulator instance. -* \param sigQuality Pointer to signal strength data; range 0, .. , 100. +* \param sig_quality Pointer to signal strength data; range 0, .. , 100. * \return int. -* \retval DRX_STS_OK sigStrength contains valid data. -* \retval DRX_STS_INVALID_ARG sigStrength is NULL. -* \retval DRX_STS_ERROR Erroneous data, sigStrength contains invalid data. +* \retval DRX_STS_OK sig_strength contains valid data. +* \retval DRX_STS_INVALID_ARG sig_strength is NULL. +* \retval DRX_STS_ERROR Erroneous data, sig_strength contains invalid data. */ static int -CtrlSigStrength(pDRXDemodInstance_t demod, u16 *sigStrength) +ctrl_sig_strength(pdrx_demod_instance_t demod, u16 *sig_strength) { - pDRXJData_t extAttr = NULL; + pdrxj_data_t ext_attr = NULL; enum drx_standard standard = DRX_STANDARD_UNKNOWN; /* Check arguments */ - if ((sigStrength == NULL) || (demod == NULL)) { + if ((sig_strength == NULL) || (demod == NULL)) { return (DRX_STS_INVALID_ARG); } - extAttr = (pDRXJData_t) demod->myExtAttr; - standard = extAttr->standard; - *sigStrength = 0; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; + standard = ext_attr->standard; + *sig_strength = 0; /* Signal strength indication for each standard */ switch (standard) { @@ -14573,7 +14573,7 @@ CtrlSigStrength(pDRXDemodInstance_t demod, u16 *sigStrength) case DRX_STANDARD_ITU_B: /* fallthrough */ case DRX_STANDARD_ITU_C: #endif - CHK_ERROR(GetSigStrength(demod, sigStrength)); + CHK_ERROR(get_sig_strength(demod, sig_strength)); break; #ifndef DRXJ_DIGITAL_ONLY case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ @@ -14583,7 +14583,7 @@ CtrlSigStrength(pDRXDemodInstance_t demod, u16 *sigStrength) case DRX_STANDARD_PAL_SECAM_LP: /* fallthrough */ case DRX_STANDARD_NTSC: /* fallthrough */ case DRX_STANDARD_FM: - CHK_ERROR(GetAtvSigStrength(demod, sigStrength)); + CHK_ERROR(get_atv_sig_strength(demod, sig_strength)); break; #endif case DRX_STANDARD_UNKNOWN: /* fallthrough */ @@ -14600,50 +14600,50 @@ rw_error: /*============================================================================*/ /** -* \fn int CtrlGetCfgOOBMisc() +* \fn int ctrl_get_cfg_oob_misc() * \brief Get current state information of OOB. -* \param pointer to DRXJCfgOOBMisc_t. +* \param pointer to drxj_cfg_oob_misc_t. * \return int. * */ #ifndef DRXJ_DIGITAL_ONLY static int -CtrlGetCfgOOBMisc(pDRXDemodInstance_t demod, pDRXJCfgOOBMisc_t misc) +ctrl_get_cfg_oob_misc(pdrx_demod_instance_t demod, p_drxj_cfg_oob_misc_t misc) { - struct i2c_device_addr *devAddr = NULL; + struct i2c_device_addr *dev_addr = NULL; u16 lock = 0U; u16 state = 0U; u16 data = 0U; - u16 digitalAGCMant = 0U; - u16 digitalAGCExp = 0U; + u16 digital_agc_mant = 0U; + u16 digital_agc_exp = 0U; /* check arguments */ if (misc == NULL) { return (DRX_STS_INVALID_ARG); } - devAddr = demod->myI2CDevAddr; + dev_addr = demod->my_i2c_dev_addr; /* TODO */ /* check if the same registers are used for all standards (QAM/VSB/ATV) */ - RR16(devAddr, ORX_NSU_TUN_IFGAIN_W__A, &misc->agc.IFAGC); - RR16(devAddr, ORX_NSU_TUN_RFGAIN_W__A, &misc->agc.RFAGC); - RR16(devAddr, ORX_FWP_SRC_DGN_W__A, &data); + RR16(dev_addr, ORX_NSU_TUN_IFGAIN_W__A, &misc->agc.IFAGC); + RR16(dev_addr, ORX_NSU_TUN_RFGAIN_W__A, &misc->agc.RFAGC); + RR16(dev_addr, ORX_FWP_SRC_DGN_W__A, &data); - digitalAGCMant = data & ORX_FWP_SRC_DGN_W_MANT__M; - digitalAGCExp = (data & ORX_FWP_SRC_DGN_W_EXP__M) + digital_agc_mant = data & ORX_FWP_SRC_DGN_W_MANT__M; + digital_agc_exp = (data & ORX_FWP_SRC_DGN_W_EXP__M) >> ORX_FWP_SRC_DGN_W_EXP__B; - misc->agc.DigitalAGC = digitalAGCMant << digitalAGCExp; + misc->agc.digital_agc = digital_agc_mant << digital_agc_exp; - SARR16(devAddr, SCU_RAM_ORX_SCU_LOCK__A, &lock); + SARR16(dev_addr, SCU_RAM_ORX_SCU_LOCK__A, &lock); - misc->anaGainLock = ((lock & 0x0001) ? true : false); - misc->digGainLock = ((lock & 0x0002) ? true : false); - misc->freqLock = ((lock & 0x0004) ? true : false); - misc->phaseLock = ((lock & 0x0008) ? true : false); - misc->symTimingLock = ((lock & 0x0010) ? true : false); - misc->eqLock = ((lock & 0x0020) ? true : false); + misc->ana_gain_lock = ((lock & 0x0001) ? true : false); + misc->dig_gain_lock = ((lock & 0x0002) ? true : false); + misc->freq_lock = ((lock & 0x0004) ? true : false); + misc->phase_lock = ((lock & 0x0008) ? true : false); + misc->sym_timing_lock = ((lock & 0x0010) ? true : false); + misc->eq_lock = ((lock & 0x0020) ? true : false); - SARR16(devAddr, SCU_RAM_ORX_SCU_STATE__A, &state); + SARR16(dev_addr, SCU_RAM_ORX_SCU_STATE__A, &state); misc->state = (state >> 8) & 0xff; return (DRX_STS_OK); @@ -14653,24 +14653,24 @@ rw_error: #endif /** -* \fn int CtrlGetCfgVSBMisc() +* \fn int ctrl_get_cfg_vsb_misc() * \brief Get current state information of OOB. -* \param pointer to DRXJCfgOOBMisc_t. +* \param pointer to drxj_cfg_oob_misc_t. * \return int. * */ static int -CtrlGetCfgVSBMisc(pDRXDemodInstance_t demod, pDRXJCfgVSBMisc_t misc) +ctrl_get_cfg_vsb_misc(pdrx_demod_instance_t demod, p_drxj_cfg_vsb_misc_t misc) { - struct i2c_device_addr *devAddr = NULL; + struct i2c_device_addr *dev_addr = NULL; /* check arguments */ if (misc == NULL) { return (DRX_STS_INVALID_ARG); } - devAddr = demod->myI2CDevAddr; + dev_addr = demod->my_i2c_dev_addr; - CHK_ERROR(GetVSBSymbErr(devAddr, &misc->symbError)); + CHK_ERROR(get_vsb_symb_err(dev_addr, &misc->symb_error)); return (DRX_STS_OK); rw_error: @@ -14680,10 +14680,10 @@ rw_error: /*============================================================================*/ /** -* \fn int CtrlSetCfgAgcIf() +* \fn int ctrl_set_cfg_agc_if() * \brief Set IF AGC. * \param demod demod instance -* \param agcSettings If agc configuration +* \param agc_settings If agc configuration * \return int. * * Check arguments @@ -14691,14 +14691,14 @@ rw_error: * */ static int -CtrlSetCfgAgcIf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings) +ctrl_set_cfg_agc_if(pdrx_demod_instance_t demod, p_drxj_cfg_agc_t agc_settings) { /* check arguments */ - if (agcSettings == NULL) { + if (agc_settings == NULL) { return (DRX_STS_INVALID_ARG); } - switch (agcSettings->ctrlMode) { + switch (agc_settings->ctrl_mode) { case DRX_AGC_CTRL_AUTO: /* fallthrough */ case DRX_AGC_CTRL_USER: /* fallthrough */ case DRX_AGC_CTRL_OFF: /* fallthrough */ @@ -14708,7 +14708,7 @@ CtrlSetCfgAgcIf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings) } /* Distpatch */ - switch (agcSettings->standard) { + switch (agc_settings->standard) { case DRX_STANDARD_8VSB: /* fallthrough */ #ifndef DRXJ_VSB_ONLY case DRX_STANDARD_ITU_A: /* fallthrough */ @@ -14724,7 +14724,7 @@ CtrlSetCfgAgcIf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings) case DRX_STANDARD_NTSC: /* fallthrough */ case DRX_STANDARD_FM: #endif - return SetAgcIf(demod, agcSettings, true); + return set_agc_if(demod, agc_settings, true); case DRX_STANDARD_UNKNOWN: default: return (DRX_STS_INVALID_ARG); @@ -14736,10 +14736,10 @@ CtrlSetCfgAgcIf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings) /*============================================================================*/ /** -* \fn int CtrlGetCfgAgcIf() +* \fn int ctrl_get_cfg_agc_if() * \brief Retrieve IF AGC settings. * \param demod demod instance -* \param agcSettings If agc configuration +* \param agc_settings If agc configuration * \return int. * * Check arguments @@ -14747,15 +14747,15 @@ CtrlSetCfgAgcIf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings) * */ static int -CtrlGetCfgAgcIf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings) +ctrl_get_cfg_agc_if(pdrx_demod_instance_t demod, p_drxj_cfg_agc_t agc_settings) { /* check arguments */ - if (agcSettings == NULL) { + if (agc_settings == NULL) { return (DRX_STS_INVALID_ARG); } /* Distpatch */ - switch (agcSettings->standard) { + switch (agc_settings->standard) { case DRX_STANDARD_8VSB: /* fallthrough */ #ifndef DRXJ_VSB_ONLY case DRX_STANDARD_ITU_A: /* fallthrough */ @@ -14771,7 +14771,7 @@ CtrlGetCfgAgcIf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings) case DRX_STANDARD_NTSC: /* fallthrough */ case DRX_STANDARD_FM: #endif - return GetAgcIf(demod, agcSettings); + return get_agc_if(demod, agc_settings); case DRX_STANDARD_UNKNOWN: default: return (DRX_STS_INVALID_ARG); @@ -14783,10 +14783,10 @@ CtrlGetCfgAgcIf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings) /*============================================================================*/ /** -* \fn int CtrlSetCfgAgcRf() +* \fn int ctrl_set_cfg_agc_rf() * \brief Set RF AGC. * \param demod demod instance -* \param agcSettings rf agc configuration +* \param agc_settings rf agc configuration * \return int. * * Check arguments @@ -14794,14 +14794,14 @@ CtrlGetCfgAgcIf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings) * */ static int -CtrlSetCfgAgcRf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings) +ctrl_set_cfg_agc_rf(pdrx_demod_instance_t demod, p_drxj_cfg_agc_t agc_settings) { /* check arguments */ - if (agcSettings == NULL) { + if (agc_settings == NULL) { return (DRX_STS_INVALID_ARG); } - switch (agcSettings->ctrlMode) { + switch (agc_settings->ctrl_mode) { case DRX_AGC_CTRL_AUTO: /* fallthrough */ case DRX_AGC_CTRL_USER: /* fallthrough */ case DRX_AGC_CTRL_OFF: @@ -14811,7 +14811,7 @@ CtrlSetCfgAgcRf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings) } /* Distpatch */ - switch (agcSettings->standard) { + switch (agc_settings->standard) { case DRX_STANDARD_8VSB: /* fallthrough */ #ifndef DRXJ_VSB_ONLY case DRX_STANDARD_ITU_A: /* fallthrough */ @@ -14827,7 +14827,7 @@ CtrlSetCfgAgcRf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings) case DRX_STANDARD_NTSC: /* fallthrough */ case DRX_STANDARD_FM: #endif - return SetAgcRf(demod, agcSettings, true); + return set_agc_rf(demod, agc_settings, true); case DRX_STANDARD_UNKNOWN: default: return (DRX_STS_INVALID_ARG); @@ -14839,10 +14839,10 @@ CtrlSetCfgAgcRf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings) /*============================================================================*/ /** -* \fn int CtrlGetCfgAgcRf() +* \fn int ctrl_get_cfg_agc_rf() * \brief Retrieve RF AGC settings. * \param demod demod instance -* \param agcSettings Rf agc configuration +* \param agc_settings Rf agc configuration * \return int. * * Check arguments @@ -14850,15 +14850,15 @@ CtrlSetCfgAgcRf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings) * */ static int -CtrlGetCfgAgcRf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings) +ctrl_get_cfg_agc_rf(pdrx_demod_instance_t demod, p_drxj_cfg_agc_t agc_settings) { /* check arguments */ - if (agcSettings == NULL) { + if (agc_settings == NULL) { return (DRX_STS_INVALID_ARG); } /* Distpatch */ - switch (agcSettings->standard) { + switch (agc_settings->standard) { case DRX_STANDARD_8VSB: /* fallthrough */ #ifndef DRXJ_VSB_ONLY case DRX_STANDARD_ITU_A: /* fallthrough */ @@ -14874,7 +14874,7 @@ CtrlGetCfgAgcRf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings) case DRX_STANDARD_NTSC: /* fallthrough */ case DRX_STANDARD_FM: #endif - return GetAgcRf(demod, agcSettings); + return get_agc_rf(demod, agc_settings); case DRX_STANDARD_UNKNOWN: default: return (DRX_STS_INVALID_ARG); @@ -14886,7 +14886,7 @@ CtrlGetCfgAgcRf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings) /*============================================================================*/ /** -* \fn int CtrlGetCfgAgcInternal() +* \fn int ctrl_get_cfg_agc_internal() * \brief Retrieve internal AGC value. * \param demod demod instance * \param u16 @@ -14897,47 +14897,47 @@ CtrlGetCfgAgcRf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings) * */ static int -CtrlGetCfgAgcInternal(pDRXDemodInstance_t demod, u16 *agcInternal) +ctrl_get_cfg_agc_internal(pdrx_demod_instance_t demod, u16 *agc_internal) { - struct i2c_device_addr *devAddr = NULL; - DRXLockStatus_t lockStatus = DRX_NOT_LOCKED; - pDRXJData_t extAttr = NULL; - u16 iqmCfScaleSh = 0; - u16 iqmCfPower = 0; - u16 iqmCfAmp = 0; - u16 iqmCfGain = 0; + struct i2c_device_addr *dev_addr = NULL; + drx_lock_status_t lock_status = DRX_NOT_LOCKED; + pdrxj_data_t ext_attr = NULL; + u16 iqm_cf_scale_sh = 0; + u16 iqm_cf_power = 0; + u16 iqm_cf_amp = 0; + u16 iqm_cf_gain = 0; /* check arguments */ - if (agcInternal == NULL) { + if (agc_internal == NULL) { return (DRX_STS_INVALID_ARG); } - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; - CHK_ERROR(CtrlLockStatus(demod, &lockStatus)); - if (lockStatus != DRXJ_DEMOD_LOCK && lockStatus != DRX_LOCKED) { - *agcInternal = 0; + CHK_ERROR(ctrl_lock_status(demod, &lock_status)); + if (lock_status != DRXJ_DEMOD_LOCK && lock_status != DRX_LOCKED) { + *agc_internal = 0; return DRX_STS_OK; } /* Distpatch */ - switch (extAttr->standard) { + switch (ext_attr->standard) { case DRX_STANDARD_8VSB: - iqmCfGain = 57; + iqm_cf_gain = 57; break; #ifndef DRXJ_VSB_ONLY case DRX_STANDARD_ITU_A: case DRX_STANDARD_ITU_B: case DRX_STANDARD_ITU_C: - switch (extAttr->constellation) { + switch (ext_attr->constellation) { case DRX_CONSTELLATION_QAM256: case DRX_CONSTELLATION_QAM128: case DRX_CONSTELLATION_QAM32: case DRX_CONSTELLATION_QAM16: - iqmCfGain = 57; + iqm_cf_gain = 57; break; case DRX_CONSTELLATION_QAM64: - iqmCfGain = 56; + iqm_cf_gain = 56; break; default: return (DRX_STS_ERROR); @@ -14948,18 +14948,18 @@ CtrlGetCfgAgcInternal(pDRXDemodInstance_t demod, u16 *agcInternal) return (DRX_STS_INVALID_ARG); } - RR16(devAddr, IQM_CF_POW__A, &iqmCfPower); - RR16(devAddr, IQM_CF_SCALE_SH__A, &iqmCfScaleSh); - RR16(devAddr, IQM_CF_AMP__A, &iqmCfAmp); + RR16(dev_addr, IQM_CF_POW__A, &iqm_cf_power); + RR16(dev_addr, IQM_CF_SCALE_SH__A, &iqm_cf_scale_sh); + RR16(dev_addr, IQM_CF_AMP__A, &iqm_cf_amp); /* IQM_CF_PWR_CORRECTION_dB = 3; P5dB =10*log10(IQM_CF_POW)+12-6*9-IQM_CF_PWR_CORRECTION_dB; */ /* P4dB = P5dB -20*log10(IQM_CF_AMP)-6*10 -IQM_CF_Gain_dB-18+6*(27-IQM_CF_SCALE_SH*2-10) +6*7+10*log10(1+0.115/4); */ /* PadcdB = P4dB +3 -6 +60; dBmV */ - *agcInternal = (u16) (Log10Times100(iqmCfPower) - - 2 * Log10Times100(iqmCfAmp) - - iqmCfGain - 120 * iqmCfScaleSh + 781); + *agc_internal = (u16) (log1_times100(iqm_cf_power) + - 2 * log1_times100(iqm_cf_amp) + - iqm_cf_gain - 120 * iqm_cf_scale_sh + 781); return (DRX_STS_OK); rw_error: @@ -14969,7 +14969,7 @@ rw_error: /*============================================================================*/ /** -* \fn int CtrlSetCfgPreSaw() +* \fn int ctrl_set_cfg_pre_saw() * \brief Set Pre-saw reference. * \param demod demod instance * \param u16 * @@ -14980,39 +14980,39 @@ rw_error: * */ static int -CtrlSetCfgPreSaw(pDRXDemodInstance_t demod, pDRXJCfgPreSaw_t preSaw) +ctrl_set_cfg_pre_saw(pdrx_demod_instance_t demod, p_drxj_cfg_pre_saw_t pre_saw) { - struct i2c_device_addr *devAddr = NULL; - pDRXJData_t extAttr = NULL; + struct i2c_device_addr *dev_addr = NULL; + pdrxj_data_t ext_attr = NULL; - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* check arguments */ - if ((preSaw == NULL) || (preSaw->reference > IQM_AF_PDREF__M) + if ((pre_saw == NULL) || (pre_saw->reference > IQM_AF_PDREF__M) ) { return (DRX_STS_INVALID_ARG); } /* Only if standard is currently active */ - if ((extAttr->standard == preSaw->standard) || - (DRXJ_ISQAMSTD(extAttr->standard) && - DRXJ_ISQAMSTD(preSaw->standard)) || - (DRXJ_ISATVSTD(extAttr->standard) && - DRXJ_ISATVSTD(preSaw->standard))) { - WR16(devAddr, IQM_AF_PDREF__A, preSaw->reference); + if ((ext_attr->standard == pre_saw->standard) || + (DRXJ_ISQAMSTD(ext_attr->standard) && + DRXJ_ISQAMSTD(pre_saw->standard)) || + (DRXJ_ISATVSTD(ext_attr->standard) && + DRXJ_ISATVSTD(pre_saw->standard))) { + WR16(dev_addr, IQM_AF_PDREF__A, pre_saw->reference); } /* Store pre-saw settings */ - switch (preSaw->standard) { + switch (pre_saw->standard) { case DRX_STANDARD_8VSB: - extAttr->vsbPreSawCfg = *preSaw; + ext_attr->vsb_pre_saw_cfg = *pre_saw; break; #ifndef DRXJ_VSB_ONLY case DRX_STANDARD_ITU_A: /* fallthrough */ case DRX_STANDARD_ITU_B: /* fallthrough */ case DRX_STANDARD_ITU_C: - extAttr->qamPreSawCfg = *preSaw; + ext_attr->qam_pre_saw_cfg = *pre_saw; break; #endif #ifndef DRXJ_DIGITAL_ONLY @@ -15023,7 +15023,7 @@ CtrlSetCfgPreSaw(pDRXDemodInstance_t demod, pDRXJCfgPreSaw_t preSaw) case DRX_STANDARD_PAL_SECAM_LP: /* fallthrough */ case DRX_STANDARD_NTSC: /* fallthrough */ case DRX_STANDARD_FM: - extAttr->atvPreSawCfg = *preSaw; + ext_attr->atv_pre_saw_cfg = *pre_saw; break; #endif default: @@ -15038,7 +15038,7 @@ rw_error: /*============================================================================*/ /** -* \fn int CtrlSetCfgAfeGain() +* \fn int ctrl_set_cfg_afe_gain() * \brief Set AFE Gain. * \param demod demod instance * \param u16 * @@ -15049,21 +15049,21 @@ rw_error: * */ static int -CtrlSetCfgAfeGain(pDRXDemodInstance_t demod, pDRXJCfgAfeGain_t afeGain) +ctrl_set_cfg_afe_gain(pdrx_demod_instance_t demod, p_drxj_cfg_afe_gain_t afe_gain) { - struct i2c_device_addr *devAddr = NULL; - pDRXJData_t extAttr = NULL; + struct i2c_device_addr *dev_addr = NULL; + pdrxj_data_t ext_attr = NULL; u8 gain = 0; /* check arguments */ - if (afeGain == NULL) { + if (afe_gain == NULL) { return (DRX_STS_INVALID_ARG); } - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; - switch (afeGain->standard) { + switch (afe_gain->standard) { case DRX_STANDARD_8VSB: /* fallthrough */ #ifndef DRXJ_VSB_ONLY case DRX_STANDARD_ITU_A: /* fallthrough */ @@ -15079,27 +15079,27 @@ CtrlSetCfgAfeGain(pDRXDemodInstance_t demod, pDRXJCfgAfeGain_t afeGain) /* TODO PGA gain is also written by microcode (at least by QAM and VSB) So I (PJ) think interface requires choice between auto, user mode */ - if (afeGain->gain >= 329) + if (afe_gain->gain >= 329) gain = 15; - else if (afeGain->gain <= 147) + else if (afe_gain->gain <= 147) gain = 0; else - gain = (afeGain->gain - 140 + 6) / 13; + gain = (afe_gain->gain - 140 + 6) / 13; /* Only if standard is currently active */ - if (extAttr->standard == afeGain->standard) - WR16(devAddr, IQM_AF_PGA_GAIN__A, gain); + if (ext_attr->standard == afe_gain->standard) + WR16(dev_addr, IQM_AF_PGA_GAIN__A, gain); /* Store AFE Gain settings */ - switch (afeGain->standard) { + switch (afe_gain->standard) { case DRX_STANDARD_8VSB: - extAttr->vsbPgaCfg = gain * 13 + 140; + ext_attr->vsb_pga_cfg = gain * 13 + 140; break; #ifndef DRXJ_VSB_ONLY case DRX_STANDARD_ITU_A: /* fallthrough */ case DRX_STANDARD_ITU_B: /* fallthrough */ case DRX_STANDARD_ITU_C: - extAttr->qamPgaCfg = gain * 13 + 140; + ext_attr->qam_pga_cfg = gain * 13 + 140; break; #endif default: @@ -15114,7 +15114,7 @@ rw_error: /*============================================================================*/ /** -* \fn int CtrlGetCfgPreSaw() +* \fn int ctrl_get_cfg_pre_saw() * \brief Get Pre-saw reference setting. * \param demod demod instance * \param u16 * @@ -15125,28 +15125,28 @@ rw_error: * */ static int -CtrlGetCfgPreSaw(pDRXDemodInstance_t demod, pDRXJCfgPreSaw_t preSaw) +ctrl_get_cfg_pre_saw(pdrx_demod_instance_t demod, p_drxj_cfg_pre_saw_t pre_saw) { - struct i2c_device_addr *devAddr = NULL; - pDRXJData_t extAttr = NULL; + struct i2c_device_addr *dev_addr = NULL; + pdrxj_data_t ext_attr = NULL; /* check arguments */ - if (preSaw == NULL) { + if (pre_saw == NULL) { return (DRX_STS_INVALID_ARG); } - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; - switch (preSaw->standard) { + switch (pre_saw->standard) { case DRX_STANDARD_8VSB: - *preSaw = extAttr->vsbPreSawCfg; + *pre_saw = ext_attr->vsb_pre_saw_cfg; break; #ifndef DRXJ_VSB_ONLY case DRX_STANDARD_ITU_A: /* fallthrough */ case DRX_STANDARD_ITU_B: /* fallthrough */ case DRX_STANDARD_ITU_C: - *preSaw = extAttr->qamPreSawCfg; + *pre_saw = ext_attr->qam_pre_saw_cfg; break; #endif #ifndef DRXJ_DIGITAL_ONLY @@ -15156,12 +15156,12 @@ CtrlGetCfgPreSaw(pDRXDemodInstance_t demod, pDRXJCfgPreSaw_t preSaw) case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */ case DRX_STANDARD_PAL_SECAM_LP: /* fallthrough */ case DRX_STANDARD_NTSC: - extAttr->atvPreSawCfg.standard = DRX_STANDARD_NTSC; - *preSaw = extAttr->atvPreSawCfg; + ext_attr->atv_pre_saw_cfg.standard = DRX_STANDARD_NTSC; + *pre_saw = ext_attr->atv_pre_saw_cfg; break; case DRX_STANDARD_FM: - extAttr->atvPreSawCfg.standard = DRX_STANDARD_FM; - *preSaw = extAttr->atvPreSawCfg; + ext_attr->atv_pre_saw_cfg.standard = DRX_STANDARD_FM; + *pre_saw = ext_attr->atv_pre_saw_cfg; break; #endif default: @@ -15174,7 +15174,7 @@ CtrlGetCfgPreSaw(pDRXDemodInstance_t demod, pDRXJCfgPreSaw_t preSaw) /*============================================================================*/ /** -* \fn int CtrlGetCfgAfeGain() +* \fn int ctrl_get_cfg_afe_gain() * \brief Get AFE Gain. * \param demod demod instance * \param u16 * @@ -15185,28 +15185,28 @@ CtrlGetCfgPreSaw(pDRXDemodInstance_t demod, pDRXJCfgPreSaw_t preSaw) * */ static int -CtrlGetCfgAfeGain(pDRXDemodInstance_t demod, pDRXJCfgAfeGain_t afeGain) +ctrl_get_cfg_afe_gain(pdrx_demod_instance_t demod, p_drxj_cfg_afe_gain_t afe_gain) { - struct i2c_device_addr *devAddr = NULL; - pDRXJData_t extAttr = NULL; + struct i2c_device_addr *dev_addr = NULL; + pdrxj_data_t ext_attr = NULL; /* check arguments */ - if (afeGain == NULL) { + if (afe_gain == NULL) { return (DRX_STS_INVALID_ARG); } - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; - switch (afeGain->standard) { + switch (afe_gain->standard) { case DRX_STANDARD_8VSB: - afeGain->gain = extAttr->vsbPgaCfg; + afe_gain->gain = ext_attr->vsb_pga_cfg; break; #ifndef DRXJ_VSB_ONLY case DRX_STANDARD_ITU_A: /* fallthrough */ case DRX_STANDARD_ITU_B: /* fallthrough */ case DRX_STANDARD_ITU_C: - afeGain->gain = extAttr->qamPgaCfg; + afe_gain->gain = ext_attr->qam_pga_cfg; break; #endif default: @@ -15219,7 +15219,7 @@ CtrlGetCfgAfeGain(pDRXDemodInstance_t demod, pDRXJCfgAfeGain_t afeGain) /*============================================================================*/ /** -* \fn int CtrlGetFecMeasSeqCount() +* \fn int ctrl_get_fec_meas_seq_count() * \brief Get FEC measurement sequnce number. * \param demod demod instance * \param u16 * @@ -15230,14 +15230,14 @@ CtrlGetCfgAfeGain(pDRXDemodInstance_t demod, pDRXJCfgAfeGain_t afeGain) * */ static int -CtrlGetFecMeasSeqCount(pDRXDemodInstance_t demod, u16 *fecMeasSeqCount) +ctrl_get_fec_meas_seq_count(pdrx_demod_instance_t demod, u16 *fec_meas_seq_count) { /* check arguments */ - if (fecMeasSeqCount == NULL) { + if (fec_meas_seq_count == NULL) { return (DRX_STS_INVALID_ARG); } - RR16(demod->myI2CDevAddr, SCU_RAM_FEC_MEAS_COUNT__A, fecMeasSeqCount); + RR16(demod->my_i2c_dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, fec_meas_seq_count); return (DRX_STS_OK); rw_error: @@ -15247,7 +15247,7 @@ rw_error: /*============================================================================*/ /** -* \fn int CtrlGetAccumCrRSCwErr() +* \fn int ctrl_get_accum_cr_rs_cw_err() * \brief Get accumulative corrected RS codeword number. * \param demod demod instance * \param u32 * @@ -15258,14 +15258,14 @@ rw_error: * */ static int -CtrlGetAccumCrRSCwErr(pDRXDemodInstance_t demod, u32 *accumCrRsCWErr) +ctrl_get_accum_cr_rs_cw_err(pdrx_demod_instance_t demod, u32 *accum_cr_rs_cw_err) { - if (accumCrRsCWErr == NULL) { + if (accum_cr_rs_cw_err == NULL) { return (DRX_STS_INVALID_ARG); } - RR32(demod->myI2CDevAddr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, - accumCrRsCWErr); + RR32(demod->my_i2c_dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, + accum_cr_rs_cw_err); return (DRX_STS_OK); rw_error: @@ -15273,100 +15273,100 @@ rw_error: } /** -* \fn int CtrlSetCfg() +* \fn int ctrl_set_cfg() * \brief Set 'some' configuration of the device. * \param devmod Pointer to demodulator instance. * \param config Pointer to configuration parameters (type and data). * \return int. */ -static int CtrlSetCfg(pDRXDemodInstance_t demod, pDRXCfg_t config) +static int ctrl_set_cfg(pdrx_demod_instance_t demod, pdrx_cfg_t config) { if (config == NULL) { return (DRX_STS_INVALID_ARG); } DUMMY_READ(); - switch (config->cfgType) { + switch (config->cfg_type) { case DRX_CFG_MPEG_OUTPUT: - return CtrlSetCfgMPEGOutput(demod, - (pDRXCfgMPEGOutput_t) config-> - cfgData); + return ctrl_set_cfg_mpeg_output(demod, + (pdrx_cfg_mpeg_output_t) config-> + cfg_data); case DRX_CFG_PINS_SAFE_MODE: - return CtrlSetCfgPdrSafeMode(demod, (bool *) config->cfgData); + return ctrl_set_cfg_pdr_safe_mode(demod, (bool *) config->cfg_data); case DRXJ_CFG_AGC_RF: - return CtrlSetCfgAgcRf(demod, (pDRXJCfgAgc_t) config->cfgData); + return ctrl_set_cfg_agc_rf(demod, (p_drxj_cfg_agc_t) config->cfg_data); case DRXJ_CFG_AGC_IF: - return CtrlSetCfgAgcIf(demod, (pDRXJCfgAgc_t) config->cfgData); + return ctrl_set_cfg_agc_if(demod, (p_drxj_cfg_agc_t) config->cfg_data); case DRXJ_CFG_PRE_SAW: - return CtrlSetCfgPreSaw(demod, - (pDRXJCfgPreSaw_t) config->cfgData); + return ctrl_set_cfg_pre_saw(demod, + (p_drxj_cfg_pre_saw_t) config->cfg_data); case DRXJ_CFG_AFE_GAIN: - return CtrlSetCfgAfeGain(demod, - (pDRXJCfgAfeGain_t) config->cfgData); + return ctrl_set_cfg_afe_gain(demod, + (p_drxj_cfg_afe_gain_t) config->cfg_data); case DRXJ_CFG_SMART_ANT: - return CtrlSetCfgSmartAnt(demod, - (pDRXJCfgSmartAnt_t) (config-> - cfgData)); + return ctrl_set_cfg_smart_ant(demod, + (p_drxj_cfg_smart_ant_t) (config-> + cfg_data)); case DRXJ_CFG_RESET_PACKET_ERR: - return CtrlSetCfgResetPktErr(demod); + return ctrl_set_cfg_reset_pkt_err(demod); #ifndef DRXJ_DIGITAL_ONLY case DRXJ_CFG_OOB_PRE_SAW: - return CtrlSetCfgOOBPreSAW(demod, (u16 *) (config->cfgData)); + return ctrl_set_cfg_oob_pre_saw(demod, (u16 *) (config->cfg_data)); case DRXJ_CFG_OOB_LO_POW: - return CtrlSetCfgOOBLoPower(demod, - (pDRXJCfgOobLoPower_t) (config-> - cfgData)); + return ctrl_set_cfg_oob_lo_power(demod, + (p_drxj_cfg_oob_lo_power_t) (config-> + cfg_data)); case DRXJ_CFG_ATV_MISC: - return CtrlSetCfgAtvMisc(demod, - (pDRXJCfgAtvMisc_t) config->cfgData); + return ctrl_set_cfg_atv_misc(demod, + (p_drxj_cfg_atv_misc_t) config->cfg_data); case DRXJ_CFG_ATV_EQU_COEF: - return CtrlSetCfgAtvEquCoef(demod, - (pDRXJCfgAtvEquCoef_t) config-> - cfgData); + return ctrl_set_cfg_atv_equ_coef(demod, + (p_drxj_cfg_atv_equ_coef_t) config-> + cfg_data); case DRXJ_CFG_ATV_OUTPUT: - return CtrlSetCfgATVOutput(demod, - (pDRXJCfgAtvOutput_t) config-> - cfgData); + return ctrl_set_cfg_atv_output(demod, + (p_drxj_cfg_atv_output_t) config-> + cfg_data); #endif case DRXJ_CFG_MPEG_OUTPUT_MISC: - return CtrlSetCfgMpegOutputMisc(demod, - (pDRXJCfgMpegOutputMisc_t) - config->cfgData); + return ctrl_set_cfg_mpeg_output_misc(demod, + (p_drxj_cfg_mpeg_output_misc_t) + config->cfg_data); #ifndef DRXJ_EXCLUDE_AUDIO case DRX_CFG_AUD_VOLUME: - return AUDCtrlSetCfgVolume(demod, - (pDRXCfgAudVolume_t) config-> - cfgData); + return aud_ctrl_set_cfg_volume(demod, + (pdrx_cfg_aud_volume_t) config-> + cfg_data); case DRX_CFG_I2S_OUTPUT: - return AUDCtrlSetCfgOutputI2S(demod, - (pDRXCfgI2SOutput_t) config-> - cfgData); + return aud_ctrl_set_cfg_output_i2s(demod, + (pdrx_cfg_i2s_output_t) config-> + cfg_data); case DRX_CFG_AUD_AUTOSOUND: - return AUDCtrSetlCfgAutoSound(demod, (pDRXCfgAudAutoSound_t) - config->cfgData); + return aud_ctr_setl_cfg_auto_sound(demod, (pdrx_cfg_aud_auto_sound_t) + config->cfg_data); case DRX_CFG_AUD_ASS_THRES: - return AUDCtrlSetCfgASSThres(demod, (pDRXCfgAudASSThres_t) - config->cfgData); + return aud_ctrl_set_cfg_ass_thres(demod, (pdrx_cfg_aud_ass_thres_t) + config->cfg_data); case DRX_CFG_AUD_CARRIER: - return AUDCtrlSetCfgCarrier(demod, - (pDRXCfgAudCarriers_t) config-> - cfgData); + return aud_ctrl_set_cfg_carrier(demod, + (pdrx_cfg_aud_carriers_t) config-> + cfg_data); case DRX_CFG_AUD_DEVIATION: - return AUDCtrlSetCfgDev(demod, - (pDRXCfgAudDeviation_t) config-> - cfgData); + return aud_ctrl_set_cfg_dev(demod, + (pdrx_cfg_aud_deviation_t) config-> + cfg_data); case DRX_CFG_AUD_PRESCALE: - return AUDCtrlSetCfgPrescale(demod, - (pDRXCfgAudPrescale_t) config-> - cfgData); + return aud_ctrl_set_cfg_prescale(demod, + (pdrx_cfg_aud_prescale_t) config-> + cfg_data); case DRX_CFG_AUD_MIXER: - return AUDCtrlSetCfgMixer(demod, - (pDRXCfgAudMixer_t) config->cfgData); + return aud_ctrl_set_cfg_mixer(demod, + (pdrx_cfg_aud_mixer_t) config->cfg_data); case DRX_CFG_AUD_AVSYNC: - return AUDCtrlSetCfgAVSync(demod, - (pDRXCfgAudAVSync_t) config-> - cfgData); + return aud_ctrl_set_cfg_av_sync(demod, + (pdrx_cfg_aud_av_sync_t) config-> + cfg_data); #endif default: @@ -15381,14 +15381,14 @@ rw_error: /*============================================================================*/ /** -* \fn int CtrlGetCfg() +* \fn int ctrl_get_cfg() * \brief Get 'some' configuration of the device. * \param devmod Pointer to demodulator instance. * \param config Pointer to configuration parameters (type and data). * \return int. */ -static int CtrlGetCfg(pDRXDemodInstance_t demod, pDRXCfg_t config) +static int ctrl_get_cfg(pdrx_demod_instance_t demod, pdrx_cfg_t config) { if (config == NULL) { return (DRX_STS_INVALID_ARG); @@ -15396,108 +15396,108 @@ static int CtrlGetCfg(pDRXDemodInstance_t demod, pDRXCfg_t config) DUMMY_READ(); - switch (config->cfgType) { + switch (config->cfg_type) { case DRX_CFG_MPEG_OUTPUT: - return CtrlGetCfgMPEGOutput(demod, - (pDRXCfgMPEGOutput_t) config-> - cfgData); + return ctrl_get_cfg_mpeg_output(demod, + (pdrx_cfg_mpeg_output_t) config-> + cfg_data); case DRX_CFG_PINS_SAFE_MODE: - return CtrlGetCfgPdrSafeMode(demod, (bool *) config->cfgData); + return ctrl_get_cfg_pdr_safe_mode(demod, (bool *) config->cfg_data); case DRXJ_CFG_AGC_RF: - return CtrlGetCfgAgcRf(demod, (pDRXJCfgAgc_t) config->cfgData); + return ctrl_get_cfg_agc_rf(demod, (p_drxj_cfg_agc_t) config->cfg_data); case DRXJ_CFG_AGC_IF: - return CtrlGetCfgAgcIf(demod, (pDRXJCfgAgc_t) config->cfgData); + return ctrl_get_cfg_agc_if(demod, (p_drxj_cfg_agc_t) config->cfg_data); case DRXJ_CFG_AGC_INTERNAL: - return CtrlGetCfgAgcInternal(demod, (u16 *) config->cfgData); + return ctrl_get_cfg_agc_internal(demod, (u16 *) config->cfg_data); case DRXJ_CFG_PRE_SAW: - return CtrlGetCfgPreSaw(demod, - (pDRXJCfgPreSaw_t) config->cfgData); + return ctrl_get_cfg_pre_saw(demod, + (p_drxj_cfg_pre_saw_t) config->cfg_data); case DRXJ_CFG_AFE_GAIN: - return CtrlGetCfgAfeGain(demod, - (pDRXJCfgAfeGain_t) config->cfgData); + return ctrl_get_cfg_afe_gain(demod, + (p_drxj_cfg_afe_gain_t) config->cfg_data); case DRXJ_CFG_ACCUM_CR_RS_CW_ERR: - return CtrlGetAccumCrRSCwErr(demod, (u32 *) config->cfgData); + return ctrl_get_accum_cr_rs_cw_err(demod, (u32 *) config->cfg_data); case DRXJ_CFG_FEC_MERS_SEQ_COUNT: - return CtrlGetFecMeasSeqCount(demod, (u16 *) config->cfgData); + return ctrl_get_fec_meas_seq_count(demod, (u16 *) config->cfg_data); case DRXJ_CFG_VSB_MISC: - return CtrlGetCfgVSBMisc(demod, - (pDRXJCfgVSBMisc_t) config->cfgData); + return ctrl_get_cfg_vsb_misc(demod, + (p_drxj_cfg_vsb_misc_t) config->cfg_data); case DRXJ_CFG_SYMBOL_CLK_OFFSET: - return CtrlGetCfgSymbolClockOffset(demod, - (s32 *) config->cfgData); + return ctrl_get_cfg_symbol_clock_offset(demod, + (s32 *) config->cfg_data); #ifndef DRXJ_DIGITAL_ONLY case DRXJ_CFG_OOB_MISC: - return CtrlGetCfgOOBMisc(demod, - (pDRXJCfgOOBMisc_t) config->cfgData); + return ctrl_get_cfg_oob_misc(demod, + (p_drxj_cfg_oob_misc_t) config->cfg_data); case DRXJ_CFG_OOB_PRE_SAW: - return CtrlGetCfgOOBPreSAW(demod, (u16 *) (config->cfgData)); + return ctrl_get_cfg_oob_pre_saw(demod, (u16 *) (config->cfg_data)); case DRXJ_CFG_OOB_LO_POW: - return CtrlGetCfgOOBLoPower(demod, - (pDRXJCfgOobLoPower_t) (config-> - cfgData)); + return ctrl_get_cfg_oob_lo_power(demod, + (p_drxj_cfg_oob_lo_power_t) (config-> + cfg_data)); case DRXJ_CFG_ATV_EQU_COEF: - return CtrlGetCfgAtvEquCoef(demod, - (pDRXJCfgAtvEquCoef_t) config-> - cfgData); + return ctrl_get_cfg_atv_equ_coef(demod, + (p_drxj_cfg_atv_equ_coef_t) config-> + cfg_data); case DRXJ_CFG_ATV_MISC: - return CtrlGetCfgAtvMisc(demod, - (pDRXJCfgAtvMisc_t) config->cfgData); + return ctrl_get_cfg_atv_misc(demod, + (p_drxj_cfg_atv_misc_t) config->cfg_data); case DRXJ_CFG_ATV_OUTPUT: - return CtrlGetCfgAtvOutput(demod, - (pDRXJCfgAtvOutput_t) config-> - cfgData); + return ctrl_get_cfg_atv_output(demod, + (p_drxj_cfg_atv_output_t) config-> + cfg_data); case DRXJ_CFG_ATV_AGC_STATUS: - return CtrlGetCfgAtvAgcStatus(demod, - (pDRXJCfgAtvAgcStatus_t) config-> - cfgData); + return ctrl_get_cfg_atv_agc_status(demod, + (p_drxj_cfg_atv_agc_status_t) config-> + cfg_data); #endif case DRXJ_CFG_MPEG_OUTPUT_MISC: - return CtrlGetCfgMpegOutputMisc(demod, - (pDRXJCfgMpegOutputMisc_t) - config->cfgData); + return ctrl_get_cfg_mpeg_output_misc(demod, + (p_drxj_cfg_mpeg_output_misc_t) + config->cfg_data); case DRXJ_CFG_HW_CFG: - return CtrlGetCfgHwCfg(demod, - (pDRXJCfgHwCfg_t) config->cfgData); + return ctrl_get_cfg_hw_cfg(demod, + (p_drxj_cfg_hw_cfg_t) config->cfg_data); #ifndef DRXJ_EXCLUDE_AUDIO case DRX_CFG_AUD_VOLUME: - return AUDCtrlGetCfgVolume(demod, - (pDRXCfgAudVolume_t) config-> - cfgData); + return aud_ctrl_get_cfg_volume(demod, + (pdrx_cfg_aud_volume_t) config-> + cfg_data); case DRX_CFG_I2S_OUTPUT: - return AUDCtrlGetCfgOutputI2S(demod, - (pDRXCfgI2SOutput_t) config-> - cfgData); + return aud_ctrl_get_cfg_output_i2s(demod, + (pdrx_cfg_i2s_output_t) config-> + cfg_data); case DRX_CFG_AUD_RDS: - return AUDCtrlGetCfgRDS(demod, - (pDRXCfgAudRDS_t) config->cfgData); + return aud_ctrl_get_cfg_rds(demod, + (pdrx_cfg_aud_rds_t) config->cfg_data); case DRX_CFG_AUD_AUTOSOUND: - return AUDCtrlGetCfgAutoSound(demod, - (pDRXCfgAudAutoSound_t) config-> - cfgData); + return aud_ctrl_get_cfg_auto_sound(demod, + (pdrx_cfg_aud_auto_sound_t) config-> + cfg_data); case DRX_CFG_AUD_ASS_THRES: - return AUDCtrlGetCfgASSThres(demod, - (pDRXCfgAudASSThres_t) config-> - cfgData); + return aud_ctrl_get_cfg_ass_thres(demod, + (pdrx_cfg_aud_ass_thres_t) config-> + cfg_data); case DRX_CFG_AUD_CARRIER: - return AUDCtrlGetCfgCarrier(demod, - (pDRXCfgAudCarriers_t) config-> - cfgData); + return aud_ctrl_get_cfg_carrier(demod, + (pdrx_cfg_aud_carriers_t) config-> + cfg_data); case DRX_CFG_AUD_DEVIATION: - return AUDCtrlGetCfgDev(demod, - (pDRXCfgAudDeviation_t) config-> - cfgData); + return aud_ctrl_get_cfg_dev(demod, + (pdrx_cfg_aud_deviation_t) config-> + cfg_data); case DRX_CFG_AUD_PRESCALE: - return AUDCtrlGetCfgPrescale(demod, - (pDRXCfgAudPrescale_t) config-> - cfgData); + return aud_ctrl_get_cfg_prescale(demod, + (pdrx_cfg_aud_prescale_t) config-> + cfg_data); case DRX_CFG_AUD_MIXER: - return AUDCtrlGetCfgMixer(demod, - (pDRXCfgAudMixer_t) config->cfgData); + return aud_ctrl_get_cfg_mixer(demod, + (pdrx_cfg_aud_mixer_t) config->cfg_data); case DRX_CFG_AUD_AVSYNC: - return AUDCtrlGetCfgAVSync(demod, - (pDRXCfgAudAVSync_t) config-> - cfgData); + return aud_ctrl_get_cfg_av_sync(demod, + (pdrx_cfg_aud_av_sync_t) config-> + cfg_data); #endif default: @@ -15512,262 +15512,262 @@ rw_error: /*============================================================================= ===== EXPORTED FUNCTIONS ====================================================*/ /** -* \fn DRXJ_Open() +* \fn drxj_open() * \brief Open the demod instance, configure device, configure drxdriver * \return Status_t Return status. * -* DRXJ_Open() can be called with a NULL ucode image => no ucode upload. -* This means that DRXJ_Open() must NOT contain SCU commands or, in general, +* drxj_open() can be called with a NULL ucode image => no ucode upload. +* This means that drxj_open() must NOT contain SCU commands or, in general, * rely on SCU or AUD ucode to be present. * */ -int DRXJ_Open(pDRXDemodInstance_t demod) +int drxj_open(pdrx_demod_instance_t demod) { - struct i2c_device_addr *devAddr = NULL; - pDRXJData_t extAttr = NULL; - pDRXCommonAttr_t commonAttr = NULL; - u32 driverVersion = 0; - DRXUCodeInfo_t ucodeInfo; - DRXCfgMPEGOutput_t cfgMPEGOutput; + struct i2c_device_addr *dev_addr = NULL; + pdrxj_data_t ext_attr = NULL; + pdrx_common_attr_t common_attr = NULL; + u32 driver_version = 0; + drxu_code_info_t ucode_info; + drx_cfg_mpeg_output_t cfg_mpeg_output; /* Check arguments */ - if (demod->myExtAttr == NULL) { + if (demod->my_ext_attr == NULL) { return (DRX_STS_INVALID_ARG); } - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; - commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; + common_attr = (pdrx_common_attr_t) demod->my_common_attr; - CHK_ERROR(PowerUpDevice(demod)); - commonAttr->currentPowerMode = DRX_POWER_UP; + CHK_ERROR(power_up_device(demod)); + common_attr->current_power_mode = DRX_POWER_UP; /* has to be in front of setIqmAf and setOrxNsuAox */ - CHK_ERROR(GetDeviceCapabilities(demod)); + CHK_ERROR(get_device_capabilities(demod)); /* Soft reset of sys- and osc-clockdomain */ - WR16(devAddr, SIO_CC_SOFT_RST__A, (SIO_CC_SOFT_RST_SYS__M | + WR16(dev_addr, SIO_CC_SOFT_RST__A, (SIO_CC_SOFT_RST_SYS__M | SIO_CC_SOFT_RST_OSC__M)); - WR16(devAddr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); - CHK_ERROR(DRXBSP_HST_Sleep(1)); + WR16(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); + CHK_ERROR(drxbsp_hst_sleep(1)); /* TODO first make sure that everything keeps working before enabling this */ /* PowerDownAnalogBlocks() */ - WR16(devAddr, ATV_TOP_STDBY__A, (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE) + WR16(dev_addr, ATV_TOP_STDBY__A, (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE) | ATV_TOP_STDBY_SIF_STDBY_STANDBY); - CHK_ERROR(SetIqmAf(demod, false)); - CHK_ERROR(SetOrxNsuAox(demod, false)); + CHK_ERROR(set_iqm_af(demod, false)); + CHK_ERROR(set_orx_nsu_aox(demod, false)); - CHK_ERROR(InitHI(demod)); + CHK_ERROR(init_hi(demod)); /* disable mpegoutput pins */ - cfgMPEGOutput.enableMPEGOutput = false; - CHK_ERROR(CtrlSetCfgMPEGOutput(demod, &cfgMPEGOutput)); + cfg_mpeg_output.enable_mpeg_output = false; + CHK_ERROR(ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output)); /* Stop AUD Inform SetAudio it will need to do all setting */ - CHK_ERROR(PowerDownAud(demod)); + CHK_ERROR(power_down_aud(demod)); /* Stop SCU */ - WR16(devAddr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP); + WR16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP); /* Upload microcode */ - if (commonAttr->microcode != NULL) { + if (common_attr->microcode != NULL) { /* Dirty trick to use common ucode upload & verify, pretend device is already open */ - commonAttr->isOpened = true; - ucodeInfo.mcData = commonAttr->microcode; - ucodeInfo.mcSize = commonAttr->microcodeSize; + common_attr->is_opened = true; + ucode_info.mc_data = common_attr->microcode; + ucode_info.mc_size = common_attr->microcode_size; #ifdef DRXJ_SPLIT_UCODE_UPLOAD /* Upload microcode without audio part */ - CHK_ERROR(CtrlUCodeUpload - (demod, &ucodeInfo, UCODE_UPLOAD, false)); + CHK_ERROR(ctrl_u_codeUpload + (demod, &ucode_info, UCODE_UPLOAD, false)); #else - CHK_ERROR(DRX_Ctrl(demod, DRX_CTRL_LOAD_UCODE, &ucodeInfo)); + CHK_ERROR(drx_ctrl(demod, DRX_CTRL_LOAD_UCODE, &ucode_info)); #endif /* DRXJ_SPLIT_UCODE_UPLOAD */ - if (commonAttr->verifyMicrocode == true) { + if (common_attr->verify_microcode == true) { #ifdef DRXJ_SPLIT_UCODE_UPLOAD - CHK_ERROR(CtrlUCodeUpload - (demod, &ucodeInfo, UCODE_VERIFY, false)); + CHK_ERROR(ctrl_u_codeUpload + (demod, &ucode_info, UCODE_VERIFY, false)); #else - CHK_ERROR(DRX_Ctrl - (demod, DRX_CTRL_VERIFY_UCODE, &ucodeInfo)); + CHK_ERROR(drx_ctrl + (demod, DRX_CTRL_VERIFY_UCODE, &ucode_info)); #endif /* DRXJ_SPLIT_UCODE_UPLOAD */ } - commonAttr->isOpened = false; + common_attr->is_opened = false; } /* Run SCU for a little while to initialize microcode version numbers */ - WR16(devAddr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); + WR16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); /* Open tuner instance */ - if (demod->myTuner != NULL) { - demod->myTuner->myCommonAttr->myUserData = (void *)demod; + if (demod->my_tuner != NULL) { + demod->my_tuner->my_common_attr->myUser_data = (void *)demod; - if (commonAttr->tunerPortNr == 1) { - bool bridgeClosed = true; - CHK_ERROR(CtrlI2CBridge(demod, &bridgeClosed)); + if (common_attr->tuner_port_nr == 1) { + bool bridge_closed = true; + CHK_ERROR(ctrl_i2c_bridge(demod, &bridge_closed)); } - CHK_ERROR(DRXBSP_TUNER_Open(demod->myTuner)); + CHK_ERROR(drxbsp_tuner_open(demod->my_tuner)); - if (commonAttr->tunerPortNr == 1) { - bool bridgeClosed = false; - CHK_ERROR(CtrlI2CBridge(demod, &bridgeClosed)); + if (common_attr->tuner_port_nr == 1) { + bool bridge_closed = false; + CHK_ERROR(ctrl_i2c_bridge(demod, &bridge_closed)); } - commonAttr->tunerMinFreqRF = - ((demod->myTuner)->myCommonAttr->minFreqRF); - commonAttr->tunerMaxFreqRF = - ((demod->myTuner)->myCommonAttr->maxFreqRF); + common_attr->tuner_min_freq_rf = + ((demod->my_tuner)->my_common_attr->min_freq_rf); + common_attr->tuner_max_freq_rf = + ((demod->my_tuner)->my_common_attr->max_freq_rf); } /* Initialize scan timeout */ - commonAttr->scanDemodLockTimeout = DRXJ_SCAN_TIMEOUT; - commonAttr->scanDesiredLock = DRX_LOCKED; + common_attr->scan_demod_lock_timeout = DRXJ_SCAN_TIMEOUT; + common_attr->scan_desired_lock = DRX_LOCKED; /* Initialize default AFE configuartion for QAM */ - if (extAttr->hasLNA) { + if (ext_attr->has_lna) { /* IF AGC off, PGA active */ #ifndef DRXJ_VSB_ONLY - extAttr->qamIfAgcCfg.standard = DRX_STANDARD_ITU_B; - extAttr->qamIfAgcCfg.ctrlMode = DRX_AGC_CTRL_OFF; - extAttr->qamPgaCfg = 140 + (11 * 13); + ext_attr->qam_if_agc_cfg.standard = DRX_STANDARD_ITU_B; + ext_attr->qam_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_OFF; + ext_attr->qam_pga_cfg = 140 + (11 * 13); #endif - extAttr->vsbIfAgcCfg.standard = DRX_STANDARD_8VSB; - extAttr->vsbIfAgcCfg.ctrlMode = DRX_AGC_CTRL_OFF; - extAttr->vsbPgaCfg = 140 + (11 * 13); + ext_attr->vsb_if_agc_cfg.standard = DRX_STANDARD_8VSB; + ext_attr->vsb_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_OFF; + ext_attr->vsb_pga_cfg = 140 + (11 * 13); } else { /* IF AGC on, PGA not active */ #ifndef DRXJ_VSB_ONLY - extAttr->qamIfAgcCfg.standard = DRX_STANDARD_ITU_B; - extAttr->qamIfAgcCfg.ctrlMode = DRX_AGC_CTRL_AUTO; - extAttr->qamIfAgcCfg.minOutputLevel = 0; - extAttr->qamIfAgcCfg.maxOutputLevel = 0x7FFF; - extAttr->qamIfAgcCfg.speed = 3; - extAttr->qamIfAgcCfg.top = 1297; - extAttr->qamPgaCfg = 140; + ext_attr->qam_if_agc_cfg.standard = DRX_STANDARD_ITU_B; + ext_attr->qam_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; + ext_attr->qam_if_agc_cfg.min_output_level = 0; + ext_attr->qam_if_agc_cfg.max_output_level = 0x7FFF; + ext_attr->qam_if_agc_cfg.speed = 3; + ext_attr->qam_if_agc_cfg.top = 1297; + ext_attr->qam_pga_cfg = 140; #endif - extAttr->vsbIfAgcCfg.standard = DRX_STANDARD_8VSB; - extAttr->vsbIfAgcCfg.ctrlMode = DRX_AGC_CTRL_AUTO; - extAttr->vsbIfAgcCfg.minOutputLevel = 0; - extAttr->vsbIfAgcCfg.maxOutputLevel = 0x7FFF; - extAttr->vsbIfAgcCfg.speed = 3; - extAttr->vsbIfAgcCfg.top = 1024; - extAttr->vsbPgaCfg = 140; - } - /* TODO: remove minOutputLevel and maxOutputLevel for both QAM and VSB after */ + ext_attr->vsb_if_agc_cfg.standard = DRX_STANDARD_8VSB; + ext_attr->vsb_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; + ext_attr->vsb_if_agc_cfg.min_output_level = 0; + ext_attr->vsb_if_agc_cfg.max_output_level = 0x7FFF; + ext_attr->vsb_if_agc_cfg.speed = 3; + ext_attr->vsb_if_agc_cfg.top = 1024; + ext_attr->vsb_pga_cfg = 140; + } + /* TODO: remove min_output_level and max_output_level for both QAM and VSB after */ /* mc has not used them */ #ifndef DRXJ_VSB_ONLY - extAttr->qamRfAgcCfg.standard = DRX_STANDARD_ITU_B; - extAttr->qamRfAgcCfg.ctrlMode = DRX_AGC_CTRL_AUTO; - extAttr->qamRfAgcCfg.minOutputLevel = 0; - extAttr->qamRfAgcCfg.maxOutputLevel = 0x7FFF; - extAttr->qamRfAgcCfg.speed = 3; - extAttr->qamRfAgcCfg.top = 9500; - extAttr->qamRfAgcCfg.cutOffCurrent = 4000; - extAttr->qamPreSawCfg.standard = DRX_STANDARD_ITU_B; - extAttr->qamPreSawCfg.reference = 0x07; - extAttr->qamPreSawCfg.usePreSaw = true; + ext_attr->qam_rf_agc_cfg.standard = DRX_STANDARD_ITU_B; + ext_attr->qam_rf_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; + ext_attr->qam_rf_agc_cfg.min_output_level = 0; + ext_attr->qam_rf_agc_cfg.max_output_level = 0x7FFF; + ext_attr->qam_rf_agc_cfg.speed = 3; + ext_attr->qam_rf_agc_cfg.top = 9500; + ext_attr->qam_rf_agc_cfg.cut_off_current = 4000; + ext_attr->qam_pre_saw_cfg.standard = DRX_STANDARD_ITU_B; + ext_attr->qam_pre_saw_cfg.reference = 0x07; + ext_attr->qam_pre_saw_cfg.use_pre_saw = true; #endif /* Initialize default AFE configuartion for VSB */ - extAttr->vsbRfAgcCfg.standard = DRX_STANDARD_8VSB; - extAttr->vsbRfAgcCfg.ctrlMode = DRX_AGC_CTRL_AUTO; - extAttr->vsbRfAgcCfg.minOutputLevel = 0; - extAttr->vsbRfAgcCfg.maxOutputLevel = 0x7FFF; - extAttr->vsbRfAgcCfg.speed = 3; - extAttr->vsbRfAgcCfg.top = 9500; - extAttr->vsbRfAgcCfg.cutOffCurrent = 4000; - extAttr->vsbPreSawCfg.standard = DRX_STANDARD_8VSB; - extAttr->vsbPreSawCfg.reference = 0x07; - extAttr->vsbPreSawCfg.usePreSaw = true; + ext_attr->vsb_rf_agc_cfg.standard = DRX_STANDARD_8VSB; + ext_attr->vsb_rf_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; + ext_attr->vsb_rf_agc_cfg.min_output_level = 0; + ext_attr->vsb_rf_agc_cfg.max_output_level = 0x7FFF; + ext_attr->vsb_rf_agc_cfg.speed = 3; + ext_attr->vsb_rf_agc_cfg.top = 9500; + ext_attr->vsb_rf_agc_cfg.cut_off_current = 4000; + ext_attr->vsb_pre_saw_cfg.standard = DRX_STANDARD_8VSB; + ext_attr->vsb_pre_saw_cfg.reference = 0x07; + ext_attr->vsb_pre_saw_cfg.use_pre_saw = true; #ifndef DRXJ_DIGITAL_ONLY /* Initialize default AFE configuartion for ATV */ - extAttr->atvRfAgcCfg.standard = DRX_STANDARD_NTSC; - extAttr->atvRfAgcCfg.ctrlMode = DRX_AGC_CTRL_AUTO; - extAttr->atvRfAgcCfg.top = 9500; - extAttr->atvRfAgcCfg.cutOffCurrent = 4000; - extAttr->atvRfAgcCfg.speed = 3; - extAttr->atvIfAgcCfg.standard = DRX_STANDARD_NTSC; - extAttr->atvIfAgcCfg.ctrlMode = DRX_AGC_CTRL_AUTO; - extAttr->atvIfAgcCfg.speed = 3; - extAttr->atvIfAgcCfg.top = 2400; - extAttr->atvPreSawCfg.reference = 0x0007; - extAttr->atvPreSawCfg.usePreSaw = true; - extAttr->atvPreSawCfg.standard = DRX_STANDARD_NTSC; + ext_attr->atv_rf_agc_cfg.standard = DRX_STANDARD_NTSC; + ext_attr->atv_rf_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; + ext_attr->atv_rf_agc_cfg.top = 9500; + ext_attr->atv_rf_agc_cfg.cut_off_current = 4000; + ext_attr->atv_rf_agc_cfg.speed = 3; + ext_attr->atv_if_agc_cfg.standard = DRX_STANDARD_NTSC; + ext_attr->atv_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; + ext_attr->atv_if_agc_cfg.speed = 3; + ext_attr->atv_if_agc_cfg.top = 2400; + ext_attr->atv_pre_saw_cfg.reference = 0x0007; + ext_attr->atv_pre_saw_cfg.use_pre_saw = true; + ext_attr->atv_pre_saw_cfg.standard = DRX_STANDARD_NTSC; #endif - extAttr->standard = DRX_STANDARD_UNKNOWN; + ext_attr->standard = DRX_STANDARD_UNKNOWN; - CHK_ERROR(SmartAntInit(demod)); + CHK_ERROR(smart_ant_init(demod)); /* Stamp driver version number in SCU data RAM in BCD code Done to enable field application engineers to retreive drxdriver version via I2C from SCU RAM */ - driverVersion = (VERSION_MAJOR / 100) % 10; - driverVersion <<= 4; - driverVersion += (VERSION_MAJOR / 10) % 10; - driverVersion <<= 4; - driverVersion += (VERSION_MAJOR % 10); - driverVersion <<= 4; - driverVersion += (VERSION_MINOR % 10); - driverVersion <<= 4; - driverVersion += (VERSION_PATCH / 1000) % 10; - driverVersion <<= 4; - driverVersion += (VERSION_PATCH / 100) % 10; - driverVersion <<= 4; - driverVersion += (VERSION_PATCH / 10) % 10; - driverVersion <<= 4; - driverVersion += (VERSION_PATCH % 10); - WR16(devAddr, SCU_RAM_DRIVER_VER_HI__A, (u16) (driverVersion >> 16)); - WR16(devAddr, SCU_RAM_DRIVER_VER_LO__A, - (u16) (driverVersion & 0xFFFF)); + driver_version = (VERSION_MAJOR / 100) % 10; + driver_version <<= 4; + driver_version += (VERSION_MAJOR / 10) % 10; + driver_version <<= 4; + driver_version += (VERSION_MAJOR % 10); + driver_version <<= 4; + driver_version += (VERSION_MINOR % 10); + driver_version <<= 4; + driver_version += (VERSION_PATCH / 1000) % 10; + driver_version <<= 4; + driver_version += (VERSION_PATCH / 100) % 10; + driver_version <<= 4; + driver_version += (VERSION_PATCH / 10) % 10; + driver_version <<= 4; + driver_version += (VERSION_PATCH % 10); + WR16(dev_addr, SCU_RAM_DRIVER_VER_HI__A, (u16) (driver_version >> 16)); + WR16(dev_addr, SCU_RAM_DRIVER_VER_LO__A, + (u16) (driver_version & 0xFFFF)); /* refresh the audio data structure with default */ - extAttr->audData = DRXJDefaultAudData_g; + ext_attr->aud_data = drxj_default_aud_data_g; return (DRX_STS_OK); rw_error: - commonAttr->isOpened = false; + common_attr->is_opened = false; return (DRX_STS_ERROR); } /*============================================================================*/ /** -* \fn DRXJ_Close() +* \fn drxj_close() * \brief Close the demod instance, power down the device * \return Status_t Return status. * */ -int DRXJ_Close(pDRXDemodInstance_t demod) +int drxj_close(pdrx_demod_instance_t demod) { - struct i2c_device_addr *devAddr = NULL; - pDRXJData_t extAttr = NULL; - pDRXCommonAttr_t commonAttr = NULL; - DRXPowerMode_t powerMode = DRX_POWER_UP; + struct i2c_device_addr *dev_addr = NULL; + pdrxj_data_t ext_attr = NULL; + pdrx_common_attr_t common_attr = NULL; + drx_power_mode_t power_mode = DRX_POWER_UP; - commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; - devAddr = demod->myI2CDevAddr; - extAttr = (pDRXJData_t) demod->myExtAttr; + common_attr = (pdrx_common_attr_t) demod->my_common_attr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* power up */ - CHK_ERROR(CtrlPowerMode(demod, &powerMode)); + CHK_ERROR(ctrl_power_mode(demod, &power_mode)); - if (demod->myTuner != NULL) { + if (demod->my_tuner != NULL) { /* Check if bridge is used */ - if (commonAttr->tunerPortNr == 1) { - bool bridgeClosed = true; - CHK_ERROR(CtrlI2CBridge(demod, &bridgeClosed)); + if (common_attr->tuner_port_nr == 1) { + bool bridge_closed = true; + CHK_ERROR(ctrl_i2c_bridge(demod, &bridge_closed)); } - CHK_ERROR(DRXBSP_TUNER_Close(demod->myTuner)); - if (commonAttr->tunerPortNr == 1) { - bool bridgeClosed = false; - CHK_ERROR(CtrlI2CBridge(demod, &bridgeClosed)); + CHK_ERROR(drxbsp_tuner_close(demod->my_tuner)); + if (common_attr->tuner_port_nr == 1) { + bool bridge_closed = false; + CHK_ERROR(ctrl_i2c_bridge(demod, &bridge_closed)); } }; - WR16(devAddr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); - powerMode = DRX_POWER_DOWN; - CHK_ERROR(CtrlPowerMode(demod, &powerMode)); + WR16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); + power_mode = DRX_POWER_DOWN; + CHK_ERROR(ctrl_power_mode(demod, &power_mode)); return DRX_STS_OK; rw_error: @@ -15776,193 +15776,193 @@ rw_error: /*============================================================================*/ /** -* \fn DRXJ_Ctrl() +* \fn drxj_ctrl() * \brief DRXJ specific control function * \return Status_t Return status. */ int -DRXJ_Ctrl(pDRXDemodInstance_t demod, u32 ctrl, void *ctrlData) +drxj_ctrl(pdrx_demod_instance_t demod, u32 ctrl, void *ctrl_data) { switch (ctrl) { /*======================================================================*/ case DRX_CTRL_SET_CHANNEL: { - return CtrlSetChannel(demod, (pDRXChannel_t) ctrlData); + return ctrl_set_channel(demod, (pdrx_channel_t) ctrl_data); } break; /*======================================================================*/ case DRX_CTRL_GET_CHANNEL: { - return CtrlGetChannel(demod, (pDRXChannel_t) ctrlData); + return ctrl_get_channel(demod, (pdrx_channel_t) ctrl_data); } break; /*======================================================================*/ case DRX_CTRL_SIG_QUALITY: { - return CtrlSigQuality(demod, - (pDRXSigQuality_t) ctrlData); + return ctrl_sig_quality(demod, + (pdrx_sig_quality_t) ctrl_data); } break; /*======================================================================*/ case DRX_CTRL_SIG_STRENGTH: { - return CtrlSigStrength(demod, (u16 *) ctrlData); + return ctrl_sig_strength(demod, (u16 *) ctrl_data); } break; /*======================================================================*/ case DRX_CTRL_CONSTEL: { - return CtrlConstel(demod, (pDRXComplex_t) ctrlData); + return ctrl_constel(demod, (pdrx_complex_t) ctrl_data); } break; /*======================================================================*/ case DRX_CTRL_SET_CFG: { - return CtrlSetCfg(demod, (pDRXCfg_t) ctrlData); + return ctrl_set_cfg(demod, (pdrx_cfg_t) ctrl_data); } break; /*======================================================================*/ case DRX_CTRL_GET_CFG: { - return CtrlGetCfg(demod, (pDRXCfg_t) ctrlData); + return ctrl_get_cfg(demod, (pdrx_cfg_t) ctrl_data); } break; /*======================================================================*/ case DRX_CTRL_I2C_BRIDGE: { - return CtrlI2CBridge(demod, (bool *) ctrlData); + return ctrl_i2c_bridge(demod, (bool *) ctrl_data); } break; /*======================================================================*/ case DRX_CTRL_LOCK_STATUS: { - return CtrlLockStatus(demod, - (pDRXLockStatus_t) ctrlData); + return ctrl_lock_status(demod, + (pdrx_lock_status_t) ctrl_data); } break; /*======================================================================*/ case DRX_CTRL_SET_STANDARD: { - return CtrlSetStandard(demod, - (enum drx_standard *) ctrlData); + return ctrl_set_standard(demod, + (enum drx_standard *) ctrl_data); } break; /*======================================================================*/ case DRX_CTRL_GET_STANDARD: { - return CtrlGetStandard(demod, - (enum drx_standard *) ctrlData); + return ctrl_get_standard(demod, + (enum drx_standard *) ctrl_data); } break; /*======================================================================*/ case DRX_CTRL_POWER_MODE: { - return CtrlPowerMode(demod, (pDRXPowerMode_t) ctrlData); + return ctrl_power_mode(demod, (pdrx_power_mode_t) ctrl_data); } break; /*======================================================================*/ case DRX_CTRL_VERSION: { - return CtrlVersion(demod, - (pDRXVersionList_t *) ctrlData); + return ctrl_version(demod, + (p_drx_version_list_t *) ctrl_data); } break; /*======================================================================*/ case DRX_CTRL_PROBE_DEVICE: { - return CtrlProbeDevice(demod); + return ctrl_probe_device(demod); } break; /*======================================================================*/ case DRX_CTRL_SET_OOB: { - return CtrlSetOOB(demod, (pDRXOOB_t) ctrlData); + return ctrl_set_oob(demod, (p_drxoob_t) ctrl_data); } break; /*======================================================================*/ case DRX_CTRL_GET_OOB: { - return CtrlGetOOB(demod, (pDRXOOBStatus_t) ctrlData); + return ctrl_get_oob(demod, (pdrxoob_status_t) ctrl_data); } break; /*======================================================================*/ case DRX_CTRL_SET_UIO_CFG: { - return CtrlSetUIOCfg(demod, (pDRXUIOCfg_t) ctrlData); + return ctrl_set_uio_cfg(demod, (pdrxuio_cfg_t) ctrl_data); } break; /*======================================================================*/ case DRX_CTRL_GET_UIO_CFG: { - return CtrlGetUIOCfg(demod, (pDRXUIOCfg_t) ctrlData); + return CtrlGetuio_cfg(demod, (pdrxuio_cfg_t) ctrl_data); } break; /*======================================================================*/ case DRX_CTRL_UIO_READ: { - return CtrlUIORead(demod, (pDRXUIOData_t) ctrlData); + return ctrl_uio_read(demod, (pdrxuio_data_t) ctrl_data); } break; /*======================================================================*/ case DRX_CTRL_UIO_WRITE: { - return CtrlUIOWrite(demod, (pDRXUIOData_t) ctrlData); + return ctrl_uio_write(demod, (pdrxuio_data_t) ctrl_data); } break; /*======================================================================*/ case DRX_CTRL_AUD_SET_STANDARD: { - return AUDCtrlSetStandard(demod, - (pDRXAudStandard_t) ctrlData); + return aud_ctrl_set_standard(demod, + (pdrx_aud_standard_t) ctrl_data); } break; /*======================================================================*/ case DRX_CTRL_AUD_GET_STANDARD: { - return AUDCtrlGetStandard(demod, - (pDRXAudStandard_t) ctrlData); + return aud_ctrl_get_standard(demod, + (pdrx_aud_standard_t) ctrl_data); } break; /*======================================================================*/ case DRX_CTRL_AUD_GET_STATUS: { - return AUDCtrlGetStatus(demod, - (pDRXAudStatus_t) ctrlData); + return aud_ctrl_get_status(demod, + (pdrx_aud_status_t) ctrl_data); } break; /*======================================================================*/ case DRX_CTRL_AUD_BEEP: { - return AUDCtrlBeep(demod, (pDRXAudBeep_t) ctrlData); + return aud_ctrl_beep(demod, (pdrx_aud_beep_t) ctrl_data); } break; /*======================================================================*/ case DRX_CTRL_I2C_READWRITE: { - return CtrlI2CWriteRead(demod, - (pDRXI2CData_t) ctrlData); + return ctrl_i2c_write_read(demod, + (pdrxi2c_data_t) ctrl_data); } break; #ifdef DRXJ_SPLIT_UCODE_UPLOAD case DRX_CTRL_LOAD_UCODE: { - return CtrlUCodeUpload(demod, - (pDRXUCodeInfo_t) ctrlData, + return ctrl_u_codeUpload(demod, + (p_drxu_code_info_t) ctrl_data, UCODE_UPLOAD, false); } break; case DRX_CTRL_VERIFY_UCODE: { - return CtrlUCodeUpload(demod, - (pDRXUCodeInfo_t) ctrlData, + return ctrl_u_codeUpload(demod, + (p_drxu_code_info_t) ctrl_data, UCODE_VERIFY, false); } break; #endif /* DRXJ_SPLIT_UCODE_UPLOAD */ case DRX_CTRL_VALIDATE_UCODE: { - return CtrlValidateUCode(demod); + return ctrl_validate_u_code(demod); } break; default: diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.h b/drivers/media/dvb-frontends/drx39xyj/drxj.h index 15b2bb0..54b5c14 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.h +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.h @@ -77,15 +77,15 @@ TYPEDEFS typedef struct { u16 command; /**< Command number */ - u16 parameterLen; + u16 parameter_len; /**< Data length in byte */ - u16 resultLen; + u16 result_len; /**< result length in byte */ u16 *parameter; /**< General purpous param */ u16 *result; /**< General purpous param */ - } DRXJSCUCmd_t, *pDRXJSCUCmd_t; + } drxjscu_cmd_t, *p_drxjscu_cmd_t; /*============================================================================*/ /*============================================================================*/ @@ -137,25 +137,25 @@ TYPEDEFS DRXJ_CFG_OOB_LO_POW, DRXJ_CFG_MAX /* dummy, never to be used */ - } DRXJCfgType_t, *pDRXJCfgType_t; + } drxj_cfg_type_t, *pdrxj_cfg_type_t; /** -* /struct DRXJCfgSmartAntIO_t +* /struct drxj_cfg_smart_ant_io_t * smart antenna i/o. */ - typedef enum DRXJCfgSmartAntIO_t { + typedef enum drxj_cfg_smart_ant_io_t { DRXJ_SMT_ANT_OUTPUT = 0, DRXJ_SMT_ANT_INPUT - } DRXJCfgSmartAntIO_t, *pDRXJCfgSmartAntIO_t; + } drxj_cfg_smart_ant_io_t, *pdrxj_cfg_smart_ant_io_t; /** -* /struct DRXJCfgSmartAnt_t +* /struct drxj_cfg_smart_ant_t * Set smart antenna. */ typedef struct { - DRXJCfgSmartAntIO_t io; - u16 ctrlData; - } DRXJCfgSmartAnt_t, *pDRXJCfgSmartAnt_t; + drxj_cfg_smart_ant_io_t io; + u16 ctrl_data; + } drxj_cfg_smart_ant_t, *p_drxj_cfg_smart_ant_t; /** * /struct DRXJAGCSTATUS_t @@ -164,101 +164,101 @@ TYPEDEFS typedef struct { u16 IFAGC; u16 RFAGC; - u16 DigitalAGC; - } DRXJAgcStatus_t, *pDRXJAgcStatus_t; + u16 digital_agc; + } drxj_agc_status_t, *pdrxj_agc_status_t; /* DRXJ_CFG_AGC_RF, DRXJ_CFG_AGC_IF */ /** -* /struct DRXJAgcCtrlMode_t +* /struct drxj_agc_ctrl_mode_t * Available AGCs modes in the DRXJ. */ typedef enum { DRX_AGC_CTRL_AUTO = 0, DRX_AGC_CTRL_USER, DRX_AGC_CTRL_OFF - } DRXJAgcCtrlMode_t, *pDRXJAgcCtrlMode_t; + } drxj_agc_ctrl_mode_t, *pdrxj_agc_ctrl_mode_t; /** -* /struct DRXJCfgAgc_t +* /struct drxj_cfg_agc_t * Generic interface for all AGCs present on the DRXJ. */ typedef struct { enum drx_standard standard; /* standard for which these settings apply */ - DRXJAgcCtrlMode_t ctrlMode; /* off, user, auto */ - u16 outputLevel; /* range dependent on AGC */ - u16 minOutputLevel; /* range dependent on AGC */ - u16 maxOutputLevel; /* range dependent on AGC */ + drxj_agc_ctrl_mode_t ctrl_mode; /* off, user, auto */ + u16 output_level; /* range dependent on AGC */ + u16 min_output_level; /* range dependent on AGC */ + u16 max_output_level; /* range dependent on AGC */ u16 speed; /* range dependent on AGC */ u16 top; /* rf-agc take over point */ - u16 cutOffCurrent; /* rf-agc is accelerated if output current + u16 cut_off_current; /* rf-agc is accelerated if output current is below cut-off current */ - } DRXJCfgAgc_t, *pDRXJCfgAgc_t; + } drxj_cfg_agc_t, *p_drxj_cfg_agc_t; /* DRXJ_CFG_PRE_SAW */ /** -* /struct DRXJCfgPreSaw_t +* /struct drxj_cfg_pre_saw_t * Interface to configure pre SAW sense. */ typedef struct { enum drx_standard standard; /* standard to which these settings apply */ u16 reference; /* pre SAW reference value, range 0 .. 31 */ - bool usePreSaw; /* true algorithms must use pre SAW sense */ - } DRXJCfgPreSaw_t, *pDRXJCfgPreSaw_t; + bool use_pre_saw; /* true algorithms must use pre SAW sense */ + } drxj_cfg_pre_saw_t, *p_drxj_cfg_pre_saw_t; /* DRXJ_CFG_AFE_GAIN */ /** -* /struct DRXJCfgAfeGain_t +* /struct drxj_cfg_afe_gain_t * Interface to configure gain of AFE (LNA + PGA). */ typedef struct { enum drx_standard standard; /* standard to which these settings apply */ u16 gain; /* gain in 0.1 dB steps, DRXJ range 140 .. 335 */ - } DRXJCfgAfeGain_t, *pDRXJCfgAfeGain_t; + } drxj_cfg_afe_gain_t, *p_drxj_cfg_afe_gain_t; /** -* /struct DRXJRSErrors_t +* /struct DRXJrs_errors_t * Available failure information in DRXJ_FEC_RS. * * Container for errors that are received in the most recently finished measurment period * */ typedef struct { - u16 nrBitErrors; + u16 nr_bit_errors; /**< no of pre RS bit errors */ - u16 nrSymbolErrors; + u16 nr_symbol_errors; /**< no of pre RS symbol errors */ - u16 nrPacketErrors; + u16 nr_packet_errors; /**< no of pre RS packet errors */ - u16 nrFailures; + u16 nr_failures; /**< no of post RS failures to decode */ - u16 nrSncParFailCount; + u16 nr_snc_par_fail_count; /**< no of post RS bit erros */ - } DRXJRSErrors_t, *pDRXJRSErrors_t; + } DRXJrs_errors_t, *p_drxjrs_errors_t; /** -* /struct DRXJCfgVSBMisc_t +* /struct drxj_cfg_vsb_misc_t * symbol error rate */ typedef struct { - u32 symbError; + u32 symb_error; /**< symbol error rate sps */ - } DRXJCfgVSBMisc_t, *pDRXJCfgVSBMisc_t; + } drxj_cfg_vsb_misc_t, *p_drxj_cfg_vsb_misc_t; /** -* /enum DRXJMpegOutputClockRate_t +* /enum drxj_mpeg_output_clock_rate_t * Mpeg output clock rate. * */ typedef enum { DRXJ_MPEG_START_WIDTH_1CLKCYC, DRXJ_MPEG_START_WIDTH_8CLKCYC - } DRXJMpegStartWidth_t, *pDRXJMpegStartWidth_t; + } drxj_mpeg_start_width_t, *pdrxj_mpeg_start_width_t; /** -* /enum DRXJMpegOutputClockRate_t +* /enum drxj_mpeg_output_clock_rate_t * Mpeg output clock rate. * */ @@ -270,7 +270,7 @@ TYPEDEFS DRXJ_MPEGOUTPUT_CLOCK_RATE_30375K, DRXJ_MPEGOUTPUT_CLOCK_RATE_25313K, DRXJ_MPEGOUTPUT_CLOCK_RATE_21696K - } DRXJMpegOutputClockRate_t, *pDRXJMpegOutputClockRate_t; + } drxj_mpeg_output_clock_rate_t, *pdrxj_mpeg_output_clock_rate_t; /** * /struct DRXJCfgMisc_t @@ -279,15 +279,15 @@ TYPEDEFS * set MPEG output clock rate */ typedef struct { - bool disableTEIHandling; /**< if true pass (not change) TEI bit */ - bool bitReverseMpegOutout; /**< if true, parallel: msb on MD0; serial: lsb out first */ - DRXJMpegOutputClockRate_t mpegOutputClockRate; + bool disable_tei_handling; /**< if true pass (not change) TEI bit */ + bool bit_reverse_mpeg_outout; /**< if true, parallel: msb on MD0; serial: lsb out first */ + drxj_mpeg_output_clock_rate_t mpeg_output_clock_rate; /**< set MPEG output clock rate that overwirtes the derived one from symbol rate */ - DRXJMpegStartWidth_t mpegStartWidth; /**< set MPEG output start width */ - } DRXJCfgMpegOutputMisc_t, *pDRXJCfgMpegOutputMisc_t; + drxj_mpeg_start_width_t mpeg_start_width; /**< set MPEG output start width */ + } drxj_cfg_mpeg_output_misc_t, *p_drxj_cfg_mpeg_output_misc_t; /** -* /enum DRXJXtalFreq_t +* /enum drxj_xtal_freq_t * Supported external crystal reference frequency. */ typedef enum { @@ -295,38 +295,38 @@ TYPEDEFS DRXJ_XTAL_FREQ_27MHZ, DRXJ_XTAL_FREQ_20P25MHZ, DRXJ_XTAL_FREQ_4MHZ - } DRXJXtalFreq_t, *pDRXJXtalFreq_t; + } drxj_xtal_freq_t, *pdrxj_xtal_freq_t; /** -* /enum DRXJXtalFreq_t +* /enum drxj_xtal_freq_t * Supported external crystal reference frequency. */ typedef enum { DRXJ_I2C_SPEED_400KBPS, DRXJ_I2C_SPEED_100KBPS - } DRXJI2CSpeed_t, *pDRXJI2CSpeed_t; + } drxji2c_speed_t, *pdrxji2c_speed_t; /** -* /struct DRXJCfgHwCfg_t +* /struct drxj_cfg_hw_cfg_t * Get hw configuration, such as crystal reference frequency, I2C speed, etc... */ typedef struct { - DRXJXtalFreq_t xtalFreq; + drxj_xtal_freq_t xtal_freq; /**< crystal reference frequency */ - DRXJI2CSpeed_t i2cSpeed; + drxji2c_speed_t i2c_speed; /**< 100 or 400 kbps */ - } DRXJCfgHwCfg_t, *pDRXJCfgHwCfg_t; + } drxj_cfg_hw_cfg_t, *p_drxj_cfg_hw_cfg_t; /* * DRXJ_CFG_ATV_MISC */ typedef struct { - s16 peakFilter; /* -8 .. 15 */ - u16 noiseFilter; /* 0 .. 15 */ - } DRXJCfgAtvMisc_t, *pDRXJCfgAtvMisc_t; + s16 peak_filter; /* -8 .. 15 */ + u16 noise_filter; /* 0 .. 15 */ + } drxj_cfg_atv_misc_t, *p_drxj_cfg_atv_misc_t; /* - * DRXJCfgOOBMisc_t + * drxj_cfg_oob_misc_t */ #define DRXJ_OOB_STATE_RESET 0x0 #define DRXJ_OOB_STATE_AGN_HUNT 0x1 @@ -340,15 +340,15 @@ TYPEDEFS #define DRXJ_OOB_STATE_SYNC 0x40 typedef struct { - DRXJAgcStatus_t agc; - bool eqLock; - bool symTimingLock; - bool phaseLock; - bool freqLock; - bool digGainLock; - bool anaGainLock; + drxj_agc_status_t agc; + bool eq_lock; + bool sym_timing_lock; + bool phase_lock; + bool freq_lock; + bool dig_gain_lock; + bool ana_gain_lock; u8 state; - } DRXJCfgOOBMisc_t, *pDRXJCfgOOBMisc_t; + } drxj_cfg_oob_misc_t, *p_drxj_cfg_oob_misc_t; /* * Index of in array of coef @@ -359,7 +359,7 @@ TYPEDEFS DRXJ_OOB_LO_POW_MINUS10DB, DRXJ_OOB_LO_POW_MINUS15DB, DRXJ_OOB_LO_POW_MAX - } DRXJCfgOobLoPower_t, *pDRXJCfgOobLoPower_t; + } drxj_cfg_oob_lo_power_t, *p_drxj_cfg_oob_lo_power_t; /* * DRXJ_CFG_ATV_EQU_COEF @@ -369,7 +369,7 @@ TYPEDEFS s16 coef1; /* -256 .. 255 */ s16 coef2; /* -256 .. 255 */ s16 coef3; /* -256 .. 255 */ - } DRXJCfgAtvEquCoef_t, *pDRXJCfgAtvEquCoef_t; + } drxj_cfg_atv_equ_coef_t, *p_drxj_cfg_atv_equ_coef_t; /* * Index of in array of coef @@ -383,7 +383,7 @@ TYPEDEFS DRXJ_COEF_IDX_DK, DRXJ_COEF_IDX_I, DRXJ_COEF_IDX_MAX - } DRXJCoefArrayIndex_t, *pDRXJCoefArrayIndex_t; + } drxj_coef_array_index_t, *pdrxj_coef_array_index_t; /* * DRXJ_CFG_ATV_OUTPUT @@ -399,32 +399,32 @@ TYPEDEFS DRXJ_SIF_ATTENUATION_3DB, DRXJ_SIF_ATTENUATION_6DB, DRXJ_SIF_ATTENUATION_9DB - } DRXJSIFAttenuation_t, *pDRXJSIFAttenuation_t; + } drxjsif_attenuation_t, *pdrxjsif_attenuation_t; /** -* /struct DRXJCfgAtvOutput_t +* /struct drxj_cfg_atv_output_t * SIF attenuation setting. * */ typedef struct { - bool enableCVBSOutput; /* true= enabled */ - bool enableSIFOutput; /* true= enabled */ - DRXJSIFAttenuation_t sifAttenuation; - } DRXJCfgAtvOutput_t, *pDRXJCfgAtvOutput_t; + bool enable_cvbs_output; /* true= enabled */ + bool enable_sif_output; /* true= enabled */ + drxjsif_attenuation_t sif_attenuation; + } drxj_cfg_atv_output_t, *p_drxj_cfg_atv_output_t; /* DRXJ_CFG_ATV_AGC_STATUS (get only) */ /* TODO : AFE interface not yet finished, subject to change */ typedef struct { - u16 rfAgcGain; /* 0 .. 877 uA */ - u16 ifAgcGain; /* 0 .. 877 uA */ - s16 videoAgcGain; /* -75 .. 1972 in 0.1 dB steps */ - s16 audioAgcGain; /* -4 .. 1020 in 0.1 dB steps */ - u16 rfAgcLoopGain; /* 0 .. 7 */ - u16 ifAgcLoopGain; /* 0 .. 7 */ - u16 videoAgcLoopGain; /* 0 .. 7 */ - } DRXJCfgAtvAgcStatus_t, *pDRXJCfgAtvAgcStatus_t; + u16 rf_agc_gain; /* 0 .. 877 uA */ + u16 if_agc_gain; /* 0 .. 877 uA */ + s16 video_agc_gain; /* -75 .. 1972 in 0.1 dB steps */ + s16 audio_agc_gain; /* -4 .. 1020 in 0.1 dB steps */ + u16 rf_agc_loop_gain; /* 0 .. 7 */ + u16 if_agc_loop_gain; /* 0 .. 7 */ + u16 video_agc_loop_gain; /* 0 .. 7 */ + } drxj_cfg_atv_agc_status_t, *p_drxj_cfg_atv_agc_status_t; /*============================================================================*/ /*============================================================================*/ @@ -439,142 +439,142 @@ TYPEDEFS /*========================================*/ /** -* /struct DRXJData_t +* /struct drxj_data_t * DRXJ specific attributes. * * Global data container for DRXJ specific data. * */ typedef struct { - /* device capabilties (determined during DRX_Open()) */ - bool hasLNA; /**< true if LNA (aka PGA) present */ - bool hasOOB; /**< true if OOB supported */ - bool hasNTSC; /**< true if NTSC supported */ - bool hasBTSC; /**< true if BTSC supported */ - bool hasSMATX; /**< true if mat_tx is available */ - bool hasSMARX; /**< true if mat_rx is available */ - bool hasGPIO; /**< true if GPIO is available */ - bool hasIRQN; /**< true if IRQN is available */ + /* device capabilties (determined during drx_open()) */ + bool has_lna; /**< true if LNA (aka PGA) present */ + bool has_oob; /**< true if OOB supported */ + bool has_ntsc; /**< true if NTSC supported */ + bool has_btsc; /**< true if BTSC supported */ + bool has_smatx; /**< true if mat_tx is available */ + bool has_smarx; /**< true if mat_rx is available */ + bool has_gpio; /**< true if GPIO is available */ + bool has_irqn; /**< true if IRQN is available */ /* A1/A2/A... */ u8 mfx; /**< metal fix */ /* tuner settings */ - bool mirrorFreqSpectOOB;/**< tuner inversion (true = tuner mirrors the signal */ + bool mirror_freq_spectOOB;/**< tuner inversion (true = tuner mirrors the signal */ /* standard/channel settings */ enum drx_standard standard; /**< current standard information */ enum drx_modulation constellation; /**< current constellation */ s32 frequency; /**< center signal frequency in KHz */ - enum drx_bandwidth currBandwidth; + enum drx_bandwidth curr_bandwidth; /**< current channel bandwidth */ enum drx_mirror mirror; /**< current channel mirror */ /* signal quality information */ - u32 fecBitsDesired; /**< BER accounting period */ - u16 fecVdPlen; /**< no of trellis symbols: VD SER measurement period */ - u16 qamVdPrescale; /**< Viterbi Measurement Prescale */ - u16 qamVdPeriod; /**< Viterbi Measurement period */ - u16 fecRsPlen; /**< defines RS BER measurement period */ - u16 fecRsPrescale; /**< ReedSolomon Measurement Prescale */ - u16 fecRsPeriod; /**< ReedSolomon Measurement period */ - bool resetPktErrAcc; /**< Set a flag to reset accumulated packet error */ - u16 pktErrAccStart; /**< Set a flag to reset accumulated packet error */ + u32 fec_bits_desired; /**< BER accounting period */ + u16 fec_vd_plen; /**< no of trellis symbols: VD SER measurement period */ + u16 qam_vd_prescale; /**< Viterbi Measurement Prescale */ + u16 qam_vd_period; /**< Viterbi Measurement period */ + u16 fec_rs_plen; /**< defines RS BER measurement period */ + u16 fec_rs_prescale; /**< ReedSolomon Measurement Prescale */ + u16 fec_rs_period; /**< ReedSolomon Measurement period */ + bool reset_pkt_err_acc; /**< Set a flag to reset accumulated packet error */ + u16 pkt_errAccStart; /**< Set a flag to reset accumulated packet error */ /* HI configuration */ - u16 HICfgTimingDiv; /**< HI Configure() parameter 2 */ - u16 HICfgBridgeDelay; /**< HI Configure() parameter 3 */ - u16 HICfgWakeUpKey; /**< HI Configure() parameter 4 */ - u16 HICfgCtrl; /**< HI Configure() parameter 5 */ - u16 HICfgTransmit; /**< HI Configure() parameter 6 */ + u16 hi_cfg_timing_div; /**< HI Configure() parameter 2 */ + u16 hi_cfg_bridge_delay; /**< HI Configure() parameter 3 */ + u16 hi_cfg_wake_up_key; /**< HI Configure() parameter 4 */ + u16 hi_cfg_ctrl; /**< HI Configure() parameter 5 */ + u16 hi_cfg_transmit; /**< HI Configure() parameter 6 */ /* UIO configuartion */ - DRXUIOMode_t uioSmaRxMode;/**< current mode of SmaRx pin */ - DRXUIOMode_t uioSmaTxMode;/**< current mode of SmaTx pin */ - DRXUIOMode_t uioGPIOMode; /**< current mode of ASEL pin */ - DRXUIOMode_t uioIRQNMode; /**< current mode of IRQN pin */ + drxuio_mode_t uio_sma_rx_mode;/**< current mode of SmaRx pin */ + drxuio_mode_t uio_sma_tx_mode;/**< current mode of SmaTx pin */ + drxuio_mode_t uio_gpio_mode; /**< current mode of ASEL pin */ + drxuio_mode_t uio_irqn_mode; /**< current mode of IRQN pin */ /* IQM fs frequecy shift and inversion */ - u32 iqmFsRateOfs; /**< frequency shifter setting after setchannel */ - bool posImage; /**< Ture: positive image */ + u32 iqm_fs_rate_ofs; /**< frequency shifter setting after setchannel */ + bool pos_image; /**< Ture: positive image */ /* IQM RC frequecy shift */ - u32 iqmRcRateOfs; /**< frequency shifter setting after setchannel */ + u32 iqm_rc_rate_ofs; /**< frequency shifter setting after setchannel */ /* ATV configuartion */ - u32 atvCfgChangedFlags; /**< flag: flags cfg changes */ - s16 atvTopEqu0[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU0__A */ - s16 atvTopEqu1[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU1__A */ - s16 atvTopEqu2[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU2__A */ - s16 atvTopEqu3[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU3__A */ - bool phaseCorrectionBypass;/**< flag: true=bypass */ - s16 atvTopVidPeak; /**< shadow of ATV_TOP_VID_PEAK__A */ - u16 atvTopNoiseTh; /**< shadow of ATV_TOP_NOISE_TH__A */ - bool enableCVBSOutput; /**< flag CVBS ouput enable */ - bool enableSIFOutput; /**< flag SIF ouput enable */ - DRXJSIFAttenuation_t sifAttenuation; + u32 atv_cfg_changed_flags; /**< flag: flags cfg changes */ + s16 atv_top_equ0[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU0__A */ + s16 atv_top_equ1[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU1__A */ + s16 atv_top_equ2[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU2__A */ + s16 atv_top_equ3[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU3__A */ + bool phase_correction_bypass;/**< flag: true=bypass */ + s16 atv_top_vid_peak; /**< shadow of ATV_TOP_VID_PEAK__A */ + u16 atv_top_noise_th; /**< shadow of ATV_TOP_NOISE_TH__A */ + bool enable_cvbs_output; /**< flag CVBS ouput enable */ + bool enable_sif_output; /**< flag SIF ouput enable */ + drxjsif_attenuation_t sif_attenuation; /**< current SIF att setting */ /* Agc configuration for QAM and VSB */ - DRXJCfgAgc_t qamRfAgcCfg; /**< qam RF AGC config */ - DRXJCfgAgc_t qamIfAgcCfg; /**< qam IF AGC config */ - DRXJCfgAgc_t vsbRfAgcCfg; /**< vsb RF AGC config */ - DRXJCfgAgc_t vsbIfAgcCfg; /**< vsb IF AGC config */ + drxj_cfg_agc_t qam_rf_agc_cfg; /**< qam RF AGC config */ + drxj_cfg_agc_t qam_if_agc_cfg; /**< qam IF AGC config */ + drxj_cfg_agc_t vsb_rf_agc_cfg; /**< vsb RF AGC config */ + drxj_cfg_agc_t vsb_if_agc_cfg; /**< vsb IF AGC config */ /* PGA gain configuration for QAM and VSB */ - u16 qamPgaCfg; /**< qam PGA config */ - u16 vsbPgaCfg; /**< vsb PGA config */ + u16 qam_pga_cfg; /**< qam PGA config */ + u16 vsb_pga_cfg; /**< vsb PGA config */ /* Pre SAW configuration for QAM and VSB */ - DRXJCfgPreSaw_t qamPreSawCfg; + drxj_cfg_pre_saw_t qam_pre_saw_cfg; /**< qam pre SAW config */ - DRXJCfgPreSaw_t vsbPreSawCfg; + drxj_cfg_pre_saw_t vsb_pre_saw_cfg; /**< qam pre SAW config */ /* Version information */ - char vText[2][12]; /**< allocated text versions */ - DRXVersion_t vVersion[2]; /**< allocated versions structs */ - DRXVersionList_t vListElements[2]; + char v_text[2][12]; /**< allocated text versions */ + drx_version_t v_version[2]; /**< allocated versions structs */ + drx_version_list_t v_list_elements[2]; /**< allocated version list */ /* smart antenna configuration */ - bool smartAntInverted; + bool smart_ant_inverted; /* Tracking filter setting for OOB */ - u16 oobTrkFilterCfg[8]; - bool oobPowerOn; + u16 oob_trk_filter_cfg[8]; + bool oob_power_on; /* MPEG static bitrate setting */ - u32 mpegTsStaticBitrate; /**< bitrate static MPEG output */ - bool disableTEIhandling; /**< MPEG TS TEI handling */ - bool bitReverseMpegOutout;/**< MPEG output bit order */ - DRXJMpegOutputClockRate_t mpegOutputClockRate; + u32 mpeg_ts_static_bitrate; /**< bitrate static MPEG output */ + bool disable_te_ihandling; /**< MPEG TS TEI handling */ + bool bit_reverse_mpeg_outout;/**< MPEG output bit order */ + drxj_mpeg_output_clock_rate_t mpeg_output_clock_rate; /**< MPEG output clock rate */ - DRXJMpegStartWidth_t mpegStartWidth; + drxj_mpeg_start_width_t mpeg_start_width; /**< MPEG Start width */ /* Pre SAW & Agc configuration for ATV */ - DRXJCfgPreSaw_t atvPreSawCfg; + drxj_cfg_pre_saw_t atv_pre_saw_cfg; /**< atv pre SAW config */ - DRXJCfgAgc_t atvRfAgcCfg; /**< atv RF AGC config */ - DRXJCfgAgc_t atvIfAgcCfg; /**< atv IF AGC config */ - u16 atvPgaCfg; /**< atv pga config */ + drxj_cfg_agc_t atv_rf_agc_cfg; /**< atv RF AGC config */ + drxj_cfg_agc_t atv_if_agc_cfg; /**< atv IF AGC config */ + u16 atv_pga_cfg; /**< atv pga config */ - u32 currSymbolRate; + u32 curr_symbol_rate; /* pin-safe mode */ - bool pdrSafeMode; /**< PDR safe mode activated */ - u16 pdrSafeRestoreValGpio; - u16 pdrSafeRestoreValVSync; - u16 pdrSafeRestoreValSmaRx; - u16 pdrSafeRestoreValSmaTx; + bool pdr_safe_mode; /**< PDR safe mode activated */ + u16 pdr_safe_restore_val_gpio; + u16 pdr_safe_restore_val_v_sync; + u16 pdr_safe_restore_val_sma_rx; + u16 pdr_safe_restore_val_sma_tx; /* OOB pre-saw value */ - u16 oobPreSaw; - DRXJCfgOobLoPower_t oobLoPow; + u16 oob_pre_saw; + drxj_cfg_oob_lo_power_t oob_lo_pow; - DRXAudData_t audData; + drx_aud_data_t aud_data; /**< audio storage */ - } DRXJData_t, *pDRXJData_t; + } drxj_data_t, *pdrxj_data_t; /*------------------------------------------------------------------------- Access MACROS @@ -591,7 +591,7 @@ Access MACROS */ #define DRXJ_ATTR_BTSC_DETECT(d) \ - (((pDRXJData_t)(d)->myExtAttr)->audData.btscDetect) + (((pdrxj_data_t)(d)->my_ext_attr)->aud_data.btsc_detect) /** * \brief Actual access macros @@ -723,20 +723,20 @@ STRUCTS Exported FUNCTIONS -------------------------------------------------------------------------*/ - extern int DRXJ_Open(pDRXDemodInstance_t demod); - extern int DRXJ_Close(pDRXDemodInstance_t demod); - extern int DRXJ_Ctrl(pDRXDemodInstance_t demod, - u32 ctrl, void *ctrlData); + extern int drxj_open(pdrx_demod_instance_t demod); + extern int drxj_close(pdrx_demod_instance_t demod); + extern int drxj_ctrl(pdrx_demod_instance_t demod, + u32 ctrl, void *ctrl_data); /*------------------------------------------------------------------------- Exported GLOBAL VARIABLES -------------------------------------------------------------------------*/ - extern DRXAccessFunc_t drxDapDRXJFunct_g; - extern DRXDemodFunc_t DRXJFunctions_g; - extern DRXJData_t DRXJData_g; - extern struct i2c_device_addr DRXJDefaultAddr_g; - extern DRXCommonAttr_t DRXJDefaultCommAttr_g; - extern DRXDemodInstance_t DRXJDefaultDemod_g; + extern drx_access_func_t drx_dap_drxj_funct_g; + extern drx_demod_func_t drxj_functions_g; + extern drxj_data_t drxj_data_g; + extern struct i2c_device_addr drxj_default_addr_g; + extern drx_common_attr_t drxj_default_comm_attr_g; + extern drx_demod_instance_t drxj_default_demod_g; /*------------------------------------------------------------------------- THE END diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj_map.h b/drivers/media/dvb-frontends/drx39xyj/drxj_map.h index 3ffc7b0..af42754 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj_map.h +++ b/drivers/media/dvb-frontends/drx39xyj/drxj_map.h @@ -53,8 +53,8 @@ extern "C" { #ifdef _REGISTERTABLE_ #include - extern RegisterTable_t drxj_map[]; - extern RegisterTableInfo_t drxj_map_info[]; + extern register_table_t drxj_map[]; + extern register_table_info_t drxj_map_info[]; #endif #define ATV_COMM_EXEC__A 0xC00000 -- cgit v1.1 From 22892268cd65d50b5d2faa2232fc39ebd98b7142 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Thu, 16 Jan 2014 11:28:52 -0300 Subject: [media] drx-j: do more CodingStyle fixes This time, use checkpatch --strict --fix. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drx39xxj.c | 2 +- drivers/media/dvb-frontends/drx39xyj/drx39xxj.h | 2 +- .../media/dvb-frontends/drx39xyj/drx39xxj_dummy.c | 2 +- .../media/dvb-frontends/drx39xyj/drx_dap_fasi.c | 32 +-- .../media/dvb-frontends/drx39xyj/drx_dap_fasi.h | 4 +- drivers/media/dvb-frontends/drx39xyj/drx_driver.c | 20 +- drivers/media/dvb-frontends/drx39xyj/drx_driver.h | 32 +-- drivers/media/dvb-frontends/drx39xyj/drxj.c | 270 ++++++++++----------- drivers/media/dvb-frontends/drx39xyj/drxj.h | 6 +- drivers/media/dvb-frontends/drx39xyj/drxj_mc.h | 2 +- drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsb.h | 2 +- .../media/dvb-frontends/drx39xyj/drxj_mc_vsbqam.h | 2 +- 12 files changed, 188 insertions(+), 188 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c index d80ef7e..d32bab0 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c @@ -376,7 +376,7 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) demod->my_ext_attr = demod_ext_attr; memcpy(demod->my_ext_attr, &drxj_data_g, sizeof(drxj_data_t)); - ((drxj_data_t *) demod->my_ext_attr)->uio_sma_tx_mode = + ((drxj_data_t *)demod->my_ext_attr)->uio_sma_tx_mode = DRX_UIO_MODE_READWRITE; demod->my_tuner = NULL; diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h index 30657c8..622172d 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h @@ -35,6 +35,6 @@ struct drx39xxj_state { unsigned int i2c_gate_open:1; }; -extern struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c); +struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c); #endif /* DVB_DUMMY_FE_H */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c b/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c index 61e04c6..2cedf7c 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c @@ -30,7 +30,7 @@ int drxbsp_tuner_set_frequency(struct tuner_instance *tuner, int drxbsp_tuner_get_frequency(struct tuner_instance *tuner, - u32 mode, + u32 mode, s32 *r_ffrequency, s32 *i_ffrequency) { diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c index 71805b4..9e9556b 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c @@ -252,8 +252,8 @@ static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr, addr &= ~DRXDAP_FASI_FLAGS; addr |= flags; -#if (( DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && \ - (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1) ) +#if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && \ + (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1)) /* short format address preferred but long format otherwise */ if (DRXDAP_FASI_LONG_FORMAT(addr)) { #endif @@ -263,8 +263,8 @@ static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr, buf[bufx++] = (u8) ((addr >> 24) & 0xFF); buf[bufx++] = (u8) ((addr >> 7) & 0xFF); #endif -#if (( DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && \ - (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1) ) +#if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && \ + (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1)) } else { #endif #if (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1) @@ -273,8 +273,8 @@ static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr, (u8) (((addr >> 16) & 0x0F) | ((addr >> 18) & 0xF0)); #endif -#if (( DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && \ - (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1) ) +#if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && \ + (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1)) } #endif @@ -478,8 +478,8 @@ static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr, /* Buffer device address */ addr &= ~DRXDAP_FASI_FLAGS; addr |= flags; -#if (( (DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && \ - ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1) ) +#if (((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && \ + ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1)) /* short format address preferred but long format otherwise */ if (DRXDAP_FASI_LONG_FORMAT(addr)) { #endif @@ -489,8 +489,8 @@ static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr, buf[bufx++] = (u8) ((addr >> 24) & 0xFF); buf[bufx++] = (u8) ((addr >> 7) & 0xFF); #endif -#if (( (DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && \ - ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1) ) +#if (((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && \ + ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1)) } else { #endif #if ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1) @@ -499,8 +499,8 @@ static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr, (u8) (((addr >> 16) & 0x0F) | ((addr >> 18) & 0xF0)); #endif -#if (( (DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && \ - ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1) ) +#if (((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && \ + ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1)) } #endif @@ -526,8 +526,8 @@ static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr, st = drxbsp_i2c_write_read(dev_addr, (u16) (bufx), buf, - (struct i2c_device_addr *) (NULL), - 0, (u8 *) (NULL)); + (struct i2c_device_addr *)(NULL), + 0, (u8 *)(NULL)); if ((st != DRX_STS_OK) && (first_err == DRX_STS_OK)) { /* at the end, return the first error encountered */ @@ -543,8 +543,8 @@ static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr, st = drxbsp_i2c_write_read(dev_addr, (u16) (bufx + todo), buf, - (struct i2c_device_addr *) (NULL), - 0, (u8 *) (NULL)); + (struct i2c_device_addr *)(NULL), + 0, (u8 *)(NULL)); if ((st != DRX_STS_OK) && (first_err == DRX_STS_OK)) { /* at the end, return the first error encountered */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.h b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.h index 4152d62..02b2c30 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.h @@ -93,8 +93,8 @@ #endif /* check */ -#if (( DRXDAPFASI_LONG_ADDR_ALLOWED == 0) && \ - (DRXDAPFASI_SHORT_ADDR_ALLOWED == 0) ) +#if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 0) && \ + (DRXDAPFASI_SHORT_ADDR_ALLOWED == 0)) #error At least one of short- or long-addressing format must be allowed. *; /* illegal statement to force compiler error */ #endif diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c index 847e17a..e8d1a26 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c @@ -99,7 +99,7 @@ DEFINES /*=== MACROS =================================================================*/ /*============================================================================*/ -#define DRX_ISPOWERDOWNMODE(mode) ( ( mode == DRX_POWER_MODE_9 ) || \ +#define DRX_ISPOWERDOWNMODE(mode) (( mode == DRX_POWER_MODE_9) || \ (mode == DRX_POWER_MODE_10) || \ (mode == DRX_POWER_MODE_11) || \ (mode == DRX_POWER_MODE_12) || \ @@ -107,7 +107,7 @@ DEFINES (mode == DRX_POWER_MODE_14) || \ (mode == DRX_POWER_MODE_15) || \ (mode == DRX_POWER_MODE_16) || \ - (mode == DRX_POWER_DOWN) ) + (mode == DRX_POWER_DOWN)) /*------------------------------------------------------------------------------ GLOBAL VARIABLES @@ -147,7 +147,7 @@ FUNCTIONS /* Prototype of default scanning function */ static int scan_function_default(void *scan_context, - drx_scan_command_t scan_command, + drx_scan_command_t scan_command, pdrx_channel_t scan_channel, bool *get_next_channel); /** @@ -355,7 +355,7 @@ scan_prepare_next_scan(pdrx_demod_instance_t demod, s32 skip) */ static int scan_function_default(void *scan_context, - drx_scan_command_t scan_command, + drx_scan_command_t scan_command, pdrx_channel_t scan_channel, bool *get_next_channel) { pdrx_demod_instance_t demod = NULL; @@ -604,7 +604,7 @@ static int ctrl_scan_stop(pdrx_demod_instance_t demod) static int ctrl_scan_next(pdrx_demod_instance_t demod, u16 *scan_progress) { pdrx_common_attr_t common_attr = (pdrx_common_attr_t) (NULL); - bool *scan_ready = (bool *) (NULL); + bool *scan_ready = (bool *)(NULL); u16 max_progress = DRX_SCAN_MAX_PROGRESS; u32 num_tries = 0; u32 i = 0; @@ -983,14 +983,14 @@ static u16 u_code_compute_crc(u8 *block_data, u16 nr_words) */ static int ctrl_u_code(pdrx_demod_instance_t demod, - p_drxu_code_info_t mc_info, drxu_code_action_t action) + p_drxu_code_info_t mc_info, drxu_code_action_t action) { int rc; u16 i = 0; u16 mc_nr_of_blks = 0; u16 mc_magic_word = 0; - u8 *mc_data = (u8 *) (NULL); - struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) (NULL); + u8 *mc_data = (u8 *)(NULL); + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); dev_addr = demod->my_i2c_dev_addr; @@ -1420,7 +1420,7 @@ drx_ctrl(pdrx_demod_instance_t demod, u32 ctrl, void *ctrl_data) /*======================================================================*/ case DRX_CTRL_VERSION: - return ctrl_version(demod, (p_drx_version_list_t *) ctrl_data); + return ctrl_version(demod, (p_drx_version_list_t *)ctrl_data); break; /*======================================================================*/ @@ -1463,7 +1463,7 @@ drx_ctrl(pdrx_demod_instance_t demod, u32 ctrl, void *ctrl_data) /*===================================================================*/ case DRX_CTRL_SCAN_NEXT: { - return ctrl_scan_next(demod, (u16 *) ctrl_data); + return ctrl_scan_next(demod, (u16 *)ctrl_data); } break; diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h index f4a0411..ca07a6c 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h @@ -493,23 +493,23 @@ MACROS /** * \brief Macro to sign extend signed 9 bit value to signed 16 bit value */ -#define DRX_S9TOS16(x) ((((u16)x)&0x100)?((s16)((u16)(x)|0xFF00)):(x)) +#define DRX_S9TOS16(x) ((((u16)x)&0x100) ? ((s16)((u16)(x)|0xFF00)) : (x)) /** * \brief Macro to sign extend signed 9 bit value to signed 16 bit value */ -#define DRX_S24TODRXFREQ(x) (( ( (u32) x) & 0x00800000UL ) ? \ +#define DRX_S24TODRXFREQ(x) ((( (u32) x) & 0x00800000UL) ? \ ((s32) \ - (( (u32) x) | 0xFF000000 ) ) : \ - ((s32) x) ) + (((u32) x) | 0xFF000000) ) : \ + ((s32) x)) /** * \brief Macro to convert 16 bit register value to a s32 */ -#define DRX_U16TODRXFREQ(x) (( x & 0x8000) ? \ +#define DRX_U16TODRXFREQ(x) ((x & 0x8000) ? \ ((s32) \ - (( (u32) x) | 0xFFFF0000 ) ) : \ - ((s32) x) ) + (((u32) x) | 0xFFFF0000) ) : \ + ((s32) x)) /*------------------------------------------------------------------------- ENUM @@ -2868,14 +2868,14 @@ Access macros #define DRX_GET_PRESET(d, x) \ DRX_ACCESSMACRO_GET((d), (x), DRX_XS_CFG_PRESET, char*, "ERROR") -#define DRX_SET_AUD_BTSC_DETECT(d, x) DRX_ACCESSMACRO_SET( (d), (x), \ +#define DRX_SET_AUD_BTSC_DETECT(d, x) DRX_ACCESSMACRO_SET((d), (x), \ DRX_XS_CFG_AUD_BTSC_DETECT, drx_aud_btsc_detect_t) -#define DRX_GET_AUD_BTSC_DETECT(d, x) DRX_ACCESSMACRO_GET( (d), (x), \ +#define DRX_GET_AUD_BTSC_DETECT(d, x) DRX_ACCESSMACRO_GET((d), (x), \ DRX_XS_CFG_AUD_BTSC_DETECT, drx_aud_btsc_detect_t, DRX_UNKNOWN) -#define DRX_SET_QAM_LOCKRANGE(d, x) DRX_ACCESSMACRO_SET( (d), (x), \ +#define DRX_SET_QAM_LOCKRANGE(d, x) DRX_ACCESSMACRO_SET((d), (x), \ DRX_XS_CFG_QAM_LOCKRANGE, drx_qam_lock_range_t) -#define DRX_GET_QAM_LOCKRANGE(d, x) DRX_ACCESSMACRO_GET( (d), (x), \ +#define DRX_GET_QAM_LOCKRANGE(d, x) DRX_ACCESSMACRO_GET((d), (x), \ DRX_XS_CFG_QAM_LOCKRANGE, drx_qam_lock_range_t, DRX_UNKNOWN) /** @@ -2883,20 +2883,20 @@ Access macros * \retval true std is an ATV standard * \retval false std is an ATV standard */ -#define DRX_ISATVSTD(std) ( ( (std) == DRX_STANDARD_PAL_SECAM_BG ) || \ +#define DRX_ISATVSTD(std) (( (std) == DRX_STANDARD_PAL_SECAM_BG) || \ ((std) == DRX_STANDARD_PAL_SECAM_DK) || \ ((std) == DRX_STANDARD_PAL_SECAM_I) || \ ((std) == DRX_STANDARD_PAL_SECAM_L) || \ ((std) == DRX_STANDARD_PAL_SECAM_LP) || \ ((std) == DRX_STANDARD_NTSC) || \ - ((std) == DRX_STANDARD_FM) ) + ((std) == DRX_STANDARD_FM)) /** * \brief Macro to check if std is an QAM standard * \retval true std is an QAM standards * \retval false std is an QAM standards */ -#define DRX_ISQAMSTD(std) ( ( (std) == DRX_STANDARD_ITU_A ) || \ +#define DRX_ISQAMSTD(std) (( (std) == DRX_STANDARD_ITU_A) || \ ((std) == DRX_STANDARD_ITU_B) || \ ((std) == DRX_STANDARD_ITU_C) || \ ((std) == DRX_STANDARD_ITU_D)) @@ -2906,14 +2906,14 @@ Access macros * \retval true std is VSB standard * \retval false std is not VSB standard */ -#define DRX_ISVSBSTD(std) ( (std) == DRX_STANDARD_8VSB ) +#define DRX_ISVSBSTD(std) ((std) == DRX_STANDARD_8VSB) /** * \brief Macro to check if std is DVBT standard * \retval true std is DVBT standard * \retval false std is not DVBT standard */ -#define DRX_ISDVBTSTD(std) ( (std) == DRX_STANDARD_DVBT ) +#define DRX_ISDVBTSTD(std) ((std) == DRX_STANDARD_DVBT) /*------------------------------------------------------------------------- Exported FUNCTIONS diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index 3a63520..bd7ad18 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -509,34 +509,34 @@ DEFINES } while (0) #define WR16(dev, addr, val) \ - CHK_ERROR(DRXJ_DAP.write_reg16func( (dev), (addr), (val), 0) ) + CHK_ERROR(DRXJ_DAP.write_reg16func((dev), (addr), (val), 0)) #define RR16(dev, addr, val) \ - CHK_ERROR(DRXJ_DAP.read_reg16func( (dev), (addr), (val), 0) ) + CHK_ERROR(DRXJ_DAP.read_reg16func((dev), (addr), (val), 0)) #define WR32(dev, addr, val) \ - CHK_ERROR(DRXJ_DAP.write_reg32func( (dev), (addr), (val), 0) ) + CHK_ERROR(DRXJ_DAP.write_reg32func((dev), (addr), (val), 0)) #define RR32(dev, addr, val) \ - CHK_ERROR(DRXJ_DAP.read_reg32func( (dev), (addr), (val), 0) ) + CHK_ERROR(DRXJ_DAP.read_reg32func((dev), (addr), (val), 0)) #define WRB(dev, addr, len, block) \ - CHK_ERROR(DRXJ_DAP.write_block_func( (dev), (addr), (len), (block), 0) ) + CHK_ERROR(DRXJ_DAP.write_block_func((dev), (addr), (len), (block), 0)) #define RRB(dev, addr, len, block) \ - CHK_ERROR(DRXJ_DAP.read_block_func( (dev), (addr), (len), (block), 0) ) + CHK_ERROR(DRXJ_DAP.read_block_func((dev), (addr), (len), (block), 0)) #define BCWR16(dev, addr, val) \ - CHK_ERROR(DRXJ_DAP.write_reg16func( (dev), (addr), (val), DRXDAP_FASI_BROADCAST) ) + CHK_ERROR(DRXJ_DAP.write_reg16func((dev), (addr), (val), DRXDAP_FASI_BROADCAST)) #define ARR32(dev, addr, val) \ - CHK_ERROR(drxj_dap_atomic_read_reg32( (dev), (addr), (val), 0) ) + CHK_ERROR(drxj_dap_atomic_read_reg32((dev), (addr), (val), 0)) #define SARR16(dev, addr, val) \ - CHK_ERROR(drxj_dap_scu_atomic_read_reg16( (dev), (addr), (val), 0) ) + CHK_ERROR(drxj_dap_scu_atomic_read_reg16((dev), (addr), (val), 0)) #define SAWR16(dev, addr, val) \ - CHK_ERROR(drxj_dap_scu_atomic_write_reg16( (dev), (addr), (val), 0) ) + CHK_ERROR(drxj_dap_scu_atomic_write_reg16((dev), (addr), (val), 0)) /** * This macro is used to create byte arrays for block writes. @@ -570,15 +570,15 @@ DEFINES /*=== STANDARD RELATED MACROS ================================================*/ /*============================================================================*/ -#define DRXJ_ISATVSTD(std) ( ( std == DRX_STANDARD_PAL_SECAM_BG ) || \ +#define DRXJ_ISATVSTD(std) (( std == DRX_STANDARD_PAL_SECAM_BG) || \ (std == DRX_STANDARD_PAL_SECAM_DK) || \ (std == DRX_STANDARD_PAL_SECAM_I) || \ (std == DRX_STANDARD_PAL_SECAM_L) || \ (std == DRX_STANDARD_PAL_SECAM_LP) || \ (std == DRX_STANDARD_NTSC) || \ - (std == DRX_STANDARD_FM) ) + (std == DRX_STANDARD_FM)) -#define DRXJ_ISQAMSTD(std) ( ( std == DRX_STANDARD_ITU_A ) || \ +#define DRXJ_ISQAMSTD(std) (( std == DRX_STANDARD_ITU_A) || \ (std == DRX_STANDARD_ITU_B) || \ (std == DRX_STANDARD_ITU_C) || \ (std == DRX_STANDARD_ITU_D)) @@ -950,7 +950,7 @@ struct i2c_device_addr drxj_default_addr_g = { * \brief Default common attributes of a drxj demodulator instance. */ drx_common_attr_t drxj_default_comm_attr_g = { - (u8 *) NULL, /* ucode ptr */ + (u8 *)NULL, /* ucode ptr */ 0, /* ucode size */ true, /* ucode verify switch */ {0}, /* version record */ @@ -1147,7 +1147,7 @@ FUNCTIONS /* Some prototypes */ static int hi_command(struct i2c_device_addr *dev_addr, - const pdrxj_hi_cmd_t cmd, u16 *result); + const pdrxj_hi_cmd_t cmd, u16 *result); static int ctrl_lock_status(pdrx_demod_instance_t demod, pdrx_lock_status_t lock_stat); @@ -1173,7 +1173,7 @@ ctrl_set_cfg_afe_gain(pdrx_demod_instance_t demod, p_drxj_cfg_afe_gain_t afe_gai #ifdef DRXJ_SPLIT_UCODE_UPLOAD static int ctrl_u_codeUpload(pdrx_demod_instance_t demod, - p_drxu_code_info_t mc_info, + p_drxu_code_info_t mc_info, drxu_code_action_t action, bool audio_mc_upload); #endif /* DRXJ_SPLIT_UCODE_UPLOAD */ @@ -1683,7 +1683,7 @@ static const u16 nicam_presc_table_val[43] = TODO: check ignoring single/multimaster is ok for AUD access ? */ -#define DRXJ_ISAUDWRITE(addr) (((((addr)>>16)&1) == 1)?true:false) +#define DRXJ_ISAUDWRITE(addr) (((((addr)>>16)&1) == 1) ? true : false) #define DRXJ_DAP_AUDTRIF_TIMEOUT 80 /* millisec */ /*============================================================================*/ @@ -2136,7 +2136,7 @@ int drxj_dap_atomic_read_write_block(struct i2c_device_addr *dev_addr, word = ((u16) data[2 * i]); word += (((u16) data[(2 * i) + 1]) << 8); drxj_dap_write_reg16(dev_addr, - (DRXJ_HI_ATOMIC_BUF_START + i), + (DRXJ_HI_ATOMIC_BUF_START + i), word, 0); } } @@ -2147,7 +2147,7 @@ int drxj_dap_atomic_read_write_block(struct i2c_device_addr *dev_addr, /* read data from buffer */ for (i = 0; i < (datasize / 2); i++) { drxj_dap_read_reg16(dev_addr, - (DRXJ_HI_ATOMIC_BUF_START + i), + (DRXJ_HI_ATOMIC_BUF_START + i), &word, 0); data[2 * i] = (u8) (word & 0xFF); data[(2 * i) + 1] = (u8) (word >> 8); @@ -2338,7 +2338,7 @@ static int init_hi(const pdrx_demod_instance_t demod) { pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); pdrx_common_attr_t common_attr = (pdrx_common_attr_t) (NULL); - struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) (NULL); + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); ext_attr = (pdrxj_data_t) demod->my_ext_attr; common_attr = (pdrx_common_attr_t) demod->my_common_attr; @@ -2415,7 +2415,7 @@ static int get_device_capabilities(pdrx_demod_instance_t demod) { pdrx_common_attr_t common_attr = (pdrx_common_attr_t) (NULL); pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; - struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) (NULL); + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); u16 sio_pdr_ohw_cfg = 0; u32 sio_top_jtagid_lo = 0; u16 bid = 0; @@ -2588,7 +2588,7 @@ rw_error: static int power_up_device(pdrx_demod_instance_t demod) { - struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) (NULL); + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); u8 data = 0; u16 retry_count = 0; struct i2c_device_addr wake_up_addr; @@ -2603,12 +2603,12 @@ static int power_up_device(pdrx_demod_instance_t demod) do { data = 0; drxbsp_i2c_write_read(&wake_up_addr, 1, &data, - (struct i2c_device_addr *) (NULL), 0, - (u8 *) (NULL)); + (struct i2c_device_addr *)(NULL), 0, + (u8 *)(NULL)); drxbsp_hst_sleep(10); retry_count++; } while ((drxbsp_i2c_write_read - ((struct i2c_device_addr *) (NULL), 0, (u8 *) (NULL), dev_addr, 1, + ((struct i2c_device_addr *) (NULL), 0, (u8 *)(NULL), dev_addr, 1, &data) != DRX_STS_OK) && (retry_count < DRXJ_MAX_RETRIES_POWERUP)); @@ -2638,7 +2638,7 @@ static int power_up_device(pdrx_demod_instance_t demod) static int ctrl_set_cfg_mpeg_output(pdrx_demod_instance_t demod, pdrx_cfg_mpeg_output_t cfg_data) { - struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) (NULL); + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); pdrx_common_attr_t common_attr = (pdrx_common_attr_t) (NULL); u16 fec_oc_reg_mode = 0; @@ -3040,7 +3040,7 @@ rw_error: static int ctrl_get_cfg_mpeg_output(pdrx_demod_instance_t demod, pdrx_cfg_mpeg_output_t cfg_data) { - struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) (NULL); + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); pdrx_common_attr_t common_attr = (pdrx_common_attr_t) (NULL); drx_lock_status_t lock_status = DRX_NOT_LOCKED; u32 rate_reg = 0; @@ -3098,7 +3098,7 @@ rw_error: static int set_mpegtei_handling(pdrx_demod_instance_t demod) { pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); - struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) (NULL); + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); u16 fec_oc_dpr_mode = 0; u16 fec_oc_snc_mode = 0; u16 fec_oc_ems_mode = 0; @@ -3146,7 +3146,7 @@ rw_error: static int bit_reverse_mpeg_output(pdrx_demod_instance_t demod) { pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); - struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) (NULL); + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); u16 fec_oc_ipr_mode = 0; dev_addr = demod->my_i2c_dev_addr; @@ -3182,7 +3182,7 @@ rw_error: static int set_mpeg_output_clock_rate(pdrx_demod_instance_t demod) { pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); - struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) (NULL); + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); dev_addr = demod->my_i2c_dev_addr; ext_attr = (pdrxj_data_t) demod->my_ext_attr; @@ -3210,7 +3210,7 @@ rw_error: static int set_mpeg_start_width(pdrx_demod_instance_t demod) { pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); - struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) (NULL); + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); u16 fec_oc_comm_mb = 0; pdrx_common_attr_t common_attr = (pdrx_common_attr_t) NULL; @@ -3247,7 +3247,7 @@ rw_error: */ static int ctrl_set_cfg_mpeg_output_misc(pdrx_demod_instance_t demod, - p_drxj_cfg_mpeg_output_misc_t cfg_data) + p_drxj_cfg_mpeg_output_misc_t cfg_data) { pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); @@ -3297,7 +3297,7 @@ rw_error: */ static int ctrl_get_cfg_mpeg_output_misc(pdrx_demod_instance_t demod, - p_drxj_cfg_mpeg_output_misc_t cfg_data) + p_drxj_cfg_mpeg_output_misc_t cfg_data) { pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); u16 data = 0; @@ -4206,7 +4206,7 @@ ctrl_i2c_write_read(pdrx_demod_instance_t demod, pdrxi2c_data_t i2c_data) int tuner_i2c_write_read(struct tuner_instance *tuner, - struct i2c_device_addr *w_dev_addr, + struct i2c_device_addr *w_dev_addr, u16 w_count, u8 *wData, struct i2c_device_addr *r_dev_addr, u16 r_count, u8 *r_data) @@ -4359,7 +4359,7 @@ static int ctrl_set_cfg_pdr_safe_mode(pdrx_demod_instance_t demod, bool *enable) { pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; - struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) NULL; + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; pdrx_common_attr_t common_attr = (pdrx_common_attr_t) NULL; if (enable == NULL) { @@ -4758,7 +4758,7 @@ rw_error: */ static int set_frequency(pdrx_demod_instance_t demod, - pdrx_channel_t channel, s32 tuner_freq_offset) + pdrx_channel_t channel, s32 tuner_freq_offset) { struct i2c_device_addr *dev_addr = NULL; pdrx_common_attr_t common_attr = NULL; @@ -5046,7 +5046,7 @@ static int get_ctl_freq_offset(pdrx_demod_instance_t demod, s32 *ctl_freq) /* both registers are sign extended */ nominal_frequency = ext_attr->iqm_fs_rate_ofs; - ARR32(dev_addr, IQM_FS_RATE_LO__A, (u32 *) ¤t_frequency); + ARR32(dev_addr, IQM_FS_RATE_LO__A, (u32 *)¤t_frequency); if (ext_attr->pos_image == true) { /* negative image */ @@ -5144,7 +5144,7 @@ set_agc_rf(pdrx_demod_instance_t demod, p_drxj_cfg_agc_t agc_settings, bool atom (dev_addr, SCU_RAM_AGC_KI_RED__A, &data, 0)); data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M; CHK_ERROR((*scu_wr16) (dev_addr, SCU_RAM_AGC_KI_RED__A, - (~ + (~ (agc_settings-> speed << SCU_RAM_AGC_KI_RED_RAGC_RED__B) @@ -5383,7 +5383,7 @@ set_agc_if(pdrx_demod_instance_t demod, p_drxj_cfg_agc_t agc_settings, bool atom (dev_addr, SCU_RAM_AGC_KI_RED__A, &data, 0)); data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M; CHK_ERROR((*scu_wr16) (dev_addr, SCU_RAM_AGC_KI_RED__A, - (~ + (~ (agc_settings-> speed << SCU_RAM_AGC_KI_RED_IAGC_RED__B) @@ -5468,7 +5468,7 @@ set_agc_if(pdrx_demod_instance_t demod, p_drxj_cfg_agc_t agc_settings, bool atom /* always set the top to support configurations without if-loop */ CHK_ERROR((*scu_wr16) (dev_addr, - SCU_RAM_AGC_INGAIN_TGT_MIN__A, + SCU_RAM_AGC_INGAIN_TGT_MIN__A, agc_settings->top, 0)); } @@ -5870,9 +5870,9 @@ static int set_vsb_leak_n_gain(pdrx_demod_instance_t demod) dev_addr = demod->my_i2c_dev_addr; WRB(dev_addr, VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__A, - sizeof(vsb_ffe_leak_gain_ram0), ((u8 *) vsb_ffe_leak_gain_ram0)); + sizeof(vsb_ffe_leak_gain_ram0), ((u8 *)vsb_ffe_leak_gain_ram0)); WRB(dev_addr, VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__A, - sizeof(vsb_ffe_leak_gain_ram1), ((u8 *) vsb_ffe_leak_gain_ram1)); + sizeof(vsb_ffe_leak_gain_ram1), ((u8 *)vsb_ffe_leak_gain_ram1)); return (DRX_STS_OK); rw_error: @@ -5966,9 +5966,9 @@ static int set_vsb(pdrx_demod_instance_t demod) WR16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 1); WRB(dev_addr, IQM_CF_TAP_RE0__A, sizeof(vsb_taps_re), - ((u8 *) vsb_taps_re)); + ((u8 *)vsb_taps_re)); WRB(dev_addr, IQM_CF_TAP_IM0__A, sizeof(vsb_taps_re), - ((u8 *) vsb_taps_re)); + ((u8 *)vsb_taps_re)); WR16(dev_addr, VSB_TOP_BNTHRESH__A, 330); /* set higher threshold */ WR16(dev_addr, VSB_TOP_CLPLASTNUM__A, 90); /* burst detection on */ @@ -6382,7 +6382,7 @@ rw_error: #ifndef DRXJ_VSB_ONLY static int set_qam_measurement(pdrx_demod_instance_t demod, - enum drx_modulation constellation, u32 symbol_rate) + enum drx_modulation constellation, u32 symbol_rate) { struct i2c_device_addr *dev_addr = NULL; /* device address for I2C writes */ pdrxj_data_t ext_attr = NULL; /* Global data container for DRXJ specif data */ @@ -6564,9 +6564,9 @@ static int set_qam16(pdrx_demod_instance_t demod) }; WRB(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), - ((u8 *) qam_dq_qual_fun)); + ((u8 *)qam_dq_qual_fun)); WRB(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), - ((u8 *) qam_eq_cma_rad)); + ((u8 *)qam_eq_cma_rad)); WR16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 140); WR16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 50); @@ -6644,9 +6644,9 @@ static int set_qam32(pdrx_demod_instance_t demod) }; WRB(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), - ((u8 *) qam_dq_qual_fun)); + ((u8 *)qam_dq_qual_fun)); WRB(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), - ((u8 *) qam_eq_cma_rad)); + ((u8 *)qam_eq_cma_rad)); WR16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 90); WR16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 50); @@ -6724,9 +6724,9 @@ static int set_qam64(pdrx_demod_instance_t demod) }; WRB(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), - ((u8 *) qam_dq_qual_fun)); + ((u8 *)qam_dq_qual_fun)); WRB(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), - ((u8 *) qam_eq_cma_rad)); + ((u8 *)qam_eq_cma_rad)); WR16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 105); WR16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60); @@ -6804,9 +6804,9 @@ static int set_qam128(pdrx_demod_instance_t demod) }; WRB(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), - ((u8 *) qam_dq_qual_fun)); + ((u8 *)qam_dq_qual_fun)); WRB(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), - ((u8 *) qam_eq_cma_rad)); + ((u8 *)qam_eq_cma_rad)); WR16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 50); WR16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60); @@ -6884,9 +6884,9 @@ static int set_qam256(pdrx_demod_instance_t demod) }; WRB(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), - ((u8 *) qam_dq_qual_fun)); + ((u8 *)qam_dq_qual_fun)); WRB(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), - ((u8 *) qam_eq_cma_rad)); + ((u8 *)qam_eq_cma_rad)); WR16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 50); WR16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60); @@ -6949,7 +6949,7 @@ rw_error: */ static int set_qam(pdrx_demod_instance_t demod, - pdrx_channel_t channel, s32 tuner_freq_offset, u32 op) + pdrx_channel_t channel, s32 tuner_freq_offset, u32 op) { struct i2c_device_addr *dev_addr = NULL; pdrxj_data_t ext_attr = NULL; @@ -7308,33 +7308,33 @@ set_qam(pdrx_demod_instance_t demod, if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) { if (ext_attr->standard == DRX_STANDARD_ITU_A) { WRB(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_a_taps), - ((u8 *) qam_a_taps)); + ((u8 *)qam_a_taps)); WRB(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_a_taps), - ((u8 *) qam_a_taps)); + ((u8 *)qam_a_taps)); } else if (ext_attr->standard == DRX_STANDARD_ITU_B) { switch (channel->constellation) { case DRX_CONSTELLATION_QAM64: WRB(dev_addr, IQM_CF_TAP_RE0__A, - sizeof(qam_b64_taps), ((u8 *) qam_b64_taps)); + sizeof(qam_b64_taps), ((u8 *)qam_b64_taps)); WRB(dev_addr, IQM_CF_TAP_IM0__A, - sizeof(qam_b64_taps), ((u8 *) qam_b64_taps)); + sizeof(qam_b64_taps), ((u8 *)qam_b64_taps)); break; case DRX_CONSTELLATION_QAM256: WRB(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_b256_taps), - ((u8 *) qam_b256_taps)); + ((u8 *)qam_b256_taps)); WRB(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_b256_taps), - ((u8 *) qam_b256_taps)); + ((u8 *)qam_b256_taps)); break; default: return (DRX_STS_ERROR); } } else if (ext_attr->standard == DRX_STANDARD_ITU_C) { WRB(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_c_taps), - ((u8 *) qam_c_taps)); + ((u8 *)qam_c_taps)); WRB(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_c_taps), - ((u8 *) qam_c_taps)); + ((u8 *)qam_c_taps)); } /* SETP 4: constellation specific setup */ @@ -7693,7 +7693,7 @@ rw_error: */ static int set_qamChannel(pdrx_demod_instance_t demod, - pdrx_channel_t channel, s32 tuner_freq_offset) + pdrx_channel_t channel, s32 tuner_freq_offset) { drx_lock_status_t lock_status = DRX_NOT_LOCKED; pdrxj_data_t ext_attr = NULL; @@ -8639,7 +8639,7 @@ rw_error: */ static int ctrl_get_cfg_atv_agc_status(pdrx_demod_instance_t demod, - p_drxj_cfg_atv_agc_status_t agc_status) + p_drxj_cfg_atv_agc_status_t agc_status) { struct i2c_device_addr *dev_addr = NULL; pdrxj_data_t ext_attr = NULL; @@ -9166,9 +9166,9 @@ trouble ? WR16(dev_addr, IQM_RT_LO_INCR__A, IQM_RT_LO_INCR_MN); WR16(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M); WRB(dev_addr, IQM_CF_TAP_RE0__A, sizeof(ntsc_taps_re), - ((u8 *) ntsc_taps_re)); + ((u8 *)ntsc_taps_re)); WRB(dev_addr, IQM_CF_TAP_IM0__A, sizeof(ntsc_taps_im), - ((u8 *) ntsc_taps_im)); + ((u8 *)ntsc_taps_im)); WR16(dev_addr, ATV_TOP_CR_AMP_TH__A, ATV_TOP_CR_AMP_TH_MN); WR16(dev_addr, ATV_TOP_CR_CONT__A, @@ -9196,9 +9196,9 @@ trouble ? WR16(dev_addr, IQM_RT_LO_INCR__A, 2994); WR16(dev_addr, IQM_CF_MIDTAP__A, 0); WRB(dev_addr, IQM_CF_TAP_RE0__A, sizeof(fm_taps_re), - ((u8 *) fm_taps_re)); + ((u8 *)fm_taps_re)); WRB(dev_addr, IQM_CF_TAP_IM0__A, sizeof(fm_taps_im), - ((u8 *) fm_taps_im)); + ((u8 *)fm_taps_im)); WR16(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_FM | ATV_TOP_STD_VID_POL_FM)); WR16(dev_addr, ATV_TOP_MOD_CONTROL__A, 0); @@ -9218,9 +9218,9 @@ trouble ? WR16(dev_addr, IQM_RT_LO_INCR__A, 1820); /* TODO check with IS */ WR16(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M); WRB(dev_addr, IQM_CF_TAP_RE0__A, sizeof(bg_taps_re), - ((u8 *) bg_taps_re)); + ((u8 *)bg_taps_re)); WRB(dev_addr, IQM_CF_TAP_IM0__A, sizeof(bg_taps_im), - ((u8 *) bg_taps_im)); + ((u8 *)bg_taps_im)); WR16(dev_addr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_BG); WR16(dev_addr, ATV_TOP_CR_AMP_TH__A, ATV_TOP_CR_AMP_TH_BG); WR16(dev_addr, ATV_TOP_CR_CONT__A, @@ -9247,9 +9247,9 @@ trouble ? WR16(dev_addr, IQM_RT_LO_INCR__A, 2225); /* TODO check with IS */ WR16(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M); WRB(dev_addr, IQM_CF_TAP_RE0__A, sizeof(dk_i_l_lp_taps_re), - ((u8 *) dk_i_l_lp_taps_re)); + ((u8 *)dk_i_l_lp_taps_re)); WRB(dev_addr, IQM_CF_TAP_IM0__A, sizeof(dk_i_l_lp_taps_im), - ((u8 *) dk_i_l_lp_taps_im)); + ((u8 *)dk_i_l_lp_taps_im)); WR16(dev_addr, ATV_TOP_CR_AMP_TH__A, ATV_TOP_CR_AMP_TH_DK); WR16(dev_addr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_DK); WR16(dev_addr, ATV_TOP_CR_CONT__A, @@ -9276,9 +9276,9 @@ trouble ? WR16(dev_addr, IQM_RT_LO_INCR__A, 2225); /* TODO check with IS */ WR16(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M); WRB(dev_addr, IQM_CF_TAP_RE0__A, sizeof(dk_i_l_lp_taps_re), - ((u8 *) dk_i_l_lp_taps_re)); + ((u8 *)dk_i_l_lp_taps_re)); WRB(dev_addr, IQM_CF_TAP_IM0__A, sizeof(dk_i_l_lp_taps_im), - ((u8 *) dk_i_l_lp_taps_im)); + ((u8 *)dk_i_l_lp_taps_im)); WR16(dev_addr, ATV_TOP_CR_AMP_TH__A, ATV_TOP_CR_AMP_TH_I); WR16(dev_addr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_I); WR16(dev_addr, ATV_TOP_CR_CONT__A, @@ -9306,9 +9306,9 @@ trouble ? WR16(dev_addr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_L); WR16(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M); WRB(dev_addr, IQM_CF_TAP_RE0__A, sizeof(dk_i_l_lp_taps_re), - ((u8 *) dk_i_l_lp_taps_re)); + ((u8 *)dk_i_l_lp_taps_re)); WRB(dev_addr, IQM_CF_TAP_IM0__A, sizeof(dk_i_l_lp_taps_im), - ((u8 *) dk_i_l_lp_taps_im)); + ((u8 *)dk_i_l_lp_taps_im)); WR16(dev_addr, ATV_TOP_CR_AMP_TH__A, 0x2); /* TODO check with IS */ WR16(dev_addr, ATV_TOP_CR_CONT__A, (ATV_TOP_CR_CONT_CR_P_L | @@ -9337,9 +9337,9 @@ trouble ? WR16(dev_addr, IQM_RT_LO_INCR__A, 2225); /* TODO check with IS */ WR16(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M); WRB(dev_addr, IQM_CF_TAP_RE0__A, sizeof(dk_i_l_lp_taps_re), - ((u8 *) dk_i_l_lp_taps_re)); + ((u8 *)dk_i_l_lp_taps_re)); WRB(dev_addr, IQM_CF_TAP_IM0__A, sizeof(dk_i_l_lp_taps_im), - ((u8 *) dk_i_l_lp_taps_im)); + ((u8 *)dk_i_l_lp_taps_im)); WR16(dev_addr, ATV_TOP_CR_AMP_TH__A, 0x2); /* TODO check with IS */ WR16(dev_addr, ATV_TOP_CR_CONT__A, (ATV_TOP_CR_CONT_CR_P_LP | @@ -9457,7 +9457,7 @@ rw_error: */ static int set_atv_channel(pdrx_demod_instance_t demod, - s32 tuner_freq_offset, + s32 tuner_freq_offset, pdrx_channel_t channel, enum drx_standard standard) { drxjscu_cmd_t cmd_scu = { /* command */ 0, @@ -9524,7 +9524,7 @@ rw_error: #ifndef DRXJ_DIGITAL_ONLY static int get_atv_channel(pdrx_demod_instance_t demod, - pdrx_channel_t channel, enum drx_standard standard) + pdrx_channel_t channel, enum drx_standard standard) { s32 offset = 0; struct i2c_device_addr *dev_addr = NULL; @@ -9811,7 +9811,7 @@ static int power_down_aud(pdrx_demod_instance_t demod) struct i2c_device_addr *dev_addr = NULL; pdrxj_data_t ext_attr = NULL; - dev_addr = (struct i2c_device_addr *) demod->my_i2c_dev_addr; + dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; ext_attr = (pdrxj_data_t) demod->my_ext_attr; WR16(dev_addr, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP); @@ -9844,7 +9844,7 @@ static int aud_get_modus(pdrx_demod_instance_t demod, u16 *modus) return DRX_STS_INVALID_ARG; } - dev_addr = (struct i2c_device_addr *) demod->my_i2c_dev_addr; + dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* power up */ @@ -9887,7 +9887,7 @@ aud_ctrl_get_cfg_rds(pdrx_demod_instance_t demod, pdrx_cfg_aud_rds_t status) u16 r_rds_data = 0; u16 rds_data_cnt = 0; - addr = (struct i2c_device_addr *) demod->my_i2c_dev_addr; + addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; ext_attr = (pdrxj_data_t) demod->my_ext_attr; if (status == NULL) { @@ -9958,7 +9958,7 @@ aud_ctrl_get_carrier_detect_status(pdrx_demod_instance_t demod, pdrx_aud_status_ return DRX_STS_INVALID_ARG; } - dev_addr = (struct i2c_device_addr *) demod->my_i2c_dev_addr; + dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* power up */ @@ -10036,7 +10036,7 @@ aud_ctrl_get_status(pdrx_demod_instance_t demod, pdrx_aud_status_t status) return DRX_STS_INVALID_ARG; } - dev_addr = (struct i2c_device_addr *) demod->my_i2c_dev_addr; + dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* carrier detection */ @@ -10080,7 +10080,7 @@ aud_ctrl_get_cfg_volume(pdrx_demod_instance_t demod, pdrx_cfg_aud_volume_t volum return DRX_STS_INVALID_ARG; } - dev_addr = (struct i2c_device_addr *) demod->my_i2c_dev_addr; + dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* power up */ @@ -10212,7 +10212,7 @@ aud_ctrl_set_cfg_volume(pdrx_demod_instance_t demod, pdrx_cfg_aud_volume_t volum return DRX_STS_INVALID_ARG; } - dev_addr = (struct i2c_device_addr *) demod->my_i2c_dev_addr; + dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* power up */ @@ -10347,7 +10347,7 @@ aud_ctrl_get_cfg_output_i2s(pdrx_demod_instance_t demod, pdrx_cfg_i2s_output_t o return DRX_STS_INVALID_ARG; } - dev_addr = (struct i2c_device_addr *) demod->my_i2c_dev_addr; + dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* power up */ @@ -10453,7 +10453,7 @@ aud_ctrl_set_cfg_output_i2s(pdrx_demod_instance_t demod, pdrx_cfg_i2s_output_t o return DRX_STS_INVALID_ARG; } - dev_addr = (struct i2c_device_addr *) demod->my_i2c_dev_addr; + dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* power up */ @@ -10594,9 +10594,9 @@ rw_error: */ static int aud_ctrl_get_cfg_auto_sound(pdrx_demod_instance_t demod, - pdrx_cfg_aud_auto_sound_t auto_sound) + pdrx_cfg_aud_auto_sound_t auto_sound) { - struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) NULL; + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; u16 r_modus = 0; @@ -10651,9 +10651,9 @@ rw_error: */ static int aud_ctr_setl_cfg_auto_sound(pdrx_demod_instance_t demod, - pdrx_cfg_aud_auto_sound_t auto_sound) + pdrx_cfg_aud_auto_sound_t auto_sound) { - struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) NULL; + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; u16 r_modus = 0; @@ -10718,7 +10718,7 @@ rw_error: static int aud_ctrl_get_cfg_ass_thres(pdrx_demod_instance_t demod, pdrx_cfg_aud_ass_thres_t thres) { - struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) NULL; + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; u16 thres_a2 = 0; @@ -10762,7 +10762,7 @@ rw_error: static int aud_ctrl_set_cfg_ass_thres(pdrx_demod_instance_t demod, pdrx_cfg_aud_ass_thres_t thres) { - struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) NULL; + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; if (thres == NULL) { @@ -10801,7 +10801,7 @@ rw_error: static int aud_ctrl_get_cfg_carrier(pdrx_demod_instance_t demod, pdrx_cfg_aud_carriers_t carriers) { - struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) NULL; + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; u16 w_modus = 0; @@ -10906,7 +10906,7 @@ rw_error: static int aud_ctrl_set_cfg_carrier(pdrx_demod_instance_t demod, pdrx_cfg_aud_carriers_t carriers) { - struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) NULL; + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; u16 w_modus = 0; @@ -11006,7 +11006,7 @@ rw_error: static int aud_ctrl_get_cfg_mixer(pdrx_demod_instance_t demod, pdrx_cfg_aud_mixer_t mixer) { - struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) NULL; + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; u16 src_i2s_matr = 0; @@ -11101,7 +11101,7 @@ rw_error: static int aud_ctrl_set_cfg_mixer(pdrx_demod_instance_t demod, pdrx_cfg_aud_mixer_t mixer) { - struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) NULL; + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; u16 src_i2s_matr = 0; @@ -11209,7 +11209,7 @@ rw_error: static int aud_ctrl_set_cfg_av_sync(pdrx_demod_instance_t demod, pdrx_cfg_aud_av_sync_t av_sync) { - struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) NULL; + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; u16 w_aud_vid_sync = 0; @@ -11274,7 +11274,7 @@ rw_error: static int aud_ctrl_get_cfg_av_sync(pdrx_demod_instance_t demod, pdrx_cfg_aud_av_sync_t av_sync) { - struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) NULL; + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; u16 w_aud_vid_sync = 0; @@ -11331,7 +11331,7 @@ rw_error: static int aud_ctrl_get_cfg_dev(pdrx_demod_instance_t demod, pdrx_cfg_aud_deviation_t dev) { - struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) NULL; + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; u16 r_modus = 0; @@ -11372,7 +11372,7 @@ rw_error: static int aud_ctrl_set_cfg_dev(pdrx_demod_instance_t demod, pdrx_cfg_aud_deviation_t dev) { - struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) NULL; + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; u16 w_modus = 0; @@ -11425,7 +11425,7 @@ rw_error: static int aud_ctrl_get_cfg_prescale(pdrx_demod_instance_t demod, pdrx_cfg_aud_prescale_t presc) { - struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) NULL; + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; u16 r_max_fm_deviation = 0; @@ -11500,7 +11500,7 @@ rw_error: static int aud_ctrl_set_cfg_prescale(pdrx_demod_instance_t demod, pdrx_cfg_aud_prescale_t presc) { - struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) NULL; + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; u16 w_max_fm_deviation = 0; @@ -11582,7 +11582,7 @@ rw_error: */ static int aud_ctrl_beep(pdrx_demod_instance_t demod, pdrx_aud_beep_t beep) { - struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) NULL; + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; u16 the_beep = 0; @@ -11657,7 +11657,7 @@ aud_ctrl_set_standard(pdrx_demod_instance_t demod, pdrx_aud_standard_t standard) return DRX_STS_INVALID_ARG; } - dev_addr = (struct i2c_device_addr *) demod->my_i2c_dev_addr; + dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* power up */ @@ -11829,7 +11829,7 @@ aud_ctrl_get_standard(pdrx_demod_instance_t demod, pdrx_aud_standard_t standard) } ext_attr = (pdrxj_data_t) demod->my_ext_attr; - dev_addr = (struct i2c_device_addr *) demod->my_i2c_dev_addr; + dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; /* power up */ if (ext_attr->aud_data.audio_is_active == false) { @@ -11997,7 +11997,7 @@ rw_error: */ static int get_oob_lock_status(pdrx_demod_instance_t demod, - struct i2c_device_addr *dev_addr, pdrx_lock_status_t oob_lock) + struct i2c_device_addr *dev_addr, pdrx_lock_status_t oob_lock) { drxjscu_cmd_t scu_cmd; u16 cmd_result[2]; @@ -12707,7 +12707,7 @@ static int ctrl_set_oob(pdrx_demod_instance_t demod, p_drxoob_t oob_param) /* PRE-Filter coefficients (PFI) */ WRB(dev_addr, ORX_FWP_PFI_A_W__A, sizeof(pfi_coeffs[mode_index]), - ((u8 *) pfi_coeffs[mode_index])); + ((u8 *)pfi_coeffs[mode_index])); WR16(dev_addr, ORX_TOP_MDE_W__A, mode_index); /* NYQUIST-Filter coefficients (NYQ) */ @@ -13185,7 +13185,7 @@ ctrl_set_channel(pdrx_demod_instance_t demod, pdrx_channel_t channel) } CHK_ERROR(drxbsp_tuner_set_frequency(demod->my_tuner, - tuner_mode, tuner_set_freq)); + tuner_mode, tuner_set_freq)); if (common_attr->tuner_port_nr == 1) { /* open tuner bridge */ bridge_closed = false; @@ -13194,7 +13194,7 @@ ctrl_set_channel(pdrx_demod_instance_t demod, pdrx_channel_t channel) /* Get actual frequency set by tuner and compute offset */ CHK_ERROR(drxbsp_tuner_get_frequency(demod->my_tuner, - 0, + 0, &tuner_get_freq, &intermediate_freq)); tuner_freq_offset = tuner_get_freq - tuner_set_freq; @@ -13230,7 +13230,7 @@ ctrl_set_channel(pdrx_demod_instance_t demod, pdrx_channel_t channel) ext_attr->mirror = channel->mirror; } CHK_ERROR(set_atv_channel(demod, - tuner_freq_offset, channel, standard)); + tuner_freq_offset, channel, standard)); break; #endif #ifndef DRXJ_VSB_ONLY @@ -13259,7 +13259,7 @@ ctrl_set_channel(pdrx_demod_instance_t demod, pdrx_channel_t channel) /* set tuner frequency */ CHK_ERROR(drxbsp_tuner_set_frequency(demod->my_tuner, - tuner_mode, tuner_set_freq)); + tuner_mode, tuner_set_freq)); if (common_attr->tuner_port_nr == 1) { /* open tuner bridge */ bridge_closed = false; @@ -13336,7 +13336,7 @@ ctrl_get_channel(pdrx_demod_instance_t demod, pdrx_channel_t channel) /* Get frequency from tuner */ CHK_ERROR(drxbsp_tuner_get_frequency(demod->my_tuner, - 0, + 0, &(channel->frequency), &intermediate_freq)); tuner_freq_offset = channel->frequency - ext_attr->frequency; @@ -13998,7 +13998,7 @@ ctrl_power_mode(pdrx_demod_instance_t demod, pdrx_power_mode_t mode) { pdrx_common_attr_t common_attr = (pdrx_common_attr_t) NULL; pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; - struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) NULL; + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; u16 sio_cc_pwd_mode = 0; common_attr = (pdrx_common_attr_t) demod->my_common_attr; @@ -14125,7 +14125,7 @@ static int ctrl_version(pdrx_demod_instance_t demod, p_drx_version_list_t *version_list) { pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); - struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) (NULL); + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); pdrx_common_attr_t common_attr = (pdrx_common_attr_t) (NULL); u16 ucode_major_minor = 0; /* BCD Ma:Ma:Ma:Mi */ u16 ucode_patch = 0; /* BCD Pa:Pa:Pa:Pa */ @@ -14371,14 +14371,14 @@ bool is_mc_block_audio(u32 addr) */ static int ctrl_u_codeUpload(pdrx_demod_instance_t demod, - p_drxu_code_info_t mc_info, + p_drxu_code_info_t mc_info, drxu_code_action_t action, bool upload_audio_mc) { u16 i = 0; u16 mc_nr_of_blks = 0; u16 mc_magic_word = 0; - u8 *mc_data = (u8 *) (NULL); - struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) (NULL); + u8 *mc_data = (u8 *)(NULL); + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); dev_addr = demod->my_i2c_dev_addr; @@ -15293,7 +15293,7 @@ static int ctrl_set_cfg(pdrx_demod_instance_t demod, pdrx_cfg_t config) (pdrx_cfg_mpeg_output_t) config-> cfg_data); case DRX_CFG_PINS_SAFE_MODE: - return ctrl_set_cfg_pdr_safe_mode(demod, (bool *) config->cfg_data); + return ctrl_set_cfg_pdr_safe_mode(demod, (bool *)config->cfg_data); case DRXJ_CFG_AGC_RF: return ctrl_set_cfg_agc_rf(demod, (p_drxj_cfg_agc_t) config->cfg_data); case DRXJ_CFG_AGC_IF: @@ -15312,7 +15312,7 @@ static int ctrl_set_cfg(pdrx_demod_instance_t demod, pdrx_cfg_t config) return ctrl_set_cfg_reset_pkt_err(demod); #ifndef DRXJ_DIGITAL_ONLY case DRXJ_CFG_OOB_PRE_SAW: - return ctrl_set_cfg_oob_pre_saw(demod, (u16 *) (config->cfg_data)); + return ctrl_set_cfg_oob_pre_saw(demod, (u16 *)(config->cfg_data)); case DRXJ_CFG_OOB_LO_POW: return ctrl_set_cfg_oob_lo_power(demod, (p_drxj_cfg_oob_lo_power_t) (config-> @@ -15402,13 +15402,13 @@ static int ctrl_get_cfg(pdrx_demod_instance_t demod, pdrx_cfg_t config) (pdrx_cfg_mpeg_output_t) config-> cfg_data); case DRX_CFG_PINS_SAFE_MODE: - return ctrl_get_cfg_pdr_safe_mode(demod, (bool *) config->cfg_data); + return ctrl_get_cfg_pdr_safe_mode(demod, (bool *)config->cfg_data); case DRXJ_CFG_AGC_RF: return ctrl_get_cfg_agc_rf(demod, (p_drxj_cfg_agc_t) config->cfg_data); case DRXJ_CFG_AGC_IF: return ctrl_get_cfg_agc_if(demod, (p_drxj_cfg_agc_t) config->cfg_data); case DRXJ_CFG_AGC_INTERNAL: - return ctrl_get_cfg_agc_internal(demod, (u16 *) config->cfg_data); + return ctrl_get_cfg_agc_internal(demod, (u16 *)config->cfg_data); case DRXJ_CFG_PRE_SAW: return ctrl_get_cfg_pre_saw(demod, (p_drxj_cfg_pre_saw_t) config->cfg_data); @@ -15416,21 +15416,21 @@ static int ctrl_get_cfg(pdrx_demod_instance_t demod, pdrx_cfg_t config) return ctrl_get_cfg_afe_gain(demod, (p_drxj_cfg_afe_gain_t) config->cfg_data); case DRXJ_CFG_ACCUM_CR_RS_CW_ERR: - return ctrl_get_accum_cr_rs_cw_err(demod, (u32 *) config->cfg_data); + return ctrl_get_accum_cr_rs_cw_err(demod, (u32 *)config->cfg_data); case DRXJ_CFG_FEC_MERS_SEQ_COUNT: - return ctrl_get_fec_meas_seq_count(demod, (u16 *) config->cfg_data); + return ctrl_get_fec_meas_seq_count(demod, (u16 *)config->cfg_data); case DRXJ_CFG_VSB_MISC: return ctrl_get_cfg_vsb_misc(demod, (p_drxj_cfg_vsb_misc_t) config->cfg_data); case DRXJ_CFG_SYMBOL_CLK_OFFSET: return ctrl_get_cfg_symbol_clock_offset(demod, - (s32 *) config->cfg_data); + (s32 *)config->cfg_data); #ifndef DRXJ_DIGITAL_ONLY case DRXJ_CFG_OOB_MISC: return ctrl_get_cfg_oob_misc(demod, (p_drxj_cfg_oob_misc_t) config->cfg_data); case DRXJ_CFG_OOB_PRE_SAW: - return ctrl_get_cfg_oob_pre_saw(demod, (u16 *) (config->cfg_data)); + return ctrl_get_cfg_oob_pre_saw(demod, (u16 *)(config->cfg_data)); case DRXJ_CFG_OOB_LO_POW: return ctrl_get_cfg_oob_lo_power(demod, (p_drxj_cfg_oob_lo_power_t) (config-> @@ -15806,7 +15806,7 @@ drxj_ctrl(pdrx_demod_instance_t demod, u32 ctrl, void *ctrl_data) /*======================================================================*/ case DRX_CTRL_SIG_STRENGTH: { - return ctrl_sig_strength(demod, (u16 *) ctrl_data); + return ctrl_sig_strength(demod, (u16 *)ctrl_data); } break; /*======================================================================*/ @@ -15830,7 +15830,7 @@ drxj_ctrl(pdrx_demod_instance_t demod, u32 ctrl, void *ctrl_data) /*======================================================================*/ case DRX_CTRL_I2C_BRIDGE: { - return ctrl_i2c_bridge(demod, (bool *) ctrl_data); + return ctrl_i2c_bridge(demod, (bool *)ctrl_data); } break; /*======================================================================*/ @@ -15844,14 +15844,14 @@ drxj_ctrl(pdrx_demod_instance_t demod, u32 ctrl, void *ctrl_data) case DRX_CTRL_SET_STANDARD: { return ctrl_set_standard(demod, - (enum drx_standard *) ctrl_data); + (enum drx_standard *)ctrl_data); } break; /*======================================================================*/ case DRX_CTRL_GET_STANDARD: { return ctrl_get_standard(demod, - (enum drx_standard *) ctrl_data); + (enum drx_standard *)ctrl_data); } break; /*======================================================================*/ @@ -15864,7 +15864,7 @@ drxj_ctrl(pdrx_demod_instance_t demod, u32 ctrl, void *ctrl_data) case DRX_CTRL_VERSION: { return ctrl_version(demod, - (p_drx_version_list_t *) ctrl_data); + (p_drx_version_list_t *)ctrl_data); } break; /*======================================================================*/ diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.h b/drivers/media/dvb-frontends/drx39xyj/drxj.h index 54b5c14..d882f22 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.h +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.h @@ -723,9 +723,9 @@ STRUCTS Exported FUNCTIONS -------------------------------------------------------------------------*/ - extern int drxj_open(pdrx_demod_instance_t demod); - extern int drxj_close(pdrx_demod_instance_t demod); - extern int drxj_ctrl(pdrx_demod_instance_t demod, + int drxj_open(pdrx_demod_instance_t demod); + int drxj_close(pdrx_demod_instance_t demod); + int drxj_ctrl(pdrx_demod_instance_t demod, u32 ctrl, void *ctrl_data); /*------------------------------------------------------------------------- diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj_mc.h b/drivers/media/dvb-frontends/drx39xyj/drxj_mc.h index 16f7a9f..dc2af8f 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj_mc.h +++ b/drivers/media/dvb-frontends/drx39xyj/drxj_mc.h @@ -41,7 +41,7 @@ #ifndef __DRXJ_MC_MAIN_H__ #define __DRXJ_MC_MAIN_H__ -#define DRXJ_MC_MAIN ((u8 *) drxj_mc_main_g) +#define DRXJ_MC_MAIN ((u8 *)drxj_mc_main_g) const u8 drxj_mc_main_g[] = { 0x48, 0x4c, 0x00, 0x06, 0x00, 0x00, 0xf3, 0x10, 0x00, 0x00, 0x00, 0x08, diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsb.h b/drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsb.h index 211323591..a6c29ca 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsb.h +++ b/drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsb.h @@ -41,7 +41,7 @@ #ifndef __DRXJ_MC_VSB_H__ #define __DRXJ_MC_VSB_H__ -#define DRXJ_MC_VSB ((u8 *) drxj_mc_vsb_g) +#define DRXJ_MC_VSB ((u8 *)drxj_mc_vsb_g) const u8 drxj_mc_vsb_g[] = { 0x48, 0x4c, 0x00, 0x03, 0x00, 0x00, 0x2b, 0x62, 0x00, 0x00, 0x00, 0x08, diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsbqam.h b/drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsbqam.h index 9996c69..471660c 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsbqam.h +++ b/drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsbqam.h @@ -42,7 +42,7 @@ #ifndef __DRXJ_MC_VSBQAM_H__ #define __DRXJ_MC_VSBQAM_H__ -#define DRXJ_MC_VSBQAM ((u8 *) drxj_mc_vsbqam_g) +#define DRXJ_MC_VSBQAM ((u8 *)drxj_mc_vsbqam_g) const u8 drxj_mc_vsbqam_g[] = { 0x48, 0x4c, 0x00, 0x04, 0x00, 0x00, 0x56, 0xa0, 0x00, 0x00, 0x00, 0x08, -- cgit v1.1 From c677f7601fa672b4835d0ae3422a761e5e2ab27a Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Thu, 16 Jan 2014 11:32:04 -0300 Subject: [media] drx-j: remove the unused tuner_i2c_write_read() function This function is not static. Also, it is not used anywhere. So, drop it. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drxj.c | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index bd7ad18..5bf215e 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -4204,22 +4204,6 @@ ctrl_i2c_write_read(pdrx_demod_instance_t demod, pdrxi2c_data_t i2c_data) return (DRX_STS_FUNC_NOT_AVAILABLE); } -int -tuner_i2c_write_read(struct tuner_instance *tuner, - struct i2c_device_addr *w_dev_addr, - u16 w_count, - u8 *wData, - struct i2c_device_addr *r_dev_addr, u16 r_count, u8 *r_data) -{ - pdrx_demod_instance_t demod; - drxi2c_data_t i2c_data = - { 2, w_dev_addr, w_count, wData, r_dev_addr, r_count, r_data }; - - demod = (pdrx_demod_instance_t) (tuner->my_common_attr->myUser_data); - - return (ctrl_i2c_write_read(demod, &i2c_data)); -} - /* -------------------------------------------------------------------------- */ /** * \brief Measure result of ADC synchronisation -- cgit v1.1 From 4d7bb0ebbbb00c34fc6f4449d083fe6a55e78db1 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Thu, 16 Jan 2014 11:49:13 -0300 Subject: [media] drx-j: Remove a bunch of unused but assigned vars None of those vars are used on those functions. Just remove them. After this patch, there's just one of such warnings: drivers/media/dvb-frontends/drx39xyj/drxj.c: In function 'ctrl_get_qam_sig_quality': drivers/media/dvb-frontends/drx39xyj/drxj.c:7872:6: warning: variable 'ber_cnt' set but not used [-Wunused-but-set-variable] u32 ber_cnt = 0; /* BER count */ We'll keep it, as BER count will be useful when converting the frontend to report statistics via DVBv5 API Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drxj.c | 136 ++++++---------------------- 1 file changed, 29 insertions(+), 107 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index 5bf215e..24f84e5 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -3341,13 +3341,10 @@ static int ctrl_get_cfg_hw_cfg(pdrx_demod_instance_t demod, p_drxj_cfg_hw_cfg_t cfg_data) { u16 data = 0; - pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); - if (cfg_data == NULL) { + if (cfg_data == NULL) return (DRX_STS_INVALID_ARG); - } - ext_attr = (pdrxj_data_t) demod->my_ext_attr; WR16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA); RR16(demod->my_i2c_dev_addr, SIO_PDR_OHW_CFG__A, &data); WR16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000); @@ -4299,11 +4296,7 @@ rw_error: static int iqm_set_af(pdrx_demod_instance_t demod, bool active) { u16 data = 0; - struct i2c_device_addr *dev_addr = NULL; - pdrxj_data_t ext_attr = NULL; - - ext_attr = (pdrxj_data_t) demod->my_ext_attr; - dev_addr = demod->my_i2c_dev_addr; + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; /* Configure IQM */ RR16(dev_addr, IQM_AF_STDBY__A, &data); @@ -4315,7 +4308,6 @@ static int iqm_set_af(pdrx_demod_instance_t demod, bool active) & (~IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE) ); } else { /* active */ - data |= (IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE | IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE | IQM_AF_STDBY_STDBY_PD_A2_ACTIVE @@ -4342,17 +4334,14 @@ ctrl_set_cfg_atv_output(pdrx_demod_instance_t demod, p_drxj_cfg_atv_output_t out static int ctrl_set_cfg_pdr_safe_mode(pdrx_demod_instance_t demod, bool *enable) { - pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; - struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; - pdrx_common_attr_t common_attr = (pdrx_common_attr_t) NULL; + pdrxj_data_t ext_attr = NULL; + struct i2c_device_addr *dev_addr = NULL; - if (enable == NULL) { + if (enable == NULL) return (DRX_STS_INVALID_ARG); - } dev_addr = demod->my_i2c_dev_addr; ext_attr = (pdrxj_data_t) demod->my_ext_attr; - common_attr = demod->my_common_attr; /* Write magic word to enable pdr reg write */ WR16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); @@ -4744,27 +4733,22 @@ static int set_frequency(pdrx_demod_instance_t demod, pdrx_channel_t channel, s32 tuner_freq_offset) { - struct i2c_device_addr *dev_addr = NULL; - pdrx_common_attr_t common_attr = NULL; + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + pdrxj_data_t ext_attr = demod->my_ext_attr; s32 sampling_frequency = 0; s32 frequency_shift = 0; s32 if_freq_actual = 0; - s32 rf_freq_residual = 0; + s32 rf_freq_residual = -1 * tuner_freq_offset; s32 adc_freq = 0; s32 intermediate_freq = 0; u32 iqm_fs_rate_ofs = 0; - pdrxj_data_t ext_attr = NULL; bool adc_flip = true; bool select_pos_image = false; - bool rf_mirror = false; - bool tuner_mirror = true; + bool rf_mirror; + bool tuner_mirror; bool image_to_select = true; s32 fm_frequency_shift = 0; - dev_addr = demod->my_i2c_dev_addr; - common_attr = (pdrx_common_attr_t) demod->my_common_attr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; - rf_freq_residual = -1 * tuner_freq_offset; rf_mirror = (ext_attr->mirror == DRX_MIRROR_YES) ? true : false; tuner_mirror = demod->my_common_attr->mirror_freq_spect ? false : true; /* @@ -4851,17 +4835,13 @@ rw_error: static int get_sig_strength(pdrx_demod_instance_t demod, u16 *sig_strength) { + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; u16 rf_gain = 0; u16 if_gain = 0; u16 if_agc_sns = 0; u16 if_agc_top = 0; u16 rf_agc_max = 0; u16 rf_agc_min = 0; - pdrxj_data_t ext_attr = NULL; - struct i2c_device_addr *dev_addr = NULL; - - ext_attr = (pdrxj_data_t) demod->my_ext_attr; - dev_addr = demod->my_i2c_dev_addr; RR16(dev_addr, IQM_AF_AGC_IF__A, &if_gain); if_gain &= IQM_AF_AGC_IF__M; @@ -4976,13 +4956,8 @@ static int get_str_freq_offset(pdrx_demod_instance_t demod, s32 *str_freq) u32 symbol_frequency_ratio = 0; u32 symbol_nom_frequency_ratio = 0; - enum drx_standard standard = DRX_STANDARD_UNKNOWN; - struct i2c_device_addr *dev_addr = NULL; - pdrxj_data_t ext_attr = NULL; - - dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; - standard = ext_attr->standard; + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + pdrxj_data_t ext_attr = demod->my_ext_attr; ARR32(dev_addr, IQM_RC_RATE_LO__A, &symbol_frequency_ratio); symbol_nom_frequency_ratio = ext_attr->iqm_rc_rate_ofs; @@ -5607,7 +5582,7 @@ rw_error: */ static int power_down_vsb(pdrx_demod_instance_t demod, bool primary) { - struct i2c_device_addr *dev_addr = NULL; + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; drxjscu_cmd_t cmd_scu = { /* command */ 0, /* parameter_len */ 0, /* result_len */ 0, @@ -5615,11 +5590,8 @@ static int power_down_vsb(pdrx_demod_instance_t demod, bool primary) /* *result */ NULL }; u16 cmd_result = 0; - pdrxj_data_t ext_attr = NULL; drx_cfg_mpeg_output_t cfg_mpeg_output; - dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* STOP demodulator reset of FEC and VSB HW @@ -6303,13 +6275,9 @@ static int power_down_qam(pdrx_demod_instance_t demod, bool primary) /* *result */ NULL }; u16 cmd_result = 0; - struct i2c_device_addr *dev_addr = NULL; - pdrxj_data_t ext_attr = NULL; + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; drx_cfg_mpeg_output_t cfg_mpeg_output; - dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; - /* STOP demodulator resets IQM, QAM and FEC HW blocks @@ -8626,17 +8594,14 @@ ctrl_get_cfg_atv_agc_status(pdrx_demod_instance_t demod, p_drxj_cfg_atv_agc_status_t agc_status) { struct i2c_device_addr *dev_addr = NULL; - pdrxj_data_t ext_attr = NULL; u16 data = 0; u32 tmp = 0; /* Check arguments */ - if (agc_status == NULL) { + if (agc_status == NULL) return DRX_STS_INVALID_ARG; - } dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* RFgain = (IQM_AF_AGC_RF__A * 26.75)/1000 (uA) @@ -8728,11 +8693,7 @@ rw_error: */ static int power_up_atv(pdrx_demod_instance_t demod, enum drx_standard standard) { - struct i2c_device_addr *dev_addr = NULL; - pdrxj_data_t ext_attr = NULL; - - dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; /* ATV NTSC */ WR16(dev_addr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_ACTIVE); @@ -8766,7 +8727,7 @@ rw_error: static int power_down_atv(pdrx_demod_instance_t demod, enum drx_standard standard, bool primary) { - struct i2c_device_addr *dev_addr = NULL; + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; drxjscu_cmd_t cmd_scu = { /* command */ 0, /* parameter_len */ 0, /* result_len */ 0, @@ -8774,10 +8735,7 @@ power_down_atv(pdrx_demod_instance_t demod, enum drx_standard standard, bool pri /* *result */ NULL }; u16 cmd_result = 0; - pdrxj_data_t ext_attr = NULL; - dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* ATV NTSC */ /* Stop ATV SCU (will reset ATV and IQM hardware */ @@ -9511,11 +9469,7 @@ get_atv_channel(pdrx_demod_instance_t demod, pdrx_channel_t channel, enum drx_standard standard) { s32 offset = 0; - struct i2c_device_addr *dev_addr = NULL; - pdrxj_data_t ext_attr = NULL; - - dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; /* Bandwidth */ channel->bandwidth = ((pdrxj_data_t) demod->my_ext_attr)->curr_bandwidth; @@ -10580,16 +10534,12 @@ static int aud_ctrl_get_cfg_auto_sound(pdrx_demod_instance_t demod, pdrx_cfg_aud_auto_sound_t auto_sound) { - struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; - pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; - + pdrxj_data_t ext_attr = NULL; u16 r_modus = 0; - if (auto_sound == NULL) { + if (auto_sound == NULL) return DRX_STS_INVALID_ARG; - } - dev_addr = demod->my_i2c_dev_addr; ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* power up */ @@ -11315,17 +11265,10 @@ rw_error: static int aud_ctrl_get_cfg_dev(pdrx_demod_instance_t demod, pdrx_cfg_aud_deviation_t dev) { - struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; - pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; - u16 r_modus = 0; - if (dev == NULL) { + if (dev == NULL) return DRX_STS_INVALID_ARG; - } - - ext_attr = (pdrxj_data_t) demod->my_ext_attr; - dev_addr = demod->my_i2c_dev_addr; CHK_ERROR(aud_get_modus(demod, &r_modus)); @@ -12395,11 +12338,7 @@ rw_error: static int set_orx_nsu_aox(pdrx_demod_instance_t demod, bool active) { u16 data = 0; - struct i2c_device_addr *dev_addr = NULL; - pdrxj_data_t ext_attr = NULL; - - ext_attr = (pdrxj_data_t) demod->my_ext_attr; - dev_addr = demod->my_i2c_dev_addr; + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; /* Configure NSU_AOX */ RR16(dev_addr, ORX_NSU_AOX_STDBY_W__A, &data); @@ -12458,7 +12397,6 @@ rw_error: static int ctrl_set_oob(pdrx_demod_instance_t demod, p_drxoob_t oob_param) { #ifndef DRXJ_DIGITAL_ONLY - drxoob_downstream_standard_t standard = DRX_OOB_MODE_A; s32 freq = 0; /* KHz */ struct i2c_device_addr *dev_addr = NULL; pdrxj_data_t ext_attr = NULL; @@ -12503,8 +12441,6 @@ static int ctrl_set_oob(pdrx_demod_instance_t demod, p_drxoob_t oob_param) return (DRX_STS_OK); } - standard = oob_param->standard; - freq = oob_param->frequency; if ((freq < 70000) || (freq > 130000)) return (DRX_STS_ERROR); @@ -13931,15 +13867,12 @@ static int ctrl_get_cfg_symbol_clock_offset(pdrx_demod_instance_t demod, s32 *rate_offset) { enum drx_standard standard = DRX_STANDARD_UNKNOWN; - struct i2c_device_addr *dev_addr = NULL; pdrxj_data_t ext_attr = NULL; /* check arguments */ - if (rate_offset == NULL) { + if (rate_offset == NULL) return (DRX_STS_INVALID_ARG); - } - dev_addr = demod->my_i2c_dev_addr; ext_attr = (pdrxj_data_t) demod->my_ext_attr; standard = ext_attr->standard; @@ -15111,15 +15044,12 @@ rw_error: static int ctrl_get_cfg_pre_saw(pdrx_demod_instance_t demod, p_drxj_cfg_pre_saw_t pre_saw) { - struct i2c_device_addr *dev_addr = NULL; pdrxj_data_t ext_attr = NULL; /* check arguments */ - if (pre_saw == NULL) { + if (pre_saw == NULL) return (DRX_STS_INVALID_ARG); - } - dev_addr = demod->my_i2c_dev_addr; ext_attr = (pdrxj_data_t) demod->my_ext_attr; switch (pre_saw->standard) { @@ -15171,16 +15101,13 @@ ctrl_get_cfg_pre_saw(pdrx_demod_instance_t demod, p_drxj_cfg_pre_saw_t pre_saw) static int ctrl_get_cfg_afe_gain(pdrx_demod_instance_t demod, p_drxj_cfg_afe_gain_t afe_gain) { - struct i2c_device_addr *dev_addr = NULL; pdrxj_data_t ext_attr = NULL; /* check arguments */ - if (afe_gain == NULL) { + if (afe_gain == NULL) return (DRX_STS_INVALID_ARG); - } - dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = demod->my_ext_attr; switch (afe_gain->standard) { case DRX_STANDARD_8VSB: @@ -15724,15 +15651,10 @@ rw_error: */ int drxj_close(pdrx_demod_instance_t demod) { - struct i2c_device_addr *dev_addr = NULL; - pdrxj_data_t ext_attr = NULL; - pdrx_common_attr_t common_attr = NULL; + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + pdrx_common_attr_t common_attr = demod->my_common_attr; drx_power_mode_t power_mode = DRX_POWER_UP; - common_attr = (pdrx_common_attr_t) demod->my_common_attr; - dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; - /* power up */ CHK_ERROR(ctrl_power_mode(demod, &power_mode)); -- cgit v1.1 From 4a8a8694de2a4d1d94854ac96b1132030b46b685 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Thu, 16 Jan 2014 12:05:15 -0300 Subject: [media] drx-j: Some minor CodingStyle fixes at headers No functional changes. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h | 22 ++++++++-------------- drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h | 9 ++------- 2 files changed, 10 insertions(+), 21 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h b/drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h index dd2fc797..80d7b20 100644 --- a/drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h +++ b/drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h @@ -1,4 +1,6 @@ /* + I2C API, implementation depends on board specifics + Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. All rights reserved. @@ -26,20 +28,12 @@ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ -/** -* \file $Id: bsp_i2c.h,v 1.5 2009/07/07 14:20:30 justin Exp $ -* -* \brief I2C API, implementation depends on board specifics -* -* This module encapsulates I2C access.In some applications several devices -* share one I2C bus. If these devices have the same I2C address some kind -* off "switch" must be implemented to ensure error free communication with -* one device. In case such a "switch" is used, the device ID can be used -* to implement control over this "switch". -* -* + This module encapsulates I2C access.In some applications several devices + share one I2C bus. If these devices have the same I2C address some kind + off "switch" must be implemented to ensure error free communication with + one device. In case such a "switch" is used, the device ID can be used + to implement control over this "switch". */ #ifndef __BSPI2C_H__ @@ -123,7 +117,7 @@ Exported FUNCTIONS */ drx_status_t drxbsp_i2c_write_read(struct i2c_device_addr *w_dev_addr, u16 w_count, - u8 *wData, + u8 *w_data, struct i2c_device_addr *r_dev_addr, u16 r_count, u8 *r_data); diff --git a/drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h b/drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h index 0016ba7..080ac02e 100644 --- a/drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h +++ b/drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h @@ -1,4 +1,6 @@ /* + Tuner dependable type definitions, macro's and functions + Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. All rights reserved. @@ -28,13 +30,6 @@ POSSIBILITY OF SUCH DAMAGE. */ -/** -* \file $Id: bsp_tuner.h,v 1.5 2009/10/19 22:15:13 dingtao Exp $ -* -* \brief Tuner dependable type definitions, macro's and functions -* -*/ - #ifndef __DRXBSP_TUNER_H__ #define __DRXBSP_TUNER_H__ /*------------------------------------------------------------------------------ -- cgit v1.1 From f531f22505f683a947e74e48f646e93ad1afe208 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Thu, 16 Jan 2014 12:20:38 -0300 Subject: [media] drx-j: make a few functions static drivers/media/dvb-frontends/drx39xyj/drx_driver.c:181:7: warning: no previous prototype for 'get_scan_context' [-Wmissing-prototypes] void *get_scan_context(pdrx_demod_instance_t demod, void *scan_context) drivers/media/dvb-frontends/drx39xyj/drx_driver.c: At top level: drivers/media/dvb-frontends/drx39xyj/drx_driver.c:842:5: warning: no previous prototype for 'ctrl_dump_registers' [-Wmissing-prototypes] int ctrl_dump_registers(pdrx_demod_instance_t demod, Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drx_driver.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c index e8d1a26..db92b4f 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c @@ -178,7 +178,7 @@ static drx_scan_func_t get_scan_function(pdrx_demod_instance_t demod) * \param scan_context: Context Pointer. * \return drx_scan_func_t. */ -void *get_scan_context(pdrx_demod_instance_t demod, void *scan_context) +static void *get_scan_context(pdrx_demod_instance_t demod, void *scan_context) { pdrx_common_attr_t common_attr = (pdrx_common_attr_t) (NULL); @@ -839,7 +839,7 @@ ctrl_program_tuner(pdrx_demod_instance_t demod, pdrx_channel_t channel) * \retval DRX_STS_INVALID_ARG: Wrong parameters. * */ -int ctrl_dump_registers(pdrx_demod_instance_t demod, +static int ctrl_dump_registers(pdrx_demod_instance_t demod, p_drx_reg_dump_t registers) { u16 i = 0; -- cgit v1.1 From ffe7c4f921836a577ba650b3263062a63524e49e Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Thu, 16 Jan 2014 12:17:27 -0300 Subject: [media] drx-j: Get rid of drx39xyj/bsp_tuner.h This file is not used anywhere. Drop it. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h | 204 ----------------------- 1 file changed, 204 deletions(-) delete mode 100644 drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h diff --git a/drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h b/drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h deleted file mode 100644 index 080ac02e..0000000 --- a/drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h +++ /dev/null @@ -1,204 +0,0 @@ -/* - Tuner dependable type definitions, macro's and functions - - Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - * Neither the name of Trident Microsystems nor Hauppauge Computer Works - nor the names of its contributors may be used to endorse or promote - products derived from this software without specific prior written - permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. -*/ - -#ifndef __DRXBSP_TUNER_H__ -#define __DRXBSP_TUNER_H__ -/*------------------------------------------------------------------------------ -INCLUDES -------------------------------------------------------------------------------*/ -#include "bsp_types.h" -#include "bsp_i2c.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/*------------------------------------------------------------------------------ -DEFINES -------------------------------------------------------------------------------*/ - - /* Sub-mode bits should be adjacent and incremental */ -#define TUNER_MODE_SUB0 0x0001 /* for sub-mode (e.g. RF-AGC setting) */ -#define TUNER_MODE_SUB1 0x0002 /* for sub-mode (e.g. RF-AGC setting) */ -#define TUNER_MODE_SUB2 0x0004 /* for sub-mode (e.g. RF-AGC setting) */ -#define TUNER_MODE_SUB3 0x0008 /* for sub-mode (e.g. RF-AGC setting) */ -#define TUNER_MODE_SUB4 0x0010 /* for sub-mode (e.g. RF-AGC setting) */ -#define TUNER_MODE_SUB5 0x0020 /* for sub-mode (e.g. RF-AGC setting) */ -#define TUNER_MODE_SUB6 0x0040 /* for sub-mode (e.g. RF-AGC setting) */ -#define TUNER_MODE_SUB7 0x0080 /* for sub-mode (e.g. RF-AGC setting) */ - -#define TUNER_MODE_DIGITAL 0x0100 /* for digital channel (e.g. DVB-T) */ -#define TUNER_MODE_ANALOG 0x0200 /* for analog channel (e.g. PAL) */ -#define TUNER_MODE_SWITCH 0x0400 /* during channel switch & scanning */ -#define TUNER_MODE_LOCK 0x0800 /* after tuner has locked */ -#define TUNER_MODE_6MHZ 0x1000 /* for 6MHz bandwidth channels */ -#define TUNER_MODE_7MHZ 0x2000 /* for 7MHz bandwidth channels */ -#define TUNER_MODE_8MHZ 0x4000 /* for 8MHz bandwidth channels */ - -#define TUNER_MODE_SUB_MAX 8 -#define TUNER_MODE_SUBALL (TUNER_MODE_SUB0 | TUNER_MODE_SUB1 | \ - TUNER_MODE_SUB2 | TUNER_MODE_SUB3 | \ - TUNER_MODE_SUB4 | TUNER_MODE_SUB5 | \ - TUNER_MODE_SUB6 | TUNER_MODE_SUB7) - -/*------------------------------------------------------------------------------ -TYPEDEFS -------------------------------------------------------------------------------*/ - - typedef u32 tuner_mode_t; - typedef u32 *ptuner_mode_t; - - typedef char *tuner_sub_mode_t; /* description of submode */ - typedef tuner_sub_mode_t *ptuner_sub_mode_t; - - typedef enum { - - TUNER_LOCKED, - TUNER_NOT_LOCKED - } tuner_lock_status_t, *ptuner_lock_status_t; - - typedef struct { - - char *name; /* Tuner brand & type name */ - s32 min_freq_rf; /* Lowest RF input frequency, in kHz */ - s32 max_freq_rf; /* Highest RF input frequency, in kHz */ - - u8 sub_mode; /* Index to sub-mode in use */ - ptuner_sub_mode_t sub_modeDescriptions; /* Pointer to description of sub-modes */ - u8 sub_modes; /* Number of available sub-modes */ - - /* The following fields will be either 0, NULL or false and do not need - initialisation */ - void *self_check; /* gives proof of initialization */ - bool programmed; /* only valid if self_check is OK */ - s32 r_ffrequency; /* only valid if programmed */ - s32 i_ffrequency; /* only valid if programmed */ - - void *myUser_data; /* pointer to associated demod instance */ - u16 my_capabilities; /* value for storing application flags */ - - } tuner_common_attr_t, *ptuner_common_attr_t; - -/* -* Generic functions for DRX devices. -*/ - typedef struct tuner_instance_s *p_tuner_instance_t; - - typedef drx_status_t(*tuner_open_func_t) (p_tuner_instance_t tuner); - typedef drx_status_t(*tuner_close_func_t) (p_tuner_instance_t tuner); - - typedef drx_status_t(*tuner_set_frequency_func_t) (p_tuner_instance_t tuner, - tuner_mode_t mode, - s32 - frequency); - - typedef drx_status_t(*tuner_get_frequency_func_t) (p_tuner_instance_t tuner, - tuner_mode_t mode, - s32 * - r_ffrequency, - s32 * - i_ffrequency); - - typedef drx_status_t(*tuner_lock_status_func_t) (p_tuner_instance_t tuner, - ptuner_lock_status_t - lock_stat); - - typedef drx_status_t(*tune_ri2c_write_read_func_t) (p_tuner_instance_t tuner, - struct i2c_device_addr * - w_dev_addr, u16 w_count, - u8 *wData, - struct i2c_device_addr * - r_dev_addr, u16 r_count, - u8 *r_data); - - typedef struct { - tuner_open_func_t open_func; - tuner_close_func_t close_func; - tuner_set_frequency_func_t set_frequency_func; - tuner_get_frequency_func_t get_frequency_func; - tuner_lock_status_func_t lock_statusFunc; - tune_ri2c_write_read_func_t i2c_write_read_func; - - } tuner_func_t, *ptuner_func_t; - - typedef struct tuner_instance_s { - - struct i2c_device_addr my_i2c_dev_addr; - ptuner_common_attr_t my_common_attr; - void *my_ext_attr; - ptuner_func_t my_funct; - - } tuner_instance_t; - -/*------------------------------------------------------------------------------ -ENUM -------------------------------------------------------------------------------*/ - -/*------------------------------------------------------------------------------ -STRUCTS -------------------------------------------------------------------------------*/ - -/*------------------------------------------------------------------------------ -Exported FUNCTIONS -------------------------------------------------------------------------------*/ - - drx_status_t drxbsp_tuner_open(p_tuner_instance_t tuner); - - drx_status_t drxbsp_tuner_close(p_tuner_instance_t tuner); - - drx_status_t drxbsp_tuner_set_frequency(p_tuner_instance_t tuner, - tuner_mode_t mode, - s32 frequency); - - drx_status_t drxbsp_tuner_get_frequency(p_tuner_instance_t tuner, - tuner_mode_t mode, - s32 *r_ffrequency, - s32 *i_ffrequency); - - drx_status_t drxbsp_tuner_lock_status(p_tuner_instance_t tuner, - ptuner_lock_status_t lock_stat); - - drx_status_t drxbsp_tuner_default_i2c_write_read(p_tuner_instance_t tuner, - struct i2c_device_addr *w_dev_addr, - u16 w_count, - u8 *wData, - struct i2c_device_addr *r_dev_addr, - u16 r_count, u8 *r_data); - -/*------------------------------------------------------------------------------ -THE END -------------------------------------------------------------------------------*/ -#ifdef __cplusplus -} -#endif -#endif /* __DRXBSP_TUNER_H__ */ -/* End of file */ -- cgit v1.1 From 1bfc9e15a10ae88eb94cba17dba4d31941f5d939 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Thu, 16 Jan 2014 12:51:36 -0300 Subject: [media] drx-j: get rid of typedefs in drx_driver.h Most of the changes were done with scripts like: for i in drivers/media/dvb-frontends/drx39xyj/*.[ch]; do perl -ne '$var = "drx_sig_quality"; s,\b($var)_t\s+,struct \1 ,g; s,\bp_*($var)_t\s+,struct \1 *,g; s,\b($var)_t\b,struct \1,g; s,\bp_*($var)_t\b,struct \1 *,g; print $_' <$i >a && mv a $i; done Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drx39xxj.c | 50 +- drivers/media/dvb-frontends/drx39xyj/drx39xxj.h | 2 +- .../media/dvb-frontends/drx39xyj/drx_dap_fasi.c | 120 +-- .../media/dvb-frontends/drx39xyj/drx_dap_fasi.h | 2 +- drivers/media/dvb-frontends/drx39xyj/drx_driver.c | 110 +- drivers/media/dvb-frontends/drx39xyj/drx_driver.h | 1060 +++++++++----------- drivers/media/dvb-frontends/drx39xyj/drxj.c | 746 +++++++------- drivers/media/dvb-frontends/drx39xyj/drxj.h | 28 +- 8 files changed, 999 insertions(+), 1119 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c index d32bab0..837bb64 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c @@ -33,9 +33,9 @@ static int drx39xxj_set_powerstate(struct dvb_frontend *fe, int enable) { struct drx39xxj_state *state = fe->demodulator_priv; - drx_demod_instance_t *demod = state->demod; + struct drx_demod_instance *demod = state->demod; int result; - drx_power_mode_t power_mode; + enum drx_power_mode power_mode; if (enable) power_mode = DRX_POWER_UP; @@ -55,9 +55,9 @@ static int drx39xxj_set_powerstate(struct dvb_frontend *fe, int enable) static int drx39xxj_read_status(struct dvb_frontend *fe, fe_status_t *status) { struct drx39xxj_state *state = fe->demodulator_priv; - drx_demod_instance_t *demod = state->demod; + struct drx_demod_instance *demod = state->demod; int result; - drx_lock_status_t lock_status; + enum drx_lock_status lock_status; *status = 0; @@ -102,9 +102,9 @@ static int drx39xxj_read_status(struct dvb_frontend *fe, fe_status_t *status) static int drx39xxj_read_ber(struct dvb_frontend *fe, u32 *ber) { struct drx39xxj_state *state = fe->demodulator_priv; - drx_demod_instance_t *demod = state->demod; + struct drx_demod_instance *demod = state->demod; int result; - drx_sig_quality_t sig_quality; + struct drx_sig_quality sig_quality; result = drx_ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); if (result != DRX_STS_OK) { @@ -121,9 +121,9 @@ static int drx39xxj_read_signal_strength(struct dvb_frontend *fe, u16 *strength) { struct drx39xxj_state *state = fe->demodulator_priv; - drx_demod_instance_t *demod = state->demod; + struct drx_demod_instance *demod = state->demod; int result; - drx_sig_quality_t sig_quality; + struct drx_sig_quality sig_quality; result = drx_ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); if (result != DRX_STS_OK) { @@ -140,9 +140,9 @@ static int drx39xxj_read_signal_strength(struct dvb_frontend *fe, static int drx39xxj_read_snr(struct dvb_frontend *fe, u16 *snr) { struct drx39xxj_state *state = fe->demodulator_priv; - drx_demod_instance_t *demod = state->demod; + struct drx_demod_instance *demod = state->demod; int result; - drx_sig_quality_t sig_quality; + struct drx_sig_quality sig_quality; result = drx_ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); if (result != DRX_STS_OK) { @@ -158,9 +158,9 @@ static int drx39xxj_read_snr(struct dvb_frontend *fe, u16 *snr) static int drx39xxj_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) { struct drx39xxj_state *state = fe->demodulator_priv; - drx_demod_instance_t *demod = state->demod; + struct drx_demod_instance *demod = state->demod; int result; - drx_sig_quality_t sig_quality; + struct drx_sig_quality sig_quality; result = drx_ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); if (result != DRX_STS_OK) { @@ -180,12 +180,12 @@ static int drx39xxj_set_frontend(struct dvb_frontend *fe) #endif struct dtv_frontend_properties *p = &fe->dtv_property_cache; struct drx39xxj_state *state = fe->demodulator_priv; - drx_demod_instance_t *demod = state->demod; + struct drx_demod_instance *demod = state->demod; enum drx_standard standard = DRX_STANDARD_8VSB; - drx_channel_t channel; + struct drx_channel channel; int result; - drxuio_data_t uio_data; - drx_channel_t def_channel = { /* frequency */ 0, + struct drxuio_data uio_data; + struct drx_channel def_channel = { /* frequency */ 0, /* bandwidth */ DRX_BANDWIDTH_6MHZ, /* mirror */ DRX_MIRROR_NO, /* constellation */ DRX_CONSTELLATION_AUTO, @@ -268,7 +268,7 @@ static int drx39xxj_sleep(struct dvb_frontend *fe) static int drx39xxj_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) { struct drx39xxj_state *state = fe->demodulator_priv; - drx_demod_instance_t *demod = state->demod; + struct drx_demod_instance *demod = state->demod; bool i2c_gate_state; int result; @@ -326,11 +326,11 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) struct drx39xxj_state *state = NULL; struct i2c_device_addr *demod_addr = NULL; - drx_common_attr_t *demod_comm_attr = NULL; + struct drx_common_attr *demod_comm_attr = NULL; drxj_data_t *demod_ext_attr = NULL; - drx_demod_instance_t *demod = NULL; - drxuio_cfg_t uio_cfg; - drxuio_data_t uio_data; + struct drx_demod_instance *demod = NULL; + struct drxuio_cfg uio_cfg; + struct drxuio_data uio_data; int result; /* allocate memory for the internal state */ @@ -338,7 +338,7 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) if (state == NULL) goto error; - demod = kmalloc(sizeof(drx_demod_instance_t), GFP_KERNEL); + demod = kmalloc(sizeof(struct drx_demod_instance), GFP_KERNEL); if (demod == NULL) goto error; @@ -346,7 +346,7 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) if (demod_addr == NULL) goto error; - demod_comm_attr = kmalloc(sizeof(drx_common_attr_t), GFP_KERNEL); + demod_comm_attr = kmalloc(sizeof(struct drx_common_attr), GFP_KERNEL); if (demod_comm_attr == NULL) goto error; @@ -358,7 +358,7 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) state->i2c = i2c; state->demod = demod; - memcpy(demod, &drxj_default_demod_g, sizeof(drx_demod_instance_t)); + memcpy(demod, &drxj_default_demod_g, sizeof(struct drx_demod_instance)); demod->my_i2c_dev_addr = demod_addr; memcpy(demod->my_i2c_dev_addr, &drxj_default_addr_g, @@ -366,7 +366,7 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) demod->my_i2c_dev_addr->user_data = state; demod->my_common_attr = demod_comm_attr; memcpy(demod->my_common_attr, &drxj_default_comm_attr_g, - sizeof(drx_common_attr_t)); + sizeof(struct drx_common_attr)); demod->my_common_attr->microcode = DRXJ_MC_MAIN; #if 0 demod->my_common_attr->verify_microcode = false; diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h index 622172d..a7eb716 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h @@ -28,7 +28,7 @@ struct drx39xxj_state { struct i2c_adapter *i2c; - drx_demod_instance_t *demod; + struct drx_demod_instance *demod; enum drx_standard current_standard; struct dvb_frontend frontend; int powered_up:1; diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c index 9e9556b..3f33b13 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c @@ -56,62 +56,62 @@ /* Function prototypes */ static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr, /* address of I2C device */ - dr_xaddr_t addr, /* address of register/memory */ + u32 addr, /* address of register/memory */ u16 datasize, /* size of data */ u8 *data, /* data to send */ - dr_xflags_t flags); /* special device flags */ + u32 flags); /* special device flags */ static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr, /* address of I2C device */ - dr_xaddr_t addr, /* address of register/memory */ + u32 addr, /* address of register/memory */ u16 datasize, /* size of data */ u8 *data, /* data to send */ - dr_xflags_t flags); /* special device flags */ + u32 flags); /* special device flags */ static int drxdap_fasi_write_reg8(struct i2c_device_addr *dev_addr, /* address of I2C device */ - dr_xaddr_t addr, /* address of register */ + u32 addr, /* address of register */ u8 data, /* data to write */ - dr_xflags_t flags); /* special device flags */ + u32 flags); /* special device flags */ static int drxdap_fasi_read_reg8(struct i2c_device_addr *dev_addr, /* address of I2C device */ - dr_xaddr_t addr, /* address of register */ + u32 addr, /* address of register */ u8 *data, /* buffer to receive data */ - dr_xflags_t flags); /* special device flags */ + u32 flags); /* special device flags */ static int drxdap_fasi_read_modify_write_reg8(struct i2c_device_addr *dev_addr, /* address of I2C device */ - dr_xaddr_t waddr, /* address of register */ - dr_xaddr_t raddr, /* address to read back from */ + u32 waddr, /* address of register */ + u32 raddr, /* address to read back from */ u8 datain, /* data to send */ u8 *dataout); /* data to receive back */ static int drxdap_fasi_write_reg16(struct i2c_device_addr *dev_addr, /* address of I2C device */ - dr_xaddr_t addr, /* address of register */ + u32 addr, /* address of register */ u16 data, /* data to write */ - dr_xflags_t flags); /* special device flags */ + u32 flags); /* special device flags */ static int drxdap_fasi_read_reg16(struct i2c_device_addr *dev_addr, /* address of I2C device */ - dr_xaddr_t addr, /* address of register */ + u32 addr, /* address of register */ u16 *data, /* buffer to receive data */ - dr_xflags_t flags); /* special device flags */ + u32 flags); /* special device flags */ static int drxdap_fasi_read_modify_write_reg16(struct i2c_device_addr *dev_addr, /* address of I2C device */ - dr_xaddr_t waddr, /* address of register */ - dr_xaddr_t raddr, /* address to read back from */ + u32 waddr, /* address of register */ + u32 raddr, /* address to read back from */ u16 datain, /* data to send */ u16 *dataout); /* data to receive back */ static int drxdap_fasi_write_reg32(struct i2c_device_addr *dev_addr, /* address of I2C device */ - dr_xaddr_t addr, /* address of register */ + u32 addr, /* address of register */ u32 data, /* data to write */ - dr_xflags_t flags); /* special device flags */ + u32 flags); /* special device flags */ static int drxdap_fasi_read_reg32(struct i2c_device_addr *dev_addr, /* address of I2C device */ - dr_xaddr_t addr, /* address of register */ + u32 addr, /* address of register */ u32 *data, /* buffer to receive data */ - dr_xflags_t flags); /* special device flags */ + u32 flags); /* special device flags */ static int drxdap_fasi_read_modify_write_reg32(struct i2c_device_addr *dev_addr, /* address of I2C device */ - dr_xaddr_t waddr, /* address of register */ - dr_xaddr_t raddr, /* address to read back from */ + u32 waddr, /* address of register */ + u32 raddr, /* address to read back from */ u32 datain, /* data to send */ u32 *dataout); /* data to receive back */ @@ -119,7 +119,7 @@ static int drxdap_fasi_read_modify_write_reg32(struct i2c_device_addr *dev_addr, char drx_dap_fasi_module_name[] = "FASI Data Access Protocol"; char drx_dap_fasi_version_text[] = ""; -drx_version_t drx_dap_fasi_version = { +struct drx_version drx_dap_fasi_version = { DRX_MODULE_DAP, /**< type identifier of the module */ drx_dap_fasi_module_name, /**< name or description of module */ @@ -130,7 +130,7 @@ drx_version_t drx_dap_fasi_version = { }; /* The structure containing the protocol interface */ -drx_access_func_t drx_dap_fasi_funct_g = { +struct drx_access_func drx_dap_fasi_funct_g = { &drx_dap_fasi_version, drxdap_fasi_write_block, /* Supported */ drxdap_fasi_read_block, /* Supported */ @@ -150,24 +150,24 @@ drx_access_func_t drx_dap_fasi_funct_g = { /* Functions not supported by protocol*/ static int drxdap_fasi_write_reg8(struct i2c_device_addr *dev_addr, /* address of I2C device */ - dr_xaddr_t addr, /* address of register */ + u32 addr, /* address of register */ u8 data, /* data to write */ - dr_xflags_t flags) + u32 flags) { /* special device flags */ return DRX_STS_ERROR; } static int drxdap_fasi_read_reg8(struct i2c_device_addr *dev_addr, /* address of I2C device */ - dr_xaddr_t addr, /* address of register */ + u32 addr, /* address of register */ u8 *data, /* buffer to receive data */ - dr_xflags_t flags) + u32 flags) { /* special device flags */ return DRX_STS_ERROR; } static int drxdap_fasi_read_modify_write_reg8(struct i2c_device_addr *dev_addr, /* address of I2C device */ - dr_xaddr_t waddr, /* address of register */ - dr_xaddr_t raddr, /* address to read back from */ + u32 waddr, /* address of register */ + u32 raddr, /* address to read back from */ u8 datain, /* data to send */ u8 *dataout) { /* data to receive back */ @@ -175,8 +175,8 @@ static int drxdap_fasi_read_modify_write_reg8(struct i2c_device_addr *dev_addr, } static int drxdap_fasi_read_modify_write_reg32(struct i2c_device_addr *dev_addr, /* address of I2C device */ - dr_xaddr_t waddr, /* address of register */ - dr_xaddr_t raddr, /* address to read back from */ + u32 waddr, /* address of register */ + u32 raddr, /* address to read back from */ u32 datain, /* data to send */ u32 *dataout) { /* data to receive back */ @@ -189,10 +189,10 @@ static int drxdap_fasi_read_modify_write_reg32(struct i2c_device_addr *dev_addr, * * int drxdap_fasi_read_block ( * struct i2c_device_addr *dev_addr, -- address of I2C device -* dr_xaddr_t addr, -- address of chip register/memory +* u32 addr, -- address of chip register/memory * u16 datasize, -- number of bytes to read * u8 *data, -- data to receive -* dr_xflags_t flags) -- special device flags +* u32 flags) -- special device flags * * Read block data from chip address. Because the chip is word oriented, * the number of bytes to read must be even. @@ -211,9 +211,9 @@ static int drxdap_fasi_read_modify_write_reg32(struct i2c_device_addr *dev_addr, ******************************/ static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr, - dr_xaddr_t addr, + u32 addr, u16 datasize, - u8 *data, dr_xflags_t flags) + u8 *data, u32 flags) { u8 buf[4]; u16 bufx; @@ -304,8 +304,8 @@ static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr, * * int drxdap_fasi_read_modify_write_reg16 ( * struct i2c_device_addr *dev_addr, -- address of I2C device -* dr_xaddr_t waddr, -- address of chip register/memory -* dr_xaddr_t raddr, -- chip address to read back from +* u32 waddr, -- address of chip register/memory +* u32 raddr, -- chip address to read back from * u16 wdata, -- data to send * u16 *rdata) -- data to receive back * @@ -326,8 +326,8 @@ static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr, ******************************/ static int drxdap_fasi_read_modify_write_reg16(struct i2c_device_addr *dev_addr, - dr_xaddr_t waddr, - dr_xaddr_t raddr, + u32 waddr, + u32 raddr, u16 wdata, u16 *rdata) { int rc = DRX_STS_ERROR; @@ -350,9 +350,9 @@ static int drxdap_fasi_read_modify_write_reg16(struct i2c_device_addr *dev_addr, * * int drxdap_fasi_read_reg16 ( * struct i2c_device_addr *dev_addr, -- address of I2C device -* dr_xaddr_t addr, -- address of chip register/memory +* u32 addr, -- address of chip register/memory * u16 *data, -- data to receive -* dr_xflags_t flags) -- special device flags +* u32 flags) -- special device flags * * Read one 16-bit register or memory location. The data received back is * converted back to the target platform's endianness. @@ -365,8 +365,8 @@ static int drxdap_fasi_read_modify_write_reg16(struct i2c_device_addr *dev_addr, ******************************/ static int drxdap_fasi_read_reg16(struct i2c_device_addr *dev_addr, - dr_xaddr_t addr, - u16 *data, dr_xflags_t flags) + u32 addr, + u16 *data, u32 flags) { u8 buf[sizeof(*data)]; int rc; @@ -383,9 +383,9 @@ static int drxdap_fasi_read_reg16(struct i2c_device_addr *dev_addr, * * int drxdap_fasi_read_reg32 ( * struct i2c_device_addr *dev_addr, -- address of I2C device -* dr_xaddr_t addr, -- address of chip register/memory +* u32 addr, -- address of chip register/memory * u32 *data, -- data to receive -* dr_xflags_t flags) -- special device flags +* u32 flags) -- special device flags * * Read one 32-bit register or memory location. The data received back is * converted back to the target platform's endianness. @@ -398,8 +398,8 @@ static int drxdap_fasi_read_reg16(struct i2c_device_addr *dev_addr, ******************************/ static int drxdap_fasi_read_reg32(struct i2c_device_addr *dev_addr, - dr_xaddr_t addr, - u32 *data, dr_xflags_t flags) + u32 addr, + u32 *data, u32 flags) { u8 buf[sizeof(*data)]; int rc; @@ -418,10 +418,10 @@ static int drxdap_fasi_read_reg32(struct i2c_device_addr *dev_addr, * * int drxdap_fasi_write_block ( * struct i2c_device_addr *dev_addr, -- address of I2C device -* dr_xaddr_t addr, -- address of chip register/memory +* u32 addr, -- address of chip register/memory * u16 datasize, -- number of bytes to read * u8 *data, -- data to receive -* dr_xflags_t flags) -- special device flags +* u32 flags) -- special device flags * * Write block data to chip address. Because the chip is word oriented, * the number of bytes to write must be even. @@ -437,9 +437,9 @@ static int drxdap_fasi_read_reg32(struct i2c_device_addr *dev_addr, ******************************/ static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr, - dr_xaddr_t addr, + u32 addr, u16 datasize, - u8 *data, dr_xflags_t flags) + u8 *data, u32 flags) { u8 buf[DRXDAP_MAX_WCHUNKSIZE]; int st = DRX_STS_ERROR; @@ -562,9 +562,9 @@ static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr, * * int drxdap_fasi_write_reg16 ( * struct i2c_device_addr *dev_addr, -- address of I2C device -* dr_xaddr_t addr, -- address of chip register/memory +* u32 addr, -- address of chip register/memory * u16 data, -- data to send -* dr_xflags_t flags) -- special device flags +* u32 flags) -- special device flags * * Write one 16-bit register or memory location. The data being written is * converted from the target platform's endianness to little endian. @@ -576,8 +576,8 @@ static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr, ******************************/ static int drxdap_fasi_write_reg16(struct i2c_device_addr *dev_addr, - dr_xaddr_t addr, - u16 data, dr_xflags_t flags) + u32 addr, + u16 data, u32 flags) { u8 buf[sizeof(data)]; @@ -591,9 +591,9 @@ static int drxdap_fasi_write_reg16(struct i2c_device_addr *dev_addr, * * int drxdap_fasi_write_reg32 ( * struct i2c_device_addr *dev_addr, -- address of I2C device -* dr_xaddr_t addr, -- address of chip register/memory +* u32 addr, -- address of chip register/memory * u32 data, -- data to send -* dr_xflags_t flags) -- special device flags +* u32 flags) -- special device flags * * Write one 32-bit register or memory location. The data being written is * converted from the target platform's endianness to little endian. @@ -605,8 +605,8 @@ static int drxdap_fasi_write_reg16(struct i2c_device_addr *dev_addr, ******************************/ static int drxdap_fasi_write_reg32(struct i2c_device_addr *dev_addr, - dr_xaddr_t addr, - u32 data, dr_xflags_t flags) + u32 addr, + u32 data, u32 flags) { u8 buf[sizeof(data)]; diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.h b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.h index 02b2c30..4151876 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.h @@ -238,7 +238,7 @@ extern "C" { #endif - extern drx_access_func_t drx_dap_fasi_funct_g; + extern struct drx_access_func drx_dap_fasi_funct_g; #define DRXDAP_FASI_RMW 0x10000000 #define DRXDAP_FASI_BROADCAST 0x20000000 diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c index db92b4f..af894b9 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c @@ -147,21 +147,21 @@ FUNCTIONS /* Prototype of default scanning function */ static int scan_function_default(void *scan_context, - drx_scan_command_t scan_command, - pdrx_channel_t scan_channel, bool *get_next_channel); + enum drx_scan_command scan_command, + struct drx_channel *scan_channel, bool *get_next_channel); /** * \brief Get pointer to scanning function. * \param demod: Pointer to demodulator instance. * \return drx_scan_func_t. */ -static drx_scan_func_t get_scan_function(pdrx_demod_instance_t demod) +static drx_scan_func_t get_scan_function(struct drx_demod_instance *demod) { - pdrx_common_attr_t common_attr = (pdrx_common_attr_t) (NULL); + struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL); drx_scan_func_t scan_func = (drx_scan_func_t) (NULL); /* get scan function from common attributes */ - common_attr = (pdrx_common_attr_t) demod->my_common_attr; + common_attr = (struct drx_common_attr *) demod->my_common_attr; scan_func = common_attr->scan_function; if (scan_func != NULL) { @@ -178,12 +178,12 @@ static drx_scan_func_t get_scan_function(pdrx_demod_instance_t demod) * \param scan_context: Context Pointer. * \return drx_scan_func_t. */ -static void *get_scan_context(pdrx_demod_instance_t demod, void *scan_context) +static void *get_scan_context(struct drx_demod_instance *demod, void *scan_context) { - pdrx_common_attr_t common_attr = (pdrx_common_attr_t) (NULL); + struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL); /* get scan function from common attributes */ - common_attr = (pdrx_common_attr_t) demod->my_common_attr; + common_attr = (struct drx_common_attr *) demod->my_common_attr; scan_context = common_attr->scan_context; if (scan_context == NULL) { @@ -211,11 +211,11 @@ static void *get_scan_context(pdrx_demod_instance_t demod, void *scan_context) * In case DRX_NEVER_LOCK is returned the poll-wait will be aborted. * */ -static int scan_wait_for_lock(pdrx_demod_instance_t demod, bool *is_locked) +static int scan_wait_for_lock(struct drx_demod_instance *demod, bool *is_locked) { bool done_waiting = false; - drx_lock_status_t lock_state = DRX_NOT_LOCKED; - drx_lock_status_t desired_lock_state = DRX_NOT_LOCKED; + enum drx_lock_status lock_state = DRX_NOT_LOCKED; + enum drx_lock_status desired_lock_state = DRX_NOT_LOCKED; u32 timeout_value = 0; u32 start_time_lock_stage = 0; u32 current_time = 0; @@ -273,17 +273,17 @@ static int scan_wait_for_lock(pdrx_demod_instance_t demod, bool *is_locked) * */ static int -scan_prepare_next_scan(pdrx_demod_instance_t demod, s32 skip) +scan_prepare_next_scan(struct drx_demod_instance *demod, s32 skip) { - pdrx_common_attr_t common_attr = (pdrx_common_attr_t) (NULL); + struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL); u16 table_index = 0; u16 frequency_plan_size = 0; - p_drx_frequency_plan_t frequency_plan = (p_drx_frequency_plan_t) (NULL); + struct drx_frequency_plan *frequency_plan = (struct drx_frequency_plan *) (NULL); s32 next_frequency = 0; s32 tuner_min_frequency = 0; s32 tuner_max_frequency = 0; - common_attr = (pdrx_common_attr_t) demod->my_common_attr; + common_attr = (struct drx_common_attr *) demod->my_common_attr; table_index = common_attr->scan_freq_plan_index; frequency_plan = common_attr->scan_param->frequency_plan; next_frequency = common_attr->scan_next_frequency; @@ -355,14 +355,14 @@ scan_prepare_next_scan(pdrx_demod_instance_t demod, s32 skip) */ static int scan_function_default(void *scan_context, - drx_scan_command_t scan_command, - pdrx_channel_t scan_channel, bool *get_next_channel) + enum drx_scan_command scan_command, + struct drx_channel *scan_channel, bool *get_next_channel) { - pdrx_demod_instance_t demod = NULL; + struct drx_demod_instance *demod = NULL; int status = DRX_STS_ERROR; bool is_locked = false; - demod = (pdrx_demod_instance_t) scan_context; + demod = (struct drx_demod_instance *) scan_context; if (scan_command != DRX_SCAN_COMMAND_NEXT) { /* just return OK if not doing "scan next" */ @@ -412,21 +412,21 @@ scan_function_default(void *scan_context, * */ static int -ctrl_scan_init(pdrx_demod_instance_t demod, p_drx_scan_param_t scan_param) +ctrl_scan_init(struct drx_demod_instance *demod, struct drx_scan_param *scan_param) { int status = DRX_STS_ERROR; - pdrx_common_attr_t common_attr = (pdrx_common_attr_t) (NULL); + struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL); s32 max_tuner_freq = 0; s32 min_tuner_freq = 0; u16 nr_channels_in_plan = 0; u16 i = 0; void *scan_context = NULL; - common_attr = (pdrx_common_attr_t) demod->my_common_attr; + common_attr = (struct drx_common_attr *) demod->my_common_attr; common_attr->scan_active = true; /* invalidate a previous SCAN_INIT */ - common_attr->scan_param = (p_drx_scan_param_t) (NULL); + common_attr->scan_param = NULL; common_attr->scan_next_frequency = 0; /* Check parameters */ @@ -551,13 +551,13 @@ ctrl_scan_init(pdrx_demod_instance_t demod, p_drx_scan_param_t scan_param) * \retval DRX_STS_ERROR: Something went wrong. * \retval DRX_STS_INVALID_ARG: Wrong parameters. */ -static int ctrl_scan_stop(pdrx_demod_instance_t demod) +static int ctrl_scan_stop(struct drx_demod_instance *demod) { int status = DRX_STS_ERROR; - pdrx_common_attr_t common_attr = (pdrx_common_attr_t) (NULL); + struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL); void *scan_context = NULL; - common_attr = (pdrx_common_attr_t) demod->my_common_attr; + common_attr = (struct drx_common_attr *) demod->my_common_attr; common_attr->scan_active = true; if ((common_attr->scan_param == NULL) || @@ -601,15 +601,15 @@ static int ctrl_scan_stop(pdrx_demod_instance_t demod) * Progress indication will run from 0 upto DRX_SCAN_MAX_PROGRESS during scan. * */ -static int ctrl_scan_next(pdrx_demod_instance_t demod, u16 *scan_progress) +static int ctrl_scan_next(struct drx_demod_instance *demod, u16 *scan_progress) { - pdrx_common_attr_t common_attr = (pdrx_common_attr_t) (NULL); + struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL); bool *scan_ready = (bool *)(NULL); u16 max_progress = DRX_SCAN_MAX_PROGRESS; u32 num_tries = 0; u32 i = 0; - common_attr = (pdrx_common_attr_t) demod->my_common_attr; + common_attr = (struct drx_common_attr *) demod->my_common_attr; /* Check scan parameters */ if (scan_progress == NULL) { @@ -635,9 +635,9 @@ static int ctrl_scan_next(pdrx_demod_instance_t demod, u16 *scan_progress) scan_ready = &(common_attr->scan_ready); for (i = 0; ((i < num_tries) && ((*scan_ready) == false)); i++) { - drx_channel_t scan_channel = { 0 }; + struct drx_channel scan_channel = { 0 }; int status = DRX_STS_ERROR; - p_drx_frequency_plan_t freq_plan = (p_drx_frequency_plan_t) (NULL); + struct drx_frequency_plan *freq_plan = (struct drx_frequency_plan *) (NULL); bool next_channel = false; void *scan_context = NULL; @@ -728,9 +728,9 @@ static int ctrl_scan_next(pdrx_demod_instance_t demod, u16 *scan_progress) * */ static int -ctrl_program_tuner(pdrx_demod_instance_t demod, pdrx_channel_t channel) +ctrl_program_tuner(struct drx_demod_instance *demod, struct drx_channel *channel) { - pdrx_common_attr_t common_attr = (pdrx_common_attr_t) (NULL); + struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL); enum drx_standard standard = DRX_STANDARD_UNKNOWN; u32 tuner_mode = 0; int status = DRX_STS_ERROR; @@ -742,7 +742,7 @@ ctrl_program_tuner(pdrx_demod_instance_t demod, pdrx_channel_t channel) return DRX_STS_INVALID_ARG; } - common_attr = (pdrx_common_attr_t) demod->my_common_attr; + common_attr = (struct drx_common_attr *) demod->my_common_attr; /* select analog or digital tuner mode based on current standard */ if (drx_ctrl(demod, DRX_CTRL_GET_STANDARD, &standard) != DRX_STS_OK) { @@ -839,8 +839,8 @@ ctrl_program_tuner(pdrx_demod_instance_t demod, pdrx_channel_t channel) * \retval DRX_STS_INVALID_ARG: Wrong parameters. * */ -static int ctrl_dump_registers(pdrx_demod_instance_t demod, - p_drx_reg_dump_t registers) +static int ctrl_dump_registers(struct drx_demod_instance *demod, + struct drx_reg_dump *registers) { u16 i = 0; @@ -982,8 +982,8 @@ static u16 u_code_compute_crc(u8 *block_data, u16 nr_words) * - Provided image is corrupt */ static int -ctrl_u_code(pdrx_demod_instance_t demod, - p_drxu_code_info_t mc_info, drxu_code_action_t action) +ctrl_u_code(struct drx_demod_instance *demod, + struct drxu_code_info *mc_info, enum drxu_code_action action) { int rc; u16 i = 0; @@ -1123,7 +1123,7 @@ ctrl_u_code(pdrx_demod_instance_t demod, [DRX_UCODE_MAX_BUF_SIZE]; u32 bytes_to_compare = 0; u32 bytes_left_to_compare = 0; - dr_xaddr_t curr_addr = (dr_xaddr_t) 0; + u32 curr_addr = (dr_xaddr_t) 0; u8 *curr_ptr = NULL; bytes_left_to_compare = mc_block_nr_bytes; @@ -1202,16 +1202,16 @@ ctrl_u_code(pdrx_demod_instance_t demod, * \retval DRX_STS_INVALID_ARG: Invalid arguments. */ static int -ctrl_version(pdrx_demod_instance_t demod, p_drx_version_list_t *version_list) +ctrl_version(struct drx_demod_instance *demod, struct drx_version_list **version_list) { static char drx_driver_core_module_name[] = "Core driver"; static char drx_driver_core_version_text[] = DRX_VERSIONSTRING(VERSION_MAJOR, VERSION_MINOR, VERSION_PATCH); - static drx_version_t drx_driver_core_version; - static drx_version_list_t drx_driver_core_versionList; + static struct drx_version drx_driver_core_version; + static struct drx_version_list drx_driver_core_versionList; - p_drx_version_list_t demod_version_list = (p_drx_version_list_t) (NULL); + struct drx_version_list *demod_version_list = (struct drx_version_list *) (NULL); int return_status = DRX_STS_ERROR; /* Check arguments */ @@ -1234,13 +1234,13 @@ ctrl_version(pdrx_demod_instance_t demod, p_drx_version_list_t *version_list) drx_driver_core_version.v_string = drx_driver_core_version_text; drx_driver_core_versionList.version = &drx_driver_core_version; - drx_driver_core_versionList.next = (p_drx_version_list_t) (NULL); + drx_driver_core_versionList.next = (struct drx_version_list *) (NULL); if ((return_status == DRX_STS_OK) && (demod_version_list != NULL)) { /* Append versioninfo from driver to versioninfo from demod */ /* Return version info in "bottom-up" order. This way, multiple devices can be handled without using malloc. */ - p_drx_version_list_t current_list_element = demod_version_list; + struct drx_version_list *current_list_element = demod_version_list; while (current_list_element->next != NULL) { current_list_element = current_list_element->next; } @@ -1271,7 +1271,7 @@ ctrl_version(pdrx_demod_instance_t demod, p_drx_version_list_t *version_list) * */ -int drx_init(pdrx_demod_instance_t demods[]) +int drx_init(struct drx_demod_instance *demods[]) { return DRX_STS_OK; } @@ -1305,7 +1305,7 @@ int drx_term(void) * */ -int drx_open(pdrx_demod_instance_t demod) +int drx_open(struct drx_demod_instance *demod) { int status = DRX_STS_OK; @@ -1342,7 +1342,7 @@ int drx_open(pdrx_demod_instance_t demod) * Put device into sleep mode. */ -int drx_close(pdrx_demod_instance_t demod) +int drx_close(struct drx_demod_instance *demod) { int status = DRX_STS_OK; @@ -1383,7 +1383,7 @@ int drx_close(pdrx_demod_instance_t demod) */ int -drx_ctrl(pdrx_demod_instance_t demod, u32 ctrl, void *ctrl_data) +drx_ctrl(struct drx_demod_instance *demod, u32 ctrl, void *ctrl_data) { int status = DRX_STS_ERROR; @@ -1420,7 +1420,7 @@ drx_ctrl(pdrx_demod_instance_t demod, u32 ctrl, void *ctrl_data) /*======================================================================*/ case DRX_CTRL_VERSION: - return ctrl_version(demod, (p_drx_version_list_t *)ctrl_data); + return ctrl_version(demod, (struct drx_version_list **)ctrl_data); break; /*======================================================================*/ @@ -1438,7 +1438,7 @@ drx_ctrl(pdrx_demod_instance_t demod, u32 ctrl, void *ctrl_data) /*===================================================================*/ case DRX_CTRL_LOAD_UCODE: return ctrl_u_code(demod, - (p_drxu_code_info_t) ctrl_data, + (struct drxu_code_info *)ctrl_data, UCODE_UPLOAD); break; @@ -1446,7 +1446,7 @@ drx_ctrl(pdrx_demod_instance_t demod, u32 ctrl, void *ctrl_data) case DRX_CTRL_VERIFY_UCODE: { return ctrl_u_code(demod, - (p_drxu_code_info_t) ctrl_data, + (struct drxu_code_info *)ctrl_data, UCODE_VERIFY); } break; @@ -1456,7 +1456,7 @@ drx_ctrl(pdrx_demod_instance_t demod, u32 ctrl, void *ctrl_data) case DRX_CTRL_SCAN_INIT: { return ctrl_scan_init(demod, - (p_drx_scan_param_t) ctrl_data); + (struct drx_scan_param *) ctrl_data); } break; @@ -1479,7 +1479,7 @@ drx_ctrl(pdrx_demod_instance_t demod, u32 ctrl, void *ctrl_data) case DRX_CTRL_PROGRAM_TUNER: { return ctrl_program_tuner(demod, - (pdrx_channel_t) + (struct drx_channel *) ctrl_data); } break; @@ -1488,7 +1488,7 @@ drx_ctrl(pdrx_demod_instance_t demod, u32 ctrl, void *ctrl_data) case DRX_CTRL_DUMP_REGISTERS: { return ctrl_dump_registers(demod, - (p_drx_reg_dump_t) + (struct drx_reg_dump *) ctrl_data); } break; diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h index ca07a6c..e0316f6 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h @@ -242,7 +242,6 @@ struct tuner_instance { struct tuner_ops *my_funct; }; - int drxbsp_tuner_open(struct tuner_instance *tuner); int drxbsp_tuner_close(struct tuner_instance *tuner); @@ -498,9 +497,9 @@ MACROS /** * \brief Macro to sign extend signed 9 bit value to signed 16 bit value */ -#define DRX_S24TODRXFREQ(x) ((( (u32) x) & 0x00800000UL) ? \ +#define DRX_S24TODRXFREQ(x) ((((u32) x) & 0x00800000UL) ? \ ((s32) \ - (((u32) x) | 0xFF000000) ) : \ + (((u32) x) | 0xFF000000)) : \ ((s32) x)) /** @@ -508,7 +507,7 @@ MACROS */ #define DRX_U16TODRXFREQ(x) ((x & 0x8000) ? \ ((s32) \ - (((u32) x) | 0xFFFF0000) ) : \ + (((u32) x) | 0xFFFF0000)) : \ ((s32) x)) /*------------------------------------------------------------------------- @@ -856,133 +855,141 @@ enum drx_pilot_mode { #define DRX_CTRL_MAX (DRX_CTRL_BASE + 44) /* never to be used */ /** -* \enum drxu_code_action_t -* \brief Used to indicate if firmware has to be uploaded or verified. -*/ - - typedef enum { - UCODE_UPLOAD, - /**< Upload the microcode image to device */ - UCODE_VERIFY - /**< Compare microcode image with code on device */ - } drxu_code_action_t, *pdrxu_code_action_t; + * enum drxu_code_action - indicate if firmware has to be uploaded or verified. + * @UCODE_UPLOAD: Upload the microcode image to device + * @UCODE_VERIFY: Compare microcode image with code on device + */ +enum drxu_code_action { + UCODE_UPLOAD, + UCODE_VERIFY +}; /** -* \enum drx_lock_status_t -* \brief Used to reflect current lock status of demodulator. +* \enum enum drx_lock_status * \brief Used to reflect current lock status of demodulator. * * The generic lock states have device dependent semantics. -*/ - typedef enum { + DRX_NEVER_LOCK = 0, - /**< Device will never lock on this signal */ + **< Device will never lock on this signal * DRX_NOT_LOCKED, - /**< Device has no lock at all */ + **< Device has no lock at all * DRX_LOCK_STATE_1, - /**< Generic lock state */ + **< Generic lock state * DRX_LOCK_STATE_2, - /**< Generic lock state */ + **< Generic lock state * DRX_LOCK_STATE_3, - /**< Generic lock state */ + **< Generic lock state * DRX_LOCK_STATE_4, - /**< Generic lock state */ + **< Generic lock state * DRX_LOCK_STATE_5, - /**< Generic lock state */ + **< Generic lock state * DRX_LOCK_STATE_6, - /**< Generic lock state */ + **< Generic lock state * DRX_LOCK_STATE_7, - /**< Generic lock state */ + **< Generic lock state * DRX_LOCK_STATE_8, - /**< Generic lock state */ + **< Generic lock state * DRX_LOCK_STATE_9, - /**< Generic lock state */ - DRX_LOCKED /**< Device is in lock */ - } drx_lock_status_t, *pdrx_lock_status_t; - -/** -* \enum DRXUIO_t -* \brief Used to address a User IO (UIO). -*/ - typedef enum { - DRX_UIO1, - DRX_UIO2, - DRX_UIO3, - DRX_UIO4, - DRX_UIO5, - DRX_UIO6, - DRX_UIO7, - DRX_UIO8, - DRX_UIO9, - DRX_UIO10, - DRX_UIO11, - DRX_UIO12, - DRX_UIO13, - DRX_UIO14, - DRX_UIO15, - DRX_UIO16, - DRX_UIO17, - DRX_UIO18, - DRX_UIO19, - DRX_UIO20, - DRX_UIO21, - DRX_UIO22, - DRX_UIO23, - DRX_UIO24, - DRX_UIO25, - DRX_UIO26, - DRX_UIO27, - DRX_UIO28, - DRX_UIO29, - DRX_UIO30, - DRX_UIO31, - DRX_UIO32, - DRX_UIO_MAX = DRX_UIO32 - } DRXUIO_t, *p_drxuio_t; - -/** -* \enum drxuio_mode_t -* \brief Used to configure the modus oprandi of a UIO. + **< Generic lock state * + DRX_LOCKED **< Device is in lock * +*/ + +enum drx_lock_status { + DRX_NEVER_LOCK = 0, + DRX_NOT_LOCKED, + DRX_LOCK_STATE_1, + DRX_LOCK_STATE_2, + DRX_LOCK_STATE_3, + DRX_LOCK_STATE_4, + DRX_LOCK_STATE_5, + DRX_LOCK_STATE_6, + DRX_LOCK_STATE_7, + DRX_LOCK_STATE_8, + DRX_LOCK_STATE_9, + DRX_LOCKED +}; + +/** +* \enum enum drx_uio* \brief Used to address a User IO (UIO). +*/ +enum drx_uio { + DRX_UIO1, + DRX_UIO2, + DRX_UIO3, + DRX_UIO4, + DRX_UIO5, + DRX_UIO6, + DRX_UIO7, + DRX_UIO8, + DRX_UIO9, + DRX_UIO10, + DRX_UIO11, + DRX_UIO12, + DRX_UIO13, + DRX_UIO14, + DRX_UIO15, + DRX_UIO16, + DRX_UIO17, + DRX_UIO18, + DRX_UIO19, + DRX_UIO20, + DRX_UIO21, + DRX_UIO22, + DRX_UIO23, + DRX_UIO24, + DRX_UIO25, + DRX_UIO26, + DRX_UIO27, + DRX_UIO28, + DRX_UIO29, + DRX_UIO30, + DRX_UIO31, + DRX_UIO32, + DRX_UIO_MAX = DRX_UIO32 +}; + +/** +* \enum enum drxuio_mode * \brief Used to configure the modus oprandi of a UIO. * * DRX_UIO_MODE_FIRMWARE is an old uio mode. * It is replaced by the modes DRX_UIO_MODE_FIRMWARE0 .. DRX_UIO_MODE_FIRMWARE9. * To be backward compatible DRX_UIO_MODE_FIRMWARE is equivalent to * DRX_UIO_MODE_FIRMWARE0. */ - typedef enum { - DRX_UIO_MODE_DISABLE = 0x01, - /**< not used, pin is configured as input */ - DRX_UIO_MODE_READWRITE = 0x02, - /**< used for read/write by application */ - DRX_UIO_MODE_FIRMWARE = 0x04, - /**< controlled by firmware, function 0 */ - DRX_UIO_MODE_FIRMWARE0 = DRX_UIO_MODE_FIRMWARE, - /**< same as above */ - DRX_UIO_MODE_FIRMWARE1 = 0x08, - /**< controlled by firmware, function 1 */ - DRX_UIO_MODE_FIRMWARE2 = 0x10, - /**< controlled by firmware, function 2 */ - DRX_UIO_MODE_FIRMWARE3 = 0x20, - /**< controlled by firmware, function 3 */ - DRX_UIO_MODE_FIRMWARE4 = 0x40, - /**< controlled by firmware, function 4 */ - DRX_UIO_MODE_FIRMWARE5 = 0x80 - /**< controlled by firmware, function 5 */ - } drxuio_mode_t, *pdrxuio_mode_t; - -/** -* \enum drxoob_downstream_standard_t -* \brief Used to select OOB standard. +enum drxuio_mode { + DRX_UIO_MODE_DISABLE = 0x01, + /**< not used, pin is configured as input */ + DRX_UIO_MODE_READWRITE = 0x02, + /**< used for read/write by application */ + DRX_UIO_MODE_FIRMWARE = 0x04, + /**< controlled by firmware, function 0 */ + DRX_UIO_MODE_FIRMWARE0 = DRX_UIO_MODE_FIRMWARE, + /**< same as above */ + DRX_UIO_MODE_FIRMWARE1 = 0x08, + /**< controlled by firmware, function 1 */ + DRX_UIO_MODE_FIRMWARE2 = 0x10, + /**< controlled by firmware, function 2 */ + DRX_UIO_MODE_FIRMWARE3 = 0x20, + /**< controlled by firmware, function 3 */ + DRX_UIO_MODE_FIRMWARE4 = 0x40, + /**< controlled by firmware, function 4 */ + DRX_UIO_MODE_FIRMWARE5 = 0x80 + /**< controlled by firmware, function 5 */ +}; + +/** +* \enum enum drxoob_downstream_standard * \brief Used to select OOB standard. * * Based on ANSI 55-1 and 55-2 */ - typedef enum { - DRX_OOB_MODE_A = 0, - /**< ANSI 55-1 */ - DRX_OOB_MODE_B_GRADE_A, - /**< ANSI 55-2 A */ - DRX_OOB_MODE_B_GRADE_B - /**< ANSI 55-2 B */ - } drxoob_downstream_standard_t, *pdrxoob_downstream_standard_t; +enum drxoob_downstream_standard { + DRX_OOB_MODE_A = 0, + /**< ANSI 55-1 */ + DRX_OOB_MODE_B_GRADE_A, + /**< ANSI 55-2 A */ + DRX_OOB_MODE_B_GRADE_B + /**< ANSI 55-2 B */ +}; /*------------------------------------------------------------------------- STRUCTS @@ -994,14 +1001,8 @@ STRUCTS /*============================================================================*/ /*============================================================================*/ -/** -* \enum drx_cfg_type_t -* \brief Generic configuration function identifiers. -*/ - typedef u32 drx_cfg_type_t, *pdrx_cfg_type_t; - #ifndef DRX_CFG_BASE -#define DRX_CFG_BASE ((drx_cfg_type_t)0) +#define DRX_CFG_BASE 0 #endif #define DRX_CFG_MPEG_OUTPUT (DRX_CFG_BASE + 0) /* MPEG TS output */ @@ -1032,17 +1033,16 @@ STRUCTS /*============================================================================*/ /** -* \struct drxu_code_info_t -* \brief Parameters for microcode upload and verfiy. +* \struct struct drxu_code_info * \brief Parameters for microcode upload and verfiy. * * Used by DRX_CTRL_LOAD_UCODE and DRX_CTRL_VERIFY_UCODE */ - typedef struct { - u8 *mc_data; - /**< Pointer to microcode image. */ - u16 mc_size; - /**< Microcode image size. */ - } drxu_code_info_t, *p_drxu_code_info_t; +struct drxu_code_info { + u8 *mc_data; + /**< Pointer to microcode image. */ + u16 mc_size; + /**< Microcode image size. */ +}; /** * \struct drx_mc_version_rec_t @@ -1063,12 +1063,12 @@ STRUCTS */ #define AUX_VER_RECORD 0x8000 - typedef struct { - u16 aux_type; /* type of aux data - 0x8000 for version record */ - u32 mc_dev_type; /* device type, based on JTAG ID */ - u32 mc_version; /* version of microcode */ - u32 mc_base_version; /* in case of patch: the original microcode version */ - } drx_mc_version_rec_t, *pdrx_mc_version_rec_t; +struct drx_mc_version_rec { + u16 aux_type; /* type of aux data - 0x8000 for version record */ + u32 mc_dev_type; /* device type, based on JTAG ID */ + u32 mc_version; /* version of microcode */ + u32 mc_base_version; /* in case of patch: the original microcode version */ +}; /*========================================*/ @@ -1078,186 +1078,140 @@ STRUCTS * * Used by DRX_CTRL_LOAD_FILTER */ - typedef struct { - u8 *data_re; - /**< pointer to coefficients for RE */ - u8 *data_im; - /**< pointer to coefficients for IM */ - u16 size_re; - /**< size of coefficients for RE */ - u16 size_im; - /**< size of coefficients for IM */ - } drx_filter_info_t, *pdrx_filter_info_t; +struct drx_filter_info { + u8 *data_re; + /**< pointer to coefficients for RE */ + u8 *data_im; + /**< pointer to coefficients for IM */ + u16 size_re; + /**< size of coefficients for RE */ + u16 size_im; + /**< size of coefficients for IM */ +}; /*========================================*/ /** -* \struct drx_channel_t -* \brief The set of parameters describing a single channel. +* \struct struct drx_channel * \brief The set of parameters describing a single channel. * * Used by DRX_CTRL_SET_CHANNEL and DRX_CTRL_GET_CHANNEL. * Only certain fields need to be used for a specfic standard. * */ - typedef struct { - s32 frequency; - /**< frequency in kHz */ - enum drx_bandwidth bandwidth; - /**< bandwidth */ - enum drx_mirror mirror; /**< mirrored or not on RF */ - enum drx_modulation constellation; - /**< constellation */ - enum drx_hierarchy hierarchy; - /**< hierarchy */ - enum drx_priority priority; /**< priority */ - enum drx_coderate coderate; /**< coderate */ - enum drx_guard guard; /**< guard interval */ - enum drx_fft_mode fftmode; /**< fftmode */ - enum drx_classification classification; - /**< classification */ - u32 symbolrate; - /**< symbolrate in symbols/sec */ - enum drx_interleave_mode interleavemode; - /**< interleaveMode QAM */ - enum drx_ldpc ldpc; /**< ldpc */ - enum drx_carrier_mode carrier; /**< carrier */ - enum drx_frame_mode framemode; - /**< frame mode */ - enum drx_pilot_mode pilot; /**< pilot mode */ - } drx_channel_t, *pdrx_channel_t; +struct drx_channel { + s32 frequency; + /**< frequency in kHz */ + enum drx_bandwidth bandwidth; + /**< bandwidth */ + enum drx_mirror mirror; /**< mirrored or not on RF */ + enum drx_modulation constellation; + /**< constellation */ + enum drx_hierarchy hierarchy; + /**< hierarchy */ + enum drx_priority priority; /**< priority */ + enum drx_coderate coderate; /**< coderate */ + enum drx_guard guard; /**< guard interval */ + enum drx_fft_mode fftmode; /**< fftmode */ + enum drx_classification classification; + /**< classification */ + u32 symbolrate; + /**< symbolrate in symbols/sec */ + enum drx_interleave_mode interleavemode; + /**< interleaveMode QAM */ + enum drx_ldpc ldpc; /**< ldpc */ + enum drx_carrier_mode carrier; /**< carrier */ + enum drx_frame_mode framemode; + /**< frame mode */ + enum drx_pilot_mode pilot; /**< pilot mode */ +}; /*========================================*/ /** -* \struct drx_sig_quality_t -* Signal quality metrics. +* \struct struct drx_sig_quality * Signal quality metrics. * * Used by DRX_CTRL_SIG_QUALITY. */ - typedef struct { - u16 MER; /**< in steps of 0.1 dB */ - u32 pre_viterbi_ber; - /**< in steps of 1/scale_factor_ber */ - u32 post_viterbi_ber; - /**< in steps of 1/scale_factor_ber */ - u32 scale_factor_ber; - /**< scale factor for BER */ - u16 packet_error; - /**< number of packet errors */ - u32 post_reed_solomon_ber; - /**< in steps of 1/scale_factor_ber */ - u32 pre_ldpc_ber; - /**< in steps of 1/scale_factor_ber */ - u32 aver_iter;/**< in steps of 0.01 */ - u16 indicator; - /**< indicative signal quality low=0..100=high */ - } drx_sig_quality_t, *pdrx_sig_quality_t; - - typedef enum { - DRX_SQI_SPEED_FAST = 0, - DRX_SQI_SPEED_MEDIUM, - DRX_SQI_SPEED_SLOW, - DRX_SQI_SPEED_UNKNOWN = DRX_UNKNOWN - } drx_cfg_sqi_speed_t, *pdrx_cfg_sqi_speed_t; +struct drx_sig_quality { + u16 MER; /**< in steps of 0.1 dB */ + u32 pre_viterbi_ber; + /**< in steps of 1/scale_factor_ber */ + u32 post_viterbi_ber; + /**< in steps of 1/scale_factor_ber */ + u32 scale_factor_ber; + /**< scale factor for BER */ + u16 packet_error; + /**< number of packet errors */ + u32 post_reed_solomon_ber; + /**< in steps of 1/scale_factor_ber */ + u32 pre_ldpc_ber; + /**< in steps of 1/scale_factor_ber */ + u32 aver_iter;/**< in steps of 0.01 */ + u16 indicator; + /**< indicative signal quality low=0..100=high */ +}; + +enum drx_cfg_sqi_speed { + DRX_SQI_SPEED_FAST = 0, + DRX_SQI_SPEED_MEDIUM, + DRX_SQI_SPEED_SLOW, + DRX_SQI_SPEED_UNKNOWN = DRX_UNKNOWN +}; /*========================================*/ /** -* \struct drx_complex_t -* A complex number. +* \struct struct drx_complex * A complex number. * * Used by DRX_CTRL_CONSTEL. */ - typedef struct { - s16 im; - /**< Imaginary part. */ - s16 re; - /**< Real part. */ - } drx_complex_t, *pdrx_complex_t; +struct drx_complex { + s16 im; + /**< Imaginary part. */ + s16 re; + /**< Real part. */ +}; /*========================================*/ /** -* \struct drx_frequency_plan_t -* Array element of a frequency plan. +* \struct struct drx_frequency_plan * Array element of a frequency plan. * * Used by DRX_CTRL_SCAN_INIT. */ - typedef struct { - s32 first; - /**< First centre frequency in this band */ - s32 last; - /**< Last centre frequency in this band */ - s32 step; - /**< Stepping frequency in this band */ - enum drx_bandwidth bandwidth; - /**< Bandwidth within this frequency band */ - u16 ch_number; - /**< First channel number in this band, or first - index in ch_names */ - char **ch_names; - /**< Optional list of channel names in this - band */ - } drx_frequency_plan_t, *p_drx_frequency_plan_t; - -/*========================================*/ - -/** -* \struct drx_frequency_plan_info_t -* Array element of a list of frequency plans. -* -* Used by frequency_plan.h -*/ - typedef struct { - p_drx_frequency_plan_t freq_plan; - int freq_planSize; - char *freq_planName; - } drx_frequency_plan_info_t, *pdrx_frequency_plan_info_t; - -/*========================================*/ - -/** -* /struct drx_scan_data_qam_t -* QAM specific scanning variables -*/ - typedef struct { - u32 *symbolrate; /**< list of symbolrates to scan */ - u16 symbolrate_size; /**< size of symbolrate array */ - enum drx_modulation *constellation; - /**< list of constellations */ - u16 constellation_size; /**< size of constellation array */ - u16 if_agc_threshold; /**< thresholf for IF-AGC based - scanning filter */ - } drx_scan_data_qam_t, *pdrx_scan_data_qam_t; - -/*========================================*/ - -/** -* /struct drx_scan_data_atv_t -* ATV specific scanning variables -*/ - typedef struct { - s16 svr_threshold; - /**< threshold of Sound/Video ratio in 0.1dB steps */ - } drx_scan_data_atv_t, *pdrx_scan_data_atv_t; +struct drx_frequency_plan { + s32 first; + /**< First centre frequency in this band */ + s32 last; + /**< Last centre frequency in this band */ + s32 step; + /**< Stepping frequency in this band */ + enum drx_bandwidth bandwidth; + /**< Bandwidth within this frequency band */ + u16 ch_number; + /**< First channel number in this band, or first + index in ch_names */ + char **ch_names; + /**< Optional list of channel names in this + band */ +}; /*========================================*/ /** -* \struct drx_scan_param_t -* Parameters for channel scan. +* \struct struct drx_scan_param * Parameters for channel scan. * * Used by DRX_CTRL_SCAN_INIT. */ - typedef struct { - p_drx_frequency_plan_t frequency_plan; - /**< Frequency plan (array)*/ - u16 frequency_plan_size; /**< Number of bands */ - u32 num_tries; /**< Max channels tried */ - s32 skip; /**< Minimum frequency step to take - after a channel is found */ - void *ext_params; /**< Standard specific params */ - } drx_scan_param_t, *p_drx_scan_param_t; +struct drx_scan_param { + struct drx_frequency_plan *frequency_plan; + /**< Frequency plan (array)*/ + u16 frequency_plan_size; /**< Number of bands */ + u32 num_tries; /**< Max channels tried */ + s32 skip; /**< Minimum frequency step to take + after a channel is found */ + void *ext_params; /**< Standard specific params */ +}; /*========================================*/ @@ -1265,31 +1219,30 @@ STRUCTS * \brief Scan commands. * Used by scanning algorithms. */ - typedef enum { +enum drx_scan_command { DRX_SCAN_COMMAND_INIT = 0,/**< Initialize scanning */ DRX_SCAN_COMMAND_NEXT, /**< Next scan */ DRX_SCAN_COMMAND_STOP /**< Stop scanning */ - } drx_scan_command_t, *pdrx_scan_command_t; +}; /*========================================*/ /** * \brief Inner scan function prototype. */ - typedef int(*drx_scan_func_t) (void *scan_context, - drx_scan_command_t scan_command, - pdrx_channel_t scan_channel, - bool *get_next_channel); +typedef int(*drx_scan_func_t) (void *scan_context, + enum drx_scan_command scan_command, + struct drx_channel *scan_channel, + bool *get_next_channel); /*========================================*/ /** -* \struct drxtps_info_t -* TPS information, DVB-T specific. +* \struct struct drxtps_info * TPS information, DVB-T specific. * * Used by DRX_CTRL_TPS_INFO. */ - typedef struct { + struct drxtps_info { enum drx_fft_mode fftmode; /**< Fft mode */ enum drx_guard guard; /**< Guard interval */ enum drx_modulation constellation; @@ -1303,7 +1256,7 @@ STRUCTS enum drx_tps_frame frame; /**< Tps frame */ u8 length; /**< Length */ u16 cell_id; /**< Cell id */ - } drxtps_info_t, *pdrxtps_info_t; + }; /*========================================*/ @@ -1312,7 +1265,7 @@ STRUCTS * * Used by DRX_CTRL_SET_POWER_MODE. */ - typedef enum { + enum drx_power_mode { DRX_POWER_UP = 0, /**< Generic , Power Up Mode */ DRX_POWER_MODE_1, @@ -1350,17 +1303,16 @@ STRUCTS /**< Device specific , Power Down Mode */ DRX_POWER_DOWN = 255 /**< Generic , Power Down Mode */ - } drx_power_mode_t, *pdrx_power_mode_t; + }; /*========================================*/ /** -* \enum drx_module_t -* \brief Software module identification. +* \enum enum drx_module * \brief Software module identification. * * Used by DRX_CTRL_VERSION. */ - typedef enum { + enum drx_module { DRX_MODULE_DEVICE, DRX_MODULE_MICROCODE, DRX_MODULE_DRIVERCORE, @@ -1370,16 +1322,15 @@ STRUCTS DRX_MODULE_BSP_TUNER, DRX_MODULE_BSP_HOST, DRX_MODULE_UNKNOWN - } drx_module_t, *pdrx_module_t; + }; /** -* \enum drx_version_t -* \brief Version information of one software module. +* \enum struct drx_version * \brief Version information of one software module. * * Used by DRX_CTRL_VERSION. */ - typedef struct { - drx_module_t module_type; + struct drx_version { + enum drx_module module_type; /**< Type identifier of the module */ char *module_name; /**< Name or description of module */ @@ -1387,19 +1338,18 @@ STRUCTS u16 v_minor; /**< Minor version number */ u16 v_patch; /**< Patch version number */ char *v_string; /**< Version as text string */ - } drx_version_t, *pdrx_version_t; + }; /** -* \enum drx_version_list_t -* \brief List element of NULL terminated, linked list for version information. +* \enum struct drx_version_list * \brief List element of NULL terminated, linked list for version information. * * Used by DRX_CTRL_VERSION. */ - typedef struct drx_version_list_s { - pdrx_version_t version;/**< Version information */ - struct drx_version_list_s *next; - /**< Next list element */ - } drx_version_list_t, *p_drx_version_list_t; +struct drx_version_list { + struct drx_version *version;/**< Version information */ + struct drx_version_list *next; + /**< Next list element */ +}; /*========================================*/ @@ -1408,12 +1358,12 @@ STRUCTS * * Used by DRX_CTRL_UIO_CFG. */ - typedef struct { - DRXUIO_t uio; + struct drxuio_cfg { + enum drx_uio uio; /**< UIO identifier */ - drxuio_mode_t mode; + enum drxuio_mode mode; /**< UIO operational mode */ - } drxuio_cfg_t, *pdrxuio_cfg_t; + }; /*========================================*/ @@ -1422,12 +1372,12 @@ STRUCTS * * Used by DRX_CTRL_UIO_READ and DRX_CTRL_UIO_WRITE. */ - typedef struct { - DRXUIO_t uio; + struct drxuio_data { + enum drx_uio uio; /**< UIO identifier */ bool value; /**< UIO value (true=1, false=0) */ - } drxuio_data_t, *pdrxuio_data_t; + }; /*========================================*/ @@ -1436,13 +1386,13 @@ STRUCTS * * Used by DRX_CTRL_SET_OOB. */ - typedef struct { + struct drxoob { s32 frequency; /**< Frequency in kHz */ - drxoob_downstream_standard_t standard; + enum drxoob_downstream_standard standard; /**< OOB standard */ bool spectrum_inverted; /**< If true, then spectrum is inverted */ - } DRXOOB_t, *p_drxoob_t; + }; /*========================================*/ @@ -1451,12 +1401,12 @@ STRUCTS * * Used by DRX_CTRL_GET_OOB. */ - typedef struct { + struct drxoob_status { s32 frequency; /**< Frequency in Khz */ - drx_lock_status_t lock; /**< Lock status */ + enum drx_lock_status lock; /**< Lock status */ u32 mer; /**< MER */ s32 symbol_rate_offset; /**< Symbolrate offset in ppm */ - } drxoob_status_t, *pdrxoob_status_t; + }; /*========================================*/ @@ -1466,12 +1416,12 @@ STRUCTS * Used by DRX_CTRL_SET_CFG and DRX_CTRL_GET_CFG. * A sort of nested drx_ctrl() functionality for device specific controls. */ - typedef struct { - drx_cfg_type_t cfg_type; + struct drx_cfg { + u32 cfg_type; /**< Function identifier */ void *cfg_data; /**< Function data */ - } drx_cfg_t, *pdrx_cfg_t; + }; /*========================================*/ @@ -1480,21 +1430,20 @@ STRUCTS * MStart width [nr MCLK cycles] for serial MPEG output. */ - typedef enum { + enum drxmpeg_str_width { DRX_MPEG_STR_WIDTH_1, DRX_MPEG_STR_WIDTH_8 - } drxmpeg_str_width_t, *pdrxmpeg_str_width_t; + }; /* CTRL CFG MPEG ouput */ /** -* \struct drx_cfg_mpeg_output_t -* \brief Configuartion parameters for MPEG output control. +* \struct struct drx_cfg_mpeg_output * \brief Configuartion parameters for MPEG output control. * * Used by DRX_CFG_MPEG_OUTPUT, in combination with DRX_CTRL_SET_CFG and * DRX_CTRL_GET_CFG. */ - typedef struct { + struct drx_cfg_mpeg_output { bool enable_mpeg_output;/**< If true, enable MPEG output */ bool insert_rs_byte; /**< If true, insert RS byte */ bool enable_parallel; /**< If true, parallel out otherwise @@ -1510,41 +1459,21 @@ STRUCTS TS */ u32 bitrate; /**< Maximum bitrate in b/s in case static clockrate is selected */ - drxmpeg_str_width_t width_str; + enum drxmpeg_str_width width_str; /**< MPEG start width */ - } drx_cfg_mpeg_output_t, *pdrx_cfg_mpeg_output_t; - -/* CTRL CFG SMA */ -/** -* /struct drx_cfg_smaio_t -* smart antenna i/o. -*/ - typedef enum drx_cfg_smaio_t { - DRX_SMA_OUTPUT = 0, - DRX_SMA_INPUT - } drx_cfg_smaio_t, *pdrx_cfg_smaio_t; + }; -/** -* /struct drx_cfg_sma_t -* Set smart antenna. -*/ - typedef struct { - drx_cfg_smaio_t io; - u16 ctrl_data; - bool smart_ant_inverted; - } drx_cfg_sma_t, *pdrx_cfg_sma_t; /*========================================*/ /** -* \struct drxi2c_data_t -* \brief Data for I2C via 2nd or 3rd or etc I2C port. +* \struct struct drxi2c_data * \brief Data for I2C via 2nd or 3rd or etc I2C port. * * Used by DRX_CTRL_I2C_READWRITE. * If port_nr is equal to primairy port_nr BSPI2C will be used. * */ - typedef struct { + struct drxi2c_data { u16 port_nr; /**< I2C port number */ struct i2c_device_addr *w_dev_addr; /**< Write device address */ @@ -1554,17 +1483,16 @@ STRUCTS /**< Read device address */ u16 r_count; /**< Size of data to read in bytes */ u8 *r_data; /**< Pointer to read buffer */ - } drxi2c_data_t, *pdrxi2c_data_t; + }; /*========================================*/ /** -* \enum drx_aud_standard_t -* \brief Audio standard identifier. +* \enum enum drx_aud_standard * \brief Audio standard identifier. * * Used by DRX_CTRL_SET_AUD. */ - typedef enum { + enum drx_aud_standard { DRX_AUD_STANDARD_BTSC, /**< set BTSC standard (USA) */ DRX_AUD_STANDARD_A2, /**< set A2-Korea FM Stereo */ DRX_AUD_STANDARD_EIAJ, /**< set to Japanese FM Stereo */ @@ -1588,35 +1516,33 @@ STRUCTS /**< Automatic Standard Detection */ DRX_AUD_STANDARD_UNKNOWN = DRX_UNKNOWN /**< used as auto and for readback */ - } drx_aud_standard_t, *pdrx_aud_standard_t; + }; -/* CTRL_AUD_GET_STATUS - drx_aud_status_t */ +/* CTRL_AUD_GET_STATUS - struct drx_aud_status */ /** -* \enum drx_aud_nicam_status_t -* \brief Status of NICAM carrier. +* \enum enum drx_aud_nicam_status * \brief Status of NICAM carrier. */ - typedef enum { + enum drx_aud_nicam_status { DRX_AUD_NICAM_DETECTED = 0, /**< NICAM carrier detected */ DRX_AUD_NICAM_NOT_DETECTED, /**< NICAM carrier not detected */ DRX_AUD_NICAM_BAD /**< NICAM carrier bad quality */ - } drx_aud_nicam_status_t, *pdrx_aud_nicam_status_t; + }; /** -* \struct drx_aud_status_t -* \brief Audio status characteristics. +* \struct struct drx_aud_status * \brief Audio status characteristics. */ - typedef struct { + struct drx_aud_status { bool stereo; /**< stereo detection */ bool carrier_a; /**< carrier A detected */ bool carrier_b; /**< carrier B detected */ bool sap; /**< sap / bilingual detection */ bool rds; /**< RDS data array present */ - drx_aud_nicam_status_t nicam_status; + enum drx_aud_nicam_status nicam_status; /**< status of NICAM carrier */ s8 fm_ident; /**< FM Identification value */ - } drx_aud_status_t, *pdrx_aud_status_t; + }; /* CTRL_AUD_READ_RDS - DRXRDSdata_t */ @@ -1624,234 +1550,218 @@ STRUCTS * \struct DRXRDSdata_t * \brief Raw RDS data array. */ - typedef struct { + struct drx_cfg_aud_rds { bool valid; /**< RDS data validation */ u16 data[18]; /**< data from one RDS data array */ - } drx_cfg_aud_rds_t, *pdrx_cfg_aud_rds_t; + }; -/* DRX_CFG_AUD_VOLUME - drx_cfg_aud_volume_t - set/get */ +/* DRX_CFG_AUD_VOLUME - struct drx_cfg_aud_volume - set/get */ /** * \enum DRXAudAVCDecayTime_t * \brief Automatic volume control configuration. */ - typedef enum { + enum drx_aud_avc_mode { DRX_AUD_AVC_OFF, /**< Automatic volume control off */ DRX_AUD_AVC_DECAYTIME_8S, /**< level volume in 8 seconds */ DRX_AUD_AVC_DECAYTIME_4S, /**< level volume in 4 seconds */ DRX_AUD_AVC_DECAYTIME_2S, /**< level volume in 2 seconds */ DRX_AUD_AVC_DECAYTIME_20MS/**< level volume in 20 millisec */ - } drx_aud_avc_mode_t, *pdrx_aud_avc_mode_t; + }; /** * /enum DRXAudMaxAVCGain_t * /brief Automatic volume control max gain in audio baseband. */ - typedef enum { + enum drx_aud_avc_max_gain { DRX_AUD_AVC_MAX_GAIN_0DB, /**< maximum AVC gain 0 dB */ DRX_AUD_AVC_MAX_GAIN_6DB, /**< maximum AVC gain 6 dB */ DRX_AUD_AVC_MAX_GAIN_12DB /**< maximum AVC gain 12 dB */ - } drx_aud_avc_max_gain_t, *pdrx_aud_avc_max_gain_t; + }; /** * /enum DRXAudMaxAVCAtten_t * /brief Automatic volume control max attenuation in audio baseband. */ - typedef enum { + enum drx_aud_avc_max_atten { DRX_AUD_AVC_MAX_ATTEN_12DB, /**< maximum AVC attenuation 12 dB */ DRX_AUD_AVC_MAX_ATTEN_18DB, /**< maximum AVC attenuation 18 dB */ DRX_AUD_AVC_MAX_ATTEN_24DB/**< maximum AVC attenuation 24 dB */ - } drx_aud_avc_max_atten_t, *pdrx_aud_avc_max_atten_t; + }; /** -* \struct drx_cfg_aud_volume_t -* \brief Audio volume configuration. +* \struct struct drx_cfg_aud_volume * \brief Audio volume configuration. */ - typedef struct { + struct drx_cfg_aud_volume { bool mute; /**< mute overrides volume setting */ s16 volume; /**< volume, range -114 to 12 dB */ - drx_aud_avc_mode_t avc_mode; /**< AVC auto volume control mode */ + enum drx_aud_avc_mode avc_mode; /**< AVC auto volume control mode */ u16 avc_ref_level; /**< AVC reference level */ - drx_aud_avc_max_gain_t avc_max_gain; + enum drx_aud_avc_max_gain avc_max_gain; /**< AVC max gain selection */ - drx_aud_avc_max_atten_t avc_max_atten; + enum drx_aud_avc_max_atten avc_max_atten; /**< AVC max attenuation selection */ s16 strength_left; /**< quasi-peak, left speaker */ s16 strength_right; /**< quasi-peak, right speaker */ - } drx_cfg_aud_volume_t, *pdrx_cfg_aud_volume_t; + }; -/* DRX_CFG_I2S_OUTPUT - drx_cfg_i2s_output_t - set/get */ +/* DRX_CFG_I2S_OUTPUT - struct drx_cfg_i2s_output - set/get */ /** -* \enum drxi2s_mode_t -* \brief I2S output mode. +* \enum enum drxi2s_mode * \brief I2S output mode. */ - typedef enum { + enum drxi2s_mode { DRX_I2S_MODE_MASTER, /**< I2S is in master mode */ DRX_I2S_MODE_SLAVE /**< I2S is in slave mode */ - } drxi2s_mode_t, *pdrxi2s_mode_t; + }; /** -* \enum drxi2s_word_length_t -* \brief Width of I2S data. +* \enum enum drxi2s_word_length * \brief Width of I2S data. */ - typedef enum { + enum drxi2s_word_length { DRX_I2S_WORDLENGTH_32 = 0,/**< I2S data is 32 bit wide */ DRX_I2S_WORDLENGTH_16 = 1 /**< I2S data is 16 bit wide */ - } drxi2s_word_length_t, *pdrxi2s_word_length_t; + }; /** -* \enum drxi2s_format_t -* \brief Data wordstrobe alignment for I2S. +* \enum enum drxi2s_format * \brief Data wordstrobe alignment for I2S. */ - typedef enum { + enum drxi2s_format { DRX_I2S_FORMAT_WS_WITH_DATA, /**< I2S data and wordstrobe are aligned */ DRX_I2S_FORMAT_WS_ADVANCED /**< I2S data one cycle after wordstrobe */ - } drxi2s_format_t, *pdrxi2s_format_t; + }; /** -* \enum drxi2s_polarity_t -* \brief Polarity of I2S data. +* \enum enum drxi2s_polarity * \brief Polarity of I2S data. */ - typedef enum { + enum drxi2s_polarity { DRX_I2S_POLARITY_RIGHT,/**< wordstrobe - right high, left low */ DRX_I2S_POLARITY_LEFT /**< wordstrobe - right low, left high */ - } drxi2s_polarity_t, *pdrxi2s_polarity_t; + }; /** -* \struct drx_cfg_i2s_output_t -* \brief I2S output configuration. +* \struct struct drx_cfg_i2s_output * \brief I2S output configuration. */ - typedef struct { + struct drx_cfg_i2s_output { bool output_enable; /**< I2S output enable */ u32 frequency; /**< range from 8000-48000 Hz */ - drxi2s_mode_t mode; /**< I2S mode, master or slave */ - drxi2s_word_length_t word_length; + enum drxi2s_mode mode; /**< I2S mode, master or slave */ + enum drxi2s_word_length word_length; /**< I2S wordlength, 16 or 32 bits */ - drxi2s_polarity_t polarity;/**< I2S wordstrobe polarity */ - drxi2s_format_t format; /**< I2S wordstrobe delay to data */ - } drx_cfg_i2s_output_t, *pdrx_cfg_i2s_output_t; + enum drxi2s_polarity polarity;/**< I2S wordstrobe polarity */ + enum drxi2s_format format; /**< I2S wordstrobe delay to data */ + }; /* ------------------------------expert interface-----------------------------*/ /** -* /enum drx_aud_fm_deemphasis_t -* setting for FM-Deemphasis in audio demodulator. +* /enum enum drx_aud_fm_deemphasis * setting for FM-Deemphasis in audio demodulator. * */ - typedef enum { + enum drx_aud_fm_deemphasis { DRX_AUD_FM_DEEMPH_50US, DRX_AUD_FM_DEEMPH_75US, DRX_AUD_FM_DEEMPH_OFF - } drx_aud_fm_deemphasis_t, *pdrx_aud_fm_deemphasis_t; + }; /** * /enum DRXAudDeviation_t * setting for deviation mode in audio demodulator. * */ - typedef enum { + enum drx_cfg_aud_deviation { DRX_AUD_DEVIATION_NORMAL, DRX_AUD_DEVIATION_HIGH - } drx_cfg_aud_deviation_t, *pdrx_cfg_aud_deviation_t; + }; /** -* /enum drx_no_carrier_option_t -* setting for carrier, mute/noise. +* /enum enum drx_no_carrier_option * setting for carrier, mute/noise. * */ - typedef enum { + enum drx_no_carrier_option { DRX_NO_CARRIER_MUTE, DRX_NO_CARRIER_NOISE - } drx_no_carrier_option_t, *pdrx_no_carrier_option_t; + }; /** * \enum DRXAudAutoSound_t * \brief Automatic Sound */ - typedef enum { + enum drx_cfg_aud_auto_sound { DRX_AUD_AUTO_SOUND_OFF = 0, DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON, DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_OFF - } drx_cfg_aud_auto_sound_t, *pdrx_cfg_aud_auto_sound_t; + }; /** * \enum DRXAudASSThres_t * \brief Automatic Sound Select Thresholds */ - typedef struct { + struct drx_cfg_aud_ass_thres { u16 a2; /* A2 Threshold for ASS configuration */ u16 btsc; /* BTSC Threshold for ASS configuration */ u16 nicam; /* Nicam Threshold for ASS configuration */ - } drx_cfg_aud_ass_thres_t, *pdrx_cfg_aud_ass_thres_t; + }; /** -* \struct drx_aud_carrier_t -* \brief Carrier detection related parameters +* \struct struct drx_aud_carrier * \brief Carrier detection related parameters */ - typedef struct { + struct drx_aud_carrier { u16 thres; /* carrier detetcion threshold for primary carrier (A) */ - drx_no_carrier_option_t opt; /* Mute or noise at no carrier detection (A) */ + enum drx_no_carrier_option opt; /* Mute or noise at no carrier detection (A) */ s32 shift; /* DC level of incoming signal (A) */ s32 dco; /* frequency adjustment (A) */ - } drx_aud_carrier_t, *p_drx_cfg_aud_carrier_t; + }; /** -* \struct drx_cfg_aud_carriers_t -* \brief combining carrier A & B to one struct +* \struct struct drx_cfg_aud_carriers * \brief combining carrier A & B to one struct */ - typedef struct { - drx_aud_carrier_t a; - drx_aud_carrier_t b; - } drx_cfg_aud_carriers_t, *pdrx_cfg_aud_carriers_t; + struct drx_cfg_aud_carriers { + struct drx_aud_carrier a; + struct drx_aud_carrier b; + }; /** -* /enum drx_aud_i2s_src_t -* Selection of audio source +* /enum enum drx_aud_i2s_src * Selection of audio source */ - typedef enum { + enum drx_aud_i2s_src { DRX_AUD_SRC_MONO, DRX_AUD_SRC_STEREO_OR_AB, DRX_AUD_SRC_STEREO_OR_A, - DRX_AUD_SRC_STEREO_OR_B - } drx_aud_i2s_src_t, *pdrx_aud_i2s_src_t; + DRX_AUD_SRC_STEREO_OR_B}; /** -* \enum drx_aud_i2s_matrix_t -* \brief Used for selecting I2S output. +* \enum enum drx_aud_i2s_matrix * \brief Used for selecting I2S output. */ - typedef enum { + enum drx_aud_i2s_matrix { DRX_AUD_I2S_MATRIX_A_MONO, /**< A sound only, stereo or mono */ DRX_AUD_I2S_MATRIX_B_MONO, /**< B sound only, stereo or mono */ DRX_AUD_I2S_MATRIX_STEREO, /**< A+B sound, transparant */ - DRX_AUD_I2S_MATRIX_MONO /**< A+B mixed to mono sum, (L+R)/2 */ - } drx_aud_i2s_matrix_t, *pdrx_aud_i2s_matrix_t; + DRX_AUD_I2S_MATRIX_MONO /**< A+B mixed to mono sum, (L+R)/2 */}; /** -* /enum drx_aud_fm_matrix_t -* setting for FM-Matrix in audio demodulator. +* /enum enum drx_aud_fm_matrix * setting for FM-Matrix in audio demodulator. * */ - typedef enum { + enum drx_aud_fm_matrix { DRX_AUD_FM_MATRIX_NO_MATRIX, DRX_AUD_FM_MATRIX_GERMAN, DRX_AUD_FM_MATRIX_KOREAN, DRX_AUD_FM_MATRIX_SOUND_A, - DRX_AUD_FM_MATRIX_SOUND_B - } drx_aud_fm_matrix_t, *pdrx_aud_fm_matrix_t; + DRX_AUD_FM_MATRIX_SOUND_B}; /** * \struct DRXAudMatrices_t * \brief Mixer settings */ - typedef struct { - drx_aud_i2s_src_t source_i2s; - drx_aud_i2s_matrix_t matrix_i2s; - drx_aud_fm_matrix_t matrix_fm; - } drx_cfg_aud_mixer_t, *pdrx_cfg_aud_mixer_t; +struct drx_cfg_aud_mixer { + enum drx_aud_i2s_src source_i2s; + enum drx_aud_i2s_matrix matrix_i2s; + enum drx_aud_fm_matrix matrix_fm; +}; /** * \enum DRXI2SVidSync_t @@ -1859,76 +1769,68 @@ STRUCTS * AUTO_1 and AUTO_2 are for automatic video standard detection with preference * for NTSC or Monochrome, because the frequencies are too close (59.94 & 60 Hz) */ - typedef enum { + enum drx_cfg_aud_av_sync { DRX_AUD_AVSYNC_OFF,/**< audio/video synchronization is off */ DRX_AUD_AVSYNC_NTSC, /**< it is an NTSC system */ DRX_AUD_AVSYNC_MONOCHROME, /**< it is a MONOCHROME system */ DRX_AUD_AVSYNC_PAL_SECAM - /**< it is a PAL/SECAM system */ - } drx_cfg_aud_av_sync_t, *pdrx_cfg_aud_av_sync_t; + /**< it is a PAL/SECAM system */}; /** -* \struct drx_cfg_aud_prescale_t -* \brief Prescalers +* \struct struct drx_cfg_aud_prescale * \brief Prescalers */ - typedef struct { - u16 fm_deviation; - s16 nicam_gain; - } drx_cfg_aud_prescale_t, *pdrx_cfg_aud_prescale_t; +struct drx_cfg_aud_prescale { + u16 fm_deviation; + s16 nicam_gain; +}; /** -* \struct drx_aud_beep_t -* \brief Beep +* \struct struct drx_aud_beep * \brief Beep */ - typedef struct { - s16 volume; /* dB */ - u16 frequency; /* Hz */ - bool mute; - } drx_aud_beep_t, *pdrx_aud_beep_t; +struct drx_aud_beep { + s16 volume; /* dB */ + u16 frequency; /* Hz */ + bool mute; +}; /** -* \enum drx_aud_btsc_detect_t -* \brief BTSC detetcion mode +* \enum enum drx_aud_btsc_detect * \brief BTSC detetcion mode */ - typedef enum { + enum drx_aud_btsc_detect { DRX_BTSC_STEREO, - DRX_BTSC_MONO_AND_SAP - } drx_aud_btsc_detect_t, *pdrx_aud_btsc_detect_t; - -/** -* \struct drx_aud_data_t -* \brief Audio data structure -*/ - typedef struct { - /* audio storage */ - bool audio_is_active; - drx_aud_standard_t audio_standard; - drx_cfg_i2s_output_t i2sdata; - drx_cfg_aud_volume_t volume; - drx_cfg_aud_auto_sound_t auto_sound; - drx_cfg_aud_ass_thres_t ass_thresholds; - drx_cfg_aud_carriers_t carriers; - drx_cfg_aud_mixer_t mixer; - drx_cfg_aud_deviation_t deviation; - drx_cfg_aud_av_sync_t av_sync; - drx_cfg_aud_prescale_t prescale; - drx_aud_fm_deemphasis_t deemph; - drx_aud_btsc_detect_t btsc_detect; - /* rds */ - u16 rds_data_counter; - bool rds_data_present; - } drx_aud_data_t, *pdrx_aud_data_t; - -/** -* \enum drx_qam_lock_range_t -* \brief QAM lock range mode -*/ - typedef enum { + DRX_BTSC_MONO_AND_SAP}; + +/** +* \struct struct drx_aud_data * \brief Audio data structure +*/ +struct drx_aud_data { + /* audio storage */ + bool audio_is_active; + enum drx_aud_standard audio_standard; + struct drx_cfg_i2s_output i2sdata; + struct drx_cfg_aud_volume volume; + enum drx_cfg_aud_auto_sound auto_sound; + struct drx_cfg_aud_ass_thres ass_thresholds; + struct drx_cfg_aud_carriers carriers; + struct drx_cfg_aud_mixer mixer; + enum drx_cfg_aud_deviation deviation; + enum drx_cfg_aud_av_sync av_sync; + struct drx_cfg_aud_prescale prescale; + enum drx_aud_fm_deemphasis deemph; + enum drx_aud_btsc_detect btsc_detect; + /* rds */ + u16 rds_data_counter; + bool rds_data_present; +}; + +/** +* \enum enum drx_qam_lock_range * \brief QAM lock range mode +*/ + enum drx_qam_lock_range { DRX_QAM_LOCKRANGE_NORMAL, - DRX_QAM_LOCKRANGE_EXTENDED - } drx_qam_lock_range_t, *pdrx_qam_lock_range_t; + DRX_QAM_LOCKRANGE_EXTENDED}; /*============================================================================*/ /*============================================================================*/ @@ -1944,101 +1846,98 @@ STRUCTS /* Write block of data to device */ typedef int(*drx_write_block_func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ - dr_xaddr_t addr, /* address of register/memory */ + u32 addr, /* address of register/memory */ u16 datasize, /* size of data in bytes */ u8 *data, /* data to send */ - dr_xflags_t flags); + u32 flags); /* Read block of data from device */ typedef int(*drx_read_block_func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ - dr_xaddr_t addr, /* address of register/memory */ + u32 addr, /* address of register/memory */ u16 datasize, /* size of data in bytes */ u8 *data, /* receive buffer */ - dr_xflags_t flags); + u32 flags); /* Write 8-bits value to device */ typedef int(*drx_write_reg8func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ - dr_xaddr_t addr, /* address of register/memory */ + u32 addr, /* address of register/memory */ u8 data, /* data to send */ - dr_xflags_t flags); + u32 flags); /* Read 8-bits value to device */ typedef int(*drx_read_reg8func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ - dr_xaddr_t addr, /* address of register/memory */ + u32 addr, /* address of register/memory */ u8 *data, /* receive buffer */ - dr_xflags_t flags); + u32 flags); /* Read modify write 8-bits value to device */ typedef int(*drx_read_modify_write_reg8func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ - dr_xaddr_t waddr, /* write address of register */ - dr_xaddr_t raddr, /* read address of register */ + u32 waddr, /* write address of register */ + u32 raddr, /* read address of register */ u8 wdata, /* data to write */ u8 *rdata); /* data to read */ /* Write 16-bits value to device */ typedef int(*drx_write_reg16func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ - dr_xaddr_t addr, /* address of register/memory */ + u32 addr, /* address of register/memory */ u16 data, /* data to send */ - dr_xflags_t flags); + u32 flags); /* Read 16-bits value to device */ typedef int(*drx_read_reg16func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ - dr_xaddr_t addr, /* address of register/memory */ + u32 addr, /* address of register/memory */ u16 *data, /* receive buffer */ - dr_xflags_t flags); + u32 flags); /* Read modify write 16-bits value to device */ typedef int(*drx_read_modify_write_reg16func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ - dr_xaddr_t waddr, /* write address of register */ - dr_xaddr_t raddr, /* read address of register */ + u32 waddr, /* write address of register */ + u32 raddr, /* read address of register */ u16 wdata, /* data to write */ u16 *rdata); /* data to read */ /* Write 32-bits value to device */ typedef int(*drx_write_reg32func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ - dr_xaddr_t addr, /* address of register/memory */ + u32 addr, /* address of register/memory */ u32 data, /* data to send */ - dr_xflags_t flags); + u32 flags); /* Read 32-bits value to device */ typedef int(*drx_read_reg32func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ - dr_xaddr_t addr, /* address of register/memory */ + u32 addr, /* address of register/memory */ u32 *data, /* receive buffer */ - dr_xflags_t flags); + u32 flags); /* Read modify write 32-bits value to device */ typedef int(*drx_read_modify_write_reg32func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ - dr_xaddr_t waddr, /* write address of register */ - dr_xaddr_t raddr, /* read address of register */ + u32 waddr, /* write address of register */ + u32 raddr, /* read address of register */ u32 wdata, /* data to write */ u32 *rdata); /* data to read */ /** -* \struct drx_access_func_t -* \brief Interface to an access protocol. -*/ - typedef struct { - pdrx_version_t protocolVersion; - drx_write_block_func_t write_block_func; - drx_read_block_func_t read_block_func; - drx_write_reg8func_t write_reg8func; - drx_read_reg8func_t read_reg8func; - drx_read_modify_write_reg8func_t read_modify_write_reg8func; - drx_write_reg16func_t write_reg16func; - drx_read_reg16func_t read_reg16func; - drx_read_modify_write_reg16func_t read_modify_write_reg16func; - drx_write_reg32func_t write_reg32func; - drx_read_reg32func_t read_reg32func; - drx_read_modify_write_reg32func_t read_modify_write_reg32func; - } drx_access_func_t, *pdrx_access_func_t; +* \struct struct drx_access_func * \brief Interface to an access protocol. +*/ +struct drx_access_func { + struct drx_version *protocolVersion; + drx_write_block_func_t write_block_func; + drx_read_block_func_t read_block_func; + drx_write_reg8func_t write_reg8func; + drx_read_reg8func_t read_reg8func; + drx_read_modify_write_reg8func_t read_modify_write_reg8func; + drx_write_reg16func_t write_reg16func; + drx_read_reg16func_t read_reg16func; + drx_read_modify_write_reg16func_t read_modify_write_reg16func; + drx_write_reg32func_t write_reg32func; + drx_read_reg32func_t read_reg32func; + drx_read_modify_write_reg32func_t read_modify_write_reg32func; +}; /* Register address and data for register dump function */ - typedef struct { - - dr_xaddr_t address; - u32 data; - - } drx_reg_dump_t, *p_drx_reg_dump_t; +struct drx_reg_dump { + u32 address; + u32 data; +}; /*============================================================================*/ /*============================================================================*/ @@ -2047,17 +1946,16 @@ STRUCTS /*============================================================================*/ /** -* \struct drx_common_attr_t -* \brief Set of common attributes, shared by all DRX devices. +* \struct struct drx_common_attr * \brief Set of common attributes, shared by all DRX devices. */ - typedef struct { + struct drx_common_attr { /* Microcode (firmware) attributes */ u8 *microcode; /**< Pointer to microcode image. */ u16 microcode_size; /**< Size of microcode image in bytes. */ bool verify_microcode; /**< Use microcode verify or not. */ - drx_mc_version_rec_t mcversion; + struct drx_mc_version_rec mcversion; /**< Version record of microcode from file */ /* Clocks and tuner attributes */ @@ -2073,13 +1971,13 @@ STRUCTS /**< Mirror IF frequency spectrum or not.*/ /* Initial MPEG output attributes */ - drx_cfg_mpeg_output_t mpeg_cfg; + struct drx_cfg_mpeg_output mpeg_cfg; /**< MPEG configuration */ bool is_opened; /**< if true instance is already opened. */ /* Channel scan */ - p_drx_scan_param_t scan_param; + struct drx_scan_param *scan_param; /**< scan parameters */ u16 scan_freq_plan_index; /**< next index in freq plan */ @@ -2097,14 +1995,14 @@ STRUCTS /* Channel scan - parameters for default DTV scan function in core driver */ u16 scan_demod_lock_timeout; /**< millisecs to wait for lock */ - drx_lock_status_t scan_desired_lock; + enum drx_lock_status scan_desired_lock; /**< lock requirement for channel found */ /* scan_active can be used by SetChannel to decide how to program the tuner, fast or slow (but stable). Usually fast during scan. */ bool scan_active; /**< true when scan routines are active */ /* Power management */ - drx_power_mode_t current_power_mode; + enum drx_power_mode current_power_mode; /**< current power management mode */ /* Tuner */ @@ -2117,7 +2015,7 @@ STRUCTS bool tuner_if_agc_pol; /**< if true invert IF AGC polarity */ bool tuner_slow_mode; /**< if true invert IF AGC polarity */ - drx_channel_t current_channel; + struct drx_channel current_channel; /**< current channel parameters */ enum drx_standard current_standard; /**< current standard selection */ @@ -2127,51 +2025,47 @@ STRUCTS /**< standard in DI cache if available */ bool use_bootloader; /**< use bootloader in open */ u32 capabilities; /**< capabilities flags */ - u32 product_id; /**< product ID inc. metal fix number */ - - } drx_common_attr_t, *pdrx_common_attr_t; + u32 product_id; /**< product ID inc. metal fix number */}; /* * Generic functions for DRX devices. */ - typedef struct drx_demod_instance_s *pdrx_demod_instance_t; - typedef int(*drx_open_func_t) (pdrx_demod_instance_t demod); - typedef int(*drx_close_func_t) (pdrx_demod_instance_t demod); - typedef int(*drx_ctrl_func_t) (pdrx_demod_instance_t demod, +struct drx_demod_instance; + + typedef int(*drx_open_func_t) (struct drx_demod_instance *demod); + typedef int(*drx_close_func_t) (struct drx_demod_instance *demod); + typedef int(*drx_ctrl_func_t) (struct drx_demod_instance *demod, u32 ctrl, void *ctrl_data); /** -* \struct drx_demod_func_t -* \brief A stucture containing all functions of a demodulator. +* \struct struct drx_demod_func * \brief A stucture containing all functions of a demodulator. */ - typedef struct { + struct drx_demod_func { u32 type_id; /**< Device type identifier. */ drx_open_func_t open_func; /**< Pointer to Open() function. */ drx_close_func_t close_func;/**< Pointer to Close() function. */ - drx_ctrl_func_t ctrl_func; /**< Pointer to Ctrl() function. */ - } drx_demod_func_t, *pdrx_demod_func_t; + drx_ctrl_func_t ctrl_func; /**< Pointer to Ctrl() function. */}; /** -* \struct drx_demod_instance_t -* \brief Top structure of demodulator instance. +* \struct struct drx_demod_instance * \brief Top structure of demodulator instance. */ - typedef struct drx_demod_instance_s { + struct drx_demod_instance { /* type specific demodulator data */ - pdrx_demod_func_t my_demod_funct; + struct drx_demod_func *my_demod_funct; /**< demodulator functions */ - pdrx_access_func_t my_access_funct; + struct drx_access_func *my_access_funct; /**< data access protocol functions */ struct tuner_instance *my_tuner; /**< tuner instance,if NULL then baseband */ struct i2c_device_addr *my_i2c_dev_addr; /**< i2c address and device identifier */ - pdrx_common_attr_t my_common_attr; + struct drx_common_attr *my_common_attr; /**< common DRX attributes */ void *my_ext_attr; /**< device specific attributes */ /* generic demodulator data */ - } drx_demod_instance_t; + }; /*------------------------------------------------------------------------- MACROS @@ -2828,7 +2722,7 @@ Access macros #define DRX_ACCESSMACRO_SET(demod, value, cfg_name, data_type) \ do { \ - drx_cfg_t config; \ + struct drx_cfg config; \ data_type cfg_data; \ config.cfg_type = cfg_name; \ config.cfg_data = &cfg_data; \ @@ -2839,7 +2733,7 @@ Access macros #define DRX_ACCESSMACRO_GET(demod, value, cfg_name, data_type, error_value) \ do { \ int cfg_status; \ - drx_cfg_t config; \ + struct drx_cfg config; \ data_type cfg_data; \ config.cfg_type = cfg_name; \ config.cfg_data = &cfg_data; \ @@ -2869,21 +2763,21 @@ Access macros DRX_ACCESSMACRO_GET((d), (x), DRX_XS_CFG_PRESET, char*, "ERROR") #define DRX_SET_AUD_BTSC_DETECT(d, x) DRX_ACCESSMACRO_SET((d), (x), \ - DRX_XS_CFG_AUD_BTSC_DETECT, drx_aud_btsc_detect_t) + DRX_XS_CFG_AUD_BTSC_DETECT, enum drx_aud_btsc_detect) #define DRX_GET_AUD_BTSC_DETECT(d, x) DRX_ACCESSMACRO_GET((d), (x), \ - DRX_XS_CFG_AUD_BTSC_DETECT, drx_aud_btsc_detect_t, DRX_UNKNOWN) + DRX_XS_CFG_AUD_BTSC_DETECT, enum drx_aud_btsc_detect, DRX_UNKNOWN) #define DRX_SET_QAM_LOCKRANGE(d, x) DRX_ACCESSMACRO_SET((d), (x), \ - DRX_XS_CFG_QAM_LOCKRANGE, drx_qam_lock_range_t) + DRX_XS_CFG_QAM_LOCKRANGE, enum drx_qam_lock_range) #define DRX_GET_QAM_LOCKRANGE(d, x) DRX_ACCESSMACRO_GET((d), (x), \ - DRX_XS_CFG_QAM_LOCKRANGE, drx_qam_lock_range_t, DRX_UNKNOWN) + DRX_XS_CFG_QAM_LOCKRANGE, enum drx_qam_lock_range, DRX_UNKNOWN) /** * \brief Macro to check if std is an ATV standard * \retval true std is an ATV standard * \retval false std is an ATV standard */ -#define DRX_ISATVSTD(std) (( (std) == DRX_STANDARD_PAL_SECAM_BG) || \ +#define DRX_ISATVSTD(std) (((std) == DRX_STANDARD_PAL_SECAM_BG) || \ ((std) == DRX_STANDARD_PAL_SECAM_DK) || \ ((std) == DRX_STANDARD_PAL_SECAM_I) || \ ((std) == DRX_STANDARD_PAL_SECAM_L) || \ @@ -2896,7 +2790,7 @@ Access macros * \retval true std is an QAM standards * \retval false std is an QAM standards */ -#define DRX_ISQAMSTD(std) (( (std) == DRX_STANDARD_ITU_A) || \ +#define DRX_ISQAMSTD(std) (((std) == DRX_STANDARD_ITU_A) || \ ((std) == DRX_STANDARD_ITU_B) || \ ((std) == DRX_STANDARD_ITU_C) || \ ((std) == DRX_STANDARD_ITU_D)) @@ -2919,15 +2813,15 @@ Access macros Exported FUNCTIONS -------------------------------------------------------------------------*/ - int drx_init(pdrx_demod_instance_t demods[]); + int drx_init(struct drx_demod_instance *demods[]); int drx_term(void); - int drx_open(pdrx_demod_instance_t demod); + int drx_open(struct drx_demod_instance *demod); - int drx_close(pdrx_demod_instance_t demod); + int drx_close(struct drx_demod_instance *demod); - int drx_ctrl(pdrx_demod_instance_t demod, + int drx_ctrl(struct drx_demod_instance *demod, u32 ctrl, void *ctrl_data); /*------------------------------------------------------------------------- diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index 24f84e5..fc727d9 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -586,9 +586,9 @@ DEFINES /*----------------------------------------------------------------------------- STATIC VARIABLES ----------------------------------------------------------------------------*/ -int drxj_open(pdrx_demod_instance_t demod); -int drxj_close(pdrx_demod_instance_t demod); -int drxj_ctrl(pdrx_demod_instance_t demod, +int drxj_open(struct drx_demod_instance *demod); +int drxj_close(struct drx_demod_instance *demod); +int drxj_ctrl(struct drx_demod_instance *demod, u32 ctrl, void *ctrl_data); /*----------------------------------------------------------------------------- @@ -599,59 +599,59 @@ GLOBAL VARIABLES */ static int drxj_dap_read_block(struct i2c_device_addr *dev_addr, - dr_xaddr_t addr, + u32 addr, u16 datasize, - u8 *data, dr_xflags_t flags); + u8 *data, u32 flags); static int drxj_dap_read_modify_write_reg8(struct i2c_device_addr *dev_addr, - dr_xaddr_t waddr, - dr_xaddr_t raddr, + u32 waddr, + u32 raddr, u8 wdata, u8 *rdata); static int drxj_dap_read_modify_write_reg16(struct i2c_device_addr *dev_addr, - dr_xaddr_t waddr, - dr_xaddr_t raddr, + u32 waddr, + u32 raddr, u16 wdata, u16 *rdata); static int drxj_dap_read_modify_write_reg32(struct i2c_device_addr *dev_addr, - dr_xaddr_t waddr, - dr_xaddr_t raddr, + u32 waddr, + u32 raddr, u32 wdata, u32 *rdata); static int drxj_dap_read_reg8(struct i2c_device_addr *dev_addr, - dr_xaddr_t addr, - u8 *data, dr_xflags_t flags); + u32 addr, + u8 *data, u32 flags); static int drxj_dap_read_reg16(struct i2c_device_addr *dev_addr, - dr_xaddr_t addr, - u16 *data, dr_xflags_t flags); + u32 addr, + u16 *data, u32 flags); static int drxj_dap_read_reg32(struct i2c_device_addr *dev_addr, - dr_xaddr_t addr, - u32 *data, dr_xflags_t flags); + u32 addr, + u32 *data, u32 flags); static int drxj_dap_write_block(struct i2c_device_addr *dev_addr, - dr_xaddr_t addr, + u32 addr, u16 datasize, - u8 *data, dr_xflags_t flags); + u8 *data, u32 flags); static int drxj_dap_write_reg8(struct i2c_device_addr *dev_addr, - dr_xaddr_t addr, - u8 data, dr_xflags_t flags); + u32 addr, + u8 data, u32 flags); static int drxj_dap_write_reg16(struct i2c_device_addr *dev_addr, - dr_xaddr_t addr, - u16 data, dr_xflags_t flags); + u32 addr, + u16 data, u32 flags); static int drxj_dap_write_reg32(struct i2c_device_addr *dev_addr, - dr_xaddr_t addr, - u32 data, dr_xflags_t flags); + u32 addr, + u32 data, u32 flags); /* The version structure of this protocol implementation */ char drx_dap_drxj_module_name[] = "DRXJ Data Access Protocol"; char drx_dap_drxj_version_text[] = "0.0.0"; -drx_version_t drx_dap_drxj_version = { +struct drx_version drx_dap_drxj_version = { DRX_MODULE_DAP, /**< type identifier of the module */ drx_dap_drxj_module_name, /**< name or description of module */ @@ -662,7 +662,7 @@ drx_version_t drx_dap_drxj_version = { }; /* The structure containing the protocol interface */ -drx_access_func_t drx_dap_drxj_funct_g = { +struct drx_access_func drx_dap_drxj_funct_g = { &drx_dap_drxj_version, drxj_dap_write_block, /* Supported */ drxj_dap_read_block, /* Supported */ @@ -681,7 +681,7 @@ drx_access_func_t drx_dap_drxj_funct_g = { * /var DRXJ_Func_g * /brief The driver functions of the drxj */ -drx_demod_func_t drxj_functions_g = { +struct drx_demod_func drxj_functions_g = { DRXJ_TYPE_ID, drxj_open, drxj_close, @@ -848,7 +848,7 @@ drxj_data_t drxj_data_g = { "01234567890" /* human readable version device specific code */ }, { - { /* drx_version_t for microcode */ + { /* struct drx_version for microcode */ DRX_MODULE_UNKNOWN, (char *)(NULL), 0, @@ -856,7 +856,7 @@ drxj_data_t drxj_data_g = { 0, (char *)(NULL) }, - { /* drx_version_t for device specific code */ + { /* struct drx_version for device specific code */ DRX_MODULE_UNKNOWN, (char *)(NULL), 0, @@ -866,13 +866,13 @@ drxj_data_t drxj_data_g = { } }, { - { /* drx_version_list_t for microcode */ - (pdrx_version_t) (NULL), - (p_drx_version_list_t) (NULL) + { /* struct drx_version_list for microcode */ + (struct drx_version *) (NULL), + (struct drx_version_list *) (NULL) }, - { /* drx_version_list_t for device specific code */ - (pdrx_version_t) (NULL), - (p_drx_version_list_t) (NULL) + { /* struct drx_version_list for device specific code */ + (struct drx_version *) (NULL), + (struct drx_version_list *) (NULL) } }, #endif @@ -949,7 +949,7 @@ struct i2c_device_addr drxj_default_addr_g = { * \var drxj_default_comm_attr_g * \brief Default common attributes of a drxj demodulator instance. */ -drx_common_attr_t drxj_default_comm_attr_g = { +struct drx_common_attr drxj_default_comm_attr_g = { (u8 *)NULL, /* ucode ptr */ 0, /* ucode size */ true, /* ucode verify switch */ @@ -1021,7 +1021,7 @@ drx_common_attr_t drxj_default_comm_attr_g = { * \var drxj_default_demod_g * \brief Default drxj demodulator instance. */ -drx_demod_instance_t drxj_default_demod_g = { +struct drx_demod_instance drxj_default_demod_g = { &drxj_functions_g, /* demod functions */ &DRXJ_DAP, /* data access protocol functions */ NULL, /* tuner instance */ @@ -1036,7 +1036,7 @@ drx_demod_instance_t drxj_default_demod_g = { * This structure is DRXK specific. * */ -drx_aud_data_t drxj_default_aud_data_g = { +struct drx_aud_data drxj_default_aud_data_g = { false, /* audio_is_active */ DRX_AUD_STANDARD_AUTO, /* audio_standard */ @@ -1150,31 +1150,31 @@ hi_command(struct i2c_device_addr *dev_addr, const pdrxj_hi_cmd_t cmd, u16 *result); static int -ctrl_lock_status(pdrx_demod_instance_t demod, pdrx_lock_status_t lock_stat); +ctrl_lock_status(struct drx_demod_instance *demod, enum drx_lock_status *lock_stat); static int -ctrl_power_mode(pdrx_demod_instance_t demod, pdrx_power_mode_t mode); +ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode); -static int power_down_aud(pdrx_demod_instance_t demod); +static int power_down_aud(struct drx_demod_instance *demod); #ifndef DRXJ_DIGITAL_ONLY -static int power_up_aud(pdrx_demod_instance_t demod, bool set_standard); +static int power_up_aud(struct drx_demod_instance *demod, bool set_standard); #endif static int -aud_ctrl_set_standard(pdrx_demod_instance_t demod, pdrx_aud_standard_t standard); +aud_ctrl_set_standard(struct drx_demod_instance *demod, enum drx_aud_standard *standard); static int -ctrl_set_cfg_pre_saw(pdrx_demod_instance_t demod, p_drxj_cfg_pre_saw_t pre_saw); +ctrl_set_cfg_pre_saw(struct drx_demod_instance *demod, p_drxj_cfg_pre_saw_t pre_saw); static int -ctrl_set_cfg_afe_gain(pdrx_demod_instance_t demod, p_drxj_cfg_afe_gain_t afe_gain); +ctrl_set_cfg_afe_gain(struct drx_demod_instance *demod, p_drxj_cfg_afe_gain_t afe_gain); #ifdef DRXJ_SPLIT_UCODE_UPLOAD static int -ctrl_u_codeUpload(pdrx_demod_instance_t demod, - p_drxu_code_info_t mc_info, - drxu_code_action_t action, bool audio_mc_upload); +ctrl_u_codeUpload(struct drx_demod_instance *demod, + struct drxu_code_info *mc_info, + enum drxu_code_actionaction, bool audio_mc_upload); #endif /* DRXJ_SPLIT_UCODE_UPLOAD */ /*============================================================================*/ @@ -1688,7 +1688,7 @@ static const u16 nicam_presc_table_val[43] = /*============================================================================*/ /** -* \fn bool is_handled_by_aud_tr_if( dr_xaddr_t addr ) +* \fn bool is_handled_by_aud_tr_if( u32 addr ) * \brief Check if this address is handled by the audio token ring interface. * \param addr * \return bool @@ -1697,7 +1697,7 @@ static const u16 nicam_presc_table_val[43] = * */ static -bool is_handled_by_aud_tr_if(dr_xaddr_t addr) +bool is_handled_by_aud_tr_if(u32 addr) { bool retval = false; @@ -1713,9 +1713,9 @@ bool is_handled_by_aud_tr_if(dr_xaddr_t addr) /*============================================================================*/ static int drxj_dap_read_block(struct i2c_device_addr *dev_addr, - dr_xaddr_t addr, + u32 addr, u16 datasize, - u8 *data, dr_xflags_t flags) + u8 *data, u32 flags) { return drx_dap_fasi_funct_g.read_block_func(dev_addr, addr, datasize, data, flags); @@ -1724,8 +1724,8 @@ static int drxj_dap_read_block(struct i2c_device_addr *dev_addr, /*============================================================================*/ static int drxj_dap_read_modify_write_reg8(struct i2c_device_addr *dev_addr, - dr_xaddr_t waddr, - dr_xaddr_t raddr, + u32 waddr, + u32 raddr, u8 wdata, u8 *rdata) { return drx_dap_fasi_funct_g.read_modify_write_reg8func(dev_addr, @@ -1757,8 +1757,8 @@ static int drxj_dap_read_modify_write_reg8(struct i2c_device_addr *dev_addr, See comments drxj_dap_read_modify_write_reg16 */ #if (DRXDAPFASI_LONG_ADDR_ALLOWED == 0) static int drxj_dap_rm_write_reg16short(struct i2c_device_addr *dev_addr, - dr_xaddr_t waddr, - dr_xaddr_t raddr, + u32 waddr, + u32 raddr, u16 wdata, u16 *rdata) { int rc; @@ -1796,8 +1796,8 @@ static int drxj_dap_rm_write_reg16short(struct i2c_device_addr *dev_addr, /*============================================================================*/ static int drxj_dap_read_modify_write_reg16(struct i2c_device_addr *dev_addr, - dr_xaddr_t waddr, - dr_xaddr_t raddr, + u32 waddr, + u32 raddr, u16 wdata, u16 *rdata) { /* TODO: correct short/long addressing format decision, @@ -1815,8 +1815,8 @@ static int drxj_dap_read_modify_write_reg16(struct i2c_device_addr *dev_addr, /*============================================================================*/ static int drxj_dap_read_modify_write_reg32(struct i2c_device_addr *dev_addr, - dr_xaddr_t waddr, - dr_xaddr_t raddr, + u32 waddr, + u32 raddr, u32 wdata, u32 *rdata) { return drx_dap_fasi_funct_g.read_modify_write_reg32func(dev_addr, @@ -1827,8 +1827,8 @@ static int drxj_dap_read_modify_write_reg32(struct i2c_device_addr *dev_addr, /*============================================================================*/ static int drxj_dap_read_reg8(struct i2c_device_addr *dev_addr, - dr_xaddr_t addr, - u8 *data, dr_xflags_t flags) + u32 addr, + u8 *data, u32 flags) { return drx_dap_fasi_funct_g.read_reg8func(dev_addr, addr, data, flags); } @@ -1849,7 +1849,7 @@ static int drxj_dap_read_reg8(struct i2c_device_addr *dev_addr, * */ static int drxj_dap_read_aud_reg16(struct i2c_device_addr *dev_addr, - dr_xaddr_t addr, u16 *data) + u32 addr, u16 *data) { u32 start_timer = 0; u32 current_timer = 0; @@ -1861,7 +1861,7 @@ static int drxj_dap_read_aud_reg16(struct i2c_device_addr *dev_addr, if (DRXDAP_FASI_ADDR2BANK(addr) == 3) { stat = DRX_STS_INVALID_ARG; } else { - const dr_xaddr_t write_bit = ((dr_xaddr_t) 1) << 16; + const u32 write_bit = ((dr_xaddr_t) 1) << 16; /* Force reset write bit */ addr &= (~write_bit); @@ -1929,8 +1929,8 @@ static int drxj_dap_read_aud_reg16(struct i2c_device_addr *dev_addr, /*============================================================================*/ static int drxj_dap_read_reg16(struct i2c_device_addr *dev_addr, - dr_xaddr_t addr, - u16 *data, dr_xflags_t flags) + u32 addr, + u16 *data, u32 flags) { int stat = DRX_STS_ERROR; @@ -1952,8 +1952,8 @@ static int drxj_dap_read_reg16(struct i2c_device_addr *dev_addr, /*============================================================================*/ static int drxj_dap_read_reg32(struct i2c_device_addr *dev_addr, - dr_xaddr_t addr, - u32 *data, dr_xflags_t flags) + u32 addr, + u32 *data, u32 flags) { return drx_dap_fasi_funct_g.read_reg32func(dev_addr, addr, data, flags); } @@ -1961,9 +1961,9 @@ static int drxj_dap_read_reg32(struct i2c_device_addr *dev_addr, /*============================================================================*/ static int drxj_dap_write_block(struct i2c_device_addr *dev_addr, - dr_xaddr_t addr, + u32 addr, u16 datasize, - u8 *data, dr_xflags_t flags) + u8 *data, u32 flags) { return drx_dap_fasi_funct_g.write_block_func(dev_addr, addr, datasize, data, flags); @@ -1972,8 +1972,8 @@ static int drxj_dap_write_block(struct i2c_device_addr *dev_addr, /*============================================================================*/ static int drxj_dap_write_reg8(struct i2c_device_addr *dev_addr, - dr_xaddr_t addr, - u8 data, dr_xflags_t flags) + u32 addr, + u8 data, u32 flags) { return drx_dap_fasi_funct_g.write_reg8func(dev_addr, addr, data, flags); } @@ -1994,7 +1994,7 @@ static int drxj_dap_write_reg8(struct i2c_device_addr *dev_addr, * */ static int drxj_dap_write_aud_reg16(struct i2c_device_addr *dev_addr, - dr_xaddr_t addr, u16 data) + u32 addr, u16 data) { int stat = DRX_STS_ERROR; @@ -2006,7 +2006,7 @@ static int drxj_dap_write_aud_reg16(struct i2c_device_addr *dev_addr, u32 current_timer = 0; u32 delta_timer = 0; u16 tr_status = 0; - const dr_xaddr_t write_bit = ((dr_xaddr_t) 1) << 16; + const u32 write_bit = ((dr_xaddr_t) 1) << 16; /* Force write bit */ addr |= write_bit; @@ -2041,8 +2041,8 @@ static int drxj_dap_write_aud_reg16(struct i2c_device_addr *dev_addr, /*============================================================================*/ static int drxj_dap_write_reg16(struct i2c_device_addr *dev_addr, - dr_xaddr_t addr, - u16 data, dr_xflags_t flags) + u32 addr, + u16 data, u32 flags) { int stat = DRX_STS_ERROR; @@ -2064,8 +2064,8 @@ static int drxj_dap_write_reg16(struct i2c_device_addr *dev_addr, /*============================================================================*/ static int drxj_dap_write_reg32(struct i2c_device_addr *dev_addr, - dr_xaddr_t addr, - u32 data, dr_xflags_t flags) + u32 addr, + u32 data, u32 flags) { return drx_dap_fasi_funct_g.write_reg32func(dev_addr, addr, data, flags); } @@ -2095,7 +2095,7 @@ static int drxj_dap_write_reg32(struct i2c_device_addr *dev_addr, */ static int drxj_dap_atomic_read_write_block(struct i2c_device_addr *dev_addr, - dr_xaddr_t addr, + u32 addr, u16 datasize, u8 *data, bool read_flag) { @@ -2169,8 +2169,8 @@ rw_error: */ static int drxj_dap_atomic_read_reg32(struct i2c_device_addr *dev_addr, - dr_xaddr_t addr, - u32 *data, dr_xflags_t flags) + u32 addr, + u32 *data, u32 flags) { u8 buf[sizeof(*data)]; int rc = DRX_STS_ERROR; @@ -2219,7 +2219,7 @@ int drxj_dap_atomic_read_reg32(struct i2c_device_addr *dev_addr, * enable/disable should not need re-configuration of the HI. * */ -static int hi_cfg_command(const pdrx_demod_instance_t demod) +static int hi_cfg_command(const struct drx_demod_instance *demod) { pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); drxj_hi_cmd_t hi_cmd; @@ -2322,7 +2322,7 @@ rw_error: } /** -* \fn int init_hi( const pdrx_demod_instance_t demod ) +* \fn int init_hi( const struct drx_demod_instance *demod ) * \brief Initialise and configurate HI. * \param demod pointer to demod data. * \return int Return status. @@ -2334,14 +2334,14 @@ rw_error: * bridging is controlled. * */ -static int init_hi(const pdrx_demod_instance_t demod) +static int init_hi(const struct drx_demod_instance *demod) { pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); - pdrx_common_attr_t common_attr = (pdrx_common_attr_t) (NULL); + struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL); struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); ext_attr = (pdrxj_data_t) demod->my_ext_attr; - common_attr = (pdrx_common_attr_t) demod->my_common_attr; + common_attr = (struct drx_common_attr *) demod->my_common_attr; dev_addr = demod->my_i2c_dev_addr; /* PATCH for bug 5003, HI ucode v3.1.0 */ @@ -2411,16 +2411,16 @@ rw_error: * * ext_attr->has_oob * */ -static int get_device_capabilities(pdrx_demod_instance_t demod) +static int get_device_capabilities(struct drx_demod_instance *demod) { - pdrx_common_attr_t common_attr = (pdrx_common_attr_t) (NULL); + struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL); pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); u16 sio_pdr_ohw_cfg = 0; u32 sio_top_jtagid_lo = 0; u16 bid = 0; - common_attr = (pdrx_common_attr_t) demod->my_common_attr; + common_attr = (struct drx_common_attr *) demod->my_common_attr; ext_attr = (pdrxj_data_t) demod->my_ext_attr; dev_addr = demod->my_i2c_dev_addr; @@ -2586,7 +2586,7 @@ rw_error: #define DRXJ_MAX_RETRIES_POWERUP 10 #endif -static int power_up_device(pdrx_demod_instance_t demod) +static int power_up_device(struct drx_demod_instance *demod) { struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); u8 data = 0; @@ -2636,11 +2636,11 @@ static int power_up_device(pdrx_demod_instance_t demod) * */ static int -ctrl_set_cfg_mpeg_output(pdrx_demod_instance_t demod, pdrx_cfg_mpeg_output_t cfg_data) +ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_output *cfg_data) { struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); - pdrx_common_attr_t common_attr = (pdrx_common_attr_t) (NULL); + struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL); u16 fec_oc_reg_mode = 0; u16 fec_oc_reg_ipr_mode = 0; u16 fec_oc_reg_ipr_invert = 0; @@ -2661,7 +2661,7 @@ ctrl_set_cfg_mpeg_output(pdrx_demod_instance_t demod, pdrx_cfg_mpeg_output_t cfg dev_addr = demod->my_i2c_dev_addr; ext_attr = (pdrxj_data_t) demod->my_ext_attr; - common_attr = (pdrx_common_attr_t) demod->my_common_attr; + common_attr = (struct drx_common_attr *) demod->my_common_attr; if (cfg_data->enable_mpeg_output == true) { /* quick and dirty patch to set MPEG incase current std is not @@ -3038,11 +3038,11 @@ rw_error: * */ static int -ctrl_get_cfg_mpeg_output(pdrx_demod_instance_t demod, pdrx_cfg_mpeg_output_t cfg_data) +ctrl_get_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_output *cfg_data) { struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); - pdrx_common_attr_t common_attr = (pdrx_common_attr_t) (NULL); - drx_lock_status_t lock_status = DRX_NOT_LOCKED; + struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL); + enum drx_lock_status lock_status = DRX_NOT_LOCKED; u32 rate_reg = 0; u32 data64hi = 0; u32 data64lo = 0; @@ -3095,7 +3095,7 @@ rw_error: * This routine should be called during a set channel of QAM/VSB * */ -static int set_mpegtei_handling(pdrx_demod_instance_t demod) +static int set_mpegtei_handling(struct drx_demod_instance *demod) { pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); @@ -3143,7 +3143,7 @@ rw_error: * This routine should be called during a set channel of QAM/VSB * */ -static int bit_reverse_mpeg_output(pdrx_demod_instance_t demod) +static int bit_reverse_mpeg_output(struct drx_demod_instance *demod) { pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); @@ -3179,7 +3179,7 @@ rw_error: * This routine should be called during a set channel of QAM/VSB * */ -static int set_mpeg_output_clock_rate(pdrx_demod_instance_t demod) +static int set_mpeg_output_clock_rate(struct drx_demod_instance *demod) { pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); @@ -3207,12 +3207,12 @@ rw_error: * This routine should be called during a set channel of QAM/VSB * */ -static int set_mpeg_start_width(pdrx_demod_instance_t demod) +static int set_mpeg_start_width(struct drx_demod_instance *demod) { pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); u16 fec_oc_comm_mb = 0; - pdrx_common_attr_t common_attr = (pdrx_common_attr_t) NULL; + struct drx_common_attr *common_attr = (struct drx_common_attr *) NULL; dev_addr = demod->my_i2c_dev_addr; ext_attr = (pdrxj_data_t) demod->my_ext_attr; @@ -3246,7 +3246,7 @@ rw_error: * */ static int -ctrl_set_cfg_mpeg_output_misc(pdrx_demod_instance_t demod, +ctrl_set_cfg_mpeg_output_misc(struct drx_demod_instance *demod, p_drxj_cfg_mpeg_output_misc_t cfg_data) { pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); @@ -3296,7 +3296,7 @@ rw_error: * */ static int -ctrl_get_cfg_mpeg_output_misc(pdrx_demod_instance_t demod, +ctrl_get_cfg_mpeg_output_misc(struct drx_demod_instance *demod, p_drxj_cfg_mpeg_output_misc_t cfg_data) { pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); @@ -3338,7 +3338,7 @@ rw_error: * */ static int -ctrl_get_cfg_hw_cfg(pdrx_demod_instance_t demod, p_drxj_cfg_hw_cfg_t cfg_data) +ctrl_get_cfg_hw_cfg(struct drx_demod_instance *demod, p_drxj_cfg_hw_cfg_t cfg_data) { u16 data = 0; @@ -3371,7 +3371,7 @@ rw_error: * \param uio_cfg Pointer to a configuration setting for a certain UIO. * \return int. */ -static int ctrl_set_uio_cfg(pdrx_demod_instance_t demod, pdrxuio_cfg_t uio_cfg) +static int ctrl_set_uio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg *uio_cfg) { pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); @@ -3484,11 +3484,11 @@ rw_error: * \param uio_cfg Pointer to a configuration setting for a certain UIO. * \return int. */ -static int CtrlGetuio_cfg(pdrx_demod_instance_t demod, pdrxuio_cfg_t uio_cfg) +static int CtrlGetuio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg *uio_cfg) { pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; - pdrxuio_mode_t uio_mode[4] = { NULL }; + enum drxuio_mode *uio_mode[4] = { NULL }; bool *uio_available[4] = { NULL }; ext_attr = demod->my_ext_attr; @@ -3528,7 +3528,7 @@ static int CtrlGetuio_cfg(pdrx_demod_instance_t demod, pdrxuio_cfg_t uio_cfg) * \return int. */ static int -ctrl_uio_write(pdrx_demod_instance_t demod, pdrxuio_data_t uio_data) +ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data) { pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); u16 pin_cfg_value = 0; @@ -3673,7 +3673,7 @@ rw_error: * \param uio_data Pointer to data container for a certain UIO. * \return int. */ -static int ctrl_uio_read(pdrx_demod_instance_t demod, pdrxuio_data_t uio_data) +static int ctrl_uio_read(struct drx_demod_instance *demod, struct drxuio_data *uio_data) { pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); u16 pin_cfg_value = 0; @@ -3820,7 +3820,7 @@ rw_error: */ static int -ctrl_i2c_bridge(pdrx_demod_instance_t demod, bool *bridge_closed) +ctrl_i2c_bridge(struct drx_demod_instance *demod, bool *bridge_closed) { drxj_hi_cmd_t hi_cmd; u16 result = 0; @@ -3851,16 +3851,16 @@ ctrl_i2c_bridge(pdrx_demod_instance_t demod, bool *bridge_closed) /** * \fn int smart_ant_init() * \brief Initialize Smart Antenna. -* \param pointer to drx_demod_instance_t. +* \param pointer to struct drx_demod_instance. * \return int. * */ -static int smart_ant_init(pdrx_demod_instance_t demod) +static int smart_ant_init(struct drx_demod_instance *demod) { u16 data = 0; pdrxj_data_t ext_attr = NULL; struct i2c_device_addr *dev_addr = NULL; - drxuio_cfg_t uio_cfg = { DRX_UIO1, DRX_UIO_MODE_FIRMWARE_SMA }; + struct drxuio_cfg uio_cfg = { DRX_UIO1, DRX_UIO_MODE_FIRMWARE_SMA }; dev_addr = demod->my_i2c_dev_addr; ext_attr = (pdrxj_data_t) demod->my_ext_attr; @@ -3899,7 +3899,7 @@ rw_error: * */ static int -ctrl_set_cfg_smart_ant(pdrx_demod_instance_t demod, p_drxj_cfg_smart_ant_t smart_ant) +ctrl_set_cfg_smart_ant(struct drx_demod_instance *demod, p_drxj_cfg_smart_ant_t smart_ant) { pdrxj_data_t ext_attr = NULL; struct i2c_device_addr *dev_addr = NULL; @@ -4092,7 +4092,7 @@ rw_error: */ #define ADDR_AT_SCU_SPACE(x) ((x - 0x82E000) * 2) static -int drxj_dap_scu_atomic_read_write_block(struct i2c_device_addr *dev_addr, dr_xaddr_t addr, u16 datasize, /* max 30 bytes because the limit of SCU parameter */ +int drxj_dap_scu_atomic_read_write_block(struct i2c_device_addr *dev_addr, u32 addr, u16 datasize, /* max 30 bytes because the limit of SCU parameter */ u8 *data, bool read_flag) { drxjscu_cmd_t scu_cmd; @@ -4154,8 +4154,8 @@ rw_error: */ static int drxj_dap_scu_atomic_read_reg16(struct i2c_device_addr *dev_addr, - dr_xaddr_t addr, - u16 *data, dr_xflags_t flags) + u32 addr, + u16 *data, u32 flags) { u8 buf[2]; int rc = DRX_STS_ERROR; @@ -4181,8 +4181,8 @@ int drxj_dap_scu_atomic_read_reg16(struct i2c_device_addr *dev_addr, */ static int drxj_dap_scu_atomic_write_reg16(struct i2c_device_addr *dev_addr, - dr_xaddr_t addr, - u16 data, dr_xflags_t flags) + u32 addr, + u16 data, u32 flags) { u8 buf[2]; int rc = DRX_STS_ERROR; @@ -4196,7 +4196,7 @@ int drxj_dap_scu_atomic_write_reg16(struct i2c_device_addr *dev_addr, } static int -ctrl_i2c_write_read(pdrx_demod_instance_t demod, pdrxi2c_data_t i2c_data) +ctrl_i2c_write_read(struct drx_demod_instance *demod, struct drxi2c_data *i2c_data) { return (DRX_STS_FUNC_NOT_AVAILABLE); } @@ -4211,7 +4211,7 @@ ctrl_i2c_write_read(pdrx_demod_instance_t demod, pdrxi2c_data_t i2c_data) * \retval DRX_STS_ERROR Failure: I2C error * */ -static int adc_sync_measurement(pdrx_demod_instance_t demod, u16 *count) +static int adc_sync_measurement(struct drx_demod_instance *demod, u16 *count) { u16 data = 0; struct i2c_device_addr *dev_addr = NULL; @@ -4256,7 +4256,7 @@ rw_error: * */ -static int adc_synchronization(pdrx_demod_instance_t demod) +static int adc_synchronization(struct drx_demod_instance *demod) { u16 count = 0; struct i2c_device_addr *dev_addr = NULL; @@ -4293,7 +4293,7 @@ rw_error: * \param active * \return int. */ -static int iqm_set_af(pdrx_demod_instance_t demod, bool active) +static int iqm_set_af(struct drx_demod_instance *demod, bool active) { u16 data = 0; struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; @@ -4323,7 +4323,7 @@ rw_error: /* -------------------------------------------------------------------------- */ static int -ctrl_set_cfg_atv_output(pdrx_demod_instance_t demod, p_drxj_cfg_atv_output_t output_cfg); +ctrl_set_cfg_atv_output(struct drx_demod_instance *demod, p_drxj_cfg_atv_output_t output_cfg); /** * \brief set configuration of pin-safe mode @@ -4332,7 +4332,7 @@ ctrl_set_cfg_atv_output(pdrx_demod_instance_t demod, p_drxj_cfg_atv_output_t out * \return int. */ static int -ctrl_set_cfg_pdr_safe_mode(pdrx_demod_instance_t demod, bool *enable) +ctrl_set_cfg_pdr_safe_mode(struct drx_demod_instance *demod, bool *enable) { pdrxj_data_t ext_attr = NULL; struct i2c_device_addr *dev_addr = NULL; @@ -4455,7 +4455,7 @@ rw_error: * \return int. */ static int -ctrl_get_cfg_pdr_safe_mode(pdrx_demod_instance_t demod, bool *enabled) +ctrl_get_cfg_pdr_safe_mode(struct drx_demod_instance *demod, bool *enabled) { pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; @@ -4474,7 +4474,7 @@ ctrl_get_cfg_pdr_safe_mode(pdrx_demod_instance_t demod, bool *enabled) * \param demod Demodulator instance. * \return int. */ -static int ctrl_validate_u_code(pdrx_demod_instance_t demod) +static int ctrl_validate_u_code(struct drx_demod_instance *demod) { u32 mc_dev, mc_patch; u16 ver_type; @@ -4522,10 +4522,10 @@ static int ctrl_validate_u_code(pdrx_demod_instance_t demod) * \param channel pointer to channel data. * \return int. */ -static int init_agc(pdrx_demod_instance_t demod) +static int init_agc(struct drx_demod_instance *demod) { struct i2c_device_addr *dev_addr = NULL; - pdrx_common_attr_t common_attr = NULL; + struct drx_common_attr *common_attr = NULL; pdrxj_data_t ext_attr = NULL; p_drxj_cfg_agc_t p_agc_rf_settings = NULL; p_drxj_cfg_agc_t p_agc_if_settings = NULL; @@ -4545,7 +4545,7 @@ static int init_agc(pdrx_demod_instance_t demod) u16 agc_rf = 0; u16 agc_if = 0; dev_addr = demod->my_i2c_dev_addr; - common_attr = (pdrx_common_attr_t) demod->my_common_attr; + common_attr = (struct drx_common_attr *) demod->my_common_attr; ext_attr = (pdrxj_data_t) demod->my_ext_attr; switch (ext_attr->standard) { @@ -4730,8 +4730,8 @@ rw_error: * \return int. */ static int -set_frequency(pdrx_demod_instance_t demod, - pdrx_channel_t channel, s32 tuner_freq_offset) +set_frequency(struct drx_demod_instance *demod, + struct drx_channel *channel, s32 tuner_freq_offset) { struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; pdrxj_data_t ext_attr = demod->my_ext_attr; @@ -4833,7 +4833,7 @@ rw_error: #define DRXJ_RFAGC_MAX 0x3fff #define DRXJ_RFAGC_MIN 0x800 -static int get_sig_strength(pdrx_demod_instance_t demod, u16 *sig_strength) +static int get_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength) { struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; u16 rf_gain = 0; @@ -4888,7 +4888,7 @@ rw_error: * \retval DRX_STS_ERROR Erroneous data, sig_strength contains invalid data. */ #ifdef DRXJ_SIGNAL_ACCUM_ERR -static int get_acc_pkt_err(pdrx_demod_instance_t demod, u16 *packet_err) +static int get_acc_pkt_err(struct drx_demod_instance *demod, u16 *packet_err) { static u16 pkt_err; static u16 last_pkt_err; @@ -4929,7 +4929,7 @@ rw_error: * \retval DRX_STS_OK. * \retval DRX_STS_ERROR Erroneous data. */ -static int ctrl_set_cfg_reset_pkt_err(pdrx_demod_instance_t demod) +static int ctrl_set_cfg_reset_pkt_err(struct drx_demod_instance *demod) { #ifdef DRXJ_SIGNAL_ACCUM_ERR pdrxj_data_t ext_attr = NULL; @@ -4951,7 +4951,7 @@ rw_error: * \brief Get symbol rate offset in QAM & 8VSB mode * \return Error code */ -static int get_str_freq_offset(pdrx_demod_instance_t demod, s32 *str_freq) +static int get_str_freq_offset(struct drx_demod_instance *demod, s32 *str_freq) { u32 symbol_frequency_ratio = 0; u32 symbol_nom_frequency_ratio = 0; @@ -4984,7 +4984,7 @@ rw_error: * \brief Get the value of ctl_freq in QAM & ATSC mode * \return Error code */ -static int get_ctl_freq_offset(pdrx_demod_instance_t demod, s32 *ctl_freq) +static int get_ctl_freq_offset(struct drx_demod_instance *demod, s32 *ctl_freq) { s32 sampling_frequency = 0; s32 current_frequency = 0; @@ -4994,12 +4994,12 @@ static int get_ctl_freq_offset(pdrx_demod_instance_t demod, s32 *ctl_freq) u32 data64hi = 0; u32 data64lo = 0; pdrxj_data_t ext_attr = NULL; - pdrx_common_attr_t common_attr = NULL; + struct drx_common_attr *common_attr = NULL; struct i2c_device_addr *dev_addr = NULL; dev_addr = demod->my_i2c_dev_addr; ext_attr = (pdrxj_data_t) demod->my_ext_attr; - common_attr = (pdrx_common_attr_t) demod->my_common_attr; + common_attr = (struct drx_common_attr *) demod->my_common_attr; sampling_frequency = common_attr->sys_clock_freq / 3; @@ -5041,16 +5041,16 @@ rw_error: * \return int. */ static int -set_agc_rf(pdrx_demod_instance_t demod, p_drxj_cfg_agc_t agc_settings, bool atomic) +set_agc_rf(struct drx_demod_instance *demod, p_drxj_cfg_agc_t agc_settings, bool atomic) { struct i2c_device_addr *dev_addr = NULL; pdrxj_data_t ext_attr = NULL; p_drxj_cfg_agc_t p_agc_settings = NULL; - pdrx_common_attr_t common_attr = NULL; + struct drx_common_attr *common_attr = NULL; drx_write_reg16func_t scu_wr16 = NULL; drx_read_reg16func_t scu_rr16 = NULL; - common_attr = (pdrx_common_attr_t) demod->my_common_attr; + common_attr = (struct drx_common_attr *) demod->my_common_attr; dev_addr = demod->my_i2c_dev_addr; ext_attr = (pdrxj_data_t) demod->my_ext_attr; @@ -5219,7 +5219,7 @@ rw_error: * \return int. */ static int -get_agc_rf(pdrx_demod_instance_t demod, p_drxj_cfg_agc_t agc_settings) +get_agc_rf(struct drx_demod_instance *demod, p_drxj_cfg_agc_t agc_settings) { struct i2c_device_addr *dev_addr = NULL; pdrxj_data_t ext_attr = NULL; @@ -5280,16 +5280,16 @@ rw_error: * \return int. */ static int -set_agc_if(pdrx_demod_instance_t demod, p_drxj_cfg_agc_t agc_settings, bool atomic) +set_agc_if(struct drx_demod_instance *demod, p_drxj_cfg_agc_t agc_settings, bool atomic) { struct i2c_device_addr *dev_addr = NULL; pdrxj_data_t ext_attr = NULL; p_drxj_cfg_agc_t p_agc_settings = NULL; - pdrx_common_attr_t common_attr = NULL; + struct drx_common_attr *common_attr = NULL; drx_write_reg16func_t scu_wr16 = NULL; drx_read_reg16func_t scu_rr16 = NULL; - common_attr = (pdrx_common_attr_t) demod->my_common_attr; + common_attr = (struct drx_common_attr *) demod->my_common_attr; dev_addr = demod->my_i2c_dev_addr; ext_attr = (pdrxj_data_t) demod->my_ext_attr; @@ -5471,7 +5471,7 @@ rw_error: * \return int. */ static int -get_agc_if(pdrx_demod_instance_t demod, p_drxj_cfg_agc_t agc_settings) +get_agc_if(struct drx_demod_instance *demod, p_drxj_cfg_agc_t agc_settings) { struct i2c_device_addr *dev_addr = NULL; pdrxj_data_t ext_attr = NULL; @@ -5532,7 +5532,7 @@ rw_error: * \param active * \return int. */ -static int set_iqm_af(pdrx_demod_instance_t demod, bool active) +static int set_iqm_af(struct drx_demod_instance *demod, bool active) { u16 data = 0; struct i2c_device_addr *dev_addr = NULL; @@ -5580,7 +5580,7 @@ rw_error: * \param channel pointer to channel data. * \return int. */ -static int power_down_vsb(pdrx_demod_instance_t demod, bool primary) +static int power_down_vsb(struct drx_demod_instance *demod, bool primary) { struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; drxjscu_cmd_t cmd_scu = { /* command */ 0, @@ -5590,7 +5590,7 @@ static int power_down_vsb(pdrx_demod_instance_t demod, bool primary) /* *result */ NULL }; u16 cmd_result = 0; - drx_cfg_mpeg_output_t cfg_mpeg_output; + struct drx_cfg_mpeg_output cfg_mpeg_output; /* STOP demodulator @@ -5632,7 +5632,7 @@ rw_error: * \param demod instance of demodulator. * \return int. */ -static int set_vsb_leak_n_gain(pdrx_demod_instance_t demod) +static int set_vsb_leak_n_gain(struct drx_demod_instance *demod) { struct i2c_device_addr *dev_addr = NULL; @@ -5842,12 +5842,12 @@ rw_error: * \return int. * */ -static int set_vsb(pdrx_demod_instance_t demod) +static int set_vsb(struct drx_demod_instance *demod) { struct i2c_device_addr *dev_addr = NULL; u16 cmd_result = 0; u16 cmd_param = 0; - pdrx_common_attr_t common_attr = NULL; + struct drx_common_attr *common_attr = NULL; drxjscu_cmd_t cmd_scu; pdrxj_data_t ext_attr = NULL; const u8 vsb_taps_re[] = { @@ -5882,7 +5882,7 @@ static int set_vsb(pdrx_demod_instance_t demod) }; dev_addr = demod->my_i2c_dev_addr; - common_attr = (pdrx_common_attr_t) demod->my_common_attr; + common_attr = (struct drx_common_attr *) demod->my_common_attr; ext_attr = (pdrxj_data_t) demod->my_ext_attr; /* stop all comm_exec */ @@ -6003,7 +6003,7 @@ static int set_vsb(pdrx_demod_instance_t demod) { /* TODO: move to set_standard after hardware reset value problem is solved */ /* Configure initial MPEG output */ - drx_cfg_mpeg_output_t cfg_mpeg_output; + struct drx_cfg_mpeg_output cfg_mpeg_output; cfg_mpeg_output.enable_mpeg_output = true; cfg_mpeg_output.insert_rs_byte = common_attr->mpeg_cfg.insert_rs_byte; cfg_mpeg_output.enable_parallel = @@ -6202,7 +6202,7 @@ rw_error: * \return int. */ static int -ctrl_get_vsb_constel(pdrx_demod_instance_t demod, pdrx_complex_t complex_nr) +ctrl_get_vsb_constel(struct drx_demod_instance *demod, struct drx_complex *complex_nr) { struct i2c_device_addr *dev_addr = NULL; /**< device address */ @@ -6266,7 +6266,7 @@ rw_error: * \param channel pointer to channel data. * \return int. */ -static int power_down_qam(pdrx_demod_instance_t demod, bool primary) +static int power_down_qam(struct drx_demod_instance *demod, bool primary) { drxjscu_cmd_t cmd_scu = { /* command */ 0, /* parameter_len */ 0, @@ -6276,7 +6276,7 @@ static int power_down_qam(pdrx_demod_instance_t demod, bool primary) }; u16 cmd_result = 0; struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; - drx_cfg_mpeg_output_t cfg_mpeg_output; + struct drx_cfg_mpeg_output cfg_mpeg_output; /* STOP demodulator @@ -6333,7 +6333,7 @@ rw_error: */ #ifndef DRXJ_VSB_ONLY static int -set_qam_measurement(pdrx_demod_instance_t demod, +set_qam_measurement(struct drx_demod_instance *demod, enum drx_modulation constellation, u32 symbol_rate) { struct i2c_device_addr *dev_addr = NULL; /* device address for I2C writes */ @@ -6495,7 +6495,7 @@ rw_error: * \param demod instance of demod. * \return int. */ -static int set_qam16(pdrx_demod_instance_t demod) +static int set_qam16(struct drx_demod_instance *demod) { struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; const u8 qam_dq_qual_fun[] = { @@ -6575,7 +6575,7 @@ rw_error: * \param demod instance of demod. * \return int. */ -static int set_qam32(pdrx_demod_instance_t demod) +static int set_qam32(struct drx_demod_instance *demod) { struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; const u8 qam_dq_qual_fun[] = { @@ -6655,7 +6655,7 @@ rw_error: * \param demod instance of demod. * \return int. */ -static int set_qam64(pdrx_demod_instance_t demod) +static int set_qam64(struct drx_demod_instance *demod) { struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; const u8 qam_dq_qual_fun[] = { /* this is hw reset value. no necessary to re-write */ @@ -6735,7 +6735,7 @@ rw_error: * \param demod: instance of demod. * \return int. */ -static int set_qam128(pdrx_demod_instance_t demod) +static int set_qam128(struct drx_demod_instance *demod) { struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; const u8 qam_dq_qual_fun[] = { @@ -6815,7 +6815,7 @@ rw_error: * \param demod: instance of demod. * \return int. */ -static int set_qam256(pdrx_demod_instance_t demod) +static int set_qam256(struct drx_demod_instance *demod) { struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; const u8 qam_dq_qual_fun[] = { @@ -6900,12 +6900,12 @@ rw_error: * \return int. */ static int -set_qam(pdrx_demod_instance_t demod, - pdrx_channel_t channel, s32 tuner_freq_offset, u32 op) +set_qam(struct drx_demod_instance *demod, + struct drx_channel *channel, s32 tuner_freq_offset, u32 op) { struct i2c_device_addr *dev_addr = NULL; pdrxj_data_t ext_attr = NULL; - pdrx_common_attr_t common_attr = NULL; + struct drx_common_attr *common_attr = NULL; u16 cmd_result = 0; u32 adc_frequency = 0; u32 iqm_rc_rate = 0; @@ -7042,7 +7042,7 @@ set_qam(pdrx_demod_instance_t demod, dev_addr = demod->my_i2c_dev_addr; ext_attr = (pdrxj_data_t) demod->my_ext_attr; - common_attr = (pdrx_common_attr_t) demod->my_common_attr; + common_attr = (struct drx_common_attr *) demod->my_common_attr; if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) { if (ext_attr->standard == DRX_STANDARD_ITU_B) { @@ -7321,7 +7321,7 @@ set_qam(pdrx_demod_instance_t demod, { /* TODO: move to set_standard after hardware reset value problem is solved */ /* Configure initial MPEG output */ - drx_cfg_mpeg_output_t cfg_mpeg_output; + struct drx_cfg_mpeg_output cfg_mpeg_output; cfg_mpeg_output.enable_mpeg_output = true; cfg_mpeg_output.insert_rs_byte = @@ -7363,8 +7363,8 @@ rw_error: /*============================================================================*/ static int -ctrl_get_qam_sig_quality(pdrx_demod_instance_t demod, pdrx_sig_quality_t sig_quality); -static int qam_flip_spec(pdrx_demod_instance_t demod, pdrx_channel_t channel) +ctrl_get_qam_sig_quality(struct drx_demod_instance *demod, struct drx_sig_quality *sig_quality); +static int qam_flip_spec(struct drx_demod_instance *demod, struct drx_channel *channel) { u32 iqm_fs_rate_ofs = 0; u32 iqm_fs_rate_lo = 0; @@ -7461,11 +7461,11 @@ rw_error: * \return int. */ static int -qam64auto(pdrx_demod_instance_t demod, - pdrx_channel_t channel, - s32 tuner_freq_offset, pdrx_lock_status_t lock_status) +qam64auto(struct drx_demod_instance *demod, + struct drx_channel *channel, + s32 tuner_freq_offset, enum drx_lock_status *lock_status) { - drx_sig_quality_t sig_quality; + struct drx_sig_quality sig_quality; u16 data = 0; u32 state = NO_LOCK; u32 start_time = 0; @@ -7575,11 +7575,11 @@ rw_error: * \return int. */ static int -qam256auto(pdrx_demod_instance_t demod, - pdrx_channel_t channel, - s32 tuner_freq_offset, pdrx_lock_status_t lock_status) +qam256auto(struct drx_demod_instance *demod, + struct drx_channel *channel, + s32 tuner_freq_offset, enum drx_lock_status *lock_status) { - drx_sig_quality_t sig_quality; + struct drx_sig_quality sig_quality; u32 state = NO_LOCK; u32 start_time = 0; u32 d_locked_time = 0; @@ -7644,10 +7644,10 @@ rw_error: * \return int. */ static int -set_qamChannel(pdrx_demod_instance_t demod, - pdrx_channel_t channel, s32 tuner_freq_offset) +set_qamChannel(struct drx_demod_instance *demod, + struct drx_channel *channel, s32 tuner_freq_offset) { - drx_lock_status_t lock_status = DRX_NOT_LOCKED; + enum drx_lock_status lock_status = DRX_NOT_LOCKED; pdrxj_data_t ext_attr = NULL; bool auto_flag = false; @@ -7848,7 +7848,7 @@ rw_error: * Pre-condition: Device must be started and in lock. */ static int -ctrl_get_qam_sig_quality(pdrx_demod_instance_t demod, pdrx_sig_quality_t sig_quality) +ctrl_get_qam_sig_quality(struct drx_demod_instance *demod, struct drx_sig_quality *sig_quality) { struct i2c_device_addr *dev_addr = NULL; pdrxj_data_t ext_attr = NULL; @@ -8030,7 +8030,7 @@ rw_error: * \return int. */ static int -ctrl_get_qam_constel(pdrx_demod_instance_t demod, pdrx_complex_t complex_nr) +ctrl_get_qam_constel(struct drx_demod_instance *demod, struct drx_complex *complex_nr) { u16 fec_oc_ocr_mode = 0; /**< FEC OCR grabber configuration */ @@ -8220,7 +8220,7 @@ static int atv_equ_coef_index(enum drx_standard standard, int *index) * */ static int -atv_update_config(pdrx_demod_instance_t demod, bool force_update) +atv_update_config(struct drx_demod_instance *demod, bool force_update) { struct i2c_device_addr *dev_addr = NULL; pdrxj_data_t ext_attr = NULL; @@ -8328,7 +8328,7 @@ rw_error: * */ static int -ctrl_set_cfg_atv_output(pdrx_demod_instance_t demod, p_drxj_cfg_atv_output_t output_cfg) +ctrl_set_cfg_atv_output(struct drx_demod_instance *demod, p_drxj_cfg_atv_output_t output_cfg) { pdrxj_data_t ext_attr = NULL; @@ -8385,7 +8385,7 @@ rw_error: * */ static int -ctrl_set_cfg_atv_equ_coef(pdrx_demod_instance_t demod, p_drxj_cfg_atv_equ_coef_t coef) +ctrl_set_cfg_atv_equ_coef(struct drx_demod_instance *demod, p_drxj_cfg_atv_equ_coef_t coef) { pdrxj_data_t ext_attr = NULL; int index; @@ -8439,7 +8439,7 @@ rw_error: * */ static int -ctrl_get_cfg_atv_equ_coef(pdrx_demod_instance_t demod, p_drxj_cfg_atv_equ_coef_t coef) +ctrl_get_cfg_atv_equ_coef(struct drx_demod_instance *demod, p_drxj_cfg_atv_equ_coef_t coef) { pdrxj_data_t ext_attr = NULL; int index = 0; @@ -8477,7 +8477,7 @@ rw_error: * */ static int -ctrl_set_cfg_atv_misc(pdrx_demod_instance_t demod, p_drxj_cfg_atv_misc_t settings) +ctrl_set_cfg_atv_misc(struct drx_demod_instance *demod, p_drxj_cfg_atv_misc_t settings) { pdrxj_data_t ext_attr = NULL; @@ -8522,7 +8522,7 @@ rw_error: * regitsers. */ static int -ctrl_get_cfg_atv_misc(pdrx_demod_instance_t demod, p_drxj_cfg_atv_misc_t settings) +ctrl_get_cfg_atv_misc(struct drx_demod_instance *demod, p_drxj_cfg_atv_misc_t settings) { pdrxj_data_t ext_attr = NULL; @@ -8551,7 +8551,7 @@ ctrl_get_cfg_atv_misc(pdrx_demod_instance_t demod, p_drxj_cfg_atv_misc_t setting * */ static int -ctrl_get_cfg_atv_output(pdrx_demod_instance_t demod, p_drxj_cfg_atv_output_t output_cfg) +ctrl_get_cfg_atv_output(struct drx_demod_instance *demod, p_drxj_cfg_atv_output_t output_cfg) { u16 data = 0; @@ -8590,7 +8590,7 @@ rw_error: * */ static int -ctrl_get_cfg_atv_agc_status(pdrx_demod_instance_t demod, +ctrl_get_cfg_atv_agc_status(struct drx_demod_instance *demod, p_drxj_cfg_atv_agc_status_t agc_status) { struct i2c_device_addr *dev_addr = NULL; @@ -8691,7 +8691,7 @@ rw_error: * * Starts ATV and IQM * * AUdio already started during standard init for ATV. */ -static int power_up_atv(pdrx_demod_instance_t demod, enum drx_standard standard) +static int power_up_atv(struct drx_demod_instance *demod, enum drx_standard standard) { struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; @@ -8725,7 +8725,7 @@ rw_error: * Calls audio power down */ static int -power_down_atv(pdrx_demod_instance_t demod, enum drx_standard standard, bool primary) +power_down_atv(struct drx_demod_instance *demod, enum drx_standard standard, bool primary) { struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; drxjscu_cmd_t cmd_scu = { /* command */ 0, @@ -8783,7 +8783,7 @@ rw_error: #ifndef DRXJ_DIGITAL_ONLY #define SCU_RAM_ATV_ENABLE_IIR_WA__A 0x831F6D /* TODO remove after done with reg import */ static int -set_atv_standard(pdrx_demod_instance_t demod, enum drx_standard *standard) +set_atv_standard(struct drx_demod_instance *demod, enum drx_standard *standard) { /* TODO: enable alternative for tap settings via external file @@ -9052,8 +9052,8 @@ trouble ? u16 cmd_result = 0; u16 cmd_param = 0; #ifdef DRXJ_SPLIT_UCODE_UPLOAD - drxu_code_info_t ucode_info; - pdrx_common_attr_t common_attr = NULL; + struct drxu_code_info ucode_info; + struct drx_common_attr *common_attr = NULL; #endif /* DRXJ_SPLIT_UCODE_UPLOAD */ pdrxj_data_t ext_attr = NULL; @@ -9398,9 +9398,9 @@ rw_error: * */ static int -set_atv_channel(pdrx_demod_instance_t demod, +set_atv_channel(struct drx_demod_instance *demod, s32 tuner_freq_offset, - pdrx_channel_t channel, enum drx_standard standard) + struct drx_channel *channel, enum drx_standard standard) { drxjscu_cmd_t cmd_scu = { /* command */ 0, /* parameter_len */ 0, @@ -9465,8 +9465,8 @@ rw_error: */ #ifndef DRXJ_DIGITAL_ONLY static int -get_atv_channel(pdrx_demod_instance_t demod, - pdrx_channel_t channel, enum drx_standard standard) +get_atv_channel(struct drx_demod_instance *demod, + struct drx_channel *channel, enum drx_standard standard) { s32 offset = 0; struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; @@ -9548,7 +9548,7 @@ rw_error: * is not used ? */ static int -get_atv_sig_strength(pdrx_demod_instance_t demod, u16 *sig_strength) +get_atv_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength) { struct i2c_device_addr *dev_addr = NULL; pdrxj_data_t ext_attr = NULL; @@ -9657,7 +9657,7 @@ rw_error: * */ static int -atv_sig_quality(pdrx_demod_instance_t demod, pdrx_sig_quality_t sig_quality) +atv_sig_quality(struct drx_demod_instance *demod, struct drx_sig_quality *sig_quality) { struct i2c_device_addr *dev_addr = NULL; u16 quality_indicator = 0; @@ -9715,9 +9715,9 @@ rw_error: * \return int. * */ -static int power_up_aud(pdrx_demod_instance_t demod, bool set_standard) +static int power_up_aud(struct drx_demod_instance *demod, bool set_standard) { - drx_aud_standard_t aud_standard = DRX_AUD_STANDARD_AUTO; + enum drx_aud_standard aud_standard = DRX_AUD_STANDARD_AUTO; struct i2c_device_addr *dev_addr = NULL; dev_addr = demod->my_i2c_dev_addr; @@ -9744,7 +9744,7 @@ rw_error: * \return int. * */ -static int power_down_aud(pdrx_demod_instance_t demod) +static int power_down_aud(struct drx_demod_instance *demod) { struct i2c_device_addr *dev_addr = NULL; pdrxj_data_t ext_attr = NULL; @@ -9769,7 +9769,7 @@ rw_error: * \return int. * */ -static int aud_get_modus(pdrx_demod_instance_t demod, u16 *modus) +static int aud_get_modus(struct drx_demod_instance *demod, u16 *modus) { struct i2c_device_addr *dev_addr = NULL; pdrxj_data_t ext_attr = NULL; @@ -9810,12 +9810,11 @@ rw_error: /** * \brief Get audio RDS dat * \param demod instance of demodulator -* \param pointer to drx_cfg_aud_rds_t -* \return int. +* \param pointer to struct drx_cfg_aud_rds * \return int. * */ static int -aud_ctrl_get_cfg_rds(pdrx_demod_instance_t demod, pdrx_cfg_aud_rds_t status) +aud_ctrl_get_cfg_rds(struct drx_demod_instance *demod, struct drx_cfg_aud_rds *status) { struct i2c_device_addr *addr = NULL; pdrxj_data_t ext_attr = NULL; @@ -9885,7 +9884,7 @@ rw_error: * */ static int -aud_ctrl_get_carrier_detect_status(pdrx_demod_instance_t demod, pdrx_aud_status_t status) +aud_ctrl_get_carrier_detect_status(struct drx_demod_instance *demod, struct drx_aud_status *status) { pdrxj_data_t ext_attr = NULL; struct i2c_device_addr *dev_addr = NULL; @@ -9963,11 +9962,11 @@ rw_error: * */ static int -aud_ctrl_get_status(pdrx_demod_instance_t demod, pdrx_aud_status_t status) +aud_ctrl_get_status(struct drx_demod_instance *demod, struct drx_aud_status *status) { pdrxj_data_t ext_attr = NULL; struct i2c_device_addr *dev_addr = NULL; - drx_cfg_aud_rds_t rds = { false, {0} }; + struct drx_cfg_aud_rds rds = { false, {0} }; u16 r_data = 0; if (status == NULL) { @@ -9999,12 +9998,11 @@ rw_error: /** * \brief Get the current volume settings * \param demod instance of demodulator -* \param pointer to drx_cfg_aud_volume_t -* \return int. +* \param pointer to struct drx_cfg_aud_volume * \return int. * */ static int -aud_ctrl_get_cfg_volume(pdrx_demod_instance_t demod, pdrx_cfg_aud_volume_t volume) +aud_ctrl_get_cfg_volume(struct drx_demod_instance *demod, struct drx_cfg_aud_volume *volume) { struct i2c_device_addr *dev_addr = NULL; pdrxj_data_t ext_attr = NULL; @@ -10133,12 +10131,11 @@ rw_error: /** * \brief Set the current volume settings * \param demod instance of demodulator -* \param pointer to drx_cfg_aud_volume_t -* \return int. +* \param pointer to struct drx_cfg_aud_volume * \return int. * */ static int -aud_ctrl_set_cfg_volume(pdrx_demod_instance_t demod, pdrx_cfg_aud_volume_t volume) +aud_ctrl_set_cfg_volume(struct drx_demod_instance *demod, struct drx_cfg_aud_volume *volume) { struct i2c_device_addr *dev_addr = NULL; pdrxj_data_t ext_attr = NULL; @@ -10268,12 +10265,11 @@ rw_error: /** * \brief Get the I2S settings * \param demod instance of demodulator -* \param pointer to drx_cfg_i2s_output_t -* \return int. +* \param pointer to struct drx_cfg_i2s_output * \return int. * */ static int -aud_ctrl_get_cfg_output_i2s(pdrx_demod_instance_t demod, pdrx_cfg_i2s_output_t output) +aud_ctrl_get_cfg_output_i2s(struct drx_demod_instance *demod, struct drx_cfg_i2s_output *output) { struct i2c_device_addr *dev_addr = NULL; pdrxj_data_t ext_attr = NULL; @@ -10371,12 +10367,11 @@ rw_error: /** * \brief Set the I2S settings * \param demod instance of demodulator -* \param pointer to drx_cfg_i2s_output_t -* \return int. +* \param pointer to struct drx_cfg_i2s_output * \return int. * */ static int -aud_ctrl_set_cfg_output_i2s(pdrx_demod_instance_t demod, pdrx_cfg_i2s_output_t output) +aud_ctrl_set_cfg_output_i2s(struct drx_demod_instance *demod, struct drx_cfg_i2s_output *output) { struct i2c_device_addr *dev_addr = NULL; pdrxj_data_t ext_attr = NULL; @@ -10531,8 +10526,8 @@ rw_error: * */ static int -aud_ctrl_get_cfg_auto_sound(pdrx_demod_instance_t demod, - pdrx_cfg_aud_auto_sound_t auto_sound) +aud_ctrl_get_cfg_auto_sound(struct drx_demod_instance *demod, + enum drx_cfg_aud_auto_sound *auto_sound) { pdrxj_data_t ext_attr = NULL; u16 r_modus = 0; @@ -10584,8 +10579,8 @@ rw_error: * */ static int -aud_ctr_setl_cfg_auto_sound(pdrx_demod_instance_t demod, - pdrx_cfg_aud_auto_sound_t auto_sound) +aud_ctr_setl_cfg_auto_sound(struct drx_demod_instance *demod, + enum drx_cfg_aud_auto_sound *auto_sound) { struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; @@ -10650,7 +10645,7 @@ rw_error: * */ static int -aud_ctrl_get_cfg_ass_thres(pdrx_demod_instance_t demod, pdrx_cfg_aud_ass_thres_t thres) +aud_ctrl_get_cfg_ass_thres(struct drx_demod_instance *demod, struct drx_cfg_aud_ass_thres *thres) { struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; @@ -10694,7 +10689,7 @@ rw_error: * */ static int -aud_ctrl_set_cfg_ass_thres(pdrx_demod_instance_t demod, pdrx_cfg_aud_ass_thres_t thres) +aud_ctrl_set_cfg_ass_thres(struct drx_demod_instance *demod, struct drx_cfg_aud_ass_thres *thres) { struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; @@ -10728,12 +10723,11 @@ rw_error: /** * \brief Get Audio Carrier settings * \param demod instance of demodulator -* \param pointer to pdrx_aud_carrier_t -* \return int. +* \param pointer to struct drx_aud_carrier ** \return int. * */ static int -aud_ctrl_get_cfg_carrier(pdrx_demod_instance_t demod, pdrx_cfg_aud_carriers_t carriers) +aud_ctrl_get_cfg_carrier(struct drx_demod_instance *demod, struct drx_cfg_aud_carriers *carriers) { struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; @@ -10833,12 +10827,11 @@ rw_error: /** * \brief Set Audio Carrier settings * \param demod instance of demodulator -* \param pointer to pdrx_aud_carrier_t -* \return int. +* \param pointer to struct drx_aud_carrier ** \return int. * */ static int -aud_ctrl_set_cfg_carrier(pdrx_demod_instance_t demod, pdrx_cfg_aud_carriers_t carriers) +aud_ctrl_set_cfg_carrier(struct drx_demod_instance *demod, struct drx_cfg_aud_carriers *carriers) { struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; @@ -10938,7 +10931,7 @@ rw_error: * */ static int -aud_ctrl_get_cfg_mixer(pdrx_demod_instance_t demod, pdrx_cfg_aud_mixer_t mixer) +aud_ctrl_get_cfg_mixer(struct drx_demod_instance *demod, struct drx_cfg_aud_mixer *mixer) { struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; @@ -11033,7 +11026,7 @@ rw_error: * */ static int -aud_ctrl_set_cfg_mixer(pdrx_demod_instance_t demod, pdrx_cfg_aud_mixer_t mixer) +aud_ctrl_set_cfg_mixer(struct drx_demod_instance *demod, struct drx_cfg_aud_mixer *mixer) { struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; @@ -11141,7 +11134,7 @@ rw_error: * */ static int -aud_ctrl_set_cfg_av_sync(pdrx_demod_instance_t demod, pdrx_cfg_aud_av_sync_t av_sync) +aud_ctrl_set_cfg_av_sync(struct drx_demod_instance *demod, enum drx_cfg_aud_av_sync *av_sync) { struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; @@ -11206,7 +11199,7 @@ rw_error: * */ static int -aud_ctrl_get_cfg_av_sync(pdrx_demod_instance_t demod, pdrx_cfg_aud_av_sync_t av_sync) +aud_ctrl_get_cfg_av_sync(struct drx_demod_instance *demod, enum drx_cfg_aud_av_sync *av_sync) { struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; @@ -11258,12 +11251,11 @@ rw_error: /** * \brief Get deviation mode * \param demod instance of demodulator -* \param pointer to drx_cfg_aud_deviation_t -* \return int. +* \param pointer to enum drx_cfg_aud_deviation * \return int. * */ static int -aud_ctrl_get_cfg_dev(pdrx_demod_instance_t demod, pdrx_cfg_aud_deviation_t dev) +aud_ctrl_get_cfg_dev(struct drx_demod_instance *demod, enum drx_cfg_aud_deviation *dev) { u16 r_modus = 0; @@ -11292,12 +11284,11 @@ rw_error: /** * \brief Get deviation mode * \param demod instance of demodulator -* \param pointer to drx_cfg_aud_deviation_t -* \return int. +* \param pointer to enum drx_cfg_aud_deviation * \return int. * */ static int -aud_ctrl_set_cfg_dev(pdrx_demod_instance_t demod, pdrx_cfg_aud_deviation_t dev) +aud_ctrl_set_cfg_dev(struct drx_demod_instance *demod, enum drx_cfg_aud_deviation *dev) { struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; @@ -11345,12 +11336,11 @@ rw_error: /** * \brief Get Prescaler settings * \param demod instance of demodulator -* \param pointer to drx_cfg_aud_prescale_t -* \return int. +* \param pointer to struct drx_cfg_aud_prescale * \return int. * */ static int -aud_ctrl_get_cfg_prescale(pdrx_demod_instance_t demod, pdrx_cfg_aud_prescale_t presc) +aud_ctrl_get_cfg_prescale(struct drx_demod_instance *demod, struct drx_cfg_aud_prescale *presc) { struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; @@ -11420,12 +11410,11 @@ rw_error: /** * \brief Set Prescaler settings * \param demod instance of demodulator -* \param pointer to drx_cfg_aud_prescale_t -* \return int. +* \param pointer to struct drx_cfg_aud_prescale * \return int. * */ static int -aud_ctrl_set_cfg_prescale(pdrx_demod_instance_t demod, pdrx_cfg_aud_prescale_t presc) +aud_ctrl_set_cfg_prescale(struct drx_demod_instance *demod, struct drx_cfg_aud_prescale *presc) { struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; @@ -11503,11 +11492,10 @@ rw_error: /** * \brief Beep * \param demod instance of demodulator -* \param pointer to drx_aud_beep_t -* \return int. +* \param pointer to struct drx_aud_beep * \return int. * */ -static int aud_ctrl_beep(pdrx_demod_instance_t demod, pdrx_aud_beep_t beep) +static int aud_ctrl_beep(struct drx_demod_instance *demod, struct drx_aud_beep *beep) { struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; @@ -11561,12 +11549,11 @@ rw_error: /** * \brief Set an audio standard * \param demod instance of demodulator -* \param pointer to drx_aud_standard_t -* \return int. +* \param pointer to enum drx_aud_standard * \return int. * */ static int -aud_ctrl_set_standard(pdrx_demod_instance_t demod, pdrx_aud_standard_t standard) +aud_ctrl_set_standard(struct drx_demod_instance *demod, enum drx_aud_standard *standard) { struct i2c_device_addr *dev_addr = NULL; pdrxj_data_t ext_attr = NULL; @@ -11739,12 +11726,11 @@ rw_error: /** * \brief Get the current audio standard * \param demod instance of demodulator -* \param pointer to drx_aud_standard_t -* \return int. +* \param pointer to enum drx_aud_standard * \return int. * */ static int -aud_ctrl_get_standard(pdrx_demod_instance_t demod, pdrx_aud_standard_t standard) +aud_ctrl_get_standard(struct drx_demod_instance *demod, enum drx_aud_standard *standard) { struct i2c_device_addr *dev_addr = NULL; pdrxj_data_t ext_attr = NULL; @@ -11851,9 +11837,9 @@ rw_error: * */ static int -fm_lock_status(pdrx_demod_instance_t demod, pdrx_lock_status_t lock_stat) +fm_lock_status(struct drx_demod_instance *demod, enum drx_lock_status *lock_stat) { - drx_aud_status_t status; + struct drx_aud_status status; /* Check detection of audio carriers */ CHK_ERROR(aud_ctrl_get_carrier_detect_status(demod, &status)); @@ -11883,9 +11869,9 @@ rw_error: * */ static int -fm_sig_quality(pdrx_demod_instance_t demod, pdrx_sig_quality_t sig_quality) +fm_sig_quality(struct drx_demod_instance *demod, struct drx_sig_quality *sig_quality) { - drx_lock_status_t lock_status = DRX_NOT_LOCKED; + enum drx_lock_status lock_status = DRX_NOT_LOCKED; CHK_ERROR(fm_lock_status(demod, &lock_status)); if (lock_status == DRX_LOCKED) { @@ -11923,8 +11909,8 @@ rw_error: * */ static int -get_oob_lock_status(pdrx_demod_instance_t demod, - struct i2c_device_addr *dev_addr, pdrx_lock_status_t oob_lock) +get_oob_lock_status(struct drx_demod_instance *demod, + struct i2c_device_addr *dev_addr, enum drx_lock_status *oob_lock) { drxjscu_cmd_t scu_cmd; u16 cmd_result[2]; @@ -12059,7 +12045,7 @@ rw_error: * */ static int -get_oob_freq_offset(pdrx_demod_instance_t demod, s32 *freq_offset) +get_oob_freq_offset(struct drx_demod_instance *demod, s32 *freq_offset) { u16 data = 0; u16 rot = 0; @@ -12072,7 +12058,7 @@ get_oob_freq_offset(pdrx_demod_instance_t demod, s32 *freq_offset) u32 data64hi = 0; u32 data64lo = 0; u32 temp_freq_offset = 0; - pdrx_common_attr_t common_attr = (pdrx_common_attr_t) (NULL); + struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL); struct i2c_device_addr *dev_addr = NULL; /* check arguments */ @@ -12081,7 +12067,7 @@ get_oob_freq_offset(pdrx_demod_instance_t demod, s32 *freq_offset) } dev_addr = demod->my_i2c_dev_addr; - common_attr = (pdrx_common_attr_t) demod->my_common_attr; + common_attr = (struct drx_common_attr *) demod->my_common_attr; *freq_offset = 0; @@ -12160,7 +12146,7 @@ rw_error: * */ static int -get_oob_frequency(pdrx_demod_instance_t demod, s32 *frequency) +get_oob_frequency(struct drx_demod_instance *demod, s32 *frequency) { u16 data = 0; s32 freq_offset = 0; @@ -12335,7 +12321,7 @@ rw_error: * \param active * \return int. */ -static int set_orx_nsu_aox(pdrx_demod_instance_t demod, bool active) +static int set_orx_nsu_aox(struct drx_demod_instance *demod, bool active) { u16 data = 0; struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; @@ -12394,7 +12380,7 @@ rw_error: /* Coefficients for the nyquist fitler (total: 27 taps) */ #define NYQFILTERLEN 27 -static int ctrl_set_oob(pdrx_demod_instance_t demod, p_drxoob_t oob_param) +static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_param) { #ifndef DRXJ_DIGITAL_ONLY s32 freq = 0; /* KHz */ @@ -12667,7 +12653,7 @@ rw_error: * \return int. */ static int -ctrl_get_oob(pdrx_demod_instance_t demod, pdrxoob_status_t oob_status) +ctrl_get_oob(struct drx_demod_instance *demod, struct drxoob_status *oob_status) { #ifndef DRXJ_DIGITAL_ONLY struct i2c_device_addr *dev_addr = NULL; @@ -12711,7 +12697,7 @@ rw_error: */ #ifndef DRXJ_DIGITAL_ONLY static int -ctrl_set_cfg_oob_pre_saw(pdrx_demod_instance_t demod, u16 *cfg_data) +ctrl_set_cfg_oob_pre_saw(struct drx_demod_instance *demod, u16 *cfg_data) { struct i2c_device_addr *dev_addr = NULL; pdrxj_data_t ext_attr = NULL; @@ -12738,7 +12724,7 @@ rw_error: */ #ifndef DRXJ_DIGITAL_ONLY static int -ctrl_get_cfg_oob_pre_saw(pdrx_demod_instance_t demod, u16 *cfg_data) +ctrl_get_cfg_oob_pre_saw(struct drx_demod_instance *demod, u16 *cfg_data) { pdrxj_data_t ext_attr = NULL; @@ -12761,7 +12747,7 @@ ctrl_get_cfg_oob_pre_saw(pdrx_demod_instance_t demod, u16 *cfg_data) */ #ifndef DRXJ_DIGITAL_ONLY static int -ctrl_set_cfg_oob_lo_power(pdrx_demod_instance_t demod, p_drxj_cfg_oob_lo_power_t cfg_data) +ctrl_set_cfg_oob_lo_power(struct drx_demod_instance *demod, p_drxj_cfg_oob_lo_power_t cfg_data) { struct i2c_device_addr *dev_addr = NULL; pdrxj_data_t ext_attr = NULL; @@ -12788,7 +12774,7 @@ rw_error: */ #ifndef DRXJ_DIGITAL_ONLY static int -ctrl_get_cfg_oob_lo_power(pdrx_demod_instance_t demod, p_drxj_cfg_oob_lo_power_t cfg_data) +ctrl_get_cfg_oob_lo_power(struct drx_demod_instance *demod, p_drxj_cfg_oob_lo_power_t cfg_data) { pdrxj_data_t ext_attr = NULL; @@ -12825,7 +12811,7 @@ ctrl_get_cfg_oob_lo_power(pdrx_demod_instance_t demod, p_drxj_cfg_oob_lo_power_t * */ static int -ctrl_set_channel(pdrx_demod_instance_t demod, pdrx_channel_t channel) +ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) { s32 tuner_set_freq = 0; @@ -12836,7 +12822,7 @@ ctrl_set_channel(pdrx_demod_instance_t demod, pdrx_channel_t channel) struct i2c_device_addr *dev_addr = NULL; enum drx_standard standard = DRX_STANDARD_UNKNOWN; u32 tuner_mode = 0; - pdrx_common_attr_t common_attr = NULL; + struct drx_common_attr *common_attr = NULL; bool bridge_closed = false; #ifndef DRXJ_VSB_ONLY u32 min_symbol_rate = 0; @@ -12849,7 +12835,7 @@ ctrl_set_channel(pdrx_demod_instance_t demod, pdrx_channel_t channel) return DRX_STS_INVALID_ARG; } - common_attr = (pdrx_common_attr_t) demod->my_common_attr; + common_attr = (struct drx_common_attr *) demod->my_common_attr; dev_addr = demod->my_i2c_dev_addr; ext_attr = (pdrxj_data_t) demod->my_ext_attr; standard = ext_attr->standard; @@ -12931,7 +12917,7 @@ ctrl_set_channel(pdrx_demod_instance_t demod, pdrx_channel_t channel) #ifndef DRXJ_VSB_ONLY if ((standard == DRX_STANDARD_ITU_A) || (standard == DRX_STANDARD_ITU_C)) { - drxuio_cfg_t uio_cfg = { DRX_UIO1, DRX_UIO_MODE_FIRMWARE_SAW }; + struct drxuio_cfg uio_cfg = { DRX_UIO1, DRX_UIO_MODE_FIRMWARE_SAW }; int bw_rolloff_factor = 0; bw_rolloff_factor = (standard == DRX_STANDARD_ITU_A) ? 115 : 113; @@ -13013,7 +12999,7 @@ ctrl_set_channel(pdrx_demod_instance_t demod, pdrx_channel_t channel) if ((ext_attr->uio_sma_tx_mode) == DRX_UIO_MODE_FIRMWARE_SAW) { /* SAW SW, user UIO is used for switchable SAW */ - drxuio_data_t uio1 = { DRX_UIO1, false }; + struct drxuio_data uio1 = { DRX_UIO1, false }; switch (channel->bandwidth) { case DRX_BANDWIDTH_8MHZ: @@ -13207,13 +13193,13 @@ rw_error: * \return int. */ static int -ctrl_get_channel(pdrx_demod_instance_t demod, pdrx_channel_t channel) +ctrl_get_channel(struct drx_demod_instance *demod, struct drx_channel *channel) { struct i2c_device_addr *dev_addr = NULL; pdrxj_data_t ext_attr = NULL; - drx_lock_status_t lock_status = DRX_NOT_LOCKED; + enum drx_lock_status lock_status = DRX_NOT_LOCKED; enum drx_standard standard = DRX_STANDARD_UNKNOWN; - pdrx_common_attr_t common_attr = NULL; + struct drx_common_attr *common_attr = NULL; s32 intermediate_freq = 0; s32 ctl_freq_offset = 0; u32 iqm_rc_rateLo = 0; @@ -13231,7 +13217,7 @@ ctrl_get_channel(pdrx_demod_instance_t demod, pdrx_channel_t channel) dev_addr = demod->my_i2c_dev_addr; ext_attr = (pdrxj_data_t) demod->my_ext_attr; standard = ext_attr->standard; - common_attr = (pdrx_common_attr_t) demod->my_common_attr; + common_attr = (struct drx_common_attr *) demod->my_common_attr; /* initialize channel fields */ channel->mirror = DRX_MIRROR_UNKNOWN; @@ -13458,12 +13444,12 @@ mer2indicator(u16 mer, u16 min_mer, u16 threshold_mer, u16 max_mer) */ static int -ctrl_sig_quality(pdrx_demod_instance_t demod, pdrx_sig_quality_t sig_quality) +ctrl_sig_quality(struct drx_demod_instance *demod, struct drx_sig_quality *sig_quality) { struct i2c_device_addr *dev_addr = NULL; pdrxj_data_t ext_attr = NULL; enum drx_standard standard = DRX_STANDARD_UNKNOWN; - drx_lock_status_t lock_status = DRX_NOT_LOCKED; + enum drx_lock_status lock_status = DRX_NOT_LOCKED; u16 min_mer = 0; u16 max_mer = 0; u16 threshold_mer = 0; @@ -13592,7 +13578,7 @@ rw_error: * */ static int -ctrl_lock_status(pdrx_demod_instance_t demod, pdrx_lock_status_t lock_stat) +ctrl_lock_status(struct drx_demod_instance *demod, enum drx_lock_status *lock_stat) { enum drx_standard standard = DRX_STANDARD_UNKNOWN; pdrxj_data_t ext_attr = NULL; @@ -13689,7 +13675,7 @@ rw_error: * \return int. */ static int -ctrl_constel(pdrx_demod_instance_t demod, pdrx_complex_t complex_nr) +ctrl_constel(struct drx_demod_instance *demod, struct drx_complex *complex_nr) { enum drx_standard standard = DRX_STANDARD_UNKNOWN; /**< active standard */ @@ -13737,7 +13723,7 @@ rw_error: * */ static int -ctrl_set_standard(pdrx_demod_instance_t demod, enum drx_standard *standard) +ctrl_set_standard(struct drx_demod_instance *demod, enum drx_standard *standard) { pdrxj_data_t ext_attr = NULL; enum drx_standard prev_standard; @@ -13837,7 +13823,7 @@ rw_error: * */ static int -ctrl_get_standard(pdrx_demod_instance_t demod, enum drx_standard *standard) +ctrl_get_standard(struct drx_demod_instance *demod, enum drx_standard *standard) { pdrxj_data_t ext_attr = NULL; ext_attr = (pdrxj_data_t) demod->my_ext_attr; @@ -13864,7 +13850,7 @@ rw_error: * */ static int -ctrl_get_cfg_symbol_clock_offset(pdrx_demod_instance_t demod, s32 *rate_offset) +ctrl_get_cfg_symbol_clock_offset(struct drx_demod_instance *demod, s32 *rate_offset) { enum drx_standard standard = DRX_STANDARD_UNKNOWN; pdrxj_data_t ext_attr = NULL; @@ -13911,14 +13897,14 @@ rw_error: * */ static int -ctrl_power_mode(pdrx_demod_instance_t demod, pdrx_power_mode_t mode) +ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode) { - pdrx_common_attr_t common_attr = (pdrx_common_attr_t) NULL; + struct drx_common_attr *common_attr = (struct drx_common_attr *) NULL; pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; u16 sio_cc_pwd_mode = 0; - common_attr = (pdrx_common_attr_t) demod->my_common_attr; + common_attr = (struct drx_common_attr *) demod->my_common_attr; ext_attr = (pdrxj_data_t) demod->my_ext_attr; dev_addr = demod->my_i2c_dev_addr; @@ -14039,11 +14025,11 @@ rw_error: * */ static int -ctrl_version(pdrx_demod_instance_t demod, p_drx_version_list_t *version_list) +ctrl_version(struct drx_demod_instance *demod, struct drx_version_list **version_list) { pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); - pdrx_common_attr_t common_attr = (pdrx_common_attr_t) (NULL); + struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL); u16 ucode_major_minor = 0; /* BCD Ma:Ma:Ma:Mi */ u16 ucode_patch = 0; /* BCD Pa:Pa:Pa:Pa */ u16 major = 0; @@ -14061,7 +14047,7 @@ ctrl_version(pdrx_demod_instance_t demod, p_drx_version_list_t *version_list) dev_addr = demod->my_i2c_dev_addr; ext_attr = (pdrxj_data_t) demod->my_ext_attr; - common_attr = (pdrx_common_attr_t) demod->my_common_attr; + common_attr = (struct drx_common_attr *) demod->my_common_attr; /* Microcode version *************************************** */ @@ -14163,14 +14149,14 @@ ctrl_version(pdrx_demod_instance_t demod, p_drx_version_list_t *version_list) } ext_attr->v_list_elements[1].version = &(ext_attr->v_version[1]); - ext_attr->v_list_elements[1].next = (p_drx_version_list_t) (NULL); + ext_attr->v_list_elements[1].next = (struct drx_version_list *) (NULL); *version_list = &(ext_attr->v_list_elements[0]); return (DRX_STS_OK); rw_error: - *version_list = (p_drx_version_list_t) (NULL); + *version_list = (struct drx_version_list *) (NULL); return (DRX_STS_ERROR); } @@ -14189,18 +14175,18 @@ rw_error: * */ -static int ctrl_probe_device(pdrx_demod_instance_t demod) +static int ctrl_probe_device(struct drx_demod_instance *demod) { - drx_power_mode_t org_power_mode = DRX_POWER_UP; + enum drx_power_mode org_power_mode = DRX_POWER_UP; int ret_status = DRX_STS_OK; - pdrx_common_attr_t common_attr = (pdrx_common_attr_t) (NULL); + struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL); - common_attr = (pdrx_common_attr_t) demod->my_common_attr; + common_attr = (struct drx_common_attr *) demod->my_common_attr; if (common_attr->is_opened == false || common_attr->current_power_mode != DRX_POWER_UP) { struct i2c_device_addr *dev_addr = NULL; - drx_power_mode_t power_mode = DRX_POWER_UP; + enum drx_power_mode power_mode = DRX_POWER_UP; u32 jtag = 0; dev_addr = demod->my_i2c_dev_addr; @@ -14287,9 +14273,9 @@ bool is_mc_block_audio(u32 addr) * \return int. */ static int -ctrl_u_codeUpload(pdrx_demod_instance_t demod, - p_drxu_code_info_t mc_info, - drxu_code_action_t action, bool upload_audio_mc) +ctrl_u_codeUpload(struct drx_demod_instance *demod, + struct drxu_code_info *mc_info, + enum drxu_code_actionaction, bool upload_audio_mc) { u16 i = 0; u16 mc_nr_of_blks = 0; @@ -14379,7 +14365,7 @@ ctrl_u_codeUpload(pdrx_demod_instance_t demod, [DRXJ_UCODE_MAX_BUF_SIZE]; u32 bytes_to_compare = 0; u32 bytes_left_to_compare = 0; - dr_xaddr_t curr_addr = (dr_xaddr_t) 0; + u32 curr_addr = (dr_xaddr_t) 0; u8 *curr_ptr = NULL; bytes_left_to_compare = mc_block_nr_bytes; @@ -14468,7 +14454,7 @@ ctrl_u_codeUpload(pdrx_demod_instance_t demod, */ static int -ctrl_sig_strength(pdrx_demod_instance_t demod, u16 *sig_strength) +ctrl_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength) { pdrxj_data_t ext_attr = NULL; enum drx_standard standard = DRX_STANDARD_UNKNOWN; @@ -14525,7 +14511,7 @@ rw_error: */ #ifndef DRXJ_DIGITAL_ONLY static int -ctrl_get_cfg_oob_misc(pdrx_demod_instance_t demod, p_drxj_cfg_oob_misc_t misc) +ctrl_get_cfg_oob_misc(struct drx_demod_instance *demod, p_drxj_cfg_oob_misc_t misc) { struct i2c_device_addr *dev_addr = NULL; u16 lock = 0U; @@ -14577,7 +14563,7 @@ rw_error: * */ static int -ctrl_get_cfg_vsb_misc(pdrx_demod_instance_t demod, p_drxj_cfg_vsb_misc_t misc) +ctrl_get_cfg_vsb_misc(struct drx_demod_instance *demod, p_drxj_cfg_vsb_misc_t misc) { struct i2c_device_addr *dev_addr = NULL; @@ -14608,7 +14594,7 @@ rw_error: * */ static int -ctrl_set_cfg_agc_if(pdrx_demod_instance_t demod, p_drxj_cfg_agc_t agc_settings) +ctrl_set_cfg_agc_if(struct drx_demod_instance *demod, p_drxj_cfg_agc_t agc_settings) { /* check arguments */ if (agc_settings == NULL) { @@ -14664,7 +14650,7 @@ ctrl_set_cfg_agc_if(pdrx_demod_instance_t demod, p_drxj_cfg_agc_t agc_settings) * */ static int -ctrl_get_cfg_agc_if(pdrx_demod_instance_t demod, p_drxj_cfg_agc_t agc_settings) +ctrl_get_cfg_agc_if(struct drx_demod_instance *demod, p_drxj_cfg_agc_t agc_settings) { /* check arguments */ if (agc_settings == NULL) { @@ -14711,7 +14697,7 @@ ctrl_get_cfg_agc_if(pdrx_demod_instance_t demod, p_drxj_cfg_agc_t agc_settings) * */ static int -ctrl_set_cfg_agc_rf(pdrx_demod_instance_t demod, p_drxj_cfg_agc_t agc_settings) +ctrl_set_cfg_agc_rf(struct drx_demod_instance *demod, p_drxj_cfg_agc_t agc_settings) { /* check arguments */ if (agc_settings == NULL) { @@ -14767,7 +14753,7 @@ ctrl_set_cfg_agc_rf(pdrx_demod_instance_t demod, p_drxj_cfg_agc_t agc_settings) * */ static int -ctrl_get_cfg_agc_rf(pdrx_demod_instance_t demod, p_drxj_cfg_agc_t agc_settings) +ctrl_get_cfg_agc_rf(struct drx_demod_instance *demod, p_drxj_cfg_agc_t agc_settings) { /* check arguments */ if (agc_settings == NULL) { @@ -14814,10 +14800,10 @@ ctrl_get_cfg_agc_rf(pdrx_demod_instance_t demod, p_drxj_cfg_agc_t agc_settings) * */ static int -ctrl_get_cfg_agc_internal(pdrx_demod_instance_t demod, u16 *agc_internal) +ctrl_get_cfg_agc_internal(struct drx_demod_instance *demod, u16 *agc_internal) { struct i2c_device_addr *dev_addr = NULL; - drx_lock_status_t lock_status = DRX_NOT_LOCKED; + enum drx_lock_status lock_status = DRX_NOT_LOCKED; pdrxj_data_t ext_attr = NULL; u16 iqm_cf_scale_sh = 0; u16 iqm_cf_power = 0; @@ -14897,7 +14883,7 @@ rw_error: * */ static int -ctrl_set_cfg_pre_saw(pdrx_demod_instance_t demod, p_drxj_cfg_pre_saw_t pre_saw) +ctrl_set_cfg_pre_saw(struct drx_demod_instance *demod, p_drxj_cfg_pre_saw_t pre_saw) { struct i2c_device_addr *dev_addr = NULL; pdrxj_data_t ext_attr = NULL; @@ -14966,7 +14952,7 @@ rw_error: * */ static int -ctrl_set_cfg_afe_gain(pdrx_demod_instance_t demod, p_drxj_cfg_afe_gain_t afe_gain) +ctrl_set_cfg_afe_gain(struct drx_demod_instance *demod, p_drxj_cfg_afe_gain_t afe_gain) { struct i2c_device_addr *dev_addr = NULL; pdrxj_data_t ext_attr = NULL; @@ -15042,7 +15028,7 @@ rw_error: * */ static int -ctrl_get_cfg_pre_saw(pdrx_demod_instance_t demod, p_drxj_cfg_pre_saw_t pre_saw) +ctrl_get_cfg_pre_saw(struct drx_demod_instance *demod, p_drxj_cfg_pre_saw_t pre_saw) { pdrxj_data_t ext_attr = NULL; @@ -15099,7 +15085,7 @@ ctrl_get_cfg_pre_saw(pdrx_demod_instance_t demod, p_drxj_cfg_pre_saw_t pre_saw) * */ static int -ctrl_get_cfg_afe_gain(pdrx_demod_instance_t demod, p_drxj_cfg_afe_gain_t afe_gain) +ctrl_get_cfg_afe_gain(struct drx_demod_instance *demod, p_drxj_cfg_afe_gain_t afe_gain) { pdrxj_data_t ext_attr = NULL; @@ -15141,7 +15127,7 @@ ctrl_get_cfg_afe_gain(pdrx_demod_instance_t demod, p_drxj_cfg_afe_gain_t afe_gai * */ static int -ctrl_get_fec_meas_seq_count(pdrx_demod_instance_t demod, u16 *fec_meas_seq_count) +ctrl_get_fec_meas_seq_count(struct drx_demod_instance *demod, u16 *fec_meas_seq_count) { /* check arguments */ if (fec_meas_seq_count == NULL) { @@ -15169,7 +15155,7 @@ rw_error: * */ static int -ctrl_get_accum_cr_rs_cw_err(pdrx_demod_instance_t demod, u32 *accum_cr_rs_cw_err) +ctrl_get_accum_cr_rs_cw_err(struct drx_demod_instance *demod, u32 *accum_cr_rs_cw_err) { if (accum_cr_rs_cw_err == NULL) { return (DRX_STS_INVALID_ARG); @@ -15191,7 +15177,7 @@ rw_error: * \return int. */ -static int ctrl_set_cfg(pdrx_demod_instance_t demod, pdrx_cfg_t config) +static int ctrl_set_cfg(struct drx_demod_instance *demod, struct drx_cfg *config) { if (config == NULL) { return (DRX_STS_INVALID_ARG); @@ -15201,7 +15187,7 @@ static int ctrl_set_cfg(pdrx_demod_instance_t demod, pdrx_cfg_t config) switch (config->cfg_type) { case DRX_CFG_MPEG_OUTPUT: return ctrl_set_cfg_mpeg_output(demod, - (pdrx_cfg_mpeg_output_t) config-> + (struct drx_cfg_mpeg_output *) config-> cfg_data); case DRX_CFG_PINS_SAFE_MODE: return ctrl_set_cfg_pdr_safe_mode(demod, (bool *)config->cfg_data); @@ -15247,36 +15233,36 @@ static int ctrl_set_cfg(pdrx_demod_instance_t demod, pdrx_cfg_t config) #ifndef DRXJ_EXCLUDE_AUDIO case DRX_CFG_AUD_VOLUME: return aud_ctrl_set_cfg_volume(demod, - (pdrx_cfg_aud_volume_t) config-> + (struct drx_cfg_aud_volume *) config-> cfg_data); case DRX_CFG_I2S_OUTPUT: return aud_ctrl_set_cfg_output_i2s(demod, - (pdrx_cfg_i2s_output_t) config-> + (struct drx_cfg_i2s_output *) config-> cfg_data); case DRX_CFG_AUD_AUTOSOUND: - return aud_ctr_setl_cfg_auto_sound(demod, (pdrx_cfg_aud_auto_sound_t) + return aud_ctr_setl_cfg_auto_sound(demod, (enum drx_cfg_aud_auto_sound *) config->cfg_data); case DRX_CFG_AUD_ASS_THRES: - return aud_ctrl_set_cfg_ass_thres(demod, (pdrx_cfg_aud_ass_thres_t) + return aud_ctrl_set_cfg_ass_thres(demod, (struct drx_cfg_aud_ass_thres *) config->cfg_data); case DRX_CFG_AUD_CARRIER: return aud_ctrl_set_cfg_carrier(demod, - (pdrx_cfg_aud_carriers_t) config-> + (struct drx_cfg_aud_carriers *) config-> cfg_data); case DRX_CFG_AUD_DEVIATION: return aud_ctrl_set_cfg_dev(demod, - (pdrx_cfg_aud_deviation_t) config-> + (enum drx_cfg_aud_deviation *) config-> cfg_data); case DRX_CFG_AUD_PRESCALE: return aud_ctrl_set_cfg_prescale(demod, - (pdrx_cfg_aud_prescale_t) config-> + (struct drx_cfg_aud_prescale *) config-> cfg_data); case DRX_CFG_AUD_MIXER: return aud_ctrl_set_cfg_mixer(demod, - (pdrx_cfg_aud_mixer_t) config->cfg_data); + (struct drx_cfg_aud_mixer *) config->cfg_data); case DRX_CFG_AUD_AVSYNC: return aud_ctrl_set_cfg_av_sync(demod, - (pdrx_cfg_aud_av_sync_t) config-> + (enum drx_cfg_aud_av_sync *) config-> cfg_data); #endif @@ -15299,7 +15285,7 @@ rw_error: * \return int. */ -static int ctrl_get_cfg(pdrx_demod_instance_t demod, pdrx_cfg_t config) +static int ctrl_get_cfg(struct drx_demod_instance *demod, struct drx_cfg *config) { if (config == NULL) { return (DRX_STS_INVALID_ARG); @@ -15310,7 +15296,7 @@ static int ctrl_get_cfg(pdrx_demod_instance_t demod, pdrx_cfg_t config) switch (config->cfg_type) { case DRX_CFG_MPEG_OUTPUT: return ctrl_get_cfg_mpeg_output(demod, - (pdrx_cfg_mpeg_output_t) config-> + (struct drx_cfg_mpeg_output *) config-> cfg_data); case DRX_CFG_PINS_SAFE_MODE: return ctrl_get_cfg_pdr_safe_mode(demod, (bool *)config->cfg_data); @@ -15372,42 +15358,42 @@ static int ctrl_get_cfg(pdrx_demod_instance_t demod, pdrx_cfg_t config) #ifndef DRXJ_EXCLUDE_AUDIO case DRX_CFG_AUD_VOLUME: return aud_ctrl_get_cfg_volume(demod, - (pdrx_cfg_aud_volume_t) config-> + (struct drx_cfg_aud_volume *) config-> cfg_data); case DRX_CFG_I2S_OUTPUT: return aud_ctrl_get_cfg_output_i2s(demod, - (pdrx_cfg_i2s_output_t) config-> + (struct drx_cfg_i2s_output *) config-> cfg_data); case DRX_CFG_AUD_RDS: return aud_ctrl_get_cfg_rds(demod, - (pdrx_cfg_aud_rds_t) config->cfg_data); + (struct drx_cfg_aud_rds *) config->cfg_data); case DRX_CFG_AUD_AUTOSOUND: return aud_ctrl_get_cfg_auto_sound(demod, - (pdrx_cfg_aud_auto_sound_t) config-> + (enum drx_cfg_aud_auto_sound *) config-> cfg_data); case DRX_CFG_AUD_ASS_THRES: return aud_ctrl_get_cfg_ass_thres(demod, - (pdrx_cfg_aud_ass_thres_t) config-> + (struct drx_cfg_aud_ass_thres *) config-> cfg_data); case DRX_CFG_AUD_CARRIER: return aud_ctrl_get_cfg_carrier(demod, - (pdrx_cfg_aud_carriers_t) config-> + (struct drx_cfg_aud_carriers *) config-> cfg_data); case DRX_CFG_AUD_DEVIATION: return aud_ctrl_get_cfg_dev(demod, - (pdrx_cfg_aud_deviation_t) config-> + (enum drx_cfg_aud_deviation *) config-> cfg_data); case DRX_CFG_AUD_PRESCALE: return aud_ctrl_get_cfg_prescale(demod, - (pdrx_cfg_aud_prescale_t) config-> + (struct drx_cfg_aud_prescale *) config-> cfg_data); case DRX_CFG_AUD_MIXER: return aud_ctrl_get_cfg_mixer(demod, - (pdrx_cfg_aud_mixer_t) config->cfg_data); + (struct drx_cfg_aud_mixer *) config->cfg_data); case DRX_CFG_AUD_AVSYNC: return aud_ctrl_get_cfg_av_sync(demod, - (pdrx_cfg_aud_av_sync_t) config-> + (enum drx_cfg_aud_av_sync *) config-> cfg_data); #endif @@ -15432,14 +15418,14 @@ rw_error: * rely on SCU or AUD ucode to be present. * */ -int drxj_open(pdrx_demod_instance_t demod) +int drxj_open(struct drx_demod_instance *demod) { struct i2c_device_addr *dev_addr = NULL; pdrxj_data_t ext_attr = NULL; - pdrx_common_attr_t common_attr = NULL; + struct drx_common_attr *common_attr = NULL; u32 driver_version = 0; - drxu_code_info_t ucode_info; - drx_cfg_mpeg_output_t cfg_mpeg_output; + struct drxu_code_info ucode_info; + struct drx_cfg_mpeg_output cfg_mpeg_output; /* Check arguments */ if (demod->my_ext_attr == NULL) { @@ -15448,7 +15434,7 @@ int drxj_open(pdrx_demod_instance_t demod) dev_addr = demod->my_i2c_dev_addr; ext_attr = (pdrxj_data_t) demod->my_ext_attr; - common_attr = (pdrx_common_attr_t) demod->my_common_attr; + common_attr = (struct drx_common_attr *) demod->my_common_attr; CHK_ERROR(power_up_device(demod)); common_attr->current_power_mode = DRX_POWER_UP; @@ -15649,11 +15635,11 @@ rw_error: * \return Status_t Return status. * */ -int drxj_close(pdrx_demod_instance_t demod) +int drxj_close(struct drx_demod_instance *demod) { struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; - pdrx_common_attr_t common_attr = demod->my_common_attr; - drx_power_mode_t power_mode = DRX_POWER_UP; + struct drx_common_attr *common_attr = demod->my_common_attr; + enum drx_power_mode power_mode = DRX_POWER_UP; /* power up */ CHK_ERROR(ctrl_power_mode(demod, &power_mode)); @@ -15687,26 +15673,26 @@ rw_error: * \return Status_t Return status. */ int -drxj_ctrl(pdrx_demod_instance_t demod, u32 ctrl, void *ctrl_data) +drxj_ctrl(struct drx_demod_instance *demod, u32 ctrl, void *ctrl_data) { switch (ctrl) { /*======================================================================*/ case DRX_CTRL_SET_CHANNEL: { - return ctrl_set_channel(demod, (pdrx_channel_t) ctrl_data); + return ctrl_set_channel(demod, (struct drx_channel *) ctrl_data); } break; /*======================================================================*/ case DRX_CTRL_GET_CHANNEL: { - return ctrl_get_channel(demod, (pdrx_channel_t) ctrl_data); + return ctrl_get_channel(demod, (struct drx_channel *) ctrl_data); } break; /*======================================================================*/ case DRX_CTRL_SIG_QUALITY: { return ctrl_sig_quality(demod, - (pdrx_sig_quality_t) ctrl_data); + (struct drx_sig_quality *) ctrl_data); } break; /*======================================================================*/ @@ -15718,19 +15704,19 @@ drxj_ctrl(pdrx_demod_instance_t demod, u32 ctrl, void *ctrl_data) /*======================================================================*/ case DRX_CTRL_CONSTEL: { - return ctrl_constel(demod, (pdrx_complex_t) ctrl_data); + return ctrl_constel(demod, (struct drx_complex *) ctrl_data); } break; /*======================================================================*/ case DRX_CTRL_SET_CFG: { - return ctrl_set_cfg(demod, (pdrx_cfg_t) ctrl_data); + return ctrl_set_cfg(demod, (struct drx_cfg *) ctrl_data); } break; /*======================================================================*/ case DRX_CTRL_GET_CFG: { - return ctrl_get_cfg(demod, (pdrx_cfg_t) ctrl_data); + return ctrl_get_cfg(demod, (struct drx_cfg *) ctrl_data); } break; /*======================================================================*/ @@ -15743,7 +15729,7 @@ drxj_ctrl(pdrx_demod_instance_t demod, u32 ctrl, void *ctrl_data) case DRX_CTRL_LOCK_STATUS: { return ctrl_lock_status(demod, - (pdrx_lock_status_t) ctrl_data); + (enum drx_lock_status *)ctrl_data); } break; /*======================================================================*/ @@ -15763,14 +15749,14 @@ drxj_ctrl(pdrx_demod_instance_t demod, u32 ctrl, void *ctrl_data) /*======================================================================*/ case DRX_CTRL_POWER_MODE: { - return ctrl_power_mode(demod, (pdrx_power_mode_t) ctrl_data); + return ctrl_power_mode(demod, (enum drx_power_mode *) ctrl_data); } break; /*======================================================================*/ case DRX_CTRL_VERSION: { return ctrl_version(demod, - (p_drx_version_list_t *)ctrl_data); + (struct drx_version_list **)ctrl_data); } break; /*======================================================================*/ @@ -15782,64 +15768,64 @@ drxj_ctrl(pdrx_demod_instance_t demod, u32 ctrl, void *ctrl_data) /*======================================================================*/ case DRX_CTRL_SET_OOB: { - return ctrl_set_oob(demod, (p_drxoob_t) ctrl_data); + return ctrl_set_oob(demod, (struct drxoob *) ctrl_data); } break; /*======================================================================*/ case DRX_CTRL_GET_OOB: { - return ctrl_get_oob(demod, (pdrxoob_status_t) ctrl_data); + return ctrl_get_oob(demod, (struct drxoob_status *) ctrl_data); } break; /*======================================================================*/ case DRX_CTRL_SET_UIO_CFG: { - return ctrl_set_uio_cfg(demod, (pdrxuio_cfg_t) ctrl_data); + return ctrl_set_uio_cfg(demod, (struct drxuio_cfg *) ctrl_data); } break; /*======================================================================*/ case DRX_CTRL_GET_UIO_CFG: { - return CtrlGetuio_cfg(demod, (pdrxuio_cfg_t) ctrl_data); + return CtrlGetuio_cfg(demod, (struct drxuio_cfg *) ctrl_data); } break; /*======================================================================*/ case DRX_CTRL_UIO_READ: { - return ctrl_uio_read(demod, (pdrxuio_data_t) ctrl_data); + return ctrl_uio_read(demod, (struct drxuio_data *) ctrl_data); } break; /*======================================================================*/ case DRX_CTRL_UIO_WRITE: { - return ctrl_uio_write(demod, (pdrxuio_data_t) ctrl_data); + return ctrl_uio_write(demod, (struct drxuio_data *) ctrl_data); } break; /*======================================================================*/ case DRX_CTRL_AUD_SET_STANDARD: { return aud_ctrl_set_standard(demod, - (pdrx_aud_standard_t) ctrl_data); + (enum drx_aud_standard *) ctrl_data); } break; /*======================================================================*/ case DRX_CTRL_AUD_GET_STANDARD: { return aud_ctrl_get_standard(demod, - (pdrx_aud_standard_t) ctrl_data); + (enum drx_aud_standard *) ctrl_data); } break; /*======================================================================*/ case DRX_CTRL_AUD_GET_STATUS: { return aud_ctrl_get_status(demod, - (pdrx_aud_status_t) ctrl_data); + (struct drx_aud_status *) ctrl_data); } break; /*======================================================================*/ case DRX_CTRL_AUD_BEEP: { - return aud_ctrl_beep(demod, (pdrx_aud_beep_t) ctrl_data); + return aud_ctrl_beep(demod, (struct drx_aud_beep *) ctrl_data); } break; @@ -15847,7 +15833,7 @@ drxj_ctrl(pdrx_demod_instance_t demod, u32 ctrl, void *ctrl_data) case DRX_CTRL_I2C_READWRITE: { return ctrl_i2c_write_read(demod, - (pdrxi2c_data_t) ctrl_data); + (struct drxi2c_data *) ctrl_data); } break; #ifdef DRXJ_SPLIT_UCODE_UPLOAD diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.h b/drivers/media/dvb-frontends/drx39xyj/drxj.h index d882f22..91272f10 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.h +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.h @@ -489,10 +489,10 @@ TYPEDEFS u16 hi_cfg_transmit; /**< HI Configure() parameter 6 */ /* UIO configuartion */ - drxuio_mode_t uio_sma_rx_mode;/**< current mode of SmaRx pin */ - drxuio_mode_t uio_sma_tx_mode;/**< current mode of SmaTx pin */ - drxuio_mode_t uio_gpio_mode; /**< current mode of ASEL pin */ - drxuio_mode_t uio_irqn_mode; /**< current mode of IRQN pin */ + enum drxuio_mode uio_sma_rx_mode;/**< current mode of SmaRx pin */ + enum drxuio_mode uio_sma_tx_mode;/**< current mode of SmaTx pin */ + enum drxuio_mode uio_gpio_mode; /**< current mode of ASEL pin */ + enum drxuio_mode uio_irqn_mode; /**< current mode of IRQN pin */ /* IQM fs frequecy shift and inversion */ u32 iqm_fs_rate_ofs; /**< frequency shifter setting after setchannel */ @@ -531,8 +531,8 @@ TYPEDEFS /* Version information */ char v_text[2][12]; /**< allocated text versions */ - drx_version_t v_version[2]; /**< allocated versions structs */ - drx_version_list_t v_list_elements[2]; + struct drx_version v_version[2]; /**< allocated versions structs */ + struct drx_version_list v_list_elements[2]; /**< allocated version list */ /* smart antenna configuration */ @@ -571,7 +571,7 @@ TYPEDEFS u16 oob_pre_saw; drxj_cfg_oob_lo_power_t oob_lo_pow; - drx_aud_data_t aud_data; + struct drx_aud_data aud_data; /**< audio storage */ } drxj_data_t, *pdrxj_data_t; @@ -723,20 +723,20 @@ STRUCTS Exported FUNCTIONS -------------------------------------------------------------------------*/ - int drxj_open(pdrx_demod_instance_t demod); - int drxj_close(pdrx_demod_instance_t demod); - int drxj_ctrl(pdrx_demod_instance_t demod, + int drxj_open(struct drx_demod_instance *demod); + int drxj_close(struct drx_demod_instance *demod); + int drxj_ctrl(struct drx_demod_instance *demod, u32 ctrl, void *ctrl_data); /*------------------------------------------------------------------------- Exported GLOBAL VARIABLES -------------------------------------------------------------------------*/ - extern drx_access_func_t drx_dap_drxj_funct_g; - extern drx_demod_func_t drxj_functions_g; + extern struct drx_access_func drx_dap_drxj_funct_g; + extern struct drx_demod_func drxj_functions_g; extern drxj_data_t drxj_data_g; extern struct i2c_device_addr drxj_default_addr_g; - extern drx_common_attr_t drxj_default_comm_attr_g; - extern drx_demod_instance_t drxj_default_demod_g; + extern struct drx_common_attr drxj_default_comm_attr_g; + extern struct drx_demod_instance drxj_default_demod_g; /*------------------------------------------------------------------------- THE END -- cgit v1.1 From b3ce3a8311615df43ec3a1969086f9fffcc8dceb Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Thu, 16 Jan 2014 15:33:14 -0300 Subject: [media] drx-j: Get rid of typedefs on drxh.h This were fixed with the help of this small perl script: #!/usr/bin/perl my $dir = shift or die "need a dir"; my $type = shift or die "need type"; my $var = shift or die "need var"; sub handle_file { my $file = shift; my $out; open IN, $file or die "can't open $file"; $out .= $_ while (); close IN; $out =~ s/\btypedef\s+($type)\s+\{([\d\D]+?)\s*\}\s+\b($var)[^\;]+\;/$type $var \{\2\};/; $out =~ s,\b($var)_t\s+,$type \1 ,g; $out =~ s,\bp_*($var)_t\s+,$type \1 *,g; $out =~ s,\b($var)_t\b,$type \1,g; $out =~ s,\bp_*($var)_t\b,$type \1 *,g; open OUT, ">$file" or die "can't open $file"; print OUT $out; close OUT; } sub parse_dir { my $file = $File::Find::name; return if (!($file =~ /.[ch]$/)); handle_file $file; } find({wanted => \&parse_dir, no_chdir => 1}, $dir); Some manual work were needed. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drx39xxj.c | 8 +- drivers/media/dvb-frontends/drx39xyj/drxj.c | 542 ++++++++++++------------ drivers/media/dvb-frontends/drx39xyj/drxj.h | 245 +++++------ 3 files changed, 379 insertions(+), 416 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c index 837bb64..0d2ec99 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c @@ -327,7 +327,7 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) struct i2c_device_addr *demod_addr = NULL; struct drx_common_attr *demod_comm_attr = NULL; - drxj_data_t *demod_ext_attr = NULL; + struct drxj_data *demod_ext_attr = NULL; struct drx_demod_instance *demod = NULL; struct drxuio_cfg uio_cfg; struct drxuio_data uio_data; @@ -350,7 +350,7 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) if (demod_comm_attr == NULL) goto error; - demod_ext_attr = kmalloc(sizeof(drxj_data_t), GFP_KERNEL); + demod_ext_attr = kmalloc(sizeof(struct drxj_data), GFP_KERNEL); if (demod_ext_attr == NULL) goto error; @@ -375,8 +375,8 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) demod->my_common_attr->intermediate_freq = 5000; demod->my_ext_attr = demod_ext_attr; - memcpy(demod->my_ext_attr, &drxj_data_g, sizeof(drxj_data_t)); - ((drxj_data_t *)demod->my_ext_attr)->uio_sma_tx_mode = + memcpy(demod->my_ext_attr, &drxj_data_g, sizeof(struct drxj_data)); + ((struct drxj_data *)demod->my_ext_attr)->uio_sma_tx_mode = DRX_UIO_MODE_READWRITE; demod->my_tuner = NULL; diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index fc727d9..14a87ca 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -688,7 +688,7 @@ struct drx_demod_func drxj_functions_g = { drxj_ctrl }; -drxj_data_t drxj_data_g = { +struct drxj_data drxj_data_g = { false, /* has_lna : true if LNA (aka PGA) present */ false, /* has_oob : true if OOB supported */ false, /* has_ntsc: true if NTSC supported */ @@ -1165,10 +1165,10 @@ static int aud_ctrl_set_standard(struct drx_demod_instance *demod, enum drx_aud_standard *standard); static int -ctrl_set_cfg_pre_saw(struct drx_demod_instance *demod, p_drxj_cfg_pre_saw_t pre_saw); +ctrl_set_cfg_pre_saw(struct drx_demod_instance *demod, struct drxj_cfg_pre_saw *pre_saw); static int -ctrl_set_cfg_afe_gain(struct drx_demod_instance *demod, p_drxj_cfg_afe_gain_t afe_gain); +ctrl_set_cfg_afe_gain(struct drx_demod_instance *demod, struct drxj_cfg_afe_gain *afe_gain); #ifdef DRXJ_SPLIT_UCODE_UPLOAD static int @@ -2221,11 +2221,11 @@ int drxj_dap_atomic_read_reg32(struct i2c_device_addr *dev_addr, */ static int hi_cfg_command(const struct drx_demod_instance *demod) { - pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); + struct drxj_data *ext_attr = (struct drxj_data *) (NULL); drxj_hi_cmd_t hi_cmd; u16 result = 0; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; hi_cmd.cmd = SIO_HI_RA_RAM_CMD_CONFIG; hi_cmd.param1 = SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY; @@ -2336,11 +2336,11 @@ rw_error: */ static int init_hi(const struct drx_demod_instance *demod) { - pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); + struct drxj_data *ext_attr = (struct drxj_data *) (NULL); struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL); struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; common_attr = (struct drx_common_attr *) demod->my_common_attr; dev_addr = demod->my_i2c_dev_addr; @@ -2414,14 +2414,14 @@ rw_error: static int get_device_capabilities(struct drx_demod_instance *demod) { struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL); - pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; + struct drxj_data *ext_attr = (struct drxj_data *) NULL; struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); u16 sio_pdr_ohw_cfg = 0; u32 sio_top_jtagid_lo = 0; u16 bid = 0; common_attr = (struct drx_common_attr *) demod->my_common_attr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; dev_addr = demod->my_i2c_dev_addr; WR16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); @@ -2639,7 +2639,7 @@ static int ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_output *cfg_data) { struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); - pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); + struct drxj_data *ext_attr = (struct drxj_data *) (NULL); struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL); u16 fec_oc_reg_mode = 0; u16 fec_oc_reg_ipr_mode = 0; @@ -2660,7 +2660,7 @@ ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o } dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; common_attr = (struct drx_common_attr *) demod->my_common_attr; if (cfg_data->enable_mpeg_output == true) { @@ -3097,14 +3097,14 @@ rw_error: */ static int set_mpegtei_handling(struct drx_demod_instance *demod) { - pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); + struct drxj_data *ext_attr = (struct drxj_data *) (NULL); struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); u16 fec_oc_dpr_mode = 0; u16 fec_oc_snc_mode = 0; u16 fec_oc_ems_mode = 0; dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; RR16(dev_addr, FEC_OC_DPR_MODE__A, &fec_oc_dpr_mode); RR16(dev_addr, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode); @@ -3145,12 +3145,12 @@ rw_error: */ static int bit_reverse_mpeg_output(struct drx_demod_instance *demod) { - pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); + struct drxj_data *ext_attr = (struct drxj_data *) (NULL); struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); u16 fec_oc_ipr_mode = 0; dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; RR16(dev_addr, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode); @@ -3181,11 +3181,11 @@ rw_error: */ static int set_mpeg_output_clock_rate(struct drx_demod_instance *demod) { - pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); + struct drxj_data *ext_attr = (struct drxj_data *) (NULL); struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; if (ext_attr->mpeg_output_clock_rate != DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO) { WR16(dev_addr, FEC_OC_DTO_PERIOD__A, @@ -3209,13 +3209,13 @@ rw_error: */ static int set_mpeg_start_width(struct drx_demod_instance *demod) { - pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); + struct drxj_data *ext_attr = (struct drxj_data *) (NULL); struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); u16 fec_oc_comm_mb = 0; struct drx_common_attr *common_attr = (struct drx_common_attr *) NULL; dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; common_attr = demod->my_common_attr; if ((common_attr->mpeg_cfg.static_clk == true) @@ -3247,15 +3247,15 @@ rw_error: */ static int ctrl_set_cfg_mpeg_output_misc(struct drx_demod_instance *demod, - p_drxj_cfg_mpeg_output_misc_t cfg_data) + struct drxj_cfg_mpeg_output_misc *cfg_data) { - pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); + struct drxj_data *ext_attr = (struct drxj_data *) (NULL); if (cfg_data == NULL) { return (DRX_STS_INVALID_ARG); } - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; /* Set disable TEI bit handling flag. @@ -3297,16 +3297,16 @@ rw_error: */ static int ctrl_get_cfg_mpeg_output_misc(struct drx_demod_instance *demod, - p_drxj_cfg_mpeg_output_misc_t cfg_data) + struct drxj_cfg_mpeg_output_misc *cfg_data) { - pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); + struct drxj_data *ext_attr = (struct drxj_data *) (NULL); u16 data = 0; if (cfg_data == NULL) { return (DRX_STS_INVALID_ARG); } - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; cfg_data->disable_tei_handling = ext_attr->disable_te_ihandling; cfg_data->bit_reverse_mpeg_outout = ext_attr->bit_reverse_mpeg_outout; cfg_data->mpeg_start_width = ext_attr->mpeg_start_width; @@ -3315,7 +3315,7 @@ ctrl_get_cfg_mpeg_output_misc(struct drx_demod_instance *demod, } else { RR16(demod->my_i2c_dev_addr, FEC_OC_DTO_PERIOD__A, &data); cfg_data->mpeg_output_clock_rate = - (drxj_mpeg_output_clock_rate_t) (data + 1); + (enum drxj_mpeg_output_clock_rate) (data + 1); } return (DRX_STS_OK); @@ -3338,7 +3338,7 @@ rw_error: * */ static int -ctrl_get_cfg_hw_cfg(struct drx_demod_instance *demod, p_drxj_cfg_hw_cfg_t cfg_data) +ctrl_get_cfg_hw_cfg(struct drx_demod_instance *demod, struct drxj_cfg_hw_cfg *cfg_data) { u16 data = 0; @@ -3349,8 +3349,8 @@ ctrl_get_cfg_hw_cfg(struct drx_demod_instance *demod, p_drxj_cfg_hw_cfg_t cfg_da RR16(demod->my_i2c_dev_addr, SIO_PDR_OHW_CFG__A, &data); WR16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000); - cfg_data->i2c_speed = (drxji2c_speed_t) ((data >> 6) & 0x1); - cfg_data->xtal_freq = (drxj_xtal_freq_t) (data & 0x3); + cfg_data->i2c_speed = (enum drxji2c_speed) ((data >> 6) & 0x1); + cfg_data->xtal_freq = (enum drxj_xtal_freq) (data & 0x3); return (DRX_STS_OK); rw_error: @@ -3373,12 +3373,12 @@ rw_error: */ static int ctrl_set_uio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg *uio_cfg) { - pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); + struct drxj_data *ext_attr = (struct drxj_data *) (NULL); if ((uio_cfg == NULL) || (demod == NULL)) { return DRX_STS_INVALID_ARG; } - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; /* Write magic word to enable pdr reg write */ WR16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); @@ -3487,7 +3487,7 @@ rw_error: static int CtrlGetuio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg *uio_cfg) { - pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; + struct drxj_data *ext_attr = (struct drxj_data *) NULL; enum drxuio_mode *uio_mode[4] = { NULL }; bool *uio_available[4] = { NULL }; @@ -3530,7 +3530,7 @@ static int CtrlGetuio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg *u static int ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data) { - pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); + struct drxj_data *ext_attr = (struct drxj_data *) (NULL); u16 pin_cfg_value = 0; u16 value = 0; @@ -3538,7 +3538,7 @@ ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data) return DRX_STS_INVALID_ARG; } - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; /* Write magic word to enable pdr reg write */ WR16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); @@ -3675,7 +3675,7 @@ rw_error: */ static int ctrl_uio_read(struct drx_demod_instance *demod, struct drxuio_data *uio_data) { - pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); + struct drxj_data *ext_attr = (struct drxj_data *) (NULL); u16 pin_cfg_value = 0; u16 value = 0; @@ -3683,7 +3683,7 @@ static int ctrl_uio_read(struct drx_demod_instance *demod, struct drxuio_data *u return DRX_STS_INVALID_ARG; } - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; /* Write magic word to enable pdr reg write */ WR16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); @@ -3858,12 +3858,12 @@ ctrl_i2c_bridge(struct drx_demod_instance *demod, bool *bridge_closed) static int smart_ant_init(struct drx_demod_instance *demod) { u16 data = 0; - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; struct i2c_device_addr *dev_addr = NULL; struct drxuio_cfg uio_cfg = { DRX_UIO1, DRX_UIO_MODE_FIRMWARE_SMA }; dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; /* Write magic word to enable pdr reg write */ WR16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); @@ -3894,21 +3894,21 @@ rw_error: /** * \fn int ctrl_set_cfg_smart_ant() * \brief Set Smart Antenna. -* \param pointer to drxj_cfg_smart_ant_t. +* \param pointer to struct drxj_cfg_smart_ant. * \return int. * */ static int -ctrl_set_cfg_smart_ant(struct drx_demod_instance *demod, p_drxj_cfg_smart_ant_t smart_ant) +ctrl_set_cfg_smart_ant(struct drx_demod_instance *demod, struct drxj_cfg_smart_ant *smart_ant) { - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; struct i2c_device_addr *dev_addr = NULL; u16 data = 0; u32 start_time = 0; static bool bit_inverted; dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; /* check arguments */ if (smart_ant == NULL) { @@ -3986,7 +3986,7 @@ rw_error: return (DRX_STS_ERROR); } -static int scu_command(struct i2c_device_addr *dev_addr, p_drxjscu_cmd_t cmd) +static int scu_command(struct i2c_device_addr *dev_addr, struct drxjscu_cmd *cmd) { u16 cur_cmd = 0; u32 start_time = 0; @@ -4095,7 +4095,7 @@ static int drxj_dap_scu_atomic_read_write_block(struct i2c_device_addr *dev_addr, u32 addr, u16 datasize, /* max 30 bytes because the limit of SCU parameter */ u8 *data, bool read_flag) { - drxjscu_cmd_t scu_cmd; + struct drxjscu_cmd scu_cmd; u16 set_param_parameters[15]; u16 cmd_result[15]; @@ -4323,7 +4323,7 @@ rw_error: /* -------------------------------------------------------------------------- */ static int -ctrl_set_cfg_atv_output(struct drx_demod_instance *demod, p_drxj_cfg_atv_output_t output_cfg); +ctrl_set_cfg_atv_output(struct drx_demod_instance *demod, struct drxj_cfg_atv_output *output_cfg); /** * \brief set configuration of pin-safe mode @@ -4334,14 +4334,14 @@ ctrl_set_cfg_atv_output(struct drx_demod_instance *demod, p_drxj_cfg_atv_output_ static int ctrl_set_cfg_pdr_safe_mode(struct drx_demod_instance *demod, bool *enable) { - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; struct i2c_device_addr *dev_addr = NULL; if (enable == NULL) return (DRX_STS_INVALID_ARG); dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; /* Write magic word to enable pdr reg write */ WR16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); @@ -4457,13 +4457,13 @@ rw_error: static int ctrl_get_cfg_pdr_safe_mode(struct drx_demod_instance *demod, bool *enabled) { - pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; + struct drxj_data *ext_attr = (struct drxj_data *) NULL; if (enabled == NULL) { return (DRX_STS_INVALID_ARG); } - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; *enabled = ext_attr->pdr_safe_mode; return (DRX_STS_OK); @@ -4526,9 +4526,9 @@ static int init_agc(struct drx_demod_instance *demod) { struct i2c_device_addr *dev_addr = NULL; struct drx_common_attr *common_attr = NULL; - pdrxj_data_t ext_attr = NULL; - p_drxj_cfg_agc_t p_agc_rf_settings = NULL; - p_drxj_cfg_agc_t p_agc_if_settings = NULL; + struct drxj_data *ext_attr = NULL; + struct drxj_cfg_agc *p_agc_rf_settings = NULL; + struct drxj_cfg_agc *p_agc_if_settings = NULL; u16 ingain_tgt_max = 0; u16 clp_dir_to = 0; u16 sns_sum_max = 0; @@ -4546,7 +4546,7 @@ static int init_agc(struct drx_demod_instance *demod) u16 agc_if = 0; dev_addr = demod->my_i2c_dev_addr; common_attr = (struct drx_common_attr *) demod->my_common_attr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; switch (ext_attr->standard) { case DRX_STANDARD_8VSB: @@ -4734,7 +4734,7 @@ set_frequency(struct drx_demod_instance *demod, struct drx_channel *channel, s32 tuner_freq_offset) { struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; - pdrxj_data_t ext_attr = demod->my_ext_attr; + struct drxj_data *ext_attr = demod->my_ext_attr; s32 sampling_frequency = 0; s32 frequency_shift = 0; s32 if_freq_actual = 0; @@ -4893,10 +4893,10 @@ static int get_acc_pkt_err(struct drx_demod_instance *demod, u16 *packet_err) static u16 pkt_err; static u16 last_pkt_err; u16 data = 0; - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; struct i2c_device_addr *dev_addr = NULL; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; dev_addr = demod->my_i2c_dev_addr; RR16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, &data); @@ -4932,10 +4932,10 @@ rw_error: static int ctrl_set_cfg_reset_pkt_err(struct drx_demod_instance *demod) { #ifdef DRXJ_SIGNAL_ACCUM_ERR - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; u16 packet_error = 0; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; ext_attr->reset_pkt_err_acc = true; /* call to reset counter */ CHK_ERROR(get_acc_pkt_err(demod, &packet_error)); @@ -4957,7 +4957,7 @@ static int get_str_freq_offset(struct drx_demod_instance *demod, s32 *str_freq) u32 symbol_nom_frequency_ratio = 0; struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; - pdrxj_data_t ext_attr = demod->my_ext_attr; + struct drxj_data *ext_attr = demod->my_ext_attr; ARR32(dev_addr, IQM_RC_RATE_LO__A, &symbol_frequency_ratio); symbol_nom_frequency_ratio = ext_attr->iqm_rc_rate_ofs; @@ -4993,12 +4993,12 @@ static int get_ctl_freq_offset(struct drx_demod_instance *demod, s32 *ctl_freq) s32 sign = 1; u32 data64hi = 0; u32 data64lo = 0; - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; struct drx_common_attr *common_attr = NULL; struct i2c_device_addr *dev_addr = NULL; dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; common_attr = (struct drx_common_attr *) demod->my_common_attr; sampling_frequency = common_attr->sys_clock_freq / 3; @@ -5041,18 +5041,18 @@ rw_error: * \return int. */ static int -set_agc_rf(struct drx_demod_instance *demod, p_drxj_cfg_agc_t agc_settings, bool atomic) +set_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, bool atomic) { struct i2c_device_addr *dev_addr = NULL; - pdrxj_data_t ext_attr = NULL; - p_drxj_cfg_agc_t p_agc_settings = NULL; + struct drxj_data *ext_attr = NULL; + struct drxj_cfg_agc *p_agc_settings = NULL; struct drx_common_attr *common_attr = NULL; drx_write_reg16func_t scu_wr16 = NULL; drx_read_reg16func_t scu_rr16 = NULL; common_attr = (struct drx_common_attr *) demod->my_common_attr; dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; if (atomic) { scu_rr16 = drxj_dap_scu_atomic_read_reg16; @@ -5219,14 +5219,14 @@ rw_error: * \return int. */ static int -get_agc_rf(struct drx_demod_instance *demod, p_drxj_cfg_agc_t agc_settings) +get_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings) { struct i2c_device_addr *dev_addr = NULL; - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; enum drx_standard standard = DRX_STANDARD_UNKNOWN; dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; /* Return stored AGC settings */ standard = agc_settings->standard; @@ -5280,18 +5280,18 @@ rw_error: * \return int. */ static int -set_agc_if(struct drx_demod_instance *demod, p_drxj_cfg_agc_t agc_settings, bool atomic) +set_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, bool atomic) { struct i2c_device_addr *dev_addr = NULL; - pdrxj_data_t ext_attr = NULL; - p_drxj_cfg_agc_t p_agc_settings = NULL; + struct drxj_data *ext_attr = NULL; + struct drxj_cfg_agc *p_agc_settings = NULL; struct drx_common_attr *common_attr = NULL; drx_write_reg16func_t scu_wr16 = NULL; drx_read_reg16func_t scu_rr16 = NULL; common_attr = (struct drx_common_attr *) demod->my_common_attr; dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; if (atomic) { scu_rr16 = drxj_dap_scu_atomic_read_reg16; @@ -5471,14 +5471,14 @@ rw_error: * \return int. */ static int -get_agc_if(struct drx_demod_instance *demod, p_drxj_cfg_agc_t agc_settings) +get_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings) { struct i2c_device_addr *dev_addr = NULL; - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; enum drx_standard standard = DRX_STANDARD_UNKNOWN; dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; /* Return stored ATV AGC settings */ standard = agc_settings->standard; @@ -5583,7 +5583,7 @@ rw_error: static int power_down_vsb(struct drx_demod_instance *demod, bool primary) { struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; - drxjscu_cmd_t cmd_scu = { /* command */ 0, + struct drxjscu_cmd cmd_scu = { /* command */ 0, /* parameter_len */ 0, /* result_len */ 0, /* *parameter */ NULL, @@ -5848,8 +5848,8 @@ static int set_vsb(struct drx_demod_instance *demod) u16 cmd_result = 0; u16 cmd_param = 0; struct drx_common_attr *common_attr = NULL; - drxjscu_cmd_t cmd_scu; - pdrxj_data_t ext_attr = NULL; + struct drxjscu_cmd cmd_scu; + struct drxj_data *ext_attr = NULL; const u8 vsb_taps_re[] = { DRXJ_16TO8(-2), /* re0 */ DRXJ_16TO8(4), /* re1 */ @@ -5883,7 +5883,7 @@ static int set_vsb(struct drx_demod_instance *demod) dev_addr = demod->my_i2c_dev_addr; common_attr = (struct drx_common_attr *) demod->my_common_attr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; /* stop all comm_exec */ WR16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP); @@ -5987,9 +5987,9 @@ static int set_vsb(struct drx_demod_instance *demod) CHK_ERROR(set_agc_if(demod, &(ext_attr->vsb_if_agc_cfg), false)); CHK_ERROR(set_agc_rf(demod, &(ext_attr->vsb_rf_agc_cfg), false)); { - /* TODO fix this, store a drxj_cfg_afe_gain_t structure in drxj_data_t instead + /* TODO fix this, store a struct drxj_cfg_afe_gain structure in struct drxj_data instead of only the gain */ - drxj_cfg_afe_gain_t vsb_pga_cfg = { DRX_STANDARD_8VSB, 0 }; + struct drxj_cfg_afe_gain vsb_pga_cfg = { DRX_STANDARD_8VSB, 0 }; vsb_pga_cfg.gain = ext_attr->vsb_pga_cfg; CHK_ERROR(ctrl_set_cfg_afe_gain(demod, &vsb_pga_cfg)); @@ -6268,7 +6268,7 @@ rw_error: */ static int power_down_qam(struct drx_demod_instance *demod, bool primary) { - drxjscu_cmd_t cmd_scu = { /* command */ 0, + struct drxjscu_cmd cmd_scu = { /* command */ 0, /* parameter_len */ 0, /* result_len */ 0, /* *parameter */ NULL, @@ -6337,7 +6337,7 @@ set_qam_measurement(struct drx_demod_instance *demod, enum drx_modulation constellation, u32 symbol_rate) { struct i2c_device_addr *dev_addr = NULL; /* device address for I2C writes */ - pdrxj_data_t ext_attr = NULL; /* Global data container for DRXJ specif data */ + struct drxj_data *ext_attr = NULL; /* Global data container for DRXJ specif data */ u32 fec_bits_desired = 0; /* BER accounting period */ u16 fec_rs_plen = 0; /* defines RS BER measurement period */ u16 fec_rs_prescale = 0; /* ReedSolomon Measurement Prescale */ @@ -6350,7 +6350,7 @@ set_qam_measurement(struct drx_demod_instance *demod, u16 qam_vd_prescale = 0; /* Viterbi Measurement Prescale */ dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; fec_bits_desired = ext_attr->fec_bits_desired; fec_rs_prescale = ext_attr->fec_rs_prescale; @@ -6904,7 +6904,7 @@ set_qam(struct drx_demod_instance *demod, struct drx_channel *channel, s32 tuner_freq_offset, u32 op) { struct i2c_device_addr *dev_addr = NULL; - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; struct drx_common_attr *common_attr = NULL; u16 cmd_result = 0; u32 adc_frequency = 0; @@ -6913,7 +6913,7 @@ set_qam(struct drx_demod_instance *demod, u16 iqm_rc_stretch = 0; u16 set_env_parameters = 0; u16 set_param_parameters[2] = { 0 }; - drxjscu_cmd_t cmd_scu = { /* command */ 0, + struct drxjscu_cmd cmd_scu = { /* command */ 0, /* parameter_len */ 0, /* result_len */ 0, /* parameter */ NULL, @@ -7041,7 +7041,7 @@ set_qam(struct drx_demod_instance *demod, }; dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; common_attr = (struct drx_common_attr *) demod->my_common_attr; if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) { @@ -7247,9 +7247,9 @@ set_qam(struct drx_demod_instance *demod, CHK_ERROR(set_agc_if(demod, &(ext_attr->qam_if_agc_cfg), false)); CHK_ERROR(set_agc_rf(demod, &(ext_attr->qam_rf_agc_cfg), false)); { - /* TODO fix this, store a drxj_cfg_afe_gain_t structure in drxj_data_t instead + /* TODO fix this, store a struct drxj_cfg_afe_gain structure in struct drxj_data instead of only the gain */ - drxj_cfg_afe_gain_t qam_pga_cfg = { DRX_STANDARD_ITU_B, 0 }; + struct drxj_cfg_afe_gain qam_pga_cfg = { DRX_STANDARD_ITU_B, 0 }; qam_pga_cfg.gain = ext_attr->qam_pga_cfg; CHK_ERROR(ctrl_set_cfg_afe_gain(demod, &qam_pga_cfg)); @@ -7375,10 +7375,10 @@ static int qam_flip_spec(struct drx_demod_instance *demod, struct drx_channel *c int i = 0; int ofsofs = 0; struct i2c_device_addr *dev_addr = NULL; - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; /* Silence the controlling of lc, equ, and the acquisition state machine */ RR16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, &qam_ctl_ena); @@ -7470,11 +7470,11 @@ qam64auto(struct drx_demod_instance *demod, u32 state = NO_LOCK; u32 start_time = 0; u32 d_locked_time = 0; - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; u32 timeout_ofs = 0; /* external attributes for storing aquired channel constellation */ - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; *lock_status = DRX_NOT_LOCKED; start_time = drxbsp_hst_clock(); state = NO_LOCK; @@ -7583,11 +7583,11 @@ qam256auto(struct drx_demod_instance *demod, u32 state = NO_LOCK; u32 start_time = 0; u32 d_locked_time = 0; - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; u32 timeout_ofs = DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME; /* external attributes for storing aquired channel constellation */ - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; *lock_status = DRX_NOT_LOCKED; start_time = drxbsp_hst_clock(); state = NO_LOCK; @@ -7648,11 +7648,11 @@ set_qamChannel(struct drx_demod_instance *demod, struct drx_channel *channel, s32 tuner_freq_offset) { enum drx_lock_status lock_status = DRX_NOT_LOCKED; - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; bool auto_flag = false; /* external attributes for storing aquired channel constellation */ - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; /* set QAM channel constellation */ switch (channel->constellation) { @@ -7794,7 +7794,7 @@ rw_error: * */ static int -GetQAMRSErr_count(struct i2c_device_addr *dev_addr, p_drxjrs_errors_t rs_errors) +GetQAMRSErr_count(struct i2c_device_addr *dev_addr, struct drxjrs_errors *rs_errors) { u16 nr_bit_errors = 0, nr_symbol_errors = 0, @@ -7851,9 +7851,9 @@ static int ctrl_get_qam_sig_quality(struct drx_demod_instance *demod, struct drx_sig_quality *sig_quality) { struct i2c_device_addr *dev_addr = NULL; - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; enum drx_modulation constellation = DRX_CONSTELLATION_UNKNOWN; - DRXJrs_errors_t measuredrs_errors = { 0, 0, 0, 0, 0 }; + struct drxjrs_errors measuredrs_errors = { 0, 0, 0, 0, 0 }; u32 pre_bit_err_rs = 0; /* pre RedSolomon Bit Error Rate */ u32 post_bit_err_rs = 0; /* post RedSolomon Bit Error Rate */ @@ -7881,7 +7881,7 @@ ctrl_get_qam_sig_quality(struct drx_demod_instance *demod, struct drx_sig_qualit /* get device basic information */ dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; constellation = ext_attr->constellation; /* read the physical registers */ @@ -8223,10 +8223,10 @@ static int atv_update_config(struct drx_demod_instance *demod, bool force_update) { struct i2c_device_addr *dev_addr = NULL; - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; /* equalizer coefficients */ if (force_update || @@ -8328,16 +8328,16 @@ rw_error: * */ static int -ctrl_set_cfg_atv_output(struct drx_demod_instance *demod, p_drxj_cfg_atv_output_t output_cfg) +ctrl_set_cfg_atv_output(struct drx_demod_instance *demod, struct drxj_cfg_atv_output *output_cfg) { - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; /* Check arguments */ if (output_cfg == NULL) { return (DRX_STS_INVALID_ARG); } - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; if (output_cfg->enable_sif_output) { switch (output_cfg->sif_attenuation) { case DRXJ_SIF_ATTENUATION_0DB: /* fallthrough */ @@ -8385,12 +8385,12 @@ rw_error: * */ static int -ctrl_set_cfg_atv_equ_coef(struct drx_demod_instance *demod, p_drxj_cfg_atv_equ_coef_t coef) +ctrl_set_cfg_atv_equ_coef(struct drx_demod_instance *demod, struct drxj_cfg_atv_equ_coef *coef) { - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; int index; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; /* current standard needs to be an ATV standard */ if (!DRXJ_ISATVSTD(ext_attr->standard)) { @@ -8439,12 +8439,12 @@ rw_error: * */ static int -ctrl_get_cfg_atv_equ_coef(struct drx_demod_instance *demod, p_drxj_cfg_atv_equ_coef_t coef) +ctrl_get_cfg_atv_equ_coef(struct drx_demod_instance *demod, struct drxj_cfg_atv_equ_coef *coef) { - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; int index = 0; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; /* current standard needs to be an ATV standard */ if (!DRXJ_ISATVSTD(ext_attr->standard)) { @@ -8477,9 +8477,9 @@ rw_error: * */ static int -ctrl_set_cfg_atv_misc(struct drx_demod_instance *demod, p_drxj_cfg_atv_misc_t settings) +ctrl_set_cfg_atv_misc(struct drx_demod_instance *demod, struct drxj_cfg_atv_misc *settings) { - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; /* Check arguments */ if ((settings == NULL) || @@ -8489,7 +8489,7 @@ ctrl_set_cfg_atv_misc(struct drx_demod_instance *demod, p_drxj_cfg_atv_misc_t se return (DRX_STS_INVALID_ARG); } /* if */ - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; if (settings->peak_filter != ext_attr->atv_top_vid_peak) { ext_attr->atv_top_vid_peak = settings->peak_filter; @@ -8522,16 +8522,16 @@ rw_error: * regitsers. */ static int -ctrl_get_cfg_atv_misc(struct drx_demod_instance *demod, p_drxj_cfg_atv_misc_t settings) +ctrl_get_cfg_atv_misc(struct drx_demod_instance *demod, struct drxj_cfg_atv_misc *settings) { - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; /* Check arguments */ if (settings == NULL) { return DRX_STS_INVALID_ARG; } - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; settings->peak_filter = ext_attr->atv_top_vid_peak; settings->noise_filter = ext_attr->atv_top_noise_th; @@ -8551,7 +8551,7 @@ ctrl_get_cfg_atv_misc(struct drx_demod_instance *demod, p_drxj_cfg_atv_misc_t se * */ static int -ctrl_get_cfg_atv_output(struct drx_demod_instance *demod, p_drxj_cfg_atv_output_t output_cfg) +ctrl_get_cfg_atv_output(struct drx_demod_instance *demod, struct drxj_cfg_atv_output *output_cfg) { u16 data = 0; @@ -8572,7 +8572,7 @@ ctrl_get_cfg_atv_output(struct drx_demod_instance *demod, p_drxj_cfg_atv_output_ } else { output_cfg->enable_sif_output = true; RR16(demod->my_i2c_dev_addr, ATV_TOP_AF_SIF_ATT__A, &data); - output_cfg->sif_attenuation = (drxjsif_attenuation_t) data; + output_cfg->sif_attenuation = (enum drxjsif_attenuation) data; } return (DRX_STS_OK); @@ -8591,7 +8591,7 @@ rw_error: */ static int ctrl_get_cfg_atv_agc_status(struct drx_demod_instance *demod, - p_drxj_cfg_atv_agc_status_t agc_status) + struct drxj_cfg_atv_agc_status *agc_status) { struct i2c_device_addr *dev_addr = NULL; u16 data = 0; @@ -8728,7 +8728,7 @@ static int power_down_atv(struct drx_demod_instance *demod, enum drx_standard standard, bool primary) { struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; - drxjscu_cmd_t cmd_scu = { /* command */ 0, + struct drxjscu_cmd cmd_scu = { /* command */ 0, /* parameter_len */ 0, /* result_len */ 0, /* *parameter */ NULL, @@ -9043,7 +9043,7 @@ trouble ? }; struct i2c_device_addr *dev_addr = NULL; - drxjscu_cmd_t cmd_scu = { /* command */ 0, + struct drxjscu_cmd cmd_scu = { /* command */ 0, /* parameter_len */ 0, /* result_len */ 0, /* *parameter */ NULL, @@ -9055,9 +9055,9 @@ trouble ? struct drxu_code_info ucode_info; struct drx_common_attr *common_attr = NULL; #endif /* DRXJ_SPLIT_UCODE_UPLOAD */ - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; dev_addr = demod->my_i2c_dev_addr; #ifdef DRXJ_SPLIT_UCODE_UPLOAD @@ -9402,18 +9402,18 @@ set_atv_channel(struct drx_demod_instance *demod, s32 tuner_freq_offset, struct drx_channel *channel, enum drx_standard standard) { - drxjscu_cmd_t cmd_scu = { /* command */ 0, + struct drxjscu_cmd cmd_scu = { /* command */ 0, /* parameter_len */ 0, /* result_len */ 0, /* parameter */ NULL, /* result */ NULL }; u16 cmd_result = 0; - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; struct i2c_device_addr *dev_addr = NULL; dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; /* Program frequency shifter @@ -9472,7 +9472,7 @@ get_atv_channel(struct drx_demod_instance *demod, struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; /* Bandwidth */ - channel->bandwidth = ((pdrxj_data_t) demod->my_ext_attr)->curr_bandwidth; + channel->bandwidth = ((struct drxj_data *) demod->my_ext_attr)->curr_bandwidth; switch (standard) { case DRX_STANDARD_NTSC: @@ -9551,7 +9551,7 @@ static int get_atv_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength) { struct i2c_device_addr *dev_addr = NULL; - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; /* All weights must add up to 100 (%) TODO: change weights when IF ctrl is available */ @@ -9574,7 +9574,7 @@ get_atv_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength) u32 if_strength = 0; /* 0.. 100 */ dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; *sig_strength = 0; @@ -9747,10 +9747,10 @@ rw_error: static int power_down_aud(struct drx_demod_instance *demod) { struct i2c_device_addr *dev_addr = NULL; - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; WR16(dev_addr, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP); @@ -9772,7 +9772,7 @@ rw_error: static int aud_get_modus(struct drx_demod_instance *demod, u16 *modus) { struct i2c_device_addr *dev_addr = NULL; - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; u16 r_modus = 0; u16 r_modusHi = 0; @@ -9783,7 +9783,7 @@ static int aud_get_modus(struct drx_demod_instance *demod, u16 *modus) } dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; /* power up */ if (ext_attr->aud_data.audio_is_active == false) { @@ -9817,7 +9817,7 @@ static int aud_ctrl_get_cfg_rds(struct drx_demod_instance *demod, struct drx_cfg_aud_rds *status) { struct i2c_device_addr *addr = NULL; - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; u16 r_rds_array_cnt_init = 0; u16 r_rds_array_cnt_check = 0; @@ -9825,7 +9825,7 @@ aud_ctrl_get_cfg_rds(struct drx_demod_instance *demod, struct drx_cfg_aud_rds *s u16 rds_data_cnt = 0; addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; if (status == NULL) { return DRX_STS_INVALID_ARG; @@ -9886,7 +9886,7 @@ rw_error: static int aud_ctrl_get_carrier_detect_status(struct drx_demod_instance *demod, struct drx_aud_status *status) { - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; struct i2c_device_addr *dev_addr = NULL; u16 r_data = 0; @@ -9896,7 +9896,7 @@ aud_ctrl_get_carrier_detect_status(struct drx_demod_instance *demod, struct drx_ } dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; /* power up */ if (ext_attr->aud_data.audio_is_active == false) { @@ -9964,7 +9964,7 @@ rw_error: static int aud_ctrl_get_status(struct drx_demod_instance *demod, struct drx_aud_status *status) { - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; struct i2c_device_addr *dev_addr = NULL; struct drx_cfg_aud_rds rds = { false, {0} }; u16 r_data = 0; @@ -9974,7 +9974,7 @@ aud_ctrl_get_status(struct drx_demod_instance *demod, struct drx_aud_status *sta } dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; /* carrier detection */ CHK_ERROR(aud_ctrl_get_carrier_detect_status(demod, status)); @@ -10005,7 +10005,7 @@ static int aud_ctrl_get_cfg_volume(struct drx_demod_instance *demod, struct drx_cfg_aud_volume *volume) { struct i2c_device_addr *dev_addr = NULL; - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; u16 r_volume = 0; u16 r_avc = 0; @@ -10017,7 +10017,7 @@ aud_ctrl_get_cfg_volume(struct drx_demod_instance *demod, struct drx_cfg_aud_vol } dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; /* power up */ if (ext_attr->aud_data.audio_is_active == false) { @@ -10138,7 +10138,7 @@ static int aud_ctrl_set_cfg_volume(struct drx_demod_instance *demod, struct drx_cfg_aud_volume *volume) { struct i2c_device_addr *dev_addr = NULL; - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; u16 w_volume = 0; u16 w_avc = 0; @@ -10148,7 +10148,7 @@ aud_ctrl_set_cfg_volume(struct drx_demod_instance *demod, struct drx_cfg_aud_vol } dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; /* power up */ if (ext_attr->aud_data.audio_is_active == false) { @@ -10272,7 +10272,7 @@ static int aud_ctrl_get_cfg_output_i2s(struct drx_demod_instance *demod, struct drx_cfg_i2s_output *output) { struct i2c_device_addr *dev_addr = NULL; - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; u16 w_i2s_config = 0; u16 r_i2s_freq = 0; @@ -10282,7 +10282,7 @@ aud_ctrl_get_cfg_output_i2s(struct drx_demod_instance *demod, struct drx_cfg_i2s } dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; /* power up */ if (ext_attr->aud_data.audio_is_active == false) { @@ -10374,7 +10374,7 @@ static int aud_ctrl_set_cfg_output_i2s(struct drx_demod_instance *demod, struct drx_cfg_i2s_output *output) { struct i2c_device_addr *dev_addr = NULL; - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; u16 w_i2s_config = 0; u16 w_i2s_pads_data_da = 0; @@ -10387,7 +10387,7 @@ aud_ctrl_set_cfg_output_i2s(struct drx_demod_instance *demod, struct drx_cfg_i2s } dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; /* power up */ if (ext_attr->aud_data.audio_is_active == false) { @@ -10529,13 +10529,13 @@ static int aud_ctrl_get_cfg_auto_sound(struct drx_demod_instance *demod, enum drx_cfg_aud_auto_sound *auto_sound) { - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; u16 r_modus = 0; if (auto_sound == NULL) return DRX_STS_INVALID_ARG; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; /* power up */ if (ext_attr->aud_data.audio_is_active == false) { @@ -10583,7 +10583,7 @@ aud_ctr_setl_cfg_auto_sound(struct drx_demod_instance *demod, enum drx_cfg_aud_auto_sound *auto_sound) { struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; - pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; + struct drxj_data *ext_attr = (struct drxj_data *) NULL; u16 r_modus = 0; u16 w_modus = 0; @@ -10593,7 +10593,7 @@ aud_ctr_setl_cfg_auto_sound(struct drx_demod_instance *demod, } dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; /* power up */ if (ext_attr->aud_data.audio_is_active == false) { @@ -10648,7 +10648,7 @@ static int aud_ctrl_get_cfg_ass_thres(struct drx_demod_instance *demod, struct drx_cfg_aud_ass_thres *thres) { struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; - pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; + struct drxj_data *ext_attr = (struct drxj_data *) NULL; u16 thres_a2 = 0; u16 thres_btsc = 0; @@ -10659,7 +10659,7 @@ aud_ctrl_get_cfg_ass_thres(struct drx_demod_instance *demod, struct drx_cfg_aud_ } dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; /* power up */ if (ext_attr->aud_data.audio_is_active == false) { @@ -10692,14 +10692,14 @@ static int aud_ctrl_set_cfg_ass_thres(struct drx_demod_instance *demod, struct drx_cfg_aud_ass_thres *thres) { struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; - pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; + struct drxj_data *ext_attr = (struct drxj_data *) NULL; if (thres == NULL) { return DRX_STS_INVALID_ARG; } dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; /* power up */ if (ext_attr->aud_data.audio_is_active == false) { @@ -10730,7 +10730,7 @@ static int aud_ctrl_get_cfg_carrier(struct drx_demod_instance *demod, struct drx_cfg_aud_carriers *carriers) { struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; - pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; + struct drxj_data *ext_attr = (struct drxj_data *) NULL; u16 w_modus = 0; @@ -10753,7 +10753,7 @@ aud_ctrl_get_cfg_carrier(struct drx_demod_instance *demod, struct drx_cfg_aud_ca } dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; /* power up */ if (ext_attr->aud_data.audio_is_active == false) { @@ -10834,7 +10834,7 @@ static int aud_ctrl_set_cfg_carrier(struct drx_demod_instance *demod, struct drx_cfg_aud_carriers *carriers) { struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; - pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; + struct drxj_data *ext_attr = (struct drxj_data *) NULL; u16 w_modus = 0; u16 r_modus = 0; @@ -10852,7 +10852,7 @@ aud_ctrl_set_cfg_carrier(struct drx_demod_instance *demod, struct drx_cfg_aud_ca } dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; /* power up */ if (ext_attr->aud_data.audio_is_active == false) { @@ -10934,7 +10934,7 @@ static int aud_ctrl_get_cfg_mixer(struct drx_demod_instance *demod, struct drx_cfg_aud_mixer *mixer) { struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; - pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; + struct drxj_data *ext_attr = (struct drxj_data *) NULL; u16 src_i2s_matr = 0; u16 fm_matr = 0; @@ -10944,7 +10944,7 @@ aud_ctrl_get_cfg_mixer(struct drx_demod_instance *demod, struct drx_cfg_aud_mixe } dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; /* power up */ if (ext_attr->aud_data.audio_is_active == false) { @@ -11029,7 +11029,7 @@ static int aud_ctrl_set_cfg_mixer(struct drx_demod_instance *demod, struct drx_cfg_aud_mixer *mixer) { struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; - pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; + struct drxj_data *ext_attr = (struct drxj_data *) NULL; u16 src_i2s_matr = 0; u16 fm_matr = 0; @@ -11039,7 +11039,7 @@ aud_ctrl_set_cfg_mixer(struct drx_demod_instance *demod, struct drx_cfg_aud_mixe } dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; /* power up */ if (ext_attr->aud_data.audio_is_active == false) { @@ -11137,7 +11137,7 @@ static int aud_ctrl_set_cfg_av_sync(struct drx_demod_instance *demod, enum drx_cfg_aud_av_sync *av_sync) { struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; - pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; + struct drxj_data *ext_attr = (struct drxj_data *) NULL; u16 w_aud_vid_sync = 0; @@ -11146,7 +11146,7 @@ aud_ctrl_set_cfg_av_sync(struct drx_demod_instance *demod, enum drx_cfg_aud_av_s } dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; /* power up */ if (ext_attr->aud_data.audio_is_active == false) { @@ -11202,7 +11202,7 @@ static int aud_ctrl_get_cfg_av_sync(struct drx_demod_instance *demod, enum drx_cfg_aud_av_sync *av_sync) { struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; - pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; + struct drxj_data *ext_attr = (struct drxj_data *) NULL; u16 w_aud_vid_sync = 0; @@ -11211,7 +11211,7 @@ aud_ctrl_get_cfg_av_sync(struct drx_demod_instance *demod, enum drx_cfg_aud_av_s } dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; /* power up */ if (ext_attr->aud_data.audio_is_active == false) { @@ -11291,7 +11291,7 @@ static int aud_ctrl_set_cfg_dev(struct drx_demod_instance *demod, enum drx_cfg_aud_deviation *dev) { struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; - pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; + struct drxj_data *ext_attr = (struct drxj_data *) NULL; u16 w_modus = 0; u16 r_modus = 0; @@ -11300,7 +11300,7 @@ aud_ctrl_set_cfg_dev(struct drx_demod_instance *demod, enum drx_cfg_aud_deviatio return DRX_STS_INVALID_ARG; } - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; dev_addr = demod->my_i2c_dev_addr; CHK_ERROR(aud_get_modus(demod, &r_modus)); @@ -11343,7 +11343,7 @@ static int aud_ctrl_get_cfg_prescale(struct drx_demod_instance *demod, struct drx_cfg_aud_prescale *presc) { struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; - pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; + struct drxj_data *ext_attr = (struct drxj_data *) NULL; u16 r_max_fm_deviation = 0; u16 r_nicam_prescaler = 0; @@ -11353,7 +11353,7 @@ aud_ctrl_get_cfg_prescale(struct drx_demod_instance *demod, struct drx_cfg_aud_p } dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; /* power up */ if (ext_attr->aud_data.audio_is_active == false) { @@ -11417,7 +11417,7 @@ static int aud_ctrl_set_cfg_prescale(struct drx_demod_instance *demod, struct drx_cfg_aud_prescale *presc) { struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; - pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; + struct drxj_data *ext_attr = (struct drxj_data *) NULL; u16 w_max_fm_deviation = 0; u16 nicam_prescaler; @@ -11427,7 +11427,7 @@ aud_ctrl_set_cfg_prescale(struct drx_demod_instance *demod, struct drx_cfg_aud_p } dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; /* power up */ if (ext_attr->aud_data.audio_is_active == false) { @@ -11498,7 +11498,7 @@ rw_error: static int aud_ctrl_beep(struct drx_demod_instance *demod, struct drx_aud_beep *beep) { struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; - pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; + struct drxj_data *ext_attr = (struct drxj_data *) NULL; u16 the_beep = 0; u16 volume = 0; @@ -11509,7 +11509,7 @@ static int aud_ctrl_beep(struct drx_demod_instance *demod, struct drx_aud_beep * } dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; /* power up */ if (ext_attr->aud_data.audio_is_active == false) { @@ -11556,7 +11556,7 @@ static int aud_ctrl_set_standard(struct drx_demod_instance *demod, enum drx_aud_standard *standard) { struct i2c_device_addr *dev_addr = NULL; - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; enum drx_standard current_standard = DRX_STANDARD_UNKNOWN; u16 w_standard = 0; @@ -11572,7 +11572,7 @@ aud_ctrl_set_standard(struct drx_demod_instance *demod, enum drx_aud_standard *s } dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; /* power up */ if (ext_attr->aud_data.audio_is_active == false) { @@ -11733,7 +11733,7 @@ static int aud_ctrl_get_standard(struct drx_demod_instance *demod, enum drx_aud_standard *standard) { struct i2c_device_addr *dev_addr = NULL; - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; u16 r_data = 0; @@ -11741,7 +11741,7 @@ aud_ctrl_get_standard(struct drx_demod_instance *demod, enum drx_aud_standard *s return DRX_STS_INVALID_ARG; } - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; /* power up */ @@ -11912,7 +11912,7 @@ static int get_oob_lock_status(struct drx_demod_instance *demod, struct i2c_device_addr *dev_addr, enum drx_lock_status *oob_lock) { - drxjscu_cmd_t scu_cmd; + struct drxjscu_cmd scu_cmd; u16 cmd_result[2]; u16 oob_lock_state; @@ -12385,11 +12385,11 @@ static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_par #ifndef DRXJ_DIGITAL_ONLY s32 freq = 0; /* KHz */ struct i2c_device_addr *dev_addr = NULL; - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; u16 i = 0; bool mirror_freq_spectOOB = false; u16 trk_filter_value = 0; - drxjscu_cmd_t scu_cmd; + struct drxjscu_cmd scu_cmd; u16 set_param_parameters[3]; u16 cmd_result[2] = { 0, 0 }; s16 nyquist_coeffs[4][(NYQFILTERLEN + 1) / 2] = { @@ -12408,7 +12408,7 @@ static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_par u16 mode_index; dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; mirror_freq_spectOOB = ext_attr->mirror_freq_spectOOB; /* Check parameters */ @@ -12657,11 +12657,11 @@ ctrl_get_oob(struct drx_demod_instance *demod, struct drxoob_status *oob_status) { #ifndef DRXJ_DIGITAL_ONLY struct i2c_device_addr *dev_addr = NULL; - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; u16 data = 0; dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; /* check arguments */ if (oob_status == NULL) { @@ -12700,13 +12700,13 @@ static int ctrl_set_cfg_oob_pre_saw(struct drx_demod_instance *demod, u16 *cfg_data) { struct i2c_device_addr *dev_addr = NULL; - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; if (cfg_data == NULL) { return (DRX_STS_INVALID_ARG); } dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; WR16(dev_addr, ORX_NSU_AOX_STHR_W__A, *cfg_data); ext_attr->oob_pre_saw = *cfg_data; @@ -12726,12 +12726,12 @@ rw_error: static int ctrl_get_cfg_oob_pre_saw(struct drx_demod_instance *demod, u16 *cfg_data) { - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; if (cfg_data == NULL) { return (DRX_STS_INVALID_ARG); } - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; *cfg_data = ext_attr->oob_pre_saw; @@ -12742,21 +12742,20 @@ ctrl_get_cfg_oob_pre_saw(struct drx_demod_instance *demod, u16 *cfg_data) /** * \fn int ctrl_set_cfg_oob_lo_power() * \brief Configure LO Power value -* \param cfg_data Pointer to p_drxj_cfg_oob_lo_power_t -* \return Error code +* \param cfg_data Pointer to enum drxj_cfg_oob_lo_power ** \return Error code */ #ifndef DRXJ_DIGITAL_ONLY static int -ctrl_set_cfg_oob_lo_power(struct drx_demod_instance *demod, p_drxj_cfg_oob_lo_power_t cfg_data) +ctrl_set_cfg_oob_lo_power(struct drx_demod_instance *demod, enum drxj_cfg_oob_lo_power *cfg_data) { struct i2c_device_addr *dev_addr = NULL; - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; if (cfg_data == NULL) { return (DRX_STS_INVALID_ARG); } dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; WR16(dev_addr, ORX_NSU_AOX_LOPOW_W__A, *cfg_data); ext_attr->oob_lo_pow = *cfg_data; @@ -12769,19 +12768,18 @@ rw_error: /** * \fn int ctrl_get_cfg_oob_lo_power() * \brief Configure LO Power value -* \param cfg_data Pointer to p_drxj_cfg_oob_lo_power_t -* \return Error code +* \param cfg_data Pointer to enum drxj_cfg_oob_lo_power ** \return Error code */ #ifndef DRXJ_DIGITAL_ONLY static int -ctrl_get_cfg_oob_lo_power(struct drx_demod_instance *demod, p_drxj_cfg_oob_lo_power_t cfg_data) +ctrl_get_cfg_oob_lo_power(struct drx_demod_instance *demod, enum drxj_cfg_oob_lo_power *cfg_data) { - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; if (cfg_data == NULL) { return (DRX_STS_INVALID_ARG); } - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; *cfg_data = ext_attr->oob_lo_pow; @@ -12818,7 +12816,7 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) s32 tuner_get_freq = 0; s32 tuner_freq_offset = 0; s32 intermediate_freq = 0; - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; struct i2c_device_addr *dev_addr = NULL; enum drx_standard standard = DRX_STANDARD_UNKNOWN; u32 tuner_mode = 0; @@ -12837,7 +12835,7 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) common_attr = (struct drx_common_attr *) demod->my_common_attr; dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; standard = ext_attr->standard; /* check valid standards */ @@ -13196,7 +13194,7 @@ static int ctrl_get_channel(struct drx_demod_instance *demod, struct drx_channel *channel) { struct i2c_device_addr *dev_addr = NULL; - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; enum drx_lock_status lock_status = DRX_NOT_LOCKED; enum drx_standard standard = DRX_STANDARD_UNKNOWN; struct drx_common_attr *common_attr = NULL; @@ -13215,7 +13213,7 @@ ctrl_get_channel(struct drx_demod_instance *demod, struct drx_channel *channel) } dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; standard = ext_attr->standard; common_attr = (struct drx_common_attr *) demod->my_common_attr; @@ -13323,7 +13321,7 @@ ctrl_get_channel(struct drx_demod_instance *demod, struct drx_channel *channel) } /* if (standard == DRX_STANDARD_ITU_B) */ { - drxjscu_cmd_t cmd_scu = + struct drxjscu_cmd cmd_scu = { /* command */ 0, /* parameter_len */ 0, /* result_len */ 0, @@ -13447,7 +13445,7 @@ static int ctrl_sig_quality(struct drx_demod_instance *demod, struct drx_sig_quality *sig_quality) { struct i2c_device_addr *dev_addr = NULL; - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; enum drx_standard standard = DRX_STANDARD_UNKNOWN; enum drx_lock_status lock_status = DRX_NOT_LOCKED; u16 min_mer = 0; @@ -13459,7 +13457,7 @@ ctrl_sig_quality(struct drx_demod_instance *demod, struct drx_sig_quality *sig_q return (DRX_STS_INVALID_ARG); } - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; standard = ext_attr->standard; /* get basic information */ @@ -13581,9 +13579,9 @@ static int ctrl_lock_status(struct drx_demod_instance *demod, enum drx_lock_status *lock_stat) { enum drx_standard standard = DRX_STANDARD_UNKNOWN; - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; struct i2c_device_addr *dev_addr = NULL; - drxjscu_cmd_t cmd_scu = { /* command */ 0, + struct drxjscu_cmd cmd_scu = { /* command */ 0, /* parameter_len */ 0, /* result_len */ 0, /* *parameter */ NULL, @@ -13598,7 +13596,7 @@ ctrl_lock_status(struct drx_demod_instance *demod, enum drx_lock_status *lock_st } dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; standard = ext_attr->standard; *lock_stat = DRX_NOT_LOCKED; @@ -13686,7 +13684,7 @@ ctrl_constel(struct drx_demod_instance *demod, struct drx_complex *complex_nr) } /* read device info */ - standard = ((pdrxj_data_t) demod->my_ext_attr)->standard; + standard = ((struct drxj_data *) demod->my_ext_attr)->standard; /* Read constellation point */ switch (standard) { @@ -13725,7 +13723,7 @@ rw_error: static int ctrl_set_standard(struct drx_demod_instance *demod, enum drx_standard *standard) { - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; enum drx_standard prev_standard; /* check arguments */ @@ -13733,7 +13731,7 @@ ctrl_set_standard(struct drx_demod_instance *demod, enum drx_standard *standard) return (DRX_STS_INVALID_ARG); } - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; prev_standard = ext_attr->standard; /* @@ -13825,8 +13823,8 @@ rw_error: static int ctrl_get_standard(struct drx_demod_instance *demod, enum drx_standard *standard) { - pdrxj_data_t ext_attr = NULL; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + struct drxj_data *ext_attr = NULL; + ext_attr = (struct drxj_data *) demod->my_ext_attr; /* check arguments */ if (standard == NULL) { @@ -13853,13 +13851,13 @@ static int ctrl_get_cfg_symbol_clock_offset(struct drx_demod_instance *demod, s32 *rate_offset) { enum drx_standard standard = DRX_STANDARD_UNKNOWN; - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; /* check arguments */ if (rate_offset == NULL) return (DRX_STS_INVALID_ARG); - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; standard = ext_attr->standard; switch (standard) { @@ -13900,12 +13898,12 @@ static int ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode) { struct drx_common_attr *common_attr = (struct drx_common_attr *) NULL; - pdrxj_data_t ext_attr = (pdrxj_data_t) NULL; + struct drxj_data *ext_attr = (struct drxj_data *) NULL; struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; u16 sio_cc_pwd_mode = 0; common_attr = (struct drx_common_attr *) demod->my_common_attr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; dev_addr = demod->my_i2c_dev_addr; /* Check arguments */ @@ -14027,7 +14025,7 @@ rw_error: static int ctrl_version(struct drx_demod_instance *demod, struct drx_version_list **version_list) { - pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); + struct drxj_data *ext_attr = (struct drxj_data *) (NULL); struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL); u16 ucode_major_minor = 0; /* BCD Ma:Ma:Ma:Mi */ @@ -14046,7 +14044,7 @@ ctrl_version(struct drx_demod_instance *demod, struct drx_version_list **version static char device_name[] = "Device"; dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; common_attr = (struct drx_common_attr *) demod->my_common_attr; /* Microcode version *************************************** */ @@ -14282,10 +14280,10 @@ ctrl_u_codeUpload(struct drx_demod_instance *demod, u16 mc_magic_word = 0; u8 *mc_data = (u8 *)(NULL); struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); - pdrxj_data_t ext_attr = (pdrxj_data_t) (NULL); + struct drxj_data *ext_attr = (struct drxj_data *) (NULL); dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; /* Check arguments */ if ((mc_info == NULL) || @@ -14456,7 +14454,7 @@ ctrl_u_codeUpload(struct drx_demod_instance *demod, static int ctrl_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength) { - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; enum drx_standard standard = DRX_STANDARD_UNKNOWN; /* Check arguments */ @@ -14464,7 +14462,7 @@ ctrl_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength) return (DRX_STS_INVALID_ARG); } - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; standard = ext_attr->standard; *sig_strength = 0; @@ -14505,13 +14503,13 @@ rw_error: /** * \fn int ctrl_get_cfg_oob_misc() * \brief Get current state information of OOB. -* \param pointer to drxj_cfg_oob_misc_t. +* \param pointer to struct drxj_cfg_oob_misc. * \return int. * */ #ifndef DRXJ_DIGITAL_ONLY static int -ctrl_get_cfg_oob_misc(struct drx_demod_instance *demod, p_drxj_cfg_oob_misc_t misc) +ctrl_get_cfg_oob_misc(struct drx_demod_instance *demod, struct drxj_cfg_oob_misc *misc) { struct i2c_device_addr *dev_addr = NULL; u16 lock = 0U; @@ -14558,12 +14556,12 @@ rw_error: /** * \fn int ctrl_get_cfg_vsb_misc() * \brief Get current state information of OOB. -* \param pointer to drxj_cfg_oob_misc_t. +* \param pointer to struct drxj_cfg_oob_misc. * \return int. * */ static int -ctrl_get_cfg_vsb_misc(struct drx_demod_instance *demod, p_drxj_cfg_vsb_misc_t misc) +ctrl_get_cfg_vsb_misc(struct drx_demod_instance *demod, struct drxj_cfg_vsb_misc *misc) { struct i2c_device_addr *dev_addr = NULL; @@ -14594,7 +14592,7 @@ rw_error: * */ static int -ctrl_set_cfg_agc_if(struct drx_demod_instance *demod, p_drxj_cfg_agc_t agc_settings) +ctrl_set_cfg_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings) { /* check arguments */ if (agc_settings == NULL) { @@ -14650,7 +14648,7 @@ ctrl_set_cfg_agc_if(struct drx_demod_instance *demod, p_drxj_cfg_agc_t agc_setti * */ static int -ctrl_get_cfg_agc_if(struct drx_demod_instance *demod, p_drxj_cfg_agc_t agc_settings) +ctrl_get_cfg_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings) { /* check arguments */ if (agc_settings == NULL) { @@ -14697,7 +14695,7 @@ ctrl_get_cfg_agc_if(struct drx_demod_instance *demod, p_drxj_cfg_agc_t agc_setti * */ static int -ctrl_set_cfg_agc_rf(struct drx_demod_instance *demod, p_drxj_cfg_agc_t agc_settings) +ctrl_set_cfg_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings) { /* check arguments */ if (agc_settings == NULL) { @@ -14753,7 +14751,7 @@ ctrl_set_cfg_agc_rf(struct drx_demod_instance *demod, p_drxj_cfg_agc_t agc_setti * */ static int -ctrl_get_cfg_agc_rf(struct drx_demod_instance *demod, p_drxj_cfg_agc_t agc_settings) +ctrl_get_cfg_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings) { /* check arguments */ if (agc_settings == NULL) { @@ -14804,7 +14802,7 @@ ctrl_get_cfg_agc_internal(struct drx_demod_instance *demod, u16 *agc_internal) { struct i2c_device_addr *dev_addr = NULL; enum drx_lock_status lock_status = DRX_NOT_LOCKED; - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; u16 iqm_cf_scale_sh = 0; u16 iqm_cf_power = 0; u16 iqm_cf_amp = 0; @@ -14815,7 +14813,7 @@ ctrl_get_cfg_agc_internal(struct drx_demod_instance *demod, u16 *agc_internal) return (DRX_STS_INVALID_ARG); } dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; CHK_ERROR(ctrl_lock_status(demod, &lock_status)); if (lock_status != DRXJ_DEMOD_LOCK && lock_status != DRX_LOCKED) { @@ -14883,13 +14881,13 @@ rw_error: * */ static int -ctrl_set_cfg_pre_saw(struct drx_demod_instance *demod, p_drxj_cfg_pre_saw_t pre_saw) +ctrl_set_cfg_pre_saw(struct drx_demod_instance *demod, struct drxj_cfg_pre_saw *pre_saw) { struct i2c_device_addr *dev_addr = NULL; - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; /* check arguments */ if ((pre_saw == NULL) || (pre_saw->reference > IQM_AF_PDREF__M) @@ -14952,10 +14950,10 @@ rw_error: * */ static int -ctrl_set_cfg_afe_gain(struct drx_demod_instance *demod, p_drxj_cfg_afe_gain_t afe_gain) +ctrl_set_cfg_afe_gain(struct drx_demod_instance *demod, struct drxj_cfg_afe_gain *afe_gain) { struct i2c_device_addr *dev_addr = NULL; - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; u8 gain = 0; /* check arguments */ @@ -14964,7 +14962,7 @@ ctrl_set_cfg_afe_gain(struct drx_demod_instance *demod, p_drxj_cfg_afe_gain_t af } dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; switch (afe_gain->standard) { case DRX_STANDARD_8VSB: /* fallthrough */ @@ -15028,15 +15026,15 @@ rw_error: * */ static int -ctrl_get_cfg_pre_saw(struct drx_demod_instance *demod, p_drxj_cfg_pre_saw_t pre_saw) +ctrl_get_cfg_pre_saw(struct drx_demod_instance *demod, struct drxj_cfg_pre_saw *pre_saw) { - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; /* check arguments */ if (pre_saw == NULL) return (DRX_STS_INVALID_ARG); - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; switch (pre_saw->standard) { case DRX_STANDARD_8VSB: @@ -15085,9 +15083,9 @@ ctrl_get_cfg_pre_saw(struct drx_demod_instance *demod, p_drxj_cfg_pre_saw_t pre_ * */ static int -ctrl_get_cfg_afe_gain(struct drx_demod_instance *demod, p_drxj_cfg_afe_gain_t afe_gain) +ctrl_get_cfg_afe_gain(struct drx_demod_instance *demod, struct drxj_cfg_afe_gain *afe_gain) { - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; /* check arguments */ if (afe_gain == NULL) @@ -15192,18 +15190,18 @@ static int ctrl_set_cfg(struct drx_demod_instance *demod, struct drx_cfg *config case DRX_CFG_PINS_SAFE_MODE: return ctrl_set_cfg_pdr_safe_mode(demod, (bool *)config->cfg_data); case DRXJ_CFG_AGC_RF: - return ctrl_set_cfg_agc_rf(demod, (p_drxj_cfg_agc_t) config->cfg_data); + return ctrl_set_cfg_agc_rf(demod, (struct drxj_cfg_agc *) config->cfg_data); case DRXJ_CFG_AGC_IF: - return ctrl_set_cfg_agc_if(demod, (p_drxj_cfg_agc_t) config->cfg_data); + return ctrl_set_cfg_agc_if(demod, (struct drxj_cfg_agc *) config->cfg_data); case DRXJ_CFG_PRE_SAW: return ctrl_set_cfg_pre_saw(demod, - (p_drxj_cfg_pre_saw_t) config->cfg_data); + (struct drxj_cfg_pre_saw *) config->cfg_data); case DRXJ_CFG_AFE_GAIN: return ctrl_set_cfg_afe_gain(demod, - (p_drxj_cfg_afe_gain_t) config->cfg_data); + (struct drxj_cfg_afe_gain *) config->cfg_data); case DRXJ_CFG_SMART_ANT: return ctrl_set_cfg_smart_ant(demod, - (p_drxj_cfg_smart_ant_t) (config-> + (struct drxj_cfg_smart_ant *) (config-> cfg_data)); case DRXJ_CFG_RESET_PACKET_ERR: return ctrl_set_cfg_reset_pkt_err(demod); @@ -15212,23 +15210,23 @@ static int ctrl_set_cfg(struct drx_demod_instance *demod, struct drx_cfg *config return ctrl_set_cfg_oob_pre_saw(demod, (u16 *)(config->cfg_data)); case DRXJ_CFG_OOB_LO_POW: return ctrl_set_cfg_oob_lo_power(demod, - (p_drxj_cfg_oob_lo_power_t) (config-> + (enum drxj_cfg_oob_lo_power *) (config-> cfg_data)); case DRXJ_CFG_ATV_MISC: return ctrl_set_cfg_atv_misc(demod, - (p_drxj_cfg_atv_misc_t) config->cfg_data); + (struct drxj_cfg_atv_misc *) config->cfg_data); case DRXJ_CFG_ATV_EQU_COEF: return ctrl_set_cfg_atv_equ_coef(demod, - (p_drxj_cfg_atv_equ_coef_t) config-> + (struct drxj_cfg_atv_equ_coef *) config-> cfg_data); case DRXJ_CFG_ATV_OUTPUT: return ctrl_set_cfg_atv_output(demod, - (p_drxj_cfg_atv_output_t) config-> + (struct drxj_cfg_atv_output *) config-> cfg_data); #endif case DRXJ_CFG_MPEG_OUTPUT_MISC: return ctrl_set_cfg_mpeg_output_misc(demod, - (p_drxj_cfg_mpeg_output_misc_t) + (struct drxj_cfg_mpeg_output_misc *) config->cfg_data); #ifndef DRXJ_EXCLUDE_AUDIO case DRX_CFG_AUD_VOLUME: @@ -15301,60 +15299,60 @@ static int ctrl_get_cfg(struct drx_demod_instance *demod, struct drx_cfg *config case DRX_CFG_PINS_SAFE_MODE: return ctrl_get_cfg_pdr_safe_mode(demod, (bool *)config->cfg_data); case DRXJ_CFG_AGC_RF: - return ctrl_get_cfg_agc_rf(demod, (p_drxj_cfg_agc_t) config->cfg_data); + return ctrl_get_cfg_agc_rf(demod, (struct drxj_cfg_agc *) config->cfg_data); case DRXJ_CFG_AGC_IF: - return ctrl_get_cfg_agc_if(demod, (p_drxj_cfg_agc_t) config->cfg_data); + return ctrl_get_cfg_agc_if(demod, (struct drxj_cfg_agc *) config->cfg_data); case DRXJ_CFG_AGC_INTERNAL: return ctrl_get_cfg_agc_internal(demod, (u16 *)config->cfg_data); case DRXJ_CFG_PRE_SAW: return ctrl_get_cfg_pre_saw(demod, - (p_drxj_cfg_pre_saw_t) config->cfg_data); + (struct drxj_cfg_pre_saw *) config->cfg_data); case DRXJ_CFG_AFE_GAIN: return ctrl_get_cfg_afe_gain(demod, - (p_drxj_cfg_afe_gain_t) config->cfg_data); + (struct drxj_cfg_afe_gain *) config->cfg_data); case DRXJ_CFG_ACCUM_CR_RS_CW_ERR: return ctrl_get_accum_cr_rs_cw_err(demod, (u32 *)config->cfg_data); case DRXJ_CFG_FEC_MERS_SEQ_COUNT: return ctrl_get_fec_meas_seq_count(demod, (u16 *)config->cfg_data); case DRXJ_CFG_VSB_MISC: return ctrl_get_cfg_vsb_misc(demod, - (p_drxj_cfg_vsb_misc_t) config->cfg_data); + (struct drxj_cfg_vsb_misc *) config->cfg_data); case DRXJ_CFG_SYMBOL_CLK_OFFSET: return ctrl_get_cfg_symbol_clock_offset(demod, (s32 *)config->cfg_data); #ifndef DRXJ_DIGITAL_ONLY case DRXJ_CFG_OOB_MISC: return ctrl_get_cfg_oob_misc(demod, - (p_drxj_cfg_oob_misc_t) config->cfg_data); + (struct drxj_cfg_oob_misc *) config->cfg_data); case DRXJ_CFG_OOB_PRE_SAW: return ctrl_get_cfg_oob_pre_saw(demod, (u16 *)(config->cfg_data)); case DRXJ_CFG_OOB_LO_POW: return ctrl_get_cfg_oob_lo_power(demod, - (p_drxj_cfg_oob_lo_power_t) (config-> + (enum drxj_cfg_oob_lo_power *) (config-> cfg_data)); case DRXJ_CFG_ATV_EQU_COEF: return ctrl_get_cfg_atv_equ_coef(demod, - (p_drxj_cfg_atv_equ_coef_t) config-> + (struct drxj_cfg_atv_equ_coef *) config-> cfg_data); case DRXJ_CFG_ATV_MISC: return ctrl_get_cfg_atv_misc(demod, - (p_drxj_cfg_atv_misc_t) config->cfg_data); + (struct drxj_cfg_atv_misc *) config->cfg_data); case DRXJ_CFG_ATV_OUTPUT: return ctrl_get_cfg_atv_output(demod, - (p_drxj_cfg_atv_output_t) config-> + (struct drxj_cfg_atv_output *) config-> cfg_data); case DRXJ_CFG_ATV_AGC_STATUS: return ctrl_get_cfg_atv_agc_status(demod, - (p_drxj_cfg_atv_agc_status_t) config-> + (struct drxj_cfg_atv_agc_status *) config-> cfg_data); #endif case DRXJ_CFG_MPEG_OUTPUT_MISC: return ctrl_get_cfg_mpeg_output_misc(demod, - (p_drxj_cfg_mpeg_output_misc_t) + (struct drxj_cfg_mpeg_output_misc *) config->cfg_data); case DRXJ_CFG_HW_CFG: return ctrl_get_cfg_hw_cfg(demod, - (p_drxj_cfg_hw_cfg_t) config->cfg_data); + (struct drxj_cfg_hw_cfg *) config->cfg_data); #ifndef DRXJ_EXCLUDE_AUDIO case DRX_CFG_AUD_VOLUME: return aud_ctrl_get_cfg_volume(demod, @@ -15421,7 +15419,7 @@ rw_error: int drxj_open(struct drx_demod_instance *demod) { struct i2c_device_addr *dev_addr = NULL; - pdrxj_data_t ext_attr = NULL; + struct drxj_data *ext_attr = NULL; struct drx_common_attr *common_attr = NULL; u32 driver_version = 0; struct drxu_code_info ucode_info; @@ -15433,7 +15431,7 @@ int drxj_open(struct drx_demod_instance *demod) } dev_addr = demod->my_i2c_dev_addr; - ext_attr = (pdrxj_data_t) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; common_attr = (struct drx_common_attr *) demod->my_common_attr; CHK_ERROR(power_up_device(demod)); diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.h b/drivers/media/dvb-frontends/drx39xyj/drxj.h index 91272f10..f41a61e 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.h +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.h @@ -1,3 +1,4 @@ + /* Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. All rights reserved. @@ -74,7 +75,7 @@ TYPEDEFS /*============================================================================*/ /*============================================================================*/ - typedef struct { + struct drxjscu_cmd { u16 command; /**< Command number */ u16 parameter_len; @@ -84,8 +85,7 @@ TYPEDEFS u16 *parameter; /**< General purpous param */ u16 *result; - /**< General purpous param */ - } drxjscu_cmd_t, *p_drxjscu_cmd_t; + /**< General purpous param */}; /*============================================================================*/ /*============================================================================*/ @@ -111,7 +111,7 @@ TYPEDEFS /*#define DRX_CTRL_BASE (0x0000)*/ #define DRXJ_CTRL_CFG_BASE (0x1000) - typedef enum { + enum drxj_cfg_type { DRXJ_CFG_AGC_RF = DRXJ_CTRL_CFG_BASE, DRXJ_CFG_AGC_IF, DRXJ_CFG_AGC_INTERNAL, @@ -136,96 +136,85 @@ TYPEDEFS DRXJ_CFG_HW_CFG, DRXJ_CFG_OOB_LO_POW, - DRXJ_CFG_MAX /* dummy, never to be used */ - } drxj_cfg_type_t, *pdrxj_cfg_type_t; + DRXJ_CFG_MAX /* dummy, never to be used */}; /** -* /struct drxj_cfg_smart_ant_io_t -* smart antenna i/o. +* /struct enum drxj_cfg_smart_ant_io * smart antenna i/o. */ - typedef enum drxj_cfg_smart_ant_io_t { - DRXJ_SMT_ANT_OUTPUT = 0, - DRXJ_SMT_ANT_INPUT - } drxj_cfg_smart_ant_io_t, *pdrxj_cfg_smart_ant_io_t; +enum drxj_cfg_smart_ant_io { + DRXJ_SMT_ANT_OUTPUT = 0, + DRXJ_SMT_ANT_INPUT +}; /** -* /struct drxj_cfg_smart_ant_t -* Set smart antenna. +* /struct struct drxj_cfg_smart_ant * Set smart antenna. */ - typedef struct { - drxj_cfg_smart_ant_io_t io; + struct drxj_cfg_smart_ant { + enum drxj_cfg_smart_ant_io io; u16 ctrl_data; - } drxj_cfg_smart_ant_t, *p_drxj_cfg_smart_ant_t; + }; /** * /struct DRXJAGCSTATUS_t * AGC status information from the DRXJ-IQM-AF. */ - typedef struct { - u16 IFAGC; - u16 RFAGC; - u16 digital_agc; - } drxj_agc_status_t, *pdrxj_agc_status_t; +struct drxj_agc_status { + u16 IFAGC; + u16 RFAGC; + u16 digital_agc; +}; /* DRXJ_CFG_AGC_RF, DRXJ_CFG_AGC_IF */ /** -* /struct drxj_agc_ctrl_mode_t -* Available AGCs modes in the DRXJ. +* /struct enum drxj_agc_ctrl_mode * Available AGCs modes in the DRXJ. */ - typedef enum { + enum drxj_agc_ctrl_mode { DRX_AGC_CTRL_AUTO = 0, DRX_AGC_CTRL_USER, - DRX_AGC_CTRL_OFF - } drxj_agc_ctrl_mode_t, *pdrxj_agc_ctrl_mode_t; + DRX_AGC_CTRL_OFF}; /** -* /struct drxj_cfg_agc_t -* Generic interface for all AGCs present on the DRXJ. +* /struct struct drxj_cfg_agc * Generic interface for all AGCs present on the DRXJ. */ - typedef struct { + struct drxj_cfg_agc { enum drx_standard standard; /* standard for which these settings apply */ - drxj_agc_ctrl_mode_t ctrl_mode; /* off, user, auto */ + enum drxj_agc_ctrl_mode ctrl_mode; /* off, user, auto */ u16 output_level; /* range dependent on AGC */ u16 min_output_level; /* range dependent on AGC */ u16 max_output_level; /* range dependent on AGC */ u16 speed; /* range dependent on AGC */ u16 top; /* rf-agc take over point */ u16 cut_off_current; /* rf-agc is accelerated if output current - is below cut-off current */ - } drxj_cfg_agc_t, *p_drxj_cfg_agc_t; + is below cut-off current */}; /* DRXJ_CFG_PRE_SAW */ /** -* /struct drxj_cfg_pre_saw_t -* Interface to configure pre SAW sense. +* /struct struct drxj_cfg_pre_saw * Interface to configure pre SAW sense. */ - typedef struct { + struct drxj_cfg_pre_saw { enum drx_standard standard; /* standard to which these settings apply */ u16 reference; /* pre SAW reference value, range 0 .. 31 */ - bool use_pre_saw; /* true algorithms must use pre SAW sense */ - } drxj_cfg_pre_saw_t, *p_drxj_cfg_pre_saw_t; + bool use_pre_saw; /* true algorithms must use pre SAW sense */}; /* DRXJ_CFG_AFE_GAIN */ /** -* /struct drxj_cfg_afe_gain_t -* Interface to configure gain of AFE (LNA + PGA). +* /struct struct drxj_cfg_afe_gain * Interface to configure gain of AFE (LNA + PGA). */ - typedef struct { + struct drxj_cfg_afe_gain { enum drx_standard standard; /* standard to which these settings apply */ - u16 gain; /* gain in 0.1 dB steps, DRXJ range 140 .. 335 */ - } drxj_cfg_afe_gain_t, *p_drxj_cfg_afe_gain_t; + u16 gain; /* gain in 0.1 dB steps, DRXJ range 140 .. 335 */}; /** -* /struct DRXJrs_errors_t +* /struct drxjrs_errors * Available failure information in DRXJ_FEC_RS. * * Container for errors that are received in the most recently finished measurment period * */ - typedef struct { + struct drxjrs_errors { u16 nr_bit_errors; /**< no of pre RS bit errors */ u16 nr_symbol_errors; @@ -236,41 +225,35 @@ TYPEDEFS /**< no of post RS failures to decode */ u16 nr_snc_par_fail_count; /**< no of post RS bit erros */ - } DRXJrs_errors_t, *p_drxjrs_errors_t; + }; /** -* /struct drxj_cfg_vsb_misc_t -* symbol error rate +* /struct struct drxj_cfg_vsb_misc * symbol error rate */ - typedef struct { + struct drxj_cfg_vsb_misc { u32 symb_error; - /**< symbol error rate sps */ - } drxj_cfg_vsb_misc_t, *p_drxj_cfg_vsb_misc_t; + /**< symbol error rate sps */}; /** -* /enum drxj_mpeg_output_clock_rate_t -* Mpeg output clock rate. +* /enum enum drxj_mpeg_output_clock_rate * Mpeg output clock rate. * */ - typedef enum { + enum drxj_mpeg_start_width { DRXJ_MPEG_START_WIDTH_1CLKCYC, - DRXJ_MPEG_START_WIDTH_8CLKCYC - } drxj_mpeg_start_width_t, *pdrxj_mpeg_start_width_t; + DRXJ_MPEG_START_WIDTH_8CLKCYC}; /** -* /enum drxj_mpeg_output_clock_rate_t -* Mpeg output clock rate. +* /enum enum drxj_mpeg_output_clock_rate * Mpeg output clock rate. * */ - typedef enum { + enum drxj_mpeg_output_clock_rate { DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO, DRXJ_MPEGOUTPUT_CLOCK_RATE_75973K, DRXJ_MPEGOUTPUT_CLOCK_RATE_50625K, DRXJ_MPEGOUTPUT_CLOCK_RATE_37968K, DRXJ_MPEGOUTPUT_CLOCK_RATE_30375K, DRXJ_MPEGOUTPUT_CLOCK_RATE_25313K, - DRXJ_MPEGOUTPUT_CLOCK_RATE_21696K - } drxj_mpeg_output_clock_rate_t, *pdrxj_mpeg_output_clock_rate_t; + DRXJ_MPEGOUTPUT_CLOCK_RATE_21696K}; /** * /struct DRXJCfgMisc_t @@ -278,56 +261,47 @@ TYPEDEFS * reverse MPEG output bit order * set MPEG output clock rate */ - typedef struct { + struct drxj_cfg_mpeg_output_misc { bool disable_tei_handling; /**< if true pass (not change) TEI bit */ bool bit_reverse_mpeg_outout; /**< if true, parallel: msb on MD0; serial: lsb out first */ - drxj_mpeg_output_clock_rate_t mpeg_output_clock_rate; + enum drxj_mpeg_output_clock_rate mpeg_output_clock_rate; /**< set MPEG output clock rate that overwirtes the derived one from symbol rate */ - drxj_mpeg_start_width_t mpeg_start_width; /**< set MPEG output start width */ - } drxj_cfg_mpeg_output_misc_t, *p_drxj_cfg_mpeg_output_misc_t; + enum drxj_mpeg_start_width mpeg_start_width; /**< set MPEG output start width */}; /** -* /enum drxj_xtal_freq_t -* Supported external crystal reference frequency. +* /enum enum drxj_xtal_freq * Supported external crystal reference frequency. */ - typedef enum { + enum drxj_xtal_freq { DRXJ_XTAL_FREQ_RSVD, DRXJ_XTAL_FREQ_27MHZ, DRXJ_XTAL_FREQ_20P25MHZ, - DRXJ_XTAL_FREQ_4MHZ - } drxj_xtal_freq_t, *pdrxj_xtal_freq_t; + DRXJ_XTAL_FREQ_4MHZ}; /** -* /enum drxj_xtal_freq_t -* Supported external crystal reference frequency. +* /enum enum drxj_xtal_freq * Supported external crystal reference frequency. */ - typedef enum { + enum drxji2c_speed { DRXJ_I2C_SPEED_400KBPS, - DRXJ_I2C_SPEED_100KBPS - } drxji2c_speed_t, *pdrxji2c_speed_t; + DRXJ_I2C_SPEED_100KBPS}; /** -* /struct drxj_cfg_hw_cfg_t -* Get hw configuration, such as crystal reference frequency, I2C speed, etc... +* /struct struct drxj_cfg_hw_cfg * Get hw configuration, such as crystal reference frequency, I2C speed, etc... */ - typedef struct { - drxj_xtal_freq_t xtal_freq; + struct drxj_cfg_hw_cfg { + enum drxj_xtal_freq xtal_freq; /**< crystal reference frequency */ - drxji2c_speed_t i2c_speed; - /**< 100 or 400 kbps */ - } drxj_cfg_hw_cfg_t, *p_drxj_cfg_hw_cfg_t; + enum drxji2c_speed i2c_speed; + /**< 100 or 400 kbps */}; /* * DRXJ_CFG_ATV_MISC */ - typedef struct { + struct drxj_cfg_atv_misc { s16 peak_filter; /* -8 .. 15 */ - u16 noise_filter; /* 0 .. 15 */ - } drxj_cfg_atv_misc_t, *p_drxj_cfg_atv_misc_t; + u16 noise_filter; /* 0 .. 15 */}; /* - * drxj_cfg_oob_misc_t - */ + * struct drxj_cfg_oob_misc */ #define DRXJ_OOB_STATE_RESET 0x0 #define DRXJ_OOB_STATE_AGN_HUNT 0x1 #define DRXJ_OOB_STATE_DGN_HUNT 0x2 @@ -339,42 +313,40 @@ TYPEDEFS #define DRXJ_OOB_STATE_EQT_HUNT 0x30 #define DRXJ_OOB_STATE_SYNC 0x40 - typedef struct { - drxj_agc_status_t agc; - bool eq_lock; - bool sym_timing_lock; - bool phase_lock; - bool freq_lock; - bool dig_gain_lock; - bool ana_gain_lock; - u8 state; - } drxj_cfg_oob_misc_t, *p_drxj_cfg_oob_misc_t; +struct drxj_cfg_oob_misc { + struct drxj_agc_status agc; + bool eq_lock; + bool sym_timing_lock; + bool phase_lock; + bool freq_lock; + bool dig_gain_lock; + bool ana_gain_lock; + u8 state; + }; /* * Index of in array of coef */ - typedef enum { + enum drxj_cfg_oob_lo_power { DRXJ_OOB_LO_POW_MINUS0DB = 0, DRXJ_OOB_LO_POW_MINUS5DB, DRXJ_OOB_LO_POW_MINUS10DB, DRXJ_OOB_LO_POW_MINUS15DB, - DRXJ_OOB_LO_POW_MAX - } drxj_cfg_oob_lo_power_t, *p_drxj_cfg_oob_lo_power_t; + DRXJ_OOB_LO_POW_MAX}; /* * DRXJ_CFG_ATV_EQU_COEF */ - typedef struct { + struct drxj_cfg_atv_equ_coef { s16 coef0; /* -256 .. 255 */ s16 coef1; /* -256 .. 255 */ s16 coef2; /* -256 .. 255 */ - s16 coef3; /* -256 .. 255 */ - } drxj_cfg_atv_equ_coef_t, *p_drxj_cfg_atv_equ_coef_t; + s16 coef3; /* -256 .. 255 */}; /* * Index of in array of coef */ - typedef enum { + enum drxj_coef_array_index { DRXJ_COEF_IDX_MN = 0, DRXJ_COEF_IDX_FM, DRXJ_COEF_IDX_L, @@ -382,8 +354,7 @@ TYPEDEFS DRXJ_COEF_IDX_BG, DRXJ_COEF_IDX_DK, DRXJ_COEF_IDX_I, - DRXJ_COEF_IDX_MAX - } drxj_coef_array_index_t, *pdrxj_coef_array_index_t; + DRXJ_COEF_IDX_MAX}; /* * DRXJ_CFG_ATV_OUTPUT @@ -394,37 +365,34 @@ TYPEDEFS * Attenuation setting for SIF AGC. * */ - typedef enum { + enum drxjsif_attenuation { DRXJ_SIF_ATTENUATION_0DB, DRXJ_SIF_ATTENUATION_3DB, DRXJ_SIF_ATTENUATION_6DB, - DRXJ_SIF_ATTENUATION_9DB - } drxjsif_attenuation_t, *pdrxjsif_attenuation_t; + DRXJ_SIF_ATTENUATION_9DB}; /** -* /struct drxj_cfg_atv_output_t -* SIF attenuation setting. +* /struct struct drxj_cfg_atv_output * SIF attenuation setting. * */ - typedef struct { - bool enable_cvbs_output; /* true= enabled */ - bool enable_sif_output; /* true= enabled */ - drxjsif_attenuation_t sif_attenuation; - } drxj_cfg_atv_output_t, *p_drxj_cfg_atv_output_t; +struct drxj_cfg_atv_output { + bool enable_cvbs_output; /* true= enabled */ + bool enable_sif_output; /* true= enabled */ + enum drxjsif_attenuation sif_attenuation; +}; /* DRXJ_CFG_ATV_AGC_STATUS (get only) */ /* TODO : AFE interface not yet finished, subject to change */ - typedef struct { + struct drxj_cfg_atv_agc_status { u16 rf_agc_gain; /* 0 .. 877 uA */ u16 if_agc_gain; /* 0 .. 877 uA */ s16 video_agc_gain; /* -75 .. 1972 in 0.1 dB steps */ s16 audio_agc_gain; /* -4 .. 1020 in 0.1 dB steps */ u16 rf_agc_loop_gain; /* 0 .. 7 */ u16 if_agc_loop_gain; /* 0 .. 7 */ - u16 video_agc_loop_gain; /* 0 .. 7 */ - } drxj_cfg_atv_agc_status_t, *p_drxj_cfg_atv_agc_status_t; + u16 video_agc_loop_gain; /* 0 .. 7 */}; /*============================================================================*/ /*============================================================================*/ @@ -439,13 +407,12 @@ TYPEDEFS /*========================================*/ /** -* /struct drxj_data_t -* DRXJ specific attributes. +* /struct struct drxj_data * DRXJ specific attributes. * * Global data container for DRXJ specific data. * */ - typedef struct { + struct drxj_data { /* device capabilties (determined during drx_open()) */ bool has_lna; /**< true if LNA (aka PGA) present */ bool has_oob; /**< true if OOB supported */ @@ -511,22 +478,22 @@ TYPEDEFS u16 atv_top_noise_th; /**< shadow of ATV_TOP_NOISE_TH__A */ bool enable_cvbs_output; /**< flag CVBS ouput enable */ bool enable_sif_output; /**< flag SIF ouput enable */ - drxjsif_attenuation_t sif_attenuation; + enum drxjsif_attenuation sif_attenuation; /**< current SIF att setting */ /* Agc configuration for QAM and VSB */ - drxj_cfg_agc_t qam_rf_agc_cfg; /**< qam RF AGC config */ - drxj_cfg_agc_t qam_if_agc_cfg; /**< qam IF AGC config */ - drxj_cfg_agc_t vsb_rf_agc_cfg; /**< vsb RF AGC config */ - drxj_cfg_agc_t vsb_if_agc_cfg; /**< vsb IF AGC config */ + struct drxj_cfg_agc qam_rf_agc_cfg; /**< qam RF AGC config */ + struct drxj_cfg_agc qam_if_agc_cfg; /**< qam IF AGC config */ + struct drxj_cfg_agc vsb_rf_agc_cfg; /**< vsb RF AGC config */ + struct drxj_cfg_agc vsb_if_agc_cfg; /**< vsb IF AGC config */ /* PGA gain configuration for QAM and VSB */ u16 qam_pga_cfg; /**< qam PGA config */ u16 vsb_pga_cfg; /**< vsb PGA config */ /* Pre SAW configuration for QAM and VSB */ - drxj_cfg_pre_saw_t qam_pre_saw_cfg; + struct drxj_cfg_pre_saw qam_pre_saw_cfg; /**< qam pre SAW config */ - drxj_cfg_pre_saw_t vsb_pre_saw_cfg; + struct drxj_cfg_pre_saw vsb_pre_saw_cfg; /**< qam pre SAW config */ /* Version information */ @@ -546,16 +513,16 @@ TYPEDEFS u32 mpeg_ts_static_bitrate; /**< bitrate static MPEG output */ bool disable_te_ihandling; /**< MPEG TS TEI handling */ bool bit_reverse_mpeg_outout;/**< MPEG output bit order */ - drxj_mpeg_output_clock_rate_t mpeg_output_clock_rate; + enum drxj_mpeg_output_clock_rate mpeg_output_clock_rate; /**< MPEG output clock rate */ - drxj_mpeg_start_width_t mpeg_start_width; + enum drxj_mpeg_start_width mpeg_start_width; /**< MPEG Start width */ /* Pre SAW & Agc configuration for ATV */ - drxj_cfg_pre_saw_t atv_pre_saw_cfg; + struct drxj_cfg_pre_saw atv_pre_saw_cfg; /**< atv pre SAW config */ - drxj_cfg_agc_t atv_rf_agc_cfg; /**< atv RF AGC config */ - drxj_cfg_agc_t atv_if_agc_cfg; /**< atv IF AGC config */ + struct drxj_cfg_agc atv_rf_agc_cfg; /**< atv RF AGC config */ + struct drxj_cfg_agc atv_if_agc_cfg; /**< atv IF AGC config */ u16 atv_pga_cfg; /**< atv pga config */ u32 curr_symbol_rate; @@ -569,12 +536,10 @@ TYPEDEFS /* OOB pre-saw value */ u16 oob_pre_saw; - drxj_cfg_oob_lo_power_t oob_lo_pow; + enum drxj_cfg_oob_lo_power oob_lo_pow; struct drx_aud_data aud_data; - /**< audio storage */ - - } drxj_data_t, *pdrxj_data_t; + /**< audio storage */}; /*------------------------------------------------------------------------- Access MACROS @@ -591,7 +556,7 @@ Access MACROS */ #define DRXJ_ATTR_BTSC_DETECT(d) \ - (((pdrxj_data_t)(d)->my_ext_attr)->aud_data.btsc_detect) + (((struct drxj_data *)(d)->my_ext_attr)->aud_data.btsc_detect) /** * \brief Actual access macros @@ -733,7 +698,7 @@ Exported GLOBAL VARIABLES -------------------------------------------------------------------------*/ extern struct drx_access_func drx_dap_drxj_funct_g; extern struct drx_demod_func drxj_functions_g; - extern drxj_data_t drxj_data_g; + extern struct drxj_data drxj_data_g; extern struct i2c_device_addr drxj_default_addr_g; extern struct drx_common_attr drxj_default_comm_attr_g; extern struct drx_demod_instance drxj_default_demod_g; -- cgit v1.1 From adc0e25893a40520f7bfca4e1ac910b5643ef0f2 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Thu, 16 Jan 2014 15:56:51 -0300 Subject: [media] drx-j: a few more CodingStyle fixups Some whitespace cleanups. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drx_driver.c | 2 +- drivers/media/dvb-frontends/drx39xyj/drxj.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c index af894b9..1b55bb5 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c @@ -99,7 +99,7 @@ DEFINES /*=== MACROS =================================================================*/ /*============================================================================*/ -#define DRX_ISPOWERDOWNMODE(mode) (( mode == DRX_POWER_MODE_9) || \ +#define DRX_ISPOWERDOWNMODE(mode) ((mode == DRX_POWER_MODE_9) || \ (mode == DRX_POWER_MODE_10) || \ (mode == DRX_POWER_MODE_11) || \ (mode == DRX_POWER_MODE_12) || \ diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index 14a87ca..bb67ede 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -570,7 +570,7 @@ DEFINES /*=== STANDARD RELATED MACROS ================================================*/ /*============================================================================*/ -#define DRXJ_ISATVSTD(std) (( std == DRX_STANDARD_PAL_SECAM_BG) || \ +#define DRXJ_ISATVSTD(std) ((std == DRX_STANDARD_PAL_SECAM_BG) || \ (std == DRX_STANDARD_PAL_SECAM_DK) || \ (std == DRX_STANDARD_PAL_SECAM_I) || \ (std == DRX_STANDARD_PAL_SECAM_L) || \ @@ -578,7 +578,7 @@ DEFINES (std == DRX_STANDARD_NTSC) || \ (std == DRX_STANDARD_FM)) -#define DRXJ_ISQAMSTD(std) (( std == DRX_STANDARD_ITU_A) || \ +#define DRXJ_ISQAMSTD(std) ((std == DRX_STANDARD_ITU_A) || \ (std == DRX_STANDARD_ITU_B) || \ (std == DRX_STANDARD_ITU_C) || \ (std == DRX_STANDARD_ITU_D)) -- cgit v1.1 From b1d0a59649ea4a799502c858a4cb5d50c82d31f7 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Thu, 16 Jan 2014 16:34:03 -0300 Subject: [media] drx-j: Don't use buffer if an error occurs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit drivers/media/dvb-frontends/drx39xyj/drxj.c: In function ‘drxj_dap_scu_atomic_read_reg16’: drivers/media/dvb-frontends/drx39xyj/drxj.c:4170:9: warning: ‘*((void *)&buf+1)’ may be used uninitialized in this function [-Wmaybe-uninitialized] word = (u16) (buf[0] + (buf[1] << 8)); ^ drivers/media/dvb-frontends/drx39xyj/drxj.c:4170:9: warning: ‘buf’ may be used uninitialized in this function [-Wmaybe-uninitialized] drivers/media/dvb-frontends/drx39xyj/drxj.c: In function ‘drxj_dap_atomic_read_reg32.isra.59’: drivers/media/dvb-frontends/drx39xyj/drxj.c:2186:7: warning: ‘*((void *)&buf+3)’ may be used uninitialized in this function [-Wmaybe-uninitialized] word = (u32) buf[3]; ^ drivers/media/dvb-frontends/drx39xyj/drxj.c:2188:10: warning: ‘*((void *)&buf+2)’ may be used uninitialized in this function [-Wmaybe-uninitialized] word |= (u32) buf[2]; ^ drivers/media/dvb-frontends/drx39xyj/drxj.c:2190:10: warning: ‘*((void *)&buf+1)’ may be used uninitialized in this function [-Wmaybe-uninitialized] word |= (u32) buf[1]; ^ drivers/media/dvb-frontends/drx39xyj/drxj.c:2192:10: warning: ‘buf’ may be used uninitialized in this function [-Wmaybe-uninitialized] word |= (u32) buf[0]; ^ Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drxj.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index bb67ede..d51cea9 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -2183,6 +2183,9 @@ int drxj_dap_atomic_read_reg32(struct i2c_device_addr *dev_addr, rc = drxj_dap_atomic_read_write_block(dev_addr, addr, sizeof(*data), buf, true); + if (rc < 0) + return 0; + word = (u32) buf[3]; word <<= 8; word |= (u32) buf[2]; @@ -4166,6 +4169,8 @@ int drxj_dap_scu_atomic_read_reg16(struct i2c_device_addr *dev_addr, } rc = drxj_dap_scu_atomic_read_write_block(dev_addr, addr, 2, buf, true); + if (rc < 0) + return rc; word = (u16) (buf[0] + (buf[1] << 8)); -- cgit v1.1 From 068e94ea1700b1340ced1ea5dc7b3bdb41098613 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Thu, 16 Jan 2014 19:41:13 -0300 Subject: [media] drx-j: replace the ugly CHK_ERROR() macro Using return and goto inside macros is ugly and makes harder to understand the code and the labels. Remove those macros, and add a proper error debug message, when something bad happens. This was generated using the following coccinelle script: @@ @@ -DUMMY_READ(); +do { + u16 dummy; + RR16(demod->my_i2c_dev_addr, SCU_RAM_VERSION_HI__A, &dummy); +} while (0); @@ expression dev, addr, val; @@ -WR16(dev, addr, val) +CHK_ERROR(DRXJ_DAP.write_reg16func(dev, addr, val, 0)) @@ expression dev, addr, val; @@ -RR16(dev, addr, val) +CHK_ERROR(DRXJ_DAP.read_reg16func(dev, addr, val, 0)) @@ expression dev, addr, val; @@ -WR32(dev, addr, val) +CHK_ERROR(DRXJ_DAP.write_reg32func(dev, addr, val, 0)) @@ expression dev, addr, val; @@ -RR32(dev, addr, val) +CHK_ERROR(DRXJ_DAP.read_reg32func(dev, addr, val, 0)) @@ expression dev, addr, val, block; @@ -WRB(dev, addr, val, block) +CHK_ERROR(DRXJ_DAP.write_block_func(dev, addr, val, block, 0)) @@ expression dev, addr, val, block; @@ -RRB(dev, addr, val, block) +CHK_ERROR(DRXJ_DAP.read_block_func(dev, addr, val, block, 0)) @@ expression dev, addr, val; @@ -BCWR16(dev, addr, val) +CHK_ERROR(DRXJ_DAP.write_reg16func(dev, addr, val, DRXDAP_FASI_BROADCAST)) @@ expression dev, addr, val; @@ -ARR32(dev, addr, val) +CHK_ERROR(drxj_dap_atomic_read_reg32(dev, addr, val, 0)) @@ expression dev, addr, val; @@ -SARR16(dev, addr, val) +CHK_ERROR(drxj_dap_scu_atomic_read_reg16(dev, addr, val, 0)) @@ expression x; @@ -CHK_ERROR(x); +rc = x; +if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; +} Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drxj.c | 8488 +++++++++++++++++++++------ 1 file changed, 6758 insertions(+), 1730 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index d51cea9..13bb381 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -40,6 +40,8 @@ INCLUDE FILES ----------------------------------------------------------------------------*/ +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + #include "drxj.h" #include "drxj_map.h" @@ -478,66 +480,6 @@ DEFINES /*=== REGISTER ACCESS MACROS =================================================*/ /*============================================================================*/ -#ifdef DRXJDRIVER_DEBUG -#include -#define CHK_ERROR(s) \ - do { \ - if ((s) != DRX_STS_OK) \ - { \ - fprintf(stderr, \ - "ERROR[\n file : %s\n line : %d\n]\n", \ - __FILE__, __LINE__); \ - goto rw_error; }; \ - } \ - while (0 != 0) -#else -#define CHK_ERROR(s) \ - do { \ - if ((s) != DRX_STS_OK) { goto rw_error; } \ - } while (0 != 0) -#endif - -#define CHK_ZERO(s) \ - do { \ - if ((s) == 0) return DRX_STS_ERROR; \ - } while (0) - -#define DUMMY_READ() \ - do { \ - u16 dummy; \ - RR16(demod->my_i2c_dev_addr, SCU_RAM_VERSION_HI__A, &dummy); \ - } while (0) - -#define WR16(dev, addr, val) \ - CHK_ERROR(DRXJ_DAP.write_reg16func((dev), (addr), (val), 0)) - -#define RR16(dev, addr, val) \ - CHK_ERROR(DRXJ_DAP.read_reg16func((dev), (addr), (val), 0)) - -#define WR32(dev, addr, val) \ - CHK_ERROR(DRXJ_DAP.write_reg32func((dev), (addr), (val), 0)) - -#define RR32(dev, addr, val) \ - CHK_ERROR(DRXJ_DAP.read_reg32func((dev), (addr), (val), 0)) - -#define WRB(dev, addr, len, block) \ - CHK_ERROR(DRXJ_DAP.write_block_func((dev), (addr), (len), (block), 0)) - -#define RRB(dev, addr, len, block) \ - CHK_ERROR(DRXJ_DAP.read_block_func((dev), (addr), (len), (block), 0)) - -#define BCWR16(dev, addr, val) \ - CHK_ERROR(DRXJ_DAP.write_reg16func((dev), (addr), (val), DRXDAP_FASI_BROADCAST)) - -#define ARR32(dev, addr, val) \ - CHK_ERROR(drxj_dap_atomic_read_reg32((dev), (addr), (val), 0)) - -#define SARR16(dev, addr, val) \ - CHK_ERROR(drxj_dap_scu_atomic_read_reg16((dev), (addr), (val), 0)) - -#define SAWR16(dev, addr, val) \ - CHK_ERROR(drxj_dap_scu_atomic_write_reg16((dev), (addr), (val), 0)) - /** * This macro is used to create byte arrays for block writes. * Block writes speed up I2C traffic between host and demod. @@ -2100,7 +2042,7 @@ int drxj_dap_atomic_read_write_block(struct i2c_device_addr *dev_addr, u8 *data, bool read_flag) { drxj_hi_cmd_t hi_cmd; - + int rc; u16 word; u16 dummy = 0; u16 i = 0; @@ -2141,7 +2083,11 @@ int drxj_dap_atomic_read_write_block(struct i2c_device_addr *dev_addr, } } - CHK_ERROR(hi_command(dev_addr, &hi_cmd, &dummy)); + rc = hi_command(dev_addr, &hi_cmd, &dummy); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if (read_flag == true) { /* read data from buffer */ @@ -2227,6 +2173,7 @@ static int hi_cfg_command(const struct drx_demod_instance *demod) struct drxj_data *ext_attr = (struct drxj_data *) (NULL); drxj_hi_cmd_t hi_cmd; u16 result = 0; + int rc; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -2238,7 +2185,11 @@ static int hi_cfg_command(const struct drx_demod_instance *demod) hi_cmd.param5 = ext_attr->hi_cfg_ctrl; hi_cmd.param6 = ext_attr->hi_cfg_transmit; - CHK_ERROR(hi_command(demod->my_i2c_dev_addr, &hi_cmd, &result)); + rc = hi_command(demod->my_i2c_dev_addr, &hi_cmd, &result); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Reset power down flag (set one call only) */ ext_attr->hi_cfg_ctrl &= (~(SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ)); @@ -2266,20 +2217,45 @@ hi_command(struct i2c_device_addr *dev_addr, const pdrxj_hi_cmd_t cmd, u16 *resu u16 wait_cmd = 0; u16 nr_retries = 0; bool powerdown_cmd = false; + int rc; /* Write parameters */ switch (cmd->cmd) { case SIO_HI_RA_RAM_CMD_CONFIG: case SIO_HI_RA_RAM_CMD_ATOMIC_COPY: - WR16(dev_addr, SIO_HI_RA_RAM_PAR_6__A, cmd->param6); - WR16(dev_addr, SIO_HI_RA_RAM_PAR_5__A, cmd->param5); - WR16(dev_addr, SIO_HI_RA_RAM_PAR_4__A, cmd->param4); - WR16(dev_addr, SIO_HI_RA_RAM_PAR_3__A, cmd->param3); + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_HI_RA_RAM_PAR_6__A, cmd->param6, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_HI_RA_RAM_PAR_5__A, cmd->param5, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_HI_RA_RAM_PAR_4__A, cmd->param4, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_HI_RA_RAM_PAR_3__A, cmd->param3, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* fallthrough */ case SIO_HI_RA_RAM_CMD_BRDCTRL: - WR16(dev_addr, SIO_HI_RA_RAM_PAR_2__A, cmd->param2); - WR16(dev_addr, SIO_HI_RA_RAM_PAR_1__A, cmd->param1); + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_HI_RA_RAM_PAR_2__A, cmd->param2, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_HI_RA_RAM_PAR_1__A, cmd->param1, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* fallthrough */ case SIO_HI_RA_RAM_CMD_NULL: /* No parameters */ @@ -2291,7 +2267,11 @@ hi_command(struct i2c_device_addr *dev_addr, const pdrxj_hi_cmd_t cmd, u16 *resu } /* Write command */ - WR16(dev_addr, SIO_HI_RA_RAM_CMD__A, cmd->cmd); + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_HI_RA_RAM_CMD__A, cmd->cmd, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if ((cmd->cmd) == SIO_HI_RA_RAM_CMD_RESET) { /* Allow for HI to reset */ @@ -2311,11 +2291,19 @@ hi_command(struct i2c_device_addr *dev_addr, const pdrxj_hi_cmd_t cmd, u16 *resu goto rw_error; }; - RR16(dev_addr, SIO_HI_RA_RAM_CMD__A, &wait_cmd); + rc = DRXJ_DAP.read_reg16func(dev_addr, SIO_HI_RA_RAM_CMD__A, &wait_cmd, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } while (wait_cmd != 0); /* Read result */ - RR16(dev_addr, SIO_HI_RA_RAM_RES__A, result); + rc = DRXJ_DAP.read_reg16func(dev_addr, SIO_HI_RA_RAM_RES__A, result, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } /* if ( powerdown_cmd == true ) */ @@ -2342,13 +2330,18 @@ static int init_hi(const struct drx_demod_instance *demod) struct drxj_data *ext_attr = (struct drxj_data *) (NULL); struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL); struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); + int rc; ext_attr = (struct drxj_data *) demod->my_ext_attr; common_attr = (struct drx_common_attr *) demod->my_common_attr; dev_addr = demod->my_i2c_dev_addr; /* PATCH for bug 5003, HI ucode v3.1.0 */ - WR16(dev_addr, 0x4301D7, 0x801); + rc = DRXJ_DAP.write_reg16func(dev_addr, 0x4301D7, 0x801, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Timing div, 250ns/Psys */ /* Timing div, = ( delay (nano seconds) * sysclk (kHz) )/ 1000 */ @@ -2380,7 +2373,11 @@ static int init_hi(const struct drx_demod_instance *demod) /* transit mode time out delay and watch dog divider */ ext_attr->hi_cfg_transmit = SIO_HI_RA_RAM_PAR_6__PRE; - CHK_ERROR(hi_cfg_command(demod)); + rc = hi_cfg_command(demod); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } return (DRX_STS_OK); @@ -2422,14 +2419,27 @@ static int get_device_capabilities(struct drx_demod_instance *demod) u16 sio_pdr_ohw_cfg = 0; u32 sio_top_jtagid_lo = 0; u16 bid = 0; + int rc; common_attr = (struct drx_common_attr *) demod->my_common_attr; ext_attr = (struct drxj_data *) demod->my_ext_attr; dev_addr = demod->my_i2c_dev_addr; - WR16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); - RR16(dev_addr, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg); - WR16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE); + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.read_reg16func(dev_addr, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } switch ((sio_pdr_ohw_cfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) { case 0: @@ -2455,15 +2465,31 @@ static int get_device_capabilities(struct drx_demod_instance *demod) Determine device capabilities Based on pinning v47 */ - RR32(dev_addr, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo); + rc = DRXJ_DAP.read_reg32func(dev_addr, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } ext_attr->mfx = (u8) ((sio_top_jtagid_lo >> 29) & 0xF); switch ((sio_top_jtagid_lo >> 12) & 0xFF) { case 0x31: - WR16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); - RR16(dev_addr, SIO_PDR_UIO_IN_HI__A, &bid); + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.read_reg16func(dev_addr, SIO_PDR_UIO_IN_HI__A, &bid, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } bid = (bid >> 10) & 0xf; - WR16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE); + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } ext_attr->has_lna = true; ext_attr->has_ntsc = false; @@ -2600,9 +2626,11 @@ static int power_up_device(struct drx_demod_instance *demod) wake_up_addr.i2c_addr = DRXJ_WAKE_UP_KEY; wake_up_addr.i2c_dev_id = dev_addr->i2c_dev_id; wake_up_addr.user_data = dev_addr->user_data; - /* CHK_ERROR macro not used, I2C access may fail in this case: no ack - dummy write must be used to wake uop device, dummy read must be used to - reset HI state machine (avoiding actual writes) */ + /* + * I2C access may fail in this case: no ack + * dummy write must be used to wake uop device, dummy read must be used to + * reset HI state machine (avoiding actual writes) + */ do { data = 0; drxbsp_i2c_write_read(&wake_up_addr, 1, &data, @@ -2644,6 +2672,7 @@ ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); struct drxj_data *ext_attr = (struct drxj_data *) (NULL); struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL); + int rc; u16 fec_oc_reg_mode = 0; u16 fec_oc_reg_ipr_mode = 0; u16 fec_oc_reg_ipr_invert = 0; @@ -2657,6 +2686,7 @@ ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M | FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M | FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M; + /* check arguments */ if ((demod == NULL) || (cfg_data == NULL)) { return (DRX_STS_INVALID_ARG); @@ -2693,19 +2723,55 @@ ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o return (DRX_STS_OK); } - WR16(dev_addr, FEC_OC_OCR_INVERT__A, 0); + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_OCR_INVERT__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } switch (ext_attr->standard) { case DRX_STANDARD_8VSB: - WR16(dev_addr, FEC_OC_FCT_USAGE__A, 7); /* 2048 bytes fifo ram */ - WR16(dev_addr, FEC_OC_TMD_CTL_UPD_RATE__A, 10); - WR16(dev_addr, FEC_OC_TMD_INT_UPD_RATE__A, 10); - WR16(dev_addr, FEC_OC_AVR_PARM_A__A, 5); - WR16(dev_addr, FEC_OC_AVR_PARM_B__A, 7); - WR16(dev_addr, FEC_OC_RCN_GAIN__A, 10); + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_FCT_USAGE__A, 7, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* 2048 bytes fifo ram */ + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_TMD_CTL_UPD_RATE__A, 10, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_TMD_INT_UPD_RATE__A, 10, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_AVR_PARM_A__A, 5, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_AVR_PARM_B__A, 7, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_RCN_GAIN__A, 10, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Low Water Mark for synchronization */ - WR16(dev_addr, FEC_OC_SNC_LWM__A, 3); + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_SNC_LWM__A, 3, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* High Water Mark for synchronization */ - WR16(dev_addr, FEC_OC_SNC_HWM__A, 5); + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_SNC_HWM__A, 5, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } break; case DRX_STANDARD_ITU_A: case DRX_STANDARD_ITU_C: @@ -2734,31 +2800,70 @@ ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o (ext_attr->curr_symbol_rate / 8) * nr_bits * 188; /* pass through b/c Annex A/c need following settings */ case DRX_STANDARD_ITU_B: - WR16(dev_addr, FEC_OC_FCT_USAGE__A, - FEC_OC_FCT_USAGE__PRE); - WR16(dev_addr, FEC_OC_TMD_CTL_UPD_RATE__A, - FEC_OC_TMD_CTL_UPD_RATE__PRE); - WR16(dev_addr, FEC_OC_TMD_INT_UPD_RATE__A, 5); - WR16(dev_addr, FEC_OC_AVR_PARM_A__A, - FEC_OC_AVR_PARM_A__PRE); - WR16(dev_addr, FEC_OC_AVR_PARM_B__A, - FEC_OC_AVR_PARM_B__PRE); + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_FCT_USAGE__A, FEC_OC_FCT_USAGE__PRE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_TMD_CTL_UPD_RATE__A, FEC_OC_TMD_CTL_UPD_RATE__PRE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_TMD_INT_UPD_RATE__A, 5, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_AVR_PARM_A__A, FEC_OC_AVR_PARM_A__PRE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_AVR_PARM_B__A, FEC_OC_AVR_PARM_B__PRE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if (cfg_data->static_clk == true) { - WR16(dev_addr, FEC_OC_RCN_GAIN__A, 0xD); + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_RCN_GAIN__A, 0xD, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } else { - WR16(dev_addr, FEC_OC_RCN_GAIN__A, - FEC_OC_RCN_GAIN__PRE); + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_RCN_GAIN__A, FEC_OC_RCN_GAIN__PRE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_SNC_LWM__A, 2, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_SNC_HWM__A, 12, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; } - WR16(dev_addr, FEC_OC_SNC_LWM__A, 2); - WR16(dev_addr, FEC_OC_SNC_HWM__A, 12); break; default: break; } /* swtich (standard) */ /* Check insertion of the Reed-Solomon parity bytes */ - RR16(dev_addr, FEC_OC_MODE__A, &fec_oc_reg_mode); - RR16(dev_addr, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode); + rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_OC_MODE__A, &fec_oc_reg_mode, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if (cfg_data->insert_rs_byte == true) { /* enable parity symbol forward */ fec_oc_reg_mode |= FEC_OC_MODE_PARITY__M; @@ -2918,97 +3023,287 @@ ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o dto_rate = frac28(bit_rate, common_attr->sys_clock_freq * 1000); dto_rate >>= 3; - WR16(dev_addr, FEC_OC_DTO_RATE_HI__A, - (u16) ((dto_rate >> 16) & FEC_OC_DTO_RATE_HI__M)); - WR16(dev_addr, FEC_OC_DTO_RATE_LO__A, - (u16) (dto_rate & FEC_OC_DTO_RATE_LO_RATE_LO__M)); - WR16(dev_addr, FEC_OC_DTO_MODE__A, - FEC_OC_DTO_MODE_DYNAMIC__M | - FEC_OC_DTO_MODE_OFFSET_ENABLE__M); - WR16(dev_addr, FEC_OC_FCT_MODE__A, - FEC_OC_FCT_MODE_RAT_ENA__M | - FEC_OC_FCT_MODE_VIRT_ENA__M); - WR16(dev_addr, FEC_OC_DTO_BURST_LEN__A, - fec_oc_dto_burst_len); + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_DTO_RATE_HI__A, (u16)((dto_rate >> 16) & FEC_OC_DTO_RATE_HI__M), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_DTO_RATE_LO__A, (u16)(dto_rate & FEC_OC_DTO_RATE_LO_RATE_LO__M), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M | FEC_OC_DTO_MODE_OFFSET_ENABLE__M, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_FCT_MODE__A, FEC_OC_FCT_MODE_RAT_ENA__M | FEC_OC_FCT_MODE_VIRT_ENA__M, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_DTO_BURST_LEN__A, fec_oc_dto_burst_len, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if (ext_attr->mpeg_output_clock_rate != DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO) fec_oc_dto_period = ext_attr->mpeg_output_clock_rate - 1; - WR16(dev_addr, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period); + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } else { /* Dynamic mode */ - WR16(dev_addr, FEC_OC_DTO_MODE__A, - FEC_OC_DTO_MODE_DYNAMIC__M); - WR16(dev_addr, FEC_OC_FCT_MODE__A, 0); + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_FCT_MODE__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } - WR32(dev_addr, FEC_OC_RCN_CTL_RATE_LO__A, rcn_rate); + rc = DRXJ_DAP.write_reg32func(dev_addr, FEC_OC_RCN_CTL_RATE_LO__A, rcn_rate, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Write appropriate registers with requested configuration */ - WR16(dev_addr, FEC_OC_MODE__A, fec_oc_reg_mode); - WR16(dev_addr, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode); - WR16(dev_addr, FEC_OC_IPR_INVERT__A, fec_oc_reg_ipr_invert); + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_MODE__A, fec_oc_reg_mode, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_IPR_INVERT__A, fec_oc_reg_ipr_invert, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* enabling for both parallel and serial now */ /* Write magic word to enable pdr reg write */ - WR16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA); + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Set MPEG TS pads to outputmode */ - WR16(dev_addr, SIO_PDR_MSTRT_CFG__A, 0x0013); - WR16(dev_addr, SIO_PDR_MERR_CFG__A, 0x0013); - WR16(dev_addr, SIO_PDR_MCLK_CFG__A, - MPEG_OUTPUT_CLK_DRIVE_STRENGTH << SIO_PDR_MCLK_CFG_DRIVE__B - | 0x03 << SIO_PDR_MCLK_CFG_MODE__B); - WR16(dev_addr, SIO_PDR_MVAL_CFG__A, 0x0013); + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MSTRT_CFG__A, 0x0013, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MERR_CFG__A, 0x0013, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MCLK_CFG__A, MPEG_OUTPUT_CLK_DRIVE_STRENGTH << SIO_PDR_MCLK_CFG_DRIVE__B | 0x03 << SIO_PDR_MCLK_CFG_MODE__B, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MVAL_CFG__A, 0x0013, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } sio_pdr_md_cfg = MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH << SIO_PDR_MD0_CFG_DRIVE__B | 0x03 << SIO_PDR_MD0_CFG_MODE__B; - WR16(dev_addr, SIO_PDR_MD0_CFG__A, sio_pdr_md_cfg); + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD0_CFG__A, sio_pdr_md_cfg, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if (cfg_data->enable_parallel == true) { /* MPEG data output is paralel -> set MD1 to MD7 to output mode */ sio_pdr_md_cfg = MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH << SIO_PDR_MD0_CFG_DRIVE__B | 0x03 << SIO_PDR_MD0_CFG_MODE__B; - WR16(dev_addr, SIO_PDR_MD0_CFG__A, sio_pdr_md_cfg); - WR16(dev_addr, SIO_PDR_MD1_CFG__A, sio_pdr_md_cfg); - WR16(dev_addr, SIO_PDR_MD2_CFG__A, sio_pdr_md_cfg); - WR16(dev_addr, SIO_PDR_MD3_CFG__A, sio_pdr_md_cfg); - WR16(dev_addr, SIO_PDR_MD4_CFG__A, sio_pdr_md_cfg); - WR16(dev_addr, SIO_PDR_MD5_CFG__A, sio_pdr_md_cfg); - WR16(dev_addr, SIO_PDR_MD6_CFG__A, sio_pdr_md_cfg); - WR16(dev_addr, SIO_PDR_MD7_CFG__A, sio_pdr_md_cfg); + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD0_CFG__A, sio_pdr_md_cfg, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD1_CFG__A, sio_pdr_md_cfg, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD2_CFG__A, sio_pdr_md_cfg, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD3_CFG__A, sio_pdr_md_cfg, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD4_CFG__A, sio_pdr_md_cfg, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD5_CFG__A, sio_pdr_md_cfg, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD6_CFG__A, sio_pdr_md_cfg, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD7_CFG__A, sio_pdr_md_cfg, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } else { /* MPEG data output is serial -> set MD1 to MD7 to tri-state */ - WR16(dev_addr, SIO_PDR_MD1_CFG__A, 0x0000); - WR16(dev_addr, SIO_PDR_MD2_CFG__A, 0x0000); - WR16(dev_addr, SIO_PDR_MD3_CFG__A, 0x0000); - WR16(dev_addr, SIO_PDR_MD4_CFG__A, 0x0000); - WR16(dev_addr, SIO_PDR_MD5_CFG__A, 0x0000); - WR16(dev_addr, SIO_PDR_MD6_CFG__A, 0x0000); - WR16(dev_addr, SIO_PDR_MD7_CFG__A, 0x0000); + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD1_CFG__A, 0x0000, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD2_CFG__A, 0x0000, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD3_CFG__A, 0x0000, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD4_CFG__A, 0x0000, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD5_CFG__A, 0x0000, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD6_CFG__A, 0x0000, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD7_CFG__A, 0x0000, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } /* Enable Monitor Bus output over MPEG pads and ctl input */ - WR16(dev_addr, SIO_PDR_MON_CFG__A, 0x0000); + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MON_CFG__A, 0x0000, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Write nomagic word to enable pdr reg write */ - WR16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000); + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } else { /* Write magic word to enable pdr reg write */ - WR16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA); + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Set MPEG TS pads to inputmode */ - WR16(dev_addr, SIO_PDR_MSTRT_CFG__A, 0x0000); - WR16(dev_addr, SIO_PDR_MERR_CFG__A, 0x0000); - WR16(dev_addr, SIO_PDR_MCLK_CFG__A, 0x0000); - WR16(dev_addr, SIO_PDR_MVAL_CFG__A, 0x0000); - WR16(dev_addr, SIO_PDR_MD0_CFG__A, 0x0000); - WR16(dev_addr, SIO_PDR_MD1_CFG__A, 0x0000); - WR16(dev_addr, SIO_PDR_MD2_CFG__A, 0x0000); - WR16(dev_addr, SIO_PDR_MD3_CFG__A, 0x0000); - WR16(dev_addr, SIO_PDR_MD4_CFG__A, 0x0000); - WR16(dev_addr, SIO_PDR_MD5_CFG__A, 0x0000); - WR16(dev_addr, SIO_PDR_MD6_CFG__A, 0x0000); - WR16(dev_addr, SIO_PDR_MD7_CFG__A, 0x0000); + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MSTRT_CFG__A, 0x0000, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MERR_CFG__A, 0x0000, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MCLK_CFG__A, 0x0000, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MVAL_CFG__A, 0x0000, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD0_CFG__A, 0x0000, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD1_CFG__A, 0x0000, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD2_CFG__A, 0x0000, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD3_CFG__A, 0x0000, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD4_CFG__A, 0x0000, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD5_CFG__A, 0x0000, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD6_CFG__A, 0x0000, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD7_CFG__A, 0x0000, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Enable Monitor Bus output over MPEG pads and ctl input */ - WR16(dev_addr, SIO_PDR_MON_CFG__A, 0x0000); + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MON_CFG__A, 0x0000, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Write nomagic word to enable pdr reg write */ - WR16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000); + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } /* save values for restore after re-acquire */ @@ -3046,6 +3341,7 @@ ctrl_get_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL); enum drx_lock_status lock_status = DRX_NOT_LOCKED; + int rc; u32 rate_reg = 0; u32 data64hi = 0; u32 data64lo = 0; @@ -3067,9 +3363,17 @@ ctrl_get_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o cfg_data->static_clk = common_attr->mpeg_cfg.static_clk; cfg_data->bitrate = 0; - CHK_ERROR(ctrl_lock_status(demod, &lock_status)); + rc = ctrl_lock_status(demod, &lock_status); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if ((lock_status == DRX_LOCKED)) { - RR32(dev_addr, FEC_OC_RCN_DYN_RATE_LO__A, &rate_reg); + rc = DRXJ_DAP.read_reg32func(dev_addr, FEC_OC_RCN_DYN_RATE_LO__A, &rate_reg, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Frcn_rate = rate_reg * Fsys / 2 ^ 25 */ mult32(rate_reg, common_attr->sys_clock_freq * 1000, &data64hi, &data64lo); @@ -3102,6 +3406,7 @@ static int set_mpegtei_handling(struct drx_demod_instance *demod) { struct drxj_data *ext_attr = (struct drxj_data *) (NULL); struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); + int rc; u16 fec_oc_dpr_mode = 0; u16 fec_oc_snc_mode = 0; u16 fec_oc_ems_mode = 0; @@ -3109,9 +3414,21 @@ static int set_mpegtei_handling(struct drx_demod_instance *demod) dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; - RR16(dev_addr, FEC_OC_DPR_MODE__A, &fec_oc_dpr_mode); - RR16(dev_addr, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode); - RR16(dev_addr, FEC_OC_EMS_MODE__A, &fec_oc_ems_mode); + rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_OC_DPR_MODE__A, &fec_oc_dpr_mode, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_OC_EMS_MODE__A, &fec_oc_ems_mode, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* reset to default, allow TEI bit to be changed */ fec_oc_dpr_mode &= (~FEC_OC_DPR_MODE_ERR_DISABLE__M); @@ -3127,9 +3444,21 @@ static int set_mpegtei_handling(struct drx_demod_instance *demod) fec_oc_ems_mode |= ((0x01) << (FEC_OC_EMS_MODE_MODE__B)); } - WR16(dev_addr, FEC_OC_DPR_MODE__A, fec_oc_dpr_mode); - WR16(dev_addr, FEC_OC_SNC_MODE__A, fec_oc_snc_mode); - WR16(dev_addr, FEC_OC_EMS_MODE__A, fec_oc_ems_mode); + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_DPR_MODE__A, fec_oc_dpr_mode, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_SNC_MODE__A, fec_oc_snc_mode, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_EMS_MODE__A, fec_oc_ems_mode, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } return (DRX_STS_OK); rw_error: @@ -3150,12 +3479,17 @@ static int bit_reverse_mpeg_output(struct drx_demod_instance *demod) { struct drxj_data *ext_attr = (struct drxj_data *) (NULL); struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); + int rc; u16 fec_oc_ipr_mode = 0; dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; - RR16(dev_addr, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode); + rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* reset to default (normal bit order) */ fec_oc_ipr_mode &= (~FEC_OC_IPR_MODE_REVERSE_ORDER__M); @@ -3165,7 +3499,11 @@ static int bit_reverse_mpeg_output(struct drx_demod_instance *demod) fec_oc_ipr_mode |= FEC_OC_IPR_MODE_REVERSE_ORDER__M; } - WR16(dev_addr, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode); + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } return (DRX_STS_OK); rw_error: @@ -3186,13 +3524,17 @@ static int set_mpeg_output_clock_rate(struct drx_demod_instance *demod) { struct drxj_data *ext_attr = (struct drxj_data *) (NULL); struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); + int rc; dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; if (ext_attr->mpeg_output_clock_rate != DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO) { - WR16(dev_addr, FEC_OC_DTO_PERIOD__A, - ext_attr->mpeg_output_clock_rate - 1); + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_DTO_PERIOD__A, ext_attr->mpeg_output_clock_rate - 1, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } return (DRX_STS_OK); @@ -3214,8 +3556,9 @@ static int set_mpeg_start_width(struct drx_demod_instance *demod) { struct drxj_data *ext_attr = (struct drxj_data *) (NULL); struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); - u16 fec_oc_comm_mb = 0; struct drx_common_attr *common_attr = (struct drx_common_attr *) NULL; + int rc; + u16 fec_oc_comm_mb = 0; dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -3223,12 +3566,20 @@ static int set_mpeg_start_width(struct drx_demod_instance *demod) if ((common_attr->mpeg_cfg.static_clk == true) && (common_attr->mpeg_cfg.enable_parallel == false)) { - RR16(dev_addr, FEC_OC_COMM_MB__A, &fec_oc_comm_mb); + rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_OC_COMM_MB__A, &fec_oc_comm_mb, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } fec_oc_comm_mb &= ~FEC_OC_COMM_MB_CTL_ON; if (ext_attr->mpeg_start_width == DRXJ_MPEG_START_WIDTH_8CLKCYC) { fec_oc_comm_mb |= FEC_OC_COMM_MB_CTL_ON; } - WR16(dev_addr, FEC_OC_COMM_MB__A, fec_oc_comm_mb); + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_COMM_MB__A, fec_oc_comm_mb, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } return (DRX_STS_OK); @@ -3253,6 +3604,7 @@ ctrl_set_cfg_mpeg_output_misc(struct drx_demod_instance *demod, struct drxj_cfg_mpeg_output_misc *cfg_data) { struct drxj_data *ext_attr = (struct drxj_data *) (NULL); + int rc; if (cfg_data == NULL) { return (DRX_STS_INVALID_ARG); @@ -3274,10 +3626,26 @@ ctrl_set_cfg_mpeg_output_misc(struct drx_demod_instance *demod, ext_attr->mpeg_output_clock_rate = cfg_data->mpeg_output_clock_rate; ext_attr->mpeg_start_width = cfg_data->mpeg_start_width; /* Don't care what the active standard is, activate setting immediatly */ - CHK_ERROR(set_mpegtei_handling(demod)); - CHK_ERROR(bit_reverse_mpeg_output(demod)); - CHK_ERROR(set_mpeg_output_clock_rate(demod)); - CHK_ERROR(set_mpeg_start_width(demod)); + rc = set_mpegtei_handling(demod); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = bit_reverse_mpeg_output(demod); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = set_mpeg_output_clock_rate(demod); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = set_mpeg_start_width(demod); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } return (DRX_STS_OK); rw_error: @@ -3303,6 +3671,7 @@ ctrl_get_cfg_mpeg_output_misc(struct drx_demod_instance *demod, struct drxj_cfg_mpeg_output_misc *cfg_data) { struct drxj_data *ext_attr = (struct drxj_data *) (NULL); + int rc; u16 data = 0; if (cfg_data == NULL) { @@ -3316,7 +3685,11 @@ ctrl_get_cfg_mpeg_output_misc(struct drx_demod_instance *demod, if (ext_attr->mpeg_output_clock_rate != DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO) { cfg_data->mpeg_output_clock_rate = ext_attr->mpeg_output_clock_rate; } else { - RR16(demod->my_i2c_dev_addr, FEC_OC_DTO_PERIOD__A, &data); + rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, FEC_OC_DTO_PERIOD__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } cfg_data->mpeg_output_clock_rate = (enum drxj_mpeg_output_clock_rate) (data + 1); } @@ -3343,14 +3716,27 @@ rw_error: static int ctrl_get_cfg_hw_cfg(struct drx_demod_instance *demod, struct drxj_cfg_hw_cfg *cfg_data) { + int rc; u16 data = 0; if (cfg_data == NULL) return (DRX_STS_INVALID_ARG); - WR16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA); - RR16(demod->my_i2c_dev_addr, SIO_PDR_OHW_CFG__A, &data); - WR16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000); + rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SIO_PDR_OHW_CFG__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } cfg_data->i2c_speed = (enum drxji2c_speed) ((data >> 6) & 0x1); cfg_data->xtal_freq = (enum drxj_xtal_freq) (data & 0x3); @@ -3377,6 +3763,7 @@ rw_error: static int ctrl_set_uio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg *uio_cfg) { struct drxj_data *ext_attr = (struct drxj_data *) (NULL); + int rc; if ((uio_cfg == NULL) || (demod == NULL)) { return DRX_STS_INVALID_ARG; @@ -3384,7 +3771,11 @@ static int ctrl_set_uio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg ext_attr = (struct drxj_data *) demod->my_ext_attr; /* Write magic word to enable pdr reg write */ - WR16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); + rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } switch (uio_cfg->uio) { /*====================================================================*/ case DRX_UIO1: @@ -3400,7 +3791,11 @@ static int ctrl_set_uio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg case DRX_UIO_MODE_DISABLE: ext_attr->uio_sma_tx_mode = uio_cfg->mode; /* pad configuration register is set 0 - input mode */ - WR16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0); + rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } break; default: return DRX_STS_INVALID_ARG; @@ -3419,7 +3814,11 @@ static int ctrl_set_uio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg case DRX_UIO_MODE_DISABLE: ext_attr->uio_sma_rx_mode = uio_cfg->mode; /* pad configuration register is set 0 - input mode */ - WR16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, 0); + rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } break; default: return DRX_STS_INVALID_ARG; @@ -3439,7 +3838,11 @@ static int ctrl_set_uio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg case DRX_UIO_MODE_DISABLE: ext_attr->uio_gpio_mode = uio_cfg->mode; /* pad configuration register is set 0 - input mode */ - WR16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, 0); + rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } break; default: return DRX_STS_INVALID_ARG; @@ -3457,7 +3860,11 @@ static int ctrl_set_uio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg break; case DRX_UIO_MODE_DISABLE: /* pad configuration register is set 0 - input mode */ - WR16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, 0); + rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } ext_attr->uio_irqn_mode = uio_cfg->mode; break; case DRX_UIO_MODE_FIRMWARE0: /* falltrough */ @@ -3472,7 +3879,11 @@ static int ctrl_set_uio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg } /* switch ( uio_cfg->uio ) */ /* Write magic word to disable pdr reg write */ - WR16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000); + rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } return (DRX_STS_OK); rw_error: @@ -3534,6 +3945,7 @@ static int ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data) { struct drxj_data *ext_attr = (struct drxj_data *) (NULL); + int rc; u16 pin_cfg_value = 0; u16 value = 0; @@ -3544,7 +3956,11 @@ ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data) ext_attr = (struct drxj_data *) demod->my_ext_attr; /* Write magic word to enable pdr reg write */ - WR16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); + rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } switch (uio_data->uio) { /*====================================================================*/ case DRX_UIO1: @@ -3562,17 +3978,29 @@ ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data) /* io_pad_cfg_drive is set to power 2 (23 mA) */ /* write to io pad configuration register - output mode */ - WR16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, pin_cfg_value); + rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, pin_cfg_value, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* use corresponding bit in io data output registar */ - RR16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value); + rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if (uio_data->value == false) { value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */ } else { value |= 0x8000; /* write one to 15th bit - 1st UIO */ } /* write back to io data output register */ - WR16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value); + rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } break; /*======================================================================*/ case DRX_UIO2: @@ -3589,17 +4017,29 @@ ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data) /* io_pad_cfg_drive is set to power 2 (23 mA) */ /* write to io pad configuration register - output mode */ - WR16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, pin_cfg_value); + rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, pin_cfg_value, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* use corresponding bit in io data output registar */ - RR16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value); + rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if (uio_data->value == false) { value &= 0xBFFF; /* write zero to 14th bit - 2nd UIO */ } else { value |= 0x4000; /* write one to 14th bit - 2nd UIO */ } /* write back to io data output register */ - WR16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value); + rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } break; /*====================================================================*/ case DRX_UIO3: @@ -3616,17 +4056,29 @@ ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data) /* io_pad_cfg_drive is set to power 2 (23 mA) */ /* write to io pad configuration register - output mode */ - WR16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, pin_cfg_value); + rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, pin_cfg_value, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* use corresponding bit in io data output registar */ - RR16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, &value); + rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, &value, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if (uio_data->value == false) { value &= 0xFFFB; /* write zero to 2nd bit - 3rd UIO */ } else { value |= 0x0004; /* write one to 2nd bit - 3rd UIO */ } /* write back to io data output register */ - WR16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, value); + rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, value, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } break; /*=====================================================================*/ case DRX_UIO4: @@ -3644,17 +4096,29 @@ ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data) /* io_pad_cfg_drive is set to power 2 (23 mA) */ /* write to io pad configuration register - output mode */ - WR16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, pin_cfg_value); + rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, pin_cfg_value, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* use corresponding bit in io data output registar */ - RR16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value); + rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if (uio_data->value == false) { value &= 0xEFFF; /* write zero to 12th bit - 4th UIO */ } else { value |= 0x1000; /* write one to 12th bit - 4th UIO */ } /* write back to io data output register */ - WR16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value); + rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } break; /*=====================================================================*/ default: @@ -3662,7 +4126,11 @@ ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data) } /* switch ( uio_data->uio ) */ /* Write magic word to disable pdr reg write */ - WR16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000); + rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } return (DRX_STS_OK); rw_error: @@ -3679,6 +4147,7 @@ rw_error: static int ctrl_uio_read(struct drx_demod_instance *demod, struct drxuio_data *uio_data) { struct drxj_data *ext_attr = (struct drxj_data *) (NULL); + int rc; u16 pin_cfg_value = 0; u16 value = 0; @@ -3689,7 +4158,11 @@ static int ctrl_uio_read(struct drx_demod_instance *demod, struct drxuio_data *u ext_attr = (struct drxj_data *) demod->my_ext_attr; /* Write magic word to enable pdr reg write */ - WR16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); + rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } switch (uio_data->uio) { /*====================================================================*/ case DRX_UIO1: @@ -3707,9 +4180,17 @@ static int ctrl_uio_read(struct drx_demod_instance *demod, struct drxuio_data *u /* io_pad_cfg_drive is set to power 2 (23 mA) */ /* write to io pad configuration register - input mode */ - WR16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, pin_cfg_value); + rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, pin_cfg_value, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } - RR16(demod->my_i2c_dev_addr, SIO_PDR_UIO_IN_LO__A, &value); + rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SIO_PDR_UIO_IN_LO__A, &value, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if ((value & 0x8000) != 0) { /* check 15th bit - 1st UIO */ uio_data->value = true; } else { @@ -3732,9 +4213,17 @@ static int ctrl_uio_read(struct drx_demod_instance *demod, struct drxuio_data *u /* io_pad_cfg_drive is set to power 2 (23 mA) */ /* write to io pad configuration register - input mode */ - WR16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, pin_cfg_value); + rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, pin_cfg_value, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } - RR16(demod->my_i2c_dev_addr, SIO_PDR_UIO_IN_LO__A, &value); + rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SIO_PDR_UIO_IN_LO__A, &value, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if ((value & 0x4000) != 0) { /* check 14th bit - 2nd UIO */ uio_data->value = true; @@ -3758,10 +4247,18 @@ static int ctrl_uio_read(struct drx_demod_instance *demod, struct drxuio_data *u /* io_pad_cfg_drive is set to power 2 (23 mA) */ /* write to io pad configuration register - input mode */ - WR16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, pin_cfg_value); + rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, pin_cfg_value, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* read io input data registar */ - RR16(demod->my_i2c_dev_addr, SIO_PDR_UIO_IN_HI__A, &value); + rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SIO_PDR_UIO_IN_HI__A, &value, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if ((value & 0x0004) != 0) { /* check 2nd bit - 3rd UIO */ uio_data->value = true; } else { @@ -3784,10 +4281,18 @@ static int ctrl_uio_read(struct drx_demod_instance *demod, struct drxuio_data *u /* io_pad_cfg_drive is set to power 2 (23 mA) */ /* write to io pad configuration register - input mode */ - WR16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, pin_cfg_value); + rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, pin_cfg_value, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* read io input data registar */ - RR16(demod->my_i2c_dev_addr, SIO_PDR_UIO_IN_LO__A, &value); + rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SIO_PDR_UIO_IN_LO__A, &value, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if ((value & 0x1000) != 0) { /* check 12th bit - 4th UIO */ uio_data->value = true; } else { @@ -3800,7 +4305,11 @@ static int ctrl_uio_read(struct drx_demod_instance *demod, struct drxuio_data *u } /* switch ( uio_data->uio ) */ /* Write magic word to disable pdr reg write */ - WR16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000); + rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } return (DRX_STS_OK); rw_error: @@ -3860,34 +4369,67 @@ ctrl_i2c_bridge(struct drx_demod_instance *demod, bool *bridge_closed) */ static int smart_ant_init(struct drx_demod_instance *demod) { - u16 data = 0; struct drxj_data *ext_attr = NULL; struct i2c_device_addr *dev_addr = NULL; struct drxuio_cfg uio_cfg = { DRX_UIO1, DRX_UIO_MODE_FIRMWARE_SMA }; + int rc; + u16 data = 0; dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; /* Write magic word to enable pdr reg write */ - WR16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); + rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* init smart antenna */ - RR16(dev_addr, SIO_SA_TX_COMMAND__A, &data); - if (ext_attr->smart_ant_inverted) - WR16(dev_addr, SIO_SA_TX_COMMAND__A, - (data | SIO_SA_TX_COMMAND_TX_INVERT__M) - | SIO_SA_TX_COMMAND_TX_ENABLE__M); + rc = DRXJ_DAP.read_reg16func(dev_addr, SIO_SA_TX_COMMAND__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + if (ext_attr->smart_ant_inverted){ + + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_SA_TX_COMMAND__A, (data | SIO_SA_TX_COMMAND_TX_INVERT__M) | SIO_SA_TX_COMMAND_TX_ENABLE__M, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + } else - WR16(dev_addr, SIO_SA_TX_COMMAND__A, - (data & (~SIO_SA_TX_COMMAND_TX_INVERT__M)) - | SIO_SA_TX_COMMAND_TX_ENABLE__M); + { + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_SA_TX_COMMAND__A, (data & (~SIO_SA_TX_COMMAND_TX_INVERT__M)) | SIO_SA_TX_COMMAND_TX_ENABLE__M, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + } /* config SMA_TX pin to smart antenna mode */ - CHK_ERROR(ctrl_set_uio_cfg(demod, &uio_cfg)); - WR16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0x13); - WR16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_GPIO_FNC__A, 0x03); + rc = ctrl_set_uio_cfg(demod, &uio_cfg); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0x13, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_GPIO_FNC__A, 0x03, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Write magic word to disable pdr reg write */ - WR16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000); + rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } return (DRX_STS_OK); rw_error: @@ -3906,8 +4448,9 @@ ctrl_set_cfg_smart_ant(struct drx_demod_instance *demod, struct drxj_cfg_smart_a { struct drxj_data *ext_attr = NULL; struct i2c_device_addr *dev_addr = NULL; - u16 data = 0; + int rc; u32 start_time = 0; + u16 data = 0; static bool bit_inverted; dev_addr = demod->my_i2c_dev_addr; @@ -3920,12 +4463,20 @@ ctrl_set_cfg_smart_ant(struct drx_demod_instance *demod, struct drxj_cfg_smart_a if (bit_inverted != ext_attr->smart_ant_inverted || ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_FIRMWARE_SMA) { - CHK_ERROR(smart_ant_init(demod)); + rc = smart_ant_init(demod); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } bit_inverted = ext_attr->smart_ant_inverted; } /* Write magic word to enable pdr reg write */ - WR16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); + rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } switch (smart_ant->io) { case DRXJ_SMT_ANT_OUTPUT: @@ -3936,7 +4487,11 @@ ctrl_set_cfg_smart_ant(struct drx_demod_instance *demod, struct drxj_cfg_smart_a */ start_time = drxbsp_hst_clock(); do { - RR16(dev_addr, SIO_SA_TX_STATUS__A, &data); + rc = DRXJ_DAP.read_reg16func(dev_addr, SIO_SA_TX_STATUS__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } while ((data & SIO_SA_TX_STATUS_BUSY__M) && ((drxbsp_hst_clock() - start_time) < DRXJ_MAX_WAITTIME)); @@ -3946,30 +4501,33 @@ ctrl_set_cfg_smart_ant(struct drx_demod_instance *demod, struct drxj_cfg_smart_a } /* write to smart antenna configuration register */ - WR16(dev_addr, SIO_SA_TX_DATA0__A, 0x9200 - | ((smart_ant->ctrl_data & 0x0001) << 8) - | ((smart_ant->ctrl_data & 0x0002) << 10) - | ((smart_ant->ctrl_data & 0x0004) << 12) - ); - WR16(dev_addr, SIO_SA_TX_DATA1__A, 0x4924 - | ((smart_ant->ctrl_data & 0x0008) >> 2) - | ((smart_ant->ctrl_data & 0x0010)) - | ((smart_ant->ctrl_data & 0x0020) << 2) - | ((smart_ant->ctrl_data & 0x0040) << 4) - | ((smart_ant->ctrl_data & 0x0080) << 6) - ); - WR16(dev_addr, SIO_SA_TX_DATA2__A, 0x2492 - | ((smart_ant->ctrl_data & 0x0100) >> 8) - | ((smart_ant->ctrl_data & 0x0200) >> 6) - | ((smart_ant->ctrl_data & 0x0400) >> 4) - | ((smart_ant->ctrl_data & 0x0800) >> 2) - | ((smart_ant->ctrl_data & 0x1000)) - | ((smart_ant->ctrl_data & 0x2000) << 2) - ); - WR16(dev_addr, SIO_SA_TX_DATA3__A, 0xff8d); + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_SA_TX_DATA0__A, 0x9200 | ((smart_ant->ctrl_data & 0x0001) << 8) | ((smart_ant->ctrl_data & 0x0002) << 10) | ((smart_ant->ctrl_data & 0x0004) << 12), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_SA_TX_DATA1__A, 0x4924 | ((smart_ant->ctrl_data & 0x0008) >> 2) | ((smart_ant->ctrl_data & 0x0010)) | ((smart_ant->ctrl_data & 0x0020) << 2) | ((smart_ant->ctrl_data & 0x0040) << 4) | ((smart_ant->ctrl_data & 0x0080) << 6), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_SA_TX_DATA2__A, 0x2492 | ((smart_ant->ctrl_data & 0x0100) >> 8) | ((smart_ant->ctrl_data & 0x0200) >> 6) | ((smart_ant->ctrl_data & 0x0400) >> 4) | ((smart_ant->ctrl_data & 0x0800) >> 2) | ((smart_ant->ctrl_data & 0x1000)) | ((smart_ant->ctrl_data & 0x2000) << 2), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_SA_TX_DATA3__A, 0xff8d, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* trigger the sending */ - WR16(dev_addr, SIO_SA_TX_LENGTH__A, 56); + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_SA_TX_LENGTH__A, 56, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } break; case DRXJ_SMT_ANT_INPUT: @@ -3982,7 +4540,11 @@ ctrl_set_cfg_smart_ant(struct drx_demod_instance *demod, struct drxj_cfg_smart_a return (DRX_STS_INVALID_ARG); } /* Write magic word to enable pdr reg write */ - WR16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000); + rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } return (DRX_STS_OK); rw_error: @@ -3991,30 +4553,55 @@ rw_error: static int scu_command(struct i2c_device_addr *dev_addr, struct drxjscu_cmd *cmd) { - u16 cur_cmd = 0; + int rc; u32 start_time = 0; + u16 cur_cmd = 0; /* Check param */ if (cmd == NULL) return (DRX_STS_INVALID_ARG); /* Wait until SCU command interface is ready to receive command */ - RR16(dev_addr, SCU_RAM_COMMAND__A, &cur_cmd); + rc = DRXJ_DAP.read_reg16func(dev_addr, SCU_RAM_COMMAND__A, &cur_cmd, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if (cur_cmd != DRX_SCU_READY) { return (DRX_STS_ERROR); } switch (cmd->parameter_len) { case 5: - WR16(dev_addr, SCU_RAM_PARAM_4__A, *(cmd->parameter + 4)); /* fallthrough */ + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_PARAM_4__A, *(cmd->parameter + 4), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* fallthrough */ case 4: - WR16(dev_addr, SCU_RAM_PARAM_3__A, *(cmd->parameter + 3)); /* fallthrough */ + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_PARAM_3__A, *(cmd->parameter + 3), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* fallthrough */ case 3: - WR16(dev_addr, SCU_RAM_PARAM_2__A, *(cmd->parameter + 2)); /* fallthrough */ + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_PARAM_2__A, *(cmd->parameter + 2), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* fallthrough */ case 2: - WR16(dev_addr, SCU_RAM_PARAM_1__A, *(cmd->parameter + 1)); /* fallthrough */ + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_PARAM_1__A, *(cmd->parameter + 1), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* fallthrough */ case 1: - WR16(dev_addr, SCU_RAM_PARAM_0__A, *(cmd->parameter + 0)); /* fallthrough */ + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_PARAM_0__A, *(cmd->parameter + 0), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* fallthrough */ case 0: /* do nothing */ break; @@ -4022,12 +4609,20 @@ static int scu_command(struct i2c_device_addr *dev_addr, struct drxjscu_cmd *cmd /* this number of parameters is not supported */ return (DRX_STS_ERROR); } - WR16(dev_addr, SCU_RAM_COMMAND__A, cmd->command); + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_COMMAND__A, cmd->command, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Wait until SCU has processed command */ start_time = drxbsp_hst_clock(); do { - RR16(dev_addr, SCU_RAM_COMMAND__A, &cur_cmd); + rc = DRXJ_DAP.read_reg16func(dev_addr, SCU_RAM_COMMAND__A, &cur_cmd, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } while (!(cur_cmd == DRX_SCU_READY) && ((drxbsp_hst_clock() - start_time) < DRXJ_MAX_WAITTIME)); @@ -4041,13 +4636,29 @@ static int scu_command(struct i2c_device_addr *dev_addr, struct drxjscu_cmd *cmd switch (cmd->result_len) { case 4: - RR16(dev_addr, SCU_RAM_PARAM_3__A, cmd->result + 3); /* fallthrough */ + rc = DRXJ_DAP.read_reg16func(dev_addr, SCU_RAM_PARAM_3__A, cmd->result + 3, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* fallthrough */ case 3: - RR16(dev_addr, SCU_RAM_PARAM_2__A, cmd->result + 2); /* fallthrough */ + rc = DRXJ_DAP.read_reg16func(dev_addr, SCU_RAM_PARAM_2__A, cmd->result + 2, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* fallthrough */ case 2: - RR16(dev_addr, SCU_RAM_PARAM_1__A, cmd->result + 1); /* fallthrough */ + rc = DRXJ_DAP.read_reg16func(dev_addr, SCU_RAM_PARAM_1__A, cmd->result + 1, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* fallthrough */ case 1: - RR16(dev_addr, SCU_RAM_PARAM_0__A, cmd->result + 0); /* fallthrough */ + rc = DRXJ_DAP.read_reg16func(dev_addr, SCU_RAM_PARAM_0__A, cmd->result + 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* fallthrough */ case 0: /* do nothing */ break; @@ -4099,6 +4710,7 @@ int drxj_dap_scu_atomic_read_write_block(struct i2c_device_addr *dev_addr, u32 a u8 *data, bool read_flag) { struct drxjscu_cmd scu_cmd; + int rc; u16 set_param_parameters[15]; u16 cmd_result[15]; @@ -4131,7 +4743,11 @@ int drxj_dap_scu_atomic_read_write_block(struct i2c_device_addr *dev_addr, u32 a SCU_RAM_COMMAND_CMD_AUX_SCU_ATOMIC_ACCESS; scu_cmd.result = cmd_result; scu_cmd.parameter = set_param_parameters; - CHK_ERROR(scu_command(dev_addr, &scu_cmd)); + rc = scu_command(dev_addr, &scu_cmd); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if (read_flag == true) { int i = 0; @@ -4218,28 +4834,53 @@ ctrl_i2c_write_read(struct drx_demod_instance *demod, struct drxi2c_data *i2c_da */ static int adc_sync_measurement(struct drx_demod_instance *demod, u16 *count) { - u16 data = 0; struct i2c_device_addr *dev_addr = NULL; + int rc; + u16 data = 0; dev_addr = demod->my_i2c_dev_addr; /* Start measurement */ - WR16(dev_addr, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE); - WR16(dev_addr, IQM_AF_START_LOCK__A, 1); + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_START_LOCK__A, 1, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Wait at least 3*128*(1/sysclk) <<< 1 millisec */ - CHK_ERROR(drxbsp_hst_sleep(1)); + rc = drxbsp_hst_sleep(1); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } *count = 0; - RR16(dev_addr, IQM_AF_PHASE0__A, &data); + rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_PHASE0__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if (data == 127) { *count = *count + 1; } - RR16(dev_addr, IQM_AF_PHASE1__A, &data); + rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_PHASE1__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if (data == 127) { *count = *count + 1; } - RR16(dev_addr, IQM_AF_PHASE2__A, &data); + rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_PHASE2__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if (data == 127) { *count = *count + 1; } @@ -4263,23 +4904,40 @@ rw_error: static int adc_synchronization(struct drx_demod_instance *demod) { - u16 count = 0; struct i2c_device_addr *dev_addr = NULL; + int rc; + u16 count = 0; dev_addr = demod->my_i2c_dev_addr; - CHK_ERROR(adc_sync_measurement(demod, &count)); + rc = adc_sync_measurement(demod, &count); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if (count == 1) { /* Try sampling on a diffrent edge */ u16 clk_neg = 0; - RR16(dev_addr, IQM_AF_CLKNEG__A, &clk_neg); + rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_CLKNEG__A, &clk_neg, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } clk_neg ^= IQM_AF_CLKNEG_CLKNEGDATA__M; - WR16(dev_addr, IQM_AF_CLKNEG__A, clk_neg); + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_CLKNEG__A, clk_neg, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } - CHK_ERROR(adc_sync_measurement(demod, &count)); + rc = adc_sync_measurement(demod, &count); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } if (count < 2) { @@ -4300,11 +4958,16 @@ rw_error: */ static int iqm_set_af(struct drx_demod_instance *demod, bool active) { - u16 data = 0; struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + int rc; + u16 data = 0; /* Configure IQM */ - RR16(dev_addr, IQM_AF_STDBY__A, &data); + rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_STDBY__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if (!active) { data &= ((~IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE) @@ -4319,7 +4982,11 @@ static int iqm_set_af(struct drx_demod_instance *demod, bool active) | IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE | IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE); } - WR16(dev_addr, IQM_AF_STDBY__A, data); + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_STDBY__A, data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } return (DRX_STS_OK); rw_error: @@ -4341,6 +5008,7 @@ ctrl_set_cfg_pdr_safe_mode(struct drx_demod_instance *demod, bool *enable) { struct drxj_data *ext_attr = NULL; struct i2c_device_addr *dev_addr = NULL; + int rc; if (enable == NULL) return (DRX_STS_INVALID_ARG); @@ -4349,87 +5017,215 @@ ctrl_set_cfg_pdr_safe_mode(struct drx_demod_instance *demod, bool *enable) ext_attr = (struct drxj_data *) demod->my_ext_attr; /* Write magic word to enable pdr reg write */ - WR16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if (*enable == true) { bool bridge_enabled = false; /* MPEG pins to input */ - WR16(dev_addr, SIO_PDR_MSTRT_CFG__A, DRXJ_PIN_SAFE_MODE); - WR16(dev_addr, SIO_PDR_MERR_CFG__A, DRXJ_PIN_SAFE_MODE); - WR16(dev_addr, SIO_PDR_MCLK_CFG__A, DRXJ_PIN_SAFE_MODE); - WR16(dev_addr, SIO_PDR_MVAL_CFG__A, DRXJ_PIN_SAFE_MODE); - WR16(dev_addr, SIO_PDR_MD0_CFG__A, DRXJ_PIN_SAFE_MODE); - WR16(dev_addr, SIO_PDR_MD1_CFG__A, DRXJ_PIN_SAFE_MODE); - WR16(dev_addr, SIO_PDR_MD2_CFG__A, DRXJ_PIN_SAFE_MODE); - WR16(dev_addr, SIO_PDR_MD3_CFG__A, DRXJ_PIN_SAFE_MODE); - WR16(dev_addr, SIO_PDR_MD4_CFG__A, DRXJ_PIN_SAFE_MODE); - WR16(dev_addr, SIO_PDR_MD5_CFG__A, DRXJ_PIN_SAFE_MODE); - WR16(dev_addr, SIO_PDR_MD6_CFG__A, DRXJ_PIN_SAFE_MODE); - WR16(dev_addr, SIO_PDR_MD7_CFG__A, DRXJ_PIN_SAFE_MODE); + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MSTRT_CFG__A, DRXJ_PIN_SAFE_MODE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MERR_CFG__A, DRXJ_PIN_SAFE_MODE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MCLK_CFG__A, DRXJ_PIN_SAFE_MODE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MVAL_CFG__A, DRXJ_PIN_SAFE_MODE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD0_CFG__A, DRXJ_PIN_SAFE_MODE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD1_CFG__A, DRXJ_PIN_SAFE_MODE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD2_CFG__A, DRXJ_PIN_SAFE_MODE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD3_CFG__A, DRXJ_PIN_SAFE_MODE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD4_CFG__A, DRXJ_PIN_SAFE_MODE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD5_CFG__A, DRXJ_PIN_SAFE_MODE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD6_CFG__A, DRXJ_PIN_SAFE_MODE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD7_CFG__A, DRXJ_PIN_SAFE_MODE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* PD_I2C_SDA2 Bridge off, Port2 Inactive PD_I2C_SCL2 Bridge off, Port2 Inactive */ - CHK_ERROR(ctrl_i2c_bridge(demod, &bridge_enabled)); - WR16(dev_addr, SIO_PDR_I2C_SDA2_CFG__A, DRXJ_PIN_SAFE_MODE); - WR16(dev_addr, SIO_PDR_I2C_SCL2_CFG__A, DRXJ_PIN_SAFE_MODE); + rc = ctrl_i2c_bridge(demod, &bridge_enabled); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_I2C_SDA2_CFG__A, DRXJ_PIN_SAFE_MODE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_I2C_SCL2_CFG__A, DRXJ_PIN_SAFE_MODE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* PD_GPIO Store and set to input PD_VSYNC Store and set to input PD_SMA_RX Store and set to input PD_SMA_TX Store and set to input */ - RR16(dev_addr, SIO_PDR_GPIO_CFG__A, - &ext_attr->pdr_safe_restore_val_gpio); - RR16(dev_addr, SIO_PDR_VSYNC_CFG__A, - &ext_attr->pdr_safe_restore_val_v_sync); - RR16(dev_addr, SIO_PDR_SMA_RX_CFG__A, - &ext_attr->pdr_safe_restore_val_sma_rx); - RR16(dev_addr, SIO_PDR_SMA_TX_CFG__A, - &ext_attr->pdr_safe_restore_val_sma_tx); - WR16(dev_addr, SIO_PDR_GPIO_CFG__A, DRXJ_PIN_SAFE_MODE); - WR16(dev_addr, SIO_PDR_VSYNC_CFG__A, DRXJ_PIN_SAFE_MODE); - WR16(dev_addr, SIO_PDR_SMA_RX_CFG__A, DRXJ_PIN_SAFE_MODE); - WR16(dev_addr, SIO_PDR_SMA_TX_CFG__A, DRXJ_PIN_SAFE_MODE); + rc = DRXJ_DAP.read_reg16func(dev_addr, SIO_PDR_GPIO_CFG__A, &ext_attr->pdr_safe_restore_val_gpio, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.read_reg16func(dev_addr, SIO_PDR_VSYNC_CFG__A, &ext_attr->pdr_safe_restore_val_v_sync, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.read_reg16func(dev_addr, SIO_PDR_SMA_RX_CFG__A, &ext_attr->pdr_safe_restore_val_sma_rx, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.read_reg16func(dev_addr, SIO_PDR_SMA_TX_CFG__A, &ext_attr->pdr_safe_restore_val_sma_tx, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_GPIO_CFG__A, DRXJ_PIN_SAFE_MODE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_VSYNC_CFG__A, DRXJ_PIN_SAFE_MODE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_SMA_RX_CFG__A, DRXJ_PIN_SAFE_MODE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_SMA_TX_CFG__A, DRXJ_PIN_SAFE_MODE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* PD_RF_AGC Analog DAC outputs, cannot be set to input or tristate! PD_IF_AGC Analog DAC outputs, cannot be set to input or tristate! */ - CHK_ERROR(iqm_set_af(demod, false)); + rc = iqm_set_af(demod, false); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* PD_CVBS Analog DAC output, standby mode PD_SIF Analog DAC output, standby mode */ - WR16(dev_addr, ATV_TOP_STDBY__A, - (ATV_TOP_STDBY_SIF_STDBY_STANDBY & - (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE))); + rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_STDBY__A, (ATV_TOP_STDBY_SIF_STDBY_STANDBY & (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE)), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* PD_I2S_CL Input PD_I2S_DA Input PD_I2S_WS Input */ - WR16(dev_addr, SIO_PDR_I2S_CL_CFG__A, DRXJ_PIN_SAFE_MODE); - WR16(dev_addr, SIO_PDR_I2S_DA_CFG__A, DRXJ_PIN_SAFE_MODE); - WR16(dev_addr, SIO_PDR_I2S_WS_CFG__A, DRXJ_PIN_SAFE_MODE); + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_I2S_CL_CFG__A, DRXJ_PIN_SAFE_MODE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_I2S_DA_CFG__A, DRXJ_PIN_SAFE_MODE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_I2S_WS_CFG__A, DRXJ_PIN_SAFE_MODE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } else { /* No need to restore MPEG pins; is done in SetStandard/SetChannel */ /* PD_I2C_SDA2 Port2 active PD_I2C_SCL2 Port2 active */ - WR16(dev_addr, SIO_PDR_I2C_SDA2_CFG__A, - SIO_PDR_I2C_SDA2_CFG__PRE); - WR16(dev_addr, SIO_PDR_I2C_SCL2_CFG__A, - SIO_PDR_I2C_SCL2_CFG__PRE); + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_I2C_SDA2_CFG__A, SIO_PDR_I2C_SDA2_CFG__PRE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_I2C_SCL2_CFG__A, SIO_PDR_I2C_SCL2_CFG__PRE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* PD_GPIO Restore PD_VSYNC Restore PD_SMA_RX Restore PD_SMA_TX Restore */ - WR16(dev_addr, SIO_PDR_GPIO_CFG__A, - ext_attr->pdr_safe_restore_val_gpio); - WR16(dev_addr, SIO_PDR_VSYNC_CFG__A, - ext_attr->pdr_safe_restore_val_v_sync); - WR16(dev_addr, SIO_PDR_SMA_RX_CFG__A, - ext_attr->pdr_safe_restore_val_sma_rx); - WR16(dev_addr, SIO_PDR_SMA_TX_CFG__A, - ext_attr->pdr_safe_restore_val_sma_tx); + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_GPIO_CFG__A, ext_attr->pdr_safe_restore_val_gpio, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_VSYNC_CFG__A, ext_attr->pdr_safe_restore_val_v_sync, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_SMA_RX_CFG__A, ext_attr->pdr_safe_restore_val_sma_rx, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_SMA_TX_CFG__A, ext_attr->pdr_safe_restore_val_sma_tx, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* PD_RF_AGC, PD_IF_AGC No need to restore; will be restored in SetStandard/SetChannel */ @@ -4442,7 +5238,11 @@ ctrl_set_cfg_pdr_safe_mode(struct drx_demod_instance *demod, bool *enable) } /* Write magic word to disable pdr reg write */ - WR16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000); + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } ext_attr->pdr_safe_mode = *enable; return (DRX_STS_OK); @@ -4534,6 +5334,7 @@ static int init_agc(struct drx_demod_instance *demod) struct drxj_data *ext_attr = NULL; struct drxj_cfg_agc *p_agc_rf_settings = NULL; struct drxj_cfg_agc *p_agc_if_settings = NULL; + int rc; u16 ingain_tgt_max = 0; u16 clp_dir_to = 0; u16 sns_sum_max = 0; @@ -4549,6 +5350,7 @@ static int init_agc(struct drx_demod_instance *demod) u16 clp_ctrl_mode = 0; u16 agc_rf = 0; u16 agc_if = 0; + dev_addr = demod->my_i2c_dev_addr; common_attr = (struct drx_common_attr *) demod->my_common_attr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -4566,19 +5368,71 @@ static int init_agc(struct drx_demod_instance *demod) ki_min = 0x0117; ingain_tgt_max = 16383; clp_ctrl_mode = 0; - WR16(dev_addr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff); - WR16(dev_addr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0); - WR16(dev_addr, SCU_RAM_AGC_CLP_SUM__A, 0); - WR16(dev_addr, SCU_RAM_AGC_CLP_CYCCNT__A, 0); - WR16(dev_addr, SCU_RAM_AGC_CLP_DIR_WD__A, 0); - WR16(dev_addr, SCU_RAM_AGC_CLP_DIR_STP__A, 1); - WR16(dev_addr, SCU_RAM_AGC_SNS_SUM__A, 0); - WR16(dev_addr, SCU_RAM_AGC_SNS_CYCCNT__A, 0); - WR16(dev_addr, SCU_RAM_AGC_SNS_DIR_WD__A, 0); - WR16(dev_addr, SCU_RAM_AGC_SNS_DIR_STP__A, 1); - WR16(dev_addr, SCU_RAM_AGC_INGAIN__A, 1024); - WR16(dev_addr, SCU_RAM_VSB_AGC_POW_TGT__A, 22600); - WR16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, 13200); + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_CLP_SUM__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_CLP_CYCCNT__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_CLP_DIR_WD__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_CLP_DIR_STP__A, 1, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_SNS_SUM__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_SNS_CYCCNT__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_SNS_DIR_WD__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_SNS_DIR_STP__A, 1, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_INGAIN__A, 1024, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_VSB_AGC_POW_TGT__A, 22600, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, 13200, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } p_agc_if_settings = &(ext_attr->vsb_if_agc_cfg); p_agc_rf_settings = &(ext_attr->vsb_rf_agc_cfg); break; @@ -4597,23 +5451,75 @@ static int init_agc(struct drx_demod_instance *demod) agc_kiDgain = 0x7; ki_min = 0x0117; clp_ctrl_mode = 0; - WR16(dev_addr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff); - WR16(dev_addr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0); - WR16(dev_addr, SCU_RAM_AGC_CLP_SUM__A, 0); - WR16(dev_addr, SCU_RAM_AGC_CLP_CYCCNT__A, 0); - WR16(dev_addr, SCU_RAM_AGC_CLP_DIR_WD__A, 0); - WR16(dev_addr, SCU_RAM_AGC_CLP_DIR_STP__A, 1); - WR16(dev_addr, SCU_RAM_AGC_SNS_SUM__A, 0); - WR16(dev_addr, SCU_RAM_AGC_SNS_CYCCNT__A, 0); - WR16(dev_addr, SCU_RAM_AGC_SNS_DIR_WD__A, 0); - WR16(dev_addr, SCU_RAM_AGC_SNS_DIR_STP__A, 1); + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_CLP_SUM__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_CLP_CYCCNT__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_CLP_DIR_WD__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_CLP_DIR_STP__A, 1, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_SNS_SUM__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_SNS_CYCCNT__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_SNS_DIR_WD__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_SNS_DIR_STP__A, 1, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } p_agc_if_settings = &(ext_attr->qam_if_agc_cfg); p_agc_rf_settings = &(ext_attr->qam_rf_agc_cfg); - WR16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, p_agc_if_settings->top); + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, p_agc_if_settings->top, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } - RR16(dev_addr, SCU_RAM_AGC_KI__A, &agc_ki); + rc = DRXJ_DAP.read_reg16func(dev_addr, SCU_RAM_AGC_KI__A, &agc_ki, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } agc_ki &= 0xf000; - WR16(dev_addr, SCU_RAM_AGC_KI__A, agc_ki); + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_KI__A, agc_ki, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } break; #endif #ifndef DRXJ_DIGITAL_ONLY @@ -4631,7 +5537,11 @@ static int init_agc(struct drx_demod_instance *demod) clp_ctrl_mode = 1; p_agc_if_settings = &(ext_attr->atv_if_agc_cfg); p_agc_rf_settings = &(ext_attr->atv_rf_agc_cfg); - WR16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, p_agc_if_settings->top); + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, p_agc_if_settings->top, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } break; case DRX_STANDARD_NTSC: case DRX_STANDARD_PAL_SECAM_BG: @@ -4650,7 +5560,11 @@ static int init_agc(struct drx_demod_instance *demod) p_agc_rf_settings = &(ext_attr->atv_rf_agc_cfg); sns_dir_to = (u16) (-9); clp_ctrl_mode = 1; - WR16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, p_agc_if_settings->top); + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, p_agc_if_settings->top, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } break; case DRX_STANDARD_PAL_SECAM_L: case DRX_STANDARD_PAL_SECAM_LP: @@ -4667,7 +5581,11 @@ static int init_agc(struct drx_demod_instance *demod) clp_ctrl_mode = 1; p_agc_if_settings = &(ext_attr->atv_if_agc_cfg); p_agc_rf_settings = &(ext_attr->atv_rf_agc_cfg); - WR16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, p_agc_if_settings->top); + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, p_agc_if_settings->top, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } break; #endif default: @@ -4675,32 +5593,136 @@ static int init_agc(struct drx_demod_instance *demod) } /* for new AGC interface */ - WR16(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_if_settings->top); - WR16(dev_addr, SCU_RAM_AGC_INGAIN__A, p_agc_if_settings->top); /* Gain fed from inner to outer AGC */ - WR16(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max); - WR16(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, if_iaccu_hi_tgt_min); - WR16(dev_addr, SCU_RAM_AGC_IF_IACCU_HI__A, 0); /* set to p_agc_settings->top before */ - WR16(dev_addr, SCU_RAM_AGC_IF_IACCU_LO__A, 0); - WR16(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, 0); - WR16(dev_addr, SCU_RAM_AGC_RF_IACCU_LO__A, 0); - WR16(dev_addr, SCU_RAM_AGC_RF_MAX__A, 32767); - WR16(dev_addr, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max); - WR16(dev_addr, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max); - WR16(dev_addr, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, ki_innergain_min); - WR16(dev_addr, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50); - WR16(dev_addr, SCU_RAM_AGC_KI_CYCLEN__A, 500); - WR16(dev_addr, SCU_RAM_AGC_SNS_CYCLEN__A, 500); - WR16(dev_addr, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20); - WR16(dev_addr, SCU_RAM_AGC_KI_MIN__A, ki_min); - WR16(dev_addr, SCU_RAM_AGC_KI_MAX__A, ki_max); - WR16(dev_addr, SCU_RAM_AGC_KI_RED__A, 0); - WR16(dev_addr, SCU_RAM_AGC_CLP_SUM_MIN__A, 8); - WR16(dev_addr, SCU_RAM_AGC_CLP_CYCLEN__A, 500); - WR16(dev_addr, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to); - WR16(dev_addr, SCU_RAM_AGC_SNS_SUM_MIN__A, 8); - WR16(dev_addr, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to); - WR16(dev_addr, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, 50); - WR16(dev_addr, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode); + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_if_settings->top, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_INGAIN__A, p_agc_if_settings->top, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Gain fed from inner to outer AGC */ + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, if_iaccu_hi_tgt_min, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_IF_IACCU_HI__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* set to p_agc_settings->top before */ + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_IF_IACCU_LO__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_RF_IACCU_LO__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_RF_MAX__A, 32767, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, ki_innergain_min, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_KI_CYCLEN__A, 500, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_SNS_CYCLEN__A, 500, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_KI_MIN__A, ki_min, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_KI_MAX__A, ki_max, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_KI_RED__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_CLP_SUM_MIN__A, 8, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_CLP_CYCLEN__A, 500, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_SNS_SUM_MIN__A, 8, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, 50, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } agc_rf = 0x800 + p_agc_rf_settings->cut_off_current; if (common_attr->tuner_rf_agc_pol == true) { @@ -4712,14 +5734,30 @@ static int init_agc(struct drx_demod_instance *demod) agc_rf = 0x87ff - agc_rf; } - WR16(dev_addr, IQM_AF_AGC_RF__A, agc_rf); - WR16(dev_addr, IQM_AF_AGC_IF__A, agc_if); + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_AGC_RF__A, agc_rf, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_AGC_IF__A, agc_if, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Set/restore Ki DGAIN factor */ - RR16(dev_addr, SCU_RAM_AGC_KI__A, &data); + rc = DRXJ_DAP.read_reg16func(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } data &= ~SCU_RAM_AGC_KI_DGAIN__M; data |= (agc_kiDgain << SCU_RAM_AGC_KI_DGAIN__B); - WR16(dev_addr, SCU_RAM_AGC_KI__A, data); + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_KI__A, data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } return (DRX_STS_OK); rw_error: @@ -4740,6 +5778,7 @@ set_frequency(struct drx_demod_instance *demod, { struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; struct drxj_data *ext_attr = demod->my_ext_attr; + int rc; s32 sampling_frequency = 0; s32 frequency_shift = 0; s32 if_freq_actual = 0; @@ -4814,7 +5853,11 @@ set_frequency(struct drx_demod_instance *demod, /* Program frequency shifter with tuner offset compensation */ /* frequency_shift += tuner_freq_offset; TODO */ - WR32(dev_addr, IQM_FS_RATE_OFS_LO__A, iqm_fs_rate_ofs); + rc = DRXJ_DAP.write_reg32func(dev_addr, IQM_FS_RATE_OFS_LO__A, iqm_fs_rate_ofs, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } ext_attr->iqm_fs_rate_ofs = iqm_fs_rate_ofs; ext_attr->pos_image = (bool) (rf_mirror ^ tuner_mirror ^ select_pos_image); @@ -4841,6 +5884,7 @@ rw_error: static int get_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength) { struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + int rc; u16 rf_gain = 0; u16 if_gain = 0; u16 if_agc_sns = 0; @@ -4848,9 +5892,17 @@ static int get_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength) u16 rf_agc_max = 0; u16 rf_agc_min = 0; - RR16(dev_addr, IQM_AF_AGC_IF__A, &if_gain); + rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_AGC_IF__A, &if_gain, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if_gain &= IQM_AF_AGC_IF__M; - RR16(dev_addr, IQM_AF_AGC_RF__A, &rf_gain); + rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_AGC_RF__A, &rf_gain, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } rf_gain &= IQM_AF_AGC_RF__M; if_agc_sns = DRXJ_AGC_SNS; @@ -4862,18 +5914,27 @@ static int get_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength) if (rf_gain > rf_agc_max) *sig_strength = 100; else if (rf_gain > rf_agc_min) { - CHK_ZERO(rf_agc_max - rf_agc_min); + if (rf_agc_max == rf_agc_min) { + pr_err("error: rf_agc_max == rf_agc_min\n"); + return DRX_STS_ERROR;; + } *sig_strength = 75 + 25 * (rf_gain - rf_agc_min) / (rf_agc_max - rf_agc_min); } else *sig_strength = 75; } else if (if_gain > if_agc_sns) { - CHK_ZERO(if_agc_top - if_agc_sns); + if (if_agc_top == if_agc_sns) { + pr_err("error: if_agc_top == if_agc_sns\n"); + return DRX_STS_ERROR;; + } *sig_strength = 20 + 55 * (if_gain - if_agc_sns) / (if_agc_top - if_agc_sns); } else { - CHK_ZERO(if_agc_sns); + if (!if_agc_sns) { + pr_err("error: if_agc_sns is zero!\n"); + return DRX_STS_ERROR;; + } *sig_strength = (20 * if_gain / if_agc_sns); } @@ -4895,6 +5956,7 @@ rw_error: #ifdef DRXJ_SIGNAL_ACCUM_ERR static int get_acc_pkt_err(struct drx_demod_instance *demod, u16 *packet_err) { + int rc; static u16 pkt_err; static u16 last_pkt_err; u16 data = 0; @@ -4904,7 +5966,11 @@ static int get_acc_pkt_err(struct drx_demod_instance *demod, u16 *packet_err) ext_attr = (struct drxj_data *) demod->my_ext_attr; dev_addr = demod->my_i2c_dev_addr; - RR16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, &data); + rc = DRXJ_DAP.read_reg16func(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if (ext_attr->reset_pkt_err_acc == true) { last_pkt_err = data; pkt_err = 0; @@ -4938,12 +6004,17 @@ static int ctrl_set_cfg_reset_pkt_err(struct drx_demod_instance *demod) { #ifdef DRXJ_SIGNAL_ACCUM_ERR struct drxj_data *ext_attr = NULL; + int rc; u16 packet_error = 0; ext_attr = (struct drxj_data *) demod->my_ext_attr; ext_attr->reset_pkt_err_acc = true; /* call to reset counter */ - CHK_ERROR(get_acc_pkt_err(demod, &packet_error)); + rc = get_acc_pkt_err(demod, &packet_error); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } return (DRX_STS_OK); rw_error: @@ -4958,13 +6029,18 @@ rw_error: */ static int get_str_freq_offset(struct drx_demod_instance *demod, s32 *str_freq) { + int rc; u32 symbol_frequency_ratio = 0; u32 symbol_nom_frequency_ratio = 0; struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; struct drxj_data *ext_attr = demod->my_ext_attr; - ARR32(dev_addr, IQM_RC_RATE_LO__A, &symbol_frequency_ratio); + rc = drxj_dap_atomic_read_reg32(dev_addr, IQM_RC_RATE_LO__A, &symbol_frequency_ratio, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } symbol_nom_frequency_ratio = ext_attr->iqm_rc_rate_ofs; if (symbol_frequency_ratio > symbol_nom_frequency_ratio) @@ -5001,6 +6077,7 @@ static int get_ctl_freq_offset(struct drx_demod_instance *demod, s32 *ctl_freq) struct drxj_data *ext_attr = NULL; struct drx_common_attr *common_attr = NULL; struct i2c_device_addr *dev_addr = NULL; + int rc; dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -5010,7 +6087,11 @@ static int get_ctl_freq_offset(struct drx_demod_instance *demod, s32 *ctl_freq) /* both registers are sign extended */ nominal_frequency = ext_attr->iqm_fs_rate_ofs; - ARR32(dev_addr, IQM_FS_RATE_LO__A, (u32 *)¤t_frequency); + rc = drxj_dap_atomic_read_reg32(dev_addr, IQM_FS_RATE_LO__A, (u32 *)¤t_frequency, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if (ext_attr->pos_image == true) { /* negative image */ @@ -5052,6 +6133,7 @@ set_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, struct drxj_data *ext_attr = NULL; struct drxj_cfg_agc *p_agc_settings = NULL; struct drx_common_attr *common_attr = NULL; + int rc; drx_write_reg16func_t scu_wr16 = NULL; drx_read_reg16func_t scu_rr16 = NULL; @@ -5079,13 +6161,24 @@ set_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, case DRX_AGC_CTRL_AUTO: /* Enable RF AGC DAC */ - RR16(dev_addr, IQM_AF_STDBY__A, &data); + rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_STDBY__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } data |= IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE; - WR16(dev_addr, IQM_AF_STDBY__A, data); + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_STDBY__A, data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Enable SCU RF AGC loop */ - CHK_ERROR((*scu_rr16) - (dev_addr, SCU_RAM_AGC_KI__A, &data, 0)); + rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } data &= ~SCU_RAM_AGC_KI_RF__M; if (ext_attr->standard == DRX_STANDARD_8VSB) { data |= (2 << SCU_RAM_AGC_KI_RF__B); @@ -5100,20 +6193,24 @@ set_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, } else { data &= ~SCU_RAM_AGC_KI_INV_RF_POL__M; } - CHK_ERROR((*scu_wr16) - (dev_addr, SCU_RAM_AGC_KI__A, data, 0)); + rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Set speed ( using complementary reduction value ) */ - CHK_ERROR((*scu_rr16) - (dev_addr, SCU_RAM_AGC_KI_RED__A, &data, 0)); + rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M; - CHK_ERROR((*scu_wr16) (dev_addr, SCU_RAM_AGC_KI_RED__A, - (~ - (agc_settings-> - speed << - SCU_RAM_AGC_KI_RED_RAGC_RED__B) -& SCU_RAM_AGC_KI_RED_RAGC_RED__M) - | data, 0)); + rc = (*scu_wr16) (dev_addr, SCU_RAM_AGC_KI_RED__A,(~(agc_settings->speed << SCU_RAM_AGC_KI_RED_RAGC_RED__B) & SCU_RAM_AGC_KI_RED_RAGC_RED__M) | data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if (agc_settings->standard == DRX_STANDARD_8VSB) p_agc_settings = &(ext_attr->vsb_if_agc_cfg); @@ -5126,58 +6223,92 @@ set_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, /* Set TOP, only if IF-AGC is in AUTO mode */ if (p_agc_settings->ctrl_mode == DRX_AGC_CTRL_AUTO) { - CHK_ERROR((*scu_wr16) - (dev_addr, - SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, - agc_settings->top, 0)); - CHK_ERROR((*scu_wr16) - (dev_addr, - SCU_RAM_AGC_IF_IACCU_HI_TGT__A, - agc_settings->top, 0)); + rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, agc_settings->top, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, agc_settings->top, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } /* Cut-Off current */ - CHK_ERROR((*scu_wr16) - (dev_addr, SCU_RAM_AGC_RF_IACCU_HI_CO__A, - agc_settings->cut_off_current, 0)); + rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_RF_IACCU_HI_CO__A, agc_settings->cut_off_current, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } break; case DRX_AGC_CTRL_USER: /* Enable RF AGC DAC */ - RR16(dev_addr, IQM_AF_STDBY__A, &data); + rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_STDBY__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } data |= IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE; - WR16(dev_addr, IQM_AF_STDBY__A, data); + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_STDBY__A, data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Disable SCU RF AGC loop */ - CHK_ERROR((*scu_rr16) - (dev_addr, SCU_RAM_AGC_KI__A, &data, 0)); + rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } data &= ~SCU_RAM_AGC_KI_RF__M; if (common_attr->tuner_rf_agc_pol) { data |= SCU_RAM_AGC_KI_INV_RF_POL__M; } else { data &= ~SCU_RAM_AGC_KI_INV_RF_POL__M; } - CHK_ERROR((*scu_wr16) - (dev_addr, SCU_RAM_AGC_KI__A, data, 0)); + rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Write value to output pin */ - CHK_ERROR((*scu_wr16) - (dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, - agc_settings->output_level, 0)); + rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, agc_settings->output_level, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } break; case DRX_AGC_CTRL_OFF: /* Disable RF AGC DAC */ - RR16(dev_addr, IQM_AF_STDBY__A, &data); + rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_STDBY__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } data &= (~IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE); - WR16(dev_addr, IQM_AF_STDBY__A, data); + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_STDBY__A, data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Disable SCU RF AGC loop */ - CHK_ERROR((*scu_rr16) - (dev_addr, SCU_RAM_AGC_KI__A, &data, 0)); + rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } data &= ~SCU_RAM_AGC_KI_RF__M; - CHK_ERROR((*scu_wr16) - (dev_addr, SCU_RAM_AGC_KI__A, data, 0)); + rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } break; default: return (DRX_STS_INVALID_ARG); @@ -5229,6 +6360,7 @@ get_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings) struct i2c_device_addr *dev_addr = NULL; struct drxj_data *ext_attr = NULL; enum drx_standard standard = DRX_STANDARD_UNKNOWN; + int rc; dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -5268,8 +6400,11 @@ get_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings) DRXJ_ISQAMSTD(agc_settings->standard)) || (DRXJ_ISATVSTD(ext_attr->standard) && DRXJ_ISATVSTD(agc_settings->standard))) { - SARR16(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, - &(agc_settings->output_level)); + rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, &(agc_settings->output_level), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } return (DRX_STS_OK); @@ -5293,6 +6428,7 @@ set_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, struct drx_common_attr *common_attr = NULL; drx_write_reg16func_t scu_wr16 = NULL; drx_read_reg16func_t scu_rr16 = NULL; + int rc; common_attr = (struct drx_common_attr *) demod->my_common_attr; dev_addr = demod->my_i2c_dev_addr; @@ -5317,13 +6453,24 @@ set_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, switch (agc_settings->ctrl_mode) { case DRX_AGC_CTRL_AUTO: /* Enable IF AGC DAC */ - RR16(dev_addr, IQM_AF_STDBY__A, &data); + rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_STDBY__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } data |= IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE; - WR16(dev_addr, IQM_AF_STDBY__A, data); + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_STDBY__A, data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Enable SCU IF AGC loop */ - CHK_ERROR((*scu_rr16) - (dev_addr, SCU_RAM_AGC_KI__A, &data, 0)); + rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M; data &= ~SCU_RAM_AGC_KI_IF__M; if (ext_attr->standard == DRX_STANDARD_8VSB) { @@ -5339,20 +6486,24 @@ set_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, } else { data &= ~SCU_RAM_AGC_KI_INV_IF_POL__M; } - CHK_ERROR((*scu_wr16) - (dev_addr, SCU_RAM_AGC_KI__A, data, 0)); + rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Set speed (using complementary reduction value) */ - CHK_ERROR((*scu_rr16) - (dev_addr, SCU_RAM_AGC_KI_RED__A, &data, 0)); + rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M; - CHK_ERROR((*scu_wr16) (dev_addr, SCU_RAM_AGC_KI_RED__A, - (~ - (agc_settings-> - speed << - SCU_RAM_AGC_KI_RED_IAGC_RED__B) -& SCU_RAM_AGC_KI_RED_IAGC_RED__M) - | data, 0)); + rc = (*scu_wr16) (dev_addr, SCU_RAM_AGC_KI_RED__A, (~(agc_settings->speed << SCU_RAM_AGC_KI_RED_IAGC_RED__B) & SCU_RAM_AGC_KI_RED_IAGC_RED__M) | data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if (agc_settings->standard == DRX_STANDARD_8VSB) p_agc_settings = &(ext_attr->vsb_rf_agc_cfg); @@ -5365,36 +6516,51 @@ set_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, /* Restore TOP */ if (p_agc_settings->ctrl_mode == DRX_AGC_CTRL_AUTO) { - CHK_ERROR((*scu_wr16) - (dev_addr, - SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, - p_agc_settings->top, 0)); - CHK_ERROR((*scu_wr16) - (dev_addr, - SCU_RAM_AGC_IF_IACCU_HI_TGT__A, - p_agc_settings->top, 0)); + rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, p_agc_settings->top, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, p_agc_settings->top, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } else { - CHK_ERROR((*scu_wr16) - (dev_addr, - SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, - 0, 0)); - CHK_ERROR((*scu_wr16) - (dev_addr, - SCU_RAM_AGC_IF_IACCU_HI_TGT__A, 0, - 0)); + rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } break; case DRX_AGC_CTRL_USER: /* Enable IF AGC DAC */ - RR16(dev_addr, IQM_AF_STDBY__A, &data); + rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_STDBY__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } data |= IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE; - WR16(dev_addr, IQM_AF_STDBY__A, data); + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_STDBY__A, data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Disable SCU IF AGC loop */ - CHK_ERROR((*scu_rr16) - (dev_addr, SCU_RAM_AGC_KI__A, &data, 0)); + rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M; data |= SCU_RAM_AGC_KI_IF_AGC_DISABLE__M; if (common_attr->tuner_if_agc_pol) { @@ -5402,38 +6568,59 @@ set_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, } else { data &= ~SCU_RAM_AGC_KI_INV_IF_POL__M; } - CHK_ERROR((*scu_wr16) - (dev_addr, SCU_RAM_AGC_KI__A, data, 0)); + rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Write value to output pin */ - CHK_ERROR((*scu_wr16) - (dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, - agc_settings->output_level, 0)); + rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, agc_settings->output_level, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } break; case DRX_AGC_CTRL_OFF: /* Disable If AGC DAC */ - RR16(dev_addr, IQM_AF_STDBY__A, &data); + rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_STDBY__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } data &= (~IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE); - WR16(dev_addr, IQM_AF_STDBY__A, data); + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_STDBY__A, data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Disable SCU IF AGC loop */ - CHK_ERROR((*scu_rr16) - (dev_addr, SCU_RAM_AGC_KI__A, &data, 0)); + rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M; data |= SCU_RAM_AGC_KI_IF_AGC_DISABLE__M; - CHK_ERROR((*scu_wr16) - (dev_addr, SCU_RAM_AGC_KI__A, data, 0)); + rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } break; default: return (DRX_STS_INVALID_ARG); } /* switch ( agcsettings->ctrl_mode ) */ /* always set the top to support configurations without if-loop */ - CHK_ERROR((*scu_wr16) (dev_addr, - SCU_RAM_AGC_INGAIN_TGT_MIN__A, - agc_settings->top, 0)); + rc = (*scu_wr16) (dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, agc_settings->top, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } /* Store if agc settings */ @@ -5481,6 +6668,7 @@ get_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings) struct i2c_device_addr *dev_addr = NULL; struct drxj_data *ext_attr = NULL; enum drx_standard standard = DRX_STANDARD_UNKNOWN; + int rc; dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -5521,8 +6709,11 @@ get_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings) (DRXJ_ISATVSTD(ext_attr->standard) && DRXJ_ISATVSTD(agc_settings->standard))) { /* read output level */ - SARR16(dev_addr, SCU_RAM_AGC_IF_IACCU_HI__A, - &(agc_settings->output_level)); + rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_HI__A, &(agc_settings->output_level), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } return (DRX_STS_OK); @@ -5541,11 +6732,16 @@ static int set_iqm_af(struct drx_demod_instance *demod, bool active) { u16 data = 0; struct i2c_device_addr *dev_addr = NULL; + int rc; dev_addr = demod->my_i2c_dev_addr; /* Configure IQM */ - RR16(dev_addr, IQM_AF_STDBY__A, &data); + rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_STDBY__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if (!active) { data &= ((~IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE) @@ -5561,7 +6757,11 @@ static int set_iqm_af(struct drx_demod_instance *demod, bool active) | IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE | IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE); } - WR16(dev_addr, IQM_AF_STDBY__A, data); + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_STDBY__A, data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } return (DRX_STS_OK); rw_error: @@ -5594,8 +6794,9 @@ static int power_down_vsb(struct drx_demod_instance *demod, bool primary) /* *parameter */ NULL, /* *result */ NULL }; - u16 cmd_result = 0; struct drx_cfg_mpeg_output cfg_mpeg_output; + int rc; + u16 cmd_result = 0; /* STOP demodulator @@ -5607,24 +6808,68 @@ static int power_down_vsb(struct drx_demod_instance *demod, bool primary) cmd_scu.result_len = 1; cmd_scu.parameter = NULL; cmd_scu.result = &cmd_result; - CHK_ERROR(scu_command(dev_addr, &cmd_scu)); + rc = scu_command(dev_addr, &cmd_scu); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* stop all comm_exec */ - WR16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP); - WR16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP); + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if (primary == true) { - WR16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP); - CHK_ERROR(set_iqm_af(demod, false)); + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = set_iqm_af(demod, false); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } else { - WR16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP); - WR16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP); - WR16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP); - WR16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP); - WR16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP); + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } cfg_mpeg_output.enable_mpeg_output = false; - CHK_ERROR(ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output)); + rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } return (DRX_STS_OK); rw_error: @@ -5640,6 +6885,7 @@ rw_error: static int set_vsb_leak_n_gain(struct drx_demod_instance *demod) { struct i2c_device_addr *dev_addr = NULL; + int rc; const u8 vsb_ffe_leak_gain_ram0[] = { DRXJ_16TO8(0x8), /* FFETRAINLKRATIO1 */ @@ -5830,10 +7076,16 @@ static int set_vsb_leak_n_gain(struct drx_demod_instance *demod) }; dev_addr = demod->my_i2c_dev_addr; - WRB(dev_addr, VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__A, - sizeof(vsb_ffe_leak_gain_ram0), ((u8 *)vsb_ffe_leak_gain_ram0)); - WRB(dev_addr, VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__A, - sizeof(vsb_ffe_leak_gain_ram1), ((u8 *)vsb_ffe_leak_gain_ram1)); + rc = DRXJ_DAP.write_block_func(dev_addr, VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__A, sizeof(vsb_ffe_leak_gain_ram0), ((u8 *)vsb_ffe_leak_gain_ram0), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_block_func(dev_addr, VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__A, sizeof(vsb_ffe_leak_gain_ram1), ((u8 *)vsb_ffe_leak_gain_ram1), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } return (DRX_STS_OK); rw_error: @@ -5850,11 +7102,12 @@ rw_error: static int set_vsb(struct drx_demod_instance *demod) { struct i2c_device_addr *dev_addr = NULL; - u16 cmd_result = 0; - u16 cmd_param = 0; + int rc; struct drx_common_attr *common_attr = NULL; struct drxjscu_cmd cmd_scu; struct drxj_data *ext_attr = NULL; + u16 cmd_result = 0; + u16 cmd_param = 0; const u8 vsb_taps_re[] = { DRXJ_16TO8(-2), /* re0 */ DRXJ_16TO8(4), /* re1 */ @@ -5891,13 +7144,41 @@ static int set_vsb(struct drx_demod_instance *demod) ext_attr = (struct drxj_data *) demod->my_ext_attr; /* stop all comm_exec */ - WR16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP); - WR16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP); - WR16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP); - WR16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP); - WR16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP); - WR16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP); - WR16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP); + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* reset demodulator */ cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB @@ -5906,105 +7187,313 @@ static int set_vsb(struct drx_demod_instance *demod) cmd_scu.result_len = 1; cmd_scu.parameter = NULL; cmd_scu.result = &cmd_result; - CHK_ERROR(scu_command(dev_addr, &cmd_scu)); + rc = scu_command(dev_addr, &cmd_scu); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } - WR16(dev_addr, IQM_AF_DCF_BYPASS__A, 1); - WR16(dev_addr, IQM_FS_ADJ_SEL__A, IQM_FS_ADJ_SEL_B_VSB); - WR16(dev_addr, IQM_RC_ADJ_SEL__A, IQM_RC_ADJ_SEL_B_VSB); + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_DCF_BYPASS__A, 1, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_FS_ADJ_SEL__A, IQM_FS_ADJ_SEL_B_VSB, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RC_ADJ_SEL__A, IQM_RC_ADJ_SEL_B_VSB, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } ext_attr->iqm_rc_rate_ofs = 0x00AD0D79; - WR32(dev_addr, IQM_RC_RATE_OFS_LO__A, ext_attr->iqm_rc_rate_ofs); - WR16(dev_addr, VSB_TOP_CFAGC_GAINSHIFT__A, 4); - WR16(dev_addr, VSB_TOP_CYGN1TRK__A, 1); - - WR16(dev_addr, IQM_RC_CROUT_ENA__A, 1); - WR16(dev_addr, IQM_RC_STRETCH__A, 28); - WR16(dev_addr, IQM_RT_ACTIVE__A, 0); - WR16(dev_addr, IQM_CF_SYMMETRIC__A, 0); - WR16(dev_addr, IQM_CF_MIDTAP__A, 3); - WR16(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_VSB__M); - WR16(dev_addr, IQM_CF_SCALE__A, 1393); - WR16(dev_addr, IQM_CF_SCALE_SH__A, 0); - WR16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 1); - - WRB(dev_addr, IQM_CF_TAP_RE0__A, sizeof(vsb_taps_re), - ((u8 *)vsb_taps_re)); - WRB(dev_addr, IQM_CF_TAP_IM0__A, sizeof(vsb_taps_re), - ((u8 *)vsb_taps_re)); - - WR16(dev_addr, VSB_TOP_BNTHRESH__A, 330); /* set higher threshold */ - WR16(dev_addr, VSB_TOP_CLPLASTNUM__A, 90); /* burst detection on */ - WR16(dev_addr, VSB_TOP_SNRTH_RCA1__A, 0x0042); /* drop thresholds by 1 dB */ - WR16(dev_addr, VSB_TOP_SNRTH_RCA2__A, 0x0053); /* drop thresholds by 2 dB */ - WR16(dev_addr, VSB_TOP_EQCTRL__A, 0x1); /* cma on */ - WR16(dev_addr, SCU_RAM_GPIO__A, 0); /* GPIO */ + rc = DRXJ_DAP.write_reg32func(dev_addr, IQM_RC_RATE_OFS_LO__A, ext_attr->iqm_rc_rate_ofs, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_CFAGC_GAINSHIFT__A, 4, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_CYGN1TRK__A, 1, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RC_CROUT_ENA__A, 1, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RC_STRETCH__A, 28, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_ACTIVE__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_SYMMETRIC__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_MIDTAP__A, 3, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_VSB__M, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_SCALE__A, 1393, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_SCALE_SH__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_POW_MEAS_LEN__A, 1, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(vsb_taps_re), ((u8 *)vsb_taps_re), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(vsb_taps_re), ((u8 *)vsb_taps_re), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_BNTHRESH__A, 330, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* set higher threshold */ + rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_CLPLASTNUM__A, 90, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* burst detection on */ + rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_SNRTH_RCA1__A, 0x0042, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* drop thresholds by 1 dB */ + rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_SNRTH_RCA2__A, 0x0053, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* drop thresholds by 2 dB */ + rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_EQCTRL__A, 0x1, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* cma on */ + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_GPIO__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* GPIO */ /* Initialize the FEC Subsystem */ - WR16(dev_addr, FEC_TOP_ANNEX__A, FEC_TOP_ANNEX_D); + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_TOP_ANNEX__A, FEC_TOP_ANNEX_D, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } { u16 fec_oc_snc_mode = 0; - RR16(dev_addr, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode); + rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* output data even when not locked */ - WR16(dev_addr, FEC_OC_SNC_MODE__A, - fec_oc_snc_mode | FEC_OC_SNC_MODE_UNLOCK_ENABLE__M); + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_SNC_MODE__A, fec_oc_snc_mode | FEC_OC_SNC_MODE_UNLOCK_ENABLE__M, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } /* set clip */ - WR16(dev_addr, IQM_AF_CLP_LEN__A, 0); - WR16(dev_addr, IQM_AF_CLP_TH__A, 470); - WR16(dev_addr, IQM_AF_SNS_LEN__A, 0); - WR16(dev_addr, VSB_TOP_SNRTH_PT__A, 0xD4); + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_CLP_LEN__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_CLP_TH__A, 470, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_SNS_LEN__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_SNRTH_PT__A, 0xD4, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* no transparent, no A&C framing; parity is set in mpegoutput */ { u16 fec_oc_reg_mode = 0; - RR16(dev_addr, FEC_OC_MODE__A, &fec_oc_reg_mode); - WR16(dev_addr, FEC_OC_MODE__A, fec_oc_reg_mode & - (~(FEC_OC_MODE_TRANSPARENT__M - | FEC_OC_MODE_CLEAR__M | FEC_OC_MODE_RETAIN_FRAMING__M) - )); + rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_OC_MODE__A, &fec_oc_reg_mode, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_MODE__A, fec_oc_reg_mode & (~(FEC_OC_MODE_TRANSPARENT__M | FEC_OC_MODE_CLEAR__M | FEC_OC_MODE_RETAIN_FRAMING__M)), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } - WR16(dev_addr, FEC_DI_TIMEOUT_LO__A, 0); /* timeout counter for restarting */ - WR16(dev_addr, FEC_DI_TIMEOUT_HI__A, 3); - WR16(dev_addr, FEC_RS_MODE__A, 0); /* bypass disabled */ + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_DI_TIMEOUT_LO__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* timeout counter for restarting */ + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_DI_TIMEOUT_HI__A, 3, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_RS_MODE__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* bypass disabled */ /* initialize RS packet error measurement parameters */ - WR16(dev_addr, FEC_RS_MEASUREMENT_PERIOD__A, FEC_RS_MEASUREMENT_PERIOD); - WR16(dev_addr, FEC_RS_MEASUREMENT_PRESCALE__A, - FEC_RS_MEASUREMENT_PRESCALE); + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_RS_MEASUREMENT_PERIOD__A, FEC_RS_MEASUREMENT_PERIOD, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_RS_MEASUREMENT_PRESCALE__A, FEC_RS_MEASUREMENT_PRESCALE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* init measurement period of MER/SER */ - WR16(dev_addr, VSB_TOP_MEASUREMENT_PERIOD__A, - VSB_TOP_MEASUREMENT_PERIOD); - WR32(dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0); - WR16(dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, 0); - WR16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0); + rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_MEASUREMENT_PERIOD__A, VSB_TOP_MEASUREMENT_PERIOD, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg32func(dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } - WR16(dev_addr, VSB_TOP_CKGN1TRK__A, 128); + rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_CKGN1TRK__A, 128, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* B-Input to ADC, PGA+filter in standby */ if (ext_attr->has_lna == false) { - WR16(dev_addr, IQM_AF_AMUX__A, 0x02); + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_AMUX__A, 0x02, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } }; /* turn on IQMAF. It has to be in front of setAgc**() */ - CHK_ERROR(set_iqm_af(demod, true)); - CHK_ERROR(adc_synchronization(demod)); + rc = set_iqm_af(demod, true); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = adc_synchronization(demod); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } - CHK_ERROR(init_agc(demod)); - CHK_ERROR(set_agc_if(demod, &(ext_attr->vsb_if_agc_cfg), false)); - CHK_ERROR(set_agc_rf(demod, &(ext_attr->vsb_rf_agc_cfg), false)); + rc = init_agc(demod); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = set_agc_if(demod, &(ext_attr->vsb_if_agc_cfg), false); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = set_agc_rf(demod, &(ext_attr->vsb_rf_agc_cfg), false); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } { /* TODO fix this, store a struct drxj_cfg_afe_gain structure in struct drxj_data instead of only the gain */ struct drxj_cfg_afe_gain vsb_pga_cfg = { DRX_STANDARD_8VSB, 0 }; vsb_pga_cfg.gain = ext_attr->vsb_pga_cfg; - CHK_ERROR(ctrl_set_cfg_afe_gain(demod, &vsb_pga_cfg)); + rc = ctrl_set_cfg_afe_gain(demod, &vsb_pga_cfg); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->vsb_pre_saw_cfg)); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; } - CHK_ERROR(ctrl_set_cfg_pre_saw(demod, &(ext_attr->vsb_pre_saw_cfg))); /* Mpeg output has to be in front of FEC active */ - CHK_ERROR(set_mpegtei_handling(demod)); - CHK_ERROR(bit_reverse_mpeg_output(demod)); - CHK_ERROR(set_mpeg_start_width(demod)); + rc = set_mpegtei_handling(demod); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = bit_reverse_mpeg_output(demod); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = set_mpeg_start_width(demod); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } { /* TODO: move to set_standard after hardware reset value problem is solved */ /* Configure initial MPEG output */ @@ -6020,7 +7509,11 @@ static int set_vsb(struct drx_demod_instance *demod) cfg_mpeg_output.invert_clk = common_attr->mpeg_cfg.invert_clk; cfg_mpeg_output.static_clk = common_attr->mpeg_cfg.static_clk; cfg_mpeg_output.bitrate = common_attr->mpeg_cfg.bitrate; - CHK_ERROR(ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output)); + rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } /* TBD: what parameters should be set */ @@ -6031,30 +7524,81 @@ static int set_vsb(struct drx_demod_instance *demod) cmd_scu.result_len = 1; cmd_scu.parameter = &cmd_param; cmd_scu.result = &cmd_result; - CHK_ERROR(scu_command(dev_addr, &cmd_scu)); - - WR16(dev_addr, VSB_TOP_BEAGC_GAINSHIFT__A, 0x0004); - WR16(dev_addr, VSB_TOP_SNRTH_PT__A, 0x00D2); - WR16(dev_addr, VSB_TOP_SYSSMTRNCTRL__A, VSB_TOP_SYSSMTRNCTRL__PRE - | VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__M); - WR16(dev_addr, VSB_TOP_BEDETCTRL__A, 0x142); - WR16(dev_addr, VSB_TOP_LBAGCREFLVL__A, 640); - WR16(dev_addr, VSB_TOP_CYGN1ACQ__A, 4); - WR16(dev_addr, VSB_TOP_CYGN1TRK__A, 2); - WR16(dev_addr, VSB_TOP_CYGN2TRK__A, 3); + rc = scu_command(dev_addr, &cmd_scu); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } - /* start demodulator */ - cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB - | SCU_RAM_COMMAND_CMD_DEMOD_START; + rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_BEAGC_GAINSHIFT__A, 0x0004, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_SNRTH_PT__A, 0x00D2, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_SYSSMTRNCTRL__A, VSB_TOP_SYSSMTRNCTRL__PRE | VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__M, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_BEDETCTRL__A, 0x142, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_LBAGCREFLVL__A, 640, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_CYGN1ACQ__A, 4, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_CYGN1TRK__A, 2, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_CYGN2TRK__A, 3, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* start demodulator */ + cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB + | SCU_RAM_COMMAND_CMD_DEMOD_START; cmd_scu.parameter_len = 0; cmd_scu.result_len = 1; cmd_scu.parameter = NULL; cmd_scu.result = &cmd_result; - CHK_ERROR(scu_command(dev_addr, &cmd_scu)); + rc = scu_command(dev_addr, &cmd_scu); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } - WR16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE); - WR16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_ACTIVE); - WR16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE); + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_ACTIVE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } return (DRX_STS_OK); rw_error: @@ -6068,13 +7612,18 @@ rw_error: */ static int get_vsb_post_rs_pck_err(struct i2c_device_addr *dev_addr, u16 *pck_errs) { + int rc; u16 data = 0; u16 period = 0; u16 prescale = 0; u16 packet_errorsMant = 0; u16 packet_errorsExp = 0; - RR16(dev_addr, FEC_RS_NR_FAILURES__A, &data); + rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_RS_NR_FAILURES__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } packet_errorsMant = data & FEC_RS_NR_FAILURES_FIXED_MANT__M; packet_errorsExp = (data & FEC_RS_NR_FAILURES_EXP__M) >> FEC_RS_NR_FAILURES_EXP__B; @@ -6082,7 +7631,10 @@ static int get_vsb_post_rs_pck_err(struct i2c_device_addr *dev_addr, u16 *pck_er prescale = FEC_RS_MEASUREMENT_PRESCALE; /* packet error rate = (error packet number) per second */ /* 77.3 us is time for per packet */ - CHK_ZERO(period * prescale); + if (period * prescale == 0) { + pr_err("error: period and/or prescale is zero!\n"); + return DRX_STS_ERROR;; + } *pck_errs = (u16) frac_times1e6(packet_errorsMant * (1 << packet_errorsExp), (period * prescale * 77)); @@ -6099,13 +7651,18 @@ rw_error: */ static int get_vs_bpost_viterbi_ber(struct i2c_device_addr *dev_addr, u32 *ber) { + int rc; u16 data = 0; u16 period = 0; u16 prescale = 0; u16 bit_errors_mant = 0; u16 bit_errors_exp = 0; - RR16(dev_addr, FEC_RS_NR_BIT_ERRORS__A, &data); + rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_RS_NR_BIT_ERRORS__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } period = FEC_RS_MEASUREMENT_PERIOD; prescale = FEC_RS_MEASUREMENT_PRESCALE; @@ -6116,7 +7673,10 @@ static int get_vs_bpost_viterbi_ber(struct i2c_device_addr *dev_addr, u32 *ber) if (((bit_errors_mant << bit_errors_exp) >> 3) > 68700) *ber = 26570; else { - CHK_ZERO(period * prescale); + if (period * prescale == 0) { + pr_err("error: period and/or prescale is zero!\n"); + return DRX_STS_ERROR;; + } *ber = frac_times1e6(bit_errors_mant << ((bit_errors_exp > @@ -6138,8 +7698,13 @@ rw_error: static int get_vs_bpre_viterbi_ber(struct i2c_device_addr *dev_addr, u32 *ber) { u16 data = 0; + int rc; - RR16(dev_addr, VSB_TOP_NR_SYM_ERRS__A, &data); + rc = DRXJ_DAP.read_reg16func(dev_addr, VSB_TOP_NR_SYM_ERRS__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } *ber = frac_times1e6(data, VSB_TOP_MEASUREMENT_PERIOD * SYMBOLS_PER_SEGMENT); @@ -6156,13 +7721,18 @@ rw_error: */ static int get_vsb_symb_err(struct i2c_device_addr *dev_addr, u32 *ser) { + int rc; u16 data = 0; u16 period = 0; u16 prescale = 0; u16 symb_errors_mant = 0; u16 symb_errors_exp = 0; - RR16(dev_addr, FEC_RS_NR_SYMBOL_ERRORS__A, &data); + rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_RS_NR_SYMBOL_ERRORS__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } period = FEC_RS_MEASUREMENT_PERIOD; prescale = FEC_RS_MEASUREMENT_PRESCALE; @@ -6170,7 +7740,10 @@ static int get_vsb_symb_err(struct i2c_device_addr *dev_addr, u32 *ser) symb_errors_exp = (data & FEC_RS_NR_SYMBOL_ERRORS_EXP__M) >> FEC_RS_NR_SYMBOL_ERRORS_EXP__B; - CHK_ZERO(period * prescale); + if (period * prescale == 0) { + pr_err("error: period and/or prescale is zero!\n"); + return DRX_STS_ERROR;; + } *ser = (u32) frac_times1e6((symb_errors_mant << symb_errors_exp) * 1000, (period * prescale * 77318)); @@ -6186,9 +7759,14 @@ rw_error: */ static int get_vsbmer(struct i2c_device_addr *dev_addr, u16 *mer) { + int rc; u16 data_hi = 0; - RR16(dev_addr, VSB_TOP_ERR_ENERGY_H__A, &data_hi); + rc = DRXJ_DAP.read_reg16func(dev_addr, VSB_TOP_ERR_ENERGY_H__A, &data_hi, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } *mer = (u16) (log1_times100(21504) - log1_times100((data_hi << 6) / 52)); @@ -6210,6 +7788,7 @@ static int ctrl_get_vsb_constel(struct drx_demod_instance *demod, struct drx_complex *complex_nr) { struct i2c_device_addr *dev_addr = NULL; + int rc; /**< device address */ u16 vsb_top_comm_mb = 0; /**< VSB SL MB configuration */ u16 vsb_top_comm_mbInit = 0; /**< VSB SL MB intial configuration */ @@ -6224,21 +7803,41 @@ ctrl_get_vsb_constel(struct drx_demod_instance *demod, struct drx_complex *compl /* Needs to be checked when external interface PG is updated */ /* Configure MB (Monitor bus) */ - RR16(dev_addr, VSB_TOP_COMM_MB__A, &vsb_top_comm_mbInit); + rc = DRXJ_DAP.read_reg16func(dev_addr, VSB_TOP_COMM_MB__A, &vsb_top_comm_mbInit, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* set observe flag & MB mux */ vsb_top_comm_mb = (vsb_top_comm_mbInit | VSB_TOP_COMM_MB_OBS_OBS_ON | VSB_TOP_COMM_MB_MUX_OBS_VSB_TCMEQ_2); - WR16(dev_addr, VSB_TOP_COMM_MB__A, vsb_top_comm_mb); + rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_COMM_MB__A, vsb_top_comm_mb, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Enable MB grabber in the FEC OC */ - WR16(dev_addr, FEC_OC_OCR_MODE__A, FEC_OC_OCR_MODE_GRAB_ENABLE__M); + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_OCR_MODE__A, FEC_OC_OCR_MODE_GRAB_ENABLE__M, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Disable MB grabber in the FEC OC */ - WR16(dev_addr, FEC_OC_OCR_MODE__A, 0x0); + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_OCR_MODE__A, 0x0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* read data */ - RR32(dev_addr, FEC_OC_OCR_GRAB_RD1__A, &data); + rc = DRXJ_DAP.read_reg32func(dev_addr, FEC_OC_OCR_GRAB_RD1__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } re = (u16) (((data >> 10) & 0x300) | ((data >> 2) & 0xff)); if (re & 0x0200) { re |= 0xfc00; @@ -6247,7 +7846,11 @@ ctrl_get_vsb_constel(struct drx_demod_instance *demod, struct drx_complex *compl complex_nr->im = 0; /* Restore MB (Monitor bus) */ - WR16(dev_addr, VSB_TOP_COMM_MB__A, vsb_top_comm_mbInit); + rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_COMM_MB__A, vsb_top_comm_mbInit, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } return (DRX_STS_OK); rw_error: @@ -6279,17 +7882,26 @@ static int power_down_qam(struct drx_demod_instance *demod, bool primary) /* *parameter */ NULL, /* *result */ NULL }; - u16 cmd_result = 0; + int rc; struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; struct drx_cfg_mpeg_output cfg_mpeg_output; + u16 cmd_result = 0; /* STOP demodulator resets IQM, QAM and FEC HW blocks */ /* stop all comm_exec */ - WR16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP); - WR16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP); + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_STOP; @@ -6297,21 +7909,57 @@ static int power_down_qam(struct drx_demod_instance *demod, bool primary) cmd_scu.result_len = 1; cmd_scu.parameter = NULL; cmd_scu.result = &cmd_result; - CHK_ERROR(scu_command(dev_addr, &cmd_scu)); + rc = scu_command(dev_addr, &cmd_scu); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if (primary == true) { - WR16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP); - CHK_ERROR(set_iqm_af(demod, false)); + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = set_iqm_af(demod, false); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } else { - WR16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP); - WR16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP); - WR16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP); - WR16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP); - WR16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP); + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } cfg_mpeg_output.enable_mpeg_output = false; - CHK_ERROR(ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output)); + rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } return (DRX_STS_OK); rw_error: @@ -6343,6 +7991,7 @@ set_qam_measurement(struct drx_demod_instance *demod, { struct i2c_device_addr *dev_addr = NULL; /* device address for I2C writes */ struct drxj_data *ext_attr = NULL; /* Global data container for DRXJ specif data */ + int rc; u32 fec_bits_desired = 0; /* BER accounting period */ u16 fec_rs_plen = 0; /* defines RS BER measurement period */ u16 fec_rs_prescale = 0; /* ReedSolomon Measurement Prescale */ @@ -6401,7 +8050,10 @@ set_qam_measurement(struct drx_demod_instance *demod, ext_attr->fec_rs_plen = fec_rs_plen; /* for getSigQual */ fec_rs_bit_cnt = fec_rs_prescale * fec_rs_plen; /* temp storage */ - CHK_ZERO(fec_rs_bit_cnt); + if (fec_rs_bit_cnt == 0) { + pr_err("error: fec_rs_bit_cnt is zero!\n"); + return DRX_STS_ERROR;; + } fec_rs_period = fec_bits_desired / fec_rs_bit_cnt + 1; /* ceil */ if (ext_attr->standard != DRX_STANDARD_ITU_B) fec_oc_snc_fail_period = fec_rs_period; @@ -6433,14 +8085,38 @@ set_qam_measurement(struct drx_demod_instance *demod, return (DRX_STS_INVALID_ARG); } - WR16(dev_addr, FEC_OC_SNC_FAIL_PERIOD__A, (u16) fec_oc_snc_fail_period); - WR16(dev_addr, FEC_RS_MEASUREMENT_PERIOD__A, (u16) fec_rs_period); - WR16(dev_addr, FEC_RS_MEASUREMENT_PRESCALE__A, fec_rs_prescale); + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_SNC_FAIL_PERIOD__A, (u16)fec_oc_snc_fail_period, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_RS_MEASUREMENT_PERIOD__A, (u16)fec_rs_period, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_RS_MEASUREMENT_PRESCALE__A, fec_rs_prescale, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } ext_attr->fec_rs_period = (u16) fec_rs_period; ext_attr->fec_rs_prescale = fec_rs_prescale; - WR32(dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0); - WR16(dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, 0); - WR16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0); + rc = DRXJ_DAP.write_reg32func(dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if (ext_attr->standard == DRX_STANDARD_ITU_B) { /* Parameters for Viterbi Decoder */ @@ -6471,7 +8147,10 @@ set_qam_measurement(struct drx_demod_instance *demod, default: return (DRX_STS_INVALID_ARG); } - CHK_ZERO(qam_vd_period); + if (qam_vd_period == 0) { + pr_err("error: qam_vd_period is zero!\n"); + return DRX_STS_ERROR;; + } qam_vd_period = fec_bits_desired / qam_vd_period; /* limit to max 16 bit value (I2C register width) if needed */ if (qam_vd_period > 0xFFFF) @@ -6480,9 +8159,16 @@ set_qam_measurement(struct drx_demod_instance *demod, /* a(16 bit) * b(16 bit) = 32 bit result => mult32 not needed */ qam_vd_bit_cnt *= qam_vd_period; - WR16(dev_addr, QAM_VD_MEASUREMENT_PERIOD__A, - (u16) qam_vd_period); - WR16(dev_addr, QAM_VD_MEASUREMENT_PRESCALE__A, qam_vd_prescale); + rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_VD_MEASUREMENT_PERIOD__A, (u16)qam_vd_period, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_VD_MEASUREMENT_PRESCALE__A, qam_vd_prescale, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } ext_attr->qam_vd_period = (u16) qam_vd_period; ext_attr->qam_vd_prescale = qam_vd_prescale; } @@ -6503,6 +8189,7 @@ rw_error: static int set_qam16(struct drx_demod_instance *demod) { struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + int rc; const u8 qam_dq_qual_fun[] = { DRXJ_16TO8(2), /* fun0 */ DRXJ_16TO8(2), /* fun1 */ @@ -6520,52 +8207,206 @@ static int set_qam16(struct drx_demod_instance *demod) DRXJ_16TO8(13517), /* RAD5 */ }; - WRB(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), - ((u8 *)qam_dq_qual_fun)); - WRB(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), - ((u8 *)qam_eq_cma_rad)); - - WR16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 140); - WR16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 50); - WR16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 120); - WR16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 230); - WR16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 95); - WR16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 105); - - WR16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); - WR16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56); - WR16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3); - - WR16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 16); - WR16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 220); - WR16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 25); - WR16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 6); - WR16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) (-24)); - WR16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) (-65)); - WR16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) (-127)); - - WR16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15); - WR16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40); - WR16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2); - WR16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20); - WR16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255); - WR16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2); - WR16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10); - WR16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 50); - WR16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12); - WR16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); - WR16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24); - WR16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12); - WR16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); - WR16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16); - WR16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16); - WR16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32); - WR16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 240); - WR16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5); - WR16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15); - WR16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32); - - WR16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 40960); + rc = DRXJ_DAP.write_block_func(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_block_func(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 140, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 50, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 120, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 230, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 95, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 105, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 16, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 220, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 25, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 6, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-24), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-65), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-127), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 50, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 240, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 40960, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } return (DRX_STS_OK); rw_error: @@ -6583,6 +8424,7 @@ rw_error: static int set_qam32(struct drx_demod_instance *demod) { struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + int rc; const u8 qam_dq_qual_fun[] = { DRXJ_16TO8(3), /* fun0 */ DRXJ_16TO8(3), /* fun1 */ @@ -6600,52 +8442,206 @@ static int set_qam32(struct drx_demod_instance *demod) DRXJ_16TO8(6707), /* RAD5 */ }; - WRB(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), - ((u8 *)qam_dq_qual_fun)); - WRB(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), - ((u8 *)qam_eq_cma_rad)); - - WR16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 90); - WR16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 50); - WR16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100); - WR16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 170); - WR16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80); - WR16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 100); - - WR16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); - WR16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56); - WR16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3); - - WR16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12); - WR16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 140); - WR16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) (-8)); - WR16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) (-16)); - WR16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) (-26)); - WR16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) (-56)); - WR16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) (-86)); - - WR16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15); - WR16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40); - WR16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2); - WR16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20); - WR16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255); - WR16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2); - WR16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10); - WR16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 50); - WR16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12); - WR16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); - WR16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24); - WR16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12); - WR16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); - WR16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16); - WR16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16); - WR16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32); - WR16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 176); - WR16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5); - WR16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15); - WR16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 8); - - WR16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 20480); + rc = DRXJ_DAP.write_block_func(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_block_func(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 90, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 50, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 170, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 100, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 140, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16)(-8), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16)(-16), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-26), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-56), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-86), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 50, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 176, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 8, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 20480, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } return (DRX_STS_OK); rw_error: @@ -6663,6 +8659,7 @@ rw_error: static int set_qam64(struct drx_demod_instance *demod) { struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + int rc; const u8 qam_dq_qual_fun[] = { /* this is hw reset value. no necessary to re-write */ DRXJ_16TO8(4), /* fun0 */ DRXJ_16TO8(4), /* fun1 */ @@ -6680,52 +8677,206 @@ static int set_qam64(struct drx_demod_instance *demod) DRXJ_16TO8(15609), /* RAD5 */ }; - WRB(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), - ((u8 *)qam_dq_qual_fun)); - WRB(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), - ((u8 *)qam_eq_cma_rad)); - - WR16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 105); - WR16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60); - WR16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100); - WR16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 195); - WR16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80); - WR16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 84); - - WR16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); - WR16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32); - WR16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3); - - WR16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12); - WR16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 141); - WR16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 7); - WR16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 0); - WR16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) (-15)); - WR16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) (-45)); - WR16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) (-80)); - - WR16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15); - WR16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40); - WR16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2); - WR16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30); - WR16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255); - WR16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2); - WR16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 15); - WR16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80); - WR16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12); - WR16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); - WR16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24); - WR16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12); - WR16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); - WR16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16); - WR16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16); - WR16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48); - WR16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 160); - WR16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5); - WR16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15); - WR16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32); - - WR16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 43008); + rc = DRXJ_DAP.write_block_func(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_block_func(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 105, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 195, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 84, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 141, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 7, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-15), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-45), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-80), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 15, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 160, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 43008, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } return (DRX_STS_OK); rw_error: @@ -6743,6 +8894,7 @@ rw_error: static int set_qam128(struct drx_demod_instance *demod) { struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + int rc; const u8 qam_dq_qual_fun[] = { DRXJ_16TO8(6), /* fun0 */ DRXJ_16TO8(6), /* fun1 */ @@ -6760,52 +8912,206 @@ static int set_qam128(struct drx_demod_instance *demod) DRXJ_16TO8(7238), /* RAD5 */ }; - WRB(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), - ((u8 *)qam_dq_qual_fun)); - WRB(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), - ((u8 *)qam_eq_cma_rad)); - - WR16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 50); - WR16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60); - WR16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100); - WR16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 140); - WR16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80); - WR16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 100); - - WR16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); - WR16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32); - WR16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3); - - WR16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8); - WR16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 65); - WR16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 5); - WR16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 3); - WR16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) (-1)); - WR16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 12); - WR16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) (-23)); - - WR16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15); - WR16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40); - WR16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2); - WR16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40); - WR16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255); - WR16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2); - WR16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20); - WR16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80); - WR16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12); - WR16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); - WR16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24); - WR16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12); - WR16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); - WR16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16); - WR16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16); - WR16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32); - WR16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 144); - WR16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5); - WR16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15); - WR16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16); - - WR16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 20992); + rc = DRXJ_DAP.write_block_func(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_block_func(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 50, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 140, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 100, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 65, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 5, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 3, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-1), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 12, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-23), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 144, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 20992, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } return (DRX_STS_OK); rw_error: @@ -6823,6 +9129,7 @@ rw_error: static int set_qam256(struct drx_demod_instance *demod) { struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + int rc; const u8 qam_dq_qual_fun[] = { DRXJ_16TO8(8), /* fun0 */ DRXJ_16TO8(8), /* fun1 */ @@ -6840,52 +9147,206 @@ static int set_qam256(struct drx_demod_instance *demod) DRXJ_16TO8(15356), /* RAD5 */ }; - WRB(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), - ((u8 *)qam_dq_qual_fun)); - WRB(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), - ((u8 *)qam_eq_cma_rad)); - - WR16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 50); - WR16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60); - WR16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100); - WR16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 150); - WR16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80); - WR16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 110); - - WR16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); - WR16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 16); - WR16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3); - - WR16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8); - WR16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 74); - WR16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 18); - WR16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 13); - WR16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, 7); - WR16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 0); - WR16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) (-8)); - - WR16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15); - WR16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40); - WR16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2); - WR16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50); - WR16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255); - WR16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2); - WR16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 25); - WR16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80); - WR16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12); - WR16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); - WR16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24); - WR16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12); - WR16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); - WR16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16); - WR16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16); - WR16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48); - WR16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 80); - WR16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5); - WR16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15); - WR16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16); - - WR16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 43520); + rc = DRXJ_DAP.write_block_func(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_block_func(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 50, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 150, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 110, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 16, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 74, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 18, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 13, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, 7, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-8), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 25, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 80, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 43520, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } return (DRX_STS_OK); rw_error: @@ -6911,9 +9372,10 @@ set_qam(struct drx_demod_instance *demod, struct i2c_device_addr *dev_addr = NULL; struct drxj_data *ext_attr = NULL; struct drx_common_attr *common_attr = NULL; - u16 cmd_result = 0; + int rc; u32 adc_frequency = 0; u32 iqm_rc_rate = 0; + u16 cmd_result = 0; u16 lc_symbol_freq = 0; u16 iqm_rc_stretch = 0; u16 set_env_parameters = 0; @@ -7070,7 +9532,10 @@ set_qam(struct drx_demod_instance *demod, } } else { adc_frequency = (common_attr->sys_clock_freq * 1000) / 3; - CHK_ZERO(channel->symbolrate); + if (channel->symbolrate == 0) { + pr_err("error: channel symbolrate is zero!\n"); + return DRX_STS_ERROR;; + } iqm_rc_rate = (adc_frequency / channel->symbolrate) * (1 << 21) + (frac28 @@ -7111,13 +9576,41 @@ set_qam(struct drx_demod_instance *demod, resets SCU variables */ /* stop all comm_exec */ - WR16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP); - WR16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP); - WR16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP); - WR16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP); - WR16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP); - WR16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP); - WR16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP); + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_RESET; @@ -7125,7 +9618,11 @@ set_qam(struct drx_demod_instance *demod, cmd_scu.result_len = 1; cmd_scu.parameter = NULL; cmd_scu.result = &cmd_result; - CHK_ERROR(scu_command(dev_addr, &cmd_scu)); + rc = scu_command(dev_addr, &cmd_scu); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) { @@ -7140,7 +9637,11 @@ set_qam(struct drx_demod_instance *demod, cmd_scu.result_len = 1; cmd_scu.parameter = &set_env_parameters; cmd_scu.result = &cmd_result; - CHK_ERROR(scu_command(dev_addr, &cmd_scu)); + rc = scu_command(dev_addr, &cmd_scu); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM; @@ -7148,168 +9649,457 @@ set_qam(struct drx_demod_instance *demod, cmd_scu.result_len = 1; cmd_scu.parameter = set_param_parameters; cmd_scu.result = &cmd_result; - CHK_ERROR(scu_command(dev_addr, &cmd_scu)); + rc = scu_command(dev_addr, &cmd_scu); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* set symbol rate */ - WR32(dev_addr, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate); + rc = DRXJ_DAP.write_reg32func(dev_addr, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } ext_attr->iqm_rc_rate_ofs = iqm_rc_rate; - CHK_ERROR(set_qam_measurement - (demod, channel->constellation, channel->symbolrate)); + rc = set_qam_measurement(demod, channel->constellation, channel->symbolrate); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } /* STEP 3: enable the system in a mode where the ADC provides valid signal setup constellation independent registers */ /* from qam_cmd.py script (qam_driver_b) */ /* TODO: remove re-writes of HW reset values */ if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_SPECTRUM)) { - CHK_ERROR(set_frequency(demod, channel, tuner_freq_offset)); + rc = set_frequency(demod, channel, tuner_freq_offset); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) { - WR16(dev_addr, QAM_LC_SYMBOL_FREQ__A, lc_symbol_freq); - WR16(dev_addr, IQM_RC_STRETCH__A, iqm_rc_stretch); + rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_SYMBOL_FREQ__A, lc_symbol_freq, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RC_STRETCH__A, iqm_rc_stretch, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } if (op & QAM_SET_OP_ALL) { if (ext_attr->has_lna == false) { - WR16(dev_addr, IQM_AF_AMUX__A, 0x02); + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_AMUX__A, 0x02, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_SYMMETRIC__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_MIDTAP__A, 3, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_QAM__M, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; } - WR16(dev_addr, IQM_CF_SYMMETRIC__A, 0); - WR16(dev_addr, IQM_CF_MIDTAP__A, 3); - WR16(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_QAM__M); - - WR16(dev_addr, SCU_RAM_QAM_WR_RSV_0__A, 0x5f); /* scu temporary shut down agc */ - WR16(dev_addr, IQM_AF_SYNC_SEL__A, 3); - WR16(dev_addr, IQM_AF_CLP_LEN__A, 0); - WR16(dev_addr, IQM_AF_CLP_TH__A, 448); - WR16(dev_addr, IQM_AF_SNS_LEN__A, 0); - WR16(dev_addr, IQM_AF_PDREF__A, 4); - WR16(dev_addr, IQM_AF_STDBY__A, 0x10); - WR16(dev_addr, IQM_AF_PGA_GAIN__A, 11); + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_WR_RSV_0__A, 0x5f, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* scu temporary shut down agc */ - WR16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 1); - WR16(dev_addr, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE); /*! reset default val ! */ + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_SYNC_SEL__A, 3, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_CLP_LEN__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_CLP_TH__A, 448, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_SNS_LEN__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_PDREF__A, 4, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_STDBY__A, 0x10, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_PGA_GAIN__A, 11, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } - WR16(dev_addr, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE); /*! reset default val ! */ + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_POW_MEAS_LEN__A, 1, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /*! reset default val ! */ + + rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /*! reset default val ! */ if (ext_attr->standard == DRX_STANDARD_ITU_B) { - WR16(dev_addr, QAM_SY_SYNC_LWM__A, QAM_SY_SYNC_LWM__PRE); /*! reset default val ! */ - WR16(dev_addr, QAM_SY_SYNC_AWM__A, QAM_SY_SYNC_AWM__PRE); /*! reset default val ! */ - WR16(dev_addr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE); /*! reset default val ! */ + rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_SY_SYNC_LWM__A, QAM_SY_SYNC_LWM__PRE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /*! reset default val ! */ + rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_SY_SYNC_AWM__A, QAM_SY_SYNC_AWM__PRE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /*! reset default val ! */ + rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /*! reset default val ! */ } else { switch (channel->constellation) { case DRX_CONSTELLATION_QAM16: case DRX_CONSTELLATION_QAM64: case DRX_CONSTELLATION_QAM256: - WR16(dev_addr, QAM_SY_SYNC_LWM__A, 0x03); - WR16(dev_addr, QAM_SY_SYNC_AWM__A, 0x04); - WR16(dev_addr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE); /*! reset default val ! */ + rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_SY_SYNC_LWM__A, 0x03, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_SY_SYNC_AWM__A, 0x04, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /*! reset default val ! */ break; case DRX_CONSTELLATION_QAM32: case DRX_CONSTELLATION_QAM128: - WR16(dev_addr, QAM_SY_SYNC_LWM__A, 0x03); - WR16(dev_addr, QAM_SY_SYNC_AWM__A, 0x05); - WR16(dev_addr, QAM_SY_SYNC_HWM__A, 0x06); + rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_SY_SYNC_LWM__A, 0x03, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_SY_SYNC_AWM__A, 0x05, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_SY_SYNC_HWM__A, 0x06, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } break; default: return (DRX_STS_ERROR); } /* switch */ } - WR16(dev_addr, QAM_LC_MODE__A, QAM_LC_MODE__PRE); /*! reset default val ! */ - WR16(dev_addr, QAM_LC_RATE_LIMIT__A, 3); - WR16(dev_addr, QAM_LC_LPF_FACTORP__A, 4); - WR16(dev_addr, QAM_LC_LPF_FACTORI__A, 4); - WR16(dev_addr, QAM_LC_MODE__A, 7); - WR16(dev_addr, QAM_LC_QUAL_TAB0__A, 1); - WR16(dev_addr, QAM_LC_QUAL_TAB1__A, 1); - WR16(dev_addr, QAM_LC_QUAL_TAB2__A, 1); - WR16(dev_addr, QAM_LC_QUAL_TAB3__A, 1); - WR16(dev_addr, QAM_LC_QUAL_TAB4__A, 2); - WR16(dev_addr, QAM_LC_QUAL_TAB5__A, 2); - WR16(dev_addr, QAM_LC_QUAL_TAB6__A, 2); - WR16(dev_addr, QAM_LC_QUAL_TAB8__A, 2); - WR16(dev_addr, QAM_LC_QUAL_TAB9__A, 2); - WR16(dev_addr, QAM_LC_QUAL_TAB10__A, 2); - WR16(dev_addr, QAM_LC_QUAL_TAB12__A, 2); - WR16(dev_addr, QAM_LC_QUAL_TAB15__A, 3); - WR16(dev_addr, QAM_LC_QUAL_TAB16__A, 3); - WR16(dev_addr, QAM_LC_QUAL_TAB20__A, 4); - WR16(dev_addr, QAM_LC_QUAL_TAB25__A, 4); - - WR16(dev_addr, IQM_FS_ADJ_SEL__A, 1); - WR16(dev_addr, IQM_RC_ADJ_SEL__A, 1); - WR16(dev_addr, IQM_CF_ADJ_SEL__A, 1); - WR16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 0); - WR16(dev_addr, SCU_RAM_GPIO__A, 0); + rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_MODE__A, QAM_LC_MODE__PRE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /*! reset default val ! */ + rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_RATE_LIMIT__A, 3, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_LPF_FACTORP__A, 4, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_LPF_FACTORI__A, 4, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_MODE__A, 7, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_QUAL_TAB0__A, 1, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_QUAL_TAB1__A, 1, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_QUAL_TAB2__A, 1, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_QUAL_TAB3__A, 1, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_QUAL_TAB4__A, 2, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_QUAL_TAB5__A, 2, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_QUAL_TAB6__A, 2, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_QUAL_TAB8__A, 2, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_QUAL_TAB9__A, 2, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_QUAL_TAB10__A, 2, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_QUAL_TAB12__A, 2, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_QUAL_TAB15__A, 3, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_QUAL_TAB16__A, 3, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_QUAL_TAB20__A, 4, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_QUAL_TAB25__A, 4, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_FS_ADJ_SEL__A, 1, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RC_ADJ_SEL__A, 1, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_ADJ_SEL__A, 1, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_POW_MEAS_LEN__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_GPIO__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* No more resets of the IQM, current standard correctly set => now AGCs can be configured. */ /* turn on IQMAF. It has to be in front of setAgc**() */ - CHK_ERROR(set_iqm_af(demod, true)); - CHK_ERROR(adc_synchronization(demod)); + rc = set_iqm_af(demod, true); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = adc_synchronization(demod); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } - CHK_ERROR(init_agc(demod)); - CHK_ERROR(set_agc_if(demod, &(ext_attr->qam_if_agc_cfg), false)); - CHK_ERROR(set_agc_rf(demod, &(ext_attr->qam_rf_agc_cfg), false)); + rc = init_agc(demod); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = set_agc_if(demod, &(ext_attr->qam_if_agc_cfg), false); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = set_agc_rf(demod, &(ext_attr->qam_rf_agc_cfg), false); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } { /* TODO fix this, store a struct drxj_cfg_afe_gain structure in struct drxj_data instead of only the gain */ struct drxj_cfg_afe_gain qam_pga_cfg = { DRX_STANDARD_ITU_B, 0 }; qam_pga_cfg.gain = ext_attr->qam_pga_cfg; - CHK_ERROR(ctrl_set_cfg_afe_gain(demod, &qam_pga_cfg)); + rc = ctrl_set_cfg_afe_gain(demod, &qam_pga_cfg); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->qam_pre_saw_cfg)); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; } - CHK_ERROR(ctrl_set_cfg_pre_saw(demod, &(ext_attr->qam_pre_saw_cfg))); } if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) { if (ext_attr->standard == DRX_STANDARD_ITU_A) { - WRB(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_a_taps), - ((u8 *)qam_a_taps)); - WRB(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_a_taps), - ((u8 *)qam_a_taps)); + rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_a_taps), ((u8 *)qam_a_taps), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_a_taps), ((u8 *)qam_a_taps), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } else if (ext_attr->standard == DRX_STANDARD_ITU_B) { switch (channel->constellation) { case DRX_CONSTELLATION_QAM64: - WRB(dev_addr, IQM_CF_TAP_RE0__A, - sizeof(qam_b64_taps), ((u8 *)qam_b64_taps)); - WRB(dev_addr, IQM_CF_TAP_IM0__A, - sizeof(qam_b64_taps), ((u8 *)qam_b64_taps)); + rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_b64_taps), ((u8 *)qam_b64_taps), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_b64_taps), ((u8 *)qam_b64_taps), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } break; case DRX_CONSTELLATION_QAM256: - WRB(dev_addr, IQM_CF_TAP_RE0__A, - sizeof(qam_b256_taps), - ((u8 *)qam_b256_taps)); - WRB(dev_addr, IQM_CF_TAP_IM0__A, - sizeof(qam_b256_taps), - ((u8 *)qam_b256_taps)); + rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_b256_taps), ((u8 *)qam_b256_taps), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_b256_taps), ((u8 *)qam_b256_taps), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } break; default: return (DRX_STS_ERROR); } } else if (ext_attr->standard == DRX_STANDARD_ITU_C) { - WRB(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_c_taps), - ((u8 *)qam_c_taps)); - WRB(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_c_taps), - ((u8 *)qam_c_taps)); + rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_c_taps), ((u8 *)qam_c_taps), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_c_taps), ((u8 *)qam_c_taps), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } /* SETP 4: constellation specific setup */ switch (channel->constellation) { case DRX_CONSTELLATION_QAM16: - CHK_ERROR(set_qam16(demod)); + rc = set_qam16(demod); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } break; case DRX_CONSTELLATION_QAM32: - CHK_ERROR(set_qam32(demod)); + rc = set_qam32(demod); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } break; case DRX_CONSTELLATION_QAM64: - CHK_ERROR(set_qam64(demod)); + rc = set_qam64(demod); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } break; case DRX_CONSTELLATION_QAM128: - CHK_ERROR(set_qam128(demod)); + rc = set_qam128(demod); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } break; case DRX_CONSTELLATION_QAM256: - CHK_ERROR(set_qam256(demod)); + rc = set_qam256(demod); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } break; default: return (DRX_STS_ERROR); @@ -7317,12 +10107,28 @@ set_qam(struct drx_demod_instance *demod, } if ((op & QAM_SET_OP_ALL)) { - WR16(dev_addr, IQM_CF_SCALE_SH__A, 0); + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_SCALE_SH__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Mpeg output has to be in front of FEC active */ - CHK_ERROR(set_mpegtei_handling(demod)); - CHK_ERROR(bit_reverse_mpeg_output(demod)); - CHK_ERROR(set_mpeg_start_width(demod)); + rc = set_mpegtei_handling(demod); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = bit_reverse_mpeg_output(demod); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = set_mpeg_start_width(demod); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } { /* TODO: move to set_standard after hardware reset value problem is solved */ /* Configure initial MPEG output */ @@ -7341,7 +10147,11 @@ set_qam(struct drx_demod_instance *demod, cfg_mpeg_output.invert_clk = common_attr->mpeg_cfg.invert_clk; cfg_mpeg_output.static_clk = common_attr->mpeg_cfg.static_clk; cfg_mpeg_output.bitrate = common_attr->mpeg_cfg.bitrate; - CHK_ERROR(ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output)); + rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } } @@ -7354,12 +10164,28 @@ set_qam(struct drx_demod_instance *demod, cmd_scu.result_len = 1; cmd_scu.parameter = NULL; cmd_scu.result = &cmd_result; - CHK_ERROR(scu_command(dev_addr, &cmd_scu)); + rc = scu_command(dev_addr, &cmd_scu); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } - WR16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE); - WR16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE); - WR16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE); + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } return (DRX_STS_OK); rw_error: @@ -7371,6 +10197,7 @@ static int ctrl_get_qam_sig_quality(struct drx_demod_instance *demod, struct drx_sig_quality *sig_quality); static int qam_flip_spec(struct drx_demod_instance *demod, struct drx_channel *channel) { + int rc; u32 iqm_fs_rate_ofs = 0; u32 iqm_fs_rate_lo = 0; u16 qam_ctl_ena = 0; @@ -7386,65 +10213,163 @@ static int qam_flip_spec(struct drx_demod_instance *demod, struct drx_channel *c ext_attr = (struct drxj_data *) demod->my_ext_attr; /* Silence the controlling of lc, equ, and the acquisition state machine */ - RR16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, &qam_ctl_ena); - WR16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, qam_ctl_ena - & ~(SCU_RAM_QAM_CTL_ENA_ACQ__M - | SCU_RAM_QAM_CTL_ENA_EQU__M | SCU_RAM_QAM_CTL_ENA_LC__M)); + rc = DRXJ_DAP.read_reg16func(dev_addr, SCU_RAM_QAM_CTL_ENA__A, &qam_ctl_ena, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_CTL_ENA__A, qam_ctl_ena & ~(SCU_RAM_QAM_CTL_ENA_ACQ__M | SCU_RAM_QAM_CTL_ENA_EQU__M | SCU_RAM_QAM_CTL_ENA_LC__M), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* freeze the frequency control loop */ - WR16(dev_addr, QAM_LC_CF__A, 0); - WR16(dev_addr, QAM_LC_CF1__A, 0); + rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_CF__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_CF1__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } - ARR32(dev_addr, IQM_FS_RATE_OFS_LO__A, &iqm_fs_rate_ofs); - ARR32(dev_addr, IQM_FS_RATE_LO__A, &iqm_fs_rate_lo); + rc = drxj_dap_atomic_read_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, &iqm_fs_rate_ofs, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_atomic_read_reg32(dev_addr, IQM_FS_RATE_LO__A, &iqm_fs_rate_lo, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } ofsofs = iqm_fs_rate_lo - iqm_fs_rate_ofs; iqm_fs_rate_ofs = ~iqm_fs_rate_ofs + 1; iqm_fs_rate_ofs -= 2 * ofsofs; /* freeze dq/fq updating */ - RR16(dev_addr, QAM_DQ_MODE__A, &data); + rc = DRXJ_DAP.read_reg16func(dev_addr, QAM_DQ_MODE__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } data = (data & 0xfff9); - WR16(dev_addr, QAM_DQ_MODE__A, data); - WR16(dev_addr, QAM_FQ_MODE__A, data); + rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_DQ_MODE__A, data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_FQ_MODE__A, data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* lc_cp / _ci / _ca */ - WR16(dev_addr, QAM_LC_CI__A, 0); - WR16(dev_addr, QAM_LC_EP__A, 0); - WR16(dev_addr, QAM_FQ_LA_FACTOR__A, 0); + rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_CI__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_EP__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_FQ_LA_FACTOR__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* flip the spec */ - WR32(dev_addr, IQM_FS_RATE_OFS_LO__A, iqm_fs_rate_ofs); + rc = DRXJ_DAP.write_reg32func(dev_addr, IQM_FS_RATE_OFS_LO__A, iqm_fs_rate_ofs, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } ext_attr->iqm_fs_rate_ofs = iqm_fs_rate_ofs; ext_attr->pos_image = (ext_attr->pos_image) ? false : true; /* freeze dq/fq updating */ - RR16(dev_addr, QAM_DQ_MODE__A, &data); + rc = DRXJ_DAP.read_reg16func(dev_addr, QAM_DQ_MODE__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } equ_mode = data; data = (data & 0xfff9); - WR16(dev_addr, QAM_DQ_MODE__A, data); - WR16(dev_addr, QAM_FQ_MODE__A, data); + rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_DQ_MODE__A, data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_FQ_MODE__A, data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } for (i = 0; i < 28; i++) { - RR16(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), &data); - WR16(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), -data); + rc = DRXJ_DAP.read_reg16func(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), -data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } for (i = 0; i < 24; i++) { - RR16(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), &data); - WR16(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), -data); + rc = DRXJ_DAP.read_reg16func(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), -data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } data = equ_mode; - WR16(dev_addr, QAM_DQ_MODE__A, data); - WR16(dev_addr, QAM_FQ_MODE__A, data); + rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_DQ_MODE__A, data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_FQ_MODE__A, data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } - WR16(dev_addr, SCU_RAM_QAM_FSM_STATE_TGT__A, 4); + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_STATE_TGT__A, 4, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } i = 0; while ((fsm_state != 4) && (i++ < 100)) { - RR16(dev_addr, SCU_RAM_QAM_FSM_STATE__A, &fsm_state); + rc = DRXJ_DAP.read_reg16func(dev_addr, SCU_RAM_QAM_FSM_STATE__A, &fsm_state, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_CTL_ENA__A, (qam_ctl_ena | 0x0016), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; } - WR16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, (qam_ctl_ena | 0x0016)); return (DRX_STS_OK); rw_error: @@ -7471,12 +10396,13 @@ qam64auto(struct drx_demod_instance *demod, s32 tuner_freq_offset, enum drx_lock_status *lock_status) { struct drx_sig_quality sig_quality; - u16 data = 0; + struct drxj_data *ext_attr = NULL; + int rc; u32 state = NO_LOCK; u32 start_time = 0; u32 d_locked_time = 0; - struct drxj_data *ext_attr = NULL; u32 timeout_ofs = 0; + u16 data = 0; /* external attributes for storing aquired channel constellation */ ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -7484,13 +10410,20 @@ qam64auto(struct drx_demod_instance *demod, start_time = drxbsp_hst_clock(); state = NO_LOCK; do { - CHK_ERROR(ctrl_lock_status(demod, lock_status)); + rc = ctrl_lock_status(demod, lock_status); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } switch (state) { case NO_LOCK: if (*lock_status == DRXJ_DEMOD_LOCK) { - CHK_ERROR(ctrl_get_qam_sig_quality - (demod, &sig_quality)); + rc = ctrl_get_qam_sig_quality(demod, &sig_quality); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if (sig_quality.MER > 208) { state = DEMOD_LOCKED; /* some delay to see if fec_lock possible TODO find the right value */ @@ -7503,10 +10436,16 @@ qam64auto(struct drx_demod_instance *demod, if ((*lock_status == DRXJ_DEMOD_LOCK) && /* still demod_lock in 150ms */ ((drxbsp_hst_clock() - d_locked_time) > DRXJ_QAM_FEC_LOCK_WAITTIME)) { - RR16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, - &data); - WR16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, - data | 0x1); + rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } state = SYNC_FLIPPED; drxbsp_hst_sleep(10); } @@ -7515,13 +10454,23 @@ qam64auto(struct drx_demod_instance *demod, if (*lock_status == DRXJ_DEMOD_LOCK) { if (channel->mirror == DRX_MIRROR_AUTO) { /* flip sync pattern back */ - RR16(demod->my_i2c_dev_addr, - QAM_SY_TIMEOUT__A, &data); - WR16(demod->my_i2c_dev_addr, - QAM_SY_TIMEOUT__A, data & 0xFFFE); + rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data & 0xFFFE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* flip spectrum */ ext_attr->mirror = DRX_MIRROR_YES; - CHK_ERROR(qam_flip_spec(demod, channel)); + rc = qam_flip_spec(demod, channel); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } state = SPEC_MIRRORED; /* reset timer TODO: still need 500ms? */ start_time = d_locked_time = @@ -7539,13 +10488,22 @@ qam64auto(struct drx_demod_instance *demod, if ((*lock_status == DRXJ_DEMOD_LOCK) && /* still demod_lock in 150ms */ ((drxbsp_hst_clock() - d_locked_time) > DRXJ_QAM_FEC_LOCK_WAITTIME)) { - CHK_ERROR(ctrl_get_qam_sig_quality - (demod, &sig_quality)); + rc = ctrl_get_qam_sig_quality(demod, &sig_quality); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if (sig_quality.MER > 208) { - RR16(demod->my_i2c_dev_addr, - QAM_SY_TIMEOUT__A, &data); - WR16(demod->my_i2c_dev_addr, - QAM_SY_TIMEOUT__A, data | 0x1); + rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* no need to wait lock */ start_time = drxbsp_hst_clock() - @@ -7585,10 +10543,11 @@ qam256auto(struct drx_demod_instance *demod, s32 tuner_freq_offset, enum drx_lock_status *lock_status) { struct drx_sig_quality sig_quality; + struct drxj_data *ext_attr = NULL; + int rc; u32 state = NO_LOCK; u32 start_time = 0; u32 d_locked_time = 0; - struct drxj_data *ext_attr = NULL; u32 timeout_ofs = DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME; /* external attributes for storing aquired channel constellation */ @@ -7597,12 +10556,19 @@ qam256auto(struct drx_demod_instance *demod, start_time = drxbsp_hst_clock(); state = NO_LOCK; do { - CHK_ERROR(ctrl_lock_status(demod, lock_status)); + rc = ctrl_lock_status(demod, lock_status); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } switch (state) { case NO_LOCK: if (*lock_status == DRXJ_DEMOD_LOCK) { - CHK_ERROR(ctrl_get_qam_sig_quality - (demod, &sig_quality)); + rc = ctrl_get_qam_sig_quality(demod, &sig_quality); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if (sig_quality.MER > 268) { state = DEMOD_LOCKED; timeout_ofs += DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME; /* see something, wait longer */ @@ -7616,7 +10582,11 @@ qam256auto(struct drx_demod_instance *demod, ((drxbsp_hst_clock() - d_locked_time) > DRXJ_QAM_FEC_LOCK_WAITTIME)) { ext_attr->mirror = DRX_MIRROR_YES; - CHK_ERROR(qam_flip_spec(demod, channel)); + rc = qam_flip_spec(demod, channel); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } state = SPEC_MIRRORED; /* reset timer TODO: still need 300ms? */ start_time = drxbsp_hst_clock(); @@ -7652,8 +10622,9 @@ static int set_qamChannel(struct drx_demod_instance *demod, struct drx_channel *channel, s32 tuner_freq_offset) { - enum drx_lock_status lock_status = DRX_NOT_LOCKED; struct drxj_data *ext_attr = NULL; + int rc; + enum drx_lock_status lock_status = DRX_NOT_LOCKED; bool auto_flag = false; /* external attributes for storing aquired channel constellation */ @@ -7672,22 +10643,29 @@ set_qamChannel(struct drx_demod_instance *demod, } else { ext_attr->mirror = channel->mirror; } - CHK_ERROR(set_qam - (demod, channel, tuner_freq_offset, QAM_SET_OP_ALL)); + rc = set_qam(demod, channel, tuner_freq_offset, QAM_SET_OP_ALL); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if ((ext_attr->standard == DRX_STANDARD_ITU_B) && (channel->constellation == DRX_CONSTELLATION_QAM64)) { - CHK_ERROR(qam64auto - (demod, channel, tuner_freq_offset, - &lock_status)); + rc = qam64auto(demod, channel, tuner_freq_offset, &lock_status); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } if ((ext_attr->standard == DRX_STANDARD_ITU_B) && (channel->mirror == DRX_MIRROR_AUTO) && (channel->constellation == DRX_CONSTELLATION_QAM256)) { - CHK_ERROR(qam256auto - (demod, channel, tuner_freq_offset, - &lock_status)); + rc = qam256auto(demod, channel, tuner_freq_offset, &lock_status); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } break; case DRX_CONSTELLATION_AUTO: /* for channel scan */ @@ -7701,12 +10679,16 @@ set_qamChannel(struct drx_demod_instance *demod, } else { ext_attr->mirror = channel->mirror; } - CHK_ERROR(set_qam - (demod, channel, tuner_freq_offset, - QAM_SET_OP_ALL)); - CHK_ERROR(qam256auto - (demod, channel, tuner_freq_offset, - &lock_status)); + rc = set_qam(demod, channel, tuner_freq_offset, QAM_SET_OP_ALL); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = qam256auto(demod, channel, tuner_freq_offset, &lock_status); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if (lock_status < DRX_LOCKED) { /* QAM254 not locked -> try to lock QAM64 constellation */ @@ -7721,25 +10703,38 @@ set_qamChannel(struct drx_demod_instance *demod, } { u16 qam_ctl_ena = 0; - RR16(demod->my_i2c_dev_addr, - SCU_RAM_QAM_CTL_ENA__A, - &qam_ctl_ena); - WR16(demod->my_i2c_dev_addr, - SCU_RAM_QAM_CTL_ENA__A, - qam_ctl_ena & - ~SCU_RAM_QAM_CTL_ENA_ACQ__M); - WR16(demod->my_i2c_dev_addr, SCU_RAM_QAM_FSM_STATE_TGT__A, 0x2); /* force to rate hunting */ - - CHK_ERROR(set_qam - (demod, channel, - tuner_freq_offset, - QAM_SET_OP_CONSTELLATION)); - WR16(demod->my_i2c_dev_addr, - SCU_RAM_QAM_CTL_ENA__A, qam_ctl_ena); + rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SCU_RAM_QAM_CTL_ENA__A, &qam_ctl_ena, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SCU_RAM_QAM_CTL_ENA__A, qam_ctl_ena & ~SCU_RAM_QAM_CTL_ENA_ACQ__M, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SCU_RAM_QAM_FSM_STATE_TGT__A, 0x2, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* force to rate hunting */ + + rc = set_qam(demod, channel, tuner_freq_offset, QAM_SET_OP_CONSTELLATION); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SCU_RAM_QAM_CTL_ENA__A, qam_ctl_ena, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + rc = qam64auto(demod, channel, tuner_freq_offset, &lock_status); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; } - CHK_ERROR(qam64auto - (demod, channel, tuner_freq_offset, - &lock_status)); } channel->constellation = DRX_CONSTELLATION_AUTO; } else if (ext_attr->standard == DRX_STANDARD_ITU_C) { @@ -7754,22 +10749,38 @@ set_qamChannel(struct drx_demod_instance *demod, } { u16 qam_ctl_ena = 0; - RR16(demod->my_i2c_dev_addr, - SCU_RAM_QAM_CTL_ENA__A, &qam_ctl_ena); - WR16(demod->my_i2c_dev_addr, - SCU_RAM_QAM_CTL_ENA__A, - qam_ctl_ena & ~SCU_RAM_QAM_CTL_ENA_ACQ__M); - WR16(demod->my_i2c_dev_addr, SCU_RAM_QAM_FSM_STATE_TGT__A, 0x2); /* force to rate hunting */ - - CHK_ERROR(set_qam - (demod, channel, tuner_freq_offset, - QAM_SET_OP_CONSTELLATION)); - WR16(demod->my_i2c_dev_addr, - SCU_RAM_QAM_CTL_ENA__A, qam_ctl_ena); - } - CHK_ERROR(qam64auto - (demod, channel, tuner_freq_offset, - &lock_status)); + rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SCU_RAM_QAM_CTL_ENA__A, &qam_ctl_ena, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SCU_RAM_QAM_CTL_ENA__A, qam_ctl_ena & ~SCU_RAM_QAM_CTL_ENA_ACQ__M, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SCU_RAM_QAM_FSM_STATE_TGT__A, 0x2, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* force to rate hunting */ + + rc = set_qam(demod, channel, tuner_freq_offset, QAM_SET_OP_CONSTELLATION); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SCU_RAM_QAM_CTL_ENA__A, qam_ctl_ena, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + rc = qam64auto(demod, channel, tuner_freq_offset, &lock_status); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } channel->constellation = DRX_CONSTELLATION_AUTO; } else { channel->constellation = DRX_CONSTELLATION_AUTO; @@ -7801,6 +10812,7 @@ rw_error: static int GetQAMRSErr_count(struct i2c_device_addr *dev_addr, struct drxjrs_errors *rs_errors) { + int rc; u16 nr_bit_errors = 0, nr_symbol_errors = 0, nr_packet_errors = 0, nr_failures = 0, nr_snc_par_fail_count = 0; @@ -7813,15 +10825,35 @@ GetQAMRSErr_count(struct i2c_device_addr *dev_addr, struct drxjrs_errors *rs_err /* all reported errors are received in the */ /* most recently finished measurment period */ /* no of pre RS bit errors */ - RR16(dev_addr, FEC_RS_NR_BIT_ERRORS__A, &nr_bit_errors); + rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_RS_NR_BIT_ERRORS__A, &nr_bit_errors, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* no of symbol errors */ - RR16(dev_addr, FEC_RS_NR_SYMBOL_ERRORS__A, &nr_symbol_errors); + rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_RS_NR_SYMBOL_ERRORS__A, &nr_symbol_errors, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* no of packet errors */ - RR16(dev_addr, FEC_RS_NR_PACKET_ERRORS__A, &nr_packet_errors); + rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_RS_NR_PACKET_ERRORS__A, &nr_packet_errors, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* no of failures to decode */ - RR16(dev_addr, FEC_RS_NR_FAILURES__A, &nr_failures); + rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_RS_NR_FAILURES__A, &nr_failures, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* no of post RS bit erros */ - RR16(dev_addr, FEC_OC_SNC_FAIL_COUNT__A, &nr_snc_par_fail_count); + rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_OC_SNC_FAIL_COUNT__A, &nr_snc_par_fail_count, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* TODO: NOTE */ /* These register values are fetched in non-atomic fashion */ /* It is possible that the read values contain unrelated information */ @@ -7857,6 +10889,7 @@ ctrl_get_qam_sig_quality(struct drx_demod_instance *demod, struct drx_sig_qualit { struct i2c_device_addr *dev_addr = NULL; struct drxj_data *ext_attr = NULL; + int rc; enum drx_modulation constellation = DRX_CONSTELLATION_UNKNOWN; struct drxjrs_errors measuredrs_errors = { 0, 0, 0, 0, 0 }; @@ -7891,11 +10924,23 @@ ctrl_get_qam_sig_quality(struct drx_demod_instance *demod, struct drx_sig_qualit /* read the physical registers */ /* Get the RS error data */ - CHK_ERROR(GetQAMRSErr_count(dev_addr, &measuredrs_errors)); + rc = GetQAMRSErr_count(dev_addr, &measuredrs_errors); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* get the register value needed for MER */ - RR16(dev_addr, QAM_SL_ERR_POWER__A, &qam_sl_err_power); + rc = DRXJ_DAP.read_reg16func(dev_addr, QAM_SL_ERR_POWER__A, &qam_sl_err_power, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* get the register value needed for post RS BER */ - RR16(dev_addr, FEC_OC_SNC_FAIL_PERIOD__A, &fec_oc_period); + rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_OC_SNC_FAIL_PERIOD__A, &fec_oc_period, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* get constants needed for signal quality calculation */ fec_rs_period = ext_attr->fec_rs_period; @@ -7946,7 +10991,11 @@ ctrl_get_qam_sig_quality(struct drx_demod_instance *demod, struct drx_sig_qualit /* get the register value */ /* no of quadrature symbol errors */ - RR16(dev_addr, QAM_VD_NR_QSYM_ERRORS__A, &qsym_err_vd); + rc = DRXJ_DAP.read_reg16func(dev_addr, QAM_VD_NR_QSYM_ERRORS__A, &qsym_err_vd, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Extract the Exponent and the Mantisa */ /* of number of quadrature symbol errors */ e = (qsym_err_vd & QAM_VD_NR_QSYM_ERRORS_EXP__M) >> @@ -8016,7 +11065,11 @@ ctrl_get_qam_sig_quality(struct drx_demod_instance *demod, struct drx_sig_qualit sig_quality->post_reed_solomon_ber = qam_post_rs_ber; sig_quality->scale_factor_ber = ((u32) 1000000); #ifdef DRXJ_SIGNAL_ACCUM_ERR - CHK_ERROR(get_acc_pkt_err(demod, &sig_quality->packet_error)); + rc = get_acc_pkt_err(demod, &sig_quality->packet_error); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } #else sig_quality->packet_error = ((u16) pkt_errs); #endif @@ -8037,6 +11090,9 @@ rw_error: static int ctrl_get_qam_constel(struct drx_demod_instance *demod, struct drx_complex *complex_nr) { + struct i2c_device_addr *dev_addr = NULL; + int rc; + u32 data = 0; u16 fec_oc_ocr_mode = 0; /**< FEC OCR grabber configuration */ u16 qam_sl_comm_mb = 0;/**< QAM SL MB configuration */ @@ -8044,8 +11100,6 @@ ctrl_get_qam_constel(struct drx_demod_instance *demod, struct drx_complex *compl /**< QAM SL MB intial configuration */ u16 im = 0; /**< constellation Im part */ u16 re = 0; /**< constellation Re part */ - u32 data = 0; - struct i2c_device_addr *dev_addr = NULL; /**< device address */ /* read device info */ @@ -8056,13 +11110,21 @@ ctrl_get_qam_constel(struct drx_demod_instance *demod, struct drx_complex *compl /* Needs to be checked when external interface PG is updated */ /* Configure MB (Monitor bus) */ - RR16(dev_addr, QAM_SL_COMM_MB__A, &qam_sl_comm_mbInit); + rc = DRXJ_DAP.read_reg16func(dev_addr, QAM_SL_COMM_MB__A, &qam_sl_comm_mbInit, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* set observe flag & MB mux */ qam_sl_comm_mb = qam_sl_comm_mbInit & (~(QAM_SL_COMM_MB_OBS__M + QAM_SL_COMM_MB_MUX_OBS__M)); qam_sl_comm_mb |= (QAM_SL_COMM_MB_OBS_ON + QAM_SL_COMM_MB_MUX_OBS_CONST_CORR); - WR16(dev_addr, QAM_SL_COMM_MB__A, qam_sl_comm_mb); + rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_SL_COMM_MB__A, qam_sl_comm_mb, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Enable MB grabber in the FEC OC */ fec_oc_ocr_mode = (/* output select: observe bus */ @@ -8077,13 +11139,25 @@ ctrl_get_qam_constel(struct drx_demod_instance *demod, struct drx_complex *compl /* grabber mode: continuous */ (FEC_OC_OCR_MODE_GRAB_COUNTED__M & (0x0 << FEC_OC_OCR_MODE_GRAB_COUNTED__B))); - WR16(dev_addr, FEC_OC_OCR_MODE__A, fec_oc_ocr_mode); + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_OCR_MODE__A, fec_oc_ocr_mode, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Disable MB grabber in the FEC OC */ - WR16(dev_addr, FEC_OC_OCR_MODE__A, 0x00); + rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_OCR_MODE__A, 0x00, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* read data */ - RR32(dev_addr, FEC_OC_OCR_GRAB_RD0__A, &data); + rc = DRXJ_DAP.read_reg32func(dev_addr, FEC_OC_OCR_GRAB_RD0__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } re = (u16) (data & FEC_OC_OCR_GRAB_RD0__M); im = (u16) ((data >> 16) & FEC_OC_OCR_GRAB_RD1__M); @@ -8101,7 +11175,11 @@ ctrl_get_qam_constel(struct drx_demod_instance *demod, struct drx_complex *compl complex_nr->im = ((s16) im); /* Restore MB (Monitor bus) */ - WR16(dev_addr, QAM_SL_COMM_MB__A, qam_sl_comm_mbInit); + rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_SL_COMM_MB__A, qam_sl_comm_mbInit, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } return (DRX_STS_OK); rw_error: @@ -8229,6 +11307,7 @@ atv_update_config(struct drx_demod_instance *demod, bool force_update) { struct i2c_device_addr *dev_addr = NULL; struct drxj_data *ext_attr = NULL; + int rc; dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -8238,37 +11317,73 @@ atv_update_config(struct drx_demod_instance *demod, bool force_update) ((ext_attr->atv_cfg_changed_flags & DRXJ_ATV_CHANGED_COEF) != 0)) { int index = 0; - CHK_ERROR(atv_equ_coef_index(ext_attr->standard, &index)); - WR16(dev_addr, ATV_TOP_EQU0__A, ext_attr->atv_top_equ0[index]); - WR16(dev_addr, ATV_TOP_EQU1__A, ext_attr->atv_top_equ1[index]); - WR16(dev_addr, ATV_TOP_EQU2__A, ext_attr->atv_top_equ2[index]); - WR16(dev_addr, ATV_TOP_EQU3__A, ext_attr->atv_top_equ3[index]); + rc = atv_equ_coef_index(ext_attr->standard, &index); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_EQU0__A, ext_attr->atv_top_equ0[index], 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_EQU1__A, ext_attr->atv_top_equ1[index], 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_EQU2__A, ext_attr->atv_top_equ2[index], 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_EQU3__A, ext_attr->atv_top_equ3[index], 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } /* bypass fast carrier recovery */ if (force_update) { u16 data = 0; - RR16(dev_addr, IQM_RT_ROT_BP__A, &data); + rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_RT_ROT_BP__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } data &= (~((u16) IQM_RT_ROT_BP_ROT_OFF__M)); if (ext_attr->phase_correction_bypass) { data |= IQM_RT_ROT_BP_ROT_OFF_OFF; } else { data |= IQM_RT_ROT_BP_ROT_OFF_ACTIVE; } - WR16(dev_addr, IQM_RT_ROT_BP__A, data); + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_ROT_BP__A, data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } /* peak filter setting */ if (force_update || ((ext_attr->atv_cfg_changed_flags & DRXJ_ATV_CHANGED_PEAK_FLT) != 0)) { - WR16(dev_addr, ATV_TOP_VID_PEAK__A, ext_attr->atv_top_vid_peak); + rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_VID_PEAK__A, ext_attr->atv_top_vid_peak, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } /* noise filter setting */ if (force_update || ((ext_attr->atv_cfg_changed_flags & DRXJ_ATV_CHANGED_NOISE_FLT) != 0)) { - WR16(dev_addr, ATV_TOP_NOISE_TH__A, ext_attr->atv_top_noise_th); + rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_NOISE_TH__A, ext_attr->atv_top_noise_th, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } /* SIF attenuation */ @@ -8293,7 +11408,11 @@ atv_update_config(struct drx_demod_instance *demod, bool force_update) return DRX_STS_ERROR; break; } - WR16(dev_addr, ATV_TOP_AF_SIF_ATT__A, attenuation); + rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_AF_SIF_ATT__A, attenuation, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } /* SIF & CVBS enable */ @@ -8301,7 +11420,11 @@ atv_update_config(struct drx_demod_instance *demod, bool force_update) ((ext_attr->atv_cfg_changed_flags & DRXJ_ATV_CHANGED_OUTPUT) != 0)) { u16 data = 0; - RR16(dev_addr, ATV_TOP_STDBY__A, &data); + rc = DRXJ_DAP.read_reg16func(dev_addr, ATV_TOP_STDBY__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if (ext_attr->enable_cvbs_output) { data |= ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE; } else { @@ -8313,7 +11436,11 @@ atv_update_config(struct drx_demod_instance *demod, bool force_update) } else { data |= ATV_TOP_STDBY_SIF_STDBY_STANDBY; } - WR16(dev_addr, ATV_TOP_STDBY__A, data); + rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_STDBY__A, data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } ext_attr->atv_cfg_changed_flags = 0; @@ -8336,6 +11463,7 @@ static int ctrl_set_cfg_atv_output(struct drx_demod_instance *demod, struct drxj_cfg_atv_output *output_cfg) { struct drxj_data *ext_attr = NULL; + int rc; /* Check arguments */ if (output_cfg == NULL) { @@ -8372,7 +11500,11 @@ ctrl_set_cfg_atv_output(struct drx_demod_instance *demod, struct drxj_cfg_atv_ou ext_attr->atv_cfg_changed_flags |= DRXJ_ATV_CHANGED_OUTPUT; } - CHK_ERROR(atv_update_config(demod, false)); + rc = atv_update_config(demod, false); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } return (DRX_STS_OK); rw_error: @@ -8393,6 +11525,7 @@ static int ctrl_set_cfg_atv_equ_coef(struct drx_demod_instance *demod, struct drxj_cfg_atv_equ_coef *coef) { struct drxj_data *ext_attr = NULL; + int rc; int index; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -8415,14 +11548,22 @@ ctrl_set_cfg_atv_equ_coef(struct drx_demod_instance *demod, struct drxj_cfg_atv_ return (DRX_STS_INVALID_ARG); } - CHK_ERROR(atv_equ_coef_index(ext_attr->standard, &index)); + rc = atv_equ_coef_index(ext_attr->standard, &index); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } ext_attr->atv_top_equ0[index] = coef->coef0; ext_attr->atv_top_equ1[index] = coef->coef1; ext_attr->atv_top_equ2[index] = coef->coef2; ext_attr->atv_top_equ3[index] = coef->coef3; ext_attr->atv_cfg_changed_flags |= DRXJ_ATV_CHANGED_COEF; - CHK_ERROR(atv_update_config(demod, false)); + rc = atv_update_config(demod, false); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } return (DRX_STS_OK); rw_error: @@ -8447,6 +11588,7 @@ static int ctrl_get_cfg_atv_equ_coef(struct drx_demod_instance *demod, struct drxj_cfg_atv_equ_coef *coef) { struct drxj_data *ext_attr = NULL; + int rc; int index = 0; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -8461,7 +11603,11 @@ ctrl_get_cfg_atv_equ_coef(struct drx_demod_instance *demod, struct drxj_cfg_atv_ return DRX_STS_INVALID_ARG; } - CHK_ERROR(atv_equ_coef_index(ext_attr->standard, &index)); + rc = atv_equ_coef_index(ext_attr->standard, &index); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } coef->coef0 = ext_attr->atv_top_equ0[index]; coef->coef1 = ext_attr->atv_top_equ1[index]; coef->coef2 = ext_attr->atv_top_equ2[index]; @@ -8485,6 +11631,7 @@ static int ctrl_set_cfg_atv_misc(struct drx_demod_instance *demod, struct drxj_cfg_atv_misc *settings) { struct drxj_data *ext_attr = NULL; + int rc; /* Check arguments */ if ((settings == NULL) || @@ -8506,7 +11653,11 @@ ctrl_set_cfg_atv_misc(struct drx_demod_instance *demod, struct drxj_cfg_atv_misc ext_attr->atv_cfg_changed_flags |= DRXJ_ATV_CHANGED_NOISE_FLT; } - CHK_ERROR(atv_update_config(demod, false)); + rc = atv_update_config(demod, false); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } return (DRX_STS_OK); rw_error: @@ -8532,9 +11683,8 @@ ctrl_get_cfg_atv_misc(struct drx_demod_instance *demod, struct drxj_cfg_atv_misc struct drxj_data *ext_attr = NULL; /* Check arguments */ - if (settings == NULL) { + if (settings == NULL) return DRX_STS_INVALID_ARG; - } ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -8558,6 +11708,7 @@ ctrl_get_cfg_atv_misc(struct drx_demod_instance *demod, struct drxj_cfg_atv_misc static int ctrl_get_cfg_atv_output(struct drx_demod_instance *demod, struct drxj_cfg_atv_output *output_cfg) { + int rc; u16 data = 0; /* Check arguments */ @@ -8565,7 +11716,11 @@ ctrl_get_cfg_atv_output(struct drx_demod_instance *demod, struct drxj_cfg_atv_ou return DRX_STS_INVALID_ARG; } - RR16(demod->my_i2c_dev_addr, ATV_TOP_STDBY__A, &data); + rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, ATV_TOP_STDBY__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if (data & ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE) { output_cfg->enable_cvbs_output = true; } else { @@ -8576,7 +11731,11 @@ ctrl_get_cfg_atv_output(struct drx_demod_instance *demod, struct drxj_cfg_atv_ou output_cfg->enable_sif_output = false; } else { output_cfg->enable_sif_output = true; - RR16(demod->my_i2c_dev_addr, ATV_TOP_AF_SIF_ATT__A, &data); + rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, ATV_TOP_AF_SIF_ATT__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } output_cfg->sif_attenuation = (enum drxjsif_attenuation) data; } @@ -8599,6 +11758,7 @@ ctrl_get_cfg_atv_agc_status(struct drx_demod_instance *demod, struct drxj_cfg_atv_agc_status *agc_status) { struct i2c_device_addr *dev_addr = NULL; + int rc; u16 data = 0; u32 tmp = 0; @@ -8614,7 +11774,11 @@ ctrl_get_cfg_atv_agc_status(struct drx_demod_instance *demod, IQM_AF_AGC_RF__A * 27 is 20 bits worst case. */ - RR16(dev_addr, IQM_AF_AGC_RF__A, &data); + rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_AGC_RF__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } tmp = ((u32) data) * 27 - ((u32) (data >> 2)); /* nA */ agc_status->rf_agc_gain = (u16) (tmp / 1000); /* uA */ /* rounding */ @@ -8628,7 +11792,11 @@ ctrl_get_cfg_atv_agc_status(struct drx_demod_instance *demod, IQM_AF_AGC_IF__A * 27 is 20 bits worst case. */ - RR16(dev_addr, IQM_AF_AGC_IF__A, &data); + rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_AGC_IF__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } tmp = ((u32) data) * 27 - ((u32) (data >> 2)); /* nA */ agc_status->if_agc_gain = (u16) (tmp / 1000); /* uA */ /* rounding */ @@ -8644,7 +11812,11 @@ ctrl_get_cfg_atv_agc_status(struct drx_demod_instance *demod, = (ATV_TOP_SFR_VID_GAIN__A/32) - 75 (in 0.1 dB) */ - SARR16(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, &data); + rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* dividing by 32 inclusive rounding */ data >>= 4; if ((data & 1) != 0) { @@ -8661,7 +11833,11 @@ ctrl_get_cfg_atv_agc_status(struct drx_demod_instance *demod, = (SCU_RAM_ATV_SIF_GAIN__A/2) - 4 (in 0.1 dB) */ - SARR16(dev_addr, SCU_RAM_ATV_SIF_GAIN__A, &data); + rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_ATV_SIF_GAIN__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } data &= SCU_RAM_ATV_SIF_GAIN__M; /* dividing by 2 inclusive rounding */ if ((data & 1) != 0) { @@ -8671,7 +11847,11 @@ ctrl_get_cfg_atv_agc_status(struct drx_demod_instance *demod, agc_status->audio_agc_gain = ((s16) data) - 4; /* 0.1 dB */ /* Loop gain's */ - SARR16(dev_addr, SCU_RAM_AGC_KI__A, &data); + rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } agc_status->video_agc_loop_gain = ((data & SCU_RAM_AGC_KI_DGAIN__M) >> SCU_RAM_AGC_KI_DGAIN__B); agc_status->rf_agc_loop_gain = @@ -8699,14 +11879,31 @@ rw_error: static int power_up_atv(struct drx_demod_instance *demod, enum drx_standard standard) { struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + int rc; /* ATV NTSC */ - WR16(dev_addr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_ACTIVE); + rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_ACTIVE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* turn on IQM_AF */ - CHK_ERROR(set_iqm_af(demod, true)); - CHK_ERROR(adc_synchronization(demod)); + rc = set_iqm_af(demod, true); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = adc_synchronization(demod); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } - WR16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE); + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Audio, already done during set standard */ @@ -8739,6 +11936,7 @@ power_down_atv(struct drx_demod_instance *demod, enum drx_standard standard, boo /* *parameter */ NULL, /* *result */ NULL }; + int rc; u16 cmd_result = 0; /* ATV NTSC */ @@ -8750,23 +11948,66 @@ power_down_atv(struct drx_demod_instance *demod, enum drx_standard standard, boo cmd_scu.result_len = 1; cmd_scu.parameter = NULL; cmd_scu.result = &cmd_result; - CHK_ERROR(scu_command(dev_addr, &cmd_scu)); + rc = scu_command(dev_addr, &cmd_scu); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Disable ATV outputs (ATV reset enables CVBS, undo this) */ - WR16(dev_addr, ATV_TOP_STDBY__A, (ATV_TOP_STDBY_SIF_STDBY_STANDBY & - (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE))); + rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_STDBY__A, (ATV_TOP_STDBY_SIF_STDBY_STANDBY & (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE)), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } - WR16(dev_addr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_STOP); + rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_STOP, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if (primary == true) { - WR16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP); - CHK_ERROR(set_iqm_af(demod, false)); + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = set_iqm_af(demod, false); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } else { - WR16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP); - WR16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP); - WR16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP); - WR16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP); - WR16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP); + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + rc = power_down_aud(demod); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; } - CHK_ERROR(power_down_aud(demod)); return (DRX_STS_OK); rw_error: @@ -9061,6 +12302,7 @@ trouble ? struct drx_common_attr *common_attr = NULL; #endif /* DRXJ_SPLIT_UCODE_UPLOAD */ struct drxj_data *ext_attr = NULL; + int rc; ext_attr = (struct drxj_data *) demod->my_ext_attr; dev_addr = demod->my_i2c_dev_addr; @@ -9074,12 +12316,18 @@ trouble ? ucode_info.mc_size = common_attr->microcode_size; /* Upload only audio microcode */ - CHK_ERROR(ctrl_u_codeUpload - (demod, &ucode_info, UCODE_UPLOAD, true)); + rc = ctrl_u_codeUpload(demod, &ucode_info, UCODE_UPLOAD, true); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if (common_attr->verify_microcode == true) { - CHK_ERROR(ctrl_u_codeUpload - (demod, &ucode_info, UCODE_VERIFY, true)); + rc = ctrl_u_codeUpload(demod, &ucode_info, UCODE_VERIFY, true); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } /* Prevent uploading audio microcode again */ @@ -9087,12 +12335,36 @@ trouble ? } #endif /* DRXJ_SPLIT_UCODE_UPLOAD */ - WR16(dev_addr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_STOP); - WR16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP); - WR16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP); - WR16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP); - WR16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP); - WR16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP); + rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_STOP, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Reset ATV SCU */ cmd_scu.command = SCU_RAM_COMMAND_STANDARD_ATV | SCU_RAM_COMMAND_CMD_DEMOD_RESET; @@ -9100,9 +12372,17 @@ trouble ? cmd_scu.result_len = 1; cmd_scu.parameter = NULL; cmd_scu.result = &cmd_result; - CHK_ERROR(scu_command(dev_addr, &cmd_scu)); + rc = scu_command(dev_addr, &cmd_scu); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } - WR16(dev_addr, ATV_TOP_MOD_CONTROL__A, ATV_TOP_MOD_CONTROL__PRE); + rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_MOD_CONTROL__A, ATV_TOP_MOD_CONTROL__PRE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* TODO remove AUTO/OFF patches after ucode fix. */ switch (*standard) { @@ -9110,29 +12390,73 @@ trouble ? /* NTSC */ cmd_param = SCU_RAM_ATV_STANDARD_STANDARD_MN; - WR16(dev_addr, IQM_RT_LO_INCR__A, IQM_RT_LO_INCR_MN); - WR16(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M); - WRB(dev_addr, IQM_CF_TAP_RE0__A, sizeof(ntsc_taps_re), - ((u8 *)ntsc_taps_re)); - WRB(dev_addr, IQM_CF_TAP_IM0__A, sizeof(ntsc_taps_im), - ((u8 *)ntsc_taps_im)); - - WR16(dev_addr, ATV_TOP_CR_AMP_TH__A, ATV_TOP_CR_AMP_TH_MN); - WR16(dev_addr, ATV_TOP_CR_CONT__A, - (ATV_TOP_CR_CONT_CR_P_MN | - ATV_TOP_CR_CONT_CR_D_MN | ATV_TOP_CR_CONT_CR_I_MN)); - WR16(dev_addr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_MN); - WR16(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_MN | - ATV_TOP_STD_VID_POL_MN)); - WR16(dev_addr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_MN); - - WR16(dev_addr, SCU_RAM_ATV_AGC_MODE__A, - (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM | - SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE)); - WR16(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000); - WR16(dev_addr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000); - WR16(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, - SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_BG_MN); + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_LO_INCR__A, IQM_RT_LO_INCR_MN, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(ntsc_taps_re), ((u8 *)ntsc_taps_re), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(ntsc_taps_im), ((u8 *)ntsc_taps_im), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_AMP_TH__A, ATV_TOP_CR_AMP_TH_MN, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_CONT__A, (ATV_TOP_CR_CONT_CR_P_MN | ATV_TOP_CR_CONT_CR_D_MN | ATV_TOP_CR_CONT_CR_I_MN), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_MN, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_MN | ATV_TOP_STD_VID_POL_MN), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_MN, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM | SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_BG_MN, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } ext_attr->phase_correction_bypass = false; ext_attr->enable_cvbs_output = true; break; @@ -9140,21 +12464,52 @@ trouble ? /* FM */ cmd_param = SCU_RAM_ATV_STANDARD_STANDARD_FM; - WR16(dev_addr, IQM_RT_LO_INCR__A, 2994); - WR16(dev_addr, IQM_CF_MIDTAP__A, 0); - WRB(dev_addr, IQM_CF_TAP_RE0__A, sizeof(fm_taps_re), - ((u8 *)fm_taps_re)); - WRB(dev_addr, IQM_CF_TAP_IM0__A, sizeof(fm_taps_im), - ((u8 *)fm_taps_im)); - WR16(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_FM | - ATV_TOP_STD_VID_POL_FM)); - WR16(dev_addr, ATV_TOP_MOD_CONTROL__A, 0); - WR16(dev_addr, ATV_TOP_CR_CONT__A, 0); - - WR16(dev_addr, SCU_RAM_ATV_AGC_MODE__A, - (SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW | - SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM)); - WR16(dev_addr, IQM_RT_ROT_BP__A, IQM_RT_ROT_BP_ROT_OFF_OFF); + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_LO_INCR__A, 2994, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_MIDTAP__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(fm_taps_re), ((u8 *)fm_taps_re), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(fm_taps_im), ((u8 *)fm_taps_im), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_FM | ATV_TOP_STD_VID_POL_FM), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_MOD_CONTROL__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_CONT__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW | SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_ROT_BP__A, IQM_RT_ROT_BP_ROT_OFF_OFF, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } ext_attr->phase_correction_bypass = true; ext_attr->enable_cvbs_output = false; break; @@ -9162,27 +12517,71 @@ trouble ? /* PAL/SECAM B/G */ cmd_param = SCU_RAM_ATV_STANDARD_STANDARD_B; - WR16(dev_addr, IQM_RT_LO_INCR__A, 1820); /* TODO check with IS */ - WR16(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M); - WRB(dev_addr, IQM_CF_TAP_RE0__A, sizeof(bg_taps_re), - ((u8 *)bg_taps_re)); - WRB(dev_addr, IQM_CF_TAP_IM0__A, sizeof(bg_taps_im), - ((u8 *)bg_taps_im)); - WR16(dev_addr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_BG); - WR16(dev_addr, ATV_TOP_CR_AMP_TH__A, ATV_TOP_CR_AMP_TH_BG); - WR16(dev_addr, ATV_TOP_CR_CONT__A, - (ATV_TOP_CR_CONT_CR_P_BG | - ATV_TOP_CR_CONT_CR_D_BG | ATV_TOP_CR_CONT_CR_I_BG)); - WR16(dev_addr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_BG); - WR16(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_BG | - ATV_TOP_STD_VID_POL_BG)); - WR16(dev_addr, SCU_RAM_ATV_AGC_MODE__A, - (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM | - SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE)); - WR16(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000); - WR16(dev_addr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000); - WR16(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, - SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_BG_MN); + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_LO_INCR__A, 1820, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* TODO check with IS */ + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(bg_taps_re), ((u8 *)bg_taps_re), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(bg_taps_im), ((u8 *)bg_taps_im), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_BG, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_AMP_TH__A, ATV_TOP_CR_AMP_TH_BG, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_CONT__A, (ATV_TOP_CR_CONT_CR_P_BG | ATV_TOP_CR_CONT_CR_D_BG | ATV_TOP_CR_CONT_CR_I_BG), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_BG, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_BG | ATV_TOP_STD_VID_POL_BG), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM | SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_BG_MN, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } ext_attr->phase_correction_bypass = false; ext_attr->atv_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; ext_attr->enable_cvbs_output = true; @@ -9191,27 +12590,71 @@ trouble ? /* PAL/SECAM D/K */ cmd_param = SCU_RAM_ATV_STANDARD_STANDARD_DK; - WR16(dev_addr, IQM_RT_LO_INCR__A, 2225); /* TODO check with IS */ - WR16(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M); - WRB(dev_addr, IQM_CF_TAP_RE0__A, sizeof(dk_i_l_lp_taps_re), - ((u8 *)dk_i_l_lp_taps_re)); - WRB(dev_addr, IQM_CF_TAP_IM0__A, sizeof(dk_i_l_lp_taps_im), - ((u8 *)dk_i_l_lp_taps_im)); - WR16(dev_addr, ATV_TOP_CR_AMP_TH__A, ATV_TOP_CR_AMP_TH_DK); - WR16(dev_addr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_DK); - WR16(dev_addr, ATV_TOP_CR_CONT__A, - (ATV_TOP_CR_CONT_CR_P_DK | - ATV_TOP_CR_CONT_CR_D_DK | ATV_TOP_CR_CONT_CR_I_DK)); - WR16(dev_addr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_DK); - WR16(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_DK | - ATV_TOP_STD_VID_POL_DK)); - WR16(dev_addr, SCU_RAM_ATV_AGC_MODE__A, - (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM | - SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE)); - WR16(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000); - WR16(dev_addr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000); - WR16(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, - SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_DK); + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_LO_INCR__A, 2225, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* TODO check with IS */ + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(dk_i_l_lp_taps_re), ((u8 *)dk_i_l_lp_taps_re), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(dk_i_l_lp_taps_im), ((u8 *)dk_i_l_lp_taps_im), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_AMP_TH__A, ATV_TOP_CR_AMP_TH_DK, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_DK, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_CONT__A, (ATV_TOP_CR_CONT_CR_P_DK | ATV_TOP_CR_CONT_CR_D_DK | ATV_TOP_CR_CONT_CR_I_DK), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_DK, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_DK | ATV_TOP_STD_VID_POL_DK), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM | SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_DK, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } ext_attr->phase_correction_bypass = false; ext_attr->atv_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; ext_attr->enable_cvbs_output = true; @@ -9220,27 +12663,71 @@ trouble ? /* PAL/SECAM I */ cmd_param = SCU_RAM_ATV_STANDARD_STANDARD_I; - WR16(dev_addr, IQM_RT_LO_INCR__A, 2225); /* TODO check with IS */ - WR16(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M); - WRB(dev_addr, IQM_CF_TAP_RE0__A, sizeof(dk_i_l_lp_taps_re), - ((u8 *)dk_i_l_lp_taps_re)); - WRB(dev_addr, IQM_CF_TAP_IM0__A, sizeof(dk_i_l_lp_taps_im), - ((u8 *)dk_i_l_lp_taps_im)); - WR16(dev_addr, ATV_TOP_CR_AMP_TH__A, ATV_TOP_CR_AMP_TH_I); - WR16(dev_addr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_I); - WR16(dev_addr, ATV_TOP_CR_CONT__A, - (ATV_TOP_CR_CONT_CR_P_I | - ATV_TOP_CR_CONT_CR_D_I | ATV_TOP_CR_CONT_CR_I_I)); - WR16(dev_addr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_I); - WR16(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_I | - ATV_TOP_STD_VID_POL_I)); - WR16(dev_addr, SCU_RAM_ATV_AGC_MODE__A, - (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM | - SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE)); - WR16(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000); - WR16(dev_addr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000); - WR16(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, - SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_I); + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_LO_INCR__A, 2225, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* TODO check with IS */ + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(dk_i_l_lp_taps_re), ((u8 *)dk_i_l_lp_taps_re), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(dk_i_l_lp_taps_im), ((u8 *)dk_i_l_lp_taps_im), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_AMP_TH__A, ATV_TOP_CR_AMP_TH_I, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_I, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_CONT__A, (ATV_TOP_CR_CONT_CR_P_I | ATV_TOP_CR_CONT_CR_D_I | ATV_TOP_CR_CONT_CR_I_I), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_I, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_I | ATV_TOP_STD_VID_POL_I), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM | SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_I, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } ext_attr->phase_correction_bypass = false; ext_attr->atv_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; ext_attr->enable_cvbs_output = true; @@ -9249,28 +12736,71 @@ trouble ? /* PAL/SECAM L with negative modulation */ cmd_param = SCU_RAM_ATV_STANDARD_STANDARD_L; - WR16(dev_addr, IQM_RT_LO_INCR__A, 2225); /* TODO check with IS */ - WR16(dev_addr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_L); - WR16(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M); - WRB(dev_addr, IQM_CF_TAP_RE0__A, sizeof(dk_i_l_lp_taps_re), - ((u8 *)dk_i_l_lp_taps_re)); - WRB(dev_addr, IQM_CF_TAP_IM0__A, sizeof(dk_i_l_lp_taps_im), - ((u8 *)dk_i_l_lp_taps_im)); - WR16(dev_addr, ATV_TOP_CR_AMP_TH__A, 0x2); /* TODO check with IS */ - WR16(dev_addr, ATV_TOP_CR_CONT__A, - (ATV_TOP_CR_CONT_CR_P_L | - ATV_TOP_CR_CONT_CR_D_L | ATV_TOP_CR_CONT_CR_I_L)); - WR16(dev_addr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_L); - WR16(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_L | - ATV_TOP_STD_VID_POL_L)); - WR16(dev_addr, SCU_RAM_ATV_AGC_MODE__A, - (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_AM | - SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_ENABLE | - SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW)); - WR16(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000); - WR16(dev_addr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000); - WR16(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, - SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_LLP); + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_LO_INCR__A, 2225, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* TODO check with IS */ + rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_L, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(dk_i_l_lp_taps_re), ((u8 *)dk_i_l_lp_taps_re), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(dk_i_l_lp_taps_im), ((u8 *)dk_i_l_lp_taps_im), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_AMP_TH__A, 0x2, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* TODO check with IS */ + rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_CONT__A, (ATV_TOP_CR_CONT_CR_P_L | ATV_TOP_CR_CONT_CR_D_L | ATV_TOP_CR_CONT_CR_I_L), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_L, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_L | ATV_TOP_STD_VID_POL_L), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_AM | SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_ENABLE | SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_LLP, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } ext_attr->phase_correction_bypass = false; ext_attr->atv_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_USER; ext_attr->atv_if_agc_cfg.output_level = ext_attr->atv_rf_agc_cfg.top; @@ -9280,28 +12810,71 @@ trouble ? /* PAL/SECAM L with positive modulation */ cmd_param = SCU_RAM_ATV_STANDARD_STANDARD_LP; - WR16(dev_addr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_LP); - WR16(dev_addr, IQM_RT_LO_INCR__A, 2225); /* TODO check with IS */ - WR16(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M); - WRB(dev_addr, IQM_CF_TAP_RE0__A, sizeof(dk_i_l_lp_taps_re), - ((u8 *)dk_i_l_lp_taps_re)); - WRB(dev_addr, IQM_CF_TAP_IM0__A, sizeof(dk_i_l_lp_taps_im), - ((u8 *)dk_i_l_lp_taps_im)); - WR16(dev_addr, ATV_TOP_CR_AMP_TH__A, 0x2); /* TODO check with IS */ - WR16(dev_addr, ATV_TOP_CR_CONT__A, - (ATV_TOP_CR_CONT_CR_P_LP | - ATV_TOP_CR_CONT_CR_D_LP | ATV_TOP_CR_CONT_CR_I_LP)); - WR16(dev_addr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_LP); - WR16(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_LP | - ATV_TOP_STD_VID_POL_LP)); - WR16(dev_addr, SCU_RAM_ATV_AGC_MODE__A, - (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_AM | - SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_ENABLE | - SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW)); - WR16(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000); - WR16(dev_addr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000); - WR16(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, - SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_LLP); + rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_LP, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_LO_INCR__A, 2225, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* TODO check with IS */ + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(dk_i_l_lp_taps_re), ((u8 *)dk_i_l_lp_taps_re), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(dk_i_l_lp_taps_im), ((u8 *)dk_i_l_lp_taps_im), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_AMP_TH__A, 0x2, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* TODO check with IS */ + rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_CONT__A, (ATV_TOP_CR_CONT_CR_P_LP | ATV_TOP_CR_CONT_CR_D_LP | ATV_TOP_CR_CONT_CR_I_LP), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_LP, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_LP | ATV_TOP_STD_VID_POL_LP), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_AM | SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_ENABLE | SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_LLP, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } ext_attr->phase_correction_bypass = false; ext_attr->atv_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_USER; ext_attr->atv_if_agc_cfg.output_level = ext_attr->atv_rf_agc_cfg.top; @@ -9313,56 +12886,199 @@ trouble ? /* Common initializations FM & NTSC & B/G & D/K & I & L & LP */ if (ext_attr->has_lna == false) { - WR16(dev_addr, IQM_AF_AMUX__A, 0x01); + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_AMUX__A, 0x01, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } - WR16(dev_addr, SCU_RAM_ATV_STANDARD__A, 0x002); - WR16(dev_addr, IQM_AF_CLP_LEN__A, IQM_AF_CLP_LEN_ATV); - WR16(dev_addr, IQM_AF_CLP_TH__A, IQM_AF_CLP_TH_ATV); - WR16(dev_addr, IQM_AF_SNS_LEN__A, IQM_AF_SNS_LEN_ATV); - CHK_ERROR(ctrl_set_cfg_pre_saw(demod, &(ext_attr->atv_pre_saw_cfg))); - WR16(dev_addr, IQM_AF_AGC_IF__A, 10248); + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_STANDARD__A, 0x002, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_CLP_LEN__A, IQM_AF_CLP_LEN_ATV, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_CLP_TH__A, IQM_AF_CLP_TH_ATV, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_SNS_LEN__A, IQM_AF_SNS_LEN_ATV, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->atv_pre_saw_cfg)); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_AGC_IF__A, 10248, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } ext_attr->iqm_rc_rate_ofs = 0x00200000L; - WR32(dev_addr, IQM_RC_RATE_OFS_LO__A, ext_attr->iqm_rc_rate_ofs); - WR16(dev_addr, IQM_RC_ADJ_SEL__A, IQM_RC_ADJ_SEL_B_OFF); - WR16(dev_addr, IQM_RC_STRETCH__A, IQM_RC_STRETCH_ATV); + rc = DRXJ_DAP.write_reg32func(dev_addr, IQM_RC_RATE_OFS_LO__A, ext_attr->iqm_rc_rate_ofs, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RC_ADJ_SEL__A, IQM_RC_ADJ_SEL_B_OFF, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RC_STRETCH__A, IQM_RC_STRETCH_ATV, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } - WR16(dev_addr, IQM_RT_ACTIVE__A, IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_ON | - IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_ON); + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_ACTIVE__A, IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_ON | IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_ON, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } - WR16(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_ATV__M); - WR16(dev_addr, IQM_CF_SYMMETRIC__A, IQM_CF_SYMMETRIC_IM__M); + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_ATV__M, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_SYMMETRIC__A, IQM_CF_SYMMETRIC_IM__M, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* default: SIF in standby */ - WR16(dev_addr, ATV_TOP_SYNC_SLICE__A, ATV_TOP_SYNC_SLICE_MN); - WR16(dev_addr, ATV_TOP_MOD_ACCU__A, ATV_TOP_MOD_ACCU__PRE); - - WR16(dev_addr, SCU_RAM_ATV_SIF_GAIN__A, 0x080); - WR16(dev_addr, SCU_RAM_ATV_FAGC_TH_RED__A, 10); - WR16(dev_addr, SCU_RAM_ATV_AAGC_CNT__A, 7); - WR16(dev_addr, SCU_RAM_ATV_NAGC_KI_MIN__A, 0x0225); - WR16(dev_addr, SCU_RAM_ATV_NAGC_KI_MAX__A, 0x0547); - WR16(dev_addr, SCU_RAM_ATV_KI_CHANGE_TH__A, 20); - WR16(dev_addr, SCU_RAM_ATV_LOCK__A, 0); - - WR16(dev_addr, IQM_RT_DELAY__A, IQM_RT_DELAY__PRE); - WR16(dev_addr, SCU_RAM_ATV_BPC_KI_MIN__A, 531); - WR16(dev_addr, SCU_RAM_ATV_PAGC_KI_MIN__A, 1061); - WR16(dev_addr, SCU_RAM_ATV_BP_REF_MIN__A, 100); - WR16(dev_addr, SCU_RAM_ATV_BP_REF_MAX__A, 260); - WR16(dev_addr, SCU_RAM_ATV_BP_LVL__A, 0); - WR16(dev_addr, SCU_RAM_ATV_AMS_MAX__A, 0); - WR16(dev_addr, SCU_RAM_ATV_AMS_MIN__A, 2047); - WR16(dev_addr, SCU_RAM_GPIO__A, 0); + rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_SYNC_SLICE__A, ATV_TOP_SYNC_SLICE_MN, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_MOD_ACCU__A, ATV_TOP_MOD_ACCU__PRE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_SIF_GAIN__A, 0x080, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_FAGC_TH_RED__A, 10, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AAGC_CNT__A, 7, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_NAGC_KI_MIN__A, 0x0225, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_NAGC_KI_MAX__A, 0x0547, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_KI_CHANGE_TH__A, 20, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_LOCK__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_DELAY__A, IQM_RT_DELAY__PRE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_BPC_KI_MIN__A, 531, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_PAGC_KI_MIN__A, 1061, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_BP_REF_MIN__A, 100, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_BP_REF_MAX__A, 260, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_BP_LVL__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AMS_MAX__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AMS_MIN__A, 2047, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_GPIO__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Override reset values with current shadow settings */ - CHK_ERROR(atv_update_config(demod, true)); + rc = atv_update_config(demod, true); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Configure/restore AGC settings */ - CHK_ERROR(init_agc(demod)); - CHK_ERROR(set_agc_if(demod, &(ext_attr->atv_if_agc_cfg), false)); - CHK_ERROR(set_agc_rf(demod, &(ext_attr->atv_rf_agc_cfg), false)); - CHK_ERROR(ctrl_set_cfg_pre_saw(demod, &(ext_attr->atv_pre_saw_cfg))); + rc = init_agc(demod); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = set_agc_if(demod, &(ext_attr->atv_if_agc_cfg), false); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = set_agc_rf(demod, &(ext_attr->atv_rf_agc_cfg), false); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->atv_pre_saw_cfg)); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Set SCU ATV substandard,assuming this doesn't require running ATV block */ cmd_scu.command = SCU_RAM_COMMAND_STANDARD_ATV | @@ -9371,14 +13087,30 @@ trouble ? cmd_scu.result_len = 1; cmd_scu.parameter = &cmd_param; cmd_scu.result = &cmd_result; - CHK_ERROR(scu_command(dev_addr, &cmd_scu)); + rc = scu_command(dev_addr, &cmd_scu); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* turn the analog work around on/off (must after set_env b/c it is set in mc) */ if (ext_attr->mfx == 0x03) { - WR16(dev_addr, SCU_RAM_ATV_ENABLE_IIR_WA__A, 0); + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_ENABLE_IIR_WA__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } else { - WR16(dev_addr, SCU_RAM_ATV_ENABLE_IIR_WA__A, 1); - WR16(dev_addr, SCU_RAM_ATV_IIR_CRIT__A, 225); + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_ENABLE_IIR_WA__A, 1, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_IIR_CRIT__A, 225, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } return (DRX_STS_OK); @@ -9416,6 +13148,7 @@ set_atv_channel(struct drx_demod_instance *demod, u16 cmd_result = 0; struct drxj_data *ext_attr = NULL; struct i2c_device_addr *dev_addr = NULL; + int rc; dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -9430,8 +13163,16 @@ set_atv_channel(struct drx_demod_instance *demod, ext_attr->mirror = channel->mirror; } - CHK_ERROR(set_frequency(demod, channel, tuner_freq_offset)); - WR16(dev_addr, ATV_TOP_CR_FREQ__A, ATV_TOP_CR_FREQ__PRE); + rc = set_frequency(demod, channel, tuner_freq_offset); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_FREQ__A, ATV_TOP_CR_FREQ__PRE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Start ATV SCU */ cmd_scu.command = SCU_RAM_COMMAND_STANDARD_ATV | @@ -9440,7 +13181,11 @@ set_atv_channel(struct drx_demod_instance *demod, cmd_scu.result_len = 1; cmd_scu.parameter = NULL; cmd_scu.result = &cmd_result; - CHK_ERROR(scu_command(dev_addr, &cmd_scu)); + rc = scu_command(dev_addr, &cmd_scu); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* if ( (ext_attr->standard == DRX_STANDARD_FM) && (ext_attr->flagSetAUDdone == true) ) { @@ -9475,6 +13220,7 @@ get_atv_channel(struct drx_demod_instance *demod, { s32 offset = 0; struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + int rc; /* Bandwidth */ channel->bandwidth = ((struct drxj_data *) demod->my_ext_attr)->curr_bandwidth; @@ -9489,7 +13235,11 @@ get_atv_channel(struct drx_demod_instance *demod, u16 measured_offset = 0; /* get measured frequency offset */ - RR16(dev_addr, ATV_TOP_CR_FREQ__A, &measured_offset); + rc = DRXJ_DAP.read_reg16func(dev_addr, ATV_TOP_CR_FREQ__A, &measured_offset, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Signed 8 bit register => sign extension needed */ if ((measured_offset & 0x0080) != 0) { /* sign extension */ @@ -9504,7 +13254,11 @@ get_atv_channel(struct drx_demod_instance *demod, u16 measured_offset = 0; /* get measured frequency offset */ - RR16(dev_addr, ATV_TOP_CR_FREQ__A, &measured_offset); + rc = DRXJ_DAP.read_reg16func(dev_addr, ATV_TOP_CR_FREQ__A, &measured_offset, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Signed 8 bit register => sign extension needed */ if ((measured_offset & 0x0080) != 0) { /* sign extension */ @@ -9557,6 +13311,7 @@ get_atv_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength) { struct i2c_device_addr *dev_addr = NULL; struct drxj_data *ext_attr = NULL; + int rc; /* All weights must add up to 100 (%) TODO: change weights when IF ctrl is available */ @@ -9590,12 +13345,20 @@ get_atv_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength) case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */ case DRX_STANDARD_PAL_SECAM_LP: /* fallthrough */ case DRX_STANDARD_NTSC: - SARR16(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, &digital_curr_gain); + rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, &digital_curr_gain, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } digital_max_gain = 22512; /* taken from ucode */ digital_min_gain = 2400; /* taken from ucode */ break; case DRX_STANDARD_FM: - SARR16(dev_addr, SCU_RAM_ATV_SIF_GAIN__A, &digital_curr_gain); + rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_ATV_SIF_GAIN__A, &digital_curr_gain, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } digital_max_gain = 0x4ff; /* taken from ucode */ digital_min_gain = 0; /* taken from ucode */ break; @@ -9603,8 +13366,16 @@ get_atv_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength) return (DRX_STS_ERROR); break; } - RR16(dev_addr, IQM_AF_AGC_RF__A, &rf_curr_gain); - RR16(dev_addr, IQM_AF_AGC_IF__A, &if_curr_gain); + rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_AGC_RF__A, &rf_curr_gain, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_AGC_IF__A, &if_curr_gain, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* clipping */ if (digital_curr_gain >= digital_max_gain) @@ -9666,6 +13437,7 @@ atv_sig_quality(struct drx_demod_instance *demod, struct drx_sig_quality *sig_qu { struct i2c_device_addr *dev_addr = NULL; u16 quality_indicator = 0; + int rc; dev_addr = demod->my_i2c_dev_addr; @@ -9684,7 +13456,11 @@ atv_sig_quality(struct drx_demod_instance *demod, struct drx_sig_quality *sig_qu 0x700..0x7ff: no signal => 0% .. 30% */ - SARR16(dev_addr, SCU_RAM_ATV_CR_LOCK__A, &quality_indicator); + rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_ATV_CR_LOCK__A, &quality_indicator, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } quality_indicator &= SCU_RAM_ATV_CR_LOCK_CR_LOCK__M; if (quality_indicator <= 0x80) { sig_quality->indicator = @@ -9724,16 +13500,33 @@ static int power_up_aud(struct drx_demod_instance *demod, bool set_standard) { enum drx_aud_standard aud_standard = DRX_AUD_STANDARD_AUTO; struct i2c_device_addr *dev_addr = NULL; + int rc; dev_addr = demod->my_i2c_dev_addr; - WR16(dev_addr, AUD_TOP_COMM_EXEC__A, AUD_TOP_COMM_EXEC_ACTIVE); + rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_TOP_COMM_EXEC__A, AUD_TOP_COMM_EXEC_ACTIVE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* setup TR interface: R/W mode, fifosize=8 */ - WR16(dev_addr, AUD_TOP_TR_MDE__A, 8); - WR16(dev_addr, AUD_COMM_EXEC__A, AUD_COMM_EXEC_ACTIVE); + rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_TOP_TR_MDE__A, 8, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_COMM_EXEC__A, AUD_COMM_EXEC_ACTIVE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if (set_standard == true) { - CHK_ERROR(aud_ctrl_set_standard(demod, &aud_standard)); + rc = aud_ctrl_set_standard(demod, &aud_standard); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } return DRX_STS_OK; @@ -9753,11 +13546,16 @@ static int power_down_aud(struct drx_demod_instance *demod) { struct i2c_device_addr *dev_addr = NULL; struct drxj_data *ext_attr = NULL; + int rc; dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; - WR16(dev_addr, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP); + rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } ext_attr->aud_data.audio_is_active = false; @@ -9778,6 +13576,7 @@ static int aud_get_modus(struct drx_demod_instance *demod, u16 *modus) { struct i2c_device_addr *dev_addr = NULL; struct drxj_data *ext_attr = NULL; + int rc; u16 r_modus = 0; u16 r_modusHi = 0; @@ -9792,13 +13591,25 @@ static int aud_get_modus(struct drx_demod_instance *demod, u16 *modus) /* power up */ if (ext_attr->aud_data.audio_is_active == false) { - CHK_ERROR(power_up_aud(demod, true)); + rc = power_up_aud(demod, true); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } ext_attr->aud_data.audio_is_active = true; } /* Modus register is combined in to RAM location */ - RR16(dev_addr, AUD_DEM_RAM_MODUS_HI__A, &r_modusHi); - RR16(dev_addr, AUD_DEM_RAM_MODUS_LO__A, &r_modusLo); + rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_RAM_MODUS_HI__A, &r_modusHi, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_RAM_MODUS_LO__A, &r_modusLo, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } r_modus = ((r_modusHi << 12) & AUD_DEM_RAM_MODUS_HI__M) | (((r_modusLo & AUD_DEM_RAM_MODUS_LO__M))); @@ -9823,6 +13634,7 @@ aud_ctrl_get_cfg_rds(struct drx_demod_instance *demod, struct drx_cfg_aud_rds *s { struct i2c_device_addr *addr = NULL; struct drxj_data *ext_attr = NULL; + int rc; u16 r_rds_array_cnt_init = 0; u16 r_rds_array_cnt_check = 0; @@ -9838,13 +13650,21 @@ aud_ctrl_get_cfg_rds(struct drx_demod_instance *demod, struct drx_cfg_aud_rds *s /* power up */ if (ext_attr->aud_data.audio_is_active == false) { - CHK_ERROR(power_up_aud(demod, true)); + rc = power_up_aud(demod, true); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } ext_attr->aud_data.audio_is_active = true; } status->valid = false; - RR16(addr, AUD_DEM_RD_RDS_ARRAY_CNT__A, &r_rds_array_cnt_init); + rc = DRXJ_DAP.read_reg16func(addr, AUD_DEM_RD_RDS_ARRAY_CNT__A, &r_rds_array_cnt_init, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if (r_rds_array_cnt_init == AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT_RDS_DATA_NOT_VALID) { @@ -9864,11 +13684,19 @@ aud_ctrl_get_cfg_rds(struct drx_demod_instance *demod, struct drx_cfg_aud_rds *s /* new data */ /* read the data */ for (rds_data_cnt = 0; rds_data_cnt < AUD_RDS_ARRAY_SIZE; rds_data_cnt++) { - RR16(addr, AUD_DEM_RD_RDS_DATA__A, &r_rds_data); + rc = DRXJ_DAP.read_reg16func(addr, AUD_DEM_RD_RDS_DATA__A, &r_rds_data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } status->data[rds_data_cnt] = r_rds_data; } - RR16(addr, AUD_DEM_RD_RDS_ARRAY_CNT__A, &r_rds_array_cnt_check); + rc = DRXJ_DAP.read_reg16func(addr, AUD_DEM_RD_RDS_ARRAY_CNT__A, &r_rds_array_cnt_check, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if (r_rds_array_cnt_check == r_rds_array_cnt_init) { status->valid = true; @@ -9893,7 +13721,7 @@ aud_ctrl_get_carrier_detect_status(struct drx_demod_instance *demod, struct drx_ { struct drxj_data *ext_attr = NULL; struct i2c_device_addr *dev_addr = NULL; - + int rc; u16 r_data = 0; if (status == NULL) { @@ -9905,7 +13733,11 @@ aud_ctrl_get_carrier_detect_status(struct drx_demod_instance *demod, struct drx_ /* power up */ if (ext_attr->aud_data.audio_is_active == false) { - CHK_ERROR(power_up_aud(demod, true)); + rc = power_up_aud(demod, true); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } ext_attr->aud_data.audio_is_active = true; } @@ -9917,7 +13749,11 @@ aud_ctrl_get_carrier_detect_status(struct drx_demod_instance *demod, struct drx_ status->stereo = false; /* read stereo sound mode indication */ - RR16(dev_addr, AUD_DEM_RD_STATUS__A, &r_data); + rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_RD_STATUS__A, &r_data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* carrier a detected */ if ((r_data & AUD_DEM_RD_STATUS_STAT_CARR_A__M) == @@ -9972,6 +13808,7 @@ aud_ctrl_get_status(struct drx_demod_instance *demod, struct drx_aud_status *sta struct drxj_data *ext_attr = NULL; struct i2c_device_addr *dev_addr = NULL; struct drx_cfg_aud_rds rds = { false, {0} }; + int rc; u16 r_data = 0; if (status == NULL) { @@ -9982,15 +13819,27 @@ aud_ctrl_get_status(struct drx_demod_instance *demod, struct drx_aud_status *sta ext_attr = (struct drxj_data *) demod->my_ext_attr; /* carrier detection */ - CHK_ERROR(aud_ctrl_get_carrier_detect_status(demod, status)); + rc = aud_ctrl_get_carrier_detect_status(demod, status); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* rds data */ status->rds = false; - CHK_ERROR(aud_ctrl_get_cfg_rds(demod, &rds)); + rc = aud_ctrl_get_cfg_rds(demod, &rds); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } status->rds = ext_attr->aud_data.rds_data_present; /* fm_ident */ - RR16(dev_addr, AUD_DSP_RD_FM_IDENT_VALUE__A, &r_data); + rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DSP_RD_FM_IDENT_VALUE__A, &r_data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } r_data >>= AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__B; status->fm_ident = (s8) r_data; @@ -10011,6 +13860,7 @@ aud_ctrl_get_cfg_volume(struct drx_demod_instance *demod, struct drx_cfg_aud_vol { struct i2c_device_addr *dev_addr = NULL; struct drxj_data *ext_attr = NULL; + int rc; u16 r_volume = 0; u16 r_avc = 0; @@ -10026,13 +13876,21 @@ aud_ctrl_get_cfg_volume(struct drx_demod_instance *demod, struct drx_cfg_aud_vol /* power up */ if (ext_attr->aud_data.audio_is_active == false) { - CHK_ERROR(power_up_aud(demod, true)); + rc = power_up_aud(demod, true); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } ext_attr->aud_data.audio_is_active = true; } /* volume */ volume->mute = ext_attr->aud_data.volume.mute; - RR16(dev_addr, AUD_DSP_WR_VOLUME__A, &r_volume); + rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DSP_WR_VOLUME__A, &r_volume, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if (r_volume == 0) { volume->mute = true; volume->volume = ext_attr->aud_data.volume.volume; @@ -10050,7 +13908,11 @@ aud_ctrl_get_cfg_volume(struct drx_demod_instance *demod, struct drx_cfg_aud_vol } /* automatic volume control */ - RR16(dev_addr, AUD_DSP_WR_AVC__A, &r_avc); + rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DSP_WR_AVC__A, &r_avc, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if ((r_avc & AUD_DSP_WR_AVC_AVC_ON__M) == AUD_DSP_WR_AVC_AVC_ON_OFF) { @@ -10118,12 +13980,20 @@ aud_ctrl_get_cfg_volume(struct drx_demod_instance *demod, struct drx_cfg_aud_vol /* QP vaues */ /* left carrier */ - RR16(dev_addr, AUD_DSP_RD_QPEAK_L__A, &r_strength_left); + rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DSP_RD_QPEAK_L__A, &r_strength_left, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } volume->strength_left = (((s16) log1_times100(r_strength_left)) - AUD_CARRIER_STRENGTH_QP_0DB_LOG10T100) / 5; /* right carrier */ - RR16(dev_addr, AUD_DSP_RD_QPEAK_R__A, &r_strength_right); + rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DSP_RD_QPEAK_R__A, &r_strength_right, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } volume->strength_right = (((s16) log1_times100(r_strength_right)) - AUD_CARRIER_STRENGTH_QP_0DB_LOG10T100) / 5; @@ -10144,6 +14014,7 @@ aud_ctrl_set_cfg_volume(struct drx_demod_instance *demod, struct drx_cfg_aud_vol { struct i2c_device_addr *dev_addr = NULL; struct drxj_data *ext_attr = NULL; + int rc; u16 w_volume = 0; u16 w_avc = 0; @@ -10157,7 +14028,11 @@ aud_ctrl_set_cfg_volume(struct drx_demod_instance *demod, struct drx_cfg_aud_vol /* power up */ if (ext_attr->aud_data.audio_is_active == false) { - CHK_ERROR(power_up_aud(demod, true)); + rc = power_up_aud(demod, true); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } ext_attr->aud_data.audio_is_active = true; } @@ -10168,7 +14043,11 @@ aud_ctrl_set_cfg_volume(struct drx_demod_instance *demod, struct drx_cfg_aud_vol return DRX_STS_INVALID_ARG; } - RR16(dev_addr, AUD_DSP_WR_VOLUME__A, &w_volume); + rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DSP_WR_VOLUME__A, &w_volume, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* clear the volume mask */ w_volume &= (u16) ~AUD_DSP_WR_VOLUME_VOL_MAIN__M; @@ -10182,10 +14061,18 @@ aud_ctrl_set_cfg_volume(struct drx_demod_instance *demod, struct drx_cfg_aud_vol AUD_DSP_WR_VOLUME_VOL_MAIN__B); } - WR16(dev_addr, AUD_DSP_WR_VOLUME__A, w_volume); + rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DSP_WR_VOLUME__A, w_volume, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* automatic volume control */ - RR16(dev_addr, AUD_DSP_WR_AVC__A, &w_avc); + rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DSP_WR_AVC__A, &w_avc, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* clear masks that require writing */ w_avc &= (u16) ~AUD_DSP_WR_AVC_AVC_ON__M; @@ -10256,7 +14143,11 @@ aud_ctrl_set_cfg_volume(struct drx_demod_instance *demod, struct drx_cfg_aud_vol w_avc &= (u16) ~AUD_DSP_WR_AVC_AVC_REF_LEV__M; w_avc |= (u16) (volume->avc_ref_level << AUD_DSP_WR_AVC_AVC_REF_LEV__B); - WR16(dev_addr, AUD_DSP_WR_AVC__A, w_avc); + rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DSP_WR_AVC__A, w_avc, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* all done, store config in data structure */ ext_attr->aud_data.volume = *volume; @@ -10278,7 +14169,7 @@ aud_ctrl_get_cfg_output_i2s(struct drx_demod_instance *demod, struct drx_cfg_i2s { struct i2c_device_addr *dev_addr = NULL; struct drxj_data *ext_attr = NULL; - + int rc; u16 w_i2s_config = 0; u16 r_i2s_freq = 0; @@ -10291,12 +14182,24 @@ aud_ctrl_get_cfg_output_i2s(struct drx_demod_instance *demod, struct drx_cfg_i2s /* power up */ if (ext_attr->aud_data.audio_is_active == false) { - CHK_ERROR(power_up_aud(demod, true)); + rc = power_up_aud(demod, true); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } ext_attr->aud_data.audio_is_active = true; } - RR16(dev_addr, AUD_DEM_RAM_I2S_CONFIG2__A, &w_i2s_config); - RR16(dev_addr, AUD_DSP_WR_I2S_OUT_FS__A, &r_i2s_freq); + rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_RAM_I2S_CONFIG2__A, &w_i2s_config, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DSP_WR_I2S_OUT_FS__A, &r_i2s_freq, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* I2S mode */ switch (w_i2s_config & AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__M) { @@ -10380,7 +14283,7 @@ aud_ctrl_set_cfg_output_i2s(struct drx_demod_instance *demod, struct drx_cfg_i2s { struct i2c_device_addr *dev_addr = NULL; struct drxj_data *ext_attr = NULL; - + int rc; u16 w_i2s_config = 0; u16 w_i2s_pads_data_da = 0; u16 w_i2s_pads_data_cl = 0; @@ -10396,11 +14299,19 @@ aud_ctrl_set_cfg_output_i2s(struct drx_demod_instance *demod, struct drx_cfg_i2s /* power up */ if (ext_attr->aud_data.audio_is_active == false) { - CHK_ERROR(power_up_aud(demod, true)); + rc = power_up_aud(demod, true); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } ext_attr->aud_data.audio_is_active = true; } - RR16(dev_addr, AUD_DEM_RAM_I2S_CONFIG2__A, &w_i2s_config); + rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_RAM_I2S_CONFIG2__A, &w_i2s_config, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* I2S mode */ w_i2s_config &= (u16) ~AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__M; @@ -10485,11 +14396,23 @@ aud_ctrl_set_cfg_output_i2s(struct drx_demod_instance *demod, struct drx_cfg_i2s w_i2s_freq *= 2; } - WR16(dev_addr, AUD_DEM_WR_I2S_CONFIG2__A, w_i2s_config); - WR16(dev_addr, AUD_DSP_WR_I2S_OUT_FS__A, (u16) w_i2s_freq); + rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DEM_WR_I2S_CONFIG2__A, w_i2s_config, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DSP_WR_I2S_OUT_FS__A, (u16)w_i2s_freq, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* configure I2S output pads for master or slave mode */ - WR16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if (output->mode == DRX_I2S_MODE_MASTER) { w_i2s_pads_data_da = SIO_PDR_I2S_DA_CFG_MODE__MASTER | @@ -10507,11 +14430,27 @@ aud_ctrl_set_cfg_output_i2s(struct drx_demod_instance *demod, struct drx_cfg_i2s SIO_PDR_I2S_WS_CFG_DRIVE__SLAVE; } - WR16(dev_addr, SIO_PDR_I2S_DA_CFG__A, w_i2s_pads_data_da); - WR16(dev_addr, SIO_PDR_I2S_CL_CFG__A, w_i2s_pads_data_cl); - WR16(dev_addr, SIO_PDR_I2S_WS_CFG__A, w_i2s_pads_data_ws); + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_I2S_DA_CFG__A, w_i2s_pads_data_da, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_I2S_CL_CFG__A, w_i2s_pads_data_cl, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_I2S_WS_CFG__A, w_i2s_pads_data_ws, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } - WR16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE); + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* all done, store config in data structure */ ext_attr->aud_data.i2sdata = *output; @@ -10535,6 +14474,7 @@ aud_ctrl_get_cfg_auto_sound(struct drx_demod_instance *demod, enum drx_cfg_aud_auto_sound *auto_sound) { struct drxj_data *ext_attr = NULL; + int rc; u16 r_modus = 0; if (auto_sound == NULL) @@ -10544,11 +14484,19 @@ aud_ctrl_get_cfg_auto_sound(struct drx_demod_instance *demod, /* power up */ if (ext_attr->aud_data.audio_is_active == false) { - CHK_ERROR(power_up_aud(demod, true)); + rc = power_up_aud(demod, true); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } ext_attr->aud_data.audio_is_active = true; } - CHK_ERROR(aud_get_modus(demod, &r_modus)); + rc = aud_get_modus(demod, &r_modus); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } switch (r_modus & (AUD_DEM_WR_MODUS_MOD_ASS__M | AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__M)) { @@ -10589,7 +14537,7 @@ aud_ctr_setl_cfg_auto_sound(struct drx_demod_instance *demod, { struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; struct drxj_data *ext_attr = (struct drxj_data *) NULL; - + int rc; u16 r_modus = 0; u16 w_modus = 0; @@ -10602,11 +14550,19 @@ aud_ctr_setl_cfg_auto_sound(struct drx_demod_instance *demod, /* power up */ if (ext_attr->aud_data.audio_is_active == false) { - CHK_ERROR(power_up_aud(demod, true)); + rc = power_up_aud(demod, true); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } ext_attr->aud_data.audio_is_active = true; } - CHK_ERROR(aud_get_modus(demod, &r_modus)); + rc = aud_get_modus(demod, &r_modus); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } w_modus = r_modus; /* clear ASS & ASC bits */ @@ -10631,7 +14587,11 @@ aud_ctr_setl_cfg_auto_sound(struct drx_demod_instance *demod, } if (w_modus != r_modus) { - WR16(dev_addr, AUD_DEM_WR_MODUS__A, w_modus); + rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DEM_WR_MODUS__A, w_modus, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } /* copy to data structure */ ext_attr->aud_data.auto_sound = *auto_sound; @@ -10654,7 +14614,7 @@ aud_ctrl_get_cfg_ass_thres(struct drx_demod_instance *demod, struct drx_cfg_aud_ { struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; struct drxj_data *ext_attr = (struct drxj_data *) NULL; - + int rc; u16 thres_a2 = 0; u16 thres_btsc = 0; u16 thres_nicam = 0; @@ -10668,13 +14628,29 @@ aud_ctrl_get_cfg_ass_thres(struct drx_demod_instance *demod, struct drx_cfg_aud_ /* power up */ if (ext_attr->aud_data.audio_is_active == false) { - CHK_ERROR(power_up_aud(demod, true)); + rc = power_up_aud(demod, true); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } ext_attr->aud_data.audio_is_active = true; } - RR16(dev_addr, AUD_DEM_RAM_A2_THRSHLD__A, &thres_a2); - RR16(dev_addr, AUD_DEM_RAM_BTSC_THRSHLD__A, &thres_btsc); - RR16(dev_addr, AUD_DEM_RAM_NICAM_THRSHLD__A, &thres_nicam); + rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_RAM_A2_THRSHLD__A, &thres_a2, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_RAM_BTSC_THRSHLD__A, &thres_btsc, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_RAM_NICAM_THRSHLD__A, &thres_nicam, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } thres->a2 = thres_a2; thres->btsc = thres_btsc; @@ -10698,7 +14674,7 @@ aud_ctrl_set_cfg_ass_thres(struct drx_demod_instance *demod, struct drx_cfg_aud_ { struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; struct drxj_data *ext_attr = (struct drxj_data *) NULL; - + int rc; if (thres == NULL) { return DRX_STS_INVALID_ARG; } @@ -10708,13 +14684,29 @@ aud_ctrl_set_cfg_ass_thres(struct drx_demod_instance *demod, struct drx_cfg_aud_ /* power up */ if (ext_attr->aud_data.audio_is_active == false) { - CHK_ERROR(power_up_aud(demod, true)); + rc = power_up_aud(demod, true); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } ext_attr->aud_data.audio_is_active = true; } - WR16(dev_addr, AUD_DEM_WR_A2_THRSHLD__A, thres->a2); - WR16(dev_addr, AUD_DEM_WR_BTSC_THRSHLD__A, thres->btsc); - WR16(dev_addr, AUD_DEM_WR_NICAM_THRSHLD__A, thres->nicam); + rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DEM_WR_A2_THRSHLD__A, thres->a2, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DEM_WR_BTSC_THRSHLD__A, thres->btsc, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DEM_WR_NICAM_THRSHLD__A, thres->nicam, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* update DRXK data structure with hardware values */ ext_attr->aud_data.ass_thresholds = *thres; @@ -10736,7 +14728,7 @@ aud_ctrl_get_cfg_carrier(struct drx_demod_instance *demod, struct drx_cfg_aud_ca { struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; struct drxj_data *ext_attr = (struct drxj_data *) NULL; - + int rc; u16 w_modus = 0; u16 dco_a_hi = 0; @@ -10762,11 +14754,19 @@ aud_ctrl_get_cfg_carrier(struct drx_demod_instance *demod, struct drx_cfg_aud_ca /* power up */ if (ext_attr->aud_data.audio_is_active == false) { - CHK_ERROR(power_up_aud(demod, true)); + rc = power_up_aud(demod, true); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } ext_attr->aud_data.audio_is_active = true; } - CHK_ERROR(aud_get_modus(demod, &w_modus)); + rc = aud_get_modus(demod, &w_modus); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Behaviour of primary audio channel */ switch (w_modus & (AUD_DEM_WR_MODUS_MOD_CM_A__M)) { @@ -10795,10 +14795,26 @@ aud_ctrl_get_cfg_carrier(struct drx_demod_instance *demod, struct drx_cfg_aud_ca } /* frequency adjustment for primary & secondary audio channel */ - RR16(dev_addr, AUD_DEM_RAM_DCO_A_HI__A, &dco_a_hi); - RR16(dev_addr, AUD_DEM_RAM_DCO_A_LO__A, &dco_a_lo); - RR16(dev_addr, AUD_DEM_RAM_DCO_B_HI__A, &dco_b_hi); - RR16(dev_addr, AUD_DEM_RAM_DCO_B_LO__A, &dco_b_lo); + rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_RAM_DCO_A_HI__A, &dco_a_hi, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_RAM_DCO_A_LO__A, &dco_a_lo, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_RAM_DCO_B_HI__A, &dco_b_hi, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_RAM_DCO_B_LO__A, &dco_b_lo, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } valA = (((u32) dco_a_hi) << 12) | ((u32) dco_a_lo & 0xFFF); valB = (((u32) dco_b_hi) << 12) | ((u32) dco_b_lo & 0xFFF); @@ -10809,16 +14825,32 @@ aud_ctrl_get_cfg_carrier(struct drx_demod_instance *demod, struct drx_cfg_aud_ca /* DC level of the incoming FM signal on the primary & seconday sound channel */ - RR16(dev_addr, AUD_DSP_RD_FM_DC_LEVEL_A__A, &dc_lvl_a); - RR16(dev_addr, AUD_DSP_RD_FM_DC_LEVEL_B__A, &dc_lvl_b); + rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DSP_RD_FM_DC_LEVEL_A__A, &dc_lvl_a, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DSP_RD_FM_DC_LEVEL_B__A, &dc_lvl_b, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* offset (kHz) = (dcLvl / 322) */ carriers->a.shift = (DRX_U16TODRXFREQ(dc_lvl_a) / 322L); carriers->b.shift = (DRX_U16TODRXFREQ(dc_lvl_b) / 322L); /* Carrier detetcion threshold for primary & secondary channel */ - RR16(dev_addr, AUD_DEM_RAM_CM_A_THRSHLD__A, &cm_thes_a); - RR16(dev_addr, AUD_DEM_RAM_CM_B_THRSHLD__A, &cm_thes_b); + rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_RAM_CM_A_THRSHLD__A, &cm_thes_a, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_RAM_CM_B_THRSHLD__A, &cm_thes_b, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } carriers->a.thres = cm_thes_a; carriers->b.thres = cm_thes_b; @@ -10840,7 +14872,7 @@ aud_ctrl_set_cfg_carrier(struct drx_demod_instance *demod, struct drx_cfg_aud_ca { struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; struct drxj_data *ext_attr = (struct drxj_data *) NULL; - + int rc; u16 w_modus = 0; u16 r_modus = 0; @@ -10861,11 +14893,19 @@ aud_ctrl_set_cfg_carrier(struct drx_demod_instance *demod, struct drx_cfg_aud_ca /* power up */ if (ext_attr->aud_data.audio_is_active == false) { - CHK_ERROR(power_up_aud(demod, true)); + rc = power_up_aud(demod, true); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } ext_attr->aud_data.audio_is_active = true; } - CHK_ERROR(aud_get_modus(demod, &r_modus)); + rc = aud_get_modus(demod, &r_modus); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } w_modus = r_modus; w_modus &= (u16) ~AUD_DEM_WR_MODUS_MOD_CM_A__M; @@ -10898,7 +14938,11 @@ aud_ctrl_set_cfg_carrier(struct drx_demod_instance *demod, struct drx_cfg_aud_ca /* now update the modus register */ if (w_modus != r_modus) { - WR16(dev_addr, AUD_DEM_WR_MODUS__A, w_modus); + rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DEM_WR_MODUS__A, w_modus, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } /* frequency adjustment for primary & secondary audio channel */ @@ -10910,14 +14954,38 @@ aud_ctrl_set_cfg_carrier(struct drx_demod_instance *demod, struct drx_cfg_aud_ca dco_b_hi = (u16) ((valB >> 12) & 0xFFF); dco_b_lo = (u16) (valB & 0xFFF); - WR16(dev_addr, AUD_DEM_WR_DCO_A_HI__A, dco_a_hi); - WR16(dev_addr, AUD_DEM_WR_DCO_A_LO__A, dco_a_lo); - WR16(dev_addr, AUD_DEM_WR_DCO_B_HI__A, dco_b_hi); - WR16(dev_addr, AUD_DEM_WR_DCO_B_LO__A, dco_b_lo); + rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DEM_WR_DCO_A_HI__A, dco_a_hi, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DEM_WR_DCO_A_LO__A, dco_a_lo, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DEM_WR_DCO_B_HI__A, dco_b_hi, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DEM_WR_DCO_B_LO__A, dco_b_lo, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Carrier detetcion threshold for primary & secondary channel */ - WR16(dev_addr, AUD_DEM_WR_CM_A_THRSHLD__A, carriers->a.thres); - WR16(dev_addr, AUD_DEM_WR_CM_B_THRSHLD__A, carriers->b.thres); + rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DEM_WR_CM_A_THRSHLD__A, carriers->a.thres, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DEM_WR_CM_B_THRSHLD__A, carriers->b.thres, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* update DRXK data structure */ ext_attr->aud_data.carriers = *carriers; @@ -10940,7 +15008,7 @@ aud_ctrl_get_cfg_mixer(struct drx_demod_instance *demod, struct drx_cfg_aud_mixe { struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; struct drxj_data *ext_attr = (struct drxj_data *) NULL; - + int rc; u16 src_i2s_matr = 0; u16 fm_matr = 0; @@ -10953,12 +15021,20 @@ aud_ctrl_get_cfg_mixer(struct drx_demod_instance *demod, struct drx_cfg_aud_mixe /* power up */ if (ext_attr->aud_data.audio_is_active == false) { - CHK_ERROR(power_up_aud(demod, true)); + rc = power_up_aud(demod, true); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } ext_attr->aud_data.audio_is_active = true; } /* Source Selctor */ - RR16(dev_addr, AUD_DSP_WR_SRC_I2S_MATR__A, &src_i2s_matr); + rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DSP_WR_SRC_I2S_MATR__A, &src_i2s_matr, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } switch (src_i2s_matr & AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__M) { case AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_MONO: @@ -10996,7 +15072,11 @@ aud_ctrl_get_cfg_mixer(struct drx_demod_instance *demod, struct drx_cfg_aud_mixe } /* FM Matrix */ - RR16(dev_addr, AUD_DEM_WR_FM_MATRIX__A, &fm_matr); + rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_WR_FM_MATRIX__A, &fm_matr, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } switch (fm_matr & AUD_DEM_WR_FM_MATRIX__M) { case AUD_DEM_WR_FM_MATRIX_NO_MATRIX: mixer->matrix_fm = DRX_AUD_FM_MATRIX_NO_MATRIX; @@ -11035,7 +15115,7 @@ aud_ctrl_set_cfg_mixer(struct drx_demod_instance *demod, struct drx_cfg_aud_mixe { struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; struct drxj_data *ext_attr = (struct drxj_data *) NULL; - + int rc; u16 src_i2s_matr = 0; u16 fm_matr = 0; @@ -11048,12 +15128,20 @@ aud_ctrl_set_cfg_mixer(struct drx_demod_instance *demod, struct drx_cfg_aud_mixe /* power up */ if (ext_attr->aud_data.audio_is_active == false) { - CHK_ERROR(power_up_aud(demod, true)); + rc = power_up_aud(demod, true); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } ext_attr->aud_data.audio_is_active = true; } /* Source Selctor */ - RR16(dev_addr, AUD_DSP_WR_SRC_I2S_MATR__A, &src_i2s_matr); + rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DSP_WR_SRC_I2S_MATR__A, &src_i2s_matr, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } src_i2s_matr &= (u16) ~AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__M; switch (mixer->source_i2s) { @@ -11092,10 +15180,18 @@ aud_ctrl_set_cfg_mixer(struct drx_demod_instance *demod, struct drx_cfg_aud_mixe return DRX_STS_INVALID_ARG; } /* write the result */ - WR16(dev_addr, AUD_DSP_WR_SRC_I2S_MATR__A, src_i2s_matr); + rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DSP_WR_SRC_I2S_MATR__A, src_i2s_matr, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* FM Matrix */ - RR16(dev_addr, AUD_DEM_WR_FM_MATRIX__A, &fm_matr); + rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_WR_FM_MATRIX__A, &fm_matr, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } fm_matr &= (u16) ~AUD_DEM_WR_FM_MATRIX__M; switch (mixer->matrix_fm) { case DRX_AUD_FM_MATRIX_NO_MATRIX: @@ -11119,7 +15215,11 @@ aud_ctrl_set_cfg_mixer(struct drx_demod_instance *demod, struct drx_cfg_aud_mixe /* Only write if ASS is off */ if (ext_attr->aud_data.auto_sound == DRX_AUD_AUTO_SOUND_OFF) { - WR16(dev_addr, AUD_DEM_WR_FM_MATRIX__A, fm_matr); + rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DEM_WR_FM_MATRIX__A, fm_matr, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } /* update the data structure with hardware state */ @@ -11143,7 +15243,7 @@ aud_ctrl_set_cfg_av_sync(struct drx_demod_instance *demod, enum drx_cfg_aud_av_s { struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; struct drxj_data *ext_attr = (struct drxj_data *) NULL; - + int rc; u16 w_aud_vid_sync = 0; if (av_sync == NULL) { @@ -11155,12 +15255,20 @@ aud_ctrl_set_cfg_av_sync(struct drx_demod_instance *demod, enum drx_cfg_aud_av_s /* power up */ if (ext_attr->aud_data.audio_is_active == false) { - CHK_ERROR(power_up_aud(demod, true)); + rc = power_up_aud(demod, true); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } ext_attr->aud_data.audio_is_active = true; } /* audio/video synchronisation */ - RR16(dev_addr, AUD_DSP_WR_AV_SYNC__A, &w_aud_vid_sync); + rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DSP_WR_AV_SYNC__A, &w_aud_vid_sync, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } w_aud_vid_sync &= (u16) ~AUD_DSP_WR_AV_SYNC_AV_ON__M; @@ -11189,7 +15297,11 @@ aud_ctrl_set_cfg_av_sync(struct drx_demod_instance *demod, enum drx_cfg_aud_av_s return DRX_STS_INVALID_ARG; } - WR16(dev_addr, AUD_DSP_WR_AV_SYNC__A, w_aud_vid_sync); + rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DSP_WR_AV_SYNC__A, w_aud_vid_sync, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } return DRX_STS_OK; rw_error: return DRX_STS_ERROR; @@ -11208,7 +15320,7 @@ aud_ctrl_get_cfg_av_sync(struct drx_demod_instance *demod, enum drx_cfg_aud_av_s { struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; struct drxj_data *ext_attr = (struct drxj_data *) NULL; - + int rc; u16 w_aud_vid_sync = 0; if (av_sync == NULL) { @@ -11220,12 +15332,20 @@ aud_ctrl_get_cfg_av_sync(struct drx_demod_instance *demod, enum drx_cfg_aud_av_s /* power up */ if (ext_attr->aud_data.audio_is_active == false) { - CHK_ERROR(power_up_aud(demod, true)); + rc = power_up_aud(demod, true); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } ext_attr->aud_data.audio_is_active = true; } /* audio/video synchronisation */ - RR16(dev_addr, AUD_DSP_WR_AV_SYNC__A, &w_aud_vid_sync); + rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DSP_WR_AV_SYNC__A, &w_aud_vid_sync, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if ((w_aud_vid_sync & AUD_DSP_WR_AV_SYNC_AV_ON__M) == AUD_DSP_WR_AV_SYNC_AV_ON_DISABLE) { @@ -11263,11 +15383,16 @@ static int aud_ctrl_get_cfg_dev(struct drx_demod_instance *demod, enum drx_cfg_aud_deviation *dev) { u16 r_modus = 0; + int rc; if (dev == NULL) return DRX_STS_INVALID_ARG; - CHK_ERROR(aud_get_modus(demod, &r_modus)); + rc = aud_get_modus(demod, &r_modus); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } switch (r_modus & AUD_DEM_WR_MODUS_MOD_HDEV_A__M) { case AUD_DEM_WR_MODUS_MOD_HDEV_A_NORMAL: @@ -11297,7 +15422,7 @@ aud_ctrl_set_cfg_dev(struct drx_demod_instance *demod, enum drx_cfg_aud_deviatio { struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; struct drxj_data *ext_attr = (struct drxj_data *) NULL; - + int rc; u16 w_modus = 0; u16 r_modus = 0; @@ -11308,7 +15433,11 @@ aud_ctrl_set_cfg_dev(struct drx_demod_instance *demod, enum drx_cfg_aud_deviatio ext_attr = (struct drxj_data *) demod->my_ext_attr; dev_addr = demod->my_i2c_dev_addr; - CHK_ERROR(aud_get_modus(demod, &r_modus)); + rc = aud_get_modus(demod, &r_modus); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } w_modus = r_modus; @@ -11327,7 +15456,11 @@ aud_ctrl_set_cfg_dev(struct drx_demod_instance *demod, enum drx_cfg_aud_deviatio /* now update the modus register */ if (w_modus != r_modus) { - WR16(dev_addr, AUD_DEM_WR_MODUS__A, w_modus); + rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DEM_WR_MODUS__A, w_modus, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } /* store in drxk data struct */ ext_attr->aud_data.deviation = *dev; @@ -11349,7 +15482,7 @@ aud_ctrl_get_cfg_prescale(struct drx_demod_instance *demod, struct drx_cfg_aud_p { struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; struct drxj_data *ext_attr = (struct drxj_data *) NULL; - + int rc; u16 r_max_fm_deviation = 0; u16 r_nicam_prescaler = 0; @@ -11362,13 +15495,25 @@ aud_ctrl_get_cfg_prescale(struct drx_demod_instance *demod, struct drx_cfg_aud_p /* power up */ if (ext_attr->aud_data.audio_is_active == false) { - CHK_ERROR(power_up_aud(demod, true)); + rc = power_up_aud(demod, true); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } ext_attr->aud_data.audio_is_active = true; } /* read register data */ - RR16(dev_addr, AUD_DSP_WR_NICAM_PRESC__A, &r_nicam_prescaler); - RR16(dev_addr, AUD_DSP_WR_FM_PRESC__A, &r_max_fm_deviation); + rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DSP_WR_NICAM_PRESC__A, &r_nicam_prescaler, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DSP_WR_FM_PRESC__A, &r_max_fm_deviation, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* calculate max FM deviation */ r_max_fm_deviation >>= AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__B; @@ -11423,7 +15568,7 @@ aud_ctrl_set_cfg_prescale(struct drx_demod_instance *demod, struct drx_cfg_aud_p { struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; struct drxj_data *ext_attr = (struct drxj_data *) NULL; - + int rc; u16 w_max_fm_deviation = 0; u16 nicam_prescaler; @@ -11436,7 +15581,11 @@ aud_ctrl_set_cfg_prescale(struct drx_demod_instance *demod, struct drx_cfg_aud_p /* power up */ if (ext_attr->aud_data.audio_is_active == false) { - CHK_ERROR(power_up_aud(demod, true)); + rc = power_up_aud(demod, true); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } ext_attr->aud_data.audio_is_active = true; } @@ -11483,8 +15632,16 @@ aud_ctrl_set_cfg_prescale(struct drx_demod_instance *demod, struct drx_cfg_aud_p } /* end of setting NICAM Prescaler */ - WR16(dev_addr, AUD_DSP_WR_NICAM_PRESC__A, nicam_prescaler); - WR16(dev_addr, AUD_DSP_WR_FM_PRESC__A, w_max_fm_deviation); + rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DSP_WR_NICAM_PRESC__A, nicam_prescaler, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DSP_WR_FM_PRESC__A, w_max_fm_deviation, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } ext_attr->aud_data.prescale = *presc; @@ -11504,7 +15661,7 @@ static int aud_ctrl_beep(struct drx_demod_instance *demod, struct drx_aud_beep * { struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; struct drxj_data *ext_attr = (struct drxj_data *) NULL; - + int rc; u16 the_beep = 0; u16 volume = 0; u32 frequency = 0; @@ -11518,7 +15675,11 @@ static int aud_ctrl_beep(struct drx_demod_instance *demod, struct drx_aud_beep * /* power up */ if (ext_attr->aud_data.audio_is_active == false) { - CHK_ERROR(power_up_aud(demod, true)); + rc = power_up_aud(demod, true); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } ext_attr->aud_data.audio_is_active = true; } @@ -11543,7 +15704,11 @@ static int aud_ctrl_beep(struct drx_demod_instance *demod, struct drx_aud_beep * the_beep = 0; } - WR16(dev_addr, AUD_DSP_WR_BEEPER__A, the_beep); + rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DSP_WR_BEEPER__A, the_beep, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } return DRX_STS_OK; rw_error: @@ -11563,7 +15728,7 @@ aud_ctrl_set_standard(struct drx_demod_instance *demod, enum drx_aud_standard *s struct i2c_device_addr *dev_addr = NULL; struct drxj_data *ext_attr = NULL; enum drx_standard current_standard = DRX_STANDARD_UNKNOWN; - + int rc; u16 w_standard = 0; u16 w_modus = 0; u16 r_modus = 0; @@ -11581,7 +15746,11 @@ aud_ctrl_set_standard(struct drx_demod_instance *demod, enum drx_aud_standard *s /* power up */ if (ext_attr->aud_data.audio_is_active == false) { - CHK_ERROR(power_up_aud(demod, false)); + rc = power_up_aud(demod, false); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } ext_attr->aud_data.audio_is_active = true; } @@ -11594,19 +15763,54 @@ aud_ctrl_set_standard(struct drx_demod_instance *demod, enum drx_aud_standard *s ext_attr->aud_data.volume.mute = true; /* restore data structure from DRX ExtAttr, call volume first to mute */ - CHK_ERROR(aud_ctrl_set_cfg_volume(demod, &ext_attr->aud_data.volume)); - CHK_ERROR(aud_ctrl_set_cfg_carrier(demod, &ext_attr->aud_data.carriers)); - CHK_ERROR(aud_ctrl_set_cfg_ass_thres - (demod, &ext_attr->aud_data.ass_thresholds)); - CHK_ERROR(aud_ctr_setl_cfg_auto_sound(demod, &ext_attr->aud_data.auto_sound)); - CHK_ERROR(aud_ctrl_set_cfg_mixer(demod, &ext_attr->aud_data.mixer)); - CHK_ERROR(aud_ctrl_set_cfg_av_sync(demod, &ext_attr->aud_data.av_sync)); - CHK_ERROR(aud_ctrl_set_cfg_output_i2s(demod, &ext_attr->aud_data.i2sdata)); + rc = aud_ctrl_set_cfg_volume(demod, &ext_attr->aud_data.volume); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = aud_ctrl_set_cfg_carrier(demod, &ext_attr->aud_data.carriers); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = aud_ctrl_set_cfg_ass_thres(demod, &ext_attr->aud_data.ass_thresholds); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = aud_ctr_setl_cfg_auto_sound(demod, &ext_attr->aud_data.auto_sound); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = aud_ctrl_set_cfg_mixer(demod, &ext_attr->aud_data.mixer); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = aud_ctrl_set_cfg_av_sync(demod, &ext_attr->aud_data.av_sync); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = aud_ctrl_set_cfg_output_i2s(demod, &ext_attr->aud_data.i2sdata); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* get prescaler from presets */ - CHK_ERROR(aud_ctrl_set_cfg_prescale(demod, &ext_attr->aud_data.prescale)); + rc = aud_ctrl_set_cfg_prescale(demod, &ext_attr->aud_data.prescale); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } - CHK_ERROR(aud_get_modus(demod, &r_modus)); + rc = aud_get_modus(demod, &r_modus); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } w_modus = r_modus; @@ -11702,10 +15906,18 @@ aud_ctrl_set_standard(struct drx_demod_instance *demod, enum drx_aud_standard *s } if (w_modus != r_modus) { - WR16(dev_addr, AUD_DEM_WR_MODUS__A, w_modus); + rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DEM_WR_MODUS__A, w_modus, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } - WR16(dev_addr, AUD_DEM_WR_STANDARD_SEL__A, w_standard); + rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DEM_WR_STANDARD_SEL__A, w_standard, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /**************************************************************************/ /* NOT calling aud_ctrl_set_cfg_volume to avoid interfering standard */ @@ -11716,7 +15928,11 @@ aud_ctrl_set_standard(struct drx_demod_instance *demod, enum drx_aud_standard *s if (ext_attr->aud_data.volume.mute == false) { w_volume |= (u16) ((volume_buffer + AUD_VOLUME_ZERO_DB) << AUD_DSP_WR_VOLUME_VOL_MAIN__B); - WR16(dev_addr, AUD_DSP_WR_VOLUME__A, w_volume); + rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DSP_WR_VOLUME__A, w_volume, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } /* write standard selected */ @@ -11739,7 +15955,7 @@ aud_ctrl_get_standard(struct drx_demod_instance *demod, enum drx_aud_standard *s { struct i2c_device_addr *dev_addr = NULL; struct drxj_data *ext_attr = NULL; - + int rc; u16 r_data = 0; if (standard == NULL) { @@ -11751,13 +15967,21 @@ aud_ctrl_get_standard(struct drx_demod_instance *demod, enum drx_aud_standard *s /* power up */ if (ext_attr->aud_data.audio_is_active == false) { - CHK_ERROR(power_up_aud(demod, true)); + rc = power_up_aud(demod, true); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } ext_attr->aud_data.audio_is_active = true; } *standard = DRX_AUD_STANDARD_UNKNOWN; - RR16(dev_addr, AUD_DEM_RD_STANDARD_RES__A, &r_data); + rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_RD_STANDARD_RES__A, &r_data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* return OK if the detection is not ready yet */ if (r_data >= AUD_DEM_RD_STANDARD_RES_STD_RESULT_DETECTION_STILL_ACTIVE) { @@ -11845,9 +16069,14 @@ static int fm_lock_status(struct drx_demod_instance *demod, enum drx_lock_status *lock_stat) { struct drx_aud_status status; + int rc; /* Check detection of audio carriers */ - CHK_ERROR(aud_ctrl_get_carrier_detect_status(demod, &status)); + rc = aud_ctrl_get_carrier_detect_status(demod, &status); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* locked if either primary or secondary carrier is detected */ if ((status.carrier_a == true) || (status.carrier_b == true)) { @@ -11877,8 +16106,13 @@ static int fm_sig_quality(struct drx_demod_instance *demod, struct drx_sig_quality *sig_quality) { enum drx_lock_status lock_status = DRX_NOT_LOCKED; + int rc; - CHK_ERROR(fm_lock_status(demod, &lock_status)); + rc = fm_lock_status(demod, &lock_status); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if (lock_status == DRX_LOCKED) { sig_quality->indicator = 100; } else { @@ -11918,6 +16152,7 @@ get_oob_lock_status(struct drx_demod_instance *demod, struct i2c_device_addr *dev_addr, enum drx_lock_status *oob_lock) { struct drxjscu_cmd scu_cmd; + int rc; u16 cmd_result[2]; u16 oob_lock_state; @@ -11929,7 +16164,11 @@ get_oob_lock_status(struct drx_demod_instance *demod, scu_cmd.result = cmd_result; scu_cmd.parameter_len = 0; - CHK_ERROR(scu_command(dev_addr, &scu_cmd)); + rc = scu_command(dev_addr, &scu_cmd); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if (scu_cmd.result[1] < 0x4000) { /* 0x00 NOT LOCKED */ @@ -11982,6 +16221,7 @@ get_oob_symbol_rate_offset(struct i2c_device_addr *dev_addr, s32 *symbol_rate_of /* trim 12656250/15625 = 810 */ /* offset = -{(timing_offset*(symbol_rate * 2^-5))/(2^8*810)} [ppm] */ /* offset = -[(symbol_rate * 2^-5)*(timing_offset)/(2^8)]/810 [ppm] */ + int rc; s32 timing_offset = 0; u32 unsigned_timing_offset = 0; s32 division_factor = 810; @@ -11991,7 +16231,11 @@ get_oob_symbol_rate_offset(struct i2c_device_addr *dev_addr, s32 *symbol_rate_of *symbol_rate_offset = 0; /* read data rate */ - SARR16(dev_addr, SCU_RAM_ORX_RF_RX_DATA_RATE__A, &data); + rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_ORX_RF_RX_DATA_RATE__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } switch (data & SCU_RAM_ORX_RF_RX_DATA_RATE__M) { case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC: case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC: @@ -12011,7 +16255,11 @@ get_oob_symbol_rate_offset(struct i2c_device_addr *dev_addr, s32 *symbol_rate_of return (DRX_STS_ERROR); } - RR16(dev_addr, ORX_CON_CTI_DTI_R__A, &data); + rc = DRXJ_DAP.read_reg16func(dev_addr, ORX_CON_CTI_DTI_R__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* convert data to positive and keep information about sign */ if ((data & 0x8000) == 0x8000) { if (data == 0x8000) @@ -12052,6 +16300,9 @@ rw_error: static int get_oob_freq_offset(struct drx_demod_instance *demod, s32 *freq_offset) { + struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL); + struct i2c_device_addr *dev_addr = NULL; + int rc; u16 data = 0; u16 rot = 0; u16 symbol_rateReg = 0; @@ -12063,8 +16314,6 @@ get_oob_freq_offset(struct drx_demod_instance *demod, s32 *freq_offset) u32 data64hi = 0; u32 data64lo = 0; u32 temp_freq_offset = 0; - struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL); - struct i2c_device_addr *dev_addr = NULL; /* check arguments */ if ((demod == NULL) || (freq_offset == NULL)) { @@ -12077,10 +16326,18 @@ get_oob_freq_offset(struct drx_demod_instance *demod, s32 *freq_offset) *freq_offset = 0; /* read sign (spectrum inversion) */ - RR16(dev_addr, ORX_FWP_IQM_FRQ_W__A, &rot); + rc = DRXJ_DAP.read_reg16func(dev_addr, ORX_FWP_IQM_FRQ_W__A, &rot, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* read frequency offset */ - SARR16(dev_addr, SCU_RAM_ORX_FRQ_OFFSET__A, &data); + rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_ORX_FRQ_OFFSET__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* find COARSE frequency offset */ /* coarse_freq_offset = ( 25312500Hz*FRQ_OFFSET >> 21 ); */ if (data & 0x8000) { @@ -12094,7 +16351,11 @@ get_oob_freq_offset(struct drx_demod_instance *demod, s32 *freq_offset) /* get value in KHz */ coarse_freq_offset = coarse_sign * frac(temp_freq_offset, 1000, FRAC_ROUND); /* KHz */ /* read data rate */ - SARR16(dev_addr, SCU_RAM_ORX_RF_RX_DATA_RATE__A, &symbol_rateReg); + rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_ORX_RF_RX_DATA_RATE__A, &symbol_rateReg, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } switch (symbol_rateReg & SCU_RAM_ORX_RF_RX_DATA_RATE__M) { case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC: case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC: @@ -12116,7 +16377,11 @@ get_oob_freq_offset(struct drx_demod_instance *demod, s32 *freq_offset) /* find FINE frequency offset */ /* fine_freq_offset = ( (CORRECTION_VALUE*symbol_rate) >> 18 ); */ - RR16(dev_addr, ORX_CON_CPH_FRQ_R__A, &data); + rc = DRXJ_DAP.read_reg16func(dev_addr, ORX_CON_CPH_FRQ_R__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* at least 5 MSB are 0 so first divide with 2^5 without information loss */ fine_freq_offset = (symbol_rate >> 5); if (data & 0x8000) { @@ -12153,20 +16418,29 @@ rw_error: static int get_oob_frequency(struct drx_demod_instance *demod, s32 *frequency) { + struct i2c_device_addr *dev_addr = NULL; + int rc; u16 data = 0; s32 freq_offset = 0; s32 freq = 0; - struct i2c_device_addr *dev_addr = NULL; dev_addr = demod->my_i2c_dev_addr; *frequency = 0; /* KHz */ - SARR16(dev_addr, SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__A, &data); + rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } freq = (s32) ((s32) data * 50 + 50000L); - CHK_ERROR(get_oob_freq_offset(demod, &freq_offset)); + rc = get_oob_freq_offset(demod, &freq_offset); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } *frequency = freq + freq_offset; @@ -12187,11 +16461,16 @@ rw_error: */ static int get_oobmer(struct i2c_device_addr *dev_addr, u32 *mer) { + int rc; u16 data = 0; *mer = 0; /* READ MER */ - RR16(dev_addr, ORX_EQU_MER_MER_R__A, &data); + rc = DRXJ_DAP.read_reg16func(dev_addr, ORX_EQU_MER_MER_R__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } switch (data) { case 0: /* fall through */ case 1: @@ -12328,11 +16607,16 @@ rw_error: */ static int set_orx_nsu_aox(struct drx_demod_instance *demod, bool active) { - u16 data = 0; struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + int rc; + u16 data = 0; /* Configure NSU_AOX */ - RR16(dev_addr, ORX_NSU_AOX_STDBY_W__A, &data); + rc = DRXJ_DAP.read_reg16func(dev_addr, ORX_NSU_AOX_STDBY_W__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if (!active) { data &= ((~ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON) @@ -12354,7 +16638,11 @@ static int set_orx_nsu_aox(struct drx_demod_instance *demod, bool active) | ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON); } - WR16(dev_addr, ORX_NSU_AOX_STDBY_W__A, data); + rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_NSU_AOX_STDBY_W__A, data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } return (DRX_STS_OK); rw_error: @@ -12388,6 +16676,7 @@ rw_error: static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_param) { #ifndef DRXJ_DIGITAL_ONLY + int rc; s32 freq = 0; /* KHz */ struct i2c_device_addr *dev_addr = NULL; struct drxj_data *ext_attr = NULL; @@ -12424,9 +16713,21 @@ static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_par scu_cmd.parameter_len = 0; scu_cmd.result_len = 1; scu_cmd.result = cmd_result; - CHK_ERROR(scu_command(dev_addr, &scu_cmd)); - CHK_ERROR(set_orx_nsu_aox(demod, false)); - WR16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP); + rc = scu_command(dev_addr, &scu_cmd); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = set_orx_nsu_aox(demod, false); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } ext_attr->oob_power_on = false; return (DRX_STS_OK); @@ -12454,13 +16755,21 @@ static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_par /*********/ /* Stop */ /*********/ - WR16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP); + rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB | SCU_RAM_COMMAND_CMD_DEMOD_STOP; scu_cmd.parameter_len = 0; scu_cmd.result_len = 1; scu_cmd.result = cmd_result; - CHK_ERROR(scu_command(dev_addr, &scu_cmd)); + rc = scu_command(dev_addr, &scu_cmd); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /*********/ /* Reset */ /*********/ @@ -12469,7 +16778,11 @@ static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_par scu_cmd.parameter_len = 0; scu_cmd.result_len = 1; scu_cmd.result = cmd_result; - CHK_ERROR(scu_command(dev_addr, &scu_cmd)); + rc = scu_command(dev_addr, &scu_cmd); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /***********/ /* SET_ENV */ /***********/ @@ -12541,94 +16854,294 @@ static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_par scu_cmd.result_len = 1; scu_cmd.result = cmd_result; mode_index = mode_val[(set_param_parameters[0] & 0xC0) >> 6]; - CHK_ERROR(scu_command(dev_addr, &scu_cmd)); - - WR16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA); /* Write magic word to enable pdr reg write */ - WR16(dev_addr, SIO_PDR_OOB_CRX_CFG__A, - OOB_CRX_DRIVE_STRENGTH << SIO_PDR_OOB_CRX_CFG_DRIVE__B - | 0x03 << SIO_PDR_OOB_CRX_CFG_MODE__B); - WR16(dev_addr, SIO_PDR_OOB_DRX_CFG__A, - OOB_DRX_DRIVE_STRENGTH << SIO_PDR_OOB_DRX_CFG_DRIVE__B - | 0x03 << SIO_PDR_OOB_DRX_CFG_MODE__B); - WR16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000); /* Write magic word to disable pdr reg write */ - - WR16(dev_addr, ORX_TOP_COMM_KEY__A, 0); - WR16(dev_addr, ORX_FWP_AAG_LEN_W__A, 16000); - WR16(dev_addr, ORX_FWP_AAG_THR_W__A, 40); + rc = scu_command(dev_addr, &scu_cmd); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Write magic word to enable pdr reg write */ + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_OOB_CRX_CFG__A, OOB_CRX_DRIVE_STRENGTH << SIO_PDR_OOB_CRX_CFG_DRIVE__B | 0x03 << SIO_PDR_OOB_CRX_CFG_MODE__B, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_OOB_DRX_CFG__A, OOB_DRX_DRIVE_STRENGTH << SIO_PDR_OOB_DRX_CFG_DRIVE__B | 0x03 << SIO_PDR_OOB_DRX_CFG_MODE__B, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Write magic word to disable pdr reg write */ + + rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_TOP_COMM_KEY__A, 0, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_FWP_AAG_LEN_W__A, 16000, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_FWP_AAG_THR_W__A, 40, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* ddc */ - WR16(dev_addr, ORX_DDC_OFO_SET_W__A, ORX_DDC_OFO_SET_W__PRE); + rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_DDC_OFO_SET_W__A, ORX_DDC_OFO_SET_W__PRE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* nsu */ - WR16(dev_addr, ORX_NSU_AOX_LOPOW_W__A, ext_attr->oob_lo_pow); + rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_NSU_AOX_LOPOW_W__A, ext_attr->oob_lo_pow, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* initialization for target mode */ - WR16(dev_addr, SCU_RAM_ORX_TARGET_MODE__A, - SCU_RAM_ORX_TARGET_MODE_2048KBPS_SQRT); - WR16(dev_addr, SCU_RAM_ORX_FREQ_GAIN_CORR__A, - SCU_RAM_ORX_FREQ_GAIN_CORR_2048KBPS); + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_TARGET_MODE__A, SCU_RAM_ORX_TARGET_MODE_2048KBPS_SQRT, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_FREQ_GAIN_CORR__A, SCU_RAM_ORX_FREQ_GAIN_CORR_2048KBPS, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Reset bits for timing and freq. recovery */ - WR16(dev_addr, SCU_RAM_ORX_RST_CPH__A, 0x0001); - WR16(dev_addr, SCU_RAM_ORX_RST_CTI__A, 0x0002); - WR16(dev_addr, SCU_RAM_ORX_RST_KRN__A, 0x0004); - WR16(dev_addr, SCU_RAM_ORX_RST_KRP__A, 0x0008); + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_RST_CPH__A, 0x0001, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_RST_CTI__A, 0x0002, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_RST_KRN__A, 0x0004, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_RST_KRP__A, 0x0008, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* AGN_LOCK = {2048>>3, -2048, 8, -8, 0, 1}; */ - WR16(dev_addr, SCU_RAM_ORX_AGN_LOCK_TH__A, 2048 >> 3); - WR16(dev_addr, SCU_RAM_ORX_AGN_LOCK_TOTH__A, (u16) (-2048)); - WR16(dev_addr, SCU_RAM_ORX_AGN_ONLOCK_TTH__A, 8); - WR16(dev_addr, SCU_RAM_ORX_AGN_UNLOCK_TTH__A, (u16) (-8)); - WR16(dev_addr, SCU_RAM_ORX_AGN_LOCK_MASK__A, 1); + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_AGN_LOCK_TH__A, 2048 >> 3, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_AGN_LOCK_TOTH__A, (u16)(-2048), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_AGN_ONLOCK_TTH__A, 8, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_AGN_UNLOCK_TTH__A, (u16)(-8), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_AGN_LOCK_MASK__A, 1, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* DGN_LOCK = {10, -2048, 8, -8, 0, 1<<1}; */ - WR16(dev_addr, SCU_RAM_ORX_DGN_LOCK_TH__A, 10); - WR16(dev_addr, SCU_RAM_ORX_DGN_LOCK_TOTH__A, (u16) (-2048)); - WR16(dev_addr, SCU_RAM_ORX_DGN_ONLOCK_TTH__A, 8); - WR16(dev_addr, SCU_RAM_ORX_DGN_UNLOCK_TTH__A, (u16) (-8)); - WR16(dev_addr, SCU_RAM_ORX_DGN_LOCK_MASK__A, 1 << 1); + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_DGN_LOCK_TH__A, 10, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_DGN_LOCK_TOTH__A, (u16)(-2048), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_DGN_ONLOCK_TTH__A, 8, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_DGN_UNLOCK_TTH__A, (u16)(-8), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_DGN_LOCK_MASK__A, 1 << 1, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* FRQ_LOCK = {15,-2048, 8, -8, 0, 1<<2}; */ - WR16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TH__A, 17); - WR16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TOTH__A, (u16) (-2048)); - WR16(dev_addr, SCU_RAM_ORX_FRQ_ONLOCK_TTH__A, 8); - WR16(dev_addr, SCU_RAM_ORX_FRQ_UNLOCK_TTH__A, (u16) (-8)); - WR16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_MASK__A, 1 << 2); + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TH__A, 17, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TOTH__A, (u16)(-2048), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_FRQ_ONLOCK_TTH__A, 8, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_FRQ_UNLOCK_TTH__A, (u16)(-8), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_FRQ_LOCK_MASK__A, 1 << 2, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* PHA_LOCK = {5000, -2048, 8, -8, 0, 1<<3}; */ - WR16(dev_addr, SCU_RAM_ORX_PHA_LOCK_TH__A, 3000); - WR16(dev_addr, SCU_RAM_ORX_PHA_LOCK_TOTH__A, (u16) (-2048)); - WR16(dev_addr, SCU_RAM_ORX_PHA_ONLOCK_TTH__A, 8); - WR16(dev_addr, SCU_RAM_ORX_PHA_UNLOCK_TTH__A, (u16) (-8)); - WR16(dev_addr, SCU_RAM_ORX_PHA_LOCK_MASK__A, 1 << 3); + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_PHA_LOCK_TH__A, 3000, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_PHA_LOCK_TOTH__A, (u16)(-2048), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_PHA_ONLOCK_TTH__A, 8, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_PHA_UNLOCK_TTH__A, (u16)(-8), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_PHA_LOCK_MASK__A, 1 << 3, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* TIM_LOCK = {300, -2048, 8, -8, 0, 1<<4}; */ - WR16(dev_addr, SCU_RAM_ORX_TIM_LOCK_TH__A, 400); - WR16(dev_addr, SCU_RAM_ORX_TIM_LOCK_TOTH__A, (u16) (-2048)); - WR16(dev_addr, SCU_RAM_ORX_TIM_ONLOCK_TTH__A, 8); - WR16(dev_addr, SCU_RAM_ORX_TIM_UNLOCK_TTH__A, (u16) (-8)); - WR16(dev_addr, SCU_RAM_ORX_TIM_LOCK_MASK__A, 1 << 4); + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_TIM_LOCK_TH__A, 400, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_TIM_LOCK_TOTH__A, (u16)(-2048), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_TIM_ONLOCK_TTH__A, 8, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_TIM_UNLOCK_TTH__A, (u16)(-8), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_TIM_LOCK_MASK__A, 1 << 4, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* EQU_LOCK = {20, -2048, 8, -8, 0, 1<<5}; */ - WR16(dev_addr, SCU_RAM_ORX_EQU_LOCK_TH__A, 20); - WR16(dev_addr, SCU_RAM_ORX_EQU_LOCK_TOTH__A, (u16) (-2048)); - WR16(dev_addr, SCU_RAM_ORX_EQU_ONLOCK_TTH__A, 4); - WR16(dev_addr, SCU_RAM_ORX_EQU_UNLOCK_TTH__A, (u16) (-4)); - WR16(dev_addr, SCU_RAM_ORX_EQU_LOCK_MASK__A, 1 << 5); + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_EQU_LOCK_TH__A, 20, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_EQU_LOCK_TOTH__A, (u16)(-2048), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_EQU_ONLOCK_TTH__A, 4, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_EQU_UNLOCK_TTH__A, (u16)(-4), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_EQU_LOCK_MASK__A, 1 << 5, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* PRE-Filter coefficients (PFI) */ - WRB(dev_addr, ORX_FWP_PFI_A_W__A, sizeof(pfi_coeffs[mode_index]), - ((u8 *)pfi_coeffs[mode_index])); - WR16(dev_addr, ORX_TOP_MDE_W__A, mode_index); + rc = DRXJ_DAP.write_block_func(dev_addr, ORX_FWP_PFI_A_W__A, sizeof(pfi_coeffs[mode_index]), ((u8 *)pfi_coeffs[mode_index]), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_TOP_MDE_W__A, mode_index, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* NYQUIST-Filter coefficients (NYQ) */ for (i = 0; i < (NYQFILTERLEN + 1) / 2; i++) { - WR16(dev_addr, ORX_FWP_NYQ_ADR_W__A, i); - WR16(dev_addr, ORX_FWP_NYQ_COF_RW__A, - nyquist_coeffs[mode_index][i]); + rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_FWP_NYQ_ADR_W__A, i, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_FWP_NYQ_COF_RW__A, nyquist_coeffs[mode_index][i], 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_FWP_NYQ_ADR_W__A, 31, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_ACTIVE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; } - WR16(dev_addr, ORX_FWP_NYQ_ADR_W__A, 31); - WR16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_ACTIVE); /*********/ /* Start */ /*********/ @@ -12637,10 +17150,22 @@ static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_par scu_cmd.parameter_len = 0; scu_cmd.result_len = 1; scu_cmd.result = cmd_result; - CHK_ERROR(scu_command(dev_addr, &scu_cmd)); + rc = scu_command(dev_addr, &scu_cmd); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } - CHK_ERROR(set_orx_nsu_aox(demod, true)); - WR16(dev_addr, ORX_NSU_AOX_STHR_W__A, ext_attr->oob_pre_saw); + rc = set_orx_nsu_aox(demod, true); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_NSU_AOX_STHR_W__A, ext_attr->oob_pre_saw, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } ext_attr->oob_power_on = true; @@ -12661,6 +17186,7 @@ static int ctrl_get_oob(struct drx_demod_instance *demod, struct drxoob_status *oob_status) { #ifndef DRXJ_DIGITAL_ONLY + int rc; struct i2c_device_addr *dev_addr = NULL; struct drxj_data *ext_attr = NULL; u16 data = 0; @@ -12676,17 +17202,52 @@ ctrl_get_oob(struct drx_demod_instance *demod, struct drxoob_status *oob_status) if (ext_attr->oob_power_on == false) return (DRX_STS_ERROR); - RR16(dev_addr, ORX_DDC_OFO_SET_W__A, &data); - RR16(dev_addr, ORX_NSU_TUN_RFGAIN_W__A, &data); - RR16(dev_addr, ORX_FWP_AAG_THR_W__A, &data); - SARR16(dev_addr, SCU_RAM_ORX_DGN_KI__A, &data); - RR16(dev_addr, ORX_FWP_SRC_DGN_W__A, &data); + rc = DRXJ_DAP.read_reg16func(dev_addr, ORX_DDC_OFO_SET_W__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.read_reg16func(dev_addr, ORX_NSU_TUN_RFGAIN_W__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.read_reg16func(dev_addr, ORX_FWP_AAG_THR_W__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_ORX_DGN_KI__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.read_reg16func(dev_addr, ORX_FWP_SRC_DGN_W__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } - CHK_ERROR(get_oob_lock_status(demod, dev_addr, &oob_status->lock)); - CHK_ERROR(get_oob_frequency(demod, &oob_status->frequency)); - CHK_ERROR(get_oobmer(dev_addr, &oob_status->mer)); - CHK_ERROR(get_oob_symbol_rate_offset - (dev_addr, &oob_status->symbol_rate_offset)); + rc = get_oob_lock_status(demod, dev_addr, &oob_status->lock); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = get_oob_frequency(demod, &oob_status->frequency); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = get_oobmer(dev_addr, &oob_status->mer); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = get_oob_symbol_rate_offset(dev_addr, &oob_status->symbol_rate_offset); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } return (DRX_STS_OK); rw_error: @@ -12706,6 +17267,7 @@ ctrl_set_cfg_oob_pre_saw(struct drx_demod_instance *demod, u16 *cfg_data) { struct i2c_device_addr *dev_addr = NULL; struct drxj_data *ext_attr = NULL; + int rc; if (cfg_data == NULL) { return (DRX_STS_INVALID_ARG); @@ -12713,7 +17275,11 @@ ctrl_set_cfg_oob_pre_saw(struct drx_demod_instance *demod, u16 *cfg_data) dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; - WR16(dev_addr, ORX_NSU_AOX_STHR_W__A, *cfg_data); + rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_NSU_AOX_STHR_W__A, *cfg_data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } ext_attr->oob_pre_saw = *cfg_data; return (DRX_STS_OK); rw_error: @@ -12755,6 +17321,7 @@ ctrl_set_cfg_oob_lo_power(struct drx_demod_instance *demod, enum drxj_cfg_oob_lo { struct i2c_device_addr *dev_addr = NULL; struct drxj_data *ext_attr = NULL; + int rc; if (cfg_data == NULL) { return (DRX_STS_INVALID_ARG); @@ -12762,7 +17329,11 @@ ctrl_set_cfg_oob_lo_power(struct drx_demod_instance *demod, enum drxj_cfg_oob_lo dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; - WR16(dev_addr, ORX_NSU_AOX_LOPOW_W__A, *cfg_data); + rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_NSU_AOX_LOPOW_W__A, *cfg_data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } ext_attr->oob_lo_pow = *cfg_data; return (DRX_STS_OK); rw_error: @@ -12816,7 +17387,7 @@ ctrl_get_cfg_oob_lo_power(struct drx_demod_instance *demod, enum drxj_cfg_oob_lo static int ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) { - + int rc; s32 tuner_set_freq = 0; s32 tuner_get_freq = 0; s32 tuner_freq_offset = 0; @@ -12927,7 +17498,11 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) min_symbol_rate = DRXJ_QAM_SYMBOLRATE_MIN; max_symbol_rate = DRXJ_QAM_SYMBOLRATE_MAX; /* config SMA_TX pin to SAW switch mode */ - CHK_ERROR(ctrl_set_uio_cfg(demod, &uio_cfg)); + rc = ctrl_set_uio_cfg(demod, &uio_cfg); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if (channel->symbolrate < min_symbol_rate || channel->symbolrate > max_symbol_rate) { @@ -13019,10 +17594,18 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) return (DRX_STS_INVALID_ARG); } - CHK_ERROR(ctrl_uio_write(demod, &uio1)); + rc = ctrl_uio_write(demod, &uio1); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } #endif /* DRXJ_VSB_ONLY */ - WR16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /*== Tune, fast mode ======================================================*/ if (demod->my_tuner != NULL) { /* Determine tuner mode and freq to tune to ... */ @@ -13089,23 +17672,35 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) if (common_attr->tuner_port_nr == 1) { /* close tuner bridge */ bridge_closed = true; - CHK_ERROR(ctrl_i2c_bridge(demod, &bridge_closed)); + rc = ctrl_i2c_bridge(demod, &bridge_closed); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* set tuner frequency */ } - CHK_ERROR(drxbsp_tuner_set_frequency(demod->my_tuner, - tuner_mode, tuner_set_freq)); + rc = drxbsp_tuner_set_frequency(demod->my_tuner, tuner_mode, tuner_set_freq); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if (common_attr->tuner_port_nr == 1) { /* open tuner bridge */ bridge_closed = false; - CHK_ERROR(ctrl_i2c_bridge(demod, &bridge_closed)); + rc = ctrl_i2c_bridge(demod, &bridge_closed); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } /* Get actual frequency set by tuner and compute offset */ - CHK_ERROR(drxbsp_tuner_get_frequency(demod->my_tuner, - 0, - &tuner_get_freq, - &intermediate_freq)); + rc = drxbsp_tuner_get_frequency(demod->my_tuner, 0, &tuner_get_freq, &intermediate_freq); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } tuner_freq_offset = tuner_get_freq - tuner_set_freq; common_attr->intermediate_freq = intermediate_freq; } else { @@ -13122,8 +17717,16 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) } else { ext_attr->mirror = channel->mirror; } - CHK_ERROR(set_vsb(demod)); - CHK_ERROR(set_frequency(demod, channel, tuner_freq_offset)); + rc = set_vsb(demod); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = set_frequency(demod, channel, tuner_freq_offset); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } break; #ifndef DRXJ_DIGITAL_ONLY case DRX_STANDARD_NTSC: /* fallthrough */ @@ -13138,15 +17741,22 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) } else { ext_attr->mirror = channel->mirror; } - CHK_ERROR(set_atv_channel(demod, - tuner_freq_offset, channel, standard)); + rc = set_atv_channel(demod, tuner_freq_offset, channel, standard); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } break; #endif #ifndef DRXJ_VSB_ONLY case DRX_STANDARD_ITU_A: /* fallthrough */ case DRX_STANDARD_ITU_B: /* fallthrough */ case DRX_STANDARD_ITU_C: - CHK_ERROR(set_qamChannel(demod, channel, tuner_freq_offset)); + rc = set_qamChannel(demod, channel, tuner_freq_offset); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } break; #endif case DRX_STANDARD_UNKNOWN: @@ -13163,16 +17773,27 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) if (common_attr->tuner_port_nr == 1) { /* close tuner bridge */ bridge_closed = true; - CHK_ERROR(ctrl_i2c_bridge(demod, &bridge_closed)); + rc = ctrl_i2c_bridge(demod, &bridge_closed); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } /* set tuner frequency */ - CHK_ERROR(drxbsp_tuner_set_frequency(demod->my_tuner, - tuner_mode, tuner_set_freq)); + rc = drxbsp_tuner_set_frequency(demod->my_tuner, tuner_mode, tuner_set_freq); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if (common_attr->tuner_port_nr == 1) { /* open tuner bridge */ bridge_closed = false; - CHK_ERROR(ctrl_i2c_bridge(demod, &bridge_closed)); + rc = ctrl_i2c_bridge(demod, &bridge_closed); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } } @@ -13200,6 +17821,7 @@ ctrl_get_channel(struct drx_demod_instance *demod, struct drx_channel *channel) { struct i2c_device_addr *dev_addr = NULL; struct drxj_data *ext_attr = NULL; + int rc; enum drx_lock_status lock_status = DRX_NOT_LOCKED; enum drx_standard standard = DRX_STANDARD_UNKNOWN; struct drx_common_attr *common_attr = NULL; @@ -13244,10 +17866,11 @@ ctrl_get_channel(struct drx_demod_instance *demod, struct drx_channel *channel) bool tuner_mirror = common_attr->mirror_freq_spect ? false : true; /* Get frequency from tuner */ - CHK_ERROR(drxbsp_tuner_get_frequency(demod->my_tuner, - 0, - &(channel->frequency), - &intermediate_freq)); + rc = drxbsp_tuner_get_frequency(demod->my_tuner, 0, &(channel->frequency), &intermediate_freq); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } tuner_freq_offset = channel->frequency - ext_attr->frequency; if (tuner_mirror == true) { /* positive image */ @@ -13266,9 +17889,17 @@ ctrl_get_channel(struct drx_demod_instance *demod, struct drx_channel *channel) } /* check lock status */ - CHK_ERROR(ctrl_lock_status(demod, &lock_status)); + rc = ctrl_lock_status(demod, &lock_status); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if ((lock_status == DRX_LOCKED) || (lock_status == DRXJ_DEMOD_LOCK)) { - ARR32(dev_addr, IQM_RC_RATE_LO__A, &iqm_rc_rateLo); + rc = drxj_dap_atomic_read_reg32(dev_addr, IQM_RC_RATE_LO__A, &iqm_rc_rateLo, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } adc_frequency = (common_attr->sys_clock_freq * 1000) / 3; channel->symbolrate = @@ -13278,7 +17909,11 @@ ctrl_get_channel(struct drx_demod_instance *demod, struct drx_channel *channel) case DRX_STANDARD_8VSB: channel->bandwidth = DRX_BANDWIDTH_6MHZ; /* get the channel frequency */ - CHK_ERROR(get_ctl_freq_offset(demod, &ctl_freq_offset)); + rc = get_ctl_freq_offset(demod, &ctl_freq_offset); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } channel->frequency -= ctl_freq_offset; /* get the channel constellation */ channel->constellation = DRX_CONSTELLATION_AUTO; @@ -13289,8 +17924,11 @@ ctrl_get_channel(struct drx_demod_instance *demod, struct drx_channel *channel) case DRX_STANDARD_ITU_C: { /* get the channel frequency */ - CHK_ERROR(get_ctl_freq_offset - (demod, &ctl_freq_offset)); + rc = get_ctl_freq_offset(demod, &ctl_freq_offset); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } channel->frequency -= ctl_freq_offset; if (standard == DRX_STANDARD_ITU_B) { @@ -13342,7 +17980,11 @@ ctrl_get_channel(struct drx_demod_instance *demod, struct drx_channel *channel) cmd_scu.result_len = 3; cmd_scu.parameter = NULL; cmd_scu.result = cmd_result; - CHK_ERROR(scu_command(dev_addr, &cmd_scu)); + rc = scu_command(dev_addr, &cmd_scu); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } channel->interleavemode = (enum drx_interleave_mode) (cmd_scu. @@ -13386,7 +18028,11 @@ ctrl_get_channel(struct drx_demod_instance *demod, struct drx_channel *channel) case DRX_STANDARD_PAL_SECAM_L: case DRX_STANDARD_PAL_SECAM_LP: case DRX_STANDARD_FM: - CHK_ERROR(get_atv_channel(demod, channel, standard)); + rc = get_atv_channel(demod, channel, standard); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } break; #endif case DRX_STANDARD_UNKNOWN: /* fall trough */ @@ -13451,6 +18097,7 @@ ctrl_sig_quality(struct drx_demod_instance *demod, struct drx_sig_quality *sig_q { struct i2c_device_addr *dev_addr = NULL; struct drxj_data *ext_attr = NULL; + int rc; enum drx_standard standard = DRX_STANDARD_UNKNOWN; enum drx_lock_status lock_status = DRX_NOT_LOCKED; u16 min_mer = 0; @@ -13467,14 +18114,25 @@ ctrl_sig_quality(struct drx_demod_instance *demod, struct drx_sig_quality *sig_q /* get basic information */ dev_addr = demod->my_i2c_dev_addr; - CHK_ERROR(ctrl_lock_status(demod, &lock_status)); + rc = ctrl_lock_status(demod, &lock_status); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } switch (standard) { case DRX_STANDARD_8VSB: #ifdef DRXJ_SIGNAL_ACCUM_ERR - CHK_ERROR(get_acc_pkt_err(demod, &sig_quality->packet_error)); + rc = get_acc_pkt_err(demod, &sig_quality->packet_error); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } #else - CHK_ERROR(get_vsb_post_rs_pck_err - (dev_addr, &sig_quality->packet_error)); + rc = get_vsb_post_rs_pck_err(dev_addr, &sig_quality->packet_error); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } #endif if (lock_status != DRXJ_DEMOD_LOCK && lock_status != DRX_LOCKED) { sig_quality->post_viterbi_ber = 500000; @@ -13482,11 +18140,21 @@ ctrl_sig_quality(struct drx_demod_instance *demod, struct drx_sig_quality *sig_q sig_quality->pre_viterbi_ber = 0; } else { /* PostViterbi is compute in steps of 10^(-6) */ - CHK_ERROR(get_vs_bpre_viterbi_ber - (dev_addr, &sig_quality->pre_viterbi_ber)); - CHK_ERROR(get_vs_bpost_viterbi_ber - (dev_addr, &sig_quality->post_viterbi_ber)); - CHK_ERROR(get_vsbmer(dev_addr, &sig_quality->MER)); + rc = get_vs_bpre_viterbi_ber(dev_addr, &sig_quality->pre_viterbi_ber); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = get_vs_bpost_viterbi_ber(dev_addr, &sig_quality->post_viterbi_ber); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = get_vsbmer(dev_addr, &sig_quality->MER); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } min_mer = 20; max_mer = 360; @@ -13501,7 +18169,11 @@ ctrl_sig_quality(struct drx_demod_instance *demod, struct drx_sig_quality *sig_q case DRX_STANDARD_ITU_A: case DRX_STANDARD_ITU_B: case DRX_STANDARD_ITU_C: - CHK_ERROR(ctrl_get_qam_sig_quality(demod, sig_quality)); + rc = ctrl_get_qam_sig_quality(demod, sig_quality); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if (lock_status != DRXJ_DEMOD_LOCK && lock_status != DRX_LOCKED) { switch (ext_attr->constellation) { case DRX_CONSTELLATION_QAM256: @@ -13555,10 +18227,18 @@ ctrl_sig_quality(struct drx_demod_instance *demod, struct drx_sig_quality *sig_q case DRX_STANDARD_PAL_SECAM_L: case DRX_STANDARD_PAL_SECAM_LP: case DRX_STANDARD_NTSC: - CHK_ERROR(atv_sig_quality(demod, sig_quality)); + rc = atv_sig_quality(demod, sig_quality); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } break; case DRX_STANDARD_FM: - CHK_ERROR(fm_sig_quality(demod, sig_quality)); + rc = fm_sig_quality(demod, sig_quality); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } break; #endif default: @@ -13592,6 +18272,7 @@ ctrl_lock_status(struct drx_demod_instance *demod, enum drx_lock_status *lock_st /* *parameter */ NULL, /* *result */ NULL }; + int rc; u16 cmd_result[2] = { 0, 0 }; u16 demod_lock = SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_DEMOD_LOCKED; @@ -13644,7 +18325,11 @@ ctrl_lock_status(struct drx_demod_instance *demod, enum drx_lock_status *lock_st cmd_scu.result_len = 2; cmd_scu.parameter = NULL; cmd_scu.result = cmd_result; - CHK_ERROR(scu_command(dev_addr, &cmd_scu)); + rc = scu_command(dev_addr, &cmd_scu); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* set the lock status */ if (cmd_scu.result[1] < demod_lock) { @@ -13680,6 +18365,7 @@ rw_error: static int ctrl_constel(struct drx_demod_instance *demod, struct drx_complex *complex_nr) { + int rc; enum drx_standard standard = DRX_STANDARD_UNKNOWN; /**< active standard */ @@ -13694,13 +18380,21 @@ ctrl_constel(struct drx_demod_instance *demod, struct drx_complex *complex_nr) /* Read constellation point */ switch (standard) { case DRX_STANDARD_8VSB: - CHK_ERROR(ctrl_get_vsb_constel(demod, complex_nr)); + rc = ctrl_get_vsb_constel(demod, complex_nr); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } break; #ifndef DRXJ_VSB_ONLY case DRX_STANDARD_ITU_A: /* fallthrough */ case DRX_STANDARD_ITU_B: /* fallthrough */ case DRX_STANDARD_ITU_C: - CHK_ERROR(ctrl_get_qam_constel(demod, complex_nr)); + rc = ctrl_get_qam_constel(demod, complex_nr); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } break; #endif case DRX_STANDARD_UNKNOWN: @@ -13729,6 +18423,7 @@ static int ctrl_set_standard(struct drx_demod_instance *demod, enum drx_standard *standard) { struct drxj_data *ext_attr = NULL; + int rc; enum drx_standard prev_standard; /* check arguments */ @@ -13747,11 +18442,19 @@ ctrl_set_standard(struct drx_demod_instance *demod, enum drx_standard *standard) case DRX_STANDARD_ITU_A: /* fallthrough */ case DRX_STANDARD_ITU_B: /* fallthrough */ case DRX_STANDARD_ITU_C: - CHK_ERROR(power_down_qam(demod, false)); + rc = power_down_qam(demod, false); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } break; #endif case DRX_STANDARD_8VSB: - CHK_ERROR(power_down_vsb(demod, false)); + rc = power_down_vsb(demod, false); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } break; #ifndef DRXJ_DIGITAL_ONLY case DRX_STANDARD_NTSC: /* fallthrough */ @@ -13761,7 +18464,11 @@ ctrl_set_standard(struct drx_demod_instance *demod, enum drx_standard *standard) case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */ case DRX_STANDARD_PAL_SECAM_LP: - CHK_ERROR(power_down_atv(demod, prev_standard, false)); + rc = power_down_atv(demod, prev_standard, false); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } break; #endif case DRX_STANDARD_UNKNOWN: @@ -13783,11 +18490,22 @@ ctrl_set_standard(struct drx_demod_instance *demod, enum drx_standard *standard) case DRX_STANDARD_ITU_A: /* fallthrough */ case DRX_STANDARD_ITU_B: /* fallthrough */ case DRX_STANDARD_ITU_C: - DUMMY_READ(); + do { + u16 dummy; + rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SCU_RAM_VERSION_HI__A, &dummy, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + }while (0); break; #endif case DRX_STANDARD_8VSB: - CHK_ERROR(set_vsb_leak_n_gain(demod)); + rc = set_vsb_leak_n_gain(demod); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } break; #ifndef DRXJ_DIGITAL_ONLY case DRX_STANDARD_NTSC: /* fallthrough */ @@ -13797,8 +18515,16 @@ ctrl_set_standard(struct drx_demod_instance *demod, enum drx_standard *standard) case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */ case DRX_STANDARD_PAL_SECAM_LP: - CHK_ERROR(set_atv_standard(demod, standard)); - CHK_ERROR(power_up_atv(demod, *standard)); + rc = set_atv_standard(demod, standard); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = power_up_atv(demod, *standard); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } break; #endif default: @@ -13829,6 +18555,7 @@ static int ctrl_get_standard(struct drx_demod_instance *demod, enum drx_standard *standard) { struct drxj_data *ext_attr = NULL; + int rc; ext_attr = (struct drxj_data *) demod->my_ext_attr; /* check arguments */ @@ -13836,7 +18563,14 @@ ctrl_get_standard(struct drx_demod_instance *demod, enum drx_standard *standard) return (DRX_STS_INVALID_ARG); } (*standard) = ext_attr->standard; - DUMMY_READ(); + do { + u16 dummy; + rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SCU_RAM_VERSION_HI__A, &dummy, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + }while (0); return (DRX_STS_OK); rw_error: @@ -13856,6 +18590,7 @@ static int ctrl_get_cfg_symbol_clock_offset(struct drx_demod_instance *demod, s32 *rate_offset) { enum drx_standard standard = DRX_STANDARD_UNKNOWN; + int rc; struct drxj_data *ext_attr = NULL; /* check arguments */ @@ -13872,7 +18607,11 @@ ctrl_get_cfg_symbol_clock_offset(struct drx_demod_instance *demod, s32 *rate_off case DRX_STANDARD_ITU_B: /* fallthrough */ case DRX_STANDARD_ITU_C: #endif - CHK_ERROR(get_str_freq_offset(demod, rate_offset)); + rc = get_str_freq_offset(demod, rate_offset); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } break; case DRX_STANDARD_NTSC: case DRX_STANDARD_UNKNOWN: @@ -13905,6 +18644,7 @@ ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode) struct drx_common_attr *common_attr = (struct drx_common_attr *) NULL; struct drxj_data *ext_attr = (struct drxj_data *) NULL; struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; + int rc; u16 sio_cc_pwd_mode = 0; common_attr = (struct drx_common_attr *) demod->my_common_attr; @@ -13943,7 +18683,11 @@ ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode) /* Check if device needs to be powered up */ if ((common_attr->current_power_mode != DRX_POWER_UP)) { - CHK_ERROR(power_up_device(demod)); + rc = power_up_device(demod); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } if ((*mode == DRX_POWER_UP)) { @@ -13964,10 +18708,18 @@ ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode) case DRX_STANDARD_ITU_A: case DRX_STANDARD_ITU_B: case DRX_STANDARD_ITU_C: - CHK_ERROR(power_down_qam(demod, true)); + rc = power_down_qam(demod, true); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } break; case DRX_STANDARD_8VSB: - CHK_ERROR(power_down_vsb(demod, true)); + rc = power_down_vsb(demod, true); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } break; case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ @@ -13976,7 +18728,11 @@ ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode) case DRX_STANDARD_PAL_SECAM_LP: /* fallthrough */ case DRX_STANDARD_NTSC: /* fallthrough */ case DRX_STANDARD_FM: - CHK_ERROR(power_down_atv(demod, ext_attr->standard, true)); + rc = power_down_atv(demod, ext_attr->standard, true); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } break; case DRX_STANDARD_UNKNOWN: /* Do nothing */ @@ -13987,14 +18743,30 @@ ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode) } if (*mode != DRXJ_POWER_DOWN_MAIN_PATH) { - WR16(dev_addr, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode); - WR16(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Initialize HI, wakeup key especially before put IC to sleep */ - CHK_ERROR(init_hi(demod)); + rc = init_hi(demod); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } ext_attr->hi_cfg_ctrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; - CHK_ERROR(hi_cfg_command(demod)); + rc = hi_cfg_command(demod); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } } @@ -14033,6 +18805,7 @@ ctrl_version(struct drx_demod_instance *demod, struct drx_version_list **version struct drxj_data *ext_attr = (struct drxj_data *) (NULL); struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL); + int rc; u16 ucode_major_minor = 0; /* BCD Ma:Ma:Ma:Mi */ u16 ucode_patch = 0; /* BCD Pa:Pa:Pa:Pa */ u16 major = 0; @@ -14059,8 +18832,16 @@ ctrl_version(struct drx_demod_instance *demod, struct drx_version_list **version ext_attr->v_version[0].v_string = ext_attr->v_text[0]; if (common_attr->is_opened == true) { - SARR16(dev_addr, SCU_RAM_VERSION_HI__A, &ucode_major_minor); - SARR16(dev_addr, SCU_RAM_VERSION_LO__A, &ucode_patch); + rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_VERSION_HI__A, &ucode_major_minor, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_VERSION_LO__A, &ucode_patch, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Translate BCD to numbers and string */ /* TODO: The most significant Ma and Pa will be ignored, check with spec */ @@ -14111,11 +18892,31 @@ ctrl_version(struct drx_demod_instance *demod, struct drx_version_list **version /* Device version *************************************** */ /* Check device id */ - RR16(dev_addr, SIO_TOP_COMM_KEY__A, &key); - WR16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA); - RR32(dev_addr, SIO_TOP_JTAGID_LO__A, &jtag); - RR16(dev_addr, SIO_PDR_UIO_IN_HI__A, &bid); - WR16(dev_addr, SIO_TOP_COMM_KEY__A, key); + rc = DRXJ_DAP.read_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, &key, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.read_reg32func(dev_addr, SIO_TOP_JTAGID_LO__A, &jtag, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.read_reg16func(dev_addr, SIO_PDR_UIO_IN_HI__A, &bid, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, key, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } ext_attr->v_version[1].module_type = DRX_MODULE_DEVICE; ext_attr->v_version[1].module_name = device_name; @@ -14183,6 +18984,7 @@ static int ctrl_probe_device(struct drx_demod_instance *demod) enum drx_power_mode org_power_mode = DRX_POWER_UP; int ret_status = DRX_STS_OK; struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL); + int rc; common_attr = (struct drx_common_attr *) demod->my_common_attr; @@ -14198,17 +19000,33 @@ static int ctrl_probe_device(struct drx_demod_instance *demod) org_power_mode = common_attr->current_power_mode; if (demod->my_common_attr->is_opened == false) { - CHK_ERROR(power_up_device(demod)); + rc = power_up_device(demod); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } common_attr->current_power_mode = DRX_POWER_UP; } else { /* Wake-up device, feedback from device */ - CHK_ERROR(ctrl_power_mode(demod, &power_mode)); + rc = ctrl_power_mode(demod, &power_mode); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } /* Initialize HI, wakeup key especially */ - CHK_ERROR(init_hi(demod)); + rc = init_hi(demod); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Check device id */ - RR32(dev_addr, SIO_TOP_JTAGID_LO__A, &jtag); + rc = DRXJ_DAP.read_reg32func(dev_addr, SIO_TOP_JTAGID_LO__A, &jtag, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } jtag = (jtag >> 12) & 0xFFFF; switch (jtag) { case 0x3931: /* fallthrough */ @@ -14230,11 +19048,22 @@ static int ctrl_probe_device(struct drx_demod_instance *demod) /* Device was not opened, return to orginal powermode, feedback from device */ - CHK_ERROR(ctrl_power_mode(demod, &org_power_mode)); + rc = ctrl_power_mode(demod, &org_power_mode); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } else { /* dummy read to make this function fail in case device suddenly disappears after a succesful drx_open */ - DUMMY_READ(); + do { + u16 dummy; + rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SCU_RAM_VERSION_HI__A, &dummy, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + }while (0); } return (ret_status); @@ -14286,6 +19115,7 @@ ctrl_u_codeUpload(struct drx_demod_instance *demod, u8 *mc_data = (u8 *)(NULL); struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); struct drxj_data *ext_attr = (struct drxj_data *) (NULL); + int rc; dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -14461,6 +19291,7 @@ ctrl_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength) { struct drxj_data *ext_attr = NULL; enum drx_standard standard = DRX_STANDARD_UNKNOWN; + int rc; /* Check arguments */ if ((sig_strength == NULL) || (demod == NULL)) { @@ -14479,7 +19310,11 @@ ctrl_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength) case DRX_STANDARD_ITU_B: /* fallthrough */ case DRX_STANDARD_ITU_C: #endif - CHK_ERROR(get_sig_strength(demod, sig_strength)); + rc = get_sig_strength(demod, sig_strength); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } break; #ifndef DRXJ_DIGITAL_ONLY case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ @@ -14489,7 +19324,11 @@ ctrl_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength) case DRX_STANDARD_PAL_SECAM_LP: /* fallthrough */ case DRX_STANDARD_NTSC: /* fallthrough */ case DRX_STANDARD_FM: - CHK_ERROR(get_atv_sig_strength(demod, sig_strength)); + rc = get_atv_sig_strength(demod, sig_strength); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } break; #endif case DRX_STANDARD_UNKNOWN: /* fallthrough */ @@ -14517,6 +19356,7 @@ static int ctrl_get_cfg_oob_misc(struct drx_demod_instance *demod, struct drxj_cfg_oob_misc *misc) { struct i2c_device_addr *dev_addr = NULL; + int rc; u16 lock = 0U; u16 state = 0U; u16 data = 0U; @@ -14531,16 +19371,32 @@ ctrl_get_cfg_oob_misc(struct drx_demod_instance *demod, struct drxj_cfg_oob_misc /* TODO */ /* check if the same registers are used for all standards (QAM/VSB/ATV) */ - RR16(dev_addr, ORX_NSU_TUN_IFGAIN_W__A, &misc->agc.IFAGC); - RR16(dev_addr, ORX_NSU_TUN_RFGAIN_W__A, &misc->agc.RFAGC); - RR16(dev_addr, ORX_FWP_SRC_DGN_W__A, &data); + rc = DRXJ_DAP.read_reg16func(dev_addr, ORX_NSU_TUN_IFGAIN_W__A, &misc->agc.IFAGC, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.read_reg16func(dev_addr, ORX_NSU_TUN_RFGAIN_W__A, &misc->agc.RFAGC, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.read_reg16func(dev_addr, ORX_FWP_SRC_DGN_W__A, &data, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } digital_agc_mant = data & ORX_FWP_SRC_DGN_W_MANT__M; digital_agc_exp = (data & ORX_FWP_SRC_DGN_W_EXP__M) >> ORX_FWP_SRC_DGN_W_EXP__B; misc->agc.digital_agc = digital_agc_mant << digital_agc_exp; - SARR16(dev_addr, SCU_RAM_ORX_SCU_LOCK__A, &lock); + rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_ORX_SCU_LOCK__A, &lock, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } misc->ana_gain_lock = ((lock & 0x0001) ? true : false); misc->dig_gain_lock = ((lock & 0x0002) ? true : false); @@ -14549,7 +19405,11 @@ ctrl_get_cfg_oob_misc(struct drx_demod_instance *demod, struct drxj_cfg_oob_misc misc->sym_timing_lock = ((lock & 0x0010) ? true : false); misc->eq_lock = ((lock & 0x0020) ? true : false); - SARR16(dev_addr, SCU_RAM_ORX_SCU_STATE__A, &state); + rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_ORX_SCU_STATE__A, &state, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } misc->state = (state >> 8) & 0xff; return (DRX_STS_OK); @@ -14569,6 +19429,7 @@ static int ctrl_get_cfg_vsb_misc(struct drx_demod_instance *demod, struct drxj_cfg_vsb_misc *misc) { struct i2c_device_addr *dev_addr = NULL; + int rc; /* check arguments */ if (misc == NULL) { @@ -14576,7 +19437,11 @@ ctrl_get_cfg_vsb_misc(struct drx_demod_instance *demod, struct drxj_cfg_vsb_misc } dev_addr = demod->my_i2c_dev_addr; - CHK_ERROR(get_vsb_symb_err(dev_addr, &misc->symb_error)); + rc = get_vsb_symb_err(dev_addr, &misc->symb_error); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } return (DRX_STS_OK); rw_error: @@ -14806,6 +19671,7 @@ static int ctrl_get_cfg_agc_internal(struct drx_demod_instance *demod, u16 *agc_internal) { struct i2c_device_addr *dev_addr = NULL; + int rc; enum drx_lock_status lock_status = DRX_NOT_LOCKED; struct drxj_data *ext_attr = NULL; u16 iqm_cf_scale_sh = 0; @@ -14820,7 +19686,11 @@ ctrl_get_cfg_agc_internal(struct drx_demod_instance *demod, u16 *agc_internal) dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; - CHK_ERROR(ctrl_lock_status(demod, &lock_status)); + rc = ctrl_lock_status(demod, &lock_status); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if (lock_status != DRXJ_DEMOD_LOCK && lock_status != DRX_LOCKED) { *agc_internal = 0; return DRX_STS_OK; @@ -14854,9 +19724,21 @@ ctrl_get_cfg_agc_internal(struct drx_demod_instance *demod, u16 *agc_internal) return (DRX_STS_INVALID_ARG); } - RR16(dev_addr, IQM_CF_POW__A, &iqm_cf_power); - RR16(dev_addr, IQM_CF_SCALE_SH__A, &iqm_cf_scale_sh); - RR16(dev_addr, IQM_CF_AMP__A, &iqm_cf_amp); + rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_CF_POW__A, &iqm_cf_power, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_CF_SCALE_SH__A, &iqm_cf_scale_sh, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_CF_AMP__A, &iqm_cf_amp, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* IQM_CF_PWR_CORRECTION_dB = 3; P5dB =10*log10(IQM_CF_POW)+12-6*9-IQM_CF_PWR_CORRECTION_dB; */ /* P4dB = P5dB -20*log10(IQM_CF_AMP)-6*10 @@ -14890,6 +19772,7 @@ ctrl_set_cfg_pre_saw(struct drx_demod_instance *demod, struct drxj_cfg_pre_saw * { struct i2c_device_addr *dev_addr = NULL; struct drxj_data *ext_attr = NULL; + int rc; dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -14906,7 +19789,11 @@ ctrl_set_cfg_pre_saw(struct drx_demod_instance *demod, struct drxj_cfg_pre_saw * DRXJ_ISQAMSTD(pre_saw->standard)) || (DRXJ_ISATVSTD(ext_attr->standard) && DRXJ_ISATVSTD(pre_saw->standard))) { - WR16(dev_addr, IQM_AF_PDREF__A, pre_saw->reference); + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_PDREF__A, pre_saw->reference, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } /* Store pre-saw settings */ @@ -14959,6 +19846,7 @@ ctrl_set_cfg_afe_gain(struct drx_demod_instance *demod, struct drxj_cfg_afe_gain { struct i2c_device_addr *dev_addr = NULL; struct drxj_data *ext_attr = NULL; + int rc; u8 gain = 0; /* check arguments */ @@ -14993,8 +19881,14 @@ ctrl_set_cfg_afe_gain(struct drx_demod_instance *demod, struct drxj_cfg_afe_gain gain = (afe_gain->gain - 140 + 6) / 13; /* Only if standard is currently active */ - if (ext_attr->standard == afe_gain->standard) - WR16(dev_addr, IQM_AF_PGA_GAIN__A, gain); + if (ext_attr->standard == afe_gain->standard){ + + rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_PGA_GAIN__A, gain, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + } /* Store AFE Gain settings */ switch (afe_gain->standard) { @@ -15132,12 +20026,17 @@ ctrl_get_cfg_afe_gain(struct drx_demod_instance *demod, struct drxj_cfg_afe_gain static int ctrl_get_fec_meas_seq_count(struct drx_demod_instance *demod, u16 *fec_meas_seq_count) { + int rc; /* check arguments */ if (fec_meas_seq_count == NULL) { return (DRX_STS_INVALID_ARG); } - RR16(demod->my_i2c_dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, fec_meas_seq_count); + rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, fec_meas_seq_count, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } return (DRX_STS_OK); rw_error: @@ -15160,12 +20059,16 @@ rw_error: static int ctrl_get_accum_cr_rs_cw_err(struct drx_demod_instance *demod, u32 *accum_cr_rs_cw_err) { + int rc; if (accum_cr_rs_cw_err == NULL) { return (DRX_STS_INVALID_ARG); } - RR32(demod->my_i2c_dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, - accum_cr_rs_cw_err); + rc = DRXJ_DAP.read_reg32func(demod->my_i2c_dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, accum_cr_rs_cw_err, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } return (DRX_STS_OK); rw_error: @@ -15182,11 +20085,19 @@ rw_error: */ static int ctrl_set_cfg(struct drx_demod_instance *demod, struct drx_cfg *config) { - if (config == NULL) { + int rc; + + if (config == NULL) return (DRX_STS_INVALID_ARG); - } - DUMMY_READ(); + do { + u16 dummy; + rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SCU_RAM_VERSION_HI__A, &dummy, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + }while (0); switch (config->cfg_type) { case DRX_CFG_MPEG_OUTPUT: return ctrl_set_cfg_mpeg_output(demod, @@ -15290,11 +20201,19 @@ rw_error: static int ctrl_get_cfg(struct drx_demod_instance *demod, struct drx_cfg *config) { - if (config == NULL) { + int rc; + + if (config == NULL) return (DRX_STS_INVALID_ARG); - } - DUMMY_READ(); + do { + u16 dummy; + rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SCU_RAM_VERSION_HI__A, &dummy, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + }while (0); switch (config->cfg_type) { case DRX_CFG_MPEG_OUTPUT: @@ -15429,45 +20348,91 @@ int drxj_open(struct drx_demod_instance *demod) u32 driver_version = 0; struct drxu_code_info ucode_info; struct drx_cfg_mpeg_output cfg_mpeg_output; + int rc; /* Check arguments */ - if (demod->my_ext_attr == NULL) { + if (demod->my_ext_attr == NULL) return (DRX_STS_INVALID_ARG); - } dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; common_attr = (struct drx_common_attr *) demod->my_common_attr; - CHK_ERROR(power_up_device(demod)); + rc = power_up_device(demod); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } common_attr->current_power_mode = DRX_POWER_UP; /* has to be in front of setIqmAf and setOrxNsuAox */ - CHK_ERROR(get_device_capabilities(demod)); + rc = get_device_capabilities(demod); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Soft reset of sys- and osc-clockdomain */ - WR16(dev_addr, SIO_CC_SOFT_RST__A, (SIO_CC_SOFT_RST_SYS__M | - SIO_CC_SOFT_RST_OSC__M)); - WR16(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); - CHK_ERROR(drxbsp_hst_sleep(1)); + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_CC_SOFT_RST__A, (SIO_CC_SOFT_RST_SYS__M | SIO_CC_SOFT_RST_OSC__M), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxbsp_hst_sleep(1); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* TODO first make sure that everything keeps working before enabling this */ /* PowerDownAnalogBlocks() */ - WR16(dev_addr, ATV_TOP_STDBY__A, (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE) - | ATV_TOP_STDBY_SIF_STDBY_STANDBY); + rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_STDBY__A, (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE) | ATV_TOP_STDBY_SIF_STDBY_STANDBY, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } - CHK_ERROR(set_iqm_af(demod, false)); - CHK_ERROR(set_orx_nsu_aox(demod, false)); + rc = set_iqm_af(demod, false); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = set_orx_nsu_aox(demod, false); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } - CHK_ERROR(init_hi(demod)); + rc = init_hi(demod); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* disable mpegoutput pins */ cfg_mpeg_output.enable_mpeg_output = false; - CHK_ERROR(ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output)); + rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Stop AUD Inform SetAudio it will need to do all setting */ - CHK_ERROR(power_down_aud(demod)); + rc = power_down_aud(demod); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Stop SCU */ - WR16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP); + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Upload microcode */ if (common_attr->microcode != NULL) { @@ -15479,25 +20444,42 @@ int drxj_open(struct drx_demod_instance *demod) #ifdef DRXJ_SPLIT_UCODE_UPLOAD /* Upload microcode without audio part */ - CHK_ERROR(ctrl_u_codeUpload - (demod, &ucode_info, UCODE_UPLOAD, false)); + rc = ctrl_u_codeUpload(demod, &ucode_info, UCODE_UPLOAD, false); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } #else - CHK_ERROR(drx_ctrl(demod, DRX_CTRL_LOAD_UCODE, &ucode_info)); + rc = drx_ctrl(demod, DRX_CTRL_LOAD_UCODE, &ucode_info); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } #endif /* DRXJ_SPLIT_UCODE_UPLOAD */ if (common_attr->verify_microcode == true) { #ifdef DRXJ_SPLIT_UCODE_UPLOAD - CHK_ERROR(ctrl_u_codeUpload - (demod, &ucode_info, UCODE_VERIFY, false)); + rc = ctrl_u_codeUpload(demod, &ucode_info, UCODE_VERIFY, false); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } #else - CHK_ERROR(drx_ctrl - (demod, DRX_CTRL_VERIFY_UCODE, &ucode_info)); + rc = drx_ctrl(demod, DRX_CTRL_VERIFY_UCODE, &ucode_info); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } #endif /* DRXJ_SPLIT_UCODE_UPLOAD */ } common_attr->is_opened = false; } /* Run SCU for a little while to initialize microcode version numbers */ - WR16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Open tuner instance */ if (demod->my_tuner != NULL) { @@ -15505,14 +20487,26 @@ int drxj_open(struct drx_demod_instance *demod) if (common_attr->tuner_port_nr == 1) { bool bridge_closed = true; - CHK_ERROR(ctrl_i2c_bridge(demod, &bridge_closed)); + rc = ctrl_i2c_bridge(demod, &bridge_closed); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } - CHK_ERROR(drxbsp_tuner_open(demod->my_tuner)); + rc = drxbsp_tuner_open(demod->my_tuner); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if (common_attr->tuner_port_nr == 1) { bool bridge_closed = false; - CHK_ERROR(ctrl_i2c_bridge(demod, &bridge_closed)); + rc = ctrl_i2c_bridge(demod, &bridge_closed); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } common_attr->tuner_min_freq_rf = ((demod->my_tuner)->my_common_attr->min_freq_rf); @@ -15597,7 +20591,11 @@ int drxj_open(struct drx_demod_instance *demod) #endif ext_attr->standard = DRX_STANDARD_UNKNOWN; - CHK_ERROR(smart_ant_init(demod)); + rc = smart_ant_init(demod); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Stamp driver version number in SCU data RAM in BCD code Done to enable field application engineers to retreive drxdriver version @@ -15618,9 +20616,16 @@ int drxj_open(struct drx_demod_instance *demod) driver_version += (VERSION_PATCH / 10) % 10; driver_version <<= 4; driver_version += (VERSION_PATCH % 10); - WR16(dev_addr, SCU_RAM_DRIVER_VER_HI__A, (u16) (driver_version >> 16)); - WR16(dev_addr, SCU_RAM_DRIVER_VER_LO__A, - (u16) (driver_version & 0xFFFF)); + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_DRIVER_VER_HI__A, (u16)(driver_version >> 16), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_DRIVER_VER_LO__A, (u16)(driver_version & 0xFFFF), 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } /* refresh the audio data structure with default */ ext_attr->aud_data = drxj_default_aud_data_g; @@ -15642,27 +20647,52 @@ int drxj_close(struct drx_demod_instance *demod) { struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; struct drx_common_attr *common_attr = demod->my_common_attr; + int rc; enum drx_power_mode power_mode = DRX_POWER_UP; /* power up */ - CHK_ERROR(ctrl_power_mode(demod, &power_mode)); + rc = ctrl_power_mode(demod, &power_mode); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } if (demod->my_tuner != NULL) { /* Check if bridge is used */ if (common_attr->tuner_port_nr == 1) { bool bridge_closed = true; - CHK_ERROR(ctrl_i2c_bridge(demod, &bridge_closed)); + rc = ctrl_i2c_bridge(demod, &bridge_closed); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + rc = drxbsp_tuner_close(demod->my_tuner); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; } - CHK_ERROR(drxbsp_tuner_close(demod->my_tuner)); if (common_attr->tuner_port_nr == 1) { bool bridge_closed = false; - CHK_ERROR(ctrl_i2c_bridge(demod, &bridge_closed)); + rc = ctrl_i2c_bridge(demod, &bridge_closed); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } } }; - WR16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); + rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } power_mode = DRX_POWER_DOWN; - CHK_ERROR(ctrl_power_mode(demod, &power_mode)); + rc = ctrl_power_mode(demod, &power_mode); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; + } return DRX_STS_OK; rw_error: @@ -15865,5 +20895,3 @@ drxj_ctrl(struct drx_demod_instance *demod, u32 ctrl, void *ctrl_data) } return (DRX_STS_OK); } - -/* END OF FILE */ -- cgit v1.1 From 64e49cb9887da807c787449c3b00e1e6281514c7 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Fri, 17 Jan 2014 06:28:28 -0300 Subject: [media] drx-j: don't use parenthesis on return CodingStyle fix: don't use parenthesis on return, as it is not a function. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- .../media/dvb-frontends/drx39xyj/drx39xxj_dummy.c | 4 +- drivers/media/dvb-frontends/drx39xyj/drx_driver.c | 20 +- drivers/media/dvb-frontends/drx39xyj/drxj.c | 790 ++++++++++----------- 3 files changed, 407 insertions(+), 407 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c b/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c index 2cedf7c..448558e 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c @@ -50,12 +50,12 @@ u32 drxbsp_hst_clock(void) int drxbsp_hst_memcmp(void *s1, void *s2, u32 n) { - return (memcmp(s1, s2, (size_t) n)); + return memcmp(s1, s2, (size_t)n); } void *drxbsp_hst_memcpy(void *to, void *from, u32 n) { - return (memcpy(to, from, (size_t) n)); + return memcpy(to, from, (size_t)n); } int drxbsp_i2c_write_read(struct i2c_device_addr *w_dev_addr, diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c index 1b55bb5..2c88e47 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c @@ -373,7 +373,7 @@ scan_function_default(void *scan_context, status = drx_ctrl(demod, DRX_CTRL_SET_CHANNEL, scan_channel); if (status != DRX_STS_OK) { - return (status); + return status; } status = scan_wait_for_lock(demod, &is_locked); @@ -688,7 +688,7 @@ static int ctrl_scan_next(struct drx_demod_instance *demod, u16 *scan_progress) if (next_status != DRX_STS_OK) { common_attr->scan_active = false; - return (next_status); + return next_status; } } if (status != DRX_STS_BUSY) { @@ -702,7 +702,7 @@ static int ctrl_scan_next(struct drx_demod_instance *demod, u16 *scan_progress) /* End of scan reached: call stop-scan, ignore any error */ ctrl_scan_stop(demod); common_attr->scan_active = false; - return (DRX_STS_READY); + return DRX_STS_READY; } common_attr->scan_active = false; @@ -958,7 +958,7 @@ static u16 u_code_compute_crc(u8 *block_data, u16 nr_words) i++; block_data += (sizeof(u16)); } - return ((u16) (crc_word >> 16)); + return (u16)(crc_word >> 16); } /*============================================================================*/ @@ -1110,7 +1110,7 @@ ctrl_u_code(struct drx_demod_instance *demod, mc_data, 0x0000) != DRX_STS_OK) { - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /* if */ }; break; @@ -1151,7 +1151,7 @@ ctrl_u_code(struct drx_demod_instance *demod, mc_dataBuffer, 0x0000) != DRX_STS_OK) { - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } result = @@ -1315,7 +1315,7 @@ int drx_open(struct drx_demod_instance *demod) (demod->my_ext_attr == NULL) || (demod->my_i2c_dev_addr == NULL) || (demod->my_common_attr->is_opened == true)) { - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } status = (*(demod->my_demod_funct->open_func)) (demod); @@ -1392,13 +1392,13 @@ drx_ctrl(struct drx_demod_instance *demod, u32 ctrl, void *ctrl_data) (demod->my_common_attr == NULL) || (demod->my_ext_attr == NULL) || (demod->my_i2c_dev_addr == NULL) ) { - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } if (((demod->my_common_attr->is_opened == false) && (ctrl != DRX_CTRL_PROBE_DEVICE) && (ctrl != DRX_CTRL_VERSION)) ) { - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } if ((DRX_ISPOWERDOWNMODE(demod->my_common_attr->current_power_mode) && @@ -1498,7 +1498,7 @@ drx_ctrl(struct drx_demod_instance *demod, u32 ctrl, void *ctrl_data) return DRX_STS_FUNC_NOT_AVAILABLE; } } else { - return (status); + return status; } return DRX_STS_OK; diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index 13bb381..4e20595 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -1327,7 +1327,7 @@ static u32 log1_times100(u32 x) u32 r = 0; if (x == 0) - return (0); + return 0; /* Scale x (normalize) */ /* computing y in log(x/y) = log(x) - log(y) */ @@ -1367,7 +1367,7 @@ static u32 log1_times100(u32 x) if (y & ((u32) 1)) r++; - return (r); + return r; } @@ -1403,7 +1403,7 @@ static u32 frac_times1e6(u32 N, u32 D) frac++; } - return (frac); + return frac; } /*============================================================================*/ @@ -1446,7 +1446,7 @@ static u32 d_b2lin_times100(u32 gd_b) result *= remainder_fac; /* conversion from 1e-4 to 1e-2 */ - return ((result + 50) / 100); + return (result + 50) / 100; } #ifndef DRXJ_DIGITAL_ONLY @@ -1474,7 +1474,7 @@ static u32 frac(u32 N, u32 D, u16 RC) frac = 0; remainder = 0; - return (frac); + return frac; } if (D > N) { @@ -1507,7 +1507,7 @@ static u32 frac(u32 N, u32 D, u16 RC) } } - return (frac); + return frac; } #endif @@ -1529,7 +1529,7 @@ static u16 u_code_read16(u8 *addr) word <<= 8; word |= ((u16) addr[1]); - return (word); + return word; } /*============================================================================*/ @@ -1553,7 +1553,7 @@ static u32 u_code_read32(u8 *addr) word <<= 8; word |= ((u16) addr[3]); - return (word); + return word; } /*============================================================================*/ @@ -1583,7 +1583,7 @@ static u16 u_code_compute_crc(u8 *block_data, u16 nr_words) i++; block_data += (sizeof(u16)); } - return ((u16) (crc_word >> 16)); + return (u16)(crc_word >> 16); } #endif /* DRXJ_SPLIT_UCODE_UPLOAD */ @@ -1649,7 +1649,7 @@ bool is_handled_by_aud_tr_if(u32 addr) retval = true; } - return (retval); + return retval; } /*============================================================================*/ @@ -2051,7 +2051,7 @@ int drxj_dap_atomic_read_write_block(struct i2c_device_addr *dev_addr, if ((data == NULL) || (dev_addr == NULL) || ((datasize % 2) != 0) || ((datasize / 2) > 8) ) { - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } /* Set up HI parameters to read or write n bytes */ @@ -2103,7 +2103,7 @@ int drxj_dap_atomic_read_write_block(struct i2c_device_addr *dev_addr, return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } @@ -2194,10 +2194,10 @@ static int hi_cfg_command(const struct drx_demod_instance *demod) /* Reset power down flag (set one call only) */ ext_attr->hi_cfg_ctrl &= (~(SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ)); - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /** @@ -2262,7 +2262,7 @@ hi_command(struct i2c_device_addr *dev_addr, const pdrxj_hi_cmd_t cmd, u16 *resu break; default: - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; break; } @@ -2307,9 +2307,9 @@ hi_command(struct i2c_device_addr *dev_addr, const pdrxj_hi_cmd_t cmd, u16 *resu } /* if ( powerdown_cmd == true ) */ - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /** @@ -2379,10 +2379,10 @@ static int init_hi(const struct drx_demod_instance *demod) goto rw_error; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /*============================================================================*/ @@ -2458,7 +2458,7 @@ static int get_device_capabilities(struct drx_demod_instance *demod) common_attr->osc_clock_freq = 4000; break; default: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /* @@ -2592,13 +2592,13 @@ static int get_device_capabilities(struct drx_demod_instance *demod) break; default: /* Unknown device variant */ - return (DRX_STS_ERROR); + return DRX_STS_ERROR; break; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /** @@ -2647,10 +2647,10 @@ static int power_up_device(struct drx_demod_instance *demod) drxbsp_hst_sleep(10); if (retry_count == DRXJ_MAX_RETRIES_POWERUP) { - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } - return (DRX_STS_OK); + return DRX_STS_OK; } /*----------------------------------------------------------------------------*/ @@ -2689,7 +2689,7 @@ ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o /* check arguments */ if ((demod == NULL) || (cfg_data == NULL)) { - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } dev_addr = demod->my_i2c_dev_addr; @@ -2720,7 +2720,7 @@ ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o common_attr->mpeg_cfg.invert_clk = cfg_data->invert_clk; common_attr->mpeg_cfg.static_clk = cfg_data->static_clk; common_attr->mpeg_cfg.bitrate = cfg_data->bitrate; - return (DRX_STS_OK); + return DRX_STS_OK; } rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_OCR_INVERT__A, 0, 0); @@ -2792,7 +2792,7 @@ ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o nr_bits = 4; break; default: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /* ext_attr->constellation */ /* max_bit_rate = symbol_rate * nr_bits * coef */ /* coef = 188/204 */ @@ -2883,7 +2883,7 @@ ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o rcn_rate = 0x005F64D4; break; default: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } break; case DRX_STANDARD_ITU_A: @@ -2896,7 +2896,7 @@ ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o 188; break; default: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /* ext_attr->standard */ } else { /* insert_rs_byte == false */ @@ -2918,7 +2918,7 @@ ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o rcn_rate = 0x005AEC1A; break; default: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } break; case DRX_STANDARD_ITU_A: @@ -2931,7 +2931,7 @@ ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o 204; break; default: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /* ext_attr->standard */ } @@ -3015,7 +3015,7 @@ ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o } break; default: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } bit_rate = common_attr->sys_clock_freq * 1000 / (fec_oc_dto_period + @@ -3318,9 +3318,9 @@ ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o common_attr->mpeg_cfg.static_clk = cfg_data->static_clk; common_attr->mpeg_cfg.bitrate = cfg_data->bitrate; - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /*----------------------------------------------------------------------------*/ @@ -3347,7 +3347,7 @@ ctrl_get_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o u32 data64lo = 0; if (cfg_data == NULL) { - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } dev_addr = demod->my_i2c_dev_addr; common_attr = demod->my_common_attr; @@ -3380,9 +3380,9 @@ ctrl_get_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o cfg_data->bitrate = (data64hi << 7) | (data64lo >> 25); } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /*----------------------------------------------------------------------------*/ @@ -3460,9 +3460,9 @@ static int set_mpegtei_handling(struct drx_demod_instance *demod) goto rw_error; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /*----------------------------------------------------------------------------*/ @@ -3505,9 +3505,9 @@ static int bit_reverse_mpeg_output(struct drx_demod_instance *demod) goto rw_error; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /*----------------------------------------------------------------------------*/ @@ -3537,9 +3537,9 @@ static int set_mpeg_output_clock_rate(struct drx_demod_instance *demod) } } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /*----------------------------------------------------------------------------*/ @@ -3582,9 +3582,9 @@ static int set_mpeg_start_width(struct drx_demod_instance *demod) } } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /*----------------------------------------------------------------------------*/ @@ -3607,7 +3607,7 @@ ctrl_set_cfg_mpeg_output_misc(struct drx_demod_instance *demod, int rc; if (cfg_data == NULL) { - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -3647,9 +3647,9 @@ ctrl_set_cfg_mpeg_output_misc(struct drx_demod_instance *demod, goto rw_error; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /*----------------------------------------------------------------------------*/ @@ -3675,7 +3675,7 @@ ctrl_get_cfg_mpeg_output_misc(struct drx_demod_instance *demod, u16 data = 0; if (cfg_data == NULL) { - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -3694,9 +3694,9 @@ ctrl_get_cfg_mpeg_output_misc(struct drx_demod_instance *demod, (enum drxj_mpeg_output_clock_rate) (data + 1); } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /*----------------------------------------------------------------------------*/ @@ -3720,7 +3720,7 @@ ctrl_get_cfg_hw_cfg(struct drx_demod_instance *demod, struct drxj_cfg_hw_cfg *cf u16 data = 0; if (cfg_data == NULL) - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0); if (rc != DRX_STS_OK) { @@ -3741,9 +3741,9 @@ ctrl_get_cfg_hw_cfg(struct drx_demod_instance *demod, struct drxj_cfg_hw_cfg *cf cfg_data->i2c_speed = (enum drxji2c_speed) ((data >> 6) & 0x1); cfg_data->xtal_freq = (enum drxj_xtal_freq) (data & 0x3); - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /*----------------------------------------------------------------------------*/ @@ -3885,9 +3885,9 @@ static int ctrl_set_uio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg goto rw_error; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /*============================================================================*/ @@ -4132,9 +4132,9 @@ ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data) goto rw_error; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /** @@ -4311,9 +4311,9 @@ static int ctrl_uio_read(struct drx_demod_instance *demod, struct drxuio_data *u goto rw_error; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /*---------------------------------------------------------------------------*/ @@ -4339,7 +4339,7 @@ ctrl_i2c_bridge(struct drx_demod_instance *demod, bool *bridge_closed) /* check arguments */ if (bridge_closed == NULL) { - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } hi_cmd.cmd = SIO_HI_RA_RAM_CMD_BRDCTRL; @@ -4431,9 +4431,9 @@ static int smart_ant_init(struct drx_demod_instance *demod) goto rw_error; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /** @@ -4458,7 +4458,7 @@ ctrl_set_cfg_smart_ant(struct drx_demod_instance *demod, struct drxj_cfg_smart_a /* check arguments */ if (smart_ant == NULL) { - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } if (bit_inverted != ext_attr->smart_ant_inverted @@ -4497,7 +4497,7 @@ ctrl_set_cfg_smart_ant(struct drx_demod_instance *demod, struct drxj_cfg_smart_a DRXJ_MAX_WAITTIME)); if (data & SIO_SA_TX_STATUS_BUSY__M) { - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /* write to smart antenna configuration register */ @@ -4537,7 +4537,7 @@ ctrl_set_cfg_smart_ant(struct drx_demod_instance *demod, struct drxj_cfg_smart_a WR16( dev_addr, SIO_SA_TX_COMMAND__A, data & (~SIO_SA_TX_COMMAND_TX_ENABLE__M) ); */ default: - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } /* Write magic word to enable pdr reg write */ rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); @@ -4546,9 +4546,9 @@ ctrl_set_cfg_smart_ant(struct drx_demod_instance *demod, struct drxj_cfg_smart_a goto rw_error; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } static int scu_command(struct i2c_device_addr *dev_addr, struct drxjscu_cmd *cmd) @@ -4559,7 +4559,7 @@ static int scu_command(struct i2c_device_addr *dev_addr, struct drxjscu_cmd *cmd /* Check param */ if (cmd == NULL) - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; /* Wait until SCU command interface is ready to receive command */ rc = DRXJ_DAP.read_reg16func(dev_addr, SCU_RAM_COMMAND__A, &cur_cmd, 0); @@ -4568,7 +4568,7 @@ static int scu_command(struct i2c_device_addr *dev_addr, struct drxjscu_cmd *cmd goto rw_error; } if (cur_cmd != DRX_SCU_READY) { - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } switch (cmd->parameter_len) { @@ -4607,7 +4607,7 @@ static int scu_command(struct i2c_device_addr *dev_addr, struct drxjscu_cmd *cmd break; default: /* this number of parameters is not supported */ - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_COMMAND__A, cmd->command, 0); if (rc != DRX_STS_OK) { @@ -4627,7 +4627,7 @@ static int scu_command(struct i2c_device_addr *dev_addr, struct drxjscu_cmd *cmd && ((drxbsp_hst_clock() - start_time) < DRXJ_MAX_WAITTIME)); if (cur_cmd != DRX_SCU_READY) { - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /* read results */ @@ -4664,7 +4664,7 @@ static int scu_command(struct i2c_device_addr *dev_addr, struct drxjscu_cmd *cmd break; default: /* this number of parameters is not supported */ - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /* Check if an error was reported by SCU */ @@ -4686,10 +4686,10 @@ static int scu_command(struct i2c_device_addr *dev_addr, struct drxjscu_cmd *cmd } } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /** @@ -4718,7 +4718,7 @@ int drxj_dap_scu_atomic_read_write_block(struct i2c_device_addr *dev_addr, u32 a if ((data == NULL) || (dev_addr == NULL) || ((datasize % 2) != 0) || ((datasize / 2) > 16) ) { - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } set_param_parameters[1] = (u16) ADDR_AT_SCU_SPACE(addr); @@ -4761,7 +4761,7 @@ int drxj_dap_scu_atomic_read_write_block(struct i2c_device_addr *dev_addr, u32 a return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } @@ -4819,7 +4819,7 @@ int drxj_dap_scu_atomic_write_reg16(struct i2c_device_addr *dev_addr, static int ctrl_i2c_write_read(struct drx_demod_instance *demod, struct drxi2c_data *i2c_data) { - return (DRX_STS_FUNC_NOT_AVAILABLE); + return DRX_STS_FUNC_NOT_AVAILABLE; } /* -------------------------------------------------------------------------- */ @@ -4885,9 +4885,9 @@ static int adc_sync_measurement(struct drx_demod_instance *demod, u16 *count) *count = *count + 1; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /** @@ -4942,12 +4942,12 @@ static int adc_synchronization(struct drx_demod_instance *demod) if (count < 2) { /* TODO: implement fallback scenarios */ - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /** @@ -4988,9 +4988,9 @@ static int iqm_set_af(struct drx_demod_instance *demod, bool active) goto rw_error; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /* -------------------------------------------------------------------------- */ @@ -5011,7 +5011,7 @@ ctrl_set_cfg_pdr_safe_mode(struct drx_demod_instance *demod, bool *enable) int rc; if (enable == NULL) - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -5245,10 +5245,10 @@ ctrl_set_cfg_pdr_safe_mode(struct drx_demod_instance *demod, bool *enable) } ext_attr->pdr_safe_mode = *enable; - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /* -------------------------------------------------------------------------- */ @@ -5265,13 +5265,13 @@ ctrl_get_cfg_pdr_safe_mode(struct drx_demod_instance *demod, bool *enabled) struct drxj_data *ext_attr = (struct drxj_data *) NULL; if (enabled == NULL) { - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } ext_attr = (struct drxj_data *) demod->my_ext_attr; *enabled = ext_attr->pdr_safe_mode; - return (DRX_STS_OK); + return DRX_STS_OK; } /** @@ -5589,7 +5589,7 @@ static int init_agc(struct drx_demod_instance *demod) break; #endif default: - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } /* for new AGC interface */ @@ -5759,9 +5759,9 @@ static int init_agc(struct drx_demod_instance *demod) goto rw_error; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /** @@ -5820,7 +5820,7 @@ set_frequency(struct drx_demod_instance *demod, select_pos_image = false; break; default: - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } intermediate_freq = demod->my_common_attr->intermediate_freq; sampling_frequency = demod->my_common_attr->sys_clock_freq / 3; @@ -5861,9 +5861,9 @@ set_frequency(struct drx_demod_instance *demod, ext_attr->iqm_fs_rate_ofs = iqm_fs_rate_ofs; ext_attr->pos_image = (bool) (rf_mirror ^ tuner_mirror ^ select_pos_image); - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /** @@ -5938,9 +5938,9 @@ static int get_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength) *sig_strength = (20 * if_gain / if_agc_sns); } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /** @@ -5986,9 +5986,9 @@ static int get_acc_pkt_err(struct drx_demod_instance *demod, u16 *packet_err) *packet_err = pkt_err; last_pkt_err = data; - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } #endif @@ -6016,10 +6016,10 @@ static int ctrl_set_cfg_reset_pkt_err(struct drx_demod_instance *demod) goto rw_error; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: #endif - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /** @@ -6055,9 +6055,9 @@ static int get_str_freq_offset(struct drx_demod_instance *demod, s32 *str_freq) symbol_frequency_ratio), (symbol_frequency_ratio + (1 << 23))); - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /** @@ -6112,9 +6112,9 @@ static int get_ctl_freq_offset(struct drx_demod_instance *demod, s32 *ctl_freq) *ctl_freq = (s32) ((((data64lo >> 28) & 0xf) | (data64hi << 4)) * sign); - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /*============================================================================*/ @@ -6219,7 +6219,7 @@ set_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, else if (DRXJ_ISATVSTD(agc_settings->standard)) p_agc_settings = &(ext_attr->atv_if_agc_cfg); else - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; /* Set TOP, only if IF-AGC is in AUTO mode */ if (p_agc_settings->ctrl_mode == DRX_AGC_CTRL_AUTO) { @@ -6311,7 +6311,7 @@ set_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, } break; default: - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } /* switch ( agcsettings->ctrl_mode ) */ } @@ -6339,12 +6339,12 @@ set_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, break; #endif default: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /** @@ -6390,7 +6390,7 @@ get_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings) break; #endif default: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } agc_settings->standard = standard; @@ -6407,9 +6407,9 @@ get_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings) } } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /** @@ -6512,7 +6512,7 @@ set_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, else if (DRXJ_ISATVSTD(agc_settings->standard)) p_agc_settings = &(ext_attr->atv_rf_agc_cfg); else - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; /* Restore TOP */ if (p_agc_settings->ctrl_mode == DRX_AGC_CTRL_AUTO) { @@ -6612,7 +6612,7 @@ set_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, } break; default: - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } /* switch ( agcsettings->ctrl_mode ) */ /* always set the top to support configurations without if-loop */ @@ -6647,12 +6647,12 @@ set_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, break; #endif default: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /** @@ -6698,7 +6698,7 @@ get_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings) break; #endif default: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } agc_settings->standard = standard; @@ -6716,9 +6716,9 @@ get_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings) } } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /** @@ -6763,9 +6763,9 @@ static int set_iqm_af(struct drx_demod_instance *demod, bool active) goto rw_error; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /*============================================================================*/ @@ -6871,9 +6871,9 @@ static int power_down_vsb(struct drx_demod_instance *demod, bool primary) goto rw_error; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /** @@ -7087,9 +7087,9 @@ static int set_vsb_leak_n_gain(struct drx_demod_instance *demod) goto rw_error; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /** @@ -7600,9 +7600,9 @@ static int set_vsb(struct drx_demod_instance *demod) goto rw_error; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /** @@ -7639,9 +7639,9 @@ static int get_vsb_post_rs_pck_err(struct i2c_device_addr *dev_addr, u16 *pck_er (u16) frac_times1e6(packet_errorsMant * (1 << packet_errorsExp), (period * prescale * 77)); - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /** @@ -7685,9 +7685,9 @@ static int get_vs_bpost_viterbi_ber(struct i2c_device_addr *dev_addr, u32 *ber) ((bit_errors_exp > 2) ? 1 : 8)); } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /** @@ -7709,9 +7709,9 @@ static int get_vs_bpre_viterbi_ber(struct i2c_device_addr *dev_addr, u32 *ber) frac_times1e6(data, VSB_TOP_MEASUREMENT_PERIOD * SYMBOLS_PER_SEGMENT); - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /** @@ -7747,9 +7747,9 @@ static int get_vsb_symb_err(struct i2c_device_addr *dev_addr, u32 *ser) *ser = (u32) frac_times1e6((symb_errors_mant << symb_errors_exp) * 1000, (period * prescale * 77318)); - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /** @@ -7770,9 +7770,9 @@ static int get_vsbmer(struct i2c_device_addr *dev_addr, u16 *mer) *mer = (u16) (log1_times100(21504) - log1_times100((data_hi << 6) / 52)); - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /*============================================================================*/ @@ -7852,9 +7852,9 @@ ctrl_get_vsb_constel(struct drx_demod_instance *demod, struct drx_complex *compl goto rw_error; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /*============================================================================*/ @@ -7961,9 +7961,9 @@ static int power_down_qam(struct drx_demod_instance *demod, bool primary) goto rw_error; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /*============================================================================*/ @@ -8026,7 +8026,7 @@ set_qam_measurement(struct drx_demod_instance *demod, fec_bits_desired = 8 * symbol_rate; break; default: - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } /* Parameters for Reed-Solomon Decoder */ @@ -8045,7 +8045,7 @@ set_qam_measurement(struct drx_demod_instance *demod, fec_rs_plen = 128 * 7; break; default: - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } ext_attr->fec_rs_plen = fec_rs_plen; /* for getSigQual */ @@ -8078,11 +8078,11 @@ set_qam_measurement(struct drx_demod_instance *demod, fec_oc_snc_fail_period = 25805; break; default: - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } break; default: - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_SNC_FAIL_PERIOD__A, (u16)fec_oc_snc_fail_period, 0); @@ -8145,7 +8145,7 @@ set_qam_measurement(struct drx_demod_instance *demod, * (QAM_TOP_CONSTELLATION_QAM256 + 1); break; default: - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } if (qam_vd_period == 0) { pr_err("error: qam_vd_period is zero!\n"); @@ -8173,9 +8173,9 @@ set_qam_measurement(struct drx_demod_instance *demod, ext_attr->qam_vd_prescale = qam_vd_prescale; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /*============================================================================*/ @@ -8408,9 +8408,9 @@ static int set_qam16(struct drx_demod_instance *demod) goto rw_error; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /*============================================================================*/ @@ -8643,9 +8643,9 @@ static int set_qam32(struct drx_demod_instance *demod) goto rw_error; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /*============================================================================*/ @@ -8878,9 +8878,9 @@ static int set_qam64(struct drx_demod_instance *demod) goto rw_error; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /*============================================================================*/ @@ -9113,9 +9113,9 @@ static int set_qam128(struct drx_demod_instance *demod) goto rw_error; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /*============================================================================*/ @@ -9348,9 +9348,9 @@ static int set_qam256(struct drx_demod_instance *demod) goto rw_error; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /*============================================================================*/ @@ -9528,7 +9528,7 @@ set_qam(struct drx_demod_instance *demod, iqm_rc_stretch = IQM_RC_STRETCH_QAM_B_64; break; default: - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } } else { adc_frequency = (common_attr->sys_clock_freq * 1000) / 3; @@ -9565,7 +9565,7 @@ set_qam(struct drx_demod_instance *demod, set_param_parameters[0] = channel->constellation; /* constellation */ set_param_parameters[1] = DRX_INTERLEAVEMODE_I12_J17; /* interleave mode */ } else { - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } } @@ -9831,7 +9831,7 @@ set_qam(struct drx_demod_instance *demod, } break; default: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /* switch */ } @@ -10049,7 +10049,7 @@ set_qam(struct drx_demod_instance *demod, } break; default: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } } else if (ext_attr->standard == DRX_STANDARD_ITU_C) { rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_c_taps), ((u8 *)qam_c_taps), 0); @@ -10102,7 +10102,7 @@ set_qam(struct drx_demod_instance *demod, } break; default: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /* switch */ } @@ -10187,9 +10187,9 @@ set_qam(struct drx_demod_instance *demod, goto rw_error; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /*============================================================================*/ @@ -10371,9 +10371,9 @@ static int qam_flip_spec(struct drx_demod_instance *demod, struct drx_channel *c goto rw_error; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } @@ -10523,9 +10523,9 @@ qam64auto(struct drx_demod_instance *demod, ); /* Returning control to apllication ... */ - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /** @@ -10606,9 +10606,9 @@ qam256auto(struct drx_demod_instance *demod, ((drxbsp_hst_clock() - start_time) < (DRXJ_QAM_MAX_WAITTIME + timeout_ofs))); - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /** @@ -10784,19 +10784,19 @@ set_qamChannel(struct drx_demod_instance *demod, channel->constellation = DRX_CONSTELLATION_AUTO; } else { channel->constellation = DRX_CONSTELLATION_AUTO; - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } break; default: - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: /* restore starting value */ if (auto_flag) channel->constellation = DRX_CONSTELLATION_AUTO; - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /*============================================================================*/ @@ -10819,7 +10819,7 @@ GetQAMRSErr_count(struct i2c_device_addr *dev_addr, struct drxjrs_errors *rs_err /* check arguments */ if (dev_addr == NULL) { - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } /* all reported errors are received in the */ @@ -10865,9 +10865,9 @@ GetQAMRSErr_count(struct i2c_device_addr *dev_addr, struct drxjrs_errors *rs_err rs_errors->nr_snc_par_fail_count = nr_snc_par_fail_count & FEC_OC_SNC_FAIL_COUNT__M; - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /*============================================================================*/ @@ -10968,7 +10968,7 @@ ctrl_get_qam_sig_quality(struct drx_demod_instance *demod, struct drx_sig_qualit qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM256 << 2; break; default: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /* ------------------------------ */ @@ -11074,9 +11074,9 @@ ctrl_get_qam_sig_quality(struct drx_demod_instance *demod, struct drx_sig_qualit sig_quality->packet_error = ((u16) pkt_errs); #endif - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /** @@ -11181,9 +11181,9 @@ ctrl_get_qam_constel(struct drx_demod_instance *demod, struct drx_complex *compl goto rw_error; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } #endif /* #ifndef DRXJ_VSB_ONLY */ @@ -11445,9 +11445,9 @@ atv_update_config(struct drx_demod_instance *demod, bool force_update) ext_attr->atv_cfg_changed_flags = 0; - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /* -------------------------------------------------------------------------- */ @@ -11467,7 +11467,7 @@ ctrl_set_cfg_atv_output(struct drx_demod_instance *demod, struct drxj_cfg_atv_ou /* Check arguments */ if (output_cfg == NULL) { - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -11506,9 +11506,9 @@ ctrl_set_cfg_atv_output(struct drx_demod_instance *demod, struct drxj_cfg_atv_ou goto rw_error; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /* -------------------------------------------------------------------------- */ @@ -11545,7 +11545,7 @@ ctrl_set_cfg_atv_equ_coef(struct drx_demod_instance *demod, struct drxj_cfg_atv_ (coef->coef1 < ((s16) ~(ATV_TOP_EQU1_EQU_C1__M >> 1))) || (coef->coef2 < ((s16) ~(ATV_TOP_EQU2_EQU_C2__M >> 1))) || (coef->coef3 < ((s16) ~(ATV_TOP_EQU3_EQU_C3__M >> 1)))) { - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } rc = atv_equ_coef_index(ext_attr->standard, &index); @@ -11565,9 +11565,9 @@ ctrl_set_cfg_atv_equ_coef(struct drx_demod_instance *demod, struct drxj_cfg_atv_ goto rw_error; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /* -------------------------------------------------------------------------- */ @@ -11613,9 +11613,9 @@ ctrl_get_cfg_atv_equ_coef(struct drx_demod_instance *demod, struct drxj_cfg_atv_ coef->coef2 = ext_attr->atv_top_equ2[index]; coef->coef3 = ext_attr->atv_top_equ3[index]; - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /* -------------------------------------------------------------------------- */ @@ -11638,7 +11638,7 @@ ctrl_set_cfg_atv_misc(struct drx_demod_instance *demod, struct drxj_cfg_atv_misc ((settings->peak_filter) < (s16) (-8)) || ((settings->peak_filter) > (s16) (15)) || ((settings->noise_filter) > 15)) { - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } /* if */ ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -11659,9 +11659,9 @@ ctrl_set_cfg_atv_misc(struct drx_demod_instance *demod, struct drxj_cfg_atv_misc goto rw_error; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /* -------------------------------------------------------------------------- */ @@ -11691,7 +11691,7 @@ ctrl_get_cfg_atv_misc(struct drx_demod_instance *demod, struct drxj_cfg_atv_misc settings->peak_filter = ext_attr->atv_top_vid_peak; settings->noise_filter = ext_attr->atv_top_noise_th; - return (DRX_STS_OK); + return DRX_STS_OK; } /* -------------------------------------------------------------------------- */ @@ -11739,9 +11739,9 @@ ctrl_get_cfg_atv_output(struct drx_demod_instance *demod, struct drxj_cfg_atv_ou output_cfg->sif_attenuation = (enum drxjsif_attenuation) data; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /* -------------------------------------------------------------------------- */ @@ -11859,9 +11859,9 @@ ctrl_get_cfg_atv_agc_status(struct drx_demod_instance *demod, agc_status->if_agc_loop_gain = ((data & SCU_RAM_AGC_KI_IF__M) >> SCU_RAM_AGC_KI_IF__B); - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /* -------------------------------------------------------------------------- */ @@ -11907,9 +11907,9 @@ static int power_up_atv(struct drx_demod_instance *demod, enum drx_standard stan /* Audio, already done during set standard */ - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } #endif /* #ifndef DRXJ_DIGITAL_ONLY */ @@ -12009,9 +12009,9 @@ power_down_atv(struct drx_demod_instance *demod, enum drx_standard standard, boo goto rw_error; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /* -------------------------------------------------------------------------- */ @@ -12881,7 +12881,7 @@ trouble ? ext_attr->enable_cvbs_output = true; break; default: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /* Common initializations FM & NTSC & B/G & D/K & I & L & LP */ @@ -13113,9 +13113,9 @@ trouble ? } } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } #endif @@ -13192,9 +13192,9 @@ set_atv_channel(struct drx_demod_instance *demod, ext_attr->detectedRDS = (bool)false; }*/ - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } #endif @@ -13276,14 +13276,14 @@ get_atv_channel(struct drx_demod_instance *demod, channel->bandwidth = DRX_BANDWIDTH_UNKNOWN; break; default: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } channel->frequency -= offset; - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /* -------------------------------------------------------------------------- */ @@ -13363,7 +13363,7 @@ get_atv_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength) digital_min_gain = 0; /* taken from ucode */ break; default: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; break; } rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_AGC_RF__A, &rf_curr_gain, 0); @@ -13415,9 +13415,9 @@ get_atv_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength) rf_weight * rf_strength + if_weight * if_strength); *sig_strength /= 100; - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /* -------------------------------------------------------------------------- */ @@ -13473,9 +13473,9 @@ atv_sig_quality(struct drx_demod_instance *demod, struct drx_sig_quality *sig_qu (30 * (0x7FF - quality_indicator)) / (0x7FF - 0x701); } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } #endif /* DRXJ_DIGITAL_ONLY */ @@ -15628,7 +15628,7 @@ aud_ctrl_set_cfg_prescale(struct drx_demod_instance *demod, struct drx_cfg_aud_p /* shift before writing to register */ nicam_prescaler <<= 8; } else { - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } /* end of setting NICAM Prescaler */ @@ -16085,10 +16085,10 @@ fm_lock_status(struct drx_demod_instance *demod, enum drx_lock_status *lock_stat *lock_stat = DRX_NOT_LOCKED; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /*============================================================================*/ @@ -16119,10 +16119,10 @@ fm_sig_quality(struct drx_demod_instance *demod, struct drx_sig_quality *sig_qua sig_quality->indicator = 0; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } #endif @@ -16192,9 +16192,9 @@ get_oob_lock_status(struct drx_demod_instance *demod, /* *oob_lock = scu_cmd.result[1]; */ - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /** @@ -16252,7 +16252,7 @@ get_oob_symbol_rate_offset(struct i2c_device_addr *dev_addr, s32 *symbol_rate_of symbol_rate = 1544000; /* bps */ break; default: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } rc = DRXJ_DAP.read_reg16func(dev_addr, ORX_CON_CTI_DTI_R__A, &data, 0); @@ -16282,9 +16282,9 @@ get_oob_symbol_rate_offset(struct i2c_device_addr *dev_addr, s32 *symbol_rate_of *symbol_rate_offset = timing_offset; - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /** @@ -16372,7 +16372,7 @@ get_oob_freq_offset(struct drx_demod_instance *demod, s32 *freq_offset) symbol_rate = 1544000; break; default: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /* find FINE frequency offset */ @@ -16400,9 +16400,9 @@ get_oob_freq_offset(struct drx_demod_instance *demod, s32 *freq_offset) else *freq_offset = (coarse_freq_offset + fine_freq_offset); - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /** @@ -16444,9 +16444,9 @@ get_oob_frequency(struct drx_demod_instance *demod, s32 *frequency) *frequency = freq + freq_offset; - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /** @@ -16592,9 +16592,9 @@ static int get_oobmer(struct i2c_device_addr *dev_addr, u32 *mer) *mer = 0; break; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } #endif /*#ifndef DRXJ_DIGITAL_ONLY */ @@ -16644,9 +16644,9 @@ static int set_orx_nsu_aox(struct drx_demod_instance *demod, bool active) goto rw_error; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /** @@ -16730,12 +16730,12 @@ static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_par } ext_attr->oob_power_on = false; - return (DRX_STS_OK); + return DRX_STS_OK; } freq = oob_param->frequency; if ((freq < 70000) || (freq > 130000)) - return (DRX_STS_ERROR); + return DRX_STS_ERROR; freq = (freq - 50000) / 50; { @@ -17169,10 +17169,10 @@ static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_par ext_attr->oob_power_on = true; - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: #endif - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /** @@ -17196,11 +17196,11 @@ ctrl_get_oob(struct drx_demod_instance *demod, struct drxoob_status *oob_status) /* check arguments */ if (oob_status == NULL) { - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } if (ext_attr->oob_power_on == false) - return (DRX_STS_ERROR); + return DRX_STS_ERROR; rc = DRXJ_DAP.read_reg16func(dev_addr, ORX_DDC_OFO_SET_W__A, &data, 0); if (rc != DRX_STS_OK) { @@ -17249,10 +17249,10 @@ ctrl_get_oob(struct drx_demod_instance *demod, struct drxoob_status *oob_status) goto rw_error; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: #endif - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /** @@ -17270,7 +17270,7 @@ ctrl_set_cfg_oob_pre_saw(struct drx_demod_instance *demod, u16 *cfg_data) int rc; if (cfg_data == NULL) { - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -17281,9 +17281,9 @@ ctrl_set_cfg_oob_pre_saw(struct drx_demod_instance *demod, u16 *cfg_data) goto rw_error; } ext_attr->oob_pre_saw = *cfg_data; - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } #endif @@ -17300,13 +17300,13 @@ ctrl_get_cfg_oob_pre_saw(struct drx_demod_instance *demod, u16 *cfg_data) struct drxj_data *ext_attr = NULL; if (cfg_data == NULL) { - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } ext_attr = (struct drxj_data *) demod->my_ext_attr; *cfg_data = ext_attr->oob_pre_saw; - return (DRX_STS_OK); + return DRX_STS_OK; } #endif @@ -17324,7 +17324,7 @@ ctrl_set_cfg_oob_lo_power(struct drx_demod_instance *demod, enum drxj_cfg_oob_lo int rc; if (cfg_data == NULL) { - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -17335,9 +17335,9 @@ ctrl_set_cfg_oob_lo_power(struct drx_demod_instance *demod, enum drxj_cfg_oob_lo goto rw_error; } ext_attr->oob_lo_pow = *cfg_data; - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } #endif @@ -17353,13 +17353,13 @@ ctrl_get_cfg_oob_lo_power(struct drx_demod_instance *demod, enum drxj_cfg_oob_lo struct drxj_data *ext_attr = NULL; if (cfg_data == NULL) { - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } ext_attr = (struct drxj_data *) demod->my_ext_attr; *cfg_data = ext_attr->oob_lo_pow; - return (DRX_STS_OK); + return DRX_STS_OK; } #endif /*============================================================================*/ @@ -17434,7 +17434,7 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) break; case DRX_STANDARD_UNKNOWN: default: - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } /* check bandwidth QAM annex B, NTSC and 8VSB */ @@ -17449,7 +17449,7 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) case DRX_BANDWIDTH_8MHZ: /* fall through */ case DRX_BANDWIDTH_7MHZ: /* fall through */ default: - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } } #ifndef DRXJ_DIGITAL_ONLY @@ -17462,7 +17462,7 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) case DRX_BANDWIDTH_6MHZ: /* fall through */ case DRX_BANDWIDTH_UNKNOWN: /* fall through */ default: - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } } /* check bandwidth PAL/SECAM */ @@ -17479,7 +17479,7 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) case DRX_BANDWIDTH_6MHZ: /* fall through */ case DRX_BANDWIDTH_7MHZ: /* fall through */ default: - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } } #endif @@ -17506,7 +17506,7 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) if (channel->symbolrate < min_symbol_rate || channel->symbolrate > max_symbol_rate) { - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } switch (channel->constellation) { @@ -17532,7 +17532,7 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) } break; default: - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } } @@ -17546,7 +17546,7 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) case DRX_CONSTELLATION_QAM64: break; default: - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } switch (channel->interleavemode) { @@ -17571,7 +17571,7 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) case DRX_INTERLEAVEMODE_AUTO: break; default: - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } } @@ -17591,7 +17591,7 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) break; case DRX_BANDWIDTH_UNKNOWN: default: - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } rc = ctrl_uio_write(demod, &uio1); @@ -17641,7 +17641,7 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) break; case DRX_STANDARD_UNKNOWN: default: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /* switch(standard) */ tuner_mode |= TUNER_MODE_SWITCH; @@ -17761,7 +17761,7 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) #endif case DRX_STANDARD_UNKNOWN: default: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /*== Re-tune, slow mode ===================================================*/ @@ -17801,9 +17801,9 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) /* flag the packet error counter reset */ ext_attr->reset_pkt_err_acc = true; - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /*============================================================================= @@ -18015,7 +18015,7 @@ ctrl_get_channel(struct drx_demod_instance *demod, struct drx_channel *channel) default: channel->constellation = DRX_CONSTELLATION_UNKNOWN; - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } } break; @@ -18037,7 +18037,7 @@ ctrl_get_channel(struct drx_demod_instance *demod, struct drx_channel *channel) #endif case DRX_STANDARD_UNKNOWN: /* fall trough */ default: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /* switch ( standard ) */ if (lock_status == DRX_LOCKED) { @@ -18045,9 +18045,9 @@ ctrl_get_channel(struct drx_demod_instance *demod, struct drx_channel *channel) } } /* if ( lock_status == DRX_LOCKED ) */ - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /*============================================================================= @@ -18106,7 +18106,7 @@ ctrl_sig_quality(struct drx_demod_instance *demod, struct drx_sig_quality *sig_q /* Check arguments */ if ((sig_quality == NULL) || (demod == NULL)) { - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -18193,7 +18193,7 @@ ctrl_sig_quality(struct drx_demod_instance *demod, struct drx_sig_quality *sig_q break; default: sig_quality->MER = 0; - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } } @@ -18213,7 +18213,7 @@ ctrl_sig_quality(struct drx_demod_instance *demod, struct drx_sig_quality *sig_q case DRX_CONSTELLATION_QAM16: break; default: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } sig_quality->indicator = mer2indicator(sig_quality->MER, min_mer, threshold_mer, @@ -18242,12 +18242,12 @@ ctrl_sig_quality(struct drx_demod_instance *demod, struct drx_sig_quality *sig_q break; #endif default: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /*============================================================================*/ @@ -18278,7 +18278,7 @@ ctrl_lock_status(struct drx_demod_instance *demod, enum drx_lock_status *lock_st /* check arguments */ if ((demod == NULL) || (lock_stat == NULL)) { - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } dev_addr = demod->my_i2c_dev_addr; @@ -18317,7 +18317,7 @@ ctrl_lock_status(struct drx_demod_instance *demod, enum drx_lock_status *lock_st #endif case DRX_STANDARD_UNKNOWN: /* fallthrough */ default: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /* define the SCU command paramters and execute the command */ @@ -18347,9 +18347,9 @@ ctrl_lock_status(struct drx_demod_instance *demod, enum drx_lock_status *lock_st *lock_stat = DRX_NEVER_LOCK; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /*============================================================================*/ @@ -18371,7 +18371,7 @@ ctrl_constel(struct drx_demod_instance *demod, struct drx_complex *complex_nr) /* check arguments */ if ((demod == NULL) || (complex_nr == NULL)) { - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } /* read device info */ @@ -18399,12 +18399,12 @@ ctrl_constel(struct drx_demod_instance *demod, struct drx_complex *complex_nr) #endif case DRX_STANDARD_UNKNOWN: default: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /*============================================================================*/ @@ -18428,7 +18428,7 @@ ctrl_set_standard(struct drx_demod_instance *demod, enum drx_standard *standard) /* check arguments */ if ((standard == NULL) || (demod == NULL)) { - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -18476,7 +18476,7 @@ ctrl_set_standard(struct drx_demod_instance *demod, enum drx_standard *standard) break; case DRX_STANDARD_AUTO: /* fallthrough */ default: - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } /* @@ -18529,15 +18529,15 @@ ctrl_set_standard(struct drx_demod_instance *demod, enum drx_standard *standard) #endif default: ext_attr->standard = DRX_STANDARD_UNKNOWN; - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; break; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: /* Don't know what the standard is now ... try again */ ext_attr->standard = DRX_STANDARD_UNKNOWN; - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /*============================================================================*/ @@ -18560,7 +18560,7 @@ ctrl_get_standard(struct drx_demod_instance *demod, enum drx_standard *standard) /* check arguments */ if (standard == NULL) { - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } (*standard) = ext_attr->standard; do { @@ -18572,9 +18572,9 @@ ctrl_get_standard(struct drx_demod_instance *demod, enum drx_standard *standard) } }while (0); - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /*============================================================================*/ @@ -18595,7 +18595,7 @@ ctrl_get_cfg_symbol_clock_offset(struct drx_demod_instance *demod, s32 *rate_off /* check arguments */ if (rate_offset == NULL) - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; ext_attr = (struct drxj_data *) demod->my_ext_attr; standard = ext_attr->standard; @@ -18616,12 +18616,12 @@ ctrl_get_cfg_symbol_clock_offset(struct drx_demod_instance *demod, s32 *rate_off case DRX_STANDARD_NTSC: case DRX_STANDARD_UNKNOWN: default: - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /*============================================================================*/ @@ -18653,12 +18653,12 @@ ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode) /* Check arguments */ if (mode == NULL) { - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } /* If already in requested power mode, do nothing */ if (common_attr->current_power_mode == *mode) { - return (DRX_STS_OK); + return DRX_STS_OK; } switch (*mode) { @@ -18677,7 +18677,7 @@ ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode) break; default: /* Unknow sleep mode */ - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; break; } @@ -18739,7 +18739,7 @@ ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode) break; case DRX_STANDARD_AUTO: /* fallthrough */ default: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } if (*mode != DRXJ_POWER_DOWN_MAIN_PATH) { @@ -18772,9 +18772,9 @@ ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode) common_attr->current_power_mode = *mode; - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /*============================================================================*/ @@ -18957,11 +18957,11 @@ ctrl_version(struct drx_demod_instance *demod, struct drx_version_list **version *version_list = &(ext_attr->v_list_elements[0]); - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: *version_list = (struct drx_version_list *) (NULL); - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } @@ -19066,11 +19066,11 @@ static int ctrl_probe_device(struct drx_demod_instance *demod) }while (0); } - return (ret_status); + return ret_status; rw_error: common_attr->current_power_mode = org_power_mode; - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } #ifdef DRXJ_SPLIT_UCODE_UPLOAD @@ -19087,9 +19087,9 @@ rw_error: bool is_mc_block_audio(u32 addr) { if ((addr == AUD_XFP_PRAM_4K__A) || (addr == AUD_XDFP_PRAM_4K__A)) { - return (true); + return true; } - return (false); + return false; } /*============================================================================*/ @@ -19185,7 +19185,7 @@ ctrl_u_codeUpload(struct drx_demod_instance *demod, mc_data, 0x0000) != DRX_STS_OK) { - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } }; break; @@ -19226,7 +19226,7 @@ ctrl_u_codeUpload(struct drx_demod_instance *demod, mc_dataBuffer, 0x0000) != DRX_STS_OK) { - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } result = @@ -19235,7 +19235,7 @@ ctrl_u_codeUpload(struct drx_demod_instance *demod, bytes_to_compare); if (result != 0) { - return (DRX_STS_ERROR); + return DRX_STS_ERROR; }; curr_addr += @@ -19266,7 +19266,7 @@ ctrl_u_codeUpload(struct drx_demod_instance *demod, ext_attr->flag_aud_mc_uploaded = false; } - return (DRX_STS_OK); + return DRX_STS_OK; } #endif /* DRXJ_SPLIT_UCODE_UPLOAD */ @@ -19295,7 +19295,7 @@ ctrl_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength) /* Check arguments */ if ((sig_strength == NULL) || (demod == NULL)) { - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -19333,14 +19333,14 @@ ctrl_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength) #endif case DRX_STANDARD_UNKNOWN: /* fallthrough */ default: - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } /* TODO */ /* find out if signal strength is calculated in the same way for all standards */ - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /*============================================================================*/ @@ -19365,7 +19365,7 @@ ctrl_get_cfg_oob_misc(struct drx_demod_instance *demod, struct drxj_cfg_oob_misc /* check arguments */ if (misc == NULL) { - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } dev_addr = demod->my_i2c_dev_addr; @@ -19412,9 +19412,9 @@ ctrl_get_cfg_oob_misc(struct drx_demod_instance *demod, struct drxj_cfg_oob_misc } misc->state = (state >> 8) & 0xff; - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } #endif @@ -19433,7 +19433,7 @@ ctrl_get_cfg_vsb_misc(struct drx_demod_instance *demod, struct drxj_cfg_vsb_misc /* check arguments */ if (misc == NULL) { - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } dev_addr = demod->my_i2c_dev_addr; @@ -19443,9 +19443,9 @@ ctrl_get_cfg_vsb_misc(struct drx_demod_instance *demod, struct drxj_cfg_vsb_misc goto rw_error; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /*============================================================================*/ @@ -19466,7 +19466,7 @@ ctrl_set_cfg_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_s { /* check arguments */ if (agc_settings == NULL) { - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } switch (agc_settings->ctrl_mode) { @@ -19475,7 +19475,7 @@ ctrl_set_cfg_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_s case DRX_AGC_CTRL_OFF: /* fallthrough */ break; default: - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } /* Distpatch */ @@ -19498,10 +19498,10 @@ ctrl_set_cfg_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_s return set_agc_if(demod, agc_settings, true); case DRX_STANDARD_UNKNOWN: default: - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } - return (DRX_STS_OK); + return DRX_STS_OK; } /*============================================================================*/ @@ -19522,7 +19522,7 @@ ctrl_get_cfg_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_s { /* check arguments */ if (agc_settings == NULL) { - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } /* Distpatch */ @@ -19545,10 +19545,10 @@ ctrl_get_cfg_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_s return get_agc_if(demod, agc_settings); case DRX_STANDARD_UNKNOWN: default: - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } - return (DRX_STS_OK); + return DRX_STS_OK; } /*============================================================================*/ @@ -19569,7 +19569,7 @@ ctrl_set_cfg_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_s { /* check arguments */ if (agc_settings == NULL) { - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } switch (agc_settings->ctrl_mode) { @@ -19578,7 +19578,7 @@ ctrl_set_cfg_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_s case DRX_AGC_CTRL_OFF: break; default: - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } /* Distpatch */ @@ -19601,10 +19601,10 @@ ctrl_set_cfg_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_s return set_agc_rf(demod, agc_settings, true); case DRX_STANDARD_UNKNOWN: default: - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } - return (DRX_STS_OK); + return DRX_STS_OK; } /*============================================================================*/ @@ -19625,7 +19625,7 @@ ctrl_get_cfg_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_s { /* check arguments */ if (agc_settings == NULL) { - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } /* Distpatch */ @@ -19648,10 +19648,10 @@ ctrl_get_cfg_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_s return get_agc_rf(demod, agc_settings); case DRX_STANDARD_UNKNOWN: default: - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } - return (DRX_STS_OK); + return DRX_STS_OK; } /*============================================================================*/ @@ -19681,7 +19681,7 @@ ctrl_get_cfg_agc_internal(struct drx_demod_instance *demod, u16 *agc_internal) /* check arguments */ if (agc_internal == NULL) { - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -19716,12 +19716,12 @@ ctrl_get_cfg_agc_internal(struct drx_demod_instance *demod, u16 *agc_internal) iqm_cf_gain = 56; break; default: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } break; #endif default: - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_CF_POW__A, &iqm_cf_power, 0); @@ -19749,9 +19749,9 @@ ctrl_get_cfg_agc_internal(struct drx_demod_instance *demod, u16 *agc_internal) - 2 * log1_times100(iqm_cf_amp) - iqm_cf_gain - 120 * iqm_cf_scale_sh + 781); - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /*============================================================================*/ @@ -19780,7 +19780,7 @@ ctrl_set_cfg_pre_saw(struct drx_demod_instance *demod, struct drxj_cfg_pre_saw * /* check arguments */ if ((pre_saw == NULL) || (pre_saw->reference > IQM_AF_PDREF__M) ) { - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } /* Only if standard is currently active */ @@ -19820,12 +19820,12 @@ ctrl_set_cfg_pre_saw(struct drx_demod_instance *demod, struct drxj_cfg_pre_saw * break; #endif default: - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /*============================================================================*/ @@ -19851,7 +19851,7 @@ ctrl_set_cfg_afe_gain(struct drx_demod_instance *demod, struct drxj_cfg_afe_gain /* check arguments */ if (afe_gain == NULL) { - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } dev_addr = demod->my_i2c_dev_addr; @@ -19867,7 +19867,7 @@ ctrl_set_cfg_afe_gain(struct drx_demod_instance *demod, struct drxj_cfg_afe_gain /* Do nothing */ break; default: - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } /* TODO PGA gain is also written by microcode (at least by QAM and VSB) @@ -19903,12 +19903,12 @@ ctrl_set_cfg_afe_gain(struct drx_demod_instance *demod, struct drxj_cfg_afe_gain break; #endif default: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /*============================================================================*/ @@ -19931,7 +19931,7 @@ ctrl_get_cfg_pre_saw(struct drx_demod_instance *demod, struct drxj_cfg_pre_saw * /* check arguments */ if (pre_saw == NULL) - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -19962,10 +19962,10 @@ ctrl_get_cfg_pre_saw(struct drx_demod_instance *demod, struct drxj_cfg_pre_saw * break; #endif default: - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } - return (DRX_STS_OK); + return DRX_STS_OK; } /*============================================================================*/ @@ -19988,7 +19988,7 @@ ctrl_get_cfg_afe_gain(struct drx_demod_instance *demod, struct drxj_cfg_afe_gain /* check arguments */ if (afe_gain == NULL) - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; ext_attr = demod->my_ext_attr; @@ -20004,10 +20004,10 @@ ctrl_get_cfg_afe_gain(struct drx_demod_instance *demod, struct drxj_cfg_afe_gain break; #endif default: - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } - return (DRX_STS_OK); + return DRX_STS_OK; } /*============================================================================*/ @@ -20029,7 +20029,7 @@ ctrl_get_fec_meas_seq_count(struct drx_demod_instance *demod, u16 *fec_meas_seq_ int rc; /* check arguments */ if (fec_meas_seq_count == NULL) { - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, fec_meas_seq_count, 0); @@ -20038,9 +20038,9 @@ ctrl_get_fec_meas_seq_count(struct drx_demod_instance *demod, u16 *fec_meas_seq_ goto rw_error; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /*============================================================================*/ @@ -20061,7 +20061,7 @@ ctrl_get_accum_cr_rs_cw_err(struct drx_demod_instance *demod, u32 *accum_cr_rs_c { int rc; if (accum_cr_rs_cw_err == NULL) { - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } rc = DRXJ_DAP.read_reg32func(demod->my_i2c_dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, accum_cr_rs_cw_err, 0); @@ -20070,9 +20070,9 @@ ctrl_get_accum_cr_rs_cw_err(struct drx_demod_instance *demod, u32 *accum_cr_rs_c goto rw_error; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /** @@ -20088,7 +20088,7 @@ static int ctrl_set_cfg(struct drx_demod_instance *demod, struct drx_cfg *config int rc; if (config == NULL) - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; do { u16 dummy; @@ -20181,12 +20181,12 @@ static int ctrl_set_cfg(struct drx_demod_instance *demod, struct drx_cfg *config #endif default: - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /*============================================================================*/ @@ -20204,7 +20204,7 @@ static int ctrl_get_cfg(struct drx_demod_instance *demod, struct drx_cfg *config int rc; if (config == NULL) - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; do { u16 dummy; @@ -20320,12 +20320,12 @@ static int ctrl_get_cfg(struct drx_demod_instance *demod, struct drx_cfg *config #endif default: - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; } - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /*============================================================================= @@ -20352,7 +20352,7 @@ int drxj_open(struct drx_demod_instance *demod) /* Check arguments */ if (demod->my_ext_attr == NULL) - return (DRX_STS_INVALID_ARG); + return DRX_STS_INVALID_ARG; dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -20630,10 +20630,10 @@ int drxj_open(struct drx_demod_instance *demod) /* refresh the audio data structure with default */ ext_attr->aud_data = drxj_default_aud_data_g; - return (DRX_STS_OK); + return DRX_STS_OK; rw_error: common_attr->is_opened = false; - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /*============================================================================*/ @@ -20696,7 +20696,7 @@ int drxj_close(struct drx_demod_instance *demod) return DRX_STS_OK; rw_error: - return (DRX_STS_ERROR); + return DRX_STS_ERROR; } /*============================================================================*/ @@ -20712,13 +20712,13 @@ drxj_ctrl(struct drx_demod_instance *demod, u32 ctrl, void *ctrl_data) /*======================================================================*/ case DRX_CTRL_SET_CHANNEL: { - return ctrl_set_channel(demod, (struct drx_channel *) ctrl_data); + return ctrl_set_channel(demod, (struct drx_channel *)ctrl_data); } break; /*======================================================================*/ case DRX_CTRL_GET_CHANNEL: { - return ctrl_get_channel(demod, (struct drx_channel *) ctrl_data); + return ctrl_get_channel(demod, (struct drx_channel *)ctrl_data); } break; /*======================================================================*/ @@ -20737,19 +20737,19 @@ drxj_ctrl(struct drx_demod_instance *demod, u32 ctrl, void *ctrl_data) /*======================================================================*/ case DRX_CTRL_CONSTEL: { - return ctrl_constel(demod, (struct drx_complex *) ctrl_data); + return ctrl_constel(demod, (struct drx_complex *)ctrl_data); } break; /*======================================================================*/ case DRX_CTRL_SET_CFG: { - return ctrl_set_cfg(demod, (struct drx_cfg *) ctrl_data); + return ctrl_set_cfg(demod, (struct drx_cfg *)ctrl_data); } break; /*======================================================================*/ case DRX_CTRL_GET_CFG: { - return ctrl_get_cfg(demod, (struct drx_cfg *) ctrl_data); + return ctrl_get_cfg(demod, (struct drx_cfg *)ctrl_data); } break; /*======================================================================*/ @@ -20782,7 +20782,7 @@ drxj_ctrl(struct drx_demod_instance *demod, u32 ctrl, void *ctrl_data) /*======================================================================*/ case DRX_CTRL_POWER_MODE: { - return ctrl_power_mode(demod, (enum drx_power_mode *) ctrl_data); + return ctrl_power_mode(demod, (enum drx_power_mode *)ctrl_data); } break; /*======================================================================*/ @@ -20801,37 +20801,37 @@ drxj_ctrl(struct drx_demod_instance *demod, u32 ctrl, void *ctrl_data) /*======================================================================*/ case DRX_CTRL_SET_OOB: { - return ctrl_set_oob(demod, (struct drxoob *) ctrl_data); + return ctrl_set_oob(demod, (struct drxoob *)ctrl_data); } break; /*======================================================================*/ case DRX_CTRL_GET_OOB: { - return ctrl_get_oob(demod, (struct drxoob_status *) ctrl_data); + return ctrl_get_oob(demod, (struct drxoob_status *)ctrl_data); } break; /*======================================================================*/ case DRX_CTRL_SET_UIO_CFG: { - return ctrl_set_uio_cfg(demod, (struct drxuio_cfg *) ctrl_data); + return ctrl_set_uio_cfg(demod, (struct drxuio_cfg *)ctrl_data); } break; /*======================================================================*/ case DRX_CTRL_GET_UIO_CFG: { - return CtrlGetuio_cfg(demod, (struct drxuio_cfg *) ctrl_data); + return CtrlGetuio_cfg(demod, (struct drxuio_cfg *)ctrl_data); } break; /*======================================================================*/ case DRX_CTRL_UIO_READ: { - return ctrl_uio_read(demod, (struct drxuio_data *) ctrl_data); + return ctrl_uio_read(demod, (struct drxuio_data *)ctrl_data); } break; /*======================================================================*/ case DRX_CTRL_UIO_WRITE: { - return ctrl_uio_write(demod, (struct drxuio_data *) ctrl_data); + return ctrl_uio_write(demod, (struct drxuio_data *)ctrl_data); } break; /*======================================================================*/ @@ -20858,7 +20858,7 @@ drxj_ctrl(struct drx_demod_instance *demod, u32 ctrl, void *ctrl_data) /*======================================================================*/ case DRX_CTRL_AUD_BEEP: { - return aud_ctrl_beep(demod, (struct drx_aud_beep *) ctrl_data); + return aud_ctrl_beep(demod, (struct drx_aud_beep *)ctrl_data); } break; @@ -20891,7 +20891,7 @@ drxj_ctrl(struct drx_demod_instance *demod, u32 ctrl, void *ctrl_data) } break; default: - return (DRX_STS_FUNC_NOT_AVAILABLE); + return DRX_STS_FUNC_NOT_AVAILABLE; } - return (DRX_STS_OK); + return DRX_STS_OK; } -- cgit v1.1 From 259f380e6828c1dd324d43b16c0c95d34f33b4aa Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Fri, 17 Jan 2014 06:40:47 -0300 Subject: [media] drx-j: Simplify logic expressions Don't need to test boolean x == true or x == false. That makes the code more compact. patch generated with make coccicheck and manually reviewed. While here, remove uneeded ';'. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drx_driver.c | 22 ++--- drivers/media/dvb-frontends/drx39xyj/drxj.c | 106 +++++++++++----------- 2 files changed, 64 insertions(+), 64 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c index 2c88e47..5974b7c 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c @@ -227,7 +227,7 @@ static int scan_wait_for_lock(struct drx_demod_instance *demod, bool *is_locked) start_time_lock_stage = drxbsp_hst_clock(); /* Start polling loop, checking for lock & timeout */ - while (done_waiting == false) { + while (!done_waiting) { if (drx_ctrl(demod, DRX_CTRL_LOCK_STATUS, &lock_state) != DRX_STS_OK) { @@ -326,7 +326,7 @@ scan_prepare_next_scan(struct drx_demod_instance *demod, s32 skip) common_attr->scan_ready = true; } } while ((next_frequency < tuner_min_frequency) && - (common_attr->scan_ready == false)); + (!common_attr->scan_ready)); /* Store new values */ common_attr->scan_freq_plan_index = table_index; @@ -384,7 +384,7 @@ scan_function_default(void *scan_context, /* done with this channel, move to next one */ *get_next_channel = true; - if (is_locked == false) { + if (!is_locked) { /* no channel found */ return DRX_STS_BUSY; } @@ -634,7 +634,7 @@ static int ctrl_scan_next(struct drx_demod_instance *demod, u16 *scan_progress) num_tries = common_attr->scan_param->num_tries; scan_ready = &(common_attr->scan_ready); - for (i = 0; ((i < num_tries) && ((*scan_ready) == false)); i++) { + for (i = 0; ((i < num_tries) && (!(*scan_ready))); i++) { struct drx_channel scan_channel = { 0 }; int status = DRX_STS_ERROR; struct drx_frequency_plan *freq_plan = (struct drx_frequency_plan *) (NULL); @@ -670,7 +670,7 @@ static int ctrl_scan_next(struct drx_demod_instance *demod, u16 *scan_progress) &next_channel); /* Proceed to next channel if requested */ - if (next_channel == true) { + if (next_channel) { int next_status = DRX_STS_ERROR; s32 skip = 0; @@ -698,7 +698,7 @@ static int ctrl_scan_next(struct drx_demod_instance *demod, u16 *scan_progress) } } /* for ( i = 0; i < ( ... num_tries); i++) */ - if ((*scan_ready) == true) { + if ((*scan_ready)) { /* End of scan reached: call stop-scan, ignore any error */ ctrl_scan_stop(demod); common_attr->scan_active = false; @@ -1112,7 +1112,7 @@ ctrl_u_code(struct drx_demod_instance *demod, DRX_STS_OK) { return DRX_STS_ERROR; } /* if */ - }; + } break; /*================================================================*/ @@ -1171,7 +1171,7 @@ ctrl_u_code(struct drx_demod_instance *demod, bytes_left_to_compare -= ((u32) bytes_to_compare); } /* while( bytes_to_compare > DRX_UCODE_MAX_BUF_SIZE ) */ - }; + } break; /*================================================================*/ @@ -1314,7 +1314,7 @@ int drx_open(struct drx_demod_instance *demod) (demod->my_common_attr == NULL) || (demod->my_ext_attr == NULL) || (demod->my_i2c_dev_addr == NULL) || - (demod->my_common_attr->is_opened == true)) { + (demod->my_common_attr->is_opened)) { return DRX_STS_INVALID_ARG; } @@ -1351,7 +1351,7 @@ int drx_close(struct drx_demod_instance *demod) (demod->my_common_attr == NULL) || (demod->my_ext_attr == NULL) || (demod->my_i2c_dev_addr == NULL) || - (demod->my_common_attr->is_opened == false)) { + (!demod->my_common_attr->is_opened)) { return DRX_STS_INVALID_ARG; } @@ -1395,7 +1395,7 @@ drx_ctrl(struct drx_demod_instance *demod, u32 ctrl, void *ctrl_data) return DRX_STS_INVALID_ARG; } - if (((demod->my_common_attr->is_opened == false) && + if (((!demod->my_common_attr->is_opened) && (ctrl != DRX_CTRL_PROBE_DEVICE) && (ctrl != DRX_CTRL_VERSION)) ) { return DRX_STS_INVALID_ARG; diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index 4e20595..6e7ce75 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -1819,14 +1819,14 @@ static int drxj_dap_read_aud_reg16(struct i2c_device_addr *dev_addr, if (stat != DRX_STS_OK) { break; - }; + } current_timer = drxbsp_hst_clock(); delta_timer = current_timer - start_timer; if (delta_timer > DRXJ_DAP_AUDTRIF_TIMEOUT) { stat = DRX_STS_ERROR; break; - }; + } } while (((tr_status & AUD_TOP_TR_CTR_FIFO_LOCK__M) == AUD_TOP_TR_CTR_FIFO_LOCK_LOCKED) || @@ -1845,14 +1845,14 @@ static int drxj_dap_read_aud_reg16(struct i2c_device_addr *dev_addr, &tr_status, 0x0000); if (stat != DRX_STS_OK) { break; - }; + } current_timer = drxbsp_hst_clock(); delta_timer = current_timer - start_timer; if (delta_timer > DRXJ_DAP_AUDTRIF_TIMEOUT) { stat = DRX_STS_ERROR; break; - }; + } } /* while ( ... ) */ } @@ -1961,14 +1961,14 @@ static int drxj_dap_write_aud_reg16(struct i2c_device_addr *dev_addr, data, &tr_status); if (stat != DRX_STS_OK) { break; - }; + } current_timer = drxbsp_hst_clock(); delta_timer = current_timer - start_timer; if (delta_timer > DRXJ_DAP_AUDTRIF_TIMEOUT) { stat = DRX_STS_ERROR; break; - }; + } } while (((tr_status & AUD_TOP_TR_CTR_FIFO_LOCK__M) == AUD_TOP_TR_CTR_FIFO_LOCK_LOCKED) || @@ -2062,7 +2062,7 @@ int drxj_dap_atomic_read_write_block(struct i2c_device_addr *dev_addr, hi_cmd.param2 = (u16) DRXDAP_FASI_ADDR2OFFSET(DRXJ_HI_ATOMIC_BUF_START); hi_cmd.param3 = (u16) ((datasize / 2) - 1); - if (read_flag == false) { + if (!read_flag) { hi_cmd.param3 |= DRXJ_HI_ATOMIC_WRITE; } else { hi_cmd.param3 |= DRXJ_HI_ATOMIC_READ; @@ -2071,7 +2071,7 @@ int drxj_dap_atomic_read_write_block(struct i2c_device_addr *dev_addr, DRXDAP_FASI_ADDR2BANK(addr)); hi_cmd.param5 = (u16) DRXDAP_FASI_ADDR2OFFSET(addr); - if (read_flag == false) { + if (!read_flag) { /* write data to buffer */ for (i = 0; i < (datasize / 2); i++) { @@ -2089,7 +2089,7 @@ int drxj_dap_atomic_read_write_block(struct i2c_device_addr *dev_addr, goto rw_error; } - if (read_flag == true) { + if (read_flag) { /* read data from buffer */ for (i = 0; i < (datasize / 2); i++) { drxj_dap_read_reg16(dev_addr, @@ -2283,13 +2283,13 @@ hi_command(struct i2c_device_addr *dev_addr, const pdrxj_hi_cmd_t cmd, u16 *resu (((cmd-> param5) & SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) == SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ)); - if (powerdown_cmd == false) { + if (!powerdown_cmd) { /* Wait until command rdy */ do { nr_retries++; if (nr_retries > DRXJ_MAX_RETRIES) { goto rw_error; - }; + } rc = DRXJ_DAP.read_reg16func(dev_addr, SIO_HI_RA_RAM_CMD__A, &wait_cmd, 0); if (rc != DRX_STS_OK) { @@ -3436,7 +3436,7 @@ static int set_mpegtei_handling(struct drx_demod_instance *demod) FEC_OC_SNC_MODE_CORR_DISABLE__M)); fec_oc_ems_mode &= (~FEC_OC_EMS_MODE_MODE__M); - if (ext_attr->disable_te_ihandling == true) { + if (ext_attr->disable_te_ihandling) { /* do not change TEI bit */ fec_oc_dpr_mode |= FEC_OC_DPR_MODE_ERR_DISABLE__M; fec_oc_snc_mode |= FEC_OC_SNC_MODE_CORR_DISABLE__M | @@ -3494,7 +3494,7 @@ static int bit_reverse_mpeg_output(struct drx_demod_instance *demod) /* reset to default (normal bit order) */ fec_oc_ipr_mode &= (~FEC_OC_IPR_MODE_REVERSE_ORDER__M); - if (ext_attr->bit_reverse_mpeg_outout == true) { + if (ext_attr->bit_reverse_mpeg_outout) { /* reverse bit order */ fec_oc_ipr_mode |= FEC_OC_IPR_MODE_REVERSE_ORDER__M; } @@ -3780,7 +3780,7 @@ static int ctrl_set_uio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg /*====================================================================*/ case DRX_UIO1: /* DRX_UIO1: SMA_TX UIO-1 */ - if (ext_attr->has_smatx != true) + if (!ext_attr->has_smatx) return DRX_STS_ERROR; switch (uio_cfg->mode) { case DRX_UIO_MODE_FIRMWARE_SMA: /* falltrough */ @@ -3804,7 +3804,7 @@ static int ctrl_set_uio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg /*====================================================================*/ case DRX_UIO2: /* DRX_UIO2: SMA_RX UIO-2 */ - if (ext_attr->has_smarx != true) + if (!ext_attr->has_smarx) return DRX_STS_ERROR; switch (uio_cfg->mode) { case DRX_UIO_MODE_FIRMWARE0: /* falltrough */ @@ -3828,7 +3828,7 @@ static int ctrl_set_uio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg /*====================================================================*/ case DRX_UIO3: /* DRX_UIO3: GPIO UIO-3 */ - if (ext_attr->has_gpio != true) + if (!ext_attr->has_gpio) return DRX_STS_ERROR; switch (uio_cfg->mode) { case DRX_UIO_MODE_FIRMWARE0: /* falltrough */ @@ -3852,7 +3852,7 @@ static int ctrl_set_uio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg /*====================================================================*/ case DRX_UIO4: /* DRX_UIO4: IRQN UIO-4 */ - if (ext_attr->has_irqn != true) + if (!ext_attr->has_irqn) return DRX_STS_ERROR; switch (uio_cfg->mode) { case DRX_UIO_MODE_READWRITE: @@ -3925,7 +3925,7 @@ static int CtrlGetuio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg *u return DRX_STS_INVALID_ARG; } - if (*uio_available[uio_cfg->uio] == false) { + if (!*uio_available[uio_cfg->uio]) { return DRX_STS_ERROR; } @@ -3965,7 +3965,7 @@ ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data) /*====================================================================*/ case DRX_UIO1: /* DRX_UIO1: SMA_TX UIO-1 */ - if (ext_attr->has_smatx != true) + if (!ext_attr->has_smatx) return DRX_STS_ERROR; if ((ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_READWRITE) && (ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_FIRMWARE_SAW)) { @@ -4005,7 +4005,7 @@ ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data) /*======================================================================*/ case DRX_UIO2: /* DRX_UIO2: SMA_RX UIO-2 */ - if (ext_attr->has_smarx != true) + if (!ext_attr->has_smarx) return DRX_STS_ERROR; if (ext_attr->uio_sma_rx_mode != DRX_UIO_MODE_READWRITE) { return DRX_STS_ERROR; @@ -4044,7 +4044,7 @@ ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data) /*====================================================================*/ case DRX_UIO3: /* DRX_UIO3: ASEL UIO-3 */ - if (ext_attr->has_gpio != true) + if (!ext_attr->has_gpio) return DRX_STS_ERROR; if (ext_attr->uio_gpio_mode != DRX_UIO_MODE_READWRITE) { return DRX_STS_ERROR; @@ -4083,7 +4083,7 @@ ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data) /*=====================================================================*/ case DRX_UIO4: /* DRX_UIO4: IRQN UIO-4 */ - if (ext_attr->has_irqn != true) + if (!ext_attr->has_irqn) return DRX_STS_ERROR; if (ext_attr->uio_irqn_mode != DRX_UIO_MODE_READWRITE) { @@ -4167,7 +4167,7 @@ static int ctrl_uio_read(struct drx_demod_instance *demod, struct drxuio_data *u /*====================================================================*/ case DRX_UIO1: /* DRX_UIO1: SMA_TX UIO-1 */ - if (ext_attr->has_smatx != true) + if (!ext_attr->has_smatx) return DRX_STS_ERROR; if (ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_READWRITE) { @@ -4200,7 +4200,7 @@ static int ctrl_uio_read(struct drx_demod_instance *demod, struct drxuio_data *u /*======================================================================*/ case DRX_UIO2: /* DRX_UIO2: SMA_RX UIO-2 */ - if (ext_attr->has_smarx != true) + if (!ext_attr->has_smarx) return DRX_STS_ERROR; if (ext_attr->uio_sma_rx_mode != DRX_UIO_MODE_READWRITE) { @@ -4234,7 +4234,7 @@ static int ctrl_uio_read(struct drx_demod_instance *demod, struct drxuio_data *u /*=====================================================================*/ case DRX_UIO3: /* DRX_UIO3: GPIO UIO-3 */ - if (ext_attr->has_gpio != true) + if (!ext_attr->has_gpio) return DRX_STS_ERROR; if (ext_attr->uio_gpio_mode != DRX_UIO_MODE_READWRITE) { @@ -4268,7 +4268,7 @@ static int ctrl_uio_read(struct drx_demod_instance *demod, struct drxuio_data *u /*=====================================================================*/ case DRX_UIO4: /* DRX_UIO4: IRQN UIO-4 */ - if (ext_attr->has_irqn != true) + if (!ext_attr->has_irqn) return DRX_STS_ERROR; if (ext_attr->uio_irqn_mode != DRX_UIO_MODE_READWRITE) { @@ -4344,7 +4344,7 @@ ctrl_i2c_bridge(struct drx_demod_instance *demod, bool *bridge_closed) hi_cmd.cmd = SIO_HI_RA_RAM_CMD_BRDCTRL; hi_cmd.param1 = SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY; - if (*bridge_closed == true) { + if (*bridge_closed) { hi_cmd.param2 = SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED; } else { hi_cmd.param2 = SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN; @@ -4749,7 +4749,7 @@ int drxj_dap_scu_atomic_read_write_block(struct i2c_device_addr *dev_addr, u32 a goto rw_error; } - if (read_flag == true) { + if (read_flag) { int i = 0; /* read data from buffer */ for (i = 0; i < (datasize / 2); i++) { @@ -5023,7 +5023,7 @@ ctrl_set_cfg_pdr_safe_mode(struct drx_demod_instance *demod, bool *enable) goto rw_error; } - if (*enable == true) { + if (*enable) { bool bridge_enabled = false; /* MPEG pins to input */ @@ -5824,7 +5824,7 @@ set_frequency(struct drx_demod_instance *demod, } intermediate_freq = demod->my_common_attr->intermediate_freq; sampling_frequency = demod->my_common_attr->sys_clock_freq / 3; - if (tuner_mirror == true) { + if (tuner_mirror) { /* tuner doesn't mirror */ if_freq_actual = intermediate_freq + rf_freq_residual + fm_frequency_shift; @@ -5971,7 +5971,7 @@ static int get_acc_pkt_err(struct drx_demod_instance *demod, u16 *packet_err) pr_err("error %d\n", rc); goto rw_error; } - if (ext_attr->reset_pkt_err_acc == true) { + if (ext_attr->reset_pkt_err_acc) { last_pkt_err = data; pkt_err = 0; ext_attr->reset_pkt_err_acc = false; @@ -6093,7 +6093,7 @@ static int get_ctl_freq_offset(struct drx_demod_instance *demod, s32 *ctl_freq) goto rw_error; } - if (ext_attr->pos_image == true) { + if (ext_attr->pos_image) { /* negative image */ carrier_frequency_shift = nominal_frequency - current_frequency; } else { @@ -6825,7 +6825,7 @@ static int power_down_vsb(struct drx_demod_instance *demod, bool primary) pr_err("error %d\n", rc); goto rw_error; } - if (primary == true) { + if (primary) { rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0); if (rc != DRX_STS_OK) { pr_err("error %d\n", rc); @@ -7425,13 +7425,13 @@ static int set_vsb(struct drx_demod_instance *demod) goto rw_error; } /* B-Input to ADC, PGA+filter in standby */ - if (ext_attr->has_lna == false) { + if (!ext_attr->has_lna) { rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_AMUX__A, 0x02, 0); if (rc != DRX_STS_OK) { pr_err("error %d\n", rc); goto rw_error; } - }; + } /* turn on IQMAF. It has to be in front of setAgc**() */ rc = set_iqm_af(demod, true); @@ -7915,7 +7915,7 @@ static int power_down_qam(struct drx_demod_instance *demod, bool primary) goto rw_error; } - if (primary == true) { + if (primary) { rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0); if (rc != DRX_STS_OK) { pr_err("error %d\n", rc); @@ -9694,7 +9694,7 @@ set_qam(struct drx_demod_instance *demod, } if (op & QAM_SET_OP_ALL) { - if (ext_attr->has_lna == false) { + if (!ext_attr->has_lna) { rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_AMUX__A, 0x02, 0); if (rc != DRX_STS_OK) { pr_err("error %d\n", rc); @@ -11965,7 +11965,7 @@ power_down_atv(struct drx_demod_instance *demod, enum drx_standard standard, boo pr_err("error %d\n", rc); goto rw_error; } - if (primary == true) { + if (primary) { rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0); if (rc != DRX_STS_OK) { pr_err("error %d\n", rc); @@ -12885,7 +12885,7 @@ trouble ? } /* Common initializations FM & NTSC & B/G & D/K & I & L & LP */ - if (ext_attr->has_lna == false) { + if (!ext_attr->has_lna) { rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_AMUX__A, 0x01, 0); if (rc != DRX_STS_OK) { pr_err("error %d\n", rc); @@ -13521,7 +13521,7 @@ static int power_up_aud(struct drx_demod_instance *demod, bool set_standard) goto rw_error; } - if (set_standard == true) { + if (set_standard) { rc = aud_ctrl_set_standard(demod, &aud_standard); if (rc != DRX_STS_OK) { pr_err("error %d\n", rc); @@ -16797,12 +16797,12 @@ static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_par /* signal is transmitted inverted */ ((oob_param->spectrum_inverted == true) & /* and tuner is not mirroring the signal */ - (mirror_freq_spectOOB == false)) | + (!mirror_freq_spectOOB)) | /* or */ /* signal is transmitted noninverted */ ((oob_param->spectrum_inverted == false) & /* and tuner is mirroring the signal */ - (mirror_freq_spectOOB == true)) + (mirror_freq_spectOOB)) ) set_param_parameters[0] = SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC; @@ -16815,12 +16815,12 @@ static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_par /* signal is transmitted inverted */ ((oob_param->spectrum_inverted == true) & /* and tuner is not mirroring the signal */ - (mirror_freq_spectOOB == false)) | + (!mirror_freq_spectOOB)) | /* or */ /* signal is transmitted noninverted */ ((oob_param->spectrum_inverted == false) & /* and tuner is mirroring the signal */ - (mirror_freq_spectOOB == true)) + (mirror_freq_spectOOB)) ) set_param_parameters[0] = SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_INVSPEC; @@ -16834,12 +16834,12 @@ static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_par /* signal is transmitted inverted */ ((oob_param->spectrum_inverted == true) & /* and tuner is not mirroring the signal */ - (mirror_freq_spectOOB == false)) | + (!mirror_freq_spectOOB)) | /* or */ /* signal is transmitted noninverted */ ((oob_param->spectrum_inverted == false) & /* and tuner is mirroring the signal */ - (mirror_freq_spectOOB == true)) + (mirror_freq_spectOOB)) ) set_param_parameters[0] = SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_INVSPEC; @@ -17199,7 +17199,7 @@ ctrl_get_oob(struct drx_demod_instance *demod, struct drxoob_status *oob_status) return DRX_STS_INVALID_ARG; } - if (ext_attr->oob_power_on == false) + if (!ext_attr->oob_power_on) return DRX_STS_ERROR; rc = DRXJ_DAP.read_reg16func(dev_addr, ORX_DDC_OFO_SET_W__A, &data, 0); @@ -17872,7 +17872,7 @@ ctrl_get_channel(struct drx_demod_instance *demod, struct drx_channel *channel) goto rw_error; } tuner_freq_offset = channel->frequency - ext_attr->frequency; - if (tuner_mirror == true) { + if (tuner_mirror) { /* positive image */ channel->frequency += tuner_freq_offset; } else { @@ -19187,7 +19187,7 @@ ctrl_u_codeUpload(struct drx_demod_instance *demod, DRX_STS_OK) { return DRX_STS_ERROR; } - }; + } break; /*===================================================================*/ @@ -19236,7 +19236,7 @@ ctrl_u_codeUpload(struct drx_demod_instance *demod, if (result != 0) { return DRX_STS_ERROR; - }; + } curr_addr += ((dr_xaddr_t) @@ -19246,7 +19246,7 @@ ctrl_u_codeUpload(struct drx_demod_instance *demod, bytes_left_to_compare -= ((u32) bytes_to_compare); } /* while( bytes_to_compare > DRXJ_UCODE_MAX_BUF_SIZE ) */ - }; + } break; /*===================================================================*/ @@ -19262,7 +19262,7 @@ ctrl_u_codeUpload(struct drx_demod_instance *demod, mc_data += mc_block_nr_bytes; } /* for( i = 0 ; iflag_aud_mc_uploaded = false; } @@ -20680,7 +20680,7 @@ int drxj_close(struct drx_demod_instance *demod) goto rw_error; } } - }; + } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0); if (rc != DRX_STS_OK) { -- cgit v1.1 From e33f2193ade658a509d01178a95c32b9242b7d61 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Fri, 17 Jan 2014 06:47:04 -0300 Subject: [media] drx-j: More CamelCase fixups Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- .../media/dvb-frontends/drx39xyj/drx_dap_fasi.c | 6 +- drivers/media/dvb-frontends/drx39xyj/drx_driver.c | 26 ++--- drivers/media/dvb-frontends/drx39xyj/drx_driver.h | 8 +- drivers/media/dvb-frontends/drx39xyj/drxj.c | 126 ++++++++++----------- drivers/media/dvb-frontends/drx39xyj/drxj.h | 4 +- 5 files changed, 85 insertions(+), 85 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c index 3f33b13..6053878 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c @@ -514,13 +514,13 @@ static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr, */ todo = (block_size < datasize ? block_size : datasize); if (todo == 0) { - u16 overhead_sizeI2cAddr = 0; + u16 overhead_size_i2c_addr = 0; u16 data_block_size = 0; - overhead_sizeI2cAddr = + overhead_size_i2c_addr = (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1); data_block_size = - (DRXDAP_MAX_WCHUNKSIZE - overhead_sizeI2cAddr) & ~1; + (DRXDAP_MAX_WCHUNKSIZE - overhead_size_i2c_addr) & ~1; /* write device address */ st = drxbsp_i2c_write_read(dev_addr, diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c index 5974b7c..d1d9ded 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c @@ -294,7 +294,7 @@ scan_prepare_next_scan(struct drx_demod_instance *demod, s32 skip) /* Search next frequency to scan */ /* always take at least one step */ - (common_attr->scan_channelsScanned)++; + (common_attr->scan_channels_scanned)++; next_frequency += frequency_plan[table_index].step; skip -= frequency_plan[table_index].step; @@ -302,7 +302,7 @@ scan_prepare_next_scan(struct drx_demod_instance *demod, s32 skip) without exceeding end of the band */ while ((skip > 0) && (next_frequency <= frequency_plan[table_index].last)) { - (common_attr->scan_channelsScanned)++; + (common_attr->scan_channels_scanned)++; next_frequency += frequency_plan[table_index].step; skip -= frequency_plan[table_index].step; } @@ -528,7 +528,7 @@ ctrl_scan_init(struct drx_demod_instance *demod, struct drx_scan_param *scan_par /* Store parameters */ common_attr->scan_ready = false; common_attr->scan_max_channels = nr_channels_in_plan; - common_attr->scan_channelsScanned = 0; + common_attr->scan_channels_scanned = 0; common_attr->scan_param = scan_param; /* SCAN_NEXT is now allowed */ scan_context = get_scan_context(demod, scan_context); @@ -626,7 +626,7 @@ static int ctrl_scan_next(struct drx_demod_instance *demod, u16 *scan_progress) return DRX_STS_ERROR; } - *scan_progress = (u16) (((common_attr->scan_channelsScanned) * + *scan_progress = (u16) (((common_attr->scan_channels_scanned) * ((u32) (max_progress))) / (common_attr->scan_max_channels)); @@ -682,7 +682,7 @@ static int ctrl_scan_next(struct drx_demod_instance *demod, u16 *scan_progress) /* keep track of progress */ *scan_progress = - (u16) (((common_attr->scan_channelsScanned) * + (u16) (((common_attr->scan_channels_scanned) * ((u32) (max_progress))) / (common_attr->scan_max_channels)); @@ -1119,7 +1119,7 @@ ctrl_u_code(struct drx_demod_instance *demod, case UCODE_VERIFY: { int result = 0; - u8 mc_dataBuffer + u8 mc_data_buffer [DRX_UCODE_MAX_BUF_SIZE]; u32 bytes_to_compare = 0; u32 bytes_left_to_compare = 0; @@ -1148,7 +1148,7 @@ ctrl_u_code(struct drx_demod_instance *demod, (u16) bytes_to_compare, (u8 *) - mc_dataBuffer, + mc_data_buffer, 0x0000) != DRX_STS_OK) { return DRX_STS_ERROR; @@ -1156,7 +1156,7 @@ ctrl_u_code(struct drx_demod_instance *demod, result = drxbsp_hst_memcmp(curr_ptr, - mc_dataBuffer, + mc_data_buffer, bytes_to_compare); if (result != 0) { @@ -1209,7 +1209,7 @@ ctrl_version(struct drx_demod_instance *demod, struct drx_version_list **version DRX_VERSIONSTRING(VERSION_MAJOR, VERSION_MINOR, VERSION_PATCH); static struct drx_version drx_driver_core_version; - static struct drx_version_list drx_driver_core_versionList; + static struct drx_version_list drx_driver_core_version_list; struct drx_version_list *demod_version_list = (struct drx_version_list *) (NULL); int return_status = DRX_STS_ERROR; @@ -1233,8 +1233,8 @@ ctrl_version(struct drx_demod_instance *demod, struct drx_version_list **version drx_driver_core_version.v_patch = VERSION_PATCH; drx_driver_core_version.v_string = drx_driver_core_version_text; - drx_driver_core_versionList.version = &drx_driver_core_version; - drx_driver_core_versionList.next = (struct drx_version_list *) (NULL); + drx_driver_core_version_list.version = &drx_driver_core_version; + drx_driver_core_version_list.next = (struct drx_version_list *) (NULL); if ((return_status == DRX_STS_OK) && (demod_version_list != NULL)) { /* Append versioninfo from driver to versioninfo from demod */ @@ -1244,12 +1244,12 @@ ctrl_version(struct drx_demod_instance *demod, struct drx_version_list **version while (current_list_element->next != NULL) { current_list_element = current_list_element->next; } - current_list_element->next = &drx_driver_core_versionList; + current_list_element->next = &drx_driver_core_version_list; *version_list = demod_version_list; } else { /* Just return versioninfo from driver */ - *version_list = &drx_driver_core_versionList; + *version_list = &drx_driver_core_version_list; } return DRX_STS_OK; diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h index e0316f6..975b3ba 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h @@ -182,7 +182,7 @@ struct tuner_common { s32 max_freq_rf; /* Highest RF input frequency, in kHz */ u8 sub_mode; /* Index to sub-mode in use */ - char ***sub_modeDescriptions; /* Pointer to description of sub-modes */ + char ***sub_mode_descriptions; /* Pointer to description of sub-modes */ u8 sub_modes; /* Number of available sub-modes */ /* The following fields will be either 0, NULL or false and do not need @@ -192,7 +192,7 @@ struct tuner_common { s32 r_ffrequency; /* only valid if programmed */ s32 i_ffrequency; /* only valid if programmed */ - void *myUser_data; /* pointer to associated demod instance */ + void *my_user_data; /* pointer to associated demod instance */ u16 my_capabilities; /* value for storing application flags */ }; @@ -230,7 +230,7 @@ struct tuner_ops { tuner_close_func_t close_func; tuner_set_frequency_func_t set_frequency_func; tuner_get_frequency_func_t get_frequency_func; - tuner_lock_status_func_t lock_statusFunc; + tuner_lock_status_func_t lock_status_func; tune_ri2c_write_read_func_t i2c_write_read_func; }; @@ -1985,7 +1985,7 @@ struct drx_reg_dump { /**< next freq to scan */ bool scan_ready; /**< scan ready flag */ u32 scan_max_channels;/**< number of channels in freqplan */ - u32 scan_channelsScanned; + u32 scan_channels_scanned; /**< number of channels scanned */ /* Channel scan - inner loop: demod related */ drx_scan_func_t scan_function; diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index 6e7ce75..f6361b6 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -661,7 +661,7 @@ struct drxj_data drxj_data_g = { 1, /* fec_rs_prescale */ FEC_RS_MEASUREMENT_PERIOD, /* fec_rs_period */ true, /* reset_pkt_err_acc */ - 0, /* pkt_errAccStart */ + 0, /* pkt_err_acc_start */ /* HI configuration */ 0, /* hi_cfg_timing_div */ @@ -1114,7 +1114,7 @@ ctrl_set_cfg_afe_gain(struct drx_demod_instance *demod, struct drxj_cfg_afe_gain #ifdef DRXJ_SPLIT_UCODE_UPLOAD static int -ctrl_u_codeUpload(struct drx_demod_instance *demod, +ctrl_u_code_upload(struct drx_demod_instance *demod, struct drxu_code_info *mc_info, enum drxu_code_actionaction, bool audio_mc_upload); #endif /* DRXJ_SPLIT_UCODE_UPLOAD */ @@ -3892,13 +3892,13 @@ rw_error: /*============================================================================*/ /** -* \fn int CtrlGetuio_cfg() +* \fn int ctrl_getuio_cfg() * \brief Get modus oprandi UIO. * \param demod Pointer to demodulator instance. * \param uio_cfg Pointer to a configuration setting for a certain UIO. * \return int. */ -static int CtrlGetuio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg *uio_cfg) +static int ctrl_getuio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg *uio_cfg) { struct drxj_data *ext_attr = (struct drxj_data *) NULL; @@ -5345,7 +5345,7 @@ static int init_agc(struct drx_demod_instance *demod) u16 ki_max = 0; u16 if_iaccu_hi_tgt_min = 0; u16 data = 0; - u16 agc_kiDgain = 0; + u16 agc_ki_dgain = 0; u16 ki_min = 0; u16 clp_ctrl_mode = 0; u16 agc_rf = 0; @@ -5363,7 +5363,7 @@ static int init_agc(struct drx_demod_instance *demod) sns_dir_to = (u16) (-9); ki_innergain_min = (u16) (-32768); ki_max = 0x032C; - agc_kiDgain = 0xC; + agc_ki_dgain = 0xC; if_iaccu_hi_tgt_min = 2047; ki_min = 0x0117; ingain_tgt_max = 16383; @@ -5448,7 +5448,7 @@ static int init_agc(struct drx_demod_instance *demod) ki_innergain_min = 0; ki_max = 0x0657; if_iaccu_hi_tgt_min = 2047; - agc_kiDgain = 0x7; + agc_ki_dgain = 0x7; ki_min = 0x0117; clp_ctrl_mode = 0; rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff, 0); @@ -5528,7 +5528,7 @@ static int init_agc(struct drx_demod_instance *demod) sns_sum_max = 1023; ki_innergain_min = (u16) (-32768); if_iaccu_hi_tgt_min = 2047; - agc_kiDgain = 0x7; + agc_ki_dgain = 0x7; ki_min = 0x0225; ki_max = 0x0547; clp_dir_to = (u16) (-9); @@ -5551,7 +5551,7 @@ static int init_agc(struct drx_demod_instance *demod) sns_sum_max = 1023; ki_innergain_min = (u16) (-32768); if_iaccu_hi_tgt_min = 2047; - agc_kiDgain = 0x7; + agc_ki_dgain = 0x7; ki_min = 0x0225; ki_max = 0x0547; clp_dir_to = (u16) (-9); @@ -5572,7 +5572,7 @@ static int init_agc(struct drx_demod_instance *demod) sns_sum_max = 1023; ki_innergain_min = (u16) (-32768); if_iaccu_hi_tgt_min = 2047; - agc_kiDgain = 0x7; + agc_ki_dgain = 0x7; ki_min = 0x0225; ki_max = 0x0547; clp_dir_to = (u16) (-9); @@ -5752,7 +5752,7 @@ static int init_agc(struct drx_demod_instance *demod) goto rw_error; } data &= ~SCU_RAM_AGC_KI_DGAIN__M; - data |= (agc_kiDgain << SCU_RAM_AGC_KI_DGAIN__B); + data |= (agc_ki_dgain << SCU_RAM_AGC_KI_DGAIN__B); rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_KI__A, data, 0); if (rc != DRX_STS_OK) { pr_err("error %d\n", rc); @@ -7616,16 +7616,16 @@ static int get_vsb_post_rs_pck_err(struct i2c_device_addr *dev_addr, u16 *pck_er u16 data = 0; u16 period = 0; u16 prescale = 0; - u16 packet_errorsMant = 0; - u16 packet_errorsExp = 0; + u16 packet_errors_mant = 0; + u16 packet_errors_exp = 0; rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_RS_NR_FAILURES__A, &data, 0); if (rc != DRX_STS_OK) { pr_err("error %d\n", rc); goto rw_error; } - packet_errorsMant = data & FEC_RS_NR_FAILURES_FIXED_MANT__M; - packet_errorsExp = (data & FEC_RS_NR_FAILURES_EXP__M) + packet_errors_mant = data & FEC_RS_NR_FAILURES_FIXED_MANT__M; + packet_errors_exp = (data & FEC_RS_NR_FAILURES_EXP__M) >> FEC_RS_NR_FAILURES_EXP__B; period = FEC_RS_MEASUREMENT_PERIOD; prescale = FEC_RS_MEASUREMENT_PRESCALE; @@ -7636,7 +7636,7 @@ static int get_vsb_post_rs_pck_err(struct i2c_device_addr *dev_addr, u16 *pck_er return DRX_STS_ERROR;; } *pck_errs = - (u16) frac_times1e6(packet_errorsMant * (1 << packet_errorsExp), + (u16) frac_times1e6(packet_errors_mant * (1 << packet_errors_exp), (period * prescale * 77)); return DRX_STS_OK; @@ -7791,7 +7791,7 @@ ctrl_get_vsb_constel(struct drx_demod_instance *demod, struct drx_complex *compl int rc; /**< device address */ u16 vsb_top_comm_mb = 0; /**< VSB SL MB configuration */ - u16 vsb_top_comm_mbInit = 0; /**< VSB SL MB intial configuration */ + u16 vsb_top_comm_mb_init = 0; /**< VSB SL MB intial configuration */ u16 re = 0; /**< constellation Re part */ u32 data = 0; @@ -7803,13 +7803,13 @@ ctrl_get_vsb_constel(struct drx_demod_instance *demod, struct drx_complex *compl /* Needs to be checked when external interface PG is updated */ /* Configure MB (Monitor bus) */ - rc = DRXJ_DAP.read_reg16func(dev_addr, VSB_TOP_COMM_MB__A, &vsb_top_comm_mbInit, 0); + rc = DRXJ_DAP.read_reg16func(dev_addr, VSB_TOP_COMM_MB__A, &vsb_top_comm_mb_init, 0); if (rc != DRX_STS_OK) { pr_err("error %d\n", rc); goto rw_error; } /* set observe flag & MB mux */ - vsb_top_comm_mb = (vsb_top_comm_mbInit | + vsb_top_comm_mb = (vsb_top_comm_mb_init | VSB_TOP_COMM_MB_OBS_OBS_ON | VSB_TOP_COMM_MB_MUX_OBS_VSB_TCMEQ_2); rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_COMM_MB__A, vsb_top_comm_mb, 0); @@ -7846,7 +7846,7 @@ ctrl_get_vsb_constel(struct drx_demod_instance *demod, struct drx_complex *compl complex_nr->im = 0; /* Restore MB (Monitor bus) */ - rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_COMM_MB__A, vsb_top_comm_mbInit, 0); + rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_COMM_MB__A, vsb_top_comm_mb_init, 0); if (rc != DRX_STS_OK) { pr_err("error %d\n", rc); goto rw_error; @@ -10612,14 +10612,14 @@ rw_error: } /** -* \fn int set_qamChannel () +* \fn int set_qam_channel () * \brief Set QAM channel according to the requested constellation. * \param demod: instance of demod. * \param channel: pointer to channel data. * \return int. */ static int -set_qamChannel(struct drx_demod_instance *demod, +set_qam_channel(struct drx_demod_instance *demod, struct drx_channel *channel, s32 tuner_freq_offset) { struct drxj_data *ext_attr = NULL; @@ -10802,7 +10802,7 @@ rw_error: /*============================================================================*/ /** -* \fn static short GetQAMRSErr_count(struct i2c_device_addr *dev_addr) +* \fn static short get_qamrs_err_count(struct i2c_device_addr *dev_addr) * \brief Get RS error count in QAM mode (used for post RS BER calculation) * \return Error code * @@ -10810,7 +10810,7 @@ rw_error: * */ static int -GetQAMRSErr_count(struct i2c_device_addr *dev_addr, struct drxjrs_errors *rs_errors) +get_qamrs_err_count(struct i2c_device_addr *dev_addr, struct drxjrs_errors *rs_errors) { int rc; u16 nr_bit_errors = 0, @@ -10924,7 +10924,7 @@ ctrl_get_qam_sig_quality(struct drx_demod_instance *demod, struct drx_sig_qualit /* read the physical registers */ /* Get the RS error data */ - rc = GetQAMRSErr_count(dev_addr, &measuredrs_errors); + rc = get_qamrs_err_count(dev_addr, &measuredrs_errors); if (rc != DRX_STS_OK) { pr_err("error %d\n", rc); goto rw_error; @@ -11096,7 +11096,7 @@ ctrl_get_qam_constel(struct drx_demod_instance *demod, struct drx_complex *compl u16 fec_oc_ocr_mode = 0; /**< FEC OCR grabber configuration */ u16 qam_sl_comm_mb = 0;/**< QAM SL MB configuration */ - u16 qam_sl_comm_mbInit = 0; + u16 qam_sl_comm_mb_init = 0; /**< QAM SL MB intial configuration */ u16 im = 0; /**< constellation Im part */ u16 re = 0; /**< constellation Re part */ @@ -11110,13 +11110,13 @@ ctrl_get_qam_constel(struct drx_demod_instance *demod, struct drx_complex *compl /* Needs to be checked when external interface PG is updated */ /* Configure MB (Monitor bus) */ - rc = DRXJ_DAP.read_reg16func(dev_addr, QAM_SL_COMM_MB__A, &qam_sl_comm_mbInit, 0); + rc = DRXJ_DAP.read_reg16func(dev_addr, QAM_SL_COMM_MB__A, &qam_sl_comm_mb_init, 0); if (rc != DRX_STS_OK) { pr_err("error %d\n", rc); goto rw_error; } /* set observe flag & MB mux */ - qam_sl_comm_mb = qam_sl_comm_mbInit & (~(QAM_SL_COMM_MB_OBS__M + + qam_sl_comm_mb = qam_sl_comm_mb_init & (~(QAM_SL_COMM_MB_OBS__M + QAM_SL_COMM_MB_MUX_OBS__M)); qam_sl_comm_mb |= (QAM_SL_COMM_MB_OBS_ON + QAM_SL_COMM_MB_MUX_OBS_CONST_CORR); @@ -11175,7 +11175,7 @@ ctrl_get_qam_constel(struct drx_demod_instance *demod, struct drx_complex *compl complex_nr->im = ((s16) im); /* Restore MB (Monitor bus) */ - rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_SL_COMM_MB__A, qam_sl_comm_mbInit, 0); + rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_SL_COMM_MB__A, qam_sl_comm_mb_init, 0); if (rc != DRX_STS_OK) { pr_err("error %d\n", rc); goto rw_error; @@ -12316,14 +12316,14 @@ trouble ? ucode_info.mc_size = common_attr->microcode_size; /* Upload only audio microcode */ - rc = ctrl_u_codeUpload(demod, &ucode_info, UCODE_UPLOAD, true); + rc = ctrl_u_code_upload(demod, &ucode_info, UCODE_UPLOAD, true); if (rc != DRX_STS_OK) { pr_err("error %d\n", rc); goto rw_error; } if (common_attr->verify_microcode == true) { - rc = ctrl_u_codeUpload(demod, &ucode_info, UCODE_VERIFY, true); + rc = ctrl_u_code_upload(demod, &ucode_info, UCODE_VERIFY, true); if (rc != DRX_STS_OK) { pr_err("error %d\n", rc); goto rw_error; @@ -13579,8 +13579,8 @@ static int aud_get_modus(struct drx_demod_instance *demod, u16 *modus) int rc; u16 r_modus = 0; - u16 r_modusHi = 0; - u16 r_modusLo = 0; + u16 r_modus_hi = 0; + u16 r_modus_lo = 0; if (modus == NULL) { return DRX_STS_INVALID_ARG; @@ -13600,19 +13600,19 @@ static int aud_get_modus(struct drx_demod_instance *demod, u16 *modus) } /* Modus register is combined in to RAM location */ - rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_RAM_MODUS_HI__A, &r_modusHi, 0); + rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_RAM_MODUS_HI__A, &r_modus_hi, 0); if (rc != DRX_STS_OK) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_RAM_MODUS_LO__A, &r_modusLo, 0); + rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_RAM_MODUS_LO__A, &r_modus_lo, 0); if (rc != DRX_STS_OK) { pr_err("error %d\n", rc); goto rw_error; } - r_modus = ((r_modusHi << 12) & AUD_DEM_RAM_MODUS_HI__M) - | (((r_modusLo & AUD_DEM_RAM_MODUS_LO__M))); + r_modus = ((r_modus_hi << 12) & AUD_DEM_RAM_MODUS_HI__M) + | (((r_modus_lo & AUD_DEM_RAM_MODUS_LO__M))); *modus = r_modus; @@ -16305,7 +16305,7 @@ get_oob_freq_offset(struct drx_demod_instance *demod, s32 *freq_offset) int rc; u16 data = 0; u16 rot = 0; - u16 symbol_rateReg = 0; + u16 symbol_rate_reg = 0; u32 symbol_rate = 0; s32 coarse_freq_offset = 0; s32 fine_freq_offset = 0; @@ -16351,12 +16351,12 @@ get_oob_freq_offset(struct drx_demod_instance *demod, s32 *freq_offset) /* get value in KHz */ coarse_freq_offset = coarse_sign * frac(temp_freq_offset, 1000, FRAC_ROUND); /* KHz */ /* read data rate */ - rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_ORX_RF_RX_DATA_RATE__A, &symbol_rateReg, 0); + rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_ORX_RF_RX_DATA_RATE__A, &symbol_rate_reg, 0); if (rc != DRX_STS_OK) { pr_err("error %d\n", rc); goto rw_error; } - switch (symbol_rateReg & SCU_RAM_ORX_RF_RX_DATA_RATE__M) { + switch (symbol_rate_reg & SCU_RAM_ORX_RF_RX_DATA_RATE__M) { case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC: case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC: case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC_ALT: @@ -16681,7 +16681,7 @@ static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_par struct i2c_device_addr *dev_addr = NULL; struct drxj_data *ext_attr = NULL; u16 i = 0; - bool mirror_freq_spectOOB = false; + bool mirror_freq_spect_oob = false; u16 trk_filter_value = 0; struct drxjscu_cmd scu_cmd; u16 set_param_parameters[3]; @@ -16703,7 +16703,7 @@ static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_par dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; - mirror_freq_spectOOB = ext_attr->mirror_freq_spectOOB; + mirror_freq_spect_oob = ext_attr->mirror_freq_spect_oob; /* Check parameters */ if (oob_param == NULL) { @@ -16797,12 +16797,12 @@ static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_par /* signal is transmitted inverted */ ((oob_param->spectrum_inverted == true) & /* and tuner is not mirroring the signal */ - (!mirror_freq_spectOOB)) | + (!mirror_freq_spect_oob)) | /* or */ /* signal is transmitted noninverted */ ((oob_param->spectrum_inverted == false) & /* and tuner is mirroring the signal */ - (mirror_freq_spectOOB)) + (mirror_freq_spect_oob)) ) set_param_parameters[0] = SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC; @@ -16815,12 +16815,12 @@ static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_par /* signal is transmitted inverted */ ((oob_param->spectrum_inverted == true) & /* and tuner is not mirroring the signal */ - (!mirror_freq_spectOOB)) | + (!mirror_freq_spect_oob)) | /* or */ /* signal is transmitted noninverted */ ((oob_param->spectrum_inverted == false) & /* and tuner is mirroring the signal */ - (mirror_freq_spectOOB)) + (mirror_freq_spect_oob)) ) set_param_parameters[0] = SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_INVSPEC; @@ -16834,12 +16834,12 @@ static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_par /* signal is transmitted inverted */ ((oob_param->spectrum_inverted == true) & /* and tuner is not mirroring the signal */ - (!mirror_freq_spectOOB)) | + (!mirror_freq_spect_oob)) | /* or */ /* signal is transmitted noninverted */ ((oob_param->spectrum_inverted == false) & /* and tuner is mirroring the signal */ - (mirror_freq_spectOOB)) + (mirror_freq_spect_oob)) ) set_param_parameters[0] = SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_INVSPEC; @@ -17752,7 +17752,7 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) case DRX_STANDARD_ITU_A: /* fallthrough */ case DRX_STANDARD_ITU_B: /* fallthrough */ case DRX_STANDARD_ITU_C: - rc = set_qamChannel(demod, channel, tuner_freq_offset); + rc = set_qam_channel(demod, channel, tuner_freq_offset); if (rc != DRX_STS_OK) { pr_err("error %d\n", rc); goto rw_error; @@ -17827,7 +17827,7 @@ ctrl_get_channel(struct drx_demod_instance *demod, struct drx_channel *channel) struct drx_common_attr *common_attr = NULL; s32 intermediate_freq = 0; s32 ctl_freq_offset = 0; - u32 iqm_rc_rateLo = 0; + u32 iqm_rc_rate_lo = 0; u32 adc_frequency = 0; #ifndef DRXJ_VSB_ONLY int bandwidth_temp = 0; @@ -17895,7 +17895,7 @@ ctrl_get_channel(struct drx_demod_instance *demod, struct drx_channel *channel) goto rw_error; } if ((lock_status == DRX_LOCKED) || (lock_status == DRXJ_DEMOD_LOCK)) { - rc = drxj_dap_atomic_read_reg32(dev_addr, IQM_RC_RATE_LO__A, &iqm_rc_rateLo, 0); + rc = drxj_dap_atomic_read_reg32(dev_addr, IQM_RC_RATE_LO__A, &iqm_rc_rate_lo, 0); if (rc != DRX_STS_OK) { pr_err("error %d\n", rc); goto rw_error; @@ -17903,7 +17903,7 @@ ctrl_get_channel(struct drx_demod_instance *demod, struct drx_channel *channel) adc_frequency = (common_attr->sys_clock_freq * 1000) / 3; channel->symbolrate = - frac28(adc_frequency, (iqm_rc_rateLo + (1 << 23))) >> 7; + frac28(adc_frequency, (iqm_rc_rate_lo + (1 << 23))) >> 7; switch (standard) { case DRX_STANDARD_8VSB: @@ -19095,7 +19095,7 @@ bool is_mc_block_audio(u32 addr) /*============================================================================*/ /** -* \fn int ctrl_u_codeUpload() +* \fn int ctrl_u_code_upload() * \brief Handle Audio or !Audio part of microcode upload. * \param demod Pointer to demodulator instance. * \param mc_info Pointer to information about microcode data. @@ -19105,7 +19105,7 @@ bool is_mc_block_audio(u32 addr) * \return int. */ static int -ctrl_u_codeUpload(struct drx_demod_instance *demod, +ctrl_u_code_upload(struct drx_demod_instance *demod, struct drxu_code_info *mc_info, enum drxu_code_actionaction, bool upload_audio_mc) { @@ -19194,7 +19194,7 @@ ctrl_u_codeUpload(struct drx_demod_instance *demod, case UCODE_VERIFY: { int result = 0; - u8 mc_dataBuffer + u8 mc_data_buffer [DRXJ_UCODE_MAX_BUF_SIZE]; u32 bytes_to_compare = 0; u32 bytes_left_to_compare = 0; @@ -19223,7 +19223,7 @@ ctrl_u_codeUpload(struct drx_demod_instance *demod, (u16) bytes_to_compare, (u8 *) - mc_dataBuffer, + mc_data_buffer, 0x0000) != DRX_STS_OK) { return DRX_STS_ERROR; @@ -19231,7 +19231,7 @@ ctrl_u_codeUpload(struct drx_demod_instance *demod, result = drxbsp_hst_memcmp(curr_ptr, - mc_dataBuffer, + mc_data_buffer, bytes_to_compare); if (result != 0) { @@ -20444,7 +20444,7 @@ int drxj_open(struct drx_demod_instance *demod) #ifdef DRXJ_SPLIT_UCODE_UPLOAD /* Upload microcode without audio part */ - rc = ctrl_u_codeUpload(demod, &ucode_info, UCODE_UPLOAD, false); + rc = ctrl_u_code_upload(demod, &ucode_info, UCODE_UPLOAD, false); if (rc != DRX_STS_OK) { pr_err("error %d\n", rc); goto rw_error; @@ -20458,7 +20458,7 @@ int drxj_open(struct drx_demod_instance *demod) #endif /* DRXJ_SPLIT_UCODE_UPLOAD */ if (common_attr->verify_microcode == true) { #ifdef DRXJ_SPLIT_UCODE_UPLOAD - rc = ctrl_u_codeUpload(demod, &ucode_info, UCODE_VERIFY, false); + rc = ctrl_u_code_upload(demod, &ucode_info, UCODE_VERIFY, false); if (rc != DRX_STS_OK) { pr_err("error %d\n", rc); goto rw_error; @@ -20483,7 +20483,7 @@ int drxj_open(struct drx_demod_instance *demod) /* Open tuner instance */ if (demod->my_tuner != NULL) { - demod->my_tuner->my_common_attr->myUser_data = (void *)demod; + demod->my_tuner->my_common_attr->my_user_data = (void *)demod; if (common_attr->tuner_port_nr == 1) { bool bridge_closed = true; @@ -20819,7 +20819,7 @@ drxj_ctrl(struct drx_demod_instance *demod, u32 ctrl, void *ctrl_data) /*======================================================================*/ case DRX_CTRL_GET_UIO_CFG: { - return CtrlGetuio_cfg(demod, (struct drxuio_cfg *)ctrl_data); + return ctrl_getuio_cfg(demod, (struct drxuio_cfg *)ctrl_data); } break; /*======================================================================*/ @@ -20872,14 +20872,14 @@ drxj_ctrl(struct drx_demod_instance *demod, u32 ctrl, void *ctrl_data) #ifdef DRXJ_SPLIT_UCODE_UPLOAD case DRX_CTRL_LOAD_UCODE: { - return ctrl_u_codeUpload(demod, + return ctrl_u_code_upload(demod, (p_drxu_code_info_t) ctrl_data, UCODE_UPLOAD, false); } break; case DRX_CTRL_VERIFY_UCODE: { - return ctrl_u_codeUpload(demod, + return ctrl_u_code_upload(demod, (p_drxu_code_info_t) ctrl_data, UCODE_VERIFY, false); } diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.h b/drivers/media/dvb-frontends/drx39xyj/drxj.h index f41a61e..c38245e 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.h +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.h @@ -426,7 +426,7 @@ struct drxj_cfg_atv_output { u8 mfx; /**< metal fix */ /* tuner settings */ - bool mirror_freq_spectOOB;/**< tuner inversion (true = tuner mirrors the signal */ + bool mirror_freq_spect_oob;/**< tuner inversion (true = tuner mirrors the signal */ /* standard/channel settings */ enum drx_standard standard; /**< current standard information */ @@ -446,7 +446,7 @@ struct drxj_cfg_atv_output { u16 fec_rs_prescale; /**< ReedSolomon Measurement Prescale */ u16 fec_rs_period; /**< ReedSolomon Measurement period */ bool reset_pkt_err_acc; /**< Set a flag to reset accumulated packet error */ - u16 pkt_errAccStart; /**< Set a flag to reset accumulated packet error */ + u16 pkt_err_acc_start; /**< Set a flag to reset accumulated packet error */ /* HI configuration */ u16 hi_cfg_timing_div; /**< HI Configure() parameter 2 */ -- cgit v1.1 From 60d3603ba0b69b69b2acfe3f60217e08788d489b Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Fri, 17 Jan 2014 07:00:31 -0300 Subject: [media] drx-j: Remove typedefs in drxj.c Remove three typedefs from drxj.c, using the following script: use File::Find; use strict; my $dir = shift or die "need a dir"; my $type = shift or die "need type"; my $var = shift or die "need var"; sub handle_file { my $file = shift; my $out; open IN, $file or die "can't open $file"; $out .= $_ while (); close IN; $out =~ s/\btypedef\s+($type)\s+\{([\d\D]+?)\s*\}\s+\b($var)[^\;]+\;/$type $var \{\2\};/; # This replaces the typedef declaration for a simple struct declaration - style 1 # This replaces the typedef declaration for a simple struct declaration - style 2 # Replace struct occurrences $out =~ s,\b($var)_t\s+,$type \1 ,g; $out =~ s,\bp_*($var)_t\s+,$type \1 *,g; $out =~ s,\b($var)_t\b,$type \1,g; $out =~ s,\bp_*($var)_t\b,$type \1 *,g; open OUT, ">$file" or die "can't open $file"; print OUT $out; close OUT; } sub parse_dir { my $file = $File::Find::name; return if (!($file =~ /.[ch]$/)); handle_file $file; } find({wanted => \&parse_dir, no_chdir => 1}, $dir); Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drxj.c | 27 ++++++++++++--------------- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index f6361b6..c5def7d 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -1050,37 +1050,34 @@ struct drx_aud_data drxj_default_aud_data_g = { /*----------------------------------------------------------------------------- STRUCTURES ----------------------------------------------------------------------------*/ -typedef struct { +struct drxjeq_stat { u16 eq_mse; u8 eq_mode; u8 eq_ctrl; - u8 eq_stat; -} drxjeq_stat_t, *pdrxjeq_stat_t; + u8 eq_stat;}; /* HI command */ -typedef struct { +struct drxj_hi_cmd { u16 cmd; u16 param1; u16 param2; u16 param3; u16 param4; u16 param5; - u16 param6; -} drxj_hi_cmd_t, *pdrxj_hi_cmd_t; + u16 param6;}; #ifdef DRXJ_SPLIT_UCODE_UPLOAD /*============================================================================*/ /*=== MICROCODE RELATED STRUCTURES ===========================================*/ /*============================================================================*/ -typedef struct { +struct drxu_code_block_hdr { u32 addr; u16 size; u16 flags; /* bit[15..2]=reserved, bit[1]= compression on/off bit[0]= CRC on/off */ - u16 CRC; -} drxu_code_block_hdr_t, *pdrxu_code_block_hdr_t; + u16 CRC;}; #endif /* DRXJ_SPLIT_UCODE_UPLOAD */ /*----------------------------------------------------------------------------- @@ -1089,7 +1086,7 @@ FUNCTIONS /* Some prototypes */ static int hi_command(struct i2c_device_addr *dev_addr, - const pdrxj_hi_cmd_t cmd, u16 *result); + const struct drxj_hi_cmd *cmd, u16 *result); static int ctrl_lock_status(struct drx_demod_instance *demod, enum drx_lock_status *lock_stat); @@ -2041,7 +2038,7 @@ int drxj_dap_atomic_read_write_block(struct i2c_device_addr *dev_addr, u16 datasize, u8 *data, bool read_flag) { - drxj_hi_cmd_t hi_cmd; + struct drxj_hi_cmd hi_cmd; int rc; u16 word; u16 dummy = 0; @@ -2171,7 +2168,7 @@ int drxj_dap_atomic_read_reg32(struct i2c_device_addr *dev_addr, static int hi_cfg_command(const struct drx_demod_instance *demod) { struct drxj_data *ext_attr = (struct drxj_data *) (NULL); - drxj_hi_cmd_t hi_cmd; + struct drxj_hi_cmd hi_cmd; u16 result = 0; int rc; @@ -2212,7 +2209,7 @@ rw_error: * */ static int -hi_command(struct i2c_device_addr *dev_addr, const pdrxj_hi_cmd_t cmd, u16 *result) +hi_command(struct i2c_device_addr *dev_addr, const struct drxj_hi_cmd *cmd, u16 *result) { u16 wait_cmd = 0; u16 nr_retries = 0; @@ -4334,7 +4331,7 @@ rw_error: static int ctrl_i2c_bridge(struct drx_demod_instance *demod, bool *bridge_closed) { - drxj_hi_cmd_t hi_cmd; + struct drxj_hi_cmd hi_cmd; u16 result = 0; /* check arguments */ @@ -19141,7 +19138,7 @@ ctrl_u_code_upload(struct drx_demod_instance *demod, /* Process microcode blocks */ for (i = 0; i < mc_nr_of_blks; i++) { - drxu_code_block_hdr_t block_hdr; + struct drxu_code_block_hdr block_hdr; u16 mc_block_nr_bytes = 0; /* Process block header */ -- cgit v1.1 From 6371351777640bffe63d37edbba226116d4d7034 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Fri, 17 Jan 2014 07:12:28 -0300 Subject: [media] drx-j: CodingStyle fixups on drxj.c Fix almost all checkpatch.pl warnings/errors on drxj.c, except for: - 80 cols whitespacing; - too many leading tabs; - a false positive at DRXJ_16TO8() macro. - static char array declaration should probably be static const char as adding "const" would cause warnings. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- .../media/dvb-frontends/drx39xyj/drx_dap_fasi.c | 6 +- drivers/media/dvb-frontends/drx39xyj/drx_driver.c | 17 +- drivers/media/dvb-frontends/drx39xyj/drxj.c | 1770 ++++++++------------ 3 files changed, 749 insertions(+), 1044 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c index 6053878..4671dcc 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c @@ -284,9 +284,8 @@ static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr, * No special action is needed for write chunks here. */ rc = drxbsp_i2c_write_read(dev_addr, bufx, buf, 0, 0, 0); - if (rc == DRX_STS_OK) { + if (rc == DRX_STS_OK) rc = drxbsp_i2c_write_read(0, 0, 0, dev_addr, todo, data); - } #else /* In multi master mode, do everything in one RW action */ rc = drxbsp_i2c_write_read(dev_addr, bufx, buf, dev_addr, todo, @@ -338,9 +337,8 @@ static int drxdap_fasi_read_modify_write_reg16(struct i2c_device_addr *dev_addr, } rc = drxdap_fasi_write_reg16(dev_addr, waddr, wdata, DRXDAP_FASI_RMW); - if (rc == DRX_STS_OK) { + if (rc == DRX_STS_OK) rc = drxdap_fasi_read_reg16(dev_addr, raddr, rdata, 0); - } #endif return rc; diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c index d1d9ded..4234b7d 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c @@ -186,9 +186,8 @@ static void *get_scan_context(struct drx_demod_instance *demod, void *scan_conte common_attr = (struct drx_common_attr *) demod->my_common_attr; scan_context = common_attr->scan_context; - if (scan_context == NULL) { + if (scan_context == NULL) scan_context = (void *)demod; - } return scan_context; } @@ -482,10 +481,8 @@ ctrl_scan_init(struct drx_demod_instance *demod, struct drx_scan_param *scan_par s32 n = 0; n = (min_tuner_freq - first_freq) / step; - if (((min_tuner_freq - - first_freq) % step) != 0) { + if (((min_tuner_freq - first_freq) % step) != 0) n++; - } min_freq = first_freq + n * step; } @@ -495,10 +492,8 @@ ctrl_scan_init(struct drx_demod_instance *demod, struct drx_scan_param *scan_par s32 n = 0; n = (last_freq - max_tuner_freq) / step; - if (((last_freq - - max_tuner_freq) % step) != 0) { + if (((last_freq - max_tuner_freq) % step) != 0) n++; - } max_freq = last_freq - n * step; } } @@ -950,9 +945,8 @@ static u16 u_code_compute_crc(u8 *block_data, u16 nr_words) crc_word |= (u32) u_code_read16(block_data); for (j = 0; j < 16; j++) { crc_word <<= 1; - if (carry != 0) { + if (carry != 0) crc_word ^= 0x80050000UL; - } carry = crc_word & 0x80000000UL; } i++; @@ -1320,9 +1314,8 @@ int drx_open(struct drx_demod_instance *demod) status = (*(demod->my_demod_funct->open_func)) (demod); - if (status == DRX_STS_OK) { + if (status == DRX_STS_OK) demod->my_common_attr->is_opened = true; - } return status; } diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index c5def7d..f1fe3e3 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -26,14 +26,9 @@ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ -/** -* \file $Id: drxj.c,v 1.637 2010/01/18 17:21:10 dingtao Exp $ -* -* \brief DRXJ specific implementation of DRX driver -* -* \author Dragan Savic, Milos Nikolic, Mihajlo Katona, Tao Ding, Paul Janssen + DRXJ specific implementation of DRX driver + authors: Dragan Savic, Milos Nikolic, Mihajlo Katona, Tao Ding, Paul Janssen */ /*----------------------------------------------------------------------------- @@ -487,7 +482,7 @@ DEFINES * x -> lowbyte(x), highbyte(x) */ #define DRXJ_16TO8(x) ((u8) (((u16)x) & 0xFF)), \ - ((u8)((((u16)x)>>8)&0xFF)) + ((u8)((((u16)x)>>8)&0xFF)) /** * This macro is used to convert byte array to 16 bit register value for block read. * Block read speed up I2C traffic between host and demod. @@ -526,14 +521,6 @@ DEFINES (std == DRX_STANDARD_ITU_D)) /*----------------------------------------------------------------------------- -STATIC VARIABLES -----------------------------------------------------------------------------*/ -int drxj_open(struct drx_demod_instance *demod); -int drxj_close(struct drx_demod_instance *demod); -int drxj_ctrl(struct drx_demod_instance *demod, - u32 ctrl, void *ctrl_data); - -/*----------------------------------------------------------------------------- GLOBAL VARIABLES ----------------------------------------------------------------------------*/ /* @@ -1054,7 +1041,8 @@ struct drxjeq_stat { u16 eq_mse; u8 eq_mode; u8 eq_ctrl; - u8 eq_stat;}; + u8 eq_stat; +}; /* HI command */ struct drxj_hi_cmd { @@ -1064,7 +1052,8 @@ struct drxj_hi_cmd { u16 param3; u16 param4; u16 param5; - u16 param6;}; + u16 param6; +}; #ifdef DRXJ_SPLIT_UCODE_UPLOAD /*============================================================================*/ @@ -1077,7 +1066,8 @@ struct drxu_code_block_hdr { u16 flags; /* bit[15..2]=reserved, bit[1]= compression on/off bit[0]= CRC on/off */ - u16 CRC;}; + u16 CRC; +}; #endif /* DRXJ_SPLIT_UCODE_UPLOAD */ /*----------------------------------------------------------------------------- @@ -1361,7 +1351,7 @@ static u32 log1_times100(u32 x) y /= 108853; /* (log2(10) << scale) */ r = (y >> 1); /* rounding */ - if (y & ((u32) 1)) + if (y & ((u32)1)) r++; return r; @@ -1396,9 +1386,8 @@ static u32 frac_times1e6(u32 N, u32 D) remainder <<= 4; frac += remainder / D; remainder = remainder % D; - if ((remainder * 2) > D) { + if ((remainder * 2) > D) frac++; - } return frac; } @@ -1589,8 +1578,8 @@ static u16 u_code_compute_crc(u8 *block_data, u16 nr_words) * and rounded. For calc used formula: 16*10^(prescaleGain[dB]/20). * */ -static const u16 nicam_presc_table_val[43] = - { 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, +static const u16 nicam_presc_table_val[43] = { + 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 7, 8, 9, 10, 11, 13, 14, 16, 18, 20, 23, 25, 28, 32, 36, 40, 45, 51, 57, 64, 71, 80, 90, 101, 113, 127 @@ -1702,9 +1691,8 @@ static int drxj_dap_rm_write_reg16short(struct i2c_device_addr *dev_addr, { int rc; - if (rdata == NULL) { + if (rdata == NULL) return DRX_STS_INVALID_ARG; - } /* Set RMW flag */ rc = drx_dap_fasi_funct_g.write_reg16func(dev_addr, @@ -1814,9 +1802,8 @@ static int drxj_dap_read_aud_reg16(struct i2c_device_addr *dev_addr, SIO_HI_RA_RAM_S0_RMWBUF__A, 0x0000, &tr_status); - if (stat != DRX_STS_OK) { + if (stat != DRX_STS_OK) break; - } current_timer = drxbsp_hst_clock(); delta_timer = current_timer - start_timer; @@ -1840,9 +1827,8 @@ static int drxj_dap_read_aud_reg16(struct i2c_device_addr *dev_addr, stat = drxj_dap_read_reg16(dev_addr, AUD_TOP_TR_CTR__A, &tr_status, 0x0000); - if (stat != DRX_STS_OK) { + if (stat != DRX_STS_OK) break; - } current_timer = drxbsp_hst_clock(); delta_timer = current_timer - start_timer; @@ -1853,15 +1839,12 @@ static int drxj_dap_read_aud_reg16(struct i2c_device_addr *dev_addr, } /* while ( ... ) */ } - /* if { stat == DRX_STS_OK ) */ /* Read value */ - if (stat == DRX_STS_OK) { + if (stat == DRX_STS_OK) stat = drxj_dap_read_modify_write_reg16(dev_addr, AUD_TOP_TR_RD_REG__A, SIO_HI_RA_RAM_S0_RMWBUF__A, 0x0000, data); - } - /* if { stat == DRX_STS_OK ) */ return stat; } @@ -1874,16 +1857,14 @@ static int drxj_dap_read_reg16(struct i2c_device_addr *dev_addr, int stat = DRX_STS_ERROR; /* Check param */ - if ((dev_addr == NULL) || (data == NULL)) { + if ((dev_addr == NULL) || (data == NULL)) return DRX_STS_INVALID_ARG; - } - if (is_handled_by_aud_tr_if(addr)) { + if (is_handled_by_aud_tr_if(addr)) stat = drxj_dap_read_aud_reg16(dev_addr, addr, data); - } else { + else stat = drx_dap_fasi_funct_g.read_reg16func(dev_addr, - addr, data, flags); - } + addr, data, flags); return stat; } @@ -1956,9 +1937,8 @@ static int drxj_dap_write_aud_reg16(struct i2c_device_addr *dev_addr, addr, SIO_HI_RA_RAM_S0_RMWBUF__A, data, &tr_status); - if (stat != DRX_STS_OK) { + if (stat != DRX_STS_OK) break; - } current_timer = drxbsp_hst_clock(); delta_timer = current_timer - start_timer; @@ -1986,16 +1966,14 @@ static int drxj_dap_write_reg16(struct i2c_device_addr *dev_addr, int stat = DRX_STS_ERROR; /* Check param */ - if (dev_addr == NULL) { + if (dev_addr == NULL) return DRX_STS_INVALID_ARG; - } - if (is_handled_by_aud_tr_if(addr)) { + if (is_handled_by_aud_tr_if(addr)) stat = drxj_dap_write_aud_reg16(dev_addr, addr, data); - } else { + else stat = drx_dap_fasi_funct_g.write_reg16func(dev_addr, - addr, data, flags); - } + addr, data, flags); return stat; } @@ -2045,11 +2023,8 @@ int drxj_dap_atomic_read_write_block(struct i2c_device_addr *dev_addr, u16 i = 0; /* Parameter check */ - if ((data == NULL) || - (dev_addr == NULL) || ((datasize % 2) != 0) || ((datasize / 2) > 8) - ) { + if (!data || !dev_addr || ((datasize % 2)) || ((datasize / 2) > 8)) return DRX_STS_INVALID_ARG; - } /* Set up HI parameters to read or write n bytes */ hi_cmd.cmd = SIO_HI_RA_RAM_CMD_ATOMIC_COPY; @@ -2059,11 +2034,10 @@ int drxj_dap_atomic_read_write_block(struct i2c_device_addr *dev_addr, hi_cmd.param2 = (u16) DRXDAP_FASI_ADDR2OFFSET(DRXJ_HI_ATOMIC_BUF_START); hi_cmd.param3 = (u16) ((datasize / 2) - 1); - if (!read_flag) { + if (!read_flag) hi_cmd.param3 |= DRXJ_HI_ATOMIC_WRITE; - } else { + else hi_cmd.param3 |= DRXJ_HI_ATOMIC_READ; - } hi_cmd.param4 = (u16) ((DRXDAP_FASI_ADDR2BLOCK(addr) << 6) + DRXDAP_FASI_ADDR2BANK(addr)); hi_cmd.param5 = (u16) DRXDAP_FASI_ADDR2OFFSET(addr); @@ -2119,12 +2093,11 @@ int drxj_dap_atomic_read_reg32(struct i2c_device_addr *dev_addr, int rc = DRX_STS_ERROR; u32 word = 0; - if (!data) { + if (!data) return DRX_STS_INVALID_ARG; - } rc = drxj_dap_atomic_read_write_block(dev_addr, addr, - sizeof(*data), buf, true); + sizeof(*data), buf, true); if (rc < 0) return 0; @@ -2270,10 +2243,8 @@ hi_command(struct i2c_device_addr *dev_addr, const struct drxj_hi_cmd *cmd, u16 goto rw_error; } - if ((cmd->cmd) == SIO_HI_RA_RAM_CMD_RESET) { - /* Allow for HI to reset */ + if ((cmd->cmd) == SIO_HI_RA_RAM_CMD_RESET) drxbsp_hst_sleep(1); - } /* Detect power down to ommit reading result */ powerdown_cmd = (bool) ((cmd->cmd == SIO_HI_RA_RAM_CMD_CONFIG) && @@ -2285,6 +2256,7 @@ hi_command(struct i2c_device_addr *dev_addr, const struct drxj_hi_cmd *cmd, u16 do { nr_retries++; if (nr_retries > DRXJ_MAX_RETRIES) { + pr_err("timeout\n"); goto rw_error; } @@ -2345,9 +2317,8 @@ static int init_hi(const struct drx_demod_instance *demod) ext_attr->hi_cfg_timing_div = (u16) ((common_attr->sys_clock_freq / 1000) * HI_I2C_DELAY) / 1000; /* Clipping */ - if ((ext_attr->hi_cfg_timing_div) > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M) { + if ((ext_attr->hi_cfg_timing_div) > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M) ext_attr->hi_cfg_timing_div = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M; - } /* Bridge delay, uses oscilator clock */ /* Delay = ( delay (nano seconds) * oscclk (kHz) )/ 1000 */ /* SDA brdige delay */ @@ -2355,9 +2326,8 @@ static int init_hi(const struct drx_demod_instance *demod) (u16) ((common_attr->osc_clock_freq / 1000) * HI_I2C_BRIDGE_DELAY) / 1000; /* Clipping */ - if ((ext_attr->hi_cfg_bridge_delay) > SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) { + if ((ext_attr->hi_cfg_bridge_delay) > SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) ext_attr->hi_cfg_bridge_delay = SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M; - } /* SCL bridge delay, same as SDA for now */ ext_attr->hi_cfg_bridge_delay += ((ext_attr->hi_cfg_bridge_delay) << SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B); @@ -2643,9 +2613,8 @@ static int power_up_device(struct drx_demod_instance *demod) /* Need some recovery time .... */ drxbsp_hst_sleep(10); - if (retry_count == DRXJ_MAX_RETRIES_POWERUP) { + if (retry_count == DRXJ_MAX_RETRIES_POWERUP) return DRX_STS_ERROR; - } return DRX_STS_OK; } @@ -2685,9 +2654,8 @@ ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M; /* check arguments */ - if ((demod == NULL) || (cfg_data == NULL)) { + if ((demod == NULL) || (cfg_data == NULL)) return DRX_STS_INVALID_ARG; - } dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -2939,35 +2907,30 @@ ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o } /* Control slective inversion of output bits */ - if (cfg_data->invert_data == true) { + if (cfg_data->invert_data == true) fec_oc_reg_ipr_invert |= invert_data_mask; - } else { + else fec_oc_reg_ipr_invert &= (~(invert_data_mask)); - } - if (cfg_data->invert_err == true) { + if (cfg_data->invert_err == true) fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MERR__M; - } else { + else fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MERR__M)); - } - if (cfg_data->invert_str == true) { + if (cfg_data->invert_str == true) fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MSTRT__M; - } else { + else fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MSTRT__M)); - } - if (cfg_data->invert_val == true) { + if (cfg_data->invert_val == true) fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MVAL__M; - } else { + else fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MVAL__M)); - } - if (cfg_data->invert_clk == true) { + if (cfg_data->invert_clk == true) fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MCLK__M; - } else { + else fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MCLK__M)); - } if (cfg_data->static_clk == true) { /* Static mode */ u32 dto_rate = 0; @@ -2980,9 +2943,8 @@ ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o switch (ext_attr->standard) { case DRX_STANDARD_8VSB: fec_oc_dto_period = 4; - if (cfg_data->insert_rs_byte == true) { + if (cfg_data->insert_rs_byte == true) fec_oc_dto_burst_len = 208; - } break; case DRX_STANDARD_ITU_A: { @@ -3001,15 +2963,13 @@ ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o break; case DRX_STANDARD_ITU_B: fec_oc_dto_period = 1; - if (cfg_data->insert_rs_byte == true) { + if (cfg_data->insert_rs_byte == true) fec_oc_dto_burst_len = 128; - } break; case DRX_STANDARD_ITU_C: fec_oc_dto_period = 1; - if (cfg_data->insert_rs_byte == true) { + if (cfg_data->insert_rs_byte == true) fec_oc_dto_burst_len = 204; - } break; default: return DRX_STS_ERROR; @@ -3045,10 +3005,8 @@ ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o pr_err("error %d\n", rc); goto rw_error; } - if (ext_attr->mpeg_output_clock_rate != - DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO) - fec_oc_dto_period = - ext_attr->mpeg_output_clock_rate - 1; + if (ext_attr->mpeg_output_clock_rate != DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO) + fec_oc_dto_period = ext_attr->mpeg_output_clock_rate - 1; rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period, 0); if (rc != DRX_STS_OK) { pr_err("error %d\n", rc); @@ -3343,9 +3301,9 @@ ctrl_get_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o u32 data64hi = 0; u32 data64lo = 0; - if (cfg_data == NULL) { + if (cfg_data == NULL) return DRX_STS_INVALID_ARG; - } + dev_addr = demod->my_i2c_dev_addr; common_attr = demod->my_common_attr; @@ -3491,10 +3449,8 @@ static int bit_reverse_mpeg_output(struct drx_demod_instance *demod) /* reset to default (normal bit order) */ fec_oc_ipr_mode &= (~FEC_OC_IPR_MODE_REVERSE_ORDER__M); - if (ext_attr->bit_reverse_mpeg_outout) { - /* reverse bit order */ + if (ext_attr->bit_reverse_mpeg_outout) fec_oc_ipr_mode |= FEC_OC_IPR_MODE_REVERSE_ORDER__M; - } rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode, 0); if (rc != DRX_STS_OK) { @@ -3569,9 +3525,8 @@ static int set_mpeg_start_width(struct drx_demod_instance *demod) goto rw_error; } fec_oc_comm_mb &= ~FEC_OC_COMM_MB_CTL_ON; - if (ext_attr->mpeg_start_width == DRXJ_MPEG_START_WIDTH_8CLKCYC) { + if (ext_attr->mpeg_start_width == DRXJ_MPEG_START_WIDTH_8CLKCYC) fec_oc_comm_mb |= FEC_OC_COMM_MB_CTL_ON; - } rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_COMM_MB__A, fec_oc_comm_mb, 0); if (rc != DRX_STS_OK) { pr_err("error %d\n", rc); @@ -3600,14 +3555,13 @@ static int ctrl_set_cfg_mpeg_output_misc(struct drx_demod_instance *demod, struct drxj_cfg_mpeg_output_misc *cfg_data) { - struct drxj_data *ext_attr = (struct drxj_data *) (NULL); + struct drxj_data *ext_attr = NULL; int rc; - if (cfg_data == NULL) { + if (cfg_data == NULL) return DRX_STS_INVALID_ARG; - } - ext_attr = (struct drxj_data *) demod->my_ext_attr; + ext_attr = demod->my_ext_attr; /* Set disable TEI bit handling flag. @@ -3667,13 +3621,12 @@ static int ctrl_get_cfg_mpeg_output_misc(struct drx_demod_instance *demod, struct drxj_cfg_mpeg_output_misc *cfg_data) { - struct drxj_data *ext_attr = (struct drxj_data *) (NULL); + struct drxj_data *ext_attr = NULL; int rc; u16 data = 0; - if (cfg_data == NULL) { + if (cfg_data == NULL) return DRX_STS_INVALID_ARG; - } ext_attr = (struct drxj_data *) demod->my_ext_attr; cfg_data->disable_tei_handling = ext_attr->disable_te_ihandling; @@ -3762,9 +3715,9 @@ static int ctrl_set_uio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg struct drxj_data *ext_attr = (struct drxj_data *) (NULL); int rc; - if ((uio_cfg == NULL) || (demod == NULL)) { + if ((uio_cfg == NULL) || (demod == NULL)) return DRX_STS_INVALID_ARG; - } + ext_attr = (struct drxj_data *) demod->my_ext_attr; /* Write magic word to enable pdr reg write */ @@ -3914,17 +3867,14 @@ static int ctrl_getuio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg * uio_available[DRX_UIO3] = &ext_attr->has_gpio; uio_available[DRX_UIO4] = &ext_attr->has_irqn; - if (uio_cfg == NULL) { + if (uio_cfg == NULL) return DRX_STS_INVALID_ARG; - } - if ((uio_cfg->uio > DRX_UIO4) || (uio_cfg->uio < DRX_UIO1)) { + if ((uio_cfg->uio > DRX_UIO4) || (uio_cfg->uio < DRX_UIO1)) return DRX_STS_INVALID_ARG; - } - if (!*uio_available[uio_cfg->uio]) { + if (!*uio_available[uio_cfg->uio]) return DRX_STS_ERROR; - } uio_cfg->mode = *uio_mode[uio_cfg->uio]; @@ -3946,9 +3896,8 @@ ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data) u16 pin_cfg_value = 0; u16 value = 0; - if ((uio_data == NULL) || (demod == NULL)) { + if ((uio_data == NULL) || (demod == NULL)) return DRX_STS_INVALID_ARG; - } ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -3987,11 +3936,11 @@ ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data) pr_err("error %d\n", rc); goto rw_error; } - if (uio_data->value == false) { + if (!uio_data->value) value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */ - } else { + else value |= 0x8000; /* write one to 15th bit - 1st UIO */ - } + /* write back to io data output register */ rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0); if (rc != DRX_STS_OK) { @@ -4004,9 +3953,9 @@ ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data) /* DRX_UIO2: SMA_RX UIO-2 */ if (!ext_attr->has_smarx) return DRX_STS_ERROR; - if (ext_attr->uio_sma_rx_mode != DRX_UIO_MODE_READWRITE) { + if (ext_attr->uio_sma_rx_mode != DRX_UIO_MODE_READWRITE) return DRX_STS_ERROR; - } + pin_cfg_value = 0; /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ pin_cfg_value |= 0x0113; @@ -4026,11 +3975,11 @@ ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data) pr_err("error %d\n", rc); goto rw_error; } - if (uio_data->value == false) { + if (!uio_data->value) value &= 0xBFFF; /* write zero to 14th bit - 2nd UIO */ - } else { + else value |= 0x4000; /* write one to 14th bit - 2nd UIO */ - } + /* write back to io data output register */ rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0); if (rc != DRX_STS_OK) { @@ -4043,9 +3992,9 @@ ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data) /* DRX_UIO3: ASEL UIO-3 */ if (!ext_attr->has_gpio) return DRX_STS_ERROR; - if (ext_attr->uio_gpio_mode != DRX_UIO_MODE_READWRITE) { + if (ext_attr->uio_gpio_mode != DRX_UIO_MODE_READWRITE) return DRX_STS_ERROR; - } + pin_cfg_value = 0; /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ pin_cfg_value |= 0x0113; @@ -4065,11 +4014,11 @@ ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data) pr_err("error %d\n", rc); goto rw_error; } - if (uio_data->value == false) { + if (!uio_data->value) value &= 0xFFFB; /* write zero to 2nd bit - 3rd UIO */ - } else { + else value |= 0x0004; /* write one to 2nd bit - 3rd UIO */ - } + /* write back to io data output register */ rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, value, 0); if (rc != DRX_STS_OK) { @@ -4083,9 +4032,9 @@ ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data) if (!ext_attr->has_irqn) return DRX_STS_ERROR; - if (ext_attr->uio_irqn_mode != DRX_UIO_MODE_READWRITE) { + if (ext_attr->uio_irqn_mode != DRX_UIO_MODE_READWRITE) return DRX_STS_ERROR; - } + pin_cfg_value = 0; /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ pin_cfg_value |= 0x0113; @@ -4105,11 +4054,11 @@ ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data) pr_err("error %d\n", rc); goto rw_error; } - if (uio_data->value == false) { + if (uio_data->value == false) value &= 0xEFFF; /* write zero to 12th bit - 4th UIO */ - } else { + else value |= 0x1000; /* write one to 12th bit - 4th UIO */ - } + /* write back to io data output register */ rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0); if (rc != DRX_STS_OK) { @@ -4148,9 +4097,8 @@ static int ctrl_uio_read(struct drx_demod_instance *demod, struct drxuio_data *u u16 pin_cfg_value = 0; u16 value = 0; - if ((uio_data == NULL) || (demod == NULL)) { + if ((uio_data == NULL) || (demod == NULL)) return DRX_STS_INVALID_ARG; - } ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -4167,9 +4115,9 @@ static int ctrl_uio_read(struct drx_demod_instance *demod, struct drxuio_data *u if (!ext_attr->has_smatx) return DRX_STS_ERROR; - if (ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_READWRITE) { + if (ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_READWRITE) return DRX_STS_ERROR; - } + pin_cfg_value = 0; /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ pin_cfg_value |= 0x0110; @@ -4200,9 +4148,9 @@ static int ctrl_uio_read(struct drx_demod_instance *demod, struct drxuio_data *u if (!ext_attr->has_smarx) return DRX_STS_ERROR; - if (ext_attr->uio_sma_rx_mode != DRX_UIO_MODE_READWRITE) { + if (ext_attr->uio_sma_rx_mode != DRX_UIO_MODE_READWRITE) return DRX_STS_ERROR; - } + pin_cfg_value = 0; /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ pin_cfg_value |= 0x0110; @@ -4222,11 +4170,11 @@ static int ctrl_uio_read(struct drx_demod_instance *demod, struct drxuio_data *u goto rw_error; } - if ((value & 0x4000) != 0) { /* check 14th bit - 2nd UIO */ + if ((value & 0x4000) != 0) /* check 14th bit - 2nd UIO */ uio_data->value = true; - } else { + else uio_data->value = false; - } + break; /*=====================================================================*/ case DRX_UIO3: @@ -4234,9 +4182,9 @@ static int ctrl_uio_read(struct drx_demod_instance *demod, struct drxuio_data *u if (!ext_attr->has_gpio) return DRX_STS_ERROR; - if (ext_attr->uio_gpio_mode != DRX_UIO_MODE_READWRITE) { + if (ext_attr->uio_gpio_mode != DRX_UIO_MODE_READWRITE) return DRX_STS_ERROR; - } + pin_cfg_value = 0; /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ pin_cfg_value |= 0x0110; @@ -4268,9 +4216,9 @@ static int ctrl_uio_read(struct drx_demod_instance *demod, struct drxuio_data *u if (!ext_attr->has_irqn) return DRX_STS_ERROR; - if (ext_attr->uio_irqn_mode != DRX_UIO_MODE_READWRITE) { + if (ext_attr->uio_irqn_mode != DRX_UIO_MODE_READWRITE) return DRX_STS_ERROR; - } + pin_cfg_value = 0; /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ pin_cfg_value |= 0x0110; @@ -4290,11 +4238,11 @@ static int ctrl_uio_read(struct drx_demod_instance *demod, struct drxuio_data *u pr_err("error %d\n", rc); goto rw_error; } - if ((value & 0x1000) != 0) { /* check 12th bit - 4th UIO */ + if ((value & 0x1000) != 0) /* check 12th bit - 4th UIO */ uio_data->value = true; - } else { + else uio_data->value = false; - } + break; /*====================================================================*/ default: @@ -4335,17 +4283,15 @@ ctrl_i2c_bridge(struct drx_demod_instance *demod, bool *bridge_closed) u16 result = 0; /* check arguments */ - if (bridge_closed == NULL) { + if (bridge_closed == NULL) return DRX_STS_INVALID_ARG; - } hi_cmd.cmd = SIO_HI_RA_RAM_CMD_BRDCTRL; hi_cmd.param1 = SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY; - if (*bridge_closed) { + if (*bridge_closed) hi_cmd.param2 = SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED; - } else { + else hi_cmd.param2 = SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN; - } return hi_command(demod->my_i2c_dev_addr, &hi_cmd, &result); } @@ -4387,22 +4333,19 @@ static int smart_ant_init(struct drx_demod_instance *demod) pr_err("error %d\n", rc); goto rw_error; } - if (ext_attr->smart_ant_inverted){ - - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_SA_TX_COMMAND__A, (data | SIO_SA_TX_COMMAND_TX_INVERT__M) | SIO_SA_TX_COMMAND_TX_ENABLE__M, 0); - if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; - } + if (ext_attr->smart_ant_inverted) { + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_SA_TX_COMMAND__A, (data | SIO_SA_TX_COMMAND_TX_INVERT__M) | SIO_SA_TX_COMMAND_TX_ENABLE__M, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; } - else - { - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_SA_TX_COMMAND__A, (data & (~SIO_SA_TX_COMMAND_TX_INVERT__M)) | SIO_SA_TX_COMMAND_TX_ENABLE__M, 0); - if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; - } + } else { + rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_SA_TX_COMMAND__A, (data & (~SIO_SA_TX_COMMAND_TX_INVERT__M)) | SIO_SA_TX_COMMAND_TX_ENABLE__M, 0); + if (rc != DRX_STS_OK) { + pr_err("error %d\n", rc); + goto rw_error; } + } /* config SMA_TX pin to smart antenna mode */ rc = ctrl_set_uio_cfg(demod, &uio_cfg); @@ -4454,9 +4397,8 @@ ctrl_set_cfg_smart_ant(struct drx_demod_instance *demod, struct drxj_cfg_smart_a ext_attr = (struct drxj_data *) demod->my_ext_attr; /* check arguments */ - if (smart_ant == NULL) { + if (smart_ant == NULL) return DRX_STS_INVALID_ARG; - } if (bit_inverted != ext_attr->smart_ant_inverted || ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_FIRMWARE_SMA) { @@ -4489,13 +4431,10 @@ ctrl_set_cfg_smart_ant(struct drx_demod_instance *demod, struct drxj_cfg_smart_a pr_err("error %d\n", rc); goto rw_error; } - } while ((data & SIO_SA_TX_STATUS_BUSY__M) - && ((drxbsp_hst_clock() - start_time) < - DRXJ_MAX_WAITTIME)); + } while ((data & SIO_SA_TX_STATUS_BUSY__M) && ((drxbsp_hst_clock() - start_time) < DRXJ_MAX_WAITTIME)); - if (data & SIO_SA_TX_STATUS_BUSY__M) { + if (data & SIO_SA_TX_STATUS_BUSY__M) return DRX_STS_ERROR; - } /* write to smart antenna configuration register */ rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_SA_TX_DATA0__A, 0x9200 | ((smart_ant->ctrl_data & 0x0001) << 8) | ((smart_ant->ctrl_data & 0x0002) << 10) | ((smart_ant->ctrl_data & 0x0004) << 12), 0); @@ -4564,9 +4503,8 @@ static int scu_command(struct i2c_device_addr *dev_addr, struct drxjscu_cmd *cmd pr_err("error %d\n", rc); goto rw_error; } - if (cur_cmd != DRX_SCU_READY) { + if (cur_cmd != DRX_SCU_READY) return DRX_STS_ERROR; - } switch (cmd->parameter_len) { case 5: @@ -4623,9 +4561,8 @@ static int scu_command(struct i2c_device_addr *dev_addr, struct drxjscu_cmd *cmd } while (!(cur_cmd == DRX_SCU_READY) && ((drxbsp_hst_clock() - start_time) < DRXJ_MAX_WAITTIME)); - if (cur_cmd != DRX_SCU_READY) { + if (cur_cmd != DRX_SCU_READY) return DRX_STS_ERROR; - } /* read results */ if ((cmd->result_len > 0) && (cmd->result != NULL)) { @@ -4676,11 +4613,10 @@ static int scu_command(struct i2c_device_addr *dev_addr, struct drxjscu_cmd *cmd return DRX_STS_INVALID_ARG; } /* here it is assumed that negative means error, and positive no error */ - else if (err < 0) { + else if (err < 0) return DRX_STS_ERROR; - } else { + else return DRX_STS_OK; - } } return DRX_STS_OK; @@ -4712,11 +4648,8 @@ int drxj_dap_scu_atomic_read_write_block(struct i2c_device_addr *dev_addr, u32 a u16 cmd_result[15]; /* Parameter check */ - if ((data == NULL) || - (dev_addr == NULL) || ((datasize % 2) != 0) || ((datasize / 2) > 16) - ) { + if (!data || !dev_addr || (datasize % 2) || ((datasize / 2) > 16)) return DRX_STS_INVALID_ARG; - } set_param_parameters[1] = (u16) ADDR_AT_SCU_SPACE(addr); if (read_flag) { /* read */ @@ -4777,9 +4710,8 @@ int drxj_dap_scu_atomic_read_reg16(struct i2c_device_addr *dev_addr, int rc = DRX_STS_ERROR; u16 word = 0; - if (!data) { + if (!data) return DRX_STS_INVALID_ARG; - } rc = drxj_dap_scu_atomic_read_write_block(dev_addr, addr, 2, buf, true); if (rc < 0) @@ -4862,25 +4794,22 @@ static int adc_sync_measurement(struct drx_demod_instance *demod, u16 *count) pr_err("error %d\n", rc); goto rw_error; } - if (data == 127) { + if (data == 127) *count = *count + 1; - } rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_PHASE1__A, &data, 0); if (rc != DRX_STS_OK) { pr_err("error %d\n", rc); goto rw_error; } - if (data == 127) { + if (data == 127) *count = *count + 1; - } rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_PHASE2__A, &data, 0); if (rc != DRX_STS_OK) { pr_err("error %d\n", rc); goto rw_error; } - if (data == 127) { + if (data == 127) *count = *count + 1; - } return DRX_STS_OK; rw_error: @@ -4937,10 +4866,9 @@ static int adc_synchronization(struct drx_demod_instance *demod) } } - if (count < 2) { - /* TODO: implement fallback scenarios */ + /* TODO: implement fallback scenarios */ + if (count < 2) return DRX_STS_ERROR; - } return DRX_STS_OK; rw_error: @@ -4965,20 +4893,10 @@ static int iqm_set_af(struct drx_demod_instance *demod, bool active) pr_err("error %d\n", rc); goto rw_error; } - if (!active) { - data &= ((~IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE) - & (~IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE) - & (~IQM_AF_STDBY_STDBY_PD_A2_ACTIVE) - & (~IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE) - & (~IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE) - ); - } else { /* active */ - data |= (IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE - | IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE - | IQM_AF_STDBY_STDBY_PD_A2_ACTIVE - | IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE - | IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE); - } + if (!active) + data &= ((~IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_PD_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE)); + else + data |= (IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE | IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE | IQM_AF_STDBY_STDBY_PD_A2_ACTIVE | IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE | IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE); rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_STDBY__A, data, 0); if (rc != DRX_STS_OK) { pr_err("error %d\n", rc); @@ -5261,9 +5179,8 @@ ctrl_get_cfg_pdr_safe_mode(struct drx_demod_instance *demod, bool *enabled) { struct drxj_data *ext_attr = (struct drxj_data *) NULL; - if (enabled == NULL) { + if (enabled == NULL) return DRX_STS_INVALID_ARG; - } ext_attr = (struct drxj_data *) demod->my_ext_attr; *enabled = ext_attr->pdr_safe_mode; @@ -5722,14 +5639,12 @@ static int init_agc(struct drx_demod_instance *demod) } agc_rf = 0x800 + p_agc_rf_settings->cut_off_current; - if (common_attr->tuner_rf_agc_pol == true) { + if (common_attr->tuner_rf_agc_pol == true) agc_rf = 0x87ff - agc_rf; - } agc_if = 0x800; - if (common_attr->tuner_if_agc_pol == true) { + if (common_attr->tuner_if_agc_pol == true) agc_rf = 0x87ff - agc_rf; - } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_AGC_RF__A, agc_rf, 0); if (rc != DRX_STS_OK) { @@ -5821,15 +5736,10 @@ set_frequency(struct drx_demod_instance *demod, } intermediate_freq = demod->my_common_attr->intermediate_freq; sampling_frequency = demod->my_common_attr->sys_clock_freq / 3; - if (tuner_mirror) { - /* tuner doesn't mirror */ - if_freq_actual = - intermediate_freq + rf_freq_residual + fm_frequency_shift; - } else { - /* tuner mirrors */ - if_freq_actual = - intermediate_freq - rf_freq_residual - fm_frequency_shift; - } + if (tuner_mirror) + if_freq_actual = intermediate_freq + rf_freq_residual + fm_frequency_shift; + else + if_freq_actual = intermediate_freq - rf_freq_residual - fm_frequency_shift; if (if_freq_actual > sampling_frequency / 2) { /* adc mirrors */ adc_freq = sampling_frequency - if_freq_actual; @@ -5913,7 +5823,7 @@ static int get_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength) else if (rf_gain > rf_agc_min) { if (rf_agc_max == rf_agc_min) { pr_err("error: rf_agc_max == rf_agc_min\n"); - return DRX_STS_ERROR;; + return DRX_STS_ERROR; } *sig_strength = 75 + 25 * (rf_gain - rf_agc_min) / (rf_agc_max - @@ -5923,14 +5833,14 @@ static int get_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength) } else if (if_gain > if_agc_sns) { if (if_agc_top == if_agc_sns) { pr_err("error: if_agc_top == if_agc_sns\n"); - return DRX_STS_ERROR;; + return DRX_STS_ERROR; } *sig_strength = 20 + 55 * (if_gain - if_agc_sns) / (if_agc_top - if_agc_sns); } else { if (!if_agc_sns) { pr_err("error: if_agc_sns is zero!\n"); - return DRX_STS_ERROR;; + return DRX_STS_ERROR; } *sig_strength = (20 * if_gain / if_agc_sns); } @@ -6177,19 +6087,17 @@ set_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, goto rw_error; } data &= ~SCU_RAM_AGC_KI_RF__M; - if (ext_attr->standard == DRX_STANDARD_8VSB) { + if (ext_attr->standard == DRX_STANDARD_8VSB) data |= (2 << SCU_RAM_AGC_KI_RF__B); - } else if (DRXJ_ISQAMSTD(ext_attr->standard)) { + else if (DRXJ_ISQAMSTD(ext_attr->standard)) data |= (5 << SCU_RAM_AGC_KI_RF__B); - } else { + else data |= (4 << SCU_RAM_AGC_KI_RF__B); - } - if (common_attr->tuner_rf_agc_pol) { + if (common_attr->tuner_rf_agc_pol) data |= SCU_RAM_AGC_KI_INV_RF_POL__M; - } else { + else data &= ~SCU_RAM_AGC_KI_INV_RF_POL__M; - } rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0); if (rc != DRX_STS_OK) { pr_err("error %d\n", rc); @@ -6203,7 +6111,7 @@ set_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, goto rw_error; } data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M; - rc = (*scu_wr16) (dev_addr, SCU_RAM_AGC_KI_RED__A,(~(agc_settings->speed << SCU_RAM_AGC_KI_RED_RAGC_RED__B) & SCU_RAM_AGC_KI_RED_RAGC_RED__M) | data, 0); + rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, (~(agc_settings->speed << SCU_RAM_AGC_KI_RED_RAGC_RED__B) & SCU_RAM_AGC_KI_RED_RAGC_RED__M) | data, 0); if (rc != DRX_STS_OK) { pr_err("error %d\n", rc); goto rw_error; @@ -6261,11 +6169,10 @@ set_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, goto rw_error; } data &= ~SCU_RAM_AGC_KI_RF__M; - if (common_attr->tuner_rf_agc_pol) { + if (common_attr->tuner_rf_agc_pol) data |= SCU_RAM_AGC_KI_INV_RF_POL__M; - } else { + else data &= ~SCU_RAM_AGC_KI_INV_RF_POL__M; - } rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0); if (rc != DRX_STS_OK) { pr_err("error %d\n", rc); @@ -6470,19 +6377,17 @@ set_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, } data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M; data &= ~SCU_RAM_AGC_KI_IF__M; - if (ext_attr->standard == DRX_STANDARD_8VSB) { + if (ext_attr->standard == DRX_STANDARD_8VSB) data |= (3 << SCU_RAM_AGC_KI_IF__B); - } else if (DRXJ_ISQAMSTD(ext_attr->standard)) { + else if (DRXJ_ISQAMSTD(ext_attr->standard)) data |= (6 << SCU_RAM_AGC_KI_IF__B); - } else { + else data |= (5 << SCU_RAM_AGC_KI_IF__B); - } - if (common_attr->tuner_if_agc_pol) { + if (common_attr->tuner_if_agc_pol) data |= SCU_RAM_AGC_KI_INV_IF_POL__M; - } else { + else data &= ~SCU_RAM_AGC_KI_INV_IF_POL__M; - } rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0); if (rc != DRX_STS_OK) { pr_err("error %d\n", rc); @@ -6560,11 +6465,10 @@ set_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, } data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M; data |= SCU_RAM_AGC_KI_IF_AGC_DISABLE__M; - if (common_attr->tuner_if_agc_pol) { + if (common_attr->tuner_if_agc_pol) data |= SCU_RAM_AGC_KI_INV_IF_POL__M; - } else { + else data &= ~SCU_RAM_AGC_KI_INV_IF_POL__M; - } rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0); if (rc != DRX_STS_OK) { pr_err("error %d\n", rc); @@ -6739,21 +6643,10 @@ static int set_iqm_af(struct drx_demod_instance *demod, bool active) pr_err("error %d\n", rc); goto rw_error; } - if (!active) { - data &= ((~IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE) - & (~IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE) - & (~IQM_AF_STDBY_STDBY_PD_A2_ACTIVE) - & (~IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE) - & (~IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE) - ); - } else { /* active */ - - data |= (IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE - | IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE - | IQM_AF_STDBY_STDBY_PD_A2_ACTIVE - | IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE - | IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE); - } + if (!active) + data &= ((~IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_PD_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE)); + else + data |= (IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE | IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE | IQM_AF_STDBY_STDBY_PD_A2_ACTIVE | IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE | IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE); rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_STDBY__A, data, 0); if (rc != DRX_STS_OK) { pr_err("error %d\n", rc); @@ -7630,7 +7523,7 @@ static int get_vsb_post_rs_pck_err(struct i2c_device_addr *dev_addr, u16 *pck_er /* 77.3 us is time for per packet */ if (period * prescale == 0) { pr_err("error: period and/or prescale is zero!\n"); - return DRX_STS_ERROR;; + return DRX_STS_ERROR; } *pck_errs = (u16) frac_times1e6(packet_errors_mant * (1 << packet_errors_exp), @@ -7672,7 +7565,7 @@ static int get_vs_bpost_viterbi_ber(struct i2c_device_addr *dev_addr, u32 *ber) else { if (period * prescale == 0) { pr_err("error: period and/or prescale is zero!\n"); - return DRX_STS_ERROR;; + return DRX_STS_ERROR; } *ber = frac_times1e6(bit_errors_mant << @@ -7739,7 +7632,7 @@ static int get_vsb_symb_err(struct i2c_device_addr *dev_addr, u32 *ser) if (period * prescale == 0) { pr_err("error: period and/or prescale is zero!\n"); - return DRX_STS_ERROR;; + return DRX_STS_ERROR; } *ser = (u32) frac_times1e6((symb_errors_mant << symb_errors_exp) * 1000, (period * prescale * 77318)); @@ -7836,9 +7729,8 @@ ctrl_get_vsb_constel(struct drx_demod_instance *demod, struct drx_complex *compl goto rw_error; } re = (u16) (((data >> 10) & 0x300) | ((data >> 2) & 0xff)); - if (re & 0x0200) { + if (re & 0x0200) re |= 0xfc00; - } complex_nr->re = re; complex_nr->im = 0; @@ -8049,7 +7941,7 @@ set_qam_measurement(struct drx_demod_instance *demod, fec_rs_bit_cnt = fec_rs_prescale * fec_rs_plen; /* temp storage */ if (fec_rs_bit_cnt == 0) { pr_err("error: fec_rs_bit_cnt is zero!\n"); - return DRX_STS_ERROR;; + return DRX_STS_ERROR; } fec_rs_period = fec_bits_desired / fec_rs_bit_cnt + 1; /* ceil */ if (ext_attr->standard != DRX_STANDARD_ITU_B) @@ -8146,7 +8038,7 @@ set_qam_measurement(struct drx_demod_instance *demod, } if (qam_vd_period == 0) { pr_err("error: qam_vd_period is zero!\n"); - return DRX_STS_ERROR;; + return DRX_STS_ERROR; } qam_vd_period = fec_bits_desired / qam_vd_period; /* limit to max 16 bit value (I2C register width) if needed */ @@ -9531,7 +9423,7 @@ set_qam(struct drx_demod_instance *demod, adc_frequency = (common_attr->sys_clock_freq * 1000) / 3; if (channel->symbolrate == 0) { pr_err("error: channel symbolrate is zero!\n"); - return DRX_STS_ERROR;; + return DRX_STS_ERROR; } iqm_rc_rate = (adc_frequency / channel->symbolrate) * (1 << 21) + @@ -10635,11 +10527,10 @@ set_qam_channel(struct drx_demod_instance *demod, case DRX_CONSTELLATION_QAM128: case DRX_CONSTELLATION_QAM256: ext_attr->constellation = channel->constellation; - if (channel->mirror == DRX_MIRROR_AUTO) { + if (channel->mirror == DRX_MIRROR_AUTO) ext_attr->mirror = DRX_MIRROR_NO; - } else { + else ext_attr->mirror = channel->mirror; - } rc = set_qam(demod, channel, tuner_freq_offset, QAM_SET_OP_ALL); if (rc != DRX_STS_OK) { pr_err("error %d\n", rc); @@ -10671,11 +10562,10 @@ set_qam_channel(struct drx_demod_instance *demod, /* try to lock default QAM constellation: QAM64 */ channel->constellation = DRX_CONSTELLATION_QAM256; ext_attr->constellation = DRX_CONSTELLATION_QAM256; - if (channel->mirror == DRX_MIRROR_AUTO) { + if (channel->mirror == DRX_MIRROR_AUTO) ext_attr->mirror = DRX_MIRROR_NO; - } else { + else ext_attr->mirror = channel->mirror; - } rc = set_qam(demod, channel, tuner_freq_offset, QAM_SET_OP_ALL); if (rc != DRX_STS_OK) { pr_err("error %d\n", rc); @@ -10693,11 +10583,10 @@ set_qam_channel(struct drx_demod_instance *demod, DRX_CONSTELLATION_QAM64; ext_attr->constellation = DRX_CONSTELLATION_QAM64; - if (channel->mirror == DRX_MIRROR_AUTO) { + if (channel->mirror == DRX_MIRROR_AUTO) ext_attr->mirror = DRX_MIRROR_NO; - } else { + else ext_attr->mirror = channel->mirror; - } { u16 qam_ctl_ena = 0; rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SCU_RAM_QAM_CTL_ENA__A, &qam_ctl_ena, 0); @@ -10739,11 +10628,10 @@ set_qam_channel(struct drx_demod_instance *demod, ext_attr->constellation = DRX_CONSTELLATION_QAM64; auto_flag = true; - if (channel->mirror == DRX_MIRROR_AUTO) { + if (channel->mirror == DRX_MIRROR_AUTO) ext_attr->mirror = DRX_MIRROR_NO; - } else { + else ext_attr->mirror = channel->mirror; - } { u16 qam_ctl_ena = 0; rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SCU_RAM_QAM_CTL_ENA__A, &qam_ctl_ena, 0); @@ -10815,9 +10703,8 @@ get_qamrs_err_count(struct i2c_device_addr *dev_addr, struct drxjrs_errors *rs_e nr_packet_errors = 0, nr_failures = 0, nr_snc_par_fail_count = 0; /* check arguments */ - if (dev_addr == NULL) { + if (dev_addr == NULL) return DRX_STS_INVALID_ARG; - } /* all reported errors are received in the */ /* most recently finished measurment period */ @@ -10977,9 +10864,7 @@ ctrl_get_qam_sig_quality(struct drx_demod_instance *demod, struct drx_sig_qualit if (qam_sl_err_power == 0) qam_sl_mer = 0; else - qam_sl_mer = - log1_times100(qam_sl_sig_power) - - log1_times100((u32) qam_sl_err_power); + qam_sl_mer = log1_times100(qam_sl_sig_power) - log1_times100((u32)qam_sl_err_power); /* ----------------------------------------- */ /* Pre Viterbi Symbol Error Rate Calculation */ @@ -11000,13 +10885,10 @@ ctrl_get_qam_sig_quality(struct drx_demod_instance *demod, struct drx_sig_qualit m = (qsym_err_vd & QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__M) >> QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__B; - if ((m << e) >> 3 > 549752) { /* the max of frac_times1e6 */ - qam_vd_ser = 500000; /* clip BER 0.5 */ - } else { - qam_vd_ser = - frac_times1e6(m << ((e > 2) ? (e - 3) : e), - vd_bit_cnt * ((e > 2) ? 1 : 8) / 8); - } + if ((m << e) >> 3 > 549752) + qam_vd_ser = 500000; + else + qam_vd_ser = frac_times1e6(m << ((e > 2) ? (e - 3) : e), vd_bit_cnt * ((e > 2) ? 1 : 8) / 8); /* --------------------------------------- */ /* pre and post RedSolomon BER Calculation */ @@ -11027,11 +10909,10 @@ ctrl_get_qam_sig_quality(struct drx_demod_instance *demod, struct drx_sig_qualit ber_cnt = m << e; /*qam_pre_rs_ber = frac_times1e6( ber_cnt, rs_bit_cnt ); */ - if (m > (rs_bit_cnt >> (e + 1)) || (rs_bit_cnt >> e) == 0) { - qam_pre_rs_ber = 500000; /* clip BER 0.5 */ - } else { + if (m > (rs_bit_cnt >> (e + 1)) || (rs_bit_cnt >> e) == 0) + qam_pre_rs_ber = 500000; + else qam_pre_rs_ber = frac_times1e6(m, rs_bit_cnt >> e); - } /* post RS BER = 1000000* (11.17 * FEC_OC_SNC_FAIL_COUNT__A) / */ /* (1504.0 * FEC_OC_SNC_FAIL_PERIOD__A) */ @@ -11053,11 +10934,10 @@ ctrl_get_qam_sig_quality(struct drx_demod_instance *demod, struct drx_sig_qualit /* fill signal quality data structure */ sig_quality->MER = ((u16) qam_sl_mer); - if (ext_attr->standard == DRX_STANDARD_ITU_B) { + if (ext_attr->standard == DRX_STANDARD_ITU_B) sig_quality->pre_viterbi_ber = qam_vd_ser; - } else { + else sig_quality->pre_viterbi_ber = qam_pre_rs_ber; - } sig_quality->post_viterbi_ber = qam_pre_rs_ber; sig_quality->post_reed_solomon_ber = qam_post_rs_ber; sig_quality->scale_factor_ber = ((u32) 1000000); @@ -11162,12 +11042,10 @@ ctrl_get_qam_constel(struct drx_demod_instance *demod, struct drx_complex *compl /* interpret data (re & im) according to the Monitor bus mapping ?? */ /* sign extension, 10th bit is sign bit */ - if ((re & 0x0200) == 0x0200) { + if ((re & 0x0200) == 0x0200) re |= 0xFC00; - } - if ((im & 0x0200) == 0x0200) { + if ((im & 0x0200) == 0x0200) im |= 0xFC00; - } complex_nr->re = ((s16) re); complex_nr->im = ((s16) im); @@ -11351,11 +11229,10 @@ atv_update_config(struct drx_demod_instance *demod, bool force_update) goto rw_error; } data &= (~((u16) IQM_RT_ROT_BP_ROT_OFF__M)); - if (ext_attr->phase_correction_bypass) { + if (ext_attr->phase_correction_bypass) data |= IQM_RT_ROT_BP_ROT_OFF_OFF; - } else { + else data |= IQM_RT_ROT_BP_ROT_OFF_ACTIVE; - } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_ROT_BP__A, data, 0); if (rc != DRX_STS_OK) { pr_err("error %d\n", rc); @@ -11422,17 +11299,15 @@ atv_update_config(struct drx_demod_instance *demod, bool force_update) pr_err("error %d\n", rc); goto rw_error; } - if (ext_attr->enable_cvbs_output) { + if (ext_attr->enable_cvbs_output) data |= ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE; - } else { + else data &= (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE); - } - if (ext_attr->enable_sif_output) { + if (ext_attr->enable_sif_output) data &= (~ATV_TOP_STDBY_SIF_STDBY_STANDBY); - } else { + else data |= ATV_TOP_STDBY_SIF_STDBY_STANDBY; - } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_STDBY__A, data, 0); if (rc != DRX_STS_OK) { pr_err("error %d\n", rc); @@ -11463,9 +11338,8 @@ ctrl_set_cfg_atv_output(struct drx_demod_instance *demod, struct drxj_cfg_atv_ou int rc; /* Check arguments */ - if (output_cfg == NULL) { + if (output_cfg == NULL) return DRX_STS_INVALID_ARG; - } ext_attr = (struct drxj_data *) demod->my_ext_attr; if (output_cfg->enable_sif_output) { @@ -11528,9 +11402,8 @@ ctrl_set_cfg_atv_equ_coef(struct drx_demod_instance *demod, struct drxj_cfg_atv_ ext_attr = (struct drxj_data *) demod->my_ext_attr; /* current standard needs to be an ATV standard */ - if (!DRXJ_ISATVSTD(ext_attr->standard)) { + if (!DRXJ_ISATVSTD(ext_attr->standard)) return DRX_STS_ERROR; - } /* Check arguments */ if ((coef == NULL) || @@ -11591,14 +11464,12 @@ ctrl_get_cfg_atv_equ_coef(struct drx_demod_instance *demod, struct drxj_cfg_atv_ ext_attr = (struct drxj_data *) demod->my_ext_attr; /* current standard needs to be an ATV standard */ - if (!DRXJ_ISATVSTD(ext_attr->standard)) { + if (!DRXJ_ISATVSTD(ext_attr->standard)) return DRX_STS_ERROR; - } /* Check arguments */ - if (coef == NULL) { + if (coef == NULL) return DRX_STS_INVALID_ARG; - } rc = atv_equ_coef_index(ext_attr->standard, &index); if (rc != DRX_STS_OK) { @@ -11709,20 +11580,18 @@ ctrl_get_cfg_atv_output(struct drx_demod_instance *demod, struct drxj_cfg_atv_ou u16 data = 0; /* Check arguments */ - if (output_cfg == NULL) { + if (output_cfg == NULL) return DRX_STS_INVALID_ARG; - } rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, ATV_TOP_STDBY__A, &data, 0); if (rc != DRX_STS_OK) { pr_err("error %d\n", rc); goto rw_error; } - if (data & ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE) { + if (data & ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE) output_cfg->enable_cvbs_output = true; - } else { + else output_cfg->enable_cvbs_output = false; - } if (data & ATV_TOP_STDBY_SIF_STDBY_STANDBY) { output_cfg->enable_sif_output = false; @@ -11779,9 +11648,8 @@ ctrl_get_cfg_atv_agc_status(struct drx_demod_instance *demod, tmp = ((u32) data) * 27 - ((u32) (data >> 2)); /* nA */ agc_status->rf_agc_gain = (u16) (tmp / 1000); /* uA */ /* rounding */ - if (tmp % 1000 >= 500) { + if (tmp % 1000 >= 500) (agc_status->rf_agc_gain)++; - } /* IFgain = (IQM_AF_AGC_IF__A * 26.75)/1000 (uA) @@ -11797,9 +11665,8 @@ ctrl_get_cfg_atv_agc_status(struct drx_demod_instance *demod, tmp = ((u32) data) * 27 - ((u32) (data >> 2)); /* nA */ agc_status->if_agc_gain = (u16) (tmp / 1000); /* uA */ /* rounding */ - if (tmp % 1000 >= 500) { + if (tmp % 1000 >= 500) (agc_status->if_agc_gain)++; - } /* videoGain = (ATV_TOP_SFR_VID_GAIN__A/16 -150)* 0.05 (dB) @@ -11816,9 +11683,8 @@ ctrl_get_cfg_atv_agc_status(struct drx_demod_instance *demod, } /* dividing by 32 inclusive rounding */ data >>= 4; - if ((data & 1) != 0) { + if ((data & 1) != 0) data++; - } data >>= 1; agc_status->video_agc_gain = ((s16) data) - 75; /* 0.1 dB */ @@ -11837,9 +11703,8 @@ ctrl_get_cfg_atv_agc_status(struct drx_demod_instance *demod, } data &= SCU_RAM_ATV_SIF_GAIN__M; /* dividing by 2 inclusive rounding */ - if ((data & 1) != 0) { + if ((data & 1) != 0) data++; - } data >>= 1; agc_status->audio_agc_gain = ((s16) data) - 4; /* 0.1 dB */ @@ -12334,33 +12199,33 @@ trouble ? rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_STOP, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } /* Reset ATV SCU */ cmd_scu.command = SCU_RAM_COMMAND_STANDARD_ATV | @@ -12377,8 +12242,8 @@ trouble ? rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_MOD_CONTROL__A, ATV_TOP_MOD_CONTROL__PRE, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } /* TODO remove AUTO/OFF patches after ucode fix. */ @@ -12389,70 +12254,70 @@ trouble ? rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_LO_INCR__A, IQM_RT_LO_INCR_MN, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(ntsc_taps_re), ((u8 *)ntsc_taps_re), 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(ntsc_taps_im), ((u8 *)ntsc_taps_im), 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_AMP_TH__A, ATV_TOP_CR_AMP_TH_MN, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_CONT__A, (ATV_TOP_CR_CONT_CR_P_MN | ATV_TOP_CR_CONT_CR_D_MN | ATV_TOP_CR_CONT_CR_I_MN), 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_MN, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_MN | ATV_TOP_STD_VID_POL_MN), 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_MN, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM | SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE), 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_BG_MN, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } ext_attr->phase_correction_bypass = false; ext_attr->enable_cvbs_output = true; @@ -12463,49 +12328,49 @@ trouble ? rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_LO_INCR__A, 2994, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_MIDTAP__A, 0, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(fm_taps_re), ((u8 *)fm_taps_re), 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(fm_taps_im), ((u8 *)fm_taps_im), 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_FM | ATV_TOP_STD_VID_POL_FM), 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_MOD_CONTROL__A, 0, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_CONT__A, 0, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW | SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM), 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_ROT_BP__A, IQM_RT_ROT_BP_ROT_OFF_OFF, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } ext_attr->phase_correction_bypass = true; ext_attr->enable_cvbs_output = false; @@ -12516,68 +12381,68 @@ trouble ? rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_LO_INCR__A, 1820, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } /* TODO check with IS */ rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(bg_taps_re), ((u8 *)bg_taps_re), 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(bg_taps_im), ((u8 *)bg_taps_im), 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_BG, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_AMP_TH__A, ATV_TOP_CR_AMP_TH_BG, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_CONT__A, (ATV_TOP_CR_CONT_CR_P_BG | ATV_TOP_CR_CONT_CR_D_BG | ATV_TOP_CR_CONT_CR_I_BG), 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_BG, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_BG | ATV_TOP_STD_VID_POL_BG), 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM | SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE), 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_BG_MN, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } ext_attr->phase_correction_bypass = false; ext_attr->atv_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; @@ -12589,68 +12454,68 @@ trouble ? rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_LO_INCR__A, 2225, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } /* TODO check with IS */ rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(dk_i_l_lp_taps_re), ((u8 *)dk_i_l_lp_taps_re), 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(dk_i_l_lp_taps_im), ((u8 *)dk_i_l_lp_taps_im), 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_AMP_TH__A, ATV_TOP_CR_AMP_TH_DK, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_DK, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_CONT__A, (ATV_TOP_CR_CONT_CR_P_DK | ATV_TOP_CR_CONT_CR_D_DK | ATV_TOP_CR_CONT_CR_I_DK), 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_DK, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_DK | ATV_TOP_STD_VID_POL_DK), 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM | SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE), 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_DK, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } ext_attr->phase_correction_bypass = false; ext_attr->atv_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; @@ -12662,68 +12527,68 @@ trouble ? rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_LO_INCR__A, 2225, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } /* TODO check with IS */ rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(dk_i_l_lp_taps_re), ((u8 *)dk_i_l_lp_taps_re), 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(dk_i_l_lp_taps_im), ((u8 *)dk_i_l_lp_taps_im), 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_AMP_TH__A, ATV_TOP_CR_AMP_TH_I, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_I, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_CONT__A, (ATV_TOP_CR_CONT_CR_P_I | ATV_TOP_CR_CONT_CR_D_I | ATV_TOP_CR_CONT_CR_I_I), 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_I, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_I | ATV_TOP_STD_VID_POL_I), 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM | SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE), 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_I, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } ext_attr->phase_correction_bypass = false; ext_attr->atv_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; @@ -12735,68 +12600,68 @@ trouble ? rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_LO_INCR__A, 2225, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } /* TODO check with IS */ rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_L, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(dk_i_l_lp_taps_re), ((u8 *)dk_i_l_lp_taps_re), 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(dk_i_l_lp_taps_im), ((u8 *)dk_i_l_lp_taps_im), 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_AMP_TH__A, 0x2, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } /* TODO check with IS */ rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_CONT__A, (ATV_TOP_CR_CONT_CR_P_L | ATV_TOP_CR_CONT_CR_D_L | ATV_TOP_CR_CONT_CR_I_L), 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_L, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_L | ATV_TOP_STD_VID_POL_L), 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_AM | SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_ENABLE | SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW), 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_LLP, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } ext_attr->phase_correction_bypass = false; ext_attr->atv_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_USER; @@ -12809,68 +12674,68 @@ trouble ? rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_LP, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_LO_INCR__A, 2225, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } /* TODO check with IS */ rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(dk_i_l_lp_taps_re), ((u8 *)dk_i_l_lp_taps_re), 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(dk_i_l_lp_taps_im), ((u8 *)dk_i_l_lp_taps_im), 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_AMP_TH__A, 0x2, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } /* TODO check with IS */ rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_CONT__A, (ATV_TOP_CR_CONT_CR_P_LP | ATV_TOP_CR_CONT_CR_D_LP | ATV_TOP_CR_CONT_CR_I_LP), 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_LP, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_LP | ATV_TOP_STD_VID_POL_LP), 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_AM | SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_ENABLE | SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW), 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_LLP, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } ext_attr->phase_correction_bypass = false; ext_attr->atv_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_USER; @@ -12885,30 +12750,30 @@ trouble ? if (!ext_attr->has_lna) { rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_AMUX__A, 0x01, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_STANDARD__A, 0x002, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_CLP_LEN__A, IQM_AF_CLP_LEN_ATV, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_CLP_TH__A, IQM_AF_CLP_TH_ATV, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_SNS_LEN__A, IQM_AF_SNS_LEN_ATV, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->atv_pre_saw_cfg)); if (rc != DRX_STS_OK) { @@ -12917,135 +12782,135 @@ trouble ? } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_AGC_IF__A, 10248, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } ext_attr->iqm_rc_rate_ofs = 0x00200000L; rc = DRXJ_DAP.write_reg32func(dev_addr, IQM_RC_RATE_OFS_LO__A, ext_attr->iqm_rc_rate_ofs, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RC_ADJ_SEL__A, IQM_RC_ADJ_SEL_B_OFF, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RC_STRETCH__A, IQM_RC_STRETCH_ATV, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_ACTIVE__A, IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_ON | IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_ON, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_ATV__M, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_SYMMETRIC__A, IQM_CF_SYMMETRIC_IM__M, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } /* default: SIF in standby */ rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_SYNC_SLICE__A, ATV_TOP_SYNC_SLICE_MN, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_MOD_ACCU__A, ATV_TOP_MOD_ACCU__PRE, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_SIF_GAIN__A, 0x080, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_FAGC_TH_RED__A, 10, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AAGC_CNT__A, 7, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_NAGC_KI_MIN__A, 0x0225, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_NAGC_KI_MAX__A, 0x0547, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_KI_CHANGE_TH__A, 20, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_LOCK__A, 0, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_DELAY__A, IQM_RT_DELAY__PRE, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_BPC_KI_MIN__A, 531, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_PAGC_KI_MIN__A, 1061, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_BP_REF_MIN__A, 100, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_BP_REF_MAX__A, 260, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_BP_LVL__A, 0, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AMS_MAX__A, 0, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AMS_MIN__A, 2047, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_GPIO__A, 0, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } /* Override reset values with current shadow settings */ @@ -13094,19 +12959,19 @@ trouble ? if (ext_attr->mfx == 0x03) { rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_ENABLE_IIR_WA__A, 0, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } } else { rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_ENABLE_IIR_WA__A, 1, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_IIR_CRIT__A, 225, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } } @@ -13154,11 +13019,10 @@ set_atv_channel(struct drx_demod_instance *demod, Program frequency shifter No need to account for mirroring on RF */ - if (channel->mirror == DRX_MIRROR_AUTO) { + if (channel->mirror == DRX_MIRROR_AUTO) ext_attr->mirror = DRX_MIRROR_NO; - } else { + else ext_attr->mirror = channel->mirror; - } rc = set_frequency(demod, channel, tuner_freq_offset); if (rc != DRX_STS_OK) { @@ -13238,10 +13102,8 @@ get_atv_channel(struct drx_demod_instance *demod, goto rw_error; } /* Signed 8 bit register => sign extension needed */ - if ((measured_offset & 0x0080) != 0) { - /* sign extension */ + if ((measured_offset & 0x0080) != 0) measured_offset |= 0xFF80; - } offset += (s32) (((s16) measured_offset) * 10); break; @@ -13257,10 +13119,8 @@ get_atv_channel(struct drx_demod_instance *demod, goto rw_error; } /* Signed 8 bit register => sign extension needed */ - if ((measured_offset & 0x0080) != 0) { - /* sign extension */ + if ((measured_offset & 0x0080) != 0) measured_offset |= 0xFF80; - } offset -= (s32) (((s16) measured_offset) * 10); } @@ -13376,17 +13236,17 @@ get_atv_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength) /* clipping */ if (digital_curr_gain >= digital_max_gain) - digital_curr_gain = (u16) digital_max_gain; + digital_curr_gain = (u16)digital_max_gain; if (digital_curr_gain <= digital_min_gain) - digital_curr_gain = (u16) digital_min_gain; + digital_curr_gain = (u16)digital_min_gain; if (if_curr_gain <= if_max_gain) - if_curr_gain = (u16) if_max_gain; + if_curr_gain = (u16)if_max_gain; if (if_curr_gain >= if_min_gain) - if_curr_gain = (u16) if_min_gain; + if_curr_gain = (u16)if_min_gain; if (rf_curr_gain <= rf_max_gain) - rf_curr_gain = (u16) rf_max_gain; + rf_curr_gain = (u16)rf_max_gain; if (rf_curr_gain >= rf_min_gain) - rf_curr_gain = (u16) rf_min_gain; + rf_curr_gain = (u16)rf_min_gain; /* TODO: use SCU_RAM_ATV_RAGC_HR__A to shift max and min in case of clipping at ADC */ @@ -13462,13 +13322,10 @@ atv_sig_quality(struct drx_demod_instance *demod, struct drx_sig_quality *sig_qu if (quality_indicator <= 0x80) { sig_quality->indicator = 80 + ((20 * (0x80 - quality_indicator)) / 0x80); - } else if (quality_indicator <= 0x700) { - sig_quality->indicator = 30 + - ((50 * (0x700 - quality_indicator)) / (0x700 - 0x81)); - } else { - sig_quality->indicator = - (30 * (0x7FF - quality_indicator)) / (0x7FF - 0x701); - } + } else if (quality_indicator <= 0x700) + sig_quality->indicator = 30 + ((50 * (0x700 - quality_indicator)) / (0x700 - 0x81)); + else + sig_quality->indicator = (30 * (0x7FF - quality_indicator)) / (0x7FF - 0x701); return DRX_STS_OK; rw_error: @@ -13579,9 +13436,8 @@ static int aud_get_modus(struct drx_demod_instance *demod, u16 *modus) u16 r_modus_hi = 0; u16 r_modus_lo = 0; - if (modus == NULL) { + if (modus == NULL) return DRX_STS_INVALID_ARG; - } dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -13641,9 +13497,8 @@ aud_ctrl_get_cfg_rds(struct drx_demod_instance *demod, struct drx_cfg_aud_rds *s addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; - if (status == NULL) { + if (status == NULL) return DRX_STS_INVALID_ARG; - } /* power up */ if (ext_attr->aud_data.audio_is_active == false) { @@ -13721,9 +13576,8 @@ aud_ctrl_get_carrier_detect_status(struct drx_demod_instance *demod, struct drx_ int rc; u16 r_data = 0; - if (status == NULL) { + if (status == NULL) return DRX_STS_INVALID_ARG; - } dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -13753,38 +13607,28 @@ aud_ctrl_get_carrier_detect_status(struct drx_demod_instance *demod, struct drx_ } /* carrier a detected */ - if ((r_data & AUD_DEM_RD_STATUS_STAT_CARR_A__M) == - AUD_DEM_RD_STATUS_STAT_CARR_A_DETECTED) { + if ((r_data & AUD_DEM_RD_STATUS_STAT_CARR_A__M) == AUD_DEM_RD_STATUS_STAT_CARR_A_DETECTED) status->carrier_a = true; - } /* carrier b detected */ - if ((r_data & AUD_DEM_RD_STATUS_STAT_CARR_B__M) == - AUD_DEM_RD_STATUS_STAT_CARR_B_DETECTED) { + if ((r_data & AUD_DEM_RD_STATUS_STAT_CARR_B__M) == AUD_DEM_RD_STATUS_STAT_CARR_B_DETECTED) status->carrier_b = true; - } /* nicam detected */ if ((r_data & AUD_DEM_RD_STATUS_STAT_NICAM__M) == AUD_DEM_RD_STATUS_STAT_NICAM_NICAM_DETECTED) { - if ((r_data & AUD_DEM_RD_STATUS_BAD_NICAM__M) == - AUD_DEM_RD_STATUS_BAD_NICAM_OK) { + if ((r_data & AUD_DEM_RD_STATUS_BAD_NICAM__M) == AUD_DEM_RD_STATUS_BAD_NICAM_OK) status->nicam_status = DRX_AUD_NICAM_DETECTED; - } else { + else status->nicam_status = DRX_AUD_NICAM_BAD; - } } /* audio mode bilingual or SAP detected */ - if ((r_data & AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__M) == - AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP_SAP) { + if ((r_data & AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__M) == AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP_SAP) status->sap = true; - } /* stereo detected */ - if ((r_data & AUD_DEM_RD_STATUS_STAT_STEREO__M) == - AUD_DEM_RD_STATUS_STAT_STEREO_STEREO) { + if ((r_data & AUD_DEM_RD_STATUS_STAT_STEREO__M) == AUD_DEM_RD_STATUS_STAT_STEREO_STEREO) status->stereo = true; - } return DRX_STS_OK; rw_error: @@ -13808,9 +13652,8 @@ aud_ctrl_get_status(struct drx_demod_instance *demod, struct drx_aud_status *sta int rc; u16 r_data = 0; - if (status == NULL) { + if (status == NULL) return DRX_STS_INVALID_ARG; - } dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -13864,9 +13707,8 @@ aud_ctrl_get_cfg_volume(struct drx_demod_instance *demod, struct drx_cfg_aud_vol u16 r_strength_left = 0; u16 r_strength_right = 0; - if (volume == NULL) { + if (volume == NULL) return DRX_STS_INVALID_ARG; - } dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -13896,12 +13738,10 @@ aud_ctrl_get_cfg_volume(struct drx_demod_instance *demod, struct drx_cfg_aud_vol volume->volume = ((r_volume & AUD_DSP_WR_VOLUME_VOL_MAIN__M) >> AUD_DSP_WR_VOLUME_VOL_MAIN__B) - AUD_VOLUME_ZERO_DB; - if (volume->volume < AUD_VOLUME_DB_MIN) { + if (volume->volume < AUD_VOLUME_DB_MIN) volume->volume = AUD_VOLUME_DB_MIN; - } - if (volume->volume > AUD_VOLUME_DB_MAX) { + if (volume->volume > AUD_VOLUME_DB_MAX) volume->volume = AUD_VOLUME_DB_MAX; - } } /* automatic volume control */ @@ -13911,8 +13751,7 @@ aud_ctrl_get_cfg_volume(struct drx_demod_instance *demod, struct drx_cfg_aud_vol goto rw_error; } - if ((r_avc & AUD_DSP_WR_AVC_AVC_ON__M) == AUD_DSP_WR_AVC_AVC_ON_OFF) - { + if ((r_avc & AUD_DSP_WR_AVC_AVC_ON__M) == AUD_DSP_WR_AVC_AVC_ON_OFF) { volume->avc_mode = DRX_AUD_AVC_OFF; } else { switch (r_avc & AUD_DSP_WR_AVC_AVC_DECAY__M) { @@ -14016,9 +13855,8 @@ aud_ctrl_set_cfg_volume(struct drx_demod_instance *demod, struct drx_cfg_aud_vol u16 w_volume = 0; u16 w_avc = 0; - if (volume == NULL) { + if (volume == NULL) return DRX_STS_INVALID_ARG; - } dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -14036,9 +13874,8 @@ aud_ctrl_set_cfg_volume(struct drx_demod_instance *demod, struct drx_cfg_aud_vol /* volume */ /* volume range from -60 to 12 (expressed in dB) */ if ((volume->volume < AUD_VOLUME_DB_MIN) || - (volume->volume > AUD_VOLUME_DB_MAX)) { + (volume->volume > AUD_VOLUME_DB_MAX)) return DRX_STS_INVALID_ARG; - } rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DSP_WR_VOLUME__A, &w_volume, 0); if (rc != DRX_STS_OK) { @@ -14048,15 +13885,10 @@ aud_ctrl_set_cfg_volume(struct drx_demod_instance *demod, struct drx_cfg_aud_vol /* clear the volume mask */ w_volume &= (u16) ~AUD_DSP_WR_VOLUME_VOL_MAIN__M; - if (volume->mute == true) { - /* mute */ - /* mute overrules volume */ - w_volume |= (u16) (0); - - } else { - w_volume |= (u16) ((volume->volume + AUD_VOLUME_ZERO_DB) << - AUD_DSP_WR_VOLUME_VOL_MAIN__B); - } + if (volume->mute == true) + w_volume |= (u16)(0); + else + w_volume |= (u16)((volume->volume + AUD_VOLUME_ZERO_DB) << AUD_DSP_WR_VOLUME_VOL_MAIN__B); rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DSP_WR_VOLUME__A, w_volume, 0); if (rc != DRX_STS_OK) { @@ -14133,9 +13965,8 @@ aud_ctrl_set_cfg_volume(struct drx_demod_instance *demod, struct drx_cfg_aud_vol } /* avc reference level */ - if (volume->avc_ref_level > AUD_MAX_AVC_REF_LEVEL) { + if (volume->avc_ref_level > AUD_MAX_AVC_REF_LEVEL) return DRX_STS_INVALID_ARG; - } w_avc &= (u16) ~AUD_DSP_WR_AVC_AVC_REF_LEV__M; w_avc |= (u16) (volume->avc_ref_level << AUD_DSP_WR_AVC_AVC_REF_LEV__B); @@ -14170,9 +14001,8 @@ aud_ctrl_get_cfg_output_i2s(struct drx_demod_instance *demod, struct drx_cfg_i2s u16 w_i2s_config = 0; u16 r_i2s_freq = 0; - if (output == NULL) { + if (output == NULL) return DRX_STS_INVALID_ARG; - } dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -14247,18 +14077,15 @@ aud_ctrl_get_cfg_output_i2s(struct drx_demod_instance *demod, struct drx_cfg_i2s } /* I2S output enabled */ - if ((w_i2s_config & AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__M) - == AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_ENABLE) { + if ((w_i2s_config & AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__M) == AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_ENABLE) output->output_enable = true; - } else { + else output->output_enable = false; - } if (r_i2s_freq > 0) { output->frequency = 6144UL * 48000 / r_i2s_freq; - if (output->word_length == DRX_I2S_WORDLENGTH_16) { + if (output->word_length == DRX_I2S_WORDLENGTH_16) output->frequency *= 2; - } } else { output->frequency = AUD_I2S_FREQUENCY_MAX; } @@ -14287,9 +14114,8 @@ aud_ctrl_set_cfg_output_i2s(struct drx_demod_instance *demod, struct drx_cfg_i2s u16 w_i2s_pads_data_ws = 0; u32 w_i2s_freq = 0; - if (output == NULL) { + if (output == NULL) return DRX_STS_INVALID_ARG; - } dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -14367,11 +14193,10 @@ aud_ctrl_set_cfg_output_i2s(struct drx_demod_instance *demod, struct drx_cfg_i2s /* I2S output enabled */ w_i2s_config &= (u16) ~AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__M; - if (output->output_enable == true) { + if (output->output_enable == true) w_i2s_config |= AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_ENABLE; - } else { + else w_i2s_config |= AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_DISABLE; - } /* I2S frequency @@ -14389,9 +14214,8 @@ aud_ctrl_set_cfg_output_i2s(struct drx_demod_instance *demod, struct drx_cfg_i2s w_i2s_freq = (6144UL * 48000UL) + (output->frequency >> 1); w_i2s_freq /= output->frequency; - if (output->word_length == DRX_I2S_WORDLENGTH_16) { + if (output->word_length == DRX_I2S_WORDLENGTH_16) w_i2s_freq *= 2; - } rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DEM_WR_I2S_CONFIG2__A, w_i2s_config, 0); if (rc != DRX_STS_OK) { @@ -14538,9 +14362,8 @@ aud_ctr_setl_cfg_auto_sound(struct drx_demod_instance *demod, u16 r_modus = 0; u16 w_modus = 0; - if (auto_sound == NULL) { + if (auto_sound == NULL) return DRX_STS_INVALID_ARG; - } dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -14616,9 +14439,8 @@ aud_ctrl_get_cfg_ass_thres(struct drx_demod_instance *demod, struct drx_cfg_aud_ u16 thres_btsc = 0; u16 thres_nicam = 0; - if (thres == NULL) { + if (thres == NULL) return DRX_STS_INVALID_ARG; - } dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -14672,9 +14494,8 @@ aud_ctrl_set_cfg_ass_thres(struct drx_demod_instance *demod, struct drx_cfg_aud_ struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; struct drxj_data *ext_attr = (struct drxj_data *) NULL; int rc; - if (thres == NULL) { + if (thres == NULL) return DRX_STS_INVALID_ARG; - } dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -14742,9 +14563,8 @@ aud_ctrl_get_cfg_carrier(struct drx_demod_instance *demod, struct drx_cfg_aud_ca u16 cm_thes_a = 0; u16 cm_thes_b = 0; - if (carriers == NULL) { + if (carriers == NULL) return DRX_STS_INVALID_ARG; - } dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -14872,18 +14692,15 @@ aud_ctrl_set_cfg_carrier(struct drx_demod_instance *demod, struct drx_cfg_aud_ca int rc; u16 w_modus = 0; u16 r_modus = 0; - u16 dco_a_hi = 0; u16 dco_a_lo = 0; u16 dco_b_hi = 0; u16 dco_b_lo = 0; - s32 valA = 0; s32 valB = 0; - if (carriers == NULL) { + if (carriers == NULL) return DRX_STS_INVALID_ARG; - } dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -15009,9 +14826,8 @@ aud_ctrl_get_cfg_mixer(struct drx_demod_instance *demod, struct drx_cfg_aud_mixe u16 src_i2s_matr = 0; u16 fm_matr = 0; - if (mixer == NULL) { + if (mixer == NULL) return DRX_STS_INVALID_ARG; - } dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -15116,9 +14932,8 @@ aud_ctrl_set_cfg_mixer(struct drx_demod_instance *demod, struct drx_cfg_aud_mixe u16 src_i2s_matr = 0; u16 fm_matr = 0; - if (mixer == NULL) { + if (mixer == NULL) return DRX_STS_INVALID_ARG; - } dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -15243,9 +15058,8 @@ aud_ctrl_set_cfg_av_sync(struct drx_demod_instance *demod, enum drx_cfg_aud_av_s int rc; u16 w_aud_vid_sync = 0; - if (av_sync == NULL) { + if (av_sync == NULL) return DRX_STS_INVALID_ARG; - } dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -15269,11 +15083,10 @@ aud_ctrl_set_cfg_av_sync(struct drx_demod_instance *demod, enum drx_cfg_aud_av_s w_aud_vid_sync &= (u16) ~AUD_DSP_WR_AV_SYNC_AV_ON__M; - if (*av_sync == DRX_AUD_AVSYNC_OFF) { + if (*av_sync == DRX_AUD_AVSYNC_OFF) w_aud_vid_sync |= AUD_DSP_WR_AV_SYNC_AV_ON_DISABLE; - } else { + else w_aud_vid_sync |= AUD_DSP_WR_AV_SYNC_AV_ON_ENABLE; - } w_aud_vid_sync &= (u16) ~AUD_DSP_WR_AV_SYNC_AV_STD_SEL__M; @@ -15320,9 +15133,8 @@ aud_ctrl_get_cfg_av_sync(struct drx_demod_instance *demod, enum drx_cfg_aud_av_s int rc; u16 w_aud_vid_sync = 0; - if (av_sync == NULL) { + if (av_sync == NULL) return DRX_STS_INVALID_ARG; - } dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -15423,9 +15235,8 @@ aud_ctrl_set_cfg_dev(struct drx_demod_instance *demod, enum drx_cfg_aud_deviatio u16 w_modus = 0; u16 r_modus = 0; - if (dev == NULL) { + if (dev == NULL) return DRX_STS_INVALID_ARG; - } ext_attr = (struct drxj_data *) demod->my_ext_attr; dev_addr = demod->my_i2c_dev_addr; @@ -15483,9 +15294,8 @@ aud_ctrl_get_cfg_prescale(struct drx_demod_instance *demod, struct drx_cfg_aud_p u16 r_max_fm_deviation = 0; u16 r_nicam_prescaler = 0; - if (presc == NULL) { + if (presc == NULL) return DRX_STS_INVALID_ARG; - } dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -15537,16 +15347,10 @@ aud_ctrl_get_cfg_prescale(struct drx_demod_instance *demod, struct drx_cfg_aud_p */ r_nicam_prescaler >>= 8; - if (r_nicam_prescaler <= 1) { + if (r_nicam_prescaler <= 1) presc->nicam_gain = -241; - } else { - - presc->nicam_gain = (s16) (((s32) - (log1_times100 - (10 * r_nicam_prescaler * - r_nicam_prescaler)) - (s32) - (log1_times100(10 * 16 * 16)))); - } + else + presc->nicam_gain = (s16)(((s32)(log1_times100(10 * r_nicam_prescaler * r_nicam_prescaler)) - (s32)(log1_times100(10 * 16 * 16)))); return DRX_STS_OK; rw_error: @@ -15569,9 +15373,8 @@ aud_ctrl_set_cfg_prescale(struct drx_demod_instance *demod, struct drx_cfg_aud_p u16 w_max_fm_deviation = 0; u16 nicam_prescaler; - if (presc == NULL) { + if (presc == NULL) return DRX_STS_INVALID_ARG; - } dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -15589,11 +15392,8 @@ aud_ctrl_set_cfg_prescale(struct drx_demod_instance *demod, struct drx_cfg_aud_p /* setting of max FM deviation */ w_max_fm_deviation = (u16) (frac(3600UL, presc->fm_deviation, 0)); w_max_fm_deviation <<= AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__B; - if (w_max_fm_deviation >= - AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_28_KHZ_FM_DEVIATION) { - w_max_fm_deviation = - AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_28_KHZ_FM_DEVIATION; - } + if (w_max_fm_deviation >= AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_28_KHZ_FM_DEVIATION) + w_max_fm_deviation = AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_28_KHZ_FM_DEVIATION; /* NICAM Prescaler */ if ((presc->nicam_gain >= -241) && (presc->nicam_gain <= 180)) { @@ -15618,9 +15418,8 @@ aud_ctrl_set_cfg_prescale(struct drx_demod_instance *demod, struct drx_cfg_aud_p ((d_b2lin_times100(presc->nicam_gain + 241UL) + 50UL) / 100UL); /* clip result */ - if (nicam_prescaler > 127) { + if (nicam_prescaler > 127) nicam_prescaler = 127; - } /* shift before writing to register */ nicam_prescaler <<= 8; @@ -15663,9 +15462,8 @@ static int aud_ctrl_beep(struct drx_demod_instance *demod, struct drx_aud_beep * u16 volume = 0; u32 frequency = 0; - if (beep == NULL) { + if (beep == NULL) return DRX_STS_INVALID_ARG; - } dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -15680,26 +15478,22 @@ static int aud_ctrl_beep(struct drx_demod_instance *demod, struct drx_aud_beep * ext_attr->aud_data.audio_is_active = true; } - if ((beep->volume > 0) || (beep->volume < -127)) { + if ((beep->volume > 0) || (beep->volume < -127)) return DRX_STS_INVALID_ARG; - } - if (beep->frequency > 3000) { + if (beep->frequency > 3000) return DRX_STS_INVALID_ARG; - } volume = (u16) beep->volume + 127; the_beep |= volume << AUD_DSP_WR_BEEPER_BEEP_VOLUME__B; frequency = ((u32) beep->frequency) * 23 / 500; - if (frequency > AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__M) { + if (frequency > AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__M) frequency = AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__M; - } the_beep |= (u16) frequency; - if (beep->mute == true) { + if (beep->mute == true) the_beep = 0; - } rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DSP_WR_BEEPER__A, the_beep, 0); if (rc != DRX_STS_OK) { @@ -15734,9 +15528,8 @@ aud_ctrl_set_standard(struct drx_demod_instance *demod, enum drx_aud_standard *s s16 volume_buffer = 0; u16 w_volume = 0; - if (standard == NULL) { + if (standard == NULL) return DRX_STS_INVALID_ARG; - } dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -15817,9 +15610,8 @@ aud_ctrl_set_standard(struct drx_demod_instance *demod, enum drx_aud_standard *s break; case DRX_AUD_STANDARD_BTSC: w_standard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_BTSC_STEREO; - if (ext_attr->aud_data.btsc_detect == DRX_BTSC_MONO_AND_SAP) { + if (ext_attr->aud_data.btsc_detect == DRX_BTSC_MONO_AND_SAP) w_standard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_BTSC_SAP; - } break; case DRX_AUD_STANDARD_A2: w_standard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_M_KOREA; @@ -15867,40 +15659,32 @@ aud_ctrl_set_standard(struct drx_demod_instance *demod, enum drx_aud_standard *s w_modus &= (u16) ~AUD_DEM_WR_MODUS_MOD_6_5MHZ__M; - if ((current_standard == DRX_STANDARD_PAL_SECAM_L) || - (current_standard == DRX_STANDARD_PAL_SECAM_LP)) { + if ((current_standard == DRX_STANDARD_PAL_SECAM_L) || (current_standard == DRX_STANDARD_PAL_SECAM_LP)) w_modus |= (AUD_DEM_WR_MODUS_MOD_6_5MHZ_SECAM); - } else { + else w_modus |= (AUD_DEM_WR_MODUS_MOD_6_5MHZ_D_K); - } w_modus &= (u16) ~AUD_DEM_WR_MODUS_MOD_4_5MHZ__M; - if (current_standard == DRX_STANDARD_NTSC) { + if (current_standard == DRX_STANDARD_NTSC) w_modus |= (AUD_DEM_WR_MODUS_MOD_4_5MHZ_M_BTSC); - - } else { /* non USA, ignore standard M to save time */ - + else w_modus |= (AUD_DEM_WR_MODUS_MOD_4_5MHZ_CHROMA); - } } w_modus &= (u16) ~AUD_DEM_WR_MODUS_MOD_FMRADIO__M; /* just get hardcoded deemphasis and activate here */ - if (ext_attr->aud_data.deemph == DRX_AUD_FM_DEEMPH_50US) { + if (ext_attr->aud_data.deemph == DRX_AUD_FM_DEEMPH_50US) w_modus |= (AUD_DEM_WR_MODUS_MOD_FMRADIO_EU_50U); - } else { + else w_modus |= (AUD_DEM_WR_MODUS_MOD_FMRADIO_US_75U); - } w_modus &= (u16) ~AUD_DEM_WR_MODUS_MOD_BTSC__M; - if (ext_attr->aud_data.btsc_detect == DRX_BTSC_STEREO) { + if (ext_attr->aud_data.btsc_detect == DRX_BTSC_STEREO) w_modus |= (AUD_DEM_WR_MODUS_MOD_BTSC_BTSC_STEREO); - } else { /* DRX_BTSC_MONO_AND_SAP */ - + else w_modus |= (AUD_DEM_WR_MODUS_MOD_BTSC_BTSC_SAP); - } if (w_modus != r_modus) { rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DEM_WR_MODUS__A, w_modus, 0); @@ -15955,9 +15739,8 @@ aud_ctrl_get_standard(struct drx_demod_instance *demod, enum drx_aud_standard *s int rc; u16 r_data = 0; - if (standard == NULL) { + if (standard == NULL) return DRX_STS_INVALID_ARG; - } ext_attr = (struct drxj_data *) demod->my_ext_attr; dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; @@ -16076,11 +15859,10 @@ fm_lock_status(struct drx_demod_instance *demod, enum drx_lock_status *lock_stat } /* locked if either primary or secondary carrier is detected */ - if ((status.carrier_a == true) || (status.carrier_b == true)) { + if ((status.carrier_a == true) || (status.carrier_b == true)) *lock_stat = DRX_LOCKED; - } else { + else *lock_stat = DRX_NOT_LOCKED; - } return DRX_STS_OK; @@ -16110,11 +15892,10 @@ fm_sig_quality(struct drx_demod_instance *demod, struct drx_sig_quality *sig_qua pr_err("error %d\n", rc); goto rw_error; } - if (lock_status == DRX_LOCKED) { + if (lock_status == DRX_LOCKED) sig_quality->indicator = 100; - } else { + else sig_quality->indicator = 0; - } return DRX_STS_OK; @@ -16177,11 +15958,10 @@ get_oob_lock_status(struct drx_demod_instance *demod, /* 0x80 DEMOD + OOB LOCKED (system lock) */ oob_lock_state = scu_cmd.result[1] & 0x00FF; - if (oob_lock_state & 0x0008) { + if (oob_lock_state & 0x0008) *oob_lock = DRXJ_OOB_SYNC_LOCK; - } else if ((oob_lock_state & 0x0002) && (oob_lock_state & 0x0001)) { + else if ((oob_lock_state & 0x0002) && (oob_lock_state & 0x0001)) *oob_lock = DRXJ_OOB_AGC_LOCK; - } } else { /* 0xC0 NEVER LOCKED (system will never be able to lock to the signal) */ *oob_lock = DRX_NEVER_LOCK; @@ -16230,8 +16010,8 @@ get_oob_symbol_rate_offset(struct i2c_device_addr *dev_addr, s32 *symbol_rate_of /* read data rate */ rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_ORX_RF_RX_DATA_RATE__A, &data, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } switch (data & SCU_RAM_ORX_RF_RX_DATA_RATE__M) { case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC: @@ -16254,8 +16034,8 @@ get_oob_symbol_rate_offset(struct i2c_device_addr *dev_addr, s32 *symbol_rate_of rc = DRXJ_DAP.read_reg16func(dev_addr, ORX_CON_CTI_DTI_R__A, &data, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } /* convert data to positive and keep information about sign */ if ((data & 0x8000) == 0x8000) { @@ -16313,9 +16093,8 @@ get_oob_freq_offset(struct drx_demod_instance *demod, s32 *freq_offset) u32 temp_freq_offset = 0; /* check arguments */ - if ((demod == NULL) || (freq_offset == NULL)) { + if ((demod == NULL) || (freq_offset == NULL)) return DRX_STS_INVALID_ARG; - } dev_addr = demod->my_i2c_dev_addr; common_attr = (struct drx_common_attr *) demod->my_common_attr; @@ -16614,27 +16393,10 @@ static int set_orx_nsu_aox(struct drx_demod_instance *demod, bool active) pr_err("error %d\n", rc); goto rw_error; } - if (!active) { - data &= ((~ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON) - & (~ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON) - & (~ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON) - & (~ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON) - & (~ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON) - & (~ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON) - & (~ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON) - & (~ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON) - ); - } else { /* active */ - - data |= (ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON - | ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON - | ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON - | ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON - | ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON - | ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON - | ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON - | ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON); - } + if (!active) + data &= ((~ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON)); + else + data |= (ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON); rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_NSU_AOX_STDBY_W__A, data, 0); if (rc != DRX_STS_OK) { pr_err("error %d\n", rc); @@ -16722,8 +16484,8 @@ static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_par } rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } ext_attr->oob_power_on = false; @@ -16754,8 +16516,8 @@ static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_par /*********/ rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB | SCU_RAM_COMMAND_CMD_DEMOD_STOP; @@ -16859,289 +16621,289 @@ static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_par rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } /* Write magic word to enable pdr reg write */ rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_OOB_CRX_CFG__A, OOB_CRX_DRIVE_STRENGTH << SIO_PDR_OOB_CRX_CFG_DRIVE__B | 0x03 << SIO_PDR_OOB_CRX_CFG_MODE__B, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_OOB_DRX_CFG__A, OOB_DRX_DRIVE_STRENGTH << SIO_PDR_OOB_DRX_CFG_DRIVE__B | 0x03 << SIO_PDR_OOB_DRX_CFG_MODE__B, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } /* Write magic word to disable pdr reg write */ rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_TOP_COMM_KEY__A, 0, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_FWP_AAG_LEN_W__A, 16000, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_FWP_AAG_THR_W__A, 40, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } /* ddc */ rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_DDC_OFO_SET_W__A, ORX_DDC_OFO_SET_W__PRE, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } /* nsu */ rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_NSU_AOX_LOPOW_W__A, ext_attr->oob_lo_pow, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } /* initialization for target mode */ rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_TARGET_MODE__A, SCU_RAM_ORX_TARGET_MODE_2048KBPS_SQRT, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_FREQ_GAIN_CORR__A, SCU_RAM_ORX_FREQ_GAIN_CORR_2048KBPS, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } /* Reset bits for timing and freq. recovery */ rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_RST_CPH__A, 0x0001, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_RST_CTI__A, 0x0002, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_RST_KRN__A, 0x0004, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_RST_KRP__A, 0x0008, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } /* AGN_LOCK = {2048>>3, -2048, 8, -8, 0, 1}; */ rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_AGN_LOCK_TH__A, 2048 >> 3, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_AGN_LOCK_TOTH__A, (u16)(-2048), 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_AGN_ONLOCK_TTH__A, 8, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_AGN_UNLOCK_TTH__A, (u16)(-8), 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_AGN_LOCK_MASK__A, 1, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } /* DGN_LOCK = {10, -2048, 8, -8, 0, 1<<1}; */ rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_DGN_LOCK_TH__A, 10, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_DGN_LOCK_TOTH__A, (u16)(-2048), 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_DGN_ONLOCK_TTH__A, 8, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_DGN_UNLOCK_TTH__A, (u16)(-8), 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_DGN_LOCK_MASK__A, 1 << 1, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } /* FRQ_LOCK = {15,-2048, 8, -8, 0, 1<<2}; */ rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TH__A, 17, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TOTH__A, (u16)(-2048), 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_FRQ_ONLOCK_TTH__A, 8, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_FRQ_UNLOCK_TTH__A, (u16)(-8), 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_FRQ_LOCK_MASK__A, 1 << 2, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } /* PHA_LOCK = {5000, -2048, 8, -8, 0, 1<<3}; */ rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_PHA_LOCK_TH__A, 3000, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_PHA_LOCK_TOTH__A, (u16)(-2048), 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_PHA_ONLOCK_TTH__A, 8, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_PHA_UNLOCK_TTH__A, (u16)(-8), 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_PHA_LOCK_MASK__A, 1 << 3, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } /* TIM_LOCK = {300, -2048, 8, -8, 0, 1<<4}; */ rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_TIM_LOCK_TH__A, 400, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_TIM_LOCK_TOTH__A, (u16)(-2048), 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_TIM_ONLOCK_TTH__A, 8, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_TIM_UNLOCK_TTH__A, (u16)(-8), 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_TIM_LOCK_MASK__A, 1 << 4, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } /* EQU_LOCK = {20, -2048, 8, -8, 0, 1<<5}; */ rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_EQU_LOCK_TH__A, 20, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_EQU_LOCK_TOTH__A, (u16)(-2048), 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_EQU_ONLOCK_TTH__A, 4, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_EQU_UNLOCK_TTH__A, (u16)(-4), 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_EQU_LOCK_MASK__A, 1 << 5, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } /* PRE-Filter coefficients (PFI) */ rc = DRXJ_DAP.write_block_func(dev_addr, ORX_FWP_PFI_A_W__A, sizeof(pfi_coeffs[mode_index]), ((u8 *)pfi_coeffs[mode_index]), 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_TOP_MDE_W__A, mode_index, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } /* NYQUIST-Filter coefficients (NYQ) */ for (i = 0; i < (NYQFILTERLEN + 1) / 2; i++) { rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_FWP_NYQ_ADR_W__A, i, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_FWP_NYQ_COF_RW__A, nyquist_coeffs[mode_index][i], 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } } rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_FWP_NYQ_ADR_W__A, 31, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_ACTIVE, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } - /*********/ + /*********/ /* Start */ - /*********/ + /*********/ scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB | SCU_RAM_COMMAND_CMD_DEMOD_START; scu_cmd.parameter_len = 0; @@ -17160,8 +16922,8 @@ static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_par } rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_NSU_AOX_STHR_W__A, ext_attr->oob_pre_saw, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } ext_attr->oob_power_on = true; @@ -17192,37 +16954,36 @@ ctrl_get_oob(struct drx_demod_instance *demod, struct drxoob_status *oob_status) ext_attr = (struct drxj_data *) demod->my_ext_attr; /* check arguments */ - if (oob_status == NULL) { + if (oob_status == NULL) return DRX_STS_INVALID_ARG; - } if (!ext_attr->oob_power_on) return DRX_STS_ERROR; rc = DRXJ_DAP.read_reg16func(dev_addr, ORX_DDC_OFO_SET_W__A, &data, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.read_reg16func(dev_addr, ORX_NSU_TUN_RFGAIN_W__A, &data, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.read_reg16func(dev_addr, ORX_FWP_AAG_THR_W__A, &data, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_ORX_DGN_KI__A, &data, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = DRXJ_DAP.read_reg16func(dev_addr, ORX_FWP_SRC_DGN_W__A, &data, 0); if (rc != DRX_STS_OK) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d\n", rc); + goto rw_error; } rc = get_oob_lock_status(demod, dev_addr, &oob_status->lock); @@ -17266,9 +17027,9 @@ ctrl_set_cfg_oob_pre_saw(struct drx_demod_instance *demod, u16 *cfg_data) struct drxj_data *ext_attr = NULL; int rc; - if (cfg_data == NULL) { + if (cfg_data == NULL) return DRX_STS_INVALID_ARG; - } + dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -17296,9 +17057,9 @@ ctrl_get_cfg_oob_pre_saw(struct drx_demod_instance *demod, u16 *cfg_data) { struct drxj_data *ext_attr = NULL; - if (cfg_data == NULL) { + if (cfg_data == NULL) return DRX_STS_INVALID_ARG; - } + ext_attr = (struct drxj_data *) demod->my_ext_attr; *cfg_data = ext_attr->oob_pre_saw; @@ -17320,9 +17081,9 @@ ctrl_set_cfg_oob_lo_power(struct drx_demod_instance *demod, enum drxj_cfg_oob_lo struct drxj_data *ext_attr = NULL; int rc; - if (cfg_data == NULL) { + if (cfg_data == NULL) return DRX_STS_INVALID_ARG; - } + dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -17349,9 +17110,9 @@ ctrl_get_cfg_oob_lo_power(struct drx_demod_instance *demod, enum drxj_cfg_oob_lo { struct drxj_data *ext_attr = NULL; - if (cfg_data == NULL) { + if (cfg_data == NULL) return DRX_STS_INVALID_ARG; - } + ext_attr = (struct drxj_data *) demod->my_ext_attr; *cfg_data = ext_attr->oob_lo_pow; @@ -17402,9 +17163,8 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) int bandwidth = 0; #endif /*== check arguments ======================================================*/ - if ((demod == NULL) || (channel == NULL)) { + if ((demod == NULL) || (channel == NULL)) return DRX_STS_INVALID_ARG; - } common_attr = (struct drx_common_attr *) demod->my_common_attr; dev_addr = demod->my_i2c_dev_addr; @@ -17515,9 +17275,8 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) bandwidth_temp = channel->symbolrate * bw_rolloff_factor; bandwidth = bandwidth_temp / 100; - if ((bandwidth_temp % 100) >= 50) { + if ((bandwidth_temp % 100) >= 50) bandwidth++; - } if (bandwidth <= 6100000) { channel->bandwidth = DRX_BANDWIDTH_6MHZ; @@ -17709,11 +17468,10 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) /*== Setup demod for specific standard ====================================*/ switch (standard) { case DRX_STANDARD_8VSB: - if (channel->mirror == DRX_MIRROR_AUTO) { + if (channel->mirror == DRX_MIRROR_AUTO) ext_attr->mirror = DRX_MIRROR_NO; - } else { + else ext_attr->mirror = channel->mirror; - } rc = set_vsb(demod); if (rc != DRX_STS_OK) { pr_err("error %d\n", rc); @@ -17733,11 +17491,10 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */ case DRX_STANDARD_PAL_SECAM_LP: - if (channel->mirror == DRX_MIRROR_AUTO) { + if (channel->mirror == DRX_MIRROR_AUTO) ext_attr->mirror = DRX_MIRROR_NO; - } else { + else ext_attr->mirror = channel->mirror; - } rc = set_atv_channel(demod, tuner_freq_offset, channel, standard); if (rc != DRX_STS_OK) { pr_err("error %d\n", rc); @@ -17832,9 +17589,8 @@ ctrl_get_channel(struct drx_demod_instance *demod, struct drx_channel *channel) #endif /* check arguments */ - if ((demod == NULL) || (channel == NULL)) { + if ((demod == NULL) || (channel == NULL)) return DRX_STS_INVALID_ARG; - } dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -17878,9 +17634,8 @@ ctrl_get_channel(struct drx_demod_instance *demod, struct drx_channel *channel) } /* Handle sound carrier offset in RF domain */ - if (standard == DRX_STANDARD_FM) { + if (standard == DRX_STANDARD_FM) channel->frequency -= DRXJ_FM_CARRIER_FREQ_OFFSET; - } } else { intermediate_freq = common_attr->intermediate_freq; } @@ -17935,17 +17690,15 @@ ctrl_get_channel(struct drx_demod_instance *demod, struct drx_channel *channel) u32 roll_off = 113; /* default annex C */ - if (standard == DRX_STANDARD_ITU_A) { + if (standard == DRX_STANDARD_ITU_A) roll_off = 115; - } bandwidth_temp = channel->symbolrate * roll_off; bandwidth = bandwidth_temp / 100; - if ((bandwidth_temp % 100) >= 50) { + if ((bandwidth_temp % 100) >= 50) bandwidth++; - } if (bandwidth <= 6000000) { channel->bandwidth = @@ -17961,13 +17714,7 @@ ctrl_get_channel(struct drx_demod_instance *demod, struct drx_channel *channel) } /* if (standard == DRX_STANDARD_ITU_B) */ { - struct drxjscu_cmd cmd_scu = - { /* command */ 0, - /* parameter_len */ 0, - /* result_len */ 0, - /* parameter */ NULL, - /* result */ NULL - }; + struct drxjscu_cmd cmd_scu = { 0, 0, NULL, NULL }; u16 cmd_result[3] = { 0, 0, 0 }; cmd_scu.command = @@ -18037,9 +17784,8 @@ ctrl_get_channel(struct drx_demod_instance *demod, struct drx_channel *channel) return DRX_STS_ERROR; } /* switch ( standard ) */ - if (lock_status == DRX_LOCKED) { + if (lock_status == DRX_LOCKED) channel->mirror = ext_attr->mirror; - } } /* if ( lock_status == DRX_LOCKED ) */ return DRX_STS_OK; @@ -18059,18 +17805,13 @@ mer2indicator(u16 mer, u16 min_mer, u16 threshold_mer, u16 max_mer) if (mer < min_mer) { indicator = 0; } else if (mer < threshold_mer) { - if ((threshold_mer - min_mer) != 0) { - indicator = - 25 * (mer - min_mer) / (threshold_mer - min_mer); - } + if ((threshold_mer - min_mer) != 0) + indicator = 25 * (mer - min_mer) / (threshold_mer - min_mer); } else if (mer < max_mer) { - if ((max_mer - threshold_mer) != 0) { - indicator = - 25 + 75 * (mer - threshold_mer) / (max_mer - - threshold_mer); - } else { + if ((max_mer - threshold_mer) != 0) + indicator = 25 + 75 * (mer - threshold_mer) / (max_mer - threshold_mer); + else indicator = 25; - } } else { indicator = 100; } @@ -18102,9 +17843,8 @@ ctrl_sig_quality(struct drx_demod_instance *demod, struct drx_sig_quality *sig_q u16 threshold_mer = 0; /* Check arguments */ - if ((sig_quality == NULL) || (demod == NULL)) { + if ((sig_quality == NULL) || (demod == NULL)) return DRX_STS_INVALID_ARG; - } ext_attr = (struct drxj_data *) demod->my_ext_attr; standard = ext_attr->standard; @@ -18274,9 +18014,8 @@ ctrl_lock_status(struct drx_demod_instance *demod, enum drx_lock_status *lock_st u16 demod_lock = SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_DEMOD_LOCKED; /* check arguments */ - if ((demod == NULL) || (lock_stat == NULL)) { + if ((demod == NULL) || (lock_stat == NULL)) return DRX_STS_INVALID_ARG; - } dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -18367,9 +18106,8 @@ ctrl_constel(struct drx_demod_instance *demod, struct drx_complex *complex_nr) /**< active standard */ /* check arguments */ - if ((demod == NULL) || (complex_nr == NULL)) { + if ((demod == NULL) || (complex_nr == NULL)) return DRX_STS_INVALID_ARG; - } /* read device info */ standard = ((struct drxj_data *) demod->my_ext_attr)->standard; @@ -18424,9 +18162,8 @@ ctrl_set_standard(struct drx_demod_instance *demod, enum drx_standard *standard) enum drx_standard prev_standard; /* check arguments */ - if ((standard == NULL) || (demod == NULL)) { + if ((standard == NULL) || (demod == NULL)) return DRX_STS_INVALID_ARG; - } ext_attr = (struct drxj_data *) demod->my_ext_attr; prev_standard = ext_attr->standard; @@ -18494,7 +18231,7 @@ ctrl_set_standard(struct drx_demod_instance *demod, enum drx_standard *standard) pr_err("error %d\n", rc); goto rw_error; } - }while (0); + } while (0); break; #endif case DRX_STANDARD_8VSB: @@ -18556,10 +18293,10 @@ ctrl_get_standard(struct drx_demod_instance *demod, enum drx_standard *standard) ext_attr = (struct drxj_data *) demod->my_ext_attr; /* check arguments */ - if (standard == NULL) { + if (standard == NULL) return DRX_STS_INVALID_ARG; - } - (*standard) = ext_attr->standard; + + *standard = ext_attr->standard; do { u16 dummy; rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SCU_RAM_VERSION_HI__A, &dummy, 0); @@ -18567,7 +18304,7 @@ ctrl_get_standard(struct drx_demod_instance *demod, enum drx_standard *standard) pr_err("error %d\n", rc); goto rw_error; } - }while (0); + } while (0); return DRX_STS_OK; rw_error: @@ -18649,14 +18386,12 @@ ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode) dev_addr = demod->my_i2c_dev_addr; /* Check arguments */ - if (mode == NULL) { + if (mode == NULL) return DRX_STS_INVALID_ARG; - } /* If already in requested power mode, do nothing */ - if (common_attr->current_power_mode == *mode) { + if (common_attr->current_power_mode == *mode) return DRX_STS_OK; - } switch (*mode) { case DRX_POWER_UP: @@ -18814,9 +18549,8 @@ ctrl_version(struct drx_demod_instance *demod, struct drx_version_list **version u16 mfx = 0; u16 bid = 0; u16 key = 0; - - static char ucode_name[] = "Microcode"; - static char device_name[] = "Device"; + static const char ucode_name[] = "Microcode"; + static const char device_name[] = "Device"; dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -18932,22 +18666,20 @@ ctrl_version(struct drx_demod_instance *demod, struct drx_version_list **version subtype = (u16) ((jtag >> 12) & 0xFF); mfx = (u16) (jtag >> 29); ext_attr->v_version[1].v_minor = 1; - if (mfx == 0x03) { + if (mfx == 0x03) ext_attr->v_version[1].v_patch = mfx + 2; - } else { + else ext_attr->v_version[1].v_patch = mfx + 1; - } ext_attr->v_version[1].v_string[6] = ((char)(subtype & 0xF)) + '0'; ext_attr->v_version[1].v_major = (subtype & 0x0F); subtype >>= 4; ext_attr->v_version[1].v_string[5] = ((char)(subtype & 0xF)) + '0'; ext_attr->v_version[1].v_major += 10 * subtype; ext_attr->v_version[1].v_string[9] = 'A'; - if (mfx == 0x03) { + if (mfx == 0x03) ext_attr->v_version[1].v_string[10] = ((char)(mfx & 0xF)) + '2'; - } else { + else ext_attr->v_version[1].v_string[10] = ((char)(mfx & 0xF)) + '1'; - } ext_attr->v_list_elements[1].version = &(ext_attr->v_version[1]); ext_attr->v_list_elements[1].next = (struct drx_version_list *) (NULL); @@ -19060,7 +18792,7 @@ static int ctrl_probe_device(struct drx_demod_instance *demod) pr_err("error %d\n", rc); goto rw_error; } - }while (0); + } while (0); } return ret_status; @@ -19083,9 +18815,9 @@ rw_error: */ bool is_mc_block_audio(u32 addr) { - if ((addr == AUD_XFP_PRAM_4K__A) || (addr == AUD_XDFP_PRAM_4K__A)) { + if ((addr == AUD_XFP_PRAM_4K__A) || (addr == AUD_XDFP_PRAM_4K__A)) return true; - } + return false; } @@ -19203,16 +18935,10 @@ ctrl_u_code_upload(struct drx_demod_instance *demod, curr_ptr = mc_data; while (bytes_left_to_compare != 0) { - if (bytes_left_to_compare > - ((u32) - DRXJ_UCODE_MAX_BUF_SIZE)) { - bytes_to_compare = - ((u32) - DRXJ_UCODE_MAX_BUF_SIZE); - } else { - bytes_to_compare = - bytes_left_to_compare; - } + if (bytes_left_to_compare > ((u32)DRXJ_UCODE_MAX_BUF_SIZE)) + bytes_to_compare = ((u32)DRXJ_UCODE_MAX_BUF_SIZE); + else + bytes_to_compare = bytes_left_to_compare; if (demod->my_access_funct-> read_block_func(dev_addr, @@ -19231,9 +18957,8 @@ ctrl_u_code_upload(struct drx_demod_instance *demod, mc_data_buffer, bytes_to_compare); - if (result != 0) { + if (result != 0) return DRX_STS_ERROR; - } curr_addr += ((dr_xaddr_t) @@ -19259,9 +18984,8 @@ ctrl_u_code_upload(struct drx_demod_instance *demod, mc_data += mc_block_nr_bytes; } /* for( i = 0 ; iflag_aud_mc_uploaded = false; - } return DRX_STS_OK; } @@ -19291,9 +19015,8 @@ ctrl_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength) int rc; /* Check arguments */ - if ((sig_strength == NULL) || (demod == NULL)) { + if ((sig_strength == NULL) || (demod == NULL)) return DRX_STS_INVALID_ARG; - } ext_attr = (struct drxj_data *) demod->my_ext_attr; standard = ext_attr->standard; @@ -19361,9 +19084,9 @@ ctrl_get_cfg_oob_misc(struct drx_demod_instance *demod, struct drxj_cfg_oob_misc u16 digital_agc_exp = 0U; /* check arguments */ - if (misc == NULL) { + if (misc == NULL) return DRX_STS_INVALID_ARG; - } + dev_addr = demod->my_i2c_dev_addr; /* TODO */ @@ -19429,9 +19152,9 @@ ctrl_get_cfg_vsb_misc(struct drx_demod_instance *demod, struct drxj_cfg_vsb_misc int rc; /* check arguments */ - if (misc == NULL) { + if (misc == NULL) return DRX_STS_INVALID_ARG; - } + dev_addr = demod->my_i2c_dev_addr; rc = get_vsb_symb_err(dev_addr, &misc->symb_error); @@ -19462,9 +19185,8 @@ static int ctrl_set_cfg_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings) { /* check arguments */ - if (agc_settings == NULL) { + if (agc_settings == NULL) return DRX_STS_INVALID_ARG; - } switch (agc_settings->ctrl_mode) { case DRX_AGC_CTRL_AUTO: /* fallthrough */ @@ -19518,9 +19240,8 @@ static int ctrl_get_cfg_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings) { /* check arguments */ - if (agc_settings == NULL) { + if (agc_settings == NULL) return DRX_STS_INVALID_ARG; - } /* Distpatch */ switch (agc_settings->standard) { @@ -19565,9 +19286,8 @@ static int ctrl_set_cfg_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings) { /* check arguments */ - if (agc_settings == NULL) { + if (agc_settings == NULL) return DRX_STS_INVALID_ARG; - } switch (agc_settings->ctrl_mode) { case DRX_AGC_CTRL_AUTO: /* fallthrough */ @@ -19621,9 +19341,8 @@ static int ctrl_get_cfg_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings) { /* check arguments */ - if (agc_settings == NULL) { + if (agc_settings == NULL) return DRX_STS_INVALID_ARG; - } /* Distpatch */ switch (agc_settings->standard) { @@ -19677,9 +19396,8 @@ ctrl_get_cfg_agc_internal(struct drx_demod_instance *demod, u16 *agc_internal) u16 iqm_cf_gain = 0; /* check arguments */ - if (agc_internal == NULL) { + if (agc_internal == NULL) return DRX_STS_INVALID_ARG; - } dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -19847,9 +19565,8 @@ ctrl_set_cfg_afe_gain(struct drx_demod_instance *demod, struct drxj_cfg_afe_gain u8 gain = 0; /* check arguments */ - if (afe_gain == NULL) { + if (afe_gain == NULL) return DRX_STS_INVALID_ARG; - } dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -19878,8 +19595,7 @@ ctrl_set_cfg_afe_gain(struct drx_demod_instance *demod, struct drxj_cfg_afe_gain gain = (afe_gain->gain - 140 + 6) / 13; /* Only if standard is currently active */ - if (ext_attr->standard == afe_gain->standard){ - + if (ext_attr->standard == afe_gain->standard) { rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_PGA_GAIN__A, gain, 0); if (rc != DRX_STS_OK) { pr_err("error %d\n", rc); @@ -20025,9 +19741,8 @@ ctrl_get_fec_meas_seq_count(struct drx_demod_instance *demod, u16 *fec_meas_seq_ { int rc; /* check arguments */ - if (fec_meas_seq_count == NULL) { + if (fec_meas_seq_count == NULL) return DRX_STS_INVALID_ARG; - } rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, fec_meas_seq_count, 0); if (rc != DRX_STS_OK) { @@ -20057,9 +19772,8 @@ static int ctrl_get_accum_cr_rs_cw_err(struct drx_demod_instance *demod, u32 *accum_cr_rs_cw_err) { int rc; - if (accum_cr_rs_cw_err == NULL) { + if (accum_cr_rs_cw_err == NULL) return DRX_STS_INVALID_ARG; - } rc = DRXJ_DAP.read_reg32func(demod->my_i2c_dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, accum_cr_rs_cw_err, 0); if (rc != DRX_STS_OK) { @@ -20094,7 +19808,7 @@ static int ctrl_set_cfg(struct drx_demod_instance *demod, struct drx_cfg *config pr_err("error %d\n", rc); goto rw_error; } - }while (0); + } while (0); switch (config->cfg_type) { case DRX_CFG_MPEG_OUTPUT: return ctrl_set_cfg_mpeg_output(demod, @@ -20210,7 +19924,7 @@ static int ctrl_get_cfg(struct drx_demod_instance *demod, struct drx_cfg *config pr_err("error %d\n", rc); goto rw_error; } - }while (0); + } while (0); switch (config->cfg_type) { case DRX_CFG_MPEG_OUTPUT: -- cgit v1.1 From 9482354f4a17b8eb2cdc055f6de0386237a3abd2 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Fri, 17 Jan 2014 10:18:16 -0300 Subject: [media] drx-j: Use the Linux error codes Instead of defining its own set of error codes, use the linux native ones. Please note that this patch made a "stupid" error code mapping, just replacing the codes with the closest one. In special, -EIO is being used on several places. I'm pretty sure this could be better assigned, but a change like that would require lots o time and efforts, without much benefit. So lets do adjstments at the error codes latter, when we have more time. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h | 14 +- drivers/media/dvb-frontends/drx39xyj/drx39xxj.c | 26 +- .../media/dvb-frontends/drx39xyj/drx39xxj_dummy.c | 12 +- .../media/dvb-frontends/drx39xyj/drx_dap_fasi.c | 66 +- drivers/media/dvb-frontends/drx39xyj/drx_driver.c | 239 +- drivers/media/dvb-frontends/drx39xyj/drx_driver.h | 37 +- drivers/media/dvb-frontends/drx39xyj/drxj.c | 3868 ++++++++++---------- 7 files changed, 2122 insertions(+), 2140 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h b/drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h index 80d7b20..5b5421f 100644 --- a/drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h +++ b/drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h @@ -71,8 +71,8 @@ Exported FUNCTIONS * \fn drxbsp_i2c_init() * \brief Initialize I2C communication module. * \return drx_status_t Return status. -* \retval DRX_STS_OK Initialization successful. -* \retval DRX_STS_ERROR Initialization failed. +* \retval 0 Initialization successful. +* \retval -EIO Initialization failed. */ drx_status_t drxbsp_i2c_init(void); @@ -80,8 +80,8 @@ Exported FUNCTIONS * \fn drxbsp_i2c_term() * \brief Terminate I2C communication module. * \return drx_status_t Return status. -* \retval DRX_STS_OK Termination successful. -* \retval DRX_STS_ERROR Termination failed. +* \retval 0 Termination successful. +* \retval -EIO Termination failed. */ drx_status_t drxbsp_i2c_term(void); @@ -100,9 +100,9 @@ Exported FUNCTIONS * \param r_count The number of bytes to read * \param r_data The array to read the data from * \return drx_status_t Return status. -* \retval DRX_STS_OK Succes. -* \retval DRX_STS_ERROR Failure. -* \retval DRX_STS_INVALID_ARG Parameter 'wcount' is not zero but parameter +* \retval 0 Succes. +* \retval -EIO Failure. +* \retval -EINVAL Parameter 'wcount' is not zero but parameter * 'wdata' contains NULL. * Idem for 'rcount' and 'rdata'. * Both w_dev_addr and r_dev_addr are NULL. diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c index 0d2ec99..6db009e 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c @@ -43,7 +43,7 @@ static int drx39xxj_set_powerstate(struct dvb_frontend *fe, int enable) power_mode = DRX_POWER_DOWN; result = drx_ctrl(demod, DRX_CTRL_POWER_MODE, &power_mode); - if (result != DRX_STS_OK) { + if (result != 0) { printk(KERN_ERR "Power state change failed\n"); return 0; } @@ -62,7 +62,7 @@ static int drx39xxj_read_status(struct dvb_frontend *fe, fe_status_t *status) *status = 0; result = drx_ctrl(demod, DRX_CTRL_LOCK_STATUS, &lock_status); - if (result != DRX_STS_OK) { + if (result != 0) { printk(KERN_ERR "drx39xxj: could not get lock status!\n"); *status = 0; } @@ -107,7 +107,7 @@ static int drx39xxj_read_ber(struct dvb_frontend *fe, u32 *ber) struct drx_sig_quality sig_quality; result = drx_ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); - if (result != DRX_STS_OK) { + if (result != 0) { printk(KERN_ERR "drx39xxj: could not get ber!\n"); *ber = 0; return 0; @@ -126,7 +126,7 @@ static int drx39xxj_read_signal_strength(struct dvb_frontend *fe, struct drx_sig_quality sig_quality; result = drx_ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); - if (result != DRX_STS_OK) { + if (result != 0) { printk(KERN_ERR "drx39xxj: could not get signal strength!\n"); *strength = 0; return 0; @@ -145,7 +145,7 @@ static int drx39xxj_read_snr(struct dvb_frontend *fe, u16 *snr) struct drx_sig_quality sig_quality; result = drx_ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); - if (result != DRX_STS_OK) { + if (result != 0) { printk(KERN_ERR "drx39xxj: could not read snr!\n"); *snr = 0; return 0; @@ -163,7 +163,7 @@ static int drx39xxj_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) struct drx_sig_quality sig_quality; result = drx_ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); - if (result != DRX_STS_OK) { + if (result != 0) { printk(KERN_ERR "drx39xxj: could not get uc blocks!\n"); *ucblocks = 0; return 0; @@ -217,7 +217,7 @@ static int drx39xxj_set_frontend(struct dvb_frontend *fe) if (standard != state->current_standard || state->powered_up == 0) { /* Set the standard (will be powered up if necessary */ result = drx_ctrl(demod, DRX_CTRL_SET_STANDARD, &standard); - if (result != DRX_STS_OK) { + if (result != 0) { printk(KERN_ERR "Failed to set standard! result=%02x\n", result); return -EINVAL; @@ -234,7 +234,7 @@ static int drx39xxj_set_frontend(struct dvb_frontend *fe) /* program channel */ result = drx_ctrl(demod, DRX_CTRL_SET_CHANNEL, &channel); - if (result != DRX_STS_OK) { + if (result != 0) { printk(KERN_ERR "Failed to set channel!\n"); return -EINVAL; } @@ -242,7 +242,7 @@ static int drx39xxj_set_frontend(struct dvb_frontend *fe) uio_data.uio = DRX_UIO1; uio_data.value = false; result = drx_ctrl(demod, DRX_CTRL_UIO_WRITE, &uio_data); - if (result != DRX_STS_OK) { + if (result != 0) { printk(KERN_ERR "Failed to disable LNA!\n"); return 0; } @@ -288,7 +288,7 @@ static int drx39xxj_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) } result = drx_ctrl(demod, DRX_CTRL_I2C_BRIDGE, &i2c_gate_state); - if (result != DRX_STS_OK) { + if (result != 0) { printk(KERN_ERR "drx39xxj: could not open i2c gate [%d]\n", result); dump_stack(); @@ -382,7 +382,7 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) demod->my_tuner = NULL; result = drx_open(demod); - if (result != DRX_STS_OK) { + if (result != 0) { printk(KERN_ERR "DRX open failed! Aborting\n"); kfree(state); return NULL; @@ -393,7 +393,7 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) uio_cfg.mode = DRX_UIO_MODE_READWRITE; /* Configure user-I/O #3: enable read/write */ result = drx_ctrl(demod, DRX_CTRL_UIO_CFG, &uio_cfg); - if (result != DRX_STS_OK) { + if (result != 0) { printk(KERN_ERR "Failed to setup LNA GPIO!\n"); return NULL; } @@ -401,7 +401,7 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) uio_data.uio = DRX_UIO1; uio_data.value = false; result = drx_ctrl(demod, DRX_CTRL_UIO_WRITE, &uio_data); - if (result != DRX_STS_OK) { + if (result != 0) { printk(KERN_ERR "Failed to disable LNA!\n"); return NULL; } diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c b/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c index 448558e..8540774 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c @@ -13,19 +13,19 @@ /* Dummy function to satisfy drxj.c */ int drxbsp_tuner_open(struct tuner_instance *tuner) { - return DRX_STS_OK; + return 0; } int drxbsp_tuner_close(struct tuner_instance *tuner) { - return DRX_STS_OK; + return 0; } int drxbsp_tuner_set_frequency(struct tuner_instance *tuner, u32 mode, s32 center_frequency) { - return DRX_STS_OK; + return 0; } int @@ -34,13 +34,13 @@ drxbsp_tuner_get_frequency(struct tuner_instance *tuner, s32 *r_ffrequency, s32 *i_ffrequency) { - return DRX_STS_OK; + return 0; } int drxbsp_hst_sleep(u32 n) { msleep(n); - return DRX_STS_OK; + return 0; } u32 drxbsp_hst_clock(void) @@ -107,7 +107,7 @@ int drxbsp_i2c_write_read(struct i2c_device_addr *w_dev_addr, return -EREMOTEIO; } - return DRX_STS_OK; + return 0; #ifdef DJH_DEBUG struct drx39xxj_state *state = w_dev_addr->user_data; diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c index 4671dcc..e0fc219 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c @@ -154,7 +154,7 @@ static int drxdap_fasi_write_reg8(struct i2c_device_addr *dev_addr, /* address o u8 data, /* data to write */ u32 flags) { /* special device flags */ - return DRX_STS_ERROR; + return -EIO; } static int drxdap_fasi_read_reg8(struct i2c_device_addr *dev_addr, /* address of I2C device */ @@ -162,7 +162,7 @@ static int drxdap_fasi_read_reg8(struct i2c_device_addr *dev_addr, /* address of u8 *data, /* buffer to receive data */ u32 flags) { /* special device flags */ - return DRX_STS_ERROR; + return -EIO; } static int drxdap_fasi_read_modify_write_reg8(struct i2c_device_addr *dev_addr, /* address of I2C device */ @@ -171,7 +171,7 @@ static int drxdap_fasi_read_modify_write_reg8(struct i2c_device_addr *dev_addr, u8 datain, /* data to send */ u8 *dataout) { /* data to receive back */ - return DRX_STS_ERROR; + return -EIO; } static int drxdap_fasi_read_modify_write_reg32(struct i2c_device_addr *dev_addr, /* address of I2C device */ @@ -180,7 +180,7 @@ static int drxdap_fasi_read_modify_write_reg32(struct i2c_device_addr *dev_addr, u32 datain, /* data to send */ u32 *dataout) { /* data to receive back */ - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -204,9 +204,9 @@ static int drxdap_fasi_read_modify_write_reg32(struct i2c_device_addr *dev_addr, * the target platform. * * Output: -* - DRX_STS_OK if reading was successful +* - 0 if reading was successful * in that case: data read is in *data. -* - DRX_STS_ERROR if anything went wrong +* - -EIO if anything went wrong * ******************************/ @@ -222,7 +222,7 @@ static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr, /* Check parameters ******************************************************* */ if (dev_addr == NULL) { - return DRX_STS_INVALID_ARG; + return -EINVAL; } overhead_size = (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1) + @@ -233,7 +233,7 @@ static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr, DRXDAP_FASI_LONG_FORMAT(addr)) || (overhead_size > (DRXDAP_MAX_WCHUNKSIZE)) || ((datasize != 0) && (data == NULL)) || ((datasize & 1) == 1)) { - return DRX_STS_INVALID_ARG; + return -EINVAL; } /* ReadModifyWrite & mode flag bits are not allowed */ @@ -284,7 +284,7 @@ static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr, * No special action is needed for write chunks here. */ rc = drxbsp_i2c_write_read(dev_addr, bufx, buf, 0, 0, 0); - if (rc == DRX_STS_OK) + if (rc == 0) rc = drxbsp_i2c_write_read(0, 0, 0, dev_addr, todo, data); #else /* In multi master mode, do everything in one RW action */ @@ -294,7 +294,7 @@ static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr, data += todo; addr += (todo >> 1); datasize -= todo; - } while (datasize && rc == DRX_STS_OK); + } while (datasize && rc == 0); return rc; } @@ -318,9 +318,9 @@ static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr, * master on the I2C bus. * * Output: -* - DRX_STS_OK if reading was successful +* - 0 if reading was successful * in that case: read back data is at *rdata -* - DRX_STS_ERROR if anything went wrong +* - -EIO if anything went wrong * ******************************/ @@ -329,15 +329,15 @@ static int drxdap_fasi_read_modify_write_reg16(struct i2c_device_addr *dev_addr, u32 raddr, u16 wdata, u16 *rdata) { - int rc = DRX_STS_ERROR; + int rc = -EIO; #if (DRXDAPFASI_LONG_ADDR_ALLOWED == 1) if (rdata == NULL) { - return DRX_STS_INVALID_ARG; + return -EINVAL; } rc = drxdap_fasi_write_reg16(dev_addr, waddr, wdata, DRXDAP_FASI_RMW); - if (rc == DRX_STS_OK) + if (rc == 0) rc = drxdap_fasi_read_reg16(dev_addr, raddr, rdata, 0); #endif @@ -356,9 +356,9 @@ static int drxdap_fasi_read_modify_write_reg16(struct i2c_device_addr *dev_addr, * converted back to the target platform's endianness. * * Output: -* - DRX_STS_OK if reading was successful +* - 0 if reading was successful * in that case: read data is at *data -* - DRX_STS_ERROR if anything went wrong +* - -EIO if anything went wrong * ******************************/ @@ -370,7 +370,7 @@ static int drxdap_fasi_read_reg16(struct i2c_device_addr *dev_addr, int rc; if (!data) { - return DRX_STS_INVALID_ARG; + return -EINVAL; } rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags); *data = buf[0] + (((u16) buf[1]) << 8); @@ -389,9 +389,9 @@ static int drxdap_fasi_read_reg16(struct i2c_device_addr *dev_addr, * converted back to the target platform's endianness. * * Output: -* - DRX_STS_OK if reading was successful +* - 0 if reading was successful * in that case: read data is at *data -* - DRX_STS_ERROR if anything went wrong +* - -EIO if anything went wrong * ******************************/ @@ -403,7 +403,7 @@ static int drxdap_fasi_read_reg32(struct i2c_device_addr *dev_addr, int rc; if (!data) { - return DRX_STS_INVALID_ARG; + return -EINVAL; } rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags); *data = (((u32) buf[0]) << 0) + @@ -429,8 +429,8 @@ static int drxdap_fasi_read_reg32(struct i2c_device_addr *dev_addr, * the target platform. * * Output: -* - DRX_STS_OK if writing was successful -* - DRX_STS_ERROR if anything went wrong +* - 0 if writing was successful +* - -EIO if anything went wrong * ******************************/ @@ -440,14 +440,14 @@ static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr, u8 *data, u32 flags) { u8 buf[DRXDAP_MAX_WCHUNKSIZE]; - int st = DRX_STS_ERROR; - int first_err = DRX_STS_OK; + int st = -EIO; + int first_err = 0; u16 overhead_size = 0; u16 block_size = 0; /* Check parameters ******************************************************* */ if (dev_addr == NULL) { - return DRX_STS_INVALID_ARG; + return -EINVAL; } overhead_size = (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1) + @@ -458,7 +458,7 @@ static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr, DRXDAP_FASI_LONG_FORMAT(addr)) || (overhead_size > (DRXDAP_MAX_WCHUNKSIZE)) || ((datasize != 0) && (data == NULL)) || ((datasize & 1) == 1)) { - return DRX_STS_INVALID_ARG; + return -EINVAL; } flags &= DRXDAP_FASI_FLAGS; @@ -527,7 +527,7 @@ static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr, (struct i2c_device_addr *)(NULL), 0, (u8 *)(NULL)); - if ((st != DRX_STS_OK) && (first_err == DRX_STS_OK)) { + if ((st != 0) && (first_err == 0)) { /* at the end, return the first error encountered */ first_err = st; } @@ -544,7 +544,7 @@ static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr, (struct i2c_device_addr *)(NULL), 0, (u8 *)(NULL)); - if ((st != DRX_STS_OK) && (first_err == DRX_STS_OK)) { + if ((st != 0) && (first_err == 0)) { /* at the end, return the first error encountered */ first_err = st; } @@ -568,8 +568,8 @@ static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr, * converted from the target platform's endianness to little endian. * * Output: -* - DRX_STS_OK if writing was successful -* - DRX_STS_ERROR if anything went wrong +* - 0 if writing was successful +* - -EIO if anything went wrong * ******************************/ @@ -597,8 +597,8 @@ static int drxdap_fasi_write_reg16(struct i2c_device_addr *dev_addr, * converted from the target platform's endianness to little endian. * * Output: -* - DRX_STS_OK if writing was successful -* - DRX_STS_ERROR if anything went wrong +* - 0 if writing was successful +* - -EIO if anything went wrong * ******************************/ diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c index 4234b7d..1737a8c 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c @@ -197,8 +197,8 @@ static void *get_scan_context(struct drx_demod_instance *demod, void *scan_conte * \param demod: Pointer to demodulator instance. * \param lock_stat: Pointer to bool indicating if end result is lock or not. * \return int. -* \retval DRX_STS_OK: Success -* \retval DRX_STS_ERROR: I2C failure or bsp function failure. +* \retval 0: Success +* \retval -EIO: I2C failure or bsp function failure. * * Wait until timeout, desired lock or NEVER_LOCK. * Assume: @@ -229,8 +229,8 @@ static int scan_wait_for_lock(struct drx_demod_instance *demod, bool *is_locked) while (!done_waiting) { if (drx_ctrl(demod, DRX_CTRL_LOCK_STATUS, &lock_state) != - DRX_STS_OK) { - return DRX_STS_ERROR; + 0) { + return -EIO; } current_time = drxbsp_hst_clock(); @@ -246,14 +246,14 @@ static int scan_wait_for_lock(struct drx_demod_instance *demod, bool *is_locked) /* lock_state == DRX_NOT_LOCKED and timeout */ done_waiting = true; } else { - if (drxbsp_hst_sleep(10) != DRX_STS_OK) { - return DRX_STS_ERROR; + if (drxbsp_hst_sleep(10) != 0) { + return -EIO; } } /* if ( timer_value > timeout_value ) .. */ } /* while */ - return DRX_STS_OK; + return 0; } /*============================================================================*/ @@ -263,8 +263,8 @@ static int scan_wait_for_lock(struct drx_demod_instance *demod, bool *is_locked) * \param demod: Pointer to demodulator instance. * \param skip : Minimum frequency step to take. * \return int. -* \retval DRX_STS_OK: Succes. -* \retval DRX_STS_INVALID_ARG: Invalid frequency plan. +* \retval 0: Succes. +* \retval -EINVAL: Invalid frequency plan. * * Helper function for ctrl_scan_next() function. * Compute next frequency & index in frequency plan. @@ -331,7 +331,7 @@ scan_prepare_next_scan(struct drx_demod_instance *demod, s32 skip) common_attr->scan_freq_plan_index = table_index; common_attr->scan_next_frequency = next_frequency; - return DRX_STS_OK; + return 0; } /*============================================================================*/ @@ -345,10 +345,10 @@ scan_prepare_next_scan(struct drx_demod_instance *demod, s32 skip) * \param get_next_channel: Return true if next frequency is desired at next call * * \return int. -* \retval DRX_STS_OK: Channel found, DRX_CTRL_GET_CHANNEL can be used +* \retval 0: Channel found, DRX_CTRL_GET_CHANNEL can be used * to retrieve channel parameters. -* \retval DRX_STS_BUSY: Channel not found (yet). -* \retval DRX_STS_ERROR: Something went wrong. +* \retval -EBUSY: Channel not found (yet). +* \retval -EIO: Something went wrong. * * scan_channel and get_next_channel will be NULL for INIT and STOP. */ @@ -358,25 +358,25 @@ scan_function_default(void *scan_context, struct drx_channel *scan_channel, bool *get_next_channel) { struct drx_demod_instance *demod = NULL; - int status = DRX_STS_ERROR; + int status = -EIO; bool is_locked = false; demod = (struct drx_demod_instance *) scan_context; if (scan_command != DRX_SCAN_COMMAND_NEXT) { /* just return OK if not doing "scan next" */ - return DRX_STS_OK; + return 0; } *get_next_channel = false; status = drx_ctrl(demod, DRX_CTRL_SET_CHANNEL, scan_channel); - if (status != DRX_STS_OK) { + if (status != 0) { return status; } status = scan_wait_for_lock(demod, &is_locked); - if (status != DRX_STS_OK) { + if (status != 0) { return status; } @@ -385,10 +385,10 @@ scan_function_default(void *scan_context, if (!is_locked) { /* no channel found */ - return DRX_STS_BUSY; + return -EBUSY; } /* channel found */ - return DRX_STS_OK; + return 0; } /*============================================================================*/ @@ -398,10 +398,10 @@ scan_function_default(void *scan_context, * \param demod: Pointer to demodulator instance. * \param scan_param: Pointer to scan parameters. * \return int. -* \retval DRX_STS_OK: Initialized for scan. -* \retval DRX_STS_ERROR: No overlap between frequency plan and tuner +* \retval 0: Initialized for scan. +* \retval -EIO: No overlap between frequency plan and tuner * range. -* \retval DRX_STS_INVALID_ARG: Wrong parameters. +* \retval -EINVAL: Wrong parameters. * * This function should be called before starting a complete channel scan. * It will prepare everything for a complete channel scan. @@ -413,7 +413,6 @@ scan_function_default(void *scan_context, static int ctrl_scan_init(struct drx_demod_instance *demod, struct drx_scan_param *scan_param) { - int status = DRX_STS_ERROR; struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL); s32 max_tuner_freq = 0; s32 min_tuner_freq = 0; @@ -437,7 +436,7 @@ ctrl_scan_init(struct drx_demod_instance *demod, struct drx_scan_param *scan_par (scan_param->frequency_plan_size == 0) ) { common_attr->scan_active = false; - return DRX_STS_INVALID_ARG; + return -EINVAL; } /* Check frequency plan contents */ @@ -454,13 +453,13 @@ ctrl_scan_init(struct drx_demod_instance *demod, struct drx_scan_param *scan_par if (step <= 0) { /* Step must be positive and non-zero */ common_attr->scan_active = false; - return DRX_STS_INVALID_ARG; + return -EINVAL; } if (first_freq > last_freq) { /* First center frequency is higher than last center frequency */ common_attr->scan_active = false; - return DRX_STS_INVALID_ARG; + return -EINVAL; } width = last_freq - first_freq; @@ -469,7 +468,7 @@ ctrl_scan_init(struct drx_demod_instance *demod, struct drx_scan_param *scan_par /* Difference between last and first center frequency is not an integer number of steps */ common_attr->scan_active = false; - return DRX_STS_INVALID_ARG; + return -EINVAL; } /* Check if frequency plan entry intersects with tuner range */ @@ -517,7 +516,7 @@ ctrl_scan_init(struct drx_demod_instance *demod, struct drx_scan_param *scan_par if (nr_channels_in_plan == 0) { /* Tuner range and frequency plan ranges do not overlap */ common_attr->scan_active = false; - return DRX_STS_ERROR; + return -EIO; } /* Store parameters */ @@ -528,12 +527,14 @@ ctrl_scan_init(struct drx_demod_instance *demod, struct drx_scan_param *scan_par scan_context = get_scan_context(demod, scan_context); - status = (*(get_scan_function(demod))) - (scan_context, DRX_SCAN_COMMAND_INIT, NULL, NULL); + /* + * FIXME: Should we really ignore the result of the scan function? + */ + (*(get_scan_function(demod)))(scan_context, DRX_SCAN_COMMAND_INIT, NULL, NULL); common_attr->scan_active = false; - return DRX_STS_OK; + return 0; } /*============================================================================*/ @@ -542,13 +543,13 @@ ctrl_scan_init(struct drx_demod_instance *demod, struct drx_scan_param *scan_par * \brief Stop scanning. * \param demod: Pointer to demodulator instance. * \return int. -* \retval DRX_STS_OK: Scan stopped. -* \retval DRX_STS_ERROR: Something went wrong. -* \retval DRX_STS_INVALID_ARG: Wrong parameters. +* \retval 0: Scan stopped. +* \retval -EIO: Something went wrong. +* \retval -EINVAL: Wrong parameters. */ static int ctrl_scan_stop(struct drx_demod_instance *demod) { - int status = DRX_STS_ERROR; + int status = -EIO; struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL); void *scan_context = NULL; @@ -559,7 +560,7 @@ static int ctrl_scan_stop(struct drx_demod_instance *demod) (common_attr->scan_max_channels == 0)) { /* Scan was not running, just return OK */ common_attr->scan_active = false; - return DRX_STS_OK; + return 0; } /* Call default or device-specific scanning stop function */ @@ -583,15 +584,15 @@ static int ctrl_scan_stop(struct drx_demod_instance *demod) * \param demod: Pointer to demodulator instance. * \param scan_progress: Pointer to scan progress. * \return int. -* \retval DRX_STS_OK: Channel found, DRX_CTRL_GET_CHANNEL can be used +* \retval 0: Channel found, DRX_CTRL_GET_CHANNEL can be used * to retrieve channel parameters. -* \retval DRX_STS_BUSY: Tried part of the channels, as specified in +* \retval -EBUSY: Tried part of the channels, as specified in * num_tries field of scan parameters. At least one * more call to DRX_CTRL_SCAN_NEXT is needed to * complete scanning. -* \retval DRX_STS_READY: Reached end of scan range. -* \retval DRX_STS_ERROR: Something went wrong. -* \retval DRX_STS_INVALID_ARG: Wrong parameters. The scan_progress may be NULL. +* \retval -ERANGE: Reached end of scan range. +* \retval -EIO: Something went wrong. +* \retval -EINVAL: Wrong parameters. The scan_progress may be NULL. * * Progress indication will run from 0 upto DRX_SCAN_MAX_PROGRESS during scan. * @@ -609,7 +610,7 @@ static int ctrl_scan_next(struct drx_demod_instance *demod, u16 *scan_progress) /* Check scan parameters */ if (scan_progress == NULL) { common_attr->scan_active = false; - return DRX_STS_INVALID_ARG; + return -EINVAL; } *scan_progress = 0; @@ -618,7 +619,7 @@ static int ctrl_scan_next(struct drx_demod_instance *demod, u16 *scan_progress) (common_attr->scan_max_channels == 0)) { /* ctrl_scan_init() was not called succesfully before ctrl_scan_next() */ common_attr->scan_active = false; - return DRX_STS_ERROR; + return -EIO; } *scan_progress = (u16) (((common_attr->scan_channels_scanned) * @@ -631,7 +632,7 @@ static int ctrl_scan_next(struct drx_demod_instance *demod, u16 *scan_progress) for (i = 0; ((i < num_tries) && (!(*scan_ready))); i++) { struct drx_channel scan_channel = { 0 }; - int status = DRX_STS_ERROR; + int status = -EIO; struct drx_frequency_plan *freq_plan = (struct drx_frequency_plan *) (NULL); bool next_channel = false; void *scan_context = NULL; @@ -666,10 +667,10 @@ static int ctrl_scan_next(struct drx_demod_instance *demod, u16 *scan_progress) /* Proceed to next channel if requested */ if (next_channel) { - int next_status = DRX_STS_ERROR; + int next_status = -EIO; s32 skip = 0; - if (status == DRX_STS_OK) { + if (status == 0) { /* a channel was found, so skip some frequency steps */ skip = common_attr->scan_param->skip; } @@ -681,12 +682,12 @@ static int ctrl_scan_next(struct drx_demod_instance *demod, u16 *scan_progress) ((u32) (max_progress))) / (common_attr->scan_max_channels)); - if (next_status != DRX_STS_OK) { + if (next_status != 0) { common_attr->scan_active = false; return next_status; } } - if (status != DRX_STS_BUSY) { + if (status != -EBUSY) { /* channel found or error */ common_attr->scan_active = false; return status; @@ -697,12 +698,12 @@ static int ctrl_scan_next(struct drx_demod_instance *demod, u16 *scan_progress) /* End of scan reached: call stop-scan, ignore any error */ ctrl_scan_stop(demod); common_attr->scan_active = false; - return DRX_STS_READY; + return -ERANGE; } common_attr->scan_active = false; - return DRX_STS_BUSY; + return -EBUSY; } #endif /* #ifndef DRX_EXCLUDE_SCAN */ @@ -714,9 +715,9 @@ static int ctrl_scan_next(struct drx_demod_instance *demod, u16 *scan_progress) * \param demod: Pointer to demodulator instance. * \param tunerChannel: Pointer to tuning parameters. * \return int. -* \retval DRX_STS_OK: Tuner programmed successfully. -* \retval DRX_STS_ERROR: Something went wrong. -* \retval DRX_STS_INVALID_ARG: Wrong parameters. +* \retval 0: Tuner programmed successfully. +* \retval -EIO: Something went wrong. +* \retval -EINVAL: Wrong parameters. * * tunerChannel passes parameters to program the tuner, * but also returns the actual RF and IF frequency from the tuner. @@ -728,20 +729,20 @@ ctrl_program_tuner(struct drx_demod_instance *demod, struct drx_channel *channel struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL); enum drx_standard standard = DRX_STANDARD_UNKNOWN; u32 tuner_mode = 0; - int status = DRX_STS_ERROR; + int status = -EIO; s32 if_frequency = 0; bool tuner_slow_mode = false; /* can't tune without a tuner */ if (demod->my_tuner == NULL) { - return DRX_STS_INVALID_ARG; + return -EINVAL; } common_attr = (struct drx_common_attr *) demod->my_common_attr; /* select analog or digital tuner mode based on current standard */ - if (drx_ctrl(demod, DRX_CTRL_GET_STANDARD, &standard) != DRX_STS_OK) { - return DRX_STS_ERROR; + if (drx_ctrl(demod, DRX_CTRL_GET_STANDARD, &standard) != 0) { + return -EIO; } if (DRX_ISATVSTD(standard)) { @@ -763,7 +764,7 @@ ctrl_program_tuner(struct drx_demod_instance *demod, struct drx_channel *channel tuner_mode |= TUNER_MODE_8MHZ; break; default: /* note: also for unknown bandwidth */ - return DRX_STS_INVALID_ARG; + return -EINVAL; } DRX_GET_TUNERSLOWMODE(demod, tuner_slow_mode); @@ -777,11 +778,11 @@ ctrl_program_tuner(struct drx_demod_instance *demod, struct drx_channel *channel if (common_attr->tuner_port_nr == 1) { bool bridge_closed = true; - int status_bridge = DRX_STS_ERROR; + int status_bridge = -EIO; status_bridge = drx_ctrl(demod, DRX_CTRL_I2C_BRIDGE, &bridge_closed); - if (status_bridge != DRX_STS_OK) { + if (status_bridge != 0) { return status_bridge; } } @@ -792,17 +793,17 @@ ctrl_program_tuner(struct drx_demod_instance *demod, struct drx_channel *channel /* attempt restoring bridge before checking status of set_frequency */ if (common_attr->tuner_port_nr == 1) { bool bridge_closed = false; - int status_bridge = DRX_STS_ERROR; + int status_bridge = -EIO; status_bridge = drx_ctrl(demod, DRX_CTRL_I2C_BRIDGE, &bridge_closed); - if (status_bridge != DRX_STS_OK) { + if (status_bridge != 0) { return status_bridge; } } /* now check status of drxbsp_tuner_set_frequency */ - if (status != DRX_STS_OK) { + if (status != 0) { return status; } @@ -811,7 +812,7 @@ ctrl_program_tuner(struct drx_demod_instance *demod, struct drx_channel *channel tuner_mode, &(channel->frequency), &(if_frequency)); - if (status != DRX_STS_OK) { + if (status != 0) { return status; } @@ -819,7 +820,7 @@ ctrl_program_tuner(struct drx_demod_instance *demod, struct drx_channel *channel TODO: check if this is required and safe */ DRX_SET_INTERMEDIATEFREQ(demod, if_frequency); - return DRX_STS_OK; + return 0; } /*============================================================================*/ @@ -829,9 +830,9 @@ ctrl_program_tuner(struct drx_demod_instance *demod, struct drx_channel *channel * \param demod: Pointer to demodulator instance. * \param registers: Registers to dump. * \return int. -* \retval DRX_STS_OK: Dump executed successfully. -* \retval DRX_STS_ERROR: Something went wrong. -* \retval DRX_STS_INVALID_ARG: Wrong parameters. +* \retval 0: Dump executed successfully. +* \retval -EIO: Something went wrong. +* \retval -EINVAL: Wrong parameters. * */ static int ctrl_dump_registers(struct drx_demod_instance *demod, @@ -841,12 +842,12 @@ static int ctrl_dump_registers(struct drx_demod_instance *demod, if (registers == NULL) { /* registers not supplied */ - return DRX_STS_INVALID_ARG; + return -EINVAL; } /* start dumping registers */ while (registers[i].address != 0) { - int status = DRX_STS_ERROR; + int status = -EIO; u16 value = 0; u32 data = 0; @@ -857,7 +858,7 @@ static int ctrl_dump_registers(struct drx_demod_instance *demod, data = (u32) value; - if (status != DRX_STS_OK) { + if (status != 0) { /* no breakouts; depending on device ID, some HW blocks might not be available */ data |= ((u32) status) << 16; @@ -867,7 +868,7 @@ static int ctrl_dump_registers(struct drx_demod_instance *demod, } /* all done, all OK (any errors are saved inside data) */ - return DRX_STS_OK; + return 0; } /*============================================================================*/ @@ -963,15 +964,15 @@ static u16 u_code_compute_crc(u8 *block_data, u16 nr_words) * \param mc_info: Pointer to information about microcode data. * \param action: Either UCODE_UPLOAD or UCODE_VERIFY * \return int. -* \retval DRX_STS_OK: +* \retval 0: * - In case of UCODE_UPLOAD: code is successfully uploaded. * - In case of UCODE_VERIFY: image on device is equal to * image provided to this control function. -* \retval DRX_STS_ERROR: +* \retval -EIO: * - In case of UCODE_UPLOAD: I2C error. * - In case of UCODE_VERIFY: I2C error or image on device * is not equal to image provided to this control function. -* \retval DRX_STS_INVALID_ARG: +* \retval -EINVAL: * - Invalid arguments. * - Provided image is corrupt */ @@ -990,7 +991,7 @@ ctrl_u_code(struct drx_demod_instance *demod, /* Check arguments */ if ((mc_info == NULL) || (mc_info->mc_data == NULL)) { - return DRX_STS_INVALID_ARG; + return -EINVAL; } mc_data = mc_info->mc_data; @@ -1003,7 +1004,7 @@ ctrl_u_code(struct drx_demod_instance *demod, if ((mc_magic_word != DRX_UCODE_MAGIC_WORD) || (mc_nr_of_blks == 0)) { /* wrong endianess or wrong data ? */ - return DRX_STS_INVALID_ARG; + return -EINVAL; } /* Scan microcode blocks first for version info if uploading */ @@ -1053,7 +1054,7 @@ ctrl_u_code(struct drx_demod_instance *demod, It is also valid if no validation control exists. */ rc = drx_ctrl(demod, DRX_CTRL_VALIDATE_UCODE, NULL); - if (rc != DRX_STS_OK && rc != DRX_STS_FUNC_NOT_AVAILABLE) { + if (rc != 0 && rc != -ENOTSUPP) { return rc; } @@ -1085,7 +1086,7 @@ ctrl_u_code(struct drx_demod_instance *demod, (block_hdr.CRC != u_code_compute_crc(mc_data, block_hdr.size))) ) { /* Wrong data ! */ - return DRX_STS_INVALID_ARG; + return -EINVAL; } mc_block_nr_bytes = block_hdr.size * ((u16) sizeof(u16)); @@ -1103,8 +1104,8 @@ ctrl_u_code(struct drx_demod_instance *demod, addr, mc_block_nr_bytes, mc_data, 0x0000) != - DRX_STS_OK) { - return DRX_STS_ERROR; + 0) { + return -EIO; } /* if */ } break; @@ -1144,8 +1145,8 @@ ctrl_u_code(struct drx_demod_instance *demod, (u8 *) mc_data_buffer, 0x0000) != - DRX_STS_OK) { - return DRX_STS_ERROR; + 0) { + return -EIO; } result = @@ -1154,7 +1155,7 @@ ctrl_u_code(struct drx_demod_instance *demod, bytes_to_compare); if (result != 0) { - return DRX_STS_ERROR; + return -EIO; } curr_addr += @@ -1170,7 +1171,7 @@ ctrl_u_code(struct drx_demod_instance *demod, /*================================================================*/ default: - return DRX_STS_INVALID_ARG; + return -EINVAL; break; } /* switch ( action ) */ @@ -1182,7 +1183,7 @@ ctrl_u_code(struct drx_demod_instance *demod, } /* for( i = 0 ; imy_demod_funct == NULL) || @@ -1309,12 +1310,12 @@ int drx_open(struct drx_demod_instance *demod) (demod->my_ext_attr == NULL) || (demod->my_i2c_dev_addr == NULL) || (demod->my_common_attr->is_opened)) { - return DRX_STS_INVALID_ARG; + return -EINVAL; } status = (*(demod->my_demod_funct->open_func)) (demod); - if (status == DRX_STS_OK) + if (status == 0) demod->my_common_attr->is_opened = true; return status; @@ -1326,10 +1327,10 @@ int drx_open(struct drx_demod_instance *demod) * \brief Close device. * \param demod: A pointer to a demodulator instance. * \return int Return status. -* \retval DRX_STS_OK: Closed demod instance with succes. -* \retval DRX_STS_ERROR: Driver not initialized or error during close +* \retval 0: Closed demod instance with succes. +* \retval -EIO: Driver not initialized or error during close * demod. -* \retval DRX_STS_INVALID_ARG: Demod instance has invalid content. +* \retval -EINVAL: Demod instance has invalid content. * * Free resources occupied by device instance. * Put device into sleep mode. @@ -1337,7 +1338,7 @@ int drx_open(struct drx_demod_instance *demod) int drx_close(struct drx_demod_instance *demod) { - int status = DRX_STS_OK; + int status = 0; if ((demod == NULL) || (demod->my_demod_funct == NULL) || @@ -1345,7 +1346,7 @@ int drx_close(struct drx_demod_instance *demod) (demod->my_ext_attr == NULL) || (demod->my_i2c_dev_addr == NULL) || (!demod->my_common_attr->is_opened)) { - return DRX_STS_INVALID_ARG; + return -EINVAL; } status = (*(demod->my_demod_funct->close_func)) (demod); @@ -1363,12 +1364,12 @@ int drx_close(struct drx_demod_instance *demod) * \param ctrl: Reference to desired control function. * \param ctrl_data: Pointer to data structure for control function. * \return int Return status. -* \retval DRX_STS_OK: Control function completed successfully. -* \retval DRX_STS_ERROR: Driver not initialized or error during +* \retval 0: Control function completed successfully. +* \retval -EIO: Driver not initialized or error during * control demod. -* \retval DRX_STS_INVALID_ARG: Demod instance or ctrl_data has invalid +* \retval -EINVAL: Demod instance or ctrl_data has invalid * content. -* \retval DRX_STS_FUNC_NOT_AVAILABLE: Specified control function is not +* \retval -ENOTSUPP: Specified control function is not * available. * * Data needed or returned by the control function is stored in ctrl_data. @@ -1378,20 +1379,20 @@ int drx_close(struct drx_demod_instance *demod) int drx_ctrl(struct drx_demod_instance *demod, u32 ctrl, void *ctrl_data) { - int status = DRX_STS_ERROR; + int status = -EIO; if ((demod == NULL) || (demod->my_demod_funct == NULL) || (demod->my_common_attr == NULL) || (demod->my_ext_attr == NULL) || (demod->my_i2c_dev_addr == NULL) ) { - return DRX_STS_INVALID_ARG; + return -EINVAL; } if (((!demod->my_common_attr->is_opened) && (ctrl != DRX_CTRL_PROBE_DEVICE) && (ctrl != DRX_CTRL_VERSION)) ) { - return DRX_STS_INVALID_ARG; + return -EINVAL; } if ((DRX_ISPOWERDOWNMODE(demod->my_common_attr->current_power_mode) && @@ -1400,7 +1401,7 @@ drx_ctrl(struct drx_demod_instance *demod, u32 ctrl, void *ctrl_data) (ctrl != DRX_CTRL_NOP) && (ctrl != DRX_CTRL_VERSION) ) ) { - return DRX_STS_FUNC_NOT_AVAILABLE; + return -ENOTSUPP; } /* Fixed control functions */ @@ -1408,7 +1409,7 @@ drx_ctrl(struct drx_demod_instance *demod, u32 ctrl, void *ctrl_data) /*======================================================================*/ case DRX_CTRL_NOP: /* No operation */ - return DRX_STS_OK; + return 0; break; /*======================================================================*/ @@ -1425,7 +1426,7 @@ drx_ctrl(struct drx_demod_instance *demod, u32 ctrl, void *ctrl_data) /* Virtual functions */ /* First try calling function from derived class */ status = (*(demod->my_demod_funct->ctrl_func)) (demod, ctrl, ctrl_data); - if (status == DRX_STS_FUNC_NOT_AVAILABLE) { + if (status == -ENOTSUPP) { /* Now try calling a the base class function */ switch (ctrl) { /*===================================================================*/ @@ -1488,13 +1489,13 @@ drx_ctrl(struct drx_demod_instance *demod, u32 ctrl, void *ctrl_data) /*===================================================================*/ default: - return DRX_STS_FUNC_NOT_AVAILABLE; + return -ENOTSUPP; } } else { return status; } - return DRX_STS_OK; + return 0; } /*============================================================================*/ diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h index 975b3ba..1b71622 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h @@ -28,30 +28,11 @@ POSSIBILITY OF SUCH DAMAGE. */ -/** -* \file $Id: drx_driver.h,v 1.84 2010/01/14 22:47:50 dingtao Exp $ -* -* \brief DRX driver API -* -*/ #ifndef __DRXDRIVER_H__ #define __DRXDRIVER_H__ #include -/*------------------------------------------------------------------------- -INCLUDES --------------------------------------------------------------------------*/ - -enum drx_status { - DRX_STS_READY = 3, /**< device/service is ready */ - DRX_STS_BUSY = 2, /**< device/service is busy */ - DRX_STS_OK = 1, /**< everything is OK */ - DRX_STS_INVALID_ARG = -1, - /**< invalid arguments */ - DRX_STS_ERROR = -2, /**< general error */ - DRX_STS_FUNC_NOT_AVAILABLE = -3 - /**< unavailable functionality */ -}; +#include /* * This structure contains the I2C address, the device ID and a user_data pointer. @@ -82,8 +63,8 @@ Exported FUNCTIONS * \fn drxbsp_i2c_init() * \brief Initialize I2C communication module. * \return int Return status. -* \retval DRX_STS_OK Initialization successful. -* \retval DRX_STS_ERROR Initialization failed. +* \retval 0 Initialization successful. +* \retval -EIO Initialization failed. */ int drxbsp_i2c_init(void); @@ -91,8 +72,8 @@ int drxbsp_i2c_init(void); * \fn drxbsp_i2c_term() * \brief Terminate I2C communication module. * \return int Return status. -* \retval DRX_STS_OK Termination successful. -* \retval DRX_STS_ERROR Termination failed. +* \retval 0 Termination successful. +* \retval -EIO Termination failed. */ int drxbsp_i2c_term(void); @@ -111,9 +92,9 @@ int drxbsp_i2c_term(void); * \param r_count The number of bytes to read * \param r_data The array to read the data from * \return int Return status. -* \retval DRX_STS_OK Succes. -* \retval DRX_STS_ERROR Failure. -* \retval DRX_STS_INVALID_ARG Parameter 'wcount' is not zero but parameter +* \retval 0 Succes. +* \retval -EIO Failure. +* \retval -EINVAL Parameter 'wcount' is not zero but parameter * 'wdata' contains NULL. * Idem for 'rcount' and 'rdata'. * Both w_dev_addr and r_dev_addr are NULL. @@ -2738,7 +2719,7 @@ Access macros config.cfg_type = cfg_name; \ config.cfg_data = &cfg_data; \ cfg_status = drx_ctrl(demod, DRX_CTRL_GET_CFG, &config); \ - if (cfg_status == DRX_STS_OK) { \ + if (cfg_status == 0) { \ value = cfg_data; \ } else { \ value = (data_type)error_value; \ diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index f1fe3e3..811e09c 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -1672,8 +1672,8 @@ static int drxj_dap_read_modify_write_reg8(struct i2c_device_addr *dev_addr, * \param wdata Data to write * \param rdata Buffer for data to read * \return int -* \retval DRX_STS_OK Succes -* \retval DRX_STS_ERROR Timeout, I2C error, illegal bank +* \retval 0 Succes +* \retval -EIO Timeout, I2C error, illegal bank * * 16 bits register read modify write access using short addressing format only. * Requires knowledge of the registermap, thus device dependent. @@ -1692,24 +1692,24 @@ static int drxj_dap_rm_write_reg16short(struct i2c_device_addr *dev_addr, int rc; if (rdata == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; /* Set RMW flag */ rc = drx_dap_fasi_funct_g.write_reg16func(dev_addr, SIO_HI_RA_RAM_S0_FLG_ACC__A, SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__M, 0x0000); - if (rc == DRX_STS_OK) { + if (rc == 0) { /* Write new data: triggers RMW */ rc = drx_dap_fasi_funct_g.write_reg16func(dev_addr, waddr, wdata, 0x0000); } - if (rc == DRX_STS_OK) { + if (rc == 0) { /* Read old data */ rc = drx_dap_fasi_funct_g.read_reg16func(dev_addr, raddr, rdata, 0x0000); } - if (rc == DRX_STS_OK) { + if (rc == 0) { /* Reset RMW flag */ rc = drx_dap_fasi_funct_g.write_reg16func(dev_addr, SIO_HI_RA_RAM_S0_FLG_ACC__A, @@ -1769,8 +1769,8 @@ static int drxj_dap_read_reg8(struct i2c_device_addr *dev_addr, * \param addr * \param data * \return int -* \retval DRX_STS_OK Succes -* \retval DRX_STS_ERROR Timeout, I2C error, illegal bank +* \retval 0 Succes +* \retval -EIO Timeout, I2C error, illegal bank * * 16 bits register read access via audio token ring interface. * @@ -1782,11 +1782,11 @@ static int drxj_dap_read_aud_reg16(struct i2c_device_addr *dev_addr, u32 current_timer = 0; u32 delta_timer = 0; u16 tr_status = 0; - int stat = DRX_STS_ERROR; + int stat = -EIO; /* No read possible for bank 3, return with error */ if (DRXDAP_FASI_ADDR2BANK(addr) == 3) { - stat = DRX_STS_INVALID_ARG; + stat = -EINVAL; } else { const u32 write_bit = ((dr_xaddr_t) 1) << 16; @@ -1802,13 +1802,13 @@ static int drxj_dap_read_aud_reg16(struct i2c_device_addr *dev_addr, SIO_HI_RA_RAM_S0_RMWBUF__A, 0x0000, &tr_status); - if (stat != DRX_STS_OK) + if (stat != 0) break; current_timer = drxbsp_hst_clock(); delta_timer = current_timer - start_timer; if (delta_timer > DRXJ_DAP_AUDTRIF_TIMEOUT) { - stat = DRX_STS_ERROR; + stat = -EIO; break; } @@ -1819,7 +1819,7 @@ static int drxj_dap_read_aud_reg16(struct i2c_device_addr *dev_addr, } /* if ( DRXDAP_FASI_ADDR2BANK(addr)!=3 ) */ /* Wait for read ready status or timeout */ - if (stat == DRX_STS_OK) { + if (stat == 0) { start_timer = drxbsp_hst_clock(); while ((tr_status & AUD_TOP_TR_CTR_FIFO_RD_RDY__M) != @@ -1827,20 +1827,20 @@ static int drxj_dap_read_aud_reg16(struct i2c_device_addr *dev_addr, stat = drxj_dap_read_reg16(dev_addr, AUD_TOP_TR_CTR__A, &tr_status, 0x0000); - if (stat != DRX_STS_OK) + if (stat != 0) break; current_timer = drxbsp_hst_clock(); delta_timer = current_timer - start_timer; if (delta_timer > DRXJ_DAP_AUDTRIF_TIMEOUT) { - stat = DRX_STS_ERROR; + stat = -EIO; break; } } /* while ( ... ) */ } /* Read value */ - if (stat == DRX_STS_OK) + if (stat == 0) stat = drxj_dap_read_modify_write_reg16(dev_addr, AUD_TOP_TR_RD_REG__A, SIO_HI_RA_RAM_S0_RMWBUF__A, @@ -1854,11 +1854,11 @@ static int drxj_dap_read_reg16(struct i2c_device_addr *dev_addr, u32 addr, u16 *data, u32 flags) { - int stat = DRX_STS_ERROR; + int stat = -EIO; /* Check param */ if ((dev_addr == NULL) || (data == NULL)) - return DRX_STS_INVALID_ARG; + return -EINVAL; if (is_handled_by_aud_tr_if(addr)) stat = drxj_dap_read_aud_reg16(dev_addr, addr, data); @@ -1907,8 +1907,8 @@ static int drxj_dap_write_reg8(struct i2c_device_addr *dev_addr, * \param addr * \param data * \return int -* \retval DRX_STS_OK Succes -* \retval DRX_STS_ERROR Timeout, I2C error, illegal bank +* \retval 0 Succes +* \retval -EIO Timeout, I2C error, illegal bank * * 16 bits register write access via audio token ring interface. * @@ -1916,11 +1916,11 @@ static int drxj_dap_write_reg8(struct i2c_device_addr *dev_addr, static int drxj_dap_write_aud_reg16(struct i2c_device_addr *dev_addr, u32 addr, u16 data) { - int stat = DRX_STS_ERROR; + int stat = -EIO; /* No write possible for bank 2, return with error */ if (DRXDAP_FASI_ADDR2BANK(addr) == 2) { - stat = DRX_STS_INVALID_ARG; + stat = -EINVAL; } else { u32 start_timer = 0; u32 current_timer = 0; @@ -1937,13 +1937,13 @@ static int drxj_dap_write_aud_reg16(struct i2c_device_addr *dev_addr, addr, SIO_HI_RA_RAM_S0_RMWBUF__A, data, &tr_status); - if (stat != DRX_STS_OK) + if (stat != 0) break; current_timer = drxbsp_hst_clock(); delta_timer = current_timer - start_timer; if (delta_timer > DRXJ_DAP_AUDTRIF_TIMEOUT) { - stat = DRX_STS_ERROR; + stat = -EIO; break; } @@ -1963,11 +1963,11 @@ static int drxj_dap_write_reg16(struct i2c_device_addr *dev_addr, u32 addr, u16 data, u32 flags) { - int stat = DRX_STS_ERROR; + int stat = -EIO; /* Check param */ if (dev_addr == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; if (is_handled_by_aud_tr_if(addr)) stat = drxj_dap_write_aud_reg16(dev_addr, addr, data); @@ -2006,8 +2006,8 @@ static int drxj_dap_write_reg32(struct i2c_device_addr *dev_addr, * \param datasize size of data buffer in bytes * \param data pointer to data buffer * \return int -* \retval DRX_STS_OK Succes -* \retval DRX_STS_ERROR Timeout, I2C error, illegal bank +* \retval 0 Succes +* \retval -EIO Timeout, I2C error, illegal bank * */ static @@ -2024,7 +2024,7 @@ int drxj_dap_atomic_read_write_block(struct i2c_device_addr *dev_addr, /* Parameter check */ if (!data || !dev_addr || ((datasize % 2)) || ((datasize / 2) > 8)) - return DRX_STS_INVALID_ARG; + return -EINVAL; /* Set up HI parameters to read or write n bytes */ hi_cmd.cmd = SIO_HI_RA_RAM_CMD_ATOMIC_COPY; @@ -2055,7 +2055,7 @@ int drxj_dap_atomic_read_write_block(struct i2c_device_addr *dev_addr, } rc = hi_command(dev_addr, &hi_cmd, &dummy); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -2071,10 +2071,10 @@ int drxj_dap_atomic_read_write_block(struct i2c_device_addr *dev_addr, } } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } @@ -2090,11 +2090,11 @@ int drxj_dap_atomic_read_reg32(struct i2c_device_addr *dev_addr, u32 *data, u32 flags) { u8 buf[sizeof(*data)]; - int rc = DRX_STS_ERROR; + int rc = -EIO; u32 word = 0; if (!data) - return DRX_STS_INVALID_ARG; + return -EINVAL; rc = drxj_dap_atomic_read_write_block(dev_addr, addr, sizeof(*data), buf, true); @@ -2156,7 +2156,7 @@ static int hi_cfg_command(const struct drx_demod_instance *demod) hi_cmd.param6 = ext_attr->hi_cfg_transmit; rc = hi_command(demod->my_i2c_dev_addr, &hi_cmd, &result); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -2164,10 +2164,10 @@ static int hi_cfg_command(const struct drx_demod_instance *demod) /* Reset power down flag (set one call only) */ ext_attr->hi_cfg_ctrl &= (~(SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ)); - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /** @@ -2195,34 +2195,34 @@ hi_command(struct i2c_device_addr *dev_addr, const struct drxj_hi_cmd *cmd, u16 case SIO_HI_RA_RAM_CMD_CONFIG: case SIO_HI_RA_RAM_CMD_ATOMIC_COPY: rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_HI_RA_RAM_PAR_6__A, cmd->param6, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_HI_RA_RAM_PAR_5__A, cmd->param5, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_HI_RA_RAM_PAR_4__A, cmd->param4, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_HI_RA_RAM_PAR_3__A, cmd->param3, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* fallthrough */ case SIO_HI_RA_RAM_CMD_BRDCTRL: rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_HI_RA_RAM_PAR_2__A, cmd->param2, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_HI_RA_RAM_PAR_1__A, cmd->param1, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -2232,13 +2232,13 @@ hi_command(struct i2c_device_addr *dev_addr, const struct drxj_hi_cmd *cmd, u16 break; default: - return DRX_STS_INVALID_ARG; + return -EINVAL; break; } /* Write command */ rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_HI_RA_RAM_CMD__A, cmd->cmd, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -2261,7 +2261,7 @@ hi_command(struct i2c_device_addr *dev_addr, const struct drxj_hi_cmd *cmd, u16 } rc = DRXJ_DAP.read_reg16func(dev_addr, SIO_HI_RA_RAM_CMD__A, &wait_cmd, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -2269,16 +2269,16 @@ hi_command(struct i2c_device_addr *dev_addr, const struct drxj_hi_cmd *cmd, u16 /* Read result */ rc = DRXJ_DAP.read_reg16func(dev_addr, SIO_HI_RA_RAM_RES__A, result, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } /* if ( powerdown_cmd == true ) */ - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /** @@ -2286,8 +2286,8 @@ rw_error: * \brief Initialise and configurate HI. * \param demod pointer to demod data. * \return int Return status. -* \retval DRX_STS_OK Success. -* \retval DRX_STS_ERROR Failure. +* \retval 0 Success. +* \retval -EIO Failure. * * Needs to know Psys (System Clock period) and Posc (Osc Clock period) * Need to store configuration in driver because of the way I2C @@ -2307,7 +2307,7 @@ static int init_hi(const struct drx_demod_instance *demod) /* PATCH for bug 5003, HI ucode v3.1.0 */ rc = DRXJ_DAP.write_reg16func(dev_addr, 0x4301D7, 0x801, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -2341,15 +2341,15 @@ static int init_hi(const struct drx_demod_instance *demod) ext_attr->hi_cfg_transmit = SIO_HI_RA_RAM_PAR_6__PRE; rc = hi_cfg_command(demod); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -2367,8 +2367,8 @@ rw_error: * \brief Get and store device capabilities. * \param demod Pointer to demodulator instance. * \return int. -* \return DRX_STS_OK Success -* \retval DRX_STS_ERROR Failure +* \return 0 Success +* \retval -EIO Failure * * Depending on pulldowns on MDx pins the following internals are set: * * common_attr->osc_clock_freq @@ -2393,17 +2393,17 @@ static int get_device_capabilities(struct drx_demod_instance *demod) dev_addr = demod->my_i2c_dev_addr; rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.read_reg16func(dev_addr, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -2425,7 +2425,7 @@ static int get_device_capabilities(struct drx_demod_instance *demod) common_attr->osc_clock_freq = 4000; break; default: - return DRX_STS_ERROR; + return -EIO; } /* @@ -2433,7 +2433,7 @@ static int get_device_capabilities(struct drx_demod_instance *demod) Based on pinning v47 */ rc = DRXJ_DAP.read_reg32func(dev_addr, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -2442,18 +2442,18 @@ static int get_device_capabilities(struct drx_demod_instance *demod) switch ((sio_top_jtagid_lo >> 12) & 0xFF) { case 0x31: rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.read_reg16func(dev_addr, SIO_PDR_UIO_IN_HI__A, &bid, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } bid = (bid >> 10) & 0xf; rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -2559,13 +2559,13 @@ static int get_device_capabilities(struct drx_demod_instance *demod) break; default: /* Unknown device variant */ - return DRX_STS_ERROR; + return -EIO; break; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /** @@ -2573,8 +2573,8 @@ rw_error: * \brief Power up device. * \param demod Pointer to demodulator instance. * \return int. -* \return DRX_STS_OK Success -* \retval DRX_STS_ERROR Failure, I2C or max retries reached +* \return 0 Success +* \retval -EIO Failure, I2C or max retries reached * */ @@ -2608,15 +2608,15 @@ static int power_up_device(struct drx_demod_instance *demod) } while ((drxbsp_i2c_write_read ((struct i2c_device_addr *) (NULL), 0, (u8 *)(NULL), dev_addr, 1, &data) - != DRX_STS_OK) && (retry_count < DRXJ_MAX_RETRIES_POWERUP)); + != 0) && (retry_count < DRXJ_MAX_RETRIES_POWERUP)); /* Need some recovery time .... */ drxbsp_hst_sleep(10); if (retry_count == DRXJ_MAX_RETRIES_POWERUP) - return DRX_STS_ERROR; + return -EIO; - return DRX_STS_OK; + return 0; } /*----------------------------------------------------------------------------*/ @@ -2655,7 +2655,7 @@ ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o /* check arguments */ if ((demod == NULL) || (cfg_data == NULL)) - return DRX_STS_INVALID_ARG; + return -EINVAL; dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -2685,55 +2685,55 @@ ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o common_attr->mpeg_cfg.invert_clk = cfg_data->invert_clk; common_attr->mpeg_cfg.static_clk = cfg_data->static_clk; common_attr->mpeg_cfg.bitrate = cfg_data->bitrate; - return DRX_STS_OK; + return 0; } rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_OCR_INVERT__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } switch (ext_attr->standard) { case DRX_STANDARD_8VSB: rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_FCT_USAGE__A, 7, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* 2048 bytes fifo ram */ rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_TMD_CTL_UPD_RATE__A, 10, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_TMD_INT_UPD_RATE__A, 10, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_AVR_PARM_A__A, 5, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_AVR_PARM_B__A, 7, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_RCN_GAIN__A, 10, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Low Water Mark for synchronization */ rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_SNC_LWM__A, 3, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* High Water Mark for synchronization */ rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_SNC_HWM__A, 5, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -2757,7 +2757,7 @@ ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o nr_bits = 4; break; default: - return DRX_STS_ERROR; + return -EIO; } /* ext_attr->constellation */ /* max_bit_rate = symbol_rate * nr_bits * coef */ /* coef = 188/204 */ @@ -2766,50 +2766,50 @@ ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o /* pass through b/c Annex A/c need following settings */ case DRX_STANDARD_ITU_B: rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_FCT_USAGE__A, FEC_OC_FCT_USAGE__PRE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_TMD_CTL_UPD_RATE__A, FEC_OC_TMD_CTL_UPD_RATE__PRE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_TMD_INT_UPD_RATE__A, 5, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_AVR_PARM_A__A, FEC_OC_AVR_PARM_A__PRE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_AVR_PARM_B__A, FEC_OC_AVR_PARM_B__PRE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } if (cfg_data->static_clk == true) { rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_RCN_GAIN__A, 0xD, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } else { rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_RCN_GAIN__A, FEC_OC_RCN_GAIN__PRE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_SNC_LWM__A, 2, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_SNC_HWM__A, 12, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -2820,12 +2820,12 @@ ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o /* Check insertion of the Reed-Solomon parity bytes */ rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_OC_MODE__A, &fec_oc_reg_mode, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -2848,7 +2848,7 @@ ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o rcn_rate = 0x005F64D4; break; default: - return DRX_STS_ERROR; + return -EIO; } break; case DRX_STANDARD_ITU_A: @@ -2861,7 +2861,7 @@ ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o 188; break; default: - return DRX_STS_ERROR; + return -EIO; } /* ext_attr->standard */ } else { /* insert_rs_byte == false */ @@ -2883,7 +2883,7 @@ ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o rcn_rate = 0x005AEC1A; break; default: - return DRX_STS_ERROR; + return -EIO; } break; case DRX_STANDARD_ITU_A: @@ -2896,7 +2896,7 @@ ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o 204; break; default: - return DRX_STS_ERROR; + return -EIO; } /* ext_attr->standard */ } @@ -2972,7 +2972,7 @@ ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o fec_oc_dto_burst_len = 204; break; default: - return DRX_STS_ERROR; + return -EIO; } bit_rate = common_attr->sys_clock_freq * 1000 / (fec_oc_dto_period + @@ -2981,70 +2981,70 @@ ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o frac28(bit_rate, common_attr->sys_clock_freq * 1000); dto_rate >>= 3; rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_DTO_RATE_HI__A, (u16)((dto_rate >> 16) & FEC_OC_DTO_RATE_HI__M), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_DTO_RATE_LO__A, (u16)(dto_rate & FEC_OC_DTO_RATE_LO_RATE_LO__M), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M | FEC_OC_DTO_MODE_OFFSET_ENABLE__M, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_FCT_MODE__A, FEC_OC_FCT_MODE_RAT_ENA__M | FEC_OC_FCT_MODE_VIRT_ENA__M, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_DTO_BURST_LEN__A, fec_oc_dto_burst_len, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } if (ext_attr->mpeg_output_clock_rate != DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO) fec_oc_dto_period = ext_attr->mpeg_output_clock_rate - 1; rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } else { /* Dynamic mode */ rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_FCT_MODE__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } rc = DRXJ_DAP.write_reg32func(dev_addr, FEC_OC_RCN_CTL_RATE_LO__A, rcn_rate, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Write appropriate registers with requested configuration */ rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_MODE__A, fec_oc_reg_mode, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_IPR_INVERT__A, fec_oc_reg_ipr_invert, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -3052,28 +3052,28 @@ ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o /* enabling for both parallel and serial now */ /* Write magic word to enable pdr reg write */ rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Set MPEG TS pads to outputmode */ rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MSTRT_CFG__A, 0x0013, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MERR_CFG__A, 0x0013, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MCLK_CFG__A, MPEG_OUTPUT_CLK_DRIVE_STRENGTH << SIO_PDR_MCLK_CFG_DRIVE__B | 0x03 << SIO_PDR_MCLK_CFG_MODE__B, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MVAL_CFG__A, 0x0013, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -3081,7 +3081,7 @@ ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH << SIO_PDR_MD0_CFG_DRIVE__B | 0x03 << SIO_PDR_MD0_CFG_MODE__B; rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD0_CFG__A, sio_pdr_md_cfg, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -3091,171 +3091,171 @@ ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o SIO_PDR_MD0_CFG_DRIVE__B | 0x03 << SIO_PDR_MD0_CFG_MODE__B; rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD0_CFG__A, sio_pdr_md_cfg, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD1_CFG__A, sio_pdr_md_cfg, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD2_CFG__A, sio_pdr_md_cfg, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD3_CFG__A, sio_pdr_md_cfg, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD4_CFG__A, sio_pdr_md_cfg, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD5_CFG__A, sio_pdr_md_cfg, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD6_CFG__A, sio_pdr_md_cfg, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD7_CFG__A, sio_pdr_md_cfg, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } else { /* MPEG data output is serial -> set MD1 to MD7 to tri-state */ rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD1_CFG__A, 0x0000, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD2_CFG__A, 0x0000, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD3_CFG__A, 0x0000, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD4_CFG__A, 0x0000, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD5_CFG__A, 0x0000, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD6_CFG__A, 0x0000, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD7_CFG__A, 0x0000, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } /* Enable Monitor Bus output over MPEG pads and ctl input */ rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MON_CFG__A, 0x0000, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Write nomagic word to enable pdr reg write */ rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } else { /* Write magic word to enable pdr reg write */ rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Set MPEG TS pads to inputmode */ rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MSTRT_CFG__A, 0x0000, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MERR_CFG__A, 0x0000, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MCLK_CFG__A, 0x0000, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MVAL_CFG__A, 0x0000, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD0_CFG__A, 0x0000, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD1_CFG__A, 0x0000, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD2_CFG__A, 0x0000, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD3_CFG__A, 0x0000, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD4_CFG__A, 0x0000, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD5_CFG__A, 0x0000, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD6_CFG__A, 0x0000, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD7_CFG__A, 0x0000, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Enable Monitor Bus output over MPEG pads and ctl input */ rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MON_CFG__A, 0x0000, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Write nomagic word to enable pdr reg write */ rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -3273,9 +3273,9 @@ ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o common_attr->mpeg_cfg.static_clk = cfg_data->static_clk; common_attr->mpeg_cfg.bitrate = cfg_data->bitrate; - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*----------------------------------------------------------------------------*/ @@ -3302,7 +3302,7 @@ ctrl_get_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o u32 data64lo = 0; if (cfg_data == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; dev_addr = demod->my_i2c_dev_addr; common_attr = demod->my_common_attr; @@ -3319,13 +3319,13 @@ ctrl_get_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o cfg_data->bitrate = 0; rc = ctrl_lock_status(demod, &lock_status); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } if ((lock_status == DRX_LOCKED)) { rc = DRXJ_DAP.read_reg32func(dev_addr, FEC_OC_RCN_DYN_RATE_LO__A, &rate_reg, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -3335,9 +3335,9 @@ ctrl_get_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o cfg_data->bitrate = (data64hi << 7) | (data64lo >> 25); } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*----------------------------------------------------------------------------*/ @@ -3370,17 +3370,17 @@ static int set_mpegtei_handling(struct drx_demod_instance *demod) ext_attr = (struct drxj_data *) demod->my_ext_attr; rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_OC_DPR_MODE__A, &fec_oc_dpr_mode, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_OC_EMS_MODE__A, &fec_oc_ems_mode, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -3400,24 +3400,24 @@ static int set_mpegtei_handling(struct drx_demod_instance *demod) } rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_DPR_MODE__A, fec_oc_dpr_mode, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_SNC_MODE__A, fec_oc_snc_mode, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_EMS_MODE__A, fec_oc_ems_mode, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*----------------------------------------------------------------------------*/ @@ -3441,7 +3441,7 @@ static int bit_reverse_mpeg_output(struct drx_demod_instance *demod) ext_attr = (struct drxj_data *) demod->my_ext_attr; rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -3453,14 +3453,14 @@ static int bit_reverse_mpeg_output(struct drx_demod_instance *demod) fec_oc_ipr_mode |= FEC_OC_IPR_MODE_REVERSE_ORDER__M; rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*----------------------------------------------------------------------------*/ @@ -3484,15 +3484,15 @@ static int set_mpeg_output_clock_rate(struct drx_demod_instance *demod) if (ext_attr->mpeg_output_clock_rate != DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO) { rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_DTO_PERIOD__A, ext_attr->mpeg_output_clock_rate - 1, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*----------------------------------------------------------------------------*/ @@ -3520,7 +3520,7 @@ static int set_mpeg_start_width(struct drx_demod_instance *demod) if ((common_attr->mpeg_cfg.static_clk == true) && (common_attr->mpeg_cfg.enable_parallel == false)) { rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_OC_COMM_MB__A, &fec_oc_comm_mb, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -3528,15 +3528,15 @@ static int set_mpeg_start_width(struct drx_demod_instance *demod) if (ext_attr->mpeg_start_width == DRXJ_MPEG_START_WIDTH_8CLKCYC) fec_oc_comm_mb |= FEC_OC_COMM_MB_CTL_ON; rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_COMM_MB__A, fec_oc_comm_mb, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*----------------------------------------------------------------------------*/ @@ -3559,7 +3559,7 @@ ctrl_set_cfg_mpeg_output_misc(struct drx_demod_instance *demod, int rc; if (cfg_data == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; ext_attr = demod->my_ext_attr; @@ -3578,29 +3578,29 @@ ctrl_set_cfg_mpeg_output_misc(struct drx_demod_instance *demod, ext_attr->mpeg_start_width = cfg_data->mpeg_start_width; /* Don't care what the active standard is, activate setting immediatly */ rc = set_mpegtei_handling(demod); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = bit_reverse_mpeg_output(demod); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = set_mpeg_output_clock_rate(demod); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = set_mpeg_start_width(demod); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*----------------------------------------------------------------------------*/ @@ -3626,7 +3626,7 @@ ctrl_get_cfg_mpeg_output_misc(struct drx_demod_instance *demod, u16 data = 0; if (cfg_data == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; ext_attr = (struct drxj_data *) demod->my_ext_attr; cfg_data->disable_tei_handling = ext_attr->disable_te_ihandling; @@ -3636,7 +3636,7 @@ ctrl_get_cfg_mpeg_output_misc(struct drx_demod_instance *demod, cfg_data->mpeg_output_clock_rate = ext_attr->mpeg_output_clock_rate; } else { rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, FEC_OC_DTO_PERIOD__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -3644,9 +3644,9 @@ ctrl_get_cfg_mpeg_output_misc(struct drx_demod_instance *demod, (enum drxj_mpeg_output_clock_rate) (data + 1); } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*----------------------------------------------------------------------------*/ @@ -3670,20 +3670,20 @@ ctrl_get_cfg_hw_cfg(struct drx_demod_instance *demod, struct drxj_cfg_hw_cfg *cf u16 data = 0; if (cfg_data == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SIO_PDR_OHW_CFG__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -3691,9 +3691,9 @@ ctrl_get_cfg_hw_cfg(struct drx_demod_instance *demod, struct drxj_cfg_hw_cfg *cf cfg_data->i2c_speed = (enum drxji2c_speed) ((data >> 6) & 0x1); cfg_data->xtal_freq = (enum drxj_xtal_freq) (data & 0x3); - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*----------------------------------------------------------------------------*/ @@ -3716,13 +3716,13 @@ static int ctrl_set_uio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg int rc; if ((uio_cfg == NULL) || (demod == NULL)) - return DRX_STS_INVALID_ARG; + return -EINVAL; ext_attr = (struct drxj_data *) demod->my_ext_attr; /* Write magic word to enable pdr reg write */ rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -3731,7 +3731,7 @@ static int ctrl_set_uio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg case DRX_UIO1: /* DRX_UIO1: SMA_TX UIO-1 */ if (!ext_attr->has_smatx) - return DRX_STS_ERROR; + return -EIO; switch (uio_cfg->mode) { case DRX_UIO_MODE_FIRMWARE_SMA: /* falltrough */ case DRX_UIO_MODE_FIRMWARE_SAW: /* falltrough */ @@ -3742,20 +3742,20 @@ static int ctrl_set_uio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg ext_attr->uio_sma_tx_mode = uio_cfg->mode; /* pad configuration register is set 0 - input mode */ rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } break; default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } /* switch ( uio_cfg->mode ) */ break; /*====================================================================*/ case DRX_UIO2: /* DRX_UIO2: SMA_RX UIO-2 */ if (!ext_attr->has_smarx) - return DRX_STS_ERROR; + return -EIO; switch (uio_cfg->mode) { case DRX_UIO_MODE_FIRMWARE0: /* falltrough */ case DRX_UIO_MODE_READWRITE: @@ -3765,13 +3765,13 @@ static int ctrl_set_uio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg ext_attr->uio_sma_rx_mode = uio_cfg->mode; /* pad configuration register is set 0 - input mode */ rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } break; default: - return DRX_STS_INVALID_ARG; + return -EINVAL; break; } /* switch ( uio_cfg->mode ) */ break; @@ -3779,7 +3779,7 @@ static int ctrl_set_uio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg case DRX_UIO3: /* DRX_UIO3: GPIO UIO-3 */ if (!ext_attr->has_gpio) - return DRX_STS_ERROR; + return -EIO; switch (uio_cfg->mode) { case DRX_UIO_MODE_FIRMWARE0: /* falltrough */ case DRX_UIO_MODE_READWRITE: @@ -3789,13 +3789,13 @@ static int ctrl_set_uio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg ext_attr->uio_gpio_mode = uio_cfg->mode; /* pad configuration register is set 0 - input mode */ rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } break; default: - return DRX_STS_INVALID_ARG; + return -EINVAL; break; } /* switch ( uio_cfg->mode ) */ break; @@ -3803,7 +3803,7 @@ static int ctrl_set_uio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg case DRX_UIO4: /* DRX_UIO4: IRQN UIO-4 */ if (!ext_attr->has_irqn) - return DRX_STS_ERROR; + return -EIO; switch (uio_cfg->mode) { case DRX_UIO_MODE_READWRITE: ext_attr->uio_irqn_mode = uio_cfg->mode; @@ -3811,7 +3811,7 @@ static int ctrl_set_uio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg case DRX_UIO_MODE_DISABLE: /* pad configuration register is set 0 - input mode */ rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -3819,25 +3819,25 @@ static int ctrl_set_uio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg break; case DRX_UIO_MODE_FIRMWARE0: /* falltrough */ default: - return DRX_STS_INVALID_ARG; + return -EINVAL; break; } /* switch ( uio_cfg->mode ) */ break; /*====================================================================*/ default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } /* switch ( uio_cfg->uio ) */ /* Write magic word to disable pdr reg write */ rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -3868,17 +3868,17 @@ static int ctrl_getuio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg * uio_available[DRX_UIO4] = &ext_attr->has_irqn; if (uio_cfg == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; if ((uio_cfg->uio > DRX_UIO4) || (uio_cfg->uio < DRX_UIO1)) - return DRX_STS_INVALID_ARG; + return -EINVAL; if (!*uio_available[uio_cfg->uio]) - return DRX_STS_ERROR; + return -EIO; uio_cfg->mode = *uio_mode[uio_cfg->uio]; - return DRX_STS_OK; + return 0; } /** @@ -3897,13 +3897,13 @@ ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data) u16 value = 0; if ((uio_data == NULL) || (demod == NULL)) - return DRX_STS_INVALID_ARG; + return -EINVAL; ext_attr = (struct drxj_data *) demod->my_ext_attr; /* Write magic word to enable pdr reg write */ rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -3912,10 +3912,10 @@ ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data) case DRX_UIO1: /* DRX_UIO1: SMA_TX UIO-1 */ if (!ext_attr->has_smatx) - return DRX_STS_ERROR; + return -EIO; if ((ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_READWRITE) && (ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_FIRMWARE_SAW)) { - return DRX_STS_ERROR; + return -EIO; } pin_cfg_value = 0; /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ @@ -3925,14 +3925,14 @@ ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data) /* write to io pad configuration register - output mode */ rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, pin_cfg_value, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* use corresponding bit in io data output registar */ rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -3943,7 +3943,7 @@ ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data) /* write back to io data output register */ rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -3952,9 +3952,9 @@ ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data) case DRX_UIO2: /* DRX_UIO2: SMA_RX UIO-2 */ if (!ext_attr->has_smarx) - return DRX_STS_ERROR; + return -EIO; if (ext_attr->uio_sma_rx_mode != DRX_UIO_MODE_READWRITE) - return DRX_STS_ERROR; + return -EIO; pin_cfg_value = 0; /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ @@ -3964,14 +3964,14 @@ ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data) /* write to io pad configuration register - output mode */ rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, pin_cfg_value, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* use corresponding bit in io data output registar */ rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -3982,7 +3982,7 @@ ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data) /* write back to io data output register */ rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -3991,9 +3991,9 @@ ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data) case DRX_UIO3: /* DRX_UIO3: ASEL UIO-3 */ if (!ext_attr->has_gpio) - return DRX_STS_ERROR; + return -EIO; if (ext_attr->uio_gpio_mode != DRX_UIO_MODE_READWRITE) - return DRX_STS_ERROR; + return -EIO; pin_cfg_value = 0; /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ @@ -4003,14 +4003,14 @@ ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data) /* write to io pad configuration register - output mode */ rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, pin_cfg_value, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* use corresponding bit in io data output registar */ rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, &value, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -4021,7 +4021,7 @@ ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data) /* write back to io data output register */ rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, value, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -4030,10 +4030,10 @@ ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data) case DRX_UIO4: /* DRX_UIO4: IRQN UIO-4 */ if (!ext_attr->has_irqn) - return DRX_STS_ERROR; + return -EIO; if (ext_attr->uio_irqn_mode != DRX_UIO_MODE_READWRITE) - return DRX_STS_ERROR; + return -EIO; pin_cfg_value = 0; /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ @@ -4043,14 +4043,14 @@ ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data) /* write to io pad configuration register - output mode */ rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, pin_cfg_value, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* use corresponding bit in io data output registar */ rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -4061,26 +4061,26 @@ ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data) /* write back to io data output register */ rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } break; /*=====================================================================*/ default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } /* switch ( uio_data->uio ) */ /* Write magic word to disable pdr reg write */ rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /** @@ -4098,13 +4098,13 @@ static int ctrl_uio_read(struct drx_demod_instance *demod, struct drxuio_data *u u16 value = 0; if ((uio_data == NULL) || (demod == NULL)) - return DRX_STS_INVALID_ARG; + return -EINVAL; ext_attr = (struct drxj_data *) demod->my_ext_attr; /* Write magic word to enable pdr reg write */ rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -4113,10 +4113,10 @@ static int ctrl_uio_read(struct drx_demod_instance *demod, struct drxuio_data *u case DRX_UIO1: /* DRX_UIO1: SMA_TX UIO-1 */ if (!ext_attr->has_smatx) - return DRX_STS_ERROR; + return -EIO; if (ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_READWRITE) - return DRX_STS_ERROR; + return -EIO; pin_cfg_value = 0; /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ @@ -4126,13 +4126,13 @@ static int ctrl_uio_read(struct drx_demod_instance *demod, struct drxuio_data *u /* write to io pad configuration register - input mode */ rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, pin_cfg_value, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SIO_PDR_UIO_IN_LO__A, &value, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -4146,10 +4146,10 @@ static int ctrl_uio_read(struct drx_demod_instance *demod, struct drxuio_data *u case DRX_UIO2: /* DRX_UIO2: SMA_RX UIO-2 */ if (!ext_attr->has_smarx) - return DRX_STS_ERROR; + return -EIO; if (ext_attr->uio_sma_rx_mode != DRX_UIO_MODE_READWRITE) - return DRX_STS_ERROR; + return -EIO; pin_cfg_value = 0; /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ @@ -4159,13 +4159,13 @@ static int ctrl_uio_read(struct drx_demod_instance *demod, struct drxuio_data *u /* write to io pad configuration register - input mode */ rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, pin_cfg_value, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SIO_PDR_UIO_IN_LO__A, &value, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -4180,10 +4180,10 @@ static int ctrl_uio_read(struct drx_demod_instance *demod, struct drxuio_data *u case DRX_UIO3: /* DRX_UIO3: GPIO UIO-3 */ if (!ext_attr->has_gpio) - return DRX_STS_ERROR; + return -EIO; if (ext_attr->uio_gpio_mode != DRX_UIO_MODE_READWRITE) - return DRX_STS_ERROR; + return -EIO; pin_cfg_value = 0; /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ @@ -4193,14 +4193,14 @@ static int ctrl_uio_read(struct drx_demod_instance *demod, struct drxuio_data *u /* write to io pad configuration register - input mode */ rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, pin_cfg_value, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* read io input data registar */ rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SIO_PDR_UIO_IN_HI__A, &value, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -4214,10 +4214,10 @@ static int ctrl_uio_read(struct drx_demod_instance *demod, struct drxuio_data *u case DRX_UIO4: /* DRX_UIO4: IRQN UIO-4 */ if (!ext_attr->has_irqn) - return DRX_STS_ERROR; + return -EIO; if (ext_attr->uio_irqn_mode != DRX_UIO_MODE_READWRITE) - return DRX_STS_ERROR; + return -EIO; pin_cfg_value = 0; /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ @@ -4227,14 +4227,14 @@ static int ctrl_uio_read(struct drx_demod_instance *demod, struct drxuio_data *u /* write to io pad configuration register - input mode */ rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, pin_cfg_value, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* read io input data registar */ rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SIO_PDR_UIO_IN_LO__A, &value, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -4246,19 +4246,19 @@ static int ctrl_uio_read(struct drx_demod_instance *demod, struct drxuio_data *u break; /*====================================================================*/ default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } /* switch ( uio_data->uio ) */ /* Write magic word to disable pdr reg write */ rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*---------------------------------------------------------------------------*/ @@ -4284,7 +4284,7 @@ ctrl_i2c_bridge(struct drx_demod_instance *demod, bool *bridge_closed) /* check arguments */ if (bridge_closed == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; hi_cmd.cmd = SIO_HI_RA_RAM_CMD_BRDCTRL; hi_cmd.param1 = SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY; @@ -4323,25 +4323,25 @@ static int smart_ant_init(struct drx_demod_instance *demod) /* Write magic word to enable pdr reg write */ rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* init smart antenna */ rc = DRXJ_DAP.read_reg16func(dev_addr, SIO_SA_TX_COMMAND__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } if (ext_attr->smart_ant_inverted) { rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_SA_TX_COMMAND__A, (data | SIO_SA_TX_COMMAND_TX_INVERT__M) | SIO_SA_TX_COMMAND_TX_ENABLE__M, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } else { rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_SA_TX_COMMAND__A, (data & (~SIO_SA_TX_COMMAND_TX_INVERT__M)) | SIO_SA_TX_COMMAND_TX_ENABLE__M, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -4349,31 +4349,31 @@ static int smart_ant_init(struct drx_demod_instance *demod) /* config SMA_TX pin to smart antenna mode */ rc = ctrl_set_uio_cfg(demod, &uio_cfg); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0x13, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_GPIO_FNC__A, 0x03, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Write magic word to disable pdr reg write */ rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /** @@ -4398,12 +4398,12 @@ ctrl_set_cfg_smart_ant(struct drx_demod_instance *demod, struct drxj_cfg_smart_a /* check arguments */ if (smart_ant == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; if (bit_inverted != ext_attr->smart_ant_inverted || ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_FIRMWARE_SMA) { rc = smart_ant_init(demod); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -4412,7 +4412,7 @@ ctrl_set_cfg_smart_ant(struct drx_demod_instance *demod, struct drxj_cfg_smart_a /* Write magic word to enable pdr reg write */ rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -4427,40 +4427,40 @@ ctrl_set_cfg_smart_ant(struct drx_demod_instance *demod, struct drxj_cfg_smart_a start_time = drxbsp_hst_clock(); do { rc = DRXJ_DAP.read_reg16func(dev_addr, SIO_SA_TX_STATUS__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } while ((data & SIO_SA_TX_STATUS_BUSY__M) && ((drxbsp_hst_clock() - start_time) < DRXJ_MAX_WAITTIME)); if (data & SIO_SA_TX_STATUS_BUSY__M) - return DRX_STS_ERROR; + return -EIO; /* write to smart antenna configuration register */ rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_SA_TX_DATA0__A, 0x9200 | ((smart_ant->ctrl_data & 0x0001) << 8) | ((smart_ant->ctrl_data & 0x0002) << 10) | ((smart_ant->ctrl_data & 0x0004) << 12), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_SA_TX_DATA1__A, 0x4924 | ((smart_ant->ctrl_data & 0x0008) >> 2) | ((smart_ant->ctrl_data & 0x0010)) | ((smart_ant->ctrl_data & 0x0020) << 2) | ((smart_ant->ctrl_data & 0x0040) << 4) | ((smart_ant->ctrl_data & 0x0080) << 6), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_SA_TX_DATA2__A, 0x2492 | ((smart_ant->ctrl_data & 0x0100) >> 8) | ((smart_ant->ctrl_data & 0x0200) >> 6) | ((smart_ant->ctrl_data & 0x0400) >> 4) | ((smart_ant->ctrl_data & 0x0800) >> 2) | ((smart_ant->ctrl_data & 0x1000)) | ((smart_ant->ctrl_data & 0x2000) << 2), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_SA_TX_DATA3__A, 0xff8d, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* trigger the sending */ rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_SA_TX_LENGTH__A, 56, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -4473,18 +4473,18 @@ ctrl_set_cfg_smart_ant(struct drx_demod_instance *demod, struct drxj_cfg_smart_a WR16( dev_addr, SIO_SA_TX_COMMAND__A, data & (~SIO_SA_TX_COMMAND_TX_ENABLE__M) ); */ default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } /* Write magic word to enable pdr reg write */ rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } static int scu_command(struct i2c_device_addr *dev_addr, struct drxjscu_cmd *cmd) @@ -4495,45 +4495,45 @@ static int scu_command(struct i2c_device_addr *dev_addr, struct drxjscu_cmd *cmd /* Check param */ if (cmd == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; /* Wait until SCU command interface is ready to receive command */ rc = DRXJ_DAP.read_reg16func(dev_addr, SCU_RAM_COMMAND__A, &cur_cmd, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } if (cur_cmd != DRX_SCU_READY) - return DRX_STS_ERROR; + return -EIO; switch (cmd->parameter_len) { case 5: rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_PARAM_4__A, *(cmd->parameter + 4), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* fallthrough */ case 4: rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_PARAM_3__A, *(cmd->parameter + 3), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* fallthrough */ case 3: rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_PARAM_2__A, *(cmd->parameter + 2), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* fallthrough */ case 2: rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_PARAM_1__A, *(cmd->parameter + 1), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* fallthrough */ case 1: rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_PARAM_0__A, *(cmd->parameter + 0), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* fallthrough */ @@ -4542,10 +4542,10 @@ static int scu_command(struct i2c_device_addr *dev_addr, struct drxjscu_cmd *cmd break; default: /* this number of parameters is not supported */ - return DRX_STS_ERROR; + return -EIO; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_COMMAND__A, cmd->command, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -4554,7 +4554,7 @@ static int scu_command(struct i2c_device_addr *dev_addr, struct drxjscu_cmd *cmd start_time = drxbsp_hst_clock(); do { rc = DRXJ_DAP.read_reg16func(dev_addr, SCU_RAM_COMMAND__A, &cur_cmd, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -4562,7 +4562,7 @@ static int scu_command(struct i2c_device_addr *dev_addr, struct drxjscu_cmd *cmd && ((drxbsp_hst_clock() - start_time) < DRXJ_MAX_WAITTIME)); if (cur_cmd != DRX_SCU_READY) - return DRX_STS_ERROR; + return -EIO; /* read results */ if ((cmd->result_len > 0) && (cmd->result != NULL)) { @@ -4571,25 +4571,25 @@ static int scu_command(struct i2c_device_addr *dev_addr, struct drxjscu_cmd *cmd switch (cmd->result_len) { case 4: rc = DRXJ_DAP.read_reg16func(dev_addr, SCU_RAM_PARAM_3__A, cmd->result + 3, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* fallthrough */ case 3: rc = DRXJ_DAP.read_reg16func(dev_addr, SCU_RAM_PARAM_2__A, cmd->result + 2, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* fallthrough */ case 2: rc = DRXJ_DAP.read_reg16func(dev_addr, SCU_RAM_PARAM_1__A, cmd->result + 1, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* fallthrough */ case 1: rc = DRXJ_DAP.read_reg16func(dev_addr, SCU_RAM_PARAM_0__A, cmd->result + 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* fallthrough */ @@ -4598,7 +4598,7 @@ static int scu_command(struct i2c_device_addr *dev_addr, struct drxjscu_cmd *cmd break; default: /* this number of parameters is not supported */ - return DRX_STS_ERROR; + return -EIO; } /* Check if an error was reported by SCU */ @@ -4610,19 +4610,19 @@ static int scu_command(struct i2c_device_addr *dev_addr, struct drxjscu_cmd *cmd || (err == (s16) SCU_RAM_PARAM_0_RESULT_INVPAR) || (err == (s16) SCU_RAM_PARAM_0_RESULT_SIZE) ) { - return DRX_STS_INVALID_ARG; + return -EINVAL; } /* here it is assumed that negative means error, and positive no error */ else if (err < 0) - return DRX_STS_ERROR; + return -EIO; else - return DRX_STS_OK; + return 0; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /** @@ -4633,8 +4633,8 @@ rw_error: * \param datasize size of data buffer in bytes * \param data pointer to data buffer * \return int -* \retval DRX_STS_OK Succes -* \retval DRX_STS_ERROR Timeout, I2C error, illegal bank +* \retval 0 Succes +* \retval -EIO Timeout, I2C error, illegal bank * */ #define ADDR_AT_SCU_SPACE(x) ((x - 0x82E000) * 2) @@ -4649,7 +4649,7 @@ int drxj_dap_scu_atomic_read_write_block(struct i2c_device_addr *dev_addr, u32 a /* Parameter check */ if (!data || !dev_addr || (datasize % 2) || ((datasize / 2) > 16)) - return DRX_STS_INVALID_ARG; + return -EINVAL; set_param_parameters[1] = (u16) ADDR_AT_SCU_SPACE(addr); if (read_flag) { /* read */ @@ -4674,7 +4674,7 @@ int drxj_dap_scu_atomic_read_write_block(struct i2c_device_addr *dev_addr, u32 a scu_cmd.result = cmd_result; scu_cmd.parameter = set_param_parameters; rc = scu_command(dev_addr, &scu_cmd); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -4688,10 +4688,10 @@ int drxj_dap_scu_atomic_read_write_block(struct i2c_device_addr *dev_addr, u32 a } } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } @@ -4707,11 +4707,11 @@ int drxj_dap_scu_atomic_read_reg16(struct i2c_device_addr *dev_addr, u16 *data, u32 flags) { u8 buf[2]; - int rc = DRX_STS_ERROR; + int rc = -EIO; u16 word = 0; if (!data) - return DRX_STS_INVALID_ARG; + return -EINVAL; rc = drxj_dap_scu_atomic_read_write_block(dev_addr, addr, 2, buf, true); if (rc < 0) @@ -4735,7 +4735,7 @@ int drxj_dap_scu_atomic_write_reg16(struct i2c_device_addr *dev_addr, u16 data, u32 flags) { u8 buf[2]; - int rc = DRX_STS_ERROR; + int rc = -EIO; buf[0] = (u8) (data & 0xff); buf[1] = (u8) ((data >> 8) & 0xff); @@ -4748,7 +4748,7 @@ int drxj_dap_scu_atomic_write_reg16(struct i2c_device_addr *dev_addr, static int ctrl_i2c_write_read(struct drx_demod_instance *demod, struct drxi2c_data *i2c_data) { - return DRX_STS_FUNC_NOT_AVAILABLE; + return -ENOTSUPP; } /* -------------------------------------------------------------------------- */ @@ -4757,8 +4757,8 @@ ctrl_i2c_write_read(struct drx_demod_instance *demod, struct drxi2c_data *i2c_da * \param demod demod instance * \param count (returned) count * \return int. -* \retval DRX_STS_OK Success -* \retval DRX_STS_ERROR Failure: I2C error +* \retval 0 Success +* \retval -EIO Failure: I2C error * */ static int adc_sync_measurement(struct drx_demod_instance *demod, u16 *count) @@ -4771,57 +4771,57 @@ static int adc_sync_measurement(struct drx_demod_instance *demod, u16 *count) /* Start measurement */ rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_START_LOCK__A, 1, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Wait at least 3*128*(1/sysclk) <<< 1 millisec */ rc = drxbsp_hst_sleep(1); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } *count = 0; rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_PHASE0__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } if (data == 127) *count = *count + 1; rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_PHASE1__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } if (data == 127) *count = *count + 1; rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_PHASE2__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } if (data == 127) *count = *count + 1; - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /** * \brief Synchronize analog and digital clock domains * \param demod demod instance * \return int. -* \retval DRX_STS_OK Success -* \retval DRX_STS_ERROR Failure: I2C error or failure to synchronize +* \retval 0 Success +* \retval -EIO Failure: I2C error or failure to synchronize * * An IQM reset will also reset the results of this synchronization. * After an IQM reset this routine needs to be called again. @@ -4837,7 +4837,7 @@ static int adc_synchronization(struct drx_demod_instance *demod) dev_addr = demod->my_i2c_dev_addr; rc = adc_sync_measurement(demod, &count); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -4847,20 +4847,20 @@ static int adc_synchronization(struct drx_demod_instance *demod) u16 clk_neg = 0; rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_CLKNEG__A, &clk_neg, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } clk_neg ^= IQM_AF_CLKNEG_CLKNEGDATA__M; rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_CLKNEG__A, clk_neg, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = adc_sync_measurement(demod, &count); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -4868,11 +4868,11 @@ static int adc_synchronization(struct drx_demod_instance *demod) /* TODO: implement fallback scenarios */ if (count < 2) - return DRX_STS_ERROR; + return -EIO; - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /** @@ -4889,7 +4889,7 @@ static int iqm_set_af(struct drx_demod_instance *demod, bool active) /* Configure IQM */ rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_STDBY__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -4898,14 +4898,14 @@ static int iqm_set_af(struct drx_demod_instance *demod, bool active) else data |= (IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE | IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE | IQM_AF_STDBY_STDBY_PD_A2_ACTIVE | IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE | IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE); rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_STDBY__A, data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /* -------------------------------------------------------------------------- */ @@ -4926,14 +4926,14 @@ ctrl_set_cfg_pdr_safe_mode(struct drx_demod_instance *demod, bool *enable) int rc; if (enable == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; /* Write magic word to enable pdr reg write */ rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -4943,62 +4943,62 @@ ctrl_set_cfg_pdr_safe_mode(struct drx_demod_instance *demod, bool *enable) /* MPEG pins to input */ rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MSTRT_CFG__A, DRXJ_PIN_SAFE_MODE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MERR_CFG__A, DRXJ_PIN_SAFE_MODE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MCLK_CFG__A, DRXJ_PIN_SAFE_MODE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MVAL_CFG__A, DRXJ_PIN_SAFE_MODE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD0_CFG__A, DRXJ_PIN_SAFE_MODE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD1_CFG__A, DRXJ_PIN_SAFE_MODE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD2_CFG__A, DRXJ_PIN_SAFE_MODE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD3_CFG__A, DRXJ_PIN_SAFE_MODE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD4_CFG__A, DRXJ_PIN_SAFE_MODE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD5_CFG__A, DRXJ_PIN_SAFE_MODE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD6_CFG__A, DRXJ_PIN_SAFE_MODE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD7_CFG__A, DRXJ_PIN_SAFE_MODE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -5006,17 +5006,17 @@ ctrl_set_cfg_pdr_safe_mode(struct drx_demod_instance *demod, bool *enable) /* PD_I2C_SDA2 Bridge off, Port2 Inactive PD_I2C_SCL2 Bridge off, Port2 Inactive */ rc = ctrl_i2c_bridge(demod, &bridge_enabled); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_I2C_SDA2_CFG__A, DRXJ_PIN_SAFE_MODE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_I2C_SCL2_CFG__A, DRXJ_PIN_SAFE_MODE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -5026,42 +5026,42 @@ ctrl_set_cfg_pdr_safe_mode(struct drx_demod_instance *demod, bool *enable) PD_SMA_RX Store and set to input PD_SMA_TX Store and set to input */ rc = DRXJ_DAP.read_reg16func(dev_addr, SIO_PDR_GPIO_CFG__A, &ext_attr->pdr_safe_restore_val_gpio, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.read_reg16func(dev_addr, SIO_PDR_VSYNC_CFG__A, &ext_attr->pdr_safe_restore_val_v_sync, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.read_reg16func(dev_addr, SIO_PDR_SMA_RX_CFG__A, &ext_attr->pdr_safe_restore_val_sma_rx, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.read_reg16func(dev_addr, SIO_PDR_SMA_TX_CFG__A, &ext_attr->pdr_safe_restore_val_sma_tx, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_GPIO_CFG__A, DRXJ_PIN_SAFE_MODE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_VSYNC_CFG__A, DRXJ_PIN_SAFE_MODE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_SMA_RX_CFG__A, DRXJ_PIN_SAFE_MODE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_SMA_TX_CFG__A, DRXJ_PIN_SAFE_MODE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -5069,7 +5069,7 @@ ctrl_set_cfg_pdr_safe_mode(struct drx_demod_instance *demod, bool *enable) /* PD_RF_AGC Analog DAC outputs, cannot be set to input or tristate! PD_IF_AGC Analog DAC outputs, cannot be set to input or tristate! */ rc = iqm_set_af(demod, false); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -5077,7 +5077,7 @@ ctrl_set_cfg_pdr_safe_mode(struct drx_demod_instance *demod, bool *enable) /* PD_CVBS Analog DAC output, standby mode PD_SIF Analog DAC output, standby mode */ rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_STDBY__A, (ATV_TOP_STDBY_SIF_STDBY_STANDBY & (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE)), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -5086,17 +5086,17 @@ ctrl_set_cfg_pdr_safe_mode(struct drx_demod_instance *demod, bool *enable) PD_I2S_DA Input PD_I2S_WS Input */ rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_I2S_CL_CFG__A, DRXJ_PIN_SAFE_MODE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_I2S_DA_CFG__A, DRXJ_PIN_SAFE_MODE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_I2S_WS_CFG__A, DRXJ_PIN_SAFE_MODE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -5107,12 +5107,12 @@ ctrl_set_cfg_pdr_safe_mode(struct drx_demod_instance *demod, bool *enable) /* PD_I2C_SDA2 Port2 active PD_I2C_SCL2 Port2 active */ rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_I2C_SDA2_CFG__A, SIO_PDR_I2C_SDA2_CFG__PRE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_I2C_SCL2_CFG__A, SIO_PDR_I2C_SCL2_CFG__PRE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -5122,22 +5122,22 @@ ctrl_set_cfg_pdr_safe_mode(struct drx_demod_instance *demod, bool *enable) PD_SMA_RX Restore PD_SMA_TX Restore */ rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_GPIO_CFG__A, ext_attr->pdr_safe_restore_val_gpio, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_VSYNC_CFG__A, ext_attr->pdr_safe_restore_val_v_sync, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_SMA_RX_CFG__A, ext_attr->pdr_safe_restore_val_sma_rx, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_SMA_TX_CFG__A, ext_attr->pdr_safe_restore_val_sma_tx, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -5154,16 +5154,16 @@ ctrl_set_cfg_pdr_safe_mode(struct drx_demod_instance *demod, bool *enable) /* Write magic word to disable pdr reg write */ rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } ext_attr->pdr_safe_mode = *enable; - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /* -------------------------------------------------------------------------- */ @@ -5180,12 +5180,12 @@ ctrl_get_cfg_pdr_safe_mode(struct drx_demod_instance *demod, bool *enabled) struct drxj_data *ext_attr = (struct drxj_data *) NULL; if (enabled == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; ext_attr = (struct drxj_data *) demod->my_ext_attr; *enabled = ext_attr->pdr_safe_mode; - return DRX_STS_OK; + return 0; } /** @@ -5214,15 +5214,15 @@ static int ctrl_validate_u_code(struct drx_demod_instance *demod) (((mc_dev >> 16) & 0xFFF) != 0x393) && (((mc_dev >> 16) & 0xFFF) != 0x394)) { /* Microcode is marked for another device - error */ - return DRX_STS_INVALID_ARG; + return -EINVAL; } else if (mc_patch != 0) { /* Patch not allowed because there is no ROM */ - return DRX_STS_INVALID_ARG; + return -EINVAL; } } /* Everything else: OK */ - return DRX_STS_OK; + return 0; } /*============================================================================*/ @@ -5283,67 +5283,67 @@ static int init_agc(struct drx_demod_instance *demod) ingain_tgt_max = 16383; clp_ctrl_mode = 0; rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_CLP_SUM__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_CLP_CYCCNT__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_CLP_DIR_WD__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_CLP_DIR_STP__A, 1, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_SNS_SUM__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_SNS_CYCCNT__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_SNS_DIR_WD__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_SNS_DIR_STP__A, 1, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_INGAIN__A, 1024, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_VSB_AGC_POW_TGT__A, 22600, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, 13200, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -5366,71 +5366,71 @@ static int init_agc(struct drx_demod_instance *demod) ki_min = 0x0117; clp_ctrl_mode = 0; rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_CLP_SUM__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_CLP_CYCCNT__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_CLP_DIR_WD__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_CLP_DIR_STP__A, 1, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_SNS_SUM__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_SNS_CYCCNT__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_SNS_DIR_WD__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_SNS_DIR_STP__A, 1, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } p_agc_if_settings = &(ext_attr->qam_if_agc_cfg); p_agc_rf_settings = &(ext_attr->qam_rf_agc_cfg); rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, p_agc_if_settings->top, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.read_reg16func(dev_addr, SCU_RAM_AGC_KI__A, &agc_ki, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } agc_ki &= 0xf000; rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_KI__A, agc_ki, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -5452,7 +5452,7 @@ static int init_agc(struct drx_demod_instance *demod) p_agc_if_settings = &(ext_attr->atv_if_agc_cfg); p_agc_rf_settings = &(ext_attr->atv_rf_agc_cfg); rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, p_agc_if_settings->top, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -5475,7 +5475,7 @@ static int init_agc(struct drx_demod_instance *demod) sns_dir_to = (u16) (-9); clp_ctrl_mode = 1; rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, p_agc_if_settings->top, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -5496,144 +5496,144 @@ static int init_agc(struct drx_demod_instance *demod) p_agc_if_settings = &(ext_attr->atv_if_agc_cfg); p_agc_rf_settings = &(ext_attr->atv_rf_agc_cfg); rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, p_agc_if_settings->top, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } break; #endif default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } /* for new AGC interface */ rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_if_settings->top, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_INGAIN__A, p_agc_if_settings->top, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Gain fed from inner to outer AGC */ rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, if_iaccu_hi_tgt_min, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_IF_IACCU_HI__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* set to p_agc_settings->top before */ rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_IF_IACCU_LO__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_RF_IACCU_LO__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_RF_MAX__A, 32767, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, ki_innergain_min, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_KI_CYCLEN__A, 500, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_SNS_CYCLEN__A, 500, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_KI_MIN__A, ki_min, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_KI_MAX__A, ki_max, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_KI_RED__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_CLP_SUM_MIN__A, 8, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_CLP_CYCLEN__A, 500, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_SNS_SUM_MIN__A, 8, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, 50, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -5647,33 +5647,33 @@ static int init_agc(struct drx_demod_instance *demod) agc_rf = 0x87ff - agc_rf; rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_AGC_RF__A, agc_rf, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_AGC_IF__A, agc_if, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Set/restore Ki DGAIN factor */ rc = DRXJ_DAP.read_reg16func(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } data &= ~SCU_RAM_AGC_KI_DGAIN__M; data |= (agc_ki_dgain << SCU_RAM_AGC_KI_DGAIN__B); rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_KI__A, data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /** @@ -5732,7 +5732,7 @@ set_frequency(struct drx_demod_instance *demod, select_pos_image = false; break; default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } intermediate_freq = demod->my_common_attr->intermediate_freq; sampling_frequency = demod->my_common_attr->sys_clock_freq / 3; @@ -5761,16 +5761,16 @@ set_frequency(struct drx_demod_instance *demod, /* Program frequency shifter with tuner offset compensation */ /* frequency_shift += tuner_freq_offset; TODO */ rc = DRXJ_DAP.write_reg32func(dev_addr, IQM_FS_RATE_OFS_LO__A, iqm_fs_rate_ofs, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } ext_attr->iqm_fs_rate_ofs = iqm_fs_rate_ofs; ext_attr->pos_image = (bool) (rf_mirror ^ tuner_mirror ^ select_pos_image); - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /** @@ -5779,9 +5779,9 @@ rw_error: * \param demod Pointer to demod instance * \param u16-t Pointer to signal strength data; range 0, .. , 100. * \return int. -* \retval DRX_STS_OK sig_strength contains valid data. -* \retval DRX_STS_INVALID_ARG sig_strength is NULL. -* \retval DRX_STS_ERROR Erroneous data, sig_strength contains invalid data. +* \retval 0 sig_strength contains valid data. +* \retval -EINVAL sig_strength is NULL. +* \retval -EIO Erroneous data, sig_strength contains invalid data. */ #define DRXJ_AGC_TOP 0x2800 #define DRXJ_AGC_SNS 0x1600 @@ -5800,13 +5800,13 @@ static int get_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength) u16 rf_agc_min = 0; rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_AGC_IF__A, &if_gain, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } if_gain &= IQM_AF_AGC_IF__M; rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_AGC_RF__A, &rf_gain, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -5823,7 +5823,7 @@ static int get_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength) else if (rf_gain > rf_agc_min) { if (rf_agc_max == rf_agc_min) { pr_err("error: rf_agc_max == rf_agc_min\n"); - return DRX_STS_ERROR; + return -EIO; } *sig_strength = 75 + 25 * (rf_gain - rf_agc_min) / (rf_agc_max - @@ -5833,21 +5833,21 @@ static int get_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength) } else if (if_gain > if_agc_sns) { if (if_agc_top == if_agc_sns) { pr_err("error: if_agc_top == if_agc_sns\n"); - return DRX_STS_ERROR; + return -EIO; } *sig_strength = 20 + 55 * (if_gain - if_agc_sns) / (if_agc_top - if_agc_sns); } else { if (!if_agc_sns) { pr_err("error: if_agc_sns is zero!\n"); - return DRX_STS_ERROR; + return -EIO; } *sig_strength = (20 * if_gain / if_agc_sns); } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /** @@ -5856,9 +5856,9 @@ rw_error: * \param demod Pointer to demod instance * \param packet_err Pointer to packet error * \return int. -* \retval DRX_STS_OK sig_strength contains valid data. -* \retval DRX_STS_INVALID_ARG sig_strength is NULL. -* \retval DRX_STS_ERROR Erroneous data, sig_strength contains invalid data. +* \retval 0 sig_strength contains valid data. +* \retval -EINVAL sig_strength is NULL. +* \retval -EIO Erroneous data, sig_strength contains invalid data. */ #ifdef DRXJ_SIGNAL_ACCUM_ERR static int get_acc_pkt_err(struct drx_demod_instance *demod, u16 *packet_err) @@ -5874,7 +5874,7 @@ static int get_acc_pkt_err(struct drx_demod_instance *demod, u16 *packet_err) dev_addr = demod->my_i2c_dev_addr; rc = DRXJ_DAP.read_reg16func(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -5893,9 +5893,9 @@ static int get_acc_pkt_err(struct drx_demod_instance *demod, u16 *packet_err) *packet_err = pkt_err; last_pkt_err = data; - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } #endif @@ -5904,8 +5904,8 @@ rw_error: * \brief Reset Accumulating packet error count. * \param demod Pointer to demod instance * \return int. -* \retval DRX_STS_OK. -* \retval DRX_STS_ERROR Erroneous data. +* \retval 0. +* \retval -EIO Erroneous data. */ static int ctrl_set_cfg_reset_pkt_err(struct drx_demod_instance *demod) { @@ -5918,15 +5918,15 @@ static int ctrl_set_cfg_reset_pkt_err(struct drx_demod_instance *demod) ext_attr->reset_pkt_err_acc = true; /* call to reset counter */ rc = get_acc_pkt_err(demod, &packet_error); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - return DRX_STS_OK; + return 0; rw_error: #endif - return DRX_STS_ERROR; + return -EIO; } /** @@ -5944,7 +5944,7 @@ static int get_str_freq_offset(struct drx_demod_instance *demod, s32 *str_freq) struct drxj_data *ext_attr = demod->my_ext_attr; rc = drxj_dap_atomic_read_reg32(dev_addr, IQM_RC_RATE_LO__A, &symbol_frequency_ratio, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -5962,9 +5962,9 @@ static int get_str_freq_offset(struct drx_demod_instance *demod, s32 *str_freq) symbol_frequency_ratio), (symbol_frequency_ratio + (1 << 23))); - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /** @@ -5995,7 +5995,7 @@ static int get_ctl_freq_offset(struct drx_demod_instance *demod, s32 *ctl_freq) /* both registers are sign extended */ nominal_frequency = ext_attr->iqm_fs_rate_ofs; rc = drxj_dap_atomic_read_reg32(dev_addr, IQM_FS_RATE_LO__A, (u32 *)¤t_frequency, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -6019,9 +6019,9 @@ static int get_ctl_freq_offset(struct drx_demod_instance *demod, s32 *ctl_freq) *ctl_freq = (s32) ((((data64lo >> 28) & 0xf) | (data64hi << 4)) * sign); - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -6069,20 +6069,20 @@ set_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, /* Enable RF AGC DAC */ rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_STDBY__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } data |= IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE; rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_STDBY__A, data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Enable SCU RF AGC loop */ rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -6099,20 +6099,20 @@ set_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, else data &= ~SCU_RAM_AGC_KI_INV_RF_POL__M; rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Set speed ( using complementary reduction value ) */ rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M; rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, (~(agc_settings->speed << SCU_RAM_AGC_KI_RED_RAGC_RED__B) & SCU_RAM_AGC_KI_RED_RAGC_RED__M) | data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -6124,17 +6124,17 @@ set_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, else if (DRXJ_ISATVSTD(agc_settings->standard)) p_agc_settings = &(ext_attr->atv_if_agc_cfg); else - return DRX_STS_INVALID_ARG; + return -EINVAL; /* Set TOP, only if IF-AGC is in AUTO mode */ if (p_agc_settings->ctrl_mode == DRX_AGC_CTRL_AUTO) { rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, agc_settings->top, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, agc_settings->top, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -6142,7 +6142,7 @@ set_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, /* Cut-Off current */ rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_RF_IACCU_HI_CO__A, agc_settings->cut_off_current, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -6151,20 +6151,20 @@ set_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, /* Enable RF AGC DAC */ rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_STDBY__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } data |= IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE; rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_STDBY__A, data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Disable SCU RF AGC loop */ rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -6174,14 +6174,14 @@ set_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, else data &= ~SCU_RAM_AGC_KI_INV_RF_POL__M; rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Write value to output pin */ rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, agc_settings->output_level, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -6190,32 +6190,32 @@ set_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, /* Disable RF AGC DAC */ rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_STDBY__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } data &= (~IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE); rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_STDBY__A, data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Disable SCU RF AGC loop */ rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } data &= ~SCU_RAM_AGC_KI_RF__M; rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } break; default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } /* switch ( agcsettings->ctrl_mode ) */ } @@ -6243,12 +6243,12 @@ set_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, break; #endif default: - return DRX_STS_ERROR; + return -EIO; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /** @@ -6294,7 +6294,7 @@ get_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings) break; #endif default: - return DRX_STS_ERROR; + return -EIO; } agc_settings->standard = standard; @@ -6305,15 +6305,15 @@ get_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings) (DRXJ_ISATVSTD(ext_attr->standard) && DRXJ_ISATVSTD(agc_settings->standard))) { rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, &(agc_settings->output_level), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /** @@ -6358,20 +6358,20 @@ set_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, case DRX_AGC_CTRL_AUTO: /* Enable IF AGC DAC */ rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_STDBY__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } data |= IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE; rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_STDBY__A, data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Enable SCU IF AGC loop */ rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -6389,20 +6389,20 @@ set_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, else data &= ~SCU_RAM_AGC_KI_INV_IF_POL__M; rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Set speed (using complementary reduction value) */ rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M; rc = (*scu_wr16) (dev_addr, SCU_RAM_AGC_KI_RED__A, (~(agc_settings->speed << SCU_RAM_AGC_KI_RED_IAGC_RED__B) & SCU_RAM_AGC_KI_RED_IAGC_RED__M) | data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -6414,28 +6414,28 @@ set_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, else if (DRXJ_ISATVSTD(agc_settings->standard)) p_agc_settings = &(ext_attr->atv_rf_agc_cfg); else - return DRX_STS_INVALID_ARG; + return -EINVAL; /* Restore TOP */ if (p_agc_settings->ctrl_mode == DRX_AGC_CTRL_AUTO) { rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, p_agc_settings->top, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, p_agc_settings->top, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } else { rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -6446,20 +6446,20 @@ set_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, /* Enable IF AGC DAC */ rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_STDBY__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } data |= IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE; rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_STDBY__A, data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Disable SCU IF AGC loop */ rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -6470,14 +6470,14 @@ set_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, else data &= ~SCU_RAM_AGC_KI_INV_IF_POL__M; rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Write value to output pin */ rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, agc_settings->output_level, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -6487,38 +6487,38 @@ set_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, /* Disable If AGC DAC */ rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_STDBY__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } data &= (~IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE); rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_STDBY__A, data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Disable SCU IF AGC loop */ rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M; data |= SCU_RAM_AGC_KI_IF_AGC_DISABLE__M; rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } break; default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } /* switch ( agcsettings->ctrl_mode ) */ /* always set the top to support configurations without if-loop */ rc = (*scu_wr16) (dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, agc_settings->top, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -6548,12 +6548,12 @@ set_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, break; #endif default: - return DRX_STS_ERROR; + return -EIO; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /** @@ -6599,7 +6599,7 @@ get_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings) break; #endif default: - return DRX_STS_ERROR; + return -EIO; } agc_settings->standard = standard; @@ -6611,15 +6611,15 @@ get_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings) DRXJ_ISATVSTD(agc_settings->standard))) { /* read output level */ rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_HI__A, &(agc_settings->output_level), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /** @@ -6639,7 +6639,7 @@ static int set_iqm_af(struct drx_demod_instance *demod, bool active) /* Configure IQM */ rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_STDBY__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -6648,14 +6648,14 @@ static int set_iqm_af(struct drx_demod_instance *demod, bool active) else data |= (IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE | IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE | IQM_AF_STDBY_STDBY_PD_A2_ACTIVE | IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE | IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE); rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_STDBY__A, data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -6699,56 +6699,56 @@ static int power_down_vsb(struct drx_demod_instance *demod, bool primary) cmd_scu.parameter = NULL; cmd_scu.result = &cmd_result; rc = scu_command(dev_addr, &cmd_scu); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* stop all comm_exec */ rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } if (primary) { rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = set_iqm_af(demod, false); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } else { rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -6756,14 +6756,14 @@ static int power_down_vsb(struct drx_demod_instance *demod, bool primary) cfg_mpeg_output.enable_mpeg_output = false; rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /** @@ -6967,19 +6967,19 @@ static int set_vsb_leak_n_gain(struct drx_demod_instance *demod) dev_addr = demod->my_i2c_dev_addr; rc = DRXJ_DAP.write_block_func(dev_addr, VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__A, sizeof(vsb_ffe_leak_gain_ram0), ((u8 *)vsb_ffe_leak_gain_ram0), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_block_func(dev_addr, VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__A, sizeof(vsb_ffe_leak_gain_ram1), ((u8 *)vsb_ffe_leak_gain_ram1), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /** @@ -7035,37 +7035,37 @@ static int set_vsb(struct drx_demod_instance *demod) /* stop all comm_exec */ rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -7078,147 +7078,147 @@ static int set_vsb(struct drx_demod_instance *demod) cmd_scu.parameter = NULL; cmd_scu.result = &cmd_result; rc = scu_command(dev_addr, &cmd_scu); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_DCF_BYPASS__A, 1, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_FS_ADJ_SEL__A, IQM_FS_ADJ_SEL_B_VSB, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RC_ADJ_SEL__A, IQM_RC_ADJ_SEL_B_VSB, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } ext_attr->iqm_rc_rate_ofs = 0x00AD0D79; rc = DRXJ_DAP.write_reg32func(dev_addr, IQM_RC_RATE_OFS_LO__A, ext_attr->iqm_rc_rate_ofs, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_CFAGC_GAINSHIFT__A, 4, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_CYGN1TRK__A, 1, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RC_CROUT_ENA__A, 1, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RC_STRETCH__A, 28, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_ACTIVE__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_SYMMETRIC__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_MIDTAP__A, 3, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_VSB__M, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_SCALE__A, 1393, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_SCALE_SH__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_POW_MEAS_LEN__A, 1, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(vsb_taps_re), ((u8 *)vsb_taps_re), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(vsb_taps_re), ((u8 *)vsb_taps_re), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_BNTHRESH__A, 330, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* set higher threshold */ rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_CLPLASTNUM__A, 90, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* burst detection on */ rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_SNRTH_RCA1__A, 0x0042, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* drop thresholds by 1 dB */ rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_SNRTH_RCA2__A, 0x0053, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* drop thresholds by 2 dB */ rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_EQCTRL__A, 0x1, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* cma on */ rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_GPIO__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* GPIO */ /* Initialize the FEC Subsystem */ rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_TOP_ANNEX__A, FEC_TOP_ANNEX_D, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } { u16 fec_oc_snc_mode = 0; rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* output data even when not locked */ rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_SNC_MODE__A, fec_oc_snc_mode | FEC_OC_SNC_MODE_UNLOCK_ENABLE__M, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -7226,22 +7226,22 @@ static int set_vsb(struct drx_demod_instance *demod) /* set clip */ rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_CLP_LEN__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_CLP_TH__A, 470, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_SNS_LEN__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_SNRTH_PT__A, 0xD4, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -7249,75 +7249,75 @@ static int set_vsb(struct drx_demod_instance *demod) { u16 fec_oc_reg_mode = 0; rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_OC_MODE__A, &fec_oc_reg_mode, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_MODE__A, fec_oc_reg_mode & (~(FEC_OC_MODE_TRANSPARENT__M | FEC_OC_MODE_CLEAR__M | FEC_OC_MODE_RETAIN_FRAMING__M)), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_DI_TIMEOUT_LO__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* timeout counter for restarting */ rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_DI_TIMEOUT_HI__A, 3, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_RS_MODE__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* bypass disabled */ /* initialize RS packet error measurement parameters */ rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_RS_MEASUREMENT_PERIOD__A, FEC_RS_MEASUREMENT_PERIOD, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_RS_MEASUREMENT_PRESCALE__A, FEC_RS_MEASUREMENT_PRESCALE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* init measurement period of MER/SER */ rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_MEASUREMENT_PERIOD__A, VSB_TOP_MEASUREMENT_PERIOD, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg32func(dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_CKGN1TRK__A, 128, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* B-Input to ADC, PGA+filter in standby */ if (!ext_attr->has_lna) { rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_AMUX__A, 0x02, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -7325,28 +7325,28 @@ static int set_vsb(struct drx_demod_instance *demod) /* turn on IQMAF. It has to be in front of setAgc**() */ rc = set_iqm_af(demod, true); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = adc_synchronization(demod); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = init_agc(demod); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = set_agc_if(demod, &(ext_attr->vsb_if_agc_cfg), false); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = set_agc_rf(demod, &(ext_attr->vsb_rf_agc_cfg), false); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -7357,30 +7357,30 @@ static int set_vsb(struct drx_demod_instance *demod) vsb_pga_cfg.gain = ext_attr->vsb_pga_cfg; rc = ctrl_set_cfg_afe_gain(demod, &vsb_pga_cfg); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->vsb_pre_saw_cfg)); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Mpeg output has to be in front of FEC active */ rc = set_mpegtei_handling(demod); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = bit_reverse_mpeg_output(demod); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = set_mpeg_start_width(demod); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -7400,7 +7400,7 @@ static int set_vsb(struct drx_demod_instance *demod) cfg_mpeg_output.static_clk = common_attr->mpeg_cfg.static_clk; cfg_mpeg_output.bitrate = common_attr->mpeg_cfg.bitrate; rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -7415,48 +7415,48 @@ static int set_vsb(struct drx_demod_instance *demod) cmd_scu.parameter = &cmd_param; cmd_scu.result = &cmd_result; rc = scu_command(dev_addr, &cmd_scu); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_BEAGC_GAINSHIFT__A, 0x0004, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_SNRTH_PT__A, 0x00D2, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_SYSSMTRNCTRL__A, VSB_TOP_SYSSMTRNCTRL__PRE | VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__M, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_BEDETCTRL__A, 0x142, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_LBAGCREFLVL__A, 640, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_CYGN1ACQ__A, 4, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_CYGN1TRK__A, 2, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_CYGN2TRK__A, 3, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -7469,30 +7469,30 @@ static int set_vsb(struct drx_demod_instance *demod) cmd_scu.parameter = NULL; cmd_scu.result = &cmd_result; rc = scu_command(dev_addr, &cmd_scu); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_ACTIVE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /** @@ -7510,7 +7510,7 @@ static int get_vsb_post_rs_pck_err(struct i2c_device_addr *dev_addr, u16 *pck_er u16 packet_errors_exp = 0; rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_RS_NR_FAILURES__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -7523,15 +7523,15 @@ static int get_vsb_post_rs_pck_err(struct i2c_device_addr *dev_addr, u16 *pck_er /* 77.3 us is time for per packet */ if (period * prescale == 0) { pr_err("error: period and/or prescale is zero!\n"); - return DRX_STS_ERROR; + return -EIO; } *pck_errs = (u16) frac_times1e6(packet_errors_mant * (1 << packet_errors_exp), (period * prescale * 77)); - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /** @@ -7549,7 +7549,7 @@ static int get_vs_bpost_viterbi_ber(struct i2c_device_addr *dev_addr, u32 *ber) u16 bit_errors_exp = 0; rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_RS_NR_BIT_ERRORS__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -7565,7 +7565,7 @@ static int get_vs_bpost_viterbi_ber(struct i2c_device_addr *dev_addr, u32 *ber) else { if (period * prescale == 0) { pr_err("error: period and/or prescale is zero!\n"); - return DRX_STS_ERROR; + return -EIO; } *ber = frac_times1e6(bit_errors_mant << @@ -7575,9 +7575,9 @@ static int get_vs_bpost_viterbi_ber(struct i2c_device_addr *dev_addr, u32 *ber) ((bit_errors_exp > 2) ? 1 : 8)); } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /** @@ -7591,7 +7591,7 @@ static int get_vs_bpre_viterbi_ber(struct i2c_device_addr *dev_addr, u32 *ber) int rc; rc = DRXJ_DAP.read_reg16func(dev_addr, VSB_TOP_NR_SYM_ERRS__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -7599,9 +7599,9 @@ static int get_vs_bpre_viterbi_ber(struct i2c_device_addr *dev_addr, u32 *ber) frac_times1e6(data, VSB_TOP_MEASUREMENT_PERIOD * SYMBOLS_PER_SEGMENT); - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /** @@ -7619,7 +7619,7 @@ static int get_vsb_symb_err(struct i2c_device_addr *dev_addr, u32 *ser) u16 symb_errors_exp = 0; rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_RS_NR_SYMBOL_ERRORS__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -7632,14 +7632,14 @@ static int get_vsb_symb_err(struct i2c_device_addr *dev_addr, u32 *ser) if (period * prescale == 0) { pr_err("error: period and/or prescale is zero!\n"); - return DRX_STS_ERROR; + return -EIO; } *ser = (u32) frac_times1e6((symb_errors_mant << symb_errors_exp) * 1000, (period * prescale * 77318)); - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /** @@ -7653,16 +7653,16 @@ static int get_vsbmer(struct i2c_device_addr *dev_addr, u16 *mer) u16 data_hi = 0; rc = DRXJ_DAP.read_reg16func(dev_addr, VSB_TOP_ERR_ENERGY_H__A, &data_hi, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } *mer = (u16) (log1_times100(21504) - log1_times100((data_hi << 6) / 52)); - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -7694,7 +7694,7 @@ ctrl_get_vsb_constel(struct drx_demod_instance *demod, struct drx_complex *compl /* Configure MB (Monitor bus) */ rc = DRXJ_DAP.read_reg16func(dev_addr, VSB_TOP_COMM_MB__A, &vsb_top_comm_mb_init, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -7703,28 +7703,28 @@ ctrl_get_vsb_constel(struct drx_demod_instance *demod, struct drx_complex *compl VSB_TOP_COMM_MB_OBS_OBS_ON | VSB_TOP_COMM_MB_MUX_OBS_VSB_TCMEQ_2); rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_COMM_MB__A, vsb_top_comm_mb, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Enable MB grabber in the FEC OC */ rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_OCR_MODE__A, FEC_OC_OCR_MODE_GRAB_ENABLE__M, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Disable MB grabber in the FEC OC */ rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_OCR_MODE__A, 0x0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* read data */ rc = DRXJ_DAP.read_reg32func(dev_addr, FEC_OC_OCR_GRAB_RD1__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -7736,14 +7736,14 @@ ctrl_get_vsb_constel(struct drx_demod_instance *demod, struct drx_complex *compl /* Restore MB (Monitor bus) */ rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_COMM_MB__A, vsb_top_comm_mb_init, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -7782,12 +7782,12 @@ static int power_down_qam(struct drx_demod_instance *demod, bool primary) */ /* stop all comm_exec */ rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -7799,45 +7799,45 @@ static int power_down_qam(struct drx_demod_instance *demod, bool primary) cmd_scu.parameter = NULL; cmd_scu.result = &cmd_result; rc = scu_command(dev_addr, &cmd_scu); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } if (primary) { rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = set_iqm_af(demod, false); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } else { rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -7845,14 +7845,14 @@ static int power_down_qam(struct drx_demod_instance *demod, bool primary) cfg_mpeg_output.enable_mpeg_output = false; rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -7915,7 +7915,7 @@ set_qam_measurement(struct drx_demod_instance *demod, fec_bits_desired = 8 * symbol_rate; break; default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } /* Parameters for Reed-Solomon Decoder */ @@ -7934,14 +7934,14 @@ set_qam_measurement(struct drx_demod_instance *demod, fec_rs_plen = 128 * 7; break; default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } ext_attr->fec_rs_plen = fec_rs_plen; /* for getSigQual */ fec_rs_bit_cnt = fec_rs_prescale * fec_rs_plen; /* temp storage */ if (fec_rs_bit_cnt == 0) { pr_err("error: fec_rs_bit_cnt is zero!\n"); - return DRX_STS_ERROR; + return -EIO; } fec_rs_period = fec_bits_desired / fec_rs_bit_cnt + 1; /* ceil */ if (ext_attr->standard != DRX_STANDARD_ITU_B) @@ -7967,42 +7967,42 @@ set_qam_measurement(struct drx_demod_instance *demod, fec_oc_snc_fail_period = 25805; break; default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } break; default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_SNC_FAIL_PERIOD__A, (u16)fec_oc_snc_fail_period, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_RS_MEASUREMENT_PERIOD__A, (u16)fec_rs_period, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_RS_MEASUREMENT_PRESCALE__A, fec_rs_prescale, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } ext_attr->fec_rs_period = (u16) fec_rs_period; ext_attr->fec_rs_prescale = fec_rs_prescale; rc = DRXJ_DAP.write_reg32func(dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -8034,11 +8034,11 @@ set_qam_measurement(struct drx_demod_instance *demod, * (QAM_TOP_CONSTELLATION_QAM256 + 1); break; default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } if (qam_vd_period == 0) { pr_err("error: qam_vd_period is zero!\n"); - return DRX_STS_ERROR; + return -EIO; } qam_vd_period = fec_bits_desired / qam_vd_period; /* limit to max 16 bit value (I2C register width) if needed */ @@ -8049,12 +8049,12 @@ set_qam_measurement(struct drx_demod_instance *demod, qam_vd_bit_cnt *= qam_vd_period; rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_VD_MEASUREMENT_PERIOD__A, (u16)qam_vd_period, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_VD_MEASUREMENT_PRESCALE__A, qam_vd_prescale, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -8062,9 +8062,9 @@ set_qam_measurement(struct drx_demod_instance *demod, ext_attr->qam_vd_prescale = qam_vd_prescale; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -8097,209 +8097,209 @@ static int set_qam16(struct drx_demod_instance *demod) }; rc = DRXJ_DAP.write_block_func(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_block_func(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 140, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 50, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 120, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 230, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 95, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 105, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 16, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 220, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 25, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 6, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-24), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-65), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-127), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 50, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 240, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 40960, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -8332,209 +8332,209 @@ static int set_qam32(struct drx_demod_instance *demod) }; rc = DRXJ_DAP.write_block_func(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_block_func(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 90, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 50, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 170, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 100, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 140, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16)(-8), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16)(-16), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-26), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-56), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-86), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 50, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 176, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 8, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 20480, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -8567,209 +8567,209 @@ static int set_qam64(struct drx_demod_instance *demod) }; rc = DRXJ_DAP.write_block_func(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_block_func(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 105, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 195, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 84, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 141, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 7, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-15), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-45), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-80), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 15, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 160, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 43008, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -8802,209 +8802,209 @@ static int set_qam128(struct drx_demod_instance *demod) }; rc = DRXJ_DAP.write_block_func(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_block_func(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 50, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 140, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 100, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 65, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 5, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 3, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-1), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 12, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-23), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 144, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 20992, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -9037,209 +9037,209 @@ static int set_qam256(struct drx_demod_instance *demod) }; rc = DRXJ_DAP.write_block_func(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_block_func(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 50, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 150, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 110, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 16, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 74, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 18, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 13, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, 7, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-8), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 25, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 80, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 43520, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -9417,13 +9417,13 @@ set_qam(struct drx_demod_instance *demod, iqm_rc_stretch = IQM_RC_STRETCH_QAM_B_64; break; default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } } else { adc_frequency = (common_attr->sys_clock_freq * 1000) / 3; if (channel->symbolrate == 0) { pr_err("error: channel symbolrate is zero!\n"); - return DRX_STS_ERROR; + return -EIO; } iqm_rc_rate = (adc_frequency / channel->symbolrate) * (1 << 21) + @@ -9454,7 +9454,7 @@ set_qam(struct drx_demod_instance *demod, set_param_parameters[0] = channel->constellation; /* constellation */ set_param_parameters[1] = DRX_INTERLEAVEMODE_I12_J17; /* interleave mode */ } else { - return DRX_STS_INVALID_ARG; + return -EINVAL; } } @@ -9466,37 +9466,37 @@ set_qam(struct drx_demod_instance *demod, */ /* stop all comm_exec */ rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -9508,7 +9508,7 @@ set_qam(struct drx_demod_instance *demod, cmd_scu.parameter = NULL; cmd_scu.result = &cmd_result; rc = scu_command(dev_addr, &cmd_scu); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -9527,7 +9527,7 @@ set_qam(struct drx_demod_instance *demod, cmd_scu.parameter = &set_env_parameters; cmd_scu.result = &cmd_result; rc = scu_command(dev_addr, &cmd_scu); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -9539,19 +9539,19 @@ set_qam(struct drx_demod_instance *demod, cmd_scu.parameter = set_param_parameters; cmd_scu.result = &cmd_result; rc = scu_command(dev_addr, &cmd_scu); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* set symbol rate */ rc = DRXJ_DAP.write_reg32func(dev_addr, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } ext_attr->iqm_rc_rate_ofs = iqm_rc_rate; rc = set_qam_measurement(demod, channel->constellation, channel->symbolrate); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -9562,7 +9562,7 @@ set_qam(struct drx_demod_instance *demod, /* TODO: remove re-writes of HW reset values */ if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_SPECTRUM)) { rc = set_frequency(demod, channel, tuner_freq_offset); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -9571,12 +9571,12 @@ set_qam(struct drx_demod_instance *demod, if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) { rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_SYMBOL_FREQ__A, lc_symbol_freq, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RC_STRETCH__A, iqm_rc_stretch, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -9585,98 +9585,98 @@ set_qam(struct drx_demod_instance *demod, if (op & QAM_SET_OP_ALL) { if (!ext_attr->has_lna) { rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_AMUX__A, 0x02, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_SYMMETRIC__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_MIDTAP__A, 3, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_QAM__M, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_WR_RSV_0__A, 0x5f, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* scu temporary shut down agc */ rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_SYNC_SEL__A, 3, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_CLP_LEN__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_CLP_TH__A, 448, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_SNS_LEN__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_PDREF__A, 4, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_STDBY__A, 0x10, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_PGA_GAIN__A, 11, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_POW_MEAS_LEN__A, 1, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /*! reset default val ! */ rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /*! reset default val ! */ if (ext_attr->standard == DRX_STANDARD_ITU_B) { rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_SY_SYNC_LWM__A, QAM_SY_SYNC_LWM__PRE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /*! reset default val ! */ rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_SY_SYNC_AWM__A, QAM_SY_SYNC_AWM__PRE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /*! reset default val ! */ rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /*! reset default val ! */ @@ -9686,17 +9686,17 @@ set_qam(struct drx_demod_instance *demod, case DRX_CONSTELLATION_QAM64: case DRX_CONSTELLATION_QAM256: rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_SY_SYNC_LWM__A, 0x03, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_SY_SYNC_AWM__A, 0x04, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /*! reset default val ! */ @@ -9704,149 +9704,149 @@ set_qam(struct drx_demod_instance *demod, case DRX_CONSTELLATION_QAM32: case DRX_CONSTELLATION_QAM128: rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_SY_SYNC_LWM__A, 0x03, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_SY_SYNC_AWM__A, 0x05, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_SY_SYNC_HWM__A, 0x06, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } break; default: - return DRX_STS_ERROR; + return -EIO; } /* switch */ } rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_MODE__A, QAM_LC_MODE__PRE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /*! reset default val ! */ rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_RATE_LIMIT__A, 3, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_LPF_FACTORP__A, 4, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_LPF_FACTORI__A, 4, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_MODE__A, 7, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_QUAL_TAB0__A, 1, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_QUAL_TAB1__A, 1, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_QUAL_TAB2__A, 1, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_QUAL_TAB3__A, 1, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_QUAL_TAB4__A, 2, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_QUAL_TAB5__A, 2, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_QUAL_TAB6__A, 2, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_QUAL_TAB8__A, 2, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_QUAL_TAB9__A, 2, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_QUAL_TAB10__A, 2, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_QUAL_TAB12__A, 2, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_QUAL_TAB15__A, 3, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_QUAL_TAB16__A, 3, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_QUAL_TAB20__A, 4, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_QUAL_TAB25__A, 4, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_FS_ADJ_SEL__A, 1, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RC_ADJ_SEL__A, 1, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_ADJ_SEL__A, 1, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_POW_MEAS_LEN__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_GPIO__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -9855,28 +9855,28 @@ set_qam(struct drx_demod_instance *demod, now AGCs can be configured. */ /* turn on IQMAF. It has to be in front of setAgc**() */ rc = set_iqm_af(demod, true); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = adc_synchronization(demod); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = init_agc(demod); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = set_agc_if(demod, &(ext_attr->qam_if_agc_cfg), false); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = set_agc_rf(demod, &(ext_attr->qam_rf_agc_cfg), false); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -9887,13 +9887,13 @@ set_qam(struct drx_demod_instance *demod, qam_pga_cfg.gain = ext_attr->qam_pga_cfg; rc = ctrl_set_cfg_afe_gain(demod, &qam_pga_cfg); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->qam_pre_saw_cfg)); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -9902,12 +9902,12 @@ set_qam(struct drx_demod_instance *demod, if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) { if (ext_attr->standard == DRX_STANDARD_ITU_A) { rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_a_taps), ((u8 *)qam_a_taps), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_a_taps), ((u8 *)qam_a_taps), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -9915,39 +9915,39 @@ set_qam(struct drx_demod_instance *demod, switch (channel->constellation) { case DRX_CONSTELLATION_QAM64: rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_b64_taps), ((u8 *)qam_b64_taps), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_b64_taps), ((u8 *)qam_b64_taps), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } break; case DRX_CONSTELLATION_QAM256: rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_b256_taps), ((u8 *)qam_b256_taps), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_b256_taps), ((u8 *)qam_b256_taps), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } break; default: - return DRX_STS_ERROR; + return -EIO; } } else if (ext_attr->standard == DRX_STANDARD_ITU_C) { rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_c_taps), ((u8 *)qam_c_taps), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_c_taps), ((u8 *)qam_c_taps), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -9957,64 +9957,64 @@ set_qam(struct drx_demod_instance *demod, switch (channel->constellation) { case DRX_CONSTELLATION_QAM16: rc = set_qam16(demod); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } break; case DRX_CONSTELLATION_QAM32: rc = set_qam32(demod); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } break; case DRX_CONSTELLATION_QAM64: rc = set_qam64(demod); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } break; case DRX_CONSTELLATION_QAM128: rc = set_qam128(demod); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } break; case DRX_CONSTELLATION_QAM256: rc = set_qam256(demod); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } break; default: - return DRX_STS_ERROR; + return -EIO; } /* switch */ } if ((op & QAM_SET_OP_ALL)) { rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_SCALE_SH__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Mpeg output has to be in front of FEC active */ rc = set_mpegtei_handling(demod); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = bit_reverse_mpeg_output(demod); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = set_mpeg_start_width(demod); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -10037,7 +10037,7 @@ set_qam(struct drx_demod_instance *demod, cfg_mpeg_output.static_clk = common_attr->mpeg_cfg.static_clk; cfg_mpeg_output.bitrate = common_attr->mpeg_cfg.bitrate; rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -10054,31 +10054,31 @@ set_qam(struct drx_demod_instance *demod, cmd_scu.parameter = NULL; cmd_scu.result = &cmd_result; rc = scu_command(dev_addr, &cmd_scu); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -10103,35 +10103,35 @@ static int qam_flip_spec(struct drx_demod_instance *demod, struct drx_channel *c /* Silence the controlling of lc, equ, and the acquisition state machine */ rc = DRXJ_DAP.read_reg16func(dev_addr, SCU_RAM_QAM_CTL_ENA__A, &qam_ctl_ena, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_CTL_ENA__A, qam_ctl_ena & ~(SCU_RAM_QAM_CTL_ENA_ACQ__M | SCU_RAM_QAM_CTL_ENA_EQU__M | SCU_RAM_QAM_CTL_ENA_LC__M), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* freeze the frequency control loop */ rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_CF__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_CF1__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = drxj_dap_atomic_read_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, &iqm_fs_rate_ofs, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = drxj_dap_atomic_read_reg32(dev_addr, IQM_FS_RATE_LO__A, &iqm_fs_rate_lo, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -10141,42 +10141,42 @@ static int qam_flip_spec(struct drx_demod_instance *demod, struct drx_channel *c /* freeze dq/fq updating */ rc = DRXJ_DAP.read_reg16func(dev_addr, QAM_DQ_MODE__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } data = (data & 0xfff9); rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_DQ_MODE__A, data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_FQ_MODE__A, data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* lc_cp / _ci / _ca */ rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_CI__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_EP__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_FQ_LA_FACTOR__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* flip the spec */ rc = DRXJ_DAP.write_reg32func(dev_addr, IQM_FS_RATE_OFS_LO__A, iqm_fs_rate_ofs, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -10185,31 +10185,31 @@ static int qam_flip_spec(struct drx_demod_instance *demod, struct drx_channel *c /* freeze dq/fq updating */ rc = DRXJ_DAP.read_reg16func(dev_addr, QAM_DQ_MODE__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } equ_mode = data; data = (data & 0xfff9); rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_DQ_MODE__A, data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_FQ_MODE__A, data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } for (i = 0; i < 28; i++) { rc = DRXJ_DAP.read_reg16func(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), -data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -10217,12 +10217,12 @@ static int qam_flip_spec(struct drx_demod_instance *demod, struct drx_channel *c for (i = 0; i < 24; i++) { rc = DRXJ_DAP.read_reg16func(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), -data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -10230,18 +10230,18 @@ static int qam_flip_spec(struct drx_demod_instance *demod, struct drx_channel *c data = equ_mode; rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_DQ_MODE__A, data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_FQ_MODE__A, data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_STATE_TGT__A, 4, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -10249,20 +10249,20 @@ static int qam_flip_spec(struct drx_demod_instance *demod, struct drx_channel *c i = 0; while ((fsm_state != 4) && (i++ < 100)) { rc = DRXJ_DAP.read_reg16func(dev_addr, SCU_RAM_QAM_FSM_STATE__A, &fsm_state, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_CTL_ENA__A, (qam_ctl_ena | 0x0016), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } @@ -10300,7 +10300,7 @@ qam64auto(struct drx_demod_instance *demod, state = NO_LOCK; do { rc = ctrl_lock_status(demod, lock_status); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -10309,7 +10309,7 @@ qam64auto(struct drx_demod_instance *demod, case NO_LOCK: if (*lock_status == DRXJ_DEMOD_LOCK) { rc = ctrl_get_qam_sig_quality(demod, &sig_quality); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -10326,12 +10326,12 @@ qam64auto(struct drx_demod_instance *demod, ((drxbsp_hst_clock() - d_locked_time) > DRXJ_QAM_FEC_LOCK_WAITTIME)) { rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -10344,19 +10344,19 @@ qam64auto(struct drx_demod_instance *demod, if (channel->mirror == DRX_MIRROR_AUTO) { /* flip sync pattern back */ rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data & 0xFFFE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* flip spectrum */ ext_attr->mirror = DRX_MIRROR_YES; rc = qam_flip_spec(demod, channel); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -10378,18 +10378,18 @@ qam64auto(struct drx_demod_instance *demod, ((drxbsp_hst_clock() - d_locked_time) > DRXJ_QAM_FEC_LOCK_WAITTIME)) { rc = ctrl_get_qam_sig_quality(demod, &sig_quality); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } if (sig_quality.MER > 208) { rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -10412,9 +10412,9 @@ qam64auto(struct drx_demod_instance *demod, ); /* Returning control to apllication ... */ - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /** @@ -10446,7 +10446,7 @@ qam256auto(struct drx_demod_instance *demod, state = NO_LOCK; do { rc = ctrl_lock_status(demod, lock_status); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -10454,7 +10454,7 @@ qam256auto(struct drx_demod_instance *demod, case NO_LOCK: if (*lock_status == DRXJ_DEMOD_LOCK) { rc = ctrl_get_qam_sig_quality(demod, &sig_quality); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -10472,7 +10472,7 @@ qam256auto(struct drx_demod_instance *demod, DRXJ_QAM_FEC_LOCK_WAITTIME)) { ext_attr->mirror = DRX_MIRROR_YES; rc = qam_flip_spec(demod, channel); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -10495,9 +10495,9 @@ qam256auto(struct drx_demod_instance *demod, ((drxbsp_hst_clock() - start_time) < (DRXJ_QAM_MAX_WAITTIME + timeout_ofs))); - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /** @@ -10532,7 +10532,7 @@ set_qam_channel(struct drx_demod_instance *demod, else ext_attr->mirror = channel->mirror; rc = set_qam(demod, channel, tuner_freq_offset, QAM_SET_OP_ALL); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -10540,7 +10540,7 @@ set_qam_channel(struct drx_demod_instance *demod, if ((ext_attr->standard == DRX_STANDARD_ITU_B) && (channel->constellation == DRX_CONSTELLATION_QAM64)) { rc = qam64auto(demod, channel, tuner_freq_offset, &lock_status); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -10550,7 +10550,7 @@ set_qam_channel(struct drx_demod_instance *demod, (channel->mirror == DRX_MIRROR_AUTO) && (channel->constellation == DRX_CONSTELLATION_QAM256)) { rc = qam256auto(demod, channel, tuner_freq_offset, &lock_status); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -10567,12 +10567,12 @@ set_qam_channel(struct drx_demod_instance *demod, else ext_attr->mirror = channel->mirror; rc = set_qam(demod, channel, tuner_freq_offset, QAM_SET_OP_ALL); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = qam256auto(demod, channel, tuner_freq_offset, &lock_status); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -10590,34 +10590,34 @@ set_qam_channel(struct drx_demod_instance *demod, { u16 qam_ctl_ena = 0; rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SCU_RAM_QAM_CTL_ENA__A, &qam_ctl_ena, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SCU_RAM_QAM_CTL_ENA__A, qam_ctl_ena & ~SCU_RAM_QAM_CTL_ENA_ACQ__M, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SCU_RAM_QAM_FSM_STATE_TGT__A, 0x2, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* force to rate hunting */ rc = set_qam(demod, channel, tuner_freq_offset, QAM_SET_OP_CONSTELLATION); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SCU_RAM_QAM_CTL_ENA__A, qam_ctl_ena, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } rc = qam64auto(demod, channel, tuner_freq_offset, &lock_status); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -10635,53 +10635,53 @@ set_qam_channel(struct drx_demod_instance *demod, { u16 qam_ctl_ena = 0; rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SCU_RAM_QAM_CTL_ENA__A, &qam_ctl_ena, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SCU_RAM_QAM_CTL_ENA__A, qam_ctl_ena & ~SCU_RAM_QAM_CTL_ENA_ACQ__M, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SCU_RAM_QAM_FSM_STATE_TGT__A, 0x2, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* force to rate hunting */ rc = set_qam(demod, channel, tuner_freq_offset, QAM_SET_OP_CONSTELLATION); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SCU_RAM_QAM_CTL_ENA__A, qam_ctl_ena, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } rc = qam64auto(demod, channel, tuner_freq_offset, &lock_status); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } channel->constellation = DRX_CONSTELLATION_AUTO; } else { channel->constellation = DRX_CONSTELLATION_AUTO; - return DRX_STS_INVALID_ARG; + return -EINVAL; } break; default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } - return DRX_STS_OK; + return 0; rw_error: /* restore starting value */ if (auto_flag) channel->constellation = DRX_CONSTELLATION_AUTO; - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -10704,37 +10704,37 @@ get_qamrs_err_count(struct i2c_device_addr *dev_addr, struct drxjrs_errors *rs_e /* check arguments */ if (dev_addr == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; /* all reported errors are received in the */ /* most recently finished measurment period */ /* no of pre RS bit errors */ rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_RS_NR_BIT_ERRORS__A, &nr_bit_errors, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* no of symbol errors */ rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_RS_NR_SYMBOL_ERRORS__A, &nr_symbol_errors, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* no of packet errors */ rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_RS_NR_PACKET_ERRORS__A, &nr_packet_errors, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* no of failures to decode */ rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_RS_NR_FAILURES__A, &nr_failures, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* no of post RS bit erros */ rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_OC_SNC_FAIL_COUNT__A, &nr_snc_par_fail_count, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -10749,9 +10749,9 @@ get_qamrs_err_count(struct i2c_device_addr *dev_addr, struct drxjrs_errors *rs_e rs_errors->nr_snc_par_fail_count = nr_snc_par_fail_count & FEC_OC_SNC_FAIL_COUNT__M; - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -10762,9 +10762,9 @@ rw_error: * \param devmod Pointer to demodulator instance. * \param sig_quality Pointer to signal quality data. * \return int. -* \retval DRX_STS_OK sig_quality contains valid data. -* \retval DRX_STS_INVALID_ARG sig_quality is NULL. -* \retval DRX_STS_ERROR Erroneous data, sig_quality contains invalid data. +* \retval 0 sig_quality contains valid data. +* \retval -EINVAL sig_quality is NULL. +* \retval -EIO Erroneous data, sig_quality contains invalid data. * Pre-condition: Device must be started and in lock. */ @@ -10809,19 +10809,19 @@ ctrl_get_qam_sig_quality(struct drx_demod_instance *demod, struct drx_sig_qualit /* read the physical registers */ /* Get the RS error data */ rc = get_qamrs_err_count(dev_addr, &measuredrs_errors); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* get the register value needed for MER */ rc = DRXJ_DAP.read_reg16func(dev_addr, QAM_SL_ERR_POWER__A, &qam_sl_err_power, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* get the register value needed for post RS BER */ rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_OC_SNC_FAIL_PERIOD__A, &fec_oc_period, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -10852,7 +10852,7 @@ ctrl_get_qam_sig_quality(struct drx_demod_instance *demod, struct drx_sig_qualit qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM256 << 2; break; default: - return DRX_STS_ERROR; + return -EIO; } /* ------------------------------ */ @@ -10874,7 +10874,7 @@ ctrl_get_qam_sig_quality(struct drx_demod_instance *demod, struct drx_sig_qualit /* get the register value */ /* no of quadrature symbol errors */ rc = DRXJ_DAP.read_reg16func(dev_addr, QAM_VD_NR_QSYM_ERRORS__A, &qsym_err_vd, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -10943,7 +10943,7 @@ ctrl_get_qam_sig_quality(struct drx_demod_instance *demod, struct drx_sig_qualit sig_quality->scale_factor_ber = ((u32) 1000000); #ifdef DRXJ_SIGNAL_ACCUM_ERR rc = get_acc_pkt_err(demod, &sig_quality->packet_error); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -10951,9 +10951,9 @@ ctrl_get_qam_sig_quality(struct drx_demod_instance *demod, struct drx_sig_qualit sig_quality->packet_error = ((u16) pkt_errs); #endif - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /** @@ -10988,7 +10988,7 @@ ctrl_get_qam_constel(struct drx_demod_instance *demod, struct drx_complex *compl /* Configure MB (Monitor bus) */ rc = DRXJ_DAP.read_reg16func(dev_addr, QAM_SL_COMM_MB__A, &qam_sl_comm_mb_init, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -10998,7 +10998,7 @@ ctrl_get_qam_constel(struct drx_demod_instance *demod, struct drx_complex *compl qam_sl_comm_mb |= (QAM_SL_COMM_MB_OBS_ON + QAM_SL_COMM_MB_MUX_OBS_CONST_CORR); rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_SL_COMM_MB__A, qam_sl_comm_mb, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -11017,21 +11017,21 @@ ctrl_get_qam_constel(struct drx_demod_instance *demod, struct drx_complex *compl (FEC_OC_OCR_MODE_GRAB_COUNTED__M & (0x0 << FEC_OC_OCR_MODE_GRAB_COUNTED__B))); rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_OCR_MODE__A, fec_oc_ocr_mode, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Disable MB grabber in the FEC OC */ rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_OCR_MODE__A, 0x00, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* read data */ rc = DRXJ_DAP.read_reg32func(dev_addr, FEC_OC_OCR_GRAB_RD0__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -11051,14 +11051,14 @@ ctrl_get_qam_constel(struct drx_demod_instance *demod, struct drx_complex *compl /* Restore MB (Monitor bus) */ rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_SL_COMM_MB__A, qam_sl_comm_mb_init, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } #endif /* #ifndef DRXJ_VSB_ONLY */ @@ -11161,11 +11161,11 @@ static int atv_equ_coef_index(enum drx_standard standard, int *index) break; default: *index = (int)DRXJ_COEF_IDX_MN; /* still return a valid index */ - return DRX_STS_ERROR; + return -EIO; break; } - return DRX_STS_OK; + return 0; } /* -------------------------------------------------------------------------- */ @@ -11193,27 +11193,27 @@ atv_update_config(struct drx_demod_instance *demod, bool force_update) int index = 0; rc = atv_equ_coef_index(ext_attr->standard, &index); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_EQU0__A, ext_attr->atv_top_equ0[index], 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_EQU1__A, ext_attr->atv_top_equ1[index], 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_EQU2__A, ext_attr->atv_top_equ2[index], 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_EQU3__A, ext_attr->atv_top_equ3[index], 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -11224,7 +11224,7 @@ atv_update_config(struct drx_demod_instance *demod, bool force_update) u16 data = 0; rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_RT_ROT_BP__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -11234,7 +11234,7 @@ atv_update_config(struct drx_demod_instance *demod, bool force_update) else data |= IQM_RT_ROT_BP_ROT_OFF_ACTIVE; rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_ROT_BP__A, data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -11244,7 +11244,7 @@ atv_update_config(struct drx_demod_instance *demod, bool force_update) if (force_update || ((ext_attr->atv_cfg_changed_flags & DRXJ_ATV_CHANGED_PEAK_FLT) != 0)) { rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_VID_PEAK__A, ext_attr->atv_top_vid_peak, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -11254,7 +11254,7 @@ atv_update_config(struct drx_demod_instance *demod, bool force_update) if (force_update || ((ext_attr->atv_cfg_changed_flags & DRXJ_ATV_CHANGED_NOISE_FLT) != 0)) { rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_NOISE_TH__A, ext_attr->atv_top_noise_th, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -11279,11 +11279,11 @@ atv_update_config(struct drx_demod_instance *demod, bool force_update) attenuation = ATV_TOP_AF_SIF_ATT_M9DB; break; default: - return DRX_STS_ERROR; + return -EIO; break; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_AF_SIF_ATT__A, attenuation, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -11295,7 +11295,7 @@ atv_update_config(struct drx_demod_instance *demod, bool force_update) u16 data = 0; rc = DRXJ_DAP.read_reg16func(dev_addr, ATV_TOP_STDBY__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -11309,7 +11309,7 @@ atv_update_config(struct drx_demod_instance *demod, bool force_update) else data |= ATV_TOP_STDBY_SIF_STDBY_STANDBY; rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_STDBY__A, data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -11317,9 +11317,9 @@ atv_update_config(struct drx_demod_instance *demod, bool force_update) ext_attr->atv_cfg_changed_flags = 0; - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /* -------------------------------------------------------------------------- */ @@ -11339,7 +11339,7 @@ ctrl_set_cfg_atv_output(struct drx_demod_instance *demod, struct drxj_cfg_atv_ou /* Check arguments */ if (output_cfg == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; ext_attr = (struct drxj_data *) demod->my_ext_attr; if (output_cfg->enable_sif_output) { @@ -11351,7 +11351,7 @@ ctrl_set_cfg_atv_output(struct drx_demod_instance *demod, struct drxj_cfg_atv_ou /* Do nothing */ break; default: - return DRX_STS_INVALID_ARG; + return -EINVAL; break; } @@ -11372,14 +11372,14 @@ ctrl_set_cfg_atv_output(struct drx_demod_instance *demod, struct drxj_cfg_atv_ou } rc = atv_update_config(demod, false); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /* -------------------------------------------------------------------------- */ @@ -11403,7 +11403,7 @@ ctrl_set_cfg_atv_equ_coef(struct drx_demod_instance *demod, struct drxj_cfg_atv_ /* current standard needs to be an ATV standard */ if (!DRXJ_ISATVSTD(ext_attr->standard)) - return DRX_STS_ERROR; + return -EIO; /* Check arguments */ if ((coef == NULL) || @@ -11415,11 +11415,11 @@ ctrl_set_cfg_atv_equ_coef(struct drx_demod_instance *demod, struct drxj_cfg_atv_ (coef->coef1 < ((s16) ~(ATV_TOP_EQU1_EQU_C1__M >> 1))) || (coef->coef2 < ((s16) ~(ATV_TOP_EQU2_EQU_C2__M >> 1))) || (coef->coef3 < ((s16) ~(ATV_TOP_EQU3_EQU_C3__M >> 1)))) { - return DRX_STS_INVALID_ARG; + return -EINVAL; } rc = atv_equ_coef_index(ext_attr->standard, &index); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -11430,14 +11430,14 @@ ctrl_set_cfg_atv_equ_coef(struct drx_demod_instance *demod, struct drxj_cfg_atv_ ext_attr->atv_cfg_changed_flags |= DRXJ_ATV_CHANGED_COEF; rc = atv_update_config(demod, false); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /* -------------------------------------------------------------------------- */ @@ -11465,14 +11465,14 @@ ctrl_get_cfg_atv_equ_coef(struct drx_demod_instance *demod, struct drxj_cfg_atv_ /* current standard needs to be an ATV standard */ if (!DRXJ_ISATVSTD(ext_attr->standard)) - return DRX_STS_ERROR; + return -EIO; /* Check arguments */ if (coef == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; rc = atv_equ_coef_index(ext_attr->standard, &index); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -11481,9 +11481,9 @@ ctrl_get_cfg_atv_equ_coef(struct drx_demod_instance *demod, struct drxj_cfg_atv_ coef->coef2 = ext_attr->atv_top_equ2[index]; coef->coef3 = ext_attr->atv_top_equ3[index]; - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /* -------------------------------------------------------------------------- */ @@ -11506,7 +11506,7 @@ ctrl_set_cfg_atv_misc(struct drx_demod_instance *demod, struct drxj_cfg_atv_misc ((settings->peak_filter) < (s16) (-8)) || ((settings->peak_filter) > (s16) (15)) || ((settings->noise_filter) > 15)) { - return DRX_STS_INVALID_ARG; + return -EINVAL; } /* if */ ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -11522,14 +11522,14 @@ ctrl_set_cfg_atv_misc(struct drx_demod_instance *demod, struct drxj_cfg_atv_misc } rc = atv_update_config(demod, false); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /* -------------------------------------------------------------------------- */ @@ -11552,14 +11552,14 @@ ctrl_get_cfg_atv_misc(struct drx_demod_instance *demod, struct drxj_cfg_atv_misc /* Check arguments */ if (settings == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; ext_attr = (struct drxj_data *) demod->my_ext_attr; settings->peak_filter = ext_attr->atv_top_vid_peak; settings->noise_filter = ext_attr->atv_top_noise_th; - return DRX_STS_OK; + return 0; } /* -------------------------------------------------------------------------- */ @@ -11581,10 +11581,10 @@ ctrl_get_cfg_atv_output(struct drx_demod_instance *demod, struct drxj_cfg_atv_ou /* Check arguments */ if (output_cfg == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, ATV_TOP_STDBY__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -11598,16 +11598,16 @@ ctrl_get_cfg_atv_output(struct drx_demod_instance *demod, struct drxj_cfg_atv_ou } else { output_cfg->enable_sif_output = true; rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, ATV_TOP_AF_SIF_ATT__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } output_cfg->sif_attenuation = (enum drxjsif_attenuation) data; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /* -------------------------------------------------------------------------- */ @@ -11630,7 +11630,7 @@ ctrl_get_cfg_atv_agc_status(struct drx_demod_instance *demod, /* Check arguments */ if (agc_status == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; dev_addr = demod->my_i2c_dev_addr; @@ -11641,7 +11641,7 @@ ctrl_get_cfg_atv_agc_status(struct drx_demod_instance *demod, IQM_AF_AGC_RF__A * 27 is 20 bits worst case. */ rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_AGC_RF__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -11658,7 +11658,7 @@ ctrl_get_cfg_atv_agc_status(struct drx_demod_instance *demod, IQM_AF_AGC_IF__A * 27 is 20 bits worst case. */ rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_AGC_IF__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -11677,7 +11677,7 @@ ctrl_get_cfg_atv_agc_status(struct drx_demod_instance *demod, */ rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -11697,7 +11697,7 @@ ctrl_get_cfg_atv_agc_status(struct drx_demod_instance *demod, */ rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_ATV_SIF_GAIN__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -11710,7 +11710,7 @@ ctrl_get_cfg_atv_agc_status(struct drx_demod_instance *demod, /* Loop gain's */ rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -11721,9 +11721,9 @@ ctrl_get_cfg_atv_agc_status(struct drx_demod_instance *demod, agc_status->if_agc_loop_gain = ((data & SCU_RAM_AGC_KI_IF__M) >> SCU_RAM_AGC_KI_IF__B); - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /* -------------------------------------------------------------------------- */ @@ -11745,33 +11745,33 @@ static int power_up_atv(struct drx_demod_instance *demod, enum drx_standard stan /* ATV NTSC */ rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_ACTIVE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* turn on IQM_AF */ rc = set_iqm_af(demod, true); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = adc_synchronization(demod); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Audio, already done during set standard */ - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } #endif /* #ifndef DRXJ_DIGITAL_ONLY */ @@ -11811,69 +11811,69 @@ power_down_atv(struct drx_demod_instance *demod, enum drx_standard standard, boo cmd_scu.parameter = NULL; cmd_scu.result = &cmd_result; rc = scu_command(dev_addr, &cmd_scu); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Disable ATV outputs (ATV reset enables CVBS, undo this) */ rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_STDBY__A, (ATV_TOP_STDBY_SIF_STDBY_STANDBY & (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE)), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_STOP, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } if (primary) { rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = set_iqm_af(demod, false); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } else { rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } rc = power_down_aud(demod); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /* -------------------------------------------------------------------------- */ @@ -12179,14 +12179,14 @@ trouble ? /* Upload only audio microcode */ rc = ctrl_u_code_upload(demod, &ucode_info, UCODE_UPLOAD, true); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } if (common_attr->verify_microcode == true) { rc = ctrl_u_code_upload(demod, &ucode_info, UCODE_VERIFY, true); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -12198,32 +12198,32 @@ trouble ? #endif /* DRXJ_SPLIT_UCODE_UPLOAD */ rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_STOP, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -12235,13 +12235,13 @@ trouble ? cmd_scu.parameter = NULL; cmd_scu.result = &cmd_result; rc = scu_command(dev_addr, &cmd_scu); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_MOD_CONTROL__A, ATV_TOP_MOD_CONTROL__PRE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -12253,69 +12253,69 @@ trouble ? cmd_param = SCU_RAM_ATV_STANDARD_STANDARD_MN; rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_LO_INCR__A, IQM_RT_LO_INCR_MN, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(ntsc_taps_re), ((u8 *)ntsc_taps_re), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(ntsc_taps_im), ((u8 *)ntsc_taps_im), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_AMP_TH__A, ATV_TOP_CR_AMP_TH_MN, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_CONT__A, (ATV_TOP_CR_CONT_CR_P_MN | ATV_TOP_CR_CONT_CR_D_MN | ATV_TOP_CR_CONT_CR_I_MN), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_MN, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_MN | ATV_TOP_STD_VID_POL_MN), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_MN, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM | SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_BG_MN, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -12327,48 +12327,48 @@ trouble ? cmd_param = SCU_RAM_ATV_STANDARD_STANDARD_FM; rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_LO_INCR__A, 2994, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_MIDTAP__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(fm_taps_re), ((u8 *)fm_taps_re), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(fm_taps_im), ((u8 *)fm_taps_im), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_FM | ATV_TOP_STD_VID_POL_FM), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_MOD_CONTROL__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_CONT__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW | SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_ROT_BP__A, IQM_RT_ROT_BP_ROT_OFF_OFF, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -12380,67 +12380,67 @@ trouble ? cmd_param = SCU_RAM_ATV_STANDARD_STANDARD_B; rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_LO_INCR__A, 1820, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* TODO check with IS */ rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(bg_taps_re), ((u8 *)bg_taps_re), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(bg_taps_im), ((u8 *)bg_taps_im), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_BG, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_AMP_TH__A, ATV_TOP_CR_AMP_TH_BG, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_CONT__A, (ATV_TOP_CR_CONT_CR_P_BG | ATV_TOP_CR_CONT_CR_D_BG | ATV_TOP_CR_CONT_CR_I_BG), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_BG, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_BG | ATV_TOP_STD_VID_POL_BG), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM | SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_BG_MN, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -12453,67 +12453,67 @@ trouble ? cmd_param = SCU_RAM_ATV_STANDARD_STANDARD_DK; rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_LO_INCR__A, 2225, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* TODO check with IS */ rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(dk_i_l_lp_taps_re), ((u8 *)dk_i_l_lp_taps_re), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(dk_i_l_lp_taps_im), ((u8 *)dk_i_l_lp_taps_im), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_AMP_TH__A, ATV_TOP_CR_AMP_TH_DK, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_DK, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_CONT__A, (ATV_TOP_CR_CONT_CR_P_DK | ATV_TOP_CR_CONT_CR_D_DK | ATV_TOP_CR_CONT_CR_I_DK), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_DK, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_DK | ATV_TOP_STD_VID_POL_DK), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM | SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_DK, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -12526,67 +12526,67 @@ trouble ? cmd_param = SCU_RAM_ATV_STANDARD_STANDARD_I; rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_LO_INCR__A, 2225, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* TODO check with IS */ rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(dk_i_l_lp_taps_re), ((u8 *)dk_i_l_lp_taps_re), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(dk_i_l_lp_taps_im), ((u8 *)dk_i_l_lp_taps_im), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_AMP_TH__A, ATV_TOP_CR_AMP_TH_I, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_I, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_CONT__A, (ATV_TOP_CR_CONT_CR_P_I | ATV_TOP_CR_CONT_CR_D_I | ATV_TOP_CR_CONT_CR_I_I), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_I, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_I | ATV_TOP_STD_VID_POL_I), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM | SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_I, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -12599,67 +12599,67 @@ trouble ? cmd_param = SCU_RAM_ATV_STANDARD_STANDARD_L; rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_LO_INCR__A, 2225, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* TODO check with IS */ rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_L, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(dk_i_l_lp_taps_re), ((u8 *)dk_i_l_lp_taps_re), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(dk_i_l_lp_taps_im), ((u8 *)dk_i_l_lp_taps_im), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_AMP_TH__A, 0x2, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* TODO check with IS */ rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_CONT__A, (ATV_TOP_CR_CONT_CR_P_L | ATV_TOP_CR_CONT_CR_D_L | ATV_TOP_CR_CONT_CR_I_L), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_L, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_L | ATV_TOP_STD_VID_POL_L), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_AM | SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_ENABLE | SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_LLP, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -12673,67 +12673,67 @@ trouble ? cmd_param = SCU_RAM_ATV_STANDARD_STANDARD_LP; rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_LP, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_LO_INCR__A, 2225, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* TODO check with IS */ rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(dk_i_l_lp_taps_re), ((u8 *)dk_i_l_lp_taps_re), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(dk_i_l_lp_taps_im), ((u8 *)dk_i_l_lp_taps_im), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_AMP_TH__A, 0x2, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* TODO check with IS */ rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_CONT__A, (ATV_TOP_CR_CONT_CR_P_LP | ATV_TOP_CR_CONT_CR_D_LP | ATV_TOP_CR_CONT_CR_I_LP), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_LP, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_LP | ATV_TOP_STD_VID_POL_LP), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_AM | SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_ENABLE | SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_LLP, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -12743,201 +12743,201 @@ trouble ? ext_attr->enable_cvbs_output = true; break; default: - return DRX_STS_ERROR; + return -EIO; } /* Common initializations FM & NTSC & B/G & D/K & I & L & LP */ if (!ext_attr->has_lna) { rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_AMUX__A, 0x01, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_STANDARD__A, 0x002, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_CLP_LEN__A, IQM_AF_CLP_LEN_ATV, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_CLP_TH__A, IQM_AF_CLP_TH_ATV, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_SNS_LEN__A, IQM_AF_SNS_LEN_ATV, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->atv_pre_saw_cfg)); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_AGC_IF__A, 10248, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } ext_attr->iqm_rc_rate_ofs = 0x00200000L; rc = DRXJ_DAP.write_reg32func(dev_addr, IQM_RC_RATE_OFS_LO__A, ext_attr->iqm_rc_rate_ofs, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RC_ADJ_SEL__A, IQM_RC_ADJ_SEL_B_OFF, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RC_STRETCH__A, IQM_RC_STRETCH_ATV, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_ACTIVE__A, IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_ON | IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_ON, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_ATV__M, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_SYMMETRIC__A, IQM_CF_SYMMETRIC_IM__M, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* default: SIF in standby */ rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_SYNC_SLICE__A, ATV_TOP_SYNC_SLICE_MN, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_MOD_ACCU__A, ATV_TOP_MOD_ACCU__PRE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_SIF_GAIN__A, 0x080, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_FAGC_TH_RED__A, 10, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AAGC_CNT__A, 7, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_NAGC_KI_MIN__A, 0x0225, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_NAGC_KI_MAX__A, 0x0547, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_KI_CHANGE_TH__A, 20, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_LOCK__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_DELAY__A, IQM_RT_DELAY__PRE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_BPC_KI_MIN__A, 531, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_PAGC_KI_MIN__A, 1061, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_BP_REF_MIN__A, 100, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_BP_REF_MAX__A, 260, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_BP_LVL__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AMS_MAX__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AMS_MIN__A, 2047, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_GPIO__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Override reset values with current shadow settings */ rc = atv_update_config(demod, true); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Configure/restore AGC settings */ rc = init_agc(demod); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = set_agc_if(demod, &(ext_attr->atv_if_agc_cfg), false); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = set_agc_rf(demod, &(ext_attr->atv_rf_agc_cfg), false); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->atv_pre_saw_cfg)); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -12950,7 +12950,7 @@ trouble ? cmd_scu.parameter = &cmd_param; cmd_scu.result = &cmd_result; rc = scu_command(dev_addr, &cmd_scu); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -12958,26 +12958,26 @@ trouble ? /* turn the analog work around on/off (must after set_env b/c it is set in mc) */ if (ext_attr->mfx == 0x03) { rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_ENABLE_IIR_WA__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } else { rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_ENABLE_IIR_WA__A, 1, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_IIR_CRIT__A, 225, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } #endif @@ -13025,12 +13025,12 @@ set_atv_channel(struct drx_demod_instance *demod, ext_attr->mirror = channel->mirror; rc = set_frequency(demod, channel, tuner_freq_offset); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_FREQ__A, ATV_TOP_CR_FREQ__PRE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -13043,7 +13043,7 @@ set_atv_channel(struct drx_demod_instance *demod, cmd_scu.parameter = NULL; cmd_scu.result = &cmd_result; rc = scu_command(dev_addr, &cmd_scu); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -13053,9 +13053,9 @@ set_atv_channel(struct drx_demod_instance *demod, ext_attr->detectedRDS = (bool)false; }*/ - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } #endif @@ -13097,7 +13097,7 @@ get_atv_channel(struct drx_demod_instance *demod, /* get measured frequency offset */ rc = DRXJ_DAP.read_reg16func(dev_addr, ATV_TOP_CR_FREQ__A, &measured_offset, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -13114,7 +13114,7 @@ get_atv_channel(struct drx_demod_instance *demod, /* get measured frequency offset */ rc = DRXJ_DAP.read_reg16func(dev_addr, ATV_TOP_CR_FREQ__A, &measured_offset, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -13133,14 +13133,14 @@ get_atv_channel(struct drx_demod_instance *demod, channel->bandwidth = DRX_BANDWIDTH_UNKNOWN; break; default: - return DRX_STS_ERROR; + return -EIO; } channel->frequency -= offset; - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /* -------------------------------------------------------------------------- */ @@ -13150,8 +13150,8 @@ rw_error: * \param devmod Pointer to demodulator instance. * \param sig_quality Pointer to signal strength data; range 0, .. , 100. * \return int. -* \retval DRX_STS_OK sig_strength contains valid data. -* \retval DRX_STS_ERROR Erroneous data, sig_strength equals 0. +* \retval 0 sig_strength contains valid data. +* \retval -EIO Erroneous data, sig_strength equals 0. * * Taking into account: * * digital gain @@ -13203,7 +13203,7 @@ get_atv_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength) case DRX_STANDARD_PAL_SECAM_LP: /* fallthrough */ case DRX_STANDARD_NTSC: rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, &digital_curr_gain, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -13212,7 +13212,7 @@ get_atv_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength) break; case DRX_STANDARD_FM: rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_ATV_SIF_GAIN__A, &digital_curr_gain, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -13220,16 +13220,16 @@ get_atv_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength) digital_min_gain = 0; /* taken from ucode */ break; default: - return DRX_STS_ERROR; + return -EIO; break; } rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_AGC_RF__A, &rf_curr_gain, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_AGC_IF__A, &if_curr_gain, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -13272,9 +13272,9 @@ get_atv_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength) rf_weight * rf_strength + if_weight * if_strength); *sig_strength /= 100; - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /* -------------------------------------------------------------------------- */ @@ -13284,8 +13284,8 @@ rw_error: * \param devmod Pointer to demodulator instance. * \param sig_quality Pointer to signal quality structure. * \return int. -* \retval DRX_STS_OK sig_quality contains valid data. -* \retval DRX_STS_ERROR Erroneous data, sig_quality indicator equals 0. +* \retval 0 sig_quality contains valid data. +* \retval -EIO Erroneous data, sig_quality indicator equals 0. * * */ @@ -13314,7 +13314,7 @@ atv_sig_quality(struct drx_demod_instance *demod, struct drx_sig_quality *sig_qu */ rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_ATV_CR_LOCK__A, &quality_indicator, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -13327,9 +13327,9 @@ atv_sig_quality(struct drx_demod_instance *demod, struct drx_sig_quality *sig_qu else sig_quality->indicator = (30 * (0x7FF - quality_indicator)) / (0x7FF - 0x701); - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } #endif /* DRXJ_DIGITAL_ONLY */ @@ -13359,33 +13359,33 @@ static int power_up_aud(struct drx_demod_instance *demod, bool set_standard) dev_addr = demod->my_i2c_dev_addr; rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_TOP_COMM_EXEC__A, AUD_TOP_COMM_EXEC_ACTIVE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* setup TR interface: R/W mode, fifosize=8 */ rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_TOP_TR_MDE__A, 8, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_COMM_EXEC__A, AUD_COMM_EXEC_ACTIVE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } if (set_standard) { rc = aud_ctrl_set_standard(demod, &aud_standard); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -13406,16 +13406,16 @@ static int power_down_aud(struct drx_demod_instance *demod) ext_attr = (struct drxj_data *) demod->my_ext_attr; rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } ext_attr->aud_data.audio_is_active = false; - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -13437,7 +13437,7 @@ static int aud_get_modus(struct drx_demod_instance *demod, u16 *modus) u16 r_modus_lo = 0; if (modus == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -13445,7 +13445,7 @@ static int aud_get_modus(struct drx_demod_instance *demod, u16 *modus) /* power up */ if (ext_attr->aud_data.audio_is_active == false) { rc = power_up_aud(demod, true); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -13454,12 +13454,12 @@ static int aud_get_modus(struct drx_demod_instance *demod, u16 *modus) /* Modus register is combined in to RAM location */ rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_RAM_MODUS_HI__A, &r_modus_hi, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_RAM_MODUS_LO__A, &r_modus_lo, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -13469,9 +13469,9 @@ static int aud_get_modus(struct drx_demod_instance *demod, u16 *modus) *modus = r_modus; - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } @@ -13498,12 +13498,12 @@ aud_ctrl_get_cfg_rds(struct drx_demod_instance *demod, struct drx_cfg_aud_rds *s ext_attr = (struct drxj_data *) demod->my_ext_attr; if (status == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; /* power up */ if (ext_attr->aud_data.audio_is_active == false) { rc = power_up_aud(demod, true); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -13513,7 +13513,7 @@ aud_ctrl_get_cfg_rds(struct drx_demod_instance *demod, struct drx_cfg_aud_rds *s status->valid = false; rc = DRXJ_DAP.read_reg16func(addr, AUD_DEM_RD_RDS_ARRAY_CNT__A, &r_rds_array_cnt_init, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -13521,12 +13521,12 @@ aud_ctrl_get_cfg_rds(struct drx_demod_instance *demod, struct drx_cfg_aud_rds *s if (r_rds_array_cnt_init == AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT_RDS_DATA_NOT_VALID) { /* invalid data */ - return DRX_STS_OK; + return 0; } if (ext_attr->aud_data.rds_data_counter == r_rds_array_cnt_init) { /* no new data */ - return DRX_STS_OK; + return 0; } /* RDS is detected, as long as FM radio is selected assume @@ -13537,7 +13537,7 @@ aud_ctrl_get_cfg_rds(struct drx_demod_instance *demod, struct drx_cfg_aud_rds *s /* read the data */ for (rds_data_cnt = 0; rds_data_cnt < AUD_RDS_ARRAY_SIZE; rds_data_cnt++) { rc = DRXJ_DAP.read_reg16func(addr, AUD_DEM_RD_RDS_DATA__A, &r_rds_data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -13545,7 +13545,7 @@ aud_ctrl_get_cfg_rds(struct drx_demod_instance *demod, struct drx_cfg_aud_rds *s } rc = DRXJ_DAP.read_reg16func(addr, AUD_DEM_RD_RDS_ARRAY_CNT__A, &r_rds_array_cnt_check, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -13555,9 +13555,9 @@ aud_ctrl_get_cfg_rds(struct drx_demod_instance *demod, struct drx_cfg_aud_rds *s ext_attr->aud_data.rds_data_counter = r_rds_array_cnt_check; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -13577,7 +13577,7 @@ aud_ctrl_get_carrier_detect_status(struct drx_demod_instance *demod, struct drx_ u16 r_data = 0; if (status == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -13585,7 +13585,7 @@ aud_ctrl_get_carrier_detect_status(struct drx_demod_instance *demod, struct drx_ /* power up */ if (ext_attr->aud_data.audio_is_active == false) { rc = power_up_aud(demod, true); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -13601,7 +13601,7 @@ aud_ctrl_get_carrier_detect_status(struct drx_demod_instance *demod, struct drx_ /* read stereo sound mode indication */ rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_RD_STATUS__A, &r_data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -13630,9 +13630,9 @@ aud_ctrl_get_carrier_detect_status(struct drx_demod_instance *demod, struct drx_ if ((r_data & AUD_DEM_RD_STATUS_STAT_STEREO__M) == AUD_DEM_RD_STATUS_STAT_STEREO_STEREO) status->stereo = true; - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -13653,14 +13653,14 @@ aud_ctrl_get_status(struct drx_demod_instance *demod, struct drx_aud_status *sta u16 r_data = 0; if (status == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; /* carrier detection */ rc = aud_ctrl_get_carrier_detect_status(demod, status); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -13668,7 +13668,7 @@ aud_ctrl_get_status(struct drx_demod_instance *demod, struct drx_aud_status *sta /* rds data */ status->rds = false; rc = aud_ctrl_get_cfg_rds(demod, &rds); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -13676,16 +13676,16 @@ aud_ctrl_get_status(struct drx_demod_instance *demod, struct drx_aud_status *sta /* fm_ident */ rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DSP_RD_FM_IDENT_VALUE__A, &r_data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } r_data >>= AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__B; status->fm_ident = (s8) r_data; - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -13708,7 +13708,7 @@ aud_ctrl_get_cfg_volume(struct drx_demod_instance *demod, struct drx_cfg_aud_vol u16 r_strength_right = 0; if (volume == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -13716,7 +13716,7 @@ aud_ctrl_get_cfg_volume(struct drx_demod_instance *demod, struct drx_cfg_aud_vol /* power up */ if (ext_attr->aud_data.audio_is_active == false) { rc = power_up_aud(demod, true); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -13726,7 +13726,7 @@ aud_ctrl_get_cfg_volume(struct drx_demod_instance *demod, struct drx_cfg_aud_vol /* volume */ volume->mute = ext_attr->aud_data.volume.mute; rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DSP_WR_VOLUME__A, &r_volume, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -13746,7 +13746,7 @@ aud_ctrl_get_cfg_volume(struct drx_demod_instance *demod, struct drx_cfg_aud_vol /* automatic volume control */ rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DSP_WR_AVC__A, &r_avc, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -13768,7 +13768,7 @@ aud_ctrl_get_cfg_volume(struct drx_demod_instance *demod, struct drx_cfg_aud_vol volume->avc_mode = DRX_AUD_AVC_DECAYTIME_2S; break; default: - return DRX_STS_ERROR; + return -EIO; break; } } @@ -13785,7 +13785,7 @@ aud_ctrl_get_cfg_volume(struct drx_demod_instance *demod, struct drx_cfg_aud_vol volume->avc_max_atten = DRX_AUD_AVC_MAX_ATTEN_24DB; break; default: - return DRX_STS_ERROR; + return -EIO; break; } @@ -13801,7 +13801,7 @@ aud_ctrl_get_cfg_volume(struct drx_demod_instance *demod, struct drx_cfg_aud_vol volume->avc_max_gain = DRX_AUD_AVC_MAX_GAIN_12DB; break; default: - return DRX_STS_ERROR; + return -EIO; break; } @@ -13817,7 +13817,7 @@ aud_ctrl_get_cfg_volume(struct drx_demod_instance *demod, struct drx_cfg_aud_vol /* QP vaues */ /* left carrier */ rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DSP_RD_QPEAK_L__A, &r_strength_left, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -13826,16 +13826,16 @@ aud_ctrl_get_cfg_volume(struct drx_demod_instance *demod, struct drx_cfg_aud_vol /* right carrier */ rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DSP_RD_QPEAK_R__A, &r_strength_right, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } volume->strength_right = (((s16) log1_times100(r_strength_right)) - AUD_CARRIER_STRENGTH_QP_0DB_LOG10T100) / 5; - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -13856,7 +13856,7 @@ aud_ctrl_set_cfg_volume(struct drx_demod_instance *demod, struct drx_cfg_aud_vol u16 w_avc = 0; if (volume == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -13864,7 +13864,7 @@ aud_ctrl_set_cfg_volume(struct drx_demod_instance *demod, struct drx_cfg_aud_vol /* power up */ if (ext_attr->aud_data.audio_is_active == false) { rc = power_up_aud(demod, true); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -13875,10 +13875,10 @@ aud_ctrl_set_cfg_volume(struct drx_demod_instance *demod, struct drx_cfg_aud_vol /* volume range from -60 to 12 (expressed in dB) */ if ((volume->volume < AUD_VOLUME_DB_MIN) || (volume->volume > AUD_VOLUME_DB_MAX)) - return DRX_STS_INVALID_ARG; + return -EINVAL; rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DSP_WR_VOLUME__A, &w_volume, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -13891,14 +13891,14 @@ aud_ctrl_set_cfg_volume(struct drx_demod_instance *demod, struct drx_cfg_aud_vol w_volume |= (u16)((volume->volume + AUD_VOLUME_ZERO_DB) << AUD_DSP_WR_VOLUME_VOL_MAIN__B); rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DSP_WR_VOLUME__A, w_volume, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* automatic volume control */ rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DSP_WR_AVC__A, &w_avc, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -13928,7 +13928,7 @@ aud_ctrl_set_cfg_volume(struct drx_demod_instance *demod, struct drx_cfg_aud_vol w_avc |= AUD_DSP_WR_AVC_AVC_DECAY_2_SEC; break; default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } } @@ -13945,7 +13945,7 @@ aud_ctrl_set_cfg_volume(struct drx_demod_instance *demod, struct drx_cfg_aud_vol w_avc |= AUD_DSP_WR_AVC_AVC_MAX_ATT_24DB; break; default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } /* max gain */ @@ -13961,18 +13961,18 @@ aud_ctrl_set_cfg_volume(struct drx_demod_instance *demod, struct drx_cfg_aud_vol w_avc |= AUD_DSP_WR_AVC_AVC_MAX_GAIN_12DB; break; default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } /* avc reference level */ if (volume->avc_ref_level > AUD_MAX_AVC_REF_LEVEL) - return DRX_STS_INVALID_ARG; + return -EINVAL; w_avc &= (u16) ~AUD_DSP_WR_AVC_AVC_REF_LEV__M; w_avc |= (u16) (volume->avc_ref_level << AUD_DSP_WR_AVC_AVC_REF_LEV__B); rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DSP_WR_AVC__A, w_avc, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -13980,9 +13980,9 @@ aud_ctrl_set_cfg_volume(struct drx_demod_instance *demod, struct drx_cfg_aud_vol /* all done, store config in data structure */ ext_attr->aud_data.volume = *volume; - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -14002,7 +14002,7 @@ aud_ctrl_get_cfg_output_i2s(struct drx_demod_instance *demod, struct drx_cfg_i2s u16 r_i2s_freq = 0; if (output == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -14010,7 +14010,7 @@ aud_ctrl_get_cfg_output_i2s(struct drx_demod_instance *demod, struct drx_cfg_i2s /* power up */ if (ext_attr->aud_data.audio_is_active == false) { rc = power_up_aud(demod, true); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -14018,12 +14018,12 @@ aud_ctrl_get_cfg_output_i2s(struct drx_demod_instance *demod, struct drx_cfg_i2s } rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_RAM_I2S_CONFIG2__A, &w_i2s_config, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DSP_WR_I2S_OUT_FS__A, &r_i2s_freq, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -14037,7 +14037,7 @@ aud_ctrl_get_cfg_output_i2s(struct drx_demod_instance *demod, struct drx_cfg_i2s output->mode = DRX_I2S_MODE_SLAVE; break; default: - return DRX_STS_ERROR; + return -EIO; } /* I2S format */ @@ -14049,7 +14049,7 @@ aud_ctrl_get_cfg_output_i2s(struct drx_demod_instance *demod, struct drx_cfg_i2s output->format = DRX_I2S_FORMAT_WS_WITH_DATA; break; default: - return DRX_STS_ERROR; + return -EIO; } /* I2S word length */ @@ -14061,7 +14061,7 @@ aud_ctrl_get_cfg_output_i2s(struct drx_demod_instance *demod, struct drx_cfg_i2s output->word_length = DRX_I2S_WORDLENGTH_32; break; default: - return DRX_STS_ERROR; + return -EIO; } /* I2S polarity */ @@ -14073,7 +14073,7 @@ aud_ctrl_get_cfg_output_i2s(struct drx_demod_instance *demod, struct drx_cfg_i2s output->polarity = DRX_I2S_POLARITY_RIGHT; break; default: - return DRX_STS_ERROR; + return -EIO; } /* I2S output enabled */ @@ -14090,9 +14090,9 @@ aud_ctrl_get_cfg_output_i2s(struct drx_demod_instance *demod, struct drx_cfg_i2s output->frequency = AUD_I2S_FREQUENCY_MAX; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -14115,7 +14115,7 @@ aud_ctrl_set_cfg_output_i2s(struct drx_demod_instance *demod, struct drx_cfg_i2s u32 w_i2s_freq = 0; if (output == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -14123,7 +14123,7 @@ aud_ctrl_set_cfg_output_i2s(struct drx_demod_instance *demod, struct drx_cfg_i2s /* power up */ if (ext_attr->aud_data.audio_is_active == false) { rc = power_up_aud(demod, true); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -14131,7 +14131,7 @@ aud_ctrl_set_cfg_output_i2s(struct drx_demod_instance *demod, struct drx_cfg_i2s } rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_RAM_I2S_CONFIG2__A, &w_i2s_config, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -14147,7 +14147,7 @@ aud_ctrl_set_cfg_output_i2s(struct drx_demod_instance *demod, struct drx_cfg_i2s w_i2s_config |= AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST_SLAVE; break; default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } /* I2S format */ @@ -14161,7 +14161,7 @@ aud_ctrl_set_cfg_output_i2s(struct drx_demod_instance *demod, struct drx_cfg_i2s w_i2s_config |= AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE_NO_DELAY; break; default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } /* I2S word length */ @@ -14175,7 +14175,7 @@ aud_ctrl_set_cfg_output_i2s(struct drx_demod_instance *demod, struct drx_cfg_i2s w_i2s_config |= AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_32; break; default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } /* I2S polarity */ @@ -14188,7 +14188,7 @@ aud_ctrl_set_cfg_output_i2s(struct drx_demod_instance *demod, struct drx_cfg_i2s w_i2s_config |= AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL_LEFT_LOW; break; default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } /* I2S output enabled */ @@ -14208,7 +14208,7 @@ aud_ctrl_set_cfg_output_i2s(struct drx_demod_instance *demod, struct drx_cfg_i2s */ if ((output->frequency > AUD_I2S_FREQUENCY_MAX) || output->frequency < AUD_I2S_FREQUENCY_MIN) { - return DRX_STS_INVALID_ARG; + return -EINVAL; } w_i2s_freq = (6144UL * 48000UL) + (output->frequency >> 1); @@ -14218,19 +14218,19 @@ aud_ctrl_set_cfg_output_i2s(struct drx_demod_instance *demod, struct drx_cfg_i2s w_i2s_freq *= 2; rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DEM_WR_I2S_CONFIG2__A, w_i2s_config, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DSP_WR_I2S_OUT_FS__A, (u16)w_i2s_freq, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* configure I2S output pads for master or slave mode */ rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -14252,23 +14252,23 @@ aud_ctrl_set_cfg_output_i2s(struct drx_demod_instance *demod, struct drx_cfg_i2s } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_I2S_DA_CFG__A, w_i2s_pads_data_da, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_I2S_CL_CFG__A, w_i2s_pads_data_cl, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_I2S_WS_CFG__A, w_i2s_pads_data_ws, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -14276,9 +14276,9 @@ aud_ctrl_set_cfg_output_i2s(struct drx_demod_instance *demod, struct drx_cfg_i2s /* all done, store config in data structure */ ext_attr->aud_data.i2sdata = *output; - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -14299,14 +14299,14 @@ aud_ctrl_get_cfg_auto_sound(struct drx_demod_instance *demod, u16 r_modus = 0; if (auto_sound == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; ext_attr = (struct drxj_data *) demod->my_ext_attr; /* power up */ if (ext_attr->aud_data.audio_is_active == false) { rc = power_up_aud(demod, true); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -14314,7 +14314,7 @@ aud_ctrl_get_cfg_auto_sound(struct drx_demod_instance *demod, } rc = aud_get_modus(demod, &r_modus); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -14335,12 +14335,12 @@ aud_ctrl_get_cfg_auto_sound(struct drx_demod_instance *demod, DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_OFF; break; default: - return DRX_STS_ERROR; + return -EIO; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -14363,7 +14363,7 @@ aud_ctr_setl_cfg_auto_sound(struct drx_demod_instance *demod, u16 w_modus = 0; if (auto_sound == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -14371,7 +14371,7 @@ aud_ctr_setl_cfg_auto_sound(struct drx_demod_instance *demod, /* power up */ if (ext_attr->aud_data.audio_is_active == false) { rc = power_up_aud(demod, true); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -14379,7 +14379,7 @@ aud_ctr_setl_cfg_auto_sound(struct drx_demod_instance *demod, } rc = aud_get_modus(demod, &r_modus); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -14403,12 +14403,12 @@ aud_ctr_setl_cfg_auto_sound(struct drx_demod_instance *demod, w_modus |= AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_DISABLED; break; default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } if (w_modus != r_modus) { rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DEM_WR_MODUS__A, w_modus, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -14416,9 +14416,9 @@ aud_ctr_setl_cfg_auto_sound(struct drx_demod_instance *demod, /* copy to data structure */ ext_attr->aud_data.auto_sound = *auto_sound; - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -14440,7 +14440,7 @@ aud_ctrl_get_cfg_ass_thres(struct drx_demod_instance *demod, struct drx_cfg_aud_ u16 thres_nicam = 0; if (thres == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -14448,7 +14448,7 @@ aud_ctrl_get_cfg_ass_thres(struct drx_demod_instance *demod, struct drx_cfg_aud_ /* power up */ if (ext_attr->aud_data.audio_is_active == false) { rc = power_up_aud(demod, true); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -14456,17 +14456,17 @@ aud_ctrl_get_cfg_ass_thres(struct drx_demod_instance *demod, struct drx_cfg_aud_ } rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_RAM_A2_THRSHLD__A, &thres_a2, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_RAM_BTSC_THRSHLD__A, &thres_btsc, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_RAM_NICAM_THRSHLD__A, &thres_nicam, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -14475,9 +14475,9 @@ aud_ctrl_get_cfg_ass_thres(struct drx_demod_instance *demod, struct drx_cfg_aud_ thres->btsc = thres_btsc; thres->nicam = thres_nicam; - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -14495,7 +14495,7 @@ aud_ctrl_set_cfg_ass_thres(struct drx_demod_instance *demod, struct drx_cfg_aud_ struct drxj_data *ext_attr = (struct drxj_data *) NULL; int rc; if (thres == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -14503,7 +14503,7 @@ aud_ctrl_set_cfg_ass_thres(struct drx_demod_instance *demod, struct drx_cfg_aud_ /* power up */ if (ext_attr->aud_data.audio_is_active == false) { rc = power_up_aud(demod, true); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -14511,17 +14511,17 @@ aud_ctrl_set_cfg_ass_thres(struct drx_demod_instance *demod, struct drx_cfg_aud_ } rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DEM_WR_A2_THRSHLD__A, thres->a2, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DEM_WR_BTSC_THRSHLD__A, thres->btsc, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DEM_WR_NICAM_THRSHLD__A, thres->nicam, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -14529,9 +14529,9 @@ aud_ctrl_set_cfg_ass_thres(struct drx_demod_instance *demod, struct drx_cfg_aud_ /* update DRXK data structure with hardware values */ ext_attr->aud_data.ass_thresholds = *thres; - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -14564,7 +14564,7 @@ aud_ctrl_get_cfg_carrier(struct drx_demod_instance *demod, struct drx_cfg_aud_ca u16 cm_thes_b = 0; if (carriers == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -14572,7 +14572,7 @@ aud_ctrl_get_cfg_carrier(struct drx_demod_instance *demod, struct drx_cfg_aud_ca /* power up */ if (ext_attr->aud_data.audio_is_active == false) { rc = power_up_aud(demod, true); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -14580,7 +14580,7 @@ aud_ctrl_get_cfg_carrier(struct drx_demod_instance *demod, struct drx_cfg_aud_ca } rc = aud_get_modus(demod, &w_modus); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -14594,7 +14594,7 @@ aud_ctrl_get_cfg_carrier(struct drx_demod_instance *demod, struct drx_cfg_aud_ca carriers->a.opt = DRX_NO_CARRIER_NOISE; break; default: - return DRX_STS_ERROR; + return -EIO; break; } @@ -14607,28 +14607,28 @@ aud_ctrl_get_cfg_carrier(struct drx_demod_instance *demod, struct drx_cfg_aud_ca carriers->b.opt = DRX_NO_CARRIER_NOISE; break; default: - return DRX_STS_ERROR; + return -EIO; break; } /* frequency adjustment for primary & secondary audio channel */ rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_RAM_DCO_A_HI__A, &dco_a_hi, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_RAM_DCO_A_LO__A, &dco_a_lo, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_RAM_DCO_B_HI__A, &dco_b_hi, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_RAM_DCO_B_LO__A, &dco_b_lo, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -14643,12 +14643,12 @@ aud_ctrl_get_cfg_carrier(struct drx_demod_instance *demod, struct drx_cfg_aud_ca /* DC level of the incoming FM signal on the primary & seconday sound channel */ rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DSP_RD_FM_DC_LEVEL_A__A, &dc_lvl_a, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DSP_RD_FM_DC_LEVEL_B__A, &dc_lvl_b, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -14659,12 +14659,12 @@ aud_ctrl_get_cfg_carrier(struct drx_demod_instance *demod, struct drx_cfg_aud_ca /* Carrier detetcion threshold for primary & secondary channel */ rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_RAM_CM_A_THRSHLD__A, &cm_thes_a, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_RAM_CM_B_THRSHLD__A, &cm_thes_b, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -14672,9 +14672,9 @@ aud_ctrl_get_cfg_carrier(struct drx_demod_instance *demod, struct drx_cfg_aud_ca carriers->a.thres = cm_thes_a; carriers->b.thres = cm_thes_b; - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -14700,7 +14700,7 @@ aud_ctrl_set_cfg_carrier(struct drx_demod_instance *demod, struct drx_cfg_aud_ca s32 valB = 0; if (carriers == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -14708,7 +14708,7 @@ aud_ctrl_set_cfg_carrier(struct drx_demod_instance *demod, struct drx_cfg_aud_ca /* power up */ if (ext_attr->aud_data.audio_is_active == false) { rc = power_up_aud(demod, true); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -14716,7 +14716,7 @@ aud_ctrl_set_cfg_carrier(struct drx_demod_instance *demod, struct drx_cfg_aud_ca } rc = aud_get_modus(demod, &r_modus); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -14732,7 +14732,7 @@ aud_ctrl_set_cfg_carrier(struct drx_demod_instance *demod, struct drx_cfg_aud_ca w_modus |= AUD_DEM_WR_MODUS_MOD_CM_A_NOISE; break; default: - return DRX_STS_INVALID_ARG; + return -EINVAL; break; } @@ -14746,14 +14746,14 @@ aud_ctrl_set_cfg_carrier(struct drx_demod_instance *demod, struct drx_cfg_aud_ca w_modus |= AUD_DEM_WR_MODUS_MOD_CM_B_NOISE; break; default: - return DRX_STS_INVALID_ARG; + return -EINVAL; break; } /* now update the modus register */ if (w_modus != r_modus) { rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DEM_WR_MODUS__A, w_modus, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -14769,34 +14769,34 @@ aud_ctrl_set_cfg_carrier(struct drx_demod_instance *demod, struct drx_cfg_aud_ca dco_b_lo = (u16) (valB & 0xFFF); rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DEM_WR_DCO_A_HI__A, dco_a_hi, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DEM_WR_DCO_A_LO__A, dco_a_lo, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DEM_WR_DCO_B_HI__A, dco_b_hi, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DEM_WR_DCO_B_LO__A, dco_b_lo, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Carrier detetcion threshold for primary & secondary channel */ rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DEM_WR_CM_A_THRSHLD__A, carriers->a.thres, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DEM_WR_CM_B_THRSHLD__A, carriers->b.thres, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -14804,9 +14804,9 @@ aud_ctrl_set_cfg_carrier(struct drx_demod_instance *demod, struct drx_cfg_aud_ca /* update DRXK data structure */ ext_attr->aud_data.carriers = *carriers; - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -14827,7 +14827,7 @@ aud_ctrl_get_cfg_mixer(struct drx_demod_instance *demod, struct drx_cfg_aud_mixe u16 fm_matr = 0; if (mixer == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -14835,7 +14835,7 @@ aud_ctrl_get_cfg_mixer(struct drx_demod_instance *demod, struct drx_cfg_aud_mixe /* power up */ if (ext_attr->aud_data.audio_is_active == false) { rc = power_up_aud(demod, true); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -14844,7 +14844,7 @@ aud_ctrl_get_cfg_mixer(struct drx_demod_instance *demod, struct drx_cfg_aud_mixe /* Source Selctor */ rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DSP_WR_SRC_I2S_MATR__A, &src_i2s_matr, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -14863,7 +14863,7 @@ aud_ctrl_get_cfg_mixer(struct drx_demod_instance *demod, struct drx_cfg_aud_mixe mixer->source_i2s = DRX_AUD_SRC_STEREO_OR_B; break; default: - return DRX_STS_ERROR; + return -EIO; } /* Matrix */ @@ -14881,12 +14881,12 @@ aud_ctrl_get_cfg_mixer(struct drx_demod_instance *demod, struct drx_cfg_aud_mixe mixer->matrix_i2s = DRX_AUD_I2S_MATRIX_B_MONO; break; default: - return DRX_STS_ERROR; + return -EIO; } /* FM Matrix */ rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_WR_FM_MATRIX__A, &fm_matr, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -14907,12 +14907,12 @@ aud_ctrl_get_cfg_mixer(struct drx_demod_instance *demod, struct drx_cfg_aud_mixe mixer->matrix_fm = DRX_AUD_FM_MATRIX_SOUND_B; break; default: - return DRX_STS_ERROR; + return -EIO; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -14933,7 +14933,7 @@ aud_ctrl_set_cfg_mixer(struct drx_demod_instance *demod, struct drx_cfg_aud_mixe u16 fm_matr = 0; if (mixer == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -14941,7 +14941,7 @@ aud_ctrl_set_cfg_mixer(struct drx_demod_instance *demod, struct drx_cfg_aud_mixe /* power up */ if (ext_attr->aud_data.audio_is_active == false) { rc = power_up_aud(demod, true); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -14950,7 +14950,7 @@ aud_ctrl_set_cfg_mixer(struct drx_demod_instance *demod, struct drx_cfg_aud_mixe /* Source Selctor */ rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DSP_WR_SRC_I2S_MATR__A, &src_i2s_matr, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -14970,7 +14970,7 @@ aud_ctrl_set_cfg_mixer(struct drx_demod_instance *demod, struct drx_cfg_aud_mixe src_i2s_matr |= AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_B; break; default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } /* Matrix */ @@ -14989,18 +14989,18 @@ aud_ctrl_set_cfg_mixer(struct drx_demod_instance *demod, struct drx_cfg_aud_mixe src_i2s_matr |= AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_SOUND_B; break; default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } /* write the result */ rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DSP_WR_SRC_I2S_MATR__A, src_i2s_matr, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* FM Matrix */ rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_WR_FM_MATRIX__A, &fm_matr, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -15022,13 +15022,13 @@ aud_ctrl_set_cfg_mixer(struct drx_demod_instance *demod, struct drx_cfg_aud_mixe fm_matr |= AUD_DEM_WR_FM_MATRIX_SOUND_B; break; default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } /* Only write if ASS is off */ if (ext_attr->aud_data.auto_sound == DRX_AUD_AUTO_SOUND_OFF) { rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DEM_WR_FM_MATRIX__A, fm_matr, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -15037,9 +15037,9 @@ aud_ctrl_set_cfg_mixer(struct drx_demod_instance *demod, struct drx_cfg_aud_mixe /* update the data structure with hardware state */ ext_attr->aud_data.mixer = *mixer; - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -15059,7 +15059,7 @@ aud_ctrl_set_cfg_av_sync(struct drx_demod_instance *demod, enum drx_cfg_aud_av_s u16 w_aud_vid_sync = 0; if (av_sync == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -15067,7 +15067,7 @@ aud_ctrl_set_cfg_av_sync(struct drx_demod_instance *demod, enum drx_cfg_aud_av_s /* power up */ if (ext_attr->aud_data.audio_is_active == false) { rc = power_up_aud(demod, true); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -15076,7 +15076,7 @@ aud_ctrl_set_cfg_av_sync(struct drx_demod_instance *demod, enum drx_cfg_aud_av_s /* audio/video synchronisation */ rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DSP_WR_AV_SYNC__A, &w_aud_vid_sync, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -15104,17 +15104,17 @@ aud_ctrl_set_cfg_av_sync(struct drx_demod_instance *demod, enum drx_cfg_aud_av_s /* OK */ break; default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DSP_WR_AV_SYNC__A, w_aud_vid_sync, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -15134,7 +15134,7 @@ aud_ctrl_get_cfg_av_sync(struct drx_demod_instance *demod, enum drx_cfg_aud_av_s u16 w_aud_vid_sync = 0; if (av_sync == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -15142,7 +15142,7 @@ aud_ctrl_get_cfg_av_sync(struct drx_demod_instance *demod, enum drx_cfg_aud_av_s /* power up */ if (ext_attr->aud_data.audio_is_active == false) { rc = power_up_aud(demod, true); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -15151,7 +15151,7 @@ aud_ctrl_get_cfg_av_sync(struct drx_demod_instance *demod, enum drx_cfg_aud_av_s /* audio/video synchronisation */ rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DSP_WR_AV_SYNC__A, &w_aud_vid_sync, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -15159,7 +15159,7 @@ aud_ctrl_get_cfg_av_sync(struct drx_demod_instance *demod, enum drx_cfg_aud_av_s if ((w_aud_vid_sync & AUD_DSP_WR_AV_SYNC_AV_ON__M) == AUD_DSP_WR_AV_SYNC_AV_ON_DISABLE) { *av_sync = DRX_AUD_AVSYNC_OFF; - return DRX_STS_OK; + return 0; } switch (w_aud_vid_sync & AUD_DSP_WR_AV_SYNC_AV_STD_SEL__M) { @@ -15173,12 +15173,12 @@ aud_ctrl_get_cfg_av_sync(struct drx_demod_instance *demod, enum drx_cfg_aud_av_s *av_sync = DRX_AUD_AVSYNC_PAL_SECAM; break; default: - return DRX_STS_ERROR; + return -EIO; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -15195,10 +15195,10 @@ aud_ctrl_get_cfg_dev(struct drx_demod_instance *demod, enum drx_cfg_aud_deviatio int rc; if (dev == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; rc = aud_get_modus(demod, &r_modus); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -15211,12 +15211,12 @@ aud_ctrl_get_cfg_dev(struct drx_demod_instance *demod, enum drx_cfg_aud_deviatio *dev = DRX_AUD_DEVIATION_HIGH; break; default: - return DRX_STS_ERROR; + return -EIO; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -15236,13 +15236,13 @@ aud_ctrl_set_cfg_dev(struct drx_demod_instance *demod, enum drx_cfg_aud_deviatio u16 r_modus = 0; if (dev == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; ext_attr = (struct drxj_data *) demod->my_ext_attr; dev_addr = demod->my_i2c_dev_addr; rc = aud_get_modus(demod, &r_modus); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -15259,13 +15259,13 @@ aud_ctrl_set_cfg_dev(struct drx_demod_instance *demod, enum drx_cfg_aud_deviatio w_modus |= AUD_DEM_WR_MODUS_MOD_HDEV_A_HIGH_DEVIATION; break; default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } /* now update the modus register */ if (w_modus != r_modus) { rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DEM_WR_MODUS__A, w_modus, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -15273,9 +15273,9 @@ aud_ctrl_set_cfg_dev(struct drx_demod_instance *demod, enum drx_cfg_aud_deviatio /* store in drxk data struct */ ext_attr->aud_data.deviation = *dev; - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -15295,7 +15295,7 @@ aud_ctrl_get_cfg_prescale(struct drx_demod_instance *demod, struct drx_cfg_aud_p u16 r_nicam_prescaler = 0; if (presc == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -15303,7 +15303,7 @@ aud_ctrl_get_cfg_prescale(struct drx_demod_instance *demod, struct drx_cfg_aud_p /* power up */ if (ext_attr->aud_data.audio_is_active == false) { rc = power_up_aud(demod, true); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -15312,12 +15312,12 @@ aud_ctrl_get_cfg_prescale(struct drx_demod_instance *demod, struct drx_cfg_aud_p /* read register data */ rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DSP_WR_NICAM_PRESC__A, &r_nicam_prescaler, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DSP_WR_FM_PRESC__A, &r_max_fm_deviation, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -15352,9 +15352,9 @@ aud_ctrl_get_cfg_prescale(struct drx_demod_instance *demod, struct drx_cfg_aud_p else presc->nicam_gain = (s16)(((s32)(log1_times100(10 * r_nicam_prescaler * r_nicam_prescaler)) - (s32)(log1_times100(10 * 16 * 16)))); - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -15374,7 +15374,7 @@ aud_ctrl_set_cfg_prescale(struct drx_demod_instance *demod, struct drx_cfg_aud_p u16 nicam_prescaler; if (presc == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -15382,7 +15382,7 @@ aud_ctrl_set_cfg_prescale(struct drx_demod_instance *demod, struct drx_cfg_aud_p /* power up */ if (ext_attr->aud_data.audio_is_active == false) { rc = power_up_aud(demod, true); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -15424,26 +15424,26 @@ aud_ctrl_set_cfg_prescale(struct drx_demod_instance *demod, struct drx_cfg_aud_p /* shift before writing to register */ nicam_prescaler <<= 8; } else { - return DRX_STS_INVALID_ARG; + return -EINVAL; } /* end of setting NICAM Prescaler */ rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DSP_WR_NICAM_PRESC__A, nicam_prescaler, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DSP_WR_FM_PRESC__A, w_max_fm_deviation, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } ext_attr->aud_data.prescale = *presc; - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -15463,7 +15463,7 @@ static int aud_ctrl_beep(struct drx_demod_instance *demod, struct drx_aud_beep * u32 frequency = 0; if (beep == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -15471,7 +15471,7 @@ static int aud_ctrl_beep(struct drx_demod_instance *demod, struct drx_aud_beep * /* power up */ if (ext_attr->aud_data.audio_is_active == false) { rc = power_up_aud(demod, true); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -15479,10 +15479,10 @@ static int aud_ctrl_beep(struct drx_demod_instance *demod, struct drx_aud_beep * } if ((beep->volume > 0) || (beep->volume < -127)) - return DRX_STS_INVALID_ARG; + return -EINVAL; if (beep->frequency > 3000) - return DRX_STS_INVALID_ARG; + return -EINVAL; volume = (u16) beep->volume + 127; the_beep |= volume << AUD_DSP_WR_BEEPER_BEEP_VOLUME__B; @@ -15496,14 +15496,14 @@ static int aud_ctrl_beep(struct drx_demod_instance *demod, struct drx_aud_beep * the_beep = 0; rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DSP_WR_BEEPER__A, the_beep, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -15529,7 +15529,7 @@ aud_ctrl_set_standard(struct drx_demod_instance *demod, enum drx_aud_standard *s u16 w_volume = 0; if (standard == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -15537,7 +15537,7 @@ aud_ctrl_set_standard(struct drx_demod_instance *demod, enum drx_aud_standard *s /* power up */ if (ext_attr->aud_data.audio_is_active == false) { rc = power_up_aud(demod, false); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -15554,50 +15554,50 @@ aud_ctrl_set_standard(struct drx_demod_instance *demod, enum drx_aud_standard *s ext_attr->aud_data.volume.mute = true; /* restore data structure from DRX ExtAttr, call volume first to mute */ rc = aud_ctrl_set_cfg_volume(demod, &ext_attr->aud_data.volume); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = aud_ctrl_set_cfg_carrier(demod, &ext_attr->aud_data.carriers); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = aud_ctrl_set_cfg_ass_thres(demod, &ext_attr->aud_data.ass_thresholds); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = aud_ctr_setl_cfg_auto_sound(demod, &ext_attr->aud_data.auto_sound); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = aud_ctrl_set_cfg_mixer(demod, &ext_attr->aud_data.mixer); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = aud_ctrl_set_cfg_av_sync(demod, &ext_attr->aud_data.av_sync); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = aud_ctrl_set_cfg_output_i2s(demod, &ext_attr->aud_data.i2sdata); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* get prescaler from presets */ rc = aud_ctrl_set_cfg_prescale(demod, &ext_attr->aud_data.prescale); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = aud_get_modus(demod, &r_modus); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -15650,7 +15650,7 @@ aud_ctrl_set_standard(struct drx_demod_instance *demod, enum drx_aud_standard *s w_standard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_AUTO; break; default: - return DRX_STS_ERROR; + return -EIO; } if (*standard == DRX_AUD_STANDARD_AUTO) { @@ -15688,14 +15688,14 @@ aud_ctrl_set_standard(struct drx_demod_instance *demod, enum drx_aud_standard *s if (w_modus != r_modus) { rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DEM_WR_MODUS__A, w_modus, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DEM_WR_STANDARD_SEL__A, w_standard, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -15710,7 +15710,7 @@ aud_ctrl_set_standard(struct drx_demod_instance *demod, enum drx_aud_standard *s w_volume |= (u16) ((volume_buffer + AUD_VOLUME_ZERO_DB) << AUD_DSP_WR_VOLUME_VOL_MAIN__B); rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DSP_WR_VOLUME__A, w_volume, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -15719,9 +15719,9 @@ aud_ctrl_set_standard(struct drx_demod_instance *demod, enum drx_aud_standard *s /* write standard selected */ ext_attr->aud_data.audio_standard = *standard; - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -15740,7 +15740,7 @@ aud_ctrl_get_standard(struct drx_demod_instance *demod, enum drx_aud_standard *s u16 r_data = 0; if (standard == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; ext_attr = (struct drxj_data *) demod->my_ext_attr; dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; @@ -15748,7 +15748,7 @@ aud_ctrl_get_standard(struct drx_demod_instance *demod, enum drx_aud_standard *s /* power up */ if (ext_attr->aud_data.audio_is_active == false) { rc = power_up_aud(demod, true); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -15758,7 +15758,7 @@ aud_ctrl_get_standard(struct drx_demod_instance *demod, enum drx_aud_standard *s *standard = DRX_AUD_STANDARD_UNKNOWN; rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_RD_STANDARD_RES__A, &r_data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -15766,7 +15766,7 @@ aud_ctrl_get_standard(struct drx_demod_instance *demod, enum drx_aud_standard *s /* return OK if the detection is not ready yet */ if (r_data >= AUD_DEM_RD_STANDARD_RES_STD_RESULT_DETECTION_STILL_ACTIVE) { *standard = DRX_AUD_STANDARD_NOT_READY; - return DRX_STS_OK; + return 0; } /* detection done, return correct standard */ @@ -15831,9 +15831,9 @@ aud_ctrl_get_standard(struct drx_demod_instance *demod, enum drx_aud_standard *s *standard = DRX_AUD_STANDARD_UNKNOWN; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } @@ -15853,7 +15853,7 @@ fm_lock_status(struct drx_demod_instance *demod, enum drx_lock_status *lock_stat /* Check detection of audio carriers */ rc = aud_ctrl_get_carrier_detect_status(demod, &status); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -15864,10 +15864,10 @@ fm_lock_status(struct drx_demod_instance *demod, enum drx_lock_status *lock_stat else *lock_stat = DRX_NOT_LOCKED; - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -15888,7 +15888,7 @@ fm_sig_quality(struct drx_demod_instance *demod, struct drx_sig_quality *sig_qua int rc; rc = fm_lock_status(demod, &lock_status); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -15897,10 +15897,10 @@ fm_sig_quality(struct drx_demod_instance *demod, struct drx_sig_quality *sig_qua else sig_quality->indicator = 0; - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } #endif @@ -15943,7 +15943,7 @@ get_oob_lock_status(struct drx_demod_instance *demod, scu_cmd.parameter_len = 0; rc = scu_command(dev_addr, &scu_cmd); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -15969,9 +15969,9 @@ get_oob_lock_status(struct drx_demod_instance *demod, /* *oob_lock = scu_cmd.result[1]; */ - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /** @@ -16009,7 +16009,7 @@ get_oob_symbol_rate_offset(struct i2c_device_addr *dev_addr, s32 *symbol_rate_of *symbol_rate_offset = 0; /* read data rate */ rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_ORX_RF_RX_DATA_RATE__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -16029,11 +16029,11 @@ get_oob_symbol_rate_offset(struct i2c_device_addr *dev_addr, s32 *symbol_rate_of symbol_rate = 1544000; /* bps */ break; default: - return DRX_STS_ERROR; + return -EIO; } rc = DRXJ_DAP.read_reg16func(dev_addr, ORX_CON_CTI_DTI_R__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -16059,9 +16059,9 @@ get_oob_symbol_rate_offset(struct i2c_device_addr *dev_addr, s32 *symbol_rate_of *symbol_rate_offset = timing_offset; - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /** @@ -16094,7 +16094,7 @@ get_oob_freq_offset(struct drx_demod_instance *demod, s32 *freq_offset) /* check arguments */ if ((demod == NULL) || (freq_offset == NULL)) - return DRX_STS_INVALID_ARG; + return -EINVAL; dev_addr = demod->my_i2c_dev_addr; common_attr = (struct drx_common_attr *) demod->my_common_attr; @@ -16103,14 +16103,14 @@ get_oob_freq_offset(struct drx_demod_instance *demod, s32 *freq_offset) /* read sign (spectrum inversion) */ rc = DRXJ_DAP.read_reg16func(dev_addr, ORX_FWP_IQM_FRQ_W__A, &rot, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* read frequency offset */ rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_ORX_FRQ_OFFSET__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -16128,7 +16128,7 @@ get_oob_freq_offset(struct drx_demod_instance *demod, s32 *freq_offset) coarse_freq_offset = coarse_sign * frac(temp_freq_offset, 1000, FRAC_ROUND); /* KHz */ /* read data rate */ rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_ORX_RF_RX_DATA_RATE__A, &symbol_rate_reg, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -16148,13 +16148,13 @@ get_oob_freq_offset(struct drx_demod_instance *demod, s32 *freq_offset) symbol_rate = 1544000; break; default: - return DRX_STS_ERROR; + return -EIO; } /* find FINE frequency offset */ /* fine_freq_offset = ( (CORRECTION_VALUE*symbol_rate) >> 18 ); */ rc = DRXJ_DAP.read_reg16func(dev_addr, ORX_CON_CPH_FRQ_R__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -16176,9 +16176,9 @@ get_oob_freq_offset(struct drx_demod_instance *demod, s32 *freq_offset) else *freq_offset = (coarse_freq_offset + fine_freq_offset); - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /** @@ -16205,7 +16205,7 @@ get_oob_frequency(struct drx_demod_instance *demod, s32 *frequency) *frequency = 0; /* KHz */ rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -16213,16 +16213,16 @@ get_oob_frequency(struct drx_demod_instance *demod, s32 *frequency) freq = (s32) ((s32) data * 50 + 50000L); rc = get_oob_freq_offset(demod, &freq_offset); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } *frequency = freq + freq_offset; - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /** @@ -16243,7 +16243,7 @@ static int get_oobmer(struct i2c_device_addr *dev_addr, u32 *mer) *mer = 0; /* READ MER */ rc = DRXJ_DAP.read_reg16func(dev_addr, ORX_EQU_MER_MER_R__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -16368,9 +16368,9 @@ static int get_oobmer(struct i2c_device_addr *dev_addr, u32 *mer) *mer = 0; break; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } #endif /*#ifndef DRXJ_DIGITAL_ONLY */ @@ -16389,7 +16389,7 @@ static int set_orx_nsu_aox(struct drx_demod_instance *demod, bool active) /* Configure NSU_AOX */ rc = DRXJ_DAP.read_reg16func(dev_addr, ORX_NSU_AOX_STDBY_W__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -16398,14 +16398,14 @@ static int set_orx_nsu_aox(struct drx_demod_instance *demod, bool active) else data |= (ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON); rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_NSU_AOX_STDBY_W__A, data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /** @@ -16473,28 +16473,28 @@ static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_par scu_cmd.result_len = 1; scu_cmd.result = cmd_result; rc = scu_command(dev_addr, &scu_cmd); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = set_orx_nsu_aox(demod, false); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } ext_attr->oob_power_on = false; - return DRX_STS_OK; + return 0; } freq = oob_param->frequency; if ((freq < 70000) || (freq > 130000)) - return DRX_STS_ERROR; + return -EIO; freq = (freq - 50000) / 50; { @@ -16515,7 +16515,7 @@ static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_par /* Stop */ /*********/ rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -16525,7 +16525,7 @@ static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_par scu_cmd.result_len = 1; scu_cmd.result = cmd_result; rc = scu_command(dev_addr, &scu_cmd); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -16538,7 +16538,7 @@ static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_par scu_cmd.result_len = 1; scu_cmd.result = cmd_result; rc = scu_command(dev_addr, &scu_cmd); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -16614,266 +16614,266 @@ static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_par scu_cmd.result = cmd_result; mode_index = mode_val[(set_param_parameters[0] & 0xC0) >> 6]; rc = scu_command(dev_addr, &scu_cmd); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Write magic word to enable pdr reg write */ rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_OOB_CRX_CFG__A, OOB_CRX_DRIVE_STRENGTH << SIO_PDR_OOB_CRX_CFG_DRIVE__B | 0x03 << SIO_PDR_OOB_CRX_CFG_MODE__B, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_OOB_DRX_CFG__A, OOB_DRX_DRIVE_STRENGTH << SIO_PDR_OOB_DRX_CFG_DRIVE__B | 0x03 << SIO_PDR_OOB_DRX_CFG_MODE__B, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Write magic word to disable pdr reg write */ rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_TOP_COMM_KEY__A, 0, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_FWP_AAG_LEN_W__A, 16000, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_FWP_AAG_THR_W__A, 40, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* ddc */ rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_DDC_OFO_SET_W__A, ORX_DDC_OFO_SET_W__PRE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* nsu */ rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_NSU_AOX_LOPOW_W__A, ext_attr->oob_lo_pow, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* initialization for target mode */ rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_TARGET_MODE__A, SCU_RAM_ORX_TARGET_MODE_2048KBPS_SQRT, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_FREQ_GAIN_CORR__A, SCU_RAM_ORX_FREQ_GAIN_CORR_2048KBPS, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Reset bits for timing and freq. recovery */ rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_RST_CPH__A, 0x0001, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_RST_CTI__A, 0x0002, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_RST_KRN__A, 0x0004, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_RST_KRP__A, 0x0008, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* AGN_LOCK = {2048>>3, -2048, 8, -8, 0, 1}; */ rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_AGN_LOCK_TH__A, 2048 >> 3, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_AGN_LOCK_TOTH__A, (u16)(-2048), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_AGN_ONLOCK_TTH__A, 8, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_AGN_UNLOCK_TTH__A, (u16)(-8), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_AGN_LOCK_MASK__A, 1, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* DGN_LOCK = {10, -2048, 8, -8, 0, 1<<1}; */ rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_DGN_LOCK_TH__A, 10, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_DGN_LOCK_TOTH__A, (u16)(-2048), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_DGN_ONLOCK_TTH__A, 8, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_DGN_UNLOCK_TTH__A, (u16)(-8), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_DGN_LOCK_MASK__A, 1 << 1, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* FRQ_LOCK = {15,-2048, 8, -8, 0, 1<<2}; */ rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TH__A, 17, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TOTH__A, (u16)(-2048), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_FRQ_ONLOCK_TTH__A, 8, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_FRQ_UNLOCK_TTH__A, (u16)(-8), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_FRQ_LOCK_MASK__A, 1 << 2, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* PHA_LOCK = {5000, -2048, 8, -8, 0, 1<<3}; */ rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_PHA_LOCK_TH__A, 3000, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_PHA_LOCK_TOTH__A, (u16)(-2048), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_PHA_ONLOCK_TTH__A, 8, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_PHA_UNLOCK_TTH__A, (u16)(-8), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_PHA_LOCK_MASK__A, 1 << 3, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* TIM_LOCK = {300, -2048, 8, -8, 0, 1<<4}; */ rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_TIM_LOCK_TH__A, 400, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_TIM_LOCK_TOTH__A, (u16)(-2048), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_TIM_ONLOCK_TTH__A, 8, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_TIM_UNLOCK_TTH__A, (u16)(-8), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_TIM_LOCK_MASK__A, 1 << 4, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* EQU_LOCK = {20, -2048, 8, -8, 0, 1<<5}; */ rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_EQU_LOCK_TH__A, 20, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_EQU_LOCK_TOTH__A, (u16)(-2048), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_EQU_ONLOCK_TTH__A, 4, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_EQU_UNLOCK_TTH__A, (u16)(-4), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_EQU_LOCK_MASK__A, 1 << 5, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* PRE-Filter coefficients (PFI) */ rc = DRXJ_DAP.write_block_func(dev_addr, ORX_FWP_PFI_A_W__A, sizeof(pfi_coeffs[mode_index]), ((u8 *)pfi_coeffs[mode_index]), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_TOP_MDE_W__A, mode_index, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -16881,23 +16881,23 @@ static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_par /* NYQUIST-Filter coefficients (NYQ) */ for (i = 0; i < (NYQFILTERLEN + 1) / 2; i++) { rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_FWP_NYQ_ADR_W__A, i, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_FWP_NYQ_COF_RW__A, nyquist_coeffs[mode_index][i], 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_FWP_NYQ_ADR_W__A, 31, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_ACTIVE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -16910,28 +16910,28 @@ static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_par scu_cmd.result_len = 1; scu_cmd.result = cmd_result; rc = scu_command(dev_addr, &scu_cmd); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = set_orx_nsu_aox(demod, true); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_NSU_AOX_STHR_W__A, ext_attr->oob_pre_saw, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } ext_attr->oob_power_on = true; - return DRX_STS_OK; + return 0; rw_error: #endif - return DRX_STS_ERROR; + return -EIO; } /** @@ -16955,62 +16955,62 @@ ctrl_get_oob(struct drx_demod_instance *demod, struct drxoob_status *oob_status) /* check arguments */ if (oob_status == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; if (!ext_attr->oob_power_on) - return DRX_STS_ERROR; + return -EIO; rc = DRXJ_DAP.read_reg16func(dev_addr, ORX_DDC_OFO_SET_W__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.read_reg16func(dev_addr, ORX_NSU_TUN_RFGAIN_W__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.read_reg16func(dev_addr, ORX_FWP_AAG_THR_W__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_ORX_DGN_KI__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.read_reg16func(dev_addr, ORX_FWP_SRC_DGN_W__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = get_oob_lock_status(demod, dev_addr, &oob_status->lock); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = get_oob_frequency(demod, &oob_status->frequency); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = get_oobmer(dev_addr, &oob_status->mer); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = get_oob_symbol_rate_offset(dev_addr, &oob_status->symbol_rate_offset); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - return DRX_STS_OK; + return 0; rw_error: #endif - return DRX_STS_ERROR; + return -EIO; } /** @@ -17028,20 +17028,20 @@ ctrl_set_cfg_oob_pre_saw(struct drx_demod_instance *demod, u16 *cfg_data) int rc; if (cfg_data == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_NSU_AOX_STHR_W__A, *cfg_data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } ext_attr->oob_pre_saw = *cfg_data; - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } #endif @@ -17058,13 +17058,13 @@ ctrl_get_cfg_oob_pre_saw(struct drx_demod_instance *demod, u16 *cfg_data) struct drxj_data *ext_attr = NULL; if (cfg_data == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; ext_attr = (struct drxj_data *) demod->my_ext_attr; *cfg_data = ext_attr->oob_pre_saw; - return DRX_STS_OK; + return 0; } #endif @@ -17082,20 +17082,20 @@ ctrl_set_cfg_oob_lo_power(struct drx_demod_instance *demod, enum drxj_cfg_oob_lo int rc; if (cfg_data == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_NSU_AOX_LOPOW_W__A, *cfg_data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } ext_attr->oob_lo_pow = *cfg_data; - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } #endif @@ -17111,13 +17111,13 @@ ctrl_get_cfg_oob_lo_power(struct drx_demod_instance *demod, enum drxj_cfg_oob_lo struct drxj_data *ext_attr = NULL; if (cfg_data == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; ext_attr = (struct drxj_data *) demod->my_ext_attr; *cfg_data = ext_attr->oob_lo_pow; - return DRX_STS_OK; + return 0; } #endif /*============================================================================*/ @@ -17164,7 +17164,7 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) #endif /*== check arguments ======================================================*/ if ((demod == NULL) || (channel == NULL)) - return DRX_STS_INVALID_ARG; + return -EINVAL; common_attr = (struct drx_common_attr *) demod->my_common_attr; dev_addr = demod->my_i2c_dev_addr; @@ -17191,7 +17191,7 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) break; case DRX_STANDARD_UNKNOWN: default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } /* check bandwidth QAM annex B, NTSC and 8VSB */ @@ -17206,7 +17206,7 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) case DRX_BANDWIDTH_8MHZ: /* fall through */ case DRX_BANDWIDTH_7MHZ: /* fall through */ default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } } #ifndef DRXJ_DIGITAL_ONLY @@ -17219,7 +17219,7 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) case DRX_BANDWIDTH_6MHZ: /* fall through */ case DRX_BANDWIDTH_UNKNOWN: /* fall through */ default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } } /* check bandwidth PAL/SECAM */ @@ -17236,7 +17236,7 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) case DRX_BANDWIDTH_6MHZ: /* fall through */ case DRX_BANDWIDTH_7MHZ: /* fall through */ default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } } #endif @@ -17256,14 +17256,14 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) max_symbol_rate = DRXJ_QAM_SYMBOLRATE_MAX; /* config SMA_TX pin to SAW switch mode */ rc = ctrl_set_uio_cfg(demod, &uio_cfg); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } if (channel->symbolrate < min_symbol_rate || channel->symbolrate > max_symbol_rate) { - return DRX_STS_INVALID_ARG; + return -EINVAL; } switch (channel->constellation) { @@ -17288,7 +17288,7 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) } break; default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } } @@ -17302,7 +17302,7 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) case DRX_CONSTELLATION_QAM64: break; default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } switch (channel->interleavemode) { @@ -17327,7 +17327,7 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) case DRX_INTERLEAVEMODE_AUTO: break; default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } } @@ -17347,18 +17347,18 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) break; case DRX_BANDWIDTH_UNKNOWN: default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } rc = ctrl_uio_write(demod, &uio1); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } #endif /* DRXJ_VSB_ONLY */ rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -17397,7 +17397,7 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) break; case DRX_STANDARD_UNKNOWN: default: - return DRX_STS_ERROR; + return -EIO; } /* switch(standard) */ tuner_mode |= TUNER_MODE_SWITCH; @@ -17418,7 +17418,7 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) */ tuner_mode |= TUNER_MODE_6MHZ; break; - /* return (DRX_STS_INVALID_ARG); */ + /* return (-EINVAL); */ } /* store bandwidth for GetChannel() */ @@ -17429,7 +17429,7 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) /* close tuner bridge */ bridge_closed = true; rc = ctrl_i2c_bridge(demod, &bridge_closed); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -17437,7 +17437,7 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) } rc = drxbsp_tuner_set_frequency(demod->my_tuner, tuner_mode, tuner_set_freq); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -17445,7 +17445,7 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) /* open tuner bridge */ bridge_closed = false; rc = ctrl_i2c_bridge(demod, &bridge_closed); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -17453,7 +17453,7 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) /* Get actual frequency set by tuner and compute offset */ rc = drxbsp_tuner_get_frequency(demod->my_tuner, 0, &tuner_get_freq, &intermediate_freq); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -17473,12 +17473,12 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) else ext_attr->mirror = channel->mirror; rc = set_vsb(demod); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = set_frequency(demod, channel, tuner_freq_offset); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -17496,7 +17496,7 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) else ext_attr->mirror = channel->mirror; rc = set_atv_channel(demod, tuner_freq_offset, channel, standard); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -17507,7 +17507,7 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) case DRX_STANDARD_ITU_B: /* fallthrough */ case DRX_STANDARD_ITU_C: rc = set_qam_channel(demod, channel, tuner_freq_offset); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -17515,7 +17515,7 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) #endif case DRX_STANDARD_UNKNOWN: default: - return DRX_STS_ERROR; + return -EIO; } /*== Re-tune, slow mode ===================================================*/ @@ -17528,7 +17528,7 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) /* close tuner bridge */ bridge_closed = true; rc = ctrl_i2c_bridge(demod, &bridge_closed); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -17536,7 +17536,7 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) /* set tuner frequency */ rc = drxbsp_tuner_set_frequency(demod->my_tuner, tuner_mode, tuner_set_freq); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -17544,7 +17544,7 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) /* open tuner bridge */ bridge_closed = false; rc = ctrl_i2c_bridge(demod, &bridge_closed); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -17555,9 +17555,9 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) /* flag the packet error counter reset */ ext_attr->reset_pkt_err_acc = true; - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================= @@ -17590,7 +17590,7 @@ ctrl_get_channel(struct drx_demod_instance *demod, struct drx_channel *channel) /* check arguments */ if ((demod == NULL) || (channel == NULL)) - return DRX_STS_INVALID_ARG; + return -EINVAL; dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -17620,7 +17620,7 @@ ctrl_get_channel(struct drx_demod_instance *demod, struct drx_channel *channel) /* Get frequency from tuner */ rc = drxbsp_tuner_get_frequency(demod->my_tuner, 0, &(channel->frequency), &intermediate_freq); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -17642,13 +17642,13 @@ ctrl_get_channel(struct drx_demod_instance *demod, struct drx_channel *channel) /* check lock status */ rc = ctrl_lock_status(demod, &lock_status); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } if ((lock_status == DRX_LOCKED) || (lock_status == DRXJ_DEMOD_LOCK)) { rc = drxj_dap_atomic_read_reg32(dev_addr, IQM_RC_RATE_LO__A, &iqm_rc_rate_lo, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -17662,7 +17662,7 @@ ctrl_get_channel(struct drx_demod_instance *demod, struct drx_channel *channel) channel->bandwidth = DRX_BANDWIDTH_6MHZ; /* get the channel frequency */ rc = get_ctl_freq_offset(demod, &ctl_freq_offset); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -17677,7 +17677,7 @@ ctrl_get_channel(struct drx_demod_instance *demod, struct drx_channel *channel) { /* get the channel frequency */ rc = get_ctl_freq_offset(demod, &ctl_freq_offset); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -17714,7 +17714,7 @@ ctrl_get_channel(struct drx_demod_instance *demod, struct drx_channel *channel) } /* if (standard == DRX_STANDARD_ITU_B) */ { - struct drxjscu_cmd cmd_scu = { 0, 0, NULL, NULL }; + struct drxjscu_cmd cmd_scu = { 0, 0, 0, NULL, NULL }; u16 cmd_result[3] = { 0, 0, 0 }; cmd_scu.command = @@ -17725,7 +17725,7 @@ ctrl_get_channel(struct drx_demod_instance *demod, struct drx_channel *channel) cmd_scu.parameter = NULL; cmd_scu.result = cmd_result; rc = scu_command(dev_addr, &cmd_scu); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -17759,7 +17759,7 @@ ctrl_get_channel(struct drx_demod_instance *demod, struct drx_channel *channel) default: channel->constellation = DRX_CONSTELLATION_UNKNOWN; - return DRX_STS_ERROR; + return -EIO; } } break; @@ -17773,7 +17773,7 @@ ctrl_get_channel(struct drx_demod_instance *demod, struct drx_channel *channel) case DRX_STANDARD_PAL_SECAM_LP: case DRX_STANDARD_FM: rc = get_atv_channel(demod, channel, standard); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -17781,16 +17781,16 @@ ctrl_get_channel(struct drx_demod_instance *demod, struct drx_channel *channel) #endif case DRX_STANDARD_UNKNOWN: /* fall trough */ default: - return DRX_STS_ERROR; + return -EIO; } /* switch ( standard ) */ if (lock_status == DRX_LOCKED) channel->mirror = ext_attr->mirror; } /* if ( lock_status == DRX_LOCKED ) */ - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================= @@ -17825,9 +17825,9 @@ mer2indicator(u16 mer, u16 min_mer, u16 threshold_mer, u16 max_mer) * \param devmod Pointer to demodulator instance. * \param sig_quality Pointer to signal quality data. * \return int. -* \retval DRX_STS_OK sig_quality contains valid data. -* \retval DRX_STS_INVALID_ARG sig_quality is NULL. -* \retval DRX_STS_ERROR Erroneous data, sig_quality contains invalid data. +* \retval 0 sig_quality contains valid data. +* \retval -EINVAL sig_quality is NULL. +* \retval -EIO Erroneous data, sig_quality contains invalid data. */ static int @@ -17844,7 +17844,7 @@ ctrl_sig_quality(struct drx_demod_instance *demod, struct drx_sig_quality *sig_q /* Check arguments */ if ((sig_quality == NULL) || (demod == NULL)) - return DRX_STS_INVALID_ARG; + return -EINVAL; ext_attr = (struct drxj_data *) demod->my_ext_attr; standard = ext_attr->standard; @@ -17852,7 +17852,7 @@ ctrl_sig_quality(struct drx_demod_instance *demod, struct drx_sig_quality *sig_q /* get basic information */ dev_addr = demod->my_i2c_dev_addr; rc = ctrl_lock_status(demod, &lock_status); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -17860,13 +17860,13 @@ ctrl_sig_quality(struct drx_demod_instance *demod, struct drx_sig_quality *sig_q case DRX_STANDARD_8VSB: #ifdef DRXJ_SIGNAL_ACCUM_ERR rc = get_acc_pkt_err(demod, &sig_quality->packet_error); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } #else rc = get_vsb_post_rs_pck_err(dev_addr, &sig_quality->packet_error); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -17878,17 +17878,17 @@ ctrl_sig_quality(struct drx_demod_instance *demod, struct drx_sig_quality *sig_q } else { /* PostViterbi is compute in steps of 10^(-6) */ rc = get_vs_bpre_viterbi_ber(dev_addr, &sig_quality->pre_viterbi_ber); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = get_vs_bpost_viterbi_ber(dev_addr, &sig_quality->post_viterbi_ber); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = get_vsbmer(dev_addr, &sig_quality->MER); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -17907,7 +17907,7 @@ ctrl_sig_quality(struct drx_demod_instance *demod, struct drx_sig_quality *sig_q case DRX_STANDARD_ITU_B: case DRX_STANDARD_ITU_C: rc = ctrl_get_qam_sig_quality(demod, sig_quality); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -17930,7 +17930,7 @@ ctrl_sig_quality(struct drx_demod_instance *demod, struct drx_sig_quality *sig_q break; default: sig_quality->MER = 0; - return DRX_STS_ERROR; + return -EIO; } } @@ -17950,7 +17950,7 @@ ctrl_sig_quality(struct drx_demod_instance *demod, struct drx_sig_quality *sig_q case DRX_CONSTELLATION_QAM16: break; default: - return DRX_STS_ERROR; + return -EIO; } sig_quality->indicator = mer2indicator(sig_quality->MER, min_mer, threshold_mer, @@ -17965,26 +17965,26 @@ ctrl_sig_quality(struct drx_demod_instance *demod, struct drx_sig_quality *sig_q case DRX_STANDARD_PAL_SECAM_LP: case DRX_STANDARD_NTSC: rc = atv_sig_quality(demod, sig_quality); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } break; case DRX_STANDARD_FM: rc = fm_sig_quality(demod, sig_quality); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } break; #endif default: - return DRX_STS_ERROR; + return -EIO; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -18015,7 +18015,7 @@ ctrl_lock_status(struct drx_demod_instance *demod, enum drx_lock_status *lock_st /* check arguments */ if ((demod == NULL) || (lock_stat == NULL)) - return DRX_STS_INVALID_ARG; + return -EINVAL; dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -18053,7 +18053,7 @@ ctrl_lock_status(struct drx_demod_instance *demod, enum drx_lock_status *lock_st #endif case DRX_STANDARD_UNKNOWN: /* fallthrough */ default: - return DRX_STS_ERROR; + return -EIO; } /* define the SCU command paramters and execute the command */ @@ -18062,7 +18062,7 @@ ctrl_lock_status(struct drx_demod_instance *demod, enum drx_lock_status *lock_st cmd_scu.parameter = NULL; cmd_scu.result = cmd_result; rc = scu_command(dev_addr, &cmd_scu); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -18083,9 +18083,9 @@ ctrl_lock_status(struct drx_demod_instance *demod, enum drx_lock_status *lock_st *lock_stat = DRX_NEVER_LOCK; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -18107,7 +18107,7 @@ ctrl_constel(struct drx_demod_instance *demod, struct drx_complex *complex_nr) /* check arguments */ if ((demod == NULL) || (complex_nr == NULL)) - return DRX_STS_INVALID_ARG; + return -EINVAL; /* read device info */ standard = ((struct drxj_data *) demod->my_ext_attr)->standard; @@ -18116,7 +18116,7 @@ ctrl_constel(struct drx_demod_instance *demod, struct drx_complex *complex_nr) switch (standard) { case DRX_STANDARD_8VSB: rc = ctrl_get_vsb_constel(demod, complex_nr); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -18126,7 +18126,7 @@ ctrl_constel(struct drx_demod_instance *demod, struct drx_complex *complex_nr) case DRX_STANDARD_ITU_B: /* fallthrough */ case DRX_STANDARD_ITU_C: rc = ctrl_get_qam_constel(demod, complex_nr); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -18134,12 +18134,12 @@ ctrl_constel(struct drx_demod_instance *demod, struct drx_complex *complex_nr) #endif case DRX_STANDARD_UNKNOWN: default: - return DRX_STS_ERROR; + return -EIO; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -18163,7 +18163,7 @@ ctrl_set_standard(struct drx_demod_instance *demod, enum drx_standard *standard) /* check arguments */ if ((standard == NULL) || (demod == NULL)) - return DRX_STS_INVALID_ARG; + return -EINVAL; ext_attr = (struct drxj_data *) demod->my_ext_attr; prev_standard = ext_attr->standard; @@ -18177,7 +18177,7 @@ ctrl_set_standard(struct drx_demod_instance *demod, enum drx_standard *standard) case DRX_STANDARD_ITU_B: /* fallthrough */ case DRX_STANDARD_ITU_C: rc = power_down_qam(demod, false); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -18185,7 +18185,7 @@ ctrl_set_standard(struct drx_demod_instance *demod, enum drx_standard *standard) #endif case DRX_STANDARD_8VSB: rc = power_down_vsb(demod, false); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -18199,7 +18199,7 @@ ctrl_set_standard(struct drx_demod_instance *demod, enum drx_standard *standard) case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */ case DRX_STANDARD_PAL_SECAM_LP: rc = power_down_atv(demod, prev_standard, false); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -18210,7 +18210,7 @@ ctrl_set_standard(struct drx_demod_instance *demod, enum drx_standard *standard) break; case DRX_STANDARD_AUTO: /* fallthrough */ default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } /* @@ -18227,7 +18227,7 @@ ctrl_set_standard(struct drx_demod_instance *demod, enum drx_standard *standard) do { u16 dummy; rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SCU_RAM_VERSION_HI__A, &dummy, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -18236,7 +18236,7 @@ ctrl_set_standard(struct drx_demod_instance *demod, enum drx_standard *standard) #endif case DRX_STANDARD_8VSB: rc = set_vsb_leak_n_gain(demod); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -18250,12 +18250,12 @@ ctrl_set_standard(struct drx_demod_instance *demod, enum drx_standard *standard) case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */ case DRX_STANDARD_PAL_SECAM_LP: rc = set_atv_standard(demod, standard); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = power_up_atv(demod, *standard); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -18263,15 +18263,15 @@ ctrl_set_standard(struct drx_demod_instance *demod, enum drx_standard *standard) #endif default: ext_attr->standard = DRX_STANDARD_UNKNOWN; - return DRX_STS_INVALID_ARG; + return -EINVAL; break; } - return DRX_STS_OK; + return 0; rw_error: /* Don't know what the standard is now ... try again */ ext_attr->standard = DRX_STANDARD_UNKNOWN; - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -18294,21 +18294,21 @@ ctrl_get_standard(struct drx_demod_instance *demod, enum drx_standard *standard) /* check arguments */ if (standard == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; *standard = ext_attr->standard; do { u16 dummy; rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SCU_RAM_VERSION_HI__A, &dummy, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } while (0); - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -18329,7 +18329,7 @@ ctrl_get_cfg_symbol_clock_offset(struct drx_demod_instance *demod, s32 *rate_off /* check arguments */ if (rate_offset == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; ext_attr = (struct drxj_data *) demod->my_ext_attr; standard = ext_attr->standard; @@ -18342,7 +18342,7 @@ ctrl_get_cfg_symbol_clock_offset(struct drx_demod_instance *demod, s32 *rate_off case DRX_STANDARD_ITU_C: #endif rc = get_str_freq_offset(demod, rate_offset); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -18350,12 +18350,12 @@ ctrl_get_cfg_symbol_clock_offset(struct drx_demod_instance *demod, s32 *rate_off case DRX_STANDARD_NTSC: case DRX_STANDARD_UNKNOWN: default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -18366,9 +18366,9 @@ rw_error: * \param demod Pointer to demodulator instance. * \param mode Pointer to new power mode. * \return int. -* \retval DRX_STS_OK Success -* \retval DRX_STS_ERROR I2C error or other failure -* \retval DRX_STS_INVALID_ARG Invalid mode argument. +* \retval 0 Success +* \retval -EIO I2C error or other failure +* \retval -EINVAL Invalid mode argument. * * */ @@ -18387,11 +18387,11 @@ ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode) /* Check arguments */ if (mode == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; /* If already in requested power mode, do nothing */ if (common_attr->current_power_mode == *mode) - return DRX_STS_OK; + return 0; switch (*mode) { case DRX_POWER_UP: @@ -18409,14 +18409,14 @@ ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode) break; default: /* Unknow sleep mode */ - return DRX_STS_INVALID_ARG; + return -EINVAL; break; } /* Check if device needs to be powered up */ if ((common_attr->current_power_mode != DRX_POWER_UP)) { rc = power_up_device(demod); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -18441,14 +18441,14 @@ ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode) case DRX_STANDARD_ITU_B: case DRX_STANDARD_ITU_C: rc = power_down_qam(demod, true); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } break; case DRX_STANDARD_8VSB: rc = power_down_vsb(demod, true); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -18461,7 +18461,7 @@ ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode) case DRX_STANDARD_NTSC: /* fallthrough */ case DRX_STANDARD_FM: rc = power_down_atv(demod, ext_attr->standard, true); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -18471,31 +18471,31 @@ ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode) break; case DRX_STANDARD_AUTO: /* fallthrough */ default: - return DRX_STS_ERROR; + return -EIO; } if (*mode != DRXJ_POWER_DOWN_MAIN_PATH) { rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Initialize HI, wakeup key especially before put IC to sleep */ rc = init_hi(demod); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } ext_attr->hi_cfg_ctrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; rc = hi_cfg_command(demod); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -18504,9 +18504,9 @@ ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode) common_attr->current_power_mode = *mode; - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -18549,8 +18549,8 @@ ctrl_version(struct drx_demod_instance *demod, struct drx_version_list **version u16 mfx = 0; u16 bid = 0; u16 key = 0; - static const char ucode_name[] = "Microcode"; - static const char device_name[] = "Device"; + static char ucode_name[] = "Microcode"; + static char device_name[] = "Device"; dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -18564,12 +18564,12 @@ ctrl_version(struct drx_demod_instance *demod, struct drx_version_list **version if (common_attr->is_opened == true) { rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_VERSION_HI__A, &ucode_major_minor, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_VERSION_LO__A, &ucode_patch, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -18624,27 +18624,27 @@ ctrl_version(struct drx_demod_instance *demod, struct drx_version_list **version /* Device version *************************************** */ /* Check device id */ rc = DRXJ_DAP.read_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, &key, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.read_reg32func(dev_addr, SIO_TOP_JTAGID_LO__A, &jtag, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.read_reg16func(dev_addr, SIO_PDR_UIO_IN_HI__A, &bid, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, key, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -18686,11 +18686,11 @@ ctrl_version(struct drx_demod_instance *demod, struct drx_version_list **version *version_list = &(ext_attr->v_list_elements[0]); - return DRX_STS_OK; + return 0; rw_error: *version_list = (struct drx_version_list *) (NULL); - return DRX_STS_ERROR; + return -EIO; } @@ -18701,8 +18701,8 @@ rw_error: * \brief Probe device, check if it is present * \param demod Pointer to demodulator instance. * \return int. -* \retval DRX_STS_OK a drx39xxj device has been detected. -* \retval DRX_STS_ERROR no drx39xxj device detected. +* \retval 0 a drx39xxj device has been detected. +* \retval -EIO no drx39xxj device detected. * * This funtion can be caled before open() and after close(). * @@ -18711,7 +18711,7 @@ rw_error: static int ctrl_probe_device(struct drx_demod_instance *demod) { enum drx_power_mode org_power_mode = DRX_POWER_UP; - int ret_status = DRX_STS_OK; + int ret_status = 0; struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL); int rc; @@ -18730,7 +18730,7 @@ static int ctrl_probe_device(struct drx_demod_instance *demod) if (demod->my_common_attr->is_opened == false) { rc = power_up_device(demod); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -18738,21 +18738,21 @@ static int ctrl_probe_device(struct drx_demod_instance *demod) } else { /* Wake-up device, feedback from device */ rc = ctrl_power_mode(demod, &power_mode); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } /* Initialize HI, wakeup key especially */ rc = init_hi(demod); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Check device id */ rc = DRXJ_DAP.read_reg32func(dev_addr, SIO_TOP_JTAGID_LO__A, &jtag, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -18771,14 +18771,14 @@ static int ctrl_probe_device(struct drx_demod_instance *demod) /* ok , do nothing */ break; default: - ret_status = DRX_STS_ERROR; + ret_status = -EIO; break; } /* Device was not opened, return to orginal powermode, feedback from device */ rc = ctrl_power_mode(demod, &org_power_mode); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -18788,7 +18788,7 @@ static int ctrl_probe_device(struct drx_demod_instance *demod) do { u16 dummy; rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SCU_RAM_VERSION_HI__A, &dummy, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -18799,7 +18799,7 @@ static int ctrl_probe_device(struct drx_demod_instance *demod) rw_error: common_attr->current_power_mode = org_power_mode; - return DRX_STS_ERROR; + return -EIO; } #ifdef DRXJ_SPLIT_UCODE_UPLOAD @@ -18852,7 +18852,7 @@ ctrl_u_code_upload(struct drx_demod_instance *demod, /* Check arguments */ if ((mc_info == NULL) || (mc_info->mc_data == NULL) || (mc_info->mc_size == 0)) { - return DRX_STS_INVALID_ARG; + return -EINVAL; } mc_data = mc_info->mc_data; @@ -18865,7 +18865,7 @@ ctrl_u_code_upload(struct drx_demod_instance *demod, if ((mc_magic_word != DRXJ_UCODE_MAGIC_WORD) || (mc_nr_of_blks == 0)) { /* wrong endianess or wrong data ? */ - return DRX_STS_INVALID_ARG; + return -EINVAL; } /* Process microcode blocks */ @@ -18894,7 +18894,7 @@ ctrl_u_code_upload(struct drx_demod_instance *demod, (block_hdr.CRC != u_code_compute_crc(mc_data, block_hdr.size))) ) { /* Wrong data ! */ - return DRX_STS_INVALID_ARG; + return -EINVAL; } mc_block_nr_bytes = block_hdr.size * sizeof(u16); @@ -18913,8 +18913,8 @@ ctrl_u_code_upload(struct drx_demod_instance *demod, addr, mc_block_nr_bytes, mc_data, 0x0000) != - DRX_STS_OK) { - return DRX_STS_ERROR; + 0) { + return -EIO; } } break; @@ -18948,8 +18948,8 @@ ctrl_u_code_upload(struct drx_demod_instance *demod, (u8 *) mc_data_buffer, 0x0000) != - DRX_STS_OK) { - return DRX_STS_ERROR; + 0) { + return -EIO; } result = @@ -18958,7 +18958,7 @@ ctrl_u_code_upload(struct drx_demod_instance *demod, bytes_to_compare); if (result != 0) - return DRX_STS_ERROR; + return -EIO; curr_addr += ((dr_xaddr_t) @@ -18973,7 +18973,7 @@ ctrl_u_code_upload(struct drx_demod_instance *demod, /*===================================================================*/ default: - return DRX_STS_INVALID_ARG; + return -EINVAL; break; } /* switch ( action ) */ @@ -18987,7 +18987,7 @@ ctrl_u_code_upload(struct drx_demod_instance *demod, if (!upload_audio_mc) ext_attr->flag_aud_mc_uploaded = false; - return DRX_STS_OK; + return 0; } #endif /* DRXJ_SPLIT_UCODE_UPLOAD */ @@ -19002,9 +19002,9 @@ ctrl_u_code_upload(struct drx_demod_instance *demod, * \param devmod Pointer to demodulator instance. * \param sig_quality Pointer to signal strength data; range 0, .. , 100. * \return int. -* \retval DRX_STS_OK sig_strength contains valid data. -* \retval DRX_STS_INVALID_ARG sig_strength is NULL. -* \retval DRX_STS_ERROR Erroneous data, sig_strength contains invalid data. +* \retval 0 sig_strength contains valid data. +* \retval -EINVAL sig_strength is NULL. +* \retval -EIO Erroneous data, sig_strength contains invalid data. */ static int @@ -19016,7 +19016,7 @@ ctrl_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength) /* Check arguments */ if ((sig_strength == NULL) || (demod == NULL)) - return DRX_STS_INVALID_ARG; + return -EINVAL; ext_attr = (struct drxj_data *) demod->my_ext_attr; standard = ext_attr->standard; @@ -19031,7 +19031,7 @@ ctrl_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength) case DRX_STANDARD_ITU_C: #endif rc = get_sig_strength(demod, sig_strength); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -19045,7 +19045,7 @@ ctrl_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength) case DRX_STANDARD_NTSC: /* fallthrough */ case DRX_STANDARD_FM: rc = get_atv_sig_strength(demod, sig_strength); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -19053,14 +19053,14 @@ ctrl_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength) #endif case DRX_STANDARD_UNKNOWN: /* fallthrough */ default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } /* TODO */ /* find out if signal strength is calculated in the same way for all standards */ - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -19085,24 +19085,24 @@ ctrl_get_cfg_oob_misc(struct drx_demod_instance *demod, struct drxj_cfg_oob_misc /* check arguments */ if (misc == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; dev_addr = demod->my_i2c_dev_addr; /* TODO */ /* check if the same registers are used for all standards (QAM/VSB/ATV) */ rc = DRXJ_DAP.read_reg16func(dev_addr, ORX_NSU_TUN_IFGAIN_W__A, &misc->agc.IFAGC, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.read_reg16func(dev_addr, ORX_NSU_TUN_RFGAIN_W__A, &misc->agc.RFAGC, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.read_reg16func(dev_addr, ORX_FWP_SRC_DGN_W__A, &data, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -19113,7 +19113,7 @@ ctrl_get_cfg_oob_misc(struct drx_demod_instance *demod, struct drxj_cfg_oob_misc misc->agc.digital_agc = digital_agc_mant << digital_agc_exp; rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_ORX_SCU_LOCK__A, &lock, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -19126,15 +19126,15 @@ ctrl_get_cfg_oob_misc(struct drx_demod_instance *demod, struct drxj_cfg_oob_misc misc->eq_lock = ((lock & 0x0020) ? true : false); rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_ORX_SCU_STATE__A, &state, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } misc->state = (state >> 8) & 0xff; - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } #endif @@ -19153,19 +19153,19 @@ ctrl_get_cfg_vsb_misc(struct drx_demod_instance *demod, struct drxj_cfg_vsb_misc /* check arguments */ if (misc == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; dev_addr = demod->my_i2c_dev_addr; rc = get_vsb_symb_err(dev_addr, &misc->symb_error); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -19186,7 +19186,7 @@ ctrl_set_cfg_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_s { /* check arguments */ if (agc_settings == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; switch (agc_settings->ctrl_mode) { case DRX_AGC_CTRL_AUTO: /* fallthrough */ @@ -19194,7 +19194,7 @@ ctrl_set_cfg_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_s case DRX_AGC_CTRL_OFF: /* fallthrough */ break; default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } /* Distpatch */ @@ -19217,10 +19217,10 @@ ctrl_set_cfg_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_s return set_agc_if(demod, agc_settings, true); case DRX_STANDARD_UNKNOWN: default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } - return DRX_STS_OK; + return 0; } /*============================================================================*/ @@ -19241,7 +19241,7 @@ ctrl_get_cfg_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_s { /* check arguments */ if (agc_settings == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; /* Distpatch */ switch (agc_settings->standard) { @@ -19263,10 +19263,10 @@ ctrl_get_cfg_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_s return get_agc_if(demod, agc_settings); case DRX_STANDARD_UNKNOWN: default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } - return DRX_STS_OK; + return 0; } /*============================================================================*/ @@ -19287,7 +19287,7 @@ ctrl_set_cfg_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_s { /* check arguments */ if (agc_settings == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; switch (agc_settings->ctrl_mode) { case DRX_AGC_CTRL_AUTO: /* fallthrough */ @@ -19295,7 +19295,7 @@ ctrl_set_cfg_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_s case DRX_AGC_CTRL_OFF: break; default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } /* Distpatch */ @@ -19318,10 +19318,10 @@ ctrl_set_cfg_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_s return set_agc_rf(demod, agc_settings, true); case DRX_STANDARD_UNKNOWN: default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } - return DRX_STS_OK; + return 0; } /*============================================================================*/ @@ -19342,7 +19342,7 @@ ctrl_get_cfg_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_s { /* check arguments */ if (agc_settings == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; /* Distpatch */ switch (agc_settings->standard) { @@ -19364,10 +19364,10 @@ ctrl_get_cfg_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_s return get_agc_rf(demod, agc_settings); case DRX_STANDARD_UNKNOWN: default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } - return DRX_STS_OK; + return 0; } /*============================================================================*/ @@ -19397,18 +19397,18 @@ ctrl_get_cfg_agc_internal(struct drx_demod_instance *demod, u16 *agc_internal) /* check arguments */ if (agc_internal == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; rc = ctrl_lock_status(demod, &lock_status); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } if (lock_status != DRXJ_DEMOD_LOCK && lock_status != DRX_LOCKED) { *agc_internal = 0; - return DRX_STS_OK; + return 0; } /* Distpatch */ @@ -19431,26 +19431,26 @@ ctrl_get_cfg_agc_internal(struct drx_demod_instance *demod, u16 *agc_internal) iqm_cf_gain = 56; break; default: - return DRX_STS_ERROR; + return -EIO; } break; #endif default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_CF_POW__A, &iqm_cf_power, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_CF_SCALE_SH__A, &iqm_cf_scale_sh, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_CF_AMP__A, &iqm_cf_amp, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -19464,9 +19464,9 @@ ctrl_get_cfg_agc_internal(struct drx_demod_instance *demod, u16 *agc_internal) - 2 * log1_times100(iqm_cf_amp) - iqm_cf_gain - 120 * iqm_cf_scale_sh + 781); - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -19495,7 +19495,7 @@ ctrl_set_cfg_pre_saw(struct drx_demod_instance *demod, struct drxj_cfg_pre_saw * /* check arguments */ if ((pre_saw == NULL) || (pre_saw->reference > IQM_AF_PDREF__M) ) { - return DRX_STS_INVALID_ARG; + return -EINVAL; } /* Only if standard is currently active */ @@ -19505,7 +19505,7 @@ ctrl_set_cfg_pre_saw(struct drx_demod_instance *demod, struct drxj_cfg_pre_saw * (DRXJ_ISATVSTD(ext_attr->standard) && DRXJ_ISATVSTD(pre_saw->standard))) { rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_PDREF__A, pre_saw->reference, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -19535,12 +19535,12 @@ ctrl_set_cfg_pre_saw(struct drx_demod_instance *demod, struct drxj_cfg_pre_saw * break; #endif default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -19566,7 +19566,7 @@ ctrl_set_cfg_afe_gain(struct drx_demod_instance *demod, struct drxj_cfg_afe_gain /* check arguments */ if (afe_gain == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -19581,7 +19581,7 @@ ctrl_set_cfg_afe_gain(struct drx_demod_instance *demod, struct drxj_cfg_afe_gain /* Do nothing */ break; default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } /* TODO PGA gain is also written by microcode (at least by QAM and VSB) @@ -19597,7 +19597,7 @@ ctrl_set_cfg_afe_gain(struct drx_demod_instance *demod, struct drxj_cfg_afe_gain /* Only if standard is currently active */ if (ext_attr->standard == afe_gain->standard) { rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_PGA_GAIN__A, gain, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -19616,12 +19616,12 @@ ctrl_set_cfg_afe_gain(struct drx_demod_instance *demod, struct drxj_cfg_afe_gain break; #endif default: - return DRX_STS_ERROR; + return -EIO; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -19644,7 +19644,7 @@ ctrl_get_cfg_pre_saw(struct drx_demod_instance *demod, struct drxj_cfg_pre_saw * /* check arguments */ if (pre_saw == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; ext_attr = (struct drxj_data *) demod->my_ext_attr; @@ -19675,10 +19675,10 @@ ctrl_get_cfg_pre_saw(struct drx_demod_instance *demod, struct drxj_cfg_pre_saw * break; #endif default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } - return DRX_STS_OK; + return 0; } /*============================================================================*/ @@ -19701,7 +19701,7 @@ ctrl_get_cfg_afe_gain(struct drx_demod_instance *demod, struct drxj_cfg_afe_gain /* check arguments */ if (afe_gain == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; ext_attr = demod->my_ext_attr; @@ -19717,10 +19717,10 @@ ctrl_get_cfg_afe_gain(struct drx_demod_instance *demod, struct drxj_cfg_afe_gain break; #endif default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } - return DRX_STS_OK; + return 0; } /*============================================================================*/ @@ -19742,17 +19742,17 @@ ctrl_get_fec_meas_seq_count(struct drx_demod_instance *demod, u16 *fec_meas_seq_ int rc; /* check arguments */ if (fec_meas_seq_count == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, fec_meas_seq_count, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -19773,17 +19773,17 @@ ctrl_get_accum_cr_rs_cw_err(struct drx_demod_instance *demod, u32 *accum_cr_rs_c { int rc; if (accum_cr_rs_cw_err == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; rc = DRXJ_DAP.read_reg32func(demod->my_i2c_dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, accum_cr_rs_cw_err, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /** @@ -19799,12 +19799,12 @@ static int ctrl_set_cfg(struct drx_demod_instance *demod, struct drx_cfg *config int rc; if (config == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; do { u16 dummy; rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SCU_RAM_VERSION_HI__A, &dummy, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -19892,12 +19892,12 @@ static int ctrl_set_cfg(struct drx_demod_instance *demod, struct drx_cfg *config #endif default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -19915,12 +19915,12 @@ static int ctrl_get_cfg(struct drx_demod_instance *demod, struct drx_cfg *config int rc; if (config == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; do { u16 dummy; rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SCU_RAM_VERSION_HI__A, &dummy, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -20031,12 +20031,12 @@ static int ctrl_get_cfg(struct drx_demod_instance *demod, struct drx_cfg *config #endif default: - return DRX_STS_INVALID_ARG; + return -EINVAL; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================= @@ -20063,14 +20063,14 @@ int drxj_open(struct drx_demod_instance *demod) /* Check arguments */ if (demod->my_ext_attr == NULL) - return DRX_STS_INVALID_ARG; + return -EINVAL; dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; common_attr = (struct drx_common_attr *) demod->my_common_attr; rc = power_up_device(demod); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -20078,24 +20078,24 @@ int drxj_open(struct drx_demod_instance *demod) /* has to be in front of setIqmAf and setOrxNsuAox */ rc = get_device_capabilities(demod); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Soft reset of sys- and osc-clockdomain */ rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_CC_SOFT_RST__A, (SIO_CC_SOFT_RST_SYS__M | SIO_CC_SOFT_RST_OSC__M), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = drxbsp_hst_sleep(1); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -20103,24 +20103,24 @@ int drxj_open(struct drx_demod_instance *demod) /* TODO first make sure that everything keeps working before enabling this */ /* PowerDownAnalogBlocks() */ rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_STDBY__A, (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE) | ATV_TOP_STDBY_SIF_STDBY_STANDBY, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = set_iqm_af(demod, false); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = set_orx_nsu_aox(demod, false); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = init_hi(demod); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -20128,19 +20128,19 @@ int drxj_open(struct drx_demod_instance *demod) /* disable mpegoutput pins */ cfg_mpeg_output.enable_mpeg_output = false; rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Stop AUD Inform SetAudio it will need to do all setting */ rc = power_down_aud(demod); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Stop SCU */ rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -20156,13 +20156,13 @@ int drxj_open(struct drx_demod_instance *demod) #ifdef DRXJ_SPLIT_UCODE_UPLOAD /* Upload microcode without audio part */ rc = ctrl_u_code_upload(demod, &ucode_info, UCODE_UPLOAD, false); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } #else rc = drx_ctrl(demod, DRX_CTRL_LOAD_UCODE, &ucode_info); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -20170,13 +20170,13 @@ int drxj_open(struct drx_demod_instance *demod) if (common_attr->verify_microcode == true) { #ifdef DRXJ_SPLIT_UCODE_UPLOAD rc = ctrl_u_code_upload(demod, &ucode_info, UCODE_VERIFY, false); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } #else rc = drx_ctrl(demod, DRX_CTRL_VERIFY_UCODE, &ucode_info); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -20187,7 +20187,7 @@ int drxj_open(struct drx_demod_instance *demod) /* Run SCU for a little while to initialize microcode version numbers */ rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -20199,14 +20199,14 @@ int drxj_open(struct drx_demod_instance *demod) if (common_attr->tuner_port_nr == 1) { bool bridge_closed = true; rc = ctrl_i2c_bridge(demod, &bridge_closed); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } rc = drxbsp_tuner_open(demod->my_tuner); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -20214,7 +20214,7 @@ int drxj_open(struct drx_demod_instance *demod) if (common_attr->tuner_port_nr == 1) { bool bridge_closed = false; rc = ctrl_i2c_bridge(demod, &bridge_closed); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -20303,7 +20303,7 @@ int drxj_open(struct drx_demod_instance *demod) ext_attr->standard = DRX_STANDARD_UNKNOWN; rc = smart_ant_init(demod); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -20328,12 +20328,12 @@ int drxj_open(struct drx_demod_instance *demod) driver_version <<= 4; driver_version += (VERSION_PATCH % 10); rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_DRIVER_VER_HI__A, (u16)(driver_version >> 16), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_DRIVER_VER_LO__A, (u16)(driver_version & 0xFFFF), 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -20341,10 +20341,10 @@ int drxj_open(struct drx_demod_instance *demod) /* refresh the audio data structure with default */ ext_attr->aud_data = drxj_default_aud_data_g; - return DRX_STS_OK; + return 0; rw_error: common_attr->is_opened = false; - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -20363,7 +20363,7 @@ int drxj_close(struct drx_demod_instance *demod) /* power up */ rc = ctrl_power_mode(demod, &power_mode); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -20373,20 +20373,20 @@ int drxj_close(struct drx_demod_instance *demod) if (common_attr->tuner_port_nr == 1) { bool bridge_closed = true; rc = ctrl_i2c_bridge(demod, &bridge_closed); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } rc = drxbsp_tuner_close(demod->my_tuner); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } if (common_attr->tuner_port_nr == 1) { bool bridge_closed = false; rc = ctrl_i2c_bridge(demod, &bridge_closed); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } @@ -20394,20 +20394,20 @@ int drxj_close(struct drx_demod_instance *demod) } rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } power_mode = DRX_POWER_DOWN; rc = ctrl_power_mode(demod, &power_mode); - if (rc != DRX_STS_OK) { + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - return DRX_STS_OK; + return 0; rw_error: - return DRX_STS_ERROR; + return -EIO; } /*============================================================================*/ @@ -20602,7 +20602,7 @@ drxj_ctrl(struct drx_demod_instance *demod, u32 ctrl, void *ctrl_data) } break; default: - return DRX_STS_FUNC_NOT_AVAILABLE; + return -ENOTSUPP; } - return DRX_STS_OK; + return 0; } -- cgit v1.1 From 935c6654044b2c7e1176464daf9957c805f6b8a3 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Fri, 17 Jan 2014 11:36:17 -0300 Subject: [media] drx-j: Replace printk's by pr_foo() Instead of using printk's, use the pr_foo() macros. That fixes some checkpatch warnings and provide a better error, warning and debug support. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drx39xxj.c | 36 ++++++++++++---------- .../media/dvb-frontends/drx39xyj/drx39xxj_dummy.c | 10 +++--- drivers/media/dvb-frontends/drx39xyj/drxj.c | 2 +- 3 files changed, 26 insertions(+), 22 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c index 6db009e..e5f276f 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c @@ -19,6 +19,8 @@ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.= */ +#define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__ + #include #include #include @@ -44,7 +46,7 @@ static int drx39xxj_set_powerstate(struct dvb_frontend *fe, int enable) result = drx_ctrl(demod, DRX_CTRL_POWER_MODE, &power_mode); if (result != 0) { - printk(KERN_ERR "Power state change failed\n"); + pr_err("Power state change failed\n"); return 0; } @@ -63,14 +65,14 @@ static int drx39xxj_read_status(struct dvb_frontend *fe, fe_status_t *status) result = drx_ctrl(demod, DRX_CTRL_LOCK_STATUS, &lock_status); if (result != 0) { - printk(KERN_ERR "drx39xxj: could not get lock status!\n"); + pr_err("drx39xxj: could not get lock status!\n"); *status = 0; } switch (lock_status) { case DRX_NEVER_LOCK: *status = 0; - printk(KERN_ERR "drx says NEVER_LOCK\n"); + pr_err("drx says NEVER_LOCK\n"); break; case DRX_NOT_LOCKED: *status = 0; @@ -93,7 +95,7 @@ static int drx39xxj_read_status(struct dvb_frontend *fe, fe_status_t *status) | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK; break; default: - printk(KERN_ERR "Lock state unknown %d\n", lock_status); + pr_err("Lock state unknown %d\n", lock_status); } return 0; @@ -108,7 +110,7 @@ static int drx39xxj_read_ber(struct dvb_frontend *fe, u32 *ber) result = drx_ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); if (result != 0) { - printk(KERN_ERR "drx39xxj: could not get ber!\n"); + pr_err("drx39xxj: could not get ber!\n"); *ber = 0; return 0; } @@ -127,7 +129,7 @@ static int drx39xxj_read_signal_strength(struct dvb_frontend *fe, result = drx_ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); if (result != 0) { - printk(KERN_ERR "drx39xxj: could not get signal strength!\n"); + pr_err("drx39xxj: could not get signal strength!\n"); *strength = 0; return 0; } @@ -146,7 +148,7 @@ static int drx39xxj_read_snr(struct dvb_frontend *fe, u16 *snr) result = drx_ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); if (result != 0) { - printk(KERN_ERR "drx39xxj: could not read snr!\n"); + pr_err("drx39xxj: could not read snr!\n"); *snr = 0; return 0; } @@ -164,7 +166,7 @@ static int drx39xxj_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) result = drx_ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); if (result != 0) { - printk(KERN_ERR "drx39xxj: could not get uc blocks!\n"); + pr_err("drx39xxj: could not get uc blocks!\n"); *ucblocks = 0; return 0; } @@ -218,7 +220,7 @@ static int drx39xxj_set_frontend(struct dvb_frontend *fe) /* Set the standard (will be powered up if necessary */ result = drx_ctrl(demod, DRX_CTRL_SET_STANDARD, &standard); if (result != 0) { - printk(KERN_ERR "Failed to set standard! result=%02x\n", + pr_err("Failed to set standard! result=%02x\n", result); return -EINVAL; } @@ -235,7 +237,7 @@ static int drx39xxj_set_frontend(struct dvb_frontend *fe) /* program channel */ result = drx_ctrl(demod, DRX_CTRL_SET_CHANNEL, &channel); if (result != 0) { - printk(KERN_ERR "Failed to set channel!\n"); + pr_err("Failed to set channel!\n"); return -EINVAL; } /* Just for giggles, let's shut off the LNA again.... */ @@ -243,14 +245,14 @@ static int drx39xxj_set_frontend(struct dvb_frontend *fe) uio_data.value = false; result = drx_ctrl(demod, DRX_CTRL_UIO_WRITE, &uio_data); if (result != 0) { - printk(KERN_ERR "Failed to disable LNA!\n"); + pr_err("Failed to disable LNA!\n"); return 0; } #ifdef DJH_DEBUG for (i = 0; i < 2000; i++) { fe_status_t status; drx39xxj_read_status(fe, &status); - printk(KERN_DBG "i=%d status=%d\n", i, status); + pr_dbg("i=%d status=%d\n", i, status); msleep(100); i += 100; } @@ -273,7 +275,7 @@ static int drx39xxj_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) int result; #ifdef DJH_DEBUG - printk(KERN_DBG "i2c gate call: enable=%d state=%d\n", enable, + pr_dbg("i2c gate call: enable=%d state=%d\n", enable, state->i2c_gate_open); #endif @@ -289,7 +291,7 @@ static int drx39xxj_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) result = drx_ctrl(demod, DRX_CTRL_I2C_BRIDGE, &i2c_gate_state); if (result != 0) { - printk(KERN_ERR "drx39xxj: could not open i2c gate [%d]\n", + pr_err("drx39xxj: could not open i2c gate [%d]\n", result); dump_stack(); } else { @@ -383,7 +385,7 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) result = drx_open(demod); if (result != 0) { - printk(KERN_ERR "DRX open failed! Aborting\n"); + pr_err("DRX open failed! Aborting\n"); kfree(state); return NULL; } @@ -394,7 +396,7 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) /* Configure user-I/O #3: enable read/write */ result = drx_ctrl(demod, DRX_CTRL_UIO_CFG, &uio_cfg); if (result != 0) { - printk(KERN_ERR "Failed to setup LNA GPIO!\n"); + pr_err("Failed to setup LNA GPIO!\n"); return NULL; } @@ -402,7 +404,7 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) uio_data.value = false; result = drx_ctrl(demod, DRX_CTRL_UIO_WRITE, &uio_data); if (result != 0) { - printk(KERN_ERR "Failed to disable LNA!\n"); + pr_err("Failed to disable LNA!\n"); return NULL; } diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c b/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c index 8540774..c5187a1 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c @@ -1,3 +1,5 @@ +#define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__ + #include #include #include @@ -99,11 +101,11 @@ int drxbsp_i2c_write_read(struct i2c_device_addr *w_dev_addr, } if (state->i2c == NULL) { - printk("i2c was zero, aborting\n"); + pr_err("i2c was zero, aborting\n"); return 0; } if (i2c_transfer(state->i2c, msg, num_msgs) != num_msgs) { - printk(KERN_WARNING "drx3933: I2C write/read failed\n"); + pr_warn("drx3933: I2C write/read failed\n"); return -EREMOTEIO; } @@ -119,11 +121,11 @@ int drxbsp_i2c_write_read(struct i2c_device_addr *w_dev_addr, .flags = I2C_M_RD, .buf = r_data, .len = r_count}, }; - printk("drx3933 i2c operation addr=%x i2c=%p, wc=%x rc=%x\n", + pr_dbg("drx3933 i2c operation addr=%x i2c=%p, wc=%x rc=%x\n", w_dev_addr->i2c_addr, state->i2c, w_count, r_count); if (i2c_transfer(state->i2c, msg, 2) != 2) { - printk(KERN_WARNING "drx3933: I2C write/read failed\n"); + pr_warn("drx3933: I2C write/read failed\n"); return -EREMOTEIO; } #endif diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index 811e09c..aafe6df 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -35,7 +35,7 @@ INCLUDE FILES ----------------------------------------------------------------------------*/ -#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt +#define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__ #include "drxj.h" #include "drxj_map.h" -- cgit v1.1 From b8cbcd354feddba18f42d8d056762c7151605013 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Fri, 17 Jan 2014 12:20:41 -0300 Subject: [media] drx-j: get rid of some ugly macros There are several get/set macros that are bogus: they just call another macro and do either: x = FOO(d) or FOO(d) = x As checkpatch complains about that, and replacing all of them are as easy as running a small coccinelle script, get rid of all of them. Script used: @@ expression d, x; @@ -DRX_SET_MIRRORFREQSPECT(d, x); +DRX_ATTR_MIRRORFREQSPECT(d) = x; @@ expression d, x; @@ -DRX_GET_MIRRORFREQSPECT(d, x); +x = DRX_ATTR_MIRRORFREQSPECT(d); @@ expression d, x; @@ -DRX_SET_CURRENTPOWERMODE(d, x); +DRX_ATTR_CURRENTPOWERMODE(d) = x; @@ expression d, x; @@ -DRX_GET_CURRENTPOWERMODE(d, x); +x = DRX_ATTR_CURRENTPOWERMODE(d); @@ expression d, x; @@ -DRX_SET_MICROCODE(d, x); +DRX_ATTR_MICROCODE(d) = x; @@ expression d, x; @@ -DRX_GET_MICROCODE(d, x); +x = DRX_ATTR_MICROCODE(d); @@ expression d, x; @@ -DRX_SET_MICROCODESIZE(d, x); +DRX_ATTR_MICROCODESIZE(d) = x; @@ expression d, x; @@ -DRX_GET_MICROCODESIZE(d, x); +x = DRX_ATTR_MICROCODESIZE(d); @@ expression d, x; @@ -DRX_SET_VERIFYMICROCODE(d, x); +DRX_ATTR_VERIFYMICROCODE(d) = x; @@ expression d, x; @@ -DRX_GET_VERIFYMICROCODE(d, x); +x = DRX_ATTR_VERIFYMICROCODE(d); @@ expression d, x; @@ -DRX_SET_MCVERTYPE(d, x); +DRX_ATTR_MCRECORD(d).aux_type = x; @@ expression d, x; @@ -DRX_GET_MCVERTYPE(d, x); +x = DRX_ATTR_MCRECORD(d).aux_type; @@ expression d, x; @@ -DRX_SET_MCDEV(d, x); +DRX_ATTR_MCRECORD(d).mc_dev_type = x; @@ expression d, x; @@ -DRX_GET_MCDEV(d, x); +x = DRX_ATTR_MCRECORD(d).mc_dev_type; @@ expression d, x; @@ -DRX_SET_MCVERSION(d, x); +DRX_ATTR_MCRECORD(d).mc_version = x; @@ expression d, x; @@ -DRX_GET_MCVERSION(d, x); +x = DRX_ATTR_MCRECORD(d).mc_version; @@ expression d, x; @@ -DRX_SET_MCPATCH(d, x); +DRX_ATTR_MCRECORD(d).mc_base_version = x; @@ expression d, x; @@ -DRX_GET_MCPATCH(d, x); +x = DRX_ATTR_MCRECORD(d).mc_base_version; @@ expression d, x; @@ -DRX_SET_I2CADDR(d, x); +DRX_ATTR_I2CADDR(d) = x; @@ expression d, x; @@ -DRX_GET_I2CADDR(d, x); +x = DRX_ATTR_I2CADDR(d); @@ expression d, x; @@ -DRX_SET_I2CDEVID(d, x); +DRX_ATTR_I2CDEVID(d) = x; @@ expression d, x; @@ -DRX_GET_I2CDEVID(d, x); +x = DRX_ATTR_I2CDEVID(d); @@ expression d, x; @@ -DRX_SET_USEBOOTLOADER(d, x); +DRX_ATTR_USEBOOTLOADER(d) = x; @@ expression d, x; @@ -DRX_GET_USEBOOTLOADER(d, x); +x = DRX_ATTR_USEBOOTLOADER(d); @@ expression d, x; @@ -DRX_SET_CURRENTSTANDARD(d, x); +DRX_ATTR_CURRENTSTANDARD(d) = x; @@ expression d, x; @@ -DRX_GET_CURRENTSTANDARD(d, x); +x = DRX_ATTR_CURRENTSTANDARD(d); @@ expression d, x; @@ -DRX_SET_PREVSTANDARD(d, x); +DRX_ATTR_PREVSTANDARD(d) = x; @@ expression d, x; @@ -DRX_GET_PREVSTANDARD(d, x); +x = DRX_ATTR_PREVSTANDARD(d); @@ expression d, x; @@ -DRX_SET_CACHESTANDARD(d, x); +DRX_ATTR_CACHESTANDARD(d) = x; @@ expression d, x; @@ -DRX_GET_CACHESTANDARD(d, x); +x = DRX_ATTR_CACHESTANDARD(d); @@ expression d, x; @@ -DRX_SET_CURRENTCHANNEL(d, x); +DRX_ATTR_CURRENTCHANNEL(d) = x; @@ expression d, x; @@ -DRX_GET_CURRENTCHANNEL(d, x); +x = DRX_ATTR_CURRENTCHANNEL(d); @@ expression d, x; @@ -DRX_SET_ISOPENED(d, x); +DRX_ATTR_ISOPENED(d) = x; @@ expression d, x; @@ -DRX_GET_ISOPENED(d, x); +x = DRX_ATTR_ISOPENED(d); @@ expression d, x; @@ -DRX_SET_TUNER(d, x); +DRX_ATTR_TUNER(d) = x; @@ expression d, x; @@ -DRX_GET_TUNER(d, x); +x = DRX_ATTR_TUNER(d); @@ expression d, x; @@ -DRX_SET_CAPABILITIES(d, x); +DRX_ATTR_CAPABILITIES(d) = x; @@ expression d, x; @@ -DRX_GET_CAPABILITIES(d, x); +x = DRX_ATTR_CAPABILITIES(d); @@ expression d, x; @@ -DRX_SET_PRODUCTID(d, x); +DRX_ATTR_PRODUCTID(d) = x; @@ expression d, x; @@ -DRX_GET_PRODUCTID(d, x); +x = DRX_ATTR_PRODUCTID(d); @@ expression d, x; @@ -DRX_SET_MFX(d, x); +DRX_ATTR_PRODUCTID(d) = x; @@ expression d, x; @@ -DRX_GET_MFX(d, x); +x = DRX_ATTR_PRODUCTID(d); @@ expression d, x; @@ -DRX_SET_INTERMEDIATEFREQ(d, x); +DRX_ATTR_INTERMEDIATEFREQ(d) = x; @@ expression d, x; @@ -DRX_GET_INTERMEDIATEFREQ(d, x); +x = DRX_ATTR_INTERMEDIATEFREQ(d); @@ expression d, x; @@ -DRX_SET_SYSCLOCKFREQ(d, x); +DRX_ATTR_SYSCLOCKFREQ(d) = x; @@ expression d, x; @@ -DRX_GET_SYSCLOCKFREQ(d, x); +x = DRX_ATTR_SYSCLOCKFREQ(d); @@ expression d, x; @@ -DRX_SET_TUNERRFAGCPOL(d, x); +DRX_ATTR_TUNERRFAGCPOL(d) = x; @@ expression d, x; @@ -DRX_GET_TUNERRFAGCPOL(d, x); +x = DRX_ATTR_TUNERRFAGCPOL(d); @@ expression d, x; @@ -DRX_SET_TUNERIFAGCPOL(d, x); +DRX_ATTR_TUNERIFAGCPOL(d) = x; @@ expression d, x; @@ -DRX_GET_TUNERIFAGCPOL(d, x); +x = DRX_ATTR_TUNERIFAGCPOL(d); @@ expression d, x; @@ -DRX_SET_TUNERSLOWMODE(d, x); +DRX_ATTR_TUNERSLOWMODE(d) = x; @@ expression d, x; @@ -DRX_GET_TUNERSLOWMODE(d, x); +x = DRX_ATTR_TUNERSLOWMODE(d); @@ expression d, x; @@ -DRX_SET_TUNERPORTNR(d, x); +DRX_ATTR_TUNERSPORTNR(d) = x; Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drx_driver.c | 26 +- drivers/media/dvb-frontends/drx39xyj/drx_driver.h | 331 ---------------------- drivers/media/dvb-frontends/drx39xyj/drxj.c | 6 +- 3 files changed, 14 insertions(+), 349 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c index 1737a8c..34bc76c 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c @@ -767,7 +767,7 @@ ctrl_program_tuner(struct drx_demod_instance *demod, struct drx_channel *channel return -EINVAL; } - DRX_GET_TUNERSLOWMODE(demod, tuner_slow_mode); + tuner_slow_mode = DRX_ATTR_TUNERSLOWMODE(demod); /* select fast (switch) or slow (lock) tuner mode */ if (tuner_slow_mode) { @@ -818,7 +818,7 @@ ctrl_program_tuner(struct drx_demod_instance *demod, struct drx_channel *channel /* update common attributes with information available from this function; TODO: check if this is required and safe */ - DRX_SET_INTERMEDIATEFREQ(demod, if_frequency); + DRX_ATTR_INTERMEDIATEFREQ(demod) = if_frequency; return 0; } @@ -1010,10 +1010,10 @@ ctrl_u_code(struct drx_demod_instance *demod, /* Scan microcode blocks first for version info if uploading */ if (action == UCODE_UPLOAD) { /* Clear version block */ - DRX_SET_MCVERTYPE(demod, 0); - DRX_SET_MCDEV(demod, 0); - DRX_SET_MCVERSION(demod, 0); - DRX_SET_MCPATCH(demod, 0); + DRX_ATTR_MCRECORD(demod).aux_type = 0; + DRX_ATTR_MCRECORD(demod).mc_dev_type = 0; + DRX_ATTR_MCRECORD(demod).mc_version = 0; + DRX_ATTR_MCRECORD(demod).mc_base_version = 0; for (i = 0; i < mc_nr_of_blks; i++) { drxu_code_block_hdr_t block_hdr; @@ -1032,17 +1032,13 @@ ctrl_u_code(struct drx_demod_instance *demod, u8 *auxblk = mc_info->mc_data + block_hdr.addr; u16 auxtype = u_code_read16(auxblk); if (DRX_ISMCVERTYPE(auxtype)) { - DRX_SET_MCVERTYPE(demod, - u_code_read16(auxblk)); + DRX_ATTR_MCRECORD(demod).aux_type = u_code_read16(auxblk); auxblk += sizeof(u16); - DRX_SET_MCDEV(demod, - u_code_read32(auxblk)); + DRX_ATTR_MCRECORD(demod).mc_dev_type = u_code_read32(auxblk); auxblk += sizeof(u32); - DRX_SET_MCVERSION(demod, - u_code_read32(auxblk)); + DRX_ATTR_MCRECORD(demod).mc_version = u_code_read32(auxblk); auxblk += sizeof(u32); - DRX_SET_MCPATCH(demod, - u_code_read32(auxblk)); + DRX_ATTR_MCRECORD(demod).mc_base_version = u_code_read32(auxblk); } } @@ -1351,7 +1347,7 @@ int drx_close(struct drx_demod_instance *demod) status = (*(demod->my_demod_funct->close_func)) (demod); - DRX_SET_ISOPENED(demod, false); + DRX_ATTR_ISOPENED(demod) = false; return status; } diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h index 1b71622..2a78466 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h @@ -2364,341 +2364,10 @@ Access macros #define DRX_ATTR_TUNER(d) ((d)->my_tuner) #define DRX_ATTR_I2CADDR(d) ((d)->my_i2c_dev_addr->i2c_addr) #define DRX_ATTR_I2CDEVID(d) ((d)->my_i2c_dev_addr->i2c_dev_id) - -/** -* \brief Actual access macro's -* \param d pointer to demod instance -* \param x value to set ar to get -* -* SET macro's must be used to set the value of an attribute. -* GET macro's must be used to retrieve the value of an attribute. -* -*/ - -/**************************/ - -#define DRX_SET_MIRRORFREQSPECT(d, x) \ - do { \ - DRX_ATTR_MIRRORFREQSPECT(d) = (x); \ - } while (0) - -#define DRX_GET_MIRRORFREQSPECT(d, x) \ - do { \ - (x) = DRX_ATTR_MIRRORFREQSPECT(d); \ - } while (0) - -/**************************/ - -#define DRX_SET_CURRENTPOWERMODE(d, x) \ - do { \ - DRX_ATTR_CURRENTPOWERMODE(d) = (x); \ - } while (0) - -#define DRX_GET_CURRENTPOWERMODE(d, x) \ - do { \ - (x) = DRX_ATTR_CURRENTPOWERMODE(d); \ - } while (0) - -/**************************/ - -#define DRX_SET_MICROCODE(d, x) \ - do { \ - DRX_ATTR_MICROCODE(d) = (x); \ - } while (0) - -#define DRX_GET_MICROCODE(d, x) \ - do { \ - (x) = DRX_ATTR_MICROCODE(d); \ - } while (0) - -/**************************/ - -#define DRX_SET_MICROCODESIZE(d, x) \ - do { \ - DRX_ATTR_MICROCODESIZE(d) = (x); \ - } while (0) - -#define DRX_GET_MICROCODESIZE(d, x) \ - do { \ - (x) = DRX_ATTR_MICROCODESIZE(d); \ - } while (0) - -/**************************/ - -#define DRX_SET_VERIFYMICROCODE(d, x) \ - do { \ - DRX_ATTR_VERIFYMICROCODE(d) = (x); \ - } while (0) - -#define DRX_GET_VERIFYMICROCODE(d, x) \ - do { \ - (x) = DRX_ATTR_VERIFYMICROCODE(d); \ - } while (0) - -/**************************/ - -#define DRX_SET_MCVERTYPE(d, x) \ - do { \ - DRX_ATTR_MCRECORD(d).aux_type = (x); \ - } while (0) - -#define DRX_GET_MCVERTYPE(d, x) \ - do { \ - (x) = DRX_ATTR_MCRECORD(d).aux_type; \ - } while (0) - -/**************************/ - #define DRX_ISMCVERTYPE(x) ((x) == AUX_VER_RECORD) /**************************/ -#define DRX_SET_MCDEV(d, x) \ - do { \ - DRX_ATTR_MCRECORD(d).mc_dev_type = (x); \ - } while (0) - -#define DRX_GET_MCDEV(d, x) \ - do { \ - (x) = DRX_ATTR_MCRECORD(d).mc_dev_type; \ - } while (0) - -/**************************/ - -#define DRX_SET_MCVERSION(d, x) \ - do { \ - DRX_ATTR_MCRECORD(d).mc_version = (x); \ - } while (0) - -#define DRX_GET_MCVERSION(d, x) \ - do { \ - (x) = DRX_ATTR_MCRECORD(d).mc_version; \ - } while (0) - -/**************************/ -#define DRX_SET_MCPATCH(d, x) \ - do { \ - DRX_ATTR_MCRECORD(d).mc_base_version = (x); \ - } while (0) - -#define DRX_GET_MCPATCH(d, x) \ - do { \ - (x) = DRX_ATTR_MCRECORD(d).mc_base_version; \ - } while (0) - -/**************************/ - -#define DRX_SET_I2CADDR(d, x) \ - do { \ - DRX_ATTR_I2CADDR(d) = (x); \ - } while (0) - -#define DRX_GET_I2CADDR(d, x) \ - do { \ - (x) = DRX_ATTR_I2CADDR(d); \ - } while (0) - -/**************************/ - -#define DRX_SET_I2CDEVID(d, x) \ - do { \ - DRX_ATTR_I2CDEVID(d) = (x); \ - } while (0) - -#define DRX_GET_I2CDEVID(d, x) \ - do { \ - (x) = DRX_ATTR_I2CDEVID(d); \ - } while (0) - -/**************************/ - -#define DRX_SET_USEBOOTLOADER(d, x) \ - do { \ - DRX_ATTR_USEBOOTLOADER(d) = (x); \ - } while (0) - -#define DRX_GET_USEBOOTLOADER(d, x) \ - do { \ - (x) = DRX_ATTR_USEBOOTLOADER(d); \ - } while (0) - -/**************************/ - -#define DRX_SET_CURRENTSTANDARD(d, x) \ - do { \ - DRX_ATTR_CURRENTSTANDARD(d) = (x); \ - } while (0) - -#define DRX_GET_CURRENTSTANDARD(d, x) \ - do { \ - (x) = DRX_ATTR_CURRENTSTANDARD(d); \ - } while (0) - -/**************************/ - -#define DRX_SET_PREVSTANDARD(d, x) \ - do { \ - DRX_ATTR_PREVSTANDARD(d) = (x); \ - } while (0) - -#define DRX_GET_PREVSTANDARD(d, x) \ - do { \ - (x) = DRX_ATTR_PREVSTANDARD(d); \ - } while (0) - -/**************************/ - -#define DRX_SET_CACHESTANDARD(d, x) \ - do { \ - DRX_ATTR_CACHESTANDARD(d) = (x); \ - } while (0) - -#define DRX_GET_CACHESTANDARD(d, x) \ - do { \ - (x) = DRX_ATTR_CACHESTANDARD(d); \ - } while (0) - -/**************************/ - -#define DRX_SET_CURRENTCHANNEL(d, x) \ - do { \ - DRX_ATTR_CURRENTCHANNEL(d) = (x); \ - } while (0) - -#define DRX_GET_CURRENTCHANNEL(d, x) \ - do { \ - (x) = DRX_ATTR_CURRENTCHANNEL(d); \ - } while (0) - -/**************************/ - -#define DRX_SET_ISOPENED(d, x) \ - do { \ - DRX_ATTR_ISOPENED(d) = (x); \ - } while (0) - -#define DRX_GET_ISOPENED(d, x) \ - do { \ - (x) = DRX_ATTR_ISOPENED(d); \ - } while (0) - -/**************************/ - -#define DRX_SET_TUNER(d, x) \ - do { \ - DRX_ATTR_TUNER(d) = (x); \ - } while (0) - -#define DRX_GET_TUNER(d, x) \ - do { \ - (x) = DRX_ATTR_TUNER(d); \ - } while (0) - -/**************************/ - -#define DRX_SET_CAPABILITIES(d, x) \ - do { \ - DRX_ATTR_CAPABILITIES(d) = (x); \ - } while (0) - -#define DRX_GET_CAPABILITIES(d, x) \ - do { \ - (x) = DRX_ATTR_CAPABILITIES(d); \ - } while (0) - -/**************************/ - -#define DRX_SET_PRODUCTID(d, x) \ - do { \ - DRX_ATTR_PRODUCTID(d) |= (x << 4); \ - } while (0) - -#define DRX_GET_PRODUCTID(d, x) \ - do { \ - (x) = (DRX_ATTR_PRODUCTID(d) >> 4); \ - } while (0) - -/**************************/ - -#define DRX_SET_MFX(d, x) \ - do { \ - DRX_ATTR_PRODUCTID(d) |= (x); \ - } while (0) - -#define DRX_GET_MFX(d, x) \ - do { \ - (x) = (DRX_ATTR_PRODUCTID(d) & 0xF); \ - } while (0) - -/**************************/ - -#define DRX_SET_INTERMEDIATEFREQ(d, x) \ - do { \ - DRX_ATTR_INTERMEDIATEFREQ(d) = (x); \ - } while (0) - -#define DRX_GET_INTERMEDIATEFREQ(d, x) \ - do { \ - (x) = DRX_ATTR_INTERMEDIATEFREQ(d); \ - } while (0) - -/**************************/ - -#define DRX_SET_SYSCLOCKFREQ(d, x) \ - do { \ - DRX_ATTR_SYSCLOCKFREQ(d) = (x); \ - } while (0) - -#define DRX_GET_SYSCLOCKFREQ(d, x) \ - do { \ - (x) = DRX_ATTR_SYSCLOCKFREQ(d); \ - } while (0) - -/**************************/ - -#define DRX_SET_TUNERRFAGCPOL(d, x) \ - do { \ - DRX_ATTR_TUNERRFAGCPOL(d) = (x); \ - } while (0) - -#define DRX_GET_TUNERRFAGCPOL(d, x) \ - do { \ - (x) = DRX_ATTR_TUNERRFAGCPOL(d); \ - } while (0) - -/**************************/ - -#define DRX_SET_TUNERIFAGCPOL(d, x) \ - do { \ - DRX_ATTR_TUNERIFAGCPOL(d) = (x); \ - } while (0) - -#define DRX_GET_TUNERIFAGCPOL(d, x) \ - do { \ - (x) = DRX_ATTR_TUNERIFAGCPOL(d); \ - } while (0) - -/**************************/ - -#define DRX_SET_TUNERSLOWMODE(d, x) \ - do { \ - DRX_ATTR_TUNERSLOWMODE(d) = (x); \ - } while (0) - -#define DRX_GET_TUNERSLOWMODE(d, x) \ - do { \ - (x) = DRX_ATTR_TUNERSLOWMODE(d); \ - } while (0) - -/**************************/ - -#define DRX_SET_TUNERPORTNR(d, x) \ - do { \ - DRX_ATTR_TUNERSPORTNR(d) = (x); \ - } while (0) - -/**************************/ - /* Macros with device-specific handling are converted to CFG functions */ #define DRX_ACCESSMACRO_SET(demod, value, cfg_name, data_type) \ diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index aafe6df..668ac1a 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -5205,9 +5205,9 @@ static int ctrl_validate_u_code(struct drx_demod_instance *demod) * - product ID in version record's device ID does not * match DRXJ1 product IDs - 0x393 or 0x394 */ - DRX_GET_MCVERTYPE(demod, ver_type); - DRX_GET_MCDEV(demod, mc_dev); - DRX_GET_MCPATCH(demod, mc_patch); + ver_type = DRX_ATTR_MCRECORD(demod).aux_type; + mc_dev = DRX_ATTR_MCRECORD(demod).mc_dev_type; + mc_patch = DRX_ATTR_MCRECORD(demod).mc_base_version; if (DRX_ISMCVERTYPE(ver_type)) { if ((mc_dev != 0) && -- cgit v1.1 From ab0db7e06988e2ca54934d115cb35ffcb3a79c81 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Fri, 17 Jan 2014 12:51:14 -0300 Subject: [media] drx-j: remove typedefs at drx_driver.c Get rid of another typedef defined on this driver. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drx_driver.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c index 34bc76c..9eb4bbf 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c @@ -117,7 +117,7 @@ GLOBAL VARIABLES STRUCTURES ------------------------------------------------------------------------------*/ /** \brief Structure of the microcode block headers */ -typedef struct { +struct drxu_code_block_hdr { u32 addr; /**< Destination address of the data in this block */ u16 size; @@ -129,8 +129,7 @@ typedef struct { - bit[1]= compression on/off - bit[15..2]=reserved */ u16 CRC;/**< CRC value of the data block, only valid if CRC flag is - set. */ -} drxu_code_block_hdr_t, *pdrxu_code_block_hdr_t; + set. */}; /*------------------------------------------------------------------------------ FUNCTIONS @@ -1015,7 +1014,7 @@ ctrl_u_code(struct drx_demod_instance *demod, DRX_ATTR_MCRECORD(demod).mc_version = 0; DRX_ATTR_MCRECORD(demod).mc_base_version = 0; for (i = 0; i < mc_nr_of_blks; i++) { - drxu_code_block_hdr_t block_hdr; + struct drxu_code_block_hdr block_hdr; /* Process block header */ block_hdr.addr = u_code_read32(mc_data); @@ -1060,7 +1059,7 @@ ctrl_u_code(struct drx_demod_instance *demod, /* Process microcode blocks */ for (i = 0; i < mc_nr_of_blks; i++) { - drxu_code_block_hdr_t block_hdr; + struct drxu_code_block_hdr block_hdr; u16 mc_block_nr_bytes = 0; /* Process block header */ -- cgit v1.1 From c361fda0e5d4d803a0caa3bd2516217a395630f1 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Fri, 17 Jan 2014 13:50:08 -0300 Subject: [media] drx-j: remove drxj_options.h This file is empty (actually, all commented there). So, remove it. We should latter remove those macros too, or convert them into a struct to allow dynamically enable the options during device probing time. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drxj.c | 4 -- .../media/dvb-frontends/drx39xyj/drxj_options.h | 65 ---------------------- 2 files changed, 69 deletions(-) delete mode 100644 drivers/media/dvb-frontends/drx39xyj/drxj_options.h diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index 668ac1a..c047452 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -40,10 +40,6 @@ INCLUDE FILES #include "drxj.h" #include "drxj_map.h" -#ifdef DRXJ_OPTIONS_H -#include "drxj_options.h" -#endif - /*============================================================================*/ /*=== DEFINES ================================================================*/ /*============================================================================*/ diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj_options.h b/drivers/media/dvb-frontends/drx39xyj/drxj_options.h deleted file mode 100644 index f390286..0000000 --- a/drivers/media/dvb-frontends/drx39xyj/drxj_options.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - * Neither the name of Trident Microsystems nor Hauppauge Computer Works - nor the names of its contributors may be used to endorse or promote - products derived from this software without specific prior written - permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. -*/ - -/** -* \file $Id: drxj_options.h,v 1.5 2009/10/05 21:32:49 dingtao Exp $ -* -* \brief DRXJ optional settings -* -* \author Tao Ding -*/ - -/* Note: Please add preprocessor DRXJ_OPTIONS_H for drxj.c to include this file */ -#ifndef __DRXJ_OPTIONS_H__ -#define __DRXJ_OPTIONS_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/* #define DRXJ_DIGITAL_ONLY */ -/* #define DRXJ_VSB_ONLY */ -/* #define DRXJ_SIGNAL_ACCUM_ERR */ -/* #define MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH 0x03 */ -/* #define MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH 0x04 */ -/* #define MPEG_OUTPUT_CLK_DRIVE_STRENGTH 0x05 */ -/* #define OOB_CRX_DRIVE_STRENGTH 0x04 */ -/* #define OOB_DRX_DRIVE_STRENGTH 0x05 */ -/* #define DRXJ_QAM_MAX_WAITTIME 1000 */ -/* #define DRXJ_QAM_FEC_LOCK_WAITTIME 200 */ -/* #define DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME 250 */ - -/*------------------------------------------------------------------------- -THE END --------------------------------------------------------------------------*/ -#ifdef __cplusplus -} -#endif -#endif /* __DRXJ_OPTIONS_H__ */ -- cgit v1.1 From 2f1f733386ce6dac70c0936b81b9f630ddfb1837 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Fri, 17 Jan 2014 11:51:52 -0300 Subject: [media] drx-j: make checkpatch.pl happy Fix the remaining checkpatch.pl compliants at drxj. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- .../media/dvb-frontends/drx39xyj/drx_dap_fasi.c | 69 +-- .../media/dvb-frontends/drx39xyj/drx_dap_fasi.h | 9 +- drivers/media/dvb-frontends/drx39xyj/drx_driver.c | 123 ++---- drivers/media/dvb-frontends/drx39xyj/drx_driver.h | 486 ++++++++++----------- .../dvb-frontends/drx39xyj/drx_driver_version.h | 7 - drivers/media/dvb-frontends/drx39xyj/drxj.h | 52 +-- drivers/media/dvb-frontends/drx39xyj/drxj_map.h | 7 - 7 files changed, 325 insertions(+), 428 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c index e0fc219..2a37098 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c @@ -26,28 +26,17 @@ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ -/******************************************************************************* -* FILENAME: $Id: drx_dap_fasi.c,v 1.7 2009/12/28 14:36:21 carlo Exp $ -* -* DESCRIPTION: -* Part of DRX driver. -* Data access protocol: Fast Access Sequential Interface (fasi) -* Fast access, because of short addressing format (16 instead of 32 bits addr) -* Sequential, because of I2C. -* These functions know how the chip's memory and registers are to be accessed, -* but nothing more. -* -* These functions should not need adapting to a new platform. -* -* USAGE: -* - -* -* NOTES: -* -* -*******************************************************************************/ + DESCRIPTION: + Part of DRX driver. + Data access protocol: Fast Access Sequential Interface (fasi) + Fast access, because of short addressing format (16 instead of 32 bits addr) + Sequential, because of I2C. + These functions know how the chip's memory and registers are to be accessed, + but nothing more. + + These functions should not need adapting to a new platform. +*/ #include "drx_dap_fasi.h" #include "drx_driver.h" /* for drxbsp_hst_memcpy() */ @@ -221,9 +210,8 @@ static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr, u16 overhead_size = 0; /* Check parameters ******************************************************* */ - if (dev_addr == NULL) { + if (dev_addr == NULL) return -EINVAL; - } overhead_size = (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1) + (DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2); @@ -252,8 +240,7 @@ static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr, addr &= ~DRXDAP_FASI_FLAGS; addr |= flags; -#if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && \ - (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1)) +#if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1)) /* short format address preferred but long format otherwise */ if (DRXDAP_FASI_LONG_FORMAT(addr)) { #endif @@ -263,8 +250,7 @@ static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr, buf[bufx++] = (u8) ((addr >> 24) & 0xFF); buf[bufx++] = (u8) ((addr >> 7) & 0xFF); #endif -#if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && \ - (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1)) +#if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1)) } else { #endif #if (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1) @@ -273,8 +259,7 @@ static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr, (u8) (((addr >> 16) & 0x0F) | ((addr >> 18) & 0xF0)); #endif -#if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && \ - (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1)) +#if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1)) } #endif @@ -332,9 +317,8 @@ static int drxdap_fasi_read_modify_write_reg16(struct i2c_device_addr *dev_addr, int rc = -EIO; #if (DRXDAPFASI_LONG_ADDR_ALLOWED == 1) - if (rdata == NULL) { + if (rdata == NULL) return -EINVAL; - } rc = drxdap_fasi_write_reg16(dev_addr, waddr, wdata, DRXDAP_FASI_RMW); if (rc == 0) @@ -369,9 +353,9 @@ static int drxdap_fasi_read_reg16(struct i2c_device_addr *dev_addr, u8 buf[sizeof(*data)]; int rc; - if (!data) { + if (!data) return -EINVAL; - } + rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags); *data = buf[0] + (((u16) buf[1]) << 8); return rc; @@ -402,9 +386,9 @@ static int drxdap_fasi_read_reg32(struct i2c_device_addr *dev_addr, u8 buf[sizeof(*data)]; int rc; - if (!data) { + if (!data) return -EINVAL; - } + rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags); *data = (((u32) buf[0]) << 0) + (((u32) buf[1]) << 8) + @@ -446,9 +430,8 @@ static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr, u16 block_size = 0; /* Check parameters ******************************************************* */ - if (dev_addr == NULL) { + if (dev_addr == NULL) return -EINVAL; - } overhead_size = (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1) + (DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2); @@ -457,9 +440,8 @@ static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr, ((!(DRXDAPFASI_LONG_ADDR_ALLOWED)) && DRXDAP_FASI_LONG_FORMAT(addr)) || (overhead_size > (DRXDAP_MAX_WCHUNKSIZE)) || - ((datasize != 0) && (data == NULL)) || ((datasize & 1) == 1)) { + ((datasize != 0) && (data == NULL)) || ((datasize & 1) == 1)) return -EINVAL; - } flags &= DRXDAP_FASI_FLAGS; flags &= ~DRXDAP_FASI_MODEFLAGS; @@ -476,8 +458,7 @@ static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr, /* Buffer device address */ addr &= ~DRXDAP_FASI_FLAGS; addr |= flags; -#if (((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && \ - ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1)) +#if (((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1)) /* short format address preferred but long format otherwise */ if (DRXDAP_FASI_LONG_FORMAT(addr)) { #endif @@ -487,8 +468,7 @@ static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr, buf[bufx++] = (u8) ((addr >> 24) & 0xFF); buf[bufx++] = (u8) ((addr >> 7) & 0xFF); #endif -#if (((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && \ - ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1)) +#if (((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1)) } else { #endif #if ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1) @@ -497,8 +477,7 @@ static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr, (u8) (((addr >> 16) & 0x0F) | ((addr >> 18) & 0xF0)); #endif -#if (((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && \ - ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1)) +#if (((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1)) } #endif diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.h b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.h index 4151876..354ec07 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.h @@ -234,11 +234,7 @@ /*-------- Public API functions ----------------------------------------------*/ -#ifdef __cplusplus -extern "C" { -#endif - - extern struct drx_access_func drx_dap_fasi_funct_g; +extern struct drx_access_func drx_dap_fasi_funct_g; #define DRXDAP_FASI_RMW 0x10000000 #define DRXDAP_FASI_BROADCAST 0x20000000 @@ -257,7 +253,4 @@ extern "C" { #define DRXDAP_FASI_LONG_FORMAT(addr) (((addr) & 0xFC30FF80) != 0) #define DRXDAP_FASI_OFFSET_TOO_LARGE(addr) (((addr) & 0x00008000) != 0) -#ifdef __cplusplus -} -#endif #endif /* __DRX_DAP_FASI_H__ */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c index 9eb4bbf..bfd02411 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c @@ -226,31 +226,25 @@ static int scan_wait_for_lock(struct drx_demod_instance *demod, bool *is_locked) /* Start polling loop, checking for lock & timeout */ while (!done_waiting) { - - if (drx_ctrl(demod, DRX_CTRL_LOCK_STATUS, &lock_state) != - 0) { + if (drx_ctrl(demod, DRX_CTRL_LOCK_STATUS, &lock_state)) return -EIO; - } + current_time = drxbsp_hst_clock(); timer_value = current_time - start_time_lock_stage; if (lock_state >= desired_lock_state) { *is_locked = true; done_waiting = true; - } /* if ( lock_state >= desired_lock_state ) .. */ - else if (lock_state == DRX_NEVER_LOCK) { + } else if (lock_state == DRX_NEVER_LOCK) { done_waiting = true; - } /* if ( lock_state == DRX_NEVER_LOCK ) .. */ - else if (timer_value > timeout_value) { + } else if (timer_value > timeout_value) { /* lock_state == DRX_NOT_LOCKED and timeout */ done_waiting = true; } else { - if (drxbsp_hst_sleep(10) != 0) { + if (drxbsp_hst_sleep(10) != 0) return -EIO; - } - } /* if ( timer_value > timeout_value ) .. */ - - } /* while */ + } + } return 0; } @@ -356,36 +350,30 @@ scan_function_default(void *scan_context, enum drx_scan_command scan_command, struct drx_channel *scan_channel, bool *get_next_channel) { - struct drx_demod_instance *demod = NULL; - int status = -EIO; + struct drx_demod_instance *demod = scan_context; + int status; bool is_locked = false; - demod = (struct drx_demod_instance *) scan_context; - - if (scan_command != DRX_SCAN_COMMAND_NEXT) { - /* just return OK if not doing "scan next" */ + /* just return OK if not doing "scan next" */ + if (scan_command != DRX_SCAN_COMMAND_NEXT) return 0; - } *get_next_channel = false; status = drx_ctrl(demod, DRX_CTRL_SET_CHANNEL, scan_channel); - if (status != 0) { + if (status) return status; - } status = scan_wait_for_lock(demod, &is_locked); - if (status != 0) { + if (status) return status; - } /* done with this channel, move to next one */ *get_next_channel = true; - if (!is_locked) { - /* no channel found */ - return -EBUSY; - } + if (!is_locked) + return -EBUSY; /* no channel found */ + /* channel found */ return 0; } @@ -733,23 +721,20 @@ ctrl_program_tuner(struct drx_demod_instance *demod, struct drx_channel *channel bool tuner_slow_mode = false; /* can't tune without a tuner */ - if (demod->my_tuner == NULL) { + if (demod->my_tuner == NULL) return -EINVAL; - } - common_attr = (struct drx_common_attr *) demod->my_common_attr; + common_attr = demod->my_common_attr; /* select analog or digital tuner mode based on current standard */ - if (drx_ctrl(demod, DRX_CTRL_GET_STANDARD, &standard) != 0) { + if (drx_ctrl(demod, DRX_CTRL_GET_STANDARD, &standard)) return -EIO; - } - if (DRX_ISATVSTD(standard)) { + if (DRX_ISATVSTD(standard)) tuner_mode |= TUNER_MODE_ANALOG; - } else { /* note: also for unknown standard */ + else - tuner_mode |= TUNER_MODE_DIGITAL; - } + tuner_mode |= TUNER_MODE_DIGITAL; /* also for unknown standard */ /* select tuner bandwidth */ switch (channel->bandwidth) { @@ -769,25 +754,23 @@ ctrl_program_tuner(struct drx_demod_instance *demod, struct drx_channel *channel tuner_slow_mode = DRX_ATTR_TUNERSLOWMODE(demod); /* select fast (switch) or slow (lock) tuner mode */ - if (tuner_slow_mode) { + if (tuner_slow_mode) tuner_mode |= TUNER_MODE_LOCK; - } else { + else tuner_mode |= TUNER_MODE_SWITCH; - } if (common_attr->tuner_port_nr == 1) { bool bridge_closed = true; int status_bridge = -EIO; - status_bridge = - drx_ctrl(demod, DRX_CTRL_I2C_BRIDGE, &bridge_closed); - if (status_bridge != 0) { + status_bridge = drx_ctrl(demod, DRX_CTRL_I2C_BRIDGE, + &bridge_closed); + if (status_bridge) return status_bridge; - } } status = drxbsp_tuner_set_frequency(demod->my_tuner, - tuner_mode, channel->frequency); + tuner_mode, channel->frequency); /* attempt restoring bridge before checking status of set_frequency */ if (common_attr->tuner_port_nr == 1) { @@ -796,24 +779,21 @@ ctrl_program_tuner(struct drx_demod_instance *demod, struct drx_channel *channel status_bridge = drx_ctrl(demod, DRX_CTRL_I2C_BRIDGE, &bridge_closed); - if (status_bridge != 0) { + if (status_bridge) return status_bridge; - } } /* now check status of drxbsp_tuner_set_frequency */ - if (status != 0) { + if (status) return status; - } /* get actual RF and IF frequencies from tuner */ status = drxbsp_tuner_get_frequency(demod->my_tuner, tuner_mode, &(channel->frequency), &(if_frequency)); - if (status != 0) { + if (status) return status; - } /* update common attributes with information available from this function; TODO: check if this is required and safe */ @@ -839,29 +819,27 @@ static int ctrl_dump_registers(struct drx_demod_instance *demod, { u16 i = 0; - if (registers == NULL) { - /* registers not supplied */ - return -EINVAL; - } + if (registers == NULL) + return -EINVAL; /* registers not supplied */ /* start dumping registers */ - while (registers[i].address != 0) { + while (registers[i].address) { int status = -EIO; u16 value = 0; u32 data = 0; - status = - demod->my_access_funct->read_reg16func(demod->my_i2c_dev_addr, + status = demod->my_access_funct->read_reg16func(demod->my_i2c_dev_addr, registers[i].address, &value, 0); data = (u32) value; - if (status != 0) { - /* no breakouts; - depending on device ID, some HW blocks might not be available */ + /* + * On error: no breakouts; + * depending on device ID, some HW blocks might not be available + */ + if (status) data |= ((u32) status) << 16; - } registers[i].data = data; i++; } @@ -989,9 +967,8 @@ ctrl_u_code(struct drx_demod_instance *demod, dev_addr = demod->my_i2c_dev_addr; /* Check arguments */ - if ((mc_info == NULL) || (mc_info->mc_data == NULL)) { + if ((mc_info == NULL) || (mc_info->mc_data == NULL)) return -EINVAL; - } mc_data = mc_info->mc_data; @@ -1001,10 +978,8 @@ ctrl_u_code(struct drx_demod_instance *demod, mc_nr_of_blks = u_code_read16(mc_data); mc_data += sizeof(u16); - if ((mc_magic_word != DRX_UCODE_MAGIC_WORD) || (mc_nr_of_blks == 0)) { - /* wrong endianess or wrong data ? */ - return -EINVAL; - } + if ((mc_magic_word != DRX_UCODE_MAGIC_WORD) || (mc_nr_of_blks == 0)) + return -EINVAL; /* wrong endianess or wrong data ? */ /* Scan microcode blocks first for version info if uploading */ if (action == UCODE_UPLOAD) { @@ -1049,9 +1024,8 @@ ctrl_u_code(struct drx_demod_instance *demod, It is also valid if no validation control exists. */ rc = drx_ctrl(demod, DRX_CTRL_VALIDATE_UCODE, NULL); - if (rc != 0 && rc != -ENOTSUPP) { + if (rc != 0 && rc != -ENOTSUPP) return rc; - } /* Restore data pointer */ mc_data = mc_info->mc_data + 2 * sizeof(u16); @@ -1149,9 +1123,8 @@ ctrl_u_code(struct drx_demod_instance *demod, mc_data_buffer, bytes_to_compare); - if (result != 0) { + if (result != 0) return -EIO; - } curr_addr += ((dr_xaddr_t) @@ -1205,9 +1178,8 @@ ctrl_version(struct drx_demod_instance *demod, struct drx_version_list **version int return_status = -EIO; /* Check arguments */ - if (version_list == NULL) { + if (version_list == NULL) return -EINVAL; - } /* Get version info list from demod */ return_status = (*(demod->my_demod_funct->ctrl_func)) (demod, @@ -1231,9 +1203,8 @@ ctrl_version(struct drx_demod_instance *demod, struct drx_version_list **version /* Return version info in "bottom-up" order. This way, multiple devices can be handled without using malloc. */ struct drx_version_list *current_list_element = demod_version_list; - while (current_list_element->next != NULL) { + while (current_list_element->next != NULL) current_list_element = current_list_element->next; - } current_list_element->next = &drx_driver_core_version_list; *version_list = demod_version_list; diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h index 2a78466..c36321b9 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h @@ -2056,275 +2056,275 @@ Conversion from enum values to human readable form. /* standard */ #define DRX_STR_STANDARD(x) ( \ - (x == DRX_STANDARD_DVBT) ? "DVB-T" : \ - (x == DRX_STANDARD_8VSB) ? "8VSB" : \ - (x == DRX_STANDARD_NTSC) ? "NTSC" : \ - (x == DRX_STANDARD_PAL_SECAM_BG) ? "PAL/SECAM B/G" : \ - (x == DRX_STANDARD_PAL_SECAM_DK) ? "PAL/SECAM D/K" : \ - (x == DRX_STANDARD_PAL_SECAM_I) ? "PAL/SECAM I" : \ - (x == DRX_STANDARD_PAL_SECAM_L) ? "PAL/SECAM L" : \ - (x == DRX_STANDARD_PAL_SECAM_LP) ? "PAL/SECAM LP" : \ - (x == DRX_STANDARD_ITU_A) ? "ITU-A" : \ - (x == DRX_STANDARD_ITU_B) ? "ITU-B" : \ - (x == DRX_STANDARD_ITU_C) ? "ITU-C" : \ - (x == DRX_STANDARD_ITU_D) ? "ITU-D" : \ - (x == DRX_STANDARD_FM) ? "FM" : \ - (x == DRX_STANDARD_DTMB) ? "DTMB" : \ - (x == DRX_STANDARD_AUTO) ? "Auto" : \ - (x == DRX_STANDARD_UNKNOWN) ? "Unknown" : \ - "(Invalid)") + (x == DRX_STANDARD_DVBT) ? "DVB-T" : \ + (x == DRX_STANDARD_8VSB) ? "8VSB" : \ + (x == DRX_STANDARD_NTSC) ? "NTSC" : \ + (x == DRX_STANDARD_PAL_SECAM_BG) ? "PAL/SECAM B/G" : \ + (x == DRX_STANDARD_PAL_SECAM_DK) ? "PAL/SECAM D/K" : \ + (x == DRX_STANDARD_PAL_SECAM_I) ? "PAL/SECAM I" : \ + (x == DRX_STANDARD_PAL_SECAM_L) ? "PAL/SECAM L" : \ + (x == DRX_STANDARD_PAL_SECAM_LP) ? "PAL/SECAM LP" : \ + (x == DRX_STANDARD_ITU_A) ? "ITU-A" : \ + (x == DRX_STANDARD_ITU_B) ? "ITU-B" : \ + (x == DRX_STANDARD_ITU_C) ? "ITU-C" : \ + (x == DRX_STANDARD_ITU_D) ? "ITU-D" : \ + (x == DRX_STANDARD_FM) ? "FM" : \ + (x == DRX_STANDARD_DTMB) ? "DTMB" : \ + (x == DRX_STANDARD_AUTO) ? "Auto" : \ + (x == DRX_STANDARD_UNKNOWN) ? "Unknown" : \ + "(Invalid)") /* channel */ #define DRX_STR_BANDWIDTH(x) ( \ - (x == DRX_BANDWIDTH_8MHZ) ? "8 MHz" : \ - (x == DRX_BANDWIDTH_7MHZ) ? "7 MHz" : \ - (x == DRX_BANDWIDTH_6MHZ) ? "6 MHz" : \ - (x == DRX_BANDWIDTH_AUTO) ? "Auto" : \ - (x == DRX_BANDWIDTH_UNKNOWN) ? "Unknown" : \ - "(Invalid)") + (x == DRX_BANDWIDTH_8MHZ) ? "8 MHz" : \ + (x == DRX_BANDWIDTH_7MHZ) ? "7 MHz" : \ + (x == DRX_BANDWIDTH_6MHZ) ? "6 MHz" : \ + (x == DRX_BANDWIDTH_AUTO) ? "Auto" : \ + (x == DRX_BANDWIDTH_UNKNOWN) ? "Unknown" : \ + "(Invalid)") #define DRX_STR_FFTMODE(x) ( \ - (x == DRX_FFTMODE_2K) ? "2k" : \ - (x == DRX_FFTMODE_4K) ? "4k" : \ - (x == DRX_FFTMODE_8K) ? "8k" : \ - (x == DRX_FFTMODE_AUTO) ? "Auto" : \ - (x == DRX_FFTMODE_UNKNOWN) ? "Unknown" : \ - "(Invalid)") + (x == DRX_FFTMODE_2K) ? "2k" : \ + (x == DRX_FFTMODE_4K) ? "4k" : \ + (x == DRX_FFTMODE_8K) ? "8k" : \ + (x == DRX_FFTMODE_AUTO) ? "Auto" : \ + (x == DRX_FFTMODE_UNKNOWN) ? "Unknown" : \ + "(Invalid)") #define DRX_STR_GUARD(x) ( \ - (x == DRX_GUARD_1DIV32) ? "1/32nd" : \ - (x == DRX_GUARD_1DIV16) ? "1/16th" : \ - (x == DRX_GUARD_1DIV8) ? "1/8th" : \ - (x == DRX_GUARD_1DIV4) ? "1/4th" : \ - (x == DRX_GUARD_AUTO) ? "Auto" : \ - (x == DRX_GUARD_UNKNOWN) ? "Unknown" : \ - "(Invalid)") + (x == DRX_GUARD_1DIV32) ? "1/32nd" : \ + (x == DRX_GUARD_1DIV16) ? "1/16th" : \ + (x == DRX_GUARD_1DIV8) ? "1/8th" : \ + (x == DRX_GUARD_1DIV4) ? "1/4th" : \ + (x == DRX_GUARD_AUTO) ? "Auto" : \ + (x == DRX_GUARD_UNKNOWN) ? "Unknown" : \ + "(Invalid)") #define DRX_STR_CONSTELLATION(x) ( \ - (x == DRX_CONSTELLATION_BPSK) ? "BPSK" : \ - (x == DRX_CONSTELLATION_QPSK) ? "QPSK" : \ - (x == DRX_CONSTELLATION_PSK8) ? "PSK8" : \ - (x == DRX_CONSTELLATION_QAM16) ? "QAM16" : \ - (x == DRX_CONSTELLATION_QAM32) ? "QAM32" : \ - (x == DRX_CONSTELLATION_QAM64) ? "QAM64" : \ - (x == DRX_CONSTELLATION_QAM128) ? "QAM128" : \ - (x == DRX_CONSTELLATION_QAM256) ? "QAM256" : \ - (x == DRX_CONSTELLATION_QAM512) ? "QAM512" : \ - (x == DRX_CONSTELLATION_QAM1024) ? "QAM1024" : \ - (x == DRX_CONSTELLATION_QPSK_NR) ? "QPSK_NR" : \ - (x == DRX_CONSTELLATION_AUTO) ? "Auto" : \ - (x == DRX_CONSTELLATION_UNKNOWN) ? "Unknown" : \ - "(Invalid)") + (x == DRX_CONSTELLATION_BPSK) ? "BPSK" : \ + (x == DRX_CONSTELLATION_QPSK) ? "QPSK" : \ + (x == DRX_CONSTELLATION_PSK8) ? "PSK8" : \ + (x == DRX_CONSTELLATION_QAM16) ? "QAM16" : \ + (x == DRX_CONSTELLATION_QAM32) ? "QAM32" : \ + (x == DRX_CONSTELLATION_QAM64) ? "QAM64" : \ + (x == DRX_CONSTELLATION_QAM128) ? "QAM128" : \ + (x == DRX_CONSTELLATION_QAM256) ? "QAM256" : \ + (x == DRX_CONSTELLATION_QAM512) ? "QAM512" : \ + (x == DRX_CONSTELLATION_QAM1024) ? "QAM1024" : \ + (x == DRX_CONSTELLATION_QPSK_NR) ? "QPSK_NR" : \ + (x == DRX_CONSTELLATION_AUTO) ? "Auto" : \ + (x == DRX_CONSTELLATION_UNKNOWN) ? "Unknown" : \ + "(Invalid)") #define DRX_STR_CODERATE(x) ( \ - (x == DRX_CODERATE_1DIV2) ? "1/2nd" : \ - (x == DRX_CODERATE_2DIV3) ? "2/3rd" : \ - (x == DRX_CODERATE_3DIV4) ? "3/4th" : \ - (x == DRX_CODERATE_5DIV6) ? "5/6th" : \ - (x == DRX_CODERATE_7DIV8) ? "7/8th" : \ - (x == DRX_CODERATE_AUTO) ? "Auto" : \ - (x == DRX_CODERATE_UNKNOWN) ? "Unknown" : \ - "(Invalid)") + (x == DRX_CODERATE_1DIV2) ? "1/2nd" : \ + (x == DRX_CODERATE_2DIV3) ? "2/3rd" : \ + (x == DRX_CODERATE_3DIV4) ? "3/4th" : \ + (x == DRX_CODERATE_5DIV6) ? "5/6th" : \ + (x == DRX_CODERATE_7DIV8) ? "7/8th" : \ + (x == DRX_CODERATE_AUTO) ? "Auto" : \ + (x == DRX_CODERATE_UNKNOWN) ? "Unknown" : \ + "(Invalid)") #define DRX_STR_HIERARCHY(x) ( \ - (x == DRX_HIERARCHY_NONE) ? "None" : \ - (x == DRX_HIERARCHY_ALPHA1) ? "Alpha=1" : \ - (x == DRX_HIERARCHY_ALPHA2) ? "Alpha=2" : \ - (x == DRX_HIERARCHY_ALPHA4) ? "Alpha=4" : \ - (x == DRX_HIERARCHY_AUTO) ? "Auto" : \ - (x == DRX_HIERARCHY_UNKNOWN) ? "Unknown" : \ - "(Invalid)") + (x == DRX_HIERARCHY_NONE) ? "None" : \ + (x == DRX_HIERARCHY_ALPHA1) ? "Alpha=1" : \ + (x == DRX_HIERARCHY_ALPHA2) ? "Alpha=2" : \ + (x == DRX_HIERARCHY_ALPHA4) ? "Alpha=4" : \ + (x == DRX_HIERARCHY_AUTO) ? "Auto" : \ + (x == DRX_HIERARCHY_UNKNOWN) ? "Unknown" : \ + "(Invalid)") #define DRX_STR_PRIORITY(x) ( \ - (x == DRX_PRIORITY_LOW) ? "Low" : \ - (x == DRX_PRIORITY_HIGH) ? "High" : \ - (x == DRX_PRIORITY_UNKNOWN) ? "Unknown" : \ - "(Invalid)") + (x == DRX_PRIORITY_LOW) ? "Low" : \ + (x == DRX_PRIORITY_HIGH) ? "High" : \ + (x == DRX_PRIORITY_UNKNOWN) ? "Unknown" : \ + "(Invalid)") #define DRX_STR_MIRROR(x) ( \ - (x == DRX_MIRROR_NO) ? "Normal" : \ - (x == DRX_MIRROR_YES) ? "Mirrored" : \ - (x == DRX_MIRROR_AUTO) ? "Auto" : \ - (x == DRX_MIRROR_UNKNOWN) ? "Unknown" : \ - "(Invalid)") + (x == DRX_MIRROR_NO) ? "Normal" : \ + (x == DRX_MIRROR_YES) ? "Mirrored" : \ + (x == DRX_MIRROR_AUTO) ? "Auto" : \ + (x == DRX_MIRROR_UNKNOWN) ? "Unknown" : \ + "(Invalid)") #define DRX_STR_CLASSIFICATION(x) ( \ - (x == DRX_CLASSIFICATION_GAUSS) ? "Gaussion" : \ - (x == DRX_CLASSIFICATION_HVY_GAUSS) ? "Heavy Gaussion" : \ - (x == DRX_CLASSIFICATION_COCHANNEL) ? "Co-channel" : \ - (x == DRX_CLASSIFICATION_STATIC) ? "Static echo" : \ - (x == DRX_CLASSIFICATION_MOVING) ? "Moving echo" : \ - (x == DRX_CLASSIFICATION_ZERODB) ? "Zero dB echo" : \ - (x == DRX_CLASSIFICATION_UNKNOWN) ? "Unknown" : \ - (x == DRX_CLASSIFICATION_AUTO) ? "Auto" : \ - "(Invalid)") + (x == DRX_CLASSIFICATION_GAUSS) ? "Gaussion" : \ + (x == DRX_CLASSIFICATION_HVY_GAUSS) ? "Heavy Gaussion" : \ + (x == DRX_CLASSIFICATION_COCHANNEL) ? "Co-channel" : \ + (x == DRX_CLASSIFICATION_STATIC) ? "Static echo" : \ + (x == DRX_CLASSIFICATION_MOVING) ? "Moving echo" : \ + (x == DRX_CLASSIFICATION_ZERODB) ? "Zero dB echo" : \ + (x == DRX_CLASSIFICATION_UNKNOWN) ? "Unknown" : \ + (x == DRX_CLASSIFICATION_AUTO) ? "Auto" : \ + "(Invalid)") #define DRX_STR_INTERLEAVEMODE(x) ( \ - (x == DRX_INTERLEAVEMODE_I128_J1) ? "I128_J1" : \ - (x == DRX_INTERLEAVEMODE_I128_J1_V2) ? "I128_J1_V2" : \ - (x == DRX_INTERLEAVEMODE_I128_J2) ? "I128_J2" : \ - (x == DRX_INTERLEAVEMODE_I64_J2) ? "I64_J2" : \ - (x == DRX_INTERLEAVEMODE_I128_J3) ? "I128_J3" : \ - (x == DRX_INTERLEAVEMODE_I32_J4) ? "I32_J4" : \ - (x == DRX_INTERLEAVEMODE_I128_J4) ? "I128_J4" : \ - (x == DRX_INTERLEAVEMODE_I16_J8) ? "I16_J8" : \ - (x == DRX_INTERLEAVEMODE_I128_J5) ? "I128_J5" : \ - (x == DRX_INTERLEAVEMODE_I8_J16) ? "I8_J16" : \ - (x == DRX_INTERLEAVEMODE_I128_J6) ? "I128_J6" : \ - (x == DRX_INTERLEAVEMODE_RESERVED_11) ? "Reserved 11" : \ - (x == DRX_INTERLEAVEMODE_I128_J7) ? "I128_J7" : \ - (x == DRX_INTERLEAVEMODE_RESERVED_13) ? "Reserved 13" : \ - (x == DRX_INTERLEAVEMODE_I128_J8) ? "I128_J8" : \ - (x == DRX_INTERLEAVEMODE_RESERVED_15) ? "Reserved 15" : \ - (x == DRX_INTERLEAVEMODE_I12_J17) ? "I12_J17" : \ - (x == DRX_INTERLEAVEMODE_I5_J4) ? "I5_J4" : \ - (x == DRX_INTERLEAVEMODE_B52_M240) ? "B52_M240" : \ - (x == DRX_INTERLEAVEMODE_B52_M720) ? "B52_M720" : \ - (x == DRX_INTERLEAVEMODE_B52_M48) ? "B52_M48" : \ - (x == DRX_INTERLEAVEMODE_B52_M0) ? "B52_M0" : \ - (x == DRX_INTERLEAVEMODE_UNKNOWN) ? "Unknown" : \ - (x == DRX_INTERLEAVEMODE_AUTO) ? "Auto" : \ - "(Invalid)") + (x == DRX_INTERLEAVEMODE_I128_J1) ? "I128_J1" : \ + (x == DRX_INTERLEAVEMODE_I128_J1_V2) ? "I128_J1_V2" : \ + (x == DRX_INTERLEAVEMODE_I128_J2) ? "I128_J2" : \ + (x == DRX_INTERLEAVEMODE_I64_J2) ? "I64_J2" : \ + (x == DRX_INTERLEAVEMODE_I128_J3) ? "I128_J3" : \ + (x == DRX_INTERLEAVEMODE_I32_J4) ? "I32_J4" : \ + (x == DRX_INTERLEAVEMODE_I128_J4) ? "I128_J4" : \ + (x == DRX_INTERLEAVEMODE_I16_J8) ? "I16_J8" : \ + (x == DRX_INTERLEAVEMODE_I128_J5) ? "I128_J5" : \ + (x == DRX_INTERLEAVEMODE_I8_J16) ? "I8_J16" : \ + (x == DRX_INTERLEAVEMODE_I128_J6) ? "I128_J6" : \ + (x == DRX_INTERLEAVEMODE_RESERVED_11) ? "Reserved 11" : \ + (x == DRX_INTERLEAVEMODE_I128_J7) ? "I128_J7" : \ + (x == DRX_INTERLEAVEMODE_RESERVED_13) ? "Reserved 13" : \ + (x == DRX_INTERLEAVEMODE_I128_J8) ? "I128_J8" : \ + (x == DRX_INTERLEAVEMODE_RESERVED_15) ? "Reserved 15" : \ + (x == DRX_INTERLEAVEMODE_I12_J17) ? "I12_J17" : \ + (x == DRX_INTERLEAVEMODE_I5_J4) ? "I5_J4" : \ + (x == DRX_INTERLEAVEMODE_B52_M240) ? "B52_M240" : \ + (x == DRX_INTERLEAVEMODE_B52_M720) ? "B52_M720" : \ + (x == DRX_INTERLEAVEMODE_B52_M48) ? "B52_M48" : \ + (x == DRX_INTERLEAVEMODE_B52_M0) ? "B52_M0" : \ + (x == DRX_INTERLEAVEMODE_UNKNOWN) ? "Unknown" : \ + (x == DRX_INTERLEAVEMODE_AUTO) ? "Auto" : \ + "(Invalid)") #define DRX_STR_LDPC(x) ( \ - (x == DRX_LDPC_0_4) ? "0.4" : \ - (x == DRX_LDPC_0_6) ? "0.6" : \ - (x == DRX_LDPC_0_8) ? "0.8" : \ - (x == DRX_LDPC_AUTO) ? "Auto" : \ - (x == DRX_LDPC_UNKNOWN) ? "Unknown" : \ - "(Invalid)") + (x == DRX_LDPC_0_4) ? "0.4" : \ + (x == DRX_LDPC_0_6) ? "0.6" : \ + (x == DRX_LDPC_0_8) ? "0.8" : \ + (x == DRX_LDPC_AUTO) ? "Auto" : \ + (x == DRX_LDPC_UNKNOWN) ? "Unknown" : \ + "(Invalid)") #define DRX_STR_CARRIER(x) ( \ - (x == DRX_CARRIER_MULTI) ? "Multi" : \ - (x == DRX_CARRIER_SINGLE) ? "Single" : \ - (x == DRX_CARRIER_AUTO) ? "Auto" : \ - (x == DRX_CARRIER_UNKNOWN) ? "Unknown" : \ - "(Invalid)") + (x == DRX_CARRIER_MULTI) ? "Multi" : \ + (x == DRX_CARRIER_SINGLE) ? "Single" : \ + (x == DRX_CARRIER_AUTO) ? "Auto" : \ + (x == DRX_CARRIER_UNKNOWN) ? "Unknown" : \ + "(Invalid)") #define DRX_STR_FRAMEMODE(x) ( \ - (x == DRX_FRAMEMODE_420) ? "420" : \ - (x == DRX_FRAMEMODE_595) ? "595" : \ - (x == DRX_FRAMEMODE_945) ? "945" : \ - (x == DRX_FRAMEMODE_420_FIXED_PN) ? "420 with fixed PN" : \ - (x == DRX_FRAMEMODE_945_FIXED_PN) ? "945 with fixed PN" : \ - (x == DRX_FRAMEMODE_AUTO) ? "Auto" : \ - (x == DRX_FRAMEMODE_UNKNOWN) ? "Unknown" : \ - "(Invalid)") + (x == DRX_FRAMEMODE_420) ? "420" : \ + (x == DRX_FRAMEMODE_595) ? "595" : \ + (x == DRX_FRAMEMODE_945) ? "945" : \ + (x == DRX_FRAMEMODE_420_FIXED_PN) ? "420 with fixed PN" : \ + (x == DRX_FRAMEMODE_945_FIXED_PN) ? "945 with fixed PN" : \ + (x == DRX_FRAMEMODE_AUTO) ? "Auto" : \ + (x == DRX_FRAMEMODE_UNKNOWN) ? "Unknown" : \ + "(Invalid)") #define DRX_STR_PILOT(x) ( \ - (x == DRX_PILOT_ON) ? "On" : \ - (x == DRX_PILOT_OFF) ? "Off" : \ - (x == DRX_PILOT_AUTO) ? "Auto" : \ - (x == DRX_PILOT_UNKNOWN) ? "Unknown" : \ - "(Invalid)") + (x == DRX_PILOT_ON) ? "On" : \ + (x == DRX_PILOT_OFF) ? "Off" : \ + (x == DRX_PILOT_AUTO) ? "Auto" : \ + (x == DRX_PILOT_UNKNOWN) ? "Unknown" : \ + "(Invalid)") /* TPS */ #define DRX_STR_TPS_FRAME(x) ( \ - (x == DRX_TPS_FRAME1) ? "Frame1" : \ - (x == DRX_TPS_FRAME2) ? "Frame2" : \ - (x == DRX_TPS_FRAME3) ? "Frame3" : \ - (x == DRX_TPS_FRAME4) ? "Frame4" : \ - (x == DRX_TPS_FRAME_UNKNOWN) ? "Unknown" : \ - "(Invalid)") + (x == DRX_TPS_FRAME1) ? "Frame1" : \ + (x == DRX_TPS_FRAME2) ? "Frame2" : \ + (x == DRX_TPS_FRAME3) ? "Frame3" : \ + (x == DRX_TPS_FRAME4) ? "Frame4" : \ + (x == DRX_TPS_FRAME_UNKNOWN) ? "Unknown" : \ + "(Invalid)") /* lock status */ #define DRX_STR_LOCKSTATUS(x) ( \ - (x == DRX_NEVER_LOCK) ? "Never" : \ - (x == DRX_NOT_LOCKED) ? "No" : \ - (x == DRX_LOCKED) ? "Locked" : \ - (x == DRX_LOCK_STATE_1) ? "Lock state 1" : \ - (x == DRX_LOCK_STATE_2) ? "Lock state 2" : \ - (x == DRX_LOCK_STATE_3) ? "Lock state 3" : \ - (x == DRX_LOCK_STATE_4) ? "Lock state 4" : \ - (x == DRX_LOCK_STATE_5) ? "Lock state 5" : \ - (x == DRX_LOCK_STATE_6) ? "Lock state 6" : \ - (x == DRX_LOCK_STATE_7) ? "Lock state 7" : \ - (x == DRX_LOCK_STATE_8) ? "Lock state 8" : \ - (x == DRX_LOCK_STATE_9) ? "Lock state 9" : \ - "(Invalid)") + (x == DRX_NEVER_LOCK) ? "Never" : \ + (x == DRX_NOT_LOCKED) ? "No" : \ + (x == DRX_LOCKED) ? "Locked" : \ + (x == DRX_LOCK_STATE_1) ? "Lock state 1" : \ + (x == DRX_LOCK_STATE_2) ? "Lock state 2" : \ + (x == DRX_LOCK_STATE_3) ? "Lock state 3" : \ + (x == DRX_LOCK_STATE_4) ? "Lock state 4" : \ + (x == DRX_LOCK_STATE_5) ? "Lock state 5" : \ + (x == DRX_LOCK_STATE_6) ? "Lock state 6" : \ + (x == DRX_LOCK_STATE_7) ? "Lock state 7" : \ + (x == DRX_LOCK_STATE_8) ? "Lock state 8" : \ + (x == DRX_LOCK_STATE_9) ? "Lock state 9" : \ + "(Invalid)") /* version information , modules */ #define DRX_STR_MODULE(x) ( \ - (x == DRX_MODULE_DEVICE) ? "Device" : \ - (x == DRX_MODULE_MICROCODE) ? "Microcode" : \ - (x == DRX_MODULE_DRIVERCORE) ? "CoreDriver" : \ - (x == DRX_MODULE_DEVICEDRIVER) ? "DeviceDriver" : \ - (x == DRX_MODULE_BSP_I2C) ? "BSP I2C" : \ - (x == DRX_MODULE_BSP_TUNER) ? "BSP Tuner" : \ - (x == DRX_MODULE_BSP_HOST) ? "BSP Host" : \ - (x == DRX_MODULE_DAP) ? "Data Access Protocol" : \ - (x == DRX_MODULE_UNKNOWN) ? "Unknown" : \ - "(Invalid)") + (x == DRX_MODULE_DEVICE) ? "Device" : \ + (x == DRX_MODULE_MICROCODE) ? "Microcode" : \ + (x == DRX_MODULE_DRIVERCORE) ? "CoreDriver" : \ + (x == DRX_MODULE_DEVICEDRIVER) ? "DeviceDriver" : \ + (x == DRX_MODULE_BSP_I2C) ? "BSP I2C" : \ + (x == DRX_MODULE_BSP_TUNER) ? "BSP Tuner" : \ + (x == DRX_MODULE_BSP_HOST) ? "BSP Host" : \ + (x == DRX_MODULE_DAP) ? "Data Access Protocol" : \ + (x == DRX_MODULE_UNKNOWN) ? "Unknown" : \ + "(Invalid)") #define DRX_STR_POWER_MODE(x) ( \ - (x == DRX_POWER_UP) ? "DRX_POWER_UP " : \ - (x == DRX_POWER_MODE_1) ? "DRX_POWER_MODE_1" : \ - (x == DRX_POWER_MODE_2) ? "DRX_POWER_MODE_2" : \ - (x == DRX_POWER_MODE_3) ? "DRX_POWER_MODE_3" : \ - (x == DRX_POWER_MODE_4) ? "DRX_POWER_MODE_4" : \ - (x == DRX_POWER_MODE_5) ? "DRX_POWER_MODE_5" : \ - (x == DRX_POWER_MODE_6) ? "DRX_POWER_MODE_6" : \ - (x == DRX_POWER_MODE_7) ? "DRX_POWER_MODE_7" : \ - (x == DRX_POWER_MODE_8) ? "DRX_POWER_MODE_8" : \ - (x == DRX_POWER_MODE_9) ? "DRX_POWER_MODE_9" : \ - (x == DRX_POWER_MODE_10) ? "DRX_POWER_MODE_10" : \ - (x == DRX_POWER_MODE_11) ? "DRX_POWER_MODE_11" : \ - (x == DRX_POWER_MODE_12) ? "DRX_POWER_MODE_12" : \ - (x == DRX_POWER_MODE_13) ? "DRX_POWER_MODE_13" : \ - (x == DRX_POWER_MODE_14) ? "DRX_POWER_MODE_14" : \ - (x == DRX_POWER_MODE_15) ? "DRX_POWER_MODE_15" : \ - (x == DRX_POWER_MODE_16) ? "DRX_POWER_MODE_16" : \ - (x == DRX_POWER_DOWN) ? "DRX_POWER_DOWN " : \ - "(Invalid)") + (x == DRX_POWER_UP) ? "DRX_POWER_UP " : \ + (x == DRX_POWER_MODE_1) ? "DRX_POWER_MODE_1" : \ + (x == DRX_POWER_MODE_2) ? "DRX_POWER_MODE_2" : \ + (x == DRX_POWER_MODE_3) ? "DRX_POWER_MODE_3" : \ + (x == DRX_POWER_MODE_4) ? "DRX_POWER_MODE_4" : \ + (x == DRX_POWER_MODE_5) ? "DRX_POWER_MODE_5" : \ + (x == DRX_POWER_MODE_6) ? "DRX_POWER_MODE_6" : \ + (x == DRX_POWER_MODE_7) ? "DRX_POWER_MODE_7" : \ + (x == DRX_POWER_MODE_8) ? "DRX_POWER_MODE_8" : \ + (x == DRX_POWER_MODE_9) ? "DRX_POWER_MODE_9" : \ + (x == DRX_POWER_MODE_10) ? "DRX_POWER_MODE_10" : \ + (x == DRX_POWER_MODE_11) ? "DRX_POWER_MODE_11" : \ + (x == DRX_POWER_MODE_12) ? "DRX_POWER_MODE_12" : \ + (x == DRX_POWER_MODE_13) ? "DRX_POWER_MODE_13" : \ + (x == DRX_POWER_MODE_14) ? "DRX_POWER_MODE_14" : \ + (x == DRX_POWER_MODE_15) ? "DRX_POWER_MODE_15" : \ + (x == DRX_POWER_MODE_16) ? "DRX_POWER_MODE_16" : \ + (x == DRX_POWER_DOWN) ? "DRX_POWER_DOWN " : \ + "(Invalid)") #define DRX_STR_OOB_STANDARD(x) ( \ - (x == DRX_OOB_MODE_A) ? "ANSI 55-1 " : \ - (x == DRX_OOB_MODE_B_GRADE_A) ? "ANSI 55-2 A" : \ - (x == DRX_OOB_MODE_B_GRADE_B) ? "ANSI 55-2 B" : \ - "(Invalid)") + (x == DRX_OOB_MODE_A) ? "ANSI 55-1 " : \ + (x == DRX_OOB_MODE_B_GRADE_A) ? "ANSI 55-2 A" : \ + (x == DRX_OOB_MODE_B_GRADE_B) ? "ANSI 55-2 B" : \ + "(Invalid)") #define DRX_STR_AUD_STANDARD(x) ( \ - (x == DRX_AUD_STANDARD_BTSC) ? "BTSC" : \ - (x == DRX_AUD_STANDARD_A2) ? "A2" : \ - (x == DRX_AUD_STANDARD_EIAJ) ? "EIAJ" : \ - (x == DRX_AUD_STANDARD_FM_STEREO) ? "FM Stereo" : \ - (x == DRX_AUD_STANDARD_AUTO) ? "Auto" : \ - (x == DRX_AUD_STANDARD_M_MONO) ? "M-Standard Mono" : \ - (x == DRX_AUD_STANDARD_D_K_MONO) ? "D/K Mono FM" : \ - (x == DRX_AUD_STANDARD_BG_FM) ? "B/G-Dual Carrier FM (A2)" : \ - (x == DRX_AUD_STANDARD_D_K1) ? "D/K1-Dual Carrier FM" : \ - (x == DRX_AUD_STANDARD_D_K2) ? "D/K2-Dual Carrier FM" : \ - (x == DRX_AUD_STANDARD_D_K3) ? "D/K3-Dual Carrier FM" : \ - (x == DRX_AUD_STANDARD_BG_NICAM_FM) ? "B/G-NICAM-FM" : \ - (x == DRX_AUD_STANDARD_L_NICAM_AM) ? "L-NICAM-AM" : \ - (x == DRX_AUD_STANDARD_I_NICAM_FM) ? "I-NICAM-FM" : \ - (x == DRX_AUD_STANDARD_D_K_NICAM_FM) ? "D/K-NICAM-FM" : \ - (x == DRX_AUD_STANDARD_UNKNOWN) ? "Unknown" : \ - "(Invalid)") + (x == DRX_AUD_STANDARD_BTSC) ? "BTSC" : \ + (x == DRX_AUD_STANDARD_A2) ? "A2" : \ + (x == DRX_AUD_STANDARD_EIAJ) ? "EIAJ" : \ + (x == DRX_AUD_STANDARD_FM_STEREO) ? "FM Stereo" : \ + (x == DRX_AUD_STANDARD_AUTO) ? "Auto" : \ + (x == DRX_AUD_STANDARD_M_MONO) ? "M-Standard Mono" : \ + (x == DRX_AUD_STANDARD_D_K_MONO) ? "D/K Mono FM" : \ + (x == DRX_AUD_STANDARD_BG_FM) ? "B/G-Dual Carrier FM (A2)" : \ + (x == DRX_AUD_STANDARD_D_K1) ? "D/K1-Dual Carrier FM" : \ + (x == DRX_AUD_STANDARD_D_K2) ? "D/K2-Dual Carrier FM" : \ + (x == DRX_AUD_STANDARD_D_K3) ? "D/K3-Dual Carrier FM" : \ + (x == DRX_AUD_STANDARD_BG_NICAM_FM) ? "B/G-NICAM-FM" : \ + (x == DRX_AUD_STANDARD_L_NICAM_AM) ? "L-NICAM-AM" : \ + (x == DRX_AUD_STANDARD_I_NICAM_FM) ? "I-NICAM-FM" : \ + (x == DRX_AUD_STANDARD_D_K_NICAM_FM) ? "D/K-NICAM-FM" : \ + (x == DRX_AUD_STANDARD_UNKNOWN) ? "Unknown" : \ + "(Invalid)") #define DRX_STR_AUD_STEREO(x) ( \ - (x == true) ? "Stereo" : \ - (x == false) ? "Mono" : \ - "(Invalid)") + (x == true) ? "Stereo" : \ + (x == false) ? "Mono" : \ + "(Invalid)") #define DRX_STR_AUD_SAP(x) ( \ - (x == true) ? "Present" : \ - (x == false) ? "Not present" : \ - "(Invalid)") + (x == true) ? "Present" : \ + (x == false) ? "Not present" : \ + "(Invalid)") #define DRX_STR_AUD_CARRIER(x) ( \ - (x == true) ? "Present" : \ - (x == false) ? "Not present" : \ - "(Invalid)") + (x == true) ? "Present" : \ + (x == false) ? "Not present" : \ + "(Invalid)") #define DRX_STR_AUD_RDS(x) ( \ - (x == true) ? "Available" : \ - (x == false) ? "Not Available" : \ - "(Invalid)") + (x == true) ? "Available" : \ + (x == false) ? "Not Available" : \ + "(Invalid)") #define DRX_STR_AUD_NICAM_STATUS(x) ( \ - (x == DRX_AUD_NICAM_DETECTED) ? "Detected" : \ - (x == DRX_AUD_NICAM_NOT_DETECTED) ? "Not detected" : \ - (x == DRX_AUD_NICAM_BAD) ? "Bad" : \ - "(Invalid)") + (x == DRX_AUD_NICAM_DETECTED) ? "Detected" : \ + (x == DRX_AUD_NICAM_NOT_DETECTED) ? "Not detected" : \ + (x == DRX_AUD_NICAM_BAD) ? "Bad" : \ + "(Invalid)") #define DRX_STR_RDS_VALID(x) ( \ - (x == true) ? "Valid" : \ - (x == false) ? "Not Valid" : \ - "(Invalid)") + (x == true) ? "Valid" : \ + (x == false) ? "Not Valid" : \ + "(Invalid)") /*------------------------------------------------------------------------- Access macros @@ -2371,29 +2371,29 @@ Access macros /* Macros with device-specific handling are converted to CFG functions */ #define DRX_ACCESSMACRO_SET(demod, value, cfg_name, data_type) \ - do { \ - struct drx_cfg config; \ - data_type cfg_data; \ - config.cfg_type = cfg_name; \ - config.cfg_data = &cfg_data; \ - cfg_data = value; \ - drx_ctrl(demod, DRX_CTRL_SET_CFG, &config); \ - } while (0) + do { \ + struct drx_cfg config; \ + data_type cfg_data; \ + config.cfg_type = cfg_name; \ + config.cfg_data = &cfg_data; \ + cfg_data = value; \ + drx_ctrl(demod, DRX_CTRL_SET_CFG, &config); \ + } while (0) #define DRX_ACCESSMACRO_GET(demod, value, cfg_name, data_type, error_value) \ - do { \ - int cfg_status; \ - struct drx_cfg config; \ - data_type cfg_data; \ - config.cfg_type = cfg_name; \ - config.cfg_data = &cfg_data; \ - cfg_status = drx_ctrl(demod, DRX_CTRL_GET_CFG, &config); \ - if (cfg_status == 0) { \ - value = cfg_data; \ - } else { \ - value = (data_type)error_value; \ - } \ - } while (0) + do { \ + int cfg_status; \ + struct drx_cfg config; \ + data_type cfg_data; \ + config.cfg_type = cfg_name; \ + config.cfg_data = &cfg_data; \ + cfg_status = drx_ctrl(demod, DRX_CTRL_GET_CFG, &config); \ + if (cfg_status == 0) { \ + value = cfg_data; \ + } else { \ + value = (data_type)error_value; \ + } \ + } while (0) /* Configuration functions for usage by Access (XS) Macros */ @@ -2408,9 +2408,9 @@ Access macros /* Access Macros with device-specific handling */ #define DRX_SET_PRESET(d, x) \ - DRX_ACCESSMACRO_SET((d), (x), DRX_XS_CFG_PRESET, char*) + DRX_ACCESSMACRO_SET((d), (x), DRX_XS_CFG_PRESET, char*) #define DRX_GET_PRESET(d, x) \ - DRX_ACCESSMACRO_GET((d), (x), DRX_XS_CFG_PRESET, char*, "ERROR") + DRX_ACCESSMACRO_GET((d), (x), DRX_XS_CFG_PRESET, char*, "ERROR") #define DRX_SET_AUD_BTSC_DETECT(d, x) DRX_ACCESSMACRO_SET((d), (x), \ DRX_XS_CFG_AUD_BTSC_DETECT, enum drx_aud_btsc_detect) diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver_version.h b/drivers/media/dvb-frontends/drx39xyj/drx_driver_version.h index 07986bd..ff05a4f 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver_version.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver_version.h @@ -47,10 +47,6 @@ #ifndef __DRX_DRIVER_VERSION__H__ #define __DRX_DRIVER_VERSION__H__ INCLUDED -#ifdef __cplusplus -extern "C" { -#endif - #ifdef _REGISTERTABLE_ #include extern register_table_t drx_driver_version[]; @@ -69,9 +65,6 @@ extern "C" { #define VERSION_MINOR 0 #define VERSION_PATCH 56 -#ifdef __cplusplus -} -#endif #endif /* __DRX_DRIVER_VERSION__H__ */ /* * End of file (drx_driver_version.h) diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.h b/drivers/media/dvb-frontends/drx39xyj/drxj.h index c38245e..6d46513 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.h +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.h @@ -27,14 +27,10 @@ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ -/** -* \file $Id: drxj.h,v 1.132 2009/12/22 12:13:48 danielg Exp $ -* -* \brief DRXJ specific header file -* -* \author Dragan Savic, Milos Nikolic, Mihajlo Katona, Tao Ding, Paul Janssen + DRXJ specific header file + + Authors: Dragan Savic, Milos Nikolic, Mihajlo Katona, Tao Ding, Paul Janssen */ #ifndef __DRXJ_H__ @@ -46,10 +42,6 @@ INCLUDES #include "drx_driver.h" #include "drx_dap_fasi.h" -#ifdef __cplusplus -extern "C" { -#endif - /* Check DRX-J specific dap condition */ /* Multi master mode and short addr format only will not work. RMW, CRC reset, broadcast and switching back to single master mode @@ -322,7 +314,7 @@ struct drxj_cfg_oob_misc { bool dig_gain_lock; bool ana_gain_lock; u8 state; - }; +}; /* * Index of in array of coef @@ -558,27 +550,6 @@ Access MACROS #define DRXJ_ATTR_BTSC_DETECT(d) \ (((struct drxj_data *)(d)->my_ext_attr)->aud_data.btsc_detect) -/** -* \brief Actual access macros -* \param d pointer to demod instance -* \param x value to set or to get -* -* SET macros must be used to set the value of an attribute. -* GET macros must be used to retrieve the value of an attribute. -* Depending on the value of DRX_USE_ACCESS_FUNCTIONS the macro's will be -* substituted by "direct-access-inline-code" or a function call. -* -*/ -#define DRXJ_GET_BTSC_DETECT(d, x) \ - do { \ - (x) = DRXJ_ATTR_BTSC_DETECT((d); \ - } while (0) - -#define DRXJ_SET_BTSC_DETECT(d, x) \ - do { \ - DRXJ_ATTR_BTSC_DETECT(d) = (x); \ - } while (0) - /*------------------------------------------------------------------------- DEFINES -------------------------------------------------------------------------*/ @@ -669,12 +640,12 @@ DEFINES /* Convert OOB lock status to string */ #define DRXJ_STR_OOB_LOCKSTATUS(x) ( \ - (x == DRX_NEVER_LOCK) ? "Never" : \ - (x == DRX_NOT_LOCKED) ? "No" : \ - (x == DRX_LOCKED) ? "Locked" : \ - (x == DRX_LOCK_STATE_1) ? "AGC lock" : \ - (x == DRX_LOCK_STATE_2) ? "sync lock" : \ - "(Invalid)") + (x == DRX_NEVER_LOCK) ? "Never" : \ + (x == DRX_NOT_LOCKED) ? "No" : \ + (x == DRX_LOCKED) ? "Locked" : \ + (x == DRX_LOCK_STATE_1) ? "AGC lock" : \ + (x == DRX_LOCK_STATE_2) ? "sync lock" : \ + "(Invalid)") /*------------------------------------------------------------------------- ENUM @@ -706,7 +677,4 @@ Exported GLOBAL VARIABLES /*------------------------------------------------------------------------- THE END -------------------------------------------------------------------------*/ -#ifdef __cplusplus -} -#endif #endif /* __DRXJ_H__ */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj_map.h b/drivers/media/dvb-frontends/drx39xyj/drxj_map.h index af42754..0bbd4ae 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj_map.h +++ b/drivers/media/dvb-frontends/drx39xyj/drxj_map.h @@ -47,10 +47,6 @@ #ifndef __DRXJ_MAP__H__ #define __DRXJ_MAP__H__ INCLUDED -#ifdef __cplusplus -extern "C" { -#endif - #ifdef _REGISTERTABLE_ #include extern register_table_t drxj_map[]; @@ -15056,7 +15052,4 @@ extern "C" { #define VSB_EQTAP_RAM_EQTAP_RAM__M 0xFFF #define VSB_EQTAP_RAM_EQTAP_RAM__PRE 0x0 -#ifdef __cplusplus -} -#endif #endif -- cgit v1.1 From 9cf5370e3150f853cd9fa5a2537d6eb69acd703b Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Fri, 17 Jan 2014 16:02:09 -0300 Subject: [media] drx-j: remove the useless microcode_size This var is not used. Remove it from the code, as we'll now be converting the driver to load the firmware from an external file. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drx_driver.h | 4 ---- drivers/media/dvb-frontends/drx39xyj/drxj.c | 10 +++------- 2 files changed, 3 insertions(+), 11 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h index c36321b9..f5add1a 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h @@ -1021,8 +1021,6 @@ STRUCTS struct drxu_code_info { u8 *mc_data; /**< Pointer to microcode image. */ - u16 mc_size; - /**< Microcode image size. */ }; /** @@ -1932,7 +1930,6 @@ struct drx_reg_dump { struct drx_common_attr { /* Microcode (firmware) attributes */ u8 *microcode; /**< Pointer to microcode image. */ - u16 microcode_size; /**< Size of microcode image in bytes. */ bool verify_microcode; /**< Use microcode verify or not. */ @@ -2351,7 +2348,6 @@ Access macros #define DRX_ATTR_CACHESTANDARD(d) ((d)->my_common_attr->di_cache_standard) #define DRX_ATTR_CURRENTCHANNEL(d) ((d)->my_common_attr->current_channel) #define DRX_ATTR_MICROCODE(d) ((d)->my_common_attr->microcode) -#define DRX_ATTR_MICROCODESIZE(d) ((d)->my_common_attr->microcode_size) #define DRX_ATTR_VERIFYMICROCODE(d) ((d)->my_common_attr->verify_microcode) #define DRX_ATTR_CAPABILITIES(d) ((d)->my_common_attr->capabilities) #define DRX_ATTR_PRODUCTID(d) ((d)->my_common_attr->product_id) diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index c047452..e21dd5a 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -876,7 +876,6 @@ struct i2c_device_addr drxj_default_addr_g = { */ struct drx_common_attr drxj_default_comm_attr_g = { (u8 *)NULL, /* ucode ptr */ - 0, /* ucode size */ true, /* ucode verify switch */ {0}, /* version record */ @@ -12171,7 +12170,6 @@ trouble ? /* Check if audio microcode is already uploaded */ if (!(ext_attr->flag_aud_mc_uploaded)) { ucode_info.mc_data = common_attr->microcode; - ucode_info.mc_size = common_attr->microcode_size; /* Upload only audio microcode */ rc = ctrl_u_code_upload(demod, &ucode_info, UCODE_UPLOAD, true); @@ -18831,8 +18829,8 @@ bool is_mc_block_audio(u32 addr) */ static int ctrl_u_code_upload(struct drx_demod_instance *demod, - struct drxu_code_info *mc_info, - enum drxu_code_actionaction, bool upload_audio_mc) + struct drxu_code_info *mc_info, + enum drxu_code_actionaction, bool upload_audio_mc) { u16 i = 0; u16 mc_nr_of_blks = 0; @@ -18846,8 +18844,7 @@ ctrl_u_code_upload(struct drx_demod_instance *demod, ext_attr = (struct drxj_data *) demod->my_ext_attr; /* Check arguments */ - if ((mc_info == NULL) || - (mc_info->mc_data == NULL) || (mc_info->mc_size == 0)) { + if (!mc_info || !mc_info->mc_data) { return -EINVAL; } @@ -20147,7 +20144,6 @@ int drxj_open(struct drx_demod_instance *demod) pretend device is already open */ common_attr->is_opened = true; ucode_info.mc_data = common_attr->microcode; - ucode_info.mc_size = common_attr->microcode_size; #ifdef DRXJ_SPLIT_UCODE_UPLOAD /* Upload microcode without audio part */ -- cgit v1.1 From 29b93d8f9ca0635281a6c27f778355caacfc59be Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sat, 18 Jan 2014 07:38:30 -0300 Subject: [media] drx-j: Fix release and error path on drx39xxj.c There are memory leaks on both DVB release and dvb attach error path. Fix them. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drx39xxj.c | 31 +++++++++++++++---------- 1 file changed, 19 insertions(+), 12 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c index e5f276f..44e9baf 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c @@ -318,6 +318,12 @@ static int drx39xxj_get_tune_settings(struct dvb_frontend *fe, static void drx39xxj_release(struct dvb_frontend *fe) { struct drx39xxj_state *state = fe->demodulator_priv; + struct drx_demod_instance *demod = state->demod; + + kfree(demod->my_ext_attr); + kfree(demod->my_common_attr); + kfree(demod->my_i2c_dev_addr); + kfree(demod); kfree(state); } @@ -378,16 +384,14 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) demod->my_ext_attr = demod_ext_attr; memcpy(demod->my_ext_attr, &drxj_data_g, sizeof(struct drxj_data)); - ((struct drxj_data *)demod->my_ext_attr)->uio_sma_tx_mode = - DRX_UIO_MODE_READWRITE; + ((struct drxj_data *)demod->my_ext_attr)->uio_sma_tx_mode = DRX_UIO_MODE_READWRITE; demod->my_tuner = NULL; result = drx_open(demod); if (result != 0) { pr_err("DRX open failed! Aborting\n"); - kfree(state); - return NULL; + goto error; } /* Turn off the LNA */ @@ -395,9 +399,9 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) uio_cfg.mode = DRX_UIO_MODE_READWRITE; /* Configure user-I/O #3: enable read/write */ result = drx_ctrl(demod, DRX_CTRL_UIO_CFG, &uio_cfg); - if (result != 0) { + if (result) { pr_err("Failed to setup LNA GPIO!\n"); - return NULL; + goto error; } uio_data.uio = DRX_UIO1; @@ -405,7 +409,7 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) result = drx_ctrl(demod, DRX_CTRL_UIO_WRITE, &uio_data); if (result != 0) { pr_err("Failed to disable LNA!\n"); - return NULL; + goto error; } /* create dvb_frontend */ @@ -416,10 +420,12 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) return &state->frontend; error: - if (state != NULL) - kfree(state); - if (demod != NULL) - kfree(demod); + kfree(demod_ext_attr); + kfree(demod_comm_attr); + kfree(demod_addr); + kfree(demod); + kfree(state); + return NULL; } EXPORT_SYMBOL(drx39xxj_attach); @@ -431,7 +437,8 @@ static struct dvb_frontend_ops drx39xxj_ops = { .frequency_stepsize = 62500, .frequency_min = 51000000, .frequency_max = 858000000, - .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB}, + .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB + }, .init = drx39xxj_init, .i2c_gate_ctrl = drx39xxj_i2c_gate_ctrl, -- cgit v1.1 From 782ae20df2af894c6840cb2da1221b28dcf3e969 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sat, 18 Jan 2014 11:12:46 -0300 Subject: [media] drx-j: Be sure that all allocated data are properly initialized The state struct is allocated without cleaning the memory. This causes random bugs. Clean it, and move the memcpy functions just below each kalloc, to be clearer that all those data are properly filled. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drx39xxj.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c index 44e9baf..a19547b 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c @@ -342,7 +342,7 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) int result; /* allocate memory for the internal state */ - state = kmalloc(sizeof(struct drx39xxj_state), GFP_KERNEL); + state = kzalloc(sizeof(struct drx39xxj_state), GFP_KERNEL); if (state == NULL) goto error; @@ -353,39 +353,38 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) demod_addr = kmalloc(sizeof(struct i2c_device_addr), GFP_KERNEL); if (demod_addr == NULL) goto error; + memcpy(demod_addr, &drxj_default_addr_g, + sizeof(struct i2c_device_addr)); demod_comm_attr = kmalloc(sizeof(struct drx_common_attr), GFP_KERNEL); if (demod_comm_attr == NULL) goto error; + memcpy(demod_comm_attr, &drxj_default_comm_attr_g, + sizeof(struct drx_common_attr)); demod_ext_attr = kmalloc(sizeof(struct drxj_data), GFP_KERNEL); if (demod_ext_attr == NULL) goto error; + memcpy(demod_ext_attr, &drxj_data_g, sizeof(struct drxj_data)); /* setup the state */ state->i2c = i2c; state->demod = demod; + /* setup the demod data */ memcpy(demod, &drxj_default_demod_g, sizeof(struct drx_demod_instance)); demod->my_i2c_dev_addr = demod_addr; - memcpy(demod->my_i2c_dev_addr, &drxj_default_addr_g, - sizeof(struct i2c_device_addr)); - demod->my_i2c_dev_addr->user_data = state; demod->my_common_attr = demod_comm_attr; - memcpy(demod->my_common_attr, &drxj_default_comm_attr_g, - sizeof(struct drx_common_attr)); + demod->my_i2c_dev_addr->user_data = state; demod->my_common_attr->microcode = DRXJ_MC_MAIN; #if 0 demod->my_common_attr->verify_microcode = false; #endif demod->my_common_attr->verify_microcode = true; demod->my_common_attr->intermediate_freq = 5000; - demod->my_ext_attr = demod_ext_attr; - memcpy(demod->my_ext_attr, &drxj_data_g, sizeof(struct drxj_data)); - ((struct drxj_data *)demod->my_ext_attr)->uio_sma_tx_mode = DRX_UIO_MODE_READWRITE; - + ((struct drxj_data *)demod_ext_attr)->uio_sma_tx_mode = DRX_UIO_MODE_READWRITE; demod->my_tuner = NULL; result = drx_open(demod); -- cgit v1.1 From b48293db4a348e9759c1f8a41a84f2e9f559decf Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sat, 18 Jan 2014 11:13:02 -0300 Subject: [media] drx-j: dynamically load the firmware Instead of hardcoding the firmware files together with the driver, use request_firmware() way, loading it from userspace. The firmware files are placed at: http://linuxtv.org/downloads/firmware/#8 And they'll be latter submitted to linux-firmware git tree. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drx39xxj.c | 12 +- drivers/media/dvb-frontends/drx39xyj/drx39xxj.h | 1 + drivers/media/dvb-frontends/drx39xyj/drx_driver.c | 255 +- drivers/media/dvb-frontends/drx39xyj/drx_driver.h | 51 +- drivers/media/dvb-frontends/drx39xyj/drxj.c | 6 +- drivers/media/dvb-frontends/drx39xyj/drxj_mc.h | 7829 -------------------- drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsb.h | 1439 ---- .../media/dvb-frontends/drx39xyj/drxj_mc_vsbqam.h | 2824 ------- 8 files changed, 181 insertions(+), 12236 deletions(-) delete mode 100644 drivers/media/dvb-frontends/drx39xyj/drxj_mc.h delete mode 100644 drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsb.h delete mode 100644 drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsbqam.h diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c index a19547b..f0f14ed 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c @@ -29,9 +29,10 @@ #include "dvb_frontend.h" #include "drx39xxj.h" #include "drx_driver.h" -#include "drxj_mc.h" #include "drxj.h" +#define DRX39XX_MAIN_FIRMWARE "dvb-fe-drxj-mc-1.0.8.fw" + static int drx39xxj_set_powerstate(struct dvb_frontend *fe, int enable) { struct drx39xxj_state *state = fe->demodulator_priv; @@ -323,6 +324,8 @@ static void drx39xxj_release(struct dvb_frontend *fe) kfree(demod->my_ext_attr); kfree(demod->my_common_attr); kfree(demod->my_i2c_dev_addr); + if (demod->firmware) + release_firmware(demod->firmware); kfree(demod); kfree(state); } @@ -377,15 +380,13 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) demod->my_i2c_dev_addr = demod_addr; demod->my_common_attr = demod_comm_attr; demod->my_i2c_dev_addr->user_data = state; - demod->my_common_attr->microcode = DRXJ_MC_MAIN; -#if 0 - demod->my_common_attr->verify_microcode = false; -#endif + demod->my_common_attr->microcode_file = DRX39XX_MAIN_FIRMWARE; demod->my_common_attr->verify_microcode = true; demod->my_common_attr->intermediate_freq = 5000; demod->my_ext_attr = demod_ext_attr; ((struct drxj_data *)demod_ext_attr)->uio_sma_tx_mode = DRX_UIO_MODE_READWRITE; demod->my_tuner = NULL; + demod->i2c = i2c; result = drx_open(demod); if (result != 0) { @@ -455,3 +456,4 @@ static struct dvb_frontend_ops drx39xxj_ops = { MODULE_DESCRIPTION("Micronas DRX39xxj Frontend"); MODULE_AUTHOR("Devin Heitmueller"); MODULE_LICENSE("GPL"); +MODULE_FIRMWARE(DRX39XX_MAIN_FIRMWARE); diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h index a7eb716..8c24d73 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h @@ -33,6 +33,7 @@ struct drx39xxj_state { struct dvb_frontend frontend; int powered_up:1; unsigned int i2c_gate_open:1; + const struct firmware *fw; }; struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c); diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c index bfd02411..194be83 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c @@ -1,4 +1,6 @@ /* + Generic DRX functionality, DRX driver core. + Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. All rights reserved. @@ -28,12 +30,8 @@ POSSIBILITY OF SUCH DAMAGE. */ -/** -* \file $Id: drx_driver.c,v 1.40 2010/01/12 01:24:56 lfeng Exp $ -* -* \brief Generic DRX functionality, DRX driver core. -* -*/ +#define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__ + /*------------------------------------------------------------------------------ INCLUDE FILES @@ -957,32 +955,64 @@ static int ctrl_u_code(struct drx_demod_instance *demod, struct drxu_code_info *mc_info, enum drxu_code_action action) { + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; int rc; u16 i = 0; u16 mc_nr_of_blks = 0; u16 mc_magic_word = 0; - u8 *mc_data = (u8 *)(NULL); - struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); - - dev_addr = demod->my_i2c_dev_addr; + const u8 *mc_data_init = NULL; + u8 *mc_data = NULL; + char *mc_file = mc_info->mc_file; /* Check arguments */ - if ((mc_info == NULL) || (mc_info->mc_data == NULL)) + if (!mc_info || !mc_file) return -EINVAL; - mc_data = mc_info->mc_data; + if (demod->firmware) { + mc_data_init = demod->firmware->data; + mc_data = (void *)mc_data_init; - /* Check data */ - mc_magic_word = u_code_read16(mc_data); - mc_data += sizeof(u16); - mc_nr_of_blks = u_code_read16(mc_data); - mc_data += sizeof(u16); + /* Check data */ + mc_magic_word = u_code_read16(mc_data); + mc_data += sizeof(u16); + mc_nr_of_blks = u_code_read16(mc_data); + mc_data += sizeof(u16); + } else { + const struct firmware *fw = NULL; + unsigned size = 0; - if ((mc_magic_word != DRX_UCODE_MAGIC_WORD) || (mc_nr_of_blks == 0)) - return -EINVAL; /* wrong endianess or wrong data ? */ + rc = request_firmware(&fw, mc_file, demod->i2c->dev.parent); + if (rc < 0) { + pr_err("Couldn't read firmware %s\n", mc_file); + return -ENOENT; + } + demod->firmware = fw; + mc_data_init = demod->firmware->data; + size = demod->firmware->size; + + pr_info("Firmware %s, size %u\n", mc_file, size); + + mc_data = (void *)mc_data_init; + /* Check data */ + if (mc_data - mc_data_init + 2 * sizeof(u16) > size) + goto eof; + mc_magic_word = u_code_read16(mc_data); + mc_data += sizeof(u16); + mc_nr_of_blks = u_code_read16(mc_data); + mc_data += sizeof(u16); + + + if ((mc_magic_word != DRX_UCODE_MAGIC_WORD) || (mc_nr_of_blks == 0)) { + rc = -EINVAL; /* wrong endianess or wrong data ? */ + pr_err("Firmware magic word doesn't match\n"); + goto release; + } + + /* + * Scan microcode blocks first for version info + * and firmware check + */ - /* Scan microcode blocks first for version info if uploading */ - if (action == UCODE_UPLOAD) { /* Clear version block */ DRX_ATTR_MCRECORD(demod).aux_type = 0; DRX_ATTR_MCRECORD(demod).mc_dev_type = 0; @@ -991,6 +1021,9 @@ ctrl_u_code(struct drx_demod_instance *demod, for (i = 0; i < mc_nr_of_blks; i++) { struct drxu_code_block_hdr block_hdr; + if (mc_data - mc_data_init + + 3 * sizeof(u16) + sizeof(u32) > size) + goto eof; /* Process block header */ block_hdr.addr = u_code_read32(mc_data); mc_data += sizeof(u32); @@ -1002,9 +1035,15 @@ ctrl_u_code(struct drx_demod_instance *demod, mc_data += sizeof(u16); if (block_hdr.flags & 0x8) { + u8 *auxblk = ((void *)mc_data_init) + block_hdr.addr; + u16 auxtype; + + if (mc_data - mc_data_init + sizeof(u16) + + 2 * sizeof(u32) > size) + goto eof; + /* Aux block. Check type */ - u8 *auxblk = mc_info->mc_data + block_hdr.addr; - u16 auxtype = u_code_read16(auxblk); + auxtype = u_code_read16(auxblk); if (DRX_ISMCVERTYPE(auxtype)) { DRX_ATTR_MCRECORD(demod).aux_type = u_code_read16(auxblk); auxblk += sizeof(u16); @@ -1015,20 +1054,28 @@ ctrl_u_code(struct drx_demod_instance *demod, DRX_ATTR_MCRECORD(demod).mc_base_version = u_code_read32(auxblk); } } + if (mc_data - mc_data_init + + block_hdr.size * sizeof(u16) > size) + goto eof; /* Next block */ mc_data += block_hdr.size * sizeof(u16); } + /* Restore data pointer */ + mc_data = ((void *)mc_data_init) + 2 * sizeof(u16); + } + + if (action == UCODE_UPLOAD) { /* After scanning, validate the microcode. It is also valid if no validation control exists. */ rc = drx_ctrl(demod, DRX_CTRL_VALIDATE_UCODE, NULL); - if (rc != 0 && rc != -ENOTSUPP) - return rc; - - /* Restore data pointer */ - mc_data = mc_info->mc_data + 2 * sizeof(u16); + if (rc != 0 && rc != -ENOTSUPP) { + pr_err("Validate ucode not supported\n"); + goto release; + } + pr_info("Uploading firmware %s\n", mc_file); } /* Process microcode blocks */ @@ -1055,103 +1102,85 @@ ctrl_u_code(struct drx_demod_instance *demod, (block_hdr.CRC != u_code_compute_crc(mc_data, block_hdr.size))) ) { /* Wrong data ! */ - return -EINVAL; + rc = -EINVAL; + pr_err("firmware CRC is wrong\n"); + goto release; } + if (!block_hdr.size) + continue; + mc_block_nr_bytes = block_hdr.size * ((u16) sizeof(u16)); - if (block_hdr.size != 0) { - /* Perform the desired action */ - switch (action) { - /*================================================================*/ - case UCODE_UPLOAD: - { - /* Upload microcode */ - if (demod->my_access_funct-> - write_block_func(dev_addr, - (dr_xaddr_t) block_hdr. - addr, mc_block_nr_bytes, - mc_data, - 0x0000) != - 0) { - return -EIO; - } /* if */ - } - break; - - /*================================================================*/ - case UCODE_VERIFY: - { - int result = 0; - u8 mc_data_buffer - [DRX_UCODE_MAX_BUF_SIZE]; - u32 bytes_to_compare = 0; - u32 bytes_left_to_compare = 0; - u32 curr_addr = (dr_xaddr_t) 0; - u8 *curr_ptr = NULL; - - bytes_left_to_compare = mc_block_nr_bytes; - curr_addr = block_hdr.addr; - curr_ptr = mc_data; - - while (bytes_left_to_compare != 0) { - if (bytes_left_to_compare > - ((u32) - DRX_UCODE_MAX_BUF_SIZE)) { - bytes_to_compare = - ((u32) - DRX_UCODE_MAX_BUF_SIZE); - } else { - bytes_to_compare = - bytes_left_to_compare; - } - - if (demod->my_access_funct-> - read_block_func(dev_addr, - curr_addr, - (u16) - bytes_to_compare, - (u8 *) - mc_data_buffer, - 0x0000) != - 0) { - return -EIO; - } - - result = - drxbsp_hst_memcmp(curr_ptr, - mc_data_buffer, - bytes_to_compare); - - if (result != 0) - return -EIO; - - curr_addr += - ((dr_xaddr_t) - (bytes_to_compare / 2)); - curr_ptr = - &(curr_ptr[bytes_to_compare]); - bytes_left_to_compare -= - ((u32) bytes_to_compare); - } /* while( bytes_to_compare > DRX_UCODE_MAX_BUF_SIZE ) */ + /* Perform the desired action */ + switch (action) { + case UCODE_UPLOAD: + /* Upload microcode */ + if (demod->my_access_funct->write_block_func(dev_addr, + block_hdr.addr, + mc_block_nr_bytes, + mc_data, 0x0000)) { + pr_err("error writing firmware\n"); + goto release; + } + break; + case UCODE_VERIFY: { + int result = 0; + u8 mc_data_buffer[DRX_UCODE_MAX_BUF_SIZE]; + u32 bytes_to_comp = 0; + u32 bytes_left = mc_block_nr_bytes; + u32 curr_addr = block_hdr.addr; + u8 *curr_ptr = mc_data; + + while (bytes_left != 0) { + if (bytes_left > DRX_UCODE_MAX_BUF_SIZE) + bytes_to_comp = DRX_UCODE_MAX_BUF_SIZE; + else + bytes_to_comp = bytes_left; + + if (demod->my_access_funct-> + read_block_func(dev_addr, + curr_addr, + (u16)bytes_to_comp, + (u8 *)mc_data_buffer, + 0x0000)) { + pr_err("error reading firmware\n"); + goto release; } - break; - /*================================================================*/ - default: - return -EINVAL; - break; + result =drxbsp_hst_memcmp(curr_ptr, + mc_data_buffer, + bytes_to_comp); + + if (result) { + pr_err("error verifying firmware\n"); + return -EIO; + } - } /* switch ( action ) */ + curr_addr += ((dr_xaddr_t)(bytes_to_comp / 2)); + curr_ptr =&(curr_ptr[bytes_to_comp]); + bytes_left -=((u32) bytes_to_comp); + } + break; } + default: + return -EINVAL; + break; - /* if (block_hdr.size != 0 ) */ - /* Next block */ + } mc_data += mc_block_nr_bytes; - - } /* for( i = 0 ; ifirmware); + demod->firmware = NULL; + + return rc; } /*============================================================================*/ diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h index f5add1a..1696e0d 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h @@ -33,6 +33,8 @@ #include #include +#include +#include /* * This structure contains the I2C address, the device ID and a user_data pointer. @@ -1014,13 +1016,14 @@ STRUCTS /*============================================================================*/ /** -* \struct struct drxu_code_info * \brief Parameters for microcode upload and verfiy. -* -* Used by DRX_CTRL_LOAD_UCODE and DRX_CTRL_VERIFY_UCODE -*/ + * struct drxu_code_info Parameters for microcode upload and verfiy. + * + * @mc_file: microcode file name + * + * Used by DRX_CTRL_LOAD_UCODE and DRX_CTRL_VERIFY_UCODE + */ struct drxu_code_info { - u8 *mc_data; - /**< Pointer to microcode image. */ + char *mc_file; }; /** @@ -1929,8 +1932,7 @@ struct drx_reg_dump { */ struct drx_common_attr { /* Microcode (firmware) attributes */ - u8 *microcode; /**< Pointer to microcode image. */ - /**< Size of microcode image in bytes. */ + char *microcode_file; /**< microcode filename */ bool verify_microcode; /**< Use microcode verify or not. */ struct drx_mc_version_rec mcversion; @@ -2029,21 +2031,24 @@ struct drx_demod_instance; /** * \struct struct drx_demod_instance * \brief Top structure of demodulator instance. */ - struct drx_demod_instance { - /* type specific demodulator data */ - struct drx_demod_func *my_demod_funct; - /**< demodulator functions */ - struct drx_access_func *my_access_funct; - /**< data access protocol functions */ - struct tuner_instance *my_tuner; - /**< tuner instance,if NULL then baseband */ - struct i2c_device_addr *my_i2c_dev_addr; - /**< i2c address and device identifier */ - struct drx_common_attr *my_common_attr; - /**< common DRX attributes */ - void *my_ext_attr; /**< device specific attributes */ - /* generic demodulator data */ - }; +struct drx_demod_instance { + /* type specific demodulator data */ + struct drx_demod_func *my_demod_funct; + /**< demodulator functions */ + struct drx_access_func *my_access_funct; + /**< data access protocol functions */ + struct tuner_instance *my_tuner; + /**< tuner instance,if NULL then baseband */ + struct i2c_device_addr *my_i2c_dev_addr; + /**< i2c address and device identifier */ + struct drx_common_attr *my_common_attr; + /**< common DRX attributes */ + void *my_ext_attr; /**< device specific attributes */ + /* generic demodulator data */ + + struct i2c_adapter *i2c; + const struct firmware *firmware; +}; /*------------------------------------------------------------------------- MACROS diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index e21dd5a..b90e6c1 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -875,7 +875,7 @@ struct i2c_device_addr drxj_default_addr_g = { * \brief Default common attributes of a drxj demodulator instance. */ struct drx_common_attr drxj_default_comm_attr_g = { - (u8 *)NULL, /* ucode ptr */ + NULL, /* ucode file */ true, /* ucode verify switch */ {0}, /* version record */ @@ -20139,11 +20139,11 @@ int drxj_open(struct drx_demod_instance *demod) } /* Upload microcode */ - if (common_attr->microcode != NULL) { + if (common_attr->microcode_file != NULL) { /* Dirty trick to use common ucode upload & verify, pretend device is already open */ common_attr->is_opened = true; - ucode_info.mc_data = common_attr->microcode; + ucode_info.mc_file = common_attr->microcode_file; #ifdef DRXJ_SPLIT_UCODE_UPLOAD /* Upload microcode without audio part */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj_mc.h b/drivers/media/dvb-frontends/drx39xyj/drxj_mc.h deleted file mode 100644 index dc2af8f..0000000 --- a/drivers/media/dvb-frontends/drx39xyj/drxj_mc.h +++ /dev/null @@ -1,7829 +0,0 @@ -/* - Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - * Neither the name of Trident Microsystems nor Hauppauge Computer Works - nor the names of its contributors may be used to endorse or promote - products derived from this software without specific prior written - permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. -*/ - -/*----------------------------------------------------------------------------- -* DESCRIPTION: -* Contains firmware version: 1.0.8 -* -* USAGE: -* Include. -* -* NOTES: -*/ - -#ifndef __DRXJ_MC_MAIN_H__ -#define __DRXJ_MC_MAIN_H__ - -#define DRXJ_MC_MAIN ((u8 *)drxj_mc_main_g) - -const u8 drxj_mc_main_g[] = { - 0x48, 0x4c, 0x00, 0x06, 0x00, 0x00, 0xf3, 0x10, 0x00, 0x00, 0x00, 0x08, - 0x00, 0x00, 0x01, 0x07, - 0x00, 0x00, 0x1f, 0xf0, 0x00, 0x01, 0xdd, 0x81, 0x00, 0x40, 0x0a, 0x00, - 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Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - * Neither the name of Trident Microsystems nor Hauppauge Computer Works - nor the names of its contributors may be used to endorse or promote - products derived from this software without specific prior written - permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. -*/ - -/*----------------------------------------------------------------------------- -* DESCRIPTION: -* Contains firmware version: 1.0.8 -* -* USAGE: -* Include. -* -* NOTES: -----------------------------------------------------------------------------*/ - -#ifndef __DRXJ_MC_VSB_H__ -#define __DRXJ_MC_VSB_H__ - -#define DRXJ_MC_VSB ((u8 *)drxj_mc_vsb_g) - -const u8 drxj_mc_vsb_g[] = { - 0x48, 0x4c, 0x00, 0x03, 0x00, 0x00, 0x2b, 0x62, 0x00, 0x00, 0x00, 0x08, - 0x00, 0x00, 0x00, 0x82, - 0x00, 0x00, 0x15, 0x9e, 0x00, 0x01, 0x92, 0x3b, 0x2a, 0x02, 0xe4, 0xf8, - 0x7f, 0x90, 0xf0, 0xf8, - 0xf0, 0xa3, 0x02, 0x22, 0xa6, 0x15, 0x23, 0x7f, 0x71, 0x7e, 0x29, 0x12, - 0x90, 0x61, 0x19, 0x7b, - 0xf0, 0xef, 0xd0, 0xc0, 0xaf, 0xa2, 0xd1, 0x92, 0xaf, 0xc2, 0x28, 0x12, - 0x90, 0xb6, 0x19, 0x7b, - 0xfd, 0xe0, 0x4d, 0xef, 0x90, 0xff, 0xf6, 0x7f, 0xf0, 0xee, 0xef, 0xa3, - 0xa2, 0xf0, 0x92, 0xd1, - 0xd0, 0xaf, 0xe4, 0xd0, 0x7f, 0x90, 0xf0, 0xf8, 0xf0, 0xa3, 0xe4, 0x22, - 0x7f, 0x90, 0xf0, 0xf8, - 0xf0, 0xa3, 0x02, 0x22, 0x70, 0x09, 0x00, 0x22, 0x00, 0x00, 0x02, 0x00, - 0x00, 0x28, 0x7a, 0x90, - 0xe0, 0xfa, 0xa3, 0xfe, 0xff, 0xe0, 0x30, 0x7d, 0x94, 0x7c, 0x29, 0x12, - 0x90, 0xa5, 0xfc, 0x7a, - 0xfe, 0xe0, 0xe0, 0xa3, 0x7d, 0xff, 0x7c, 0x31, 0x12, 0x94, 0xa5, 0x29, - 0x7b, 0x90, 0xe0, 0x01, - 0x7e, 0xff, 0x7d, 0x00, 0x7c, 0x2e, 0x12, 0x94, 0xa5, 0x29, 0x7b, 0x90, - 0xe0, 0x02, 0x7e, 0xff, - 0x7d, 0x00, 0x7c, 0x22, 0x12, 0x94, 0xa5, 0x29, 0x7b, 0x90, 0xe0, 0x03, - 0x7e, 0xff, 0x7d, 0x00, - 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0x12, 0x22, 0x00, 0xb2, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x74, 0x38, - 0x90, 0xff, 0xf8, 0x7f, - 0xa3, 0xf0, 0x22, 0xf0, 0x90, 0xe4, 0xf8, 0x7f, 0xa3, 0xf0, 0x22, 0xf0, - 0x90, 0xe4, 0xf8, 0x7f, - 0xa3, 0xf0, 0x22, 0xf0, 0x00, 0x83, 0x1f, 0xfe, 0x00, 0x02, 0x00, 0x01, - 0xe8, 0x03, 0x10, 0x00, - 0x08, 0x00, 0x80, 0x00, 0x03, 0x94, 0x00, 0xd9, 0x00, 0x10, 0x00, 0x08, - 0x00, 0x00, 0x00, 0x00 -}; - -#endif /* __DRXJ_MC_VSB_H__ */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsbqam.h b/drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsbqam.h deleted file mode 100644 index 471660c..0000000 --- a/drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsbqam.h +++ /dev/null @@ -1,2824 +0,0 @@ -/* - Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - * Neither the name of Trident Microsystems nor Hauppauge Computer Works - nor the names of its contributors may be used to endorse or promote - products derived from this software without specific prior written - permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. -*/ - -/*----------------------------------------------------------------------------- -* DESCRIPTION: -* Contains firmware version: 1.0.8 -* -* USAGE: -* Include. -* -* NOTES: -* -----------------------------------------------------------------------------*/ - -#ifndef __DRXJ_MC_VSBQAM_H__ -#define __DRXJ_MC_VSBQAM_H__ - -#define DRXJ_MC_VSBQAM ((u8 *)drxj_mc_vsbqam_g) - -const u8 drxj_mc_vsbqam_g[] = { - 0x48, 0x4c, 0x00, 0x04, 0x00, 0x00, 0x56, 0xa0, 0x00, 0x00, 0x00, 0x08, - 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Split the first loop that verifies the firmware size into a separate routine, making the code more readable. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drx_driver.c | 215 ++++++++++++---------- 1 file changed, 122 insertions(+), 93 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c index 194be83..94768b1 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c @@ -933,6 +933,86 @@ static u16 u_code_compute_crc(u8 *block_data, u16 nr_words) /*============================================================================*/ + +static int check_firmware(struct drx_demod_instance *demod, u8 *mc_data, + unsigned size) +{ + struct drxu_code_block_hdr block_hdr; + int i; + unsigned count = 2 * sizeof(u16); + u32 mc_dev_type, mc_version, mc_base_version; + u16 mc_nr_of_blks = u_code_read16(mc_data + sizeof(u16)); + + /* + * Scan microcode blocks first for version info + * and firmware check + */ + + /* Clear version block */ + DRX_ATTR_MCRECORD(demod).aux_type = 0; + DRX_ATTR_MCRECORD(demod).mc_dev_type = 0; + DRX_ATTR_MCRECORD(demod).mc_version = 0; + DRX_ATTR_MCRECORD(demod).mc_base_version = 0; + + for (i = 0; i < mc_nr_of_blks; i++) { + if (count + 3 * sizeof(u16) + sizeof(u32) > size) + goto eof; + + /* Process block header */ + block_hdr.addr = u_code_read32(mc_data + count); + count += sizeof(u32); + block_hdr.size = u_code_read16(mc_data + count); + count += sizeof(u16); + block_hdr.flags = u_code_read16(mc_data + count); + count += sizeof(u16); + block_hdr.CRC = u_code_read16(mc_data + count); + count += sizeof(u16); + + pr_debug("%u: addr %u, size %u, flags 0x%04x, CRC 0x%04x\n", + count, block_hdr.addr, block_hdr.size, block_hdr.flags, + block_hdr.CRC); + + if (block_hdr.flags & 0x8) { + u8 *auxblk = ((void *)mc_data) + block_hdr.addr; + u16 auxtype; + + if (block_hdr.addr + sizeof(u16) > size) + goto eof; + + auxtype = u_code_read16(auxblk); + + /* Aux block. Check type */ + if (DRX_ISMCVERTYPE(auxtype)) { + if (block_hdr.addr + 2 * sizeof(u16) + 2 * sizeof (u32) > size) + goto eof; + + auxblk += sizeof(u16); + mc_dev_type = u_code_read32(auxblk); + auxblk += sizeof(u32); + mc_version = u_code_read32(auxblk); + auxblk += sizeof(u32); + mc_base_version = u_code_read32(auxblk); + + DRX_ATTR_MCRECORD(demod).aux_type = auxtype; + DRX_ATTR_MCRECORD(demod).mc_dev_type = mc_dev_type; + DRX_ATTR_MCRECORD(demod).mc_version = mc_version; + DRX_ATTR_MCRECORD(demod).mc_base_version = mc_base_version; + + pr_info("Firmware dev %x, ver %x, base ver %x\n", + mc_dev_type, mc_version, mc_base_version); + + } + } else if (count + block_hdr.size * sizeof(u16) > size) + goto eof; + + count += block_hdr.size * sizeof(u16); + } + return 0; +eof: + pr_err("Firmware is truncated at pos %u/%u\n", count, size); + return -EINVAL; +} + /** * \brief Handle microcode upload or verify. * \param dev_addr: Address of device. @@ -962,24 +1042,15 @@ ctrl_u_code(struct drx_demod_instance *demod, u16 mc_magic_word = 0; const u8 *mc_data_init = NULL; u8 *mc_data = NULL; + unsigned size; char *mc_file = mc_info->mc_file; /* Check arguments */ if (!mc_info || !mc_file) return -EINVAL; - if (demod->firmware) { - mc_data_init = demod->firmware->data; - mc_data = (void *)mc_data_init; - - /* Check data */ - mc_magic_word = u_code_read16(mc_data); - mc_data += sizeof(u16); - mc_nr_of_blks = u_code_read16(mc_data); - mc_data += sizeof(u16); - } else { + if (!demod->firmware) { const struct firmware *fw = NULL; - unsigned size = 0; rc = request_firmware(&fw, mc_file, demod->i2c->dev.parent); if (rc < 0) { @@ -987,95 +1058,49 @@ ctrl_u_code(struct drx_demod_instance *demod, return -ENOENT; } demod->firmware = fw; - mc_data_init = demod->firmware->data; - size = demod->firmware->size; - - pr_info("Firmware %s, size %u\n", mc_file, size); - - mc_data = (void *)mc_data_init; - /* Check data */ - if (mc_data - mc_data_init + 2 * sizeof(u16) > size) - goto eof; - mc_magic_word = u_code_read16(mc_data); - mc_data += sizeof(u16); - mc_nr_of_blks = u_code_read16(mc_data); - mc_data += sizeof(u16); - - if ((mc_magic_word != DRX_UCODE_MAGIC_WORD) || (mc_nr_of_blks == 0)) { - rc = -EINVAL; /* wrong endianess or wrong data ? */ - pr_err("Firmware magic word doesn't match\n"); + if (demod->firmware->size < 2 * sizeof(u16)) { + rc = -EINVAL; + pr_err("Firmware is too short!\n"); goto release; } - /* - * Scan microcode blocks first for version info - * and firmware check - */ - - /* Clear version block */ - DRX_ATTR_MCRECORD(demod).aux_type = 0; - DRX_ATTR_MCRECORD(demod).mc_dev_type = 0; - DRX_ATTR_MCRECORD(demod).mc_version = 0; - DRX_ATTR_MCRECORD(demod).mc_base_version = 0; - for (i = 0; i < mc_nr_of_blks; i++) { - struct drxu_code_block_hdr block_hdr; - - if (mc_data - mc_data_init + - 3 * sizeof(u16) + sizeof(u32) > size) - goto eof; - /* Process block header */ - block_hdr.addr = u_code_read32(mc_data); - mc_data += sizeof(u32); - block_hdr.size = u_code_read16(mc_data); - mc_data += sizeof(u16); - block_hdr.flags = u_code_read16(mc_data); - mc_data += sizeof(u16); - block_hdr.CRC = u_code_read16(mc_data); - mc_data += sizeof(u16); - - if (block_hdr.flags & 0x8) { - u8 *auxblk = ((void *)mc_data_init) + block_hdr.addr; - u16 auxtype; - - if (mc_data - mc_data_init + sizeof(u16) + - 2 * sizeof(u32) > size) - goto eof; + pr_info("Firmware %s, size %zu\n", + mc_file, demod->firmware->size); + } - /* Aux block. Check type */ - auxtype = u_code_read16(auxblk); - if (DRX_ISMCVERTYPE(auxtype)) { - DRX_ATTR_MCRECORD(demod).aux_type = u_code_read16(auxblk); - auxblk += sizeof(u16); - DRX_ATTR_MCRECORD(demod).mc_dev_type = u_code_read32(auxblk); - auxblk += sizeof(u32); - DRX_ATTR_MCRECORD(demod).mc_version = u_code_read32(auxblk); - auxblk += sizeof(u32); - DRX_ATTR_MCRECORD(demod).mc_base_version = u_code_read32(auxblk); - } - } - if (mc_data - mc_data_init + - block_hdr.size * sizeof(u16) > size) - goto eof; + mc_data_init = demod->firmware->data; + size = demod->firmware->size; - /* Next block */ - mc_data += block_hdr.size * sizeof(u16); - } + mc_data = (void *)mc_data_init; + /* Check data */ + mc_magic_word = u_code_read16(mc_data); + mc_data += sizeof(u16); + mc_nr_of_blks = u_code_read16(mc_data); + mc_data += sizeof(u16); - /* Restore data pointer */ - mc_data = ((void *)mc_data_init) + 2 * sizeof(u16); + if ((mc_magic_word != DRX_UCODE_MAGIC_WORD) || (mc_nr_of_blks == 0)) { + rc = -EINVAL; + pr_err("Firmware magic word doesn't match\n"); + goto release; } if (action == UCODE_UPLOAD) { + rc = check_firmware(demod, (u8 *)mc_data_init, size); + if (rc) + goto release; + /* After scanning, validate the microcode. It is also valid if no validation control exists. */ rc = drx_ctrl(demod, DRX_CTRL_VALIDATE_UCODE, NULL); if (rc != 0 && rc != -ENOTSUPP) { pr_err("Validate ucode not supported\n"); - goto release; + return rc; } pr_info("Uploading firmware %s\n", mc_file); + } else if (action == UCODE_VERIFY) { + pr_info("Verifying if firmware upload was ok.\n"); } /* Process microcode blocks */ @@ -1093,6 +1118,10 @@ ctrl_u_code(struct drx_demod_instance *demod, block_hdr.CRC = u_code_read16(mc_data); mc_data += sizeof(u16); + pr_debug("%u: addr %u, size %u, flags 0x%04x, CRC 0x%04x\n", + (unsigned)(mc_data - mc_data_init), block_hdr.addr, + block_hdr.size, block_hdr.flags, block_hdr.CRC); + /* Check block header on: - data larger than 64Kb - if CRC enabled check CRC @@ -1114,17 +1143,18 @@ ctrl_u_code(struct drx_demod_instance *demod, /* Perform the desired action */ switch (action) { - case UCODE_UPLOAD: - /* Upload microcode */ + case UCODE_UPLOAD: /* Upload microcode */ if (demod->my_access_funct->write_block_func(dev_addr, block_hdr.addr, mc_block_nr_bytes, mc_data, 0x0000)) { - pr_err("error writing firmware\n"); + rc = -EIO; + pr_err("error writing firmware at pos %u\n", + (unsigned)(mc_data - mc_data_init)); goto release; } break; - case UCODE_VERIFY: { + case UCODE_VERIFY: { /* Verify uploaded microcode */ int result = 0; u8 mc_data_buffer[DRX_UCODE_MAX_BUF_SIZE]; u32 bytes_to_comp = 0; @@ -1144,8 +1174,9 @@ ctrl_u_code(struct drx_demod_instance *demod, (u16)bytes_to_comp, (u8 *)mc_data_buffer, 0x0000)) { - pr_err("error reading firmware\n"); - goto release; + pr_err("error reading firmware at pos %u\n", + (unsigned)(mc_data - mc_data_init)); + return -EIO; } result =drxbsp_hst_memcmp(curr_ptr, @@ -1153,7 +1184,8 @@ ctrl_u_code(struct drx_demod_instance *demod, bytes_to_comp); if (result) { - pr_err("error verifying firmware\n"); + pr_err("error verifying firmware at pos %u\n", + (unsigned)(mc_data - mc_data_init)); return -EIO; } @@ -1172,10 +1204,7 @@ ctrl_u_code(struct drx_demod_instance *demod, } return 0; -eof: - rc = -ENOENT; - pr_err("Firmware file %s is truncated at pos %lu\n", - mc_file, (unsigned long)(mc_data - mc_data_init)); + release: release_firmware(demod->firmware); demod->firmware = NULL; -- cgit v1.1 From 959505bd24fde7ac50fb4854d64fe53171320eaf Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sun, 19 Jan 2014 07:15:11 -0300 Subject: [media] em28xx: add support for PCTV 80e remote controller This stick uses the same RC-5 remote controll found on other PCTV devices. So, just use the existing keymap. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/em28xx/em28xx-cards.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/media/usb/em28xx/em28xx-cards.c b/drivers/media/usb/em28xx/em28xx-cards.c index ed0edfd..138659b 100644 --- a/drivers/media/usb/em28xx/em28xx-cards.c +++ b/drivers/media/usb/em28xx/em28xx-cards.c @@ -2145,6 +2145,7 @@ struct em28xx_board em28xx_boards[] = { .has_dvb = 1, .dvb_gpio = em2874_pctv_80e_digital, .decoder = EM28XX_NODECODER, + .ir_codes = RC_MAP_PINNACLE_PCTV_HD, }, /* 1ae7:9003/9004 SpeedLink Vicious And Devine Laplace webcam * Empia EM2765 + OmniVision OV2640 */ -- cgit v1.1 From e2b8e8d2410a7121a1fe7b0bebeab9baa82541b5 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sun, 19 Jan 2014 09:50:18 -0300 Subject: [media] drx-j: remove unused code from drx_driver.c There are several drx-j code there that are never used, as they don't even fit into Linux DVB subystem model. Remove them, in order to simplify the code. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drx_driver.c | 789 +--------------------- drivers/media/dvb-frontends/drx39xyj/drx_driver.h | 4 - 2 files changed, 1 insertion(+), 792 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c index 94768b1..c144fb7 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c @@ -135,719 +135,6 @@ FUNCTIONS /*============================================================================*/ /*============================================================================*/ -/*== Channel Scan Functions ==================================================*/ -/*============================================================================*/ -/*============================================================================*/ - -#ifndef DRX_EXCLUDE_SCAN - -/* Prototype of default scanning function */ -static int -scan_function_default(void *scan_context, - enum drx_scan_command scan_command, - struct drx_channel *scan_channel, bool *get_next_channel); - -/** -* \brief Get pointer to scanning function. -* \param demod: Pointer to demodulator instance. -* \return drx_scan_func_t. -*/ -static drx_scan_func_t get_scan_function(struct drx_demod_instance *demod) -{ - struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL); - drx_scan_func_t scan_func = (drx_scan_func_t) (NULL); - - /* get scan function from common attributes */ - common_attr = (struct drx_common_attr *) demod->my_common_attr; - scan_func = common_attr->scan_function; - - if (scan_func != NULL) { - /* return device-specific scan function if it's not NULL */ - return scan_func; - } - /* otherwise return default scan function in core driver */ - return &scan_function_default; -} - -/** -* \brief Get Context pointer. -* \param demod: Pointer to demodulator instance. -* \param scan_context: Context Pointer. -* \return drx_scan_func_t. -*/ -static void *get_scan_context(struct drx_demod_instance *demod, void *scan_context) -{ - struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL); - - /* get scan function from common attributes */ - common_attr = (struct drx_common_attr *) demod->my_common_attr; - scan_context = common_attr->scan_context; - - if (scan_context == NULL) - scan_context = (void *)demod; - - return scan_context; -} - -/** -* \brief Wait for lock while scanning. -* \param demod: Pointer to demodulator instance. -* \param lock_stat: Pointer to bool indicating if end result is lock or not. -* \return int. -* \retval 0: Success -* \retval -EIO: I2C failure or bsp function failure. -* -* Wait until timeout, desired lock or NEVER_LOCK. -* Assume: -* - lock function returns : at least DRX_NOT_LOCKED and a lock state -* higher than DRX_NOT_LOCKED. -* - BSP has a clock function to retrieve a millisecond ticker value. -* - BSP has a sleep function to enable sleep of n millisecond. -* -* In case DRX_NEVER_LOCK is returned the poll-wait will be aborted. -* -*/ -static int scan_wait_for_lock(struct drx_demod_instance *demod, bool *is_locked) -{ - bool done_waiting = false; - enum drx_lock_status lock_state = DRX_NOT_LOCKED; - enum drx_lock_status desired_lock_state = DRX_NOT_LOCKED; - u32 timeout_value = 0; - u32 start_time_lock_stage = 0; - u32 current_time = 0; - u32 timer_value = 0; - - *is_locked = false; - timeout_value = (u32) demod->my_common_attr->scan_demod_lock_timeout; - desired_lock_state = demod->my_common_attr->scan_desired_lock; - start_time_lock_stage = drxbsp_hst_clock(); - - /* Start polling loop, checking for lock & timeout */ - while (!done_waiting) { - if (drx_ctrl(demod, DRX_CTRL_LOCK_STATUS, &lock_state)) - return -EIO; - - current_time = drxbsp_hst_clock(); - - timer_value = current_time - start_time_lock_stage; - if (lock_state >= desired_lock_state) { - *is_locked = true; - done_waiting = true; - } else if (lock_state == DRX_NEVER_LOCK) { - done_waiting = true; - } else if (timer_value > timeout_value) { - /* lock_state == DRX_NOT_LOCKED and timeout */ - done_waiting = true; - } else { - if (drxbsp_hst_sleep(10) != 0) - return -EIO; - } - } - - return 0; -} - -/*============================================================================*/ - -/** -* \brief Determine next frequency to scan. -* \param demod: Pointer to demodulator instance. -* \param skip : Minimum frequency step to take. -* \return int. -* \retval 0: Succes. -* \retval -EINVAL: Invalid frequency plan. -* -* Helper function for ctrl_scan_next() function. -* Compute next frequency & index in frequency plan. -* Check if scan is ready. -* -*/ -static int -scan_prepare_next_scan(struct drx_demod_instance *demod, s32 skip) -{ - struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL); - u16 table_index = 0; - u16 frequency_plan_size = 0; - struct drx_frequency_plan *frequency_plan = (struct drx_frequency_plan *) (NULL); - s32 next_frequency = 0; - s32 tuner_min_frequency = 0; - s32 tuner_max_frequency = 0; - - common_attr = (struct drx_common_attr *) demod->my_common_attr; - table_index = common_attr->scan_freq_plan_index; - frequency_plan = common_attr->scan_param->frequency_plan; - next_frequency = common_attr->scan_next_frequency; - tuner_min_frequency = common_attr->tuner_min_freq_rf; - tuner_max_frequency = common_attr->tuner_max_freq_rf; - - do { - /* Search next frequency to scan */ - - /* always take at least one step */ - (common_attr->scan_channels_scanned)++; - next_frequency += frequency_plan[table_index].step; - skip -= frequency_plan[table_index].step; - - /* and then as many steps necessary to exceed 'skip' - without exceeding end of the band */ - while ((skip > 0) && - (next_frequency <= frequency_plan[table_index].last)) { - (common_attr->scan_channels_scanned)++; - next_frequency += frequency_plan[table_index].step; - skip -= frequency_plan[table_index].step; - } - /* reset skip, in case we move to the next band later */ - skip = 0; - - if (next_frequency > frequency_plan[table_index].last) { - /* reached end of this band */ - table_index++; - frequency_plan_size = - common_attr->scan_param->frequency_plan_size; - if (table_index >= frequency_plan_size) { - /* reached end of frequency plan */ - common_attr->scan_ready = true; - } else { - next_frequency = frequency_plan[table_index].first; - } - } - if (next_frequency > (tuner_max_frequency)) { - /* reached end of tuner range */ - common_attr->scan_ready = true; - } - } while ((next_frequency < tuner_min_frequency) && - (!common_attr->scan_ready)); - - /* Store new values */ - common_attr->scan_freq_plan_index = table_index; - common_attr->scan_next_frequency = next_frequency; - - return 0; -} - -/*============================================================================*/ - -/** -* \brief Default DTV scanning function. -* -* \param demod: Pointer to demodulator instance. -* \param scan_command: Scanning command: INIT, NEXT or STOP. -* \param scan_channel: Channel to check: frequency and bandwidth, others AUTO -* \param get_next_channel: Return true if next frequency is desired at next call -* -* \return int. -* \retval 0: Channel found, DRX_CTRL_GET_CHANNEL can be used -* to retrieve channel parameters. -* \retval -EBUSY: Channel not found (yet). -* \retval -EIO: Something went wrong. -* -* scan_channel and get_next_channel will be NULL for INIT and STOP. -*/ -static int -scan_function_default(void *scan_context, - enum drx_scan_command scan_command, - struct drx_channel *scan_channel, bool *get_next_channel) -{ - struct drx_demod_instance *demod = scan_context; - int status; - bool is_locked = false; - - /* just return OK if not doing "scan next" */ - if (scan_command != DRX_SCAN_COMMAND_NEXT) - return 0; - - *get_next_channel = false; - - status = drx_ctrl(demod, DRX_CTRL_SET_CHANNEL, scan_channel); - if (status) - return status; - - status = scan_wait_for_lock(demod, &is_locked); - if (status) - return status; - - /* done with this channel, move to next one */ - *get_next_channel = true; - - if (!is_locked) - return -EBUSY; /* no channel found */ - - /* channel found */ - return 0; -} - -/*============================================================================*/ - -/** -* \brief Initialize for channel scan. -* \param demod: Pointer to demodulator instance. -* \param scan_param: Pointer to scan parameters. -* \return int. -* \retval 0: Initialized for scan. -* \retval -EIO: No overlap between frequency plan and tuner -* range. -* \retval -EINVAL: Wrong parameters. -* -* This function should be called before starting a complete channel scan. -* It will prepare everything for a complete channel scan. -* After calling this function the DRX_CTRL_SCAN_NEXT control function can be -* used to perform the actual scanning. Scanning will start at the first -* center frequency of the frequency plan that is within the tuner range. -* -*/ -static int -ctrl_scan_init(struct drx_demod_instance *demod, struct drx_scan_param *scan_param) -{ - struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL); - s32 max_tuner_freq = 0; - s32 min_tuner_freq = 0; - u16 nr_channels_in_plan = 0; - u16 i = 0; - void *scan_context = NULL; - - common_attr = (struct drx_common_attr *) demod->my_common_attr; - common_attr->scan_active = true; - - /* invalidate a previous SCAN_INIT */ - common_attr->scan_param = NULL; - common_attr->scan_next_frequency = 0; - - /* Check parameters */ - if (((demod->my_tuner == NULL) && - (scan_param->num_tries != 1)) || - (scan_param == NULL) || - (scan_param->num_tries == 0) || - (scan_param->frequency_plan == NULL) || - (scan_param->frequency_plan_size == 0) - ) { - common_attr->scan_active = false; - return -EINVAL; - } - - /* Check frequency plan contents */ - max_tuner_freq = common_attr->tuner_max_freq_rf; - min_tuner_freq = common_attr->tuner_min_freq_rf; - for (i = 0; i < (scan_param->frequency_plan_size); i++) { - s32 width = 0; - s32 step = scan_param->frequency_plan[i].step; - s32 first_freq = scan_param->frequency_plan[i].first; - s32 last_freq = scan_param->frequency_plan[i].last; - s32 min_freq = 0; - s32 max_freq = 0; - - if (step <= 0) { - /* Step must be positive and non-zero */ - common_attr->scan_active = false; - return -EINVAL; - } - - if (first_freq > last_freq) { - /* First center frequency is higher than last center frequency */ - common_attr->scan_active = false; - return -EINVAL; - } - - width = last_freq - first_freq; - - if ((width % step) != 0) { - /* Difference between last and first center frequency is not - an integer number of steps */ - common_attr->scan_active = false; - return -EINVAL; - } - - /* Check if frequency plan entry intersects with tuner range */ - if (last_freq >= min_tuner_freq) { - if (first_freq <= max_tuner_freq) { - if (first_freq >= min_tuner_freq) { - min_freq = first_freq; - } else { - s32 n = 0; - - n = (min_tuner_freq - first_freq) / step; - if (((min_tuner_freq - first_freq) % step) != 0) - n++; - min_freq = first_freq + n * step; - } - - if (last_freq <= max_tuner_freq) { - max_freq = last_freq; - } else { - s32 n = 0; - - n = (last_freq - max_tuner_freq) / step; - if (((last_freq - max_tuner_freq) % step) != 0) - n++; - max_freq = last_freq - n * step; - } - } - } - - /* Keep track of total number of channels within tuner range - in this frequency plan. */ - if ((min_freq != 0) && (max_freq != 0)) { - nr_channels_in_plan += - (u16) (((max_freq - min_freq) / step) + 1); - - /* Determine first frequency (within tuner range) to scan */ - if (common_attr->scan_next_frequency == 0) { - common_attr->scan_next_frequency = min_freq; - common_attr->scan_freq_plan_index = i; - } - } - - } /* for ( ... ) */ - - if (nr_channels_in_plan == 0) { - /* Tuner range and frequency plan ranges do not overlap */ - common_attr->scan_active = false; - return -EIO; - } - - /* Store parameters */ - common_attr->scan_ready = false; - common_attr->scan_max_channels = nr_channels_in_plan; - common_attr->scan_channels_scanned = 0; - common_attr->scan_param = scan_param; /* SCAN_NEXT is now allowed */ - - scan_context = get_scan_context(demod, scan_context); - - /* - * FIXME: Should we really ignore the result of the scan function? - */ - (*(get_scan_function(demod)))(scan_context, DRX_SCAN_COMMAND_INIT, NULL, NULL); - - common_attr->scan_active = false; - - return 0; -} - -/*============================================================================*/ - -/** -* \brief Stop scanning. -* \param demod: Pointer to demodulator instance. -* \return int. -* \retval 0: Scan stopped. -* \retval -EIO: Something went wrong. -* \retval -EINVAL: Wrong parameters. -*/ -static int ctrl_scan_stop(struct drx_demod_instance *demod) -{ - int status = -EIO; - struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL); - void *scan_context = NULL; - - common_attr = (struct drx_common_attr *) demod->my_common_attr; - common_attr->scan_active = true; - - if ((common_attr->scan_param == NULL) || - (common_attr->scan_max_channels == 0)) { - /* Scan was not running, just return OK */ - common_attr->scan_active = false; - return 0; - } - - /* Call default or device-specific scanning stop function */ - scan_context = get_scan_context(demod, scan_context); - - status = (*(get_scan_function(demod))) - (scan_context, DRX_SCAN_COMMAND_STOP, NULL, NULL); - - /* All done, invalidate scan-init */ - common_attr->scan_param = NULL; - common_attr->scan_max_channels = 0; - common_attr->scan_active = false; - - return status; -} - -/*============================================================================*/ - -/** -* \brief Scan for next channel. -* \param demod: Pointer to demodulator instance. -* \param scan_progress: Pointer to scan progress. -* \return int. -* \retval 0: Channel found, DRX_CTRL_GET_CHANNEL can be used -* to retrieve channel parameters. -* \retval -EBUSY: Tried part of the channels, as specified in -* num_tries field of scan parameters. At least one -* more call to DRX_CTRL_SCAN_NEXT is needed to -* complete scanning. -* \retval -ERANGE: Reached end of scan range. -* \retval -EIO: Something went wrong. -* \retval -EINVAL: Wrong parameters. The scan_progress may be NULL. -* -* Progress indication will run from 0 upto DRX_SCAN_MAX_PROGRESS during scan. -* -*/ -static int ctrl_scan_next(struct drx_demod_instance *demod, u16 *scan_progress) -{ - struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL); - bool *scan_ready = (bool *)(NULL); - u16 max_progress = DRX_SCAN_MAX_PROGRESS; - u32 num_tries = 0; - u32 i = 0; - - common_attr = (struct drx_common_attr *) demod->my_common_attr; - - /* Check scan parameters */ - if (scan_progress == NULL) { - common_attr->scan_active = false; - return -EINVAL; - } - - *scan_progress = 0; - common_attr->scan_active = true; - if ((common_attr->scan_param == NULL) || - (common_attr->scan_max_channels == 0)) { - /* ctrl_scan_init() was not called succesfully before ctrl_scan_next() */ - common_attr->scan_active = false; - return -EIO; - } - - *scan_progress = (u16) (((common_attr->scan_channels_scanned) * - ((u32) (max_progress))) / - (common_attr->scan_max_channels)); - - /* Scan */ - num_tries = common_attr->scan_param->num_tries; - scan_ready = &(common_attr->scan_ready); - - for (i = 0; ((i < num_tries) && (!(*scan_ready))); i++) { - struct drx_channel scan_channel = { 0 }; - int status = -EIO; - struct drx_frequency_plan *freq_plan = (struct drx_frequency_plan *) (NULL); - bool next_channel = false; - void *scan_context = NULL; - - /* Next channel to scan */ - freq_plan = - &(common_attr->scan_param-> - frequency_plan[common_attr->scan_freq_plan_index]); - scan_channel.frequency = common_attr->scan_next_frequency; - scan_channel.bandwidth = freq_plan->bandwidth; - scan_channel.mirror = DRX_MIRROR_AUTO; - scan_channel.constellation = DRX_CONSTELLATION_AUTO; - scan_channel.hierarchy = DRX_HIERARCHY_AUTO; - scan_channel.priority = DRX_PRIORITY_HIGH; - scan_channel.coderate = DRX_CODERATE_AUTO; - scan_channel.guard = DRX_GUARD_AUTO; - scan_channel.fftmode = DRX_FFTMODE_AUTO; - scan_channel.classification = DRX_CLASSIFICATION_AUTO; - scan_channel.symbolrate = 0; - scan_channel.interleavemode = DRX_INTERLEAVEMODE_AUTO; - scan_channel.ldpc = DRX_LDPC_AUTO; - scan_channel.carrier = DRX_CARRIER_AUTO; - scan_channel.framemode = DRX_FRAMEMODE_AUTO; - scan_channel.pilot = DRX_PILOT_AUTO; - - /* Call default or device-specific scanning function */ - scan_context = get_scan_context(demod, scan_context); - - status = (*(get_scan_function(demod))) - (scan_context, DRX_SCAN_COMMAND_NEXT, &scan_channel, - &next_channel); - - /* Proceed to next channel if requested */ - if (next_channel) { - int next_status = -EIO; - s32 skip = 0; - - if (status == 0) { - /* a channel was found, so skip some frequency steps */ - skip = common_attr->scan_param->skip; - } - next_status = scan_prepare_next_scan(demod, skip); - - /* keep track of progress */ - *scan_progress = - (u16) (((common_attr->scan_channels_scanned) * - ((u32) (max_progress))) / - (common_attr->scan_max_channels)); - - if (next_status != 0) { - common_attr->scan_active = false; - return next_status; - } - } - if (status != -EBUSY) { - /* channel found or error */ - common_attr->scan_active = false; - return status; - } - } /* for ( i = 0; i < ( ... num_tries); i++) */ - - if ((*scan_ready)) { - /* End of scan reached: call stop-scan, ignore any error */ - ctrl_scan_stop(demod); - common_attr->scan_active = false; - return -ERANGE; - } - - common_attr->scan_active = false; - - return -EBUSY; -} - -#endif /* #ifndef DRX_EXCLUDE_SCAN */ - -/*============================================================================*/ - -/** -* \brief Program tuner. -* \param demod: Pointer to demodulator instance. -* \param tunerChannel: Pointer to tuning parameters. -* \return int. -* \retval 0: Tuner programmed successfully. -* \retval -EIO: Something went wrong. -* \retval -EINVAL: Wrong parameters. -* -* tunerChannel passes parameters to program the tuner, -* but also returns the actual RF and IF frequency from the tuner. -* -*/ -static int -ctrl_program_tuner(struct drx_demod_instance *demod, struct drx_channel *channel) -{ - struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL); - enum drx_standard standard = DRX_STANDARD_UNKNOWN; - u32 tuner_mode = 0; - int status = -EIO; - s32 if_frequency = 0; - bool tuner_slow_mode = false; - - /* can't tune without a tuner */ - if (demod->my_tuner == NULL) - return -EINVAL; - - common_attr = demod->my_common_attr; - - /* select analog or digital tuner mode based on current standard */ - if (drx_ctrl(demod, DRX_CTRL_GET_STANDARD, &standard)) - return -EIO; - - if (DRX_ISATVSTD(standard)) - tuner_mode |= TUNER_MODE_ANALOG; - else - - tuner_mode |= TUNER_MODE_DIGITAL; /* also for unknown standard */ - - /* select tuner bandwidth */ - switch (channel->bandwidth) { - case DRX_BANDWIDTH_6MHZ: - tuner_mode |= TUNER_MODE_6MHZ; - break; - case DRX_BANDWIDTH_7MHZ: - tuner_mode |= TUNER_MODE_7MHZ; - break; - case DRX_BANDWIDTH_8MHZ: - tuner_mode |= TUNER_MODE_8MHZ; - break; - default: /* note: also for unknown bandwidth */ - return -EINVAL; - } - - tuner_slow_mode = DRX_ATTR_TUNERSLOWMODE(demod); - - /* select fast (switch) or slow (lock) tuner mode */ - if (tuner_slow_mode) - tuner_mode |= TUNER_MODE_LOCK; - else - tuner_mode |= TUNER_MODE_SWITCH; - - if (common_attr->tuner_port_nr == 1) { - bool bridge_closed = true; - int status_bridge = -EIO; - - status_bridge = drx_ctrl(demod, DRX_CTRL_I2C_BRIDGE, - &bridge_closed); - if (status_bridge) - return status_bridge; - } - - status = drxbsp_tuner_set_frequency(demod->my_tuner, - tuner_mode, channel->frequency); - - /* attempt restoring bridge before checking status of set_frequency */ - if (common_attr->tuner_port_nr == 1) { - bool bridge_closed = false; - int status_bridge = -EIO; - - status_bridge = - drx_ctrl(demod, DRX_CTRL_I2C_BRIDGE, &bridge_closed); - if (status_bridge) - return status_bridge; - } - - /* now check status of drxbsp_tuner_set_frequency */ - if (status) - return status; - - /* get actual RF and IF frequencies from tuner */ - status = drxbsp_tuner_get_frequency(demod->my_tuner, - tuner_mode, - &(channel->frequency), - &(if_frequency)); - if (status) - return status; - - /* update common attributes with information available from this function; - TODO: check if this is required and safe */ - DRX_ATTR_INTERMEDIATEFREQ(demod) = if_frequency; - - return 0; -} - -/*============================================================================*/ - -/** -* \brief function to do a register dump. -* \param demod: Pointer to demodulator instance. -* \param registers: Registers to dump. -* \return int. -* \retval 0: Dump executed successfully. -* \retval -EIO: Something went wrong. -* \retval -EINVAL: Wrong parameters. -* -*/ -static int ctrl_dump_registers(struct drx_demod_instance *demod, - struct drx_reg_dump *registers) -{ - u16 i = 0; - - if (registers == NULL) - return -EINVAL; /* registers not supplied */ - - /* start dumping registers */ - while (registers[i].address) { - int status = -EIO; - u16 value = 0; - u32 data = 0; - - status = demod->my_access_funct->read_reg16func(demod->my_i2c_dev_addr, - registers[i].address, - &value, 0); - - data = (u32) value; - - /* - * On error: no breakouts; - * depending on device ID, some HW blocks might not be available - */ - if (status) - data |= ((u32) status) << 16; - registers[i].data = data; - i++; - } - - /* all done, all OK (any errors are saved inside data) */ - return 0; -} - -/*============================================================================*/ -/*============================================================================*/ /*===Microcode related functions==============================================*/ /*============================================================================*/ /*============================================================================*/ @@ -1281,39 +568,6 @@ ctrl_version(struct drx_demod_instance *demod, struct drx_version_list **version /*============================================================================*/ /** -* \brief This function is obsolete. -* \param demods: Don't care, parameter is ignored. -* \return int Return status. -* \retval 0: Initialization completed. -* -* This function is obsolete, prototype available for backward compatability. -* -*/ - -int drx_init(struct drx_demod_instance *demods[]) -{ - return 0; -} - -/*============================================================================*/ - -/** -* \brief This function is obsolete. -* \return int Return status. -* \retval 0: Terminated driver successful. -* -* This function is obsolete, prototype available for backward compatability. -* -*/ - -int drx_term(void) -{ - return 0; -} - -/*============================================================================*/ - -/** * \brief Open a demodulator instance. * \param demod: A pointer to a demodulator instance. * \return int Return status. @@ -1469,50 +723,9 @@ drx_ctrl(struct drx_demod_instance *demod, u32 ctrl, void *ctrl_data) } break; -#ifndef DRX_EXCLUDE_SCAN - /*===================================================================*/ - case DRX_CTRL_SCAN_INIT: - { - return ctrl_scan_init(demod, - (struct drx_scan_param *) ctrl_data); - } - break; - - /*===================================================================*/ - case DRX_CTRL_SCAN_NEXT: - { - return ctrl_scan_next(demod, (u16 *)ctrl_data); - } - break; - - /*===================================================================*/ - case DRX_CTRL_SCAN_STOP: - { - return ctrl_scan_stop(demod); - } - break; -#endif /* #ifndef DRX_EXCLUDE_SCAN */ - - /*===================================================================*/ - case DRX_CTRL_PROGRAM_TUNER: - { - return ctrl_program_tuner(demod, - (struct drx_channel *) - ctrl_data); - } - break; - - /*===================================================================*/ - case DRX_CTRL_DUMP_REGISTERS: - { - return ctrl_dump_registers(demod, - (struct drx_reg_dump *) - ctrl_data); - } - break; - /*===================================================================*/ default: + pr_err("control %d not supported\n", ctrl); return -ENOTSUPP; } } else { diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h index 1696e0d..343ae51 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h @@ -2464,10 +2464,6 @@ Access macros Exported FUNCTIONS -------------------------------------------------------------------------*/ - int drx_init(struct drx_demod_instance *demods[]); - - int drx_term(void); - int drx_open(struct drx_demod_instance *demod); int drx_close(struct drx_demod_instance *demod); -- cgit v1.1 From d0b2519e04bbce2bef1450f23a7a337f129834ef Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sun, 19 Jan 2014 10:06:43 -0300 Subject: [media] drx-j: get rid of its own be??_to_cpu() implementation Instead of handling endiannes with its own internal way, use the already existing macros. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drx_driver.c | 86 +++++------------------ 1 file changed, 16 insertions(+), 70 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c index c144fb7..0803298 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c @@ -134,62 +134,8 @@ FUNCTIONS ------------------------------------------------------------------------------*/ /*============================================================================*/ -/*============================================================================*/ /*===Microcode related functions==============================================*/ /*============================================================================*/ -/*============================================================================*/ - -/** -* \brief Read a 16 bits word, expects big endian data. -* \param addr: Pointer to memory from which to read the 16 bits word. -* \return u16 The data read. -* -* This function takes care of the possible difference in endianness between the -* host and the data contained in the microcode image file. -* -*/ -static u16 u_code_read16(u8 *addr) -{ - /* Works fo any host processor */ - - u16 word = 0; - - word = ((u16) addr[0]); - word <<= 8; - word |= ((u16) addr[1]); - - return word; -} - -/*============================================================================*/ - -/** -* \brief Read a 32 bits word, expects big endian data. -* \param addr: Pointer to memory from which to read the 32 bits word. -* \return u32 The data read. -* -* This function takes care of the possible difference in endianness between the -* host and the data contained in the microcode image file. -* -*/ -static u32 u_code_read32(u8 *addr) -{ - /* Works fo any host processor */ - - u32 word = 0; - - word = ((u16) addr[0]); - word <<= 8; - word |= ((u16) addr[1]); - word <<= 8; - word |= ((u16) addr[2]); - word <<= 8; - word |= ((u16) addr[3]); - - return word; -} - -/*============================================================================*/ /** * \brief Compute CRC of block of microcode data. @@ -205,7 +151,7 @@ static u16 u_code_compute_crc(u8 *block_data, u16 nr_words) u32 carry = 0; while (i < nr_words) { - crc_word |= (u32) u_code_read16(block_data); + crc_word |= (u32) be16_to_cpu(*(u32 *)(block_data)); for (j = 0; j < 16; j++) { crc_word <<= 1; if (carry != 0) @@ -228,7 +174,7 @@ static int check_firmware(struct drx_demod_instance *demod, u8 *mc_data, int i; unsigned count = 2 * sizeof(u16); u32 mc_dev_type, mc_version, mc_base_version; - u16 mc_nr_of_blks = u_code_read16(mc_data + sizeof(u16)); + u16 mc_nr_of_blks = be16_to_cpu(*(u32 *)(mc_data + sizeof(u16))); /* * Scan microcode blocks first for version info @@ -246,13 +192,13 @@ static int check_firmware(struct drx_demod_instance *demod, u8 *mc_data, goto eof; /* Process block header */ - block_hdr.addr = u_code_read32(mc_data + count); + block_hdr.addr = be32_to_cpu(*(u32 *)(mc_data + count)); count += sizeof(u32); - block_hdr.size = u_code_read16(mc_data + count); + block_hdr.size = be16_to_cpu(*(u32 *)(mc_data + count)); count += sizeof(u16); - block_hdr.flags = u_code_read16(mc_data + count); + block_hdr.flags = be16_to_cpu(*(u32 *)(mc_data + count)); count += sizeof(u16); - block_hdr.CRC = u_code_read16(mc_data + count); + block_hdr.CRC = be16_to_cpu(*(u32 *)(mc_data + count)); count += sizeof(u16); pr_debug("%u: addr %u, size %u, flags 0x%04x, CRC 0x%04x\n", @@ -266,7 +212,7 @@ static int check_firmware(struct drx_demod_instance *demod, u8 *mc_data, if (block_hdr.addr + sizeof(u16) > size) goto eof; - auxtype = u_code_read16(auxblk); + auxtype = be16_to_cpu(*(u32 *)(auxblk)); /* Aux block. Check type */ if (DRX_ISMCVERTYPE(auxtype)) { @@ -274,11 +220,11 @@ static int check_firmware(struct drx_demod_instance *demod, u8 *mc_data, goto eof; auxblk += sizeof(u16); - mc_dev_type = u_code_read32(auxblk); + mc_dev_type = be32_to_cpu(*(u32 *)(auxblk)); auxblk += sizeof(u32); - mc_version = u_code_read32(auxblk); + mc_version = be32_to_cpu(*(u32 *)(auxblk)); auxblk += sizeof(u32); - mc_base_version = u_code_read32(auxblk); + mc_base_version = be32_to_cpu(*(u32 *)(auxblk)); DRX_ATTR_MCRECORD(demod).aux_type = auxtype; DRX_ATTR_MCRECORD(demod).mc_dev_type = mc_dev_type; @@ -361,9 +307,9 @@ ctrl_u_code(struct drx_demod_instance *demod, mc_data = (void *)mc_data_init; /* Check data */ - mc_magic_word = u_code_read16(mc_data); + mc_magic_word = be16_to_cpu(*(u32 *)(mc_data)); mc_data += sizeof(u16); - mc_nr_of_blks = u_code_read16(mc_data); + mc_nr_of_blks = be16_to_cpu(*(u32 *)(mc_data)); mc_data += sizeof(u16); if ((mc_magic_word != DRX_UCODE_MAGIC_WORD) || (mc_nr_of_blks == 0)) { @@ -396,13 +342,13 @@ ctrl_u_code(struct drx_demod_instance *demod, u16 mc_block_nr_bytes = 0; /* Process block header */ - block_hdr.addr = u_code_read32(mc_data); + block_hdr.addr = be32_to_cpu(*(u32 *)(mc_data)); mc_data += sizeof(u32); - block_hdr.size = u_code_read16(mc_data); + block_hdr.size = be16_to_cpu(*(u32 *)(mc_data)); mc_data += sizeof(u16); - block_hdr.flags = u_code_read16(mc_data); + block_hdr.flags = be16_to_cpu(*(u32 *)(mc_data)); mc_data += sizeof(u16); - block_hdr.CRC = u_code_read16(mc_data); + block_hdr.CRC = be16_to_cpu(*(u32 *)(mc_data)); mc_data += sizeof(u16); pr_debug("%u: addr %u, size %u, flags 0x%04x, CRC 0x%04x\n", -- cgit v1.1 From aafdbaa6cfb4dd02a1eb1ebcbb63a3aba3f8eaa4 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sun, 19 Jan 2014 10:31:47 -0300 Subject: [media] drx-j: reset the DVB scan configuration at powerup Without this fixup, the DRX-J will not be properly initialized, loosing several PIDs. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drxj.c | 151 +++++++++++++++------------- 1 file changed, 80 insertions(+), 71 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index b90e6c1..b1ad26b 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -18354,6 +18354,81 @@ rw_error: /*============================================================================*/ +static void drxj_reset_mode(struct drxj_data *ext_attr) +{ + /* Initialize default AFE configuartion for QAM */ + if (ext_attr->has_lna) { + /* IF AGC off, PGA active */ +#ifndef DRXJ_VSB_ONLY + ext_attr->qam_if_agc_cfg.standard = DRX_STANDARD_ITU_B; + ext_attr->qam_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_OFF; + ext_attr->qam_pga_cfg = 140 + (11 * 13); +#endif + ext_attr->vsb_if_agc_cfg.standard = DRX_STANDARD_8VSB; + ext_attr->vsb_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_OFF; + ext_attr->vsb_pga_cfg = 140 + (11 * 13); + } else { + /* IF AGC on, PGA not active */ +#ifndef DRXJ_VSB_ONLY + ext_attr->qam_if_agc_cfg.standard = DRX_STANDARD_ITU_B; + ext_attr->qam_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; + ext_attr->qam_if_agc_cfg.min_output_level = 0; + ext_attr->qam_if_agc_cfg.max_output_level = 0x7FFF; + ext_attr->qam_if_agc_cfg.speed = 3; + ext_attr->qam_if_agc_cfg.top = 1297; + ext_attr->qam_pga_cfg = 140; +#endif + ext_attr->vsb_if_agc_cfg.standard = DRX_STANDARD_8VSB; + ext_attr->vsb_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; + ext_attr->vsb_if_agc_cfg.min_output_level = 0; + ext_attr->vsb_if_agc_cfg.max_output_level = 0x7FFF; + ext_attr->vsb_if_agc_cfg.speed = 3; + ext_attr->vsb_if_agc_cfg.top = 1024; + ext_attr->vsb_pga_cfg = 140; + } + /* TODO: remove min_output_level and max_output_level for both QAM and VSB after */ + /* mc has not used them */ +#ifndef DRXJ_VSB_ONLY + ext_attr->qam_rf_agc_cfg.standard = DRX_STANDARD_ITU_B; + ext_attr->qam_rf_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; + ext_attr->qam_rf_agc_cfg.min_output_level = 0; + ext_attr->qam_rf_agc_cfg.max_output_level = 0x7FFF; + ext_attr->qam_rf_agc_cfg.speed = 3; + ext_attr->qam_rf_agc_cfg.top = 9500; + ext_attr->qam_rf_agc_cfg.cut_off_current = 4000; + ext_attr->qam_pre_saw_cfg.standard = DRX_STANDARD_ITU_B; + ext_attr->qam_pre_saw_cfg.reference = 0x07; + ext_attr->qam_pre_saw_cfg.use_pre_saw = true; +#endif + /* Initialize default AFE configuartion for VSB */ + ext_attr->vsb_rf_agc_cfg.standard = DRX_STANDARD_8VSB; + ext_attr->vsb_rf_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; + ext_attr->vsb_rf_agc_cfg.min_output_level = 0; + ext_attr->vsb_rf_agc_cfg.max_output_level = 0x7FFF; + ext_attr->vsb_rf_agc_cfg.speed = 3; + ext_attr->vsb_rf_agc_cfg.top = 9500; + ext_attr->vsb_rf_agc_cfg.cut_off_current = 4000; + ext_attr->vsb_pre_saw_cfg.standard = DRX_STANDARD_8VSB; + ext_attr->vsb_pre_saw_cfg.reference = 0x07; + ext_attr->vsb_pre_saw_cfg.use_pre_saw = true; + +#ifndef DRXJ_DIGITAL_ONLY + /* Initialize default AFE configuartion for ATV */ + ext_attr->atv_rf_agc_cfg.standard = DRX_STANDARD_NTSC; + ext_attr->atv_rf_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; + ext_attr->atv_rf_agc_cfg.top = 9500; + ext_attr->atv_rf_agc_cfg.cut_off_current = 4000; + ext_attr->atv_rf_agc_cfg.speed = 3; + ext_attr->atv_if_agc_cfg.standard = DRX_STANDARD_NTSC; + ext_attr->atv_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; + ext_attr->atv_if_agc_cfg.speed = 3; + ext_attr->atv_if_agc_cfg.top = 2400; + ext_attr->atv_pre_saw_cfg.reference = 0x0007; + ext_attr->atv_pre_saw_cfg.use_pre_saw = true; + ext_attr->atv_pre_saw_cfg.standard = DRX_STANDARD_NTSC; +#endif +} + /** * \fn int ctrl_power_mode() * \brief Set the power mode of the device to the specified power mode @@ -18418,6 +18493,9 @@ ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode) if ((*mode == DRX_POWER_UP)) { /* Restore analog & pin configuartion */ + + /* Initialize default AFE configuartion for VSB */ + drxj_reset_mode(ext_attr); } else { /* Power down to requested mode */ /* Backup some register settings */ @@ -20034,6 +20112,7 @@ rw_error: /*============================================================================= ===== EXPORTED FUNCTIONS ====================================================*/ + /** * \fn drxj_open() * \brief Open the demod instance, configure device, configure drxdriver @@ -20221,77 +20300,7 @@ int drxj_open(struct drx_demod_instance *demod) common_attr->scan_demod_lock_timeout = DRXJ_SCAN_TIMEOUT; common_attr->scan_desired_lock = DRX_LOCKED; - /* Initialize default AFE configuartion for QAM */ - if (ext_attr->has_lna) { - /* IF AGC off, PGA active */ -#ifndef DRXJ_VSB_ONLY - ext_attr->qam_if_agc_cfg.standard = DRX_STANDARD_ITU_B; - ext_attr->qam_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_OFF; - ext_attr->qam_pga_cfg = 140 + (11 * 13); -#endif - ext_attr->vsb_if_agc_cfg.standard = DRX_STANDARD_8VSB; - ext_attr->vsb_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_OFF; - ext_attr->vsb_pga_cfg = 140 + (11 * 13); - } else { - /* IF AGC on, PGA not active */ -#ifndef DRXJ_VSB_ONLY - ext_attr->qam_if_agc_cfg.standard = DRX_STANDARD_ITU_B; - ext_attr->qam_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; - ext_attr->qam_if_agc_cfg.min_output_level = 0; - ext_attr->qam_if_agc_cfg.max_output_level = 0x7FFF; - ext_attr->qam_if_agc_cfg.speed = 3; - ext_attr->qam_if_agc_cfg.top = 1297; - ext_attr->qam_pga_cfg = 140; -#endif - ext_attr->vsb_if_agc_cfg.standard = DRX_STANDARD_8VSB; - ext_attr->vsb_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; - ext_attr->vsb_if_agc_cfg.min_output_level = 0; - ext_attr->vsb_if_agc_cfg.max_output_level = 0x7FFF; - ext_attr->vsb_if_agc_cfg.speed = 3; - ext_attr->vsb_if_agc_cfg.top = 1024; - ext_attr->vsb_pga_cfg = 140; - } - /* TODO: remove min_output_level and max_output_level for both QAM and VSB after */ - /* mc has not used them */ -#ifndef DRXJ_VSB_ONLY - ext_attr->qam_rf_agc_cfg.standard = DRX_STANDARD_ITU_B; - ext_attr->qam_rf_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; - ext_attr->qam_rf_agc_cfg.min_output_level = 0; - ext_attr->qam_rf_agc_cfg.max_output_level = 0x7FFF; - ext_attr->qam_rf_agc_cfg.speed = 3; - ext_attr->qam_rf_agc_cfg.top = 9500; - ext_attr->qam_rf_agc_cfg.cut_off_current = 4000; - ext_attr->qam_pre_saw_cfg.standard = DRX_STANDARD_ITU_B; - ext_attr->qam_pre_saw_cfg.reference = 0x07; - ext_attr->qam_pre_saw_cfg.use_pre_saw = true; -#endif - /* Initialize default AFE configuartion for VSB */ - ext_attr->vsb_rf_agc_cfg.standard = DRX_STANDARD_8VSB; - ext_attr->vsb_rf_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; - ext_attr->vsb_rf_agc_cfg.min_output_level = 0; - ext_attr->vsb_rf_agc_cfg.max_output_level = 0x7FFF; - ext_attr->vsb_rf_agc_cfg.speed = 3; - ext_attr->vsb_rf_agc_cfg.top = 9500; - ext_attr->vsb_rf_agc_cfg.cut_off_current = 4000; - ext_attr->vsb_pre_saw_cfg.standard = DRX_STANDARD_8VSB; - ext_attr->vsb_pre_saw_cfg.reference = 0x07; - ext_attr->vsb_pre_saw_cfg.use_pre_saw = true; - -#ifndef DRXJ_DIGITAL_ONLY - /* Initialize default AFE configuartion for ATV */ - ext_attr->atv_rf_agc_cfg.standard = DRX_STANDARD_NTSC; - ext_attr->atv_rf_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; - ext_attr->atv_rf_agc_cfg.top = 9500; - ext_attr->atv_rf_agc_cfg.cut_off_current = 4000; - ext_attr->atv_rf_agc_cfg.speed = 3; - ext_attr->atv_if_agc_cfg.standard = DRX_STANDARD_NTSC; - ext_attr->atv_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; - ext_attr->atv_if_agc_cfg.speed = 3; - ext_attr->atv_if_agc_cfg.top = 2400; - ext_attr->atv_pre_saw_cfg.reference = 0x0007; - ext_attr->atv_pre_saw_cfg.use_pre_saw = true; - ext_attr->atv_pre_saw_cfg.standard = DRX_STANDARD_NTSC; -#endif + drxj_reset_mode(ext_attr); ext_attr->standard = DRX_STANDARD_UNKNOWN; rc = smart_ant_init(demod); -- cgit v1.1 From 96b43136b8c1824ad1a02269c1c48f25d2df8282 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sun, 19 Jan 2014 12:08:36 -0300 Subject: [media] drx-j: Allow standard selection ClearQAM is currently not working. Add support for it too. Unlikely other ATSC tuners, though, this device will not auto-detect between ATSC and ClearQAM. So, the delivery system should be properly set. Also, this frontend seems to also support DVB-C annex A/C. Add experimental support for them. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drx39xxj.c | 29 +++++++++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c index f0f14ed..7a7a4a8 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c @@ -188,7 +188,8 @@ static int drx39xxj_set_frontend(struct dvb_frontend *fe) struct drx_channel channel; int result; struct drxuio_data uio_data; - struct drx_channel def_channel = { /* frequency */ 0, + static const struct drx_channel def_channel = { + /* frequency */ 0, /* bandwidth */ DRX_BANDWIDTH_6MHZ, /* mirror */ DRX_MIRROR_NO, /* constellation */ DRX_CONSTELLATION_AUTO, @@ -204,6 +205,7 @@ static int drx39xxj_set_frontend(struct dvb_frontend *fe) /* carrier */ DRX_CARRIER_UNKNOWN, /* frame mode */ DRX_FRAMEMODE_UNKNOWN }; + u32 constellation = DRX_CONSTELLATION_AUTO; /* Bring the demod out of sleep */ drx39xxj_set_powerstate(fe, 1); @@ -217,6 +219,29 @@ static int drx39xxj_set_frontend(struct dvb_frontend *fe) fe->ops.i2c_gate_ctrl(fe, 0); } + switch (p->delivery_system) { + case SYS_ATSC: + standard = DRX_STANDARD_8VSB; + break; + case SYS_DVBC_ANNEX_B: + standard = DRX_STANDARD_ITU_B; + + switch (p->modulation) { + case QAM_64: + constellation = DRX_CONSTELLATION_QAM64; + break; + case QAM_256: + constellation = DRX_CONSTELLATION_QAM256; + break; + default: + constellation = DRX_CONSTELLATION_AUTO; + break; + } + break; + default: + return -EINVAL; + } + if (standard != state->current_standard || state->powered_up == 0) { /* Set the standard (will be powered up if necessary */ result = drx_ctrl(demod, DRX_CTRL_SET_STANDARD, &standard); @@ -233,7 +258,7 @@ static int drx39xxj_set_frontend(struct dvb_frontend *fe) channel = def_channel; channel.frequency = p->frequency / 1000; channel.bandwidth = DRX_BANDWIDTH_6MHZ; - channel.constellation = DRX_CONSTELLATION_AUTO; + channel.constellation = constellation; /* program channel */ result = drx_ctrl(demod, DRX_CTRL_SET_CHANNEL, &channel); -- cgit v1.1 From 1e76a99963f4c03d2bf7f729c28772e9a7f00386 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Wed, 22 Jan 2014 10:21:55 -0300 Subject: [media] drx-j: Some cleanups at drx_driver.c source This is mostly CodingStyle fixes and improvements. No functional changes. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drx39xxj.h | 2 +- drivers/media/dvb-frontends/drx39xyj/drx_driver.c | 269 ++++++++++------------ 2 files changed, 118 insertions(+), 153 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h index 8c24d73..b9f642e 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h @@ -31,7 +31,7 @@ struct drx39xxj_state { struct drx_demod_instance *demod; enum drx_standard current_standard; struct dvb_frontend frontend; - int powered_up:1; + unsigned int powered_up:1; unsigned int i2c_gate_open:1; const struct firmware *fw; }; diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c index 0803298..afeda82 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c @@ -32,70 +32,42 @@ #define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__ - /*------------------------------------------------------------------------------ INCLUDE FILES ------------------------------------------------------------------------------*/ #include "drx_driver.h" -#define VERSION_FIXED 0 -#if VERSION_FIXED #define VERSION_MAJOR 0 #define VERSION_MINOR 0 #define VERSION_PATCH 0 -#else -#include "drx_driver_version.h" -#endif -/*------------------------------------------------------------------------------ -DEFINES -------------------------------------------------------------------------------*/ +/* + * DEFINES + */ -/*============================================================================*/ -/*=== MICROCODE RELATED DEFINES ==============================================*/ -/*============================================================================*/ +/* +/* MICROCODE RELATED DEFINES + */ -/** \brief Magic word for checking correct Endianess of microcode data. */ -#ifndef DRX_UCODE_MAGIC_WORD +/* Magic word for checking correct Endianess of microcode data */ #define DRX_UCODE_MAGIC_WORD ((((u16)'H')<<8)+((u16)'L')) -#endif -/** \brief CRC flag in ucode header, flags field. */ -#ifndef DRX_UCODE_CRC_FLAG +/* CRC flag in ucode header, flags field. */ #define DRX_UCODE_CRC_FLAG (0x0001) -#endif -/** \brief Compression flag in ucode header, flags field. */ -#ifndef DRX_UCODE_COMPRESSION_FLAG -#define DRX_UCODE_COMPRESSION_FLAG (0x0002) -#endif - -/** \brief Maximum size of buffer used to verify the microcode. - Must be an even number. */ -#ifndef DRX_UCODE_MAX_BUF_SIZE +/* + * Maximum size of buffer used to verify the microcode. + * Must be an even number + */ #define DRX_UCODE_MAX_BUF_SIZE (DRXDAP_MAX_RCHUNKSIZE) -#endif + #if DRX_UCODE_MAX_BUF_SIZE & 1 #error DRX_UCODE_MAX_BUF_SIZE must be an even number #endif -/*============================================================================*/ -/*=== CHANNEL SCAN RELATED DEFINES ===========================================*/ -/*============================================================================*/ - -/** -* \brief Maximum progress indication. -* -* Progress indication will run from 0 upto DRX_SCAN_MAX_PROGRESS during scan. -* -*/ -#ifndef DRX_SCAN_MAX_PROGRESS -#define DRX_SCAN_MAX_PROGRESS 1000 -#endif - -/*============================================================================*/ -/*=== MACROS =================================================================*/ -/*============================================================================*/ +/* + * Power mode macros + */ #define DRX_ISPOWERDOWNMODE(mode) ((mode == DRX_POWER_MODE_9) || \ (mode == DRX_POWER_MODE_10) || \ @@ -108,41 +80,40 @@ DEFINES (mode == DRX_POWER_DOWN)) /*------------------------------------------------------------------------------ -GLOBAL VARIABLES -------------------------------------------------------------------------------*/ - -/*------------------------------------------------------------------------------ STRUCTURES ------------------------------------------------------------------------------*/ -/** \brief Structure of the microcode block headers */ + +/** + * struct drxu_code_block_hdr - Structure of the microcode block headers + * + * @addr: Destination address of the data in this block + * @size: Size of the block data following this header counted in + * 16 bits words + * @CRC: CRC value of the data block, only valid if CRC flag is + * set. + */ struct drxu_code_block_hdr { u32 addr; - /**< Destination address of the data in this block */ u16 size; - /**< Size of the block data following this header counted in - 16 bits words */ u16 flags; - /**< Flags for this data block: - - bit[0]= CRC on/off - - bit[1]= compression on/off - - bit[15..2]=reserved */ - u16 CRC;/**< CRC value of the data block, only valid if CRC flag is - set. */}; + u16 CRC; +}; /*------------------------------------------------------------------------------ FUNCTIONS ------------------------------------------------------------------------------*/ -/*============================================================================*/ -/*===Microcode related functions==============================================*/ -/*============================================================================*/ +/* + * Microcode related functions + */ /** -* \brief Compute CRC of block of microcode data. -* \param block_data: Pointer to microcode data. -* \param nr_words: Size of microcode block (number of 16 bits words). -* \return u16 The computed CRC residu. -*/ + * u_code_compute_crc - Compute CRC of block of microcode data. + * @block_data: Pointer to microcode data. + * @nr_words: Size of microcode block (number of 16 bits words). + * + * returns The computed CRC residue. + */ static u16 u_code_compute_crc(u8 *block_data, u16 nr_words) { u16 i = 0; @@ -151,7 +122,7 @@ static u16 u_code_compute_crc(u8 *block_data, u16 nr_words) u32 carry = 0; while (i < nr_words) { - crc_word |= (u32) be16_to_cpu(*(u32 *)(block_data)); + crc_word |= (u32)be16_to_cpu(*(u32 *)(block_data)); for (j = 0; j < 16; j++) { crc_word <<= 1; if (carry != 0) @@ -164,9 +135,13 @@ static u16 u_code_compute_crc(u8 *block_data, u16 nr_words) return (u16)(crc_word >> 16); } -/*============================================================================*/ - - +/** + * check_firmware - checks if the loaded firmware is valid + * + * @demod: demod structure + * @mc_data: pointer to the start of the firmware + * @size: firmware size + */ static int check_firmware(struct drx_demod_instance *demod, u8 *mc_data, unsigned size) { @@ -247,26 +222,27 @@ eof: } /** -* \brief Handle microcode upload or verify. -* \param dev_addr: Address of device. -* \param mc_info: Pointer to information about microcode data. -* \param action: Either UCODE_UPLOAD or UCODE_VERIFY -* \return int. -* \retval 0: -* - In case of UCODE_UPLOAD: code is successfully uploaded. -* - In case of UCODE_VERIFY: image on device is equal to -* image provided to this control function. -* \retval -EIO: -* - In case of UCODE_UPLOAD: I2C error. -* - In case of UCODE_VERIFY: I2C error or image on device -* is not equal to image provided to this control function. -* \retval -EINVAL: -* - Invalid arguments. -* - Provided image is corrupt -*/ -static int -ctrl_u_code(struct drx_demod_instance *demod, - struct drxu_code_info *mc_info, enum drxu_code_action action) + * ctrl_u_code - Handle microcode upload or verify. + * @dev_addr: Address of device. + * @mc_info: Pointer to information about microcode data. + * @action: Either UCODE_UPLOAD or UCODE_VERIFY + * + * This function returns: + * 0: + * - In case of UCODE_UPLOAD: code is successfully uploaded. + * - In case of UCODE_VERIFY: image on device is equal to + * image provided to this control function. + * -EIO: + * - In case of UCODE_UPLOAD: I2C error. + * - In case of UCODE_VERIFY: I2C error or image on device + * is not equal to image provided to this control function. + * -EINVAL: + * - Invalid arguments. + * - Provided image is corrupt + */ +static int ctrl_u_code(struct drx_demod_instance *demod, + struct drxu_code_info *mc_info, + enum drxu_code_action action) { struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; int rc; @@ -448,15 +424,16 @@ release: /*============================================================================*/ /** -* \brief Build list of version information. -* \param demod: A pointer to a demodulator instance. -* \param version_list: Pointer to linked list of versions. -* \return int. -* \retval 0: Version information stored in version_list -* \retval -EINVAL: Invalid arguments. -*/ -static int -ctrl_version(struct drx_demod_instance *demod, struct drx_version_list **version_list) + * ctrl_version - Build list of version information. + * @demod: A pointer to a demodulator instance. + * @version_list: Pointer to linked list of versions. + * + * This function returns: + * 0: Version information stored in version_list + * -EINVAL: Invalid arguments. + */ +static int ctrl_version(struct drx_demod_instance *demod, + struct drx_version_list **version_list) { static char drx_driver_core_module_name[] = "Core driver"; static char drx_driver_core_version_text[] = @@ -465,7 +442,7 @@ ctrl_version(struct drx_demod_instance *demod, struct drx_version_list **version static struct drx_version drx_driver_core_version; static struct drx_version_list drx_driver_core_version_list; - struct drx_version_list *demod_version_list = (struct drx_version_list *) (NULL); + struct drx_version_list *demod_version_list = NULL; int return_status = -EIO; /* Check arguments */ @@ -507,22 +484,21 @@ ctrl_version(struct drx_demod_instance *demod, struct drx_version_list **version return 0; } -/*============================================================================*/ -/*============================================================================*/ -/*== Exported functions ======================================================*/ -/*============================================================================*/ -/*============================================================================*/ +/* + * Exported functions + */ /** -* \brief Open a demodulator instance. -* \param demod: A pointer to a demodulator instance. -* \return int Return status. -* \retval 0: Opened demod instance with succes. -* \retval -EIO: Driver not initialized or unable to initialize -* demod. -* \retval -EINVAL: Demod instance has invalid content. -* -*/ + * drx_open - Open a demodulator instance. + * @demod: A pointer to a demodulator instance. + * + * This function returns: + * 0: Opened demod instance with succes. + * -EIO: Driver not initialized or unable to initialize + * demod. + * -EINVAL: Demod instance has invalid content. + * + */ int drx_open(struct drx_demod_instance *demod) { @@ -548,18 +524,18 @@ int drx_open(struct drx_demod_instance *demod) /*============================================================================*/ /** -* \brief Close device. -* \param demod: A pointer to a demodulator instance. -* \return int Return status. -* \retval 0: Closed demod instance with succes. -* \retval -EIO: Driver not initialized or error during close -* demod. -* \retval -EINVAL: Demod instance has invalid content. -* -* Free resources occupied by device instance. -* Put device into sleep mode. -*/ - + * drx_close - Close device + * @demod: A pointer to a demodulator instance. + * + * Free resources occupied by device instance. + * Put device into sleep mode. + * + * This function returns: + * 0: Closed demod instance with succes. + * -EIO: Driver not initialized or error during close + * demod. + * -EINVAL: Demod instance has invalid content. + */ int drx_close(struct drx_demod_instance *demod) { int status = 0; @@ -579,29 +555,22 @@ int drx_close(struct drx_demod_instance *demod) return status; } - -/*============================================================================*/ - /** -* \brief Control the device. -* \param demod: A pointer to a demodulator instance. -* \param ctrl: Reference to desired control function. -* \param ctrl_data: Pointer to data structure for control function. -* \return int Return status. -* \retval 0: Control function completed successfully. -* \retval -EIO: Driver not initialized or error during -* control demod. -* \retval -EINVAL: Demod instance or ctrl_data has invalid -* content. -* \retval -ENOTSUPP: Specified control function is not -* available. -* -* Data needed or returned by the control function is stored in ctrl_data. -* -*/ - -int -drx_ctrl(struct drx_demod_instance *demod, u32 ctrl, void *ctrl_data) + * drx_ctrl - Control the device. + * @demod: A pointer to a demodulator instance. + * @ctrl: Reference to desired control function. + * @ctrl_data: Pointer to data structure for control function. + * + * Data needed or returned by the control function is stored in ctrl_data. + * + * This function returns: + * 0: Control function completed successfully. + * -EIO: Driver not initialized or error during control demod. + * -EINVAL: Demod instance or ctrl_data has invalid content. + * -ENOTSUPP: Specified control function is not available. + */ + +int drx_ctrl(struct drx_demod_instance *demod, u32 ctrl, void *ctrl_data) { int status = -EIO; @@ -680,7 +649,3 @@ drx_ctrl(struct drx_demod_instance *demod, u32 ctrl, void *ctrl_data) return 0; } - -/*============================================================================*/ - -/* END OF FILE */ -- cgit v1.1 From ad55f6c881bd2d88576c6a38c4964632d4851d11 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Fri, 24 Jan 2014 06:15:46 -0300 Subject: [media] drx-j: prepend function names with drx_ at drx_driver.c In order to prepare to get rid of drx_driver.c, prepend all functions there with drx_. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drx_driver.c | 28 +++++++++++------------ 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c index afeda82..0ebc0d2 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c @@ -46,7 +46,7 @@ INCLUDE FILES */ /* -/* MICROCODE RELATED DEFINES + * MICROCODE RELATED DEFINES */ /* Magic word for checking correct Endianess of microcode data */ @@ -108,13 +108,13 @@ FUNCTIONS */ /** - * u_code_compute_crc - Compute CRC of block of microcode data. + * drx_u_code_compute_crc - Compute CRC of block of microcode data. * @block_data: Pointer to microcode data. * @nr_words: Size of microcode block (number of 16 bits words). * * returns The computed CRC residue. */ -static u16 u_code_compute_crc(u8 *block_data, u16 nr_words) +static u16 drx_u_code_compute_crc(u8 *block_data, u16 nr_words) { u16 i = 0; u16 j = 0; @@ -136,13 +136,13 @@ static u16 u_code_compute_crc(u8 *block_data, u16 nr_words) } /** - * check_firmware - checks if the loaded firmware is valid + * drx_check_firmware - checks if the loaded firmware is valid * * @demod: demod structure * @mc_data: pointer to the start of the firmware * @size: firmware size */ -static int check_firmware(struct drx_demod_instance *demod, u8 *mc_data, +static int drx_check_firmware(struct drx_demod_instance *demod, u8 *mc_data, unsigned size) { struct drxu_code_block_hdr block_hdr; @@ -222,7 +222,7 @@ eof: } /** - * ctrl_u_code - Handle microcode upload or verify. + * drx_ctrl_u_code - Handle microcode upload or verify. * @dev_addr: Address of device. * @mc_info: Pointer to information about microcode data. * @action: Either UCODE_UPLOAD or UCODE_VERIFY @@ -240,7 +240,7 @@ eof: * - Invalid arguments. * - Provided image is corrupt */ -static int ctrl_u_code(struct drx_demod_instance *demod, +static int drx_ctrl_u_code(struct drx_demod_instance *demod, struct drxu_code_info *mc_info, enum drxu_code_action action) { @@ -295,7 +295,7 @@ static int ctrl_u_code(struct drx_demod_instance *demod, } if (action == UCODE_UPLOAD) { - rc = check_firmware(demod, (u8 *)mc_data_init, size); + rc = drx_check_firmware(demod, (u8 *)mc_data_init, size); if (rc) goto release; @@ -337,7 +337,7 @@ static int ctrl_u_code(struct drx_demod_instance *demod, */ if ((block_hdr.size > 0x7FFF) || (((block_hdr.flags & DRX_UCODE_CRC_FLAG) != 0) && - (block_hdr.CRC != u_code_compute_crc(mc_data, block_hdr.size))) + (block_hdr.CRC != drx_u_code_compute_crc(mc_data, block_hdr.size))) ) { /* Wrong data ! */ rc = -EINVAL; @@ -424,7 +424,7 @@ release: /*============================================================================*/ /** - * ctrl_version - Build list of version information. + * drx_ctrl_version - Build list of version information. * @demod: A pointer to a demodulator instance. * @version_list: Pointer to linked list of versions. * @@ -432,7 +432,7 @@ release: * 0: Version information stored in version_list * -EINVAL: Invalid arguments. */ -static int ctrl_version(struct drx_demod_instance *demod, +static int drx_ctrl_version(struct drx_demod_instance *demod, struct drx_version_list **version_list) { static char drx_driver_core_module_name[] = "Core driver"; @@ -607,7 +607,7 @@ int drx_ctrl(struct drx_demod_instance *demod, u32 ctrl, void *ctrl_data) /*======================================================================*/ case DRX_CTRL_VERSION: - return ctrl_version(demod, (struct drx_version_list **)ctrl_data); + return drx_ctrl_version(demod, (struct drx_version_list **)ctrl_data); break; /*======================================================================*/ @@ -624,7 +624,7 @@ int drx_ctrl(struct drx_demod_instance *demod, u32 ctrl, void *ctrl_data) switch (ctrl) { /*===================================================================*/ case DRX_CTRL_LOAD_UCODE: - return ctrl_u_code(demod, + return drx_ctrl_u_code(demod, (struct drxu_code_info *)ctrl_data, UCODE_UPLOAD); break; @@ -632,7 +632,7 @@ int drx_ctrl(struct drx_demod_instance *demod, u32 ctrl, void *ctrl_data) /*===================================================================*/ case DRX_CTRL_VERIFY_UCODE: { - return ctrl_u_code(demod, + return drx_ctrl_u_code(demod, (struct drxu_code_info *)ctrl_data, UCODE_VERIFY); } -- cgit v1.1 From b240eacdd536bac23c9d48dfc3d527ed6870ddad Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Fri, 24 Jan 2014 06:25:07 -0300 Subject: [media] drx-j: get rid of drx_driver.c This file contains just the firmware load code, that it is also somewhat duplicated at drxj.c. Move the code into there. Latter patches will remove the duplicated code. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/Makefile | 2 +- drivers/media/dvb-frontends/drx39xyj/drx_driver.c | 651 ---------------------- drivers/media/dvb-frontends/drx39xyj/drxj.c | 597 +++++++++++++++++++- 3 files changed, 593 insertions(+), 657 deletions(-) delete mode 100644 drivers/media/dvb-frontends/drx39xyj/drx_driver.c diff --git a/drivers/media/dvb-frontends/drx39xyj/Makefile b/drivers/media/dvb-frontends/drx39xyj/Makefile index f84c5d8..d9ed094 100644 --- a/drivers/media/dvb-frontends/drx39xyj/Makefile +++ b/drivers/media/dvb-frontends/drx39xyj/Makefile @@ -1,4 +1,4 @@ -drx39xyj-objs := drx39xxj.o drx_driver.o drx39xxj_dummy.o drxj.o drx_dap_fasi.o +drx39xyj-objs := drx39xxj.o drx39xxj_dummy.o drxj.o drx_dap_fasi.o obj-$(CONFIG_DVB_DRX39XYJ) += drx39xyj.o diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c deleted file mode 100644 index 0ebc0d2..0000000 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c +++ /dev/null @@ -1,651 +0,0 @@ -/* - Generic DRX functionality, DRX driver core. - - Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - * Neither the name of Trident Microsystems nor Hauppauge Computer Works - nor the names of its contributors may be used to endorse or promote - products derived from this software without specific prior written - permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. -*/ - -#define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__ - -/*------------------------------------------------------------------------------ -INCLUDE FILES -------------------------------------------------------------------------------*/ -#include "drx_driver.h" - -#define VERSION_MAJOR 0 -#define VERSION_MINOR 0 -#define VERSION_PATCH 0 - -/* - * DEFINES - */ - -/* - * MICROCODE RELATED DEFINES - */ - -/* Magic word for checking correct Endianess of microcode data */ -#define DRX_UCODE_MAGIC_WORD ((((u16)'H')<<8)+((u16)'L')) - -/* CRC flag in ucode header, flags field. */ -#define DRX_UCODE_CRC_FLAG (0x0001) - -/* - * Maximum size of buffer used to verify the microcode. - * Must be an even number - */ -#define DRX_UCODE_MAX_BUF_SIZE (DRXDAP_MAX_RCHUNKSIZE) - -#if DRX_UCODE_MAX_BUF_SIZE & 1 -#error DRX_UCODE_MAX_BUF_SIZE must be an even number -#endif - -/* - * Power mode macros - */ - -#define DRX_ISPOWERDOWNMODE(mode) ((mode == DRX_POWER_MODE_9) || \ - (mode == DRX_POWER_MODE_10) || \ - (mode == DRX_POWER_MODE_11) || \ - (mode == DRX_POWER_MODE_12) || \ - (mode == DRX_POWER_MODE_13) || \ - (mode == DRX_POWER_MODE_14) || \ - (mode == DRX_POWER_MODE_15) || \ - (mode == DRX_POWER_MODE_16) || \ - (mode == DRX_POWER_DOWN)) - -/*------------------------------------------------------------------------------ -STRUCTURES -------------------------------------------------------------------------------*/ - -/** - * struct drxu_code_block_hdr - Structure of the microcode block headers - * - * @addr: Destination address of the data in this block - * @size: Size of the block data following this header counted in - * 16 bits words - * @CRC: CRC value of the data block, only valid if CRC flag is - * set. - */ -struct drxu_code_block_hdr { - u32 addr; - u16 size; - u16 flags; - u16 CRC; -}; - -/*------------------------------------------------------------------------------ -FUNCTIONS -------------------------------------------------------------------------------*/ - -/* - * Microcode related functions - */ - -/** - * drx_u_code_compute_crc - Compute CRC of block of microcode data. - * @block_data: Pointer to microcode data. - * @nr_words: Size of microcode block (number of 16 bits words). - * - * returns The computed CRC residue. - */ -static u16 drx_u_code_compute_crc(u8 *block_data, u16 nr_words) -{ - u16 i = 0; - u16 j = 0; - u32 crc_word = 0; - u32 carry = 0; - - while (i < nr_words) { - crc_word |= (u32)be16_to_cpu(*(u32 *)(block_data)); - for (j = 0; j < 16; j++) { - crc_word <<= 1; - if (carry != 0) - crc_word ^= 0x80050000UL; - carry = crc_word & 0x80000000UL; - } - i++; - block_data += (sizeof(u16)); - } - return (u16)(crc_word >> 16); -} - -/** - * drx_check_firmware - checks if the loaded firmware is valid - * - * @demod: demod structure - * @mc_data: pointer to the start of the firmware - * @size: firmware size - */ -static int drx_check_firmware(struct drx_demod_instance *demod, u8 *mc_data, - unsigned size) -{ - struct drxu_code_block_hdr block_hdr; - int i; - unsigned count = 2 * sizeof(u16); - u32 mc_dev_type, mc_version, mc_base_version; - u16 mc_nr_of_blks = be16_to_cpu(*(u32 *)(mc_data + sizeof(u16))); - - /* - * Scan microcode blocks first for version info - * and firmware check - */ - - /* Clear version block */ - DRX_ATTR_MCRECORD(demod).aux_type = 0; - DRX_ATTR_MCRECORD(demod).mc_dev_type = 0; - DRX_ATTR_MCRECORD(demod).mc_version = 0; - DRX_ATTR_MCRECORD(demod).mc_base_version = 0; - - for (i = 0; i < mc_nr_of_blks; i++) { - if (count + 3 * sizeof(u16) + sizeof(u32) > size) - goto eof; - - /* Process block header */ - block_hdr.addr = be32_to_cpu(*(u32 *)(mc_data + count)); - count += sizeof(u32); - block_hdr.size = be16_to_cpu(*(u32 *)(mc_data + count)); - count += sizeof(u16); - block_hdr.flags = be16_to_cpu(*(u32 *)(mc_data + count)); - count += sizeof(u16); - block_hdr.CRC = be16_to_cpu(*(u32 *)(mc_data + count)); - count += sizeof(u16); - - pr_debug("%u: addr %u, size %u, flags 0x%04x, CRC 0x%04x\n", - count, block_hdr.addr, block_hdr.size, block_hdr.flags, - block_hdr.CRC); - - if (block_hdr.flags & 0x8) { - u8 *auxblk = ((void *)mc_data) + block_hdr.addr; - u16 auxtype; - - if (block_hdr.addr + sizeof(u16) > size) - goto eof; - - auxtype = be16_to_cpu(*(u32 *)(auxblk)); - - /* Aux block. Check type */ - if (DRX_ISMCVERTYPE(auxtype)) { - if (block_hdr.addr + 2 * sizeof(u16) + 2 * sizeof (u32) > size) - goto eof; - - auxblk += sizeof(u16); - mc_dev_type = be32_to_cpu(*(u32 *)(auxblk)); - auxblk += sizeof(u32); - mc_version = be32_to_cpu(*(u32 *)(auxblk)); - auxblk += sizeof(u32); - mc_base_version = be32_to_cpu(*(u32 *)(auxblk)); - - DRX_ATTR_MCRECORD(demod).aux_type = auxtype; - DRX_ATTR_MCRECORD(demod).mc_dev_type = mc_dev_type; - DRX_ATTR_MCRECORD(demod).mc_version = mc_version; - DRX_ATTR_MCRECORD(demod).mc_base_version = mc_base_version; - - pr_info("Firmware dev %x, ver %x, base ver %x\n", - mc_dev_type, mc_version, mc_base_version); - - } - } else if (count + block_hdr.size * sizeof(u16) > size) - goto eof; - - count += block_hdr.size * sizeof(u16); - } - return 0; -eof: - pr_err("Firmware is truncated at pos %u/%u\n", count, size); - return -EINVAL; -} - -/** - * drx_ctrl_u_code - Handle microcode upload or verify. - * @dev_addr: Address of device. - * @mc_info: Pointer to information about microcode data. - * @action: Either UCODE_UPLOAD or UCODE_VERIFY - * - * This function returns: - * 0: - * - In case of UCODE_UPLOAD: code is successfully uploaded. - * - In case of UCODE_VERIFY: image on device is equal to - * image provided to this control function. - * -EIO: - * - In case of UCODE_UPLOAD: I2C error. - * - In case of UCODE_VERIFY: I2C error or image on device - * is not equal to image provided to this control function. - * -EINVAL: - * - Invalid arguments. - * - Provided image is corrupt - */ -static int drx_ctrl_u_code(struct drx_demod_instance *demod, - struct drxu_code_info *mc_info, - enum drxu_code_action action) -{ - struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; - int rc; - u16 i = 0; - u16 mc_nr_of_blks = 0; - u16 mc_magic_word = 0; - const u8 *mc_data_init = NULL; - u8 *mc_data = NULL; - unsigned size; - char *mc_file = mc_info->mc_file; - - /* Check arguments */ - if (!mc_info || !mc_file) - return -EINVAL; - - if (!demod->firmware) { - const struct firmware *fw = NULL; - - rc = request_firmware(&fw, mc_file, demod->i2c->dev.parent); - if (rc < 0) { - pr_err("Couldn't read firmware %s\n", mc_file); - return -ENOENT; - } - demod->firmware = fw; - - if (demod->firmware->size < 2 * sizeof(u16)) { - rc = -EINVAL; - pr_err("Firmware is too short!\n"); - goto release; - } - - pr_info("Firmware %s, size %zu\n", - mc_file, demod->firmware->size); - } - - mc_data_init = demod->firmware->data; - size = demod->firmware->size; - - mc_data = (void *)mc_data_init; - /* Check data */ - mc_magic_word = be16_to_cpu(*(u32 *)(mc_data)); - mc_data += sizeof(u16); - mc_nr_of_blks = be16_to_cpu(*(u32 *)(mc_data)); - mc_data += sizeof(u16); - - if ((mc_magic_word != DRX_UCODE_MAGIC_WORD) || (mc_nr_of_blks == 0)) { - rc = -EINVAL; - pr_err("Firmware magic word doesn't match\n"); - goto release; - } - - if (action == UCODE_UPLOAD) { - rc = drx_check_firmware(demod, (u8 *)mc_data_init, size); - if (rc) - goto release; - - /* After scanning, validate the microcode. - It is also valid if no validation control exists. - */ - rc = drx_ctrl(demod, DRX_CTRL_VALIDATE_UCODE, NULL); - if (rc != 0 && rc != -ENOTSUPP) { - pr_err("Validate ucode not supported\n"); - return rc; - } - pr_info("Uploading firmware %s\n", mc_file); - } else if (action == UCODE_VERIFY) { - pr_info("Verifying if firmware upload was ok.\n"); - } - - /* Process microcode blocks */ - for (i = 0; i < mc_nr_of_blks; i++) { - struct drxu_code_block_hdr block_hdr; - u16 mc_block_nr_bytes = 0; - - /* Process block header */ - block_hdr.addr = be32_to_cpu(*(u32 *)(mc_data)); - mc_data += sizeof(u32); - block_hdr.size = be16_to_cpu(*(u32 *)(mc_data)); - mc_data += sizeof(u16); - block_hdr.flags = be16_to_cpu(*(u32 *)(mc_data)); - mc_data += sizeof(u16); - block_hdr.CRC = be16_to_cpu(*(u32 *)(mc_data)); - mc_data += sizeof(u16); - - pr_debug("%u: addr %u, size %u, flags 0x%04x, CRC 0x%04x\n", - (unsigned)(mc_data - mc_data_init), block_hdr.addr, - block_hdr.size, block_hdr.flags, block_hdr.CRC); - - /* Check block header on: - - data larger than 64Kb - - if CRC enabled check CRC - */ - if ((block_hdr.size > 0x7FFF) || - (((block_hdr.flags & DRX_UCODE_CRC_FLAG) != 0) && - (block_hdr.CRC != drx_u_code_compute_crc(mc_data, block_hdr.size))) - ) { - /* Wrong data ! */ - rc = -EINVAL; - pr_err("firmware CRC is wrong\n"); - goto release; - } - - if (!block_hdr.size) - continue; - - mc_block_nr_bytes = block_hdr.size * ((u16) sizeof(u16)); - - /* Perform the desired action */ - switch (action) { - case UCODE_UPLOAD: /* Upload microcode */ - if (demod->my_access_funct->write_block_func(dev_addr, - block_hdr.addr, - mc_block_nr_bytes, - mc_data, 0x0000)) { - rc = -EIO; - pr_err("error writing firmware at pos %u\n", - (unsigned)(mc_data - mc_data_init)); - goto release; - } - break; - case UCODE_VERIFY: { /* Verify uploaded microcode */ - int result = 0; - u8 mc_data_buffer[DRX_UCODE_MAX_BUF_SIZE]; - u32 bytes_to_comp = 0; - u32 bytes_left = mc_block_nr_bytes; - u32 curr_addr = block_hdr.addr; - u8 *curr_ptr = mc_data; - - while (bytes_left != 0) { - if (bytes_left > DRX_UCODE_MAX_BUF_SIZE) - bytes_to_comp = DRX_UCODE_MAX_BUF_SIZE; - else - bytes_to_comp = bytes_left; - - if (demod->my_access_funct-> - read_block_func(dev_addr, - curr_addr, - (u16)bytes_to_comp, - (u8 *)mc_data_buffer, - 0x0000)) { - pr_err("error reading firmware at pos %u\n", - (unsigned)(mc_data - mc_data_init)); - return -EIO; - } - - result =drxbsp_hst_memcmp(curr_ptr, - mc_data_buffer, - bytes_to_comp); - - if (result) { - pr_err("error verifying firmware at pos %u\n", - (unsigned)(mc_data - mc_data_init)); - return -EIO; - } - - curr_addr += ((dr_xaddr_t)(bytes_to_comp / 2)); - curr_ptr =&(curr_ptr[bytes_to_comp]); - bytes_left -=((u32) bytes_to_comp); - } - break; - } - default: - return -EINVAL; - break; - - } - mc_data += mc_block_nr_bytes; - } - - return 0; - -release: - release_firmware(demod->firmware); - demod->firmware = NULL; - - return rc; -} - -/*============================================================================*/ - -/** - * drx_ctrl_version - Build list of version information. - * @demod: A pointer to a demodulator instance. - * @version_list: Pointer to linked list of versions. - * - * This function returns: - * 0: Version information stored in version_list - * -EINVAL: Invalid arguments. - */ -static int drx_ctrl_version(struct drx_demod_instance *demod, - struct drx_version_list **version_list) -{ - static char drx_driver_core_module_name[] = "Core driver"; - static char drx_driver_core_version_text[] = - DRX_VERSIONSTRING(VERSION_MAJOR, VERSION_MINOR, VERSION_PATCH); - - static struct drx_version drx_driver_core_version; - static struct drx_version_list drx_driver_core_version_list; - - struct drx_version_list *demod_version_list = NULL; - int return_status = -EIO; - - /* Check arguments */ - if (version_list == NULL) - return -EINVAL; - - /* Get version info list from demod */ - return_status = (*(demod->my_demod_funct->ctrl_func)) (demod, - DRX_CTRL_VERSION, - (void *) - &demod_version_list); - - /* Always fill in the information of the driver SW . */ - drx_driver_core_version.module_type = DRX_MODULE_DRIVERCORE; - drx_driver_core_version.module_name = drx_driver_core_module_name; - drx_driver_core_version.v_major = VERSION_MAJOR; - drx_driver_core_version.v_minor = VERSION_MINOR; - drx_driver_core_version.v_patch = VERSION_PATCH; - drx_driver_core_version.v_string = drx_driver_core_version_text; - - drx_driver_core_version_list.version = &drx_driver_core_version; - drx_driver_core_version_list.next = (struct drx_version_list *) (NULL); - - if ((return_status == 0) && (demod_version_list != NULL)) { - /* Append versioninfo from driver to versioninfo from demod */ - /* Return version info in "bottom-up" order. This way, multiple - devices can be handled without using malloc. */ - struct drx_version_list *current_list_element = demod_version_list; - while (current_list_element->next != NULL) - current_list_element = current_list_element->next; - current_list_element->next = &drx_driver_core_version_list; - - *version_list = demod_version_list; - } else { - /* Just return versioninfo from driver */ - *version_list = &drx_driver_core_version_list; - } - - return 0; -} - -/* - * Exported functions - */ - -/** - * drx_open - Open a demodulator instance. - * @demod: A pointer to a demodulator instance. - * - * This function returns: - * 0: Opened demod instance with succes. - * -EIO: Driver not initialized or unable to initialize - * demod. - * -EINVAL: Demod instance has invalid content. - * - */ - -int drx_open(struct drx_demod_instance *demod) -{ - int status = 0; - - if ((demod == NULL) || - (demod->my_demod_funct == NULL) || - (demod->my_common_attr == NULL) || - (demod->my_ext_attr == NULL) || - (demod->my_i2c_dev_addr == NULL) || - (demod->my_common_attr->is_opened)) { - return -EINVAL; - } - - status = (*(demod->my_demod_funct->open_func)) (demod); - - if (status == 0) - demod->my_common_attr->is_opened = true; - - return status; -} - -/*============================================================================*/ - -/** - * drx_close - Close device - * @demod: A pointer to a demodulator instance. - * - * Free resources occupied by device instance. - * Put device into sleep mode. - * - * This function returns: - * 0: Closed demod instance with succes. - * -EIO: Driver not initialized or error during close - * demod. - * -EINVAL: Demod instance has invalid content. - */ -int drx_close(struct drx_demod_instance *demod) -{ - int status = 0; - - if ((demod == NULL) || - (demod->my_demod_funct == NULL) || - (demod->my_common_attr == NULL) || - (demod->my_ext_attr == NULL) || - (demod->my_i2c_dev_addr == NULL) || - (!demod->my_common_attr->is_opened)) { - return -EINVAL; - } - - status = (*(demod->my_demod_funct->close_func)) (demod); - - DRX_ATTR_ISOPENED(demod) = false; - - return status; -} -/** - * drx_ctrl - Control the device. - * @demod: A pointer to a demodulator instance. - * @ctrl: Reference to desired control function. - * @ctrl_data: Pointer to data structure for control function. - * - * Data needed or returned by the control function is stored in ctrl_data. - * - * This function returns: - * 0: Control function completed successfully. - * -EIO: Driver not initialized or error during control demod. - * -EINVAL: Demod instance or ctrl_data has invalid content. - * -ENOTSUPP: Specified control function is not available. - */ - -int drx_ctrl(struct drx_demod_instance *demod, u32 ctrl, void *ctrl_data) -{ - int status = -EIO; - - if ((demod == NULL) || - (demod->my_demod_funct == NULL) || - (demod->my_common_attr == NULL) || - (demod->my_ext_attr == NULL) || (demod->my_i2c_dev_addr == NULL) - ) { - return -EINVAL; - } - - if (((!demod->my_common_attr->is_opened) && - (ctrl != DRX_CTRL_PROBE_DEVICE) && (ctrl != DRX_CTRL_VERSION)) - ) { - return -EINVAL; - } - - if ((DRX_ISPOWERDOWNMODE(demod->my_common_attr->current_power_mode) && - (ctrl != DRX_CTRL_POWER_MODE) && - (ctrl != DRX_CTRL_PROBE_DEVICE) && - (ctrl != DRX_CTRL_NOP) && (ctrl != DRX_CTRL_VERSION) - ) - ) { - return -ENOTSUPP; - } - - /* Fixed control functions */ - switch (ctrl) { - /*======================================================================*/ - case DRX_CTRL_NOP: - /* No operation */ - return 0; - break; - - /*======================================================================*/ - case DRX_CTRL_VERSION: - return drx_ctrl_version(demod, (struct drx_version_list **)ctrl_data); - break; - - /*======================================================================*/ - default: - /* Do nothing */ - break; - } - - /* Virtual functions */ - /* First try calling function from derived class */ - status = (*(demod->my_demod_funct->ctrl_func)) (demod, ctrl, ctrl_data); - if (status == -ENOTSUPP) { - /* Now try calling a the base class function */ - switch (ctrl) { - /*===================================================================*/ - case DRX_CTRL_LOAD_UCODE: - return drx_ctrl_u_code(demod, - (struct drxu_code_info *)ctrl_data, - UCODE_UPLOAD); - break; - - /*===================================================================*/ - case DRX_CTRL_VERIFY_UCODE: - { - return drx_ctrl_u_code(demod, - (struct drxu_code_info *)ctrl_data, - UCODE_VERIFY); - } - break; - - /*===================================================================*/ - default: - pr_err("control %d not supported\n", ctrl); - return -ENOTSUPP; - } - } else { - return status; - } - - return 0; -} diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index b1ad26b..a06c45d 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -39,6 +39,7 @@ INCLUDE FILES #include "drxj.h" #include "drxj_map.h" +#include "drx_driver.h" /*============================================================================*/ /*=== DEFINES ================================================================*/ @@ -309,6 +310,40 @@ DEFINES #define DRX_UIO_MODE_FIRMWARE_SMA DRX_UIO_MODE_FIRMWARE0 #define DRX_UIO_MODE_FIRMWARE_SAW DRX_UIO_MODE_FIRMWARE1 +/* + * MICROCODE RELATED DEFINES + */ + +/* Magic word for checking correct Endianess of microcode data */ +#define DRX_UCODE_MAGIC_WORD ((((u16)'H')<<8)+((u16)'L')) + +/* CRC flag in ucode header, flags field. */ +#define DRX_UCODE_CRC_FLAG (0x0001) + +/* + * Maximum size of buffer used to verify the microcode. + * Must be an even number + */ +#define DRX_UCODE_MAX_BUF_SIZE (DRXDAP_MAX_RCHUNKSIZE) + +#if DRX_UCODE_MAX_BUF_SIZE & 1 +#error DRX_UCODE_MAX_BUF_SIZE must be an even number +#endif + +/* + * Power mode macros + */ + +#define DRX_ISPOWERDOWNMODE(mode) ((mode == DRX_POWER_MODE_9) || \ + (mode == DRX_POWER_MODE_10) || \ + (mode == DRX_POWER_MODE_11) || \ + (mode == DRX_POWER_MODE_12) || \ + (mode == DRX_POWER_MODE_13) || \ + (mode == DRX_POWER_MODE_14) || \ + (mode == DRX_POWER_MODE_15) || \ + (mode == DRX_POWER_MODE_16) || \ + (mode == DRX_POWER_DOWN)) + #ifdef DRXJ_SPLIT_UCODE_UPLOAD /*============================================================================*/ /*=== MICROCODE RELATED DEFINES ==============================================*/ @@ -1050,20 +1085,25 @@ struct drxj_hi_cmd { u16 param6; }; -#ifdef DRXJ_SPLIT_UCODE_UPLOAD /*============================================================================*/ /*=== MICROCODE RELATED STRUCTURES ===========================================*/ /*============================================================================*/ +/** + * struct drxu_code_block_hdr - Structure of the microcode block headers + * + * @addr: Destination address of the data in this block + * @size: Size of the block data following this header counted in + * 16 bits words + * @CRC: CRC value of the data block, only valid if CRC flag is + * set. + */ struct drxu_code_block_hdr { u32 addr; u16 size; - u16 flags; /* bit[15..2]=reserved, - bit[1]= compression on/off - bit[0]= CRC on/off */ + u16 flags; u16 CRC; }; -#endif /* DRXJ_SPLIT_UCODE_UPLOAD */ /*----------------------------------------------------------------------------- FUNCTIONS @@ -20607,3 +20647,550 @@ drxj_ctrl(struct drx_demod_instance *demod, u32 ctrl, void *ctrl_data) } return 0; } + +/* + * Microcode related functions + */ + +/** + * drx_u_code_compute_crc - Compute CRC of block of microcode data. + * @block_data: Pointer to microcode data. + * @nr_words: Size of microcode block (number of 16 bits words). + * + * returns The computed CRC residue. + */ +static u16 drx_u_code_compute_crc(u8 *block_data, u16 nr_words) +{ + u16 i = 0; + u16 j = 0; + u32 crc_word = 0; + u32 carry = 0; + + while (i < nr_words) { + crc_word |= (u32)be16_to_cpu(*(u32 *)(block_data)); + for (j = 0; j < 16; j++) { + crc_word <<= 1; + if (carry != 0) + crc_word ^= 0x80050000UL; + carry = crc_word & 0x80000000UL; + } + i++; + block_data += (sizeof(u16)); + } + return (u16)(crc_word >> 16); +} + +/** + * drx_check_firmware - checks if the loaded firmware is valid + * + * @demod: demod structure + * @mc_data: pointer to the start of the firmware + * @size: firmware size + */ +static int drx_check_firmware(struct drx_demod_instance *demod, u8 *mc_data, + unsigned size) +{ + struct drxu_code_block_hdr block_hdr; + int i; + unsigned count = 2 * sizeof(u16); + u32 mc_dev_type, mc_version, mc_base_version; + u16 mc_nr_of_blks = be16_to_cpu(*(u32 *)(mc_data + sizeof(u16))); + + /* + * Scan microcode blocks first for version info + * and firmware check + */ + + /* Clear version block */ + DRX_ATTR_MCRECORD(demod).aux_type = 0; + DRX_ATTR_MCRECORD(demod).mc_dev_type = 0; + DRX_ATTR_MCRECORD(demod).mc_version = 0; + DRX_ATTR_MCRECORD(demod).mc_base_version = 0; + + for (i = 0; i < mc_nr_of_blks; i++) { + if (count + 3 * sizeof(u16) + sizeof(u32) > size) + goto eof; + + /* Process block header */ + block_hdr.addr = be32_to_cpu(*(u32 *)(mc_data + count)); + count += sizeof(u32); + block_hdr.size = be16_to_cpu(*(u32 *)(mc_data + count)); + count += sizeof(u16); + block_hdr.flags = be16_to_cpu(*(u32 *)(mc_data + count)); + count += sizeof(u16); + block_hdr.CRC = be16_to_cpu(*(u32 *)(mc_data + count)); + count += sizeof(u16); + + pr_debug("%u: addr %u, size %u, flags 0x%04x, CRC 0x%04x\n", + count, block_hdr.addr, block_hdr.size, block_hdr.flags, + block_hdr.CRC); + + if (block_hdr.flags & 0x8) { + u8 *auxblk = ((void *)mc_data) + block_hdr.addr; + u16 auxtype; + + if (block_hdr.addr + sizeof(u16) > size) + goto eof; + + auxtype = be16_to_cpu(*(u32 *)(auxblk)); + + /* Aux block. Check type */ + if (DRX_ISMCVERTYPE(auxtype)) { + if (block_hdr.addr + 2 * sizeof(u16) + 2 * sizeof (u32) > size) + goto eof; + + auxblk += sizeof(u16); + mc_dev_type = be32_to_cpu(*(u32 *)(auxblk)); + auxblk += sizeof(u32); + mc_version = be32_to_cpu(*(u32 *)(auxblk)); + auxblk += sizeof(u32); + mc_base_version = be32_to_cpu(*(u32 *)(auxblk)); + + DRX_ATTR_MCRECORD(demod).aux_type = auxtype; + DRX_ATTR_MCRECORD(demod).mc_dev_type = mc_dev_type; + DRX_ATTR_MCRECORD(demod).mc_version = mc_version; + DRX_ATTR_MCRECORD(demod).mc_base_version = mc_base_version; + + pr_info("Firmware dev %x, ver %x, base ver %x\n", + mc_dev_type, mc_version, mc_base_version); + + } + } else if (count + block_hdr.size * sizeof(u16) > size) + goto eof; + + count += block_hdr.size * sizeof(u16); + } + return 0; +eof: + pr_err("Firmware is truncated at pos %u/%u\n", count, size); + return -EINVAL; +} + +/** + * drx_ctrl_u_code - Handle microcode upload or verify. + * @dev_addr: Address of device. + * @mc_info: Pointer to information about microcode data. + * @action: Either UCODE_UPLOAD or UCODE_VERIFY + * + * This function returns: + * 0: + * - In case of UCODE_UPLOAD: code is successfully uploaded. + * - In case of UCODE_VERIFY: image on device is equal to + * image provided to this control function. + * -EIO: + * - In case of UCODE_UPLOAD: I2C error. + * - In case of UCODE_VERIFY: I2C error or image on device + * is not equal to image provided to this control function. + * -EINVAL: + * - Invalid arguments. + * - Provided image is corrupt + */ +static int drx_ctrl_u_code(struct drx_demod_instance *demod, + struct drxu_code_info *mc_info, + enum drxu_code_action action) +{ + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + int rc; + u16 i = 0; + u16 mc_nr_of_blks = 0; + u16 mc_magic_word = 0; + const u8 *mc_data_init = NULL; + u8 *mc_data = NULL; + unsigned size; + char *mc_file = mc_info->mc_file; + + /* Check arguments */ + if (!mc_info || !mc_file) + return -EINVAL; + + if (!demod->firmware) { + const struct firmware *fw = NULL; + + rc = request_firmware(&fw, mc_file, demod->i2c->dev.parent); + if (rc < 0) { + pr_err("Couldn't read firmware %s\n", mc_file); + return -ENOENT; + } + demod->firmware = fw; + + if (demod->firmware->size < 2 * sizeof(u16)) { + rc = -EINVAL; + pr_err("Firmware is too short!\n"); + goto release; + } + + pr_info("Firmware %s, size %zu\n", + mc_file, demod->firmware->size); + } + + mc_data_init = demod->firmware->data; + size = demod->firmware->size; + + mc_data = (void *)mc_data_init; + /* Check data */ + mc_magic_word = be16_to_cpu(*(u32 *)(mc_data)); + mc_data += sizeof(u16); + mc_nr_of_blks = be16_to_cpu(*(u32 *)(mc_data)); + mc_data += sizeof(u16); + + if ((mc_magic_word != DRX_UCODE_MAGIC_WORD) || (mc_nr_of_blks == 0)) { + rc = -EINVAL; + pr_err("Firmware magic word doesn't match\n"); + goto release; + } + + if (action == UCODE_UPLOAD) { + rc = drx_check_firmware(demod, (u8 *)mc_data_init, size); + if (rc) + goto release; + + /* After scanning, validate the microcode. + It is also valid if no validation control exists. + */ + rc = drx_ctrl(demod, DRX_CTRL_VALIDATE_UCODE, NULL); + if (rc != 0 && rc != -ENOTSUPP) { + pr_err("Validate ucode not supported\n"); + return rc; + } + pr_info("Uploading firmware %s\n", mc_file); + } else if (action == UCODE_VERIFY) { + pr_info("Verifying if firmware upload was ok.\n"); + } + + /* Process microcode blocks */ + for (i = 0; i < mc_nr_of_blks; i++) { + struct drxu_code_block_hdr block_hdr; + u16 mc_block_nr_bytes = 0; + + /* Process block header */ + block_hdr.addr = be32_to_cpu(*(u32 *)(mc_data)); + mc_data += sizeof(u32); + block_hdr.size = be16_to_cpu(*(u32 *)(mc_data)); + mc_data += sizeof(u16); + block_hdr.flags = be16_to_cpu(*(u32 *)(mc_data)); + mc_data += sizeof(u16); + block_hdr.CRC = be16_to_cpu(*(u32 *)(mc_data)); + mc_data += sizeof(u16); + + pr_debug("%u: addr %u, size %u, flags 0x%04x, CRC 0x%04x\n", + (unsigned)(mc_data - mc_data_init), block_hdr.addr, + block_hdr.size, block_hdr.flags, block_hdr.CRC); + + /* Check block header on: + - data larger than 64Kb + - if CRC enabled check CRC + */ + if ((block_hdr.size > 0x7FFF) || + (((block_hdr.flags & DRX_UCODE_CRC_FLAG) != 0) && + (block_hdr.CRC != drx_u_code_compute_crc(mc_data, block_hdr.size))) + ) { + /* Wrong data ! */ + rc = -EINVAL; + pr_err("firmware CRC is wrong\n"); + goto release; + } + + if (!block_hdr.size) + continue; + + mc_block_nr_bytes = block_hdr.size * ((u16) sizeof(u16)); + + /* Perform the desired action */ + switch (action) { + case UCODE_UPLOAD: /* Upload microcode */ + if (demod->my_access_funct->write_block_func(dev_addr, + block_hdr.addr, + mc_block_nr_bytes, + mc_data, 0x0000)) { + rc = -EIO; + pr_err("error writing firmware at pos %u\n", + (unsigned)(mc_data - mc_data_init)); + goto release; + } + break; + case UCODE_VERIFY: { /* Verify uploaded microcode */ + int result = 0; + u8 mc_data_buffer[DRX_UCODE_MAX_BUF_SIZE]; + u32 bytes_to_comp = 0; + u32 bytes_left = mc_block_nr_bytes; + u32 curr_addr = block_hdr.addr; + u8 *curr_ptr = mc_data; + + while (bytes_left != 0) { + if (bytes_left > DRX_UCODE_MAX_BUF_SIZE) + bytes_to_comp = DRX_UCODE_MAX_BUF_SIZE; + else + bytes_to_comp = bytes_left; + + if (demod->my_access_funct-> + read_block_func(dev_addr, + curr_addr, + (u16)bytes_to_comp, + (u8 *)mc_data_buffer, + 0x0000)) { + pr_err("error reading firmware at pos %u\n", + (unsigned)(mc_data - mc_data_init)); + return -EIO; + } + + result =drxbsp_hst_memcmp(curr_ptr, + mc_data_buffer, + bytes_to_comp); + + if (result) { + pr_err("error verifying firmware at pos %u\n", + (unsigned)(mc_data - mc_data_init)); + return -EIO; + } + + curr_addr += ((dr_xaddr_t)(bytes_to_comp / 2)); + curr_ptr =&(curr_ptr[bytes_to_comp]); + bytes_left -=((u32) bytes_to_comp); + } + break; + } + default: + return -EINVAL; + break; + + } + mc_data += mc_block_nr_bytes; + } + + return 0; + +release: + release_firmware(demod->firmware); + demod->firmware = NULL; + + return rc; +} + +/*============================================================================*/ + +/** + * drx_ctrl_version - Build list of version information. + * @demod: A pointer to a demodulator instance. + * @version_list: Pointer to linked list of versions. + * + * This function returns: + * 0: Version information stored in version_list + * -EINVAL: Invalid arguments. + */ +static int drx_ctrl_version(struct drx_demod_instance *demod, + struct drx_version_list **version_list) +{ + static char drx_driver_core_module_name[] = "Core driver"; + static char drx_driver_core_version_text[] = + DRX_VERSIONSTRING(VERSION_MAJOR, VERSION_MINOR, VERSION_PATCH); + + static struct drx_version drx_driver_core_version; + static struct drx_version_list drx_driver_core_version_list; + + struct drx_version_list *demod_version_list = NULL; + int return_status = -EIO; + + /* Check arguments */ + if (version_list == NULL) + return -EINVAL; + + /* Get version info list from demod */ + return_status = (*(demod->my_demod_funct->ctrl_func)) (demod, + DRX_CTRL_VERSION, + (void *) + &demod_version_list); + + /* Always fill in the information of the driver SW . */ + drx_driver_core_version.module_type = DRX_MODULE_DRIVERCORE; + drx_driver_core_version.module_name = drx_driver_core_module_name; + drx_driver_core_version.v_major = VERSION_MAJOR; + drx_driver_core_version.v_minor = VERSION_MINOR; + drx_driver_core_version.v_patch = VERSION_PATCH; + drx_driver_core_version.v_string = drx_driver_core_version_text; + + drx_driver_core_version_list.version = &drx_driver_core_version; + drx_driver_core_version_list.next = (struct drx_version_list *) (NULL); + + if ((return_status == 0) && (demod_version_list != NULL)) { + /* Append versioninfo from driver to versioninfo from demod */ + /* Return version info in "bottom-up" order. This way, multiple + devices can be handled without using malloc. */ + struct drx_version_list *current_list_element = demod_version_list; + while (current_list_element->next != NULL) + current_list_element = current_list_element->next; + current_list_element->next = &drx_driver_core_version_list; + + *version_list = demod_version_list; + } else { + /* Just return versioninfo from driver */ + *version_list = &drx_driver_core_version_list; + } + + return 0; +} + +/* + * Exported functions + */ + +/** + * drx_open - Open a demodulator instance. + * @demod: A pointer to a demodulator instance. + * + * This function returns: + * 0: Opened demod instance with succes. + * -EIO: Driver not initialized or unable to initialize + * demod. + * -EINVAL: Demod instance has invalid content. + * + */ + +int drx_open(struct drx_demod_instance *demod) +{ + int status = 0; + + if ((demod == NULL) || + (demod->my_demod_funct == NULL) || + (demod->my_common_attr == NULL) || + (demod->my_ext_attr == NULL) || + (demod->my_i2c_dev_addr == NULL) || + (demod->my_common_attr->is_opened)) { + return -EINVAL; + } + + status = (*(demod->my_demod_funct->open_func)) (demod); + + if (status == 0) + demod->my_common_attr->is_opened = true; + + return status; +} + +/*============================================================================*/ + +/** + * drx_close - Close device + * @demod: A pointer to a demodulator instance. + * + * Free resources occupied by device instance. + * Put device into sleep mode. + * + * This function returns: + * 0: Closed demod instance with succes. + * -EIO: Driver not initialized or error during close + * demod. + * -EINVAL: Demod instance has invalid content. + */ +int drx_close(struct drx_demod_instance *demod) +{ + int status = 0; + + if ((demod == NULL) || + (demod->my_demod_funct == NULL) || + (demod->my_common_attr == NULL) || + (demod->my_ext_attr == NULL) || + (demod->my_i2c_dev_addr == NULL) || + (!demod->my_common_attr->is_opened)) { + return -EINVAL; + } + + status = (*(demod->my_demod_funct->close_func)) (demod); + + DRX_ATTR_ISOPENED(demod) = false; + + return status; +} +/** + * drx_ctrl - Control the device. + * @demod: A pointer to a demodulator instance. + * @ctrl: Reference to desired control function. + * @ctrl_data: Pointer to data structure for control function. + * + * Data needed or returned by the control function is stored in ctrl_data. + * + * This function returns: + * 0: Control function completed successfully. + * -EIO: Driver not initialized or error during control demod. + * -EINVAL: Demod instance or ctrl_data has invalid content. + * -ENOTSUPP: Specified control function is not available. + */ + +int drx_ctrl(struct drx_demod_instance *demod, u32 ctrl, void *ctrl_data) +{ + int status = -EIO; + + if ((demod == NULL) || + (demod->my_demod_funct == NULL) || + (demod->my_common_attr == NULL) || + (demod->my_ext_attr == NULL) || (demod->my_i2c_dev_addr == NULL) + ) { + return -EINVAL; + } + + if (((!demod->my_common_attr->is_opened) && + (ctrl != DRX_CTRL_PROBE_DEVICE) && (ctrl != DRX_CTRL_VERSION)) + ) { + return -EINVAL; + } + + if ((DRX_ISPOWERDOWNMODE(demod->my_common_attr->current_power_mode) && + (ctrl != DRX_CTRL_POWER_MODE) && + (ctrl != DRX_CTRL_PROBE_DEVICE) && + (ctrl != DRX_CTRL_NOP) && (ctrl != DRX_CTRL_VERSION) + ) + ) { + return -ENOTSUPP; + } + + /* Fixed control functions */ + switch (ctrl) { + /*======================================================================*/ + case DRX_CTRL_NOP: + /* No operation */ + return 0; + break; + + /*======================================================================*/ + case DRX_CTRL_VERSION: + return drx_ctrl_version(demod, (struct drx_version_list **)ctrl_data); + break; + + /*======================================================================*/ + default: + /* Do nothing */ + break; + } + + /* Virtual functions */ + /* First try calling function from derived class */ + status = (*(demod->my_demod_funct->ctrl_func)) (demod, ctrl, ctrl_data); + if (status == -ENOTSUPP) { + /* Now try calling a the base class function */ + switch (ctrl) { + /*===================================================================*/ + case DRX_CTRL_LOAD_UCODE: + return drx_ctrl_u_code(demod, + (struct drxu_code_info *)ctrl_data, + UCODE_UPLOAD); + break; + + /*===================================================================*/ + case DRX_CTRL_VERIFY_UCODE: + { + return drx_ctrl_u_code(demod, + (struct drxu_code_info *)ctrl_data, + UCODE_VERIFY); + } + break; + + /*===================================================================*/ + default: + pr_err("control %d not supported\n", ctrl); + return -ENOTSUPP; + } + } else { + return status; + } + + return 0; +} \ No newline at end of file -- cgit v1.1 From 5b60053cae8faa211c5e407ede1a1ee9110f3f26 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Fri, 24 Jan 2014 06:31:03 -0300 Subject: [media] drx-j: Avoid any regressions by preserving old behavior The version is initialized with zero at drx_driver.c. Keep it, in order to avoid the risk of causing any regression. While here, remove the drx_driver.h from drxj, as this is not required there. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drxj.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index a06c45d..b92ca90 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -39,7 +39,6 @@ INCLUDE FILES #include "drxj.h" #include "drxj_map.h" -#include "drx_driver.h" /*============================================================================*/ /*=== DEFINES ================================================================*/ @@ -20982,7 +20981,7 @@ static int drx_ctrl_version(struct drx_demod_instance *demod, { static char drx_driver_core_module_name[] = "Core driver"; static char drx_driver_core_version_text[] = - DRX_VERSIONSTRING(VERSION_MAJOR, VERSION_MINOR, VERSION_PATCH); + DRX_VERSIONSTRING(0, 0, 0); static struct drx_version drx_driver_core_version; static struct drx_version_list drx_driver_core_version_list; @@ -21003,9 +21002,9 @@ static int drx_ctrl_version(struct drx_demod_instance *demod, /* Always fill in the information of the driver SW . */ drx_driver_core_version.module_type = DRX_MODULE_DRIVERCORE; drx_driver_core_version.module_name = drx_driver_core_module_name; - drx_driver_core_version.v_major = VERSION_MAJOR; - drx_driver_core_version.v_minor = VERSION_MINOR; - drx_driver_core_version.v_patch = VERSION_PATCH; + drx_driver_core_version.v_major = 0; + drx_driver_core_version.v_minor = 0; + drx_driver_core_version.v_patch = 0; drx_driver_core_version.v_string = drx_driver_core_version_text; drx_driver_core_version_list.version = &drx_driver_core_version; -- cgit v1.1 From 30de0bfc764fe1661928eaad9faa20548c9921e2 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Fri, 24 Jan 2014 07:49:29 -0300 Subject: [media] drx-j: Remove duplicated firmware upload code Remove the duplicated firmware upload code that was commented inside drxj.c. This code is not used, and will not work anyway, as it doesn't download the firmware from userspace. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drxj.c | 388 ---------------------------- 1 file changed, 388 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index b92ca90..cea5b6d 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -343,56 +343,6 @@ DEFINES (mode == DRX_POWER_MODE_16) || \ (mode == DRX_POWER_DOWN)) -#ifdef DRXJ_SPLIT_UCODE_UPLOAD -/*============================================================================*/ -/*=== MICROCODE RELATED DEFINES ==============================================*/ -/*============================================================================*/ - -/** -* \def DRXJ_UCODE_MAGIC_WORD -* \brief Magic word for checking correct Endianess of microcode data. -* -*/ - -#ifndef DRXJ_UCODE_MAGIC_WORD -#define DRXJ_UCODE_MAGIC_WORD ((((u16)'H')<<8)+((u16)'L')) -#endif - -/** -* \def DRXJ_UCODE_CRC_FLAG -* \brief CRC flag in ucode header, flags field. -* -*/ - -#ifndef DRXJ_UCODE_CRC_FLAG -#define DRXJ_UCODE_CRC_FLAG (0x0001) -#endif - -/** -* \def DRXJ_UCODE_COMPRESSION_FLAG -* \brief Compression flag in ucode header, flags field. -* -*/ - -#ifndef DRXJ_UCODE_COMPRESSION_FLAG -#define DRXJ_UCODE_COMPRESSION_FLAG (0x0002) -#endif - -/** -* \def DRXJ_UCODE_MAX_BUF_SIZE -* \brief Maximum size of buffer used to verify the microcode.Must be an even number. -* -*/ - -#ifndef DRXJ_UCODE_MAX_BUF_SIZE -#define DRXJ_UCODE_MAX_BUF_SIZE (DRXDAP_MAX_RCHUNKSIZE) -#endif -#if DRXJ_UCODE_MAX_BUF_SIZE & 1 -#error DRXJ_UCODE_MAX_BUF_SIZE must be an even number -#endif - -#endif /* DRXJ_SPLIT_UCODE_UPLOAD */ - /* Pin safe mode macro */ #define DRXJ_PIN_SAFE_MODE 0x0000 /*============================================================================*/ @@ -704,9 +654,6 @@ struct drxj_data drxj_data_g = { /* false, * flagHDevSet */ /* (u16) 0xFFF, * rdsLastCount */ -/*#ifdef DRXJ_SPLIT_UCODE_UPLOAD - false, * flag_aud_mc_uploaded */ -/*#endif * DRXJ_SPLIT_UCODE_UPLOAD */ /* ATV configuartion */ 0UL, /* flags cfg changes */ /* shadow of ATV_TOP_EQU0__A */ @@ -1133,13 +1080,6 @@ ctrl_set_cfg_pre_saw(struct drx_demod_instance *demod, struct drxj_cfg_pre_saw * static int ctrl_set_cfg_afe_gain(struct drx_demod_instance *demod, struct drxj_cfg_afe_gain *afe_gain); -#ifdef DRXJ_SPLIT_UCODE_UPLOAD -static int -ctrl_u_code_upload(struct drx_demod_instance *demod, - struct drxu_code_info *mc_info, - enum drxu_code_actionaction, bool audio_mc_upload); -#endif /* DRXJ_SPLIT_UCODE_UPLOAD */ - /*============================================================================*/ /*============================================================================*/ /*== HELPER FUNCTIONS ==*/ @@ -1531,82 +1471,6 @@ static u32 frac(u32 N, u32 D, u16 RC) } #endif -#ifdef DRXJ_SPLIT_UCODE_UPLOAD -/*============================================================================*/ - -/** -* \fn u16 u_code_read16( u8 *addr) -* \brief Read a 16 bits word, expect big endian data. -* \return u16 The data read. -*/ -static u16 u_code_read16(u8 *addr) -{ - /* Works fo any host processor */ - - u16 word = 0; - - word = ((u16) addr[0]); - word <<= 8; - word |= ((u16) addr[1]); - - return word; -} - -/*============================================================================*/ - -/** -* \fn u32 u_code_read32( u8 *addr) -* \brief Read a 32 bits word, expect big endian data. -* \return u32 The data read. -*/ -static u32 u_code_read32(u8 *addr) -{ - /* Works fo any host processor */ - - u32 word = 0; - - word = ((u16) addr[0]); - word <<= 8; - word |= ((u16) addr[1]); - word <<= 8; - word |= ((u16) addr[2]); - word <<= 8; - word |= ((u16) addr[3]); - - return word; -} - -/*============================================================================*/ - -/** -* \fn u16 u_code_compute_crc (u8 *block_data, u16 nr_words) -* \brief Compute CRC of block of microcode data. -* \param block_data Pointer to microcode data. -* \param nr_words Size of microcode block (number of 16 bits words). -* \return u16 The computed CRC residu. -*/ -static u16 u_code_compute_crc(u8 *block_data, u16 nr_words) -{ - u16 i = 0; - u16 j = 0; - u32 crc_word = 0; - u32 carry = 0; - - while (i < nr_words) { - crc_word |= (u32) u_code_read16(block_data); - for (j = 0; j < 16; j++) { - crc_word <<= 1; - if (carry != 0) - crc_word ^= 0x80050000UL; - carry = crc_word & 0x80000000UL; - } - i++; - block_data += (sizeof(u16)); - } - return (u16)(crc_word >> 16); -} -#endif /* DRXJ_SPLIT_UCODE_UPLOAD */ - /** * \brief Values for NICAM prescaler gain. Computed from dB to integer * and rounded. For calc used formula: 16*10^(prescaleGain[dB]/20). @@ -12193,43 +12057,12 @@ trouble ? }; u16 cmd_result = 0; u16 cmd_param = 0; -#ifdef DRXJ_SPLIT_UCODE_UPLOAD - struct drxu_code_info ucode_info; - struct drx_common_attr *common_attr = NULL; -#endif /* DRXJ_SPLIT_UCODE_UPLOAD */ struct drxj_data *ext_attr = NULL; int rc; ext_attr = (struct drxj_data *) demod->my_ext_attr; dev_addr = demod->my_i2c_dev_addr; -#ifdef DRXJ_SPLIT_UCODE_UPLOAD - common_attr = demod->my_common_attr; - - /* Check if audio microcode is already uploaded */ - if (!(ext_attr->flag_aud_mc_uploaded)) { - ucode_info.mc_data = common_attr->microcode; - - /* Upload only audio microcode */ - rc = ctrl_u_code_upload(demod, &ucode_info, UCODE_UPLOAD, true); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - if (common_attr->verify_microcode == true) { - rc = ctrl_u_code_upload(demod, &ucode_info, UCODE_VERIFY, true); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - } - - /* Prevent uploading audio microcode again */ - ext_attr->flag_aud_mc_uploaded = true; - } -#endif /* DRXJ_SPLIT_UCODE_UPLOAD */ - rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); @@ -18913,194 +18746,6 @@ rw_error: return -EIO; } -#ifdef DRXJ_SPLIT_UCODE_UPLOAD -/*============================================================================*/ - -/** -* \fn int is_mc_block_audio() -* \brief Check if MC block is Audio or not Audio. -* \param addr Pointer to demodulator instance. -* \param audioUpload true if MC block is Audio - false if MC block not Audio -* \return bool. -*/ -bool is_mc_block_audio(u32 addr) -{ - if ((addr == AUD_XFP_PRAM_4K__A) || (addr == AUD_XDFP_PRAM_4K__A)) - return true; - - return false; -} - -/*============================================================================*/ - -/** -* \fn int ctrl_u_code_upload() -* \brief Handle Audio or !Audio part of microcode upload. -* \param demod Pointer to demodulator instance. -* \param mc_info Pointer to information about microcode data. -* \param action Either UCODE_UPLOAD or UCODE_VERIFY. -* \param upload_audio_mc true if Audio MC need to be uploaded. - false if !Audio MC need to be uploaded. -* \return int. -*/ -static int -ctrl_u_code_upload(struct drx_demod_instance *demod, - struct drxu_code_info *mc_info, - enum drxu_code_actionaction, bool upload_audio_mc) -{ - u16 i = 0; - u16 mc_nr_of_blks = 0; - u16 mc_magic_word = 0; - u8 *mc_data = (u8 *)(NULL); - struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); - struct drxj_data *ext_attr = (struct drxj_data *) (NULL); - int rc; - - dev_addr = demod->my_i2c_dev_addr; - ext_attr = (struct drxj_data *) demod->my_ext_attr; - - /* Check arguments */ - if (!mc_info || !mc_info->mc_data) { - return -EINVAL; - } - - mc_data = mc_info->mc_data; - - /* Check data */ - mc_magic_word = u_code_read16(mc_data); - mc_data += sizeof(u16); - mc_nr_of_blks = u_code_read16(mc_data); - mc_data += sizeof(u16); - - if ((mc_magic_word != DRXJ_UCODE_MAGIC_WORD) || (mc_nr_of_blks == 0)) { - /* wrong endianess or wrong data ? */ - return -EINVAL; - } - - /* Process microcode blocks */ - for (i = 0; i < mc_nr_of_blks; i++) { - struct drxu_code_block_hdr block_hdr; - u16 mc_block_nr_bytes = 0; - - /* Process block header */ - block_hdr.addr = u_code_read32(mc_data); - mc_data += sizeof(u32); - block_hdr.size = u_code_read16(mc_data); - mc_data += sizeof(u16); - block_hdr.flags = u_code_read16(mc_data); - mc_data += sizeof(u16); - block_hdr.CRC = u_code_read16(mc_data); - mc_data += sizeof(u16); - - /* Check block header on: - - no data - - data larger then 64Kb - - if CRC enabled check CRC - */ - if ((block_hdr.size == 0) || - (block_hdr.size > 0x7FFF) || - (((block_hdr.flags & DRXJ_UCODE_CRC_FLAG) != 0) && - (block_hdr.CRC != u_code_compute_crc(mc_data, block_hdr.size))) - ) { - /* Wrong data ! */ - return -EINVAL; - } - - mc_block_nr_bytes = block_hdr.size * sizeof(u16); - - /* Perform the desired action */ - /* Check which part of MC need to be uploaded - Audio or not Audio */ - if (is_mc_block_audio(block_hdr.addr) == upload_audio_mc) { - switch (action) { - /*===================================================================*/ - case UCODE_UPLOAD: - { - /* Upload microcode */ - if (demod->my_access_funct-> - write_block_func(dev_addr, - (dr_xaddr_t) block_hdr. - addr, mc_block_nr_bytes, - mc_data, - 0x0000) != - 0) { - return -EIO; - } - } - break; - - /*===================================================================*/ - case UCODE_VERIFY: - { - int result = 0; - u8 mc_data_buffer - [DRXJ_UCODE_MAX_BUF_SIZE]; - u32 bytes_to_compare = 0; - u32 bytes_left_to_compare = 0; - u32 curr_addr = (dr_xaddr_t) 0; - u8 *curr_ptr = NULL; - - bytes_left_to_compare = mc_block_nr_bytes; - curr_addr = block_hdr.addr; - curr_ptr = mc_data; - - while (bytes_left_to_compare != 0) { - if (bytes_left_to_compare > ((u32)DRXJ_UCODE_MAX_BUF_SIZE)) - bytes_to_compare = ((u32)DRXJ_UCODE_MAX_BUF_SIZE); - else - bytes_to_compare = bytes_left_to_compare; - - if (demod->my_access_funct-> - read_block_func(dev_addr, - curr_addr, - (u16) - bytes_to_compare, - (u8 *) - mc_data_buffer, - 0x0000) != - 0) { - return -EIO; - } - - result = - drxbsp_hst_memcmp(curr_ptr, - mc_data_buffer, - bytes_to_compare); - - if (result != 0) - return -EIO; - - curr_addr += - ((dr_xaddr_t) - (bytes_to_compare / 2)); - curr_ptr = - &(curr_ptr[bytes_to_compare]); - bytes_left_to_compare -= - ((u32) bytes_to_compare); - } /* while( bytes_to_compare > DRXJ_UCODE_MAX_BUF_SIZE ) */ - } - break; - - /*===================================================================*/ - default: - return -EINVAL; - break; - - } /* switch ( action ) */ - } - - /* if( is_mc_block_audio( block_hdr.addr ) == upload_audio_mc ) */ - /* Next block */ - mc_data += mc_block_nr_bytes; - } /* for( i = 0 ; iflag_aud_mc_uploaded = false; - - return 0; -} -#endif /* DRXJ_SPLIT_UCODE_UPLOAD */ - /*============================================================================*/ /*== CTRL Set/Get Config related functions ===================================*/ /*============================================================================*/ @@ -20263,34 +19908,17 @@ int drxj_open(struct drx_demod_instance *demod) common_attr->is_opened = true; ucode_info.mc_file = common_attr->microcode_file; -#ifdef DRXJ_SPLIT_UCODE_UPLOAD - /* Upload microcode without audio part */ - rc = ctrl_u_code_upload(demod, &ucode_info, UCODE_UPLOAD, false); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } -#else rc = drx_ctrl(demod, DRX_CTRL_LOAD_UCODE, &ucode_info); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } -#endif /* DRXJ_SPLIT_UCODE_UPLOAD */ if (common_attr->verify_microcode == true) { -#ifdef DRXJ_SPLIT_UCODE_UPLOAD - rc = ctrl_u_code_upload(demod, &ucode_info, UCODE_VERIFY, false); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } -#else rc = drx_ctrl(demod, DRX_CTRL_VERIFY_UCODE, &ucode_info); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } -#endif /* DRXJ_SPLIT_UCODE_UPLOAD */ } common_attr->is_opened = false; } @@ -20620,22 +20248,6 @@ drxj_ctrl(struct drx_demod_instance *demod, u32 ctrl, void *ctrl_data) (struct drxi2c_data *) ctrl_data); } break; -#ifdef DRXJ_SPLIT_UCODE_UPLOAD - case DRX_CTRL_LOAD_UCODE: - { - return ctrl_u_code_upload(demod, - (p_drxu_code_info_t) ctrl_data, - UCODE_UPLOAD, false); - } - break; - case DRX_CTRL_VERIFY_UCODE: - { - return ctrl_u_code_upload(demod, - (p_drxu_code_info_t) ctrl_data, - UCODE_VERIFY, false); - } - break; -#endif /* DRXJ_SPLIT_UCODE_UPLOAD */ case DRX_CTRL_VALIDATE_UCODE: { return ctrl_validate_u_code(demod); -- cgit v1.1 From dc5a91d49d147f47b2305ad76d67982462c5ac5f Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Fri, 24 Jan 2014 11:14:17 -0300 Subject: [media] drx-j: get rid of drx_ctrl This function is used only as an abstraction layer to call the two firmware functions. Remove it. As a bonus, the drx_ctrl_function is now unused and can be removed. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drx39xxj.c | 24 +-- drivers/media/dvb-frontends/drx39xyj/drx_driver.h | 3 - drivers/media/dvb-frontends/drx39xyj/drxj.c | 185 ++-------------------- 3 files changed, 28 insertions(+), 184 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c index 7a7a4a8..7e31661 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c @@ -45,7 +45,7 @@ static int drx39xxj_set_powerstate(struct dvb_frontend *fe, int enable) else power_mode = DRX_POWER_DOWN; - result = drx_ctrl(demod, DRX_CTRL_POWER_MODE, &power_mode); + result = drxj_ctrl(demod, DRX_CTRL_POWER_MODE, &power_mode); if (result != 0) { pr_err("Power state change failed\n"); return 0; @@ -64,7 +64,7 @@ static int drx39xxj_read_status(struct dvb_frontend *fe, fe_status_t *status) *status = 0; - result = drx_ctrl(demod, DRX_CTRL_LOCK_STATUS, &lock_status); + result = drxj_ctrl(demod, DRX_CTRL_LOCK_STATUS, &lock_status); if (result != 0) { pr_err("drx39xxj: could not get lock status!\n"); *status = 0; @@ -109,7 +109,7 @@ static int drx39xxj_read_ber(struct dvb_frontend *fe, u32 *ber) int result; struct drx_sig_quality sig_quality; - result = drx_ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); + result = drxj_ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); if (result != 0) { pr_err("drx39xxj: could not get ber!\n"); *ber = 0; @@ -128,7 +128,7 @@ static int drx39xxj_read_signal_strength(struct dvb_frontend *fe, int result; struct drx_sig_quality sig_quality; - result = drx_ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); + result = drxj_ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); if (result != 0) { pr_err("drx39xxj: could not get signal strength!\n"); *strength = 0; @@ -147,7 +147,7 @@ static int drx39xxj_read_snr(struct dvb_frontend *fe, u16 *snr) int result; struct drx_sig_quality sig_quality; - result = drx_ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); + result = drxj_ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); if (result != 0) { pr_err("drx39xxj: could not read snr!\n"); *snr = 0; @@ -165,7 +165,7 @@ static int drx39xxj_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) int result; struct drx_sig_quality sig_quality; - result = drx_ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); + result = drxj_ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); if (result != 0) { pr_err("drx39xxj: could not get uc blocks!\n"); *ucblocks = 0; @@ -244,7 +244,7 @@ static int drx39xxj_set_frontend(struct dvb_frontend *fe) if (standard != state->current_standard || state->powered_up == 0) { /* Set the standard (will be powered up if necessary */ - result = drx_ctrl(demod, DRX_CTRL_SET_STANDARD, &standard); + result = drxj_ctrl(demod, DRX_CTRL_SET_STANDARD, &standard); if (result != 0) { pr_err("Failed to set standard! result=%02x\n", result); @@ -261,7 +261,7 @@ static int drx39xxj_set_frontend(struct dvb_frontend *fe) channel.constellation = constellation; /* program channel */ - result = drx_ctrl(demod, DRX_CTRL_SET_CHANNEL, &channel); + result = drxj_ctrl(demod, DRX_CTRL_SET_CHANNEL, &channel); if (result != 0) { pr_err("Failed to set channel!\n"); return -EINVAL; @@ -269,7 +269,7 @@ static int drx39xxj_set_frontend(struct dvb_frontend *fe) /* Just for giggles, let's shut off the LNA again.... */ uio_data.uio = DRX_UIO1; uio_data.value = false; - result = drx_ctrl(demod, DRX_CTRL_UIO_WRITE, &uio_data); + result = drxj_ctrl(demod, DRX_CTRL_UIO_WRITE, &uio_data); if (result != 0) { pr_err("Failed to disable LNA!\n"); return 0; @@ -315,7 +315,7 @@ static int drx39xxj_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) return 0; } - result = drx_ctrl(demod, DRX_CTRL_I2C_BRIDGE, &i2c_gate_state); + result = drxj_ctrl(demod, DRX_CTRL_I2C_BRIDGE, &i2c_gate_state); if (result != 0) { pr_err("drx39xxj: could not open i2c gate [%d]\n", result); @@ -423,7 +423,7 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) uio_cfg.uio = DRX_UIO1; uio_cfg.mode = DRX_UIO_MODE_READWRITE; /* Configure user-I/O #3: enable read/write */ - result = drx_ctrl(demod, DRX_CTRL_UIO_CFG, &uio_cfg); + result = drxj_ctrl(demod, DRX_CTRL_UIO_CFG, &uio_cfg); if (result) { pr_err("Failed to setup LNA GPIO!\n"); goto error; @@ -431,7 +431,7 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) uio_data.uio = DRX_UIO1; uio_data.value = false; - result = drx_ctrl(demod, DRX_CTRL_UIO_WRITE, &uio_data); + result = drxj_ctrl(demod, DRX_CTRL_UIO_WRITE, &uio_data); if (result != 0) { pr_err("Failed to disable LNA!\n"); goto error; diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h index 343ae51..9ecf010 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h @@ -2468,9 +2468,6 @@ Exported FUNCTIONS int drx_close(struct drx_demod_instance *demod); - int drx_ctrl(struct drx_demod_instance *demod, - u32 ctrl, void *ctrl_data); - /*------------------------------------------------------------------------- THE END -------------------------------------------------------------------------*/ diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index cea5b6d..0836735 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -19797,6 +19797,10 @@ rw_error: /*============================================================================= ===== EXPORTED FUNCTIONS ====================================================*/ +static int drx_ctrl_u_code(struct drx_demod_instance *demod, + struct drxu_code_info *mc_info, + enum drxu_code_action action); + /** * \fn drxj_open() * \brief Open the demod instance, configure device, configure drxdriver @@ -19807,6 +19811,7 @@ rw_error: * rely on SCU or AUD ucode to be present. * */ + int drxj_open(struct drx_demod_instance *demod) { struct i2c_device_addr *dev_addr = NULL; @@ -19908,15 +19913,21 @@ int drxj_open(struct drx_demod_instance *demod) common_attr->is_opened = true; ucode_info.mc_file = common_attr->microcode_file; - rc = drx_ctrl(demod, DRX_CTRL_LOAD_UCODE, &ucode_info); + if (DRX_ISPOWERDOWNMODE(demod->my_common_attr->current_power_mode)) { + pr_err("Should powerup before loading the firmware."); + return -EINVAL; + } + + rc = drx_ctrl_u_code(demod, &ucode_info, UCODE_UPLOAD); if (rc != 0) { - pr_err("error %d\n", rc); + pr_err("error %d while uploading the firmware\n", rc); goto rw_error; } if (common_attr->verify_microcode == true) { - rc = drx_ctrl(demod, DRX_CTRL_VERIFY_UCODE, &ucode_info); + rc = drx_ctrl_u_code(demod, &ucode_info, UCODE_VERIFY); if (rc != 0) { - pr_err("error %d\n", rc); + pr_err("error %d while verifying the firmware\n", + rc); goto rw_error; } } @@ -20454,17 +20465,8 @@ static int drx_ctrl_u_code(struct drx_demod_instance *demod, rc = drx_check_firmware(demod, (u8 *)mc_data_init, size); if (rc) goto release; - - /* After scanning, validate the microcode. - It is also valid if no validation control exists. - */ - rc = drx_ctrl(demod, DRX_CTRL_VALIDATE_UCODE, NULL); - if (rc != 0 && rc != -ENOTSUPP) { - pr_err("Validate ucode not supported\n"); - return rc; - } pr_info("Uploading firmware %s\n", mc_file); - } else if (action == UCODE_VERIFY) { + } else { pr_info("Verifying if firmware upload was ok.\n"); } @@ -20579,67 +20581,6 @@ release: /*============================================================================*/ -/** - * drx_ctrl_version - Build list of version information. - * @demod: A pointer to a demodulator instance. - * @version_list: Pointer to linked list of versions. - * - * This function returns: - * 0: Version information stored in version_list - * -EINVAL: Invalid arguments. - */ -static int drx_ctrl_version(struct drx_demod_instance *demod, - struct drx_version_list **version_list) -{ - static char drx_driver_core_module_name[] = "Core driver"; - static char drx_driver_core_version_text[] = - DRX_VERSIONSTRING(0, 0, 0); - - static struct drx_version drx_driver_core_version; - static struct drx_version_list drx_driver_core_version_list; - - struct drx_version_list *demod_version_list = NULL; - int return_status = -EIO; - - /* Check arguments */ - if (version_list == NULL) - return -EINVAL; - - /* Get version info list from demod */ - return_status = (*(demod->my_demod_funct->ctrl_func)) (demod, - DRX_CTRL_VERSION, - (void *) - &demod_version_list); - - /* Always fill in the information of the driver SW . */ - drx_driver_core_version.module_type = DRX_MODULE_DRIVERCORE; - drx_driver_core_version.module_name = drx_driver_core_module_name; - drx_driver_core_version.v_major = 0; - drx_driver_core_version.v_minor = 0; - drx_driver_core_version.v_patch = 0; - drx_driver_core_version.v_string = drx_driver_core_version_text; - - drx_driver_core_version_list.version = &drx_driver_core_version; - drx_driver_core_version_list.next = (struct drx_version_list *) (NULL); - - if ((return_status == 0) && (demod_version_list != NULL)) { - /* Append versioninfo from driver to versioninfo from demod */ - /* Return version info in "bottom-up" order. This way, multiple - devices can be handled without using malloc. */ - struct drx_version_list *current_list_element = demod_version_list; - while (current_list_element->next != NULL) - current_list_element = current_list_element->next; - current_list_element->next = &drx_driver_core_version_list; - - *version_list = demod_version_list; - } else { - /* Just return versioninfo from driver */ - *version_list = &drx_driver_core_version_list; - } - - return 0; -} - /* * Exported functions */ @@ -20711,97 +20652,3 @@ int drx_close(struct drx_demod_instance *demod) return status; } -/** - * drx_ctrl - Control the device. - * @demod: A pointer to a demodulator instance. - * @ctrl: Reference to desired control function. - * @ctrl_data: Pointer to data structure for control function. - * - * Data needed or returned by the control function is stored in ctrl_data. - * - * This function returns: - * 0: Control function completed successfully. - * -EIO: Driver not initialized or error during control demod. - * -EINVAL: Demod instance or ctrl_data has invalid content. - * -ENOTSUPP: Specified control function is not available. - */ - -int drx_ctrl(struct drx_demod_instance *demod, u32 ctrl, void *ctrl_data) -{ - int status = -EIO; - - if ((demod == NULL) || - (demod->my_demod_funct == NULL) || - (demod->my_common_attr == NULL) || - (demod->my_ext_attr == NULL) || (demod->my_i2c_dev_addr == NULL) - ) { - return -EINVAL; - } - - if (((!demod->my_common_attr->is_opened) && - (ctrl != DRX_CTRL_PROBE_DEVICE) && (ctrl != DRX_CTRL_VERSION)) - ) { - return -EINVAL; - } - - if ((DRX_ISPOWERDOWNMODE(demod->my_common_attr->current_power_mode) && - (ctrl != DRX_CTRL_POWER_MODE) && - (ctrl != DRX_CTRL_PROBE_DEVICE) && - (ctrl != DRX_CTRL_NOP) && (ctrl != DRX_CTRL_VERSION) - ) - ) { - return -ENOTSUPP; - } - - /* Fixed control functions */ - switch (ctrl) { - /*======================================================================*/ - case DRX_CTRL_NOP: - /* No operation */ - return 0; - break; - - /*======================================================================*/ - case DRX_CTRL_VERSION: - return drx_ctrl_version(demod, (struct drx_version_list **)ctrl_data); - break; - - /*======================================================================*/ - default: - /* Do nothing */ - break; - } - - /* Virtual functions */ - /* First try calling function from derived class */ - status = (*(demod->my_demod_funct->ctrl_func)) (demod, ctrl, ctrl_data); - if (status == -ENOTSUPP) { - /* Now try calling a the base class function */ - switch (ctrl) { - /*===================================================================*/ - case DRX_CTRL_LOAD_UCODE: - return drx_ctrl_u_code(demod, - (struct drxu_code_info *)ctrl_data, - UCODE_UPLOAD); - break; - - /*===================================================================*/ - case DRX_CTRL_VERIFY_UCODE: - { - return drx_ctrl_u_code(demod, - (struct drxu_code_info *)ctrl_data, - UCODE_VERIFY); - } - break; - - /*===================================================================*/ - default: - pr_err("control %d not supported\n", ctrl); - return -ENOTSUPP; - } - } else { - return status; - } - - return 0; -} \ No newline at end of file -- cgit v1.1 From b78359a6894ac3451bec3fde5d0499fba87b8b67 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Fri, 24 Jan 2014 12:21:17 -0300 Subject: [media] drx-j: get rid of the remaining drx generic functions Get rid of drx_open and drx_close, as those are just wrapper functions to drxj_open/drxj_close. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drx39xxj.c | 2 +- drivers/media/dvb-frontends/drx39xyj/drx_driver.h | 25 ----- drivers/media/dvb-frontends/drx39xyj/drxj.c | 108 +++++----------------- 3 files changed, 23 insertions(+), 112 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c index 7e31661..aae9e7c 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c @@ -413,7 +413,7 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) demod->my_tuner = NULL; demod->i2c = i2c; - result = drx_open(demod); + result = drxj_open(demod); if (result != 0) { pr_err("DRX open failed! Aborting\n"); goto error; diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h index 9ecf010..b9ba48f 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h @@ -2013,28 +2013,11 @@ struct drx_reg_dump { struct drx_demod_instance; - typedef int(*drx_open_func_t) (struct drx_demod_instance *demod); - typedef int(*drx_close_func_t) (struct drx_demod_instance *demod); - typedef int(*drx_ctrl_func_t) (struct drx_demod_instance *demod, - u32 ctrl, - void *ctrl_data); - -/** -* \struct struct drx_demod_func * \brief A stucture containing all functions of a demodulator. -*/ - struct drx_demod_func { - u32 type_id; /**< Device type identifier. */ - drx_open_func_t open_func; /**< Pointer to Open() function. */ - drx_close_func_t close_func;/**< Pointer to Close() function. */ - drx_ctrl_func_t ctrl_func; /**< Pointer to Ctrl() function. */}; - /** * \struct struct drx_demod_instance * \brief Top structure of demodulator instance. */ struct drx_demod_instance { /* type specific demodulator data */ - struct drx_demod_func *my_demod_funct; - /**< demodulator functions */ struct drx_access_func *my_access_funct; /**< data access protocol functions */ struct tuner_instance *my_tuner; @@ -2461,14 +2444,6 @@ Access macros #define DRX_ISDVBTSTD(std) ((std) == DRX_STANDARD_DVBT) /*------------------------------------------------------------------------- -Exported FUNCTIONS --------------------------------------------------------------------------*/ - - int drx_open(struct drx_demod_instance *demod); - - int drx_close(struct drx_demod_instance *demod); - -/*------------------------------------------------------------------------- THE END -------------------------------------------------------------------------*/ #endif /* __DRXDRIVER_H__ */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index 0836735..9bcd24b 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -586,17 +586,6 @@ struct drx_access_func drx_dap_drxj_funct_g = { drxj_dap_read_modify_write_reg32, /* Not supported */ }; -/** -* /var DRXJ_Func_g -* /brief The driver functions of the drxj -*/ -struct drx_demod_func drxj_functions_g = { - DRXJ_TYPE_ID, - drxj_open, - drxj_close, - drxj_ctrl -}; - struct drxj_data drxj_data_g = { false, /* has_lna : true if LNA (aka PGA) present */ false, /* has_oob : true if OOB supported */ @@ -927,7 +916,6 @@ struct drx_common_attr drxj_default_comm_attr_g = { * \brief Default drxj demodulator instance. */ struct drx_demod_instance drxj_default_demod_g = { - &drxj_functions_g, /* demod functions */ &DRXJ_DAP, /* data access protocol functions */ NULL, /* tuner instance */ &drxj_default_addr_g, /* i2c address & device id */ @@ -19822,6 +19810,15 @@ int drxj_open(struct drx_demod_instance *demod) struct drx_cfg_mpeg_output cfg_mpeg_output; int rc; + + if ((demod == NULL) || + (demod->my_common_attr == NULL) || + (demod->my_ext_attr == NULL) || + (demod->my_i2c_dev_addr == NULL) || + (demod->my_common_attr->is_opened)) { + return -EINVAL; + } + /* Check arguments */ if (demod->my_ext_attr == NULL) return -EINVAL; @@ -20020,6 +20017,7 @@ int drxj_open(struct drx_demod_instance *demod) /* refresh the audio data structure with default */ ext_attr->aud_data = drxj_default_aud_data_g; + demod->my_common_attr->is_opened = true; return 0; rw_error: common_attr->is_opened = false; @@ -20040,6 +20038,14 @@ int drxj_close(struct drx_demod_instance *demod) int rc; enum drx_power_mode power_mode = DRX_POWER_UP; + if ((demod == NULL) || + (demod->my_common_attr == NULL) || + (demod->my_ext_attr == NULL) || + (demod->my_i2c_dev_addr == NULL) || + (!demod->my_common_attr->is_opened)) { + return -EINVAL; + } + /* power up */ rc = ctrl_power_mode(demod, &power_mode); if (rc != 0) { @@ -20084,8 +20090,12 @@ int drxj_close(struct drx_demod_instance *demod) goto rw_error; } + DRX_ATTR_ISOPENED(demod) = false; + return 0; rw_error: + DRX_ATTR_ISOPENED(demod) = false; + return -EIO; } @@ -20578,77 +20588,3 @@ release: return rc; } - -/*============================================================================*/ - -/* - * Exported functions - */ - -/** - * drx_open - Open a demodulator instance. - * @demod: A pointer to a demodulator instance. - * - * This function returns: - * 0: Opened demod instance with succes. - * -EIO: Driver not initialized or unable to initialize - * demod. - * -EINVAL: Demod instance has invalid content. - * - */ - -int drx_open(struct drx_demod_instance *demod) -{ - int status = 0; - - if ((demod == NULL) || - (demod->my_demod_funct == NULL) || - (demod->my_common_attr == NULL) || - (demod->my_ext_attr == NULL) || - (demod->my_i2c_dev_addr == NULL) || - (demod->my_common_attr->is_opened)) { - return -EINVAL; - } - - status = (*(demod->my_demod_funct->open_func)) (demod); - - if (status == 0) - demod->my_common_attr->is_opened = true; - - return status; -} - -/*============================================================================*/ - -/** - * drx_close - Close device - * @demod: A pointer to a demodulator instance. - * - * Free resources occupied by device instance. - * Put device into sleep mode. - * - * This function returns: - * 0: Closed demod instance with succes. - * -EIO: Driver not initialized or error during close - * demod. - * -EINVAL: Demod instance has invalid content. - */ -int drx_close(struct drx_demod_instance *demod) -{ - int status = 0; - - if ((demod == NULL) || - (demod->my_demod_funct == NULL) || - (demod->my_common_attr == NULL) || - (demod->my_ext_attr == NULL) || - (demod->my_i2c_dev_addr == NULL) || - (!demod->my_common_attr->is_opened)) { - return -EINVAL; - } - - status = (*(demod->my_demod_funct->close_func)) (demod); - - DRX_ATTR_ISOPENED(demod) = false; - - return status; -} -- cgit v1.1 From 190137478fb1e2487e8b7865c88c9747a16d0f9c Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Fri, 24 Jan 2014 12:25:04 -0300 Subject: [media] drx-j: move drx39xxj into drxj.c While drxj is already too big, moving the code there will make easier to get rid of the drxj_ctrl function. It will also help to detect and remove the unused functions, helping to remove lots of dead code there. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/Makefile | 2 +- drivers/media/dvb-frontends/drx39xyj/drx39xxj.c | 484 ------------------------ drivers/media/dvb-frontends/drx39xyj/drxj.c | 484 ++++++++++++++++++++++++ 3 files changed, 485 insertions(+), 485 deletions(-) delete mode 100644 drivers/media/dvb-frontends/drx39xyj/drx39xxj.c diff --git a/drivers/media/dvb-frontends/drx39xyj/Makefile b/drivers/media/dvb-frontends/drx39xyj/Makefile index d9ed094..7f073d4 100644 --- a/drivers/media/dvb-frontends/drx39xyj/Makefile +++ b/drivers/media/dvb-frontends/drx39xyj/Makefile @@ -1,4 +1,4 @@ -drx39xyj-objs := drx39xxj.o drx39xxj_dummy.o drxj.o drx_dap_fasi.o +drx39xyj-objs := drx39xxj_dummy.o drxj.o drx_dap_fasi.o obj-$(CONFIG_DVB_DRX39XYJ) += drx39xyj.o diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c deleted file mode 100644 index aae9e7c..0000000 --- a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c +++ /dev/null @@ -1,484 +0,0 @@ -/* - * Driver for Micronas DRX39xx family (drx3933j) - * - * Written by Devin Heitmueller - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.= - */ - -#define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__ - -#include -#include -#include -#include - -#include "dvb_frontend.h" -#include "drx39xxj.h" -#include "drx_driver.h" -#include "drxj.h" - -#define DRX39XX_MAIN_FIRMWARE "dvb-fe-drxj-mc-1.0.8.fw" - -static int drx39xxj_set_powerstate(struct dvb_frontend *fe, int enable) -{ - struct drx39xxj_state *state = fe->demodulator_priv; - struct drx_demod_instance *demod = state->demod; - int result; - enum drx_power_mode power_mode; - - if (enable) - power_mode = DRX_POWER_UP; - else - power_mode = DRX_POWER_DOWN; - - result = drxj_ctrl(demod, DRX_CTRL_POWER_MODE, &power_mode); - if (result != 0) { - pr_err("Power state change failed\n"); - return 0; - } - - state->powered_up = enable; - return 0; -} - -static int drx39xxj_read_status(struct dvb_frontend *fe, fe_status_t *status) -{ - struct drx39xxj_state *state = fe->demodulator_priv; - struct drx_demod_instance *demod = state->demod; - int result; - enum drx_lock_status lock_status; - - *status = 0; - - result = drxj_ctrl(demod, DRX_CTRL_LOCK_STATUS, &lock_status); - if (result != 0) { - pr_err("drx39xxj: could not get lock status!\n"); - *status = 0; - } - - switch (lock_status) { - case DRX_NEVER_LOCK: - *status = 0; - pr_err("drx says NEVER_LOCK\n"); - break; - case DRX_NOT_LOCKED: - *status = 0; - break; - case DRX_LOCK_STATE_1: - case DRX_LOCK_STATE_2: - case DRX_LOCK_STATE_3: - case DRX_LOCK_STATE_4: - case DRX_LOCK_STATE_5: - case DRX_LOCK_STATE_6: - case DRX_LOCK_STATE_7: - case DRX_LOCK_STATE_8: - case DRX_LOCK_STATE_9: - *status = FE_HAS_SIGNAL - | FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC; - break; - case DRX_LOCKED: - *status = FE_HAS_SIGNAL - | FE_HAS_CARRIER - | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK; - break; - default: - pr_err("Lock state unknown %d\n", lock_status); - } - - return 0; -} - -static int drx39xxj_read_ber(struct dvb_frontend *fe, u32 *ber) -{ - struct drx39xxj_state *state = fe->demodulator_priv; - struct drx_demod_instance *demod = state->demod; - int result; - struct drx_sig_quality sig_quality; - - result = drxj_ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); - if (result != 0) { - pr_err("drx39xxj: could not get ber!\n"); - *ber = 0; - return 0; - } - - *ber = sig_quality.post_reed_solomon_ber; - return 0; -} - -static int drx39xxj_read_signal_strength(struct dvb_frontend *fe, - u16 *strength) -{ - struct drx39xxj_state *state = fe->demodulator_priv; - struct drx_demod_instance *demod = state->demod; - int result; - struct drx_sig_quality sig_quality; - - result = drxj_ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); - if (result != 0) { - pr_err("drx39xxj: could not get signal strength!\n"); - *strength = 0; - return 0; - } - - /* 1-100% scaled to 0-65535 */ - *strength = (sig_quality.indicator * 65535 / 100); - return 0; -} - -static int drx39xxj_read_snr(struct dvb_frontend *fe, u16 *snr) -{ - struct drx39xxj_state *state = fe->demodulator_priv; - struct drx_demod_instance *demod = state->demod; - int result; - struct drx_sig_quality sig_quality; - - result = drxj_ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); - if (result != 0) { - pr_err("drx39xxj: could not read snr!\n"); - *snr = 0; - return 0; - } - - *snr = sig_quality.MER; - return 0; -} - -static int drx39xxj_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) -{ - struct drx39xxj_state *state = fe->demodulator_priv; - struct drx_demod_instance *demod = state->demod; - int result; - struct drx_sig_quality sig_quality; - - result = drxj_ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); - if (result != 0) { - pr_err("drx39xxj: could not get uc blocks!\n"); - *ucblocks = 0; - return 0; - } - - *ucblocks = sig_quality.packet_error; - return 0; -} - -static int drx39xxj_set_frontend(struct dvb_frontend *fe) -{ -#ifdef DJH_DEBUG - int i; -#endif - struct dtv_frontend_properties *p = &fe->dtv_property_cache; - struct drx39xxj_state *state = fe->demodulator_priv; - struct drx_demod_instance *demod = state->demod; - enum drx_standard standard = DRX_STANDARD_8VSB; - struct drx_channel channel; - int result; - struct drxuio_data uio_data; - static const struct drx_channel def_channel = { - /* frequency */ 0, - /* bandwidth */ DRX_BANDWIDTH_6MHZ, - /* mirror */ DRX_MIRROR_NO, - /* constellation */ DRX_CONSTELLATION_AUTO, - /* hierarchy */ DRX_HIERARCHY_UNKNOWN, - /* priority */ DRX_PRIORITY_UNKNOWN, - /* coderate */ DRX_CODERATE_UNKNOWN, - /* guard */ DRX_GUARD_UNKNOWN, - /* fftmode */ DRX_FFTMODE_UNKNOWN, - /* classification */ DRX_CLASSIFICATION_AUTO, - /* symbolrate */ 5057000, - /* interleavemode */ DRX_INTERLEAVEMODE_UNKNOWN, - /* ldpc */ DRX_LDPC_UNKNOWN, - /* carrier */ DRX_CARRIER_UNKNOWN, - /* frame mode */ DRX_FRAMEMODE_UNKNOWN - }; - u32 constellation = DRX_CONSTELLATION_AUTO; - - /* Bring the demod out of sleep */ - drx39xxj_set_powerstate(fe, 1); - - /* Now make the tuner do it's thing... */ - if (fe->ops.tuner_ops.set_params) { - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 1); - fe->ops.tuner_ops.set_params(fe); - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 0); - } - - switch (p->delivery_system) { - case SYS_ATSC: - standard = DRX_STANDARD_8VSB; - break; - case SYS_DVBC_ANNEX_B: - standard = DRX_STANDARD_ITU_B; - - switch (p->modulation) { - case QAM_64: - constellation = DRX_CONSTELLATION_QAM64; - break; - case QAM_256: - constellation = DRX_CONSTELLATION_QAM256; - break; - default: - constellation = DRX_CONSTELLATION_AUTO; - break; - } - break; - default: - return -EINVAL; - } - - if (standard != state->current_standard || state->powered_up == 0) { - /* Set the standard (will be powered up if necessary */ - result = drxj_ctrl(demod, DRX_CTRL_SET_STANDARD, &standard); - if (result != 0) { - pr_err("Failed to set standard! result=%02x\n", - result); - return -EINVAL; - } - state->powered_up = 1; - state->current_standard = standard; - } - - /* set channel parameters */ - channel = def_channel; - channel.frequency = p->frequency / 1000; - channel.bandwidth = DRX_BANDWIDTH_6MHZ; - channel.constellation = constellation; - - /* program channel */ - result = drxj_ctrl(demod, DRX_CTRL_SET_CHANNEL, &channel); - if (result != 0) { - pr_err("Failed to set channel!\n"); - return -EINVAL; - } - /* Just for giggles, let's shut off the LNA again.... */ - uio_data.uio = DRX_UIO1; - uio_data.value = false; - result = drxj_ctrl(demod, DRX_CTRL_UIO_WRITE, &uio_data); - if (result != 0) { - pr_err("Failed to disable LNA!\n"); - return 0; - } -#ifdef DJH_DEBUG - for (i = 0; i < 2000; i++) { - fe_status_t status; - drx39xxj_read_status(fe, &status); - pr_dbg("i=%d status=%d\n", i, status); - msleep(100); - i += 100; - } -#endif - - return 0; -} - -static int drx39xxj_sleep(struct dvb_frontend *fe) -{ - /* power-down the demodulator */ - return drx39xxj_set_powerstate(fe, 0); -} - -static int drx39xxj_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) -{ - struct drx39xxj_state *state = fe->demodulator_priv; - struct drx_demod_instance *demod = state->demod; - bool i2c_gate_state; - int result; - -#ifdef DJH_DEBUG - pr_dbg("i2c gate call: enable=%d state=%d\n", enable, - state->i2c_gate_open); -#endif - - if (enable) - i2c_gate_state = true; - else - i2c_gate_state = false; - - if (state->i2c_gate_open == enable) { - /* We're already in the desired state */ - return 0; - } - - result = drxj_ctrl(demod, DRX_CTRL_I2C_BRIDGE, &i2c_gate_state); - if (result != 0) { - pr_err("drx39xxj: could not open i2c gate [%d]\n", - result); - dump_stack(); - } else { - state->i2c_gate_open = enable; - } - return 0; -} - -static int drx39xxj_init(struct dvb_frontend *fe) -{ - /* Bring the demod out of sleep */ - drx39xxj_set_powerstate(fe, 1); - - return 0; -} - -static int drx39xxj_get_tune_settings(struct dvb_frontend *fe, - struct dvb_frontend_tune_settings *tune) -{ - tune->min_delay_ms = 1000; - return 0; -} - -static void drx39xxj_release(struct dvb_frontend *fe) -{ - struct drx39xxj_state *state = fe->demodulator_priv; - struct drx_demod_instance *demod = state->demod; - - kfree(demod->my_ext_attr); - kfree(demod->my_common_attr); - kfree(demod->my_i2c_dev_addr); - if (demod->firmware) - release_firmware(demod->firmware); - kfree(demod); - kfree(state); -} - -static struct dvb_frontend_ops drx39xxj_ops; - -struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) -{ - struct drx39xxj_state *state = NULL; - - struct i2c_device_addr *demod_addr = NULL; - struct drx_common_attr *demod_comm_attr = NULL; - struct drxj_data *demod_ext_attr = NULL; - struct drx_demod_instance *demod = NULL; - struct drxuio_cfg uio_cfg; - struct drxuio_data uio_data; - int result; - - /* allocate memory for the internal state */ - state = kzalloc(sizeof(struct drx39xxj_state), GFP_KERNEL); - if (state == NULL) - goto error; - - demod = kmalloc(sizeof(struct drx_demod_instance), GFP_KERNEL); - if (demod == NULL) - goto error; - - demod_addr = kmalloc(sizeof(struct i2c_device_addr), GFP_KERNEL); - if (demod_addr == NULL) - goto error; - memcpy(demod_addr, &drxj_default_addr_g, - sizeof(struct i2c_device_addr)); - - demod_comm_attr = kmalloc(sizeof(struct drx_common_attr), GFP_KERNEL); - if (demod_comm_attr == NULL) - goto error; - memcpy(demod_comm_attr, &drxj_default_comm_attr_g, - sizeof(struct drx_common_attr)); - - demod_ext_attr = kmalloc(sizeof(struct drxj_data), GFP_KERNEL); - if (demod_ext_attr == NULL) - goto error; - memcpy(demod_ext_attr, &drxj_data_g, sizeof(struct drxj_data)); - - /* setup the state */ - state->i2c = i2c; - state->demod = demod; - - /* setup the demod data */ - memcpy(demod, &drxj_default_demod_g, sizeof(struct drx_demod_instance)); - - demod->my_i2c_dev_addr = demod_addr; - demod->my_common_attr = demod_comm_attr; - demod->my_i2c_dev_addr->user_data = state; - demod->my_common_attr->microcode_file = DRX39XX_MAIN_FIRMWARE; - demod->my_common_attr->verify_microcode = true; - demod->my_common_attr->intermediate_freq = 5000; - demod->my_ext_attr = demod_ext_attr; - ((struct drxj_data *)demod_ext_attr)->uio_sma_tx_mode = DRX_UIO_MODE_READWRITE; - demod->my_tuner = NULL; - demod->i2c = i2c; - - result = drxj_open(demod); - if (result != 0) { - pr_err("DRX open failed! Aborting\n"); - goto error; - } - - /* Turn off the LNA */ - uio_cfg.uio = DRX_UIO1; - uio_cfg.mode = DRX_UIO_MODE_READWRITE; - /* Configure user-I/O #3: enable read/write */ - result = drxj_ctrl(demod, DRX_CTRL_UIO_CFG, &uio_cfg); - if (result) { - pr_err("Failed to setup LNA GPIO!\n"); - goto error; - } - - uio_data.uio = DRX_UIO1; - uio_data.value = false; - result = drxj_ctrl(demod, DRX_CTRL_UIO_WRITE, &uio_data); - if (result != 0) { - pr_err("Failed to disable LNA!\n"); - goto error; - } - - /* create dvb_frontend */ - memcpy(&state->frontend.ops, &drx39xxj_ops, - sizeof(struct dvb_frontend_ops)); - - state->frontend.demodulator_priv = state; - return &state->frontend; - -error: - kfree(demod_ext_attr); - kfree(demod_comm_attr); - kfree(demod_addr); - kfree(demod); - kfree(state); - - return NULL; -} -EXPORT_SYMBOL(drx39xxj_attach); - -static struct dvb_frontend_ops drx39xxj_ops = { - .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B }, - .info = { - .name = "Micronas DRX39xxj family Frontend", - .frequency_stepsize = 62500, - .frequency_min = 51000000, - .frequency_max = 858000000, - .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB - }, - - .init = drx39xxj_init, - .i2c_gate_ctrl = drx39xxj_i2c_gate_ctrl, - .sleep = drx39xxj_sleep, - .set_frontend = drx39xxj_set_frontend, - .get_tune_settings = drx39xxj_get_tune_settings, - .read_status = drx39xxj_read_status, - .read_ber = drx39xxj_read_ber, - .read_signal_strength = drx39xxj_read_signal_strength, - .read_snr = drx39xxj_read_snr, - .read_ucblocks = drx39xxj_read_ucblocks, - .release = drx39xxj_release, -}; - -MODULE_DESCRIPTION("Micronas DRX39xxj Frontend"); -MODULE_AUTHOR("Devin Heitmueller"); -MODULE_LICENSE("GPL"); -MODULE_FIRMWARE(DRX39XX_MAIN_FIRMWARE); diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index 9bcd24b..6356989 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -29,6 +29,24 @@ DRXJ specific implementation of DRX driver authors: Dragan Savic, Milos Nikolic, Mihajlo Katona, Tao Ding, Paul Janssen + + The Linux DVB Driver for Micronas DRX39xx family (drx3933j) was + written by Devin Heitmueller + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ /*----------------------------------------------------------------------------- @@ -37,6 +55,14 @@ INCLUDE FILES #define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__ +#include +#include +#include +#include + +#include "dvb_frontend.h" +#include "drx39xxj.h" + #include "drxj.h" #include "drxj_map.h" @@ -44,6 +70,8 @@ INCLUDE FILES /*=== DEFINES ================================================================*/ /*============================================================================*/ +#define DRX39XX_MAIN_FIRMWARE "dvb-fe-drxj-mc-1.0.8.fw" + /** * \brief Maximum u32 value. */ @@ -20588,3 +20616,459 @@ release: return rc; } + +/* + * The Linux DVB Driver for Micronas DRX39xx family (drx3933j) + * + * Written by Devin Heitmueller + */ + +static int drx39xxj_set_powerstate(struct dvb_frontend *fe, int enable) +{ + struct drx39xxj_state *state = fe->demodulator_priv; + struct drx_demod_instance *demod = state->demod; + int result; + enum drx_power_mode power_mode; + + if (enable) + power_mode = DRX_POWER_UP; + else + power_mode = DRX_POWER_DOWN; + + result = drxj_ctrl(demod, DRX_CTRL_POWER_MODE, &power_mode); + if (result != 0) { + pr_err("Power state change failed\n"); + return 0; + } + + state->powered_up = enable; + return 0; +} + +static int drx39xxj_read_status(struct dvb_frontend *fe, fe_status_t *status) +{ + struct drx39xxj_state *state = fe->demodulator_priv; + struct drx_demod_instance *demod = state->demod; + int result; + enum drx_lock_status lock_status; + + *status = 0; + + result = drxj_ctrl(demod, DRX_CTRL_LOCK_STATUS, &lock_status); + if (result != 0) { + pr_err("drx39xxj: could not get lock status!\n"); + *status = 0; + } + + switch (lock_status) { + case DRX_NEVER_LOCK: + *status = 0; + pr_err("drx says NEVER_LOCK\n"); + break; + case DRX_NOT_LOCKED: + *status = 0; + break; + case DRX_LOCK_STATE_1: + case DRX_LOCK_STATE_2: + case DRX_LOCK_STATE_3: + case DRX_LOCK_STATE_4: + case DRX_LOCK_STATE_5: + case DRX_LOCK_STATE_6: + case DRX_LOCK_STATE_7: + case DRX_LOCK_STATE_8: + case DRX_LOCK_STATE_9: + *status = FE_HAS_SIGNAL + | FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC; + break; + case DRX_LOCKED: + *status = FE_HAS_SIGNAL + | FE_HAS_CARRIER + | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK; + break; + default: + pr_err("Lock state unknown %d\n", lock_status); + } + + return 0; +} + +static int drx39xxj_read_ber(struct dvb_frontend *fe, u32 *ber) +{ + struct drx39xxj_state *state = fe->demodulator_priv; + struct drx_demod_instance *demod = state->demod; + int result; + struct drx_sig_quality sig_quality; + + result = drxj_ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); + if (result != 0) { + pr_err("drx39xxj: could not get ber!\n"); + *ber = 0; + return 0; + } + + *ber = sig_quality.post_reed_solomon_ber; + return 0; +} + +static int drx39xxj_read_signal_strength(struct dvb_frontend *fe, + u16 *strength) +{ + struct drx39xxj_state *state = fe->demodulator_priv; + struct drx_demod_instance *demod = state->demod; + int result; + struct drx_sig_quality sig_quality; + + result = drxj_ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); + if (result != 0) { + pr_err("drx39xxj: could not get signal strength!\n"); + *strength = 0; + return 0; + } + + /* 1-100% scaled to 0-65535 */ + *strength = (sig_quality.indicator * 65535 / 100); + return 0; +} + +static int drx39xxj_read_snr(struct dvb_frontend *fe, u16 *snr) +{ + struct drx39xxj_state *state = fe->demodulator_priv; + struct drx_demod_instance *demod = state->demod; + int result; + struct drx_sig_quality sig_quality; + + result = drxj_ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); + if (result != 0) { + pr_err("drx39xxj: could not read snr!\n"); + *snr = 0; + return 0; + } + + *snr = sig_quality.MER; + return 0; +} + +static int drx39xxj_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) +{ + struct drx39xxj_state *state = fe->demodulator_priv; + struct drx_demod_instance *demod = state->demod; + int result; + struct drx_sig_quality sig_quality; + + result = drxj_ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); + if (result != 0) { + pr_err("drx39xxj: could not get uc blocks!\n"); + *ucblocks = 0; + return 0; + } + + *ucblocks = sig_quality.packet_error; + return 0; +} + +static int drx39xxj_set_frontend(struct dvb_frontend *fe) +{ +#ifdef DJH_DEBUG + int i; +#endif + struct dtv_frontend_properties *p = &fe->dtv_property_cache; + struct drx39xxj_state *state = fe->demodulator_priv; + struct drx_demod_instance *demod = state->demod; + enum drx_standard standard = DRX_STANDARD_8VSB; + struct drx_channel channel; + int result; + struct drxuio_data uio_data; + static const struct drx_channel def_channel = { + /* frequency */ 0, + /* bandwidth */ DRX_BANDWIDTH_6MHZ, + /* mirror */ DRX_MIRROR_NO, + /* constellation */ DRX_CONSTELLATION_AUTO, + /* hierarchy */ DRX_HIERARCHY_UNKNOWN, + /* priority */ DRX_PRIORITY_UNKNOWN, + /* coderate */ DRX_CODERATE_UNKNOWN, + /* guard */ DRX_GUARD_UNKNOWN, + /* fftmode */ DRX_FFTMODE_UNKNOWN, + /* classification */ DRX_CLASSIFICATION_AUTO, + /* symbolrate */ 5057000, + /* interleavemode */ DRX_INTERLEAVEMODE_UNKNOWN, + /* ldpc */ DRX_LDPC_UNKNOWN, + /* carrier */ DRX_CARRIER_UNKNOWN, + /* frame mode */ DRX_FRAMEMODE_UNKNOWN + }; + u32 constellation = DRX_CONSTELLATION_AUTO; + + /* Bring the demod out of sleep */ + drx39xxj_set_powerstate(fe, 1); + + /* Now make the tuner do it's thing... */ + if (fe->ops.tuner_ops.set_params) { + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + fe->ops.tuner_ops.set_params(fe); + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 0); + } + + switch (p->delivery_system) { + case SYS_ATSC: + standard = DRX_STANDARD_8VSB; + break; + case SYS_DVBC_ANNEX_B: + standard = DRX_STANDARD_ITU_B; + + switch (p->modulation) { + case QAM_64: + constellation = DRX_CONSTELLATION_QAM64; + break; + case QAM_256: + constellation = DRX_CONSTELLATION_QAM256; + break; + default: + constellation = DRX_CONSTELLATION_AUTO; + break; + } + break; + default: + return -EINVAL; + } + + if (standard != state->current_standard || state->powered_up == 0) { + /* Set the standard (will be powered up if necessary */ + result = drxj_ctrl(demod, DRX_CTRL_SET_STANDARD, &standard); + if (result != 0) { + pr_err("Failed to set standard! result=%02x\n", + result); + return -EINVAL; + } + state->powered_up = 1; + state->current_standard = standard; + } + + /* set channel parameters */ + channel = def_channel; + channel.frequency = p->frequency / 1000; + channel.bandwidth = DRX_BANDWIDTH_6MHZ; + channel.constellation = constellation; + + /* program channel */ + result = drxj_ctrl(demod, DRX_CTRL_SET_CHANNEL, &channel); + if (result != 0) { + pr_err("Failed to set channel!\n"); + return -EINVAL; + } + /* Just for giggles, let's shut off the LNA again.... */ + uio_data.uio = DRX_UIO1; + uio_data.value = false; + result = drxj_ctrl(demod, DRX_CTRL_UIO_WRITE, &uio_data); + if (result != 0) { + pr_err("Failed to disable LNA!\n"); + return 0; + } +#ifdef DJH_DEBUG + for (i = 0; i < 2000; i++) { + fe_status_t status; + drx39xxj_read_status(fe, &status); + pr_dbg("i=%d status=%d\n", i, status); + msleep(100); + i += 100; + } +#endif + + return 0; +} + +static int drx39xxj_sleep(struct dvb_frontend *fe) +{ + /* power-down the demodulator */ + return drx39xxj_set_powerstate(fe, 0); +} + +static int drx39xxj_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) +{ + struct drx39xxj_state *state = fe->demodulator_priv; + struct drx_demod_instance *demod = state->demod; + bool i2c_gate_state; + int result; + +#ifdef DJH_DEBUG + pr_dbg("i2c gate call: enable=%d state=%d\n", enable, + state->i2c_gate_open); +#endif + + if (enable) + i2c_gate_state = true; + else + i2c_gate_state = false; + + if (state->i2c_gate_open == enable) { + /* We're already in the desired state */ + return 0; + } + + result = drxj_ctrl(demod, DRX_CTRL_I2C_BRIDGE, &i2c_gate_state); + if (result != 0) { + pr_err("drx39xxj: could not open i2c gate [%d]\n", + result); + dump_stack(); + } else { + state->i2c_gate_open = enable; + } + return 0; +} + +static int drx39xxj_init(struct dvb_frontend *fe) +{ + /* Bring the demod out of sleep */ + drx39xxj_set_powerstate(fe, 1); + + return 0; +} + +static int drx39xxj_get_tune_settings(struct dvb_frontend *fe, + struct dvb_frontend_tune_settings *tune) +{ + tune->min_delay_ms = 1000; + return 0; +} + +static void drx39xxj_release(struct dvb_frontend *fe) +{ + struct drx39xxj_state *state = fe->demodulator_priv; + struct drx_demod_instance *demod = state->demod; + + kfree(demod->my_ext_attr); + kfree(demod->my_common_attr); + kfree(demod->my_i2c_dev_addr); + if (demod->firmware) + release_firmware(demod->firmware); + kfree(demod); + kfree(state); +} + +static struct dvb_frontend_ops drx39xxj_ops; + +struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) +{ + struct drx39xxj_state *state = NULL; + + struct i2c_device_addr *demod_addr = NULL; + struct drx_common_attr *demod_comm_attr = NULL; + struct drxj_data *demod_ext_attr = NULL; + struct drx_demod_instance *demod = NULL; + struct drxuio_cfg uio_cfg; + struct drxuio_data uio_data; + int result; + + /* allocate memory for the internal state */ + state = kzalloc(sizeof(struct drx39xxj_state), GFP_KERNEL); + if (state == NULL) + goto error; + + demod = kmalloc(sizeof(struct drx_demod_instance), GFP_KERNEL); + if (demod == NULL) + goto error; + + demod_addr = kmalloc(sizeof(struct i2c_device_addr), GFP_KERNEL); + if (demod_addr == NULL) + goto error; + memcpy(demod_addr, &drxj_default_addr_g, + sizeof(struct i2c_device_addr)); + + demod_comm_attr = kmalloc(sizeof(struct drx_common_attr), GFP_KERNEL); + if (demod_comm_attr == NULL) + goto error; + memcpy(demod_comm_attr, &drxj_default_comm_attr_g, + sizeof(struct drx_common_attr)); + + demod_ext_attr = kmalloc(sizeof(struct drxj_data), GFP_KERNEL); + if (demod_ext_attr == NULL) + goto error; + memcpy(demod_ext_attr, &drxj_data_g, sizeof(struct drxj_data)); + + /* setup the state */ + state->i2c = i2c; + state->demod = demod; + + /* setup the demod data */ + memcpy(demod, &drxj_default_demod_g, sizeof(struct drx_demod_instance)); + + demod->my_i2c_dev_addr = demod_addr; + demod->my_common_attr = demod_comm_attr; + demod->my_i2c_dev_addr->user_data = state; + demod->my_common_attr->microcode_file = DRX39XX_MAIN_FIRMWARE; + demod->my_common_attr->verify_microcode = true; + demod->my_common_attr->intermediate_freq = 5000; + demod->my_ext_attr = demod_ext_attr; + ((struct drxj_data *)demod_ext_attr)->uio_sma_tx_mode = DRX_UIO_MODE_READWRITE; + demod->my_tuner = NULL; + demod->i2c = i2c; + + result = drxj_open(demod); + if (result != 0) { + pr_err("DRX open failed! Aborting\n"); + goto error; + } + + /* Turn off the LNA */ + uio_cfg.uio = DRX_UIO1; + uio_cfg.mode = DRX_UIO_MODE_READWRITE; + /* Configure user-I/O #3: enable read/write */ + result = drxj_ctrl(demod, DRX_CTRL_UIO_CFG, &uio_cfg); + if (result) { + pr_err("Failed to setup LNA GPIO!\n"); + goto error; + } + + uio_data.uio = DRX_UIO1; + uio_data.value = false; + result = drxj_ctrl(demod, DRX_CTRL_UIO_WRITE, &uio_data); + if (result != 0) { + pr_err("Failed to disable LNA!\n"); + goto error; + } + + /* create dvb_frontend */ + memcpy(&state->frontend.ops, &drx39xxj_ops, + sizeof(struct dvb_frontend_ops)); + + state->frontend.demodulator_priv = state; + return &state->frontend; + +error: + kfree(demod_ext_attr); + kfree(demod_comm_attr); + kfree(demod_addr); + kfree(demod); + kfree(state); + + return NULL; +} +EXPORT_SYMBOL(drx39xxj_attach); + +static struct dvb_frontend_ops drx39xxj_ops = { + .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B }, + .info = { + .name = "Micronas DRX39xxj family Frontend", + .frequency_stepsize = 62500, + .frequency_min = 51000000, + .frequency_max = 858000000, + .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB + }, + + .init = drx39xxj_init, + .i2c_gate_ctrl = drx39xxj_i2c_gate_ctrl, + .sleep = drx39xxj_sleep, + .set_frontend = drx39xxj_set_frontend, + .get_tune_settings = drx39xxj_get_tune_settings, + .read_status = drx39xxj_read_status, + .read_ber = drx39xxj_read_ber, + .read_signal_strength = drx39xxj_read_signal_strength, + .read_snr = drx39xxj_read_snr, + .read_ucblocks = drx39xxj_read_ucblocks, + .release = drx39xxj_release, +}; + +MODULE_DESCRIPTION("Micronas DRX39xxj Frontend"); +MODULE_AUTHOR("Devin Heitmueller"); +MODULE_LICENSE("GPL"); +MODULE_FIRMWARE(DRX39XX_MAIN_FIRMWARE); -- cgit v1.1 From b0baeb494e4e1707cdd690126fac1964581e8db2 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Fri, 24 Jan 2014 13:00:08 -0300 Subject: [media] drx-j: get rid of drxj_ctrl() With this change, we finally got rid of all abstraction layers on this driver. This patch also fixes the LNA GPIO settings, as the original code were using a wrong control name for it. This patch exposes the several functions that aren't used. Some of them are related to analog demod that might be used some day, but others will likely never be needed, as they don't fit on Linux media APIs. Latter patches will clean up this mess. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drx_driver.h | 55 ------ drivers/media/dvb-frontends/drx39xyj/drxj.c | 205 ++-------------------- 2 files changed, 12 insertions(+), 248 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h index b9ba48f..daa9027 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h @@ -782,61 +782,6 @@ enum drx_pilot_mode { DRX_PILOT_AUTO = DRX_AUTO /**< Autodetect Pilot */ }; -#define DRX_CTRL_BASE ((u32)0) - -#define DRX_CTRL_NOP (DRX_CTRL_BASE + 0)/**< No Operation */ -#define DRX_CTRL_PROBE_DEVICE (DRX_CTRL_BASE + 1)/**< Probe device */ - -#define DRX_CTRL_LOAD_UCODE (DRX_CTRL_BASE + 2)/**< Load microcode */ -#define DRX_CTRL_VERIFY_UCODE (DRX_CTRL_BASE + 3)/**< Verify microcode */ -#define DRX_CTRL_SET_CHANNEL (DRX_CTRL_BASE + 4)/**< Set channel */ -#define DRX_CTRL_GET_CHANNEL (DRX_CTRL_BASE + 5)/**< Get channel */ -#define DRX_CTRL_LOCK_STATUS (DRX_CTRL_BASE + 6)/**< Get lock status */ -#define DRX_CTRL_SIG_QUALITY (DRX_CTRL_BASE + 7)/**< Get signal quality */ -#define DRX_CTRL_SIG_STRENGTH (DRX_CTRL_BASE + 8)/**< Get signal strength*/ -#define DRX_CTRL_RF_POWER (DRX_CTRL_BASE + 9)/**< Get RF power */ -#define DRX_CTRL_CONSTEL (DRX_CTRL_BASE + 10)/**< Get constel point */ -#define DRX_CTRL_SCAN_INIT (DRX_CTRL_BASE + 11)/**< Initialize scan */ -#define DRX_CTRL_SCAN_NEXT (DRX_CTRL_BASE + 12)/**< Scan for next */ -#define DRX_CTRL_SCAN_STOP (DRX_CTRL_BASE + 13)/**< Stop scan */ -#define DRX_CTRL_TPS_INFO (DRX_CTRL_BASE + 14)/**< Get TPS info */ -#define DRX_CTRL_SET_CFG (DRX_CTRL_BASE + 15)/**< Set configuration */ -#define DRX_CTRL_GET_CFG (DRX_CTRL_BASE + 16)/**< Get configuration */ -#define DRX_CTRL_VERSION (DRX_CTRL_BASE + 17)/**< Get version info */ -#define DRX_CTRL_I2C_BRIDGE (DRX_CTRL_BASE + 18)/**< Open/close bridge */ -#define DRX_CTRL_SET_STANDARD (DRX_CTRL_BASE + 19)/**< Set demod std */ -#define DRX_CTRL_GET_STANDARD (DRX_CTRL_BASE + 20)/**< Get demod std */ -#define DRX_CTRL_SET_OOB (DRX_CTRL_BASE + 21)/**< Set OOB param */ -#define DRX_CTRL_GET_OOB (DRX_CTRL_BASE + 22)/**< Get OOB param */ -#define DRX_CTRL_AUD_SET_STANDARD (DRX_CTRL_BASE + 23)/**< Set audio param */ -#define DRX_CTRL_AUD_GET_STANDARD (DRX_CTRL_BASE + 24)/**< Get audio param */ -#define DRX_CTRL_AUD_GET_STATUS (DRX_CTRL_BASE + 25)/**< Read RDS */ -#define DRX_CTRL_AUD_BEEP (DRX_CTRL_BASE + 26)/**< Read RDS */ -#define DRX_CTRL_I2C_READWRITE (DRX_CTRL_BASE + 27)/**< Read/write I2C */ -#define DRX_CTRL_PROGRAM_TUNER (DRX_CTRL_BASE + 28)/**< Program tuner */ - - /* Professional */ -#define DRX_CTRL_MB_CFG (DRX_CTRL_BASE + 29) /**< */ -#define DRX_CTRL_MB_READ (DRX_CTRL_BASE + 30) /**< */ -#define DRX_CTRL_MB_WRITE (DRX_CTRL_BASE + 31) /**< */ -#define DRX_CTRL_MB_CONSTEL (DRX_CTRL_BASE + 32) /**< */ -#define DRX_CTRL_MB_MER (DRX_CTRL_BASE + 33) /**< */ - - /* Misc */ -#define DRX_CTRL_UIO_CFG DRX_CTRL_SET_UIO_CFG /**< Configure UIO */ -#define DRX_CTRL_SET_UIO_CFG (DRX_CTRL_BASE + 34) /**< Configure UIO */ -#define DRX_CTRL_GET_UIO_CFG (DRX_CTRL_BASE + 35) /**< Configure UIO */ -#define DRX_CTRL_UIO_READ (DRX_CTRL_BASE + 36) /**< Read from UIO */ -#define DRX_CTRL_UIO_WRITE (DRX_CTRL_BASE + 37) /**< Write to UIO */ -#define DRX_CTRL_READ_EVENTS (DRX_CTRL_BASE + 38) /**< Read events */ -#define DRX_CTRL_HDL_EVENTS (DRX_CTRL_BASE + 39) /**< Handle events */ -#define DRX_CTRL_POWER_MODE (DRX_CTRL_BASE + 40) /**< Set power mode */ -#define DRX_CTRL_LOAD_FILTER (DRX_CTRL_BASE + 41) /**< Load chan. filter */ -#define DRX_CTRL_VALIDATE_UCODE (DRX_CTRL_BASE + 42) /**< Validate ucode */ -#define DRX_CTRL_DUMP_REGISTERS (DRX_CTRL_BASE + 43) /**< Dump registers */ - -#define DRX_CTRL_MAX (DRX_CTRL_BASE + 44) /* never to be used */ - /** * enum drxu_code_action - indicate if firmware has to be uploaded or verified. * @UCODE_UPLOAD: Upload the microcode image to device diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index 6356989..66a83b8 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -20127,187 +20127,6 @@ rw_error: return -EIO; } -/*============================================================================*/ -/** -* \fn drxj_ctrl() -* \brief DRXJ specific control function -* \return Status_t Return status. -*/ -int -drxj_ctrl(struct drx_demod_instance *demod, u32 ctrl, void *ctrl_data) -{ - switch (ctrl) { - /*======================================================================*/ - case DRX_CTRL_SET_CHANNEL: - { - return ctrl_set_channel(demod, (struct drx_channel *)ctrl_data); - } - break; - /*======================================================================*/ - case DRX_CTRL_GET_CHANNEL: - { - return ctrl_get_channel(demod, (struct drx_channel *)ctrl_data); - } - break; - /*======================================================================*/ - case DRX_CTRL_SIG_QUALITY: - { - return ctrl_sig_quality(demod, - (struct drx_sig_quality *) ctrl_data); - } - break; - /*======================================================================*/ - case DRX_CTRL_SIG_STRENGTH: - { - return ctrl_sig_strength(demod, (u16 *)ctrl_data); - } - break; - /*======================================================================*/ - case DRX_CTRL_CONSTEL: - { - return ctrl_constel(demod, (struct drx_complex *)ctrl_data); - } - break; - /*======================================================================*/ - case DRX_CTRL_SET_CFG: - { - return ctrl_set_cfg(demod, (struct drx_cfg *)ctrl_data); - } - break; - /*======================================================================*/ - case DRX_CTRL_GET_CFG: - { - return ctrl_get_cfg(demod, (struct drx_cfg *)ctrl_data); - } - break; - /*======================================================================*/ - case DRX_CTRL_I2C_BRIDGE: - { - return ctrl_i2c_bridge(demod, (bool *)ctrl_data); - } - break; - /*======================================================================*/ - case DRX_CTRL_LOCK_STATUS: - { - return ctrl_lock_status(demod, - (enum drx_lock_status *)ctrl_data); - } - break; - /*======================================================================*/ - case DRX_CTRL_SET_STANDARD: - { - return ctrl_set_standard(demod, - (enum drx_standard *)ctrl_data); - } - break; - /*======================================================================*/ - case DRX_CTRL_GET_STANDARD: - { - return ctrl_get_standard(demod, - (enum drx_standard *)ctrl_data); - } - break; - /*======================================================================*/ - case DRX_CTRL_POWER_MODE: - { - return ctrl_power_mode(demod, (enum drx_power_mode *)ctrl_data); - } - break; - /*======================================================================*/ - case DRX_CTRL_VERSION: - { - return ctrl_version(demod, - (struct drx_version_list **)ctrl_data); - } - break; - /*======================================================================*/ - case DRX_CTRL_PROBE_DEVICE: - { - return ctrl_probe_device(demod); - } - break; - /*======================================================================*/ - case DRX_CTRL_SET_OOB: - { - return ctrl_set_oob(demod, (struct drxoob *)ctrl_data); - } - break; - /*======================================================================*/ - case DRX_CTRL_GET_OOB: - { - return ctrl_get_oob(demod, (struct drxoob_status *)ctrl_data); - } - break; - /*======================================================================*/ - case DRX_CTRL_SET_UIO_CFG: - { - return ctrl_set_uio_cfg(demod, (struct drxuio_cfg *)ctrl_data); - } - break; - /*======================================================================*/ - case DRX_CTRL_GET_UIO_CFG: - { - return ctrl_getuio_cfg(demod, (struct drxuio_cfg *)ctrl_data); - } - break; - /*======================================================================*/ - case DRX_CTRL_UIO_READ: - { - return ctrl_uio_read(demod, (struct drxuio_data *)ctrl_data); - } - break; - /*======================================================================*/ - case DRX_CTRL_UIO_WRITE: - { - return ctrl_uio_write(demod, (struct drxuio_data *)ctrl_data); - } - break; - /*======================================================================*/ - case DRX_CTRL_AUD_SET_STANDARD: - { - return aud_ctrl_set_standard(demod, - (enum drx_aud_standard *) ctrl_data); - } - break; - /*======================================================================*/ - case DRX_CTRL_AUD_GET_STANDARD: - { - return aud_ctrl_get_standard(demod, - (enum drx_aud_standard *) ctrl_data); - } - break; - /*======================================================================*/ - case DRX_CTRL_AUD_GET_STATUS: - { - return aud_ctrl_get_status(demod, - (struct drx_aud_status *) ctrl_data); - } - break; - /*======================================================================*/ - case DRX_CTRL_AUD_BEEP: - { - return aud_ctrl_beep(demod, (struct drx_aud_beep *)ctrl_data); - } - break; - - /*======================================================================*/ - case DRX_CTRL_I2C_READWRITE: - { - return ctrl_i2c_write_read(demod, - (struct drxi2c_data *) ctrl_data); - } - break; - case DRX_CTRL_VALIDATE_UCODE: - { - return ctrl_validate_u_code(demod); - } - break; - default: - return -ENOTSUPP; - } - return 0; -} - /* * Microcode related functions */ @@ -20635,7 +20454,7 @@ static int drx39xxj_set_powerstate(struct dvb_frontend *fe, int enable) else power_mode = DRX_POWER_DOWN; - result = drxj_ctrl(demod, DRX_CTRL_POWER_MODE, &power_mode); + result = ctrl_power_mode(demod, &power_mode); if (result != 0) { pr_err("Power state change failed\n"); return 0; @@ -20654,7 +20473,7 @@ static int drx39xxj_read_status(struct dvb_frontend *fe, fe_status_t *status) *status = 0; - result = drxj_ctrl(demod, DRX_CTRL_LOCK_STATUS, &lock_status); + result = ctrl_lock_status(demod, &lock_status); if (result != 0) { pr_err("drx39xxj: could not get lock status!\n"); *status = 0; @@ -20699,7 +20518,7 @@ static int drx39xxj_read_ber(struct dvb_frontend *fe, u32 *ber) int result; struct drx_sig_quality sig_quality; - result = drxj_ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); + result = ctrl_sig_quality(demod, &sig_quality); if (result != 0) { pr_err("drx39xxj: could not get ber!\n"); *ber = 0; @@ -20718,7 +20537,7 @@ static int drx39xxj_read_signal_strength(struct dvb_frontend *fe, int result; struct drx_sig_quality sig_quality; - result = drxj_ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); + result = ctrl_sig_quality(demod, &sig_quality); if (result != 0) { pr_err("drx39xxj: could not get signal strength!\n"); *strength = 0; @@ -20737,7 +20556,7 @@ static int drx39xxj_read_snr(struct dvb_frontend *fe, u16 *snr) int result; struct drx_sig_quality sig_quality; - result = drxj_ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); + result = ctrl_sig_quality(demod, &sig_quality); if (result != 0) { pr_err("drx39xxj: could not read snr!\n"); *snr = 0; @@ -20755,7 +20574,7 @@ static int drx39xxj_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) int result; struct drx_sig_quality sig_quality; - result = drxj_ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); + result = ctrl_sig_quality(demod, &sig_quality); if (result != 0) { pr_err("drx39xxj: could not get uc blocks!\n"); *ucblocks = 0; @@ -20834,7 +20653,7 @@ static int drx39xxj_set_frontend(struct dvb_frontend *fe) if (standard != state->current_standard || state->powered_up == 0) { /* Set the standard (will be powered up if necessary */ - result = drxj_ctrl(demod, DRX_CTRL_SET_STANDARD, &standard); + result = ctrl_set_standard(demod, &standard); if (result != 0) { pr_err("Failed to set standard! result=%02x\n", result); @@ -20851,7 +20670,7 @@ static int drx39xxj_set_frontend(struct dvb_frontend *fe) channel.constellation = constellation; /* program channel */ - result = drxj_ctrl(demod, DRX_CTRL_SET_CHANNEL, &channel); + result = ctrl_set_channel(demod, &channel); if (result != 0) { pr_err("Failed to set channel!\n"); return -EINVAL; @@ -20859,7 +20678,7 @@ static int drx39xxj_set_frontend(struct dvb_frontend *fe) /* Just for giggles, let's shut off the LNA again.... */ uio_data.uio = DRX_UIO1; uio_data.value = false; - result = drxj_ctrl(demod, DRX_CTRL_UIO_WRITE, &uio_data); + result = ctrl_uio_write(demod, &uio_data); if (result != 0) { pr_err("Failed to disable LNA!\n"); return 0; @@ -20905,7 +20724,7 @@ static int drx39xxj_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) return 0; } - result = drxj_ctrl(demod, DRX_CTRL_I2C_BRIDGE, &i2c_gate_state); + result = ctrl_i2c_bridge(demod, &i2c_gate_state); if (result != 0) { pr_err("drx39xxj: could not open i2c gate [%d]\n", result); @@ -21013,7 +20832,7 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) uio_cfg.uio = DRX_UIO1; uio_cfg.mode = DRX_UIO_MODE_READWRITE; /* Configure user-I/O #3: enable read/write */ - result = drxj_ctrl(demod, DRX_CTRL_UIO_CFG, &uio_cfg); + result = ctrl_set_uio_cfg(demod, &uio_cfg); if (result) { pr_err("Failed to setup LNA GPIO!\n"); goto error; @@ -21021,7 +20840,7 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) uio_data.uio = DRX_UIO1; uio_data.value = false; - result = drxj_ctrl(demod, DRX_CTRL_UIO_WRITE, &uio_data); + result = ctrl_uio_write(demod, &uio_data); if (result != 0) { pr_err("Failed to disable LNA!\n"); goto error; -- cgit v1.1 From 74c8794a8fbc79efa2c5e73bf36121551bbd34bf Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Fri, 24 Jan 2014 13:16:16 -0300 Subject: [media] drx-j: comment or remove unused code In order to avoid warnings and to remove dead code, remove the functions that don't make sense to happen, while commenting the others that might still be useful some day. That reduced a lot the text size: Before: text data bss dec hex filename 58419 2916 4 61339 ef9b drivers/media/dvb-frontends/drx39xyj/drx39xyj.ko After: text data bss dec hex filename 78331 2916 4 81251 13d63 drivers/media/dvb-frontends/drx39xyj/drx39xyj.ko Without any functional changes. It could be make sense latter to remove those drivers or to move them into an analog-specific part of the driver. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drxj.c | 362 ++++++---------------------- 1 file changed, 72 insertions(+), 290 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index 66a83b8..0dfb338 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -1083,12 +1083,12 @@ ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode); static int power_down_aud(struct drx_demod_instance *demod); -#ifndef DRXJ_DIGITAL_ONLY +#if 0 static int power_up_aud(struct drx_demod_instance *demod, bool set_standard); -#endif static int aud_ctrl_set_standard(struct drx_demod_instance *demod, enum drx_aud_standard *standard); +#endif static int ctrl_set_cfg_pre_saw(struct drx_demod_instance *demod, struct drxj_cfg_pre_saw *pre_saw); @@ -1102,6 +1102,7 @@ ctrl_set_cfg_afe_gain(struct drx_demod_instance *demod, struct drxj_cfg_afe_gain /*============================================================================*/ /*============================================================================*/ +#if 0 /** * \fn void mult32(u32 a, u32 b, u32 *h, u32 *l) * \brief 32bitsx32bits signed multiplication @@ -1191,6 +1192,7 @@ static void mult32(u32 a, u32 b, u32 *h, u32 *l) } } } +#endif /*============================================================================*/ @@ -1384,6 +1386,7 @@ static u32 frac_times1e6(u32 N, u32 D) /*============================================================================*/ +#if 0 /** * \brief Compute: 100 * 10^( gd_b / 200 ). * \param u32 gd_b Gain in 0.1dB @@ -1425,7 +1428,6 @@ static u32 d_b2lin_times100(u32 gd_b) return (result + 50) / 100; } -#ifndef DRXJ_DIGITAL_ONLY #define FRAC_FLOOR 0 #define FRAC_CEIL 1 #define FRAC_ROUND 2 @@ -3194,6 +3196,7 @@ rw_error: /*----------------------------------------------------------------------------*/ +#if 0 /** * \fn int ctrl_get_cfg_mpeg_output() * \brief Get MPEG output configuration of the device. @@ -3253,6 +3256,7 @@ ctrl_get_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o rw_error: return -EIO; } +#endif /*----------------------------------------------------------------------------*/ /* MPEG Output Configuration Functions - end */ @@ -3387,6 +3391,7 @@ rw_error: * This routine should be called during a set channel of QAM/VSB * */ +#if 0 static int set_mpeg_output_clock_rate(struct drx_demod_instance *demod) { struct drxj_data *ext_attr = (struct drxj_data *) (NULL); @@ -3408,6 +3413,7 @@ static int set_mpeg_output_clock_rate(struct drx_demod_instance *demod) rw_error: return -EIO; } +#endif /*----------------------------------------------------------------------------*/ /** @@ -3453,6 +3459,7 @@ rw_error: return -EIO; } +#if 0 /*----------------------------------------------------------------------------*/ /** * \fn int ctrl_set_cfg_mpeg_output_misc() @@ -3609,6 +3616,7 @@ ctrl_get_cfg_hw_cfg(struct drx_demod_instance *demod, struct drxj_cfg_hw_cfg *cf rw_error: return -EIO; } +#endif /*----------------------------------------------------------------------------*/ /* miscellaneous configuartions - end */ @@ -3754,6 +3762,7 @@ rw_error: return -EIO; } +#if 0 /*============================================================================*/ /** * \fn int ctrl_getuio_cfg() @@ -3794,6 +3803,7 @@ static int ctrl_getuio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg * return 0; } +#endif /** * \fn int ctrl_uio_write() @@ -3997,6 +4007,7 @@ rw_error: return -EIO; } +#if 0 /** *\fn int ctrl_uio_read *\brief Read from a UIO. @@ -4174,6 +4185,7 @@ static int ctrl_uio_read(struct drx_demod_instance *demod, struct drxuio_data *u rw_error: return -EIO; } +#endif /*---------------------------------------------------------------------------*/ /* UIO Configuration Functions - end */ @@ -4290,6 +4302,7 @@ rw_error: return -EIO; } +#if 0 /** * \fn int ctrl_set_cfg_smart_ant() * \brief Set Smart Antenna. @@ -4400,6 +4413,7 @@ ctrl_set_cfg_smart_ant(struct drx_demod_instance *demod, struct drxj_cfg_smart_a rw_error: return -EIO; } +#endif static int scu_command(struct i2c_device_addr *dev_addr, struct drxjscu_cmd *cmd) { @@ -4659,12 +4673,6 @@ int drxj_dap_scu_atomic_write_reg16(struct i2c_device_addr *dev_addr, return rc; } -static int -ctrl_i2c_write_read(struct drx_demod_instance *demod, struct drxi2c_data *i2c_data) -{ - return -ENOTSUPP; -} - /* -------------------------------------------------------------------------- */ /** * \brief Measure result of ADC synchronisation @@ -4789,6 +4797,7 @@ rw_error: return -EIO; } +#if 0 /** * \brief Configure IQM AF registers * \param demod instance of demodulator. @@ -5101,43 +5110,7 @@ ctrl_get_cfg_pdr_safe_mode(struct drx_demod_instance *demod, bool *enabled) return 0; } - -/** -* \brief Verifies whether microcode can be loaded. -* \param demod Demodulator instance. -* \return int. -*/ -static int ctrl_validate_u_code(struct drx_demod_instance *demod) -{ - u32 mc_dev, mc_patch; - u16 ver_type; - - /* Check device. - * Disallow microcode if: - * - MC has version record AND - * - device ID in version record is not 0 AND - * - product ID in version record's device ID does not - * match DRXJ1 product IDs - 0x393 or 0x394 - */ - ver_type = DRX_ATTR_MCRECORD(demod).aux_type; - mc_dev = DRX_ATTR_MCRECORD(demod).mc_dev_type; - mc_patch = DRX_ATTR_MCRECORD(demod).mc_base_version; - - if (DRX_ISMCVERTYPE(ver_type)) { - if ((mc_dev != 0) && - (((mc_dev >> 16) & 0xFFF) != 0x393) && - (((mc_dev >> 16) & 0xFFF) != 0x394)) { - /* Microcode is marked for another device - error */ - return -EINVAL; - } else if (mc_patch != 0) { - /* Patch not allowed because there is no ROM */ - return -EINVAL; - } - } - - /* Everything else: OK */ - return 0; -} +#endif /*============================================================================*/ /*== END AUXILIARY FUNCTIONS ==*/ @@ -5350,7 +5323,7 @@ static int init_agc(struct drx_demod_instance *demod) } break; #endif -#ifndef DRXJ_DIGITAL_ONLY +#if 0 case DRX_STANDARD_FM: clp_sum_max = 1023; sns_sum_max = 1023; @@ -5687,6 +5660,7 @@ rw_error: return -EIO; } +#if 0 /** * \fn int get_sig_strength() * \brief Retrieve signal strength for VSB and QAM. @@ -5763,6 +5737,7 @@ static int get_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength) rw_error: return -EIO; } +#endif /** * \fn int get_acc_pkt_err() @@ -5813,6 +5788,7 @@ rw_error: } #endif +#if 0 /** * \fn int ResetAccPktErr() * \brief Reset Accumulating packet error count. @@ -5823,7 +5799,6 @@ rw_error: */ static int ctrl_set_cfg_reset_pkt_err(struct drx_demod_instance *demod) { -#ifdef DRXJ_SIGNAL_ACCUM_ERR struct drxj_data *ext_attr = NULL; int rc; u16 packet_error = 0; @@ -5839,7 +5814,6 @@ static int ctrl_set_cfg_reset_pkt_err(struct drx_demod_instance *demod) return 0; rw_error: -#endif return -EIO; } @@ -5937,6 +5911,7 @@ static int get_ctl_freq_offset(struct drx_demod_instance *demod, s32 *ctl_freq) rw_error: return -EIO; } +#endif /*============================================================================*/ @@ -6145,7 +6120,7 @@ set_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, ext_attr->qam_rf_agc_cfg = *agc_settings; break; #endif -#ifndef DRXJ_DIGITAL_ONLY +#if 0 case DRX_STANDARD_PAL_SECAM_BG: case DRX_STANDARD_PAL_SECAM_DK: case DRX_STANDARD_PAL_SECAM_I: @@ -6165,6 +6140,7 @@ rw_error: return -EIO; } +#if 0 /** * \fn int get_agc_rf () * \brief get configuration of RF AGC @@ -6196,7 +6172,7 @@ get_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings) *agc_settings = ext_attr->qam_rf_agc_cfg; break; #endif -#ifndef DRXJ_DIGITAL_ONLY +#if 0 case DRX_STANDARD_PAL_SECAM_BG: case DRX_STANDARD_PAL_SECAM_DK: case DRX_STANDARD_PAL_SECAM_I: @@ -6229,6 +6205,7 @@ get_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings) rw_error: return -EIO; } +#endif /** * \fn int set_agc_if () @@ -6450,7 +6427,7 @@ set_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, ext_attr->qam_if_agc_cfg = *agc_settings; break; #endif -#ifndef DRXJ_DIGITAL_ONLY +#if 0 case DRX_STANDARD_PAL_SECAM_BG: case DRX_STANDARD_PAL_SECAM_DK: case DRX_STANDARD_PAL_SECAM_I: @@ -6470,6 +6447,7 @@ rw_error: return -EIO; } +#if 0 /** * \fn int get_agc_if () * \brief get configuration of If AGC @@ -6501,7 +6479,6 @@ get_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings) *agc_settings = ext_attr->qam_if_agc_cfg; break; #endif -#ifndef DRXJ_DIGITAL_ONLY case DRX_STANDARD_PAL_SECAM_BG: case DRX_STANDARD_PAL_SECAM_DK: case DRX_STANDARD_PAL_SECAM_I: @@ -6511,7 +6488,6 @@ get_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings) case DRX_STANDARD_FM: *agc_settings = ext_attr->atv_if_agc_cfg; break; -#endif default: return -EIO; } @@ -6535,6 +6511,7 @@ get_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings) rw_error: return -EIO; } +#endif /** * \fn int set_iqm_af () @@ -7518,6 +7495,7 @@ rw_error: return -EIO; } +#if 0 /** * \fn static short get_vsb_symb_err(struct i2c_device_addr *dev_addr, u32 *ber) * \brief Get the values of ber in VSB mode @@ -7555,6 +7533,7 @@ static int get_vsb_symb_err(struct i2c_device_addr *dev_addr, u32 *ser) rw_error: return -EIO; } +#endif /** * \fn static int get_vsbmer(struct i2c_device_addr *dev_addr, u16 *mer) @@ -7579,6 +7558,7 @@ rw_error: return -EIO; } +#if 0 /*============================================================================*/ /** * \fn int ctrl_get_vsb_constel() @@ -7659,6 +7639,7 @@ ctrl_get_vsb_constel(struct drx_demod_instance *demod, struct drx_complex *compl rw_error: return -EIO; } +#endif /*============================================================================*/ /*== END 8VSB DATAPATH FUNCTIONS ==*/ @@ -10870,6 +10851,7 @@ rw_error: return -EIO; } +#if 0 /** * \fn int ctrl_get_qam_constel() * \brief Retreive a QAM constellation point via I2C. @@ -10974,6 +10956,7 @@ ctrl_get_qam_constel(struct drx_demod_instance *demod, struct drx_complex *compl rw_error: return -EIO; } +#endif /* #if 0 */ #endif /* #ifndef DRXJ_VSB_ONLY */ /*============================================================================*/ @@ -11042,6 +11025,7 @@ rw_error: */ /* -------------------------------------------------------------------------- */ +#if 0 /** * \brief Get array index for atv coef (ext_attr->atvTopCoefX[index]) * \param standard @@ -11297,7 +11281,6 @@ rw_error: } /* -------------------------------------------------------------------------- */ -#ifndef DRXJ_DIGITAL_ONLY /** * \fn int ctrl_set_cfg_atv_equ_coef() * \brief Set ATV equalizer coefficients @@ -11687,7 +11670,7 @@ static int power_up_atv(struct drx_demod_instance *demod, enum drx_standard stan rw_error: return -EIO; } -#endif /* #ifndef DRXJ_DIGITAL_ONLY */ +#endif /* -------------------------------------------------------------------------- */ @@ -11802,7 +11785,7 @@ rw_error: * Assuming that IQM, ATV and AUD blocks have been reset and are in STOP mode * */ -#ifndef DRXJ_DIGITAL_ONLY +#if 0 #define SCU_RAM_ATV_ENABLE_IIR_WA__A 0x831F6D /* TODO remove after done with reg import */ static int set_atv_standard(struct drx_demod_instance *demod, enum drx_standard *standard) @@ -12861,11 +12844,9 @@ trouble ? rw_error: return -EIO; } -#endif /* -------------------------------------------------------------------------- */ -#ifndef DRXJ_DIGITAL_ONLY /** * \fn int set_atv_channel () * \brief Set ATV channel. @@ -12939,7 +12920,6 @@ set_atv_channel(struct drx_demod_instance *demod, rw_error: return -EIO; } -#endif /* -------------------------------------------------------------------------- */ @@ -12956,7 +12936,6 @@ rw_error: * channel->frequency. Determines the value for channel->bandwidth. * */ -#ifndef DRXJ_DIGITAL_ONLY static int get_atv_channel(struct drx_demod_instance *demod, struct drx_channel *channel, enum drx_standard standard) @@ -13213,13 +13192,11 @@ atv_sig_quality(struct drx_demod_instance *demod, struct drx_sig_quality *sig_qu rw_error: return -EIO; } -#endif /* DRXJ_DIGITAL_ONLY */ /*============================================================================*/ /*== END ATV DATAPATH FUNCTIONS ==*/ /*============================================================================*/ -#ifndef DRXJ_EXCLUDE_AUDIO /*===========================================================================*/ /*===========================================================================*/ /*== AUDIO DATAPATH FUNCTIONS ==*/ @@ -13269,6 +13246,7 @@ static int power_up_aud(struct drx_demod_instance *demod, bool set_standard) rw_error: return -EIO; } +#endif /*============================================================================*/ @@ -13300,6 +13278,7 @@ rw_error: return -EIO; } +#if 0 /*============================================================================*/ /** * \brief Get Modus data from audio RAM @@ -15785,8 +15764,6 @@ rw_error: return -EIO; } -#endif - /*===========================================================================*/ /*== END AUDIO DATAPATH FUNCTIONS ==*/ /*===========================================================================*/ @@ -15796,7 +15773,6 @@ rw_error: /*== OOB DATAPATH FUNCTIONS ==*/ /*============================================================================*/ /*============================================================================*/ -#ifndef DRXJ_DIGITAL_ONLY /** * \fn int get_oob_lock_status () * \brief Get OOB lock status. @@ -16254,7 +16230,7 @@ static int get_oobmer(struct i2c_device_addr *dev_addr, u32 *mer) rw_error: return -EIO; } -#endif /*#ifndef DRXJ_DIGITAL_ONLY */ +#endif /** * \fn int set_orx_nsu_aox() @@ -16314,9 +16290,9 @@ rw_error: /* Coefficients for the nyquist fitler (total: 27 taps) */ #define NYQFILTERLEN 27 +#if 0 static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_param) { -#ifndef DRXJ_DIGITAL_ONLY int rc; s32 freq = 0; /* KHz */ struct i2c_device_addr *dev_addr = NULL; @@ -16812,7 +16788,6 @@ static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_par return 0; rw_error: -#endif return -EIO; } @@ -16826,7 +16801,6 @@ rw_error: static int ctrl_get_oob(struct drx_demod_instance *demod, struct drxoob_status *oob_status) { -#ifndef DRXJ_DIGITAL_ONLY int rc; struct i2c_device_addr *dev_addr = NULL; struct drxj_data *ext_attr = NULL; @@ -16891,7 +16865,6 @@ ctrl_get_oob(struct drx_demod_instance *demod, struct drxoob_status *oob_status) return 0; rw_error: -#endif return -EIO; } @@ -16901,7 +16874,6 @@ rw_error: * \param cfg_data Pointer to configuration parameter * \return Error code */ -#ifndef DRXJ_DIGITAL_ONLY static int ctrl_set_cfg_oob_pre_saw(struct drx_demod_instance *demod, u16 *cfg_data) { @@ -16925,7 +16897,6 @@ ctrl_set_cfg_oob_pre_saw(struct drx_demod_instance *demod, u16 *cfg_data) rw_error: return -EIO; } -#endif /** * \fn int ctrl_get_cfg_oob_pre_saw() @@ -16933,7 +16904,6 @@ rw_error: * \param cfg_data Pointer to configuration parameter * \return Error code */ -#ifndef DRXJ_DIGITAL_ONLY static int ctrl_get_cfg_oob_pre_saw(struct drx_demod_instance *demod, u16 *cfg_data) { @@ -16948,14 +16918,12 @@ ctrl_get_cfg_oob_pre_saw(struct drx_demod_instance *demod, u16 *cfg_data) return 0; } -#endif /** * \fn int ctrl_set_cfg_oob_lo_power() * \brief Configure LO Power value * \param cfg_data Pointer to enum drxj_cfg_oob_lo_power ** \return Error code */ -#ifndef DRXJ_DIGITAL_ONLY static int ctrl_set_cfg_oob_lo_power(struct drx_demod_instance *demod, enum drxj_cfg_oob_lo_power *cfg_data) { @@ -16979,14 +16947,12 @@ ctrl_set_cfg_oob_lo_power(struct drx_demod_instance *demod, enum drxj_cfg_oob_lo rw_error: return -EIO; } -#endif /** * \fn int ctrl_get_cfg_oob_lo_power() * \brief Configure LO Power value * \param cfg_data Pointer to enum drxj_cfg_oob_lo_power ** \return Error code */ -#ifndef DRXJ_DIGITAL_ONLY static int ctrl_get_cfg_oob_lo_power(struct drx_demod_instance *demod, enum drxj_cfg_oob_lo_power *cfg_data) { @@ -17061,7 +17027,7 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) case DRX_STANDARD_ITU_B: case DRX_STANDARD_ITU_C: #endif /* DRXJ_VSB_ONLY */ -#ifndef DRXJ_DIGITAL_ONLY +#if 0 case DRX_STANDARD_NTSC: case DRX_STANDARD_FM: case DRX_STANDARD_PAL_SECAM_BG: @@ -17069,7 +17035,7 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) case DRX_STANDARD_PAL_SECAM_I: case DRX_STANDARD_PAL_SECAM_L: case DRX_STANDARD_PAL_SECAM_LP: -#endif /* DRXJ_DIGITAL_ONLY */ +#endif break; case DRX_STANDARD_UNKNOWN: default: @@ -17091,7 +17057,7 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) return -EINVAL; } } -#ifndef DRXJ_DIGITAL_ONLY +#if 0 if (standard == DRX_STANDARD_PAL_SECAM_BG) { switch (channel->bandwidth) { case DRX_BANDWIDTH_7MHZ: /* fall through */ @@ -17248,7 +17214,7 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) if (demod->my_tuner != NULL) { /* Determine tuner mode and freq to tune to ... */ switch (standard) { -#ifndef DRXJ_DIGITAL_ONLY +#if 0 case DRX_STANDARD_NTSC: /* fallthrough */ case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ @@ -17365,7 +17331,7 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) goto rw_error; } break; -#ifndef DRXJ_DIGITAL_ONLY +#if 0 case DRX_STANDARD_NTSC: /* fallthrough */ case DRX_STANDARD_FM: /* fallthrough */ case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ @@ -17442,6 +17408,7 @@ rw_error: return -EIO; } +#if 0 /*============================================================================= ===== ctrl_get_channel() ========================================================== ===========================================================================*/ @@ -17646,7 +17613,6 @@ ctrl_get_channel(struct drx_demod_instance *demod, struct drx_channel *channel) } break; #endif -#ifndef DRXJ_DIGITAL_ONLY case DRX_STANDARD_NTSC: /* fall trough */ case DRX_STANDARD_PAL_SECAM_BG: case DRX_STANDARD_PAL_SECAM_DK: @@ -17660,7 +17626,6 @@ ctrl_get_channel(struct drx_demod_instance *demod, struct drx_channel *channel) goto rw_error; } break; -#endif case DRX_STANDARD_UNKNOWN: /* fall trough */ default: return -EIO; @@ -17674,6 +17639,7 @@ ctrl_get_channel(struct drx_demod_instance *demod, struct drx_channel *channel) rw_error: return -EIO; } +#endif /*============================================================================= ===== SigQuality() ========================================================== @@ -17839,7 +17805,7 @@ ctrl_sig_quality(struct drx_demod_instance *demod, struct drx_sig_quality *sig_q max_mer); break; #endif -#ifndef DRXJ_DIGITAL_ONLY +#if 0 case DRX_STANDARD_PAL_SECAM_BG: case DRX_STANDARD_PAL_SECAM_DK: case DRX_STANDARD_PAL_SECAM_I: @@ -17920,7 +17886,7 @@ ctrl_lock_status(struct drx_demod_instance *demod, enum drx_lock_status *lock_st SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK; break; #endif -#ifndef DRXJ_DIGITAL_ONLY +#if 0 case DRX_STANDARD_NTSC: case DRX_STANDARD_PAL_SECAM_BG: case DRX_STANDARD_PAL_SECAM_DK: @@ -17972,6 +17938,7 @@ rw_error: /*============================================================================*/ +#if 0 /** * \fn int ctrl_constel() * \brief Retreive a constellation point via I2C. @@ -18023,6 +17990,7 @@ ctrl_constel(struct drx_demod_instance *demod, struct drx_complex *complex_nr) rw_error: return -EIO; } +#endif /*============================================================================*/ @@ -18072,7 +18040,7 @@ ctrl_set_standard(struct drx_demod_instance *demod, enum drx_standard *standard) goto rw_error; } break; -#ifndef DRXJ_DIGITAL_ONLY +#if 0 case DRX_STANDARD_NTSC: /* fallthrough */ case DRX_STANDARD_FM: /* fallthrough */ case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ @@ -18123,7 +18091,7 @@ ctrl_set_standard(struct drx_demod_instance *demod, enum drx_standard *standard) goto rw_error; } break; -#ifndef DRXJ_DIGITAL_ONLY +#if 0 case DRX_STANDARD_NTSC: /* fallthrough */ case DRX_STANDARD_FM: /* fallthrough */ case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ @@ -18156,6 +18124,7 @@ rw_error: return -EIO; } +#if 0 /*============================================================================*/ /** @@ -18239,6 +18208,7 @@ ctrl_get_cfg_symbol_clock_offset(struct drx_demod_instance *demod, s32 *rate_off rw_error: return -EIO; } +#endif /*============================================================================*/ @@ -18300,7 +18270,7 @@ static void drxj_reset_mode(struct drxj_data *ext_attr) ext_attr->vsb_pre_saw_cfg.reference = 0x07; ext_attr->vsb_pre_saw_cfg.use_pre_saw = true; -#ifndef DRXJ_DIGITAL_ONLY +#if 0 /* Initialize default AFE configuartion for ATV */ ext_attr->atv_rf_agc_cfg.standard = DRX_STANDARD_NTSC; ext_attr->atv_rf_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; @@ -18469,191 +18439,7 @@ rw_error: return -EIO; } -/*============================================================================*/ - -/** -* \fn int ctrl_version() -* \brief Report version of microcode and if possible version of device -* \param demod Pointer to demodulator instance. -* \param version_list Pointer to pointer of linked list of versions. -* \return int. -* -* Using static structures so no allocation of memory is needed. -* Filling in all the fields each time, cause you don't know if they are -* changed by the application. -* -* For device: -* Major version number will be last two digits of family number. -* Minor number will be full respin number -* Patch will be metal fix number+1 -* Examples: -* DRX3942J A2 => number: 42.1.2 text: "DRX3942J:A2" -* DRX3933J B1 => number: 33.2.1 text: "DRX3933J:B1" -* -*/ -static int -ctrl_version(struct drx_demod_instance *demod, struct drx_version_list **version_list) -{ - struct drxj_data *ext_attr = (struct drxj_data *) (NULL); - struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); - struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL); - int rc; - u16 ucode_major_minor = 0; /* BCD Ma:Ma:Ma:Mi */ - u16 ucode_patch = 0; /* BCD Pa:Pa:Pa:Pa */ - u16 major = 0; - u16 minor = 0; - u16 patch = 0; - u16 idx = 0; - u32 jtag = 0; - u16 subtype = 0; - u16 mfx = 0; - u16 bid = 0; - u16 key = 0; - static char ucode_name[] = "Microcode"; - static char device_name[] = "Device"; - - dev_addr = demod->my_i2c_dev_addr; - ext_attr = (struct drxj_data *) demod->my_ext_attr; - common_attr = (struct drx_common_attr *) demod->my_common_attr; - - /* Microcode version *************************************** */ - - ext_attr->v_version[0].module_type = DRX_MODULE_MICROCODE; - ext_attr->v_version[0].module_name = ucode_name; - ext_attr->v_version[0].v_string = ext_attr->v_text[0]; - - if (common_attr->is_opened == true) { - rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_VERSION_HI__A, &ucode_major_minor, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_VERSION_LO__A, &ucode_patch, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* Translate BCD to numbers and string */ - /* TODO: The most significant Ma and Pa will be ignored, check with spec */ - minor = (ucode_major_minor & 0xF); - ucode_major_minor >>= 4; - major = (ucode_major_minor & 0xF); - ucode_major_minor >>= 4; - major += (10 * (ucode_major_minor & 0xF)); - patch = (ucode_patch & 0xF); - ucode_patch >>= 4; - patch += (10 * (ucode_patch & 0xF)); - ucode_patch >>= 4; - patch += (100 * (ucode_patch & 0xF)); - } else { - /* No microcode uploaded, No Rom existed, set version to 0.0.0 */ - patch = 0; - minor = 0; - major = 0; - } - ext_attr->v_version[0].v_major = major; - ext_attr->v_version[0].v_minor = minor; - ext_attr->v_version[0].v_patch = patch; - - if (major / 10 != 0) { - ext_attr->v_version[0].v_string[idx++] = - ((char)(major / 10)) + '0'; - major %= 10; - } - ext_attr->v_version[0].v_string[idx++] = ((char)major) + '0'; - ext_attr->v_version[0].v_string[idx++] = '.'; - ext_attr->v_version[0].v_string[idx++] = ((char)minor) + '0'; - ext_attr->v_version[0].v_string[idx++] = '.'; - if (patch / 100 != 0) { - ext_attr->v_version[0].v_string[idx++] = - ((char)(patch / 100)) + '0'; - patch %= 100; - } - if (patch / 10 != 0) { - ext_attr->v_version[0].v_string[idx++] = - ((char)(patch / 10)) + '0'; - patch %= 10; - } - ext_attr->v_version[0].v_string[idx++] = ((char)patch) + '0'; - ext_attr->v_version[0].v_string[idx] = '\0'; - - ext_attr->v_list_elements[0].version = &(ext_attr->v_version[0]); - ext_attr->v_list_elements[0].next = &(ext_attr->v_list_elements[1]); - - /* Device version *************************************** */ - /* Check device id */ - rc = DRXJ_DAP.read_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, &key, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = DRXJ_DAP.read_reg32func(dev_addr, SIO_TOP_JTAGID_LO__A, &jtag, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = DRXJ_DAP.read_reg16func(dev_addr, SIO_PDR_UIO_IN_HI__A, &bid, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, key, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - ext_attr->v_version[1].module_type = DRX_MODULE_DEVICE; - ext_attr->v_version[1].module_name = device_name; - ext_attr->v_version[1].v_string = ext_attr->v_text[1]; - ext_attr->v_version[1].v_string[0] = 'D'; - ext_attr->v_version[1].v_string[1] = 'R'; - ext_attr->v_version[1].v_string[2] = 'X'; - ext_attr->v_version[1].v_string[3] = '3'; - ext_attr->v_version[1].v_string[4] = '9'; - ext_attr->v_version[1].v_string[7] = 'J'; - ext_attr->v_version[1].v_string[8] = ':'; - ext_attr->v_version[1].v_string[11] = '\0'; - - /* DRX39xxJ type Ax */ - /* TODO semantics of mfx and spin are unclear */ - subtype = (u16) ((jtag >> 12) & 0xFF); - mfx = (u16) (jtag >> 29); - ext_attr->v_version[1].v_minor = 1; - if (mfx == 0x03) - ext_attr->v_version[1].v_patch = mfx + 2; - else - ext_attr->v_version[1].v_patch = mfx + 1; - ext_attr->v_version[1].v_string[6] = ((char)(subtype & 0xF)) + '0'; - ext_attr->v_version[1].v_major = (subtype & 0x0F); - subtype >>= 4; - ext_attr->v_version[1].v_string[5] = ((char)(subtype & 0xF)) + '0'; - ext_attr->v_version[1].v_major += 10 * subtype; - ext_attr->v_version[1].v_string[9] = 'A'; - if (mfx == 0x03) - ext_attr->v_version[1].v_string[10] = ((char)(mfx & 0xF)) + '2'; - else - ext_attr->v_version[1].v_string[10] = ((char)(mfx & 0xF)) + '1'; - - ext_attr->v_list_elements[1].version = &(ext_attr->v_version[1]); - ext_attr->v_list_elements[1].next = (struct drx_version_list *) (NULL); - - *version_list = &(ext_attr->v_list_elements[0]); - - return 0; - -rw_error: - *version_list = (struct drx_version_list *) (NULL); - return -EIO; - -} - +#if 0 /*============================================================================*/ /** @@ -18761,11 +18547,13 @@ rw_error: common_attr->current_power_mode = org_power_mode; return -EIO; } +#endif /*============================================================================*/ /*== CTRL Set/Get Config related functions ===================================*/ /*============================================================================*/ +#if 0 /*===== SigStrength() =========================================================*/ /** * \fn int ctrl_sig_strength() @@ -18807,7 +18595,6 @@ ctrl_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength) goto rw_error; } break; -#ifndef DRXJ_DIGITAL_ONLY case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ @@ -18821,7 +18608,6 @@ ctrl_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength) goto rw_error; } break; -#endif case DRX_STANDARD_UNKNOWN: /* fallthrough */ default: return -EINVAL; @@ -18842,7 +18628,6 @@ rw_error: * \return int. * */ -#ifndef DRXJ_DIGITAL_ONLY static int ctrl_get_cfg_oob_misc(struct drx_demod_instance *demod, struct drxj_cfg_oob_misc *misc) { @@ -18907,7 +18692,6 @@ ctrl_get_cfg_oob_misc(struct drx_demod_instance *demod, struct drxj_cfg_oob_misc rw_error: return -EIO; } -#endif /** * \fn int ctrl_get_cfg_vsb_misc() @@ -18976,7 +18760,7 @@ ctrl_set_cfg_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_s case DRX_STANDARD_ITU_B: /* fallthrough */ case DRX_STANDARD_ITU_C: #endif -#ifndef DRXJ_DIGITAL_ONLY +#if 0 case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ @@ -19022,7 +18806,7 @@ ctrl_get_cfg_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_s case DRX_STANDARD_ITU_B: /* fallthrough */ case DRX_STANDARD_ITU_C: #endif -#ifndef DRXJ_DIGITAL_ONLY +#if 0 case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ @@ -19077,7 +18861,6 @@ ctrl_set_cfg_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_s case DRX_STANDARD_ITU_B: /* fallthrough */ case DRX_STANDARD_ITU_C: #endif -#ifndef DRXJ_DIGITAL_ONLY case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ @@ -19085,7 +18868,6 @@ ctrl_set_cfg_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_s case DRX_STANDARD_PAL_SECAM_LP: /* fallthrough */ case DRX_STANDARD_NTSC: /* fallthrough */ case DRX_STANDARD_FM: -#endif return set_agc_rf(demod, agc_settings, true); case DRX_STANDARD_UNKNOWN: default: @@ -19123,7 +18905,6 @@ ctrl_get_cfg_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_s case DRX_STANDARD_ITU_B: /* fallthrough */ case DRX_STANDARD_ITU_C: #endif -#ifndef DRXJ_DIGITAL_ONLY case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ @@ -19131,7 +18912,6 @@ ctrl_get_cfg_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_s case DRX_STANDARD_PAL_SECAM_LP: /* fallthrough */ case DRX_STANDARD_NTSC: /* fallthrough */ case DRX_STANDARD_FM: -#endif return get_agc_rf(demod, agc_settings); case DRX_STANDARD_UNKNOWN: default: @@ -19241,6 +19021,7 @@ rw_error: } /*============================================================================*/ +#endif /** * \fn int ctrl_set_cfg_pre_saw() @@ -19294,7 +19075,7 @@ ctrl_set_cfg_pre_saw(struct drx_demod_instance *demod, struct drxj_cfg_pre_saw * ext_attr->qam_pre_saw_cfg = *pre_saw; break; #endif -#ifndef DRXJ_DIGITAL_ONLY +#if 0 case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ @@ -19397,6 +19178,7 @@ rw_error: /*============================================================================*/ +#if 0 /** * \fn int ctrl_get_cfg_pre_saw() * \brief Get Pre-saw reference setting. @@ -19430,7 +19212,6 @@ ctrl_get_cfg_pre_saw(struct drx_demod_instance *demod, struct drxj_cfg_pre_saw * *pre_saw = ext_attr->qam_pre_saw_cfg; break; #endif -#ifndef DRXJ_DIGITAL_ONLY case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ @@ -19444,7 +19225,7 @@ ctrl_get_cfg_pre_saw(struct drx_demod_instance *demod, struct drxj_cfg_pre_saw * ext_attr->atv_pre_saw_cfg.standard = DRX_STANDARD_FM; *pre_saw = ext_attr->atv_pre_saw_cfg; break; -#endif + default: return -EINVAL; } @@ -19603,7 +19384,7 @@ static int ctrl_set_cfg(struct drx_demod_instance *demod, struct drx_cfg *config cfg_data)); case DRXJ_CFG_RESET_PACKET_ERR: return ctrl_set_cfg_reset_pkt_err(demod); -#ifndef DRXJ_DIGITAL_ONLY +#if 0 case DRXJ_CFG_OOB_PRE_SAW: return ctrl_set_cfg_oob_pre_saw(demod, (u16 *)(config->cfg_data)); case DRXJ_CFG_OOB_LO_POW: @@ -19726,7 +19507,7 @@ static int ctrl_get_cfg(struct drx_demod_instance *demod, struct drx_cfg *config case DRXJ_CFG_SYMBOL_CLK_OFFSET: return ctrl_get_cfg_symbol_clock_offset(demod, (s32 *)config->cfg_data); -#ifndef DRXJ_DIGITAL_ONLY +#if 0 case DRXJ_CFG_OOB_MISC: return ctrl_get_cfg_oob_misc(demod, (struct drxj_cfg_oob_misc *) config->cfg_data); @@ -19809,6 +19590,7 @@ static int ctrl_get_cfg(struct drx_demod_instance *demod, struct drx_cfg *config rw_error: return -EIO; } +#endif /*============================================================================= ===== EXPORTED FUNCTIONS ====================================================*/ -- cgit v1.1 From d7b0631eb2798e5892e079fc6dfe1c60f3a3f222 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sun, 26 Jan 2014 14:23:24 -0300 Subject: [media] drx-j: remove some ugly bindings from drx39xxj_dummy.c This file does an ugly binding between drxj and DVB frontend. Remove most of the functions there. We still need to get rid of get_frequency and set_frequency, but such patch is a little more complex, as it should also remove some previous tuner bindings. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- .../media/dvb-frontends/drx39xyj/drx39xxj_dummy.c | 114 +-------------------- .../media/dvb-frontends/drx39xyj/drx_dap_fasi.c | 81 ++++++++++++++- drivers/media/dvb-frontends/drx39xyj/drx_driver.h | 21 ---- drivers/media/dvb-frontends/drx39xyj/drxj.c | 86 ++++++---------- 4 files changed, 113 insertions(+), 189 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c b/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c index c5187a1..33413cd 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c @@ -1,27 +1,8 @@ -#define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__ +/* Dummy function to satisfy drxj.c */ -#include -#include -#include -#include -#include -#include -#include #include - #include "drx_driver.h" -#include "drx39xxj.h" -/* Dummy function to satisfy drxj.c */ -int drxbsp_tuner_open(struct tuner_instance *tuner) -{ - return 0; -} - -int drxbsp_tuner_close(struct tuner_instance *tuner) -{ - return 0; -} int drxbsp_tuner_set_frequency(struct tuner_instance *tuner, u32 mode, @@ -38,96 +19,3 @@ drxbsp_tuner_get_frequency(struct tuner_instance *tuner, { return 0; } - -int drxbsp_hst_sleep(u32 n) -{ - msleep(n); - return 0; -} - -u32 drxbsp_hst_clock(void) -{ - return jiffies_to_msecs(jiffies); -} - -int drxbsp_hst_memcmp(void *s1, void *s2, u32 n) -{ - return memcmp(s1, s2, (size_t)n); -} - -void *drxbsp_hst_memcpy(void *to, void *from, u32 n) -{ - return memcpy(to, from, (size_t)n); -} - -int drxbsp_i2c_write_read(struct i2c_device_addr *w_dev_addr, - u16 w_count, - u8 *wData, - struct i2c_device_addr *r_dev_addr, - u16 r_count, u8 *r_data) -{ - struct drx39xxj_state *state; - struct i2c_msg msg[2]; - unsigned int num_msgs; - - if (w_dev_addr == NULL) { - /* Read only */ - state = r_dev_addr->user_data; - msg[0].addr = r_dev_addr->i2c_addr >> 1; - msg[0].flags = I2C_M_RD; - msg[0].buf = r_data; - msg[0].len = r_count; - num_msgs = 1; - } else if (r_dev_addr == NULL) { - /* Write only */ - state = w_dev_addr->user_data; - msg[0].addr = w_dev_addr->i2c_addr >> 1; - msg[0].flags = 0; - msg[0].buf = wData; - msg[0].len = w_count; - num_msgs = 1; - } else { - /* Both write and read */ - state = w_dev_addr->user_data; - msg[0].addr = w_dev_addr->i2c_addr >> 1; - msg[0].flags = 0; - msg[0].buf = wData; - msg[0].len = w_count; - msg[1].addr = r_dev_addr->i2c_addr >> 1; - msg[1].flags = I2C_M_RD; - msg[1].buf = r_data; - msg[1].len = r_count; - num_msgs = 2; - } - - if (state->i2c == NULL) { - pr_err("i2c was zero, aborting\n"); - return 0; - } - if (i2c_transfer(state->i2c, msg, num_msgs) != num_msgs) { - pr_warn("drx3933: I2C write/read failed\n"); - return -EREMOTEIO; - } - - return 0; - -#ifdef DJH_DEBUG - struct drx39xxj_state *state = w_dev_addr->user_data; - - struct i2c_msg msg[2] = { - {.addr = w_dev_addr->i2c_addr, - .flags = 0, .buf = wData, .len = w_count}, - {.addr = r_dev_addr->i2c_addr, - .flags = I2C_M_RD, .buf = r_data, .len = r_count}, - }; - - pr_dbg("drx3933 i2c operation addr=%x i2c=%p, wc=%x rc=%x\n", - w_dev_addr->i2c_addr, state->i2c, w_count, r_count); - - if (i2c_transfer(state->i2c, msg, 2) != 2) { - pr_warn("drx3933: I2C write/read failed\n"); - return -EREMOTEIO; - } -#endif - return 0; -} diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c index 2a37098..b78d45b 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c @@ -39,7 +39,11 @@ */ #include "drx_dap_fasi.h" -#include "drx_driver.h" /* for drxbsp_hst_memcpy() */ +#include "drx39xxj.h" + +#include +#include + /*============================================================================*/ @@ -172,6 +176,79 @@ static int drxdap_fasi_read_modify_write_reg32(struct i2c_device_addr *dev_addr, return -EIO; } + +int drxbsp_i2c_write_read(struct i2c_device_addr *w_dev_addr, + u16 w_count, + u8 *wData, + struct i2c_device_addr *r_dev_addr, + u16 r_count, u8 *r_data) +{ + struct drx39xxj_state *state; + struct i2c_msg msg[2]; + unsigned int num_msgs; + + if (w_dev_addr == NULL) { + /* Read only */ + state = r_dev_addr->user_data; + msg[0].addr = r_dev_addr->i2c_addr >> 1; + msg[0].flags = I2C_M_RD; + msg[0].buf = r_data; + msg[0].len = r_count; + num_msgs = 1; + } else if (r_dev_addr == NULL) { + /* Write only */ + state = w_dev_addr->user_data; + msg[0].addr = w_dev_addr->i2c_addr >> 1; + msg[0].flags = 0; + msg[0].buf = wData; + msg[0].len = w_count; + num_msgs = 1; + } else { + /* Both write and read */ + state = w_dev_addr->user_data; + msg[0].addr = w_dev_addr->i2c_addr >> 1; + msg[0].flags = 0; + msg[0].buf = wData; + msg[0].len = w_count; + msg[1].addr = r_dev_addr->i2c_addr >> 1; + msg[1].flags = I2C_M_RD; + msg[1].buf = r_data; + msg[1].len = r_count; + num_msgs = 2; + } + + if (state->i2c == NULL) { + pr_err("i2c was zero, aborting\n"); + return 0; + } + if (i2c_transfer(state->i2c, msg, num_msgs) != num_msgs) { + pr_warn("drx3933: I2C write/read failed\n"); + return -EREMOTEIO; + } + + return 0; + +#ifdef DJH_DEBUG + struct drx39xxj_state *state = w_dev_addr->user_data; + + struct i2c_msg msg[2] = { + {.addr = w_dev_addr->i2c_addr, + .flags = 0, .buf = wData, .len = w_count}, + {.addr = r_dev_addr->i2c_addr, + .flags = I2C_M_RD, .buf = r_data, .len = r_count}, + }; + + pr_dbg("drx3933 i2c operation addr=%x i2c=%p, wc=%x rc=%x\n", + w_dev_addr->i2c_addr, state->i2c, w_count, r_count); + + if (i2c_transfer(state->i2c, msg, 2) != 2) { + pr_warn("drx3933: I2C write/read failed\n"); + return -EREMOTEIO; + } +#endif + return 0; +} + /*============================================================================*/ /****************************** @@ -515,7 +592,7 @@ static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr, (data_block_size < datasize ? data_block_size : datasize); } - drxbsp_hst_memcpy(&buf[bufx], data, todo); + memcpy(&buf[bufx], data, todo); /* write (address if can do and) data */ st = drxbsp_i2c_write_read(dev_addr, (u16) (bufx + todo), diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h index daa9027..1aff810 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h @@ -225,10 +225,6 @@ struct tuner_instance { struct tuner_ops *my_funct; }; -int drxbsp_tuner_open(struct tuner_instance *tuner); - -int drxbsp_tuner_close(struct tuner_instance *tuner); - int drxbsp_tuner_set_frequency(struct tuner_instance *tuner, u32 mode, s32 frequency); @@ -238,9 +234,6 @@ int drxbsp_tuner_get_frequency(struct tuner_instance *tuner, s32 *r_ffrequency, s32 *i_ffrequency); -int drxbsp_tuner_lock_status(struct tuner_instance *tuner, - enum tuner_lock_status *lock_stat); - int drxbsp_tuner_default_i2c_write_read(struct tuner_instance *tuner, struct i2c_device_addr *w_dev_addr, u16 w_count, @@ -248,20 +241,6 @@ int drxbsp_tuner_default_i2c_write_read(struct tuner_instance *tuner, struct i2c_device_addr *r_dev_addr, u16 r_count, u8 *r_data); -int drxbsp_hst_init(void); - -int drxbsp_hst_term(void); - -void *drxbsp_hst_memcpy(void *to, void *from, u32 n); - -int drxbsp_hst_memcmp(void *s1, void *s2, u32 n); - -u32 drxbsp_hst_clock(void); - -int drxbsp_hst_sleep(u32 n); - - - /************** * * This section configures the DRX Data Access Protocols (DAPs). diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index 0dfb338..08e32d7 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -1710,7 +1710,7 @@ static int drxj_dap_read_aud_reg16(struct i2c_device_addr *dev_addr, addr &= (~write_bit); /* Set up read */ - start_timer = drxbsp_hst_clock(); + start_timer = jiffies_to_msecs(jiffies); do { /* RMW to aud TR IF until request is granted or timeout */ stat = drxj_dap_read_modify_write_reg16(dev_addr, @@ -1721,7 +1721,7 @@ static int drxj_dap_read_aud_reg16(struct i2c_device_addr *dev_addr, if (stat != 0) break; - current_timer = drxbsp_hst_clock(); + current_timer = jiffies_to_msecs(jiffies); delta_timer = current_timer - start_timer; if (delta_timer > DRXJ_DAP_AUDTRIF_TIMEOUT) { stat = -EIO; @@ -1736,7 +1736,7 @@ static int drxj_dap_read_aud_reg16(struct i2c_device_addr *dev_addr, /* Wait for read ready status or timeout */ if (stat == 0) { - start_timer = drxbsp_hst_clock(); + start_timer = jiffies_to_msecs(jiffies); while ((tr_status & AUD_TOP_TR_CTR_FIFO_RD_RDY__M) != AUD_TOP_TR_CTR_FIFO_RD_RDY_READY) { @@ -1746,7 +1746,7 @@ static int drxj_dap_read_aud_reg16(struct i2c_device_addr *dev_addr, if (stat != 0) break; - current_timer = drxbsp_hst_clock(); + current_timer = jiffies_to_msecs(jiffies); delta_timer = current_timer - start_timer; if (delta_timer > DRXJ_DAP_AUDTRIF_TIMEOUT) { stat = -EIO; @@ -1846,7 +1846,7 @@ static int drxj_dap_write_aud_reg16(struct i2c_device_addr *dev_addr, /* Force write bit */ addr |= write_bit; - start_timer = drxbsp_hst_clock(); + start_timer = jiffies_to_msecs(jiffies); do { /* RMW to aud TR IF until request is granted or timeout */ stat = drxj_dap_read_modify_write_reg16(dev_addr, @@ -1856,7 +1856,7 @@ static int drxj_dap_write_aud_reg16(struct i2c_device_addr *dev_addr, if (stat != 0) break; - current_timer = drxbsp_hst_clock(); + current_timer = jiffies_to_msecs(jiffies); delta_timer = current_timer - start_timer; if (delta_timer > DRXJ_DAP_AUDTRIF_TIMEOUT) { stat = -EIO; @@ -2160,7 +2160,7 @@ hi_command(struct i2c_device_addr *dev_addr, const struct drxj_hi_cmd *cmd, u16 } if ((cmd->cmd) == SIO_HI_RA_RAM_CMD_RESET) - drxbsp_hst_sleep(1); + msleep(1); /* Detect power down to ommit reading result */ powerdown_cmd = (bool) ((cmd->cmd == SIO_HI_RA_RAM_CMD_CONFIG) && @@ -2519,7 +2519,7 @@ static int power_up_device(struct drx_demod_instance *demod) drxbsp_i2c_write_read(&wake_up_addr, 1, &data, (struct i2c_device_addr *)(NULL), 0, (u8 *)(NULL)); - drxbsp_hst_sleep(10); + msleep(10); retry_count++; } while ((drxbsp_i2c_write_read ((struct i2c_device_addr *) (NULL), 0, (u8 *)(NULL), dev_addr, 1, @@ -2527,7 +2527,7 @@ static int power_up_device(struct drx_demod_instance *demod) != 0) && (retry_count < DRXJ_MAX_RETRIES_POWERUP)); /* Need some recovery time .... */ - drxbsp_hst_sleep(10); + msleep(10); if (retry_count == DRXJ_MAX_RETRIES_POWERUP) return -EIO; @@ -4351,14 +4351,14 @@ ctrl_set_cfg_smart_ant(struct drx_demod_instance *demod, struct drxj_cfg_smart_a RR16( dev_addr, SIO_SA_TX_COMMAND__A, &data ); WR16( dev_addr, SIO_SA_TX_COMMAND__A, data | SIO_SA_TX_COMMAND_TX_ENABLE__M ); */ - start_time = drxbsp_hst_clock(); + start_time = jiffies_to_msecs(jiffies); do { rc = DRXJ_DAP.read_reg16func(dev_addr, SIO_SA_TX_STATUS__A, &data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - } while ((data & SIO_SA_TX_STATUS_BUSY__M) && ((drxbsp_hst_clock() - start_time) < DRXJ_MAX_WAITTIME)); + } while ((data & SIO_SA_TX_STATUS_BUSY__M) && ((jiffies_to_msecs(jiffies) - start_time) < DRXJ_MAX_WAITTIME)); if (data & SIO_SA_TX_STATUS_BUSY__M) return -EIO; @@ -4479,7 +4479,7 @@ static int scu_command(struct i2c_device_addr *dev_addr, struct drxjscu_cmd *cmd } /* Wait until SCU has processed command */ - start_time = drxbsp_hst_clock(); + start_time = jiffies_to_msecs(jiffies); do { rc = DRXJ_DAP.read_reg16func(dev_addr, SCU_RAM_COMMAND__A, &cur_cmd, 0); if (rc != 0) { @@ -4487,7 +4487,7 @@ static int scu_command(struct i2c_device_addr *dev_addr, struct drxjscu_cmd *cmd goto rw_error; } } while (!(cur_cmd == DRX_SCU_READY) - && ((drxbsp_hst_clock() - start_time) < DRXJ_MAX_WAITTIME)); + && ((jiffies_to_msecs(jiffies) - start_time) < DRXJ_MAX_WAITTIME)); if (cur_cmd != DRX_SCU_READY) return -EIO; @@ -4704,11 +4704,7 @@ static int adc_sync_measurement(struct drx_demod_instance *demod, u16 *count) } /* Wait at least 3*128*(1/sysclk) <<< 1 millisec */ - rc = drxbsp_hst_sleep(1); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } + msleep(1); *count = 0; rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_PHASE0__A, &data, 0); @@ -10191,7 +10187,7 @@ qam64auto(struct drx_demod_instance *demod, /* external attributes for storing aquired channel constellation */ ext_attr = (struct drxj_data *) demod->my_ext_attr; *lock_status = DRX_NOT_LOCKED; - start_time = drxbsp_hst_clock(); + start_time = jiffies_to_msecs(jiffies); state = NO_LOCK; do { rc = ctrl_lock_status(demod, lock_status); @@ -10212,13 +10208,13 @@ qam64auto(struct drx_demod_instance *demod, state = DEMOD_LOCKED; /* some delay to see if fec_lock possible TODO find the right value */ timeout_ofs += DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME; /* see something, waiting longer */ - d_locked_time = drxbsp_hst_clock(); + d_locked_time = jiffies_to_msecs(jiffies); } } break; case DEMOD_LOCKED: if ((*lock_status == DRXJ_DEMOD_LOCK) && /* still demod_lock in 150ms */ - ((drxbsp_hst_clock() - d_locked_time) > + ((jiffies_to_msecs(jiffies) - d_locked_time) > DRXJ_QAM_FEC_LOCK_WAITTIME)) { rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0); if (rc != 0) { @@ -10231,7 +10227,7 @@ qam64auto(struct drx_demod_instance *demod, goto rw_error; } state = SYNC_FLIPPED; - drxbsp_hst_sleep(10); + msleep(10); } break; case SYNC_FLIPPED: @@ -10258,19 +10254,19 @@ qam64auto(struct drx_demod_instance *demod, state = SPEC_MIRRORED; /* reset timer TODO: still need 500ms? */ start_time = d_locked_time = - drxbsp_hst_clock(); + jiffies_to_msecs(jiffies); timeout_ofs = 0; } else { /* no need to wait lock */ start_time = - drxbsp_hst_clock() - + jiffies_to_msecs(jiffies) - DRXJ_QAM_MAX_WAITTIME - timeout_ofs; } } break; case SPEC_MIRRORED: if ((*lock_status == DRXJ_DEMOD_LOCK) && /* still demod_lock in 150ms */ - ((drxbsp_hst_clock() - d_locked_time) > + ((jiffies_to_msecs(jiffies) - d_locked_time) > DRXJ_QAM_FEC_LOCK_WAITTIME)) { rc = ctrl_get_qam_sig_quality(demod, &sig_quality); if (rc != 0) { @@ -10290,7 +10286,7 @@ qam64auto(struct drx_demod_instance *demod, } /* no need to wait lock */ start_time = - drxbsp_hst_clock() - + jiffies_to_msecs(jiffies) - DRXJ_QAM_MAX_WAITTIME - timeout_ofs; } } @@ -10298,11 +10294,11 @@ qam64auto(struct drx_demod_instance *demod, default: break; } - drxbsp_hst_sleep(10); + msleep(10); } while ((*lock_status != DRX_LOCKED) && (*lock_status != DRX_NEVER_LOCK) && - ((drxbsp_hst_clock() - start_time) < + ((jiffies_to_msecs(jiffies) - start_time) < (DRXJ_QAM_MAX_WAITTIME + timeout_ofs)) ); /* Returning control to apllication ... */ @@ -10337,7 +10333,7 @@ qam256auto(struct drx_demod_instance *demod, /* external attributes for storing aquired channel constellation */ ext_attr = (struct drxj_data *) demod->my_ext_attr; *lock_status = DRX_NOT_LOCKED; - start_time = drxbsp_hst_clock(); + start_time = jiffies_to_msecs(jiffies); state = NO_LOCK; do { rc = ctrl_lock_status(demod, lock_status); @@ -10356,14 +10352,14 @@ qam256auto(struct drx_demod_instance *demod, if (sig_quality.MER > 268) { state = DEMOD_LOCKED; timeout_ofs += DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME; /* see something, wait longer */ - d_locked_time = drxbsp_hst_clock(); + d_locked_time = jiffies_to_msecs(jiffies); } } break; case DEMOD_LOCKED: if (*lock_status == DRXJ_DEMOD_LOCK) { if ((channel->mirror == DRX_MIRROR_AUTO) && - ((drxbsp_hst_clock() - d_locked_time) > + ((jiffies_to_msecs(jiffies) - d_locked_time) > DRXJ_QAM_FEC_LOCK_WAITTIME)) { ext_attr->mirror = DRX_MIRROR_YES; rc = qam_flip_spec(demod, channel); @@ -10373,7 +10369,7 @@ qam256auto(struct drx_demod_instance *demod, } state = SPEC_MIRRORED; /* reset timer TODO: still need 300ms? */ - start_time = drxbsp_hst_clock(); + start_time = jiffies_to_msecs(jiffies); timeout_ofs = -DRXJ_QAM_MAX_WAITTIME / 2; } } @@ -10383,11 +10379,11 @@ qam256auto(struct drx_demod_instance *demod, default: break; } - drxbsp_hst_sleep(10); + msleep(10); } while ((*lock_status < DRX_LOCKED) && (*lock_status != DRX_NEVER_LOCK) && - ((drxbsp_hst_clock() - start_time) < + ((jiffies_to_msecs(jiffies) - start_time) < (DRXJ_QAM_MAX_WAITTIME + timeout_ofs))); return 0; @@ -19662,11 +19658,7 @@ int drxj_open(struct drx_demod_instance *demod) pr_err("error %d\n", rc); goto rw_error; } - rc = drxbsp_hst_sleep(1); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } + msleep(1); /* TODO first make sure that everything keeps working before enabling this */ /* PowerDownAnalogBlocks() */ @@ -19761,12 +19753,6 @@ int drxj_open(struct drx_demod_instance *demod) } } - rc = drxbsp_tuner_open(demod->my_tuner); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - if (common_attr->tuner_port_nr == 1) { bool bridge_closed = false; rc = ctrl_i2c_bridge(demod, &bridge_closed); @@ -19873,11 +19859,6 @@ int drxj_close(struct drx_demod_instance *demod) goto rw_error; } } - rc = drxbsp_tuner_close(demod->my_tuner); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } if (common_attr->tuner_port_nr == 1) { bool bridge_closed = false; rc = ctrl_i2c_bridge(demod, &bridge_closed); @@ -20185,9 +20166,8 @@ static int drx_ctrl_u_code(struct drx_demod_instance *demod, return -EIO; } - result =drxbsp_hst_memcmp(curr_ptr, - mc_data_buffer, - bytes_to_comp); + result = memcmp(curr_ptr, mc_data_buffer, + bytes_to_comp); if (result) { pr_err("error verifying firmware at pos %u\n", -- cgit v1.1 From a6530ce54b6081c168329e18839005b486eaf90e Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sun, 26 Jan 2014 14:54:08 -0300 Subject: [media] drx-j: get rid of tuner dummy get/set frequency Those functions will never be used with Linux DVB binding. Get rid of them. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- .../media/dvb-frontends/drx39xyj/drx39xxj_dummy.c | 21 -- drivers/media/dvb-frontends/drx39xyj/drx_driver.h | 3 - drivers/media/dvb-frontends/drx39xyj/drxj.c | 217 +-------------------- 3 files changed, 3 insertions(+), 238 deletions(-) delete mode 100644 drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c b/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c deleted file mode 100644 index 33413cd..0000000 --- a/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c +++ /dev/null @@ -1,21 +0,0 @@ -/* Dummy function to satisfy drxj.c */ - -#include -#include "drx_driver.h" - - -int drxbsp_tuner_set_frequency(struct tuner_instance *tuner, - u32 mode, - s32 center_frequency) -{ - return 0; -} - -int -drxbsp_tuner_get_frequency(struct tuner_instance *tuner, - u32 mode, - s32 *r_ffrequency, - s32 *i_ffrequency) -{ - return 0; -} diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h index 1aff810..aabd5c56 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h @@ -1944,8 +1944,6 @@ struct drx_demod_instance { /* type specific demodulator data */ struct drx_access_func *my_access_funct; /**< data access protocol functions */ - struct tuner_instance *my_tuner; - /**< tuner instance,if NULL then baseband */ struct i2c_device_addr *my_i2c_dev_addr; /**< i2c address and device identifier */ struct drx_common_attr *my_common_attr; @@ -2269,7 +2267,6 @@ Access macros #define DRX_ATTR_TUNERIFAGCPOL(d) ((d)->my_common_attr->tuner_if_agc_pol) #define DRX_ATTR_TUNERSLOWMODE(d) ((d)->my_common_attr->tuner_slow_mode) #define DRX_ATTR_TUNERSPORTNR(d) ((d)->my_common_attr->tuner_port_nr) -#define DRX_ATTR_TUNER(d) ((d)->my_tuner) #define DRX_ATTR_I2CADDR(d) ((d)->my_i2c_dev_addr->i2c_addr) #define DRX_ATTR_I2CDEVID(d) ((d)->my_i2c_dev_addr->i2c_dev_id) #define DRX_ISMCVERTYPE(x) ((x) == AUX_VER_RECORD) diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index 08e32d7..c9608e6 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -945,7 +945,6 @@ struct drx_common_attr drxj_default_comm_attr_g = { */ struct drx_demod_instance drxj_default_demod_g = { &DRXJ_DAP, /* data access protocol functions */ - NULL, /* tuner instance */ &drxj_default_addr_g, /* i2c address & device id */ &drxj_default_comm_attr_g, /* demod common attributes */ &drxj_data_g /* demod device specific attributes */ @@ -16990,16 +16989,12 @@ static int ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) { int rc; - s32 tuner_set_freq = 0; - s32 tuner_get_freq = 0; s32 tuner_freq_offset = 0; s32 intermediate_freq = 0; struct drxj_data *ext_attr = NULL; struct i2c_device_addr *dev_addr = NULL; enum drx_standard standard = DRX_STANDARD_UNKNOWN; - u32 tuner_mode = 0; struct drx_common_attr *common_attr = NULL; - bool bridge_closed = false; #ifndef DRXJ_VSB_ONLY u32 min_symbol_rate = 0; u32 max_symbol_rate = 0; @@ -17206,108 +17201,9 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) pr_err("error %d\n", rc); goto rw_error; } - /*== Tune, fast mode ======================================================*/ - if (demod->my_tuner != NULL) { - /* Determine tuner mode and freq to tune to ... */ - switch (standard) { -#if 0 - case DRX_STANDARD_NTSC: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_LP: - /* expecting center frequency, not picture carrier so no - conversion .... */ - tuner_mode |= TUNER_MODE_ANALOG; - tuner_set_freq = channel->frequency; - break; - case DRX_STANDARD_FM: - /* center frequency (equals sound carrier) as input, - tune to edge of SAW */ - tuner_mode |= TUNER_MODE_ANALOG; - tuner_set_freq = - channel->frequency + DRXJ_FM_CARRIER_FREQ_OFFSET; - break; -#endif - case DRX_STANDARD_8VSB: /* fallthrough */ -#ifndef DRXJ_VSB_ONLY - case DRX_STANDARD_ITU_A: /* fallthrough */ - case DRX_STANDARD_ITU_B: /* fallthrough */ - case DRX_STANDARD_ITU_C: -#endif - tuner_mode |= TUNER_MODE_DIGITAL; - tuner_set_freq = channel->frequency; - break; - case DRX_STANDARD_UNKNOWN: - default: - return -EIO; - } /* switch(standard) */ - tuner_mode |= TUNER_MODE_SWITCH; - switch (channel->bandwidth) { - case DRX_BANDWIDTH_8MHZ: - tuner_mode |= TUNER_MODE_8MHZ; - break; - case DRX_BANDWIDTH_7MHZ: - tuner_mode |= TUNER_MODE_7MHZ; - break; - case DRX_BANDWIDTH_6MHZ: - tuner_mode |= TUNER_MODE_6MHZ; - break; - default: - /* TODO: for FM which bandwidth to use ? - also check offset from centre frequency ? - For now using 6MHz. - */ - tuner_mode |= TUNER_MODE_6MHZ; - break; - /* return (-EINVAL); */ - } - - /* store bandwidth for GetChannel() */ - ext_attr->curr_bandwidth = channel->bandwidth; - ext_attr->curr_symbol_rate = channel->symbolrate; - ext_attr->frequency = tuner_set_freq; - if (common_attr->tuner_port_nr == 1) { - /* close tuner bridge */ - bridge_closed = true; - rc = ctrl_i2c_bridge(demod, &bridge_closed); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - /* set tuner frequency */ - } - - rc = drxbsp_tuner_set_frequency(demod->my_tuner, tuner_mode, tuner_set_freq); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - if (common_attr->tuner_port_nr == 1) { - /* open tuner bridge */ - bridge_closed = false; - rc = ctrl_i2c_bridge(demod, &bridge_closed); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - } - - /* Get actual frequency set by tuner and compute offset */ - rc = drxbsp_tuner_get_frequency(demod->my_tuner, 0, &tuner_get_freq, &intermediate_freq); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - tuner_freq_offset = tuner_get_freq - tuner_set_freq; - common_attr->intermediate_freq = intermediate_freq; - } else { - /* no tuner instance defined, use fixed intermediate frequency */ - tuner_freq_offset = 0; - intermediate_freq = demod->my_common_attr->intermediate_freq; - } /* if ( demod->my_tuner != NULL ) */ + tuner_freq_offset = 0; + intermediate_freq = demod->my_common_attr->intermediate_freq; /*== Setup demod for specific standard ====================================*/ switch (standard) { @@ -17362,40 +17258,6 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) return -EIO; } - /*== Re-tune, slow mode ===================================================*/ - if (demod->my_tuner != NULL) { - /* tune to slow mode */ - tuner_mode &= ~TUNER_MODE_SWITCH; - tuner_mode |= TUNER_MODE_LOCK; - - if (common_attr->tuner_port_nr == 1) { - /* close tuner bridge */ - bridge_closed = true; - rc = ctrl_i2c_bridge(demod, &bridge_closed); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - } - - /* set tuner frequency */ - rc = drxbsp_tuner_set_frequency(demod->my_tuner, tuner_mode, tuner_set_freq); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - if (common_attr->tuner_port_nr == 1) { - /* open tuner bridge */ - bridge_closed = false; - rc = ctrl_i2c_bridge(demod, &bridge_closed); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - } - } - - /* if ( demod->my_tuner !=NULL ) */ /* flag the packet error counter reset */ ext_attr->reset_pkt_err_acc = true; @@ -17459,31 +17321,7 @@ ctrl_get_channel(struct drx_demod_instance *demod, struct drx_channel *channel) /* channel->interleaver = DRX_INTERLEAVER_UNKNOWN;*/ channel->ldpc = DRX_LDPC_UNKNOWN; - if (demod->my_tuner != NULL) { - s32 tuner_freq_offset = 0; - bool tuner_mirror = common_attr->mirror_freq_spect ? false : true; - - /* Get frequency from tuner */ - rc = drxbsp_tuner_get_frequency(demod->my_tuner, 0, &(channel->frequency), &intermediate_freq); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - tuner_freq_offset = channel->frequency - ext_attr->frequency; - if (tuner_mirror) { - /* positive image */ - channel->frequency += tuner_freq_offset; - } else { - /* negative image */ - channel->frequency -= tuner_freq_offset; - } - - /* Handle sound carrier offset in RF domain */ - if (standard == DRX_STANDARD_FM) - channel->frequency -= DRXJ_FM_CARRIER_FREQ_OFFSET; - } else { - intermediate_freq = common_attr->intermediate_freq; - } + intermediate_freq = common_attr->intermediate_freq; /* check lock status */ rc = ctrl_lock_status(demod, &lock_status); @@ -19740,33 +19578,6 @@ int drxj_open(struct drx_demod_instance *demod) goto rw_error; } - /* Open tuner instance */ - if (demod->my_tuner != NULL) { - demod->my_tuner->my_common_attr->my_user_data = (void *)demod; - - if (common_attr->tuner_port_nr == 1) { - bool bridge_closed = true; - rc = ctrl_i2c_bridge(demod, &bridge_closed); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - } - - if (common_attr->tuner_port_nr == 1) { - bool bridge_closed = false; - rc = ctrl_i2c_bridge(demod, &bridge_closed); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - } - common_attr->tuner_min_freq_rf = - ((demod->my_tuner)->my_common_attr->min_freq_rf); - common_attr->tuner_max_freq_rf = - ((demod->my_tuner)->my_common_attr->max_freq_rf); - } - /* Initialize scan timeout */ common_attr->scan_demod_lock_timeout = DRXJ_SCAN_TIMEOUT; common_attr->scan_desired_lock = DRX_LOCKED; @@ -19830,7 +19641,6 @@ rw_error: int drxj_close(struct drx_demod_instance *demod) { struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; - struct drx_common_attr *common_attr = demod->my_common_attr; int rc; enum drx_power_mode power_mode = DRX_POWER_UP; @@ -19849,26 +19659,6 @@ int drxj_close(struct drx_demod_instance *demod) goto rw_error; } - if (demod->my_tuner != NULL) { - /* Check if bridge is used */ - if (common_attr->tuner_port_nr == 1) { - bool bridge_closed = true; - rc = ctrl_i2c_bridge(demod, &bridge_closed); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - } - if (common_attr->tuner_port_nr == 1) { - bool bridge_closed = false; - rc = ctrl_i2c_bridge(demod, &bridge_closed); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - } - } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0); if (rc != 0) { pr_err("error %d\n", rc); @@ -20581,7 +20371,6 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) demod->my_common_attr->intermediate_freq = 5000; demod->my_ext_attr = demod_ext_attr; ((struct drxj_data *)demod_ext_attr)->uio_sma_tx_mode = DRX_UIO_MODE_READWRITE; - demod->my_tuner = NULL; demod->i2c = i2c; result = drxj_open(demod); -- cgit v1.1 From 7abc7a54dad585311252a07c8edfa3840537a3e9 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sun, 26 Jan 2014 15:02:25 -0300 Subject: [media] drx-j: be sure to use tuner's IF Instead of just hardcoding an IF value of 5MHz, use the one provided by the tuner, with can be different for QAM and VSB. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drxj.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index c9608e6..ccd847e1 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -20171,11 +20171,21 @@ static int drx39xxj_set_frontend(struct dvb_frontend *fe) /* Bring the demod out of sleep */ drx39xxj_set_powerstate(fe, 1); - /* Now make the tuner do it's thing... */ if (fe->ops.tuner_ops.set_params) { + u32 int_freq; + if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 1); + + /* Set tuner to desired frequency and standard */ fe->ops.tuner_ops.set_params(fe); + + /* Use the tuner's IF */ + if (fe->ops.tuner_ops.get_if_frequency) { + fe->ops.tuner_ops.get_if_frequency(fe, &int_freq); + demod->my_common_attr->intermediate_freq = int_freq / 1000; + } + if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0); } -- cgit v1.1 From c76286bafc682740a3c83aebeacb2d304bd39184 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sun, 26 Jan 2014 15:30:53 -0300 Subject: [media] drx-j: avoid calling power_down_foo twice When switching from one video standard to another one, power_down_vsb is called twice. Well, as the device is already in power_down mode, the second call always fail. This causes that any subsequent frontend set to fail as well: [145074.501243] drx39xyj:power_down_vsb: called [145089.195396] drx39xyj:power_down_vsb: error -5 [145089.195404] drx39xyj:ctrl_set_standard: error -5 [145089.195417] drx39xyj:drx39xxj_set_frontend: Failed to set standard! result=fffffffb [145089.195470] drx39xyj:ctrl_sig_quality: error -5 [145089.195473] drx39xyj:drx39xxj_read_ber: drx39xxj: could not get ber! [145089.195475] drx39xyj:ctrl_sig_quality: error -5 [145089.195477] drx39xyj:drx39xxj_read_signal_strength: drx39xxj: could not get signal strength! [145089.195479] drx39xyj:ctrl_sig_quality: error -5 [145089.195480] drx39xyj:drx39xxj_read_snr: drx39xxj: could not read snr! [145089.195482] drx39xyj:ctrl_sig_quality: error -5 [145089.195484] drx39xyj:drx39xxj_read_ucblocks: drx39xxj: could not get uc blocks! [145089.195498] drx39xyj:ctrl_sig_quality: error -5 [145089.195500] drx39xyj:drx39xxj_read_ber: drx39xxj: could not get ber! [145089.195502] drx39xyj:ctrl_sig_quality: error -5 [145089.195503] drx39xyj:drx39xxj_read_signal_strength: drx39xxj: could not get signal strength! [145089.195505] drx39xyj:ctrl_sig_quality: error -5 [145089.195506] drx39xyj:drx39xxj_read_snr: drx39xxj: could not read snr! [145089.195508] drx39xyj:ctrl_sig_quality: error -5 [145089.195510] drx39xyj:drx39xxj_read_ucblocks: drx39xxj: could not get uc blocks! [145090.196291] drx39xyj:drx39xxj_read_status: drx39xxj: could not get lock status! [145090.196508] drx39xyj:ctrl_sig_quality: error -5 [145090.196511] drx39xyj:drx39xxj_read_ber: drx39xxj: could not get ber! [145090.196514] drx39xyj:ctrl_sig_quality: error -5 [145090.196515] drx39xyj:drx39xxj_read_signal_strength: drx39xxj: could not get signal strength! [145090.196518] drx39xyj:ctrl_sig_quality: error -5 [145090.196519] drx39xyj:drx39xxj_read_snr: drx39xxj: could not read snr! [145090.196522] drx39xyj:ctrl_sig_quality: error -5 [145090.196523] drx39xyj:drx39xxj_read_ucblocks: drx39xxj: could not get uc blocks! [145090.196553] drx39xyj:ctrl_sig_quality: error -5 [145090.196554] drx39xyj:drx39xxj_read_ber: drx39xxj: could not get ber! [145090.196557] drx39xyj:ctrl_sig_quality: error -5 [145090.196558] drx39xyj:drx39xxj_read_signal_strength: drx39xxj: could not get signal strength! [145090.196560] drx39xyj:ctrl_sig_quality: error -5 [145090.196562] drx39xyj:drx39xxj_read_snr: drx39xxj: could not read snr! [145090.196564] drx39xyj:ctrl_sig_quality: error -5 [145090.196565] drx39xyj:drx39xxj_read_ucblocks: drx39xxj: could not get uc blocks! [145091.119265] drx39xyj:ctrl_sig_quality: error -5 [145091.119271] drx39xyj:drx39xxj_read_ber: drx39xxj: could not get ber! [145091.119274] drx39xyj:ctrl_sig_quality: error -5 [145091.119276] drx39xyj:drx39xxj_read_signal_strength: drx39xxj: could not get signal strength! [145091.119278] drx39xyj:ctrl_sig_quality: error -5 [145091.119280] drx39xyj:drx39xxj_read_snr: drx39xxj: could not read snr! [145091.119282] drx39xyj:ctrl_sig_quality: error -5 [145091.119283] drx39xyj:drx39xxj_read_ucblocks: drx39xxj: could not get uc blocks! Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drxj.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index ccd847e1..7f17cd1 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -18264,6 +18264,7 @@ ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode) goto rw_error; } } + ext_attr->standard = DRX_STANDARD_UNKNOWN; } common_attr->current_power_mode = *mode; -- cgit v1.1 From c4dc6f9222a621c1d1f44120590093d2d58441d4 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sun, 26 Jan 2014 15:39:06 -0300 Subject: [media] drx-j: call ctrl_set_standard even if a standard is powered Modulation and other parameters might have changed. So, better to call ctrl_set_standard() even if the device is already powered. That helps to put the device into a sane state, if something got wrong on a previous set_frontend call. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drxj.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index 7f17cd1..b1a7dfe 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -20213,18 +20213,15 @@ static int drx39xxj_set_frontend(struct dvb_frontend *fe) default: return -EINVAL; } - - if (standard != state->current_standard || state->powered_up == 0) { - /* Set the standard (will be powered up if necessary */ - result = ctrl_set_standard(demod, &standard); - if (result != 0) { - pr_err("Failed to set standard! result=%02x\n", - result); - return -EINVAL; - } - state->powered_up = 1; - state->current_standard = standard; + /* Set the standard (will be powered up if necessary */ + result = ctrl_set_standard(demod, &standard); + if (result != 0) { + pr_err("Failed to set standard! result=%02x\n", + result); + return -EINVAL; } + state->powered_up = 1; + state->current_standard = standard; /* set channel parameters */ channel = def_channel; -- cgit v1.1 From ceea5e2d9dc2334c6a4b167b6134f5cd740b8e0b Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sun, 26 Jan 2014 15:55:57 -0300 Subject: [media] drx-j: use the proper timeout code on scu_command Checking if a time is after another one can have issues, as times are generally u32 wide. Use the proper macros for that at scu_command(). It should be noticed that other places also use jiffies calculus on an improper way. This should be fixed too, but the logic there is more complex. So, let's do it in separate patches. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drxj.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index b1a7dfe..c843d8f 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -4417,8 +4417,8 @@ rw_error: static int scu_command(struct i2c_device_addr *dev_addr, struct drxjscu_cmd *cmd) { int rc; - u32 start_time = 0; u16 cur_cmd = 0; + unsigned long timeout; /* Check param */ if (cmd == NULL) @@ -4478,15 +4478,17 @@ static int scu_command(struct i2c_device_addr *dev_addr, struct drxjscu_cmd *cmd } /* Wait until SCU has processed command */ - start_time = jiffies_to_msecs(jiffies); - do { + timeout = jiffies + msecs_to_jiffies(DRXJ_MAX_WAITTIME); + while (time_is_after_jiffies(timeout)) { rc = DRXJ_DAP.read_reg16func(dev_addr, SCU_RAM_COMMAND__A, &cur_cmd, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - } while (!(cur_cmd == DRX_SCU_READY) - && ((jiffies_to_msecs(jiffies) - start_time) < DRXJ_MAX_WAITTIME)); + if (cur_cmd == DRX_SCU_READY) + break; + usleep_range(1000, 2000); + } if (cur_cmd != DRX_SCU_READY) return -EIO; -- cgit v1.1 From 096c8fac7d5385b4597bb6896284e62b1849161b Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sun, 26 Jan 2014 16:07:53 -0300 Subject: [media] drx-j: remove some unused data Those struct data aren't used anymore. Get rid of them. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drx39xxj.h | 2 -- drivers/media/dvb-frontends/drx39xyj/drxj.c | 3 --- 2 files changed, 5 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h index b9f642e..2e0c50f 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h @@ -29,9 +29,7 @@ struct drx39xxj_state { struct i2c_adapter *i2c; struct drx_demod_instance *demod; - enum drx_standard current_standard; struct dvb_frontend frontend; - unsigned int powered_up:1; unsigned int i2c_gate_open:1; const struct firmware *fw; }; diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index c843d8f..6fe65f4 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -20015,7 +20015,6 @@ static int drx39xxj_set_powerstate(struct dvb_frontend *fe, int enable) return 0; } - state->powered_up = enable; return 0; } @@ -20222,8 +20221,6 @@ static int drx39xxj_set_frontend(struct dvb_frontend *fe) result); return -EINVAL; } - state->powered_up = 1; - state->current_standard = standard; /* set channel parameters */ channel = def_channel; -- cgit v1.1 From 938f11fa3fd55538b4406aece0ea22174c1f2b96 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sun, 26 Jan 2014 16:41:51 -0300 Subject: [media] drx-j: Fix qam/256 mode QAM/256 currently doesn't work, as the code is only called if channel->mirror is DRX_MIRROR_AUTO, but a prevous if prevents this condition to happen. While here, returns -EINVAL to not supported QAM modes and simplify the code, reducing the number of indents. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drxj.c | 205 +++++++++++++++------------- 1 file changed, 113 insertions(+), 92 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index 6fe65f4..8f2f265 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -10415,107 +10415,122 @@ set_qam_channel(struct drx_demod_instance *demod, switch (channel->constellation) { case DRX_CONSTELLATION_QAM16: case DRX_CONSTELLATION_QAM32: - case DRX_CONSTELLATION_QAM64: case DRX_CONSTELLATION_QAM128: + return -EINVAL; + case DRX_CONSTELLATION_QAM64: case DRX_CONSTELLATION_QAM256: + if (ext_attr->standard != DRX_STANDARD_ITU_B) + return -EINVAL; + ext_attr->constellation = channel->constellation; if (channel->mirror == DRX_MIRROR_AUTO) ext_attr->mirror = DRX_MIRROR_NO; else ext_attr->mirror = channel->mirror; + rc = set_qam(demod, channel, tuner_freq_offset, QAM_SET_OP_ALL); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - if ((ext_attr->standard == DRX_STANDARD_ITU_B) && - (channel->constellation == DRX_CONSTELLATION_QAM64)) { - rc = qam64auto(demod, channel, tuner_freq_offset, &lock_status); + if (channel->constellation == DRX_CONSTELLATION_QAM64) + rc = qam64auto(demod, channel, tuner_freq_offset, + &lock_status); + else + rc = qam256auto(demod, channel, tuner_freq_offset, + &lock_status); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + case DRX_CONSTELLATION_AUTO: /* for channel scan */ + if (ext_attr->standard == DRX_STANDARD_ITU_B) { + u16 qam_ctl_ena = 0; + + auto_flag = true; + + /* try to lock default QAM constellation: QAM256 */ + channel->constellation = DRX_CONSTELLATION_QAM256; + ext_attr->constellation = DRX_CONSTELLATION_QAM256; + if (channel->mirror == DRX_MIRROR_AUTO) + ext_attr->mirror = DRX_MIRROR_NO; + else + ext_attr->mirror = channel->mirror; + rc = set_qam(demod, channel, tuner_freq_offset, + QAM_SET_OP_ALL); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - } - - if ((ext_attr->standard == DRX_STANDARD_ITU_B) && - (channel->mirror == DRX_MIRROR_AUTO) && - (channel->constellation == DRX_CONSTELLATION_QAM256)) { - rc = qam256auto(demod, channel, tuner_freq_offset, &lock_status); + rc = qam256auto(demod, channel, tuner_freq_offset, + &lock_status); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - } - break; - case DRX_CONSTELLATION_AUTO: /* for channel scan */ - if (ext_attr->standard == DRX_STANDARD_ITU_B) { - auto_flag = true; - /* try to lock default QAM constellation: QAM64 */ - channel->constellation = DRX_CONSTELLATION_QAM256; - ext_attr->constellation = DRX_CONSTELLATION_QAM256; + + if (lock_status >= DRX_LOCKED) { + channel->constellation = DRX_CONSTELLATION_AUTO; + break; + } + + /* QAM254 not locked. Try QAM64 constellation */ + channel->constellation = DRX_CONSTELLATION_QAM64; + ext_attr->constellation = DRX_CONSTELLATION_QAM64; if (channel->mirror == DRX_MIRROR_AUTO) ext_attr->mirror = DRX_MIRROR_NO; else ext_attr->mirror = channel->mirror; - rc = set_qam(demod, channel, tuner_freq_offset, QAM_SET_OP_ALL); + + rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, + SCU_RAM_QAM_CTL_ENA__A, + &qam_ctl_ena, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = qam256auto(demod, channel, tuner_freq_offset, &lock_status); + rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, + SCU_RAM_QAM_CTL_ENA__A, + qam_ctl_ena & ~SCU_RAM_QAM_CTL_ENA_ACQ__M, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } + rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, + SCU_RAM_QAM_FSM_STATE_TGT__A, + 0x2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /* force to rate hunting */ - if (lock_status < DRX_LOCKED) { - /* QAM254 not locked -> try to lock QAM64 constellation */ - channel->constellation = - DRX_CONSTELLATION_QAM64; - ext_attr->constellation = - DRX_CONSTELLATION_QAM64; - if (channel->mirror == DRX_MIRROR_AUTO) - ext_attr->mirror = DRX_MIRROR_NO; - else - ext_attr->mirror = channel->mirror; - { - u16 qam_ctl_ena = 0; - rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SCU_RAM_QAM_CTL_ENA__A, &qam_ctl_ena, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SCU_RAM_QAM_CTL_ENA__A, qam_ctl_ena & ~SCU_RAM_QAM_CTL_ENA_ACQ__M, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SCU_RAM_QAM_FSM_STATE_TGT__A, 0x2, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } /* force to rate hunting */ + rc = set_qam(demod, channel, tuner_freq_offset, + QAM_SET_OP_CONSTELLATION); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, + SCU_RAM_QAM_CTL_ENA__A, + qam_ctl_ena, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } - rc = set_qam(demod, channel, tuner_freq_offset, QAM_SET_OP_CONSTELLATION); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SCU_RAM_QAM_CTL_ENA__A, qam_ctl_ena, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - } - rc = qam64auto(demod, channel, tuner_freq_offset, &lock_status); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } + rc = qam64auto(demod, channel, tuner_freq_offset, + &lock_status); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; } + channel->constellation = DRX_CONSTELLATION_AUTO; } else if (ext_attr->standard == DRX_STANDARD_ITU_C) { + u16 qam_ctl_ena = 0; + channel->constellation = DRX_CONSTELLATION_QAM64; ext_attr->constellation = DRX_CONSTELLATION_QAM64; auto_flag = true; @@ -10524,43 +10539,49 @@ set_qam_channel(struct drx_demod_instance *demod, ext_attr->mirror = DRX_MIRROR_NO; else ext_attr->mirror = channel->mirror; - { - u16 qam_ctl_ena = 0; - rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SCU_RAM_QAM_CTL_ENA__A, &qam_ctl_ena, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SCU_RAM_QAM_CTL_ENA__A, qam_ctl_ena & ~SCU_RAM_QAM_CTL_ENA_ACQ__M, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SCU_RAM_QAM_FSM_STATE_TGT__A, 0x2, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } /* force to rate hunting */ + rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, + SCU_RAM_QAM_CTL_ENA__A, + &qam_ctl_ena, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, + SCU_RAM_QAM_CTL_ENA__A, + qam_ctl_ena & ~SCU_RAM_QAM_CTL_ENA_ACQ__M, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, + SCU_RAM_QAM_FSM_STATE_TGT__A, + 0x2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /* force to rate hunting */ - rc = set_qam(demod, channel, tuner_freq_offset, QAM_SET_OP_CONSTELLATION); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SCU_RAM_QAM_CTL_ENA__A, qam_ctl_ena, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } + rc = set_qam(demod, channel, tuner_freq_offset, + QAM_SET_OP_CONSTELLATION); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; } - rc = qam64auto(demod, channel, tuner_freq_offset, &lock_status); + rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, + SCU_RAM_QAM_CTL_ENA__A, + qam_ctl_ena, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = qam64auto(demod, channel, tuner_freq_offset, + &lock_status); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } channel->constellation = DRX_CONSTELLATION_AUTO; } else { - channel->constellation = DRX_CONSTELLATION_AUTO; return -EINVAL; } break; -- cgit v1.1 From 97a8918abfb5f1f9718d3bf5da38fbf803066c37 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Mon, 27 Jan 2014 02:01:40 -0300 Subject: [media] drx-j: Get rid of I2C protocol version This is not used anywere. Get rid of it. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c | 15 --------------- drivers/media/dvb-frontends/drx39xyj/drx_driver.h | 1 - drivers/media/dvb-frontends/drx39xyj/drxj.c | 15 --------------- 3 files changed, 31 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c index b78d45b..b81b4f9 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c @@ -108,23 +108,8 @@ static int drxdap_fasi_read_modify_write_reg32(struct i2c_device_addr *dev_addr, u32 datain, /* data to send */ u32 *dataout); /* data to receive back */ -/* The version structure of this protocol implementation */ -char drx_dap_fasi_module_name[] = "FASI Data Access Protocol"; -char drx_dap_fasi_version_text[] = ""; - -struct drx_version drx_dap_fasi_version = { - DRX_MODULE_DAP, /**< type identifier of the module */ - drx_dap_fasi_module_name, /**< name or description of module */ - - 0, /**< major version number */ - 0, /**< minor version number */ - 0, /**< patch version number */ - drx_dap_fasi_version_text /**< version as text string */ -}; - /* The structure containing the protocol interface */ struct drx_access_func drx_dap_fasi_funct_g = { - &drx_dap_fasi_version, drxdap_fasi_write_block, /* Supported */ drxdap_fasi_read_block, /* Supported */ drxdap_fasi_write_reg8, /* Not supported */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h index aabd5c56..f3098b6 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h @@ -1825,7 +1825,6 @@ struct drx_aud_data { * \struct struct drx_access_func * \brief Interface to an access protocol. */ struct drx_access_func { - struct drx_version *protocolVersion; drx_write_block_func_t write_block_func; drx_read_block_func_t read_block_func; drx_write_reg8func_t write_reg8func; diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index 8f2f265..1e202da 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -584,23 +584,8 @@ static int drxj_dap_write_reg32(struct i2c_device_addr *dev_addr, u32 addr, u32 data, u32 flags); -/* The version structure of this protocol implementation */ -char drx_dap_drxj_module_name[] = "DRXJ Data Access Protocol"; -char drx_dap_drxj_version_text[] = "0.0.0"; - -struct drx_version drx_dap_drxj_version = { - DRX_MODULE_DAP, /**< type identifier of the module */ - drx_dap_drxj_module_name, /**< name or description of module */ - - 0, /**< major version number */ - 0, /**< minor version number */ - 0, /**< patch version number */ - drx_dap_drxj_version_text /**< version as text string */ -}; - /* The structure containing the protocol interface */ struct drx_access_func drx_dap_drxj_funct_g = { - &drx_dap_drxj_version, drxj_dap_write_block, /* Supported */ drxj_dap_read_block, /* Supported */ drxj_dap_write_reg8, /* Not supported */ -- cgit v1.1 From 0ad0c37c7c3a4a694d52f09babb1de0dff3f6a37 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Mon, 27 Jan 2014 02:07:01 -0300 Subject: [media] drx-j: get rid of function prototypes at drx_dap_fasi.c Reorder functions and data at drx_dap_fasi.c, in order to avoid having function prototypes. This is in preparation to merge this code inside drxj, removing some duplicated bits there, and getting rid of yet another abstraction layer. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- .../media/dvb-frontends/drx39xyj/drx_dap_fasi.c | 178 +++++++-------------- 1 file changed, 59 insertions(+), 119 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c index b81b4f9..3e456ba 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c +++ b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c @@ -47,82 +47,6 @@ /*============================================================================*/ -/* Function prototypes */ -static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr, /* address of I2C device */ - u32 addr, /* address of register/memory */ - u16 datasize, /* size of data */ - u8 *data, /* data to send */ - u32 flags); /* special device flags */ - -static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr, /* address of I2C device */ - u32 addr, /* address of register/memory */ - u16 datasize, /* size of data */ - u8 *data, /* data to send */ - u32 flags); /* special device flags */ - -static int drxdap_fasi_write_reg8(struct i2c_device_addr *dev_addr, /* address of I2C device */ - u32 addr, /* address of register */ - u8 data, /* data to write */ - u32 flags); /* special device flags */ - -static int drxdap_fasi_read_reg8(struct i2c_device_addr *dev_addr, /* address of I2C device */ - u32 addr, /* address of register */ - u8 *data, /* buffer to receive data */ - u32 flags); /* special device flags */ - -static int drxdap_fasi_read_modify_write_reg8(struct i2c_device_addr *dev_addr, /* address of I2C device */ - u32 waddr, /* address of register */ - u32 raddr, /* address to read back from */ - u8 datain, /* data to send */ - u8 *dataout); /* data to receive back */ - -static int drxdap_fasi_write_reg16(struct i2c_device_addr *dev_addr, /* address of I2C device */ - u32 addr, /* address of register */ - u16 data, /* data to write */ - u32 flags); /* special device flags */ - -static int drxdap_fasi_read_reg16(struct i2c_device_addr *dev_addr, /* address of I2C device */ - u32 addr, /* address of register */ - u16 *data, /* buffer to receive data */ - u32 flags); /* special device flags */ - -static int drxdap_fasi_read_modify_write_reg16(struct i2c_device_addr *dev_addr, /* address of I2C device */ - u32 waddr, /* address of register */ - u32 raddr, /* address to read back from */ - u16 datain, /* data to send */ - u16 *dataout); /* data to receive back */ - -static int drxdap_fasi_write_reg32(struct i2c_device_addr *dev_addr, /* address of I2C device */ - u32 addr, /* address of register */ - u32 data, /* data to write */ - u32 flags); /* special device flags */ - -static int drxdap_fasi_read_reg32(struct i2c_device_addr *dev_addr, /* address of I2C device */ - u32 addr, /* address of register */ - u32 *data, /* buffer to receive data */ - u32 flags); /* special device flags */ - -static int drxdap_fasi_read_modify_write_reg32(struct i2c_device_addr *dev_addr, /* address of I2C device */ - u32 waddr, /* address of register */ - u32 raddr, /* address to read back from */ - u32 datain, /* data to send */ - u32 *dataout); /* data to receive back */ - -/* The structure containing the protocol interface */ -struct drx_access_func drx_dap_fasi_funct_g = { - drxdap_fasi_write_block, /* Supported */ - drxdap_fasi_read_block, /* Supported */ - drxdap_fasi_write_reg8, /* Not supported */ - drxdap_fasi_read_reg8, /* Not supported */ - drxdap_fasi_read_modify_write_reg8, /* Not supported */ - drxdap_fasi_write_reg16, /* Supported */ - drxdap_fasi_read_reg16, /* Supported */ - drxdap_fasi_read_modify_write_reg16, /* Supported */ - drxdap_fasi_write_reg32, /* Supported */ - drxdap_fasi_read_reg32, /* Supported */ - drxdap_fasi_read_modify_write_reg32 /* Not supported */ -}; - /*============================================================================*/ /* Functions not supported by protocol*/ @@ -346,49 +270,6 @@ static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr, return rc; } -/****************************** -* -* int drxdap_fasi_read_modify_write_reg16 ( -* struct i2c_device_addr *dev_addr, -- address of I2C device -* u32 waddr, -- address of chip register/memory -* u32 raddr, -- chip address to read back from -* u16 wdata, -- data to send -* u16 *rdata) -- data to receive back -* -* Write 16-bit data, then read back the original contents of that location. -* Requires long addressing format to be allowed. -* -* Before sending data, the data is converted to little endian. The -* data received back is converted back to the target platform's endianness. -* -* WARNING: This function is only guaranteed to work if there is one -* master on the I2C bus. -* -* Output: -* - 0 if reading was successful -* in that case: read back data is at *rdata -* - -EIO if anything went wrong -* -******************************/ - -static int drxdap_fasi_read_modify_write_reg16(struct i2c_device_addr *dev_addr, - u32 waddr, - u32 raddr, - u16 wdata, u16 *rdata) -{ - int rc = -EIO; - -#if (DRXDAPFASI_LONG_ADDR_ALLOWED == 1) - if (rdata == NULL) - return -EINVAL; - - rc = drxdap_fasi_write_reg16(dev_addr, waddr, wdata, DRXDAP_FASI_RMW); - if (rc == 0) - rc = drxdap_fasi_read_reg16(dev_addr, raddr, rdata, 0); -#endif - - return rc; -} /****************************** * @@ -628,6 +509,50 @@ static int drxdap_fasi_write_reg16(struct i2c_device_addr *dev_addr, /****************************** * +* int drxdap_fasi_read_modify_write_reg16 ( +* struct i2c_device_addr *dev_addr, -- address of I2C device +* u32 waddr, -- address of chip register/memory +* u32 raddr, -- chip address to read back from +* u16 wdata, -- data to send +* u16 *rdata) -- data to receive back +* +* Write 16-bit data, then read back the original contents of that location. +* Requires long addressing format to be allowed. +* +* Before sending data, the data is converted to little endian. The +* data received back is converted back to the target platform's endianness. +* +* WARNING: This function is only guaranteed to work if there is one +* master on the I2C bus. +* +* Output: +* - 0 if reading was successful +* in that case: read back data is at *rdata +* - -EIO if anything went wrong +* +******************************/ + +static int drxdap_fasi_read_modify_write_reg16(struct i2c_device_addr *dev_addr, + u32 waddr, + u32 raddr, + u16 wdata, u16 *rdata) +{ + int rc = -EIO; + +#if (DRXDAPFASI_LONG_ADDR_ALLOWED == 1) + if (rdata == NULL) + return -EINVAL; + + rc = drxdap_fasi_write_reg16(dev_addr, waddr, wdata, DRXDAP_FASI_RMW); + if (rc == 0) + rc = drxdap_fasi_read_reg16(dev_addr, raddr, rdata, 0); +#endif + + return rc; +} + +/****************************** +* * int drxdap_fasi_write_reg32 ( * struct i2c_device_addr *dev_addr, -- address of I2C device * u32 addr, -- address of chip register/memory @@ -656,3 +581,18 @@ static int drxdap_fasi_write_reg32(struct i2c_device_addr *dev_addr, return drxdap_fasi_write_block(dev_addr, addr, sizeof(data), buf, flags); } + +/* The structure containing the protocol interface */ +struct drx_access_func drx_dap_fasi_funct_g = { + drxdap_fasi_write_block, /* Supported */ + drxdap_fasi_read_block, /* Supported */ + drxdap_fasi_write_reg8, /* Not supported */ + drxdap_fasi_read_reg8, /* Not supported */ + drxdap_fasi_read_modify_write_reg8, /* Not supported */ + drxdap_fasi_write_reg16, /* Supported */ + drxdap_fasi_read_reg16, /* Supported */ + drxdap_fasi_read_modify_write_reg16, /* Supported */ + drxdap_fasi_write_reg32, /* Supported */ + drxdap_fasi_read_reg32, /* Supported */ + drxdap_fasi_read_modify_write_reg32 /* Not supported */ +}; -- cgit v1.1 From 73b3fc3d74de4ccba5775476d685e062b7774e64 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Mon, 27 Jan 2014 02:14:14 -0300 Subject: [media] drx-j: get rid of drx_dap_fasi.c This file contains an abstract layer for the I2C transfer functions. Get rid of it, merging it at drxj. This will allow to remove another abstraction layer there, making the code easier to read, and removing the functions that just return -EIO. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/Makefile | 2 +- .../media/dvb-frontends/drx39xyj/drx_dap_fasi.c | 598 --------------------- drivers/media/dvb-frontends/drx39xyj/drxj.c | 548 +++++++++++++++++++ 3 files changed, 549 insertions(+), 599 deletions(-) delete mode 100644 drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c diff --git a/drivers/media/dvb-frontends/drx39xyj/Makefile b/drivers/media/dvb-frontends/drx39xyj/Makefile index 7f073d4..672e077 100644 --- a/drivers/media/dvb-frontends/drx39xyj/Makefile +++ b/drivers/media/dvb-frontends/drx39xyj/Makefile @@ -1,4 +1,4 @@ -drx39xyj-objs := drx39xxj_dummy.o drxj.o drx_dap_fasi.o +drx39xyj-objs := drxj.o obj-$(CONFIG_DVB_DRX39XYJ) += drx39xyj.o diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c deleted file mode 100644 index 3e456ba..0000000 --- a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c +++ /dev/null @@ -1,598 +0,0 @@ -/* - Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - * Neither the name of Trident Microsystems nor Hauppauge Computer Works - nor the names of its contributors may be used to endorse or promote - products derived from this software without specific prior written - permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - - DESCRIPTION: - Part of DRX driver. - Data access protocol: Fast Access Sequential Interface (fasi) - Fast access, because of short addressing format (16 instead of 32 bits addr) - Sequential, because of I2C. - These functions know how the chip's memory and registers are to be accessed, - but nothing more. - - These functions should not need adapting to a new platform. -*/ - -#include "drx_dap_fasi.h" -#include "drx39xxj.h" - -#include -#include - - -/*============================================================================*/ - -/*============================================================================*/ - -/* Functions not supported by protocol*/ - -static int drxdap_fasi_write_reg8(struct i2c_device_addr *dev_addr, /* address of I2C device */ - u32 addr, /* address of register */ - u8 data, /* data to write */ - u32 flags) -{ /* special device flags */ - return -EIO; -} - -static int drxdap_fasi_read_reg8(struct i2c_device_addr *dev_addr, /* address of I2C device */ - u32 addr, /* address of register */ - u8 *data, /* buffer to receive data */ - u32 flags) -{ /* special device flags */ - return -EIO; -} - -static int drxdap_fasi_read_modify_write_reg8(struct i2c_device_addr *dev_addr, /* address of I2C device */ - u32 waddr, /* address of register */ - u32 raddr, /* address to read back from */ - u8 datain, /* data to send */ - u8 *dataout) -{ /* data to receive back */ - return -EIO; -} - -static int drxdap_fasi_read_modify_write_reg32(struct i2c_device_addr *dev_addr, /* address of I2C device */ - u32 waddr, /* address of register */ - u32 raddr, /* address to read back from */ - u32 datain, /* data to send */ - u32 *dataout) -{ /* data to receive back */ - return -EIO; -} - - -int drxbsp_i2c_write_read(struct i2c_device_addr *w_dev_addr, - u16 w_count, - u8 *wData, - struct i2c_device_addr *r_dev_addr, - u16 r_count, u8 *r_data) -{ - struct drx39xxj_state *state; - struct i2c_msg msg[2]; - unsigned int num_msgs; - - if (w_dev_addr == NULL) { - /* Read only */ - state = r_dev_addr->user_data; - msg[0].addr = r_dev_addr->i2c_addr >> 1; - msg[0].flags = I2C_M_RD; - msg[0].buf = r_data; - msg[0].len = r_count; - num_msgs = 1; - } else if (r_dev_addr == NULL) { - /* Write only */ - state = w_dev_addr->user_data; - msg[0].addr = w_dev_addr->i2c_addr >> 1; - msg[0].flags = 0; - msg[0].buf = wData; - msg[0].len = w_count; - num_msgs = 1; - } else { - /* Both write and read */ - state = w_dev_addr->user_data; - msg[0].addr = w_dev_addr->i2c_addr >> 1; - msg[0].flags = 0; - msg[0].buf = wData; - msg[0].len = w_count; - msg[1].addr = r_dev_addr->i2c_addr >> 1; - msg[1].flags = I2C_M_RD; - msg[1].buf = r_data; - msg[1].len = r_count; - num_msgs = 2; - } - - if (state->i2c == NULL) { - pr_err("i2c was zero, aborting\n"); - return 0; - } - if (i2c_transfer(state->i2c, msg, num_msgs) != num_msgs) { - pr_warn("drx3933: I2C write/read failed\n"); - return -EREMOTEIO; - } - - return 0; - -#ifdef DJH_DEBUG - struct drx39xxj_state *state = w_dev_addr->user_data; - - struct i2c_msg msg[2] = { - {.addr = w_dev_addr->i2c_addr, - .flags = 0, .buf = wData, .len = w_count}, - {.addr = r_dev_addr->i2c_addr, - .flags = I2C_M_RD, .buf = r_data, .len = r_count}, - }; - - pr_dbg("drx3933 i2c operation addr=%x i2c=%p, wc=%x rc=%x\n", - w_dev_addr->i2c_addr, state->i2c, w_count, r_count); - - if (i2c_transfer(state->i2c, msg, 2) != 2) { - pr_warn("drx3933: I2C write/read failed\n"); - return -EREMOTEIO; - } -#endif - return 0; -} - -/*============================================================================*/ - -/****************************** -* -* int drxdap_fasi_read_block ( -* struct i2c_device_addr *dev_addr, -- address of I2C device -* u32 addr, -- address of chip register/memory -* u16 datasize, -- number of bytes to read -* u8 *data, -- data to receive -* u32 flags) -- special device flags -* -* Read block data from chip address. Because the chip is word oriented, -* the number of bytes to read must be even. -* -* Make sure that the buffer to receive the data is large enough. -* -* Although this function expects an even number of bytes, it is still byte -* oriented, and the data read back is NOT translated to the endianness of -* the target platform. -* -* Output: -* - 0 if reading was successful -* in that case: data read is in *data. -* - -EIO if anything went wrong -* -******************************/ - -static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr, - u32 addr, - u16 datasize, - u8 *data, u32 flags) -{ - u8 buf[4]; - u16 bufx; - int rc; - u16 overhead_size = 0; - - /* Check parameters ******************************************************* */ - if (dev_addr == NULL) - return -EINVAL; - - overhead_size = (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1) + - (DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2); - - if ((DRXDAP_FASI_OFFSET_TOO_LARGE(addr)) || - ((!(DRXDAPFASI_LONG_ADDR_ALLOWED)) && - DRXDAP_FASI_LONG_FORMAT(addr)) || - (overhead_size > (DRXDAP_MAX_WCHUNKSIZE)) || - ((datasize != 0) && (data == NULL)) || ((datasize & 1) == 1)) { - return -EINVAL; - } - - /* ReadModifyWrite & mode flag bits are not allowed */ - flags &= (~DRXDAP_FASI_RMW & ~DRXDAP_FASI_MODEFLAGS); -#if DRXDAP_SINGLE_MASTER - flags |= DRXDAP_FASI_SINGLE_MASTER; -#endif - - /* Read block from I2C **************************************************** */ - do { - u16 todo = (datasize < DRXDAP_MAX_RCHUNKSIZE ? - datasize : DRXDAP_MAX_RCHUNKSIZE); - - bufx = 0; - - addr &= ~DRXDAP_FASI_FLAGS; - addr |= flags; - -#if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1)) - /* short format address preferred but long format otherwise */ - if (DRXDAP_FASI_LONG_FORMAT(addr)) { -#endif -#if (DRXDAPFASI_LONG_ADDR_ALLOWED == 1) - buf[bufx++] = (u8) (((addr << 1) & 0xFF) | 0x01); - buf[bufx++] = (u8) ((addr >> 16) & 0xFF); - buf[bufx++] = (u8) ((addr >> 24) & 0xFF); - buf[bufx++] = (u8) ((addr >> 7) & 0xFF); -#endif -#if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1)) - } else { -#endif -#if (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1) - buf[bufx++] = (u8) ((addr << 1) & 0xFF); - buf[bufx++] = - (u8) (((addr >> 16) & 0x0F) | - ((addr >> 18) & 0xF0)); -#endif -#if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1)) - } -#endif - -#if DRXDAP_SINGLE_MASTER - /* - * In single master mode, split the read and write actions. - * No special action is needed for write chunks here. - */ - rc = drxbsp_i2c_write_read(dev_addr, bufx, buf, 0, 0, 0); - if (rc == 0) - rc = drxbsp_i2c_write_read(0, 0, 0, dev_addr, todo, data); -#else - /* In multi master mode, do everything in one RW action */ - rc = drxbsp_i2c_write_read(dev_addr, bufx, buf, dev_addr, todo, - data); -#endif - data += todo; - addr += (todo >> 1); - datasize -= todo; - } while (datasize && rc == 0); - - return rc; -} - - -/****************************** -* -* int drxdap_fasi_read_reg16 ( -* struct i2c_device_addr *dev_addr, -- address of I2C device -* u32 addr, -- address of chip register/memory -* u16 *data, -- data to receive -* u32 flags) -- special device flags -* -* Read one 16-bit register or memory location. The data received back is -* converted back to the target platform's endianness. -* -* Output: -* - 0 if reading was successful -* in that case: read data is at *data -* - -EIO if anything went wrong -* -******************************/ - -static int drxdap_fasi_read_reg16(struct i2c_device_addr *dev_addr, - u32 addr, - u16 *data, u32 flags) -{ - u8 buf[sizeof(*data)]; - int rc; - - if (!data) - return -EINVAL; - - rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags); - *data = buf[0] + (((u16) buf[1]) << 8); - return rc; -} - -/****************************** -* -* int drxdap_fasi_read_reg32 ( -* struct i2c_device_addr *dev_addr, -- address of I2C device -* u32 addr, -- address of chip register/memory -* u32 *data, -- data to receive -* u32 flags) -- special device flags -* -* Read one 32-bit register or memory location. The data received back is -* converted back to the target platform's endianness. -* -* Output: -* - 0 if reading was successful -* in that case: read data is at *data -* - -EIO if anything went wrong -* -******************************/ - -static int drxdap_fasi_read_reg32(struct i2c_device_addr *dev_addr, - u32 addr, - u32 *data, u32 flags) -{ - u8 buf[sizeof(*data)]; - int rc; - - if (!data) - return -EINVAL; - - rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags); - *data = (((u32) buf[0]) << 0) + - (((u32) buf[1]) << 8) + - (((u32) buf[2]) << 16) + (((u32) buf[3]) << 24); - return rc; -} - -/****************************** -* -* int drxdap_fasi_write_block ( -* struct i2c_device_addr *dev_addr, -- address of I2C device -* u32 addr, -- address of chip register/memory -* u16 datasize, -- number of bytes to read -* u8 *data, -- data to receive -* u32 flags) -- special device flags -* -* Write block data to chip address. Because the chip is word oriented, -* the number of bytes to write must be even. -* -* Although this function expects an even number of bytes, it is still byte -* oriented, and the data being written is NOT translated from the endianness of -* the target platform. -* -* Output: -* - 0 if writing was successful -* - -EIO if anything went wrong -* -******************************/ - -static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr, - u32 addr, - u16 datasize, - u8 *data, u32 flags) -{ - u8 buf[DRXDAP_MAX_WCHUNKSIZE]; - int st = -EIO; - int first_err = 0; - u16 overhead_size = 0; - u16 block_size = 0; - - /* Check parameters ******************************************************* */ - if (dev_addr == NULL) - return -EINVAL; - - overhead_size = (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1) + - (DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2); - - if ((DRXDAP_FASI_OFFSET_TOO_LARGE(addr)) || - ((!(DRXDAPFASI_LONG_ADDR_ALLOWED)) && - DRXDAP_FASI_LONG_FORMAT(addr)) || - (overhead_size > (DRXDAP_MAX_WCHUNKSIZE)) || - ((datasize != 0) && (data == NULL)) || ((datasize & 1) == 1)) - return -EINVAL; - - flags &= DRXDAP_FASI_FLAGS; - flags &= ~DRXDAP_FASI_MODEFLAGS; -#if DRXDAP_SINGLE_MASTER - flags |= DRXDAP_FASI_SINGLE_MASTER; -#endif - - /* Write block to I2C ***************************************************** */ - block_size = ((DRXDAP_MAX_WCHUNKSIZE) - overhead_size) & ~1; - do { - u16 todo = 0; - u16 bufx = 0; - - /* Buffer device address */ - addr &= ~DRXDAP_FASI_FLAGS; - addr |= flags; -#if (((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1)) - /* short format address preferred but long format otherwise */ - if (DRXDAP_FASI_LONG_FORMAT(addr)) { -#endif -#if ((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) - buf[bufx++] = (u8) (((addr << 1) & 0xFF) | 0x01); - buf[bufx++] = (u8) ((addr >> 16) & 0xFF); - buf[bufx++] = (u8) ((addr >> 24) & 0xFF); - buf[bufx++] = (u8) ((addr >> 7) & 0xFF); -#endif -#if (((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1)) - } else { -#endif -#if ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1) - buf[bufx++] = (u8) ((addr << 1) & 0xFF); - buf[bufx++] = - (u8) (((addr >> 16) & 0x0F) | - ((addr >> 18) & 0xF0)); -#endif -#if (((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1)) - } -#endif - - /* - In single master mode block_size can be 0. In such a case this I2C - sequense will be visible: (1) write address {i2c addr, - 4 bytes chip address} (2) write data {i2c addr, 4 bytes data } - (3) write address (4) write data etc... - Addres must be rewriten because HI is reset after data transport and - expects an address. - */ - todo = (block_size < datasize ? block_size : datasize); - if (todo == 0) { - u16 overhead_size_i2c_addr = 0; - u16 data_block_size = 0; - - overhead_size_i2c_addr = - (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1); - data_block_size = - (DRXDAP_MAX_WCHUNKSIZE - overhead_size_i2c_addr) & ~1; - - /* write device address */ - st = drxbsp_i2c_write_read(dev_addr, - (u16) (bufx), - buf, - (struct i2c_device_addr *)(NULL), - 0, (u8 *)(NULL)); - - if ((st != 0) && (first_err == 0)) { - /* at the end, return the first error encountered */ - first_err = st; - } - bufx = 0; - todo = - (data_block_size < - datasize ? data_block_size : datasize); - } - memcpy(&buf[bufx], data, todo); - /* write (address if can do and) data */ - st = drxbsp_i2c_write_read(dev_addr, - (u16) (bufx + todo), - buf, - (struct i2c_device_addr *)(NULL), - 0, (u8 *)(NULL)); - - if ((st != 0) && (first_err == 0)) { - /* at the end, return the first error encountered */ - first_err = st; - } - datasize -= todo; - data += todo; - addr += (todo >> 1); - } while (datasize); - - return first_err; -} - -/****************************** -* -* int drxdap_fasi_write_reg16 ( -* struct i2c_device_addr *dev_addr, -- address of I2C device -* u32 addr, -- address of chip register/memory -* u16 data, -- data to send -* u32 flags) -- special device flags -* -* Write one 16-bit register or memory location. The data being written is -* converted from the target platform's endianness to little endian. -* -* Output: -* - 0 if writing was successful -* - -EIO if anything went wrong -* -******************************/ - -static int drxdap_fasi_write_reg16(struct i2c_device_addr *dev_addr, - u32 addr, - u16 data, u32 flags) -{ - u8 buf[sizeof(data)]; - - buf[0] = (u8) ((data >> 0) & 0xFF); - buf[1] = (u8) ((data >> 8) & 0xFF); - - return drxdap_fasi_write_block(dev_addr, addr, sizeof(data), buf, flags); -} - -/****************************** -* -* int drxdap_fasi_read_modify_write_reg16 ( -* struct i2c_device_addr *dev_addr, -- address of I2C device -* u32 waddr, -- address of chip register/memory -* u32 raddr, -- chip address to read back from -* u16 wdata, -- data to send -* u16 *rdata) -- data to receive back -* -* Write 16-bit data, then read back the original contents of that location. -* Requires long addressing format to be allowed. -* -* Before sending data, the data is converted to little endian. The -* data received back is converted back to the target platform's endianness. -* -* WARNING: This function is only guaranteed to work if there is one -* master on the I2C bus. -* -* Output: -* - 0 if reading was successful -* in that case: read back data is at *rdata -* - -EIO if anything went wrong -* -******************************/ - -static int drxdap_fasi_read_modify_write_reg16(struct i2c_device_addr *dev_addr, - u32 waddr, - u32 raddr, - u16 wdata, u16 *rdata) -{ - int rc = -EIO; - -#if (DRXDAPFASI_LONG_ADDR_ALLOWED == 1) - if (rdata == NULL) - return -EINVAL; - - rc = drxdap_fasi_write_reg16(dev_addr, waddr, wdata, DRXDAP_FASI_RMW); - if (rc == 0) - rc = drxdap_fasi_read_reg16(dev_addr, raddr, rdata, 0); -#endif - - return rc; -} - -/****************************** -* -* int drxdap_fasi_write_reg32 ( -* struct i2c_device_addr *dev_addr, -- address of I2C device -* u32 addr, -- address of chip register/memory -* u32 data, -- data to send -* u32 flags) -- special device flags -* -* Write one 32-bit register or memory location. The data being written is -* converted from the target platform's endianness to little endian. -* -* Output: -* - 0 if writing was successful -* - -EIO if anything went wrong -* -******************************/ - -static int drxdap_fasi_write_reg32(struct i2c_device_addr *dev_addr, - u32 addr, - u32 data, u32 flags) -{ - u8 buf[sizeof(data)]; - - buf[0] = (u8) ((data >> 0) & 0xFF); - buf[1] = (u8) ((data >> 8) & 0xFF); - buf[2] = (u8) ((data >> 16) & 0xFF); - buf[3] = (u8) ((data >> 24) & 0xFF); - - return drxdap_fasi_write_block(dev_addr, addr, sizeof(data), buf, flags); -} - -/* The structure containing the protocol interface */ -struct drx_access_func drx_dap_fasi_funct_g = { - drxdap_fasi_write_block, /* Supported */ - drxdap_fasi_read_block, /* Supported */ - drxdap_fasi_write_reg8, /* Not supported */ - drxdap_fasi_read_reg8, /* Not supported */ - drxdap_fasi_read_modify_write_reg8, /* Not supported */ - drxdap_fasi_write_reg16, /* Supported */ - drxdap_fasi_read_reg16, /* Supported */ - drxdap_fasi_read_modify_write_reg16, /* Supported */ - drxdap_fasi_write_reg32, /* Supported */ - drxdap_fasi_read_reg32, /* Supported */ - drxdap_fasi_read_modify_write_reg32 /* Not supported */ -}; diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index 1e202da..94c3d6f 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -1540,6 +1540,554 @@ bool is_handled_by_aud_tr_if(u32 addr) /*============================================================================*/ +/* Functions not supported by protocol*/ + +static int drxdap_fasi_write_reg8(struct i2c_device_addr *dev_addr, /* address of I2C device */ + u32 addr, /* address of register */ + u8 data, /* data to write */ + u32 flags) +{ /* special device flags */ + return -EIO; +} + +static int drxdap_fasi_read_reg8(struct i2c_device_addr *dev_addr, /* address of I2C device */ + u32 addr, /* address of register */ + u8 *data, /* buffer to receive data */ + u32 flags) +{ /* special device flags */ + return -EIO; +} + +static int drxdap_fasi_read_modify_write_reg8(struct i2c_device_addr *dev_addr, /* address of I2C device */ + u32 waddr, /* address of register */ + u32 raddr, /* address to read back from */ + u8 datain, /* data to send */ + u8 *dataout) +{ /* data to receive back */ + return -EIO; +} + +static int drxdap_fasi_read_modify_write_reg32(struct i2c_device_addr *dev_addr, /* address of I2C device */ + u32 waddr, /* address of register */ + u32 raddr, /* address to read back from */ + u32 datain, /* data to send */ + u32 *dataout) +{ /* data to receive back */ + return -EIO; +} + + +int drxbsp_i2c_write_read(struct i2c_device_addr *w_dev_addr, + u16 w_count, + u8 *wData, + struct i2c_device_addr *r_dev_addr, + u16 r_count, u8 *r_data) +{ + struct drx39xxj_state *state; + struct i2c_msg msg[2]; + unsigned int num_msgs; + + if (w_dev_addr == NULL) { + /* Read only */ + state = r_dev_addr->user_data; + msg[0].addr = r_dev_addr->i2c_addr >> 1; + msg[0].flags = I2C_M_RD; + msg[0].buf = r_data; + msg[0].len = r_count; + num_msgs = 1; + } else if (r_dev_addr == NULL) { + /* Write only */ + state = w_dev_addr->user_data; + msg[0].addr = w_dev_addr->i2c_addr >> 1; + msg[0].flags = 0; + msg[0].buf = wData; + msg[0].len = w_count; + num_msgs = 1; + } else { + /* Both write and read */ + state = w_dev_addr->user_data; + msg[0].addr = w_dev_addr->i2c_addr >> 1; + msg[0].flags = 0; + msg[0].buf = wData; + msg[0].len = w_count; + msg[1].addr = r_dev_addr->i2c_addr >> 1; + msg[1].flags = I2C_M_RD; + msg[1].buf = r_data; + msg[1].len = r_count; + num_msgs = 2; + } + + if (state->i2c == NULL) { + pr_err("i2c was zero, aborting\n"); + return 0; + } + if (i2c_transfer(state->i2c, msg, num_msgs) != num_msgs) { + pr_warn("drx3933: I2C write/read failed\n"); + return -EREMOTEIO; + } + + return 0; + +#ifdef DJH_DEBUG + struct drx39xxj_state *state = w_dev_addr->user_data; + + struct i2c_msg msg[2] = { + {.addr = w_dev_addr->i2c_addr, + .flags = 0, .buf = wData, .len = w_count}, + {.addr = r_dev_addr->i2c_addr, + .flags = I2C_M_RD, .buf = r_data, .len = r_count}, + }; + + pr_dbg("drx3933 i2c operation addr=%x i2c=%p, wc=%x rc=%x\n", + w_dev_addr->i2c_addr, state->i2c, w_count, r_count); + + if (i2c_transfer(state->i2c, msg, 2) != 2) { + pr_warn("drx3933: I2C write/read failed\n"); + return -EREMOTEIO; + } +#endif + return 0; +} + +/*============================================================================*/ + +/****************************** +* +* int drxdap_fasi_read_block ( +* struct i2c_device_addr *dev_addr, -- address of I2C device +* u32 addr, -- address of chip register/memory +* u16 datasize, -- number of bytes to read +* u8 *data, -- data to receive +* u32 flags) -- special device flags +* +* Read block data from chip address. Because the chip is word oriented, +* the number of bytes to read must be even. +* +* Make sure that the buffer to receive the data is large enough. +* +* Although this function expects an even number of bytes, it is still byte +* oriented, and the data read back is NOT translated to the endianness of +* the target platform. +* +* Output: +* - 0 if reading was successful +* in that case: data read is in *data. +* - -EIO if anything went wrong +* +******************************/ + +static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr, + u32 addr, + u16 datasize, + u8 *data, u32 flags) +{ + u8 buf[4]; + u16 bufx; + int rc; + u16 overhead_size = 0; + + /* Check parameters ******************************************************* */ + if (dev_addr == NULL) + return -EINVAL; + + overhead_size = (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1) + + (DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2); + + if ((DRXDAP_FASI_OFFSET_TOO_LARGE(addr)) || + ((!(DRXDAPFASI_LONG_ADDR_ALLOWED)) && + DRXDAP_FASI_LONG_FORMAT(addr)) || + (overhead_size > (DRXDAP_MAX_WCHUNKSIZE)) || + ((datasize != 0) && (data == NULL)) || ((datasize & 1) == 1)) { + return -EINVAL; + } + + /* ReadModifyWrite & mode flag bits are not allowed */ + flags &= (~DRXDAP_FASI_RMW & ~DRXDAP_FASI_MODEFLAGS); +#if DRXDAP_SINGLE_MASTER + flags |= DRXDAP_FASI_SINGLE_MASTER; +#endif + + /* Read block from I2C **************************************************** */ + do { + u16 todo = (datasize < DRXDAP_MAX_RCHUNKSIZE ? + datasize : DRXDAP_MAX_RCHUNKSIZE); + + bufx = 0; + + addr &= ~DRXDAP_FASI_FLAGS; + addr |= flags; + +#if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1)) + /* short format address preferred but long format otherwise */ + if (DRXDAP_FASI_LONG_FORMAT(addr)) { +#endif +#if (DRXDAPFASI_LONG_ADDR_ALLOWED == 1) + buf[bufx++] = (u8) (((addr << 1) & 0xFF) | 0x01); + buf[bufx++] = (u8) ((addr >> 16) & 0xFF); + buf[bufx++] = (u8) ((addr >> 24) & 0xFF); + buf[bufx++] = (u8) ((addr >> 7) & 0xFF); +#endif +#if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1)) + } else { +#endif +#if (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1) + buf[bufx++] = (u8) ((addr << 1) & 0xFF); + buf[bufx++] = + (u8) (((addr >> 16) & 0x0F) | + ((addr >> 18) & 0xF0)); +#endif +#if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1)) + } +#endif + +#if DRXDAP_SINGLE_MASTER + /* + * In single master mode, split the read and write actions. + * No special action is needed for write chunks here. + */ + rc = drxbsp_i2c_write_read(dev_addr, bufx, buf, 0, 0, 0); + if (rc == 0) + rc = drxbsp_i2c_write_read(0, 0, 0, dev_addr, todo, data); +#else + /* In multi master mode, do everything in one RW action */ + rc = drxbsp_i2c_write_read(dev_addr, bufx, buf, dev_addr, todo, + data); +#endif + data += todo; + addr += (todo >> 1); + datasize -= todo; + } while (datasize && rc == 0); + + return rc; +} + + +/****************************** +* +* int drxdap_fasi_read_reg16 ( +* struct i2c_device_addr *dev_addr, -- address of I2C device +* u32 addr, -- address of chip register/memory +* u16 *data, -- data to receive +* u32 flags) -- special device flags +* +* Read one 16-bit register or memory location. The data received back is +* converted back to the target platform's endianness. +* +* Output: +* - 0 if reading was successful +* in that case: read data is at *data +* - -EIO if anything went wrong +* +******************************/ + +static int drxdap_fasi_read_reg16(struct i2c_device_addr *dev_addr, + u32 addr, + u16 *data, u32 flags) +{ + u8 buf[sizeof(*data)]; + int rc; + + if (!data) + return -EINVAL; + + rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags); + *data = buf[0] + (((u16) buf[1]) << 8); + return rc; +} + +/****************************** +* +* int drxdap_fasi_read_reg32 ( +* struct i2c_device_addr *dev_addr, -- address of I2C device +* u32 addr, -- address of chip register/memory +* u32 *data, -- data to receive +* u32 flags) -- special device flags +* +* Read one 32-bit register or memory location. The data received back is +* converted back to the target platform's endianness. +* +* Output: +* - 0 if reading was successful +* in that case: read data is at *data +* - -EIO if anything went wrong +* +******************************/ + +static int drxdap_fasi_read_reg32(struct i2c_device_addr *dev_addr, + u32 addr, + u32 *data, u32 flags) +{ + u8 buf[sizeof(*data)]; + int rc; + + if (!data) + return -EINVAL; + + rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags); + *data = (((u32) buf[0]) << 0) + + (((u32) buf[1]) << 8) + + (((u32) buf[2]) << 16) + (((u32) buf[3]) << 24); + return rc; +} + +/****************************** +* +* int drxdap_fasi_write_block ( +* struct i2c_device_addr *dev_addr, -- address of I2C device +* u32 addr, -- address of chip register/memory +* u16 datasize, -- number of bytes to read +* u8 *data, -- data to receive +* u32 flags) -- special device flags +* +* Write block data to chip address. Because the chip is word oriented, +* the number of bytes to write must be even. +* +* Although this function expects an even number of bytes, it is still byte +* oriented, and the data being written is NOT translated from the endianness of +* the target platform. +* +* Output: +* - 0 if writing was successful +* - -EIO if anything went wrong +* +******************************/ + +static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr, + u32 addr, + u16 datasize, + u8 *data, u32 flags) +{ + u8 buf[DRXDAP_MAX_WCHUNKSIZE]; + int st = -EIO; + int first_err = 0; + u16 overhead_size = 0; + u16 block_size = 0; + + /* Check parameters ******************************************************* */ + if (dev_addr == NULL) + return -EINVAL; + + overhead_size = (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1) + + (DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2); + + if ((DRXDAP_FASI_OFFSET_TOO_LARGE(addr)) || + ((!(DRXDAPFASI_LONG_ADDR_ALLOWED)) && + DRXDAP_FASI_LONG_FORMAT(addr)) || + (overhead_size > (DRXDAP_MAX_WCHUNKSIZE)) || + ((datasize != 0) && (data == NULL)) || ((datasize & 1) == 1)) + return -EINVAL; + + flags &= DRXDAP_FASI_FLAGS; + flags &= ~DRXDAP_FASI_MODEFLAGS; +#if DRXDAP_SINGLE_MASTER + flags |= DRXDAP_FASI_SINGLE_MASTER; +#endif + + /* Write block to I2C ***************************************************** */ + block_size = ((DRXDAP_MAX_WCHUNKSIZE) - overhead_size) & ~1; + do { + u16 todo = 0; + u16 bufx = 0; + + /* Buffer device address */ + addr &= ~DRXDAP_FASI_FLAGS; + addr |= flags; +#if (((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1)) + /* short format address preferred but long format otherwise */ + if (DRXDAP_FASI_LONG_FORMAT(addr)) { +#endif +#if ((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) + buf[bufx++] = (u8) (((addr << 1) & 0xFF) | 0x01); + buf[bufx++] = (u8) ((addr >> 16) & 0xFF); + buf[bufx++] = (u8) ((addr >> 24) & 0xFF); + buf[bufx++] = (u8) ((addr >> 7) & 0xFF); +#endif +#if (((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1)) + } else { +#endif +#if ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1) + buf[bufx++] = (u8) ((addr << 1) & 0xFF); + buf[bufx++] = + (u8) (((addr >> 16) & 0x0F) | + ((addr >> 18) & 0xF0)); +#endif +#if (((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1)) + } +#endif + + /* + In single master mode block_size can be 0. In such a case this I2C + sequense will be visible: (1) write address {i2c addr, + 4 bytes chip address} (2) write data {i2c addr, 4 bytes data } + (3) write address (4) write data etc... + Addres must be rewriten because HI is reset after data transport and + expects an address. + */ + todo = (block_size < datasize ? block_size : datasize); + if (todo == 0) { + u16 overhead_size_i2c_addr = 0; + u16 data_block_size = 0; + + overhead_size_i2c_addr = + (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1); + data_block_size = + (DRXDAP_MAX_WCHUNKSIZE - overhead_size_i2c_addr) & ~1; + + /* write device address */ + st = drxbsp_i2c_write_read(dev_addr, + (u16) (bufx), + buf, + (struct i2c_device_addr *)(NULL), + 0, (u8 *)(NULL)); + + if ((st != 0) && (first_err == 0)) { + /* at the end, return the first error encountered */ + first_err = st; + } + bufx = 0; + todo = + (data_block_size < + datasize ? data_block_size : datasize); + } + memcpy(&buf[bufx], data, todo); + /* write (address if can do and) data */ + st = drxbsp_i2c_write_read(dev_addr, + (u16) (bufx + todo), + buf, + (struct i2c_device_addr *)(NULL), + 0, (u8 *)(NULL)); + + if ((st != 0) && (first_err == 0)) { + /* at the end, return the first error encountered */ + first_err = st; + } + datasize -= todo; + data += todo; + addr += (todo >> 1); + } while (datasize); + + return first_err; +} + +/****************************** +* +* int drxdap_fasi_write_reg16 ( +* struct i2c_device_addr *dev_addr, -- address of I2C device +* u32 addr, -- address of chip register/memory +* u16 data, -- data to send +* u32 flags) -- special device flags +* +* Write one 16-bit register or memory location. The data being written is +* converted from the target platform's endianness to little endian. +* +* Output: +* - 0 if writing was successful +* - -EIO if anything went wrong +* +******************************/ + +static int drxdap_fasi_write_reg16(struct i2c_device_addr *dev_addr, + u32 addr, + u16 data, u32 flags) +{ + u8 buf[sizeof(data)]; + + buf[0] = (u8) ((data >> 0) & 0xFF); + buf[1] = (u8) ((data >> 8) & 0xFF); + + return drxdap_fasi_write_block(dev_addr, addr, sizeof(data), buf, flags); +} + +/****************************** +* +* int drxdap_fasi_read_modify_write_reg16 ( +* struct i2c_device_addr *dev_addr, -- address of I2C device +* u32 waddr, -- address of chip register/memory +* u32 raddr, -- chip address to read back from +* u16 wdata, -- data to send +* u16 *rdata) -- data to receive back +* +* Write 16-bit data, then read back the original contents of that location. +* Requires long addressing format to be allowed. +* +* Before sending data, the data is converted to little endian. The +* data received back is converted back to the target platform's endianness. +* +* WARNING: This function is only guaranteed to work if there is one +* master on the I2C bus. +* +* Output: +* - 0 if reading was successful +* in that case: read back data is at *rdata +* - -EIO if anything went wrong +* +******************************/ + +static int drxdap_fasi_read_modify_write_reg16(struct i2c_device_addr *dev_addr, + u32 waddr, + u32 raddr, + u16 wdata, u16 *rdata) +{ + int rc = -EIO; + +#if (DRXDAPFASI_LONG_ADDR_ALLOWED == 1) + if (rdata == NULL) + return -EINVAL; + + rc = drxdap_fasi_write_reg16(dev_addr, waddr, wdata, DRXDAP_FASI_RMW); + if (rc == 0) + rc = drxdap_fasi_read_reg16(dev_addr, raddr, rdata, 0); +#endif + + return rc; +} + +/****************************** +* +* int drxdap_fasi_write_reg32 ( +* struct i2c_device_addr *dev_addr, -- address of I2C device +* u32 addr, -- address of chip register/memory +* u32 data, -- data to send +* u32 flags) -- special device flags +* +* Write one 32-bit register or memory location. The data being written is +* converted from the target platform's endianness to little endian. +* +* Output: +* - 0 if writing was successful +* - -EIO if anything went wrong +* +******************************/ + +static int drxdap_fasi_write_reg32(struct i2c_device_addr *dev_addr, + u32 addr, + u32 data, u32 flags) +{ + u8 buf[sizeof(data)]; + + buf[0] = (u8) ((data >> 0) & 0xFF); + buf[1] = (u8) ((data >> 8) & 0xFF); + buf[2] = (u8) ((data >> 16) & 0xFF); + buf[3] = (u8) ((data >> 24) & 0xFF); + + return drxdap_fasi_write_block(dev_addr, addr, sizeof(data), buf, flags); +} + +/* The structure containing the protocol interface */ +struct drx_access_func drx_dap_fasi_funct_g = { + drxdap_fasi_write_block, /* Supported */ + drxdap_fasi_read_block, /* Supported */ + drxdap_fasi_write_reg8, /* Not supported */ + drxdap_fasi_read_reg8, /* Not supported */ + drxdap_fasi_read_modify_write_reg8, /* Not supported */ + drxdap_fasi_write_reg16, /* Supported */ + drxdap_fasi_read_reg16, /* Supported */ + drxdap_fasi_read_modify_write_reg16, /* Supported */ + drxdap_fasi_write_reg32, /* Supported */ + drxdap_fasi_read_reg32, /* Supported */ + drxdap_fasi_read_modify_write_reg32 /* Not supported */ +}; + static int drxj_dap_read_block(struct i2c_device_addr *dev_addr, u32 addr, u16 datasize, -- cgit v1.1 From 80bff4b07595cf086e5d1cda4fd6e740affff5c5 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Mon, 27 Jan 2014 02:24:25 -0300 Subject: [media] drx-j: get rid of struct drx_dap_fasi_funct_g This struct contains the first abstraction layer for the I2C access routines. Get rid of it. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drxj.c | 45 ++++++++++------------------- 1 file changed, 15 insertions(+), 30 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index 94c3d6f..8dc53345 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -2073,27 +2073,12 @@ static int drxdap_fasi_write_reg32(struct i2c_device_addr *dev_addr, return drxdap_fasi_write_block(dev_addr, addr, sizeof(data), buf, flags); } -/* The structure containing the protocol interface */ -struct drx_access_func drx_dap_fasi_funct_g = { - drxdap_fasi_write_block, /* Supported */ - drxdap_fasi_read_block, /* Supported */ - drxdap_fasi_write_reg8, /* Not supported */ - drxdap_fasi_read_reg8, /* Not supported */ - drxdap_fasi_read_modify_write_reg8, /* Not supported */ - drxdap_fasi_write_reg16, /* Supported */ - drxdap_fasi_read_reg16, /* Supported */ - drxdap_fasi_read_modify_write_reg16, /* Supported */ - drxdap_fasi_write_reg32, /* Supported */ - drxdap_fasi_read_reg32, /* Supported */ - drxdap_fasi_read_modify_write_reg32 /* Not supported */ -}; - static int drxj_dap_read_block(struct i2c_device_addr *dev_addr, u32 addr, u16 datasize, u8 *data, u32 flags) { - return drx_dap_fasi_funct_g.read_block_func(dev_addr, + return drxdap_fasi_read_block(dev_addr, addr, datasize, data, flags); } @@ -2104,7 +2089,7 @@ static int drxj_dap_read_modify_write_reg8(struct i2c_device_addr *dev_addr, u32 raddr, u8 wdata, u8 *rdata) { - return drx_dap_fasi_funct_g.read_modify_write_reg8func(dev_addr, + return drxdap_fasi_read_modify_write_reg8(dev_addr, waddr, raddr, wdata, rdata); } @@ -2143,23 +2128,23 @@ static int drxj_dap_rm_write_reg16short(struct i2c_device_addr *dev_addr, return -EINVAL; /* Set RMW flag */ - rc = drx_dap_fasi_funct_g.write_reg16func(dev_addr, + rc = drxdap_fasi_write_reg16(dev_addr, SIO_HI_RA_RAM_S0_FLG_ACC__A, SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__M, 0x0000); if (rc == 0) { /* Write new data: triggers RMW */ - rc = drx_dap_fasi_funct_g.write_reg16func(dev_addr, waddr, wdata, + rc = drxdap_fasi_write_reg16(dev_addr, waddr, wdata, 0x0000); } if (rc == 0) { /* Read old data */ - rc = drx_dap_fasi_funct_g.read_reg16func(dev_addr, raddr, rdata, + rc = drxdap_fasi_read_reg16(dev_addr, raddr, rdata, 0x0000); } if (rc == 0) { /* Reset RMW flag */ - rc = drx_dap_fasi_funct_g.write_reg16func(dev_addr, + rc = drxdap_fasi_write_reg16(dev_addr, SIO_HI_RA_RAM_S0_FLG_ACC__A, 0, 0x0000); } @@ -2179,7 +2164,7 @@ static int drxj_dap_read_modify_write_reg16(struct i2c_device_addr *dev_addr, now long format has higher prio then short because short also needs virt bnks (not impl yet) for certain audio registers */ #if (DRXDAPFASI_LONG_ADDR_ALLOWED == 1) - return drx_dap_fasi_funct_g.read_modify_write_reg16func(dev_addr, + return drxdap_fasi_read_modify_write_reg16(dev_addr, waddr, raddr, wdata, rdata); #else @@ -2194,7 +2179,7 @@ static int drxj_dap_read_modify_write_reg32(struct i2c_device_addr *dev_addr, u32 raddr, u32 wdata, u32 *rdata) { - return drx_dap_fasi_funct_g.read_modify_write_reg32func(dev_addr, + return drxdap_fasi_read_modify_write_reg32(dev_addr, waddr, raddr, wdata, rdata); } @@ -2205,7 +2190,7 @@ static int drxj_dap_read_reg8(struct i2c_device_addr *dev_addr, u32 addr, u8 *data, u32 flags) { - return drx_dap_fasi_funct_g.read_reg8func(dev_addr, addr, data, flags); + return drxdap_fasi_read_reg8(dev_addr, addr, data, flags); } /*============================================================================*/ @@ -2311,7 +2296,7 @@ static int drxj_dap_read_reg16(struct i2c_device_addr *dev_addr, if (is_handled_by_aud_tr_if(addr)) stat = drxj_dap_read_aud_reg16(dev_addr, addr, data); else - stat = drx_dap_fasi_funct_g.read_reg16func(dev_addr, + stat = drxdap_fasi_read_reg16(dev_addr, addr, data, flags); return stat; @@ -2323,7 +2308,7 @@ static int drxj_dap_read_reg32(struct i2c_device_addr *dev_addr, u32 addr, u32 *data, u32 flags) { - return drx_dap_fasi_funct_g.read_reg32func(dev_addr, addr, data, flags); + return drxdap_fasi_read_reg32(dev_addr, addr, data, flags); } /*============================================================================*/ @@ -2333,7 +2318,7 @@ static int drxj_dap_write_block(struct i2c_device_addr *dev_addr, u16 datasize, u8 *data, u32 flags) { - return drx_dap_fasi_funct_g.write_block_func(dev_addr, + return drxdap_fasi_write_block(dev_addr, addr, datasize, data, flags); } @@ -2343,7 +2328,7 @@ static int drxj_dap_write_reg8(struct i2c_device_addr *dev_addr, u32 addr, u8 data, u32 flags) { - return drx_dap_fasi_funct_g.write_reg8func(dev_addr, addr, data, flags); + return drxdap_fasi_write_reg8(dev_addr, addr, data, flags); } /*============================================================================*/ @@ -2420,7 +2405,7 @@ static int drxj_dap_write_reg16(struct i2c_device_addr *dev_addr, if (is_handled_by_aud_tr_if(addr)) stat = drxj_dap_write_aud_reg16(dev_addr, addr, data); else - stat = drx_dap_fasi_funct_g.write_reg16func(dev_addr, + stat = drxdap_fasi_write_reg16(dev_addr, addr, data, flags); return stat; @@ -2432,7 +2417,7 @@ static int drxj_dap_write_reg32(struct i2c_device_addr *dev_addr, u32 addr, u32 data, u32 flags) { - return drx_dap_fasi_funct_g.write_reg32func(dev_addr, addr, data, flags); + return drxdap_fasi_write_reg32(dev_addr, addr, data, flags); } /*============================================================================*/ -- cgit v1.1 From 244c0e06bfd4e5bce46914bb11b0aac7de73831e Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Mon, 27 Jan 2014 02:33:18 -0300 Subject: [media] drx-j: get rid of function wrappers On several places, the I2C functions are just wrappers to others. Get rid of it. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drx_driver.h | 2 - drivers/media/dvb-frontends/drx39xyj/drxj.c | 2210 ++++++++++----------- 2 files changed, 1026 insertions(+), 1186 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h index f3098b6..8419989 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h @@ -1940,8 +1940,6 @@ struct drx_demod_instance; * \struct struct drx_demod_instance * \brief Top structure of demodulator instance. */ struct drx_demod_instance { - /* type specific demodulator data */ - struct drx_access_func *my_access_funct; /**< data access protocol functions */ struct i2c_device_addr *my_i2c_dev_addr; /**< i2c address and device identifier */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index 8dc53345..7a28c20 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -226,12 +226,6 @@ DEFINES #define DRXJ_SCAN_TIMEOUT 1000 /** -* \def DRXJ_DAP -* \brief Name of structure containing all data access protocol functions. -*/ -#define DRXJ_DAP drx_dap_drxj_funct_g - -/** * \def HI_I2C_DELAY * \brief HI timing delay for I2C timing (in nano seconds) * @@ -535,70 +529,38 @@ GLOBAL VARIABLES * DRXJ DAP structures */ -static int drxj_dap_read_block(struct i2c_device_addr *dev_addr, +static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr, u32 addr, u16 datasize, u8 *data, u32 flags); -static int drxj_dap_read_modify_write_reg8(struct i2c_device_addr *dev_addr, - u32 waddr, - u32 raddr, - u8 wdata, u8 *rdata); static int drxj_dap_read_modify_write_reg16(struct i2c_device_addr *dev_addr, u32 waddr, u32 raddr, u16 wdata, u16 *rdata); -static int drxj_dap_read_modify_write_reg32(struct i2c_device_addr *dev_addr, - u32 waddr, - u32 raddr, - u32 wdata, u32 *rdata); - -static int drxj_dap_read_reg8(struct i2c_device_addr *dev_addr, - u32 addr, - u8 *data, u32 flags); - static int drxj_dap_read_reg16(struct i2c_device_addr *dev_addr, u32 addr, u16 *data, u32 flags); -static int drxj_dap_read_reg32(struct i2c_device_addr *dev_addr, +static int drxdap_fasi_read_reg32(struct i2c_device_addr *dev_addr, u32 addr, u32 *data, u32 flags); -static int drxj_dap_write_block(struct i2c_device_addr *dev_addr, +static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr, u32 addr, u16 datasize, u8 *data, u32 flags); -static int drxj_dap_write_reg8(struct i2c_device_addr *dev_addr, - u32 addr, - u8 data, u32 flags); - static int drxj_dap_write_reg16(struct i2c_device_addr *dev_addr, u32 addr, u16 data, u32 flags); -static int drxj_dap_write_reg32(struct i2c_device_addr *dev_addr, +static int drxdap_fasi_write_reg32(struct i2c_device_addr *dev_addr, u32 addr, u32 data, u32 flags); -/* The structure containing the protocol interface */ -struct drx_access_func drx_dap_drxj_funct_g = { - drxj_dap_write_block, /* Supported */ - drxj_dap_read_block, /* Supported */ - drxj_dap_write_reg8, /* Not supported */ - drxj_dap_read_reg8, /* Not supported */ - drxj_dap_read_modify_write_reg8, /* Not supported */ - drxj_dap_write_reg16, /* Supported */ - drxj_dap_read_reg16, /* Supported */ - drxj_dap_read_modify_write_reg16, /* Supported */ - drxj_dap_write_reg32, /* Supported */ - drxj_dap_read_reg32, /* Supported */ - drxj_dap_read_modify_write_reg32, /* Not supported */ -}; - struct drxj_data drxj_data_g = { false, /* has_lna : true if LNA (aka PGA) present */ false, /* has_oob : true if OOB supported */ @@ -929,7 +891,6 @@ struct drx_common_attr drxj_default_comm_attr_g = { * \brief Default drxj demodulator instance. */ struct drx_demod_instance drxj_default_demod_g = { - &DRXJ_DAP, /* data access protocol functions */ &drxj_default_addr_g, /* i2c address & device id */ &drxj_default_comm_attr_g, /* demod common attributes */ &drxj_data_g /* demod device specific attributes */ @@ -1540,43 +1501,6 @@ bool is_handled_by_aud_tr_if(u32 addr) /*============================================================================*/ -/* Functions not supported by protocol*/ - -static int drxdap_fasi_write_reg8(struct i2c_device_addr *dev_addr, /* address of I2C device */ - u32 addr, /* address of register */ - u8 data, /* data to write */ - u32 flags) -{ /* special device flags */ - return -EIO; -} - -static int drxdap_fasi_read_reg8(struct i2c_device_addr *dev_addr, /* address of I2C device */ - u32 addr, /* address of register */ - u8 *data, /* buffer to receive data */ - u32 flags) -{ /* special device flags */ - return -EIO; -} - -static int drxdap_fasi_read_modify_write_reg8(struct i2c_device_addr *dev_addr, /* address of I2C device */ - u32 waddr, /* address of register */ - u32 raddr, /* address to read back from */ - u8 datain, /* data to send */ - u8 *dataout) -{ /* data to receive back */ - return -EIO; -} - -static int drxdap_fasi_read_modify_write_reg32(struct i2c_device_addr *dev_addr, /* address of I2C device */ - u32 waddr, /* address of register */ - u32 raddr, /* address to read back from */ - u32 datain, /* data to send */ - u32 *dataout) -{ /* data to receive back */ - return -EIO; -} - - int drxbsp_i2c_write_read(struct i2c_device_addr *w_dev_addr, u16 w_count, u8 *wData, @@ -2073,27 +1997,6 @@ static int drxdap_fasi_write_reg32(struct i2c_device_addr *dev_addr, return drxdap_fasi_write_block(dev_addr, addr, sizeof(data), buf, flags); } -static int drxj_dap_read_block(struct i2c_device_addr *dev_addr, - u32 addr, - u16 datasize, - u8 *data, u32 flags) -{ - return drxdap_fasi_read_block(dev_addr, - addr, datasize, data, flags); -} - -/*============================================================================*/ - -static int drxj_dap_read_modify_write_reg8(struct i2c_device_addr *dev_addr, - u32 waddr, - u32 raddr, - u8 wdata, u8 *rdata) -{ - return drxdap_fasi_read_modify_write_reg8(dev_addr, - waddr, - raddr, wdata, rdata); -} - /*============================================================================*/ /** @@ -2172,26 +2075,6 @@ static int drxj_dap_read_modify_write_reg16(struct i2c_device_addr *dev_addr, #endif } -/*============================================================================*/ - -static int drxj_dap_read_modify_write_reg32(struct i2c_device_addr *dev_addr, - u32 waddr, - u32 raddr, - u32 wdata, u32 *rdata) -{ - return drxdap_fasi_read_modify_write_reg32(dev_addr, - waddr, - raddr, wdata, rdata); -} - -/*============================================================================*/ - -static int drxj_dap_read_reg8(struct i2c_device_addr *dev_addr, - u32 addr, - u8 *data, u32 flags) -{ - return drxdap_fasi_read_reg8(dev_addr, addr, data, flags); -} /*============================================================================*/ @@ -2296,41 +2179,10 @@ static int drxj_dap_read_reg16(struct i2c_device_addr *dev_addr, if (is_handled_by_aud_tr_if(addr)) stat = drxj_dap_read_aud_reg16(dev_addr, addr, data); else - stat = drxdap_fasi_read_reg16(dev_addr, - addr, data, flags); + stat = drxdap_fasi_read_reg16(dev_addr, addr, data, flags); return stat; } - -/*============================================================================*/ - -static int drxj_dap_read_reg32(struct i2c_device_addr *dev_addr, - u32 addr, - u32 *data, u32 flags) -{ - return drxdap_fasi_read_reg32(dev_addr, addr, data, flags); -} - -/*============================================================================*/ - -static int drxj_dap_write_block(struct i2c_device_addr *dev_addr, - u32 addr, - u16 datasize, - u8 *data, u32 flags) -{ - return drxdap_fasi_write_block(dev_addr, - addr, datasize, data, flags); -} - -/*============================================================================*/ - -static int drxj_dap_write_reg8(struct i2c_device_addr *dev_addr, - u32 addr, - u8 data, u32 flags) -{ - return drxdap_fasi_write_reg8(dev_addr, addr, data, flags); -} - /*============================================================================*/ /** @@ -2413,15 +2265,6 @@ static int drxj_dap_write_reg16(struct i2c_device_addr *dev_addr, /*============================================================================*/ -static int drxj_dap_write_reg32(struct i2c_device_addr *dev_addr, - u32 addr, - u32 data, u32 flags) -{ - return drxdap_fasi_write_reg32(dev_addr, addr, data, flags); -} - -/*============================================================================*/ - /* Free data ram in SIO HI */ #define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040 #define SIO_HI_RA_RAM_USR_END__A 0x420060 @@ -2627,34 +2470,34 @@ hi_command(struct i2c_device_addr *dev_addr, const struct drxj_hi_cmd *cmd, u16 case SIO_HI_RA_RAM_CMD_CONFIG: case SIO_HI_RA_RAM_CMD_ATOMIC_COPY: - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_HI_RA_RAM_PAR_6__A, cmd->param6, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_6__A, cmd->param6, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_HI_RA_RAM_PAR_5__A, cmd->param5, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_5__A, cmd->param5, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_HI_RA_RAM_PAR_4__A, cmd->param4, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_4__A, cmd->param4, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_HI_RA_RAM_PAR_3__A, cmd->param3, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_3__A, cmd->param3, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* fallthrough */ case SIO_HI_RA_RAM_CMD_BRDCTRL: - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_HI_RA_RAM_PAR_2__A, cmd->param2, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_2__A, cmd->param2, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_HI_RA_RAM_PAR_1__A, cmd->param1, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_1__A, cmd->param1, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -2670,7 +2513,7 @@ hi_command(struct i2c_device_addr *dev_addr, const struct drxj_hi_cmd *cmd, u16 } /* Write command */ - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_HI_RA_RAM_CMD__A, cmd->cmd, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_CMD__A, cmd->cmd, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -2693,7 +2536,7 @@ hi_command(struct i2c_device_addr *dev_addr, const struct drxj_hi_cmd *cmd, u16 goto rw_error; } - rc = DRXJ_DAP.read_reg16func(dev_addr, SIO_HI_RA_RAM_CMD__A, &wait_cmd, 0); + rc = drxj_dap_read_reg16(dev_addr, SIO_HI_RA_RAM_CMD__A, &wait_cmd, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -2701,7 +2544,7 @@ hi_command(struct i2c_device_addr *dev_addr, const struct drxj_hi_cmd *cmd, u16 } while (wait_cmd != 0); /* Read result */ - rc = DRXJ_DAP.read_reg16func(dev_addr, SIO_HI_RA_RAM_RES__A, result, 0); + rc = drxj_dap_read_reg16(dev_addr, SIO_HI_RA_RAM_RES__A, result, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -2739,7 +2582,7 @@ static int init_hi(const struct drx_demod_instance *demod) dev_addr = demod->my_i2c_dev_addr; /* PATCH for bug 5003, HI ucode v3.1.0 */ - rc = DRXJ_DAP.write_reg16func(dev_addr, 0x4301D7, 0x801, 0); + rc = drxj_dap_write_reg16(dev_addr, 0x4301D7, 0x801, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -2825,17 +2668,17 @@ static int get_device_capabilities(struct drx_demod_instance *demod) ext_attr = (struct drxj_data *) demod->my_ext_attr; dev_addr = demod->my_i2c_dev_addr; - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.read_reg16func(dev_addr, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg, 0); + rc = drxj_dap_read_reg16(dev_addr, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -2865,7 +2708,7 @@ static int get_device_capabilities(struct drx_demod_instance *demod) Determine device capabilities Based on pinning v47 */ - rc = DRXJ_DAP.read_reg32func(dev_addr, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo, 0); + rc = drxdap_fasi_read_reg32(dev_addr, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -2874,18 +2717,18 @@ static int get_device_capabilities(struct drx_demod_instance *demod) switch ((sio_top_jtagid_lo >> 12) & 0xFF) { case 0x31: - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.read_reg16func(dev_addr, SIO_PDR_UIO_IN_HI__A, &bid, 0); + rc = drxj_dap_read_reg16(dev_addr, SIO_PDR_UIO_IN_HI__A, &bid, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } bid = (bid >> 10) & 0xf; - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -3121,51 +2964,51 @@ ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o return 0; } - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_OCR_INVERT__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_OCR_INVERT__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } switch (ext_attr->standard) { case DRX_STANDARD_8VSB: - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_FCT_USAGE__A, 7, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_USAGE__A, 7, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* 2048 bytes fifo ram */ - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_TMD_CTL_UPD_RATE__A, 10, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_CTL_UPD_RATE__A, 10, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_TMD_INT_UPD_RATE__A, 10, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_INT_UPD_RATE__A, 10, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_AVR_PARM_A__A, 5, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_A__A, 5, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_AVR_PARM_B__A, 7, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_B__A, 7, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_RCN_GAIN__A, 10, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, 10, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Low Water Mark for synchronization */ - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_SNC_LWM__A, 3, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_LWM__A, 3, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* High Water Mark for synchronization */ - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_SNC_HWM__A, 5, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_HWM__A, 5, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -3198,50 +3041,50 @@ ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o (ext_attr->curr_symbol_rate / 8) * nr_bits * 188; /* pass through b/c Annex A/c need following settings */ case DRX_STANDARD_ITU_B: - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_FCT_USAGE__A, FEC_OC_FCT_USAGE__PRE, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_USAGE__A, FEC_OC_FCT_USAGE__PRE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_TMD_CTL_UPD_RATE__A, FEC_OC_TMD_CTL_UPD_RATE__PRE, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_CTL_UPD_RATE__A, FEC_OC_TMD_CTL_UPD_RATE__PRE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_TMD_INT_UPD_RATE__A, 5, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_INT_UPD_RATE__A, 5, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_AVR_PARM_A__A, FEC_OC_AVR_PARM_A__PRE, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_A__A, FEC_OC_AVR_PARM_A__PRE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_AVR_PARM_B__A, FEC_OC_AVR_PARM_B__PRE, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_B__A, FEC_OC_AVR_PARM_B__PRE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } if (cfg_data->static_clk == true) { - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_RCN_GAIN__A, 0xD, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, 0xD, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } else { - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_RCN_GAIN__A, FEC_OC_RCN_GAIN__PRE, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, FEC_OC_RCN_GAIN__PRE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_SNC_LWM__A, 2, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_LWM__A, 2, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_SNC_HWM__A, 12, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_HWM__A, 12, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -3252,12 +3095,12 @@ ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o } /* swtich (standard) */ /* Check insertion of the Reed-Solomon parity bytes */ - rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_OC_MODE__A, &fec_oc_reg_mode, 0); + rc = drxj_dap_read_reg16(dev_addr, FEC_OC_MODE__A, &fec_oc_reg_mode, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode, 0); + rc = drxj_dap_read_reg16(dev_addr, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -3413,70 +3256,70 @@ ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o dto_rate = frac28(bit_rate, common_attr->sys_clock_freq * 1000); dto_rate >>= 3; - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_DTO_RATE_HI__A, (u16)((dto_rate >> 16) & FEC_OC_DTO_RATE_HI__M), 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_RATE_HI__A, (u16)((dto_rate >> 16) & FEC_OC_DTO_RATE_HI__M), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_DTO_RATE_LO__A, (u16)(dto_rate & FEC_OC_DTO_RATE_LO_RATE_LO__M), 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_RATE_LO__A, (u16)(dto_rate & FEC_OC_DTO_RATE_LO_RATE_LO__M), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M | FEC_OC_DTO_MODE_OFFSET_ENABLE__M, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M | FEC_OC_DTO_MODE_OFFSET_ENABLE__M, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_FCT_MODE__A, FEC_OC_FCT_MODE_RAT_ENA__M | FEC_OC_FCT_MODE_VIRT_ENA__M, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_MODE__A, FEC_OC_FCT_MODE_RAT_ENA__M | FEC_OC_FCT_MODE_VIRT_ENA__M, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_DTO_BURST_LEN__A, fec_oc_dto_burst_len, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_BURST_LEN__A, fec_oc_dto_burst_len, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } if (ext_attr->mpeg_output_clock_rate != DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO) fec_oc_dto_period = ext_attr->mpeg_output_clock_rate - 1; - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } else { /* Dynamic mode */ - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_FCT_MODE__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_MODE__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } - rc = DRXJ_DAP.write_reg32func(dev_addr, FEC_OC_RCN_CTL_RATE_LO__A, rcn_rate, 0); + rc = drxdap_fasi_write_reg32(dev_addr, FEC_OC_RCN_CTL_RATE_LO__A, rcn_rate, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Write appropriate registers with requested configuration */ - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_MODE__A, fec_oc_reg_mode, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_MODE__A, fec_oc_reg_mode, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_IPR_INVERT__A, fec_oc_reg_ipr_invert, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_INVERT__A, fec_oc_reg_ipr_invert, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -3484,28 +3327,28 @@ ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o /* enabling for both parallel and serial now */ /* Write magic word to enable pdr reg write */ - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Set MPEG TS pads to outputmode */ - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MSTRT_CFG__A, 0x0013, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MSTRT_CFG__A, 0x0013, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MERR_CFG__A, 0x0013, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MERR_CFG__A, 0x0013, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MCLK_CFG__A, MPEG_OUTPUT_CLK_DRIVE_STRENGTH << SIO_PDR_MCLK_CFG_DRIVE__B | 0x03 << SIO_PDR_MCLK_CFG_MODE__B, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MCLK_CFG__A, MPEG_OUTPUT_CLK_DRIVE_STRENGTH << SIO_PDR_MCLK_CFG_DRIVE__B | 0x03 << SIO_PDR_MCLK_CFG_MODE__B, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MVAL_CFG__A, 0x0013, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MVAL_CFG__A, 0x0013, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -3513,7 +3356,7 @@ ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o sio_pdr_md_cfg = MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH << SIO_PDR_MD0_CFG_DRIVE__B | 0x03 << SIO_PDR_MD0_CFG_MODE__B; - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD0_CFG__A, sio_pdr_md_cfg, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, sio_pdr_md_cfg, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -3523,171 +3366,171 @@ ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH << SIO_PDR_MD0_CFG_DRIVE__B | 0x03 << SIO_PDR_MD0_CFG_MODE__B; - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD0_CFG__A, sio_pdr_md_cfg, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, sio_pdr_md_cfg, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD1_CFG__A, sio_pdr_md_cfg, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, sio_pdr_md_cfg, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD2_CFG__A, sio_pdr_md_cfg, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, sio_pdr_md_cfg, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD3_CFG__A, sio_pdr_md_cfg, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, sio_pdr_md_cfg, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD4_CFG__A, sio_pdr_md_cfg, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, sio_pdr_md_cfg, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD5_CFG__A, sio_pdr_md_cfg, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, sio_pdr_md_cfg, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD6_CFG__A, sio_pdr_md_cfg, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, sio_pdr_md_cfg, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD7_CFG__A, sio_pdr_md_cfg, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, sio_pdr_md_cfg, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } else { /* MPEG data output is serial -> set MD1 to MD7 to tri-state */ - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD1_CFG__A, 0x0000, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, 0x0000, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD2_CFG__A, 0x0000, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, 0x0000, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD3_CFG__A, 0x0000, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, 0x0000, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD4_CFG__A, 0x0000, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, 0x0000, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD5_CFG__A, 0x0000, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, 0x0000, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD6_CFG__A, 0x0000, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, 0x0000, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD7_CFG__A, 0x0000, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, 0x0000, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } /* Enable Monitor Bus output over MPEG pads and ctl input */ - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MON_CFG__A, 0x0000, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MON_CFG__A, 0x0000, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Write nomagic word to enable pdr reg write */ - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } else { /* Write magic word to enable pdr reg write */ - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Set MPEG TS pads to inputmode */ - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MSTRT_CFG__A, 0x0000, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MSTRT_CFG__A, 0x0000, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MERR_CFG__A, 0x0000, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MERR_CFG__A, 0x0000, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MCLK_CFG__A, 0x0000, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MCLK_CFG__A, 0x0000, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MVAL_CFG__A, 0x0000, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MVAL_CFG__A, 0x0000, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD0_CFG__A, 0x0000, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, 0x0000, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD1_CFG__A, 0x0000, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, 0x0000, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD2_CFG__A, 0x0000, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, 0x0000, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD3_CFG__A, 0x0000, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, 0x0000, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD4_CFG__A, 0x0000, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, 0x0000, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD5_CFG__A, 0x0000, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, 0x0000, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD6_CFG__A, 0x0000, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, 0x0000, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD7_CFG__A, 0x0000, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, 0x0000, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Enable Monitor Bus output over MPEG pads and ctl input */ - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MON_CFG__A, 0x0000, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MON_CFG__A, 0x0000, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Write nomagic word to enable pdr reg write */ - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -3758,7 +3601,7 @@ ctrl_get_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o goto rw_error; } if ((lock_status == DRX_LOCKED)) { - rc = DRXJ_DAP.read_reg32func(dev_addr, FEC_OC_RCN_DYN_RATE_LO__A, &rate_reg, 0); + rc = drxdap_fasi_read_reg32(dev_addr, FEC_OC_RCN_DYN_RATE_LO__A, &rate_reg, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -3804,17 +3647,17 @@ static int set_mpegtei_handling(struct drx_demod_instance *demod) dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; - rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_OC_DPR_MODE__A, &fec_oc_dpr_mode, 0); + rc = drxj_dap_read_reg16(dev_addr, FEC_OC_DPR_MODE__A, &fec_oc_dpr_mode, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode, 0); + rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_OC_EMS_MODE__A, &fec_oc_ems_mode, 0); + rc = drxj_dap_read_reg16(dev_addr, FEC_OC_EMS_MODE__A, &fec_oc_ems_mode, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -3834,17 +3677,17 @@ static int set_mpegtei_handling(struct drx_demod_instance *demod) fec_oc_ems_mode |= ((0x01) << (FEC_OC_EMS_MODE_MODE__B)); } - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_DPR_MODE__A, fec_oc_dpr_mode, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DPR_MODE__A, fec_oc_dpr_mode, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_SNC_MODE__A, fec_oc_snc_mode, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_MODE__A, fec_oc_snc_mode, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_EMS_MODE__A, fec_oc_ems_mode, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_EMS_MODE__A, fec_oc_ems_mode, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -3875,7 +3718,7 @@ static int bit_reverse_mpeg_output(struct drx_demod_instance *demod) dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; - rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode, 0); + rc = drxj_dap_read_reg16(dev_addr, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -3887,7 +3730,7 @@ static int bit_reverse_mpeg_output(struct drx_demod_instance *demod) if (ext_attr->bit_reverse_mpeg_outout) fec_oc_ipr_mode |= FEC_OC_IPR_MODE_REVERSE_ORDER__M; - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -3919,7 +3762,7 @@ static int set_mpeg_output_clock_rate(struct drx_demod_instance *demod) ext_attr = (struct drxj_data *) demod->my_ext_attr; if (ext_attr->mpeg_output_clock_rate != DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO) { - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_DTO_PERIOD__A, ext_attr->mpeg_output_clock_rate - 1, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_PERIOD__A, ext_attr->mpeg_output_clock_rate - 1, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -3956,7 +3799,7 @@ static int set_mpeg_start_width(struct drx_demod_instance *demod) if ((common_attr->mpeg_cfg.static_clk == true) && (common_attr->mpeg_cfg.enable_parallel == false)) { - rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_OC_COMM_MB__A, &fec_oc_comm_mb, 0); + rc = drxj_dap_read_reg16(dev_addr, FEC_OC_COMM_MB__A, &fec_oc_comm_mb, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -3964,7 +3807,7 @@ static int set_mpeg_start_width(struct drx_demod_instance *demod) fec_oc_comm_mb &= ~FEC_OC_COMM_MB_CTL_ON; if (ext_attr->mpeg_start_width == DRXJ_MPEG_START_WIDTH_8CLKCYC) fec_oc_comm_mb |= FEC_OC_COMM_MB_CTL_ON; - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_COMM_MB__A, fec_oc_comm_mb, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_COMM_MB__A, fec_oc_comm_mb, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -4073,7 +3916,7 @@ ctrl_get_cfg_mpeg_output_misc(struct drx_demod_instance *demod, if (ext_attr->mpeg_output_clock_rate != DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO) { cfg_data->mpeg_output_clock_rate = ext_attr->mpeg_output_clock_rate; } else { - rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, FEC_OC_DTO_PERIOD__A, &data, 0); + rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, FEC_OC_DTO_PERIOD__A, &data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -4110,17 +3953,17 @@ ctrl_get_cfg_hw_cfg(struct drx_demod_instance *demod, struct drxj_cfg_hw_cfg *cf if (cfg_data == NULL) return -EINVAL; - rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0); + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SIO_PDR_OHW_CFG__A, &data, 0); + rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_OHW_CFG__A, &data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -4160,7 +4003,7 @@ static int ctrl_set_uio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg ext_attr = (struct drxj_data *) demod->my_ext_attr; /* Write magic word to enable pdr reg write */ - rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -4180,7 +4023,7 @@ static int ctrl_set_uio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg case DRX_UIO_MODE_DISABLE: ext_attr->uio_sma_tx_mode = uio_cfg->mode; /* pad configuration register is set 0 - input mode */ - rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0, 0); + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -4203,7 +4046,7 @@ static int ctrl_set_uio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg case DRX_UIO_MODE_DISABLE: ext_attr->uio_sma_rx_mode = uio_cfg->mode; /* pad configuration register is set 0 - input mode */ - rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, 0, 0); + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -4227,7 +4070,7 @@ static int ctrl_set_uio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg case DRX_UIO_MODE_DISABLE: ext_attr->uio_gpio_mode = uio_cfg->mode; /* pad configuration register is set 0 - input mode */ - rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, 0, 0); + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -4249,7 +4092,7 @@ static int ctrl_set_uio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg break; case DRX_UIO_MODE_DISABLE: /* pad configuration register is set 0 - input mode */ - rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, 0, 0); + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -4268,7 +4111,7 @@ static int ctrl_set_uio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg } /* switch ( uio_cfg->uio ) */ /* Write magic word to disable pdr reg write */ - rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -4343,7 +4186,7 @@ ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data) ext_attr = (struct drxj_data *) demod->my_ext_attr; /* Write magic word to enable pdr reg write */ - rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -4365,14 +4208,14 @@ ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data) /* io_pad_cfg_drive is set to power 2 (23 mA) */ /* write to io pad configuration register - output mode */ - rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, pin_cfg_value, 0); + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, pin_cfg_value, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* use corresponding bit in io data output registar */ - rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0); + rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -4383,7 +4226,7 @@ ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data) value |= 0x8000; /* write one to 15th bit - 1st UIO */ /* write back to io data output register */ - rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0); + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -4404,14 +4247,14 @@ ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data) /* io_pad_cfg_drive is set to power 2 (23 mA) */ /* write to io pad configuration register - output mode */ - rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, pin_cfg_value, 0); + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, pin_cfg_value, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* use corresponding bit in io data output registar */ - rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0); + rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -4422,7 +4265,7 @@ ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data) value |= 0x4000; /* write one to 14th bit - 2nd UIO */ /* write back to io data output register */ - rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0); + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -4443,14 +4286,14 @@ ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data) /* io_pad_cfg_drive is set to power 2 (23 mA) */ /* write to io pad configuration register - output mode */ - rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, pin_cfg_value, 0); + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, pin_cfg_value, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* use corresponding bit in io data output registar */ - rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, &value, 0); + rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, &value, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -4461,7 +4304,7 @@ ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data) value |= 0x0004; /* write one to 2nd bit - 3rd UIO */ /* write back to io data output register */ - rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, value, 0); + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, value, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -4483,14 +4326,14 @@ ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data) /* io_pad_cfg_drive is set to power 2 (23 mA) */ /* write to io pad configuration register - output mode */ - rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, pin_cfg_value, 0); + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, pin_cfg_value, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* use corresponding bit in io data output registar */ - rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0); + rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -4501,7 +4344,7 @@ ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data) value |= 0x1000; /* write one to 12th bit - 4th UIO */ /* write back to io data output register */ - rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0); + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -4513,7 +4356,7 @@ ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data) } /* switch ( uio_data->uio ) */ /* Write magic word to disable pdr reg write */ - rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -4545,7 +4388,7 @@ static int ctrl_uio_read(struct drx_demod_instance *demod, struct drxuio_data *u ext_attr = (struct drxj_data *) demod->my_ext_attr; /* Write magic word to enable pdr reg write */ - rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -4567,13 +4410,13 @@ static int ctrl_uio_read(struct drx_demod_instance *demod, struct drxuio_data *u /* io_pad_cfg_drive is set to power 2 (23 mA) */ /* write to io pad configuration register - input mode */ - rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, pin_cfg_value, 0); + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, pin_cfg_value, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SIO_PDR_UIO_IN_LO__A, &value, 0); + rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_IN_LO__A, &value, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -4600,13 +4443,13 @@ static int ctrl_uio_read(struct drx_demod_instance *demod, struct drxuio_data *u /* io_pad_cfg_drive is set to power 2 (23 mA) */ /* write to io pad configuration register - input mode */ - rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, pin_cfg_value, 0); + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, pin_cfg_value, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SIO_PDR_UIO_IN_LO__A, &value, 0); + rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_IN_LO__A, &value, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -4634,14 +4477,14 @@ static int ctrl_uio_read(struct drx_demod_instance *demod, struct drxuio_data *u /* io_pad_cfg_drive is set to power 2 (23 mA) */ /* write to io pad configuration register - input mode */ - rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, pin_cfg_value, 0); + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, pin_cfg_value, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* read io input data registar */ - rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SIO_PDR_UIO_IN_HI__A, &value, 0); + rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_IN_HI__A, &value, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -4668,14 +4511,14 @@ static int ctrl_uio_read(struct drx_demod_instance *demod, struct drxuio_data *u /* io_pad_cfg_drive is set to power 2 (23 mA) */ /* write to io pad configuration register - input mode */ - rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, pin_cfg_value, 0); + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, pin_cfg_value, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* read io input data registar */ - rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SIO_PDR_UIO_IN_LO__A, &value, 0); + rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_IN_LO__A, &value, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -4692,7 +4535,7 @@ static int ctrl_uio_read(struct drx_demod_instance *demod, struct drxuio_data *u } /* switch ( uio_data->uio ) */ /* Write magic word to disable pdr reg write */ - rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -4765,25 +4608,25 @@ static int smart_ant_init(struct drx_demod_instance *demod) ext_attr = (struct drxj_data *) demod->my_ext_attr; /* Write magic word to enable pdr reg write */ - rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* init smart antenna */ - rc = DRXJ_DAP.read_reg16func(dev_addr, SIO_SA_TX_COMMAND__A, &data, 0); + rc = drxj_dap_read_reg16(dev_addr, SIO_SA_TX_COMMAND__A, &data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } if (ext_attr->smart_ant_inverted) { - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_SA_TX_COMMAND__A, (data | SIO_SA_TX_COMMAND_TX_INVERT__M) | SIO_SA_TX_COMMAND_TX_ENABLE__M, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_COMMAND__A, (data | SIO_SA_TX_COMMAND_TX_INVERT__M) | SIO_SA_TX_COMMAND_TX_ENABLE__M, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } else { - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_SA_TX_COMMAND__A, (data & (~SIO_SA_TX_COMMAND_TX_INVERT__M)) | SIO_SA_TX_COMMAND_TX_ENABLE__M, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_COMMAND__A, (data & (~SIO_SA_TX_COMMAND_TX_INVERT__M)) | SIO_SA_TX_COMMAND_TX_ENABLE__M, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -4796,19 +4639,19 @@ static int smart_ant_init(struct drx_demod_instance *demod) pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0x13, 0); + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0x13, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_GPIO_FNC__A, 0x03, 0); + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_GPIO_FNC__A, 0x03, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Write magic word to disable pdr reg write */ - rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -4855,7 +4698,7 @@ ctrl_set_cfg_smart_ant(struct drx_demod_instance *demod, struct drxj_cfg_smart_a } /* Write magic word to enable pdr reg write */ - rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -4870,7 +4713,7 @@ ctrl_set_cfg_smart_ant(struct drx_demod_instance *demod, struct drxj_cfg_smart_a */ start_time = jiffies_to_msecs(jiffies); do { - rc = DRXJ_DAP.read_reg16func(dev_addr, SIO_SA_TX_STATUS__A, &data, 0); + rc = drxj_dap_read_reg16(dev_addr, SIO_SA_TX_STATUS__A, &data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -4881,29 +4724,29 @@ ctrl_set_cfg_smart_ant(struct drx_demod_instance *demod, struct drxj_cfg_smart_a return -EIO; /* write to smart antenna configuration register */ - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_SA_TX_DATA0__A, 0x9200 | ((smart_ant->ctrl_data & 0x0001) << 8) | ((smart_ant->ctrl_data & 0x0002) << 10) | ((smart_ant->ctrl_data & 0x0004) << 12), 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_DATA0__A, 0x9200 | ((smart_ant->ctrl_data & 0x0001) << 8) | ((smart_ant->ctrl_data & 0x0002) << 10) | ((smart_ant->ctrl_data & 0x0004) << 12), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_SA_TX_DATA1__A, 0x4924 | ((smart_ant->ctrl_data & 0x0008) >> 2) | ((smart_ant->ctrl_data & 0x0010)) | ((smart_ant->ctrl_data & 0x0020) << 2) | ((smart_ant->ctrl_data & 0x0040) << 4) | ((smart_ant->ctrl_data & 0x0080) << 6), 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_DATA1__A, 0x4924 | ((smart_ant->ctrl_data & 0x0008) >> 2) | ((smart_ant->ctrl_data & 0x0010)) | ((smart_ant->ctrl_data & 0x0020) << 2) | ((smart_ant->ctrl_data & 0x0040) << 4) | ((smart_ant->ctrl_data & 0x0080) << 6), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_SA_TX_DATA2__A, 0x2492 | ((smart_ant->ctrl_data & 0x0100) >> 8) | ((smart_ant->ctrl_data & 0x0200) >> 6) | ((smart_ant->ctrl_data & 0x0400) >> 4) | ((smart_ant->ctrl_data & 0x0800) >> 2) | ((smart_ant->ctrl_data & 0x1000)) | ((smart_ant->ctrl_data & 0x2000) << 2), 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_DATA2__A, 0x2492 | ((smart_ant->ctrl_data & 0x0100) >> 8) | ((smart_ant->ctrl_data & 0x0200) >> 6) | ((smart_ant->ctrl_data & 0x0400) >> 4) | ((smart_ant->ctrl_data & 0x0800) >> 2) | ((smart_ant->ctrl_data & 0x1000)) | ((smart_ant->ctrl_data & 0x2000) << 2), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_SA_TX_DATA3__A, 0xff8d, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_DATA3__A, 0xff8d, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* trigger the sending */ - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_SA_TX_LENGTH__A, 56, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_LENGTH__A, 56, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -4920,7 +4763,7 @@ ctrl_set_cfg_smart_ant(struct drx_demod_instance *demod, struct drxj_cfg_smart_a return -EINVAL; } /* Write magic word to enable pdr reg write */ - rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -4943,7 +4786,7 @@ static int scu_command(struct i2c_device_addr *dev_addr, struct drxjscu_cmd *cmd return -EINVAL; /* Wait until SCU command interface is ready to receive command */ - rc = DRXJ_DAP.read_reg16func(dev_addr, SCU_RAM_COMMAND__A, &cur_cmd, 0); + rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_COMMAND__A, &cur_cmd, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -4953,31 +4796,31 @@ static int scu_command(struct i2c_device_addr *dev_addr, struct drxjscu_cmd *cmd switch (cmd->parameter_len) { case 5: - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_PARAM_4__A, *(cmd->parameter + 4), 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_4__A, *(cmd->parameter + 4), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* fallthrough */ case 4: - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_PARAM_3__A, *(cmd->parameter + 3), 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_3__A, *(cmd->parameter + 3), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* fallthrough */ case 3: - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_PARAM_2__A, *(cmd->parameter + 2), 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_2__A, *(cmd->parameter + 2), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* fallthrough */ case 2: - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_PARAM_1__A, *(cmd->parameter + 1), 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_1__A, *(cmd->parameter + 1), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* fallthrough */ case 1: - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_PARAM_0__A, *(cmd->parameter + 0), 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_0__A, *(cmd->parameter + 0), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -4989,7 +4832,7 @@ static int scu_command(struct i2c_device_addr *dev_addr, struct drxjscu_cmd *cmd /* this number of parameters is not supported */ return -EIO; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_COMMAND__A, cmd->command, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_COMMAND__A, cmd->command, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -4998,7 +4841,7 @@ static int scu_command(struct i2c_device_addr *dev_addr, struct drxjscu_cmd *cmd /* Wait until SCU has processed command */ timeout = jiffies + msecs_to_jiffies(DRXJ_MAX_WAITTIME); while (time_is_after_jiffies(timeout)) { - rc = DRXJ_DAP.read_reg16func(dev_addr, SCU_RAM_COMMAND__A, &cur_cmd, 0); + rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_COMMAND__A, &cur_cmd, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -5017,25 +4860,25 @@ static int scu_command(struct i2c_device_addr *dev_addr, struct drxjscu_cmd *cmd switch (cmd->result_len) { case 4: - rc = DRXJ_DAP.read_reg16func(dev_addr, SCU_RAM_PARAM_3__A, cmd->result + 3, 0); + rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_3__A, cmd->result + 3, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* fallthrough */ case 3: - rc = DRXJ_DAP.read_reg16func(dev_addr, SCU_RAM_PARAM_2__A, cmd->result + 2, 0); + rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_2__A, cmd->result + 2, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* fallthrough */ case 2: - rc = DRXJ_DAP.read_reg16func(dev_addr, SCU_RAM_PARAM_1__A, cmd->result + 1, 0); + rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_1__A, cmd->result + 1, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* fallthrough */ case 1: - rc = DRXJ_DAP.read_reg16func(dev_addr, SCU_RAM_PARAM_0__A, cmd->result + 0, 0); + rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_0__A, cmd->result + 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -5211,12 +5054,12 @@ static int adc_sync_measurement(struct drx_demod_instance *demod, u16 *count) dev_addr = demod->my_i2c_dev_addr; /* Start measurement */ - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_START_LOCK__A, 1, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_START_LOCK__A, 1, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -5226,21 +5069,21 @@ static int adc_sync_measurement(struct drx_demod_instance *demod, u16 *count) msleep(1); *count = 0; - rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_PHASE0__A, &data, 0); + rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE0__A, &data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } if (data == 127) *count = *count + 1; - rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_PHASE1__A, &data, 0); + rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE1__A, &data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } if (data == 127) *count = *count + 1; - rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_PHASE2__A, &data, 0); + rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE2__A, &data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -5283,14 +5126,14 @@ static int adc_synchronization(struct drx_demod_instance *demod) /* Try sampling on a diffrent edge */ u16 clk_neg = 0; - rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_CLKNEG__A, &clk_neg, 0); + rc = drxj_dap_read_reg16(dev_addr, IQM_AF_CLKNEG__A, &clk_neg, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } clk_neg ^= IQM_AF_CLKNEG_CLKNEGDATA__M; - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_CLKNEG__A, clk_neg, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLKNEG__A, clk_neg, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -5326,7 +5169,7 @@ static int iqm_set_af(struct drx_demod_instance *demod, bool active) u16 data = 0; /* Configure IQM */ - rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_STDBY__A, &data, 0); + rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -5335,7 +5178,7 @@ static int iqm_set_af(struct drx_demod_instance *demod, bool active) data &= ((~IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_PD_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE)); else data |= (IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE | IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE | IQM_AF_STDBY_STDBY_PD_A2_ACTIVE | IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE | IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE); - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_STDBY__A, data, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -5370,7 +5213,7 @@ ctrl_set_cfg_pdr_safe_mode(struct drx_demod_instance *demod, bool *enable) ext_attr = (struct drxj_data *) demod->my_ext_attr; /* Write magic word to enable pdr reg write */ - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -5380,62 +5223,62 @@ ctrl_set_cfg_pdr_safe_mode(struct drx_demod_instance *demod, bool *enable) bool bridge_enabled = false; /* MPEG pins to input */ - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MSTRT_CFG__A, DRXJ_PIN_SAFE_MODE, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MSTRT_CFG__A, DRXJ_PIN_SAFE_MODE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MERR_CFG__A, DRXJ_PIN_SAFE_MODE, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MERR_CFG__A, DRXJ_PIN_SAFE_MODE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MCLK_CFG__A, DRXJ_PIN_SAFE_MODE, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MCLK_CFG__A, DRXJ_PIN_SAFE_MODE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MVAL_CFG__A, DRXJ_PIN_SAFE_MODE, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MVAL_CFG__A, DRXJ_PIN_SAFE_MODE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD0_CFG__A, DRXJ_PIN_SAFE_MODE, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, DRXJ_PIN_SAFE_MODE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD1_CFG__A, DRXJ_PIN_SAFE_MODE, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, DRXJ_PIN_SAFE_MODE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD2_CFG__A, DRXJ_PIN_SAFE_MODE, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, DRXJ_PIN_SAFE_MODE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD3_CFG__A, DRXJ_PIN_SAFE_MODE, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, DRXJ_PIN_SAFE_MODE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD4_CFG__A, DRXJ_PIN_SAFE_MODE, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, DRXJ_PIN_SAFE_MODE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD5_CFG__A, DRXJ_PIN_SAFE_MODE, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, DRXJ_PIN_SAFE_MODE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD6_CFG__A, DRXJ_PIN_SAFE_MODE, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, DRXJ_PIN_SAFE_MODE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_MD7_CFG__A, DRXJ_PIN_SAFE_MODE, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, DRXJ_PIN_SAFE_MODE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -5448,12 +5291,12 @@ ctrl_set_cfg_pdr_safe_mode(struct drx_demod_instance *demod, bool *enable) pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_I2C_SDA2_CFG__A, DRXJ_PIN_SAFE_MODE, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_I2C_SDA2_CFG__A, DRXJ_PIN_SAFE_MODE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_I2C_SCL2_CFG__A, DRXJ_PIN_SAFE_MODE, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_I2C_SCL2_CFG__A, DRXJ_PIN_SAFE_MODE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -5463,42 +5306,42 @@ ctrl_set_cfg_pdr_safe_mode(struct drx_demod_instance *demod, bool *enable) PD_VSYNC Store and set to input PD_SMA_RX Store and set to input PD_SMA_TX Store and set to input */ - rc = DRXJ_DAP.read_reg16func(dev_addr, SIO_PDR_GPIO_CFG__A, &ext_attr->pdr_safe_restore_val_gpio, 0); + rc = drxj_dap_read_reg16(dev_addr, SIO_PDR_GPIO_CFG__A, &ext_attr->pdr_safe_restore_val_gpio, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.read_reg16func(dev_addr, SIO_PDR_VSYNC_CFG__A, &ext_attr->pdr_safe_restore_val_v_sync, 0); + rc = drxj_dap_read_reg16(dev_addr, SIO_PDR_VSYNC_CFG__A, &ext_attr->pdr_safe_restore_val_v_sync, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.read_reg16func(dev_addr, SIO_PDR_SMA_RX_CFG__A, &ext_attr->pdr_safe_restore_val_sma_rx, 0); + rc = drxj_dap_read_reg16(dev_addr, SIO_PDR_SMA_RX_CFG__A, &ext_attr->pdr_safe_restore_val_sma_rx, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.read_reg16func(dev_addr, SIO_PDR_SMA_TX_CFG__A, &ext_attr->pdr_safe_restore_val_sma_tx, 0); + rc = drxj_dap_read_reg16(dev_addr, SIO_PDR_SMA_TX_CFG__A, &ext_attr->pdr_safe_restore_val_sma_tx, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_GPIO_CFG__A, DRXJ_PIN_SAFE_MODE, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_GPIO_CFG__A, DRXJ_PIN_SAFE_MODE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_VSYNC_CFG__A, DRXJ_PIN_SAFE_MODE, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_VSYNC_CFG__A, DRXJ_PIN_SAFE_MODE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_SMA_RX_CFG__A, DRXJ_PIN_SAFE_MODE, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_SMA_RX_CFG__A, DRXJ_PIN_SAFE_MODE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_SMA_TX_CFG__A, DRXJ_PIN_SAFE_MODE, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_SMA_TX_CFG__A, DRXJ_PIN_SAFE_MODE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -5514,7 +5357,7 @@ ctrl_set_cfg_pdr_safe_mode(struct drx_demod_instance *demod, bool *enable) /* PD_CVBS Analog DAC output, standby mode PD_SIF Analog DAC output, standby mode */ - rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_STDBY__A, (ATV_TOP_STDBY_SIF_STDBY_STANDBY & (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE)), 0); + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STDBY__A, (ATV_TOP_STDBY_SIF_STDBY_STANDBY & (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE)), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -5523,17 +5366,17 @@ ctrl_set_cfg_pdr_safe_mode(struct drx_demod_instance *demod, bool *enable) /* PD_I2S_CL Input PD_I2S_DA Input PD_I2S_WS Input */ - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_I2S_CL_CFG__A, DRXJ_PIN_SAFE_MODE, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_I2S_CL_CFG__A, DRXJ_PIN_SAFE_MODE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_I2S_DA_CFG__A, DRXJ_PIN_SAFE_MODE, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_I2S_DA_CFG__A, DRXJ_PIN_SAFE_MODE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_I2S_WS_CFG__A, DRXJ_PIN_SAFE_MODE, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_I2S_WS_CFG__A, DRXJ_PIN_SAFE_MODE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -5544,12 +5387,12 @@ ctrl_set_cfg_pdr_safe_mode(struct drx_demod_instance *demod, bool *enable) /* PD_I2C_SDA2 Port2 active PD_I2C_SCL2 Port2 active */ - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_I2C_SDA2_CFG__A, SIO_PDR_I2C_SDA2_CFG__PRE, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_I2C_SDA2_CFG__A, SIO_PDR_I2C_SDA2_CFG__PRE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_I2C_SCL2_CFG__A, SIO_PDR_I2C_SCL2_CFG__PRE, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_I2C_SCL2_CFG__A, SIO_PDR_I2C_SCL2_CFG__PRE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -5559,22 +5402,22 @@ ctrl_set_cfg_pdr_safe_mode(struct drx_demod_instance *demod, bool *enable) PD_VSYNC Restore PD_SMA_RX Restore PD_SMA_TX Restore */ - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_GPIO_CFG__A, ext_attr->pdr_safe_restore_val_gpio, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_GPIO_CFG__A, ext_attr->pdr_safe_restore_val_gpio, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_VSYNC_CFG__A, ext_attr->pdr_safe_restore_val_v_sync, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_VSYNC_CFG__A, ext_attr->pdr_safe_restore_val_v_sync, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_SMA_RX_CFG__A, ext_attr->pdr_safe_restore_val_sma_rx, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_SMA_RX_CFG__A, ext_attr->pdr_safe_restore_val_sma_rx, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_SMA_TX_CFG__A, ext_attr->pdr_safe_restore_val_sma_tx, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_SMA_TX_CFG__A, ext_attr->pdr_safe_restore_val_sma_tx, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -5591,7 +5434,7 @@ ctrl_set_cfg_pdr_safe_mode(struct drx_demod_instance *demod, bool *enable) } /* Write magic word to disable pdr reg write */ - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -5684,67 +5527,67 @@ static int init_agc(struct drx_demod_instance *demod) ki_min = 0x0117; ingain_tgt_max = 16383; clp_ctrl_mode = 0; - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_CLP_SUM__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_CLP_CYCCNT__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCCNT__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_CLP_DIR_WD__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_WD__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_CLP_DIR_STP__A, 1, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_STP__A, 1, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_SNS_SUM__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_SNS_CYCCNT__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCCNT__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_SNS_DIR_WD__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_WD__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_SNS_DIR_STP__A, 1, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_STP__A, 1, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_INGAIN__A, 1024, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN__A, 1024, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_VSB_AGC_POW_TGT__A, 22600, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_VSB_AGC_POW_TGT__A, 22600, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, 13200, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, 13200, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -5767,71 +5610,71 @@ static int init_agc(struct drx_demod_instance *demod) agc_ki_dgain = 0x7; ki_min = 0x0117; clp_ctrl_mode = 0; - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_CLP_SUM__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_CLP_CYCCNT__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCCNT__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_CLP_DIR_WD__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_WD__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_CLP_DIR_STP__A, 1, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_STP__A, 1, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_SNS_SUM__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_SNS_CYCCNT__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCCNT__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_SNS_DIR_WD__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_WD__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_SNS_DIR_STP__A, 1, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_STP__A, 1, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } p_agc_if_settings = &(ext_attr->qam_if_agc_cfg); p_agc_rf_settings = &(ext_attr->qam_rf_agc_cfg); - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, p_agc_if_settings->top, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, p_agc_if_settings->top, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.read_reg16func(dev_addr, SCU_RAM_AGC_KI__A, &agc_ki, 0); + rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_AGC_KI__A, &agc_ki, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } agc_ki &= 0xf000; - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_KI__A, agc_ki, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI__A, agc_ki, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -5853,7 +5696,7 @@ static int init_agc(struct drx_demod_instance *demod) clp_ctrl_mode = 1; p_agc_if_settings = &(ext_attr->atv_if_agc_cfg); p_agc_rf_settings = &(ext_attr->atv_rf_agc_cfg); - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, p_agc_if_settings->top, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, p_agc_if_settings->top, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -5876,7 +5719,7 @@ static int init_agc(struct drx_demod_instance *demod) p_agc_rf_settings = &(ext_attr->atv_rf_agc_cfg); sns_dir_to = (u16) (-9); clp_ctrl_mode = 1; - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, p_agc_if_settings->top, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, p_agc_if_settings->top, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -5897,7 +5740,7 @@ static int init_agc(struct drx_demod_instance *demod) clp_ctrl_mode = 1; p_agc_if_settings = &(ext_attr->atv_if_agc_cfg); p_agc_rf_settings = &(ext_attr->atv_rf_agc_cfg); - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, p_agc_if_settings->top, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, p_agc_if_settings->top, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -5909,132 +5752,132 @@ static int init_agc(struct drx_demod_instance *demod) } /* for new AGC interface */ - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_if_settings->top, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_if_settings->top, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_INGAIN__A, p_agc_if_settings->top, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN__A, p_agc_if_settings->top, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Gain fed from inner to outer AGC */ - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, if_iaccu_hi_tgt_min, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, if_iaccu_hi_tgt_min, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_IF_IACCU_HI__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_HI__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* set to p_agc_settings->top before */ - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_IF_IACCU_LO__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_LO__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_RF_IACCU_LO__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_IACCU_LO__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_RF_MAX__A, 32767, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_MAX__A, 32767, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, ki_innergain_min, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, ki_innergain_min, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_KI_CYCLEN__A, 500, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_CYCLEN__A, 500, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_SNS_CYCLEN__A, 500, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCLEN__A, 500, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_KI_MIN__A, ki_min, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MIN__A, ki_min, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_KI_MAX__A, ki_max, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAX__A, ki_max, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_KI_RED__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_RED__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_CLP_SUM_MIN__A, 8, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM_MIN__A, 8, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_CLP_CYCLEN__A, 500, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCLEN__A, 500, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_SNS_SUM_MIN__A, 8, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM_MIN__A, 8, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, 50, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, 50, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -6048,26 +5891,26 @@ static int init_agc(struct drx_demod_instance *demod) if (common_attr->tuner_if_agc_pol == true) agc_rf = 0x87ff - agc_rf; - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_AGC_RF__A, agc_rf, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AGC_RF__A, agc_rf, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_AGC_IF__A, agc_if, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AGC_IF__A, agc_if, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Set/restore Ki DGAIN factor */ - rc = DRXJ_DAP.read_reg16func(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); + rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } data &= ~SCU_RAM_AGC_KI_DGAIN__M; data |= (agc_ki_dgain << SCU_RAM_AGC_KI_DGAIN__B); - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_AGC_KI__A, data, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI__A, data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -6162,7 +6005,7 @@ set_frequency(struct drx_demod_instance *demod, /* Program frequency shifter with tuner offset compensation */ /* frequency_shift += tuner_freq_offset; TODO */ - rc = DRXJ_DAP.write_reg32func(dev_addr, IQM_FS_RATE_OFS_LO__A, iqm_fs_rate_ofs, 0); + rc = drxdap_fasi_write_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, iqm_fs_rate_ofs, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -6202,13 +6045,13 @@ static int get_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength) u16 rf_agc_max = 0; u16 rf_agc_min = 0; - rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_AGC_IF__A, &if_gain, 0); + rc = drxj_dap_read_reg16(dev_addr, IQM_AF_AGC_IF__A, &if_gain, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } if_gain &= IQM_AF_AGC_IF__M; - rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_AGC_RF__A, &rf_gain, 0); + rc = drxj_dap_read_reg16(dev_addr, IQM_AF_AGC_RF__A, &rf_gain, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -6277,7 +6120,7 @@ static int get_acc_pkt_err(struct drx_demod_instance *demod, u16 *packet_err) ext_attr = (struct drxj_data *) demod->my_ext_attr; dev_addr = demod->my_i2c_dev_addr; - rc = DRXJ_DAP.read_reg16func(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, &data, 0); + rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, &data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -6456,8 +6299,8 @@ set_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, scu_rr16 = drxj_dap_scu_atomic_read_reg16; scu_wr16 = drxj_dap_scu_atomic_write_reg16; } else { - scu_rr16 = DRXJ_DAP.read_reg16func; - scu_wr16 = DRXJ_DAP.write_reg16func; + scu_rr16 = drxj_dap_read_reg16; + scu_wr16 = drxj_dap_write_reg16; } /* Configure AGC only if standard is currently active */ @@ -6472,13 +6315,13 @@ set_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, case DRX_AGC_CTRL_AUTO: /* Enable RF AGC DAC */ - rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_STDBY__A, &data, 0); + rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } data |= IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE; - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_STDBY__A, data, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -6554,13 +6397,13 @@ set_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, case DRX_AGC_CTRL_USER: /* Enable RF AGC DAC */ - rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_STDBY__A, &data, 0); + rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } data |= IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE; - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_STDBY__A, data, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -6593,13 +6436,13 @@ set_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, case DRX_AGC_CTRL_OFF: /* Disable RF AGC DAC */ - rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_STDBY__A, &data, 0); + rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } data &= (~IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE); - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_STDBY__A, data, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -6748,8 +6591,8 @@ set_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, scu_rr16 = drxj_dap_scu_atomic_read_reg16; scu_wr16 = drxj_dap_scu_atomic_write_reg16; } else { - scu_rr16 = DRXJ_DAP.read_reg16func; - scu_wr16 = DRXJ_DAP.write_reg16func; + scu_rr16 = drxj_dap_read_reg16; + scu_wr16 = drxj_dap_write_reg16; } /* Configure AGC only if standard is currently active */ @@ -6763,13 +6606,13 @@ set_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, switch (agc_settings->ctrl_mode) { case DRX_AGC_CTRL_AUTO: /* Enable IF AGC DAC */ - rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_STDBY__A, &data, 0); + rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } data |= IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE; - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_STDBY__A, data, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -6851,13 +6694,13 @@ set_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, case DRX_AGC_CTRL_USER: /* Enable IF AGC DAC */ - rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_STDBY__A, &data, 0); + rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } data |= IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE; - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_STDBY__A, data, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -6892,13 +6735,13 @@ set_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, case DRX_AGC_CTRL_OFF: /* Disable If AGC DAC */ - rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_STDBY__A, &data, 0); + rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } data &= (~IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE); - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_STDBY__A, data, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -7044,7 +6887,7 @@ static int set_iqm_af(struct drx_demod_instance *demod, bool active) dev_addr = demod->my_i2c_dev_addr; /* Configure IQM */ - rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_STDBY__A, &data, 0); + rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -7053,7 +6896,7 @@ static int set_iqm_af(struct drx_demod_instance *demod, bool active) data &= ((~IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_PD_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE)); else data |= (IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE | IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE | IQM_AF_STDBY_STDBY_PD_A2_ACTIVE | IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE | IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE); - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_STDBY__A, data, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -7111,18 +6954,18 @@ static int power_down_vsb(struct drx_demod_instance *demod, bool primary) } /* stop all comm_exec */ - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP, 0); + rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } if (primary) { - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -7133,27 +6976,27 @@ static int power_down_vsb(struct drx_demod_instance *demod, bool primary) goto rw_error; } } else { - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -7372,12 +7215,12 @@ static int set_vsb_leak_n_gain(struct drx_demod_instance *demod) }; dev_addr = demod->my_i2c_dev_addr; - rc = DRXJ_DAP.write_block_func(dev_addr, VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__A, sizeof(vsb_ffe_leak_gain_ram0), ((u8 *)vsb_ffe_leak_gain_ram0), 0); + rc = drxdap_fasi_write_block(dev_addr, VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__A, sizeof(vsb_ffe_leak_gain_ram0), ((u8 *)vsb_ffe_leak_gain_ram0), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_block_func(dev_addr, VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__A, sizeof(vsb_ffe_leak_gain_ram1), ((u8 *)vsb_ffe_leak_gain_ram1), 0); + rc = drxdap_fasi_write_block(dev_addr, VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__A, sizeof(vsb_ffe_leak_gain_ram1), ((u8 *)vsb_ffe_leak_gain_ram1), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -7440,37 +7283,37 @@ static int set_vsb(struct drx_demod_instance *demod) ext_attr = (struct drxj_data *) demod->my_ext_attr; /* stop all comm_exec */ - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP, 0); + rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -7489,141 +7332,141 @@ static int set_vsb(struct drx_demod_instance *demod) goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_DCF_BYPASS__A, 1, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_DCF_BYPASS__A, 1, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_FS_ADJ_SEL__A, IQM_FS_ADJ_SEL_B_VSB, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_FS_ADJ_SEL__A, IQM_FS_ADJ_SEL_B_VSB, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RC_ADJ_SEL__A, IQM_RC_ADJ_SEL_B_VSB, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_RC_ADJ_SEL__A, IQM_RC_ADJ_SEL_B_VSB, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } ext_attr->iqm_rc_rate_ofs = 0x00AD0D79; - rc = DRXJ_DAP.write_reg32func(dev_addr, IQM_RC_RATE_OFS_LO__A, ext_attr->iqm_rc_rate_ofs, 0); + rc = drxdap_fasi_write_reg32(dev_addr, IQM_RC_RATE_OFS_LO__A, ext_attr->iqm_rc_rate_ofs, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_CFAGC_GAINSHIFT__A, 4, 0); + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CFAGC_GAINSHIFT__A, 4, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_CYGN1TRK__A, 1, 0); + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1TRK__A, 1, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RC_CROUT_ENA__A, 1, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_RC_CROUT_ENA__A, 1, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RC_STRETCH__A, 28, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_RC_STRETCH__A, 28, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_ACTIVE__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_RT_ACTIVE__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_SYMMETRIC__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SYMMETRIC__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_MIDTAP__A, 3, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, 3, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_VSB__M, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_VSB__M, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_SCALE__A, 1393, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE__A, 1393, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_SCALE_SH__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_POW_MEAS_LEN__A, 1, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 1, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(vsb_taps_re), ((u8 *)vsb_taps_re), 0); + rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(vsb_taps_re), ((u8 *)vsb_taps_re), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(vsb_taps_re), ((u8 *)vsb_taps_re), 0); + rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(vsb_taps_re), ((u8 *)vsb_taps_re), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_BNTHRESH__A, 330, 0); + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BNTHRESH__A, 330, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* set higher threshold */ - rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_CLPLASTNUM__A, 90, 0); + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CLPLASTNUM__A, 90, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* burst detection on */ - rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_SNRTH_RCA1__A, 0x0042, 0); + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_RCA1__A, 0x0042, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* drop thresholds by 1 dB */ - rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_SNRTH_RCA2__A, 0x0053, 0); + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_RCA2__A, 0x0053, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* drop thresholds by 2 dB */ - rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_EQCTRL__A, 0x1, 0); + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_EQCTRL__A, 0x1, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* cma on */ - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_GPIO__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_GPIO__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* GPIO */ /* Initialize the FEC Subsystem */ - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_TOP_ANNEX__A, FEC_TOP_ANNEX_D, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_TOP_ANNEX__A, FEC_TOP_ANNEX_D, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } { u16 fec_oc_snc_mode = 0; - rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode, 0); + rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* output data even when not locked */ - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_SNC_MODE__A, fec_oc_snc_mode | FEC_OC_SNC_MODE_UNLOCK_ENABLE__M, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_MODE__A, fec_oc_snc_mode | FEC_OC_SNC_MODE_UNLOCK_ENABLE__M, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -7631,22 +7474,22 @@ static int set_vsb(struct drx_demod_instance *demod) } /* set clip */ - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_CLP_LEN__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_LEN__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_CLP_TH__A, 470, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_TH__A, 470, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_SNS_LEN__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SNS_LEN__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_SNRTH_PT__A, 0xD4, 0); + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_PT__A, 0xD4, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -7654,75 +7497,75 @@ static int set_vsb(struct drx_demod_instance *demod) /* no transparent, no A&C framing; parity is set in mpegoutput */ { u16 fec_oc_reg_mode = 0; - rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_OC_MODE__A, &fec_oc_reg_mode, 0); + rc = drxj_dap_read_reg16(dev_addr, FEC_OC_MODE__A, &fec_oc_reg_mode, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_MODE__A, fec_oc_reg_mode & (~(FEC_OC_MODE_TRANSPARENT__M | FEC_OC_MODE_CLEAR__M | FEC_OC_MODE_RETAIN_FRAMING__M)), 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_MODE__A, fec_oc_reg_mode & (~(FEC_OC_MODE_TRANSPARENT__M | FEC_OC_MODE_CLEAR__M | FEC_OC_MODE_RETAIN_FRAMING__M)), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_DI_TIMEOUT_LO__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_DI_TIMEOUT_LO__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* timeout counter for restarting */ - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_DI_TIMEOUT_HI__A, 3, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_DI_TIMEOUT_HI__A, 3, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_RS_MODE__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MODE__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* bypass disabled */ /* initialize RS packet error measurement parameters */ - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_RS_MEASUREMENT_PERIOD__A, FEC_RS_MEASUREMENT_PERIOD, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PERIOD__A, FEC_RS_MEASUREMENT_PERIOD, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_RS_MEASUREMENT_PRESCALE__A, FEC_RS_MEASUREMENT_PRESCALE, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PRESCALE__A, FEC_RS_MEASUREMENT_PRESCALE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* init measurement period of MER/SER */ - rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_MEASUREMENT_PERIOD__A, VSB_TOP_MEASUREMENT_PERIOD, 0); + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_MEASUREMENT_PERIOD__A, VSB_TOP_MEASUREMENT_PERIOD, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg32func(dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0, 0); + rc = drxdap_fasi_write_reg32(dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_CKGN1TRK__A, 128, 0); + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CKGN1TRK__A, 128, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* B-Input to ADC, PGA+filter in standby */ if (!ext_attr->has_lna) { - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_AMUX__A, 0x02, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AMUX__A, 0x02, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -7826,42 +7669,42 @@ static int set_vsb(struct drx_demod_instance *demod) goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_BEAGC_GAINSHIFT__A, 0x0004, 0); + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BEAGC_GAINSHIFT__A, 0x0004, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_SNRTH_PT__A, 0x00D2, 0); + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_PT__A, 0x00D2, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_SYSSMTRNCTRL__A, VSB_TOP_SYSSMTRNCTRL__PRE | VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__M, 0); + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SYSSMTRNCTRL__A, VSB_TOP_SYSSMTRNCTRL__PRE | VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__M, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_BEDETCTRL__A, 0x142, 0); + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BEDETCTRL__A, 0x142, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_LBAGCREFLVL__A, 640, 0); + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_LBAGCREFLVL__A, 640, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_CYGN1ACQ__A, 4, 0); + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1ACQ__A, 4, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_CYGN1TRK__A, 2, 0); + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1TRK__A, 2, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_CYGN2TRK__A, 3, 0); + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN2TRK__A, 3, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -7880,17 +7723,17 @@ static int set_vsb(struct drx_demod_instance *demod) goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_ACTIVE, 0); + rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_ACTIVE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -7915,7 +7758,7 @@ static int get_vsb_post_rs_pck_err(struct i2c_device_addr *dev_addr, u16 *pck_er u16 packet_errors_mant = 0; u16 packet_errors_exp = 0; - rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_RS_NR_FAILURES__A, &data, 0); + rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_FAILURES__A, &data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -7954,7 +7797,7 @@ static int get_vs_bpost_viterbi_ber(struct i2c_device_addr *dev_addr, u32 *ber) u16 bit_errors_mant = 0; u16 bit_errors_exp = 0; - rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_RS_NR_BIT_ERRORS__A, &data, 0); + rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_BIT_ERRORS__A, &data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -7996,7 +7839,7 @@ static int get_vs_bpre_viterbi_ber(struct i2c_device_addr *dev_addr, u32 *ber) u16 data = 0; int rc; - rc = DRXJ_DAP.read_reg16func(dev_addr, VSB_TOP_NR_SYM_ERRS__A, &data, 0); + rc = drxj_dap_read_reg16(dev_addr, VSB_TOP_NR_SYM_ERRS__A, &data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -8025,7 +7868,7 @@ static int get_vsb_symb_err(struct i2c_device_addr *dev_addr, u32 *ser) u16 symb_errors_mant = 0; u16 symb_errors_exp = 0; - rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_RS_NR_SYMBOL_ERRORS__A, &data, 0); + rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_SYMBOL_ERRORS__A, &data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -8060,7 +7903,7 @@ static int get_vsbmer(struct i2c_device_addr *dev_addr, u16 *mer) int rc; u16 data_hi = 0; - rc = DRXJ_DAP.read_reg16func(dev_addr, VSB_TOP_ERR_ENERGY_H__A, &data_hi, 0); + rc = drxj_dap_read_reg16(dev_addr, VSB_TOP_ERR_ENERGY_H__A, &data_hi, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -8102,7 +7945,7 @@ ctrl_get_vsb_constel(struct drx_demod_instance *demod, struct drx_complex *compl /* Needs to be checked when external interface PG is updated */ /* Configure MB (Monitor bus) */ - rc = DRXJ_DAP.read_reg16func(dev_addr, VSB_TOP_COMM_MB__A, &vsb_top_comm_mb_init, 0); + rc = drxj_dap_read_reg16(dev_addr, VSB_TOP_COMM_MB__A, &vsb_top_comm_mb_init, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -8111,28 +7954,28 @@ ctrl_get_vsb_constel(struct drx_demod_instance *demod, struct drx_complex *compl vsb_top_comm_mb = (vsb_top_comm_mb_init | VSB_TOP_COMM_MB_OBS_OBS_ON | VSB_TOP_COMM_MB_MUX_OBS_VSB_TCMEQ_2); - rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_COMM_MB__A, vsb_top_comm_mb, 0); + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_COMM_MB__A, vsb_top_comm_mb, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Enable MB grabber in the FEC OC */ - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_OCR_MODE__A, FEC_OC_OCR_MODE_GRAB_ENABLE__M, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_OCR_MODE__A, FEC_OC_OCR_MODE_GRAB_ENABLE__M, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Disable MB grabber in the FEC OC */ - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_OCR_MODE__A, 0x0, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_OCR_MODE__A, 0x0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* read data */ - rc = DRXJ_DAP.read_reg32func(dev_addr, FEC_OC_OCR_GRAB_RD1__A, &data, 0); + rc = drxdap_fasi_read_reg32(dev_addr, FEC_OC_OCR_GRAB_RD1__A, &data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -8144,7 +7987,7 @@ ctrl_get_vsb_constel(struct drx_demod_instance *demod, struct drx_complex *compl complex_nr->im = 0; /* Restore MB (Monitor bus) */ - rc = DRXJ_DAP.write_reg16func(dev_addr, VSB_TOP_COMM_MB__A, vsb_top_comm_mb_init, 0); + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_COMM_MB__A, vsb_top_comm_mb_init, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -8191,12 +8034,12 @@ static int power_down_qam(struct drx_demod_instance *demod, bool primary) resets IQM, QAM and FEC HW blocks */ /* stop all comm_exec */ - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP, 0); + rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -8215,7 +8058,7 @@ static int power_down_qam(struct drx_demod_instance *demod, bool primary) } if (primary) { - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -8226,27 +8069,27 @@ static int power_down_qam(struct drx_demod_instance *demod, bool primary) goto rw_error; } } else { - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -8384,34 +8227,34 @@ set_qam_measurement(struct drx_demod_instance *demod, return -EINVAL; } - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_SNC_FAIL_PERIOD__A, (u16)fec_oc_snc_fail_period, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_FAIL_PERIOD__A, (u16)fec_oc_snc_fail_period, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_RS_MEASUREMENT_PERIOD__A, (u16)fec_rs_period, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PERIOD__A, (u16)fec_rs_period, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_RS_MEASUREMENT_PRESCALE__A, fec_rs_prescale, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PRESCALE__A, fec_rs_prescale, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } ext_attr->fec_rs_period = (u16) fec_rs_period; ext_attr->fec_rs_prescale = fec_rs_prescale; - rc = DRXJ_DAP.write_reg32func(dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0, 0); + rc = drxdap_fasi_write_reg32(dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -8458,12 +8301,12 @@ set_qam_measurement(struct drx_demod_instance *demod, /* a(16 bit) * b(16 bit) = 32 bit result => mult32 not needed */ qam_vd_bit_cnt *= qam_vd_period; - rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_VD_MEASUREMENT_PERIOD__A, (u16)qam_vd_period, 0); + rc = drxj_dap_write_reg16(dev_addr, QAM_VD_MEASUREMENT_PERIOD__A, (u16)qam_vd_period, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_VD_MEASUREMENT_PRESCALE__A, qam_vd_prescale, 0); + rc = drxj_dap_write_reg16(dev_addr, QAM_VD_MEASUREMENT_PRESCALE__A, qam_vd_prescale, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -8506,202 +8349,202 @@ static int set_qam16(struct drx_demod_instance *demod) DRXJ_16TO8(13517), /* RAD5 */ }; - rc = DRXJ_DAP.write_block_func(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0); + rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_block_func(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0); + rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 140, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 140, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 50, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 50, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 120, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 120, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 230, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 230, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 95, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 95, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 105, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 105, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 16, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 16, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 220, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 220, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 25, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 25, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 6, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 6, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-24), 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-24), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-65), 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-65), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-127), 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-127), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 50, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 50, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 240, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 240, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 40960, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 40960, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -8741,202 +8584,202 @@ static int set_qam32(struct drx_demod_instance *demod) DRXJ_16TO8(6707), /* RAD5 */ }; - rc = DRXJ_DAP.write_block_func(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0); + rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_block_func(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0); + rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 90, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 90, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 50, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 50, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 170, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 170, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 100, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 100, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 140, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 140, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16)(-8), 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16)(-8), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16)(-16), 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16)(-16), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-26), 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-26), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-56), 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-56), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-86), 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-86), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 50, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 50, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 176, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 176, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 8, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 8, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 20480, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 20480, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -8976,202 +8819,202 @@ static int set_qam64(struct drx_demod_instance *demod) DRXJ_16TO8(15609), /* RAD5 */ }; - rc = DRXJ_DAP.write_block_func(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0); + rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_block_func(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0); + rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 105, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 105, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 195, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 195, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 84, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 84, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 141, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 141, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 7, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 7, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-15), 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-15), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-45), 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-45), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-80), 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-80), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 15, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 15, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 160, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 160, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 43008, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 43008, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -9211,202 +9054,202 @@ static int set_qam128(struct drx_demod_instance *demod) DRXJ_16TO8(7238), /* RAD5 */ }; - rc = DRXJ_DAP.write_block_func(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0); + rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_block_func(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0); + rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 50, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 50, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 140, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 140, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 100, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 100, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 65, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 65, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 5, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 5, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 3, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 3, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-1), 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-1), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 12, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 12, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-23), 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-23), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 144, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 144, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 20992, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 20992, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -9446,202 +9289,202 @@ static int set_qam256(struct drx_demod_instance *demod) DRXJ_16TO8(15356), /* RAD5 */ }; - rc = DRXJ_DAP.write_block_func(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0); + rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_block_func(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0); + rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 50, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 50, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 150, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 150, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 110, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 110, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 16, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 16, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 74, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 74, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 18, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 18, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 13, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 13, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, 7, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, 7, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-8), 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-8), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 25, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 25, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 80, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 80, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 43520, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 43520, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -9875,37 +9718,37 @@ set_qam(struct drx_demod_instance *demod, resets SCU variables */ /* stop all comm_exec */ - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP, 0); + rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -9954,7 +9797,7 @@ set_qam(struct drx_demod_instance *demod, goto rw_error; } /* set symbol rate */ - rc = DRXJ_DAP.write_reg32func(dev_addr, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate, 0); + rc = drxdap_fasi_write_reg32(dev_addr, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -9980,12 +9823,12 @@ set_qam(struct drx_demod_instance *demod, if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) { - rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_SYMBOL_FREQ__A, lc_symbol_freq, 0); + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_SYMBOL_FREQ__A, lc_symbol_freq, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RC_STRETCH__A, iqm_rc_stretch, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_RC_STRETCH__A, iqm_rc_stretch, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -9994,98 +9837,98 @@ set_qam(struct drx_demod_instance *demod, if (op & QAM_SET_OP_ALL) { if (!ext_attr->has_lna) { - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_AMUX__A, 0x02, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AMUX__A, 0x02, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_SYMMETRIC__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SYMMETRIC__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_MIDTAP__A, 3, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, 3, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_QAM__M, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_QAM__M, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_WR_RSV_0__A, 0x5f, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_WR_RSV_0__A, 0x5f, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* scu temporary shut down agc */ - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_SYNC_SEL__A, 3, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SYNC_SEL__A, 3, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_CLP_LEN__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_LEN__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_CLP_TH__A, 448, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_TH__A, 448, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_SNS_LEN__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SNS_LEN__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_PDREF__A, 4, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PDREF__A, 4, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_STDBY__A, 0x10, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, 0x10, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_PGA_GAIN__A, 11, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PGA_GAIN__A, 11, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_POW_MEAS_LEN__A, 1, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 1, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /*! reset default val ! */ - rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE, 0); + rc = drxj_dap_write_reg16(dev_addr, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /*! reset default val ! */ if (ext_attr->standard == DRX_STANDARD_ITU_B) { - rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_SY_SYNC_LWM__A, QAM_SY_SYNC_LWM__PRE, 0); + rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, QAM_SY_SYNC_LWM__PRE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /*! reset default val ! */ - rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_SY_SYNC_AWM__A, QAM_SY_SYNC_AWM__PRE, 0); + rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, QAM_SY_SYNC_AWM__PRE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /*! reset default val ! */ - rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE, 0); + rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -10095,17 +9938,17 @@ set_qam(struct drx_demod_instance *demod, case DRX_CONSTELLATION_QAM16: case DRX_CONSTELLATION_QAM64: case DRX_CONSTELLATION_QAM256: - rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_SY_SYNC_LWM__A, 0x03, 0); + rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, 0x03, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_SY_SYNC_AWM__A, 0x04, 0); + rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, 0x04, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE, 0); + rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -10113,17 +9956,17 @@ set_qam(struct drx_demod_instance *demod, break; case DRX_CONSTELLATION_QAM32: case DRX_CONSTELLATION_QAM128: - rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_SY_SYNC_LWM__A, 0x03, 0); + rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, 0x03, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_SY_SYNC_AWM__A, 0x05, 0); + rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, 0x05, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_SY_SYNC_HWM__A, 0x06, 0); + rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, 0x06, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -10134,128 +9977,128 @@ set_qam(struct drx_demod_instance *demod, } /* switch */ } - rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_MODE__A, QAM_LC_MODE__PRE, 0); + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_MODE__A, QAM_LC_MODE__PRE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /*! reset default val ! */ - rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_RATE_LIMIT__A, 3, 0); + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_RATE_LIMIT__A, 3, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_LPF_FACTORP__A, 4, 0); + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_LPF_FACTORP__A, 4, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_LPF_FACTORI__A, 4, 0); + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_LPF_FACTORI__A, 4, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_MODE__A, 7, 0); + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_MODE__A, 7, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_QUAL_TAB0__A, 1, 0); + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB0__A, 1, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_QUAL_TAB1__A, 1, 0); + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB1__A, 1, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_QUAL_TAB2__A, 1, 0); + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB2__A, 1, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_QUAL_TAB3__A, 1, 0); + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB3__A, 1, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_QUAL_TAB4__A, 2, 0); + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB4__A, 2, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_QUAL_TAB5__A, 2, 0); + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB5__A, 2, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_QUAL_TAB6__A, 2, 0); + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB6__A, 2, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_QUAL_TAB8__A, 2, 0); + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB8__A, 2, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_QUAL_TAB9__A, 2, 0); + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB9__A, 2, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_QUAL_TAB10__A, 2, 0); + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB10__A, 2, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_QUAL_TAB12__A, 2, 0); + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB12__A, 2, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_QUAL_TAB15__A, 3, 0); + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB15__A, 3, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_QUAL_TAB16__A, 3, 0); + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB16__A, 3, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_QUAL_TAB20__A, 4, 0); + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB20__A, 4, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_QUAL_TAB25__A, 4, 0); + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB25__A, 4, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_FS_ADJ_SEL__A, 1, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_FS_ADJ_SEL__A, 1, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RC_ADJ_SEL__A, 1, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_RC_ADJ_SEL__A, 1, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_ADJ_SEL__A, 1, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_ADJ_SEL__A, 1, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_POW_MEAS_LEN__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_GPIO__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_GPIO__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -10311,12 +10154,12 @@ set_qam(struct drx_demod_instance *demod, if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) { if (ext_attr->standard == DRX_STANDARD_ITU_A) { - rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_a_taps), ((u8 *)qam_a_taps), 0); + rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_a_taps), ((u8 *)qam_a_taps), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_a_taps), ((u8 *)qam_a_taps), 0); + rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_a_taps), ((u8 *)qam_a_taps), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -10324,24 +10167,24 @@ set_qam(struct drx_demod_instance *demod, } else if (ext_attr->standard == DRX_STANDARD_ITU_B) { switch (channel->constellation) { case DRX_CONSTELLATION_QAM64: - rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_b64_taps), ((u8 *)qam_b64_taps), 0); + rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_b64_taps), ((u8 *)qam_b64_taps), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_b64_taps), ((u8 *)qam_b64_taps), 0); + rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_b64_taps), ((u8 *)qam_b64_taps), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } break; case DRX_CONSTELLATION_QAM256: - rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_b256_taps), ((u8 *)qam_b256_taps), 0); + rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_b256_taps), ((u8 *)qam_b256_taps), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_b256_taps), ((u8 *)qam_b256_taps), 0); + rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_b256_taps), ((u8 *)qam_b256_taps), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -10351,12 +10194,12 @@ set_qam(struct drx_demod_instance *demod, return -EIO; } } else if (ext_attr->standard == DRX_STANDARD_ITU_C) { - rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_c_taps), ((u8 *)qam_c_taps), 0); + rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_c_taps), ((u8 *)qam_c_taps), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_c_taps), ((u8 *)qam_c_taps), 0); + rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_c_taps), ((u8 *)qam_c_taps), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -10406,7 +10249,7 @@ set_qam(struct drx_demod_instance *demod, } if ((op & QAM_SET_OP_ALL)) { - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_SCALE_SH__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -10470,17 +10313,17 @@ set_qam(struct drx_demod_instance *demod, } } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE, 0); + rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -10512,24 +10355,24 @@ static int qam_flip_spec(struct drx_demod_instance *demod, struct drx_channel *c ext_attr = (struct drxj_data *) demod->my_ext_attr; /* Silence the controlling of lc, equ, and the acquisition state machine */ - rc = DRXJ_DAP.read_reg16func(dev_addr, SCU_RAM_QAM_CTL_ENA__A, &qam_ctl_ena, 0); + rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, &qam_ctl_ena, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_CTL_ENA__A, qam_ctl_ena & ~(SCU_RAM_QAM_CTL_ENA_ACQ__M | SCU_RAM_QAM_CTL_ENA_EQU__M | SCU_RAM_QAM_CTL_ENA_LC__M), 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, qam_ctl_ena & ~(SCU_RAM_QAM_CTL_ENA_ACQ__M | SCU_RAM_QAM_CTL_ENA_EQU__M | SCU_RAM_QAM_CTL_ENA_LC__M), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* freeze the frequency control loop */ - rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_CF__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CF__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_CF1__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CF1__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -10550,42 +10393,42 @@ static int qam_flip_spec(struct drx_demod_instance *demod, struct drx_channel *c iqm_fs_rate_ofs -= 2 * ofsofs; /* freeze dq/fq updating */ - rc = DRXJ_DAP.read_reg16func(dev_addr, QAM_DQ_MODE__A, &data, 0); + rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_MODE__A, &data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } data = (data & 0xfff9); - rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_DQ_MODE__A, data, 0); + rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_FQ_MODE__A, data, 0); + rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* lc_cp / _ci / _ca */ - rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_CI__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CI__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_LC_EP__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_EP__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_FQ_LA_FACTOR__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_LA_FACTOR__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* flip the spec */ - rc = DRXJ_DAP.write_reg32func(dev_addr, IQM_FS_RATE_OFS_LO__A, iqm_fs_rate_ofs, 0); + rc = drxdap_fasi_write_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, iqm_fs_rate_ofs, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -10594,31 +10437,31 @@ static int qam_flip_spec(struct drx_demod_instance *demod, struct drx_channel *c ext_attr->pos_image = (ext_attr->pos_image) ? false : true; /* freeze dq/fq updating */ - rc = DRXJ_DAP.read_reg16func(dev_addr, QAM_DQ_MODE__A, &data, 0); + rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_MODE__A, &data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } equ_mode = data; data = (data & 0xfff9); - rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_DQ_MODE__A, data, 0); + rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_FQ_MODE__A, data, 0); + rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } for (i = 0; i < 28; i++) { - rc = DRXJ_DAP.read_reg16func(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), &data, 0); + rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), &data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), -data, 0); + rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), -data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -10626,12 +10469,12 @@ static int qam_flip_spec(struct drx_demod_instance *demod, struct drx_channel *c } for (i = 0; i < 24; i++) { - rc = DRXJ_DAP.read_reg16func(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), &data, 0); + rc = drxj_dap_read_reg16(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), &data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), -data, 0); + rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), -data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -10639,18 +10482,18 @@ static int qam_flip_spec(struct drx_demod_instance *demod, struct drx_channel *c } data = equ_mode; - rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_DQ_MODE__A, data, 0); + rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_FQ_MODE__A, data, 0); + rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_FSM_STATE_TGT__A, 4, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_STATE_TGT__A, 4, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -10658,13 +10501,13 @@ static int qam_flip_spec(struct drx_demod_instance *demod, struct drx_channel *c i = 0; while ((fsm_state != 4) && (i++ < 100)) { - rc = DRXJ_DAP.read_reg16func(dev_addr, SCU_RAM_QAM_FSM_STATE__A, &fsm_state, 0); + rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_QAM_FSM_STATE__A, &fsm_state, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_QAM_CTL_ENA__A, (qam_ctl_ena | 0x0016), 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, (qam_ctl_ena | 0x0016), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -10735,12 +10578,12 @@ qam64auto(struct drx_demod_instance *demod, if ((*lock_status == DRXJ_DEMOD_LOCK) && /* still demod_lock in 150ms */ ((jiffies_to_msecs(jiffies) - d_locked_time) > DRXJ_QAM_FEC_LOCK_WAITTIME)) { - rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0); + rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0); + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -10753,12 +10596,12 @@ qam64auto(struct drx_demod_instance *demod, if (*lock_status == DRXJ_DEMOD_LOCK) { if (channel->mirror == DRX_MIRROR_AUTO) { /* flip sync pattern back */ - rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0); + rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data & 0xFFFE, 0); + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data & 0xFFFE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -10793,12 +10636,12 @@ qam64auto(struct drx_demod_instance *demod, goto rw_error; } if (sig_quality.MER > 208) { - rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0); + rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0); + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -11002,21 +10845,21 @@ set_qam_channel(struct drx_demod_instance *demod, else ext_attr->mirror = channel->mirror; - rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, + rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SCU_RAM_QAM_CTL_ENA__A, &qam_ctl_ena, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SCU_RAM_QAM_CTL_ENA__A, qam_ctl_ena & ~SCU_RAM_QAM_CTL_ENA_ACQ__M, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SCU_RAM_QAM_FSM_STATE_TGT__A, 0x2, 0); if (rc != 0) { @@ -11030,7 +10873,7 @@ set_qam_channel(struct drx_demod_instance *demod, pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SCU_RAM_QAM_CTL_ENA__A, qam_ctl_ena, 0); if (rc != 0) { @@ -11057,21 +10900,21 @@ set_qam_channel(struct drx_demod_instance *demod, ext_attr->mirror = DRX_MIRROR_NO; else ext_attr->mirror = channel->mirror; - rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, + rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SCU_RAM_QAM_CTL_ENA__A, &qam_ctl_ena, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SCU_RAM_QAM_CTL_ENA__A, qam_ctl_ena & ~SCU_RAM_QAM_CTL_ENA_ACQ__M, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SCU_RAM_QAM_FSM_STATE_TGT__A, 0x2, 0); if (rc != 0) { @@ -11085,7 +10928,7 @@ set_qam_channel(struct drx_demod_instance *demod, pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(demod->my_i2c_dev_addr, + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SCU_RAM_QAM_CTL_ENA__A, qam_ctl_ena, 0); if (rc != 0) { @@ -11140,31 +10983,31 @@ get_qamrs_err_count(struct i2c_device_addr *dev_addr, struct drxjrs_errors *rs_e /* all reported errors are received in the */ /* most recently finished measurment period */ /* no of pre RS bit errors */ - rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_RS_NR_BIT_ERRORS__A, &nr_bit_errors, 0); + rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_BIT_ERRORS__A, &nr_bit_errors, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* no of symbol errors */ - rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_RS_NR_SYMBOL_ERRORS__A, &nr_symbol_errors, 0); + rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_SYMBOL_ERRORS__A, &nr_symbol_errors, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* no of packet errors */ - rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_RS_NR_PACKET_ERRORS__A, &nr_packet_errors, 0); + rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_PACKET_ERRORS__A, &nr_packet_errors, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* no of failures to decode */ - rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_RS_NR_FAILURES__A, &nr_failures, 0); + rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_FAILURES__A, &nr_failures, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* no of post RS bit erros */ - rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_OC_SNC_FAIL_COUNT__A, &nr_snc_par_fail_count, 0); + rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_FAIL_COUNT__A, &nr_snc_par_fail_count, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -11245,13 +11088,13 @@ ctrl_get_qam_sig_quality(struct drx_demod_instance *demod, struct drx_sig_qualit goto rw_error; } /* get the register value needed for MER */ - rc = DRXJ_DAP.read_reg16func(dev_addr, QAM_SL_ERR_POWER__A, &qam_sl_err_power, 0); + rc = drxj_dap_read_reg16(dev_addr, QAM_SL_ERR_POWER__A, &qam_sl_err_power, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* get the register value needed for post RS BER */ - rc = DRXJ_DAP.read_reg16func(dev_addr, FEC_OC_SNC_FAIL_PERIOD__A, &fec_oc_period, 0); + rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_FAIL_PERIOD__A, &fec_oc_period, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -11304,7 +11147,7 @@ ctrl_get_qam_sig_quality(struct drx_demod_instance *demod, struct drx_sig_qualit /* get the register value */ /* no of quadrature symbol errors */ - rc = DRXJ_DAP.read_reg16func(dev_addr, QAM_VD_NR_QSYM_ERRORS__A, &qsym_err_vd, 0); + rc = drxj_dap_read_reg16(dev_addr, QAM_VD_NR_QSYM_ERRORS__A, &qsym_err_vd, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -11419,7 +11262,7 @@ ctrl_get_qam_constel(struct drx_demod_instance *demod, struct drx_complex *compl /* Needs to be checked when external interface PG is updated */ /* Configure MB (Monitor bus) */ - rc = DRXJ_DAP.read_reg16func(dev_addr, QAM_SL_COMM_MB__A, &qam_sl_comm_mb_init, 0); + rc = drxj_dap_read_reg16(dev_addr, QAM_SL_COMM_MB__A, &qam_sl_comm_mb_init, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -11429,7 +11272,7 @@ ctrl_get_qam_constel(struct drx_demod_instance *demod, struct drx_complex *compl QAM_SL_COMM_MB_MUX_OBS__M)); qam_sl_comm_mb |= (QAM_SL_COMM_MB_OBS_ON + QAM_SL_COMM_MB_MUX_OBS_CONST_CORR); - rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_SL_COMM_MB__A, qam_sl_comm_mb, 0); + rc = drxj_dap_write_reg16(dev_addr, QAM_SL_COMM_MB__A, qam_sl_comm_mb, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -11448,21 +11291,21 @@ ctrl_get_qam_constel(struct drx_demod_instance *demod, struct drx_complex *compl /* grabber mode: continuous */ (FEC_OC_OCR_MODE_GRAB_COUNTED__M & (0x0 << FEC_OC_OCR_MODE_GRAB_COUNTED__B))); - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_OCR_MODE__A, fec_oc_ocr_mode, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_OCR_MODE__A, fec_oc_ocr_mode, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Disable MB grabber in the FEC OC */ - rc = DRXJ_DAP.write_reg16func(dev_addr, FEC_OC_OCR_MODE__A, 0x00, 0); + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_OCR_MODE__A, 0x00, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* read data */ - rc = DRXJ_DAP.read_reg32func(dev_addr, FEC_OC_OCR_GRAB_RD0__A, &data, 0); + rc = drxdap_fasi_read_reg32(dev_addr, FEC_OC_OCR_GRAB_RD0__A, &data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -11482,7 +11325,7 @@ ctrl_get_qam_constel(struct drx_demod_instance *demod, struct drx_complex *compl complex_nr->im = ((s16) im); /* Restore MB (Monitor bus) */ - rc = DRXJ_DAP.write_reg16func(dev_addr, QAM_SL_COMM_MB__A, qam_sl_comm_mb_init, 0); + rc = drxj_dap_write_reg16(dev_addr, QAM_SL_COMM_MB__A, qam_sl_comm_mb_init, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -11631,22 +11474,22 @@ atv_update_config(struct drx_demod_instance *demod, bool force_update) pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_EQU0__A, ext_attr->atv_top_equ0[index], 0); + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_EQU0__A, ext_attr->atv_top_equ0[index], 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_EQU1__A, ext_attr->atv_top_equ1[index], 0); + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_EQU1__A, ext_attr->atv_top_equ1[index], 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_EQU2__A, ext_attr->atv_top_equ2[index], 0); + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_EQU2__A, ext_attr->atv_top_equ2[index], 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_EQU3__A, ext_attr->atv_top_equ3[index], 0); + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_EQU3__A, ext_attr->atv_top_equ3[index], 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -11657,7 +11500,7 @@ atv_update_config(struct drx_demod_instance *demod, bool force_update) if (force_update) { u16 data = 0; - rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_RT_ROT_BP__A, &data, 0); + rc = drxj_dap_read_reg16(dev_addr, IQM_RT_ROT_BP__A, &data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -11667,7 +11510,7 @@ atv_update_config(struct drx_demod_instance *demod, bool force_update) data |= IQM_RT_ROT_BP_ROT_OFF_OFF; else data |= IQM_RT_ROT_BP_ROT_OFF_ACTIVE; - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_ROT_BP__A, data, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_RT_ROT_BP__A, data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -11677,7 +11520,7 @@ atv_update_config(struct drx_demod_instance *demod, bool force_update) /* peak filter setting */ if (force_update || ((ext_attr->atv_cfg_changed_flags & DRXJ_ATV_CHANGED_PEAK_FLT) != 0)) { - rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_VID_PEAK__A, ext_attr->atv_top_vid_peak, 0); + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_VID_PEAK__A, ext_attr->atv_top_vid_peak, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -11687,7 +11530,7 @@ atv_update_config(struct drx_demod_instance *demod, bool force_update) /* noise filter setting */ if (force_update || ((ext_attr->atv_cfg_changed_flags & DRXJ_ATV_CHANGED_NOISE_FLT) != 0)) { - rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_NOISE_TH__A, ext_attr->atv_top_noise_th, 0); + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_NOISE_TH__A, ext_attr->atv_top_noise_th, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -11716,7 +11559,7 @@ atv_update_config(struct drx_demod_instance *demod, bool force_update) return -EIO; break; } - rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_AF_SIF_ATT__A, attenuation, 0); + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_AF_SIF_ATT__A, attenuation, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -11728,7 +11571,7 @@ atv_update_config(struct drx_demod_instance *demod, bool force_update) ((ext_attr->atv_cfg_changed_flags & DRXJ_ATV_CHANGED_OUTPUT) != 0)) { u16 data = 0; - rc = DRXJ_DAP.read_reg16func(dev_addr, ATV_TOP_STDBY__A, &data, 0); + rc = drxj_dap_read_reg16(dev_addr, ATV_TOP_STDBY__A, &data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -11742,7 +11585,7 @@ atv_update_config(struct drx_demod_instance *demod, bool force_update) data &= (~ATV_TOP_STDBY_SIF_STDBY_STANDBY); else data |= ATV_TOP_STDBY_SIF_STDBY_STANDBY; - rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_STDBY__A, data, 0); + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STDBY__A, data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -12016,7 +11859,7 @@ ctrl_get_cfg_atv_output(struct drx_demod_instance *demod, struct drxj_cfg_atv_ou if (output_cfg == NULL) return -EINVAL; - rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, ATV_TOP_STDBY__A, &data, 0); + rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, ATV_TOP_STDBY__A, &data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -12030,7 +11873,7 @@ ctrl_get_cfg_atv_output(struct drx_demod_instance *demod, struct drxj_cfg_atv_ou output_cfg->enable_sif_output = false; } else { output_cfg->enable_sif_output = true; - rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, ATV_TOP_AF_SIF_ATT__A, &data, 0); + rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, ATV_TOP_AF_SIF_ATT__A, &data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -12073,7 +11916,7 @@ ctrl_get_cfg_atv_agc_status(struct drx_demod_instance *demod, IQM_AF_AGC_RF__A * 27 is 20 bits worst case. */ - rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_AGC_RF__A, &data, 0); + rc = drxj_dap_read_reg16(dev_addr, IQM_AF_AGC_RF__A, &data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -12090,7 +11933,7 @@ ctrl_get_cfg_atv_agc_status(struct drx_demod_instance *demod, IQM_AF_AGC_IF__A * 27 is 20 bits worst case. */ - rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_AGC_IF__A, &data, 0); + rc = drxj_dap_read_reg16(dev_addr, IQM_AF_AGC_IF__A, &data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -12177,7 +12020,7 @@ static int power_up_atv(struct drx_demod_instance *demod, enum drx_standard stan int rc; /* ATV NTSC */ - rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_ACTIVE, 0); + rc = drxj_dap_write_reg16(dev_addr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_ACTIVE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -12194,7 +12037,7 @@ static int power_up_atv(struct drx_demod_instance *demod, enum drx_standard stan goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -12249,19 +12092,19 @@ power_down_atv(struct drx_demod_instance *demod, enum drx_standard standard, boo goto rw_error; } /* Disable ATV outputs (ATV reset enables CVBS, undo this) */ - rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_STDBY__A, (ATV_TOP_STDBY_SIF_STDBY_STANDBY & (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE)), 0); + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STDBY__A, (ATV_TOP_STDBY_SIF_STDBY_STANDBY & (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE)), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_STOP, 0); + rc = drxj_dap_write_reg16(dev_addr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } if (primary) { - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -12272,27 +12115,27 @@ power_down_atv(struct drx_demod_instance *demod, enum drx_standard standard, boo goto rw_error; } } else { - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -12598,32 +12441,32 @@ trouble ? ext_attr = (struct drxj_data *) demod->my_ext_attr; dev_addr = demod->my_i2c_dev_addr; - rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_STOP, 0); + rc = drxj_dap_write_reg16(dev_addr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -12641,7 +12484,7 @@ trouble ? goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_MOD_CONTROL__A, ATV_TOP_MOD_CONTROL__PRE, 0); + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_MOD_CONTROL__A, ATV_TOP_MOD_CONTROL__PRE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -12653,69 +12496,69 @@ trouble ? /* NTSC */ cmd_param = SCU_RAM_ATV_STANDARD_STANDARD_MN; - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_LO_INCR__A, IQM_RT_LO_INCR_MN, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_RT_LO_INCR__A, IQM_RT_LO_INCR_MN, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(ntsc_taps_re), ((u8 *)ntsc_taps_re), 0); + rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(ntsc_taps_re), ((u8 *)ntsc_taps_re), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(ntsc_taps_im), ((u8 *)ntsc_taps_im), 0); + rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(ntsc_taps_im), ((u8 *)ntsc_taps_im), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_AMP_TH__A, ATV_TOP_CR_AMP_TH_MN, 0); + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_CR_AMP_TH__A, ATV_TOP_CR_AMP_TH_MN, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_CONT__A, (ATV_TOP_CR_CONT_CR_P_MN | ATV_TOP_CR_CONT_CR_D_MN | ATV_TOP_CR_CONT_CR_I_MN), 0); + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_CR_CONT__A, (ATV_TOP_CR_CONT_CR_P_MN | ATV_TOP_CR_CONT_CR_D_MN | ATV_TOP_CR_CONT_CR_I_MN), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_MN, 0); + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_MN, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_MN | ATV_TOP_STD_VID_POL_MN), 0); + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_MN | ATV_TOP_STD_VID_POL_MN), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_MN, 0); + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_MN, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM | SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE), 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM | SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_BG_MN, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_BG_MN, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -12727,48 +12570,48 @@ trouble ? /* FM */ cmd_param = SCU_RAM_ATV_STANDARD_STANDARD_FM; - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_LO_INCR__A, 2994, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_RT_LO_INCR__A, 2994, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_MIDTAP__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(fm_taps_re), ((u8 *)fm_taps_re), 0); + rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(fm_taps_re), ((u8 *)fm_taps_re), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(fm_taps_im), ((u8 *)fm_taps_im), 0); + rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(fm_taps_im), ((u8 *)fm_taps_im), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_FM | ATV_TOP_STD_VID_POL_FM), 0); + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_FM | ATV_TOP_STD_VID_POL_FM), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_MOD_CONTROL__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_MOD_CONTROL__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_CONT__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_CR_CONT__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW | SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM), 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW | SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_ROT_BP__A, IQM_RT_ROT_BP_ROT_OFF_OFF, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_RT_ROT_BP__A, IQM_RT_ROT_BP_ROT_OFF_OFF, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -12780,67 +12623,67 @@ trouble ? /* PAL/SECAM B/G */ cmd_param = SCU_RAM_ATV_STANDARD_STANDARD_B; - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_LO_INCR__A, 1820, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_RT_LO_INCR__A, 1820, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* TODO check with IS */ - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(bg_taps_re), ((u8 *)bg_taps_re), 0); + rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(bg_taps_re), ((u8 *)bg_taps_re), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(bg_taps_im), ((u8 *)bg_taps_im), 0); + rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(bg_taps_im), ((u8 *)bg_taps_im), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_BG, 0); + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_BG, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_AMP_TH__A, ATV_TOP_CR_AMP_TH_BG, 0); + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_CR_AMP_TH__A, ATV_TOP_CR_AMP_TH_BG, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_CONT__A, (ATV_TOP_CR_CONT_CR_P_BG | ATV_TOP_CR_CONT_CR_D_BG | ATV_TOP_CR_CONT_CR_I_BG), 0); + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_CR_CONT__A, (ATV_TOP_CR_CONT_CR_P_BG | ATV_TOP_CR_CONT_CR_D_BG | ATV_TOP_CR_CONT_CR_I_BG), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_BG, 0); + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_BG, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_BG | ATV_TOP_STD_VID_POL_BG), 0); + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_BG | ATV_TOP_STD_VID_POL_BG), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM | SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE), 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM | SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_BG_MN, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_BG_MN, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -12853,67 +12696,67 @@ trouble ? /* PAL/SECAM D/K */ cmd_param = SCU_RAM_ATV_STANDARD_STANDARD_DK; - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_LO_INCR__A, 2225, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_RT_LO_INCR__A, 2225, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* TODO check with IS */ - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(dk_i_l_lp_taps_re), ((u8 *)dk_i_l_lp_taps_re), 0); + rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(dk_i_l_lp_taps_re), ((u8 *)dk_i_l_lp_taps_re), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(dk_i_l_lp_taps_im), ((u8 *)dk_i_l_lp_taps_im), 0); + rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(dk_i_l_lp_taps_im), ((u8 *)dk_i_l_lp_taps_im), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_AMP_TH__A, ATV_TOP_CR_AMP_TH_DK, 0); + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_CR_AMP_TH__A, ATV_TOP_CR_AMP_TH_DK, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_DK, 0); + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_DK, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_CONT__A, (ATV_TOP_CR_CONT_CR_P_DK | ATV_TOP_CR_CONT_CR_D_DK | ATV_TOP_CR_CONT_CR_I_DK), 0); + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_CR_CONT__A, (ATV_TOP_CR_CONT_CR_P_DK | ATV_TOP_CR_CONT_CR_D_DK | ATV_TOP_CR_CONT_CR_I_DK), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_DK, 0); + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_DK, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_DK | ATV_TOP_STD_VID_POL_DK), 0); + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_DK | ATV_TOP_STD_VID_POL_DK), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM | SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE), 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM | SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_DK, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_DK, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -12926,67 +12769,67 @@ trouble ? /* PAL/SECAM I */ cmd_param = SCU_RAM_ATV_STANDARD_STANDARD_I; - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_LO_INCR__A, 2225, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_RT_LO_INCR__A, 2225, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* TODO check with IS */ - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(dk_i_l_lp_taps_re), ((u8 *)dk_i_l_lp_taps_re), 0); + rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(dk_i_l_lp_taps_re), ((u8 *)dk_i_l_lp_taps_re), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(dk_i_l_lp_taps_im), ((u8 *)dk_i_l_lp_taps_im), 0); + rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(dk_i_l_lp_taps_im), ((u8 *)dk_i_l_lp_taps_im), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_AMP_TH__A, ATV_TOP_CR_AMP_TH_I, 0); + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_CR_AMP_TH__A, ATV_TOP_CR_AMP_TH_I, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_I, 0); + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_I, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_CONT__A, (ATV_TOP_CR_CONT_CR_P_I | ATV_TOP_CR_CONT_CR_D_I | ATV_TOP_CR_CONT_CR_I_I), 0); + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_CR_CONT__A, (ATV_TOP_CR_CONT_CR_P_I | ATV_TOP_CR_CONT_CR_D_I | ATV_TOP_CR_CONT_CR_I_I), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_I, 0); + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_I, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_I | ATV_TOP_STD_VID_POL_I), 0); + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_I | ATV_TOP_STD_VID_POL_I), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM | SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE), 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM | SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_I, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_I, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -12999,67 +12842,67 @@ trouble ? /* PAL/SECAM L with negative modulation */ cmd_param = SCU_RAM_ATV_STANDARD_STANDARD_L; - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_LO_INCR__A, 2225, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_RT_LO_INCR__A, 2225, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* TODO check with IS */ - rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_L, 0); + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_L, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(dk_i_l_lp_taps_re), ((u8 *)dk_i_l_lp_taps_re), 0); + rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(dk_i_l_lp_taps_re), ((u8 *)dk_i_l_lp_taps_re), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(dk_i_l_lp_taps_im), ((u8 *)dk_i_l_lp_taps_im), 0); + rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(dk_i_l_lp_taps_im), ((u8 *)dk_i_l_lp_taps_im), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_AMP_TH__A, 0x2, 0); + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_CR_AMP_TH__A, 0x2, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* TODO check with IS */ - rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_CONT__A, (ATV_TOP_CR_CONT_CR_P_L | ATV_TOP_CR_CONT_CR_D_L | ATV_TOP_CR_CONT_CR_I_L), 0); + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_CR_CONT__A, (ATV_TOP_CR_CONT_CR_P_L | ATV_TOP_CR_CONT_CR_D_L | ATV_TOP_CR_CONT_CR_I_L), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_L, 0); + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_L, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_L | ATV_TOP_STD_VID_POL_L), 0); + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_L | ATV_TOP_STD_VID_POL_L), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_AM | SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_ENABLE | SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW), 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_AM | SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_ENABLE | SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_LLP, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_LLP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -13073,67 +12916,67 @@ trouble ? /* PAL/SECAM L with positive modulation */ cmd_param = SCU_RAM_ATV_STANDARD_STANDARD_LP; - rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_LP, 0); + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_LP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_LO_INCR__A, 2225, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_RT_LO_INCR__A, 2225, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* TODO check with IS */ - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_RE0__A, sizeof(dk_i_l_lp_taps_re), ((u8 *)dk_i_l_lp_taps_re), 0); + rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(dk_i_l_lp_taps_re), ((u8 *)dk_i_l_lp_taps_re), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_block_func(dev_addr, IQM_CF_TAP_IM0__A, sizeof(dk_i_l_lp_taps_im), ((u8 *)dk_i_l_lp_taps_im), 0); + rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(dk_i_l_lp_taps_im), ((u8 *)dk_i_l_lp_taps_im), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_AMP_TH__A, 0x2, 0); + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_CR_AMP_TH__A, 0x2, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* TODO check with IS */ - rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_CONT__A, (ATV_TOP_CR_CONT_CR_P_LP | ATV_TOP_CR_CONT_CR_D_LP | ATV_TOP_CR_CONT_CR_I_LP), 0); + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_CR_CONT__A, (ATV_TOP_CR_CONT_CR_P_LP | ATV_TOP_CR_CONT_CR_D_LP | ATV_TOP_CR_CONT_CR_I_LP), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_LP, 0); + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_LP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_LP | ATV_TOP_STD_VID_POL_LP), 0); + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_LP | ATV_TOP_STD_VID_POL_LP), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_AM | SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_ENABLE | SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW), 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_AM | SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_ENABLE | SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_LLP, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_LLP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -13149,29 +12992,29 @@ trouble ? /* Common initializations FM & NTSC & B/G & D/K & I & L & LP */ if (!ext_attr->has_lna) { - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_AMUX__A, 0x01, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AMUX__A, 0x01, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_STANDARD__A, 0x002, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_STANDARD__A, 0x002, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_CLP_LEN__A, IQM_AF_CLP_LEN_ATV, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_LEN__A, IQM_AF_CLP_LEN_ATV, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_CLP_TH__A, IQM_AF_CLP_TH_ATV, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_TH__A, IQM_AF_CLP_TH_ATV, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_SNS_LEN__A, IQM_AF_SNS_LEN_ATV, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SNS_LEN__A, IQM_AF_SNS_LEN_ATV, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -13181,134 +13024,134 @@ trouble ? pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_AGC_IF__A, 10248, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AGC_IF__A, 10248, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } ext_attr->iqm_rc_rate_ofs = 0x00200000L; - rc = DRXJ_DAP.write_reg32func(dev_addr, IQM_RC_RATE_OFS_LO__A, ext_attr->iqm_rc_rate_ofs, 0); + rc = drxdap_fasi_write_reg32(dev_addr, IQM_RC_RATE_OFS_LO__A, ext_attr->iqm_rc_rate_ofs, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RC_ADJ_SEL__A, IQM_RC_ADJ_SEL_B_OFF, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_RC_ADJ_SEL__A, IQM_RC_ADJ_SEL_B_OFF, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RC_STRETCH__A, IQM_RC_STRETCH_ATV, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_RC_STRETCH__A, IQM_RC_STRETCH_ATV, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_ACTIVE__A, IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_ON | IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_ON, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_RT_ACTIVE__A, IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_ON | IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_ON, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_ATV__M, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_ATV__M, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_CF_SYMMETRIC__A, IQM_CF_SYMMETRIC_IM__M, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SYMMETRIC__A, IQM_CF_SYMMETRIC_IM__M, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* default: SIF in standby */ - rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_SYNC_SLICE__A, ATV_TOP_SYNC_SLICE_MN, 0); + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_SYNC_SLICE__A, ATV_TOP_SYNC_SLICE_MN, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_MOD_ACCU__A, ATV_TOP_MOD_ACCU__PRE, 0); + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_MOD_ACCU__A, ATV_TOP_MOD_ACCU__PRE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_SIF_GAIN__A, 0x080, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_SIF_GAIN__A, 0x080, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_FAGC_TH_RED__A, 10, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_FAGC_TH_RED__A, 10, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AAGC_CNT__A, 7, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_AAGC_CNT__A, 7, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_NAGC_KI_MIN__A, 0x0225, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_NAGC_KI_MIN__A, 0x0225, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_NAGC_KI_MAX__A, 0x0547, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_NAGC_KI_MAX__A, 0x0547, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_KI_CHANGE_TH__A, 20, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_KI_CHANGE_TH__A, 20, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_LOCK__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_LOCK__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_RT_DELAY__A, IQM_RT_DELAY__PRE, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_RT_DELAY__A, IQM_RT_DELAY__PRE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_BPC_KI_MIN__A, 531, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_BPC_KI_MIN__A, 531, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_PAGC_KI_MIN__A, 1061, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_PAGC_KI_MIN__A, 1061, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_BP_REF_MIN__A, 100, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_BP_REF_MIN__A, 100, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_BP_REF_MAX__A, 260, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_BP_REF_MAX__A, 260, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_BP_LVL__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_BP_LVL__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AMS_MAX__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_AMS_MAX__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_AMS_MIN__A, 2047, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_AMS_MIN__A, 2047, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_GPIO__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_GPIO__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -13358,18 +13201,18 @@ trouble ? /* turn the analog work around on/off (must after set_env b/c it is set in mc) */ if (ext_attr->mfx == 0x03) { - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_ENABLE_IIR_WA__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_ENABLE_IIR_WA__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } else { - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_ENABLE_IIR_WA__A, 1, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_ENABLE_IIR_WA__A, 1, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ATV_IIR_CRIT__A, 225, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_IIR_CRIT__A, 225, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -13428,7 +13271,7 @@ set_atv_channel(struct drx_demod_instance *demod, pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_CR_FREQ__A, ATV_TOP_CR_FREQ__PRE, 0); + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_CR_FREQ__A, ATV_TOP_CR_FREQ__PRE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -13493,7 +13336,7 @@ get_atv_channel(struct drx_demod_instance *demod, u16 measured_offset = 0; /* get measured frequency offset */ - rc = DRXJ_DAP.read_reg16func(dev_addr, ATV_TOP_CR_FREQ__A, &measured_offset, 0); + rc = drxj_dap_read_reg16(dev_addr, ATV_TOP_CR_FREQ__A, &measured_offset, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -13510,7 +13353,7 @@ get_atv_channel(struct drx_demod_instance *demod, u16 measured_offset = 0; /* get measured frequency offset */ - rc = DRXJ_DAP.read_reg16func(dev_addr, ATV_TOP_CR_FREQ__A, &measured_offset, 0); + rc = drxj_dap_read_reg16(dev_addr, ATV_TOP_CR_FREQ__A, &measured_offset, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -13620,12 +13463,12 @@ get_atv_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength) return -EIO; break; } - rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_AGC_RF__A, &rf_curr_gain, 0); + rc = drxj_dap_read_reg16(dev_addr, IQM_AF_AGC_RF__A, &rf_curr_gain, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_AF_AGC_IF__A, &if_curr_gain, 0); + rc = drxj_dap_read_reg16(dev_addr, IQM_AF_AGC_IF__A, &if_curr_gain, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -13753,18 +13596,18 @@ static int power_up_aud(struct drx_demod_instance *demod, bool set_standard) dev_addr = demod->my_i2c_dev_addr; - rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_TOP_COMM_EXEC__A, AUD_TOP_COMM_EXEC_ACTIVE, 0); + rc = drxj_dap_write_reg16(dev_addr, AUD_TOP_COMM_EXEC__A, AUD_TOP_COMM_EXEC_ACTIVE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* setup TR interface: R/W mode, fifosize=8 */ - rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_TOP_TR_MDE__A, 8, 0); + rc = drxj_dap_write_reg16(dev_addr, AUD_TOP_TR_MDE__A, 8, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_COMM_EXEC__A, AUD_COMM_EXEC_ACTIVE, 0); + rc = drxj_dap_write_reg16(dev_addr, AUD_COMM_EXEC__A, AUD_COMM_EXEC_ACTIVE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -13801,7 +13644,7 @@ static int power_down_aud(struct drx_demod_instance *demod) dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; - rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP, 0); + rc = drxj_dap_write_reg16(dev_addr, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -13850,12 +13693,12 @@ static int aud_get_modus(struct drx_demod_instance *demod, u16 *modus) } /* Modus register is combined in to RAM location */ - rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_RAM_MODUS_HI__A, &r_modus_hi, 0); + rc = drxj_dap_read_reg16(dev_addr, AUD_DEM_RAM_MODUS_HI__A, &r_modus_hi, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_RAM_MODUS_LO__A, &r_modus_lo, 0); + rc = drxj_dap_read_reg16(dev_addr, AUD_DEM_RAM_MODUS_LO__A, &r_modus_lo, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -13909,7 +13752,7 @@ aud_ctrl_get_cfg_rds(struct drx_demod_instance *demod, struct drx_cfg_aud_rds *s status->valid = false; - rc = DRXJ_DAP.read_reg16func(addr, AUD_DEM_RD_RDS_ARRAY_CNT__A, &r_rds_array_cnt_init, 0); + rc = drxj_dap_read_reg16(addr, AUD_DEM_RD_RDS_ARRAY_CNT__A, &r_rds_array_cnt_init, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -13933,7 +13776,7 @@ aud_ctrl_get_cfg_rds(struct drx_demod_instance *demod, struct drx_cfg_aud_rds *s /* new data */ /* read the data */ for (rds_data_cnt = 0; rds_data_cnt < AUD_RDS_ARRAY_SIZE; rds_data_cnt++) { - rc = DRXJ_DAP.read_reg16func(addr, AUD_DEM_RD_RDS_DATA__A, &r_rds_data, 0); + rc = drxj_dap_read_reg16(addr, AUD_DEM_RD_RDS_DATA__A, &r_rds_data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -13941,7 +13784,7 @@ aud_ctrl_get_cfg_rds(struct drx_demod_instance *demod, struct drx_cfg_aud_rds *s status->data[rds_data_cnt] = r_rds_data; } - rc = DRXJ_DAP.read_reg16func(addr, AUD_DEM_RD_RDS_ARRAY_CNT__A, &r_rds_array_cnt_check, 0); + rc = drxj_dap_read_reg16(addr, AUD_DEM_RD_RDS_ARRAY_CNT__A, &r_rds_array_cnt_check, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -13997,7 +13840,7 @@ aud_ctrl_get_carrier_detect_status(struct drx_demod_instance *demod, struct drx_ status->stereo = false; /* read stereo sound mode indication */ - rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_RD_STATUS__A, &r_data, 0); + rc = drxj_dap_read_reg16(dev_addr, AUD_DEM_RD_STATUS__A, &r_data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -14072,7 +13915,7 @@ aud_ctrl_get_status(struct drx_demod_instance *demod, struct drx_aud_status *sta status->rds = ext_attr->aud_data.rds_data_present; /* fm_ident */ - rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DSP_RD_FM_IDENT_VALUE__A, &r_data, 0); + rc = drxj_dap_read_reg16(dev_addr, AUD_DSP_RD_FM_IDENT_VALUE__A, &r_data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -14122,7 +13965,7 @@ aud_ctrl_get_cfg_volume(struct drx_demod_instance *demod, struct drx_cfg_aud_vol /* volume */ volume->mute = ext_attr->aud_data.volume.mute; - rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DSP_WR_VOLUME__A, &r_volume, 0); + rc = drxj_dap_read_reg16(dev_addr, AUD_DSP_WR_VOLUME__A, &r_volume, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -14142,7 +13985,7 @@ aud_ctrl_get_cfg_volume(struct drx_demod_instance *demod, struct drx_cfg_aud_vol } /* automatic volume control */ - rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DSP_WR_AVC__A, &r_avc, 0); + rc = drxj_dap_read_reg16(dev_addr, AUD_DSP_WR_AVC__A, &r_avc, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -14213,7 +14056,7 @@ aud_ctrl_get_cfg_volume(struct drx_demod_instance *demod, struct drx_cfg_aud_vol /* QP vaues */ /* left carrier */ - rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DSP_RD_QPEAK_L__A, &r_strength_left, 0); + rc = drxj_dap_read_reg16(dev_addr, AUD_DSP_RD_QPEAK_L__A, &r_strength_left, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -14222,7 +14065,7 @@ aud_ctrl_get_cfg_volume(struct drx_demod_instance *demod, struct drx_cfg_aud_vol AUD_CARRIER_STRENGTH_QP_0DB_LOG10T100) / 5; /* right carrier */ - rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DSP_RD_QPEAK_R__A, &r_strength_right, 0); + rc = drxj_dap_read_reg16(dev_addr, AUD_DSP_RD_QPEAK_R__A, &r_strength_right, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -14274,7 +14117,7 @@ aud_ctrl_set_cfg_volume(struct drx_demod_instance *demod, struct drx_cfg_aud_vol (volume->volume > AUD_VOLUME_DB_MAX)) return -EINVAL; - rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DSP_WR_VOLUME__A, &w_volume, 0); + rc = drxj_dap_read_reg16(dev_addr, AUD_DSP_WR_VOLUME__A, &w_volume, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -14287,14 +14130,14 @@ aud_ctrl_set_cfg_volume(struct drx_demod_instance *demod, struct drx_cfg_aud_vol else w_volume |= (u16)((volume->volume + AUD_VOLUME_ZERO_DB) << AUD_DSP_WR_VOLUME_VOL_MAIN__B); - rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DSP_WR_VOLUME__A, w_volume, 0); + rc = drxj_dap_write_reg16(dev_addr, AUD_DSP_WR_VOLUME__A, w_volume, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* automatic volume control */ - rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DSP_WR_AVC__A, &w_avc, 0); + rc = drxj_dap_read_reg16(dev_addr, AUD_DSP_WR_AVC__A, &w_avc, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -14368,7 +14211,7 @@ aud_ctrl_set_cfg_volume(struct drx_demod_instance *demod, struct drx_cfg_aud_vol w_avc &= (u16) ~AUD_DSP_WR_AVC_AVC_REF_LEV__M; w_avc |= (u16) (volume->avc_ref_level << AUD_DSP_WR_AVC_AVC_REF_LEV__B); - rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DSP_WR_AVC__A, w_avc, 0); + rc = drxj_dap_write_reg16(dev_addr, AUD_DSP_WR_AVC__A, w_avc, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -14414,12 +14257,12 @@ aud_ctrl_get_cfg_output_i2s(struct drx_demod_instance *demod, struct drx_cfg_i2s ext_attr->aud_data.audio_is_active = true; } - rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_RAM_I2S_CONFIG2__A, &w_i2s_config, 0); + rc = drxj_dap_read_reg16(dev_addr, AUD_DEM_RAM_I2S_CONFIG2__A, &w_i2s_config, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DSP_WR_I2S_OUT_FS__A, &r_i2s_freq, 0); + rc = drxj_dap_read_reg16(dev_addr, AUD_DSP_WR_I2S_OUT_FS__A, &r_i2s_freq, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -14527,7 +14370,7 @@ aud_ctrl_set_cfg_output_i2s(struct drx_demod_instance *demod, struct drx_cfg_i2s ext_attr->aud_data.audio_is_active = true; } - rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_RAM_I2S_CONFIG2__A, &w_i2s_config, 0); + rc = drxj_dap_read_reg16(dev_addr, AUD_DEM_RAM_I2S_CONFIG2__A, &w_i2s_config, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -14614,19 +14457,19 @@ aud_ctrl_set_cfg_output_i2s(struct drx_demod_instance *demod, struct drx_cfg_i2s if (output->word_length == DRX_I2S_WORDLENGTH_16) w_i2s_freq *= 2; - rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DEM_WR_I2S_CONFIG2__A, w_i2s_config, 0); + rc = drxj_dap_write_reg16(dev_addr, AUD_DEM_WR_I2S_CONFIG2__A, w_i2s_config, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DSP_WR_I2S_OUT_FS__A, (u16)w_i2s_freq, 0); + rc = drxj_dap_write_reg16(dev_addr, AUD_DSP_WR_I2S_OUT_FS__A, (u16)w_i2s_freq, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* configure I2S output pads for master or slave mode */ - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -14648,23 +14491,23 @@ aud_ctrl_set_cfg_output_i2s(struct drx_demod_instance *demod, struct drx_cfg_i2s SIO_PDR_I2S_WS_CFG_DRIVE__SLAVE; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_I2S_DA_CFG__A, w_i2s_pads_data_da, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_I2S_DA_CFG__A, w_i2s_pads_data_da, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_I2S_CL_CFG__A, w_i2s_pads_data_cl, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_I2S_CL_CFG__A, w_i2s_pads_data_cl, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_I2S_WS_CFG__A, w_i2s_pads_data_ws, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_I2S_WS_CFG__A, w_i2s_pads_data_ws, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -14804,7 +14647,7 @@ aud_ctr_setl_cfg_auto_sound(struct drx_demod_instance *demod, } if (w_modus != r_modus) { - rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DEM_WR_MODUS__A, w_modus, 0); + rc = drxj_dap_write_reg16(dev_addr, AUD_DEM_WR_MODUS__A, w_modus, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -14852,17 +14695,17 @@ aud_ctrl_get_cfg_ass_thres(struct drx_demod_instance *demod, struct drx_cfg_aud_ ext_attr->aud_data.audio_is_active = true; } - rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_RAM_A2_THRSHLD__A, &thres_a2, 0); + rc = drxj_dap_read_reg16(dev_addr, AUD_DEM_RAM_A2_THRSHLD__A, &thres_a2, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_RAM_BTSC_THRSHLD__A, &thres_btsc, 0); + rc = drxj_dap_read_reg16(dev_addr, AUD_DEM_RAM_BTSC_THRSHLD__A, &thres_btsc, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_RAM_NICAM_THRSHLD__A, &thres_nicam, 0); + rc = drxj_dap_read_reg16(dev_addr, AUD_DEM_RAM_NICAM_THRSHLD__A, &thres_nicam, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -14907,17 +14750,17 @@ aud_ctrl_set_cfg_ass_thres(struct drx_demod_instance *demod, struct drx_cfg_aud_ ext_attr->aud_data.audio_is_active = true; } - rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DEM_WR_A2_THRSHLD__A, thres->a2, 0); + rc = drxj_dap_write_reg16(dev_addr, AUD_DEM_WR_A2_THRSHLD__A, thres->a2, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DEM_WR_BTSC_THRSHLD__A, thres->btsc, 0); + rc = drxj_dap_write_reg16(dev_addr, AUD_DEM_WR_BTSC_THRSHLD__A, thres->btsc, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DEM_WR_NICAM_THRSHLD__A, thres->nicam, 0); + rc = drxj_dap_write_reg16(dev_addr, AUD_DEM_WR_NICAM_THRSHLD__A, thres->nicam, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -15009,22 +14852,22 @@ aud_ctrl_get_cfg_carrier(struct drx_demod_instance *demod, struct drx_cfg_aud_ca } /* frequency adjustment for primary & secondary audio channel */ - rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_RAM_DCO_A_HI__A, &dco_a_hi, 0); + rc = drxj_dap_read_reg16(dev_addr, AUD_DEM_RAM_DCO_A_HI__A, &dco_a_hi, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_RAM_DCO_A_LO__A, &dco_a_lo, 0); + rc = drxj_dap_read_reg16(dev_addr, AUD_DEM_RAM_DCO_A_LO__A, &dco_a_lo, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_RAM_DCO_B_HI__A, &dco_b_hi, 0); + rc = drxj_dap_read_reg16(dev_addr, AUD_DEM_RAM_DCO_B_HI__A, &dco_b_hi, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_RAM_DCO_B_LO__A, &dco_b_lo, 0); + rc = drxj_dap_read_reg16(dev_addr, AUD_DEM_RAM_DCO_B_LO__A, &dco_b_lo, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -15039,12 +14882,12 @@ aud_ctrl_get_cfg_carrier(struct drx_demod_instance *demod, struct drx_cfg_aud_ca /* DC level of the incoming FM signal on the primary & seconday sound channel */ - rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DSP_RD_FM_DC_LEVEL_A__A, &dc_lvl_a, 0); + rc = drxj_dap_read_reg16(dev_addr, AUD_DSP_RD_FM_DC_LEVEL_A__A, &dc_lvl_a, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DSP_RD_FM_DC_LEVEL_B__A, &dc_lvl_b, 0); + rc = drxj_dap_read_reg16(dev_addr, AUD_DSP_RD_FM_DC_LEVEL_B__A, &dc_lvl_b, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -15055,12 +14898,12 @@ aud_ctrl_get_cfg_carrier(struct drx_demod_instance *demod, struct drx_cfg_aud_ca carriers->b.shift = (DRX_U16TODRXFREQ(dc_lvl_b) / 322L); /* Carrier detetcion threshold for primary & secondary channel */ - rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_RAM_CM_A_THRSHLD__A, &cm_thes_a, 0); + rc = drxj_dap_read_reg16(dev_addr, AUD_DEM_RAM_CM_A_THRSHLD__A, &cm_thes_a, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_RAM_CM_B_THRSHLD__A, &cm_thes_b, 0); + rc = drxj_dap_read_reg16(dev_addr, AUD_DEM_RAM_CM_B_THRSHLD__A, &cm_thes_b, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -15149,7 +14992,7 @@ aud_ctrl_set_cfg_carrier(struct drx_demod_instance *demod, struct drx_cfg_aud_ca /* now update the modus register */ if (w_modus != r_modus) { - rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DEM_WR_MODUS__A, w_modus, 0); + rc = drxj_dap_write_reg16(dev_addr, AUD_DEM_WR_MODUS__A, w_modus, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -15165,34 +15008,34 @@ aud_ctrl_set_cfg_carrier(struct drx_demod_instance *demod, struct drx_cfg_aud_ca dco_b_hi = (u16) ((valB >> 12) & 0xFFF); dco_b_lo = (u16) (valB & 0xFFF); - rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DEM_WR_DCO_A_HI__A, dco_a_hi, 0); + rc = drxj_dap_write_reg16(dev_addr, AUD_DEM_WR_DCO_A_HI__A, dco_a_hi, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DEM_WR_DCO_A_LO__A, dco_a_lo, 0); + rc = drxj_dap_write_reg16(dev_addr, AUD_DEM_WR_DCO_A_LO__A, dco_a_lo, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DEM_WR_DCO_B_HI__A, dco_b_hi, 0); + rc = drxj_dap_write_reg16(dev_addr, AUD_DEM_WR_DCO_B_HI__A, dco_b_hi, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DEM_WR_DCO_B_LO__A, dco_b_lo, 0); + rc = drxj_dap_write_reg16(dev_addr, AUD_DEM_WR_DCO_B_LO__A, dco_b_lo, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Carrier detetcion threshold for primary & secondary channel */ - rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DEM_WR_CM_A_THRSHLD__A, carriers->a.thres, 0); + rc = drxj_dap_write_reg16(dev_addr, AUD_DEM_WR_CM_A_THRSHLD__A, carriers->a.thres, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DEM_WR_CM_B_THRSHLD__A, carriers->b.thres, 0); + rc = drxj_dap_write_reg16(dev_addr, AUD_DEM_WR_CM_B_THRSHLD__A, carriers->b.thres, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -15240,7 +15083,7 @@ aud_ctrl_get_cfg_mixer(struct drx_demod_instance *demod, struct drx_cfg_aud_mixe } /* Source Selctor */ - rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DSP_WR_SRC_I2S_MATR__A, &src_i2s_matr, 0); + rc = drxj_dap_read_reg16(dev_addr, AUD_DSP_WR_SRC_I2S_MATR__A, &src_i2s_matr, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -15282,7 +15125,7 @@ aud_ctrl_get_cfg_mixer(struct drx_demod_instance *demod, struct drx_cfg_aud_mixe } /* FM Matrix */ - rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_WR_FM_MATRIX__A, &fm_matr, 0); + rc = drxj_dap_read_reg16(dev_addr, AUD_DEM_WR_FM_MATRIX__A, &fm_matr, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -15346,7 +15189,7 @@ aud_ctrl_set_cfg_mixer(struct drx_demod_instance *demod, struct drx_cfg_aud_mixe } /* Source Selctor */ - rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DSP_WR_SRC_I2S_MATR__A, &src_i2s_matr, 0); + rc = drxj_dap_read_reg16(dev_addr, AUD_DSP_WR_SRC_I2S_MATR__A, &src_i2s_matr, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -15389,14 +15232,14 @@ aud_ctrl_set_cfg_mixer(struct drx_demod_instance *demod, struct drx_cfg_aud_mixe return -EINVAL; } /* write the result */ - rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DSP_WR_SRC_I2S_MATR__A, src_i2s_matr, 0); + rc = drxj_dap_write_reg16(dev_addr, AUD_DSP_WR_SRC_I2S_MATR__A, src_i2s_matr, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* FM Matrix */ - rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_WR_FM_MATRIX__A, &fm_matr, 0); + rc = drxj_dap_read_reg16(dev_addr, AUD_DEM_WR_FM_MATRIX__A, &fm_matr, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -15424,7 +15267,7 @@ aud_ctrl_set_cfg_mixer(struct drx_demod_instance *demod, struct drx_cfg_aud_mixe /* Only write if ASS is off */ if (ext_attr->aud_data.auto_sound == DRX_AUD_AUTO_SOUND_OFF) { - rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DEM_WR_FM_MATRIX__A, fm_matr, 0); + rc = drxj_dap_write_reg16(dev_addr, AUD_DEM_WR_FM_MATRIX__A, fm_matr, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -15472,7 +15315,7 @@ aud_ctrl_set_cfg_av_sync(struct drx_demod_instance *demod, enum drx_cfg_aud_av_s } /* audio/video synchronisation */ - rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DSP_WR_AV_SYNC__A, &w_aud_vid_sync, 0); + rc = drxj_dap_read_reg16(dev_addr, AUD_DSP_WR_AV_SYNC__A, &w_aud_vid_sync, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -15504,7 +15347,7 @@ aud_ctrl_set_cfg_av_sync(struct drx_demod_instance *demod, enum drx_cfg_aud_av_s return -EINVAL; } - rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DSP_WR_AV_SYNC__A, w_aud_vid_sync, 0); + rc = drxj_dap_write_reg16(dev_addr, AUD_DSP_WR_AV_SYNC__A, w_aud_vid_sync, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -15547,7 +15390,7 @@ aud_ctrl_get_cfg_av_sync(struct drx_demod_instance *demod, enum drx_cfg_aud_av_s } /* audio/video synchronisation */ - rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DSP_WR_AV_SYNC__A, &w_aud_vid_sync, 0); + rc = drxj_dap_read_reg16(dev_addr, AUD_DSP_WR_AV_SYNC__A, &w_aud_vid_sync, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -15661,7 +15504,7 @@ aud_ctrl_set_cfg_dev(struct drx_demod_instance *demod, enum drx_cfg_aud_deviatio /* now update the modus register */ if (w_modus != r_modus) { - rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DEM_WR_MODUS__A, w_modus, 0); + rc = drxj_dap_write_reg16(dev_addr, AUD_DEM_WR_MODUS__A, w_modus, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -15708,12 +15551,12 @@ aud_ctrl_get_cfg_prescale(struct drx_demod_instance *demod, struct drx_cfg_aud_p } /* read register data */ - rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DSP_WR_NICAM_PRESC__A, &r_nicam_prescaler, 0); + rc = drxj_dap_read_reg16(dev_addr, AUD_DSP_WR_NICAM_PRESC__A, &r_nicam_prescaler, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DSP_WR_FM_PRESC__A, &r_max_fm_deviation, 0); + rc = drxj_dap_read_reg16(dev_addr, AUD_DSP_WR_FM_PRESC__A, &r_max_fm_deviation, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -15825,12 +15668,12 @@ aud_ctrl_set_cfg_prescale(struct drx_demod_instance *demod, struct drx_cfg_aud_p } /* end of setting NICAM Prescaler */ - rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DSP_WR_NICAM_PRESC__A, nicam_prescaler, 0); + rc = drxj_dap_write_reg16(dev_addr, AUD_DSP_WR_NICAM_PRESC__A, nicam_prescaler, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DSP_WR_FM_PRESC__A, w_max_fm_deviation, 0); + rc = drxj_dap_write_reg16(dev_addr, AUD_DSP_WR_FM_PRESC__A, w_max_fm_deviation, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -15892,7 +15735,7 @@ static int aud_ctrl_beep(struct drx_demod_instance *demod, struct drx_aud_beep * if (beep->mute == true) the_beep = 0; - rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DSP_WR_BEEPER__A, the_beep, 0); + rc = drxj_dap_write_reg16(dev_addr, AUD_DSP_WR_BEEPER__A, the_beep, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -16084,14 +15927,14 @@ aud_ctrl_set_standard(struct drx_demod_instance *demod, enum drx_aud_standard *s w_modus |= (AUD_DEM_WR_MODUS_MOD_BTSC_BTSC_SAP); if (w_modus != r_modus) { - rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DEM_WR_MODUS__A, w_modus, 0); + rc = drxj_dap_write_reg16(dev_addr, AUD_DEM_WR_MODUS__A, w_modus, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } - rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DEM_WR_STANDARD_SEL__A, w_standard, 0); + rc = drxj_dap_write_reg16(dev_addr, AUD_DEM_WR_STANDARD_SEL__A, w_standard, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -16106,7 +15949,7 @@ aud_ctrl_set_standard(struct drx_demod_instance *demod, enum drx_aud_standard *s if (ext_attr->aud_data.volume.mute == false) { w_volume |= (u16) ((volume_buffer + AUD_VOLUME_ZERO_DB) << AUD_DSP_WR_VOLUME_VOL_MAIN__B); - rc = DRXJ_DAP.write_reg16func(dev_addr, AUD_DSP_WR_VOLUME__A, w_volume, 0); + rc = drxj_dap_write_reg16(dev_addr, AUD_DSP_WR_VOLUME__A, w_volume, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -16154,7 +15997,7 @@ aud_ctrl_get_standard(struct drx_demod_instance *demod, enum drx_aud_standard *s *standard = DRX_AUD_STANDARD_UNKNOWN; - rc = DRXJ_DAP.read_reg16func(dev_addr, AUD_DEM_RD_STANDARD_RES__A, &r_data, 0); + rc = drxj_dap_read_reg16(dev_addr, AUD_DEM_RD_STANDARD_RES__A, &r_data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -16426,7 +16269,7 @@ get_oob_symbol_rate_offset(struct i2c_device_addr *dev_addr, s32 *symbol_rate_of return -EIO; } - rc = DRXJ_DAP.read_reg16func(dev_addr, ORX_CON_CTI_DTI_R__A, &data, 0); + rc = drxj_dap_read_reg16(dev_addr, ORX_CON_CTI_DTI_R__A, &data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -16496,7 +16339,7 @@ get_oob_freq_offset(struct drx_demod_instance *demod, s32 *freq_offset) *freq_offset = 0; /* read sign (spectrum inversion) */ - rc = DRXJ_DAP.read_reg16func(dev_addr, ORX_FWP_IQM_FRQ_W__A, &rot, 0); + rc = drxj_dap_read_reg16(dev_addr, ORX_FWP_IQM_FRQ_W__A, &rot, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -16547,7 +16390,7 @@ get_oob_freq_offset(struct drx_demod_instance *demod, s32 *freq_offset) /* find FINE frequency offset */ /* fine_freq_offset = ( (CORRECTION_VALUE*symbol_rate) >> 18 ); */ - rc = DRXJ_DAP.read_reg16func(dev_addr, ORX_CON_CPH_FRQ_R__A, &data, 0); + rc = drxj_dap_read_reg16(dev_addr, ORX_CON_CPH_FRQ_R__A, &data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -16636,7 +16479,7 @@ static int get_oobmer(struct i2c_device_addr *dev_addr, u32 *mer) *mer = 0; /* READ MER */ - rc = DRXJ_DAP.read_reg16func(dev_addr, ORX_EQU_MER_MER_R__A, &data, 0); + rc = drxj_dap_read_reg16(dev_addr, ORX_EQU_MER_MER_R__A, &data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -16782,7 +16625,7 @@ static int set_orx_nsu_aox(struct drx_demod_instance *demod, bool active) u16 data = 0; /* Configure NSU_AOX */ - rc = DRXJ_DAP.read_reg16func(dev_addr, ORX_NSU_AOX_STDBY_W__A, &data, 0); + rc = drxj_dap_read_reg16(dev_addr, ORX_NSU_AOX_STDBY_W__A, &data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -16791,7 +16634,7 @@ static int set_orx_nsu_aox(struct drx_demod_instance *demod, bool active) data &= ((~ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON)); else data |= (ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON); - rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_NSU_AOX_STDBY_W__A, data, 0); + rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_STDBY_W__A, data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -16876,7 +16719,7 @@ static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_par pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0); + rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -16908,7 +16751,7 @@ static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_par /*********/ /* Stop */ /*********/ - rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0); + rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -17013,260 +16856,260 @@ static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_par goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Write magic word to enable pdr reg write */ - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_OOB_CRX_CFG__A, OOB_CRX_DRIVE_STRENGTH << SIO_PDR_OOB_CRX_CFG_DRIVE__B | 0x03 << SIO_PDR_OOB_CRX_CFG_MODE__B, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_OOB_CRX_CFG__A, OOB_CRX_DRIVE_STRENGTH << SIO_PDR_OOB_CRX_CFG_DRIVE__B | 0x03 << SIO_PDR_OOB_CRX_CFG_MODE__B, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_PDR_OOB_DRX_CFG__A, OOB_DRX_DRIVE_STRENGTH << SIO_PDR_OOB_DRX_CFG_DRIVE__B | 0x03 << SIO_PDR_OOB_DRX_CFG_MODE__B, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_OOB_DRX_CFG__A, OOB_DRX_DRIVE_STRENGTH << SIO_PDR_OOB_DRX_CFG_DRIVE__B | 0x03 << SIO_PDR_OOB_DRX_CFG_MODE__B, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Write magic word to disable pdr reg write */ - rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_TOP_COMM_KEY__A, 0, 0); + rc = drxj_dap_write_reg16(dev_addr, ORX_TOP_COMM_KEY__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_FWP_AAG_LEN_W__A, 16000, 0); + rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_AAG_LEN_W__A, 16000, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_FWP_AAG_THR_W__A, 40, 0); + rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_AAG_THR_W__A, 40, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* ddc */ - rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_DDC_OFO_SET_W__A, ORX_DDC_OFO_SET_W__PRE, 0); + rc = drxj_dap_write_reg16(dev_addr, ORX_DDC_OFO_SET_W__A, ORX_DDC_OFO_SET_W__PRE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* nsu */ - rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_NSU_AOX_LOPOW_W__A, ext_attr->oob_lo_pow, 0); + rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_LOPOW_W__A, ext_attr->oob_lo_pow, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* initialization for target mode */ - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_TARGET_MODE__A, SCU_RAM_ORX_TARGET_MODE_2048KBPS_SQRT, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TARGET_MODE__A, SCU_RAM_ORX_TARGET_MODE_2048KBPS_SQRT, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_FREQ_GAIN_CORR__A, SCU_RAM_ORX_FREQ_GAIN_CORR_2048KBPS, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FREQ_GAIN_CORR__A, SCU_RAM_ORX_FREQ_GAIN_CORR_2048KBPS, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* Reset bits for timing and freq. recovery */ - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_RST_CPH__A, 0x0001, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_CPH__A, 0x0001, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_RST_CTI__A, 0x0002, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_CTI__A, 0x0002, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_RST_KRN__A, 0x0004, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_KRN__A, 0x0004, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_RST_KRP__A, 0x0008, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_KRP__A, 0x0008, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* AGN_LOCK = {2048>>3, -2048, 8, -8, 0, 1}; */ - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_AGN_LOCK_TH__A, 2048 >> 3, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_TH__A, 2048 >> 3, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_AGN_LOCK_TOTH__A, (u16)(-2048), 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_TOTH__A, (u16)(-2048), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_AGN_ONLOCK_TTH__A, 8, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_ONLOCK_TTH__A, 8, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_AGN_UNLOCK_TTH__A, (u16)(-8), 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_UNLOCK_TTH__A, (u16)(-8), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_AGN_LOCK_MASK__A, 1, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_MASK__A, 1, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* DGN_LOCK = {10, -2048, 8, -8, 0, 1<<1}; */ - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_DGN_LOCK_TH__A, 10, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_TH__A, 10, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_DGN_LOCK_TOTH__A, (u16)(-2048), 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_TOTH__A, (u16)(-2048), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_DGN_ONLOCK_TTH__A, 8, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_ONLOCK_TTH__A, 8, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_DGN_UNLOCK_TTH__A, (u16)(-8), 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_UNLOCK_TTH__A, (u16)(-8), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_DGN_LOCK_MASK__A, 1 << 1, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_MASK__A, 1 << 1, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* FRQ_LOCK = {15,-2048, 8, -8, 0, 1<<2}; */ - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TH__A, 17, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TH__A, 17, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TOTH__A, (u16)(-2048), 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TOTH__A, (u16)(-2048), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_FRQ_ONLOCK_TTH__A, 8, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_ONLOCK_TTH__A, 8, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_FRQ_UNLOCK_TTH__A, (u16)(-8), 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_UNLOCK_TTH__A, (u16)(-8), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_FRQ_LOCK_MASK__A, 1 << 2, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_MASK__A, 1 << 2, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* PHA_LOCK = {5000, -2048, 8, -8, 0, 1<<3}; */ - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_PHA_LOCK_TH__A, 3000, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_TH__A, 3000, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_PHA_LOCK_TOTH__A, (u16)(-2048), 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_TOTH__A, (u16)(-2048), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_PHA_ONLOCK_TTH__A, 8, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_ONLOCK_TTH__A, 8, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_PHA_UNLOCK_TTH__A, (u16)(-8), 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_UNLOCK_TTH__A, (u16)(-8), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_PHA_LOCK_MASK__A, 1 << 3, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_MASK__A, 1 << 3, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* TIM_LOCK = {300, -2048, 8, -8, 0, 1<<4}; */ - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_TIM_LOCK_TH__A, 400, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_TH__A, 400, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_TIM_LOCK_TOTH__A, (u16)(-2048), 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_TOTH__A, (u16)(-2048), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_TIM_ONLOCK_TTH__A, 8, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_ONLOCK_TTH__A, 8, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_TIM_UNLOCK_TTH__A, (u16)(-8), 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_UNLOCK_TTH__A, (u16)(-8), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_TIM_LOCK_MASK__A, 1 << 4, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_MASK__A, 1 << 4, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* EQU_LOCK = {20, -2048, 8, -8, 0, 1<<5}; */ - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_EQU_LOCK_TH__A, 20, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_TH__A, 20, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_EQU_LOCK_TOTH__A, (u16)(-2048), 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_TOTH__A, (u16)(-2048), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_EQU_ONLOCK_TTH__A, 4, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_ONLOCK_TTH__A, 4, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_EQU_UNLOCK_TTH__A, (u16)(-4), 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_UNLOCK_TTH__A, (u16)(-4), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_ORX_EQU_LOCK_MASK__A, 1 << 5, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_MASK__A, 1 << 5, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } /* PRE-Filter coefficients (PFI) */ - rc = DRXJ_DAP.write_block_func(dev_addr, ORX_FWP_PFI_A_W__A, sizeof(pfi_coeffs[mode_index]), ((u8 *)pfi_coeffs[mode_index]), 0); + rc = drxdap_fasi_write_block(dev_addr, ORX_FWP_PFI_A_W__A, sizeof(pfi_coeffs[mode_index]), ((u8 *)pfi_coeffs[mode_index]), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_TOP_MDE_W__A, mode_index, 0); + rc = drxj_dap_write_reg16(dev_addr, ORX_TOP_MDE_W__A, mode_index, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -17274,23 +17117,23 @@ static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_par /* NYQUIST-Filter coefficients (NYQ) */ for (i = 0; i < (NYQFILTERLEN + 1) / 2; i++) { - rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_FWP_NYQ_ADR_W__A, i, 0); + rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_ADR_W__A, i, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_FWP_NYQ_COF_RW__A, nyquist_coeffs[mode_index][i], 0); + rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_COF_RW__A, nyquist_coeffs[mode_index][i], 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } - rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_FWP_NYQ_ADR_W__A, 31, 0); + rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_ADR_W__A, 31, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_ACTIVE, 0); + rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_ACTIVE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -17314,7 +17157,7 @@ static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_par pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_NSU_AOX_STHR_W__A, ext_attr->oob_pre_saw, 0); + rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_STHR_W__A, ext_attr->oob_pre_saw, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -17352,17 +17195,17 @@ ctrl_get_oob(struct drx_demod_instance *demod, struct drxoob_status *oob_status) if (!ext_attr->oob_power_on) return -EIO; - rc = DRXJ_DAP.read_reg16func(dev_addr, ORX_DDC_OFO_SET_W__A, &data, 0); + rc = drxj_dap_read_reg16(dev_addr, ORX_DDC_OFO_SET_W__A, &data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.read_reg16func(dev_addr, ORX_NSU_TUN_RFGAIN_W__A, &data, 0); + rc = drxj_dap_read_reg16(dev_addr, ORX_NSU_TUN_RFGAIN_W__A, &data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.read_reg16func(dev_addr, ORX_FWP_AAG_THR_W__A, &data, 0); + rc = drxj_dap_read_reg16(dev_addr, ORX_FWP_AAG_THR_W__A, &data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -17372,7 +17215,7 @@ ctrl_get_oob(struct drx_demod_instance *demod, struct drxoob_status *oob_status) pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.read_reg16func(dev_addr, ORX_FWP_SRC_DGN_W__A, &data, 0); + rc = drxj_dap_read_reg16(dev_addr, ORX_FWP_SRC_DGN_W__A, &data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -17423,7 +17266,7 @@ ctrl_set_cfg_oob_pre_saw(struct drx_demod_instance *demod, u16 *cfg_data) dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; - rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_NSU_AOX_STHR_W__A, *cfg_data, 0); + rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_STHR_W__A, *cfg_data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -17473,7 +17316,7 @@ ctrl_set_cfg_oob_lo_power(struct drx_demod_instance *demod, enum drxj_cfg_oob_lo dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; - rc = DRXJ_DAP.write_reg16func(dev_addr, ORX_NSU_AOX_LOPOW_W__A, *cfg_data, 0); + rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_LOPOW_W__A, *cfg_data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -17737,7 +17580,7 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) } } #endif /* DRXJ_VSB_ONLY */ - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -18451,7 +18294,7 @@ ctrl_set_standard(struct drx_demod_instance *demod, enum drx_standard *standard) case DRX_STANDARD_ITU_C: do { u16 dummy; - rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SCU_RAM_VERSION_HI__A, &dummy, 0); + rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SCU_RAM_VERSION_HI__A, &dummy, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -18525,7 +18368,7 @@ ctrl_get_standard(struct drx_demod_instance *demod, enum drx_standard *standard) *standard = ext_attr->standard; do { u16 dummy; - rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SCU_RAM_VERSION_HI__A, &dummy, 0); + rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SCU_RAM_VERSION_HI__A, &dummy, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -18780,12 +18623,12 @@ ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode) } if (*mode != DRXJ_POWER_DOWN_MAIN_PATH) { - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -18873,7 +18716,7 @@ static int ctrl_probe_device(struct drx_demod_instance *demod) } /* Check device id */ - rc = DRXJ_DAP.read_reg32func(dev_addr, SIO_TOP_JTAGID_LO__A, &jtag, 0); + rc = drxdap_fasi_read_reg32(dev_addr, SIO_TOP_JTAGID_LO__A, &jtag, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -18909,7 +18752,7 @@ static int ctrl_probe_device(struct drx_demod_instance *demod) suddenly disappears after a succesful drx_open */ do { u16 dummy; - rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SCU_RAM_VERSION_HI__A, &dummy, 0); + rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SCU_RAM_VERSION_HI__A, &dummy, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -19023,17 +18866,17 @@ ctrl_get_cfg_oob_misc(struct drx_demod_instance *demod, struct drxj_cfg_oob_misc /* TODO */ /* check if the same registers are used for all standards (QAM/VSB/ATV) */ - rc = DRXJ_DAP.read_reg16func(dev_addr, ORX_NSU_TUN_IFGAIN_W__A, &misc->agc.IFAGC, 0); + rc = drxj_dap_read_reg16(dev_addr, ORX_NSU_TUN_IFGAIN_W__A, &misc->agc.IFAGC, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.read_reg16func(dev_addr, ORX_NSU_TUN_RFGAIN_W__A, &misc->agc.RFAGC, 0); + rc = drxj_dap_read_reg16(dev_addr, ORX_NSU_TUN_RFGAIN_W__A, &misc->agc.RFAGC, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.read_reg16func(dev_addr, ORX_FWP_SRC_DGN_W__A, &data, 0); + rc = drxj_dap_read_reg16(dev_addr, ORX_FWP_SRC_DGN_W__A, &data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -19366,17 +19209,17 @@ ctrl_get_cfg_agc_internal(struct drx_demod_instance *demod, u16 *agc_internal) return -EINVAL; } - rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_CF_POW__A, &iqm_cf_power, 0); + rc = drxj_dap_read_reg16(dev_addr, IQM_CF_POW__A, &iqm_cf_power, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_CF_SCALE_SH__A, &iqm_cf_scale_sh, 0); + rc = drxj_dap_read_reg16(dev_addr, IQM_CF_SCALE_SH__A, &iqm_cf_scale_sh, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.read_reg16func(dev_addr, IQM_CF_AMP__A, &iqm_cf_amp, 0); + rc = drxj_dap_read_reg16(dev_addr, IQM_CF_AMP__A, &iqm_cf_amp, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -19432,7 +19275,7 @@ ctrl_set_cfg_pre_saw(struct drx_demod_instance *demod, struct drxj_cfg_pre_saw * DRXJ_ISQAMSTD(pre_saw->standard)) || (DRXJ_ISATVSTD(ext_attr->standard) && DRXJ_ISATVSTD(pre_saw->standard))) { - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_PDREF__A, pre_saw->reference, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PDREF__A, pre_saw->reference, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -19524,7 +19367,7 @@ ctrl_set_cfg_afe_gain(struct drx_demod_instance *demod, struct drxj_cfg_afe_gain /* Only if standard is currently active */ if (ext_attr->standard == afe_gain->standard) { - rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_PGA_GAIN__A, gain, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PGA_GAIN__A, gain, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -19672,7 +19515,7 @@ ctrl_get_fec_meas_seq_count(struct drx_demod_instance *demod, u16 *fec_meas_seq_ if (fec_meas_seq_count == NULL) return -EINVAL; - rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, fec_meas_seq_count, 0); + rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, fec_meas_seq_count, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -19703,7 +19546,7 @@ ctrl_get_accum_cr_rs_cw_err(struct drx_demod_instance *demod, u32 *accum_cr_rs_c if (accum_cr_rs_cw_err == NULL) return -EINVAL; - rc = DRXJ_DAP.read_reg32func(demod->my_i2c_dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, accum_cr_rs_cw_err, 0); + rc = drxdap_fasi_read_reg32(demod->my_i2c_dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, accum_cr_rs_cw_err, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -19731,7 +19574,7 @@ static int ctrl_set_cfg(struct drx_demod_instance *demod, struct drx_cfg *config do { u16 dummy; - rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SCU_RAM_VERSION_HI__A, &dummy, 0); + rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SCU_RAM_VERSION_HI__A, &dummy, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -19847,7 +19690,7 @@ static int ctrl_get_cfg(struct drx_demod_instance *demod, struct drx_cfg *config do { u16 dummy; - rc = DRXJ_DAP.read_reg16func(demod->my_i2c_dev_addr, SCU_RAM_VERSION_HI__A, &dummy, 0); + rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SCU_RAM_VERSION_HI__A, &dummy, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -20028,12 +19871,12 @@ int drxj_open(struct drx_demod_instance *demod) } /* Soft reset of sys- and osc-clockdomain */ - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_CC_SOFT_RST__A, (SIO_CC_SOFT_RST_SYS__M | SIO_CC_SOFT_RST_OSC__M), 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_CC_SOFT_RST__A, (SIO_CC_SOFT_RST_SYS__M | SIO_CC_SOFT_RST_OSC__M), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY, 0); + rc = drxj_dap_write_reg16(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -20042,7 +19885,7 @@ int drxj_open(struct drx_demod_instance *demod) /* TODO first make sure that everything keeps working before enabling this */ /* PowerDownAnalogBlocks() */ - rc = DRXJ_DAP.write_reg16func(dev_addr, ATV_TOP_STDBY__A, (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE) | ATV_TOP_STDBY_SIF_STDBY_STANDBY, 0); + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STDBY__A, (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE) | ATV_TOP_STDBY_SIF_STDBY_STANDBY, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -20079,7 +19922,7 @@ int drxj_open(struct drx_demod_instance *demod) goto rw_error; } /* Stop SCU */ - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -20114,7 +19957,7 @@ int drxj_open(struct drx_demod_instance *demod) } /* Run SCU for a little while to initialize microcode version numbers */ - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -20152,12 +19995,12 @@ int drxj_open(struct drx_demod_instance *demod) driver_version += (VERSION_PATCH / 10) % 10; driver_version <<= 4; driver_version += (VERSION_PATCH % 10); - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_DRIVER_VER_HI__A, (u16)(driver_version >> 16), 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_DRIVER_VER_HI__A, (u16)(driver_version >> 16), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_RAM_DRIVER_VER_LO__A, (u16)(driver_version & 0xFFFF), 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_DRIVER_VER_LO__A, (u16)(driver_version & 0xFFFF), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -20201,7 +20044,7 @@ int drxj_close(struct drx_demod_instance *demod) goto rw_error; } - rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -20463,7 +20306,7 @@ static int drx_ctrl_u_code(struct drx_demod_instance *demod, /* Perform the desired action */ switch (action) { case UCODE_UPLOAD: /* Upload microcode */ - if (demod->my_access_funct->write_block_func(dev_addr, + if (drxdap_fasi_write_block(dev_addr, block_hdr.addr, mc_block_nr_bytes, mc_data, 0x0000)) { @@ -20487,8 +20330,7 @@ static int drx_ctrl_u_code(struct drx_demod_instance *demod, else bytes_to_comp = bytes_left; - if (demod->my_access_funct-> - read_block_func(dev_addr, + if (drxdap_fasi_read_block(dev_addr, curr_addr, (u16)bytes_to_comp, (u8 *)mc_data_buffer, -- cgit v1.1 From ea8f3c2c60f98ba1177f200574711abbb518024a Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sun, 16 Feb 2014 00:38:44 -0300 Subject: [media] drx-j: Allow userspace control of LNA Instead of just disabling the LNA every time, allow to control it from userspace. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drxj.c | 41 +++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index 7a28c20..f48f320 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -20683,6 +20683,46 @@ static int drx39xxj_init(struct dvb_frontend *fe) return 0; } +static int drx39xxj_set_lna(struct dvb_frontend *fe) +{ + int result; + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + struct drx39xxj_state *state = fe->demodulator_priv; + struct drx_demod_instance *demod = state->demod; + struct drxj_data *ext_attr = demod->my_ext_attr; + struct drxuio_cfg uio_cfg; + struct drxuio_data uio_data; + + if (c->lna) { + if (!ext_attr->has_lna) { + pr_err("LNA is not supported on this device!\n"); + return -EINVAL; + + } + } + + /* Turn off the LNA */ + uio_cfg.uio = DRX_UIO1; + uio_cfg.mode = DRX_UIO_MODE_READWRITE; + /* Configure user-I/O #3: enable read/write */ + result = ctrl_set_uio_cfg(demod, &uio_cfg); + if (result) { + pr_err("Failed to setup LNA GPIO!\n"); + return result; + } + + uio_data.uio = DRX_UIO1; + uio_data.value = c->lna; + result = ctrl_uio_write(demod, &uio_data); + if (result != 0) { + pr_err("Failed to %sable LNA!\n", + c->lna ? "en" : "dis"); + return result; + } + + return 0; +} + static int drx39xxj_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings *tune) { @@ -20824,6 +20864,7 @@ static struct dvb_frontend_ops drx39xxj_ops = { .read_snr = drx39xxj_read_snr, .read_ucblocks = drx39xxj_read_ucblocks, .release = drx39xxj_release, + .set_lna = drx39xxj_set_lna, }; MODULE_DESCRIPTION("Micronas DRX39xxj Frontend"); -- cgit v1.1 From 9e4c509d7444e067d39d3ac96a3398721bca4f01 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Thu, 27 Feb 2014 03:34:17 -0300 Subject: [media] drx-j: Use single master mode There are no other I2C masters here. Also, the Windows driver uses this mode (and both drxd and drxk Kernel drivers). So, switch to it. That helps to compare the logs between the Linux driver and the Windows one. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drx_driver.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h index 8419989..e54eb35 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h @@ -260,7 +260,7 @@ int drxbsp_tuner_default_i2c_write_read(struct tuner_instance *tuner, * */ #ifndef DRXDAP_SINGLE_MASTER -#define DRXDAP_SINGLE_MASTER 0 +#define DRXDAP_SINGLE_MASTER 1 #endif /** -- cgit v1.1 From d7a5478a8a3b45d39823e242bdd05e430b9c9b26 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Thu, 27 Feb 2014 05:35:13 -0300 Subject: [media] drx-j: be sure to send the powerup command at device open As drxj_close puts the device in powerdown, we need to power it up properly at drxj_open. This is the behavior noticed at the Windows driver. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drxj.c | 39 +++++++++++++++++------------ 1 file changed, 23 insertions(+), 16 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index f48f320..97a3005 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -18621,19 +18621,22 @@ ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode) default: return -EIO; } + ext_attr->standard = DRX_STANDARD_UNKNOWN; + } - if (*mode != DRXJ_POWER_DOWN_MAIN_PATH) { - rc = drxj_dap_write_reg16(dev_addr, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } + if (*mode != DRXJ_POWER_DOWN_MAIN_PATH) { + rc = drxj_dap_write_reg16(dev_addr, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + if ((*mode != DRX_POWER_UP)) { /* Initialize HI, wakeup key especially before put IC to sleep */ rc = init_hi(demod); if (rc != 0) { @@ -18648,14 +18651,13 @@ ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode) goto rw_error; } } - ext_attr->standard = DRX_STANDARD_UNKNOWN; } common_attr->current_power_mode = *mode; return 0; rw_error: - return -EIO; + return rc; } #if 0 @@ -19838,7 +19840,7 @@ int drxj_open(struct drx_demod_instance *demod) struct drxu_code_info ucode_info; struct drx_cfg_mpeg_output cfg_mpeg_output; int rc; - + enum drx_power_mode power_mode = DRX_POWER_UP; if ((demod == NULL) || (demod->my_common_attr == NULL) || @@ -19856,12 +19858,16 @@ int drxj_open(struct drx_demod_instance *demod) ext_attr = (struct drxj_data *) demod->my_ext_attr; common_attr = (struct drx_common_attr *) demod->my_common_attr; - rc = power_up_device(demod); + rc = ctrl_power_mode(demod, &power_mode); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - common_attr->current_power_mode = DRX_POWER_UP; + if (power_mode != DRX_POWER_UP) { + rc = -EINVAL; + pr_err("failed to powerup device\n"); + goto rw_error; + } /* has to be in front of setIqmAf and setOrxNsuAox */ rc = get_device_capabilities(demod); @@ -20797,6 +20803,7 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) demod->my_common_attr->microcode_file = DRX39XX_MAIN_FIRMWARE; demod->my_common_attr->verify_microcode = true; demod->my_common_attr->intermediate_freq = 5000; + demod->my_common_attr->current_power_mode = DRX_POWER_DOWN; demod->my_ext_attr = demod_ext_attr; ((struct drxj_data *)demod_ext_attr)->uio_sma_tx_mode = DRX_UIO_MODE_READWRITE; demod->i2c = i2c; -- cgit v1.1 From 8afff9a23f8506c3439a7a0d7b21e975aed96ab4 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Thu, 27 Feb 2014 08:48:44 -0300 Subject: [media] drx-j: be sure to do a full software reset Mimic what windows driver does here: it writes 0x07 to SIO_CC_SOFT_RST__A, instead of just 0x03. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drxj.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index 97a3005..ed68c52 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -19876,8 +19876,15 @@ int drxj_open(struct drx_demod_instance *demod) goto rw_error; } - /* Soft reset of sys- and osc-clockdomain */ - rc = drxj_dap_write_reg16(dev_addr, SIO_CC_SOFT_RST__A, (SIO_CC_SOFT_RST_SYS__M | SIO_CC_SOFT_RST_OSC__M), 0); + /* + * Soft reset of sys- and osc-clockdomain + * + * HACK: On windows, it writes a 0x07 here, instead of just 0x03. + * As we didn't load the firmware here yet, we should do the same. + * Btw, this is coherent with DRX-K, where we send reset codes + * for modulation (OFTM, in DRX-k), SYS and OSC clock domains. + */ + rc = drxj_dap_write_reg16(dev_addr, SIO_CC_SOFT_RST__A, (0x04 | SIO_CC_SOFT_RST_SYS__M | SIO_CC_SOFT_RST_OSC__M), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; -- cgit v1.1 From 6c955b8b3ba23a51052de66520a2adff24fe6d04 Mon Sep 17 00:00:00 2001 From: Shuah Khan Date: Fri, 28 Feb 2014 18:23:00 -0300 Subject: [media] drx-j: fix pr_dbg undefined compile errors when DJH_DEBUG is defined MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit drxj.c fails to compile with the following errors when DJH_DEBUG is defined. drivers/media/dvb-frontends/drx39xyj/drxj.c:1567:2: error: implicit declaration of function ‘pr_dbg’ [-Werror=implicit-function-declaration] pr_dbg("drx3933 i2c operation addr=%x i2c=%p, wc=%x rc=%x\n", ^ Signed-off-by: Shuah Khan Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drxj.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index ed68c52..a78af4e 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -1562,7 +1562,7 @@ int drxbsp_i2c_write_read(struct i2c_device_addr *w_dev_addr, .flags = I2C_M_RD, .buf = r_data, .len = r_count}, }; - pr_dbg("drx3933 i2c operation addr=%x i2c=%p, wc=%x rc=%x\n", + pr_debug("drx3933 i2c operation addr=%x i2c=%p, wc=%x rc=%x\n", w_dev_addr->i2c_addr, state->i2c, w_count, r_count); if (i2c_transfer(state->i2c, msg, 2) != 2) { @@ -20640,7 +20640,7 @@ static int drx39xxj_set_frontend(struct dvb_frontend *fe) for (i = 0; i < 2000; i++) { fe_status_t status; drx39xxj_read_status(fe, &status); - pr_dbg("i=%d status=%d\n", i, status); + pr_debug("i=%d status=%d\n", i, status); msleep(100); i += 100; } @@ -20663,7 +20663,7 @@ static int drx39xxj_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) int result; #ifdef DJH_DEBUG - pr_dbg("i2c gate call: enable=%d state=%d\n", enable, + pr_debug("i2c gate call: enable=%d state=%d\n", enable, state->i2c_gate_open); #endif -- cgit v1.1 From 546ef6bf2517ae5c57fd4afc9129a0c79ea83bdf Mon Sep 17 00:00:00 2001 From: Shuah Khan Date: Fri, 28 Feb 2014 18:23:01 -0300 Subject: [media] drx-j: remove return that prevents DJH_DEBUG code to run drxbsp_i2c_write_read() has return that prevents DJH_DEBUG code to run. Remove it. Signed-off-by: Shuah Khan Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drxj.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index a78af4e..72c541a 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -1550,8 +1550,6 @@ int drxbsp_i2c_write_read(struct i2c_device_addr *w_dev_addr, return -EREMOTEIO; } - return 0; - #ifdef DJH_DEBUG struct drx39xxj_state *state = w_dev_addr->user_data; -- cgit v1.1 From 1ad77b5c29b19c633afaaabf268acedca79aa818 Mon Sep 17 00:00:00 2001 From: Shuah Khan Date: Fri, 28 Feb 2014 18:23:02 -0300 Subject: [media] drx-j: fix boot failure due to null pointer dereference MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit DJH_DEBUG only code path in drxbsp_i2c_write_read() dereferences w_dev_addr and subsequently w_dev_addr->user_data->i2c which results in failure during boot. This patch fixes the null pointer derefence bug as well as the following compile errors: LD arch/x86/built-in.o CC drivers/media/dvb-frontends/drx39xyj/drxj.o drivers/media/dvb-frontends/drx39xyj/drxj.c: In function ‘drxbsp_i2c_write_read’: drivers/media/dvb-frontends/drx39xyj/drxj.c:1558:25: error: redeclaration of ‘state’ with no linkage struct drx39xxj_state *state = w_dev_addr->user_data; ^ drivers/media/dvb-frontends/drx39xyj/drxj.c:1512:25: note: previous declaration of ‘state’ was here struct drx39xxj_state *state; ^ drivers/media/dvb-frontends/drx39xyj/drxj.c:1558:2: warning: ISO C90 forbids mixed declarations and code [-Wdeclaration-after-statement] struct drx39xxj_state *state = w_dev_addr->user_data; ^ drivers/media/dvb-frontends/drx39xyj/drxj.c:1560:17: error: redeclaration of ‘msg’ with no linkage struct i2c_msg msg[2] = { ^ drivers/media/dvb-frontends/drx39xyj/drxj.c:1513:17: note: previous declaration of ‘msg’ was here struct i2c_msg msg[2]; ^ Signed-off-by: Shuah Khan Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drxj.c | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index 72c541a..585d891 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -1551,14 +1551,23 @@ int drxbsp_i2c_write_read(struct i2c_device_addr *w_dev_addr, } #ifdef DJH_DEBUG - struct drx39xxj_state *state = w_dev_addr->user_data; + if (w_dev_addr == NULL || r_dev_addr == NULL) + return 0; - struct i2c_msg msg[2] = { - {.addr = w_dev_addr->i2c_addr, - .flags = 0, .buf = wData, .len = w_count}, - {.addr = r_dev_addr->i2c_addr, - .flags = I2C_M_RD, .buf = r_data, .len = r_count}, - }; + state = w_dev_addr->user_data; + + if (state->i2c == NULL) + return 0; + + msg[0].addr = w_dev_addr->i2c_addr; + msg[0].flags = 0; + msg[0].buf = wData; + msg[0].len = w_count; + msg[1].addr = r_dev_addr->i2c_addr; + msg[1].flags = I2C_M_RD; + msg[1].buf = r_data; + msg[1].len = r_count; + num_msgs = 2; pr_debug("drx3933 i2c operation addr=%x i2c=%p, wc=%x rc=%x\n", w_dev_addr->i2c_addr, state->i2c, w_count, r_count); -- cgit v1.1 From bf9b94ab924e460459682af8cb3423e8118f9c16 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sun, 2 Mar 2014 09:52:34 -0300 Subject: [media] drx-j: disable OOB Just like the windows driver, disable OOB after setting the driver version. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drxj.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index 585d891..f7c57c97 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -16676,7 +16676,6 @@ rw_error: /* Coefficients for the nyquist fitler (total: 27 taps) */ #define NYQFILTERLEN 27 -#if 0 static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_param) { int rc; @@ -17177,6 +17176,8 @@ rw_error: return -EIO; } +#if 0 + /** * \fn int ctrl_get_oob() * \brief Set modulation standard to be used. @@ -20026,6 +20027,12 @@ int drxj_open(struct drx_demod_instance *demod) goto rw_error; } + rc = ctrl_set_oob(demod, NULL); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* refresh the audio data structure with default */ ext_attr->aud_data = drxj_default_aud_data_g; -- cgit v1.1 From 41b5cc0c919e8b61732f01cedd666bd9794fa9b0 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sun, 2 Mar 2014 11:01:11 -0300 Subject: [media] drx-j: Properly initialize mpeg struct before using it The cfg_mpeg_output has more fields than what it is initialized when the code is called. Be sure to initialize everything before use, in order to avoid random behaviors. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drxj.c | 56 ++++++----------------------- 1 file changed, 11 insertions(+), 45 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index f7c57c97..8437fd5 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -2954,20 +2954,6 @@ ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o case DRX_STANDARD_ITU_C: break; default: - /* not an MPEG producing std, just store MPEG cfg */ - common_attr->mpeg_cfg.enable_mpeg_output = - cfg_data->enable_mpeg_output; - common_attr->mpeg_cfg.insert_rs_byte = - cfg_data->insert_rs_byte; - common_attr->mpeg_cfg.enable_parallel = - cfg_data->enable_parallel; - common_attr->mpeg_cfg.invert_data = cfg_data->invert_data; - common_attr->mpeg_cfg.invert_err = cfg_data->invert_err; - common_attr->mpeg_cfg.invert_str = cfg_data->invert_str; - common_attr->mpeg_cfg.invert_val = cfg_data->invert_val; - common_attr->mpeg_cfg.invert_clk = cfg_data->invert_clk; - common_attr->mpeg_cfg.static_clk = cfg_data->static_clk; - common_attr->mpeg_cfg.bitrate = cfg_data->bitrate; return 0; } @@ -3215,6 +3201,7 @@ ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o else fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MCLK__M)); + if (cfg_data->static_clk == true) { /* Static mode */ u32 dto_rate = 0; u32 bit_rate = 0; @@ -3546,15 +3533,6 @@ ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o /* save values for restore after re-acquire */ common_attr->mpeg_cfg.enable_mpeg_output = cfg_data->enable_mpeg_output; - common_attr->mpeg_cfg.insert_rs_byte = cfg_data->insert_rs_byte; - common_attr->mpeg_cfg.enable_parallel = cfg_data->enable_parallel; - common_attr->mpeg_cfg.invert_data = cfg_data->invert_data; - common_attr->mpeg_cfg.invert_err = cfg_data->invert_err; - common_attr->mpeg_cfg.invert_str = cfg_data->invert_str; - common_attr->mpeg_cfg.invert_val = cfg_data->invert_val; - common_attr->mpeg_cfg.invert_clk = cfg_data->invert_clk; - common_attr->mpeg_cfg.static_clk = cfg_data->static_clk; - common_attr->mpeg_cfg.bitrate = cfg_data->bitrate; return 0; rw_error: @@ -7644,17 +7622,10 @@ static int set_vsb(struct drx_demod_instance *demod) /* TODO: move to set_standard after hardware reset value problem is solved */ /* Configure initial MPEG output */ struct drx_cfg_mpeg_output cfg_mpeg_output; + + memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output)); cfg_mpeg_output.enable_mpeg_output = true; - cfg_mpeg_output.insert_rs_byte = common_attr->mpeg_cfg.insert_rs_byte; - cfg_mpeg_output.enable_parallel = - common_attr->mpeg_cfg.enable_parallel; - cfg_mpeg_output.invert_data = common_attr->mpeg_cfg.invert_data; - cfg_mpeg_output.invert_err = common_attr->mpeg_cfg.invert_err; - cfg_mpeg_output.invert_str = common_attr->mpeg_cfg.invert_str; - cfg_mpeg_output.invert_val = common_attr->mpeg_cfg.invert_val; - cfg_mpeg_output.invert_clk = common_attr->mpeg_cfg.invert_clk; - cfg_mpeg_output.static_clk = common_attr->mpeg_cfg.static_clk; - cfg_mpeg_output.bitrate = common_attr->mpeg_cfg.bitrate; + rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output); if (rc != 0) { pr_err("error %d\n", rc); @@ -8034,6 +8005,7 @@ static int power_down_qam(struct drx_demod_instance *demod, bool primary) int rc; struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; struct drx_cfg_mpeg_output cfg_mpeg_output; + struct drx_common_attr *common_attr = demod->my_common_attr; u16 cmd_result = 0; /* @@ -8103,7 +8075,9 @@ static int power_down_qam(struct drx_demod_instance *demod, bool primary) } } + memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output)); cfg_mpeg_output.enable_mpeg_output = false; + rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output); if (rc != 0) { pr_err("error %d\n", rc); @@ -10283,19 +10257,9 @@ set_qam(struct drx_demod_instance *demod, /* Configure initial MPEG output */ struct drx_cfg_mpeg_output cfg_mpeg_output; + memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output)); cfg_mpeg_output.enable_mpeg_output = true; - cfg_mpeg_output.insert_rs_byte = - common_attr->mpeg_cfg.insert_rs_byte; - cfg_mpeg_output.enable_parallel = - common_attr->mpeg_cfg.enable_parallel; - cfg_mpeg_output.invert_data = - common_attr->mpeg_cfg.invert_data; - cfg_mpeg_output.invert_err = common_attr->mpeg_cfg.invert_err; - cfg_mpeg_output.invert_str = common_attr->mpeg_cfg.invert_str; - cfg_mpeg_output.invert_val = common_attr->mpeg_cfg.invert_val; - cfg_mpeg_output.invert_clk = common_attr->mpeg_cfg.invert_clk; - cfg_mpeg_output.static_clk = common_attr->mpeg_cfg.static_clk; - cfg_mpeg_output.bitrate = common_attr->mpeg_cfg.bitrate; + rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output); if (rc != 0) { pr_err("error %d\n", rc); @@ -19930,7 +19894,9 @@ int drxj_open(struct drx_demod_instance *demod) } /* disable mpegoutput pins */ + memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output)); cfg_mpeg_output.enable_mpeg_output = false; + rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output); if (rc != 0) { pr_err("error %d\n", rc); -- cgit v1.1 From a5e7a67f9e774e6373314a5f2d64cdeca707d77c Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Mon, 3 Mar 2014 06:13:17 -0300 Subject: [media] drx-j: set it to serial mode by default Currently, there's just one device using this frontend: PCTV 80e, and it works on serial mode. Change the default here to serial mode. If we add more devices, then this option should be set via config structure. Acked-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drxj.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index 8437fd5..a99040b 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -833,7 +833,7 @@ struct drx_common_attr drxj_default_comm_attr_g = { /* MPEG output configuration */ true, /* If true, enable MPEG ouput */ false, /* If true, insert RS byte */ - true, /* If true, parallel out otherwise serial */ + false, /* If true, parallel out otherwise serial */ false, /* If true, invert DATA signals */ false, /* If true, invert ERR signal */ false, /* If true, invert STR signals */ -- cgit v1.1 From b2d5dafa095c194a441bd6a861544266be0c750d Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Mon, 3 Mar 2014 13:14:45 -0300 Subject: [media] em28xx: update CARDLIST.em28xx Some new boards got added. Update the cardlist. Signed-off-by: Mauro Carvalho Chehab --- Documentation/video4linux/CARDLIST.em28xx | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/video4linux/CARDLIST.em28xx b/Documentation/video4linux/CARDLIST.em28xx index 404ac9b..cb8706b 100644 --- a/Documentation/video4linux/CARDLIST.em28xx +++ b/Documentation/video4linux/CARDLIST.em28xx @@ -87,3 +87,7 @@ 86 -> PCTV QuatroStick nano (520e) (em2884) [2013:0251] 87 -> Terratec Cinergy HTC USB XS (em2884) [0ccd:008e,0ccd:00ac] 88 -> C3 Tech Digital Duo HDTV/SDTV USB (em2884) [1b80:e755] + 89 -> Delock 61959 (em2874) [1b80:e1cc] + 90 -> KWorld USB ATSC TV Stick UB435-Q V2 (em2874) [1b80:e346] + 91 -> SpeedLink Vicious And Devine Laplace webcam (em2765) [1ae7:9003,1ae7:9004] + 92 -> PCTV DVB-S2 Stick (461e) (em28178) -- cgit v1.1 From 4fd3281a4164d88ab20910b59b4f11cdd3f3216e Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Mon, 3 Mar 2014 13:15:33 -0300 Subject: [media] Update CARDLIST.cx23885 Some boards got added there. Update the cardlist to reflect the current status. Signed-off-by: Mauro Carvalho Chehab --- Documentation/video4linux/CARDLIST.cx23885 | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/video4linux/CARDLIST.cx23885 b/Documentation/video4linux/CARDLIST.cx23885 index 9f056d5..fc009d0 100644 --- a/Documentation/video4linux/CARDLIST.cx23885 +++ b/Documentation/video4linux/CARDLIST.cx23885 @@ -31,10 +31,13 @@ 30 -> NetUP Dual DVB-T/C-CI RF [1b55:e2e4] 31 -> Leadtek Winfast PxDVR3200 H XC4000 [107d:6f39] 32 -> MPX-885 - 33 -> Mygica X8507 [14f1:8502] + 33 -> Mygica X8502/X8507 ISDB-T [14f1:8502] 34 -> TerraTec Cinergy T PCIe Dual [153b:117e] 35 -> TeVii S471 [d471:9022] 36 -> Hauppauge WinTV-HVR1255 [0070:2259] 37 -> Prof Revolution DVB-S2 8000 [8000:3034] 38 -> Hauppauge WinTV-HVR4400 [0070:c108,0070:c138,0070:c12a,0070:c1f8] 39 -> AVerTV Hybrid Express Slim HC81R [1461:d939] + 40 -> TurboSight TBS 6981 [6981:8888] + 41 -> TurboSight TBS 6980 [6980:8888] + 42 -> Leadtek Winfast PxPVR2200 [107d:6f21] -- cgit v1.1 From 6cff36b23b66f437be904407601117fc74071db3 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Mon, 3 Mar 2014 16:27:38 -0300 Subject: [media] tda18212: add support for ATSC and clearQAM on tda18272 tda18272 is programmed just like tda18212, but it also supports ClearQAM and ATSC. Add support for them. Tested with a Kworld UB435-Q on both 8VSB and 256QAM modes. Signed-off-by: Mauro Carvalho Chehab --- drivers/media/tuners/tda18212.c | 12 ++++++++++++ drivers/media/tuners/tda18212.h | 2 ++ 2 files changed, 14 insertions(+) diff --git a/drivers/media/tuners/tda18212.c b/drivers/media/tuners/tda18212.c index abe256e..05a4ac9 100644 --- a/drivers/media/tuners/tda18212.c +++ b/drivers/media/tuners/tda18212.c @@ -150,6 +150,8 @@ static int tda18212_set_params(struct dvb_frontend *fe) #define DVBT2_8 5 #define DVBC_6 6 #define DVBC_8 7 + #define ATSC_VSB 8 + #define ATSC_QAM 9 static const u8 bw_params[][3] = { /* reg: 0f 13 23 */ [DVBT_6] = { 0xb3, 0x20, 0x03 }, @@ -160,6 +162,8 @@ static int tda18212_set_params(struct dvb_frontend *fe) [DVBT2_8] = { 0xbc, 0x22, 0x01 }, [DVBC_6] = { 0x92, 0x50, 0x03 }, [DVBC_8] = { 0x92, 0x53, 0x03 }, + [ATSC_VSB] = { 0x7d, 0x20, 0x63 }, + [ATSC_QAM] = { 0x7d, 0x20, 0x63 }, }; dev_dbg(&priv->i2c->dev, @@ -171,6 +175,14 @@ static int tda18212_set_params(struct dvb_frontend *fe) fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */ switch (c->delivery_system) { + case SYS_ATSC: + if_khz = priv->cfg->if_atsc_vsb; + i = ATSC_VSB; + break; + case SYS_DVBC_ANNEX_B: + if_khz = priv->cfg->if_atsc_qam; + i = ATSC_QAM; + break; case SYS_DVBT: switch (c->bandwidth_hz) { case 6000000: diff --git a/drivers/media/tuners/tda18212.h b/drivers/media/tuners/tda18212.h index 7e0d503..c36b49e 100644 --- a/drivers/media/tuners/tda18212.h +++ b/drivers/media/tuners/tda18212.h @@ -35,6 +35,8 @@ struct tda18212_config { u16 if_dvbt2_7; u16 if_dvbt2_8; u16 if_dvbc; + u16 if_atsc_vsb; + u16 if_atsc_qam; }; #if IS_ENABLED(CONFIG_MEDIA_TUNER_TDA18212) -- cgit v1.1 From 02bc1f5574e7324c03c49b3d2892e9e404d777be Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Mon, 3 Mar 2014 16:28:39 -0300 Subject: [media] em28xx: add support for Kworld UB435-Q version 3 This device is close to Kworld UB435-Q, but it uses a different tuner. Add support for it. Tested with both 8VSB and 256QAM modulations. Signed-off-by: Mauro Carvalho Chehab --- Documentation/video4linux/CARDLIST.em28xx | 1 + drivers/media/usb/em28xx/Kconfig | 1 + drivers/media/usb/em28xx/em28xx-cards.c | 23 ++++++++++++++++++++ drivers/media/usb/em28xx/em28xx-dvb.c | 36 +++++++++++++++++++++++++++++++ drivers/media/usb/em28xx/em28xx.h | 1 + 5 files changed, 62 insertions(+) diff --git a/Documentation/video4linux/CARDLIST.em28xx b/Documentation/video4linux/CARDLIST.em28xx index cb8706b..e085b12 100644 --- a/Documentation/video4linux/CARDLIST.em28xx +++ b/Documentation/video4linux/CARDLIST.em28xx @@ -91,3 +91,4 @@ 90 -> KWorld USB ATSC TV Stick UB435-Q V2 (em2874) [1b80:e346] 91 -> SpeedLink Vicious And Devine Laplace webcam (em2765) [1ae7:9003,1ae7:9004] 92 -> PCTV DVB-S2 Stick (461e) (em28178) + 93 -> KWorld USB ATSC TV Stick UB435-Q V3 (em2874) [1b80:e34c] diff --git a/drivers/media/usb/em28xx/Kconfig b/drivers/media/usb/em28xx/Kconfig index 7fb0287..d23a912 100644 --- a/drivers/media/usb/em28xx/Kconfig +++ b/drivers/media/usb/em28xx/Kconfig @@ -53,6 +53,7 @@ config VIDEO_EM28XX_DVB select DVB_MB86A20S if MEDIA_SUBDRV_AUTOSELECT select MEDIA_TUNER_QT1010 if MEDIA_SUBDRV_AUTOSELECT select MEDIA_TUNER_TDA18271 if MEDIA_SUBDRV_AUTOSELECT + select MEDIA_TUNER_TDA18212 if MEDIA_SUBDRV_AUTOSELECT select DVB_M88DS3103 if MEDIA_SUBDRV_AUTOSELECT select MEDIA_TUNER_M88TS2022 if MEDIA_SUBDRV_AUTOSELECT select DVB_DRX39XYJ if MEDIA_SUBDRV_AUTOSELECT diff --git a/drivers/media/usb/em28xx/em28xx-cards.c b/drivers/media/usb/em28xx/em28xx-cards.c index 138659b..5cd2df1 100644 --- a/drivers/media/usb/em28xx/em28xx-cards.c +++ b/drivers/media/usb/em28xx/em28xx-cards.c @@ -189,6 +189,14 @@ static struct em28xx_reg_seq kworld_a340_digital[] = { { -1, -1, -1, -1}, }; +static struct em28xx_reg_seq kworld_ub435q_v3_digital[] = { + {EM2874_R80_GPIO_P0_CTRL, 0xff, 0xff, 100}, + {EM2874_R80_GPIO_P0_CTRL, 0xfe, 0xff, 100}, + {EM2874_R80_GPIO_P0_CTRL, 0xbe, 0xff, 100}, + {EM2874_R80_GPIO_P0_CTRL, 0xfe, 0xff, 100}, + { -1, -1, -1, -1}, +}; + /* Pinnacle Hybrid Pro eb1a:2881 */ static struct em28xx_reg_seq pinnacle_hybrid_pro_analog[] = { {EM2820_R08_GPIO_CTRL, 0xfd, ~EM_GPIO_4, 10}, @@ -2139,6 +2147,19 @@ struct em28xx_board em28xx_boards[] = { .tuner_gpio = default_tuner_gpio, .def_i2c_bus = 1, }, + /* + * 1b80:e34c KWorld USB ATSC TV Stick UB435-Q V3 + * Empia EM2874B + LG DT3305 + NXP TDA18271HDC2 + */ + [EM2874_BOARD_KWORLD_UB435Q_V3] = { + .name = "KWorld USB ATSC TV Stick UB435-Q V3", + .tuner_type = TUNER_ABSENT, + .has_dvb = 1, + .tuner_gpio = kworld_ub435q_v3_digital, + .def_i2c_bus = 1, + .i2c_speed = EM28XX_I2C_CLK_WAIT_ENABLE | + EM28XX_I2C_FREQ_100_KHZ, + }, [EM2874_BOARD_PCTV_HD_MINI_80E] = { .name = "Pinnacle PCTV HD Mini", .tuner_type = TUNER_ABSENT, @@ -2325,6 +2346,8 @@ struct usb_device_id em28xx_id_table[] = { .driver_info = EM2870_BOARD_KWORLD_A340 }, { USB_DEVICE(0x1b80, 0xe346), .driver_info = EM2874_BOARD_KWORLD_UB435Q_V2 }, + { USB_DEVICE(0x1b80, 0xe34c), + .driver_info = EM2874_BOARD_KWORLD_UB435Q_V3 }, { USB_DEVICE(0x2013, 0x024f), .driver_info = EM28174_BOARD_PCTV_290E }, { USB_DEVICE(0x2013, 0x024c), diff --git a/drivers/media/usb/em28xx/em28xx-dvb.c b/drivers/media/usb/em28xx/em28xx-dvb.c index a63a3a2..d4986bd 100644 --- a/drivers/media/usb/em28xx/em28xx-dvb.c +++ b/drivers/media/usb/em28xx/em28xx-dvb.c @@ -49,6 +49,7 @@ #include "tda18271c2dd.h" #include "drxk.h" #include "tda10071.h" +#include "tda18212.h" #include "a8293.h" #include "qt1010.h" #include "mb86a20s.h" @@ -320,6 +321,18 @@ static struct lgdt3305_config em2874_lgdt3305_dev = { .qam_if_khz = 4000, }; +static struct lgdt3305_config em2874_lgdt3305_nogate_dev = { + .i2c_addr = 0x0e, + .demod_chip = LGDT3305, + .spectral_inversion = 1, + .deny_i2c_rptr = 1, + .mpeg_mode = LGDT3305_MPEG_SERIAL, + .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE, + .tpvalid_polarity = LGDT3305_TP_VALID_HIGH, + .vsb_if_khz = 3600, + .qam_if_khz = 3600, +}; + static struct s921_config sharp_isdbt = { .demod_address = 0x30 >> 1 }; @@ -356,6 +369,12 @@ static struct tda18271_config kworld_ub435q_v2_config = { .gate = TDA18271_GATE_DIGITAL, }; +static struct tda18212_config kworld_ub435q_v3_config = { + .i2c_address = 0x60, + .if_atsc_vsb = 3600, + .if_atsc_qam = 3600, +}; + static struct zl10353_config em28xx_zl10353_xc3028_no_i2c_gate = { .demod_address = (0x1e >> 1), .no_tuner = 1, @@ -1389,6 +1408,23 @@ static int em28xx_dvb_init(struct em28xx *dev) goto out_free; } break; + case EM2874_BOARD_KWORLD_UB435Q_V3: + dvb->fe[0] = dvb_attach(lgdt3305_attach, + &em2874_lgdt3305_nogate_dev, + &dev->i2c_adap[dev->def_i2c_bus]); + if (!dvb->fe[0]) { + result = -EINVAL; + goto out_free; + } + + /* Attach the demodulator. */ + if (!dvb_attach(tda18212_attach, dvb->fe[0], + &dev->i2c_adap[dev->def_i2c_bus], + &kworld_ub435q_v3_config)) { + result = -EINVAL; + goto out_free; + } + break; case EM2874_BOARD_PCTV_HD_MINI_80E: dvb->fe[0] = dvb_attach(drx39xxj_attach, &dev->i2c_adap[dev->def_i2c_bus]); if (dvb->fe[0] != NULL) { diff --git a/drivers/media/usb/em28xx/em28xx.h b/drivers/media/usb/em28xx/em28xx.h index 90e7cec..3b08556 100644 --- a/drivers/media/usb/em28xx/em28xx.h +++ b/drivers/media/usb/em28xx/em28xx.h @@ -138,6 +138,7 @@ #define EM2874_BOARD_KWORLD_UB435Q_V2 90 #define EM2765_BOARD_SPEEDLINK_VAD_LAPLACE 91 #define EM28178_BOARD_PCTV_461E 92 +#define EM2874_BOARD_KWORLD_UB435Q_V3 93 /* Limits minimum and default number of buffers */ #define EM28XX_MIN_BUF 4 -- cgit v1.1 From 54e925498cce3795add03ba0f06087fd78c1038d Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 4 Mar 2014 12:33:45 -0300 Subject: [media] em28xx: add support for DVB monitor led Some devices have a LED to indicate when DVB capture started. Add support for it. Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/em28xx/em28xx-core.c | 26 ++++++++++++++------------ drivers/media/usb/em28xx/em28xx.h | 1 + 2 files changed, 15 insertions(+), 12 deletions(-) diff --git a/drivers/media/usb/em28xx/em28xx-core.c b/drivers/media/usb/em28xx/em28xx-core.c index 6de41c6..523d7e9 100644 --- a/drivers/media/usb/em28xx/em28xx-core.c +++ b/drivers/media/usb/em28xx/em28xx-core.c @@ -619,6 +619,7 @@ EXPORT_SYMBOL_GPL(em28xx_find_led); int em28xx_capture_start(struct em28xx *dev, int start) { int rc; + const struct em28xx_led *led = NULL; if (dev->chip_id == CHIP_ID_EM2874 || dev->chip_id == CHIP_ID_EM2884 || @@ -643,6 +644,8 @@ int em28xx_capture_start(struct em28xx *dev, int start) /* Enable video capture */ rc = em28xx_write_reg(dev, 0x48, 0x00); + if (rc < 0) + return rc; if (dev->mode == EM28XX_ANALOG_MODE) rc = em28xx_write_reg(dev, @@ -650,6 +653,8 @@ int em28xx_capture_start(struct em28xx *dev, int start) else rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x37); + if (rc < 0) + return rc; msleep(6); } else { @@ -658,19 +663,16 @@ int em28xx_capture_start(struct em28xx *dev, int start) } } - if (rc < 0) - return rc; - - /* Switch (explicitly controlled) analog capturing LED on/off */ - if (dev->mode == EM28XX_ANALOG_MODE) { - const struct em28xx_led *led; + if (dev->mode == EM28XX_ANALOG_MODE) led = em28xx_find_led(dev, EM28XX_LED_ANALOG_CAPTURING); - if (led) - em28xx_write_reg_bits(dev, led->gpio_reg, - (!start ^ led->inverted) ? - ~led->gpio_mask : led->gpio_mask, - led->gpio_mask); - } + else + led = em28xx_find_led(dev, EM28XX_LED_DIGITAL_CAPTURING); + + if (led) + em28xx_write_reg_bits(dev, led->gpio_reg, + (!start ^ led->inverted) ? + ~led->gpio_mask : led->gpio_mask, + led->gpio_mask); return rc; } diff --git a/drivers/media/usb/em28xx/em28xx.h b/drivers/media/usb/em28xx/em28xx.h index 3b08556..9e44f5b 100644 --- a/drivers/media/usb/em28xx/em28xx.h +++ b/drivers/media/usb/em28xx/em28xx.h @@ -401,6 +401,7 @@ enum em28xx_adecoder { enum em28xx_led_role { EM28XX_LED_ANALOG_CAPTURING = 0, + EM28XX_LED_DIGITAL_CAPTURING, EM28XX_LED_ILLUMINATION, EM28XX_NUM_LED_ROLES, /* must be the last */ }; -- cgit v1.1 From 59432be1c7fbf2a4f608850855ff649bee0f7b3b Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 4 Mar 2014 12:34:34 -0300 Subject: [media] em28xx: Add LED support for Kworld UB435-Q v3 This device has a led at bit 7 of GPIO reg. 0x80 to indicate when a DVB capture is happening. Add support for it. Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/em28xx/em28xx-cards.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/media/usb/em28xx/em28xx-cards.c b/drivers/media/usb/em28xx/em28xx-cards.c index 5cd2df1..66d9c87 100644 --- a/drivers/media/usb/em28xx/em28xx-cards.c +++ b/drivers/media/usb/em28xx/em28xx-cards.c @@ -516,6 +516,17 @@ static struct em28xx_led speedlink_vad_laplace_leds[] = { {-1, 0, 0, 0}, }; +static struct em28xx_led kworld_ub435q_v3_leds[] = { + { + .role = EM28XX_LED_DIGITAL_CAPTURING, + .gpio_reg = EM2874_R80_GPIO_P0_CTRL, + .gpio_mask = 0x80, + .inverted = 1, + }, + {-1, 0, 0, 0}, +}; + + /* * Board definitions */ @@ -2159,6 +2170,7 @@ struct em28xx_board em28xx_boards[] = { .def_i2c_bus = 1, .i2c_speed = EM28XX_I2C_CLK_WAIT_ENABLE | EM28XX_I2C_FREQ_100_KHZ, + .leds = kworld_ub435q_v3_leds, }, [EM2874_BOARD_PCTV_HD_MINI_80E] = { .name = "Pinnacle PCTV HD Mini", -- cgit v1.1 From 5121288d23e1417cce4907f7d875e3bfbf50ac4c Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Wed, 22 Jan 2014 01:07:25 -0300 Subject: [media] devices.txt: add video4linux device for Software Defined Radio Add new video4linux device named /dev/swradio for Software Defined Radio use. V4L device minor numbers are allocated dynamically nowadays, but there is still configuration option for old fixed style. Add note to mention that configuration option too. Signed-off-by: Antti Palosaari Acked-by: Hans Verkuil Acked-by: Alan Cox Acked-by: Greg Kroah-Hartman Signed-off-by: Mauro Carvalho Chehab --- Documentation/devices.txt | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devices.txt b/Documentation/devices.txt index 10378cc..8f3e2cb 100644 --- a/Documentation/devices.txt +++ b/Documentation/devices.txt @@ -1491,10 +1491,17 @@ Your cooperation is appreciated. 64 = /dev/radio0 Radio device ... 127 = /dev/radio63 Radio device + 128 = /dev/swradio0 Software Defined Radio device + ... + 191 = /dev/swradio63 Software Defined Radio device 224 = /dev/vbi0 Vertical blank interrupt ... 255 = /dev/vbi31 Vertical blank interrupt + Minor numbers are allocated dynamically unless + CONFIG_VIDEO_FIXED_MINOR_RANGES (default n) + configuration option is set. + 81 block I2O hard disk 0 = /dev/i2o/hdq 17th I2O hard disk, whole disk 16 = /dev/i2o/hdr 18th I2O hard disk, whole disk -- cgit v1.1 From d42626bda4629ed9ad2ebcf44a7fece0777caa58 Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Wed, 11 Dec 2013 20:03:07 -0300 Subject: [media] v4l: add device type for Software Defined Radio Add new V4L device type VFL_TYPE_SDR for Software Defined Radio. It is registered as /dev/swradio0 (/dev/sdr0 was already reserved). Signed-off-by: Antti Palosaari Acked-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/v4l2-core/v4l2-dev.c | 6 ++++++ include/media/v4l2-dev.h | 3 ++- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/media/v4l2-core/v4l2-dev.c b/drivers/media/v4l2-core/v4l2-dev.c index 0a30dbf..9764ca0 100644 --- a/drivers/media/v4l2-core/v4l2-dev.c +++ b/drivers/media/v4l2-core/v4l2-dev.c @@ -758,6 +758,8 @@ static void determine_valid_ioctls(struct video_device *vdev) * %VFL_TYPE_RADIO - A radio card * * %VFL_TYPE_SUBDEV - A subdevice + * + * %VFL_TYPE_SDR - Software Defined Radio */ int __video_register_device(struct video_device *vdev, int type, int nr, int warn_if_nr_in_use, struct module *owner) @@ -797,6 +799,10 @@ int __video_register_device(struct video_device *vdev, int type, int nr, case VFL_TYPE_SUBDEV: name_base = "v4l-subdev"; break; + case VFL_TYPE_SDR: + /* Use device name 'swradio' because 'sdr' was already taken. */ + name_base = "swradio"; + break; default: printk(KERN_ERR "%s called with unknown type: %d\n", __func__, type); diff --git a/include/media/v4l2-dev.h b/include/media/v4l2-dev.h index c768c9f..eec6e46 100644 --- a/include/media/v4l2-dev.h +++ b/include/media/v4l2-dev.h @@ -24,7 +24,8 @@ #define VFL_TYPE_VBI 1 #define VFL_TYPE_RADIO 2 #define VFL_TYPE_SUBDEV 3 -#define VFL_TYPE_MAX 4 +#define VFL_TYPE_SDR 4 +#define VFL_TYPE_MAX 5 /* Is this a receiver, transmitter or mem-to-mem? */ /* Ignored for VFL_TYPE_SUBDEV. */ -- cgit v1.1 From 84099a282e1ba0facf7eee5108031a8f38f4b4fe Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Wed, 11 Dec 2013 20:24:02 -0300 Subject: [media] v4l: add new tuner types for SDR Define tuner types V4L2_TUNER_ADC and V4L2_TUNER_RF for SDR usage. ADC is used for setting sampling rate (sampling frequency) to SDR device. Another tuner type, named as V4L2_TUNER_RF, is possible RF tuner. Is is used to down-convert RF frequency to range ADC could sample. Having RF tuner is optional, whilst in practice it is almost always there. Also add checks to VIDIOC_G_FREQUENCY, VIDIOC_S_FREQUENCY and VIDIOC_ENUM_FREQ_BANDS only allow these two tuner types when device type is SDR (VFL_TYPE_SDR). For VIDIOC_G_FREQUENCY we do not check tuner type, instead override type with V4L2_TUNER_ADC in every case (requested by Hans in order to keep functionality in line with existing tuners and existing API does not specify it). Prohibit VIDIOC_S_HW_FREQ_SEEK explicitly when device type is SDR, as device cannot do hardware seek without a hardware demodulator. Signed-off-by: Antti Palosaari Acked-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/v4l2-core/v4l2-ioctl.c | 39 ++++++++++++++++++++++++++---------- include/uapi/linux/videodev2.h | 2 ++ 2 files changed, 30 insertions(+), 11 deletions(-) diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c index 707aef7..15ab349 100644 --- a/drivers/media/v4l2-core/v4l2-ioctl.c +++ b/drivers/media/v4l2-core/v4l2-ioctl.c @@ -1291,8 +1291,11 @@ static int v4l_g_frequency(const struct v4l2_ioctl_ops *ops, struct video_device *vfd = video_devdata(file); struct v4l2_frequency *p = arg; - p->type = (vfd->vfl_type == VFL_TYPE_RADIO) ? - V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV; + if (vfd->vfl_type == VFL_TYPE_SDR) + p->type = V4L2_TUNER_ADC; + else + p->type = (vfd->vfl_type == VFL_TYPE_RADIO) ? + V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV; return ops->vidioc_g_frequency(file, fh, p); } @@ -1303,10 +1306,15 @@ static int v4l_s_frequency(const struct v4l2_ioctl_ops *ops, const struct v4l2_frequency *p = arg; enum v4l2_tuner_type type; - type = (vfd->vfl_type == VFL_TYPE_RADIO) ? - V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV; - if (p->type != type) - return -EINVAL; + if (vfd->vfl_type == VFL_TYPE_SDR) { + if (p->type != V4L2_TUNER_ADC && p->type != V4L2_TUNER_RF) + return -EINVAL; + } else { + type = (vfd->vfl_type == VFL_TYPE_RADIO) ? + V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV; + if (type != p->type) + return -EINVAL; + } return ops->vidioc_s_frequency(file, fh, p); } @@ -1386,6 +1394,10 @@ static int v4l_s_hw_freq_seek(const struct v4l2_ioctl_ops *ops, struct v4l2_hw_freq_seek *p = arg; enum v4l2_tuner_type type; + /* s_hw_freq_seek is not supported for SDR for now */ + if (vfd->vfl_type == VFL_TYPE_SDR) + return -EINVAL; + type = (vfd->vfl_type == VFL_TYPE_RADIO) ? V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV; if (p->type != type) @@ -1885,11 +1897,16 @@ static int v4l_enum_freq_bands(const struct v4l2_ioctl_ops *ops, enum v4l2_tuner_type type; int err; - type = (vfd->vfl_type == VFL_TYPE_RADIO) ? - V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV; - - if (type != p->type) - return -EINVAL; + if (vfd->vfl_type == VFL_TYPE_SDR) { + if (p->type != V4L2_TUNER_ADC && p->type != V4L2_TUNER_RF) + return -EINVAL; + type = p->type; + } else { + type = (vfd->vfl_type == VFL_TYPE_RADIO) ? + V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV; + if (type != p->type) + return -EINVAL; + } if (ops->vidioc_enum_freq_bands) return ops->vidioc_enum_freq_bands(file, fh, p); if (is_valid_ioctl(vfd, VIDIOC_G_TUNER)) { diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h index 6ae7bbe..9dc79d1 100644 --- a/include/uapi/linux/videodev2.h +++ b/include/uapi/linux/videodev2.h @@ -159,6 +159,8 @@ enum v4l2_tuner_type { V4L2_TUNER_RADIO = 1, V4L2_TUNER_ANALOG_TV = 2, V4L2_TUNER_DIGITAL_TV = 3, + V4L2_TUNER_ADC = 4, + V4L2_TUNER_RF = 5, }; enum v4l2_memory { -- cgit v1.1 From 67f9a11759d7d382d79774cf16c0bf6cb87dc4f0 Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Wed, 11 Dec 2013 20:27:31 -0300 Subject: [media] v4l: 1 Hz resolution flag for tuners Add V4L2_TUNER_CAP_1HZ for 1 Hz resolution. Signed-off-by: Antti Palosaari Acked-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- include/uapi/linux/videodev2.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h index 9dc79d1..1cf2076 100644 --- a/include/uapi/linux/videodev2.h +++ b/include/uapi/linux/videodev2.h @@ -1341,6 +1341,7 @@ struct v4l2_modulator { #define V4L2_TUNER_CAP_RDS_CONTROLS 0x0200 #define V4L2_TUNER_CAP_FREQ_BANDS 0x0400 #define V4L2_TUNER_CAP_HWSEEK_PROG_LIM 0x0800 +#define V4L2_TUNER_CAP_1HZ 0x1000 /* Flags for the 'rxsubchans' field */ #define V4L2_TUNER_SUB_MONO 0x0001 -- cgit v1.1 From 6f3073b8dcdcf7a0eabbdd60ec3706bb9d4a131c Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Thu, 12 Dec 2013 13:34:30 -0300 Subject: [media] v4l: add stream format for SDR receiver Add new V4L2 stream format definition, V4L2_BUF_TYPE_SDR_CAPTURE, for SDR receiver. Signed-off-by: Antti Palosaari Acked-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/v4l2-core/v4l2-ioctl.c | 1 + include/trace/events/v4l2.h | 1 + include/uapi/linux/videodev2.h | 11 +++++++++++ 3 files changed, 13 insertions(+) diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c index 15ab349..9a2acaf 100644 --- a/drivers/media/v4l2-core/v4l2-ioctl.c +++ b/drivers/media/v4l2-core/v4l2-ioctl.c @@ -152,6 +152,7 @@ const char *v4l2_type_names[] = { [V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY] = "vid-out-overlay", [V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE] = "vid-cap-mplane", [V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE] = "vid-out-mplane", + [V4L2_BUF_TYPE_SDR_CAPTURE] = "sdr-cap", }; EXPORT_SYMBOL(v4l2_type_names); diff --git a/include/trace/events/v4l2.h b/include/trace/events/v4l2.h index ef94eca..b9bb1f2 100644 --- a/include/trace/events/v4l2.h +++ b/include/trace/events/v4l2.h @@ -18,6 +18,7 @@ { V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY, "VIDEO_OUTPUT_OVERLAY" },\ { V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE, "VIDEO_CAPTURE_MPLANE" },\ { V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, "VIDEO_OUTPUT_MPLANE" }, \ + { V4L2_BUF_TYPE_SDR_CAPTURE, "SDR_CAPTURE" }, \ { V4L2_BUF_TYPE_PRIVATE, "PRIVATE" }) #define show_field(field) \ diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h index 1cf2076..27bed7c 100644 --- a/include/uapi/linux/videodev2.h +++ b/include/uapi/linux/videodev2.h @@ -139,6 +139,7 @@ enum v4l2_buf_type { #endif V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE = 9, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE = 10, + V4L2_BUF_TYPE_SDR_CAPTURE = 11, /* Deprecated, do not use */ V4L2_BUF_TYPE_PRIVATE = 0x80, }; @@ -1695,6 +1696,15 @@ struct v4l2_pix_format_mplane { } __attribute__ ((packed)); /** + * struct v4l2_format_sdr - SDR format definition + * @pixelformat: little endian four character code (fourcc) + */ +struct v4l2_format_sdr { + __u32 pixelformat; + __u8 reserved[28]; +} __attribute__ ((packed)); + +/** * struct v4l2_format - stream data format * @type: enum v4l2_buf_type; type of the data stream * @pix: definition of an image format @@ -1712,6 +1722,7 @@ struct v4l2_format { struct v4l2_window win; /* V4L2_BUF_TYPE_VIDEO_OVERLAY */ struct v4l2_vbi_format vbi; /* V4L2_BUF_TYPE_VBI_CAPTURE */ struct v4l2_sliced_vbi_format sliced; /* V4L2_BUF_TYPE_SLICED_VBI_CAPTURE */ + struct v4l2_format_sdr sdr; /* V4L2_BUF_TYPE_SDR_CAPTURE */ __u8 raw_data[200]; /* user-defined */ } fmt; }; -- cgit v1.1 From 855df1dc6fdb519c7552053bc095f821bc360905 Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Sat, 14 Dec 2013 13:10:20 -0300 Subject: [media] v4l: define own IOCTL ops for SDR FMT Use own format ops for SDR data: vidioc_enum_fmt_sdr_cap vidioc_g_fmt_sdr_cap vidioc_s_fmt_sdr_cap vidioc_try_fmt_sdr_cap Signed-off-by: Antti Palosaari Acked-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- include/media/v4l2-ioctl.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/media/v4l2-ioctl.h b/include/media/v4l2-ioctl.h index e0b74a4..8be32f5 100644 --- a/include/media/v4l2-ioctl.h +++ b/include/media/v4l2-ioctl.h @@ -40,6 +40,8 @@ struct v4l2_ioctl_ops { struct v4l2_fmtdesc *f); int (*vidioc_enum_fmt_vid_out_mplane)(struct file *file, void *fh, struct v4l2_fmtdesc *f); + int (*vidioc_enum_fmt_sdr_cap) (struct file *file, void *fh, + struct v4l2_fmtdesc *f); /* VIDIOC_G_FMT handlers */ int (*vidioc_g_fmt_vid_cap) (struct file *file, void *fh, @@ -62,6 +64,8 @@ struct v4l2_ioctl_ops { struct v4l2_format *f); int (*vidioc_g_fmt_vid_out_mplane)(struct file *file, void *fh, struct v4l2_format *f); + int (*vidioc_g_fmt_sdr_cap) (struct file *file, void *fh, + struct v4l2_format *f); /* VIDIOC_S_FMT handlers */ int (*vidioc_s_fmt_vid_cap) (struct file *file, void *fh, @@ -84,6 +88,8 @@ struct v4l2_ioctl_ops { struct v4l2_format *f); int (*vidioc_s_fmt_vid_out_mplane)(struct file *file, void *fh, struct v4l2_format *f); + int (*vidioc_s_fmt_sdr_cap) (struct file *file, void *fh, + struct v4l2_format *f); /* VIDIOC_TRY_FMT handlers */ int (*vidioc_try_fmt_vid_cap) (struct file *file, void *fh, @@ -106,6 +112,8 @@ struct v4l2_ioctl_ops { struct v4l2_format *f); int (*vidioc_try_fmt_vid_out_mplane)(struct file *file, void *fh, struct v4l2_format *f); + int (*vidioc_try_fmt_sdr_cap) (struct file *file, void *fh, + struct v4l2_format *f); /* Buffer handlers */ int (*vidioc_reqbufs) (struct file *file, void *fh, struct v4l2_requestbuffers *b); -- cgit v1.1 From 582c52cb9cd2616ab0d41127b22ad56ee49d40b4 Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Thu, 12 Dec 2013 13:44:14 -0300 Subject: [media] v4l: enable some IOCTLs for SDR receiver Enable stream format (FMT) IOCTLs for SDR use. These are used for negotiate used data stream format. Reorganise some some IOCTL selection logic. Signed-off-by: Antti Palosaari Acked-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/v4l2-core/v4l2-dev.c | 21 ++++++++++++++++++--- drivers/media/v4l2-core/v4l2-ioctl.c | 35 +++++++++++++++++++++++++++++++++++ 2 files changed, 53 insertions(+), 3 deletions(-) diff --git a/drivers/media/v4l2-core/v4l2-dev.c b/drivers/media/v4l2-core/v4l2-dev.c index 9764ca0..98099e8 100644 --- a/drivers/media/v4l2-core/v4l2-dev.c +++ b/drivers/media/v4l2-core/v4l2-dev.c @@ -553,7 +553,7 @@ static void determine_valid_ioctls(struct video_device *vdev) const struct v4l2_ioctl_ops *ops = vdev->ioctl_ops; bool is_vid = vdev->vfl_type == VFL_TYPE_GRABBER; bool is_vbi = vdev->vfl_type == VFL_TYPE_VBI; - bool is_radio = vdev->vfl_type == VFL_TYPE_RADIO; + bool is_sdr = vdev->vfl_type == VFL_TYPE_SDR; bool is_rx = vdev->vfl_dir != VFL_DIR_TX; bool is_tx = vdev->vfl_dir != VFL_DIR_RX; @@ -662,9 +662,20 @@ static void determine_valid_ioctls(struct video_device *vdev) ops->vidioc_try_fmt_sliced_vbi_out))) set_bit(_IOC_NR(VIDIOC_TRY_FMT), valid_ioctls); SET_VALID_IOCTL(ops, VIDIOC_G_SLICED_VBI_CAP, vidioc_g_sliced_vbi_cap); + } else if (is_sdr) { + /* SDR specific ioctls */ + if (ops->vidioc_enum_fmt_sdr_cap) + set_bit(_IOC_NR(VIDIOC_ENUM_FMT), valid_ioctls); + if (ops->vidioc_g_fmt_sdr_cap) + set_bit(_IOC_NR(VIDIOC_G_FMT), valid_ioctls); + if (ops->vidioc_s_fmt_sdr_cap) + set_bit(_IOC_NR(VIDIOC_S_FMT), valid_ioctls); + if (ops->vidioc_try_fmt_sdr_cap) + set_bit(_IOC_NR(VIDIOC_TRY_FMT), valid_ioctls); } - if (!is_radio) { - /* ioctls valid for video or vbi */ + + if (is_vid || is_vbi || is_sdr) { + /* ioctls valid for video, vbi or sdr */ SET_VALID_IOCTL(ops, VIDIOC_REQBUFS, vidioc_reqbufs); SET_VALID_IOCTL(ops, VIDIOC_QUERYBUF, vidioc_querybuf); SET_VALID_IOCTL(ops, VIDIOC_QBUF, vidioc_qbuf); @@ -672,6 +683,10 @@ static void determine_valid_ioctls(struct video_device *vdev) SET_VALID_IOCTL(ops, VIDIOC_DQBUF, vidioc_dqbuf); SET_VALID_IOCTL(ops, VIDIOC_CREATE_BUFS, vidioc_create_bufs); SET_VALID_IOCTL(ops, VIDIOC_PREPARE_BUF, vidioc_prepare_buf); + } + + if (is_vid || is_vbi) { + /* ioctls valid for video or vbi */ if (ops->vidioc_s_std) set_bit(_IOC_NR(VIDIOC_ENUMSTD), valid_ioctls); SET_VALID_IOCTL(ops, VIDIOC_S_STD, vidioc_s_std); diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c index 9a2acaf..95dd4f1 100644 --- a/drivers/media/v4l2-core/v4l2-ioctl.c +++ b/drivers/media/v4l2-core/v4l2-ioctl.c @@ -246,6 +246,7 @@ static void v4l_print_format(const void *arg, bool write_only) const struct v4l2_vbi_format *vbi; const struct v4l2_sliced_vbi_format *sliced; const struct v4l2_window *win; + const struct v4l2_format_sdr *sdr; unsigned i; pr_cont("type=%s", prt_names(p->type, v4l2_type_names)); @@ -319,6 +320,14 @@ static void v4l_print_format(const void *arg, bool write_only) sliced->service_lines[0][i], sliced->service_lines[1][i]); break; + case V4L2_BUF_TYPE_SDR_CAPTURE: + sdr = &p->fmt.sdr; + pr_cont(", pixelformat=%c%c%c%c\n", + (sdr->pixelformat >> 0) & 0xff, + (sdr->pixelformat >> 8) & 0xff, + (sdr->pixelformat >> 16) & 0xff, + (sdr->pixelformat >> 24) & 0xff); + break; } } @@ -882,6 +891,7 @@ static int check_fmt(struct file *file, enum v4l2_buf_type type) const struct v4l2_ioctl_ops *ops = vfd->ioctl_ops; bool is_vid = vfd->vfl_type == VFL_TYPE_GRABBER; bool is_vbi = vfd->vfl_type == VFL_TYPE_VBI; + bool is_sdr = vfd->vfl_type == VFL_TYPE_SDR; bool is_rx = vfd->vfl_dir != VFL_DIR_TX; bool is_tx = vfd->vfl_dir != VFL_DIR_RX; @@ -931,6 +941,10 @@ static int check_fmt(struct file *file, enum v4l2_buf_type type) if (is_vbi && is_tx && ops->vidioc_g_fmt_sliced_vbi_out) return 0; break; + case V4L2_BUF_TYPE_SDR_CAPTURE: + if (is_sdr && is_rx && ops->vidioc_g_fmt_sdr_cap) + return 0; + break; default: break; } @@ -1050,6 +1064,10 @@ static int v4l_enum_fmt(const struct v4l2_ioctl_ops *ops, if (unlikely(!is_tx || !ops->vidioc_enum_fmt_vid_out_mplane)) break; return ops->vidioc_enum_fmt_vid_out_mplane(file, fh, arg); + case V4L2_BUF_TYPE_SDR_CAPTURE: + if (unlikely(!is_rx || !ops->vidioc_enum_fmt_sdr_cap)) + break; + return ops->vidioc_enum_fmt_sdr_cap(file, fh, arg); } return -EINVAL; } @@ -1060,6 +1078,7 @@ static int v4l_g_fmt(const struct v4l2_ioctl_ops *ops, struct v4l2_format *p = arg; struct video_device *vfd = video_devdata(file); bool is_vid = vfd->vfl_type == VFL_TYPE_GRABBER; + bool is_sdr = vfd->vfl_type == VFL_TYPE_SDR; bool is_rx = vfd->vfl_dir != VFL_DIR_TX; bool is_tx = vfd->vfl_dir != VFL_DIR_RX; @@ -1104,6 +1123,10 @@ static int v4l_g_fmt(const struct v4l2_ioctl_ops *ops, if (unlikely(!is_tx || is_vid || !ops->vidioc_g_fmt_sliced_vbi_out)) break; return ops->vidioc_g_fmt_sliced_vbi_out(file, fh, arg); + case V4L2_BUF_TYPE_SDR_CAPTURE: + if (unlikely(!is_rx || !is_sdr || !ops->vidioc_g_fmt_sdr_cap)) + break; + return ops->vidioc_g_fmt_sdr_cap(file, fh, arg); } return -EINVAL; } @@ -1114,6 +1137,7 @@ static int v4l_s_fmt(const struct v4l2_ioctl_ops *ops, struct v4l2_format *p = arg; struct video_device *vfd = video_devdata(file); bool is_vid = vfd->vfl_type == VFL_TYPE_GRABBER; + bool is_sdr = vfd->vfl_type == VFL_TYPE_SDR; bool is_rx = vfd->vfl_dir != VFL_DIR_TX; bool is_tx = vfd->vfl_dir != VFL_DIR_RX; @@ -1168,6 +1192,11 @@ static int v4l_s_fmt(const struct v4l2_ioctl_ops *ops, break; CLEAR_AFTER_FIELD(p, fmt.sliced); return ops->vidioc_s_fmt_sliced_vbi_out(file, fh, arg); + case V4L2_BUF_TYPE_SDR_CAPTURE: + if (unlikely(!is_rx || !is_sdr || !ops->vidioc_s_fmt_sdr_cap)) + break; + CLEAR_AFTER_FIELD(p, fmt.sdr); + return ops->vidioc_s_fmt_sdr_cap(file, fh, arg); } return -EINVAL; } @@ -1178,6 +1207,7 @@ static int v4l_try_fmt(const struct v4l2_ioctl_ops *ops, struct v4l2_format *p = arg; struct video_device *vfd = video_devdata(file); bool is_vid = vfd->vfl_type == VFL_TYPE_GRABBER; + bool is_sdr = vfd->vfl_type == VFL_TYPE_SDR; bool is_rx = vfd->vfl_dir != VFL_DIR_TX; bool is_tx = vfd->vfl_dir != VFL_DIR_RX; @@ -1232,6 +1262,11 @@ static int v4l_try_fmt(const struct v4l2_ioctl_ops *ops, break; CLEAR_AFTER_FIELD(p, fmt.sliced); return ops->vidioc_try_fmt_sliced_vbi_out(file, fh, arg); + case V4L2_BUF_TYPE_SDR_CAPTURE: + if (unlikely(!is_rx || !is_sdr || !ops->vidioc_try_fmt_sdr_cap)) + break; + CLEAR_AFTER_FIELD(p, fmt.sdr); + return ops->vidioc_try_fmt_sdr_cap(file, fh, arg); } return -EINVAL; } -- cgit v1.1 From c9c54f72d4a8fe02a94c345dde45f42628325223 Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Tue, 17 Dec 2013 17:41:12 -0300 Subject: [media] v4l: add device capability flag for SDR receiver VIDIOC_QUERYCAP IOCTL is used to query device capabilities. Add new capability flag to inform given device supports SDR capture. Signed-off-by: Antti Palosaari Acked-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- include/uapi/linux/videodev2.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h index 27bed7c..27fedfe 100644 --- a/include/uapi/linux/videodev2.h +++ b/include/uapi/linux/videodev2.h @@ -267,6 +267,8 @@ struct v4l2_capability { #define V4L2_CAP_RADIO 0x00040000 /* is a radio device */ #define V4L2_CAP_MODULATOR 0x00080000 /* has a modulator */ +#define V4L2_CAP_SDR_CAPTURE 0x00100000 /* Is a SDR capture device */ + #define V4L2_CAP_READWRITE 0x01000000 /* read/write systemcalls */ #define V4L2_CAP_ASYNCIO 0x02000000 /* async I/O */ #define V4L2_CAP_STREAMING 0x04000000 /* streaming I/O ioctls */ -- cgit v1.1 From bfffd7431c6e7661d13c3fd141863fde55c9338b Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Fri, 20 Dec 2013 02:32:21 -0300 Subject: [media] v4l: do not allow modulator ioctls for non-radio devices Modulator ioctls could be enabled mistakenly for non-radio devices. Currently those ioctls are only valid for radio. Fix it. Signed-off-by: Hans Verkuil Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- drivers/media/v4l2-core/v4l2-dev.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/media/v4l2-core/v4l2-dev.c b/drivers/media/v4l2-core/v4l2-dev.c index 98099e8..95112f6 100644 --- a/drivers/media/v4l2-core/v4l2-dev.c +++ b/drivers/media/v4l2-core/v4l2-dev.c @@ -553,6 +553,7 @@ static void determine_valid_ioctls(struct video_device *vdev) const struct v4l2_ioctl_ops *ops = vdev->ioctl_ops; bool is_vid = vdev->vfl_type == VFL_TYPE_GRABBER; bool is_vbi = vdev->vfl_type == VFL_TYPE_VBI; + bool is_radio = vdev->vfl_type == VFL_TYPE_RADIO; bool is_sdr = vdev->vfl_type == VFL_TYPE_SDR; bool is_rx = vdev->vfl_dir != VFL_DIR_TX; bool is_tx = vdev->vfl_dir != VFL_DIR_RX; @@ -726,8 +727,8 @@ static void determine_valid_ioctls(struct video_device *vdev) SET_VALID_IOCTL(ops, VIDIOC_ENUM_DV_TIMINGS, vidioc_enum_dv_timings); SET_VALID_IOCTL(ops, VIDIOC_DV_TIMINGS_CAP, vidioc_dv_timings_cap); } - if (is_tx) { - /* transmitter only ioctls */ + if (is_tx && (is_radio || is_sdr)) { + /* radio transmitter only ioctls */ SET_VALID_IOCTL(ops, VIDIOC_G_MODULATOR, vidioc_g_modulator); SET_VALID_IOCTL(ops, VIDIOC_S_MODULATOR, vidioc_s_modulator); } -- cgit v1.1 From 70b5efb8b7be95e9e7a762c62e25a7e0aeb73ee7 Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Wed, 18 Dec 2013 23:40:49 -0300 Subject: [media] DocBook: document 1 Hz flag Update documentation to reflect 1 Hz frequency step flag. Cc: Hans Verkuil Signed-off-by: Antti Palosaari Acked-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- .../DocBook/media/v4l/vidioc-enum-freq-bands.xml | 8 +++++--- Documentation/DocBook/media/v4l/vidioc-g-frequency.xml | 5 +++-- Documentation/DocBook/media/v4l/vidioc-g-modulator.xml | 6 ++++-- Documentation/DocBook/media/v4l/vidioc-g-tuner.xml | 15 ++++++++++++--- Documentation/DocBook/media/v4l/vidioc-s-hw-freq-seek.xml | 8 ++++++-- 5 files changed, 30 insertions(+), 12 deletions(-) diff --git a/Documentation/DocBook/media/v4l/vidioc-enum-freq-bands.xml b/Documentation/DocBook/media/v4l/vidioc-enum-freq-bands.xml index 6541ba0..4e8ea65 100644 --- a/Documentation/DocBook/media/v4l/vidioc-enum-freq-bands.xml +++ b/Documentation/DocBook/media/v4l/vidioc-enum-freq-bands.xml @@ -100,7 +100,7 @@ See capability The tuner/modulator capability flags for this frequency band, see . The V4L2_TUNER_CAP_LOW -capability must be the same for all frequency bands of the selected tuner/modulator. +or V4L2_TUNER_CAP_1HZ capability must be the same for all frequency bands of the selected tuner/modulator. So either all bands have that capability set, or none of them have that capability. @@ -109,7 +109,8 @@ So either all bands have that capability set, or none of them have that capabili The lowest tunable frequency in units of 62.5 kHz, or if the capability flag V4L2_TUNER_CAP_LOW is set, in units of 62.5 -Hz, for this frequency band. +Hz, for this frequency band. A 1 Hz unit is used when the capability flag +V4L2_TUNER_CAP_1HZ is set. __u32 @@ -117,7 +118,8 @@ Hz, for this frequency band. The highest tunable frequency in units of 62.5 kHz, or if the capability flag V4L2_TUNER_CAP_LOW is set, in units of 62.5 -Hz, for this frequency band. +Hz, for this frequency band. A 1 Hz unit is used when the capability flag +V4L2_TUNER_CAP_1HZ is set. __u32 diff --git a/Documentation/DocBook/media/v4l/vidioc-g-frequency.xml b/Documentation/DocBook/media/v4l/vidioc-g-frequency.xml index c7a1c46..d1034fb 100644 --- a/Documentation/DocBook/media/v4l/vidioc-g-frequency.xml +++ b/Documentation/DocBook/media/v4l/vidioc-g-frequency.xml @@ -109,9 +109,10 @@ See __u32 frequency Tuning frequency in units of 62.5 kHz, or if the -&v4l2-tuner; or &v4l2-modulator; capabilities flag +&v4l2-tuner; or &v4l2-modulator; capability flag V4L2_TUNER_CAP_LOW is set, in units of 62.5 -Hz. +Hz. A 1 Hz unit is used when the capability flag +V4L2_TUNER_CAP_1HZ is set. __u32 diff --git a/Documentation/DocBook/media/v4l/vidioc-g-modulator.xml b/Documentation/DocBook/media/v4l/vidioc-g-modulator.xml index 7f4ac7e..7068b59 100644 --- a/Documentation/DocBook/media/v4l/vidioc-g-modulator.xml +++ b/Documentation/DocBook/media/v4l/vidioc-g-modulator.xml @@ -113,7 +113,8 @@ change for example with the current video standard. The lowest tunable frequency in units of 62.5 KHz, or if the capability flag V4L2_TUNER_CAP_LOW is set, in units of 62.5 -Hz. +Hz, or if the capability flag +V4L2_TUNER_CAP_1HZ is set, in units of 1 Hz. __u32 @@ -121,7 +122,8 @@ Hz. The highest tunable frequency in units of 62.5 KHz, or if the capability flag V4L2_TUNER_CAP_LOW is set, in units of 62.5 -Hz. +Hz, or if the capability flag +V4L2_TUNER_CAP_1HZ is set, in units of 1 Hz. __u32 diff --git a/Documentation/DocBook/media/v4l/vidioc-g-tuner.xml b/Documentation/DocBook/media/v4l/vidioc-g-tuner.xml index 6cc8201..b0d8659 100644 --- a/Documentation/DocBook/media/v4l/vidioc-g-tuner.xml +++ b/Documentation/DocBook/media/v4l/vidioc-g-tuner.xml @@ -134,7 +134,9 @@ the structure refers to a radio tuner the The lowest tunable frequency in units of 62.5 kHz, or if the capability flag V4L2_TUNER_CAP_LOW is set, in units of 62.5 -Hz. If multiple frequency bands are supported, then +Hz, or if the capability flag +V4L2_TUNER_CAP_1HZ is set, in units of 1 Hz. +If multiple frequency bands are supported, then rangelow is the lowest frequency of all the frequency bands. @@ -144,7 +146,9 @@ of all the frequency bands. The highest tunable frequency in units of 62.5 kHz, or if the capability flag V4L2_TUNER_CAP_LOW is set, in units of 62.5 -Hz. If multiple frequency bands are supported, then +Hz, or if the capability flag +V4L2_TUNER_CAP_1HZ is set, in units of 1 Hz. +If multiple frequency bands are supported, then rangehigh is the highest frequency of all the frequency bands. @@ -270,7 +274,7 @@ applications must set the array to zero. V4L2_TUNER_CAP_LOW 0x0001 When set, tuning frequencies are expressed in units of -62.5 Hz, otherwise in units of 62.5 kHz. +62.5 Hz instead of 62.5 kHz. V4L2_TUNER_CAP_NORM @@ -360,6 +364,11 @@ radio tuners. The range to search when using the hardware seek functionality is programmable, see &VIDIOC-S-HW-FREQ-SEEK; for details. + + V4L2_TUNER_CAP_1HZ + 0x1000 + When set, tuning frequencies are expressed in units of 1 Hz instead of 62.5 kHz. + diff --git a/Documentation/DocBook/media/v4l/vidioc-s-hw-freq-seek.xml b/Documentation/DocBook/media/v4l/vidioc-s-hw-freq-seek.xml index 5b379e7..a5fc4c4 100644 --- a/Documentation/DocBook/media/v4l/vidioc-s-hw-freq-seek.xml +++ b/Documentation/DocBook/media/v4l/vidioc-s-hw-freq-seek.xml @@ -121,7 +121,9 @@ field and the &v4l2-tuner; index field. If non-zero, the lowest tunable frequency of the band to search in units of 62.5 kHz, or if the &v4l2-tuner; capability field has the -V4L2_TUNER_CAP_LOW flag set, in units of 62.5 Hz. +V4L2_TUNER_CAP_LOW flag set, in units of 62.5 Hz or if the &v4l2-tuner; +capability field has the +V4L2_TUNER_CAP_1HZ flag set, in units of 1 Hz. If rangelow is zero a reasonable default value is used. @@ -131,7 +133,9 @@ is used. If non-zero, the highest tunable frequency of the band to search in units of 62.5 kHz, or if the &v4l2-tuner; capability field has the -V4L2_TUNER_CAP_LOW flag set, in units of 62.5 Hz. +V4L2_TUNER_CAP_LOW flag set, in units of 62.5 Hz or if the &v4l2-tuner; +capability field has the +V4L2_TUNER_CAP_1HZ flag set, in units of 1 Hz. If rangehigh is zero a reasonable default value is used. -- cgit v1.1 From 559f40fe0c5469d9080e3fa70638199c26cc460c Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Fri, 20 Dec 2013 01:50:38 -0300 Subject: [media] DocBook: Software Defined Radio Interface Document V4L2 SDR interface. Cc: Hans Verkuil Signed-off-by: Antti Palosaari Acked-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/v4l/compat.xml | 10 ++ Documentation/DocBook/media/v4l/dev-sdr.xml | 104 +++++++++++++++++++++ Documentation/DocBook/media/v4l/io.xml | 6 ++ Documentation/DocBook/media/v4l/pixfmt.xml | 8 ++ Documentation/DocBook/media/v4l/v4l2.xml | 1 + Documentation/DocBook/media/v4l/vidioc-g-fmt.xml | 7 ++ .../DocBook/media/v4l/vidioc-querycap.xml | 6 ++ 7 files changed, 142 insertions(+) create mode 100644 Documentation/DocBook/media/v4l/dev-sdr.xml diff --git a/Documentation/DocBook/media/v4l/compat.xml b/Documentation/DocBook/media/v4l/compat.xml index c4cac6d..0b4db0e 100644 --- a/Documentation/DocBook/media/v4l/compat.xml +++ b/Documentation/DocBook/media/v4l/compat.xml @@ -2535,6 +2535,16 @@ fields changed from _s32 to _u32.

+
+ V4L2 in Linux 3.15 + + + Added Software Defined Radio (SDR) Interface. + + + +
+
Relation of V4L2 to other Linux multimedia APIs diff --git a/Documentation/DocBook/media/v4l/dev-sdr.xml b/Documentation/DocBook/media/v4l/dev-sdr.xml new file mode 100644 index 0000000..332b87f --- /dev/null +++ b/Documentation/DocBook/media/v4l/dev-sdr.xml @@ -0,0 +1,104 @@ + Software Defined Radio Interface (SDR) + + +SDR is an abbreviation of Software Defined Radio, the radio device +which uses application software for modulation or demodulation. This interface +is intended for controlling and data streaming of such devices. + + + +SDR devices are accessed through character device special files named +/dev/swradio0 to /dev/swradio255 +with major number 81 and dynamically allocated minor numbers 0 to 255. + + +
+ Querying Capabilities + + +Devices supporting the SDR receiver interface set the +V4L2_CAP_SDR_CAPTURE and +V4L2_CAP_TUNER flag in the +capabilities field of &v4l2-capability; +returned by the &VIDIOC-QUERYCAP; ioctl. That flag means the device has an +Analog to Digital Converter (ADC), which is a mandatory element for the SDR receiver. +At least one of the read/write, streaming or asynchronous I/O methods must +be supported. + +
+ +
+ Supplemental Functions + + +SDR devices can support controls, and must +support the tuner ioctls. Tuner ioctls are used +for setting the ADC sampling rate (sampling frequency) and the possible RF tuner +frequency. + + + +The V4L2_TUNER_ADC tuner type is used for ADC tuners, and +the V4L2_TUNER_RF tuner type is used for RF tuners. The +tuner index of the RF tuner (if any) must always follow the ADC tuner index. +Normally the ADC tuner is #0 and the RF tuner is #1. + + + +The &VIDIOC-S-HW-FREQ-SEEK; ioctl is not supported. + +
+ +
+ Data Format Negotiation + + +The SDR capture device uses the format ioctls to +select the capture format. Both the sampling resolution and the data streaming +format are bound to that selectable format. In addition to the basic +format ioctls, the &VIDIOC-ENUM-FMT; ioctl +must be supported as well. + + + +To use the format ioctls applications set the +type field of a &v4l2-format; to +V4L2_BUF_TYPE_SDR_CAPTURE and use the &v4l2-format-sdr; +sdr member of the fmt +union as needed per the desired operation. +Currently only the pixelformat field of +&v4l2-format-sdr; is used. The content of that field is the V4L2 fourcc code +of the data format. + + + + struct <structname>v4l2_format_sdr</structname> + + &cs-str; + + + __u32 + pixelformat + +The data format or type of compression, set by the application. This is a +little endian four character code. +V4L2 defines SDR formats in . + + + + __u8 + reserved[28] + This array is reserved for future extensions. +Drivers and applications must set it to zero. + + + +
+ + +An SDR device may support read/write +and/or streaming (memory mapping +or user pointer) I/O. + + +
diff --git a/Documentation/DocBook/media/v4l/io.xml b/Documentation/DocBook/media/v4l/io.xml index 2c4c068..1fb11e8 100644 --- a/Documentation/DocBook/media/v4l/io.xml +++ b/Documentation/DocBook/media/v4l/io.xml @@ -1005,6 +1005,12 @@ should set this to 0. Buffer for video output overlay (OSD), see . + + V4L2_BUF_TYPE_SDR_CAPTURE + 11 + Buffer for Software Defined Radio (SDR), see . + diff --git a/Documentation/DocBook/media/v4l/pixfmt.xml b/Documentation/DocBook/media/v4l/pixfmt.xml index 72d72bd..f586d34 100644 --- a/Documentation/DocBook/media/v4l/pixfmt.xml +++ b/Documentation/DocBook/media/v4l/pixfmt.xml @@ -811,6 +811,14 @@ extended control V4L2_CID_MPEG_STREAM_TYPE, see
+
+ SDR Formats + + These formats are used for SDR Capture +interface only. + +
+
Reserved Format Identifiers diff --git a/Documentation/DocBook/media/v4l/v4l2.xml b/Documentation/DocBook/media/v4l/v4l2.xml index 6bf3532..e826d1d 100644 --- a/Documentation/DocBook/media/v4l/v4l2.xml +++ b/Documentation/DocBook/media/v4l/v4l2.xml @@ -548,6 +548,7 @@ and discussions on the V4L mailing list.
&sub-dev-teletext;
&sub-dev-radio;
&sub-dev-rds;
+
&sub-dev-sdr;
&sub-dev-event;
&sub-dev-subdev;
diff --git a/Documentation/DocBook/media/v4l/vidioc-g-fmt.xml b/Documentation/DocBook/media/v4l/vidioc-g-fmt.xml index ee8f56e..f43f1a9 100644 --- a/Documentation/DocBook/media/v4l/vidioc-g-fmt.xml +++ b/Documentation/DocBook/media/v4l/vidioc-g-fmt.xml @@ -172,6 +172,13 @@ capture and output devices. + &v4l2-format-sdr; + sdr + Definition of a data format, see +, used by SDR capture devices. + + + __u8 raw_data[200] Place holder for future extensions. diff --git a/Documentation/DocBook/media/v4l/vidioc-querycap.xml b/Documentation/DocBook/media/v4l/vidioc-querycap.xml index d5a3c97..370d49d 100644 --- a/Documentation/DocBook/media/v4l/vidioc-querycap.xml +++ b/Documentation/DocBook/media/v4l/vidioc-querycap.xml @@ -296,6 +296,12 @@ modulator programming see . + V4L2_CAP_SDR_CAPTURE + 0x00100000 + The device supports the +SDR Capture interface. + + V4L2_CAP_READWRITE 0x01000000 The device supports the Date: Mon, 13 Jan 2014 22:03:12 -0300 Subject: [media] DocBook: mark SDR API as Experimental Let it be experimental still as all SDR drivers are in staging. Cc: Hans Verkuil Signed-off-by: Antti Palosaari Acked-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/v4l/compat.xml | 3 +++ Documentation/DocBook/media/v4l/dev-sdr.xml | 6 ++++++ 2 files changed, 9 insertions(+) diff --git a/Documentation/DocBook/media/v4l/compat.xml b/Documentation/DocBook/media/v4l/compat.xml index 0b4db0e..e72eaab 100644 --- a/Documentation/DocBook/media/v4l/compat.xml +++ b/Documentation/DocBook/media/v4l/compat.xml @@ -2661,6 +2661,9 @@ ioctls. Exporting DMABUF files using &VIDIOC-EXPBUF; ioctl. + + Software Defined Radio (SDR) Interface, . +
diff --git a/Documentation/DocBook/media/v4l/dev-sdr.xml b/Documentation/DocBook/media/v4l/dev-sdr.xml index 332b87f..ac9f1af 100644 --- a/Documentation/DocBook/media/v4l/dev-sdr.xml +++ b/Documentation/DocBook/media/v4l/dev-sdr.xml @@ -1,5 +1,11 @@ Software Defined Radio Interface (SDR) + + Experimental + This is an experimental + interface and may change in the future. + + SDR is an abbreviation of Software Defined Radio, the radio device which uses application software for modulation or demodulation. This interface -- cgit v1.1 From b36514da98d5b5efafefcfe4fc6a2214e7e52a7f Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Fri, 20 Dec 2013 01:52:29 -0300 Subject: [media] v4l2-framework.txt: add SDR device type Add SDR device type to v4l2-framework.txt document. Cc: Hans Verkuil Signed-off-by: Antti Palosaari Acked-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- Documentation/video4linux/v4l2-framework.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/video4linux/v4l2-framework.txt b/Documentation/video4linux/v4l2-framework.txt index 6c4866b..ae3a2cc 100644 --- a/Documentation/video4linux/v4l2-framework.txt +++ b/Documentation/video4linux/v4l2-framework.txt @@ -768,6 +768,7 @@ types exist: VFL_TYPE_GRABBER: videoX for video input/output devices VFL_TYPE_VBI: vbiX for vertical blank data (i.e. closed captions, teletext) VFL_TYPE_RADIO: radioX for radio tuners +VFL_TYPE_SDR: swradioX for Software Defined Radio tuners The last argument gives you a certain amount of control over the device device node number used (i.e. the X in videoX). Normally you will pass -1 -- cgit v1.1 From fee629e93f18a81089e3b6a5fe53b57b0d244eba Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Fri, 7 Feb 2014 11:19:37 -0300 Subject: [media] DocBook: add Antti at the V4L2 revision list Add SDR to V3.15 revlist, and add the credits to Antti. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/v4l/v4l2.xml | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/Documentation/DocBook/media/v4l/v4l2.xml b/Documentation/DocBook/media/v4l/v4l2.xml index e826d1d..61a7bb1 100644 --- a/Documentation/DocBook/media/v4l/v4l2.xml +++ b/Documentation/DocBook/media/v4l/v4l2.xml @@ -107,6 +107,16 @@ Remote Controller chapter. + + Antti + Palosaari + SDR API. + +
+ crope@iki.fi +
+ + @@ -144,10 +154,10 @@ applications. --> 3.15 2014-02-03 - hv + hv, ap Update several sections of "Common API Elements": "Opening and Closing Devices" "Querying Capabilities", "Application Priority", "Video Inputs and Outputs", "Audio Inputs and Outputs" -"Tuners and Modulators", "Video Standards" and "Digital Video (DV) Timings". +"Tuners and Modulators", "Video Standards" and "Digital Video (DV) Timings". Added SDR API. -- cgit v1.1 From 804a04e6ccbf0ad9778799f1d7684b229eebc27b Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Wed, 5 Mar 2014 14:18:59 -0300 Subject: [media] DocBook: Fix a breakage at controls.xml Some previous patch introduced this bug: /devel/v4l/patchwork/Documentation/DocBook/controls.xml:2262: parser error : attributes construct error ^ /devel/v4l/patchwork/Documentation/DocBook/controls.xml:2262: parser error : Couldn't find end of Start Tag row line 2262 ^ Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/v4l/controls.xml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/DocBook/media/v4l/controls.xml b/Documentation/DocBook/media/v4l/controls.xml index 0e1770c..b7f3feb 100644 --- a/Documentation/DocBook/media/v4l/controls.xml +++ b/Documentation/DocBook/media/v4l/controls.xml @@ -2259,7 +2259,7 @@ VBV buffer control. - + V4L2_CID_MPEG_VIDEO_MV_H_SEARCH_RANGE  integer -- cgit v1.1 From 96a5b3a869e3dc7d55bf04a48a8dca8a4025787e Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Fri, 31 Jan 2014 21:55:47 -0300 Subject: [media] xc2028: silence compiler warnings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There is now new tuner types which are not handled on that switch-case. Print error if unknown tuner type is meet. drivers/media/tuners/tuner-xc2028.c: In function ‘generic_set_freq’: drivers/media/tuners/tuner-xc2028.c:1037:2: warning: enumeration value ‘V4L2_TUNER_ADC’ not handled in switch [-Wswitch] switch (new_type) { ^ drivers/media/tuners/tuner-xc2028.c:1037:2: warning: enumeration value ‘V4L2_TUNER_RF’ not handled in switch [-Wswitch] Cc: Mauro Carvalho Chehab Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- drivers/media/tuners/tuner-xc2028.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/media/tuners/tuner-xc2028.c b/drivers/media/tuners/tuner-xc2028.c index cca508d..76a8165 100644 --- a/drivers/media/tuners/tuner-xc2028.c +++ b/drivers/media/tuners/tuner-xc2028.c @@ -1107,6 +1107,9 @@ static int generic_set_freq(struct dvb_frontend *fe, u32 freq /* in HZ */, offset += 200000; } #endif + default: + tuner_err("Unsupported tuner type %d.\n", new_type); + break; } div = (freq - offset + DIV / 2) / DIV; -- cgit v1.1 From 94b5fa6c20b7ac916e099b44cc812ac1ec6e5d3e Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Fri, 22 Nov 2013 14:20:14 -0300 Subject: [media] rtl28xxu: add module parameter to disable IR Disable IR interrupts in order to avoid SDR sample loss. IR interrupts causes some extra load for device and it seems be one reason to loss samples when sampling rate is high. Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/dvb-usb-v2/rtl28xxu.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/media/usb/dvb-usb-v2/rtl28xxu.c b/drivers/media/usb/dvb-usb-v2/rtl28xxu.c index a331af1..5e223e8 100644 --- a/drivers/media/usb/dvb-usb-v2/rtl28xxu.c +++ b/drivers/media/usb/dvb-usb-v2/rtl28xxu.c @@ -35,6 +35,9 @@ #include "tua9001.h" #include "r820t.h" +static int rtl28xxu_disable_rc; +module_param_named(disable_rc, rtl28xxu_disable_rc, int, 0644); +MODULE_PARM_DESC(disable_rc, "disable RTL2832U remote controller"); DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); static int rtl28xxu_ctrl_msg(struct dvb_usb_device *d, struct rtl28xxu_req *req) @@ -1322,6 +1325,10 @@ err: static int rtl2832u_get_rc_config(struct dvb_usb_device *d, struct dvb_usb_rc *rc) { + /* disable IR interrupts in order to avoid SDR sample loss */ + if (rtl28xxu_disable_rc) + return rtl28xx_wr_reg(d, IR_RX_IE, 0x00); + /* load empty to enable rc */ if (!rc->map_name) rc->map_name = RC_MAP_EMPTY; -- cgit v1.1 From 5791eee2647ff358e6cb11b2830c62a92e2674c7 Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Sat, 12 Oct 2013 23:45:34 -0300 Subject: [media] rtl2832: remove unused if_dvbt config parameter All used tuners has get_if_frequency() callback and that parameter is not needed and will not needed as all upcoming tuner drivers should implement get_if_frequency(). Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/rtl2832.c | 6 ------ drivers/media/dvb-frontends/rtl2832.h | 7 ------- drivers/media/usb/dvb-usb-v2/rtl28xxu.c | 2 -- 3 files changed, 15 deletions(-) diff --git a/drivers/media/dvb-frontends/rtl2832.c b/drivers/media/dvb-frontends/rtl2832.c index ff73da9..61d4ecb 100644 --- a/drivers/media/dvb-frontends/rtl2832.c +++ b/drivers/media/dvb-frontends/rtl2832.c @@ -514,12 +514,6 @@ static int rtl2832_init(struct dvb_frontend *fe) goto err; } - if (!fe->ops.tuner_ops.get_if_frequency) { - ret = rtl2832_set_if(fe, priv->cfg.if_dvbt); - if (ret) - goto err; - } - /* * r820t NIM code does a software reset here at the demod - * may not be needed, as there's already a software reset at set_params() diff --git a/drivers/media/dvb-frontends/rtl2832.h b/drivers/media/dvb-frontends/rtl2832.h index 2cfbb6a..e543081 100644 --- a/drivers/media/dvb-frontends/rtl2832.h +++ b/drivers/media/dvb-frontends/rtl2832.h @@ -38,13 +38,6 @@ struct rtl2832_config { u32 xtal; /* - * IFs for all used modes. - * Hz - * 4570000, 4571429, 36000000, 36125000, 36166667, 44000000 - */ - u32 if_dvbt; - - /* * tuner * XXX: This must be keep sync with dvb_usb_rtl28xxu demod driver. */ diff --git a/drivers/media/usb/dvb-usb-v2/rtl28xxu.c b/drivers/media/usb/dvb-usb-v2/rtl28xxu.c index 5e223e8..c6ff39e 100644 --- a/drivers/media/usb/dvb-usb-v2/rtl28xxu.c +++ b/drivers/media/usb/dvb-usb-v2/rtl28xxu.c @@ -589,14 +589,12 @@ err: static struct rtl2832_config rtl28xxu_rtl2832_fc0012_config = { .i2c_addr = 0x10, /* 0x20 */ .xtal = 28800000, - .if_dvbt = 0, .tuner = TUNER_RTL2832_FC0012 }; static struct rtl2832_config rtl28xxu_rtl2832_fc0013_config = { .i2c_addr = 0x10, /* 0x20 */ .xtal = 28800000, - .if_dvbt = 0, .tuner = TUNER_RTL2832_FC0013 }; -- cgit v1.1 From 3ca2418d707c9eeafa76f6096eb8e06d1cfa8bdb Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Sun, 13 Oct 2013 00:06:44 -0300 Subject: [media] rtl2832: style changes and minor cleanup Most of those were reported by checkpatch.pl... debug module parameter is not used anywhere so remove it. Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/rtl2832.c | 26 +++++++--------- drivers/media/dvb-frontends/rtl2832.h | 2 +- drivers/media/dvb-frontends/rtl2832_priv.h | 50 +++++++++++++++--------------- 3 files changed, 38 insertions(+), 40 deletions(-) diff --git a/drivers/media/dvb-frontends/rtl2832.c b/drivers/media/dvb-frontends/rtl2832.c index 61d4ecb..00e63b9 100644 --- a/drivers/media/dvb-frontends/rtl2832.c +++ b/drivers/media/dvb-frontends/rtl2832.c @@ -24,11 +24,6 @@ /* Max transfer size done by I2C transfer functions */ #define MAX_XFER_SIZE 64 - -int rtl2832_debug; -module_param_named(debug, rtl2832_debug, int, 0644); -MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); - #define REG_MASK(b) (BIT(b + 1) - 1) static const struct rtl2832_reg_entry registers[] = { @@ -189,8 +184,9 @@ static int rtl2832_wr(struct rtl2832_priv *priv, u8 reg, u8 *val, int len) if (ret == 1) { ret = 0; } else { - dev_warn(&priv->i2c->dev, "%s: i2c wr failed=%d reg=%02x " \ - "len=%d\n", KBUILD_MODNAME, ret, reg, len); + dev_warn(&priv->i2c->dev, + "%s: i2c wr failed=%d reg=%02x len=%d\n", + KBUILD_MODNAME, ret, reg, len); ret = -EREMOTEIO; } return ret; @@ -218,8 +214,9 @@ static int rtl2832_rd(struct rtl2832_priv *priv, u8 reg, u8 *val, int len) if (ret == 2) { ret = 0; } else { - dev_warn(&priv->i2c->dev, "%s: i2c rd failed=%d reg=%02x " \ - "len=%d\n", KBUILD_MODNAME, ret, reg, len); + dev_warn(&priv->i2c->dev, + "%s: i2c rd failed=%d reg=%02x len=%d\n", + KBUILD_MODNAME, ret, reg, len); ret = -EREMOTEIO; } return ret; @@ -417,7 +414,7 @@ static int rtl2832_set_if(struct dvb_frontend *fe, u32 if_freq) ret = rtl2832_wr_demod_reg(priv, DVBT_PSET_IFFREQ, pset_iffreq); - return (ret); + return ret; } static int rtl2832_init(struct dvb_frontend *fe) @@ -516,7 +513,8 @@ static int rtl2832_init(struct dvb_frontend *fe) /* * r820t NIM code does a software reset here at the demod - - * may not be needed, as there's already a software reset at set_params() + * may not be needed, as there's already a software reset at + * set_params() */ #if 1 /* soft reset */ @@ -593,9 +591,9 @@ static int rtl2832_set_frontend(struct dvb_frontend *fe) }; - dev_dbg(&priv->i2c->dev, "%s: frequency=%d bandwidth_hz=%d " \ - "inversion=%d\n", __func__, c->frequency, - c->bandwidth_hz, c->inversion); + dev_dbg(&priv->i2c->dev, + "%s: frequency=%d bandwidth_hz=%d inversion=%d\n", + __func__, c->frequency, c->bandwidth_hz, c->inversion); /* program tuner */ if (fe->ops.tuner_ops.set_params) diff --git a/drivers/media/dvb-frontends/rtl2832.h b/drivers/media/dvb-frontends/rtl2832.h index e543081..fa4e5f6 100644 --- a/drivers/media/dvb-frontends/rtl2832.h +++ b/drivers/media/dvb-frontends/rtl2832.h @@ -51,7 +51,7 @@ struct rtl2832_config { }; #if IS_ENABLED(CONFIG_DVB_RTL2832) -extern struct dvb_frontend *rtl2832_attach( +struct dvb_frontend *rtl2832_attach( const struct rtl2832_config *cfg, struct i2c_adapter *i2c ); diff --git a/drivers/media/dvb-frontends/rtl2832_priv.h b/drivers/media/dvb-frontends/rtl2832_priv.h index b5f2b80..4c845af 100644 --- a/drivers/media/dvb-frontends/rtl2832_priv.h +++ b/drivers/media/dvb-frontends/rtl2832_priv.h @@ -267,7 +267,7 @@ static const struct rtl2832_reg_value rtl2832_tuner_init_tua9001[] = { {DVBT_OPT_ADC_IQ, 0x1}, {DVBT_AD_AVI, 0x0}, {DVBT_AD_AVQ, 0x0}, - {DVBT_SPEC_INV, 0x0}, + {DVBT_SPEC_INV, 0x0}, }; static const struct rtl2832_reg_value rtl2832_tuner_init_fc0012[] = { @@ -301,7 +301,7 @@ static const struct rtl2832_reg_value rtl2832_tuner_init_fc0012[] = { {DVBT_GI_PGA_STATE, 0x0}, {DVBT_EN_AGC_PGA, 0x1}, {DVBT_IF_AGC_MAN, 0x0}, - {DVBT_SPEC_INV, 0x0}, + {DVBT_SPEC_INV, 0x0}, }; static const struct rtl2832_reg_value rtl2832_tuner_init_e4000[] = { @@ -339,32 +339,32 @@ static const struct rtl2832_reg_value rtl2832_tuner_init_e4000[] = { {DVBT_REG_MONSEL, 0x1}, {DVBT_REG_MON, 0x1}, {DVBT_REG_4MSEL, 0x0}, - {DVBT_SPEC_INV, 0x0}, + {DVBT_SPEC_INV, 0x0}, }; static const struct rtl2832_reg_value rtl2832_tuner_init_r820t[] = { - {DVBT_DAGC_TRG_VAL, 0x39}, - {DVBT_AGC_TARG_VAL_0, 0x0}, - {DVBT_AGC_TARG_VAL_8_1, 0x40}, - {DVBT_AAGC_LOOP_GAIN, 0x16}, - {DVBT_LOOP_GAIN2_3_0, 0x8}, - {DVBT_LOOP_GAIN2_4, 0x1}, - {DVBT_LOOP_GAIN3, 0x18}, - {DVBT_VTOP1, 0x35}, - {DVBT_VTOP2, 0x21}, - {DVBT_VTOP3, 0x21}, - {DVBT_KRF1, 0x0}, - {DVBT_KRF2, 0x40}, - {DVBT_KRF3, 0x10}, - {DVBT_KRF4, 0x10}, - {DVBT_IF_AGC_MIN, 0x80}, - {DVBT_IF_AGC_MAX, 0x7f}, - {DVBT_RF_AGC_MIN, 0x80}, - {DVBT_RF_AGC_MAX, 0x7f}, - {DVBT_POLAR_RF_AGC, 0x0}, - {DVBT_POLAR_IF_AGC, 0x0}, - {DVBT_AD7_SETTING, 0xe9f4}, - {DVBT_SPEC_INV, 0x1}, + {DVBT_DAGC_TRG_VAL, 0x39}, + {DVBT_AGC_TARG_VAL_0, 0x0}, + {DVBT_AGC_TARG_VAL_8_1, 0x40}, + {DVBT_AAGC_LOOP_GAIN, 0x16}, + {DVBT_LOOP_GAIN2_3_0, 0x8}, + {DVBT_LOOP_GAIN2_4, 0x1}, + {DVBT_LOOP_GAIN3, 0x18}, + {DVBT_VTOP1, 0x35}, + {DVBT_VTOP2, 0x21}, + {DVBT_VTOP3, 0x21}, + {DVBT_KRF1, 0x0}, + {DVBT_KRF2, 0x40}, + {DVBT_KRF3, 0x10}, + {DVBT_KRF4, 0x10}, + {DVBT_IF_AGC_MIN, 0x80}, + {DVBT_IF_AGC_MAX, 0x7f}, + {DVBT_RF_AGC_MIN, 0x80}, + {DVBT_RF_AGC_MAX, 0x7f}, + {DVBT_POLAR_RF_AGC, 0x0}, + {DVBT_POLAR_IF_AGC, 0x0}, + {DVBT_AD7_SETTING, 0xe9f4}, + {DVBT_SPEC_INV, 0x1}, }; #endif /* RTL2832_PRIV_H */ -- cgit v1.1 From 8823f0288d345a26b27502c71f8ca3d05b4ac013 Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Tue, 26 Nov 2013 12:53:46 -0300 Subject: [media] rtl2832: provide muxed I2C adapter RTL2832 provides gated / repeater I2C adapter for tuner. Implement it as a muxed I2C adapter. Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/Kconfig | 2 +- drivers/media/dvb-frontends/rtl2832.c | 26 ++++++++++++++++++++++++++ drivers/media/dvb-frontends/rtl2832.h | 13 +++++++++++++ drivers/media/dvb-frontends/rtl2832_priv.h | 2 ++ 4 files changed, 42 insertions(+), 1 deletion(-) diff --git a/drivers/media/dvb-frontends/Kconfig b/drivers/media/dvb-frontends/Kconfig index 611c794..025fc54 100644 --- a/drivers/media/dvb-frontends/Kconfig +++ b/drivers/media/dvb-frontends/Kconfig @@ -441,7 +441,7 @@ config DVB_RTL2830 config DVB_RTL2832 tristate "Realtek RTL2832 DVB-T" - depends on DVB_CORE && I2C + depends on DVB_CORE && I2C && I2C_MUX default m if !MEDIA_SUBDRV_AUTOSELECT help Say Y when you want to support this frontend. diff --git a/drivers/media/dvb-frontends/rtl2832.c b/drivers/media/dvb-frontends/rtl2832.c index 00e63b9..dc46cf08 100644 --- a/drivers/media/dvb-frontends/rtl2832.c +++ b/drivers/media/dvb-frontends/rtl2832.c @@ -891,9 +891,29 @@ static void rtl2832_release(struct dvb_frontend *fe) struct rtl2832_priv *priv = fe->demodulator_priv; dev_dbg(&priv->i2c->dev, "%s:\n", __func__); + i2c_del_mux_adapter(priv->i2c_adapter); kfree(priv); } +static int rtl2832_select(struct i2c_adapter *adap, void *mux_priv, u32 chan) +{ + struct rtl2832_priv *priv = mux_priv; + return rtl2832_i2c_gate_ctrl(&priv->fe, 1); +} + +static int rtl2832_deselect(struct i2c_adapter *adap, void *mux_priv, u32 chan) +{ + struct rtl2832_priv *priv = mux_priv; + return rtl2832_i2c_gate_ctrl(&priv->fe, 0); +} + +struct i2c_adapter *rtl2832_get_i2c_adapter(struct dvb_frontend *fe) +{ + struct rtl2832_priv *priv = fe->demodulator_priv; + return priv->i2c_adapter; +} +EXPORT_SYMBOL(rtl2832_get_i2c_adapter); + struct dvb_frontend *rtl2832_attach(const struct rtl2832_config *cfg, struct i2c_adapter *i2c) { @@ -918,6 +938,12 @@ struct dvb_frontend *rtl2832_attach(const struct rtl2832_config *cfg, if (ret) goto err; + /* create muxed i2c adapter */ + priv->i2c_adapter = i2c_add_mux_adapter(i2c, &i2c->dev, priv, 0, 0, 0, + rtl2832_select, rtl2832_deselect); + if (priv->i2c_adapter == NULL) + goto err; + /* create dvb_frontend */ memcpy(&priv->fe.ops, &rtl2832_ops, sizeof(struct dvb_frontend_ops)); priv->fe.demodulator_priv = priv; diff --git a/drivers/media/dvb-frontends/rtl2832.h b/drivers/media/dvb-frontends/rtl2832.h index fa4e5f6..a9202d7 100644 --- a/drivers/media/dvb-frontends/rtl2832.h +++ b/drivers/media/dvb-frontends/rtl2832.h @@ -55,7 +55,13 @@ struct dvb_frontend *rtl2832_attach( const struct rtl2832_config *cfg, struct i2c_adapter *i2c ); + +extern struct i2c_adapter *rtl2832_get_i2c_adapter( + struct dvb_frontend *fe +); + #else + static inline struct dvb_frontend *rtl2832_attach( const struct rtl2832_config *config, struct i2c_adapter *i2c @@ -64,6 +70,13 @@ static inline struct dvb_frontend *rtl2832_attach( pr_warn("%s: driver disabled by Kconfig\n", __func__); return NULL; } + +static inline struct i2c_adapter *rtl2832_get_i2c_adapter( + struct dvb_frontend *fe +) +{ + return NULL; +} #endif diff --git a/drivers/media/dvb-frontends/rtl2832_priv.h b/drivers/media/dvb-frontends/rtl2832_priv.h index 4c845af..ec26c92 100644 --- a/drivers/media/dvb-frontends/rtl2832_priv.h +++ b/drivers/media/dvb-frontends/rtl2832_priv.h @@ -23,9 +23,11 @@ #include "dvb_frontend.h" #include "rtl2832.h" +#include struct rtl2832_priv { struct i2c_adapter *i2c; + struct i2c_adapter *i2c_adapter; struct dvb_frontend fe; struct rtl2832_config cfg; -- cgit v1.1 From 0ea872d43e9a68d1b540f382d139e9d99d9f8301 Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Tue, 3 Dec 2013 18:19:39 -0300 Subject: [media] rtl2832: add muxed I2C adapter for demod itself There was a deadlock between master I2C adapter and muxed I2C adapter. Implement two I2C muxed I2C adapters and leave master alone, just only for offering I2C adapter for these mux adapters. Reported-by: Luis Alves Reported-by: Benjamin Larsson Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/rtl2832.c | 71 ++++++++++++++++++++++++------ drivers/media/dvb-frontends/rtl2832_priv.h | 1 + 2 files changed, 58 insertions(+), 14 deletions(-) diff --git a/drivers/media/dvb-frontends/rtl2832.c b/drivers/media/dvb-frontends/rtl2832.c index dc46cf08..c0366a8 100644 --- a/drivers/media/dvb-frontends/rtl2832.c +++ b/drivers/media/dvb-frontends/rtl2832.c @@ -180,7 +180,7 @@ static int rtl2832_wr(struct rtl2832_priv *priv, u8 reg, u8 *val, int len) buf[0] = reg; memcpy(&buf[1], val, len); - ret = i2c_transfer(priv->i2c, msg, 1); + ret = i2c_transfer(priv->i2c_adapter, msg, 1); if (ret == 1) { ret = 0; } else { @@ -210,7 +210,7 @@ static int rtl2832_rd(struct rtl2832_priv *priv, u8 reg, u8 *val, int len) } }; - ret = i2c_transfer(priv->i2c, msg, 2); + ret = i2c_transfer(priv->i2c_adapter, msg, 2); if (ret == 2) { ret = 0; } else { @@ -891,26 +891,61 @@ static void rtl2832_release(struct dvb_frontend *fe) struct rtl2832_priv *priv = fe->demodulator_priv; dev_dbg(&priv->i2c->dev, "%s:\n", __func__); + i2c_del_mux_adapter(priv->i2c_adapter_tuner); i2c_del_mux_adapter(priv->i2c_adapter); kfree(priv); } -static int rtl2832_select(struct i2c_adapter *adap, void *mux_priv, u32 chan) +static int rtl2832_select(struct i2c_adapter *adap, void *mux_priv, u32 chan_id) { struct rtl2832_priv *priv = mux_priv; - return rtl2832_i2c_gate_ctrl(&priv->fe, 1); -} + int ret; + u8 buf[2]; + struct i2c_msg msg[1] = { + { + .addr = priv->cfg.i2c_addr, + .flags = 0, + .len = sizeof(buf), + .buf = buf, + } + }; -static int rtl2832_deselect(struct i2c_adapter *adap, void *mux_priv, u32 chan) -{ - struct rtl2832_priv *priv = mux_priv; - return rtl2832_i2c_gate_ctrl(&priv->fe, 0); + if (priv->i2c_gate_state == chan_id) + return 0; + + /* select reg bank 1 */ + buf[0] = 0x00; + buf[1] = 0x01; + + ret = i2c_transfer(adap, msg, 1); + if (ret != 1) + goto err; + + priv->page = 1; + + /* open or close I2C repeater gate */ + buf[0] = 0x01; + if (chan_id == 1) + buf[1] = 0x18; /* open */ + else + buf[1] = 0x10; /* close */ + + ret = i2c_transfer(adap, msg, 1); + if (ret != 1) + goto err; + + priv->i2c_gate_state = chan_id; + + return 0; +err: + dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); + return -EREMOTEIO; } struct i2c_adapter *rtl2832_get_i2c_adapter(struct dvb_frontend *fe) { struct rtl2832_priv *priv = fe->demodulator_priv; - return priv->i2c_adapter; + return priv->i2c_adapter_tuner; } EXPORT_SYMBOL(rtl2832_get_i2c_adapter); @@ -933,15 +968,21 @@ struct dvb_frontend *rtl2832_attach(const struct rtl2832_config *cfg, priv->tuner = cfg->tuner; memcpy(&priv->cfg, cfg, sizeof(struct rtl2832_config)); + /* create muxed i2c adapter for demod itself */ + priv->i2c_adapter = i2c_add_mux_adapter(i2c, &i2c->dev, priv, 0, 0, 0, + rtl2832_select, NULL); + if (priv->i2c_adapter == NULL) + goto err; + /* check if the demod is there */ ret = rtl2832_rd_reg(priv, 0x00, 0x0, &tmp); if (ret) goto err; - /* create muxed i2c adapter */ - priv->i2c_adapter = i2c_add_mux_adapter(i2c, &i2c->dev, priv, 0, 0, 0, - rtl2832_select, rtl2832_deselect); - if (priv->i2c_adapter == NULL) + /* create muxed i2c adapter for demod tuner bus */ + priv->i2c_adapter_tuner = i2c_add_mux_adapter(i2c, &i2c->dev, priv, + 0, 1, 0, rtl2832_select, NULL); + if (priv->i2c_adapter_tuner == NULL) goto err; /* create dvb_frontend */ @@ -954,6 +995,8 @@ struct dvb_frontend *rtl2832_attach(const struct rtl2832_config *cfg, return &priv->fe; err: dev_dbg(&i2c->dev, "%s: failed=%d\n", __func__, ret); + if (priv && priv->i2c_adapter) + i2c_del_mux_adapter(priv->i2c_adapter); kfree(priv); return NULL; } diff --git a/drivers/media/dvb-frontends/rtl2832_priv.h b/drivers/media/dvb-frontends/rtl2832_priv.h index ec26c92..8b7c1ae 100644 --- a/drivers/media/dvb-frontends/rtl2832_priv.h +++ b/drivers/media/dvb-frontends/rtl2832_priv.h @@ -28,6 +28,7 @@ struct rtl2832_priv { struct i2c_adapter *i2c; struct i2c_adapter *i2c_adapter; + struct i2c_adapter *i2c_adapter_tuner; struct dvb_frontend fe; struct rtl2832_config cfg; -- cgit v1.1 From 0db5c800aa460c9f3cb142d65b5893c47ddcecb8 Mon Sep 17 00:00:00 2001 From: Luis Alves Date: Wed, 4 Dec 2013 20:21:22 -0300 Subject: [media] rtl2832: Fix deadlock on i2c mux select function Signed-off-by: Luis Alves Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/rtl2832.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/media/dvb-frontends/rtl2832.c b/drivers/media/dvb-frontends/rtl2832.c index c0366a8..cfc5438 100644 --- a/drivers/media/dvb-frontends/rtl2832.c +++ b/drivers/media/dvb-frontends/rtl2832.c @@ -917,7 +917,7 @@ static int rtl2832_select(struct i2c_adapter *adap, void *mux_priv, u32 chan_id) buf[0] = 0x00; buf[1] = 0x01; - ret = i2c_transfer(adap, msg, 1); + ret = __i2c_transfer(adap, msg, 1); if (ret != 1) goto err; @@ -930,7 +930,7 @@ static int rtl2832_select(struct i2c_adapter *adap, void *mux_priv, u32 chan_id) else buf[1] = 0x10; /* close */ - ret = i2c_transfer(adap, msg, 1); + ret = __i2c_transfer(adap, msg, 1); if (ret != 1) goto err; -- cgit v1.1 From 92d20d9fd13a2616294dc804ba3bb78312b84850 Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Sat, 8 Feb 2014 03:50:04 -0300 Subject: [media] rtl2832: implement delayed I2C gate close Delay possible I2C gate close a little bit in order to see if there is next message coming to tuner in a sequence. Also, export private muxed I2C adapter. That is aimed only for SDR extension module as SDR belongs to same RTL2832 physical I2C bus (it is physically property of RTL2832, whilst it is own kernel module). Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/rtl2832.c | 92 +++++++++++++++++++++++++++++- drivers/media/dvb-frontends/rtl2832.h | 12 ++++ drivers/media/dvb-frontends/rtl2832_priv.h | 1 + 3 files changed, 102 insertions(+), 3 deletions(-) diff --git a/drivers/media/dvb-frontends/rtl2832.c b/drivers/media/dvb-frontends/rtl2832.c index cfc5438..fdbed35 100644 --- a/drivers/media/dvb-frontends/rtl2832.c +++ b/drivers/media/dvb-frontends/rtl2832.c @@ -891,16 +891,65 @@ static void rtl2832_release(struct dvb_frontend *fe) struct rtl2832_priv *priv = fe->demodulator_priv; dev_dbg(&priv->i2c->dev, "%s:\n", __func__); + cancel_delayed_work_sync(&priv->i2c_gate_work); i2c_del_mux_adapter(priv->i2c_adapter_tuner); i2c_del_mux_adapter(priv->i2c_adapter); kfree(priv); } +/* + * Delay mechanism to avoid unneeded I2C gate open / close. Gate close is + * delayed here a little bit in order to see if there is sequence of I2C + * messages sent to same I2C bus. + * We must use unlocked version of __i2c_transfer() in order to avoid deadlock + * as lock is already taken by calling muxed i2c_transfer(). + */ +static void rtl2832_i2c_gate_work(struct work_struct *work) +{ + struct rtl2832_priv *priv = container_of(work, + struct rtl2832_priv, i2c_gate_work.work); + struct i2c_adapter *adap = priv->i2c; + int ret; + u8 buf[2]; + struct i2c_msg msg[1] = { + { + .addr = priv->cfg.i2c_addr, + .flags = 0, + .len = sizeof(buf), + .buf = buf, + } + }; + + /* select reg bank 1 */ + buf[0] = 0x00; + buf[1] = 0x01; + ret = __i2c_transfer(adap, msg, 1); + if (ret != 1) + goto err; + + priv->page = 1; + + /* close I2C repeater gate */ + buf[0] = 0x01; + buf[1] = 0x10; + ret = __i2c_transfer(adap, msg, 1); + if (ret != 1) + goto err; + + priv->i2c_gate_state = 0; + + return; +err: + dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); + + return; +} + static int rtl2832_select(struct i2c_adapter *adap, void *mux_priv, u32 chan_id) { struct rtl2832_priv *priv = mux_priv; int ret; - u8 buf[2]; + u8 buf[2], val; struct i2c_msg msg[1] = { { .addr = priv->cfg.i2c_addr, @@ -909,6 +958,22 @@ static int rtl2832_select(struct i2c_adapter *adap, void *mux_priv, u32 chan_id) .buf = buf, } }; + struct i2c_msg msg_rd[2] = { + { + .addr = priv->cfg.i2c_addr, + .flags = 0, + .len = 1, + .buf = "\x01", + }, { + .addr = priv->cfg.i2c_addr, + .flags = I2C_M_RD, + .len = 1, + .buf = &val, + } + }; + + /* terminate possible gate closing */ + cancel_delayed_work_sync(&priv->i2c_gate_work); if (priv->i2c_gate_state == chan_id) return 0; @@ -916,13 +981,17 @@ static int rtl2832_select(struct i2c_adapter *adap, void *mux_priv, u32 chan_id) /* select reg bank 1 */ buf[0] = 0x00; buf[1] = 0x01; - ret = __i2c_transfer(adap, msg, 1); if (ret != 1) goto err; priv->page = 1; + /* we must read that register, otherwise there will be errors */ + ret = __i2c_transfer(adap, msg_rd, 2); + if (ret != 2) + goto err; + /* open or close I2C repeater gate */ buf[0] = 0x01; if (chan_id == 1) @@ -939,9 +1008,18 @@ static int rtl2832_select(struct i2c_adapter *adap, void *mux_priv, u32 chan_id) return 0; err: dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); + return -EREMOTEIO; } +static int rtl2832_deselect(struct i2c_adapter *adap, void *mux_priv, + u32 chan_id) +{ + struct rtl2832_priv *priv = mux_priv; + schedule_delayed_work(&priv->i2c_gate_work, usecs_to_jiffies(100)); + return 0; +} + struct i2c_adapter *rtl2832_get_i2c_adapter(struct dvb_frontend *fe) { struct rtl2832_priv *priv = fe->demodulator_priv; @@ -949,6 +1027,13 @@ struct i2c_adapter *rtl2832_get_i2c_adapter(struct dvb_frontend *fe) } EXPORT_SYMBOL(rtl2832_get_i2c_adapter); +struct i2c_adapter *rtl2832_get_private_i2c_adapter(struct dvb_frontend *fe) +{ + struct rtl2832_priv *priv = fe->demodulator_priv; + return priv->i2c_adapter; +} +EXPORT_SYMBOL(rtl2832_get_private_i2c_adapter); + struct dvb_frontend *rtl2832_attach(const struct rtl2832_config *cfg, struct i2c_adapter *i2c) { @@ -967,6 +1052,7 @@ struct dvb_frontend *rtl2832_attach(const struct rtl2832_config *cfg, priv->i2c = i2c; priv->tuner = cfg->tuner; memcpy(&priv->cfg, cfg, sizeof(struct rtl2832_config)); + INIT_DELAYED_WORK(&priv->i2c_gate_work, rtl2832_i2c_gate_work); /* create muxed i2c adapter for demod itself */ priv->i2c_adapter = i2c_add_mux_adapter(i2c, &i2c->dev, priv, 0, 0, 0, @@ -981,7 +1067,7 @@ struct dvb_frontend *rtl2832_attach(const struct rtl2832_config *cfg, /* create muxed i2c adapter for demod tuner bus */ priv->i2c_adapter_tuner = i2c_add_mux_adapter(i2c, &i2c->dev, priv, - 0, 1, 0, rtl2832_select, NULL); + 0, 1, 0, rtl2832_select, rtl2832_deselect); if (priv->i2c_adapter_tuner == NULL) goto err; diff --git a/drivers/media/dvb-frontends/rtl2832.h b/drivers/media/dvb-frontends/rtl2832.h index a9202d7..cb3b6b0 100644 --- a/drivers/media/dvb-frontends/rtl2832.h +++ b/drivers/media/dvb-frontends/rtl2832.h @@ -60,6 +60,10 @@ extern struct i2c_adapter *rtl2832_get_i2c_adapter( struct dvb_frontend *fe ); +extern struct i2c_adapter *rtl2832_get_private_i2c_adapter( + struct dvb_frontend *fe +); + #else static inline struct dvb_frontend *rtl2832_attach( @@ -77,6 +81,14 @@ static inline struct i2c_adapter *rtl2832_get_i2c_adapter( { return NULL; } + +static inline struct i2c_adapter *rtl2832_get_private_i2c_adapter( + struct dvb_frontend *fe +) +{ + return NULL; +} + #endif diff --git a/drivers/media/dvb-frontends/rtl2832_priv.h b/drivers/media/dvb-frontends/rtl2832_priv.h index 8b7c1ae..ae469f0 100644 --- a/drivers/media/dvb-frontends/rtl2832_priv.h +++ b/drivers/media/dvb-frontends/rtl2832_priv.h @@ -37,6 +37,7 @@ struct rtl2832_priv { u8 tuner; u8 page; /* active register page */ + struct delayed_work i2c_gate_work; }; struct rtl2832_reg_entry { -- cgit v1.1 From 951d9953c4e6201fd0d1264275c93a165cb2fa8d Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Fri, 31 Jan 2014 21:27:19 -0300 Subject: [media] DocBook: media: document V4L2_CTRL_CLASS_RF_TUNER It is class for RF tuner specific controls, like gain controls, filters, signal strength. Cc: Hans Verkuil Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/v4l/vidioc-g-ext-ctrls.xml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/DocBook/media/v4l/vidioc-g-ext-ctrls.xml b/Documentation/DocBook/media/v4l/vidioc-g-ext-ctrls.xml index b3bb957..e9f6735 100644 --- a/Documentation/DocBook/media/v4l/vidioc-g-ext-ctrls.xml +++ b/Documentation/DocBook/media/v4l/vidioc-g-ext-ctrls.xml @@ -327,7 +327,12 @@ These controls are described in . - + + V4L2_CTRL_CLASS_RF_TUNER + 0xa20000 + The class containing RF tuner controls. +These controls are described in . + -- cgit v1.1 From 851897a4adc42ad7b6327e4c64f599c07a6c5ebb Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Thu, 30 Jan 2014 00:00:10 -0300 Subject: [media] DocBook: document RF tuner gain controls Add documentation for LNA, mixer and IF gain controls. These controls are RF tuner specific. Signed-off-by: Antti Palosaari Acked-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/v4l/controls.xml | 91 ++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) diff --git a/Documentation/DocBook/media/v4l/controls.xml b/Documentation/DocBook/media/v4l/controls.xml index b7f3feb..28bf173 100644 --- a/Documentation/DocBook/media/v4l/controls.xml +++ b/Documentation/DocBook/media/v4l/controls.xml @@ -4991,4 +4991,95 @@ defines possible values for de-emphasis. Here they are: + +
+ RF Tuner Control Reference + + The RF Tuner (RF_TUNER) class includes controls for common features +of devices having RF tuner. + + + RF_TUNER Control IDs + + + + + + + + + + + ID + Type + + + Description + + + + + + V4L2_CID_RF_TUNER_CLASS  + class + The RF_TUNER class +descriptor. Calling &VIDIOC-QUERYCTRL; for this control will return a +description of this control class. + + + V4L2_CID_RF_TUNER_LNA_GAIN_AUTO  + boolean + + + Enables/disables LNA automatic gain control (AGC) + + + V4L2_CID_RF_TUNER_MIXER_GAIN_AUTO  + boolean + + + Enables/disables mixer automatic gain control (AGC) + + + V4L2_CID_RF_TUNER_IF_GAIN_AUTO  + boolean + + + Enables/disables IF automatic gain control (AGC) + + + V4L2_CID_RF_TUNER_LNA_GAIN  + integer + + + LNA (low noise amplifier) gain is first +gain stage on the RF tuner signal path. It is located very close to tuner +antenna input. Used when V4L2_CID_RF_TUNER_LNA_GAIN_AUTO is not set. +The range and step are driver-specific. + + + V4L2_CID_RF_TUNER_MIXER_GAIN  + integer + + + Mixer gain is second gain stage on the RF +tuner signal path. It is located inside mixer block, where RF signal is +down-converted by the mixer. Used when V4L2_CID_RF_TUNER_MIXER_GAIN_AUTO +is not set. The range and step are driver-specific. + + + V4L2_CID_RF_TUNER_IF_GAIN  + integer + + + IF gain is last gain stage on the RF tuner +signal path. It is located on output of RF tuner. It controls signal level of +intermediate frequency output or baseband output. Used when +V4L2_CID_RF_TUNER_IF_GAIN_AUTO is not set. The range and step are +driver-specific. + + + +
+
-- cgit v1.1 From 80807fada4398d11ebd2bb28b3b49ca6a59e1260 Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Fri, 24 Jan 2014 23:44:26 -0300 Subject: [media] v4l: add RF tuner gain controls Modern silicon RF tuners used nowadays has many controllable gain stages on signal path. Usually, but not always, there is at least 3 gain stages. Also on some cases there could be multiple gain stages within the ones specified here. However, I think that having these three controllable gain stages offers enough fine-tuning for real use cases. 1) LNA gain. That is first gain just after antenna input. 2) Mixer gain. It is located quite middle of the signal path, where RF signal is down-converted to IF/BB. 3) IF gain. That is last gain in order to adjust output signal level to optimal level for receiving party (usually demodulator ADC). Each gain stage could be set rather often both manual or automatic (AGC) mode. Due to that add separate controls for controlling operation mode. Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- drivers/media/v4l2-core/v4l2-ctrls.c | 15 +++++++++++++++ include/uapi/linux/v4l2-controls.h | 11 +++++++++++ 2 files changed, 26 insertions(+) diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c index e9e12c4..1168f68 100644 --- a/drivers/media/v4l2-core/v4l2-ctrls.c +++ b/drivers/media/v4l2-core/v4l2-ctrls.c @@ -859,6 +859,14 @@ const char *v4l2_ctrl_get_name(u32 id) case V4L2_CID_FM_RX_CLASS: return "FM Radio Receiver Controls"; case V4L2_CID_TUNE_DEEMPHASIS: return "De-Emphasis"; case V4L2_CID_RDS_RECEPTION: return "RDS Reception"; + + case V4L2_CID_RF_TUNER_CLASS: return "RF Tuner Controls"; + case V4L2_CID_RF_TUNER_LNA_GAIN_AUTO: return "LNA Gain, Auto"; + case V4L2_CID_RF_TUNER_LNA_GAIN: return "LNA Gain"; + case V4L2_CID_RF_TUNER_MIXER_GAIN_AUTO: return "Mixer Gain, Auto"; + case V4L2_CID_RF_TUNER_MIXER_GAIN: return "Mixer Gain"; + case V4L2_CID_RF_TUNER_IF_GAIN_AUTO: return "IF Gain, Auto"; + case V4L2_CID_RF_TUNER_IF_GAIN: return "IF Gain"; default: return NULL; } @@ -908,6 +916,9 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, case V4L2_CID_WIDE_DYNAMIC_RANGE: case V4L2_CID_IMAGE_STABILIZATION: case V4L2_CID_RDS_RECEPTION: + case V4L2_CID_RF_TUNER_LNA_GAIN_AUTO: + case V4L2_CID_RF_TUNER_MIXER_GAIN_AUTO: + case V4L2_CID_RF_TUNER_IF_GAIN_AUTO: *type = V4L2_CTRL_TYPE_BOOLEAN; *min = 0; *max = *step = 1; @@ -997,6 +1008,7 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, case V4L2_CID_IMAGE_PROC_CLASS: case V4L2_CID_DV_CLASS: case V4L2_CID_FM_RX_CLASS: + case V4L2_CID_RF_TUNER_CLASS: *type = V4L2_CTRL_TYPE_CTRL_CLASS; /* You can neither read not write these */ *flags |= V4L2_CTRL_FLAG_READ_ONLY | V4L2_CTRL_FLAG_WRITE_ONLY; @@ -1069,6 +1081,9 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, case V4L2_CID_PILOT_TONE_FREQUENCY: case V4L2_CID_TUNE_POWER_LEVEL: case V4L2_CID_TUNE_ANTENNA_CAPACITOR: + case V4L2_CID_RF_TUNER_LNA_GAIN: + case V4L2_CID_RF_TUNER_MIXER_GAIN: + case V4L2_CID_RF_TUNER_IF_GAIN: *flags |= V4L2_CTRL_FLAG_SLIDER; break; case V4L2_CID_PAN_RELATIVE: diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h index cda6fa0..e97101c 100644 --- a/include/uapi/linux/v4l2-controls.h +++ b/include/uapi/linux/v4l2-controls.h @@ -60,6 +60,7 @@ #define V4L2_CTRL_CLASS_IMAGE_PROC 0x009f0000 /* Image processing controls */ #define V4L2_CTRL_CLASS_DV 0x00a00000 /* Digital Video controls */ #define V4L2_CTRL_CLASS_FM_RX 0x00a10000 /* FM Receiver controls */ +#define V4L2_CTRL_CLASS_RF_TUNER 0x00a20000 /* RF tuner controls */ /* User-class control IDs */ @@ -897,4 +898,14 @@ enum v4l2_deemphasis { #define V4L2_CID_RDS_RECEPTION (V4L2_CID_FM_RX_CLASS_BASE + 2) +#define V4L2_CID_RF_TUNER_CLASS_BASE (V4L2_CTRL_CLASS_RF_TUNER | 0x900) +#define V4L2_CID_RF_TUNER_CLASS (V4L2_CTRL_CLASS_RF_TUNER | 1) + +#define V4L2_CID_RF_TUNER_LNA_GAIN_AUTO (V4L2_CID_RF_TUNER_CLASS_BASE + 1) +#define V4L2_CID_RF_TUNER_LNA_GAIN (V4L2_CID_RF_TUNER_CLASS_BASE + 2) +#define V4L2_CID_RF_TUNER_MIXER_GAIN_AUTO (V4L2_CID_RF_TUNER_CLASS_BASE + 3) +#define V4L2_CID_RF_TUNER_MIXER_GAIN (V4L2_CID_RF_TUNER_CLASS_BASE + 4) +#define V4L2_CID_RF_TUNER_IF_GAIN_AUTO (V4L2_CID_RF_TUNER_CLASS_BASE + 5) +#define V4L2_CID_RF_TUNER_IF_GAIN (V4L2_CID_RF_TUNER_CLASS_BASE + 6) + #endif -- cgit v1.1 From f1343281d829d920d4158827bb420a24afe905f7 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Mon, 24 Feb 2014 14:44:50 -0300 Subject: [media] vb2: fix timecode and flags handling for output buffers When sending a buffer to a video output device some of the fields need to be copied so they arrive in the driver. These are the KEY/P/BFRAME flags and the TIMECODE flag, and, if that flag is set, the timecode field itself. There are a number of functions involved in this: the __fill_vb2_buffer() is called while preparing a buffer. For output buffers the buffer contains the video data, so any meta data associated with that (KEY/P/BFRAME and the field information) should be stored at that point. The timecode, timecode flag and timestamp information is not part of that, that information will have to be set when vb2_internal_qbuf() is called to actually queue the buffer to the driver. Usually VIDIOC_QBUF will do the prepare as well, but you can call PREPARE_BUF first and only later VIDIOC_QBUF. You most likely will want to set the timestamp and timecode when you actually queue the buffer, not when you prepare it. Finally, in buf_prepare() make sure the timestamp and sequence fields are actually cleared so that when you do a QUERYBUF of a prepared-but-not-yet-queued buffer you will not see stale timestamp/sequence data. Signed-off-by: Hans Verkuil Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab --- drivers/media/v4l2-core/videobuf2-core.c | 35 ++++++++++++++++++++++++++++++-- 1 file changed, 33 insertions(+), 2 deletions(-) diff --git a/drivers/media/v4l2-core/videobuf2-core.c b/drivers/media/v4l2-core/videobuf2-core.c index 5a5fb7f..edab3af 100644 --- a/drivers/media/v4l2-core/videobuf2-core.c +++ b/drivers/media/v4l2-core/videobuf2-core.c @@ -40,10 +40,14 @@ module_param(debug, int, 0644); #define call_qop(q, op, args...) \ (((q)->ops->op) ? ((q)->ops->op(args)) : 0) +/* Flags that are set by the vb2 core */ #define V4L2_BUFFER_MASK_FLAGS (V4L2_BUF_FLAG_MAPPED | V4L2_BUF_FLAG_QUEUED | \ V4L2_BUF_FLAG_DONE | V4L2_BUF_FLAG_ERROR | \ V4L2_BUF_FLAG_PREPARED | \ V4L2_BUF_FLAG_TIMESTAMP_MASK) +/* Output buffer flags that should be passed on to the driver */ +#define V4L2_BUFFER_OUT_FLAGS (V4L2_BUF_FLAG_PFRAME | V4L2_BUF_FLAG_BFRAME | \ + V4L2_BUF_FLAG_KEYFRAME | V4L2_BUF_FLAG_TIMECODE) /** * __vb2_buf_mem_alloc() - allocate video memory for the given buffer @@ -1025,9 +1029,21 @@ static void __fill_vb2_buffer(struct vb2_buffer *vb, const struct v4l2_buffer *b } - vb->v4l2_buf.field = b->field; - vb->v4l2_buf.timestamp = b->timestamp; + /* Zero flags that the vb2 core handles */ vb->v4l2_buf.flags = b->flags & ~V4L2_BUFFER_MASK_FLAGS; + if (V4L2_TYPE_IS_OUTPUT(b->type)) { + /* + * For output buffers mask out the timecode flag: + * this will be handled later in vb2_internal_qbuf(). + * The 'field' is valid metadata for this output buffer + * and so that needs to be copied here. + */ + vb->v4l2_buf.flags &= ~V4L2_BUF_FLAG_TIMECODE; + vb->v4l2_buf.field = b->field; + } else { + /* Zero any output buffer flags as this is a capture buffer */ + vb->v4l2_buf.flags &= ~V4L2_BUFFER_OUT_FLAGS; + } } /** @@ -1261,6 +1277,10 @@ static int __buf_prepare(struct vb2_buffer *vb, const struct v4l2_buffer *b) } vb->state = VB2_BUF_STATE_PREPARING; + vb->v4l2_buf.timestamp.tv_sec = 0; + vb->v4l2_buf.timestamp.tv_usec = 0; + vb->v4l2_buf.sequence = 0; + switch (q->memory) { case V4L2_MEMORY_MMAP: ret = __qbuf_mmap(vb, b); @@ -1448,6 +1468,17 @@ static int vb2_internal_qbuf(struct vb2_queue *q, struct v4l2_buffer *b) */ list_add_tail(&vb->queued_entry, &q->queued_list); vb->state = VB2_BUF_STATE_QUEUED; + if (V4L2_TYPE_IS_OUTPUT(q->type)) { + /* + * For output buffers copy the timestamp if needed, + * and the timecode field and flag if needed. + */ + if (q->timestamp_type == V4L2_BUF_FLAG_TIMESTAMP_COPY) + vb->v4l2_buf.timestamp = b->timestamp; + vb->v4l2_buf.flags |= b->flags & V4L2_BUF_FLAG_TIMECODE; + if (b->flags & V4L2_BUF_FLAG_TIMECODE) + vb->v4l2_buf.timecode = b->timecode; + } /* * If already streaming, give the buffer to driver for processing. -- cgit v1.1 From c6c092135d4f61b038a41685147c79e966c2399c Mon Sep 17 00:00:00 2001 From: Sakari Ailus Date: Fri, 25 Jan 2013 15:00:07 -0300 Subject: [media] v4l: Document timestamp behaviour to correspond to reality Document that monotonic timestamps are taken after the corresponding frame has been received, not when the reception has begun. This corresponds to the reality of current drivers: the timestamp is naturally taken when the hardware triggers an interrupt to tell the driver to handle the received frame. Remove the note on timestamp accuracy as it is fairly subjective what is actually an unstable timestamp. Also remove explanation that output buffer timestamps can be used to delay outputting a frame. Remove the footnote saying we always use realtime clock. Signed-off-by: Sakari Ailus Acked-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/v4l/io.xml | 56 ++++++++-------------------------- 1 file changed, 12 insertions(+), 44 deletions(-) diff --git a/Documentation/DocBook/media/v4l/io.xml b/Documentation/DocBook/media/v4l/io.xml index 1fb11e8..89544e4 100644 --- a/Documentation/DocBook/media/v4l/io.xml +++ b/Documentation/DocBook/media/v4l/io.xml @@ -339,8 +339,8 @@ returns immediately with an &EAGAIN; when no buffer is available. The queues as a side effect. Since there is no notion of doing anything "now" on a multitasking system, if an application needs to synchronize with another event it should examine the &v4l2-buffer; -timestamp of captured buffers, or set the -field before enqueuing buffers for output. +timestamp of captured or outputted buffers. + Drivers implementing memory mapping I/O must support the VIDIOC_REQBUFS, @@ -457,7 +457,7 @@ queues and unlocks all buffers as a side effect. Since there is no notion of doing anything "now" on a multitasking system, if an application needs to synchronize with another event it should examine the &v4l2-buffer; timestamp of captured -buffers, or set the field before enqueuing buffers for output. +or outputted buffers. Drivers implementing user pointer I/O must support the VIDIOC_REQBUFS, @@ -620,8 +620,7 @@ returns immediately with an &EAGAIN; when no buffer is available. The unlocks all buffers as a side effect. Since there is no notion of doing anything "now" on a multitasking system, if an application needs to synchronize with another event it should examine the &v4l2-buffer; -timestamp of captured buffers, or set the field -before enqueuing buffers for output. +timestamp of captured or outputted buffers. Drivers implementing DMABUF importing I/O must support the VIDIOC_REQBUFS, VIDIOC_QBUF, @@ -654,38 +653,11 @@ plane, are stored in struct v4l2_plane instead. In that case, struct v4l2_buffer contains an array of plane structures. - Nominally timestamps refer to the first data byte transmitted. -In practice however the wide range of hardware covered by the V4L2 API -limits timestamp accuracy. Often an interrupt routine will -sample the system clock shortly after the field or frame was stored -completely in memory. So applications must expect a constant -difference up to one field or frame period plus a small (few scan -lines) random error. The delay and error can be much -larger due to compression or transmission over an external bus when -the frames are not properly stamped by the sender. This is frequently -the case with USB cameras. Here timestamps refer to the instant the -field or frame was received by the driver, not the capture time. These -devices identify by not enumerating any video standards, see . - - Similar limitations apply to output timestamps. Typically -the video hardware locks to a clock controlling the video timing, the -horizontal and vertical synchronization pulses. At some point in the -line sequence, possibly the vertical blanking, an interrupt routine -samples the system clock, compares against the timestamp and programs -the hardware to repeat the previous field or frame, or to display the -buffer contents. - - Apart of limitations of the video device and natural -inaccuracies of all clocks, it should be noted system time itself is -not perfectly stable. It can be affected by power saving cycles, -warped to insert leap seconds, or even turned back or forth by the -system administrator affecting long term measurements. - Since no other Linux multimedia -API supports unadjusted time it would be foolish to introduce here. We -must use a universally supported clock to synchronize different media, -hence time of day. - + For timestamp types that are sampled from the system clock +(V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC) it is guaranteed that the timestamp is +taken after the complete frame has been received (or transmitted in +case of video output devices). For other kinds of +timestamps this may vary depending on the driver. struct <structname>v4l2_buffer</structname> @@ -745,13 +717,9 @@ applications when an output stream. byte was captured, as returned by the clock_gettime() function for the relevant clock id; see V4L2_BUF_FLAG_TIMESTAMP_* in - . For output streams the data - will not be displayed before this time, secondary to the nominal - frame rate determined by the current video standard in enqueued - order. Applications can for example zero this field to display - frames as soon as possible. The driver stores the time at which - the first data byte was actually sent out in the - timestamp field. This permits + . For output streams the driver + stores the time at which the last data byte was actually sent out + in the timestamp field. This permits applications to monitor the drift between the video and system clock. -- cgit v1.1 From 939f1377fbdb5d0d6d6ee1e234b8ab9328ca77ef Mon Sep 17 00:00:00 2001 From: Sakari Ailus Date: Sun, 25 Aug 2013 14:00:43 -0300 Subject: [media] v4l: Use full 32 bits for buffer flags The buffer flags field is 32 bits but the defined only used 16. This is fine, but as more than 16 bits will be used in the very near future, define them as 32-bit numbers for consistency. Signed-off-by: Sakari Ailus Acked-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/v4l/io.xml | 30 +++++++++++++-------------- include/uapi/linux/videodev2.h | 38 ++++++++++++++++++++-------------- 2 files changed, 38 insertions(+), 30 deletions(-) diff --git a/Documentation/DocBook/media/v4l/io.xml b/Documentation/DocBook/media/v4l/io.xml index 89544e4..5a2e97b 100644 --- a/Documentation/DocBook/media/v4l/io.xml +++ b/Documentation/DocBook/media/v4l/io.xml @@ -990,7 +990,7 @@ should set this to 0. V4L2_BUF_FLAG_MAPPED - 0x0001 + 0x00000001 The buffer resides in device memory and has been mapped into the application's address space, see for details. Drivers set or clear this flag when the @@ -1000,7 +1000,7 @@ Drivers set or clear this flag when the V4L2_BUF_FLAG_QUEUED - 0x0002 + 0x00000002 Internally drivers maintain two buffer queues, an incoming and outgoing queue. When this flag is set, the buffer is currently on the incoming queue. It automatically moves to the @@ -1013,7 +1013,7 @@ cleared. V4L2_BUF_FLAG_DONE - 0x0004 + 0x00000004 When this flag is set, the buffer is currently on the outgoing queue, ready to be dequeued from the driver. Drivers set or clear this flag when the VIDIOC_QUERYBUF ioctl @@ -1027,7 +1027,7 @@ state, in the application domain to say so. V4L2_BUF_FLAG_ERROR - 0x0040 + 0x00000040 When this flag is set, the buffer has been dequeued successfully, although the data might have been corrupted. This is recoverable, streaming may continue as normal and @@ -1037,7 +1037,7 @@ state, in the application domain to say so. V4L2_BUF_FLAG_KEYFRAME - 0x0008 + 0x00000008 Drivers set or clear this flag when calling the VIDIOC_DQBUF ioctl. It may be set by video capture devices when the buffer contains a compressed image which is a @@ -1045,27 +1045,27 @@ key frame (or field), &ie; can be decompressed on its own. V4L2_BUF_FLAG_PFRAME - 0x0010 + 0x00000010 Similar to V4L2_BUF_FLAG_KEYFRAME this flags predicted frames or fields which contain only differences to a previous key frame. V4L2_BUF_FLAG_BFRAME - 0x0020 + 0x00000020 Similar to V4L2_BUF_FLAG_PFRAME this is a bidirectional predicted frame or field. [ooc tbd] V4L2_BUF_FLAG_TIMECODE - 0x0100 + 0x00000100 The timecode field is valid. Drivers set or clear this flag when the VIDIOC_DQBUF ioctl is called. V4L2_BUF_FLAG_PREPARED - 0x0400 + 0x00000400 The buffer has been prepared for I/O and can be queued by the application. Drivers set or clear this flag when the VIDIOC_QUERYBUF, V4L2_BUF_FLAG_NO_CACHE_INVALIDATE - 0x0800 + 0x00000800 Caches do not have to be invalidated for this buffer. Typically applications shall use this flag if the data captured in the buffer is not going to be touched by the CPU, instead the buffer will, probably, be @@ -1084,7 +1084,7 @@ passed on to a DMA-capable hardware unit for further processing or output. V4L2_BUF_FLAG_NO_CACHE_CLEAN - 0x1000 + 0x00001000 Caches do not have to be cleaned for this buffer. Typically applications shall use this flag for output buffers if the data in this buffer has not been created by the CPU but by some DMA-capable unit, @@ -1092,7 +1092,7 @@ in which case caches have not been used. V4L2_BUF_FLAG_TIMESTAMP_MASK - 0xe000 + 0x0000e000 Mask for timestamp types below. To test the timestamp type, mask out bits not belonging to timestamp type by performing a logical and operation with buffer @@ -1100,7 +1100,7 @@ in which case caches have not been used. V4L2_BUF_FLAG_TIMESTAMP_UNKNOWN - 0x0000 + 0x00000000 Unknown timestamp type. This type is used by drivers before Linux 3.9 and may be either monotonic (see below) or realtime (wall clock). Monotonic clock has been @@ -1113,7 +1113,7 @@ in which case caches have not been used. V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC - 0x2000 + 0x00002000 The buffer timestamp has been taken from the CLOCK_MONOTONIC clock. To access the same clock outside V4L2, use @@ -1121,7 +1121,7 @@ in which case caches have not been used. V4L2_BUF_FLAG_TIMESTAMP_COPY - 0x4000 + 0x00004000 The CAPTURE buffer timestamp has been taken from the corresponding OUTPUT buffer. This flag applies only to mem2mem devices. diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h index 27fedfe..cb83876 100644 --- a/include/uapi/linux/videodev2.h +++ b/include/uapi/linux/videodev2.h @@ -674,24 +674,32 @@ struct v4l2_buffer { }; /* Flags for 'flags' field */ -#define V4L2_BUF_FLAG_MAPPED 0x0001 /* Buffer is mapped (flag) */ -#define V4L2_BUF_FLAG_QUEUED 0x0002 /* Buffer is queued for processing */ -#define V4L2_BUF_FLAG_DONE 0x0004 /* Buffer is ready */ -#define V4L2_BUF_FLAG_KEYFRAME 0x0008 /* Image is a keyframe (I-frame) */ -#define V4L2_BUF_FLAG_PFRAME 0x0010 /* Image is a P-frame */ -#define V4L2_BUF_FLAG_BFRAME 0x0020 /* Image is a B-frame */ +/* Buffer is mapped (flag) */ +#define V4L2_BUF_FLAG_MAPPED 0x00000001 +/* Buffer is queued for processing */ +#define V4L2_BUF_FLAG_QUEUED 0x00000002 +/* Buffer is ready */ +#define V4L2_BUF_FLAG_DONE 0x00000004 +/* Image is a keyframe (I-frame) */ +#define V4L2_BUF_FLAG_KEYFRAME 0x00000008 +/* Image is a P-frame */ +#define V4L2_BUF_FLAG_PFRAME 0x00000010 +/* Image is a B-frame */ +#define V4L2_BUF_FLAG_BFRAME 0x00000020 /* Buffer is ready, but the data contained within is corrupted. */ -#define V4L2_BUF_FLAG_ERROR 0x0040 -#define V4L2_BUF_FLAG_TIMECODE 0x0100 /* timecode field is valid */ -#define V4L2_BUF_FLAG_PREPARED 0x0400 /* Buffer is prepared for queuing */ +#define V4L2_BUF_FLAG_ERROR 0x00000040 +/* timecode field is valid */ +#define V4L2_BUF_FLAG_TIMECODE 0x00000100 +/* Buffer is prepared for queuing */ +#define V4L2_BUF_FLAG_PREPARED 0x00000400 /* Cache handling flags */ -#define V4L2_BUF_FLAG_NO_CACHE_INVALIDATE 0x0800 -#define V4L2_BUF_FLAG_NO_CACHE_CLEAN 0x1000 +#define V4L2_BUF_FLAG_NO_CACHE_INVALIDATE 0x00000800 +#define V4L2_BUF_FLAG_NO_CACHE_CLEAN 0x00001000 /* Timestamp type */ -#define V4L2_BUF_FLAG_TIMESTAMP_MASK 0xe000 -#define V4L2_BUF_FLAG_TIMESTAMP_UNKNOWN 0x0000 -#define V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC 0x2000 -#define V4L2_BUF_FLAG_TIMESTAMP_COPY 0x4000 +#define V4L2_BUF_FLAG_TIMESTAMP_MASK 0x0000e000 +#define V4L2_BUF_FLAG_TIMESTAMP_UNKNOWN 0x00000000 +#define V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC 0x00002000 +#define V4L2_BUF_FLAG_TIMESTAMP_COPY 0x00004000 /** * struct v4l2_exportbuffer - export of video buffer as DMABUF file descriptor -- cgit v1.1 From ade48681f132188599c5cefa8a3287c2a26fb738 Mon Sep 17 00:00:00 2001 From: Sakari Ailus Date: Tue, 25 Feb 2014 19:12:19 -0300 Subject: [media] v4l: Rename vb2_queue.timestamp_type as timestamp_flags The timestamp_type field used to contain only the timestamp type. Soon it will be used for timestamp source flags as well. Rename the field accordingly. [m.chehab@samsung.com: do the change also to drivers/staging/media and at s2255] Signed-off-by: Sakari Ailus Acked-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/parport/bw-qcam.c | 2 +- drivers/media/platform/blackfin/bfin_capture.c | 2 +- drivers/media/platform/coda.c | 4 ++-- drivers/media/platform/davinci/vpbe_display.c | 2 +- drivers/media/platform/davinci/vpif_capture.c | 2 +- drivers/media/platform/davinci/vpif_display.c | 2 +- drivers/media/platform/exynos-gsc/gsc-m2m.c | 4 ++-- drivers/media/platform/exynos4-is/fimc-capture.c | 2 +- drivers/media/platform/exynos4-is/fimc-lite.c | 2 +- drivers/media/platform/exynos4-is/fimc-m2m.c | 4 ++-- drivers/media/platform/m2m-deinterlace.c | 4 ++-- drivers/media/platform/mem2mem_testdev.c | 4 ++-- drivers/media/platform/mx2_emmaprp.c | 4 ++-- drivers/media/platform/s3c-camif/camif-capture.c | 2 +- drivers/media/platform/s5p-g2d/g2d.c | 4 ++-- drivers/media/platform/s5p-jpeg/jpeg-core.c | 4 ++-- drivers/media/platform/s5p-mfc/s5p_mfc.c | 4 ++-- drivers/media/platform/soc_camera/atmel-isi.c | 2 +- drivers/media/platform/soc_camera/mx2_camera.c | 2 +- drivers/media/platform/soc_camera/mx3_camera.c | 2 +- drivers/media/platform/soc_camera/rcar_vin.c | 2 +- drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c | 2 +- drivers/media/platform/ti-vpe/vpe.c | 4 ++-- drivers/media/platform/vivi.c | 2 +- drivers/media/platform/vsp1/vsp1_video.c | 2 +- drivers/media/usb/em28xx/em28xx-video.c | 4 ++-- drivers/media/usb/pwc/pwc-if.c | 2 +- drivers/media/usb/s2255/s2255drv.c | 2 +- drivers/media/usb/stk1160/stk1160-v4l.c | 2 +- drivers/media/usb/usbtv/usbtv-video.c | 2 +- drivers/media/usb/uvc/uvc_queue.c | 2 +- drivers/media/v4l2-core/videobuf2-core.c | 8 ++++---- drivers/staging/media/dt3155v4l/dt3155v4l.c | 2 +- drivers/staging/media/go7007/go7007-v4l2.c | 2 +- drivers/staging/media/msi3101/sdr-msi3101.c | 2 +- drivers/staging/media/omap4iss/iss_video.c | 2 +- drivers/staging/media/solo6x10/solo6x10-v4l2-enc.c | 2 +- drivers/staging/media/solo6x10/solo6x10-v4l2.c | 2 +- include/media/videobuf2-core.h | 2 +- 39 files changed, 53 insertions(+), 53 deletions(-) diff --git a/drivers/media/parport/bw-qcam.c b/drivers/media/parport/bw-qcam.c index d12bd33..a0a6ee6 100644 --- a/drivers/media/parport/bw-qcam.c +++ b/drivers/media/parport/bw-qcam.c @@ -965,7 +965,7 @@ static struct qcam *qcam_init(struct parport *port) q->drv_priv = qcam; q->ops = &qcam_video_qops; q->mem_ops = &vb2_vmalloc_memops; - q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; err = vb2_queue_init(q); if (err < 0) { v4l2_err(v4l2_dev, "couldn't init vb2_queue for %s.\n", port->name); diff --git a/drivers/media/platform/blackfin/bfin_capture.c b/drivers/media/platform/blackfin/bfin_capture.c index 2819165..200bec9 100644 --- a/drivers/media/platform/blackfin/bfin_capture.c +++ b/drivers/media/platform/blackfin/bfin_capture.c @@ -997,7 +997,7 @@ static int bcap_probe(struct platform_device *pdev) q->buf_struct_size = sizeof(struct bcap_buffer); q->ops = &bcap_video_qops; q->mem_ops = &vb2_dma_contig_memops; - q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; ret = vb2_queue_init(q); if (ret) diff --git a/drivers/media/platform/coda.c b/drivers/media/platform/coda.c index 61f3dbc..81b6f7b 100644 --- a/drivers/media/platform/coda.c +++ b/drivers/media/platform/coda.c @@ -2428,7 +2428,7 @@ static int coda_queue_init(void *priv, struct vb2_queue *src_vq, src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); src_vq->ops = &coda_qops; src_vq->mem_ops = &vb2_dma_contig_memops; - src_vq->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY; + src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; ret = vb2_queue_init(src_vq); if (ret) @@ -2440,7 +2440,7 @@ static int coda_queue_init(void *priv, struct vb2_queue *src_vq, dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); dst_vq->ops = &coda_qops; dst_vq->mem_ops = &vb2_dma_contig_memops; - dst_vq->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY; + dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; return vb2_queue_init(dst_vq); } diff --git a/drivers/media/platform/davinci/vpbe_display.c b/drivers/media/platform/davinci/vpbe_display.c index b02aba4..e512767 100644 --- a/drivers/media/platform/davinci/vpbe_display.c +++ b/drivers/media/platform/davinci/vpbe_display.c @@ -1415,7 +1415,7 @@ static int vpbe_display_reqbufs(struct file *file, void *priv, q->ops = &video_qops; q->mem_ops = &vb2_dma_contig_memops; q->buf_struct_size = sizeof(struct vpbe_disp_buffer); - q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; ret = vb2_queue_init(q); if (ret) { diff --git a/drivers/media/platform/davinci/vpif_capture.c b/drivers/media/platform/davinci/vpif_capture.c index 735ec47..cd6da8b 100644 --- a/drivers/media/platform/davinci/vpif_capture.c +++ b/drivers/media/platform/davinci/vpif_capture.c @@ -1023,7 +1023,7 @@ static int vpif_reqbufs(struct file *file, void *priv, q->ops = &video_qops; q->mem_ops = &vb2_dma_contig_memops; q->buf_struct_size = sizeof(struct vpif_cap_buffer); - q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; ret = vb2_queue_init(q); if (ret) { diff --git a/drivers/media/platform/davinci/vpif_display.c b/drivers/media/platform/davinci/vpif_display.c index 9d115cd..fd68236 100644 --- a/drivers/media/platform/davinci/vpif_display.c +++ b/drivers/media/platform/davinci/vpif_display.c @@ -983,7 +983,7 @@ static int vpif_reqbufs(struct file *file, void *priv, q->ops = &video_qops; q->mem_ops = &vb2_dma_contig_memops; q->buf_struct_size = sizeof(struct vpif_disp_buffer); - q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; ret = vb2_queue_init(q); if (ret) { diff --git a/drivers/media/platform/exynos-gsc/gsc-m2m.c b/drivers/media/platform/exynos-gsc/gsc-m2m.c index 810c3e1..6741025 100644 --- a/drivers/media/platform/exynos-gsc/gsc-m2m.c +++ b/drivers/media/platform/exynos-gsc/gsc-m2m.c @@ -590,7 +590,7 @@ static int queue_init(void *priv, struct vb2_queue *src_vq, src_vq->ops = &gsc_m2m_qops; src_vq->mem_ops = &vb2_dma_contig_memops; src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); - src_vq->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY; + src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; ret = vb2_queue_init(src_vq); if (ret) @@ -603,7 +603,7 @@ static int queue_init(void *priv, struct vb2_queue *src_vq, dst_vq->ops = &gsc_m2m_qops; dst_vq->mem_ops = &vb2_dma_contig_memops; dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); - dst_vq->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY; + dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; return vb2_queue_init(dst_vq); } diff --git a/drivers/media/platform/exynos4-is/fimc-capture.c b/drivers/media/platform/exynos4-is/fimc-capture.c index 8a712ca..92ae812 100644 --- a/drivers/media/platform/exynos4-is/fimc-capture.c +++ b/drivers/media/platform/exynos4-is/fimc-capture.c @@ -1782,7 +1782,7 @@ static int fimc_register_capture_device(struct fimc_dev *fimc, q->ops = &fimc_capture_qops; q->mem_ops = &vb2_dma_contig_memops; q->buf_struct_size = sizeof(struct fimc_vid_buffer); - q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; q->lock = &fimc->lock; ret = vb2_queue_init(q); diff --git a/drivers/media/platform/exynos4-is/fimc-lite.c b/drivers/media/platform/exynos4-is/fimc-lite.c index 1234734..2be4bb5 100644 --- a/drivers/media/platform/exynos4-is/fimc-lite.c +++ b/drivers/media/platform/exynos4-is/fimc-lite.c @@ -1313,7 +1313,7 @@ static int fimc_lite_subdev_registered(struct v4l2_subdev *sd) q->mem_ops = &vb2_dma_contig_memops; q->buf_struct_size = sizeof(struct flite_buffer); q->drv_priv = fimc; - q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; q->lock = &fimc->lock; ret = vb2_queue_init(q); diff --git a/drivers/media/platform/exynos4-is/fimc-m2m.c b/drivers/media/platform/exynos4-is/fimc-m2m.c index 9da95bd..bfc900d 100644 --- a/drivers/media/platform/exynos4-is/fimc-m2m.c +++ b/drivers/media/platform/exynos4-is/fimc-m2m.c @@ -557,7 +557,7 @@ static int queue_init(void *priv, struct vb2_queue *src_vq, src_vq->ops = &fimc_qops; src_vq->mem_ops = &vb2_dma_contig_memops; src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); - src_vq->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY; + src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; src_vq->lock = &ctx->fimc_dev->lock; ret = vb2_queue_init(src_vq); @@ -570,7 +570,7 @@ static int queue_init(void *priv, struct vb2_queue *src_vq, dst_vq->ops = &fimc_qops; dst_vq->mem_ops = &vb2_dma_contig_memops; dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); - dst_vq->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY; + dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; dst_vq->lock = &ctx->fimc_dev->lock; return vb2_queue_init(dst_vq); diff --git a/drivers/media/platform/m2m-deinterlace.c b/drivers/media/platform/m2m-deinterlace.c index 6bb86b5..f3a9e24 100644 --- a/drivers/media/platform/m2m-deinterlace.c +++ b/drivers/media/platform/m2m-deinterlace.c @@ -868,7 +868,7 @@ static int queue_init(void *priv, struct vb2_queue *src_vq, src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); src_vq->ops = &deinterlace_qops; src_vq->mem_ops = &vb2_dma_contig_memops; - src_vq->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY; + src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; q_data[V4L2_M2M_SRC].fmt = &formats[0]; q_data[V4L2_M2M_SRC].width = 640; q_data[V4L2_M2M_SRC].height = 480; @@ -885,7 +885,7 @@ static int queue_init(void *priv, struct vb2_queue *src_vq, dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); dst_vq->ops = &deinterlace_qops; dst_vq->mem_ops = &vb2_dma_contig_memops; - dst_vq->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY; + dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; q_data[V4L2_M2M_DST].fmt = &formats[0]; q_data[V4L2_M2M_DST].width = 640; q_data[V4L2_M2M_DST].height = 480; diff --git a/drivers/media/platform/mem2mem_testdev.c b/drivers/media/platform/mem2mem_testdev.c index 08e2437..02a40c5 100644 --- a/drivers/media/platform/mem2mem_testdev.c +++ b/drivers/media/platform/mem2mem_testdev.c @@ -777,7 +777,7 @@ static int queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *ds src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); src_vq->ops = &m2mtest_qops; src_vq->mem_ops = &vb2_vmalloc_memops; - src_vq->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY; + src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; src_vq->lock = &ctx->dev->dev_mutex; ret = vb2_queue_init(src_vq); @@ -790,7 +790,7 @@ static int queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *ds dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); dst_vq->ops = &m2mtest_qops; dst_vq->mem_ops = &vb2_vmalloc_memops; - dst_vq->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY; + dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; dst_vq->lock = &ctx->dev->dev_mutex; return vb2_queue_init(dst_vq); diff --git a/drivers/media/platform/mx2_emmaprp.c b/drivers/media/platform/mx2_emmaprp.c index c690435..af3e106 100644 --- a/drivers/media/platform/mx2_emmaprp.c +++ b/drivers/media/platform/mx2_emmaprp.c @@ -766,7 +766,7 @@ static int queue_init(void *priv, struct vb2_queue *src_vq, src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); src_vq->ops = &emmaprp_qops; src_vq->mem_ops = &vb2_dma_contig_memops; - src_vq->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY; + src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; ret = vb2_queue_init(src_vq); if (ret) @@ -778,7 +778,7 @@ static int queue_init(void *priv, struct vb2_queue *src_vq, dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); dst_vq->ops = &emmaprp_qops; dst_vq->mem_ops = &vb2_dma_contig_memops; - dst_vq->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY; + dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; return vb2_queue_init(dst_vq); } diff --git a/drivers/media/platform/s3c-camif/camif-capture.c b/drivers/media/platform/s3c-camif/camif-capture.c index 5372111..4e4d163 100644 --- a/drivers/media/platform/s3c-camif/camif-capture.c +++ b/drivers/media/platform/s3c-camif/camif-capture.c @@ -1160,7 +1160,7 @@ int s3c_camif_register_video_node(struct camif_dev *camif, int idx) q->mem_ops = &vb2_dma_contig_memops; q->buf_struct_size = sizeof(struct camif_buffer); q->drv_priv = vp; - q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; ret = vb2_queue_init(q); if (ret) diff --git a/drivers/media/platform/s5p-g2d/g2d.c b/drivers/media/platform/s5p-g2d/g2d.c index 0fcf7d7..bf7c9b3 100644 --- a/drivers/media/platform/s5p-g2d/g2d.c +++ b/drivers/media/platform/s5p-g2d/g2d.c @@ -157,7 +157,7 @@ static int queue_init(void *priv, struct vb2_queue *src_vq, src_vq->ops = &g2d_qops; src_vq->mem_ops = &vb2_dma_contig_memops; src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); - src_vq->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY; + src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; src_vq->lock = &ctx->dev->mutex; ret = vb2_queue_init(src_vq); @@ -170,7 +170,7 @@ static int queue_init(void *priv, struct vb2_queue *src_vq, dst_vq->ops = &g2d_qops; dst_vq->mem_ops = &vb2_dma_contig_memops; dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); - dst_vq->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY; + dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; dst_vq->lock = &ctx->dev->mutex; return vb2_queue_init(dst_vq); diff --git a/drivers/media/platform/s5p-jpeg/jpeg-core.c b/drivers/media/platform/s5p-jpeg/jpeg-core.c index a1c78c8..f5e9870 100644 --- a/drivers/media/platform/s5p-jpeg/jpeg-core.c +++ b/drivers/media/platform/s5p-jpeg/jpeg-core.c @@ -1701,7 +1701,7 @@ static int queue_init(void *priv, struct vb2_queue *src_vq, src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); src_vq->ops = &s5p_jpeg_qops; src_vq->mem_ops = &vb2_dma_contig_memops; - src_vq->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY; + src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; src_vq->lock = &ctx->jpeg->lock; ret = vb2_queue_init(src_vq); @@ -1714,7 +1714,7 @@ static int queue_init(void *priv, struct vb2_queue *src_vq, dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); dst_vq->ops = &s5p_jpeg_qops; dst_vq->mem_ops = &vb2_dma_contig_memops; - dst_vq->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY; + dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; dst_vq->lock = &ctx->jpeg->lock; return vb2_queue_init(dst_vq); diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc.c b/drivers/media/platform/s5p-mfc/s5p_mfc.c index e2aac59..0e8c171 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc.c +++ b/drivers/media/platform/s5p-mfc/s5p_mfc.c @@ -794,7 +794,7 @@ static int s5p_mfc_open(struct file *file) goto err_queue_init; } q->mem_ops = (struct vb2_mem_ops *)&vb2_dma_contig_memops; - q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY; + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; ret = vb2_queue_init(q); if (ret) { mfc_err("Failed to initialize videobuf2 queue(capture)\n"); @@ -816,7 +816,7 @@ static int s5p_mfc_open(struct file *file) goto err_queue_init; } q->mem_ops = (struct vb2_mem_ops *)&vb2_dma_contig_memops; - q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY; + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; ret = vb2_queue_init(q); if (ret) { mfc_err("Failed to initialize videobuf2 queue(output)\n"); diff --git a/drivers/media/platform/soc_camera/atmel-isi.c b/drivers/media/platform/soc_camera/atmel-isi.c index 4835173..f0b6c90 100644 --- a/drivers/media/platform/soc_camera/atmel-isi.c +++ b/drivers/media/platform/soc_camera/atmel-isi.c @@ -472,7 +472,7 @@ static int isi_camera_init_videobuf(struct vb2_queue *q, q->buf_struct_size = sizeof(struct frame_buffer); q->ops = &isi_video_qops; q->mem_ops = &vb2_dma_contig_memops; - q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; return vb2_queue_init(q); } diff --git a/drivers/media/platform/soc_camera/mx2_camera.c b/drivers/media/platform/soc_camera/mx2_camera.c index d73abca..3e84480 100644 --- a/drivers/media/platform/soc_camera/mx2_camera.c +++ b/drivers/media/platform/soc_camera/mx2_camera.c @@ -794,7 +794,7 @@ static int mx2_camera_init_videobuf(struct vb2_queue *q, q->ops = &mx2_videobuf_ops; q->mem_ops = &vb2_dma_contig_memops; q->buf_struct_size = sizeof(struct mx2_buffer); - q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; return vb2_queue_init(q); } diff --git a/drivers/media/platform/soc_camera/mx3_camera.c b/drivers/media/platform/soc_camera/mx3_camera.c index f975b70..9ed81ac 100644 --- a/drivers/media/platform/soc_camera/mx3_camera.c +++ b/drivers/media/platform/soc_camera/mx3_camera.c @@ -453,7 +453,7 @@ static int mx3_camera_init_videobuf(struct vb2_queue *q, q->ops = &mx3_videobuf_ops; q->mem_ops = &vb2_dma_contig_memops; q->buf_struct_size = sizeof(struct mx3_camera_buffer); - q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; return vb2_queue_init(q); } diff --git a/drivers/media/platform/soc_camera/rcar_vin.c b/drivers/media/platform/soc_camera/rcar_vin.c index 3b1c05a..0ff5cfa 100644 --- a/drivers/media/platform/soc_camera/rcar_vin.c +++ b/drivers/media/platform/soc_camera/rcar_vin.c @@ -1360,7 +1360,7 @@ static int rcar_vin_init_videobuf2(struct vb2_queue *vq, vq->ops = &rcar_vin_vb2_ops; vq->mem_ops = &vb2_dma_contig_memops; vq->buf_struct_size = sizeof(struct rcar_vin_buffer); - vq->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; return vb2_queue_init(vq); } diff --git a/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c b/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c index 150bd4d..3e75a46 100644 --- a/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c +++ b/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c @@ -1665,7 +1665,7 @@ static int sh_mobile_ceu_init_videobuf(struct vb2_queue *q, q->ops = &sh_mobile_ceu_videobuf_ops; q->mem_ops = &vb2_dma_contig_memops; q->buf_struct_size = sizeof(struct sh_mobile_ceu_buffer); - q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; return vb2_queue_init(q); } diff --git a/drivers/media/platform/ti-vpe/vpe.c b/drivers/media/platform/ti-vpe/vpe.c index 1296c53..8ea3b89 100644 --- a/drivers/media/platform/ti-vpe/vpe.c +++ b/drivers/media/platform/ti-vpe/vpe.c @@ -1770,7 +1770,7 @@ static int queue_init(void *priv, struct vb2_queue *src_vq, src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); src_vq->ops = &vpe_qops; src_vq->mem_ops = &vb2_dma_contig_memops; - src_vq->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY; + src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; ret = vb2_queue_init(src_vq); if (ret) @@ -1783,7 +1783,7 @@ static int queue_init(void *priv, struct vb2_queue *src_vq, dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); dst_vq->ops = &vpe_qops; dst_vq->mem_ops = &vb2_dma_contig_memops; - dst_vq->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY; + dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; return vb2_queue_init(dst_vq); } diff --git a/drivers/media/platform/vivi.c b/drivers/media/platform/vivi.c index e9cd96e..776015b 100644 --- a/drivers/media/platform/vivi.c +++ b/drivers/media/platform/vivi.c @@ -1429,7 +1429,7 @@ static int __init vivi_create_instance(int inst) q->buf_struct_size = sizeof(struct vivi_buffer); q->ops = &vivi_video_qops; q->mem_ops = &vb2_vmalloc_memops; - q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; ret = vb2_queue_init(q); if (ret) diff --git a/drivers/media/platform/vsp1/vsp1_video.c b/drivers/media/platform/vsp1/vsp1_video.c index b4687a8..e41f07d 100644 --- a/drivers/media/platform/vsp1/vsp1_video.c +++ b/drivers/media/platform/vsp1/vsp1_video.c @@ -1051,7 +1051,7 @@ int vsp1_video_init(struct vsp1_video *video, struct vsp1_entity *rwpf) video->queue.buf_struct_size = sizeof(struct vsp1_video_buffer); video->queue.ops = &vsp1_video_queue_qops; video->queue.mem_ops = &vb2_dma_contig_memops; - video->queue.timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY; + video->queue.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; ret = vb2_queue_init(&video->queue); if (ret < 0) { dev_err(video->vsp1->dev, "failed to initialize vb2 queue\n"); diff --git a/drivers/media/usb/em28xx/em28xx-video.c b/drivers/media/usb/em28xx/em28xx-video.c index 19af6b3..13466c4 100644 --- a/drivers/media/usb/em28xx/em28xx-video.c +++ b/drivers/media/usb/em28xx/em28xx-video.c @@ -1029,7 +1029,7 @@ static int em28xx_vb2_setup(struct em28xx *dev) q = &dev->vb_vidq; q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; q->io_modes = VB2_READ | VB2_MMAP | VB2_USERPTR | VB2_DMABUF; - q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; q->drv_priv = dev; q->buf_struct_size = sizeof(struct em28xx_buffer); q->ops = &em28xx_video_qops; @@ -1043,7 +1043,7 @@ static int em28xx_vb2_setup(struct em28xx *dev) q = &dev->vb_vbiq; q->type = V4L2_BUF_TYPE_VBI_CAPTURE; q->io_modes = VB2_READ | VB2_MMAP | VB2_USERPTR; - q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; q->drv_priv = dev; q->buf_struct_size = sizeof(struct em28xx_buffer); q->ops = &em28xx_vbi_qops; diff --git a/drivers/media/usb/pwc/pwc-if.c b/drivers/media/usb/pwc/pwc-if.c index abf365a..8bef015 100644 --- a/drivers/media/usb/pwc/pwc-if.c +++ b/drivers/media/usb/pwc/pwc-if.c @@ -1001,7 +1001,7 @@ static int usb_pwc_probe(struct usb_interface *intf, const struct usb_device_id pdev->vb_queue.buf_struct_size = sizeof(struct pwc_frame_buf); pdev->vb_queue.ops = &pwc_vb_queue_ops; pdev->vb_queue.mem_ops = &vb2_vmalloc_memops; - pdev->vb_queue.timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + pdev->vb_queue.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; rc = vb2_queue_init(&pdev->vb_queue); if (rc < 0) { PWC_ERROR("Oops, could not initialize vb2 queue.\n"); diff --git a/drivers/media/usb/s2255/s2255drv.c b/drivers/media/usb/s2255/s2255drv.c index ef66b1b..4c7513a 100644 --- a/drivers/media/usb/s2255/s2255drv.c +++ b/drivers/media/usb/s2255/s2255drv.c @@ -1664,7 +1664,7 @@ static int s2255_probe_v4l(struct s2255_dev *dev) q->buf_struct_size = sizeof(struct s2255_buffer); q->mem_ops = &vb2_vmalloc_memops; q->ops = &s2255_video_qops; - q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; ret = vb2_queue_init(q); if (ret != 0) { dev_err(&dev->udev->dev, diff --git a/drivers/media/usb/stk1160/stk1160-v4l.c b/drivers/media/usb/stk1160/stk1160-v4l.c index c45c988..37bc00f 100644 --- a/drivers/media/usb/stk1160/stk1160-v4l.c +++ b/drivers/media/usb/stk1160/stk1160-v4l.c @@ -641,7 +641,7 @@ int stk1160_vb2_setup(struct stk1160 *dev) q->buf_struct_size = sizeof(struct stk1160_buffer); q->ops = &stk1160_video_qops; q->mem_ops = &vb2_vmalloc_memops; - q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; rc = vb2_queue_init(q); if (rc < 0) diff --git a/drivers/media/usb/usbtv/usbtv-video.c b/drivers/media/usb/usbtv/usbtv-video.c index 496bc2e..01ed1ec8 100644 --- a/drivers/media/usb/usbtv/usbtv-video.c +++ b/drivers/media/usb/usbtv/usbtv-video.c @@ -679,7 +679,7 @@ int usbtv_video_init(struct usbtv *usbtv) usbtv->vb2q.buf_struct_size = sizeof(struct usbtv_buf); usbtv->vb2q.ops = &usbtv_vb2_ops; usbtv->vb2q.mem_ops = &vb2_vmalloc_memops; - usbtv->vb2q.timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + usbtv->vb2q.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; usbtv->vb2q.lock = &usbtv->vb2q_lock; ret = vb2_queue_init(&usbtv->vb2q); if (ret < 0) { diff --git a/drivers/media/usb/uvc/uvc_queue.c b/drivers/media/usb/uvc/uvc_queue.c index ff7be97..7c14616 100644 --- a/drivers/media/usb/uvc/uvc_queue.c +++ b/drivers/media/usb/uvc/uvc_queue.c @@ -151,7 +151,7 @@ int uvc_queue_init(struct uvc_video_queue *queue, enum v4l2_buf_type type, queue->queue.buf_struct_size = sizeof(struct uvc_buffer); queue->queue.ops = &uvc_queue_qops; queue->queue.mem_ops = &vb2_vmalloc_memops; - queue->queue.timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + queue->queue.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; ret = vb2_queue_init(&queue->queue); if (ret) return ret; diff --git a/drivers/media/v4l2-core/videobuf2-core.c b/drivers/media/v4l2-core/videobuf2-core.c index edab3af..411429c 100644 --- a/drivers/media/v4l2-core/videobuf2-core.c +++ b/drivers/media/v4l2-core/videobuf2-core.c @@ -488,7 +488,7 @@ static void __fill_v4l2_buffer(struct vb2_buffer *vb, struct v4l2_buffer *b) * Clear any buffer state related flags. */ b->flags &= ~V4L2_BUFFER_MASK_FLAGS; - b->flags |= q->timestamp_type; + b->flags |= q->timestamp_flags; switch (vb->state) { case VB2_BUF_STATE_QUEUED: @@ -1473,7 +1473,7 @@ static int vb2_internal_qbuf(struct vb2_queue *q, struct v4l2_buffer *b) * For output buffers copy the timestamp if needed, * and the timecode field and flag if needed. */ - if (q->timestamp_type == V4L2_BUF_FLAG_TIMESTAMP_COPY) + if (q->timestamp_flags == V4L2_BUF_FLAG_TIMESTAMP_COPY) vb->v4l2_buf.timestamp = b->timestamp; vb->v4l2_buf.flags |= b->flags & V4L2_BUF_FLAG_TIMECODE; if (b->flags & V4L2_BUF_FLAG_TIMECODE) @@ -2226,11 +2226,11 @@ int vb2_queue_init(struct vb2_queue *q) WARN_ON(!q->io_modes) || WARN_ON(!q->ops->queue_setup) || WARN_ON(!q->ops->buf_queue) || - WARN_ON(q->timestamp_type & ~V4L2_BUF_FLAG_TIMESTAMP_MASK)) + WARN_ON(q->timestamp_flags & ~V4L2_BUF_FLAG_TIMESTAMP_MASK)) return -EINVAL; /* Warn that the driver should choose an appropriate timestamp type */ - WARN_ON(q->timestamp_type == V4L2_BUF_FLAG_TIMESTAMP_UNKNOWN); + WARN_ON(q->timestamp_flags == V4L2_BUF_FLAG_TIMESTAMP_UNKNOWN); INIT_LIST_HEAD(&q->queued_list); INIT_LIST_HEAD(&q->done_list); diff --git a/drivers/staging/media/dt3155v4l/dt3155v4l.c b/drivers/staging/media/dt3155v4l/dt3155v4l.c index e729e52..e235787 100644 --- a/drivers/staging/media/dt3155v4l/dt3155v4l.c +++ b/drivers/staging/media/dt3155v4l/dt3155v4l.c @@ -391,7 +391,7 @@ dt3155_open(struct file *filp) goto err_alloc_queue; } pd->q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; - pd->q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + pd->q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; pd->q->io_modes = VB2_READ | VB2_MMAP; pd->q->ops = &q_ops; pd->q->mem_ops = &vb2_dma_contig_memops; diff --git a/drivers/staging/media/go7007/go7007-v4l2.c b/drivers/staging/media/go7007/go7007-v4l2.c index edc52e2..efacda24 100644 --- a/drivers/staging/media/go7007/go7007-v4l2.c +++ b/drivers/staging/media/go7007/go7007-v4l2.c @@ -989,7 +989,7 @@ int go7007_v4l2_init(struct go7007 *go) go->vidq.mem_ops = &vb2_vmalloc_memops; go->vidq.drv_priv = go; go->vidq.buf_struct_size = sizeof(struct go7007_buffer); - go->vidq.timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + go->vidq.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; go->vidq.lock = &go->queue_lock; rv = vb2_queue_init(&go->vidq); if (rv) diff --git a/drivers/staging/media/msi3101/sdr-msi3101.c b/drivers/staging/media/msi3101/sdr-msi3101.c index 4c3bf77..04ff29e 100644 --- a/drivers/staging/media/msi3101/sdr-msi3101.c +++ b/drivers/staging/media/msi3101/sdr-msi3101.c @@ -1851,7 +1851,7 @@ static int msi3101_probe(struct usb_interface *intf, s->vb_queue.buf_struct_size = sizeof(struct msi3101_frame_buf); s->vb_queue.ops = &msi3101_vb2_ops; s->vb_queue.mem_ops = &vb2_vmalloc_memops; - s->vb_queue.timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + s->vb_queue.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; ret = vb2_queue_init(&s->vb_queue); if (ret < 0) { dev_err(&s->udev->dev, "Could not initialize vb2 queue\n"); diff --git a/drivers/staging/media/omap4iss/iss_video.c b/drivers/staging/media/omap4iss/iss_video.c index 8c7f350..ded31ea 100644 --- a/drivers/staging/media/omap4iss/iss_video.c +++ b/drivers/staging/media/omap4iss/iss_video.c @@ -1074,7 +1074,7 @@ static int iss_video_open(struct file *file) q->ops = &iss_video_vb2ops; q->mem_ops = &vb2_dma_contig_memops; q->buf_struct_size = sizeof(struct iss_buffer); - q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; ret = vb2_queue_init(q); if (ret) { diff --git a/drivers/staging/media/solo6x10/solo6x10-v4l2-enc.c b/drivers/staging/media/solo6x10/solo6x10-v4l2-enc.c index ce9e5aa..edcabcd 100644 --- a/drivers/staging/media/solo6x10/solo6x10-v4l2-enc.c +++ b/drivers/staging/media/solo6x10/solo6x10-v4l2-enc.c @@ -1290,7 +1290,7 @@ static struct solo_enc_dev *solo_enc_alloc(struct solo_dev *solo_dev, solo_enc->vidq.mem_ops = &vb2_dma_sg_memops; solo_enc->vidq.drv_priv = solo_enc; solo_enc->vidq.gfp_flags = __GFP_DMA32; - solo_enc->vidq.timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + solo_enc->vidq.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; solo_enc->vidq.buf_struct_size = sizeof(struct solo_vb2_buf); solo_enc->vidq.lock = &solo_enc->lock; ret = vb2_queue_init(&solo_enc->vidq); diff --git a/drivers/staging/media/solo6x10/solo6x10-v4l2.c b/drivers/staging/media/solo6x10/solo6x10-v4l2.c index 47e72da..1815f765 100644 --- a/drivers/staging/media/solo6x10/solo6x10-v4l2.c +++ b/drivers/staging/media/solo6x10/solo6x10-v4l2.c @@ -676,7 +676,7 @@ int solo_v4l2_init(struct solo_dev *solo_dev, unsigned nr) solo_dev->vidq.ops = &solo_video_qops; solo_dev->vidq.mem_ops = &vb2_dma_contig_memops; solo_dev->vidq.drv_priv = solo_dev; - solo_dev->vidq.timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + solo_dev->vidq.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; solo_dev->vidq.gfp_flags = __GFP_DMA32; solo_dev->vidq.buf_struct_size = sizeof(struct solo_vb2_buf); solo_dev->vidq.lock = &solo_dev->lock; diff --git a/include/media/videobuf2-core.h b/include/media/videobuf2-core.h index bef53ce..3770be6 100644 --- a/include/media/videobuf2-core.h +++ b/include/media/videobuf2-core.h @@ -342,7 +342,7 @@ struct vb2_queue { const struct vb2_mem_ops *mem_ops; void *drv_priv; unsigned int buf_struct_size; - u32 timestamp_type; + u32 timestamp_flags; gfp_t gfp_flags; /* private: internal use only */ -- cgit v1.1 From c57ff79270ceef426734b3c6b4874c3e415aa743 Mon Sep 17 00:00:00 2001 From: Sakari Ailus Date: Sat, 1 Mar 2014 10:28:02 -0300 Subject: [media] v4l: Timestamp flags will soon contain timestamp source, not just type Mask out other bits when comparing timestamp types. Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab --- drivers/media/v4l2-core/videobuf2-core.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/media/v4l2-core/videobuf2-core.c b/drivers/media/v4l2-core/videobuf2-core.c index 411429c..521350a 100644 --- a/drivers/media/v4l2-core/videobuf2-core.c +++ b/drivers/media/v4l2-core/videobuf2-core.c @@ -1473,7 +1473,8 @@ static int vb2_internal_qbuf(struct vb2_queue *q, struct v4l2_buffer *b) * For output buffers copy the timestamp if needed, * and the timecode field and flag if needed. */ - if (q->timestamp_flags == V4L2_BUF_FLAG_TIMESTAMP_COPY) + if ((q->timestamp_flags & V4L2_BUF_FLAG_TIMESTAMP_MASK) == + V4L2_BUF_FLAG_TIMESTAMP_COPY) vb->v4l2_buf.timestamp = b->timestamp; vb->v4l2_buf.flags |= b->flags & V4L2_BUF_FLAG_TIMECODE; if (b->flags & V4L2_BUF_FLAG_TIMECODE) @@ -2230,7 +2231,8 @@ int vb2_queue_init(struct vb2_queue *q) return -EINVAL; /* Warn that the driver should choose an appropriate timestamp type */ - WARN_ON(q->timestamp_flags == V4L2_BUF_FLAG_TIMESTAMP_UNKNOWN); + WARN_ON((q->timestamp_flags & V4L2_BUF_FLAG_TIMESTAMP_MASK) == + V4L2_BUF_FLAG_TIMESTAMP_UNKNOWN); INIT_LIST_HEAD(&q->queued_list); INIT_LIST_HEAD(&q->done_list); -- cgit v1.1 From 872484ce40881e295b046adf21f7211306477751 Mon Sep 17 00:00:00 2001 From: Sakari Ailus Date: Sun, 25 Aug 2013 17:57:03 -0300 Subject: [media] v4l: Add timestamp source flags, mask and document them Some devices do not produce timestamps that correspond to the end of the frame. The user space should be informed on the matter. This patch achieves that by adding buffer flags (and a mask) for timestamp sources since more possible timestamping points are expected than just two. A three-bit mask is defined (V4L2_BUF_FLAG_TSTAMP_SRC_MASK) and two of the eight possible values is are defined V4L2_BUF_FLAG_TSTAMP_SRC_EOF for end of frame (value zero) V4L2_BUF_FLAG_TSTAMP_SRC_SOE for start of exposure (next value). Signed-off-by: Sakari Ailus Acked-by: Kamil Debski Acked-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/v4l/io.xml | 36 ++++++++++++++++++++++++++------ drivers/media/v4l2-core/videobuf2-core.c | 4 +++- include/media/videobuf2-core.h | 2 ++ include/uapi/linux/videodev2.h | 4 ++++ 4 files changed, 39 insertions(+), 7 deletions(-) diff --git a/Documentation/DocBook/media/v4l/io.xml b/Documentation/DocBook/media/v4l/io.xml index 5a2e97b..1e7ea3c 100644 --- a/Documentation/DocBook/media/v4l/io.xml +++ b/Documentation/DocBook/media/v4l/io.xml @@ -653,12 +653,6 @@ plane, are stored in struct v4l2_plane instead. In that case, struct v4l2_buffer contains an array of plane structures. - For timestamp types that are sampled from the system clock -(V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC) it is guaranteed that the timestamp is -taken after the complete frame has been received (or transmitted in -case of video output devices). For other kinds of -timestamps this may vary depending on the driver. -
struct <structname>v4l2_buffer</structname> @@ -1125,6 +1119,36 @@ in which case caches have not been used. The CAPTURE buffer timestamp has been taken from the corresponding OUTPUT buffer. This flag applies only to mem2mem devices. + + V4L2_BUF_FLAG_TSTAMP_SRC_MASK + 0x00070000 + Mask for timestamp sources below. The timestamp source + defines the point of time the timestamp is taken in relation to + the frame. Logical 'and' operation between the + flags field and + V4L2_BUF_FLAG_TSTAMP_SRC_MASK produces the + value of the timestamp source. + + + V4L2_BUF_FLAG_TSTAMP_SRC_EOF + 0x00000000 + End Of Frame. The buffer timestamp has been taken + when the last pixel of the frame has been received or the + last pixel of the frame has been transmitted. In practice, + software generated timestamps will typically be read from + the clock a small amount of time after the last pixel has + been received or transmitten, depending on the system and + other activity in it. + + + V4L2_BUF_FLAG_TSTAMP_SRC_SOE + 0x00010000 + Start Of Exposure. The buffer timestamp has been + taken when the exposure of the frame has begun. This is + only valid for the + V4L2_BUF_TYPE_VIDEO_CAPTURE buffer + type. +
diff --git a/drivers/media/v4l2-core/videobuf2-core.c b/drivers/media/v4l2-core/videobuf2-core.c index 521350a..42a8568 100644 --- a/drivers/media/v4l2-core/videobuf2-core.c +++ b/drivers/media/v4l2-core/videobuf2-core.c @@ -2227,7 +2227,9 @@ int vb2_queue_init(struct vb2_queue *q) WARN_ON(!q->io_modes) || WARN_ON(!q->ops->queue_setup) || WARN_ON(!q->ops->buf_queue) || - WARN_ON(q->timestamp_flags & ~V4L2_BUF_FLAG_TIMESTAMP_MASK)) + WARN_ON(q->timestamp_flags & + ~(V4L2_BUF_FLAG_TIMESTAMP_MASK | + V4L2_BUF_FLAG_TSTAMP_SRC_MASK))) return -EINVAL; /* Warn that the driver should choose an appropriate timestamp type */ diff --git a/include/media/videobuf2-core.h b/include/media/videobuf2-core.h index 3770be6..bf6859e 100644 --- a/include/media/videobuf2-core.h +++ b/include/media/videobuf2-core.h @@ -312,6 +312,8 @@ struct v4l2_fh; * @buf_struct_size: size of the driver-specific buffer structure; * "0" indicates the driver doesn't want to use a custom buffer * structure type, so sizeof(struct vb2_buffer) will is used + * @timestamp_flags: Timestamp flags; V4L2_BUF_FLAGS_TIMESTAMP_* and + * V4L2_BUF_FLAGS_TSTAMP_SRC_* * @gfp_flags: additional gfp flags used when allocating the buffers. * Typically this is 0, but it may be e.g. GFP_DMA or __GFP_DMA32 * to force the buffer allocation to a specific memory zone. diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h index cb83876..17acba8 100644 --- a/include/uapi/linux/videodev2.h +++ b/include/uapi/linux/videodev2.h @@ -700,6 +700,10 @@ struct v4l2_buffer { #define V4L2_BUF_FLAG_TIMESTAMP_UNKNOWN 0x00000000 #define V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC 0x00002000 #define V4L2_BUF_FLAG_TIMESTAMP_COPY 0x00004000 +/* Timestamp sources. */ +#define V4L2_BUF_FLAG_TSTAMP_SRC_MASK 0x00070000 +#define V4L2_BUF_FLAG_TSTAMP_SRC_EOF 0x00000000 +#define V4L2_BUF_FLAG_TSTAMP_SRC_SOE 0x00010000 /** * struct v4l2_exportbuffer - export of video buffer as DMABUF file descriptor -- cgit v1.1 From 7ce6fd8f186ba6bd22886f5d935088ff80a74277 Mon Sep 17 00:00:00 2001 From: Sakari Ailus Date: Tue, 25 Feb 2014 19:08:52 -0300 Subject: [media] v4l: Handle buffer timestamp flags correctly For COPY timestamps, buffer timestamp source flags will traverse the queue untouched. Signed-off-by: Sakari Ailus Acked-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/v4l2-core/videobuf2-core.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/media/v4l2-core/videobuf2-core.c b/drivers/media/v4l2-core/videobuf2-core.c index 42a8568..79eb9ba 100644 --- a/drivers/media/v4l2-core/videobuf2-core.c +++ b/drivers/media/v4l2-core/videobuf2-core.c @@ -488,7 +488,16 @@ static void __fill_v4l2_buffer(struct vb2_buffer *vb, struct v4l2_buffer *b) * Clear any buffer state related flags. */ b->flags &= ~V4L2_BUFFER_MASK_FLAGS; - b->flags |= q->timestamp_flags; + b->flags |= q->timestamp_flags & V4L2_BUF_FLAG_TIMESTAMP_MASK; + if ((q->timestamp_flags & V4L2_BUF_FLAG_TIMESTAMP_MASK) != + V4L2_BUF_FLAG_TIMESTAMP_COPY) { + /* + * For non-COPY timestamps, drop timestamp source bits + * and obtain the timestamp source from the queue. + */ + b->flags &= ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK; + b->flags |= q->timestamp_flags & V4L2_BUF_FLAG_TSTAMP_SRC_MASK; + } switch (vb->state) { case VB2_BUF_STATE_QUEUED: @@ -1031,6 +1040,16 @@ static void __fill_vb2_buffer(struct vb2_buffer *vb, const struct v4l2_buffer *b /* Zero flags that the vb2 core handles */ vb->v4l2_buf.flags = b->flags & ~V4L2_BUFFER_MASK_FLAGS; + if ((vb->vb2_queue->timestamp_flags & V4L2_BUF_FLAG_TIMESTAMP_MASK) != + V4L2_BUF_FLAG_TIMESTAMP_COPY || !V4L2_TYPE_IS_OUTPUT(b->type)) { + /* + * Non-COPY timestamps and non-OUTPUT queues will get + * their timestamp and timestamp source flags from the + * queue. + */ + vb->v4l2_buf.flags &= ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK; + } + if (V4L2_TYPE_IS_OUTPUT(b->type)) { /* * For output buffers mask out the timecode flag: -- cgit v1.1 From c767492a58fde9f23be92744c059dd3f21814ed4 Mon Sep 17 00:00:00 2001 From: Sakari Ailus Date: Mon, 10 Feb 2014 19:26:44 -0300 Subject: [media] uvcvideo: Tell the user space we're using start-of-exposure timestamps The UVC device provided timestamps are taken from the clock once the exposure of the frame has begun, not when the reception of the frame would have been finished as almost anywhere else. Show this to the user space by using V4L2_BUF_FLAG_TSTAMP_SRC_SOE buffer flag. Signed-off-by: Sakari Ailus Acked-by: Laurent Pinchart Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/uvc/uvc_queue.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/media/usb/uvc/uvc_queue.c b/drivers/media/usb/uvc/uvc_queue.c index 7c14616..935556e 100644 --- a/drivers/media/usb/uvc/uvc_queue.c +++ b/drivers/media/usb/uvc/uvc_queue.c @@ -151,7 +151,8 @@ int uvc_queue_init(struct uvc_video_queue *queue, enum v4l2_buf_type type, queue->queue.buf_struct_size = sizeof(struct uvc_buffer); queue->queue.ops = &uvc_queue_qops; queue->queue.mem_ops = &vb2_vmalloc_memops; - queue->queue.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + queue->queue.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC + | V4L2_BUF_FLAG_TSTAMP_SRC_SOE; ret = vb2_queue_init(&queue->queue); if (ret) return ret; -- cgit v1.1 From 599b08929efe9b90e44b504454218a120bb062a0 Mon Sep 17 00:00:00 2001 From: Sakari Ailus Date: Sat, 8 Feb 2014 13:37:59 -0300 Subject: [media] exynos-gsc, m2m-deinterlace, mx2_emmaprp: Copy v4l2_buffer data from src to dst The timestamp and timecode fields were copied from destination to source, not the other way around as they should. Fix it. Signed-off-by: Sakari Ailus Acked-by: Kamil Debski Signed-off-by: Mauro Carvalho Chehab --- drivers/media/platform/exynos-gsc/gsc-m2m.c | 4 ++-- drivers/media/platform/m2m-deinterlace.c | 4 ++-- drivers/media/platform/mx2_emmaprp.c | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/media/platform/exynos-gsc/gsc-m2m.c b/drivers/media/platform/exynos-gsc/gsc-m2m.c index 6741025..3a842ee 100644 --- a/drivers/media/platform/exynos-gsc/gsc-m2m.c +++ b/drivers/media/platform/exynos-gsc/gsc-m2m.c @@ -88,8 +88,8 @@ void gsc_m2m_job_finish(struct gsc_ctx *ctx, int vb_state) dst_vb = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx); if (src_vb && dst_vb) { - src_vb->v4l2_buf.timestamp = dst_vb->v4l2_buf.timestamp; - src_vb->v4l2_buf.timecode = dst_vb->v4l2_buf.timecode; + dst_vb->v4l2_buf.timestamp = src_vb->v4l2_buf.timestamp; + dst_vb->v4l2_buf.timecode = src_vb->v4l2_buf.timecode; v4l2_m2m_buf_done(src_vb, vb_state); v4l2_m2m_buf_done(dst_vb, vb_state); diff --git a/drivers/media/platform/m2m-deinterlace.c b/drivers/media/platform/m2m-deinterlace.c index f3a9e24..3416131 100644 --- a/drivers/media/platform/m2m-deinterlace.c +++ b/drivers/media/platform/m2m-deinterlace.c @@ -207,8 +207,8 @@ static void dma_callback(void *data) src_vb = v4l2_m2m_src_buf_remove(curr_ctx->m2m_ctx); dst_vb = v4l2_m2m_dst_buf_remove(curr_ctx->m2m_ctx); - src_vb->v4l2_buf.timestamp = dst_vb->v4l2_buf.timestamp; - src_vb->v4l2_buf.timecode = dst_vb->v4l2_buf.timecode; + dst_vb->v4l2_buf.timestamp = src_vb->v4l2_buf.timestamp; + dst_vb->v4l2_buf.timecode = src_vb->v4l2_buf.timecode; v4l2_m2m_buf_done(src_vb, VB2_BUF_STATE_DONE); v4l2_m2m_buf_done(dst_vb, VB2_BUF_STATE_DONE); diff --git a/drivers/media/platform/mx2_emmaprp.c b/drivers/media/platform/mx2_emmaprp.c index af3e106..6debb02 100644 --- a/drivers/media/platform/mx2_emmaprp.c +++ b/drivers/media/platform/mx2_emmaprp.c @@ -377,8 +377,8 @@ static irqreturn_t emmaprp_irq(int irq_emma, void *data) src_vb = v4l2_m2m_src_buf_remove(curr_ctx->m2m_ctx); dst_vb = v4l2_m2m_dst_buf_remove(curr_ctx->m2m_ctx); - src_vb->v4l2_buf.timestamp = dst_vb->v4l2_buf.timestamp; - src_vb->v4l2_buf.timecode = dst_vb->v4l2_buf.timecode; + dst_vb->v4l2_buf.timestamp = src_vb->v4l2_buf.timestamp; + dst_vb->v4l2_buf.timecode = src_vb->v4l2_buf.timecode; spin_lock_irqsave(&pcdev->irqlock, flags); v4l2_m2m_buf_done(src_vb, VB2_BUF_STATE_DONE); -- cgit v1.1 From 309f4d62eda0e864c2d4eef536cc82e41931c3c5 Mon Sep 17 00:00:00 2001 From: Sakari Ailus Date: Sat, 8 Feb 2014 14:21:35 -0300 Subject: [media] v4l: Copy timestamp source flags to destination on m2m devices Copy the flags containing the timestamp source from source buffer flags to the destination buffer flags on memory-to-memory devices. This is analogous to copying the timestamp field from source to destination. Signed-off-by: Sakari Ailus Acked-by: Kamil Debski Signed-off-by: Mauro Carvalho Chehab --- drivers/media/platform/coda.c | 3 +++ drivers/media/platform/exynos-gsc/gsc-m2m.c | 4 ++++ drivers/media/platform/exynos4-is/fimc-m2m.c | 3 +++ drivers/media/platform/m2m-deinterlace.c | 3 +++ drivers/media/platform/mem2mem_testdev.c | 3 +++ drivers/media/platform/mx2_emmaprp.c | 5 +++++ drivers/media/platform/s5p-g2d/g2d.c | 3 +++ drivers/media/platform/s5p-jpeg/jpeg-core.c | 3 +++ drivers/media/platform/s5p-mfc/s5p_mfc.c | 5 +++++ drivers/media/platform/ti-vpe/vpe.c | 2 ++ 10 files changed, 34 insertions(+) diff --git a/drivers/media/platform/coda.c b/drivers/media/platform/coda.c index 81b6f7b..3e5199e 100644 --- a/drivers/media/platform/coda.c +++ b/drivers/media/platform/coda.c @@ -2829,6 +2829,9 @@ static void coda_finish_encode(struct coda_ctx *ctx) } dst_buf->v4l2_buf.timestamp = src_buf->v4l2_buf.timestamp; + dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK; + dst_buf->v4l2_buf.flags |= + src_buf->v4l2_buf.flags & V4L2_BUF_FLAG_TSTAMP_SRC_MASK; dst_buf->v4l2_buf.timecode = src_buf->v4l2_buf.timecode; v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE); diff --git a/drivers/media/platform/exynos-gsc/gsc-m2m.c b/drivers/media/platform/exynos-gsc/gsc-m2m.c index 3a842ee..d0ea94f 100644 --- a/drivers/media/platform/exynos-gsc/gsc-m2m.c +++ b/drivers/media/platform/exynos-gsc/gsc-m2m.c @@ -90,6 +90,10 @@ void gsc_m2m_job_finish(struct gsc_ctx *ctx, int vb_state) if (src_vb && dst_vb) { dst_vb->v4l2_buf.timestamp = src_vb->v4l2_buf.timestamp; dst_vb->v4l2_buf.timecode = src_vb->v4l2_buf.timecode; + dst_vb->v4l2_buf.flags &= ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK; + dst_vb->v4l2_buf.flags |= + src_vb->v4l2_buf.flags + & V4L2_BUF_FLAG_TSTAMP_SRC_MASK; v4l2_m2m_buf_done(src_vb, vb_state); v4l2_m2m_buf_done(dst_vb, vb_state); diff --git a/drivers/media/platform/exynos4-is/fimc-m2m.c b/drivers/media/platform/exynos4-is/fimc-m2m.c index bfc900d..36971d9 100644 --- a/drivers/media/platform/exynos4-is/fimc-m2m.c +++ b/drivers/media/platform/exynos4-is/fimc-m2m.c @@ -134,6 +134,9 @@ static void fimc_device_run(void *priv) goto dma_unlock; dst_vb->v4l2_buf.timestamp = src_vb->v4l2_buf.timestamp; + dst_vb->v4l2_buf.flags &= ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK; + dst_vb->v4l2_buf.flags |= + src_vb->v4l2_buf.flags & V4L2_BUF_FLAG_TSTAMP_SRC_MASK; /* Reconfigure hardware if the context has changed. */ if (fimc->m2m.ctx != ctx) { diff --git a/drivers/media/platform/m2m-deinterlace.c b/drivers/media/platform/m2m-deinterlace.c index 3416131..c21d14f 100644 --- a/drivers/media/platform/m2m-deinterlace.c +++ b/drivers/media/platform/m2m-deinterlace.c @@ -208,6 +208,9 @@ static void dma_callback(void *data) dst_vb = v4l2_m2m_dst_buf_remove(curr_ctx->m2m_ctx); dst_vb->v4l2_buf.timestamp = src_vb->v4l2_buf.timestamp; + dst_vb->v4l2_buf.flags &= ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK; + dst_vb->v4l2_buf.flags |= + src_vb->v4l2_buf.flags & V4L2_BUF_FLAG_TSTAMP_SRC_MASK; dst_vb->v4l2_buf.timecode = src_vb->v4l2_buf.timecode; v4l2_m2m_buf_done(src_vb, VB2_BUF_STATE_DONE); diff --git a/drivers/media/platform/mem2mem_testdev.c b/drivers/media/platform/mem2mem_testdev.c index 02a40c5..4bb5e88 100644 --- a/drivers/media/platform/mem2mem_testdev.c +++ b/drivers/media/platform/mem2mem_testdev.c @@ -239,6 +239,9 @@ static int device_process(struct m2mtest_ctx *ctx, memcpy(&out_vb->v4l2_buf.timestamp, &in_vb->v4l2_buf.timestamp, sizeof(struct timeval)); + out_vb->v4l2_buf.flags &= ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK; + out_vb->v4l2_buf.flags |= + in_vb->v4l2_buf.flags & V4L2_BUF_FLAG_TSTAMP_SRC_MASK; switch (ctx->mode) { case MEM2MEM_HFLIP | MEM2MEM_VFLIP: diff --git a/drivers/media/platform/mx2_emmaprp.c b/drivers/media/platform/mx2_emmaprp.c index 6debb02..0b7480e 100644 --- a/drivers/media/platform/mx2_emmaprp.c +++ b/drivers/media/platform/mx2_emmaprp.c @@ -378,6 +378,11 @@ static irqreturn_t emmaprp_irq(int irq_emma, void *data) dst_vb = v4l2_m2m_dst_buf_remove(curr_ctx->m2m_ctx); dst_vb->v4l2_buf.timestamp = src_vb->v4l2_buf.timestamp; + dst_vb->v4l2_buf.flags &= + ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK; + dst_vb->v4l2_buf.flags |= + src_vb->v4l2_buf.flags + & V4L2_BUF_FLAG_TSTAMP_SRC_MASK; dst_vb->v4l2_buf.timecode = src_vb->v4l2_buf.timecode; spin_lock_irqsave(&pcdev->irqlock, flags); diff --git a/drivers/media/platform/s5p-g2d/g2d.c b/drivers/media/platform/s5p-g2d/g2d.c index bf7c9b3..357af1e 100644 --- a/drivers/media/platform/s5p-g2d/g2d.c +++ b/drivers/media/platform/s5p-g2d/g2d.c @@ -560,6 +560,9 @@ static irqreturn_t g2d_isr(int irq, void *prv) dst->v4l2_buf.timecode = src->v4l2_buf.timecode; dst->v4l2_buf.timestamp = src->v4l2_buf.timestamp; + dst->v4l2_buf.flags &= ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK; + dst->v4l2_buf.flags |= + src->v4l2_buf.flags & V4L2_BUF_FLAG_TSTAMP_SRC_MASK; v4l2_m2m_buf_done(src, VB2_BUF_STATE_DONE); v4l2_m2m_buf_done(dst, VB2_BUF_STATE_DONE); diff --git a/drivers/media/platform/s5p-jpeg/jpeg-core.c b/drivers/media/platform/s5p-jpeg/jpeg-core.c index f5e9870..da0ad88 100644 --- a/drivers/media/platform/s5p-jpeg/jpeg-core.c +++ b/drivers/media/platform/s5p-jpeg/jpeg-core.c @@ -1766,6 +1766,9 @@ static irqreturn_t s5p_jpeg_irq(int irq, void *dev_id) dst_buf->v4l2_buf.timecode = src_buf->v4l2_buf.timecode; dst_buf->v4l2_buf.timestamp = src_buf->v4l2_buf.timestamp; + dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK; + dst_buf->v4l2_buf.flags |= + src_buf->v4l2_buf.flags & V4L2_BUF_FLAG_TSTAMP_SRC_MASK; v4l2_m2m_buf_done(src_buf, state); if (curr_ctx->mode == S5P_JPEG_ENCODE) diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc.c b/drivers/media/platform/s5p-mfc/s5p_mfc.c index 0e8c171..0c47199 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc.c +++ b/drivers/media/platform/s5p-mfc/s5p_mfc.c @@ -232,6 +232,11 @@ static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx *ctx) src_buf->b->v4l2_buf.timecode; dst_buf->b->v4l2_buf.timestamp = src_buf->b->v4l2_buf.timestamp; + dst_buf->b->v4l2_buf.flags &= + ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK; + dst_buf->b->v4l2_buf.flags |= + src_buf->b->v4l2_buf.flags + & V4L2_BUF_FLAG_TSTAMP_SRC_MASK; switch (frame_type) { case S5P_FIMV_DECODE_FRAME_I_FRAME: dst_buf->b->v4l2_buf.flags |= diff --git a/drivers/media/platform/ti-vpe/vpe.c b/drivers/media/platform/ti-vpe/vpe.c index 8ea3b89..7a77a5b 100644 --- a/drivers/media/platform/ti-vpe/vpe.c +++ b/drivers/media/platform/ti-vpe/vpe.c @@ -1278,6 +1278,8 @@ static irqreturn_t vpe_irq(int irq_vpe, void *data) d_buf = &d_vb->v4l2_buf; d_buf->timestamp = s_buf->timestamp; + d_buf->flags &= ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK; + d_buf->flags |= s_buf->flags & V4L2_BUF_FLAG_TSTAMP_SRC_MASK; if (s_buf->flags & V4L2_BUF_FLAG_TIMECODE) { d_buf->flags |= V4L2_BUF_FLAG_TIMECODE; d_buf->timecode = s_buf->timecode; -- cgit v1.1 From bfd0306462fdbc5e0a8c6999aef9dde0f9745399 Mon Sep 17 00:00:00 2001 From: Sakari Ailus Date: Fri, 7 Feb 2014 19:44:39 -0300 Subject: [media] v4l: Document timestamp buffer flag behaviour Timestamp buffer flags are constant at the moment. Document them so that 1) they're always valid and 2) not changed by the drivers. This leaves room to extend the functionality later on if needed. Signed-off-by: Sakari Ailus Acked-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/v4l/io.xml | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/DocBook/media/v4l/io.xml b/Documentation/DocBook/media/v4l/io.xml index 1e7ea3c..49e48be 100644 --- a/Documentation/DocBook/media/v4l/io.xml +++ b/Documentation/DocBook/media/v4l/io.xml @@ -653,6 +653,20 @@ plane, are stored in struct v4l2_plane instead. In that case, struct v4l2_buffer contains an array of plane structures. + Dequeued video buffers come with timestamps. The driver + decides at which part of the frame and with which clock the + timestamp is taken. Please see flags in the masks + V4L2_BUF_FLAG_TIMESTAMP_MASK and + V4L2_BUF_FLAG_TSTAMP_SRC_MASK in . These flags are always valid and constant + across all buffers during the whole video stream. Changes in these + flags may take place as a side effect of &VIDIOC-S-INPUT; or + &VIDIOC-S-OUTPUT; however. The + V4L2_BUF_FLAG_TIMESTAMP_COPY timestamp type + which is used by e.g. on mem-to-mem devices is an exception to the + rule: the timestamp source flags are copied from the OUTPUT video + buffer to the CAPTURE video buffer. + struct <structname>v4l2_buffer</structname> -- cgit v1.1 From b1e43f232698274871e1358c276d7b0242a7d607 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Sun, 16 Feb 2014 06:59:32 -0300 Subject: [media] uvcvideo: Do not use usb_set_interface on bulk EP The UVC specification uses alternate setting selection to notify devices of stream start/stop. This breaks when using bulk-based devices, as the video streaming interface has a single alternate setting in that case, making video stream start and video stream stop events to appear identical to the device. Bulk-based devices are thus not well supported by UVC. The webcam built in the Asus Zenbook UX302LA ignores the set interface request and will keep the video stream enabled when the driver tries to stop it. If USB autosuspend is enabled the device will then be suspended and will crash, requiring a cold reboot. USB trace capture showed that Windows sends a CLEAR_FEATURE(HALT) request to the bulk endpoint when stopping the stream instead of selecting alternate setting 0. The camera then behaves correctly, and thus seems to require that behaviour. Replace selection of alternate setting 0 with clearing of the endpoint halt feature at video stream stop for bulk-based devices. Let's refrain from blaming Microsoft this time, as it's not clear whether this Windows-specific but USB-compliant behaviour was specifically developed to handle bulkd-based UVC devices, or if the camera just took advantage of it. CC: stable@vger.kernel.org Signed-off-by: Oleksij Rempel Signed-off-by: Laurent Pinchart Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/uvc/uvc_video.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/media/usb/uvc/uvc_video.c b/drivers/media/usb/uvc/uvc_video.c index 103cd4e..8d52baf 100644 --- a/drivers/media/usb/uvc/uvc_video.c +++ b/drivers/media/usb/uvc/uvc_video.c @@ -1850,7 +1850,25 @@ int uvc_video_enable(struct uvc_streaming *stream, int enable) if (!enable) { uvc_uninit_video(stream, 1); - usb_set_interface(stream->dev->udev, stream->intfnum, 0); + if (stream->intf->num_altsetting > 1) { + usb_set_interface(stream->dev->udev, + stream->intfnum, 0); + } else { + /* UVC doesn't specify how to inform a bulk-based device + * when the video stream is stopped. Windows sends a + * CLEAR_FEATURE(HALT) request to the video streaming + * bulk endpoint, mimic the same behaviour. + */ + unsigned int epnum = stream->header.bEndpointAddress + & USB_ENDPOINT_NUMBER_MASK; + unsigned int dir = stream->header.bEndpointAddress + & USB_ENDPOINT_DIR_MASK; + unsigned int pipe; + + pipe = usb_sndbulkpipe(stream->dev->udev, epnum) | dir; + usb_clear_halt(stream->dev->udev, pipe); + } + uvc_queue_enable(&stream->queue, 0); uvc_video_clock_cleanup(stream); return 0; -- cgit v1.1 From e72ed08e66d044ed74c485da68ca809bebf99739 Mon Sep 17 00:00:00 2001 From: Edgar Thier Date: Thu, 20 Feb 2014 04:12:51 -0300 Subject: [media] uvcvideo: Add bayer 8-bit patterns to uvcvideo Add bayer 8-bit GUIDs to uvcvideo and associated them with the corresponding V4L2 pixel formats. Signed-off-by: Edgar Thier Signed-off-by: Laurent Pinchart Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/uvc/uvc_driver.c | 22 +++++++++++++++++++++- drivers/media/usb/uvc/uvcvideo.h | 12 ++++++++++++ 2 files changed, 33 insertions(+), 1 deletion(-) diff --git a/drivers/media/usb/uvc/uvc_driver.c b/drivers/media/usb/uvc/uvc_driver.c index b6cac17..ad47c5c 100644 --- a/drivers/media/usb/uvc/uvc_driver.c +++ b/drivers/media/usb/uvc/uvc_driver.c @@ -108,11 +108,31 @@ static struct uvc_format_desc uvc_fmts[] = { .fcc = V4L2_PIX_FMT_Y16, }, { - .name = "RGB Bayer", + .name = "BGGR Bayer (BY8 )", .guid = UVC_GUID_FORMAT_BY8, .fcc = V4L2_PIX_FMT_SBGGR8, }, { + .name = "BGGR Bayer (BA81)", + .guid = UVC_GUID_FORMAT_BA81, + .fcc = V4L2_PIX_FMT_SBGGR8, + }, + { + .name = "GBRG Bayer (GBRG)", + .guid = UVC_GUID_FORMAT_GBRG, + .fcc = V4L2_PIX_FMT_SGBRG8, + }, + { + .name = "GRBG Bayer (GRBG)", + .guid = UVC_GUID_FORMAT_GRBG, + .fcc = V4L2_PIX_FMT_SGRBG8, + }, + { + .name = "RGGB Bayer (RGGB)", + .guid = UVC_GUID_FORMAT_RGGB, + .fcc = V4L2_PIX_FMT_SRGGB8, + }, + { .name = "RGB565", .guid = UVC_GUID_FORMAT_RGBP, .fcc = V4L2_PIX_FMT_RGB565, diff --git a/drivers/media/usb/uvc/uvcvideo.h b/drivers/media/usb/uvc/uvcvideo.h index 143d5e5..b1f69a6 100644 --- a/drivers/media/usb/uvc/uvcvideo.h +++ b/drivers/media/usb/uvc/uvcvideo.h @@ -94,6 +94,18 @@ #define UVC_GUID_FORMAT_BY8 \ { 'B', 'Y', '8', ' ', 0x00, 0x00, 0x10, 0x00, \ 0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71} +#define UVC_GUID_FORMAT_BA81 \ + { 'B', 'A', '8', '1', 0x00, 0x00, 0x10, 0x00, \ + 0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71} +#define UVC_GUID_FORMAT_GBRG \ + { 'G', 'B', 'R', 'G', 0x00, 0x00, 0x10, 0x00, \ + 0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71} +#define UVC_GUID_FORMAT_GRBG \ + { 'G', 'R', 'B', 'G', 0x00, 0x00, 0x10, 0x00, \ + 0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71} +#define UVC_GUID_FORMAT_RGGB \ + { 'R', 'G', 'G', 'B', 0x00, 0x00, 0x10, 0x00, \ + 0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71} #define UVC_GUID_FORMAT_RGBP \ { 'R', 'G', 'B', 'P', 0x00, 0x00, 0x10, 0x00, \ 0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71} -- cgit v1.1 From 25aeb418c6628787fb534b114cb47de76583a27c Mon Sep 17 00:00:00 2001 From: "Lad, Prabhakar" Date: Fri, 21 Feb 2014 09:07:21 -0300 Subject: [media] omap3isp: Fix typos Signed-off-by: Lad, Prabhakar Signed-off-by: Laurent Pinchart Signed-off-by: Mauro Carvalho Chehab --- drivers/media/platform/omap3isp/isp.c | 2 +- drivers/media/platform/omap3isp/ispccdc.c | 2 +- drivers/media/platform/omap3isp/ispccp2.c | 4 ++-- drivers/media/platform/omap3isp/isphist.c | 2 +- drivers/media/platform/omap3isp/isppreview.c | 4 ++-- drivers/media/platform/omap3isp/ispqueue.c | 2 +- drivers/media/platform/omap3isp/ispresizer.h | 4 ++-- drivers/media/platform/omap3isp/ispstat.c | 4 ++-- 8 files changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/media/platform/omap3isp/isp.c b/drivers/media/platform/omap3isp/isp.c index 5807185..65a9b1d 100644 --- a/drivers/media/platform/omap3isp/isp.c +++ b/drivers/media/platform/omap3isp/isp.c @@ -391,7 +391,7 @@ static void isp_disable_interrupts(struct isp_device *isp) * @isp: OMAP3 ISP device * @idle: Consider idle state. * - * Set the power settings for the ISP and SBL bus and cConfigure the HS/VS + * Set the power settings for the ISP and SBL bus and configure the HS/VS * interrupt source. * * We need to configure the HS/VS interrupt source before interrupts get diff --git a/drivers/media/platform/omap3isp/ispccdc.c b/drivers/media/platform/omap3isp/ispccdc.c index 5db2c88..7160e4a 100644 --- a/drivers/media/platform/omap3isp/ispccdc.c +++ b/drivers/media/platform/omap3isp/ispccdc.c @@ -293,7 +293,7 @@ static int __ccdc_lsc_enable(struct isp_ccdc_device *ccdc, int enable) isp_reg_clr(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_LSC_CONFIG, ISPCCDC_LSC_ENABLE); ccdc->lsc.state = LSC_STATE_STOPPED; - dev_warn(to_device(ccdc), "LSC prefecth timeout\n"); + dev_warn(to_device(ccdc), "LSC prefetch timeout\n"); return -ETIMEDOUT; } ccdc->lsc.state = LSC_STATE_RUNNING; diff --git a/drivers/media/platform/omap3isp/ispccp2.c b/drivers/media/platform/omap3isp/ispccp2.c index e84fe05..c81ca8f 100644 --- a/drivers/media/platform/omap3isp/ispccp2.c +++ b/drivers/media/platform/omap3isp/ispccp2.c @@ -518,7 +518,7 @@ static void ccp2_mem_configure(struct isp_ccp2_device *ccp2, ISPCCP2_LCM_IRQSTATUS_EOF_IRQ, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_IRQSTATUS); - /* Enable LCM interupts */ + /* Enable LCM interrupts */ isp_reg_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_IRQENABLE, ISPCCP2_LCM_IRQSTATUS_EOF_IRQ | ISPCCP2_LCM_IRQSTATUS_OCPERROR_IRQ); @@ -1096,7 +1096,7 @@ static int ccp2_init_entities(struct isp_ccp2_device *ccp2) * implementation we use a fixed 32 bytes alignment regardless of the * input format and width. If strict 128 bits alignment support is * required ispvideo will need to be made aware of this special dual - * alignement requirements. + * alignment requirements. */ ccp2->video_in.type = V4L2_BUF_TYPE_VIDEO_OUTPUT; ccp2->video_in.bpl_alignment = 32; diff --git a/drivers/media/platform/omap3isp/isphist.c b/drivers/media/platform/omap3isp/isphist.c index e070c24..6db6cfb 100644 --- a/drivers/media/platform/omap3isp/isphist.c +++ b/drivers/media/platform/omap3isp/isphist.c @@ -351,7 +351,7 @@ static int hist_validate_params(struct ispstat *hist, void *new_conf) buf_size = hist_get_buf_size(user_cfg); if (buf_size > user_cfg->buf_size) - /* User's buf_size request wasn't enoght */ + /* User's buf_size request wasn't enough */ user_cfg->buf_size = buf_size; else if (user_cfg->buf_size > OMAP3ISP_HIST_MAX_BUF_SIZE) user_cfg->buf_size = OMAP3ISP_HIST_MAX_BUF_SIZE; diff --git a/drivers/media/platform/omap3isp/isppreview.c b/drivers/media/platform/omap3isp/isppreview.c index 1dbff14..fe91a3b 100644 --- a/drivers/media/platform/omap3isp/isppreview.c +++ b/drivers/media/platform/omap3isp/isppreview.c @@ -122,7 +122,7 @@ static struct omap3isp_prev_csc flr_prev_csc = { #define PREV_MAX_OUT_WIDTH_REV_15 4096 /* - * Coeficient Tables for the submodules in Preview. + * Coefficient Tables for the submodules in Preview. * Array is initialised with the values from.the tables text file. */ @@ -1372,7 +1372,7 @@ static void preview_init_params(struct isp_prev_device *prev) } /* - * preview_max_out_width - Handle previewer hardware ouput limitations + * preview_max_out_width - Handle previewer hardware output limitations * @isp_revision : ISP revision * returns maximum width output for current isp revision */ diff --git a/drivers/media/platform/omap3isp/ispqueue.c b/drivers/media/platform/omap3isp/ispqueue.c index 5f0f8fa..a5e6585 100644 --- a/drivers/media/platform/omap3isp/ispqueue.c +++ b/drivers/media/platform/omap3isp/ispqueue.c @@ -597,7 +597,7 @@ static int isp_video_buffer_wait(struct isp_video_buffer *buf, int nonblocking) * isp_video_queue_free - Free video buffers memory * * Buffers can only be freed if the queue isn't streaming and if no buffer is - * mapped to userspace. Return -EBUSY if those conditions aren't statisfied. + * mapped to userspace. Return -EBUSY if those conditions aren't satisfied. * * This function must be called with the queue lock held. */ diff --git a/drivers/media/platform/omap3isp/ispresizer.h b/drivers/media/platform/omap3isp/ispresizer.h index 70c1c0e..9b01e90 100644 --- a/drivers/media/platform/omap3isp/ispresizer.h +++ b/drivers/media/platform/omap3isp/ispresizer.h @@ -30,12 +30,12 @@ #include /* - * Constants for filter coefficents count + * Constants for filter coefficients count */ #define COEFF_CNT 32 /* - * struct isprsz_coef - Structure for resizer filter coeffcients. + * struct isprsz_coef - Structure for resizer filter coefficients. * @h_filter_coef_4tap: Horizontal filter coefficients for 8-phase/4-tap * mode (.5x-4x) * @v_filter_coef_4tap: Vertical filter coefficients for 8-phase/4-tap diff --git a/drivers/media/platform/omap3isp/ispstat.c b/drivers/media/platform/omap3isp/ispstat.c index a75407c..5707f85 100644 --- a/drivers/media/platform/omap3isp/ispstat.c +++ b/drivers/media/platform/omap3isp/ispstat.c @@ -144,7 +144,7 @@ static int isp_stat_buf_check_magic(struct ispstat *stat, for (w = buf->virt_addr + buf_size, end = w + MAGIC_SIZE; w < end; w++) { if (unlikely(*w != MAGIC_NUM)) { - dev_dbg(stat->isp->dev, "%s: endding magic check does " + dev_dbg(stat->isp->dev, "%s: ending magic check does " "not match.\n", stat->subdev.name); return -EINVAL; } @@ -841,7 +841,7 @@ int omap3isp_stat_s_stream(struct v4l2_subdev *subdev, int enable) if (enable) { /* * Only set enable PCR bit if the module was previously - * enabled through ioct. + * enabled through ioctl. */ isp_stat_try_enable(stat); } else { -- cgit v1.1 From fdf7bbe24d612dab8a8dc8962fdd7c0a1ac49c30 Mon Sep 17 00:00:00 2001 From: "Lad, Prabhakar" Date: Fri, 21 Feb 2014 09:07:22 -0300 Subject: [media] omap3isp: ispccdc: Remove unwanted comments This patch removes the description of members which does not exists for ispccdc_lsc structure. Signed-off-by: Lad, Prabhakar Signed-off-by: Laurent Pinchart Signed-off-by: Mauro Carvalho Chehab --- drivers/media/platform/omap3isp/ispccdc.h | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/media/platform/omap3isp/ispccdc.h b/drivers/media/platform/omap3isp/ispccdc.h index a5da9e1..9d24e41 100644 --- a/drivers/media/platform/omap3isp/ispccdc.h +++ b/drivers/media/platform/omap3isp/ispccdc.h @@ -63,12 +63,6 @@ struct ispccdc_lsc_config_req { /* * ispccdc_lsc - CCDC LSC parameters - * @update_config: Set when user changes config - * @request_enable: Whether LSC is requested to be enabled - * @config: LSC config set by user - * @update_table: Set when user provides a new LSC table to table_new - * @table_new: LSC table set by user, ISP address - * @table_inuse: LSC table currently in use, ISP address */ struct ispccdc_lsc { enum ispccdc_lsc_state state; -- cgit v1.1 From 872aba5103b2d4884a7d8790172b4c8951e52a78 Mon Sep 17 00:00:00 2001 From: "Lad, Prabhakar" Date: Fri, 21 Feb 2014 09:07:23 -0300 Subject: [media] omap3isp: Rename the variable names in description This patch renames the variable in the description to match it appropriately to function definition. Signed-off-by: Lad, Prabhakar Signed-off-by: Laurent Pinchart Signed-off-by: Mauro Carvalho Chehab --- drivers/media/platform/omap3isp/isp.h | 12 ++++++------ drivers/media/platform/omap3isp/ispccdc.c | 8 ++++---- drivers/media/platform/omap3isp/ispccp2.c | 2 +- drivers/media/platform/omap3isp/isphist.c | 2 +- drivers/media/platform/omap3isp/isppreview.c | 9 +++++---- drivers/media/platform/omap3isp/ispresizer.c | 6 +++--- drivers/media/platform/omap3isp/ispvideo.c | 4 ++-- 7 files changed, 22 insertions(+), 21 deletions(-) diff --git a/drivers/media/platform/omap3isp/isp.h b/drivers/media/platform/omap3isp/isp.h index 081f5ec..6d5e697 100644 --- a/drivers/media/platform/omap3isp/isp.h +++ b/drivers/media/platform/omap3isp/isp.h @@ -265,7 +265,7 @@ void omap3isp_unregister_entities(struct platform_device *pdev); /* * isp_reg_readl - Read value of an OMAP3 ISP register - * @dev: Device pointer specific to the OMAP3 ISP. + * @isp: Device pointer specific to the OMAP3 ISP. * @isp_mmio_range: Range to which the register offset refers to. * @reg_offset: Register offset to read from. * @@ -280,7 +280,7 @@ u32 isp_reg_readl(struct isp_device *isp, enum isp_mem_resources isp_mmio_range, /* * isp_reg_writel - Write value to an OMAP3 ISP register - * @dev: Device pointer specific to the OMAP3 ISP. + * @isp: Device pointer specific to the OMAP3 ISP. * @reg_value: 32 bit value to write to the register. * @isp_mmio_range: Range to which the register offset refers to. * @reg_offset: Register offset to write into. @@ -293,8 +293,8 @@ void isp_reg_writel(struct isp_device *isp, u32 reg_value, } /* - * isp_reg_and - Clear individual bits in an OMAP3 ISP register - * @dev: Device pointer specific to the OMAP3 ISP. + * isp_reg_clr - Clear individual bits in an OMAP3 ISP register + * @isp: Device pointer specific to the OMAP3 ISP. * @mmio_range: Range to which the register offset refers to. * @reg: Register offset to work on. * @clr_bits: 32 bit value which would be cleared in the register. @@ -310,7 +310,7 @@ void isp_reg_clr(struct isp_device *isp, enum isp_mem_resources mmio_range, /* * isp_reg_set - Set individual bits in an OMAP3 ISP register - * @dev: Device pointer specific to the OMAP3 ISP. + * @isp: Device pointer specific to the OMAP3 ISP. * @mmio_range: Range to which the register offset refers to. * @reg: Register offset to work on. * @set_bits: 32 bit value which would be set in the register. @@ -326,7 +326,7 @@ void isp_reg_set(struct isp_device *isp, enum isp_mem_resources mmio_range, /* * isp_reg_clr_set - Clear and set invidial bits in an OMAP3 ISP register - * @dev: Device pointer specific to the OMAP3 ISP. + * @isp: Device pointer specific to the OMAP3 ISP. * @mmio_range: Range to which the register offset refers to. * @reg: Register offset to work on. * @clr_bits: 32 bit value which would be cleared in the register. diff --git a/drivers/media/platform/omap3isp/ispccdc.c b/drivers/media/platform/omap3isp/ispccdc.c index 7160e4a..4d920c8 100644 --- a/drivers/media/platform/omap3isp/ispccdc.c +++ b/drivers/media/platform/omap3isp/ispccdc.c @@ -674,7 +674,7 @@ static void ccdc_config_imgattr(struct isp_ccdc_device *ccdc, u32 colptn) /* * ccdc_config - Set CCDC configuration from userspace * @ccdc: Pointer to ISP CCDC device. - * @userspace_add: Structure containing CCDC configuration sent from userspace. + * @ccdc_struct: Structure containing CCDC configuration sent from userspace. * * Returns 0 if successful, -EINVAL if the pointer to the configuration * structure is null, or the copy_from_user function fails to copy user space @@ -793,7 +793,7 @@ static void ccdc_apply_controls(struct isp_ccdc_device *ccdc) /* * omap3isp_ccdc_restore_context - Restore values of the CCDC module registers - * @dev: Pointer to ISP device + * @isp: Pointer to ISP device */ void omap3isp_ccdc_restore_context(struct isp_device *isp) { @@ -2525,7 +2525,7 @@ error_video: /* * omap3isp_ccdc_init - CCDC module initialization. - * @dev: Device pointer specific to the OMAP3 ISP. + * @isp: Device pointer specific to the OMAP3 ISP. * * TODO: Get the initialisation values from platform data. * @@ -2564,7 +2564,7 @@ int omap3isp_ccdc_init(struct isp_device *isp) /* * omap3isp_ccdc_cleanup - CCDC module cleanup. - * @dev: Device pointer specific to the OMAP3 ISP. + * @isp: Device pointer specific to the OMAP3 ISP. */ void omap3isp_ccdc_cleanup(struct isp_device *isp) { diff --git a/drivers/media/platform/omap3isp/ispccp2.c b/drivers/media/platform/omap3isp/ispccp2.c index c81ca8f..b30b67d 100644 --- a/drivers/media/platform/omap3isp/ispccp2.c +++ b/drivers/media/platform/omap3isp/ispccp2.c @@ -211,7 +211,7 @@ static void ccp2_mem_enable(struct isp_ccp2_device *ccp2, u8 enable) /* * ccp2_phyif_config - Initialize CCP2 phy interface config * @ccp2: Pointer to ISP CCP2 device - * @config: CCP2 platform data + * @pdata: CCP2 platform data * * Configure the CCP2 physical interface module from platform data. * diff --git a/drivers/media/platform/omap3isp/isphist.c b/drivers/media/platform/omap3isp/isphist.c index 6db6cfb..06a5f81 100644 --- a/drivers/media/platform/omap3isp/isphist.c +++ b/drivers/media/platform/omap3isp/isphist.c @@ -299,7 +299,7 @@ static u32 hist_get_buf_size(struct omap3isp_hist_config *conf) /* * hist_validate_params - Helper function to check user given params. - * @user_cfg: Pointer to user configuration structure. + * @new_conf: Pointer to user configuration structure. * * Returns 0 on success configuration. */ diff --git a/drivers/media/platform/omap3isp/isppreview.c b/drivers/media/platform/omap3isp/isppreview.c index fe91a3b..395b2b0 100644 --- a/drivers/media/platform/omap3isp/isppreview.c +++ b/drivers/media/platform/omap3isp/isppreview.c @@ -971,7 +971,8 @@ static void preview_setup_hw(struct isp_prev_device *prev, u32 update, /* * preview_config_ycpos - Configure byte layout of YUV image. - * @mode: Indicates the required byte layout. + * @prev: pointer to previewer private structure + * @pixelcode: pixel code */ static void preview_config_ycpos(struct isp_prev_device *prev, @@ -1373,7 +1374,7 @@ static void preview_init_params(struct isp_prev_device *prev) /* * preview_max_out_width - Handle previewer hardware output limitations - * @isp_revision : ISP revision + * @prev: pointer to previewer private structure * returns maximum width output for current isp revision */ static unsigned int preview_max_out_width(struct isp_prev_device *prev) @@ -1619,7 +1620,7 @@ static const struct v4l2_ctrl_ops preview_ctrl_ops = { /* * preview_ioctl - Handle preview module private ioctl's - * @prev: pointer to preview context structure + * @sd: pointer to v4l2 subdev structure * @cmd: configuration command * @arg: configuration argument * return -EINVAL or zero on success @@ -2350,7 +2351,7 @@ error_video_in: /* * omap3isp_preview_init - Previewer initialization. - * @dev : Pointer to ISP device + * @isp : Pointer to ISP device * return -ENOMEM or zero on success */ int omap3isp_preview_init(struct isp_device *isp) diff --git a/drivers/media/platform/omap3isp/ispresizer.c b/drivers/media/platform/omap3isp/ispresizer.c index 0d36b8b..86369df 100644 --- a/drivers/media/platform/omap3isp/ispresizer.c +++ b/drivers/media/platform/omap3isp/ispresizer.c @@ -206,7 +206,7 @@ static void resizer_set_bilinear(struct isp_res_device *res, /* * resizer_set_ycpos - Luminance and chrominance order * @res: Device context. - * @order: order type. + * @pixelcode: pixel code. */ static void resizer_set_ycpos(struct isp_res_device *res, enum v4l2_mbus_pixelcode pixelcode) @@ -918,8 +918,8 @@ static void resizer_calc_ratios(struct isp_res_device *res, /* * resizer_set_crop_params - Setup hardware with cropping parameters * @res : resizer private structure - * @crop_rect : current crop rectangle - * @ratio : resizer ratios + * @input : format on sink pad + * @output : format on source pad * return none */ static void resizer_set_crop_params(struct isp_res_device *res, diff --git a/drivers/media/platform/omap3isp/ispvideo.c b/drivers/media/platform/omap3isp/ispvideo.c index a62cf0b..85b4036 100644 --- a/drivers/media/platform/omap3isp/ispvideo.c +++ b/drivers/media/platform/omap3isp/ispvideo.c @@ -333,7 +333,7 @@ isp_video_check_format(struct isp_video *video, struct isp_video_fh *vfh) /* * ispmmu_vmap - Wrapper for Virtual memory mapping of a scatter gather list - * @dev: Device pointer specific to the OMAP3 ISP. + * @isp: Device pointer specific to the OMAP3 ISP. * @sglist: Pointer to source Scatter gather list to allocate. * @sglen: Number of elements of the scatter-gatter list. * @@ -363,7 +363,7 @@ ispmmu_vmap(struct isp_device *isp, const struct scatterlist *sglist, int sglen) /* * ispmmu_vunmap - Unmap a device address from the ISP MMU - * @dev: Device pointer specific to the OMAP3 ISP. + * @isp: Device pointer specific to the OMAP3 ISP. * @da: Device address generated from a ispmmu_vmap call. */ static void ispmmu_vunmap(struct isp_device *isp, dma_addr_t da) -- cgit v1.1 From 1e9c4d49020996a645a535cbb8f1ff78b9b120f3 Mon Sep 17 00:00:00 2001 From: Peter Meerwald Date: Fri, 28 Feb 2014 14:36:07 -0300 Subject: [media] omap3isp: Fix kerneldoc for _module_sync_is_stopping and isp_isr() Use the correct name in the comment describing function omap3isp_module_sync_is_stopping(). isp_isr() never returned IRQ_NONE, remove the comment saying so. Signed-off-by: Peter Meerwald Signed-off-by: Laurent Pinchart Signed-off-by: Mauro Carvalho Chehab --- drivers/media/platform/omap3isp/isp.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/media/platform/omap3isp/isp.c b/drivers/media/platform/omap3isp/isp.c index 65a9b1d..06a0df4 100644 --- a/drivers/media/platform/omap3isp/isp.c +++ b/drivers/media/platform/omap3isp/isp.c @@ -588,9 +588,6 @@ static void isp_isr_sbl(struct isp_device *isp) * @_isp: Pointer to the OMAP3 ISP device * * Handles the corresponding callback if plugged in. - * - * Returns IRQ_HANDLED when IRQ was correctly handled, or IRQ_NONE when the - * IRQ wasn't handled. */ static irqreturn_t isp_isr(int irq, void *_isp) { @@ -1420,7 +1417,7 @@ int omap3isp_module_sync_idle(struct media_entity *me, wait_queue_head_t *wait, } /* - * omap3isp_module_sync_is_stopped - Helper to verify if module was stopping + * omap3isp_module_sync_is_stopping - Helper to verify if module was stopping * @wait: ISP submodule's wait queue for streamoff/interrupt synchronization * @stopping: flag which tells module wants to stop * -- cgit v1.1 From 249f5a58bc844506fef2e9d5d55a88fbc708c5fa Mon Sep 17 00:00:00 2001 From: Ricardo Ribalda Delgado Date: Wed, 8 Jan 2014 05:01:33 -0300 Subject: [media] vb2: Check if there are buffers before streamon This patch adds a test preventing streamon() if there is no buffer ready. Without this patch, a user could call streamon() before preparing any buffer. This leads to a situation where if he calls close() before calling streamoff() the device is kept streaming. Signed-off-by: Ricardo Ribalda Delgado Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/v4l2-core/videobuf2-core.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/media/v4l2-core/videobuf2-core.c b/drivers/media/v4l2-core/videobuf2-core.c index 8e6695c..3c07534 100644 --- a/drivers/media/v4l2-core/videobuf2-core.c +++ b/drivers/media/v4l2-core/videobuf2-core.c @@ -1832,6 +1832,11 @@ static int vb2_internal_streamon(struct vb2_queue *q, enum v4l2_buf_type type) return -EINVAL; } + if (!q->num_buffers) { + dprintk(1, "streamon: no buffers have been allocated\n"); + return -EINVAL; + } + /* * If any buffers were queued before streamon, * we can now pass them to driver for processing. -- cgit v1.1 From 4e5a4d8a8e970bd6b96c1c710cd636770b776697 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Fri, 14 Feb 2014 06:46:50 -0300 Subject: [media] vb2: fix read/write regression Commit 88e268702bfba78448abd20a31129458707383aa ("vb2: Improve file I/O emulation to handle buffers in any order") broke read/write support if the size of the buffer being read/written is less than the size of the image. When the commit was tested originally I used qv4l2, which calls read() with exactly the size of the image. But if you try 'cat /dev/video0' then it will fail and typically hang after reading two buffers. This patch fixes the behavior by adding a new cur_index field that contains the index of the field currently being filled/read, or it is num_buffers in which case a new buffer needs to be dequeued. The old index field has been renamed to initial_index in order to be a bit more descriptive. This has been tested with both read and write. Signed-off-by: Hans Verkuil Tested-by: Hans Verkuil Cc: Andy Walls Signed-off-by: Mauro Carvalho Chehab --- drivers/media/v4l2-core/videobuf2-core.c | 46 +++++++++++++++++++++++++++----- 1 file changed, 40 insertions(+), 6 deletions(-) diff --git a/drivers/media/v4l2-core/videobuf2-core.c b/drivers/media/v4l2-core/videobuf2-core.c index 3c07534..dbc2b8a 100644 --- a/drivers/media/v4l2-core/videobuf2-core.c +++ b/drivers/media/v4l2-core/videobuf2-core.c @@ -2310,6 +2310,22 @@ struct vb2_fileio_buf { /** * struct vb2_fileio_data - queue context used by file io emulator * + * @cur_index: the index of the buffer currently being read from or + * written to. If equal to q->num_buffers then a new buffer + * must be dequeued. + * @initial_index: in the read() case all buffers are queued up immediately + * in __vb2_init_fileio() and __vb2_perform_fileio() just cycles + * buffers. However, in the write() case no buffers are initially + * queued, instead whenever a buffer is full it is queued up by + * __vb2_perform_fileio(). Only once all available buffers have + * been queued up will __vb2_perform_fileio() start to dequeue + * buffers. This means that initially __vb2_perform_fileio() + * needs to know what buffer index to use when it is queuing up + * the buffers for the first time. That initial index is stored + * in this field. Once it is equal to q->num_buffers all + * available buffers have been queued and __vb2_perform_fileio() + * should start the normal dequeue/queue cycle. + * * vb2 provides a compatibility layer and emulator of file io (read and * write) calls on top of streaming API. For proper operation it required * this structure to save the driver state between each call of the read @@ -2319,7 +2335,8 @@ struct vb2_fileio_data { struct v4l2_requestbuffers req; struct v4l2_buffer b; struct vb2_fileio_buf bufs[VIDEO_MAX_FRAME]; - unsigned int index; + unsigned int cur_index; + unsigned int initial_index; unsigned int q_count; unsigned int dq_count; unsigned int flags; @@ -2419,7 +2436,12 @@ static int __vb2_init_fileio(struct vb2_queue *q, int read) goto err_reqbufs; fileio->bufs[i].queued = 1; } - fileio->index = q->num_buffers; + /* + * All buffers have been queued, so mark that by setting + * initial_index to q->num_buffers + */ + fileio->initial_index = q->num_buffers; + fileio->cur_index = q->num_buffers; } /* @@ -2498,7 +2520,7 @@ static size_t __vb2_perform_fileio(struct vb2_queue *q, char __user *data, size_ /* * Check if we need to dequeue the buffer. */ - index = fileio->index; + index = fileio->cur_index; if (index >= q->num_buffers) { /* * Call vb2_dqbuf to get buffer back. @@ -2512,7 +2534,7 @@ static size_t __vb2_perform_fileio(struct vb2_queue *q, char __user *data, size_ return ret; fileio->dq_count += 1; - index = fileio->b.index; + fileio->cur_index = index = fileio->b.index; buf = &fileio->bufs[index]; /* @@ -2588,8 +2610,20 @@ static size_t __vb2_perform_fileio(struct vb2_queue *q, char __user *data, size_ buf->queued = 1; buf->size = vb2_plane_size(q->bufs[index], 0); fileio->q_count += 1; - if (fileio->index < q->num_buffers) - fileio->index++; + /* + * If we are queuing up buffers for the first time, then + * increase initial_index by one. + */ + if (fileio->initial_index < q->num_buffers) + fileio->initial_index++; + /* + * The next buffer to use is either a buffer that's going to be + * queued for the first time (initial_index < q->num_buffers) + * or it is equal to q->num_buffers, meaning that the next + * time we need to dequeue a buffer since we've now queued up + * all the 'first time' buffers. + */ + fileio->cur_index = fileio->initial_index; } /* -- cgit v1.1 From 952c9ee2900de152c4999d94da5c4bd846ae52e8 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Mon, 10 Feb 2014 13:12:00 -0300 Subject: [media] vb2: fix PREPARE_BUF regression Fix an incorrect test in vb2_internal_qbuf() where only DEQUEUED buffers are allowed. But PREPARED buffers are also OK. Introduced by commit 4138111a27859dcc56a5592c804dd16bb12a23d1 ("vb2: simplify qbuf/prepare_buf by removing callback"). Signed-off-by: Hans Verkuil Acked-by: Laurent Pinchart Signed-off-by: Mauro Carvalho Chehab --- drivers/media/v4l2-core/videobuf2-core.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/media/v4l2-core/videobuf2-core.c b/drivers/media/v4l2-core/videobuf2-core.c index dbc2b8a..1dc11ed 100644 --- a/drivers/media/v4l2-core/videobuf2-core.c +++ b/drivers/media/v4l2-core/videobuf2-core.c @@ -1459,11 +1459,6 @@ static int vb2_internal_qbuf(struct vb2_queue *q, struct v4l2_buffer *b) return ret; vb = q->bufs[b->index]; - if (vb->state != VB2_BUF_STATE_DEQUEUED) { - dprintk(1, "%s(): invalid buffer state %d\n", __func__, - vb->state); - return -EINVAL; - } switch (vb->state) { case VB2_BUF_STATE_DEQUEUED: @@ -1477,7 +1472,8 @@ static int vb2_internal_qbuf(struct vb2_queue *q, struct v4l2_buffer *b) dprintk(1, "qbuf: buffer still being prepared\n"); return -EINVAL; default: - dprintk(1, "qbuf: buffer already in use\n"); + dprintk(1, "%s(): invalid buffer state %d\n", __func__, + vb->state); return -EINVAL; } -- cgit v1.1 From b5b4541eef8eac83f5c0d166d8e494f7c9fff202 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Wed, 29 Jan 2014 11:53:25 -0300 Subject: [media] vb2: add debugging code to check for unbalanced ops When a vb2_queue is freed check if all the mem_ops and queue ops were balanced. So the number of calls to e.g. buf_finish has to match the number of calls to buf_prepare, etc. This code is only enabled if CONFIG_VIDEO_ADV_DEBUG is set. Signed-off-by: Hans Verkuil Acked-by: Pawel Osciak Acked-by: Laurent Pinchart Signed-off-by: Mauro Carvalho Chehab --- drivers/media/v4l2-core/videobuf2-core.c | 233 ++++++++++++++++++++++++------- include/media/videobuf2-core.h | 43 ++++++ 2 files changed, 226 insertions(+), 50 deletions(-) diff --git a/drivers/media/v4l2-core/videobuf2-core.c b/drivers/media/v4l2-core/videobuf2-core.c index 1dc11ed..917b1cb 100644 --- a/drivers/media/v4l2-core/videobuf2-core.c +++ b/drivers/media/v4l2-core/videobuf2-core.c @@ -33,12 +33,63 @@ module_param(debug, int, 0644); printk(KERN_DEBUG "vb2: " fmt, ## arg); \ } while (0) -#define call_memop(q, op, args...) \ - (((q)->mem_ops->op) ? \ - ((q)->mem_ops->op(args)) : 0) +#ifdef CONFIG_VIDEO_ADV_DEBUG + +/* + * If advanced debugging is on, then count how often each op is called, + * which can either be per-buffer or per-queue. + * + * If the op failed then the 'fail_' variant is called to decrease the + * counter. That makes it easy to check that the 'init' and 'cleanup' + * (and variations thereof) stay balanced. + */ + +#define call_memop(vb, op, args...) \ +({ \ + struct vb2_queue *_q = (vb)->vb2_queue; \ + dprintk(2, "call_memop(%p, %d, %s)%s\n", \ + _q, (vb)->v4l2_buf.index, #op, \ + _q->mem_ops->op ? "" : " (nop)"); \ + (vb)->cnt_mem_ ## op++; \ + _q->mem_ops->op ? _q->mem_ops->op(args) : 0; \ +}) +#define fail_memop(vb, op) ((vb)->cnt_mem_ ## op--) + +#define call_qop(q, op, args...) \ +({ \ + dprintk(2, "call_qop(%p, %s)%s\n", q, #op, \ + (q)->ops->op ? "" : " (nop)"); \ + (q)->cnt_ ## op++; \ + (q)->ops->op ? (q)->ops->op(args) : 0; \ +}) +#define fail_qop(q, op) ((q)->cnt_ ## op--) + +#define call_vb_qop(vb, op, args...) \ +({ \ + struct vb2_queue *_q = (vb)->vb2_queue; \ + dprintk(2, "call_vb_qop(%p, %d, %s)%s\n", \ + _q, (vb)->v4l2_buf.index, #op, \ + _q->ops->op ? "" : " (nop)"); \ + (vb)->cnt_ ## op++; \ + _q->ops->op ? _q->ops->op(args) : 0; \ +}) +#define fail_vb_qop(vb, op) ((vb)->cnt_ ## op--) + +#else + +#define call_memop(vb, op, args...) \ + ((vb)->vb2_queue->mem_ops->op ? (vb)->vb2_queue->mem_ops->op(args) : 0) +#define fail_memop(vb, op) #define call_qop(q, op, args...) \ - (((q)->ops->op) ? ((q)->ops->op(args)) : 0) + ((q)->ops->op ? (q)->ops->op(args) : 0) +#define fail_qop(q, op) + +#define call_vb_qop(vb, op, args...) \ + ((vb)->vb2_queue->ops->op ? (vb)->vb2_queue->ops->op(args) : 0) +#define fail_vb_qop(vb, op) + +#endif /* Flags that are set by the vb2 core */ #define V4L2_BUFFER_MASK_FLAGS (V4L2_BUF_FLAG_MAPPED | V4L2_BUF_FLAG_QUEUED | \ @@ -65,7 +116,7 @@ static int __vb2_buf_mem_alloc(struct vb2_buffer *vb) for (plane = 0; plane < vb->num_planes; ++plane) { unsigned long size = PAGE_ALIGN(q->plane_sizes[plane]); - mem_priv = call_memop(q, alloc, q->alloc_ctx[plane], + mem_priv = call_memop(vb, alloc, q->alloc_ctx[plane], size, q->gfp_flags); if (IS_ERR_OR_NULL(mem_priv)) goto free; @@ -77,9 +128,10 @@ static int __vb2_buf_mem_alloc(struct vb2_buffer *vb) return 0; free: + fail_memop(vb, alloc); /* Free already allocated memory if one of the allocations failed */ for (; plane > 0; --plane) { - call_memop(q, put, vb->planes[plane - 1].mem_priv); + call_memop(vb, put, vb->planes[plane - 1].mem_priv); vb->planes[plane - 1].mem_priv = NULL; } @@ -91,11 +143,10 @@ free: */ static void __vb2_buf_mem_free(struct vb2_buffer *vb) { - struct vb2_queue *q = vb->vb2_queue; unsigned int plane; for (plane = 0; plane < vb->num_planes; ++plane) { - call_memop(q, put, vb->planes[plane].mem_priv); + call_memop(vb, put, vb->planes[plane].mem_priv); vb->planes[plane].mem_priv = NULL; dprintk(3, "Freed plane %d of buffer %d\n", plane, vb->v4l2_buf.index); @@ -108,12 +159,11 @@ static void __vb2_buf_mem_free(struct vb2_buffer *vb) */ static void __vb2_buf_userptr_put(struct vb2_buffer *vb) { - struct vb2_queue *q = vb->vb2_queue; unsigned int plane; for (plane = 0; plane < vb->num_planes; ++plane) { if (vb->planes[plane].mem_priv) - call_memop(q, put_userptr, vb->planes[plane].mem_priv); + call_memop(vb, put_userptr, vb->planes[plane].mem_priv); vb->planes[plane].mem_priv = NULL; } } @@ -122,15 +172,15 @@ static void __vb2_buf_userptr_put(struct vb2_buffer *vb) * __vb2_plane_dmabuf_put() - release memory associated with * a DMABUF shared plane */ -static void __vb2_plane_dmabuf_put(struct vb2_queue *q, struct vb2_plane *p) +static void __vb2_plane_dmabuf_put(struct vb2_buffer *vb, struct vb2_plane *p) { if (!p->mem_priv) return; if (p->dbuf_mapped) - call_memop(q, unmap_dmabuf, p->mem_priv); + call_memop(vb, unmap_dmabuf, p->mem_priv); - call_memop(q, detach_dmabuf, p->mem_priv); + call_memop(vb, detach_dmabuf, p->mem_priv); dma_buf_put(p->dbuf); memset(p, 0, sizeof(*p)); } @@ -141,11 +191,10 @@ static void __vb2_plane_dmabuf_put(struct vb2_queue *q, struct vb2_plane *p) */ static void __vb2_buf_dmabuf_put(struct vb2_buffer *vb) { - struct vb2_queue *q = vb->vb2_queue; unsigned int plane; for (plane = 0; plane < vb->num_planes; ++plane) - __vb2_plane_dmabuf_put(q, &vb->planes[plane]); + __vb2_plane_dmabuf_put(vb, &vb->planes[plane]); } /** @@ -250,10 +299,11 @@ static int __vb2_queue_alloc(struct vb2_queue *q, enum v4l2_memory memory, * callback, if given. An error in initialization * results in queue setup failure. */ - ret = call_qop(q, buf_init, vb); + ret = call_vb_qop(vb, buf_init, vb); if (ret) { dprintk(1, "Buffer %d %p initialization" " failed\n", buffer, vb); + fail_vb_qop(vb, buf_init); __vb2_buf_mem_free(vb); kfree(vb); break; @@ -325,18 +375,77 @@ static int __vb2_queue_free(struct vb2_queue *q, unsigned int buffers) } /* Call driver-provided cleanup function for each buffer, if provided */ - if (q->ops->buf_cleanup) { - for (buffer = q->num_buffers - buffers; buffer < q->num_buffers; - ++buffer) { - if (NULL == q->bufs[buffer]) - continue; - q->ops->buf_cleanup(q->bufs[buffer]); - } + for (buffer = q->num_buffers - buffers; buffer < q->num_buffers; + ++buffer) { + if (q->bufs[buffer]) + call_vb_qop(q->bufs[buffer], buf_cleanup, q->bufs[buffer]); } /* Release video buffer memory */ __vb2_free_mem(q, buffers); +#ifdef CONFIG_VIDEO_ADV_DEBUG + /* + * Check that all the calls were balances during the life-time of this + * queue. If not (or if the debug level is 1 or up), then dump the + * counters to the kernel log. + */ + if (q->num_buffers) { + bool unbalanced = q->cnt_start_streaming != q->cnt_stop_streaming || + q->cnt_wait_prepare != q->cnt_wait_finish; + + if (unbalanced || debug) { + pr_info("vb2: counters for queue %p:%s\n", q, + unbalanced ? " UNBALANCED!" : ""); + pr_info("vb2: setup: %u start_streaming: %u stop_streaming: %u\n", + q->cnt_queue_setup, q->cnt_start_streaming, + q->cnt_stop_streaming); + pr_info("vb2: wait_prepare: %u wait_finish: %u\n", + q->cnt_wait_prepare, q->cnt_wait_finish); + } + q->cnt_queue_setup = 0; + q->cnt_wait_prepare = 0; + q->cnt_wait_finish = 0; + q->cnt_start_streaming = 0; + q->cnt_stop_streaming = 0; + } + for (buffer = 0; buffer < q->num_buffers; ++buffer) { + struct vb2_buffer *vb = q->bufs[buffer]; + bool unbalanced = vb->cnt_mem_alloc != vb->cnt_mem_put || + vb->cnt_mem_prepare != vb->cnt_mem_finish || + vb->cnt_mem_get_userptr != vb->cnt_mem_put_userptr || + vb->cnt_mem_attach_dmabuf != vb->cnt_mem_detach_dmabuf || + vb->cnt_mem_map_dmabuf != vb->cnt_mem_unmap_dmabuf || + vb->cnt_buf_queue != vb->cnt_buf_done || + vb->cnt_buf_prepare != vb->cnt_buf_finish || + vb->cnt_buf_init != vb->cnt_buf_cleanup; + + if (unbalanced || debug) { + pr_info("vb2: counters for queue %p, buffer %d:%s\n", + q, buffer, unbalanced ? " UNBALANCED!" : ""); + pr_info("vb2: buf_init: %u buf_cleanup: %u buf_prepare: %u buf_finish: %u\n", + vb->cnt_buf_init, vb->cnt_buf_cleanup, + vb->cnt_buf_prepare, vb->cnt_buf_finish); + pr_info("vb2: buf_queue: %u buf_done: %u\n", + vb->cnt_buf_queue, vb->cnt_buf_done); + pr_info("vb2: alloc: %u put: %u prepare: %u finish: %u mmap: %u\n", + vb->cnt_mem_alloc, vb->cnt_mem_put, + vb->cnt_mem_prepare, vb->cnt_mem_finish, + vb->cnt_mem_mmap); + pr_info("vb2: get_userptr: %u put_userptr: %u\n", + vb->cnt_mem_get_userptr, vb->cnt_mem_put_userptr); + pr_info("vb2: attach_dmabuf: %u detach_dmabuf: %u map_dmabuf: %u unmap_dmabuf: %u\n", + vb->cnt_mem_attach_dmabuf, vb->cnt_mem_detach_dmabuf, + vb->cnt_mem_map_dmabuf, vb->cnt_mem_unmap_dmabuf); + pr_info("vb2: get_dmabuf: %u num_users: %u vaddr: %u cookie: %u\n", + vb->cnt_mem_get_dmabuf, + vb->cnt_mem_num_users, + vb->cnt_mem_vaddr, + vb->cnt_mem_cookie); + } + } +#endif + /* Free videobuf buffers */ for (buffer = q->num_buffers - buffers; buffer < q->num_buffers; ++buffer) { @@ -428,7 +537,7 @@ static bool __buffer_in_use(struct vb2_queue *q, struct vb2_buffer *vb) * case anyway. If num_users() returns more than 1, * we are not the only user of the plane's memory. */ - if (mem_priv && call_memop(q, num_users, mem_priv) > 1) + if (mem_priv && call_memop(vb, num_users, mem_priv) > 1) return true; } return false; @@ -716,8 +825,10 @@ static int __reqbufs(struct vb2_queue *q, struct v4l2_requestbuffers *req) */ ret = call_qop(q, queue_setup, q, NULL, &num_buffers, &num_planes, q->plane_sizes, q->alloc_ctx); - if (ret) + if (ret) { + fail_qop(q, queue_setup); return ret; + } /* Finally, allocate buffers and video memory */ ret = __vb2_queue_alloc(q, req->memory, num_buffers, num_planes); @@ -736,6 +847,8 @@ static int __reqbufs(struct vb2_queue *q, struct v4l2_requestbuffers *req) ret = call_qop(q, queue_setup, q, NULL, &num_buffers, &num_planes, q->plane_sizes, q->alloc_ctx); + if (ret) + fail_qop(q, queue_setup); if (!ret && allocated_buffers < num_buffers) ret = -ENOMEM; @@ -816,8 +929,10 @@ static int __create_bufs(struct vb2_queue *q, struct v4l2_create_buffers *create */ ret = call_qop(q, queue_setup, q, &create->format, &num_buffers, &num_planes, q->plane_sizes, q->alloc_ctx); - if (ret) + if (ret) { + fail_qop(q, queue_setup); return ret; + } /* Finally, allocate buffers and video memory */ ret = __vb2_queue_alloc(q, create->memory, num_buffers, @@ -841,6 +956,8 @@ static int __create_bufs(struct vb2_queue *q, struct v4l2_create_buffers *create */ ret = call_qop(q, queue_setup, q, &create->format, &num_buffers, &num_planes, q->plane_sizes, q->alloc_ctx); + if (ret) + fail_qop(q, queue_setup); if (!ret && allocated_buffers < num_buffers) ret = -ENOMEM; @@ -895,12 +1012,10 @@ EXPORT_SYMBOL_GPL(vb2_create_bufs); */ void *vb2_plane_vaddr(struct vb2_buffer *vb, unsigned int plane_no) { - struct vb2_queue *q = vb->vb2_queue; - if (plane_no > vb->num_planes || !vb->planes[plane_no].mem_priv) return NULL; - return call_memop(q, vaddr, vb->planes[plane_no].mem_priv); + return call_memop(vb, vaddr, vb->planes[plane_no].mem_priv); } EXPORT_SYMBOL_GPL(vb2_plane_vaddr); @@ -918,12 +1033,10 @@ EXPORT_SYMBOL_GPL(vb2_plane_vaddr); */ void *vb2_plane_cookie(struct vb2_buffer *vb, unsigned int plane_no) { - struct vb2_queue *q = vb->vb2_queue; - if (plane_no > vb->num_planes || !vb->planes[plane_no].mem_priv) return NULL; - return call_memop(q, cookie, vb->planes[plane_no].mem_priv); + return call_memop(vb, cookie, vb->planes[plane_no].mem_priv); } EXPORT_SYMBOL_GPL(vb2_plane_cookie); @@ -951,12 +1064,19 @@ void vb2_buffer_done(struct vb2_buffer *vb, enum vb2_buffer_state state) if (state != VB2_BUF_STATE_DONE && state != VB2_BUF_STATE_ERROR) return; +#ifdef CONFIG_VIDEO_ADV_DEBUG + /* + * Although this is not a callback, it still does have to balance + * with the buf_queue op. So update this counter manually. + */ + vb->cnt_buf_done++; +#endif dprintk(4, "Done processing on buffer %d, state: %d\n", vb->v4l2_buf.index, state); /* sync buffers */ for (plane = 0; plane < vb->num_planes; ++plane) - call_memop(q, finish, vb->planes[plane].mem_priv); + call_memop(vb, finish, vb->planes[plane].mem_priv); /* Add the buffer to the done buffers list */ spin_lock_irqsave(&q->done_lock, flags); @@ -1102,19 +1222,20 @@ static int __qbuf_userptr(struct vb2_buffer *vb, const struct v4l2_buffer *b) /* Release previously acquired memory if present */ if (vb->planes[plane].mem_priv) - call_memop(q, put_userptr, vb->planes[plane].mem_priv); + call_memop(vb, put_userptr, vb->planes[plane].mem_priv); vb->planes[plane].mem_priv = NULL; vb->v4l2_planes[plane].m.userptr = 0; vb->v4l2_planes[plane].length = 0; /* Acquire each plane's memory */ - mem_priv = call_memop(q, get_userptr, q->alloc_ctx[plane], + mem_priv = call_memop(vb, get_userptr, q->alloc_ctx[plane], planes[plane].m.userptr, planes[plane].length, write); if (IS_ERR_OR_NULL(mem_priv)) { dprintk(1, "qbuf: failed acquiring userspace " "memory for plane %d\n", plane); + fail_memop(vb, get_userptr); ret = mem_priv ? PTR_ERR(mem_priv) : -EINVAL; goto err; } @@ -1125,9 +1246,10 @@ static int __qbuf_userptr(struct vb2_buffer *vb, const struct v4l2_buffer *b) * Call driver-specific initialization on the newly acquired buffer, * if provided. */ - ret = call_qop(q, buf_init, vb); + ret = call_vb_qop(vb, buf_init, vb); if (ret) { dprintk(1, "qbuf: buffer initialization failed\n"); + fail_vb_qop(vb, buf_init); goto err; } @@ -1143,7 +1265,7 @@ err: /* In case of errors, release planes that were already acquired */ for (plane = 0; plane < vb->num_planes; ++plane) { if (vb->planes[plane].mem_priv) - call_memop(q, put_userptr, vb->planes[plane].mem_priv); + call_memop(vb, put_userptr, vb->planes[plane].mem_priv); vb->planes[plane].mem_priv = NULL; vb->v4l2_planes[plane].m.userptr = 0; vb->v4l2_planes[plane].length = 0; @@ -1208,14 +1330,15 @@ static int __qbuf_dmabuf(struct vb2_buffer *vb, const struct v4l2_buffer *b) dprintk(1, "qbuf: buffer for plane %d changed\n", plane); /* Release previously acquired memory if present */ - __vb2_plane_dmabuf_put(q, &vb->planes[plane]); + __vb2_plane_dmabuf_put(vb, &vb->planes[plane]); memset(&vb->v4l2_planes[plane], 0, sizeof(struct v4l2_plane)); /* Acquire each plane's memory */ - mem_priv = call_memop(q, attach_dmabuf, q->alloc_ctx[plane], + mem_priv = call_memop(vb, attach_dmabuf, q->alloc_ctx[plane], dbuf, planes[plane].length, write); if (IS_ERR(mem_priv)) { dprintk(1, "qbuf: failed to attach dmabuf\n"); + fail_memop(vb, attach_dmabuf); ret = PTR_ERR(mem_priv); dma_buf_put(dbuf); goto err; @@ -1230,10 +1353,11 @@ static int __qbuf_dmabuf(struct vb2_buffer *vb, const struct v4l2_buffer *b) * the buffer(s).. */ for (plane = 0; plane < vb->num_planes; ++plane) { - ret = call_memop(q, map_dmabuf, vb->planes[plane].mem_priv); + ret = call_memop(vb, map_dmabuf, vb->planes[plane].mem_priv); if (ret) { dprintk(1, "qbuf: failed to map dmabuf for plane %d\n", plane); + fail_memop(vb, map_dmabuf); goto err; } vb->planes[plane].dbuf_mapped = 1; @@ -1243,9 +1367,10 @@ static int __qbuf_dmabuf(struct vb2_buffer *vb, const struct v4l2_buffer *b) * Call driver-specific initialization on the newly acquired buffer, * if provided. */ - ret = call_qop(q, buf_init, vb); + ret = call_vb_qop(vb, buf_init, vb); if (ret) { dprintk(1, "qbuf: buffer initialization failed\n"); + fail_vb_qop(vb, buf_init); goto err; } @@ -1277,9 +1402,9 @@ static void __enqueue_in_driver(struct vb2_buffer *vb) /* sync buffers */ for (plane = 0; plane < vb->num_planes; ++plane) - call_memop(q, prepare, vb->planes[plane].mem_priv); + call_memop(vb, prepare, vb->planes[plane].mem_priv); - q->ops->buf_queue(vb); + call_vb_qop(vb, buf_queue, vb); } static int __buf_prepare(struct vb2_buffer *vb, const struct v4l2_buffer *b) @@ -1334,8 +1459,11 @@ static int __buf_prepare(struct vb2_buffer *vb, const struct v4l2_buffer *b) ret = -EINVAL; } - if (!ret) - ret = call_qop(q, buf_prepare, vb); + if (!ret) { + ret = call_vb_qop(vb, buf_prepare, vb); + if (ret) + fail_vb_qop(vb, buf_prepare); + } if (ret) dprintk(1, "qbuf: buffer preparation failed: %d\n", ret); vb->state = ret ? VB2_BUF_STATE_DEQUEUED : VB2_BUF_STATE_PREPARED; @@ -1432,6 +1560,8 @@ static int vb2_start_streaming(struct vb2_queue *q) /* Tell the driver to start streaming */ ret = call_qop(q, start_streaming, q, atomic_read(&q->queued_count)); + if (ret) + fail_qop(q, start_streaming); /* * If there are not enough buffers queued to start streaming, then @@ -1686,7 +1816,7 @@ static void __vb2_dqbuf(struct vb2_buffer *vb) for (i = 0; i < vb->num_planes; ++i) { if (!vb->planes[i].dbuf_mapped) continue; - call_memop(q, unmap_dmabuf, vb->planes[i].mem_priv); + call_memop(vb, unmap_dmabuf, vb->planes[i].mem_priv); vb->planes[i].dbuf_mapped = 0; } } @@ -1704,7 +1834,7 @@ static int vb2_internal_dqbuf(struct vb2_queue *q, struct v4l2_buffer *b, bool n if (ret < 0) return ret; - ret = call_qop(q, buf_finish, vb); + ret = call_vb_qop(vb, buf_finish, vb); if (ret) { dprintk(1, "dqbuf: buffer finish failed\n"); return ret; @@ -2002,10 +2132,11 @@ int vb2_expbuf(struct vb2_queue *q, struct v4l2_exportbuffer *eb) vb_plane = &vb->planes[eb->plane]; - dbuf = call_memop(q, get_dmabuf, vb_plane->mem_priv, eb->flags & O_ACCMODE); + dbuf = call_memop(vb, get_dmabuf, vb_plane->mem_priv, eb->flags & O_ACCMODE); if (IS_ERR_OR_NULL(dbuf)) { dprintk(1, "Failed to export buffer %d, plane %d\n", eb->index, eb->plane); + fail_memop(vb, get_dmabuf); return -EINVAL; } @@ -2097,9 +2228,11 @@ int vb2_mmap(struct vb2_queue *q, struct vm_area_struct *vma) return -EINVAL; } - ret = call_memop(q, mmap, vb->planes[plane].mem_priv, vma); - if (ret) + ret = call_memop(vb, mmap, vb->planes[plane].mem_priv, vma); + if (ret) { + fail_memop(vb, mmap); return ret; + } dprintk(3, "Buffer %d, plane %d successfully mapped\n", buffer, plane); return 0; diff --git a/include/media/videobuf2-core.h b/include/media/videobuf2-core.h index bf6859e..2fdb08a 100644 --- a/include/media/videobuf2-core.h +++ b/include/media/videobuf2-core.h @@ -203,6 +203,37 @@ struct vb2_buffer { struct list_head done_entry; struct vb2_plane planes[VIDEO_MAX_PLANES]; + +#ifdef CONFIG_VIDEO_ADV_DEBUG + /* + * Counters for how often these buffer-related ops are + * called. Used to check for unbalanced ops. + */ + u32 cnt_mem_alloc; + u32 cnt_mem_put; + u32 cnt_mem_get_dmabuf; + u32 cnt_mem_get_userptr; + u32 cnt_mem_put_userptr; + u32 cnt_mem_prepare; + u32 cnt_mem_finish; + u32 cnt_mem_attach_dmabuf; + u32 cnt_mem_detach_dmabuf; + u32 cnt_mem_map_dmabuf; + u32 cnt_mem_unmap_dmabuf; + u32 cnt_mem_vaddr; + u32 cnt_mem_cookie; + u32 cnt_mem_num_users; + u32 cnt_mem_mmap; + + u32 cnt_buf_init; + u32 cnt_buf_prepare; + u32 cnt_buf_finish; + u32 cnt_buf_cleanup; + u32 cnt_buf_queue; + + /* This counts the number of calls to vb2_buffer_done() */ + u32 cnt_buf_done; +#endif }; /** @@ -366,6 +397,18 @@ struct vb2_queue { unsigned int retry_start_streaming:1; struct vb2_fileio_data *fileio; + +#ifdef CONFIG_VIDEO_ADV_DEBUG + /* + * Counters for how often these queue-related ops are + * called. Used to check for unbalanced ops. + */ + u32 cnt_queue_setup; + u32 cnt_wait_prepare; + u32 cnt_wait_finish; + u32 cnt_start_streaming; + u32 cnt_stop_streaming; +#endif }; void *vb2_plane_vaddr(struct vb2_buffer *vb, unsigned int plane_no); -- cgit v1.1 From 0647064293d745720fc62e2edc7734fa8af06adf Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Tue, 4 Mar 2014 07:27:13 -0300 Subject: [media] vb2: change result code of buf_finish to void The buf_finish op should always work, so change the return type to void. Update the few drivers that use it. Signed-off-by: Hans Verkuil Acked-by: Pawel Osciak Reviewed-by: Pawel Osciak Signed-off-by: Mauro Carvalho Chehab --- drivers/media/parport/bw-qcam.c | 3 +-- drivers/media/pci/sta2x11/sta2x11_vip.c | 4 +--- drivers/media/platform/marvell-ccic/mcam-core.c | 3 +-- drivers/media/usb/pwc/pwc-if.c | 4 ++-- drivers/media/usb/uvc/uvc_queue.c | 3 +-- drivers/media/v4l2-core/videobuf2-core.c | 6 +----- drivers/staging/media/go7007/go7007-v4l2.c | 3 +-- include/media/videobuf2-core.h | 2 +- 8 files changed, 9 insertions(+), 19 deletions(-) diff --git a/drivers/media/parport/bw-qcam.c b/drivers/media/parport/bw-qcam.c index a0a6ee6..cf2db63 100644 --- a/drivers/media/parport/bw-qcam.c +++ b/drivers/media/parport/bw-qcam.c @@ -667,7 +667,7 @@ static void buffer_queue(struct vb2_buffer *vb) vb2_buffer_done(vb, VB2_BUF_STATE_DONE); } -static int buffer_finish(struct vb2_buffer *vb) +static void buffer_finish(struct vb2_buffer *vb) { struct qcam *qcam = vb2_get_drv_priv(vb->vb2_queue); void *vbuf = vb2_plane_vaddr(vb, 0); @@ -691,7 +691,6 @@ static int buffer_finish(struct vb2_buffer *vb) if (len != size) vb->state = VB2_BUF_STATE_ERROR; vb2_set_plane_payload(vb, 0, len); - return 0; } static struct vb2_ops qcam_video_qops = { diff --git a/drivers/media/pci/sta2x11/sta2x11_vip.c b/drivers/media/pci/sta2x11/sta2x11_vip.c index e5cfb6c..e66556c 100644 --- a/drivers/media/pci/sta2x11/sta2x11_vip.c +++ b/drivers/media/pci/sta2x11/sta2x11_vip.c @@ -327,7 +327,7 @@ static void buffer_queue(struct vb2_buffer *vb) } spin_unlock(&vip->lock); } -static int buffer_finish(struct vb2_buffer *vb) +static void buffer_finish(struct vb2_buffer *vb) { struct sta2x11_vip *vip = vb2_get_drv_priv(vb->vb2_queue); struct vip_buffer *vip_buf = to_vip_buffer(vb); @@ -338,8 +338,6 @@ static int buffer_finish(struct vb2_buffer *vb) spin_unlock(&vip->lock); vip_active_buf_next(vip); - - return 0; } static int start_streaming(struct vb2_queue *vq, unsigned int count) diff --git a/drivers/media/platform/marvell-ccic/mcam-core.c b/drivers/media/platform/marvell-ccic/mcam-core.c index 32fab30..8b34c48 100644 --- a/drivers/media/platform/marvell-ccic/mcam-core.c +++ b/drivers/media/platform/marvell-ccic/mcam-core.c @@ -1238,7 +1238,7 @@ static int mcam_vb_sg_buf_prepare(struct vb2_buffer *vb) return 0; } -static int mcam_vb_sg_buf_finish(struct vb2_buffer *vb) +static void mcam_vb_sg_buf_finish(struct vb2_buffer *vb) { struct mcam_camera *cam = vb2_get_drv_priv(vb->vb2_queue); struct sg_table *sg_table = vb2_dma_sg_plane_desc(vb, 0); @@ -1246,7 +1246,6 @@ static int mcam_vb_sg_buf_finish(struct vb2_buffer *vb) if (sg_table) dma_unmap_sg(cam->dev, sg_table->sgl, sg_table->nents, DMA_FROM_DEVICE); - return 0; } static void mcam_vb_sg_buf_cleanup(struct vb2_buffer *vb) diff --git a/drivers/media/usb/pwc/pwc-if.c b/drivers/media/usb/pwc/pwc-if.c index 8bef015..1a27096 100644 --- a/drivers/media/usb/pwc/pwc-if.c +++ b/drivers/media/usb/pwc/pwc-if.c @@ -614,7 +614,7 @@ static int buffer_prepare(struct vb2_buffer *vb) return 0; } -static int buffer_finish(struct vb2_buffer *vb) +static void buffer_finish(struct vb2_buffer *vb) { struct pwc_device *pdev = vb2_get_drv_priv(vb->vb2_queue); struct pwc_frame_buf *buf = container_of(vb, struct pwc_frame_buf, vb); @@ -624,7 +624,7 @@ static int buffer_finish(struct vb2_buffer *vb) * filled, take the pwc data we've stored in buf->data and decompress * it into a usable format, storing the result in the vb2_buffer */ - return pwc_decompress(pdev, buf); + pwc_decompress(pdev, buf); } static void buffer_cleanup(struct vb2_buffer *vb) diff --git a/drivers/media/usb/uvc/uvc_queue.c b/drivers/media/usb/uvc/uvc_queue.c index 935556e..26172cb 100644 --- a/drivers/media/usb/uvc/uvc_queue.c +++ b/drivers/media/usb/uvc/uvc_queue.c @@ -106,7 +106,7 @@ static void uvc_buffer_queue(struct vb2_buffer *vb) spin_unlock_irqrestore(&queue->irqlock, flags); } -static int uvc_buffer_finish(struct vb2_buffer *vb) +static void uvc_buffer_finish(struct vb2_buffer *vb) { struct uvc_video_queue *queue = vb2_get_drv_priv(vb->vb2_queue); struct uvc_streaming *stream = @@ -114,7 +114,6 @@ static int uvc_buffer_finish(struct vb2_buffer *vb) struct uvc_buffer *buf = container_of(vb, struct uvc_buffer, buf); uvc_video_clock_update(stream, &vb->v4l2_buf, buf); - return 0; } static void uvc_wait_prepare(struct vb2_queue *vq) diff --git a/drivers/media/v4l2-core/videobuf2-core.c b/drivers/media/v4l2-core/videobuf2-core.c index 917b1cb..2be3cfe 100644 --- a/drivers/media/v4l2-core/videobuf2-core.c +++ b/drivers/media/v4l2-core/videobuf2-core.c @@ -1834,11 +1834,7 @@ static int vb2_internal_dqbuf(struct vb2_queue *q, struct v4l2_buffer *b, bool n if (ret < 0) return ret; - ret = call_vb_qop(vb, buf_finish, vb); - if (ret) { - dprintk(1, "dqbuf: buffer finish failed\n"); - return ret; - } + call_vb_qop(vb, buf_finish, vb); switch (vb->state) { case VB2_BUF_STATE_DONE: diff --git a/drivers/staging/media/go7007/go7007-v4l2.c b/drivers/staging/media/go7007/go7007-v4l2.c index efacda24..a349878 100644 --- a/drivers/staging/media/go7007/go7007-v4l2.c +++ b/drivers/staging/media/go7007/go7007-v4l2.c @@ -470,7 +470,7 @@ static int go7007_buf_prepare(struct vb2_buffer *vb) return 0; } -static int go7007_buf_finish(struct vb2_buffer *vb) +static void go7007_buf_finish(struct vb2_buffer *vb) { struct vb2_queue *vq = vb->vb2_queue; struct go7007 *go = vb2_get_drv_priv(vq); @@ -483,7 +483,6 @@ static int go7007_buf_finish(struct vb2_buffer *vb) V4L2_BUF_FLAG_PFRAME); buf->flags |= frame_type_flag; buf->field = V4L2_FIELD_NONE; - return 0; } static int go7007_start_streaming(struct vb2_queue *q, unsigned int count) diff --git a/include/media/videobuf2-core.h b/include/media/videobuf2-core.h index 2fdb08a..8d62a51 100644 --- a/include/media/videobuf2-core.h +++ b/include/media/videobuf2-core.h @@ -311,7 +311,7 @@ struct vb2_ops { int (*buf_init)(struct vb2_buffer *vb); int (*buf_prepare)(struct vb2_buffer *vb); - int (*buf_finish)(struct vb2_buffer *vb); + void (*buf_finish)(struct vb2_buffer *vb); void (*buf_cleanup)(struct vb2_buffer *vb); int (*start_streaming)(struct vb2_queue *q, unsigned int count); -- cgit v1.1 From 1a17948184a3320e0bb0aab561112211d2e9b7a8 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Tue, 4 Mar 2014 07:28:11 -0300 Subject: [media] pwc: do not decompress the image unless the state is DONE There is no point in trying to decompress a captured frame unless the buffer state is OK. It won't be used in any other state, and in fact the contents of the buffer might well be corrupt. Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/pwc/pwc-if.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/media/usb/pwc/pwc-if.c b/drivers/media/usb/pwc/pwc-if.c index 1a27096..84a6720 100644 --- a/drivers/media/usb/pwc/pwc-if.c +++ b/drivers/media/usb/pwc/pwc-if.c @@ -619,12 +619,15 @@ static void buffer_finish(struct vb2_buffer *vb) struct pwc_device *pdev = vb2_get_drv_priv(vb->vb2_queue); struct pwc_frame_buf *buf = container_of(vb, struct pwc_frame_buf, vb); - /* - * Application has called dqbuf and is getting back a buffer we've - * filled, take the pwc data we've stored in buf->data and decompress - * it into a usable format, storing the result in the vb2_buffer - */ - pwc_decompress(pdev, buf); + if (vb->state == VB2_BUF_STATE_DONE) { + /* + * Application has called dqbuf and is getting back a buffer + * we've filled, take the pwc data we've stored in buf->data + * and decompress it into a usable format, storing the result + * in the vb2_buffer. + */ + pwc_decompress(pdev, buf); + } } static void buffer_cleanup(struct vb2_buffer *vb) -- cgit v1.1 From 9c0863b1cc485f2bacac0675c68b73e5341cfd26 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Tue, 4 Mar 2014 07:34:49 -0300 Subject: [media] vb2: call buf_finish from __queue_cancel If a queue was canceled, then the buf_finish op was never called for the pending buffers. So add this call to queue_cancel. Before calling buf_finish set the buffer state to PREPARED, which is the correct state. That way the states DONE and ERROR will only be seen in buf_finish if streaming is in progress. Since buf_finish can now be called from non-streaming state we need to adapt the handful of drivers that actually need to know this. Signed-off-by: Hans Verkuil Acked-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab --- drivers/media/parport/bw-qcam.c | 3 +++ drivers/media/pci/sta2x11/sta2x11_vip.c | 3 ++- drivers/media/usb/uvc/uvc_queue.c | 3 ++- drivers/media/v4l2-core/videobuf2-core.c | 17 +++++++++++++++-- include/media/videobuf2-core.h | 10 +++++++++- 5 files changed, 31 insertions(+), 5 deletions(-) diff --git a/drivers/media/parport/bw-qcam.c b/drivers/media/parport/bw-qcam.c index cf2db63..8a0e84c 100644 --- a/drivers/media/parport/bw-qcam.c +++ b/drivers/media/parport/bw-qcam.c @@ -674,6 +674,9 @@ static void buffer_finish(struct vb2_buffer *vb) int size = vb->vb2_queue->plane_sizes[0]; int len; + if (!vb2_is_streaming(vb->vb2_queue)) + return; + mutex_lock(&qcam->lock); parport_claim_or_block(qcam->pdev); diff --git a/drivers/media/pci/sta2x11/sta2x11_vip.c b/drivers/media/pci/sta2x11/sta2x11_vip.c index e66556c..bb11443 100644 --- a/drivers/media/pci/sta2x11/sta2x11_vip.c +++ b/drivers/media/pci/sta2x11/sta2x11_vip.c @@ -337,7 +337,8 @@ static void buffer_finish(struct vb2_buffer *vb) list_del_init(&vip_buf->list); spin_unlock(&vip->lock); - vip_active_buf_next(vip); + if (vb2_is_streaming(vb->vb2_queue)) + vip_active_buf_next(vip); } static int start_streaming(struct vb2_queue *vq, unsigned int count) diff --git a/drivers/media/usb/uvc/uvc_queue.c b/drivers/media/usb/uvc/uvc_queue.c index 26172cb..6e92d20 100644 --- a/drivers/media/usb/uvc/uvc_queue.c +++ b/drivers/media/usb/uvc/uvc_queue.c @@ -113,7 +113,8 @@ static void uvc_buffer_finish(struct vb2_buffer *vb) container_of(queue, struct uvc_streaming, queue); struct uvc_buffer *buf = container_of(vb, struct uvc_buffer, buf); - uvc_video_clock_update(stream, &vb->v4l2_buf, buf); + if (vb->state == VB2_BUF_STATE_DONE) + uvc_video_clock_update(stream, &vb->v4l2_buf, buf); } static void uvc_wait_prepare(struct vb2_queue *vq) diff --git a/drivers/media/v4l2-core/videobuf2-core.c b/drivers/media/v4l2-core/videobuf2-core.c index 2be3cfe..16ae66f 100644 --- a/drivers/media/v4l2-core/videobuf2-core.c +++ b/drivers/media/v4l2-core/videobuf2-core.c @@ -1929,9 +1929,22 @@ static void __vb2_queue_cancel(struct vb2_queue *q) /* * Reinitialize all buffers for next use. + * Make sure to call buf_finish for any queued buffers. Normally + * that's done in dqbuf, but that's not going to happen when we + * cancel the whole queue. Note: this code belongs here, not in + * __vb2_dqbuf() since in vb2_internal_dqbuf() there is a critical + * call to __fill_v4l2_buffer() after buf_finish(). That order can't + * be changed, so we can't move the buf_finish() to __vb2_dqbuf(). */ - for (i = 0; i < q->num_buffers; ++i) - __vb2_dqbuf(q->bufs[i]); + for (i = 0; i < q->num_buffers; ++i) { + struct vb2_buffer *vb = q->bufs[i]; + + if (vb->state != VB2_BUF_STATE_DEQUEUED) { + vb->state = VB2_BUF_STATE_PREPARED; + call_vb_qop(vb, buf_finish, vb); + } + __vb2_dqbuf(vb); + } } static int vb2_internal_streamon(struct vb2_queue *q, enum v4l2_buf_type type) diff --git a/include/media/videobuf2-core.h b/include/media/videobuf2-core.h index 8d62a51..2ffcb81 100644 --- a/include/media/videobuf2-core.h +++ b/include/media/videobuf2-core.h @@ -276,7 +276,15 @@ struct vb2_buffer { * in driver; optional * @buf_finish: called before every dequeue of the buffer back to * userspace; drivers may perform any operations required - * before userspace accesses the buffer; optional + * before userspace accesses the buffer; optional. The + * buffer state can be one of the following: DONE and + * ERROR occur while streaming is in progress, and the + * PREPARED state occurs when the queue has been canceled + * and all pending buffers are being returned to their + * default DEQUEUED state. Typically you only have to do + * something if the state is VB2_BUF_STATE_DONE, since in + * all other cases the buffer contents will be ignored + * anyway. * @buf_cleanup: called once before the buffer is freed; drivers may * perform any additional cleanup; optional * @start_streaming: called once to enter 'streaming' state; the driver may -- cgit v1.1 From 3f12e6b0d91a68f977f803ed03757a2fa9ba6b9f Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Fri, 28 Feb 2014 12:25:28 -0300 Subject: [media] vb2: consistent usage of periods in videobuf2-core.h Sometimes sentences in comments ended with a period, and sometimes they didn't. Add periods. No other changes. Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- include/media/videobuf2-core.h | 40 ++++++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/include/media/videobuf2-core.h b/include/media/videobuf2-core.h index 2ffcb81..b852b39 100644 --- a/include/media/videobuf2-core.h +++ b/include/media/videobuf2-core.h @@ -34,49 +34,49 @@ struct vb2_fileio_data; * usually will result in the allocator freeing the buffer (if * no other users of this buffer are present); the buf_priv * argument is the allocator private per-buffer structure - * previously returned from the alloc callback + * previously returned from the alloc callback. * @get_userptr: acquire userspace memory for a hardware operation; used for * USERPTR memory types; vaddr is the address passed to the * videobuf layer when queuing a video buffer of USERPTR type; * should return an allocator private per-buffer structure * associated with the buffer on success, NULL on failure; * the returned private structure will then be passed as buf_priv - * argument to other ops in this structure + * argument to other ops in this structure. * @put_userptr: inform the allocator that a USERPTR buffer will no longer - * be used + * be used. * @attach_dmabuf: attach a shared struct dma_buf for a hardware operation; * used for DMABUF memory types; alloc_ctx is the alloc context * dbuf is the shared dma_buf; returns NULL on failure; * allocator private per-buffer structure on success; - * this needs to be used for further accesses to the buffer + * this needs to be used for further accesses to the buffer. * @detach_dmabuf: inform the exporter of the buffer that the current DMABUF * buffer is no longer used; the buf_priv argument is the * allocator private per-buffer structure previously returned - * from the attach_dmabuf callback + * from the attach_dmabuf callback. * @map_dmabuf: request for access to the dmabuf from allocator; the allocator * of dmabuf is informed that this driver is going to use the - * dmabuf + * dmabuf. * @unmap_dmabuf: releases access control to the dmabuf - allocator is notified - * that this driver is done using the dmabuf for now + * that this driver is done using the dmabuf for now. * @prepare: called every time the buffer is passed from userspace to the - * driver, useful for cache synchronisation, optional + * driver, useful for cache synchronisation, optional. * @finish: called every time the buffer is passed back from the driver - * to the userspace, also optional + * to the userspace, also optional. * @vaddr: return a kernel virtual address to a given memory buffer * associated with the passed private structure or NULL if no - * such mapping exists + * such mapping exists. * @cookie: return allocator specific cookie for a given memory buffer * associated with the passed private structure or NULL if not - * available + * available. * @num_users: return the current number of users of a memory buffer; * return 1 if the videobuf layer (or actually the driver using - * it) is the only user + * it) is the only user. * @mmap: setup a userspace mapping for a given memory buffer under - * the provided virtual memory region + * the provided virtual memory region. * * Required ops for USERPTR types: get_userptr, put_userptr. * Required ops for MMAP types: alloc, put, num_users, mmap. - * Required ops for read/write access types: alloc, put, num_users, vaddr + * Required ops for read/write access types: alloc, put, num_users, vaddr. * Required ops for DMABUF types: attach_dmabuf, detach_dmabuf, map_dmabuf, * unmap_dmabuf. */ @@ -258,22 +258,22 @@ struct vb2_buffer { * @wait_prepare: release any locks taken while calling vb2 functions; * it is called before an ioctl needs to wait for a new * buffer to arrive; required to avoid a deadlock in - * blocking access type + * blocking access type. * @wait_finish: reacquire all locks released in the previous callback; * required to continue operation after sleeping while - * waiting for a new buffer to arrive + * waiting for a new buffer to arrive. * @buf_init: called once after allocating a buffer (in MMAP case) * or after acquiring a new USERPTR buffer; drivers may * perform additional buffer-related initialization; * initialization failure (return != 0) will prevent - * queue setup from completing successfully; optional + * queue setup from completing successfully; optional. * @buf_prepare: called every time the buffer is queued from userspace * and from the VIDIOC_PREPARE_BUF ioctl; drivers may * perform any initialization required before each hardware * operation in this callback; drivers that support * VIDIOC_CREATE_BUFS must also validate the buffer size; * if an error is returned, the buffer will not be queued - * in driver; optional + * in driver; optional. * @buf_finish: called before every dequeue of the buffer back to * userspace; drivers may perform any operations required * before userspace accesses the buffer; optional. The @@ -286,7 +286,7 @@ struct vb2_buffer { * all other cases the buffer contents will be ignored * anyway. * @buf_cleanup: called once before the buffer is freed; drivers may - * perform any additional cleanup; optional + * perform any additional cleanup; optional. * @start_streaming: called once to enter 'streaming' state; the driver may * receive buffers with @buf_queue callback before * @start_streaming is called; the driver gets the number @@ -307,7 +307,7 @@ struct vb2_buffer { * the buffer back by calling vb2_buffer_done() function; * it is allways called after calling STREAMON ioctl; * might be called before start_streaming callback if user - * pre-queued buffers before calling STREAMON + * pre-queued buffers before calling STREAMON. */ struct vb2_ops { int (*queue_setup)(struct vb2_queue *q, const struct v4l2_format *fmt, -- cgit v1.1 From 256f3162c17595b3fde1c4f18389719e8a2952f5 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Wed, 29 Jan 2014 13:36:53 -0300 Subject: [media] vb2: fix buf_init/buf_cleanup call sequences Ensure that these ops are properly balanced. There are two scenarios: 1) for MMAP buf_init is called when the buffers are created and buf_cleanup must be called when the queue is finally freed. This scenario was always working. 2) for USERPTR and DMABUF it is more complicated. When a buffer is queued the code checks if all planes of this buffer have been acquired before. If that's the case, then only buf_prepare has to be called. Otherwise buf_cleanup needs to be called if the buffer was acquired before, then, once all changed planes have been (re)acquired, buf_init has to be called followed by buf_prepare. Should buf_prepare fail, then buf_cleanup must be called on the newly acquired planes to release them in. Finally, in __vb2_queue_free we have to check if the buffer was actually acquired before calling buf_cleanup. While that it always true for MMAP mode, it is not necessarily true for the other modes. E.g. if you just call REQBUFS and close the file handle, then buffers were never queued and so no buf_init was ever called. Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/v4l2-core/videobuf2-core.c | 100 +++++++++++++++++++++---------- 1 file changed, 67 insertions(+), 33 deletions(-) diff --git a/drivers/media/v4l2-core/videobuf2-core.c b/drivers/media/v4l2-core/videobuf2-core.c index 16ae66f..6c33b78 100644 --- a/drivers/media/v4l2-core/videobuf2-core.c +++ b/drivers/media/v4l2-core/videobuf2-core.c @@ -377,8 +377,10 @@ static int __vb2_queue_free(struct vb2_queue *q, unsigned int buffers) /* Call driver-provided cleanup function for each buffer, if provided */ for (buffer = q->num_buffers - buffers; buffer < q->num_buffers; ++buffer) { - if (q->bufs[buffer]) - call_vb_qop(q->bufs[buffer], buf_cleanup, q->bufs[buffer]); + struct vb2_buffer *vb = q->bufs[buffer]; + + if (vb && vb->planes[0].mem_priv) + call_vb_qop(vb, buf_cleanup, vb); } /* Release video buffer memory */ @@ -1196,6 +1198,7 @@ static int __qbuf_userptr(struct vb2_buffer *vb, const struct v4l2_buffer *b) unsigned int plane; int ret; int write = !V4L2_TYPE_IS_OUTPUT(q->type); + bool reacquired = vb->planes[0].mem_priv == NULL; /* Copy relevant information provided by the userspace */ __fill_vb2_buffer(vb, b, planes); @@ -1221,12 +1224,16 @@ static int __qbuf_userptr(struct vb2_buffer *vb, const struct v4l2_buffer *b) } /* Release previously acquired memory if present */ - if (vb->planes[plane].mem_priv) + if (vb->planes[plane].mem_priv) { + if (!reacquired) { + reacquired = true; + call_vb_qop(vb, buf_cleanup, vb); + } call_memop(vb, put_userptr, vb->planes[plane].mem_priv); + } vb->planes[plane].mem_priv = NULL; - vb->v4l2_planes[plane].m.userptr = 0; - vb->v4l2_planes[plane].length = 0; + memset(&vb->v4l2_planes[plane], 0, sizeof(struct v4l2_plane)); /* Acquire each plane's memory */ mem_priv = call_memop(vb, get_userptr, q->alloc_ctx[plane], @@ -1243,23 +1250,34 @@ static int __qbuf_userptr(struct vb2_buffer *vb, const struct v4l2_buffer *b) } /* - * Call driver-specific initialization on the newly acquired buffer, - * if provided. - */ - ret = call_vb_qop(vb, buf_init, vb); - if (ret) { - dprintk(1, "qbuf: buffer initialization failed\n"); - fail_vb_qop(vb, buf_init); - goto err; - } - - /* * Now that everything is in order, copy relevant information * provided by userspace. */ for (plane = 0; plane < vb->num_planes; ++plane) vb->v4l2_planes[plane] = planes[plane]; + if (reacquired) { + /* + * One or more planes changed, so we must call buf_init to do + * the driver-specific initialization on the newly acquired + * buffer, if provided. + */ + ret = call_vb_qop(vb, buf_init, vb); + if (ret) { + dprintk(1, "qbuf: buffer initialization failed\n"); + fail_vb_qop(vb, buf_init); + goto err; + } + } + + ret = call_vb_qop(vb, buf_prepare, vb); + if (ret) { + dprintk(1, "qbuf: buffer preparation failed\n"); + fail_vb_qop(vb, buf_prepare); + call_vb_qop(vb, buf_cleanup, vb); + goto err; + } + return 0; err: /* In case of errors, release planes that were already acquired */ @@ -1279,8 +1297,13 @@ err: */ static int __qbuf_mmap(struct vb2_buffer *vb, const struct v4l2_buffer *b) { + int ret; + __fill_vb2_buffer(vb, b, vb->v4l2_planes); - return 0; + ret = call_vb_qop(vb, buf_prepare, vb); + if (ret) + fail_vb_qop(vb, buf_prepare); + return ret; } /** @@ -1294,6 +1317,7 @@ static int __qbuf_dmabuf(struct vb2_buffer *vb, const struct v4l2_buffer *b) unsigned int plane; int ret; int write = !V4L2_TYPE_IS_OUTPUT(q->type); + bool reacquired = vb->planes[0].mem_priv == NULL; /* Copy relevant information provided by the userspace */ __fill_vb2_buffer(vb, b, planes); @@ -1329,6 +1353,11 @@ static int __qbuf_dmabuf(struct vb2_buffer *vb, const struct v4l2_buffer *b) dprintk(1, "qbuf: buffer for plane %d changed\n", plane); + if (!reacquired) { + reacquired = true; + call_vb_qop(vb, buf_cleanup, vb); + } + /* Release previously acquired memory if present */ __vb2_plane_dmabuf_put(vb, &vb->planes[plane]); memset(&vb->v4l2_planes[plane], 0, sizeof(struct v4l2_plane)); @@ -1364,23 +1393,33 @@ static int __qbuf_dmabuf(struct vb2_buffer *vb, const struct v4l2_buffer *b) } /* - * Call driver-specific initialization on the newly acquired buffer, - * if provided. - */ - ret = call_vb_qop(vb, buf_init, vb); - if (ret) { - dprintk(1, "qbuf: buffer initialization failed\n"); - fail_vb_qop(vb, buf_init); - goto err; - } - - /* * Now that everything is in order, copy relevant information * provided by userspace. */ for (plane = 0; plane < vb->num_planes; ++plane) vb->v4l2_planes[plane] = planes[plane]; + if (reacquired) { + /* + * Call driver-specific initialization on the newly acquired buffer, + * if provided. + */ + ret = call_vb_qop(vb, buf_init, vb); + if (ret) { + dprintk(1, "qbuf: buffer initialization failed\n"); + fail_vb_qop(vb, buf_init); + goto err; + } + } + + ret = call_vb_qop(vb, buf_prepare, vb); + if (ret) { + dprintk(1, "qbuf: buffer preparation failed\n"); + fail_vb_qop(vb, buf_prepare); + call_vb_qop(vb, buf_cleanup, vb); + goto err; + } + return 0; err: /* In case of errors, release planes that were already acquired */ @@ -1459,11 +1498,6 @@ static int __buf_prepare(struct vb2_buffer *vb, const struct v4l2_buffer *b) ret = -EINVAL; } - if (!ret) { - ret = call_vb_qop(vb, buf_prepare, vb); - if (ret) - fail_vb_qop(vb, buf_prepare); - } if (ret) dprintk(1, "qbuf: buffer preparation failed: %d\n", ret); vb->state = ret ? VB2_BUF_STATE_DEQUEUED : VB2_BUF_STATE_PREPARED; -- cgit v1.1 From 6ea3b980f058d9dbc79ba88c652d581fa2d00792 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Thu, 6 Feb 2014 05:46:11 -0300 Subject: [media] vb2: rename queued_count to owned_by_drv_count 'queued_count' is a bit vague since it is not clear to which queue it refers to: the vb2 internal list of buffers or the driver-owned list of buffers. Rename to make it explicit. Signed-off-by: Hans Verkuil Acked-by: Pawel Osciak Acked-by: Laurent Pinchart Signed-off-by: Mauro Carvalho Chehab --- drivers/media/v4l2-core/videobuf2-core.c | 10 +++++----- include/media/videobuf2-core.h | 4 ++-- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/media/v4l2-core/videobuf2-core.c b/drivers/media/v4l2-core/videobuf2-core.c index 6c33b78..ef29a22 100644 --- a/drivers/media/v4l2-core/videobuf2-core.c +++ b/drivers/media/v4l2-core/videobuf2-core.c @@ -1084,7 +1084,7 @@ void vb2_buffer_done(struct vb2_buffer *vb, enum vb2_buffer_state state) spin_lock_irqsave(&q->done_lock, flags); vb->state = state; list_add_tail(&vb->done_entry, &q->done_list); - atomic_dec(&q->queued_count); + atomic_dec(&q->owned_by_drv_count); spin_unlock_irqrestore(&q->done_lock, flags); /* Inform any processes that may be waiting for buffers */ @@ -1437,7 +1437,7 @@ static void __enqueue_in_driver(struct vb2_buffer *vb) unsigned int plane; vb->state = VB2_BUF_STATE_ACTIVE; - atomic_inc(&q->queued_count); + atomic_inc(&q->owned_by_drv_count); /* sync buffers */ for (plane = 0; plane < vb->num_planes; ++plane) @@ -1593,7 +1593,7 @@ static int vb2_start_streaming(struct vb2_queue *q) int ret; /* Tell the driver to start streaming */ - ret = call_qop(q, start_streaming, q, atomic_read(&q->queued_count)); + ret = call_qop(q, start_streaming, q, atomic_read(&q->owned_by_drv_count)); if (ret) fail_qop(q, start_streaming); @@ -1826,7 +1826,7 @@ int vb2_wait_for_all_buffers(struct vb2_queue *q) } if (!q->retry_start_streaming) - wait_event(q->done_wq, !atomic_read(&q->queued_count)); + wait_event(q->done_wq, !atomic_read(&q->owned_by_drv_count)); return 0; } EXPORT_SYMBOL_GPL(vb2_wait_for_all_buffers); @@ -1958,7 +1958,7 @@ static void __vb2_queue_cancel(struct vb2_queue *q) * has not already dequeued before initiating cancel. */ INIT_LIST_HEAD(&q->done_list); - atomic_set(&q->queued_count, 0); + atomic_set(&q->owned_by_drv_count, 0); wake_up_all(&q->done_wq); /* diff --git a/include/media/videobuf2-core.h b/include/media/videobuf2-core.h index b852b39..36e3e8e 100644 --- a/include/media/videobuf2-core.h +++ b/include/media/videobuf2-core.h @@ -361,7 +361,7 @@ struct v4l2_fh; * @bufs: videobuf buffer structures * @num_buffers: number of allocated/used buffers * @queued_list: list of buffers currently queued from userspace - * @queued_count: number of buffers owned by the driver + * @owned_by_drv_count: number of buffers owned by the driver * @done_list: list of buffers ready to be dequeued to userspace * @done_lock: lock to protect done_list list * @done_wq: waitqueue for processes waiting for buffers ready to be dequeued @@ -393,7 +393,7 @@ struct vb2_queue { struct list_head queued_list; - atomic_t queued_count; + atomic_t owned_by_drv_count; struct list_head done_list; spinlock_t done_lock; wait_queue_head_t done_wq; -- cgit v1.1 From a7afcaccfab2fb012841852eaead79861dc9cb5f Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Mon, 24 Feb 2014 13:41:20 -0300 Subject: [media] vb2: don't init the list if there are still buffers __vb2_queue_free() would init the queued_list at all times, even if q->num_buffers > 0. This should only happen if num_buffers == 0. This situation can happen if a CREATE_BUFFERS call couldn't allocate enough buffers and had to free those it did manage to allocate before returning an error. While we're at it: __vb2_queue_alloc() returns the number of buffers allocated, not an error code. So stick the result in allocated_buffers instead of ret as that's very confusing. Signed-off-by: Hans Verkuil Acked-by: Laurent Pinchart Signed-off-by: Mauro Carvalho Chehab --- drivers/media/v4l2-core/videobuf2-core.c | 29 +++++++++++++++++------------ 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/drivers/media/v4l2-core/videobuf2-core.c b/drivers/media/v4l2-core/videobuf2-core.c index ef29a22..4e50043 100644 --- a/drivers/media/v4l2-core/videobuf2-core.c +++ b/drivers/media/v4l2-core/videobuf2-core.c @@ -456,9 +456,10 @@ static int __vb2_queue_free(struct vb2_queue *q, unsigned int buffers) } q->num_buffers -= buffers; - if (!q->num_buffers) + if (!q->num_buffers) { q->memory = 0; - INIT_LIST_HEAD(&q->queued_list); + INIT_LIST_HEAD(&q->queued_list); + } return 0; } @@ -833,14 +834,12 @@ static int __reqbufs(struct vb2_queue *q, struct v4l2_requestbuffers *req) } /* Finally, allocate buffers and video memory */ - ret = __vb2_queue_alloc(q, req->memory, num_buffers, num_planes); - if (ret == 0) { + allocated_buffers = __vb2_queue_alloc(q, req->memory, num_buffers, num_planes); + if (allocated_buffers == 0) { dprintk(1, "Memory allocation failed\n"); return -ENOMEM; } - allocated_buffers = ret; - /* * Check if driver can handle the allocated number of buffers. */ @@ -864,6 +863,10 @@ static int __reqbufs(struct vb2_queue *q, struct v4l2_requestbuffers *req) q->num_buffers = allocated_buffers; if (ret < 0) { + /* + * Note: __vb2_queue_free() will subtract 'allocated_buffers' + * from q->num_buffers. + */ __vb2_queue_free(q, allocated_buffers); return ret; } @@ -937,20 +940,18 @@ static int __create_bufs(struct vb2_queue *q, struct v4l2_create_buffers *create } /* Finally, allocate buffers and video memory */ - ret = __vb2_queue_alloc(q, create->memory, num_buffers, + allocated_buffers = __vb2_queue_alloc(q, create->memory, num_buffers, num_planes); - if (ret == 0) { + if (allocated_buffers == 0) { dprintk(1, "Memory allocation failed\n"); return -ENOMEM; } - allocated_buffers = ret; - /* * Check if driver can handle the so far allocated number of buffers. */ - if (ret < num_buffers) { - num_buffers = ret; + if (allocated_buffers < num_buffers) { + num_buffers = allocated_buffers; /* * q->num_buffers contains the total number of buffers, that the @@ -973,6 +974,10 @@ static int __create_bufs(struct vb2_queue *q, struct v4l2_create_buffers *create q->num_buffers += allocated_buffers; if (ret < 0) { + /* + * Note: __vb2_queue_free() will subtract 'allocated_buffers' + * from q->num_buffers. + */ __vb2_queue_free(q, allocated_buffers); return -ENOMEM; } -- cgit v1.1 From b3379c6201bb3555298cdbf0aa004af260f2a6a4 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Mon, 24 Feb 2014 13:51:03 -0300 Subject: [media] vb2: only call start_streaming if sufficient buffers are queued In commit 02f142ecd24aaf891324ffba8527284c1731b561 support was added to start_streaming to return -ENOBUFS if insufficient buffers were queued for the DMA engine to start. The vb2 core would attempt calling start_streaming again if another buffer would be queued up. Later analysis uncovered problems with the queue management if start_streaming would return an error: the buffers are enqueued to the driver before the start_streaming op is called, so after an error they are never returned to the vb2 core. The solution for this is to let the driver return them to the vb2 core in case of an error while starting the DMA engine. However, in the case of -ENOBUFS that would be weird: it is not a real error, it just says that more buffers are needed. Requiring start_streaming to give them back only to have them requeued again the next time the application calls QBUF is inefficient. This patch changes this mechanism: it adds a 'min_buffers_needed' field to vb2_queue that drivers can set with the minimum number of buffers required to start the DMA engine. The start_streaming op is only called if enough buffers are queued. The -ENOBUFS handling has been dropped in favor of this new method. Drivers are expected to return buffers back to vb2 core with state QUEUED if start_streaming would return an error. The vb2 core checks for this and produces a warning if that didn't happen and it will forcefully reclaim such buffers to ensure that the internal vb2 core state remains consistent and all buffer-related resources have been correctly freed and all op calls have been balanced. __reqbufs() has been updated to check that at least min_buffers_needed buffers could be allocated. If fewer buffers were allocated then __reqbufs will free what was allocated and return -ENOMEM. Based on a suggestion from Pawel Osciak. __create_bufs() doesn't do that check, since the use of __create_bufs assumes some advance scenario where the user might want more control. Instead streamon will check if enough buffers were allocated to prevent streaming with fewer than the minimum required number of buffers. Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/platform/davinci/vpbe_display.c | 6 +- drivers/media/platform/davinci/vpif_capture.c | 7 +- drivers/media/platform/davinci/vpif_display.c | 7 +- drivers/media/platform/s5p-tv/mixer_video.c | 6 +- drivers/media/v4l2-core/videobuf2-core.c | 146 ++++++++++++++++-------- drivers/staging/media/davinci_vpfe/vpfe_video.c | 3 +- include/media/videobuf2-core.h | 14 ++- 7 files changed, 116 insertions(+), 73 deletions(-) diff --git a/drivers/media/platform/davinci/vpbe_display.c b/drivers/media/platform/davinci/vpbe_display.c index e512767..7a0e40e 100644 --- a/drivers/media/platform/davinci/vpbe_display.c +++ b/drivers/media/platform/davinci/vpbe_display.c @@ -344,11 +344,6 @@ static int vpbe_start_streaming(struct vb2_queue *vq, unsigned int count) struct vpbe_device *vpbe_dev = fh->disp_dev->vpbe_dev; int ret; - /* If buffer queue is empty, return error */ - if (list_empty(&layer->dma_queue)) { - v4l2_err(&vpbe_dev->v4l2_dev, "buffer queue is empty\n"); - return -ENOBUFS; - } /* Get the next frame from the buffer queue */ layer->next_frm = layer->cur_frm = list_entry(layer->dma_queue.next, struct vpbe_disp_buffer, list); @@ -1416,6 +1411,7 @@ static int vpbe_display_reqbufs(struct file *file, void *priv, q->mem_ops = &vb2_dma_contig_memops; q->buf_struct_size = sizeof(struct vpbe_disp_buffer); q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + q->min_buffers_needed = 1; ret = vb2_queue_init(q); if (ret) { diff --git a/drivers/media/platform/davinci/vpif_capture.c b/drivers/media/platform/davinci/vpif_capture.c index cd6da8b..756da78 100644 --- a/drivers/media/platform/davinci/vpif_capture.c +++ b/drivers/media/platform/davinci/vpif_capture.c @@ -272,13 +272,7 @@ static int vpif_start_streaming(struct vb2_queue *vq, unsigned int count) unsigned long flags; int ret; - /* If buffer queue is empty, return error */ spin_lock_irqsave(&common->irqlock, flags); - if (list_empty(&common->dma_queue)) { - spin_unlock_irqrestore(&common->irqlock, flags); - vpif_dbg(1, debug, "buffer queue is empty\n"); - return -ENOBUFS; - } /* Get the next frame from the buffer queue */ common->cur_frm = common->next_frm = list_entry(common->dma_queue.next, @@ -1024,6 +1018,7 @@ static int vpif_reqbufs(struct file *file, void *priv, q->mem_ops = &vb2_dma_contig_memops; q->buf_struct_size = sizeof(struct vpif_cap_buffer); q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + q->min_buffers_needed = 1; ret = vb2_queue_init(q); if (ret) { diff --git a/drivers/media/platform/davinci/vpif_display.c b/drivers/media/platform/davinci/vpif_display.c index fd68236..0ac841e 100644 --- a/drivers/media/platform/davinci/vpif_display.c +++ b/drivers/media/platform/davinci/vpif_display.c @@ -234,13 +234,7 @@ static int vpif_start_streaming(struct vb2_queue *vq, unsigned int count) unsigned long flags; int ret; - /* If buffer queue is empty, return error */ spin_lock_irqsave(&common->irqlock, flags); - if (list_empty(&common->dma_queue)) { - spin_unlock_irqrestore(&common->irqlock, flags); - vpif_err("buffer queue is empty\n"); - return -ENOBUFS; - } /* Get the next frame from the buffer queue */ common->next_frm = common->cur_frm = @@ -984,6 +978,7 @@ static int vpif_reqbufs(struct file *file, void *priv, q->mem_ops = &vb2_dma_contig_memops; q->buf_struct_size = sizeof(struct vpif_disp_buffer); q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + q->min_buffers_needed = 1; ret = vb2_queue_init(q); if (ret) { diff --git a/drivers/media/platform/s5p-tv/mixer_video.c b/drivers/media/platform/s5p-tv/mixer_video.c index c5059ba..a1ce55f 100644 --- a/drivers/media/platform/s5p-tv/mixer_video.c +++ b/drivers/media/platform/s5p-tv/mixer_video.c @@ -946,11 +946,6 @@ static int start_streaming(struct vb2_queue *vq, unsigned int count) mxr_dbg(mdev, "%s\n", __func__); - if (count == 0) { - mxr_dbg(mdev, "no output buffers queued\n"); - return -ENOBUFS; - } - /* block any changes in output configuration */ mxr_output_get(mdev); @@ -1124,6 +1119,7 @@ struct mxr_layer *mxr_base_layer_create(struct mxr_device *mdev, .drv_priv = layer, .buf_struct_size = sizeof(struct mxr_buffer), .ops = &mxr_video_qops, + .min_buffers_needed = 1, .mem_ops = &vb2_dma_contig_memops, }; diff --git a/drivers/media/v4l2-core/videobuf2-core.c b/drivers/media/v4l2-core/videobuf2-core.c index 4e50043..ce308f6 100644 --- a/drivers/media/v4l2-core/videobuf2-core.c +++ b/drivers/media/v4l2-core/videobuf2-core.c @@ -818,6 +818,7 @@ static int __reqbufs(struct vb2_queue *q, struct v4l2_requestbuffers *req) * Make sure the requested values and current defaults are sane. */ num_buffers = min_t(unsigned int, req->count, VIDEO_MAX_FRAME); + num_buffers = max_t(unsigned int, req->count, q->min_buffers_needed); memset(q->plane_sizes, 0, sizeof(q->plane_sizes)); memset(q->alloc_ctx, 0, sizeof(q->alloc_ctx)); q->memory = req->memory; @@ -841,9 +842,16 @@ static int __reqbufs(struct vb2_queue *q, struct v4l2_requestbuffers *req) } /* + * There is no point in continuing if we can't allocate the minimum + * number of buffers needed by this vb2_queue. + */ + if (allocated_buffers < q->min_buffers_needed) + ret = -ENOMEM; + + /* * Check if driver can handle the allocated number of buffers. */ - if (allocated_buffers < num_buffers) { + if (!ret && allocated_buffers < num_buffers) { num_buffers = allocated_buffers; ret = call_qop(q, queue_setup, q, NULL, &num_buffers, @@ -1051,13 +1059,20 @@ EXPORT_SYMBOL_GPL(vb2_plane_cookie); * vb2_buffer_done() - inform videobuf that an operation on a buffer is finished * @vb: vb2_buffer returned from the driver * @state: either VB2_BUF_STATE_DONE if the operation finished successfully - * or VB2_BUF_STATE_ERROR if the operation finished with an error + * or VB2_BUF_STATE_ERROR if the operation finished with an error. + * If start_streaming fails then it should return buffers with state + * VB2_BUF_STATE_QUEUED to put them back into the queue. * * This function should be called by the driver after a hardware operation on * a buffer is finished and the buffer may be returned to userspace. The driver * cannot use this buffer anymore until it is queued back to it by videobuf * by the means of buf_queue callback. Only buffers previously queued to the * driver by buf_queue can be passed to this function. + * + * While streaming a buffer can only be returned in state DONE or ERROR. + * The start_streaming op can also return them in case the DMA engine cannot + * be started for some reason. In that case the buffers should be returned with + * state QUEUED. */ void vb2_buffer_done(struct vb2_buffer *vb, enum vb2_buffer_state state) { @@ -1065,11 +1080,17 @@ void vb2_buffer_done(struct vb2_buffer *vb, enum vb2_buffer_state state) unsigned long flags; unsigned int plane; - if (vb->state != VB2_BUF_STATE_ACTIVE) + if (WARN_ON(vb->state != VB2_BUF_STATE_ACTIVE)) return; - if (state != VB2_BUF_STATE_DONE && state != VB2_BUF_STATE_ERROR) - return; + if (!q->start_streaming_called) { + if (WARN_ON(state != VB2_BUF_STATE_QUEUED)) + state = VB2_BUF_STATE_QUEUED; + } else if (!WARN_ON(!q->start_streaming_called)) { + if (WARN_ON(state != VB2_BUF_STATE_DONE && + state != VB2_BUF_STATE_ERROR)) + state = VB2_BUF_STATE_ERROR; + } #ifdef CONFIG_VIDEO_ADV_DEBUG /* @@ -1088,10 +1109,14 @@ void vb2_buffer_done(struct vb2_buffer *vb, enum vb2_buffer_state state) /* Add the buffer to the done buffers list */ spin_lock_irqsave(&q->done_lock, flags); vb->state = state; - list_add_tail(&vb->done_entry, &q->done_list); + if (state != VB2_BUF_STATE_QUEUED) + list_add_tail(&vb->done_entry, &q->done_list); atomic_dec(&q->owned_by_drv_count); spin_unlock_irqrestore(&q->done_lock, flags); + if (state == VB2_BUF_STATE_QUEUED) + return; + /* Inform any processes that may be waiting for buffers */ wake_up(&q->done_wq); } @@ -1588,34 +1613,49 @@ EXPORT_SYMBOL_GPL(vb2_prepare_buf); * vb2_start_streaming() - Attempt to start streaming. * @q: videobuf2 queue * - * If there are not enough buffers, then retry_start_streaming is set to - * 1 and 0 is returned. The next time a buffer is queued and - * retry_start_streaming is 1, this function will be called again to - * retry starting the DMA engine. + * Attempt to start streaming. When this function is called there must be + * at least q->min_buffers_needed buffers queued up (i.e. the minimum + * number of buffers required for the DMA engine to function). If the + * @start_streaming op fails it is supposed to return all the driver-owned + * buffers back to vb2 in state QUEUED. Check if that happened and if + * not warn and reclaim them forcefully. */ static int vb2_start_streaming(struct vb2_queue *q) { + struct vb2_buffer *vb; int ret; - /* Tell the driver to start streaming */ - ret = call_qop(q, start_streaming, q, atomic_read(&q->owned_by_drv_count)); - if (ret) - fail_qop(q, start_streaming); - /* - * If there are not enough buffers queued to start streaming, then - * the start_streaming operation will return -ENOBUFS and you have to - * retry when the next buffer is queued. + * If any buffers were queued before streamon, + * we can now pass them to driver for processing. */ - if (ret == -ENOBUFS) { - dprintk(1, "qbuf: not enough buffers, retry when more buffers are queued.\n"); - q->retry_start_streaming = 1; + list_for_each_entry(vb, &q->queued_list, queued_entry) + __enqueue_in_driver(vb); + + /* Tell the driver to start streaming */ + ret = call_qop(q, start_streaming, q, + atomic_read(&q->owned_by_drv_count)); + q->start_streaming_called = ret == 0; + if (!ret) return 0; + + fail_qop(q, start_streaming); + dprintk(1, "qbuf: driver refused to start streaming\n"); + if (WARN_ON(atomic_read(&q->owned_by_drv_count))) { + unsigned i; + + /* + * Forcefully reclaim buffers if the driver did not + * correctly return them to vb2. + */ + for (i = 0; i < q->num_buffers; ++i) { + vb = q->bufs[i]; + if (vb->state == VB2_BUF_STATE_ACTIVE) + vb2_buffer_done(vb, VB2_BUF_STATE_QUEUED); + } + /* Must be zero now */ + WARN_ON(atomic_read(&q->owned_by_drv_count)); } - if (ret) - dprintk(1, "qbuf: driver refused to start streaming\n"); - else - q->retry_start_streaming = 0; return ret; } @@ -1651,6 +1691,7 @@ static int vb2_internal_qbuf(struct vb2_queue *q, struct v4l2_buffer *b) * dequeued in dqbuf. */ list_add_tail(&vb->queued_entry, &q->queued_list); + q->queued_count++; vb->state = VB2_BUF_STATE_QUEUED; if (V4L2_TYPE_IS_OUTPUT(q->type)) { /* @@ -1669,13 +1710,20 @@ static int vb2_internal_qbuf(struct vb2_queue *q, struct v4l2_buffer *b) * If already streaming, give the buffer to driver for processing. * If not, the buffer will be given to driver on next streamon. */ - if (q->streaming) + if (q->start_streaming_called) __enqueue_in_driver(vb); /* Fill buffer information for the userspace */ __fill_v4l2_buffer(vb, b); - if (q->retry_start_streaming) { + /* + * If streamon has been called, and we haven't yet called + * start_streaming() since not enough buffers were queued, and + * we now have reached the minimum number of queued buffers, + * then we can finally call start_streaming(). + */ + if (q->streaming && !q->start_streaming_called && + q->queued_count >= q->min_buffers_needed) { ret = vb2_start_streaming(q); if (ret) return ret; @@ -1830,7 +1878,7 @@ int vb2_wait_for_all_buffers(struct vb2_queue *q) return -EINVAL; } - if (!q->retry_start_streaming) + if (q->start_streaming_called) wait_event(q->done_wq, !atomic_read(&q->owned_by_drv_count)); return 0; } @@ -1891,6 +1939,7 @@ static int vb2_internal_dqbuf(struct vb2_queue *q, struct v4l2_buffer *b, bool n __fill_v4l2_buffer(vb, b); /* Remove from videobuf queue */ list_del(&vb->queued_entry); + q->queued_count--; /* go back to dequeued state */ __vb2_dqbuf(vb); @@ -1941,18 +1990,23 @@ static void __vb2_queue_cancel(struct vb2_queue *q) { unsigned int i; - if (q->retry_start_streaming) { - q->retry_start_streaming = 0; - q->streaming = 0; - } - /* * Tell driver to stop all transactions and release all queued * buffers. */ - if (q->streaming) + if (q->start_streaming_called) call_qop(q, stop_streaming, q); q->streaming = 0; + q->start_streaming_called = 0; + q->queued_count = 0; + + if (WARN_ON(atomic_read(&q->owned_by_drv_count))) { + for (i = 0; i < q->num_buffers; ++i) + if (q->bufs[i]->state == VB2_BUF_STATE_ACTIVE) + vb2_buffer_done(q->bufs[i], VB2_BUF_STATE_ERROR); + /* Must be zero now */ + WARN_ON(atomic_read(&q->owned_by_drv_count)); + } /* * Remove all buffers from videobuf's list... @@ -1988,7 +2042,6 @@ static void __vb2_queue_cancel(struct vb2_queue *q) static int vb2_internal_streamon(struct vb2_queue *q, enum v4l2_buf_type type) { - struct vb2_buffer *vb; int ret; if (type != q->type) { @@ -2010,19 +2063,22 @@ static int vb2_internal_streamon(struct vb2_queue *q, enum v4l2_buf_type type) dprintk(1, "streamon: no buffers have been allocated\n"); return -EINVAL; } + if (q->num_buffers < q->min_buffers_needed) { + dprintk(1, "streamon: need at least %u allocated buffers\n", + q->min_buffers_needed); + return -EINVAL; + } /* - * If any buffers were queued before streamon, - * we can now pass them to driver for processing. + * Tell driver to start streaming provided sufficient buffers + * are available. */ - list_for_each_entry(vb, &q->queued_list, queued_entry) - __enqueue_in_driver(vb); - - /* Tell driver to start streaming. */ - ret = vb2_start_streaming(q); - if (ret) { - __vb2_queue_cancel(q); - return ret; + if (q->queued_count >= q->min_buffers_needed) { + ret = vb2_start_streaming(q); + if (ret) { + __vb2_queue_cancel(q); + return ret; + } } q->streaming = 1; diff --git a/drivers/staging/media/davinci_vpfe/vpfe_video.c b/drivers/staging/media/davinci_vpfe/vpfe_video.c index 1f3b0f9..8c101cb 100644 --- a/drivers/staging/media/davinci_vpfe/vpfe_video.c +++ b/drivers/staging/media/davinci_vpfe/vpfe_video.c @@ -1201,8 +1201,6 @@ static int vpfe_start_streaming(struct vb2_queue *vq, unsigned int count) unsigned long addr; int ret; - if (count == 0) - return -ENOBUFS; ret = mutex_lock_interruptible(&video->lock); if (ret) goto streamoff; @@ -1327,6 +1325,7 @@ static int vpfe_reqbufs(struct file *file, void *priv, q->type = req_buf->type; q->io_modes = VB2_MMAP | VB2_USERPTR; q->drv_priv = fh; + q->min_buffers_needed = 1; q->ops = &video_qops; q->mem_ops = &vb2_dma_contig_memops; q->buf_struct_size = sizeof(struct vpfe_cap_buffer); diff --git a/include/media/videobuf2-core.h b/include/media/videobuf2-core.h index 36e3e8e..af46211 100644 --- a/include/media/videobuf2-core.h +++ b/include/media/videobuf2-core.h @@ -356,20 +356,24 @@ struct v4l2_fh; * @gfp_flags: additional gfp flags used when allocating the buffers. * Typically this is 0, but it may be e.g. GFP_DMA or __GFP_DMA32 * to force the buffer allocation to a specific memory zone. + * @min_buffers_needed: the minimum number of buffers needed before + * start_streaming() can be called. Used when a DMA engine + * cannot be started unless at least this number of buffers + * have been queued into the driver. * * @memory: current memory type used * @bufs: videobuf buffer structures * @num_buffers: number of allocated/used buffers * @queued_list: list of buffers currently queued from userspace + * @queued_count: number of buffers queued and ready for streaming. * @owned_by_drv_count: number of buffers owned by the driver * @done_list: list of buffers ready to be dequeued to userspace * @done_lock: lock to protect done_list list * @done_wq: waitqueue for processes waiting for buffers ready to be dequeued * @alloc_ctx: memory type/allocator-specific contexts for each plane * @streaming: current streaming state - * @retry_start_streaming: start_streaming() was called, but there were not enough - * buffers queued. If set, then retry calling start_streaming when - * queuing a new buffer. + * @start_streaming_called: start_streaming() was called successfully and we + * started streaming. * @fileio: file io emulator internal data, used only if emulator is active */ struct vb2_queue { @@ -385,6 +389,7 @@ struct vb2_queue { unsigned int buf_struct_size; u32 timestamp_flags; gfp_t gfp_flags; + u32 min_buffers_needed; /* private: internal use only */ enum v4l2_memory memory; @@ -392,6 +397,7 @@ struct vb2_queue { unsigned int num_buffers; struct list_head queued_list; + unsigned int queued_count; atomic_t owned_by_drv_count; struct list_head done_list; @@ -402,7 +408,7 @@ struct vb2_queue { unsigned int plane_sizes[VIDEO_MAX_PLANES]; unsigned int streaming:1; - unsigned int retry_start_streaming:1; + unsigned int start_streaming_called:1; struct vb2_fileio_data *fileio; -- cgit v1.1 From fb64dca805f091b52dbe8d6504390f63d961cbbd Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Fri, 28 Feb 2014 12:49:18 -0300 Subject: [media] vb2: properly clean up PREPARED and QUEUED buffers If __reqbufs was called then existing buffers are freed. However, if that happens without ever having started STREAMON, but if buffers have been queued, then the buf_finish op is never called. Add a call to __vb2_queue_cancel in __reqbufs so that these buffers are cleaned up there as well. Signed-off-by: Hans Verkuil Acked-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab --- drivers/media/v4l2-core/videobuf2-core.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/media/v4l2-core/videobuf2-core.c b/drivers/media/v4l2-core/videobuf2-core.c index ce308f6..17f1d07 100644 --- a/drivers/media/v4l2-core/videobuf2-core.c +++ b/drivers/media/v4l2-core/videobuf2-core.c @@ -100,6 +100,8 @@ module_param(debug, int, 0644); #define V4L2_BUFFER_OUT_FLAGS (V4L2_BUF_FLAG_PFRAME | V4L2_BUF_FLAG_BFRAME | \ V4L2_BUF_FLAG_KEYFRAME | V4L2_BUF_FLAG_TIMECODE) +static void __vb2_queue_cancel(struct vb2_queue *q); + /** * __vb2_buf_mem_alloc() - allocate video memory for the given buffer */ @@ -802,6 +804,12 @@ static int __reqbufs(struct vb2_queue *q, struct v4l2_requestbuffers *req) return -EBUSY; } + /* + * Call queue_cancel to clean up any buffers in the PREPARED or + * QUEUED state which is possible if buffers were prepared or + * queued without ever calling STREAMON. + */ + __vb2_queue_cancel(q); ret = __vb2_queue_free(q, q->num_buffers); if (ret) return ret; -- cgit v1.1 From e4d2581649fe87bbd506c4d55591c4de9d2962d8 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Mon, 3 Feb 2014 11:22:45 -0300 Subject: [media] vb2: replace BUG by WARN_ON No need to oops for this, WARN_ON is good enough. Signed-off-by: Hans Verkuil Acked-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab --- drivers/media/v4l2-core/videobuf2-core.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/media/v4l2-core/videobuf2-core.c b/drivers/media/v4l2-core/videobuf2-core.c index 17f1d07..f8fe1d9 100644 --- a/drivers/media/v4l2-core/videobuf2-core.c +++ b/drivers/media/v4l2-core/videobuf2-core.c @@ -2597,9 +2597,9 @@ static int __vb2_init_fileio(struct vb2_queue *q, int read) /* * Sanity check */ - if ((read && !(q->io_modes & VB2_READ)) || - (!read && !(q->io_modes & VB2_WRITE))) - BUG(); + if (WARN_ON((read && !(q->io_modes & VB2_READ)) || + (!read && !(q->io_modes & VB2_WRITE)))) + return -EINVAL; /* * Check if device supports mapping buffers to kernel virtual space. -- cgit v1.1 From 3f1a9a33a58eebcc5799d9a6b797e9e19cf8627f Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Tue, 25 Feb 2014 09:42:45 -0300 Subject: [media] vb2: fix streamoff handling if streamon wasn't called If you request buffers, then queue buffers and then call STREAMOFF those buffers are not returned to their dequeued state because streamoff will just return if q->streaming was 0. This means that afterwards you can never QBUF that same buffer again unless you do STREAMON, REQBUFS or close the filehandle first. It is clear that if you do STREAMOFF even if no STREAMON was called before, you still want to have all buffers returned to their proper dequeued state. Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/v4l2-core/videobuf2-core.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/media/v4l2-core/videobuf2-core.c b/drivers/media/v4l2-core/videobuf2-core.c index f8fe1d9..d853cd4 100644 --- a/drivers/media/v4l2-core/videobuf2-core.c +++ b/drivers/media/v4l2-core/videobuf2-core.c @@ -2125,14 +2125,14 @@ static int vb2_internal_streamoff(struct vb2_queue *q, enum v4l2_buf_type type) return -EINVAL; } - if (!q->streaming) { - dprintk(3, "streamoff successful: not streaming\n"); - return 0; - } - /* * Cancel will pause streaming and remove all buffers from the driver * and videobuf, effectively returning control over them to userspace. + * + * Note that we do this even if q->streaming == 0: if you prepare or + * queue buffers, and then call streamoff without ever having called + * streamon, you would still expect those buffers to be returned to + * their normal dequeued state. */ __vb2_queue_cancel(q); -- cgit v1.1 From 9cf3c31a8b63f56066de73695e256b7da96fff1e Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Fri, 28 Feb 2014 13:30:48 -0300 Subject: [media] vb2: call buf_finish after the state check Don't call buf_finish unless we know that the buffer is in a valid state. Signed-off-by: Hans Verkuil Acked-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab --- drivers/media/v4l2-core/videobuf2-core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/media/v4l2-core/videobuf2-core.c b/drivers/media/v4l2-core/videobuf2-core.c index d853cd4..f9059bb 100644 --- a/drivers/media/v4l2-core/videobuf2-core.c +++ b/drivers/media/v4l2-core/videobuf2-core.c @@ -1929,8 +1929,6 @@ static int vb2_internal_dqbuf(struct vb2_queue *q, struct v4l2_buffer *b, bool n if (ret < 0) return ret; - call_vb_qop(vb, buf_finish, vb); - switch (vb->state) { case VB2_BUF_STATE_DONE: dprintk(3, "dqbuf: Returning done buffer\n"); @@ -1943,6 +1941,8 @@ static int vb2_internal_dqbuf(struct vb2_queue *q, struct v4l2_buffer *b, bool n return -EINVAL; } + call_vb_qop(vb, buf_finish, vb); + /* Fill buffer information for the userspace */ __fill_v4l2_buffer(vb, b); /* Remove from videobuf queue */ -- cgit v1.1 From 48d829dadb80a2570aaa99fa324da41b3e05f43b Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Fri, 21 Feb 2014 05:34:49 -0300 Subject: [media] vivi: correctly cleanup after a start_streaming failure If start_streaming fails then any queued buffers must be given back to the vb2 core. Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/platform/vivi.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/vivi.c b/drivers/media/platform/vivi.c index 776015b..cfe7548 100644 --- a/drivers/media/platform/vivi.c +++ b/drivers/media/platform/vivi.c @@ -889,10 +889,20 @@ static void buffer_queue(struct vb2_buffer *vb) static int start_streaming(struct vb2_queue *vq, unsigned int count) { struct vivi_dev *dev = vb2_get_drv_priv(vq); + int err; dprintk(dev, 1, "%s\n", __func__); dev->seq_count = 0; - return vivi_start_generating(dev); + err = vivi_start_generating(dev); + if (err) { + struct vivi_buffer *buf, *tmp; + + list_for_each_entry_safe(buf, tmp, &dev->vidq.active, list) { + list_del(&buf->list); + vb2_buffer_done(&buf->vb, VB2_BUF_STATE_QUEUED); + } + } + return err; } /* abort streaming and wait for last buffer */ -- cgit v1.1 From ba38acb1423aa0bc9cd2b38229452b4056911130 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Tue, 25 Feb 2014 07:15:54 -0300 Subject: [media] vivi: fix ENUM_FRAMEINTERVALS implementation This function never checked if width and height are correct. Add such a check so the v4l2-compliance tool returns OK again for vivi. Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/platform/vivi.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/vivi.c b/drivers/media/platform/vivi.c index cfe7548..3890f4f 100644 --- a/drivers/media/platform/vivi.c +++ b/drivers/media/platform/vivi.c @@ -1121,7 +1121,11 @@ static int vidioc_enum_frameintervals(struct file *file, void *priv, if (!fmt) return -EINVAL; - /* regarding width & height - we support any */ + /* check for valid width/height */ + if (fival->width < 48 || fival->width > MAX_WIDTH || (fival->width & 3)) + return -EINVAL; + if (fival->height < 32 || fival->height > MAX_HEIGHT) + return -EINVAL; fival->type = V4L2_FRMIVAL_TYPE_CONTINUOUS; -- cgit v1.1 From 88e4fcda55e07278fcf5f6eea684685ffc0633e2 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 4 Mar 2014 20:49:07 -0300 Subject: [media] em28xx: only enable PCTV 80e led when streaming Instead of keeping the led always on, use it to indicate when DVB is streaming. Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/em28xx/em28xx-cards.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/media/usb/em28xx/em28xx-cards.c b/drivers/media/usb/em28xx/em28xx-cards.c index 66d9c87..2fb300e 100644 --- a/drivers/media/usb/em28xx/em28xx-cards.c +++ b/drivers/media/usb/em28xx/em28xx-cards.c @@ -228,8 +228,8 @@ static struct em28xx_reg_seq terratec_cinergy_USB_XS_FR_digital[] = { 7: LED on, active high */ static struct em28xx_reg_seq em2874_pctv_80e_digital[] = { {EM28XX_R06_I2C_CLK, 0x45, 0xff, 10}, /*400 KHz*/ - {EM2874_R80_GPIO_P0_CTRL, 0x80, 0xff, 100},/*Demod reset*/ - {EM2874_R80_GPIO_P0_CTRL, 0xc0, 0xff, 10}, + {EM2874_R80_GPIO_P0_CTRL, 0x00, 0xff, 100},/*Demod reset*/ + {EM2874_R80_GPIO_P0_CTRL, 0x40, 0xff, 10}, { -1, -1, -1, -1}, }; @@ -526,6 +526,16 @@ static struct em28xx_led kworld_ub435q_v3_leds[] = { {-1, 0, 0, 0}, }; +static struct em28xx_led pctv_80e_leds[] = { + { + .role = EM28XX_LED_DIGITAL_CAPTURING, + .gpio_reg = EM2874_R80_GPIO_P0_CTRL, + .gpio_mask = 0x80, + .inverted = 0, + }, + {-1, 0, 0, 0}, +}; + /* * Board definitions @@ -2179,6 +2189,7 @@ struct em28xx_board em28xx_boards[] = { .dvb_gpio = em2874_pctv_80e_digital, .decoder = EM28XX_NODECODER, .ir_codes = RC_MAP_PINNACLE_PCTV_HD, + .leds = pctv_80e_leds, }, /* 1ae7:9003/9004 SpeedLink Vicious And Devine Laplace webcam * Empia EM2765 + OmniVision OV2640 */ -- cgit v1.1 From 47677e51e2a4040c204d7971a5103592600185b1 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Wed, 5 Mar 2014 11:21:07 -0300 Subject: [media] em28xx: Only deallocate struct em28xx after finishing all extensions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We can't free struct em28xx while one of the extensions is still using it. So, add a kref() to control it, freeing it only after the extensions fini calls. Reviewed-by: Frank Schäfer Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/em28xx/em28xx-audio.c | 7 ++++++- drivers/media/usb/em28xx/em28xx-cards.c | 32 +++++++++++++++++++++++++------- drivers/media/usb/em28xx/em28xx-dvb.c | 5 ++++- drivers/media/usb/em28xx/em28xx-input.c | 8 +++++++- drivers/media/usb/em28xx/em28xx-video.c | 15 ++++++++------- drivers/media/usb/em28xx/em28xx.h | 8 ++++++-- 6 files changed, 56 insertions(+), 19 deletions(-) diff --git a/drivers/media/usb/em28xx/em28xx-audio.c b/drivers/media/usb/em28xx/em28xx-audio.c index 0f5b6f3..f75c0a5 100644 --- a/drivers/media/usb/em28xx/em28xx-audio.c +++ b/drivers/media/usb/em28xx/em28xx-audio.c @@ -301,6 +301,7 @@ static int snd_em28xx_capture_open(struct snd_pcm_substream *substream) goto err; } + kref_get(&dev->ref); dev->adev.users++; mutex_unlock(&dev->lock); @@ -341,6 +342,7 @@ static int snd_em28xx_pcm_close(struct snd_pcm_substream *substream) substream->runtime->dma_area = NULL; } mutex_unlock(&dev->lock); + kref_put(&dev->ref, em28xx_free_device); return 0; } @@ -895,6 +897,8 @@ static int em28xx_audio_init(struct em28xx *dev) em28xx_info("Binding audio extension\n"); + kref_get(&dev->ref); + printk(KERN_INFO "em28xx-audio.c: Copyright (C) 2006 Markus " "Rechberger\n"); printk(KERN_INFO @@ -967,7 +971,7 @@ static int em28xx_audio_fini(struct em28xx *dev) if (dev == NULL) return 0; - if (dev->has_alsa_audio != 1) { + if (!dev->has_alsa_audio) { /* This device does not support the extension (in this case the device is expecting the snd-usb-audio module or doesn't have analog audio support at all) */ @@ -986,6 +990,7 @@ static int em28xx_audio_fini(struct em28xx *dev) dev->adev.sndcard = NULL; } + kref_put(&dev->ref, em28xx_free_device); return 0; } diff --git a/drivers/media/usb/em28xx/em28xx-cards.c b/drivers/media/usb/em28xx/em28xx-cards.c index 2fb300e..e7ec3b7 100644 --- a/drivers/media/usb/em28xx/em28xx-cards.c +++ b/drivers/media/usb/em28xx/em28xx-cards.c @@ -2939,7 +2939,7 @@ static void flush_request_modules(struct em28xx *dev) * unregisters the v4l2,i2c and usb devices * called when the device gets disconnected or at module unload */ -void em28xx_release_resources(struct em28xx *dev) +static void em28xx_release_resources(struct em28xx *dev) { /*FIXME: I2C IR should be disconnected */ @@ -2956,7 +2956,27 @@ void em28xx_release_resources(struct em28xx *dev) mutex_unlock(&dev->lock); }; -EXPORT_SYMBOL_GPL(em28xx_release_resources); + +/** + * em28xx_free_device() - Free em28xx device + * + * @ref: struct kref for em28xx device + * + * This is called when all extensions and em28xx core unregisters a device + */ +void em28xx_free_device(struct kref *ref) +{ + struct em28xx *dev = kref_to_dev(ref); + + em28xx_info("Freeing device\n"); + + if (!dev->disconnected) + em28xx_release_resources(dev); + + kfree(dev->alt_max_pkt_size_isoc); + kfree(dev); +} +EXPORT_SYMBOL_GPL(em28xx_free_device); /* * em28xx_init_dev() @@ -3409,6 +3429,8 @@ static int em28xx_usb_probe(struct usb_interface *interface, dev->dvb_xfer_bulk ? "bulk" : "isoc"); } + kref_init(&dev->ref); + request_modules(dev); /* Should be the last thing to do, to avoid newer udev's to @@ -3453,11 +3475,7 @@ static void em28xx_usb_disconnect(struct usb_interface *interface) em28xx_close_extension(dev); em28xx_release_resources(dev); - - if (!dev->users) { - kfree(dev->alt_max_pkt_size_isoc); - kfree(dev); - } + kref_put(&dev->ref, em28xx_free_device); } static int em28xx_usb_suspend(struct usb_interface *interface, diff --git a/drivers/media/usb/em28xx/em28xx-dvb.c b/drivers/media/usb/em28xx/em28xx-dvb.c index d4986bd..cacdca3 100644 --- a/drivers/media/usb/em28xx/em28xx-dvb.c +++ b/drivers/media/usb/em28xx/em28xx-dvb.c @@ -1043,7 +1043,6 @@ static int em28xx_dvb_init(struct em28xx *dev) em28xx_info("Binding DVB extension\n"); dvb = kzalloc(sizeof(struct em28xx_dvb), GFP_KERNEL); - if (dvb == NULL) { em28xx_info("em28xx_dvb: memory allocation failed\n"); return -ENOMEM; @@ -1521,6 +1520,9 @@ static int em28xx_dvb_init(struct em28xx *dev) dvb->adapter.mfe_shared = mfe_shared; em28xx_info("DVB extension successfully initialized\n"); + + kref_get(&dev->ref); + ret: em28xx_set_mode(dev, EM28XX_SUSPEND); mutex_unlock(&dev->lock); @@ -1577,6 +1579,7 @@ static int em28xx_dvb_fini(struct em28xx *dev) em28xx_unregister_dvb(dvb); kfree(dvb); dev->dvb = NULL; + kref_put(&dev->ref, em28xx_free_device); } return 0; diff --git a/drivers/media/usb/em28xx/em28xx-input.c b/drivers/media/usb/em28xx/em28xx-input.c index 47a2c1d..2a9bf66 100644 --- a/drivers/media/usb/em28xx/em28xx-input.c +++ b/drivers/media/usb/em28xx/em28xx-input.c @@ -676,6 +676,8 @@ static int em28xx_ir_init(struct em28xx *dev) return 0; } + kref_get(&dev->ref); + if (dev->board.buttons) em28xx_init_buttons(dev); @@ -816,7 +818,7 @@ static int em28xx_ir_fini(struct em28xx *dev) /* skip detach on non attached boards */ if (!ir) - return 0; + goto ref_put; if (ir->rc) rc_unregister_device(ir->rc); @@ -824,6 +826,10 @@ static int em28xx_ir_fini(struct em28xx *dev) /* done */ kfree(ir); dev->ir = NULL; + +ref_put: + kref_put(&dev->ref, em28xx_free_device); + return 0; } diff --git a/drivers/media/usb/em28xx/em28xx-video.c b/drivers/media/usb/em28xx/em28xx-video.c index 13466c4..0856e5d 100644 --- a/drivers/media/usb/em28xx/em28xx-video.c +++ b/drivers/media/usb/em28xx/em28xx-video.c @@ -1837,7 +1837,6 @@ static int em28xx_v4l2_open(struct file *filp) video_device_node_name(vdev), v4l2_type_names[fh_type], dev->users); - if (mutex_lock_interruptible(&dev->lock)) return -ERESTARTSYS; fh = kzalloc(sizeof(struct em28xx_fh), GFP_KERNEL); @@ -1869,6 +1868,7 @@ static int em28xx_v4l2_open(struct file *filp) v4l2_device_call_all(&dev->v4l2_dev, 0, tuner, s_radio); } + kref_get(&dev->ref); dev->users++; mutex_unlock(&dev->lock); @@ -1926,9 +1926,8 @@ static int em28xx_v4l2_fini(struct em28xx *dev) dev->clk = NULL; } - if (dev->users) - em28xx_warn("Device is open ! Memory deallocation is deferred on last close.\n"); mutex_unlock(&dev->lock); + kref_put(&dev->ref, em28xx_free_device); return 0; } @@ -1976,11 +1975,9 @@ static int em28xx_v4l2_close(struct file *filp) mutex_lock(&dev->lock); if (dev->users == 1) { - /* free the remaining resources if device is disconnected */ - if (dev->disconnected) { - kfree(dev->alt_max_pkt_size_isoc); + /* No sense to try to write to the device */ + if (dev->disconnected) goto exit; - } /* Save some power by putting tuner to sleep */ v4l2_device_call_all(&dev->v4l2_dev, 0, core, s_power, 0); @@ -2001,6 +1998,8 @@ static int em28xx_v4l2_close(struct file *filp) exit: dev->users--; mutex_unlock(&dev->lock); + kref_put(&dev->ref, em28xx_free_device); + return 0; } @@ -2515,6 +2514,8 @@ static int em28xx_v4l2_init(struct em28xx *dev) em28xx_info("V4L2 extension successfully initialized\n"); + kref_get(&dev->ref); + mutex_unlock(&dev->lock); return 0; diff --git a/drivers/media/usb/em28xx/em28xx.h b/drivers/media/usb/em28xx/em28xx.h index 9e44f5b..2051fc9 100644 --- a/drivers/media/usb/em28xx/em28xx.h +++ b/drivers/media/usb/em28xx/em28xx.h @@ -32,6 +32,7 @@ #include #include #include +#include #include #include @@ -536,9 +537,10 @@ struct em28xx_i2c_bus { enum em28xx_i2c_algo_type algo_type; }; - /* main device struct */ struct em28xx { + struct kref ref; + /* generic device properties */ char name[30]; /* name (including minor) of the device */ int model; /* index in the device_data struct */ @@ -710,6 +712,8 @@ struct em28xx { struct em28xx_dvb *dvb; }; +#define kref_to_dev(d) container_of(d, struct em28xx, ref) + struct em28xx_ops { struct list_head next; char *name; @@ -771,7 +775,7 @@ extern struct em28xx_board em28xx_boards[]; extern struct usb_device_id em28xx_id_table[]; int em28xx_tuner_callback(void *ptr, int component, int command, int arg); void em28xx_setup_xc3028(struct em28xx *dev, struct xc2028_ctrl *ctl); -void em28xx_release_resources(struct em28xx *dev); +void em28xx_free_device(struct kref *ref); /* Provided by em28xx-camera.c */ int em28xx_detect_sensor(struct em28xx *dev); -- cgit v1.1 From b45e34f2a6724042c068bf588322598c5ae435de Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Fri, 7 Mar 2014 14:40:46 -0300 Subject: [media] em28xx-dvb: remove one level of identation at fini callback MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Simplify the logic a little by removing one level of identation. Also, it only makes sense to print something if the .fini callback is actually doing something. Reviewed-by: Frank Schäfer Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/em28xx/em28xx-dvb.c | 48 +++++++++++++++++++---------------- 1 file changed, 26 insertions(+), 22 deletions(-) diff --git a/drivers/media/usb/em28xx/em28xx-dvb.c b/drivers/media/usb/em28xx/em28xx-dvb.c index cacdca3..6638394 100644 --- a/drivers/media/usb/em28xx/em28xx-dvb.c +++ b/drivers/media/usb/em28xx/em28xx-dvb.c @@ -1543,6 +1543,9 @@ static inline void prevent_sleep(struct dvb_frontend_ops *ops) static int em28xx_dvb_fini(struct em28xx *dev) { + struct em28xx_dvb *dvb; + struct i2c_client *client; + if (dev->is_audio_only) { /* Shouldn't initialize IR for this interface */ return 0; @@ -1553,35 +1556,36 @@ static int em28xx_dvb_fini(struct em28xx *dev) return 0; } - em28xx_info("Closing DVB extension"); + if (!dev->dvb) + return 0; - if (dev->dvb) { - struct em28xx_dvb *dvb = dev->dvb; - struct i2c_client *client = dvb->i2c_client_tuner; + em28xx_info("Closing DVB extension"); - em28xx_uninit_usb_xfer(dev, EM28XX_DIGITAL_MODE); + dvb = dev->dvb; + client = dvb->i2c_client_tuner; - if (dev->disconnected) { - /* We cannot tell the device to sleep - * once it has been unplugged. */ - if (dvb->fe[0]) - prevent_sleep(&dvb->fe[0]->ops); - if (dvb->fe[1]) - prevent_sleep(&dvb->fe[1]->ops); - } + em28xx_uninit_usb_xfer(dev, EM28XX_DIGITAL_MODE); - /* remove I2C tuner */ - if (client) { - module_put(client->dev.driver->owner); - i2c_unregister_device(client); - } + if (dev->disconnected) { + /* We cannot tell the device to sleep + * once it has been unplugged. */ + if (dvb->fe[0]) + prevent_sleep(&dvb->fe[0]->ops); + if (dvb->fe[1]) + prevent_sleep(&dvb->fe[1]->ops); + } - em28xx_unregister_dvb(dvb); - kfree(dvb); - dev->dvb = NULL; - kref_put(&dev->ref, em28xx_free_device); + /* remove I2C tuner */ + if (client) { + module_put(client->dev.driver->owner); + i2c_unregister_device(client); } + em28xx_unregister_dvb(dvb); + kfree(dvb); + dev->dvb = NULL; + kref_put(&dev->ref, em28xx_free_device); + return 0; } -- cgit v1.1 From c4cfb29303ddf26dab0b754d26f0917db90f8144 Mon Sep 17 00:00:00 2001 From: Fengguang Wu Date: Sun, 9 Mar 2014 09:08:30 -0300 Subject: [media] drx-j: drxj_default_aud_data_g can be static Fix sparse warning: drivers/media/dvb-frontends/drx39xyj/drxj.c:1039:16: sparse: symbol 'drxj_default_aud_data_g' was not declared. Should it be static? Signed-off-by: Fengguang Wu Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drxj.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index a99040b..0232b14 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -902,7 +902,7 @@ struct drx_demod_instance drxj_default_demod_g = { * This structure is DRXK specific. * */ -struct drx_aud_data drxj_default_aud_data_g = { +static struct drx_aud_data drxj_default_aud_data_g = { false, /* audio_is_active */ DRX_AUD_STANDARD_AUTO, /* audio_standard */ -- cgit v1.1 From 73b8922fefed64c9bcb70e25b30a069bb9e61f40 Mon Sep 17 00:00:00 2001 From: Dave Jones Date: Wed, 4 Sep 2013 23:51:48 -0300 Subject: [media] drx-d: add missing braces in drxd_hard.c:DRXD_init No functional changes, but removes a duplicate check, if !state->type_A. Signed-off-by: Dave Jones Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drxd_hard.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/media/dvb-frontends/drxd_hard.c b/drivers/media/dvb-frontends/drxd_hard.c index 959ae36..5b87ece 100644 --- a/drivers/media/dvb-frontends/drxd_hard.c +++ b/drivers/media/dvb-frontends/drxd_hard.c @@ -2688,11 +2688,11 @@ static int DRXD_init(struct drxd_state *state, const u8 *fw, u32 fw_size) status = EnableAndResetMB(state); if (status < 0) break; - if (state->type_A) + if (state->type_A) { status = ResetCEFR(state); if (status < 0) break; - + } if (fw) { status = DownloadMicrocode(state, fw, fw_size); if (status < 0) -- cgit v1.1 From db5657c5ec47d3a787d4be300f97041ada51f806 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sun, 9 Mar 2014 09:32:58 -0300 Subject: [media] drx-j: Don't use 0 as NULL Fixes the following warnings: drivers/media/dvb-frontends/drx39xyj/drxj.c:1679:65: warning: Using plain integer as NULL pointer drivers/media/dvb-frontends/drx39xyj/drxj.c:1679:71: warning: Using plain integer as NULL pointer drivers/media/dvb-frontends/drx39xyj/drxj.c:1681:52: warning: Using plain integer as NULL pointer drivers/media/dvb-frontends/drx39xyj/drxj.c:1681:58: warning: Using plain integer as NULL pointer Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drxj.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index 0232b14..af3b69c 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -1676,9 +1676,10 @@ static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr, * In single master mode, split the read and write actions. * No special action is needed for write chunks here. */ - rc = drxbsp_i2c_write_read(dev_addr, bufx, buf, 0, 0, 0); + rc = drxbsp_i2c_write_read(dev_addr, bufx, buf, + NULL, 0, NULL); if (rc == 0) - rc = drxbsp_i2c_write_read(0, 0, 0, dev_addr, todo, data); + rc = drxbsp_i2c_write_read(NULL, 0, NULL, dev_addr, todo, data); #else /* In multi master mode, do everything in one RW action */ rc = drxbsp_i2c_write_read(dev_addr, bufx, buf, dev_addr, todo, -- cgit v1.1 From 87bf0e54872097de30752b8dc0f90eff8c53a11d Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sun, 9 Mar 2014 09:36:59 -0300 Subject: [media] drx-j: Fix dubious usage of "&" instead of "&&" Fixes the following warnings: drivers/media/dvb-frontends/drx39xyj/drxj.c:16764:68: warning: dubious: x & !y drivers/media/dvb-frontends/drx39xyj/drxj.c:16778:68: warning: dubious: x & !y drivers/media/dvb-frontends/drx39xyj/drxj.c:16797:68: warning: dubious: x & !y Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drxj.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index af3b69c..1e6dab7 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -16762,12 +16762,12 @@ static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_par case DRX_OOB_MODE_A: if ( /* signal is transmitted inverted */ - ((oob_param->spectrum_inverted == true) & + ((oob_param->spectrum_inverted == true) && /* and tuner is not mirroring the signal */ (!mirror_freq_spect_oob)) | /* or */ /* signal is transmitted noninverted */ - ((oob_param->spectrum_inverted == false) & + ((oob_param->spectrum_inverted == false) && /* and tuner is mirroring the signal */ (mirror_freq_spect_oob)) ) @@ -16780,12 +16780,12 @@ static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_par case DRX_OOB_MODE_B_GRADE_A: if ( /* signal is transmitted inverted */ - ((oob_param->spectrum_inverted == true) & + ((oob_param->spectrum_inverted == true) && /* and tuner is not mirroring the signal */ (!mirror_freq_spect_oob)) | /* or */ /* signal is transmitted noninverted */ - ((oob_param->spectrum_inverted == false) & + ((oob_param->spectrum_inverted == false) && /* and tuner is mirroring the signal */ (mirror_freq_spect_oob)) ) @@ -16799,12 +16799,12 @@ static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_par default: if ( /* signal is transmitted inverted */ - ((oob_param->spectrum_inverted == true) & + ((oob_param->spectrum_inverted == true) && /* and tuner is not mirroring the signal */ (!mirror_freq_spect_oob)) | /* or */ /* signal is transmitted noninverted */ - ((oob_param->spectrum_inverted == false) & + ((oob_param->spectrum_inverted == false) && /* and tuner is mirroring the signal */ (mirror_freq_spect_oob)) ) -- cgit v1.1 From d1f2aae3d91ba107b68540aad7fbf188b734b566 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sun, 9 Mar 2014 09:46:39 -0300 Subject: [media] drx39xxj.h: Fix undefined reference to attach function As reported by the kbuild test robot : drivers/built-in.o: In function `em28xx_dvb_init': em28xx-dvb.c:(.text+0x876f2c): undefined reference to `drx39xxj_attach' That happens when CONFIG_VIDEO_EM28XX_DVB is selected, and neither CONFIG_MEDIA_SUBDRV_AUTOSELECT or DVB_DRX39XYJ is selected. Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drx39xxj.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h index 2e0c50f..cfd0b96 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h @@ -34,6 +34,12 @@ struct drx39xxj_state { const struct firmware *fw; }; +#if IS_ENABLED(CONFIG_DVB_DRX39XYJ) struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c); +#else +static inline struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) { + return NULL; +}; +#endif #endif /* DVB_DUMMY_FE_H */ -- cgit v1.1 From 1d001c3fde34992bd3607ad57221655cbfc74068 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sun, 9 Mar 2014 10:10:19 -0300 Subject: [media] drx-j: don't use mc_info before checking if its not NULL smatch warning: drivers/media/dvb-frontends/drx39xyj/drxj.c:20803 drx_ctrl_u_code() warn: variable dereferenced before check 'mc_info' (see line 20800) Reported-by: Dan Carpenter Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drxj.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index 1e6dab7..a8fd53b 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -20208,12 +20208,14 @@ static int drx_ctrl_u_code(struct drx_demod_instance *demod, const u8 *mc_data_init = NULL; u8 *mc_data = NULL; unsigned size; - char *mc_file = mc_info->mc_file; + char *mc_file; /* Check arguments */ - if (!mc_info || !mc_file) + if (!mc_info || !mc_info->mc_file) return -EINVAL; + mc_file = mc_info->mc_file; + if (!demod->firmware) { const struct firmware *fw = NULL; -- cgit v1.1 From b6c4065eef7ce18d29870cbcf979e7d8c803c551 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sun, 9 Mar 2014 07:34:51 -0300 Subject: [media] drx-j: get rid of dead code There are large chunks of code at drx-j that aren't used. Most of them are due to analog TV support. Well, just enabling them won't make analog support work, as devices with DRX and analog support requires an extra chip (avf4910). We don't have drivers for it, nor the current device that uses this frontend has support for analog TV. So, let's just get rid of this code. If latter needed, this patch can easily be reverted from git history. Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drxj.c | 10769 +++----------------------- 1 file changed, 1128 insertions(+), 9641 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index a8fd53b..e8c8908 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -1028,13 +1028,6 @@ ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode); static int power_down_aud(struct drx_demod_instance *demod); -#if 0 -static int power_up_aud(struct drx_demod_instance *demod, bool set_standard); - -static int -aud_ctrl_set_standard(struct drx_demod_instance *demod, enum drx_aud_standard *standard); -#endif - static int ctrl_set_cfg_pre_saw(struct drx_demod_instance *demod, struct drxj_cfg_pre_saw *pre_saw); @@ -1047,97 +1040,6 @@ ctrl_set_cfg_afe_gain(struct drx_demod_instance *demod, struct drxj_cfg_afe_gain /*============================================================================*/ /*============================================================================*/ -#if 0 -/** -* \fn void mult32(u32 a, u32 b, u32 *h, u32 *l) -* \brief 32bitsx32bits signed multiplication -* \param a 32 bits multiplicant, typecast from signed to unisgned -* \param b 32 bits multiplier, typecast from signed to unisgned -* \param h pointer to high part 64 bits result, typecast from signed to unisgned -* \param l pointer to low part 64 bits result -* -* For the 2n+n addition a + b: -* if a >= 0, then h += 0 (sign extension = 0) -* but if a < 0, then h += 2^n-1 ==> h -= 1. -* -* Also, if a + b < 2^n, then a + b >= a && a + b >= b -* but if a + b >= 2^n, then R = a + b - 2^n, -* and because a < 2^n && b < 2*n ==> R < a && R < b. -* Therefore, to detect overflow, simply compare the addition result with -* one of the operands; if the result is smaller, overflow has occurred and -* h must be incremented. -* -* Booth multiplication uses additions and subtractions to reduce the number -* of iterations. This is done by taking three subsequent bits abc and calculating -* the following multiplication factor: -2a + b + c. This factor is multiplied -* by the second operand and added to the result. Next, the first operand is -* shifted two bits (hence one of the three bits is reused) and the process -* repeated. The last iteration has only two bits left, but we simply add -* a zero to the end. -* -* Hence: (n=4) -* 1 * a = 0 * 4a + 1 * a -* 2 * a = 1 * 4a - 2 * a -* 3 * a = 1 * 4a - 1 * a -* -1 * a = 0 * 4a - 1 * a -* -5 * a = -1 * 4a - 1 * a -* -* etc. -* -* Note that the function is type size independent. Any unsigned integer type -* can be substituted for booth_t. -* -*/ - -#define DRX_IS_BOOTH_NEGATIVE(__a) (((__a) & (1 << (sizeof(u32) * 8 - 1))) != 0) - -static void mult32(u32 a, u32 b, u32 *h, u32 *l) -{ - unsigned int i; - *h = *l = 0; - - /* n/2 iterations; shift operand a left two bits after each iteration. */ - /* This automatically appends a zero to the operand for the last iteration. */ - for (i = 0; i < sizeof(a) * 8; i += 2, a = a << 2) { - /* Shift result left two bits */ - *h = (*h << 2) + (*l >> (sizeof(*l) * 8 - 2)); - *l = (*l << 2); - - /* Take the first three bits of operand a for the Booth conversion: */ - /* 0, 7: do nothing */ - /* 1, 2: add b */ - /* 3 : add 2b */ - /* 4 : subtract 2b */ - /* 5, 6: subtract b */ - switch (a >> (sizeof(a) * 8 - 3)) { - case 3: - *l += b; - *h = *h - DRX_IS_BOOTH_NEGATIVE(b) + (*l < b); - case 1: - case 2: - *l += b; - *h = *h - DRX_IS_BOOTH_NEGATIVE(b) + (*l < b); - break; - case 4: - *l -= b; - *h = *h - !DRX_IS_BOOTH_NEGATIVE(b) + !b + (*l < - ((u32) - (- - ((s32) - b)))); - case 5: - case 6: - *l -= b; - *h = *h - !DRX_IS_BOOTH_NEGATIVE(b) + !b + (*l < - ((u32) - (- - ((s32) - b)))); - break; - } - } -} -#endif /*============================================================================*/ @@ -1331,108 +1233,6 @@ static u32 frac_times1e6(u32 N, u32 D) /*============================================================================*/ -#if 0 -/** -* \brief Compute: 100 * 10^( gd_b / 200 ). -* \param u32 gd_b Gain in 0.1dB -* \return u32 Gainfactor in 0.01 resolution -* -*/ -static u32 d_b2lin_times100(u32 gd_b) -{ - u32 result = 0; - u32 nr6d_b_steps = 0; - u32 remainder = 0; - u32 remainder_fac = 0; - - /* start with factors 2 (6.02dB) */ - nr6d_b_steps = gd_b * 1000UL / 60206UL; - if (nr6d_b_steps > 17) { - /* Result max overflow if > log2( maxu32 / 2e4 ) ~= 17.7 */ - return MAX_U32; - } - result = (1 << nr6d_b_steps); - - /* calculate remaining factor, - poly approximation of 10^(gd_b/200): - - y = 1E-04x2 + 0.0106x + 1.0026 - - max deviation < 0.005 for range x = [0 ... 60] - */ - remainder = ((gd_b * 1000UL) % 60206UL) / 1000UL; - /* using 1e-4 for poly calculation */ - remainder_fac = 1 * remainder * remainder; - remainder_fac += 106 * remainder; - remainder_fac += 10026; - - /* multiply by remaining factor */ - result *= remainder_fac; - - /* conversion from 1e-4 to 1e-2 */ - return (result + 50) / 100; -} - -#define FRAC_FLOOR 0 -#define FRAC_CEIL 1 -#define FRAC_ROUND 2 -/** -* \fn u32 frac( u32 N, u32 D, u16 RC ) -* \brief Compute: N/D. -* \param N nominator 32-bits. -* \param D denominator 32-bits. -* \param RC-result correction: 0-floor; 1-ceil; 2-round -* \return u32 -* \retval N/D, 32 bits -* -* If D=0 returns 0 -*/ -static u32 frac(u32 N, u32 D, u16 RC) -{ - u32 remainder = 0; - u32 frac = 0; - u16 bit_cnt = 32; - - if (D == 0) { - frac = 0; - remainder = 0; - - return frac; - } - - if (D > N) { - frac = 0; - remainder = N; - } else { - remainder = 0; - frac = N; - while (bit_cnt-- > 0) { - remainder <<= 1; - remainder |= ((frac & 0x80000000) >> 31); - frac <<= 1; - if (remainder < D) { - frac &= 0xFFFFFFFE; - } else { - remainder -= D; - frac |= 0x1; - } - } - - /* result correction if needed */ - if ((RC == FRAC_CEIL) && (remainder != 0)) { - /* ceil the result */ - /*(remainder is not zero -> value behind decimal point exists) */ - frac++; - } - if ((RC == FRAC_ROUND) && (remainder >= D >> 1)) { - /* remainder is bigger from D/2 -> round the result */ - frac++; - } - } - - return frac; -} -#endif /** * \brief Values for NICAM prescaler gain. Computed from dB to integer @@ -3542,67 +3342,6 @@ rw_error: /*----------------------------------------------------------------------------*/ -#if 0 -/** -* \fn int ctrl_get_cfg_mpeg_output() -* \brief Get MPEG output configuration of the device. -* \param devmod Pointer to demodulator instance. -* \param cfg_data Pointer to MPEG output configuaration struct. -* \return int. -* -* Retrieve MPEG output configuartion. -* -*/ -static int -ctrl_get_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_output *cfg_data) -{ - struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); - struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL); - enum drx_lock_status lock_status = DRX_NOT_LOCKED; - int rc; - u32 rate_reg = 0; - u32 data64hi = 0; - u32 data64lo = 0; - - if (cfg_data == NULL) - return -EINVAL; - - dev_addr = demod->my_i2c_dev_addr; - common_attr = demod->my_common_attr; - - cfg_data->enable_mpeg_output = common_attr->mpeg_cfg.enable_mpeg_output; - cfg_data->insert_rs_byte = common_attr->mpeg_cfg.insert_rs_byte; - cfg_data->enable_parallel = common_attr->mpeg_cfg.enable_parallel; - cfg_data->invert_data = common_attr->mpeg_cfg.invert_data; - cfg_data->invert_err = common_attr->mpeg_cfg.invert_err; - cfg_data->invert_str = common_attr->mpeg_cfg.invert_str; - cfg_data->invert_val = common_attr->mpeg_cfg.invert_val; - cfg_data->invert_clk = common_attr->mpeg_cfg.invert_clk; - cfg_data->static_clk = common_attr->mpeg_cfg.static_clk; - cfg_data->bitrate = 0; - - rc = ctrl_lock_status(demod, &lock_status); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - if ((lock_status == DRX_LOCKED)) { - rc = drxdap_fasi_read_reg32(dev_addr, FEC_OC_RCN_DYN_RATE_LO__A, &rate_reg, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - /* Frcn_rate = rate_reg * Fsys / 2 ^ 25 */ - mult32(rate_reg, common_attr->sys_clock_freq * 1000, &data64hi, - &data64lo); - cfg_data->bitrate = (data64hi << 7) | (data64lo >> 25); - } - - return 0; -rw_error: - return -EIO; -} -#endif /*----------------------------------------------------------------------------*/ /* MPEG Output Configuration Functions - end */ @@ -3729,40 +3468,6 @@ rw_error: /*----------------------------------------------------------------------------*/ /** -* \fn int set_mpeg_output_clock_rate() -* \brief Set MPEG output clock rate. -* \param devmod Pointer to demodulator instance. -* \return int. -* -* This routine should be called during a set channel of QAM/VSB -* -*/ -#if 0 -static int set_mpeg_output_clock_rate(struct drx_demod_instance *demod) -{ - struct drxj_data *ext_attr = (struct drxj_data *) (NULL); - struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); - int rc; - - dev_addr = demod->my_i2c_dev_addr; - ext_attr = (struct drxj_data *) demod->my_ext_attr; - - if (ext_attr->mpeg_output_clock_rate != DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO) { - rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_PERIOD__A, ext_attr->mpeg_output_clock_rate - 1, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - } - - return 0; -rw_error: - return -EIO; -} -#endif - -/*----------------------------------------------------------------------------*/ -/** * \fn int set_mpeg_start_width() * \brief Set MPEG start width. * \param devmod Pointer to demodulator instance. @@ -3805,165 +3510,6 @@ rw_error: return -EIO; } -#if 0 -/*----------------------------------------------------------------------------*/ -/** -* \fn int ctrl_set_cfg_mpeg_output_misc() -* \brief Set miscellaneous configuartions -* \param devmod Pointer to demodulator instance. -* \param cfg_data pDRXJCfgMisc_t -* \return int. -* -* This routine can be used to set configuartion options that are DRXJ -* specific and/or added to the requirements at a late stage. -* -*/ -static int -ctrl_set_cfg_mpeg_output_misc(struct drx_demod_instance *demod, - struct drxj_cfg_mpeg_output_misc *cfg_data) -{ - struct drxj_data *ext_attr = NULL; - int rc; - - if (cfg_data == NULL) - return -EINVAL; - - ext_attr = demod->my_ext_attr; - - /* - Set disable TEI bit handling flag. - TEI must be left untouched by device in case of BER measurements using - external equipment that is unable to ignore the TEI bit in the TS. - Default will false (enable TEI bit handling). - Reverse output bit order. Default is false (msb on MD7 (parallel) or out first (serial)). - Set clock rate. Default is auto that is derived from symbol rate. - The flags and values will also be used to set registers during a set channel. - */ - ext_attr->disable_te_ihandling = cfg_data->disable_tei_handling; - ext_attr->bit_reverse_mpeg_outout = cfg_data->bit_reverse_mpeg_outout; - ext_attr->mpeg_output_clock_rate = cfg_data->mpeg_output_clock_rate; - ext_attr->mpeg_start_width = cfg_data->mpeg_start_width; - /* Don't care what the active standard is, activate setting immediatly */ - rc = set_mpegtei_handling(demod); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = bit_reverse_mpeg_output(demod); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = set_mpeg_output_clock_rate(demod); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = set_mpeg_start_width(demod); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - return 0; -rw_error: - return -EIO; -} - -/*----------------------------------------------------------------------------*/ - -/** -* \fn int ctrl_get_cfg_mpeg_output_misc() -* \brief Get miscellaneous configuartions. -* \param devmod Pointer to demodulator instance. -* \param cfg_data Pointer to DRXJCfgMisc_t. -* \return int. -* -* This routine can be used to retreive the current setting of the configuartion -* options that are DRXJ specific and/or added to the requirements at a -* late stage. -* -*/ -static int -ctrl_get_cfg_mpeg_output_misc(struct drx_demod_instance *demod, - struct drxj_cfg_mpeg_output_misc *cfg_data) -{ - struct drxj_data *ext_attr = NULL; - int rc; - u16 data = 0; - - if (cfg_data == NULL) - return -EINVAL; - - ext_attr = (struct drxj_data *) demod->my_ext_attr; - cfg_data->disable_tei_handling = ext_attr->disable_te_ihandling; - cfg_data->bit_reverse_mpeg_outout = ext_attr->bit_reverse_mpeg_outout; - cfg_data->mpeg_start_width = ext_attr->mpeg_start_width; - if (ext_attr->mpeg_output_clock_rate != DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO) { - cfg_data->mpeg_output_clock_rate = ext_attr->mpeg_output_clock_rate; - } else { - rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, FEC_OC_DTO_PERIOD__A, &data, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - cfg_data->mpeg_output_clock_rate = - (enum drxj_mpeg_output_clock_rate) (data + 1); - } - - return 0; -rw_error: - return -EIO; -} - -/*----------------------------------------------------------------------------*/ - -/** -* \fn int ctrl_get_cfg_hw_cfg() -* \brief Get HW configuartions. -* \param devmod Pointer to demodulator instance. -* \param cfg_data Pointer to Bool. -* \return int. -* -* This routine can be used to retreive the current setting of the configuartion -* options that are DRXJ specific and/or added to the requirements at a -* late stage. -* -*/ -static int -ctrl_get_cfg_hw_cfg(struct drx_demod_instance *demod, struct drxj_cfg_hw_cfg *cfg_data) -{ - int rc; - u16 data = 0; - - if (cfg_data == NULL) - return -EINVAL; - - rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_OHW_CFG__A, &data, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - cfg_data->i2c_speed = (enum drxji2c_speed) ((data >> 6) & 0x1); - cfg_data->xtal_freq = (enum drxj_xtal_freq) (data & 0x3); - - return 0; -rw_error: - return -EIO; -} -#endif - /*----------------------------------------------------------------------------*/ /* miscellaneous configuartions - end */ /*----------------------------------------------------------------------------*/ @@ -4108,68 +3654,25 @@ rw_error: return -EIO; } -#if 0 -/*============================================================================*/ /** -* \fn int ctrl_getuio_cfg() -* \brief Get modus oprandi UIO. +* \fn int ctrl_uio_write() +* \brief Write to a UIO. * \param demod Pointer to demodulator instance. -* \param uio_cfg Pointer to a configuration setting for a certain UIO. +* \param uio_data Pointer to data container for a certain UIO. * \return int. */ -static int ctrl_getuio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg *uio_cfg) +static int +ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data) { + struct drxj_data *ext_attr = (struct drxj_data *) (NULL); + int rc; + u16 pin_cfg_value = 0; + u16 value = 0; - struct drxj_data *ext_attr = (struct drxj_data *) NULL; - enum drxuio_mode *uio_mode[4] = { NULL }; - bool *uio_available[4] = { NULL }; - - ext_attr = demod->my_ext_attr; - - uio_mode[DRX_UIO1] = &ext_attr->uio_sma_tx_mode; - uio_mode[DRX_UIO2] = &ext_attr->uio_sma_rx_mode; - uio_mode[DRX_UIO3] = &ext_attr->uio_gpio_mode; - uio_mode[DRX_UIO4] = &ext_attr->uio_irqn_mode; - - uio_available[DRX_UIO1] = &ext_attr->has_smatx; - uio_available[DRX_UIO2] = &ext_attr->has_smarx; - uio_available[DRX_UIO3] = &ext_attr->has_gpio; - uio_available[DRX_UIO4] = &ext_attr->has_irqn; - - if (uio_cfg == NULL) - return -EINVAL; - - if ((uio_cfg->uio > DRX_UIO4) || (uio_cfg->uio < DRX_UIO1)) + if ((uio_data == NULL) || (demod == NULL)) return -EINVAL; - if (!*uio_available[uio_cfg->uio]) - return -EIO; - - uio_cfg->mode = *uio_mode[uio_cfg->uio]; - - return 0; -} -#endif - -/** -* \fn int ctrl_uio_write() -* \brief Write to a UIO. -* \param demod Pointer to demodulator instance. -* \param uio_data Pointer to data container for a certain UIO. -* \return int. -*/ -static int -ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data) -{ - struct drxj_data *ext_attr = (struct drxj_data *) (NULL); - int rc; - u16 pin_cfg_value = 0; - u16 value = 0; - - if ((uio_data == NULL) || (demod == NULL)) - return -EINVAL; - - ext_attr = (struct drxj_data *) demod->my_ext_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; /* Write magic word to enable pdr reg write */ rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); @@ -4353,186 +3856,6 @@ rw_error: return -EIO; } -#if 0 -/** -*\fn int ctrl_uio_read -*\brief Read from a UIO. -* \param demod Pointer to demodulator instance. -* \param uio_data Pointer to data container for a certain UIO. -* \return int. -*/ -static int ctrl_uio_read(struct drx_demod_instance *demod, struct drxuio_data *uio_data) -{ - struct drxj_data *ext_attr = (struct drxj_data *) (NULL); - int rc; - u16 pin_cfg_value = 0; - u16 value = 0; - - if ((uio_data == NULL) || (demod == NULL)) - return -EINVAL; - - ext_attr = (struct drxj_data *) demod->my_ext_attr; - - /* Write magic word to enable pdr reg write */ - rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - switch (uio_data->uio) { - /*====================================================================*/ - case DRX_UIO1: - /* DRX_UIO1: SMA_TX UIO-1 */ - if (!ext_attr->has_smatx) - return -EIO; - - if (ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_READWRITE) - return -EIO; - - pin_cfg_value = 0; - /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ - pin_cfg_value |= 0x0110; - /* io_pad_cfg_mode output mode is drive always */ - /* io_pad_cfg_drive is set to power 2 (23 mA) */ - - /* write to io pad configuration register - input mode */ - rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, pin_cfg_value, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_IN_LO__A, &value, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - if ((value & 0x8000) != 0) { /* check 15th bit - 1st UIO */ - uio_data->value = true; - } else { - uio_data->value = false; - } - break; - /*======================================================================*/ - case DRX_UIO2: - /* DRX_UIO2: SMA_RX UIO-2 */ - if (!ext_attr->has_smarx) - return -EIO; - - if (ext_attr->uio_sma_rx_mode != DRX_UIO_MODE_READWRITE) - return -EIO; - - pin_cfg_value = 0; - /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ - pin_cfg_value |= 0x0110; - /* io_pad_cfg_mode output mode is drive always */ - /* io_pad_cfg_drive is set to power 2 (23 mA) */ - - /* write to io pad configuration register - input mode */ - rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, pin_cfg_value, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_IN_LO__A, &value, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - if ((value & 0x4000) != 0) /* check 14th bit - 2nd UIO */ - uio_data->value = true; - else - uio_data->value = false; - - break; - /*=====================================================================*/ - case DRX_UIO3: - /* DRX_UIO3: GPIO UIO-3 */ - if (!ext_attr->has_gpio) - return -EIO; - - if (ext_attr->uio_gpio_mode != DRX_UIO_MODE_READWRITE) - return -EIO; - - pin_cfg_value = 0; - /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ - pin_cfg_value |= 0x0110; - /* io_pad_cfg_mode output mode is drive always */ - /* io_pad_cfg_drive is set to power 2 (23 mA) */ - - /* write to io pad configuration register - input mode */ - rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, pin_cfg_value, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* read io input data registar */ - rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_IN_HI__A, &value, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - if ((value & 0x0004) != 0) { /* check 2nd bit - 3rd UIO */ - uio_data->value = true; - } else { - uio_data->value = false; - } - break; - /*=====================================================================*/ - case DRX_UIO4: - /* DRX_UIO4: IRQN UIO-4 */ - if (!ext_attr->has_irqn) - return -EIO; - - if (ext_attr->uio_irqn_mode != DRX_UIO_MODE_READWRITE) - return -EIO; - - pin_cfg_value = 0; - /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ - pin_cfg_value |= 0x0110; - /* io_pad_cfg_mode output mode is drive always */ - /* io_pad_cfg_drive is set to power 2 (23 mA) */ - - /* write to io pad configuration register - input mode */ - rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, pin_cfg_value, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* read io input data registar */ - rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_IN_LO__A, &value, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - if ((value & 0x1000) != 0) /* check 12th bit - 4th UIO */ - uio_data->value = true; - else - uio_data->value = false; - - break; - /*====================================================================*/ - default: - return -EINVAL; - } /* switch ( uio_data->uio ) */ - - /* Write magic word to disable pdr reg write */ - rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - return 0; -rw_error: - return -EIO; -} -#endif - /*---------------------------------------------------------------------------*/ /* UIO Configuration Functions - end */ /*---------------------------------------------------------------------------*/ @@ -4648,119 +3971,6 @@ rw_error: return -EIO; } -#if 0 -/** -* \fn int ctrl_set_cfg_smart_ant() -* \brief Set Smart Antenna. -* \param pointer to struct drxj_cfg_smart_ant. -* \return int. -* -*/ -static int -ctrl_set_cfg_smart_ant(struct drx_demod_instance *demod, struct drxj_cfg_smart_ant *smart_ant) -{ - struct drxj_data *ext_attr = NULL; - struct i2c_device_addr *dev_addr = NULL; - int rc; - u32 start_time = 0; - u16 data = 0; - static bool bit_inverted; - - dev_addr = demod->my_i2c_dev_addr; - ext_attr = (struct drxj_data *) demod->my_ext_attr; - - /* check arguments */ - if (smart_ant == NULL) - return -EINVAL; - - if (bit_inverted != ext_attr->smart_ant_inverted - || ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_FIRMWARE_SMA) { - rc = smart_ant_init(demod); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - bit_inverted = ext_attr->smart_ant_inverted; - } - - /* Write magic word to enable pdr reg write */ - rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - switch (smart_ant->io) { - case DRXJ_SMT_ANT_OUTPUT: - /* enable Tx if Mode B (input) is supported */ - /* - RR16( dev_addr, SIO_SA_TX_COMMAND__A, &data ); - WR16( dev_addr, SIO_SA_TX_COMMAND__A, data | SIO_SA_TX_COMMAND_TX_ENABLE__M ); - */ - start_time = jiffies_to_msecs(jiffies); - do { - rc = drxj_dap_read_reg16(dev_addr, SIO_SA_TX_STATUS__A, &data, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - } while ((data & SIO_SA_TX_STATUS_BUSY__M) && ((jiffies_to_msecs(jiffies) - start_time) < DRXJ_MAX_WAITTIME)); - - if (data & SIO_SA_TX_STATUS_BUSY__M) - return -EIO; - - /* write to smart antenna configuration register */ - rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_DATA0__A, 0x9200 | ((smart_ant->ctrl_data & 0x0001) << 8) | ((smart_ant->ctrl_data & 0x0002) << 10) | ((smart_ant->ctrl_data & 0x0004) << 12), 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_DATA1__A, 0x4924 | ((smart_ant->ctrl_data & 0x0008) >> 2) | ((smart_ant->ctrl_data & 0x0010)) | ((smart_ant->ctrl_data & 0x0020) << 2) | ((smart_ant->ctrl_data & 0x0040) << 4) | ((smart_ant->ctrl_data & 0x0080) << 6), 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_DATA2__A, 0x2492 | ((smart_ant->ctrl_data & 0x0100) >> 8) | ((smart_ant->ctrl_data & 0x0200) >> 6) | ((smart_ant->ctrl_data & 0x0400) >> 4) | ((smart_ant->ctrl_data & 0x0800) >> 2) | ((smart_ant->ctrl_data & 0x1000)) | ((smart_ant->ctrl_data & 0x2000) << 2), 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_DATA3__A, 0xff8d, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* trigger the sending */ - rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_LENGTH__A, 56, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - break; - case DRXJ_SMT_ANT_INPUT: - /* disable Tx if Mode B (input) is supported */ - /* - RR16( dev_addr, SIO_SA_TX_COMMAND__A, &data ); - WR16( dev_addr, SIO_SA_TX_COMMAND__A, data & (~SIO_SA_TX_COMMAND_TX_ENABLE__M) ); - */ - default: - return -EINVAL; - } - /* Write magic word to enable pdr reg write */ - rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - return 0; -rw_error: - return -EIO; -} -#endif - static int scu_command(struct i2c_device_addr *dev_addr, struct drxjscu_cmd *cmd) { int rc; @@ -5141,321 +4351,6 @@ rw_error: return -EIO; } -#if 0 -/** -* \brief Configure IQM AF registers -* \param demod instance of demodulator. -* \param active -* \return int. -*/ -static int iqm_set_af(struct drx_demod_instance *demod, bool active) -{ - struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; - int rc; - u16 data = 0; - - /* Configure IQM */ - rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - if (!active) - data &= ((~IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_PD_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE)); - else - data |= (IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE | IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE | IQM_AF_STDBY_STDBY_PD_A2_ACTIVE | IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE | IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE); - rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - return 0; -rw_error: - return -EIO; -} - -/* -------------------------------------------------------------------------- */ -static int -ctrl_set_cfg_atv_output(struct drx_demod_instance *demod, struct drxj_cfg_atv_output *output_cfg); - -/** -* \brief set configuration of pin-safe mode -* \param demod instance of demodulator. -* \param enable boolean; true: activate pin-safe mode, false: de-activate p.s.m. -* \return int. -*/ -static int -ctrl_set_cfg_pdr_safe_mode(struct drx_demod_instance *demod, bool *enable) -{ - struct drxj_data *ext_attr = NULL; - struct i2c_device_addr *dev_addr = NULL; - int rc; - - if (enable == NULL) - return -EINVAL; - - dev_addr = demod->my_i2c_dev_addr; - ext_attr = (struct drxj_data *) demod->my_ext_attr; - - /* Write magic word to enable pdr reg write */ - rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - if (*enable) { - bool bridge_enabled = false; - - /* MPEG pins to input */ - rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MSTRT_CFG__A, DRXJ_PIN_SAFE_MODE, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MERR_CFG__A, DRXJ_PIN_SAFE_MODE, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MCLK_CFG__A, DRXJ_PIN_SAFE_MODE, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MVAL_CFG__A, DRXJ_PIN_SAFE_MODE, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, DRXJ_PIN_SAFE_MODE, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, DRXJ_PIN_SAFE_MODE, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, DRXJ_PIN_SAFE_MODE, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, DRXJ_PIN_SAFE_MODE, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, DRXJ_PIN_SAFE_MODE, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, DRXJ_PIN_SAFE_MODE, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, DRXJ_PIN_SAFE_MODE, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, DRXJ_PIN_SAFE_MODE, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* PD_I2C_SDA2 Bridge off, Port2 Inactive - PD_I2C_SCL2 Bridge off, Port2 Inactive */ - rc = ctrl_i2c_bridge(demod, &bridge_enabled); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_I2C_SDA2_CFG__A, DRXJ_PIN_SAFE_MODE, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_I2C_SCL2_CFG__A, DRXJ_PIN_SAFE_MODE, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* PD_GPIO Store and set to input - PD_VSYNC Store and set to input - PD_SMA_RX Store and set to input - PD_SMA_TX Store and set to input */ - rc = drxj_dap_read_reg16(dev_addr, SIO_PDR_GPIO_CFG__A, &ext_attr->pdr_safe_restore_val_gpio, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_read_reg16(dev_addr, SIO_PDR_VSYNC_CFG__A, &ext_attr->pdr_safe_restore_val_v_sync, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_read_reg16(dev_addr, SIO_PDR_SMA_RX_CFG__A, &ext_attr->pdr_safe_restore_val_sma_rx, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_read_reg16(dev_addr, SIO_PDR_SMA_TX_CFG__A, &ext_attr->pdr_safe_restore_val_sma_tx, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_GPIO_CFG__A, DRXJ_PIN_SAFE_MODE, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_VSYNC_CFG__A, DRXJ_PIN_SAFE_MODE, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_SMA_RX_CFG__A, DRXJ_PIN_SAFE_MODE, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_SMA_TX_CFG__A, DRXJ_PIN_SAFE_MODE, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* PD_RF_AGC Analog DAC outputs, cannot be set to input or tristate! - PD_IF_AGC Analog DAC outputs, cannot be set to input or tristate! */ - rc = iqm_set_af(demod, false); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* PD_CVBS Analog DAC output, standby mode - PD_SIF Analog DAC output, standby mode */ - rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STDBY__A, (ATV_TOP_STDBY_SIF_STDBY_STANDBY & (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE)), 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* PD_I2S_CL Input - PD_I2S_DA Input - PD_I2S_WS Input */ - rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_I2S_CL_CFG__A, DRXJ_PIN_SAFE_MODE, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_I2S_DA_CFG__A, DRXJ_PIN_SAFE_MODE, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_I2S_WS_CFG__A, DRXJ_PIN_SAFE_MODE, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - } else { - /* No need to restore MPEG pins; - is done in SetStandard/SetChannel */ - - /* PD_I2C_SDA2 Port2 active - PD_I2C_SCL2 Port2 active */ - rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_I2C_SDA2_CFG__A, SIO_PDR_I2C_SDA2_CFG__PRE, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_I2C_SCL2_CFG__A, SIO_PDR_I2C_SCL2_CFG__PRE, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* PD_GPIO Restore - PD_VSYNC Restore - PD_SMA_RX Restore - PD_SMA_TX Restore */ - rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_GPIO_CFG__A, ext_attr->pdr_safe_restore_val_gpio, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_VSYNC_CFG__A, ext_attr->pdr_safe_restore_val_v_sync, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_SMA_RX_CFG__A, ext_attr->pdr_safe_restore_val_sma_rx, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_SMA_TX_CFG__A, ext_attr->pdr_safe_restore_val_sma_tx, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* PD_RF_AGC, PD_IF_AGC - No need to restore; will be restored in SetStandard/SetChannel */ - - /* PD_CVBS, PD_SIF - No need to restore; will be restored in SetStandard/SetChannel */ - - /* PD_I2S_CL, PD_I2S_DA, PD_I2S_WS - Should be restored via DRX_CTRL_SET_AUD */ - } - - /* Write magic word to disable pdr reg write */ - rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - ext_attr->pdr_safe_mode = *enable; - - return 0; - -rw_error: - return -EIO; -} - -/* -------------------------------------------------------------------------- */ - -/** -* \brief get configuration of pin-safe mode -* \param demod instance of demodulator. -* \param enable boolean indicating whether pin-safe mode is active -* \return int. -*/ -static int -ctrl_get_cfg_pdr_safe_mode(struct drx_demod_instance *demod, bool *enabled) -{ - struct drxj_data *ext_attr = (struct drxj_data *) NULL; - - if (enabled == NULL) - return -EINVAL; - - ext_attr = (struct drxj_data *) demod->my_ext_attr; - *enabled = ext_attr->pdr_safe_mode; - - return 0; -} -#endif - /*============================================================================*/ /*== END AUXILIARY FUNCTIONS ==*/ /*============================================================================*/ @@ -5667,72 +4562,6 @@ static int init_agc(struct drx_demod_instance *demod) } break; #endif -#if 0 - case DRX_STANDARD_FM: - clp_sum_max = 1023; - sns_sum_max = 1023; - ki_innergain_min = (u16) (-32768); - if_iaccu_hi_tgt_min = 2047; - agc_ki_dgain = 0x7; - ki_min = 0x0225; - ki_max = 0x0547; - clp_dir_to = (u16) (-9); - sns_dir_to = (u16) (-9); - ingain_tgt_max = 9000; - clp_ctrl_mode = 1; - p_agc_if_settings = &(ext_attr->atv_if_agc_cfg); - p_agc_rf_settings = &(ext_attr->atv_rf_agc_cfg); - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, p_agc_if_settings->top, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - break; - case DRX_STANDARD_NTSC: - case DRX_STANDARD_PAL_SECAM_BG: - case DRX_STANDARD_PAL_SECAM_DK: - case DRX_STANDARD_PAL_SECAM_I: - clp_sum_max = 1023; - sns_sum_max = 1023; - ki_innergain_min = (u16) (-32768); - if_iaccu_hi_tgt_min = 2047; - agc_ki_dgain = 0x7; - ki_min = 0x0225; - ki_max = 0x0547; - clp_dir_to = (u16) (-9); - ingain_tgt_max = 9000; - p_agc_if_settings = &(ext_attr->atv_if_agc_cfg); - p_agc_rf_settings = &(ext_attr->atv_rf_agc_cfg); - sns_dir_to = (u16) (-9); - clp_ctrl_mode = 1; - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, p_agc_if_settings->top, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - break; - case DRX_STANDARD_PAL_SECAM_L: - case DRX_STANDARD_PAL_SECAM_LP: - clp_sum_max = 1023; - sns_sum_max = 1023; - ki_innergain_min = (u16) (-32768); - if_iaccu_hi_tgt_min = 2047; - agc_ki_dgain = 0x7; - ki_min = 0x0225; - ki_max = 0x0547; - clp_dir_to = (u16) (-9); - sns_dir_to = (u16) (-9); - ingain_tgt_max = 9000; - clp_ctrl_mode = 1; - p_agc_if_settings = &(ext_attr->atv_if_agc_cfg); - p_agc_rf_settings = &(ext_attr->atv_rf_agc_cfg); - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, p_agc_if_settings->top, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - break; -#endif default: return -EINVAL; } @@ -6004,85 +4833,6 @@ rw_error: return -EIO; } -#if 0 -/** -* \fn int get_sig_strength() -* \brief Retrieve signal strength for VSB and QAM. -* \param demod Pointer to demod instance -* \param u16-t Pointer to signal strength data; range 0, .. , 100. -* \return int. -* \retval 0 sig_strength contains valid data. -* \retval -EINVAL sig_strength is NULL. -* \retval -EIO Erroneous data, sig_strength contains invalid data. -*/ -#define DRXJ_AGC_TOP 0x2800 -#define DRXJ_AGC_SNS 0x1600 -#define DRXJ_RFAGC_MAX 0x3fff -#define DRXJ_RFAGC_MIN 0x800 - -static int get_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength) -{ - struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; - int rc; - u16 rf_gain = 0; - u16 if_gain = 0; - u16 if_agc_sns = 0; - u16 if_agc_top = 0; - u16 rf_agc_max = 0; - u16 rf_agc_min = 0; - - rc = drxj_dap_read_reg16(dev_addr, IQM_AF_AGC_IF__A, &if_gain, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - if_gain &= IQM_AF_AGC_IF__M; - rc = drxj_dap_read_reg16(dev_addr, IQM_AF_AGC_RF__A, &rf_gain, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rf_gain &= IQM_AF_AGC_RF__M; - - if_agc_sns = DRXJ_AGC_SNS; - if_agc_top = DRXJ_AGC_TOP; - rf_agc_max = DRXJ_RFAGC_MAX; - rf_agc_min = DRXJ_RFAGC_MIN; - - if (if_gain > if_agc_top) { - if (rf_gain > rf_agc_max) - *sig_strength = 100; - else if (rf_gain > rf_agc_min) { - if (rf_agc_max == rf_agc_min) { - pr_err("error: rf_agc_max == rf_agc_min\n"); - return -EIO; - } - *sig_strength = - 75 + 25 * (rf_gain - rf_agc_min) / (rf_agc_max - - rf_agc_min); - } else - *sig_strength = 75; - } else if (if_gain > if_agc_sns) { - if (if_agc_top == if_agc_sns) { - pr_err("error: if_agc_top == if_agc_sns\n"); - return -EIO; - } - *sig_strength = - 20 + 55 * (if_gain - if_agc_sns) / (if_agc_top - if_agc_sns); - } else { - if (!if_agc_sns) { - pr_err("error: if_agc_sns is zero!\n"); - return -EIO; - } - *sig_strength = (20 * if_gain / if_agc_sns); - } - - return 0; -rw_error: - return -EIO; -} -#endif - /** * \fn int get_acc_pkt_err() * \brief Retrieve signal strength for VSB and QAM. @@ -6132,130 +4882,6 @@ rw_error: } #endif -#if 0 -/** -* \fn int ResetAccPktErr() -* \brief Reset Accumulating packet error count. -* \param demod Pointer to demod instance -* \return int. -* \retval 0. -* \retval -EIO Erroneous data. -*/ -static int ctrl_set_cfg_reset_pkt_err(struct drx_demod_instance *demod) -{ - struct drxj_data *ext_attr = NULL; - int rc; - u16 packet_error = 0; - - ext_attr = (struct drxj_data *) demod->my_ext_attr; - ext_attr->reset_pkt_err_acc = true; - /* call to reset counter */ - rc = get_acc_pkt_err(demod, &packet_error); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - return 0; -rw_error: - return -EIO; -} - -/** -* \fn static short get_str_freq_offset() -* \brief Get symbol rate offset in QAM & 8VSB mode -* \return Error code -*/ -static int get_str_freq_offset(struct drx_demod_instance *demod, s32 *str_freq) -{ - int rc; - u32 symbol_frequency_ratio = 0; - u32 symbol_nom_frequency_ratio = 0; - - struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; - struct drxj_data *ext_attr = demod->my_ext_attr; - - rc = drxj_dap_atomic_read_reg32(dev_addr, IQM_RC_RATE_LO__A, &symbol_frequency_ratio, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - symbol_nom_frequency_ratio = ext_attr->iqm_rc_rate_ofs; - - if (symbol_frequency_ratio > symbol_nom_frequency_ratio) - *str_freq = - -1 * - frac_times1e6((symbol_frequency_ratio - - symbol_nom_frequency_ratio), - (symbol_frequency_ratio + (1 << 23))); - else - *str_freq = - frac_times1e6((symbol_nom_frequency_ratio - - symbol_frequency_ratio), - (symbol_frequency_ratio + (1 << 23))); - - return 0; -rw_error: - return -EIO; -} - -/** -* \fn static short get_ctl_freq_offset -* \brief Get the value of ctl_freq in QAM & ATSC mode -* \return Error code -*/ -static int get_ctl_freq_offset(struct drx_demod_instance *demod, s32 *ctl_freq) -{ - s32 sampling_frequency = 0; - s32 current_frequency = 0; - s32 nominal_frequency = 0; - s32 carrier_frequency_shift = 0; - s32 sign = 1; - u32 data64hi = 0; - u32 data64lo = 0; - struct drxj_data *ext_attr = NULL; - struct drx_common_attr *common_attr = NULL; - struct i2c_device_addr *dev_addr = NULL; - int rc; - - dev_addr = demod->my_i2c_dev_addr; - ext_attr = (struct drxj_data *) demod->my_ext_attr; - common_attr = (struct drx_common_attr *) demod->my_common_attr; - - sampling_frequency = common_attr->sys_clock_freq / 3; - - /* both registers are sign extended */ - nominal_frequency = ext_attr->iqm_fs_rate_ofs; - rc = drxj_dap_atomic_read_reg32(dev_addr, IQM_FS_RATE_LO__A, (u32 *)¤t_frequency, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - if (ext_attr->pos_image) { - /* negative image */ - carrier_frequency_shift = nominal_frequency - current_frequency; - } else { - /* positive image */ - carrier_frequency_shift = current_frequency - nominal_frequency; - } - - /* carrier Frequency Shift In Hz */ - if (carrier_frequency_shift < 0) { - sign = -1; - carrier_frequency_shift *= sign; - } - - /* *ctl_freq = carrier_frequency_shift * 50.625e6 / (1 << 28); */ - mult32(carrier_frequency_shift, sampling_frequency, &data64hi, &data64lo); - *ctl_freq = - (s32) ((((data64lo >> 28) & 0xf) | (data64hi << 4)) * sign); - - return 0; -rw_error: - return -EIO; -} -#endif /*============================================================================*/ @@ -6464,92 +5090,14 @@ set_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, ext_attr->qam_rf_agc_cfg = *agc_settings; break; #endif -#if 0 - case DRX_STANDARD_PAL_SECAM_BG: - case DRX_STANDARD_PAL_SECAM_DK: - case DRX_STANDARD_PAL_SECAM_I: - case DRX_STANDARD_PAL_SECAM_L: - case DRX_STANDARD_PAL_SECAM_LP: - case DRX_STANDARD_NTSC: - case DRX_STANDARD_FM: - ext_attr->atv_rf_agc_cfg = *agc_settings; - break; -#endif - default: - return -EIO; - } - - return 0; -rw_error: - return -EIO; -} - -#if 0 -/** -* \fn int get_agc_rf () -* \brief get configuration of RF AGC -* \param demod instance of demodulator. -* \param agc_settings AGC configuration structure -* \return int. -*/ -static int -get_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings) -{ - struct i2c_device_addr *dev_addr = NULL; - struct drxj_data *ext_attr = NULL; - enum drx_standard standard = DRX_STANDARD_UNKNOWN; - int rc; - - dev_addr = demod->my_i2c_dev_addr; - ext_attr = (struct drxj_data *) demod->my_ext_attr; - - /* Return stored AGC settings */ - standard = agc_settings->standard; - switch (agc_settings->standard) { - case DRX_STANDARD_8VSB: - *agc_settings = ext_attr->vsb_rf_agc_cfg; - break; -#ifndef DRXJ_VSB_ONLY - case DRX_STANDARD_ITU_A: - case DRX_STANDARD_ITU_B: - case DRX_STANDARD_ITU_C: - *agc_settings = ext_attr->qam_rf_agc_cfg; - break; -#endif -#if 0 - case DRX_STANDARD_PAL_SECAM_BG: - case DRX_STANDARD_PAL_SECAM_DK: - case DRX_STANDARD_PAL_SECAM_I: - case DRX_STANDARD_PAL_SECAM_L: - case DRX_STANDARD_PAL_SECAM_LP: - case DRX_STANDARD_NTSC: - case DRX_STANDARD_FM: - *agc_settings = ext_attr->atv_rf_agc_cfg; - break; -#endif default: return -EIO; } - agc_settings->standard = standard; - - /* Get AGC output only if standard is currently active. */ - if ((ext_attr->standard == agc_settings->standard) || - (DRXJ_ISQAMSTD(ext_attr->standard) && - DRXJ_ISQAMSTD(agc_settings->standard)) || - (DRXJ_ISATVSTD(ext_attr->standard) && - DRXJ_ISATVSTD(agc_settings->standard))) { - rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, &(agc_settings->output_level), 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - } return 0; rw_error: return -EIO; } -#endif /** * \fn int set_agc_if () @@ -6771,91 +5319,14 @@ set_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, ext_attr->qam_if_agc_cfg = *agc_settings; break; #endif -#if 0 - case DRX_STANDARD_PAL_SECAM_BG: - case DRX_STANDARD_PAL_SECAM_DK: - case DRX_STANDARD_PAL_SECAM_I: - case DRX_STANDARD_PAL_SECAM_L: - case DRX_STANDARD_PAL_SECAM_LP: - case DRX_STANDARD_NTSC: - case DRX_STANDARD_FM: - ext_attr->atv_if_agc_cfg = *agc_settings; - break; -#endif - default: - return -EIO; - } - - return 0; -rw_error: - return -EIO; -} - -#if 0 -/** -* \fn int get_agc_if () -* \brief get configuration of If AGC -* \param demod instance of demodulator. -* \param agc_settings AGC configuration structure -* \return int. -*/ -static int -get_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings) -{ - struct i2c_device_addr *dev_addr = NULL; - struct drxj_data *ext_attr = NULL; - enum drx_standard standard = DRX_STANDARD_UNKNOWN; - int rc; - - dev_addr = demod->my_i2c_dev_addr; - ext_attr = (struct drxj_data *) demod->my_ext_attr; - - /* Return stored ATV AGC settings */ - standard = agc_settings->standard; - switch (agc_settings->standard) { - case DRX_STANDARD_8VSB: - *agc_settings = ext_attr->vsb_if_agc_cfg; - break; -#ifndef DRXJ_VSB_ONLY - case DRX_STANDARD_ITU_A: - case DRX_STANDARD_ITU_B: - case DRX_STANDARD_ITU_C: - *agc_settings = ext_attr->qam_if_agc_cfg; - break; -#endif - case DRX_STANDARD_PAL_SECAM_BG: - case DRX_STANDARD_PAL_SECAM_DK: - case DRX_STANDARD_PAL_SECAM_I: - case DRX_STANDARD_PAL_SECAM_L: - case DRX_STANDARD_PAL_SECAM_LP: - case DRX_STANDARD_NTSC: - case DRX_STANDARD_FM: - *agc_settings = ext_attr->atv_if_agc_cfg; - break; default: return -EIO; } - agc_settings->standard = standard; - - /* Get AGC output only if standard is currently active */ - if ((ext_attr->standard == agc_settings->standard) || - (DRXJ_ISQAMSTD(ext_attr->standard) && - DRXJ_ISQAMSTD(agc_settings->standard)) || - (DRXJ_ISATVSTD(ext_attr->standard) && - DRXJ_ISATVSTD(agc_settings->standard))) { - /* read output level */ - rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_HI__A, &(agc_settings->output_level), 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - } return 0; rw_error: return -EIO; } -#endif /** * \fn int set_iqm_af () @@ -7832,151 +6303,29 @@ rw_error: return -EIO; } -#if 0 /** -* \fn static short get_vsb_symb_err(struct i2c_device_addr *dev_addr, u32 *ber) -* \brief Get the values of ber in VSB mode +* \fn static int get_vsbmer(struct i2c_device_addr *dev_addr, u16 *mer) +* \brief Get the values of MER * \return Error code */ -static int get_vsb_symb_err(struct i2c_device_addr *dev_addr, u32 *ser) +static int get_vsbmer(struct i2c_device_addr *dev_addr, u16 *mer) { int rc; - u16 data = 0; - u16 period = 0; - u16 prescale = 0; - u16 symb_errors_mant = 0; - u16 symb_errors_exp = 0; + u16 data_hi = 0; - rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_SYMBOL_ERRORS__A, &data, 0); + rc = drxj_dap_read_reg16(dev_addr, VSB_TOP_ERR_ENERGY_H__A, &data_hi, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - period = FEC_RS_MEASUREMENT_PERIOD; - prescale = FEC_RS_MEASUREMENT_PRESCALE; - - symb_errors_mant = data & FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__M; - symb_errors_exp = (data & FEC_RS_NR_SYMBOL_ERRORS_EXP__M) - >> FEC_RS_NR_SYMBOL_ERRORS_EXP__B; - - if (period * prescale == 0) { - pr_err("error: period and/or prescale is zero!\n"); - return -EIO; - } - *ser = (u32) frac_times1e6((symb_errors_mant << symb_errors_exp) * 1000, - (period * prescale * 77318)); + *mer = + (u16) (log1_times100(21504) - log1_times100((data_hi << 6) / 52)); return 0; rw_error: return -EIO; } -#endif - -/** -* \fn static int get_vsbmer(struct i2c_device_addr *dev_addr, u16 *mer) -* \brief Get the values of MER -* \return Error code -*/ -static int get_vsbmer(struct i2c_device_addr *dev_addr, u16 *mer) -{ - int rc; - u16 data_hi = 0; - - rc = drxj_dap_read_reg16(dev_addr, VSB_TOP_ERR_ENERGY_H__A, &data_hi, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - *mer = - (u16) (log1_times100(21504) - log1_times100((data_hi << 6) / 52)); - - return 0; -rw_error: - return -EIO; -} - -#if 0 -/*============================================================================*/ -/** -* \fn int ctrl_get_vsb_constel() -* \brief Retreive a VSB constellation point via I2C. -* \param demod Pointer to demodulator instance. -* \param complex_nr Pointer to the structure in which to store the - constellation point. -* \return int. -*/ -static int -ctrl_get_vsb_constel(struct drx_demod_instance *demod, struct drx_complex *complex_nr) -{ - struct i2c_device_addr *dev_addr = NULL; - int rc; - /**< device address */ - u16 vsb_top_comm_mb = 0; /**< VSB SL MB configuration */ - u16 vsb_top_comm_mb_init = 0; /**< VSB SL MB intial configuration */ - u16 re = 0; /**< constellation Re part */ - u32 data = 0; - - /* read device info */ - dev_addr = demod->my_i2c_dev_addr; - - /* TODO: */ - /* Monitor bus grabbing is an open external interface issue */ - /* Needs to be checked when external interface PG is updated */ - - /* Configure MB (Monitor bus) */ - rc = drxj_dap_read_reg16(dev_addr, VSB_TOP_COMM_MB__A, &vsb_top_comm_mb_init, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - /* set observe flag & MB mux */ - vsb_top_comm_mb = (vsb_top_comm_mb_init | - VSB_TOP_COMM_MB_OBS_OBS_ON | - VSB_TOP_COMM_MB_MUX_OBS_VSB_TCMEQ_2); - rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_COMM_MB__A, vsb_top_comm_mb, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* Enable MB grabber in the FEC OC */ - rc = drxj_dap_write_reg16(dev_addr, FEC_OC_OCR_MODE__A, FEC_OC_OCR_MODE_GRAB_ENABLE__M, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* Disable MB grabber in the FEC OC */ - rc = drxj_dap_write_reg16(dev_addr, FEC_OC_OCR_MODE__A, 0x0, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* read data */ - rc = drxdap_fasi_read_reg32(dev_addr, FEC_OC_OCR_GRAB_RD1__A, &data, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - re = (u16) (((data >> 10) & 0x300) | ((data >> 2) & 0xff)); - if (re & 0x0200) - re |= 0xfc00; - complex_nr->re = re; - complex_nr->im = 0; - - /* Restore MB (Monitor bus) */ - rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_COMM_MB__A, vsb_top_comm_mb_init, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - return 0; -rw_error: - return -EIO; -} -#endif /*============================================================================*/ /*== END 8VSB DATAPATH FUNCTIONS ==*/ @@ -11202,112 +9551,6 @@ rw_error: return -EIO; } -#if 0 -/** -* \fn int ctrl_get_qam_constel() -* \brief Retreive a QAM constellation point via I2C. -* \param demod Pointer to demodulator instance. -* \param complex_nr Pointer to the structure in which to store the - constellation point. -* \return int. -*/ -static int -ctrl_get_qam_constel(struct drx_demod_instance *demod, struct drx_complex *complex_nr) -{ - struct i2c_device_addr *dev_addr = NULL; - int rc; - u32 data = 0; - u16 fec_oc_ocr_mode = 0; - /**< FEC OCR grabber configuration */ - u16 qam_sl_comm_mb = 0;/**< QAM SL MB configuration */ - u16 qam_sl_comm_mb_init = 0; - /**< QAM SL MB intial configuration */ - u16 im = 0; /**< constellation Im part */ - u16 re = 0; /**< constellation Re part */ - /**< device address */ - - /* read device info */ - dev_addr = demod->my_i2c_dev_addr; - - /* TODO: */ - /* Monitor bus grabbing is an open external interface issue */ - /* Needs to be checked when external interface PG is updated */ - - /* Configure MB (Monitor bus) */ - rc = drxj_dap_read_reg16(dev_addr, QAM_SL_COMM_MB__A, &qam_sl_comm_mb_init, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - /* set observe flag & MB mux */ - qam_sl_comm_mb = qam_sl_comm_mb_init & (~(QAM_SL_COMM_MB_OBS__M + - QAM_SL_COMM_MB_MUX_OBS__M)); - qam_sl_comm_mb |= (QAM_SL_COMM_MB_OBS_ON + - QAM_SL_COMM_MB_MUX_OBS_CONST_CORR); - rc = drxj_dap_write_reg16(dev_addr, QAM_SL_COMM_MB__A, qam_sl_comm_mb, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* Enable MB grabber in the FEC OC */ - fec_oc_ocr_mode = (/* output select: observe bus */ - (FEC_OC_OCR_MODE_MB_SELECT__M & - (0x0 << FEC_OC_OCR_MODE_MB_SELECT__B)) | - /* grabber enable: on */ - (FEC_OC_OCR_MODE_GRAB_ENABLE__M & - (0x1 << FEC_OC_OCR_MODE_GRAB_ENABLE__B)) | - /* grabber select: observe bus */ - (FEC_OC_OCR_MODE_GRAB_SELECT__M & - (0x0 << FEC_OC_OCR_MODE_GRAB_SELECT__B)) | - /* grabber mode: continuous */ - (FEC_OC_OCR_MODE_GRAB_COUNTED__M & - (0x0 << FEC_OC_OCR_MODE_GRAB_COUNTED__B))); - rc = drxj_dap_write_reg16(dev_addr, FEC_OC_OCR_MODE__A, fec_oc_ocr_mode, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* Disable MB grabber in the FEC OC */ - rc = drxj_dap_write_reg16(dev_addr, FEC_OC_OCR_MODE__A, 0x00, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* read data */ - rc = drxdap_fasi_read_reg32(dev_addr, FEC_OC_OCR_GRAB_RD0__A, &data, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - re = (u16) (data & FEC_OC_OCR_GRAB_RD0__M); - im = (u16) ((data >> 16) & FEC_OC_OCR_GRAB_RD1__M); - - /* TODO: */ - /* interpret data (re & im) according to the Monitor bus mapping ?? */ - - /* sign extension, 10th bit is sign bit */ - if ((re & 0x0200) == 0x0200) - re |= 0xFC00; - if ((im & 0x0200) == 0x0200) - im |= 0xFC00; - complex_nr->re = ((s16) re); - complex_nr->im = ((s16) im); - - /* Restore MB (Monitor bus) */ - rc = drxj_dap_write_reg16(dev_addr, QAM_SL_COMM_MB__A, qam_sl_comm_mb_init, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - return 0; -rw_error: - return -EIO; -} -#endif /* #if 0 */ #endif /* #ifndef DRXJ_VSB_ONLY */ /*============================================================================*/ @@ -11376,308 +9619,159 @@ rw_error: */ /* -------------------------------------------------------------------------- */ -#if 0 -/** -* \brief Get array index for atv coef (ext_attr->atvTopCoefX[index]) -* \param standard -* \param pointer to index -* \return int. -* -*/ -static int atv_equ_coef_index(enum drx_standard standard, int *index) -{ - switch (standard) { - case DRX_STANDARD_PAL_SECAM_BG: - *index = (int)DRXJ_COEF_IDX_BG; - break; - case DRX_STANDARD_PAL_SECAM_DK: - *index = (int)DRXJ_COEF_IDX_DK; - break; - case DRX_STANDARD_PAL_SECAM_I: - *index = (int)DRXJ_COEF_IDX_I; - break; - case DRX_STANDARD_PAL_SECAM_L: - *index = (int)DRXJ_COEF_IDX_L; - break; - case DRX_STANDARD_PAL_SECAM_LP: - *index = (int)DRXJ_COEF_IDX_LP; - break; - case DRX_STANDARD_NTSC: - *index = (int)DRXJ_COEF_IDX_MN; - break; - case DRX_STANDARD_FM: - *index = (int)DRXJ_COEF_IDX_FM; - break; - default: - *index = (int)DRXJ_COEF_IDX_MN; /* still return a valid index */ - return -EIO; - break; - } - - return 0; -} - -/* -------------------------------------------------------------------------- */ /** -* \fn int atv_update_config () -* \brief Flush changes in ATV shadow registers to physical registers. +* \fn int power_down_atv () +* \brief Power down ATV. * \param demod instance of demodulator -* \param force_update don't look at standard or change flags, flush all. +* \param standard either NTSC or FM (sub strandard for ATV ) * \return int. * +* Stops and thus resets ATV and IQM block +* SIF and CVBS ADC are powered down +* Calls audio power down */ static int -atv_update_config(struct drx_demod_instance *demod, bool force_update) +power_down_atv(struct drx_demod_instance *demod, enum drx_standard standard, bool primary) { - struct i2c_device_addr *dev_addr = NULL; - struct drxj_data *ext_attr = NULL; + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + struct drxjscu_cmd cmd_scu = { /* command */ 0, + /* parameter_len */ 0, + /* result_len */ 0, + /* *parameter */ NULL, + /* *result */ NULL + }; int rc; + u16 cmd_result = 0; - dev_addr = demod->my_i2c_dev_addr; - ext_attr = (struct drxj_data *) demod->my_ext_attr; - - /* equalizer coefficients */ - if (force_update || - ((ext_attr->atv_cfg_changed_flags & DRXJ_ATV_CHANGED_COEF) != 0)) { - int index = 0; + /* ATV NTSC */ - rc = atv_equ_coef_index(ext_attr->standard, &index); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_EQU0__A, ext_attr->atv_top_equ0[index], 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_EQU1__A, ext_attr->atv_top_equ1[index], 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_EQU2__A, ext_attr->atv_top_equ2[index], 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_EQU3__A, ext_attr->atv_top_equ3[index], 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } + /* Stop ATV SCU (will reset ATV and IQM hardware */ + cmd_scu.command = SCU_RAM_COMMAND_STANDARD_ATV | + SCU_RAM_COMMAND_CMD_DEMOD_STOP; + cmd_scu.parameter_len = 0; + cmd_scu.result_len = 1; + cmd_scu.parameter = NULL; + cmd_scu.result = &cmd_result; + rc = scu_command(dev_addr, &cmd_scu); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* Disable ATV outputs (ATV reset enables CVBS, undo this) */ + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STDBY__A, (ATV_TOP_STDBY_SIF_STDBY_STANDBY & (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE)), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; } - /* bypass fast carrier recovery */ - if (force_update) { - u16 data = 0; - - rc = drxj_dap_read_reg16(dev_addr, IQM_RT_ROT_BP__A, &data, 0); + rc = drxj_dap_write_reg16(dev_addr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + if (primary) { + rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - data &= (~((u16) IQM_RT_ROT_BP_ROT_OFF__M)); - if (ext_attr->phase_correction_bypass) - data |= IQM_RT_ROT_BP_ROT_OFF_OFF; - else - data |= IQM_RT_ROT_BP_ROT_OFF_ACTIVE; - rc = drxj_dap_write_reg16(dev_addr, IQM_RT_ROT_BP__A, data, 0); + rc = set_iqm_af(demod, false); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - } - - /* peak filter setting */ - if (force_update || - ((ext_attr->atv_cfg_changed_flags & DRXJ_ATV_CHANGED_PEAK_FLT) != 0)) { - rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_VID_PEAK__A, ext_attr->atv_top_vid_peak, 0); + } else { + rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - } - - /* noise filter setting */ - if (force_update || - ((ext_attr->atv_cfg_changed_flags & DRXJ_ATV_CHANGED_NOISE_FLT) != 0)) { - rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_NOISE_TH__A, ext_attr->atv_top_noise_th, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - } - - /* SIF attenuation */ - if (force_update || - ((ext_attr->atv_cfg_changed_flags & DRXJ_ATV_CHANGED_SIF_ATT) != 0)) { - u16 attenuation = 0; - - switch (ext_attr->sif_attenuation) { - case DRXJ_SIF_ATTENUATION_0DB: - attenuation = ATV_TOP_AF_SIF_ATT_0DB; - break; - case DRXJ_SIF_ATTENUATION_3DB: - attenuation = ATV_TOP_AF_SIF_ATT_M3DB; - break; - case DRXJ_SIF_ATTENUATION_6DB: - attenuation = ATV_TOP_AF_SIF_ATT_M6DB; - break; - case DRXJ_SIF_ATTENUATION_9DB: - attenuation = ATV_TOP_AF_SIF_ATT_M9DB; - break; - default: - return -EIO; - break; - } - rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_AF_SIF_ATT__A, attenuation, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - } - - /* SIF & CVBS enable */ - if (force_update || - ((ext_attr->atv_cfg_changed_flags & DRXJ_ATV_CHANGED_OUTPUT) != 0)) { - u16 data = 0; - - rc = drxj_dap_read_reg16(dev_addr, ATV_TOP_STDBY__A, &data, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - if (ext_attr->enable_cvbs_output) - data |= ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE; - else - data &= (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE); - - if (ext_attr->enable_sif_output) - data &= (~ATV_TOP_STDBY_SIF_STDBY_STANDBY); - else - data |= ATV_TOP_STDBY_SIF_STDBY_STANDBY; - rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STDBY__A, data, 0); + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } } - - ext_attr->atv_cfg_changed_flags = 0; + rc = power_down_aud(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } return 0; rw_error: return -EIO; } -/* -------------------------------------------------------------------------- */ +/*============================================================================*/ + /** -* \fn int ctrl_set_cfg_atv_output() -* \brief Configure ATV ouputs +* \brief Power up AUD. * \param demod instance of demodulator -* \param output_cfg output configuaration * \return int. * */ -static int -ctrl_set_cfg_atv_output(struct drx_demod_instance *demod, struct drxj_cfg_atv_output *output_cfg) +static int power_down_aud(struct drx_demod_instance *demod) { + struct i2c_device_addr *dev_addr = NULL; struct drxj_data *ext_attr = NULL; int rc; - /* Check arguments */ - if (output_cfg == NULL) - return -EINVAL; - + dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; - if (output_cfg->enable_sif_output) { - switch (output_cfg->sif_attenuation) { - case DRXJ_SIF_ATTENUATION_0DB: /* fallthrough */ - case DRXJ_SIF_ATTENUATION_3DB: /* fallthrough */ - case DRXJ_SIF_ATTENUATION_6DB: /* fallthrough */ - case DRXJ_SIF_ATTENUATION_9DB: - /* Do nothing */ - break; - default: - return -EINVAL; - break; - } - - if (ext_attr->sif_attenuation != output_cfg->sif_attenuation) { - ext_attr->sif_attenuation = output_cfg->sif_attenuation; - ext_attr->atv_cfg_changed_flags |= DRXJ_ATV_CHANGED_SIF_ATT; - } - } - if (ext_attr->enable_cvbs_output != output_cfg->enable_cvbs_output) { - ext_attr->enable_cvbs_output = output_cfg->enable_cvbs_output; - ext_attr->atv_cfg_changed_flags |= DRXJ_ATV_CHANGED_OUTPUT; - } - - if (ext_attr->enable_sif_output != output_cfg->enable_sif_output) { - ext_attr->enable_sif_output = output_cfg->enable_sif_output; - ext_attr->atv_cfg_changed_flags |= DRXJ_ATV_CHANGED_OUTPUT; - } - - rc = atv_update_config(demod, false); + rc = drxj_dap_write_reg16(dev_addr, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } + ext_attr->aud_data.audio_is_active = false; + return 0; rw_error: return -EIO; } -/* -------------------------------------------------------------------------- */ /** -* \fn int ctrl_set_cfg_atv_equ_coef() -* \brief Set ATV equalizer coefficients -* \param demod instance of demodulator -* \param coef the equalizer coefficients +* \fn int set_orx_nsu_aox() +* \brief Configure OrxNsuAox for OOB +* \param demod instance of demodulator. +* \param active * \return int. -* */ -static int -ctrl_set_cfg_atv_equ_coef(struct drx_demod_instance *demod, struct drxj_cfg_atv_equ_coef *coef) +static int set_orx_nsu_aox(struct drx_demod_instance *demod, bool active) { - struct drxj_data *ext_attr = NULL; + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; int rc; - int index; - - ext_attr = (struct drxj_data *) demod->my_ext_attr; - - /* current standard needs to be an ATV standard */ - if (!DRXJ_ISATVSTD(ext_attr->standard)) - return -EIO; - - /* Check arguments */ - if ((coef == NULL) || - (coef->coef0 > (ATV_TOP_EQU0_EQU_C0__M / 2)) || - (coef->coef1 > (ATV_TOP_EQU1_EQU_C1__M / 2)) || - (coef->coef2 > (ATV_TOP_EQU2_EQU_C2__M / 2)) || - (coef->coef3 > (ATV_TOP_EQU3_EQU_C3__M / 2)) || - (coef->coef0 < ((s16) ~(ATV_TOP_EQU0_EQU_C0__M >> 1))) || - (coef->coef1 < ((s16) ~(ATV_TOP_EQU1_EQU_C1__M >> 1))) || - (coef->coef2 < ((s16) ~(ATV_TOP_EQU2_EQU_C2__M >> 1))) || - (coef->coef3 < ((s16) ~(ATV_TOP_EQU3_EQU_C3__M >> 1)))) { - return -EINVAL; - } + u16 data = 0; - rc = atv_equ_coef_index(ext_attr->standard, &index); + /* Configure NSU_AOX */ + rc = drxj_dap_read_reg16(dev_addr, ORX_NSU_AOX_STDBY_W__A, &data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - ext_attr->atv_top_equ0[index] = coef->coef0; - ext_attr->atv_top_equ1[index] = coef->coef1; - ext_attr->atv_top_equ2[index] = coef->coef2; - ext_attr->atv_top_equ3[index] = coef->coef3; - ext_attr->atv_cfg_changed_flags |= DRXJ_ATV_CHANGED_COEF; - - rc = atv_update_config(demod, false); + if (!active) + data &= ((~ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON)); + else + data |= (ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON); + rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_STDBY_W__A, data, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; @@ -11688,7534 +9782,1351 @@ rw_error: return -EIO; } -/* -------------------------------------------------------------------------- */ /** -* \fn int ctrl_get_cfg_atv_equ_coef() -* \brief Get ATV equ coef settings +* \fn int ctrl_set_oob() +* \brief Set OOB channel to be used. * \param demod instance of demodulator -* \param coef The ATV equ coefficients +* \param oob_param OOB parameters for channel setting. +* \frequency should be in KHz * \return int. * -* The values are read from the shadow registers maintained by the drxdriver -* If registers are manipulated outside of the drxdriver scope the reported -* settings will not reflect these changes because of the use of shadow -* regitsers. +* Accepts only. Returns error otherwise. +* Demapper value is written after scu_command START +* because START command causes COMM_EXEC transition +* from 0 to 1 which causes all registers to be +* overwritten with initial value * */ -static int -ctrl_get_cfg_atv_equ_coef(struct drx_demod_instance *demod, struct drxj_cfg_atv_equ_coef *coef) -{ - struct drxj_data *ext_attr = NULL; - int rc; - int index = 0; - - ext_attr = (struct drxj_data *) demod->my_ext_attr; - - /* current standard needs to be an ATV standard */ - if (!DRXJ_ISATVSTD(ext_attr->standard)) - return -EIO; - - /* Check arguments */ - if (coef == NULL) - return -EINVAL; - rc = atv_equ_coef_index(ext_attr->standard, &index); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - coef->coef0 = ext_attr->atv_top_equ0[index]; - coef->coef1 = ext_attr->atv_top_equ1[index]; - coef->coef2 = ext_attr->atv_top_equ2[index]; - coef->coef3 = ext_attr->atv_top_equ3[index]; +/* Nyquist filter impulse response */ +#define IMPULSE_COSINE_ALPHA_0_3 {-3, -4, -1, 6, 10, 7, -5, -20, -25, -10, 29, 79, 123, 140} /*sqrt raised-cosine filter with alpha=0.3 */ +#define IMPULSE_COSINE_ALPHA_0_5 { 2, 0, -2, -2, 2, 5, 2, -10, -20, -14, 20, 74, 125, 145} /*sqrt raised-cosine filter with alpha=0.5 */ +#define IMPULSE_COSINE_ALPHA_RO_0_5 { 0, 0, 1, 2, 3, 0, -7, -15, -16, 0, 34, 77, 114, 128} /*full raised-cosine filter with alpha=0.5 (receiver only) */ - return 0; -rw_error: - return -EIO; -} +/* Coefficients for the nyquist fitler (total: 27 taps) */ +#define NYQFILTERLEN 27 -/* -------------------------------------------------------------------------- */ -/** -* \fn int ctrl_set_cfg_atv_misc() -* \brief Set misc. settings for ATV. -* \param demod instance of demodulator -* \param -* \return int. -* -*/ -static int -ctrl_set_cfg_atv_misc(struct drx_demod_instance *demod, struct drxj_cfg_atv_misc *settings) +static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_param) { - struct drxj_data *ext_attr = NULL; int rc; - - /* Check arguments */ - if ((settings == NULL) || - ((settings->peak_filter) < (s16) (-8)) || - ((settings->peak_filter) > (s16) (15)) || - ((settings->noise_filter) > 15)) { - return -EINVAL; - } - /* if */ - ext_attr = (struct drxj_data *) demod->my_ext_attr; - - if (settings->peak_filter != ext_attr->atv_top_vid_peak) { - ext_attr->atv_top_vid_peak = settings->peak_filter; - ext_attr->atv_cfg_changed_flags |= DRXJ_ATV_CHANGED_PEAK_FLT; - } - - if (settings->noise_filter != ext_attr->atv_top_noise_th) { - ext_attr->atv_top_noise_th = settings->noise_filter; - ext_attr->atv_cfg_changed_flags |= DRXJ_ATV_CHANGED_NOISE_FLT; - } - - rc = atv_update_config(demod, false); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - return 0; -rw_error: - return -EIO; -} - -/* -------------------------------------------------------------------------- */ -/** -* \fn int ctrl_get_cfg_atv_misc() -* \brief Get misc settings of ATV. -* \param demod instance of demodulator -* \param settings misc. ATV settings -* \return int. -* -* The values are read from the shadow registers maintained by the drxdriver -* If registers are manipulated outside of the drxdriver scope the reported -* settings will not reflect these changes because of the use of shadow -* regitsers. -*/ -static int -ctrl_get_cfg_atv_misc(struct drx_demod_instance *demod, struct drxj_cfg_atv_misc *settings) -{ + s32 freq = 0; /* KHz */ + struct i2c_device_addr *dev_addr = NULL; struct drxj_data *ext_attr = NULL; + u16 i = 0; + bool mirror_freq_spect_oob = false; + u16 trk_filter_value = 0; + struct drxjscu_cmd scu_cmd; + u16 set_param_parameters[3]; + u16 cmd_result[2] = { 0, 0 }; + s16 nyquist_coeffs[4][(NYQFILTERLEN + 1) / 2] = { + IMPULSE_COSINE_ALPHA_0_3, /* Target Mode 0 */ + IMPULSE_COSINE_ALPHA_0_3, /* Target Mode 1 */ + IMPULSE_COSINE_ALPHA_0_5, /* Target Mode 2 */ + IMPULSE_COSINE_ALPHA_RO_0_5 /* Target Mode 3 */ + }; + u8 mode_val[4] = { 2, 2, 0, 1 }; + u8 pfi_coeffs[4][6] = { + {DRXJ_16TO8(-92), DRXJ_16TO8(-108), DRXJ_16TO8(100)}, /* TARGET_MODE = 0: PFI_A = -23/32; PFI_B = -54/32; PFI_C = 25/32; fg = 0.5 MHz (Att=26dB) */ + {DRXJ_16TO8(-64), DRXJ_16TO8(-80), DRXJ_16TO8(80)}, /* TARGET_MODE = 1: PFI_A = -16/32; PFI_B = -40/32; PFI_C = 20/32; fg = 1.0 MHz (Att=28dB) */ + {DRXJ_16TO8(-80), DRXJ_16TO8(-98), DRXJ_16TO8(92)}, /* TARGET_MODE = 2, 3: PFI_A = -20/32; PFI_B = -49/32; PFI_C = 23/32; fg = 0.8 MHz (Att=25dB) */ + {DRXJ_16TO8(-80), DRXJ_16TO8(-98), DRXJ_16TO8(92)} /* TARGET_MODE = 2, 3: PFI_A = -20/32; PFI_B = -49/32; PFI_C = 23/32; fg = 0.8 MHz (Att=25dB) */ + }; + u16 mode_index; - /* Check arguments */ - if (settings == NULL) - return -EINVAL; - + dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; + mirror_freq_spect_oob = ext_attr->mirror_freq_spect_oob; - settings->peak_filter = ext_attr->atv_top_vid_peak; - settings->noise_filter = ext_attr->atv_top_noise_th; - - return 0; -} - -/* -------------------------------------------------------------------------- */ - -/* -------------------------------------------------------------------------- */ -/** -* \fn int ctrl_get_cfg_atv_output() -* \brief -* \param demod instance of demodulator -* \param output_cfg output configuaration -* \return int. -* -*/ -static int -ctrl_get_cfg_atv_output(struct drx_demod_instance *demod, struct drxj_cfg_atv_output *output_cfg) -{ - int rc; - u16 data = 0; - - /* Check arguments */ - if (output_cfg == NULL) - return -EINVAL; - - rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, ATV_TOP_STDBY__A, &data, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - if (data & ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE) - output_cfg->enable_cvbs_output = true; - else - output_cfg->enable_cvbs_output = false; - - if (data & ATV_TOP_STDBY_SIF_STDBY_STANDBY) { - output_cfg->enable_sif_output = false; - } else { - output_cfg->enable_sif_output = true; - rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, ATV_TOP_AF_SIF_ATT__A, &data, 0); + /* Check parameters */ + if (oob_param == NULL) { + /* power off oob module */ + scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB + | SCU_RAM_COMMAND_CMD_DEMOD_STOP; + scu_cmd.parameter_len = 0; + scu_cmd.result_len = 1; + scu_cmd.result = cmd_result; + rc = scu_command(dev_addr, &scu_cmd); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = set_orx_nsu_aox(demod, false); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - output_cfg->sif_attenuation = (enum drxjsif_attenuation) data; - } - - return 0; -rw_error: - return -EIO; -} - -/* -------------------------------------------------------------------------- */ -/** -* \fn int ctrl_get_cfg_atv_agc_status() -* \brief -* \param demod instance of demodulator -* \param agc_status agc status -* \return int. -* -*/ -static int -ctrl_get_cfg_atv_agc_status(struct drx_demod_instance *demod, - struct drxj_cfg_atv_agc_status *agc_status) -{ - struct i2c_device_addr *dev_addr = NULL; - int rc; - u16 data = 0; - u32 tmp = 0; - /* Check arguments */ - if (agc_status == NULL) - return -EINVAL; + ext_attr->oob_power_on = false; + return 0; + } - dev_addr = demod->my_i2c_dev_addr; + freq = oob_param->frequency; + if ((freq < 70000) || (freq > 130000)) + return -EIO; + freq = (freq - 50000) / 50; - /* - RFgain = (IQM_AF_AGC_RF__A * 26.75)/1000 (uA) - = ((IQM_AF_AGC_RF__A * 27) - (0.25*IQM_AF_AGC_RF__A))/1000 + { + u16 index = 0; + u16 remainder = 0; + u16 *trk_filtercfg = ext_attr->oob_trk_filter_cfg; - IQM_AF_AGC_RF__A * 27 is 20 bits worst case. - */ - rc = drxj_dap_read_reg16(dev_addr, IQM_AF_AGC_RF__A, &data, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; + index = (u16) ((freq - 400) / 200); + remainder = (u16) ((freq - 400) % 200); + trk_filter_value = + trk_filtercfg[index] - (trk_filtercfg[index] - + trk_filtercfg[index + + 1]) / 10 * remainder / + 20; } - tmp = ((u32) data) * 27 - ((u32) (data >> 2)); /* nA */ - agc_status->rf_agc_gain = (u16) (tmp / 1000); /* uA */ - /* rounding */ - if (tmp % 1000 >= 500) - (agc_status->rf_agc_gain)++; - - /* - IFgain = (IQM_AF_AGC_IF__A * 26.75)/1000 (uA) - = ((IQM_AF_AGC_IF__A * 27) - (0.25*IQM_AF_AGC_IF__A))/1000 - IQM_AF_AGC_IF__A * 27 is 20 bits worst case. - */ - rc = drxj_dap_read_reg16(dev_addr, IQM_AF_AGC_IF__A, &data, 0); + /*********/ + /* Stop */ + /*********/ + rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - tmp = ((u32) data) * 27 - ((u32) (data >> 2)); /* nA */ - agc_status->if_agc_gain = (u16) (tmp / 1000); /* uA */ - /* rounding */ - if (tmp % 1000 >= 500) - (agc_status->if_agc_gain)++; - - /* - videoGain = (ATV_TOP_SFR_VID_GAIN__A/16 -150)* 0.05 (dB) - = (ATV_TOP_SFR_VID_GAIN__A/16 -150)/20 (dB) - = 10*(ATV_TOP_SFR_VID_GAIN__A/16 -150)/20 (in 0.1 dB) - = (ATV_TOP_SFR_VID_GAIN__A/16 -150)/2 (in 0.1 dB) - = (ATV_TOP_SFR_VID_GAIN__A/32) - 75 (in 0.1 dB) - */ - - rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, &data, 0); + scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB + | SCU_RAM_COMMAND_CMD_DEMOD_STOP; + scu_cmd.parameter_len = 0; + scu_cmd.result_len = 1; + scu_cmd.result = cmd_result; + rc = scu_command(dev_addr, &scu_cmd); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - /* dividing by 32 inclusive rounding */ - data >>= 4; - if ((data & 1) != 0) - data++; - data >>= 1; - agc_status->video_agc_gain = ((s16) data) - 75; /* 0.1 dB */ - - /* - audioGain = (SCU_RAM_ATV_SIF_GAIN__A -8)* 0.05 (dB) - = (SCU_RAM_ATV_SIF_GAIN__A -8)/20 (dB) - = 10*(SCU_RAM_ATV_SIF_GAIN__A -8)/20 (in 0.1 dB) - = (SCU_RAM_ATV_SIF_GAIN__A -8)/2 (in 0.1 dB) - = (SCU_RAM_ATV_SIF_GAIN__A/2) - 4 (in 0.1 dB) - */ - - rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_ATV_SIF_GAIN__A, &data, 0); - if (rc != 0) { + /*********/ + /* Reset */ + /*********/ + scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB + | SCU_RAM_COMMAND_CMD_DEMOD_RESET; + scu_cmd.parameter_len = 0; + scu_cmd.result_len = 1; + scu_cmd.result = cmd_result; + rc = scu_command(dev_addr, &scu_cmd); + if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - data &= SCU_RAM_ATV_SIF_GAIN__M; - /* dividing by 2 inclusive rounding */ - if ((data & 1) != 0) - data++; - data >>= 1; - agc_status->audio_agc_gain = ((s16) data) - 4; /* 0.1 dB */ - - /* Loop gain's */ - rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); + /***********/ + /* SET_ENV */ + /***********/ + /* set frequency, spectrum inversion and data rate */ + scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB + | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV; + scu_cmd.parameter_len = 3; + /* 1-data rate;2-frequency */ + switch (oob_param->standard) { + case DRX_OOB_MODE_A: + if ( + /* signal is transmitted inverted */ + ((oob_param->spectrum_inverted == true) && + /* and tuner is not mirroring the signal */ + (!mirror_freq_spect_oob)) | + /* or */ + /* signal is transmitted noninverted */ + ((oob_param->spectrum_inverted == false) && + /* and tuner is mirroring the signal */ + (mirror_freq_spect_oob)) + ) + set_param_parameters[0] = + SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC; + else + set_param_parameters[0] = + SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC; + break; + case DRX_OOB_MODE_B_GRADE_A: + if ( + /* signal is transmitted inverted */ + ((oob_param->spectrum_inverted == true) && + /* and tuner is not mirroring the signal */ + (!mirror_freq_spect_oob)) | + /* or */ + /* signal is transmitted noninverted */ + ((oob_param->spectrum_inverted == false) && + /* and tuner is mirroring the signal */ + (mirror_freq_spect_oob)) + ) + set_param_parameters[0] = + SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_INVSPEC; + else + set_param_parameters[0] = + SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_REGSPEC; + break; + case DRX_OOB_MODE_B_GRADE_B: + default: + if ( + /* signal is transmitted inverted */ + ((oob_param->spectrum_inverted == true) && + /* and tuner is not mirroring the signal */ + (!mirror_freq_spect_oob)) | + /* or */ + /* signal is transmitted noninverted */ + ((oob_param->spectrum_inverted == false) && + /* and tuner is mirroring the signal */ + (mirror_freq_spect_oob)) + ) + set_param_parameters[0] = + SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_INVSPEC; + else + set_param_parameters[0] = + SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_REGSPEC; + break; + } + set_param_parameters[1] = (u16) (freq & 0xFFFF); + set_param_parameters[2] = trk_filter_value; + scu_cmd.parameter = set_param_parameters; + scu_cmd.result_len = 1; + scu_cmd.result = cmd_result; + mode_index = mode_val[(set_param_parameters[0] & 0xC0) >> 6]; + rc = scu_command(dev_addr, &scu_cmd); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - agc_status->video_agc_loop_gain = - ((data & SCU_RAM_AGC_KI_DGAIN__M) >> SCU_RAM_AGC_KI_DGAIN__B); - agc_status->rf_agc_loop_gain = - ((data & SCU_RAM_AGC_KI_RF__M) >> SCU_RAM_AGC_KI_RF__B); - agc_status->if_agc_loop_gain = - ((data & SCU_RAM_AGC_KI_IF__M) >> SCU_RAM_AGC_KI_IF__B); - - return 0; -rw_error: - return -EIO; -} -/* -------------------------------------------------------------------------- */ - -/** -* \fn int power_up_atv () -* \brief Power up ATV. -* \param demod instance of demodulator -* \param standard either NTSC or FM (sub strandard for ATV ) -* \return int. -* -* * Starts ATV and IQM -* * AUdio already started during standard init for ATV. -*/ -static int power_up_atv(struct drx_demod_instance *demod, enum drx_standard standard) -{ - struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; - int rc; + rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Write magic word to enable pdr reg write */ + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_OOB_CRX_CFG__A, OOB_CRX_DRIVE_STRENGTH << SIO_PDR_OOB_CRX_CFG_DRIVE__B | 0x03 << SIO_PDR_OOB_CRX_CFG_MODE__B, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_OOB_DRX_CFG__A, OOB_DRX_DRIVE_STRENGTH << SIO_PDR_OOB_DRX_CFG_DRIVE__B | 0x03 << SIO_PDR_OOB_DRX_CFG_MODE__B, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Write magic word to disable pdr reg write */ - /* ATV NTSC */ - rc = drxj_dap_write_reg16(dev_addr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_ACTIVE, 0); + rc = drxj_dap_write_reg16(dev_addr, ORX_TOP_COMM_KEY__A, 0, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - /* turn on IQM_AF */ - rc = set_iqm_af(demod, true); + rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_AAG_LEN_W__A, 16000, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = adc_synchronization(demod); + rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_AAG_THR_W__A, 40, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE, 0); + /* ddc */ + rc = drxj_dap_write_reg16(dev_addr, ORX_DDC_OFO_SET_W__A, ORX_DDC_OFO_SET_W__PRE, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - /* Audio, already done during set standard */ - - return 0; -rw_error: - return -EIO; -} -#endif - -/* -------------------------------------------------------------------------- */ - -/** -* \fn int power_down_atv () -* \brief Power down ATV. -* \param demod instance of demodulator -* \param standard either NTSC or FM (sub strandard for ATV ) -* \return int. -* -* Stops and thus resets ATV and IQM block -* SIF and CVBS ADC are powered down -* Calls audio power down -*/ -static int -power_down_atv(struct drx_demod_instance *demod, enum drx_standard standard, bool primary) -{ - struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; - struct drxjscu_cmd cmd_scu = { /* command */ 0, - /* parameter_len */ 0, - /* result_len */ 0, - /* *parameter */ NULL, - /* *result */ NULL - }; - int rc; - u16 cmd_result = 0; - - /* ATV NTSC */ + /* nsu */ + rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_LOPOW_W__A, ext_attr->oob_lo_pow, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } - /* Stop ATV SCU (will reset ATV and IQM hardware */ - cmd_scu.command = SCU_RAM_COMMAND_STANDARD_ATV | - SCU_RAM_COMMAND_CMD_DEMOD_STOP; - cmd_scu.parameter_len = 0; - cmd_scu.result_len = 1; - cmd_scu.parameter = NULL; - cmd_scu.result = &cmd_result; - rc = scu_command(dev_addr, &cmd_scu); + /* initialization for target mode */ + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TARGET_MODE__A, SCU_RAM_ORX_TARGET_MODE_2048KBPS_SQRT, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - /* Disable ATV outputs (ATV reset enables CVBS, undo this) */ - rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STDBY__A, (ATV_TOP_STDBY_SIF_STDBY_STANDBY & (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE)), 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FREQ_GAIN_CORR__A, SCU_RAM_ORX_FREQ_GAIN_CORR_2048KBPS, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = drxj_dap_write_reg16(dev_addr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_STOP, 0); + /* Reset bits for timing and freq. recovery */ + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_CPH__A, 0x0001, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - if (primary) { - rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = set_iqm_af(demod, false); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - } else { - rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_CTI__A, 0x0002, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; } - rc = power_down_aud(demod); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_KRN__A, 0x0004, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_KRP__A, 0x0008, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - return 0; -rw_error: - return -EIO; -} - -/* -------------------------------------------------------------------------- */ -/** -* \fn int set_atv_standard () -* \brief Set up ATV demodulator. -* \param demod instance of demodulator -* \param standard either NTSC or FM (sub strandard for ATV ) -* \return int. -* -* Init all channel independent registers. -* Assuming that IQM, ATV and AUD blocks have been reset and are in STOP mode -* -*/ -#if 0 -#define SCU_RAM_ATV_ENABLE_IIR_WA__A 0x831F6D /* TODO remove after done with reg import */ -static int -set_atv_standard(struct drx_demod_instance *demod, enum drx_standard *standard) -{ -/* TODO: enable alternative for tap settings via external file - -something like: -#ifdef DRXJ_ATV_COEF_FILE -#include DRXJ_ATV_COEF_FILE -#else -... code defining fixed coef's ... -#endif - -Cutsomer must create file "customer_coefs.c.inc" containing -modified copy off the constants below, and define the compiler -switch DRXJ_ATV_COEF_FILE="customer_coefs.c.inc". - -Still to check if this will work; DRXJ_16TO8 macro may cause -trouble ? -*/ - const u8 ntsc_taps_re[] = { - DRXJ_16TO8(-12), /* re0 */ - DRXJ_16TO8(-9), /* re1 */ - DRXJ_16TO8(9), /* re2 */ - DRXJ_16TO8(19), /* re3 */ - DRXJ_16TO8(-4), /* re4 */ - DRXJ_16TO8(-24), /* re5 */ - DRXJ_16TO8(-6), /* re6 */ - DRXJ_16TO8(16), /* re7 */ - DRXJ_16TO8(6), /* re8 */ - DRXJ_16TO8(-16), /* re9 */ - DRXJ_16TO8(-5), /* re10 */ - DRXJ_16TO8(13), /* re11 */ - DRXJ_16TO8(-2), /* re12 */ - DRXJ_16TO8(-20), /* re13 */ - DRXJ_16TO8(4), /* re14 */ - DRXJ_16TO8(25), /* re15 */ - DRXJ_16TO8(-6), /* re16 */ - DRXJ_16TO8(-36), /* re17 */ - DRXJ_16TO8(2), /* re18 */ - DRXJ_16TO8(38), /* re19 */ - DRXJ_16TO8(-10), /* re20 */ - DRXJ_16TO8(-48), /* re21 */ - DRXJ_16TO8(35), /* re22 */ - DRXJ_16TO8(94), /* re23 */ - DRXJ_16TO8(-59), /* re24 */ - DRXJ_16TO8(-217), /* re25 */ - DRXJ_16TO8(50), /* re26 */ - DRXJ_16TO8(679) /* re27 */ - }; - const u8 ntsc_taps_im[] = { - DRXJ_16TO8(11), /* im0 */ - DRXJ_16TO8(1), /* im1 */ - DRXJ_16TO8(-10), /* im2 */ - DRXJ_16TO8(2), /* im3 */ - DRXJ_16TO8(24), /* im4 */ - DRXJ_16TO8(21), /* im5 */ - DRXJ_16TO8(1), /* im6 */ - DRXJ_16TO8(-4), /* im7 */ - DRXJ_16TO8(7), /* im8 */ - DRXJ_16TO8(14), /* im9 */ - DRXJ_16TO8(27), /* im10 */ - DRXJ_16TO8(42), /* im11 */ - DRXJ_16TO8(22), /* im12 */ - DRXJ_16TO8(-20), /* im13 */ - DRXJ_16TO8(2), /* im14 */ - DRXJ_16TO8(98), /* im15 */ - DRXJ_16TO8(122), /* im16 */ - DRXJ_16TO8(0), /* im17 */ - DRXJ_16TO8(-85), /* im18 */ - DRXJ_16TO8(51), /* im19 */ - DRXJ_16TO8(247), /* im20 */ - DRXJ_16TO8(192), /* im21 */ - DRXJ_16TO8(-55), /* im22 */ - DRXJ_16TO8(-95), /* im23 */ - DRXJ_16TO8(217), /* im24 */ - DRXJ_16TO8(544), /* im25 */ - DRXJ_16TO8(553), /* im26 */ - DRXJ_16TO8(302) /* im27 */ - }; - const u8 bg_taps_re[] = { - DRXJ_16TO8(-18), /* re0 */ - DRXJ_16TO8(18), /* re1 */ - DRXJ_16TO8(19), /* re2 */ - DRXJ_16TO8(-26), /* re3 */ - DRXJ_16TO8(-20), /* re4 */ - DRXJ_16TO8(36), /* re5 */ - DRXJ_16TO8(5), /* re6 */ - DRXJ_16TO8(-51), /* re7 */ - DRXJ_16TO8(15), /* re8 */ - DRXJ_16TO8(45), /* re9 */ - DRXJ_16TO8(-46), /* re10 */ - DRXJ_16TO8(-24), /* re11 */ - DRXJ_16TO8(71), /* re12 */ - DRXJ_16TO8(-17), /* re13 */ - DRXJ_16TO8(-83), /* re14 */ - DRXJ_16TO8(74), /* re15 */ - DRXJ_16TO8(75), /* re16 */ - DRXJ_16TO8(-134), /* re17 */ - DRXJ_16TO8(-40), /* re18 */ - DRXJ_16TO8(191), /* re19 */ - DRXJ_16TO8(-11), /* re20 */ - DRXJ_16TO8(-233), /* re21 */ - DRXJ_16TO8(74), /* re22 */ - DRXJ_16TO8(271), /* re23 */ - DRXJ_16TO8(-132), /* re24 */ - DRXJ_16TO8(-341), /* re25 */ - DRXJ_16TO8(172), /* re26 */ - DRXJ_16TO8(801) /* re27 */ - }; - const u8 bg_taps_im[] = { - DRXJ_16TO8(-24), /* im0 */ - DRXJ_16TO8(-10), /* im1 */ - DRXJ_16TO8(9), /* im2 */ - DRXJ_16TO8(-5), /* im3 */ - DRXJ_16TO8(-51), /* im4 */ - DRXJ_16TO8(-17), /* im5 */ - DRXJ_16TO8(31), /* im6 */ - DRXJ_16TO8(-48), /* im7 */ - DRXJ_16TO8(-95), /* im8 */ - DRXJ_16TO8(25), /* im9 */ - DRXJ_16TO8(37), /* im10 */ - DRXJ_16TO8(-123), /* im11 */ - DRXJ_16TO8(-77), /* im12 */ - DRXJ_16TO8(94), /* im13 */ - DRXJ_16TO8(-10), /* im14 */ - DRXJ_16TO8(-149), /* im15 */ - DRXJ_16TO8(10), /* im16 */ - DRXJ_16TO8(108), /* im17 */ - DRXJ_16TO8(-49), /* im18 */ - DRXJ_16TO8(-59), /* im19 */ - DRXJ_16TO8(90), /* im20 */ - DRXJ_16TO8(73), /* im21 */ - DRXJ_16TO8(55), /* im22 */ - DRXJ_16TO8(148), /* im23 */ - DRXJ_16TO8(86), /* im24 */ - DRXJ_16TO8(146), /* im25 */ - DRXJ_16TO8(687), /* im26 */ - DRXJ_16TO8(877) /* im27 */ - }; - const u8 dk_i_l_lp_taps_re[] = { - DRXJ_16TO8(-23), /* re0 */ - DRXJ_16TO8(9), /* re1 */ - DRXJ_16TO8(16), /* re2 */ - DRXJ_16TO8(-26), /* re3 */ - DRXJ_16TO8(-3), /* re4 */ - DRXJ_16TO8(13), /* re5 */ - DRXJ_16TO8(-19), /* re6 */ - DRXJ_16TO8(-3), /* re7 */ - DRXJ_16TO8(13), /* re8 */ - DRXJ_16TO8(-26), /* re9 */ - DRXJ_16TO8(-4), /* re10 */ - DRXJ_16TO8(28), /* re11 */ - DRXJ_16TO8(-15), /* re12 */ - DRXJ_16TO8(-14), /* re13 */ - DRXJ_16TO8(10), /* re14 */ - DRXJ_16TO8(1), /* re15 */ - DRXJ_16TO8(39), /* re16 */ - DRXJ_16TO8(-18), /* re17 */ - DRXJ_16TO8(-90), /* re18 */ - DRXJ_16TO8(109), /* re19 */ - DRXJ_16TO8(113), /* re20 */ - DRXJ_16TO8(-235), /* re21 */ - DRXJ_16TO8(-49), /* re22 */ - DRXJ_16TO8(359), /* re23 */ - DRXJ_16TO8(-79), /* re24 */ - DRXJ_16TO8(-459), /* re25 */ - DRXJ_16TO8(206), /* re26 */ - DRXJ_16TO8(894) /* re27 */ - }; - const u8 dk_i_l_lp_taps_im[] = { - DRXJ_16TO8(-8), /* im0 */ - DRXJ_16TO8(-20), /* im1 */ - DRXJ_16TO8(17), /* im2 */ - DRXJ_16TO8(-14), /* im3 */ - DRXJ_16TO8(-52), /* im4 */ - DRXJ_16TO8(4), /* im5 */ - DRXJ_16TO8(9), /* im6 */ - DRXJ_16TO8(-62), /* im7 */ - DRXJ_16TO8(-47), /* im8 */ - DRXJ_16TO8(0), /* im9 */ - DRXJ_16TO8(-20), /* im10 */ - DRXJ_16TO8(-48), /* im11 */ - DRXJ_16TO8(-65), /* im12 */ - DRXJ_16TO8(-23), /* im13 */ - DRXJ_16TO8(44), /* im14 */ - DRXJ_16TO8(-60), /* im15 */ - DRXJ_16TO8(-113), /* im16 */ - DRXJ_16TO8(92), /* im17 */ - DRXJ_16TO8(81), /* im18 */ - DRXJ_16TO8(-125), /* im19 */ - DRXJ_16TO8(28), /* im20 */ - DRXJ_16TO8(182), /* im21 */ - DRXJ_16TO8(35), /* im22 */ - DRXJ_16TO8(94), /* im23 */ - DRXJ_16TO8(180), /* im24 */ - DRXJ_16TO8(134), /* im25 */ - DRXJ_16TO8(657), /* im26 */ - DRXJ_16TO8(1023) /* im27 */ - }; - const u8 fm_taps_re[] = { - DRXJ_16TO8(0), /* re0 */ - DRXJ_16TO8(0), /* re1 */ - DRXJ_16TO8(0), /* re2 */ - DRXJ_16TO8(0), /* re3 */ - DRXJ_16TO8(0), /* re4 */ - DRXJ_16TO8(0), /* re5 */ - DRXJ_16TO8(0), /* re6 */ - DRXJ_16TO8(0), /* re7 */ - DRXJ_16TO8(0), /* re8 */ - DRXJ_16TO8(0), /* re9 */ - DRXJ_16TO8(0), /* re10 */ - DRXJ_16TO8(0), /* re11 */ - DRXJ_16TO8(0), /* re12 */ - DRXJ_16TO8(0), /* re13 */ - DRXJ_16TO8(0), /* re14 */ - DRXJ_16TO8(0), /* re15 */ - DRXJ_16TO8(0), /* re16 */ - DRXJ_16TO8(0), /* re17 */ - DRXJ_16TO8(0), /* re18 */ - DRXJ_16TO8(0), /* re19 */ - DRXJ_16TO8(0), /* re20 */ - DRXJ_16TO8(0), /* re21 */ - DRXJ_16TO8(0), /* re22 */ - DRXJ_16TO8(0), /* re23 */ - DRXJ_16TO8(0), /* re24 */ - DRXJ_16TO8(0), /* re25 */ - DRXJ_16TO8(0), /* re26 */ - DRXJ_16TO8(0) /* re27 */ - }; - const u8 fm_taps_im[] = { - DRXJ_16TO8(-6), /* im0 */ - DRXJ_16TO8(2), /* im1 */ - DRXJ_16TO8(14), /* im2 */ - DRXJ_16TO8(-38), /* im3 */ - DRXJ_16TO8(58), /* im4 */ - DRXJ_16TO8(-62), /* im5 */ - DRXJ_16TO8(42), /* im6 */ - DRXJ_16TO8(0), /* im7 */ - DRXJ_16TO8(-45), /* im8 */ - DRXJ_16TO8(73), /* im9 */ - DRXJ_16TO8(-65), /* im10 */ - DRXJ_16TO8(23), /* im11 */ - DRXJ_16TO8(34), /* im12 */ - DRXJ_16TO8(-77), /* im13 */ - DRXJ_16TO8(80), /* im14 */ - DRXJ_16TO8(-39), /* im15 */ - DRXJ_16TO8(-25), /* im16 */ - DRXJ_16TO8(78), /* im17 */ - DRXJ_16TO8(-90), /* im18 */ - DRXJ_16TO8(52), /* im19 */ - DRXJ_16TO8(16), /* im20 */ - DRXJ_16TO8(-77), /* im21 */ - DRXJ_16TO8(97), /* im22 */ - DRXJ_16TO8(-62), /* im23 */ - DRXJ_16TO8(-8), /* im24 */ - DRXJ_16TO8(75), /* im25 */ - DRXJ_16TO8(-100), /* im26 */ - DRXJ_16TO8(70) /* im27 */ - }; + /* AGN_LOCK = {2048>>3, -2048, 8, -8, 0, 1}; */ + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_TH__A, 2048 >> 3, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_TOTH__A, (u16)(-2048), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_ONLOCK_TTH__A, 8, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_UNLOCK_TTH__A, (u16)(-8), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_MASK__A, 1, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } - struct i2c_device_addr *dev_addr = NULL; - struct drxjscu_cmd cmd_scu = { /* command */ 0, - /* parameter_len */ 0, - /* result_len */ 0, - /* *parameter */ NULL, - /* *result */ NULL - }; - u16 cmd_result = 0; - u16 cmd_param = 0; - struct drxj_data *ext_attr = NULL; - int rc; + /* DGN_LOCK = {10, -2048, 8, -8, 0, 1<<1}; */ + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_TH__A, 10, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_TOTH__A, (u16)(-2048), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_ONLOCK_TTH__A, 8, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_UNLOCK_TTH__A, (u16)(-8), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_MASK__A, 1 << 1, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } - ext_attr = (struct drxj_data *) demod->my_ext_attr; - dev_addr = demod->my_i2c_dev_addr; + /* FRQ_LOCK = {15,-2048, 8, -8, 0, 1<<2}; */ + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TH__A, 17, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TOTH__A, (u16)(-2048), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_ONLOCK_TTH__A, 8, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_UNLOCK_TTH__A, (u16)(-8), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_MASK__A, 1 << 2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } - rc = drxj_dap_write_reg16(dev_addr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_STOP, 0); + /* PHA_LOCK = {5000, -2048, 8, -8, 0, 1<<3}; */ + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_TH__A, 3000, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_TOTH__A, (u16)(-2048), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_ONLOCK_TTH__A, 8, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_UNLOCK_TTH__A, (u16)(-8), 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_MASK__A, 1 << 3, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); + + /* TIM_LOCK = {300, -2048, 8, -8, 0, 1<<4}; */ + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_TH__A, 400, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - /* Reset ATV SCU */ - cmd_scu.command = SCU_RAM_COMMAND_STANDARD_ATV | - SCU_RAM_COMMAND_CMD_DEMOD_RESET; - cmd_scu.parameter_len = 0; - cmd_scu.result_len = 1; - cmd_scu.parameter = NULL; - cmd_scu.result = &cmd_result; - rc = scu_command(dev_addr, &cmd_scu); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_TOTH__A, (u16)(-2048), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_ONLOCK_TTH__A, 8, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_UNLOCK_TTH__A, (u16)(-8), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_MASK__A, 1 << 4, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_MOD_CONTROL__A, ATV_TOP_MOD_CONTROL__PRE, 0); + /* EQU_LOCK = {20, -2048, 8, -8, 0, 1<<5}; */ + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_TH__A, 20, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_TOTH__A, (u16)(-2048), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_ONLOCK_TTH__A, 4, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_UNLOCK_TTH__A, (u16)(-4), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_MASK__A, 1 << 5, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - /* TODO remove AUTO/OFF patches after ucode fix. */ - switch (*standard) { - case DRX_STANDARD_NTSC: - /* NTSC */ - cmd_param = SCU_RAM_ATV_STANDARD_STANDARD_MN; + /* PRE-Filter coefficients (PFI) */ + rc = drxdap_fasi_write_block(dev_addr, ORX_FWP_PFI_A_W__A, sizeof(pfi_coeffs[mode_index]), ((u8 *)pfi_coeffs[mode_index]), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, ORX_TOP_MDE_W__A, mode_index, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } - rc = drxj_dap_write_reg16(dev_addr, IQM_RT_LO_INCR__A, IQM_RT_LO_INCR_MN, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(ntsc_taps_re), ((u8 *)ntsc_taps_re), 0); + /* NYQUIST-Filter coefficients (NYQ) */ + for (i = 0; i < (NYQFILTERLEN + 1) / 2; i++) { + rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_ADR_W__A, i, 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(ntsc_taps_im), ((u8 *)ntsc_taps_im), 0); + rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_COF_RW__A, nyquist_coeffs[mode_index][i], 0); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } + } + rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_ADR_W__A, 31, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_ACTIVE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /*********/ + /* Start */ + /*********/ + scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB + | SCU_RAM_COMMAND_CMD_DEMOD_START; + scu_cmd.parameter_len = 0; + scu_cmd.result_len = 1; + scu_cmd.result = cmd_result; + rc = scu_command(dev_addr, &scu_cmd); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } - rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_CR_AMP_TH__A, ATV_TOP_CR_AMP_TH_MN, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_CR_CONT__A, (ATV_TOP_CR_CONT_CR_P_MN | ATV_TOP_CR_CONT_CR_D_MN | ATV_TOP_CR_CONT_CR_I_MN), 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_MN, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_MN | ATV_TOP_STD_VID_POL_MN), 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_MN, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } + rc = set_orx_nsu_aox(demod, true); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_STHR_W__A, ext_attr->oob_pre_saw, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM | SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE), 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_BG_MN, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - ext_attr->phase_correction_bypass = false; - ext_attr->enable_cvbs_output = true; - break; - case DRX_STANDARD_FM: - /* FM */ - cmd_param = SCU_RAM_ATV_STANDARD_STANDARD_FM; - - rc = drxj_dap_write_reg16(dev_addr, IQM_RT_LO_INCR__A, 2994, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, 0, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(fm_taps_re), ((u8 *)fm_taps_re), 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(fm_taps_im), ((u8 *)fm_taps_im), 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_FM | ATV_TOP_STD_VID_POL_FM), 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_MOD_CONTROL__A, 0, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_CR_CONT__A, 0, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW | SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM), 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, IQM_RT_ROT_BP__A, IQM_RT_ROT_BP_ROT_OFF_OFF, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - ext_attr->phase_correction_bypass = true; - ext_attr->enable_cvbs_output = false; - break; - case DRX_STANDARD_PAL_SECAM_BG: - /* PAL/SECAM B/G */ - cmd_param = SCU_RAM_ATV_STANDARD_STANDARD_B; - - rc = drxj_dap_write_reg16(dev_addr, IQM_RT_LO_INCR__A, 1820, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } /* TODO check with IS */ - rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(bg_taps_re), ((u8 *)bg_taps_re), 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(bg_taps_im), ((u8 *)bg_taps_im), 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_BG, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_CR_AMP_TH__A, ATV_TOP_CR_AMP_TH_BG, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_CR_CONT__A, (ATV_TOP_CR_CONT_CR_P_BG | ATV_TOP_CR_CONT_CR_D_BG | ATV_TOP_CR_CONT_CR_I_BG), 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_BG, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_BG | ATV_TOP_STD_VID_POL_BG), 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM | SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE), 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_BG_MN, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - ext_attr->phase_correction_bypass = false; - ext_attr->atv_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; - ext_attr->enable_cvbs_output = true; - break; - case DRX_STANDARD_PAL_SECAM_DK: - /* PAL/SECAM D/K */ - cmd_param = SCU_RAM_ATV_STANDARD_STANDARD_DK; - - rc = drxj_dap_write_reg16(dev_addr, IQM_RT_LO_INCR__A, 2225, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } /* TODO check with IS */ - rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(dk_i_l_lp_taps_re), ((u8 *)dk_i_l_lp_taps_re), 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(dk_i_l_lp_taps_im), ((u8 *)dk_i_l_lp_taps_im), 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_CR_AMP_TH__A, ATV_TOP_CR_AMP_TH_DK, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_DK, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_CR_CONT__A, (ATV_TOP_CR_CONT_CR_P_DK | ATV_TOP_CR_CONT_CR_D_DK | ATV_TOP_CR_CONT_CR_I_DK), 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_DK, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_DK | ATV_TOP_STD_VID_POL_DK), 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM | SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE), 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_DK, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - ext_attr->phase_correction_bypass = false; - ext_attr->atv_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; - ext_attr->enable_cvbs_output = true; - break; - case DRX_STANDARD_PAL_SECAM_I: - /* PAL/SECAM I */ - cmd_param = SCU_RAM_ATV_STANDARD_STANDARD_I; - - rc = drxj_dap_write_reg16(dev_addr, IQM_RT_LO_INCR__A, 2225, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } /* TODO check with IS */ - rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(dk_i_l_lp_taps_re), ((u8 *)dk_i_l_lp_taps_re), 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(dk_i_l_lp_taps_im), ((u8 *)dk_i_l_lp_taps_im), 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_CR_AMP_TH__A, ATV_TOP_CR_AMP_TH_I, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_I, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_CR_CONT__A, (ATV_TOP_CR_CONT_CR_P_I | ATV_TOP_CR_CONT_CR_D_I | ATV_TOP_CR_CONT_CR_I_I), 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_I, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_I | ATV_TOP_STD_VID_POL_I), 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM | SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE), 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_I, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - ext_attr->phase_correction_bypass = false; - ext_attr->atv_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; - ext_attr->enable_cvbs_output = true; - break; - case DRX_STANDARD_PAL_SECAM_L: - /* PAL/SECAM L with negative modulation */ - cmd_param = SCU_RAM_ATV_STANDARD_STANDARD_L; - - rc = drxj_dap_write_reg16(dev_addr, IQM_RT_LO_INCR__A, 2225, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } /* TODO check with IS */ - rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_L, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(dk_i_l_lp_taps_re), ((u8 *)dk_i_l_lp_taps_re), 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(dk_i_l_lp_taps_im), ((u8 *)dk_i_l_lp_taps_im), 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_CR_AMP_TH__A, 0x2, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } /* TODO check with IS */ - rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_CR_CONT__A, (ATV_TOP_CR_CONT_CR_P_L | ATV_TOP_CR_CONT_CR_D_L | ATV_TOP_CR_CONT_CR_I_L), 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_L, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_L | ATV_TOP_STD_VID_POL_L), 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_AM | SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_ENABLE | SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW), 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_LLP, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - ext_attr->phase_correction_bypass = false; - ext_attr->atv_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_USER; - ext_attr->atv_if_agc_cfg.output_level = ext_attr->atv_rf_agc_cfg.top; - ext_attr->enable_cvbs_output = true; - break; - case DRX_STANDARD_PAL_SECAM_LP: - /* PAL/SECAM L with positive modulation */ - cmd_param = SCU_RAM_ATV_STANDARD_STANDARD_LP; - - rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_VID_AMP__A, ATV_TOP_VID_AMP_LP, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, IQM_RT_LO_INCR__A, 2225, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } /* TODO check with IS */ - rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, IQM_CF_MIDTAP_RE__M, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(dk_i_l_lp_taps_re), ((u8 *)dk_i_l_lp_taps_re), 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(dk_i_l_lp_taps_im), ((u8 *)dk_i_l_lp_taps_im), 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_CR_AMP_TH__A, 0x2, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } /* TODO check with IS */ - rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_CR_CONT__A, (ATV_TOP_CR_CONT_CR_P_LP | ATV_TOP_CR_CONT_CR_D_LP | ATV_TOP_CR_CONT_CR_I_LP), 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_CR_OVM_TH__A, ATV_TOP_CR_OVM_TH_LP, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STD__A, (ATV_TOP_STD_MODE_LP | ATV_TOP_STD_VID_POL_LP), 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_AGC_MODE__A, (SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_AM | SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_ENABLE | SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW), 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_AMS_MAX_REF__A, SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_LLP, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - ext_attr->phase_correction_bypass = false; - ext_attr->atv_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_USER; - ext_attr->atv_if_agc_cfg.output_level = ext_attr->atv_rf_agc_cfg.top; - ext_attr->enable_cvbs_output = true; - break; - default: - return -EIO; - } - - /* Common initializations FM & NTSC & B/G & D/K & I & L & LP */ - if (!ext_attr->has_lna) { - rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AMUX__A, 0x01, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - } - - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_STANDARD__A, 0x002, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_LEN__A, IQM_AF_CLP_LEN_ATV, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_TH__A, IQM_AF_CLP_TH_ATV, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SNS_LEN__A, IQM_AF_SNS_LEN_ATV, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->atv_pre_saw_cfg)); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AGC_IF__A, 10248, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - ext_attr->iqm_rc_rate_ofs = 0x00200000L; - rc = drxdap_fasi_write_reg32(dev_addr, IQM_RC_RATE_OFS_LO__A, ext_attr->iqm_rc_rate_ofs, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, IQM_RC_ADJ_SEL__A, IQM_RC_ADJ_SEL_B_OFF, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, IQM_RC_STRETCH__A, IQM_RC_STRETCH_ATV, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - rc = drxj_dap_write_reg16(dev_addr, IQM_RT_ACTIVE__A, IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_ON | IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_ON, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - rc = drxj_dap_write_reg16(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_ATV__M, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SYMMETRIC__A, IQM_CF_SYMMETRIC_IM__M, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - /* default: SIF in standby */ - rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_SYNC_SLICE__A, ATV_TOP_SYNC_SLICE_MN, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_MOD_ACCU__A, ATV_TOP_MOD_ACCU__PRE, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_SIF_GAIN__A, 0x080, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_FAGC_TH_RED__A, 10, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_AAGC_CNT__A, 7, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_NAGC_KI_MIN__A, 0x0225, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_NAGC_KI_MAX__A, 0x0547, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_KI_CHANGE_TH__A, 20, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_LOCK__A, 0, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - rc = drxj_dap_write_reg16(dev_addr, IQM_RT_DELAY__A, IQM_RT_DELAY__PRE, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_BPC_KI_MIN__A, 531, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_PAGC_KI_MIN__A, 1061, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_BP_REF_MIN__A, 100, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_BP_REF_MAX__A, 260, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_BP_LVL__A, 0, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_AMS_MAX__A, 0, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_AMS_MIN__A, 2047, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_GPIO__A, 0, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* Override reset values with current shadow settings */ - rc = atv_update_config(demod, true); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* Configure/restore AGC settings */ - rc = init_agc(demod); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = set_agc_if(demod, &(ext_attr->atv_if_agc_cfg), false); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = set_agc_rf(demod, &(ext_attr->atv_rf_agc_cfg), false); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->atv_pre_saw_cfg)); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* Set SCU ATV substandard,assuming this doesn't require running ATV block */ - cmd_scu.command = SCU_RAM_COMMAND_STANDARD_ATV | - SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV; - cmd_scu.parameter_len = 1; - cmd_scu.result_len = 1; - cmd_scu.parameter = &cmd_param; - cmd_scu.result = &cmd_result; - rc = scu_command(dev_addr, &cmd_scu); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* turn the analog work around on/off (must after set_env b/c it is set in mc) */ - if (ext_attr->mfx == 0x03) { - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_ENABLE_IIR_WA__A, 0, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - } else { - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_ENABLE_IIR_WA__A, 1, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ATV_IIR_CRIT__A, 225, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - } - - return 0; -rw_error: - return -EIO; -} - -/* -------------------------------------------------------------------------- */ - -/** -* \fn int set_atv_channel () -* \brief Set ATV channel. -* \param demod: instance of demod. -* \return int. -* -* Not much needs to be done here, only start the SCU for NTSC/FM. -* Mirrored channels are not expected in the RF domain, so IQM FS setting -* doesn't need to be remembered. -* The channel->mirror parameter is therefor ignored. -* -*/ -static int -set_atv_channel(struct drx_demod_instance *demod, - s32 tuner_freq_offset, - struct drx_channel *channel, enum drx_standard standard) -{ - struct drxjscu_cmd cmd_scu = { /* command */ 0, - /* parameter_len */ 0, - /* result_len */ 0, - /* parameter */ NULL, - /* result */ NULL - }; - u16 cmd_result = 0; - struct drxj_data *ext_attr = NULL; - struct i2c_device_addr *dev_addr = NULL; - int rc; - - dev_addr = demod->my_i2c_dev_addr; - ext_attr = (struct drxj_data *) demod->my_ext_attr; - - /* - Program frequency shifter - No need to account for mirroring on RF - */ - if (channel->mirror == DRX_MIRROR_AUTO) - ext_attr->mirror = DRX_MIRROR_NO; - else - ext_attr->mirror = channel->mirror; - - rc = set_frequency(demod, channel, tuner_freq_offset); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_CR_FREQ__A, ATV_TOP_CR_FREQ__PRE, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* Start ATV SCU */ - cmd_scu.command = SCU_RAM_COMMAND_STANDARD_ATV | - SCU_RAM_COMMAND_CMD_DEMOD_START; - cmd_scu.parameter_len = 0; - cmd_scu.result_len = 1; - cmd_scu.parameter = NULL; - cmd_scu.result = &cmd_result; - rc = scu_command(dev_addr, &cmd_scu); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - -/* if ( (ext_attr->standard == DRX_STANDARD_FM) && (ext_attr->flagSetAUDdone == true) ) - { - ext_attr->detectedRDS = (bool)false; - }*/ - - return 0; -rw_error: - return -EIO; -} - -/* -------------------------------------------------------------------------- */ - -/** -* \fn int get_atv_channel () -* \brief Set ATV channel. -* \param demod: instance of demod. -* \param channel: pointer to channel data. -* \param standard: NTSC or FM. -* \return int. -* -* Covers NTSC, PAL/SECAM - B/G, D/K, I, L, LP and FM. -* Computes the frequency offset in te RF domain and adds it to -* channel->frequency. Determines the value for channel->bandwidth. -* -*/ -static int -get_atv_channel(struct drx_demod_instance *demod, - struct drx_channel *channel, enum drx_standard standard) -{ - s32 offset = 0; - struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; - int rc; - - /* Bandwidth */ - channel->bandwidth = ((struct drxj_data *) demod->my_ext_attr)->curr_bandwidth; - - switch (standard) { - case DRX_STANDARD_NTSC: - case DRX_STANDARD_PAL_SECAM_BG: - case DRX_STANDARD_PAL_SECAM_DK: - case DRX_STANDARD_PAL_SECAM_I: - case DRX_STANDARD_PAL_SECAM_L: - { - u16 measured_offset = 0; - - /* get measured frequency offset */ - rc = drxj_dap_read_reg16(dev_addr, ATV_TOP_CR_FREQ__A, &measured_offset, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - /* Signed 8 bit register => sign extension needed */ - if ((measured_offset & 0x0080) != 0) - measured_offset |= 0xFF80; - offset += - (s32) (((s16) measured_offset) * 10); - break; - } - case DRX_STANDARD_PAL_SECAM_LP: - { - u16 measured_offset = 0; - - /* get measured frequency offset */ - rc = drxj_dap_read_reg16(dev_addr, ATV_TOP_CR_FREQ__A, &measured_offset, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - /* Signed 8 bit register => sign extension needed */ - if ((measured_offset & 0x0080) != 0) - measured_offset |= 0xFF80; - offset -= - (s32) (((s16) measured_offset) * 10); - } - break; - case DRX_STANDARD_FM: - /* TODO: compute offset using AUD_DSP_RD_FM_DC_LEVEL_A__A and - AUD_DSP_RD_FM_DC_LEVEL_B__A. For now leave frequency as is. - */ - /* No bandwidth know for FM */ - channel->bandwidth = DRX_BANDWIDTH_UNKNOWN; - break; - default: - return -EIO; - } - - channel->frequency -= offset; - - return 0; -rw_error: - return -EIO; -} - -/* -------------------------------------------------------------------------- */ -/** -* \fn int get_atv_sig_strength() -* \brief Retrieve signal strength for ATV & FM. -* \param devmod Pointer to demodulator instance. -* \param sig_quality Pointer to signal strength data; range 0, .. , 100. -* \return int. -* \retval 0 sig_strength contains valid data. -* \retval -EIO Erroneous data, sig_strength equals 0. -* -* Taking into account: -* * digital gain -* * IF gain (not implemented yet, waiting for IF gain control by ucode) -* * RF gain -* -* All weights (digital, if, rf) must add up to 100. -* -* TODO: ? dynamically adapt weights in case RF and/or IF agc of drxj -* is not used ? -*/ -static int -get_atv_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength) -{ - struct i2c_device_addr *dev_addr = NULL; - struct drxj_data *ext_attr = NULL; - int rc; - - /* All weights must add up to 100 (%) - TODO: change weights when IF ctrl is available */ - u32 digital_weight = 50; /* 0 .. 100 */ - u32 rf_weight = 50; /* 0 .. 100 */ - u32 if_weight = 0; /* 0 .. 100 */ - - u16 digital_curr_gain = 0; - u32 digital_max_gain = 0; - u32 digital_min_gain = 0; - u16 rf_curr_gain = 0; - u32 rf_max_gain = 0x800; /* taken from ucode */ - u32 rf_min_gain = 0x7fff; - u16 if_curr_gain = 0; - u32 if_max_gain = 0x800; /* taken from ucode */ - u32 if_min_gain = 0x7fff; - - u32 digital_strength = 0; /* 0.. 100 */ - u32 rf_strength = 0; /* 0.. 100 */ - u32 if_strength = 0; /* 0.. 100 */ - - dev_addr = demod->my_i2c_dev_addr; - ext_attr = (struct drxj_data *) demod->my_ext_attr; - - *sig_strength = 0; - - switch (ext_attr->standard) { - case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_LP: /* fallthrough */ - case DRX_STANDARD_NTSC: - rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_ATV_VID_GAIN_HI__A, &digital_curr_gain, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - digital_max_gain = 22512; /* taken from ucode */ - digital_min_gain = 2400; /* taken from ucode */ - break; - case DRX_STANDARD_FM: - rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_ATV_SIF_GAIN__A, &digital_curr_gain, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - digital_max_gain = 0x4ff; /* taken from ucode */ - digital_min_gain = 0; /* taken from ucode */ - break; - default: - return -EIO; - break; - } - rc = drxj_dap_read_reg16(dev_addr, IQM_AF_AGC_RF__A, &rf_curr_gain, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_read_reg16(dev_addr, IQM_AF_AGC_IF__A, &if_curr_gain, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* clipping */ - if (digital_curr_gain >= digital_max_gain) - digital_curr_gain = (u16)digital_max_gain; - if (digital_curr_gain <= digital_min_gain) - digital_curr_gain = (u16)digital_min_gain; - if (if_curr_gain <= if_max_gain) - if_curr_gain = (u16)if_max_gain; - if (if_curr_gain >= if_min_gain) - if_curr_gain = (u16)if_min_gain; - if (rf_curr_gain <= rf_max_gain) - rf_curr_gain = (u16)rf_max_gain; - if (rf_curr_gain >= rf_min_gain) - rf_curr_gain = (u16)rf_min_gain; - - /* TODO: use SCU_RAM_ATV_RAGC_HR__A to shift max and min in case - of clipping at ADC */ - - /* Compute signal strength (in %) per "gain domain" */ - - /* Digital gain */ - /* TODO: ADC clipping not handled */ - digital_strength = (100 * (digital_max_gain - (u32) digital_curr_gain)) / - (digital_max_gain - digital_min_gain); - - /* TODO: IF gain not implemented yet in microcode, check after impl. */ - if_strength = (100 * ((u32) if_curr_gain - if_max_gain)) / - (if_min_gain - if_max_gain); - - /* Rf gain */ - /* TODO: ADC clipping not handled */ - rf_strength = (100 * ((u32) rf_curr_gain - rf_max_gain)) / - (rf_min_gain - rf_max_gain); - - /* Compute a weighted signal strength (in %) */ - *sig_strength = (u16) (digital_weight * digital_strength + - rf_weight * rf_strength + if_weight * if_strength); - *sig_strength /= 100; - - return 0; -rw_error: - return -EIO; -} - -/* -------------------------------------------------------------------------- */ -/** -* \fn int atv_sig_quality() -* \brief Retrieve signal quality indication for ATV. -* \param devmod Pointer to demodulator instance. -* \param sig_quality Pointer to signal quality structure. -* \return int. -* \retval 0 sig_quality contains valid data. -* \retval -EIO Erroneous data, sig_quality indicator equals 0. -* -* -*/ -static int -atv_sig_quality(struct drx_demod_instance *demod, struct drx_sig_quality *sig_quality) -{ - struct i2c_device_addr *dev_addr = NULL; - u16 quality_indicator = 0; - int rc; - - dev_addr = demod->my_i2c_dev_addr; - - /* defined values for fields not used */ - sig_quality->MER = 0; - sig_quality->pre_viterbi_ber = 0; - sig_quality->post_viterbi_ber = 0; - sig_quality->scale_factor_ber = 1; - sig_quality->packet_error = 0; - sig_quality->post_reed_solomon_ber = 0; - - /* - Mapping: - 0x000..0x080: strong signal => 80% .. 100% - 0x080..0x700: weak signal => 30% .. 80% - 0x700..0x7ff: no signal => 0% .. 30% - */ - - rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_ATV_CR_LOCK__A, &quality_indicator, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - quality_indicator &= SCU_RAM_ATV_CR_LOCK_CR_LOCK__M; - if (quality_indicator <= 0x80) { - sig_quality->indicator = - 80 + ((20 * (0x80 - quality_indicator)) / 0x80); - } else if (quality_indicator <= 0x700) - sig_quality->indicator = 30 + ((50 * (0x700 - quality_indicator)) / (0x700 - 0x81)); - else - sig_quality->indicator = (30 * (0x7FF - quality_indicator)) / (0x7FF - 0x701); - - return 0; -rw_error: - return -EIO; -} - -/*============================================================================*/ -/*== END ATV DATAPATH FUNCTIONS ==*/ -/*============================================================================*/ - -/*===========================================================================*/ -/*===========================================================================*/ -/*== AUDIO DATAPATH FUNCTIONS ==*/ -/*===========================================================================*/ -/*===========================================================================*/ - -/* -* \brief Power up AUD. -* \param demod instance of demodulator -* \return int. -* -*/ -static int power_up_aud(struct drx_demod_instance *demod, bool set_standard) -{ - enum drx_aud_standard aud_standard = DRX_AUD_STANDARD_AUTO; - struct i2c_device_addr *dev_addr = NULL; - int rc; - - dev_addr = demod->my_i2c_dev_addr; - - rc = drxj_dap_write_reg16(dev_addr, AUD_TOP_COMM_EXEC__A, AUD_TOP_COMM_EXEC_ACTIVE, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - /* setup TR interface: R/W mode, fifosize=8 */ - rc = drxj_dap_write_reg16(dev_addr, AUD_TOP_TR_MDE__A, 8, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, AUD_COMM_EXEC__A, AUD_COMM_EXEC_ACTIVE, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - if (set_standard) { - rc = aud_ctrl_set_standard(demod, &aud_standard); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - } - - return 0; -rw_error: - return -EIO; -} -#endif - -/*============================================================================*/ - -/** -* \brief Power up AUD. -* \param demod instance of demodulator -* \return int. -* -*/ -static int power_down_aud(struct drx_demod_instance *demod) -{ - struct i2c_device_addr *dev_addr = NULL; - struct drxj_data *ext_attr = NULL; - int rc; - - dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; - ext_attr = (struct drxj_data *) demod->my_ext_attr; - - rc = drxj_dap_write_reg16(dev_addr, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - ext_attr->aud_data.audio_is_active = false; - - return 0; -rw_error: - return -EIO; -} - -#if 0 -/*============================================================================*/ -/** -* \brief Get Modus data from audio RAM -* \param demod instance of demodulator -* \param pointer to modus -* \return int. -* -*/ -static int aud_get_modus(struct drx_demod_instance *demod, u16 *modus) -{ - struct i2c_device_addr *dev_addr = NULL; - struct drxj_data *ext_attr = NULL; - int rc; - - u16 r_modus = 0; - u16 r_modus_hi = 0; - u16 r_modus_lo = 0; - - if (modus == NULL) - return -EINVAL; - - dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; - ext_attr = (struct drxj_data *) demod->my_ext_attr; - - /* power up */ - if (ext_attr->aud_data.audio_is_active == false) { - rc = power_up_aud(demod, true); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - ext_attr->aud_data.audio_is_active = true; - } - - /* Modus register is combined in to RAM location */ - rc = drxj_dap_read_reg16(dev_addr, AUD_DEM_RAM_MODUS_HI__A, &r_modus_hi, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_read_reg16(dev_addr, AUD_DEM_RAM_MODUS_LO__A, &r_modus_lo, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - r_modus = ((r_modus_hi << 12) & AUD_DEM_RAM_MODUS_HI__M) - | (((r_modus_lo & AUD_DEM_RAM_MODUS_LO__M))); - - *modus = r_modus; - - return 0; -rw_error: - return -EIO; - -} - -/*============================================================================*/ -/** -* \brief Get audio RDS dat -* \param demod instance of demodulator -* \param pointer to struct drx_cfg_aud_rds * \return int. -* -*/ -static int -aud_ctrl_get_cfg_rds(struct drx_demod_instance *demod, struct drx_cfg_aud_rds *status) -{ - struct i2c_device_addr *addr = NULL; - struct drxj_data *ext_attr = NULL; - int rc; - - u16 r_rds_array_cnt_init = 0; - u16 r_rds_array_cnt_check = 0; - u16 r_rds_data = 0; - u16 rds_data_cnt = 0; - - addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; - ext_attr = (struct drxj_data *) demod->my_ext_attr; - - if (status == NULL) - return -EINVAL; - - /* power up */ - if (ext_attr->aud_data.audio_is_active == false) { - rc = power_up_aud(demod, true); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - ext_attr->aud_data.audio_is_active = true; - } - - status->valid = false; - - rc = drxj_dap_read_reg16(addr, AUD_DEM_RD_RDS_ARRAY_CNT__A, &r_rds_array_cnt_init, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - if (r_rds_array_cnt_init == - AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT_RDS_DATA_NOT_VALID) { - /* invalid data */ - return 0; - } - - if (ext_attr->aud_data.rds_data_counter == r_rds_array_cnt_init) { - /* no new data */ - return 0; - } - - /* RDS is detected, as long as FM radio is selected assume - RDS will be available */ - ext_attr->aud_data.rds_data_present = true; - - /* new data */ - /* read the data */ - for (rds_data_cnt = 0; rds_data_cnt < AUD_RDS_ARRAY_SIZE; rds_data_cnt++) { - rc = drxj_dap_read_reg16(addr, AUD_DEM_RD_RDS_DATA__A, &r_rds_data, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - status->data[rds_data_cnt] = r_rds_data; - } - - rc = drxj_dap_read_reg16(addr, AUD_DEM_RD_RDS_ARRAY_CNT__A, &r_rds_array_cnt_check, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - if (r_rds_array_cnt_check == r_rds_array_cnt_init) { - status->valid = true; - ext_attr->aud_data.rds_data_counter = r_rds_array_cnt_check; - } - - return 0; -rw_error: - return -EIO; -} - -/*============================================================================*/ -/** -* \brief Get the current audio carrier detection status -* \param demod instance of demodulator -* \param pointer to aud_ctrl_get_status -* \return int. -* -*/ -static int -aud_ctrl_get_carrier_detect_status(struct drx_demod_instance *demod, struct drx_aud_status *status) -{ - struct drxj_data *ext_attr = NULL; - struct i2c_device_addr *dev_addr = NULL; - int rc; - u16 r_data = 0; - - if (status == NULL) - return -EINVAL; - - dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; - ext_attr = (struct drxj_data *) demod->my_ext_attr; - - /* power up */ - if (ext_attr->aud_data.audio_is_active == false) { - rc = power_up_aud(demod, true); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - ext_attr->aud_data.audio_is_active = true; - } - - /* initialize the variables */ - status->carrier_a = false; - status->carrier_b = false; - status->nicam_status = DRX_AUD_NICAM_NOT_DETECTED; - status->sap = false; - status->stereo = false; - - /* read stereo sound mode indication */ - rc = drxj_dap_read_reg16(dev_addr, AUD_DEM_RD_STATUS__A, &r_data, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* carrier a detected */ - if ((r_data & AUD_DEM_RD_STATUS_STAT_CARR_A__M) == AUD_DEM_RD_STATUS_STAT_CARR_A_DETECTED) - status->carrier_a = true; - - /* carrier b detected */ - if ((r_data & AUD_DEM_RD_STATUS_STAT_CARR_B__M) == AUD_DEM_RD_STATUS_STAT_CARR_B_DETECTED) - status->carrier_b = true; - /* nicam detected */ - if ((r_data & AUD_DEM_RD_STATUS_STAT_NICAM__M) == - AUD_DEM_RD_STATUS_STAT_NICAM_NICAM_DETECTED) { - if ((r_data & AUD_DEM_RD_STATUS_BAD_NICAM__M) == AUD_DEM_RD_STATUS_BAD_NICAM_OK) - status->nicam_status = DRX_AUD_NICAM_DETECTED; - else - status->nicam_status = DRX_AUD_NICAM_BAD; - } - - /* audio mode bilingual or SAP detected */ - if ((r_data & AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__M) == AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP_SAP) - status->sap = true; - - /* stereo detected */ - if ((r_data & AUD_DEM_RD_STATUS_STAT_STEREO__M) == AUD_DEM_RD_STATUS_STAT_STEREO_STEREO) - status->stereo = true; - - return 0; -rw_error: - return -EIO; -} - -/*============================================================================*/ -/** -* \brief Get the current audio status parameters -* \param demod instance of demodulator -* \param pointer to aud_ctrl_get_status -* \return int. -* -*/ -static int -aud_ctrl_get_status(struct drx_demod_instance *demod, struct drx_aud_status *status) -{ - struct drxj_data *ext_attr = NULL; - struct i2c_device_addr *dev_addr = NULL; - struct drx_cfg_aud_rds rds = { false, {0} }; - int rc; - u16 r_data = 0; - - if (status == NULL) - return -EINVAL; - - dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; - ext_attr = (struct drxj_data *) demod->my_ext_attr; - - /* carrier detection */ - rc = aud_ctrl_get_carrier_detect_status(demod, status); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* rds data */ - status->rds = false; - rc = aud_ctrl_get_cfg_rds(demod, &rds); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - status->rds = ext_attr->aud_data.rds_data_present; - - /* fm_ident */ - rc = drxj_dap_read_reg16(dev_addr, AUD_DSP_RD_FM_IDENT_VALUE__A, &r_data, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - r_data >>= AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__B; - status->fm_ident = (s8) r_data; - - return 0; -rw_error: - return -EIO; -} - -/*============================================================================*/ -/** -* \brief Get the current volume settings -* \param demod instance of demodulator -* \param pointer to struct drx_cfg_aud_volume * \return int. -* -*/ -static int -aud_ctrl_get_cfg_volume(struct drx_demod_instance *demod, struct drx_cfg_aud_volume *volume) -{ - struct i2c_device_addr *dev_addr = NULL; - struct drxj_data *ext_attr = NULL; - int rc; - - u16 r_volume = 0; - u16 r_avc = 0; - u16 r_strength_left = 0; - u16 r_strength_right = 0; - - if (volume == NULL) - return -EINVAL; - - dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; - ext_attr = (struct drxj_data *) demod->my_ext_attr; - - /* power up */ - if (ext_attr->aud_data.audio_is_active == false) { - rc = power_up_aud(demod, true); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - ext_attr->aud_data.audio_is_active = true; - } - - /* volume */ - volume->mute = ext_attr->aud_data.volume.mute; - rc = drxj_dap_read_reg16(dev_addr, AUD_DSP_WR_VOLUME__A, &r_volume, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - if (r_volume == 0) { - volume->mute = true; - volume->volume = ext_attr->aud_data.volume.volume; - } else { - volume->mute = false; - volume->volume = ((r_volume & AUD_DSP_WR_VOLUME_VOL_MAIN__M) >> - AUD_DSP_WR_VOLUME_VOL_MAIN__B) - - AUD_VOLUME_ZERO_DB; - if (volume->volume < AUD_VOLUME_DB_MIN) - volume->volume = AUD_VOLUME_DB_MIN; - if (volume->volume > AUD_VOLUME_DB_MAX) - volume->volume = AUD_VOLUME_DB_MAX; - } - - /* automatic volume control */ - rc = drxj_dap_read_reg16(dev_addr, AUD_DSP_WR_AVC__A, &r_avc, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - if ((r_avc & AUD_DSP_WR_AVC_AVC_ON__M) == AUD_DSP_WR_AVC_AVC_ON_OFF) { - volume->avc_mode = DRX_AUD_AVC_OFF; - } else { - switch (r_avc & AUD_DSP_WR_AVC_AVC_DECAY__M) { - case AUD_DSP_WR_AVC_AVC_DECAY_20_MSEC: - volume->avc_mode = DRX_AUD_AVC_DECAYTIME_20MS; - break; - case AUD_DSP_WR_AVC_AVC_DECAY_8_SEC: - volume->avc_mode = DRX_AUD_AVC_DECAYTIME_8S; - break; - case AUD_DSP_WR_AVC_AVC_DECAY_4_SEC: - volume->avc_mode = DRX_AUD_AVC_DECAYTIME_4S; - break; - case AUD_DSP_WR_AVC_AVC_DECAY_2_SEC: - volume->avc_mode = DRX_AUD_AVC_DECAYTIME_2S; - break; - default: - return -EIO; - break; - } - } - - /* max attenuation */ - switch (r_avc & AUD_DSP_WR_AVC_AVC_MAX_ATT__M) { - case AUD_DSP_WR_AVC_AVC_MAX_ATT_12DB: - volume->avc_max_atten = DRX_AUD_AVC_MAX_ATTEN_12DB; - break; - case AUD_DSP_WR_AVC_AVC_MAX_ATT_18DB: - volume->avc_max_atten = DRX_AUD_AVC_MAX_ATTEN_18DB; - break; - case AUD_DSP_WR_AVC_AVC_MAX_ATT_24DB: - volume->avc_max_atten = DRX_AUD_AVC_MAX_ATTEN_24DB; - break; - default: - return -EIO; - break; - } - - /* max gain */ - switch (r_avc & AUD_DSP_WR_AVC_AVC_MAX_GAIN__M) { - case AUD_DSP_WR_AVC_AVC_MAX_GAIN_0DB: - volume->avc_max_gain = DRX_AUD_AVC_MAX_GAIN_0DB; - break; - case AUD_DSP_WR_AVC_AVC_MAX_GAIN_6DB: - volume->avc_max_gain = DRX_AUD_AVC_MAX_GAIN_6DB; - break; - case AUD_DSP_WR_AVC_AVC_MAX_GAIN_12DB: - volume->avc_max_gain = DRX_AUD_AVC_MAX_GAIN_12DB; - break; - default: - return -EIO; - break; - } - - /* reference level */ - volume->avc_ref_level = (u16) ((r_avc & AUD_DSP_WR_AVC_AVC_REF_LEV__M) >> - AUD_DSP_WR_AVC_AVC_REF_LEV__B); - - /* read qpeak registers and calculate strength of left and right carrier */ - /* quasi peaks formula: QP(dB) = 20 * log( AUD_DSP_RD_QPEAKx / Q(0dB) */ - /* Q(0dB) represents QP value of 0dB (hex value 0x4000) */ - /* left carrier */ - - /* QP vaues */ - /* left carrier */ - rc = drxj_dap_read_reg16(dev_addr, AUD_DSP_RD_QPEAK_L__A, &r_strength_left, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - volume->strength_left = (((s16) log1_times100(r_strength_left)) - - AUD_CARRIER_STRENGTH_QP_0DB_LOG10T100) / 5; - - /* right carrier */ - rc = drxj_dap_read_reg16(dev_addr, AUD_DSP_RD_QPEAK_R__A, &r_strength_right, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - volume->strength_right = (((s16) log1_times100(r_strength_right)) - - AUD_CARRIER_STRENGTH_QP_0DB_LOG10T100) / 5; - - return 0; -rw_error: - return -EIO; -} - -/*============================================================================*/ -/** -* \brief Set the current volume settings -* \param demod instance of demodulator -* \param pointer to struct drx_cfg_aud_volume * \return int. -* -*/ -static int -aud_ctrl_set_cfg_volume(struct drx_demod_instance *demod, struct drx_cfg_aud_volume *volume) -{ - struct i2c_device_addr *dev_addr = NULL; - struct drxj_data *ext_attr = NULL; - int rc; - - u16 w_volume = 0; - u16 w_avc = 0; - - if (volume == NULL) - return -EINVAL; - - dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; - ext_attr = (struct drxj_data *) demod->my_ext_attr; - - /* power up */ - if (ext_attr->aud_data.audio_is_active == false) { - rc = power_up_aud(demod, true); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - ext_attr->aud_data.audio_is_active = true; - } - - /* volume */ - /* volume range from -60 to 12 (expressed in dB) */ - if ((volume->volume < AUD_VOLUME_DB_MIN) || - (volume->volume > AUD_VOLUME_DB_MAX)) - return -EINVAL; - - rc = drxj_dap_read_reg16(dev_addr, AUD_DSP_WR_VOLUME__A, &w_volume, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* clear the volume mask */ - w_volume &= (u16) ~AUD_DSP_WR_VOLUME_VOL_MAIN__M; - if (volume->mute == true) - w_volume |= (u16)(0); - else - w_volume |= (u16)((volume->volume + AUD_VOLUME_ZERO_DB) << AUD_DSP_WR_VOLUME_VOL_MAIN__B); - - rc = drxj_dap_write_reg16(dev_addr, AUD_DSP_WR_VOLUME__A, w_volume, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* automatic volume control */ - rc = drxj_dap_read_reg16(dev_addr, AUD_DSP_WR_AVC__A, &w_avc, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* clear masks that require writing */ - w_avc &= (u16) ~AUD_DSP_WR_AVC_AVC_ON__M; - w_avc &= (u16) ~AUD_DSP_WR_AVC_AVC_DECAY__M; - - if (volume->avc_mode == DRX_AUD_AVC_OFF) { - w_avc |= (AUD_DSP_WR_AVC_AVC_ON_OFF); - } else { - - w_avc |= (AUD_DSP_WR_AVC_AVC_ON_ON); - - /* avc decay */ - switch (volume->avc_mode) { - case DRX_AUD_AVC_DECAYTIME_20MS: - w_avc |= AUD_DSP_WR_AVC_AVC_DECAY_20_MSEC; - break; - case DRX_AUD_AVC_DECAYTIME_8S: - w_avc |= AUD_DSP_WR_AVC_AVC_DECAY_8_SEC; - break; - case DRX_AUD_AVC_DECAYTIME_4S: - w_avc |= AUD_DSP_WR_AVC_AVC_DECAY_4_SEC; - break; - case DRX_AUD_AVC_DECAYTIME_2S: - w_avc |= AUD_DSP_WR_AVC_AVC_DECAY_2_SEC; - break; - default: - return -EINVAL; - } - } - - /* max attenuation */ - w_avc &= (u16) ~AUD_DSP_WR_AVC_AVC_MAX_ATT__M; - switch (volume->avc_max_atten) { - case DRX_AUD_AVC_MAX_ATTEN_12DB: - w_avc |= AUD_DSP_WR_AVC_AVC_MAX_ATT_12DB; - break; - case DRX_AUD_AVC_MAX_ATTEN_18DB: - w_avc |= AUD_DSP_WR_AVC_AVC_MAX_ATT_18DB; - break; - case DRX_AUD_AVC_MAX_ATTEN_24DB: - w_avc |= AUD_DSP_WR_AVC_AVC_MAX_ATT_24DB; - break; - default: - return -EINVAL; - } - - /* max gain */ - w_avc &= (u16) ~AUD_DSP_WR_AVC_AVC_MAX_GAIN__M; - switch (volume->avc_max_gain) { - case DRX_AUD_AVC_MAX_GAIN_0DB: - w_avc |= AUD_DSP_WR_AVC_AVC_MAX_GAIN_0DB; - break; - case DRX_AUD_AVC_MAX_GAIN_6DB: - w_avc |= AUD_DSP_WR_AVC_AVC_MAX_GAIN_6DB; - break; - case DRX_AUD_AVC_MAX_GAIN_12DB: - w_avc |= AUD_DSP_WR_AVC_AVC_MAX_GAIN_12DB; - break; - default: - return -EINVAL; - } - - /* avc reference level */ - if (volume->avc_ref_level > AUD_MAX_AVC_REF_LEVEL) - return -EINVAL; - - w_avc &= (u16) ~AUD_DSP_WR_AVC_AVC_REF_LEV__M; - w_avc |= (u16) (volume->avc_ref_level << AUD_DSP_WR_AVC_AVC_REF_LEV__B); - - rc = drxj_dap_write_reg16(dev_addr, AUD_DSP_WR_AVC__A, w_avc, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* all done, store config in data structure */ - ext_attr->aud_data.volume = *volume; - - return 0; -rw_error: - return -EIO; -} - -/*============================================================================*/ -/** -* \brief Get the I2S settings -* \param demod instance of demodulator -* \param pointer to struct drx_cfg_i2s_output * \return int. -* -*/ -static int -aud_ctrl_get_cfg_output_i2s(struct drx_demod_instance *demod, struct drx_cfg_i2s_output *output) -{ - struct i2c_device_addr *dev_addr = NULL; - struct drxj_data *ext_attr = NULL; - int rc; - u16 w_i2s_config = 0; - u16 r_i2s_freq = 0; - - if (output == NULL) - return -EINVAL; - - dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; - ext_attr = (struct drxj_data *) demod->my_ext_attr; - - /* power up */ - if (ext_attr->aud_data.audio_is_active == false) { - rc = power_up_aud(demod, true); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - ext_attr->aud_data.audio_is_active = true; - } - - rc = drxj_dap_read_reg16(dev_addr, AUD_DEM_RAM_I2S_CONFIG2__A, &w_i2s_config, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_read_reg16(dev_addr, AUD_DSP_WR_I2S_OUT_FS__A, &r_i2s_freq, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* I2S mode */ - switch (w_i2s_config & AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__M) { - case AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST_MASTER: - output->mode = DRX_I2S_MODE_MASTER; - break; - case AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST_SLAVE: - output->mode = DRX_I2S_MODE_SLAVE; - break; - default: - return -EIO; - } - - /* I2S format */ - switch (w_i2s_config & AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__M) { - case AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE_DELAY: - output->format = DRX_I2S_FORMAT_WS_ADVANCED; - break; - case AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE_NO_DELAY: - output->format = DRX_I2S_FORMAT_WS_WITH_DATA; - break; - default: - return -EIO; - } - - /* I2S word length */ - switch (w_i2s_config & AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__M) { - case AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_16: - output->word_length = DRX_I2S_WORDLENGTH_16; - break; - case AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_32: - output->word_length = DRX_I2S_WORDLENGTH_32; - break; - default: - return -EIO; - } - - /* I2S polarity */ - switch (w_i2s_config & AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__M) { - case AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL_LEFT_HIGH: - output->polarity = DRX_I2S_POLARITY_LEFT; - break; - case AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL_LEFT_LOW: - output->polarity = DRX_I2S_POLARITY_RIGHT; - break; - default: - return -EIO; - } - - /* I2S output enabled */ - if ((w_i2s_config & AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__M) == AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_ENABLE) - output->output_enable = true; - else - output->output_enable = false; - - if (r_i2s_freq > 0) { - output->frequency = 6144UL * 48000 / r_i2s_freq; - if (output->word_length == DRX_I2S_WORDLENGTH_16) - output->frequency *= 2; - } else { - output->frequency = AUD_I2S_FREQUENCY_MAX; - } - - return 0; -rw_error: - return -EIO; -} - -/*============================================================================*/ -/** -* \brief Set the I2S settings -* \param demod instance of demodulator -* \param pointer to struct drx_cfg_i2s_output * \return int. -* -*/ -static int -aud_ctrl_set_cfg_output_i2s(struct drx_demod_instance *demod, struct drx_cfg_i2s_output *output) -{ - struct i2c_device_addr *dev_addr = NULL; - struct drxj_data *ext_attr = NULL; - int rc; - u16 w_i2s_config = 0; - u16 w_i2s_pads_data_da = 0; - u16 w_i2s_pads_data_cl = 0; - u16 w_i2s_pads_data_ws = 0; - u32 w_i2s_freq = 0; - - if (output == NULL) - return -EINVAL; - - dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; - ext_attr = (struct drxj_data *) demod->my_ext_attr; - - /* power up */ - if (ext_attr->aud_data.audio_is_active == false) { - rc = power_up_aud(demod, true); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - ext_attr->aud_data.audio_is_active = true; - } - - rc = drxj_dap_read_reg16(dev_addr, AUD_DEM_RAM_I2S_CONFIG2__A, &w_i2s_config, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* I2S mode */ - w_i2s_config &= (u16) ~AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__M; - - switch (output->mode) { - case DRX_I2S_MODE_MASTER: - w_i2s_config |= AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST_MASTER; - break; - case DRX_I2S_MODE_SLAVE: - w_i2s_config |= AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST_SLAVE; - break; - default: - return -EINVAL; - } - - /* I2S format */ - w_i2s_config &= (u16) ~AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__M; - - switch (output->format) { - case DRX_I2S_FORMAT_WS_ADVANCED: - w_i2s_config |= AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE_DELAY; - break; - case DRX_I2S_FORMAT_WS_WITH_DATA: - w_i2s_config |= AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE_NO_DELAY; - break; - default: - return -EINVAL; - } - - /* I2S word length */ - w_i2s_config &= (u16) ~AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__M; - - switch (output->word_length) { - case DRX_I2S_WORDLENGTH_16: - w_i2s_config |= AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_16; - break; - case DRX_I2S_WORDLENGTH_32: - w_i2s_config |= AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_32; - break; - default: - return -EINVAL; - } - - /* I2S polarity */ - w_i2s_config &= (u16) ~AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__M; - switch (output->polarity) { - case DRX_I2S_POLARITY_LEFT: - w_i2s_config |= AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL_LEFT_HIGH; - break; - case DRX_I2S_POLARITY_RIGHT: - w_i2s_config |= AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL_LEFT_LOW; - break; - default: - return -EINVAL; - } - - /* I2S output enabled */ - w_i2s_config &= (u16) ~AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__M; - if (output->output_enable == true) - w_i2s_config |= AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_ENABLE; - else - w_i2s_config |= AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_DISABLE; - - /* - I2S frequency - - w_i2s_freq = 6144 * 48000 * nrbits / ( 32 * frequency ) - - 16bit: 6144 * 48000 / ( 2 * freq ) = ( 6144 * 48000 / freq ) / 2 - 32bit: 6144 * 48000 / freq = ( 6144 * 48000 / freq ) - */ - if ((output->frequency > AUD_I2S_FREQUENCY_MAX) || - output->frequency < AUD_I2S_FREQUENCY_MIN) { - return -EINVAL; - } - - w_i2s_freq = (6144UL * 48000UL) + (output->frequency >> 1); - w_i2s_freq /= output->frequency; - - if (output->word_length == DRX_I2S_WORDLENGTH_16) - w_i2s_freq *= 2; - - rc = drxj_dap_write_reg16(dev_addr, AUD_DEM_WR_I2S_CONFIG2__A, w_i2s_config, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, AUD_DSP_WR_I2S_OUT_FS__A, (u16)w_i2s_freq, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* configure I2S output pads for master or slave mode */ - rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - if (output->mode == DRX_I2S_MODE_MASTER) { - w_i2s_pads_data_da = SIO_PDR_I2S_DA_CFG_MODE__MASTER | - SIO_PDR_I2S_DA_CFG_DRIVE__MASTER; - w_i2s_pads_data_cl = SIO_PDR_I2S_CL_CFG_MODE__MASTER | - SIO_PDR_I2S_CL_CFG_DRIVE__MASTER; - w_i2s_pads_data_ws = SIO_PDR_I2S_WS_CFG_MODE__MASTER | - SIO_PDR_I2S_WS_CFG_DRIVE__MASTER; - } else { - w_i2s_pads_data_da = SIO_PDR_I2S_DA_CFG_MODE__SLAVE | - SIO_PDR_I2S_DA_CFG_DRIVE__SLAVE; - w_i2s_pads_data_cl = SIO_PDR_I2S_CL_CFG_MODE__SLAVE | - SIO_PDR_I2S_CL_CFG_DRIVE__SLAVE; - w_i2s_pads_data_ws = SIO_PDR_I2S_WS_CFG_MODE__SLAVE | - SIO_PDR_I2S_WS_CFG_DRIVE__SLAVE; - } - - rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_I2S_DA_CFG__A, w_i2s_pads_data_da, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_I2S_CL_CFG__A, w_i2s_pads_data_cl, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_I2S_WS_CFG__A, w_i2s_pads_data_ws, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* all done, store config in data structure */ - ext_attr->aud_data.i2sdata = *output; - - return 0; -rw_error: - return -EIO; -} - -/*============================================================================*/ -/** -* \brief Get the Automatic Standard Select (ASS) -* and Automatic Sound Change (ASC) -* \param demod instance of demodulator -* \param pointer to pDRXAudAutoSound_t -* \return int. -* -*/ -static int -aud_ctrl_get_cfg_auto_sound(struct drx_demod_instance *demod, - enum drx_cfg_aud_auto_sound *auto_sound) -{ - struct drxj_data *ext_attr = NULL; - int rc; - u16 r_modus = 0; - - if (auto_sound == NULL) - return -EINVAL; - - ext_attr = (struct drxj_data *) demod->my_ext_attr; - - /* power up */ - if (ext_attr->aud_data.audio_is_active == false) { - rc = power_up_aud(demod, true); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - ext_attr->aud_data.audio_is_active = true; - } - - rc = aud_get_modus(demod, &r_modus); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - switch (r_modus & (AUD_DEM_WR_MODUS_MOD_ASS__M | - AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__M)) { - case AUD_DEM_WR_MODUS_MOD_ASS_OFF | AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_DISABLED: - case AUD_DEM_WR_MODUS_MOD_ASS_OFF | AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_ENABLED: - *auto_sound = - DRX_AUD_AUTO_SOUND_OFF; - break; - case AUD_DEM_WR_MODUS_MOD_ASS_ON | AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_ENABLED: - *auto_sound = - DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON; - break; - case AUD_DEM_WR_MODUS_MOD_ASS_ON | AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_DISABLED: - *auto_sound = - DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_OFF; - break; - default: - return -EIO; - } - - return 0; -rw_error: - return -EIO; -} - -/*============================================================================*/ -/** -* \brief Set the Automatic Standard Select (ASS) -* and Automatic Sound Change (ASC) -* \param demod instance of demodulator -* \param pointer to pDRXAudAutoSound_t -* \return int. -* -*/ -static int -aud_ctr_setl_cfg_auto_sound(struct drx_demod_instance *demod, - enum drx_cfg_aud_auto_sound *auto_sound) -{ - struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; - struct drxj_data *ext_attr = (struct drxj_data *) NULL; - int rc; - u16 r_modus = 0; - u16 w_modus = 0; - - if (auto_sound == NULL) - return -EINVAL; - - dev_addr = demod->my_i2c_dev_addr; - ext_attr = (struct drxj_data *) demod->my_ext_attr; - - /* power up */ - if (ext_attr->aud_data.audio_is_active == false) { - rc = power_up_aud(demod, true); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - ext_attr->aud_data.audio_is_active = true; - } - - rc = aud_get_modus(demod, &r_modus); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - w_modus = r_modus; - /* clear ASS & ASC bits */ - w_modus &= (u16) ~AUD_DEM_WR_MODUS_MOD_ASS__M; - w_modus &= (u16) ~AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__M; - - switch (*auto_sound) { - case DRX_AUD_AUTO_SOUND_OFF: - w_modus |= AUD_DEM_WR_MODUS_MOD_ASS_OFF; - w_modus |= AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_DISABLED; - break; - case DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON: - w_modus |= AUD_DEM_WR_MODUS_MOD_ASS_ON; - w_modus |= AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_ENABLED; - break; - case DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_OFF: - w_modus |= AUD_DEM_WR_MODUS_MOD_ASS_ON; - w_modus |= AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_DISABLED; - break; - default: - return -EINVAL; - } - - if (w_modus != r_modus) { - rc = drxj_dap_write_reg16(dev_addr, AUD_DEM_WR_MODUS__A, w_modus, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - } - /* copy to data structure */ - ext_attr->aud_data.auto_sound = *auto_sound; - - return 0; -rw_error: - return -EIO; -} - -/*============================================================================*/ -/** -* \brief Get the Automatic Standard Select thresholds -* \param demod instance of demodulator -* \param pointer to pDRXAudASSThres_t -* \return int. -* -*/ -static int -aud_ctrl_get_cfg_ass_thres(struct drx_demod_instance *demod, struct drx_cfg_aud_ass_thres *thres) -{ - struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; - struct drxj_data *ext_attr = (struct drxj_data *) NULL; - int rc; - u16 thres_a2 = 0; - u16 thres_btsc = 0; - u16 thres_nicam = 0; - - if (thres == NULL) - return -EINVAL; - - dev_addr = demod->my_i2c_dev_addr; - ext_attr = (struct drxj_data *) demod->my_ext_attr; - - /* power up */ - if (ext_attr->aud_data.audio_is_active == false) { - rc = power_up_aud(demod, true); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - ext_attr->aud_data.audio_is_active = true; - } - - rc = drxj_dap_read_reg16(dev_addr, AUD_DEM_RAM_A2_THRSHLD__A, &thres_a2, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_read_reg16(dev_addr, AUD_DEM_RAM_BTSC_THRSHLD__A, &thres_btsc, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_read_reg16(dev_addr, AUD_DEM_RAM_NICAM_THRSHLD__A, &thres_nicam, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - thres->a2 = thres_a2; - thres->btsc = thres_btsc; - thres->nicam = thres_nicam; - - return 0; -rw_error: - return -EIO; -} - -/*============================================================================*/ -/** -* \brief Get the Automatic Standard Select thresholds -* \param demod instance of demodulator -* \param pointer to pDRXAudASSThres_t -* \return int. -* -*/ -static int -aud_ctrl_set_cfg_ass_thres(struct drx_demod_instance *demod, struct drx_cfg_aud_ass_thres *thres) -{ - struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; - struct drxj_data *ext_attr = (struct drxj_data *) NULL; - int rc; - if (thres == NULL) - return -EINVAL; - - dev_addr = demod->my_i2c_dev_addr; - ext_attr = (struct drxj_data *) demod->my_ext_attr; - - /* power up */ - if (ext_attr->aud_data.audio_is_active == false) { - rc = power_up_aud(demod, true); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - ext_attr->aud_data.audio_is_active = true; - } - - rc = drxj_dap_write_reg16(dev_addr, AUD_DEM_WR_A2_THRSHLD__A, thres->a2, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, AUD_DEM_WR_BTSC_THRSHLD__A, thres->btsc, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, AUD_DEM_WR_NICAM_THRSHLD__A, thres->nicam, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* update DRXK data structure with hardware values */ - ext_attr->aud_data.ass_thresholds = *thres; - - return 0; -rw_error: - return -EIO; -} - -/*============================================================================*/ -/** -* \brief Get Audio Carrier settings -* \param demod instance of demodulator -* \param pointer to struct drx_aud_carrier ** \return int. -* -*/ -static int -aud_ctrl_get_cfg_carrier(struct drx_demod_instance *demod, struct drx_cfg_aud_carriers *carriers) -{ - struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; - struct drxj_data *ext_attr = (struct drxj_data *) NULL; - int rc; - u16 w_modus = 0; - - u16 dco_a_hi = 0; - u16 dco_a_lo = 0; - u16 dco_b_hi = 0; - u16 dco_b_lo = 0; - - u32 valA = 0; - u32 valB = 0; - - u16 dc_lvl_a = 0; - u16 dc_lvl_b = 0; - - u16 cm_thes_a = 0; - u16 cm_thes_b = 0; - - if (carriers == NULL) - return -EINVAL; - - dev_addr = demod->my_i2c_dev_addr; - ext_attr = (struct drxj_data *) demod->my_ext_attr; - - /* power up */ - if (ext_attr->aud_data.audio_is_active == false) { - rc = power_up_aud(demod, true); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - ext_attr->aud_data.audio_is_active = true; - } - - rc = aud_get_modus(demod, &w_modus); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* Behaviour of primary audio channel */ - switch (w_modus & (AUD_DEM_WR_MODUS_MOD_CM_A__M)) { - case AUD_DEM_WR_MODUS_MOD_CM_A_MUTE: - carriers->a.opt = DRX_NO_CARRIER_MUTE; - break; - case AUD_DEM_WR_MODUS_MOD_CM_A_NOISE: - carriers->a.opt = DRX_NO_CARRIER_NOISE; - break; - default: - return -EIO; - break; - } - - /* Behaviour of secondary audio channel */ - switch (w_modus & (AUD_DEM_WR_MODUS_MOD_CM_B__M)) { - case AUD_DEM_WR_MODUS_MOD_CM_B_MUTE: - carriers->b.opt = DRX_NO_CARRIER_MUTE; - break; - case AUD_DEM_WR_MODUS_MOD_CM_B_NOISE: - carriers->b.opt = DRX_NO_CARRIER_NOISE; - break; - default: - return -EIO; - break; - } - - /* frequency adjustment for primary & secondary audio channel */ - rc = drxj_dap_read_reg16(dev_addr, AUD_DEM_RAM_DCO_A_HI__A, &dco_a_hi, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_read_reg16(dev_addr, AUD_DEM_RAM_DCO_A_LO__A, &dco_a_lo, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_read_reg16(dev_addr, AUD_DEM_RAM_DCO_B_HI__A, &dco_b_hi, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_read_reg16(dev_addr, AUD_DEM_RAM_DCO_B_LO__A, &dco_b_lo, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - valA = (((u32) dco_a_hi) << 12) | ((u32) dco_a_lo & 0xFFF); - valB = (((u32) dco_b_hi) << 12) | ((u32) dco_b_lo & 0xFFF); - - /* Multiply by 20250 * 1>>24 ~= 2 / 1657 */ - carriers->a.dco = DRX_S24TODRXFREQ(valA) * 2L / 1657L; - carriers->b.dco = DRX_S24TODRXFREQ(valB) * 2L / 1657L; - - /* DC level of the incoming FM signal on the primary - & seconday sound channel */ - rc = drxj_dap_read_reg16(dev_addr, AUD_DSP_RD_FM_DC_LEVEL_A__A, &dc_lvl_a, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_read_reg16(dev_addr, AUD_DSP_RD_FM_DC_LEVEL_B__A, &dc_lvl_b, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* offset (kHz) = (dcLvl / 322) */ - carriers->a.shift = (DRX_U16TODRXFREQ(dc_lvl_a) / 322L); - carriers->b.shift = (DRX_U16TODRXFREQ(dc_lvl_b) / 322L); - - /* Carrier detetcion threshold for primary & secondary channel */ - rc = drxj_dap_read_reg16(dev_addr, AUD_DEM_RAM_CM_A_THRSHLD__A, &cm_thes_a, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_read_reg16(dev_addr, AUD_DEM_RAM_CM_B_THRSHLD__A, &cm_thes_b, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - carriers->a.thres = cm_thes_a; - carriers->b.thres = cm_thes_b; - - return 0; -rw_error: - return -EIO; -} - -/*============================================================================*/ -/** -* \brief Set Audio Carrier settings -* \param demod instance of demodulator -* \param pointer to struct drx_aud_carrier ** \return int. -* -*/ -static int -aud_ctrl_set_cfg_carrier(struct drx_demod_instance *demod, struct drx_cfg_aud_carriers *carriers) -{ - struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; - struct drxj_data *ext_attr = (struct drxj_data *) NULL; - int rc; - u16 w_modus = 0; - u16 r_modus = 0; - u16 dco_a_hi = 0; - u16 dco_a_lo = 0; - u16 dco_b_hi = 0; - u16 dco_b_lo = 0; - s32 valA = 0; - s32 valB = 0; - - if (carriers == NULL) - return -EINVAL; - - dev_addr = demod->my_i2c_dev_addr; - ext_attr = (struct drxj_data *) demod->my_ext_attr; - - /* power up */ - if (ext_attr->aud_data.audio_is_active == false) { - rc = power_up_aud(demod, true); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - ext_attr->aud_data.audio_is_active = true; - } - - rc = aud_get_modus(demod, &r_modus); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - w_modus = r_modus; - w_modus &= (u16) ~AUD_DEM_WR_MODUS_MOD_CM_A__M; - /* Behaviour of primary audio channel */ - switch (carriers->a.opt) { - case DRX_NO_CARRIER_MUTE: - w_modus |= AUD_DEM_WR_MODUS_MOD_CM_A_MUTE; - break; - case DRX_NO_CARRIER_NOISE: - w_modus |= AUD_DEM_WR_MODUS_MOD_CM_A_NOISE; - break; - default: - return -EINVAL; - break; - } - - /* Behaviour of secondary audio channel */ - w_modus &= (u16) ~AUD_DEM_WR_MODUS_MOD_CM_B__M; - switch (carriers->b.opt) { - case DRX_NO_CARRIER_MUTE: - w_modus |= AUD_DEM_WR_MODUS_MOD_CM_B_MUTE; - break; - case DRX_NO_CARRIER_NOISE: - w_modus |= AUD_DEM_WR_MODUS_MOD_CM_B_NOISE; - break; - default: - return -EINVAL; - break; - } - - /* now update the modus register */ - if (w_modus != r_modus) { - rc = drxj_dap_write_reg16(dev_addr, AUD_DEM_WR_MODUS__A, w_modus, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - } - - /* frequency adjustment for primary & secondary audio channel */ - valA = (s32) ((carriers->a.dco) * 1657L / 2); - valB = (s32) ((carriers->b.dco) * 1657L / 2); - - dco_a_hi = (u16) ((valA >> 12) & 0xFFF); - dco_a_lo = (u16) (valA & 0xFFF); - dco_b_hi = (u16) ((valB >> 12) & 0xFFF); - dco_b_lo = (u16) (valB & 0xFFF); - - rc = drxj_dap_write_reg16(dev_addr, AUD_DEM_WR_DCO_A_HI__A, dco_a_hi, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, AUD_DEM_WR_DCO_A_LO__A, dco_a_lo, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, AUD_DEM_WR_DCO_B_HI__A, dco_b_hi, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, AUD_DEM_WR_DCO_B_LO__A, dco_b_lo, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* Carrier detetcion threshold for primary & secondary channel */ - rc = drxj_dap_write_reg16(dev_addr, AUD_DEM_WR_CM_A_THRSHLD__A, carriers->a.thres, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, AUD_DEM_WR_CM_B_THRSHLD__A, carriers->b.thres, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* update DRXK data structure */ - ext_attr->aud_data.carriers = *carriers; - - return 0; -rw_error: - return -EIO; -} - -/*============================================================================*/ -/** -* \brief Get I2S Source, I2S matrix and FM matrix -* \param demod instance of demodulator -* \param pointer to pDRXAudmixer_t -* \return int. -* -*/ -static int -aud_ctrl_get_cfg_mixer(struct drx_demod_instance *demod, struct drx_cfg_aud_mixer *mixer) -{ - struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; - struct drxj_data *ext_attr = (struct drxj_data *) NULL; - int rc; - u16 src_i2s_matr = 0; - u16 fm_matr = 0; - - if (mixer == NULL) - return -EINVAL; - - dev_addr = demod->my_i2c_dev_addr; - ext_attr = (struct drxj_data *) demod->my_ext_attr; - - /* power up */ - if (ext_attr->aud_data.audio_is_active == false) { - rc = power_up_aud(demod, true); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - ext_attr->aud_data.audio_is_active = true; - } - - /* Source Selctor */ - rc = drxj_dap_read_reg16(dev_addr, AUD_DSP_WR_SRC_I2S_MATR__A, &src_i2s_matr, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - switch (src_i2s_matr & AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__M) { - case AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_MONO: - mixer->source_i2s = DRX_AUD_SRC_MONO; - break; - case AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_AB: - mixer->source_i2s = DRX_AUD_SRC_STEREO_OR_AB; - break; - case AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_A: - mixer->source_i2s = DRX_AUD_SRC_STEREO_OR_A; - break; - case AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_B: - mixer->source_i2s = DRX_AUD_SRC_STEREO_OR_B; - break; - default: - return -EIO; - } - - /* Matrix */ - switch (src_i2s_matr & AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__M) { - case AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_MONO: - mixer->matrix_i2s = DRX_AUD_I2S_MATRIX_MONO; - break; - case AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_STEREO: - mixer->matrix_i2s = DRX_AUD_I2S_MATRIX_STEREO; - break; - case AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_SOUND_A: - mixer->matrix_i2s = DRX_AUD_I2S_MATRIX_A_MONO; - break; - case AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_SOUND_B: - mixer->matrix_i2s = DRX_AUD_I2S_MATRIX_B_MONO; - break; - default: - return -EIO; - } - - /* FM Matrix */ - rc = drxj_dap_read_reg16(dev_addr, AUD_DEM_WR_FM_MATRIX__A, &fm_matr, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - switch (fm_matr & AUD_DEM_WR_FM_MATRIX__M) { - case AUD_DEM_WR_FM_MATRIX_NO_MATRIX: - mixer->matrix_fm = DRX_AUD_FM_MATRIX_NO_MATRIX; - break; - case AUD_DEM_WR_FM_MATRIX_GERMAN_MATRIX: - mixer->matrix_fm = DRX_AUD_FM_MATRIX_GERMAN; - break; - case AUD_DEM_WR_FM_MATRIX_KOREAN_MATRIX: - mixer->matrix_fm = DRX_AUD_FM_MATRIX_KOREAN; - break; - case AUD_DEM_WR_FM_MATRIX_SOUND_A: - mixer->matrix_fm = DRX_AUD_FM_MATRIX_SOUND_A; - break; - case AUD_DEM_WR_FM_MATRIX_SOUND_B: - mixer->matrix_fm = DRX_AUD_FM_MATRIX_SOUND_B; - break; - default: - return -EIO; - } - - return 0; -rw_error: - return -EIO; -} - -/*============================================================================*/ -/** -* \brief Set I2S Source, I2S matrix and FM matrix -* \param demod instance of demodulator -* \param pointer to DRXAudmixer_t -* \return int. -* -*/ -static int -aud_ctrl_set_cfg_mixer(struct drx_demod_instance *demod, struct drx_cfg_aud_mixer *mixer) -{ - struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; - struct drxj_data *ext_attr = (struct drxj_data *) NULL; - int rc; - u16 src_i2s_matr = 0; - u16 fm_matr = 0; - - if (mixer == NULL) - return -EINVAL; - - dev_addr = demod->my_i2c_dev_addr; - ext_attr = (struct drxj_data *) demod->my_ext_attr; - - /* power up */ - if (ext_attr->aud_data.audio_is_active == false) { - rc = power_up_aud(demod, true); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - ext_attr->aud_data.audio_is_active = true; - } - - /* Source Selctor */ - rc = drxj_dap_read_reg16(dev_addr, AUD_DSP_WR_SRC_I2S_MATR__A, &src_i2s_matr, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - src_i2s_matr &= (u16) ~AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__M; - - switch (mixer->source_i2s) { - case DRX_AUD_SRC_MONO: - src_i2s_matr |= AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_MONO; - break; - case DRX_AUD_SRC_STEREO_OR_AB: - src_i2s_matr |= AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_AB; - break; - case DRX_AUD_SRC_STEREO_OR_A: - src_i2s_matr |= AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_A; - break; - case DRX_AUD_SRC_STEREO_OR_B: - src_i2s_matr |= AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_B; - break; - default: - return -EINVAL; - } - - /* Matrix */ - src_i2s_matr &= (u16) ~AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__M; - switch (mixer->matrix_i2s) { - case DRX_AUD_I2S_MATRIX_MONO: - src_i2s_matr |= AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_MONO; - break; - case DRX_AUD_I2S_MATRIX_STEREO: - src_i2s_matr |= AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_STEREO; - break; - case DRX_AUD_I2S_MATRIX_A_MONO: - src_i2s_matr |= AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_SOUND_A; - break; - case DRX_AUD_I2S_MATRIX_B_MONO: - src_i2s_matr |= AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_SOUND_B; - break; - default: - return -EINVAL; - } - /* write the result */ - rc = drxj_dap_write_reg16(dev_addr, AUD_DSP_WR_SRC_I2S_MATR__A, src_i2s_matr, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* FM Matrix */ - rc = drxj_dap_read_reg16(dev_addr, AUD_DEM_WR_FM_MATRIX__A, &fm_matr, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - fm_matr &= (u16) ~AUD_DEM_WR_FM_MATRIX__M; - switch (mixer->matrix_fm) { - case DRX_AUD_FM_MATRIX_NO_MATRIX: - fm_matr |= AUD_DEM_WR_FM_MATRIX_NO_MATRIX; - break; - case DRX_AUD_FM_MATRIX_GERMAN: - fm_matr |= AUD_DEM_WR_FM_MATRIX_GERMAN_MATRIX; - break; - case DRX_AUD_FM_MATRIX_KOREAN: - fm_matr |= AUD_DEM_WR_FM_MATRIX_KOREAN_MATRIX; - break; - case DRX_AUD_FM_MATRIX_SOUND_A: - fm_matr |= AUD_DEM_WR_FM_MATRIX_SOUND_A; - break; - case DRX_AUD_FM_MATRIX_SOUND_B: - fm_matr |= AUD_DEM_WR_FM_MATRIX_SOUND_B; - break; - default: - return -EINVAL; - } - - /* Only write if ASS is off */ - if (ext_attr->aud_data.auto_sound == DRX_AUD_AUTO_SOUND_OFF) { - rc = drxj_dap_write_reg16(dev_addr, AUD_DEM_WR_FM_MATRIX__A, fm_matr, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - } - - /* update the data structure with hardware state */ - ext_attr->aud_data.mixer = *mixer; - - return 0; -rw_error: - return -EIO; -} - -/*============================================================================*/ -/** -* \brief Set AV Sync settings -* \param demod instance of demodulator -* \param pointer to DRXICfgAVSync_t -* \return int. -* -*/ -static int -aud_ctrl_set_cfg_av_sync(struct drx_demod_instance *demod, enum drx_cfg_aud_av_sync *av_sync) -{ - struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; - struct drxj_data *ext_attr = (struct drxj_data *) NULL; - int rc; - u16 w_aud_vid_sync = 0; - - if (av_sync == NULL) - return -EINVAL; - - dev_addr = demod->my_i2c_dev_addr; - ext_attr = (struct drxj_data *) demod->my_ext_attr; - - /* power up */ - if (ext_attr->aud_data.audio_is_active == false) { - rc = power_up_aud(demod, true); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - ext_attr->aud_data.audio_is_active = true; - } - - /* audio/video synchronisation */ - rc = drxj_dap_read_reg16(dev_addr, AUD_DSP_WR_AV_SYNC__A, &w_aud_vid_sync, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - w_aud_vid_sync &= (u16) ~AUD_DSP_WR_AV_SYNC_AV_ON__M; - - if (*av_sync == DRX_AUD_AVSYNC_OFF) - w_aud_vid_sync |= AUD_DSP_WR_AV_SYNC_AV_ON_DISABLE; - else - w_aud_vid_sync |= AUD_DSP_WR_AV_SYNC_AV_ON_ENABLE; - - w_aud_vid_sync &= (u16) ~AUD_DSP_WR_AV_SYNC_AV_STD_SEL__M; - - switch (*av_sync) { - case DRX_AUD_AVSYNC_NTSC: - w_aud_vid_sync |= AUD_DSP_WR_AV_SYNC_AV_STD_SEL_NTSC; - break; - case DRX_AUD_AVSYNC_MONOCHROME: - w_aud_vid_sync |= AUD_DSP_WR_AV_SYNC_AV_STD_SEL_MONOCHROME; - break; - case DRX_AUD_AVSYNC_PAL_SECAM: - w_aud_vid_sync |= AUD_DSP_WR_AV_SYNC_AV_STD_SEL_PAL_SECAM; - break; - case DRX_AUD_AVSYNC_OFF: - /* OK */ - break; - default: - return -EINVAL; - } - - rc = drxj_dap_write_reg16(dev_addr, AUD_DSP_WR_AV_SYNC__A, w_aud_vid_sync, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - return 0; -rw_error: - return -EIO; -} - -/*============================================================================*/ -/** -* \brief Get AV Sync settings -* \param demod instance of demodulator -* \param pointer to DRXICfgAVSync_t -* \return int. -* -*/ -static int -aud_ctrl_get_cfg_av_sync(struct drx_demod_instance *demod, enum drx_cfg_aud_av_sync *av_sync) -{ - struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; - struct drxj_data *ext_attr = (struct drxj_data *) NULL; - int rc; - u16 w_aud_vid_sync = 0; - - if (av_sync == NULL) - return -EINVAL; - - dev_addr = demod->my_i2c_dev_addr; - ext_attr = (struct drxj_data *) demod->my_ext_attr; - - /* power up */ - if (ext_attr->aud_data.audio_is_active == false) { - rc = power_up_aud(demod, true); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - ext_attr->aud_data.audio_is_active = true; - } - - /* audio/video synchronisation */ - rc = drxj_dap_read_reg16(dev_addr, AUD_DSP_WR_AV_SYNC__A, &w_aud_vid_sync, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - if ((w_aud_vid_sync & AUD_DSP_WR_AV_SYNC_AV_ON__M) == - AUD_DSP_WR_AV_SYNC_AV_ON_DISABLE) { - *av_sync = DRX_AUD_AVSYNC_OFF; - return 0; - } - - switch (w_aud_vid_sync & AUD_DSP_WR_AV_SYNC_AV_STD_SEL__M) { - case AUD_DSP_WR_AV_SYNC_AV_STD_SEL_NTSC: - *av_sync = DRX_AUD_AVSYNC_NTSC; - break; - case AUD_DSP_WR_AV_SYNC_AV_STD_SEL_MONOCHROME: - *av_sync = DRX_AUD_AVSYNC_MONOCHROME; - break; - case AUD_DSP_WR_AV_SYNC_AV_STD_SEL_PAL_SECAM: - *av_sync = DRX_AUD_AVSYNC_PAL_SECAM; - break; - default: - return -EIO; - } - - return 0; -rw_error: - return -EIO; -} - -/*============================================================================*/ -/** -* \brief Get deviation mode -* \param demod instance of demodulator -* \param pointer to enum drx_cfg_aud_deviation * \return int. -* -*/ -static int -aud_ctrl_get_cfg_dev(struct drx_demod_instance *demod, enum drx_cfg_aud_deviation *dev) -{ - u16 r_modus = 0; - int rc; - - if (dev == NULL) - return -EINVAL; - - rc = aud_get_modus(demod, &r_modus); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - switch (r_modus & AUD_DEM_WR_MODUS_MOD_HDEV_A__M) { - case AUD_DEM_WR_MODUS_MOD_HDEV_A_NORMAL: - *dev = DRX_AUD_DEVIATION_NORMAL; - break; - case AUD_DEM_WR_MODUS_MOD_HDEV_A_HIGH_DEVIATION: - *dev = DRX_AUD_DEVIATION_HIGH; - break; - default: - return -EIO; - } - - return 0; -rw_error: - return -EIO; -} - -/*============================================================================*/ -/** -* \brief Get deviation mode -* \param demod instance of demodulator -* \param pointer to enum drx_cfg_aud_deviation * \return int. -* -*/ -static int -aud_ctrl_set_cfg_dev(struct drx_demod_instance *demod, enum drx_cfg_aud_deviation *dev) -{ - struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; - struct drxj_data *ext_attr = (struct drxj_data *) NULL; - int rc; - u16 w_modus = 0; - u16 r_modus = 0; - - if (dev == NULL) - return -EINVAL; - - ext_attr = (struct drxj_data *) demod->my_ext_attr; - dev_addr = demod->my_i2c_dev_addr; - - rc = aud_get_modus(demod, &r_modus); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - w_modus = r_modus; - - w_modus &= (u16) ~AUD_DEM_WR_MODUS_MOD_HDEV_A__M; - - switch (*dev) { - case DRX_AUD_DEVIATION_NORMAL: - w_modus |= AUD_DEM_WR_MODUS_MOD_HDEV_A_NORMAL; - break; - case DRX_AUD_DEVIATION_HIGH: - w_modus |= AUD_DEM_WR_MODUS_MOD_HDEV_A_HIGH_DEVIATION; - break; - default: - return -EINVAL; - } - - /* now update the modus register */ - if (w_modus != r_modus) { - rc = drxj_dap_write_reg16(dev_addr, AUD_DEM_WR_MODUS__A, w_modus, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - } - /* store in drxk data struct */ - ext_attr->aud_data.deviation = *dev; - - return 0; -rw_error: - return -EIO; -} - -/*============================================================================*/ -/** -* \brief Get Prescaler settings -* \param demod instance of demodulator -* \param pointer to struct drx_cfg_aud_prescale * \return int. -* -*/ -static int -aud_ctrl_get_cfg_prescale(struct drx_demod_instance *demod, struct drx_cfg_aud_prescale *presc) -{ - struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; - struct drxj_data *ext_attr = (struct drxj_data *) NULL; - int rc; - u16 r_max_fm_deviation = 0; - u16 r_nicam_prescaler = 0; - - if (presc == NULL) - return -EINVAL; - - dev_addr = demod->my_i2c_dev_addr; - ext_attr = (struct drxj_data *) demod->my_ext_attr; - - /* power up */ - if (ext_attr->aud_data.audio_is_active == false) { - rc = power_up_aud(demod, true); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - ext_attr->aud_data.audio_is_active = true; - } - - /* read register data */ - rc = drxj_dap_read_reg16(dev_addr, AUD_DSP_WR_NICAM_PRESC__A, &r_nicam_prescaler, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_read_reg16(dev_addr, AUD_DSP_WR_FM_PRESC__A, &r_max_fm_deviation, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* calculate max FM deviation */ - r_max_fm_deviation >>= AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__B; - if (r_max_fm_deviation > 0) { - presc->fm_deviation = 3600UL + (r_max_fm_deviation >> 1); - presc->fm_deviation /= r_max_fm_deviation; - } else { - presc->fm_deviation = 380; /* kHz */ - } - - /* calculate NICAM gain from pre-scaler */ - /* - nicam_gain = 20 * ( log10( preScaler / 16) ) - = ( 100log10( preScaler ) - 100log10( 16 ) ) / 5 - - because log1_times100() cannot return negative numbers - = ( 100log10( 10 * preScaler ) - 100log10( 10 * 16) ) / 5 - - for 0.1dB resolution: - - nicam_gain = 200 * ( log10( preScaler / 16) ) - = 2 * ( 100log10( 10 * preScaler ) - 100log10( 10 * 16) ) - = ( 100log10( 10 * preScaler^2 ) - 100log10( 10 * 16^2 ) ) - - */ - r_nicam_prescaler >>= 8; - if (r_nicam_prescaler <= 1) - presc->nicam_gain = -241; - else - presc->nicam_gain = (s16)(((s32)(log1_times100(10 * r_nicam_prescaler * r_nicam_prescaler)) - (s32)(log1_times100(10 * 16 * 16)))); - - return 0; -rw_error: - return -EIO; -} - -/*============================================================================*/ -/** -* \brief Set Prescaler settings -* \param demod instance of demodulator -* \param pointer to struct drx_cfg_aud_prescale * \return int. -* -*/ -static int -aud_ctrl_set_cfg_prescale(struct drx_demod_instance *demod, struct drx_cfg_aud_prescale *presc) -{ - struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; - struct drxj_data *ext_attr = (struct drxj_data *) NULL; - int rc; - u16 w_max_fm_deviation = 0; - u16 nicam_prescaler; - - if (presc == NULL) - return -EINVAL; - - dev_addr = demod->my_i2c_dev_addr; - ext_attr = (struct drxj_data *) demod->my_ext_attr; - - /* power up */ - if (ext_attr->aud_data.audio_is_active == false) { - rc = power_up_aud(demod, true); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - ext_attr->aud_data.audio_is_active = true; - } - - /* setting of max FM deviation */ - w_max_fm_deviation = (u16) (frac(3600UL, presc->fm_deviation, 0)); - w_max_fm_deviation <<= AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__B; - if (w_max_fm_deviation >= AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_28_KHZ_FM_DEVIATION) - w_max_fm_deviation = AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_28_KHZ_FM_DEVIATION; - - /* NICAM Prescaler */ - if ((presc->nicam_gain >= -241) && (presc->nicam_gain <= 180)) { - /* calculation - - prescaler = 16 * 10^( gd_b / 20 ) - - minval of gd_b = -20*log( 16 ) = -24.1dB - - negative numbers not allowed for d_b2lin_times100, so - - prescaler = 16 * 10^( gd_b / 20 ) - = 10^( (gd_b / 20) + log10(16) ) - = 10^( (gd_b + 20log10(16)) / 20 ) - - in 0.1dB - - = 10^( G0.1dB + 200log10(16)) / 200 ) - - */ - nicam_prescaler = (u16) - ((d_b2lin_times100(presc->nicam_gain + 241UL) + 50UL) / 100UL); - - /* clip result */ - if (nicam_prescaler > 127) - nicam_prescaler = 127; - - /* shift before writing to register */ - nicam_prescaler <<= 8; - } else { - return -EINVAL; - } - /* end of setting NICAM Prescaler */ - - rc = drxj_dap_write_reg16(dev_addr, AUD_DSP_WR_NICAM_PRESC__A, nicam_prescaler, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, AUD_DSP_WR_FM_PRESC__A, w_max_fm_deviation, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - ext_attr->aud_data.prescale = *presc; - - return 0; -rw_error: - return -EIO; -} - -/*============================================================================*/ -/** -* \brief Beep -* \param demod instance of demodulator -* \param pointer to struct drx_aud_beep * \return int. -* -*/ -static int aud_ctrl_beep(struct drx_demod_instance *demod, struct drx_aud_beep *beep) -{ - struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; - struct drxj_data *ext_attr = (struct drxj_data *) NULL; - int rc; - u16 the_beep = 0; - u16 volume = 0; - u32 frequency = 0; - - if (beep == NULL) - return -EINVAL; - - dev_addr = demod->my_i2c_dev_addr; - ext_attr = (struct drxj_data *) demod->my_ext_attr; - - /* power up */ - if (ext_attr->aud_data.audio_is_active == false) { - rc = power_up_aud(demod, true); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - ext_attr->aud_data.audio_is_active = true; - } - - if ((beep->volume > 0) || (beep->volume < -127)) - return -EINVAL; - - if (beep->frequency > 3000) - return -EINVAL; - - volume = (u16) beep->volume + 127; - the_beep |= volume << AUD_DSP_WR_BEEPER_BEEP_VOLUME__B; - - frequency = ((u32) beep->frequency) * 23 / 500; - if (frequency > AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__M) - frequency = AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__M; - the_beep |= (u16) frequency; - - if (beep->mute == true) - the_beep = 0; - - rc = drxj_dap_write_reg16(dev_addr, AUD_DSP_WR_BEEPER__A, the_beep, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - return 0; -rw_error: - return -EIO; -} - -/*============================================================================*/ -/** -* \brief Set an audio standard -* \param demod instance of demodulator -* \param pointer to enum drx_aud_standard * \return int. -* -*/ -static int -aud_ctrl_set_standard(struct drx_demod_instance *demod, enum drx_aud_standard *standard) -{ - struct i2c_device_addr *dev_addr = NULL; - struct drxj_data *ext_attr = NULL; - enum drx_standard current_standard = DRX_STANDARD_UNKNOWN; - int rc; - u16 w_standard = 0; - u16 w_modus = 0; - u16 r_modus = 0; - - bool mute_buffer = false; - s16 volume_buffer = 0; - u16 w_volume = 0; - - if (standard == NULL) - return -EINVAL; - - dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; - ext_attr = (struct drxj_data *) demod->my_ext_attr; - - /* power up */ - if (ext_attr->aud_data.audio_is_active == false) { - rc = power_up_aud(demod, false); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - ext_attr->aud_data.audio_is_active = true; - } - - /* reset RDS data availability flag */ - ext_attr->aud_data.rds_data_present = false; - - /* we need to mute from here to avoid noise during standard switching */ - mute_buffer = ext_attr->aud_data.volume.mute; - volume_buffer = ext_attr->aud_data.volume.volume; - - ext_attr->aud_data.volume.mute = true; - /* restore data structure from DRX ExtAttr, call volume first to mute */ - rc = aud_ctrl_set_cfg_volume(demod, &ext_attr->aud_data.volume); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = aud_ctrl_set_cfg_carrier(demod, &ext_attr->aud_data.carriers); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = aud_ctrl_set_cfg_ass_thres(demod, &ext_attr->aud_data.ass_thresholds); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = aud_ctr_setl_cfg_auto_sound(demod, &ext_attr->aud_data.auto_sound); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = aud_ctrl_set_cfg_mixer(demod, &ext_attr->aud_data.mixer); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = aud_ctrl_set_cfg_av_sync(demod, &ext_attr->aud_data.av_sync); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = aud_ctrl_set_cfg_output_i2s(demod, &ext_attr->aud_data.i2sdata); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* get prescaler from presets */ - rc = aud_ctrl_set_cfg_prescale(demod, &ext_attr->aud_data.prescale); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - rc = aud_get_modus(demod, &r_modus); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - w_modus = r_modus; - - switch (*standard) { - case DRX_AUD_STANDARD_AUTO: - w_standard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_AUTO; - break; - case DRX_AUD_STANDARD_BTSC: - w_standard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_BTSC_STEREO; - if (ext_attr->aud_data.btsc_detect == DRX_BTSC_MONO_AND_SAP) - w_standard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_BTSC_SAP; - break; - case DRX_AUD_STANDARD_A2: - w_standard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_M_KOREA; - break; - case DRX_AUD_STANDARD_EIAJ: - w_standard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_EIA_J; - break; - case DRX_AUD_STANDARD_FM_STEREO: - w_standard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_FM_RADIO; - break; - case DRX_AUD_STANDARD_BG_FM: - w_standard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_BG_FM; - break; - case DRX_AUD_STANDARD_D_K1: - w_standard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K1; - break; - case DRX_AUD_STANDARD_D_K2: - w_standard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K2; - break; - case DRX_AUD_STANDARD_D_K3: - w_standard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K3; - break; - case DRX_AUD_STANDARD_BG_NICAM_FM: - w_standard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_BG_NICAM_FM; - break; - case DRX_AUD_STANDARD_L_NICAM_AM: - w_standard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_L_NICAM_AM; - break; - case DRX_AUD_STANDARD_I_NICAM_FM: - w_standard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_I_NICAM_FM; - break; - case DRX_AUD_STANDARD_D_K_NICAM_FM: - w_standard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K_NICAM_FM; - break; - case DRX_AUD_STANDARD_UNKNOWN: - w_standard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_AUTO; - break; - default: - return -EIO; - } - - if (*standard == DRX_AUD_STANDARD_AUTO) { - /* we need the current standard here */ - current_standard = ext_attr->standard; - - w_modus &= (u16) ~AUD_DEM_WR_MODUS_MOD_6_5MHZ__M; - - if ((current_standard == DRX_STANDARD_PAL_SECAM_L) || (current_standard == DRX_STANDARD_PAL_SECAM_LP)) - w_modus |= (AUD_DEM_WR_MODUS_MOD_6_5MHZ_SECAM); - else - w_modus |= (AUD_DEM_WR_MODUS_MOD_6_5MHZ_D_K); - - w_modus &= (u16) ~AUD_DEM_WR_MODUS_MOD_4_5MHZ__M; - if (current_standard == DRX_STANDARD_NTSC) - w_modus |= (AUD_DEM_WR_MODUS_MOD_4_5MHZ_M_BTSC); - else - w_modus |= (AUD_DEM_WR_MODUS_MOD_4_5MHZ_CHROMA); - - } - - w_modus &= (u16) ~AUD_DEM_WR_MODUS_MOD_FMRADIO__M; - - /* just get hardcoded deemphasis and activate here */ - if (ext_attr->aud_data.deemph == DRX_AUD_FM_DEEMPH_50US) - w_modus |= (AUD_DEM_WR_MODUS_MOD_FMRADIO_EU_50U); - else - w_modus |= (AUD_DEM_WR_MODUS_MOD_FMRADIO_US_75U); - - w_modus &= (u16) ~AUD_DEM_WR_MODUS_MOD_BTSC__M; - if (ext_attr->aud_data.btsc_detect == DRX_BTSC_STEREO) - w_modus |= (AUD_DEM_WR_MODUS_MOD_BTSC_BTSC_STEREO); - else - w_modus |= (AUD_DEM_WR_MODUS_MOD_BTSC_BTSC_SAP); - - if (w_modus != r_modus) { - rc = drxj_dap_write_reg16(dev_addr, AUD_DEM_WR_MODUS__A, w_modus, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - } - - rc = drxj_dap_write_reg16(dev_addr, AUD_DEM_WR_STANDARD_SEL__A, w_standard, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /**************************************************************************/ - /* NOT calling aud_ctrl_set_cfg_volume to avoid interfering standard */ - /* detection, need to keep things very minimal here, but keep audio */ - /* buffers intact */ - /**************************************************************************/ - ext_attr->aud_data.volume.mute = mute_buffer; - if (ext_attr->aud_data.volume.mute == false) { - w_volume |= (u16) ((volume_buffer + AUD_VOLUME_ZERO_DB) << - AUD_DSP_WR_VOLUME_VOL_MAIN__B); - rc = drxj_dap_write_reg16(dev_addr, AUD_DSP_WR_VOLUME__A, w_volume, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - } - - /* write standard selected */ - ext_attr->aud_data.audio_standard = *standard; - - return 0; -rw_error: - return -EIO; -} - -/*============================================================================*/ -/** -* \brief Get the current audio standard -* \param demod instance of demodulator -* \param pointer to enum drx_aud_standard * \return int. -* -*/ -static int -aud_ctrl_get_standard(struct drx_demod_instance *demod, enum drx_aud_standard *standard) -{ - struct i2c_device_addr *dev_addr = NULL; - struct drxj_data *ext_attr = NULL; - int rc; - u16 r_data = 0; - - if (standard == NULL) - return -EINVAL; - - ext_attr = (struct drxj_data *) demod->my_ext_attr; - dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; - - /* power up */ - if (ext_attr->aud_data.audio_is_active == false) { - rc = power_up_aud(demod, true); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - ext_attr->aud_data.audio_is_active = true; - } - - *standard = DRX_AUD_STANDARD_UNKNOWN; - - rc = drxj_dap_read_reg16(dev_addr, AUD_DEM_RD_STANDARD_RES__A, &r_data, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* return OK if the detection is not ready yet */ - if (r_data >= AUD_DEM_RD_STANDARD_RES_STD_RESULT_DETECTION_STILL_ACTIVE) { - *standard = DRX_AUD_STANDARD_NOT_READY; - return 0; - } - - /* detection done, return correct standard */ - switch (r_data) { - /* no standard detected */ - case AUD_DEM_RD_STANDARD_RES_STD_RESULT_NO_SOUND_STANDARD: - *standard = DRX_AUD_STANDARD_UNKNOWN; - break; - /* standard is KOREA(A2) */ - case AUD_DEM_RD_STANDARD_RES_STD_RESULT_NTSC_M_DUAL_CARRIER_FM: - *standard = DRX_AUD_STANDARD_A2; - break; - /* standard is EIA-J (Japan) */ - case AUD_DEM_RD_STANDARD_RES_STD_RESULT_NTSC_EIA_J: - *standard = DRX_AUD_STANDARD_EIAJ; - break; - /* standard is BTSC-stereo */ - case AUD_DEM_RD_STANDARD_RES_STD_RESULT_BTSC_STEREO: - *standard = DRX_AUD_STANDARD_BTSC; - break; - /* standard is BTSC-mono (SAP) */ - case AUD_DEM_RD_STANDARD_RES_STD_RESULT_BTSC_MONO_SAP: - *standard = DRX_AUD_STANDARD_BTSC; - break; - /* standard is FM radio */ - case AUD_DEM_RD_STANDARD_RES_STD_RESULT_FM_RADIO: - *standard = DRX_AUD_STANDARD_FM_STEREO; - break; - /* standard is BG FM */ - case AUD_DEM_RD_STANDARD_RES_STD_RESULT_B_G_DUAL_CARRIER_FM: - *standard = DRX_AUD_STANDARD_BG_FM; - break; - /* standard is DK-1 FM */ - case AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K1_DUAL_CARRIER_FM: - *standard = DRX_AUD_STANDARD_D_K1; - break; - /* standard is DK-2 FM */ - case AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K2_DUAL_CARRIER_FM: - *standard = DRX_AUD_STANDARD_D_K2; - break; - /* standard is DK-3 FM */ - case AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K3_DUAL_CARRIER_FM: - *standard = DRX_AUD_STANDARD_D_K3; - break; - /* standard is BG-NICAM FM */ - case AUD_DEM_RD_STANDARD_RES_STD_RESULT_B_G_NICAM_FM: - *standard = DRX_AUD_STANDARD_BG_NICAM_FM; - break; - /* standard is L-NICAM AM */ - case AUD_DEM_RD_STANDARD_RES_STD_RESULT_L_NICAM_AM: - *standard = DRX_AUD_STANDARD_L_NICAM_AM; - break; - /* standard is I-NICAM FM */ - case AUD_DEM_RD_STANDARD_RES_STD_RESULT_I_NICAM_FM: - *standard = DRX_AUD_STANDARD_I_NICAM_FM; - break; - /* standard is DK-NICAM FM */ - case AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K_NICAM_FM: - *standard = DRX_AUD_STANDARD_D_K_NICAM_FM; - break; - default: - *standard = DRX_AUD_STANDARD_UNKNOWN; - } - - return 0; -rw_error: - return -EIO; - -} - -/*============================================================================*/ -/** -* \brief Retreive lock status in case of FM standard -* \param demod instance of demodulator -* \param pointer to lock status -* \return int. -* -*/ -static int -fm_lock_status(struct drx_demod_instance *demod, enum drx_lock_status *lock_stat) -{ - struct drx_aud_status status; - int rc; - - /* Check detection of audio carriers */ - rc = aud_ctrl_get_carrier_detect_status(demod, &status); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* locked if either primary or secondary carrier is detected */ - if ((status.carrier_a == true) || (status.carrier_b == true)) - *lock_stat = DRX_LOCKED; - else - *lock_stat = DRX_NOT_LOCKED; - - return 0; - -rw_error: - return -EIO; -} - -/*============================================================================*/ -/** -* \brief retreive signal quality in case of FM standard -* \param demod instance of demodulator -* \param pointer to signal quality -* \return int. -* -* Only the quality indicator field is will be supplied. -* This will either be 0% or 100%, nothing in between. -* -*/ -static int -fm_sig_quality(struct drx_demod_instance *demod, struct drx_sig_quality *sig_quality) -{ - enum drx_lock_status lock_status = DRX_NOT_LOCKED; - int rc; - - rc = fm_lock_status(demod, &lock_status); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - if (lock_status == DRX_LOCKED) - sig_quality->indicator = 100; - else - sig_quality->indicator = 0; - - return 0; - -rw_error: - return -EIO; -} - -/*===========================================================================*/ -/*== END AUDIO DATAPATH FUNCTIONS ==*/ -/*===========================================================================*/ - -/*============================================================================*/ -/*============================================================================*/ -/*== OOB DATAPATH FUNCTIONS ==*/ -/*============================================================================*/ -/*============================================================================*/ -/** -* \fn int get_oob_lock_status () -* \brief Get OOB lock status. -* \param dev_addr I2C address - \ oob_lock OOB lock status. -* \return int. -* -* Gets OOB lock status -* -*/ -static int -get_oob_lock_status(struct drx_demod_instance *demod, - struct i2c_device_addr *dev_addr, enum drx_lock_status *oob_lock) -{ - struct drxjscu_cmd scu_cmd; - int rc; - u16 cmd_result[2]; - u16 oob_lock_state; - - *oob_lock = DRX_NOT_LOCKED; - - scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB | - SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK; - scu_cmd.result_len = 2; - scu_cmd.result = cmd_result; - scu_cmd.parameter_len = 0; - - rc = scu_command(dev_addr, &scu_cmd); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - if (scu_cmd.result[1] < 0x4000) { - /* 0x00 NOT LOCKED */ - *oob_lock = DRX_NOT_LOCKED; - } else if (scu_cmd.result[1] < 0x8000) { - /* 0x40 DEMOD LOCKED */ - *oob_lock = DRXJ_OOB_SYNC_LOCK; - } else if (scu_cmd.result[1] < 0xC000) { - /* 0x80 DEMOD + OOB LOCKED (system lock) */ - oob_lock_state = scu_cmd.result[1] & 0x00FF; - - if (oob_lock_state & 0x0008) - *oob_lock = DRXJ_OOB_SYNC_LOCK; - else if ((oob_lock_state & 0x0002) && (oob_lock_state & 0x0001)) - *oob_lock = DRXJ_OOB_AGC_LOCK; - } else { - /* 0xC0 NEVER LOCKED (system will never be able to lock to the signal) */ - *oob_lock = DRX_NEVER_LOCK; - } - - /* *oob_lock = scu_cmd.result[1]; */ - - return 0; -rw_error: - return -EIO; -} - -/** -* \fn int get_oob_symbol_rate_offset () -* \brief Get OOB Symbol rate offset. Unit is [ppm] -* \param dev_addr I2C address -* \ Symbol Rate Offset OOB parameter. -* \return int. -* -* Gets OOB frequency offset -* -*/ -static int -get_oob_symbol_rate_offset(struct i2c_device_addr *dev_addr, s32 *symbol_rate_offset) -{ -/* offset = -{(timing_offset/2^19)*(symbol_rate/12,656250MHz)}*10^6 [ppm] */ -/* offset = -{(timing_offset/2^19)*(symbol_rate/12656250)}*10^6 [ppm] */ -/* after reconfiguration: */ -/* offset = -{(timing_offset*symbol_rate)/(2^19*12656250)}*10^6 [ppm] */ -/* shift symbol rate left by 5 without lossing information */ -/* offset = -{(timing_offset*(symbol_rate * 2^-5))/(2^14*12656250)}*10^6 [ppm]*/ -/* shift 10^6 left by 6 without loosing information */ -/* offset = -{(timing_offset*(symbol_rate * 2^-5))/(2^8*12656250)}*15625 [ppm]*/ -/* trim 12656250/15625 = 810 */ -/* offset = -{(timing_offset*(symbol_rate * 2^-5))/(2^8*810)} [ppm] */ -/* offset = -[(symbol_rate * 2^-5)*(timing_offset)/(2^8)]/810 [ppm] */ - int rc; - s32 timing_offset = 0; - u32 unsigned_timing_offset = 0; - s32 division_factor = 810; - u16 data = 0; - u32 symbol_rate = 0; - bool negative = false; - - *symbol_rate_offset = 0; - /* read data rate */ - rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_ORX_RF_RX_DATA_RATE__A, &data, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - switch (data & SCU_RAM_ORX_RF_RX_DATA_RATE__M) { - case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC: - case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC: - case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC_ALT: - case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC_ALT: - symbol_rate = 1024000; /* bps */ - break; - case SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_REGSPEC: - case SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_INVSPEC: - symbol_rate = 772000; /* bps */ - break; - case SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_REGSPEC: - case SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_INVSPEC: - symbol_rate = 1544000; /* bps */ - break; - default: - return -EIO; - } - - rc = drxj_dap_read_reg16(dev_addr, ORX_CON_CTI_DTI_R__A, &data, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - /* convert data to positive and keep information about sign */ - if ((data & 0x8000) == 0x8000) { - if (data == 0x8000) - unsigned_timing_offset = 32768; - else - unsigned_timing_offset = 0x00007FFF & (u32) (-data); - negative = true; - } else - unsigned_timing_offset = (u32) data; - - symbol_rate = symbol_rate >> 5; - unsigned_timing_offset = (unsigned_timing_offset * symbol_rate); - unsigned_timing_offset = frac(unsigned_timing_offset, 256, FRAC_ROUND); - unsigned_timing_offset = frac(unsigned_timing_offset, - division_factor, FRAC_ROUND); - if (negative) - timing_offset = (s32) unsigned_timing_offset; - else - timing_offset = -(s32) unsigned_timing_offset; - - *symbol_rate_offset = timing_offset; - - return 0; -rw_error: - return -EIO; -} - -/** -* \fn int get_oob_freq_offset () -* \brief Get OOB lock status. -* \param dev_addr I2C address -* \ freq_offset OOB frequency offset. -* \return int. -* -* Gets OOB frequency offset -* -*/ -static int -get_oob_freq_offset(struct drx_demod_instance *demod, s32 *freq_offset) -{ - struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL); - struct i2c_device_addr *dev_addr = NULL; - int rc; - u16 data = 0; - u16 rot = 0; - u16 symbol_rate_reg = 0; - u32 symbol_rate = 0; - s32 coarse_freq_offset = 0; - s32 fine_freq_offset = 0; - s32 fine_sign = 1; - s32 coarse_sign = 1; - u32 data64hi = 0; - u32 data64lo = 0; - u32 temp_freq_offset = 0; - - /* check arguments */ - if ((demod == NULL) || (freq_offset == NULL)) - return -EINVAL; - - dev_addr = demod->my_i2c_dev_addr; - common_attr = (struct drx_common_attr *) demod->my_common_attr; - - *freq_offset = 0; - - /* read sign (spectrum inversion) */ - rc = drxj_dap_read_reg16(dev_addr, ORX_FWP_IQM_FRQ_W__A, &rot, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* read frequency offset */ - rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_ORX_FRQ_OFFSET__A, &data, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - /* find COARSE frequency offset */ - /* coarse_freq_offset = ( 25312500Hz*FRQ_OFFSET >> 21 ); */ - if (data & 0x8000) { - data = (0xffff - data + 1); - coarse_sign = -1; - } - mult32(data, (common_attr->sys_clock_freq * 1000) / 6, &data64hi, - &data64lo); - temp_freq_offset = (((data64lo >> 21) & 0x7ff) | (data64hi << 11)); - - /* get value in KHz */ - coarse_freq_offset = coarse_sign * frac(temp_freq_offset, 1000, FRAC_ROUND); /* KHz */ - /* read data rate */ - rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_ORX_RF_RX_DATA_RATE__A, &symbol_rate_reg, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - switch (symbol_rate_reg & SCU_RAM_ORX_RF_RX_DATA_RATE__M) { - case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC: - case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC: - case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC_ALT: - case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC_ALT: - symbol_rate = 1024000; - break; - case SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_REGSPEC: - case SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_INVSPEC: - symbol_rate = 772000; - break; - case SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_REGSPEC: - case SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_INVSPEC: - symbol_rate = 1544000; - break; - default: - return -EIO; - } - - /* find FINE frequency offset */ - /* fine_freq_offset = ( (CORRECTION_VALUE*symbol_rate) >> 18 ); */ - rc = drxj_dap_read_reg16(dev_addr, ORX_CON_CPH_FRQ_R__A, &data, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - /* at least 5 MSB are 0 so first divide with 2^5 without information loss */ - fine_freq_offset = (symbol_rate >> 5); - if (data & 0x8000) { - fine_freq_offset *= 0xffff - data + 1; /* Hz */ - fine_sign = -1; - } else { - fine_freq_offset *= data; /* Hz */ - } - /* Left to divide with 8192 (2^13) */ - fine_freq_offset = frac(fine_freq_offset, 8192, FRAC_ROUND); - /* and to divide with 1000 to get KHz */ - fine_freq_offset = fine_sign * frac(fine_freq_offset, 1000, FRAC_ROUND); /* KHz */ - - if ((rot & 0x8000) == 0x8000) - *freq_offset = -(coarse_freq_offset + fine_freq_offset); - else - *freq_offset = (coarse_freq_offset + fine_freq_offset); - - return 0; -rw_error: - return -EIO; -} - -/** -* \fn int get_oob_frequency () -* \brief Get OOB frequency (Unit:KHz). -* \param dev_addr I2C address -* \ frequency OOB frequency parameters. -* \return int. -* -* Gets OOB frequency -* -*/ -static int -get_oob_frequency(struct drx_demod_instance *demod, s32 *frequency) -{ - struct i2c_device_addr *dev_addr = NULL; - int rc; - u16 data = 0; - s32 freq_offset = 0; - s32 freq = 0; - - dev_addr = demod->my_i2c_dev_addr; - - *frequency = 0; /* KHz */ - - rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__A, &data, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - freq = (s32) ((s32) data * 50 + 50000L); - - rc = get_oob_freq_offset(demod, &freq_offset); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - *frequency = freq + freq_offset; - - return 0; -rw_error: - return -EIO; -} - -/** -* \fn int get_oobmer () -* \brief Get OOB MER. -* \param dev_addr I2C address - \ MER OOB parameter in dB. -* \return int. -* -* Gets OOB MER. Table for MER is in Programming guide. -* -*/ -static int get_oobmer(struct i2c_device_addr *dev_addr, u32 *mer) -{ - int rc; - u16 data = 0; - - *mer = 0; - /* READ MER */ - rc = drxj_dap_read_reg16(dev_addr, ORX_EQU_MER_MER_R__A, &data, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - switch (data) { - case 0: /* fall through */ - case 1: - *mer = 39; - break; - case 2: - *mer = 33; - break; - case 3: - *mer = 29; - break; - case 4: - *mer = 27; - break; - case 5: - *mer = 25; - break; - case 6: - *mer = 23; - break; - case 7: - *mer = 22; - break; - case 8: - *mer = 21; - break; - case 9: - *mer = 20; - break; - case 10: - *mer = 19; - break; - case 11: - *mer = 18; - break; - case 12: - *mer = 17; - break; - case 13: /* fall through */ - case 14: - *mer = 16; - break; - case 15: /* fall through */ - case 16: - *mer = 15; - break; - case 17: /* fall through */ - case 18: - *mer = 14; - break; - case 19: /* fall through */ - case 20: - *mer = 13; - break; - case 21: /* fall through */ - case 22: - *mer = 12; - break; - case 23: /* fall through */ - case 24: /* fall through */ - case 25: - *mer = 11; - break; - case 26: /* fall through */ - case 27: /* fall through */ - case 28: - *mer = 10; - break; - case 29: /* fall through */ - case 30: /* fall through */ - case 31: /* fall through */ - case 32: - *mer = 9; - break; - case 33: /* fall through */ - case 34: /* fall through */ - case 35: /* fall through */ - case 36: - *mer = 8; - break; - case 37: /* fall through */ - case 38: /* fall through */ - case 39: /* fall through */ - case 40: - *mer = 7; - break; - case 41: /* fall through */ - case 42: /* fall through */ - case 43: /* fall through */ - case 44: /* fall through */ - case 45: - *mer = 6; - break; - case 46: /* fall through */ - case 47: /* fall through */ - case 48: /* fall through */ - case 49: /* fall through */ - case 50: /* fall through */ - *mer = 5; - break; - case 51: /* fall through */ - case 52: /* fall through */ - case 53: /* fall through */ - case 54: /* fall through */ - case 55: /* fall through */ - case 56: /* fall through */ - case 57: - *mer = 4; - break; - case 58: /* fall through */ - case 59: /* fall through */ - case 60: /* fall through */ - case 61: /* fall through */ - case 62: /* fall through */ - case 63: - *mer = 0; - break; - default: - *mer = 0; - break; - } - return 0; -rw_error: - return -EIO; -} -#endif - -/** -* \fn int set_orx_nsu_aox() -* \brief Configure OrxNsuAox for OOB -* \param demod instance of demodulator. -* \param active -* \return int. -*/ -static int set_orx_nsu_aox(struct drx_demod_instance *demod, bool active) -{ - struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; - int rc; - u16 data = 0; - - /* Configure NSU_AOX */ - rc = drxj_dap_read_reg16(dev_addr, ORX_NSU_AOX_STDBY_W__A, &data, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - if (!active) - data &= ((~ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON)); - else - data |= (ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON); - rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_STDBY_W__A, data, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - return 0; -rw_error: - return -EIO; -} - -/** -* \fn int ctrl_set_oob() -* \brief Set OOB channel to be used. -* \param demod instance of demodulator -* \param oob_param OOB parameters for channel setting. -* \frequency should be in KHz -* \return int. -* -* Accepts only. Returns error otherwise. -* Demapper value is written after scu_command START -* because START command causes COMM_EXEC transition -* from 0 to 1 which causes all registers to be -* overwritten with initial value -* -*/ - -/* Nyquist filter impulse response */ -#define IMPULSE_COSINE_ALPHA_0_3 {-3, -4, -1, 6, 10, 7, -5, -20, -25, -10, 29, 79, 123, 140} /*sqrt raised-cosine filter with alpha=0.3 */ -#define IMPULSE_COSINE_ALPHA_0_5 { 2, 0, -2, -2, 2, 5, 2, -10, -20, -14, 20, 74, 125, 145} /*sqrt raised-cosine filter with alpha=0.5 */ -#define IMPULSE_COSINE_ALPHA_RO_0_5 { 0, 0, 1, 2, 3, 0, -7, -15, -16, 0, 34, 77, 114, 128} /*full raised-cosine filter with alpha=0.5 (receiver only) */ - -/* Coefficients for the nyquist fitler (total: 27 taps) */ -#define NYQFILTERLEN 27 - -static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_param) -{ - int rc; - s32 freq = 0; /* KHz */ - struct i2c_device_addr *dev_addr = NULL; - struct drxj_data *ext_attr = NULL; - u16 i = 0; - bool mirror_freq_spect_oob = false; - u16 trk_filter_value = 0; - struct drxjscu_cmd scu_cmd; - u16 set_param_parameters[3]; - u16 cmd_result[2] = { 0, 0 }; - s16 nyquist_coeffs[4][(NYQFILTERLEN + 1) / 2] = { - IMPULSE_COSINE_ALPHA_0_3, /* Target Mode 0 */ - IMPULSE_COSINE_ALPHA_0_3, /* Target Mode 1 */ - IMPULSE_COSINE_ALPHA_0_5, /* Target Mode 2 */ - IMPULSE_COSINE_ALPHA_RO_0_5 /* Target Mode 3 */ - }; - u8 mode_val[4] = { 2, 2, 0, 1 }; - u8 pfi_coeffs[4][6] = { - {DRXJ_16TO8(-92), DRXJ_16TO8(-108), DRXJ_16TO8(100)}, /* TARGET_MODE = 0: PFI_A = -23/32; PFI_B = -54/32; PFI_C = 25/32; fg = 0.5 MHz (Att=26dB) */ - {DRXJ_16TO8(-64), DRXJ_16TO8(-80), DRXJ_16TO8(80)}, /* TARGET_MODE = 1: PFI_A = -16/32; PFI_B = -40/32; PFI_C = 20/32; fg = 1.0 MHz (Att=28dB) */ - {DRXJ_16TO8(-80), DRXJ_16TO8(-98), DRXJ_16TO8(92)}, /* TARGET_MODE = 2, 3: PFI_A = -20/32; PFI_B = -49/32; PFI_C = 23/32; fg = 0.8 MHz (Att=25dB) */ - {DRXJ_16TO8(-80), DRXJ_16TO8(-98), DRXJ_16TO8(92)} /* TARGET_MODE = 2, 3: PFI_A = -20/32; PFI_B = -49/32; PFI_C = 23/32; fg = 0.8 MHz (Att=25dB) */ - }; - u16 mode_index; - - dev_addr = demod->my_i2c_dev_addr; - ext_attr = (struct drxj_data *) demod->my_ext_attr; - mirror_freq_spect_oob = ext_attr->mirror_freq_spect_oob; - - /* Check parameters */ - if (oob_param == NULL) { - /* power off oob module */ - scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB - | SCU_RAM_COMMAND_CMD_DEMOD_STOP; - scu_cmd.parameter_len = 0; - scu_cmd.result_len = 1; - scu_cmd.result = cmd_result; - rc = scu_command(dev_addr, &scu_cmd); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = set_orx_nsu_aox(demod, false); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - ext_attr->oob_power_on = false; - return 0; - } - - freq = oob_param->frequency; - if ((freq < 70000) || (freq > 130000)) - return -EIO; - freq = (freq - 50000) / 50; - - { - u16 index = 0; - u16 remainder = 0; - u16 *trk_filtercfg = ext_attr->oob_trk_filter_cfg; - - index = (u16) ((freq - 400) / 200); - remainder = (u16) ((freq - 400) % 200); - trk_filter_value = - trk_filtercfg[index] - (trk_filtercfg[index] - - trk_filtercfg[index + - 1]) / 10 * remainder / - 20; - } - - /*********/ - /* Stop */ - /*********/ - rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB - | SCU_RAM_COMMAND_CMD_DEMOD_STOP; - scu_cmd.parameter_len = 0; - scu_cmd.result_len = 1; - scu_cmd.result = cmd_result; - rc = scu_command(dev_addr, &scu_cmd); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - /*********/ - /* Reset */ - /*********/ - scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB - | SCU_RAM_COMMAND_CMD_DEMOD_RESET; - scu_cmd.parameter_len = 0; - scu_cmd.result_len = 1; - scu_cmd.result = cmd_result; - rc = scu_command(dev_addr, &scu_cmd); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - /***********/ - /* SET_ENV */ - /***********/ - /* set frequency, spectrum inversion and data rate */ - scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB - | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV; - scu_cmd.parameter_len = 3; - /* 1-data rate;2-frequency */ - switch (oob_param->standard) { - case DRX_OOB_MODE_A: - if ( - /* signal is transmitted inverted */ - ((oob_param->spectrum_inverted == true) && - /* and tuner is not mirroring the signal */ - (!mirror_freq_spect_oob)) | - /* or */ - /* signal is transmitted noninverted */ - ((oob_param->spectrum_inverted == false) && - /* and tuner is mirroring the signal */ - (mirror_freq_spect_oob)) - ) - set_param_parameters[0] = - SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC; - else - set_param_parameters[0] = - SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC; - break; - case DRX_OOB_MODE_B_GRADE_A: - if ( - /* signal is transmitted inverted */ - ((oob_param->spectrum_inverted == true) && - /* and tuner is not mirroring the signal */ - (!mirror_freq_spect_oob)) | - /* or */ - /* signal is transmitted noninverted */ - ((oob_param->spectrum_inverted == false) && - /* and tuner is mirroring the signal */ - (mirror_freq_spect_oob)) - ) - set_param_parameters[0] = - SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_INVSPEC; - else - set_param_parameters[0] = - SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_REGSPEC; - break; - case DRX_OOB_MODE_B_GRADE_B: - default: - if ( - /* signal is transmitted inverted */ - ((oob_param->spectrum_inverted == true) && - /* and tuner is not mirroring the signal */ - (!mirror_freq_spect_oob)) | - /* or */ - /* signal is transmitted noninverted */ - ((oob_param->spectrum_inverted == false) && - /* and tuner is mirroring the signal */ - (mirror_freq_spect_oob)) - ) - set_param_parameters[0] = - SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_INVSPEC; - else - set_param_parameters[0] = - SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_REGSPEC; - break; - } - set_param_parameters[1] = (u16) (freq & 0xFFFF); - set_param_parameters[2] = trk_filter_value; - scu_cmd.parameter = set_param_parameters; - scu_cmd.result_len = 1; - scu_cmd.result = cmd_result; - mode_index = mode_val[(set_param_parameters[0] & 0xC0) >> 6]; - rc = scu_command(dev_addr, &scu_cmd); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } /* Write magic word to enable pdr reg write */ - rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_OOB_CRX_CFG__A, OOB_CRX_DRIVE_STRENGTH << SIO_PDR_OOB_CRX_CFG_DRIVE__B | 0x03 << SIO_PDR_OOB_CRX_CFG_MODE__B, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_OOB_DRX_CFG__A, OOB_DRX_DRIVE_STRENGTH << SIO_PDR_OOB_DRX_CFG_DRIVE__B | 0x03 << SIO_PDR_OOB_DRX_CFG_MODE__B, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } /* Write magic word to disable pdr reg write */ - - rc = drxj_dap_write_reg16(dev_addr, ORX_TOP_COMM_KEY__A, 0, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_AAG_LEN_W__A, 16000, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_AAG_THR_W__A, 40, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* ddc */ - rc = drxj_dap_write_reg16(dev_addr, ORX_DDC_OFO_SET_W__A, ORX_DDC_OFO_SET_W__PRE, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* nsu */ - rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_LOPOW_W__A, ext_attr->oob_lo_pow, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* initialization for target mode */ - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TARGET_MODE__A, SCU_RAM_ORX_TARGET_MODE_2048KBPS_SQRT, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FREQ_GAIN_CORR__A, SCU_RAM_ORX_FREQ_GAIN_CORR_2048KBPS, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* Reset bits for timing and freq. recovery */ - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_CPH__A, 0x0001, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_CTI__A, 0x0002, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_KRN__A, 0x0004, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_KRP__A, 0x0008, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* AGN_LOCK = {2048>>3, -2048, 8, -8, 0, 1}; */ - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_TH__A, 2048 >> 3, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_TOTH__A, (u16)(-2048), 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_ONLOCK_TTH__A, 8, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_UNLOCK_TTH__A, (u16)(-8), 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_MASK__A, 1, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* DGN_LOCK = {10, -2048, 8, -8, 0, 1<<1}; */ - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_TH__A, 10, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_TOTH__A, (u16)(-2048), 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_ONLOCK_TTH__A, 8, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_UNLOCK_TTH__A, (u16)(-8), 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_MASK__A, 1 << 1, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* FRQ_LOCK = {15,-2048, 8, -8, 0, 1<<2}; */ - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TH__A, 17, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TOTH__A, (u16)(-2048), 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_ONLOCK_TTH__A, 8, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_UNLOCK_TTH__A, (u16)(-8), 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_MASK__A, 1 << 2, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* PHA_LOCK = {5000, -2048, 8, -8, 0, 1<<3}; */ - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_TH__A, 3000, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_TOTH__A, (u16)(-2048), 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_ONLOCK_TTH__A, 8, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_UNLOCK_TTH__A, (u16)(-8), 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_MASK__A, 1 << 3, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* TIM_LOCK = {300, -2048, 8, -8, 0, 1<<4}; */ - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_TH__A, 400, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_TOTH__A, (u16)(-2048), 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_ONLOCK_TTH__A, 8, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_UNLOCK_TTH__A, (u16)(-8), 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_MASK__A, 1 << 4, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* EQU_LOCK = {20, -2048, 8, -8, 0, 1<<5}; */ - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_TH__A, 20, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_TOTH__A, (u16)(-2048), 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_ONLOCK_TTH__A, 4, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_UNLOCK_TTH__A, (u16)(-4), 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_MASK__A, 1 << 5, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* PRE-Filter coefficients (PFI) */ - rc = drxdap_fasi_write_block(dev_addr, ORX_FWP_PFI_A_W__A, sizeof(pfi_coeffs[mode_index]), ((u8 *)pfi_coeffs[mode_index]), 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, ORX_TOP_MDE_W__A, mode_index, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* NYQUIST-Filter coefficients (NYQ) */ - for (i = 0; i < (NYQFILTERLEN + 1) / 2; i++) { - rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_ADR_W__A, i, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_COF_RW__A, nyquist_coeffs[mode_index][i], 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - } - rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_ADR_W__A, 31, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_ACTIVE, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - /*********/ - /* Start */ - /*********/ - scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB - | SCU_RAM_COMMAND_CMD_DEMOD_START; - scu_cmd.parameter_len = 0; - scu_cmd.result_len = 1; - scu_cmd.result = cmd_result; - rc = scu_command(dev_addr, &scu_cmd); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - rc = set_orx_nsu_aox(demod, true); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_STHR_W__A, ext_attr->oob_pre_saw, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - ext_attr->oob_power_on = true; - - return 0; -rw_error: - return -EIO; -} - -#if 0 - -/** -* \fn int ctrl_get_oob() -* \brief Set modulation standard to be used. -* \param demod instance of demodulator -* \param oob_status OOB status parameters. -* \return int. -*/ -static int -ctrl_get_oob(struct drx_demod_instance *demod, struct drxoob_status *oob_status) -{ - int rc; - struct i2c_device_addr *dev_addr = NULL; - struct drxj_data *ext_attr = NULL; - u16 data = 0; - - dev_addr = demod->my_i2c_dev_addr; - ext_attr = (struct drxj_data *) demod->my_ext_attr; - - /* check arguments */ - if (oob_status == NULL) - return -EINVAL; - - if (!ext_attr->oob_power_on) - return -EIO; - - rc = drxj_dap_read_reg16(dev_addr, ORX_DDC_OFO_SET_W__A, &data, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_read_reg16(dev_addr, ORX_NSU_TUN_RFGAIN_W__A, &data, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_read_reg16(dev_addr, ORX_FWP_AAG_THR_W__A, &data, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_ORX_DGN_KI__A, &data, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_read_reg16(dev_addr, ORX_FWP_SRC_DGN_W__A, &data, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - rc = get_oob_lock_status(demod, dev_addr, &oob_status->lock); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = get_oob_frequency(demod, &oob_status->frequency); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = get_oobmer(dev_addr, &oob_status->mer); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = get_oob_symbol_rate_offset(dev_addr, &oob_status->symbol_rate_offset); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - return 0; -rw_error: - return -EIO; -} - -/** -* \fn int ctrl_set_cfg_oob_pre_saw() -* \brief Configure PreSAW treshold value -* \param cfg_data Pointer to configuration parameter -* \return Error code -*/ -static int -ctrl_set_cfg_oob_pre_saw(struct drx_demod_instance *demod, u16 *cfg_data) -{ - struct i2c_device_addr *dev_addr = NULL; - struct drxj_data *ext_attr = NULL; - int rc; - - if (cfg_data == NULL) - return -EINVAL; - - dev_addr = demod->my_i2c_dev_addr; - ext_attr = (struct drxj_data *) demod->my_ext_attr; - - rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_STHR_W__A, *cfg_data, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - ext_attr->oob_pre_saw = *cfg_data; - return 0; -rw_error: - return -EIO; -} - -/** -* \fn int ctrl_get_cfg_oob_pre_saw() -* \brief Configure PreSAW treshold value -* \param cfg_data Pointer to configuration parameter -* \return Error code -*/ -static int -ctrl_get_cfg_oob_pre_saw(struct drx_demod_instance *demod, u16 *cfg_data) -{ - struct drxj_data *ext_attr = NULL; - - if (cfg_data == NULL) - return -EINVAL; - - ext_attr = (struct drxj_data *) demod->my_ext_attr; - - *cfg_data = ext_attr->oob_pre_saw; - - return 0; -} - -/** -* \fn int ctrl_set_cfg_oob_lo_power() -* \brief Configure LO Power value -* \param cfg_data Pointer to enum drxj_cfg_oob_lo_power ** \return Error code -*/ -static int -ctrl_set_cfg_oob_lo_power(struct drx_demod_instance *demod, enum drxj_cfg_oob_lo_power *cfg_data) -{ - struct i2c_device_addr *dev_addr = NULL; - struct drxj_data *ext_attr = NULL; - int rc; - - if (cfg_data == NULL) - return -EINVAL; - - dev_addr = demod->my_i2c_dev_addr; - ext_attr = (struct drxj_data *) demod->my_ext_attr; - - rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_LOPOW_W__A, *cfg_data, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - ext_attr->oob_lo_pow = *cfg_data; - return 0; -rw_error: - return -EIO; -} - -/** -* \fn int ctrl_get_cfg_oob_lo_power() -* \brief Configure LO Power value -* \param cfg_data Pointer to enum drxj_cfg_oob_lo_power ** \return Error code -*/ -static int -ctrl_get_cfg_oob_lo_power(struct drx_demod_instance *demod, enum drxj_cfg_oob_lo_power *cfg_data) -{ - struct drxj_data *ext_attr = NULL; - - if (cfg_data == NULL) - return -EINVAL; - - ext_attr = (struct drxj_data *) demod->my_ext_attr; - - *cfg_data = ext_attr->oob_lo_pow; - - return 0; -} -#endif -/*============================================================================*/ -/*== END OOB DATAPATH FUNCTIONS ==*/ -/*============================================================================*/ - -/*============================================================================= - ===== MC command related functions ========================================== - ===========================================================================*/ - -/*============================================================================= - ===== ctrl_set_channel() ========================================================== - ===========================================================================*/ -/** -* \fn int ctrl_set_channel() -* \brief Select a new transmission channel. -* \param demod instance of demod. -* \param channel Pointer to channel data. -* \return int. -* -* In case the tuner module is not used and in case of NTSC/FM the pogrammer -* must tune the tuner to the centre frequency of the NTSC/FM channel. -* -*/ -static int -ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) -{ - int rc; - s32 tuner_freq_offset = 0; - s32 intermediate_freq = 0; - struct drxj_data *ext_attr = NULL; - struct i2c_device_addr *dev_addr = NULL; - enum drx_standard standard = DRX_STANDARD_UNKNOWN; - struct drx_common_attr *common_attr = NULL; -#ifndef DRXJ_VSB_ONLY - u32 min_symbol_rate = 0; - u32 max_symbol_rate = 0; - int bandwidth_temp = 0; - int bandwidth = 0; -#endif - /*== check arguments ======================================================*/ - if ((demod == NULL) || (channel == NULL)) - return -EINVAL; - - common_attr = (struct drx_common_attr *) demod->my_common_attr; - dev_addr = demod->my_i2c_dev_addr; - ext_attr = (struct drxj_data *) demod->my_ext_attr; - standard = ext_attr->standard; - - /* check valid standards */ - switch (standard) { - case DRX_STANDARD_8VSB: -#ifndef DRXJ_VSB_ONLY - case DRX_STANDARD_ITU_A: - case DRX_STANDARD_ITU_B: - case DRX_STANDARD_ITU_C: -#endif /* DRXJ_VSB_ONLY */ -#if 0 - case DRX_STANDARD_NTSC: - case DRX_STANDARD_FM: - case DRX_STANDARD_PAL_SECAM_BG: - case DRX_STANDARD_PAL_SECAM_DK: - case DRX_STANDARD_PAL_SECAM_I: - case DRX_STANDARD_PAL_SECAM_L: - case DRX_STANDARD_PAL_SECAM_LP: -#endif - break; - case DRX_STANDARD_UNKNOWN: - default: - return -EINVAL; - } - - /* check bandwidth QAM annex B, NTSC and 8VSB */ - if ((standard == DRX_STANDARD_ITU_B) || - (standard == DRX_STANDARD_8VSB) || - (standard == DRX_STANDARD_NTSC)) { - switch (channel->bandwidth) { - case DRX_BANDWIDTH_6MHZ: - case DRX_BANDWIDTH_UNKNOWN: /* fall through */ - channel->bandwidth = DRX_BANDWIDTH_6MHZ; - break; - case DRX_BANDWIDTH_8MHZ: /* fall through */ - case DRX_BANDWIDTH_7MHZ: /* fall through */ - default: - return -EINVAL; - } - } -#if 0 - if (standard == DRX_STANDARD_PAL_SECAM_BG) { - switch (channel->bandwidth) { - case DRX_BANDWIDTH_7MHZ: /* fall through */ - case DRX_BANDWIDTH_8MHZ: - /* ok */ - break; - case DRX_BANDWIDTH_6MHZ: /* fall through */ - case DRX_BANDWIDTH_UNKNOWN: /* fall through */ - default: - return -EINVAL; - } - } - /* check bandwidth PAL/SECAM */ - if ((standard == DRX_STANDARD_PAL_SECAM_BG) || - (standard == DRX_STANDARD_PAL_SECAM_DK) || - (standard == DRX_STANDARD_PAL_SECAM_I) || - (standard == DRX_STANDARD_PAL_SECAM_L) || - (standard == DRX_STANDARD_PAL_SECAM_LP)) { - switch (channel->bandwidth) { - case DRX_BANDWIDTH_8MHZ: - case DRX_BANDWIDTH_UNKNOWN: /* fall through */ - channel->bandwidth = DRX_BANDWIDTH_8MHZ; - break; - case DRX_BANDWIDTH_6MHZ: /* fall through */ - case DRX_BANDWIDTH_7MHZ: /* fall through */ - default: - return -EINVAL; - } - } -#endif - - /* For QAM annex A and annex C: - -check symbolrate and constellation - -derive bandwidth from symbolrate (input bandwidth is ignored) - */ -#ifndef DRXJ_VSB_ONLY - if ((standard == DRX_STANDARD_ITU_A) || - (standard == DRX_STANDARD_ITU_C)) { - struct drxuio_cfg uio_cfg = { DRX_UIO1, DRX_UIO_MODE_FIRMWARE_SAW }; - int bw_rolloff_factor = 0; - - bw_rolloff_factor = (standard == DRX_STANDARD_ITU_A) ? 115 : 113; - min_symbol_rate = DRXJ_QAM_SYMBOLRATE_MIN; - max_symbol_rate = DRXJ_QAM_SYMBOLRATE_MAX; - /* config SMA_TX pin to SAW switch mode */ - rc = ctrl_set_uio_cfg(demod, &uio_cfg); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - if (channel->symbolrate < min_symbol_rate || - channel->symbolrate > max_symbol_rate) { - return -EINVAL; - } - - switch (channel->constellation) { - case DRX_CONSTELLATION_QAM16: /* fall through */ - case DRX_CONSTELLATION_QAM32: /* fall through */ - case DRX_CONSTELLATION_QAM64: /* fall through */ - case DRX_CONSTELLATION_QAM128: /* fall through */ - case DRX_CONSTELLATION_QAM256: - bandwidth_temp = channel->symbolrate * bw_rolloff_factor; - bandwidth = bandwidth_temp / 100; - - if ((bandwidth_temp % 100) >= 50) - bandwidth++; - - if (bandwidth <= 6100000) { - channel->bandwidth = DRX_BANDWIDTH_6MHZ; - } else if ((bandwidth > 6100000) - && (bandwidth <= 7100000)) { - channel->bandwidth = DRX_BANDWIDTH_7MHZ; - } else if (bandwidth > 7100000) { - channel->bandwidth = DRX_BANDWIDTH_8MHZ; - } - break; - default: - return -EINVAL; - } - } - - /* For QAM annex B: - -check constellation - */ - if (standard == DRX_STANDARD_ITU_B) { - switch (channel->constellation) { - case DRX_CONSTELLATION_AUTO: - case DRX_CONSTELLATION_QAM256: - case DRX_CONSTELLATION_QAM64: - break; - default: - return -EINVAL; - } - - switch (channel->interleavemode) { - case DRX_INTERLEAVEMODE_I128_J1: - case DRX_INTERLEAVEMODE_I128_J1_V2: - case DRX_INTERLEAVEMODE_I128_J2: - case DRX_INTERLEAVEMODE_I64_J2: - case DRX_INTERLEAVEMODE_I128_J3: - case DRX_INTERLEAVEMODE_I32_J4: - case DRX_INTERLEAVEMODE_I128_J4: - case DRX_INTERLEAVEMODE_I16_J8: - case DRX_INTERLEAVEMODE_I128_J5: - case DRX_INTERLEAVEMODE_I8_J16: - case DRX_INTERLEAVEMODE_I128_J6: - case DRX_INTERLEAVEMODE_I128_J7: - case DRX_INTERLEAVEMODE_I128_J8: - case DRX_INTERLEAVEMODE_I12_J17: - case DRX_INTERLEAVEMODE_I5_J4: - case DRX_INTERLEAVEMODE_B52_M240: - case DRX_INTERLEAVEMODE_B52_M720: - case DRX_INTERLEAVEMODE_UNKNOWN: - case DRX_INTERLEAVEMODE_AUTO: - break; - default: - return -EINVAL; - } - } - - if ((ext_attr->uio_sma_tx_mode) == DRX_UIO_MODE_FIRMWARE_SAW) { - /* SAW SW, user UIO is used for switchable SAW */ - struct drxuio_data uio1 = { DRX_UIO1, false }; - - switch (channel->bandwidth) { - case DRX_BANDWIDTH_8MHZ: - uio1.value = true; - break; - case DRX_BANDWIDTH_7MHZ: - uio1.value = false; - break; - case DRX_BANDWIDTH_6MHZ: - uio1.value = false; - break; - case DRX_BANDWIDTH_UNKNOWN: - default: - return -EINVAL; - } - - rc = ctrl_uio_write(demod, &uio1); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - } -#endif /* DRXJ_VSB_ONLY */ - rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - tuner_freq_offset = 0; - intermediate_freq = demod->my_common_attr->intermediate_freq; - - /*== Setup demod for specific standard ====================================*/ - switch (standard) { - case DRX_STANDARD_8VSB: - if (channel->mirror == DRX_MIRROR_AUTO) - ext_attr->mirror = DRX_MIRROR_NO; - else - ext_attr->mirror = channel->mirror; - rc = set_vsb(demod); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = set_frequency(demod, channel, tuner_freq_offset); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - break; -#if 0 - case DRX_STANDARD_NTSC: /* fallthrough */ - case DRX_STANDARD_FM: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_LP: - if (channel->mirror == DRX_MIRROR_AUTO) - ext_attr->mirror = DRX_MIRROR_NO; - else - ext_attr->mirror = channel->mirror; - rc = set_atv_channel(demod, tuner_freq_offset, channel, standard); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - break; -#endif -#ifndef DRXJ_VSB_ONLY - case DRX_STANDARD_ITU_A: /* fallthrough */ - case DRX_STANDARD_ITU_B: /* fallthrough */ - case DRX_STANDARD_ITU_C: - rc = set_qam_channel(demod, channel, tuner_freq_offset); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - break; -#endif - case DRX_STANDARD_UNKNOWN: - default: - return -EIO; - } - - /* flag the packet error counter reset */ - ext_attr->reset_pkt_err_acc = true; - - return 0; -rw_error: - return -EIO; -} - -#if 0 -/*============================================================================= - ===== ctrl_get_channel() ========================================================== - ===========================================================================*/ -/** -* \fn int ctrl_get_channel() -* \brief Retreive parameters of current transmission channel. -* \param demod Pointer to demod instance. -* \param channel Pointer to channel data. -* \return int. -*/ -static int -ctrl_get_channel(struct drx_demod_instance *demod, struct drx_channel *channel) -{ - struct i2c_device_addr *dev_addr = NULL; - struct drxj_data *ext_attr = NULL; - int rc; - enum drx_lock_status lock_status = DRX_NOT_LOCKED; - enum drx_standard standard = DRX_STANDARD_UNKNOWN; - struct drx_common_attr *common_attr = NULL; - s32 intermediate_freq = 0; - s32 ctl_freq_offset = 0; - u32 iqm_rc_rate_lo = 0; - u32 adc_frequency = 0; -#ifndef DRXJ_VSB_ONLY - int bandwidth_temp = 0; - int bandwidth = 0; -#endif - - /* check arguments */ - if ((demod == NULL) || (channel == NULL)) - return -EINVAL; - - dev_addr = demod->my_i2c_dev_addr; - ext_attr = (struct drxj_data *) demod->my_ext_attr; - standard = ext_attr->standard; - common_attr = (struct drx_common_attr *) demod->my_common_attr; - - /* initialize channel fields */ - channel->mirror = DRX_MIRROR_UNKNOWN; - channel->hierarchy = DRX_HIERARCHY_UNKNOWN; - channel->priority = DRX_PRIORITY_UNKNOWN; - channel->coderate = DRX_CODERATE_UNKNOWN; - channel->guard = DRX_GUARD_UNKNOWN; - channel->fftmode = DRX_FFTMODE_UNKNOWN; - channel->classification = DRX_CLASSIFICATION_UNKNOWN; - channel->bandwidth = DRX_BANDWIDTH_UNKNOWN; - channel->constellation = DRX_CONSTELLATION_UNKNOWN; - channel->symbolrate = 0; - channel->interleavemode = DRX_INTERLEAVEMODE_UNKNOWN; - channel->carrier = DRX_CARRIER_UNKNOWN; - channel->framemode = DRX_FRAMEMODE_UNKNOWN; -/* channel->interleaver = DRX_INTERLEAVER_UNKNOWN;*/ - channel->ldpc = DRX_LDPC_UNKNOWN; - - intermediate_freq = common_attr->intermediate_freq; - - /* check lock status */ - rc = ctrl_lock_status(demod, &lock_status); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - if ((lock_status == DRX_LOCKED) || (lock_status == DRXJ_DEMOD_LOCK)) { - rc = drxj_dap_atomic_read_reg32(dev_addr, IQM_RC_RATE_LO__A, &iqm_rc_rate_lo, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - adc_frequency = (common_attr->sys_clock_freq * 1000) / 3; - - channel->symbolrate = - frac28(adc_frequency, (iqm_rc_rate_lo + (1 << 23))) >> 7; - - switch (standard) { - case DRX_STANDARD_8VSB: - channel->bandwidth = DRX_BANDWIDTH_6MHZ; - /* get the channel frequency */ - rc = get_ctl_freq_offset(demod, &ctl_freq_offset); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - channel->frequency -= ctl_freq_offset; - /* get the channel constellation */ - channel->constellation = DRX_CONSTELLATION_AUTO; - break; -#ifndef DRXJ_VSB_ONLY - case DRX_STANDARD_ITU_A: - case DRX_STANDARD_ITU_B: - case DRX_STANDARD_ITU_C: - { - /* get the channel frequency */ - rc = get_ctl_freq_offset(demod, &ctl_freq_offset); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - channel->frequency -= ctl_freq_offset; - - if (standard == DRX_STANDARD_ITU_B) { - channel->bandwidth = DRX_BANDWIDTH_6MHZ; - } else { - /* annex A & C */ - - u32 roll_off = 113; /* default annex C */ - - if (standard == DRX_STANDARD_ITU_A) - roll_off = 115; - - bandwidth_temp = - channel->symbolrate * roll_off; - bandwidth = bandwidth_temp / 100; - - if ((bandwidth_temp % 100) >= 50) - bandwidth++; - - if (bandwidth <= 6000000) { - channel->bandwidth = - DRX_BANDWIDTH_6MHZ; - } else if ((bandwidth > 6000000) - && (bandwidth <= 7000000)) { - channel->bandwidth = - DRX_BANDWIDTH_7MHZ; - } else if (bandwidth > 7000000) { - channel->bandwidth = - DRX_BANDWIDTH_8MHZ; - } - } /* if (standard == DRX_STANDARD_ITU_B) */ - - { - struct drxjscu_cmd cmd_scu = { 0, 0, 0, NULL, NULL }; - u16 cmd_result[3] = { 0, 0, 0 }; - - cmd_scu.command = - SCU_RAM_COMMAND_STANDARD_QAM | - SCU_RAM_COMMAND_CMD_DEMOD_GET_PARAM; - cmd_scu.parameter_len = 0; - cmd_scu.result_len = 3; - cmd_scu.parameter = NULL; - cmd_scu.result = cmd_result; - rc = scu_command(dev_addr, &cmd_scu); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - channel->interleavemode = - (enum drx_interleave_mode) (cmd_scu. - result[2]); - } - - switch (ext_attr->constellation) { - case DRX_CONSTELLATION_QAM256: - channel->constellation = - DRX_CONSTELLATION_QAM256; - break; - case DRX_CONSTELLATION_QAM128: - channel->constellation = - DRX_CONSTELLATION_QAM128; - break; - case DRX_CONSTELLATION_QAM64: - channel->constellation = - DRX_CONSTELLATION_QAM64; - break; - case DRX_CONSTELLATION_QAM32: - channel->constellation = - DRX_CONSTELLATION_QAM32; - break; - case DRX_CONSTELLATION_QAM16: - channel->constellation = - DRX_CONSTELLATION_QAM16; - break; - default: - channel->constellation = - DRX_CONSTELLATION_UNKNOWN; - return -EIO; - } - } - break; -#endif - case DRX_STANDARD_NTSC: /* fall trough */ - case DRX_STANDARD_PAL_SECAM_BG: - case DRX_STANDARD_PAL_SECAM_DK: - case DRX_STANDARD_PAL_SECAM_I: - case DRX_STANDARD_PAL_SECAM_L: - case DRX_STANDARD_PAL_SECAM_LP: - case DRX_STANDARD_FM: - rc = get_atv_channel(demod, channel, standard); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - break; - case DRX_STANDARD_UNKNOWN: /* fall trough */ - default: - return -EIO; - } /* switch ( standard ) */ - - if (lock_status == DRX_LOCKED) - channel->mirror = ext_attr->mirror; - } - /* if ( lock_status == DRX_LOCKED ) */ - return 0; -rw_error: - return -EIO; -} -#endif - -/*============================================================================= - ===== SigQuality() ========================================================== - ===========================================================================*/ - -static u16 -mer2indicator(u16 mer, u16 min_mer, u16 threshold_mer, u16 max_mer) -{ - u16 indicator = 0; - - if (mer < min_mer) { - indicator = 0; - } else if (mer < threshold_mer) { - if ((threshold_mer - min_mer) != 0) - indicator = 25 * (mer - min_mer) / (threshold_mer - min_mer); - } else if (mer < max_mer) { - if ((max_mer - threshold_mer) != 0) - indicator = 25 + 75 * (mer - threshold_mer) / (max_mer - threshold_mer); - else - indicator = 25; - } else { - indicator = 100; - } - - return indicator; -} - -/** -* \fn int ctrl_sig_quality() -* \brief Retreive signal quality form device. -* \param devmod Pointer to demodulator instance. -* \param sig_quality Pointer to signal quality data. -* \return int. -* \retval 0 sig_quality contains valid data. -* \retval -EINVAL sig_quality is NULL. -* \retval -EIO Erroneous data, sig_quality contains invalid data. - -*/ -static int -ctrl_sig_quality(struct drx_demod_instance *demod, struct drx_sig_quality *sig_quality) -{ - struct i2c_device_addr *dev_addr = NULL; - struct drxj_data *ext_attr = NULL; - int rc; - enum drx_standard standard = DRX_STANDARD_UNKNOWN; - enum drx_lock_status lock_status = DRX_NOT_LOCKED; - u16 min_mer = 0; - u16 max_mer = 0; - u16 threshold_mer = 0; - - /* Check arguments */ - if ((sig_quality == NULL) || (demod == NULL)) - return -EINVAL; - - ext_attr = (struct drxj_data *) demod->my_ext_attr; - standard = ext_attr->standard; - - /* get basic information */ - dev_addr = demod->my_i2c_dev_addr; - rc = ctrl_lock_status(demod, &lock_status); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - switch (standard) { - case DRX_STANDARD_8VSB: -#ifdef DRXJ_SIGNAL_ACCUM_ERR - rc = get_acc_pkt_err(demod, &sig_quality->packet_error); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } -#else - rc = get_vsb_post_rs_pck_err(dev_addr, &sig_quality->packet_error); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } -#endif - if (lock_status != DRXJ_DEMOD_LOCK && lock_status != DRX_LOCKED) { - sig_quality->post_viterbi_ber = 500000; - sig_quality->MER = 20; - sig_quality->pre_viterbi_ber = 0; - } else { - /* PostViterbi is compute in steps of 10^(-6) */ - rc = get_vs_bpre_viterbi_ber(dev_addr, &sig_quality->pre_viterbi_ber); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = get_vs_bpost_viterbi_ber(dev_addr, &sig_quality->post_viterbi_ber); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = get_vsbmer(dev_addr, &sig_quality->MER); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - } - min_mer = 20; - max_mer = 360; - threshold_mer = 145; - sig_quality->post_reed_solomon_ber = 0; - sig_quality->scale_factor_ber = 1000000; - sig_quality->indicator = - mer2indicator(sig_quality->MER, min_mer, threshold_mer, - max_mer); - break; -#ifndef DRXJ_VSB_ONLY - case DRX_STANDARD_ITU_A: - case DRX_STANDARD_ITU_B: - case DRX_STANDARD_ITU_C: - rc = ctrl_get_qam_sig_quality(demod, sig_quality); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - if (lock_status != DRXJ_DEMOD_LOCK && lock_status != DRX_LOCKED) { - switch (ext_attr->constellation) { - case DRX_CONSTELLATION_QAM256: - sig_quality->MER = 210; - break; - case DRX_CONSTELLATION_QAM128: - sig_quality->MER = 180; - break; - case DRX_CONSTELLATION_QAM64: - sig_quality->MER = 150; - break; - case DRX_CONSTELLATION_QAM32: - sig_quality->MER = 120; - break; - case DRX_CONSTELLATION_QAM16: - sig_quality->MER = 90; - break; - default: - sig_quality->MER = 0; - return -EIO; - } - } - - switch (ext_attr->constellation) { - case DRX_CONSTELLATION_QAM256: - min_mer = 210; - threshold_mer = 270; - max_mer = 380; - break; - case DRX_CONSTELLATION_QAM64: - min_mer = 150; - threshold_mer = 210; - max_mer = 380; - break; - case DRX_CONSTELLATION_QAM128: - case DRX_CONSTELLATION_QAM32: - case DRX_CONSTELLATION_QAM16: - break; - default: - return -EIO; - } - sig_quality->indicator = - mer2indicator(sig_quality->MER, min_mer, threshold_mer, - max_mer); - break; -#endif -#if 0 - case DRX_STANDARD_PAL_SECAM_BG: - case DRX_STANDARD_PAL_SECAM_DK: - case DRX_STANDARD_PAL_SECAM_I: - case DRX_STANDARD_PAL_SECAM_L: - case DRX_STANDARD_PAL_SECAM_LP: - case DRX_STANDARD_NTSC: - rc = atv_sig_quality(demod, sig_quality); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - break; - case DRX_STANDARD_FM: - rc = fm_sig_quality(demod, sig_quality); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - break; -#endif - default: - return -EIO; - } - - return 0; -rw_error: - return -EIO; -} - -/*============================================================================*/ - -/** -* \fn int ctrl_lock_status() -* \brief Retreive lock status . -* \param dev_addr Pointer to demodulator device address. -* \param lock_stat Pointer to lock status structure. -* \return int. -* -*/ -static int -ctrl_lock_status(struct drx_demod_instance *demod, enum drx_lock_status *lock_stat) -{ - enum drx_standard standard = DRX_STANDARD_UNKNOWN; - struct drxj_data *ext_attr = NULL; - struct i2c_device_addr *dev_addr = NULL; - struct drxjscu_cmd cmd_scu = { /* command */ 0, - /* parameter_len */ 0, - /* result_len */ 0, - /* *parameter */ NULL, - /* *result */ NULL - }; - int rc; - u16 cmd_result[2] = { 0, 0 }; - u16 demod_lock = SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_DEMOD_LOCKED; - - /* check arguments */ - if ((demod == NULL) || (lock_stat == NULL)) - return -EINVAL; - - dev_addr = demod->my_i2c_dev_addr; - ext_attr = (struct drxj_data *) demod->my_ext_attr; - standard = ext_attr->standard; - - *lock_stat = DRX_NOT_LOCKED; - - /* define the SCU command code */ - switch (standard) { - case DRX_STANDARD_8VSB: - cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB | - SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK; - demod_lock |= 0x6; - break; -#ifndef DRXJ_VSB_ONLY - case DRX_STANDARD_ITU_A: - case DRX_STANDARD_ITU_B: - case DRX_STANDARD_ITU_C: - cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM | - SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK; - break; -#endif -#if 0 - case DRX_STANDARD_NTSC: - case DRX_STANDARD_PAL_SECAM_BG: - case DRX_STANDARD_PAL_SECAM_DK: - case DRX_STANDARD_PAL_SECAM_I: - case DRX_STANDARD_PAL_SECAM_L: - case DRX_STANDARD_PAL_SECAM_LP: - cmd_scu.command = SCU_RAM_COMMAND_STANDARD_ATV | - SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK; - break; - case DRX_STANDARD_FM: - return fm_lock_status(demod, lock_stat); -#endif - case DRX_STANDARD_UNKNOWN: /* fallthrough */ - default: - return -EIO; - } - - /* define the SCU command paramters and execute the command */ - cmd_scu.parameter_len = 0; - cmd_scu.result_len = 2; - cmd_scu.parameter = NULL; - cmd_scu.result = cmd_result; - rc = scu_command(dev_addr, &cmd_scu); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - /* set the lock status */ - if (cmd_scu.result[1] < demod_lock) { - /* 0x0000 NOT LOCKED */ - *lock_stat = DRX_NOT_LOCKED; - } else if (cmd_scu.result[1] < SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_LOCKED) { - *lock_stat = DRXJ_DEMOD_LOCK; - } else if (cmd_scu.result[1] < - SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NEVER_LOCK) { - /* 0x8000 DEMOD + FEC LOCKED (system lock) */ - *lock_stat = DRX_LOCKED; - } else { - /* 0xC000 NEVER LOCKED */ - /* (system will never be able to lock to the signal) */ - *lock_stat = DRX_NEVER_LOCK; - } - - return 0; -rw_error: - return -EIO; -} - -/*============================================================================*/ - -#if 0 -/** -* \fn int ctrl_constel() -* \brief Retreive a constellation point via I2C. -* \param demod Pointer to demodulator instance. -* \param complex_nr Pointer to the structure in which to store the - constellation point. -* \return int. -*/ -static int -ctrl_constel(struct drx_demod_instance *demod, struct drx_complex *complex_nr) -{ - int rc; - enum drx_standard standard = DRX_STANDARD_UNKNOWN; - /**< active standard */ - - /* check arguments */ - if ((demod == NULL) || (complex_nr == NULL)) - return -EINVAL; - - /* read device info */ - standard = ((struct drxj_data *) demod->my_ext_attr)->standard; - - /* Read constellation point */ - switch (standard) { - case DRX_STANDARD_8VSB: - rc = ctrl_get_vsb_constel(demod, complex_nr); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - break; -#ifndef DRXJ_VSB_ONLY - case DRX_STANDARD_ITU_A: /* fallthrough */ - case DRX_STANDARD_ITU_B: /* fallthrough */ - case DRX_STANDARD_ITU_C: - rc = ctrl_get_qam_constel(demod, complex_nr); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - break; -#endif - case DRX_STANDARD_UNKNOWN: - default: - return -EIO; - } - - return 0; -rw_error: - return -EIO; -} -#endif - -/*============================================================================*/ - -/** -* \fn int ctrl_set_standard() -* \brief Set modulation standard to be used. -* \param standard Modulation standard. -* \return int. -* -* Setup stuff for the desired demodulation standard. -* Disable and power down the previous selected demodulation standard -* -*/ -static int -ctrl_set_standard(struct drx_demod_instance *demod, enum drx_standard *standard) -{ - struct drxj_data *ext_attr = NULL; - int rc; - enum drx_standard prev_standard; - - /* check arguments */ - if ((standard == NULL) || (demod == NULL)) - return -EINVAL; - - ext_attr = (struct drxj_data *) demod->my_ext_attr; - prev_standard = ext_attr->standard; - - /* - Stop and power down previous standard - */ - switch (prev_standard) { -#ifndef DRXJ_VSB_ONLY - case DRX_STANDARD_ITU_A: /* fallthrough */ - case DRX_STANDARD_ITU_B: /* fallthrough */ - case DRX_STANDARD_ITU_C: - rc = power_down_qam(demod, false); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - break; -#endif - case DRX_STANDARD_8VSB: - rc = power_down_vsb(demod, false); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - break; -#if 0 - case DRX_STANDARD_NTSC: /* fallthrough */ - case DRX_STANDARD_FM: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_LP: - rc = power_down_atv(demod, prev_standard, false); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - break; -#endif - case DRX_STANDARD_UNKNOWN: - /* Do nothing */ - break; - case DRX_STANDARD_AUTO: /* fallthrough */ - default: - return -EINVAL; - } - - /* - Initialize channel independent registers - Power up new standard - */ - ext_attr->standard = *standard; - - switch (*standard) { -#ifndef DRXJ_VSB_ONLY - case DRX_STANDARD_ITU_A: /* fallthrough */ - case DRX_STANDARD_ITU_B: /* fallthrough */ - case DRX_STANDARD_ITU_C: - do { - u16 dummy; - rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SCU_RAM_VERSION_HI__A, &dummy, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - } while (0); - break; -#endif - case DRX_STANDARD_8VSB: - rc = set_vsb_leak_n_gain(demod); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - break; -#if 0 - case DRX_STANDARD_NTSC: /* fallthrough */ - case DRX_STANDARD_FM: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_LP: - rc = set_atv_standard(demod, standard); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = power_up_atv(demod, *standard); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - break; -#endif - default: - ext_attr->standard = DRX_STANDARD_UNKNOWN; - return -EINVAL; - break; - } - - return 0; -rw_error: - /* Don't know what the standard is now ... try again */ - ext_attr->standard = DRX_STANDARD_UNKNOWN; - return -EIO; -} - -#if 0 -/*============================================================================*/ - -/** -* \fn int ctrl_get_standard() -* \brief Get modulation standard currently used to demodulate. -* \param standard Modulation standard. -* \return int. -* -* Returns 8VSB, NTSC, QAM only. -* -*/ -static int -ctrl_get_standard(struct drx_demod_instance *demod, enum drx_standard *standard) -{ - struct drxj_data *ext_attr = NULL; - int rc; - ext_attr = (struct drxj_data *) demod->my_ext_attr; - - /* check arguments */ - if (standard == NULL) - return -EINVAL; - - *standard = ext_attr->standard; - do { - u16 dummy; - rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SCU_RAM_VERSION_HI__A, &dummy, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - } while (0); - - return 0; -rw_error: - return -EIO; -} - -/*============================================================================*/ - -/** -* \fn int ctrl_get_cfg_symbol_clock_offset() -* \brief Get frequency offsets of STR. -* \param pointer to s32. -* \return int. -* -*/ -static int -ctrl_get_cfg_symbol_clock_offset(struct drx_demod_instance *demod, s32 *rate_offset) -{ - enum drx_standard standard = DRX_STANDARD_UNKNOWN; - int rc; - struct drxj_data *ext_attr = NULL; - - /* check arguments */ - if (rate_offset == NULL) - return -EINVAL; - - ext_attr = (struct drxj_data *) demod->my_ext_attr; - standard = ext_attr->standard; - - switch (standard) { - case DRX_STANDARD_8VSB: /* fallthrough */ -#ifndef DRXJ_VSB_ONLY - case DRX_STANDARD_ITU_A: /* fallthrough */ - case DRX_STANDARD_ITU_B: /* fallthrough */ - case DRX_STANDARD_ITU_C: -#endif - rc = get_str_freq_offset(demod, rate_offset); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - break; - case DRX_STANDARD_NTSC: - case DRX_STANDARD_UNKNOWN: - default: - return -EINVAL; - } - - return 0; -rw_error: - return -EIO; -} -#endif - -/*============================================================================*/ - -static void drxj_reset_mode(struct drxj_data *ext_attr) -{ - /* Initialize default AFE configuartion for QAM */ - if (ext_attr->has_lna) { - /* IF AGC off, PGA active */ -#ifndef DRXJ_VSB_ONLY - ext_attr->qam_if_agc_cfg.standard = DRX_STANDARD_ITU_B; - ext_attr->qam_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_OFF; - ext_attr->qam_pga_cfg = 140 + (11 * 13); -#endif - ext_attr->vsb_if_agc_cfg.standard = DRX_STANDARD_8VSB; - ext_attr->vsb_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_OFF; - ext_attr->vsb_pga_cfg = 140 + (11 * 13); - } else { - /* IF AGC on, PGA not active */ -#ifndef DRXJ_VSB_ONLY - ext_attr->qam_if_agc_cfg.standard = DRX_STANDARD_ITU_B; - ext_attr->qam_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; - ext_attr->qam_if_agc_cfg.min_output_level = 0; - ext_attr->qam_if_agc_cfg.max_output_level = 0x7FFF; - ext_attr->qam_if_agc_cfg.speed = 3; - ext_attr->qam_if_agc_cfg.top = 1297; - ext_attr->qam_pga_cfg = 140; -#endif - ext_attr->vsb_if_agc_cfg.standard = DRX_STANDARD_8VSB; - ext_attr->vsb_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; - ext_attr->vsb_if_agc_cfg.min_output_level = 0; - ext_attr->vsb_if_agc_cfg.max_output_level = 0x7FFF; - ext_attr->vsb_if_agc_cfg.speed = 3; - ext_attr->vsb_if_agc_cfg.top = 1024; - ext_attr->vsb_pga_cfg = 140; - } - /* TODO: remove min_output_level and max_output_level for both QAM and VSB after */ - /* mc has not used them */ -#ifndef DRXJ_VSB_ONLY - ext_attr->qam_rf_agc_cfg.standard = DRX_STANDARD_ITU_B; - ext_attr->qam_rf_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; - ext_attr->qam_rf_agc_cfg.min_output_level = 0; - ext_attr->qam_rf_agc_cfg.max_output_level = 0x7FFF; - ext_attr->qam_rf_agc_cfg.speed = 3; - ext_attr->qam_rf_agc_cfg.top = 9500; - ext_attr->qam_rf_agc_cfg.cut_off_current = 4000; - ext_attr->qam_pre_saw_cfg.standard = DRX_STANDARD_ITU_B; - ext_attr->qam_pre_saw_cfg.reference = 0x07; - ext_attr->qam_pre_saw_cfg.use_pre_saw = true; -#endif - /* Initialize default AFE configuartion for VSB */ - ext_attr->vsb_rf_agc_cfg.standard = DRX_STANDARD_8VSB; - ext_attr->vsb_rf_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; - ext_attr->vsb_rf_agc_cfg.min_output_level = 0; - ext_attr->vsb_rf_agc_cfg.max_output_level = 0x7FFF; - ext_attr->vsb_rf_agc_cfg.speed = 3; - ext_attr->vsb_rf_agc_cfg.top = 9500; - ext_attr->vsb_rf_agc_cfg.cut_off_current = 4000; - ext_attr->vsb_pre_saw_cfg.standard = DRX_STANDARD_8VSB; - ext_attr->vsb_pre_saw_cfg.reference = 0x07; - ext_attr->vsb_pre_saw_cfg.use_pre_saw = true; + ext_attr->oob_power_on = true; -#if 0 - /* Initialize default AFE configuartion for ATV */ - ext_attr->atv_rf_agc_cfg.standard = DRX_STANDARD_NTSC; - ext_attr->atv_rf_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; - ext_attr->atv_rf_agc_cfg.top = 9500; - ext_attr->atv_rf_agc_cfg.cut_off_current = 4000; - ext_attr->atv_rf_agc_cfg.speed = 3; - ext_attr->atv_if_agc_cfg.standard = DRX_STANDARD_NTSC; - ext_attr->atv_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; - ext_attr->atv_if_agc_cfg.speed = 3; - ext_attr->atv_if_agc_cfg.top = 2400; - ext_attr->atv_pre_saw_cfg.reference = 0x0007; - ext_attr->atv_pre_saw_cfg.use_pre_saw = true; - ext_attr->atv_pre_saw_cfg.standard = DRX_STANDARD_NTSC; -#endif + return 0; +rw_error: + return -EIO; } +/*============================================================================*/ +/*== END OOB DATAPATH FUNCTIONS ==*/ +/*============================================================================*/ + +/*============================================================================= + ===== MC command related functions ========================================== + ===========================================================================*/ + +/*============================================================================= + ===== ctrl_set_channel() ========================================================== + ===========================================================================*/ /** -* \fn int ctrl_power_mode() -* \brief Set the power mode of the device to the specified power mode -* \param demod Pointer to demodulator instance. -* \param mode Pointer to new power mode. +* \fn int ctrl_set_channel() +* \brief Select a new transmission channel. +* \param demod instance of demod. +* \param channel Pointer to channel data. * \return int. -* \retval 0 Success -* \retval -EIO I2C error or other failure -* \retval -EINVAL Invalid mode argument. * +* In case the tuner module is not used and in case of NTSC/FM the pogrammer +* must tune the tuner to the centre frequency of the NTSC/FM channel. * */ static int -ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode) +ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) { - struct drx_common_attr *common_attr = (struct drx_common_attr *) NULL; - struct drxj_data *ext_attr = (struct drxj_data *) NULL; - struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; int rc; - u16 sio_cc_pwd_mode = 0; + s32 tuner_freq_offset = 0; + s32 intermediate_freq = 0; + struct drxj_data *ext_attr = NULL; + struct i2c_device_addr *dev_addr = NULL; + enum drx_standard standard = DRX_STANDARD_UNKNOWN; + struct drx_common_attr *common_attr = NULL; +#ifndef DRXJ_VSB_ONLY + u32 min_symbol_rate = 0; + u32 max_symbol_rate = 0; + int bandwidth_temp = 0; + int bandwidth = 0; +#endif + /*== check arguments ======================================================*/ + if ((demod == NULL) || (channel == NULL)) + return -EINVAL; common_attr = (struct drx_common_attr *) demod->my_common_attr; - ext_attr = (struct drxj_data *) demod->my_ext_attr; dev_addr = demod->my_i2c_dev_addr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; + standard = ext_attr->standard; - /* Check arguments */ - if (mode == NULL) - return -EINVAL; - - /* If already in requested power mode, do nothing */ - if (common_attr->current_power_mode == *mode) - return 0; - - switch (*mode) { - case DRX_POWER_UP: - case DRXJ_POWER_DOWN_MAIN_PATH: - sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_NONE; - break; - case DRXJ_POWER_DOWN_CORE: - sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_CLOCK; - break; - case DRXJ_POWER_DOWN_PLL: - sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_PLL; - break; - case DRX_POWER_DOWN: - sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_OSC; + /* check valid standards */ + switch (standard) { + case DRX_STANDARD_8VSB: +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: +#endif /* DRXJ_VSB_ONLY */ break; + case DRX_STANDARD_UNKNOWN: default: - /* Unknow sleep mode */ return -EINVAL; - break; } - /* Check if device needs to be powered up */ - if ((common_attr->current_power_mode != DRX_POWER_UP)) { - rc = power_up_device(demod); + /* check bandwidth QAM annex B, NTSC and 8VSB */ + if ((standard == DRX_STANDARD_ITU_B) || + (standard == DRX_STANDARD_8VSB) || + (standard == DRX_STANDARD_NTSC)) { + switch (channel->bandwidth) { + case DRX_BANDWIDTH_6MHZ: + case DRX_BANDWIDTH_UNKNOWN: /* fall through */ + channel->bandwidth = DRX_BANDWIDTH_6MHZ; + break; + case DRX_BANDWIDTH_8MHZ: /* fall through */ + case DRX_BANDWIDTH_7MHZ: /* fall through */ + default: + return -EINVAL; + } + } + + /* For QAM annex A and annex C: + -check symbolrate and constellation + -derive bandwidth from symbolrate (input bandwidth is ignored) + */ +#ifndef DRXJ_VSB_ONLY + if ((standard == DRX_STANDARD_ITU_A) || + (standard == DRX_STANDARD_ITU_C)) { + struct drxuio_cfg uio_cfg = { DRX_UIO1, DRX_UIO_MODE_FIRMWARE_SAW }; + int bw_rolloff_factor = 0; + + bw_rolloff_factor = (standard == DRX_STANDARD_ITU_A) ? 115 : 113; + min_symbol_rate = DRXJ_QAM_SYMBOLRATE_MIN; + max_symbol_rate = DRXJ_QAM_SYMBOLRATE_MAX; + /* config SMA_TX pin to SAW switch mode */ + rc = ctrl_set_uio_cfg(demod, &uio_cfg); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - } - if ((*mode == DRX_POWER_UP)) { - /* Restore analog & pin configuartion */ + if (channel->symbolrate < min_symbol_rate || + channel->symbolrate > max_symbol_rate) { + return -EINVAL; + } - /* Initialize default AFE configuartion for VSB */ - drxj_reset_mode(ext_attr); - } else { - /* Power down to requested mode */ - /* Backup some register settings */ - /* Set pins with possible pull-ups connected to them in input mode */ - /* Analog power down */ - /* ADC power down */ - /* Power down device */ - /* stop all comm_exec */ - /* - Stop and power down previous standard - */ + switch (channel->constellation) { + case DRX_CONSTELLATION_QAM16: /* fall through */ + case DRX_CONSTELLATION_QAM32: /* fall through */ + case DRX_CONSTELLATION_QAM64: /* fall through */ + case DRX_CONSTELLATION_QAM128: /* fall through */ + case DRX_CONSTELLATION_QAM256: + bandwidth_temp = channel->symbolrate * bw_rolloff_factor; + bandwidth = bandwidth_temp / 100; - switch (ext_attr->standard) { - case DRX_STANDARD_ITU_A: - case DRX_STANDARD_ITU_B: - case DRX_STANDARD_ITU_C: - rc = power_down_qam(demod, true); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - break; - case DRX_STANDARD_8VSB: - rc = power_down_vsb(demod, true); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; + if ((bandwidth_temp % 100) >= 50) + bandwidth++; + + if (bandwidth <= 6100000) { + channel->bandwidth = DRX_BANDWIDTH_6MHZ; + } else if ((bandwidth > 6100000) + && (bandwidth <= 7100000)) { + channel->bandwidth = DRX_BANDWIDTH_7MHZ; + } else if (bandwidth > 7100000) { + channel->bandwidth = DRX_BANDWIDTH_8MHZ; } break; - case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_LP: /* fallthrough */ - case DRX_STANDARD_NTSC: /* fallthrough */ - case DRX_STANDARD_FM: - rc = power_down_atv(demod, ext_attr->standard, true); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } + default: + return -EINVAL; + } + } + + /* For QAM annex B: + -check constellation + */ + if (standard == DRX_STANDARD_ITU_B) { + switch (channel->constellation) { + case DRX_CONSTELLATION_AUTO: + case DRX_CONSTELLATION_QAM256: + case DRX_CONSTELLATION_QAM64: break; - case DRX_STANDARD_UNKNOWN: - /* Do nothing */ + default: + return -EINVAL; + } + + switch (channel->interleavemode) { + case DRX_INTERLEAVEMODE_I128_J1: + case DRX_INTERLEAVEMODE_I128_J1_V2: + case DRX_INTERLEAVEMODE_I128_J2: + case DRX_INTERLEAVEMODE_I64_J2: + case DRX_INTERLEAVEMODE_I128_J3: + case DRX_INTERLEAVEMODE_I32_J4: + case DRX_INTERLEAVEMODE_I128_J4: + case DRX_INTERLEAVEMODE_I16_J8: + case DRX_INTERLEAVEMODE_I128_J5: + case DRX_INTERLEAVEMODE_I8_J16: + case DRX_INTERLEAVEMODE_I128_J6: + case DRX_INTERLEAVEMODE_I128_J7: + case DRX_INTERLEAVEMODE_I128_J8: + case DRX_INTERLEAVEMODE_I12_J17: + case DRX_INTERLEAVEMODE_I5_J4: + case DRX_INTERLEAVEMODE_B52_M240: + case DRX_INTERLEAVEMODE_B52_M720: + case DRX_INTERLEAVEMODE_UNKNOWN: + case DRX_INTERLEAVEMODE_AUTO: break; - case DRX_STANDARD_AUTO: /* fallthrough */ default: - return -EIO; + return -EINVAL; } - ext_attr->standard = DRX_STANDARD_UNKNOWN; } - if (*mode != DRXJ_POWER_DOWN_MAIN_PATH) { - rc = drxj_dap_write_reg16(dev_addr, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; + if ((ext_attr->uio_sma_tx_mode) == DRX_UIO_MODE_FIRMWARE_SAW) { + /* SAW SW, user UIO is used for switchable SAW */ + struct drxuio_data uio1 = { DRX_UIO1, false }; + + switch (channel->bandwidth) { + case DRX_BANDWIDTH_8MHZ: + uio1.value = true; + break; + case DRX_BANDWIDTH_7MHZ: + uio1.value = false; + break; + case DRX_BANDWIDTH_6MHZ: + uio1.value = false; + break; + case DRX_BANDWIDTH_UNKNOWN: + default: + return -EINVAL; } - rc = drxj_dap_write_reg16(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY, 0); + + rc = ctrl_uio_write(demod, &uio1); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - - if ((*mode != DRX_POWER_UP)) { - /* Initialize HI, wakeup key especially before put IC to sleep */ - rc = init_hi(demod); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - ext_attr->hi_cfg_ctrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; - rc = hi_cfg_command(demod); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - } + } +#endif /* DRXJ_VSB_ONLY */ + rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; } - common_attr->current_power_mode = *mode; - - return 0; -rw_error: - return rc; -} - -#if 0 -/*============================================================================*/ - -/** -* \fn int ctrl_probe_device() -* \brief Probe device, check if it is present -* \param demod Pointer to demodulator instance. -* \return int. -* \retval 0 a drx39xxj device has been detected. -* \retval -EIO no drx39xxj device detected. -* -* This funtion can be caled before open() and after close(). -* -*/ - -static int ctrl_probe_device(struct drx_demod_instance *demod) -{ - enum drx_power_mode org_power_mode = DRX_POWER_UP; - int ret_status = 0; - struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL); - int rc; - - common_attr = (struct drx_common_attr *) demod->my_common_attr; - - if (common_attr->is_opened == false - || common_attr->current_power_mode != DRX_POWER_UP) { - struct i2c_device_addr *dev_addr = NULL; - enum drx_power_mode power_mode = DRX_POWER_UP; - u32 jtag = 0; - - dev_addr = demod->my_i2c_dev_addr; - - /* Remeber original power mode */ - org_power_mode = common_attr->current_power_mode; + tuner_freq_offset = 0; + intermediate_freq = demod->my_common_attr->intermediate_freq; - if (demod->my_common_attr->is_opened == false) { - rc = power_up_device(demod); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - common_attr->current_power_mode = DRX_POWER_UP; - } else { - /* Wake-up device, feedback from device */ - rc = ctrl_power_mode(demod, &power_mode); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - } - /* Initialize HI, wakeup key especially */ - rc = init_hi(demod); + /*== Setup demod for specific standard ====================================*/ + switch (standard) { + case DRX_STANDARD_8VSB: + if (channel->mirror == DRX_MIRROR_AUTO) + ext_attr->mirror = DRX_MIRROR_NO; + else + ext_attr->mirror = channel->mirror; + rc = set_vsb(demod); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - - /* Check device id */ - rc = drxdap_fasi_read_reg32(dev_addr, SIO_TOP_JTAGID_LO__A, &jtag, 0); + rc = set_frequency(demod, channel, tuner_freq_offset); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - jtag = (jtag >> 12) & 0xFFFF; - switch (jtag) { - case 0x3931: /* fallthrough */ - case 0x3932: /* fallthrough */ - case 0x3933: /* fallthrough */ - case 0x3934: /* fallthrough */ - case 0x3941: /* fallthrough */ - case 0x3942: /* fallthrough */ - case 0x3943: /* fallthrough */ - case 0x3944: /* fallthrough */ - case 0x3945: /* fallthrough */ - case 0x3946: - /* ok , do nothing */ - break; - default: - ret_status = -EIO; - break; - } - - /* Device was not opened, return to orginal powermode, - feedback from device */ - rc = ctrl_power_mode(demod, &org_power_mode); + break; +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: + rc = set_qam_channel(demod, channel, tuner_freq_offset); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - } else { - /* dummy read to make this function fail in case device - suddenly disappears after a succesful drx_open */ - do { - u16 dummy; - rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SCU_RAM_VERSION_HI__A, &dummy, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - } while (0); + break; +#endif + case DRX_STANDARD_UNKNOWN: + default: + return -EIO; } - return ret_status; + /* flag the packet error counter reset */ + ext_attr->reset_pkt_err_acc = true; + return 0; rw_error: - common_attr->current_power_mode = org_power_mode; return -EIO; } -#endif -/*============================================================================*/ -/*== CTRL Set/Get Config related functions ===================================*/ -/*============================================================================*/ +/*============================================================================= + ===== SigQuality() ========================================================== + ===========================================================================*/ + +static u16 +mer2indicator(u16 mer, u16 min_mer, u16 threshold_mer, u16 max_mer) +{ + u16 indicator = 0; + + if (mer < min_mer) { + indicator = 0; + } else if (mer < threshold_mer) { + if ((threshold_mer - min_mer) != 0) + indicator = 25 * (mer - min_mer) / (threshold_mer - min_mer); + } else if (mer < max_mer) { + if ((max_mer - threshold_mer) != 0) + indicator = 25 + 75 * (mer - threshold_mer) / (max_mer - threshold_mer); + else + indicator = 25; + } else { + indicator = 100; + } + + return indicator; +} -#if 0 -/*===== SigStrength() =========================================================*/ /** -* \fn int ctrl_sig_strength() -* \brief Retrieve signal strength. +* \fn int ctrl_sig_quality() +* \brief Retreive signal quality form device. * \param devmod Pointer to demodulator instance. -* \param sig_quality Pointer to signal strength data; range 0, .. , 100. +* \param sig_quality Pointer to signal quality data. * \return int. -* \retval 0 sig_strength contains valid data. -* \retval -EINVAL sig_strength is NULL. -* \retval -EIO Erroneous data, sig_strength contains invalid data. +* \retval 0 sig_quality contains valid data. +* \retval -EINVAL sig_quality is NULL. +* \retval -EIO Erroneous data, sig_quality contains invalid data. */ static int -ctrl_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength) +ctrl_sig_quality(struct drx_demod_instance *demod, struct drx_sig_quality *sig_quality) { + struct i2c_device_addr *dev_addr = NULL; struct drxj_data *ext_attr = NULL; - enum drx_standard standard = DRX_STANDARD_UNKNOWN; int rc; + enum drx_standard standard = DRX_STANDARD_UNKNOWN; + enum drx_lock_status lock_status = DRX_NOT_LOCKED; + u16 min_mer = 0; + u16 max_mer = 0; + u16 threshold_mer = 0; /* Check arguments */ - if ((sig_strength == NULL) || (demod == NULL)) + if ((sig_quality == NULL) || (demod == NULL)) return -EINVAL; ext_attr = (struct drxj_data *) demod->my_ext_attr; standard = ext_attr->standard; - *sig_strength = 0; - /* Signal strength indication for each standard */ + /* get basic information */ + dev_addr = demod->my_i2c_dev_addr; + rc = ctrl_lock_status(demod, &lock_status); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } switch (standard) { - case DRX_STANDARD_8VSB: /* fallthrough */ + case DRX_STANDARD_8VSB: +#ifdef DRXJ_SIGNAL_ACCUM_ERR + rc = get_acc_pkt_err(demod, &sig_quality->packet_error); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } +#else + rc = get_vsb_post_rs_pck_err(dev_addr, &sig_quality->packet_error); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } +#endif + if (lock_status != DRXJ_DEMOD_LOCK && lock_status != DRX_LOCKED) { + sig_quality->post_viterbi_ber = 500000; + sig_quality->MER = 20; + sig_quality->pre_viterbi_ber = 0; + } else { + /* PostViterbi is compute in steps of 10^(-6) */ + rc = get_vs_bpre_viterbi_ber(dev_addr, &sig_quality->pre_viterbi_ber); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = get_vs_bpost_viterbi_ber(dev_addr, &sig_quality->post_viterbi_ber); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = get_vsbmer(dev_addr, &sig_quality->MER); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + min_mer = 20; + max_mer = 360; + threshold_mer = 145; + sig_quality->post_reed_solomon_ber = 0; + sig_quality->scale_factor_ber = 1000000; + sig_quality->indicator = + mer2indicator(sig_quality->MER, min_mer, threshold_mer, + max_mer); + break; #ifndef DRXJ_VSB_ONLY - case DRX_STANDARD_ITU_A: /* fallthrough */ - case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: case DRX_STANDARD_ITU_C: -#endif - rc = get_sig_strength(demod, sig_strength); + rc = ctrl_get_qam_sig_quality(demod, sig_quality); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - break; - case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_LP: /* fallthrough */ - case DRX_STANDARD_NTSC: /* fallthrough */ - case DRX_STANDARD_FM: - rc = get_atv_sig_strength(demod, sig_strength); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; + if (lock_status != DRXJ_DEMOD_LOCK && lock_status != DRX_LOCKED) { + switch (ext_attr->constellation) { + case DRX_CONSTELLATION_QAM256: + sig_quality->MER = 210; + break; + case DRX_CONSTELLATION_QAM128: + sig_quality->MER = 180; + break; + case DRX_CONSTELLATION_QAM64: + sig_quality->MER = 150; + break; + case DRX_CONSTELLATION_QAM32: + sig_quality->MER = 120; + break; + case DRX_CONSTELLATION_QAM16: + sig_quality->MER = 90; + break; + default: + sig_quality->MER = 0; + return -EIO; + } + } + + switch (ext_attr->constellation) { + case DRX_CONSTELLATION_QAM256: + min_mer = 210; + threshold_mer = 270; + max_mer = 380; + break; + case DRX_CONSTELLATION_QAM64: + min_mer = 150; + threshold_mer = 210; + max_mer = 380; + break; + case DRX_CONSTELLATION_QAM128: + case DRX_CONSTELLATION_QAM32: + case DRX_CONSTELLATION_QAM16: + break; + default: + return -EIO; } + sig_quality->indicator = + mer2indicator(sig_quality->MER, min_mer, threshold_mer, + max_mer); break; - case DRX_STANDARD_UNKNOWN: /* fallthrough */ +#endif default: - return -EINVAL; + return -EIO; } - /* TODO */ - /* find out if signal strength is calculated in the same way for all standards */ return 0; rw_error: return -EIO; } /*============================================================================*/ -/** -* \fn int ctrl_get_cfg_oob_misc() -* \brief Get current state information of OOB. -* \param pointer to struct drxj_cfg_oob_misc. -* \return int. -* -*/ -static int -ctrl_get_cfg_oob_misc(struct drx_demod_instance *demod, struct drxj_cfg_oob_misc *misc) -{ - struct i2c_device_addr *dev_addr = NULL; - int rc; - u16 lock = 0U; - u16 state = 0U; - u16 data = 0U; - u16 digital_agc_mant = 0U; - u16 digital_agc_exp = 0U; - - /* check arguments */ - if (misc == NULL) - return -EINVAL; - - dev_addr = demod->my_i2c_dev_addr; - - /* TODO */ - /* check if the same registers are used for all standards (QAM/VSB/ATV) */ - rc = drxj_dap_read_reg16(dev_addr, ORX_NSU_TUN_IFGAIN_W__A, &misc->agc.IFAGC, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_read_reg16(dev_addr, ORX_NSU_TUN_RFGAIN_W__A, &misc->agc.RFAGC, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_read_reg16(dev_addr, ORX_FWP_SRC_DGN_W__A, &data, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - digital_agc_mant = data & ORX_FWP_SRC_DGN_W_MANT__M; - digital_agc_exp = (data & ORX_FWP_SRC_DGN_W_EXP__M) - >> ORX_FWP_SRC_DGN_W_EXP__B; - misc->agc.digital_agc = digital_agc_mant << digital_agc_exp; - - rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_ORX_SCU_LOCK__A, &lock, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - misc->ana_gain_lock = ((lock & 0x0001) ? true : false); - misc->dig_gain_lock = ((lock & 0x0002) ? true : false); - misc->freq_lock = ((lock & 0x0004) ? true : false); - misc->phase_lock = ((lock & 0x0008) ? true : false); - misc->sym_timing_lock = ((lock & 0x0010) ? true : false); - misc->eq_lock = ((lock & 0x0020) ? true : false); - - rc = drxj_dap_scu_atomic_read_reg16(dev_addr, SCU_RAM_ORX_SCU_STATE__A, &state, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - misc->state = (state >> 8) & 0xff; - - return 0; -rw_error: - return -EIO; -} /** -* \fn int ctrl_get_cfg_vsb_misc() -* \brief Get current state information of OOB. -* \param pointer to struct drxj_cfg_oob_misc. +* \fn int ctrl_lock_status() +* \brief Retreive lock status . +* \param dev_addr Pointer to demodulator device address. +* \param lock_stat Pointer to lock status structure. * \return int. * */ static int -ctrl_get_cfg_vsb_misc(struct drx_demod_instance *demod, struct drxj_cfg_vsb_misc *misc) +ctrl_lock_status(struct drx_demod_instance *demod, enum drx_lock_status *lock_stat) { + enum drx_standard standard = DRX_STANDARD_UNKNOWN; + struct drxj_data *ext_attr = NULL; struct i2c_device_addr *dev_addr = NULL; + struct drxjscu_cmd cmd_scu = { /* command */ 0, + /* parameter_len */ 0, + /* result_len */ 0, + /* *parameter */ NULL, + /* *result */ NULL + }; int rc; + u16 cmd_result[2] = { 0, 0 }; + u16 demod_lock = SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_DEMOD_LOCKED; /* check arguments */ - if (misc == NULL) + if ((demod == NULL) || (lock_stat == NULL)) return -EINVAL; dev_addr = demod->my_i2c_dev_addr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; + standard = ext_attr->standard; - rc = get_vsb_symb_err(dev_addr, &misc->symb_error); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - return 0; -rw_error: - return -EIO; -} - -/*============================================================================*/ - -/** -* \fn int ctrl_set_cfg_agc_if() -* \brief Set IF AGC. -* \param demod demod instance -* \param agc_settings If agc configuration -* \return int. -* -* Check arguments -* Dispatch handling to standard specific function. -* -*/ -static int -ctrl_set_cfg_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings) -{ - /* check arguments */ - if (agc_settings == NULL) - return -EINVAL; + *lock_stat = DRX_NOT_LOCKED; - switch (agc_settings->ctrl_mode) { - case DRX_AGC_CTRL_AUTO: /* fallthrough */ - case DRX_AGC_CTRL_USER: /* fallthrough */ - case DRX_AGC_CTRL_OFF: /* fallthrough */ + /* define the SCU command code */ + switch (standard) { + case DRX_STANDARD_8VSB: + cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB | + SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK; + demod_lock |= 0x6; break; - default: - return -EINVAL; - } - - /* Distpatch */ - switch (agc_settings->standard) { - case DRX_STANDARD_8VSB: /* fallthrough */ -#ifndef DRXJ_VSB_ONLY - case DRX_STANDARD_ITU_A: /* fallthrough */ - case DRX_STANDARD_ITU_B: /* fallthrough */ - case DRX_STANDARD_ITU_C: -#endif -#if 0 - case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_LP: /* fallthrough */ - case DRX_STANDARD_NTSC: /* fallthrough */ - case DRX_STANDARD_FM: -#endif - return set_agc_if(demod, agc_settings, true); - case DRX_STANDARD_UNKNOWN: - default: - return -EINVAL; - } - - return 0; -} - -/*============================================================================*/ - -/** -* \fn int ctrl_get_cfg_agc_if() -* \brief Retrieve IF AGC settings. -* \param demod demod instance -* \param agc_settings If agc configuration -* \return int. -* -* Check arguments -* Dispatch handling to standard specific function. -* -*/ -static int -ctrl_get_cfg_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings) -{ - /* check arguments */ - if (agc_settings == NULL) - return -EINVAL; - - /* Distpatch */ - switch (agc_settings->standard) { - case DRX_STANDARD_8VSB: /* fallthrough */ #ifndef DRXJ_VSB_ONLY - case DRX_STANDARD_ITU_A: /* fallthrough */ - case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: case DRX_STANDARD_ITU_C: + cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM | + SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK; + break; #endif -#if 0 - case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_LP: /* fallthrough */ - case DRX_STANDARD_NTSC: /* fallthrough */ - case DRX_STANDARD_FM: -#endif - return get_agc_if(demod, agc_settings); - case DRX_STANDARD_UNKNOWN: + case DRX_STANDARD_UNKNOWN: /* fallthrough */ default: - return -EINVAL; + return -EIO; } - return 0; -} - -/*============================================================================*/ - -/** -* \fn int ctrl_set_cfg_agc_rf() -* \brief Set RF AGC. -* \param demod demod instance -* \param agc_settings rf agc configuration -* \return int. -* -* Check arguments -* Dispatch handling to standard specific function. -* -*/ -static int -ctrl_set_cfg_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings) -{ - /* check arguments */ - if (agc_settings == NULL) - return -EINVAL; - - switch (agc_settings->ctrl_mode) { - case DRX_AGC_CTRL_AUTO: /* fallthrough */ - case DRX_AGC_CTRL_USER: /* fallthrough */ - case DRX_AGC_CTRL_OFF: - break; - default: - return -EINVAL; + /* define the SCU command paramters and execute the command */ + cmd_scu.parameter_len = 0; + cmd_scu.result_len = 2; + cmd_scu.parameter = NULL; + cmd_scu.result = cmd_result; + rc = scu_command(dev_addr, &cmd_scu); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; } - /* Distpatch */ - switch (agc_settings->standard) { - case DRX_STANDARD_8VSB: /* fallthrough */ -#ifndef DRXJ_VSB_ONLY - case DRX_STANDARD_ITU_A: /* fallthrough */ - case DRX_STANDARD_ITU_B: /* fallthrough */ - case DRX_STANDARD_ITU_C: -#endif - case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_LP: /* fallthrough */ - case DRX_STANDARD_NTSC: /* fallthrough */ - case DRX_STANDARD_FM: - return set_agc_rf(demod, agc_settings, true); - case DRX_STANDARD_UNKNOWN: - default: - return -EINVAL; + /* set the lock status */ + if (cmd_scu.result[1] < demod_lock) { + /* 0x0000 NOT LOCKED */ + *lock_stat = DRX_NOT_LOCKED; + } else if (cmd_scu.result[1] < SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_LOCKED) { + *lock_stat = DRXJ_DEMOD_LOCK; + } else if (cmd_scu.result[1] < + SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NEVER_LOCK) { + /* 0x8000 DEMOD + FEC LOCKED (system lock) */ + *lock_stat = DRX_LOCKED; + } else { + /* 0xC000 NEVER LOCKED */ + /* (system will never be able to lock to the signal) */ + *lock_stat = DRX_NEVER_LOCK; } return 0; +rw_error: + return -EIO; } /*============================================================================*/ /** -* \fn int ctrl_get_cfg_agc_rf() -* \brief Retrieve RF AGC settings. -* \param demod demod instance -* \param agc_settings Rf agc configuration +* \fn int ctrl_set_standard() +* \brief Set modulation standard to be used. +* \param standard Modulation standard. * \return int. * -* Check arguments -* Dispatch handling to standard specific function. +* Setup stuff for the desired demodulation standard. +* Disable and power down the previous selected demodulation standard * */ static int -ctrl_get_cfg_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings) +ctrl_set_standard(struct drx_demod_instance *demod, enum drx_standard *standard) { + struct drxj_data *ext_attr = NULL; + int rc; + enum drx_standard prev_standard; + /* check arguments */ - if (agc_settings == NULL) + if ((standard == NULL) || (demod == NULL)) return -EINVAL; - /* Distpatch */ - switch (agc_settings->standard) { - case DRX_STANDARD_8VSB: /* fallthrough */ + ext_attr = (struct drxj_data *) demod->my_ext_attr; + prev_standard = ext_attr->standard; + + /* + Stop and power down previous standard + */ + switch (prev_standard) { #ifndef DRXJ_VSB_ONLY case DRX_STANDARD_ITU_A: /* fallthrough */ case DRX_STANDARD_ITU_B: /* fallthrough */ case DRX_STANDARD_ITU_C: + rc = power_down_qam(demod, false); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; #endif - case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_LP: /* fallthrough */ - case DRX_STANDARD_NTSC: /* fallthrough */ - case DRX_STANDARD_FM: - return get_agc_rf(demod, agc_settings); + case DRX_STANDARD_8VSB: + rc = power_down_vsb(demod, false); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; case DRX_STANDARD_UNKNOWN: + /* Do nothing */ + break; + case DRX_STANDARD_AUTO: /* fallthrough */ + default: + return -EINVAL; + } + + /* + Initialize channel independent registers + Power up new standard + */ + ext_attr->standard = *standard; + + switch (*standard) { +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: + do { + u16 dummy; + rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SCU_RAM_VERSION_HI__A, &dummy, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } while (0); + break; +#endif + case DRX_STANDARD_8VSB: + rc = set_vsb_leak_n_gain(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; default: + ext_attr->standard = DRX_STANDARD_UNKNOWN; return -EINVAL; + break; } return 0; +rw_error: + /* Don't know what the standard is now ... try again */ + ext_attr->standard = DRX_STANDARD_UNKNOWN; + return -EIO; } /*============================================================================*/ +static void drxj_reset_mode(struct drxj_data *ext_attr) +{ + /* Initialize default AFE configuartion for QAM */ + if (ext_attr->has_lna) { + /* IF AGC off, PGA active */ +#ifndef DRXJ_VSB_ONLY + ext_attr->qam_if_agc_cfg.standard = DRX_STANDARD_ITU_B; + ext_attr->qam_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_OFF; + ext_attr->qam_pga_cfg = 140 + (11 * 13); +#endif + ext_attr->vsb_if_agc_cfg.standard = DRX_STANDARD_8VSB; + ext_attr->vsb_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_OFF; + ext_attr->vsb_pga_cfg = 140 + (11 * 13); + } else { + /* IF AGC on, PGA not active */ +#ifndef DRXJ_VSB_ONLY + ext_attr->qam_if_agc_cfg.standard = DRX_STANDARD_ITU_B; + ext_attr->qam_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; + ext_attr->qam_if_agc_cfg.min_output_level = 0; + ext_attr->qam_if_agc_cfg.max_output_level = 0x7FFF; + ext_attr->qam_if_agc_cfg.speed = 3; + ext_attr->qam_if_agc_cfg.top = 1297; + ext_attr->qam_pga_cfg = 140; +#endif + ext_attr->vsb_if_agc_cfg.standard = DRX_STANDARD_8VSB; + ext_attr->vsb_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; + ext_attr->vsb_if_agc_cfg.min_output_level = 0; + ext_attr->vsb_if_agc_cfg.max_output_level = 0x7FFF; + ext_attr->vsb_if_agc_cfg.speed = 3; + ext_attr->vsb_if_agc_cfg.top = 1024; + ext_attr->vsb_pga_cfg = 140; + } + /* TODO: remove min_output_level and max_output_level for both QAM and VSB after */ + /* mc has not used them */ +#ifndef DRXJ_VSB_ONLY + ext_attr->qam_rf_agc_cfg.standard = DRX_STANDARD_ITU_B; + ext_attr->qam_rf_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; + ext_attr->qam_rf_agc_cfg.min_output_level = 0; + ext_attr->qam_rf_agc_cfg.max_output_level = 0x7FFF; + ext_attr->qam_rf_agc_cfg.speed = 3; + ext_attr->qam_rf_agc_cfg.top = 9500; + ext_attr->qam_rf_agc_cfg.cut_off_current = 4000; + ext_attr->qam_pre_saw_cfg.standard = DRX_STANDARD_ITU_B; + ext_attr->qam_pre_saw_cfg.reference = 0x07; + ext_attr->qam_pre_saw_cfg.use_pre_saw = true; +#endif + /* Initialize default AFE configuartion for VSB */ + ext_attr->vsb_rf_agc_cfg.standard = DRX_STANDARD_8VSB; + ext_attr->vsb_rf_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; + ext_attr->vsb_rf_agc_cfg.min_output_level = 0; + ext_attr->vsb_rf_agc_cfg.max_output_level = 0x7FFF; + ext_attr->vsb_rf_agc_cfg.speed = 3; + ext_attr->vsb_rf_agc_cfg.top = 9500; + ext_attr->vsb_rf_agc_cfg.cut_off_current = 4000; + ext_attr->vsb_pre_saw_cfg.standard = DRX_STANDARD_8VSB; + ext_attr->vsb_pre_saw_cfg.reference = 0x07; + ext_attr->vsb_pre_saw_cfg.use_pre_saw = true; +} + /** -* \fn int ctrl_get_cfg_agc_internal() -* \brief Retrieve internal AGC value. -* \param demod demod instance -* \param u16 +* \fn int ctrl_power_mode() +* \brief Set the power mode of the device to the specified power mode +* \param demod Pointer to demodulator instance. +* \param mode Pointer to new power mode. * \return int. +* \retval 0 Success +* \retval -EIO I2C error or other failure +* \retval -EINVAL Invalid mode argument. * -* Check arguments -* Dispatch handling to standard specific function. * */ static int -ctrl_get_cfg_agc_internal(struct drx_demod_instance *demod, u16 *agc_internal) +ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode) { - struct i2c_device_addr *dev_addr = NULL; + struct drx_common_attr *common_attr = (struct drx_common_attr *) NULL; + struct drxj_data *ext_attr = (struct drxj_data *) NULL; + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; int rc; - enum drx_lock_status lock_status = DRX_NOT_LOCKED; - struct drxj_data *ext_attr = NULL; - u16 iqm_cf_scale_sh = 0; - u16 iqm_cf_power = 0; - u16 iqm_cf_amp = 0; - u16 iqm_cf_gain = 0; + u16 sio_cc_pwd_mode = 0; - /* check arguments */ - if (agc_internal == NULL) - return -EINVAL; - dev_addr = demod->my_i2c_dev_addr; + common_attr = (struct drx_common_attr *) demod->my_common_attr; ext_attr = (struct drxj_data *) demod->my_ext_attr; + dev_addr = demod->my_i2c_dev_addr; - rc = ctrl_lock_status(demod, &lock_status); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - if (lock_status != DRXJ_DEMOD_LOCK && lock_status != DRX_LOCKED) { - *agc_internal = 0; + /* Check arguments */ + if (mode == NULL) + return -EINVAL; + + /* If already in requested power mode, do nothing */ + if (common_attr->current_power_mode == *mode) return 0; - } - /* Distpatch */ - switch (ext_attr->standard) { - case DRX_STANDARD_8VSB: - iqm_cf_gain = 57; + switch (*mode) { + case DRX_POWER_UP: + case DRXJ_POWER_DOWN_MAIN_PATH: + sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_NONE; break; -#ifndef DRXJ_VSB_ONLY - case DRX_STANDARD_ITU_A: - case DRX_STANDARD_ITU_B: - case DRX_STANDARD_ITU_C: - switch (ext_attr->constellation) { - case DRX_CONSTELLATION_QAM256: - case DRX_CONSTELLATION_QAM128: - case DRX_CONSTELLATION_QAM32: - case DRX_CONSTELLATION_QAM16: - iqm_cf_gain = 57; + case DRXJ_POWER_DOWN_CORE: + sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_CLOCK; + break; + case DRXJ_POWER_DOWN_PLL: + sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_PLL; + break; + case DRX_POWER_DOWN: + sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_OSC; + break; + default: + /* Unknow sleep mode */ + return -EINVAL; + break; + } + + /* Check if device needs to be powered up */ + if ((common_attr->current_power_mode != DRX_POWER_UP)) { + rc = power_up_device(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + + if ((*mode == DRX_POWER_UP)) { + /* Restore analog & pin configuartion */ + + /* Initialize default AFE configuartion for VSB */ + drxj_reset_mode(ext_attr); + } else { + /* Power down to requested mode */ + /* Backup some register settings */ + /* Set pins with possible pull-ups connected to them in input mode */ + /* Analog power down */ + /* ADC power down */ + /* Power down device */ + /* stop all comm_exec */ + /* + Stop and power down previous standard + */ + + switch (ext_attr->standard) { + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: + rc = power_down_qam(demod, true); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + case DRX_STANDARD_8VSB: + rc = power_down_vsb(demod, true); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_LP: /* fallthrough */ + case DRX_STANDARD_NTSC: /* fallthrough */ + case DRX_STANDARD_FM: + rc = power_down_atv(demod, ext_attr->standard, true); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } break; - case DRX_CONSTELLATION_QAM64: - iqm_cf_gain = 56; + case DRX_STANDARD_UNKNOWN: + /* Do nothing */ break; + case DRX_STANDARD_AUTO: /* fallthrough */ default: return -EIO; } - break; -#endif - default: - return -EINVAL; + ext_attr->standard = DRX_STANDARD_UNKNOWN; } - rc = drxj_dap_read_reg16(dev_addr, IQM_CF_POW__A, &iqm_cf_power, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_read_reg16(dev_addr, IQM_CF_SCALE_SH__A, &iqm_cf_scale_sh, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - rc = drxj_dap_read_reg16(dev_addr, IQM_CF_AMP__A, &iqm_cf_amp, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; + if (*mode != DRXJ_POWER_DOWN_MAIN_PATH) { + rc = drxj_dap_write_reg16(dev_addr, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + if ((*mode != DRX_POWER_UP)) { + /* Initialize HI, wakeup key especially before put IC to sleep */ + rc = init_hi(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + ext_attr->hi_cfg_ctrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; + rc = hi_cfg_command(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } } - /* IQM_CF_PWR_CORRECTION_dB = 3; - P5dB =10*log10(IQM_CF_POW)+12-6*9-IQM_CF_PWR_CORRECTION_dB; */ - /* P4dB = P5dB -20*log10(IQM_CF_AMP)-6*10 - -IQM_CF_Gain_dB-18+6*(27-IQM_CF_SCALE_SH*2-10) - +6*7+10*log10(1+0.115/4); */ - /* PadcdB = P4dB +3 -6 +60; dBmV */ - *agc_internal = (u16) (log1_times100(iqm_cf_power) - - 2 * log1_times100(iqm_cf_amp) - - iqm_cf_gain - 120 * iqm_cf_scale_sh + 781); + + common_attr->current_power_mode = *mode; return 0; rw_error: - return -EIO; + return rc; } /*============================================================================*/ -#endif +/*== CTRL Set/Get Config related functions ===================================*/ +/*============================================================================*/ /** * \fn int ctrl_set_cfg_pre_saw() @@ -19269,17 +11180,6 @@ ctrl_set_cfg_pre_saw(struct drx_demod_instance *demod, struct drxj_cfg_pre_saw * ext_attr->qam_pre_saw_cfg = *pre_saw; break; #endif -#if 0 - case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_LP: /* fallthrough */ - case DRX_STANDARD_NTSC: /* fallthrough */ - case DRX_STANDARD_FM: - ext_attr->atv_pre_saw_cfg = *pre_saw; - break; -#endif default: return -EINVAL; } @@ -19372,419 +11272,6 @@ rw_error: /*============================================================================*/ -#if 0 -/** -* \fn int ctrl_get_cfg_pre_saw() -* \brief Get Pre-saw reference setting. -* \param demod demod instance -* \param u16 * -* \return int. -* -* Check arguments -* Dispatch handling to standard specific function. -* -*/ -static int -ctrl_get_cfg_pre_saw(struct drx_demod_instance *demod, struct drxj_cfg_pre_saw *pre_saw) -{ - struct drxj_data *ext_attr = NULL; - - /* check arguments */ - if (pre_saw == NULL) - return -EINVAL; - - ext_attr = (struct drxj_data *) demod->my_ext_attr; - - switch (pre_saw->standard) { - case DRX_STANDARD_8VSB: - *pre_saw = ext_attr->vsb_pre_saw_cfg; - break; -#ifndef DRXJ_VSB_ONLY - case DRX_STANDARD_ITU_A: /* fallthrough */ - case DRX_STANDARD_ITU_B: /* fallthrough */ - case DRX_STANDARD_ITU_C: - *pre_saw = ext_attr->qam_pre_saw_cfg; - break; -#endif - case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */ - case DRX_STANDARD_PAL_SECAM_LP: /* fallthrough */ - case DRX_STANDARD_NTSC: - ext_attr->atv_pre_saw_cfg.standard = DRX_STANDARD_NTSC; - *pre_saw = ext_attr->atv_pre_saw_cfg; - break; - case DRX_STANDARD_FM: - ext_attr->atv_pre_saw_cfg.standard = DRX_STANDARD_FM; - *pre_saw = ext_attr->atv_pre_saw_cfg; - break; - - default: - return -EINVAL; - } - - return 0; -} - -/*============================================================================*/ - -/** -* \fn int ctrl_get_cfg_afe_gain() -* \brief Get AFE Gain. -* \param demod demod instance -* \param u16 * -* \return int. -* -* Check arguments -* Dispatch handling to standard specific function. -* -*/ -static int -ctrl_get_cfg_afe_gain(struct drx_demod_instance *demod, struct drxj_cfg_afe_gain *afe_gain) -{ - struct drxj_data *ext_attr = NULL; - - /* check arguments */ - if (afe_gain == NULL) - return -EINVAL; - - ext_attr = demod->my_ext_attr; - - switch (afe_gain->standard) { - case DRX_STANDARD_8VSB: - afe_gain->gain = ext_attr->vsb_pga_cfg; - break; -#ifndef DRXJ_VSB_ONLY - case DRX_STANDARD_ITU_A: /* fallthrough */ - case DRX_STANDARD_ITU_B: /* fallthrough */ - case DRX_STANDARD_ITU_C: - afe_gain->gain = ext_attr->qam_pga_cfg; - break; -#endif - default: - return -EINVAL; - } - - return 0; -} - -/*============================================================================*/ - -/** -* \fn int ctrl_get_fec_meas_seq_count() -* \brief Get FEC measurement sequnce number. -* \param demod demod instance -* \param u16 * -* \return int. -* -* Check arguments -* Dispatch handling to standard specific function. -* -*/ -static int -ctrl_get_fec_meas_seq_count(struct drx_demod_instance *demod, u16 *fec_meas_seq_count) -{ - int rc; - /* check arguments */ - if (fec_meas_seq_count == NULL) - return -EINVAL; - - rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, fec_meas_seq_count, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - return 0; -rw_error: - return -EIO; -} - -/*============================================================================*/ - -/** -* \fn int ctrl_get_accum_cr_rs_cw_err() -* \brief Get accumulative corrected RS codeword number. -* \param demod demod instance -* \param u32 * -* \return int. -* -* Check arguments -* Dispatch handling to standard specific function. -* -*/ -static int -ctrl_get_accum_cr_rs_cw_err(struct drx_demod_instance *demod, u32 *accum_cr_rs_cw_err) -{ - int rc; - if (accum_cr_rs_cw_err == NULL) - return -EINVAL; - - rc = drxdap_fasi_read_reg32(demod->my_i2c_dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, accum_cr_rs_cw_err, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - - return 0; -rw_error: - return -EIO; -} - -/** -* \fn int ctrl_set_cfg() -* \brief Set 'some' configuration of the device. -* \param devmod Pointer to demodulator instance. -* \param config Pointer to configuration parameters (type and data). -* \return int. - -*/ -static int ctrl_set_cfg(struct drx_demod_instance *demod, struct drx_cfg *config) -{ - int rc; - - if (config == NULL) - return -EINVAL; - - do { - u16 dummy; - rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SCU_RAM_VERSION_HI__A, &dummy, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - } while (0); - switch (config->cfg_type) { - case DRX_CFG_MPEG_OUTPUT: - return ctrl_set_cfg_mpeg_output(demod, - (struct drx_cfg_mpeg_output *) config-> - cfg_data); - case DRX_CFG_PINS_SAFE_MODE: - return ctrl_set_cfg_pdr_safe_mode(demod, (bool *)config->cfg_data); - case DRXJ_CFG_AGC_RF: - return ctrl_set_cfg_agc_rf(demod, (struct drxj_cfg_agc *) config->cfg_data); - case DRXJ_CFG_AGC_IF: - return ctrl_set_cfg_agc_if(demod, (struct drxj_cfg_agc *) config->cfg_data); - case DRXJ_CFG_PRE_SAW: - return ctrl_set_cfg_pre_saw(demod, - (struct drxj_cfg_pre_saw *) config->cfg_data); - case DRXJ_CFG_AFE_GAIN: - return ctrl_set_cfg_afe_gain(demod, - (struct drxj_cfg_afe_gain *) config->cfg_data); - case DRXJ_CFG_SMART_ANT: - return ctrl_set_cfg_smart_ant(demod, - (struct drxj_cfg_smart_ant *) (config-> - cfg_data)); - case DRXJ_CFG_RESET_PACKET_ERR: - return ctrl_set_cfg_reset_pkt_err(demod); -#if 0 - case DRXJ_CFG_OOB_PRE_SAW: - return ctrl_set_cfg_oob_pre_saw(demod, (u16 *)(config->cfg_data)); - case DRXJ_CFG_OOB_LO_POW: - return ctrl_set_cfg_oob_lo_power(demod, - (enum drxj_cfg_oob_lo_power *) (config-> - cfg_data)); - case DRXJ_CFG_ATV_MISC: - return ctrl_set_cfg_atv_misc(demod, - (struct drxj_cfg_atv_misc *) config->cfg_data); - case DRXJ_CFG_ATV_EQU_COEF: - return ctrl_set_cfg_atv_equ_coef(demod, - (struct drxj_cfg_atv_equ_coef *) config-> - cfg_data); - case DRXJ_CFG_ATV_OUTPUT: - return ctrl_set_cfg_atv_output(demod, - (struct drxj_cfg_atv_output *) config-> - cfg_data); -#endif - case DRXJ_CFG_MPEG_OUTPUT_MISC: - return ctrl_set_cfg_mpeg_output_misc(demod, - (struct drxj_cfg_mpeg_output_misc *) - config->cfg_data); -#ifndef DRXJ_EXCLUDE_AUDIO - case DRX_CFG_AUD_VOLUME: - return aud_ctrl_set_cfg_volume(demod, - (struct drx_cfg_aud_volume *) config-> - cfg_data); - case DRX_CFG_I2S_OUTPUT: - return aud_ctrl_set_cfg_output_i2s(demod, - (struct drx_cfg_i2s_output *) config-> - cfg_data); - case DRX_CFG_AUD_AUTOSOUND: - return aud_ctr_setl_cfg_auto_sound(demod, (enum drx_cfg_aud_auto_sound *) - config->cfg_data); - case DRX_CFG_AUD_ASS_THRES: - return aud_ctrl_set_cfg_ass_thres(demod, (struct drx_cfg_aud_ass_thres *) - config->cfg_data); - case DRX_CFG_AUD_CARRIER: - return aud_ctrl_set_cfg_carrier(demod, - (struct drx_cfg_aud_carriers *) config-> - cfg_data); - case DRX_CFG_AUD_DEVIATION: - return aud_ctrl_set_cfg_dev(demod, - (enum drx_cfg_aud_deviation *) config-> - cfg_data); - case DRX_CFG_AUD_PRESCALE: - return aud_ctrl_set_cfg_prescale(demod, - (struct drx_cfg_aud_prescale *) config-> - cfg_data); - case DRX_CFG_AUD_MIXER: - return aud_ctrl_set_cfg_mixer(demod, - (struct drx_cfg_aud_mixer *) config->cfg_data); - case DRX_CFG_AUD_AVSYNC: - return aud_ctrl_set_cfg_av_sync(demod, - (enum drx_cfg_aud_av_sync *) config-> - cfg_data); - -#endif - default: - return -EINVAL; - } - - return 0; -rw_error: - return -EIO; -} - -/*============================================================================*/ - -/** -* \fn int ctrl_get_cfg() -* \brief Get 'some' configuration of the device. -* \param devmod Pointer to demodulator instance. -* \param config Pointer to configuration parameters (type and data). -* \return int. -*/ - -static int ctrl_get_cfg(struct drx_demod_instance *demod, struct drx_cfg *config) -{ - int rc; - - if (config == NULL) - return -EINVAL; - - do { - u16 dummy; - rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SCU_RAM_VERSION_HI__A, &dummy, 0); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } - } while (0); - - switch (config->cfg_type) { - case DRX_CFG_MPEG_OUTPUT: - return ctrl_get_cfg_mpeg_output(demod, - (struct drx_cfg_mpeg_output *) config-> - cfg_data); - case DRX_CFG_PINS_SAFE_MODE: - return ctrl_get_cfg_pdr_safe_mode(demod, (bool *)config->cfg_data); - case DRXJ_CFG_AGC_RF: - return ctrl_get_cfg_agc_rf(demod, (struct drxj_cfg_agc *) config->cfg_data); - case DRXJ_CFG_AGC_IF: - return ctrl_get_cfg_agc_if(demod, (struct drxj_cfg_agc *) config->cfg_data); - case DRXJ_CFG_AGC_INTERNAL: - return ctrl_get_cfg_agc_internal(demod, (u16 *)config->cfg_data); - case DRXJ_CFG_PRE_SAW: - return ctrl_get_cfg_pre_saw(demod, - (struct drxj_cfg_pre_saw *) config->cfg_data); - case DRXJ_CFG_AFE_GAIN: - return ctrl_get_cfg_afe_gain(demod, - (struct drxj_cfg_afe_gain *) config->cfg_data); - case DRXJ_CFG_ACCUM_CR_RS_CW_ERR: - return ctrl_get_accum_cr_rs_cw_err(demod, (u32 *)config->cfg_data); - case DRXJ_CFG_FEC_MERS_SEQ_COUNT: - return ctrl_get_fec_meas_seq_count(demod, (u16 *)config->cfg_data); - case DRXJ_CFG_VSB_MISC: - return ctrl_get_cfg_vsb_misc(demod, - (struct drxj_cfg_vsb_misc *) config->cfg_data); - case DRXJ_CFG_SYMBOL_CLK_OFFSET: - return ctrl_get_cfg_symbol_clock_offset(demod, - (s32 *)config->cfg_data); -#if 0 - case DRXJ_CFG_OOB_MISC: - return ctrl_get_cfg_oob_misc(demod, - (struct drxj_cfg_oob_misc *) config->cfg_data); - case DRXJ_CFG_OOB_PRE_SAW: - return ctrl_get_cfg_oob_pre_saw(demod, (u16 *)(config->cfg_data)); - case DRXJ_CFG_OOB_LO_POW: - return ctrl_get_cfg_oob_lo_power(demod, - (enum drxj_cfg_oob_lo_power *) (config-> - cfg_data)); - case DRXJ_CFG_ATV_EQU_COEF: - return ctrl_get_cfg_atv_equ_coef(demod, - (struct drxj_cfg_atv_equ_coef *) config-> - cfg_data); - case DRXJ_CFG_ATV_MISC: - return ctrl_get_cfg_atv_misc(demod, - (struct drxj_cfg_atv_misc *) config->cfg_data); - case DRXJ_CFG_ATV_OUTPUT: - return ctrl_get_cfg_atv_output(demod, - (struct drxj_cfg_atv_output *) config-> - cfg_data); - case DRXJ_CFG_ATV_AGC_STATUS: - return ctrl_get_cfg_atv_agc_status(demod, - (struct drxj_cfg_atv_agc_status *) config-> - cfg_data); -#endif - case DRXJ_CFG_MPEG_OUTPUT_MISC: - return ctrl_get_cfg_mpeg_output_misc(demod, - (struct drxj_cfg_mpeg_output_misc *) - config->cfg_data); - case DRXJ_CFG_HW_CFG: - return ctrl_get_cfg_hw_cfg(demod, - (struct drxj_cfg_hw_cfg *) config->cfg_data); -#ifndef DRXJ_EXCLUDE_AUDIO - case DRX_CFG_AUD_VOLUME: - return aud_ctrl_get_cfg_volume(demod, - (struct drx_cfg_aud_volume *) config-> - cfg_data); - case DRX_CFG_I2S_OUTPUT: - return aud_ctrl_get_cfg_output_i2s(demod, - (struct drx_cfg_i2s_output *) config-> - cfg_data); - - case DRX_CFG_AUD_RDS: - return aud_ctrl_get_cfg_rds(demod, - (struct drx_cfg_aud_rds *) config->cfg_data); - case DRX_CFG_AUD_AUTOSOUND: - return aud_ctrl_get_cfg_auto_sound(demod, - (enum drx_cfg_aud_auto_sound *) config-> - cfg_data); - case DRX_CFG_AUD_ASS_THRES: - return aud_ctrl_get_cfg_ass_thres(demod, - (struct drx_cfg_aud_ass_thres *) config-> - cfg_data); - case DRX_CFG_AUD_CARRIER: - return aud_ctrl_get_cfg_carrier(demod, - (struct drx_cfg_aud_carriers *) config-> - cfg_data); - case DRX_CFG_AUD_DEVIATION: - return aud_ctrl_get_cfg_dev(demod, - (enum drx_cfg_aud_deviation *) config-> - cfg_data); - case DRX_CFG_AUD_PRESCALE: - return aud_ctrl_get_cfg_prescale(demod, - (struct drx_cfg_aud_prescale *) config-> - cfg_data); - case DRX_CFG_AUD_MIXER: - return aud_ctrl_get_cfg_mixer(demod, - (struct drx_cfg_aud_mixer *) config->cfg_data); - case DRX_CFG_AUD_AVSYNC: - return aud_ctrl_get_cfg_av_sync(demod, - (enum drx_cfg_aud_av_sync *) config-> - cfg_data); -#endif - - default: - return -EINVAL; - } - - return 0; -rw_error: - return -EIO; -} -#endif /*============================================================================= ===== EXPORTED FUNCTIONS ====================================================*/ -- cgit v1.1 From 01473146394f28735778aefaf9faae109d6ee5f2 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sun, 9 Mar 2014 10:33:19 -0300 Subject: [media] drx-j: remove external symbols This driver doesn't export any external symbol, except for the attach() method. Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drxj.c | 12 ++++++------ drivers/media/dvb-frontends/drx39xyj/drxj.h | 30 ----------------------------- 2 files changed, 6 insertions(+), 36 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index e8c8908..828d052 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -561,7 +561,7 @@ static int drxdap_fasi_write_reg32(struct i2c_device_addr *dev_addr, u32 addr, u32 data, u32 flags); -struct drxj_data drxj_data_g = { +static struct drxj_data drxj_data_g = { false, /* has_lna : true if LNA (aka PGA) present */ false, /* has_oob : true if OOB supported */ false, /* has_ntsc: true if NTSC supported */ @@ -810,7 +810,7 @@ struct drxj_data drxj_data_g = { * \var drxj_default_addr_g * \brief Default I2C address and device identifier. */ -struct i2c_device_addr drxj_default_addr_g = { +static struct i2c_device_addr drxj_default_addr_g = { DRXJ_DEF_I2C_ADDR, /* i2c address */ DRXJ_DEF_DEMOD_DEV_ID /* device id */ }; @@ -819,7 +819,7 @@ struct i2c_device_addr drxj_default_addr_g = { * \var drxj_default_comm_attr_g * \brief Default common attributes of a drxj demodulator instance. */ -struct drx_common_attr drxj_default_comm_attr_g = { +static struct drx_common_attr drxj_default_comm_attr_g = { NULL, /* ucode file */ true, /* ucode verify switch */ {0}, /* version record */ @@ -890,7 +890,7 @@ struct drx_common_attr drxj_default_comm_attr_g = { * \var drxj_default_demod_g * \brief Default drxj demodulator instance. */ -struct drx_demod_instance drxj_default_demod_g = { +static struct drx_demod_instance drxj_default_demod_g = { &drxj_default_addr_g, /* i2c address & device id */ &drxj_default_comm_attr_g, /* demod common attributes */ &drxj_data_g /* demod device specific attributes */ @@ -11291,7 +11291,7 @@ static int drx_ctrl_u_code(struct drx_demod_instance *demod, * */ -int drxj_open(struct drx_demod_instance *demod) +static int drxj_open(struct drx_demod_instance *demod) { struct i2c_device_addr *dev_addr = NULL; struct drxj_data *ext_attr = NULL; @@ -11504,7 +11504,7 @@ rw_error: * \return Status_t Return status. * */ -int drxj_close(struct drx_demod_instance *demod) +static int drxj_close(struct drx_demod_instance *demod) { struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; int rc; diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.h b/drivers/media/dvb-frontends/drx39xyj/drxj.h index 6d46513..55ad535 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.h +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.h @@ -647,34 +647,4 @@ DEFINES (x == DRX_LOCK_STATE_2) ? "sync lock" : \ "(Invalid)") -/*------------------------------------------------------------------------- -ENUM --------------------------------------------------------------------------*/ - -/*------------------------------------------------------------------------- -STRUCTS --------------------------------------------------------------------------*/ - -/*------------------------------------------------------------------------- -Exported FUNCTIONS --------------------------------------------------------------------------*/ - - int drxj_open(struct drx_demod_instance *demod); - int drxj_close(struct drx_demod_instance *demod); - int drxj_ctrl(struct drx_demod_instance *demod, - u32 ctrl, void *ctrl_data); - -/*------------------------------------------------------------------------- -Exported GLOBAL VARIABLES --------------------------------------------------------------------------*/ - extern struct drx_access_func drx_dap_drxj_funct_g; - extern struct drx_demod_func drxj_functions_g; - extern struct drxj_data drxj_data_g; - extern struct i2c_device_addr drxj_default_addr_g; - extern struct drx_common_attr drxj_default_comm_attr_g; - extern struct drx_demod_instance drxj_default_demod_g; - -/*------------------------------------------------------------------------- -THE END --------------------------------------------------------------------------*/ #endif /* __DRXJ_H__ */ -- cgit v1.1 From 1e5ec31a462f6d02aba57dbdb9119478943fc2e8 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sun, 9 Mar 2014 10:33:54 -0300 Subject: [media] drx-j: Fix usage of drxj_close() This function is currently not used. However, it was meant to be called at device release. So, add it there. While here, remove the bad check, as reported by Dan, as smatch warning: drivers/media/dvb-frontends/drx39xyj/drxj.c:20041 drxj_close() warn: variable dereferenced before check 'demod' (see line 20036) Reported-by: Dan Carpenter Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drxj.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index 828d052..c5205d5 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -11510,8 +11510,7 @@ static int drxj_close(struct drx_demod_instance *demod) int rc; enum drx_power_mode power_mode = DRX_POWER_UP; - if ((demod == NULL) || - (demod->my_common_attr == NULL) || + if ((demod->my_common_attr == NULL) || (demod->my_ext_attr == NULL) || (demod->my_i2c_dev_addr == NULL) || (!demod->my_common_attr->is_opened)) { @@ -12218,6 +12217,8 @@ static void drx39xxj_release(struct dvb_frontend *fe) struct drx39xxj_state *state = fe->demodulator_priv; struct drx_demod_instance *demod = state->demod; + drxj_close(demod); + kfree(demod->my_ext_attr); kfree(demod->my_common_attr); kfree(demod->my_i2c_dev_addr); -- cgit v1.1 From 691cbbe354dc4eef4f196da0985da66b5172a49a Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sun, 9 Mar 2014 10:36:24 -0300 Subject: [media] drx-j: propagate returned error from request_firmware() Fix a smatch warning: drivers/media/dvb-frontends/drx39xyj/drxj.c:11711 drx_ctrl_u_code() info: why not propagate 'rc' from request_firmware() instead of (-2)? Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drxj.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index c5205d5..a26ddc9 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -11708,7 +11708,7 @@ static int drx_ctrl_u_code(struct drx_demod_instance *demod, rc = request_firmware(&fw, mc_file, demod->i2c->dev.parent); if (rc < 0) { pr_err("Couldn't read firmware %s\n", mc_file); - return -ENOENT; + return rc; } demod->firmware = fw; -- cgit v1.1 From 9c44a5d76edf135cbe59e4ef990c6d592ee7e378 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sun, 9 Mar 2014 10:47:01 -0300 Subject: [media] drx-j: get rid of some unused vars MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit As reported when compiled with W=1: drivers/media/dvb-frontends/drx39xyj/drxj.c: In function ‘ctrl_set_channel’: drivers/media/dvb-frontends/drx39xyj/drxj.c:10340:26: warning: variable ‘common_attr’ set but not used [-Wunused-but-set-variable] struct drx_common_attr *common_attr = NULL; ^ drivers/media/dvb-frontends/drx39xyj/drxj.c:10336:6: warning: variable ‘intermediate_freq’ set but not used [-Wunused-but-set-variable] s32 intermediate_freq = 0; Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drxj.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index a26ddc9..a36cfa6 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -10333,11 +10333,9 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) { int rc; s32 tuner_freq_offset = 0; - s32 intermediate_freq = 0; struct drxj_data *ext_attr = NULL; struct i2c_device_addr *dev_addr = NULL; enum drx_standard standard = DRX_STANDARD_UNKNOWN; - struct drx_common_attr *common_attr = NULL; #ifndef DRXJ_VSB_ONLY u32 min_symbol_rate = 0; u32 max_symbol_rate = 0; @@ -10348,7 +10346,6 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) if ((demod == NULL) || (channel == NULL)) return -EINVAL; - common_attr = (struct drx_common_attr *) demod->my_common_attr; dev_addr = demod->my_i2c_dev_addr; ext_attr = (struct drxj_data *) demod->my_ext_attr; standard = ext_attr->standard; @@ -10506,7 +10503,6 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) } tuner_freq_offset = 0; - intermediate_freq = demod->my_common_attr->intermediate_freq; /*== Setup demod for specific standard ====================================*/ switch (standard) { -- cgit v1.1 From 6f64c522bc8373bc2c0cf5078b9fa940f2d41099 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sun, 9 Mar 2014 17:30:48 -0300 Subject: [media] drx-j: Don't use "state" for DVB lock state State is already used on other places for the state struct. Don't use it here, to avoid troubles with latter patches. Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drxj.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index a36cfa6..7022a69 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -8861,7 +8861,7 @@ qam64auto(struct drx_demod_instance *demod, struct drx_sig_quality sig_quality; struct drxj_data *ext_attr = NULL; int rc; - u32 state = NO_LOCK; + u32 lck_state = NO_LOCK; u32 start_time = 0; u32 d_locked_time = 0; u32 timeout_ofs = 0; @@ -8871,7 +8871,7 @@ qam64auto(struct drx_demod_instance *demod, ext_attr = (struct drxj_data *) demod->my_ext_attr; *lock_status = DRX_NOT_LOCKED; start_time = jiffies_to_msecs(jiffies); - state = NO_LOCK; + lck_state = NO_LOCK; do { rc = ctrl_lock_status(demod, lock_status); if (rc != 0) { @@ -8879,7 +8879,7 @@ qam64auto(struct drx_demod_instance *demod, goto rw_error; } - switch (state) { + switch (lck_state) { case NO_LOCK: if (*lock_status == DRXJ_DEMOD_LOCK) { rc = ctrl_get_qam_sig_quality(demod, &sig_quality); @@ -8888,7 +8888,7 @@ qam64auto(struct drx_demod_instance *demod, goto rw_error; } if (sig_quality.MER > 208) { - state = DEMOD_LOCKED; + lck_state = DEMOD_LOCKED; /* some delay to see if fec_lock possible TODO find the right value */ timeout_ofs += DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME; /* see something, waiting longer */ d_locked_time = jiffies_to_msecs(jiffies); @@ -8909,7 +8909,7 @@ qam64auto(struct drx_demod_instance *demod, pr_err("error %d\n", rc); goto rw_error; } - state = SYNC_FLIPPED; + lck_state = SYNC_FLIPPED; msleep(10); } break; @@ -8934,7 +8934,7 @@ qam64auto(struct drx_demod_instance *demod, pr_err("error %d\n", rc); goto rw_error; } - state = SPEC_MIRRORED; + lck_state = SPEC_MIRRORED; /* reset timer TODO: still need 500ms? */ start_time = d_locked_time = jiffies_to_msecs(jiffies); @@ -9008,7 +9008,7 @@ qam256auto(struct drx_demod_instance *demod, struct drx_sig_quality sig_quality; struct drxj_data *ext_attr = NULL; int rc; - u32 state = NO_LOCK; + u32 lck_state = NO_LOCK; u32 start_time = 0; u32 d_locked_time = 0; u32 timeout_ofs = DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME; @@ -9017,14 +9017,14 @@ qam256auto(struct drx_demod_instance *demod, ext_attr = (struct drxj_data *) demod->my_ext_attr; *lock_status = DRX_NOT_LOCKED; start_time = jiffies_to_msecs(jiffies); - state = NO_LOCK; + lck_state = NO_LOCK; do { rc = ctrl_lock_status(demod, lock_status); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - switch (state) { + switch (lck_state) { case NO_LOCK: if (*lock_status == DRXJ_DEMOD_LOCK) { rc = ctrl_get_qam_sig_quality(demod, &sig_quality); @@ -9033,7 +9033,7 @@ qam256auto(struct drx_demod_instance *demod, goto rw_error; } if (sig_quality.MER > 268) { - state = DEMOD_LOCKED; + lck_state = DEMOD_LOCKED; timeout_ofs += DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME; /* see something, wait longer */ d_locked_time = jiffies_to_msecs(jiffies); } @@ -9050,7 +9050,7 @@ qam256auto(struct drx_demod_instance *demod, pr_err("error %d\n", rc); goto rw_error; } - state = SPEC_MIRRORED; + lck_state = SPEC_MIRRORED; /* reset timer TODO: still need 300ms? */ start_time = jiffies_to_msecs(jiffies); timeout_ofs = -DRXJ_QAM_MAX_WAITTIME / 2; -- cgit v1.1 From 80e5ed14e12d4452538c0492a560ab9a0294a850 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sun, 9 Mar 2014 17:37:27 -0300 Subject: [media] drx-j: re-add get_sig_strength() We'll need to use this function. Restore it from the git history. This function will be used on the next patch. Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drxj.c | 77 +++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index 7022a69..ca807b1 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -9352,6 +9352,83 @@ rw_error: /*============================================================================*/ /** + * \fn int get_sig_strength() + * \brief Retrieve signal strength for VSB and QAM. + * \param demod Pointer to demod instance + * \param u16-t Pointer to signal strength data; range 0, .. , 100. + * \return int. + * \retval 0 sig_strength contains valid data. + * \retval -EINVAL sig_strength is NULL. + * \retval -EIO Erroneous data, sig_strength contains invalid data. + */ +#define DRXJ_AGC_TOP 0x2800 +#define DRXJ_AGC_SNS 0x1600 +#define DRXJ_RFAGC_MAX 0x3fff +#define DRXJ_RFAGC_MIN 0x800 + +static int get_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength) +{ + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + int rc; + u16 rf_gain = 0; + u16 if_gain = 0; + u16 if_agc_sns = 0; + u16 if_agc_top = 0; + u16 rf_agc_max = 0; + u16 rf_agc_min = 0; + + rc = drxj_dap_read_reg16(dev_addr, IQM_AF_AGC_IF__A, &if_gain, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + if_gain &= IQM_AF_AGC_IF__M; + rc = drxj_dap_read_reg16(dev_addr, IQM_AF_AGC_RF__A, &rf_gain, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rf_gain &= IQM_AF_AGC_RF__M; + + if_agc_sns = DRXJ_AGC_SNS; + if_agc_top = DRXJ_AGC_TOP; + rf_agc_max = DRXJ_RFAGC_MAX; + rf_agc_min = DRXJ_RFAGC_MIN; + + if (if_gain > if_agc_top) { + if (rf_gain > rf_agc_max) + *sig_strength = 100; + else if (rf_gain > rf_agc_min) { + if (rf_agc_max == rf_agc_min) { + pr_err("error: rf_agc_max == rf_agc_min\n"); + return -EIO; + } + *sig_strength = + 75 + 25 * (rf_gain - rf_agc_min) / (rf_agc_max - + rf_agc_min); + } else + *sig_strength = 75; + } else if (if_gain > if_agc_sns) { + if (if_agc_top == if_agc_sns) { + pr_err("error: if_agc_top == if_agc_sns\n"); + return -EIO; + } + *sig_strength = + 20 + 55 * (if_gain - if_agc_sns) / (if_agc_top - if_agc_sns); + } else { + if (!if_agc_sns) { + pr_err("error: if_agc_sns is zero!\n"); + return -EIO; + } + *sig_strength = (20 * if_gain / if_agc_sns); + } + + return 0; + rw_error: + return -EIO; +} + +/** * \fn int ctrl_get_qam_sig_quality() * \brief Retreive QAM signal quality from device. * \param devmod Pointer to demodulator instance. -- cgit v1.1 From 03fdfbfd3b5944bfd210541a83c9b222e2c20920 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sun, 9 Mar 2014 17:46:01 -0300 Subject: [media] drx-j: Prepare to use DVBv5 stats Convert the stats internally to use DVBv5. For now, it will keep showing everything via DVBv3 API only, as the .len value were not initialized. That allows testing if the new stats code didn't break anything. A latter patch will add the final bits for the DVBv5 stats to fully work. Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drx_driver.h | 24 -- drivers/media/dvb-frontends/drx39xyj/drxj.c | 321 +++++++++------------- 2 files changed, 125 insertions(+), 220 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h index e54eb35..9076bf2 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h @@ -1033,30 +1033,6 @@ struct drx_channel { /*========================================*/ -/** -* \struct struct drx_sig_quality * Signal quality metrics. -* -* Used by DRX_CTRL_SIG_QUALITY. -*/ -struct drx_sig_quality { - u16 MER; /**< in steps of 0.1 dB */ - u32 pre_viterbi_ber; - /**< in steps of 1/scale_factor_ber */ - u32 post_viterbi_ber; - /**< in steps of 1/scale_factor_ber */ - u32 scale_factor_ber; - /**< scale factor for BER */ - u16 packet_error; - /**< number of packet errors */ - u32 post_reed_solomon_ber; - /**< in steps of 1/scale_factor_ber */ - u32 pre_ldpc_ber; - /**< in steps of 1/scale_factor_ber */ - u32 aver_iter;/**< in steps of 0.01 */ - u16 indicator; - /**< indicative signal quality low=0..100=high */ -}; - enum drx_cfg_sqi_speed { DRX_SQI_SPEED_FAST = 0, DRX_SQI_SPEED_MEDIUM, diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index ca807b1..6005e34 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -8656,10 +8656,12 @@ rw_error: } /*============================================================================*/ -static int -ctrl_get_qam_sig_quality(struct drx_demod_instance *demod, struct drx_sig_quality *sig_quality); +static int ctrl_get_qam_sig_quality(struct drx_demod_instance *demod); + static int qam_flip_spec(struct drx_demod_instance *demod, struct drx_channel *channel) { + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + struct drxj_data *ext_attr = demod->my_ext_attr; int rc; u32 iqm_fs_rate_ofs = 0; u32 iqm_fs_rate_lo = 0; @@ -8669,11 +8671,6 @@ static int qam_flip_spec(struct drx_demod_instance *demod, struct drx_channel *c u16 fsm_state = 0; int i = 0; int ofsofs = 0; - struct i2c_device_addr *dev_addr = NULL; - struct drxj_data *ext_attr = NULL; - - dev_addr = demod->my_i2c_dev_addr; - ext_attr = (struct drxj_data *) demod->my_ext_attr; /* Silence the controlling of lc, equ, and the acquisition state machine */ rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, &qam_ctl_ena, 0); @@ -8858,8 +8855,10 @@ qam64auto(struct drx_demod_instance *demod, struct drx_channel *channel, s32 tuner_freq_offset, enum drx_lock_status *lock_status) { - struct drx_sig_quality sig_quality; - struct drxj_data *ext_attr = NULL; + struct drxj_data *ext_attr = demod->my_ext_attr; + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + struct drx39xxj_state *state = dev_addr->user_data; + struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache; int rc; u32 lck_state = NO_LOCK; u32 start_time = 0; @@ -8868,7 +8867,6 @@ qam64auto(struct drx_demod_instance *demod, u16 data = 0; /* external attributes for storing aquired channel constellation */ - ext_attr = (struct drxj_data *) demod->my_ext_attr; *lock_status = DRX_NOT_LOCKED; start_time = jiffies_to_msecs(jiffies); lck_state = NO_LOCK; @@ -8882,12 +8880,12 @@ qam64auto(struct drx_demod_instance *demod, switch (lck_state) { case NO_LOCK: if (*lock_status == DRXJ_DEMOD_LOCK) { - rc = ctrl_get_qam_sig_quality(demod, &sig_quality); + rc = ctrl_get_qam_sig_quality(demod); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - if (sig_quality.MER > 208) { + if (p->cnr.stat[0].svalue > 20800) { lck_state = DEMOD_LOCKED; /* some delay to see if fec_lock possible TODO find the right value */ timeout_ofs += DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME; /* see something, waiting longer */ @@ -8951,12 +8949,12 @@ qam64auto(struct drx_demod_instance *demod, if ((*lock_status == DRXJ_DEMOD_LOCK) && /* still demod_lock in 150ms */ ((jiffies_to_msecs(jiffies) - d_locked_time) > DRXJ_QAM_FEC_LOCK_WAITTIME)) { - rc = ctrl_get_qam_sig_quality(demod, &sig_quality); + rc = ctrl_get_qam_sig_quality(demod); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - if (sig_quality.MER > 208) { + if (p->cnr.stat[0].svalue > 20800) { rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0); if (rc != 0) { pr_err("error %d\n", rc); @@ -9005,8 +9003,10 @@ qam256auto(struct drx_demod_instance *demod, struct drx_channel *channel, s32 tuner_freq_offset, enum drx_lock_status *lock_status) { - struct drx_sig_quality sig_quality; - struct drxj_data *ext_attr = NULL; + struct drxj_data *ext_attr = demod->my_ext_attr; + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + struct drx39xxj_state *state = dev_addr->user_data; + struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache; int rc; u32 lck_state = NO_LOCK; u32 start_time = 0; @@ -9014,7 +9014,6 @@ qam256auto(struct drx_demod_instance *demod, u32 timeout_ofs = DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME; /* external attributes for storing aquired channel constellation */ - ext_attr = (struct drxj_data *) demod->my_ext_attr; *lock_status = DRX_NOT_LOCKED; start_time = jiffies_to_msecs(jiffies); lck_state = NO_LOCK; @@ -9027,12 +9026,12 @@ qam256auto(struct drx_demod_instance *demod, switch (lck_state) { case NO_LOCK: if (*lock_status == DRXJ_DEMOD_LOCK) { - rc = ctrl_get_qam_sig_quality(demod, &sig_quality); + rc = ctrl_get_qam_sig_quality(demod); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - if (sig_quality.MER > 268) { + if (p->cnr.stat[0].svalue > 26800) { lck_state = DEMOD_LOCKED; timeout_ofs += DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME; /* see something, wait longer */ d_locked_time = jiffies_to_msecs(jiffies); @@ -9441,13 +9440,15 @@ static int get_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength) * Pre-condition: Device must be started and in lock. */ static int -ctrl_get_qam_sig_quality(struct drx_demod_instance *demod, struct drx_sig_quality *sig_quality) +ctrl_get_qam_sig_quality(struct drx_demod_instance *demod) { - struct i2c_device_addr *dev_addr = NULL; - struct drxj_data *ext_attr = NULL; - int rc; - enum drx_modulation constellation = DRX_CONSTELLATION_UNKNOWN; + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + struct drxj_data *ext_attr = demod->my_ext_attr; + struct drx39xxj_state *state = dev_addr->user_data; + struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache; struct drxjrs_errors measuredrs_errors = { 0, 0, 0, 0, 0 }; + enum drx_modulation constellation = ext_attr->constellation; + int rc; u32 pre_bit_err_rs = 0; /* pre RedSolomon Bit Error Rate */ u32 post_bit_err_rs = 0; /* post RedSolomon Bit Error Rate */ @@ -9473,11 +9474,6 @@ ctrl_get_qam_sig_quality(struct drx_demod_instance *demod, struct drx_sig_qualit u16 qam_vd_period = 0; /* Viterbi Measurement period */ u32 vd_bit_cnt = 0; /* ViterbiDecoder Bit Count */ - /* get device basic information */ - dev_addr = demod->my_i2c_dev_addr; - ext_attr = (struct drxj_data *) demod->my_ext_attr; - constellation = ext_attr->constellation; - /* read the physical registers */ /* Get the RS error data */ rc = get_qamrs_err_count(dev_addr, &measuredrs_errors); @@ -9605,26 +9601,43 @@ ctrl_get_qam_sig_quality(struct drx_demod_instance *demod, struct drx_sig_qualit qam_post_rs_ber = e / m; /* fill signal quality data structure */ - sig_quality->MER = ((u16) qam_sl_mer); + p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER; + p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; + p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER; + p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; + p->block_error.stat[0].scale = FE_SCALE_COUNTER; + p->cnr.stat[0].scale = FE_SCALE_DECIBEL; + + p->cnr.stat[0].svalue = ((u16) qam_sl_mer) * 100; if (ext_attr->standard == DRX_STANDARD_ITU_B) - sig_quality->pre_viterbi_ber = qam_vd_ser; + p->pre_bit_error.stat[0].uvalue += qam_vd_ser; else - sig_quality->pre_viterbi_ber = qam_pre_rs_ber; - sig_quality->post_viterbi_ber = qam_pre_rs_ber; - sig_quality->post_reed_solomon_ber = qam_post_rs_ber; - sig_quality->scale_factor_ber = ((u32) 1000000); + p->pre_bit_error.stat[0].uvalue += qam_pre_rs_ber; + + p->post_bit_error.stat[0].uvalue = qam_post_rs_ber; + + p->pre_bit_count.stat[0].uvalue += 1000000; + p->post_bit_count.stat[0].uvalue += 1000000; + + p->block_error.stat[0].uvalue += pkt_errs; + #ifdef DRXJ_SIGNAL_ACCUM_ERR rc = get_acc_pkt_err(demod, &sig_quality->packet_error); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } -#else - sig_quality->packet_error = ((u16) pkt_errs); #endif return 0; rw_error: + p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + return -EIO; } @@ -10627,28 +10640,6 @@ rw_error: ===== SigQuality() ========================================================== ===========================================================================*/ -static u16 -mer2indicator(u16 mer, u16 min_mer, u16 threshold_mer, u16 max_mer) -{ - u16 indicator = 0; - - if (mer < min_mer) { - indicator = 0; - } else if (mer < threshold_mer) { - if ((threshold_mer - min_mer) != 0) - indicator = 25 * (mer - min_mer) / (threshold_mer - min_mer); - } else if (mer < max_mer) { - if ((max_mer - threshold_mer) != 0) - indicator = 25 + 75 * (mer - threshold_mer) / (max_mer - threshold_mer); - else - indicator = 25; - } else { - indicator = 100; - } - - return indicator; -} - /** * \fn int ctrl_sig_quality() * \brief Retreive signal quality form device. @@ -10661,130 +10652,94 @@ mer2indicator(u16 mer, u16 min_mer, u16 threshold_mer, u16 max_mer) */ static int -ctrl_sig_quality(struct drx_demod_instance *demod, struct drx_sig_quality *sig_quality) +ctrl_sig_quality(struct drx_demod_instance *demod, + enum drx_lock_status lock_status) { - struct i2c_device_addr *dev_addr = NULL; - struct drxj_data *ext_attr = NULL; + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + struct drxj_data *ext_attr = demod->my_ext_attr; + struct drx39xxj_state *state = dev_addr->user_data; + struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache; + enum drx_standard standard = ext_attr->standard; int rc; - enum drx_standard standard = DRX_STANDARD_UNKNOWN; - enum drx_lock_status lock_status = DRX_NOT_LOCKED; - u16 min_mer = 0; - u16 max_mer = 0; - u16 threshold_mer = 0; - - /* Check arguments */ - if ((sig_quality == NULL) || (demod == NULL)) - return -EINVAL; + u32 ber; + u16 pkt, mer, strength; - ext_attr = (struct drxj_data *) demod->my_ext_attr; - standard = ext_attr->standard; - - /* get basic information */ - dev_addr = demod->my_i2c_dev_addr; - rc = ctrl_lock_status(demod, &lock_status); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; + rc = get_sig_strength(demod, &strength); + if (rc < 0) { + pr_err("error getting signal strength %d\n", rc); + p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + } else { + p->strength.stat[0].scale = FE_SCALE_RELATIVE; + p->strength.stat[0].uvalue = 65535UL * strength/ 100; } + switch (standard) { case DRX_STANDARD_8VSB: #ifdef DRXJ_SIGNAL_ACCUM_ERR - rc = get_acc_pkt_err(demod, &sig_quality->packet_error); - if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; - } -#else - rc = get_vsb_post_rs_pck_err(dev_addr, &sig_quality->packet_error); + rc = get_acc_pkt_err(demod, &pkt); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } #endif if (lock_status != DRXJ_DEMOD_LOCK && lock_status != DRX_LOCKED) { - sig_quality->post_viterbi_ber = 500000; - sig_quality->MER = 20; - sig_quality->pre_viterbi_ber = 0; + p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; } else { + rc = get_vsb_post_rs_pck_err(dev_addr, &pkt); + if (rc != 0) { + pr_err("error %d getting UCB\n", rc); + p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + } else { + p->block_error.stat[0].scale = FE_SCALE_COUNTER; + p->block_error.stat[0].uvalue += pkt; + } + /* PostViterbi is compute in steps of 10^(-6) */ - rc = get_vs_bpre_viterbi_ber(dev_addr, &sig_quality->pre_viterbi_ber); + rc = get_vs_bpre_viterbi_ber(dev_addr, &ber); if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d getting pre-ber\n", rc); + p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + } else { + p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER; + p->pre_bit_error.stat[0].uvalue += ber; + p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER; + p->pre_bit_count.stat[0].uvalue += 1000000; } - rc = get_vs_bpost_viterbi_ber(dev_addr, &sig_quality->post_viterbi_ber); + + rc = get_vs_bpost_viterbi_ber(dev_addr, &ber); if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d getting post-ber\n", rc); + p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + } else { + p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; + p->post_bit_error.stat[0].uvalue += ber; + p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; + p->post_bit_count.stat[0].uvalue += 1000000; } - rc = get_vsbmer(dev_addr, &sig_quality->MER); + rc = get_vsbmer(dev_addr, &mer); if (rc != 0) { - pr_err("error %d\n", rc); - goto rw_error; + pr_err("error %d getting MER\n", rc); + p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + } else { + p->cnr.stat[0].svalue = mer * 100; + p->cnr.stat[0].scale = FE_SCALE_DECIBEL; } } - min_mer = 20; - max_mer = 360; - threshold_mer = 145; - sig_quality->post_reed_solomon_ber = 0; - sig_quality->scale_factor_ber = 1000000; - sig_quality->indicator = - mer2indicator(sig_quality->MER, min_mer, threshold_mer, - max_mer); break; #ifndef DRXJ_VSB_ONLY case DRX_STANDARD_ITU_A: case DRX_STANDARD_ITU_B: case DRX_STANDARD_ITU_C: - rc = ctrl_get_qam_sig_quality(demod, sig_quality); + rc = ctrl_get_qam_sig_quality(demod); if (rc != 0) { pr_err("error %d\n", rc); goto rw_error; } - if (lock_status != DRXJ_DEMOD_LOCK && lock_status != DRX_LOCKED) { - switch (ext_attr->constellation) { - case DRX_CONSTELLATION_QAM256: - sig_quality->MER = 210; - break; - case DRX_CONSTELLATION_QAM128: - sig_quality->MER = 180; - break; - case DRX_CONSTELLATION_QAM64: - sig_quality->MER = 150; - break; - case DRX_CONSTELLATION_QAM32: - sig_quality->MER = 120; - break; - case DRX_CONSTELLATION_QAM16: - sig_quality->MER = 90; - break; - default: - sig_quality->MER = 0; - return -EIO; - } - } - - switch (ext_attr->constellation) { - case DRX_CONSTELLATION_QAM256: - min_mer = 210; - threshold_mer = 270; - max_mer = 380; - break; - case DRX_CONSTELLATION_QAM64: - min_mer = 150; - threshold_mer = 210; - max_mer = 380; - break; - case DRX_CONSTELLATION_QAM128: - case DRX_CONSTELLATION_QAM32: - case DRX_CONSTELLATION_QAM16: - break; - default: - return -EIO; - } - sig_quality->indicator = - mer2indicator(sig_quality->MER, min_mer, threshold_mer, - max_mer); break; #endif default: @@ -11997,81 +11952,61 @@ static int drx39xxj_read_status(struct dvb_frontend *fe, fe_status_t *status) default: pr_err("Lock state unknown %d\n", lock_status); } + ctrl_sig_quality(demod, lock_status); return 0; } static int drx39xxj_read_ber(struct dvb_frontend *fe, u32 *ber) { - struct drx39xxj_state *state = fe->demodulator_priv; - struct drx_demod_instance *demod = state->demod; - int result; - struct drx_sig_quality sig_quality; + struct dtv_frontend_properties *p = &fe->dtv_property_cache; - result = ctrl_sig_quality(demod, &sig_quality); - if (result != 0) { - pr_err("drx39xxj: could not get ber!\n"); + if (p->pre_bit_error.stat[0].scale == FE_SCALE_NOT_AVAILABLE) { *ber = 0; return 0; } - *ber = sig_quality.post_reed_solomon_ber; + *ber = p->pre_bit_error.stat[0].uvalue; return 0; } static int drx39xxj_read_signal_strength(struct dvb_frontend *fe, u16 *strength) { - struct drx39xxj_state *state = fe->demodulator_priv; - struct drx_demod_instance *demod = state->demod; - int result; - struct drx_sig_quality sig_quality; + struct dtv_frontend_properties *p = &fe->dtv_property_cache; - result = ctrl_sig_quality(demod, &sig_quality); - if (result != 0) { - pr_err("drx39xxj: could not get signal strength!\n"); + if (p->strength.stat[0].scale == FE_SCALE_NOT_AVAILABLE) { *strength = 0; return 0; } - /* 1-100% scaled to 0-65535 */ - *strength = (sig_quality.indicator * 65535 / 100); + *strength = p->strength.stat[0].uvalue; return 0; } static int drx39xxj_read_snr(struct dvb_frontend *fe, u16 *snr) { - struct drx39xxj_state *state = fe->demodulator_priv; - struct drx_demod_instance *demod = state->demod; - int result; - struct drx_sig_quality sig_quality; + struct dtv_frontend_properties *p = &fe->dtv_property_cache; - result = ctrl_sig_quality(demod, &sig_quality); - if (result != 0) { - pr_err("drx39xxj: could not read snr!\n"); + if (p->cnr.stat[0].scale == FE_SCALE_NOT_AVAILABLE) { *snr = 0; return 0; } - *snr = sig_quality.MER; + *snr = p->cnr.stat[0].svalue / 10; return 0; } -static int drx39xxj_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) +static int drx39xxj_read_ucblocks(struct dvb_frontend *fe, u32 *ucb) { - struct drx39xxj_state *state = fe->demodulator_priv; - struct drx_demod_instance *demod = state->demod; - int result; - struct drx_sig_quality sig_quality; + struct dtv_frontend_properties *p = &fe->dtv_property_cache; - result = ctrl_sig_quality(demod, &sig_quality); - if (result != 0) { - pr_err("drx39xxj: could not get uc blocks!\n"); - *ucblocks = 0; + if (p->block_error.stat[0].scale == FE_SCALE_NOT_AVAILABLE) { + *ucb = 0; return 0; } - *ucblocks = sig_quality.packet_error; + *ucb = p->block_error.stat[0].uvalue; return 0; } @@ -12178,15 +12113,9 @@ static int drx39xxj_set_frontend(struct dvb_frontend *fe) pr_err("Failed to disable LNA!\n"); return 0; } -#ifdef DJH_DEBUG - for (i = 0; i < 2000; i++) { - fe_status_t status; - drx39xxj_read_status(fe, &status); - pr_debug("i=%d status=%d\n", i, status); - msleep(100); - i += 100; - } -#endif + + /* After set_frontend, except for strength, stats aren't available */ + p->strength.stat[0].scale = FE_SCALE_RELATIVE; return 0; } -- cgit v1.1 From 6983257813dcc052cb46639f28ac77f46ec7350f Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Mon, 10 Mar 2014 08:08:53 -0300 Subject: [media] drx-j: properly handle bit counts on stats Instead of just assuming that the min resolution is 1E-6, pass both bit error and bit counts for userspace to calculate BER. The same applies for PER, for 8VSB. It is not clear how to get the packet count for QAM. So, for now, don't expose PER for QAM. Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drxj.c | 89 ++++++++++++++++------------- 1 file changed, 50 insertions(+), 39 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index 6005e34..9958277 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -6199,7 +6199,8 @@ rw_error: * \brief Get the values of packet error in 8VSB mode * \return Error code */ -static int get_vsb_post_rs_pck_err(struct i2c_device_addr *dev_addr, u16 *pck_errs) +static int get_vsb_post_rs_pck_err(struct i2c_device_addr *dev_addr, + u16 *pck_errs, u16 *pck_count) { int rc; u16 data = 0; @@ -6224,9 +6225,8 @@ static int get_vsb_post_rs_pck_err(struct i2c_device_addr *dev_addr, u16 *pck_er pr_err("error: period and/or prescale is zero!\n"); return -EIO; } - *pck_errs = - (u16) frac_times1e6(packet_errors_mant * (1 << packet_errors_exp), - (period * prescale * 77)); + *pck_errs = packet_errors_mant * (1 << packet_errors_exp); + *pck_count = period * prescale * 77; return 0; rw_error: @@ -6238,7 +6238,8 @@ rw_error: * \brief Get the values of ber in VSB mode * \return Error code */ -static int get_vs_bpost_viterbi_ber(struct i2c_device_addr *dev_addr, u32 *ber) +static int get_vs_bpost_viterbi_ber(struct i2c_device_addr *dev_addr, + u32 *ber, u32 *cnt) { int rc; u16 data = 0; @@ -6259,19 +6260,17 @@ static int get_vs_bpost_viterbi_ber(struct i2c_device_addr *dev_addr, u32 *ber) bit_errors_exp = (data & FEC_RS_NR_BIT_ERRORS_EXP__M) >> FEC_RS_NR_BIT_ERRORS_EXP__B; + *cnt = period * prescale * 207 * ((bit_errors_exp > 2) ? 1 : 8); + if (((bit_errors_mant << bit_errors_exp) >> 3) > 68700) - *ber = 26570; + *ber = (*cnt) * 26570; else { if (period * prescale == 0) { pr_err("error: period and/or prescale is zero!\n"); return -EIO; } - *ber = - frac_times1e6(bit_errors_mant << - ((bit_errors_exp > - 2) ? (bit_errors_exp - 3) : bit_errors_exp), - period * prescale * 207 * - ((bit_errors_exp > 2) ? 1 : 8)); + *ber = bit_errors_mant << ((bit_errors_exp > 2) ? + (bit_errors_exp - 3) : bit_errors_exp); } return 0; @@ -6284,7 +6283,8 @@ rw_error: * \brief Get the values of ber in VSB mode * \return Error code */ -static int get_vs_bpre_viterbi_ber(struct i2c_device_addr *dev_addr, u32 *ber) +static int get_vs_bpre_viterbi_ber(struct i2c_device_addr *dev_addr, + u32 *ber, u32 *cnt) { u16 data = 0; int rc; @@ -6292,15 +6292,12 @@ static int get_vs_bpre_viterbi_ber(struct i2c_device_addr *dev_addr, u32 *ber) rc = drxj_dap_read_reg16(dev_addr, VSB_TOP_NR_SYM_ERRS__A, &data, 0); if (rc != 0) { pr_err("error %d\n", rc); - goto rw_error; + return -EIO; } - *ber = - frac_times1e6(data, - VSB_TOP_MEASUREMENT_PERIOD * SYMBOLS_PER_SEGMENT); + *ber = data; + *cnt = VSB_TOP_MEASUREMENT_PERIOD * SYMBOLS_PER_SEGMENT; return 0; -rw_error: - return -EIO; } /** @@ -9289,7 +9286,8 @@ rw_error: * */ static int -get_qamrs_err_count(struct i2c_device_addr *dev_addr, struct drxjrs_errors *rs_errors) +get_qamrs_err_count(struct i2c_device_addr *dev_addr, + struct drxjrs_errors *rs_errors) { int rc; u16 nr_bit_errors = 0, @@ -9474,6 +9472,8 @@ ctrl_get_qam_sig_quality(struct drx_demod_instance *demod) u16 qam_vd_period = 0; /* Viterbi Measurement period */ u32 vd_bit_cnt = 0; /* ViterbiDecoder Bit Count */ + p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + /* read the physical registers */ /* Get the RS error data */ rc = get_qamrs_err_count(dev_addr, &measuredrs_errors); @@ -9554,9 +9554,9 @@ ctrl_get_qam_sig_quality(struct drx_demod_instance *demod) QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__B; if ((m << e) >> 3 > 549752) - qam_vd_ser = 500000; + qam_vd_ser = 500000 * vd_bit_cnt * ((e > 2) ? 1 : 8) / 8; else - qam_vd_ser = frac_times1e6(m << ((e > 2) ? (e - 3) : e), vd_bit_cnt * ((e > 2) ? 1 : 8) / 8); + qam_vd_ser = m << ((e > 2) ? (e - 3) : e); /* --------------------------------------- */ /* pre and post RedSolomon BER Calculation */ @@ -9578,9 +9578,9 @@ ctrl_get_qam_sig_quality(struct drx_demod_instance *demod) /*qam_pre_rs_ber = frac_times1e6( ber_cnt, rs_bit_cnt ); */ if (m > (rs_bit_cnt >> (e + 1)) || (rs_bit_cnt >> e) == 0) - qam_pre_rs_ber = 500000; + qam_pre_rs_ber = 500000 * rs_bit_cnt >> e; else - qam_pre_rs_ber = frac_times1e6(m, rs_bit_cnt >> e); + qam_pre_rs_ber = m; /* post RS BER = 1000000* (11.17 * FEC_OC_SNC_FAIL_COUNT__A) / */ /* (1504.0 * FEC_OC_SNC_FAIL_PERIOD__A) */ @@ -9609,16 +9609,16 @@ ctrl_get_qam_sig_quality(struct drx_demod_instance *demod) p->cnr.stat[0].scale = FE_SCALE_DECIBEL; p->cnr.stat[0].svalue = ((u16) qam_sl_mer) * 100; - if (ext_attr->standard == DRX_STANDARD_ITU_B) + if (ext_attr->standard == DRX_STANDARD_ITU_B) { p->pre_bit_error.stat[0].uvalue += qam_vd_ser; - else + p->pre_bit_count.stat[0].uvalue += vd_bit_cnt * ((e > 2) ? 1 : 8) / 8; + } else { p->pre_bit_error.stat[0].uvalue += qam_pre_rs_ber; + p->pre_bit_count.stat[0].uvalue += rs_bit_cnt >> e; + } p->post_bit_error.stat[0].uvalue = qam_post_rs_ber; - p->pre_bit_count.stat[0].uvalue += 1000000; - p->post_bit_count.stat[0].uvalue += 1000000; - p->block_error.stat[0].uvalue += pkt_errs; #ifdef DRXJ_SIGNAL_ACCUM_ERR @@ -10661,8 +10661,8 @@ ctrl_sig_quality(struct drx_demod_instance *demod, struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache; enum drx_standard standard = ext_attr->standard; int rc; - u32 ber; - u16 pkt, mer, strength; + u32 ber, cnt; + u16 err, pkt, mer, strength; rc = get_sig_strength(demod, &strength); if (rc < 0) { @@ -10684,23 +10684,26 @@ ctrl_sig_quality(struct drx_demod_instance *demod, #endif if (lock_status != DRXJ_DEMOD_LOCK && lock_status != DRX_LOCKED) { p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; - p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; } else { - rc = get_vsb_post_rs_pck_err(dev_addr, &pkt); + rc = get_vsb_post_rs_pck_err(dev_addr, &err, &pkt); if (rc != 0) { pr_err("error %d getting UCB\n", rc); p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; } else { p->block_error.stat[0].scale = FE_SCALE_COUNTER; - p->block_error.stat[0].uvalue += pkt; + p->block_error.stat[0].uvalue += err; + p->block_count.stat[0].scale = FE_SCALE_COUNTER; + p->block_count.stat[0].uvalue += pkt; } /* PostViterbi is compute in steps of 10^(-6) */ - rc = get_vs_bpre_viterbi_ber(dev_addr, &ber); + rc = get_vs_bpre_viterbi_ber(dev_addr, &ber, &cnt); if (rc != 0) { pr_err("error %d getting pre-ber\n", rc); p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; @@ -10708,10 +10711,10 @@ ctrl_sig_quality(struct drx_demod_instance *demod, p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER; p->pre_bit_error.stat[0].uvalue += ber; p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER; - p->pre_bit_count.stat[0].uvalue += 1000000; + p->pre_bit_count.stat[0].uvalue += cnt; } - rc = get_vs_bpost_viterbi_ber(dev_addr, &ber); + rc = get_vs_bpost_viterbi_ber(dev_addr, &ber, &cnt); if (rc != 0) { pr_err("error %d getting post-ber\n", rc); p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; @@ -10719,7 +10722,7 @@ ctrl_sig_quality(struct drx_demod_instance *demod, p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; p->post_bit_error.stat[0].uvalue += ber; p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; - p->post_bit_count.stat[0].uvalue += 1000000; + p->post_bit_count.stat[0].uvalue += cnt; } rc = get_vsbmer(dev_addr, &mer); if (rc != 0) { @@ -11966,7 +11969,15 @@ static int drx39xxj_read_ber(struct dvb_frontend *fe, u32 *ber) return 0; } - *ber = p->pre_bit_error.stat[0].uvalue; + if (!p->pre_bit_count.stat[0].uvalue) { + if (!p->pre_bit_error.stat[0].uvalue) + *ber = 0; + else + *ber = 1000000; + } else { + *ber = frac_times1e6(p->pre_bit_error.stat[0].uvalue, + p->pre_bit_count.stat[0].uvalue); + } return 0; } -- cgit v1.1 From 80846a5c2f6650c903e6fa0708030cb6ba1124c8 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Mon, 10 Mar 2014 08:18:31 -0300 Subject: [media] drx-j: Fix detection of no signal When the signal is 7, it means that no signal was received. Value experimentally measured. Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drxj.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index 9958277..8098d87 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -9420,6 +9420,9 @@ static int get_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength) *sig_strength = (20 * if_gain / if_agc_sns); } + if (*sig_strength <= 7) + *sig_strength = 0; + return 0; rw_error: return -EIO; -- cgit v1.1 From d591590e1b5bba2f96b44b1e05f65bc8269f0a68 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Mon, 10 Mar 2014 08:22:34 -0300 Subject: [media] drx-j: enable DVBv5 stats Now that everything is set, let's enable DVBv5 stats, for applications that support it. DVBv3 apps will still work. Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drxj.c | 29 +++++++++++++++++++++++++---- 1 file changed, 25 insertions(+), 4 deletions(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index 8098d87..0c0e9f3 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -6200,7 +6200,7 @@ rw_error: * \return Error code */ static int get_vsb_post_rs_pck_err(struct i2c_device_addr *dev_addr, - u16 *pck_errs, u16 *pck_count) + u32 *pck_errs, u32 *pck_count) { int rc; u16 data = 0; @@ -10664,8 +10664,8 @@ ctrl_sig_quality(struct drx_demod_instance *demod, struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache; enum drx_standard standard = ext_attr->standard; int rc; - u32 ber, cnt; - u16 err, pkt, mer, strength; + u32 ber, cnt, err, pkt; + u16 mer, strength; rc = get_sig_strength(demod, &strength); if (rc < 0) { @@ -12249,11 +12249,11 @@ static struct dvb_frontend_ops drx39xxj_ops; struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) { struct drx39xxj_state *state = NULL; - struct i2c_device_addr *demod_addr = NULL; struct drx_common_attr *demod_comm_attr = NULL; struct drxj_data *demod_ext_attr = NULL; struct drx_demod_instance *demod = NULL; + struct dtv_frontend_properties *p; struct drxuio_cfg uio_cfg; struct drxuio_data uio_data; int result; @@ -12331,6 +12331,27 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) sizeof(struct dvb_frontend_ops)); state->frontend.demodulator_priv = state; + + /* Initialize stats - needed for DVBv5 stats to work */ + p = &state->frontend.dtv_property_cache; + p->strength.len = 1; + p->pre_bit_count.len = 1; + p->pre_bit_error.len = 1; + p->post_bit_count.len = 1; + p->post_bit_error.len = 1; + p->block_count.len = 1; + p->block_error.len = 1; + p->cnr.len = 1; + + p->strength.stat[0].scale = FE_SCALE_RELATIVE; + p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + return &state->frontend; error: -- cgit v1.1 From ee0f4a144423cdb5744ceca4ed9e91582c39becf Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 11 Mar 2014 07:34:44 -0300 Subject: drx-j: use ber_count var drivers/media/dvb-frontends/drx39xyj/drxj.c: In function 'ctrl_get_qam_sig_quality': drivers/media/dvb-frontends/drx39xyj/drxj.c:9468:6: warning: variable 'ber_cnt' set but not used [-Wunused-but-set-variable] u32 ber_cnt = 0; /* BER count */ ^ By reading the comment, it is said that BER should be calculated as: qam_pre_rs_ber = frac_times1e6( ber_cnt, rs_bit_cnt ); Also, it makes sense to take the mantissa into account, so fix the code to do what's commented. Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drxj.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index 0c0e9f3..41d4bfe 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -9583,7 +9583,7 @@ ctrl_get_qam_sig_quality(struct drx_demod_instance *demod) if (m > (rs_bit_cnt >> (e + 1)) || (rs_bit_cnt >> e) == 0) qam_pre_rs_ber = 500000 * rs_bit_cnt >> e; else - qam_pre_rs_ber = m; + qam_pre_rs_ber = ber_cnt; /* post RS BER = 1000000* (11.17 * FEC_OC_SNC_FAIL_COUNT__A) / */ /* (1504.0 * FEC_OC_SNC_FAIL_PERIOD__A) */ -- cgit v1.1 From 0d49e7761173520ff02cec6f11d581f8ebca764d Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 11 Mar 2014 07:43:54 -0300 Subject: drx-j: Fix post-BER calculus on QAM modulation There are two troubles there: 1) the bit error measure were not accumulating; 2) it was missing the bit count. Fix them. Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drxj.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index 41d4bfe..b8c5a85 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -9620,7 +9620,8 @@ ctrl_get_qam_sig_quality(struct drx_demod_instance *demod) p->pre_bit_count.stat[0].uvalue += rs_bit_cnt >> e; } - p->post_bit_error.stat[0].uvalue = qam_post_rs_ber; + p->post_bit_error.stat[0].uvalue += qam_post_rs_ber; + p->post_bit_count.stat[0].uvalue += rs_bit_cnt >> e; p->block_error.stat[0].uvalue += pkt_errs; -- cgit v1.1 From 9b05837352e7c90b5af81fb7a5e499e91d376ee0 Mon Sep 17 00:00:00 2001 From: Fengguang Wu Date: Tue, 4 Feb 2014 06:02:02 -0300 Subject: [media] drivers/media/usb/usbtv/usbtv-core.c:119:22: sparse: symbol 'usbtv_id_table' was not declared. Should it be static? tree: git://linuxtv.org/media_tree.git master head: a3550ea665acd1922df8275379028c1634675629 commit: a3550ea665acd1922df8275379028c1634675629 [499/499] [media] usbtv: split core and video implementation reproduce: make C=1 CF=-D__CHECK_ENDIAN__ sparse warnings: (new ones prefixed by >>) >> drivers/media/usb/usbtv/usbtv-core.c:119:22: sparse: symbol 'usbtv_id_table' was not declared. Should it be static? >> drivers/media/usb/usbtv/usbtv-core.c:129:19: sparse: symbol 'usbtv_usb_driver' was not declared. Should it be static? Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/usbtv/usbtv-core.c | 4 ++-- drivers/media/usb/usbtv/usbtv-video.c | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/media/usb/usbtv/usbtv-core.c b/drivers/media/usb/usbtv/usbtv-core.c index d543928..2f87ddf 100644 --- a/drivers/media/usb/usbtv/usbtv-core.c +++ b/drivers/media/usb/usbtv/usbtv-core.c @@ -114,7 +114,7 @@ static void usbtv_disconnect(struct usb_interface *intf) v4l2_device_put(&usbtv->v4l2_dev); } -struct usb_device_id usbtv_id_table[] = { +static struct usb_device_id usbtv_id_table[] = { { USB_DEVICE(0x1b71, 0x3002) }, {} }; @@ -124,7 +124,7 @@ MODULE_AUTHOR("Lubomir Rintel"); MODULE_DESCRIPTION("Fushicai USBTV007 Video Grabber Driver"); MODULE_LICENSE("Dual BSD/GPL"); -struct usb_driver usbtv_usb_driver = { +static struct usb_driver usbtv_usb_driver = { .name = "usbtv", .id_table = usbtv_id_table, .probe = usbtv_probe, diff --git a/drivers/media/usb/usbtv/usbtv-video.c b/drivers/media/usb/usbtv/usbtv-video.c index 01ed1ec8..20365bd 100644 --- a/drivers/media/usb/usbtv/usbtv-video.c +++ b/drivers/media/usb/usbtv/usbtv-video.c @@ -562,7 +562,7 @@ static int usbtv_s_input(struct file *file, void *priv, unsigned int i) return usbtv_select_input(usbtv, i); } -struct v4l2_ioctl_ops usbtv_ioctl_ops = { +static struct v4l2_ioctl_ops usbtv_ioctl_ops = { .vidioc_querycap = usbtv_querycap, .vidioc_enum_input = usbtv_enum_input, .vidioc_enum_fmt_vid_cap = usbtv_enum_fmt_vid_cap, @@ -584,7 +584,7 @@ struct v4l2_ioctl_ops usbtv_ioctl_ops = { .vidioc_streamoff = vb2_ioctl_streamoff, }; -struct v4l2_file_operations usbtv_fops = { +static struct v4l2_file_operations usbtv_fops = { .owner = THIS_MODULE, .unlocked_ioctl = video_ioctl2, .mmap = vb2_fop_mmap, @@ -645,7 +645,7 @@ static int usbtv_stop_streaming(struct vb2_queue *vq) return 0; } -struct vb2_ops usbtv_vb2_ops = { +static struct vb2_ops usbtv_vb2_ops = { .queue_setup = usbtv_queue_setup, .buf_queue = usbtv_buf_queue, .start_streaming = usbtv_start_streaming, -- cgit v1.1 From c817d927b0f7c3b3c8defa7c6ce77f934ec31eb7 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Fri, 21 Feb 2014 06:16:32 -0300 Subject: [media] v4l2-ctrls: replace BUG_ON by WARN_ON BUG_ON is unnecessarily strict. Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/v4l2-core/v4l2-ctrls.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c index 1168f68..5c3e8ca 100644 --- a/drivers/media/v4l2-core/v4l2-ctrls.c +++ b/drivers/media/v4l2-core/v4l2-ctrls.c @@ -1942,7 +1942,8 @@ void v4l2_ctrl_cluster(unsigned ncontrols, struct v4l2_ctrl **controls) int i; /* The first control is the master control and it must not be NULL */ - BUG_ON(ncontrols == 0 || controls[0] == NULL); + if (WARN_ON(ncontrols == 0 || controls[0] == NULL)) + return; for (i = 0; i < ncontrols; i++) { if (controls[i]) { -- cgit v1.1 From 111eeaa73a10513ce47339445b1b164041a835b3 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 21 Feb 2014 16:57:17 -0300 Subject: [media] v4l: VIDEO_SH_VOU should depend on HAS_DMA If NO_DMA=y: warning: (VIDEO_DM6446_CCDC && VIDEO_DM355_CCDC && VIDEO_DM365_ISIF && VIDEO_OMAP2_VOUT && VIDEO_SH_VOU && VIDEO_VIU && VIDEO_TIMBERDALE && VIDEO_MX1 && VIDEO_OMAP1) selects VIDEOBUF_DMA_CONTIG which has unmet direct dependencies (MEDIA_SUPPORT && HAS_DMA) drivers/built-in.o: In function `videobuf_vm_close': videobuf-dma-contig.c:(.text+0x407aa0): undefined reference to `videobuf_queue_cancel' drivers/built-in.o: In function `__videobuf_dc_alloc': videobuf-dma-contig.c:(.text+0x407ba2): undefined reference to `dma_alloc_coherent' drivers/built-in.o: In function `__videobuf_mmap_mapper': videobuf-dma-contig.c:(.text+0x407d44): undefined reference to `dma_free_coherent' drivers/built-in.o: In function `free_buffer': sh_vou.c:(.text+0x41f73a): undefined reference to `videobuf_waiton' drivers/built-in.o: In function `sh_vou_poll': sh_vou.c:(.text+0x41f884): undefined reference to `videobuf_poll_stream' drivers/built-in.o: In function `sh_vou_buf_prepare': sh_vou.c:(.text+0x41fdf6): undefined reference to `videobuf_iolock' drivers/built-in.o: In function `sh_vou_reqbufs': sh_vou.c:(.text+0x4203b0): undefined reference to `videobuf_reqbufs' drivers/built-in.o: In function `sh_vou_querybuf': sh_vou.c:(.text+0x42040a): undefined reference to `videobuf_querybuf' drivers/built-in.o: In function `sh_vou_qbuf': sh_vou.c:(.text+0x42045e): undefined reference to `videobuf_qbuf' drivers/built-in.o: In function `sh_vou_dqbuf': sh_vou.c:(.text+0x4204c2): undefined reference to `videobuf_dqbuf' drivers/built-in.o: In function `sh_vou_streamon': sh_vou.c:(.text+0x420572): undefined reference to `videobuf_streamon' drivers/built-in.o: In function `sh_vou_streamoff': sh_vou.c:(.text+0x4205d2): undefined reference to `videobuf_streamoff' drivers/built-in.o: In function `sh_vou_mmap': sh_vou.c:(.text+0x420c46): undefined reference to `videobuf_mmap_mapper' VIDEO_SH_VOU selects VIDEOBUF_DMA_CONTIG, which bypasses its dependency on HAS_DMA. Make VIDEO_SH_VOU depend on HAS_DMA to fix this. Signed-off-by: Geert Uytterhoeven Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/platform/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig index b2a4403..c137abf 100644 --- a/drivers/media/platform/Kconfig +++ b/drivers/media/platform/Kconfig @@ -36,7 +36,7 @@ source "drivers/media/platform/blackfin/Kconfig" config VIDEO_SH_VOU tristate "SuperH VOU video output driver" depends on MEDIA_CAMERA_SUPPORT - depends on VIDEO_DEV && I2C + depends on VIDEO_DEV && I2C && HAS_DMA depends on ARCH_SHMOBILE || COMPILE_TEST select VIDEOBUF_DMA_CONTIG help -- cgit v1.1 From f97881fe500026053c24d2a0ef8aebfd3c2a1ca8 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 26 Feb 2014 08:01:48 -0300 Subject: [media] arv: fix sleep_on race interruptible_sleep_on is racy and going away. In the arv driver that race has probably never caused problems since it would require a whole video frame to be captured before the read function has a chance to go to sleep, but using wait_event_interruptible lets us kill off the old interface. In order to do this, we have to slightly adapt the meaning of the ar->start_capture field to distinguish between not having started a frame and having completed it. Signed-off-by: Arnd Bergmann Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/platform/arv.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/media/platform/arv.c b/drivers/media/platform/arv.c index e346d32d..e9410e4 100644 --- a/drivers/media/platform/arv.c +++ b/drivers/media/platform/arv.c @@ -109,7 +109,7 @@ extern struct cpuinfo_m32r boot_cpu_data; struct ar { struct v4l2_device v4l2_dev; struct video_device vdev; - unsigned int start_capture; /* duaring capture in INT. mode. */ + int start_capture; /* duaring capture in INT. mode. */ #if USE_INT unsigned char *line_buff; /* DMA line buffer */ #endif @@ -307,11 +307,11 @@ static ssize_t ar_read(struct file *file, char *buf, size_t count, loff_t *ppos) /* * Okay, kick AR LSI to invoke an interrupt */ - ar->start_capture = 0; + ar->start_capture = -1; ar_outl(arvcr1 | ARVCR1_HIEN, ARVCR1); local_irq_restore(flags); /* .... AR interrupts .... */ - interruptible_sleep_on(&ar->wait); + wait_event_interruptible(ar->wait, ar->start_capture == 0); if (signal_pending(current)) { printk(KERN_ERR "arv: interrupted while get frame data.\n"); ret = -EINTR; -- cgit v1.1 From fbcb2dc3519ac09068e09ef8c1de35e006de29ec Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Sun, 2 Mar 2014 06:43:12 -0300 Subject: [media] media DocBook: fix NV16M description The NV16M description contained some copy-and-paste text from NV12M, suggesting that this format is a 4:2:0 format when it really is a 4:2:2 format. Fixed the text. Signed-off-by: Hans Verkuil Acked-by: Laurent Pinchart Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/v4l/pixfmt-nv16m.xml | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/Documentation/DocBook/media/v4l/pixfmt-nv16m.xml b/Documentation/DocBook/media/v4l/pixfmt-nv16m.xml index c51d5a4..fb2b5e3 100644 --- a/Documentation/DocBook/media/v4l/pixfmt-nv16m.xml +++ b/Documentation/DocBook/media/v4l/pixfmt-nv16m.xml @@ -12,18 +12,17 @@ Description - This is a multi-planar, two-plane version of the YUV 4:2:0 format. + This is a multi-planar, two-plane version of the YUV 4:2:2 format. The three components are separated into two sub-images or planes. V4L2_PIX_FMT_NV16M differs from V4L2_PIX_FMT_NV16 in that the two planes are non-contiguous in memory, i.e. the chroma -plane does not necessarily immediately follows the luma plane. +plane does not necessarily immediately follow the luma plane. The luminance data occupies the first plane. The Y plane has one byte per pixel. In the second plane there is chrominance data with alternating chroma samples. The CbCr plane is the same width and height, in bytes, as the Y plane. -Each CbCr pair belongs to four pixels. For example, +Each CbCr pair belongs to two pixels. For example, Cb0/Cr0 belongs to -Y'00, Y'01, -Y'10, Y'11. +Y'00, Y'01. V4L2_PIX_FMT_NV61M is the same as V4L2_PIX_FMT_NV16M except the Cb and Cr bytes are swapped, the CrCb plane starts with a Cr byte. -- cgit v1.1 From 6fb0e403e4399c5d495d6c0e866533bfd87b4b23 Mon Sep 17 00:00:00 2001 From: Jon Mason Date: Mon, 3 Mar 2014 14:00:38 -0300 Subject: [media] staging/dt3155v4l: use PCI_VENDOR_ID_INTEL Use PCI_VENDOR_ID_INTEL instead of creating its own vendor ID #define. Signed-off-by: Jon Mason Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/staging/media/dt3155v4l/dt3155v4l.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/staging/media/dt3155v4l/dt3155v4l.c b/drivers/staging/media/dt3155v4l/dt3155v4l.c index e235787..68d41e2 100644 --- a/drivers/staging/media/dt3155v4l/dt3155v4l.c +++ b/drivers/staging/media/dt3155v4l/dt3155v4l.c @@ -31,7 +31,6 @@ #include "dt3155v4l.h" -#define DT3155_VENDOR_ID 0x8086 #define DT3155_DEVICE_ID 0x1223 /* DT3155_CHUNK_SIZE is 4M (2^22) 8 full size buffers */ @@ -975,7 +974,7 @@ dt3155_remove(struct pci_dev *pdev) } static const struct pci_device_id pci_ids[] = { - { PCI_DEVICE(DT3155_VENDOR_ID, DT3155_DEVICE_ID) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, DT3155_DEVICE_ID) }, { 0, /* zero marks the end */ }, }; MODULE_DEVICE_TABLE(pci, pci_ids); -- cgit v1.1 From 73a8ca4877e17bece77f103336aa1e05cc3adcf0 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Wed, 5 Mar 2014 08:09:37 -0300 Subject: [media] em28xx-cards: remove a wrong indent level This code is correct but the indenting is wrong and triggers a static checker warning "add curly braces?". Signed-off-by: Dan Carpenter Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/em28xx/em28xx-cards.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/media/usb/em28xx/em28xx-cards.c b/drivers/media/usb/em28xx/em28xx-cards.c index e7ec3b7..50aa5a5 100644 --- a/drivers/media/usb/em28xx/em28xx-cards.c +++ b/drivers/media/usb/em28xx/em28xx-cards.c @@ -3418,8 +3418,8 @@ static int em28xx_usb_probe(struct usb_interface *interface, if (has_video) { if (!dev->analog_ep_isoc || (try_bulk && dev->analog_ep_bulk)) dev->analog_xfer_bulk = 1; - em28xx_info("analog set to %s mode.\n", - dev->analog_xfer_bulk ? "bulk" : "isoc"); + em28xx_info("analog set to %s mode.\n", + dev->analog_xfer_bulk ? "bulk" : "isoc"); } if (has_dvb) { if (!dev->dvb_ep_isoc || (try_bulk && dev->dvb_ep_bulk)) -- cgit v1.1 From 785a3de18badb13a94a4cf71ebe38ea84b63a132 Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Thu, 27 Feb 2014 13:44:47 -0300 Subject: [media] tvp5150: Fix type mismatch warning in clamp macro This patch fixes the following warning: drivers/media/i2c/tvp5150.c: In function '__tvp5150_try_crop': include/linux/kernel.h:762:17: warning: comparison of distinct pointer types lacks a cast [enabled by default] (void) (&__val == &__min); \ ^ drivers/media/i2c/tvp5150.c:886:16: note: in expansion of macro 'clamp' rect->width = clamp(rect->width, ^ include/linux/kernel.h:763:17: warning: comparison of distinct pointer types lacks a cast [enabled by default] (void) (&__val == &__max); \ ^ drivers/media/i2c/tvp5150.c:886:16: note: in expansion of macro 'clamp' rect->width = clamp(rect->width, ^ include/linux/kernel.h:762:17: warning: comparison of distinct pointer types lacks a cast [enabled by default] (void) (&__val == &__min); \ ^ drivers/media/i2c/tvp5150.c:904:17: note: in expansion of macro 'clamp' rect->height = clamp(rect->height, ^ include/linux/kernel.h:763:17: warning: comparison of distinct pointer types lacks a cast [enabled by default] (void) (&__val == &__max); \ ^ drivers/media/i2c/tvp5150.c:904:17: note: in expansion of macro 'clamp' rect->height = clamp(rect->height, ^ Signed-off-by: Philipp Zabel Acked-by: Lad, Prabhakar Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/i2c/tvp5150.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/media/i2c/tvp5150.c b/drivers/media/i2c/tvp5150.c index 542d252..8ac52fc 100644 --- a/drivers/media/i2c/tvp5150.c +++ b/drivers/media/i2c/tvp5150.c @@ -16,9 +16,9 @@ #include "tvp5150_reg.h" -#define TVP5150_H_MAX 720 -#define TVP5150_V_MAX_525_60 480 -#define TVP5150_V_MAX_OTHERS 576 +#define TVP5150_H_MAX 720U +#define TVP5150_V_MAX_525_60 480U +#define TVP5150_V_MAX_OTHERS 576U #define TVP5150_MAX_CROP_LEFT 511 #define TVP5150_MAX_CROP_TOP 127 #define TVP5150_CROP_SHIFT 2 -- cgit v1.1 From 2a0489d351b1cefff6be2f6ac33826788da35266 Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Thu, 27 Feb 2014 13:44:48 -0300 Subject: [media] tvp5150: Make debug module parameter visible in sysfs Set permissions on the debug module parameter to make it appear in sysfs. Signed-off-by: Philipp Zabel Acked-by: Lad, Prabhakar Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/i2c/tvp5150.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/i2c/tvp5150.c b/drivers/media/i2c/tvp5150.c index 8ac52fc..4fd3688 100644 --- a/drivers/media/i2c/tvp5150.c +++ b/drivers/media/i2c/tvp5150.c @@ -29,7 +29,7 @@ MODULE_LICENSE("GPL"); static int debug; -module_param(debug, int, 0); +module_param(debug, int, 0644); MODULE_PARM_DESC(debug, "Debug level (0-2)"); struct tvp5150 { -- cgit v1.1 From 4a1df5e8f6712df3b5f8aeb09771a1169ddd8e8c Mon Sep 17 00:00:00 2001 From: sensoray-dev Date: Fri, 28 Feb 2014 19:19:44 -0300 Subject: [media] s2255drv: memory leak fix Fixes memory leak introduced by commit 47d8c881c304642a68d398b87d9e8846e643c81a. Signed-off-by: Dean Anderson Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/s2255/s2255drv.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/media/usb/s2255/s2255drv.c b/drivers/media/usb/s2255/s2255drv.c index 4c7513a..1d4ba2b 100644 --- a/drivers/media/usb/s2255/s2255drv.c +++ b/drivers/media/usb/s2255/s2255drv.c @@ -2175,11 +2175,6 @@ static int s2255_stop_acquire(struct s2255_vc *vc) mutex_lock(&dev->cmdlock); chn_rev = G_chnmap[vc->idx]; - buffer = kzalloc(512, GFP_KERNEL); - if (buffer == NULL) { - dev_err(&dev->udev->dev, "out of mem\n"); - return -ENOMEM; - } /* send the stop command */ buffer[0] = IN_DATA_TOKEN; buffer[1] = (__le32) cpu_to_le32(chn_rev); -- cgit v1.1 From cbe504d4d4d88375ef912975f816d1e3c3f14194 Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Tue, 25 Feb 2014 06:10:27 -0300 Subject: [media] media: soc_camera: rcar_vin: Add support for 10-bit YUV cameras Add support for MBUS YUV10 BT656 and BT601 formats at rcar driver. Signed-off-by: Phil Edworthy Signed-off-by: Guennadi Liakhovetski Signed-off-by: Mauro Carvalho Chehab --- drivers/media/platform/soc_camera/rcar_vin.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/media/platform/soc_camera/rcar_vin.c b/drivers/media/platform/soc_camera/rcar_vin.c index 0ff5cfa..704eee7 100644 --- a/drivers/media/platform/soc_camera/rcar_vin.c +++ b/drivers/media/platform/soc_camera/rcar_vin.c @@ -68,6 +68,8 @@ #define VNMC_YCAL (1 << 19) #define VNMC_INF_YUV8_BT656 (0 << 16) #define VNMC_INF_YUV8_BT601 (1 << 16) +#define VNMC_INF_YUV10_BT656 (2 << 16) +#define VNMC_INF_YUV10_BT601 (3 << 16) #define VNMC_INF_YUV16 (5 << 16) #define VNMC_VUP (1 << 10) #define VNMC_IM_ODD (0 << 3) @@ -275,6 +277,12 @@ static int rcar_vin_setup(struct rcar_vin_priv *priv) /* BT.656 8bit YCbCr422 or BT.601 8bit YCbCr422 */ vnmc |= priv->pdata->flags & RCAR_VIN_BT656 ? VNMC_INF_YUV8_BT656 : VNMC_INF_YUV8_BT601; + break; + case V4L2_MBUS_FMT_YUYV10_2X10: + /* BT.656 10bit YCbCr422 or BT.601 10bit YCbCr422 */ + vnmc |= priv->pdata->flags & RCAR_VIN_BT656 ? + VNMC_INF_YUV10_BT656 : VNMC_INF_YUV10_BT601; + break; default: break; } @@ -1003,6 +1011,7 @@ static int rcar_vin_get_formats(struct soc_camera_device *icd, unsigned int idx, switch (code) { case V4L2_MBUS_FMT_YUYV8_1X16: case V4L2_MBUS_FMT_YUYV8_2X8: + case V4L2_MBUS_FMT_YUYV10_2X10: if (cam->extra_fmt) break; -- cgit v1.1 From bb60fcb29baeead3128b3a8dd123578bead55c81 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Sun, 24 Nov 2013 17:44:08 -0300 Subject: [media] MAINTAINERS: remove myself as a maintainer of VEU and VOU V4L2 drivers Since I'm currently unable to dedicate sufficient time to the maintainership of these two drivers update their status to "orphan" until new maintainers appear. Signed-off-by: Guennadi Liakhovetski Signed-off-by: Mauro Carvalho Chehab --- MAINTAINERS | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 0d0d6a1..c1c6be8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -7837,15 +7837,13 @@ F: drivers/media/usb/siano/ F: drivers/media/mmc/siano/ SH_VEU V4L2 MEM2MEM DRIVER -M: Guennadi Liakhovetski L: linux-media@vger.kernel.org -S: Maintained +S: Orphan F: drivers/media/platform/sh_veu.c SH_VOU V4L2 OUTPUT DRIVER -M: Guennadi Liakhovetski L: linux-media@vger.kernel.org -S: Odd Fixes +S: Orphan F: drivers/media/platform/sh_vou.c F: include/media/sh_vou.h -- cgit v1.1 From b9db140c1e4644dc93900db476546e119dce5a28 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Mon, 10 Mar 2014 20:15:12 -0300 Subject: [media] v4l: of: Support empty port nodes Empty port nodes are allowed but currently unsupported as the v4l2_of_get_next_endpoint() function assumes that all port nodes have at least an endpoint. Fix this. Signed-off-by: Laurent Pinchart Signed-off-by: Mauro Carvalho Chehab --- drivers/media/v4l2-core/v4l2-of.c | 52 +++++++++++++++++++++------------------ 1 file changed, 28 insertions(+), 24 deletions(-) diff --git a/drivers/media/v4l2-core/v4l2-of.c b/drivers/media/v4l2-core/v4l2-of.c index 42e3e8a..4c07343 100644 --- a/drivers/media/v4l2-core/v4l2-of.c +++ b/drivers/media/v4l2-core/v4l2-of.c @@ -166,43 +166,51 @@ struct device_node *v4l2_of_get_next_endpoint(const struct device_node *parent, struct device_node *prev) { struct device_node *endpoint; - struct device_node *port = NULL; + struct device_node *port; if (!parent) return NULL; + /* + * Start by locating the port node. If no previous endpoint is specified + * search for the first port node, otherwise get the previous endpoint + * parent port node. + */ if (!prev) { struct device_node *node; - /* - * It's the first call, we have to find a port subnode - * within this node or within an optional 'ports' node. - */ + node = of_get_child_by_name(parent, "ports"); if (node) parent = node; port = of_get_child_by_name(parent, "port"); + of_node_put(node); - if (port) { - /* Found a port, get an endpoint. */ - endpoint = of_get_next_child(port, NULL); - of_node_put(port); - } else { - endpoint = NULL; - } - - if (!endpoint) - pr_err("%s(): no endpoint nodes specified for %s\n", + if (!port) { + pr_err("%s(): no port node found in %s\n", __func__, parent->full_name); - of_node_put(node); + return NULL; + } } else { port = of_get_parent(prev); - if (!port) + if (!port) { /* Hm, has someone given us the root node ?... */ return NULL; + } - /* Avoid dropping prev node refcount to 0. */ + /* + * Avoid dropping prev node refcount to 0 when getting the next + * child below. + */ of_node_get(prev); + } + + while (1) { + /* + * Now that we have a port node, get the next endpoint by + * getting the next child. If the previous endpoint is NULL this + * will return the first child. + */ endpoint = of_get_next_child(port, prev); if (endpoint) { of_node_put(port); @@ -210,18 +218,14 @@ struct device_node *v4l2_of_get_next_endpoint(const struct device_node *parent, } /* No more endpoints under this port, try the next one. */ + prev = NULL; + do { port = of_get_next_child(parent, port); if (!port) return NULL; } while (of_node_cmp(port->name, "port")); - - /* Pick up the first endpoint in this port. */ - endpoint = of_get_next_child(port, NULL); - of_node_put(port); } - - return endpoint; } EXPORT_SYMBOL(v4l2_of_get_next_endpoint); -- cgit v1.1 From bc46263b84782439925e9f3fe4d545ae830869a4 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Wed, 12 Feb 2014 06:02:05 -0300 Subject: [media] lm3560: remove FSF address from the license There is no need to keep the FSF address inside each file. Moreover, it might change in future which will make this one obsolete. There is no functional change. Signed-off-by: Andy Shevchenko Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab --- drivers/media/i2c/lm3560.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/media/i2c/lm3560.c b/drivers/media/i2c/lm3560.c index d98ca3a..fea37a3 100644 --- a/drivers/media/i2c/lm3560.c +++ b/drivers/media/i2c/lm3560.c @@ -15,12 +15,6 @@ * WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA - * 02110-1301 USA - * */ #include -- cgit v1.1 From d1166b0f178d8dce66714288e25af1d4d6c6f2d3 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Wed, 12 Feb 2014 06:02:06 -0300 Subject: [media] lm3560: keep style for the comments Let's keep the style for all comments in the code, namely using small letters whenever it's possible. There is no functional change. Signed-off-by: Andy Shevchenko Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab --- drivers/media/i2c/lm3560.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/media/i2c/lm3560.c b/drivers/media/i2c/lm3560.c index fea37a3..93e5227 100644 --- a/drivers/media/i2c/lm3560.c +++ b/drivers/media/i2c/lm3560.c @@ -36,7 +36,7 @@ #define REG_FLAG 0xd0 #define REG_CONFIG1 0xe0 -/* Fault Mask */ +/* fault mask */ #define FAULT_TIMEOUT (1<<0) #define FAULT_OVERTEMP (1<<1) #define FAULT_SHORT_CIRCUIT (1<<2) @@ -47,7 +47,8 @@ enum led_enable { MODE_FLASH = 0x3, }; -/* struct lm3560_flash +/** + * struct lm3560_flash * * @pdata: platform data * @regmap: reg. map for i2c @@ -92,7 +93,7 @@ static int lm3560_mode_ctrl(struct lm3560_flash *flash) return rval; } -/* led1/2 enable/disable */ +/* led1/2 enable/disable */ static int lm3560_enable_ctrl(struct lm3560_flash *flash, enum lm3560_led_id led_no, bool on) { @@ -162,7 +163,7 @@ static int lm3560_flash_brt_ctrl(struct lm3560_flash *flash, return rval; } -/* V4L2 controls */ +/* v4l2 controls */ static int lm3560_get_ctrl(struct v4l2_ctrl *ctrl, enum lm3560_led_id led_no) { struct lm3560_flash *flash = to_lm3560_flash(ctrl, led_no); @@ -291,6 +292,7 @@ static int lm3560_init_controls(struct lm3560_flash *flash, const struct v4l2_ctrl_ops *ops = &lm3560_led_ctrl_ops[led_no]; v4l2_ctrl_handler_init(hdl, 8); + /* flash mode */ v4l2_ctrl_new_std_menu(hdl, ops, V4L2_CID_FLASH_LED_MODE, V4L2_FLASH_LED_MODE_TORCH, ~0x7, @@ -303,6 +305,7 @@ static int lm3560_init_controls(struct lm3560_flash *flash, /* flash strobe */ v4l2_ctrl_new_std(hdl, ops, V4L2_CID_FLASH_STROBE, 0, 0, 0, 0); + /* flash strobe stop */ v4l2_ctrl_new_std(hdl, ops, V4L2_CID_FLASH_STROBE_STOP, 0, 0, 0, 0); @@ -389,7 +392,7 @@ static int lm3560_init_device(struct lm3560_flash *flash) rval = lm3560_mode_ctrl(flash); if (rval < 0) return rval; - /* Reset faults */ + /* reset faults */ rval = regmap_read(flash->regmap, REG_FLAG, ®_val); return rval; } -- cgit v1.1 From 341ef565f8287695709266e7533995ffcdcc7a38 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Wed, 12 Feb 2014 06:02:07 -0300 Subject: [media] lm3560: prevent memory leak in case of pdata absence If we have no pdata defined and driver fails to register we leak memory. Converting to devm_kzalloc prevents this to happen. Signed-off-by: Andy Shevchenko Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab --- drivers/media/i2c/lm3560.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/media/i2c/lm3560.c b/drivers/media/i2c/lm3560.c index 93e5227..c23de59 100644 --- a/drivers/media/i2c/lm3560.c +++ b/drivers/media/i2c/lm3560.c @@ -416,8 +416,7 @@ static int lm3560_probe(struct i2c_client *client, /* if there is no platform data, use chip default value */ if (pdata == NULL) { - pdata = - kzalloc(sizeof(struct lm3560_platform_data), GFP_KERNEL); + pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL); if (pdata == NULL) return -ENODEV; pdata->peak = LM3560_PEAK_3600mA; -- cgit v1.1 From 00ae54a728e3ab8c08ab4c3e9f6a5beef9b4ca5a Mon Sep 17 00:00:00 2001 From: Daniel Jeong Date: Mon, 3 Mar 2014 06:52:09 -0300 Subject: [media] controls.xml: Document addtional Flash fault bits Descriptions for flash faults V4L2_FLASH_FAULT_UNDER_VOLTAGE, V4L2_FLASH_FAULT_INPUT_VOLTAGE, and V4L2_FLASH_FAULT_LED_OVER_TEMPERATURE. Removed spaces before tabs. Signed-off-by: Daniel Jeong Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/v4l/controls.xml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/Documentation/DocBook/media/v4l/controls.xml b/Documentation/DocBook/media/v4l/controls.xml index 28bf173..0340b962 100644 --- a/Documentation/DocBook/media/v4l/controls.xml +++ b/Documentation/DocBook/media/v4l/controls.xml @@ -4390,6 +4390,24 @@ interface and may change in the future. The flash controller has detected a short or open circuit condition on the indicator LED. + + V4L2_FLASH_FAULT_UNDER_VOLTAGE + Flash controller voltage to the flash LED + has been below the minimum limit specific to the flash + controller. + + + V4L2_FLASH_FAULT_INPUT_VOLTAGE + The input voltage of the flash controller is below + the limit under which strobing the flash at full current + will not be possible.The condition persists until this flag + is no longer set. + + + V4L2_FLASH_FAULT_LED_OVER_TEMPERATURE + The temperature of the LED has exceeded its + allowed upper limit. + -- cgit v1.1 From 935aa6b2e8a911e81baecec0537dd7e478dc8c91 Mon Sep 17 00:00:00 2001 From: Daniel Jeong Date: Mon, 3 Mar 2014 06:52:08 -0300 Subject: [media] v4l2-controls.h: Add addtional Flash fault bits Three Flash fault are added. V4L2_FLASH_FAULT_UNDER_VOLTAGE for the case low voltage below the min. limit. V4L2_FLASH_FAULT_INPUT_VOLTAGE for the case falling input voltage and chip adjust flash current not occur under voltage event. V4L2_FLASH_FAULT_LED_OVER_TEMPERATURE for the case the temperature exceed the maximun limit Signed-off-by: Daniel Jeong Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab --- include/uapi/linux/v4l2-controls.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h index e97101c..6501c0b 100644 --- a/include/uapi/linux/v4l2-controls.h +++ b/include/uapi/linux/v4l2-controls.h @@ -815,6 +815,9 @@ enum v4l2_flash_strobe_source { #define V4L2_FLASH_FAULT_SHORT_CIRCUIT (1 << 3) #define V4L2_FLASH_FAULT_OVER_CURRENT (1 << 4) #define V4L2_FLASH_FAULT_INDICATOR (1 << 5) +#define V4L2_FLASH_FAULT_UNDER_VOLTAGE (1 << 6) +#define V4L2_FLASH_FAULT_INPUT_VOLTAGE (1 << 7) +#define V4L2_FLASH_FAULT_LED_OVER_TEMPERATURE (1 << 8) #define V4L2_CID_FLASH_CHARGE (V4L2_CID_FLASH_CLASS_BASE + 11) #define V4L2_CID_FLASH_READY (V4L2_CID_FLASH_CLASS_BASE + 12) -- cgit v1.1 From dc76df5d48ba4e8b219269b890bb3043b05a8700 Mon Sep 17 00:00:00 2001 From: Daniel Jeong Date: Mon, 3 Mar 2014 06:52:10 -0300 Subject: [media] lm3646: add new dual LED Flash driver This patch adds the driver for the LM3646, dual LED Flash driver. The LM3646 has two 1.5A sync. boost converter with dual white current source. It is controlled via an I2C compatible interface. Each flash brightness, torch brightness and enable/disable can be controlled. Under voltage, input voltage monitor and thermal threshhold Faults are added. Please refer the datasheet http://www.ti.com/lit/ds/snvs962/snvs962.pdf Signed-off-by: Daniel Jeong Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab --- drivers/media/i2c/Kconfig | 9 + drivers/media/i2c/Makefile | 1 + drivers/media/i2c/lm3646.c | 414 +++++++++++++++++++++++++++++++++++++++++++++ include/media/lm3646.h | 87 ++++++++++ 4 files changed, 511 insertions(+) create mode 100644 drivers/media/i2c/lm3646.c create mode 100644 include/media/lm3646.h diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig index 4aa9c53..c7f2823 100644 --- a/drivers/media/i2c/Kconfig +++ b/drivers/media/i2c/Kconfig @@ -629,6 +629,15 @@ config VIDEO_LM3560 This is a driver for the lm3560 dual flash controllers. It controls flash, torch LEDs. +config VIDEO_LM3646 + tristate "LM3646 dual flash driver support" + depends on I2C && VIDEO_V4L2 && MEDIA_CONTROLLER + depends on MEDIA_CAMERA_SUPPORT + select REGMAP_I2C + ---help--- + This is a driver for the lm3646 dual flash controllers. It controls + flash, torch LEDs. + comment "Video improvement chips" config VIDEO_UPD64031A diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile index 48888ae..01b6bfc 100644 --- a/drivers/media/i2c/Makefile +++ b/drivers/media/i2c/Makefile @@ -72,6 +72,7 @@ obj-$(CONFIG_VIDEO_S5C73M3) += s5c73m3/ obj-$(CONFIG_VIDEO_ADP1653) += adp1653.o obj-$(CONFIG_VIDEO_AS3645A) += as3645a.o obj-$(CONFIG_VIDEO_LM3560) += lm3560.o +obj-$(CONFIG_VIDEO_LM3646) += lm3646.o obj-$(CONFIG_VIDEO_SMIAPP_PLL) += smiapp-pll.o obj-$(CONFIG_VIDEO_AK881X) += ak881x.o obj-$(CONFIG_VIDEO_IR_I2C) += ir-kbd-i2c.o diff --git a/drivers/media/i2c/lm3646.c b/drivers/media/i2c/lm3646.c new file mode 100644 index 0000000..626fb46 --- /dev/null +++ b/drivers/media/i2c/lm3646.c @@ -0,0 +1,414 @@ +/* + * drivers/media/i2c/lm3646.c + * General device driver for TI lm3646, Dual FLASH LED Driver + * + * Copyright (C) 2014 Texas Instruments + * + * Contact: Daniel Jeong + * Ldd-Mlp + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* registers definitions */ +#define REG_ENABLE 0x01 +#define REG_TORCH_BR 0x05 +#define REG_FLASH_BR 0x05 +#define REG_FLASH_TOUT 0x04 +#define REG_FLAG 0x08 +#define REG_STROBE_SRC 0x06 +#define REG_LED1_FLASH_BR 0x06 +#define REG_LED1_TORCH_BR 0x07 + +#define MASK_ENABLE 0x03 +#define MASK_TORCH_BR 0x70 +#define MASK_FLASH_BR 0x0F +#define MASK_FLASH_TOUT 0x07 +#define MASK_FLAG 0xFF +#define MASK_STROBE_SRC 0x80 + +/* Fault Mask */ +#define FAULT_TIMEOUT (1<<0) +#define FAULT_SHORT_CIRCUIT (1<<1) +#define FAULT_UVLO (1<<2) +#define FAULT_IVFM (1<<3) +#define FAULT_OCP (1<<4) +#define FAULT_OVERTEMP (1<<5) +#define FAULT_NTC_TRIP (1<<6) +#define FAULT_OVP (1<<7) + +enum led_mode { + MODE_SHDN = 0x0, + MODE_TORCH = 0x2, + MODE_FLASH = 0x3, +}; + +/* + * struct lm3646_flash + * + * @pdata: platform data + * @regmap: reg. map for i2c + * @lock: muxtex for serial access. + * @led_mode: V4L2 LED mode + * @ctrls_led: V4L2 contols + * @subdev_led: V4L2 subdev + * @mode_reg : mode register value + */ +struct lm3646_flash { + struct device *dev; + struct lm3646_platform_data *pdata; + struct regmap *regmap; + + struct v4l2_ctrl_handler ctrls_led; + struct v4l2_subdev subdev_led; + + u8 mode_reg; +}; + +#define to_lm3646_flash(_ctrl) \ + container_of(_ctrl->handler, struct lm3646_flash, ctrls_led) + +/* enable mode control */ +static int lm3646_mode_ctrl(struct lm3646_flash *flash, + enum v4l2_flash_led_mode led_mode) +{ + switch (led_mode) { + case V4L2_FLASH_LED_MODE_NONE: + return regmap_write(flash->regmap, + REG_ENABLE, flash->mode_reg | MODE_SHDN); + case V4L2_FLASH_LED_MODE_TORCH: + return regmap_write(flash->regmap, + REG_ENABLE, flash->mode_reg | MODE_TORCH); + case V4L2_FLASH_LED_MODE_FLASH: + return regmap_write(flash->regmap, + REG_ENABLE, flash->mode_reg | MODE_FLASH); + } + return -EINVAL; +} + +/* V4L2 controls */ +static int lm3646_get_ctrl(struct v4l2_ctrl *ctrl) +{ + struct lm3646_flash *flash = to_lm3646_flash(ctrl); + unsigned int reg_val; + int rval; + + if (ctrl->id != V4L2_CID_FLASH_FAULT) + return -EINVAL; + + rval = regmap_read(flash->regmap, REG_FLAG, ®_val); + if (rval < 0) + return rval; + + ctrl->val = 0; + if (reg_val & FAULT_TIMEOUT) + ctrl->val |= V4L2_FLASH_FAULT_TIMEOUT; + if (reg_val & FAULT_SHORT_CIRCUIT) + ctrl->val |= V4L2_FLASH_FAULT_SHORT_CIRCUIT; + if (reg_val & FAULT_UVLO) + ctrl->val |= V4L2_FLASH_FAULT_UNDER_VOLTAGE; + if (reg_val & FAULT_IVFM) + ctrl->val |= V4L2_FLASH_FAULT_INPUT_VOLTAGE; + if (reg_val & FAULT_OCP) + ctrl->val |= V4L2_FLASH_FAULT_OVER_CURRENT; + if (reg_val & FAULT_OVERTEMP) + ctrl->val |= V4L2_FLASH_FAULT_OVER_TEMPERATURE; + if (reg_val & FAULT_NTC_TRIP) + ctrl->val |= V4L2_FLASH_FAULT_LED_OVER_TEMPERATURE; + if (reg_val & FAULT_OVP) + ctrl->val |= V4L2_FLASH_FAULT_OVER_VOLTAGE; + + return 0; +} + +static int lm3646_set_ctrl(struct v4l2_ctrl *ctrl) +{ + struct lm3646_flash *flash = to_lm3646_flash(ctrl); + unsigned int reg_val; + int rval = -EINVAL; + + switch (ctrl->id) { + case V4L2_CID_FLASH_LED_MODE: + + if (ctrl->val != V4L2_FLASH_LED_MODE_FLASH) + return lm3646_mode_ctrl(flash, ctrl->val); + /* switch to SHDN mode before flash strobe on */ + return lm3646_mode_ctrl(flash, V4L2_FLASH_LED_MODE_NONE); + + case V4L2_CID_FLASH_STROBE_SOURCE: + return regmap_update_bits(flash->regmap, + REG_STROBE_SRC, MASK_STROBE_SRC, + (ctrl->val) << 7); + + case V4L2_CID_FLASH_STROBE: + + /* read and check current mode of chip to start flash */ + rval = regmap_read(flash->regmap, REG_ENABLE, ®_val); + if (rval < 0 || ((reg_val & MASK_ENABLE) != MODE_SHDN)) + return rval; + /* flash on */ + return lm3646_mode_ctrl(flash, V4L2_FLASH_LED_MODE_FLASH); + + case V4L2_CID_FLASH_STROBE_STOP: + + /* + * flash mode will be turned automatically + * from FLASH mode to SHDN mode after flash duration timeout + * read and check current mode of chip to stop flash + */ + rval = regmap_read(flash->regmap, REG_ENABLE, ®_val); + if (rval < 0) + return rval; + if ((reg_val & MASK_ENABLE) == MODE_FLASH) + return lm3646_mode_ctrl(flash, + V4L2_FLASH_LED_MODE_NONE); + return rval; + + case V4L2_CID_FLASH_TIMEOUT: + return regmap_update_bits(flash->regmap, + REG_FLASH_TOUT, MASK_FLASH_TOUT, + LM3646_FLASH_TOUT_ms_TO_REG + (ctrl->val)); + + case V4L2_CID_FLASH_INTENSITY: + return regmap_update_bits(flash->regmap, + REG_FLASH_BR, MASK_FLASH_BR, + LM3646_TOTAL_FLASH_BRT_uA_TO_REG + (ctrl->val)); + + case V4L2_CID_FLASH_TORCH_INTENSITY: + return regmap_update_bits(flash->regmap, + REG_TORCH_BR, MASK_TORCH_BR, + LM3646_TOTAL_TORCH_BRT_uA_TO_REG + (ctrl->val) << 4); + } + + return -EINVAL; +} + +static const struct v4l2_ctrl_ops lm3646_led_ctrl_ops = { + .g_volatile_ctrl = lm3646_get_ctrl, + .s_ctrl = lm3646_set_ctrl, +}; + +static int lm3646_init_controls(struct lm3646_flash *flash) +{ + struct v4l2_ctrl *fault; + struct v4l2_ctrl_handler *hdl = &flash->ctrls_led; + const struct v4l2_ctrl_ops *ops = &lm3646_led_ctrl_ops; + + v4l2_ctrl_handler_init(hdl, 8); + /* flash mode */ + v4l2_ctrl_new_std_menu(hdl, ops, V4L2_CID_FLASH_LED_MODE, + V4L2_FLASH_LED_MODE_TORCH, ~0x7, + V4L2_FLASH_LED_MODE_NONE); + + /* flash source */ + v4l2_ctrl_new_std_menu(hdl, ops, V4L2_CID_FLASH_STROBE_SOURCE, + 0x1, ~0x3, V4L2_FLASH_STROBE_SOURCE_SOFTWARE); + + /* flash strobe */ + v4l2_ctrl_new_std(hdl, ops, V4L2_CID_FLASH_STROBE, 0, 0, 0, 0); + /* flash strobe stop */ + v4l2_ctrl_new_std(hdl, ops, V4L2_CID_FLASH_STROBE_STOP, 0, 0, 0, 0); + + /* flash strobe timeout */ + v4l2_ctrl_new_std(hdl, ops, V4L2_CID_FLASH_TIMEOUT, + LM3646_FLASH_TOUT_MIN, + LM3646_FLASH_TOUT_MAX, + LM3646_FLASH_TOUT_STEP, flash->pdata->flash_timeout); + + /* max flash current */ + v4l2_ctrl_new_std(hdl, ops, V4L2_CID_FLASH_INTENSITY, + LM3646_TOTAL_FLASH_BRT_MIN, + LM3646_TOTAL_FLASH_BRT_MAX, + LM3646_TOTAL_FLASH_BRT_STEP, + LM3646_TOTAL_FLASH_BRT_MAX); + + /* max torch current */ + v4l2_ctrl_new_std(hdl, ops, V4L2_CID_FLASH_TORCH_INTENSITY, + LM3646_TOTAL_TORCH_BRT_MIN, + LM3646_TOTAL_TORCH_BRT_MAX, + LM3646_TOTAL_TORCH_BRT_STEP, + LM3646_TOTAL_TORCH_BRT_MAX); + + /* fault */ + fault = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_FLASH_FAULT, 0, + V4L2_FLASH_FAULT_OVER_VOLTAGE + | V4L2_FLASH_FAULT_OVER_TEMPERATURE + | V4L2_FLASH_FAULT_SHORT_CIRCUIT + | V4L2_FLASH_FAULT_TIMEOUT, 0, 0); + if (fault != NULL) + fault->flags |= V4L2_CTRL_FLAG_VOLATILE; + + if (hdl->error) + return hdl->error; + + flash->subdev_led.ctrl_handler = hdl; + return 0; +} + +/* initialize device */ +static const struct v4l2_subdev_ops lm3646_ops = { + .core = NULL, +}; + +static const struct regmap_config lm3646_regmap = { + .reg_bits = 8, + .val_bits = 8, + .max_register = 0xFF, +}; + +static int lm3646_subdev_init(struct lm3646_flash *flash) +{ + struct i2c_client *client = to_i2c_client(flash->dev); + int rval; + + v4l2_i2c_subdev_init(&flash->subdev_led, client, &lm3646_ops); + flash->subdev_led.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + strcpy(flash->subdev_led.name, LM3646_NAME); + rval = lm3646_init_controls(flash); + if (rval) + goto err_out; + rval = media_entity_init(&flash->subdev_led.entity, 0, NULL, 0); + if (rval < 0) + goto err_out; + flash->subdev_led.entity.type = MEDIA_ENT_T_V4L2_SUBDEV_FLASH; + return rval; + +err_out: + v4l2_ctrl_handler_free(&flash->ctrls_led); + return rval; +} + +static int lm3646_init_device(struct lm3646_flash *flash) +{ + unsigned int reg_val; + int rval; + + /* read the value of mode register to reduce redundant i2c accesses */ + rval = regmap_read(flash->regmap, REG_ENABLE, ®_val); + if (rval < 0) + return rval; + flash->mode_reg = reg_val & 0xfc; + + /* output disable */ + rval = lm3646_mode_ctrl(flash, V4L2_FLASH_LED_MODE_NONE); + if (rval < 0) + return rval; + + /* + * LED1 flash current setting + * LED2 flash current = Total(Max) flash current - LED1 flash current + */ + rval = regmap_update_bits(flash->regmap, + REG_LED1_FLASH_BR, 0x7F, + LM3646_LED1_FLASH_BRT_uA_TO_REG + (flash->pdata->led1_flash_brt)); + + if (rval < 0) + return rval; + + /* + * LED1 torch current setting + * LED2 torch current = Total(Max) torch current - LED1 torch current + */ + rval = regmap_update_bits(flash->regmap, + REG_LED1_TORCH_BR, 0x7F, + LM3646_LED1_TORCH_BRT_uA_TO_REG + (flash->pdata->led1_torch_brt)); + if (rval < 0) + return rval; + + /* Reset flag register */ + return regmap_read(flash->regmap, REG_FLAG, ®_val); +} + +static int lm3646_probe(struct i2c_client *client, + const struct i2c_device_id *devid) +{ + struct lm3646_flash *flash; + struct lm3646_platform_data *pdata = dev_get_platdata(&client->dev); + int rval; + + flash = devm_kzalloc(&client->dev, sizeof(*flash), GFP_KERNEL); + if (flash == NULL) + return -ENOMEM; + + flash->regmap = devm_regmap_init_i2c(client, &lm3646_regmap); + if (IS_ERR(flash->regmap)) + return PTR_ERR(flash->regmap); + + /* check device tree if there is no platform data */ + if (pdata == NULL) { + pdata = devm_kzalloc(&client->dev, + sizeof(struct lm3646_platform_data), + GFP_KERNEL); + if (pdata == NULL) + return -ENOMEM; + /* use default data in case of no platform data */ + pdata->flash_timeout = LM3646_FLASH_TOUT_MAX; + pdata->led1_torch_brt = LM3646_LED1_TORCH_BRT_MAX; + pdata->led1_flash_brt = LM3646_LED1_FLASH_BRT_MAX; + } + flash->pdata = pdata; + flash->dev = &client->dev; + + rval = lm3646_subdev_init(flash); + if (rval < 0) + return rval; + + rval = lm3646_init_device(flash); + if (rval < 0) + return rval; + + i2c_set_clientdata(client, flash); + + return 0; +} + +static int lm3646_remove(struct i2c_client *client) +{ + struct lm3646_flash *flash = i2c_get_clientdata(client); + + v4l2_device_unregister_subdev(&flash->subdev_led); + v4l2_ctrl_handler_free(&flash->ctrls_led); + media_entity_cleanup(&flash->subdev_led.entity); + + return 0; +} + +static const struct i2c_device_id lm3646_id_table[] = { + {LM3646_NAME, 0}, + {} +}; + +MODULE_DEVICE_TABLE(i2c, lm3646_id_table); + +static struct i2c_driver lm3646_i2c_driver = { + .driver = { + .name = LM3646_NAME, + }, + .probe = lm3646_probe, + .remove = lm3646_remove, + .id_table = lm3646_id_table, +}; + +module_i2c_driver(lm3646_i2c_driver); + +MODULE_AUTHOR("Daniel Jeong "); +MODULE_AUTHOR("Ldd Mlp "); +MODULE_DESCRIPTION("Texas Instruments LM3646 Dual Flash LED driver"); +MODULE_LICENSE("GPL"); diff --git a/include/media/lm3646.h b/include/media/lm3646.h new file mode 100644 index 0000000..c6acf5a --- /dev/null +++ b/include/media/lm3646.h @@ -0,0 +1,87 @@ +/* + * include/media/lm3646.h + * + * Copyright (C) 2014 Texas Instruments + * + * Contact: Daniel Jeong + * Ldd-Mlp + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + */ + +#ifndef __LM3646_H__ +#define __LM3646_H__ + +#include + +#define LM3646_NAME "lm3646" +#define LM3646_I2C_ADDR_REV1 (0x67) +#define LM3646_I2C_ADDR_REV0 (0x63) + +/* TOTAL FLASH Brightness Max + * min 93350uA, step 93750uA, max 1499600uA + */ +#define LM3646_TOTAL_FLASH_BRT_MIN 93350 +#define LM3646_TOTAL_FLASH_BRT_STEP 93750 +#define LM3646_TOTAL_FLASH_BRT_MAX 1499600 +#define LM3646_TOTAL_FLASH_BRT_uA_TO_REG(a) \ + ((a) < LM3646_TOTAL_FLASH_BRT_MIN ? 0 : \ + ((((a) - LM3646_TOTAL_FLASH_BRT_MIN) / LM3646_TOTAL_FLASH_BRT_STEP))) + +/* TOTAL TORCH Brightness Max + * min 23040uA, step 23430uA, max 187100uA + */ +#define LM3646_TOTAL_TORCH_BRT_MIN 23040 +#define LM3646_TOTAL_TORCH_BRT_STEP 23430 +#define LM3646_TOTAL_TORCH_BRT_MAX 187100 +#define LM3646_TOTAL_TORCH_BRT_uA_TO_REG(a) \ + ((a) < LM3646_TOTAL_TORCH_BRT_MIN ? 0 : \ + ((((a) - LM3646_TOTAL_TORCH_BRT_MIN) / LM3646_TOTAL_TORCH_BRT_STEP))) + +/* LED1 FLASH Brightness + * min 23040uA, step 11718uA, max 1499600uA + */ +#define LM3646_LED1_FLASH_BRT_MIN 23040 +#define LM3646_LED1_FLASH_BRT_STEP 11718 +#define LM3646_LED1_FLASH_BRT_MAX 1499600 +#define LM3646_LED1_FLASH_BRT_uA_TO_REG(a) \ + ((a) <= LM3646_LED1_FLASH_BRT_MIN ? 0 : \ + ((((a) - LM3646_LED1_FLASH_BRT_MIN) / LM3646_LED1_FLASH_BRT_STEP))+1) + +/* LED1 TORCH Brightness + * min 2530uA, step 1460uA, max 187100uA + */ +#define LM3646_LED1_TORCH_BRT_MIN 2530 +#define LM3646_LED1_TORCH_BRT_STEP 1460 +#define LM3646_LED1_TORCH_BRT_MAX 187100 +#define LM3646_LED1_TORCH_BRT_uA_TO_REG(a) \ + ((a) <= LM3646_LED1_TORCH_BRT_MIN ? 0 : \ + ((((a) - LM3646_LED1_TORCH_BRT_MIN) / LM3646_LED1_TORCH_BRT_STEP))+1) + +/* FLASH TIMEOUT DURATION + * min 50ms, step 50ms, max 400ms + */ +#define LM3646_FLASH_TOUT_MIN 50 +#define LM3646_FLASH_TOUT_STEP 50 +#define LM3646_FLASH_TOUT_MAX 400 +#define LM3646_FLASH_TOUT_ms_TO_REG(a) \ + ((a) <= LM3646_FLASH_TOUT_MIN ? 0 : \ + (((a) - LM3646_FLASH_TOUT_MIN) / LM3646_FLASH_TOUT_STEP)) + +/* struct lm3646_platform_data + * + * @flash_timeout: flash timeout + * @led1_flash_brt: led1 flash mode brightness, uA + * @led1_torch_brt: led1 torch mode brightness, uA + */ +struct lm3646_platform_data { + + u32 flash_timeout; + + u32 led1_flash_brt; + u32 led1_torch_brt; +}; + +#endif /* __LM3646_H__ */ -- cgit v1.1 From bc826d6e39fe5f09cbadf8723e9183e6331b586f Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Thu, 6 Mar 2014 07:24:21 -0300 Subject: [media] v4l2-compat-ioctl32: fix wrong VIDIOC_SUBDEV_G/S_EDID32 support The wrong ioctl numbers were used due to a copy-and-paste error. Signed-off-by: Hans Verkuil Cc: stable@vger.kernel.org # for v3.7 and up Acked-by: Laurent Pinchart Signed-off-by: Mauro Carvalho Chehab --- drivers/media/v4l2-core/v4l2-compat-ioctl32.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/media/v4l2-core/v4l2-compat-ioctl32.c b/drivers/media/v4l2-core/v4l2-compat-ioctl32.c index 1b18616..7e23e19 100644 --- a/drivers/media/v4l2-core/v4l2-compat-ioctl32.c +++ b/drivers/media/v4l2-core/v4l2-compat-ioctl32.c @@ -787,8 +787,8 @@ static int put_v4l2_subdev_edid32(struct v4l2_subdev_edid *kp, struct v4l2_subde #define VIDIOC_DQBUF32 _IOWR('V', 17, struct v4l2_buffer32) #define VIDIOC_ENUMSTD32 _IOWR('V', 25, struct v4l2_standard32) #define VIDIOC_ENUMINPUT32 _IOWR('V', 26, struct v4l2_input32) -#define VIDIOC_SUBDEV_G_EDID32 _IOWR('V', 63, struct v4l2_subdev_edid32) -#define VIDIOC_SUBDEV_S_EDID32 _IOWR('V', 64, struct v4l2_subdev_edid32) +#define VIDIOC_SUBDEV_G_EDID32 _IOWR('V', 40, struct v4l2_subdev_edid32) +#define VIDIOC_SUBDEV_S_EDID32 _IOWR('V', 41, struct v4l2_subdev_edid32) #define VIDIOC_TRY_FMT32 _IOWR('V', 64, struct v4l2_format32) #define VIDIOC_G_EXT_CTRLS32 _IOWR('V', 71, struct v4l2_ext_controls32) #define VIDIOC_S_EXT_CTRLS32 _IOWR('V', 72, struct v4l2_ext_controls32) -- cgit v1.1 From 254a47770163f9322333660ebdabf99ba49873da Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Tue, 4 Mar 2014 07:46:47 -0300 Subject: [media] v4l2: allow v4l2_subdev_edid to be used with video nodes Struct v4l2_subdev_edid and the VIDIOC_SUBDEV_G/S_EDID ioctls were specific for subdevices, but for hardware with a simple video pipeline you do not need/want to create subdevice nodes to just get/set the EDID. Move the v4l2_subdev_edid struct to v4l2-common.h and rename as v4l2_edid. Add the same ioctls to videodev2.h as well, thus allowing this API to be used with both video nodes and v4l-subdev nodes. Signed-off-by: Hans Verkuil Acked-by: Laurent Pinchart Signed-off-by: Mauro Carvalho Chehab --- include/uapi/linux/v4l2-common.h | 8 ++++++++ include/uapi/linux/v4l2-subdev.h | 14 +++++--------- include/uapi/linux/videodev2.h | 2 ++ 3 files changed, 15 insertions(+), 9 deletions(-) diff --git a/include/uapi/linux/v4l2-common.h b/include/uapi/linux/v4l2-common.h index 4f0667e..270db89 100644 --- a/include/uapi/linux/v4l2-common.h +++ b/include/uapi/linux/v4l2-common.h @@ -68,4 +68,12 @@ #define V4L2_SUBDEV_SEL_FLAG_SIZE_LE V4L2_SEL_FLAG_LE #define V4L2_SUBDEV_SEL_FLAG_KEEP_CONFIG V4L2_SEL_FLAG_KEEP_CONFIG +struct v4l2_edid { + __u32 pad; + __u32 start_block; + __u32 blocks; + __u32 reserved[5]; + __u8 __user *edid; +}; + #endif /* __V4L2_COMMON__ */ diff --git a/include/uapi/linux/v4l2-subdev.h b/include/uapi/linux/v4l2-subdev.h index a33c4da..87e0515 100644 --- a/include/uapi/linux/v4l2-subdev.h +++ b/include/uapi/linux/v4l2-subdev.h @@ -148,13 +148,8 @@ struct v4l2_subdev_selection { __u32 reserved[8]; }; -struct v4l2_subdev_edid { - __u32 pad; - __u32 start_block; - __u32 blocks; - __u32 reserved[5]; - __u8 __user *edid; -}; +/* Backwards compatibility define --- to be removed */ +#define v4l2_subdev_edid v4l2_edid #define VIDIOC_SUBDEV_G_FMT _IOWR('V', 4, struct v4l2_subdev_format) #define VIDIOC_SUBDEV_S_FMT _IOWR('V', 5, struct v4l2_subdev_format) @@ -174,7 +169,8 @@ struct v4l2_subdev_edid { _IOWR('V', 61, struct v4l2_subdev_selection) #define VIDIOC_SUBDEV_S_SELECTION \ _IOWR('V', 62, struct v4l2_subdev_selection) -#define VIDIOC_SUBDEV_G_EDID _IOWR('V', 40, struct v4l2_subdev_edid) -#define VIDIOC_SUBDEV_S_EDID _IOWR('V', 41, struct v4l2_subdev_edid) +/* These two G/S_EDID ioctls are identical to the ioctls in videodev2.h */ +#define VIDIOC_SUBDEV_G_EDID _IOWR('V', 40, struct v4l2_edid) +#define VIDIOC_SUBDEV_S_EDID _IOWR('V', 41, struct v4l2_edid) #endif diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h index 17acba8..339738a 100644 --- a/include/uapi/linux/videodev2.h +++ b/include/uapi/linux/videodev2.h @@ -1913,6 +1913,8 @@ struct v4l2_create_buffers { #define VIDIOC_QUERYMENU _IOWR('V', 37, struct v4l2_querymenu) #define VIDIOC_G_INPUT _IOR('V', 38, int) #define VIDIOC_S_INPUT _IOWR('V', 39, int) +#define VIDIOC_G_EDID _IOWR('V', 40, struct v4l2_edid) +#define VIDIOC_S_EDID _IOWR('V', 41, struct v4l2_edid) #define VIDIOC_G_OUTPUT _IOR('V', 46, int) #define VIDIOC_S_OUTPUT _IOWR('V', 47, int) #define VIDIOC_ENUMOUTPUT _IOWR('V', 48, struct v4l2_output) -- cgit v1.1 From dd519bb34a09d86db720f8a65e7dee1a85b2e90f Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Fri, 7 Mar 2014 07:18:37 -0300 Subject: [media] v4l2: add VIDIOC_G/S_EDID support to the v4l2 core Support this ioctl as part of the v4l2 core. Use the new ioctl name and struct v4l2_edid type in the existing core code. Signed-off-by: Hans Verkuil Acked-by: Laurent Pinchart Signed-off-by: Mauro Carvalho Chehab --- drivers/media/v4l2-core/v4l2-compat-ioctl32.c | 32 +++++++++++++-------------- drivers/media/v4l2-core/v4l2-dev.c | 2 ++ drivers/media/v4l2-core/v4l2-ioctl.c | 16 +++++++++++--- drivers/media/v4l2-core/v4l2-subdev.c | 4 ++-- include/media/v4l2-ioctl.h | 2 ++ include/media/v4l2-subdev.h | 4 ++-- 6 files changed, 37 insertions(+), 23 deletions(-) diff --git a/drivers/media/v4l2-core/v4l2-compat-ioctl32.c b/drivers/media/v4l2-core/v4l2-compat-ioctl32.c index 7e23e19..872f1ca 100644 --- a/drivers/media/v4l2-core/v4l2-compat-ioctl32.c +++ b/drivers/media/v4l2-core/v4l2-compat-ioctl32.c @@ -740,7 +740,7 @@ static int put_v4l2_event32(struct v4l2_event *kp, struct v4l2_event32 __user *u return 0; } -struct v4l2_subdev_edid32 { +struct v4l2_edid32 { __u32 pad; __u32 start_block; __u32 blocks; @@ -748,11 +748,11 @@ struct v4l2_subdev_edid32 { compat_caddr_t edid; }; -static int get_v4l2_subdev_edid32(struct v4l2_subdev_edid *kp, struct v4l2_subdev_edid32 __user *up) +static int get_v4l2_edid32(struct v4l2_edid *kp, struct v4l2_edid32 __user *up) { u32 tmp; - if (!access_ok(VERIFY_READ, up, sizeof(struct v4l2_subdev_edid32)) || + if (!access_ok(VERIFY_READ, up, sizeof(struct v4l2_edid32)) || get_user(kp->pad, &up->pad) || get_user(kp->start_block, &up->start_block) || get_user(kp->blocks, &up->blocks) || @@ -763,11 +763,11 @@ static int get_v4l2_subdev_edid32(struct v4l2_subdev_edid *kp, struct v4l2_subde return 0; } -static int put_v4l2_subdev_edid32(struct v4l2_subdev_edid *kp, struct v4l2_subdev_edid32 __user *up) +static int put_v4l2_edid32(struct v4l2_edid *kp, struct v4l2_edid32 __user *up) { u32 tmp = (u32)((unsigned long)kp->edid); - if (!access_ok(VERIFY_WRITE, up, sizeof(struct v4l2_subdev_edid32)) || + if (!access_ok(VERIFY_WRITE, up, sizeof(struct v4l2_edid32)) || put_user(kp->pad, &up->pad) || put_user(kp->start_block, &up->start_block) || put_user(kp->blocks, &up->blocks) || @@ -787,8 +787,8 @@ static int put_v4l2_subdev_edid32(struct v4l2_subdev_edid *kp, struct v4l2_subde #define VIDIOC_DQBUF32 _IOWR('V', 17, struct v4l2_buffer32) #define VIDIOC_ENUMSTD32 _IOWR('V', 25, struct v4l2_standard32) #define VIDIOC_ENUMINPUT32 _IOWR('V', 26, struct v4l2_input32) -#define VIDIOC_SUBDEV_G_EDID32 _IOWR('V', 40, struct v4l2_subdev_edid32) -#define VIDIOC_SUBDEV_S_EDID32 _IOWR('V', 41, struct v4l2_subdev_edid32) +#define VIDIOC_G_EDID32 _IOWR('V', 40, struct v4l2_edid32) +#define VIDIOC_S_EDID32 _IOWR('V', 41, struct v4l2_edid32) #define VIDIOC_TRY_FMT32 _IOWR('V', 64, struct v4l2_format32) #define VIDIOC_G_EXT_CTRLS32 _IOWR('V', 71, struct v4l2_ext_controls32) #define VIDIOC_S_EXT_CTRLS32 _IOWR('V', 72, struct v4l2_ext_controls32) @@ -816,7 +816,7 @@ static long do_video_ioctl(struct file *file, unsigned int cmd, unsigned long ar struct v4l2_ext_controls v2ecs; struct v4l2_event v2ev; struct v4l2_create_buffers v2crt; - struct v4l2_subdev_edid v2edid; + struct v4l2_edid v2edid; unsigned long vx; int vi; } karg; @@ -849,8 +849,8 @@ static long do_video_ioctl(struct file *file, unsigned int cmd, unsigned long ar case VIDIOC_S_OUTPUT32: cmd = VIDIOC_S_OUTPUT; break; case VIDIOC_CREATE_BUFS32: cmd = VIDIOC_CREATE_BUFS; break; case VIDIOC_PREPARE_BUF32: cmd = VIDIOC_PREPARE_BUF; break; - case VIDIOC_SUBDEV_G_EDID32: cmd = VIDIOC_SUBDEV_G_EDID; break; - case VIDIOC_SUBDEV_S_EDID32: cmd = VIDIOC_SUBDEV_S_EDID; break; + case VIDIOC_G_EDID32: cmd = VIDIOC_G_EDID; break; + case VIDIOC_S_EDID32: cmd = VIDIOC_S_EDID; break; } switch (cmd) { @@ -868,9 +868,9 @@ static long do_video_ioctl(struct file *file, unsigned int cmd, unsigned long ar compatible_arg = 0; break; - case VIDIOC_SUBDEV_G_EDID: - case VIDIOC_SUBDEV_S_EDID: - err = get_v4l2_subdev_edid32(&karg.v2edid, up); + case VIDIOC_G_EDID: + case VIDIOC_S_EDID: + err = get_v4l2_edid32(&karg.v2edid, up); compatible_arg = 0; break; @@ -966,9 +966,9 @@ static long do_video_ioctl(struct file *file, unsigned int cmd, unsigned long ar err = put_v4l2_event32(&karg.v2ev, up); break; - case VIDIOC_SUBDEV_G_EDID: - case VIDIOC_SUBDEV_S_EDID: - err = put_v4l2_subdev_edid32(&karg.v2edid, up); + case VIDIOC_G_EDID: + case VIDIOC_S_EDID: + err = put_v4l2_edid32(&karg.v2edid, up); break; case VIDIOC_G_FMT: diff --git a/drivers/media/v4l2-core/v4l2-dev.c b/drivers/media/v4l2-core/v4l2-dev.c index 95112f6..634d863 100644 --- a/drivers/media/v4l2-core/v4l2-dev.c +++ b/drivers/media/v4l2-core/v4l2-dev.c @@ -701,6 +701,7 @@ static void determine_valid_ioctls(struct video_device *vdev) SET_VALID_IOCTL(ops, VIDIOC_G_AUDIO, vidioc_g_audio); SET_VALID_IOCTL(ops, VIDIOC_S_AUDIO, vidioc_s_audio); SET_VALID_IOCTL(ops, VIDIOC_QUERY_DV_TIMINGS, vidioc_query_dv_timings); + SET_VALID_IOCTL(ops, VIDIOC_S_EDID, vidioc_s_edid); } if (is_tx) { SET_VALID_IOCTL(ops, VIDIOC_ENUMOUTPUT, vidioc_enum_output); @@ -726,6 +727,7 @@ static void determine_valid_ioctls(struct video_device *vdev) SET_VALID_IOCTL(ops, VIDIOC_G_DV_TIMINGS, vidioc_g_dv_timings); SET_VALID_IOCTL(ops, VIDIOC_ENUM_DV_TIMINGS, vidioc_enum_dv_timings); SET_VALID_IOCTL(ops, VIDIOC_DV_TIMINGS_CAP, vidioc_dv_timings_cap); + SET_VALID_IOCTL(ops, VIDIOC_G_EDID, vidioc_g_edid); } if (is_tx && (is_radio || is_sdr)) { /* radio transmitter only ioctls */ diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c index 95dd4f1..6536e15 100644 --- a/drivers/media/v4l2-core/v4l2-ioctl.c +++ b/drivers/media/v4l2-core/v4l2-ioctl.c @@ -844,6 +844,14 @@ static void v4l_print_freq_band(const void *arg, bool write_only) p->rangehigh, p->modulation); } +static void v4l_print_edid(const void *arg, bool write_only) +{ + const struct v4l2_edid *p = arg; + + pr_cont("pad=%u, start_block=%u, blocks=%u\n", + p->pad, p->start_block, p->blocks); +} + static void v4l_print_u32(const void *arg, bool write_only) { pr_cont("value=%u\n", *(const u32 *)arg); @@ -2062,6 +2070,8 @@ static struct v4l2_ioctl_info v4l2_ioctls[] = { IOCTL_INFO_FNC(VIDIOC_QUERYMENU, v4l_querymenu, v4l_print_querymenu, INFO_FL_CTRL | INFO_FL_CLEAR(v4l2_querymenu, index)), IOCTL_INFO_STD(VIDIOC_G_INPUT, vidioc_g_input, v4l_print_u32, 0), IOCTL_INFO_FNC(VIDIOC_S_INPUT, v4l_s_input, v4l_print_u32, INFO_FL_PRIO), + IOCTL_INFO_STD(VIDIOC_G_EDID, vidioc_g_edid, v4l_print_edid, INFO_FL_CLEAR(v4l2_edid, edid)), + IOCTL_INFO_STD(VIDIOC_S_EDID, vidioc_s_edid, v4l_print_edid, INFO_FL_PRIO | INFO_FL_CLEAR(v4l2_edid, edid)), IOCTL_INFO_STD(VIDIOC_G_OUTPUT, vidioc_g_output, v4l_print_u32, 0), IOCTL_INFO_FNC(VIDIOC_S_OUTPUT, v4l_s_output, v4l_print_u32, INFO_FL_PRIO), IOCTL_INFO_FNC(VIDIOC_ENUMOUTPUT, v4l_enumoutput, v4l_print_enumoutput, INFO_FL_CLEAR(v4l2_output, index)), @@ -2274,9 +2284,9 @@ static int check_array_args(unsigned int cmd, void *parg, size_t *array_size, break; } - case VIDIOC_SUBDEV_G_EDID: - case VIDIOC_SUBDEV_S_EDID: { - struct v4l2_subdev_edid *edid = parg; + case VIDIOC_G_EDID: + case VIDIOC_S_EDID: { + struct v4l2_edid *edid = parg; if (edid->blocks) { if (edid->blocks > 256) { diff --git a/drivers/media/v4l2-core/v4l2-subdev.c b/drivers/media/v4l2-core/v4l2-subdev.c index 60d2550..aea84ac 100644 --- a/drivers/media/v4l2-core/v4l2-subdev.c +++ b/drivers/media/v4l2-core/v4l2-subdev.c @@ -349,10 +349,10 @@ static long subdev_do_ioctl(struct file *file, unsigned int cmd, void *arg) sd, pad, set_selection, subdev_fh, sel); } - case VIDIOC_SUBDEV_G_EDID: + case VIDIOC_G_EDID: return v4l2_subdev_call(sd, pad, get_edid, arg); - case VIDIOC_SUBDEV_S_EDID: + case VIDIOC_S_EDID: return v4l2_subdev_call(sd, pad, set_edid, arg); #endif default: diff --git a/include/media/v4l2-ioctl.h b/include/media/v4l2-ioctl.h index 8be32f5..50cf7c1 100644 --- a/include/media/v4l2-ioctl.h +++ b/include/media/v4l2-ioctl.h @@ -273,6 +273,8 @@ struct v4l2_ioctl_ops { struct v4l2_enum_dv_timings *timings); int (*vidioc_dv_timings_cap) (struct file *file, void *fh, struct v4l2_dv_timings_cap *cap); + int (*vidioc_g_edid) (struct file *file, void *fh, struct v4l2_edid *edid); + int (*vidioc_s_edid) (struct file *file, void *fh, struct v4l2_edid *edid); int (*vidioc_subscribe_event) (struct v4l2_fh *fh, const struct v4l2_event_subscription *sub); diff --git a/include/media/v4l2-subdev.h b/include/media/v4l2-subdev.h index 1752530..855c928 100644 --- a/include/media/v4l2-subdev.h +++ b/include/media/v4l2-subdev.h @@ -507,8 +507,8 @@ struct v4l2_subdev_pad_ops { struct v4l2_subdev_selection *sel); int (*set_selection)(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh, struct v4l2_subdev_selection *sel); - int (*get_edid)(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid); - int (*set_edid)(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid); + int (*get_edid)(struct v4l2_subdev *sd, struct v4l2_edid *edid); + int (*set_edid)(struct v4l2_subdev *sd, struct v4l2_edid *edid); #ifdef CONFIG_MEDIA_CONTROLLER int (*link_validate)(struct v4l2_subdev *sd, struct media_link *link, struct v4l2_subdev_format *source_fmt, -- cgit v1.1 From b09dfac83201812bf359e32a17afc7f6763ae379 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Tue, 4 Mar 2014 08:05:19 -0300 Subject: [media] adv*: replace the deprecated v4l2_subdev_edid by v4l2_edid Signed-off-by: Hans Verkuil Acked-by: Laurent Pinchart Signed-off-by: Mauro Carvalho Chehab --- drivers/media/i2c/ad9389b.c | 2 +- drivers/media/i2c/adv7511.c | 2 +- drivers/media/i2c/adv7604.c | 4 ++-- drivers/media/i2c/adv7842.c | 4 ++-- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/media/i2c/ad9389b.c b/drivers/media/i2c/ad9389b.c index 83225d6..1b7ecfd 100644 --- a/drivers/media/i2c/ad9389b.c +++ b/drivers/media/i2c/ad9389b.c @@ -573,7 +573,7 @@ static const struct v4l2_subdev_core_ops ad9389b_core_ops = { /* ------------------------------ PAD OPS ------------------------------ */ -static int ad9389b_get_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid) +static int ad9389b_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) { struct ad9389b_state *state = get_ad9389b_state(sd); diff --git a/drivers/media/i2c/adv7511.c b/drivers/media/i2c/adv7511.c index ee61894..942ca4b 100644 --- a/drivers/media/i2c/adv7511.c +++ b/drivers/media/i2c/adv7511.c @@ -597,7 +597,7 @@ static int adv7511_isr(struct v4l2_subdev *sd, u32 status, bool *handled) return 0; } -static int adv7511_get_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid) +static int adv7511_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) { struct adv7511_state *state = get_adv7511_state(sd); diff --git a/drivers/media/i2c/adv7604.c b/drivers/media/i2c/adv7604.c index 71c8570..98cc540 100644 --- a/drivers/media/i2c/adv7604.c +++ b/drivers/media/i2c/adv7604.c @@ -1658,7 +1658,7 @@ static int adv7604_isr(struct v4l2_subdev *sd, u32 status, bool *handled) return 0; } -static int adv7604_get_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid) +static int adv7604_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) { struct adv7604_state *state = to_state(sd); u8 *data = NULL; @@ -1728,7 +1728,7 @@ static int get_edid_spa_location(const u8 *edid) return -1; } -static int adv7604_set_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid) +static int adv7604_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) { struct adv7604_state *state = to_state(sd); int spa_loc; diff --git a/drivers/media/i2c/adv7842.c b/drivers/media/i2c/adv7842.c index 88ce9dc..636ac08 100644 --- a/drivers/media/i2c/adv7842.c +++ b/drivers/media/i2c/adv7842.c @@ -2014,7 +2014,7 @@ static int adv7842_isr(struct v4l2_subdev *sd, u32 status, bool *handled) return 0; } -static int adv7842_get_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid) +static int adv7842_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) { struct adv7842_state *state = to_state(sd); u8 *data = NULL; @@ -2054,7 +2054,7 @@ static int adv7842_get_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edi return 0; } -static int adv7842_set_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *e) +static int adv7842_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *e) { struct adv7842_state *state = to_state(sd); int err = 0; -- cgit v1.1 From e25436581f4117a0df9bf5539f6a7702a78df317 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Fri, 7 Mar 2014 11:17:33 -0300 Subject: [media] DocBook v4l2: update the G/S_EDID documentation Document that it is now possible to call G/S_EDID from video nodes, not just sub-device nodes. Add a note that -EINVAL will be returned if the pad does not support EDIDs. Signed-off-by: Hans Verkuil Acked-by: Laurent Pinchart Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/v4l/v4l2.xml | 2 +- Documentation/DocBook/media/v4l/vidioc-g-edid.xml | 162 +++++++++++++++++++++ .../DocBook/media/v4l/vidioc-subdev-g-edid.xml | 152 ------------------- 3 files changed, 163 insertions(+), 153 deletions(-) create mode 100644 Documentation/DocBook/media/v4l/vidioc-g-edid.xml delete mode 100644 Documentation/DocBook/media/v4l/vidioc-subdev-g-edid.xml diff --git a/Documentation/DocBook/media/v4l/v4l2.xml b/Documentation/DocBook/media/v4l/v4l2.xml index 61a7bb1..b445161 100644 --- a/Documentation/DocBook/media/v4l/v4l2.xml +++ b/Documentation/DocBook/media/v4l/v4l2.xml @@ -607,6 +607,7 @@ and discussions on the V4L mailing list. &sub-g-crop; &sub-g-ctrl; &sub-g-dv-timings; + &sub-g-edid; &sub-g-enc-index; &sub-g-ext-ctrls; &sub-g-fbuf; @@ -638,7 +639,6 @@ and discussions on the V4L mailing list. &sub-subdev-enum-frame-size; &sub-subdev-enum-mbus-code; &sub-subdev-g-crop; - &sub-subdev-g-edid; &sub-subdev-g-fmt; &sub-subdev-g-frame-interval; &sub-subdev-g-selection; diff --git a/Documentation/DocBook/media/v4l/vidioc-g-edid.xml b/Documentation/DocBook/media/v4l/vidioc-g-edid.xml new file mode 100644 index 0000000..ce4563b --- /dev/null +++ b/Documentation/DocBook/media/v4l/vidioc-g-edid.xml @@ -0,0 +1,162 @@ + + + ioctl VIDIOC_G_EDID, VIDIOC_S_EDID + &manvol; + + + + VIDIOC_G_EDID + VIDIOC_S_EDID + Get or set the EDID of a video receiver/transmitter + + + + + + int ioctl + int fd + int request + struct v4l2_edid *argp + + + + + int ioctl + int fd + int request + const struct v4l2_edid *argp + + + + + + Arguments + + + + fd + + &fd; + + + + request + + VIDIOC_G_EDID, VIDIOC_S_EDID + + + + argp + + + + + + + + + Description + These ioctls can be used to get or set an EDID associated with an input + from a receiver or an output of a transmitter device. They can be + used with subdevice nodes (/dev/v4l-subdevX) or with video nodes (/dev/videoX). + + When used with video nodes the pad field represents the + input (for video capture devices) or output (for video output devices) index as + is returned by &VIDIOC-ENUMINPUT; and &VIDIOC-ENUMOUTPUT; respectively. When used + with subdevice nodes the pad field represents the + input or output pad of the subdevice. If there is no EDID support for the given + pad value, then the &EINVAL; will be returned. + + To get the EDID data the application has to fill in the pad, + start_block, blocks and edid + fields and call VIDIOC_G_EDID. The current EDID from block + start_block and of size blocks + will be placed in the memory edid points to. The edid + pointer must point to memory at least blocks * 128 bytes + large (the size of one block is 128 bytes). + + If there are fewer blocks than specified, then the driver will set blocks + to the actual number of blocks. If there are no EDID blocks available at all, then the error code + ENODATA is set. + + If blocks have to be retrieved from the sink, then this call will block until they + have been read. + + To set the EDID blocks of a receiver the application has to fill in the pad, + blocks and edid fields and set + start_block to 0. It is not possible to set part of an EDID, + it is always all or nothing. Setting the EDID data is only valid for receivers as it makes + no sense for a transmitter. + + The driver assumes that the full EDID is passed in. If there are more EDID blocks than + the hardware can handle then the EDID is not written, but instead the error code E2BIG is set + and blocks is set to the maximum that the hardware supports. + If start_block is any + value other than 0 then the error code EINVAL is set. + + To disable an EDID you set blocks to 0. Depending on the + hardware this will drive the hotplug pin low and/or block the source from reading the EDID + data in some way. In any case, the end result is the same: the EDID is no longer available. + + +
+ struct <structname>v4l2_edid</structname> + + &cs-str; + + + __u32 + pad + Pad for which to get/set the EDID blocks. When used with a video device + node the pad represents the input or output index as returned by + &VIDIOC-ENUMINPUT; and &VIDIOC-ENUMOUTPUT; respectively. + + + __u32 + start_block + Read the EDID from starting with this block. Must be 0 when setting + the EDID. + + + __u32 + blocks + The number of blocks to get or set. Must be less or equal to 256 (the + maximum number of blocks as defined by the standard). When you set the EDID and + blocks is 0, then the EDID is disabled or erased. + + + __u8 * + edid + Pointer to memory that contains the EDID. The minimum size is + blocks * 128. + + + __u32 + reserved[5] + Reserved for future extensions. Applications and drivers must + set the array to zero. + + + +
+ + + + &return-value; + + + + ENODATA + + The EDID data is not available. + + + + E2BIG + + The EDID data you provided is more than the hardware can handle. + + + + + diff --git a/Documentation/DocBook/media/v4l/vidioc-subdev-g-edid.xml b/Documentation/DocBook/media/v4l/vidioc-subdev-g-edid.xml deleted file mode 100644 index bbd18f0..0000000 --- a/Documentation/DocBook/media/v4l/vidioc-subdev-g-edid.xml +++ /dev/null @@ -1,152 +0,0 @@ - - - ioctl VIDIOC_SUBDEV_G_EDID, VIDIOC_SUBDEV_S_EDID - &manvol; - - - - VIDIOC_SUBDEV_G_EDID - VIDIOC_SUBDEV_S_EDID - Get or set the EDID of a video receiver/transmitter - - - - - - int ioctl - int fd - int request - struct v4l2_subdev_edid *argp - - - - - int ioctl - int fd - int request - const struct v4l2_subdev_edid *argp - - - - - - Arguments - - - - fd - - &fd; - - - - request - - VIDIOC_SUBDEV_G_EDID, VIDIOC_SUBDEV_S_EDID - - - - argp - - - - - - - - - Description - These ioctls can be used to get or set an EDID associated with an input pad - from a receiver or an output pad of a transmitter subdevice. - - To get the EDID data the application has to fill in the pad, - start_block, blocks and edid - fields and call VIDIOC_SUBDEV_G_EDID. The current EDID from block - start_block and of size blocks - will be placed in the memory edid points to. The edid - pointer must point to memory at least blocks * 128 bytes - large (the size of one block is 128 bytes). - - If there are fewer blocks than specified, then the driver will set blocks - to the actual number of blocks. If there are no EDID blocks available at all, then the error code - ENODATA is set. - - If blocks have to be retrieved from the sink, then this call will block until they - have been read. - - To set the EDID blocks of a receiver the application has to fill in the pad, - blocks and edid fields and set - start_block to 0. It is not possible to set part of an EDID, - it is always all or nothing. Setting the EDID data is only valid for receivers as it makes - no sense for a transmitter. - - The driver assumes that the full EDID is passed in. If there are more EDID blocks than - the hardware can handle then the EDID is not written, but instead the error code E2BIG is set - and blocks is set to the maximum that the hardware supports. - If start_block is any - value other than 0 then the error code EINVAL is set. - - To disable an EDID you set blocks to 0. Depending on the - hardware this will drive the hotplug pin low and/or block the source from reading the EDID - data in some way. In any case, the end result is the same: the EDID is no longer available. - - - - struct <structname>v4l2_subdev_edid</structname> - - &cs-str; - - - __u32 - pad - Pad for which to get/set the EDID blocks. - - - __u32 - start_block - Read the EDID from starting with this block. Must be 0 when setting - the EDID. - - - __u32 - blocks - The number of blocks to get or set. Must be less or equal to 256 (the - maximum number of blocks as defined by the standard). When you set the EDID and - blocks is 0, then the EDID is disabled or erased. - - - __u8 * - edid - Pointer to memory that contains the EDID. The minimum size is - blocks * 128. - - - __u32 - reserved[5] - Reserved for future extensions. Applications and drivers must - set the array to zero. - - - -
- - - - &return-value; - - - - ENODATA - - The EDID data is not available. - - - - E2BIG - - The EDID data you provided is more than the hardware can handle. - - - - - -- cgit v1.1 From 297a0ae32bf84c8ae135971eb21f18ee5f4ca3ea Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Fri, 7 Mar 2014 13:14:27 -0300 Subject: [media] adv7180: Fix remove order The mutex is used in the subdev callbacks, so unregister the subdev before the mutex is destroyed. Signed-off-by: Lars-Peter Clausen Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/i2c/adv7180.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/media/i2c/adv7180.c b/drivers/media/i2c/adv7180.c index d7d99f1..1a3622a 100644 --- a/drivers/media/i2c/adv7180.c +++ b/drivers/media/i2c/adv7180.c @@ -616,8 +616,8 @@ static int adv7180_probe(struct i2c_client *client, err_free_ctrl: adv7180_exit_controls(state); err_unreg_subdev: - mutex_destroy(&state->mutex); v4l2_device_unregister_subdev(sd); + mutex_destroy(&state->mutex); err: printk(KERN_ERR KBUILD_MODNAME ": Failed to probe: %d\n", ret); return ret; @@ -640,8 +640,8 @@ static int adv7180_remove(struct i2c_client *client) } } - mutex_destroy(&state->mutex); v4l2_device_unregister_subdev(sd); + mutex_destroy(&state->mutex); return 0; } -- cgit v1.1 From b13f4af25c0a36d74a69f7d30e2a28fa941e99b5 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Fri, 7 Mar 2014 13:14:28 -0300 Subject: [media] adv7180: Free control handler on remove() Make sure to free the control handler when the device is removed. Signed-off-by: Lars-Peter Clausen Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/i2c/adv7180.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/media/i2c/adv7180.c b/drivers/media/i2c/adv7180.c index 1a3622a..2359fd8 100644 --- a/drivers/media/i2c/adv7180.c +++ b/drivers/media/i2c/adv7180.c @@ -641,6 +641,7 @@ static int adv7180_remove(struct i2c_client *client) } v4l2_device_unregister_subdev(sd); + adv7180_exit_controls(state); mutex_destroy(&state->mutex); return 0; } -- cgit v1.1 From 3de0a911561ceb3fcd1211faecf05e68b60105a1 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Fri, 7 Mar 2014 13:14:29 -0300 Subject: [media] adv7180: Remove unnecessary v4l2_device_unregister_subdev() from probe error path The device can't possibly be registered at this point, so no need to to call v4l2_device_unregister_subdev(). Signed-off-by: Lars-Peter Clausen Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/i2c/adv7180.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/media/i2c/adv7180.c b/drivers/media/i2c/adv7180.c index 2359fd8..85cb4e9 100644 --- a/drivers/media/i2c/adv7180.c +++ b/drivers/media/i2c/adv7180.c @@ -616,7 +616,6 @@ static int adv7180_probe(struct i2c_client *client, err_free_ctrl: adv7180_exit_controls(state); err_unreg_subdev: - v4l2_device_unregister_subdev(sd); mutex_destroy(&state->mutex); err: printk(KERN_ERR KBUILD_MODNAME ": Failed to probe: %d\n", ret); -- cgit v1.1 From 7933c177fa5235f250203ccfe9d8402b11129144 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Fri, 7 Mar 2014 13:14:30 -0300 Subject: [media] adv7180: Remove duplicated probe error message The device driver core already prints out a very similar message when a driver fails to probe. No need to print one in the driver itself. Signed-off-by: Lars-Peter Clausen Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/i2c/adv7180.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/media/i2c/adv7180.c b/drivers/media/i2c/adv7180.c index 85cb4e9..98a3ff1 100644 --- a/drivers/media/i2c/adv7180.c +++ b/drivers/media/i2c/adv7180.c @@ -618,7 +618,6 @@ err_free_ctrl: err_unreg_subdev: mutex_destroy(&state->mutex); err: - printk(KERN_ERR KBUILD_MODNAME ": Failed to probe: %d\n", ret); return ret; } -- cgit v1.1 From 0c25534d456535a879aba482dc14795213312514 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Fri, 7 Mar 2014 13:14:31 -0300 Subject: [media] adv7180: Use threaded IRQ instead of IRQ + workqueue The proper way to handle IRQs that need to be able to sleep in their IRQ handler is to use a threaded IRQ. Signed-off-by: Lars-Peter Clausen Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/i2c/adv7180.c | 33 +++++---------------------------- 1 file changed, 5 insertions(+), 28 deletions(-) diff --git a/drivers/media/i2c/adv7180.c b/drivers/media/i2c/adv7180.c index 98a3ff1..c750aae 100644 --- a/drivers/media/i2c/adv7180.c +++ b/drivers/media/i2c/adv7180.c @@ -123,7 +123,6 @@ struct adv7180_state { struct v4l2_ctrl_handler ctrl_hdl; struct v4l2_subdev sd; - struct work_struct work; struct mutex mutex; /* mutual excl. when accessing chip */ int irq; v4l2_std_id curr_norm; @@ -449,10 +448,9 @@ static const struct v4l2_subdev_ops adv7180_ops = { .video = &adv7180_video_ops, }; -static void adv7180_work(struct work_struct *work) +static irqreturn_t adv7180_irq(int irq, void *devid) { - struct adv7180_state *state = container_of(work, struct adv7180_state, - work); + struct adv7180_state *state = devid; struct i2c_client *client = v4l2_get_subdevdata(&state->sd); u8 isr3; @@ -468,17 +466,6 @@ static void adv7180_work(struct work_struct *work) __adv7180_status(client, NULL, &state->curr_norm); mutex_unlock(&state->mutex); - enable_irq(state->irq); -} - -static irqreturn_t adv7180_irq(int irq, void *devid) -{ - struct adv7180_state *state = devid; - - schedule_work(&state->work); - - disable_irq_nosync(state->irq); - return IRQ_HANDLED; } @@ -533,8 +520,8 @@ static int init_device(struct i2c_client *client, struct adv7180_state *state) /* register for interrupts */ if (state->irq > 0) { - ret = request_irq(state->irq, adv7180_irq, 0, KBUILD_MODNAME, - state); + ret = request_threaded_irq(state->irq, NULL, adv7180_irq, + IRQF_ONESHOT, KBUILD_MODNAME, state); if (ret) return ret; @@ -598,7 +585,6 @@ static int adv7180_probe(struct i2c_client *client, } state->irq = client->irq; - INIT_WORK(&state->work, adv7180_work); mutex_init(&state->mutex); state->autodetect = true; state->input = 0; @@ -626,17 +612,8 @@ static int adv7180_remove(struct i2c_client *client) struct v4l2_subdev *sd = i2c_get_clientdata(client); struct adv7180_state *state = to_state(sd); - if (state->irq > 0) { + if (state->irq > 0) free_irq(client->irq, state); - if (cancel_work_sync(&state->work)) { - /* - * Work was pending, therefore we need to enable - * IRQ here to balance the disable_irq() done in the - * interrupt handler. - */ - enable_irq(state->irq); - } - } v4l2_device_unregister_subdev(sd); adv7180_exit_controls(state); -- cgit v1.1 From fa5b7945aefdbcd4419f0b8872ce67866d8071e3 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Fri, 7 Mar 2014 13:14:32 -0300 Subject: [media] adv7180: Add support for async device registration Add support for async device registration to the adv7180 driver. Signed-off-by: Lars-Peter Clausen Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/i2c/adv7180.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/media/i2c/adv7180.c b/drivers/media/i2c/adv7180.c index c750aae..623cec5 100644 --- a/drivers/media/i2c/adv7180.c +++ b/drivers/media/i2c/adv7180.c @@ -597,8 +597,16 @@ static int adv7180_probe(struct i2c_client *client, ret = init_device(client, state); if (ret) goto err_free_ctrl; + + ret = v4l2_async_register_subdev(sd); + if (ret) + goto err_free_irq; + return 0; +err_free_irq: + if (state->irq > 0) + free_irq(client->irq, state); err_free_ctrl: adv7180_exit_controls(state); err_unreg_subdev: @@ -612,6 +620,8 @@ static int adv7180_remove(struct i2c_client *client) struct v4l2_subdev *sd = i2c_get_clientdata(client); struct adv7180_state *state = to_state(sd); + v4l2_async_unregister_subdev(sd); + if (state->irq > 0) free_irq(client->irq, state); -- cgit v1.1 From e246c3332daa885e911630922ee08c7956dfea0e Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Mon, 10 Mar 2014 14:05:39 -0300 Subject: [media] adv7180: Add support for power down The adv7180 has a low power mode in which the analog and the digital processing section are shut down. Implement the s_power callback to let bridge drivers put the part into low power mode when not needed. Signed-off-by: Lars-Peter Clausen Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/i2c/adv7180.c | 52 ++++++++++++++++++++++++++++++++++++--------- 1 file changed, 42 insertions(+), 10 deletions(-) diff --git a/drivers/media/i2c/adv7180.c b/drivers/media/i2c/adv7180.c index 623cec5..9cfc9a3 100644 --- a/drivers/media/i2c/adv7180.c +++ b/drivers/media/i2c/adv7180.c @@ -127,6 +127,7 @@ struct adv7180_state { int irq; v4l2_std_id curr_norm; bool autodetect; + bool powered; u8 input; }; #define to_adv7180_sd(_ctrl) (&container_of(_ctrl->handler, \ @@ -311,6 +312,37 @@ out: return ret; } +static int adv7180_set_power(struct adv7180_state *state, + struct i2c_client *client, bool on) +{ + u8 val; + + if (on) + val = ADV7180_PWR_MAN_ON; + else + val = ADV7180_PWR_MAN_OFF; + + return i2c_smbus_write_byte_data(client, ADV7180_PWR_MAN_REG, val); +} + +static int adv7180_s_power(struct v4l2_subdev *sd, int on) +{ + struct adv7180_state *state = to_state(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + ret = mutex_lock_interruptible(&state->mutex); + if (ret) + return ret; + + ret = adv7180_set_power(state, client, on); + if (ret == 0) + state->powered = on; + + mutex_unlock(&state->mutex); + return ret; +} + static int adv7180_s_ctrl(struct v4l2_ctrl *ctrl) { struct v4l2_subdev *sd = to_adv7180_sd(ctrl); @@ -441,6 +473,7 @@ static const struct v4l2_subdev_video_ops adv7180_video_ops = { static const struct v4l2_subdev_core_ops adv7180_core_ops = { .s_std = adv7180_s_std, + .s_power = adv7180_s_power, }; static const struct v4l2_subdev_ops adv7180_ops = { @@ -587,6 +620,7 @@ static int adv7180_probe(struct i2c_client *client, state->irq = client->irq; mutex_init(&state->mutex); state->autodetect = true; + state->powered = true; state->input = 0; sd = &state->sd; v4l2_i2c_subdev_init(sd, client, &adv7180_ops); @@ -640,13 +674,10 @@ static const struct i2c_device_id adv7180_id[] = { static int adv7180_suspend(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); - int ret; + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct adv7180_state *state = to_state(sd); - ret = i2c_smbus_write_byte_data(client, ADV7180_PWR_MAN_REG, - ADV7180_PWR_MAN_OFF); - if (ret < 0) - return ret; - return 0; + return adv7180_set_power(state, client, false); } static int adv7180_resume(struct device *dev) @@ -656,10 +687,11 @@ static int adv7180_resume(struct device *dev) struct adv7180_state *state = to_state(sd); int ret; - ret = i2c_smbus_write_byte_data(client, ADV7180_PWR_MAN_REG, - ADV7180_PWR_MAN_ON); - if (ret < 0) - return ret; + if (state->powered) { + ret = adv7180_set_power(state, client, true); + if (ret) + return ret; + } ret = init_device(client, state); if (ret < 0) return ret; -- cgit v1.1 From d0ce898c39bf070ad59751df36206b5ccd3d1c03 Mon Sep 17 00:00:00 2001 From: Joonyoung Shim Date: Thu, 20 Feb 2014 23:22:12 -0300 Subject: [media] s5p-mfc: Replaced commas with semicolons There is no any reason to use comma here. Signed-off-by: Joonyoung Shim Signed-off-by: Kamil Debski Signed-off-by: Mauro Carvalho Chehab --- drivers/media/platform/s5p-mfc/s5p_mfc.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc.c b/drivers/media/platform/s5p-mfc/s5p_mfc.c index 0c47199..89356ae 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc.c +++ b/drivers/media/platform/s5p-mfc/s5p_mfc.c @@ -1152,9 +1152,9 @@ static int s5p_mfc_probe(struct platform_device *pdev) ret = -ENOMEM; goto err_dec_alloc; } - vfd->fops = &s5p_mfc_fops, + vfd->fops = &s5p_mfc_fops; vfd->ioctl_ops = get_dec_v4l2_ioctl_ops(); - vfd->release = video_device_release, + vfd->release = video_device_release; vfd->lock = &dev->mfc_mutex; vfd->v4l2_dev = &dev->v4l2_dev; vfd->vfl_dir = VFL_DIR_M2M; @@ -1177,9 +1177,9 @@ static int s5p_mfc_probe(struct platform_device *pdev) ret = -ENOMEM; goto err_enc_alloc; } - vfd->fops = &s5p_mfc_fops, + vfd->fops = &s5p_mfc_fops; vfd->ioctl_ops = get_enc_v4l2_ioctl_ops(); - vfd->release = video_device_release, + vfd->release = video_device_release; vfd->lock = &dev->mfc_mutex; vfd->v4l2_dev = &dev->v4l2_dev; vfd->vfl_dir = VFL_DIR_M2M; -- cgit v1.1 From ad7f22b55dfdf09f6d1187080f486da1ca235f01 Mon Sep 17 00:00:00 2001 From: Seung-Woo Kim Date: Thu, 6 Mar 2014 01:55:39 -0300 Subject: [media] s5p-mfc: remove meaningless memory bank assignment This patch removes meaningless assignment of memory bank to itself. Signed-off-by: Seung-Woo Kim Acked-by: Sachin Kamat Signed-off-by: Kamil Debski Signed-off-by: Mauro Carvalho Chehab --- drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c b/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c index 2475a3c..ee05f2d 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c @@ -44,8 +44,6 @@ int s5p_mfc_alloc_firmware(struct s5p_mfc_dev *dev) return -ENOMEM; } - dev->bank1 = dev->bank1; - if (HAS_PORTNUM(dev) && IS_TWOPORT(dev)) { bank2_virt = dma_alloc_coherent(dev->mem_dev_r, 1 << MFC_BASE_ALIGN_ORDER, &bank2_dma_addr, GFP_KERNEL); -- cgit v1.1 From 4340583159b354f0c967b71518699bcc814c8614 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Mon, 10 Mar 2014 10:58:23 -0300 Subject: [media] mem2mem_testdev: use 40ms default transfer time The default of 1 second is a bit painful, switch to a 25 Hz framerate. Signed-off-by: Hans Verkuil Signed-off-by: Kamil Debski Signed-off-by: Mauro Carvalho Chehab --- drivers/media/platform/mem2mem_testdev.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/media/platform/mem2mem_testdev.c b/drivers/media/platform/mem2mem_testdev.c index 4bb5e88..5c6067d 100644 --- a/drivers/media/platform/mem2mem_testdev.c +++ b/drivers/media/platform/mem2mem_testdev.c @@ -60,9 +60,7 @@ MODULE_PARM_DESC(debug, "activates debug info"); #define MEM2MEM_VID_MEM_LIMIT (16 * 1024 * 1024) /* Default transaction time in msec */ -#define MEM2MEM_DEF_TRANSTIME 1000 -/* Default number of buffers per transaction */ -#define MEM2MEM_DEF_TRANSLEN 1 +#define MEM2MEM_DEF_TRANSTIME 40 #define MEM2MEM_COLOR_STEP (0xff >> 4) #define MEM2MEM_NUM_TILES 8 @@ -804,10 +802,10 @@ static const struct v4l2_ctrl_config m2mtest_ctrl_trans_time_msec = { .id = V4L2_CID_TRANS_TIME_MSEC, .name = "Transaction Time (msec)", .type = V4L2_CTRL_TYPE_INTEGER, - .def = 1001, + .def = MEM2MEM_DEF_TRANSTIME, .min = 1, .max = 10001, - .step = 100, + .step = 1, }; static const struct v4l2_ctrl_config m2mtest_ctrl_trans_num_bufs = { -- cgit v1.1 From 4e8ec0a46f48c86b215a5b76f621927aa40a2440 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Mon, 10 Mar 2014 10:58:24 -0300 Subject: [media] mem2mem_testdev: pick default format with try_fmt This resolves an issue raised by v4l2-compliance: if the given format does not exist, then pick a default format. While there is an exception regarding this for TV capture drivers, this m2m driver should do the right thing. Signed-off-by: Hans Verkuil Signed-off-by: Kamil Debski Signed-off-by: Mauro Carvalho Chehab --- drivers/media/platform/mem2mem_testdev.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/mem2mem_testdev.c b/drivers/media/platform/mem2mem_testdev.c index 5c6067d..104d863 100644 --- a/drivers/media/platform/mem2mem_testdev.c +++ b/drivers/media/platform/mem2mem_testdev.c @@ -543,7 +543,11 @@ static int vidioc_try_fmt_vid_cap(struct file *file, void *priv, struct m2mtest_ctx *ctx = file2ctx(file); fmt = find_format(f); - if (!fmt || !(fmt->types & MEM2MEM_CAPTURE)) { + if (!fmt) { + f->fmt.pix.pixelformat = formats[0].fourcc; + fmt = find_format(f); + } + if (!(fmt->types & MEM2MEM_CAPTURE)) { v4l2_err(&ctx->dev->v4l2_dev, "Fourcc format (0x%08x) invalid.\n", f->fmt.pix.pixelformat); @@ -561,7 +565,11 @@ static int vidioc_try_fmt_vid_out(struct file *file, void *priv, struct m2mtest_ctx *ctx = file2ctx(file); fmt = find_format(f); - if (!fmt || !(fmt->types & MEM2MEM_OUTPUT)) { + if (!fmt) { + f->fmt.pix.pixelformat = formats[0].fourcc; + fmt = find_format(f); + } + if (!(fmt->types & MEM2MEM_OUTPUT)) { v4l2_err(&ctx->dev->v4l2_dev, "Fourcc format (0x%08x) invalid.\n", f->fmt.pix.pixelformat); -- cgit v1.1 From f063bb6638c5337929d091c0d3abdbd049f829ba Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Mon, 10 Mar 2014 10:58:25 -0300 Subject: [media] mem2mem_testdev: set priv to 0 v4l2_compliance fix. Signed-off-by: Hans Verkuil Signed-off-by: Kamil Debski Signed-off-by: Mauro Carvalho Chehab --- drivers/media/platform/mem2mem_testdev.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/media/platform/mem2mem_testdev.c b/drivers/media/platform/mem2mem_testdev.c index 104d863..c4b54f8 100644 --- a/drivers/media/platform/mem2mem_testdev.c +++ b/drivers/media/platform/mem2mem_testdev.c @@ -532,6 +532,7 @@ static int vidioc_try_fmt(struct v4l2_format *f, struct m2mtest_fmt *fmt) f->fmt.pix.width &= ~DIM_ALIGN_MASK; f->fmt.pix.bytesperline = (f->fmt.pix.width * fmt->depth) >> 3; f->fmt.pix.sizeimage = f->fmt.pix.height * f->fmt.pix.bytesperline; + f->fmt.pix.priv = 0; return 0; } -- cgit v1.1 From 782f36ca697034b43177b0d7e05d691f6bce120f Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Mon, 10 Mar 2014 10:58:26 -0300 Subject: [media] mem2mem_testdev: add USERPTR support There is no reason why we shouldn't enable this here. Signed-off-by: Hans Verkuil Signed-off-by: Kamil Debski Signed-off-by: Mauro Carvalho Chehab --- drivers/media/platform/mem2mem_testdev.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/mem2mem_testdev.c b/drivers/media/platform/mem2mem_testdev.c index c4b54f8..8e2aed2 100644 --- a/drivers/media/platform/mem2mem_testdev.c +++ b/drivers/media/platform/mem2mem_testdev.c @@ -782,7 +782,7 @@ static int queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *ds int ret; src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT; - src_vq->io_modes = VB2_MMAP | VB2_DMABUF; + src_vq->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF; src_vq->drv_priv = ctx; src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); src_vq->ops = &m2mtest_qops; @@ -795,7 +795,7 @@ static int queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *ds return ret; dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; - dst_vq->io_modes = VB2_MMAP | VB2_DMABUF; + dst_vq->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF; dst_vq->drv_priv = ctx; dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); dst_vq->ops = &m2mtest_qops; -- cgit v1.1 From a773632c1f9096f76d4b5a112d8e5a7183097aa6 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Mon, 10 Mar 2014 10:58:27 -0300 Subject: [media] mem2mem_testdev: return pending buffers in stop_streaming() To keep the vb2 buffer administration in balance stop_streaming() must return any pending buffers to the vb2 framework. Signed-off-by: Hans Verkuil Signed-off-by: Kamil Debski Signed-off-by: Mauro Carvalho Chehab --- drivers/media/platform/mem2mem_testdev.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/media/platform/mem2mem_testdev.c b/drivers/media/platform/mem2mem_testdev.c index 8e2aed2..1ba1a83 100644 --- a/drivers/media/platform/mem2mem_testdev.c +++ b/drivers/media/platform/mem2mem_testdev.c @@ -768,10 +768,31 @@ static void m2mtest_buf_queue(struct vb2_buffer *vb) v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vb); } +static int m2mtest_stop_streaming(struct vb2_queue *q) +{ + struct m2mtest_ctx *ctx = vb2_get_drv_priv(q); + struct vb2_buffer *vb; + unsigned long flags; + + for (;;) { + if (V4L2_TYPE_IS_OUTPUT(q->type)) + vb = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); + else + vb = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); + if (vb == NULL) + return 0; + spin_lock_irqsave(&ctx->dev->irqlock, flags); + v4l2_m2m_buf_done(vb, VB2_BUF_STATE_ERROR); + spin_unlock_irqrestore(&ctx->dev->irqlock, flags); + } + return 0; +} + static struct vb2_ops m2mtest_qops = { .queue_setup = m2mtest_queue_setup, .buf_prepare = m2mtest_buf_prepare, .buf_queue = m2mtest_buf_queue, + .stop_streaming = m2mtest_stop_streaming, .wait_prepare = vb2_ops_wait_prepare, .wait_finish = vb2_ops_wait_finish, }; -- cgit v1.1 From ca5f5fdb298a838958367b6fd769a3d084c67183 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Mon, 10 Mar 2014 10:58:28 -0300 Subject: [media] mem2mem_testdev: fix field, sequence and time copying - Set the sequence counters correctly. - Copy timestamps, timecode, relevant buffer flags and field from the received buffer to the outgoing buffer. Signed-off-by: Hans Verkuil Signed-off-by: Kamil Debski Signed-off-by: Mauro Carvalho Chehab --- drivers/media/platform/mem2mem_testdev.c | 27 ++++++++++++++++++++++++--- 1 file changed, 24 insertions(+), 3 deletions(-) diff --git a/drivers/media/platform/mem2mem_testdev.c b/drivers/media/platform/mem2mem_testdev.c index 1ba1a83..dec8092 100644 --- a/drivers/media/platform/mem2mem_testdev.c +++ b/drivers/media/platform/mem2mem_testdev.c @@ -112,6 +112,7 @@ struct m2mtest_q_data { unsigned int width; unsigned int height; unsigned int sizeimage; + unsigned int sequence; struct m2mtest_fmt *fmt; }; @@ -234,12 +235,21 @@ static int device_process(struct m2mtest_ctx *ctx, bytes_left = bytesperline - tile_w * MEM2MEM_NUM_TILES; w = 0; + out_vb->v4l2_buf.sequence = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE)->sequence++; + in_vb->v4l2_buf.sequence = q_data->sequence++; memcpy(&out_vb->v4l2_buf.timestamp, &in_vb->v4l2_buf.timestamp, sizeof(struct timeval)); - out_vb->v4l2_buf.flags &= ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK; - out_vb->v4l2_buf.flags |= - in_vb->v4l2_buf.flags & V4L2_BUF_FLAG_TSTAMP_SRC_MASK; + if (in_vb->v4l2_buf.flags & V4L2_BUF_FLAG_TIMECODE) + memcpy(&out_vb->v4l2_buf.timecode, &in_vb->v4l2_buf.timecode, + sizeof(struct v4l2_timecode)); + out_vb->v4l2_buf.field = in_vb->v4l2_buf.field; + out_vb->v4l2_buf.flags = in_vb->v4l2_buf.flags & + (V4L2_BUF_FLAG_TIMECODE | + V4L2_BUF_FLAG_KEYFRAME | + V4L2_BUF_FLAG_PFRAME | + V4L2_BUF_FLAG_BFRAME | + V4L2_BUF_FLAG_TSTAMP_SRC_MASK); switch (ctx->mode) { case MEM2MEM_HFLIP | MEM2MEM_VFLIP: @@ -765,9 +775,19 @@ static int m2mtest_buf_prepare(struct vb2_buffer *vb) static void m2mtest_buf_queue(struct vb2_buffer *vb) { struct m2mtest_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue); + v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vb); } +static int m2mtest_start_streaming(struct vb2_queue *q, unsigned count) +{ + struct m2mtest_ctx *ctx = vb2_get_drv_priv(q); + struct m2mtest_q_data *q_data = get_q_data(ctx, q->type); + + q_data->sequence = 0; + return 0; +} + static int m2mtest_stop_streaming(struct vb2_queue *q) { struct m2mtest_ctx *ctx = vb2_get_drv_priv(q); @@ -792,6 +812,7 @@ static struct vb2_ops m2mtest_qops = { .queue_setup = m2mtest_queue_setup, .buf_prepare = m2mtest_buf_prepare, .buf_queue = m2mtest_buf_queue, + .start_streaming = m2mtest_start_streaming, .stop_streaming = m2mtest_stop_streaming, .wait_prepare = vb2_ops_wait_prepare, .wait_finish = vb2_ops_wait_finish, -- cgit v1.1 From 5c3112b5beb1005609bf91749c528d32ad7b47f8 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Mon, 10 Mar 2014 10:58:29 -0300 Subject: [media] mem2mem_testdev: improve field handling try_fmt should just set field to NONE and not return an error if a different field was passed. buf_prepare should check if the field passed in from userspace has a supported field value. At the moment only NONE is supported and ANY is mapped to NONE. Signed-off-by: Hans Verkuil Signed-off-by: Kamil Debski Signed-off-by: Mauro Carvalho Chehab --- drivers/media/platform/mem2mem_testdev.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/drivers/media/platform/mem2mem_testdev.c b/drivers/media/platform/mem2mem_testdev.c index dec8092..4f3096b 100644 --- a/drivers/media/platform/mem2mem_testdev.c +++ b/drivers/media/platform/mem2mem_testdev.c @@ -516,19 +516,8 @@ static int vidioc_g_fmt_vid_cap(struct file *file, void *priv, static int vidioc_try_fmt(struct v4l2_format *f, struct m2mtest_fmt *fmt) { - enum v4l2_field field; - - field = f->fmt.pix.field; - - if (field == V4L2_FIELD_ANY) - field = V4L2_FIELD_NONE; - else if (V4L2_FIELD_NONE != field) - return -EINVAL; - /* V4L2 specification suggests the driver corrects the format struct * if any of the dimensions is unsupported */ - f->fmt.pix.field = field; - if (f->fmt.pix.height < MIN_H) f->fmt.pix.height = MIN_H; else if (f->fmt.pix.height > MAX_H) @@ -542,6 +531,7 @@ static int vidioc_try_fmt(struct v4l2_format *f, struct m2mtest_fmt *fmt) f->fmt.pix.width &= ~DIM_ALIGN_MASK; f->fmt.pix.bytesperline = (f->fmt.pix.width * fmt->depth) >> 3; f->fmt.pix.sizeimage = f->fmt.pix.height * f->fmt.pix.bytesperline; + f->fmt.pix.field = V4L2_FIELD_NONE; f->fmt.pix.priv = 0; return 0; @@ -760,6 +750,15 @@ static int m2mtest_buf_prepare(struct vb2_buffer *vb) dprintk(ctx->dev, "type: %d\n", vb->vb2_queue->type); q_data = get_q_data(ctx, vb->vb2_queue->type); + if (V4L2_TYPE_IS_OUTPUT(vb->vb2_queue->type)) { + if (vb->v4l2_buf.field == V4L2_FIELD_ANY) + vb->v4l2_buf.field = V4L2_FIELD_NONE; + if (vb->v4l2_buf.field != V4L2_FIELD_NONE) { + dprintk(ctx->dev, "%s field isn't supported\n", + __func__); + return -EINVAL; + } + } if (vb2_plane_size(vb, 0) < q_data->sizeimage) { dprintk(ctx->dev, "%s data will not fit into plane (%lu < %lu)\n", -- cgit v1.1 From 90d9c3e1ede2a7d4a0dedfff6e22f46ebd7484c0 Mon Sep 17 00:00:00 2001 From: Gianluca Gennari Date: Tue, 11 Mar 2014 10:41:47 -0300 Subject: [media] drx39xyj: fix 64 bit division on 32 bit arch Fix this linker warning: WARNING: "__divdi3" [media_build/v4l/drx39xyj.ko] undefined! [m.chehab@samsung.com: add include for asm/div64.h] Signed-off-by: Gianluca Gennari Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/drx39xyj/drxj.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index b8c5a85..9482954 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -59,6 +59,7 @@ INCLUDE FILES #include #include #include +#include #include "dvb_frontend.h" #include "drx39xxj.h" @@ -12002,13 +12003,16 @@ static int drx39xxj_read_signal_strength(struct dvb_frontend *fe, static int drx39xxj_read_snr(struct dvb_frontend *fe, u16 *snr) { struct dtv_frontend_properties *p = &fe->dtv_property_cache; + u64 tmp64; if (p->cnr.stat[0].scale == FE_SCALE_NOT_AVAILABLE) { *snr = 0; return 0; } - *snr = p->cnr.stat[0].svalue / 10; + tmp64 = p->cnr.stat[0].svalue; + do_div(tmp64, 10); + *snr = tmp64; return 0; } -- cgit v1.1 From e01c15dbbd8e4737743a29ff325fe54ff8680786 Mon Sep 17 00:00:00 2001 From: Marcus Folkesson Date: Wed, 5 Feb 2014 12:56:13 -0300 Subject: [media] media: i2c: Kconfig: create dependency to MEDIA_CONTROLLER for adv7* These chips makes use of the media_entity in the v4l2_subdev struct and is therefor dependent of the MEDIA_CONTROLLER config. Signed-off-by: Marcus Folkesson Signed-off-by: Mauro Carvalho Chehab --- drivers/media/i2c/Kconfig | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig index c7f2823..194caba 100644 --- a/drivers/media/i2c/Kconfig +++ b/drivers/media/i2c/Kconfig @@ -196,7 +196,7 @@ config VIDEO_ADV7183 config VIDEO_ADV7604 tristate "Analog Devices ADV7604 decoder" - depends on VIDEO_V4L2 && I2C && VIDEO_V4L2_SUBDEV_API + depends on VIDEO_V4L2 && I2C && VIDEO_V4L2_SUBDEV_API && MEDIA_CONTROLLER ---help--- Support for the Analog Devices ADV7604 video decoder. @@ -208,7 +208,7 @@ config VIDEO_ADV7604 config VIDEO_ADV7842 tristate "Analog Devices ADV7842 decoder" - depends on VIDEO_V4L2 && I2C && VIDEO_V4L2_SUBDEV_API + depends on VIDEO_V4L2 && I2C && VIDEO_V4L2_SUBDEV_API && MEDIA_CONTROLLER ---help--- Support for the Analog Devices ADV7842 video decoder. @@ -431,7 +431,7 @@ config VIDEO_ADV7393 config VIDEO_ADV7511 tristate "Analog Devices ADV7511 encoder" - depends on VIDEO_V4L2 && I2C && VIDEO_V4L2_SUBDEV_API + depends on VIDEO_V4L2 && I2C && VIDEO_V4L2_SUBDEV_API && MEDIA_CONTROLLER ---help--- Support for the Analog Devices ADV7511 video encoder. -- cgit v1.1 From 493a9cfdb9f7bd576603d15778419dddd49994a2 Mon Sep 17 00:00:00 2001 From: Pojar George Date: Fri, 7 Feb 2014 14:56:17 -0300 Subject: [media] bttv: Add support for Kworld V-Stream Xpert TV PVR878 New board addition. No other changes. [m.chehab@samsung.com: rebase patch and fix whitespace mangling] Signed-off-by: Pojar George Signed-off-by: Mauro Carvalho Chehab --- Documentation/video4linux/CARDLIST.bttv | 1 + drivers/media/pci/bt8xx/bttv-cards.c | 17 ++++++++++++++++- drivers/media/pci/bt8xx/bttv-input.c | 1 + drivers/media/pci/bt8xx/bttv.h | 1 + 4 files changed, 19 insertions(+), 1 deletion(-) diff --git a/Documentation/video4linux/CARDLIST.bttv b/Documentation/video4linux/CARDLIST.bttv index f144750..2f6e935 100644 --- a/Documentation/video4linux/CARDLIST.bttv +++ b/Documentation/video4linux/CARDLIST.bttv @@ -163,3 +163,4 @@ 162 -> Adlink MPG24 163 -> Bt848 Capture 14MHz 164 -> CyberVision CV06 (SV) +165 -> Kworld V-Stream Xpert TV PVR878 diff --git a/drivers/media/pci/bt8xx/bttv-cards.c b/drivers/media/pci/bt8xx/bttv-cards.c index 6662b49..d06963b 100644 --- a/drivers/media/pci/bt8xx/bttv-cards.c +++ b/drivers/media/pci/bt8xx/bttv-cards.c @@ -2855,7 +2855,22 @@ struct tvcard bttv_tvcards[] = { .tuner_type = TUNER_ABSENT, .tuner_addr = ADDR_UNSET, }, - + [BTTV_BOARD_KWORLD_VSTREAM_XPERT] = { + /* Pojar George */ + .name = "Kworld V-Stream Xpert TV PVR878", + .video_inputs = 3, + /* .audio_inputs= 1, */ + .svhs = 2, + .gpiomask = 0x001c0007, + .muxsel = MUXSEL(2, 3, 1, 1), + .gpiomux = { 0, 1, 2, 2 }, + .gpiomute = 3, + .pll = PLL_28, + .tuner_type = TUNER_TENA_9533_DI, + .tuner_addr = ADDR_UNSET, + .has_remote = 1, + .has_radio = 1, + }, }; static const unsigned int bttv_num_tvcards = ARRAY_SIZE(bttv_tvcards); diff --git a/drivers/media/pci/bt8xx/bttv-input.c b/drivers/media/pci/bt8xx/bttv-input.c index f368213..5930bce 100644 --- a/drivers/media/pci/bt8xx/bttv-input.c +++ b/drivers/media/pci/bt8xx/bttv-input.c @@ -483,6 +483,7 @@ int bttv_input_init(struct bttv *btv) case BTTV_BOARD_ASKEY_CPH03X: case BTTV_BOARD_CONCEPTRONIC_CTVFMI2: case BTTV_BOARD_CONTVFMI: + case BTTV_BOARD_KWORLD_VSTREAM_XPERT: ir_codes = RC_MAP_PIXELVIEW; ir->mask_keycode = 0x001F00; ir->mask_keyup = 0x006000; diff --git a/drivers/media/pci/bt8xx/bttv.h b/drivers/media/pci/bt8xx/bttv.h index df578ef..bb5da34 100644 --- a/drivers/media/pci/bt8xx/bttv.h +++ b/drivers/media/pci/bt8xx/bttv.h @@ -188,6 +188,7 @@ #define BTTV_BOARD_ADLINK_MPG24 0xa2 #define BTTV_BOARD_BT848_CAP_14 0xa3 #define BTTV_BOARD_CYBERVISION_CV06 0xa4 +#define BTTV_BOARD_KWORLD_VSTREAM_XPERT 0xa5 /* more card-specific defines */ #define PT2254_L_CHANNEL 0x10 -- cgit v1.1 From c6a328a06b19082a4d2bad05bd6151e1bd6ab292 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sat, 8 Feb 2014 11:32:15 -0300 Subject: [media] omap_vout: Add DVI display type support Since the introduction of the new OMAP DSS DVI connector driver in commit 348077b154357eec595068a3336ef6beb870e6f3 ("OMAPDSS: Add new DVI Connector driver"), DVI outputs report a new display type of OMAP_DISPLAY_TYPE_DVI instead of OMAP_DISPLAY_TYPE_DPI. Handle the new type in the IRQ handler. Signed-off-by: Laurent Pinchart Acked-by: Tomi Valkeinen Signed-off-by: Mauro Carvalho Chehab --- drivers/media/platform/omap/omap_vout.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/media/platform/omap/omap_vout.c b/drivers/media/platform/omap/omap_vout.c index dfd0a21..9a726ea 100644 --- a/drivers/media/platform/omap/omap_vout.c +++ b/drivers/media/platform/omap/omap_vout.c @@ -601,6 +601,7 @@ static void omap_vout_isr(void *arg, unsigned int irqstatus) switch (cur_display->type) { case OMAP_DISPLAY_TYPE_DSI: case OMAP_DISPLAY_TYPE_DPI: + case OMAP_DISPLAY_TYPE_DVI: if (mgr_id == OMAP_DSS_CHANNEL_LCD) irq = DISPC_IRQ_VSYNC; else if (mgr_id == OMAP_DSS_CHANNEL_LCD2) -- cgit v1.1 From f61e2268a06c3ea7354a1f4b3d878bedb8b776b1 Mon Sep 17 00:00:00 2001 From: Satoshi Nagahama Date: Mon, 10 Feb 2014 06:45:29 -0300 Subject: [media] Siano: smsusb - Add a device id for PX-S1UD Add a device id to support for PX-S1UD (PLEX ISDB-T usb dongle) which has sms2270. Signed-off-by: Satoshi Nagahama Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/siano/smsusb.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/media/usb/siano/smsusb.c b/drivers/media/usb/siano/smsusb.c index 05bd91a..1836a41 100644 --- a/drivers/media/usb/siano/smsusb.c +++ b/drivers/media/usb/siano/smsusb.c @@ -653,6 +653,8 @@ static const struct usb_device_id smsusb_id_table[] = { .driver_info = SMS1XXX_BOARD_ZTE_DVB_DATA_CARD }, { USB_DEVICE(0x19D2, 0x0078), .driver_info = SMS1XXX_BOARD_ONDA_MDTV_DATA_CARD }, + { USB_DEVICE(0x3275, 0x0080), + .driver_info = SMS1XXX_BOARD_SIANO_RIO }, { } /* Terminating entry */ }; -- cgit v1.1 From 7b802ce7e8c67510389fdbbe29edd87a75df3a93 Mon Sep 17 00:00:00 2001 From: James Hogan Date: Mon, 10 Feb 2014 18:31:56 -0300 Subject: [media] rc-main: store_filter: pass errors to userland MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Propagate errors returned by drivers from the s_filter callback back to userland when updating scancode filters. This allows userland to see when the filter couldn't be updated, usually because it's not a valid filter for the hardware. Previously the filter was being updated conditionally on success of s_filter, but the write always reported success back to userland. Reported-by: Antti Seppälä Signed-off-by: James Hogan Signed-off-by: Mauro Carvalho Chehab --- drivers/media/rc/rc-main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/rc/rc-main.c b/drivers/media/rc/rc-main.c index 2ec60f8..6448128 100644 --- a/drivers/media/rc/rc-main.c +++ b/drivers/media/rc/rc-main.c @@ -1090,7 +1090,7 @@ static ssize_t store_filter(struct device *device, unlock: mutex_unlock(&dev->lock); - return count; + return (ret < 0) ? ret : count; } static void rc_dev_release(struct device *device) -- cgit v1.1 From 7a1dd50b89d4569baea71a80ad1a9def2353ad7d Mon Sep 17 00:00:00 2001 From: Joonyoung Shim Date: Mon, 10 Feb 2014 22:54:34 -0300 Subject: [media] au0828: fix i2c clock speed for DViCO FusionHDTV7 DViCO FusionHDTV7 device that use au0828 can fail to communicate with xc5000 using i2c interface because of high i2c clock speed - i2c clock stretching bug. It causes to fail xc5000 firmware loading normally at the current driver. Already this problem fixed as changing to low i2c clock speed at HVR-950q device, also DViCO FusionHDTV7 device can solve it as using low i2c clock speed - 20KHz. Signed-off-by: Joonyoung Shim Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/au0828/au0828-cards.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/usb/au0828/au0828-cards.c b/drivers/media/usb/au0828/au0828-cards.c index 00291ea..7fdadf9 100644 --- a/drivers/media/usb/au0828/au0828-cards.c +++ b/drivers/media/usb/au0828/au0828-cards.c @@ -108,7 +108,7 @@ struct au0828_board au0828_boards[] = { .name = "DViCO FusionHDTV USB", .tuner_type = UNSET, .tuner_addr = ADDR_UNSET, - .i2c_clk_divider = AU0828_I2C_CLK_250KHZ, + .i2c_clk_divider = AU0828_I2C_CLK_20KHZ, }, [AU0828_BOARD_HAUPPAUGE_WOODBURY] = { .name = "Hauppauge Woodbury", -- cgit v1.1 From c3c2077d9579472b07581ecdaf6cc5a60b1700bc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Antti=20Sepp=C3=A4l=C3=A4?= Date: Sun, 16 Feb 2014 07:16:02 -0300 Subject: [media] nuvoton-cir: Activate PNP device when probing MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On certain motherboards (mainly Intel NUC series) bios keeps the Nuvoton CIR device disabled at boot. This patch adds a call to kernel PNP layer to activate the device if it is not already activated. This will improve the chances of the PNP probe actually succeeding on Intel NUC platforms. Signed-off-by: Antti Seppälä Cc: Jarod Wilson Signed-off-by: Mauro Carvalho Chehab --- drivers/media/rc/nuvoton-cir.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/media/rc/nuvoton-cir.c b/drivers/media/rc/nuvoton-cir.c index b41e52e..b81325d 100644 --- a/drivers/media/rc/nuvoton-cir.c +++ b/drivers/media/rc/nuvoton-cir.c @@ -985,6 +985,12 @@ static int nvt_probe(struct pnp_dev *pdev, const struct pnp_device_id *dev_id) goto exit_free_dev_rdev; ret = -ENODEV; + /* activate pnp device */ + if (pnp_activate_dev(pdev) < 0) { + dev_err(&pdev->dev, "Could not activate PNP device!\n"); + goto exit_free_dev_rdev; + } + /* validate pnp resources */ if (!pnp_port_valid(pdev, 0) || pnp_port_len(pdev, 0) < CIR_IOREG_LENGTH) { -- cgit v1.1 From b8c7d915087c97a21fa415fa0e860e59739da202 Mon Sep 17 00:00:00 2001 From: James Hogan Date: Fri, 28 Feb 2014 20:17:02 -0300 Subject: [media] rc-main: add generic scancode filtering MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add generic scancode filtering of RC input events, and fall back to permitting any RC_FILTER_NORMAL scancode filter to be set if no s_filter callback exists. This allows raw IR decoder events to be filtered, and potentially allows hardware decoders to set looser filters and rely on generic code to filter out the corner cases. Signed-off-by: James Hogan Reviewed-by: Antti Seppälä Signed-off-by: Mauro Carvalho Chehab --- drivers/media/rc/rc-main.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/drivers/media/rc/rc-main.c b/drivers/media/rc/rc-main.c index 6448128..0a4f680 100644 --- a/drivers/media/rc/rc-main.c +++ b/drivers/media/rc/rc-main.c @@ -633,6 +633,7 @@ EXPORT_SYMBOL_GPL(rc_repeat); static void ir_do_keydown(struct rc_dev *dev, int scancode, u32 keycode, u8 toggle) { + struct rc_scancode_filter *filter; bool new_event = !dev->keypressed || dev->last_scancode != scancode || dev->last_toggle != toggle; @@ -640,6 +641,11 @@ static void ir_do_keydown(struct rc_dev *dev, int scancode, if (new_event && dev->keypressed) ir_do_keyup(dev, false); + /* Generic scancode filtering */ + filter = &dev->scancode_filters[RC_FILTER_NORMAL]; + if (filter->mask && ((scancode ^ filter->data) & filter->mask)) + return; + input_event(dev->input_dev, EV_MSC, MSC_SCAN, scancode); if (new_event && keycode != KEY_RESERVED) { @@ -1019,9 +1025,7 @@ static ssize_t show_filter(struct device *device, return -EINVAL; mutex_lock(&dev->lock); - if (!dev->s_filter) - val = 0; - else if (fattr->mask) + if (fattr->mask) val = dev->scancode_filters[fattr->type].mask; else val = dev->scancode_filters[fattr->type].data; @@ -1069,7 +1073,7 @@ static ssize_t store_filter(struct device *device, return ret; /* Scancode filter not supported (but still accept 0) */ - if (!dev->s_filter) + if (!dev->s_filter && fattr->type != RC_FILTER_NORMAL) return val ? -EINVAL : count; mutex_lock(&dev->lock); @@ -1081,9 +1085,11 @@ static ssize_t store_filter(struct device *device, local_filter.mask = val; else local_filter.data = val; - ret = dev->s_filter(dev, fattr->type, &local_filter); - if (ret < 0) - goto unlock; + if (dev->s_filter) { + ret = dev->s_filter(dev, fattr->type, &local_filter); + if (ret < 0) + goto unlock; + } /* Success, commit the new filter */ *filter = local_filter; -- cgit v1.1 From 1a1934fab0c920f0d3bceeb60c9fe2dae8a56be9 Mon Sep 17 00:00:00 2001 From: James Hogan Date: Fri, 28 Feb 2014 20:17:03 -0300 Subject: [media] rc: abstract access to allowed/enabled protocols MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The allowed and enabled protocol masks need to be expanded to be per filter type in order to support wakeup filter protocol selection. To ease that process abstract access to the rc_dev::allowed_protos and rc_dev::enabled_protocols members with inline functions. Signed-off-by: James Hogan Reviewed-by: Antti Seppälä Signed-off-by: Mauro Carvalho Chehab --- drivers/hid/hid-picolcd_cir.c | 2 +- drivers/media/common/siano/smsir.c | 2 +- drivers/media/i2c/ir-kbd-i2c.c | 4 ++-- drivers/media/pci/cx23885/cx23885-input.c | 2 +- drivers/media/pci/cx88/cx88-input.c | 2 +- drivers/media/rc/ati_remote.c | 2 +- drivers/media/rc/ene_ir.c | 2 +- drivers/media/rc/fintek-cir.c | 2 +- drivers/media/rc/gpio-ir-recv.c | 4 ++-- drivers/media/rc/iguanair.c | 2 +- drivers/media/rc/imon.c | 7 ++++--- drivers/media/rc/ir-jvc-decoder.c | 2 +- drivers/media/rc/ir-lirc-codec.c | 2 +- drivers/media/rc/ir-mce_kbd-decoder.c | 2 +- drivers/media/rc/ir-nec-decoder.c | 2 +- drivers/media/rc/ir-raw.c | 2 +- drivers/media/rc/ir-rc5-decoder.c | 6 +++--- drivers/media/rc/ir-rc5-sz-decoder.c | 2 +- drivers/media/rc/ir-rc6-decoder.c | 6 +++--- drivers/media/rc/ir-sanyo-decoder.c | 2 +- drivers/media/rc/ir-sharp-decoder.c | 2 +- drivers/media/rc/ir-sony-decoder.c | 10 +++++----- drivers/media/rc/ite-cir.c | 2 +- drivers/media/rc/mceusb.c | 2 +- drivers/media/rc/nuvoton-cir.c | 2 +- drivers/media/rc/rc-loopback.c | 2 +- drivers/media/rc/redrat3.c | 2 +- drivers/media/rc/st_rc.c | 2 +- drivers/media/rc/streamzap.c | 2 +- drivers/media/rc/ttusbir.c | 2 +- drivers/media/rc/winbond-cir.c | 2 +- drivers/media/usb/dvb-usb-v2/dvb_usb_core.c | 2 +- drivers/media/usb/dvb-usb/dvb-usb-remote.c | 2 +- drivers/media/usb/em28xx/em28xx-input.c | 8 ++++---- drivers/media/usb/tm6000/tm6000-input.c | 2 +- include/media/rc-core.h | 22 ++++++++++++++++++++++ 36 files changed, 73 insertions(+), 50 deletions(-) diff --git a/drivers/hid/hid-picolcd_cir.c b/drivers/hid/hid-picolcd_cir.c index 59d5eb1..cf1a9f1 100644 --- a/drivers/hid/hid-picolcd_cir.c +++ b/drivers/hid/hid-picolcd_cir.c @@ -114,7 +114,7 @@ int picolcd_init_cir(struct picolcd_data *data, struct hid_report *report) rdev->priv = data; rdev->driver_type = RC_DRIVER_IR_RAW; - rdev->allowed_protos = RC_BIT_ALL; + rc_set_allowed_protocols(rdev, RC_BIT_ALL); rdev->open = picolcd_cir_open; rdev->close = picolcd_cir_close; rdev->input_name = data->hdev->name; diff --git a/drivers/media/common/siano/smsir.c b/drivers/media/common/siano/smsir.c index b8c5cad..6d7c0c8 100644 --- a/drivers/media/common/siano/smsir.c +++ b/drivers/media/common/siano/smsir.c @@ -88,7 +88,7 @@ int sms_ir_init(struct smscore_device_t *coredev) dev->priv = coredev; dev->driver_type = RC_DRIVER_IR_RAW; - dev->allowed_protos = RC_BIT_ALL; + rc_set_allowed_protocols(dev, RC_BIT_ALL); dev->map_name = sms_get_board(board_id)->rc_codes; dev->driver_name = MODULE_NAME; diff --git a/drivers/media/i2c/ir-kbd-i2c.c b/drivers/media/i2c/ir-kbd-i2c.c index 99ee456..c8fe135 100644 --- a/drivers/media/i2c/ir-kbd-i2c.c +++ b/drivers/media/i2c/ir-kbd-i2c.c @@ -431,8 +431,8 @@ static int ir_probe(struct i2c_client *client, const struct i2c_device_id *id) * Initialize the other fields of rc_dev */ rc->map_name = ir->ir_codes; - rc->allowed_protos = rc_type; - rc->enabled_protocols = rc_type; + rc_set_allowed_protocols(rc, rc_type); + rc_set_enabled_protocols(rc, rc_type); if (!rc->driver_name) rc->driver_name = MODULE_NAME; diff --git a/drivers/media/pci/cx23885/cx23885-input.c b/drivers/media/pci/cx23885/cx23885-input.c index 8a49e7c..097d0a0 100644 --- a/drivers/media/pci/cx23885/cx23885-input.c +++ b/drivers/media/pci/cx23885/cx23885-input.c @@ -346,7 +346,7 @@ int cx23885_input_init(struct cx23885_dev *dev) } rc->dev.parent = &dev->pci->dev; rc->driver_type = driver_type; - rc->allowed_protos = allowed_protos; + rc_set_allowed_protocols(rc, allowed_protos); rc->priv = kernel_ir; rc->open = cx23885_input_ir_open; rc->close = cx23885_input_ir_close; diff --git a/drivers/media/pci/cx88/cx88-input.c b/drivers/media/pci/cx88/cx88-input.c index f29e18c..f991696 100644 --- a/drivers/media/pci/cx88/cx88-input.c +++ b/drivers/media/pci/cx88/cx88-input.c @@ -469,7 +469,7 @@ int cx88_ir_init(struct cx88_core *core, struct pci_dev *pci) dev->timeout = 10 * 1000 * 1000; /* 10 ms */ } else { dev->driver_type = RC_DRIVER_SCANCODE; - dev->allowed_protos = rc_type; + rc_set_allowed_protocols(dev, rc_type); } ir->core = core; diff --git a/drivers/media/rc/ati_remote.c b/drivers/media/rc/ati_remote.c index 4d6a63f..2df7c55 100644 --- a/drivers/media/rc/ati_remote.c +++ b/drivers/media/rc/ati_remote.c @@ -784,7 +784,7 @@ static void ati_remote_rc_init(struct ati_remote *ati_remote) rdev->priv = ati_remote; rdev->driver_type = RC_DRIVER_SCANCODE; - rdev->allowed_protos = RC_BIT_OTHER; + rc_set_allowed_protocols(rdev, RC_BIT_OTHER); rdev->driver_name = "ati_remote"; rdev->open = ati_remote_rc_open; diff --git a/drivers/media/rc/ene_ir.c b/drivers/media/rc/ene_ir.c index c1444f8..fc9d23f 100644 --- a/drivers/media/rc/ene_ir.c +++ b/drivers/media/rc/ene_ir.c @@ -1059,7 +1059,7 @@ static int ene_probe(struct pnp_dev *pnp_dev, const struct pnp_device_id *id) learning_mode_force = false; rdev->driver_type = RC_DRIVER_IR_RAW; - rdev->allowed_protos = RC_BIT_ALL; + rc_set_allowed_protocols(rdev, RC_BIT_ALL); rdev->priv = dev; rdev->open = ene_open; rdev->close = ene_close; diff --git a/drivers/media/rc/fintek-cir.c b/drivers/media/rc/fintek-cir.c index d6fa441..46b66e5 100644 --- a/drivers/media/rc/fintek-cir.c +++ b/drivers/media/rc/fintek-cir.c @@ -541,7 +541,7 @@ static int fintek_probe(struct pnp_dev *pdev, const struct pnp_device_id *dev_id /* Set up the rc device */ rdev->priv = fintek; rdev->driver_type = RC_DRIVER_IR_RAW; - rdev->allowed_protos = RC_BIT_ALL; + rc_set_allowed_protocols(rdev, RC_BIT_ALL); rdev->open = fintek_open; rdev->close = fintek_close; rdev->input_name = FINTEK_DESCRIPTION; diff --git a/drivers/media/rc/gpio-ir-recv.c b/drivers/media/rc/gpio-ir-recv.c index 80c611c..29b5f89 100644 --- a/drivers/media/rc/gpio-ir-recv.c +++ b/drivers/media/rc/gpio-ir-recv.c @@ -145,9 +145,9 @@ static int gpio_ir_recv_probe(struct platform_device *pdev) rcdev->dev.parent = &pdev->dev; rcdev->driver_name = GPIO_IR_DRIVER_NAME; if (pdata->allowed_protos) - rcdev->allowed_protos = pdata->allowed_protos; + rc_set_allowed_protocols(rcdev, pdata->allowed_protos); else - rcdev->allowed_protos = RC_BIT_ALL; + rc_set_allowed_protocols(rcdev, RC_BIT_ALL); rcdev->map_name = pdata->map_name ?: RC_MAP_EMPTY; gpio_dev->rcdev = rcdev; diff --git a/drivers/media/rc/iguanair.c b/drivers/media/rc/iguanair.c index a83519a..627ddfd 100644 --- a/drivers/media/rc/iguanair.c +++ b/drivers/media/rc/iguanair.c @@ -495,7 +495,7 @@ static int iguanair_probe(struct usb_interface *intf, usb_to_input_id(ir->udev, &rc->input_id); rc->dev.parent = &intf->dev; rc->driver_type = RC_DRIVER_IR_RAW; - rc->allowed_protos = RC_BIT_ALL; + rc_set_allowed_protocols(rc, RC_BIT_ALL); rc->priv = ir; rc->open = iguanair_open; rc->close = iguanair_close; diff --git a/drivers/media/rc/imon.c b/drivers/media/rc/imon.c index 822b9f4..6f24e77 100644 --- a/drivers/media/rc/imon.c +++ b/drivers/media/rc/imon.c @@ -1017,7 +1017,7 @@ static int imon_ir_change_protocol(struct rc_dev *rc, u64 *rc_type) unsigned char ir_proto_packet[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x86 }; - if (*rc_type && !(*rc_type & rc->allowed_protos)) + if (*rc_type && !rc_protocols_allowed(rc, *rc_type)) dev_warn(dev, "Looks like you're trying to use an IR protocol " "this device does not support\n"); @@ -1867,7 +1867,8 @@ static struct rc_dev *imon_init_rdev(struct imon_context *ictx) rdev->priv = ictx; rdev->driver_type = RC_DRIVER_SCANCODE; - rdev->allowed_protos = RC_BIT_OTHER | RC_BIT_RC6_MCE; /* iMON PAD or MCE */ + /* iMON PAD or MCE */ + rc_set_allowed_protocols(rdev, RC_BIT_OTHER | RC_BIT_RC6_MCE); rdev->change_protocol = imon_ir_change_protocol; rdev->driver_name = MOD_NAME; @@ -1880,7 +1881,7 @@ static struct rc_dev *imon_init_rdev(struct imon_context *ictx) if (ictx->product == 0xffdc) { imon_get_ffdc_type(ictx); - rdev->allowed_protos = ictx->rc_type; + rc_set_allowed_protocols(rdev, ictx->rc_type); } imon_set_display_type(ictx); diff --git a/drivers/media/rc/ir-jvc-decoder.c b/drivers/media/rc/ir-jvc-decoder.c index 3948138..4ea62a1 100644 --- a/drivers/media/rc/ir-jvc-decoder.c +++ b/drivers/media/rc/ir-jvc-decoder.c @@ -47,7 +47,7 @@ static int ir_jvc_decode(struct rc_dev *dev, struct ir_raw_event ev) { struct jvc_dec *data = &dev->raw->jvc; - if (!(dev->enabled_protocols & RC_BIT_JVC)) + if (!rc_protocols_enabled(dev, RC_BIT_JVC)) return 0; if (!is_timing_event(ev)) { diff --git a/drivers/media/rc/ir-lirc-codec.c b/drivers/media/rc/ir-lirc-codec.c index ed2c8a1..d731da6 100644 --- a/drivers/media/rc/ir-lirc-codec.c +++ b/drivers/media/rc/ir-lirc-codec.c @@ -35,7 +35,7 @@ static int ir_lirc_decode(struct rc_dev *dev, struct ir_raw_event ev) struct lirc_codec *lirc = &dev->raw->lirc; int sample; - if (!(dev->enabled_protocols & RC_BIT_LIRC)) + if (!rc_protocols_enabled(dev, RC_BIT_LIRC)) return 0; if (!dev->raw->lirc.drv || !dev->raw->lirc.drv->rbuf) diff --git a/drivers/media/rc/ir-mce_kbd-decoder.c b/drivers/media/rc/ir-mce_kbd-decoder.c index 9f3c9b5..0c55f79 100644 --- a/drivers/media/rc/ir-mce_kbd-decoder.c +++ b/drivers/media/rc/ir-mce_kbd-decoder.c @@ -216,7 +216,7 @@ static int ir_mce_kbd_decode(struct rc_dev *dev, struct ir_raw_event ev) u32 scancode; unsigned long delay; - if (!(dev->enabled_protocols & RC_BIT_MCE_KBD)) + if (!rc_protocols_enabled(dev, RC_BIT_MCE_KBD)) return 0; if (!is_timing_event(ev)) { diff --git a/drivers/media/rc/ir-nec-decoder.c b/drivers/media/rc/ir-nec-decoder.c index e687a42..9de1791 100644 --- a/drivers/media/rc/ir-nec-decoder.c +++ b/drivers/media/rc/ir-nec-decoder.c @@ -52,7 +52,7 @@ static int ir_nec_decode(struct rc_dev *dev, struct ir_raw_event ev) u8 address, not_address, command, not_command; bool send_32bits = false; - if (!(dev->enabled_protocols & RC_BIT_NEC)) + if (!rc_protocols_enabled(dev, RC_BIT_NEC)) return 0; if (!is_timing_event(ev)) { diff --git a/drivers/media/rc/ir-raw.c b/drivers/media/rc/ir-raw.c index f0656fa..763c9d1 100644 --- a/drivers/media/rc/ir-raw.c +++ b/drivers/media/rc/ir-raw.c @@ -256,7 +256,7 @@ int ir_raw_event_register(struct rc_dev *dev) return -ENOMEM; dev->raw->dev = dev; - dev->enabled_protocols = ~0; + rc_set_enabled_protocols(dev, ~0); rc = kfifo_alloc(&dev->raw->kfifo, sizeof(struct ir_raw_event) * MAX_IR_EVENT_SIZE, GFP_KERNEL); diff --git a/drivers/media/rc/ir-rc5-decoder.c b/drivers/media/rc/ir-rc5-decoder.c index 1085e17..4295d9b 100644 --- a/drivers/media/rc/ir-rc5-decoder.c +++ b/drivers/media/rc/ir-rc5-decoder.c @@ -52,7 +52,7 @@ static int ir_rc5_decode(struct rc_dev *dev, struct ir_raw_event ev) u8 toggle; u32 scancode; - if (!(dev->enabled_protocols & (RC_BIT_RC5 | RC_BIT_RC5X))) + if (!rc_protocols_enabled(dev, RC_BIT_RC5 | RC_BIT_RC5X)) return 0; if (!is_timing_event(ev)) { @@ -128,7 +128,7 @@ again: if (data->wanted_bits == RC5X_NBITS) { /* RC5X */ u8 xdata, command, system; - if (!(dev->enabled_protocols & RC_BIT_RC5X)) { + if (!rc_protocols_enabled(dev, RC_BIT_RC5X)) { data->state = STATE_INACTIVE; return 0; } @@ -145,7 +145,7 @@ again: } else { /* RC5 */ u8 command, system; - if (!(dev->enabled_protocols & RC_BIT_RC5)) { + if (!rc_protocols_enabled(dev, RC_BIT_RC5)) { data->state = STATE_INACTIVE; return 0; } diff --git a/drivers/media/rc/ir-rc5-sz-decoder.c b/drivers/media/rc/ir-rc5-sz-decoder.c index 984e5b9..dc18b74 100644 --- a/drivers/media/rc/ir-rc5-sz-decoder.c +++ b/drivers/media/rc/ir-rc5-sz-decoder.c @@ -48,7 +48,7 @@ static int ir_rc5_sz_decode(struct rc_dev *dev, struct ir_raw_event ev) u8 toggle, command, system; u32 scancode; - if (!(dev->enabled_protocols & RC_BIT_RC5_SZ)) + if (!rc_protocols_enabled(dev, RC_BIT_RC5_SZ)) return 0; if (!is_timing_event(ev)) { diff --git a/drivers/media/rc/ir-rc6-decoder.c b/drivers/media/rc/ir-rc6-decoder.c index 7cba7d3..cfbd64e 100644 --- a/drivers/media/rc/ir-rc6-decoder.c +++ b/drivers/media/rc/ir-rc6-decoder.c @@ -89,9 +89,9 @@ static int ir_rc6_decode(struct rc_dev *dev, struct ir_raw_event ev) u32 scancode; u8 toggle; - if (!(dev->enabled_protocols & - (RC_BIT_RC6_0 | RC_BIT_RC6_6A_20 | RC_BIT_RC6_6A_24 | - RC_BIT_RC6_6A_32 | RC_BIT_RC6_MCE))) + if (!rc_protocols_enabled(dev, RC_BIT_RC6_0 | RC_BIT_RC6_6A_20 | + RC_BIT_RC6_6A_24 | RC_BIT_RC6_6A_32 | + RC_BIT_RC6_MCE)) return 0; if (!is_timing_event(ev)) { diff --git a/drivers/media/rc/ir-sanyo-decoder.c b/drivers/media/rc/ir-sanyo-decoder.c index e1351ed..eb715f0 100644 --- a/drivers/media/rc/ir-sanyo-decoder.c +++ b/drivers/media/rc/ir-sanyo-decoder.c @@ -58,7 +58,7 @@ static int ir_sanyo_decode(struct rc_dev *dev, struct ir_raw_event ev) u32 scancode; u8 address, command, not_command; - if (!(dev->enabled_protocols & RC_BIT_SANYO)) + if (!rc_protocols_enabled(dev, RC_BIT_SANYO)) return 0; if (!is_timing_event(ev)) { diff --git a/drivers/media/rc/ir-sharp-decoder.c b/drivers/media/rc/ir-sharp-decoder.c index 4895bc7..66d2039 100644 --- a/drivers/media/rc/ir-sharp-decoder.c +++ b/drivers/media/rc/ir-sharp-decoder.c @@ -48,7 +48,7 @@ static int ir_sharp_decode(struct rc_dev *dev, struct ir_raw_event ev) struct sharp_dec *data = &dev->raw->sharp; u32 msg, echo, address, command, scancode; - if (!(dev->enabled_protocols & RC_BIT_SHARP)) + if (!rc_protocols_enabled(dev, RC_BIT_SHARP)) return 0; if (!is_timing_event(ev)) { diff --git a/drivers/media/rc/ir-sony-decoder.c b/drivers/media/rc/ir-sony-decoder.c index 29ab9c2..599c19a 100644 --- a/drivers/media/rc/ir-sony-decoder.c +++ b/drivers/media/rc/ir-sony-decoder.c @@ -45,8 +45,8 @@ static int ir_sony_decode(struct rc_dev *dev, struct ir_raw_event ev) u32 scancode; u8 device, subdevice, function; - if (!(dev->enabled_protocols & - (RC_BIT_SONY12 | RC_BIT_SONY15 | RC_BIT_SONY20))) + if (!rc_protocols_enabled(dev, RC_BIT_SONY12 | RC_BIT_SONY15 | + RC_BIT_SONY20)) return 0; if (!is_timing_event(ev)) { @@ -124,7 +124,7 @@ static int ir_sony_decode(struct rc_dev *dev, struct ir_raw_event ev) switch (data->count) { case 12: - if (!(dev->enabled_protocols & RC_BIT_SONY12)) { + if (!rc_protocols_enabled(dev, RC_BIT_SONY12)) { data->state = STATE_INACTIVE; return 0; } @@ -133,7 +133,7 @@ static int ir_sony_decode(struct rc_dev *dev, struct ir_raw_event ev) function = bitrev8((data->bits >> 4) & 0xFE); break; case 15: - if (!(dev->enabled_protocols & RC_BIT_SONY15)) { + if (!rc_protocols_enabled(dev, RC_BIT_SONY15)) { data->state = STATE_INACTIVE; return 0; } @@ -142,7 +142,7 @@ static int ir_sony_decode(struct rc_dev *dev, struct ir_raw_event ev) function = bitrev8((data->bits >> 7) & 0xFE); break; case 20: - if (!(dev->enabled_protocols & RC_BIT_SONY20)) { + if (!rc_protocols_enabled(dev, RC_BIT_SONY20)) { data->state = STATE_INACTIVE; return 0; } diff --git a/drivers/media/rc/ite-cir.c b/drivers/media/rc/ite-cir.c index 63b4225..ab24cc6 100644 --- a/drivers/media/rc/ite-cir.c +++ b/drivers/media/rc/ite-cir.c @@ -1563,7 +1563,7 @@ static int ite_probe(struct pnp_dev *pdev, const struct pnp_device_id /* set up ir-core props */ rdev->priv = itdev; rdev->driver_type = RC_DRIVER_IR_RAW; - rdev->allowed_protos = RC_BIT_ALL; + rc_set_allowed_protocols(rdev, RC_BIT_ALL); rdev->open = ite_open; rdev->close = ite_close; rdev->s_idle = ite_s_idle; diff --git a/drivers/media/rc/mceusb.c b/drivers/media/rc/mceusb.c index c01b4c1..5d8f3d4 100644 --- a/drivers/media/rc/mceusb.c +++ b/drivers/media/rc/mceusb.c @@ -1211,7 +1211,7 @@ static struct rc_dev *mceusb_init_rc_dev(struct mceusb_dev *ir) rc->dev.parent = dev; rc->priv = ir; rc->driver_type = RC_DRIVER_IR_RAW; - rc->allowed_protos = RC_BIT_ALL; + rc_set_allowed_protocols(rc, RC_BIT_ALL); rc->timeout = MS_TO_NS(100); if (!ir->flags.no_tx) { rc->s_tx_mask = mceusb_set_tx_mask; diff --git a/drivers/media/rc/nuvoton-cir.c b/drivers/media/rc/nuvoton-cir.c index b81325d..d244e1a 100644 --- a/drivers/media/rc/nuvoton-cir.c +++ b/drivers/media/rc/nuvoton-cir.c @@ -1044,7 +1044,7 @@ static int nvt_probe(struct pnp_dev *pdev, const struct pnp_device_id *dev_id) /* Set up the rc device */ rdev->priv = nvt; rdev->driver_type = RC_DRIVER_IR_RAW; - rdev->allowed_protos = RC_BIT_ALL; + rc_set_allowed_protocols(rdev, RC_BIT_ALL); rdev->open = nvt_open; rdev->close = nvt_close; rdev->tx_ir = nvt_tx_ir; diff --git a/drivers/media/rc/rc-loopback.c b/drivers/media/rc/rc-loopback.c index 53d0282..0a88e0c 100644 --- a/drivers/media/rc/rc-loopback.c +++ b/drivers/media/rc/rc-loopback.c @@ -195,7 +195,7 @@ static int __init loop_init(void) rc->map_name = RC_MAP_EMPTY; rc->priv = &loopdev; rc->driver_type = RC_DRIVER_IR_RAW; - rc->allowed_protos = RC_BIT_ALL; + rc_set_allowed_protocols(rc, RC_BIT_ALL); rc->timeout = 100 * 1000 * 1000; /* 100 ms */ rc->min_timeout = 1; rc->max_timeout = UINT_MAX; diff --git a/drivers/media/rc/redrat3.c b/drivers/media/rc/redrat3.c index a5d4f88..47cd373 100644 --- a/drivers/media/rc/redrat3.c +++ b/drivers/media/rc/redrat3.c @@ -922,7 +922,7 @@ static struct rc_dev *redrat3_init_rc_dev(struct redrat3_dev *rr3) rc->dev.parent = dev; rc->priv = rr3; rc->driver_type = RC_DRIVER_IR_RAW; - rc->allowed_protos = RC_BIT_ALL; + rc_set_allowed_protocols(rc, RC_BIT_ALL); rc->timeout = US_TO_NS(2750); rc->tx_ir = redrat3_transmit_ir; rc->s_tx_carrier = redrat3_set_tx_carrier; diff --git a/drivers/media/rc/st_rc.c b/drivers/media/rc/st_rc.c index 8f0cddb..22e4c1f 100644 --- a/drivers/media/rc/st_rc.c +++ b/drivers/media/rc/st_rc.c @@ -287,7 +287,7 @@ static int st_rc_probe(struct platform_device *pdev) st_rc_hardware_init(rc_dev); rdev->driver_type = RC_DRIVER_IR_RAW; - rdev->allowed_protos = RC_BIT_ALL; + rc_set_allowed_protocols(rdev, RC_BIT_ALL); /* rx sampling rate is 10Mhz */ rdev->rx_resolution = 100; rdev->timeout = US_TO_NS(MAX_SYMB_TIME); diff --git a/drivers/media/rc/streamzap.c b/drivers/media/rc/streamzap.c index d7b11e6..f4e0bc3 100644 --- a/drivers/media/rc/streamzap.c +++ b/drivers/media/rc/streamzap.c @@ -322,7 +322,7 @@ static struct rc_dev *streamzap_init_rc_dev(struct streamzap_ir *sz) rdev->dev.parent = dev; rdev->priv = sz; rdev->driver_type = RC_DRIVER_IR_RAW; - rdev->allowed_protos = RC_BIT_ALL; + rc_set_allowed_protocols(rdev, RC_BIT_ALL); rdev->driver_name = DRIVER_NAME; rdev->map_name = RC_MAP_STREAMZAP; diff --git a/drivers/media/rc/ttusbir.c b/drivers/media/rc/ttusbir.c index d8de205..c5be38e 100644 --- a/drivers/media/rc/ttusbir.c +++ b/drivers/media/rc/ttusbir.c @@ -318,7 +318,7 @@ static int ttusbir_probe(struct usb_interface *intf, usb_to_input_id(tt->udev, &rc->input_id); rc->dev.parent = &intf->dev; rc->driver_type = RC_DRIVER_IR_RAW; - rc->allowed_protos = RC_BIT_ALL; + rc_set_allowed_protocols(rc, RC_BIT_ALL); rc->priv = tt; rc->driver_name = DRIVER_NAME; rc->map_name = RC_MAP_TT_1500; diff --git a/drivers/media/rc/winbond-cir.c b/drivers/media/rc/winbond-cir.c index 904baf4..a8b981f 100644 --- a/drivers/media/rc/winbond-cir.c +++ b/drivers/media/rc/winbond-cir.c @@ -1082,7 +1082,7 @@ wbcir_probe(struct pnp_dev *device, const struct pnp_device_id *dev_id) data->dev->dev.parent = &device->dev; data->dev->timeout = MS_TO_NS(100); data->dev->rx_resolution = US_TO_NS(2); - data->dev->allowed_protos = RC_BIT_ALL; + rc_set_allowed_protocols(data->dev, RC_BIT_ALL); err = rc_register_device(data->dev); if (err) diff --git a/drivers/media/usb/dvb-usb-v2/dvb_usb_core.c b/drivers/media/usb/dvb-usb-v2/dvb_usb_core.c index 8a054d6..de02db8 100644 --- a/drivers/media/usb/dvb-usb-v2/dvb_usb_core.c +++ b/drivers/media/usb/dvb-usb-v2/dvb_usb_core.c @@ -164,7 +164,7 @@ static int dvb_usbv2_remote_init(struct dvb_usb_device *d) dev->driver_name = (char *) d->props->driver_name; dev->map_name = d->rc.map_name; dev->driver_type = d->rc.driver_type; - dev->allowed_protos = d->rc.allowed_protos; + rc_set_allowed_protocols(dev, d->rc.allowed_protos); dev->change_protocol = d->rc.change_protocol; dev->priv = d; diff --git a/drivers/media/usb/dvb-usb/dvb-usb-remote.c b/drivers/media/usb/dvb-usb/dvb-usb-remote.c index 41bacff..4058aea 100644 --- a/drivers/media/usb/dvb-usb/dvb-usb-remote.c +++ b/drivers/media/usb/dvb-usb/dvb-usb-remote.c @@ -272,7 +272,7 @@ static int rc_core_dvb_usb_remote_init(struct dvb_usb_device *d) dev->driver_name = d->props.rc.core.module_name; dev->map_name = d->props.rc.core.rc_codes; dev->change_protocol = d->props.rc.core.change_protocol; - dev->allowed_protos = d->props.rc.core.allowed_protos; + rc_set_allowed_protocols(dev, d->props.rc.core.allowed_protos); dev->driver_type = d->props.rc.core.driver_type; usb_to_input_id(d->udev, &dev->input_id); dev->input_name = "IR-receiver inside an USB DVB receiver"; diff --git a/drivers/media/usb/em28xx/em28xx-input.c b/drivers/media/usb/em28xx/em28xx-input.c index 2a9bf66..56ef49d 100644 --- a/drivers/media/usb/em28xx/em28xx-input.c +++ b/drivers/media/usb/em28xx/em28xx-input.c @@ -727,7 +727,7 @@ static int em28xx_ir_init(struct em28xx *dev) case EM2820_BOARD_HAUPPAUGE_WINTV_USB_2: rc->map_name = RC_MAP_HAUPPAUGE; ir->get_key_i2c = em28xx_get_key_em_haup; - rc->allowed_protos = RC_BIT_RC5; + rc_set_allowed_protocols(rc, RC_BIT_RC5); break; case EM2820_BOARD_LEADTEK_WINFAST_USBII_DELUXE: rc->map_name = RC_MAP_WINFAST_USBII_DELUXE; @@ -743,7 +743,7 @@ static int em28xx_ir_init(struct em28xx *dev) switch (dev->chip_id) { case CHIP_ID_EM2860: case CHIP_ID_EM2883: - rc->allowed_protos = RC_BIT_RC5 | RC_BIT_NEC; + rc_set_allowed_protocols(rc, RC_BIT_RC5 | RC_BIT_NEC); ir->get_key = default_polling_getkey; break; case CHIP_ID_EM2884: @@ -751,8 +751,8 @@ static int em28xx_ir_init(struct em28xx *dev) case CHIP_ID_EM28174: case CHIP_ID_EM28178: ir->get_key = em2874_polling_getkey; - rc->allowed_protos = RC_BIT_RC5 | RC_BIT_NEC | - RC_BIT_RC6_0; + rc_set_allowed_protocols(rc, RC_BIT_RC5 | RC_BIT_NEC | + RC_BIT_RC6_0); break; default: err = -ENODEV; diff --git a/drivers/media/usb/tm6000/tm6000-input.c b/drivers/media/usb/tm6000/tm6000-input.c index 8a6bbf1..d1af543 100644 --- a/drivers/media/usb/tm6000/tm6000-input.c +++ b/drivers/media/usb/tm6000/tm6000-input.c @@ -422,7 +422,7 @@ int tm6000_ir_init(struct tm6000_core *dev) ir->rc = rc; /* input setup */ - rc->allowed_protos = RC_BIT_RC5 | RC_BIT_NEC; + rc_set_allowed_protocols(rc, RC_BIT_RC5 | RC_BIT_NEC); /* Neded, in order to support NEC remotes with 24 or 32 bits */ rc->scanmask = 0xffff; rc->priv = ir; diff --git a/include/media/rc-core.h b/include/media/rc-core.h index 5e7197e..6f3c3d9 100644 --- a/include/media/rc-core.h +++ b/include/media/rc-core.h @@ -160,6 +160,28 @@ struct rc_dev { #define to_rc_dev(d) container_of(d, struct rc_dev, dev) +static inline bool rc_protocols_allowed(struct rc_dev *rdev, u64 protos) +{ + return rdev->allowed_protos & protos; +} + +/* should be called prior to registration or with mutex held */ +static inline void rc_set_allowed_protocols(struct rc_dev *rdev, u64 protos) +{ + rdev->allowed_protos = protos; +} + +static inline bool rc_protocols_enabled(struct rc_dev *rdev, u64 protos) +{ + return rdev->enabled_protocols & protos; +} + +/* should be called prior to registration or with mutex held */ +static inline void rc_set_enabled_protocols(struct rc_dev *rdev, u64 protos) +{ + rdev->enabled_protocols = protos; +} + /* * From rc-main.c * Those functions can be used on any type of Remote Controller. They -- cgit v1.1 From acff5f24732acc8a55d0a0f0ee1d19442267df63 Mon Sep 17 00:00:00 2001 From: James Hogan Date: Fri, 28 Feb 2014 20:17:04 -0300 Subject: [media] rc: add allowed/enabled wakeup protocol masks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Only a single allowed and enabled protocol mask currently exists in struct rc_dev, however to support a separate wakeup filter protocol two of each are needed, ideally as an array. Therefore make both rc_dev::allowed_protos and rc_dev::enabled_protocols arrays, update all users to reference the first element (RC_FILTER_NORMAL), and add a couple more helper functions for drivers to use for setting the allowed and enabled wakeup protocols. We also rename allowed_protos to allowed_protocols while we're at it, which is more consistent with enabled_protocols. Signed-off-by: James Hogan Reviewed-by: Antti Seppälä Signed-off-by: Mauro Carvalho Chehab --- drivers/media/rc/rc-main.c | 10 +++++----- include/media/rc-core.h | 32 ++++++++++++++++++++++++-------- 2 files changed, 29 insertions(+), 13 deletions(-) diff --git a/drivers/media/rc/rc-main.c b/drivers/media/rc/rc-main.c index 0a4f680..309d791 100644 --- a/drivers/media/rc/rc-main.c +++ b/drivers/media/rc/rc-main.c @@ -830,9 +830,9 @@ static ssize_t show_protocols(struct device *device, mutex_lock(&dev->lock); - enabled = dev->enabled_protocols; + enabled = dev->enabled_protocols[RC_FILTER_NORMAL]; if (dev->driver_type == RC_DRIVER_SCANCODE) - allowed = dev->allowed_protos; + allowed = dev->allowed_protocols[RC_FILTER_NORMAL]; else if (dev->raw) allowed = ir_raw_get_allowed_protocols(); else { @@ -906,7 +906,7 @@ static ssize_t store_protocols(struct device *device, ret = -EINVAL; goto out; } - type = dev->enabled_protocols; + type = dev->enabled_protocols[RC_FILTER_NORMAL]; while ((tmp = strsep((char **) &data, " \n")) != NULL) { if (!*tmp) @@ -964,7 +964,7 @@ static ssize_t store_protocols(struct device *device, } } - dev->enabled_protocols = type; + dev->enabled_protocols[RC_FILTER_NORMAL] = type; IR_dprintk(1, "Current protocol(s): 0x%llx\n", (long long)type); @@ -1316,7 +1316,7 @@ int rc_register_device(struct rc_dev *dev) rc = dev->change_protocol(dev, &rc_type); if (rc < 0) goto out_raw; - dev->enabled_protocols = rc_type; + dev->enabled_protocols[RC_FILTER_NORMAL] = rc_type; } mutex_unlock(&dev->lock); diff --git a/include/media/rc-core.h b/include/media/rc-core.h index 6f3c3d9..f165115 100644 --- a/include/media/rc-core.h +++ b/include/media/rc-core.h @@ -73,8 +73,10 @@ enum rc_filter_type { * @input_dev: the input child device used to communicate events to userspace * @driver_type: specifies if protocol decoding is done in hardware or software * @idle: used to keep track of RX state - * @allowed_protos: bitmask with the supported RC_BIT_* protocols - * @enabled_protocols: bitmask with the enabled RC_BIT_* protocols + * @allowed_protocols: bitmask with the supported RC_BIT_* protocols for each + * filter type + * @enabled_protocols: bitmask with the enabled RC_BIT_* protocols for each + * filter type * @scanmask: some hardware decoders are not capable of providing the full * scancode to the application. As this is a hardware limit, we can't do * anything with it. Yet, as the same keycode table can be used with other @@ -124,8 +126,8 @@ struct rc_dev { struct input_dev *input_dev; enum rc_driver_type driver_type; bool idle; - u64 allowed_protos; - u64 enabled_protocols; + u64 allowed_protocols[RC_FILTER_MAX]; + u64 enabled_protocols[RC_FILTER_MAX]; u32 users; u32 scanmask; void *priv; @@ -162,24 +164,38 @@ struct rc_dev { static inline bool rc_protocols_allowed(struct rc_dev *rdev, u64 protos) { - return rdev->allowed_protos & protos; + return rdev->allowed_protocols[RC_FILTER_NORMAL] & protos; } /* should be called prior to registration or with mutex held */ static inline void rc_set_allowed_protocols(struct rc_dev *rdev, u64 protos) { - rdev->allowed_protos = protos; + rdev->allowed_protocols[RC_FILTER_NORMAL] = protos; } static inline bool rc_protocols_enabled(struct rc_dev *rdev, u64 protos) { - return rdev->enabled_protocols & protos; + return rdev->enabled_protocols[RC_FILTER_NORMAL] & protos; } /* should be called prior to registration or with mutex held */ static inline void rc_set_enabled_protocols(struct rc_dev *rdev, u64 protos) { - rdev->enabled_protocols = protos; + rdev->enabled_protocols[RC_FILTER_NORMAL] = protos; +} + +/* should be called prior to registration or with mutex held */ +static inline void rc_set_allowed_wakeup_protocols(struct rc_dev *rdev, + u64 protos) +{ + rdev->allowed_protocols[RC_FILTER_WAKEUP] = protos; +} + +/* should be called prior to registration or with mutex held */ +static inline void rc_set_enabled_wakeup_protocols(struct rc_dev *rdev, + u64 protos) +{ + rdev->enabled_protocols[RC_FILTER_WAKEUP] = protos; } /* -- cgit v1.1 From ab88c66deace78989aa71cb139284cf7fb227ba4 Mon Sep 17 00:00:00 2001 From: James Hogan Date: Fri, 28 Feb 2014 20:17:05 -0300 Subject: [media] rc: add wakeup_protocols sysfs file MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a wakeup_protocols sysfs file which controls the new rc_dev::enabled_protocols[RC_FILTER_WAKEUP], which is the mask of protocols that are used for the wakeup filter. A new RC driver callback change_wakeup_protocol() is called to change the wakeup protocol mask. Signed-off-by: James Hogan Reviewed-by: Antti Seppälä Signed-off-by: Mauro Carvalho Chehab --- Documentation/ABI/testing/sysfs-class-rc | 23 +++++- .../DocBook/media/v4l/remote_controllers.xml | 20 +++++- drivers/media/rc/rc-main.c | 82 +++++++++++++--------- include/media/rc-core.h | 3 + 4 files changed, 90 insertions(+), 38 deletions(-) diff --git a/Documentation/ABI/testing/sysfs-class-rc b/Documentation/ABI/testing/sysfs-class-rc index c0e1d14..b65674d 100644 --- a/Documentation/ABI/testing/sysfs-class-rc +++ b/Documentation/ABI/testing/sysfs-class-rc @@ -61,6 +61,25 @@ Description: an error. This value may be reset to 0 if the current protocol is altered. +What: /sys/class/rc/rcN/wakeup_protocols +Date: Feb 2014 +KernelVersion: 3.15 +Contact: Mauro Carvalho Chehab +Description: + Reading this file returns a list of available protocols to use + for the wakeup filter, something like: + "rc5 rc6 nec jvc [sony]" + The enabled wakeup protocol is shown in [] brackets. + Writing "+proto" will add a protocol to the list of enabled + wakeup protocols. + Writing "-proto" will remove a protocol from the list of enabled + wakeup protocols. + Writing "proto" will use "proto" for wakeup events. + Writing "none" will disable wakeup. + Write fails with EINVAL if an invalid protocol combination or + unknown protocol name is used, or if wakeup is not supported by + the hardware. + What: /sys/class/rc/rcN/wakeup_filter Date: Jan 2014 KernelVersion: 3.15 @@ -74,7 +93,7 @@ Description: scancodes which match the filter will wake the system from e.g. suspend to RAM or power off. Otherwise the write will fail with an error. - This value may be reset to 0 if the current protocol is altered. + This value may be reset to 0 if the wakeup protocol is altered. What: /sys/class/rc/rcN/wakeup_filter_mask Date: Jan 2014 @@ -89,4 +108,4 @@ Description: scancodes which match the filter will wake the system from e.g. suspend to RAM or power off. Otherwise the write will fail with an error. - This value may be reset to 0 if the current protocol is altered. + This value may be reset to 0 if the wakeup protocol is altered. diff --git a/Documentation/DocBook/media/v4l/remote_controllers.xml b/Documentation/DocBook/media/v4l/remote_controllers.xml index c440a81..5124a6c 100644 --- a/Documentation/DocBook/media/v4l/remote_controllers.xml +++ b/Documentation/DocBook/media/v4l/remote_controllers.xml @@ -102,6 +102,22 @@ an error. This value may be reset to 0 if the current protocol is altered. +
+/sys/class/rc/rcN/wakeup_protocols +Reading this file returns a list of available protocols to use for the +wakeup filter, something like: +rc5 rc6 nec jvc [sony] +The enabled wakeup protocol is shown in [] brackets. +Writing "+proto" will add a protocol to the list of enabled wakeup +protocols. +Writing "-proto" will remove a protocol from the list of enabled wakeup +protocols. +Writing "proto" will use "proto" for wakeup events. +Writing "none" will disable wakeup. +Write fails with EINVAL if an invalid protocol combination or unknown +protocol name is used, or if wakeup is not supported by the hardware. + +
/sys/class/rc/rcN/wakeup_filter Sets the scancode wakeup filter expected value. @@ -112,7 +128,7 @@ to trigger a system wake event. scancodes which match the filter will wake the system from e.g. suspend to RAM or power off. Otherwise the write will fail with an error. -This value may be reset to 0 if the current protocol is altered. +This value may be reset to 0 if the wakeup protocol is altered.
@@ -125,7 +141,7 @@ expected value to trigger a system wake event. scancodes which match the filter will wake the system from e.g. suspend to RAM or power off. Otherwise the write will fail with an error. -This value may be reset to 0 if the current protocol is altered. +This value may be reset to 0 if the wakeup protocol is altered.
diff --git a/drivers/media/rc/rc-main.c b/drivers/media/rc/rc-main.c index 309d791..e6e3ec7 100644 --- a/drivers/media/rc/rc-main.c +++ b/drivers/media/rc/rc-main.c @@ -803,13 +803,38 @@ static struct { }; /** - * show_protocols() - shows the current IR protocol(s) + * struct rc_filter_attribute - Device attribute relating to a filter type. + * @attr: Device attribute. + * @type: Filter type. + * @mask: false for filter value, true for filter mask. + */ +struct rc_filter_attribute { + struct device_attribute attr; + enum rc_filter_type type; + bool mask; +}; +#define to_rc_filter_attr(a) container_of(a, struct rc_filter_attribute, attr) + +#define RC_PROTO_ATTR(_name, _mode, _show, _store, _type) \ + struct rc_filter_attribute dev_attr_##_name = { \ + .attr = __ATTR(_name, _mode, _show, _store), \ + .type = (_type), \ + } +#define RC_FILTER_ATTR(_name, _mode, _show, _store, _type, _mask) \ + struct rc_filter_attribute dev_attr_##_name = { \ + .attr = __ATTR(_name, _mode, _show, _store), \ + .type = (_type), \ + .mask = (_mask), \ + } + +/** + * show_protocols() - shows the current/wakeup IR protocol(s) * @device: the device descriptor * @mattr: the device attribute struct (unused) * @buf: a pointer to the output buffer * * This routine is a callback routine for input read the IR protocol type(s). - * it is trigged by reading /sys/class/rc/rc?/protocols. + * it is trigged by reading /sys/class/rc/rc?/[wakeup_]protocols. * It returns the protocol names of supported protocols. * Enabled protocols are printed in brackets. * @@ -820,6 +845,7 @@ static ssize_t show_protocols(struct device *device, struct device_attribute *mattr, char *buf) { struct rc_dev *dev = to_rc_dev(device); + struct rc_filter_attribute *fattr = to_rc_filter_attr(mattr); u64 allowed, enabled; char *tmp = buf; int i; @@ -830,9 +856,10 @@ static ssize_t show_protocols(struct device *device, mutex_lock(&dev->lock); - enabled = dev->enabled_protocols[RC_FILTER_NORMAL]; - if (dev->driver_type == RC_DRIVER_SCANCODE) - allowed = dev->allowed_protocols[RC_FILTER_NORMAL]; + enabled = dev->enabled_protocols[fattr->type]; + if (dev->driver_type == RC_DRIVER_SCANCODE || + fattr->type == RC_FILTER_WAKEUP) + allowed = dev->allowed_protocols[fattr->type]; else if (dev->raw) allowed = ir_raw_get_allowed_protocols(); else { @@ -864,14 +891,14 @@ static ssize_t show_protocols(struct device *device, } /** - * store_protocols() - changes the current IR protocol(s) + * store_protocols() - changes the current/wakeup IR protocol(s) * @device: the device descriptor * @mattr: the device attribute struct (unused) * @buf: a pointer to the input buffer * @len: length of the input buffer * * This routine is for changing the IR protocol type. - * It is trigged by writing to /sys/class/rc/rc?/protocols. + * It is trigged by writing to /sys/class/rc/rc?/[wakeup_]protocols. * Writing "+proto" will add a protocol to the list of enabled protocols. * Writing "-proto" will remove a protocol from the list of enabled protocols. * Writing "proto" will enable only "proto". @@ -888,12 +915,14 @@ static ssize_t store_protocols(struct device *device, size_t len) { struct rc_dev *dev = to_rc_dev(device); + struct rc_filter_attribute *fattr = to_rc_filter_attr(mattr); bool enable, disable; const char *tmp; u64 type; u64 mask; int rc, i, count = 0; ssize_t ret; + int (*change_protocol)(struct rc_dev *dev, u64 *rc_type); /* Device is being removed */ if (!dev) @@ -906,7 +935,7 @@ static ssize_t store_protocols(struct device *device, ret = -EINVAL; goto out; } - type = dev->enabled_protocols[RC_FILTER_NORMAL]; + type = dev->enabled_protocols[fattr->type]; while ((tmp = strsep((char **) &data, " \n")) != NULL) { if (!*tmp) @@ -954,8 +983,10 @@ static ssize_t store_protocols(struct device *device, goto out; } - if (dev->change_protocol) { - rc = dev->change_protocol(dev, &type); + change_protocol = (fattr->type == RC_FILTER_NORMAL) + ? dev->change_protocol : dev->change_wakeup_protocol; + if (change_protocol) { + rc = change_protocol(dev, &type); if (rc < 0) { IR_dprintk(1, "Error setting protocols to 0x%llx\n", (long long)type); @@ -964,7 +995,7 @@ static ssize_t store_protocols(struct device *device, } } - dev->enabled_protocols[RC_FILTER_NORMAL] = type; + dev->enabled_protocols[fattr->type] = type; IR_dprintk(1, "Current protocol(s): 0x%llx\n", (long long)type); @@ -976,26 +1007,6 @@ out: } /** - * struct rc_filter_attribute - Device attribute relating to a filter type. - * @attr: Device attribute. - * @type: Filter type. - * @mask: false for filter value, true for filter mask. - */ -struct rc_filter_attribute { - struct device_attribute attr; - enum rc_filter_type type; - bool mask; -}; -#define to_rc_filter_attr(a) container_of(a, struct rc_filter_attribute, attr) - -#define RC_FILTER_ATTR(_name, _mode, _show, _store, _type, _mask) \ - struct rc_filter_attribute dev_attr_##_name = { \ - .attr = __ATTR(_name, _mode, _show, _store), \ - .type = (_type), \ - .mask = (_mask), \ - } - -/** * show_filter() - shows the current scancode filter value or mask * @device: the device descriptor * @attr: the device attribute struct @@ -1128,8 +1139,10 @@ static int rc_dev_uevent(struct device *device, struct kobj_uevent_env *env) /* * Static device attribute struct with the sysfs attributes for IR's */ -static DEVICE_ATTR(protocols, S_IRUGO | S_IWUSR, - show_protocols, store_protocols); +static RC_PROTO_ATTR(protocols, S_IRUGO | S_IWUSR, + show_protocols, store_protocols, RC_FILTER_NORMAL); +static RC_PROTO_ATTR(wakeup_protocols, S_IRUGO | S_IWUSR, + show_protocols, store_protocols, RC_FILTER_WAKEUP); static RC_FILTER_ATTR(filter, S_IRUGO|S_IWUSR, show_filter, store_filter, RC_FILTER_NORMAL, false); static RC_FILTER_ATTR(filter_mask, S_IRUGO|S_IWUSR, @@ -1140,7 +1153,8 @@ static RC_FILTER_ATTR(wakeup_filter_mask, S_IRUGO|S_IWUSR, show_filter, store_filter, RC_FILTER_WAKEUP, true); static struct attribute *rc_dev_attrs[] = { - &dev_attr_protocols.attr, + &dev_attr_protocols.attr.attr, + &dev_attr_wakeup_protocols.attr.attr, &dev_attr_filter.attr.attr, &dev_attr_filter_mask.attr.attr, &dev_attr_wakeup_filter.attr.attr, diff --git a/include/media/rc-core.h b/include/media/rc-core.h index f165115..0b9f890 100644 --- a/include/media/rc-core.h +++ b/include/media/rc-core.h @@ -97,6 +97,8 @@ enum rc_filter_type { * @tx_resolution: resolution (in ns) of output sampler * @scancode_filters: scancode filters (indexed by enum rc_filter_type) * @change_protocol: allow changing the protocol used on hardware decoders + * @change_wakeup_protocol: allow changing the protocol used for wakeup + * filtering * @open: callback to allow drivers to enable polling/irq when IR input device * is opened. * @close: callback to allow drivers to disable polling/irq when IR input device @@ -145,6 +147,7 @@ struct rc_dev { u32 tx_resolution; struct rc_scancode_filter scancode_filters[RC_FILTER_MAX]; int (*change_protocol)(struct rc_dev *dev, u64 *rc_type); + int (*change_wakeup_protocol)(struct rc_dev *dev, u64 *rc_type); int (*open)(struct rc_dev *dev); void (*close)(struct rc_dev *dev); int (*s_tx_mask)(struct rc_dev *dev, u32 mask); -- cgit v1.1 From 6bea25af147fcddcd8fd4557f4184c847c5c6ffd Mon Sep 17 00:00:00 2001 From: James Hogan Date: Fri, 28 Feb 2014 20:17:06 -0300 Subject: [media] rc-main: automatically refresh filter on protocol change MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When either of the normal or wakeup filter protocols are changed, refresh the corresponding scancode filter, i.e. try and set the same scancode filter with the new protocol. If that fails clear the filter instead. If no protocol was selected the filter is just cleared, and if no s_filter callback exists the filter is left unmodified. Similarly clear the filter mask when the filter is set if no protocol is currently selected. This simplifies driver code which no longer has to explicitly worry about modifying the filter on a protocol change. This also allows the change_wakeup_protocol callback to be omitted entirely if there is only a single available wakeup protocol at a time, since selecting no protocol will automatically clear the wakeup filter, disabling wakeup. Signed-off-by: James Hogan Reviewed-by: Antti Seppälä Signed-off-by: Mauro Carvalho Chehab --- drivers/media/rc/rc-main.c | 41 +++++++++++++++++++++++++++++++++++++++-- 1 file changed, 39 insertions(+), 2 deletions(-) diff --git a/drivers/media/rc/rc-main.c b/drivers/media/rc/rc-main.c index e6e3ec7..b1a6900 100644 --- a/drivers/media/rc/rc-main.c +++ b/drivers/media/rc/rc-main.c @@ -918,11 +918,12 @@ static ssize_t store_protocols(struct device *device, struct rc_filter_attribute *fattr = to_rc_filter_attr(mattr); bool enable, disable; const char *tmp; - u64 type; + u64 old_type, type; u64 mask; int rc, i, count = 0; ssize_t ret; int (*change_protocol)(struct rc_dev *dev, u64 *rc_type); + struct rc_scancode_filter local_filter, *filter; /* Device is being removed */ if (!dev) @@ -935,7 +936,8 @@ static ssize_t store_protocols(struct device *device, ret = -EINVAL; goto out; } - type = dev->enabled_protocols[fattr->type]; + old_type = dev->enabled_protocols[fattr->type]; + type = old_type; while ((tmp = strsep((char **) &data, " \n")) != NULL) { if (!*tmp) @@ -999,6 +1001,36 @@ static ssize_t store_protocols(struct device *device, IR_dprintk(1, "Current protocol(s): 0x%llx\n", (long long)type); + /* + * If the protocol is changed the filter needs updating. + * Try setting the same filter with the new protocol (if any). + * Fall back to clearing the filter. + */ + filter = &dev->scancode_filters[fattr->type]; + if (old_type != type && filter->mask) { + local_filter = *filter; + if (!type) { + /* no protocol => clear filter */ + ret = -1; + } else if (!dev->s_filter) { + /* generic filtering => accept any filter */ + ret = 0; + } else { + /* hardware filtering => try setting, otherwise clear */ + ret = dev->s_filter(dev, fattr->type, &local_filter); + } + if (ret < 0) { + /* clear the filter */ + local_filter.data = 0; + local_filter.mask = 0; + if (dev->s_filter) + dev->s_filter(dev, fattr->type, &local_filter); + } + + /* commit the new filter */ + *filter = local_filter; + } + ret = len; out: @@ -1096,6 +1128,11 @@ static ssize_t store_filter(struct device *device, local_filter.mask = val; else local_filter.data = val; + if (!dev->enabled_protocols[fattr->type] && local_filter.mask) { + /* refuse to set a filter unless a protocol is enabled */ + ret = -EINVAL; + goto unlock; + } if (dev->s_filter) { ret = dev->s_filter(dev, fattr->type, &local_filter); if (ret < 0) -- cgit v1.1 From f99bababe0ac3f4d6f8b0368a22600f0ba24042b Mon Sep 17 00:00:00 2001 From: James Hogan Date: Fri, 28 Feb 2014 20:28:51 -0300 Subject: [media] dt: binding: add binding for ImgTec IR block Add device tree binding for ImgTec Consumer Infrared block, specifically major revision 1 of the hardware. Signed-off-by: James Hogan Acked-by: Rob Herring Signed-off-by: Mauro Carvalho Chehab --- .../devicetree/bindings/media/img-ir-rev1.txt | 34 ++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/img-ir-rev1.txt diff --git a/Documentation/devicetree/bindings/media/img-ir-rev1.txt b/Documentation/devicetree/bindings/media/img-ir-rev1.txt new file mode 100644 index 0000000..5434ce6 --- /dev/null +++ b/Documentation/devicetree/bindings/media/img-ir-rev1.txt @@ -0,0 +1,34 @@ +* ImgTec Infrared (IR) decoder version 1 + +This binding is for Imagination Technologies' Infrared decoder block, +specifically major revision 1. + +Required properties: +- compatible: Should be "img,ir-rev1" +- reg: Physical base address of the controller and length of + memory mapped region. +- interrupts: The interrupt specifier to the cpu. + +Optional properties: +- clocks: List of clock specifiers as described in standard + clock bindings. + Up to 3 clocks may be specified in the following order: + 1st: Core clock (defaults to 32.768KHz if omitted). + 2nd: System side (fast) clock. + 3rd: Power modulation clock. +- clock-names: List of clock names corresponding to the clocks + specified in the clocks property. + Accepted clock names are: + "core": Core clock. + "sys": System clock. + "mod": Power modulation clock. + +Example: + + ir@02006200 { + compatible = "img,ir-rev1"; + reg = <0x02006200 0x100>; + interrupts = <29 4>; + clocks = <&clk_32khz>; + clock-names = "core"; + }; -- cgit v1.1 From 160a8f8aec4da4b68842784be3e7296e8c9860dc Mon Sep 17 00:00:00 2001 From: James Hogan Date: Fri, 28 Feb 2014 20:28:52 -0300 Subject: [media] rc: img-ir: add base driver Add base driver for the ImgTec Infrared decoder block. The driver is split into separate components for raw (software) decode and hardware decoder which are in following commits. Signed-off-by: James Hogan Signed-off-by: Mauro Carvalho Chehab --- drivers/media/rc/img-ir/img-ir-core.c | 176 ++++++++++++++++++++++++++++++++++ drivers/media/rc/img-ir/img-ir.h | 166 ++++++++++++++++++++++++++++++++ 2 files changed, 342 insertions(+) create mode 100644 drivers/media/rc/img-ir/img-ir-core.c create mode 100644 drivers/media/rc/img-ir/img-ir.h diff --git a/drivers/media/rc/img-ir/img-ir-core.c b/drivers/media/rc/img-ir/img-ir-core.c new file mode 100644 index 0000000..6b78348 --- /dev/null +++ b/drivers/media/rc/img-ir/img-ir-core.c @@ -0,0 +1,176 @@ +/* + * ImgTec IR Decoder found in PowerDown Controller. + * + * Copyright 2010-2014 Imagination Technologies Ltd. + * + * This contains core img-ir code for setting up the driver. The two interfaces + * (raw and hardware decode) are handled separately. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "img-ir.h" + +static irqreturn_t img_ir_isr(int irq, void *dev_id) +{ + struct img_ir_priv *priv = dev_id; + u32 irq_status; + + spin_lock(&priv->lock); + /* we have to clear irqs before reading */ + irq_status = img_ir_read(priv, IMG_IR_IRQ_STATUS); + img_ir_write(priv, IMG_IR_IRQ_CLEAR, irq_status); + + /* don't handle valid data irqs if we're only interested in matches */ + irq_status &= img_ir_read(priv, IMG_IR_IRQ_ENABLE); + + /* hand off edge interrupts to raw decode handler */ + if (irq_status & IMG_IR_IRQ_EDGE && img_ir_raw_enabled(&priv->raw)) + img_ir_isr_raw(priv, irq_status); + + /* hand off hardware match interrupts to hardware decode handler */ + if (irq_status & (IMG_IR_IRQ_DATA_MATCH | + IMG_IR_IRQ_DATA_VALID | + IMG_IR_IRQ_DATA2_VALID) && + img_ir_hw_enabled(&priv->hw)) + img_ir_isr_hw(priv, irq_status); + + spin_unlock(&priv->lock); + return IRQ_HANDLED; +} + +static void img_ir_setup(struct img_ir_priv *priv) +{ + /* start off with interrupts disabled */ + img_ir_write(priv, IMG_IR_IRQ_ENABLE, 0); + + img_ir_setup_raw(priv); + img_ir_setup_hw(priv); + + if (!IS_ERR(priv->clk)) + clk_prepare_enable(priv->clk); +} + +static void img_ir_ident(struct img_ir_priv *priv) +{ + u32 core_rev = img_ir_read(priv, IMG_IR_CORE_REV); + + dev_info(priv->dev, + "IMG IR Decoder (%d.%d.%d.%d) probed successfully\n", + (core_rev & IMG_IR_DESIGNER) >> IMG_IR_DESIGNER_SHIFT, + (core_rev & IMG_IR_MAJOR_REV) >> IMG_IR_MAJOR_REV_SHIFT, + (core_rev & IMG_IR_MINOR_REV) >> IMG_IR_MINOR_REV_SHIFT, + (core_rev & IMG_IR_MAINT_REV) >> IMG_IR_MAINT_REV_SHIFT); + dev_info(priv->dev, "Modes:%s%s\n", + img_ir_hw_enabled(&priv->hw) ? " hardware" : "", + img_ir_raw_enabled(&priv->raw) ? " raw" : ""); +} + +static int img_ir_probe(struct platform_device *pdev) +{ + struct img_ir_priv *priv; + struct resource *res_regs; + int irq, error, error2; + + /* Get resources from platform device */ + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + dev_err(&pdev->dev, "cannot find IRQ resource\n"); + return irq; + } + + /* Private driver data */ + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) { + dev_err(&pdev->dev, "cannot allocate device data\n"); + return -ENOMEM; + } + platform_set_drvdata(pdev, priv); + priv->dev = &pdev->dev; + spin_lock_init(&priv->lock); + + /* Ioremap the registers */ + res_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); + priv->reg_base = devm_ioremap_resource(&pdev->dev, res_regs); + if (IS_ERR(priv->reg_base)) + return PTR_ERR(priv->reg_base); + + /* Get core clock */ + priv->clk = devm_clk_get(&pdev->dev, "core"); + if (IS_ERR(priv->clk)) + dev_warn(&pdev->dev, "cannot get core clock resource\n"); + /* + * The driver doesn't need to know about the system ("sys") or power + * modulation ("mod") clocks yet + */ + + /* Set up raw & hw decoder */ + error = img_ir_probe_raw(priv); + error2 = img_ir_probe_hw(priv); + if (error && error2) + return (error == -ENODEV) ? error2 : error; + + /* Get the IRQ */ + priv->irq = irq; + error = request_irq(priv->irq, img_ir_isr, 0, "img-ir", priv); + if (error) { + dev_err(&pdev->dev, "cannot register IRQ %u\n", + priv->irq); + error = -EIO; + goto err_irq; + } + + img_ir_ident(priv); + img_ir_setup(priv); + + return 0; + +err_irq: + img_ir_remove_hw(priv); + img_ir_remove_raw(priv); + return error; +} + +static int img_ir_remove(struct platform_device *pdev) +{ + struct img_ir_priv *priv = platform_get_drvdata(pdev); + + free_irq(priv->irq, img_ir_isr); + img_ir_remove_hw(priv); + img_ir_remove_raw(priv); + + if (!IS_ERR(priv->clk)) + clk_disable_unprepare(priv->clk); + return 0; +} + +static SIMPLE_DEV_PM_OPS(img_ir_pmops, img_ir_suspend, img_ir_resume); + +static const struct of_device_id img_ir_match[] = { + { .compatible = "img,ir-rev1" }, + {} +}; +MODULE_DEVICE_TABLE(of, img_ir_match); + +static struct platform_driver img_ir_driver = { + .driver = { + .name = "img-ir", + .owner = THIS_MODULE, + .of_match_table = img_ir_match, + .pm = &img_ir_pmops, + }, + .probe = img_ir_probe, + .remove = img_ir_remove, +}; + +module_platform_driver(img_ir_driver); + +MODULE_AUTHOR("Imagination Technologies Ltd."); +MODULE_DESCRIPTION("ImgTec IR"); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/rc/img-ir/img-ir.h b/drivers/media/rc/img-ir/img-ir.h new file mode 100644 index 0000000..afb1893 --- /dev/null +++ b/drivers/media/rc/img-ir/img-ir.h @@ -0,0 +1,166 @@ +/* + * ImgTec IR Decoder found in PowerDown Controller. + * + * Copyright 2010-2014 Imagination Technologies Ltd. + */ + +#ifndef _IMG_IR_H_ +#define _IMG_IR_H_ + +#include +#include + +#include "img-ir-raw.h" +#include "img-ir-hw.h" + +/* registers */ + +/* relative to the start of the IR block of registers */ +#define IMG_IR_CONTROL 0x00 +#define IMG_IR_STATUS 0x04 +#define IMG_IR_DATA_LW 0x08 +#define IMG_IR_DATA_UP 0x0c +#define IMG_IR_LEAD_SYMB_TIMING 0x10 +#define IMG_IR_S00_SYMB_TIMING 0x14 +#define IMG_IR_S01_SYMB_TIMING 0x18 +#define IMG_IR_S10_SYMB_TIMING 0x1c +#define IMG_IR_S11_SYMB_TIMING 0x20 +#define IMG_IR_FREE_SYMB_TIMING 0x24 +#define IMG_IR_POW_MOD_PARAMS 0x28 +#define IMG_IR_POW_MOD_ENABLE 0x2c +#define IMG_IR_IRQ_MSG_DATA_LW 0x30 +#define IMG_IR_IRQ_MSG_DATA_UP 0x34 +#define IMG_IR_IRQ_MSG_MASK_LW 0x38 +#define IMG_IR_IRQ_MSG_MASK_UP 0x3c +#define IMG_IR_IRQ_ENABLE 0x40 +#define IMG_IR_IRQ_STATUS 0x44 +#define IMG_IR_IRQ_CLEAR 0x48 +#define IMG_IR_IRCORE_ID 0xf0 +#define IMG_IR_CORE_REV 0xf4 +#define IMG_IR_CORE_DES1 0xf8 +#define IMG_IR_CORE_DES2 0xfc + + +/* field masks */ + +/* IMG_IR_CONTROL */ +#define IMG_IR_DECODEN 0x40000000 +#define IMG_IR_CODETYPE 0x30000000 +#define IMG_IR_CODETYPE_SHIFT 28 +#define IMG_IR_HDRTOG 0x08000000 +#define IMG_IR_LDRDEC 0x04000000 +#define IMG_IR_DECODINPOL 0x02000000 /* active high */ +#define IMG_IR_BITORIEN 0x01000000 /* MSB first */ +#define IMG_IR_D1VALIDSEL 0x00008000 +#define IMG_IR_BITINV 0x00000040 /* don't invert */ +#define IMG_IR_DECODEND2 0x00000010 +#define IMG_IR_BITORIEND2 0x00000002 /* MSB first */ +#define IMG_IR_BITINVD2 0x00000001 /* don't invert */ + +/* IMG_IR_STATUS */ +#define IMG_IR_RXDVALD2 0x00001000 +#define IMG_IR_IRRXD 0x00000400 +#define IMG_IR_TOGSTATE 0x00000200 +#define IMG_IR_RXDVAL 0x00000040 +#define IMG_IR_RXDLEN 0x0000003f +#define IMG_IR_RXDLEN_SHIFT 0 + +/* IMG_IR_LEAD_SYMB_TIMING, IMG_IR_Sxx_SYMB_TIMING */ +#define IMG_IR_PD_MAX 0xff000000 +#define IMG_IR_PD_MAX_SHIFT 24 +#define IMG_IR_PD_MIN 0x00ff0000 +#define IMG_IR_PD_MIN_SHIFT 16 +#define IMG_IR_W_MAX 0x0000ff00 +#define IMG_IR_W_MAX_SHIFT 8 +#define IMG_IR_W_MIN 0x000000ff +#define IMG_IR_W_MIN_SHIFT 0 + +/* IMG_IR_FREE_SYMB_TIMING */ +#define IMG_IR_MAXLEN 0x0007e000 +#define IMG_IR_MAXLEN_SHIFT 13 +#define IMG_IR_MINLEN 0x00001f00 +#define IMG_IR_MINLEN_SHIFT 8 +#define IMG_IR_FT_MIN 0x000000ff +#define IMG_IR_FT_MIN_SHIFT 0 + +/* IMG_IR_POW_MOD_PARAMS */ +#define IMG_IR_PERIOD_LEN 0x3f000000 +#define IMG_IR_PERIOD_LEN_SHIFT 24 +#define IMG_IR_PERIOD_DUTY 0x003f0000 +#define IMG_IR_PERIOD_DUTY_SHIFT 16 +#define IMG_IR_STABLE_STOP 0x00003f00 +#define IMG_IR_STABLE_STOP_SHIFT 8 +#define IMG_IR_STABLE_START 0x0000003f +#define IMG_IR_STABLE_START_SHIFT 0 + +/* IMG_IR_POW_MOD_ENABLE */ +#define IMG_IR_POWER_OUT_EN 0x00000002 +#define IMG_IR_POWER_MOD_EN 0x00000001 + +/* IMG_IR_IRQ_ENABLE, IMG_IR_IRQ_STATUS, IMG_IR_IRQ_CLEAR */ +#define IMG_IR_IRQ_DEC2_ERR 0x00000080 +#define IMG_IR_IRQ_DEC_ERR 0x00000040 +#define IMG_IR_IRQ_ACT_LEVEL 0x00000020 +#define IMG_IR_IRQ_FALL_EDGE 0x00000010 +#define IMG_IR_IRQ_RISE_EDGE 0x00000008 +#define IMG_IR_IRQ_DATA_MATCH 0x00000004 +#define IMG_IR_IRQ_DATA2_VALID 0x00000002 +#define IMG_IR_IRQ_DATA_VALID 0x00000001 +#define IMG_IR_IRQ_ALL 0x000000ff +#define IMG_IR_IRQ_EDGE (IMG_IR_IRQ_FALL_EDGE | IMG_IR_IRQ_RISE_EDGE) + +/* IMG_IR_CORE_ID */ +#define IMG_IR_CORE_ID 0x00ff0000 +#define IMG_IR_CORE_ID_SHIFT 16 +#define IMG_IR_CORE_CONFIG 0x0000ffff +#define IMG_IR_CORE_CONFIG_SHIFT 0 + +/* IMG_IR_CORE_REV */ +#define IMG_IR_DESIGNER 0xff000000 +#define IMG_IR_DESIGNER_SHIFT 24 +#define IMG_IR_MAJOR_REV 0x00ff0000 +#define IMG_IR_MAJOR_REV_SHIFT 16 +#define IMG_IR_MINOR_REV 0x0000ff00 +#define IMG_IR_MINOR_REV_SHIFT 8 +#define IMG_IR_MAINT_REV 0x000000ff +#define IMG_IR_MAINT_REV_SHIFT 0 + +struct device; +struct clk; + +/** + * struct img_ir_priv - Private driver data. + * @dev: Platform device. + * @irq: IRQ number. + * @clk: Input clock. + * @reg_base: Iomem base address of IR register block. + * @lock: Protects IR registers and variables in this struct. + * @raw: Driver data for raw decoder. + * @hw: Driver data for hardware decoder. + */ +struct img_ir_priv { + struct device *dev; + int irq; + struct clk *clk; + void __iomem *reg_base; + spinlock_t lock; + + struct img_ir_priv_raw raw; + struct img_ir_priv_hw hw; +}; + +/* Hardware access */ + +static inline void img_ir_write(struct img_ir_priv *priv, + unsigned int reg_offs, unsigned int data) +{ + iowrite32(data, priv->reg_base + reg_offs); +} + +static inline unsigned int img_ir_read(struct img_ir_priv *priv, + unsigned int reg_offs) +{ + return ioread32(priv->reg_base + reg_offs); +} + +#endif /* _IMG_IR_H_ */ -- cgit v1.1 From 3fed7dbe8b94ab45298d9e63b90c1c57a01b6d5b Mon Sep 17 00:00:00 2001 From: James Hogan Date: Fri, 28 Feb 2014 20:28:53 -0300 Subject: [media] rc: img-ir: add raw driver Add raw IR remote control input driver for the ImgTec Infrared decoder block's raw edge interrupts. Generic software protocol decoders are used to allow multiple protocols to be supported at a time, including those not supported by the hardware decoder. Signed-off-by: James Hogan Signed-off-by: Mauro Carvalho Chehab --- drivers/media/rc/img-ir/img-ir-raw.c | 151 +++++++++++++++++++++++++++++++++++ drivers/media/rc/img-ir/img-ir-raw.h | 60 ++++++++++++++ 2 files changed, 211 insertions(+) create mode 100644 drivers/media/rc/img-ir/img-ir-raw.c create mode 100644 drivers/media/rc/img-ir/img-ir-raw.h diff --git a/drivers/media/rc/img-ir/img-ir-raw.c b/drivers/media/rc/img-ir/img-ir-raw.c new file mode 100644 index 0000000..cfb01d9 --- /dev/null +++ b/drivers/media/rc/img-ir/img-ir-raw.c @@ -0,0 +1,151 @@ +/* + * ImgTec IR Raw Decoder found in PowerDown Controller. + * + * Copyright 2010-2014 Imagination Technologies Ltd. + * + * This ties into the input subsystem using the RC-core in raw mode. Raw IR + * signal edges are reported and decoded by generic software decoders. + */ + +#include +#include +#include "img-ir.h" + +#define ECHO_TIMEOUT_MS 150 /* ms between echos */ + +/* must be called with priv->lock held */ +static void img_ir_refresh_raw(struct img_ir_priv *priv, u32 irq_status) +{ + struct img_ir_priv_raw *raw = &priv->raw; + struct rc_dev *rc_dev = priv->raw.rdev; + int multiple; + u32 ir_status; + + /* find whether both rise and fall was detected */ + multiple = ((irq_status & IMG_IR_IRQ_EDGE) == IMG_IR_IRQ_EDGE); + /* + * If so, we need to see if the level has actually changed. + * If it's just noise that we didn't have time to process, + * there's no point reporting it. + */ + ir_status = img_ir_read(priv, IMG_IR_STATUS) & IMG_IR_IRRXD; + if (multiple && ir_status == raw->last_status) + return; + raw->last_status = ir_status; + + /* report the edge to the IR raw decoders */ + if (ir_status) /* low */ + ir_raw_event_store_edge(rc_dev, IR_SPACE); + else /* high */ + ir_raw_event_store_edge(rc_dev, IR_PULSE); + ir_raw_event_handle(rc_dev); +} + +/* called with priv->lock held */ +void img_ir_isr_raw(struct img_ir_priv *priv, u32 irq_status) +{ + struct img_ir_priv_raw *raw = &priv->raw; + + /* check not removing */ + if (!raw->rdev) + return; + + img_ir_refresh_raw(priv, irq_status); + + /* start / push back the echo timer */ + mod_timer(&raw->timer, jiffies + msecs_to_jiffies(ECHO_TIMEOUT_MS)); +} + +/* + * Echo timer callback function. + * The raw decoders expect to get a final sample even if there are no edges, in + * order to be assured of the final space. If there are no edges for a certain + * time we use this timer to emit a final sample to satisfy them. + */ +static void img_ir_echo_timer(unsigned long arg) +{ + struct img_ir_priv *priv = (struct img_ir_priv *)arg; + + spin_lock_irq(&priv->lock); + + /* check not removing */ + if (priv->raw.rdev) + /* + * It's safe to pass irq_status=0 since it's only used to check + * for double edges. + */ + img_ir_refresh_raw(priv, 0); + + spin_unlock_irq(&priv->lock); +} + +void img_ir_setup_raw(struct img_ir_priv *priv) +{ + u32 irq_en; + + if (!priv->raw.rdev) + return; + + /* clear and enable edge interrupts */ + spin_lock_irq(&priv->lock); + irq_en = img_ir_read(priv, IMG_IR_IRQ_ENABLE); + irq_en |= IMG_IR_IRQ_EDGE; + img_ir_write(priv, IMG_IR_IRQ_CLEAR, IMG_IR_IRQ_EDGE); + img_ir_write(priv, IMG_IR_IRQ_ENABLE, irq_en); + spin_unlock_irq(&priv->lock); +} + +int img_ir_probe_raw(struct img_ir_priv *priv) +{ + struct img_ir_priv_raw *raw = &priv->raw; + struct rc_dev *rdev; + int error; + + /* Set up the echo timer */ + setup_timer(&raw->timer, img_ir_echo_timer, (unsigned long)priv); + + /* Allocate raw decoder */ + raw->rdev = rdev = rc_allocate_device(); + if (!rdev) { + dev_err(priv->dev, "cannot allocate raw input device\n"); + return -ENOMEM; + } + rdev->priv = priv; + rdev->map_name = RC_MAP_EMPTY; + rdev->input_name = "IMG Infrared Decoder Raw"; + rdev->driver_type = RC_DRIVER_IR_RAW; + + /* Register raw decoder */ + error = rc_register_device(rdev); + if (error) { + dev_err(priv->dev, "failed to register raw IR input device\n"); + rc_free_device(rdev); + raw->rdev = NULL; + return error; + } + + return 0; +} + +void img_ir_remove_raw(struct img_ir_priv *priv) +{ + struct img_ir_priv_raw *raw = &priv->raw; + struct rc_dev *rdev = raw->rdev; + u32 irq_en; + + if (!rdev) + return; + + /* switch off and disable raw (edge) interrupts */ + spin_lock_irq(&priv->lock); + raw->rdev = NULL; + irq_en = img_ir_read(priv, IMG_IR_IRQ_ENABLE); + irq_en &= ~IMG_IR_IRQ_EDGE; + img_ir_write(priv, IMG_IR_IRQ_ENABLE, irq_en); + img_ir_write(priv, IMG_IR_IRQ_CLEAR, IMG_IR_IRQ_EDGE); + spin_unlock_irq(&priv->lock); + + rc_unregister_device(rdev); + + del_timer_sync(&raw->timer); +} diff --git a/drivers/media/rc/img-ir/img-ir-raw.h b/drivers/media/rc/img-ir/img-ir-raw.h new file mode 100644 index 0000000..9802ffd --- /dev/null +++ b/drivers/media/rc/img-ir/img-ir-raw.h @@ -0,0 +1,60 @@ +/* + * ImgTec IR Raw Decoder found in PowerDown Controller. + * + * Copyright 2010-2014 Imagination Technologies Ltd. + */ + +#ifndef _IMG_IR_RAW_H_ +#define _IMG_IR_RAW_H_ + +struct img_ir_priv; + +#ifdef CONFIG_IR_IMG_RAW + +/** + * struct img_ir_priv_raw - Private driver data for raw decoder. + * @rdev: Raw remote control device + * @timer: Timer to echo samples to keep soft decoders happy. + * @last_status: Last raw status bits. + */ +struct img_ir_priv_raw { + struct rc_dev *rdev; + struct timer_list timer; + u32 last_status; +}; + +static inline bool img_ir_raw_enabled(struct img_ir_priv_raw *raw) +{ + return raw->rdev; +}; + +void img_ir_isr_raw(struct img_ir_priv *priv, u32 irq_status); +void img_ir_setup_raw(struct img_ir_priv *priv); +int img_ir_probe_raw(struct img_ir_priv *priv); +void img_ir_remove_raw(struct img_ir_priv *priv); + +#else + +struct img_ir_priv_raw { +}; +static inline bool img_ir_raw_enabled(struct img_ir_priv_raw *raw) +{ + return false; +}; +static inline void img_ir_isr_raw(struct img_ir_priv *priv, u32 irq_status) +{ +} +static inline void img_ir_setup_raw(struct img_ir_priv *priv) +{ +} +static inline int img_ir_probe_raw(struct img_ir_priv *priv) +{ + return -ENODEV; +} +static inline void img_ir_remove_raw(struct img_ir_priv *priv) +{ +} + +#endif /* CONFIG_IR_IMG_RAW */ + +#endif /* _IMG_IR_RAW_H_ */ -- cgit v1.1 From 30dd9e0c8dc3478b63d7865df5434fcf01a07f3f Mon Sep 17 00:00:00 2001 From: James Hogan Date: Fri, 28 Feb 2014 20:28:54 -0300 Subject: [media] rc: img-ir: add hardware decoder driver Add remote control input driver for the ImgTec Infrared block hardware decoder, which is set up with timings for a specific protocol and supports mask/value filtering and wake events. The hardware decoder timing values, raw data to scan code conversion function and scan code filter to raw data filter conversion function will be provided in separate files for each protocol which this part of the driver can use. The new generic scan code filter interface is made use of to reduce interrupts and control wake events. Signed-off-by: James Hogan Signed-off-by: Mauro Carvalho Chehab --- drivers/media/rc/img-ir/img-ir-hw.c | 1032 +++++++++++++++++++++++++++++++++++ drivers/media/rc/img-ir/img-ir-hw.h | 269 +++++++++ 2 files changed, 1301 insertions(+) create mode 100644 drivers/media/rc/img-ir/img-ir-hw.c create mode 100644 drivers/media/rc/img-ir/img-ir-hw.h diff --git a/drivers/media/rc/img-ir/img-ir-hw.c b/drivers/media/rc/img-ir/img-ir-hw.c new file mode 100644 index 0000000..21c8bbc --- /dev/null +++ b/drivers/media/rc/img-ir/img-ir-hw.c @@ -0,0 +1,1032 @@ +/* + * ImgTec IR Hardware Decoder found in PowerDown Controller. + * + * Copyright 2010-2014 Imagination Technologies Ltd. + * + * This ties into the input subsystem using the RC-core. Protocol support is + * provided in separate modules which provide the parameters and scancode + * translation functions to set up the hardware decoder and interpret the + * resulting input. + */ + +#include +#include +#include +#include +#include +#include +#include "img-ir.h" + +/* Decoders lock (only modified to preprocess them) */ +static DEFINE_SPINLOCK(img_ir_decoders_lock); + +static bool img_ir_decoders_preprocessed; +static struct img_ir_decoder *img_ir_decoders[] = { + NULL +}; + +#define IMG_IR_F_FILTER BIT(RC_FILTER_NORMAL) /* enable filtering */ +#define IMG_IR_F_WAKE BIT(RC_FILTER_WAKEUP) /* enable waking */ + +/* code type quirks */ + +#define IMG_IR_QUIRK_CODE_BROKEN 0x1 /* Decode is broken */ +#define IMG_IR_QUIRK_CODE_LEN_INCR 0x2 /* Bit length needs increment */ + +/* functions for preprocessing timings, ensuring max is set */ + +static void img_ir_timing_preprocess(struct img_ir_timing_range *range, + unsigned int unit) +{ + if (range->max < range->min) + range->max = range->min; + if (unit) { + /* multiply by unit and convert to microseconds */ + range->min = (range->min*unit)/1000; + range->max = (range->max*unit + 999)/1000; /* round up */ + } +} + +static void img_ir_symbol_timing_preprocess(struct img_ir_symbol_timing *timing, + unsigned int unit) +{ + img_ir_timing_preprocess(&timing->pulse, unit); + img_ir_timing_preprocess(&timing->space, unit); +} + +static void img_ir_timings_preprocess(struct img_ir_timings *timings, + unsigned int unit) +{ + img_ir_symbol_timing_preprocess(&timings->ldr, unit); + img_ir_symbol_timing_preprocess(&timings->s00, unit); + img_ir_symbol_timing_preprocess(&timings->s01, unit); + img_ir_symbol_timing_preprocess(&timings->s10, unit); + img_ir_symbol_timing_preprocess(&timings->s11, unit); + /* default s10 and s11 to s00 and s01 if no leader */ + if (unit) + /* multiply by unit and convert to microseconds (round up) */ + timings->ft.ft_min = (timings->ft.ft_min*unit + 999)/1000; +} + +/* functions for filling empty fields with defaults */ + +static void img_ir_timing_defaults(struct img_ir_timing_range *range, + struct img_ir_timing_range *defaults) +{ + if (!range->min) + range->min = defaults->min; + if (!range->max) + range->max = defaults->max; +} + +static void img_ir_symbol_timing_defaults(struct img_ir_symbol_timing *timing, + struct img_ir_symbol_timing *defaults) +{ + img_ir_timing_defaults(&timing->pulse, &defaults->pulse); + img_ir_timing_defaults(&timing->space, &defaults->space); +} + +static void img_ir_timings_defaults(struct img_ir_timings *timings, + struct img_ir_timings *defaults) +{ + img_ir_symbol_timing_defaults(&timings->ldr, &defaults->ldr); + img_ir_symbol_timing_defaults(&timings->s00, &defaults->s00); + img_ir_symbol_timing_defaults(&timings->s01, &defaults->s01); + img_ir_symbol_timing_defaults(&timings->s10, &defaults->s10); + img_ir_symbol_timing_defaults(&timings->s11, &defaults->s11); + if (!timings->ft.ft_min) + timings->ft.ft_min = defaults->ft.ft_min; +} + +/* functions for converting timings to register values */ + +/** + * img_ir_control() - Convert control struct to control register value. + * @control: Control data + * + * Returns: The control register value equivalent of @control. + */ +static u32 img_ir_control(const struct img_ir_control *control) +{ + u32 ctrl = control->code_type << IMG_IR_CODETYPE_SHIFT; + if (control->decoden) + ctrl |= IMG_IR_DECODEN; + if (control->hdrtog) + ctrl |= IMG_IR_HDRTOG; + if (control->ldrdec) + ctrl |= IMG_IR_LDRDEC; + if (control->decodinpol) + ctrl |= IMG_IR_DECODINPOL; + if (control->bitorien) + ctrl |= IMG_IR_BITORIEN; + if (control->d1validsel) + ctrl |= IMG_IR_D1VALIDSEL; + if (control->bitinv) + ctrl |= IMG_IR_BITINV; + if (control->decodend2) + ctrl |= IMG_IR_DECODEND2; + if (control->bitoriend2) + ctrl |= IMG_IR_BITORIEND2; + if (control->bitinvd2) + ctrl |= IMG_IR_BITINVD2; + return ctrl; +} + +/** + * img_ir_timing_range_convert() - Convert microsecond range. + * @out: Output timing range in clock cycles with a shift. + * @in: Input timing range in microseconds. + * @tolerance: Tolerance as a fraction of 128 (roughly percent). + * @clock_hz: IR clock rate in Hz. + * @shift: Shift of output units. + * + * Converts min and max from microseconds to IR clock cycles, applies a + * tolerance, and shifts for the register, rounding in the right direction. + * Note that in and out can safely be the same object. + */ +static void img_ir_timing_range_convert(struct img_ir_timing_range *out, + const struct img_ir_timing_range *in, + unsigned int tolerance, + unsigned long clock_hz, + unsigned int shift) +{ + unsigned int min = in->min; + unsigned int max = in->max; + /* add a tolerance */ + min = min - (min*tolerance >> 7); + max = max + (max*tolerance >> 7); + /* convert from microseconds into clock cycles */ + min = min*clock_hz / 1000000; + max = (max*clock_hz + 999999) / 1000000; /* round up */ + /* apply shift and copy to output */ + out->min = min >> shift; + out->max = (max + ((1 << shift) - 1)) >> shift; /* round up */ +} + +/** + * img_ir_symbol_timing() - Convert symbol timing struct to register value. + * @timing: Symbol timing data + * @tolerance: Timing tolerance where 0-128 represents 0-100% + * @clock_hz: Frequency of source clock in Hz + * @pd_shift: Shift to apply to symbol period + * @w_shift: Shift to apply to symbol width + * + * Returns: Symbol timing register value based on arguments. + */ +static u32 img_ir_symbol_timing(const struct img_ir_symbol_timing *timing, + unsigned int tolerance, + unsigned long clock_hz, + unsigned int pd_shift, + unsigned int w_shift) +{ + struct img_ir_timing_range hw_pulse, hw_period; + /* we calculate period in hw_period, then convert in place */ + hw_period.min = timing->pulse.min + timing->space.min; + hw_period.max = timing->pulse.max + timing->space.max; + img_ir_timing_range_convert(&hw_period, &hw_period, + tolerance, clock_hz, pd_shift); + img_ir_timing_range_convert(&hw_pulse, &timing->pulse, + tolerance, clock_hz, w_shift); + /* construct register value */ + return (hw_period.max << IMG_IR_PD_MAX_SHIFT) | + (hw_period.min << IMG_IR_PD_MIN_SHIFT) | + (hw_pulse.max << IMG_IR_W_MAX_SHIFT) | + (hw_pulse.min << IMG_IR_W_MIN_SHIFT); +} + +/** + * img_ir_free_timing() - Convert free time timing struct to register value. + * @timing: Free symbol timing data + * @clock_hz: Source clock frequency in Hz + * + * Returns: Free symbol timing register value. + */ +static u32 img_ir_free_timing(const struct img_ir_free_timing *timing, + unsigned long clock_hz) +{ + unsigned int minlen, maxlen, ft_min; + /* minlen is only 5 bits, and round minlen to multiple of 2 */ + if (timing->minlen < 30) + minlen = timing->minlen & -2; + else + minlen = 30; + /* maxlen has maximum value of 48, and round maxlen to multiple of 2 */ + if (timing->maxlen < 48) + maxlen = (timing->maxlen + 1) & -2; + else + maxlen = 48; + /* convert and shift ft_min, rounding upwards */ + ft_min = (timing->ft_min*clock_hz + 999999) / 1000000; + ft_min = (ft_min + 7) >> 3; + /* construct register value */ + return (timing->maxlen << IMG_IR_MAXLEN_SHIFT) | + (timing->minlen << IMG_IR_MINLEN_SHIFT) | + (ft_min << IMG_IR_FT_MIN_SHIFT); +} + +/** + * img_ir_free_timing_dynamic() - Update free time register value. + * @st_ft: Static free time register value from img_ir_free_timing. + * @filter: Current filter which may additionally restrict min/max len. + * + * Returns: Updated free time register value based on the current filter. + */ +static u32 img_ir_free_timing_dynamic(u32 st_ft, struct img_ir_filter *filter) +{ + unsigned int minlen, maxlen, newminlen, newmaxlen; + + /* round minlen, maxlen to multiple of 2 */ + newminlen = filter->minlen & -2; + newmaxlen = (filter->maxlen + 1) & -2; + /* extract min/max len from register */ + minlen = (st_ft & IMG_IR_MINLEN) >> IMG_IR_MINLEN_SHIFT; + maxlen = (st_ft & IMG_IR_MAXLEN) >> IMG_IR_MAXLEN_SHIFT; + /* if the new values are more restrictive, update the register value */ + if (newminlen > minlen) { + st_ft &= ~IMG_IR_MINLEN; + st_ft |= newminlen << IMG_IR_MINLEN_SHIFT; + } + if (newmaxlen < maxlen) { + st_ft &= ~IMG_IR_MAXLEN; + st_ft |= newmaxlen << IMG_IR_MAXLEN_SHIFT; + } + return st_ft; +} + +/** + * img_ir_timings_convert() - Convert timings to register values + * @regs: Output timing register values + * @timings: Input timing data + * @tolerance: Timing tolerance where 0-128 represents 0-100% + * @clock_hz: Source clock frequency in Hz + */ +static void img_ir_timings_convert(struct img_ir_timing_regvals *regs, + const struct img_ir_timings *timings, + unsigned int tolerance, + unsigned int clock_hz) +{ + /* leader symbol timings are divided by 16 */ + regs->ldr = img_ir_symbol_timing(&timings->ldr, tolerance, clock_hz, + 4, 4); + /* other symbol timings, pd fields only are divided by 2 */ + regs->s00 = img_ir_symbol_timing(&timings->s00, tolerance, clock_hz, + 1, 0); + regs->s01 = img_ir_symbol_timing(&timings->s01, tolerance, clock_hz, + 1, 0); + regs->s10 = img_ir_symbol_timing(&timings->s10, tolerance, clock_hz, + 1, 0); + regs->s11 = img_ir_symbol_timing(&timings->s11, tolerance, clock_hz, + 1, 0); + regs->ft = img_ir_free_timing(&timings->ft, clock_hz); +} + +/** + * img_ir_decoder_preprocess() - Preprocess timings in decoder. + * @decoder: Decoder to be preprocessed. + * + * Ensures that the symbol timing ranges are valid with respect to ordering, and + * does some fixed conversion on them. + */ +static void img_ir_decoder_preprocess(struct img_ir_decoder *decoder) +{ + /* default tolerance */ + if (!decoder->tolerance) + decoder->tolerance = 10; /* percent */ + /* and convert tolerance to fraction out of 128 */ + decoder->tolerance = decoder->tolerance * 128 / 100; + + /* fill in implicit fields */ + img_ir_timings_preprocess(&decoder->timings, decoder->unit); + + /* do the same for repeat timings if applicable */ + if (decoder->repeat) { + img_ir_timings_preprocess(&decoder->rtimings, decoder->unit); + img_ir_timings_defaults(&decoder->rtimings, &decoder->timings); + } +} + +/** + * img_ir_decoder_convert() - Generate internal timings in decoder. + * @decoder: Decoder to be converted to internal timings. + * @timings: Timing register values. + * @clock_hz: IR clock rate in Hz. + * + * Fills out the repeat timings and timing register values for a specific clock + * rate. + */ +static void img_ir_decoder_convert(const struct img_ir_decoder *decoder, + struct img_ir_reg_timings *reg_timings, + unsigned int clock_hz) +{ + /* calculate control value */ + reg_timings->ctrl = img_ir_control(&decoder->control); + + /* fill in implicit fields and calculate register values */ + img_ir_timings_convert(®_timings->timings, &decoder->timings, + decoder->tolerance, clock_hz); + + /* do the same for repeat timings if applicable */ + if (decoder->repeat) + img_ir_timings_convert(®_timings->rtimings, + &decoder->rtimings, decoder->tolerance, + clock_hz); +} + +/** + * img_ir_write_timings() - Write timings to the hardware now + * @priv: IR private data + * @regs: Timing register values to write + * @type: RC filter type (RC_FILTER_*) + * + * Write timing register values @regs to the hardware, taking into account the + * current filter which may impose restrictions on the length of the expected + * data. + */ +static void img_ir_write_timings(struct img_ir_priv *priv, + struct img_ir_timing_regvals *regs, + enum rc_filter_type type) +{ + struct img_ir_priv_hw *hw = &priv->hw; + + /* filter may be more restrictive to minlen, maxlen */ + u32 ft = regs->ft; + if (hw->flags & BIT(type)) + ft = img_ir_free_timing_dynamic(regs->ft, &hw->filters[type]); + /* write to registers */ + img_ir_write(priv, IMG_IR_LEAD_SYMB_TIMING, regs->ldr); + img_ir_write(priv, IMG_IR_S00_SYMB_TIMING, regs->s00); + img_ir_write(priv, IMG_IR_S01_SYMB_TIMING, regs->s01); + img_ir_write(priv, IMG_IR_S10_SYMB_TIMING, regs->s10); + img_ir_write(priv, IMG_IR_S11_SYMB_TIMING, regs->s11); + img_ir_write(priv, IMG_IR_FREE_SYMB_TIMING, ft); + dev_dbg(priv->dev, "timings: ldr=%#x, s=[%#x, %#x, %#x, %#x], ft=%#x\n", + regs->ldr, regs->s00, regs->s01, regs->s10, regs->s11, ft); +} + +static void img_ir_write_filter(struct img_ir_priv *priv, + struct img_ir_filter *filter) +{ + if (filter) { + dev_dbg(priv->dev, "IR filter=%016llx & %016llx\n", + (unsigned long long)filter->data, + (unsigned long long)filter->mask); + img_ir_write(priv, IMG_IR_IRQ_MSG_DATA_LW, (u32)filter->data); + img_ir_write(priv, IMG_IR_IRQ_MSG_DATA_UP, (u32)(filter->data + >> 32)); + img_ir_write(priv, IMG_IR_IRQ_MSG_MASK_LW, (u32)filter->mask); + img_ir_write(priv, IMG_IR_IRQ_MSG_MASK_UP, (u32)(filter->mask + >> 32)); + } else { + dev_dbg(priv->dev, "IR clearing filter\n"); + img_ir_write(priv, IMG_IR_IRQ_MSG_MASK_LW, 0); + img_ir_write(priv, IMG_IR_IRQ_MSG_MASK_UP, 0); + } +} + +/* caller must have lock */ +static void _img_ir_set_filter(struct img_ir_priv *priv, + struct img_ir_filter *filter) +{ + struct img_ir_priv_hw *hw = &priv->hw; + u32 irq_en, irq_on; + + irq_en = img_ir_read(priv, IMG_IR_IRQ_ENABLE); + if (filter) { + /* Only use the match interrupt */ + hw->filters[RC_FILTER_NORMAL] = *filter; + hw->flags |= IMG_IR_F_FILTER; + irq_on = IMG_IR_IRQ_DATA_MATCH; + irq_en &= ~(IMG_IR_IRQ_DATA_VALID | IMG_IR_IRQ_DATA2_VALID); + } else { + /* Only use the valid interrupt */ + hw->flags &= ~IMG_IR_F_FILTER; + irq_en &= ~IMG_IR_IRQ_DATA_MATCH; + irq_on = IMG_IR_IRQ_DATA_VALID | IMG_IR_IRQ_DATA2_VALID; + } + irq_en |= irq_on; + + img_ir_write_filter(priv, filter); + /* clear any interrupts we're enabling so we don't handle old ones */ + img_ir_write(priv, IMG_IR_IRQ_CLEAR, irq_on); + img_ir_write(priv, IMG_IR_IRQ_ENABLE, irq_en); +} + +/* caller must have lock */ +static void _img_ir_set_wake_filter(struct img_ir_priv *priv, + struct img_ir_filter *filter) +{ + struct img_ir_priv_hw *hw = &priv->hw; + if (filter) { + /* Enable wake, and copy filter for later */ + hw->filters[RC_FILTER_WAKEUP] = *filter; + hw->flags |= IMG_IR_F_WAKE; + } else { + /* Disable wake */ + hw->flags &= ~IMG_IR_F_WAKE; + } +} + +/* Callback for setting scancode filter */ +static int img_ir_set_filter(struct rc_dev *dev, enum rc_filter_type type, + struct rc_scancode_filter *sc_filter) +{ + struct img_ir_priv *priv = dev->priv; + struct img_ir_priv_hw *hw = &priv->hw; + struct img_ir_filter filter, *filter_ptr = &filter; + int ret = 0; + + dev_dbg(priv->dev, "IR scancode %sfilter=%08x & %08x\n", + type == RC_FILTER_WAKEUP ? "wake " : "", + sc_filter->data, + sc_filter->mask); + + spin_lock_irq(&priv->lock); + + /* filtering can always be disabled */ + if (!sc_filter->mask) { + filter_ptr = NULL; + goto set_unlock; + } + + /* current decoder must support scancode filtering */ + if (!hw->decoder || !hw->decoder->filter) { + ret = -EINVAL; + goto unlock; + } + + /* convert scancode filter to raw filter */ + filter.minlen = 0; + filter.maxlen = ~0; + ret = hw->decoder->filter(sc_filter, &filter, hw->enabled_protocols); + if (ret) + goto unlock; + dev_dbg(priv->dev, "IR raw %sfilter=%016llx & %016llx\n", + type == RC_FILTER_WAKEUP ? "wake " : "", + (unsigned long long)filter.data, + (unsigned long long)filter.mask); + +set_unlock: + /* apply raw filters */ + switch (type) { + case RC_FILTER_NORMAL: + _img_ir_set_filter(priv, filter_ptr); + break; + case RC_FILTER_WAKEUP: + _img_ir_set_wake_filter(priv, filter_ptr); + break; + default: + ret = -EINVAL; + }; + +unlock: + spin_unlock_irq(&priv->lock); + return ret; +} + +/** + * img_ir_set_decoder() - Set the current decoder. + * @priv: IR private data. + * @decoder: Decoder to use with immediate effect. + * @proto: Protocol bitmap (or 0 to use decoder->type). + */ +static void img_ir_set_decoder(struct img_ir_priv *priv, + const struct img_ir_decoder *decoder, + u64 proto) +{ + struct img_ir_priv_hw *hw = &priv->hw; + struct rc_dev *rdev = hw->rdev; + u32 ir_status, irq_en; + spin_lock_irq(&priv->lock); + + /* switch off and disable interrupts */ + img_ir_write(priv, IMG_IR_CONTROL, 0); + irq_en = img_ir_read(priv, IMG_IR_IRQ_ENABLE); + img_ir_write(priv, IMG_IR_IRQ_ENABLE, irq_en & IMG_IR_IRQ_EDGE); + img_ir_write(priv, IMG_IR_IRQ_CLEAR, IMG_IR_IRQ_ALL & ~IMG_IR_IRQ_EDGE); + + /* ack any data already detected */ + ir_status = img_ir_read(priv, IMG_IR_STATUS); + if (ir_status & (IMG_IR_RXDVAL | IMG_IR_RXDVALD2)) { + ir_status &= ~(IMG_IR_RXDVAL | IMG_IR_RXDVALD2); + img_ir_write(priv, IMG_IR_STATUS, ir_status); + img_ir_read(priv, IMG_IR_DATA_LW); + img_ir_read(priv, IMG_IR_DATA_UP); + } + + /* stop the end timer and switch back to normal mode */ + del_timer_sync(&hw->end_timer); + hw->mode = IMG_IR_M_NORMAL; + + /* clear the wakeup scancode filter */ + rdev->scancode_filters[RC_FILTER_WAKEUP].data = 0; + rdev->scancode_filters[RC_FILTER_WAKEUP].mask = 0; + + /* clear raw filters */ + _img_ir_set_filter(priv, NULL); + _img_ir_set_wake_filter(priv, NULL); + + /* clear the enabled protocols */ + hw->enabled_protocols = 0; + + /* switch decoder */ + hw->decoder = decoder; + if (!decoder) + goto unlock; + + /* set the enabled protocols */ + if (!proto) + proto = decoder->type; + hw->enabled_protocols = proto; + + /* write the new timings */ + img_ir_decoder_convert(decoder, &hw->reg_timings, hw->clk_hz); + img_ir_write_timings(priv, &hw->reg_timings.timings, RC_FILTER_NORMAL); + + /* set up and enable */ + img_ir_write(priv, IMG_IR_CONTROL, hw->reg_timings.ctrl); + + +unlock: + spin_unlock_irq(&priv->lock); +} + +/** + * img_ir_decoder_compatable() - Find whether a decoder will work with a device. + * @priv: IR private data. + * @dec: Decoder to check. + * + * Returns: true if @dec is compatible with the device @priv refers to. + */ +static bool img_ir_decoder_compatible(struct img_ir_priv *priv, + const struct img_ir_decoder *dec) +{ + unsigned int ct; + + /* don't accept decoders using code types which aren't supported */ + ct = dec->control.code_type; + if (priv->hw.ct_quirks[ct] & IMG_IR_QUIRK_CODE_BROKEN) + return false; + + return true; +} + +/** + * img_ir_allowed_protos() - Get allowed protocols from global decoder list. + * @priv: IR private data. + * + * Returns: Mask of protocols supported by the device @priv refers to. + */ +static u64 img_ir_allowed_protos(struct img_ir_priv *priv) +{ + u64 protos = 0; + struct img_ir_decoder **decp; + + for (decp = img_ir_decoders; *decp; ++decp) { + const struct img_ir_decoder *dec = *decp; + if (img_ir_decoder_compatible(priv, dec)) + protos |= dec->type; + } + return protos; +} + +/* Callback for changing protocol using sysfs */ +static int img_ir_change_protocol(struct rc_dev *dev, u64 *ir_type) +{ + struct img_ir_priv *priv = dev->priv; + struct img_ir_priv_hw *hw = &priv->hw; + struct rc_dev *rdev = hw->rdev; + struct img_ir_decoder **decp; + u64 wakeup_protocols; + + if (!*ir_type) { + /* disable all protocols */ + img_ir_set_decoder(priv, NULL, 0); + goto success; + } + for (decp = img_ir_decoders; *decp; ++decp) { + const struct img_ir_decoder *dec = *decp; + if (!img_ir_decoder_compatible(priv, dec)) + continue; + if (*ir_type & dec->type) { + *ir_type &= dec->type; + img_ir_set_decoder(priv, dec, *ir_type); + goto success; + } + } + return -EINVAL; + +success: + /* + * Only allow matching wakeup protocols for now, and only if filtering + * is supported. + */ + wakeup_protocols = *ir_type; + if (!hw->decoder || !hw->decoder->filter) + wakeup_protocols = 0; + rc_set_allowed_wakeup_protocols(rdev, wakeup_protocols); + rc_set_enabled_wakeup_protocols(rdev, wakeup_protocols); + return 0; +} + +/* Changes ir-core protocol device attribute */ +static void img_ir_set_protocol(struct img_ir_priv *priv, u64 proto) +{ + struct rc_dev *rdev = priv->hw.rdev; + + spin_lock_irq(&rdev->rc_map.lock); + rdev->rc_map.rc_type = __ffs64(proto); + spin_unlock_irq(&rdev->rc_map.lock); + + mutex_lock(&rdev->lock); + rc_set_enabled_protocols(rdev, proto); + rc_set_allowed_wakeup_protocols(rdev, proto); + rc_set_enabled_wakeup_protocols(rdev, proto); + mutex_unlock(&rdev->lock); +} + +/* Set up IR decoders */ +static void img_ir_init_decoders(void) +{ + struct img_ir_decoder **decp; + + spin_lock(&img_ir_decoders_lock); + if (!img_ir_decoders_preprocessed) { + for (decp = img_ir_decoders; *decp; ++decp) + img_ir_decoder_preprocess(*decp); + img_ir_decoders_preprocessed = true; + } + spin_unlock(&img_ir_decoders_lock); +} + +#ifdef CONFIG_PM_SLEEP +/** + * img_ir_enable_wake() - Switch to wake mode. + * @priv: IR private data. + * + * Returns: non-zero if the IR can wake the system. + */ +static int img_ir_enable_wake(struct img_ir_priv *priv) +{ + struct img_ir_priv_hw *hw = &priv->hw; + int ret = 0; + + spin_lock_irq(&priv->lock); + if (hw->flags & IMG_IR_F_WAKE) { + /* interrupt only on a match */ + hw->suspend_irqen = img_ir_read(priv, IMG_IR_IRQ_ENABLE); + img_ir_write(priv, IMG_IR_IRQ_ENABLE, IMG_IR_IRQ_DATA_MATCH); + img_ir_write_filter(priv, &hw->filters[RC_FILTER_WAKEUP]); + img_ir_write_timings(priv, &hw->reg_timings.timings, + RC_FILTER_WAKEUP); + hw->mode = IMG_IR_M_WAKE; + ret = 1; + } + spin_unlock_irq(&priv->lock); + return ret; +} + +/** + * img_ir_disable_wake() - Switch out of wake mode. + * @priv: IR private data + * + * Returns: 1 if the hardware should be allowed to wake from a sleep state. + * 0 otherwise. + */ +static int img_ir_disable_wake(struct img_ir_priv *priv) +{ + struct img_ir_priv_hw *hw = &priv->hw; + int ret = 0; + + spin_lock_irq(&priv->lock); + if (hw->flags & IMG_IR_F_WAKE) { + /* restore normal filtering */ + if (hw->flags & IMG_IR_F_FILTER) { + img_ir_write(priv, IMG_IR_IRQ_ENABLE, + (hw->suspend_irqen & IMG_IR_IRQ_EDGE) | + IMG_IR_IRQ_DATA_MATCH); + img_ir_write_filter(priv, + &hw->filters[RC_FILTER_NORMAL]); + } else { + img_ir_write(priv, IMG_IR_IRQ_ENABLE, + (hw->suspend_irqen & IMG_IR_IRQ_EDGE) | + IMG_IR_IRQ_DATA_VALID | + IMG_IR_IRQ_DATA2_VALID); + img_ir_write_filter(priv, NULL); + } + img_ir_write_timings(priv, &hw->reg_timings.timings, + RC_FILTER_NORMAL); + hw->mode = IMG_IR_M_NORMAL; + ret = 1; + } + spin_unlock_irq(&priv->lock); + return ret; +} +#endif /* CONFIG_PM_SLEEP */ + +/* lock must be held */ +static void img_ir_begin_repeat(struct img_ir_priv *priv) +{ + struct img_ir_priv_hw *hw = &priv->hw; + if (hw->mode == IMG_IR_M_NORMAL) { + /* switch to repeat timings */ + img_ir_write(priv, IMG_IR_CONTROL, 0); + hw->mode = IMG_IR_M_REPEATING; + img_ir_write_timings(priv, &hw->reg_timings.rtimings, + RC_FILTER_NORMAL); + img_ir_write(priv, IMG_IR_CONTROL, hw->reg_timings.ctrl); + } +} + +/* lock must be held */ +static void img_ir_end_repeat(struct img_ir_priv *priv) +{ + struct img_ir_priv_hw *hw = &priv->hw; + if (hw->mode == IMG_IR_M_REPEATING) { + /* switch to normal timings */ + img_ir_write(priv, IMG_IR_CONTROL, 0); + hw->mode = IMG_IR_M_NORMAL; + img_ir_write_timings(priv, &hw->reg_timings.timings, + RC_FILTER_NORMAL); + img_ir_write(priv, IMG_IR_CONTROL, hw->reg_timings.ctrl); + } +} + +/* lock must be held */ +static void img_ir_handle_data(struct img_ir_priv *priv, u32 len, u64 raw) +{ + struct img_ir_priv_hw *hw = &priv->hw; + const struct img_ir_decoder *dec = hw->decoder; + int ret = IMG_IR_SCANCODE; + int scancode; + if (dec->scancode) + ret = dec->scancode(len, raw, &scancode, hw->enabled_protocols); + else if (len >= 32) + scancode = (u32)raw; + else if (len < 32) + scancode = (u32)raw & ((1 << len)-1); + dev_dbg(priv->dev, "data (%u bits) = %#llx\n", + len, (unsigned long long)raw); + if (ret == IMG_IR_SCANCODE) { + dev_dbg(priv->dev, "decoded scan code %#x\n", scancode); + rc_keydown(hw->rdev, scancode, 0); + img_ir_end_repeat(priv); + } else if (ret == IMG_IR_REPEATCODE) { + if (hw->mode == IMG_IR_M_REPEATING) { + dev_dbg(priv->dev, "decoded repeat code\n"); + rc_repeat(hw->rdev); + } else { + dev_dbg(priv->dev, "decoded unexpected repeat code, ignoring\n"); + } + } else { + dev_dbg(priv->dev, "decode failed (%d)\n", ret); + return; + } + + + if (dec->repeat) { + unsigned long interval; + + img_ir_begin_repeat(priv); + + /* update timer, but allowing for 1/8th tolerance */ + interval = dec->repeat + (dec->repeat >> 3); + mod_timer(&hw->end_timer, + jiffies + msecs_to_jiffies(interval)); + } +} + +/* timer function to end waiting for repeat. */ +static void img_ir_end_timer(unsigned long arg) +{ + struct img_ir_priv *priv = (struct img_ir_priv *)arg; + + spin_lock_irq(&priv->lock); + img_ir_end_repeat(priv); + spin_unlock_irq(&priv->lock); +} + +#ifdef CONFIG_COMMON_CLK +static void img_ir_change_frequency(struct img_ir_priv *priv, + struct clk_notifier_data *change) +{ + struct img_ir_priv_hw *hw = &priv->hw; + + dev_dbg(priv->dev, "clk changed %lu HZ -> %lu HZ\n", + change->old_rate, change->new_rate); + + spin_lock_irq(&priv->lock); + if (hw->clk_hz == change->new_rate) + goto unlock; + hw->clk_hz = change->new_rate; + /* refresh current timings */ + if (hw->decoder) { + img_ir_decoder_convert(hw->decoder, &hw->reg_timings, + hw->clk_hz); + switch (hw->mode) { + case IMG_IR_M_NORMAL: + img_ir_write_timings(priv, &hw->reg_timings.timings, + RC_FILTER_NORMAL); + break; + case IMG_IR_M_REPEATING: + img_ir_write_timings(priv, &hw->reg_timings.rtimings, + RC_FILTER_NORMAL); + break; +#ifdef CONFIG_PM_SLEEP + case IMG_IR_M_WAKE: + img_ir_write_timings(priv, &hw->reg_timings.timings, + RC_FILTER_WAKEUP); + break; +#endif + } + } +unlock: + spin_unlock_irq(&priv->lock); +} + +static int img_ir_clk_notify(struct notifier_block *self, unsigned long action, + void *data) +{ + struct img_ir_priv *priv = container_of(self, struct img_ir_priv, + hw.clk_nb); + switch (action) { + case POST_RATE_CHANGE: + img_ir_change_frequency(priv, data); + break; + default: + break; + } + return NOTIFY_OK; +} +#endif /* CONFIG_COMMON_CLK */ + +/* called with priv->lock held */ +void img_ir_isr_hw(struct img_ir_priv *priv, u32 irq_status) +{ + struct img_ir_priv_hw *hw = &priv->hw; + u32 ir_status, len, lw, up; + unsigned int ct; + + /* use the current decoder */ + if (!hw->decoder) + return; + + ir_status = img_ir_read(priv, IMG_IR_STATUS); + if (!(ir_status & (IMG_IR_RXDVAL | IMG_IR_RXDVALD2))) + return; + ir_status &= ~(IMG_IR_RXDVAL | IMG_IR_RXDVALD2); + img_ir_write(priv, IMG_IR_STATUS, ir_status); + + len = (ir_status & IMG_IR_RXDLEN) >> IMG_IR_RXDLEN_SHIFT; + /* some versions report wrong length for certain code types */ + ct = hw->decoder->control.code_type; + if (hw->ct_quirks[ct] & IMG_IR_QUIRK_CODE_LEN_INCR) + ++len; + + lw = img_ir_read(priv, IMG_IR_DATA_LW); + up = img_ir_read(priv, IMG_IR_DATA_UP); + img_ir_handle_data(priv, len, (u64)up << 32 | lw); +} + +void img_ir_setup_hw(struct img_ir_priv *priv) +{ + struct img_ir_decoder **decp; + + if (!priv->hw.rdev) + return; + + /* Use the first available decoder (or disable stuff if NULL) */ + for (decp = img_ir_decoders; *decp; ++decp) { + const struct img_ir_decoder *dec = *decp; + if (img_ir_decoder_compatible(priv, dec)) { + img_ir_set_protocol(priv, dec->type); + img_ir_set_decoder(priv, dec, 0); + return; + } + } + img_ir_set_decoder(priv, NULL, 0); +} + +/** + * img_ir_probe_hw_caps() - Probe capabilities of the hardware. + * @priv: IR private data. + */ +static void img_ir_probe_hw_caps(struct img_ir_priv *priv) +{ + struct img_ir_priv_hw *hw = &priv->hw; + /* + * When a version of the block becomes available without these quirks, + * they'll have to depend on the core revision. + */ + hw->ct_quirks[IMG_IR_CODETYPE_PULSELEN] + |= IMG_IR_QUIRK_CODE_LEN_INCR; + hw->ct_quirks[IMG_IR_CODETYPE_BIPHASE] + |= IMG_IR_QUIRK_CODE_BROKEN; + hw->ct_quirks[IMG_IR_CODETYPE_2BITPULSEPOS] + |= IMG_IR_QUIRK_CODE_BROKEN; +} + +int img_ir_probe_hw(struct img_ir_priv *priv) +{ + struct img_ir_priv_hw *hw = &priv->hw; + struct rc_dev *rdev; + int error; + + /* Ensure hardware decoders have been preprocessed */ + img_ir_init_decoders(); + + /* Probe hardware capabilities */ + img_ir_probe_hw_caps(priv); + + /* Set up the end timer */ + setup_timer(&hw->end_timer, img_ir_end_timer, (unsigned long)priv); + + /* Register a clock notifier */ + if (!IS_ERR(priv->clk)) { + hw->clk_hz = clk_get_rate(priv->clk); +#ifdef CONFIG_COMMON_CLK + hw->clk_nb.notifier_call = img_ir_clk_notify; + error = clk_notifier_register(priv->clk, &hw->clk_nb); + if (error) + dev_warn(priv->dev, + "failed to register clock notifier\n"); +#endif + } else { + hw->clk_hz = 32768; + } + + /* Allocate hardware decoder */ + hw->rdev = rdev = rc_allocate_device(); + if (!rdev) { + dev_err(priv->dev, "cannot allocate input device\n"); + error = -ENOMEM; + goto err_alloc_rc; + } + rdev->priv = priv; + rdev->map_name = RC_MAP_EMPTY; + rc_set_allowed_protocols(rdev, img_ir_allowed_protos(priv)); + rdev->input_name = "IMG Infrared Decoder"; + rdev->s_filter = img_ir_set_filter; + + /* Register hardware decoder */ + error = rc_register_device(rdev); + if (error) { + dev_err(priv->dev, "failed to register IR input device\n"); + goto err_register_rc; + } + + /* + * Set this after rc_register_device as no protocols have been + * registered yet. + */ + rdev->change_protocol = img_ir_change_protocol; + + device_init_wakeup(priv->dev, 1); + + return 0; + +err_register_rc: + img_ir_set_decoder(priv, NULL, 0); + hw->rdev = NULL; + rc_free_device(rdev); +err_alloc_rc: +#ifdef CONFIG_COMMON_CLK + if (!IS_ERR(priv->clk)) + clk_notifier_unregister(priv->clk, &hw->clk_nb); +#endif + return error; +} + +void img_ir_remove_hw(struct img_ir_priv *priv) +{ + struct img_ir_priv_hw *hw = &priv->hw; + struct rc_dev *rdev = hw->rdev; + if (!rdev) + return; + img_ir_set_decoder(priv, NULL, 0); + hw->rdev = NULL; + rc_unregister_device(rdev); +#ifdef CONFIG_COMMON_CLK + if (!IS_ERR(priv->clk)) + clk_notifier_unregister(priv->clk, &hw->clk_nb); +#endif +} + +#ifdef CONFIG_PM_SLEEP +int img_ir_suspend(struct device *dev) +{ + struct img_ir_priv *priv = dev_get_drvdata(dev); + + if (device_may_wakeup(dev) && img_ir_enable_wake(priv)) + enable_irq_wake(priv->irq); + return 0; +} + +int img_ir_resume(struct device *dev) +{ + struct img_ir_priv *priv = dev_get_drvdata(dev); + + if (device_may_wakeup(dev) && img_ir_disable_wake(priv)) + disable_irq_wake(priv->irq); + return 0; +} +#endif /* CONFIG_PM_SLEEP */ diff --git a/drivers/media/rc/img-ir/img-ir-hw.h b/drivers/media/rc/img-ir/img-ir-hw.h new file mode 100644 index 0000000..6c9a94a --- /dev/null +++ b/drivers/media/rc/img-ir/img-ir-hw.h @@ -0,0 +1,269 @@ +/* + * ImgTec IR Hardware Decoder found in PowerDown Controller. + * + * Copyright 2010-2014 Imagination Technologies Ltd. + */ + +#ifndef _IMG_IR_HW_H_ +#define _IMG_IR_HW_H_ + +#include +#include + +/* constants */ + +#define IMG_IR_CODETYPE_PULSELEN 0x0 /* Sony */ +#define IMG_IR_CODETYPE_PULSEDIST 0x1 /* NEC, Toshiba, Micom, Sharp */ +#define IMG_IR_CODETYPE_BIPHASE 0x2 /* RC-5/6 */ +#define IMG_IR_CODETYPE_2BITPULSEPOS 0x3 /* RC-MM */ + + +/* Timing information */ + +/** + * struct img_ir_control - Decoder control settings + * @decoden: Primary decoder enable + * @code_type: Decode type (see IMG_IR_CODETYPE_*) + * @hdrtog: Detect header toggle symbol after leader symbol + * @ldrdec: Don't discard leader if maximum width reached + * @decodinpol: Decoder input polarity (1=active high) + * @bitorien: Bit orientation (1=MSB first) + * @d1validsel: Decoder 2 takes over if it detects valid data + * @bitinv: Bit inversion switch (1=don't invert) + * @decodend2: Secondary decoder enable (no leader symbol) + * @bitoriend2: Bit orientation (1=MSB first) + * @bitinvd2: Secondary decoder bit inversion switch (1=don't invert) + */ +struct img_ir_control { + unsigned decoden:1; + unsigned code_type:2; + unsigned hdrtog:1; + unsigned ldrdec:1; + unsigned decodinpol:1; + unsigned bitorien:1; + unsigned d1validsel:1; + unsigned bitinv:1; + unsigned decodend2:1; + unsigned bitoriend2:1; + unsigned bitinvd2:1; +}; + +/** + * struct img_ir_timing_range - range of timing values + * @min: Minimum timing value + * @max: Maximum timing value (if < @min, this will be set to @min during + * preprocessing step, so it is normally not explicitly initialised + * and is taken care of by the tolerance) + */ +struct img_ir_timing_range { + u16 min; + u16 max; +}; + +/** + * struct img_ir_symbol_timing - timing data for a symbol + * @pulse: Timing range for the length of the pulse in this symbol + * @space: Timing range for the length of the space in this symbol + */ +struct img_ir_symbol_timing { + struct img_ir_timing_range pulse; + struct img_ir_timing_range space; +}; + +/** + * struct img_ir_free_timing - timing data for free time symbol + * @minlen: Minimum number of bits of data + * @maxlen: Maximum number of bits of data + * @ft_min: Minimum free time after message + */ +struct img_ir_free_timing { + /* measured in bits */ + u8 minlen; + u8 maxlen; + u16 ft_min; +}; + +/** + * struct img_ir_timings - Timing values. + * @ldr: Leader symbol timing data + * @s00: Zero symbol timing data for primary decoder + * @s01: One symbol timing data for primary decoder + * @s10: Zero symbol timing data for secondary (no leader symbol) decoder + * @s11: One symbol timing data for secondary (no leader symbol) decoder + * @ft: Free time symbol timing data + */ +struct img_ir_timings { + struct img_ir_symbol_timing ldr, s00, s01, s10, s11; + struct img_ir_free_timing ft; +}; + +/** + * struct img_ir_filter - Filter IR events. + * @data: Data to match. + * @mask: Mask of bits to compare. + * @minlen: Additional minimum number of bits. + * @maxlen: Additional maximum number of bits. + */ +struct img_ir_filter { + u64 data; + u64 mask; + u8 minlen; + u8 maxlen; +}; + +/** + * struct img_ir_timing_regvals - Calculated timing register values. + * @ldr: Leader symbol timing register value + * @s00: Zero symbol timing register value for primary decoder + * @s01: One symbol timing register value for primary decoder + * @s10: Zero symbol timing register value for secondary decoder + * @s11: One symbol timing register value for secondary decoder + * @ft: Free time symbol timing register value + */ +struct img_ir_timing_regvals { + u32 ldr, s00, s01, s10, s11, ft; +}; + +#define IMG_IR_SCANCODE 0 /* new scancode */ +#define IMG_IR_REPEATCODE 1 /* repeat the previous code */ + +/** + * struct img_ir_decoder - Decoder settings for an IR protocol. + * @type: Protocol types bitmap. + * @tolerance: Timing tolerance as a percentage (default 10%). + * @unit: Unit of timings in nanoseconds (default 1 us). + * @timings: Primary timings + * @rtimings: Additional override timings while waiting for repeats. + * @repeat: Maximum repeat interval (always in milliseconds). + * @control: Control flags. + * + * @scancode: Pointer to function to convert the IR data into a scancode (it + * must be safe to execute in interrupt context). + * Returns IMG_IR_SCANCODE to emit new scancode. + * Returns IMG_IR_REPEATCODE to repeat previous code. + * Returns -errno (e.g. -EINVAL) on error. + * @filter: Pointer to function to convert scancode filter to raw hardware + * filter. The minlen and maxlen fields will have been initialised + * to the maximum range. + */ +struct img_ir_decoder { + /* core description */ + u64 type; + unsigned int tolerance; + unsigned int unit; + struct img_ir_timings timings; + struct img_ir_timings rtimings; + unsigned int repeat; + struct img_ir_control control; + + /* scancode logic */ + int (*scancode)(int len, u64 raw, int *scancode, u64 protocols); + int (*filter)(const struct rc_scancode_filter *in, + struct img_ir_filter *out, u64 protocols); +}; + +/** + * struct img_ir_reg_timings - Reg values for decoder timings at clock rate. + * @ctrl: Processed control register value. + * @timings: Processed primary timings. + * @rtimings: Processed repeat timings. + */ +struct img_ir_reg_timings { + u32 ctrl; + struct img_ir_timing_regvals timings; + struct img_ir_timing_regvals rtimings; +}; + +int img_ir_register_decoder(struct img_ir_decoder *dec); +void img_ir_unregister_decoder(struct img_ir_decoder *dec); + +struct img_ir_priv; + +#ifdef CONFIG_IR_IMG_HW + +enum img_ir_mode { + IMG_IR_M_NORMAL, + IMG_IR_M_REPEATING, +#ifdef CONFIG_PM_SLEEP + IMG_IR_M_WAKE, +#endif +}; + +/** + * struct img_ir_priv_hw - Private driver data for hardware decoder. + * @ct_quirks: Quirk bits for each code type. + * @rdev: Remote control device + * @clk_nb: Notifier block for clock notify events. + * @end_timer: Timer until repeat timeout. + * @decoder: Current decoder settings. + * @enabled_protocols: Currently enabled protocols. + * @clk_hz: Current core clock rate in Hz. + * @reg_timings: Timing reg values for decoder at clock rate. + * @flags: IMG_IR_F_*. + * @filters: HW filters (derived from scancode filters). + * @mode: Current decode mode. + * @suspend_irqen: Saved IRQ enable mask over suspend. + */ +struct img_ir_priv_hw { + unsigned int ct_quirks[4]; + struct rc_dev *rdev; + struct notifier_block clk_nb; + struct timer_list end_timer; + const struct img_ir_decoder *decoder; + u64 enabled_protocols; + unsigned long clk_hz; + struct img_ir_reg_timings reg_timings; + unsigned int flags; + struct img_ir_filter filters[RC_FILTER_MAX]; + + enum img_ir_mode mode; + u32 suspend_irqen; +}; + +static inline bool img_ir_hw_enabled(struct img_ir_priv_hw *hw) +{ + return hw->rdev; +}; + +void img_ir_isr_hw(struct img_ir_priv *priv, u32 irq_status); +void img_ir_setup_hw(struct img_ir_priv *priv); +int img_ir_probe_hw(struct img_ir_priv *priv); +void img_ir_remove_hw(struct img_ir_priv *priv); + +#ifdef CONFIG_PM_SLEEP +int img_ir_suspend(struct device *dev); +int img_ir_resume(struct device *dev); +#else +#define img_ir_suspend NULL +#define img_ir_resume NULL +#endif + +#else + +struct img_ir_priv_hw { +}; + +static inline bool img_ir_hw_enabled(struct img_ir_priv_hw *hw) +{ + return false; +}; +static inline void img_ir_isr_hw(struct img_ir_priv *priv, u32 irq_status) +{ +} +static inline void img_ir_setup_hw(struct img_ir_priv *priv) +{ +} +static inline int img_ir_probe_hw(struct img_ir_priv *priv) +{ + return -ENODEV; +} +static inline void img_ir_remove_hw(struct img_ir_priv *priv) +{ +} + +#define img_ir_suspend NULL +#define img_ir_resume NULL + +#endif /* CONFIG_IR_IMG_HW */ + +#endif /* _IMG_IR_HW_H_ */ -- cgit v1.1 From 54b2912040d15725004a598cf600f501ab6405f4 Mon Sep 17 00:00:00 2001 From: James Hogan Date: Fri, 28 Feb 2014 20:28:55 -0300 Subject: [media] rc: img-ir: add to build Add ImgTec IR decoder driver to the build system. Signed-off-by: James Hogan Signed-off-by: Mauro Carvalho Chehab --- drivers/media/rc/Kconfig | 2 ++ drivers/media/rc/Makefile | 1 + drivers/media/rc/img-ir/Kconfig | 26 ++++++++++++++++++++++++++ drivers/media/rc/img-ir/Makefile | 6 ++++++ 4 files changed, 35 insertions(+) create mode 100644 drivers/media/rc/img-ir/Kconfig create mode 100644 drivers/media/rc/img-ir/Makefile diff --git a/drivers/media/rc/Kconfig b/drivers/media/rc/Kconfig index 3b25887..8fbd377 100644 --- a/drivers/media/rc/Kconfig +++ b/drivers/media/rc/Kconfig @@ -309,6 +309,8 @@ config IR_RX51 The driver uses omap DM timers for generating the carrier wave and pulses. +source "drivers/media/rc/img-ir/Kconfig" + config RC_LOOPBACK tristate "Remote Control Loopback Driver" depends on RC_CORE diff --git a/drivers/media/rc/Makefile b/drivers/media/rc/Makefile index 36dafed..f8b54ff 100644 --- a/drivers/media/rc/Makefile +++ b/drivers/media/rc/Makefile @@ -32,3 +32,4 @@ obj-$(CONFIG_IR_GPIO_CIR) += gpio-ir-recv.o obj-$(CONFIG_IR_IGUANA) += iguanair.o obj-$(CONFIG_IR_TTUSBIR) += ttusbir.o obj-$(CONFIG_RC_ST) += st_rc.o +obj-$(CONFIG_IR_IMG) += img-ir/ diff --git a/drivers/media/rc/img-ir/Kconfig b/drivers/media/rc/img-ir/Kconfig new file mode 100644 index 0000000..60eaba6 --- /dev/null +++ b/drivers/media/rc/img-ir/Kconfig @@ -0,0 +1,26 @@ +config IR_IMG + tristate "ImgTec IR Decoder" + depends on RC_CORE + select IR_IMG_HW if !IR_IMG_RAW + help + Say Y or M here if you want to use the ImgTec infrared decoder + functionality found in SoCs such as TZ1090. + +config IR_IMG_RAW + bool "Raw decoder" + depends on IR_IMG + help + Say Y here to enable the raw mode driver which passes raw IR signal + changes to the IR raw decoders for software decoding. This is much + less reliable (due to lack of timestamps) and consumes more + processing power than using hardware decode, but can be useful for + testing, debug, and to make more protocols available. + +config IR_IMG_HW + bool "Hardware decoder" + depends on IR_IMG + help + Say Y here to enable the hardware decode driver which decodes the IR + signals in hardware. This is more reliable, consumes less processing + power since only a single interrupt is received for each scancode, + and allows an IR scancode to be used as a wake event. diff --git a/drivers/media/rc/img-ir/Makefile b/drivers/media/rc/img-ir/Makefile new file mode 100644 index 0000000..4ef86ed --- /dev/null +++ b/drivers/media/rc/img-ir/Makefile @@ -0,0 +1,6 @@ +img-ir-y := img-ir-core.o +img-ir-$(CONFIG_IR_IMG_RAW) += img-ir-raw.o +img-ir-$(CONFIG_IR_IMG_HW) += img-ir-hw.o +img-ir-objs := $(img-ir-y) + +obj-$(CONFIG_IR_IMG) += img-ir.o -- cgit v1.1 From 635abb7054f204e036bc6afe41b1f50825294867 Mon Sep 17 00:00:00 2001 From: James Hogan Date: Fri, 28 Feb 2014 20:28:56 -0300 Subject: [media] rc: img-ir: add NEC decoder module Add an img-ir module for decoding the NEC and extended NEC infrared protocols. Signed-off-by: James Hogan Signed-off-by: Mauro Carvalho Chehab --- drivers/media/rc/img-ir/Kconfig | 7 ++ drivers/media/rc/img-ir/Makefile | 1 + drivers/media/rc/img-ir/img-ir-hw.c | 5 ++ drivers/media/rc/img-ir/img-ir-nec.c | 148 +++++++++++++++++++++++++++++++++++ 4 files changed, 161 insertions(+) create mode 100644 drivers/media/rc/img-ir/img-ir-nec.c diff --git a/drivers/media/rc/img-ir/Kconfig b/drivers/media/rc/img-ir/Kconfig index 60eaba6..28498a2 100644 --- a/drivers/media/rc/img-ir/Kconfig +++ b/drivers/media/rc/img-ir/Kconfig @@ -24,3 +24,10 @@ config IR_IMG_HW signals in hardware. This is more reliable, consumes less processing power since only a single interrupt is received for each scancode, and allows an IR scancode to be used as a wake event. + +config IR_IMG_NEC + bool "NEC protocol support" + depends on IR_IMG_HW + help + Say Y here to enable support for the NEC, extended NEC, and 32-bit + NEC protocols in the ImgTec infrared decoder block. diff --git a/drivers/media/rc/img-ir/Makefile b/drivers/media/rc/img-ir/Makefile index 4ef86ed..c409197 100644 --- a/drivers/media/rc/img-ir/Makefile +++ b/drivers/media/rc/img-ir/Makefile @@ -1,6 +1,7 @@ img-ir-y := img-ir-core.o img-ir-$(CONFIG_IR_IMG_RAW) += img-ir-raw.o img-ir-$(CONFIG_IR_IMG_HW) += img-ir-hw.o +img-ir-$(CONFIG_IR_IMG_NEC) += img-ir-nec.o img-ir-objs := $(img-ir-y) obj-$(CONFIG_IR_IMG) += img-ir.o diff --git a/drivers/media/rc/img-ir/img-ir-hw.c b/drivers/media/rc/img-ir/img-ir-hw.c index 21c8bbc..139f2c7 100644 --- a/drivers/media/rc/img-ir/img-ir-hw.c +++ b/drivers/media/rc/img-ir/img-ir-hw.c @@ -20,8 +20,13 @@ /* Decoders lock (only modified to preprocess them) */ static DEFINE_SPINLOCK(img_ir_decoders_lock); +extern struct img_ir_decoder img_ir_nec; + static bool img_ir_decoders_preprocessed; static struct img_ir_decoder *img_ir_decoders[] = { +#ifdef CONFIG_IR_IMG_NEC + &img_ir_nec, +#endif NULL }; diff --git a/drivers/media/rc/img-ir/img-ir-nec.c b/drivers/media/rc/img-ir/img-ir-nec.c new file mode 100644 index 0000000..e7a731bc --- /dev/null +++ b/drivers/media/rc/img-ir/img-ir-nec.c @@ -0,0 +1,148 @@ +/* + * ImgTec IR Decoder setup for NEC protocol. + * + * Copyright 2010-2014 Imagination Technologies Ltd. + */ + +#include "img-ir-hw.h" + +/* Convert NEC data to a scancode */ +static int img_ir_nec_scancode(int len, u64 raw, int *scancode, u64 protocols) +{ + unsigned int addr, addr_inv, data, data_inv; + /* a repeat code has no data */ + if (!len) + return IMG_IR_REPEATCODE; + if (len != 32) + return -EINVAL; + /* raw encoding: ddDDaaAA */ + addr = (raw >> 0) & 0xff; + addr_inv = (raw >> 8) & 0xff; + data = (raw >> 16) & 0xff; + data_inv = (raw >> 24) & 0xff; + if ((data_inv ^ data) != 0xff) { + /* 32-bit NEC (used by Apple and TiVo remotes) */ + /* scan encoding: aaAAddDD */ + *scancode = addr_inv << 24 | + addr << 16 | + data_inv << 8 | + data; + } else if ((addr_inv ^ addr) != 0xff) { + /* Extended NEC */ + /* scan encoding: AAaaDD */ + *scancode = addr << 16 | + addr_inv << 8 | + data; + } else { + /* Normal NEC */ + /* scan encoding: AADD */ + *scancode = addr << 8 | + data; + } + return IMG_IR_SCANCODE; +} + +/* Convert NEC scancode to NEC data filter */ +static int img_ir_nec_filter(const struct rc_scancode_filter *in, + struct img_ir_filter *out, u64 protocols) +{ + unsigned int addr, addr_inv, data, data_inv; + unsigned int addr_m, addr_inv_m, data_m, data_inv_m; + + data = in->data & 0xff; + data_m = in->mask & 0xff; + + if ((in->data | in->mask) & 0xff000000) { + /* 32-bit NEC (used by Apple and TiVo remotes) */ + /* scan encoding: aaAAddDD */ + addr_inv = (in->data >> 24) & 0xff; + addr_inv_m = (in->mask >> 24) & 0xff; + addr = (in->data >> 16) & 0xff; + addr_m = (in->mask >> 16) & 0xff; + data_inv = (in->data >> 8) & 0xff; + data_inv_m = (in->mask >> 8) & 0xff; + } else if ((in->data | in->mask) & 0x00ff0000) { + /* Extended NEC */ + /* scan encoding AAaaDD */ + addr = (in->data >> 16) & 0xff; + addr_m = (in->mask >> 16) & 0xff; + addr_inv = (in->data >> 8) & 0xff; + addr_inv_m = (in->mask >> 8) & 0xff; + data_inv = data ^ 0xff; + data_inv_m = data_m; + } else { + /* Normal NEC */ + /* scan encoding: AADD */ + addr = (in->data >> 8) & 0xff; + addr_m = (in->mask >> 8) & 0xff; + addr_inv = addr ^ 0xff; + addr_inv_m = addr_m; + data_inv = data ^ 0xff; + data_inv_m = data_m; + } + + /* raw encoding: ddDDaaAA */ + out->data = data_inv << 24 | + data << 16 | + addr_inv << 8 | + addr; + out->mask = data_inv_m << 24 | + data_m << 16 | + addr_inv_m << 8 | + addr_m; + return 0; +} + +/* + * NEC decoder + * See also http://www.sbprojects.com/knowledge/ir/nec.php + * http://wiki.altium.com/display/ADOH/NEC+Infrared+Transmission+Protocol + */ +struct img_ir_decoder img_ir_nec = { + .type = RC_BIT_NEC, + .control = { + .decoden = 1, + .code_type = IMG_IR_CODETYPE_PULSEDIST, + }, + /* main timings */ + .unit = 562500, /* 562.5 us */ + .timings = { + /* leader symbol */ + .ldr = { + .pulse = { 16 /* 9ms */ }, + .space = { 8 /* 4.5ms */ }, + }, + /* 0 symbol */ + .s00 = { + .pulse = { 1 /* 562.5 us */ }, + .space = { 1 /* 562.5 us */ }, + }, + /* 1 symbol */ + .s01 = { + .pulse = { 1 /* 562.5 us */ }, + .space = { 3 /* 1687.5 us */ }, + }, + /* free time */ + .ft = { + .minlen = 32, + .maxlen = 32, + .ft_min = 10, /* 5.625 ms */ + }, + }, + /* repeat codes */ + .repeat = 108, /* 108 ms */ + .rtimings = { + /* leader symbol */ + .ldr = { + .space = { 4 /* 2.25 ms */ }, + }, + /* free time */ + .ft = { + .minlen = 0, /* repeat code has no data */ + .maxlen = 0, + }, + }, + /* scancode logic */ + .scancode = img_ir_nec_scancode, + .filter = img_ir_nec_filter, +}; -- cgit v1.1 From 693365337891df8677c3faf193a35a73097ed141 Mon Sep 17 00:00:00 2001 From: James Hogan Date: Fri, 28 Feb 2014 20:28:57 -0300 Subject: [media] rc: img-ir: add JVC decoder module Add an img-ir module for decoding the JVC infrared protocol. Signed-off-by: James Hogan Signed-off-by: Mauro Carvalho Chehab --- drivers/media/rc/img-ir/Kconfig | 7 +++ drivers/media/rc/img-ir/Makefile | 1 + drivers/media/rc/img-ir/img-ir-hw.c | 4 ++ drivers/media/rc/img-ir/img-ir-jvc.c | 92 ++++++++++++++++++++++++++++++++++++ 4 files changed, 104 insertions(+) create mode 100644 drivers/media/rc/img-ir/img-ir-jvc.c diff --git a/drivers/media/rc/img-ir/Kconfig b/drivers/media/rc/img-ir/Kconfig index 28498a2..96006fbf 100644 --- a/drivers/media/rc/img-ir/Kconfig +++ b/drivers/media/rc/img-ir/Kconfig @@ -31,3 +31,10 @@ config IR_IMG_NEC help Say Y here to enable support for the NEC, extended NEC, and 32-bit NEC protocols in the ImgTec infrared decoder block. + +config IR_IMG_JVC + bool "JVC protocol support" + depends on IR_IMG_HW + help + Say Y here to enable support for the JVC protocol in the ImgTec + infrared decoder block. diff --git a/drivers/media/rc/img-ir/Makefile b/drivers/media/rc/img-ir/Makefile index c409197..c5f8f06 100644 --- a/drivers/media/rc/img-ir/Makefile +++ b/drivers/media/rc/img-ir/Makefile @@ -2,6 +2,7 @@ img-ir-y := img-ir-core.o img-ir-$(CONFIG_IR_IMG_RAW) += img-ir-raw.o img-ir-$(CONFIG_IR_IMG_HW) += img-ir-hw.o img-ir-$(CONFIG_IR_IMG_NEC) += img-ir-nec.o +img-ir-$(CONFIG_IR_IMG_JVC) += img-ir-jvc.o img-ir-objs := $(img-ir-y) obj-$(CONFIG_IR_IMG) += img-ir.o diff --git a/drivers/media/rc/img-ir/img-ir-hw.c b/drivers/media/rc/img-ir/img-ir-hw.c index 139f2c7..81c50e3 100644 --- a/drivers/media/rc/img-ir/img-ir-hw.c +++ b/drivers/media/rc/img-ir/img-ir-hw.c @@ -21,12 +21,16 @@ static DEFINE_SPINLOCK(img_ir_decoders_lock); extern struct img_ir_decoder img_ir_nec; +extern struct img_ir_decoder img_ir_jvc; static bool img_ir_decoders_preprocessed; static struct img_ir_decoder *img_ir_decoders[] = { #ifdef CONFIG_IR_IMG_NEC &img_ir_nec, #endif +#ifdef CONFIG_IR_IMG_JVC + &img_ir_jvc, +#endif NULL }; diff --git a/drivers/media/rc/img-ir/img-ir-jvc.c b/drivers/media/rc/img-ir/img-ir-jvc.c new file mode 100644 index 0000000..ae55867 --- /dev/null +++ b/drivers/media/rc/img-ir/img-ir-jvc.c @@ -0,0 +1,92 @@ +/* + * ImgTec IR Decoder setup for JVC protocol. + * + * Copyright 2012-2014 Imagination Technologies Ltd. + */ + +#include "img-ir-hw.h" + +/* Convert JVC data to a scancode */ +static int img_ir_jvc_scancode(int len, u64 raw, int *scancode, u64 protocols) +{ + unsigned int cust, data; + + if (len != 16) + return -EINVAL; + + cust = (raw >> 0) & 0xff; + data = (raw >> 8) & 0xff; + + *scancode = cust << 8 | data; + return IMG_IR_SCANCODE; +} + +/* Convert JVC scancode to JVC data filter */ +static int img_ir_jvc_filter(const struct rc_scancode_filter *in, + struct img_ir_filter *out, u64 protocols) +{ + unsigned int cust, data; + unsigned int cust_m, data_m; + + cust = (in->data >> 8) & 0xff; + cust_m = (in->mask >> 8) & 0xff; + data = (in->data >> 0) & 0xff; + data_m = (in->mask >> 0) & 0xff; + + out->data = cust | data << 8; + out->mask = cust_m | data_m << 8; + + return 0; +} + +/* + * JVC decoder + * See also http://www.sbprojects.com/knowledge/ir/jvc.php + * http://support.jvc.com/consumer/support/documents/RemoteCodes.pdf + */ +struct img_ir_decoder img_ir_jvc = { + .type = RC_BIT_JVC, + .control = { + .decoden = 1, + .code_type = IMG_IR_CODETYPE_PULSEDIST, + .decodend2 = 1, + }, + /* main timings */ + .unit = 527500, /* 527.5 us */ + .timings = { + /* leader symbol */ + .ldr = { + .pulse = { 16 /* 8.44 ms */ }, + .space = { 8 /* 4.22 ms */ }, + }, + /* 0 symbol */ + .s00 = { + .pulse = { 1 /* 527.5 us +-60 us */ }, + .space = { 1 /* 527.5 us */ }, + }, + /* 1 symbol */ + .s01 = { + .pulse = { 1 /* 527.5 us +-60 us */ }, + .space = { 3 /* 1.5825 ms +-40 us */ }, + }, + /* 0 symbol (no leader) */ + .s00 = { + .pulse = { 1 /* 527.5 us +-60 us */ }, + .space = { 1 /* 527.5 us */ }, + }, + /* 1 symbol (no leader) */ + .s01 = { + .pulse = { 1 /* 527.5 us +-60 us */ }, + .space = { 3 /* 1.5825 ms +-40 us */ }, + }, + /* free time */ + .ft = { + .minlen = 16, + .maxlen = 16, + .ft_min = 10, /* 5.275 ms */ + }, + }, + /* scancode logic */ + .scancode = img_ir_jvc_scancode, + .filter = img_ir_jvc_filter, +}; -- cgit v1.1 From e72b21abc8ec76b3e2c332e631f15d975e781e37 Mon Sep 17 00:00:00 2001 From: James Hogan Date: Fri, 28 Feb 2014 20:28:58 -0300 Subject: [media] rc: img-ir: add Sony decoder module Add an img-ir module for decoding the Sony infrared protocol. Signed-off-by: James Hogan Signed-off-by: Mauro Carvalho Chehab --- drivers/media/rc/img-ir/Kconfig | 7 ++ drivers/media/rc/img-ir/Makefile | 1 + drivers/media/rc/img-ir/img-ir-hw.c | 4 + drivers/media/rc/img-ir/img-ir-sony.c | 145 ++++++++++++++++++++++++++++++++++ 4 files changed, 157 insertions(+) create mode 100644 drivers/media/rc/img-ir/img-ir-sony.c diff --git a/drivers/media/rc/img-ir/Kconfig b/drivers/media/rc/img-ir/Kconfig index 96006fbf..ab36577 100644 --- a/drivers/media/rc/img-ir/Kconfig +++ b/drivers/media/rc/img-ir/Kconfig @@ -38,3 +38,10 @@ config IR_IMG_JVC help Say Y here to enable support for the JVC protocol in the ImgTec infrared decoder block. + +config IR_IMG_SONY + bool "Sony protocol support" + depends on IR_IMG_HW + help + Say Y here to enable support for the Sony protocol in the ImgTec + infrared decoder block. diff --git a/drivers/media/rc/img-ir/Makefile b/drivers/media/rc/img-ir/Makefile index c5f8f06..978c0c6 100644 --- a/drivers/media/rc/img-ir/Makefile +++ b/drivers/media/rc/img-ir/Makefile @@ -3,6 +3,7 @@ img-ir-$(CONFIG_IR_IMG_RAW) += img-ir-raw.o img-ir-$(CONFIG_IR_IMG_HW) += img-ir-hw.o img-ir-$(CONFIG_IR_IMG_NEC) += img-ir-nec.o img-ir-$(CONFIG_IR_IMG_JVC) += img-ir-jvc.o +img-ir-$(CONFIG_IR_IMG_SONY) += img-ir-sony.o img-ir-objs := $(img-ir-y) obj-$(CONFIG_IR_IMG) += img-ir.o diff --git a/drivers/media/rc/img-ir/img-ir-hw.c b/drivers/media/rc/img-ir/img-ir-hw.c index 81c50e3..0d4f921 100644 --- a/drivers/media/rc/img-ir/img-ir-hw.c +++ b/drivers/media/rc/img-ir/img-ir-hw.c @@ -22,6 +22,7 @@ static DEFINE_SPINLOCK(img_ir_decoders_lock); extern struct img_ir_decoder img_ir_nec; extern struct img_ir_decoder img_ir_jvc; +extern struct img_ir_decoder img_ir_sony; static bool img_ir_decoders_preprocessed; static struct img_ir_decoder *img_ir_decoders[] = { @@ -31,6 +32,9 @@ static struct img_ir_decoder *img_ir_decoders[] = { #ifdef CONFIG_IR_IMG_JVC &img_ir_jvc, #endif +#ifdef CONFIG_IR_IMG_SONY + &img_ir_sony, +#endif NULL }; diff --git a/drivers/media/rc/img-ir/img-ir-sony.c b/drivers/media/rc/img-ir/img-ir-sony.c new file mode 100644 index 0000000..993409a --- /dev/null +++ b/drivers/media/rc/img-ir/img-ir-sony.c @@ -0,0 +1,145 @@ +/* + * ImgTec IR Decoder setup for Sony (SIRC) protocol. + * + * Copyright 2012-2014 Imagination Technologies Ltd. + */ + +#include "img-ir-hw.h" + +/* Convert Sony data to a scancode */ +static int img_ir_sony_scancode(int len, u64 raw, int *scancode, u64 protocols) +{ + unsigned int dev, subdev, func; + + switch (len) { + case 12: + if (!(protocols & RC_BIT_SONY12)) + return -EINVAL; + func = raw & 0x7f; /* first 7 bits */ + raw >>= 7; + dev = raw & 0x1f; /* next 5 bits */ + subdev = 0; + break; + case 15: + if (!(protocols & RC_BIT_SONY15)) + return -EINVAL; + func = raw & 0x7f; /* first 7 bits */ + raw >>= 7; + dev = raw & 0xff; /* next 8 bits */ + subdev = 0; + break; + case 20: + if (!(protocols & RC_BIT_SONY20)) + return -EINVAL; + func = raw & 0x7f; /* first 7 bits */ + raw >>= 7; + dev = raw & 0x1f; /* next 5 bits */ + raw >>= 5; + subdev = raw & 0xff; /* next 8 bits */ + break; + default: + return -EINVAL; + } + *scancode = dev << 16 | subdev << 8 | func; + return IMG_IR_SCANCODE; +} + +/* Convert NEC scancode to NEC data filter */ +static int img_ir_sony_filter(const struct rc_scancode_filter *in, + struct img_ir_filter *out, u64 protocols) +{ + unsigned int dev, subdev, func; + unsigned int dev_m, subdev_m, func_m; + unsigned int len = 0; + + dev = (in->data >> 16) & 0xff; + dev_m = (in->mask >> 16) & 0xff; + subdev = (in->data >> 8) & 0xff; + subdev_m = (in->mask >> 8) & 0xff; + func = (in->data >> 0) & 0x7f; + func_m = (in->mask >> 0) & 0x7f; + + if (subdev & subdev_m) { + /* can't encode subdev and higher device bits */ + if (dev & dev_m & 0xe0) + return -EINVAL; + /* subdevice (extended) bits only in 20 bit encoding */ + if (!(protocols & RC_BIT_SONY20)) + return -EINVAL; + len = 20; + dev_m &= 0x1f; + } else if (dev & dev_m & 0xe0) { + /* upper device bits only in 15 bit encoding */ + if (!(protocols & RC_BIT_SONY15)) + return -EINVAL; + len = 15; + subdev_m = 0; + } else { + /* + * The hardware mask cannot distinguish high device bits and low + * extended bits, so logically AND those bits of the masks + * together. + */ + subdev_m &= (dev_m >> 5) | 0xf8; + dev_m &= 0x1f; + } + + /* ensure there aren't any bits straying between fields */ + dev &= dev_m; + subdev &= subdev_m; + + /* write the hardware filter */ + out->data = func | + dev << 7 | + subdev << 15; + out->mask = func_m | + dev_m << 7 | + subdev_m << 15; + + if (len) { + out->minlen = len; + out->maxlen = len; + } + return 0; +} + +/* + * Sony SIRC decoder + * See also http://www.sbprojects.com/knowledge/ir/sirc.php + * http://picprojects.org.uk/projects/sirc/sonysirc.pdf + */ +struct img_ir_decoder img_ir_sony = { + .type = RC_BIT_SONY12 | RC_BIT_SONY15 | RC_BIT_SONY20, + .control = { + .decoden = 1, + .code_type = IMG_IR_CODETYPE_PULSELEN, + }, + /* main timings */ + .unit = 600000, /* 600 us */ + .timings = { + /* leader symbol */ + .ldr = { + .pulse = { 4 /* 2.4 ms */ }, + .space = { 1 /* 600 us */ }, + }, + /* 0 symbol */ + .s00 = { + .pulse = { 1 /* 600 us */ }, + .space = { 1 /* 600 us */ }, + }, + /* 1 symbol */ + .s01 = { + .pulse = { 2 /* 1.2 ms */ }, + .space = { 1 /* 600 us */ }, + }, + /* free time */ + .ft = { + .minlen = 12, + .maxlen = 20, + .ft_min = 10, /* 6 ms */ + }, + }, + /* scancode logic */ + .scancode = img_ir_sony_scancode, + .filter = img_ir_sony_filter, +}; -- cgit v1.1 From 3c11305eee6a13695954dbc067234d492cb7879c Mon Sep 17 00:00:00 2001 From: James Hogan Date: Fri, 28 Feb 2014 20:28:59 -0300 Subject: [media] rc: img-ir: add Sharp decoder module Add an img-ir module for decoding the Sharp infrared protocol. Signed-off-by: James Hogan Signed-off-by: Mauro Carvalho Chehab --- drivers/media/rc/img-ir/Kconfig | 7 +++ drivers/media/rc/img-ir/Makefile | 1 + drivers/media/rc/img-ir/img-ir-hw.c | 4 ++ drivers/media/rc/img-ir/img-ir-sharp.c | 99 ++++++++++++++++++++++++++++++++++ 4 files changed, 111 insertions(+) create mode 100644 drivers/media/rc/img-ir/img-ir-sharp.c diff --git a/drivers/media/rc/img-ir/Kconfig b/drivers/media/rc/img-ir/Kconfig index ab36577..48627f9 100644 --- a/drivers/media/rc/img-ir/Kconfig +++ b/drivers/media/rc/img-ir/Kconfig @@ -45,3 +45,10 @@ config IR_IMG_SONY help Say Y here to enable support for the Sony protocol in the ImgTec infrared decoder block. + +config IR_IMG_SHARP + bool "Sharp protocol support" + depends on IR_IMG_HW + help + Say Y here to enable support for the Sharp protocol in the ImgTec + infrared decoder block. diff --git a/drivers/media/rc/img-ir/Makefile b/drivers/media/rc/img-ir/Makefile index 978c0c6..792a3c4 100644 --- a/drivers/media/rc/img-ir/Makefile +++ b/drivers/media/rc/img-ir/Makefile @@ -4,6 +4,7 @@ img-ir-$(CONFIG_IR_IMG_HW) += img-ir-hw.o img-ir-$(CONFIG_IR_IMG_NEC) += img-ir-nec.o img-ir-$(CONFIG_IR_IMG_JVC) += img-ir-jvc.o img-ir-$(CONFIG_IR_IMG_SONY) += img-ir-sony.o +img-ir-$(CONFIG_IR_IMG_SHARP) += img-ir-sharp.o img-ir-objs := $(img-ir-y) obj-$(CONFIG_IR_IMG) += img-ir.o diff --git a/drivers/media/rc/img-ir/img-ir-hw.c b/drivers/media/rc/img-ir/img-ir-hw.c index 0d4f921..9931dfa 100644 --- a/drivers/media/rc/img-ir/img-ir-hw.c +++ b/drivers/media/rc/img-ir/img-ir-hw.c @@ -23,6 +23,7 @@ static DEFINE_SPINLOCK(img_ir_decoders_lock); extern struct img_ir_decoder img_ir_nec; extern struct img_ir_decoder img_ir_jvc; extern struct img_ir_decoder img_ir_sony; +extern struct img_ir_decoder img_ir_sharp; static bool img_ir_decoders_preprocessed; static struct img_ir_decoder *img_ir_decoders[] = { @@ -35,6 +36,9 @@ static struct img_ir_decoder *img_ir_decoders[] = { #ifdef CONFIG_IR_IMG_SONY &img_ir_sony, #endif +#ifdef CONFIG_IR_IMG_SHARP + &img_ir_sharp, +#endif NULL }; diff --git a/drivers/media/rc/img-ir/img-ir-sharp.c b/drivers/media/rc/img-ir/img-ir-sharp.c new file mode 100644 index 0000000..3397cc5 --- /dev/null +++ b/drivers/media/rc/img-ir/img-ir-sharp.c @@ -0,0 +1,99 @@ +/* + * ImgTec IR Decoder setup for Sharp protocol. + * + * Copyright 2012-2014 Imagination Technologies Ltd. + */ + +#include "img-ir-hw.h" + +/* Convert Sharp data to a scancode */ +static int img_ir_sharp_scancode(int len, u64 raw, int *scancode, u64 protocols) +{ + unsigned int addr, cmd, exp, chk; + + if (len != 15) + return -EINVAL; + + addr = (raw >> 0) & 0x1f; + cmd = (raw >> 5) & 0xff; + exp = (raw >> 13) & 0x1; + chk = (raw >> 14) & 0x1; + + /* validate data */ + if (!exp) + return -EINVAL; + if (chk) + /* probably the second half of the message */ + return -EINVAL; + + *scancode = addr << 8 | cmd; + return IMG_IR_SCANCODE; +} + +/* Convert Sharp scancode to Sharp data filter */ +static int img_ir_sharp_filter(const struct rc_scancode_filter *in, + struct img_ir_filter *out, u64 protocols) +{ + unsigned int addr, cmd, exp = 0, chk = 0; + unsigned int addr_m, cmd_m, exp_m = 0, chk_m = 0; + + addr = (in->data >> 8) & 0x1f; + addr_m = (in->mask >> 8) & 0x1f; + cmd = (in->data >> 0) & 0xff; + cmd_m = (in->mask >> 0) & 0xff; + if (cmd_m) { + /* if filtering commands, we can only match the first part */ + exp = 1; + exp_m = 1; + chk = 0; + chk_m = 1; + } + + out->data = addr | + cmd << 5 | + exp << 13 | + chk << 14; + out->mask = addr_m | + cmd_m << 5 | + exp_m << 13 | + chk_m << 14; + + return 0; +} + +/* + * Sharp decoder + * See also http://www.sbprojects.com/knowledge/ir/sharp.php + */ +struct img_ir_decoder img_ir_sharp = { + .type = RC_BIT_SHARP, + .control = { + .decoden = 0, + .decodend2 = 1, + .code_type = IMG_IR_CODETYPE_PULSEDIST, + .d1validsel = 1, + }, + /* main timings */ + .tolerance = 20, /* 20% */ + .timings = { + /* 0 symbol */ + .s10 = { + .pulse = { 320 /* 320 us */ }, + .space = { 680 /* 1 ms period */ }, + }, + /* 1 symbol */ + .s11 = { + .pulse = { 320 /* 320 us */ }, + .space = { 1680 /* 2 ms period */ }, + }, + /* free time */ + .ft = { + .minlen = 15, + .maxlen = 15, + .ft_min = 5000, /* 5 ms */ + }, + }, + /* scancode logic */ + .scancode = img_ir_sharp_scancode, + .filter = img_ir_sharp_filter, +}; -- cgit v1.1 From 46b35083ce24c1a2a721df605815978f75ca3b66 Mon Sep 17 00:00:00 2001 From: James Hogan Date: Fri, 28 Feb 2014 20:29:00 -0300 Subject: [media] rc: img-ir: add Sanyo decoder module Add an img-ir module for decoding the Sanyo infrared protocol. Signed-off-by: James Hogan Signed-off-by: Mauro Carvalho Chehab --- drivers/media/rc/img-ir/Kconfig | 7 ++ drivers/media/rc/img-ir/Makefile | 1 + drivers/media/rc/img-ir/img-ir-hw.c | 4 ++ drivers/media/rc/img-ir/img-ir-sanyo.c | 122 +++++++++++++++++++++++++++++++++ 4 files changed, 134 insertions(+) create mode 100644 drivers/media/rc/img-ir/img-ir-sanyo.c diff --git a/drivers/media/rc/img-ir/Kconfig b/drivers/media/rc/img-ir/Kconfig index 48627f9..03ba9fc 100644 --- a/drivers/media/rc/img-ir/Kconfig +++ b/drivers/media/rc/img-ir/Kconfig @@ -52,3 +52,10 @@ config IR_IMG_SHARP help Say Y here to enable support for the Sharp protocol in the ImgTec infrared decoder block. + +config IR_IMG_SANYO + bool "Sanyo protocol support" + depends on IR_IMG_HW + help + Say Y here to enable support for the Sanyo protocol (used by Sanyo, + Aiwa, Chinon remotes) in the ImgTec infrared decoder block. diff --git a/drivers/media/rc/img-ir/Makefile b/drivers/media/rc/img-ir/Makefile index 792a3c4..92a459d 100644 --- a/drivers/media/rc/img-ir/Makefile +++ b/drivers/media/rc/img-ir/Makefile @@ -5,6 +5,7 @@ img-ir-$(CONFIG_IR_IMG_NEC) += img-ir-nec.o img-ir-$(CONFIG_IR_IMG_JVC) += img-ir-jvc.o img-ir-$(CONFIG_IR_IMG_SONY) += img-ir-sony.o img-ir-$(CONFIG_IR_IMG_SHARP) += img-ir-sharp.o +img-ir-$(CONFIG_IR_IMG_SANYO) += img-ir-sanyo.o img-ir-objs := $(img-ir-y) obj-$(CONFIG_IR_IMG) += img-ir.o diff --git a/drivers/media/rc/img-ir/img-ir-hw.c b/drivers/media/rc/img-ir/img-ir-hw.c index 9931dfa..cbbfd7d 100644 --- a/drivers/media/rc/img-ir/img-ir-hw.c +++ b/drivers/media/rc/img-ir/img-ir-hw.c @@ -24,6 +24,7 @@ extern struct img_ir_decoder img_ir_nec; extern struct img_ir_decoder img_ir_jvc; extern struct img_ir_decoder img_ir_sony; extern struct img_ir_decoder img_ir_sharp; +extern struct img_ir_decoder img_ir_sanyo; static bool img_ir_decoders_preprocessed; static struct img_ir_decoder *img_ir_decoders[] = { @@ -39,6 +40,9 @@ static struct img_ir_decoder *img_ir_decoders[] = { #ifdef CONFIG_IR_IMG_SHARP &img_ir_sharp, #endif +#ifdef CONFIG_IR_IMG_SANYO + &img_ir_sanyo, +#endif NULL }; diff --git a/drivers/media/rc/img-ir/img-ir-sanyo.c b/drivers/media/rc/img-ir/img-ir-sanyo.c new file mode 100644 index 0000000..c2c763e --- /dev/null +++ b/drivers/media/rc/img-ir/img-ir-sanyo.c @@ -0,0 +1,122 @@ +/* + * ImgTec IR Decoder setup for Sanyo protocol. + * + * Copyright 2012-2014 Imagination Technologies Ltd. + * + * From ir-sanyo-decoder.c: + * + * This protocol uses the NEC protocol timings. However, data is formatted as: + * 13 bits Custom Code + * 13 bits NOT(Custom Code) + * 8 bits Key data + * 8 bits NOT(Key data) + * + * According with LIRC, this protocol is used on Sanyo, Aiwa and Chinon + * Information for this protocol is available at the Sanyo LC7461 datasheet. + */ + +#include "img-ir-hw.h" + +/* Convert Sanyo data to a scancode */ +static int img_ir_sanyo_scancode(int len, u64 raw, int *scancode, u64 protocols) +{ + unsigned int addr, addr_inv, data, data_inv; + /* a repeat code has no data */ + if (!len) + return IMG_IR_REPEATCODE; + if (len != 42) + return -EINVAL; + addr = (raw >> 0) & 0x1fff; + addr_inv = (raw >> 13) & 0x1fff; + data = (raw >> 26) & 0xff; + data_inv = (raw >> 34) & 0xff; + /* Validate data */ + if ((data_inv ^ data) != 0xff) + return -EINVAL; + /* Validate address */ + if ((addr_inv ^ addr) != 0x1fff) + return -EINVAL; + + /* Normal Sanyo */ + *scancode = addr << 8 | data; + return IMG_IR_SCANCODE; +} + +/* Convert Sanyo scancode to Sanyo data filter */ +static int img_ir_sanyo_filter(const struct rc_scancode_filter *in, + struct img_ir_filter *out, u64 protocols) +{ + unsigned int addr, addr_inv, data, data_inv; + unsigned int addr_m, data_m; + + data = in->data & 0xff; + data_m = in->mask & 0xff; + data_inv = data ^ 0xff; + + if (in->data & 0xff700000) + return -EINVAL; + + addr = (in->data >> 8) & 0x1fff; + addr_m = (in->mask >> 8) & 0x1fff; + addr_inv = addr ^ 0x1fff; + + out->data = (u64)data_inv << 34 | + (u64)data << 26 | + addr_inv << 13 | + addr; + out->mask = (u64)data_m << 34 | + (u64)data_m << 26 | + addr_m << 13 | + addr_m; + return 0; +} + +/* Sanyo decoder */ +struct img_ir_decoder img_ir_sanyo = { + .type = RC_BIT_SANYO, + .control = { + .decoden = 1, + .code_type = IMG_IR_CODETYPE_PULSEDIST, + }, + /* main timings */ + .unit = 562500, /* 562.5 us */ + .timings = { + /* leader symbol */ + .ldr = { + .pulse = { 16 /* 9ms */ }, + .space = { 8 /* 4.5ms */ }, + }, + /* 0 symbol */ + .s00 = { + .pulse = { 1 /* 562.5 us */ }, + .space = { 1 /* 562.5 us */ }, + }, + /* 1 symbol */ + .s01 = { + .pulse = { 1 /* 562.5 us */ }, + .space = { 3 /* 1687.5 us */ }, + }, + /* free time */ + .ft = { + .minlen = 42, + .maxlen = 42, + .ft_min = 10, /* 5.625 ms */ + }, + }, + /* repeat codes */ + .repeat = 108, /* 108 ms */ + .rtimings = { + /* leader symbol */ + .ldr = { + .space = { 4 /* 2.25 ms */ }, + }, + /* free time */ + .ft = { + .minlen = 0, /* repeat code has no data */ + .maxlen = 0, + }, + }, + /* scancode logic */ + .scancode = img_ir_sanyo_scancode, + .filter = img_ir_sanyo_filter, +}; -- cgit v1.1 From f8817c9ea1f44aca9f342c6a314da4eb64ba0cb4 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Sat, 1 Mar 2014 10:51:36 -0300 Subject: [media] av7110_hw: fix a sanity check in av7110_fw_cmd() ARRAY_SIZE(buf) (8 elements) was intended instead of sizeof(buf) (16 bytes). But this is just a sanity check and the callers always pass valid values so this doesn't cause a problem. Signed-off-by: Dan Carpenter Signed-off-by: Mauro Carvalho Chehab --- drivers/media/pci/ttpci/av7110_hw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/pci/ttpci/av7110_hw.c b/drivers/media/pci/ttpci/av7110_hw.c index 6299d5d..300bd3c 100644 --- a/drivers/media/pci/ttpci/av7110_hw.c +++ b/drivers/media/pci/ttpci/av7110_hw.c @@ -501,7 +501,7 @@ int av7110_fw_cmd(struct av7110 *av7110, int type, int com, int num, ...) // dprintk(4, "%p\n", av7110); - if (2 + num > sizeof(buf)) { + if (2 + num > ARRAY_SIZE(buf)) { printk(KERN_WARNING "%s: %s len=%d is too big!\n", KBUILD_MODNAME, __func__, num); -- cgit v1.1 From cdcb12e78a4559c1842fbf8fb82e770b9f7362d6 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Sat, 1 Mar 2014 10:55:29 -0300 Subject: [media] ddbridge: remove unneeded an NULL check Static checkers complain about the inconsistent NULL check here. There is an unchecked dereference of "input->fe" in the call to tuner_attach_tda18271() and there is a second unchecked dereference a couple lines later when we do: input->fe2->tuner_priv = input->fe->tuner_priv; But actually "intput->fe" can't be NULL because if demod_attach_drxk() fails to allocate it, then we would have return an error code. Signed-off-by: Dan Carpenter Signed-off-by: Mauro Carvalho Chehab --- drivers/media/pci/ddbridge/ddbridge-core.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/media/pci/ddbridge/ddbridge-core.c b/drivers/media/pci/ddbridge/ddbridge-core.c index 9375f30..fb52bda8 100644 --- a/drivers/media/pci/ddbridge/ddbridge-core.c +++ b/drivers/media/pci/ddbridge/ddbridge-core.c @@ -876,10 +876,8 @@ static int dvb_input_attach(struct ddb_input *input) return -ENODEV; if (tuner_attach_tda18271(input) < 0) return -ENODEV; - if (input->fe) { - if (dvb_register_frontend(adap, input->fe) < 0) - return -ENODEV; - } + if (dvb_register_frontend(adap, input->fe) < 0) + return -ENODEV; if (input->fe2) { if (dvb_register_frontend(adap, input->fe2) < 0) return -ENODEV; -- cgit v1.1 From 262912335c823a2bbcc87003ee55d62cc27f4e48 Mon Sep 17 00:00:00 2001 From: James Hogan Date: Sat, 1 Mar 2014 19:52:25 -0300 Subject: [media] rc-main: fix missing unlock if no devno left While playing with make coccicheck I noticed this message: drivers/media/rc/rc-main.c:1245:3-9: preceding lock on line 1238 It was introduced by commit 587d1b06e07b ([media] rc-core: reuse device numbers) which returns -ENOMEM after a mutex_lock without first unlocking it when there are no more device numbers left. The added code doesn't depend on the device lock, so move it before the lock is taken. Signed-off-by: James Hogan Signed-off-by: Mauro Carvalho Chehab --- drivers/media/rc/rc-main.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/media/rc/rc-main.c b/drivers/media/rc/rc-main.c index b1a6900..f87e0f0 100644 --- a/drivers/media/rc/rc-main.c +++ b/drivers/media/rc/rc-main.c @@ -1286,14 +1286,6 @@ int rc_register_device(struct rc_dev *dev) if (dev->close) dev->input_dev->close = ir_close; - /* - * Take the lock here, as the device sysfs node will appear - * when device_add() is called, which may trigger an ir-keytable udev - * rule, which will in turn call show_protocols and access - * dev->enabled_protocols before it has been initialized. - */ - mutex_lock(&dev->lock); - do { devno = find_first_zero_bit(ir_core_dev_number, IRRCV_NUM_DEVICES); @@ -1302,6 +1294,14 @@ int rc_register_device(struct rc_dev *dev) return -ENOMEM; } while (test_and_set_bit(devno, ir_core_dev_number)); + /* + * Take the lock here, as the device sysfs node will appear + * when device_add() is called, which may trigger an ir-keytable udev + * rule, which will in turn call show_protocols and access + * dev->enabled_protocols before it has been initialized. + */ + mutex_lock(&dev->lock); + dev->devno = devno; dev_set_name(&dev->dev, "rc%ld", dev->devno); dev_set_drvdata(&dev->dev, dev); -- cgit v1.1 From 672e02485e008052394970fb46ba7e59abb90ce8 Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Sat, 1 Feb 2014 11:57:50 -0300 Subject: [media] m88ds3103: remove dead code Coverity CID 1166050: Dead default in switch (DEADCODE) Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/m88ds3103.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/drivers/media/dvb-frontends/m88ds3103.c b/drivers/media/dvb-frontends/m88ds3103.c index b8a7897..e261bf9 100644 --- a/drivers/media/dvb-frontends/m88ds3103.c +++ b/drivers/media/dvb-frontends/m88ds3103.c @@ -711,9 +711,6 @@ static int m88ds3103_get_frontend(struct dvb_frontend *fe) case 1: c->inversion = INVERSION_ON; break; - default: - dev_dbg(&priv->i2c->dev, "%s: invalid inversion\n", - __func__); } switch ((buf[1] >> 5) & 0x07) { @@ -793,9 +790,6 @@ static int m88ds3103_get_frontend(struct dvb_frontend *fe) case 1: c->pilot = PILOT_ON; break; - default: - dev_dbg(&priv->i2c->dev, "%s: invalid pilot\n", - __func__); } switch ((buf[0] >> 6) & 0x07) { @@ -823,9 +817,6 @@ static int m88ds3103_get_frontend(struct dvb_frontend *fe) case 1: c->inversion = INVERSION_ON; break; - default: - dev_dbg(&priv->i2c->dev, "%s: invalid inversion\n", - __func__); } switch ((buf[2] >> 0) & 0x03) { -- cgit v1.1 From 8a648fbbc1a1a3b4b500c63b5a953397103dfe22 Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Sat, 1 Feb 2014 12:30:28 -0300 Subject: [media] m88ds3103: remove dead code 2nd part Coverity CID 1166051: Logically dead code (DEADCODE) TS clock calculation could be more accurate, but as it is not, remove those unused clock speeds. Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/m88ds3103.c | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/drivers/media/dvb-frontends/m88ds3103.c b/drivers/media/dvb-frontends/m88ds3103.c index e261bf9..c0a78d9 100644 --- a/drivers/media/dvb-frontends/m88ds3103.c +++ b/drivers/media/dvb-frontends/m88ds3103.c @@ -428,18 +428,10 @@ static int m88ds3103_set_frontend(struct dvb_frontend *fe) goto err; switch (target_mclk) { - case 72000: - u8tmp1 = 0x00; /* 0b00 */ - u8tmp2 = 0x03; /* 0b11 */ - break; case 96000: u8tmp1 = 0x02; /* 0b10 */ u8tmp2 = 0x01; /* 0b01 */ break; - case 115200: - u8tmp1 = 0x01; /* 0b01 */ - u8tmp2 = 0x01; /* 0b01 */ - break; case 144000: u8tmp1 = 0x00; /* 0b00 */ u8tmp2 = 0x01; /* 0b01 */ @@ -448,10 +440,6 @@ static int m88ds3103_set_frontend(struct dvb_frontend *fe) u8tmp1 = 0x03; /* 0b11 */ u8tmp2 = 0x00; /* 0b00 */ break; - default: - dev_dbg(&priv->i2c->dev, "%s: invalid target_mclk\n", __func__); - ret = -EINVAL; - goto err; } ret = m88ds3103_wr_reg_mask(priv, 0x22, u8tmp1 << 6, 0xc0); -- cgit v1.1 From 2f9dff3f39f0d6dac9209e2267517aebc1c6f86c Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Sat, 1 Feb 2014 12:58:28 -0300 Subject: [media] m88ds3103: possible uninitialized scalar variable It was possible that tuner_frequency variable, used for carrier offset compensation, was uninitialized. That happens when tuner .get_frequency() callback is not defined. Currently that case is not possible as only used tuner has this callback. Coverity CID 1166057: Uninitialized scalar variable (UNINIT) Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/m88ds3103.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/media/dvb-frontends/m88ds3103.c b/drivers/media/dvb-frontends/m88ds3103.c index c0a78d9..b8f8df0 100644 --- a/drivers/media/dvb-frontends/m88ds3103.c +++ b/drivers/media/dvb-frontends/m88ds3103.c @@ -271,6 +271,13 @@ static int m88ds3103_set_frontend(struct dvb_frontend *fe) ret = fe->ops.tuner_ops.get_frequency(fe, &tuner_frequency); if (ret) goto err; + } else { + /* + * Use nominal target frequency as tuner driver does not provide + * actual frequency used. Carrier offset calculation is not + * valid. + */ + tuner_frequency = c->frequency; } /* reset */ -- cgit v1.1 From 0123f29caf65d0adef9f37f439a85d5c2822334e Mon Sep 17 00:00:00 2001 From: Ole Ernst Date: Wed, 5 Mar 2014 14:08:15 -0300 Subject: [media] dvb_frontend: Fix possible read out of bounds Check if index is within bounds _before_ accessing the value. Signed-off-by: Ole Ernst Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-core/dvb_frontend.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/media/dvb-core/dvb_frontend.c b/drivers/media/dvb-core/dvb_frontend.c index 2d32c13..6ce435a 100644 --- a/drivers/media/dvb-core/dvb_frontend.c +++ b/drivers/media/dvb-core/dvb_frontend.c @@ -1279,7 +1279,7 @@ static int dtv_property_process_get(struct dvb_frontend *fe, switch(tvp->cmd) { case DTV_ENUM_DELSYS: ncaps = 0; - while (fe->ops.delsys[ncaps] && ncaps < MAX_DELSYS) { + while (ncaps < MAX_DELSYS && fe->ops.delsys[ncaps]) { tvp->u.buffer.data[ncaps] = fe->ops.delsys[ncaps]; ncaps++; } @@ -1596,7 +1596,7 @@ static int dvbv5_set_delivery_system(struct dvb_frontend *fe, * supported */ ncaps = 0; - while (fe->ops.delsys[ncaps] && ncaps < MAX_DELSYS) { + while (ncaps < MAX_DELSYS && fe->ops.delsys[ncaps]) { if (fe->ops.delsys[ncaps] == desired_system) { c->delivery_system = desired_system; dev_dbg(fe->dvb->device, @@ -1628,7 +1628,7 @@ static int dvbv5_set_delivery_system(struct dvb_frontend *fe, * of the desired system */ ncaps = 0; - while (fe->ops.delsys[ncaps] && ncaps < MAX_DELSYS) { + while (ncaps < MAX_DELSYS && fe->ops.delsys[ncaps]) { if (dvbv3_type(fe->ops.delsys[ncaps]) == type) delsys = fe->ops.delsys[ncaps]; ncaps++; @@ -1703,7 +1703,7 @@ static int dvbv3_set_delivery_system(struct dvb_frontend *fe) * DVBv3 standard */ ncaps = 0; - while (fe->ops.delsys[ncaps] && ncaps < MAX_DELSYS) { + while (ncaps < MAX_DELSYS && fe->ops.delsys[ncaps]) { if (dvbv3_type(fe->ops.delsys[ncaps]) != DVBV3_UNKNOWN) { delsys = fe->ops.delsys[ncaps]; break; -- cgit v1.1 From 8a1edc55c1ec1ff3624c25b4ac6c1ce776d872b8 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 6 Feb 2014 14:42:31 -0300 Subject: [media] v4l: vsp1: Update copyright notice The "Renesas Corporation" listed in the copyright notice doesn't exist. Replace it with "Renesas Electronics Corporation" and update the copyright years. Signed-off-by: Laurent Pinchart Signed-off-by: Mauro Carvalho Chehab --- drivers/media/platform/vsp1/vsp1.h | 2 +- drivers/media/platform/vsp1/vsp1_drv.c | 2 +- drivers/media/platform/vsp1/vsp1_entity.c | 2 +- drivers/media/platform/vsp1/vsp1_entity.h | 2 +- drivers/media/platform/vsp1/vsp1_lif.c | 2 +- drivers/media/platform/vsp1/vsp1_lif.h | 2 +- drivers/media/platform/vsp1/vsp1_rpf.c | 2 +- drivers/media/platform/vsp1/vsp1_rwpf.c | 2 +- drivers/media/platform/vsp1/vsp1_rwpf.h | 2 +- drivers/media/platform/vsp1/vsp1_uds.c | 2 +- drivers/media/platform/vsp1/vsp1_uds.h | 2 +- drivers/media/platform/vsp1/vsp1_video.c | 2 +- drivers/media/platform/vsp1/vsp1_video.h | 2 +- drivers/media/platform/vsp1/vsp1_wpf.c | 2 +- 14 files changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/media/platform/vsp1/vsp1.h b/drivers/media/platform/vsp1/vsp1.h index 94d1b02..0313210 100644 --- a/drivers/media/platform/vsp1/vsp1.h +++ b/drivers/media/platform/vsp1/vsp1.h @@ -1,7 +1,7 @@ /* * vsp1.h -- R-Car VSP1 Driver * - * Copyright (C) 2013 Renesas Corporation + * Copyright (C) 2013-2014 Renesas Electronics Corporation * * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) * diff --git a/drivers/media/platform/vsp1/vsp1_drv.c b/drivers/media/platform/vsp1/vsp1_drv.c index 0df0a99..2f74f0e 100644 --- a/drivers/media/platform/vsp1/vsp1_drv.c +++ b/drivers/media/platform/vsp1/vsp1_drv.c @@ -1,7 +1,7 @@ /* * vsp1_drv.c -- R-Car VSP1 Driver * - * Copyright (C) 2013 Renesas Corporation + * Copyright (C) 2013-2014 Renesas Electronics Corporation * * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) * diff --git a/drivers/media/platform/vsp1/vsp1_entity.c b/drivers/media/platform/vsp1/vsp1_entity.c index 0226e47..3fc9e42 100644 --- a/drivers/media/platform/vsp1/vsp1_entity.c +++ b/drivers/media/platform/vsp1/vsp1_entity.c @@ -1,7 +1,7 @@ /* * vsp1_entity.c -- R-Car VSP1 Base Entity * - * Copyright (C) 2013 Renesas Corporation + * Copyright (C) 2013-2014 Renesas Electronics Corporation * * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) * diff --git a/drivers/media/platform/vsp1/vsp1_entity.h b/drivers/media/platform/vsp1/vsp1_entity.h index e152798..f6fd698 100644 --- a/drivers/media/platform/vsp1/vsp1_entity.h +++ b/drivers/media/platform/vsp1/vsp1_entity.h @@ -1,7 +1,7 @@ /* * vsp1_entity.h -- R-Car VSP1 Base Entity * - * Copyright (C) 2013 Renesas Corporation + * Copyright (C) 2013-2014 Renesas Electronics Corporation * * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) * diff --git a/drivers/media/platform/vsp1/vsp1_lif.c b/drivers/media/platform/vsp1/vsp1_lif.c index 74a32e6..135a789 100644 --- a/drivers/media/platform/vsp1/vsp1_lif.c +++ b/drivers/media/platform/vsp1/vsp1_lif.c @@ -1,7 +1,7 @@ /* * vsp1_lif.c -- R-Car VSP1 LCD Controller Interface * - * Copyright (C) 2013 Renesas Corporation + * Copyright (C) 2013-2014 Renesas Electronics Corporation * * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) * diff --git a/drivers/media/platform/vsp1/vsp1_lif.h b/drivers/media/platform/vsp1/vsp1_lif.h index 89b93af..7b35879 100644 --- a/drivers/media/platform/vsp1/vsp1_lif.h +++ b/drivers/media/platform/vsp1/vsp1_lif.h @@ -1,7 +1,7 @@ /* * vsp1_lif.h -- R-Car VSP1 LCD Controller Interface * - * Copyright (C) 2013 Renesas Corporation + * Copyright (C) 2013-2014 Renesas Electronics Corporation * * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) * diff --git a/drivers/media/platform/vsp1/vsp1_rpf.c b/drivers/media/platform/vsp1/vsp1_rpf.c index bce2be5..2b04d0f 100644 --- a/drivers/media/platform/vsp1/vsp1_rpf.c +++ b/drivers/media/platform/vsp1/vsp1_rpf.c @@ -1,7 +1,7 @@ /* * vsp1_rpf.c -- R-Car VSP1 Read Pixel Formatter * - * Copyright (C) 2013 Renesas Corporation + * Copyright (C) 2013-2014 Renesas Electronics Corporation * * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) * diff --git a/drivers/media/platform/vsp1/vsp1_rwpf.c b/drivers/media/platform/vsp1/vsp1_rwpf.c index 782f770..ec3dab6 100644 --- a/drivers/media/platform/vsp1/vsp1_rwpf.c +++ b/drivers/media/platform/vsp1/vsp1_rwpf.c @@ -1,7 +1,7 @@ /* * vsp1_rwpf.c -- R-Car VSP1 Read and Write Pixel Formatters * - * Copyright (C) 2013 Renesas Corporation + * Copyright (C) 2013-2014 Renesas Electronics Corporation * * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) * diff --git a/drivers/media/platform/vsp1/vsp1_rwpf.h b/drivers/media/platform/vsp1/vsp1_rwpf.h index 6cbdb54..5c5ee81 100644 --- a/drivers/media/platform/vsp1/vsp1_rwpf.h +++ b/drivers/media/platform/vsp1/vsp1_rwpf.h @@ -1,7 +1,7 @@ /* * vsp1_rwpf.h -- R-Car VSP1 Read and Write Pixel Formatters * - * Copyright (C) 2013 Renesas Corporation + * Copyright (C) 2013-2014 Renesas Electronics Corporation * * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) * diff --git a/drivers/media/platform/vsp1/vsp1_uds.c b/drivers/media/platform/vsp1/vsp1_uds.c index 0e50b37..622342a 100644 --- a/drivers/media/platform/vsp1/vsp1_uds.c +++ b/drivers/media/platform/vsp1/vsp1_uds.c @@ -1,7 +1,7 @@ /* * vsp1_uds.c -- R-Car VSP1 Up and Down Scaler * - * Copyright (C) 2013 Renesas Corporation + * Copyright (C) 2013-2014 Renesas Electronics Corporation * * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) * diff --git a/drivers/media/platform/vsp1/vsp1_uds.h b/drivers/media/platform/vsp1/vsp1_uds.h index 972a285..479d12d 100644 --- a/drivers/media/platform/vsp1/vsp1_uds.h +++ b/drivers/media/platform/vsp1/vsp1_uds.h @@ -1,7 +1,7 @@ /* * vsp1_uds.h -- R-Car VSP1 Up and Down Scaler * - * Copyright (C) 2013 Renesas Corporation + * Copyright (C) 2013-2014 Renesas Electronics Corporation * * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) * diff --git a/drivers/media/platform/vsp1/vsp1_video.c b/drivers/media/platform/vsp1/vsp1_video.c index e41f07d..b48f135 100644 --- a/drivers/media/platform/vsp1/vsp1_video.c +++ b/drivers/media/platform/vsp1/vsp1_video.c @@ -1,7 +1,7 @@ /* * vsp1_video.c -- R-Car VSP1 Video Node * - * Copyright (C) 2013 Renesas Corporation + * Copyright (C) 2013-2014 Renesas Electronics Corporation * * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) * diff --git a/drivers/media/platform/vsp1/vsp1_video.h b/drivers/media/platform/vsp1/vsp1_video.h index d8612a3..53e4b37 100644 --- a/drivers/media/platform/vsp1/vsp1_video.h +++ b/drivers/media/platform/vsp1/vsp1_video.h @@ -1,7 +1,7 @@ /* * vsp1_video.h -- R-Car VSP1 Video Node * - * Copyright (C) 2013 Renesas Corporation + * Copyright (C) 2013-2014 Renesas Electronics Corporation * * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) * diff --git a/drivers/media/platform/vsp1/vsp1_wpf.c b/drivers/media/platform/vsp1/vsp1_wpf.c index 7baed81..11a61c6 100644 --- a/drivers/media/platform/vsp1/vsp1_wpf.c +++ b/drivers/media/platform/vsp1/vsp1_wpf.c @@ -1,7 +1,7 @@ /* * vsp1_wpf.c -- R-Car VSP1 Write Pixel Formatter * - * Copyright (C) 2013 Renesas Corporation + * Copyright (C) 2013-2014 Renesas Electronics Corporation * * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) * -- cgit v1.1 From 1c1b8734094551eb4075cf68cf76892498c0da61 Mon Sep 17 00:00:00 2001 From: Jan Vcelak Date: Tue, 25 Feb 2014 21:30:45 -0300 Subject: [media] rtl28xxu: add USB ID for Genius TVGo DVB-T03 0458:707f KYE Systems Corp. (Mouse Systems) TVGo DVB-T03 [RTL2832] The USB dongle uses RTL2832U demodulator and FC0012 tuner. Signed-off-by: Jan Vcelak Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/dvb-usb-v2/rtl28xxu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/media/usb/dvb-usb-v2/rtl28xxu.c b/drivers/media/usb/dvb-usb-v2/rtl28xxu.c index c6ff39e..e9294dc 100644 --- a/drivers/media/usb/dvb-usb-v2/rtl28xxu.c +++ b/drivers/media/usb/dvb-usb-v2/rtl28xxu.c @@ -1444,6 +1444,8 @@ static const struct usb_device_id rtl28xxu_id_table[] = { /* RTL2832P devices: */ { DVB_USB_DEVICE(USB_VID_HANFTEK, 0x0131, &rtl2832u_props, "Astrometa DVB-T2", NULL) }, + { DVB_USB_DEVICE(USB_VID_KYE, 0x707f, + &rtl2832u_props, "Genius TVGo DVB-T03", NULL) }, { } }; MODULE_DEVICE_TABLE(usb, rtl28xxu_id_table); -- cgit v1.1 From c4d28cc79be8f9156fbb76874a84263872ea52b8 Mon Sep 17 00:00:00 2001 From: Masanari Iida Date: Wed, 12 Mar 2014 12:57:22 -0300 Subject: [media] DocBook: Fix typo in xml and template file Fix spelling typo under Documentation/DocBook/media. It is because these files are NOT generated by "make htmldocs", I have to fix the files. [m.chehab@samsung.com: fix a merge conflict] Signed-off-by: Masanari Iida Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/dvbproperty.xml | 2 +- Documentation/DocBook/media/v4l/compat.xml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/DocBook/media/dvb/dvbproperty.xml b/Documentation/DocBook/media/dvb/dvbproperty.xml index a9b15e3..24c22ca 100644 --- a/Documentation/DocBook/media/dvb/dvbproperty.xml +++ b/Documentation/DocBook/media/dvb/dvbproperty.xml @@ -196,7 +196,7 @@ get/set up to 64 properties. The actual meaning of each property is described on 1)For satellital delivery systems, it is measured in kHz. For the other ones, it is measured in Hz. 2)For ISDB-T, the channels are usually transmitted with an offset of 143kHz. - E.g. a valid frequncy could be 474143 kHz. The stepping is bound to the bandwidth of + E.g. a valid frequency could be 474143 kHz. The stepping is bound to the bandwidth of the channel which is 6MHz. 3)As in ISDB-Tsb the channel consists of only one or three segments the diff --git a/Documentation/DocBook/media/v4l/compat.xml b/Documentation/DocBook/media/v4l/compat.xml index e72eaab..eee6f0f 100644 --- a/Documentation/DocBook/media/v4l/compat.xml +++ b/Documentation/DocBook/media/v4l/compat.xml @@ -397,7 +397,7 @@ linkend="control" />. The depth (average number of bits per pixel) of a video image is implied by the selected image -format. V4L2 does not explicitely provide such information assuming +format. V4L2 does not explicitly provide such information assuming applications recognizing the format are aware of the image depth and others need not know. The palette field moved into the &v4l2-pix-format;: -- cgit v1.1 From 982b5ee9a91790c77a5f7637ce48e9be441ddc47 Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Tue, 4 Feb 2014 23:15:22 -0300 Subject: [media] DocBook: document RF tuner bandwidth controls Add documentation for RF tuner bandwidth controls. These controls are used to set filters on tuner signal path. Cc: Hans Verkuil Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/v4l/controls.xml | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/Documentation/DocBook/media/v4l/controls.xml b/Documentation/DocBook/media/v4l/controls.xml index 0340b962..7789215 100644 --- a/Documentation/DocBook/media/v4l/controls.xml +++ b/Documentation/DocBook/media/v4l/controls.xml @@ -5045,6 +5045,25 @@ descriptor. Calling &VIDIOC-QUERYCTRL; for this control will return a description of this control class. + V4L2_CID_RF_TUNER_BANDWIDTH_AUTO  + boolean + + + Enables/disables tuner radio channel +bandwidth configuration. In automatic mode bandwidth configuration is performed +by the driver. + + + V4L2_CID_RF_TUNER_BANDWIDTH  + integer + + + Filter(s) on tuner signal path are used to +filter signal according to receiving party needs. Driver configures filters to +fulfill desired bandwidth requirement. Used when V4L2_CID_RF_TUNER_BANDWIDTH_AUTO is not +set. The range and step are driver-specific. + + V4L2_CID_RF_TUNER_LNA_GAIN_AUTO  boolean -- cgit v1.1 From 30845f73945658f41cbcb354e7b37eaac3872567 Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Wed, 12 Mar 2014 14:53:39 -0300 Subject: [media] v4l: define unit for V4L2_CID_RF_TUNER_BANDWIDTH Use Hertz as a unit for radio channel bandwidth. Cc: Hans Verkuil Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/v4l/controls.xml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/DocBook/media/v4l/controls.xml b/Documentation/DocBook/media/v4l/controls.xml index 7789215..282f0a5 100644 --- a/Documentation/DocBook/media/v4l/controls.xml +++ b/Documentation/DocBook/media/v4l/controls.xml @@ -5061,7 +5061,7 @@ by the driver. Filter(s) on tuner signal path are used to filter signal according to receiving party needs. Driver configures filters to fulfill desired bandwidth requirement. Used when V4L2_CID_RF_TUNER_BANDWIDTH_AUTO is not -set. The range and step are driver-specific. +set. Unit is in Hz. The range and step are driver-specific. V4L2_CID_RF_TUNER_LNA_GAIN_AUTO  -- cgit v1.1 From 3ce569fd7c55ed99c04c4ebc5e49304f29a139bb Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Fri, 31 Jan 2014 23:36:13 -0300 Subject: [media] v4l: add RF tuner channel bandwidth control Modern silicon RF tuners has one or more adjustable filters on signal path, in order to filter noise from desired radio channel. Add channel bandwidth control to tell the driver which is radio channel width we want receive. Filters could be then adjusted by the driver or hardware, using RF frequency and channel bandwidth as a base of filter calculations. On automatic mode (normal mode), bandwidth is calculated from sampling rate or tuning info got from userspace. That new control gives possibility to set manual mode and let user have more control for filters. Cc: Hans Verkuil Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- drivers/media/v4l2-core/v4l2-ctrls.c | 4 ++++ include/uapi/linux/v4l2-controls.h | 2 ++ 2 files changed, 6 insertions(+) diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c index 5c3e8ca..48550b0 100644 --- a/drivers/media/v4l2-core/v4l2-ctrls.c +++ b/drivers/media/v4l2-core/v4l2-ctrls.c @@ -867,6 +867,8 @@ const char *v4l2_ctrl_get_name(u32 id) case V4L2_CID_RF_TUNER_MIXER_GAIN: return "Mixer Gain"; case V4L2_CID_RF_TUNER_IF_GAIN_AUTO: return "IF Gain, Auto"; case V4L2_CID_RF_TUNER_IF_GAIN: return "IF Gain"; + case V4L2_CID_RF_TUNER_BANDWIDTH_AUTO: return "Bandwidth, Auto"; + case V4L2_CID_RF_TUNER_BANDWIDTH: return "Bandwidth"; default: return NULL; } @@ -919,6 +921,7 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, case V4L2_CID_RF_TUNER_LNA_GAIN_AUTO: case V4L2_CID_RF_TUNER_MIXER_GAIN_AUTO: case V4L2_CID_RF_TUNER_IF_GAIN_AUTO: + case V4L2_CID_RF_TUNER_BANDWIDTH_AUTO: *type = V4L2_CTRL_TYPE_BOOLEAN; *min = 0; *max = *step = 1; @@ -1084,6 +1087,7 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, case V4L2_CID_RF_TUNER_LNA_GAIN: case V4L2_CID_RF_TUNER_MIXER_GAIN: case V4L2_CID_RF_TUNER_IF_GAIN: + case V4L2_CID_RF_TUNER_BANDWIDTH: *flags |= V4L2_CTRL_FLAG_SLIDER; break; case V4L2_CID_PAN_RELATIVE: diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h index 6501c0b..60a626c 100644 --- a/include/uapi/linux/v4l2-controls.h +++ b/include/uapi/linux/v4l2-controls.h @@ -910,5 +910,7 @@ enum v4l2_deemphasis { #define V4L2_CID_RF_TUNER_MIXER_GAIN (V4L2_CID_RF_TUNER_CLASS_BASE + 4) #define V4L2_CID_RF_TUNER_IF_GAIN_AUTO (V4L2_CID_RF_TUNER_CLASS_BASE + 5) #define V4L2_CID_RF_TUNER_IF_GAIN (V4L2_CID_RF_TUNER_CLASS_BASE + 6) +#define V4L2_CID_RF_TUNER_BANDWIDTH_AUTO (V4L2_CID_RF_TUNER_CLASS_BASE + 7) +#define V4L2_CID_RF_TUNER_BANDWIDTH (V4L2_CID_RF_TUNER_CLASS_BASE + 8) #endif -- cgit v1.1 From 835b87c7adecef13bbc2a32c8e8437201144e9c4 Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Tue, 4 Feb 2014 22:13:44 -0300 Subject: [media] v4l: reorganize RF tuner control ID numbers It appears that controls are ordered by ID number when enumerating. That could lead illogical UI as controls are usually enumerated and drawn by the application at runtime. Change order of controls by reorganizing assigned IDs now as we can. It is not reasonable possible after the API is released. Also, leave some spare space between IDs too for possible future extensions. Cc: Hans Verkuil Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- include/uapi/linux/v4l2-controls.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h index 60a626c..405279f 100644 --- a/include/uapi/linux/v4l2-controls.h +++ b/include/uapi/linux/v4l2-controls.h @@ -904,13 +904,13 @@ enum v4l2_deemphasis { #define V4L2_CID_RF_TUNER_CLASS_BASE (V4L2_CTRL_CLASS_RF_TUNER | 0x900) #define V4L2_CID_RF_TUNER_CLASS (V4L2_CTRL_CLASS_RF_TUNER | 1) -#define V4L2_CID_RF_TUNER_LNA_GAIN_AUTO (V4L2_CID_RF_TUNER_CLASS_BASE + 1) -#define V4L2_CID_RF_TUNER_LNA_GAIN (V4L2_CID_RF_TUNER_CLASS_BASE + 2) -#define V4L2_CID_RF_TUNER_MIXER_GAIN_AUTO (V4L2_CID_RF_TUNER_CLASS_BASE + 3) -#define V4L2_CID_RF_TUNER_MIXER_GAIN (V4L2_CID_RF_TUNER_CLASS_BASE + 4) -#define V4L2_CID_RF_TUNER_IF_GAIN_AUTO (V4L2_CID_RF_TUNER_CLASS_BASE + 5) -#define V4L2_CID_RF_TUNER_IF_GAIN (V4L2_CID_RF_TUNER_CLASS_BASE + 6) -#define V4L2_CID_RF_TUNER_BANDWIDTH_AUTO (V4L2_CID_RF_TUNER_CLASS_BASE + 7) -#define V4L2_CID_RF_TUNER_BANDWIDTH (V4L2_CID_RF_TUNER_CLASS_BASE + 8) +#define V4L2_CID_RF_TUNER_BANDWIDTH_AUTO (V4L2_CID_RF_TUNER_CLASS_BASE + 11) +#define V4L2_CID_RF_TUNER_BANDWIDTH (V4L2_CID_RF_TUNER_CLASS_BASE + 12) +#define V4L2_CID_RF_TUNER_LNA_GAIN_AUTO (V4L2_CID_RF_TUNER_CLASS_BASE + 41) +#define V4L2_CID_RF_TUNER_LNA_GAIN (V4L2_CID_RF_TUNER_CLASS_BASE + 42) +#define V4L2_CID_RF_TUNER_MIXER_GAIN_AUTO (V4L2_CID_RF_TUNER_CLASS_BASE + 51) +#define V4L2_CID_RF_TUNER_MIXER_GAIN (V4L2_CID_RF_TUNER_CLASS_BASE + 52) +#define V4L2_CID_RF_TUNER_IF_GAIN_AUTO (V4L2_CID_RF_TUNER_CLASS_BASE + 61) +#define V4L2_CID_RF_TUNER_IF_GAIN (V4L2_CID_RF_TUNER_CLASS_BASE + 62) #endif -- cgit v1.1 From 8dfe644bf6c696b0f24d57f87fe25aea6cecb96a Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Wed, 26 Feb 2014 20:30:35 -0300 Subject: [media] DocBook: media: add some general info about RF tuners Add some info what is RF tuner in context of V4L RF tuner class. Cc: Hans Verkuil Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/v4l/controls.xml | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/Documentation/DocBook/media/v4l/controls.xml b/Documentation/DocBook/media/v4l/controls.xml index 282f0a5..8c62ead 100644 --- a/Documentation/DocBook/media/v4l/controls.xml +++ b/Documentation/DocBook/media/v4l/controls.xml @@ -5013,8 +5013,27 @@ defines possible values for de-emphasis. Here they are:
RF Tuner Control Reference - The RF Tuner (RF_TUNER) class includes controls for common features -of devices having RF tuner. + +The RF Tuner (RF_TUNER) class includes controls for common features of devices +having RF tuner. + + +In this context, RF tuner is radio receiver circuit between antenna and +demodulator. It receives radio frequency (RF) from the antenna and converts that +received signal to lower intermediate frequency (IF) or baseband frequency (BB). +Tuners that could do baseband output are often called Zero-IF tuners. Older +tuners were typically simple PLL tuners inside a metal box, whilst newer ones +are highly integrated chips without a metal box "silicon tuners". These controls +are mostly applicable for new feature rich silicon tuners, just because older +tuners does not have much adjustable features. + + +For more information about RF tuners see +Tuner (radio) +and +RF front end +from Wikipedia. + RF_TUNER Control IDs -- cgit v1.1 From 0a670c42f26de8e65f4e61130bfb84ae1488d8c9 Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Thu, 30 Jan 2014 23:44:59 -0300 Subject: [media] DocBook: V4L: add V4L2_SDR_FMT_CU8 - 'CU08' Document V4L2_SDR_FMT_CU8 SDR format. It is complex unsigned 8-bit IQ sample. Used by software defined radio devices. Cc: Hans Verkuil Signed-off-by: Antti Palosaari Acked-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- .../DocBook/media/v4l/pixfmt-sdr-cu08.xml | 44 ++++++++++++++++++++++ Documentation/DocBook/media/v4l/pixfmt.xml | 2 + 2 files changed, 46 insertions(+) create mode 100644 Documentation/DocBook/media/v4l/pixfmt-sdr-cu08.xml diff --git a/Documentation/DocBook/media/v4l/pixfmt-sdr-cu08.xml b/Documentation/DocBook/media/v4l/pixfmt-sdr-cu08.xml new file mode 100644 index 0000000..2d80104 --- /dev/null +++ b/Documentation/DocBook/media/v4l/pixfmt-sdr-cu08.xml @@ -0,0 +1,44 @@ + + + V4L2_SDR_FMT_CU8 ('CU08') + &manvol; + + + + V4L2_SDR_FMT_CU8 + + Complex unsigned 8-bit IQ sample + + + Description + +This format contains sequence of complex number samples. Each complex number +consist two parts, called In-phase and Quadrature (IQ). Both I and Q are +represented as a 8 bit unsigned number. I value comes first and Q value after +that. + + + <constant>V4L2_SDR_FMT_CU8</constant> 1 sample + + Byte Order. + Each cell is one byte. + + + + + + start + 0: + I'0 + + + start + 1: + Q'0 + + + + + + + + + diff --git a/Documentation/DocBook/media/v4l/pixfmt.xml b/Documentation/DocBook/media/v4l/pixfmt.xml index f586d34..40adcb8 100644 --- a/Documentation/DocBook/media/v4l/pixfmt.xml +++ b/Documentation/DocBook/media/v4l/pixfmt.xml @@ -817,6 +817,8 @@ extended control V4L2_CID_MPEG_STREAM_TYPE, see These formats are used for SDR Capture interface only. + &sub-sdr-cu08; +
-- cgit v1.1 From e6001abcc559738934015da56bbbf7615d076d8e Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Fri, 31 Jan 2014 00:29:46 -0300 Subject: [media] DocBook: V4L: add V4L2_SDR_FMT_CU16LE - 'CU16' Document V4L2_SDR_FMT_CU16LE format. It is complex unsigned 16-bit little endian IQ sample. Used by software defined radio devices. Cc: Hans Verkuil Signed-off-by: Antti Palosaari Acked-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- .../DocBook/media/v4l/pixfmt-sdr-cu16le.xml | 46 ++++++++++++++++++++++ Documentation/DocBook/media/v4l/pixfmt.xml | 1 + 2 files changed, 47 insertions(+) create mode 100644 Documentation/DocBook/media/v4l/pixfmt-sdr-cu16le.xml diff --git a/Documentation/DocBook/media/v4l/pixfmt-sdr-cu16le.xml b/Documentation/DocBook/media/v4l/pixfmt-sdr-cu16le.xml new file mode 100644 index 0000000..26288ff --- /dev/null +++ b/Documentation/DocBook/media/v4l/pixfmt-sdr-cu16le.xml @@ -0,0 +1,46 @@ + + + V4L2_SDR_FMT_CU16LE ('CU16') + &manvol; + + + + V4L2_SDR_FMT_CU16LE + + Complex unsigned 16-bit little endian IQ sample + + + Description + +This format contains sequence of complex number samples. Each complex number +consist two parts, called In-phase and Quadrature (IQ). Both I and Q are +represented as a 16 bit unsigned little endian number. I value comes first +and Q value after that. + + + <constant>V4L2_SDR_FMT_CU16LE</constant> 1 sample + + Byte Order. + Each cell is one byte. + + + +
+ + start + 0: + I'0[7:0] + I'0[15:8] + + + start + 2: + Q'0[7:0] + Q'0[15:8] + + + + + + + + + diff --git a/Documentation/DocBook/media/v4l/pixfmt.xml b/Documentation/DocBook/media/v4l/pixfmt.xml index 40adcb8..f535d9b 100644 --- a/Documentation/DocBook/media/v4l/pixfmt.xml +++ b/Documentation/DocBook/media/v4l/pixfmt.xml @@ -818,6 +818,7 @@ extended control V4L2_CID_MPEG_STREAM_TYPE, see interface only. &sub-sdr-cu08; + &sub-sdr-cu16le; -- cgit v1.1 From 00419a6ab590b6cf584f704abbb56b7a5c388672 Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Tue, 4 Feb 2014 23:55:25 -0300 Subject: [media] v4l: uapi: add SDR formats CU8 and CU16LE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit V4L2_SDR_FMT_CU8 — Complex unsigned 8-bit IQ sample V4L2_SDR_FMT_CU16LE — Complex unsigned 16-bit little endian IQ sample Cc: Hans Verkuil Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- include/uapi/linux/videodev2.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h index 339738a..35f4a06 100644 --- a/include/uapi/linux/videodev2.h +++ b/include/uapi/linux/videodev2.h @@ -436,6 +436,10 @@ struct v4l2_pix_format { #define V4L2_PIX_FMT_SE401 v4l2_fourcc('S', '4', '0', '1') /* se401 janggu compressed rgb */ #define V4L2_PIX_FMT_S5C_UYVY_JPG v4l2_fourcc('S', '5', 'C', 'I') /* S5C73M3 interleaved UYVY/JPEG */ +/* SDR formats - used only for Software Defined Radio devices */ +#define V4L2_SDR_FMT_CU8 v4l2_fourcc('C', 'U', '0', '8') /* IQ u8 */ +#define V4L2_SDR_FMT_CU16LE v4l2_fourcc('C', 'U', '1', '6') /* IQ u16le */ + /* * F O R M A T E N U M E R A T I O N */ -- cgit v1.1 From c58d1de5d94eee930d151f36cb6f63a30c6bf2bb Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Wed, 5 Feb 2014 02:24:35 -0300 Subject: [media] v4l: add enum_freq_bands support to tuner sub-device Add VIDIOC_ENUM_FREQ_BANDS, enumerate supported frequency bands, IOCTL support for sub-device tuners too. Cc: Hans Verkuil Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- include/media/v4l2-subdev.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/media/v4l2-subdev.h b/include/media/v4l2-subdev.h index 855c928..28f4d8c 100644 --- a/include/media/v4l2-subdev.h +++ b/include/media/v4l2-subdev.h @@ -196,6 +196,7 @@ struct v4l2_subdev_tuner_ops { int (*s_radio)(struct v4l2_subdev *sd); int (*s_frequency)(struct v4l2_subdev *sd, const struct v4l2_frequency *freq); int (*g_frequency)(struct v4l2_subdev *sd, struct v4l2_frequency *freq); + int (*enum_freq_bands)(struct v4l2_subdev *sd, struct v4l2_frequency_band *band); int (*g_tuner)(struct v4l2_subdev *sd, struct v4l2_tuner *vt); int (*s_tuner)(struct v4l2_subdev *sd, const struct v4l2_tuner *vt); int (*g_modulator)(struct v4l2_subdev *sd, struct v4l2_modulator *vm); -- cgit v1.1 From de1dd3e9cff0f764f6244b515fe2a6ea15f9cfde Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Fri, 7 Feb 2014 03:55:32 -0300 Subject: [media] DocBook: media: document PLL lock control Document PLL lock V4L2 control. It is read only RF tuner control which is used to inform if tuner is receiving frequency or not. Cc: Hans Verkuil Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/v4l/controls.xml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/DocBook/media/v4l/controls.xml b/Documentation/DocBook/media/v4l/controls.xml index 8c62ead..47198ee 100644 --- a/Documentation/DocBook/media/v4l/controls.xml +++ b/Documentation/DocBook/media/v4l/controls.xml @@ -5134,6 +5134,15 @@ intermediate frequency output or baseband output. Used when V4L2_CID_RF_TUNER_IF_GAIN_AUTO is not set. The range and step are driver-specific. + + V4L2_CID_RF_TUNER_PLL_LOCK  + boolean + + + Is synthesizer PLL locked? RF tuner is +receiving given frequency when that control is set. This is a read-only control. + +
-- cgit v1.1 From 9aa4357e9b10b92acb85e30834f8eb4aa7b94554 Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Fri, 7 Feb 2014 02:46:16 -0300 Subject: [media] v4l: add control for RF tuner PLL lock flag Add volatile boolean control to indicate if tuner frequency synthesizer is locked to requested frequency. That means tuner is able to receive given frequency. Control is named as "PLL lock", since frequency synthesizers are based of phase-locked-loop. Maybe more general name could be wise still? Cc: Hans Verkuil Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- drivers/media/v4l2-core/v4l2-ctrls.c | 5 +++++ include/uapi/linux/v4l2-controls.h | 1 + 2 files changed, 6 insertions(+) diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c index 48550b0..55c6832 100644 --- a/drivers/media/v4l2-core/v4l2-ctrls.c +++ b/drivers/media/v4l2-core/v4l2-ctrls.c @@ -869,6 +869,7 @@ const char *v4l2_ctrl_get_name(u32 id) case V4L2_CID_RF_TUNER_IF_GAIN: return "IF Gain"; case V4L2_CID_RF_TUNER_BANDWIDTH_AUTO: return "Bandwidth, Auto"; case V4L2_CID_RF_TUNER_BANDWIDTH: return "Bandwidth"; + case V4L2_CID_RF_TUNER_PLL_LOCK: return "PLL Lock"; default: return NULL; } @@ -922,6 +923,7 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, case V4L2_CID_RF_TUNER_MIXER_GAIN_AUTO: case V4L2_CID_RF_TUNER_IF_GAIN_AUTO: case V4L2_CID_RF_TUNER_BANDWIDTH_AUTO: + case V4L2_CID_RF_TUNER_PLL_LOCK: *type = V4L2_CTRL_TYPE_BOOLEAN; *min = 0; *max = *step = 1; @@ -1106,6 +1108,9 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, case V4L2_CID_DV_RX_POWER_PRESENT: *flags |= V4L2_CTRL_FLAG_READ_ONLY; break; + case V4L2_CID_RF_TUNER_PLL_LOCK: + *flags |= V4L2_CTRL_FLAG_VOLATILE; + break; } } EXPORT_SYMBOL(v4l2_ctrl_fill); diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h index 405279f..2ac5597 100644 --- a/include/uapi/linux/v4l2-controls.h +++ b/include/uapi/linux/v4l2-controls.h @@ -912,5 +912,6 @@ enum v4l2_deemphasis { #define V4L2_CID_RF_TUNER_MIXER_GAIN (V4L2_CID_RF_TUNER_CLASS_BASE + 52) #define V4L2_CID_RF_TUNER_IF_GAIN_AUTO (V4L2_CID_RF_TUNER_CLASS_BASE + 61) #define V4L2_CID_RF_TUNER_IF_GAIN (V4L2_CID_RF_TUNER_CLASS_BASE + 62) +#define V4L2_CID_RF_TUNER_PLL_LOCK (V4L2_CID_RF_TUNER_CLASS_BASE + 91) #endif -- cgit v1.1 From 3d0c8fa3c5a0f9ffc4c3e8b4625ddeb875aee50b Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Sun, 17 Nov 2013 03:04:51 -0300 Subject: [media] msi3101: convert to SDR API Massive rewrite. Use SDR API. Fix bugs. Signed-off-by: Antti Palosaari Acked-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/staging/media/msi3101/sdr-msi3101.c | 1351 ++++++++++++--------------- 1 file changed, 573 insertions(+), 778 deletions(-) diff --git a/drivers/staging/media/msi3101/sdr-msi3101.c b/drivers/staging/media/msi3101/sdr-msi3101.c index 04ff29e..cf71e7e 100644 --- a/drivers/staging/media/msi3101/sdr-msi3101.c +++ b/drivers/staging/media/msi3101/sdr-msi3101.c @@ -21,20 +21,6 @@ * (C) 1999-2004 Nemosoft Unv. * (C) 2004-2006 Luc Saillard (luc@saillard.org) * (C) 2011 Hans de Goede - * - * Development tree of that driver will be on: - * http://git.linuxtv.org/anttip/media_tree.git/shortlog/refs/heads/mirics - * - * GNU Radio plugin "gr-kernel" for device usage will be on: - * http://git.linuxtv.org/anttip/gr-kernel.git - * - * TODO: - * Help is very highly welcome for these + all the others you could imagine: - * - split USB ADC interface and RF tuner to own drivers (msi2500 and msi001) - * - move controls to V4L2 API - * - use libv4l2 for stream format conversions - * - gr-kernel: switch to v4l2_mmap (current read eats a lot of cpu) - * - SDRSharp support */ #include @@ -48,317 +34,6 @@ #include #include -struct msi3101_gain { - u8 tot:7; - u8 baseband:6; - bool lna:1; - bool mixer:1; -}; - -/* 60 – 120 MHz band, lna 24dB, mixer 19dB */ -static const struct msi3101_gain msi3101_gain_lut_120[] = { - { 0, 0, 0, 0}, - { 1, 1, 0, 0}, - { 2, 2, 0, 0}, - { 3, 3, 0, 0}, - { 4, 4, 0, 0}, - { 5, 5, 0, 0}, - { 6, 6, 0, 0}, - { 7, 7, 0, 0}, - { 8, 8, 0, 0}, - { 9, 9, 0, 0}, - { 10, 10, 0, 0}, - { 11, 11, 0, 0}, - { 12, 12, 0, 0}, - { 13, 13, 0, 0}, - { 14, 14, 0, 0}, - { 15, 15, 0, 0}, - { 16, 16, 0, 0}, - { 17, 17, 0, 0}, - { 18, 18, 0, 0}, - { 19, 19, 0, 0}, - { 20, 20, 0, 0}, - { 21, 21, 0, 0}, - { 22, 22, 0, 0}, - { 23, 23, 0, 0}, - { 24, 24, 0, 0}, - { 25, 25, 0, 0}, - { 26, 26, 0, 0}, - { 27, 27, 0, 0}, - { 28, 28, 0, 0}, - { 29, 5, 1, 0}, - { 30, 6, 1, 0}, - { 31, 7, 1, 0}, - { 32, 8, 1, 0}, - { 33, 9, 1, 0}, - { 34, 10, 1, 0}, - { 35, 11, 1, 0}, - { 36, 12, 1, 0}, - { 37, 13, 1, 0}, - { 38, 14, 1, 0}, - { 39, 15, 1, 0}, - { 40, 16, 1, 0}, - { 41, 17, 1, 0}, - { 42, 18, 1, 0}, - { 43, 19, 1, 0}, - { 44, 20, 1, 0}, - { 45, 21, 1, 0}, - { 46, 22, 1, 0}, - { 47, 23, 1, 0}, - { 48, 24, 1, 0}, - { 49, 25, 1, 0}, - { 50, 26, 1, 0}, - { 51, 27, 1, 0}, - { 52, 28, 1, 0}, - { 53, 29, 1, 0}, - { 54, 30, 1, 0}, - { 55, 31, 1, 0}, - { 56, 32, 1, 0}, - { 57, 33, 1, 0}, - { 58, 34, 1, 0}, - { 59, 35, 1, 0}, - { 60, 36, 1, 0}, - { 61, 37, 1, 0}, - { 62, 38, 1, 0}, - { 63, 39, 1, 0}, - { 64, 40, 1, 0}, - { 65, 41, 1, 0}, - { 66, 42, 1, 0}, - { 67, 43, 1, 0}, - { 68, 44, 1, 0}, - { 69, 45, 1, 0}, - { 70, 46, 1, 0}, - { 71, 47, 1, 0}, - { 72, 48, 1, 0}, - { 73, 49, 1, 0}, - { 74, 50, 1, 0}, - { 75, 51, 1, 0}, - { 76, 52, 1, 0}, - { 77, 53, 1, 0}, - { 78, 54, 1, 0}, - { 79, 55, 1, 0}, - { 80, 56, 1, 0}, - { 81, 57, 1, 0}, - { 82, 58, 1, 0}, - { 83, 40, 1, 1}, - { 84, 41, 1, 1}, - { 85, 42, 1, 1}, - { 86, 43, 1, 1}, - { 87, 44, 1, 1}, - { 88, 45, 1, 1}, - { 89, 46, 1, 1}, - { 90, 47, 1, 1}, - { 91, 48, 1, 1}, - { 92, 49, 1, 1}, - { 93, 50, 1, 1}, - { 94, 51, 1, 1}, - { 95, 52, 1, 1}, - { 96, 53, 1, 1}, - { 97, 54, 1, 1}, - { 98, 55, 1, 1}, - { 99, 56, 1, 1}, - {100, 57, 1, 1}, - {101, 58, 1, 1}, - {102, 59, 1, 1}, -}; - -/* 120 – 245 MHz band, lna 24dB, mixer 19dB */ -static const struct msi3101_gain msi3101_gain_lut_245[] = { - { 0, 0, 0, 0}, - { 1, 1, 0, 0}, - { 2, 2, 0, 0}, - { 3, 3, 0, 0}, - { 4, 4, 0, 0}, - { 5, 5, 0, 0}, - { 6, 6, 0, 0}, - { 7, 7, 0, 0}, - { 8, 8, 0, 0}, - { 9, 9, 0, 0}, - { 10, 10, 0, 0}, - { 11, 11, 0, 0}, - { 12, 12, 0, 0}, - { 13, 13, 0, 0}, - { 14, 14, 0, 0}, - { 15, 15, 0, 0}, - { 16, 16, 0, 0}, - { 17, 17, 0, 0}, - { 18, 18, 0, 0}, - { 19, 19, 0, 0}, - { 20, 20, 0, 0}, - { 21, 21, 0, 0}, - { 22, 22, 0, 0}, - { 23, 23, 0, 0}, - { 24, 24, 0, 0}, - { 25, 25, 0, 0}, - { 26, 26, 0, 0}, - { 27, 27, 0, 0}, - { 28, 28, 0, 0}, - { 29, 5, 1, 0}, - { 30, 6, 1, 0}, - { 31, 7, 1, 0}, - { 32, 8, 1, 0}, - { 33, 9, 1, 0}, - { 34, 10, 1, 0}, - { 35, 11, 1, 0}, - { 36, 12, 1, 0}, - { 37, 13, 1, 0}, - { 38, 14, 1, 0}, - { 39, 15, 1, 0}, - { 40, 16, 1, 0}, - { 41, 17, 1, 0}, - { 42, 18, 1, 0}, - { 43, 19, 1, 0}, - { 44, 20, 1, 0}, - { 45, 21, 1, 0}, - { 46, 22, 1, 0}, - { 47, 23, 1, 0}, - { 48, 24, 1, 0}, - { 49, 25, 1, 0}, - { 50, 26, 1, 0}, - { 51, 27, 1, 0}, - { 52, 28, 1, 0}, - { 53, 29, 1, 0}, - { 54, 30, 1, 0}, - { 55, 31, 1, 0}, - { 56, 32, 1, 0}, - { 57, 33, 1, 0}, - { 58, 34, 1, 0}, - { 59, 35, 1, 0}, - { 60, 36, 1, 0}, - { 61, 37, 1, 0}, - { 62, 38, 1, 0}, - { 63, 39, 1, 0}, - { 64, 40, 1, 0}, - { 65, 41, 1, 0}, - { 66, 42, 1, 0}, - { 67, 43, 1, 0}, - { 68, 44, 1, 0}, - { 69, 45, 1, 0}, - { 70, 46, 1, 0}, - { 71, 47, 1, 0}, - { 72, 48, 1, 0}, - { 73, 49, 1, 0}, - { 74, 50, 1, 0}, - { 75, 51, 1, 0}, - { 76, 52, 1, 0}, - { 77, 53, 1, 0}, - { 78, 54, 1, 0}, - { 79, 55, 1, 0}, - { 80, 56, 1, 0}, - { 81, 57, 1, 0}, - { 82, 58, 1, 0}, - { 83, 40, 1, 1}, - { 84, 41, 1, 1}, - { 85, 42, 1, 1}, - { 86, 43, 1, 1}, - { 87, 44, 1, 1}, - { 88, 45, 1, 1}, - { 89, 46, 1, 1}, - { 90, 47, 1, 1}, - { 91, 48, 1, 1}, - { 92, 49, 1, 1}, - { 93, 50, 1, 1}, - { 94, 51, 1, 1}, - { 95, 52, 1, 1}, - { 96, 53, 1, 1}, - { 97, 54, 1, 1}, - { 98, 55, 1, 1}, - { 99, 56, 1, 1}, - {100, 57, 1, 1}, - {101, 58, 1, 1}, - {102, 59, 1, 1}, -}; - -/* 420 – 1000 MHz band, lna 7dB, mixer 19dB */ -static const struct msi3101_gain msi3101_gain_lut_1000[] = { - { 0, 0, 0, 0}, - { 1, 1, 0, 0}, - { 2, 2, 0, 0}, - { 3, 3, 0, 0}, - { 4, 4, 0, 0}, - { 5, 5, 0, 0}, - { 6, 6, 0, 0}, - { 7, 7, 0, 0}, - { 8, 8, 0, 0}, - { 9, 9, 0, 0}, - { 10, 10, 0, 0}, - { 11, 11, 0, 0}, - { 12, 5, 1, 0}, - { 13, 6, 1, 0}, - { 14, 7, 1, 0}, - { 15, 8, 1, 0}, - { 16, 9, 1, 0}, - { 17, 10, 1, 0}, - { 18, 11, 1, 0}, - { 19, 12, 1, 0}, - { 20, 13, 1, 0}, - { 21, 14, 1, 0}, - { 22, 15, 1, 0}, - { 23, 16, 1, 0}, - { 24, 17, 1, 0}, - { 25, 18, 1, 0}, - { 26, 19, 1, 0}, - { 27, 20, 1, 0}, - { 28, 21, 1, 0}, - { 29, 22, 1, 0}, - { 30, 23, 1, 0}, - { 31, 24, 1, 0}, - { 32, 25, 1, 0}, - { 33, 26, 1, 0}, - { 34, 27, 1, 0}, - { 35, 28, 1, 0}, - { 36, 29, 1, 0}, - { 37, 30, 1, 0}, - { 38, 31, 1, 0}, - { 39, 32, 1, 0}, - { 40, 33, 1, 0}, - { 41, 34, 1, 0}, - { 42, 35, 1, 0}, - { 43, 36, 1, 0}, - { 44, 37, 1, 0}, - { 45, 38, 1, 0}, - { 46, 39, 1, 0}, - { 47, 40, 1, 0}, - { 48, 41, 1, 0}, - { 49, 42, 1, 0}, - { 50, 43, 1, 0}, - { 51, 44, 1, 0}, - { 52, 45, 1, 0}, - { 53, 46, 1, 0}, - { 54, 47, 1, 0}, - { 55, 48, 1, 0}, - { 56, 49, 1, 0}, - { 57, 50, 1, 0}, - { 58, 51, 1, 0}, - { 59, 52, 1, 0}, - { 60, 53, 1, 0}, - { 61, 54, 1, 0}, - { 62, 55, 1, 0}, - { 63, 56, 1, 0}, - { 64, 57, 1, 0}, - { 65, 58, 1, 0}, - { 66, 40, 1, 1}, - { 67, 41, 1, 1}, - { 68, 42, 1, 1}, - { 69, 43, 1, 1}, - { 70, 44, 1, 1}, - { 71, 45, 1, 1}, - { 72, 46, 1, 1}, - { 73, 47, 1, 1}, - { 74, 48, 1, 1}, - { 75, 49, 1, 1}, - { 76, 50, 1, 1}, - { 77, 51, 1, 1}, - { 78, 52, 1, 1}, - { 79, 53, 1, 1}, - { 80, 54, 1, 1}, - { 81, 55, 1, 1}, - { 82, 56, 1, 1}, - { 83, 57, 1, 1}, - { 84, 58, 1, 1}, - { 85, 59, 1, 1}, -}; - /* * iConfiguration 0 * bInterfaceNumber 0 @@ -377,13 +52,72 @@ static const struct msi3101_gain msi3101_gain_lut_1000[] = { #define MAX_ISOC_ERRORS 20 /* TODO: These should be moved to V4L2 API */ -#define MSI3101_CID_SAMPLING_MODE ((V4L2_CID_USER_BASE | 0xf000) + 0) -#define MSI3101_CID_SAMPLING_RATE ((V4L2_CID_USER_BASE | 0xf000) + 1) -#define MSI3101_CID_SAMPLING_RESOLUTION ((V4L2_CID_USER_BASE | 0xf000) + 2) -#define MSI3101_CID_TUNER_RF ((V4L2_CID_USER_BASE | 0xf000) + 10) -#define MSI3101_CID_TUNER_BW ((V4L2_CID_USER_BASE | 0xf000) + 11) -#define MSI3101_CID_TUNER_IF ((V4L2_CID_USER_BASE | 0xf000) + 12) -#define MSI3101_CID_TUNER_GAIN ((V4L2_CID_USER_BASE | 0xf000) + 13) +#define V4L2_PIX_FMT_SDR_S8 v4l2_fourcc('D', 'S', '0', '8') /* signed 8-bit */ +#define V4L2_PIX_FMT_SDR_S12 v4l2_fourcc('D', 'S', '1', '2') /* signed 12-bit */ +#define V4L2_PIX_FMT_SDR_S14 v4l2_fourcc('D', 'S', '1', '4') /* signed 14-bit */ +#define V4L2_PIX_FMT_SDR_MSI2500_384 v4l2_fourcc('M', '3', '8', '4') /* Mirics MSi2500 format 384 */ + +static const struct v4l2_frequency_band bands_adc[] = { + { + .tuner = 0, + .type = V4L2_TUNER_ADC, + .index = 0, + .capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS, + .rangelow = 1200000, + .rangehigh = 15000000, + }, +}; + +static const struct v4l2_frequency_band bands_rf[] = { + { + .tuner = 1, + .type = V4L2_TUNER_RF, + .index = 0, + .capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS, + .rangelow = 49000000, + .rangehigh = 263000000, + }, { + .tuner = 1, + .type = V4L2_TUNER_RF, + .index = 1, + .capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS, + .rangelow = 390000000, + .rangehigh = 960000000, + }, +}; + +/* stream formats */ +struct msi3101_format { + char *name; + u32 pixelformat; +}; + +/* format descriptions for capture and preview */ +static struct msi3101_format formats[] = { + { + .name = "IQ U8", + .pixelformat = V4L2_SDR_FMT_CU8, + }, { + .name = "IQ U16LE", + .pixelformat = V4L2_SDR_FMT_CU16LE, +#if 0 + }, { + .name = "8-bit signed", + .pixelformat = V4L2_PIX_FMT_SDR_S8, + }, { + .name = "10+2-bit signed", + .pixelformat = V4L2_PIX_FMT_SDR_MSI2500_384, + }, { + .name = "12-bit signed", + .pixelformat = V4L2_PIX_FMT_SDR_S12, + }, { + .name = "14-bit signed", + .pixelformat = V4L2_PIX_FMT_SDR_S14, +#endif + }, +}; + +static const unsigned int NUM_FORMATS = ARRAY_SIZE(formats); /* intermediate buffers with raw data from the USB device */ struct msi3101_frame_buf { @@ -407,24 +141,30 @@ struct msi3101_state { /* Pointer to our usb_device, will be NULL after unplug */ struct usb_device *udev; /* Both mutexes most be hold when setting! */ + unsigned int f_adc, f_tuner; + u32 pixelformat; + unsigned int isoc_errors; /* number of contiguous ISOC errors */ unsigned int vb_full; /* vb is full and packets dropped */ struct urb *urbs[MAX_ISO_BUFS]; - int (*convert_stream) (struct msi3101_state *s, u32 *dst, u8 *src, + int (*convert_stream) (struct msi3101_state *s, u8 *dst, u8 *src, unsigned int src_len); /* Controls */ - struct v4l2_ctrl_handler ctrl_handler; - struct v4l2_ctrl *ctrl_sampling_rate; - struct v4l2_ctrl *ctrl_tuner_rf; - struct v4l2_ctrl *ctrl_tuner_bw; - struct v4l2_ctrl *ctrl_tuner_if; - struct v4l2_ctrl *ctrl_tuner_gain; + struct v4l2_ctrl_handler hdl; + struct v4l2_ctrl *bandwidth_auto; + struct v4l2_ctrl *bandwidth; + struct v4l2_ctrl *lna_gain_auto; + struct v4l2_ctrl *lna_gain; + struct v4l2_ctrl *mixer_gain_auto; + struct v4l2_ctrl *mixer_gain; + struct v4l2_ctrl *if_gain_auto; + struct v4l2_ctrl *if_gain; u32 next_sample; /* for track lost packets */ u32 sample; /* for sample rate calc */ - unsigned long jiffies; + unsigned long jiffies_next; unsigned int sample_ctrl_bit[4]; }; @@ -448,98 +188,79 @@ leave: /* * +=========================================================================== - * | 00-1023 | USB packet type '384' + * | 00-1023 | USB packet type '504' * +=========================================================================== * | 00- 03 | sequence number of first sample in that USB packet * +--------------------------------------------------------------------------- * | 04- 15 | garbage * +--------------------------------------------------------------------------- - * | 16- 175 | samples - * +--------------------------------------------------------------------------- - * | 176- 179 | control bits for previous samples - * +--------------------------------------------------------------------------- - * | 180- 339 | samples - * +--------------------------------------------------------------------------- - * | 340- 343 | control bits for previous samples - * +--------------------------------------------------------------------------- - * | 344- 503 | samples - * +--------------------------------------------------------------------------- - * | 504- 507 | control bits for previous samples - * +--------------------------------------------------------------------------- - * | 508- 667 | samples - * +--------------------------------------------------------------------------- - * | 668- 671 | control bits for previous samples - * +--------------------------------------------------------------------------- - * | 672- 831 | samples - * +--------------------------------------------------------------------------- - * | 832- 835 | control bits for previous samples - * +--------------------------------------------------------------------------- - * | 836- 995 | samples - * +--------------------------------------------------------------------------- - * | 996- 999 | control bits for previous samples - * +--------------------------------------------------------------------------- - * | 1000-1023 | garbage + * | 16-1023 | samples * +--------------------------------------------------------------------------- - * - * Bytes 4 - 7 could have some meaning? - * - * Control bits for previous samples is 32-bit field, containing 16 x 2-bit - * numbers. This results one 2-bit number for 8 samples. It is likely used for - * for bit shifting sample by given bits, increasing actual sampling resolution. - * Number 2 (0b10) was never seen. - * - * 6 * 16 * 2 * 4 = 768 samples. 768 * 4 = 3072 bytes + * signed 8-bit sample + * 504 * 2 = 1008 samples */ +static int msi3101_convert_stream_504(struct msi3101_state *s, u8 *dst, + u8 *src, unsigned int src_len) +{ + int i, i_max, dst_len = 0; + u32 sample_num[3]; -/* - * Integer to 32-bit IEEE floating point representation routine is taken - * from Radeon R600 driver (drivers/gpu/drm/radeon/r600_blit_kms.c). - * - * TODO: Currently we do conversion here in Kernel, but in future that will - * be moved to the libv4l2 library as video format conversions are. - */ -#define I2F_FRAC_BITS 23 -#define I2F_MASK ((1 << I2F_FRAC_BITS) - 1) + /* There could be 1-3 1024 bytes URB frames */ + i_max = src_len / 1024; -/* - * Converts signed 8-bit integer into 32-bit IEEE floating point - * representation. - */ -static u32 msi3101_convert_sample_504(struct msi3101_state *s, u16 x) -{ - u32 msb, exponent, fraction, sign; + for (i = 0; i < i_max; i++) { + sample_num[i] = src[3] << 24 | src[2] << 16 | src[1] << 8 | src[0] << 0; + if (i == 0 && s->next_sample != sample_num[0]) { + dev_dbg_ratelimited(&s->udev->dev, + "%d samples lost, %d %08x:%08x\n", + sample_num[0] - s->next_sample, + src_len, s->next_sample, sample_num[0]); + } - /* Zero is special */ - if (!x) - return 0; + /* + * Dump all unknown 'garbage' data - maybe we will discover + * someday if there is something rational... + */ + dev_dbg_ratelimited(&s->udev->dev, "%*ph\n", 12, &src[4]); - /* Negative / positive value */ - if (x & (1 << 7)) { - x = -x; - x &= 0x7f; /* result is 7 bit ... + sign */ - sign = 1 << 31; - } else { - sign = 0 << 31; + /* 504 x I+Q samples */ + src += 16; + memcpy(dst, src, 1008); + src += 1008; + dst += 1008; + dst_len += 1008; } - /* Get location of the most significant bit */ - msb = __fls(x); + /* calculate samping rate and output it in 10 seconds intervals */ + if ((s->jiffies_next + msecs_to_jiffies(10000)) <= jiffies) { + unsigned long jiffies_now = jiffies; + unsigned long msecs = jiffies_to_msecs(jiffies_now) - jiffies_to_msecs(s->jiffies_next); + unsigned int samples = sample_num[i_max - 1] - s->sample; + s->jiffies_next = jiffies_now; + s->sample = sample_num[i_max - 1]; + dev_dbg(&s->udev->dev, + "slen=%d samples=%u msecs=%lu sampling rate=%lu\n", + src_len, samples, msecs, + samples * 1000UL / msecs); + } - fraction = ror32(x, (msb - I2F_FRAC_BITS) & 0x1f) & I2F_MASK; - exponent = (127 + msb) << I2F_FRAC_BITS; + /* next sample (sample = sample + i * 504) */ + s->next_sample = sample_num[i_max - 1] + 504; - return (fraction + exponent) | sign; + return dst_len; } -static int msi3101_convert_stream_504(struct msi3101_state *s, u32 *dst, +static int msi3101_convert_stream_504_u8(struct msi3101_state *s, u8 *dst, u8 *src, unsigned int src_len) { int i, j, i_max, dst_len = 0; - u16 sample[2]; u32 sample_num[3]; + s8 *s8src; + u8 *u8dst; /* There could be 1-3 1024 bytes URB frames */ i_max = src_len / 1024; + u8dst = (u8 *) dst; for (i = 0; i < i_max; i++) { sample_num[i] = src[3] << 24 | src[2] << 16 | src[1] << 8 | src[0] << 0; @@ -556,30 +277,28 @@ static int msi3101_convert_stream_504(struct msi3101_state *s, u32 *dst, */ dev_dbg_ratelimited(&s->udev->dev, "%*ph\n", 12, &src[4]); + /* 504 x I+Q samples */ src += 16; - for (j = 0; j < 1008; j += 2) { - sample[0] = src[j + 0]; - sample[1] = src[j + 1]; - *dst++ = msi3101_convert_sample_504(s, sample[0]); - *dst++ = msi3101_convert_sample_504(s, sample[1]); - } - /* 504 x I+Q 32bit float samples */ - dst_len += 504 * 2 * 4; + s8src = (s8 *) src; + for (j = 0; j < 1008; j++) + *u8dst++ = *s8src++ + 128; + src += 1008; + dst += 1008; + dst_len += 1008; } /* calculate samping rate and output it in 10 seconds intervals */ - if ((s->jiffies + msecs_to_jiffies(10000)) <= jiffies) { - unsigned long jiffies_now = jiffies; - unsigned long msecs = jiffies_to_msecs(jiffies_now) - jiffies_to_msecs(s->jiffies); + if (unlikely(time_is_before_jiffies(s->jiffies_next))) { +#define MSECS 10000UL unsigned int samples = sample_num[i_max - 1] - s->sample; - s->jiffies = jiffies_now; + s->jiffies_next = jiffies + msecs_to_jiffies(MSECS); s->sample = sample_num[i_max - 1]; dev_dbg(&s->udev->dev, "slen=%d samples=%u msecs=%lu sampling rate=%lu\n", - src_len, samples, msecs, - samples * 1000UL / msecs); + src_len, samples, MSECS, + samples * 1000UL / MSECS); } /* next sample (sample = sample + i * 504) */ @@ -589,48 +308,53 @@ static int msi3101_convert_stream_504(struct msi3101_state *s, u32 *dst, } /* - * Converts signed ~10+2-bit integer into 32-bit IEEE floating point - * representation. + * +=========================================================================== + * | 00-1023 | USB packet type '384' + * +=========================================================================== + * | 00- 03 | sequence number of first sample in that USB packet + * +--------------------------------------------------------------------------- + * | 04- 15 | garbage + * +--------------------------------------------------------------------------- + * | 16- 175 | samples + * +--------------------------------------------------------------------------- + * | 176- 179 | control bits for previous samples + * +--------------------------------------------------------------------------- + * | 180- 339 | samples + * +--------------------------------------------------------------------------- + * | 340- 343 | control bits for previous samples + * +--------------------------------------------------------------------------- + * | 344- 503 | samples + * +--------------------------------------------------------------------------- + * | 504- 507 | control bits for previous samples + * +--------------------------------------------------------------------------- + * | 508- 667 | samples + * +--------------------------------------------------------------------------- + * | 668- 671 | control bits for previous samples + * +--------------------------------------------------------------------------- + * | 672- 831 | samples + * +--------------------------------------------------------------------------- + * | 832- 835 | control bits for previous samples + * +--------------------------------------------------------------------------- + * | 836- 995 | samples + * +--------------------------------------------------------------------------- + * | 996- 999 | control bits for previous samples + * +--------------------------------------------------------------------------- + * | 1000-1023 | garbage + * +--------------------------------------------------------------------------- + * + * Bytes 4 - 7 could have some meaning? + * + * Control bits for previous samples is 32-bit field, containing 16 x 2-bit + * numbers. This results one 2-bit number for 8 samples. It is likely used for + * for bit shifting sample by given bits, increasing actual sampling resolution. + * Number 2 (0b10) was never seen. + * + * 6 * 16 * 2 * 4 = 768 samples. 768 * 4 = 3072 bytes */ -static u32 msi3101_convert_sample_384(struct msi3101_state *s, u16 x, int shift) -{ - u32 msb, exponent, fraction, sign; - s->sample_ctrl_bit[shift]++; - - /* Zero is special */ - if (!x) - return 0; - - if (shift == 3) - shift = 2; - - /* Convert 10-bit two's complement to 12-bit */ - if (x & (1 << 9)) { - x |= ~0U << 10; /* set all the rest bits to one */ - x <<= shift; - x = -x; - x &= 0x7ff; /* result is 11 bit ... + sign */ - sign = 1 << 31; - } else { - x <<= shift; - sign = 0 << 31; - } - - /* Get location of the most significant bit */ - msb = __fls(x); - - fraction = ror32(x, (msb - I2F_FRAC_BITS) & 0x1f) & I2F_MASK; - exponent = (127 + msb) << I2F_FRAC_BITS; - - return (fraction + exponent) | sign; -} - -static int msi3101_convert_stream_384(struct msi3101_state *s, u32 *dst, +static int msi3101_convert_stream_384(struct msi3101_state *s, u8 *dst, u8 *src, unsigned int src_len) { - int i, j, k, l, i_max, dst_len = 0; - u16 sample[4]; - u32 bits; + int i, i_max, dst_len = 0; u32 sample_num[3]; /* There could be 1-3 1024 bytes URB frames */ @@ -651,38 +375,20 @@ static int msi3101_convert_stream_384(struct msi3101_state *s, u32 *dst, dev_dbg_ratelimited(&s->udev->dev, "%*ph %*ph\n", 12, &src[4], 24, &src[1000]); + /* 384 x I+Q samples */ src += 16; - for (j = 0; j < 6; j++) { - bits = src[160 + 3] << 24 | src[160 + 2] << 16 | src[160 + 1] << 8 | src[160 + 0] << 0; - for (k = 0; k < 16; k++) { - for (l = 0; l < 10; l += 5) { - sample[0] = (src[l + 0] & 0xff) >> 0 | (src[l + 1] & 0x03) << 8; - sample[1] = (src[l + 1] & 0xfc) >> 2 | (src[l + 2] & 0x0f) << 6; - sample[2] = (src[l + 2] & 0xf0) >> 4 | (src[l + 3] & 0x3f) << 4; - sample[3] = (src[l + 3] & 0xc0) >> 6 | (src[l + 4] & 0xff) << 2; - - *dst++ = msi3101_convert_sample_384(s, sample[0], (bits >> (2 * k)) & 0x3); - *dst++ = msi3101_convert_sample_384(s, sample[1], (bits >> (2 * k)) & 0x3); - *dst++ = msi3101_convert_sample_384(s, sample[2], (bits >> (2 * k)) & 0x3); - *dst++ = msi3101_convert_sample_384(s, sample[3], (bits >> (2 * k)) & 0x3); - } - src += 10; - } - dev_dbg_ratelimited(&s->udev->dev, - "sample control bits %08x\n", bits); - src += 4; - } - /* 384 x I+Q 32bit float samples */ - dst_len += 384 * 2 * 4; - src += 24; + memcpy(dst, src, 984); + src += 984 + 24; + dst += 984; + dst_len += 984; } /* calculate samping rate and output it in 10 seconds intervals */ - if ((s->jiffies + msecs_to_jiffies(10000)) <= jiffies) { + if ((s->jiffies_next + msecs_to_jiffies(10000)) <= jiffies) { unsigned long jiffies_now = jiffies; - unsigned long msecs = jiffies_to_msecs(jiffies_now) - jiffies_to_msecs(s->jiffies); + unsigned long msecs = jiffies_to_msecs(jiffies_now) - jiffies_to_msecs(s->jiffies_next); unsigned int samples = sample_num[i_max - 1] - s->sample; - s->jiffies = jiffies_now; + s->jiffies_next = jiffies_now; s->sample = sample_num[i_max - 1]; dev_dbg(&s->udev->dev, "slen=%d samples=%u msecs=%lu sampling rate=%lu bits=%d.%d.%d.%d\n", @@ -699,40 +405,21 @@ static int msi3101_convert_stream_384(struct msi3101_state *s, u32 *dst, } /* - * Converts signed 12-bit integer into 32-bit IEEE floating point - * representation. + * +=========================================================================== + * | 00-1023 | USB packet type '336' + * +=========================================================================== + * | 00- 03 | sequence number of first sample in that USB packet + * +--------------------------------------------------------------------------- + * | 04- 15 | garbage + * +--------------------------------------------------------------------------- + * | 16-1023 | samples + * +--------------------------------------------------------------------------- + * signed 12-bit sample */ -static u32 msi3101_convert_sample_336(struct msi3101_state *s, u16 x) -{ - u32 msb, exponent, fraction, sign; - - /* Zero is special */ - if (!x) - return 0; - - /* Negative / positive value */ - if (x & (1 << 11)) { - x = -x; - x &= 0x7ff; /* result is 11 bit ... + sign */ - sign = 1 << 31; - } else { - sign = 0 << 31; - } - - /* Get location of the most significant bit */ - msb = __fls(x); - - fraction = ror32(x, (msb - I2F_FRAC_BITS) & 0x1f) & I2F_MASK; - exponent = (127 + msb) << I2F_FRAC_BITS; - - return (fraction + exponent) | sign; -} - -static int msi3101_convert_stream_336(struct msi3101_state *s, u32 *dst, +static int msi3101_convert_stream_336(struct msi3101_state *s, u8 *dst, u8 *src, unsigned int src_len) { - int i, j, i_max, dst_len = 0; - u16 sample[2]; + int i, i_max, dst_len = 0; u32 sample_num[3]; /* There could be 1-3 1024 bytes URB frames */ @@ -753,25 +440,20 @@ static int msi3101_convert_stream_336(struct msi3101_state *s, u32 *dst, */ dev_dbg_ratelimited(&s->udev->dev, "%*ph\n", 12, &src[4]); + /* 336 x I+Q samples */ src += 16; - for (j = 0; j < 1008; j += 3) { - sample[0] = (src[j + 0] & 0xff) >> 0 | (src[j + 1] & 0x0f) << 8; - sample[1] = (src[j + 1] & 0xf0) >> 4 | (src[j + 2] & 0xff) << 4; - - *dst++ = msi3101_convert_sample_336(s, sample[0]); - *dst++ = msi3101_convert_sample_336(s, sample[1]); - } - /* 336 x I+Q 32bit float samples */ - dst_len += 336 * 2 * 4; + memcpy(dst, src, 1008); src += 1008; + dst += 1008; + dst_len += 1008; } /* calculate samping rate and output it in 10 seconds intervals */ - if ((s->jiffies + msecs_to_jiffies(10000)) <= jiffies) { + if ((s->jiffies_next + msecs_to_jiffies(10000)) <= jiffies) { unsigned long jiffies_now = jiffies; - unsigned long msecs = jiffies_to_msecs(jiffies_now) - jiffies_to_msecs(s->jiffies); + unsigned long msecs = jiffies_to_msecs(jiffies_now) - jiffies_to_msecs(s->jiffies_next); unsigned int samples = sample_num[i_max - 1] - s->sample; - s->jiffies = jiffies_now; + s->jiffies_next = jiffies_now; s->sample = sample_num[i_max - 1]; dev_dbg(&s->udev->dev, "slen=%d samples=%u msecs=%lu sampling rate=%lu\n", @@ -786,41 +468,75 @@ static int msi3101_convert_stream_336(struct msi3101_state *s, u32 *dst, } /* - * Converts signed 14-bit integer into 32-bit IEEE floating point - * representation. + * +=========================================================================== + * | 00-1023 | USB packet type '252' + * +=========================================================================== + * | 00- 03 | sequence number of first sample in that USB packet + * +--------------------------------------------------------------------------- + * | 04- 15 | garbage + * +--------------------------------------------------------------------------- + * | 16-1023 | samples + * +--------------------------------------------------------------------------- + * signed 14-bit sample */ -static u32 msi3101_convert_sample_252(struct msi3101_state *s, u16 x) +static int msi3101_convert_stream_252(struct msi3101_state *s, u8 *dst, + u8 *src, unsigned int src_len) { - u32 msb, exponent, fraction, sign; + int i, i_max, dst_len = 0; + u32 sample_num[3]; - /* Zero is special */ - if (!x) - return 0; + /* There could be 1-3 1024 bytes URB frames */ + i_max = src_len / 1024; - /* Negative / positive value */ - if (x & (1 << 13)) { - x = -x; - x &= 0x1fff; /* result is 13 bit ... + sign */ - sign = 1 << 31; - } else { - sign = 0 << 31; + for (i = 0; i < i_max; i++) { + sample_num[i] = src[3] << 24 | src[2] << 16 | src[1] << 8 | src[0] << 0; + if (i == 0 && s->next_sample != sample_num[0]) { + dev_dbg_ratelimited(&s->udev->dev, + "%d samples lost, %d %08x:%08x\n", + sample_num[0] - s->next_sample, + src_len, s->next_sample, sample_num[0]); + } + + /* + * Dump all unknown 'garbage' data - maybe we will discover + * someday if there is something rational... + */ + dev_dbg_ratelimited(&s->udev->dev, "%*ph\n", 12, &src[4]); + + /* 252 x I+Q samples */ + src += 16; + memcpy(dst, src, 1008); + src += 1008; + dst += 1008; + dst_len += 1008; } - /* Get location of the most significant bit */ - msb = __fls(x); + /* calculate samping rate and output it in 10 seconds intervals */ + if ((s->jiffies_next + msecs_to_jiffies(10000)) <= jiffies) { + unsigned long jiffies_now = jiffies; + unsigned long msecs = jiffies_to_msecs(jiffies_now) - jiffies_to_msecs(s->jiffies_next); + unsigned int samples = sample_num[i_max - 1] - s->sample; + s->jiffies_next = jiffies_now; + s->sample = sample_num[i_max - 1]; + dev_dbg(&s->udev->dev, + "slen=%d samples=%u msecs=%lu sampling rate=%lu\n", + src_len, samples, msecs, + samples * 1000UL / msecs); + } - fraction = ror32(x, (msb - I2F_FRAC_BITS) & 0x1f) & I2F_MASK; - exponent = (127 + msb) << I2F_FRAC_BITS; + /* next sample (sample = sample + i * 252) */ + s->next_sample = sample_num[i_max - 1] + 252; - return (fraction + exponent) | sign; + return dst_len; } -static int msi3101_convert_stream_252(struct msi3101_state *s, u32 *dst, +static int msi3101_convert_stream_252_u16(struct msi3101_state *s, u8 *dst, u8 *src, unsigned int src_len) { int i, j, i_max, dst_len = 0; - u16 sample[2]; u32 sample_num[3]; + u16 *u16dst = (u16 *) dst; + struct {signed int x:14;} se; /* There could be 1-3 1024 bytes URB frames */ i_max = src_len / 1024; @@ -840,30 +556,44 @@ static int msi3101_convert_stream_252(struct msi3101_state *s, u32 *dst, */ dev_dbg_ratelimited(&s->udev->dev, "%*ph\n", 12, &src[4]); + /* 252 x I+Q samples */ src += 16; + for (j = 0; j < 1008; j += 4) { - sample[0] = src[j + 0] >> 0 | src[j + 1] << 8; - sample[1] = src[j + 2] >> 0 | src[j + 3] << 8; + unsigned int usample[2]; + int ssample[2]; - *dst++ = msi3101_convert_sample_252(s, sample[0]); - *dst++ = msi3101_convert_sample_252(s, sample[1]); + usample[0] = src[j + 0] >> 0 | src[j + 1] << 8; + usample[1] = src[j + 2] >> 0 | src[j + 3] << 8; + + /* sign extension from 14-bit to signed int */ + ssample[0] = se.x = usample[0]; + ssample[1] = se.x = usample[1]; + + /* from signed to unsigned */ + usample[0] = ssample[0] + 8192; + usample[1] = ssample[1] + 8192; + + /* from 14-bit to 16-bit */ + *u16dst++ = (usample[0] << 2) | (usample[0] >> 12); + *u16dst++ = (usample[1] << 2) | (usample[1] >> 12); } - /* 252 x I+Q 32bit float samples */ - dst_len += 252 * 2 * 4; + src += 1008; + dst += 1008; + dst_len += 1008; } /* calculate samping rate and output it in 10 seconds intervals */ - if ((s->jiffies + msecs_to_jiffies(10000)) <= jiffies) { - unsigned long jiffies_now = jiffies; - unsigned long msecs = jiffies_to_msecs(jiffies_now) - jiffies_to_msecs(s->jiffies); + if (unlikely(time_is_before_jiffies(s->jiffies_next))) { +#define MSECS 10000UL unsigned int samples = sample_num[i_max - 1] - s->sample; - s->jiffies = jiffies_now; + s->jiffies_next = jiffies + msecs_to_jiffies(MSECS); s->sample = sample_num[i_max - 1]; dev_dbg(&s->udev->dev, "slen=%d samples=%u msecs=%lu sampling rate=%lu\n", - src_len, samples, msecs, - samples * 1000UL / msecs); + src_len, samples, MSECS, + samples * 1000UL / MSECS); } /* next sample (sample = sample + i * 252) */ @@ -883,14 +613,14 @@ static void msi3101_isoc_handler(struct urb *urb) unsigned char *iso_buf = NULL; struct msi3101_frame_buf *fbuf; - if (urb->status == -ENOENT || urb->status == -ECONNRESET || - urb->status == -ESHUTDOWN) { + if (unlikely(urb->status == -ENOENT || urb->status == -ECONNRESET || + urb->status == -ESHUTDOWN)) { dev_dbg(&s->udev->dev, "URB (%p) unlinked %ssynchronuously\n", urb, urb->status == -ENOENT ? "" : "a"); return; } - if (urb->status != 0) { + if (unlikely(urb->status != 0)) { dev_dbg(&s->udev->dev, "msi3101_isoc_handler() called with status %d\n", urb->status); @@ -910,28 +640,28 @@ static void msi3101_isoc_handler(struct urb *urb) /* Check frame error */ fstatus = urb->iso_frame_desc[i].status; - if (fstatus) { + if (unlikely(fstatus)) { dev_dbg_ratelimited(&s->udev->dev, "frame=%d/%d has error %d skipping\n", i, urb->number_of_packets, fstatus); - goto skip; + continue; } /* Check if that frame contains data */ flen = urb->iso_frame_desc[i].actual_length; - if (flen == 0) - goto skip; + if (unlikely(flen == 0)) + continue; iso_buf = urb->transfer_buffer + urb->iso_frame_desc[i].offset; /* Get free framebuffer */ fbuf = msi3101_get_next_fill_buf(s); - if (fbuf == NULL) { + if (unlikely(fbuf == NULL)) { s->vb_full++; dev_dbg_ratelimited(&s->udev->dev, "videobuf is full, %d packets dropped\n", s->vb_full); - goto skip; + continue; } /* fill framebuffer */ @@ -939,13 +669,11 @@ static void msi3101_isoc_handler(struct urb *urb) flen = s->convert_stream(s, ptr, iso_buf, flen); vb2_set_plane_payload(&fbuf->vb, 0, flen); vb2_buffer_done(&fbuf->vb, VB2_BUF_STATE_DONE); -skip: - ; } handler_end: i = usb_submit_urb(urb, GFP_ATOMIC); - if (i != 0) + if (unlikely(i != 0)) dev_dbg(&s->udev->dev, "Error (%d) re-submitting urb in msi3101_isoc_handler\n", i); @@ -1008,7 +736,7 @@ static int msi3101_isoc_init(struct msi3101_state *s) udev = s->udev; ret = usb_set_interface(s->udev, 0, 1); - if (ret < 0) + if (ret) return ret; /* Allocate and init Isochronuous urbs */ @@ -1112,14 +840,12 @@ static int msi3101_querycap(struct file *file, void *fh, strlcpy(cap->driver, KBUILD_MODNAME, sizeof(cap->driver)); strlcpy(cap->card, s->vdev.name, sizeof(cap->card)); usb_make_path(s->udev, cap->bus_info, sizeof(cap->bus_info)); - cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING | - V4L2_CAP_READWRITE; - cap->device_caps = V4L2_CAP_TUNER; + cap->device_caps = V4L2_CAP_SDR_CAPTURE | V4L2_CAP_STREAMING | + V4L2_CAP_READWRITE | V4L2_CAP_TUNER; cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS; return 0; } - /* Videobuf2 operations */ static int msi3101_queue_setup(struct vb2_queue *vq, const struct v4l2_format *fmt, unsigned int *nbuffers, @@ -1135,25 +861,14 @@ static int msi3101_queue_setup(struct vb2_queue *vq, * 3, wMaxPacketSize 3x 1024 bytes * 504, max IQ sample pairs per 1024 frame * 2, two samples, I and Q - * 4, 32-bit float + * 2, 16-bit is enough for single sample */ - sizes[0] = PAGE_ALIGN(3 * 504 * 2 * 4); /* = 12096 */ + sizes[0] = PAGE_ALIGN(3 * 504 * 2 * 2); dev_dbg(&s->udev->dev, "%s: nbuffers=%d sizes[0]=%d\n", __func__, *nbuffers, sizes[0]); return 0; } -static int msi3101_buf_prepare(struct vb2_buffer *vb) -{ - struct msi3101_state *s = vb2_get_drv_priv(vb->vb2_queue); - - /* Don't allow queing new buffers after device disconnection */ - if (!s->udev) - return -ENODEV; - - return 0; -} - static void msi3101_buf_queue(struct vb2_buffer *vb) { struct msi3101_state *s = vb2_get_drv_priv(vb->vb2_queue); @@ -1162,7 +877,7 @@ static void msi3101_buf_queue(struct vb2_buffer *vb) unsigned long flags = 0; /* Check the device has not disconnected between prep and queuing */ - if (!s->udev) { + if (unlikely(!s->udev)) { vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR); return; } @@ -1221,29 +936,46 @@ static int msi3101_set_usb_adc(struct msi3101_state *s) int ret, div_n, div_m, div_r_out, f_sr, f_vco, fract; u32 reg3, reg4, reg7; - f_sr = s->ctrl_sampling_rate->val64; + f_sr = s->f_adc; /* select stream format */ - if (f_sr < 6000000) { - s->convert_stream = msi3101_convert_stream_252; + switch (s->pixelformat) { + case V4L2_SDR_FMT_CU8: + s->convert_stream = msi3101_convert_stream_504_u8; + reg7 = 0x000c9407; + break; + case V4L2_SDR_FMT_CU16LE: + s->convert_stream = msi3101_convert_stream_252_u16; reg7 = 0x00009407; - } else if (f_sr < 8000000) { - s->convert_stream = msi3101_convert_stream_336; - reg7 = 0x00008507; - } else if (f_sr < 9000000) { + break; + case V4L2_PIX_FMT_SDR_S8: + s->convert_stream = msi3101_convert_stream_504; + reg7 = 0x000c9407; + break; + case V4L2_PIX_FMT_SDR_MSI2500_384: s->convert_stream = msi3101_convert_stream_384; reg7 = 0x0000a507; - } else { - s->convert_stream = msi3101_convert_stream_504; + break; + case V4L2_PIX_FMT_SDR_S12: + s->convert_stream = msi3101_convert_stream_336; + reg7 = 0x00008507; + break; + case V4L2_PIX_FMT_SDR_S14: + s->convert_stream = msi3101_convert_stream_252; + reg7 = 0x00009407; + break; + default: + s->convert_stream = msi3101_convert_stream_504_u8; reg7 = 0x000c9407; + break; } /* * Synthesizer config is just a educated guess... * * [7:0] 0x03, register address - * [8] 1, always - * [9] ? + * [8] 1, power control + * [9] ?, power control * [12:10] output divider * [13] 0 ? * [14] 0 ? @@ -1334,14 +1066,37 @@ err: return ret; }; +static int msi3101_set_gain(struct msi3101_state *s) +{ + int ret; + u32 reg; + dev_dbg(&s->udev->dev, "%s: lna=%d mixer=%d if=%d\n", __func__, + s->lna_gain->val, s->mixer_gain->val, s->if_gain->val); + + reg = 1 << 0; + reg |= (59 - s->if_gain->val) << 4; + reg |= 0 << 10; + reg |= (1 - s->mixer_gain->val) << 12; + reg |= (1 - s->lna_gain->val) << 13; + reg |= 4 << 14; + reg |= 0 << 17; + ret = msi3101_tuner_write(s, reg); + if (ret) + goto err; + + return 0; +err: + dev_dbg(&s->udev->dev, "%s: failed %d\n", __func__, ret); + return ret; +}; + static int msi3101_set_tuner(struct msi3101_state *s) { - int ret, i, len; + int ret, i; unsigned int n, m, thresh, frac, vco_step, tmp, f_if1; u32 reg; u64 f_vco, tmp64; u8 mode, filter_mode, lo_div; - const struct msi3101_gain *gain_lut; static const struct { u32 rf; u8 mode; @@ -1376,30 +1131,23 @@ static int msi3101_set_tuner(struct msi3101_state *s) {8000000, 0x07}, /* 8 MHz */ }; - unsigned int f_rf = s->ctrl_tuner_rf->val64; + unsigned int f_rf = s->f_tuner; /* * bandwidth (Hz) * 200000, 300000, 600000, 1536000, 5000000, 6000000, 7000000, 8000000 */ - unsigned int bandwidth = s->ctrl_tuner_bw->val; + unsigned int bandwidth; /* * intermediate frequency (Hz) * 0, 450000, 1620000, 2048000 */ - unsigned int f_if = s->ctrl_tuner_if->val; - - /* - * gain reduction (dB) - * 0 - 102 below 420 MHz - * 0 - 85 above 420 MHz - */ - int gain = s->ctrl_tuner_gain->val; + unsigned int f_if = 0; dev_dbg(&s->udev->dev, - "%s: f_rf=%d bandwidth=%d f_if=%d gain=%d\n", - __func__, f_rf, bandwidth, f_if, gain); + "%s: f_rf=%d f_if=%d\n", + __func__, f_rf, f_if); ret = -EINVAL; @@ -1430,8 +1178,16 @@ static int msi3101_set_tuner(struct msi3101_state *s) if (i == ARRAY_SIZE(if_freq_lut)) goto err; + /* filters */ + if (s->bandwidth_auto->val) + bandwidth = s->f_adc; + else + bandwidth = s->bandwidth->val; + + bandwidth = clamp(bandwidth, 200000U, 8000000U); + for (i = 0; i < ARRAY_SIZE(bandwidth_lut); i++) { - if (bandwidth == bandwidth_lut[i].freq) { + if (bandwidth <= bandwidth_lut[i].freq) { bandwidth = bandwidth_lut[i].val; break; } @@ -1440,6 +1196,11 @@ static int msi3101_set_tuner(struct msi3101_state *s) if (i == ARRAY_SIZE(bandwidth_lut)) goto err; + s->bandwidth->val = bandwidth_lut[i].freq; + + dev_dbg(&s->udev->dev, "%s: bandwidth selected=%d\n", + __func__, bandwidth_lut[i].freq); + #define F_OUT_STEP 1 #define R_REF 4 f_vco = (f_rf + f_if + f_if1) * lo_div; @@ -1504,38 +1265,7 @@ static int msi3101_set_tuner(struct msi3101_state *s) if (ret) goto err; - if (f_rf < 120000000) { - gain_lut = msi3101_gain_lut_120; - len = ARRAY_SIZE(msi3101_gain_lut_120); - } else if (f_rf < 245000000) { - gain_lut = msi3101_gain_lut_245; - len = ARRAY_SIZE(msi3101_gain_lut_120); - } else { - gain_lut = msi3101_gain_lut_1000; - len = ARRAY_SIZE(msi3101_gain_lut_1000); - } - - for (i = 0; i < len; i++) { - if (gain_lut[i].tot >= gain) - break; - } - - if (i == len) - goto err; - - dev_dbg(&s->udev->dev, - "%s: gain tot=%d baseband=%d lna=%d mixer=%d\n", - __func__, gain_lut[i].tot, gain_lut[i].baseband, - gain_lut[i].lna, gain_lut[i].mixer); - - reg = 1 << 0; - reg |= gain_lut[i].baseband << 4; - reg |= 0 << 10; - reg |= gain_lut[i].mixer << 12; - reg |= gain_lut[i].lna << 13; - reg |= 4 << 14; - reg |= 0 << 17; - ret = msi3101_tuner_write(s, reg); + ret = msi3101_set_gain(s); if (ret) goto err; @@ -1594,6 +1324,12 @@ static int msi3101_stop_streaming(struct vb2_queue *vq) msleep(20); msi3101_ctrl_msg(s, CMD_STOP_STREAMING, 0); + /* sleep USB IF / ADC */ + msi3101_ctrl_msg(s, CMD_WREG, 0x01000003); + + /* sleep tuner */ + msi3101_tuner_write(s, 0x000000); + mutex_unlock(&s->v4l2_lock); return 0; @@ -1601,7 +1337,6 @@ static int msi3101_stop_streaming(struct vb2_queue *vq) static struct vb2_ops msi3101_vb2_ops = { .queue_setup = msi3101_queue_setup, - .buf_prepare = msi3101_buf_prepare, .buf_queue = msi3101_buf_queue, .start_streaming = msi3101_start_streaming, .stop_streaming = msi3101_stop_streaming, @@ -1609,30 +1344,77 @@ static struct vb2_ops msi3101_vb2_ops = { .wait_finish = vb2_ops_wait_finish, }; -static int msi3101_enum_input(struct file *file, void *fh, struct v4l2_input *i) +static int msi3101_enum_fmt_sdr_cap(struct file *file, void *priv, + struct v4l2_fmtdesc *f) { - if (i->index != 0) + struct msi3101_state *s = video_drvdata(file); + dev_dbg(&s->udev->dev, "%s: index=%d\n", __func__, f->index); + + if (f->index >= NUM_FORMATS) return -EINVAL; - strlcpy(i->name, "SDR data", sizeof(i->name)); - i->type = V4L2_INPUT_TYPE_CAMERA; + strlcpy(f->description, formats[f->index].name, sizeof(f->description)); + f->pixelformat = formats[f->index].pixelformat; + + return 0; +} + +static int msi3101_g_fmt_sdr_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct msi3101_state *s = video_drvdata(file); + dev_dbg(&s->udev->dev, "%s: pixelformat fourcc %4.4s\n", __func__, + (char *)&s->pixelformat); + + f->fmt.sdr.pixelformat = s->pixelformat; return 0; } -static int msi3101_g_input(struct file *file, void *fh, unsigned int *i) +static int msi3101_s_fmt_sdr_cap(struct file *file, void *priv, + struct v4l2_format *f) { - *i = 0; + struct msi3101_state *s = video_drvdata(file); + struct vb2_queue *q = &s->vb_queue; + int i; + dev_dbg(&s->udev->dev, "%s: pixelformat fourcc %4.4s\n", __func__, + (char *)&f->fmt.sdr.pixelformat); + + if (vb2_is_busy(q)) + return -EBUSY; + + for (i = 0; i < NUM_FORMATS; i++) { + if (formats[i].pixelformat == f->fmt.sdr.pixelformat) { + s->pixelformat = f->fmt.sdr.pixelformat; + return 0; + } + } + + f->fmt.sdr.pixelformat = formats[0].pixelformat; + s->pixelformat = formats[0].pixelformat; return 0; } -static int msi3101_s_input(struct file *file, void *fh, unsigned int i) +static int msi3101_try_fmt_sdr_cap(struct file *file, void *priv, + struct v4l2_format *f) { - return i ? -EINVAL : 0; + struct msi3101_state *s = video_drvdata(file); + int i; + dev_dbg(&s->udev->dev, "%s: pixelformat fourcc %4.4s\n", __func__, + (char *)&f->fmt.sdr.pixelformat); + + for (i = 0; i < NUM_FORMATS; i++) { + if (formats[i].pixelformat == f->fmt.sdr.pixelformat) + return 0; + } + + f->fmt.sdr.pixelformat = formats[0].pixelformat; + + return 0; } -static int vidioc_s_tuner(struct file *file, void *priv, +static int msi3101_s_tuner(struct file *file, void *priv, const struct v4l2_tuner *v) { struct msi3101_state *s = video_drvdata(file); @@ -1641,34 +1423,113 @@ static int vidioc_s_tuner(struct file *file, void *priv, return 0; } -static int vidioc_g_tuner(struct file *file, void *priv, struct v4l2_tuner *v) +static int msi3101_g_tuner(struct file *file, void *priv, struct v4l2_tuner *v) { struct msi3101_state *s = video_drvdata(file); dev_dbg(&s->udev->dev, "%s:\n", __func__); - strcpy(v->name, "SDR RX"); - v->capability = V4L2_TUNER_CAP_LOW; + if (v->index == 0) { + strlcpy(v->name, "ADC: Mirics MSi2500", sizeof(v->name)); + v->type = V4L2_TUNER_ADC; + v->capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS; + v->rangelow = 1200000; + v->rangehigh = 15000000; + } else if (v->index == 1) { + strlcpy(v->name, "RF: Mirics MSi001", sizeof(v->name)); + v->type = V4L2_TUNER_RF; + v->capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS; + v->rangelow = 49000000; + v->rangehigh = 960000000; + } else { + return -EINVAL; + } return 0; } -static int vidioc_s_frequency(struct file *file, void *priv, +static int msi3101_g_frequency(struct file *file, void *priv, + struct v4l2_frequency *f) +{ + struct msi3101_state *s = video_drvdata(file); + int ret = 0; + dev_dbg(&s->udev->dev, "%s: tuner=%d type=%d\n", + __func__, f->tuner, f->type); + + if (f->tuner == 0) + f->frequency = s->f_adc; + else if (f->tuner == 1) + f->frequency = s->f_tuner; + else + return -EINVAL; + + return ret; +} + +static int msi3101_s_frequency(struct file *file, void *priv, const struct v4l2_frequency *f) { struct msi3101_state *s = video_drvdata(file); - dev_dbg(&s->udev->dev, "%s: frequency=%lu Hz (%u)\n", - __func__, f->frequency * 625UL / 10UL, f->frequency); + int ret, band; + dev_dbg(&s->udev->dev, "%s: tuner=%d type=%d frequency=%u\n", + __func__, f->tuner, f->type, f->frequency); + + if (f->tuner == 0) { + s->f_adc = clamp_t(unsigned int, f->frequency, + bands_adc[0].rangelow, + bands_adc[0].rangehigh); + dev_dbg(&s->udev->dev, "%s: ADC frequency=%u Hz\n", + __func__, s->f_adc); + ret = msi3101_set_usb_adc(s); + } else if (f->tuner == 1) { + #define BAND_RF_0 ((bands_rf[0].rangehigh + bands_rf[1].rangelow) / 2) + if (f->frequency < BAND_RF_0) + band = 0; + else + band = 1; + s->f_tuner = clamp_t(unsigned int, f->frequency, + bands_rf[band].rangelow, + bands_rf[band].rangehigh); + dev_dbg(&s->udev->dev, "%s: RF frequency=%u Hz\n", + __func__, f->frequency); + ret = msi3101_set_tuner(s); + } else { + return -EINVAL; + } - return v4l2_ctrl_s_ctrl_int64(s->ctrl_tuner_rf, - f->frequency * 625UL / 10UL); + return ret; +} + +static int msi3101_enum_freq_bands(struct file *file, void *priv, + struct v4l2_frequency_band *band) +{ + struct msi3101_state *s = video_drvdata(file); + dev_dbg(&s->udev->dev, "%s: tuner=%d type=%d index=%d\n", + __func__, band->tuner, band->type, band->index); + + if (band->tuner == 0) { + if (band->index >= ARRAY_SIZE(bands_adc)) + return -EINVAL; + + *band = bands_adc[band->index]; + } else if (band->tuner == 1) { + if (band->index >= ARRAY_SIZE(bands_rf)) + return -EINVAL; + + *band = bands_rf[band->index]; + } else { + return -EINVAL; + } + + return 0; } static const struct v4l2_ioctl_ops msi3101_ioctl_ops = { .vidioc_querycap = msi3101_querycap, - .vidioc_enum_input = msi3101_enum_input, - .vidioc_g_input = msi3101_g_input, - .vidioc_s_input = msi3101_s_input, + .vidioc_enum_fmt_sdr_cap = msi3101_enum_fmt_sdr_cap, + .vidioc_g_fmt_sdr_cap = msi3101_g_fmt_sdr_cap, + .vidioc_s_fmt_sdr_cap = msi3101_s_fmt_sdr_cap, + .vidioc_try_fmt_sdr_cap = msi3101_try_fmt_sdr_cap, .vidioc_reqbufs = vb2_ioctl_reqbufs, .vidioc_create_bufs = vb2_ioctl_create_bufs, @@ -1680,9 +1541,12 @@ static const struct v4l2_ioctl_ops msi3101_ioctl_ops = { .vidioc_streamon = vb2_ioctl_streamon, .vidioc_streamoff = vb2_ioctl_streamoff, - .vidioc_g_tuner = vidioc_g_tuner, - .vidioc_s_tuner = vidioc_s_tuner, - .vidioc_s_frequency = vidioc_s_frequency, + .vidioc_g_tuner = msi3101_g_tuner, + .vidioc_s_tuner = msi3101_s_tuner, + + .vidioc_g_frequency = msi3101_g_frequency, + .vidioc_s_frequency = msi3101_s_frequency, + .vidioc_enum_freq_bands = msi3101_enum_freq_bands, .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, .vidioc_unsubscribe_event = v4l2_event_unsubscribe, @@ -1710,7 +1574,7 @@ static int msi3101_s_ctrl(struct v4l2_ctrl *ctrl) { struct msi3101_state *s = container_of(ctrl->handler, struct msi3101_state, - ctrl_handler); + hdl); int ret; dev_dbg(&s->udev->dev, "%s: id=%d name=%s val=%d min=%d max=%d step=%d\n", @@ -1718,18 +1582,17 @@ static int msi3101_s_ctrl(struct v4l2_ctrl *ctrl) ctrl->minimum, ctrl->maximum, ctrl->step); switch (ctrl->id) { - case MSI3101_CID_SAMPLING_MODE: - case MSI3101_CID_SAMPLING_RATE: - case MSI3101_CID_SAMPLING_RESOLUTION: - ret = 0; - break; - case MSI3101_CID_TUNER_RF: - case MSI3101_CID_TUNER_BW: - case MSI3101_CID_TUNER_IF: - case MSI3101_CID_TUNER_GAIN: + case V4L2_CID_RF_TUNER_BANDWIDTH_AUTO: + case V4L2_CID_RF_TUNER_BANDWIDTH: ret = msi3101_set_tuner(s); break; + case V4L2_CID_RF_TUNER_LNA_GAIN: + case V4L2_CID_RF_TUNER_MIXER_GAIN: + case V4L2_CID_RF_TUNER_IF_GAIN: + ret = msi3101_set_gain(s); + break; default: + dev_dbg(&s->udev->dev, "%s: EINVAL\n", __func__); ret = -EINVAL; } @@ -1745,7 +1608,7 @@ static void msi3101_video_release(struct v4l2_device *v) struct msi3101_state *s = container_of(v, struct msi3101_state, v4l2_dev); - v4l2_ctrl_handler_free(&s->ctrl_handler); + v4l2_ctrl_handler_free(&s->hdl); v4l2_device_unregister(&s->v4l2_dev); kfree(s); } @@ -1755,81 +1618,8 @@ static int msi3101_probe(struct usb_interface *intf, { struct usb_device *udev = interface_to_usbdev(intf); struct msi3101_state *s = NULL; + const struct v4l2_ctrl_ops *ops = &msi3101_ctrl_ops; int ret; - static const char * const ctrl_sampling_mode_qmenu_strings[] = { - "Quadrature Sampling", - NULL, - }; - static const struct v4l2_ctrl_config ctrl_sampling_mode = { - .ops = &msi3101_ctrl_ops, - .id = MSI3101_CID_SAMPLING_MODE, - .type = V4L2_CTRL_TYPE_MENU, - .flags = V4L2_CTRL_FLAG_INACTIVE, - .name = "Sampling Mode", - .qmenu = ctrl_sampling_mode_qmenu_strings, - }; - static const struct v4l2_ctrl_config ctrl_sampling_rate = { - .ops = &msi3101_ctrl_ops, - .id = MSI3101_CID_SAMPLING_RATE, - .type = V4L2_CTRL_TYPE_INTEGER64, - .name = "Sampling Rate", - .min = 500000, - .max = 12000000, - .def = 2048000, - .step = 1, - }; - static const struct v4l2_ctrl_config ctrl_sampling_resolution = { - .ops = &msi3101_ctrl_ops, - .id = MSI3101_CID_SAMPLING_RESOLUTION, - .type = V4L2_CTRL_TYPE_INTEGER, - .flags = V4L2_CTRL_FLAG_INACTIVE, - .name = "Sampling Resolution", - .min = 10, - .max = 10, - .def = 10, - .step = 1, - }; - static const struct v4l2_ctrl_config ctrl_tuner_rf = { - .ops = &msi3101_ctrl_ops, - .id = MSI3101_CID_TUNER_RF, - .type = V4L2_CTRL_TYPE_INTEGER64, - .name = "Tuner RF", - .min = 40000000, - .max = 2000000000, - .def = 100000000, - .step = 1, - }; - static const struct v4l2_ctrl_config ctrl_tuner_bw = { - .ops = &msi3101_ctrl_ops, - .id = MSI3101_CID_TUNER_BW, - .type = V4L2_CTRL_TYPE_INTEGER, - .name = "Tuner BW", - .min = 200000, - .max = 8000000, - .def = 600000, - .step = 1, - }; - static const struct v4l2_ctrl_config ctrl_tuner_if = { - .ops = &msi3101_ctrl_ops, - .id = MSI3101_CID_TUNER_IF, - .type = V4L2_CTRL_TYPE_INTEGER, - .flags = V4L2_CTRL_FLAG_INACTIVE, - .name = "Tuner IF", - .min = 0, - .max = 2048000, - .def = 0, - .step = 1, - }; - static const struct v4l2_ctrl_config ctrl_tuner_gain = { - .ops = &msi3101_ctrl_ops, - .id = MSI3101_CID_TUNER_GAIN, - .type = V4L2_CTRL_TYPE_INTEGER, - .name = "Tuner Gain", - .min = 0, - .max = 102, - .def = 0, - .step = 1, - }; s = kzalloc(sizeof(struct msi3101_state), GFP_KERNEL); if (s == NULL) { @@ -1841,11 +1631,12 @@ static int msi3101_probe(struct usb_interface *intf, mutex_init(&s->vb_queue_lock); spin_lock_init(&s->queued_bufs_lock); INIT_LIST_HEAD(&s->queued_bufs); - s->udev = udev; + s->f_adc = bands_adc[0].rangelow; + s->pixelformat = V4L2_SDR_FMT_CU8; /* Init videobuf2 queue structure */ - s->vb_queue.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + s->vb_queue.type = V4L2_BUF_TYPE_SDR_CAPTURE; s->vb_queue.io_modes = VB2_MMAP | VB2_USERPTR | VB2_READ; s->vb_queue.drv_priv = s; s->vb_queue.buf_struct_size = sizeof(struct msi3101_frame_buf); @@ -1853,7 +1644,7 @@ static int msi3101_probe(struct usb_interface *intf, s->vb_queue.mem_ops = &vb2_vmalloc_memops; s->vb_queue.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; ret = vb2_queue_init(&s->vb_queue); - if (ret < 0) { + if (ret) { dev_err(&s->udev->dev, "Could not initialize vb2 queue\n"); goto err_free_mem; } @@ -1866,16 +1657,20 @@ static int msi3101_probe(struct usb_interface *intf, video_set_drvdata(&s->vdev, s); /* Register controls */ - v4l2_ctrl_handler_init(&s->ctrl_handler, 7); - v4l2_ctrl_new_custom(&s->ctrl_handler, &ctrl_sampling_mode, NULL); - s->ctrl_sampling_rate = v4l2_ctrl_new_custom(&s->ctrl_handler, &ctrl_sampling_rate, NULL); - v4l2_ctrl_new_custom(&s->ctrl_handler, &ctrl_sampling_resolution, NULL); - s->ctrl_tuner_rf = v4l2_ctrl_new_custom(&s->ctrl_handler, &ctrl_tuner_rf, NULL); - s->ctrl_tuner_bw = v4l2_ctrl_new_custom(&s->ctrl_handler, &ctrl_tuner_bw, NULL); - s->ctrl_tuner_if = v4l2_ctrl_new_custom(&s->ctrl_handler, &ctrl_tuner_if, NULL); - s->ctrl_tuner_gain = v4l2_ctrl_new_custom(&s->ctrl_handler, &ctrl_tuner_gain, NULL); - if (s->ctrl_handler.error) { - ret = s->ctrl_handler.error; + v4l2_ctrl_handler_init(&s->hdl, 5); + s->bandwidth_auto = v4l2_ctrl_new_std(&s->hdl, ops, + V4L2_CID_RF_TUNER_BANDWIDTH_AUTO, 0, 1, 1, 1); + s->bandwidth = v4l2_ctrl_new_std(&s->hdl, ops, + V4L2_CID_RF_TUNER_BANDWIDTH, 0, 8000000, 1, 0); + v4l2_ctrl_auto_cluster(2, &s->bandwidth_auto, 0, false); + s->lna_gain = v4l2_ctrl_new_std(&s->hdl, ops, + V4L2_CID_RF_TUNER_LNA_GAIN, 0, 1, 1, 1); + s->mixer_gain = v4l2_ctrl_new_std(&s->hdl, ops, + V4L2_CID_RF_TUNER_MIXER_GAIN, 0, 1, 1, 1); + s->if_gain = v4l2_ctrl_new_std(&s->hdl, ops, + V4L2_CID_RF_TUNER_IF_GAIN, 0, 59, 1, 0); + if (s->hdl.error) { + ret = s->hdl.error; dev_err(&s->udev->dev, "Could not initialize controls\n"); goto err_free_controls; } @@ -1889,12 +1684,12 @@ static int msi3101_probe(struct usb_interface *intf, goto err_free_controls; } - s->v4l2_dev.ctrl_handler = &s->ctrl_handler; + s->v4l2_dev.ctrl_handler = &s->hdl; s->vdev.v4l2_dev = &s->v4l2_dev; s->vdev.lock = &s->v4l2_lock; - ret = video_register_device(&s->vdev, VFL_TYPE_GRABBER, -1); - if (ret < 0) { + ret = video_register_device(&s->vdev, VFL_TYPE_SDR, -1); + if (ret) { dev_err(&s->udev->dev, "Failed to register as video device (%d)\n", ret); @@ -1908,7 +1703,7 @@ static int msi3101_probe(struct usb_interface *intf, err_unregister_v4l2_dev: v4l2_device_unregister(&s->v4l2_dev); err_free_controls: - v4l2_ctrl_handler_free(&s->ctrl_handler); + v4l2_ctrl_handler_free(&s->hdl); err_free_mem: kfree(s); return ret; -- cgit v1.1 From 93203dd6c7c436e62523b2ced7faf3aed77218ed Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Sun, 2 Feb 2014 23:34:23 -0300 Subject: [media] msi001: Mirics MSi001 silicon tuner driver That RF tuner driver is bound via SPI bus model and it implements V4L subdev API. I split it out from MSi3101 SDR driver. MSi3101 = MSi2500 + MSi001. Signed-off-by: Antti Palosaari Acked-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/staging/media/msi3101/Kconfig | 4 + drivers/staging/media/msi3101/Makefile | 1 + drivers/staging/media/msi3101/msi001.c | 499 +++++++++++++++++++++++++++++++++ 3 files changed, 504 insertions(+) create mode 100644 drivers/staging/media/msi3101/msi001.c diff --git a/drivers/staging/media/msi3101/Kconfig b/drivers/staging/media/msi3101/Kconfig index 0c349c8..97d5210 100644 --- a/drivers/staging/media/msi3101/Kconfig +++ b/drivers/staging/media/msi3101/Kconfig @@ -3,3 +3,7 @@ config USB_MSI3101 depends on USB && VIDEO_DEV && VIDEO_V4L2 select VIDEOBUF2_CORE select VIDEOBUF2_VMALLOC + +config MEDIA_TUNER_MSI001 + tristate "Mirics MSi001" + depends on VIDEO_V4L2 && SPI diff --git a/drivers/staging/media/msi3101/Makefile b/drivers/staging/media/msi3101/Makefile index 3730654..daf4f58 100644 --- a/drivers/staging/media/msi3101/Makefile +++ b/drivers/staging/media/msi3101/Makefile @@ -1 +1,2 @@ obj-$(CONFIG_USB_MSI3101) += sdr-msi3101.o +obj-$(CONFIG_MEDIA_TUNER_MSI001) += msi001.o diff --git a/drivers/staging/media/msi3101/msi001.c b/drivers/staging/media/msi3101/msi001.c new file mode 100644 index 0000000..25feece0 --- /dev/null +++ b/drivers/staging/media/msi3101/msi001.c @@ -0,0 +1,499 @@ +/* + * Mirics MSi001 silicon tuner driver + * + * Copyright (C) 2013 Antti Palosaari + * Copyright (C) 2014 Antti Palosaari + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +static const struct v4l2_frequency_band bands[] = { + { + .type = V4L2_TUNER_RF, + .index = 0, + .capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS, + .rangelow = 49000000, + .rangehigh = 263000000, + }, { + .type = V4L2_TUNER_RF, + .index = 1, + .capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS, + .rangelow = 390000000, + .rangehigh = 960000000, + }, +}; + +struct msi001 { + struct spi_device *spi; + struct v4l2_subdev sd; + + /* Controls */ + struct v4l2_ctrl_handler hdl; + struct v4l2_ctrl *bandwidth_auto; + struct v4l2_ctrl *bandwidth; + struct v4l2_ctrl *lna_gain; + struct v4l2_ctrl *mixer_gain; + struct v4l2_ctrl *if_gain; + + unsigned int f_tuner; +}; + +static inline struct msi001 *sd_to_msi001(struct v4l2_subdev *sd) +{ + return container_of(sd, struct msi001, sd); +} + +static int msi001_wreg(struct msi001 *s, u32 data) +{ + /* Register format: 4 bits addr + 20 bits value */ + return spi_write(s->spi, &data, 3); +}; + +static int msi001_set_gain(struct msi001 *s, int lna_gain, int mixer_gain, + int if_gain) +{ + int ret; + u32 reg; + dev_dbg(&s->spi->dev, "%s: lna=%d mixer=%d if=%d\n", __func__, + lna_gain, mixer_gain, if_gain); + + reg = 1 << 0; + reg |= (59 - if_gain) << 4; + reg |= 0 << 10; + reg |= (1 - mixer_gain) << 12; + reg |= (1 - lna_gain) << 13; + reg |= 4 << 14; + reg |= 0 << 17; + ret = msi001_wreg(s, reg); + if (ret) + goto err; + + return 0; +err: + dev_dbg(&s->spi->dev, "%s: failed %d\n", __func__, ret); + return ret; +}; + +static int msi001_set_tuner(struct msi001 *s) +{ + int ret, i; + unsigned int n, m, thresh, frac, vco_step, tmp, f_if1; + u32 reg; + u64 f_vco, tmp64; + u8 mode, filter_mode, lo_div; + static const struct { + u32 rf; + u8 mode; + u8 lo_div; + } band_lut[] = { + { 50000000, 0xe1, 16}, /* AM_MODE2, antenna 2 */ + {108000000, 0x42, 32}, /* VHF_MODE */ + {330000000, 0x44, 16}, /* B3_MODE */ + {960000000, 0x48, 4}, /* B45_MODE */ + { ~0U, 0x50, 2}, /* BL_MODE */ + }; + static const struct { + u32 freq; + u8 filter_mode; + } if_freq_lut[] = { + { 0, 0x03}, /* Zero IF */ + { 450000, 0x02}, /* 450 kHz IF */ + {1620000, 0x01}, /* 1.62 MHz IF */ + {2048000, 0x00}, /* 2.048 MHz IF */ + }; + static const struct { + u32 freq; + u8 val; + } bandwidth_lut[] = { + { 200000, 0x00}, /* 200 kHz */ + { 300000, 0x01}, /* 300 kHz */ + { 600000, 0x02}, /* 600 kHz */ + {1536000, 0x03}, /* 1.536 MHz */ + {5000000, 0x04}, /* 5 MHz */ + {6000000, 0x05}, /* 6 MHz */ + {7000000, 0x06}, /* 7 MHz */ + {8000000, 0x07}, /* 8 MHz */ + }; + + unsigned int f_rf = s->f_tuner; + + /* + * bandwidth (Hz) + * 200000, 300000, 600000, 1536000, 5000000, 6000000, 7000000, 8000000 + */ + unsigned int bandwidth; + + /* + * intermediate frequency (Hz) + * 0, 450000, 1620000, 2048000 + */ + unsigned int f_if = 0; + #define F_REF 24000000 + #define R_REF 4 + #define F_OUT_STEP 1 + + dev_dbg(&s->spi->dev, + "%s: f_rf=%d f_if=%d\n", + __func__, f_rf, f_if); + + for (i = 0; i < ARRAY_SIZE(band_lut); i++) { + if (f_rf <= band_lut[i].rf) { + mode = band_lut[i].mode; + lo_div = band_lut[i].lo_div; + break; + } + } + + if (i == ARRAY_SIZE(band_lut)) { + ret = -EINVAL; + goto err; + } + + /* AM_MODE is upconverted */ + if ((mode >> 0) & 0x1) + f_if1 = 5 * F_REF; + else + f_if1 = 0; + + for (i = 0; i < ARRAY_SIZE(if_freq_lut); i++) { + if (f_if == if_freq_lut[i].freq) { + filter_mode = if_freq_lut[i].filter_mode; + break; + } + } + + if (i == ARRAY_SIZE(if_freq_lut)) { + ret = -EINVAL; + goto err; + } + + /* filters */ + bandwidth = s->bandwidth->val; + bandwidth = clamp(bandwidth, 200000U, 8000000U); + + for (i = 0; i < ARRAY_SIZE(bandwidth_lut); i++) { + if (bandwidth <= bandwidth_lut[i].freq) { + bandwidth = bandwidth_lut[i].val; + break; + } + } + + if (i == ARRAY_SIZE(bandwidth_lut)) { + ret = -EINVAL; + goto err; + } + + s->bandwidth->val = bandwidth_lut[i].freq; + + dev_dbg(&s->spi->dev, "%s: bandwidth selected=%d\n", + __func__, bandwidth_lut[i].freq); + + f_vco = (f_rf + f_if + f_if1) * lo_div; + tmp64 = f_vco; + m = do_div(tmp64, F_REF * R_REF); + n = (unsigned int) tmp64; + + vco_step = F_OUT_STEP * lo_div; + thresh = (F_REF * R_REF) / vco_step; + frac = 1ul * thresh * m / (F_REF * R_REF); + + /* Find out greatest common divisor and divide to smaller. */ + tmp = gcd(thresh, frac); + thresh /= tmp; + frac /= tmp; + + /* Force divide to reg max. Resolution will be reduced. */ + tmp = DIV_ROUND_UP(thresh, 4095); + thresh = DIV_ROUND_CLOSEST(thresh, tmp); + frac = DIV_ROUND_CLOSEST(frac, tmp); + + /* calc real RF set */ + tmp = 1ul * F_REF * R_REF * n; + tmp += 1ul * F_REF * R_REF * frac / thresh; + tmp /= lo_div; + + dev_dbg(&s->spi->dev, + "%s: rf=%u:%u n=%d thresh=%d frac=%d\n", + __func__, f_rf, tmp, n, thresh, frac); + + ret = msi001_wreg(s, 0x00000e); + if (ret) + goto err; + + ret = msi001_wreg(s, 0x000003); + if (ret) + goto err; + + reg = 0 << 0; + reg |= mode << 4; + reg |= filter_mode << 12; + reg |= bandwidth << 14; + reg |= 0x02 << 17; + reg |= 0x00 << 20; + ret = msi001_wreg(s, reg); + if (ret) + goto err; + + reg = 5 << 0; + reg |= thresh << 4; + reg |= 1 << 19; + reg |= 1 << 21; + ret = msi001_wreg(s, reg); + if (ret) + goto err; + + reg = 2 << 0; + reg |= frac << 4; + reg |= n << 16; + ret = msi001_wreg(s, reg); + if (ret) + goto err; + + ret = msi001_set_gain(s, s->lna_gain->cur.val, s->mixer_gain->cur.val, + s->if_gain->cur.val); + if (ret) + goto err; + + reg = 6 << 0; + reg |= 63 << 4; + reg |= 4095 << 10; + ret = msi001_wreg(s, reg); + if (ret) + goto err; + + return 0; +err: + dev_dbg(&s->spi->dev, "%s: failed %d\n", __func__, ret); + return ret; +}; + +static int msi001_s_power(struct v4l2_subdev *sd, int on) +{ + struct msi001 *s = sd_to_msi001(sd); + int ret; + dev_dbg(&s->spi->dev, "%s: on=%d\n", __func__, on); + + if (on) + ret = 0; + else + ret = msi001_wreg(s, 0x000000); + + return ret; +} + +static const struct v4l2_subdev_core_ops msi001_core_ops = { + .s_power = msi001_s_power, +}; + +static int msi001_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *v) +{ + struct msi001 *s = sd_to_msi001(sd); + dev_dbg(&s->spi->dev, "%s: index=%d\n", __func__, v->index); + + strlcpy(v->name, "Mirics MSi001", sizeof(v->name)); + v->type = V4L2_TUNER_RF; + v->capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS; + v->rangelow = 49000000; + v->rangehigh = 960000000; + + return 0; +} + +static int msi001_s_tuner(struct v4l2_subdev *sd, const struct v4l2_tuner *v) +{ + struct msi001 *s = sd_to_msi001(sd); + dev_dbg(&s->spi->dev, "%s: index=%d\n", __func__, v->index); + return 0; +} + +static int msi001_g_frequency(struct v4l2_subdev *sd, struct v4l2_frequency *f) +{ + struct msi001 *s = sd_to_msi001(sd); + dev_dbg(&s->spi->dev, "%s: tuner=%d\n", __func__, f->tuner); + f->frequency = s->f_tuner; + return 0; +} + +static int msi001_s_frequency(struct v4l2_subdev *sd, + const struct v4l2_frequency *f) +{ + struct msi001 *s = sd_to_msi001(sd); + unsigned int band; + dev_dbg(&s->spi->dev, "%s: tuner=%d type=%d frequency=%u\n", + __func__, f->tuner, f->type, f->frequency); + + if (f->frequency < ((bands[0].rangehigh + bands[1].rangelow) / 2)) + band = 0; + else + band = 1; + s->f_tuner = clamp_t(unsigned int, f->frequency, + bands[band].rangelow, bands[band].rangehigh); + + return msi001_set_tuner(s); +} + +static int msi001_enum_freq_bands(struct v4l2_subdev *sd, + struct v4l2_frequency_band *band) +{ + struct msi001 *s = sd_to_msi001(sd); + dev_dbg(&s->spi->dev, "%s: tuner=%d type=%d index=%d\n", + __func__, band->tuner, band->type, band->index); + + if (band->index >= ARRAY_SIZE(bands)) + return -EINVAL; + + band->capability = bands[band->index].capability; + band->rangelow = bands[band->index].rangelow; + band->rangehigh = bands[band->index].rangehigh; + + return 0; +} + +static const struct v4l2_subdev_tuner_ops msi001_tuner_ops = { + .g_tuner = msi001_g_tuner, + .s_tuner = msi001_s_tuner, + .g_frequency = msi001_g_frequency, + .s_frequency = msi001_s_frequency, + .enum_freq_bands = msi001_enum_freq_bands, +}; + +static const struct v4l2_subdev_ops msi001_ops = { + .core = &msi001_core_ops, + .tuner = &msi001_tuner_ops, +}; + +static int msi001_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct msi001 *s = container_of(ctrl->handler, struct msi001, hdl); + + int ret; + dev_dbg(&s->spi->dev, + "%s: id=%d name=%s val=%d min=%d max=%d step=%d\n", + __func__, ctrl->id, ctrl->name, ctrl->val, + ctrl->minimum, ctrl->maximum, ctrl->step); + + switch (ctrl->id) { + case V4L2_CID_RF_TUNER_BANDWIDTH_AUTO: + case V4L2_CID_RF_TUNER_BANDWIDTH: + ret = msi001_set_tuner(s); + break; + case V4L2_CID_RF_TUNER_LNA_GAIN: + ret = msi001_set_gain(s, s->lna_gain->val, + s->mixer_gain->cur.val, s->if_gain->cur.val); + break; + case V4L2_CID_RF_TUNER_MIXER_GAIN: + ret = msi001_set_gain(s, s->lna_gain->cur.val, + s->mixer_gain->val, s->if_gain->cur.val); + break; + case V4L2_CID_RF_TUNER_IF_GAIN: + ret = msi001_set_gain(s, s->lna_gain->cur.val, + s->mixer_gain->cur.val, s->if_gain->val); + break; + default: + dev_dbg(&s->spi->dev, "%s: unkown control %d\n", + __func__, ctrl->id); + ret = -EINVAL; + } + + return ret; +} + +static const struct v4l2_ctrl_ops msi001_ctrl_ops = { + .s_ctrl = msi001_s_ctrl, +}; + +static int msi001_probe(struct spi_device *spi) +{ + struct msi001 *s; + int ret; + dev_dbg(&spi->dev, "%s:\n", __func__); + + s = kzalloc(sizeof(struct msi001), GFP_KERNEL); + if (s == NULL) { + ret = -ENOMEM; + dev_dbg(&spi->dev, "Could not allocate memory for msi001\n"); + goto err_kfree; + } + + s->spi = spi; + v4l2_spi_subdev_init(&s->sd, spi, &msi001_ops); + + /* Register controls */ + v4l2_ctrl_handler_init(&s->hdl, 5); + s->bandwidth_auto = v4l2_ctrl_new_std(&s->hdl, &msi001_ctrl_ops, + V4L2_CID_RF_TUNER_BANDWIDTH_AUTO, 0, 1, 1, 1); + s->bandwidth = v4l2_ctrl_new_std(&s->hdl, &msi001_ctrl_ops, + V4L2_CID_RF_TUNER_BANDWIDTH, 200000, 8000000, 1, 200000); + v4l2_ctrl_auto_cluster(2, &s->bandwidth_auto, 0, false); + s->lna_gain = v4l2_ctrl_new_std(&s->hdl, &msi001_ctrl_ops, + V4L2_CID_RF_TUNER_LNA_GAIN, 0, 1, 1, 1); + s->mixer_gain = v4l2_ctrl_new_std(&s->hdl, &msi001_ctrl_ops, + V4L2_CID_RF_TUNER_MIXER_GAIN, 0, 1, 1, 1); + s->if_gain = v4l2_ctrl_new_std(&s->hdl, &msi001_ctrl_ops, + V4L2_CID_RF_TUNER_IF_GAIN, 0, 59, 1, 0); + if (s->hdl.error) { + ret = s->hdl.error; + dev_err(&s->spi->dev, "Could not initialize controls\n"); + /* control init failed, free handler */ + goto err_ctrl_handler_free; + } + + s->sd.ctrl_handler = &s->hdl; + return 0; + +err_ctrl_handler_free: + v4l2_ctrl_handler_free(&s->hdl); +err_kfree: + kfree(s); + return ret; +} + +static int msi001_remove(struct spi_device *spi) +{ + struct v4l2_subdev *sd = spi_get_drvdata(spi); + struct msi001 *s = sd_to_msi001(sd); + dev_dbg(&spi->dev, "%s:\n", __func__); + + /* + * Registered by v4l2_spi_new_subdev() from master driver, but we must + * unregister it from here. Weird. + */ + v4l2_device_unregister_subdev(&s->sd); + v4l2_ctrl_handler_free(&s->hdl); + kfree(s); + return 0; +} + +static const struct spi_device_id msi001_id[] = { + {"msi001", 0}, + {} +}; +MODULE_DEVICE_TABLE(spi, msi001_id); + +static struct spi_driver msi001_driver = { + .driver = { + .name = "msi001", + .owner = THIS_MODULE, + }, + .probe = msi001_probe, + .remove = msi001_remove, + .id_table = msi001_id, +}; +module_spi_driver(msi001_driver); + +MODULE_AUTHOR("Antti Palosaari "); +MODULE_DESCRIPTION("Mirics MSi001"); +MODULE_LICENSE("GPL"); -- cgit v1.1 From 2e68f841a5d147a4273a46e1737bb09d3abdbde0 Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Sun, 2 Feb 2014 23:42:00 -0300 Subject: [media] msi3101: use msi001 tuner driver Remove MSi001 RF tuner related code as MSi001 functionality is moved to own driver. Implement SPI master adapter. Attach MSi001 driver via SPI / V4L subdev framework. Signed-off-by: Antti Palosaari Acked-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/staging/media/msi3101/Kconfig | 3 +- drivers/staging/media/msi3101/sdr-msi3101.c | 483 ++++++++-------------------- 2 files changed, 136 insertions(+), 350 deletions(-) diff --git a/drivers/staging/media/msi3101/Kconfig b/drivers/staging/media/msi3101/Kconfig index 97d5210..de0b3bb 100644 --- a/drivers/staging/media/msi3101/Kconfig +++ b/drivers/staging/media/msi3101/Kconfig @@ -1,8 +1,9 @@ config USB_MSI3101 tristate "Mirics MSi3101 SDR Dongle" - depends on USB && VIDEO_DEV && VIDEO_V4L2 + depends on USB && VIDEO_DEV && VIDEO_V4L2 && SPI select VIDEOBUF2_CORE select VIDEOBUF2_VMALLOC + select MEDIA_TUNER_MSI001 config MEDIA_TUNER_MSI001 tristate "Mirics MSi001" diff --git a/drivers/staging/media/msi3101/sdr-msi3101.c b/drivers/staging/media/msi3101/sdr-msi3101.c index cf71e7e..2135940 100644 --- a/drivers/staging/media/msi3101/sdr-msi3101.c +++ b/drivers/staging/media/msi3101/sdr-msi3101.c @@ -25,7 +25,6 @@ #include #include -#include #include #include #include @@ -33,6 +32,7 @@ #include #include #include +#include /* * iConfiguration 0 @@ -57,7 +57,7 @@ #define V4L2_PIX_FMT_SDR_S14 v4l2_fourcc('D', 'S', '1', '4') /* signed 14-bit */ #define V4L2_PIX_FMT_SDR_MSI2500_384 v4l2_fourcc('M', '3', '8', '4') /* Mirics MSi2500 format 384 */ -static const struct v4l2_frequency_band bands_adc[] = { +static const struct v4l2_frequency_band bands[] = { { .tuner = 0, .type = V4L2_TUNER_ADC, @@ -68,24 +68,6 @@ static const struct v4l2_frequency_band bands_adc[] = { }, }; -static const struct v4l2_frequency_band bands_rf[] = { - { - .tuner = 1, - .type = V4L2_TUNER_RF, - .index = 0, - .capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS, - .rangelow = 49000000, - .rangehigh = 263000000, - }, { - .tuner = 1, - .type = V4L2_TUNER_RF, - .index = 1, - .capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS, - .rangelow = 390000000, - .rangehigh = 960000000, - }, -}; - /* stream formats */ struct msi3101_format { char *name; @@ -128,6 +110,8 @@ struct msi3101_frame_buf { struct msi3101_state { struct video_device vdev; struct v4l2_device v4l2_dev; + struct v4l2_subdev *v4l2_subdev; + struct spi_master *master; /* videobuf2 queue and queued buffers list */ struct vb2_queue vb_queue; @@ -141,7 +125,7 @@ struct msi3101_state { /* Pointer to our usb_device, will be NULL after unplug */ struct usb_device *udev; /* Both mutexes most be hold when setting! */ - unsigned int f_adc, f_tuner; + unsigned int f_adc; u32 pixelformat; unsigned int isoc_errors; /* number of contiguous ISOC errors */ @@ -153,14 +137,6 @@ struct msi3101_state { /* Controls */ struct v4l2_ctrl_handler hdl; - struct v4l2_ctrl *bandwidth_auto; - struct v4l2_ctrl *bandwidth; - struct v4l2_ctrl *lna_gain_auto; - struct v4l2_ctrl *lna_gain; - struct v4l2_ctrl *mixer_gain_auto; - struct v4l2_ctrl *mixer_gain; - struct v4l2_ctrl *if_gain_auto; - struct v4l2_ctrl *if_gain; u32 next_sample; /* for track lost packets */ u32 sample; /* for sample rate calc */ @@ -822,9 +798,9 @@ static void msi3101_disconnect(struct usb_interface *intf) mutex_lock(&s->v4l2_lock); /* No need to keep the urbs around after disconnection */ s->udev = NULL; - v4l2_device_disconnect(&s->v4l2_dev); video_unregister_device(&s->vdev); + spi_unregister_master(s->master); mutex_unlock(&s->v4l2_lock); mutex_unlock(&s->vb_queue_lock); @@ -924,20 +900,25 @@ static int msi3101_ctrl_msg(struct msi3101_state *s, u8 cmd, u32 data) return ret; }; -static int msi3101_tuner_write(struct msi3101_state *s, u32 data) -{ - return msi3101_ctrl_msg(s, CMD_WREG, data << 8 | 0x09); -}; - #define F_REF 24000000 #define DIV_R_IN 2 static int msi3101_set_usb_adc(struct msi3101_state *s) { int ret, div_n, div_m, div_r_out, f_sr, f_vco, fract; u32 reg3, reg4, reg7; + struct v4l2_ctrl *bandwidth_auto; + struct v4l2_ctrl *bandwidth; f_sr = s->f_adc; + /* set tuner, subdev, filters according to sampling rate */ + bandwidth_auto = v4l2_ctrl_find(&s->hdl, V4L2_CID_RF_TUNER_BANDWIDTH_AUTO); + bandwidth = v4l2_ctrl_find(&s->hdl, V4L2_CID_RF_TUNER_BANDWIDTH); + if (v4l2_ctrl_g_ctrl(bandwidth_auto)) { + bandwidth = v4l2_ctrl_find(&s->hdl, V4L2_CID_RF_TUNER_BANDWIDTH); + v4l2_ctrl_s_ctrl(bandwidth, s->f_adc); + } + /* select stream format */ switch (s->pixelformat) { case V4L2_SDR_FMT_CU8: @@ -1066,222 +1047,6 @@ err: return ret; }; -static int msi3101_set_gain(struct msi3101_state *s) -{ - int ret; - u32 reg; - dev_dbg(&s->udev->dev, "%s: lna=%d mixer=%d if=%d\n", __func__, - s->lna_gain->val, s->mixer_gain->val, s->if_gain->val); - - reg = 1 << 0; - reg |= (59 - s->if_gain->val) << 4; - reg |= 0 << 10; - reg |= (1 - s->mixer_gain->val) << 12; - reg |= (1 - s->lna_gain->val) << 13; - reg |= 4 << 14; - reg |= 0 << 17; - ret = msi3101_tuner_write(s, reg); - if (ret) - goto err; - - return 0; -err: - dev_dbg(&s->udev->dev, "%s: failed %d\n", __func__, ret); - return ret; -}; - -static int msi3101_set_tuner(struct msi3101_state *s) -{ - int ret, i; - unsigned int n, m, thresh, frac, vco_step, tmp, f_if1; - u32 reg; - u64 f_vco, tmp64; - u8 mode, filter_mode, lo_div; - static const struct { - u32 rf; - u8 mode; - u8 lo_div; - } band_lut[] = { - { 50000000, 0xe1, 16}, /* AM_MODE2, antenna 2 */ - {108000000, 0x42, 32}, /* VHF_MODE */ - {330000000, 0x44, 16}, /* B3_MODE */ - {960000000, 0x48, 4}, /* B45_MODE */ - { ~0U, 0x50, 2}, /* BL_MODE */ - }; - static const struct { - u32 freq; - u8 filter_mode; - } if_freq_lut[] = { - { 0, 0x03}, /* Zero IF */ - { 450000, 0x02}, /* 450 kHz IF */ - {1620000, 0x01}, /* 1.62 MHz IF */ - {2048000, 0x00}, /* 2.048 MHz IF */ - }; - static const struct { - u32 freq; - u8 val; - } bandwidth_lut[] = { - { 200000, 0x00}, /* 200 kHz */ - { 300000, 0x01}, /* 300 kHz */ - { 600000, 0x02}, /* 600 kHz */ - {1536000, 0x03}, /* 1.536 MHz */ - {5000000, 0x04}, /* 5 MHz */ - {6000000, 0x05}, /* 6 MHz */ - {7000000, 0x06}, /* 7 MHz */ - {8000000, 0x07}, /* 8 MHz */ - }; - - unsigned int f_rf = s->f_tuner; - - /* - * bandwidth (Hz) - * 200000, 300000, 600000, 1536000, 5000000, 6000000, 7000000, 8000000 - */ - unsigned int bandwidth; - - /* - * intermediate frequency (Hz) - * 0, 450000, 1620000, 2048000 - */ - unsigned int f_if = 0; - - dev_dbg(&s->udev->dev, - "%s: f_rf=%d f_if=%d\n", - __func__, f_rf, f_if); - - ret = -EINVAL; - - for (i = 0; i < ARRAY_SIZE(band_lut); i++) { - if (f_rf <= band_lut[i].rf) { - mode = band_lut[i].mode; - lo_div = band_lut[i].lo_div; - break; - } - } - - if (i == ARRAY_SIZE(band_lut)) - goto err; - - /* AM_MODE is upconverted */ - if ((mode >> 0) & 0x1) - f_if1 = 5 * F_REF; - else - f_if1 = 0; - - for (i = 0; i < ARRAY_SIZE(if_freq_lut); i++) { - if (f_if == if_freq_lut[i].freq) { - filter_mode = if_freq_lut[i].filter_mode; - break; - } - } - - if (i == ARRAY_SIZE(if_freq_lut)) - goto err; - - /* filters */ - if (s->bandwidth_auto->val) - bandwidth = s->f_adc; - else - bandwidth = s->bandwidth->val; - - bandwidth = clamp(bandwidth, 200000U, 8000000U); - - for (i = 0; i < ARRAY_SIZE(bandwidth_lut); i++) { - if (bandwidth <= bandwidth_lut[i].freq) { - bandwidth = bandwidth_lut[i].val; - break; - } - } - - if (i == ARRAY_SIZE(bandwidth_lut)) - goto err; - - s->bandwidth->val = bandwidth_lut[i].freq; - - dev_dbg(&s->udev->dev, "%s: bandwidth selected=%d\n", - __func__, bandwidth_lut[i].freq); - -#define F_OUT_STEP 1 -#define R_REF 4 - f_vco = (f_rf + f_if + f_if1) * lo_div; - - tmp64 = f_vco; - m = do_div(tmp64, F_REF * R_REF); - n = (unsigned int) tmp64; - - vco_step = F_OUT_STEP * lo_div; - thresh = (F_REF * R_REF) / vco_step; - frac = 1ul * thresh * m / (F_REF * R_REF); - - /* Find out greatest common divisor and divide to smaller. */ - tmp = gcd(thresh, frac); - thresh /= tmp; - frac /= tmp; - - /* Force divide to reg max. Resolution will be reduced. */ - tmp = DIV_ROUND_UP(thresh, 4095); - thresh = DIV_ROUND_CLOSEST(thresh, tmp); - frac = DIV_ROUND_CLOSEST(frac, tmp); - - /* calc real RF set */ - tmp = 1ul * F_REF * R_REF * n; - tmp += 1ul * F_REF * R_REF * frac / thresh; - tmp /= lo_div; - - dev_dbg(&s->udev->dev, - "%s: rf=%u:%u n=%d thresh=%d frac=%d\n", - __func__, f_rf, tmp, n, thresh, frac); - - ret = msi3101_tuner_write(s, 0x00000e); - if (ret) - goto err; - - ret = msi3101_tuner_write(s, 0x000003); - if (ret) - goto err; - - reg = 0 << 0; - reg |= mode << 4; - reg |= filter_mode << 12; - reg |= bandwidth << 14; - reg |= 0x02 << 17; - reg |= 0x00 << 20; - ret = msi3101_tuner_write(s, reg); - if (ret) - goto err; - - reg = 5 << 0; - reg |= thresh << 4; - reg |= 1 << 19; - reg |= 1 << 21; - ret = msi3101_tuner_write(s, reg); - if (ret) - goto err; - - reg = 2 << 0; - reg |= frac << 4; - reg |= n << 16; - ret = msi3101_tuner_write(s, reg); - if (ret) - goto err; - - ret = msi3101_set_gain(s); - if (ret) - goto err; - - reg = 6 << 0; - reg |= 63 << 4; - reg |= 4095 << 10; - ret = msi3101_tuner_write(s, reg); - if (ret) - goto err; - - return 0; -err: - dev_dbg(&s->udev->dev, "%s: failed %d\n", __func__, ret); - return ret; -}; - static int msi3101_start_streaming(struct vb2_queue *vq, unsigned int count) { struct msi3101_state *s = vb2_get_drv_priv(vq); @@ -1294,6 +1059,9 @@ static int msi3101_start_streaming(struct vb2_queue *vq, unsigned int count) if (mutex_lock_interruptible(&s->v4l2_lock)) return -ERESTARTSYS; + /* wake-up tuner */ + v4l2_subdev_call(s->v4l2_subdev, core, s_power, 1); + ret = msi3101_set_usb_adc(s); ret = msi3101_isoc_init(s); @@ -1328,7 +1096,7 @@ static int msi3101_stop_streaming(struct vb2_queue *vq) msi3101_ctrl_msg(s, CMD_WREG, 0x01000003); /* sleep tuner */ - msi3101_tuner_write(s, 0x000000); + v4l2_subdev_call(s->v4l2_subdev, core, s_power, 0); mutex_unlock(&s->v4l2_lock); @@ -1418,33 +1186,39 @@ static int msi3101_s_tuner(struct file *file, void *priv, const struct v4l2_tuner *v) { struct msi3101_state *s = video_drvdata(file); - dev_dbg(&s->udev->dev, "%s:\n", __func__); + int ret; + dev_dbg(&s->udev->dev, "%s: index=%d\n", __func__, v->index); - return 0; + if (v->index == 0) + ret = 0; + else if (v->index == 1) + ret = v4l2_subdev_call(s->v4l2_subdev, tuner, s_tuner, v); + else + ret = -EINVAL; + + return ret; } static int msi3101_g_tuner(struct file *file, void *priv, struct v4l2_tuner *v) { struct msi3101_state *s = video_drvdata(file); - dev_dbg(&s->udev->dev, "%s:\n", __func__); + int ret; + dev_dbg(&s->udev->dev, "%s: index=%d\n", __func__, v->index); if (v->index == 0) { - strlcpy(v->name, "ADC: Mirics MSi2500", sizeof(v->name)); + strlcpy(v->name, "Mirics MSi2500", sizeof(v->name)); v->type = V4L2_TUNER_ADC; v->capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS; v->rangelow = 1200000; v->rangehigh = 15000000; + ret = 0; } else if (v->index == 1) { - strlcpy(v->name, "RF: Mirics MSi001", sizeof(v->name)); - v->type = V4L2_TUNER_RF; - v->capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS; - v->rangelow = 49000000; - v->rangehigh = 960000000; + ret = v4l2_subdev_call(s->v4l2_subdev, tuner, g_tuner, v); } else { - return -EINVAL; + ret = -EINVAL; } - return 0; + return ret; } static int msi3101_g_frequency(struct file *file, void *priv, @@ -1455,12 +1229,14 @@ static int msi3101_g_frequency(struct file *file, void *priv, dev_dbg(&s->udev->dev, "%s: tuner=%d type=%d\n", __func__, f->tuner, f->type); - if (f->tuner == 0) + if (f->tuner == 0) { f->frequency = s->f_adc; - else if (f->tuner == 1) - f->frequency = s->f_tuner; - else - return -EINVAL; + ret = 0; + } else if (f->tuner == 1) { + ret = v4l2_subdev_call(s->v4l2_subdev, tuner, g_frequency, f); + } else { + ret = -EINVAL; + } return ret; } @@ -1469,31 +1245,21 @@ static int msi3101_s_frequency(struct file *file, void *priv, const struct v4l2_frequency *f) { struct msi3101_state *s = video_drvdata(file); - int ret, band; + int ret; dev_dbg(&s->udev->dev, "%s: tuner=%d type=%d frequency=%u\n", __func__, f->tuner, f->type, f->frequency); if (f->tuner == 0) { s->f_adc = clamp_t(unsigned int, f->frequency, - bands_adc[0].rangelow, - bands_adc[0].rangehigh); + bands[0].rangelow, + bands[0].rangehigh); dev_dbg(&s->udev->dev, "%s: ADC frequency=%u Hz\n", __func__, s->f_adc); ret = msi3101_set_usb_adc(s); } else if (f->tuner == 1) { - #define BAND_RF_0 ((bands_rf[0].rangehigh + bands_rf[1].rangelow) / 2) - if (f->frequency < BAND_RF_0) - band = 0; - else - band = 1; - s->f_tuner = clamp_t(unsigned int, f->frequency, - bands_rf[band].rangelow, - bands_rf[band].rangehigh); - dev_dbg(&s->udev->dev, "%s: RF frequency=%u Hz\n", - __func__, f->frequency); - ret = msi3101_set_tuner(s); + ret = v4l2_subdev_call(s->v4l2_subdev, tuner, s_frequency, f); } else { - return -EINVAL; + ret = -EINVAL; } return ret; @@ -1503,24 +1269,25 @@ static int msi3101_enum_freq_bands(struct file *file, void *priv, struct v4l2_frequency_band *band) { struct msi3101_state *s = video_drvdata(file); + int ret; dev_dbg(&s->udev->dev, "%s: tuner=%d type=%d index=%d\n", __func__, band->tuner, band->type, band->index); if (band->tuner == 0) { - if (band->index >= ARRAY_SIZE(bands_adc)) - return -EINVAL; - - *band = bands_adc[band->index]; + if (band->index >= ARRAY_SIZE(bands)) { + ret = -EINVAL; + } else { + *band = bands[band->index]; + ret = 0; + } } else if (band->tuner == 1) { - if (band->index >= ARRAY_SIZE(bands_rf)) - return -EINVAL; - - *band = bands_rf[band->index]; + ret = v4l2_subdev_call(s->v4l2_subdev, tuner, + enum_freq_bands, band); } else { - return -EINVAL; + ret = -EINVAL; } - return 0; + return ret; } static const struct v4l2_ioctl_ops msi3101_ioctl_ops = { @@ -1570,39 +1337,6 @@ static struct video_device msi3101_template = { .ioctl_ops = &msi3101_ioctl_ops, }; -static int msi3101_s_ctrl(struct v4l2_ctrl *ctrl) -{ - struct msi3101_state *s = - container_of(ctrl->handler, struct msi3101_state, - hdl); - int ret; - dev_dbg(&s->udev->dev, - "%s: id=%d name=%s val=%d min=%d max=%d step=%d\n", - __func__, ctrl->id, ctrl->name, ctrl->val, - ctrl->minimum, ctrl->maximum, ctrl->step); - - switch (ctrl->id) { - case V4L2_CID_RF_TUNER_BANDWIDTH_AUTO: - case V4L2_CID_RF_TUNER_BANDWIDTH: - ret = msi3101_set_tuner(s); - break; - case V4L2_CID_RF_TUNER_LNA_GAIN: - case V4L2_CID_RF_TUNER_MIXER_GAIN: - case V4L2_CID_RF_TUNER_IF_GAIN: - ret = msi3101_set_gain(s); - break; - default: - dev_dbg(&s->udev->dev, "%s: EINVAL\n", __func__); - ret = -EINVAL; - } - - return ret; -} - -static const struct v4l2_ctrl_ops msi3101_ctrl_ops = { - .s_ctrl = msi3101_s_ctrl, -}; - static void msi3101_video_release(struct v4l2_device *v) { struct msi3101_state *s = @@ -1613,13 +1347,43 @@ static void msi3101_video_release(struct v4l2_device *v) kfree(s); } +static int msi3101_transfer_one_message(struct spi_master *master, + struct spi_message *m) +{ + struct msi3101_state *s = spi_master_get_devdata(master); + struct spi_transfer *t; + int ret = 0; + u32 data; + + list_for_each_entry(t, &m->transfers, transfer_list) { + dev_dbg(&s->udev->dev, "%s: msg=%*ph\n", + __func__, t->len, t->tx_buf); + data = 0x09; /* reg 9 is SPI adapter */ + data |= ((u8 *)t->tx_buf)[0] << 8; + data |= ((u8 *)t->tx_buf)[1] << 16; + data |= ((u8 *)t->tx_buf)[2] << 24; + ret = msi3101_ctrl_msg(s, CMD_WREG, data); + } + + m->status = ret; + spi_finalize_current_message(master); + return ret; +} + static int msi3101_probe(struct usb_interface *intf, const struct usb_device_id *id) { struct usb_device *udev = interface_to_usbdev(intf); struct msi3101_state *s = NULL; - const struct v4l2_ctrl_ops *ops = &msi3101_ctrl_ops; + struct v4l2_subdev *sd; + struct spi_master *master; int ret; + static struct spi_board_info board_info = { + .modalias = "msi001", + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 12000000, + }; s = kzalloc(sizeof(struct msi3101_state), GFP_KERNEL); if (s == NULL) { @@ -1632,7 +1396,7 @@ static int msi3101_probe(struct usb_interface *intf, spin_lock_init(&s->queued_bufs_lock); INIT_LIST_HEAD(&s->queued_bufs); s->udev = udev; - s->f_adc = bands_adc[0].rangelow; + s->f_adc = bands[0].rangelow; s->pixelformat = V4L2_SDR_FMT_CU8; /* Init videobuf2 queue structure */ @@ -1656,34 +1420,53 @@ static int msi3101_probe(struct usb_interface *intf, set_bit(V4L2_FL_USE_FH_PRIO, &s->vdev.flags); video_set_drvdata(&s->vdev, s); - /* Register controls */ - v4l2_ctrl_handler_init(&s->hdl, 5); - s->bandwidth_auto = v4l2_ctrl_new_std(&s->hdl, ops, - V4L2_CID_RF_TUNER_BANDWIDTH_AUTO, 0, 1, 1, 1); - s->bandwidth = v4l2_ctrl_new_std(&s->hdl, ops, - V4L2_CID_RF_TUNER_BANDWIDTH, 0, 8000000, 1, 0); - v4l2_ctrl_auto_cluster(2, &s->bandwidth_auto, 0, false); - s->lna_gain = v4l2_ctrl_new_std(&s->hdl, ops, - V4L2_CID_RF_TUNER_LNA_GAIN, 0, 1, 1, 1); - s->mixer_gain = v4l2_ctrl_new_std(&s->hdl, ops, - V4L2_CID_RF_TUNER_MIXER_GAIN, 0, 1, 1, 1); - s->if_gain = v4l2_ctrl_new_std(&s->hdl, ops, - V4L2_CID_RF_TUNER_IF_GAIN, 0, 59, 1, 0); - if (s->hdl.error) { - ret = s->hdl.error; - dev_err(&s->udev->dev, "Could not initialize controls\n"); - goto err_free_controls; - } - /* Register the v4l2_device structure */ s->v4l2_dev.release = msi3101_video_release; ret = v4l2_device_register(&intf->dev, &s->v4l2_dev); if (ret) { dev_err(&s->udev->dev, "Failed to register v4l2-device (%d)\n", ret); + goto err_free_mem; + } + + /* SPI master adapter */ + master = spi_alloc_master(&s->udev->dev, 0); + if (master == NULL) { + ret = -ENOMEM; + goto err_unregister_v4l2_dev; + } + + s->master = master; + master->bus_num = 0; + master->num_chipselect = 1; + master->transfer_one_message = msi3101_transfer_one_message; + spi_master_set_devdata(master, s); + ret = spi_register_master(master); + if (ret) { + spi_master_put(master); + goto err_unregister_v4l2_dev; + } + + /* load v4l2 subdevice */ + sd = v4l2_spi_new_subdev(&s->v4l2_dev, master, &board_info); + s->v4l2_subdev = sd; + if (sd == NULL) { + dev_err(&s->udev->dev, "cannot get v4l2 subdevice\n"); + ret = -ENODEV; + goto err_unregister_master; + } + + /* Register controls */ + v4l2_ctrl_handler_init(&s->hdl, 0); + if (s->hdl.error) { + ret = s->hdl.error; + dev_err(&s->udev->dev, "Could not initialize controls\n"); goto err_free_controls; } + /* currently all controls are from subdev */ + v4l2_ctrl_add_handler(&s->hdl, sd->ctrl_handler, NULL); + s->v4l2_dev.ctrl_handler = &s->hdl; s->vdev.v4l2_dev = &s->v4l2_dev; s->vdev.lock = &s->v4l2_lock; @@ -1700,10 +1483,12 @@ static int msi3101_probe(struct usb_interface *intf, return 0; -err_unregister_v4l2_dev: - v4l2_device_unregister(&s->v4l2_dev); err_free_controls: v4l2_ctrl_handler_free(&s->hdl); +err_unregister_master: + spi_unregister_master(s->master); +err_unregister_v4l2_dev: + v4l2_device_unregister(&s->v4l2_dev); err_free_mem: kfree(s); return ret; -- cgit v1.1 From 19a628a0cfa8f6829c59f3846dfcb17a431dfc3d Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Sun, 2 Feb 2014 23:51:30 -0300 Subject: [media] MAINTAINERS: add msi001 driver Mirics MSi001 silicon tuner driver. Currently in staging as SDR API is not ready. Signed-off-by: Antti Palosaari Acked-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- MAINTAINERS | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index c1c6be8..e7d64cc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5770,6 +5770,16 @@ L: platform-driver-x86@vger.kernel.org S: Supported F: drivers/platform/x86/msi-wmi.c +MSI001 MEDIA DRIVER +M: Antti Palosaari +L: linux-media@vger.kernel.org +W: http://linuxtv.org/ +W: http://palosaari.fi/linux/ +Q: http://patchwork.linuxtv.org/project/linux-media/list/ +T: git git://linuxtv.org/anttip/media_tree.git +S: Maintained +F: drivers/staging/media/msi3101/msi001* + MT9M032 APTINA SENSOR DRIVER M: Laurent Pinchart L: linux-media@vger.kernel.org -- cgit v1.1 From 2c57213fe043d0ed9c8f4709161ac89316e6250a Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Sun, 2 Feb 2014 23:55:12 -0300 Subject: [media] MAINTAINERS: add msi3101 driver Mirics MSi2500 (MSi3101) SDR ADC + USB interface driver. Currently in staging as SDR API is not ready. Signed-off-by: Antti Palosaari Acked-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- MAINTAINERS | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index e7d64cc..3718c32 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5780,6 +5780,16 @@ T: git git://linuxtv.org/anttip/media_tree.git S: Maintained F: drivers/staging/media/msi3101/msi001* +MSI3101 MEDIA DRIVER +M: Antti Palosaari +L: linux-media@vger.kernel.org +W: http://linuxtv.org/ +W: http://palosaari.fi/linux/ +Q: http://patchwork.linuxtv.org/project/linux-media/list/ +T: git git://linuxtv.org/anttip/media_tree.git +S: Maintained +F: drivers/staging/media/msi3101/sdr-msi3101* + MT9M032 APTINA SENSOR DRIVER M: Laurent Pinchart L: linux-media@vger.kernel.org -- cgit v1.1 From d287e4e31ed6374f8899c131075461c3c8cbd8a9 Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Wed, 26 Feb 2014 20:48:23 -0300 Subject: [media] msi3101: clamp mmap buffers to reasonable level That value is coming from the user and we need only ensure it is reasonable. That was pointed by Hans when reviewing rtl2832_sdr driver. Signed-off-by: Antti Palosaari Cc: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/staging/media/msi3101/sdr-msi3101.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/staging/media/msi3101/sdr-msi3101.c b/drivers/staging/media/msi3101/sdr-msi3101.c index 2135940..93e6eba 100644 --- a/drivers/staging/media/msi3101/sdr-msi3101.c +++ b/drivers/staging/media/msi3101/sdr-msi3101.c @@ -831,7 +831,7 @@ static int msi3101_queue_setup(struct vb2_queue *vq, dev_dbg(&s->udev->dev, "%s: *nbuffers=%d\n", __func__, *nbuffers); /* Absolute min and max number of buffers available for mmap() */ - *nbuffers = 32; + *nbuffers = clamp_t(unsigned int, *nbuffers, 8, 32); *nplanes = 1; /* * 3, wMaxPacketSize 3x 1024 bytes -- cgit v1.1 From 952a70aa680799e3f379affaab9504113d2a7ea4 Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Mon, 10 Mar 2014 16:28:18 -0300 Subject: [media] msi001: fix v4l2-compliance issues Fix msi001 driver v4l2-compliance issues. Cc: Hans Verkuil Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- drivers/staging/media/msi3101/msi001.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/staging/media/msi3101/msi001.c b/drivers/staging/media/msi3101/msi001.c index 25feece0..ac43bae 100644 --- a/drivers/staging/media/msi3101/msi001.c +++ b/drivers/staging/media/msi3101/msi001.c @@ -429,6 +429,7 @@ static int msi001_probe(struct spi_device *spi) } s->spi = spi; + s->f_tuner = bands[0].rangelow; v4l2_spi_subdev_init(&s->sd, spi, &msi001_ops); /* Register controls */ -- cgit v1.1 From c350912c8b98922cbf6d4c25989b6a16df54f4c1 Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Mon, 10 Mar 2014 16:30:44 -0300 Subject: [media] msi3101: fix v4l2-compliance issues Fix msi3101 driver v4l2-compliance issues. Cc: Hans Verkuil Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- drivers/staging/media/msi3101/sdr-msi3101.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/staging/media/msi3101/sdr-msi3101.c b/drivers/staging/media/msi3101/sdr-msi3101.c index 93e6eba..011db2c 100644 --- a/drivers/staging/media/msi3101/sdr-msi3101.c +++ b/drivers/staging/media/msi3101/sdr-msi3101.c @@ -1134,6 +1134,7 @@ static int msi3101_g_fmt_sdr_cap(struct file *file, void *priv, dev_dbg(&s->udev->dev, "%s: pixelformat fourcc %4.4s\n", __func__, (char *)&s->pixelformat); + memset(f->fmt.sdr.reserved, 0, sizeof(f->fmt.sdr.reserved)); f->fmt.sdr.pixelformat = s->pixelformat; return 0; @@ -1151,6 +1152,7 @@ static int msi3101_s_fmt_sdr_cap(struct file *file, void *priv, if (vb2_is_busy(q)) return -EBUSY; + memset(f->fmt.sdr.reserved, 0, sizeof(f->fmt.sdr.reserved)); for (i = 0; i < NUM_FORMATS; i++) { if (formats[i].pixelformat == f->fmt.sdr.pixelformat) { s->pixelformat = f->fmt.sdr.pixelformat; @@ -1172,6 +1174,7 @@ static int msi3101_try_fmt_sdr_cap(struct file *file, void *priv, dev_dbg(&s->udev->dev, "%s: pixelformat fourcc %4.4s\n", __func__, (char *)&f->fmt.sdr.pixelformat); + memset(f->fmt.sdr.reserved, 0, sizeof(f->fmt.sdr.reserved)); for (i = 0; i < NUM_FORMATS; i++) { if (formats[i].pixelformat == f->fmt.sdr.pixelformat) return 0; @@ -1233,6 +1236,7 @@ static int msi3101_g_frequency(struct file *file, void *priv, f->frequency = s->f_adc; ret = 0; } else if (f->tuner == 1) { + f->type = V4L2_TUNER_RF; ret = v4l2_subdev_call(s->v4l2_subdev, tuner, g_frequency, f); } else { ret = -EINVAL; -- cgit v1.1 From 87185c958de9cd4acd8392f00d6161f4e11807ff Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Mon, 10 Mar 2014 10:43:24 -0300 Subject: [media] v4l: rename v4l2_format_sdr to v4l2_sdr_format Rename v4l2_format_sdr to v4l2_sdr_format in order to keep it in line with other formats. Reported-by: Hans Verkuil Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/v4l/dev-sdr.xml | 2 +- drivers/media/v4l2-core/v4l2-ioctl.c | 2 +- include/uapi/linux/videodev2.h | 6 +++--- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/Documentation/DocBook/media/v4l/dev-sdr.xml b/Documentation/DocBook/media/v4l/dev-sdr.xml index ac9f1af..524b9c4 100644 --- a/Documentation/DocBook/media/v4l/dev-sdr.xml +++ b/Documentation/DocBook/media/v4l/dev-sdr.xml @@ -78,7 +78,7 @@ of the data format. - struct <structname>v4l2_format_sdr</structname> + struct <structname>v4l2_sdr_format</structname> &cs-str; diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c index 6536e15..d9113cc 100644 --- a/drivers/media/v4l2-core/v4l2-ioctl.c +++ b/drivers/media/v4l2-core/v4l2-ioctl.c @@ -246,7 +246,7 @@ static void v4l_print_format(const void *arg, bool write_only) const struct v4l2_vbi_format *vbi; const struct v4l2_sliced_vbi_format *sliced; const struct v4l2_window *win; - const struct v4l2_format_sdr *sdr; + const struct v4l2_sdr_format *sdr; unsigned i; pr_cont("type=%s", prt_names(p->type, v4l2_type_names)); diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h index 35f4a06..e35ad6c 100644 --- a/include/uapi/linux/videodev2.h +++ b/include/uapi/linux/videodev2.h @@ -1714,10 +1714,10 @@ struct v4l2_pix_format_mplane { } __attribute__ ((packed)); /** - * struct v4l2_format_sdr - SDR format definition + * struct v4l2_sdr_format - SDR format definition * @pixelformat: little endian four character code (fourcc) */ -struct v4l2_format_sdr { +struct v4l2_sdr_format { __u32 pixelformat; __u8 reserved[28]; } __attribute__ ((packed)); @@ -1740,7 +1740,7 @@ struct v4l2_format { struct v4l2_window win; /* V4L2_BUF_TYPE_VIDEO_OVERLAY */ struct v4l2_vbi_format vbi; /* V4L2_BUF_TYPE_VBI_CAPTURE */ struct v4l2_sliced_vbi_format sliced; /* V4L2_BUF_TYPE_SLICED_VBI_CAPTURE */ - struct v4l2_format_sdr sdr; /* V4L2_BUF_TYPE_SDR_CAPTURE */ + struct v4l2_sdr_format sdr; /* V4L2_BUF_TYPE_SDR_CAPTURE */ __u8 raw_data[200]; /* user-defined */ } fmt; }; -- cgit v1.1 From 078c580cb4ab16bc7a3f7a88b51d1da498f899a4 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Fri, 7 Mar 2014 08:40:59 -0300 Subject: [media] DocBook media: update STREAMON/OFF documentation Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- .../DocBook/media/v4l/vidioc-streamon.xml | 28 +++++++++++++++++----- 1 file changed, 22 insertions(+), 6 deletions(-) diff --git a/Documentation/DocBook/media/v4l/vidioc-streamon.xml b/Documentation/DocBook/media/v4l/vidioc-streamon.xml index 65dff55..df2c63d 100644 --- a/Documentation/DocBook/media/v4l/vidioc-streamon.xml +++ b/Documentation/DocBook/media/v4l/vidioc-streamon.xml @@ -52,16 +52,24 @@ The VIDIOC_STREAMON and VIDIOC_STREAMOFF ioctl start and stop the capture or output process during streaming (memory -mapping or user pointer) I/O. +mapping, user pointer or +DMABUF) I/O. - Specifically the capture hardware is disabled and no input + Capture hardware is disabled and no input buffers are filled (if there are any empty buffers in the incoming queue) until VIDIOC_STREAMON has been called. -Accordingly the output hardware is disabled, no video signal is +Output hardware is disabled and no video signal is produced until VIDIOC_STREAMON has been called. The ioctl will succeed when at least one output buffer is in the incoming queue. + Memory-to-memory devices will not start until +VIDIOC_STREAMON has been called for both the capture +and output stream types. + + If VIDIOC_STREAMON fails then any already +queued buffers will remain queued. + The VIDIOC_STREAMOFF ioctl, apart of aborting or finishing any DMA in progress, unlocks any user pointer buffers locked in physical memory, and it removes all buffers from the @@ -70,14 +78,22 @@ dequeued yet will be lost, likewise all images enqueued for output but not transmitted yet. I/O returns to the same state as after calling &VIDIOC-REQBUFS; and can be restarted accordingly. + If buffers have been queued with &VIDIOC-QBUF; and +VIDIOC_STREAMOFF is called without ever having +called VIDIOC_STREAMON, then those queued buffers +will also be removed from the incoming queue and all are returned to the +same state as after calling &VIDIOC-REQBUFS; and can be restarted +accordingly. + Both ioctls take a pointer to an integer, the desired buffer or stream type. This is the same as &v4l2-requestbuffers; type. If VIDIOC_STREAMON is called when streaming is already in progress, or if VIDIOC_STREAMOFF is called -when streaming is already stopped, then the ioctl does nothing and 0 is -returned. +when streaming is already stopped, then 0 is returned. Nothing happens in the +case of VIDIOC_STREAMON, but VIDIOC_STREAMOFF +will return queued buffers to their starting state as mentioned above. Note that applications can be preempted for unknown periods right before or after the VIDIOC_STREAMON or @@ -93,7 +109,7 @@ synchronize with other events. EINVAL - The buffertype is not supported, + The buffer type is not supported, or no buffers have been allocated (memory mapping) or enqueued (output) yet. -- cgit v1.1 From 26092ffb72ed0ca4936dd979f2acf3a8566ccd38 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Sun, 23 Feb 2014 20:12:46 -0300 Subject: [media] DocBook: fix incorrect code example The code said for (i = 0; i > 30; ++i) instead of i < 30. Fix this and clean it up a bit at the same time. Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/v4l/dev-osd.xml | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/Documentation/DocBook/media/v4l/dev-osd.xml b/Documentation/DocBook/media/v4l/dev-osd.xml index dd91d61..5485332 100644 --- a/Documentation/DocBook/media/v4l/dev-osd.xml +++ b/Documentation/DocBook/media/v4l/dev-osd.xml @@ -56,18 +56,18 @@ framebuffer device. unsigned int i; int fb_fd; -if (-1 == ioctl (fd, VIDIOC_G_FBUF, &fbuf)) { - perror ("VIDIOC_G_FBUF"); - exit (EXIT_FAILURE); +if (-1 == ioctl(fd, VIDIOC_G_FBUF, &fbuf)) { + perror("VIDIOC_G_FBUF"); + exit(EXIT_FAILURE); } -for (i = 0; i > 30; ++i) { +for (i = 0; i < 30; i++) { char dev_name[16]; struct fb_fix_screeninfo si; - snprintf (dev_name, sizeof (dev_name), "/dev/fb%u", i); + snprintf(dev_name, sizeof(dev_name), "/dev/fb%u", i); - fb_fd = open (dev_name, O_RDWR); + fb_fd = open(dev_name, O_RDWR); if (-1 == fb_fd) { switch (errno) { case ENOENT: /* no such file */ @@ -75,19 +75,19 @@ for (i = 0; i > 30; ++i) { continue; default: - perror ("open"); - exit (EXIT_FAILURE); + perror("open"); + exit(EXIT_FAILURE); } } - if (0 == ioctl (fb_fd, FBIOGET_FSCREENINFO, &si)) { - if (si.smem_start == (unsigned long) fbuf.base) + if (0 == ioctl(fb_fd, FBIOGET_FSCREENINFO, &si)) { + if (si.smem_start == (unsigned long)fbuf.base) break; } else { /* Apparently not a framebuffer device. */ } - close (fb_fd); + close(fb_fd); fb_fd = -1; } -- cgit v1.1 From 22a437cd6336193d8ffeb4217e9753fb92c7c870 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Fri, 7 Mar 2014 10:16:48 -0300 Subject: [media] DocBook media: clarify v4l2_buffer/plane fields Be more specific as to who has to fill in each field/flag: the driver or the application. Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/v4l/io.xml | 54 ++++++++++++++++++++++------------ 1 file changed, 36 insertions(+), 18 deletions(-) diff --git a/Documentation/DocBook/media/v4l/io.xml b/Documentation/DocBook/media/v4l/io.xml index 49e48be..0a5d8c6 100644 --- a/Documentation/DocBook/media/v4l/io.xml +++ b/Documentation/DocBook/media/v4l/io.xml @@ -676,10 +676,11 @@ plane structures. __u32 index - Number of the buffer, set by the application. This -field is only used for memory mapping I/O -and can range from zero to the number of buffers allocated -with the &VIDIOC-REQBUFS; ioctl (&v4l2-requestbuffers; count) minus one. + Number of the buffer, set by the application except +when calling &VIDIOC-DQBUF;, then it is set by the driver. +This field can range from zero to the number of buffers allocated +with the &VIDIOC-REQBUFS; ioctl (&v4l2-requestbuffers; count), +plus any buffers allocated with &VIDIOC-CREATE-BUFS; minus one. __u32 @@ -698,7 +699,7 @@ linkend="v4l2-buf-type" /> buffer. It depends on the negotiated data format and may change with each buffer for compressed variable size data like JPEG images. Drivers must set this field when type -refers to an input stream, applications when an output stream. +refers to an input stream, applications when it refers to an output stream. __u32 @@ -715,7 +716,7 @@ linkend="buffer-flags" />. buffer, see . This field is not used when the buffer contains VBI data. Drivers must set it when type refers to an input stream, -applications when an output stream. +applications when it refers to an output stream. struct timeval @@ -729,7 +730,9 @@ applications when an output stream. stores the time at which the last data byte was actually sent out in the timestamp field. This permits applications to monitor the drift between the video and system - clock. + clock. For output streams that use V4L2_BUF_FLAG_TIMESTAMP_COPY + the application has to fill in the timestamp which will be copied + by the driver to the capture stream. &v4l2-timecode; @@ -822,7 +825,8 @@ is the file descriptor associated with a DMABUF buffer. length Size of the buffer (not the payload) in bytes for the - single-planar API. For the multi-planar API the application sets + single-planar API. This is set by the driver based on the calls to + &VIDIOC-REQBUFS; and/or &VIDIOC-CREATE-BUFS;. For the multi-planar API the application sets this to the number of elements in the planes array. The driver will fill in the actual number of valid elements in that array. @@ -856,13 +860,15 @@ should set this to 0. bytesused The number of bytes occupied by data in the plane - (its payload). + (its payload). Drivers must set this field when type + refers to an input stream, applications when it refers to an output stream. __u32 length - Size in bytes of the plane (not its payload). + Size in bytes of the plane (not its payload). This is set by the driver + based on the calls to &VIDIOC-REQBUFS; and/or &VIDIOC-CREATE-BUFS;. union @@ -901,7 +907,9 @@ should set this to 0. __u32 data_offset - Offset in bytes to video data in the plane, if applicable. + Offset in bytes to video data in the plane. + Drivers must set this field when type + refers to an input stream, applications when it refers to an output stream. @@ -1031,7 +1039,7 @@ buffer cannot be on both queues at the same time, the V4L2_BUF_FLAG_QUEUED and V4L2_BUF_FLAG_DONE flag are mutually exclusive. They can be both cleared however, then the buffer is in "dequeued" -state, in the application domain to say so. +state, in the application domain so to say. V4L2_BUF_FLAG_ERROR @@ -1049,27 +1057,35 @@ state, in the application domain to say so. Drivers set or clear this flag when calling the VIDIOC_DQBUF ioctl. It may be set by video capture devices when the buffer contains a compressed image which is a -key frame (or field), &ie; can be decompressed on its own. +key frame (or field), &ie; can be decompressed on its own. Also know as +an I-frame. Applications can set this bit when type +refers to an output stream. V4L2_BUF_FLAG_PFRAME 0x00000010 Similar to V4L2_BUF_FLAG_KEYFRAME this flags predicted frames or fields which contain only differences to a -previous key frame. +previous key frame. Applications can set this bit when type +refers to an output stream. V4L2_BUF_FLAG_BFRAME 0x00000020 - Similar to V4L2_BUF_FLAG_PFRAME - this is a bidirectional predicted frame or field. [ooc tbd] + Similar to V4L2_BUF_FLAG_KEYFRAME +this flags a bi-directional predicted frame or field which contains only +the differences between the current frame and both the preceding and following +key frames to specify its content. Applications can set this bit when +type refers to an output stream. V4L2_BUF_FLAG_TIMECODE 0x00000100 The timecode field is valid. Drivers set or clear this flag when the VIDIOC_DQBUF -ioctl is called. +ioctl is called. Applications can set this bit and the corresponding +timecode structure when type +refers to an output stream. V4L2_BUF_FLAG_PREPARED @@ -1141,7 +1157,9 @@ in which case caches have not been used. the frame. Logical 'and' operation between the flags field and V4L2_BUF_FLAG_TSTAMP_SRC_MASK produces the - value of the timestamp source. + value of the timestamp source. Applications must set the timestamp + source when type refers to an output stream + and V4L2_BUF_FLAG_TIMESTAMP_COPY is set. V4L2_BUF_FLAG_TSTAMP_SRC_EOF -- cgit v1.1 From 8ac43395677af08b03b3c5819f968db156a180d5 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Fri, 7 Mar 2014 09:33:28 -0300 Subject: [media] DocBook media: fix broken FIELD_ALTERNATE description The sizeimage is that of a single field, not that of a full frame. That makes no sense, and in fact all drivers supporting ALTERNATE will set sizeimage to that of a field. Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/v4l/io.xml | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/Documentation/DocBook/media/v4l/io.xml b/Documentation/DocBook/media/v4l/io.xml index 0a5d8c6..97a69bf 100644 --- a/Documentation/DocBook/media/v4l/io.xml +++ b/Documentation/DocBook/media/v4l/io.xml @@ -1470,10 +1470,9 @@ or application, depending on data direction, must set &v4l2-buffer; V4L2_FIELD_BOTTOM. Any two successive fields pair to build a frame. If fields are successive, without any dropped fields between them (fields can drop individually), can be determined from -the &v4l2-buffer; sequence field. Image -sizes refer to the frame, not fields. This format cannot be selected -when using the read/write I/O method. +the &v4l2-buffer; sequence field. This format +cannot be selected when using the read/write I/O method since there +is no way to communicate if a field was a top or bottom field. V4L2_FIELD_INTERLACED_TB -- cgit v1.1 From 8ea5488a919bbd49941584f773fd66623192ffc0 Mon Sep 17 00:00:00 2001 From: Kees Cook Date: Tue, 11 Mar 2014 17:25:53 -0300 Subject: [media] media: rc-core: use %s in rc_map_get() module load rc_map_get() takes a single string literal for the module to load, so make sure it cannot be used as a format string in the call to request_module(). Signed-off-by: Kees Cook Signed-off-by: Mauro Carvalho Chehab --- drivers/media/rc/rc-main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/rc/rc-main.c b/drivers/media/rc/rc-main.c index f87e0f0..99697aa 100644 --- a/drivers/media/rc/rc-main.c +++ b/drivers/media/rc/rc-main.c @@ -62,7 +62,7 @@ struct rc_map *rc_map_get(const char *name) map = seek_rc_map(name); #ifdef MODULE if (!map) { - int rc = request_module(name); + int rc = request_module("%s", name); if (rc < 0) { printk(KERN_ERR "Couldn't load IR keymap %s\n", name); return NULL; -- cgit v1.1 From 28fd31f82dccfcfcb4c80fd916d4caf875c04d90 Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Tue, 15 Oct 2013 19:22:45 -0300 Subject: [media] e4000: convert DVB tuner to I2C driver model Driver conversion from proprietary DVB tuner model to more general I2C driver model. Cc: Jean Delvare Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- drivers/media/tuners/e4000.c | 115 ++++++++++++++++++++------------ drivers/media/tuners/e4000.h | 21 ++---- drivers/media/tuners/e4000_priv.h | 5 +- drivers/media/usb/dvb-usb-v2/rtl28xxu.c | 56 +++++++++++++--- drivers/media/usb/dvb-usb-v2/rtl28xxu.h | 1 + 5 files changed, 126 insertions(+), 72 deletions(-) diff --git a/drivers/media/tuners/e4000.c b/drivers/media/tuners/e4000.c index 40c1da7..0153169 100644 --- a/drivers/media/tuners/e4000.c +++ b/drivers/media/tuners/e4000.c @@ -31,7 +31,7 @@ static int e4000_wr_regs(struct e4000_priv *priv, u8 reg, u8 *val, int len) u8 buf[MAX_XFER_SIZE]; struct i2c_msg msg[1] = { { - .addr = priv->cfg->i2c_addr, + .addr = priv->client->addr, .flags = 0, .len = 1 + len, .buf = buf, @@ -39,7 +39,7 @@ static int e4000_wr_regs(struct e4000_priv *priv, u8 reg, u8 *val, int len) }; if (1 + len > sizeof(buf)) { - dev_warn(&priv->i2c->dev, + dev_warn(&priv->client->dev, "%s: i2c wr reg=%04x: len=%d is too big!\n", KBUILD_MODNAME, reg, len); return -EINVAL; @@ -48,11 +48,11 @@ static int e4000_wr_regs(struct e4000_priv *priv, u8 reg, u8 *val, int len) buf[0] = reg; memcpy(&buf[1], val, len); - ret = i2c_transfer(priv->i2c, msg, 1); + ret = i2c_transfer(priv->client->adapter, msg, 1); if (ret == 1) { ret = 0; } else { - dev_warn(&priv->i2c->dev, + dev_warn(&priv->client->dev, "%s: i2c wr failed=%d reg=%02x len=%d\n", KBUILD_MODNAME, ret, reg, len); ret = -EREMOTEIO; @@ -67,12 +67,12 @@ static int e4000_rd_regs(struct e4000_priv *priv, u8 reg, u8 *val, int len) u8 buf[MAX_XFER_SIZE]; struct i2c_msg msg[2] = { { - .addr = priv->cfg->i2c_addr, + .addr = priv->client->addr, .flags = 0, .len = 1, .buf = ®, }, { - .addr = priv->cfg->i2c_addr, + .addr = priv->client->addr, .flags = I2C_M_RD, .len = len, .buf = buf, @@ -80,18 +80,18 @@ static int e4000_rd_regs(struct e4000_priv *priv, u8 reg, u8 *val, int len) }; if (len > sizeof(buf)) { - dev_warn(&priv->i2c->dev, + dev_warn(&priv->client->dev, "%s: i2c rd reg=%04x: len=%d is too big!\n", KBUILD_MODNAME, reg, len); return -EINVAL; } - ret = i2c_transfer(priv->i2c, msg, 2); + ret = i2c_transfer(priv->client->adapter, msg, 2); if (ret == 2) { memcpy(val, buf, len); ret = 0; } else { - dev_warn(&priv->i2c->dev, + dev_warn(&priv->client->dev, "%s: i2c rd failed=%d reg=%02x len=%d\n", KBUILD_MODNAME, ret, reg, len); ret = -EREMOTEIO; @@ -117,7 +117,7 @@ static int e4000_init(struct dvb_frontend *fe) struct e4000_priv *priv = fe->tuner_priv; int ret; - dev_dbg(&priv->i2c->dev, "%s:\n", __func__); + dev_dbg(&priv->client->dev, "%s:\n", __func__); if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 1); @@ -186,7 +186,7 @@ err: if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0); - dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); + dev_dbg(&priv->client->dev, "%s: failed=%d\n", __func__, ret); return ret; } @@ -195,7 +195,7 @@ static int e4000_sleep(struct dvb_frontend *fe) struct e4000_priv *priv = fe->tuner_priv; int ret; - dev_dbg(&priv->i2c->dev, "%s:\n", __func__); + dev_dbg(&priv->client->dev, "%s:\n", __func__); if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 1); @@ -212,7 +212,7 @@ err: if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0); - dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); + dev_dbg(&priv->client->dev, "%s: failed=%d\n", __func__, ret); return ret; } @@ -224,7 +224,7 @@ static int e4000_set_params(struct dvb_frontend *fe) unsigned int f_vco; u8 buf[5], i_data[4], q_data[4]; - dev_dbg(&priv->i2c->dev, + dev_dbg(&priv->client->dev, "%s: delivery_system=%d frequency=%d bandwidth_hz=%d\n", __func__, c->delivery_system, c->frequency, c->bandwidth_hz); @@ -253,14 +253,15 @@ static int e4000_set_params(struct dvb_frontend *fe) * or more. */ f_vco = c->frequency * e4000_pll_lut[i].mul; - sigma_delta = div_u64(0x10000ULL * (f_vco % priv->cfg->clock), priv->cfg->clock); - buf[0] = f_vco / priv->cfg->clock; + sigma_delta = div_u64(0x10000ULL * (f_vco % priv->clock), priv->clock); + buf[0] = f_vco / priv->clock; buf[1] = (sigma_delta >> 0) & 0xff; buf[2] = (sigma_delta >> 8) & 0xff; buf[3] = 0x00; buf[4] = e4000_pll_lut[i].div; - dev_dbg(&priv->i2c->dev, "%s: f_vco=%u pll div=%d sigma_delta=%04x\n", + dev_dbg(&priv->client->dev, + "%s: f_vco=%u pll div=%d sigma_delta=%04x\n", __func__, f_vco, buf[0], sigma_delta); ret = e4000_wr_regs(priv, 0x09, buf, 5); @@ -369,7 +370,7 @@ err: if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0); - dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); + dev_dbg(&priv->client->dev, "%s: failed=%d\n", __func__, ret); return ret; } @@ -377,24 +378,13 @@ static int e4000_get_if_frequency(struct dvb_frontend *fe, u32 *frequency) { struct e4000_priv *priv = fe->tuner_priv; - dev_dbg(&priv->i2c->dev, "%s:\n", __func__); + dev_dbg(&priv->client->dev, "%s:\n", __func__); *frequency = 0; /* Zero-IF */ return 0; } -static int e4000_release(struct dvb_frontend *fe) -{ - struct e4000_priv *priv = fe->tuner_priv; - - dev_dbg(&priv->i2c->dev, "%s:\n", __func__); - - kfree(fe->tuner_priv); - - return 0; -} - static const struct dvb_tuner_ops e4000_tuner_ops = { .info = { .name = "Elonics E4000", @@ -402,8 +392,6 @@ static const struct dvb_tuner_ops e4000_tuner_ops = { .frequency_max = 862000000, }, - .release = e4000_release, - .init = e4000_init, .sleep = e4000_sleep, .set_params = e4000_set_params, @@ -411,9 +399,11 @@ static const struct dvb_tuner_ops e4000_tuner_ops = { .get_if_frequency = e4000_get_if_frequency, }; -struct dvb_frontend *e4000_attach(struct dvb_frontend *fe, - struct i2c_adapter *i2c, const struct e4000_config *cfg) +static int e4000_probe(struct i2c_client *client, + const struct i2c_device_id *id) { + struct e4000_config *cfg = client->dev.platform_data; + struct dvb_frontend *fe = cfg->fe; struct e4000_priv *priv; int ret; u8 chip_id; @@ -424,29 +414,33 @@ struct dvb_frontend *e4000_attach(struct dvb_frontend *fe, priv = kzalloc(sizeof(struct e4000_priv), GFP_KERNEL); if (!priv) { ret = -ENOMEM; - dev_err(&i2c->dev, "%s: kzalloc() failed\n", KBUILD_MODNAME); + dev_err(&client->dev, "%s: kzalloc() failed\n", KBUILD_MODNAME); goto err; } - priv->cfg = cfg; - priv->i2c = i2c; + priv->clock = cfg->clock; + priv->client = client; + priv->fe = cfg->fe; /* check if the tuner is there */ ret = e4000_rd_reg(priv, 0x02, &chip_id); if (ret < 0) goto err; - dev_dbg(&priv->i2c->dev, "%s: chip_id=%02x\n", __func__, chip_id); + dev_dbg(&priv->client->dev, + "%s: chip_id=%02x\n", __func__, chip_id); - if (chip_id != 0x40) + if (chip_id != 0x40) { + ret = -ENODEV; goto err; + } /* put sleep as chip seems to be in normal mode by default */ ret = e4000_wr_reg(priv, 0x00, 0x00); if (ret < 0) goto err; - dev_info(&priv->i2c->dev, + dev_info(&priv->client->dev, "%s: Elonics E4000 successfully identified\n", KBUILD_MODNAME); @@ -457,16 +451,49 @@ struct dvb_frontend *e4000_attach(struct dvb_frontend *fe, if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0); - return fe; + i2c_set_clientdata(client, priv); + + return 0; err: if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0); - dev_dbg(&i2c->dev, "%s: failed=%d\n", __func__, ret); + dev_dbg(&client->dev, "%s: failed=%d\n", __func__, ret); kfree(priv); - return NULL; + return ret; } -EXPORT_SYMBOL(e4000_attach); + +static int e4000_remove(struct i2c_client *client) +{ + struct e4000_priv *priv = i2c_get_clientdata(client); + struct dvb_frontend *fe = priv->fe; + + dev_dbg(&client->dev, "%s:\n", __func__); + + memset(&fe->ops.tuner_ops, 0, sizeof(struct dvb_tuner_ops)); + fe->tuner_priv = NULL; + kfree(priv); + + return 0; +} + +static const struct i2c_device_id e4000_id[] = { + {"e4000", 0}, + {} +}; +MODULE_DEVICE_TABLE(i2c, e4000_id); + +static struct i2c_driver e4000_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "e4000", + }, + .probe = e4000_probe, + .remove = e4000_remove, + .id_table = e4000_id, +}; + +module_i2c_driver(e4000_driver); MODULE_DESCRIPTION("Elonics E4000 silicon tuner driver"); MODULE_AUTHOR("Antti Palosaari "); diff --git a/drivers/media/tuners/e4000.h b/drivers/media/tuners/e4000.h index 25ee7c0..e74b8b2 100644 --- a/drivers/media/tuners/e4000.h +++ b/drivers/media/tuners/e4000.h @@ -24,12 +24,15 @@ #include #include "dvb_frontend.h" +/* + * I2C address + * 0x64, 0x65, 0x66, 0x67 + */ struct e4000_config { /* - * I2C address - * 0x64, 0x65, 0x66, 0x67 + * frontend */ - u8 i2c_addr; + struct dvb_frontend *fe; /* * clock @@ -37,16 +40,4 @@ struct e4000_config { u32 clock; }; -#if IS_ENABLED(CONFIG_MEDIA_TUNER_E4000) -extern struct dvb_frontend *e4000_attach(struct dvb_frontend *fe, - struct i2c_adapter *i2c, const struct e4000_config *cfg); -#else -static inline struct dvb_frontend *e4000_attach(struct dvb_frontend *fe, - struct i2c_adapter *i2c, const struct e4000_config *cfg) -{ - dev_warn(&i2c->dev, "%s: driver disabled by Kconfig\n", __func__); - return NULL; -} -#endif - #endif diff --git a/drivers/media/tuners/e4000_priv.h b/drivers/media/tuners/e4000_priv.h index a385505..8f45a30 100644 --- a/drivers/media/tuners/e4000_priv.h +++ b/drivers/media/tuners/e4000_priv.h @@ -24,8 +24,9 @@ #include "e4000.h" struct e4000_priv { - const struct e4000_config *cfg; - struct i2c_adapter *i2c; + struct i2c_client *client; + u32 clock; + struct dvb_frontend *fe; }; struct e4000_pll { diff --git a/drivers/media/usb/dvb-usb-v2/rtl28xxu.c b/drivers/media/usb/dvb-usb-v2/rtl28xxu.c index e9294dc..ae07740 100644 --- a/drivers/media/usb/dvb-usb-v2/rtl28xxu.c +++ b/drivers/media/usb/dvb-usb-v2/rtl28xxu.c @@ -852,11 +852,6 @@ err: return ret; } -static const struct e4000_config rtl2832u_e4000_config = { - .i2c_addr = 0x64, - .clock = 28800000, -}; - static const struct fc2580_config rtl2832u_fc2580_config = { .i2c_addr = 0x56, .clock = 16384000, @@ -890,10 +885,14 @@ static int rtl2832u_tuner_attach(struct dvb_usb_adapter *adap) int ret; struct dvb_usb_device *d = adap_to_d(adap); struct rtl28xxu_priv *priv = d_to_priv(d); - struct dvb_frontend *fe; + struct dvb_frontend *fe = NULL; + struct i2c_board_info info; + struct i2c_client *client; dev_dbg(&d->udev->dev, "%s:\n", __func__); + memset(&info, 0, sizeof(struct i2c_board_info)); + switch (priv->tuner) { case TUNER_RTL2832_FC0012: fe = dvb_attach(fc0012_attach, adap->fe[0], @@ -913,9 +912,28 @@ static int rtl2832u_tuner_attach(struct dvb_usb_adapter *adap) adap->fe[0]->ops.read_signal_strength = adap->fe[0]->ops.tuner_ops.get_rf_strength; return 0; - case TUNER_RTL2832_E4000: - fe = dvb_attach(e4000_attach, adap->fe[0], &d->i2c_adap, - &rtl2832u_e4000_config); + case TUNER_RTL2832_E4000: { + struct e4000_config e4000_config = { + .fe = adap->fe[0], + .clock = 28800000, + }; + + strlcpy(info.type, "e4000", I2C_NAME_SIZE); + info.addr = 0x64; + info.platform_data = &e4000_config; + + request_module(info.type); + client = i2c_new_device(&d->i2c_adap, &info); + if (client == NULL || client->dev.driver == NULL) + break; + + if (!try_module_get(client->dev.driver->owner)) { + i2c_unregister_device(client); + break; + } + + priv->client = client; + } break; case TUNER_RTL2832_FC2580: fe = dvb_attach(fc2580_attach, adap->fe[0], &d->i2c_adap, @@ -964,12 +982,11 @@ static int rtl2832u_tuner_attach(struct dvb_usb_adapter *adap) adap->fe[0]->ops.tuner_ops.get_rf_strength; break; default: - fe = NULL; dev_err(&d->udev->dev, "%s: unknown tuner=%d\n", KBUILD_MODNAME, priv->tuner); } - if (fe == NULL) { + if (fe == NULL && priv->client == NULL) { ret = -ENODEV; goto err; } @@ -1014,6 +1031,22 @@ err: return ret; } +static void rtl28xxu_exit(struct dvb_usb_device *d) +{ + struct rtl28xxu_priv *priv = d->priv; + struct i2c_client *client = priv->client; + + dev_dbg(&d->udev->dev, "%s:\n", __func__); + + /* remove I2C tuner */ + if (client) { + module_put(client->dev.driver->owner); + i2c_unregister_device(client); + } + + return; +} + static int rtl2831u_power_ctrl(struct dvb_usb_device *d, int onoff) { int ret; @@ -1376,6 +1409,7 @@ static const struct dvb_usb_device_properties rtl2832u_props = { .frontend_attach = rtl2832u_frontend_attach, .tuner_attach = rtl2832u_tuner_attach, .init = rtl28xxu_init, + .exit = rtl28xxu_exit, .get_rc_config = rtl2832u_get_rc_config, .num_adapters = 1, diff --git a/drivers/media/usb/dvb-usb-v2/rtl28xxu.h b/drivers/media/usb/dvb-usb-v2/rtl28xxu.h index 2142bcb..367aca1 100644 --- a/drivers/media/usb/dvb-usb-v2/rtl28xxu.h +++ b/drivers/media/usb/dvb-usb-v2/rtl28xxu.h @@ -56,6 +56,7 @@ struct rtl28xxu_priv { char *tuner_name; u8 page; /* integrated demod active register page */ bool rc_active; + struct i2c_client *client; }; enum rtl28xxu_chip_id { -- cgit v1.1 From adaa616ffb697f00db9b4ccb638c5e9e719dbb7f Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Sun, 26 Jan 2014 21:02:53 -0300 Subject: [media] e4000: implement controls via v4l2 control framework Implement gain and bandwidth controls using v4l2 control framework. Cc: Hans Verkuil Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- drivers/media/tuners/Kconfig | 2 +- drivers/media/tuners/e4000.c | 217 +++++++++++++++++++++++++++++++++++++- drivers/media/tuners/e4000_priv.h | 77 ++++++++++++++ 3 files changed, 291 insertions(+), 5 deletions(-) diff --git a/drivers/media/tuners/Kconfig b/drivers/media/tuners/Kconfig index ba2e365..3b95392 100644 --- a/drivers/media/tuners/Kconfig +++ b/drivers/media/tuners/Kconfig @@ -203,7 +203,7 @@ config MEDIA_TUNER_TDA18212 config MEDIA_TUNER_E4000 tristate "Elonics E4000 silicon tuner" - depends on MEDIA_SUPPORT && I2C + depends on MEDIA_SUPPORT && I2C && VIDEO_V4L2 default m if !MEDIA_SUBDRV_AUTOSELECT help Elonics E4000 silicon tuner driver. diff --git a/drivers/media/tuners/e4000.c b/drivers/media/tuners/e4000.c index 0153169..3a03b02 100644 --- a/drivers/media/tuners/e4000.c +++ b/drivers/media/tuners/e4000.c @@ -385,6 +385,178 @@ static int e4000_get_if_frequency(struct dvb_frontend *fe, u32 *frequency) return 0; } +static int e4000_set_lna_gain(struct dvb_frontend *fe) +{ + struct e4000_priv *priv = fe->tuner_priv; + int ret; + u8 u8tmp; + dev_dbg(&priv->client->dev, "%s: lna auto=%d->%d val=%d->%d\n", + __func__, priv->lna_gain_auto->cur.val, + priv->lna_gain_auto->val, priv->lna_gain->cur.val, + priv->lna_gain->val); + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + + if (priv->lna_gain_auto->val && priv->if_gain_auto->cur.val) + u8tmp = 0x17; + else if (priv->lna_gain_auto->val) + u8tmp = 0x19; + else if (priv->if_gain_auto->cur.val) + u8tmp = 0x16; + else + u8tmp = 0x10; + + ret = e4000_wr_reg(priv, 0x1a, u8tmp); + if (ret) + goto err; + + if (priv->lna_gain_auto->val == false) { + ret = e4000_wr_reg(priv, 0x14, priv->lna_gain->val); + if (ret) + goto err; + } + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 0); + + return 0; +err: + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 0); + + dev_dbg(&priv->client->dev, "%s: failed=%d\n", __func__, ret); + return ret; +} + +static int e4000_set_mixer_gain(struct dvb_frontend *fe) +{ + struct e4000_priv *priv = fe->tuner_priv; + int ret; + u8 u8tmp; + dev_dbg(&priv->client->dev, "%s: mixer auto=%d->%d val=%d->%d\n", + __func__, priv->mixer_gain_auto->cur.val, + priv->mixer_gain_auto->val, priv->mixer_gain->cur.val, + priv->mixer_gain->val); + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + + if (priv->mixer_gain_auto->val) + u8tmp = 0x15; + else + u8tmp = 0x14; + + ret = e4000_wr_reg(priv, 0x20, u8tmp); + if (ret) + goto err; + + if (priv->mixer_gain_auto->val == false) { + ret = e4000_wr_reg(priv, 0x15, priv->mixer_gain->val); + if (ret) + goto err; + } + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 0); + + return 0; +err: + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 0); + + dev_dbg(&priv->client->dev, "%s: failed=%d\n", __func__, ret); + return ret; +} + +static int e4000_set_if_gain(struct dvb_frontend *fe) +{ + struct e4000_priv *priv = fe->tuner_priv; + int ret; + u8 buf[2]; + u8 u8tmp; + dev_dbg(&priv->client->dev, "%s: if auto=%d->%d val=%d->%d\n", + __func__, priv->if_gain_auto->cur.val, + priv->if_gain_auto->val, priv->if_gain->cur.val, + priv->if_gain->val); + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + + if (priv->if_gain_auto->val && priv->lna_gain_auto->cur.val) + u8tmp = 0x17; + else if (priv->lna_gain_auto->cur.val) + u8tmp = 0x19; + else if (priv->if_gain_auto->val) + u8tmp = 0x16; + else + u8tmp = 0x10; + + ret = e4000_wr_reg(priv, 0x1a, u8tmp); + if (ret) + goto err; + + if (priv->if_gain_auto->val == false) { + buf[0] = e4000_if_gain_lut[priv->if_gain->val].reg16_val; + buf[1] = e4000_if_gain_lut[priv->if_gain->val].reg17_val; + ret = e4000_wr_regs(priv, 0x16, buf, 2); + if (ret) + goto err; + } + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 0); + + return 0; +err: + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 0); + + dev_dbg(&priv->client->dev, "%s: failed=%d\n", __func__, ret); + return ret; +} + +static int e4000_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct e4000_priv *priv = + container_of(ctrl->handler, struct e4000_priv, hdl); + struct dvb_frontend *fe = priv->fe; + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + int ret; + dev_dbg(&priv->client->dev, + "%s: id=%d name=%s val=%d min=%d max=%d step=%d\n", + __func__, ctrl->id, ctrl->name, ctrl->val, + ctrl->minimum, ctrl->maximum, ctrl->step); + + switch (ctrl->id) { + case V4L2_CID_RF_TUNER_BANDWIDTH_AUTO: + case V4L2_CID_RF_TUNER_BANDWIDTH: + c->bandwidth_hz = priv->bandwidth->val; + ret = e4000_set_params(priv->fe); + break; + case V4L2_CID_RF_TUNER_LNA_GAIN_AUTO: + case V4L2_CID_RF_TUNER_LNA_GAIN: + ret = e4000_set_lna_gain(priv->fe); + break; + case V4L2_CID_RF_TUNER_MIXER_GAIN_AUTO: + case V4L2_CID_RF_TUNER_MIXER_GAIN: + ret = e4000_set_mixer_gain(priv->fe); + break; + case V4L2_CID_RF_TUNER_IF_GAIN_AUTO: + case V4L2_CID_RF_TUNER_IF_GAIN: + ret = e4000_set_if_gain(priv->fe); + break; + default: + ret = -EINVAL; + } + + return ret; +} + +static const struct v4l2_ctrl_ops e4000_ctrl_ops = { + .s_ctrl = e4000_s_ctrl, +}; + static const struct dvb_tuner_ops e4000_tuner_ops = { .info = { .name = "Elonics E4000", @@ -399,6 +571,10 @@ static const struct dvb_tuner_ops e4000_tuner_ops = { .get_if_frequency = e4000_get_if_frequency, }; +/* + * Use V4L2 subdev to carry V4L2 control handler, even we don't implement + * subdev itself, just to avoid reinventing the wheel. + */ static int e4000_probe(struct i2c_client *client, const struct i2c_device_id *id) { @@ -440,6 +616,37 @@ static int e4000_probe(struct i2c_client *client, if (ret < 0) goto err; + /* Register controls */ + v4l2_ctrl_handler_init(&priv->hdl, 8); + priv->bandwidth_auto = v4l2_ctrl_new_std(&priv->hdl, &e4000_ctrl_ops, + V4L2_CID_RF_TUNER_BANDWIDTH_AUTO, 0, 1, 1, 1); + priv->bandwidth = v4l2_ctrl_new_std(&priv->hdl, &e4000_ctrl_ops, + V4L2_CID_RF_TUNER_BANDWIDTH, 4300000, 11000000, 100000, 4300000); + v4l2_ctrl_auto_cluster(2, &priv->bandwidth_auto, 0, false); + priv->lna_gain_auto = v4l2_ctrl_new_std(&priv->hdl, &e4000_ctrl_ops, + V4L2_CID_RF_TUNER_LNA_GAIN_AUTO, 0, 1, 1, 1); + priv->lna_gain = v4l2_ctrl_new_std(&priv->hdl, &e4000_ctrl_ops, + V4L2_CID_RF_TUNER_LNA_GAIN, 0, 15, 1, 10); + v4l2_ctrl_auto_cluster(2, &priv->lna_gain_auto, 0, false); + priv->mixer_gain_auto = v4l2_ctrl_new_std(&priv->hdl, &e4000_ctrl_ops, + V4L2_CID_RF_TUNER_MIXER_GAIN_AUTO, 0, 1, 1, 1); + priv->mixer_gain = v4l2_ctrl_new_std(&priv->hdl, &e4000_ctrl_ops, + V4L2_CID_RF_TUNER_MIXER_GAIN, 0, 1, 1, 1); + v4l2_ctrl_auto_cluster(2, &priv->mixer_gain_auto, 0, false); + priv->if_gain_auto = v4l2_ctrl_new_std(&priv->hdl, &e4000_ctrl_ops, + V4L2_CID_RF_TUNER_IF_GAIN_AUTO, 0, 1, 1, 1); + priv->if_gain = v4l2_ctrl_new_std(&priv->hdl, &e4000_ctrl_ops, + V4L2_CID_RF_TUNER_IF_GAIN, 0, 54, 1, 0); + v4l2_ctrl_auto_cluster(2, &priv->if_gain_auto, 0, false); + if (priv->hdl.error) { + ret = priv->hdl.error; + dev_err(&priv->client->dev, "Could not initialize controls\n"); + v4l2_ctrl_handler_free(&priv->hdl); + goto err; + } + + priv->sd.ctrl_handler = &priv->hdl; + dev_info(&priv->client->dev, "%s: Elonics E4000 successfully identified\n", KBUILD_MODNAME); @@ -448,11 +655,12 @@ static int e4000_probe(struct i2c_client *client, memcpy(&fe->ops.tuner_ops, &e4000_tuner_ops, sizeof(struct dvb_tuner_ops)); + v4l2_set_subdevdata(&priv->sd, client); + i2c_set_clientdata(client, &priv->sd); + if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0); - i2c_set_clientdata(client, priv); - return 0; err: if (fe->ops.i2c_gate_ctrl) @@ -465,11 +673,12 @@ err: static int e4000_remove(struct i2c_client *client) { - struct e4000_priv *priv = i2c_get_clientdata(client); + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct e4000_priv *priv = container_of(sd, struct e4000_priv, sd); struct dvb_frontend *fe = priv->fe; dev_dbg(&client->dev, "%s:\n", __func__); - + v4l2_ctrl_handler_free(&priv->hdl); memset(&fe->ops.tuner_ops, 0, sizeof(struct dvb_tuner_ops)); fe->tuner_priv = NULL; kfree(priv); diff --git a/drivers/media/tuners/e4000_priv.h b/drivers/media/tuners/e4000_priv.h index 8f45a30..e2ad54f 100644 --- a/drivers/media/tuners/e4000_priv.h +++ b/drivers/media/tuners/e4000_priv.h @@ -22,11 +22,25 @@ #define E4000_PRIV_H #include "e4000.h" +#include +#include struct e4000_priv { struct i2c_client *client; u32 clock; struct dvb_frontend *fe; + struct v4l2_subdev sd; + + /* Controls */ + struct v4l2_ctrl_handler hdl; + struct v4l2_ctrl *bandwidth_auto; + struct v4l2_ctrl *bandwidth; + struct v4l2_ctrl *lna_gain_auto; + struct v4l2_ctrl *lna_gain; + struct v4l2_ctrl *mixer_gain_auto; + struct v4l2_ctrl *mixer_gain; + struct v4l2_ctrl *if_gain_auto; + struct v4l2_ctrl *if_gain; }; struct e4000_pll { @@ -145,4 +159,67 @@ static const struct e4000_if_filter e4000_if_filter_lut[] = { { 0xffffffff, 0x00, 0x20 }, }; +struct e4000_if_gain { + u8 reg16_val; + u8 reg17_val; +}; + +static const struct e4000_if_gain e4000_if_gain_lut[] = { + {0x00, 0x00}, + {0x20, 0x00}, + {0x40, 0x00}, + {0x02, 0x00}, + {0x22, 0x00}, + {0x42, 0x00}, + {0x04, 0x00}, + {0x24, 0x00}, + {0x44, 0x00}, + {0x01, 0x00}, + {0x21, 0x00}, + {0x41, 0x00}, + {0x03, 0x00}, + {0x23, 0x00}, + {0x43, 0x00}, + {0x05, 0x00}, + {0x25, 0x00}, + {0x45, 0x00}, + {0x07, 0x00}, + {0x27, 0x00}, + {0x47, 0x00}, + {0x0f, 0x00}, + {0x2f, 0x00}, + {0x4f, 0x00}, + {0x17, 0x00}, + {0x37, 0x00}, + {0x57, 0x00}, + {0x1f, 0x00}, + {0x3f, 0x00}, + {0x5f, 0x00}, + {0x1f, 0x01}, + {0x3f, 0x01}, + {0x5f, 0x01}, + {0x1f, 0x02}, + {0x3f, 0x02}, + {0x5f, 0x02}, + {0x1f, 0x03}, + {0x3f, 0x03}, + {0x5f, 0x03}, + {0x1f, 0x04}, + {0x3f, 0x04}, + {0x5f, 0x04}, + {0x1f, 0x0c}, + {0x3f, 0x0c}, + {0x5f, 0x0c}, + {0x1f, 0x14}, + {0x3f, 0x14}, + {0x5f, 0x14}, + {0x1f, 0x1c}, + {0x3f, 0x1c}, + {0x5f, 0x1c}, + {0x1f, 0x24}, + {0x3f, 0x24}, + {0x5f, 0x24}, + {0x7f, 0x24}, +}; + #endif -- cgit v1.1 From 0ed0b22dc594a533a959ed8995e69e2275af40d9 Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Mon, 27 Jan 2014 03:13:19 -0300 Subject: [media] e4000: fix PLL calc to allow higher frequencies There was 32-bit overflow on VCO frequency calculation which blocks tuning to 1073 - 1104 MHz. Use 64 bit number in order to avoid VCO frequency overflow. After that fix device in question tunes to following range: 60 - 1104 MHz 1250 - 2207 MHz Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- drivers/media/tuners/e4000.c | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/drivers/media/tuners/e4000.c b/drivers/media/tuners/e4000.c index 3a03b02..ae52a1f 100644 --- a/drivers/media/tuners/e4000.c +++ b/drivers/media/tuners/e4000.c @@ -221,11 +221,11 @@ static int e4000_set_params(struct dvb_frontend *fe) struct e4000_priv *priv = fe->tuner_priv; struct dtv_frontend_properties *c = &fe->dtv_property_cache; int ret, i, sigma_delta; - unsigned int f_vco; + u64 f_vco; u8 buf[5], i_data[4], q_data[4]; dev_dbg(&priv->client->dev, - "%s: delivery_system=%d frequency=%d bandwidth_hz=%d\n", + "%s: delivery_system=%d frequency=%u bandwidth_hz=%u\n", __func__, c->delivery_system, c->frequency, c->bandwidth_hz); @@ -248,20 +248,16 @@ static int e4000_set_params(struct dvb_frontend *fe) goto err; } - /* - * Note: Currently f_vco overflows when c->frequency is 1 073 741 824 Hz - * or more. - */ - f_vco = c->frequency * e4000_pll_lut[i].mul; + f_vco = 1ull * c->frequency * e4000_pll_lut[i].mul; sigma_delta = div_u64(0x10000ULL * (f_vco % priv->clock), priv->clock); - buf[0] = f_vco / priv->clock; + buf[0] = div_u64(f_vco, priv->clock); buf[1] = (sigma_delta >> 0) & 0xff; buf[2] = (sigma_delta >> 8) & 0xff; buf[3] = 0x00; buf[4] = e4000_pll_lut[i].div; dev_dbg(&priv->client->dev, - "%s: f_vco=%u pll div=%d sigma_delta=%04x\n", + "%s: f_vco=%llu pll div=%d sigma_delta=%04x\n", __func__, f_vco, buf[0], sigma_delta); ret = e4000_wr_regs(priv, 0x09, buf, 5); -- cgit v1.1 From ecfb7ca3c8c48e90f2918a72e8ed7a2f989f2635 Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Fri, 7 Feb 2014 02:55:57 -0300 Subject: [media] e4000: implement PLL lock v4l control Implement PLL lock control to get PLL lock flag status from tuner synthesizer. Cc: Hans Verkuil Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- drivers/media/tuners/e4000.c | 53 ++++++++++++++++++++++++++++++++++++++- drivers/media/tuners/e4000_priv.h | 2 ++ 2 files changed, 54 insertions(+), 1 deletion(-) diff --git a/drivers/media/tuners/e4000.c b/drivers/media/tuners/e4000.c index ae52a1f..ed2f635 100644 --- a/drivers/media/tuners/e4000.c +++ b/drivers/media/tuners/e4000.c @@ -181,6 +181,8 @@ static int e4000_init(struct dvb_frontend *fe) if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0); + priv->active = true; + return 0; err: if (fe->ops.i2c_gate_ctrl) @@ -197,6 +199,8 @@ static int e4000_sleep(struct dvb_frontend *fe) dev_dbg(&priv->client->dev, "%s:\n", __func__); + priv->active = false; + if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 1); @@ -512,6 +516,50 @@ err: return ret; } +static int e4000_pll_lock(struct dvb_frontend *fe) +{ + struct e4000_priv *priv = fe->tuner_priv; + int ret; + u8 u8tmp; + + if (priv->active == false) + return 0; + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + + ret = e4000_rd_reg(priv, 0x07, &u8tmp); + if (ret) + goto err; + + priv->pll_lock->val = (u8tmp & 0x01); +err: + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 0); + + if (ret) + dev_dbg(&priv->client->dev, "%s: failed=%d\n", __func__, ret); + + return ret; +} + +static int e4000_g_volatile_ctrl(struct v4l2_ctrl *ctrl) +{ + struct e4000_priv *priv = + container_of(ctrl->handler, struct e4000_priv, hdl); + int ret; + + switch (ctrl->id) { + case V4L2_CID_RF_TUNER_PLL_LOCK: + ret = e4000_pll_lock(priv->fe); + break; + default: + ret = -EINVAL; + } + + return ret; +} + static int e4000_s_ctrl(struct v4l2_ctrl *ctrl) { struct e4000_priv *priv = @@ -550,6 +598,7 @@ static int e4000_s_ctrl(struct v4l2_ctrl *ctrl) } static const struct v4l2_ctrl_ops e4000_ctrl_ops = { + .g_volatile_ctrl = e4000_g_volatile_ctrl, .s_ctrl = e4000_s_ctrl, }; @@ -613,7 +662,7 @@ static int e4000_probe(struct i2c_client *client, goto err; /* Register controls */ - v4l2_ctrl_handler_init(&priv->hdl, 8); + v4l2_ctrl_handler_init(&priv->hdl, 9); priv->bandwidth_auto = v4l2_ctrl_new_std(&priv->hdl, &e4000_ctrl_ops, V4L2_CID_RF_TUNER_BANDWIDTH_AUTO, 0, 1, 1, 1); priv->bandwidth = v4l2_ctrl_new_std(&priv->hdl, &e4000_ctrl_ops, @@ -634,6 +683,8 @@ static int e4000_probe(struct i2c_client *client, priv->if_gain = v4l2_ctrl_new_std(&priv->hdl, &e4000_ctrl_ops, V4L2_CID_RF_TUNER_IF_GAIN, 0, 54, 1, 0); v4l2_ctrl_auto_cluster(2, &priv->if_gain_auto, 0, false); + priv->pll_lock = v4l2_ctrl_new_std(&priv->hdl, &e4000_ctrl_ops, + V4L2_CID_RF_TUNER_PLL_LOCK, 0, 1, 1, 0); if (priv->hdl.error) { ret = priv->hdl.error; dev_err(&priv->client->dev, "Could not initialize controls\n"); diff --git a/drivers/media/tuners/e4000_priv.h b/drivers/media/tuners/e4000_priv.h index e2ad54f..3ddd980 100644 --- a/drivers/media/tuners/e4000_priv.h +++ b/drivers/media/tuners/e4000_priv.h @@ -30,6 +30,7 @@ struct e4000_priv { u32 clock; struct dvb_frontend *fe; struct v4l2_subdev sd; + bool active; /* Controls */ struct v4l2_ctrl_handler hdl; @@ -41,6 +42,7 @@ struct e4000_priv { struct v4l2_ctrl *mixer_gain; struct v4l2_ctrl *if_gain_auto; struct v4l2_ctrl *if_gain; + struct v4l2_ctrl *pll_lock; }; struct e4000_pll { -- cgit v1.1 From 771138920eafa399f68d3492c8a75dfeea23474b Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Tue, 10 Sep 2013 00:07:56 -0300 Subject: [media] rtl2832_sdr: Realtek RTL2832 SDR driver module Implement SDR driver for Realtek RTL2832U chip as a DVB extension module. SDR module is attached by DVB USB RTL28XXU driver as a DVB SEC (satellite equipment controller) module. Abusing unused SEC here has no harm as that is DVB-T only frontend. SDR functionality is provided by RTL2832 DVB-T demodulator. I suspect it is originally planned for DAB and FM, but it could be abused general SDR, due to modern silicon tuners that has wide frequency range and a lot of configurable parameters (filters, gains, ...). http://thread.gmane.org/gmane.linux.drivers.video-input-infrastructure/44461 Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- drivers/staging/media/Kconfig | 2 + drivers/staging/media/Makefile | 2 + drivers/staging/media/rtl2832u_sdr/Kconfig | 7 + drivers/staging/media/rtl2832u_sdr/Makefile | 6 + drivers/staging/media/rtl2832u_sdr/rtl2832_sdr.c | 1471 ++++++++++++++++++++++ drivers/staging/media/rtl2832u_sdr/rtl2832_sdr.h | 54 + 6 files changed, 1542 insertions(+) create mode 100644 drivers/staging/media/rtl2832u_sdr/Kconfig create mode 100644 drivers/staging/media/rtl2832u_sdr/Makefile create mode 100644 drivers/staging/media/rtl2832u_sdr/rtl2832_sdr.c create mode 100644 drivers/staging/media/rtl2832u_sdr/rtl2832_sdr.h diff --git a/drivers/staging/media/Kconfig b/drivers/staging/media/Kconfig index 22b0c9d..a9f2e63 100644 --- a/drivers/staging/media/Kconfig +++ b/drivers/staging/media/Kconfig @@ -41,6 +41,8 @@ source "drivers/staging/media/solo6x10/Kconfig" source "drivers/staging/media/omap4iss/Kconfig" +source "drivers/staging/media/rtl2832u_sdr/Kconfig" + # Keep LIRC at the end, as it has sub-menus source "drivers/staging/media/lirc/Kconfig" diff --git a/drivers/staging/media/Makefile b/drivers/staging/media/Makefile index bedc62a..8e2c5d2 100644 --- a/drivers/staging/media/Makefile +++ b/drivers/staging/media/Makefile @@ -11,3 +11,5 @@ obj-$(CONFIG_VIDEO_OMAP4) += omap4iss/ obj-$(CONFIG_USB_SN9C102) += sn9c102/ obj-$(CONFIG_VIDEO_OMAP2) += omap24xx/ obj-$(CONFIG_VIDEO_TCM825X) += omap24xx/ +obj-$(CONFIG_DVB_RTL2832_SDR) += rtl2832u_sdr/ + diff --git a/drivers/staging/media/rtl2832u_sdr/Kconfig b/drivers/staging/media/rtl2832u_sdr/Kconfig new file mode 100644 index 0000000..3ede5fe --- /dev/null +++ b/drivers/staging/media/rtl2832u_sdr/Kconfig @@ -0,0 +1,7 @@ +config DVB_RTL2832_SDR + tristate "Realtek RTL2832 SDR" + depends on USB && DVB_CORE && I2C && VIDEO_V4L2 && DVB_USB_RTL28XXU + select DVB_RTL2832 + select VIDEOBUF2_VMALLOC + default m if !MEDIA_SUBDRV_AUTOSELECT + diff --git a/drivers/staging/media/rtl2832u_sdr/Makefile b/drivers/staging/media/rtl2832u_sdr/Makefile new file mode 100644 index 0000000..7e00a0d --- /dev/null +++ b/drivers/staging/media/rtl2832u_sdr/Makefile @@ -0,0 +1,6 @@ +obj-$(CONFIG_DVB_RTL2832_SDR) += rtl2832_sdr.o + +ccflags-y += -Idrivers/media/dvb-core +ccflags-y += -Idrivers/media/dvb-frontends +ccflags-y += -Idrivers/media/tuners +ccflags-y += -Idrivers/media/usb/dvb-usb-v2 diff --git a/drivers/staging/media/rtl2832u_sdr/rtl2832_sdr.c b/drivers/staging/media/rtl2832u_sdr/rtl2832_sdr.c new file mode 100644 index 0000000..86fffcf --- /dev/null +++ b/drivers/staging/media/rtl2832u_sdr/rtl2832_sdr.c @@ -0,0 +1,1471 @@ +/* + * Realtek RTL2832U SDR driver + * + * Copyright (C) 2013 Antti Palosaari + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * GNU Radio plugin "gr-kernel" for device usage will be on: + * http://git.linuxtv.org/anttip/gr-kernel.git + * + */ + +#include "dvb_frontend.h" +#include "rtl2832_sdr.h" +#include "dvb_usb.h" + +#include +#include +#include +#include +#include + +#include +#include + +#define MAX_BULK_BUFS (10) +#define BULK_BUFFER_SIZE (128 * 512) + +static const struct v4l2_frequency_band bands_adc[] = { + { + .tuner = 0, + .type = V4L2_TUNER_ADC, + .index = 0, + .capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS, + .rangelow = 300000, + .rangehigh = 300000, + }, + { + .tuner = 0, + .type = V4L2_TUNER_ADC, + .index = 1, + .capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS, + .rangelow = 900001, + .rangehigh = 2800000, + }, + { + .tuner = 0, + .type = V4L2_TUNER_ADC, + .index = 2, + .capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS, + .rangelow = 3200000, + .rangehigh = 3200000, + }, +}; + +static const struct v4l2_frequency_band bands_fm[] = { + { + .tuner = 1, + .type = V4L2_TUNER_RF, + .index = 0, + .capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS, + .rangelow = 50000000, + .rangehigh = 2000000000, + }, +}; + +/* stream formats */ +struct rtl2832_sdr_format { + char *name; + u32 pixelformat; +}; + +static struct rtl2832_sdr_format formats[] = { + { + .name = "IQ U8", + .pixelformat = V4L2_SDR_FMT_CU8, + }, { + .name = "IQ U16LE (emulated)", + .pixelformat = V4L2_SDR_FMT_CU16LE, + }, +}; + +static const unsigned int NUM_FORMATS = ARRAY_SIZE(formats); + +/* intermediate buffers with raw data from the USB device */ +struct rtl2832_sdr_frame_buf { + struct vb2_buffer vb; /* common v4l buffer stuff -- must be first */ + struct list_head list; +}; + +struct rtl2832_sdr_state { +#define POWER_ON (1 << 1) +#define URB_BUF (1 << 2) + unsigned long flags; + + const struct rtl2832_config *cfg; + struct dvb_frontend *fe; + struct dvb_usb_device *d; + struct i2c_adapter *i2c; + u8 bank; + + struct video_device vdev; + struct v4l2_device v4l2_dev; + + /* videobuf2 queue and queued buffers list */ + struct vb2_queue vb_queue; + struct list_head queued_bufs; + spinlock_t queued_bufs_lock; /* Protects queued_bufs */ + + /* Note if taking both locks v4l2_lock must always be locked first! */ + struct mutex v4l2_lock; /* Protects everything else */ + struct mutex vb_queue_lock; /* Protects vb_queue and capt_file */ + + /* Pointer to our usb_device, will be NULL after unplug */ + struct usb_device *udev; /* Both mutexes most be hold when setting! */ + + unsigned int vb_full; /* vb is full and packets dropped */ + + struct urb *urb_list[MAX_BULK_BUFS]; + int buf_num; + unsigned long buf_size; + u8 *buf_list[MAX_BULK_BUFS]; + dma_addr_t dma_addr[MAX_BULK_BUFS]; + int urbs_initialized; + int urbs_submitted; + + unsigned int f_adc, f_tuner; + u32 pixelformat; + + /* Controls */ + struct v4l2_ctrl_handler hdl; + struct v4l2_ctrl *bandwidth_auto; + struct v4l2_ctrl *bandwidth; + + /* for sample rate calc */ + unsigned int sample; + unsigned int sample_measured; + unsigned long jiffies_next; +}; + +/* write multiple hardware registers */ +static int rtl2832_sdr_wr(struct rtl2832_sdr_state *s, u8 reg, const u8 *val, + int len) +{ + int ret; + u8 buf[1 + len]; + struct i2c_msg msg[1] = { + { + .addr = s->cfg->i2c_addr, + .flags = 0, + .len = 1 + len, + .buf = buf, + } + }; + + buf[0] = reg; + memcpy(&buf[1], val, len); + + ret = i2c_transfer(s->i2c, msg, 1); + if (ret == 1) { + ret = 0; + } else { + dev_err(&s->i2c->dev, + "%s: I2C wr failed=%d reg=%02x len=%d\n", + KBUILD_MODNAME, ret, reg, len); + ret = -EREMOTEIO; + } + return ret; +} + +/* read multiple hardware registers */ +static int rtl2832_sdr_rd(struct rtl2832_sdr_state *s, u8 reg, u8 *val, int len) +{ + int ret; + struct i2c_msg msg[2] = { + { + .addr = s->cfg->i2c_addr, + .flags = 0, + .len = 1, + .buf = ®, + }, { + .addr = s->cfg->i2c_addr, + .flags = I2C_M_RD, + .len = len, + .buf = val, + } + }; + + ret = i2c_transfer(s->i2c, msg, 2); + if (ret == 2) { + ret = 0; + } else { + dev_err(&s->i2c->dev, + "%s: I2C rd failed=%d reg=%02x len=%d\n", + KBUILD_MODNAME, ret, reg, len); + ret = -EREMOTEIO; + } + return ret; +} + +/* write multiple registers */ +static int rtl2832_sdr_wr_regs(struct rtl2832_sdr_state *s, u16 reg, + const u8 *val, int len) +{ + int ret; + u8 reg2 = (reg >> 0) & 0xff; + u8 bank = (reg >> 8) & 0xff; + + /* switch bank if needed */ + if (bank != s->bank) { + ret = rtl2832_sdr_wr(s, 0x00, &bank, 1); + if (ret) + return ret; + + s->bank = bank; + } + + return rtl2832_sdr_wr(s, reg2, val, len); +} + +/* read multiple registers */ +static int rtl2832_sdr_rd_regs(struct rtl2832_sdr_state *s, u16 reg, u8 *val, + int len) +{ + int ret; + u8 reg2 = (reg >> 0) & 0xff; + u8 bank = (reg >> 8) & 0xff; + + /* switch bank if needed */ + if (bank != s->bank) { + ret = rtl2832_sdr_wr(s, 0x00, &bank, 1); + if (ret) + return ret; + + s->bank = bank; + } + + return rtl2832_sdr_rd(s, reg2, val, len); +} + +/* write single register */ +static int rtl2832_sdr_wr_reg(struct rtl2832_sdr_state *s, u16 reg, u8 val) +{ + return rtl2832_sdr_wr_regs(s, reg, &val, 1); +} + +#if 0 +/* read single register */ +static int rtl2832_sdr_rd_reg(struct rtl2832_sdr_state *s, u16 reg, u8 *val) +{ + return rtl2832_sdr_rd_regs(s, reg, val, 1); +} +#endif + +/* write single register with mask */ +static int rtl2832_sdr_wr_reg_mask(struct rtl2832_sdr_state *s, u16 reg, + u8 val, u8 mask) +{ + int ret; + u8 tmp; + + /* no need for read if whole reg is written */ + if (mask != 0xff) { + ret = rtl2832_sdr_rd_regs(s, reg, &tmp, 1); + if (ret) + return ret; + + val &= mask; + tmp &= ~mask; + val |= tmp; + } + + return rtl2832_sdr_wr_regs(s, reg, &val, 1); +} + +#if 0 +/* read single register with mask */ +static int rtl2832_sdr_rd_reg_mask(struct rtl2832_sdr_state *s, u16 reg, + u8 *val, u8 mask) +{ + int ret, i; + u8 tmp; + + ret = rtl2832_sdr_rd_regs(s, reg, &tmp, 1); + if (ret) + return ret; + + tmp &= mask; + + /* find position of the first bit */ + for (i = 0; i < 8; i++) { + if ((mask >> i) & 0x01) + break; + } + *val = tmp >> i; + + return 0; +} +#endif + +/* Private functions */ +static struct rtl2832_sdr_frame_buf *rtl2832_sdr_get_next_fill_buf( + struct rtl2832_sdr_state *s) +{ + unsigned long flags = 0; + struct rtl2832_sdr_frame_buf *buf = NULL; + + spin_lock_irqsave(&s->queued_bufs_lock, flags); + if (list_empty(&s->queued_bufs)) + goto leave; + + buf = list_entry(s->queued_bufs.next, + struct rtl2832_sdr_frame_buf, list); + list_del(&buf->list); +leave: + spin_unlock_irqrestore(&s->queued_bufs_lock, flags); + return buf; +} + +static unsigned int rtl2832_sdr_convert_stream(struct rtl2832_sdr_state *s, + void *dst, const u8 *src, unsigned int src_len) +{ + unsigned int dst_len; + + if (s->pixelformat == V4L2_SDR_FMT_CU8) { + /* native stream, no need to convert */ + memcpy(dst, src, src_len); + dst_len = src_len; + } else if (s->pixelformat == V4L2_SDR_FMT_CU16LE) { + /* convert u8 to u16 */ + unsigned int i; + u16 *u16dst = dst; + for (i = 0; i < src_len; i++) + *u16dst++ = (src[i] << 8) | (src[i] >> 0); + dst_len = 2 * src_len; + } else { + dst_len = 0; + } + + /* calculate samping rate and output it in 10 seconds intervals */ + if (unlikely(time_is_before_jiffies(s->jiffies_next))) { +#define MSECS 10000UL + unsigned int samples = s->sample - s->sample_measured; + s->jiffies_next = jiffies + msecs_to_jiffies(MSECS); + s->sample_measured = s->sample; + dev_dbg(&s->udev->dev, + "slen=%d samples=%u msecs=%lu sampling rate=%lu\n", + src_len, samples, MSECS, + samples * 1000UL / MSECS); + } + + /* total number of I+Q pairs */ + s->sample += src_len / 2; + + return dst_len; +} + +/* + * This gets called for the bulk stream pipe. This is done in interrupt + * time, so it has to be fast, not crash, and not stall. Neat. + */ +static void rtl2832_sdr_urb_complete(struct urb *urb) +{ + struct rtl2832_sdr_state *s = urb->context; + struct rtl2832_sdr_frame_buf *fbuf; + + dev_dbg_ratelimited(&s->udev->dev, + "%s: status=%d length=%d/%d errors=%d\n", + __func__, urb->status, urb->actual_length, + urb->transfer_buffer_length, urb->error_count); + + switch (urb->status) { + case 0: /* success */ + case -ETIMEDOUT: /* NAK */ + break; + case -ECONNRESET: /* kill */ + case -ENOENT: + case -ESHUTDOWN: + return; + default: /* error */ + dev_err_ratelimited(&s->udev->dev, "urb failed=%d\n", + urb->status); + break; + } + + if (likely(urb->actual_length > 0)) { + void *ptr; + unsigned int len; + /* get free framebuffer */ + fbuf = rtl2832_sdr_get_next_fill_buf(s); + if (unlikely(fbuf == NULL)) { + s->vb_full++; + dev_notice_ratelimited(&s->udev->dev, + "videobuf is full, %d packets dropped\n", + s->vb_full); + goto skip; + } + + /* fill framebuffer */ + ptr = vb2_plane_vaddr(&fbuf->vb, 0); + len = rtl2832_sdr_convert_stream(s, ptr, urb->transfer_buffer, + urb->actual_length); + vb2_set_plane_payload(&fbuf->vb, 0, len); + vb2_buffer_done(&fbuf->vb, VB2_BUF_STATE_DONE); + } +skip: + usb_submit_urb(urb, GFP_ATOMIC); +} + +static int rtl2832_sdr_kill_urbs(struct rtl2832_sdr_state *s) +{ + int i; + + for (i = s->urbs_submitted - 1; i >= 0; i--) { + dev_dbg(&s->udev->dev, "%s: kill urb=%d\n", __func__, i); + /* stop the URB */ + usb_kill_urb(s->urb_list[i]); + } + s->urbs_submitted = 0; + + return 0; +} + +static int rtl2832_sdr_submit_urbs(struct rtl2832_sdr_state *s) +{ + int i, ret; + + for (i = 0; i < s->urbs_initialized; i++) { + dev_dbg(&s->udev->dev, "%s: submit urb=%d\n", __func__, i); + ret = usb_submit_urb(s->urb_list[i], GFP_ATOMIC); + if (ret) { + dev_err(&s->udev->dev, + "Could not submit urb no. %d - get them all back\n", + i); + rtl2832_sdr_kill_urbs(s); + return ret; + } + s->urbs_submitted++; + } + + return 0; +} + +static int rtl2832_sdr_free_stream_bufs(struct rtl2832_sdr_state *s) +{ + if (s->flags & USB_STATE_URB_BUF) { + while (s->buf_num) { + s->buf_num--; + dev_dbg(&s->udev->dev, "%s: free buf=%d\n", + __func__, s->buf_num); + usb_free_coherent(s->udev, s->buf_size, + s->buf_list[s->buf_num], + s->dma_addr[s->buf_num]); + } + } + s->flags &= ~USB_STATE_URB_BUF; + + return 0; +} + +static int rtl2832_sdr_alloc_stream_bufs(struct rtl2832_sdr_state *s) +{ + s->buf_num = 0; + s->buf_size = BULK_BUFFER_SIZE; + + dev_dbg(&s->udev->dev, + "%s: all in all I will use %u bytes for streaming\n", + __func__, MAX_BULK_BUFS * BULK_BUFFER_SIZE); + + for (s->buf_num = 0; s->buf_num < MAX_BULK_BUFS; s->buf_num++) { + s->buf_list[s->buf_num] = usb_alloc_coherent(s->udev, + BULK_BUFFER_SIZE, GFP_ATOMIC, + &s->dma_addr[s->buf_num]); + if (!s->buf_list[s->buf_num]) { + dev_dbg(&s->udev->dev, "%s: alloc buf=%d failed\n", + __func__, s->buf_num); + rtl2832_sdr_free_stream_bufs(s); + return -ENOMEM; + } + + dev_dbg(&s->udev->dev, "%s: alloc buf=%d %p (dma %llu)\n", + __func__, s->buf_num, + s->buf_list[s->buf_num], + (long long)s->dma_addr[s->buf_num]); + s->flags |= USB_STATE_URB_BUF; + } + + return 0; +} + +static int rtl2832_sdr_free_urbs(struct rtl2832_sdr_state *s) +{ + int i; + + rtl2832_sdr_kill_urbs(s); + + for (i = s->urbs_initialized - 1; i >= 0; i--) { + if (s->urb_list[i]) { + dev_dbg(&s->udev->dev, "%s: free urb=%d\n", + __func__, i); + /* free the URBs */ + usb_free_urb(s->urb_list[i]); + } + } + s->urbs_initialized = 0; + + return 0; +} + +static int rtl2832_sdr_alloc_urbs(struct rtl2832_sdr_state *s) +{ + int i, j; + + /* allocate the URBs */ + for (i = 0; i < MAX_BULK_BUFS; i++) { + dev_dbg(&s->udev->dev, "%s: alloc urb=%d\n", __func__, i); + s->urb_list[i] = usb_alloc_urb(0, GFP_ATOMIC); + if (!s->urb_list[i]) { + dev_dbg(&s->udev->dev, "%s: failed\n", __func__); + for (j = 0; j < i; j++) + usb_free_urb(s->urb_list[j]); + return -ENOMEM; + } + usb_fill_bulk_urb(s->urb_list[i], + s->udev, + usb_rcvbulkpipe(s->udev, 0x81), + s->buf_list[i], + BULK_BUFFER_SIZE, + rtl2832_sdr_urb_complete, s); + + s->urb_list[i]->transfer_flags = URB_NO_TRANSFER_DMA_MAP; + s->urb_list[i]->transfer_dma = s->dma_addr[i]; + s->urbs_initialized++; + } + + return 0; +} + +/* Must be called with vb_queue_lock hold */ +static void rtl2832_sdr_cleanup_queued_bufs(struct rtl2832_sdr_state *s) +{ + unsigned long flags = 0; + dev_dbg(&s->udev->dev, "%s:\n", __func__); + + spin_lock_irqsave(&s->queued_bufs_lock, flags); + while (!list_empty(&s->queued_bufs)) { + struct rtl2832_sdr_frame_buf *buf; + buf = list_entry(s->queued_bufs.next, + struct rtl2832_sdr_frame_buf, list); + list_del(&buf->list); + vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR); + } + spin_unlock_irqrestore(&s->queued_bufs_lock, flags); +} + +/* The user yanked out the cable... */ +static void rtl2832_sdr_release_sec(struct dvb_frontend *fe) +{ + struct rtl2832_sdr_state *s = fe->sec_priv; + dev_dbg(&s->udev->dev, "%s:\n", __func__); + + mutex_lock(&s->vb_queue_lock); + mutex_lock(&s->v4l2_lock); + /* No need to keep the urbs around after disconnection */ + s->udev = NULL; + + v4l2_device_disconnect(&s->v4l2_dev); + video_unregister_device(&s->vdev); + mutex_unlock(&s->v4l2_lock); + mutex_unlock(&s->vb_queue_lock); + + v4l2_device_put(&s->v4l2_dev); + + fe->sec_priv = NULL; +} + +static int rtl2832_sdr_querycap(struct file *file, void *fh, + struct v4l2_capability *cap) +{ + struct rtl2832_sdr_state *s = video_drvdata(file); + dev_dbg(&s->udev->dev, "%s:\n", __func__); + + strlcpy(cap->driver, KBUILD_MODNAME, sizeof(cap->driver)); + strlcpy(cap->card, s->vdev.name, sizeof(cap->card)); + usb_make_path(s->udev, cap->bus_info, sizeof(cap->bus_info)); + cap->device_caps = V4L2_CAP_SDR_CAPTURE | V4L2_CAP_STREAMING | + V4L2_CAP_READWRITE | V4L2_CAP_TUNER; + cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS; + return 0; +} + +/* Videobuf2 operations */ +static int rtl2832_sdr_queue_setup(struct vb2_queue *vq, + const struct v4l2_format *fmt, unsigned int *nbuffers, + unsigned int *nplanes, unsigned int sizes[], void *alloc_ctxs[]) +{ + struct rtl2832_sdr_state *s = vb2_get_drv_priv(vq); + dev_dbg(&s->udev->dev, "%s: *nbuffers=%d\n", __func__, *nbuffers); + + /* Absolute min and max number of buffers available for mmap() */ + *nbuffers = clamp_t(unsigned int, *nbuffers, 8, 32); + *nplanes = 1; + /* 2 = max 16-bit sample returned */ + sizes[0] = PAGE_ALIGN(BULK_BUFFER_SIZE * 2); + dev_dbg(&s->udev->dev, "%s: nbuffers=%d sizes[0]=%d\n", + __func__, *nbuffers, sizes[0]); + return 0; +} + +static int rtl2832_sdr_buf_prepare(struct vb2_buffer *vb) +{ + struct rtl2832_sdr_state *s = vb2_get_drv_priv(vb->vb2_queue); + + /* Don't allow queing new buffers after device disconnection */ + if (!s->udev) + return -ENODEV; + + return 0; +} + +static void rtl2832_sdr_buf_queue(struct vb2_buffer *vb) +{ + struct rtl2832_sdr_state *s = vb2_get_drv_priv(vb->vb2_queue); + struct rtl2832_sdr_frame_buf *buf = + container_of(vb, struct rtl2832_sdr_frame_buf, vb); + unsigned long flags = 0; + + /* Check the device has not disconnected between prep and queuing */ + if (!s->udev) { + vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR); + return; + } + + spin_lock_irqsave(&s->queued_bufs_lock, flags); + list_add_tail(&buf->list, &s->queued_bufs); + spin_unlock_irqrestore(&s->queued_bufs_lock, flags); +} + +static int rtl2832_sdr_set_adc(struct rtl2832_sdr_state *s) +{ + struct dvb_frontend *fe = s->fe; + int ret; + unsigned int f_sr, f_if; + u8 buf[4], u8tmp1, u8tmp2; + u64 u64tmp; + u32 u32tmp; + dev_dbg(&s->udev->dev, "%s: f_adc=%u\n", __func__, s->f_adc); + + if (!test_bit(POWER_ON, &s->flags)) + return 0; + + if (s->f_adc == 0) + return 0; + + f_sr = s->f_adc; + + ret = rtl2832_sdr_wr_regs(s, 0x13e, "\x00\x00", 2); + if (ret) + goto err; + + ret = rtl2832_sdr_wr_regs(s, 0x115, "\x00\x00\x00\x00", 4); + if (ret) + goto err; + + /* get IF from tuner */ + if (fe->ops.tuner_ops.get_if_frequency) + ret = fe->ops.tuner_ops.get_if_frequency(fe, &f_if); + else + ret = -EINVAL; + + if (ret) + goto err; + + /* program IF */ + u64tmp = f_if % s->cfg->xtal; + u64tmp *= 0x400000; + u64tmp = div_u64(u64tmp, s->cfg->xtal); + u64tmp = -u64tmp; + u32tmp = u64tmp & 0x3fffff; + + dev_dbg(&s->udev->dev, "%s: f_if=%u if_ctl=%08x\n", + __func__, f_if, u32tmp); + + buf[0] = (u32tmp >> 16) & 0xff; + buf[1] = (u32tmp >> 8) & 0xff; + buf[2] = (u32tmp >> 0) & 0xff; + + ret = rtl2832_sdr_wr_regs(s, 0x119, buf, 3); + if (ret) + goto err; + + /* BB / IF mode */ + /* POR: 0x1b1=0x1f, 0x008=0x0d, 0x006=0x80 */ + if (f_if) { + u8tmp1 = 0x1a; /* disable Zero-IF */ + u8tmp2 = 0x8d; /* enable ADC I */ + } else { + u8tmp1 = 0x1b; /* enable Zero-IF, DC, IQ */ + u8tmp2 = 0xcd; /* enable ADC I, ADC Q */ + } + + ret = rtl2832_sdr_wr_reg(s, 0x1b1, u8tmp1); + if (ret) + goto err; + + ret = rtl2832_sdr_wr_reg(s, 0x008, u8tmp2); + if (ret) + goto err; + + ret = rtl2832_sdr_wr_reg(s, 0x006, 0x80); + if (ret) + goto err; + + /* program sampling rate (resampling down) */ + u32tmp = div_u64(s->cfg->xtal * 0x400000ULL, f_sr * 4U); + u32tmp <<= 2; + buf[0] = (u32tmp >> 24) & 0xff; + buf[1] = (u32tmp >> 16) & 0xff; + buf[2] = (u32tmp >> 8) & 0xff; + buf[3] = (u32tmp >> 0) & 0xff; + ret = rtl2832_sdr_wr_regs(s, 0x19f, buf, 4); + if (ret) + goto err; + + /* low-pass filter */ + ret = rtl2832_sdr_wr_regs(s, 0x11c, + "\xca\xdc\xd7\xd8\xe0\xf2\x0e\x35\x06\x50\x9c\x0d\x71\x11\x14\x71\x74\x19\x41\xa5", + 20); + if (ret) + goto err; + + ret = rtl2832_sdr_wr_regs(s, 0x017, "\x11\x10", 2); + if (ret) + goto err; + + /* mode */ + ret = rtl2832_sdr_wr_regs(s, 0x019, "\x05", 1); + if (ret) + goto err; + + ret = rtl2832_sdr_wr_regs(s, 0x01a, "\x1b\x16\x0d\x06\x01\xff", 6); + if (ret) + goto err; + + /* FSM */ + ret = rtl2832_sdr_wr_regs(s, 0x192, "\x00\xf0\x0f", 3); + if (ret) + goto err; + + /* PID filter */ + ret = rtl2832_sdr_wr_regs(s, 0x061, "\x60", 1); + if (ret) + goto err; + + /* used RF tuner based settings */ + switch (s->cfg->tuner) { + case RTL2832_TUNER_E4000: + ret = rtl2832_sdr_wr_regs(s, 0x112, "\x5a", 1); + ret = rtl2832_sdr_wr_regs(s, 0x102, "\x40", 1); + ret = rtl2832_sdr_wr_regs(s, 0x103, "\x5a", 1); + ret = rtl2832_sdr_wr_regs(s, 0x1c7, "\x30", 1); + ret = rtl2832_sdr_wr_regs(s, 0x104, "\xd0", 1); + ret = rtl2832_sdr_wr_regs(s, 0x105, "\xbe", 1); + ret = rtl2832_sdr_wr_regs(s, 0x1c8, "\x18", 1); + ret = rtl2832_sdr_wr_regs(s, 0x106, "\x35", 1); + ret = rtl2832_sdr_wr_regs(s, 0x1c9, "\x21", 1); + ret = rtl2832_sdr_wr_regs(s, 0x1ca, "\x21", 1); + ret = rtl2832_sdr_wr_regs(s, 0x1cb, "\x00", 1); + ret = rtl2832_sdr_wr_regs(s, 0x107, "\x40", 1); + ret = rtl2832_sdr_wr_regs(s, 0x1cd, "\x10", 1); + ret = rtl2832_sdr_wr_regs(s, 0x1ce, "\x10", 1); + ret = rtl2832_sdr_wr_regs(s, 0x108, "\x80", 1); + ret = rtl2832_sdr_wr_regs(s, 0x109, "\x7f", 1); + ret = rtl2832_sdr_wr_regs(s, 0x10a, "\x80", 1); + ret = rtl2832_sdr_wr_regs(s, 0x10b, "\x7f", 1); + ret = rtl2832_sdr_wr_regs(s, 0x00e, "\xfc", 1); + ret = rtl2832_sdr_wr_regs(s, 0x00e, "\xfc", 1); + ret = rtl2832_sdr_wr_regs(s, 0x011, "\xd4", 1); + ret = rtl2832_sdr_wr_regs(s, 0x1e5, "\xf0", 1); + ret = rtl2832_sdr_wr_regs(s, 0x1d9, "\x00", 1); + ret = rtl2832_sdr_wr_regs(s, 0x1db, "\x00", 1); + ret = rtl2832_sdr_wr_regs(s, 0x1dd, "\x14", 1); + ret = rtl2832_sdr_wr_regs(s, 0x1de, "\xec", 1); + ret = rtl2832_sdr_wr_regs(s, 0x1d8, "\x0c", 1); + ret = rtl2832_sdr_wr_regs(s, 0x1e6, "\x02", 1); + ret = rtl2832_sdr_wr_regs(s, 0x1d7, "\x09", 1); + ret = rtl2832_sdr_wr_regs(s, 0x00d, "\x83", 1); + ret = rtl2832_sdr_wr_regs(s, 0x010, "\x49", 1); + ret = rtl2832_sdr_wr_regs(s, 0x00d, "\x87", 1); + ret = rtl2832_sdr_wr_regs(s, 0x00d, "\x85", 1); + ret = rtl2832_sdr_wr_regs(s, 0x013, "\x02", 1); + break; + case RTL2832_TUNER_FC0012: + case RTL2832_TUNER_FC0013: + ret = rtl2832_sdr_wr_regs(s, 0x112, "\x5a", 1); + ret = rtl2832_sdr_wr_regs(s, 0x102, "\x40", 1); + ret = rtl2832_sdr_wr_regs(s, 0x103, "\x5a", 1); + ret = rtl2832_sdr_wr_regs(s, 0x1c7, "\x2c", 1); + ret = rtl2832_sdr_wr_regs(s, 0x104, "\xcc", 1); + ret = rtl2832_sdr_wr_regs(s, 0x105, "\xbe", 1); + ret = rtl2832_sdr_wr_regs(s, 0x1c8, "\x16", 1); + ret = rtl2832_sdr_wr_regs(s, 0x106, "\x35", 1); + ret = rtl2832_sdr_wr_regs(s, 0x1c9, "\x21", 1); + ret = rtl2832_sdr_wr_regs(s, 0x1ca, "\x21", 1); + ret = rtl2832_sdr_wr_regs(s, 0x1cb, "\x00", 1); + ret = rtl2832_sdr_wr_regs(s, 0x107, "\x40", 1); + ret = rtl2832_sdr_wr_regs(s, 0x1cd, "\x10", 1); + ret = rtl2832_sdr_wr_regs(s, 0x1ce, "\x10", 1); + ret = rtl2832_sdr_wr_regs(s, 0x108, "\x80", 1); + ret = rtl2832_sdr_wr_regs(s, 0x109, "\x7f", 1); + ret = rtl2832_sdr_wr_regs(s, 0x10a, "\x80", 1); + ret = rtl2832_sdr_wr_regs(s, 0x10b, "\x7f", 1); + ret = rtl2832_sdr_wr_regs(s, 0x00e, "\xfc", 1); + ret = rtl2832_sdr_wr_regs(s, 0x00e, "\xfc", 1); + ret = rtl2832_sdr_wr_regs(s, 0x011, "\xe9\xbf", 2); + ret = rtl2832_sdr_wr_regs(s, 0x1e5, "\xf0", 1); + ret = rtl2832_sdr_wr_regs(s, 0x1d9, "\x00", 1); + ret = rtl2832_sdr_wr_regs(s, 0x1db, "\x00", 1); + ret = rtl2832_sdr_wr_regs(s, 0x1dd, "\x11", 1); + ret = rtl2832_sdr_wr_regs(s, 0x1de, "\xef", 1); + ret = rtl2832_sdr_wr_regs(s, 0x1d8, "\x0c", 1); + ret = rtl2832_sdr_wr_regs(s, 0x1e6, "\x02", 1); + ret = rtl2832_sdr_wr_regs(s, 0x1d7, "\x09", 1); + break; + case RTL2832_TUNER_R820T: + ret = rtl2832_sdr_wr_regs(s, 0x112, "\x5a", 1); + ret = rtl2832_sdr_wr_regs(s, 0x102, "\x40", 1); + ret = rtl2832_sdr_wr_regs(s, 0x115, "\x01", 1); + ret = rtl2832_sdr_wr_regs(s, 0x103, "\x80", 1); + ret = rtl2832_sdr_wr_regs(s, 0x1c7, "\x24", 1); + ret = rtl2832_sdr_wr_regs(s, 0x104, "\xcc", 1); + ret = rtl2832_sdr_wr_regs(s, 0x105, "\xbe", 1); + ret = rtl2832_sdr_wr_regs(s, 0x1c8, "\x14", 1); + ret = rtl2832_sdr_wr_regs(s, 0x106, "\x35", 1); + ret = rtl2832_sdr_wr_regs(s, 0x1c9, "\x21", 1); + ret = rtl2832_sdr_wr_regs(s, 0x1ca, "\x21", 1); + ret = rtl2832_sdr_wr_regs(s, 0x1cb, "\x00", 1); + ret = rtl2832_sdr_wr_regs(s, 0x107, "\x40", 1); + ret = rtl2832_sdr_wr_regs(s, 0x1cd, "\x10", 1); + ret = rtl2832_sdr_wr_regs(s, 0x1ce, "\x10", 1); + ret = rtl2832_sdr_wr_regs(s, 0x108, "\x80", 1); + ret = rtl2832_sdr_wr_regs(s, 0x109, "\x7f", 1); + ret = rtl2832_sdr_wr_regs(s, 0x10a, "\x80", 1); + ret = rtl2832_sdr_wr_regs(s, 0x10b, "\x7f", 1); + ret = rtl2832_sdr_wr_regs(s, 0x00e, "\xfc", 1); + ret = rtl2832_sdr_wr_regs(s, 0x00e, "\xfc", 1); + ret = rtl2832_sdr_wr_regs(s, 0x011, "\xf4", 1); + break; + default: + dev_notice(&s->udev->dev, "Unsupported tuner\n"); + } + + /* software reset */ + ret = rtl2832_sdr_wr_reg_mask(s, 0x101, 0x04, 0x04); + if (ret) + goto err; + + ret = rtl2832_sdr_wr_reg_mask(s, 0x101, 0x00, 0x04); + if (ret) + goto err; +err: + return ret; +}; + +static void rtl2832_sdr_unset_adc(struct rtl2832_sdr_state *s) +{ + int ret; + + dev_dbg(&s->udev->dev, "%s:\n", __func__); + + /* PID filter */ + ret = rtl2832_sdr_wr_regs(s, 0x061, "\xe0", 1); + if (ret) + goto err; + + /* mode */ + ret = rtl2832_sdr_wr_regs(s, 0x019, "\x20", 1); + if (ret) + goto err; + + ret = rtl2832_sdr_wr_regs(s, 0x017, "\x11\x10", 2); + if (ret) + goto err; + + /* FSM */ + ret = rtl2832_sdr_wr_regs(s, 0x192, "\x00\x0f\xff", 3); + if (ret) + goto err; + + ret = rtl2832_sdr_wr_regs(s, 0x13e, "\x40\x00", 2); + if (ret) + goto err; + + ret = rtl2832_sdr_wr_regs(s, 0x115, "\x06\x3f\xce\xcc", 4); + if (ret) + goto err; +err: + return; +}; + +static int rtl2832_sdr_set_tuner_freq(struct rtl2832_sdr_state *s) +{ + struct dvb_frontend *fe = s->fe; + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + struct v4l2_ctrl *bandwidth_auto; + struct v4l2_ctrl *bandwidth; + + /* + * tuner RF (Hz) + */ + if (s->f_tuner == 0) + return 0; + + /* + * bandwidth (Hz) + */ + bandwidth_auto = v4l2_ctrl_find(&s->hdl, V4L2_CID_RF_TUNER_BANDWIDTH_AUTO); + bandwidth = v4l2_ctrl_find(&s->hdl, V4L2_CID_RF_TUNER_BANDWIDTH); + if (v4l2_ctrl_g_ctrl(bandwidth_auto)) { + c->bandwidth_hz = s->f_adc; + v4l2_ctrl_s_ctrl(bandwidth, s->f_adc); + } else { + c->bandwidth_hz = v4l2_ctrl_g_ctrl(bandwidth); + } + + c->frequency = s->f_tuner; + c->delivery_system = SYS_DVBT; + + dev_dbg(&s->udev->dev, "%s: frequency=%u bandwidth=%d\n", + __func__, c->frequency, c->bandwidth_hz); + + if (!test_bit(POWER_ON, &s->flags)) + return 0; + + if (fe->ops.tuner_ops.set_params) + fe->ops.tuner_ops.set_params(fe); + + return 0; +}; + +static int rtl2832_sdr_set_tuner(struct rtl2832_sdr_state *s) +{ + struct dvb_frontend *fe = s->fe; + + dev_dbg(&s->udev->dev, "%s:\n", __func__); + + if (fe->ops.tuner_ops.init) + fe->ops.tuner_ops.init(fe); + + return 0; +}; + +static void rtl2832_sdr_unset_tuner(struct rtl2832_sdr_state *s) +{ + struct dvb_frontend *fe = s->fe; + + dev_dbg(&s->udev->dev, "%s:\n", __func__); + + if (fe->ops.tuner_ops.sleep) + fe->ops.tuner_ops.sleep(fe); + + return; +}; + +static int rtl2832_sdr_start_streaming(struct vb2_queue *vq, unsigned int count) +{ + struct rtl2832_sdr_state *s = vb2_get_drv_priv(vq); + int ret; + dev_dbg(&s->udev->dev, "%s:\n", __func__); + + if (!s->udev) + return -ENODEV; + + if (mutex_lock_interruptible(&s->v4l2_lock)) + return -ERESTARTSYS; + + if (s->d->props->power_ctrl) + s->d->props->power_ctrl(s->d, 1); + + set_bit(POWER_ON, &s->flags); + + ret = rtl2832_sdr_set_tuner(s); + if (ret) + goto err; + + ret = rtl2832_sdr_set_tuner_freq(s); + if (ret) + goto err; + + ret = rtl2832_sdr_set_adc(s); + if (ret) + goto err; + + ret = rtl2832_sdr_alloc_stream_bufs(s); + if (ret) + goto err; + + ret = rtl2832_sdr_alloc_urbs(s); + if (ret) + goto err; + + ret = rtl2832_sdr_submit_urbs(s); + if (ret) + goto err; + +err: + mutex_unlock(&s->v4l2_lock); + + return ret; +} + +static int rtl2832_sdr_stop_streaming(struct vb2_queue *vq) +{ + struct rtl2832_sdr_state *s = vb2_get_drv_priv(vq); + dev_dbg(&s->udev->dev, "%s:\n", __func__); + + if (mutex_lock_interruptible(&s->v4l2_lock)) + return -ERESTARTSYS; + + rtl2832_sdr_kill_urbs(s); + rtl2832_sdr_free_urbs(s); + rtl2832_sdr_free_stream_bufs(s); + rtl2832_sdr_cleanup_queued_bufs(s); + rtl2832_sdr_unset_adc(s); + rtl2832_sdr_unset_tuner(s); + + clear_bit(POWER_ON, &s->flags); + + if (s->d->props->power_ctrl) + s->d->props->power_ctrl(s->d, 0); + + mutex_unlock(&s->v4l2_lock); + + return 0; +} + +static struct vb2_ops rtl2832_sdr_vb2_ops = { + .queue_setup = rtl2832_sdr_queue_setup, + .buf_prepare = rtl2832_sdr_buf_prepare, + .buf_queue = rtl2832_sdr_buf_queue, + .start_streaming = rtl2832_sdr_start_streaming, + .stop_streaming = rtl2832_sdr_stop_streaming, + .wait_prepare = vb2_ops_wait_prepare, + .wait_finish = vb2_ops_wait_finish, +}; + +static int rtl2832_sdr_g_tuner(struct file *file, void *priv, + struct v4l2_tuner *v) +{ + struct rtl2832_sdr_state *s = video_drvdata(file); + dev_dbg(&s->udev->dev, "%s: index=%d type=%d\n", + __func__, v->index, v->type); + + if (v->index == 0) { + strlcpy(v->name, "ADC: Realtek RTL2832", sizeof(v->name)); + v->type = V4L2_TUNER_ADC; + v->capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS; + v->rangelow = 300000; + v->rangehigh = 3200000; + } else if (v->index == 1) { + strlcpy(v->name, "RF: ", sizeof(v->name)); + v->type = V4L2_TUNER_RF; + v->capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS; + v->rangelow = 50000000; + v->rangehigh = 2000000000; + } else { + return -EINVAL; + } + + return 0; +} + +static int rtl2832_sdr_s_tuner(struct file *file, void *priv, + const struct v4l2_tuner *v) +{ + struct rtl2832_sdr_state *s = video_drvdata(file); + dev_dbg(&s->udev->dev, "%s:\n", __func__); + + return 0; +} + +static int rtl2832_sdr_enum_freq_bands(struct file *file, void *priv, + struct v4l2_frequency_band *band) +{ + struct rtl2832_sdr_state *s = video_drvdata(file); + dev_dbg(&s->udev->dev, "%s: tuner=%d type=%d index=%d\n", + __func__, band->tuner, band->type, band->index); + + if (band->tuner == 0) { + if (band->index >= ARRAY_SIZE(bands_adc)) + return -EINVAL; + + *band = bands_adc[band->index]; + } else if (band->tuner == 1) { + if (band->index >= ARRAY_SIZE(bands_fm)) + return -EINVAL; + + *band = bands_fm[band->index]; + } else { + return -EINVAL; + } + + return 0; +} + +static int rtl2832_sdr_g_frequency(struct file *file, void *priv, + struct v4l2_frequency *f) +{ + struct rtl2832_sdr_state *s = video_drvdata(file); + int ret = 0; + dev_dbg(&s->udev->dev, "%s: tuner=%d type=%d\n", + __func__, f->tuner, f->type); + + if (f->tuner == 0) + f->frequency = s->f_adc; + else if (f->tuner == 1) + f->frequency = s->f_tuner; + else + return -EINVAL; + + return ret; +} + +static int rtl2832_sdr_s_frequency(struct file *file, void *priv, + const struct v4l2_frequency *f) +{ + struct rtl2832_sdr_state *s = video_drvdata(file); + int ret, band; + + dev_dbg(&s->udev->dev, "%s: tuner=%d type=%d frequency=%u\n", + __func__, f->tuner, f->type, f->frequency); + + /* ADC band midpoints */ + #define BAND_ADC_0 ((bands_adc[0].rangehigh + bands_adc[1].rangelow) / 2) + #define BAND_ADC_1 ((bands_adc[1].rangehigh + bands_adc[2].rangelow) / 2) + + if (f->tuner == 0 && f->type == V4L2_TUNER_ADC) { + if (f->frequency < BAND_ADC_0) + band = 0; + else if (f->frequency < BAND_ADC_1) + band = 1; + else + band = 2; + + s->f_adc = clamp_t(unsigned int, f->frequency, + bands_adc[band].rangelow, + bands_adc[band].rangehigh); + + dev_dbg(&s->udev->dev, "%s: ADC frequency=%u Hz\n", + __func__, s->f_adc); + ret = rtl2832_sdr_set_adc(s); + } else if (f->tuner == 1) { + s->f_tuner = f->frequency; + dev_dbg(&s->udev->dev, "%s: RF frequency=%u Hz\n", + __func__, f->frequency); + + ret = rtl2832_sdr_set_tuner_freq(s); + } else { + ret = -EINVAL; + } + + return ret; +} + +static int rtl2832_sdr_enum_fmt_sdr_cap(struct file *file, void *priv, + struct v4l2_fmtdesc *f) +{ + struct rtl2832_sdr_state *s = video_drvdata(file); + dev_dbg(&s->udev->dev, "%s:\n", __func__); + + if (f->index >= NUM_FORMATS) + return -EINVAL; + + strlcpy(f->description, formats[f->index].name, sizeof(f->description)); + f->pixelformat = formats[f->index].pixelformat; + + return 0; +} + +static int rtl2832_sdr_g_fmt_sdr_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct rtl2832_sdr_state *s = video_drvdata(file); + dev_dbg(&s->udev->dev, "%s:\n", __func__); + + f->fmt.sdr.pixelformat = s->pixelformat; + + return 0; +} + +static int rtl2832_sdr_s_fmt_sdr_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct rtl2832_sdr_state *s = video_drvdata(file); + struct vb2_queue *q = &s->vb_queue; + int i; + dev_dbg(&s->udev->dev, "%s: pixelformat fourcc %4.4s\n", __func__, + (char *)&f->fmt.sdr.pixelformat); + + if (vb2_is_busy(q)) + return -EBUSY; + + for (i = 0; i < NUM_FORMATS; i++) { + if (formats[i].pixelformat == f->fmt.sdr.pixelformat) { + s->pixelformat = f->fmt.sdr.pixelformat; + return 0; + } + } + + f->fmt.sdr.pixelformat = formats[0].pixelformat; + s->pixelformat = formats[0].pixelformat; + + return 0; +} + +static int rtl2832_sdr_try_fmt_sdr_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct rtl2832_sdr_state *s = video_drvdata(file); + int i; + dev_dbg(&s->udev->dev, "%s: pixelformat fourcc %4.4s\n", __func__, + (char *)&f->fmt.sdr.pixelformat); + + for (i = 0; i < NUM_FORMATS; i++) { + if (formats[i].pixelformat == f->fmt.sdr.pixelformat) + return 0; + } + + f->fmt.sdr.pixelformat = formats[0].pixelformat; + + return 0; +} + +static const struct v4l2_ioctl_ops rtl2832_sdr_ioctl_ops = { + .vidioc_querycap = rtl2832_sdr_querycap, + + .vidioc_enum_fmt_sdr_cap = rtl2832_sdr_enum_fmt_sdr_cap, + .vidioc_g_fmt_sdr_cap = rtl2832_sdr_g_fmt_sdr_cap, + .vidioc_s_fmt_sdr_cap = rtl2832_sdr_s_fmt_sdr_cap, + .vidioc_try_fmt_sdr_cap = rtl2832_sdr_try_fmt_sdr_cap, + + .vidioc_reqbufs = vb2_ioctl_reqbufs, + .vidioc_create_bufs = vb2_ioctl_create_bufs, + .vidioc_prepare_buf = vb2_ioctl_prepare_buf, + .vidioc_querybuf = vb2_ioctl_querybuf, + .vidioc_qbuf = vb2_ioctl_qbuf, + .vidioc_dqbuf = vb2_ioctl_dqbuf, + + .vidioc_streamon = vb2_ioctl_streamon, + .vidioc_streamoff = vb2_ioctl_streamoff, + + .vidioc_g_tuner = rtl2832_sdr_g_tuner, + .vidioc_s_tuner = rtl2832_sdr_s_tuner, + + .vidioc_enum_freq_bands = rtl2832_sdr_enum_freq_bands, + .vidioc_g_frequency = rtl2832_sdr_g_frequency, + .vidioc_s_frequency = rtl2832_sdr_s_frequency, + + .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, + .vidioc_unsubscribe_event = v4l2_event_unsubscribe, + .vidioc_log_status = v4l2_ctrl_log_status, +}; + +static const struct v4l2_file_operations rtl2832_sdr_fops = { + .owner = THIS_MODULE, + .open = v4l2_fh_open, + .release = vb2_fop_release, + .read = vb2_fop_read, + .poll = vb2_fop_poll, + .mmap = vb2_fop_mmap, + .unlocked_ioctl = video_ioctl2, +}; + +static struct video_device rtl2832_sdr_template = { + .name = "Realtek RTL2832 SDR", + .release = video_device_release_empty, + .fops = &rtl2832_sdr_fops, + .ioctl_ops = &rtl2832_sdr_ioctl_ops, +}; + +static int rtl2832_sdr_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct rtl2832_sdr_state *s = + container_of(ctrl->handler, struct rtl2832_sdr_state, + hdl); + struct dvb_frontend *fe = s->fe; + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + int ret; + dev_dbg(&s->udev->dev, + "%s: id=%d name=%s val=%d min=%d max=%d step=%d\n", + __func__, ctrl->id, ctrl->name, ctrl->val, + ctrl->minimum, ctrl->maximum, ctrl->step); + + switch (ctrl->id) { + case V4L2_CID_RF_TUNER_BANDWIDTH_AUTO: + case V4L2_CID_RF_TUNER_BANDWIDTH: + if (s->bandwidth_auto->val) + s->bandwidth->val = s->f_adc; + + c->bandwidth_hz = s->bandwidth->val; + + if (!test_bit(POWER_ON, &s->flags)) + return 0; + + if (fe->ops.tuner_ops.set_params) + ret = fe->ops.tuner_ops.set_params(fe); + else + ret = 0; + break; + default: + ret = -EINVAL; + } + + return ret; +} + +static const struct v4l2_ctrl_ops rtl2832_sdr_ctrl_ops = { + .s_ctrl = rtl2832_sdr_s_ctrl, +}; + +static void rtl2832_sdr_video_release(struct v4l2_device *v) +{ + struct rtl2832_sdr_state *s = + container_of(v, struct rtl2832_sdr_state, v4l2_dev); + + v4l2_ctrl_handler_free(&s->hdl); + v4l2_device_unregister(&s->v4l2_dev); + kfree(s); +} + +struct dvb_frontend *rtl2832_sdr_attach(struct dvb_frontend *fe, + struct i2c_adapter *i2c, const struct rtl2832_config *cfg, + struct v4l2_subdev *sd) +{ + int ret; + struct rtl2832_sdr_state *s; + const struct v4l2_ctrl_ops *ops = &rtl2832_sdr_ctrl_ops; + struct dvb_usb_device *d = i2c_get_adapdata(i2c); + + s = kzalloc(sizeof(struct rtl2832_sdr_state), GFP_KERNEL); + if (s == NULL) { + dev_err(&d->udev->dev, + "Could not allocate memory for rtl2832_sdr_state\n"); + return NULL; + } + + /* setup the state */ + s->fe = fe; + s->d = d; + s->udev = d->udev; + s->i2c = i2c; + s->cfg = cfg; + s->f_adc = bands_adc[0].rangelow; + s->pixelformat = V4L2_SDR_FMT_CU8; + + mutex_init(&s->v4l2_lock); + mutex_init(&s->vb_queue_lock); + spin_lock_init(&s->queued_bufs_lock); + INIT_LIST_HEAD(&s->queued_bufs); + + /* Init videobuf2 queue structure */ + s->vb_queue.type = V4L2_BUF_TYPE_SDR_CAPTURE; + s->vb_queue.io_modes = VB2_MMAP | VB2_USERPTR | VB2_READ; + s->vb_queue.drv_priv = s; + s->vb_queue.buf_struct_size = sizeof(struct rtl2832_sdr_frame_buf); + s->vb_queue.ops = &rtl2832_sdr_vb2_ops; + s->vb_queue.mem_ops = &vb2_vmalloc_memops; + s->vb_queue.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + ret = vb2_queue_init(&s->vb_queue); + if (ret) { + dev_err(&s->udev->dev, "Could not initialize vb2 queue\n"); + goto err_free_mem; + } + + /* Register controls */ + switch (s->cfg->tuner) { + case RTL2832_TUNER_E4000: + v4l2_ctrl_handler_init(&s->hdl, 2); + s->bandwidth_auto = v4l2_ctrl_new_std(&s->hdl, ops, V4L2_CID_RF_TUNER_BANDWIDTH_AUTO, 0, 1, 1, 1); + s->bandwidth = v4l2_ctrl_new_std(&s->hdl, ops, V4L2_CID_RF_TUNER_BANDWIDTH, 4300000, 11000000, 100000, 4300000); + v4l2_ctrl_auto_cluster(2, &s->bandwidth_auto, 0, false); + break; + case RTL2832_TUNER_R820T: + v4l2_ctrl_handler_init(&s->hdl, 2); + s->bandwidth_auto = v4l2_ctrl_new_std(&s->hdl, ops, V4L2_CID_RF_TUNER_BANDWIDTH_AUTO, 0, 1, 1, 1); + s->bandwidth = v4l2_ctrl_new_std(&s->hdl, ops, V4L2_CID_RF_TUNER_BANDWIDTH, 0, 8000000, 100000, 0); + v4l2_ctrl_auto_cluster(2, &s->bandwidth_auto, 0, false); + break; + case RTL2832_TUNER_FC0012: + case RTL2832_TUNER_FC0013: + v4l2_ctrl_handler_init(&s->hdl, 2); + s->bandwidth_auto = v4l2_ctrl_new_std(&s->hdl, ops, V4L2_CID_RF_TUNER_BANDWIDTH_AUTO, 0, 1, 1, 1); + s->bandwidth = v4l2_ctrl_new_std(&s->hdl, ops, V4L2_CID_RF_TUNER_BANDWIDTH, 6000000, 8000000, 1000000, 6000000); + v4l2_ctrl_auto_cluster(2, &s->bandwidth_auto, 0, false); + break; + default: + v4l2_ctrl_handler_init(&s->hdl, 0); + dev_notice(&s->udev->dev, "%s: Unsupported tuner\n", + KBUILD_MODNAME); + goto err_free_controls; + } + + if (s->hdl.error) { + ret = s->hdl.error; + dev_err(&s->udev->dev, "Could not initialize controls\n"); + goto err_free_controls; + } + + /* Init video_device structure */ + s->vdev = rtl2832_sdr_template; + s->vdev.queue = &s->vb_queue; + s->vdev.queue->lock = &s->vb_queue_lock; + set_bit(V4L2_FL_USE_FH_PRIO, &s->vdev.flags); + video_set_drvdata(&s->vdev, s); + + /* Register the v4l2_device structure */ + s->v4l2_dev.release = rtl2832_sdr_video_release; + ret = v4l2_device_register(&s->udev->dev, &s->v4l2_dev); + if (ret) { + dev_err(&s->udev->dev, + "Failed to register v4l2-device (%d)\n", ret); + goto err_free_controls; + } + + s->v4l2_dev.ctrl_handler = &s->hdl; + s->vdev.v4l2_dev = &s->v4l2_dev; + s->vdev.lock = &s->v4l2_lock; + s->vdev.vfl_dir = VFL_DIR_RX; + + ret = video_register_device(&s->vdev, VFL_TYPE_SDR, -1); + if (ret) { + dev_err(&s->udev->dev, + "Failed to register as video device (%d)\n", + ret); + goto err_unregister_v4l2_dev; + } + dev_info(&s->udev->dev, "Registered as %s\n", + video_device_node_name(&s->vdev)); + + fe->sec_priv = s; + fe->ops.release_sec = rtl2832_sdr_release_sec; + + dev_info(&s->i2c->dev, "%s: Realtek RTL2832 SDR attached\n", + KBUILD_MODNAME); + return fe; + +err_unregister_v4l2_dev: + v4l2_device_unregister(&s->v4l2_dev); +err_free_controls: + v4l2_ctrl_handler_free(&s->hdl); +err_free_mem: + kfree(s); + return NULL; +} +EXPORT_SYMBOL(rtl2832_sdr_attach); + +MODULE_AUTHOR("Antti Palosaari "); +MODULE_DESCRIPTION("Realtek RTL2832 SDR driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/staging/media/rtl2832u_sdr/rtl2832_sdr.h b/drivers/staging/media/rtl2832u_sdr/rtl2832_sdr.h new file mode 100644 index 0000000..b865fad --- /dev/null +++ b/drivers/staging/media/rtl2832u_sdr/rtl2832_sdr.h @@ -0,0 +1,54 @@ +/* + * Realtek RTL2832U SDR driver + * + * Copyright (C) 2013 Antti Palosaari + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * GNU Radio plugin "gr-kernel" for device usage will be on: + * http://git.linuxtv.org/anttip/gr-kernel.git + * + * TODO: + * Help is very highly welcome for these + all the others you could imagine: + * - move controls to V4L2 API + * - use libv4l2 for stream format conversions + * - gr-kernel: switch to v4l2_mmap (current read eats a lot of cpu) + * - SDRSharp support + */ + +#ifndef RTL2832_SDR_H +#define RTL2832_SDR_H + +#include +#include + +/* for config struct */ +#include "rtl2832.h" + +#if IS_ENABLED(CONFIG_DVB_RTL2832_SDR) +extern struct dvb_frontend *rtl2832_sdr_attach(struct dvb_frontend *fe, + struct i2c_adapter *i2c, const struct rtl2832_config *cfg, + struct v4l2_subdev *sd); +#else +static inline struct dvb_frontend *rtl2832_sdr_attach(struct dvb_frontend *fe, + struct i2c_adapter *i2c, const struct rtl2832_config *cfg, + struct v4l2_subdev *sd) +{ + dev_warn(&i2c->dev, "%s: driver disabled by Kconfig\n", __func__); + return NULL; +} +#endif + +#endif /* RTL2832_SDR_H */ -- cgit v1.1 From 09143009d44e615068ac108bf23b69b5fcf85cbe Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Mon, 10 Feb 2014 22:15:01 -0300 Subject: [media] rtl2832_sdr: expose e4000 controls to user E4000 tuner driver provides now some controls. Expose those to userland. Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- drivers/staging/media/rtl2832u_sdr/rtl2832_sdr.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/staging/media/rtl2832u_sdr/rtl2832_sdr.c b/drivers/staging/media/rtl2832u_sdr/rtl2832_sdr.c index 86fffcf..7e20576 100644 --- a/drivers/staging/media/rtl2832u_sdr/rtl2832_sdr.c +++ b/drivers/staging/media/rtl2832u_sdr/rtl2832_sdr.c @@ -1387,10 +1387,9 @@ struct dvb_frontend *rtl2832_sdr_attach(struct dvb_frontend *fe, /* Register controls */ switch (s->cfg->tuner) { case RTL2832_TUNER_E4000: - v4l2_ctrl_handler_init(&s->hdl, 2); - s->bandwidth_auto = v4l2_ctrl_new_std(&s->hdl, ops, V4L2_CID_RF_TUNER_BANDWIDTH_AUTO, 0, 1, 1, 1); - s->bandwidth = v4l2_ctrl_new_std(&s->hdl, ops, V4L2_CID_RF_TUNER_BANDWIDTH, 4300000, 11000000, 100000, 4300000); - v4l2_ctrl_auto_cluster(2, &s->bandwidth_auto, 0, false); + v4l2_ctrl_handler_init(&s->hdl, 9); + if (sd) + v4l2_ctrl_add_handler(&s->hdl, sd->ctrl_handler, NULL); break; case RTL2832_TUNER_R820T: v4l2_ctrl_handler_init(&s->hdl, 2); -- cgit v1.1 From e8b4668937c4892685b970a94de851c5fdd27571 Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Sat, 12 Oct 2013 23:35:35 -0300 Subject: [media] rtl28xxu: constify demod config structs Optimize a little bit from data to text. Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/dvb-usb-v2/rtl28xxu.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/media/usb/dvb-usb-v2/rtl28xxu.c b/drivers/media/usb/dvb-usb-v2/rtl28xxu.c index ae07740..db98f1c 100644 --- a/drivers/media/usb/dvb-usb-v2/rtl28xxu.c +++ b/drivers/media/usb/dvb-usb-v2/rtl28xxu.c @@ -516,7 +516,7 @@ err: return ret; } -static struct rtl2830_config rtl28xxu_rtl2830_mt2060_config = { +static const struct rtl2830_config rtl28xxu_rtl2830_mt2060_config = { .i2c_addr = 0x10, /* 0x20 */ .xtal = 28800000, .ts_mode = 0, @@ -527,7 +527,7 @@ static struct rtl2830_config rtl28xxu_rtl2830_mt2060_config = { }; -static struct rtl2830_config rtl28xxu_rtl2830_qt1010_config = { +static const struct rtl2830_config rtl28xxu_rtl2830_qt1010_config = { .i2c_addr = 0x10, /* 0x20 */ .xtal = 28800000, .ts_mode = 0, @@ -537,7 +537,7 @@ static struct rtl2830_config rtl28xxu_rtl2830_qt1010_config = { .agc_targ_val = 0x2d, }; -static struct rtl2830_config rtl28xxu_rtl2830_mxl5005s_config = { +static const struct rtl2830_config rtl28xxu_rtl2830_mxl5005s_config = { .i2c_addr = 0x10, /* 0x20 */ .xtal = 28800000, .ts_mode = 0, @@ -551,7 +551,7 @@ static int rtl2831u_frontend_attach(struct dvb_usb_adapter *adap) { struct dvb_usb_device *d = adap_to_d(adap); struct rtl28xxu_priv *priv = d_to_priv(d); - struct rtl2830_config *rtl2830_config; + const struct rtl2830_config *rtl2830_config; int ret; dev_dbg(&d->udev->dev, "%s:\n", __func__); @@ -586,31 +586,31 @@ err: return ret; } -static struct rtl2832_config rtl28xxu_rtl2832_fc0012_config = { +static const struct rtl2832_config rtl28xxu_rtl2832_fc0012_config = { .i2c_addr = 0x10, /* 0x20 */ .xtal = 28800000, .tuner = TUNER_RTL2832_FC0012 }; -static struct rtl2832_config rtl28xxu_rtl2832_fc0013_config = { +static const struct rtl2832_config rtl28xxu_rtl2832_fc0013_config = { .i2c_addr = 0x10, /* 0x20 */ .xtal = 28800000, .tuner = TUNER_RTL2832_FC0013 }; -static struct rtl2832_config rtl28xxu_rtl2832_tua9001_config = { +static const struct rtl2832_config rtl28xxu_rtl2832_tua9001_config = { .i2c_addr = 0x10, /* 0x20 */ .xtal = 28800000, .tuner = TUNER_RTL2832_TUA9001, }; -static struct rtl2832_config rtl28xxu_rtl2832_e4000_config = { +static const struct rtl2832_config rtl28xxu_rtl2832_e4000_config = { .i2c_addr = 0x10, /* 0x20 */ .xtal = 28800000, .tuner = TUNER_RTL2832_E4000, }; -static struct rtl2832_config rtl28xxu_rtl2832_r820t_config = { +static const struct rtl2832_config rtl28xxu_rtl2832_r820t_config = { .i2c_addr = 0x10, .xtal = 28800000, .tuner = TUNER_RTL2832_R820T, @@ -734,7 +734,7 @@ static int rtl2832u_frontend_attach(struct dvb_usb_adapter *adap) int ret; struct dvb_usb_device *d = adap_to_d(adap); struct rtl28xxu_priv *priv = d_to_priv(d); - struct rtl2832_config *rtl2832_config; + const struct rtl2832_config *rtl2832_config; dev_dbg(&d->udev->dev, "%s:\n", __func__); -- cgit v1.1 From bcf43393579e3d4069e75a9200a87703185bcf11 Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Tue, 10 Sep 2013 00:13:57 -0300 Subject: [media] rtl28xxu: attach SDR extension module With that extension module it supports SDR. Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/dvb-usb-v2/Makefile | 1 + drivers/media/usb/dvb-usb-v2/rtl28xxu.c | 20 ++++++++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/drivers/media/usb/dvb-usb-v2/Makefile b/drivers/media/usb/dvb-usb-v2/Makefile index bc38f03..7407b83 100644 --- a/drivers/media/usb/dvb-usb-v2/Makefile +++ b/drivers/media/usb/dvb-usb-v2/Makefile @@ -41,3 +41,4 @@ ccflags-y += -I$(srctree)/drivers/media/dvb-core ccflags-y += -I$(srctree)/drivers/media/dvb-frontends ccflags-y += -I$(srctree)/drivers/media/tuners ccflags-y += -I$(srctree)/drivers/media/common +ccflags-y += -I$(srctree)/drivers/staging/media/rtl2832u_sdr diff --git a/drivers/media/usb/dvb-usb-v2/rtl28xxu.c b/drivers/media/usb/dvb-usb-v2/rtl28xxu.c index db98f1c..61b420c 100644 --- a/drivers/media/usb/dvb-usb-v2/rtl28xxu.c +++ b/drivers/media/usb/dvb-usb-v2/rtl28xxu.c @@ -24,6 +24,7 @@ #include "rtl2830.h" #include "rtl2832.h" +#include "rtl2832_sdr.h" #include "qt1010.h" #include "mt2060.h" @@ -902,6 +903,10 @@ static int rtl2832u_tuner_attach(struct dvb_usb_adapter *adap) * that to the tuner driver */ adap->fe[0]->ops.read_signal_strength = adap->fe[0]->ops.tuner_ops.get_rf_strength; + + /* attach SDR */ + dvb_attach(rtl2832_sdr_attach, adap->fe[0], &d->i2c_adap, + &rtl28xxu_rtl2832_fc0012_config, NULL); return 0; break; case TUNER_RTL2832_FC0013: @@ -911,8 +916,13 @@ static int rtl2832u_tuner_attach(struct dvb_usb_adapter *adap) /* fc0013 also supports signal strength reading */ adap->fe[0]->ops.read_signal_strength = adap->fe[0]->ops.tuner_ops.get_rf_strength; + + /* attach SDR */ + dvb_attach(rtl2832_sdr_attach, adap->fe[0], &d->i2c_adap, + &rtl28xxu_rtl2832_fc0013_config, NULL); return 0; case TUNER_RTL2832_E4000: { + struct v4l2_subdev *sd; struct e4000_config e4000_config = { .fe = adap->fe[0], .clock = 28800000, @@ -933,6 +943,12 @@ static int rtl2832u_tuner_attach(struct dvb_usb_adapter *adap) } priv->client = client; + sd = i2c_get_clientdata(client); + + /* attach SDR */ + dvb_attach(rtl2832_sdr_attach, adap->fe[0], + &d->i2c_adap, + &rtl28xxu_rtl2832_e4000_config, sd); } break; case TUNER_RTL2832_FC2580: @@ -959,6 +975,10 @@ static int rtl2832u_tuner_attach(struct dvb_usb_adapter *adap) /* Use tuner to get the signal strength */ adap->fe[0]->ops.read_signal_strength = adap->fe[0]->ops.tuner_ops.get_rf_strength; + + /* attach SDR */ + dvb_attach(rtl2832_sdr_attach, adap->fe[0], &d->i2c_adap, + &rtl28xxu_rtl2832_r820t_config, NULL); break; case TUNER_RTL2832_R828D: /* power off mn88472 demod on GPIO0 */ -- cgit v1.1 From 55cdb7ddf1a6aeae198c0903ff74008c2d2ea937 Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Mon, 3 Feb 2014 23:07:21 -0300 Subject: [media] rtl28xxu: fix switch-case style issue Use break, not return, for every case. Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/dvb-usb-v2/rtl28xxu.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/media/usb/dvb-usb-v2/rtl28xxu.c b/drivers/media/usb/dvb-usb-v2/rtl28xxu.c index 61b420c..f51949e 100644 --- a/drivers/media/usb/dvb-usb-v2/rtl28xxu.c +++ b/drivers/media/usb/dvb-usb-v2/rtl28xxu.c @@ -907,7 +907,6 @@ static int rtl2832u_tuner_attach(struct dvb_usb_adapter *adap) /* attach SDR */ dvb_attach(rtl2832_sdr_attach, adap->fe[0], &d->i2c_adap, &rtl28xxu_rtl2832_fc0012_config, NULL); - return 0; break; case TUNER_RTL2832_FC0013: fe = dvb_attach(fc0013_attach, adap->fe[0], @@ -920,7 +919,7 @@ static int rtl2832u_tuner_attach(struct dvb_usb_adapter *adap) /* attach SDR */ dvb_attach(rtl2832_sdr_attach, adap->fe[0], &d->i2c_adap, &rtl28xxu_rtl2832_fc0013_config, NULL); - return 0; + break; case TUNER_RTL2832_E4000: { struct v4l2_subdev *sd; struct e4000_config e4000_config = { -- cgit v1.1 From 3d0a73aaa95e0bdbf1462779811acbe0af7bb39e Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Mon, 10 Mar 2014 15:18:55 -0300 Subject: [media] rtl28xxu: depends on I2C_MUX We need depend on I2C_MUX as rtl2832 demod used requires it. All error/warnings: warning: (DVB_USB_RTL28XXU) selects DVB_RTL2832 which has unmet direct dependencies (MEDIA_SUPPORT && DVB_CORE && I2C && I2C_MUX) ERROR: "i2c_add_mux_adapter" [drivers/media/dvb-frontends/rtl2832.ko] undefined! ERROR: "i2c_del_mux_adapter" [drivers/media/dvb-frontends/rtl2832.ko] undefined! Reported-by: kbuild test robot Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/dvb-usb-v2/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/usb/dvb-usb-v2/Kconfig b/drivers/media/usb/dvb-usb-v2/Kconfig index bfb7378..037e519 100644 --- a/drivers/media/usb/dvb-usb-v2/Kconfig +++ b/drivers/media/usb/dvb-usb-v2/Kconfig @@ -126,7 +126,7 @@ config DVB_USB_MXL111SF config DVB_USB_RTL28XXU tristate "Realtek RTL28xxU DVB USB support" - depends on DVB_USB_V2 + depends on DVB_USB_V2 && I2C_MUX select DVB_RTL2830 select DVB_RTL2832 select MEDIA_TUNER_QT1010 if MEDIA_SUBDRV_AUTOSELECT -- cgit v1.1 From ae1f8453e828c18cf5291aeab53081dca6906f6e Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Sat, 8 Feb 2014 04:03:57 -0300 Subject: [media] rtl28xxu: use muxed RTL2832 I2C adapters for E4000 and RTL2832_SDR RTL2832 driver provides muxed I2C adapters for tuner bus I2C gate control. Pass those adapters to rtl2832_sdr and e4000 modules in order to get rid of proprietary DVB .i2c_gate_ctrl() callback use. Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/dvb-usb-v2/rtl28xxu.c | 10 ++++++++-- drivers/media/usb/dvb-usb-v2/rtl28xxu.h | 1 + 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/media/usb/dvb-usb-v2/rtl28xxu.c b/drivers/media/usb/dvb-usb-v2/rtl28xxu.c index f51949e..c83c16c 100644 --- a/drivers/media/usb/dvb-usb-v2/rtl28xxu.c +++ b/drivers/media/usb/dvb-usb-v2/rtl28xxu.c @@ -774,6 +774,9 @@ static int rtl2832u_frontend_attach(struct dvb_usb_adapter *adap) goto err; } + /* RTL2832 I2C repeater */ + priv->demod_i2c_adapter = rtl2832_get_i2c_adapter(adap->fe[0]); + /* set fe callback */ adap->fe[0]->callback = rtl2832u_frontend_callback; @@ -922,6 +925,8 @@ static int rtl2832u_tuner_attach(struct dvb_usb_adapter *adap) break; case TUNER_RTL2832_E4000: { struct v4l2_subdev *sd; + struct i2c_adapter *i2c_adap_internal = + rtl2832_get_private_i2c_adapter(adap->fe[0]); struct e4000_config e4000_config = { .fe = adap->fe[0], .clock = 28800000, @@ -932,7 +937,7 @@ static int rtl2832u_tuner_attach(struct dvb_usb_adapter *adap) info.platform_data = &e4000_config; request_module(info.type); - client = i2c_new_device(&d->i2c_adap, &info); + client = i2c_new_device(priv->demod_i2c_adapter, &info); if (client == NULL || client->dev.driver == NULL) break; @@ -943,10 +948,11 @@ static int rtl2832u_tuner_attach(struct dvb_usb_adapter *adap) priv->client = client; sd = i2c_get_clientdata(client); + i2c_set_adapdata(i2c_adap_internal, d); /* attach SDR */ dvb_attach(rtl2832_sdr_attach, adap->fe[0], - &d->i2c_adap, + i2c_adap_internal, &rtl28xxu_rtl2832_e4000_config, sd); } break; diff --git a/drivers/media/usb/dvb-usb-v2/rtl28xxu.h b/drivers/media/usb/dvb-usb-v2/rtl28xxu.h index 367aca1..a26cab1 100644 --- a/drivers/media/usb/dvb-usb-v2/rtl28xxu.h +++ b/drivers/media/usb/dvb-usb-v2/rtl28xxu.h @@ -55,6 +55,7 @@ struct rtl28xxu_priv { u8 tuner; char *tuner_name; u8 page; /* integrated demod active register page */ + struct i2c_adapter *demod_i2c_adapter; bool rc_active; struct i2c_client *client; }; -- cgit v1.1 From 1c73fc6bb542859a7f37bfc2d34f21da8a51bd30 Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Sat, 8 Feb 2014 04:21:10 -0300 Subject: [media] e4000: get rid of DVB i2c_gate_ctrl() Gate control is now implemented by rtl2832 I2C adapter so we do not need proprietary DVB i2c_gate_ctrl() anymore. Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- drivers/media/tuners/e4000.c | 103 +++++++++---------------------------------- 1 file changed, 21 insertions(+), 82 deletions(-) diff --git a/drivers/media/tuners/e4000.c b/drivers/media/tuners/e4000.c index ed2f635..29f73f6 100644 --- a/drivers/media/tuners/e4000.c +++ b/drivers/media/tuners/e4000.c @@ -119,9 +119,6 @@ static int e4000_init(struct dvb_frontend *fe) dev_dbg(&priv->client->dev, "%s:\n", __func__); - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 1); - /* dummy I2C to ensure I2C wakes up */ ret = e4000_wr_reg(priv, 0x02, 0x40); @@ -178,17 +175,11 @@ static int e4000_init(struct dvb_frontend *fe) if (ret < 0) goto err; - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 0); - priv->active = true; - - return 0; err: - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 0); + if (ret) + dev_dbg(&priv->client->dev, "%s: failed=%d\n", __func__, ret); - dev_dbg(&priv->client->dev, "%s: failed=%d\n", __func__, ret); return ret; } @@ -201,22 +192,13 @@ static int e4000_sleep(struct dvb_frontend *fe) priv->active = false; - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 1); - ret = e4000_wr_reg(priv, 0x00, 0x00); if (ret < 0) goto err; - - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 0); - - return 0; err: - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 0); + if (ret) + dev_dbg(&priv->client->dev, "%s: failed=%d\n", __func__, ret); - dev_dbg(&priv->client->dev, "%s: failed=%d\n", __func__, ret); return ret; } @@ -233,9 +215,6 @@ static int e4000_set_params(struct dvb_frontend *fe) __func__, c->delivery_system, c->frequency, c->bandwidth_hz); - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 1); - /* gain control manual */ ret = e4000_wr_reg(priv, 0x1a, 0x00); if (ret < 0) @@ -361,16 +340,10 @@ static int e4000_set_params(struct dvb_frontend *fe) ret = e4000_wr_reg(priv, 0x1a, 0x17); if (ret < 0) goto err; - - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 0); - - return 0; err: - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 0); + if (ret) + dev_dbg(&priv->client->dev, "%s: failed=%d\n", __func__, ret); - dev_dbg(&priv->client->dev, "%s: failed=%d\n", __func__, ret); return ret; } @@ -390,14 +363,12 @@ static int e4000_set_lna_gain(struct dvb_frontend *fe) struct e4000_priv *priv = fe->tuner_priv; int ret; u8 u8tmp; + dev_dbg(&priv->client->dev, "%s: lna auto=%d->%d val=%d->%d\n", __func__, priv->lna_gain_auto->cur.val, priv->lna_gain_auto->val, priv->lna_gain->cur.val, priv->lna_gain->val); - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 1); - if (priv->lna_gain_auto->val && priv->if_gain_auto->cur.val) u8tmp = 0x17; else if (priv->lna_gain_auto->val) @@ -416,16 +387,10 @@ static int e4000_set_lna_gain(struct dvb_frontend *fe) if (ret) goto err; } - - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 0); - - return 0; err: - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 0); + if (ret) + dev_dbg(&priv->client->dev, "%s: failed=%d\n", __func__, ret); - dev_dbg(&priv->client->dev, "%s: failed=%d\n", __func__, ret); return ret; } @@ -434,14 +399,12 @@ static int e4000_set_mixer_gain(struct dvb_frontend *fe) struct e4000_priv *priv = fe->tuner_priv; int ret; u8 u8tmp; + dev_dbg(&priv->client->dev, "%s: mixer auto=%d->%d val=%d->%d\n", __func__, priv->mixer_gain_auto->cur.val, priv->mixer_gain_auto->val, priv->mixer_gain->cur.val, priv->mixer_gain->val); - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 1); - if (priv->mixer_gain_auto->val) u8tmp = 0x15; else @@ -456,16 +419,10 @@ static int e4000_set_mixer_gain(struct dvb_frontend *fe) if (ret) goto err; } - - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 0); - - return 0; err: - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 0); + if (ret) + dev_dbg(&priv->client->dev, "%s: failed=%d\n", __func__, ret); - dev_dbg(&priv->client->dev, "%s: failed=%d\n", __func__, ret); return ret; } @@ -475,14 +432,12 @@ static int e4000_set_if_gain(struct dvb_frontend *fe) int ret; u8 buf[2]; u8 u8tmp; + dev_dbg(&priv->client->dev, "%s: if auto=%d->%d val=%d->%d\n", __func__, priv->if_gain_auto->cur.val, priv->if_gain_auto->val, priv->if_gain->cur.val, priv->if_gain->val); - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 1); - if (priv->if_gain_auto->val && priv->lna_gain_auto->cur.val) u8tmp = 0x17; else if (priv->lna_gain_auto->cur.val) @@ -503,16 +458,10 @@ static int e4000_set_if_gain(struct dvb_frontend *fe) if (ret) goto err; } - - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 0); - - return 0; err: - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 0); + if (ret) + dev_dbg(&priv->client->dev, "%s: failed=%d\n", __func__, ret); - dev_dbg(&priv->client->dev, "%s: failed=%d\n", __func__, ret); return ret; } @@ -525,18 +474,12 @@ static int e4000_pll_lock(struct dvb_frontend *fe) if (priv->active == false) return 0; - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 1); - ret = e4000_rd_reg(priv, 0x07, &u8tmp); if (ret) goto err; priv->pll_lock->val = (u8tmp & 0x01); err: - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 0); - if (ret) dev_dbg(&priv->client->dev, "%s: failed=%d\n", __func__, ret); @@ -567,6 +510,7 @@ static int e4000_s_ctrl(struct v4l2_ctrl *ctrl) struct dvb_frontend *fe = priv->fe; struct dtv_frontend_properties *c = &fe->dtv_property_cache; int ret; + dev_dbg(&priv->client->dev, "%s: id=%d name=%s val=%d min=%d max=%d step=%d\n", __func__, ctrl->id, ctrl->name, ctrl->val, @@ -629,9 +573,6 @@ static int e4000_probe(struct i2c_client *client, int ret; u8 chip_id; - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 1); - priv = kzalloc(sizeof(struct e4000_priv), GFP_KERNEL); if (!priv) { ret = -ENOMEM; @@ -705,16 +646,13 @@ static int e4000_probe(struct i2c_client *client, v4l2_set_subdevdata(&priv->sd, client); i2c_set_clientdata(client, &priv->sd); - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 0); - return 0; err: - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 0); + if (ret) { + dev_dbg(&client->dev, "%s: failed=%d\n", __func__, ret); + kfree(priv); + } - dev_dbg(&client->dev, "%s: failed=%d\n", __func__, ret); - kfree(priv); return ret; } @@ -725,6 +663,7 @@ static int e4000_remove(struct i2c_client *client) struct dvb_frontend *fe = priv->fe; dev_dbg(&client->dev, "%s:\n", __func__); + v4l2_ctrl_handler_free(&priv->hdl); memset(&fe->ops.tuner_ops, 0, sizeof(struct dvb_tuner_ops)); fe->tuner_priv = NULL; -- cgit v1.1 From bd428bbc7527d4ea195712598c1c252ebb4554ae Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Sat, 8 Feb 2014 06:20:35 -0300 Subject: [media] e4000: convert to Regmap API That comes possible after driver was converted to kernel I2C model (I2C binding & proper I2C client with no gate control hack). All nasty low level I2C routines are now covered by regmap. Cc: Hans Verkuil Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- drivers/media/tuners/Kconfig | 1 + drivers/media/tuners/e4000.c | 212 ++++++++++++-------------------------- drivers/media/tuners/e4000_priv.h | 2 + 3 files changed, 68 insertions(+), 147 deletions(-) diff --git a/drivers/media/tuners/Kconfig b/drivers/media/tuners/Kconfig index 3b95392..85c0d96 100644 --- a/drivers/media/tuners/Kconfig +++ b/drivers/media/tuners/Kconfig @@ -204,6 +204,7 @@ config MEDIA_TUNER_TDA18212 config MEDIA_TUNER_E4000 tristate "Elonics E4000 silicon tuner" depends on MEDIA_SUPPORT && I2C && VIDEO_V4L2 + select REGMAP_I2C default m if !MEDIA_SUBDRV_AUTOSELECT help Elonics E4000 silicon tuner driver. diff --git a/drivers/media/tuners/e4000.c b/drivers/media/tuners/e4000.c index 29f73f6..f382b90 100644 --- a/drivers/media/tuners/e4000.c +++ b/drivers/media/tuners/e4000.c @@ -21,97 +21,6 @@ #include "e4000_priv.h" #include -/* Max transfer size done by I2C transfer functions */ -#define MAX_XFER_SIZE 64 - -/* write multiple registers */ -static int e4000_wr_regs(struct e4000_priv *priv, u8 reg, u8 *val, int len) -{ - int ret; - u8 buf[MAX_XFER_SIZE]; - struct i2c_msg msg[1] = { - { - .addr = priv->client->addr, - .flags = 0, - .len = 1 + len, - .buf = buf, - } - }; - - if (1 + len > sizeof(buf)) { - dev_warn(&priv->client->dev, - "%s: i2c wr reg=%04x: len=%d is too big!\n", - KBUILD_MODNAME, reg, len); - return -EINVAL; - } - - buf[0] = reg; - memcpy(&buf[1], val, len); - - ret = i2c_transfer(priv->client->adapter, msg, 1); - if (ret == 1) { - ret = 0; - } else { - dev_warn(&priv->client->dev, - "%s: i2c wr failed=%d reg=%02x len=%d\n", - KBUILD_MODNAME, ret, reg, len); - ret = -EREMOTEIO; - } - return ret; -} - -/* read multiple registers */ -static int e4000_rd_regs(struct e4000_priv *priv, u8 reg, u8 *val, int len) -{ - int ret; - u8 buf[MAX_XFER_SIZE]; - struct i2c_msg msg[2] = { - { - .addr = priv->client->addr, - .flags = 0, - .len = 1, - .buf = ®, - }, { - .addr = priv->client->addr, - .flags = I2C_M_RD, - .len = len, - .buf = buf, - } - }; - - if (len > sizeof(buf)) { - dev_warn(&priv->client->dev, - "%s: i2c rd reg=%04x: len=%d is too big!\n", - KBUILD_MODNAME, reg, len); - return -EINVAL; - } - - ret = i2c_transfer(priv->client->adapter, msg, 2); - if (ret == 2) { - memcpy(val, buf, len); - ret = 0; - } else { - dev_warn(&priv->client->dev, - "%s: i2c rd failed=%d reg=%02x len=%d\n", - KBUILD_MODNAME, ret, reg, len); - ret = -EREMOTEIO; - } - - return ret; -} - -/* write single register */ -static int e4000_wr_reg(struct e4000_priv *priv, u8 reg, u8 val) -{ - return e4000_wr_regs(priv, reg, &val, 1); -} - -/* read single register */ -static int e4000_rd_reg(struct e4000_priv *priv, u8 reg, u8 *val) -{ - return e4000_rd_regs(priv, reg, val, 1); -} - static int e4000_init(struct dvb_frontend *fe) { struct e4000_priv *priv = fe->tuner_priv; @@ -120,58 +29,58 @@ static int e4000_init(struct dvb_frontend *fe) dev_dbg(&priv->client->dev, "%s:\n", __func__); /* dummy I2C to ensure I2C wakes up */ - ret = e4000_wr_reg(priv, 0x02, 0x40); + ret = regmap_write(priv->regmap, 0x02, 0x40); /* reset */ - ret = e4000_wr_reg(priv, 0x00, 0x01); + ret = regmap_write(priv->regmap, 0x00, 0x01); if (ret < 0) goto err; /* disable output clock */ - ret = e4000_wr_reg(priv, 0x06, 0x00); + ret = regmap_write(priv->regmap, 0x06, 0x00); if (ret < 0) goto err; - ret = e4000_wr_reg(priv, 0x7a, 0x96); + ret = regmap_write(priv->regmap, 0x7a, 0x96); if (ret < 0) goto err; /* configure gains */ - ret = e4000_wr_regs(priv, 0x7e, "\x01\xfe", 2); + ret = regmap_bulk_write(priv->regmap, 0x7e, "\x01\xfe", 2); if (ret < 0) goto err; - ret = e4000_wr_reg(priv, 0x82, 0x00); + ret = regmap_write(priv->regmap, 0x82, 0x00); if (ret < 0) goto err; - ret = e4000_wr_reg(priv, 0x24, 0x05); + ret = regmap_write(priv->regmap, 0x24, 0x05); if (ret < 0) goto err; - ret = e4000_wr_regs(priv, 0x87, "\x20\x01", 2); + ret = regmap_bulk_write(priv->regmap, 0x87, "\x20\x01", 2); if (ret < 0) goto err; - ret = e4000_wr_regs(priv, 0x9f, "\x7f\x07", 2); + ret = regmap_bulk_write(priv->regmap, 0x9f, "\x7f\x07", 2); if (ret < 0) goto err; /* DC offset control */ - ret = e4000_wr_reg(priv, 0x2d, 0x1f); + ret = regmap_write(priv->regmap, 0x2d, 0x1f); if (ret < 0) goto err; - ret = e4000_wr_regs(priv, 0x70, "\x01\x01", 2); + ret = regmap_bulk_write(priv->regmap, 0x70, "\x01\x01", 2); if (ret < 0) goto err; /* gain control */ - ret = e4000_wr_reg(priv, 0x1a, 0x17); + ret = regmap_write(priv->regmap, 0x1a, 0x17); if (ret < 0) goto err; - ret = e4000_wr_reg(priv, 0x1f, 0x1a); + ret = regmap_write(priv->regmap, 0x1f, 0x1a); if (ret < 0) goto err; @@ -192,7 +101,7 @@ static int e4000_sleep(struct dvb_frontend *fe) priv->active = false; - ret = e4000_wr_reg(priv, 0x00, 0x00); + ret = regmap_write(priv->regmap, 0x00, 0x00); if (ret < 0) goto err; err: @@ -216,7 +125,7 @@ static int e4000_set_params(struct dvb_frontend *fe) c->bandwidth_hz); /* gain control manual */ - ret = e4000_wr_reg(priv, 0x1a, 0x00); + ret = regmap_write(priv->regmap, 0x1a, 0x00); if (ret < 0) goto err; @@ -243,7 +152,7 @@ static int e4000_set_params(struct dvb_frontend *fe) "%s: f_vco=%llu pll div=%d sigma_delta=%04x\n", __func__, f_vco, buf[0], sigma_delta); - ret = e4000_wr_regs(priv, 0x09, buf, 5); + ret = regmap_bulk_write(priv->regmap, 0x09, buf, 5); if (ret < 0) goto err; @@ -258,7 +167,7 @@ static int e4000_set_params(struct dvb_frontend *fe) goto err; } - ret = e4000_wr_reg(priv, 0x10, e400_lna_filter_lut[i].val); + ret = regmap_write(priv->regmap, 0x10, e400_lna_filter_lut[i].val); if (ret < 0) goto err; @@ -276,7 +185,7 @@ static int e4000_set_params(struct dvb_frontend *fe) buf[0] = e4000_if_filter_lut[i].reg11_val; buf[1] = e4000_if_filter_lut[i].reg12_val; - ret = e4000_wr_regs(priv, 0x11, buf, 2); + ret = regmap_bulk_write(priv->regmap, 0x11, buf, 2); if (ret < 0) goto err; @@ -291,33 +200,33 @@ static int e4000_set_params(struct dvb_frontend *fe) goto err; } - ret = e4000_wr_reg(priv, 0x07, e4000_band_lut[i].reg07_val); + ret = regmap_write(priv->regmap, 0x07, e4000_band_lut[i].reg07_val); if (ret < 0) goto err; - ret = e4000_wr_reg(priv, 0x78, e4000_band_lut[i].reg78_val); + ret = regmap_write(priv->regmap, 0x78, e4000_band_lut[i].reg78_val); if (ret < 0) goto err; /* DC offset */ for (i = 0; i < 4; i++) { if (i == 0) - ret = e4000_wr_regs(priv, 0x15, "\x00\x7e\x24", 3); + ret = regmap_bulk_write(priv->regmap, 0x15, "\x00\x7e\x24", 3); else if (i == 1) - ret = e4000_wr_regs(priv, 0x15, "\x00\x7f", 2); + ret = regmap_bulk_write(priv->regmap, 0x15, "\x00\x7f", 2); else if (i == 2) - ret = e4000_wr_regs(priv, 0x15, "\x01", 1); + ret = regmap_bulk_write(priv->regmap, 0x15, "\x01", 1); else - ret = e4000_wr_regs(priv, 0x16, "\x7e", 1); + ret = regmap_bulk_write(priv->regmap, 0x16, "\x7e", 1); if (ret < 0) goto err; - ret = e4000_wr_reg(priv, 0x29, 0x01); + ret = regmap_write(priv->regmap, 0x29, 0x01); if (ret < 0) goto err; - ret = e4000_rd_regs(priv, 0x2a, buf, 3); + ret = regmap_bulk_read(priv->regmap, 0x2a, buf, 3); if (ret < 0) goto err; @@ -328,16 +237,16 @@ static int e4000_set_params(struct dvb_frontend *fe) swap(q_data[2], q_data[3]); swap(i_data[2], i_data[3]); - ret = e4000_wr_regs(priv, 0x50, q_data, 4); + ret = regmap_bulk_write(priv->regmap, 0x50, q_data, 4); if (ret < 0) goto err; - ret = e4000_wr_regs(priv, 0x60, i_data, 4); + ret = regmap_bulk_write(priv->regmap, 0x60, i_data, 4); if (ret < 0) goto err; /* gain control auto */ - ret = e4000_wr_reg(priv, 0x1a, 0x17); + ret = regmap_write(priv->regmap, 0x1a, 0x17); if (ret < 0) goto err; err: @@ -378,12 +287,12 @@ static int e4000_set_lna_gain(struct dvb_frontend *fe) else u8tmp = 0x10; - ret = e4000_wr_reg(priv, 0x1a, u8tmp); + ret = regmap_write(priv->regmap, 0x1a, u8tmp); if (ret) goto err; if (priv->lna_gain_auto->val == false) { - ret = e4000_wr_reg(priv, 0x14, priv->lna_gain->val); + ret = regmap_write(priv->regmap, 0x14, priv->lna_gain->val); if (ret) goto err; } @@ -410,12 +319,12 @@ static int e4000_set_mixer_gain(struct dvb_frontend *fe) else u8tmp = 0x14; - ret = e4000_wr_reg(priv, 0x20, u8tmp); + ret = regmap_write(priv->regmap, 0x20, u8tmp); if (ret) goto err; if (priv->mixer_gain_auto->val == false) { - ret = e4000_wr_reg(priv, 0x15, priv->mixer_gain->val); + ret = regmap_write(priv->regmap, 0x15, priv->mixer_gain->val); if (ret) goto err; } @@ -447,14 +356,14 @@ static int e4000_set_if_gain(struct dvb_frontend *fe) else u8tmp = 0x10; - ret = e4000_wr_reg(priv, 0x1a, u8tmp); + ret = regmap_write(priv->regmap, 0x1a, u8tmp); if (ret) goto err; if (priv->if_gain_auto->val == false) { buf[0] = e4000_if_gain_lut[priv->if_gain->val].reg16_val; buf[1] = e4000_if_gain_lut[priv->if_gain->val].reg17_val; - ret = e4000_wr_regs(priv, 0x16, buf, 2); + ret = regmap_bulk_write(priv->regmap, 0x16, buf, 2); if (ret) goto err; } @@ -469,16 +378,13 @@ static int e4000_pll_lock(struct dvb_frontend *fe) { struct e4000_priv *priv = fe->tuner_priv; int ret; - u8 u8tmp; + unsigned int utmp; - if (priv->active == false) - return 0; - - ret = e4000_rd_reg(priv, 0x07, &u8tmp); - if (ret) + ret = regmap_read(priv->regmap, 0x07, &utmp); + if (ret < 0) goto err; - priv->pll_lock->val = (u8tmp & 0x01); + priv->pll_lock->val = (utmp & 0x01); err: if (ret) dev_dbg(&priv->client->dev, "%s: failed=%d\n", __func__, ret); @@ -488,15 +394,19 @@ err: static int e4000_g_volatile_ctrl(struct v4l2_ctrl *ctrl) { - struct e4000_priv *priv = - container_of(ctrl->handler, struct e4000_priv, hdl); + struct e4000_priv *priv = container_of(ctrl->handler, struct e4000_priv, hdl); int ret; + if (priv->active == false) + return 0; + switch (ctrl->id) { case V4L2_CID_RF_TUNER_PLL_LOCK: ret = e4000_pll_lock(priv->fe); break; default: + dev_dbg(&priv->client->dev, "%s: unknown ctrl: id=%d name=%s\n", + __func__, ctrl->id, ctrl->name); ret = -EINVAL; } @@ -505,16 +415,13 @@ static int e4000_g_volatile_ctrl(struct v4l2_ctrl *ctrl) static int e4000_s_ctrl(struct v4l2_ctrl *ctrl) { - struct e4000_priv *priv = - container_of(ctrl->handler, struct e4000_priv, hdl); + struct e4000_priv *priv = container_of(ctrl->handler, struct e4000_priv, hdl); struct dvb_frontend *fe = priv->fe; struct dtv_frontend_properties *c = &fe->dtv_property_cache; int ret; - dev_dbg(&priv->client->dev, - "%s: id=%d name=%s val=%d min=%d max=%d step=%d\n", - __func__, ctrl->id, ctrl->name, ctrl->val, - ctrl->minimum, ctrl->maximum, ctrl->step); + if (priv->active == false) + return 0; switch (ctrl->id) { case V4L2_CID_RF_TUNER_BANDWIDTH_AUTO: @@ -535,6 +442,8 @@ static int e4000_s_ctrl(struct v4l2_ctrl *ctrl) ret = e4000_set_if_gain(priv->fe); break; default: + dev_dbg(&priv->client->dev, "%s: unknown ctrl: id=%d name=%s\n", + __func__, ctrl->id, ctrl->name); ret = -EINVAL; } @@ -571,7 +480,12 @@ static int e4000_probe(struct i2c_client *client, struct dvb_frontend *fe = cfg->fe; struct e4000_priv *priv; int ret; - u8 chip_id; + unsigned int utmp; + static const struct regmap_config regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .max_register = 0xff, + }; priv = kzalloc(sizeof(struct e4000_priv), GFP_KERNEL); if (!priv) { @@ -583,22 +497,26 @@ static int e4000_probe(struct i2c_client *client, priv->clock = cfg->clock; priv->client = client; priv->fe = cfg->fe; + priv->regmap = devm_regmap_init_i2c(client, ®map_config); + if (IS_ERR(priv->regmap)) { + ret = PTR_ERR(priv->regmap); + goto err; + } /* check if the tuner is there */ - ret = e4000_rd_reg(priv, 0x02, &chip_id); + ret = regmap_read(priv->regmap, 0x02, &utmp); if (ret < 0) goto err; - dev_dbg(&priv->client->dev, - "%s: chip_id=%02x\n", __func__, chip_id); + dev_dbg(&priv->client->dev, "%s: chip id=%02x\n", __func__, utmp); - if (chip_id != 0x40) { + if (utmp != 0x40) { ret = -ENODEV; goto err; } /* put sleep as chip seems to be in normal mode by default */ - ret = e4000_wr_reg(priv, 0x00, 0x00); + ret = regmap_write(priv->regmap, 0x00, 0x00); if (ret < 0) goto err; diff --git a/drivers/media/tuners/e4000_priv.h b/drivers/media/tuners/e4000_priv.h index 3ddd980..e772b00 100644 --- a/drivers/media/tuners/e4000_priv.h +++ b/drivers/media/tuners/e4000_priv.h @@ -24,9 +24,11 @@ #include "e4000.h" #include #include +#include struct e4000_priv { struct i2c_client *client; + struct regmap *regmap; u32 clock; struct dvb_frontend *fe; struct v4l2_subdev sd; -- cgit v1.1 From c5f51b15829d5e5dc65a9628cf4fbdcfd97636bf Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Mon, 10 Feb 2014 22:52:51 -0300 Subject: [media] e4000: rename some variables Rename some variables. Change error status checks from (ret < 0) to (ret). No actual functionality changes. Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- drivers/media/tuners/e4000.c | 332 +++++++++++++++++++------------------- drivers/media/tuners/e4000_priv.h | 2 +- 2 files changed, 167 insertions(+), 167 deletions(-) diff --git a/drivers/media/tuners/e4000.c b/drivers/media/tuners/e4000.c index f382b90..3b52550 100644 --- a/drivers/media/tuners/e4000.c +++ b/drivers/media/tuners/e4000.c @@ -23,110 +23,110 @@ static int e4000_init(struct dvb_frontend *fe) { - struct e4000_priv *priv = fe->tuner_priv; + struct e4000 *s = fe->tuner_priv; int ret; - dev_dbg(&priv->client->dev, "%s:\n", __func__); + dev_dbg(&s->client->dev, "%s:\n", __func__); /* dummy I2C to ensure I2C wakes up */ - ret = regmap_write(priv->regmap, 0x02, 0x40); + ret = regmap_write(s->regmap, 0x02, 0x40); /* reset */ - ret = regmap_write(priv->regmap, 0x00, 0x01); - if (ret < 0) + ret = regmap_write(s->regmap, 0x00, 0x01); + if (ret) goto err; /* disable output clock */ - ret = regmap_write(priv->regmap, 0x06, 0x00); - if (ret < 0) + ret = regmap_write(s->regmap, 0x06, 0x00); + if (ret) goto err; - ret = regmap_write(priv->regmap, 0x7a, 0x96); - if (ret < 0) + ret = regmap_write(s->regmap, 0x7a, 0x96); + if (ret) goto err; /* configure gains */ - ret = regmap_bulk_write(priv->regmap, 0x7e, "\x01\xfe", 2); - if (ret < 0) + ret = regmap_bulk_write(s->regmap, 0x7e, "\x01\xfe", 2); + if (ret) goto err; - ret = regmap_write(priv->regmap, 0x82, 0x00); - if (ret < 0) + ret = regmap_write(s->regmap, 0x82, 0x00); + if (ret) goto err; - ret = regmap_write(priv->regmap, 0x24, 0x05); - if (ret < 0) + ret = regmap_write(s->regmap, 0x24, 0x05); + if (ret) goto err; - ret = regmap_bulk_write(priv->regmap, 0x87, "\x20\x01", 2); - if (ret < 0) + ret = regmap_bulk_write(s->regmap, 0x87, "\x20\x01", 2); + if (ret) goto err; - ret = regmap_bulk_write(priv->regmap, 0x9f, "\x7f\x07", 2); - if (ret < 0) + ret = regmap_bulk_write(s->regmap, 0x9f, "\x7f\x07", 2); + if (ret) goto err; /* DC offset control */ - ret = regmap_write(priv->regmap, 0x2d, 0x1f); - if (ret < 0) + ret = regmap_write(s->regmap, 0x2d, 0x1f); + if (ret) goto err; - ret = regmap_bulk_write(priv->regmap, 0x70, "\x01\x01", 2); - if (ret < 0) + ret = regmap_bulk_write(s->regmap, 0x70, "\x01\x01", 2); + if (ret) goto err; /* gain control */ - ret = regmap_write(priv->regmap, 0x1a, 0x17); - if (ret < 0) + ret = regmap_write(s->regmap, 0x1a, 0x17); + if (ret) goto err; - ret = regmap_write(priv->regmap, 0x1f, 0x1a); - if (ret < 0) + ret = regmap_write(s->regmap, 0x1f, 0x1a); + if (ret) goto err; - priv->active = true; + s->active = true; err: if (ret) - dev_dbg(&priv->client->dev, "%s: failed=%d\n", __func__, ret); + dev_dbg(&s->client->dev, "%s: failed=%d\n", __func__, ret); return ret; } static int e4000_sleep(struct dvb_frontend *fe) { - struct e4000_priv *priv = fe->tuner_priv; + struct e4000 *s = fe->tuner_priv; int ret; - dev_dbg(&priv->client->dev, "%s:\n", __func__); + dev_dbg(&s->client->dev, "%s:\n", __func__); - priv->active = false; + s->active = false; - ret = regmap_write(priv->regmap, 0x00, 0x00); - if (ret < 0) + ret = regmap_write(s->regmap, 0x00, 0x00); + if (ret) goto err; err: if (ret) - dev_dbg(&priv->client->dev, "%s: failed=%d\n", __func__, ret); + dev_dbg(&s->client->dev, "%s: failed=%d\n", __func__, ret); return ret; } static int e4000_set_params(struct dvb_frontend *fe) { - struct e4000_priv *priv = fe->tuner_priv; + struct e4000 *s = fe->tuner_priv; struct dtv_frontend_properties *c = &fe->dtv_property_cache; int ret, i, sigma_delta; u64 f_vco; u8 buf[5], i_data[4], q_data[4]; - dev_dbg(&priv->client->dev, + dev_dbg(&s->client->dev, "%s: delivery_system=%d frequency=%u bandwidth_hz=%u\n", __func__, c->delivery_system, c->frequency, c->bandwidth_hz); /* gain control manual */ - ret = regmap_write(priv->regmap, 0x1a, 0x00); - if (ret < 0) + ret = regmap_write(s->regmap, 0x1a, 0x00); + if (ret) goto err; /* PLL */ @@ -141,19 +141,19 @@ static int e4000_set_params(struct dvb_frontend *fe) } f_vco = 1ull * c->frequency * e4000_pll_lut[i].mul; - sigma_delta = div_u64(0x10000ULL * (f_vco % priv->clock), priv->clock); - buf[0] = div_u64(f_vco, priv->clock); + sigma_delta = div_u64(0x10000ULL * (f_vco % s->clock), s->clock); + buf[0] = div_u64(f_vco, s->clock); buf[1] = (sigma_delta >> 0) & 0xff; buf[2] = (sigma_delta >> 8) & 0xff; buf[3] = 0x00; buf[4] = e4000_pll_lut[i].div; - dev_dbg(&priv->client->dev, + dev_dbg(&s->client->dev, "%s: f_vco=%llu pll div=%d sigma_delta=%04x\n", __func__, f_vco, buf[0], sigma_delta); - ret = regmap_bulk_write(priv->regmap, 0x09, buf, 5); - if (ret < 0) + ret = regmap_bulk_write(s->regmap, 0x09, buf, 5); + if (ret) goto err; /* LNA filter (RF filter) */ @@ -167,8 +167,8 @@ static int e4000_set_params(struct dvb_frontend *fe) goto err; } - ret = regmap_write(priv->regmap, 0x10, e400_lna_filter_lut[i].val); - if (ret < 0) + ret = regmap_write(s->regmap, 0x10, e400_lna_filter_lut[i].val); + if (ret) goto err; /* IF filters */ @@ -185,8 +185,8 @@ static int e4000_set_params(struct dvb_frontend *fe) buf[0] = e4000_if_filter_lut[i].reg11_val; buf[1] = e4000_if_filter_lut[i].reg12_val; - ret = regmap_bulk_write(priv->regmap, 0x11, buf, 2); - if (ret < 0) + ret = regmap_bulk_write(s->regmap, 0x11, buf, 2); + if (ret) goto err; /* frequency band */ @@ -200,34 +200,34 @@ static int e4000_set_params(struct dvb_frontend *fe) goto err; } - ret = regmap_write(priv->regmap, 0x07, e4000_band_lut[i].reg07_val); - if (ret < 0) + ret = regmap_write(s->regmap, 0x07, e4000_band_lut[i].reg07_val); + if (ret) goto err; - ret = regmap_write(priv->regmap, 0x78, e4000_band_lut[i].reg78_val); - if (ret < 0) + ret = regmap_write(s->regmap, 0x78, e4000_band_lut[i].reg78_val); + if (ret) goto err; /* DC offset */ for (i = 0; i < 4; i++) { if (i == 0) - ret = regmap_bulk_write(priv->regmap, 0x15, "\x00\x7e\x24", 3); + ret = regmap_bulk_write(s->regmap, 0x15, "\x00\x7e\x24", 3); else if (i == 1) - ret = regmap_bulk_write(priv->regmap, 0x15, "\x00\x7f", 2); + ret = regmap_bulk_write(s->regmap, 0x15, "\x00\x7f", 2); else if (i == 2) - ret = regmap_bulk_write(priv->regmap, 0x15, "\x01", 1); + ret = regmap_bulk_write(s->regmap, 0x15, "\x01", 1); else - ret = regmap_bulk_write(priv->regmap, 0x16, "\x7e", 1); + ret = regmap_bulk_write(s->regmap, 0x16, "\x7e", 1); - if (ret < 0) + if (ret) goto err; - ret = regmap_write(priv->regmap, 0x29, 0x01); - if (ret < 0) + ret = regmap_write(s->regmap, 0x29, 0x01); + if (ret) goto err; - ret = regmap_bulk_read(priv->regmap, 0x2a, buf, 3); - if (ret < 0) + ret = regmap_bulk_read(s->regmap, 0x2a, buf, 3); + if (ret) goto err; i_data[i] = (((buf[2] >> 0) & 0x3) << 6) | (buf[0] & 0x3f); @@ -237,30 +237,30 @@ static int e4000_set_params(struct dvb_frontend *fe) swap(q_data[2], q_data[3]); swap(i_data[2], i_data[3]); - ret = regmap_bulk_write(priv->regmap, 0x50, q_data, 4); - if (ret < 0) + ret = regmap_bulk_write(s->regmap, 0x50, q_data, 4); + if (ret) goto err; - ret = regmap_bulk_write(priv->regmap, 0x60, i_data, 4); - if (ret < 0) + ret = regmap_bulk_write(s->regmap, 0x60, i_data, 4); + if (ret) goto err; /* gain control auto */ - ret = regmap_write(priv->regmap, 0x1a, 0x17); - if (ret < 0) + ret = regmap_write(s->regmap, 0x1a, 0x17); + if (ret) goto err; err: if (ret) - dev_dbg(&priv->client->dev, "%s: failed=%d\n", __func__, ret); + dev_dbg(&s->client->dev, "%s: failed=%d\n", __func__, ret); return ret; } static int e4000_get_if_frequency(struct dvb_frontend *fe, u32 *frequency) { - struct e4000_priv *priv = fe->tuner_priv; + struct e4000 *s = fe->tuner_priv; - dev_dbg(&priv->client->dev, "%s:\n", __func__); + dev_dbg(&s->client->dev, "%s:\n", __func__); *frequency = 0; /* Zero-IF */ @@ -269,143 +269,143 @@ static int e4000_get_if_frequency(struct dvb_frontend *fe, u32 *frequency) static int e4000_set_lna_gain(struct dvb_frontend *fe) { - struct e4000_priv *priv = fe->tuner_priv; + struct e4000 *s = fe->tuner_priv; int ret; u8 u8tmp; - dev_dbg(&priv->client->dev, "%s: lna auto=%d->%d val=%d->%d\n", - __func__, priv->lna_gain_auto->cur.val, - priv->lna_gain_auto->val, priv->lna_gain->cur.val, - priv->lna_gain->val); + dev_dbg(&s->client->dev, "%s: lna auto=%d->%d val=%d->%d\n", + __func__, s->lna_gain_auto->cur.val, + s->lna_gain_auto->val, s->lna_gain->cur.val, + s->lna_gain->val); - if (priv->lna_gain_auto->val && priv->if_gain_auto->cur.val) + if (s->lna_gain_auto->val && s->if_gain_auto->cur.val) u8tmp = 0x17; - else if (priv->lna_gain_auto->val) + else if (s->lna_gain_auto->val) u8tmp = 0x19; - else if (priv->if_gain_auto->cur.val) + else if (s->if_gain_auto->cur.val) u8tmp = 0x16; else u8tmp = 0x10; - ret = regmap_write(priv->regmap, 0x1a, u8tmp); + ret = regmap_write(s->regmap, 0x1a, u8tmp); if (ret) goto err; - if (priv->lna_gain_auto->val == false) { - ret = regmap_write(priv->regmap, 0x14, priv->lna_gain->val); + if (s->lna_gain_auto->val == false) { + ret = regmap_write(s->regmap, 0x14, s->lna_gain->val); if (ret) goto err; } err: if (ret) - dev_dbg(&priv->client->dev, "%s: failed=%d\n", __func__, ret); + dev_dbg(&s->client->dev, "%s: failed=%d\n", __func__, ret); return ret; } static int e4000_set_mixer_gain(struct dvb_frontend *fe) { - struct e4000_priv *priv = fe->tuner_priv; + struct e4000 *s = fe->tuner_priv; int ret; u8 u8tmp; - dev_dbg(&priv->client->dev, "%s: mixer auto=%d->%d val=%d->%d\n", - __func__, priv->mixer_gain_auto->cur.val, - priv->mixer_gain_auto->val, priv->mixer_gain->cur.val, - priv->mixer_gain->val); + dev_dbg(&s->client->dev, "%s: mixer auto=%d->%d val=%d->%d\n", + __func__, s->mixer_gain_auto->cur.val, + s->mixer_gain_auto->val, s->mixer_gain->cur.val, + s->mixer_gain->val); - if (priv->mixer_gain_auto->val) + if (s->mixer_gain_auto->val) u8tmp = 0x15; else u8tmp = 0x14; - ret = regmap_write(priv->regmap, 0x20, u8tmp); + ret = regmap_write(s->regmap, 0x20, u8tmp); if (ret) goto err; - if (priv->mixer_gain_auto->val == false) { - ret = regmap_write(priv->regmap, 0x15, priv->mixer_gain->val); + if (s->mixer_gain_auto->val == false) { + ret = regmap_write(s->regmap, 0x15, s->mixer_gain->val); if (ret) goto err; } err: if (ret) - dev_dbg(&priv->client->dev, "%s: failed=%d\n", __func__, ret); + dev_dbg(&s->client->dev, "%s: failed=%d\n", __func__, ret); return ret; } static int e4000_set_if_gain(struct dvb_frontend *fe) { - struct e4000_priv *priv = fe->tuner_priv; + struct e4000 *s = fe->tuner_priv; int ret; u8 buf[2]; u8 u8tmp; - dev_dbg(&priv->client->dev, "%s: if auto=%d->%d val=%d->%d\n", - __func__, priv->if_gain_auto->cur.val, - priv->if_gain_auto->val, priv->if_gain->cur.val, - priv->if_gain->val); + dev_dbg(&s->client->dev, "%s: if auto=%d->%d val=%d->%d\n", + __func__, s->if_gain_auto->cur.val, + s->if_gain_auto->val, s->if_gain->cur.val, + s->if_gain->val); - if (priv->if_gain_auto->val && priv->lna_gain_auto->cur.val) + if (s->if_gain_auto->val && s->lna_gain_auto->cur.val) u8tmp = 0x17; - else if (priv->lna_gain_auto->cur.val) + else if (s->lna_gain_auto->cur.val) u8tmp = 0x19; - else if (priv->if_gain_auto->val) + else if (s->if_gain_auto->val) u8tmp = 0x16; else u8tmp = 0x10; - ret = regmap_write(priv->regmap, 0x1a, u8tmp); + ret = regmap_write(s->regmap, 0x1a, u8tmp); if (ret) goto err; - if (priv->if_gain_auto->val == false) { - buf[0] = e4000_if_gain_lut[priv->if_gain->val].reg16_val; - buf[1] = e4000_if_gain_lut[priv->if_gain->val].reg17_val; - ret = regmap_bulk_write(priv->regmap, 0x16, buf, 2); + if (s->if_gain_auto->val == false) { + buf[0] = e4000_if_gain_lut[s->if_gain->val].reg16_val; + buf[1] = e4000_if_gain_lut[s->if_gain->val].reg17_val; + ret = regmap_bulk_write(s->regmap, 0x16, buf, 2); if (ret) goto err; } err: if (ret) - dev_dbg(&priv->client->dev, "%s: failed=%d\n", __func__, ret); + dev_dbg(&s->client->dev, "%s: failed=%d\n", __func__, ret); return ret; } static int e4000_pll_lock(struct dvb_frontend *fe) { - struct e4000_priv *priv = fe->tuner_priv; + struct e4000 *s = fe->tuner_priv; int ret; unsigned int utmp; - ret = regmap_read(priv->regmap, 0x07, &utmp); - if (ret < 0) + ret = regmap_read(s->regmap, 0x07, &utmp); + if (ret) goto err; - priv->pll_lock->val = (utmp & 0x01); + s->pll_lock->val = (utmp & 0x01); err: if (ret) - dev_dbg(&priv->client->dev, "%s: failed=%d\n", __func__, ret); + dev_dbg(&s->client->dev, "%s: failed=%d\n", __func__, ret); return ret; } static int e4000_g_volatile_ctrl(struct v4l2_ctrl *ctrl) { - struct e4000_priv *priv = container_of(ctrl->handler, struct e4000_priv, hdl); + struct e4000 *s = container_of(ctrl->handler, struct e4000, hdl); int ret; - if (priv->active == false) + if (s->active == false) return 0; switch (ctrl->id) { case V4L2_CID_RF_TUNER_PLL_LOCK: - ret = e4000_pll_lock(priv->fe); + ret = e4000_pll_lock(s->fe); break; default: - dev_dbg(&priv->client->dev, "%s: unknown ctrl: id=%d name=%s\n", + dev_dbg(&s->client->dev, "%s: unknown ctrl: id=%d name=%s\n", __func__, ctrl->id, ctrl->name); ret = -EINVAL; } @@ -415,34 +415,34 @@ static int e4000_g_volatile_ctrl(struct v4l2_ctrl *ctrl) static int e4000_s_ctrl(struct v4l2_ctrl *ctrl) { - struct e4000_priv *priv = container_of(ctrl->handler, struct e4000_priv, hdl); - struct dvb_frontend *fe = priv->fe; + struct e4000 *s = container_of(ctrl->handler, struct e4000, hdl); + struct dvb_frontend *fe = s->fe; struct dtv_frontend_properties *c = &fe->dtv_property_cache; int ret; - if (priv->active == false) + if (s->active == false) return 0; switch (ctrl->id) { case V4L2_CID_RF_TUNER_BANDWIDTH_AUTO: case V4L2_CID_RF_TUNER_BANDWIDTH: - c->bandwidth_hz = priv->bandwidth->val; - ret = e4000_set_params(priv->fe); + c->bandwidth_hz = s->bandwidth->val; + ret = e4000_set_params(s->fe); break; case V4L2_CID_RF_TUNER_LNA_GAIN_AUTO: case V4L2_CID_RF_TUNER_LNA_GAIN: - ret = e4000_set_lna_gain(priv->fe); + ret = e4000_set_lna_gain(s->fe); break; case V4L2_CID_RF_TUNER_MIXER_GAIN_AUTO: case V4L2_CID_RF_TUNER_MIXER_GAIN: - ret = e4000_set_mixer_gain(priv->fe); + ret = e4000_set_mixer_gain(s->fe); break; case V4L2_CID_RF_TUNER_IF_GAIN_AUTO: case V4L2_CID_RF_TUNER_IF_GAIN: - ret = e4000_set_if_gain(priv->fe); + ret = e4000_set_if_gain(s->fe); break; default: - dev_dbg(&priv->client->dev, "%s: unknown ctrl: id=%d name=%s\n", + dev_dbg(&s->client->dev, "%s: unknown ctrl: id=%d name=%s\n", __func__, ctrl->id, ctrl->name); ret = -EINVAL; } @@ -478,7 +478,7 @@ static int e4000_probe(struct i2c_client *client, { struct e4000_config *cfg = client->dev.platform_data; struct dvb_frontend *fe = cfg->fe; - struct e4000_priv *priv; + struct e4000 *s; int ret; unsigned int utmp; static const struct regmap_config regmap_config = { @@ -487,28 +487,28 @@ static int e4000_probe(struct i2c_client *client, .max_register = 0xff, }; - priv = kzalloc(sizeof(struct e4000_priv), GFP_KERNEL); - if (!priv) { + s = kzalloc(sizeof(struct e4000), GFP_KERNEL); + if (!s) { ret = -ENOMEM; dev_err(&client->dev, "%s: kzalloc() failed\n", KBUILD_MODNAME); goto err; } - priv->clock = cfg->clock; - priv->client = client; - priv->fe = cfg->fe; - priv->regmap = devm_regmap_init_i2c(client, ®map_config); - if (IS_ERR(priv->regmap)) { - ret = PTR_ERR(priv->regmap); + s->clock = cfg->clock; + s->client = client; + s->fe = cfg->fe; + s->regmap = devm_regmap_init_i2c(client, ®map_config); + if (IS_ERR(s->regmap)) { + ret = PTR_ERR(s->regmap); goto err; } /* check if the tuner is there */ - ret = regmap_read(priv->regmap, 0x02, &utmp); - if (ret < 0) + ret = regmap_read(s->regmap, 0x02, &utmp); + if (ret) goto err; - dev_dbg(&priv->client->dev, "%s: chip id=%02x\n", __func__, utmp); + dev_dbg(&s->client->dev, "%s: chip id=%02x\n", __func__, utmp); if (utmp != 0x40) { ret = -ENODEV; @@ -516,59 +516,59 @@ static int e4000_probe(struct i2c_client *client, } /* put sleep as chip seems to be in normal mode by default */ - ret = regmap_write(priv->regmap, 0x00, 0x00); - if (ret < 0) + ret = regmap_write(s->regmap, 0x00, 0x00); + if (ret) goto err; /* Register controls */ - v4l2_ctrl_handler_init(&priv->hdl, 9); - priv->bandwidth_auto = v4l2_ctrl_new_std(&priv->hdl, &e4000_ctrl_ops, + v4l2_ctrl_handler_init(&s->hdl, 9); + s->bandwidth_auto = v4l2_ctrl_new_std(&s->hdl, &e4000_ctrl_ops, V4L2_CID_RF_TUNER_BANDWIDTH_AUTO, 0, 1, 1, 1); - priv->bandwidth = v4l2_ctrl_new_std(&priv->hdl, &e4000_ctrl_ops, + s->bandwidth = v4l2_ctrl_new_std(&s->hdl, &e4000_ctrl_ops, V4L2_CID_RF_TUNER_BANDWIDTH, 4300000, 11000000, 100000, 4300000); - v4l2_ctrl_auto_cluster(2, &priv->bandwidth_auto, 0, false); - priv->lna_gain_auto = v4l2_ctrl_new_std(&priv->hdl, &e4000_ctrl_ops, + v4l2_ctrl_auto_cluster(2, &s->bandwidth_auto, 0, false); + s->lna_gain_auto = v4l2_ctrl_new_std(&s->hdl, &e4000_ctrl_ops, V4L2_CID_RF_TUNER_LNA_GAIN_AUTO, 0, 1, 1, 1); - priv->lna_gain = v4l2_ctrl_new_std(&priv->hdl, &e4000_ctrl_ops, + s->lna_gain = v4l2_ctrl_new_std(&s->hdl, &e4000_ctrl_ops, V4L2_CID_RF_TUNER_LNA_GAIN, 0, 15, 1, 10); - v4l2_ctrl_auto_cluster(2, &priv->lna_gain_auto, 0, false); - priv->mixer_gain_auto = v4l2_ctrl_new_std(&priv->hdl, &e4000_ctrl_ops, + v4l2_ctrl_auto_cluster(2, &s->lna_gain_auto, 0, false); + s->mixer_gain_auto = v4l2_ctrl_new_std(&s->hdl, &e4000_ctrl_ops, V4L2_CID_RF_TUNER_MIXER_GAIN_AUTO, 0, 1, 1, 1); - priv->mixer_gain = v4l2_ctrl_new_std(&priv->hdl, &e4000_ctrl_ops, + s->mixer_gain = v4l2_ctrl_new_std(&s->hdl, &e4000_ctrl_ops, V4L2_CID_RF_TUNER_MIXER_GAIN, 0, 1, 1, 1); - v4l2_ctrl_auto_cluster(2, &priv->mixer_gain_auto, 0, false); - priv->if_gain_auto = v4l2_ctrl_new_std(&priv->hdl, &e4000_ctrl_ops, + v4l2_ctrl_auto_cluster(2, &s->mixer_gain_auto, 0, false); + s->if_gain_auto = v4l2_ctrl_new_std(&s->hdl, &e4000_ctrl_ops, V4L2_CID_RF_TUNER_IF_GAIN_AUTO, 0, 1, 1, 1); - priv->if_gain = v4l2_ctrl_new_std(&priv->hdl, &e4000_ctrl_ops, + s->if_gain = v4l2_ctrl_new_std(&s->hdl, &e4000_ctrl_ops, V4L2_CID_RF_TUNER_IF_GAIN, 0, 54, 1, 0); - v4l2_ctrl_auto_cluster(2, &priv->if_gain_auto, 0, false); - priv->pll_lock = v4l2_ctrl_new_std(&priv->hdl, &e4000_ctrl_ops, + v4l2_ctrl_auto_cluster(2, &s->if_gain_auto, 0, false); + s->pll_lock = v4l2_ctrl_new_std(&s->hdl, &e4000_ctrl_ops, V4L2_CID_RF_TUNER_PLL_LOCK, 0, 1, 1, 0); - if (priv->hdl.error) { - ret = priv->hdl.error; - dev_err(&priv->client->dev, "Could not initialize controls\n"); - v4l2_ctrl_handler_free(&priv->hdl); + if (s->hdl.error) { + ret = s->hdl.error; + dev_err(&s->client->dev, "Could not initialize controls\n"); + v4l2_ctrl_handler_free(&s->hdl); goto err; } - priv->sd.ctrl_handler = &priv->hdl; + s->sd.ctrl_handler = &s->hdl; - dev_info(&priv->client->dev, + dev_info(&s->client->dev, "%s: Elonics E4000 successfully identified\n", KBUILD_MODNAME); - fe->tuner_priv = priv; + fe->tuner_priv = s; memcpy(&fe->ops.tuner_ops, &e4000_tuner_ops, sizeof(struct dvb_tuner_ops)); - v4l2_set_subdevdata(&priv->sd, client); - i2c_set_clientdata(client, &priv->sd); + v4l2_set_subdevdata(&s->sd, client); + i2c_set_clientdata(client, &s->sd); return 0; err: if (ret) { dev_dbg(&client->dev, "%s: failed=%d\n", __func__, ret); - kfree(priv); + kfree(s); } return ret; @@ -577,15 +577,15 @@ err: static int e4000_remove(struct i2c_client *client) { struct v4l2_subdev *sd = i2c_get_clientdata(client); - struct e4000_priv *priv = container_of(sd, struct e4000_priv, sd); - struct dvb_frontend *fe = priv->fe; + struct e4000 *s = container_of(sd, struct e4000, sd); + struct dvb_frontend *fe = s->fe; dev_dbg(&client->dev, "%s:\n", __func__); - v4l2_ctrl_handler_free(&priv->hdl); + v4l2_ctrl_handler_free(&s->hdl); memset(&fe->ops.tuner_ops, 0, sizeof(struct dvb_tuner_ops)); fe->tuner_priv = NULL; - kfree(priv); + kfree(s); return 0; } diff --git a/drivers/media/tuners/e4000_priv.h b/drivers/media/tuners/e4000_priv.h index e772b00..cb00704 100644 --- a/drivers/media/tuners/e4000_priv.h +++ b/drivers/media/tuners/e4000_priv.h @@ -26,7 +26,7 @@ #include #include -struct e4000_priv { +struct e4000 { struct i2c_client *client; struct regmap *regmap; u32 clock; -- cgit v1.1 From bc9087549ea9f57c400013d08d311c7cd4892132 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Wed, 5 Mar 2014 20:21:38 -0300 Subject: [media] rtl2832_sdr: fixing v4l2-compliance issues Fix rtl2832_sdr driver v4l2-compliance issues. Signed-off-by: Hans Verkuil Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- drivers/staging/media/rtl2832u_sdr/rtl2832_sdr.c | 29 +++++++++++++++++++----- 1 file changed, 23 insertions(+), 6 deletions(-) diff --git a/drivers/staging/media/rtl2832u_sdr/rtl2832_sdr.c b/drivers/staging/media/rtl2832u_sdr/rtl2832_sdr.c index 7e20576..141fc8b 100644 --- a/drivers/staging/media/rtl2832u_sdr/rtl2832_sdr.c +++ b/drivers/staging/media/rtl2832u_sdr/rtl2832_sdr.c @@ -118,6 +118,7 @@ struct rtl2832_sdr_state { struct vb2_queue vb_queue; struct list_head queued_bufs; spinlock_t queued_bufs_lock; /* Protects queued_bufs */ + unsigned sequence; /* buffer sequence counter */ /* Note if taking both locks v4l2_lock must always be locked first! */ struct mutex v4l2_lock; /* Protects everything else */ @@ -413,6 +414,8 @@ static void rtl2832_sdr_urb_complete(struct urb *urb) len = rtl2832_sdr_convert_stream(s, ptr, urb->transfer_buffer, urb->actual_length); vb2_set_plane_payload(&fbuf->vb, 0, len); + v4l2_get_timestamp(&fbuf->vb.v4l2_buf.timestamp); + fbuf->vb.v4l2_buf.sequence = s->sequence++; vb2_buffer_done(&fbuf->vb, VB2_BUF_STATE_DONE); } skip: @@ -609,8 +612,9 @@ static int rtl2832_sdr_queue_setup(struct vb2_queue *vq, struct rtl2832_sdr_state *s = vb2_get_drv_priv(vq); dev_dbg(&s->udev->dev, "%s: *nbuffers=%d\n", __func__, *nbuffers); - /* Absolute min and max number of buffers available for mmap() */ - *nbuffers = clamp_t(unsigned int, *nbuffers, 8, 32); + /* Need at least 8 buffers */ + if (vq->num_buffers + *nbuffers < 8) + *nbuffers = 8 - vq->num_buffers; *nplanes = 1; /* 2 = max 16-bit sample returned */ sizes[0] = PAGE_ALIGN(BULK_BUFFER_SIZE * 2); @@ -1011,6 +1015,8 @@ static int rtl2832_sdr_start_streaming(struct vb2_queue *vq, unsigned int count) if (ret) goto err; + s->sequence = 0; + ret = rtl2832_sdr_submit_urbs(s); if (ret) goto err; @@ -1088,6 +1094,8 @@ static int rtl2832_sdr_s_tuner(struct file *file, void *priv, struct rtl2832_sdr_state *s = video_drvdata(file); dev_dbg(&s->udev->dev, "%s:\n", __func__); + if (v->index > 1) + return -EINVAL; return 0; } @@ -1123,12 +1131,15 @@ static int rtl2832_sdr_g_frequency(struct file *file, void *priv, dev_dbg(&s->udev->dev, "%s: tuner=%d type=%d\n", __func__, f->tuner, f->type); - if (f->tuner == 0) + if (f->tuner == 0) { f->frequency = s->f_adc; - else if (f->tuner == 1) + f->type = V4L2_TUNER_ADC; + } else if (f->tuner == 1) { f->frequency = s->f_tuner; - else + f->type = V4L2_TUNER_RF; + } else { return -EINVAL; + } return ret; } @@ -1162,7 +1173,9 @@ static int rtl2832_sdr_s_frequency(struct file *file, void *priv, __func__, s->f_adc); ret = rtl2832_sdr_set_adc(s); } else if (f->tuner == 1) { - s->f_tuner = f->frequency; + s->f_tuner = clamp_t(unsigned int, f->frequency, + bands_fm[0].rangelow, + bands_fm[0].rangehigh); dev_dbg(&s->udev->dev, "%s: RF frequency=%u Hz\n", __func__, f->frequency); @@ -1196,6 +1209,7 @@ static int rtl2832_sdr_g_fmt_sdr_cap(struct file *file, void *priv, dev_dbg(&s->udev->dev, "%s:\n", __func__); f->fmt.sdr.pixelformat = s->pixelformat; + memset(f->fmt.sdr.reserved, 0, sizeof(f->fmt.sdr.reserved)); return 0; } @@ -1212,6 +1226,7 @@ static int rtl2832_sdr_s_fmt_sdr_cap(struct file *file, void *priv, if (vb2_is_busy(q)) return -EBUSY; + memset(f->fmt.sdr.reserved, 0, sizeof(f->fmt.sdr.reserved)); for (i = 0; i < NUM_FORMATS; i++) { if (formats[i].pixelformat == f->fmt.sdr.pixelformat) { s->pixelformat = f->fmt.sdr.pixelformat; @@ -1233,6 +1248,7 @@ static int rtl2832_sdr_try_fmt_sdr_cap(struct file *file, void *priv, dev_dbg(&s->udev->dev, "%s: pixelformat fourcc %4.4s\n", __func__, (char *)&f->fmt.sdr.pixelformat); + memset(f->fmt.sdr.reserved, 0, sizeof(f->fmt.sdr.reserved)); for (i = 0; i < NUM_FORMATS; i++) { if (formats[i].pixelformat == f->fmt.sdr.pixelformat) return 0; @@ -1363,6 +1379,7 @@ struct dvb_frontend *rtl2832_sdr_attach(struct dvb_frontend *fe, s->i2c = i2c; s->cfg = cfg; s->f_adc = bands_adc[0].rangelow; + s->f_tuner = bands_fm[0].rangelow; s->pixelformat = V4L2_SDR_FMT_CU8; mutex_init(&s->v4l2_lock); -- cgit v1.1 From ea4d04f92c97c7986dfc363655f9c4143d35c2b9 Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Mon, 10 Mar 2014 14:28:45 -0300 Subject: [media] rtl2832_sdr: clamp bandwidth to nearest legal value in automode Clamp bandwidth to nearest legal value in automode in order to pass v4l2-compliance test. Reported-by: Hans Verkuil Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- drivers/staging/media/rtl2832u_sdr/rtl2832_sdr.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/staging/media/rtl2832u_sdr/rtl2832_sdr.c b/drivers/staging/media/rtl2832u_sdr/rtl2832_sdr.c index 141fc8b..b09f7d8 100644 --- a/drivers/staging/media/rtl2832u_sdr/rtl2832_sdr.c +++ b/drivers/staging/media/rtl2832u_sdr/rtl2832_sdr.c @@ -1322,8 +1322,16 @@ static int rtl2832_sdr_s_ctrl(struct v4l2_ctrl *ctrl) switch (ctrl->id) { case V4L2_CID_RF_TUNER_BANDWIDTH_AUTO: case V4L2_CID_RF_TUNER_BANDWIDTH: - if (s->bandwidth_auto->val) - s->bandwidth->val = s->f_adc; + /* TODO: these controls should be moved to tuner drivers */ + if (s->bandwidth_auto->val) { + /* Round towards the closest legal value */ + s32 val = s->f_adc + s->bandwidth->step / 2; + u32 offset; + val = clamp(val, s->bandwidth->minimum, s->bandwidth->maximum); + offset = val - s->bandwidth->minimum; + offset = s->bandwidth->step * (offset / s->bandwidth->step); + s->bandwidth->val = s->bandwidth->minimum + offset; + } c->bandwidth_hz = s->bandwidth->val; -- cgit v1.1 From ba6e6f6e5032679b08158eda86cf3fce456dc1ec Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Mon, 3 Feb 2014 00:00:32 -0300 Subject: [media] MAINTAINERS: add rtl2832_sdr driver Realtek RTL2832 SDR driver. Currently in staging as SDR API is not ready. Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- MAINTAINERS | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 3718c32..94c9cff 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -7351,6 +7351,16 @@ T: git git://linuxtv.org/anttip/media_tree.git S: Maintained F: drivers/media/dvb-frontends/rtl2832* +RTL2832_SDR MEDIA DRIVER +M: Antti Palosaari +L: linux-media@vger.kernel.org +W: http://linuxtv.org/ +W: http://palosaari.fi/linux/ +Q: http://patchwork.linuxtv.org/project/linux-media/list/ +T: git git://linuxtv.org/anttip/media_tree.git +S: Maintained +F: drivers/staging/media/rtl2832u_sdr/rtl2832_sdr* + RTL8180 WIRELESS DRIVER M: "John W. Linville" L: linux-wireless@vger.kernel.org -- cgit v1.1 From 17fd60fd503d3e7ae095ed75f5a1f1ed1a5d31c1 Mon Sep 17 00:00:00 2001 From: "Lad, Prabhakar" Date: Fri, 14 Mar 2014 02:25:35 -0300 Subject: [media] media: davinci: vpbe: fix build warning this patch fixes following build warning drivers/media/platform/davinci/vpbe_display.c: In function 'vpbe_start_streaming': drivers/media/platform/davinci/vpbe_display.c:344: warning: unused variable 'vpbe_dev' Signed-off-by: Lad, Prabhakar Acked-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/platform/davinci/vpbe_display.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/media/platform/davinci/vpbe_display.c b/drivers/media/platform/davinci/vpbe_display.c index 7a0e40e..b4f12d0 100644 --- a/drivers/media/platform/davinci/vpbe_display.c +++ b/drivers/media/platform/davinci/vpbe_display.c @@ -341,7 +341,6 @@ static int vpbe_start_streaming(struct vb2_queue *vq, unsigned int count) { struct vpbe_fh *fh = vb2_get_drv_priv(vq); struct vpbe_layer *layer = fh->layer; - struct vpbe_device *vpbe_dev = fh->disp_dev->vpbe_dev; int ret; /* Get the next frame from the buffer queue */ -- cgit v1.1 From 54ece68d89110f598546d3a2d10cbbbc70cb5055 Mon Sep 17 00:00:00 2001 From: James Hogan Date: Thu, 13 Mar 2014 07:29:21 -0300 Subject: [media] rc: img-ir: hw: Remove unnecessary semi-colon Fix a coccicheck warning in img-ir driver: drivers/media/rc/img-ir/img-ir-hw.c:500:2-3: Unneeded semicolon Signed-off-by: James Hogan Signed-off-by: Mauro Carvalho Chehab --- drivers/media/rc/img-ir/img-ir-hw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/rc/img-ir/img-ir-hw.c b/drivers/media/rc/img-ir/img-ir-hw.c index cbbfd7d..2abf78a 100644 --- a/drivers/media/rc/img-ir/img-ir-hw.c +++ b/drivers/media/rc/img-ir/img-ir-hw.c @@ -497,7 +497,7 @@ set_unlock: break; default: ret = -EINVAL; - }; + } unlock: spin_unlock_irq(&priv->lock); -- cgit v1.1 From 32df34d875bbfeda023485f7693c6fe1cd7946c3 Mon Sep 17 00:00:00 2001 From: James Hogan Date: Thu, 13 Mar 2014 07:29:23 -0300 Subject: [media] rc: img-ir: jvc: Remove unused no-leader timings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The JVC timings included timings intended for the secondary decoder (which matches messages with no leader), however they were in the wrong part of the timings structure, repeating s00 and s01 rather than being in s10 and s11. Distinct repeat timings can't be properly supported yet for JVC anyway since the scancode callback cannot determine which decoder matched the message, so for now remove these timings and don't bother to enable the secondary decoder. This fixes the following warnings with W=1: drivers/media/rc/img-ir/img-ir-jvc.c +76 :3: warning: initialized field overwritten [-Woverride-init] drivers/media/rc/img-ir/img-ir-jvc.c +76 :3: warning: (near initialization for ‘img_ir_jvc.timings.s00’) [-Woverride-init] drivers/media/rc/img-ir/img-ir-jvc.c +81 :3: warning: initialized field overwritten [-Woverride-init] drivers/media/rc/img-ir/img-ir-jvc.c +81 :3: warning: (near initialization for ‘img_ir_jvc.timings.s01’) [-Woverride-init] Reported-by: Mauro Carvalho Chehab Signed-off-by: James Hogan Signed-off-by: Mauro Carvalho Chehab --- drivers/media/rc/img-ir/img-ir-jvc.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/drivers/media/rc/img-ir/img-ir-jvc.c b/drivers/media/rc/img-ir/img-ir-jvc.c index ae55867..10209d2 100644 --- a/drivers/media/rc/img-ir/img-ir-jvc.c +++ b/drivers/media/rc/img-ir/img-ir-jvc.c @@ -49,7 +49,6 @@ struct img_ir_decoder img_ir_jvc = { .control = { .decoden = 1, .code_type = IMG_IR_CODETYPE_PULSEDIST, - .decodend2 = 1, }, /* main timings */ .unit = 527500, /* 527.5 us */ @@ -69,16 +68,6 @@ struct img_ir_decoder img_ir_jvc = { .pulse = { 1 /* 527.5 us +-60 us */ }, .space = { 3 /* 1.5825 ms +-40 us */ }, }, - /* 0 symbol (no leader) */ - .s00 = { - .pulse = { 1 /* 527.5 us +-60 us */ }, - .space = { 1 /* 527.5 us */ }, - }, - /* 1 symbol (no leader) */ - .s01 = { - .pulse = { 1 /* 527.5 us +-60 us */ }, - .space = { 3 /* 1.5825 ms +-40 us */ }, - }, /* free time */ .ft = { .minlen = 16, -- cgit v1.1 From b9e28d1f8301d6e393b8937282f325f13fb9cf6a Mon Sep 17 00:00:00 2001 From: James Hogan Date: Thu, 13 Mar 2014 07:29:22 -0300 Subject: [media] rc: img-ir: hw: Fix min/max bits setup MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The calculated values for the minlen and maxlen fields, which were rounded to multiples of 2 and clamped to a valid range, were left unused. Use them in the calculation of the register value rather than using the raw input minlen and maxlen. This fixes the following warning with a W=1 build: drivers/media/rc/img-ir/img-ir-hw.c In function ‘img_ir_free_timing’: drivers/media/rc/img-ir/img-ir-hw.c +228 :23: warning: variable ‘maxlen’ set but not used [-Wunused-but-set-variable] drivers/media/rc/img-ir/img-ir-hw.c +228 :15: warning: variable ‘minlen’ set but not used [-Wunused-but-set-variable] Reported-by: Mauro Carvalho Chehab Signed-off-by: James Hogan Signed-off-by: Mauro Carvalho Chehab --- drivers/media/rc/img-ir/img-ir-hw.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/media/rc/img-ir/img-ir-hw.c b/drivers/media/rc/img-ir/img-ir-hw.c index 2abf78a..579a52b 100644 --- a/drivers/media/rc/img-ir/img-ir-hw.c +++ b/drivers/media/rc/img-ir/img-ir-hw.c @@ -240,9 +240,9 @@ static u32 img_ir_free_timing(const struct img_ir_free_timing *timing, ft_min = (timing->ft_min*clock_hz + 999999) / 1000000; ft_min = (ft_min + 7) >> 3; /* construct register value */ - return (timing->maxlen << IMG_IR_MAXLEN_SHIFT) | - (timing->minlen << IMG_IR_MINLEN_SHIFT) | - (ft_min << IMG_IR_FT_MIN_SHIFT); + return (maxlen << IMG_IR_MAXLEN_SHIFT) | + (minlen << IMG_IR_MINLEN_SHIFT) | + (ft_min << IMG_IR_FT_MIN_SHIFT); } /** -- cgit v1.1 From 926977e0ae75567a87d95b245eea589a8bbb8682 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Fri, 14 Mar 2014 08:38:21 -0300 Subject: [media] v4l2-pci-skeleton: add a V4L2 PCI skeleton driver This example driver uses all the latest frameworks and can serve as a starting point for a new V4L2 PCI driver. Originally written for a presentation on how to use V4L2 frameworks during FOSDEM 2014. Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- Documentation/video4linux/v4l2-framework.txt | 4 + Documentation/video4linux/v4l2-pci-skeleton.c | 913 ++++++++++++++++++++++++++ 2 files changed, 917 insertions(+) create mode 100644 Documentation/video4linux/v4l2-pci-skeleton.c diff --git a/Documentation/video4linux/v4l2-framework.txt b/Documentation/video4linux/v4l2-framework.txt index ae3a2cc..667a433 100644 --- a/Documentation/video4linux/v4l2-framework.txt +++ b/Documentation/video4linux/v4l2-framework.txt @@ -34,6 +34,10 @@ So this framework sets up the basic building blocks that all drivers need and this same framework should make it much easier to refactor common code into utility functions shared by all drivers. +A good example to look at as a reference is the v4l2-pci-skeleton.c +source that is available in this directory. It is a skeleton driver for +a PCI capture card, and demonstrates how to use the V4L2 driver +framework. It can be used as a template for real PCI video capture driver. Structure of a driver --------------------- diff --git a/Documentation/video4linux/v4l2-pci-skeleton.c b/Documentation/video4linux/v4l2-pci-skeleton.c new file mode 100644 index 0000000..3a1c0d2 --- /dev/null +++ b/Documentation/video4linux/v4l2-pci-skeleton.c @@ -0,0 +1,913 @@ +/* + * This is a V4L2 PCI Skeleton Driver. It gives an initial skeleton source + * for use with other PCI drivers. + * + * This skeleton PCI driver assumes that the card has an S-Video connector as + * input 0 and an HDMI connector as input 1. + * + * Copyright 2014 Cisco Systems, Inc. and/or its affiliates. All rights reserved. + * + * This program is free software; you may redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +MODULE_DESCRIPTION("V4L2 PCI Skeleton Driver"); +MODULE_AUTHOR("Hans Verkuil"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(pci, skeleton_pci_tbl); + +/** + * struct skeleton - All internal data for one instance of device + * @pdev: PCI device + * @v4l2_dev: top-level v4l2 device struct + * @vdev: video node structure + * @ctrl_handler: control handler structure + * @lock: ioctl serialization mutex + * @std: current SDTV standard + * @timings: current HDTV timings + * @format: current pix format + * @input: current video input (0 = SDTV, 1 = HDTV) + * @queue: vb2 video capture queue + * @alloc_ctx: vb2 contiguous DMA context + * @qlock: spinlock controlling access to buf_list and sequence + * @buf_list: list of buffers queued for DMA + * @sequence: frame sequence counter + */ +struct skeleton { + struct pci_dev *pdev; + struct v4l2_device v4l2_dev; + struct video_device vdev; + struct v4l2_ctrl_handler ctrl_handler; + struct mutex lock; + v4l2_std_id std; + struct v4l2_dv_timings timings; + struct v4l2_pix_format format; + unsigned input; + + struct vb2_queue queue; + struct vb2_alloc_ctx *alloc_ctx; + + spinlock_t qlock; + struct list_head buf_list; + unsigned int sequence; +}; + +struct skel_buffer { + struct vb2_buffer vb; + struct list_head list; +}; + +static inline struct skel_buffer *to_skel_buffer(struct vb2_buffer *vb2) +{ + return container_of(vb2, struct skel_buffer, vb); +} + +static const struct pci_device_id skeleton_pci_tbl[] = { + /* { PCI_DEVICE(PCI_VENDOR_ID_, PCI_DEVICE_ID_) }, */ + { 0, } +}; + +/* + * HDTV: this structure has the capabilities of the HDTV receiver. + * It is used to constrain the huge list of possible formats based + * upon the hardware capabilities. + */ +static const struct v4l2_dv_timings_cap skel_timings_cap = { + .type = V4L2_DV_BT_656_1120, + /* keep this initialization for compatibility with GCC < 4.4.6 */ + .reserved = { 0 }, + V4L2_INIT_BT_TIMINGS( + 720, 1920, /* min/max width */ + 480, 1080, /* min/max height */ + 27000000, 74250000, /* min/max pixelclock*/ + V4L2_DV_BT_STD_CEA861, /* Supported standards */ + /* capabilities */ + V4L2_DV_BT_CAP_INTERLACED | V4L2_DV_BT_CAP_PROGRESSIVE + ) +}; + +/* + * Supported SDTV standards. This does the same job as skel_timings_cap, but + * for standard TV formats. + */ +#define SKEL_TVNORMS V4L2_STD_ALL + +/* + * Interrupt handler: typically interrupts happen after a new frame has been + * captured. It is the job of the handler to remove the new frame from the + * internal list and give it back to the vb2 framework, updating the sequence + * counter and timestamp at the same time. + */ +static irqreturn_t skeleton_irq(int irq, void *dev_id) +{ +#ifdef TODO + struct skeleton *skel = dev_id; + + /* handle interrupt */ + + /* Once a new frame has been captured, mark it as done like this: */ + if (captured_new_frame) { + ... + spin_lock(&skel->qlock); + list_del(&new_buf->list); + spin_unlock(&skel->qlock); + new_buf->vb.v4l2_buf.sequence = skel->sequence++; + v4l2_get_timestamp(&new_buf->vb.v4l2_buf.timestamp); + vb2_buffer_done(&new_buf->vb, VB2_BUF_STATE_DONE); + } +#endif + return IRQ_HANDLED; +} + +/* + * Setup the constraints of the queue: besides setting the number of planes + * per buffer and the size and allocation context of each plane, it also + * checks if sufficient buffers have been allocated. Usually 3 is a good + * minimum number: many DMA engines need a minimum of 2 buffers in the + * queue and you need to have another available for userspace processing. + */ +static int queue_setup(struct vb2_queue *vq, const struct v4l2_format *fmt, + unsigned int *nbuffers, unsigned int *nplanes, + unsigned int sizes[], void *alloc_ctxs[]) +{ + struct skeleton *skel = vb2_get_drv_priv(vq); + + if (vq->num_buffers + *nbuffers < 3) + *nbuffers = 3 - vq->num_buffers; + + if (fmt && fmt->fmt.pix.sizeimage < skel->format.sizeimage) + return -EINVAL; + *nplanes = 1; + sizes[0] = fmt ? fmt->fmt.pix.sizeimage : skel->format.sizeimage; + alloc_ctxs[0] = skel->alloc_ctx; + return 0; +} + +/* + * Prepare the buffer for queueing to the DMA engine: check and set the + * payload size and fill in the field. Note: if the format's field is + * V4L2_FIELD_ALTERNATE, then vb->v4l2_buf.field should be set in the + * interrupt handler since that's usually where you know if the TOP or + * BOTTOM field has been captured. + */ +static int buffer_prepare(struct vb2_buffer *vb) +{ + struct skeleton *skel = vb2_get_drv_priv(vb->vb2_queue); + unsigned long size = skel->format.sizeimage; + + if (vb2_plane_size(vb, 0) < size) { + dev_err(&skel->pdev->dev, "buffer too small (%lu < %lu)\n", + vb2_plane_size(vb, 0), size); + return -EINVAL; + } + + vb2_set_plane_payload(vb, 0, size); + vb->v4l2_buf.field = skel->format.field; + return 0; +} + +/* + * Queue this buffer to the DMA engine. + */ +static void buffer_queue(struct vb2_buffer *vb) +{ + struct skeleton *skel = vb2_get_drv_priv(vb->vb2_queue); + struct skel_buffer *buf = to_skel_buffer(vb); + unsigned long flags; + + spin_lock_irqsave(&skel->qlock, flags); + list_add_tail(&buf->list, &skel->buf_list); + + /* TODO: Update any DMA pointers if necessary */ + + spin_unlock_irqrestore(&skel->qlock, flags); +} + +static void return_all_buffers(struct skeleton *skel, + enum vb2_buffer_state state) +{ + struct skel_buffer *buf, *node; + unsigned long flags; + + spin_lock_irqsave(&skel->qlock, flags); + list_for_each_entry_safe(buf, node, &skel->buf_list, list) { + vb2_buffer_done(&buf->vb, state); + list_del(&buf->list); + } + spin_unlock_irqrestore(&skel->qlock, flags); +} + +/* + * Start streaming. First check if the minimum number of buffers have been + * queued. If not, then return -ENOBUFS and the vb2 framework will call + * this function again the next time a buffer has been queued until enough + * buffers are available to actually start the DMA engine. + */ +static int start_streaming(struct vb2_queue *vq, unsigned int count) +{ + struct skeleton *skel = vb2_get_drv_priv(vq); + int ret = 0; + + skel->sequence = 0; + + /* TODO: start DMA */ + + if (ret) { + /* + * In case of an error, return all active buffers to the + * QUEUED state + */ + return_all_buffers(skel, VB2_BUF_STATE_QUEUED); + } + return ret; +} + +/* + * Stop the DMA engine. Any remaining buffers in the DMA queue are dequeued + * and passed on to the vb2 framework marked as STATE_ERROR. + */ +static int stop_streaming(struct vb2_queue *vq) +{ + struct skeleton *skel = vb2_get_drv_priv(vq); + + /* TODO: stop DMA */ + + /* Release all active buffers */ + return_all_buffers(skel, VB2_BUF_STATE_ERROR); + return 0; +} + +/* + * The vb2 queue ops. Note that since q->lock is set we can use the standard + * vb2_ops_wait_prepare/finish helper functions. If q->lock would be NULL, + * then this driver would have to provide these ops. + */ +static struct vb2_ops skel_qops = { + .queue_setup = queue_setup, + .buf_prepare = buffer_prepare, + .buf_queue = buffer_queue, + .start_streaming = start_streaming, + .stop_streaming = stop_streaming, + .wait_prepare = vb2_ops_wait_prepare, + .wait_finish = vb2_ops_wait_finish, +}; + +/* + * Required ioctl querycap. Note that the version field is prefilled with + * the version of the kernel. + */ +static int skeleton_querycap(struct file *file, void *priv, + struct v4l2_capability *cap) +{ + struct skeleton *skel = video_drvdata(file); + + strlcpy(cap->driver, KBUILD_MODNAME, sizeof(cap->driver)); + strlcpy(cap->card, "V4L2 PCI Skeleton", sizeof(cap->card)); + snprintf(cap->bus_info, sizeof(cap->bus_info), "PCI:%s", + pci_name(skel->pdev)); + cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_READWRITE | + V4L2_CAP_STREAMING; + cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS; + return 0; +} + +/* + * Helper function to check and correct struct v4l2_pix_format. It's used + * not only in VIDIOC_TRY/S_FMT, but also elsewhere if changes to the SDTV + * standard, HDTV timings or the video input would require updating the + * current format. + */ +static void skeleton_fill_pix_format(struct skeleton *skel, + struct v4l2_pix_format *pix) +{ + pix->pixelformat = V4L2_PIX_FMT_YUYV; + if (skel->input == 0) { + /* S-Video input */ + pix->width = 720; + pix->height = (skel->std & V4L2_STD_525_60) ? 480 : 576; + pix->field = V4L2_FIELD_INTERLACED; + pix->colorspace = V4L2_COLORSPACE_SMPTE170M; + } else { + /* HDMI input */ + pix->width = skel->timings.bt.width; + pix->height = skel->timings.bt.height; + if (skel->timings.bt.interlaced) + pix->field = V4L2_FIELD_INTERLACED; + else + pix->field = V4L2_FIELD_NONE; + pix->colorspace = V4L2_COLORSPACE_REC709; + } + + /* + * The YUYV format is four bytes for every two pixels, so bytesperline + * is width * 2. + */ + pix->bytesperline = pix->width * 2; + pix->sizeimage = pix->bytesperline * pix->height; + pix->priv = 0; +} + +static int skeleton_try_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct skeleton *skel = video_drvdata(file); + struct v4l2_pix_format *pix = &f->fmt.pix; + + /* + * Due to historical reasons providing try_fmt with an unsupported + * pixelformat will return -EINVAL for video receivers. Webcam drivers, + * however, will silently correct the pixelformat. Some video capture + * applications rely on this behavior... + */ + if (pix->pixelformat != V4L2_PIX_FMT_YUYV) + return -EINVAL; + skeleton_fill_pix_format(skel, pix); + return 0; +} + +static int skeleton_s_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct skeleton *skel = video_drvdata(file); + int ret; + + ret = skeleton_try_fmt_vid_cap(file, priv, f); + if (ret) + return ret; + + /* + * It is not allowed to change the format while buffers for use with + * streaming have already been allocated. + */ + if (vb2_is_busy(&skel->queue)) + return -EBUSY; + + /* TODO: change format */ + skel->format = f->fmt.pix; + return 0; +} + +static int skeleton_g_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct skeleton *skel = video_drvdata(file); + + f->fmt.pix = skel->format; + return 0; +} + +static int skeleton_enum_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_fmtdesc *f) +{ + if (f->index != 0) + return -EINVAL; + + strlcpy(f->description, "4:2:2, packed, YUYV", sizeof(f->description)); + f->pixelformat = V4L2_PIX_FMT_YUYV; + f->flags = 0; + return 0; +} + +static int skeleton_s_std(struct file *file, void *priv, v4l2_std_id std) +{ + struct skeleton *skel = video_drvdata(file); + + /* S_STD is not supported on the HDMI input */ + if (skel->input) + return -ENODATA; + + /* + * No change, so just return. Some applications call S_STD again after + * the buffers for streaming have been set up, so we have to allow for + * this behavior. + */ + if (std == skel->std) + return 0; + + /* + * Changing the standard implies a format change, which is not allowed + * while buffers for use with streaming have already been allocated. + */ + if (vb2_is_busy(&skel->queue)) + return -EBUSY; + + /* TODO: handle changing std */ + + skel->std = std; + + /* Update the internal format */ + skeleton_fill_pix_format(skel, &skel->format); + return 0; +} + +static int skeleton_g_std(struct file *file, void *priv, v4l2_std_id *std) +{ + struct skeleton *skel = video_drvdata(file); + + /* G_STD is not supported on the HDMI input */ + if (skel->input) + return -ENODATA; + + *std = skel->std; + return 0; +} + +/* + * Query the current standard as seen by the hardware. This function shall + * never actually change the standard, it just detects and reports. + * The framework will initially set *std to tvnorms (i.e. the set of + * supported standards by this input), and this function should just AND + * this value. If there is no signal, then *std should be set to 0. + */ +static int skeleton_querystd(struct file *file, void *priv, v4l2_std_id *std) +{ + struct skeleton *skel = video_drvdata(file); + + /* QUERY_STD is not supported on the HDMI input */ + if (skel->input) + return -ENODATA; + +#ifdef TODO + /* + * Query currently seen standard. Initial value of *std is + * V4L2_STD_ALL. This function should look something like this: + */ + get_signal_info(); + if (no_signal) { + *std = 0; + return 0; + } + /* Use signal information to reduce the number of possible standards */ + if (signal_has_525_lines) + *std &= V4L2_STD_525_60; + else + *std &= V4L2_STD_625_50; +#endif + return 0; +} + +static int skeleton_s_dv_timings(struct file *file, void *_fh, + struct v4l2_dv_timings *timings) +{ + struct skeleton *skel = video_drvdata(file); + + /* S_DV_TIMINGS is not supported on the S-Video input */ + if (skel->input == 0) + return -ENODATA; + + /* Quick sanity check */ + if (!v4l2_valid_dv_timings(timings, &skel_timings_cap, NULL, NULL)) + return -EINVAL; + + /* Check if the timings are part of the CEA-861 timings. */ + if (!v4l2_find_dv_timings_cap(timings, &skel_timings_cap, + 0, NULL, NULL)) + return -EINVAL; + + /* Return 0 if the new timings are the same as the current timings. */ + if (v4l2_match_dv_timings(timings, &skel->timings, 0)) + return 0; + + /* + * Changing the timings implies a format change, which is not allowed + * while buffers for use with streaming have already been allocated. + */ + if (vb2_is_busy(&skel->queue)) + return -EBUSY; + + /* TODO: Configure new timings */ + + /* Save timings */ + skel->timings = *timings; + + /* Update the internal format */ + skeleton_fill_pix_format(skel, &skel->format); + return 0; +} + +static int skeleton_g_dv_timings(struct file *file, void *_fh, + struct v4l2_dv_timings *timings) +{ + struct skeleton *skel = video_drvdata(file); + + /* G_DV_TIMINGS is not supported on the S-Video input */ + if (skel->input == 0) + return -ENODATA; + + *timings = skel->timings; + return 0; +} + +static int skeleton_enum_dv_timings(struct file *file, void *_fh, + struct v4l2_enum_dv_timings *timings) +{ + struct skeleton *skel = video_drvdata(file); + + /* ENUM_DV_TIMINGS is not supported on the S-Video input */ + if (skel->input == 0) + return -ENODATA; + + return v4l2_enum_dv_timings_cap(timings, &skel_timings_cap, + NULL, NULL); +} + +/* + * Query the current timings as seen by the hardware. This function shall + * never actually change the timings, it just detects and reports. + * If no signal is detected, then return -ENOLINK. If the hardware cannot + * lock to the signal, then return -ENOLCK. If the signal is out of range + * of the capabilities of the system (e.g., it is possible that the receiver + * can lock but that the DMA engine it is connected to cannot handle + * pixelclocks above a certain frequency), then -ERANGE is returned. + */ +static int skeleton_query_dv_timings(struct file *file, void *_fh, + struct v4l2_dv_timings *timings) +{ + struct skeleton *skel = video_drvdata(file); + + /* QUERY_DV_TIMINGS is not supported on the S-Video input */ + if (skel->input == 0) + return -ENODATA; + +#ifdef TODO + /* + * Query currently seen timings. This function should look + * something like this: + */ + detect_timings(); + if (no_signal) + return -ENOLINK; + if (cannot_lock_to_signal) + return -ENOLCK; + if (signal_out_of_range_of_capabilities) + return -ERANGE; + + /* Useful for debugging */ + v4l2_print_dv_timings(skel->v4l2_dev.name, "query_dv_timings:", + timings, true); +#endif + return 0; +} + +static int skeleton_dv_timings_cap(struct file *file, void *fh, + struct v4l2_dv_timings_cap *cap) +{ + struct skeleton *skel = video_drvdata(file); + + /* DV_TIMINGS_CAP is not supported on the S-Video input */ + if (skel->input == 0) + return -ENODATA; + *cap = skel_timings_cap; + return 0; +} + +static int skeleton_enum_input(struct file *file, void *priv, + struct v4l2_input *i) +{ + if (i->index > 1) + return -EINVAL; + + i->type = V4L2_INPUT_TYPE_CAMERA; + if (i->index == 0) { + i->std = SKEL_TVNORMS; + strlcpy(i->name, "S-Video", sizeof(i->name)); + i->capabilities = V4L2_IN_CAP_STD; + } else { + i->std = 0; + strlcpy(i->name, "HDMI", sizeof(i->name)); + i->capabilities = V4L2_IN_CAP_DV_TIMINGS; + } + return 0; +} + +static int skeleton_s_input(struct file *file, void *priv, unsigned int i) +{ + struct skeleton *skel = video_drvdata(file); + + if (i > 1) + return -EINVAL; + + /* + * Changing the input implies a format change, which is not allowed + * while buffers for use with streaming have already been allocated. + */ + if (vb2_is_busy(&skel->queue)) + return -EBUSY; + + skel->input = i; + /* + * Update tvnorms. The tvnorms value is used by the core to implement + * VIDIOC_ENUMSTD so it has to be correct. If tvnorms == 0, then + * ENUMSTD will return -ENODATA. + */ + skel->vdev.tvnorms = i ? 0 : SKEL_TVNORMS; + + /* Update the internal format */ + skeleton_fill_pix_format(skel, &skel->format); + return 0; +} + +static int skeleton_g_input(struct file *file, void *priv, unsigned int *i) +{ + struct skeleton *skel = video_drvdata(file); + + *i = skel->input; + return 0; +} + +/* The control handler. */ +static int skeleton_s_ctrl(struct v4l2_ctrl *ctrl) +{ + /*struct skeleton *skel = + container_of(ctrl->handler, struct skeleton, ctrl_handler);*/ + + switch (ctrl->id) { + case V4L2_CID_BRIGHTNESS: + /* TODO: set brightness to ctrl->val */ + break; + case V4L2_CID_CONTRAST: + /* TODO: set contrast to ctrl->val */ + break; + case V4L2_CID_SATURATION: + /* TODO: set saturation to ctrl->val */ + break; + case V4L2_CID_HUE: + /* TODO: set hue to ctrl->val */ + break; + default: + return -EINVAL; + } + return 0; +} + +/* ------------------------------------------------------------------ + File operations for the device + ------------------------------------------------------------------*/ + +static const struct v4l2_ctrl_ops skel_ctrl_ops = { + .s_ctrl = skeleton_s_ctrl, +}; + +/* + * The set of all supported ioctls. Note that all the streaming ioctls + * use the vb2 helper functions that take care of all the locking and + * that also do ownership tracking (i.e. only the filehandle that requested + * the buffers can call the streaming ioctls, all other filehandles will + * receive -EBUSY if they attempt to call the same streaming ioctls). + * + * The last three ioctls also use standard helper functions: these implement + * standard behavior for drivers with controls. + */ +static const struct v4l2_ioctl_ops skel_ioctl_ops = { + .vidioc_querycap = skeleton_querycap, + .vidioc_try_fmt_vid_cap = skeleton_try_fmt_vid_cap, + .vidioc_s_fmt_vid_cap = skeleton_s_fmt_vid_cap, + .vidioc_g_fmt_vid_cap = skeleton_g_fmt_vid_cap, + .vidioc_enum_fmt_vid_cap = skeleton_enum_fmt_vid_cap, + + .vidioc_g_std = skeleton_g_std, + .vidioc_s_std = skeleton_s_std, + .vidioc_querystd = skeleton_querystd, + + .vidioc_s_dv_timings = skeleton_s_dv_timings, + .vidioc_g_dv_timings = skeleton_g_dv_timings, + .vidioc_enum_dv_timings = skeleton_enum_dv_timings, + .vidioc_query_dv_timings = skeleton_query_dv_timings, + .vidioc_dv_timings_cap = skeleton_dv_timings_cap, + + .vidioc_enum_input = skeleton_enum_input, + .vidioc_g_input = skeleton_g_input, + .vidioc_s_input = skeleton_s_input, + + .vidioc_reqbufs = vb2_ioctl_reqbufs, + .vidioc_create_bufs = vb2_ioctl_create_bufs, + .vidioc_querybuf = vb2_ioctl_querybuf, + .vidioc_qbuf = vb2_ioctl_qbuf, + .vidioc_dqbuf = vb2_ioctl_dqbuf, + .vidioc_expbuf = vb2_ioctl_expbuf, + .vidioc_streamon = vb2_ioctl_streamon, + .vidioc_streamoff = vb2_ioctl_streamoff, + + .vidioc_log_status = v4l2_ctrl_log_status, + .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, + .vidioc_unsubscribe_event = v4l2_event_unsubscribe, +}; + +/* + * The set of file operations. Note that all these ops are standard core + * helper functions. + */ +static const struct v4l2_file_operations skel_fops = { + .owner = THIS_MODULE, + .open = v4l2_fh_open, + .release = vb2_fop_release, + .unlocked_ioctl = video_ioctl2, + .read = vb2_fop_read, + .mmap = vb2_fop_mmap, + .poll = vb2_fop_poll, +}; + +/* + * The initial setup of this device instance. Note that the initial state of + * the driver should be complete. So the initial format, standard, timings + * and video input should all be initialized to some reasonable value. + */ +static int skeleton_probe(struct pci_dev *pdev, const struct pci_device_id *ent) +{ + /* The initial timings are chosen to be 720p60. */ + static const struct v4l2_dv_timings timings_def = + V4L2_DV_BT_CEA_1280X720P60; + struct skeleton *skel; + struct video_device *vdev; + struct v4l2_ctrl_handler *hdl; + struct vb2_queue *q; + int ret; + + /* Enable PCI */ + ret = pci_enable_device(pdev); + if (ret) + return ret; + ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); + if (ret) { + dev_err(&pdev->dev, "no suitable DMA available.\n"); + goto disable_pci; + } + + /* Allocate a new instance */ + skel = devm_kzalloc(&pdev->dev, sizeof(struct skeleton), GFP_KERNEL); + if (!skel) + return -ENOMEM; + + /* Allocate the interrupt */ + ret = devm_request_irq(&pdev->dev, pdev->irq, + skeleton_irq, 0, KBUILD_MODNAME, skel); + if (ret) { + dev_err(&pdev->dev, "request_irq failed\n"); + goto disable_pci; + } + skel->pdev = pdev; + + /* Fill in the initial format-related settings */ + skel->timings = timings_def; + skel->std = V4L2_STD_625_50; + skeleton_fill_pix_format(skel, &skel->format); + + /* Initialize the top-level structure */ + ret = v4l2_device_register(&pdev->dev, &skel->v4l2_dev); + if (ret) + goto disable_pci; + + mutex_init(&skel->lock); + + /* Add the controls */ + hdl = &skel->ctrl_handler; + v4l2_ctrl_handler_init(hdl, 4); + v4l2_ctrl_new_std(hdl, &skel_ctrl_ops, + V4L2_CID_BRIGHTNESS, 0, 255, 1, 127); + v4l2_ctrl_new_std(hdl, &skel_ctrl_ops, + V4L2_CID_CONTRAST, 0, 255, 1, 16); + v4l2_ctrl_new_std(hdl, &skel_ctrl_ops, + V4L2_CID_SATURATION, 0, 255, 1, 127); + v4l2_ctrl_new_std(hdl, &skel_ctrl_ops, + V4L2_CID_HUE, -128, 127, 1, 0); + if (hdl->error) { + ret = hdl->error; + goto free_hdl; + } + skel->v4l2_dev.ctrl_handler = hdl; + + /* Initialize the vb2 queue */ + q = &skel->queue; + q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + q->io_modes = VB2_MMAP | VB2_DMABUF | VB2_READ; + q->drv_priv = skel; + q->buf_struct_size = sizeof(struct skel_buffer); + q->ops = &skel_qops; + q->mem_ops = &vb2_dma_contig_memops; + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + /* + * Assume that this DMA engine needs to have at least two buffers + * available before it can be started. The start_streaming() op + * won't be called until at least this many buffers are queued up. + */ + q->min_buffers_needed = 2; + /* + * The serialization lock for the streaming ioctls. This is the same + * as the main serialization lock, but if some of the non-streaming + * ioctls could take a long time to execute, then you might want to + * have a different lock here to prevent VIDIOC_DQBUF from being + * blocked while waiting for another action to finish. This is + * generally not needed for PCI devices, but USB devices usually do + * want a separate lock here. + */ + q->lock = &skel->lock; + /* + * Since this driver can only do 32-bit DMA we must make sure that + * the vb2 core will allocate the buffers in 32-bit DMA memory. + */ + q->gfp_flags = GFP_DMA32; + ret = vb2_queue_init(q); + if (ret) + goto free_hdl; + + skel->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev); + if (IS_ERR(skel->alloc_ctx)) { + dev_err(&pdev->dev, "Can't allocate buffer context"); + ret = PTR_ERR(skel->alloc_ctx); + goto free_hdl; + } + INIT_LIST_HEAD(&skel->buf_list); + spin_lock_init(&skel->qlock); + + /* Initialize the video_device structure */ + vdev = &skel->vdev; + strlcpy(vdev->name, KBUILD_MODNAME, sizeof(vdev->name)); + /* + * There is nothing to clean up, so release is set to an empty release + * function. The release callback must be non-NULL. + */ + vdev->release = video_device_release_empty; + vdev->fops = &skel_fops, + vdev->ioctl_ops = &skel_ioctl_ops, + /* + * The main serialization lock. All ioctls are serialized by this + * lock. Exception: if q->lock is set, then the streaming ioctls + * are serialized by that separate lock. + */ + vdev->lock = &skel->lock; + vdev->queue = q; + vdev->v4l2_dev = &skel->v4l2_dev; + /* Supported SDTV standards, if any */ + vdev->tvnorms = SKEL_TVNORMS; + /* If this bit is set, then the v4l2 core will provide the support + * for the VIDIOC_G/S_PRIORITY ioctls. This flag will eventually + * go away once all drivers have been converted to use struct v4l2_fh. + */ + set_bit(V4L2_FL_USE_FH_PRIO, &vdev->flags); + video_set_drvdata(vdev, skel); + + ret = video_register_device(vdev, VFL_TYPE_GRABBER, -1); + if (ret) + goto free_ctx; + + dev_info(&pdev->dev, "V4L2 PCI Skeleton Driver loaded\n"); + return 0; + +free_ctx: + vb2_dma_contig_cleanup_ctx(skel->alloc_ctx); +free_hdl: + v4l2_ctrl_handler_free(&skel->ctrl_handler); + v4l2_device_unregister(&skel->v4l2_dev); +disable_pci: + pci_disable_device(pdev); + return ret; +} + +static void skeleton_remove(struct pci_dev *pdev) +{ + struct v4l2_device *v4l2_dev = pci_get_drvdata(pdev); + struct skeleton *skel = container_of(v4l2_dev, struct skeleton, v4l2_dev); + + video_unregister_device(&skel->vdev); + v4l2_ctrl_handler_free(&skel->ctrl_handler); + vb2_dma_contig_cleanup_ctx(skel->alloc_ctx); + v4l2_device_unregister(&skel->v4l2_dev); + pci_disable_device(skel->pdev); +} + +static struct pci_driver skeleton_driver = { + .name = KBUILD_MODNAME, + .probe = skeleton_probe, + .remove = skeleton_remove, + .id_table = skeleton_pci_tbl, +}; + +module_pci_driver(skeleton_driver); -- cgit v1.1 From 46609297e373c74a87acbb7e9f052a3ed8a8212c Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Fri, 14 Mar 2014 08:57:07 -0300 Subject: [media] DocBook media: clarify v4l2_pix_format and v4l2_pix_format_mplane fields Be more specific with regards to how some of these fields are interpreted. In particular the height value and which fields can be set by the application. Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/v4l/pixfmt.xml | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/Documentation/DocBook/media/v4l/pixfmt.xml b/Documentation/DocBook/media/v4l/pixfmt.xml index f535d9b..ea514d60 100644 --- a/Documentation/DocBook/media/v4l/pixfmt.xml +++ b/Documentation/DocBook/media/v4l/pixfmt.xml @@ -25,7 +25,12 @@ capturing and output, for overlay frame buffer formats see also __u32 height - Image height in pixels. + Image height in pixels. If field is + one of V4L2_FIELD_TOP, V4L2_FIELD_BOTTOM + or V4L2_FIELD_ALTERNATE then height refers to the + number of lines in the field, otherwise it refers to the number of + lines in the frame (which is twice the field height for interlaced + formats). Applications set these fields to @@ -54,7 +59,7 @@ linkend="reserved-formats" /> can request to capture or output only the top or bottom field, or both fields interlaced or sequentially stored in one buffer or alternating in separate buffers. Drivers return the actual field order selected. -For details see . +For more details on fields see . __u32 @@ -81,7 +86,10 @@ plane and is divided by the same factor as the example the Cb and Cr planes of a YUV 4:2:0 image have half as many padding bytes following each line as the Y plane. To avoid ambiguities drivers must return a bytesperline value -rounded up to a multiple of the scale factor. +rounded up to a multiple of the scale factor. +For compressed formats the bytesperline +value makes no sense. Applications and drivers must set this to 0 in +that case. __u32 @@ -97,7 +105,8 @@ hold an image. &v4l2-colorspace; colorspace This information supplements the -pixelformat and must be set by the driver, +pixelformat and must be set by the driver for +capture streams and by the application for output streams, see . @@ -135,7 +144,7 @@ set this field to zero. __u16 bytesperline Distance in bytes between the leftmost pixels in two adjacent - lines. + lines. See &v4l2-pix-format;. __u16 @@ -154,12 +163,12 @@ set this field to zero. __u32 width - Image width in pixels. + Image width in pixels. See &v4l2-pix-format;. __u32 height - Image height in pixels. + Image height in pixels. See &v4l2-pix-format;. __u32 -- cgit v1.1 From 22a5ea91df52392f98ff7ff66a1dce2c07e68568 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Fri, 14 Mar 2014 08:57:06 -0300 Subject: [media] DocBook media: v4l2_format_sdr was renamed to v4l2_sdr_format Update the DocBook files accordingly. Signed-off-by: Hans Verkuil Cc: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/v4l/dev-sdr.xml | 6 +++--- Documentation/DocBook/media/v4l/vidioc-g-fmt.xml | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/Documentation/DocBook/media/v4l/dev-sdr.xml b/Documentation/DocBook/media/v4l/dev-sdr.xml index 524b9c4..dc14804 100644 --- a/Documentation/DocBook/media/v4l/dev-sdr.xml +++ b/Documentation/DocBook/media/v4l/dev-sdr.xml @@ -69,15 +69,15 @@ must be supported as well. To use the format ioctls applications set the type field of a &v4l2-format; to -V4L2_BUF_TYPE_SDR_CAPTURE and use the &v4l2-format-sdr; +V4L2_BUF_TYPE_SDR_CAPTURE and use the &v4l2-sdr-format; sdr member of the fmt union as needed per the desired operation. Currently only the pixelformat field of -&v4l2-format-sdr; is used. The content of that field is the V4L2 fourcc code +&v4l2-sdr-format; is used. The content of that field is the V4L2 fourcc code of the data format. -
+
struct <structname>v4l2_sdr_format</structname> &cs-str; diff --git a/Documentation/DocBook/media/v4l/vidioc-g-fmt.xml b/Documentation/DocBook/media/v4l/vidioc-g-fmt.xml index f43f1a9..4fe19a7a 100644 --- a/Documentation/DocBook/media/v4l/vidioc-g-fmt.xml +++ b/Documentation/DocBook/media/v4l/vidioc-g-fmt.xml @@ -172,7 +172,7 @@ capture and output devices. - &v4l2-format-sdr; + &v4l2-sdr-format; sdr Definition of a data format, see , used by SDR capture devices. -- cgit v1.1 From ba35ca07080268af1badeb47de0f9eff28126339 Mon Sep 17 00:00:00 2001 From: Frank Schaefer Date: Fri, 17 Jan 2014 14:18:43 -0300 Subject: [media] em28xx-audio: make sure audio is unmuted on open() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In all cases, when the first capture is called, we need to call the code that unmutes the volume. Signed-off-by: Frank Schäfer Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/em28xx/em28xx-audio.c | 42 +++++++++++++++++---------------- 1 file changed, 22 insertions(+), 20 deletions(-) diff --git a/drivers/media/usb/em28xx/em28xx-audio.c b/drivers/media/usb/em28xx/em28xx-audio.c index f75c0a5..c1937ea 100644 --- a/drivers/media/usb/em28xx/em28xx-audio.c +++ b/drivers/media/usb/em28xx/em28xx-audio.c @@ -273,26 +273,28 @@ static int snd_em28xx_capture_open(struct snd_pcm_substream *substream) mutex_lock(&dev->lock); runtime->hw = snd_em28xx_hw_capture; - if ((dev->alt == 0 || dev->is_audio_only) && dev->adev.users == 0) { - if (dev->is_audio_only) - /* vendor audio is on a separate interface */ - dev->alt = 1; - else - /* vendor audio is on the same interface as video */ - dev->alt = 7; - /* - * FIXME: The intention seems to be to select the alt - * setting with the largest wMaxPacketSize for the video - * endpoint. - * At least dev->alt should be used instead, but we - * should probably not touch it at all if it is - * already >0, because wMaxPacketSize of the audio - * endpoints seems to be the same for all. - */ - - dprintk("changing alternate number on interface %d to %d\n", - dev->ifnum, dev->alt); - usb_set_interface(dev->udev, dev->ifnum, dev->alt); + + if (dev->adev.users == 0) { + if (dev->alt == 0 || dev->is_audio_only) { + if (dev->is_audio_only) + /* audio is on a separate interface */ + dev->alt = 1; + else + /* audio is on the same interface as video */ + dev->alt = 7; + /* + * FIXME: The intention seems to be to select + * the alt setting with the largest + * wMaxPacketSize for the video endpoint. + * At least dev->alt should be used instead, but + * we should probably not touch it at all if it + * is already >0, because wMaxPacketSize of the + * audio endpoints seems to be the same for all. + */ + dprintk("changing alternate number on interface %d to %d\n", + dev->ifnum, dev->alt); + usb_set_interface(dev->udev, dev->ifnum, dev->alt); + } /* Sets volume, mute, etc */ dev->mute = 0; -- cgit v1.1 From ac8f392678da1d9839fdd10e3d5a0c9400b544fa Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Fri, 14 Mar 2014 15:22:24 -0300 Subject: [media] e4000: fix 32-bit build error All error/warnings: drivers/built-in.o: In function `e4000_set_params': >> e4000.c:(.text+0x1219a1b): undefined reference to `__umoddi3' Reported-by: kbuild test robot Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- drivers/media/tuners/e4000.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/media/tuners/e4000.c b/drivers/media/tuners/e4000.c index 3b52550..67ecf1b 100644 --- a/drivers/media/tuners/e4000.c +++ b/drivers/media/tuners/e4000.c @@ -116,6 +116,7 @@ static int e4000_set_params(struct dvb_frontend *fe) struct e4000 *s = fe->tuner_priv; struct dtv_frontend_properties *c = &fe->dtv_property_cache; int ret, i, sigma_delta; + unsigned int pll_n, pll_f; u64 f_vco; u8 buf[5], i_data[4], q_data[4]; @@ -141,8 +142,9 @@ static int e4000_set_params(struct dvb_frontend *fe) } f_vco = 1ull * c->frequency * e4000_pll_lut[i].mul; - sigma_delta = div_u64(0x10000ULL * (f_vco % s->clock), s->clock); - buf[0] = div_u64(f_vco, s->clock); + pll_n = div_u64_rem(f_vco, s->clock, &pll_f); + sigma_delta = div_u64(0x10000ULL * pll_f, s->clock); + buf[0] = pll_n; buf[1] = (sigma_delta >> 0) & 0xff; buf[2] = (sigma_delta >> 8) & 0xff; buf[3] = 0x00; -- cgit v1.1 From 02b7220017cf29507aa789720a3576e7dd59fbe2 Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Fri, 14 Mar 2014 16:20:40 -0300 Subject: [media] rtl2832_sdr: do not use dynamic stack allocation Do not use dynamic stack allocation. >> drivers/staging/media/rtl2832u_sdr/rtl2832_sdr.c:181:1: warning: 'rtl2832_sdr_wr' uses dynamic stack allocation [enabled by default] Reported-by: Mauro Carvalho Chehab Reported-by: kbuild test robot Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- drivers/staging/media/rtl2832u_sdr/rtl2832_sdr.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/staging/media/rtl2832u_sdr/rtl2832_sdr.c b/drivers/staging/media/rtl2832u_sdr/rtl2832_sdr.c index b09f7d8..104ee8a 100644 --- a/drivers/staging/media/rtl2832u_sdr/rtl2832_sdr.c +++ b/drivers/staging/media/rtl2832u_sdr/rtl2832_sdr.c @@ -156,7 +156,9 @@ static int rtl2832_sdr_wr(struct rtl2832_sdr_state *s, u8 reg, const u8 *val, int len) { int ret; - u8 buf[1 + len]; +#define MAX_WR_LEN 24 +#define MAX_WR_XFER_LEN (MAX_WR_LEN + 1) + u8 buf[MAX_WR_XFER_LEN]; struct i2c_msg msg[1] = { { .addr = s->cfg->i2c_addr, @@ -166,6 +168,9 @@ static int rtl2832_sdr_wr(struct rtl2832_sdr_state *s, u8 reg, const u8 *val, } }; + if (WARN_ON(len > MAX_WR_LEN)) + return -EINVAL; + buf[0] = reg; memcpy(&buf[1], val, len); -- cgit v1.1 From 040cf86c8a121905bf201f334a4848f35de29729 Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Thu, 13 Feb 2014 15:40:59 -0300 Subject: [media] af9033: implement PID filter Implement PID filter and export it via symbol. Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/af9033.c | 53 ++++++++++++++++++++++++++++++++++++ drivers/media/dvb-frontends/af9033.h | 19 +++++++++++++ 2 files changed, 72 insertions(+) diff --git a/drivers/media/dvb-frontends/af9033.c b/drivers/media/dvb-frontends/af9033.c index 65728c2..5a1c508 100644 --- a/drivers/media/dvb-frontends/af9033.c +++ b/drivers/media/dvb-frontends/af9033.c @@ -989,6 +989,59 @@ err: return ret; } +int af9033_pid_filter_ctrl(struct dvb_frontend *fe, int onoff) +{ + struct af9033_state *state = fe->demodulator_priv; + int ret; + + dev_dbg(&state->i2c->dev, "%s: onoff=%d\n", __func__, onoff); + + ret = af9033_wr_reg_mask(state, 0x80f993, onoff, 0x01); + if (ret < 0) + goto err; + + return 0; + +err: + dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); + + return ret; +} +EXPORT_SYMBOL(af9033_pid_filter_ctrl); + +int af9033_pid_filter(struct dvb_frontend *fe, int index, u16 pid, int onoff) +{ + struct af9033_state *state = fe->demodulator_priv; + int ret; + u8 wbuf[2] = {(pid >> 0) & 0xff, (pid >> 8) & 0xff}; + + dev_dbg(&state->i2c->dev, "%s: index=%d pid=%04x onoff=%d\n", + __func__, index, pid, onoff); + + if (pid > 0x1fff) + return 0; + + ret = af9033_wr_regs(state, 0x80f996, wbuf, 2); + if (ret < 0) + goto err; + + ret = af9033_wr_reg(state, 0x80f994, onoff); + if (ret < 0) + goto err; + + ret = af9033_wr_reg(state, 0x80f995, index); + if (ret < 0) + goto err; + + return 0; + +err: + dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); + + return ret; +} +EXPORT_SYMBOL(af9033_pid_filter); + static struct dvb_frontend_ops af9033_ops; struct dvb_frontend *af9033_attach(const struct af9033_config *config, diff --git a/drivers/media/dvb-frontends/af9033.h b/drivers/media/dvb-frontends/af9033.h index c286e8f..de245f9 100644 --- a/drivers/media/dvb-frontends/af9033.h +++ b/drivers/media/dvb-frontends/af9033.h @@ -81,6 +81,11 @@ struct af9033_config { #if IS_ENABLED(CONFIG_DVB_AF9033) extern struct dvb_frontend *af9033_attach(const struct af9033_config *config, struct i2c_adapter *i2c); + +extern int af9033_pid_filter_ctrl(struct dvb_frontend *fe, int onoff); + +extern int af9033_pid_filter(struct dvb_frontend *fe, int index, u16 pid, + int onoff); #else static inline struct dvb_frontend *af9033_attach( const struct af9033_config *config, struct i2c_adapter *i2c) @@ -88,6 +93,20 @@ static inline struct dvb_frontend *af9033_attach( pr_warn("%s: driver disabled by Kconfig\n", __func__); return NULL; } + +static inline int af9033_pid_filter_ctrl(struct dvb_frontend *fe, int onoff) +{ + pr_warn("%s: driver disabled by Kconfig\n", __func__); + return -ENODEV; +} + +static inline int af9033_pid_filter(struct dvb_frontend *fe, int index, u16 pid, + int onoff) +{ + pr_warn("%s: driver disabled by Kconfig\n", __func__); + return -ENODEV; +} + #endif #endif /* AF9033_H */ -- cgit v1.1 From b24c2b4fb126007e36c5a67461527a5bfed33d17 Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Thu, 13 Feb 2014 15:53:05 -0300 Subject: [media] af9035: use af9033 PID filters PID filters are property of af9033 demod. Use PID filters from af9033 driver as it provides those now. Allow possible dual mode on USB 1.1 mode too as bandwidth could be just enough when filters are used on both frontends. Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/dvb-usb-v2/af9035.c | 61 ++++++----------------------------- 1 file changed, 10 insertions(+), 51 deletions(-) diff --git a/drivers/media/usb/dvb-usb-v2/af9035.c b/drivers/media/usb/dvb-usb-v2/af9035.c index 1434d37..31d09a2 100644 --- a/drivers/media/usb/dvb-usb-v2/af9035.c +++ b/drivers/media/usb/dvb-usb-v2/af9035.c @@ -945,12 +945,7 @@ static int af9035_frontend_callback(void *adapter_priv, int component, static int af9035_get_adapter_count(struct dvb_usb_device *d) { struct state *state = d_to_priv(d); - - /* disable 2nd adapter as we don't have PID filters implemented */ - if (d->udev->speed == USB_SPEED_FULL) - return 1; - else - return state->dual_mode + 1; + return state->dual_mode + 1; } static int af9035_frontend_attach(struct dvb_usb_adapter *adap) @@ -1376,58 +1371,15 @@ static int af9035_get_stream_config(struct dvb_frontend *fe, u8 *ts_type, return 0; } -/* - * FIXME: PID filter is property of demodulator and should be moved to the - * correct driver. Also we support only adapter #0 PID filter and will - * disable adapter #1 if USB1.1 is used. - */ static int af9035_pid_filter_ctrl(struct dvb_usb_adapter *adap, int onoff) { - struct dvb_usb_device *d = adap_to_d(adap); - int ret; - - dev_dbg(&d->udev->dev, "%s: onoff=%d\n", __func__, onoff); - - ret = af9035_wr_reg_mask(d, 0x80f993, onoff, 0x01); - if (ret < 0) - goto err; - - return 0; - -err: - dev_dbg(&d->udev->dev, "%s: failed=%d\n", __func__, ret); - - return ret; + return af9033_pid_filter_ctrl(adap->fe[0], onoff); } static int af9035_pid_filter(struct dvb_usb_adapter *adap, int index, u16 pid, int onoff) { - struct dvb_usb_device *d = adap_to_d(adap); - int ret; - u8 wbuf[2] = {(pid >> 0) & 0xff, (pid >> 8) & 0xff}; - - dev_dbg(&d->udev->dev, "%s: index=%d pid=%04x onoff=%d\n", - __func__, index, pid, onoff); - - ret = af9035_wr_regs(d, 0x80f996, wbuf, 2); - if (ret < 0) - goto err; - - ret = af9035_wr_reg(d, 0x80f994, onoff); - if (ret < 0) - goto err; - - ret = af9035_wr_reg(d, 0x80f995, index); - if (ret < 0) - goto err; - - return 0; - -err: - dev_dbg(&d->udev->dev, "%s: failed=%d\n", __func__, ret); - - return ret; + return af9033_pid_filter(adap->fe[0], index, pid, onoff); } static int af9035_probe(struct usb_interface *intf, @@ -1501,6 +1453,13 @@ static const struct dvb_usb_device_properties af9035_props = { .stream = DVB_USB_STREAM_BULK(0x84, 6, 87 * 188), }, { + .caps = DVB_USB_ADAP_HAS_PID_FILTER | + DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF, + + .pid_filter_count = 32, + .pid_filter_ctrl = af9035_pid_filter_ctrl, + .pid_filter = af9035_pid_filter, + .stream = DVB_USB_STREAM_BULK(0x85, 6, 87 * 188), }, }, -- cgit v1.1 From ed97a6fe5308e5982d118a25f0697b791af5ec50 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Fri, 14 Mar 2014 14:29:06 -0300 Subject: [media] af9033: Don't export functions for the hardware filter Exporting functions for hardware filter is a bad idea, as it breaks compilation if: CONFIG_DVB_USB_AF9035=y CONFIG_DVB_AF9033=m Because the PID filter function calls would be hardcoded at af9035. The same doesn't happen with af9033_attach() because the dvb_attach() doesn't hardcode it. Instead, it dynamically links it at runtime. However, calling dvb_attach() multiple times is problematic, as it increments module kref. So, the better is to pass one parameter for the af9033 module to fill the hardware filters, and then use it inside af9035. Signed-off-by: Mauro Carvalho Chehab Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/af9033.c | 14 +++++++++----- drivers/media/dvb-frontends/af9033.h | 23 +++++++++++++++-------- drivers/media/usb/dvb-usb-v2/af9035.c | 10 +++++++--- drivers/media/usb/dvb-usb-v2/af9035.h | 2 ++ 4 files changed, 33 insertions(+), 16 deletions(-) diff --git a/drivers/media/dvb-frontends/af9033.c b/drivers/media/dvb-frontends/af9033.c index 5a1c508..be4bec2 100644 --- a/drivers/media/dvb-frontends/af9033.c +++ b/drivers/media/dvb-frontends/af9033.c @@ -989,7 +989,7 @@ err: return ret; } -int af9033_pid_filter_ctrl(struct dvb_frontend *fe, int onoff) +static int af9033_pid_filter_ctrl(struct dvb_frontend *fe, int onoff) { struct af9033_state *state = fe->demodulator_priv; int ret; @@ -1007,9 +1007,8 @@ err: return ret; } -EXPORT_SYMBOL(af9033_pid_filter_ctrl); -int af9033_pid_filter(struct dvb_frontend *fe, int index, u16 pid, int onoff) +static int af9033_pid_filter(struct dvb_frontend *fe, int index, u16 pid, int onoff) { struct af9033_state *state = fe->demodulator_priv; int ret; @@ -1040,12 +1039,12 @@ err: return ret; } -EXPORT_SYMBOL(af9033_pid_filter); static struct dvb_frontend_ops af9033_ops; struct dvb_frontend *af9033_attach(const struct af9033_config *config, - struct i2c_adapter *i2c) + struct i2c_adapter *i2c, + struct af9033_ops *ops) { int ret; struct af9033_state *state; @@ -1120,6 +1119,11 @@ struct dvb_frontend *af9033_attach(const struct af9033_config *config, memcpy(&state->fe.ops, &af9033_ops, sizeof(struct dvb_frontend_ops)); state->fe.demodulator_priv = state; + if (ops) { + ops->pid_filter = af9033_pid_filter; + ops->pid_filter_ctrl = af9033_pid_filter_ctrl; + } + return &state->fe; err: diff --git a/drivers/media/dvb-frontends/af9033.h b/drivers/media/dvb-frontends/af9033.h index de245f9..539f4db 100644 --- a/drivers/media/dvb-frontends/af9033.h +++ b/drivers/media/dvb-frontends/af9033.h @@ -78,17 +78,24 @@ struct af9033_config { }; -#if IS_ENABLED(CONFIG_DVB_AF9033) -extern struct dvb_frontend *af9033_attach(const struct af9033_config *config, - struct i2c_adapter *i2c); +struct af9033_ops { + int (*pid_filter_ctrl)(struct dvb_frontend *fe, int onoff); + int (*pid_filter)(struct dvb_frontend *fe, int index, u16 pid, + int onoff); +}; -extern int af9033_pid_filter_ctrl(struct dvb_frontend *fe, int onoff); -extern int af9033_pid_filter(struct dvb_frontend *fe, int index, u16 pid, - int onoff); +#if IS_ENABLED(CONFIG_DVB_AF9033) +extern +struct dvb_frontend *af9033_attach(const struct af9033_config *config, + struct i2c_adapter *i2c, + struct af9033_ops *ops); + #else -static inline struct dvb_frontend *af9033_attach( - const struct af9033_config *config, struct i2c_adapter *i2c) +static inline +struct dvb_frontend *af9033_attach(const struct af9033_config *config, + struct i2c_adapter *i2c, + struct af9033_ops *ops) { pr_warn("%s: driver disabled by Kconfig\n", __func__); return NULL; diff --git a/drivers/media/usb/dvb-usb-v2/af9035.c b/drivers/media/usb/dvb-usb-v2/af9035.c index 31d09a2..021e4d3 100644 --- a/drivers/media/usb/dvb-usb-v2/af9035.c +++ b/drivers/media/usb/dvb-usb-v2/af9035.c @@ -963,7 +963,7 @@ static int af9035_frontend_attach(struct dvb_usb_adapter *adap) /* attach demodulator */ adap->fe[0] = dvb_attach(af9033_attach, &state->af9033_config[adap->id], - &d->i2c_adap); + &d->i2c_adap, &state->ops); if (adap->fe[0] == NULL) { ret = -ENODEV; goto err; @@ -1373,13 +1373,17 @@ static int af9035_get_stream_config(struct dvb_frontend *fe, u8 *ts_type, static int af9035_pid_filter_ctrl(struct dvb_usb_adapter *adap, int onoff) { - return af9033_pid_filter_ctrl(adap->fe[0], onoff); + struct state *state = adap_to_priv(adap); + + return state->ops.pid_filter_ctrl(adap->fe[0], onoff); } static int af9035_pid_filter(struct dvb_usb_adapter *adap, int index, u16 pid, int onoff) { - return af9033_pid_filter(adap->fe[0], index, pid, onoff); + struct state *state = adap_to_priv(adap); + + return state->ops.pid_filter(adap->fe[0], index, pid, onoff); } static int af9035_probe(struct usb_interface *intf, diff --git a/drivers/media/usb/dvb-usb-v2/af9035.h b/drivers/media/usb/dvb-usb-v2/af9035.h index a1c68d8..c21902f 100644 --- a/drivers/media/usb/dvb-usb-v2/af9035.h +++ b/drivers/media/usb/dvb-usb-v2/af9035.h @@ -62,6 +62,8 @@ struct state { u8 dual_mode:1; u16 eeprom_addr; struct af9033_config af9033_config[2]; + + struct af9033_ops ops; }; static const u32 clock_lut_af9035[] = { -- cgit v1.1 From 320c63870941ef3bb6e08e979d894ad6d51340d7 Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Sun, 16 Mar 2014 18:13:05 -0300 Subject: [media] e4000: make VIDEO_V4L2 dependency optional That tuner driver is mainly for DVB API, but there is some V4L2 API controls for SDR usage. Make driver compile conditional so that V4L2 is not mandatory. Without the V4L2 support driver is build as a DVB only, without SDR controls. Fixes following errors reported by kbuild test robot: ERROR: "v4l2_ctrl_auto_cluster" [drivers/media/tuners/e4000.ko] undefined! ERROR: "v4l2_ctrl_new_std" [drivers/media/tuners/e4000.ko] undefined! ERROR: "v4l2_ctrl_handler_init_class" [drivers/media/tuners/e4000.ko] undefined! ERROR: "v4l2_ctrl_handler_free" [drivers/media/tuners/e4000.ko] undefined! Reported-by: kbuild test robot Cc: Hans Verkuil Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- drivers/media/tuners/Kconfig | 2 +- drivers/media/tuners/e4000.c | 6 ++++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/media/tuners/Kconfig b/drivers/media/tuners/Kconfig index 85c0d96..a128488 100644 --- a/drivers/media/tuners/Kconfig +++ b/drivers/media/tuners/Kconfig @@ -203,7 +203,7 @@ config MEDIA_TUNER_TDA18212 config MEDIA_TUNER_E4000 tristate "Elonics E4000 silicon tuner" - depends on MEDIA_SUPPORT && I2C && VIDEO_V4L2 + depends on MEDIA_SUPPORT && I2C select REGMAP_I2C default m if !MEDIA_SUBDRV_AUTOSELECT help diff --git a/drivers/media/tuners/e4000.c b/drivers/media/tuners/e4000.c index 67ecf1b..90d9334 100644 --- a/drivers/media/tuners/e4000.c +++ b/drivers/media/tuners/e4000.c @@ -269,6 +269,7 @@ static int e4000_get_if_frequency(struct dvb_frontend *fe, u32 *frequency) return 0; } +#if IS_ENABLED(CONFIG_VIDEO_V4L2) static int e4000_set_lna_gain(struct dvb_frontend *fe) { struct e4000 *s = fe->tuner_priv; @@ -456,6 +457,7 @@ static const struct v4l2_ctrl_ops e4000_ctrl_ops = { .g_volatile_ctrl = e4000_g_volatile_ctrl, .s_ctrl = e4000_s_ctrl, }; +#endif static const struct dvb_tuner_ops e4000_tuner_ops = { .info = { @@ -522,6 +524,7 @@ static int e4000_probe(struct i2c_client *client, if (ret) goto err; +#if IS_ENABLED(CONFIG_VIDEO_V4L2) /* Register controls */ v4l2_ctrl_handler_init(&s->hdl, 9); s->bandwidth_auto = v4l2_ctrl_new_std(&s->hdl, &e4000_ctrl_ops, @@ -554,6 +557,7 @@ static int e4000_probe(struct i2c_client *client, } s->sd.ctrl_handler = &s->hdl; +#endif dev_info(&s->client->dev, "%s: Elonics E4000 successfully identified\n", @@ -584,7 +588,9 @@ static int e4000_remove(struct i2c_client *client) dev_dbg(&client->dev, "%s:\n", __func__); +#if IS_ENABLED(CONFIG_VIDEO_V4L2) v4l2_ctrl_handler_free(&s->hdl); +#endif memset(&fe->ops.tuner_ops, 0, sizeof(struct dvb_tuner_ops)); fe->tuner_priv = NULL; kfree(s); -- cgit v1.1 From df065b373f882c4efc396afa1f31cd8afedab356 Mon Sep 17 00:00:00 2001 From: Alexey Khoroshilov Date: Fri, 14 Mar 2014 18:04:03 -0300 Subject: [media] adv7180: free an interrupt on failure paths in init_device() There is request_irq() in init_device(), but the interrupt is not removed on failure paths. The patch adds proper error handling. Found by Linux Driver Verification project (linuxtesting.org). Signed-off-by: Alexey Khoroshilov Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/i2c/adv7180.c | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/drivers/media/i2c/adv7180.c b/drivers/media/i2c/adv7180.c index 9cfc9a3..5e638b1 100644 --- a/drivers/media/i2c/adv7180.c +++ b/drivers/media/i2c/adv7180.c @@ -561,40 +561,44 @@ static int init_device(struct i2c_client *client, struct adv7180_state *state) ret = i2c_smbus_write_byte_data(client, ADV7180_ADI_CTRL_REG, ADV7180_ADI_CTRL_IRQ_SPACE); if (ret < 0) - return ret; + goto err; /* config the Interrupt pin to be active low */ ret = i2c_smbus_write_byte_data(client, ADV7180_ICONF1_ADI, ADV7180_ICONF1_ACTIVE_LOW | ADV7180_ICONF1_PSYNC_ONLY); if (ret < 0) - return ret; + goto err; ret = i2c_smbus_write_byte_data(client, ADV7180_IMR1_ADI, 0); if (ret < 0) - return ret; + goto err; ret = i2c_smbus_write_byte_data(client, ADV7180_IMR2_ADI, 0); if (ret < 0) - return ret; + goto err; /* enable AD change interrupts interrupts */ ret = i2c_smbus_write_byte_data(client, ADV7180_IMR3_ADI, ADV7180_IRQ3_AD_CHANGE); if (ret < 0) - return ret; + goto err; ret = i2c_smbus_write_byte_data(client, ADV7180_IMR4_ADI, 0); if (ret < 0) - return ret; + goto err; ret = i2c_smbus_write_byte_data(client, ADV7180_ADI_CTRL_REG, 0); if (ret < 0) - return ret; + goto err; } return 0; + +err: + free_irq(state->irq, state); + return ret; } static int adv7180_probe(struct i2c_client *client, -- cgit v1.1 From 8432164ddf7bfe40748ac49995356ab4dfda43b7 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Sat, 15 Mar 2014 06:35:39 -0300 Subject: [media] Sensoray 2255 uses videobuf2 commit 340a30c514 "s2255drv: upgrade to videobuf2" changed the API used by the s2255 driver, but did not modify the Kconfig statement, which can lead to build errors when no other driver already uses VIDEOBUF2_VMALLOC. This patch does the necessary Kconfig change. Signed-off-by: Arnd Bergmann Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/s2255/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/usb/s2255/Kconfig b/drivers/media/usb/s2255/Kconfig index 7e8ee1f..8c3fcee 100644 --- a/drivers/media/usb/s2255/Kconfig +++ b/drivers/media/usb/s2255/Kconfig @@ -1,7 +1,7 @@ config USB_S2255 tristate "USB Sensoray 2255 video capture device" depends on VIDEO_V4L2 - select VIDEOBUF_VMALLOC + select VIDEOBUF2_VMALLOC default n help Say Y here if you want support for the Sensoray 2255 USB device. -- cgit v1.1 From 08debc1701ae31439f9d72ad497165b72e1b1ba4 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Mon, 10 Feb 2014 05:52:54 -0300 Subject: [media] si4713: fix Kconfig dependencies The SI4713 select should be I2C_SI4713 and the USB driver needs to depend on I2C as well. Signed-off-by: Hans Verkuil Reported-by: Paul Bolle Reported-by: Richard Weinberger Signed-off-by: Mauro Carvalho Chehab --- drivers/media/radio/si4713/Kconfig | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/media/radio/si4713/Kconfig b/drivers/media/radio/si4713/Kconfig index a7c3ba8..9c8b887 100644 --- a/drivers/media/radio/si4713/Kconfig +++ b/drivers/media/radio/si4713/Kconfig @@ -1,7 +1,7 @@ config USB_SI4713 tristate "Silicon Labs Si4713 FM Radio Transmitter support with USB" - depends on USB && RADIO_SI4713 - select SI4713 + depends on USB && I2C && RADIO_SI4713 + select I2C_SI4713 ---help--- This is a driver for USB devices with the Silicon Labs SI4713 chip. Currently these devices are known to work. @@ -16,7 +16,7 @@ config USB_SI4713 config PLATFORM_SI4713 tristate "Silicon Labs Si4713 FM Radio Transmitter support with I2C" depends on I2C && RADIO_SI4713 - select SI4713 + select I2C_SI4713 ---help--- This is a driver for I2C devices with the Silicon Labs SI4713 chip. -- cgit v1.1 From d984d325cdf4c1012a037097af4ad02e64b20431 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Mon, 17 Feb 2014 06:52:06 -0300 Subject: [media] saa6752hs: depends on CRC32 Have saa6752hs select CRC32. Signed-off-by: Hans Verkuil Reported-by: kbuild test robot Signed-off-by: Mauro Carvalho Chehab --- drivers/media/i2c/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig index 194caba..c930be3 100644 --- a/drivers/media/i2c/Kconfig +++ b/drivers/media/i2c/Kconfig @@ -668,6 +668,7 @@ comment "Audio/Video compression chips" config VIDEO_SAA6752HS tristate "Philips SAA6752HS MPEG-2 Audio/Video Encoder" depends on VIDEO_V4L2 && I2C + select CRC32 ---help--- Support for the Philips SAA6752HS MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer. -- cgit v1.1 From aee786acfc0a12bcd37a1c60f3198fb25cf7181a Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Thu, 27 Feb 2014 06:04:57 -0300 Subject: [media] videodev2.h: add parenthesis around macro arguments bt->width should be (bt)->width, and same for the other fields. Signed-off-by: Hans Verkuil Cc: stable@vger.kernel.org # For 3.12 or upper Signed-off-by: Mauro Carvalho Chehab --- include/uapi/linux/videodev2.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h index e35ad6c..ea468ee 100644 --- a/include/uapi/linux/videodev2.h +++ b/include/uapi/linux/videodev2.h @@ -1080,14 +1080,14 @@ struct v4l2_bt_timings { /* A few useful defines to calculate the total blanking and frame sizes */ #define V4L2_DV_BT_BLANKING_WIDTH(bt) \ - (bt->hfrontporch + bt->hsync + bt->hbackporch) + ((bt)->hfrontporch + (bt)->hsync + (bt)->hbackporch) #define V4L2_DV_BT_FRAME_WIDTH(bt) \ - (bt->width + V4L2_DV_BT_BLANKING_WIDTH(bt)) + ((bt)->width + V4L2_DV_BT_BLANKING_WIDTH(bt)) #define V4L2_DV_BT_BLANKING_HEIGHT(bt) \ - (bt->vfrontporch + bt->vsync + bt->vbackporch + \ - bt->il_vfrontporch + bt->il_vsync + bt->il_vbackporch) + ((bt)->vfrontporch + (bt)->vsync + (bt)->vbackporch + \ + (bt)->il_vfrontporch + (bt)->il_vsync + (bt)->il_vbackporch) #define V4L2_DV_BT_FRAME_HEIGHT(bt) \ - (bt->height + V4L2_DV_BT_BLANKING_HEIGHT(bt)) + ((bt)->height + V4L2_DV_BT_BLANKING_HEIGHT(bt)) /** struct v4l2_dv_timings - DV timings * @type: the type of the timings -- cgit v1.1 From c4885ada88e4331f8ac56d14296d0058359db2d7 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Tue, 4 Mar 2014 04:51:50 -0300 Subject: [media] v4l2-dv-timings: add module name, description, license I completely forgot to add them when I made this module. Loading this module without it will taint the kernel, which is not intended. Signed-off-by: Hans Verkuil Cc: stable@vger.kernel.org # for v3.12 and up Signed-off-by: Mauro Carvalho Chehab --- drivers/media/v4l2-core/v4l2-dv-timings.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/media/v4l2-core/v4l2-dv-timings.c b/drivers/media/v4l2-core/v4l2-dv-timings.c index f63a6bd..48b20df 100644 --- a/drivers/media/v4l2-core/v4l2-dv-timings.c +++ b/drivers/media/v4l2-core/v4l2-dv-timings.c @@ -26,6 +26,10 @@ #include #include +MODULE_AUTHOR("Hans Verkuil"); +MODULE_DESCRIPTION("V4L2 DV Timings Helper Functions"); +MODULE_LICENSE("GPL"); + const struct v4l2_dv_timings v4l2_dv_timings_presets[] = { V4L2_DV_BT_CEA_640X480P59_94, V4L2_DV_BT_CEA_720X480I59_94, -- cgit v1.1 From 30d652823de5fd7907d40e969a2d8e23938d8d03 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Fri, 7 Mar 2014 07:28:39 -0300 Subject: [media] saa7134: fix WARN_ON during resume Do not attempt to reload the tuner modules when resuming after a suspend. This triggers a WARN_ON in kernel/kmod.c:148 __request_module. This fixes https://bugzilla.kernel.org/show_bug.cgi?id=69581. This has always been wrong, but it was never noticed until the WARN_ON was added in 3.9. Signed-off-by: Hans Verkuil Cc: stable@vger.kernel.org # for v3.9 and up Signed-off-by: Mauro Carvalho Chehab --- drivers/media/pci/saa7134/saa7134-cards.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/media/pci/saa7134/saa7134-cards.c b/drivers/media/pci/saa7134/saa7134-cards.c index c9b2350..6e4bdb9 100644 --- a/drivers/media/pci/saa7134/saa7134-cards.c +++ b/drivers/media/pci/saa7134/saa7134-cards.c @@ -8045,8 +8045,8 @@ int saa7134_board_init2(struct saa7134_dev *dev) break; } /* switch() */ - /* initialize tuner */ - if (TUNER_ABSENT != dev->tuner_type) { + /* initialize tuner (don't do this when resuming) */ + if (!dev->insuspend && TUNER_ABSENT != dev->tuner_type) { int has_demod = (dev->tda9887_conf & TDA9887_PRESENT); /* Note: radio tuner address is always filled in, -- cgit v1.1 From 418a97cbcef9644e36d87140a6962d2cd4743e74 Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Sat, 1 Feb 2014 17:28:21 -0300 Subject: [media] m88ds3103: fix bug on .set_tone() Band switching didn't worked always reliably as there was one register bit set wrong. Thanks to Robert Schlabbach for pointing this bug and solution. Reported-by: Robert Schlabbach Signed-off-by: Antti Palosaari Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/m88ds3103.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/dvb-frontends/m88ds3103.c b/drivers/media/dvb-frontends/m88ds3103.c index b8f8df0..2ef8ce1 100644 --- a/drivers/media/dvb-frontends/m88ds3103.c +++ b/drivers/media/dvb-frontends/m88ds3103.c @@ -944,7 +944,7 @@ static int m88ds3103_set_tone(struct dvb_frontend *fe, switch (fe_sec_tone_mode) { case SEC_TONE_ON: tone = 0; - reg_a1_mask = 0x87; + reg_a1_mask = 0x47; break; case SEC_TONE_OFF: tone = 1; -- cgit v1.1 From 37571b163c15831cd0a213151c21387363dbf15b Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Wed, 12 Feb 2014 14:59:37 -0300 Subject: [media] em28xx-dvb: fix PCTV 461e tuner I2C binding Add missing m88ts2022 module reference counts as removing that module is not allowed when it is used by em28xx-dvb module. That same module was not unregistered correctly, fix it too. Error cases validated by returning errors from m88ds3103, m88ts2022 and a8293 probe(). Signed-off-by: Antti Palosaari Cc: stable@vger.kernel.org Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/em28xx/em28xx-dvb.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/media/usb/em28xx/em28xx-dvb.c b/drivers/media/usb/em28xx/em28xx-dvb.c index 6638394..d6ec572 100644 --- a/drivers/media/usb/em28xx/em28xx-dvb.c +++ b/drivers/media/usb/em28xx/em28xx-dvb.c @@ -1602,6 +1602,7 @@ static int em28xx_dvb_suspend(struct em28xx *dev) em28xx_info("Suspending DVB extension"); if (dev->dvb) { struct em28xx_dvb *dvb = dev->dvb; + struct i2c_client *client = dvb->i2c_client_tuner; if (dvb->fe[0]) { ret = dvb_frontend_suspend(dvb->fe[0]); @@ -1639,6 +1640,15 @@ static int em28xx_dvb_resume(struct em28xx *dev) ret = dvb_frontend_resume(dvb->fe[1]); em28xx_info("fe1 resume %d", ret); } + /* remove I2C tuner */ + if (client) { + module_put(client->dev.driver->owner); + i2c_unregister_device(client); + } + + em28xx_unregister_dvb(dvb); + kfree(dvb); + dev->dvb = NULL; } return 0; -- cgit v1.1 From 3ec40dcfb413214b2874aec858870502b61c2202 Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Tue, 11 Mar 2014 06:53:16 -0300 Subject: [media] em28xx: fix PCTV 290e LNA oops MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Pointer to device state has been moved to different location during some change. PCTV 290e LNA function still uses old pointer, carried over FE priv, and it crash. Reported-by: Janne Kujanpää Signed-off-by: Antti Palosaari Cc: stable@vger.kernel.org Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/em28xx/em28xx-dvb.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/media/usb/em28xx/em28xx-dvb.c b/drivers/media/usb/em28xx/em28xx-dvb.c index d6ec572..71e1fca 100644 --- a/drivers/media/usb/em28xx/em28xx-dvb.c +++ b/drivers/media/usb/em28xx/em28xx-dvb.c @@ -717,7 +717,8 @@ static void pctv_520e_init(struct em28xx *dev) static int em28xx_pctv_290e_set_lna(struct dvb_frontend *fe) { struct dtv_frontend_properties *c = &fe->dtv_property_cache; - struct em28xx *dev = fe->dvb->priv; + struct em28xx_i2c_bus *i2c_bus = fe->dvb->priv; + struct em28xx *dev = i2c_bus->dev; #ifdef CONFIG_GPIOLIB struct em28xx_dvb *dvb = dev->dvb; int ret; -- cgit v1.1 From 5eef22031295234990a26d809efb4100c1e60c11 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Mon, 31 Mar 2014 07:48:26 -0300 Subject: Revert "[media] em28xx-dvb: fix PCTV 461e tuner I2C binding" The first hunk of this patch got merged wrong, likely due to some changes at the em28xx resume code. Revert it to reapply it right. This reverts commit 37571b163c15831cd0a213151c21387363dbf15b. Reported-by: Chris Lee Reported-by: Hans Verkuil Cc: stable@vger.kernel.org # Don't apply this patch or 37571b163c15 Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/em28xx/em28xx-dvb.c | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/drivers/media/usb/em28xx/em28xx-dvb.c b/drivers/media/usb/em28xx/em28xx-dvb.c index 71e1fca..9b3f033 100644 --- a/drivers/media/usb/em28xx/em28xx-dvb.c +++ b/drivers/media/usb/em28xx/em28xx-dvb.c @@ -1603,7 +1603,6 @@ static int em28xx_dvb_suspend(struct em28xx *dev) em28xx_info("Suspending DVB extension"); if (dev->dvb) { struct em28xx_dvb *dvb = dev->dvb; - struct i2c_client *client = dvb->i2c_client_tuner; if (dvb->fe[0]) { ret = dvb_frontend_suspend(dvb->fe[0]); @@ -1641,15 +1640,6 @@ static int em28xx_dvb_resume(struct em28xx *dev) ret = dvb_frontend_resume(dvb->fe[1]); em28xx_info("fe1 resume %d", ret); } - /* remove I2C tuner */ - if (client) { - module_put(client->dev.driver->owner); - i2c_unregister_device(client); - } - - em28xx_unregister_dvb(dvb); - kfree(dvb); - dev->dvb = NULL; } return 0; -- cgit v1.1 From a83b93a7480441a47856dc9104bea970e84cda87 Mon Sep 17 00:00:00 2001 From: Antti Palosaari Date: Wed, 12 Feb 2014 14:59:37 -0300 Subject: [media] em28xx-dvb: fix PCTV 461e tuner I2C binding Add missing m88ts2022 module reference counts as removing that module is not allowed when it is used by em28xx-dvb module. That same module was not unregistered correctly, fix it too. Error cases validated by returning errors from m88ds3103, m88ts2022 and a8293 probe(). Signed-off-by: Antti Palosaari Cc: stable@vger.kernel.org Signed-off-by: Mauro Carvalho Chehab --- drivers/media/usb/em28xx/em28xx-dvb.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/media/usb/em28xx/em28xx-dvb.c b/drivers/media/usb/em28xx/em28xx-dvb.c index 9b3f033..f599b18 100644 --- a/drivers/media/usb/em28xx/em28xx-dvb.c +++ b/drivers/media/usb/em28xx/em28xx-dvb.c @@ -1630,6 +1630,7 @@ static int em28xx_dvb_resume(struct em28xx *dev) em28xx_info("Resuming DVB extension"); if (dev->dvb) { struct em28xx_dvb *dvb = dev->dvb; + struct i2c_client *client = dvb->i2c_client_tuner; if (dvb->fe[0]) { ret = dvb_frontend_resume(dvb->fe[0]); @@ -1640,6 +1641,15 @@ static int em28xx_dvb_resume(struct em28xx *dev) ret = dvb_frontend_resume(dvb->fe[1]); em28xx_info("fe1 resume %d", ret); } + /* remove I2C tuner */ + if (client) { + module_put(client->dev.driver->owner); + i2c_unregister_device(client); + } + + em28xx_unregister_dvb(dvb); + kfree(dvb); + dev->dvb = NULL; } return 0; -- cgit v1.1