From 0825c672599bedbb423ef26f3cdd0c5a014da149 Mon Sep 17 00:00:00 2001 From: Aleksey Makarov Date: Thu, 18 Oct 2007 07:38:14 +0100 Subject: [ARM] 4613/1: pxa300: MFP typo fix This fixes a typo in MFP address map. Signed-off-by: Aleksey Makarov Acked-by: Eric Miao Signed-off-by: Russell King --- arch/arm/mach-pxa/pxa300.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-pxa/pxa300.c b/arch/arm/mach-pxa/pxa300.c index 5363b13..7a34231 100644 --- a/arch/arm/mach-pxa/pxa300.c +++ b/arch/arm/mach-pxa/pxa300.c @@ -23,8 +23,10 @@ static struct pxa3xx_mfp_addr_map pxa300_mfp_addr_map[] __initdata = { MFP_ADDR_X(GPIO0, GPIO2, 0x00b4), MFP_ADDR_X(GPIO3, GPIO26, 0x027c), - MFP_ADDR_X(GPIO27, GPIO127, 0x0400), - MFP_ADDR_X(GPIO0_2, GPIO6_2, 0x02ec), + MFP_ADDR_X(GPIO27, GPIO98, 0x0400), + MFP_ADDR_X(GPIO99, GPIO127, 0x0600), + MFP_ADDR_X(GPIO0_2, GPIO1_2, 0x0674), + MFP_ADDR_X(GPIO2_2, GPIO6_2, 0x02dc), MFP_ADDR(nBE0, 0x0204), MFP_ADDR(nBE1, 0x0208), -- cgit v1.1 From 67f18f34583c9dda0dbcd4088df9070926f7e611 Mon Sep 17 00:00:00 2001 From: Takashi Ohmasa Date: Fri, 19 Oct 2007 13:58:51 +0100 Subject: [ARM] 4629/1: Fix VFP emulation code to clear all exception flags of FPEXC All exception flags of the FPEXC register must be cleared before returning from exception code to user code, including FP2V and OFC. Signed-off-by: Takashi Ohmasa Signed-off-by: Russell King --- arch/arm/vfp/vfpmodule.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c index eea3f50..b4e210d 100644 --- a/arch/arm/vfp/vfpmodule.c +++ b/arch/arm/vfp/vfpmodule.c @@ -229,7 +229,7 @@ void VFP9_bounce(u32 trigger, u32 fpexc, struct pt_regs *regs) /* * Enable access to the VFP so we can handle the bounce. */ - fmxr(FPEXC, fpexc & ~(FPEXC_EX|FPEXC_INV|FPEXC_UFC|FPEXC_IOC)); + fmxr(FPEXC, fpexc & ~(FPEXC_EX|FPEXC_FPV2|FPEXC_INV|FPEXC_UFC|FPEXC_OFC|FPEXC_IOC)); orig_fpscr = fpscr = fmrx(FPSCR); -- cgit v1.1 From b9a5ce3cae2f6d04c521204004a36be46656ec7b Mon Sep 17 00:00:00 2001 From: Takashi Ohmasa Date: Fri, 19 Oct 2007 13:59:15 +0100 Subject: [ARM] 4630/1: Fix the vector stride of the double vector instruction. The vector stride of the double-precision vector instructions must be changed to 1-2 from even 2-4, because the double registers numbering has been changed to 0-15 from even 0-30 by 1356c1948da967bc1d4c663762bfe21dfcec4b2f commit. Signed-off-by: Takashi Ohmasa Signed-off-by: Russell King --- arch/arm/vfp/vfpdouble.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/vfp/vfpdouble.c b/arch/arm/vfp/vfpdouble.c index 74e89f8..190a09a 100644 --- a/arch/arm/vfp/vfpdouble.c +++ b/arch/arm/vfp/vfpdouble.c @@ -1132,7 +1132,7 @@ u32 vfp_double_cpdo(u32 inst, u32 fpscr) unsigned int vecitr, veclen, vecstride; struct op *fop; - vecstride = (1 + ((fpscr & FPSCR_STRIDE_MASK) == FPSCR_STRIDE_MASK)) * 2; + vecstride = (1 + ((fpscr & FPSCR_STRIDE_MASK) == FPSCR_STRIDE_MASK)); fop = (op == FOP_EXT) ? &fops_ext[FEXT_TO_IDX(inst)] : &fops[FOP_TO_IDX(op)]; @@ -1184,10 +1184,10 @@ u32 vfp_double_cpdo(u32 inst, u32 fpscr) * CHECK: It appears to be undefined whether we stop when * we encounter an exception. We continue. */ - dest = FREG_BANK(dest) + ((FREG_IDX(dest) + vecstride) & 6); - dn = FREG_BANK(dn) + ((FREG_IDX(dn) + vecstride) & 6); + dest = FREG_BANK(dest) + ((FREG_IDX(dest) + vecstride) & 3); + dn = FREG_BANK(dn) + ((FREG_IDX(dn) + vecstride) & 3); if (FREG_BANK(dm) != 0) - dm = FREG_BANK(dm) + ((FREG_IDX(dm) + vecstride) & 6); + dm = FREG_BANK(dm) + ((FREG_IDX(dm) + vecstride) & 3); } return exceptions; -- cgit v1.1