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* ASoC: Intel: create haswell folder and move haswell platform files inJie Yang2015-04-061-709/+0
| | | | | | | | | Restructure the sound/soc/intel/ directory: create haswell folder, and move haswell platform files here. Signed-off-by: Jie Yang <yang.jie@intel.com> Reviewed-by: Liam Girdwood <liam.r.girdwood@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* ASoC: Intel: add function to load sound effect module wavesLu, Han2015-03-111-0/+2
| | | | | | | | Try to load module waves and allocate runtime blocks for it if the firmware image of module waves exists. Signed-off-by: Lu, Han <han.lu@intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* ASoC: Intel: add function to load firmware imageLu, Han2015-03-111-0/+1
| | | | | | | | | Add a general method to load firmware image, and apply to base firmware image loading. With the method, the driver will support loading multiple different modules in order to support different features. Signed-off-by: Lu, Han <han.lu@intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* Merge branch 'fix/intel' of ↵Mark Brown2015-03-111-3/+0
|\ | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into asoc-intel
| * ASoC: Intel: remove conflicts when load/unload multiple firmware imagesLu, Han2015-03-061-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | Details: 1. Unload all modules on fw_list of dsp when suspend, and reload all modules on fw_list when resume. 2. A DSP expects only one scratch, but hsw_parse_fw_image() allocates scratch blocks for each firmware image it parses. Move the allocate function sst_block_alloc_scratch() out of hsw_parse_fw_image() to make sure a scratch be allocated only after all firmware images be parsed. Signed-off-by: Lu, Han <han.lu@intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* | ASoC: Intel: Always enable DRAM block for FW dumpJie Yang2015-01-081-5/+12
|/ | | | | | | | | | The first 512 bytes of data DRAM memory is used for FW dump, and this first data SRAM block should be never power gated (always on), here always enable the block(DSRAM[0]) for D0 stage. Signed-off-by: Jie Yang <yang.jie@intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* ASoC: Intel: Work around to fix HW D3 potential crash issueJie Yang2014-10-301-14/+88
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When using clock gatings to save power, there are some known issues: 1. core clock gating (DCLCGE) must be disabled during D0 and D3 entry and updating SRAM banks (VDRTCTL0). 2. DSP trunk clock gating (DTCGE) can cause FW crashes, disable it in D0. To align with the new W/A flow from FW team, we must set VDRTCTL0.D3PGD to 1 (D3 power gating disabled) at first startup and keep it all the time. ADSP will be in D0 on first boot by BIOS part of WA. Required delays must be preserved (waiting for HW to stabilize, after enabling CCG, changing SRAM PG, D3PG). D3->D0: 1. Disable core clock gating (VDRTCTL2.DCLCGE = 0) 2. Enable other CG apart from DTCG and DCLCG (VDRTCTL2. DCLCGE and DTCGE = 0) 3. Disable D3PG (VDRTCTL0.D3PGD = 1) 4. Power up necessary SRAM and wait at least for 18 clock cycles for every bank you have powered up 5. Set D0 state(PMCS.PS = 0), wait for HW 6. Restore MCLK (clkctl.smos, disabled in D3 entry point 4) 7. Stall and reset core, set CSR 8. Enable core clock gating (VDRTCTL2.DCLCGE = 1), delay 50 us 9. Unreset core 10.Load FW, configure PLL and other necessary things 11.Unstall core Changing SRAM PG during D0: 1. Disable core clock gating (VDRTCTL2.DCLCGE = 0) 2. Set PG mask 3. Wait at least for 18 clock cycles for every bank you have powered up 4. Enable core clock gating, delay 50 us D0->D3: 1. Disable core clock gating (DCLCGE = 0) 2. Stall and reset core 3. Power down entire SRAM and wait at least for 18 clock cycles for every bank (Enable SRAM PG (ISRAMPGE = 0x3FF, DSRAMPGE = 0xFFFFF, D3SRAMPGD = 0), remember about preserving VDRTCTL0.D3PGD = 1) 4. Shutdown PLL, disable MCLK(clkctl.smos = 0), Enable DTCG to save power 5. Set D3 state(PMCS.PS = 3), delay 50 us 6. Enable core clock gating, delay 50 us Signed-off-by: Jie Yang <yang.jie@intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* ASoC: Intel: Add PM support to the HSW/BDW DSP core.Liam Girdwood2014-10-291-39/+119
| | | | | | | | | Add support for PM wake, sleep and stall calls to the core HSW/BDW driver. This includes reworking the reset and boot code and adding new calls for setting D3/D0 state. Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* ASoC: Intel: Make ADSP memory block allocation more genericLiam Girdwood2014-10-281-28/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current block allocation is tied to block type and requestor type. Make the allocation more generic by removing the struct module parameter and adding a generic block allocator structure. Also pass in the list that the blocks have to be added too in order to remove dependence on block requestor type. ASoC: Intel: update scratch allocator to use generic block allocator Update the scratch allocator to use the generic block allocator and calculate total scratch buffer size. ASoC: Intel: Add call to calculate offsets internally within the DSP. A call to calculate internal DSP memory addresses used to allocate persistent and scartch buffers. ASoC: Intel: Add runtime module support. Add support for runtime module objects that can be created for every FW module that is parsed from the FW file. This gives a 1:N mapping between the FW module from file and the runtime instantiations of that module. We also need to make sure we remove every module and runtime module when we unload the FW. ASoC: Intel: Add DMA firmware loading support Add support for DMA to load firmware modules to the DSP memory blocks. Two DMA engines are supported, DesignWare and Intel MID. ASoC: Intel: Add runtime module lookup API call Add an API to allow quick lookup of runtime modules based on ID. ASoC: Intel: Provide streams with dynamic module information Remove the hard coded module paramaters and provide each module with dynamically generated buffer information for scratch and persistent buffers. Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
*-. Merge remote-tracking branches 'asoc/topic/intel', 'asoc/topic/kirkwood', ↵Mark Brown2014-08-041-21/+36
|\ \ | | | | | | | | | 'asoc/topic/max98090' and 'asoc/topic/mc13783' into asoc-next
| * | ASoC: Intel: Fix naming of HMDC register macros.Liam Girdwood2014-07-301-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | HMDC is the correct naming for this register. Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com> Signed-off-by: Jie Yang <yang.jie@intel.com> Signed-off-by: Mark Brown <broonie@linaro.org>
| * | ASoC: intel: Cleanup useless ACPI inclusion.Lv Zheng2014-07-161-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | The sst-haswell-dsp.c is an ACPI independent file, this patch removes ACPI header files for it. Signed-off-by: Lv Zheng <lv.zheng@intel.com> Signed-off-by: Mark Brown <broonie@linaro.org>
| * | ASoC: Intel: Start with all memory banks disabledJie Yang2014-07-141-2/+3
| | | | | | | | | | | | | | | | | | | | | All required banks are enabled during boot procedure. Signed-off-by: Jie Yang <yang.jie@intel.com> Signed-off-by: Mark Brown <broonie@linaro.org>
| * | ASoC: Intel: Use a table for ADSP SRAM shiftJie Yang2014-07-141-10/+29
| | | | | | | | | | | | | | | | | | | | | Use a table for ADSP IRAM/DRAM bit shift. Signed-off-by: Jie Yang <yang.jie@intel.com> Signed-off-by: Mark Brown <broonie@linaro.org>
| * | ASoC: Intel: Merge wild cat point ADSP DRAM regionsJie Yang2014-07-141-3/+1
| |/ | | | | | | | | | | | | Merge D-SRAM0 D-SRAM1 D-SRAM2 to D-SRAM, for wild cat point ADSP mem regions. Signed-off-by: Jie Yang <yang.jie@intel.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* | ASoC: Intel: Add dummy read for SRAM block enableJie Yang2014-07-141-0/+13
|/ | | | | | | | Add dummy read after each block enable, to workaround SRAM write missing bytes issue. Signed-off-by: Jie Yang <yang.jie@intel.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* ASoC: Intel: Fix Audio DSP usage when IOMMU is enabled.Liam Girdwood2014-05-021-2/+2
| | | | | | | | | | | | The Intel IOMMU requires that the ACPI device is used to allocate all DMA memory buffers. This means we need to pass the DMA device pointer into child component devices that allocate DMA memory. We also only set the DMA mask for the ACPI device now instead of for each component device. Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* Merge remote-tracking branches 'asoc/topic/ml26124', 'asoc/topic/of', ↵Mark Brown2014-03-121-0/+517
'asoc/topic/omap', 'asoc/topic/pxa' and 'asoc/topic/rcar' into asoc-next
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