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* ASoC: fsl_sai: Make error message conciseFabio Estevam2015-01-081-1/+1
| | | | | | | | | | | Currently the error message uses 'np->full_name' which leads to a very verbose log that contains the full path of the node. We can have a concise log by using pdev->name instead. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* ASoC: fsl: drop owner assignment from platform_driversWolfram Sang2014-10-201-1/+0
| | | | | | | A platform_driver does not need to set an owner, it will be populated by the driver core. Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
* ASoC: fsl-sai: using 'lsb-first' property instead of 'big-endian-data'.Xiubo Li2014-09-011-3/+3
| | | | | | | | | | | | | | | | | | | | The 'big-endian-data' property is originally used to indicate whether the LSB firstly or MSB firstly will be transmitted to the CODEC or received from the CODEC, and there has nothing relation to the memory data. Generally, if the audio data in big endian format, which will be using the bytes reversion, Here this can only be used to bits reversion. So using the 'lsb-first' instead of 'big-endian-data' can make the code to be readable easier and more easy to understand what this property is used to do. This property used for configuring whether the LSB or the MSB is transmitted first for the fifo data. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* Merge branch 'topic/fsl' of ↵Mark Brown2014-09-011-5/+1
|\ | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into asoc-fsl-sai
| * ASoC: fsl-sai: Convert to use regmap framework's endianness method.Xiubo Li2014-08-271-5/+1
| | | | | | | | | | Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* | ASoC: fsl_sai: Set SYNC bit of TCR2 to Asynchronous ModeNicolin Chen2014-08-161-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is one design rule according to SAI's reference manual: If the transmitter bit clock and frame sync are to be used by both transmitter and receiver, the transmitter must be configured for asynchronous operation and the receiver for synchronous operation. And SYNC of TCR2 is a 2-width control bit: 00 Asynchronous mode. 01 Synchronous with receiver. 10 Synchronous with another SAI transmitter. 11 Synchronous with another SAI receiver. So the driver should have set SYNC bit of TCR2 to 0x0, and meanwhile set SYNC bit of RCR2 to 0x1 (Synchronous with transmitter). Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* | ASoC: fsl_sai: Make Synchronous and Asynchronous modes exclusiveNicolin Chen2014-08-161-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | The previous patch (ASoC: fsl_sai: Add asynchronous mode support) added new Device Tree bindings for Asynchronous and Synchronous modes support. However, these two shall not be present at the same time. So this patch just simply makes them exclusive so as to avoid incorrect Device Tree binding usage. Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* | ASoC: fsl_sai: Add asynchronous mode supportNicolin Chen2014-08-161-4/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SAI supports these operation modes: 1) asynchronous mode Both Tx and Rx are set to be asynchronous. 2) synchronous mode (Rx sync with Tx) Tx is set to be asynchronous, Rx is set to be synchronous. 3) synchronous mode (Tx sync with Rx) Rx is set to be asynchronous, Tx is set to be synchronous. 4) synchronous mode (Tx/Rx sync with another SAI's Tx) 5) synchronous mode (Tx/Rx sync with another SAI's Rx) * 4) and 5) are beyond this patch because they are related with another SAI. As the initial version of this SAI driver, it supported 2) as default while the others were totally missing. So this patch just adds supports for 1) and 3). Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* | ASoC: fsl_sai: Set SYNC bit of TCR2 to Asynchronous ModeNicolin Chen2014-08-161-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is one design rule according to SAI's reference manual: If the transmitter bit clock and frame sync are to be used by both transmitter and receiver, the transmitter must be configured for asynchronous operation and the receiver for synchronous operation. And SYNC of TCR2 is a 2-width control bit: 00 Asynchronous mode. 01 Synchronous with receiver. 10 Synchronous with another SAI transmitter. 11 Synchronous with another SAI receiver. So the driver should have set SYNC bit of TCR2 to 0x0, and meanwhile set SYNC bit of RCR2 to 0x1 (Synchronous with transmitter). Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* | ASoC: fsl_sai: Initialize with software resetNicolin Chen2014-08-161-2/+7
|/ | | | | | | | | This patch adds software reset code in dai_probe() so as to make a true init by clearing SAI's internal logic, including the bit clock generation, status flags, and FIFO pointers. Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
*-. Merge remote-tracking branches 'asoc/topic/fsl', 'asoc/topic/fsl-asrc', ↵Mark Brown2014-08-041-0/+2
|\ \ | | | | | | | | | 'asoc/topic/fsl-spdif' and 'asoc/topic/imx-audmux' into asoc-next
| * | ASoC: fsl_sai: Add stream names for DPCM usageNicolin Chen2014-07-311-0/+2
| |/ | | | | | | | | | | | | | | | | | | DPCM needs extra dapm routes in the machine driver to route audio between Front-End and Back-End. In order to differ the stream names in the route map from CODECs, we here add specific stream names to SAI driver so that we can implement ASRC via DPCM to it. Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* | ASoC: fsl_sai: Improve enable flow in fsl_sai_trigger()Nicolin Chen2014-07-251-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The previous enable flow: 1, Enable TE&RE (SAI starts to consume tx FIFO and feed rx FIFO) 2, Mask IRQ of Tx/Rx to enable its interrupt. 3, Enable DMA request of Tx/Rx. As this flow would enable DMA request later than TERE, the Tx FIFO would be easily emptied into underrun while Rx FIFO would be easily stuffed into overrun due to the delayed DMA transfering. This issue happened merely occational before the patch 'ASoC: fsl_sai: Reset FIFOs after disabling TE/RE' because there were useless data remaining in the FIFO for the gap. However, it manifested after FIFO reset's implemented. After this patch, the new flow: 1, Enable DMA request of Tx/Rx. 2, Enable TE&RE (SAI starts to consume tx FIFO and feed rx FIFO) 3, Mask IRQ of Tx/Rx to enable its interrupt. Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* | ASoC: fsl_sai: Don't reset FIFO until TE/RE bit is unsetNicolin Chen2014-07-251-5/+14
| | | | | | | | | | | | | | | | | | | | | | | | TE/RE bit of T/RCSR will remain set untill the current frame is physically finished. The FIFO reset operation should wait this bit's totally cleared rather than ignoring its status which might cause TE/RE disabling failed. This patch adds delay and timeout to wait for its completion before FIFO reset. Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* | ASoC: fsl_sai: Reduce race condition during TE/RE enablingNicolin Chen2014-07-251-11/+7
| | | | | | | | | | | | | | | | | | | | | | | | For trigger start, we don't need to check if it's the first time to enable TE/RE or second time. It doesn't hurt to enable them any way, which in the meantime can reduce race condition for TE/RE enabling. For trigger stop, we will definitely clear FRDE of current direction. Thus the driver only needs to read the opposite one's. Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* | ASoC: fsl_sai: Fix incorrect register writing in fsl_sai_isr()Nicolin Chen2014-07-171-1/+1
| | | | | | | | | | | | | | In the rx irq handling part, we should clear the flags in RCSR not TCSR. Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* | ASoC: fsl_sai: Reset FIFOs after disabling TE/RENicolin Chen2014-07-171-2/+5
|/ | | | | | | | SAI will not clear their FIFOs after disabling TE/RE. Therfore, the driver should take care the task so as not to let useless data remain in the FIFO. Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* ASoC: fsl_sai: Use FSL_SAI_xXR() and regmap_update_bits() to simplify codeNicolin Chen2014-04-141-76/+25
| | | | | | | By doing this, the driver can drop around 50 lines and become neater. Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* ASoC: fsl_sai: Fix incorrect condition check in trigger()Nicolin Chen2014-04-141-1/+2
| | | | | | | | | | | | Patch ASoC: fsl_sai: Fix buggy configurations in trigger() doesn't entirely fix the condition: FRDE of the current substream direction is being cleared while the code is still using the non-updated one. Thus this patch fixes this issue by checking the opposite one's FRDE alone since the current one's is absolutely disabled. Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* ASoC: fsl_sai: Add clock controls for SAINicolin Chen2014-04-141-2/+36
| | | | | | | | | | | | | | | | | | | | | | The SAI mainly has the following clocks: bus clock control and configure registers and to generate synchronous interrupts and DMA requests. mclk1, mclk2, mclk3 to generate the bit clock when the receiver or transmitter is configured for an internally generated bit clock. So this patch adds these clocks and their clock controls to the driver. [ To concern the old DTB cases, I've added a bit of extra code to make the driver compatible with them. And by marking clock NULL if failed to get, the clk_prepare() or clk_get_rate() would easily return 0 so no further path should be broken. -- by Nicolin ] Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com> Acked-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* ASoC: fsl_sai: Add imx6sx platform supportNicolin Chen2014-04-141-2/+10
| | | | | | | | | | | The next coming i.MX6 Solo X SoC also contains SAI module while we use imp_pcm_init() for i.MX platform. So this patch adds one compatible route for imx6sx and updates the DT doc accordingly. Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* ASoC: fsl_sai: Separately enable interrupts for Tx and Rx streamsNicolin Chen2014-04-141-2/+6
| | | | | | | | | | | We only enable one side interrupt for each stream since over/underrun on the opposite stream would be resulted from what we previously did, enabling TERE but remaining FRDE disabled, even though the xrun on the opposite direction will not break the current stream. Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com> Acked-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* ASoC: fsl_sai: Fix buggy configurations in trigger()Nicolin Chen2014-04-141-18/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current trigger() has two crucial problems: 1) The DMA request enabling operations (FSL_SAI_CSR_FRDE) for Tx and Rx are now totally exclusive: It would fail to run simultaneous Tx-Rx cases. 2) The TERE disabling operation depends on an incorrect condition -- active reference count that only gets increased in snd_pcm_open() and decreased in snd_pcm_close(): The TERE would never get cleared. So this patch overwrites the trigger function by following these rules: A) We continue to support tx-async-while-rx-sync-to-tx case alone, which's originally limited by this fsl_sai driver, but we make the code easy to modify for the further support of the opposite case. B) We enable both TE and RE for PLAYBACK stream or CAPTURE stream but only enabling the DMA request bit (FSL_SAI_CSR_FRDE) of the current direction due to the requirement of SAI -- For tx-async-while-rx-sync-to-tx case, the receiver is enabled only when both the transmitter and receiver are enabled. Tested cases: a) aplay test.wav -d5 b) arecord -r44100 -c2 -fS16_LE test.wav -d5 c) arecord -r44100 -c2 -fS16_LE -d5 | aplay d) (aplay test2.wav &); sleep 1; arecord -r44100 -c2 -fS16_LE test.wav -d1 e) (arecord -r44100 -c2 -fS16_LE test.wav -d5 &); sleep 1; aplay test.wav -d1 Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com> Acked-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* ASoC: fsl_sai: Improve fsl_sai_isr()Nicolin Chen2014-04-141-19/+45
| | | | | | | | | | This patch improves fsl_sai_isr() in these ways: 1, Add comment for mask fetching code. 2, Return IRQ_NONE if the IRQ is not for the device. 3, Use regmap_write() instead of regmap_update_bits(). Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* ASoC: fsl_sai: Fix Bit Clock Polarity configurationsNicolin Chen2014-04-081-4/+4
| | | | | | | | | | | | | | | | | | | | | The BCP bit in TCR4/RCR4 register rules as followings: 0 Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. 1 Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge. For all formats currently supported in the fsl_sai driver, they're exactly sending data on the falling edge and sampling on the rising edge. However, the driver clears this BCP bit for all of them which results click noise when working with SGTL5000 and big noise with WM8962. Thus this patch corrects the BCP settings for all the formats here to fix the nosie issue. Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com> Acked-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* ASoC: fsl_sai: Add isr to deal with error flagNicolin Chen2014-03-271-3/+82
| | | | | | | | | | | | It's quite cricial to clear error flags because SAI might hang if getting FIFO underrun during playback (I haven't confirmed the same issue on Rx overflow though). So this patch enables those irq and adds isr() to clear the flags so as to keep playback entirely safe. Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* ASoC: fsl-sai: Add SND_SOC_DAIFMT_DSP_A/B support.Xiubo Li2014-02-271-3/+42
| | | | | | | | o Add SND_SOC_DAIFMT_DSP_A support. o Add SND_SOC_DAIFMT_DSP_B support. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* ASoC: fsl-sai: fix Freescale SAI DAI format setting.Xiubo Li2014-02-261-9/+29
| | | | | | | | | | | o Fix some bugs of fsl_sai_set_dai_fmt_tr(). o Add SND_SOC_DAIFMT_LEFT_J support. o Add SND_SOC_DAIFMT_CBS_CFM support. o Add SND_SOC_DAIFMT_CBM_CFS support. o And SND_SOC_DAIFMT_RIGHT_J need to be done in the future. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* ASoC: fsl-sai: convert to use regmap API for Freeacale SAIXiubo Li2014-02-101-111/+144
| | | | | Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* ASoC: fsl-sai: Clean up the codeXiubo Li2014-01-081-4/+3
| | | | | | | Makes the code slightly shorter. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* ASoC: fsl_sai: fix the endianess for SAI fifo data.Xiubo Li2013-12-311-4/+4
| | | | | | | Revert the SAI's endianess for fifo data to/from DMA engine. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* ASoC: fsl_sai: Fix one bug for hardware limitation.Xiubo Li2013-12-311-5/+10
| | | | | | | | | | | | | This is maybe one bug or a limitation of the hardware that the {T,R}CR2's Synchronous Mode bits must be set as late as possible, or the SAI device maybe hanged up, and there has not any explaination about this limitation in the SAI Data Sheet. And the {T,R}CR2's Synchronous Mode bits must be set at the same time whether for Tx or Rx stream. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* ASoC: fsl_sai: Add disable operation for the corresponding data channel.Xiubo Li2013-12-301-8/+13
| | | | | | | | | Enables/Disables the corresponding data channel for tx/rx operation. A channel must be enabled before its FIFO is accessed, and then disable it when tx/rx is stopped or idle. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* ASoC: fsl_sai: Move the global registers setting to _dai_probe()Xiubo Li2013-12-301-5/+12
| | | | | | | | | | | Because we cannot make sure which one of _dai_fmt() and _dai_sysclk() will be firstly called. So move the RCSR/TCSR and TCR1/RCR1's initialization to _dai_probe(), and this can make sure that before any of {T,R}CR{1~5} register to be set the RCSR/TCSR's RE/TE bit has been cleared for the hareware limitation. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* ASoC: fsl_sai: Sort local variable in general wayNicolin Chen2013-12-211-7/+7
| | | | | | | | | | | | | | | | | Generally we would write code for local variable like: static new_func() { struct xxx *yyy; ... int ret; } But this driver only follows this pattern for some functions, not all. Thus this patch sorts the local variable in the general way. Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com> Reviewed-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* ASoC: fsl_sai: Make dev_err information neaterNicolin Chen2013-12-211-12/+4
| | | | | | | | | Since using dev_err() there's no need to mention SAI any more, it will print the full name of the driver -- fsl_sai. Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com> Reviewed-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* ASoC: fsl_sai: Drop useless ret in startup()Nicolin Chen2013-12-211-4/+1
| | | | | | | | We can save this ret to make the code neater. Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com> Reviewed-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* ASoC: fsl_sai: Drop useless channels check in hw_params()Nicolin Chen2013-12-211-4/+1
| | | | | | | | | SAi only supports two data channels on hardware level and the driver also does register the min->1 and max->2, so no need to check channels. Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com> Reviewed-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* ASoC: fsl_sai: Use snd_pcm_format_width()Nicolin Chen2013-12-211-15/+2
| | | | | | | | Use common helper function snd_pcm_format_width() to make code neater. Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com> Reviewed-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* ASoC: fsl_sai: Keep symmetry for clk_enable() and clk_disable()Nicolin Chen2013-12-211-6/+8
| | | | | | | | | There are two functions haven't clk_disable_unprepare() if having error. Thus fix them. Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com> Reviewed-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* ASoC: fsl-sai: Use snd_soc_dai_init_dma_data()Xiubo Li2013-12-211-2/+2
| | | | | | | Makes the code slightly shorter Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* ASoC: fsl-sai: Use devm_snd_dmaengine_pcm_register()Xiubo Li2013-12-211-14/+1
| | | | | | | Makes the code slightly shorter Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* ASoC: fsl-sai: Remove fsl_sai_remove()Xiubo Li2013-12-211-11/+0
| | | | | | | There is no need of this function and makes the code slightly shorter Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* ASoC: Add SAI SoC Digital Audio Interface driver.Xiubo Li2013-12-181-0/+492
This adds Freescale SAI ASoC Audio support. This implementation is only compatible with device tree definition. Features: o Supports playback/capture o Supports 16/20/24 bit PCM o Supports 8k - 96k sample rates o Supports master and slave mode. Signed-off-by: Alison Wang <b18965@freescale.com> Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
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