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path: root/sound/soc/codecs/tas2552.h
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* ASoC: tas2552: Fix off-by-one for max_register settingAxel Lin2015-07-231-1/+1
| | | | | | | | The latest valid register is TAS2552_VBAT_DATA. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Dan Murphy<dmurphy@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* ASoC: tas2552: Code, define alignment changes for uniformityPeter Ujfalusi2015-06-081-5/+5
| | | | | | | | | Align the numbers in the header file to the same column. At the same time change the wrapping of CFG_2 register write in the probe function to be uniform with the other calls. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* ASoC: tas2552: Correct Boost Auto-Pass Through Control register usagePeter Ujfalusi2015-06-081-11/+10
| | | | | | | | | Correct the bit definition so the code will change the bits what it supposed to change. Also rename the register define to TAS2552_BOOST_APT_CTRL. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* ASoC: tas2552: Correct Output Data register usagePeter Ujfalusi2015-06-081-4/+15
| | | | | | | | | | Do not write to DOUT Tristate register at probe time, specially not write data which is defined to be used in Output Data Register. Fix the defines for the Output Data Register and correct the register write at probe time. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* ASoC: tas2552: Correct the PLL configurationPeter Ujfalusi2015-06-081-7/+4
| | | | | | | | | | | | | | Do not restrict the sampling rate to 44.1/48KHz. The pll_clk clock should be (sampling rate * 512) in all cases. Correct the J.D calculation (the D part was incorrectly calculated). Restore PLL enable status after we are done with the configuration. Implement hardware constraint handling towards the pll_clkin: if D != 0 (in J.D) then 1.1MHz <= pll_clkin <= 9.2MHz needs to be checked. If the PLL setup does not met with this constraint, fall back to BCLK as reference clock, if BCLK fails, use the internal 1.8MHz clock. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* ASoC: tas2552: Configure the WCLK frequency based on the streamPeter Ujfalusi2015-06-051-19/+18
| | | | | | | | | | | Instead of hard wiring the WCLK frequency at probe time do it runtime. The hard wired 88_96KHz was not even setting the correct bits since it was defined as (1 << 6) which will change the I2S_OUT_SEL bit and will leave the amplifier configured for 8KHz. At the same time clean up and fix the CFG3 register bits. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* ASoC: tas2552: Add support for word length configurationPeter Ujfalusi2015-06-051-0/+10
| | | | | | | | | Configure the word length based on the params_width of the stream. Also configure the clock per frame value which is used when tas2552 is bus master. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* ASoC: tas2552: Add TDM supportPeter Ujfalusi2015-06-051-0/+3
| | | | | | | | TDM support is achieved using DSP transfer mode and setting a programmable offset which specifies where data begins with respect to the frame sync. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* ASoC: tas2552: Correct and clean up data format and BCLK/WCLK directionPeter Ujfalusi2015-06-051-9/+8
| | | | | | | | Use names from the datasheet for the definitions. Correct the data format definitions since they were not correct. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* ASoC: tas2552: Correct CFG1 register bit definitionsPeter Ujfalusi2015-06-041-9/+8
| | | | | | | | Remove the _MASK postfix of the bit definitions, collect the CFG1 bit definition in one place and correct the bit shifts at the same time. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* ASoC: tas2552: Correct PDM configuration register bit definitionsPeter Ujfalusi2015-06-041-6/+6
| | | | | | | | | | | | | The PDM clock can be selected via bit0-1. PDM_DATA_ES bit is at bit2. The code were trying to select BCLK as PDM reference clock but instead it was selecting PLL and set the DATA_ES bit to 1. Selecting the PLL output as reference clock as default does make sense, but the driver should not change the PDM data edge. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* ASoC: tas2552: Support TI TAS2552 AmplifierDan Murphy2014-07-171-0/+129
Support the TI TAS2552 Class D amplifier. The TAS2552 is a high efficiency Class-D audio power amplifier with advanced battery current management and an integrated Class-G boost The device constantly measures the current and voltage across the load and provides a digital stream of this information. Signed-off-by: Dan Murphy <dmurphy@ti.com> Signed-off-by: Mark Brown <broonie@linaro.org>
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