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| * [SPARC64]: Implement rest of generic interrupt hypervisor calls.David S. Miller2006-03-201-0/+24
| * [SPARC64]: Move devino_to_sysino out of pci_sun4v_asm.SDavid S. Miller2006-03-201-0/+5
| * [SPARC64]: Use inline patching for critical PTE operations.David S. Miller2006-03-201-3/+485
| * [SPARC64]: Move PTE field definitions back into asm/pgtable.hDavid S. Miller2006-03-201-2/+86
| * [SPARC64]: Recognize "virtual-console" as input and output console device.David S. Miller2006-03-202-0/+4
| * [SPARC64]: Deal with PTE layout differences in SUN4V.David S. Miller2006-03-201-194/+72
| * [SPARC64]: Register kernel TSB with hypervisor.David S. Miller2006-03-201-0/+1
| * [SPARC64]: Fix some SUN4V TLB miss bugs.David S. Miller2006-03-201-5/+5
| * [SPARC64]: Add SUN4V Hypervisor Console driver.David S. Miller2006-03-201-0/+3
| * [SPARC64]: Use ASI_SCRATCHPAD address 0x0 properly.David S. Miller2006-03-203-30/+31
| * [SPARC64]: Add HV_PCI_TSBID() macro.David S. Miller2006-03-201-0/+6
| * [SPARC64]: More SUN4V PCI controller work.David S. Miller2006-03-201-0/+3
| * [SPARC64]: Beginnings of SUN4V PCI controller support.David S. Miller2006-03-201-11/+45
| * [SPARC]: Clean up idprom header files.David S. Miller2006-03-202-28/+10
| * [SPARC64]: Hypervisor TSB context switching.David S. Miller2006-03-202-10/+16
| * [SPARC64]: Implement sun4v TSB miss handlers.David S. Miller2006-03-201-0/+20
| * [SPARC64]: Detect sun4v early in boot process.David S. Miller2006-03-202-0/+9
| * [SPARC64]: Sun4v cross-call sending support.David S. Miller2006-03-201-2/+12
| * [SPARC64]: Sun4v interrupt handling.David S. Miller2006-03-201-8/+14
| * [SPARC64]: Add sun4v mondo queue bases to struct trap_per_cpu.David S. Miller2006-03-201-8/+15
| * [SPARC64]: Fix some comment typos in asm/hypervisor.hDavid S. Miller2006-03-201-2/+4
| * [SPARC64]: Patch up mmu context register writes for sun4v.David S. Miller2006-03-201-5/+10
| * [SPARC64]: Register per-cpu fault status area with sun4v hypervisor.David S. Miller2006-03-201-0/+1
| * [SPARC64]: asm/cpudata.h needs asm/asi.hDavid S. Miller2006-03-201-1/+2
| * [SPARC64]: Rename gl_{1,2}insn_patch --> sun4v_{1,2}insn_patchDavid S. Miller2006-03-201-4/+7
| * [SPARC64]: Initial sun4v TLB miss handling infrastructure.David S. Miller2006-03-202-2/+17
| * [SPARC64]: Sanitize %pstate writes for sun4v.David S. Miller2006-03-201-0/+6
| * [SPARC64]: Kill all %pstate changes in context switch code.David S. Miller2006-03-201-5/+0
| * [SPARC64]: Add initial code to twiddle %gl on trap entry/exit.David S. Miller2006-03-202-0/+9
| * [SPARC64]: Add define for "GL" field of sun4v %tstate register.David S. Miller2006-03-201-2/+3
| * [SPARC64]: Add sun4v case to __GET_CPUID() patch tables.David S. Miller2006-03-201-0/+8
| * [SPARC64]: Sun4v interrupt queue register definitions.David S. Miller2006-03-201-0/+15
| * [SPARC64]: Sun4v scratchpad register layout.David S. Miller2006-03-201-0/+14
| * [SPARC64]: Sun4v specific ASI defines.David S. Miller2006-03-201-0/+9
| * [SPARC64]: Add Niagara init-store twin-load ASI defines.David S. Miller2006-03-201-1/+8
| * [SPARC64]: Add 'hypervisor' to ultra_tlb_type enumeration.David S. Miller2006-03-201-0/+1
| * [SPARC64]: SUN4V hypervisor interface defines.David S. Miller2006-03-201-0/+2072
| * [SPARC64]: Refine register window trap handling.David S. Miller2006-03-201-1/+233
| * [SPARC64]: Add explicit register args to trap state loading macros.David S. Miller2006-03-201-44/+44
| * [SPARC64]: Refine code sequences to get the cpu id.David S. Miller2006-03-203-47/+71
| * [SPARC64]: Correctable ECC errors cannot occur at trap level > 0.David S. Miller2006-03-201-6/+3
| * [SPARC64]: Access TSB with physical addresses when possible.David S. Miller2006-03-202-6/+91
| * [SPARC64]: Kill out-of-date commentary in asm-sparc64/tsb.hDavid S. Miller2006-03-201-8/+0
| * [SPARC64]: Fix race in LOAD_PER_CPU_BASE()David S. Miller2006-03-201-7/+12
| * [SPARC64]: Increase swapper_tsb size to 32K.David S. Miller2006-03-201-3/+10
| * [SPARC64]: Kill sole argument passed to setup_tba().David S. Miller2006-03-201-0/+1
| * [SPARC64]: Fix incorrect TSB lock bit handling.David S. Miller2006-03-201-2/+3
| * [SPARC64]: Preload TSB entries from update_mmu_cache().David S. Miller2006-03-201-0/+2
| * [SPARC64]: Dynamically grow TSB in response to RSS growth.David S. Miller2006-03-202-0/+8
| * [SPARC64]: Add infrastructure for dynamic TSB sizing.David S. Miller2006-03-203-6/+24
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