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* usb: ohci-at91: Forcibly suspend ports while USB suspendWenyou Yang2016-08-301-0/+14
| | | | | | | | | | | | | | | | | | | | | The usb controller does not manage correctly the suspend mode for the ehci. In echi mode, there is no way to suspend without any device connected to it. This is why this specific control is added to fix this issue. Since the suspend mode works in ohci mode, this specific control works by suspend the usb controller in ohci mode. This specific control is by setting the SUSPEND_A/B/C fields of SFR_OHCIICR(OHCI Interrupt Configuration Register) in the SFR while the OHCI USB suspend. This set operation must be done before the USB clock disabled, clear operation after the USB clock enabled. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Alan Stern <stern@rowland.harvard.edu> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* ARM: dts: at91: sama5d2: add SFR nodeCyrille Pitchen2016-03-291-0/+18
| | | | | | | | | | | This SFR node is looked up by the I2S controller driver to tune the SFR_I2SCLKSEL register. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
* ARM: at91: remove at91rm9200_sdramc.hAlexandre Belloni2015-05-201-63/+0
| | | | | | | | include/soc/at91/at91rm9200_sdramc.h is replaced by include/linux/mfd/syscon/atmel-smc.h as this is actually a syscon device. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
* pm: at91: Workaround DDRSDRC self-refresh bug with LPDDR1 memories.Peter Rosin2015-03-031-1/+1
| | | | | | | | | | | | | | | The DDRSDR controller fails miserably to put LPDDR1 memories in self-refresh. Force the controller to think it has DDR2 memories during the self-refresh period, as the DDR2 self-refresh spec is equivalent to LPDDR1, and is correctly implemented in the controller. Assume that the second controller has the same fault, but that is untested. Signed-off-by: Peter Rosin <peda@axentia.se> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
* ARM: at91: move sdramc/ddrsdr header to include/soc/at91Alexandre Belloni2014-11-133-0/+272
Move the (DDR) SDRAM controller headers to include/soc/at91 to remove the dependency on mach/ headers from the at91-reset driver. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
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