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* mtd: nand: increase max OOB size to 640Brian Norris2012-09-291-1/+1
| | | | | | | | | Some Hynix and Samsung MLC NAND have 640B OOB size. Sooner or later, we should dynamically allocate the buffers that use these macros. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: add helpers to get the supportted ONFI timing modeHuang Shijie2012-09-291-0/+25
| | | | | | | | | | | | | | add onfi_get_async_timing_mode() to get the supportted asynchronous timing mode. add onfi_get_sync_timing_mode() to get the supportted synchronous timing mode. Also add the neccessary macros : the timing modes. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: add helpers to set/get features for ONFI nandHuang Shijie2012-09-291-0/+14
| | | | | | | | | Add the set-features(0xef)/get-features(0xee) helpers for ONFI nand. Also add the necessary macros. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: nand: expand description of read_page method in comment headerMike Dunn2012-09-291-2/+4
| | | | | | | | | In the absence of any formal documentation of the nand interface, I thought this patch to the header file might be helpful. Signed-off-by: Mike Dunn <mikedunn@newsguy.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: nand: Added a device flag for subpage read supportJeff Westfahl2012-09-291-3/+4
| | | | | | | | | | | | Added a NAND device flag for subpage read support. Previously this was hard coded based on large page and soft ECC. Updated base NAND driver to use the new subpage read flag if the NAND is large page and soft ECC. Signed-off-by: Jeff Westfahl <jeff.westfahl@ni.com> Reviewed-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: fix kernel-doc warning in include/linux/mtd/nand.hRandy Dunlap2012-09-291-0/+1
| | | | | | | | | | | Fix kernel-doc warning in <linux/mtd/nand.h>: Warning(include/linux/mtd/nand.h:659): No description found for parameter 'read_byte' Signed-off-by: Randy Dunlap <rdunlap@xenotime.net> Acked-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: kill MTD_NAND_VERIFY_WRITEHuang Shijie2012-09-291-3/+0
| | | | | | | | | | | | | | | | Just as Artem suggested: "Both UBI and JFFS2 are able to read verify what they wrote already. There are also MTD tests which do this verification. So I think there is no reason to keep this in the NAND layer, let alone wasting RAM in the driver to support this feature. Besides, it does not work for sub-pages and many drivers have it broken. It hurts more than it provides benefits." So kill MTD_NAND_VERIFY_WRITE entirely. Signed-off-by: Huang Shijie <shijie8@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: nand: allow NAND_NO_SUBPAGE_WRITE to be set from driverBrian Norris2012-09-291-3/+0
| | | | | | | | | | | | | | | | | | | | The NAND_CHIPOPTIONS_MSK has limited utility and is causing real bugs. It silently masks off at least one flag that might be set by the driver (NAND_NO_SUBPAGE_WRITE). This breaks the GPMI NAND driver and possibly others. Really, as long as driver writers exercise a small amount of care with NAND_* options, this mask is not necessary at all; it was only here to prevent certain options from accidentally being set by the driver. But the original thought turns out to be a bad idea occasionally. Thus, kill it. Note, this patch fixes some major gpmi-nand breakage. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Tested-by: Huang Shijie <shijie8@gmail.com> Cc: stable@vger.kernel.org Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: nand: teach write_page and write_page_raw return an error codeJosh Wu2012-07-061-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | There is an implemention of hardware ECC write page function which may return an error indication. For instance, using Atmel HW PMECC to write one page into a nand flash, the hardware engine will compute the BCH ecc code for this page. so we need read a the status register to theck whether the ecc code is generated. But we cannot assume the status register always can be ready, for example, incorrect hardware configuration or hardware issue, in such case we need write_page() to return a error code. Since the definition of 'write_page' function in struct nand_ecc_ctrl is 'void'. So this patch will: 1. add return 'int' value for 'write_page' function. 2. to be consitent, add return 'int' value for 'write_page_raw' fuctions too. 3. add code to test the return value, and if negative, indicate an error happend when write page with ECC. 4. fix the compile warning in all impacted nand flash driver. Note: I couldn't compile-test all of these easily, as some had ARCH dependencies. Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: nand: kill NAND_NO_READRDYBrian Norris2012-07-061-6/+0
| | | | | | | | | | | According to its documentation, the NAND_NO_READRDY option is always used when autoincrement is not supported. Autoincrement support was recently dropped, so we can drop this options as well (defaulting to "no read ready check"). Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: nand: add Eon Silicon Solutions manufacturer IDBrian Norris2012-07-061-0/+1
| | | | | | | | Eon's new NAND flash: EN27LN1G08. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: nand: remove 'sndcmd' parameter of 'read_oob/read_oob_raw'Shmulik Ladkani2012-05-131-3/+2
| | | | | | | | | | | | | | As of [mtd: nand: remove autoincrement 'sndcmd' code], the NAND_CMD_READ0 command is issued unconditionally. Thus, read_oob/read_oob_raw's 'sndcmd' argument is no longer needed, as well as their return code. Remove the 'sndcmd' parameter, and set the return code to 0. Signed-off-by: Shmulik Ladkani <shmulik.ladkani@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: nand: add 'oob_required' argument to NAND {read,write}_page interfacesBrian Norris2012-05-131-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | New NAND controllers can perform read/write via HW engines which don't expose OOB data in their DMA mode. To reflect this, we should rework the nand_chip / nand_ecc_ctrl interfaces that assume that drivers will always read/write OOB data in the nand_chip.oob_poi buffer. A better interface includes a boolean argument that explicitly tells the callee when OOB data is requested by the calling layer (for reading/writing to/from nand_chip.oob_poi). This patch adds the 'oob_required' parameter to each relevant {read,write}_page interface; all 'oob_required' parameters are left unused for now. The next patch will set the parameter properly in the nand_base.c callers, and follow-up patches will make use of 'oob_required' in some of the callee functions. Note that currently, there is no harm in ignoring the 'oob_required' parameter and *always* utilizing nand_chip.oob_poi, but there can be performance/complexity/design benefits from avoiding filling oob_poi in the common case. I will try to implement this for some drivers which can be ported easily. Note: I couldn't compile-test all of these easily, as some had ARCH dependencies. [dwmw2: Merge later 1/0 vs. true/false cleanup] Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Shmulik Ladkani <shmulik.ladkani@gmail.com> Acked-by: Jiandong Zheng <jdzheng@broadcom.com> Acked-by: Mike Dunn <mikedunn@newsguy.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: add read_byte support to plat_nandJohn Crispin2012-05-131-0/+1
| | | | | | | | | | | Lantiq SoCs have a External Bus Unit (EBU) that is used to attach MTD media. As we need to co-exist with PCI on the same bus, certain swapping settings must be applied. Similar to the NOR map driver we need to apply a fix to make NAND work. The easiest way is to use byte reads. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: nand: kill NAND_NO_AUTOINCR optionBrian Norris2012-05-131-4/+1
| | | | | | | | No drivers use auto-increment NAND, so kill the NO_AUTOINCR option entirely. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: driver _read() returns max_bitflips; mtd_read() returns -EUCLEANMike Dunn2012-05-131-0/+3
| | | | | | | | | | | | | | | | | | | | | | | The drivers' _read() method, absent an error, returns a non-negative integer indicating the maximum number of bit errors that were corrected in any one region comprising an ecc step. MTD returns -EUCLEAN if this is >= bitflip_threshold, 0 otherwise. If bitflip_threshold is zero, the comparison is not made since these devices lack ECC and always return zero in the non-error case (thanks Brian)¹. Note that this is a subtle change to the driver interface. This and the preceding patches in this set were tested with ubi on top of the nandsim and docg4 devices, running the ubi test io_basic from mtd-utils. ¹ http://lists.infradead.org/pipermail/linux-mtd/2012-March/040468.html Signed-off-by: Mike Dunn <mikedunn@newsguy.com> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Acked-by: Brian Norris <computersforpeace@gmail.com> Ivan Djelic <ivan.djelic@parrot.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: add ecc_strength fields to mtd structsMike Dunn2012-03-271-0/+2
| | | | | | | | | | | | | This adds 'ecc_strength' to struct mtd_info. This stores the maximum number of bit errors that can be corrected in one writesize region. For consistency with the nand code, 'strength' is similiarly added to struct nand_ecc_ctrl. This stores the maximum number of bit errors that can be corrected in one ecc step. Signed-off-by: Mike Dunn <mikedunn@newsguy.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: nand: correct comment on nand_chip badblockbitsBrian Norris2012-03-271-2/+3
| | | | | | | | | The description for badblockbits is incorrect. I think someone just made up a false description on the spot to satisfy some kerneldoc warning. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: nand: add Macronix manufacturerBrian Norris2012-01-091-0/+1
| | | | | | | | | Macronix is produing SLC NAND MX30LF1208AA, so add their manufacturer code to the manufacturer lists. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: nand: kill member `ops' of `struct nand_chip'Brian Norris2011-09-111-3/+0
| | | | | | | | | | The nand_chip.ops field is a struct that is passed around globally with no particular reason. Every time it is used, it could just as easily be replaced with a local struct that is updated on each operation. So make it local. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@intel.com>
* mtd: support reading OOB without ECCBrian Norris2011-09-111-0/+3
| | | | | | | | | | | | | | | | | | | | | | This fixes issues with `nanddump -n' and the MEMREADOOB[64] ioctls on hardware that performs error correction when reading only OOB data. A driver for such hardware needs to know when we're doing a RAW vs. a normal write, but mtd_do_read_oob does not pass such information to the lower layers (e.g., NAND). We should pass MTD_OOB_RAW or MTD_OOB_PLACE based on the MTD file mode. For now, most drivers can get away with just setting: chip->ecc.read_oob_raw = chip->ecc.read_oob This is done by default; but for systems that behave as described above, you must supply your own replacement function. This was tested with nandsim as well as on actual SLC NAND. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Cc: Jim Quinlan <jim2101024@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@intel.com>
* mtd: nand: document nand_chip.oob_poiBrian Norris2011-09-111-1/+2
| | | | | Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@intel.com>
* mtd: support writing OOB without ECCBrian Norris2011-09-111-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes issues with `nandwrite -n -o' and the MEMWRITEOOB[64] ioctls on hardware that writes ECC when writing OOB. The problem arises as follows: `nandwrite -n' can write page data to flash without applying ECC, but when used with the `-o' option, ECC is applied (incorrectly), contrary to the `--noecc' option. I found that this is the case because my hardware computes and writes ECC data to flash upon either OOB write or page write. Thus, to support a proper "no ECC" write, my driver must know when we're performing a raw OOB write vs. a normal ECC OOB write. However, MTD does not pass any raw mode information to the write_oob functions. This patch addresses the problems by: 1) Passing MTD_OOB_RAW down to lower layers, instead of just defaulting to MTD_OOB_PLACE 2) Handling MTD_OOB_RAW within the NAND layer's `nand_do_write_oob' 3) Adding a new (replaceable) function pointer in struct ecc_ctrl; this function should support writing OOB without ECC data. Current hardware often can use the same OOB write function when writing either with or without ECC This was tested with nandsim as well as on actual SLC NAND. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Cc: Jim Quinlan <jim2101024@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@intel.com>
* mtd: nand: fix spelling error (date => data)Brian Norris2011-09-111-1/+1
| | | | | Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@intel.com>
* mtd: plat-nand: Fixup kerneldoc for struct platform_nand_chipTobias Klauser2011-09-111-2/+0
| | | | | | | | | The set_parts and priv members of struct platform_nand_chip where removed in commit c36a6ef3845262ade529afb9f458738b1f196f83 but the kerneldoc wasn't updated. Signed-off-by: Tobias Klauser <tklauser@distanz.ch> Signed-off-by: Artem Bityutskiy <dedekind1@gmail.com>
* mtd: spelling, capitalization, uniformityBrian Norris2011-09-111-25/+25
| | | | | | | | | | | | | | | | | | | | Therefor -> Therefore [Intern], [Internal] -> [INTERN] [REPLACABLE] -> [REPLACEABLE] syndrom, syndom -> syndrome ecc -> ECC buswith -> buswidth endianess -> endianness dont -> don't occures -> occurs independend -> independent wihin -> within erease -> erase blockes -> blocks ... Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com>
* mtd: plat-nand: drop unused fields from platform_nand_dataDmitry Eremin-Solenikov2011-09-111-2/+0
| | | | | | | | Drop now unused set_parts from struct platform_nand_data. Also, while we are at it, drop long unused priv field from platform_nand_data. Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com>
* mtd: nand: renumber the reorganized flags in nand.h / bbm.hBrian Norris2011-09-111-3/+3
| | | | | | | | | After several steps of rearrangement and consolidation, it is probably worth re-sequencing the numbers on some of our affected flags in nand.h and bbm.h. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com>
* mtd: nand: move NAND_CREATE_EMPTY_BBT flagBrian Norris2011-09-111-2/+0
| | | | | | | | | | | | | | | The NAND_CREATE_EMPTY_BBT flag was added by commit: 453281a973c10bce941b240d1c654d536623b16b mtd: nand: introduce NAND_CREATE_EMPTY_BBT This flag is not used within the kernel and not explained well, so I took the liberty to edit its comments. Also, this is a BBT-related flag (and closely tied with NAND_BBT_CREATE) so I'm moving it to bbm.h next to NAND_BBT_CREATE, thus requiring that we use the flag in nand_chip.bbt_options, *not* in nand_chip.options. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com>
* mtd: nand: consolidate redundant flash-based BBT flagsBrian Norris2011-09-111-10/+2
| | | | | | | | | | | | | | | | | | | | | | | | | This patch works with the following three flags from two headers (nand.h and bbm.h): (1) NAND_USE_FLASH_BBT (nand.h) (2) NAND_USE_FLASH_BBT_NO_OOB (nand.h) (3) NAND_BBT_NO_OOB (bbm.h) These flags are all related and interdependent, yet they were in different headers. Flag (2) is simply the combination of (1) and (3) and can be eliminated. This patch accomplishes the following: * eliminate NAND_USE_FLASH_BBT_NO_OOB (i.e., flag (2)) * move NAND_USE_FLASH_BBT (i.e., flag (1)) to bbm.h It's important to note that because (1) and (3) are now both found in bbm.h, they should NOT be used in the "nand_chip.options" field. I removed a small section from the mtdnand DocBook because it referes to NAND_USE_FLASH_BBT in nand.h, which has been moved to bbm.h. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com>
* mtd: nand: separate chip options / bbt_optionsBrian Norris2011-09-111-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch handles the problems we've been having with using conflicting flags from nand.h and bbm.h in the same nand_chip.options field. We should try to separate these two spaces a little more clearly, and so I have added a bbt_options field to nand_chip. Important notes about nand_chip fields: * bbt_options field should contain ONLY flags from bbm.h. They should be able to pass safely to a nand_bbt_descr data structure. - BBT option flags start with the "NAND_BBT_" prefix. * options field should contian ONLY flags from nand.h. Ideally, they should not be involved in any BBT related options. - NAND chip option flags start with the "NAND_" prefix. * Every flag should have a nice comment explaining what the flag is. While this is not yet the case on all existing flags, please be sure to write one for new flags. Even better, you can help document the code better yourself! Please try to follow these conventions to make everyone's lives easier. Among the flags that are being moved to the new bbt_options field throughout various drivers, etc. are: * NAND_BBT_SCANLASTPAGE * NAND_BBT_SCAN2NDPAGE and there will be more to come. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com>
* mtd: nand: renumber conflicting BBT flagsBrian Norris2011-05-251-2/+2
| | | | | | | | | | | The NAND_USE_FLASH_BBT_NO_OOB and NAND_CREATE_EMPTY_BBT flags conflict with the NAND_BBT_SCANBYTE1AND6 and NAND_BBT_DYNAMICSTRUCT flags, respectively. This change will allow us to utilize these options independently. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* Fix common misspellingsLucas De Marchi2011-03-311-3/+3
| | | | | | Fixes generated by 'codespell' and manually reviewed. Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi>
* mtd: nand: add software BCH ECC supportIvan Djelic2011-03-111-0/+3
| | | | | | | | | | | | | | | | | | | This patch adds software BCH ECC support to mtd, in order to handle recent NAND device ecc requirements (4 bits or more). It does so by adding a new ecc mode (NAND_ECC_SOFT_BCH) for use by board drivers, and a new Kconfig option to enable BCH support. It relies on the generic BCH library introduced in a previous patch. When a board driver uses mode NAND_ECC_SOFT_BCH, it should also set fields chip->ecc.size and chip->ecc.bytes to select BCH ecc data size and required error correction capability. See nand_bch_init() documentation for details. It has been tested on the following platforms using mtd-utils, UBI and UBIFS: x86 (with nandsim), arm926ejs. Signed-off-by: Ivan Djelic <ivan.djelic@parrot.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: fix nand kernel-doc warningsRandy Dunlap2010-12-031-0/+2
| | | | | | | | | | | Warning(include/linux/mtd/nand.h:543): No description found for parameter 'badblockbits' Warning(drivers/mtd/nand/nand_bbt.c:1101): No description found for parameter 'mtd' Signed-off-by: Randy Dunlap <randy.dunlap@oracle.com> Cc: David Woodhouse <dwmw2@infradead.org> Cc: linux-mtd@lists.infradead.org Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: remove junk tabs in nand.hSebastian Andrzej Siewior2010-10-251-168/+147
| | | | | | | | Remove tabs between type and name. Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: cleanup nand.hSebastian Andrzej Siewior2010-10-251-56/+99
| | | | | | | | | | | | | | | - *var instead of * var - proper multiline comment - func(args) instead of func (args) - 80 lines So from |total: 2 errors, 37 warnings, 654 lines checked we got to one warning. Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: nand: introduce NAND_CREATE_EMPTY_BBTSebastian Andrzej Siewior2010-10-251-0/+2
| | | | | | | | | | it will create an empty BBT table without considering vendor's BBT information. Vendor's information may be unavailable if the NAND controller has a different DATA & OOB layout or this information may be allready purged. Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: nand: add support for BBT without OOBSebastian Andrzej Siewior2010-10-251-2/+9
| | | | | | | | | | | | | | | | | | The first (sixt) byte in the OOB area contains vendor's bad block information. During identification of the NAND chip this information is collected by scanning the complete chip. The option NAND_USE_FLASH_BBT is used to store this information in a sector so we don't have to scan the complete flash. Unfortunately the code stores a marker in order to recognize the BBT in the OOB area. This will fail if the OOB area is completely used for ECC. This patch introduces the option NAND_USE_FLASH_BBT_NO_OOB which has to be used with NAND_USE_FLASH_BBT. It will then store BBT on flash without touching the OOB area. The BBT format on flash remains same except the first page starts with the recognition pattern followed by the version byte. This change was tested in nandsim and it looks good so far :) Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: add init_size hook for NAND driverHuang Shijie2010-10-251-0/+6
| | | | | | | | | | | | | | | Not all the NAND devices have all the information in additional id bytes. So add a hook in the nand_chip{} is a good method to calculate the right value of oobsize, erasesize and so on. Without the hook,you will get the wrong value, and you have to hack in the ->scan_bbt() to change the wrong value which make the code mess. Signed-off-by: Huang Shijie <shijie8@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: nand: add support for reading ONFI parameters from NAND deviceFlorian Fainelli2010-10-241-0/+68
| | | | | | | | | | | | | | This patch adds support for reading NAND device ONFI parameters and use the ONFI informations to define its geometry. In case the device supports ONFI, the onfi_version field in struct nand_chip contains the version (BCD) and the onfi_params structure can be used by drivers to set up timings and such. We currently only support ONFI 1.0 parameters. Signed-off-by: Brian Norris <norris@broadcom.com> Signed-off-by: Matthieu Castet <matthieu.castet@parrot.com> Signed-off-by: Maxime Bizon <mbizon@freebox.fr> Signed-off-by: Florian Fainelli <ffainelli@freebox.fr> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: nand: add NAND_CMD_PARAM (0xec) definitionFlorian Fainelli2010-10-241-0/+1
| | | | | | | This command is used to read the device ONFI parameters page. Signed-off-by: Florian Fainelli <ffainelli@freebox.fr> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: nand: Increase NAND_MAX_OOBSIZEBrian Norris2010-10-241-2/+2
| | | | | | | | | | | | An increase in NAND_MAX_OOBSIZE and NAND_MAX_PAGESIZE is necessary in order to support many new chips. Among those: Toshiba TC58TxG4S2FBAxx 8KB page, 576B OOB Micron MT29F64G08CBAAA 8KB page, 448B OOB Signed-off-by: Brian Norris <norris@broadcom.com> Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: Update copyright noticesDavid Woodhouse2010-08-081-3/+3
| | | | Signed-off-by: David Woodhouse <dwmw2@infradead.org>
* mtd: nand: edit macro flag for BBT scan of last page in blockBrian Norris2010-08-021-2/+0
| | | | | | | | | | | | NAND_BB_LAST_PAGE used to be in nand.h, but it pertained to bad block management and so belongs next to NAND_BBT_SCAN2NDPAGE in bbm.h. Also, its previous flag value (0x00000400) conflicted with NAND_BBT_SCANALLPAGES so I changed its value to 0x00008000. All uses of the name were modified to provide consistency with other "NAND_BBT_*" flags. Signed-off-by: Brian Norris <norris@broadcom.com> Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: nand: support alternate BB marker locations on MLCKevin Cernekee2010-05-141-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a slightly modified version of a patch submitted last year by Reuben Dowle <reuben.dowle@navico.com>. His original comments follow: This patch adds support for some MLC NAND flashes that place the BB marker in the LAST page of the bad block rather than the FIRST page used for SLC NAND and other types of MLC nand. Lifted from Samsung datasheet for K9LG8G08U0A (1Gbyte MLC NAND): " Identifying Initial Invalid Block(s) All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The initial invalid block(s) status is defined by the 1st byte in the spare area. Samsung makes sure that the last page of every initial invalid block has non-FFh data at the column address of 2,048. ... " As far as I can tell, this is the same for all Samsung MLC nand, and in fact the samsung bsp for the processor used in our project (s3c6410) actually contained a hack similar to this patch but less portable to enable use of their NAND parts. I discovered this problem when trying to use a Micron NAND which does not used this layout - I wish samsung would put their stuff in main-line to avoid this type of problem. Currently this patch causes all MLC nand with manufacturer codes from Samsung and ST(Numonyx) to use this alternative location, since these are the manufactures that I know of that use this layout. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: nand: extend NAND flash detection to new MLC chipsKevin Cernekee2010-05-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some of the newer MLC devices have a 6-byte ID sequence in which several field definitions differ from older chips in a manner that is not backward compatible. For instance: Samsung K9GAG08U0M (5-byte sequence): ec d5 14 b6 74 4th byte, bits 1:0 encode the page size: 0=1KiB, 1=2KiB, 2=4KiB, 3=8KiB 4th byte, bits 5:4 encode the block size: 0=64KiB, 1=128KiB, ... 4th byte, bit 6 encodes the OOB size: 0=8B/512B, 1=16B/512B Samsung K9GAG08U0D (6-byte sequence): ec d5 94 29 34 41 4th byte, bits 1:0 encode the page size: 0=2KiB, 1=4KiB, 3=8KiB, 4=rsvd 4th byte, bits 7;5:4 encode the block size: 0=128KiB, 1=256KiB, ... 4th byte, bits 6;3:2 encode the OOB size: 1=128B/page, 2=218B/page This patch uses the new 6-byte scheme if the following conditions are all true: 1) The ID code wraps around after exactly 6 bytes 2) Manufacturer is Samsung 3) 6th byte is zero The patch also extends the maximum OOB size from 128B to 256B. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: Workaround wrong write protect status on some xD cardsMaxim Levitsky2010-02-261-0/+6
| | | | | Signed-off-by: Maxim Levitsky <maximlevitsky@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: nand: Allow caller to pass alternative ID table to nand_scan_ident()David Woodhouse2010-02-261-1/+3
| | | | Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: nand: add ->badblockbits for minimum number of set bits in bad block byteMaxim Levitsky2010-02-261-0/+1
| | | | | | | | This can be used to protect against bitflips in that field, but now mostly for smartmedia. Signed-off-by: Maxim Levitsky <maximlevitsky@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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