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* clk: at91: add audio pll clock driversQuentin Schulz2017-09-011-0/+25
| | | | | | | | | | | | | | | | | | | This new clock driver set allows to have a fractional divided clock that would generate a precise clock particularly suitable for audio applications. The main audio pll clock has two children clocks: one that is connected to the PMC, the other that can directly drive a pad. As these two routes have different enable bits and different dividers and divider formulas, they are handled by two different drivers. Each of them could modify the rate of the main audio pll parent. The main audio pll clock can output 620MHz to 700MHz. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: at91: pmc: drop at91_pmc_baseAlexandre Belloni2016-02-171-12/+0
| | | | | | | | | at91_pmc_base is not used anymore, remove it along with at91_pmc_read and at91_pmc_write. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: at91: add generated clock driverNicolas Ferre2015-10-011-0/+7
| | | | | | | | | | | | | | Add a new type of clocks that can be provided to a peripheral. In addition to the peripheral clock, this new clock that can use several input clocks as parents can generate divided rates. This would allow a peripheral to have finer grained clocks for generating a baud rate, clocking an asynchronous part or having more options in frequency. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> [sboyd@codeaurora.org: Transition to new clk_hw provider APIs] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: at91: add PMC sama5d2 supportNicolas Ferre2015-10-011-0/+1
| | | | | | | | Add support for the new sama5d2 SoC and adapt capabilities. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: at91: cleanup PMC header file for PCR register fieldsNicolas Ferre2015-10-011-8/+6
| | | | | | | | Add _MASK and _OFFSET values and cleanup register fields layout. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: at91: change to using endian agnositc IOBen Dooks2015-04-111-2/+2
| | | | | | | | | | | | | | Change to using endian agnostic _relaxed IO accessors instead of __raw Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> -- CC: Andrew Victor <linux@maxim.org.za> CC: Nicolas Ferre <nicolas.ferre@atmel.com> CC: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com> CC: Mike Turquette <mturquette@linaro.org> (maintainer:COMMON CLK FRAMEWORK) CC: Stephen Boyd <sboyd@codeaurora.org> (maintainer:COMMON CLK FRAMEWORK) CC: linux-kernel@vger.kernel.org (open list:COMMON CLK FRAMEWORK) Signed-off-by: Michael Turquette <mturquette@linaro.org>
* clk: at91: add a driver for the h32mx clockAlexandre Belloni2014-09-221-0/+1
| | | | | | | | | | Newer SoCs have two different AHB interconnect. The AHB 32 bits Matrix interconnect (h32mx) has a clock that can be setup at the half of the h64mx clock (which is mck). The h32mx clock can not exceed 90 MHz. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
* clk: at91: add slow clks driverBoris BREZILLON2014-05-071-0/+1
| | | | | | | | | | | | | | | AT91 slow clk is a clk multiplexer. In some SoCs (sam9x5, sama5, sam9g45 families) this multiplexer can choose among 2 sources: an internal RC oscillator circuit and an oscillator using an external crystal. In other Socs (sam9260 family) the multiplexer source is hardcoded with the OSCSEL signal. Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
* clk: at91: add PMC pll clocksBoris BREZILLON2013-12-021-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds new at91 pll clock implementation using common clk framework. The pll clock layout describe the PLLX register layout. There are four pll clock layouts: - at91rm9200 - at91sam9g20 - at91sam9g45 - sama5d3 PLL clocks are given characteristics: - min/max clock source rate - ranges of valid clock output rates - values to set in out and icpll fields for each supported output range These characteristics are checked during rate change to avoid over/underclocking. These characteristics are described in atmel's SoC datasheet in "Electrical Characteristics" paragraph. Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
* ARM: at91: move at91_pmc.h to include/linux/clk/at91_pmc.hBoris BREZILLON2013-12-021-0/+190
This patch moves at91_pmc.h header from machine specific directory (arch/arm/mach-at91/include/mach/at91_pmc.h) to clk include directory (include/linux/clk/at91_pmc.h). We need this to avoid reference to machine specific headers in clk drivers. Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Acked-by: Felipe Balbi <balbi@ti.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
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