| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | clk: renesas: Add r8a77990 CPG Core Clock Definitions | Takeshi Kihara | 2018-04-24 | 1 | -0/+62 |
| This patch adds all R-Car E3 Clock Pulse Generator Core Clock Outputs. Note that internal CPG clocks (S0, S1, S2, S3, SDSRC, POST3) are not included, as they are used as internal clock sources only, and never referenced from DT. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [shimoda: add SPDX-License-Identifier] Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> | |||||
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index : op-kernel-dev | |
| Development kernel branch for OpenPOWER systems | Raptor Engineering, LLC |
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