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* [POWERPC] QEIC: Implement pluggable handlers, fix MPIC cascadingAnton Vorontsov2007-10-081-1/+67
| | | | | | | | | | | | | | | | | | | | | | | | | set_irq_chained_handler overwrites MPIC's handle_irq function (handle_fasteoi_irq) thus MPIC never gets eoi event from the cascaded IRQ. This situation hangs MPIC on MPC8568E. To solve this problem efficiently, QEIC needs pluggable handlers, specific to the underlaying interrupt controller. Patch extends qe_ic_init() function to accept low and high interrupt handlers. To avoid #ifdefs, stack of interrupt handlers specified in the header file and functions are marked 'static inline', thus handlers are compiled-in only if actually used (in the board file). Another option would be to lookup for parent controller and automatically detect handlers (will waste text size because of never used handlers, so this option abolished). qe_ic_init() also changed in regard to support multiplexed high/low lines as found in MPC8568E-MDS, plus qe_ic_cascade_muxed_mpic() handler implemented appropriately. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] 86xx: update immap_86xx.h for the 8610Timur Tabi2007-10-081-8/+78
| | | | | | | | Update the definition of the global utilities structure (ccsr_guts) in immap_86xx.h and add some related macros for the Freescale 8610 SOC. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] qe: miscellaneous code improvements and fixes to the QE libraryTimur Tabi2007-10-084-129/+193
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes numerous miscellaneous code improvements to the QE library. 1. Remove struct ucc_common and merge ucc_init_guemr() into ucc_set_type() (every caller of ucc_init_guemr() also calls ucc_set_type()). Modify all callers of ucc_set_type() accordingly. 2. Remove the unused enum ucc_pram_initial_offset. 3. Refactor qe_setbrg(), also implement work-around for errata QE_General4. 4. Several printk() calls were missing the terminating \n. 5. Add __iomem where needed, and change u16 to __be16 and u32 to __be32 where appropriate. 6. In ucc_slow_init() the RBASE and TBASE registers in the PRAM were programmed with the wrong value. 7. Add the protocol type to struct us_info and updated ucc_slow_init() to use it, instead of always programming QE_CR_PROTOCOL_UNSPECIFIED. 8. Rename ucc_slow_restart_x() to ucc_slow_restart_tx() 9. Add several macros in qe.h (mostly for slow UCC support, but also to standardize some naming convention) and remove several unused macros. 10. Update ucc_geth.c to use the new macros. 11. Add ucc_slow_info.protocol to specify which QE_CR_PROTOCOL_xxx protcol to use when initializing the UCC in ucc_slow_init(). 12. Rename ucc_slow_pram.rfcr to rbmr and ucc_slow_pram.tfcr to tbmr, since these are the real names of the registers. 13. Use the setbits, clrbits, and clrsetbits where appropriate. 14. Refactor ucc_set_qe_mux_rxtx(). 15. Remove all instances of 'volatile'. 16. Simplify get_cmxucr_reg(); 17. Replace qe_mux.cmxucrX with qe_mux.cmxucr[]. 18. Updated struct ucc_geth because struct ucc_fast is not padded any more. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] cpm: Describe multi-user ram in its own device node.Scott Wood2007-10-043-0/+36
| | | | | | | | | | | | | | | | | | | | | The way the current CPM binding describes available multi-user (a.k.a. dual-ported) RAM doesn't work well when there are multiple free regions, and it doesn't work at all if the region doesn't begin at the start of the muram area (as the hardware needs to be programmed with offsets into this area). The latter situation can happen with SMC UARTs on CPM2, as its parameter RAM is relocatable, u-boot puts it at zero, and the kernel doesn't support moving it. It is now described with a muram node, similar to QE. The current CPM binding is sufficiently recent (i.e. never appeared in an official release) that compatibility with existing device trees is not an issue. The code supporting the new binding is shared between cpm1 and cpm2, rather than remain separated. QE should be able to use this code as well, once minor fixes are made to its device trees. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] QE: Added missing CEURNR registerEmil Medve2007-10-041-2/+3
| | | | | | | | | | According to the publicly available MPC8360E RM (rev. 1 from 09/2006 and rev. 2 from 05/2007) and MPC8323E RM (rev. 1 from 09/2006), CEURNR is the QE microcode revision number register and is located at offset 0x1b8 within the QE internal register space Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] mpc82xx: Define CPU_FTR_NEED_COHERENTScott Wood2007-10-041-5/+5
| | | | | | | | The 8272 (and presumably other PCI PQ2 chips) appear to have the same issue as the 83xx regarding PCI streaming DMA. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] cpm2: Add cpm2_set_pin().Scott Wood2007-10-041-0/+9
| | | | | | | | This provides a generic way for board code to set up CPM pins, rather than directly poking magic values into registers. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] cpm2: Add SCCs to cpm2_clk_setup(), and cpm2_smc_clk_setup().Scott Wood2007-10-041-1/+4
| | | | | Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] cpm2: Infrastructure code cleanup.Scott Wood2007-10-043-18/+7
| | | | | | | | Mostly sparse fixes (__iomem annotations, etc); also, cpm2_immr is used rather than creating many temporary mappings. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] 8xx: Add pin and clock setting functions.Scott Wood2007-10-031-0/+49
| | | | | | | | | | | These let board code set up pins and clocks without having to put magic numbers directly into the registers. The clock function is mostly duplicated from the cpm2 version; hopefully this stuff can be merged at some point. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] 8xx: Infrastructure code cleanup.Scott Wood2007-10-032-16/+7
| | | | | | | | | | | | | | | | | | | | | 1. Keep a global mpc8xx_immr mapping, rather than constantly creating temporary mappings. 2. Look for new fsl,cpm1 and fsl,cpm1-pic names. 3. Always reset the CPM when not using the udbg console; this is required in case the firmware initialized a device that is incompatible with one that the kernel is about to use. 4. Remove some superfluous casts and header includes. 5. Change a usage of IMAP_ADDR to get_immrbase(). 6. Use phys_addr_t, not uint, for dpram_pbase. 7. Various sparse-related fixes, such as __iomem annotations. 8. Remove mpc8xx_show_cpuinfo, which doesn't provide anything useful beyond the generic cpuinfo handler. 9. Move prototypes for 8xx support functions from board files to sysdev/commproc.h. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] Add early debug console for CPM serial ports.Scott Wood2007-10-031-0/+1
| | | | | | | | | This code assumes that the ports have been previously set up, with buffers in DPRAM. Signed-off-by: Scott Wood <scottwood@freescale.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] Virtex: add xilinx interrupt controller driverGrant Likely2007-10-031-0/+20
| | | | | | | Adds support for the Xilinx opb-intc interrupt controller Signed-off-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* [POWERPC] Implement clockevents driver for powerpcTony Breeds2007-10-031-0/+1
| | | | | | | | | | | | This registers a clock event structure for the decrementer and turns on CONFIG_GENERIC_CLOCKEVENTS, which means that we now don't need most of timer_interrupt(), since the work is done in generic code. For secondary CPUs, their decrementer clockevent is registered when the CPU comes up (the generic code automatically removes the clockevent when the CPU goes down). Signed-off-by: Tony Breeds <tony@bakeyournoodle.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Celleb: New HTAB Guest OS Interface on BeatIshizaki Kou2007-10-031-0/+1
| | | | | | | | | | This changes the Celleb code to work with new Guest OS Interface to tweak HTAB on Beat. It detects old and new Guest OS Interfaces automatically. Signed-off-by: Kou Ishizaki <Kou.Ishizaki@toshiba.co.jp> Acked-by: Arnd Bergmann <arnd.bergmann@de.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Update mpic to use dcr_host_t.baseMichael Ellerman2007-10-031-6/+0
| | | | | | | | | Now that dcr_host_t contains the base address, we can use that in the mpic code, rather than storing it separately. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Store the base address in dcr_host_tMichael Ellerman2007-10-032-3/+9
| | | | | | | | | | In its current form, dcr_map() doesn't remember the base address you passed it, which means you need to store it somewhere else. Rather than adding the base to another struct it seems simpler to store it in the dcr_host_t. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Include pagemap.h in asm/powerpc/tlb.hMathieu Desnoyers2007-10-031-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes this powerpc build error in 2.6.22-rc6-mm1 for powerpc 64 with CONFIG_SWAP=n : In file included from include2/asm/tlb.h:60, from /home/compudj/git/linux-2.6-lttng/arch/powerpc/mm/init_64. c:56: /home/compudj/git/linux-2.6-lttng/include/asm-generic/tlb.h: In function 'tlb_flush_mmu': /home/compudj/git/linux-2.6-lttng/include/asm-generic/tlb.h:76: error: implicit declaration of function 'release_pages' /home/compudj/git/linux-2.6-lttng/include/asm-generic/tlb.h: In function 'tlb_remove_page': /home/compudj/git/linux-2.6-lttng/include/asm-generic/tlb.h:105: error: implicit declaration of function 'page_cache_release' make[2]: *** [arch/powerpc/mm/init_64.o] Error 1 release_pages is declared in linux/pagemap.h, but cannot be included in linux/swap.h because of a sparc related comment: /* only sparc can not include linux/pagemap.h in this file * so leave page_cache_release and release_pages undeclared... */ #define free_page_and_swap_cache(page) \ page_cache_release(page) #define free_pages_and_swap_cache(pages, nr) \ release_pages((pages), (nr), 0); Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] ppc64: support CONFIG_DEBUG_PREEMPTHugh Dickins2007-10-034-3/+14
| | | | | | | | | | | | | | | | | | | Add CONFIG_DEBUG_PREEMPT support to ppc64: it was useful for testing get_paca() preemption. Cheat a little, just use debug_smp_processor_id() in the debug version of get_paca(): it contains all the right checks and reporting, though get_paca() doesn't really use smp_processor_id(). Use local_paca for what might have been called __raw_get_paca(). Silence harmless warnings from io.h and lparcfg.c with local_paca - it is okay for iseries_lparcfg_data to be referencing shared_proc with preemption enabled: all cpus should show the same value for shared_proc. Why do other architectures need TRACE_IRQFLAGS_SUPPORT for DEBUG_PREEMPT? I don't know, ppc64 appears to get along fine without it. Signed-off-by: Hugh Dickins <hugh@veritas.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Limit range of __init_ref_ok somewhatStephen Rothwell2007-10-031-0/+1
| | | | | | | | This patch introduces zalloc_maybe_bootmem and uses it so that we don't have to mark a whole (largish) routine as __init_ref_ok. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Make vio_bus_type staticStephen Rothwell2007-10-031-1/+0
| | | | | Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] clk.h interface for platformsDomen Puncer2007-10-031-0/+20
| | | | | | | | | | This provides an implementation of the <linux/clk.h> interface for arch/powerpc using a set of function pointers in clk_functions. Platforms that want to support this interface should fill clk_functions and select CONFIG_PPC_CLOCK in Kconfig. Signed-off-by: Domen Puncer <domen.puncer@telargo.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Prevent direct inclusion of <asm/rwsem.h>.Robert P. J. Day2007-09-221-0/+4
| | | | | Signed-off-by: Robert P. J. Day <rpjday@mindspring.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Use __attribute__ in asm-powerpcMike Frysinger2007-09-222-3/+3
| | | | | | | | | | Pretty much everyone uses "__attribute__" or "attribute", no one uses "__attribute". This tweaks the three places in asm-powerpc where this comes up. While only asm-powerpc/types.h is interesting (for userspace), I did asm-powerpc/processor.h as well for consistency. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* Merge branch 'linux-2.6'Paul Mackerras2007-09-201-0/+5
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| * [POWERPC] Fix timekeeping on PowerPC 601Benjamin Herrenschmidt2007-09-191-0/+5
| | | | | | | | | | | | | | | | | | | | | | Recent changes to the timekeeping code broke support for the PowerPC 601 processor which doesn't have the usual timebase facility but a slightly different thing called (yuck) the RTC. This fixes it, boot tested on an old 601 based PowerMac 7200. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* | [POWERPC] Size swapper_pg_dir correctlyStephen Rothwell2007-09-192-0/+4
| | | | | | | | | | | | | | | | | | David Gibson pointed out that swapper_pg_dir actually need to be PGD_TABLE_SIZE bytes long not PAGE_SIZE. This actually saves 64k in the bss for a kernel ppc64_defconfig built with CONFIG_PPC_64K_PAGES. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
* | [POWERPC] Fix section mismatch in PCI codeStephen Rothwell2007-09-191-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Create a helper function (alloc_maybe_bootmem) that is marked __init_refok to limit the chances of mistakenly referring to other __init routines. WARNING: vmlinux.o(.text+0x2a9c4): Section mismatch: reference to .init.text:.__alloc_bootmem (between '.update_dn_pci_info' and '.pci_dn_reconfig_notifier') WARNING: vmlinux.o(.text+0x36430): Section mismatch: reference to .init.text:.__alloc_bootmem (between '.mpic_msi_init_allocator' and '.find_ht_magic_addr') WARNING: vmlinux.o(.text+0x5e804): Section mismatch: reference to .init.text:.__alloc_bootmem (between '.celleb_setup_phb' and '.celleb_fake_pci_write_config') WARNING: vmlinux.o(.text+0x5e8e8): Section mismatch: reference to .init.text:.__alloc_bootmem (between '.celleb_setup_phb' and '.celleb_fake_pci_write_config') WARNING: vmlinux.o(.text+0x5e968): Section mismatch: reference to .init.text:.__alloc_bootmem (between '.celleb_setup_phb' and '.celleb_fake_pci_write_config') Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
* | [POWERPC] MPC5200 low power modeDomen Puncer2007-09-191-0/+10
| | | | | | | | | | | | | | | | | | | | | | Low-power mode implementation for Lite5200b. Some I/O registers are also saved here. A recent U-Boot that supports this (lite5200b_PM_config) is needed. Signed-off-by: Domen Puncer <domen.puncer@telargo.com> Signed-off-by: Sylvain Munaut <tnt@246tNt.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
* | [POWERPC] spufs: Handle errors in SPU coredump code, and support coredump to ↵Michael Ellerman2007-09-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | a pipe Rework spufs_coredump_extra_notes_write() to check for and return errors. If we're coredumping to a pipe we can't trust file->f_pos, we need to maintain the foffset value passed to us. The cleanest way to do this is to have the low level write routine increment foffset when we've successfully written. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* | [POWERPC] spufs: Cleanup ELF coredump extra notes logicMichael Ellerman2007-09-191-7/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To start with, arch_notes_size() etc. is a little too ambiguous a name for my liking, so change the function names to be more explicit. Calling through macros is ugly, especially with hidden parameters, so don't do that, call the routines directly. Use ARCH_HAVE_EXTRA_ELF_NOTES as the only flag, and based on it decide whether we want the extern declarations or the empty versions. Since we have empty routines, actually use them in the coredump code to save a few #ifdefs. We want to change the handling of foffset so that the write routine updates foffset as it goes, instead of using file->f_pos (so that writing to a pipe works). So pass foffset to the write routine, and for now just set it to file->f_pos at the end of writing. It should also be possible for the write routine to fail, so change it to return int and treat a non-zero return as failure. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* | [POWERPC] spufs: Combine spufs_coredump_calls with spufs_callsMichael Ellerman2007-09-191-10/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Because spufs might be built as a module, we can't have other parts of the kernel calling directly into it, we need stub routines that check first if the module is loaded. Currently we have two structures which hold callbacks for these stubs, the syscalls are in spufs_calls and the coredump calls are in spufs_coredump_calls. In both cases the logic for registering/unregistering is essentially the same, so we can simplify things by combining the two. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Acked-by: Arnd Bergmann <arnd.bergmann@de.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
* | [POWERPC] spufs: Remove asmlinkage from spufs_callsJeremy Kerr2007-09-191-2/+2
| | | | | | | | | | | | | | | | spu_create and spu_run are wrapped by the cell syscall layer, so we don't need the asmlinkage. Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* | [POWERPC] cell: Unify spufs syscall pathJeremy Kerr2007-09-191-12/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present, a built-in spufs will not use the spufs_calls callbacks, but directly call sys_spu_create. This saves us an indirect branch, but means we have duplicated functions - one for CONFIG_SPU_FS=y and one for =m. This change unifies the spufs syscall path, and provides access to the spufs_calls structure through a get/put pair. At present, the only user of the spufs_calls structure is spu_syscalls.c, but this will facilitate adding the coredump calls later. Everyone likes numbers, right? Here's a before/after comparison with CONFIG_SPU_FS=y, doing spu_create(); close(); 64k times. Before: [jk@cell ~]$ time ./spu_create performing 65536 spu_create calls real 0m24.075s user 0m0.146s sys 0m23.925s After: [jk@cell ~]$ time ./spu_create performing 65536 spu_create calls real 0m24.777s user 0m0.141s sys 0m24.631s So, we're adding around 11us per syscall, at the benefit of having only one syscall path. Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* | [POWERPC] Remove APUS support from arch/ppcAdrian Bunk2007-09-172-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | Current status of APUS: - arch/powerpc/: removed in 2.6.23 - arch/ppc/: marked BROKEN since 2 years This therefore removes the remaining parts of APUS support from arch/ppc, include/asm-ppc, arch/powerpc and include/asm-powerpc. Signed-off-by: Adrian Bunk <bunk@stusta.de> Signed-off-by: Paul Mackerras <paulus@samba.org>
* | [POWERPC] 86xx: Fix definition of global-utilites structureTimur Tabi2007-09-141-105/+46
| | | | | | | | | | | | | | | | | | The current definition of struct ccsr_guts in immap_86xx.h was for 85xx. This patch fixes that and replaces the vague integer types with sized types of the correct endianness. The unused struct ccsr_pci is also deleted. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | [POWERPC] add clrsetbits macrosTimur Tabi2007-09-141-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the clrsetbits_xxx() macros, which are used to set and clear multiple bits in a single read-modify-write operation. Specify the bits to clear in the 'clear' parameter and the bits to set in the 'set' parameter. These macros can also be used to set a multiple-bit bit pattern using a mask, by specifying the mask in the 'clear' parameter and the new bit pattern in the 'set' parameter. There are big-endian and little-endian versions for 8, 16, 32, and 64 bits. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | [POWERPC] QE: extern par_io_config_pin and par_io_data_set funcsAnton Vorontsov2007-09-141-0/+3
| | | | | | | | | | | | | | This is needed to configure and control QE pario pins from the kernel. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | [POWERPC] Fix modpost warnings from head*.S on ppc32Kumar Gala2007-09-141-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We get warnings like the following from the various ppc32 head*.S files: WARNING: vmlinux.o(.text+0x358): Section mismatch: reference to .init.text:early_init (between 'skpinv' and 'interrupt_base') WARNING: vmlinux.o(.text+0x380): Section mismatch: reference to .init.text:machine_init (between 'skpinv' and 'interrupt_base') WARNING: vmlinux.o(.text+0x384): Section mismatch: reference to .init.text:MMU_init (between 'skpinv' and 'interrupt_base') WARNING: vmlinux.o(.text+0x3aa): Section mismatch: reference to .init.text:start_kernel (between 'skpinv' and 'interrupt_base') WARNING: vmlinux.o(.text+0x3ae): Section mismatch: reference to .init.text:start_kernel (between 'skpinv' and 'interrupt_base') Added a .text.head section simliar to what other architectures do since modpost already excludes this from its warnings. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | [POWERPC] Add cpu feature for SPE handlingKumar Gala2007-09-141-4/+22
| | | | | | | | | | | | | | | | Make it so that SPE support can be determined at runtime. This is similiar to how we handle AltiVec. This allows us to have SPE support built in and work on processors with and without SPE. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | [POWERPC] PS3: Add new LV1 error codesGeert Uytterhoeven2007-09-141-0/+9
| | | | | | | | | | | | | | | | Add new error codes that may be returned by the LV1 hypervisor Signed-off-by: Geert Uytterhoeven <Geert.Uytterhoeven@sonycom.com> Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
* | [POWERPC] Add workaround for MPICs with broken register readsOlof Johansson2007-09-141-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | Some versions of PWRficient 1682M have an interrupt controller in which the first register in each pair for interrupt sources doesn't always read with the right polarity/sense values. To work around this, keep a software copy of the register instead. Since it's not modified from the mpic itself, it's a feasible solution. Still, keep it under a config option to avoid wasting memory on other platforms. Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Paul Mackerras <paulus@samba.org>
* | [POWERPC] Move lowlevel runlatch calls under cpu feature controlOlof Johansson2007-09-141-0/+2
| | | | | | | | | | | | | | | | There's no need to call the runlatch on functions on processors that don't implement them (CPU_FTR_CTRL). Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Paul Mackerras <paulus@samba.org>
* | [POWERPC] pasemi: Export more SPRs to sysfs when CONFIG_DEBUG_KERNEL=yOlof Johansson2007-09-141-11/+37
| | | | | | | | | | | | | | | | Export some of the implementation-specific registers via sysfs. Useful when debugging, etc. Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Paul Mackerras <paulus@samba.org>
* | [POWERPC] Add an optional device_node pointer to the irq_hostMichael Ellerman2007-09-142-5/+6
| | | | | | | | | | | | | | | | | | | | The majority of irq_host implementations (3 out of 4) are associated with a device_node, and need to stash it somewhere. Rather than having it somewhere different for each host, add an optional device_node pointer to the irq_host structure. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
* | Merge branch 'linux-2.6' into for-2.6.24Paul Mackerras2007-09-141-1/+1
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| * [POWERPC] cell/PS3: Fix a bug that causes the PS3 to hang on the SPU Class 0 ↵Masato Noguchi2007-09-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | interrupt. The Cell BE Architecture spec states that the SPU MFC Class 0 interrupt is edge-triggered. The current spu interrupt handler assumes this behavior and does not clear the interrupt status. The PS3 hypervisor visualizes all SPU interrupts as level, and on return from the interrupt handler the hypervisor will deliver a new virtual interrupt for any unmasked interrupts which for which the status has not been cleared. This fix clears the interrupt status in the interrupt handler. Signed-off-by: Masato Noguchi <Masato.Noguchi@jp.sony.com> Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com> Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Acked-by: Arnd Bergmann <arnd.bergmann@de.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
* | Merge branch 'linux-2.6' into for-2.6.24Paul Mackerras2007-08-281-1/+11
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| * [POWERPC] Fix FSL BookE machine check reportingBecky Bruce2007-08-171-1/+11
| | | | | | | | | | | | | | | | | | | | Reserved MCSR bits on FSL BookE parts may have spurious values when mcheck occurs. Mask these off when printing the MCSR to avoid confusion. Also, get rid of the MCSR_GL_CI bit defined for e500 - this bit doesn't actually have any meaning. Signed-off-by: Becky Bruce <becky.bruce@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | [POWERPC] Copy over headers from arch/ppc to arch/powerpc that we needKumar Gala2007-08-228-0/+3637
| | | | | | | | | | | | | | | | | | | | | | To build arch/powerpc without including asm-ppc/ we need these files in asm-powerpc/ Moved some headers under arch/powerpc/platforms if they were only used by platform or driver files and fixed up the source file includes to match the new locations Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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