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path: root/include/asm-mips/cpu-features.h
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* [MIPS] Enable support for the userlocal hardware registerRalf Baechle2007-07-101-0/+4
| | | | | | | | Which will cut down the cost of RDHWR $29 which is used to obtain the TLS pointer and so far being emulated in software down to a single cycle operation. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] FPU ownership management & preemption fixesAtsushi Nemoto2007-03-171-0/+3
| | | | | Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Use the proper technical term for naming some of the cache macros.Ralf Baechle2006-07-131-2/+2
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Default cpu_has_mipsmt to a runtime checkChris Dearman2006-07-131-5/+1
| | | | | Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix configuration of R2 CPU features and multithreading.Ralf Baechle2006-06-291-12/+8
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Don't include linux/config.h from anywhere else in include/David Woodhouse2006-04-261-1/+0
| | | | Signed-off-by: David Woodhouse <dwmw2@infradead.org>
* [MIPS] FPU affinity for MT ASE.Ralf Baechle2006-04-191-1/+1
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] local_r4k_flush_cache_page fixAtsushi Nemoto2006-03-181-0/+3
| | | | | | | | | | If dcache_size != icache_size or dcache_size != scache_size, or set-associative cache, icache/scache does not flushed properly. Make blast_?cache_page_indexed() masks its index value correctly. Also, use physical address for physically indexed pcache/scache. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Reorganize ISA constants strictly as bitmasks.Ralf Baechle2006-01-101-24/+21
| | | | Signed-off-by: Ralf Baechle <ralf@ongar.mips.com>
* MIPS: Introduce machinery for testing for MIPSxxR1/2.Ralf Baechle2006-01-101-0/+24
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Cleanup the mess in cpu_cache_init.Ralf Baechle2005-10-291-2/+13
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Detect the MIPS R2 vectored interrupt, external interrupt controllerRalf Baechle2005-10-291-0/+24
| | | | | | options and the precense of the MT ASE. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Redo RM9000 workaround which along with other DSP ASE changes wasRalf Baechle2005-10-291-11/+0
| | | | | | causing some headache for debuggers knowing about signal frames. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Support the MIPS32 / MIPS64 DSP ASE.Ralf Baechle2005-10-291-0/+4
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Cleanup decoding of MIPSxx config registers.Ralf Baechle2005-10-291-3/+13
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [PATCH] mips: clean up 32/64-bit configurationRalf Baechle2005-09-051-2/+2
| | | | | | | | Start cleaning 32-bit vs. 64-bit configuration. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* Linux-2.6.12-rc2v2.6.12-rc2Linus Torvalds2005-04-161-0/+159
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
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