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* watchdog: renesas_wdt: update copyright datesWolfram Sang2017-09-091-2/+2
| | | | | | | Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
* watchdog: renesas_wdt: make 'clk' a variable local to probe()Wolfram Sang2017-09-091-5/+5
| | | | | | | | | | It is not needed outside probe() anymore. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
* watchdog: renesas_wdt: consistently use RuntimePM for clock managementWolfram Sang2017-09-091-14/+19
| | | | | | | | | | | | | | | | | | | | | | | On Renesas R-Car archs, RuntimePM does all the clock handling. So, use it consistently to enable/disable the clocks. Also make sure that clocks are really enabled around clk_get_rate(). clk_summary looks proper now: clock enable_cnt prepare_cnt rate ... Before this commit: At boot: rwdt 1 1 32768 0 0 WDT running: rwdt 2 2 32768 0 0 After this commit: At boot: rwdt 0 1 32768 0 0 WDT running rwdt 1 1 32768 0 0 Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
* watchdog: renesas_wdt: add another divider optionWolfram Sang2017-09-091-3/+5
| | | | | | | | | | If we set RWTCSRB to 0, we can gain 4096 as another divider value. This is supported by all R-Car Gen2 and Gen3 devices which we aim to support. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
* watchdog: renesas_wdt: apply better precisionWolfram Sang2017-09-091-9/+19
| | | | | | | | | | | | | | | | The error margin of the clks_per_second variable was too large and caused offsets when used with clock frequencies which left a remainder after applying the dividers. Now we always calculate directly using the clock rate and the divider using some helper macros. That also means that DIV_ROUND_UP moves from probe to the multiplication macro. In probe, we don't need to ensure anymore that 'clks_per_sec' would go too fast but rather ensure that the lower limit is really at least 1 to certainly get a full cycle. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
* watchdog: renesas_wdt: don't round closest with get_timeleftWolfram Sang2017-09-091-1/+1
| | | | | | | | | | We should never return more time left than there actually is. So, switch to a plain divider instead of DIV_ROUND_CLOSEST. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
* watchdog: renesas_wdt: check rate also for upper limitWolfram Sang2017-09-091-2/+2
| | | | | | | | | | When checking the clock rate, ensure also that counting all 16 bits takes at least one second to match the granularity of the framework. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
* watchdog: renesas_wdt: avoid (theoretical) type overflowWolfram Sang2017-09-091-3/+2
| | | | | | | | | | Because the smallest clock divider we can select is 1, 'clks_per_sec' must be the same type as 'rate'. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
* watchdog: renesas-wdt: add driverWolfram Sang2016-05-141-0/+213
Add support for watchdogs (RWDT and SWDT) found on RCar Gen3 based SoCs from Renesas. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
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