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Since chipidea is a dual role controller, it makes sense to move it
to its own directory, where we can also have host, otg and platform
code related to this controller. It also makes sense to break out
the driver into several compilation units like udc, host, debugging
code, etc.
Firstly, let's move the udc and platform code to drivers/usb/chipidea.
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Don't try to initialize devices that don't have driver_data assigned
to their pci ids.
Reported-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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As pointed out by Dan Carpenter, the check for NULL for the id variable
is no longer needed, especially as we just dereferenced it a few lines
earlier, causing an oops if it really was NULL.
This was caused by 62bb84ed0e4d: "usb: gadget: ci13xxx: convert to
platform device".
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Let's break ci13xxx driver into a separate udc driver and platform
drivers _pci and _msm, which will create a platform device for each pci
(or msm) device found. The approach was introduced by Felipe in dwc3
driver and there seems to be no reason not to use it.
msm related code is only compile-tested.
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Add pci ids for ChipIdea UDC as found in langwell/penwell SoCs.
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Currently, the register prefixes in the driver seem to be mixed: the
capability registers are the ones that contain capability information,
such as number of hardware endpoints, while the registers that are
used to program the controller are called operational registers.
Normally, capability registers start at 0x100 offset of the register
window and are followed by operational registers. In some versions,
however, capability registers start at 0x0 offset.
This patch renames the register and adjusts their offsets appropriately,
leaving the possibility of having a non-standard capability offset.
I couldn't find any mentions of the TESTMODE register anywhere, so I
suspect it might only be enabled in chipidea internal versions of the
controller and I'm really inclined to remove it from the driver or at
least hiding it behind a config option.
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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This patch converts the drivers in drivers/usb/gadget/* to use
module_pci_driver() macro which makes the code smaller and a bit simpler.
Signed-off-by: Axel Lin <axel.lin@gmail.com>
Cc: Thomas Dahlmann <dahlmann.thomas@arcor.de>
Cc: Xiaochen Shen <xiaochen.shen@intel.com>
Cc: Pavankumar Kondeti <pkondeti@codeaurora.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Felipe Balbi <balbi@ti.com>
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Introduces ci13xxx_udc_driver struct for bus glue drivers to hint
ci13xxx_udc core about their special requirements. The flags include
avoiding hardware register access when controller is not in peripheral
mode, enabling pull-up upon VBUS, disabling streaming mode and dependency
on transceiver driver.
Initialize gadget_ops in udc_probe so that transceiver can notify VBUS
presence even when no gadget driver is bounded.
A notify_event callback is embedded in the same struct. This patch implements
two events called CONTROLLER_RESET_EVENT and CONTROLLER_STOPPED_EVENT to
notify the bus glue driver after resetting and stopping the controller for
performing SoC specific quirks.
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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Move PCI bus code from ci13xxx_udc to a new file ci13xxx_pci. SoC's
which has MIPS USB core can include the ci13xxx_udc and keep bus glue
code in their respective gadget controller drivers.
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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