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* pinctrl/abx500: move IRQ handling to ab8500-coreLee Jones2013-02-101-296/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | In its current state the gpio-ab8500 driver looks after some GPIO lines found on the AB8500 MFD chip. It also controls all of its own IRQ handling for these GPIOs by inventing some virtual IRQs and handing those out to sub-devices. There has been quite a bit of controversy over this and it was a contributing factor to the driver being marked as BROKEN in Mainline. The reason for adopting this method was due to added complexity in the hardware. Unusually, each GPIO has two separate IRQs associated with it, one for a rising and a different one for a falling interrupt. Using this method complicates matters further because the GPIO IRQs are actually sandwiched between a bunch of IRQs which are handled solely by the AB8500 core driver. The best way for us to take this forward is to get rid of the virtual IRQs and only hand out the rising IRQ lines. If a sub-driver wishes to request a falling interrupt, they can do so by requesting a rising line in the normal way. They just have to add IRQ_TYPE_EDGE_FALLING or IRQ_TYPE_EDGE_BOTH, if they require both in the flags. Then if a falling IRQ is triggered, the AB8500 core driver will know how to handle the added complexity accordingly. This should greatly simply things. Signed-off-by: Lee Jones <lee.jones@linaro.org> [Augment to keep irq_base for a while (removed later)] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge branch 'allwinner-sunxi' into develLinus Walleij2013-02-084-0/+1989
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| * pinctrl: sunxi: add of_xlate functionMaxime Ripard2013-02-051-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | Since the pin controller of sunxi chips is represented as a single bank in the driver. Since this is neither convenient nor represented that way in the datasheets, define a custom of_xlate function with the layout <bank pin flag> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * ARM: pinctrl: sunxi: Add the pinctrl pin set for Allwinner A10Maxime Ripard2013-02-012-0/+622
| | | | | | | | | | | | | | | | Since the Allwinner SoCs variants don't have the same set of pins to handle, we need to declare the pin ranges available. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sunxi: Document sun5i pins functionsMaxime Ripard2013-02-011-4/+4
| | | | | | | | | | Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * ARM: sunxi: gpio: Add Allwinner SoCs GPIO driversMaxime Ripard2013-01-292-3/+156
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The IP responsible for the muxing on the Allwinner SoCs are also handling the GPIOs on the system. This patch adds the needed driver that relies on the pinctrl driver for most of its operations. The number of pins available for GPIOs operations are already declared in the pinctrl driver, we only need to probe a generic driver to handle the banks available for each SoC. This driver has been tested on a A13-Olinuxino. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * ARM: pinctrl: sunxi: Add the pinctrl pin set for sun5iMaxime Ripard2013-01-221-0/+253
| | | | | | | | | | | | | | | | Since the Allwinner SoCs variants don't have the same set of pins to handle, we need to declare the pin ranges available. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * ARM: sunxi: Add pinctrl driver for Allwinner SoCsMaxime Ripard2013-01-224-0/+941
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Allwinner SoCs have an IP module that handle both the muxing and the GPIOs. This IP has 8 banks of 32 bits, with a number of pins actually useful for each of these banks varying from one to another, and depending on the SoC used on the board. This driver only implements the pinctrl part, the gpio part will come eventually. Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: exynos5440: remove erroneous __initLinus Walleij2013-02-071-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | This removes the __init notation from some of the the exynos 5440 pin controller set-up functions. These functions are called from probe() and as such may be discarded before probe() completes. Cc: Thomas Abraham <thomas.abraham@linaro.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl/abx500: adjust offset for get_mode()Linus Walleij2013-02-071-1/+3
| | | | | | | | | | | | | | | | | | | | The set_mode() and get_mode() functions in the abx500 were not mirrored, leading to the wrong GPIO control bits being read out. Cc: Lee Jones <lee.jones@linaro.org> Reported-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl/abx500: add Device Tree supportLee Jones2013-02-061-5/+31
| | | | | | | | | | | | | | | | This patch will allow the ABX500 Pinctrl driver to be probed when Device Tree is enabled with an appropriate node contained. Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl/abx500: align GPIO cluster boundariesLee Jones2013-02-065-16/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Not quite sure how this ever worked. In ab8500_gpio_to_irq() the GPIO for conversion is passed through as the second argument. If GPIO13, which is a valid GPIO for IRQ functionality, was received; it would be rejected by the following guard: GPIO_IRQ_CLUSTER(5, 12, 0); /* GPIO numbers start from 1 */ if (offset >= cluster->start && offset <= cluster->end) /* Valid GPIO for IRQ use */ Signed-off-by: Lee Jones <lee.jones@linaro.org> [Augmented to account for off-by-one problem] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl/abx500: prevent error path from corrupting returning errorLee Jones2013-02-061-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | Prior to this patch abx500_gpio_probe() would return the return-value of gpiochip_remove() during its error patch regardless of what the actual failure was. So as long as gpiochip_remove() succeeded, probe() would look like it succeeded too. This patch ensures the correct error value is returned and that mutex_destroy() is invoked if gpiochip_add_pin_range() were to fail. Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl/lantiq: fix pin number in ltq_pmx_gpio_request_enableJohn Crispin2013-02-051-1/+1
| | | | | | | | | | | | | | | | | | The mapping logic inside ltq_pmx_gpio_request_enable() was broken. This only effected Falcon SoC. Signed-off-by: Thomas Langer <thomas.langer@lantiq.com> Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl/lantiq: add functionality to falcon_pinconf_dbg_showJohn Crispin2013-02-051-0/+31
| | | | | | | | | | | | | | | | | | The current code only has a stub for falcon_pinconf_dbg_show. This patch adds proper functionality. Signed-off-by: Thomas Langer <thomas.langer@lantiq.com> Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl/lantiq: fix pinconfig parametersJohn Crispin2013-02-051-0/+2
| | | | | | | | | | | | | | | | | | The Falcon driver only defined the pinconf parameters but did not pass them properly to the underlying api. Signed-off-by: Thomas Langer <thomas.langer@lantiq.com> Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl/lantiq: one of the boot leds was defined incorrectlyJohn Crispin2013-02-051-1/+1
| | | | | | | | | | | | | | | | On the Falcon SoC the bootleds are located on pins 9->14. Signed-off-by: Thomas Langer <thomas.langer@lantiq.com> Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl/lantiq: only probe available pad controllersJohn Crispin2013-02-051-0/+3
| | | | | | | | | | | | | | | | | | The template falcon.dtsi lists all 6 pad controllers that can be loaded. Only probe those that have status = "okay"; inside the dts file. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl/lantiq: the pinconf OD parameter argument was ignoredJohn Crispin2013-02-051-1/+4
| | | | | | | | | | | | | | | | When setting the OpenDrain bit we should really honour the argument passed inside the devicetree. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl/lantiq: add output pinconf parameterJohn Crispin2013-02-052-0/+15
| | | | | | | | | | | | | | | | | | While converting the boards inside OpenWrt to OF I noticed that the we are missing a pinconf parameter to set a pin to output. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl/lantiq: add pin_config_group_set supportJohn Crispin2013-02-052-20/+49
| | | | | | | | | | | | | | | | | | While converting all the boards supported by OpenWrt to OF I noticed that this feature is missing. Adding it makes the devicetrees more readable. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl/lantiq: faulty bit inversionJohn Crispin2013-02-051-1/+1
| | | | | | | | | | | | | | | | The logic of the OD bit was inverted when calling the pinconf get method. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl/lantiq: pinconf uses port instead of pinJohn Crispin2013-02-051-14/+14
| | | | | | | | | | | | | | | | | | The XWAY pinctrl driver invalidly uses the port and not the pin number to work out the registers and bits to be set for the opendrain and pullup/down resistors. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl/abx500: destroy mutex if returning early due to errorLee Jones2013-02-051-0/+3
| | | | | | | | | | | | | | | | | | Current failure path neglects to mutex_destroy() before returning an error due to an invalid parameter or an error received from gpiochip_add(). This patch aims to remedy that behaviour. Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl/abx500: beautify the ABX500 pin control driverLee Jones2013-02-051-35/+59
| | | | | | | | | | | | | | | | | | | | | | | | This patch provides some superficial changes to the driver to aid with readability and maintainability. We're mostly fixing things like white-space errors, spreading out code which as been clumped together impeding readability and comment layout, such as using the new "/**" comment start for function headers etc. No code semantics were harmed in the making of this patch. Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl/abx500: replace incorrect return valueLee Jones2013-02-051-2/+1
| | | | | | | | | | | | | | | | | | | | | | Currently in the empty abx500_pin_config_get() function, we're returning -EINVAL, with a comment stating that the reason for the failure is that the function isn't implemented yet. Well there's a proper return code for that. If we use it, we can do away with the comment too, as it would be implied. Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl/abx500: use the BIT() macro where appropriateLee Jones2013-02-051-1/+1
| | | | | | | | | | | | | | | | | | | | The BIT() macro provides a simple and easy to read way of obtaining bit offsets into things like masks and hardware registers. In this patch we're simply replacing all instances of '1 << x' with 'bit(x)'. Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl/abx500: add AB8540 sub-driverPatrice Chotard2013-02-055-0/+427
| | | | | | | | | | | | | | | | | | | | | | | | | | Add AB8540 sub driver to the ABx500 family, pins, pin groups and gpio range. As the pin controller (also the ABx500 controllers) is an inherent part of the SoC and will prevent boot if not available, select this from the Ux500 SoC Kconfig. Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Patrice Chotard <patrice.chotard@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl/abx500: add AB9540 sub-driverPatrice Chotard2013-02-055-0/+506
| | | | | | | | | | | | | | | | | | | | | | | | | | Add AB9540 sub driver to the ABx500 family, pins, pin groups and gpio range. As the pin controller (also the ABx500 controllers) is an inherent part of the SoC and will prevent boot if not available, select this from the Ux500 SoC Kconfig. Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Patrice Chotard <patrice.chotard@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl/abx500: add AB8505 sub-driverPatrice Chotard2013-02-055-0/+401
| | | | | | | | | | | | | | | | | | | | | | | | Add AB8505 sub driver to the ABx5x family. As the pin controller (also the ABx500 controllers) is an inherent part of the SoC and will prevent boot if not available, select this from the Ux500 SoC Kconfig. Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Patrice Chotard <patrice.chotard@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl/abx500: add AB8500 sub-driverPatrice Chotard2013-01-305-0/+505
| | | | | | | | | | | | | | | | | | | | | | | | This adds a subdriver for the AB8500 pinctrl portions. As the pin controller (also the ABx500 controllers) is an inherent part of the SoC and will prevent boot if not available, select this from the Ux500 SoC Kconfig. Acked-by: Olof Johansson <olof@lixom.net> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: add abx500 pinctrl driver corePatrice Chotard2013-01-304-0/+1421
| | | | | | | | | | | | | | | | | | | | | | This adds the AB8500 core driver, which will be utilized by the follow-on drivers for different ABx500 variants. Sselect the driver from the DBX500_SOC, as this chip is powering and clocking that SoC. Cc: Samuel Ortiz <sameo@linux.intel.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: core: Make pinctrl_release staticSachin Kamat2013-01-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | 'pinctrl_release' is used only in this file. Hence make it static. Without this patch we get the following sparse error: drivers/pinctrl/core.c:815:6: warning: symbol 'pinctrl_release' was not declared. Should it be static? Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | drivers/pinctrl: grab default handles from device coreLinus Walleij2013-01-232-4/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This makes the device core auto-grab the pinctrl handle and set the "default" (PINCTRL_STATE_DEFAULT) state for every device that is present in the device model right before probe. This will account for the lion's share of embedded silicon devcies. A modification of the semantics for pinctrl_get() is also done: previously if the pinctrl handle for a certain device was already taken, the pinctrl core would return an error. Now, since the core may have already default-grabbed the handle and set its state to "default", if the handle was already taken, this will be disregarded and the located, previously instanitated handle will be returned to the caller. This way all code in drivers explicitly requesting their pinctrl handlers will still be functional, and drivers that want to explicitly retrieve and switch their handles can still do that. But if the desired functionality is just boilerplate of this type in the probe() function: struct pinctrl *p; p = devm_pinctrl_get_select_default(&dev); if (IS_ERR(p)) { if (PTR_ERR(p) == -EPROBE_DEFER) return -EPROBE_DEFER; dev_warn(&dev, "no pinctrl handle\n"); } The discussion began with the addition of such boilerplate to the omap4 keypad driver: http://marc.info/?l=linux-input&m=135091157719300&w=2 A previous approach using notifiers was discussed: http://marc.info/?l=linux-kernel&m=135263661110528&w=2 This failed because it could not handle deferred probes. This patch alone does not solve the entire dilemma faced: whether code should be distributed into the drivers or if it should be centralized to e.g. a PM domain. But it solves the immediate issue of the addition of boilerplate to a lot of drivers that just want to grab the default state. As mentioned, they can later explicitly retrieve the handle and set different states, and this could as well be done by e.g. PM domains as it is only related to a certain struct device * pointer. ChangeLog v4->v5 (Stephen): - Simplified the devicecore grab code. - Deleted a piece of documentation recommending that pins be mapped to a device rather than hogged. ChangeLog v3->v4 (Linus): - Drop overzealous NULL checks. - Move kref initialization to pinctrl_create(). - Seeking Tested-by from Stephen Warren so we do not disturb the Tegra platform. - Seeking ACK on this from Greg (and others who like it) so I can merge it through the pinctrl subsystem. ChangeLog v2->v3 (Linus): - Abstain from using IS_ERR_OR_NULL() in the driver core, Russell recently sent a patch to remove it. Handle the NULL case explicitly even though it's a bogus case. - Make sure we handle probe deferral correctly in the device core file. devm_kfree() the container on error so we don't waste memory for devices without pinctrl handles. - Introduce reference counting into the pinctrl core using <linux/kref.h> so that we don't release pinctrl handles that have been obtained for two or more places. ChangeLog v1->v2 (Linus): - Only store a pointer in the device struct, and only allocate this if it's really used by the device. Cc: Felipe Balbi <balbi@ti.com> Cc: Benoit Cousson <b-cousson@ti.com> Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Mitch Bradley <wmb@firmworks.com> Cc: Ulf Hansson <ulf.hansson@linaro.org> Cc: Rafael J. Wysocki <rjw@sisk.pl> Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Rickard Andersson <rickard.andersson@stericsson.com> Cc: Russell King <linux@arm.linux.org.uk> Reviewed-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> [swarren: fixed and simplified error-handling in pinctrl_bind_pins(), to correctly handle deferred probe. Removed admonition from docs not to use pinctrl hogs for devices] Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: generic: add slew rate config parameterHaojian Zhuang2013-01-211-0/+1
| | | | | | | | | | | | | | Add PIN_CONFIG_SLEW_RATE parameter into pinconf-generic driver. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: core: get devname from pinctrl_devHaojian Zhuang2013-01-211-0/+6
| | | | | | | | | | | | | | | | | | Add new function to get devname from pinctrl_dev. pinctrl_dev_get_name() can only get pinctrl description name. If we want to use gpio driver to find pinctrl device node, we need to fetch the pinctrl device name. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: nomadik: Allow prcm_base to be extracted from Device TreeLee Jones2013-01-181-11/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Nomadik Pinctrl driver requires access to some PRCMU registers in order to run with full functionality. When Device Tree is disabled the required PRCMU base address is passed in via platform data, so in order for Device Tree booting to be as functional, we need a similar mechanism to fetch it from Device Tree. The new semantics goes like this: Parse the Device Tree and look for the PRCMU node using a provided Phandle. Obtain the ioremaped address from that node. If one was supplied via platform data over-write it with anything found in Device Tree. Fail if either the prcm_base can't be found if we're running on anything other than an STN8815 ASIC. Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: exynos: change PINCTRL_EXYNOS optionKukjin Kim2013-01-182-3/+3
| | | | | | | | | | | | | | | | | | | | | | Since pinctrl-exynos can support exynos4 and exynos5 so changed the option name to PINCTRL_EXYNOS for more clarity. Cc: Thomas Abraham <Thomas.abraham@linaro.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: tegra114: add pinctrl driver for NVIDIA's Tegra114 SoCPritesh Raithatha2013-01-183-0/+2762
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a driver for the Tegra114 pinmux, and required parameterization data for Tegra114. The driver uses the common Tegra pincontrol driver utility functions to implement the majority of the driver. This driver is not compatible with the earlier NVIDIA's SoCs, hence add new compatibile as "nvidia,tegra114-pinmux". Originally written by Pritesh. ldewangan: - cleanup the patches, - remove non-require tables. - Use module_platform_driver() for driver registartion. Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: tegra: add support for rcv-sel and drive typePritesh Raithatha2013-01-184-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NVIDIA's Tegra114 added two more configuration parameter in pinmux i.e. rcv-sel and drive type. rcv-sel: Select between High and Normal VIL/VIH receivers. RCVR_SEL=1: High VIL/VIH RCVR_SEL=0: Normal VIL/VIH drv_type: Ouptput drive type: 33-50 ohm driver: 0x1 66-100ohm driver: 0x0 Add support of these parameters to be configure from DTS file. Tegra20 and Tegra30 does not support this configuration and hence initialize their pinmux structure with reg = -1. Originally written by Pritesh Raithatha. Changes by ldewangan: - remove drvtype_width as it is always 2. - Better describe the change. Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: do not defer device tree hogsLinus Walleij2013-01-111-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | commit af1024e0f7cde9023ddd0f3116db03911d5914c0 "pinctrl: skip deferral of hogs" Attempts to avoid probe deferral on hogged pins, but we forgot the device tree case. This patch fixes this. Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reported-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl/nomadik: add device tree supportGabriel Fernandez2013-01-111-1/+276
| | | | | | | | | | | | | | | | | | | | This implements pin multiplexing and pin configuration for the Nomadik pin controller using the device tree. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@stericsson.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Philippe Langlais <philippe.langlais@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl/nomadik: simplify GPIO probeLinus Walleij2013-01-111-35/+17
| | | | | | | | | | | | | | | | | | Instead of jumping to a label later in the probe just return with an error code whenever probe() fails. Make sure to remove the gpiochip on irqdomain error now that we're at it. Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl/nomadik: make independent of <mach/irqs.h>Linus Walleij2013-01-111-3/+2
| | | | | | | | | | | | | | | | | | | | Some leftovers in the driver were using NOMADIK_* macros to translate the irq numbers to offsets, while the first base IRQ was already being passed from platform data, and the function setting the disable mask could just as well use the irqdomain. Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: add pinconf-generic defines for outputLinus Walleij2013-01-111-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a definition of a generic output configuration for a certain pin when using the generic pin configuration library. Whereas driving pins low/high is usually a GPIO business, you may want to set up pins into a default state using hogs, and never touch them again. This helps out with that scenario. Based on a patch from Patrice Chotard. Signed-off-by: Patrice Chotard <patrice.chotard@stericsson.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl/nomadik: adopt pinctrl sleep mode managementJulien Delacou2013-01-111-0/+27
| | | | | | | | | | | | | | | | | | | | This fix makes pinctrl-nomadik able to handle suspend/resume events and change hogged pins states accordingly. Signed-off-by: Julien Delacou <julien.delacou@stericsson.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: add sleep mode management for hogsJulien Delacou2013-01-112-3/+41
| | | | | | | | | | | | | | | | | | | | | | This fix allows handling sleep mode for hogged pins in pinctrl. It provides functions to set pins to sleep/default configurations according to their current state. Signed-off-by: Julien Delacou <julien.delacou@stericsson.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: skip deferral of hogsLinus Walleij2013-01-111-3/+24
|/ | | | | | | | | | | | | | | | Up until now, as hogs were always taken at the end of the pin control device registration, it didn't cause any problem. But when starting to hog pins from the device core it will cause deferral of the pin controller device itself since the default pin fetch is done *before* the device probes, so let's fix this annoyance (which is also aesthetically ugly). Also take some care to make sure that if any one map entry results in a deferral rather than a failure, then that deferral will take precedence. Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds2013-01-081-2/+5
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull ARM SoC fixes from Olof Johansson: "People are back from the holiday breaks, and it shows. Here are a bunch of fixes for a number of platforms: - A couple of small fixes for Nomadik - A larger set of changes for kirkwood/mvebu - uart driver selection, dt clocks, gpio-poweroff fixups, a few __init annotation fixes and some error handling improvement in their xor dma driver. - i.MX had a couple of minor fixes (and a critical one for flexcan2 clock setup) - MXS has a small board fix and a framebuffer bugfix - A set of fixes for Samsung Exynos, fixing default bootargs and some Exynos5440 clock issues - A set of OMAP changes including PM fixes and a few sparse warning fixups All in all a bit more positive code delta than we'd ideally want to see here, mostly from the OMAP PM changes, but nothing overly crazy." * tag 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (44 commits) ARM: clps711x: Fix bad merge of clockevents setup ARM: highbank: save and restore L2 cache and GIC on suspend ARM: highbank: add a power request clear ARM: highbank: fix secondary boot and hotplug ARM: highbank: fix typos with hignbank in power request functions ARM: dts: fix highbank cpu mpidr values ARM: dts: add device_type prop to cpu nodes on Calxeda platforms ARM: mx5: Fix MX53 flexcan2 clock ARM: OMAP2+: am33xx-hwmod: Fix wrongly terminated am33xx_usbss_mpu_irqs array pinctrl: mvebu: make pdma clock on dove mandatory ARM: Dove: Add pinctrl clock to DT dma: mv_xor: fix error handling for clocks dma: mv_xor: fix error handling of mv_xor_channel_add() arm: mvebu: Add missing ; for cpu node. arm: mvebu: Armada XP MV78230 has only three Ethernet interfaces arm: mvebu: Armada XP MV78230 has two cores, not one clk: mvebu: Remove inappropriate __init tagging ARM: Kirkwood: Use fixed-regulator instead of board gpio call ARM: Kirkwood: Fix missing sdio clock ARM: Kirkwood: Switch TWSI1 of 88f6282 to DT clock providers ...
| * pinctrl: mvebu: make pdma clock on dove mandatorySebastian Hesselbarth2013-01-071-2/+5
| | | | | | | | | | | | | | | | | | With the ability to pass clocks through DT, now make the pdma clock of dove pinctrl mandatory. Otherwise, pinctrl will hang the system when accessing some registers. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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