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* pinctrl: uniphier: fix NAND pin-mux settings for PH1-LD11/LD20Masahiro Yamada2016-06-082-2/+2
| | | | | | | My mistake in the initial support patches. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: mediatek: fix suspend/resume timing issuehongkun.cao2016-06-081-2/+2
| | | | | | | | | | | An irq which is a wake up source maybe masked unexpectedly if the wake up source irq was triggered after pinctrl irqchip suspend and before suspend_device_irqs finished. Use *_noirq callbacks to guarantee pinctrl irqchip suspend would be called after suspend_devices_irqs. Signed-off-by: hongkun.cao <hongkun.cao@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: oxnas: Rename pinctrl_utils_dt_free_map to pinctrl_utils_free_mapNeil Armstrong2016-05-311-1/+1
| | | | | | | | | | Rename pinctrl_utils_dt_free_map to pinctrl_utils_free_map, introduced in d32f7fd3bbc3 ("pinctrl: Rename pinctrl_utils_dt_free_map to pinctrl_utils_free_map") but not reported into oxnas driver. Fixes: 611dac1e48a4 ("pinctrl: Add Oxford Semiconductor OXNAS pinctrl and gpio driver") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: uniphier: add UniPhier PH1-LD20 pinctrl driverMasahiro Yamada2016-05-313-0/+1042
| | | | | | | Add pin configuration and pinmux support for UniPhier PH1-LD20 SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: uniphier: add UniPhier PH1-LD11 pinctrl driverMasahiro Yamada2016-05-313-6/+967
| | | | | | | Add pin configuration and pinmux support for UniPhier PH1-LD11 SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: uniphier: allow to have pinctrl node under syscon nodeMasahiro Yamada2016-05-317-9/+35
| | | | | | | | | | | | | | | Currently, the UniPhier pinctrl driver itself is a syscon, but it turned out much more reasonable to make it a child node of a syscon because our syscon node consists of a bunch of system configuration registers, not only pinctrl, but also phy, and misc registers. It is difficult to split the node. To allow to migrate to the new DT structure, this commit adds new compatible strings to not disturb the existing DT. After a while, the old binding will be removed. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: uniphier: add System Bus pin-mux settingsMasahiro Yamada2016-05-316-0/+166
| | | | | | | This is needed to get access to UniPhier System Bus (external bus). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: uniphier: add dedicated pins to pin tables of PH1-LD4/sLD8Masahiro Yamada2016-05-312-0/+77
| | | | | | | | These pins do not support pin-muxing, but it is useful to support pin configuration for them. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: uniphier: support pin configuration for dedicated pinsMasahiro Yamada2016-05-318-147/+144
| | | | | | | | | | | | | PH1-LD4 and PH1-sLD8 SoCs have pins that support pin configuration (pin biasing, drive strength control), but not pin-muxing. Allow to fill the mux value table with -1 for those pins; pins with mux value -1 will be skipped in the pin-mux set function. The mux value type should be changed from "unsigned" to "int" in order to accommodate -1 as a special case. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: uniphier: support per-pin input enable for new SoCsMasahiro Yamada2016-05-312-11/+14
| | | | | | | | | Upcoming new pinctrl drivers for PH1-LD11 and PH-LD20 support input signal gating for each pin. (While, existing ones only support it per pin-group.) This commit updates the core part for that. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: uniphier: introduce capability flagMasahiro Yamada2016-05-318-31/+34
| | | | | | | | | | | | | | | | | | | | | | | The core part of the UniPhier pinctrl driver needs to support a new capability for upcoming UniPhier ARMv8 SoCs. This sometimes happens because pinctrl drivers include really SoC-specific stuff. This commit intends to tidy up SoC-specific parameters of the existing drivers before adding the new one. Having just one flag would be better than adding a new struct member every time a new SoC-specific capability comes up. At this time, there is one flag, UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE. This capability (I'd say rather quirk) was added for PH1-Pro4 and PH1-Pro5 as requirement from a customer. For those SoCs, one pin-mux setting is controlled by the combination of two separate registers; the LSB bits at register offset (8 * N) and the MSB bits at (8 * N + 4). Because it is impossible to update two separate registers atomically, the LOAD_PINCTRL register should be set in order to make the pin-mux settings really effective. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: uniphier: support pin configuration in sparse pin spaceMasahiro Yamada2016-05-311-44/+42
| | | | | | | | | | Unfortunately, the pin number of the new SoC, PH1-LD11, is not contiguous. The base frame work must be adjusted to support the new SoC pinctrl driver. The pin_desc_get() exploits radix-tree for pin look-up, so it works more efficiently with sparse pin space. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: uniphier: support 3-bit drive strength controlMasahiro Yamada2016-05-312-6/+21
| | | | | | | | | The new ARMv8 SoC, PH1-LD20, supports more fine-grained drive strength control. Drive strength of some pins are controlled by 3-bit width registers (8-level granularity). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: uniphier: rename macros for drive strength controlMasahiro Yamada2016-05-318-1407/+1407
| | | | | | | | | | | | | | | | | | | | | The new ARMv8 SoC, PH1-LD20, supports more fine-grained drive strength control. Some of the configuration registers on it have 3-bit width. The feature will be supported in the next commit, but a problem is that macro names are getting longer and longer in the current naming scheme. Before moving forward, this commit renames macros as follows: UNIPHIER_PIN_DRV_4_8 -> UNIPHIER_PIN_DRV_1BIT UNIPHIER_PIN_DRV_8_12_16_20 -> UNIPHIER_PIN_DRV_2BIT UNIPHIER_PIN_DRV_FIXED_4 -> UNIPHIER_PIN_DRV_FIXED4 UNIPHIER_PIN_DRV_FIXED_5 -> UNIPHIER_PIN_DRV_FIXED5 UNIPHIER_PIN_DRV_FIXED_8 -> UNIPHIER_PIN_DRV_FIXED8 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: uniphier: allocate struct pinctrl_desc in probe functionMasahiro Yamada2016-05-318-54/+33
| | | | | | | | | | | | Currently, every SoC driver defines struct pinctrl_desc statically, i.e. it consumes memory footprint even if it is not probed. In multi-platform, many pinctrl drivers are linked (generally as built-in objects), although only one of them is actually used. So, it is reasonable to allocate memory dynamically where possible. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: uniphier: set pinctrl_desc name in common probe functionMasahiro Yamada2016-05-317-24/+7
| | | | | | | | | Every SoC driver sets the same name for struct pinctrl_desc and platform_driver. The common probe function can set desc->name instead of duplicating strings in each SoC driver. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: uniphier: set pinctrl_desc owner in common probe functionMasahiro Yamada2016-05-317-6/+1
| | | | | | | | The owner of the struct pinctrl_desc matches that of platform_driver. Set it in the common probe function. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: uniphier: fix register offsets for drive strength controlMasahiro Yamada2016-05-315-46/+46
| | | | | | | | These pin tables were generated by parsing hardware documents with a script, but the script had a bug. Fix the register offsets. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: uniphier: rename function and variable namesMasahiro Yamada2016-05-316-126/+126
| | | | | | | Make function/variable names match the file names for consistency. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: uniphier: fix .pin_dbg_show() callbackMasahiro Yamada2016-05-311-0/+6
| | | | | | | | Without this, reading the "pins" in the debugfs causes kernel BUG. Fixes: 6e9088920258 ("pinctrl: UniPhier: add UniPhier pinctrl core support") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: imx: fix initialization of imx_pinctrl_descPeng Fan2016-05-311-11/+15
| | | | | | | | | | | | | | | | | | To i.MX7D, there are two iomux controllers, iomuxc and iomuxc_lpsr. They should not share one pin controller descriptor, otherwise the value filled into imx_pinctrl_desc when probing the first iomux controller will be overridden when probing the second one. In this patch, discard the static allcoated imx_pinctrl_desc and switch to dynamically allcate pin controller descriptor for each iomux controller. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Philipp Zabel <p.zabel@pengutronix.de> Cc: Stefan Agner <stefan@agner.ch> Cc: Vladimir Zapolskiy <vz@mleia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: amlogic: gxbb: add ethernet pinsKevin Hilman2016-05-311-0/+39
| | | | | | | | Add EE domain pins for ethernet interface. Acked-by: Carlo Caione <carlo@endlessm.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: amlogic: gxbb: add more UART pinsKevin Hilman2016-05-311-0/+48
| | | | | | | | Add EE domain pins for UART A, B & C. Acked-by: Carlo Caione <carlo@endlessm.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: amlogic: gxbb: add EMMC and SD pinsKevin Hilman2016-05-311-0/+41
| | | | | | | | Add EE domain pins for eMMC and SD card. Acked-by: Carlo Caione <carlo@endlessm.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: amlogic: gxbb: add UART_AO_B, I2CKevin Hilman2016-05-311-1/+34
| | | | | | | | | Add pins for some more AO domain devices: UART_AO_B and I2C master & slave. Acked-by: Carlo Caione <carlo@endlessm.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: return -ENOMEM instead of -EINVAL for kasprintf() failureMasahiro Yamada2016-05-311-1/+1
| | | | | | | | -ENOMEM is more suitable error code because kasprintf() fails in case of memory shortage. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: digicolor: add missing platform_set_drvdata() callMasahiro Yamada2016-05-311-0/+2
| | | | | | | | | gc_pinctrl_remove() calls platform_get_drvdata(), but I see neither platform_set_drvdata() nor dev_set_drvdata() anywhere in this driver. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: pinconf: separate config parameters with commas for debugfsMasahiro Yamada2016-05-312-7/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | To improve debugfs readability, use commas instead of whitespaces for separating configuration parameters. For example, the "pinconf-pins" dump on my board will change as follows: Without this commit: # head -5 pinconf-pins Pin config settings per pin Format: pin (name): configs pin 0 (ED0): input bias pull down output drive strength (8 mA) input enabled pin 1 (ED1): input bias pull down output drive strength (8 mA) input enabled pin 2 (ED2): input bias pull down output drive strength (8 mA) input enabled With this commit: # head -5 pinconf-pins Pin config settings per pin Format: pin (name): configs pin 0 (ED0): input bias pull down, output drive strength (8 mA), input enabled pin 1 (ED1): input bias pull down, output drive strength (8 mA), input enabled pin 2 (ED2): input bias pull down, output drive strength (8 mA), input enabled Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: copy per-pin driver private data to struct pin_descMasahiro Yamada2016-05-312-10/+14
| | | | | | | | | | | | | | | | | | | | Currently, struct pinctrl_pin_desc can have per-pin driver private data, but it is not copied to struct pin_desc. For a driver with sparse pin space, for-loop search like below would be necessary in order to get the driver-specific data for a desired pin number. for (i = 0; i < pctldev->desc->npins; i++) if (pin_number == pctldev->desc->pins[i].number) return pctldev->desc->pins[i].drv_data; This is not efficient for a driver with a large number of pins. So, copy the data to struct pin_desc when each pin is registered for the faster radix tree lookup. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: do not care about blank pin nameMasahiro Yamada2016-05-313-16/+7
| | | | | | | | | If a pin name is not specified in struct pinctrl_pin_desc, pinctrl_register_one_pin() dynamically assigns its name. So, desc->name is always a valid pointer here. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: stm32: factorize stm32_pconf_input/output_get()Patrice Chotard2016-05-311-21/+10
| | | | | | | | As these 2 functions code are 95% similar, factorize them. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Acked-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: samsung: Suppress unbinding to prevent theoretical attacksKrzysztof Kozlowski2016-05-302-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Although unbinding a pinctrl driver requires root privileges but it still might be used theoretically in certain attacks (by triggering NULL pointer exception or memory corruption). Samsung pincontrol drivers are essential for system operation so their removal is not expected. They do not implement remove() driver callback and they are not buildable as modules. Suppression of the unbinding will prevent triggering NULL pointer exception like this (Odroid XU3): $ echo 13400000.pinctrl > /sys/bus/platform/drivers/samsung-pinctrl/unbind $ cat /sys/kernel/debug/gpio Unable to handle kernel NULL pointer dereference at virtual address 00000c44 pgd = ec41c000 [00000c44] *pgd=6d448835, *pte=00000000, *ppte=00000000 Internal error: Oops: 17 [#1] PREEMPT SMP ARM (samsung_gpio_get) from [<c034f9a0>] (gpiolib_seq_show+0x1b0/0x26c) (gpiolib_seq_show) from [<c01fb8c0>] (seq_read+0x304/0x4b8) (seq_read) from [<c02dbc78>] (full_proxy_read+0x4c/0x64) (full_proxy_read) from [<c01d9fb0>] (__vfs_read+0x2c/0x110) (__vfs_read) from [<c01db400>] (vfs_read+0x8c/0x110) (vfs_read) from [<c01db4c4>] (SyS_read+0x40/0x8c) (SyS_read) from [<c01078c0>] (ret_fast_syscall+0x0/0x3c) Suggested-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: oxnas: Add GPIO get_directionNeil Armstrong2016-05-301-0/+11
| | | | | | | | Implement a get_direction callback for the OXNAS GPIO driver in order to have pin output polarity in debugfs and new userspace ABI. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: max77620: add pincontrol driver for MAX77620/MAX20024Laxman Dewangan2016-05-303-0/+689
| | | | | | | | | | | | | | MAXIM Semiconductor's PMIC, MAX77620/MAX20024 has 8 GPIO pins which also act as the special function in alternate mode. Also there is configuration like push-pull, open drain, FPS timing etc for these pins. Add pin control driver to configure these parameters through pin control APIs. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: tegra: Get rid of parked_regLaxman Dewangan2016-05-301-1/+1
| | | | | | | | | | | | Remove the use of parked_reg and use parked_bit for to know whether field is supported or not. This is fix for the patch commit 1d18a3f0f0809f6c71f1f6e9e268ee904ce0b588 "pinctrl: tegra: avoid parked_reg and parked_bank Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Revert "Revert "pinctrl: tegra: avoid parked_reg and parked_bank""Linus Walleij2016-05-307-20/+14
| | | | This reverts commit 0d5358330c20d50e52e3e65ff07a5db8007041fc.
* pinctrl: Add Oxford Semiconductor OXNAS pinctrl and gpio driverNeil Armstrong2016-05-303-0/+847
| | | | | | | | Add pinctrl and gpio control support to Oxford Semiconductor OXNAS SoC Family. This version supports the ARM926EJ-S based OX810SE SoC with 34 IO pins. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* drivers/pinctrl/intel/pinctrl-baytrail.c: fix build with gcc-4.4Andrew Morton2016-05-261-3/+7
| | | | | | | | | | | | | | | | | | | | gcc-4.4 and thereabouts has issues with initializers of anonymous unions, and it generates the following warnings: drivers/pinctrl/intel/pinctrl-baytrail.c:413: error: unknown field 'simple_funcs' specified in initializer drivers/pinctrl/intel/pinctrl-baytrail.c:413: warning: missing braces around initializer drivers/pinctrl/intel/pinctrl-baytrail.c:413: warning: (near initialization for 'byt_score_groups[0].<anonymous>') drivers/pinctrl/intel/pinctrl-baytrail.c:415: error: unknown field 'simple_funcs' specified in initializer drivers/pinctrl/intel/pinctrl-baytrail.c:417: error: unknown field 'simple_funcs' specified in initializer ... Work around this. Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Cc: Heikki Krogerus <heikki.krogerus@linux.intel.com> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Merge tag 'pinctrl-v4.7-1' of ↵Linus Torvalds2016-05-19116-867/+4592
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This kernel cycle was quite calm when it comes to pin control and there is really just one major change, and that is the introduction of devm_pinctrl_register() managed resources. Apart from that linear development, details below. Core changes: - Add the devm_pinctrl_register() API and switch all applicable drivers to use it, saving lots of lines of code all over the place. New drivers: - driver for the Broadcom NS2 SoC - subdriver for the PXA25x SoCs - subdriver for the AMLogic Meson GXBB SoC Driver improvements: - the Intel Baytrail driver now properly supports pin control - Nomadik, Rockchip, Broadcom BCM2835 support the .get_direction() callback in the GPIO portions - continued development and stabilization of several SH-PFC SoC subdrivers: r8a7795, r8a7790, r8a7794 etc" * tag 'pinctrl-v4.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (85 commits) Revert "pinctrl: tegra: avoid parked_reg and parked_bank" pinctrl: meson: Fix eth_tx_en bit index pinctrl: tegra: avoid parked_reg and parked_bank pinctrl: tegra: Correctly check the supported configuration pinctrl: amlogic: Add support for Amlogic Meson GXBB SoC pinctrl: rockchip: fix pull setting error for rk3399 pinctrl: stm32: Implement .pin_config_dbg_show() pinctrl: nomadik: hide nmk_gpio_get_mode when unused pinctrl: ns2: rename pinctrl_utils_dt_free_map pinctrl: at91: Merge clk_prepare and clk_enable into clk_prepare_enable pinctrl: at91: Make at91_gpio_template const pinctrl: baytrail: fix some error handling in debugfs pinctrl: ns2: add pinmux driver support for Broadcom NS2 SoC pinctrl: sirf/atlas7: trivial fix of spelling mistake on flagged pinctrl: sh-pfc: Kill unused variable in sh_pfc_remove() pinctrl: nomadik: implement .get_direction() pinctrl: nomadik: use BIT() with offsets consequently pinctrl: exynos5440: Use off-stack memory for pinctrl_gpio_range pinctrl: zynq: Use devm_pinctrl_register() for pinctrl registration pinctrl: u300: Use devm_pinctrl_register() for pinctrl registration ...
| * Revert "pinctrl: tegra: avoid parked_reg and parked_bank"Linus Walleij2016-05-137-14/+20
| | | | | | | | This reverts commit 1d18a3f0f0809f6c71f1f6e9e268ee904ce0b588.
| * pinctrl: meson: Fix eth_tx_en bit indexAlexander Müller2016-05-111-1/+1
| | | | | | | | | | | | | | | | Fix pinctrl eth_tx_en bit index according to Hardkernel ODROID-C1 datasheet. Signed-off-by: Alexander Müller <serveralex@gmail.com> Acked-by: Carlo Caione <carlo@endlessm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: tegra: avoid parked_reg and parked_bankLaxman Dewangan2016-05-117-20/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NVIDIA's Tegra210 support the park bit to make pinmux configuration enable/disable. If parked bit is 1 then configuration does not apply and if it is 0 then pinmux configuration applies. This is to support to avoid any glitch in pinmux configurations. The parked bit is part of mux register and mux bank and hence it is not required to have member for the parked_reg and parked bank very similar to other bit field of the same register. Remove the need of the parked register and parked bank and get whether parked function supported or not by parked_bit. This is to make the parked bit handling same as other fields of mux registers. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: tegra: Correctly check the supported configurationLaxman Dewangan2016-05-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pincontrol registers of Tegra chips has multiple filed per registers. There is two type of registers mux and drive. All configurations belongs to one of these registers. If any configurations are supported then <config>_bit is set to bit position of these registers otherwise -1 to not support it. The member is defined as s32 <config>_bit:6; So if config is not supported ifor given SoC then it is set to -1 in soc pinmmux table. In common driver code, to find out that given config is supported or not, it is checked as: s8 bit = <config>_bit; if (bit > 31) { /* Not supported config */ } But in this case, bit is s8 and hence for non supporting it is -1. Correct the check as: if (bit < 0) { /* Not supported config */ } Fixes: e4c02dced975cb ("pinctrl: tegra: use signed bitfields for optional fields") Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: amlogic: Add support for Amlogic Meson GXBB SoCCarlo Caione2016-05-114-1/+443
| | | | | | | | | | | | | | | | | | | | This patch adds the basic platform file to support the pin controller found on the Amlogic Meson GXBB SoCs. Signed-off-by: Carlo Caione <carlo@endlessm.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: rockchip: fix pull setting error for rk3399David Wu2016-05-111-52/+127
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes the pinctrl pull bias setting, since the pull up/down setting is the contrary for gpio0(just the gpio0a and gpio0b) and gpio2(just the gpio2c and gpio2d). From the TRM said, the gpio0a pull polarity setting: gpio0a_p GPIO0A PE/PS programmation section, every GPIO bit corresponding to 2bits[PS:PE] 2'b00: Z(Normal operation); 2'b11: weak 1(pull-up); 2'b01: weak 0(pull-down); 2'b10: Z(Normal operation); Then, the other gpios setting as the following: gpio1a_p (e.g.: gpio1, gpio2a, gpio2b, gpio3...) GPIO1A PU/PD programmation section, every GPIO bit corresponding to 2bits 2'b00: Z(Normal operation); 2'b01: weak 1(pull-up); 2'b10: weak 0(pull-down); 2'b11: Z(Normal operation); For example,(rk3399evb board) sdmmc_cd --->gpio0_a7 localhost / # io -r -4 0xff320040 ff320040: 00004d5f In general,the value should be 0x0000cd5f since the pin has been set in the dts. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Cc: linux-gpio@vger.kernel.org Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: stm32: Implement .pin_config_dbg_show()Patrice Chotard2016-05-101-0/+174
| | | | | | | | | | Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: nomadik: hide nmk_gpio_get_mode when unusedArnd Bergmann2016-05-091-14/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | nmk_gpio_get_mode is only used in one place, and that is conditionally compiled if DEBUG_FS is enabled. A recent cleanup has marked the definition 'static', which now leads to a warning: drivers/pinctrl/nomadik/pinctrl-nomadik.c:614:12: error: 'nmk_gpio_get_mode' defined but not used [-Werror=unused-function] static int nmk_gpio_get_mode(struct nmk_gpio_chip *nmk_chip, int offset) ^~~~~~~~~~~~~~~~~ Moving the function itself inside the #ifdef shuts it up again. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Fixes: 5e81e0a0913c ("pinctrl: nomadik: use BIT() with offsets consequently") Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: ns2: rename pinctrl_utils_dt_free_mapArnd Bergmann2016-05-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A conflict of two patches caused a build error when a function got renamed but a new user appeared in the other patch: drivers/pinctrl/bcm/pinctrl-ns2-mux.c:540:17: error: 'pinctrl_utils_dt_free_map' undeclared here (not in a function) .dt_free_map = pinctrl_utils_dt_free_map, ^~~~~~~~~~~~~~~~~~~~~~~~~ This renames the new user of pinctrl_utils_dt_free_map accordingly. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Fixes: d32f7fd3bbc3 ("pinctrl: Rename pinctrl_utils_dt_free_map to pinctrl_utils_free_map") Fixes: b5aa1006e4a9 ("pinctrl: ns2: add pinmux driver support for Broadcom NS2 SoC") Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: at91: Merge clk_prepare and clk_enable into clk_prepare_enableAlexander Stein2016-05-021-10/+3
| | | | | | | | | | | | | | This simplifies the normal as well as the error path. Signed-off-by: Alexander Stein <alexanders83@web.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: at91: Make at91_gpio_template constAlexander Stein2016-05-021-1/+1
| | | | | | | | | | | | | | This template is only assigned, so make it const. Signed-off-by: Alexander Stein <alexanders83@web.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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