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* Merge tag 'armsoc-drivers' of ↵Linus Torvalds2016-10-071-11/+12
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver updates from Arnd Bergmann: "Driver updates for ARM SoCs, including a couple of newly added drivers: - The Qualcomm external bus interface 2 (EBI2), used in some of their mobile phone chips for connecting flash memory, LCD displays or other peripherals - Secure monitor firmware for Amlogic SoCs, and an NVMEM driver for the EFUSE based on that firmware interface. - Perf support for the AppliedMicro X-Gene performance monitor unit - Reset driver for STMicroelectronics STM32 - Reset driver for SocioNext UniPhier SoCs Aside from these, there are minor updates to SoC-specific bus, clocksource, firmware, pinctrl, reset, rtc and pmic drivers" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (50 commits) bus: qcom-ebi2: depend on HAS_IOMEM pinctrl: mvebu: orion5x: Generalise mv88f5181l support for 88f5181 clk: mvebu: Add clk support for the orion5x SoC mv88f5181 dt-bindings: EXYNOS: Add Exynos5433 PMU compatible clocksource: exynos_mct: Add the support for ARM64 perf: xgene: Add APM X-Gene SoC Performance Monitoring Unit driver Documentation: Add documentation for APM X-Gene SoC PMU DTS binding MAINTAINERS: Add entry for APM X-Gene SoC PMU driver bus: qcom: add EBI2 driver bus: qcom: add EBI2 device tree bindings rtc: rtc-pm8xxx: Add support for pm8018 rtc nvmem: amlogic: Add Amlogic Meson EFUSE driver firmware: Amlogic: Add secure monitor driver soc: qcom: smd: Reset rx tail rather than tx memory: atmel-sdramc: fix a possible NULL dereference reset: hi6220: allow to compile test driver on other architectures reset: zynq: add driver Kconfig option reset: sunxi: add driver Kconfig option reset: stm32: add driver Kconfig option reset: socfpga: add driver Kconfig option ...
| * Merge tag 'mvebu-drivers-4.9-1' of git://git.infradead.org/linux-mvebu into ↵Arnd Bergmann2016-09-211-11/+12
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | next/drivers Pull "mvebu drivers for 4.9 (part 1)" from Gregory CLEMENT: - Add pinctrl and clk support for the Orion5x SoC mv88f5181 variant * tag 'mvebu-drivers-4.9-1' of git://git.infradead.org/linux-mvebu: pinctrl: mvebu: orion5x: Generalise mv88f5181l support for 88f5181 clk: mvebu: Add clk support for the orion5x SoC mv88f5181
| | * pinctrl: mvebu: orion5x: Generalise mv88f5181l support for 88f5181Jamie Lentin2016-09-211-11/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As far as I'm aware the mv88f5181-b1 and mv88f5181l are the same at the pinctrl level, so re-use the definitions for both. [gregory.clement@free-electrons.com: fix commit title] Signed-off-by: Jamie Lentin <jm@lentin.co.uk> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* | | Merge tag 'gpio-v4.9-1' of ↵Linus Torvalds2016-10-051-1/+0
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio Pull GPIO updates from Linus Walleij: "This is the bulk of GPIO changes for the v4.9 series: Subsystem improvements: - do away with the last users of the obsolete Kconfig options ARCH_REQUIRE_GPIOLIB and ARCH_WANT_OPTIONAL_GPIOLIB (the latter always sounded like an item on a wishlist to Santa Claus to me). We can now select GPIOLIB and be done with it, for all archs. After some struggle it even work on UM. Not that it has GPIO, but if it wants to, it can select the library. - continued efforts to make drivers properly either tristate or bool. - introduce a warning for drivers assigning default triggers to their irqchip lines when probed from device tree, so we find and fix these ambigous drivers. It is agreed that in the OF config path, the device tree defines trigger characteristics. - the same warning, mutatis mutandis, for ACPI-probed GPIO irqchips. - we introduce the ability to mark certain IRQ lines as "unusable" as they can be taken by BIOS/firmware, unrouted in silicon and generally nasty if you use them, and such things. This is put to good use in the STMPE driver and also in the Cherryview pin control driver. - a new "mockup" virtual GPIO device that can be used for testing. The plan is to add unit tests under tools/* for exercising this device and verify that the kernel code paths are working as they should. - make memory-mapped I/O-drivers depend on HAS_IOMEM. This was implicit all the time, but when people started building UM with allyesconfig or allmodconfig it exploded in their face. - move some stray bits of device tree and ACPI HW description callbacks down into their respective implementation silo. These were causing issues when compiling on !HAS_IOMEM as well, so now eventually UM compiles the GPIOLIB library if it wants to. New drivers: - new driver for the Aspeed GPIO front-end companion to the pin controller merged through the pin control tree. - new driver for the LP873x PMIC GPIO portions. - new driver for Technologic Systems' I2C FPGA GPIO such as TS4900, TS-7970, TS-7990 and TS-4100. - new driver for the Broadcom BCM63xx series including BCM6338 and BCM6345. - new driver for the Intel WhiskeyCove PMIC GPIO. - new driver for the Allwinner AXP209 PMIC GPIO portions. - new driver for Diamond Systems 48 line GPIO-MM, another of these port-mapped I/O expansion cards. - support the STMicroelectronics STMPE1600 variant in the STMPE driver. Driver improvements: - the STMPE driver now supports rising/falling edge detection properly for IRQs. - the PCA954x will now fetch and enable its VCC regulator properly. - major rework of the PCA953x driver with the goal of eventually switching it over to use regmap and thus modernize it even more. - switch the IOP driver to use the generic MMIO GPIO library. - move the ages old HTC EGPIO (extended GPIO) GPIO expander driver over to this subsystem from MFD, achieveing some separation of concerns" * tag 'gpio-v4.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (81 commits) gpio: add missing static inline gpio: OF: localize some gpiochip init functions gpio: acpi: separation of concerns gpio: OF: separation of concerns gpio: make memory-mapped drivers depend on HAS_IOMEM gpio: stmpe: use BIT() macro gpio: stmpe: forbid unused lines to be mapped as IRQs mfd/gpio: Move HTC GPIO driver to GPIO subsystem gpio: MAINTAINERS: Add an entry for GPIO mockup driver gpio/mockup: add virtual gpio device gpio: Added zynq specific check for special pins on bank zero gpio: axp209: Implement get_direction gpio: aspeed: remove redundant return value check gpio: loongson1: remove redundant return value check ARM: omap2: fix missing include gpio: tc3589x: fix up complaints on unsigned gpio: tc3589x: add .get_direction() and small cleanup gpio: f7188x: use gpiochip_get_data instead of container_of gpio: tps65218: use devm_gpiochip_add_data() for gpio registration gpio: aspeed: fix return value check in aspeed_gpio_probe() ...
| * | | gpio: acpi: separation of concernsLinus Walleij2016-10-031-1/+0
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The generic GPIO library directly implement code for acpi_find_gpio() which is only used with CONFIG_ACPI. This was probably done because OF did the same thing, but I removed that so remove this too. Rename the internal acpi_find_gpio() in gpiolib-acpi.c to acpi_populate_gpio_lookup() which seems to be more appropriate anyway so as to avoid a namespace clash with the same function. Make the stub return -ENOENT rather than -ENOSYS (as that is for syscalls!). For some reason the sunxi pin control driver was including the private gpiolib header, it works just fine without it so remove that oneliner. Cc: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: qcom: fix masking of pinmux functionsJohn Crispin2016-10-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following commit introduced a regression by not properly masking the calculated value. Fixes: 47a01ee9a6c3 ("pinctrl: qcom: Clear all function selection bits") Signed-off-by: John Crispin <john@phrozen.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Stephen Boyd <stephen.boyd@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | Merge branch 'fixes' into develLinus Walleij2016-09-232-10/+2
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| * | | pinctrl: samsung: Remove an always false dev->of_node testSylwester Nawrocki2016-09-121-9/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | samsung_pinctrl_probe() can be called only after matching the driver by the compatible string so this already implies a non null dev->of_node. Remove the always false test and related error trace. While at it drop another error log in case of memory allocation failure - any errors are logged by the memory subsystem. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: intel: merrifield: fix dup size in probeVincent Stehlé2016-09-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In function mrfld_pinctrl_probe(), when duplicating the mrfld_families array the requested memory region length is multiplied once too many by the number of elements in the original array. Fix this to spare some memory. Fixes: 4e80c8f505741cbd ("pinctrl: intel: Add Intel Merrifield pin controller support") Signed-off-by: Vincent Stehlé <vincent.stehle@intel.com> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | | pinctrl: intel: Configure GPIO chip IRQ as wakeup interruptsNilesh Bacchewar2016-09-231-28/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On some Intel BXT platform, wake-up from suspend-to-idle on pressing power-button is not working. Its noticed that gpio-keys driver marking the second level IRQ/power-button as wake capable but Intel pintctrl driver is missing to mark GPIO chip/controller IRQ which first level IRQ as wake cable if its GPIO pin IRQ is wakeble. So, though the first level IRQ gets generated on power-button press, since it is not marked as wake capable resume/wake-up flow is not happening. Intel pintctrl/GPIO driver need to mark GPIO chip/controller IRQ (first level IRQ) as wake capable iff GPIO pin's IRQ (second level IRQ) is marked as wake cable. Changes in v2: - Add missing irq initialisation. Signed-off-by: Nilesh Bacchewar <nilesh.bacchewar@intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | | pinctrl: cherryview: Convert to use devm_gpiochip_add_data()Mika Westerberg2016-09-231-18/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This simplifies the error handling and allows us to drop the whole chv_pinctrl_remove() function. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | | pinctrl: cherryview: Do not add all southwest and north GPIOs to IRQ domainMika Westerberg2016-09-231-1/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It turns out that for north and southwest communities, they can only generate GPIO interrupts for lower 8 interrupts (IntSel value). The upper part (8-15) can only generate GPEs (General Purpose Events). Now the reason why EC events such as pressing hotkeys does not work if we mask all the interrupts is that in order to generate either interrupts or GPEs the INTMASK register must have that particular interrupt unmasked. In case of GPEs the CPU does not trigger normal interrupt (and thus the GPIO driver does not see it) but instead it causes SCI (System Control Interrupt) to be triggered with the GPE in question set. To make this all work as expected we only add those GPIOs to the IRQ domain that can actually generate interrupts (IntSel value 0-7) and skip others. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | | Merge tag 'v4.8-rc6' into develLinus Walleij2016-09-237-48/+15
|\ \ \ \ | |/ / / | | | | | | | | Linux 4.8-rc6
| * | | pinctrl: sunxi: fix uart1 CTS/RTS pins at PG on A23/A33Icenowy Zheng2016-08-232-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PG8, PG9 is said to be the CTS/RTS pins for UART1 according to the A23/33 datasheets. However, the function is wrongly named "uart2" in the pinctrl driver. This patch fixes this by modifying them to be named "uart1". Cc: stable@vger.kernel.org Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: cherryview: Do not mask all interrupts in probeMika Westerberg2016-08-221-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Cherryview GPIO controller has 8 or 16 wires connected to the I/O-APIC which can be used directly by the platform/BIOS or drivers. One such wire is used as SCI (System Control Interrupt) which ACPI depends on to be able to trigger GPEs (General Purpose Events). The pinctrl driver itself uses another IRQ resource which is wire OR of all the 8 (or 16) wires and follows what BIOS has programmed to the IntSel register of each pin. Currently the driver masks all interrupts at probe time and this prevents these direct interrupts from working as expected. The reason for this is that some early stage prototypes had some pins misconfigured causing lots of spurious interrupts. We fix this by leaving the interrupt mask untouched. This allows SCI and other direct interrupts work properly. What comes to the possible spurious interrupts we switch the default handler to be handle_bad_irq() instead of handle_simple_irq() (which was not correct anyway). Reported-by: Yu C Chen <yu.c.chen@intel.com> Reported-by: Anisse Astier <anisse@astier.eu> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: pistachio: fix mfio pll_lock pinmuxJames Hartley2016-08-221-6/+6
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A previous patch attempted to fix the pinmuxes for mfio 84 - 89, but it omitted a change to pistachio_pin_group pistachio_groups, which results in incorrect pll_lock signals being routed. Apply the correct mux settings throughout the driver. fixes: cefc03e5995e ("pinctrl: Add Pistachio SoC pin control driver") fixes: e9adb336d0bf ("pinctrl: pistachio: fix mfio84-89 function description and pinmux.") Cc: <stable@vger.kernel.org> # 4.4.x- Signed-off-by: James Hartley <james.hartley@imgtec.com> Reviewed-by: Sifan Naeem <Sifan.Naeem@imgtec.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: intel: merrifield: Add missed headerAndy Shevchenko2016-08-101-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On x86 builds the absense of <linux/io.h> makes static analyzer and compiler unhappy which fails to build the driver. CHECK drivers/pinctrl/intel/pinctrl-merrifield.c drivers/pinctrl/intel/pinctrl-merrifield.c:518:17: error: undefined identifier 'readl' drivers/pinctrl/intel/pinctrl-merrifield.c:570:17: error: undefined identifier 'readl' drivers/pinctrl/intel/pinctrl-merrifield.c:575:9: error: undefined identifier 'writel' drivers/pinctrl/intel/pinctrl-merrifield.c:645:17: error: undefined identifier 'readl' CC drivers/pinctrl/intel/pinctrl-merrifield.o drivers/pinctrl/intel/pinctrl-merrifield.c: In function ‘mrfld_pin_dbg_show’: drivers/pinctrl/intel/pinctrl-merrifield.c:518:10: error: implicit declaration of function ‘readl’ [-Werror=implicit-function-declaration] value = readl(bufcfg); ^ drivers/pinctrl/intel/pinctrl-merrifield.c: In function ‘mrfld_update_bufcfg’: drivers/pinctrl/intel/pinctrl-merrifield.c:575:2: error: implicit declaration of function ‘writel’ [-Werror=implicit-function-declaration] writel(value, bufcfg); ^ cc1: some warnings being treated as errors Add header to the top of the module. Fixes: 4e80c8f50574 ("pinctrl: intel: Add Intel Merrifield pin controller support") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl/amd: Remove the default de-bounce timeAgrawal, Nitesh-kumar2016-08-101-20/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the function amd_gpio_irq_enable() and amd_gpio_direction_input(), remove the code which is setting the default de-bounce time to 2.75ms. The driver code shall use the same settings as specified in BIOS. Any default assignment impacts TouchPad behaviour when the LevelTrig is set to EDGE FALLING. Cc: stable@vger.kernel.org Reviewed-by:  Ken Xue <Ken.Xue@amd.com> Signed-off-by: Nitesh Kumar Agrawal <Nitesh-kumar.Agrawal@amd.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: pistachio: Drop pinctrl_unregister for devm_ registered deviceWei Yongjun2016-08-101-8/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's not necessary to unregister pin controller device registered with devm_pinctrl_register() and using pinctrl_unregister() leads to a double free. This is detected by Coccinelle semantic patch. Signed-off-by: Wei Yongjun <weiyj.lk@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: meson: Drop pinctrl_unregister for devm_ registered deviceWei Yongjun2016-08-101-7/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | It's not necessary to unregister pin controller device registered with devm_pinctrl_register() and using pinctrl_unregister() leads to a double free. This is detected by Coccinelle semantic patch. Fixes: e649f7ec8c5f ("pinctrl: meson: Use devm_pinctrl_register() for pinctrl registration") Signed-off-by: Wei Yongjun <weiyj.lk@gmail.com> Reviewed-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> Acked-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: nomadik: don't default-flag IRQs as fallingLinus Walleij2016-09-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no point in adding any default trigger for these GPIO interrupts: the device tree should contain all trigger information and the platforms using the driver boots exclusively from device tree. Also the boot log is nagging me to fix this: [ 0.771057] ------------[ cut here ]------------ [ 0.775695] WARNING: CPU: 0 PID: 1 at ../drivers/gpio/gpiolib.c:1622 _gpiochip_irqchip_add+0x138/0x160 [ 0.785034] /soc/gpio@8012e000: Ignoring 2 default trigger (...) [ 0.942962] gpio 8012e000.gpio: at address e08f8000 (etc ad nauseam) Suggested-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: st: Remove STiH415/6 SoC pinctrl driver support.Peter Griffin2016-09-151-62/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | STiH415/6 SoC support is being removed from the kernel. This patch updates the ST pinctrl driver and removes references to these obsolete platforms. As some structures referenced by STiH407 based configuration were shared with STiH416 we update these names to match the remaining supported platform. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Cc: <linus.walleij@linaro.org> Cc: <linux-gpio@vger.kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: amlogic: gxbb: add i2c pinsJerome Brunet2016-09-151-0/+30
| | | | | | | | | | | | | | | | Add EE domains pins for the i2c devices A,B,C Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: amlogic: gxbb: add nand pinsJerome Brunet2016-09-151-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | Add EE domains pins for the NAND flash controller. Even tough we have no driver for the NAND flash controller yet, we need to have these pins in pinctrl as the actual pin are shared with the spifc controller. The bootloader on the S905-P200 setup pinmux for the NAND controller so we need the kernel to properly deactivate this if necessary. Acked-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: stm32: add IRQ_DOMAIN_HIERARCHY dependencyArnd Bergmann2016-09-151-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The newly added irqchip support for the stm32 pinctrl driver uses hierarchical IRQ domains as provided by the NVIC primary irqchip. This works great for any configuration that may be relevant on stm32, but when doing compile-testing (randconfig), we can enable it without NVIC or any other primary irqchip that enables IRQ_DOMAIN_HIERARCHY: drivers/pinctrl/stm32/pinctrl-stm32.c:212:13: error: 'irq_chip_eoi_parent' undeclared here (not in a function) drivers/pinctrl/stm32/pinctrl-stm32.c:213:20: error: 'irq_chip_mask_parent' undeclared here (not in a function) drivers/pinctrl/stm32/pinctrl-stm32.c:214:20: error: 'irq_chip_unmask_parent' undeclared here (not in a function) drivers/pinctrl/stm32/pinctrl-stm32.c:215:20: error: 'irq_chip_set_type_parent' undeclared here (not in a function) This adds a Kconfig dependency to limit compile-testing to configurations that have IRQ_DOMAIN_HIERARCHY already enabled. It's not obvious whether we should use 'depends on' or 'select' here, I think either one works, with 'depends on' being more intuitive, while 'select' would be less likely to cause dependency loops. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Fixes: 0eb9f683336d ("pinctrl: Add IRQ support to STM32 gpios") Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: amlogic: gxbb: add spi nor pinsJerome Brunet2016-09-151-0/+14
| | | | | | | | | | | | | | | | Add EE domains pins for the SPI flash controller Acked-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | Merge tag 'sh-pfc-for-v4.9-tag3' of ↵Linus Walleij2016-09-146-9/+207
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.9 (take three) - Return pinconf with arguments in packed format, - MSIOF and QSPI pin groups on R-Car V2H, - Voltage switching for SDHI on R-Car M2-W, E2, and M3-W.
| * | pinctrl: sh-pfc: r8a7794: Implement voltage switching for SDHISimon Horman2016-09-141-1/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All the SHDIs can operate with either 3.3V or 1.8V signals, depending on negotiation with the card. Based on work by Wolfram Sang for the r8a7790. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: sh-pfc: r8a7791: Implement voltage switching for SDHISimon Horman2016-09-141-1/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All the SHDIs can operate with either 3.3V or 1.8V signals, depending on negotiation with the card. Based on work by Wolfram Sang for the r8a7790. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: sh-pfc: Add PORT_GP_24 helper macroSimon Horman2016-09-141-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | This follows the style of existing PORT_GP_X macros and will be used by a follow-up patch for the r8a7791 SoC. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: sh-pfc: r8a7796: Add voltage switch operations for SDHISimon Horman2016-09-121-2/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch supports the {get,set}_io_voltage operations of SDHI. This operates the POCCTRL0 register on R8A7796 SoC and makes 1.8v/3.3v voltage switch. Based on work by Takeshi Kihara and Wolfram Sang. Cc: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: sh-pfc: Return pinconf with arguments in packed formatNiklas Söderlund2016-09-121-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pinconf-generic code expects configurations with arguments to be returned in a packed format in order to be displayed properly by pinconf_generic_dump_one(). Reading /sys/kernel/debug/pinctrl/e6060000.pfc/pinconf-pins on r8a7795/salvator-x now shows: pin 101 (GP_3_5): output drive strength (9 mA), pin power source (3300 selector) Instead of: pin 101 (GP_3_5): output drive strength (0 mA), pin power source (0 selector) Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: sh-pfc: r8a7792: Add MSIOF pin groupsSergei Shtylyov2016-09-121-0/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add MSIOF0/1 pin groups to the R8A7792 PFC driver. Based on the original (and large) patch by Vladimir Barinov <vladimir.barinov@cogentembedded.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: sh-pfc: r8a7792: Add QSPI pin groupsSergei Shtylyov2016-09-121-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add QSPI pin groups to the R8A7792 PFC driver. Based on the original (and large) patch by Vladimir Barinov <vladimir.barinov@cogentembedded.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | | pinctrl: meson-gxbb: add the missing SDIO interrupt pinMartin Blumenstingl2016-09-131-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the SDIO interrupt pin which can be used by sd_emmc_a. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Suggested-by: Neil Armstrong <narmstrong@baylibre.com> Fixes: 29885a656511 ("pinctrl: meson-gxbb: add the pins for the SDIO/sd_emmc_a controller") Acked-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: aspeed: fix regmap error handlingArnd Bergmann2016-09-131-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The newly added aspeed driver tries to check for a negative return value from a pinctrl function, but stores the intermediate value in a 'bool' variable, which cannot work: drivers/pinctrl/aspeed/pinctrl-aspeed.c: In function 'aspeed_sig_expr_set': drivers/pinctrl/aspeed/pinctrl-aspeed.c:192:11: error: comparison of constant '0' with boolean expression is always false [-Werror=bool-compare] This slightly reworks the logic to use an explicit comparison with zero before assigning to the temporary variable. Reported-by: Colin King <colin.king@canonical.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: mediatek: constify gpio_chip structuresJulia Lawall2016-09-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These structures are only used to copy into other structures, so declare them as const. The semantic patch that makes this change is as follows: (http://coccinelle.lip6.fr/) // <smpl> @r disable optional_qualifier@ identifier i; position p; @@ static struct gpio_chip i@p = { ... }; @ok@ identifier r.i; expression e; position p; @@ e = i@p; @bad@ position p != {r.p,ok.p}; identifier r.i; struct gpio_chip e; @@ e@i@p @depends on !bad disable optional_qualifier@ identifier r.i; @@ static +const struct gpio_chip i = { ... }; // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: stm32: constify gpio_chip structuresJulia Lawall2016-09-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These structures are only used to copy into other structures, so declare them as const. The semantic patch that makes this change is as follows: (http://coccinelle.lip6.fr/) // <smpl> @r disable optional_qualifier@ identifier i; position p; @@ static struct gpio_chip i@p = { ... }; @ok@ identifier r.i; expression e; position p; @@ e = i@p; @bad@ position p != {r.p,ok.p}; identifier r.i; struct gpio_chip e; @@ e@i@p @depends on !bad disable optional_qualifier@ identifier r.i; @@ static +const struct gpio_chip i = { ... }; // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl/amd: switch to using a bool for levelAgrawal, Nitesh-kumar2016-09-131-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The earlier patch can be simplified by using a bool to indicate level trigger. Reviewed-by: Pankaj Sen <Pankaj.Sen@amd.com> Signed-off-by: Nitesh Kumar Agrawal <Nitesh-kumar.Agrawal@amd.com> [Fixup to earlier manually applied patch] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: Add IRQ support to STM32 gpiosAlexandre TORGUE2016-09-132-1/+163
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds IRQ support to STM32 gpios. The EXTI controller has 16 lines dedicated to GPIOs. EXTI line n can be connected to only line n of one of the GPIO ports, for example EXTI0 can be connected to either PA0, or PB0, or PC0... This port selection is done by specifying the port number into System Config registers. Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: imx: accept gpio request/free from pinctrlVladimir Zapolskiy2016-09-121-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While only Freescale Vybrid SoC has settings of GPIO capabilities done by iomux controller, it is only a matter of GPIO controller driver implementation for the rest of Freescale/NXP SoCs from iMX series. As a practical example on GPIO request a pad function should be switched to GPIO, but because this requires updates to all particular iMX pinctrl drivers, for simplicity at the moment add only a proper connection between shared pinctrl-imx and pinctrl/pinmux core, namely .gpio_request_enable/.gpio_disable_free/.gpio_set_direction callbacks should return success to a caller. This change allows to progress by adding request/free callbacks into gpio-mxc.c driver. Signed-off-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl/at91: Don't provide a default trigger typeMarc Zyngier2016-09-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | at91 used to set a default trigger type for GPIO interrupts in order to cope with the old board files. These days are long gone, and it all gets probed through DT. Andras Szemzo reported that the Ethernet device on his board was bailing to be probed, due to a conflict in interrupt trigger. Surely enough, this is due to this default trigger still being present, and turning this into a IRQ_TYPE_NONE fixes the issue. Reported-by: Andras Szemzo <szemzo.andras@gmail.com> Tested-by: Andras Szemzo <szemzo.andras@gmail.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: sunxi: Remove unsupported PWM channel pinmux in H3Milo Kim2016-09-081-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | H3 has single PWM channel. The second PWM channel is not supported, so the pinctrl function should be removed. Signed-off-by: Milo Kim <woogyom.kim@gmail.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: bcm281xx: constify pinctrl_ops and pinmux_ops structuresJulia Lawall2016-09-071-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Check for pinctrl_ops and pinmux_ops structures that are only stored in the pctlops field and the pmxops field, respectively, of a pinctrl_desc structure. These fields are declared const, so pinctrl_ops and pinmux_ops structures that have this property can be declared as const also. The semantic patch that makes this change in the pinctrl_ops is as follows. The pinmux_ops case is similar. (http://coccinelle.lip6.fr/) // <smpl> @r disable optional_qualifier@ identifier i; position p; @@ static struct pinctrl_ops i@p = { ... }; @ok@ identifier r.i; struct pinctrl_desc e; position p; @@ e.pctlops = &i@p; @bad@ position p != {r.p,ok.p}; identifier r.i; struct pinctrl_ops e; @@ e@i@p @depends on !bad disable optional_qualifier@ identifier r.i; @@ static +const struct pinctrl_ops i = { ... }; // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: nsp: constify pinctrl_ops and pinmux_ops structuresJulia Lawall2016-09-071-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Check for pinctrl_ops and pinmux_ops structures that are only stored in the pctlops field and the pmxops field, respectively, of a pinctrl_desc structure. These fields are declared const, so pinctrl_ops and pinmux_ops structures that have this property can be declared as const also. The semantic patch that makes this change in the pinctrl_ops is as follows. The pinmux_ops case is similar. (http://coccinelle.lip6.fr/) // <smpl> @r disable optional_qualifier@ identifier i; position p; @@ static struct pinctrl_ops i@p = { ... }; @ok@ identifier r.i; struct pinctrl_desc e; position p; @@ e.pctlops = &i@p; @bad@ position p != {r.p,ok.p}; identifier r.i; struct pinctrl_ops e; @@ e@i@p @depends on !bad disable optional_qualifier@ identifier r.i; @@ static +const struct pinctrl_ops i = { ... }; // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: ns2: constify pinctrl_ops and pinmux_ops structuresJulia Lawall2016-09-071-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Check for pinctrl_ops and pinmux_ops structures that are only stored in the pctlops field and the pmxops field, respectively, of a pinctrl_desc structure. These fields are declared const, so pinctrl_ops and pinmux_ops structures that have this property can be declared as const also. The semantic patch that makes this change in the pinctrl_ops is as follows. The pinmux_ops case is similar. (http://coccinelle.lip6.fr/) // <smpl> @r disable optional_qualifier@ identifier i; position p; @@ static struct pinctrl_ops i@p = { ... }; @ok@ identifier r.i; struct pinctrl_desc e; position p; @@ e.pctlops = &i@p; @bad@ position p != {r.p,ok.p}; identifier r.i; struct pinctrl_ops e; @@ e@i@p @depends on !bad disable optional_qualifier@ identifier r.i; @@ static +const struct pinctrl_ops i = { ... }; // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl/amd: Configure GPIO register using BIOS settingsAgrawal, Nitesh-kumar2016-09-071-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the function amd_gpio_irq_set_type, use the settings provided by the BIOS,when the LevelTrig is Edge and activeLevel is HIGH, to configure the GPIO registers. Ignore the settings from client. Reviewed-by: Pankaj Sen <Pankaj.Sen@amd.com> Signed-off-by:Nitesh Kumar Agrawal <Nitesh-kumar.Agrawal@amd.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: sunxi: Add GR8 controller supportMylène Josserand2016-09-073-0/+546
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Just like the other member of the sunxi family, let's add a pinctrl table for the muxing options. Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: Add pinctrl-aspeed-g5 driverAndrew Jeffery2016-09-073-0/+817
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: Add pinctrl-aspeed-g4 driverAndrew Jeffery2016-09-073-0/+1240
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A subset of the pins and functions are exposed. The selection of functions and pins is driven by the development of OpenBMC[1] on the AST2400 SoC, particularly around booting the OpenPOWER Palmetto development machine. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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