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path: root/drivers/pinctrl/pxa
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* pinctrl: pxa: Use devm_pinctrl_register() for pinctrl registrationLaxman Dewangan2016-04-211-1/+1
| | | | | | | | | | | | | Use devm_pinctrl_register() for pin control registration and clean the error path. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Cc: Daniel Mack <daniel@zonque.org> Cc: Haojian Zhuang <haojian.zhuang@gmail.com> Cc: Robert Jarzmik <robert.jarzmik@free.fr> Cc: linux-arm-kernel@lists.infradead.org Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: pxa: add pxa25x architectureRobert Jarzmik2016-04-143-1/+284
| | | | | | | | | Add the pxa25x architecture, which is a pxa2xx with 85 pins. The registers spacing, and pins logic is common to pxa2xx, only the pins and their alternate function are specific to pxa25x. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: Rename pinctrl_utils_dt_free_map to pinctrl_utils_free_mapIrina Tirdea2016-04-011-1/+1
| | | | | | | | | | | Rename pinctrl_utils_dt_free_map to pinctrl_utils_free_map, since it does not depend on device tree despite the current name. This will enforce a consistent naming in pinctr-utils.c and will make it clear it can be called from outside device tree (e.g. from ACPI handling code). Signed-off-by: Irina Tirdea <irina.tirdea@intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: pxa2xx: export symbolsLinus Walleij2016-03-091-0/+2
| | | | | | | | The pxa2xxx fails some automated builds because of unexported symbols. Reported-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: pxa: pxa2xx: add pin control skeletonRobert Jarzmik2015-12-151-2/+2
| | | | | | | | | | | The wrong free functions were used to release temporary buffers. This didn't show up in the normal driver's life. Yet in suspend to RAM, the managed resource list is walked, and as memory was released, the list is corrupted and make the kernel Oops. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: pxa: add pxa27x architectureRobert Jarzmik2015-12-103-0/+576
| | | | | | | | | Add the pxa27x architecture, which is a pxa2xx with 128 pins. The registers spacing, and pins logic is common to pxa2xx, only the pins and their alternate function are specific to pxa27x. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: pxa: pxa2xx: add pin configuration supportRobert Jarzmik2015-12-101-0/+63
| | | | | | | | | | | | | | Add pin configuration for pxa2xx architectures. PXA doesn't provide any bias, push, pull capabilities. The only capability is to set a state for the pins when the platform enter sleep or deep sleep mode. The state of a pin is set by : - whether the GPIO direction was input or output - if it is output, a register set programs whether the pin should be held to ground or VccIO Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: pxa: pxa2xx: add pin muxingRobert Jarzmik2015-12-101-0/+121
| | | | | | | | | | | | | | | | | The driver is inspired from the sunxi driver. The pxa architecture specificities leading to the driver are : - each pin has 8 possible alternate functions - 4 of these are output kind - 4 of these are input kind - there is always a "gpio input" and "gpio output" function - the function matrix is very scattered : - some functions can be found on 5 different pads - the number of functions is greater than the number of pins - there is no "topology" grouping of pins (such as all SPI in one corner of the die) Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: pxa: pxa2xx: add pin control skeletonRobert Jarzmik2015-12-103-0/+353
Add a pincontrol driver for pxa2xx architecture, encompassing all pxa25x and pxa27x variants. This is only the pin muxing part of the driver. One specific consideration is also the memory space (MMIO), which is intertwined with the GPIO registers. To make things worse, the GPIO direction register also affect pin muxing, as it chooses the "kind" of pin, ie. the 4 output functions or 4 input functions. The mapping between pinctrl notions and PXA Technical Reference Manual is as follows : - a pin is obviously a pin - a group is also a pin, ie. group P101 is the pin 101 - a mux function is an alternate function (ie. gpio-in, gpio-out, MMCLK, BTRTS, etc ...) The individual architecture (pxa27x, pxa25x) instantiate a pin control by providing a table of pins, each pin being provided a list of PXA_FUNCTION (alternate functions). Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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