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* phy: qcom-qusb2: add NVMEM dependencyTobias Regnery2017-04-101-0/+1
| | | | | | | | | | | | | | | | | | | With CONFIG_NVMEM=m and CONFIG_PHY_QCOM_QUSB2=y we get a link error from calls to devm_nvmem_cell_get and nvmem_cell_read: drivers/built-in.o: In function `qusb2_phy_probe': binder.c:(.text+0x4750): undefined reference to `devm_nvmem_cell_get' drivers/built-in.o: In function `qusb2_phy_init': binder.c:(.text+0x489c): undefined reference to `nvmem_cell_read' Fix this by adding a Kconfig dependency to ensure we can only have this driver built in when the nvmem functions are also built in or we see the empty stub functions. We can still build this driver as a module when the nvmem core is build as module, too. Fixes: deffad633413 ("phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips") Signed-off-by: Tobias Regnery <tobias.regnery@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: rockchip-usb: Add vbus regulator support.Sjoerd Simons2017-04-101-0/+19
| | | | | | | | | On rockchip devices vbus is supplied by a separate power supply, often through a regulator. Add support for describing the the regulator in device-tree following the same convention as several other usb phy's. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: bcm-ns-usb3: split all writes into reg & val pairsRafał Miłecki2017-04-101-20/+49
| | | | | | | | | | | | | | | | | | So far all the PHY initialization was implemented using some totally magic values. There was some pattern there but it wasn't clear what is it about. Thanks to the patch submitted by Broadcom: [PATCH 5/6] phy: Add USB3 PHY support for Broadcom NSP SoC and the upstream "iproc-mdio" driver we now know there is a MDIO bus underneath with PHY(s) and their registers. It allows us to clean the driver a bit by making all these values less magical. The next step is switching to using a proper MDIO layer. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Acked-by: Jon Mason <jon.mason@broadcom.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: qcom-qmp: new qmp phy driver for qcom-chipsetsVivek Gautam2017-04-103-0/+1162
| | | | | | | | | | | | Qualcomm SOCs have QMP phy controller that provides support to a number of controller, viz. PCIe, UFS, and USB. Add a new driver, based on generic phy framework, for this phy controller. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Tested-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chipsVivek Gautam2017-04-103-0/+504
| | | | | | | | | | PHY transceiver driver for QUSB2 phy controller that provides HighSpeed functionality for DWC3 controller present on Qualcomm chipsets. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: rockchip-inno-usb2: add support of usb2-phy for rk3328Meng Dongyang2017-04-101-0/+44
| | | | | | | | | Add usb2-phy config information in the data of match table for rk3328. Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: phy-mt65xx-usb3: disable 100uA extraction from SS port to HS portChunfeng Yun2017-04-101-14/+10
| | | | | | | | | | There will be a problem if SS port is diasbled and HS port extracts 100uA from SS port, so disable extract 100uA from SS port in the case, when disable it, PA0_RG_USB20_INTR_EN should be set, otherwise HS port only works on LS. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: phy-mt65xx-usb3: add support for new version phyChunfeng Yun2017-04-101-128/+218
| | | | | | | | | | | There are some variations from mt2701 to mt2712: 1. banks shared by multiple ports are put back into each port, such as SPLLC and U2FREQ; 2. add a new bank MISC for u2port, and CHIP for u3port; 3. bank's offset in each port are also rearranged; Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: phy-mt65xx-usb3: move clock from phy node into port nodesChunfeng Yun2017-04-101-2/+25
| | | | | | | | | each port has its own reference clock, the HighSpeed port is 48M, and the SuperSpeed port is usually 26M, put them into port node for flexibility, this can close clock if the port is not used. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: phy-mt65xx-usb3: split SuperSpeed port into two onesChunfeng Yun2017-04-101-74/+75
| | | | | | | | | | | | | | | | | Currently usb3 port in fact includes two sub-ports, but it is not flexible for some cases, such as following one: usb3 port0 includes u2port0 and u3port0; usb2 port0 includes u2port1; If wants to support only HS, we can use u2port0 or u2port1, when select u2port0, u3port0 is not needed; If wants to support SS, we can compound u2port0 and u3port0, or u2port1 and u3port0, if select latter one, u2port0 is not needed. So it's more flexible to split usb3 port into two ones and also try best to save power by disabling unnecessary ports. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: phy-mt65xx-usb3: increase LFPS filter thresholdChunfeng Yun2017-04-101-0/+9
| | | | | | | | | Increase LFPS filter threshold to avoid some fake remote wakeup signal which cause U3 link fail and link to U2 only at about 0.01% probability. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: phy-mt65xx-usb3: improve RX detection stable timeChunfeng Yun2017-04-101-0/+18
| | | | | | | | | The default value of RX detection stable time is 10us, and this margin is too big for some critical cases which cause U3 link fail and link to U2(probability is about 1%). So change it to 5us. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: sun4i-usb: enable PHY0 dual route switching for A64 USB PHYIcenowy Zheng2017-04-101-0/+1
| | | | | | | | | | | Allwinner A64 SoC features a switchable PHY0 like the one in H3, which can switch between a MUSB controller and a pair of OHCI/EHCI controller. Enable PHY0 route auto switching for A64. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: rcar-gen3-usb2: fix implementation for runtime PMYoshihiro Shimoda2017-04-101-7/+24
| | | | | | | | | | | | This patch fixes an issue that this driver doesn't take care of the runtime PM. This code assumed that devm_phy_create() called pm_runtime_enable(dev), but it misunderstood the dev_phy_create()'s specification. This driver should call its own pm_runtime_enable() before dev_phy_create(). Fixes: f3b5a8d9b50d ("phy: rcar-gen3-usb2: Add R-Car Gen3 USB2 PHY driver") Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: rockchip-inno-usb2: fix spelling mistake: "connecetd" -> "connected"Colin Ian King2017-04-101-6/+3
| | | | | | | | trivial fix to spelling mistake in dev_dbg message, also rejoin lines to clean up checkpatch warning Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: exynos: Use one define for enable bitKrzysztof Kozlowski2017-04-103-26/+23
| | | | | | | | | | | | | There is no need for separate defines for Exynos4 and Exynos5 phy enable bit and MIPI phy reset bits. In both cases there are the same so simplify it. This reduces number of defines and allows removal of one header file. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Lee Jones <lee.jones@linaro.org> Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: exynos-mipi-video: Use consistent method to address phy registersKrzysztof Kozlowski2017-04-101-10/+10
| | | | | | | | | Exynos4 MIPI phy registers are defined with macro calculating the offset for given phyN. Use the same method for Exynos5420 to be consistent. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: exynos5: Remove duplicated defines of PHY register definesKrzysztof Kozlowski2017-04-102-0/+2
| | | | | | | | | | | | | | Phy drivers access PMU region through regmap provided by exynos-pmu driver. However there is no need to duplicate defines for PMU registers. Instead just use whatever is defined in exynos-regs-pmu.h. This reduces number of defines. Suggested-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Lee Jones <lee.jones@linaro.org> Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: exynos4: Remove duplicated defines of PHY register definesKrzysztof Kozlowski2017-04-101-6/+6
| | | | | | | | | | | | | | | | | Phy drivers access PMU region through regmap provided by exynos-pmu driver. However there is no need to duplicate defines for PMU registers. Instead just use whatever is defined in exynos-regs-pmu.h. Additionally MIPI PHY registers for Exynos5433 start from the same address as Exynos4 and Exynos5250 so re-use existing defines. This reduces number of defines and allows removal of one header file. Suggested-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Lee Jones <lee.jones@linaro.org> Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: meson8b-usb2: fix offsets for some of the registersMartin Blumenstingl2017-04-101-3/+3
| | | | | | | | | | The register offsets for REG_DBG_UART (and all following) were off by 0x4. This was not a problem yet because these registers are currently not used by the driver. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: sun4i-usb: support automatically switch PHY0 route to MUSB/HCIIcenowy Zheng2017-04-101-17/+33
| | | | | | | | | | | | | | | | | | | On newer Allwinner SoCs (H3 and after), the PHY0 node is routed to both MUSB controller for peripheral and host support (the host support is slightly broken), and a pair of EHCI/OHCI controllers, which provide a better support for host mode. Add support for automatically switch the route of PHY0 according to the status of dr_mode and id det pin. Only H3 have this function enabled in this patch, as further SoCs will be tested later and then have it enabled. As H5 is reusing the PHY driver of H3, this function is also enabled. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: sun4i-usb: add PHYCTL offset for H3 SoCIcenowy Zheng2017-04-101-0/+1
| | | | | | | | | | | The config structure of H3 in phy-sun4i-usb driver have the PHYCTL register offset missing. Add it. From the BSP source code, we know that the offset should be 0x10. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: sun4i-usb: change PHYCTL register clearing codeIcenowy Zheng2017-04-101-4/+2
| | | | | | | | | | | It seems that all SoCs with the PHYCTL register offset as 0x10 need the PHYCTL register to be cleared before it's written. Change PHYCTL register clearing code to judge whether clearing is needed based on the PHYCTL offset. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: phy-exynos-pcie: make it explicitly non-modularPaul Gortmaker2017-04-101-6/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Kconfig currently controlling compilation of this code is: drivers/phy/Kconfig:config PHY_EXYNOS_PCIE drivers/phy/Kconfig: bool "Exynos PCIe PHY driver" ...meaning that it currently is not being built as a module by anyone. Lets remove the couple traces of modular infrastructure use, so that when reading the driver there is no doubt it is builtin-only. Since module_platform_driver() uses the same init level priority as builtin_platform_driver() the init ordering remains unchanged with this commit. Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code. We also delete the MODULE_LICENSE tag etc. since all that information is already contained at the top of the file in the comments. Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Jingoo Han <jingoohan1@gmail.com> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: Kukjin Kim <kgene@kernel.org> Cc: Krzysztof Kozlowski <krzk@kernel.org> Cc: Pankaj Dubey <pankaj.dubey@samsung.com> Cc: Vivek Gautam <vivek.gautam@codeaurora.org> Cc: Javier Martinez Canillas <javier@osg.samsung.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: qcom-usb-hs: Add depends on EXTCONStephen Boyd2017-03-091-0/+1
| | | | | | | | | | | | | | | | | | | | We get the following compile errors if EXTCON is enabled as a module but this driver is builtin: drivers/built-in.o: In function `qcom_usb_hs_phy_power_off': phy-qcom-usb-hs.c:(.text+0x1089): undefined reference to `extcon_unregister_notifier' drivers/built-in.o: In function `qcom_usb_hs_phy_probe': phy-qcom-usb-hs.c:(.text+0x11b5): undefined reference to `extcon_get_edev_by_phandle' drivers/built-in.o: In function `qcom_usb_hs_phy_power_on': phy-qcom-usb-hs.c:(.text+0x128e): undefined reference to `extcon_get_state' phy-qcom-usb-hs.c:(.text+0x12a9): undefined reference to `extcon_register_notifier' so let's mark this as needing to follow the modular status of the extcon framework. Fixes: 9994a33865f4 e2427b09ba929c2b9 (phy: Add support for Qualcomm's USB HS phy") Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: phy-exynos-pcie: fix the wrong error returnJaehoon Chung2017-03-091-2/+2
| | | | | | | | | | | When it doesn't get the blk_base's resource, it was returned the error about phy_base, not blk_base. This patch is for fixing the wrong error return about blk_base. Fixes: cf0adb8e281b ("phy: phy-exynos-pcie: Add support for Exynos PCIe PHY") Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* Revert "phy: Add USB3 PHY support for Broadcom NSP SoC"Rafał Miłecki2017-03-093-186/+0
| | | | | | | | | | | | | | | | This reverts commit d7bc1a7d41bf ("phy: Add USB3 PHY support for Broadcom NSP SoC") as we already have driver for this PHY (shared by NS and NSP). It was added in commit e5666281d9ea ("phy: bcm-ns-usb3: new driver for USB 3.0 PHY on Northstar"). Instead of adding separated driver & duplicating code we should work on improving existing (old) one. Thanks to work done by Broadcom we know there is MDIO bus we weren't aware of & we know register names which makes initialization more clear. This is very valuable info and we should work on using it in existing driver afterwards. Acked-by: Jon Mason <jon.mason@broadcom.com> Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
* Merge tag 'pci-v4.11-changes' of ↵Linus Torvalds2017-02-233-0/+294
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI updates from Bjorn Helgaas: - add ASPM L1 substate support - enable PCIe Extended Tags when supported - configure PCIe MPS settings on iProc, Versatile, X-Gene, and Xilinx - increase VPD access timeout - add ACS quirks for Intel Union Point, Qualcomm QDF2400 and QDF2432 - use new pci_irq_alloc_vectors() in more drivers - fix MSI affinity memory leak - remove unused MSI interfaces and update documentation - remove unused AER .link_reset() callback - avoid pci_lock / p->pi_lock deadlock seen with perf - serialize sysfs enable/disable num_vfs operations - move DesignWare IP from drivers/pci/host/ to drivers/pci/dwc/ and refactor so we can support both hosts and endpoints - add DT ECAM-like support for HiSilicon Hip06/Hip07 controllers - add Rockchip system power management support - add Thunder-X cn81xx and cn83xx support - add Exynos 5440 PCIe PHY support * tag 'pci-v4.11-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (93 commits) PCI: dwc: Remove dependency of designware on CONFIG_PCI PCI: dwc: Add CONFIG_PCIE_DW_HOST to enable PCI dwc host PCI: dwc: Split pcie-designware.c into host and core files PCI: dwc: designware: Fix style errors in pcie-designware.c PCI: dwc: designware: Parse "num-lanes" property in dw_pcie_setup_rc() PCI: dwc: all: Split struct pcie_port into host-only and core structures PCI: dwc: designware: Get device pointer at the start of dw_pcie_host_init() PCI: dwc: all: Rename cfg_read/cfg_write to read/write PCI: dwc: all: Use platform_set_drvdata() to save private data PCI: dwc: designware: Move register defines to designware header file PCI: dwc: Use PTR_ERR_OR_ZERO to simplify code PCI: dra7xx: Group PHY API invocations PCI: dra7xx: Enable MSI and legacy interrupts simultaneously PCI: dra7xx: Add support to force RC to work in GEN1 mode PCI: dra7xx: Simplify probe code with devm_gpiod_get_optional() PCI: Move DesignWare IP support to new drivers/pci/dwc/ directory PCI: exynos: Support the PHY generic framework Documentation: binding: Modify the exynos5440 PCIe binding phy: phy-exynos-pcie: Add support for Exynos PCIe PHY Documentation: samsung-phy: Add exynos-pcie-phy binding ...
| * phy: phy-exynos-pcie: Add support for Exynos PCIe PHYJaehoon Chung2017-02-213-0/+294
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Generic PHY framework about Exynos SoCs. Current Exynos PCIe driver doesn't use the PHY framework, which makes it difficult to upstream the other Exynos variants because of different PHY registers. Move the codes relevant to PHY from Exnyos PCIe driver to PHY Exynos PCIe driver. [bhelgaas: depend on "OF && (ARCH_EXYNOS || COMPILE_TEST)", update copyright year, both per Vivek] Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Jingoo Han <jingoohan1@gmail.com> Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com> Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | phy: qcom-ufs: Fix misplaced jump labelVivek Gautam2017-01-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | We want to skip only tx/rx_iface clocks and not ref_clk_src as well. Fix the jump label accordingly. Fixes: 300f96771d78 ("phy: qcom-ufs: Skip obtaining rx/tx_iface_clk for msm8996 based phy") Cc: Subhash Jadavani <subhashj@codeaurora.org> Cc: Martin K. Petersen <martin.petersen@oracle.com> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: stable@vger.kernel.org Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* | phy: fix rockchip-inno-usb2 build errorsRandy Dunlap2017-01-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix build errors in phy-rockchip-inno-usb2.c. The driver uses extcon interfaces so it should depend on EXTCON. Fixes these build errors: drivers/built-in.o: In function `rockchip_usb2phy_otg_sm_work': phy-rockchip-inno-usb2.c:(.text+0x2bcb): undefined reference to `extcon_get_state' phy-rockchip-inno-usb2.c:(.text+0x2cd4): undefined reference to `extcon_set_state_sync' phy-rockchip-inno-usb2.c:(.text+0x2cec): undefined reference to `extcon_set_state_sync' phy-rockchip-inno-usb2.c:(.text+0x2d2d): undefined reference to `extcon_get_state' drivers/built-in.o: In function `rockchip_usb2phy_probe': phy-rockchip-inno-usb2.c:(.text+0x31d7): undefined reference to `extcon_get_edev_by_phandle' phy-rockchip-inno-usb2.c:(.text+0x321a): undefined reference to `devm_extcon_dev_allocate' phy-rockchip-inno-usb2.c:(.text+0x3230): undefined reference to `devm_extcon_dev_register' phy-rockchip-inno-usb2.c:(.text+0x375a): undefined reference to `extcon_register_notifier' Found in linux-next but is also needed in mainline. Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Cc: MyungJoo Ham <myungjoo.ham@samsung.com> Cc: Chanwoo Choi <cw00.choi@samsung.com> Cc: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* | phy: Add USB3 PHY support for Broadcom NSP SoCYendapally Reddy Dhananjaya Reddy2017-01-273-0/+186
| | | | | | | | | | | | | | | | This patch adds support for Broadcom NSP USB3 PHY Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* | phy: qcom-ufs: Suppress extraneous loggingBjorn Andersson2017-01-272-22/+5
| | | | | | | | | | | | | | | | | | | | | | | | The error paths of the common qcom-ufs functions for registering the phy, acquiring clocks and acquiring regulators all print specific error messages before returning an error, so there is no value in printing yet another - more generic - message when this occur. Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Reviewed-by: Subhash Jadavani <subhashj@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* | phy: qcom-ufs: Remove -always-on propertyBjorn Andersson2017-01-272-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The fact that a regulator is always-on is a property of the regulator, not a specific consumer. Implementing this in the driver leads to a system behaviour that is dependent on if the Qualcomm UFS PHY was ever (partially) probed. If the specific regulator should be always on in a particular device, mark it so by specifying "regulator-always-on" in the regulator node. Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Reviewed-by: Subhash Jadavani <subhashj@codeaurora.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* | phy: qcom-ufs: Correct usage of regulator_get()Bjorn Andersson2017-01-271-14/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When regulator_get() tries to resolve a regulator supply but fail to find a matching property in DeviceTree it returns a dummy regulator, if a matching supply is specified but unavailable the regulator core will return an error. Based on this we should not ignore errors upon failing to acquire the optional "vddp-ref-clk" supply. Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Reviewed-by: Subhash Jadavani <subhashj@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* | phy: qcom-ufs: Don't kfree devres resourceBjorn Andersson2017-01-271-8/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Upon failing to acquire regulator supplies the qcom-ufs driver calls kfree() on the devm allocated memory used to store the name of the regulator, leading to devres corruption. Rather than switching to using the appropriate free function the patch acknowledge the fact that "name" is always a constant string and we don't actually need to create a local copy of it, but rather just reference the constant string. Fixes: add78fc05702 ("phy: qcom-ufs: Use devm sibling of kstrdup for regulator names") Cc: stable@vger.kernel.org Reviewed-by: Subhash Jadavani <subhashj@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* | phy: Add support for Qualcomm's USB HS phyStephen Boyd2017-01-273-0/+305
| | | | | | | | | | | | | | | | | | | | | | The high-speed phy on qcom SoCs is controlled via the ULPI viewport. Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: <devicetree@vger.kernel.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* | phy: Add support for Qualcomm's USB HSIC phyStephen Boyd2017-01-273-0/+168
| | | | | | | | | | | | | | | | | | | | | | The HSIC USB controller on qcom SoCs has an integrated all digital phy controlled via the ULPI viewport. Cc: Kishon Vijay Abraham I <kishon@ti.com> Acked-by: Rob Herring <robh@kernel.org> Cc: <devicetree@vger.kernel.org> Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* | drivers: phy: constify phy_ops structuresBhumika Goyal2017-01-164-4/+4
| | | | | | | | | | | | | | | | | | | | | | Declare phy_ops structures as const as they are only passed as an argument to the function devm_phy_create. This argument is of type const struct phy_ops *, so phy_ops structures having this property can be declared as const. Done using Coccinelle: Signed-off-by: Bhumika Goyal <bhumirks@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* | phy: sun4i-usb: Replace the deprecated extcon APIChanwoo Choi2017-01-161-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | This patch replaces the deprecated extcon API as following: - extcon_set_cable_state_() -> extcon_set_state_sync() Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Chen-Yu Tsai <wens@csie.org> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* | phy: rcar-gen3-usb2: Replace the deprecated extcon APIChanwoo Choi2017-01-161-4/+4
| | | | | | | | | | | | | | | | | | This patch replaces the deprecated extcon API as following: - extcon_set_cable_state_() -> extcon_set_state_sync() Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* | phy: sun4i-usb: add support for V3s USB PHYIcenowy Zheng2017-01-161-1/+13
| | | | | | | | | | | | | | | | | | | | | | Allwinner V3s come with a USB PHY controller slightly different to other SoCs, with only one PHY. Add support for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* | phy: rockchip-inno-usb2: Set EXTCON_USB when EXTCON_CHG_USB_SDP was setBaolin Wang2017-01-161-1/+6
|/ | | | | | | | | According to the documentation, we should set the EXTCON_USB when one SDP charger connector was reported. Signed-off-by: Baolin Wang <baolin.wang@linaro.org> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* Merge tag 'scsi-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsiLinus Torvalds2016-12-144-243/+174
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull SCSI updates from James Bottomley: "This update includes the usual round of major driver updates (ncr5380, lpfc, hisi_sas, megaraid_sas, ufs, ibmvscsis, mpt3sas). There's also an assortment of minor fixes, mostly in error legs or other not very user visible stuff. The major change is the pci_alloc_irq_vectors replacement for the old pci_msix_.. calls; this effectively makes IRQ mapping generic for the drivers and allows blk_mq to use the information" * tag 'scsi-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi: (256 commits) scsi: qla4xxx: switch to pci_alloc_irq_vectors scsi: hisi_sas: support deferred probe for v2 hw scsi: megaraid_sas: switch to pci_alloc_irq_vectors scsi: scsi_devinfo: remove synchronous ALUA for NETAPP devices scsi: be2iscsi: set errno on error path scsi: be2iscsi: set errno on error path scsi: hpsa: fallback to use legacy REPORT PHYS command scsi: scsi_dh_alua: Fix RCU annotations scsi: hpsa: use %phN for short hex dumps scsi: hisi_sas: fix free'ing in probe and remove scsi: isci: switch to pci_alloc_irq_vectors scsi: ipr: Fix runaway IRQs when falling back from MSI to LSI scsi: dpt_i2o: double free on error path scsi: cxlflash: Migrate scsi command pointer to AFU command scsi: cxlflash: Migrate IOARRIN specific routines to function pointers scsi: cxlflash: Cleanup queuecommand() scsi: cxlflash: Cleanup send_tmf() scsi: cxlflash: Remove AFU command lock scsi: cxlflash: Wait for active AFU commands to timeout upon tear down scsi: cxlflash: Remove private command pool ...
| * phy: qcom-ufs: Remove common layer phy exit callbackVivek Gautam2016-11-084-14/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | The common layer phy exit callback ufs_qcom_phy_exit() calls phy_power_off() that has no meaning when phy_power_off() callback is already registered with the phy provider and the consumer makes use of the same. Instead, add a no-op specific phy_exit() callback for now to add the exit sequence at a later point. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Reviewed-by: Subhash Jadavani <subhashj@codeaurora.org> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
| * scsi: ufs-qcom: phy/hcd: Refactoring phy clock handlingVivek Gautam2016-11-081-18/+18
| | | | | | | | | | | | | | | | | | | | Add phy clock enable code to phy_power_on/off callbacks, and remove explicit calls to enable these phy clocks from the ufs-qcom hcd driver. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Reviewed-by: Subhash Jadavani <subhashj@codeaurora.org> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
| * phy: qcom-ufs-qmp-xx: Move clock and regulator init out of phy initVivek Gautam2016-11-082-52/+46
| | | | | | | | | | | | | | | | | | | | | | The phy init is meant to do phy initialization rather than just getting the clock and regulator. Move these clock and regulator get to probe(), to make room for actual phy initialization sequence. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Reviewed-by: Subhash Jadavani <subhashj@codeaurora.org> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
| * phy: qcom-ufs: Remove unnecessary function declarationsVivek Gautam2016-11-081-69/+62
| | | | | | | | | | | | | | | | | | Move the functions' definitions to remove unnecessary declarations. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Reviewed-by: Subhash Jadavani <subhashj@codeaurora.org> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
| * phy: qcom-ufs-qmp-xx: Discard remove callback for drivers.Vivek Gautam2016-11-083-41/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | remove() callback does a phy_power_off() only over the phy, and nothing else now. The phy_power_off() over the generic phy is called from the phy consumer, and phy provider driver should not explicitly need to call any phy ops. So discard the remove callback for qcom-ufs phy platform drivers. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Reviewed-by: Subhash Jadavani <subhashj@codeaurora.org> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
| * phy: qcom-ufs: Skip obtaining rx/tx_iface_clk for msm8996 based phyVivek Gautam2016-11-081-0/+5
| | | | | | | | | | | | | | | | | | | | The tx_iface_clk and rx_iface_clk no longer exist with UFS Phy present on msm8996. So skip obtaining these clocks using compatible match. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Reviewed-by: Subhash Jadavani <subhashj@codeaurora.org> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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