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* phy: add inno-usb2-phy driver for hi3798cv200 SoCPengcheng Li2018-03-163-0/+208
| | | | | | | | | | | | | | | It adds inno-usb2-phy driver for hi3798cv200 SoC USB 2.0 support. One inno-usb2-phy device can support up to two PHY ports. While there is device level reference clock and power reset to be controlled, each PHY port has its own utmi reset that needs to assert/de-assert as needed. Hi3798cv200 needs to access PHY port0 register via particular peripheral syscon controller register to control PHY, like turning on PHY clock. Signed-off-by: Pengcheng Li <lpc.li@hisilicon.com> Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: rcar-gen3-usb2: Add support for r8a77965Yoshihiro Shimoda2018-03-161-0/+4
| | | | | | | | | This patch adds support for r8a77965 (R-Car M3-N). This SoC has dedicated pins. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: stm32: add support for STM32 USB PHY Controller (USBPHYC)Amelie Delaunay2018-03-163-0/+476
| | | | | | | | | | | | | This patch adds phy transceiver driver for STM32 USB PHY Controller (USBPHYC) that provides dual port High-Speed phy for OTG (single port) and EHCI/OHCI host controller (two ports). One port of the phy is shared between the two USB controllers through a UTMI+ switch. [fengguang.wu@intel.com: Make stm32_usbphyc_get_pll_params() to be static] Signed-off-by: Fengguang Wu <fengguang.wu@intel.com> Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: add 'depends on HAS_IOMEM' to fix unmet dependencyMasahiro Yamada2018-03-163-0/+3
| | | | | | | | | | | | These configs select MFD_SYSCON, but do not depend on HAS_IOMEM. Compile testing on architecture without HAS_IOMEM causes "unmet direct dependencies" in Kconfig phase. Detected by "make ARCH=score allyesconfig". Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: amlogic: add USB3 PHY support for Meson GXL and GXMMartin Blumenstingl2018-03-163-0/+295
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a new driver for the USB3 PHY found on Meson GXL and GXM SoCs (both SoCs are using the same USB PHY register layout). Unfortunately there is no documentation for this PHY in the public S905X datasheet (published for example by Khadas). What we know so far about this PHY: - even though the Meson GXL and GXM SoCs do not expose an USB3 port (the dwc3 controller only has USB2 ports enabled) we need to initialize the USB3 PHY (specifically USB_R1_U3H_FLADJ_30MHZ_REG_MASK). Without this initialization high-speed USB devices (especially USB hard disks and thumb drives, slower devices like mice do not seem to be affected) - on some boards the USB3 PHY starts in "device mode" - we want to bring it into a known state (by switching it to host mode for now). - it is responsible for the OTG detection and for switching the first USB2 PHY between host and peripheral (aka device) mode. an interrupt can be used to detect changes between host and device mode. There are five inputs to this register area: - the clock and reset line for the USB3 PHY itself - the clock and reset line for the peripheral mode and OTG detection logic (on the GXL and GXM SoCs these are the same clock and reset line as for the USB3 PHY itself, but Amlogic sees this as two different components - even though they share the same register space - so they have to be passed individually to allow specifying different inputs on other SoCs if needed) - the interrupt for the OTG detection logic The whole OTG detection logic is not implemented yet. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Yixun Lan <yixun.lan@amlogic.com> Tested-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: berlin-usb: adjust USB_PHY_RX_CTRL init flagsAlexander Monakov2018-03-161-1/+1
| | | | | | | | | | | | | | Make the value written into the USB_PHY_RX_CTRL configuration register match 0xAA79 value written by manufacturer-supplied kernels for Sony NSZ-GS7 (Berlin2 SoC), Google Chromecast and Valve Steam Link (BG2CD). This fixes timeouts communicating to the internal hub on Steam Link. Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: Antoine Tenart <antoine.tenart@bootlin.com> Signed-off-by: Alexander Monakov <amonakov@ispras.ru> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: phy-mtk-tphy: add configurable parameters for slew rate calibrateChunfeng Yun2018-03-161-5/+15
| | | | | | | | | | There are two parameters, ref_clk and coefficient, for U2 slew rate calibrate which may vary on different SoCs, here allow them to be configurable Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: phy-mtk-tphy: keep default value of mcu_bus_ck_gate_enChunfeng Yun2018-03-161-2/+1
| | | | | | | | | The default value of mcu_bus_ck_gate_en is 1, if clear it, will prevent system to enter deep idle mode, so keep its default value and without affecting PCIe function. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: lpc18xx-usb-otg: error handling in lpc18xx_usb_otg_phy_power_on()Alexey Khoroshilov2018-03-161-1/+7
| | | | | | | | | | If regmap_update_bits() fails in lpc18xx_usb_otg_phy_power_on(), lpc->clk is left enabled. Found by Linux Driver Verification project (linuxtesting.org). Signed-off-by: Alexey Khoroshilov <khoroshilov@ispras.ru> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: allwinner: sun4i-usb: poll vbus changes on A23/A33 when driving VBUSChen-Yu Tsai2018-03-121-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The AXP223 PMIC, like the AXP221, does not generate VBUS change interrupts when N_VBUSEN is used to drive VBUS for the OTG port on the board. This was not noticed until recently, as most A23/A33 boards use a GPIO pin that does not support interrupts for OTG ID detection. This forces the driver to use polling. However the A33-OlinuXino uses a pin that does support interrupts, so the driver uses them. However the VBUS interrupt never fires, and the driver never gets to update the VBUS status. This results in musb timing out waiting for VBUS to rise. This was worked around for the AXP221 by resorting to polling changes in commit 91d96f06a760 ("phy-sun4i-usb: Add workaround for missing Vbus det interrupts on A31"). This patch adds the A23 and A33 to the list of SoCs that need the workaround. Fixes: fc1f45ed3043 ("phy-sun4i-usb: Add support for the usb-phys on the sun8i-a33 SoC") Fixes: 123dfdbcfaf5 ("phy-sun4i-usb: Add support for the usb-phys on the sun8i-a23 SoC") Cc: <stable@vger.kernel.org> # 4.3.x: 68dbc2ce77bb phy-sun4i-usb: Use of_match_node to get model specific config data Cc: <stable@vger.kernel.org> # 4.3.x: 5cf700ac9d50 phy: phy-sun4i-usb: Fix optional gpios failing probe Cc: <stable@vger.kernel.org> # 4.3.x: 04e59a0211ff phy-sun4i-usb: Fix irq free conditions to match request conditions Cc: <stable@vger.kernel.org> # 4.3.x: 91d96f06a760 phy-sun4i-usb: Add workaround for missing Vbus det interrupts on A31 Cc: <stable@vger.kernel.org> # 4.3.x Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: amlogic: phy-meson-gxl-usb2: rename some of the U2P_R2 registersMartin Blumenstingl2018-03-081-6/+5
| | | | | | | | | | | | | | | | | | | | The U2P_R2 register provides "test mode" functionality for bits 17:0. These are only used during SoC development and should be left untouched on production SoC versions. Rename these register definitions to indicate that these are for "test mode" only. While here, also merge the definitions for U2P_R2_DATA_IN_MASK and U2P_R2_DATA_IN_EN_MASK (bits 0:7) because Amlogic's internal documentation suggests that these bits belong together. The old definition was not taken from the documentation but rather from a struct definition in the Amlogic GPL kernel sources. No functional changes. Suggested-by: Yixun Lan <yixun.lan@amlogic.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: amlogic: phy-meson-gxl-usb2: default to host modeMartin Blumenstingl2018-03-082-14/+2
| | | | | | | | | | | | The USB2 PHY can switch between PHY_MODE_USB_HOST and PHY_MODE_USB_DEVICE. However, it cannot do it on it's own since it requires re-routing of the corresponding USB pins from dwc3 (which is used for host-mode) to dwc2 (which is used for device-mode). Thus we don't need to auto-detect the mode based on the USB controller, which simplifies the driver code. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: amlogic: phy-meson-gxl-usb2: support the clock and reset lineMartin Blumenstingl2018-03-081-0/+44
| | | | | | | | | | | | | | | | | | The Meson GXL USB2 PHYs require an additional clock (USB) which has to be enabled. If that clock is disabled then all PHY registers read 0x0. Luckily for us that clock is always enabled (either by harddware defaults, the bootrom, or any of the bootloaders before u-boot/BL3-3). The OTG capable USB2 PHY additionally has a reset line (USB_OTG, which is shared with other components, such as the USB3 PHY for example). Extend the driver so it handles this clock and the shared reset line. We only trigger the reset during the .init phase since it's a shared reset line, so triggering it during the driver's .reset implementation would effectively also only trigger it once anyways. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: amlogic: phy-meson-gxl-usb2: don't log an error on -EPROBE_DEFERMartin Blumenstingl2018-03-081-2/+6
| | | | | | | | | | | devm_phy_create can return -EPROBE_DEFER if the phy-supply is not ready yet. Silence this warning as the driver framework will re-attempt registering the PHY - this second try works without any errors. So only log actual errors to keep the kernel log free of misleading error messages. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: rockchip-emmc: use regmap_read_poll_timeout to poll dllrdyShawn Lin2018-03-081-22/+11
| | | | | | | | | | | Just use the API instead of open-coding it, no functional change intended. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: rockchip-emmc: retry calpad busy trimmingShawn Lin2018-03-081-10/+17
| | | | | | | | | | | It turns out that 5us isn't enough for all cases, so let's retry some more times to wait for caldone. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Tested-by: Ziyuan Xu <xzy.xu@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: Remove SOC_EXYNOS4212 dep. from PHY_EXYNOS4X12_USBUlf Magnusson2018-03-081-1/+1
| | | | | | | | | | | | | | | Exynos4212 support was removed by commit bca9085e0ae9 ("ARM: dts: exynos: remove Exynos4212 support (dead code)"). Remove the SOC_EXYNOS4212 dependency from PHY_EXYNOS4X12_USB. Discovered with the https://github.com/ulfalizer/Kconfiglib/blob/master/examples/list_undefined.py script. Signed-off-by: Ulf Magnusson <ulfalizer@gmail.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: add SPDX identifier to QMP and QUSB2 PHY driversManu Gautam2018-03-082-19/+2
| | | | | | | | The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: qcom-qmp: Add support for runtime PMManu Gautam2018-03-082-1/+179
| | | | | | | | | | Disable clocks and enable PHY autonomous mode to detect wakeup events when PHY is suspended. Core driver should notify speed to PHY driver to enable LFPS and/or RX_DET interrupts. Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: qcom-qusb2: Add support for runtime PMManu Gautam2018-03-081-0/+176
| | | | | | | | | | Disable clocks and enable DP/DM wakeup interrupts when suspending PHY. Core driver should notify speed to PHY driver to enable appropriate DP/DM wakeup interrupts polarity in suspend state. Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: Add USB speed related PHY modesManu Gautam2018-03-081-0/+2
| | | | | | | | | | | | | | | | Add following USB speed related PHY modes: LS (Low Speed), FS (Full Speed), HS (High Speed), SS (Super Speed) Speed related information is required by some QCOM PHY drivers to program PHY monitor resume/remote-wakeup events in suspended state. Speed is needed in order to set correct polarity of wakeup events for detection. E.g. QUSB2 PHY monitors DP/DM line state depending on whether speed is LS or FS/HS to detect resume. Similarly QMP USB3 PHY in SS mode should monitor RX terminations attach/detach and LFPS events depending on SSPHY is active or not. Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: qcom-qmp: Add support for QMP V3 USB3 PHYManu Gautam2018-03-081-3/+220
| | | | | | | | | | | QMP V3 USB3 PHY is a DisplayPort (DP) and USB combo PHY with dual RX/TX lanes to support type-c. There is a separate block DP_COM for configuration related to type-c or DP. Add support for dp_com region and secondary rx/tx lanes initialization. Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: qcom-qmp: Add register offsets for QMP V3 PHYManu Gautam2018-03-081-0/+149
| | | | | | | | Registers offsets for QMP V3 PHY are changed from previous versions (1/2), update same in header file. Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: qcom-qmp: Move register offsets to header fileManu Gautam2018-03-082-118/+129
| | | | | | | | | | | New revision (v3) of QMP PHY uses different offsets for almost all of the registers. Hence, move these definitions to header file so that updated offsets can be added for QMP v3. Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: qcom-qusb2: Add support for QUSB2 V2 versionManu Gautam2018-03-081-0/+64
| | | | | | | | | | | | Use register layout to add additional registers present on QUSB2 PHY V2 version for PHY initialization. Other than new registers on V2, following two register's offset and bit definitions are different: POWERDOWN control and PLL_STATUS. Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: qcom-qusb2: Add support for different register layoutsManu Gautam2018-03-081-40/+109
| | | | | | | | | | New version of QUSB2 PHY has some registers offset changed. Add support to have register layout for a target and update the same in phy_configuration. Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: qcom-qmp: Move SERDES/PCS START after PHY resetManu Gautam2018-03-081-3/+3
| | | | | | | | | Driver is currently performing PHY reset after starting SERDES/PCS. As per hardware datasheet reset must be done before starting PHY. Hence, update the sequence. Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: qcom-qmp: Fix PHY block reset sequenceManu Gautam2018-03-081-9/+19
| | | | | | | | | | | | | | PHY block or asynchronous reset requires signal to be asserted before de-asserting. Driver is only de-asserting signal which is already low, hence reset operation is a no-op. Fix this by asserting signal first. Also, resetting requires PHY clocks to be turned ON only after reset is finished. Fix that as well. Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: qcom-qusb2: Power-on PHY before initializationManu Gautam2018-03-081-32/+15
| | | | | | | | | | | | | | | PHY must be powered on before turning ON clocks and attempting to initialize it. Driver is exposing separate init and power_on routines for this. Apparently USB dwc3 core driver performs power-on after init. Also, poweron and init for QUSB2 PHY need to be executed together always, hence remove poweron callback from phy_ops and explicitly perform this from init, similar changes needed for poweroff. Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: qcom-qmp: Power-on PHY before initializationManu Gautam2018-03-081-37/+24
| | | | | | | | | | | | | | | PHY regulators which are enabled from power_on() must be ON before turning-on clocks and initializing it as part of init(). As most of the core drivers perform power_on() after init(), move PHY regulators enable to com_init() and use power_on() to only enable pipe_clk. This pipe_clk is output from PHY and some core drivers e.g. PCIe follow specific sequence after phy_init() that mandates pipe_clk to be enabled from power_on() only. On similar lines move clk_enable from init() to com_init() which executes once for multi lane PHYs. Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: qcom-qmp: Adapt to clk_bulk_* APIsVivek Gautam2018-03-081-34/+16
| | | | | | | | | Move from using array of clocks to clk_bulk_* APIs that are available now. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: qcom-qmp: Fix phy pipe clock gatingVivek Gautam2018-03-081-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pipe clock comes out of the phy and is available as long as the phy is turned on. Clock controller fails to gate this clock after the phy is turned off and generates a warning. / # [ 33.048561] gcc_usb3_phy_pipe_clk status stuck at 'on' [ 33.048585] ------------[ cut here ]------------ [ 33.052621] WARNING: CPU: 1 PID: 18 at ../drivers/clk/qcom/clk-branch.c:97 clk_branch_wait+0xf0/0x108 [ 33.057384] Modules linked in: [ 33.066497] CPU: 1 PID: 18 Comm: kworker/1:0 Tainted: G W 4.12.0-rc7-00024-gfe926e34c36d-dirty #96 [ 33.069451] Hardware name: Qualcomm Technologies, Inc. DB820c (DT) ... [ 33.278565] [<ffff00000849b27c>] clk_branch_wait+0xf0/0x108 [ 33.286375] [<ffff00000849b2f4>] clk_branch2_disable+0x28/0x34 [ 33.291761] [<ffff0000084868dc>] clk_core_disable+0x5c/0x88 [ 33.297660] [<ffff000008487d68>] clk_core_disable_lock+0x20/0x34 [ 33.303129] [<ffff000008487d98>] clk_disable+0x1c/0x24 [ 33.309384] [<ffff0000083ccd78>] qcom_qmp_phy_poweroff+0x20/0x48 [ 33.314328] [<ffff0000083c53f4>] phy_power_off+0x80/0xdc [ 33.320492] [<ffff00000875c950>] dwc3_core_exit+0x94/0xa0 [ 33.325784] [<ffff00000875c9ac>] dwc3_suspend_common+0x50/0x60 [ 33.331080] [<ffff00000875ca04>] dwc3_runtime_suspend+0x48/0x6c [ 33.336810] [<ffff0000085b82f4>] pm_generic_runtime_suspend+0x28/0x38 [ 33.342627] [<ffff0000085bace0>] __rpm_callback+0x150/0x254 [ 33.349222] [<ffff0000085bae08>] rpm_callback+0x24/0x78 [ 33.354604] [<ffff0000085b9fd8>] rpm_suspend+0xe0/0x4e4 [ 33.359813] [<ffff0000085bb784>] pm_runtime_work+0xdc/0xf0 [ 33.365028] [<ffff0000080d7b30>] process_one_work+0x12c/0x28c [ 33.370576] [<ffff0000080d7ce8>] worker_thread+0x58/0x3b8 [ 33.376393] [<ffff0000080dd4a8>] kthread+0x100/0x12c [ 33.381776] [<ffff0000080836c0>] ret_from_fork+0x10/0x50 Fix this by disabling it as the first thing in phy_exit(). Fixes: e78f3d15e115 ("phy: qcom-qmp: new qmp phy driver for qcom-chipsets") Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: add combo phy driver for HiSilicon STB SoCsJianguo Sun2018-02-213-0/+299
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add combo phy driver for HiSilicon STB SoCs. This phy can be used as pcie-phy, sata-phy or usb-phy. Changes for v5: - Add bindings doc for Hi3798CV200 peripheral controller, and refer to the bindings of this parent node in combphy bindings doc. Changes for v4: - Instead of relying on device id, add a new property hisilicon,fixed-mode for combphy device that doesn't support mode select but a fixed phy mode. - Move combphy mode select register bits definition to device tree, as it may vary from one device to another. Changes for v3: - Make combphy device be child of peripheral controller and use 'reg' property for mapping combphy configuration registers. - Kill "hisilicon,peripheral-syscon" property, since parent node is just the syscon controller now. - Check combphy id to handle the quirk that combphy0 can not configure mode but always works in USB3 mode. - Unify phy .init and .exit hooks for different combphy instances and work modes, as the only quirk we need to handle is that combphy0 can only work in USB3 mode. - Better naming for clock and reset, 'ref' to 'ref_clk', 'por' to 'por_rst'. Changes for v2: - Move DT bindings into a separate patch. - Drop the spurious newline from drivers/phy/Makefile. - Use the phy type defines in dt-bindings/phy/phy.h. - Use PTR_ERR_OR_ZERO() for checking return from devm_of_phy_provider_register(). - Add USB3 phy support. Signed-off-by: Jianguo Sun <sunjianguo1@huawei.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: sun4i-usb: add support for R40 USB PHYIcenowy Zheng2018-02-211-0/+12
| | | | | | | | | | | | Allwinner R40 features a USB PHY like the one in A64, but with 3 PHYs. Add support for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> Tested-by: Hermann Lauer <Hermann.Lauer@iwr.uni-heidelberg.de> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: tegra: remove redundant self assignment of 'map'Colin Ian King2018-02-211-1/+1
| | | | | | | | The assignment of map to itself is redundant and can be removed. Detected with Coccinelle. Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* Merge tag 'usb-4.16-rc1' of ↵Linus Torvalds2018-02-014-34/+210
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb Pull USB/PHY updates from Greg KH: "Here is the big USB and PHY driver update for 4.16-rc1. Along with the normally expected XHCI, MUSB, and Gadget driver patches, there are some PHY driver fixes, license cleanups, sysfs attribute cleanups, usbip changes, and a raft of other smaller fixes and additions. Full details are in the shortlog. All of these have been in the linux-next tree for a long time with no reported issues" * tag 'usb-4.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (137 commits) USB: serial: pl2303: new device id for Chilitag USB: misc: fix up some remaining DEVICE_ATTR() usages USB: musb: fix up one odd DEVICE_ATTR() usage USB: atm: fix up some remaining DEVICE_ATTR() usage USB: move many drivers to use DEVICE_ATTR_WO USB: move many drivers to use DEVICE_ATTR_RO USB: move many drivers to use DEVICE_ATTR_RW USB: misc: chaoskey: Use true and false for boolean values USB: storage: remove old wording about how to submit a change USB: storage: remove invalid URL from drivers usb: ehci-omap: don't complain on -EPROBE_DEFER when no PHY found usbip: list: don't list devices attached to vhci_hcd usbip: prevent bind loops on devices attached to vhci_hcd USB: serial: remove redundant initializations of 'mos_parport' usb/gadget: Fix "high bandwidth" check in usb_gadget_ep_match_desc() usb: gadget: compress return logic into one line usbip: vhci_hcd: update 'status' file header and format USB: serial: simple: add Motorola Tetra driver CDC-ACM: apply quirk for card reader usb: option: Add support for FS040U modem ...
| * Merge tag 'phy-for-4.16' of ↵Greg Kroah-Hartman2018-01-084-34/+210
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into usb-next Kishon writes: phy: for 4.16 *) Fix in exynos5-usbdrd to enumerate SuperSpeed devices on Odroid XU3 *) Fix in Broadcom USB PHY to get Dell Low Speed keyboards working *) Fix in Broadcom USB PHY to power down the PHY when XHCI disabled to save power *) Fix in Broadcom USB PHY to prevent abort in DRD mode *) Fix in Broadcom USB PHY to use the correct dt properties *) Fix in Mediatek PHY to detect device connection *) Make getting resource optional for Mediatek V1 TPHY *) Cleanup in Mediatek PHY Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| | * phy: phy-mtk-tphy: use of_device_get_match_data()Chunfeng Yun2017-12-291-6/+5
| | | | | | | | | | | | | | | | | | | | | reduce the boilerplate code to get the specific data Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| | * phy: phy-mtk-tphy: make shared banks optional for V1 TPHYChunfeng Yun2017-12-291-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | V1 TPHY for SATA doesn't have shared banks if it isn't shared with PCIe or USB, so make it optional. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| | * phy: phy-mtk-tphy: use auto instead of force to bypass utmi signalsChunfeng Yun2017-12-291-12/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When system is running, if usb2 phy is forced to bypass utmi signals, all PLL will be turned off, and it can't detect device connection anymore, so replace force mode with auto mode which can bypass utmi signals automatically if no device attached for normal flow. But keep the force mode to fix RX sensitivity degradation issue. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| | * phy: phy-brcm-usb-init: DRD mode can cause crash on startupAl Cooper2017-12-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is caused by a bug in the BDC core. When the BDC core comes out of reset and it's not selected, it gets a backup clock. When the BDC core is selected, it get's the main clock. If HOST mode is then selected the BDC core has the main clock shut off but the backup clock is not restored. The failure scenario and cause are as follows: - DRD mode is active - Device mode is selected first in bootloader - When host mode is now selected, the clock to the BDC is cut off. - BDC registers are inaccessible and therefore the BDC driver crashes upon Linux boot. The fix is to have the phy driver always force a BDC reset on startup. Fixes: 49859e55e364 ("phy: usb: phy-brcm-usb: Add Broadcom STB USB phy driver") Signed-off-by: Al Cooper <alcooperx@gmail.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| | * phy: phy-brcm-usb-init: Power down USB 3.0 PHY when XHCI disabledAl Cooper2017-12-291-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set PHY3_IDDQ_OVERRIDE in the xhci uninit routine. This will save additional power when the XHCI driver is not enabled. Fixes: 49859e55e364 ("phy: usb: phy-brcm-usb: Add Broadcom STB USB phy driver") Signed-off-by: Al Cooper <alcooperx@gmail.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| | * phy: phy-brcm-usb-init: Some Low Speed keyboards fail on 7271Al Cooper2017-12-291-12/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the the Low Speed Keep Alive signal on the 7271b0 by setting the LS_KEEP_ALIVE bit in the USB CTRL OBRIDGE register otherwise some Dell Low Speed keyboards fail. Also do a little cleanup of the EBRIDGE ESTOP_SCB_REQ bit. Since this is only used on one platform, remove it from the platform tables and just use "if (family == "). Fixes: 49859e55e364 ("phy: usb: phy-brcm-usb: Add Broadcom STB USB phy driver") Signed-off-by: Al Cooper <alcooperx@gmail.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| | * phy: phy-brcm-usb: Fix two DT properties to match bindings docAl Cooper2017-12-291-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change "brcm,has_xhci" and "brcm,has_eohci" device tree properties to the preferred "brcm,has-xhci" and "brcm,has-eohci". This also matches the existing device tree bindings document. Fixes: 49859e55e364 ("phy: usb: phy-brcm-usb: Add Broadcom STB USB phy driver") Signed-off-by: Al Cooper <alcooperx@gmail.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| | * phy: exynos5-usbdrd: Calibrate LOS levels for exynos5420/5800Vivek Gautam2017-12-291-0/+183
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding phy calibration sequence for USB 3.0 DRD PHY present on Exynos5420/5800 systems. This calibration facilitates setting certain PHY parameters viz. the Loss-of-Signal (LOS) Detector Threshold Level, as well as Tx-Vboost-Level for Super-Speed operations. Additionally we also set proper time to wait for RxDetect measurement, for desired PHY reference clock, so as to solve issue with enumeration of few USB 3.0 devices, like Samsung SUM-TSB16S 3.0 USB drive on the controller. We are using CR_port for this purpose to send required data to override the LOS values. On testing with USB 3.0 devices on USB 3.0 port present on SMDK5420, and peach-pit boards should see following message: usb 2-1: new SuperSpeed USB device number 2 using xhci-hcd and without this patch, should see below shown message: usb 1-1: new high-speed USB device number 2 using xhci-hcd [Also removed unnecessary extra lines in the register macro definitions] Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> [adapted to use phy_calibrate as entry point] Signed-off-by: Andrzej Pietrasiewicz <andrzej.p@samsung.com> Acked-by: Felipe Balbi <felipe.balbi@linux.intel.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* | | Merge branch 'for-4.16' of ↵Linus Torvalds2018-01-301-0/+31
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata Pull libata updates from Tejun Heo: "Nothing too interesting. Several patches to convert mdelay() to usleep_range(), removal of unused pata_at32, and other low level driver specific changes" * 'for-4.16' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata: ata: pata_pdc2027x: Replace mdelay with msleep ata: pata_it821x: Replace mdelay with usleep_range in it821x_firmware_command ata: sata_mv: Replace mdelay with usleep_range in mv_reset_channel ata: remove pata_at32 phy: brcm-sata: remove unused variable phy: brcm-sata: fix semicolon.cocci warnings ata: ahci_brcm: Recover from failures to identify devices phy: brcm-sata: Implement calibrate callback ahci: Add Intel Cannon Lake PCH-H PCI ID ata_piix: constify pci_bits libata:pata_atiixp: Don't use unconnected secondary port on SB600 ata: ahci_brcm: Avoid clobbering SATA_TOP_CTRL_BUS_CTRL ahci: Allow setting a default LPM policy for mobile chipsets ahci: Add PCI ids for Intel Bay Trail, Cherry Trail and Apollo Lake AHCI ahci: Annotate PCI ids for mobile Intel chipsets as such
| * | | phy: brcm-sata: remove unused variableArnd Bergmann2018-01-181-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The newly introduced calibrate function has a variable that has never been used and needs to be removed to avoid this harmless warning: drivers/phy/broadcom/phy-brcm-sata.c: In function 'brcm_stb_sata_calibrate': drivers/phy/broadcom/phy-brcm-sata.c:514:24: error: unused variable 'priv' [-Werror=unused-variable] Fixes: 3e507769d15e ("phy: brcm-sata: Implement calibrate callback") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Tejun Heo <tj@kernel.org>
| * | | phy: brcm-sata: fix semicolon.cocci warningsFengguang Wu2018-01-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | drivers/phy/broadcom/phy-brcm-sata.c:534:2-3: Unneeded semicolon Remove unneeded semicolon. Generated by: scripts/coccinelle/misc/semicolon.cocci Fixes: 3e507769d15e ("phy: brcm-sata: Implement calibrate callback") CC: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Fengguang Wu <fengguang.wu@intel.com> Signed-off-by: Tejun Heo <tj@kernel.org>
| * | | phy: brcm-sata: Implement calibrate callbackFlorian Fainelli2018-01-171-0/+32
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | Implement the calibration callback to allow turning on the Clock-Data Recovery module clamping when necessary, e.g: during failure to identify a SATA hard drive from ahci_brcm.c::brcm_ahci_read_id. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Tejun Heo <tj@kernel.org>
* | | phy: work around 'phys' references to usb-nop-xceiv devicesArnd Bergmann2018-01-191-0/+4
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Stefan Wahren reports a problem with a warning fix that was merged for v4.15: we had lots of device nodes with a 'phys' property pointing to a device node that is not compliant with the binding documented in Documentation/devicetree/bindings/phy/phy-bindings.txt This generally works because USB HCD drivers that support both the generic phy subsystem and the older usb-phy subsystem ignore most errors from phy_get() and related calls and then use the usb-phy driver instead. However, it turns out that making the usb-nop-xceiv device compatible with the generic-phy binding changes the phy_get() return code from -EINVAL to -EPROBE_DEFER, and the dwc2 usb controller driver for bcm2835 now returns -EPROBE_DEFER from its probe function rather than ignoring the failure, breaking all USB support on raspberry-pi when CONFIG_GENERIC_PHY is enabled. The same code is used in the dwc3 driver and the usb_add_hcd() function, so a reasonable assumption would be that many other platforms are affected as well. I have reviewed all the related patches and concluded that "usb-nop-xceiv" is the only USB phy that is affected by the change, and since it is by far the most commonly referenced phy, all the other USB phy drivers appear to be used in ways that are are either safe in DT (they don't use the 'phys' property), or in the driver (they already ignore -EPROBE_DEFER from generic-phy when usb-phy is available). To work around the problem, this adds a special case to _of_phy_get() so we ignore any PHY node that is compatible with "usb-nop-xceiv", as we know that this can never load no matter how much we defer. In the future, we might implement a generic-phy driver for "usb-nop-xceiv" and then remove this workaround. Since we generally want older kernels to also want to work with the fixed devicetree files, it would be good to backport the patch into stable kernels as well (3.13+ are possibly affected), even though they don't contain any of the patches that may have caused regressions. Fixes: 014d6da6cb25 ARM: dts: bcm283x: Fix DTC warnings about missing phy-cells Fixes: c5bbf358b790 arm: dts: nspire: Add missing #phy-cells to usb-nop-xceiv Fixes: 44e5dced2ef6 arm: dts: marvell: Add missing #phy-cells to usb-nop-xceiv Fixes: f568f6f554b8 ARM: dts: omap: Add missing #phy-cells to usb-nop-xceiv Fixes: d745d5f277bf ARM: dts: imx51-zii-rdu1: Add missing #phy-cells to usb-nop-xceiv Fixes: 915fbe59cbf2 ARM: dts: imx: Add missing #phy-cells to usb-nop-xceiv Link: https://marc.info/?l=linux-usb&m=151518314314753&w=2 Link: https://patchwork.kernel.org/patch/10158145/ Cc: stable@vger.kernel.org Cc: Felipe Balbi <balbi@kernel.org> Cc: Eric Anholt <eric@anholt.net> Tested-by: Stefan Wahren <stefan.wahren@i2se.com> Acked-by: Rob Herring <robh@kernel.org> Tested-by: Hans Verkuil <hans.verkuil@cisco.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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