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path: root/drivers/phy/phy-ti-pipe3.c
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* phy: remove .owner field for drivers using module_platform_driverPeter Griffin2014-09-241-1/+0
| | | | | | | | | This patch removes the superflous .owner field for drivers which use the module_platform_driver or platform_driver_register api, as this is overriden in __platform_driver_register. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: phy-ti-pipe3: Remove unncessary site specific OOM messagesPeter Griffin2014-09-241-3/+2
| | | | | | | | | | | | | The site specific OOM messages are unncessary, because they duplicate messages from the memory subsystem which include dump_stack(). Removing these superflous messages makes the kernel smaller. A discussion here http://patchwork.ozlabs.org/patch/324158/ found that all error paths from kzalloc will print a error message, and that any error path which maybe found which doesn't would be considered a bug in kzalloc. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: core: Let node ptr of PHY point to PHY and not of PHY providerKishon Vijay Abraham I2014-07-221-1/+1
| | | | | | | | | | | In case of multi-phy PHY providers, each PHY should be modeled as a sub node of the PHY provider. Then each PHY will have a different node pointer (node pointer of sub node) than that of PHY provider. Added this provision in the PHY core. Also fixed all drivers to use the updated API. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Acked-by: Lee Jones <lee.jones@linaro.org>
* phy: pipe3: insert delay to enumerate in GEN2 modeKishon Vijay Abraham I2014-07-221-1/+3
| | | | | | | | | 8-bit delay value (0xF1) is required for GEN2 devices to be enumerated consistently. Added an API to be called from PHY drivers to set this delay value and called it from PIPE3 driver to set the delay value. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Roger Quadros <rogerq@ti.com>
* phy: phy-omap-pipe3: Add support for PCIe PHYKishon Vijay Abraham I2014-07-221-21/+82
| | | | | | | | PCIe PHY uses an external pll instead of the internal pll used by SATA and USB3. So added support in pipe3 PHY to use external pll. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Roger Quadros <rogerq@ti.com>
* phy: ti-pipe3: Fix suspend/resume and module reloadRoger Quadros2014-03-091-0/+4
| | | | | | | | | | Due to Errata i783, SATA breaks if its DPLL is idled. The recommeded workaround to issue a softreset to the SATA controller doesn't seem to work. Here we just prevent SATA DPLL from Idling and hence avoid the issue altogether. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: ti-pipe3: streamline PHY operationsRoger Quadros2014-03-091-51/+63
| | | | | | | | | | | | | Limit .power_on() and .power_off() to just control the PHY power and not the DPLL. The DPLL will be enabled in .init() and idled in .exit(). Don't reprogram the DPLL if it has been already locked by the bootloader. This fixes a problem with SATA, where it fails if SATA was used by the bootloader. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: ti-pipe3: Don't get 'wkupclk' and 'refclk' for SATA PHYRoger Quadros2014-03-091-9/+15
| | | | | | | | SATA PHY doesn't need 'wkupclk; and 'refclk' so don't try to get them for SATA PHY. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: ti-pipe3: Add SATA DPLL supportRoger Quadros2014-03-091-21/+55
| | | | | | | | | USB and SATA DPLLs need different settings. Provide the SATA DPLL settings and use the proper DPLL settings based on device tree node's compatible_id. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: ti-pipe3: cleanup clock handlingRoger Quadros2014-03-091-27/+28
| | | | | | | | | | As this driver is no longer USB specific, use generic clock names. - Fix PLL_SD_SHIFT from 9 to 10 - Don't separate prepare/unprepare clock from enable/disable. This ensures optimal power savings. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: rename struct omap_control_usb to struct omap_control_phyKishon Vijay Abraham I2014-03-091-4/+4
| | | | | | | | | | | Rename struct omap_control_usb to struct omap_control_phy since it can be used to control PHY of USB, SATA and PCIE. Also move the driver and include files under *phy* and made the corresponding changes in the users of phy-omap-control. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Roger Quadros <rogerq@ti.com> Acked-by: Felipe Balbi <balbi@ti.com>
* drivers: phy: usb3/pipe3: Adapt pipe3 driver to Generic PHY FrameworkKishon Vijay Abraham I2014-03-061-0/+413
Adapted omap-usb3 PHY driver to Generic PHY Framework and moved phy-omap-usb3 driver in drivers/usb/phy to drivers/phy and also renamed the file to phy-ti-pipe3 since this same driver will be used for SATA PHY and PCIE PHY. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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