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path: root/drivers/pci/host/pcie-rockchip.c
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* PCI: Collect all native drivers under drivers/pci/controller/Shawn Lin2018-06-081-424/+0
| | | | | | | | | | | | | | | | | | Native PCI drivers for root complex devices were originally all in drivers/pci/host/. Some of these devices can also be operated in endpoint mode. Drivers for endpoint mode didn't seem to fit in the "host" directory, so we put both the root complex and endpoint drivers in per-device directories, e.g., drivers/pci/dwc/, drivers/pci/cadence/, etc. These per-device directories contain trivial Kconfig and Makefiles and clutter drivers/pci/. Make a new drivers/pci/controllers/ directory and collect all the device-specific drivers there. No functional change intended. Link: https://lkml.kernel.org/r/1520304202-232891-1-git-send-email-shawn.lin@rock-chips.com Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> [bhelgaas: changelog] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* Merge branch 'lorenzo/pci/rockchip'Bjorn Helgaas2018-06-061-1433/+147
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - update arm64 defconfig for Rockchip (Shawn Lin) - refactor Rockchip code to facilitate both root port and endpoint mode (Shawn Lin) - add Rockchip endpoint mode driver (Shawn Lin) * lorenzo/pci/rockchip: arm64: defconfig: update config for Rockchip PCIe dt-bindings: PCI: rockchip: Add DT bindings for Rockchip PCIe EP driver PCI: rockchip: Add EP driver for Rockchip PCIe controller dt-bindings: PCI: rockchip: Rename rockchip-pcie.txt to rockchip-pcie-host.txt PCI: rockchip: Split out common function to init controller PCI: rockchip: Split out rockchip_pcie_parse_dt() to parse DT PCI: rockchip: Separate common code from RC driver # Conflicts: # drivers/pci/host/pcie-rockchip.c
| * PCI: rockchip: Add EP driver for Rockchip PCIe controllerShawn Lin2018-05-111-9/+16
| | | | | | | | | | | | | | | | | | | | Add support for the Rockchip PCIe controller in endpoint mode; it currently supports up to 32 regions with each region spanning at least 1MB as per TRM. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> [lorenzo.pieralisi@arm.com: updated commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * PCI: rockchip: Split out common function to init controllerShawn Lin2018-05-101-0/+142
| | | | | | | | | | | | | | | | | | | | | | | | Most of the initialization are used for both of RC driver and EP driver; factor the initialization out to a new function, rockchip_pcie_init_port(), in pcie-rockchip.c and rename the original function to rockchip_pcie_host_init_port() to avoid confusion. No functional changed intended. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com>
| * PCI: rockchip: Split out rockchip_pcie_parse_dt() to parse DTShawn Lin2018-05-101-0/+129
| | | | | | | | | | | | | | | | | | | | | | | | | | Most of the DT properties are used for both of RC driver and EP driver, so split them out in a new function, rockchip_pcie_parse_dt(), in pcie-rockchip.c and rename the original function to rockchip_pcie_parse_host_dt() to avoid confusion. No functional changed intended. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com>
| * PCI: rockchip: Separate common code from RC driverShawn Lin2018-05-101-1594/+31
| | | | | | | | | | | | | | | | | | | | | | In preparation for introducing EP driver for Rockchip PCIe controller, rename the RC driver from pcie-rockchip.c to pcie-rockchip-host.c, and only leave some common functions in pcie-rockchip.c in order to be reused for both of RC driver and EP driver. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com>
* | Merge branch 'lorenzo/pci/dwc'Bjorn Helgaas2018-06-061-0/+2
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - reduce Keystone "link already up" log level (Fabio Estevam) - move private DT functions to drivers/pci/ (Rob Herring) - factor out dwc CONFIG_PCI Kconfig dependencies (Rob Herring) - add DesignWare support to the endpoint test driver (Gustavo Pimentel) - add DesignWare support for endpoint mode (Gustavo Pimentel) - use devm_ioremap_resource() instead of devm_ioremap() in dra7xx and artpec6 (Gustavo Pimentel) - fix Qualcomm bitwise NOT issue (Dan Carpenter) - add Qualcomm runtime PM support (Srinivas Kandagatla) * lorenzo/pci/dwc: PCI: qcom: add runtime pm support to pcie_port PCI: qcom: Fix a bitwise vs logical NOT typo PCI: dwc: dra7xx: Use devm_ioremap_resource() instead of devm_ioremap() PCI: dwc: artpec6: Use devm_ioremap_resource() instead of devm_ioremap() misc: pci_endpoint_test: Add DesignWare EP entry dt-bindings: PCI: designware: Add support for EP in DesignWare driver PCI: dwc: Add support for EP mode dt-bindings: PCI: designware: Example update PCI: Move private DT related functions into private header PCI: dwc: Move CONFIG_PCI depends to menu PCI: dwc: Replace magic number by defines PCI: dwc: Small computation improvement PCI: dwc: Replace lower into upper case characters PCI: dwc: Define maximum number of vectors PCI: imx6: Remove space before tabs PCI: keystone: Do not treat link up message as error # Conflicts: # include/linux/of_pci.h
| * | PCI: Move private DT related functions into private headerRob Herring2018-05-141-0/+2
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | The functions in linux/of_pci.h are primarily used by host bridge drivers, so they can be private to drivers/pci/. The remaining functions are still used mostly in host bridge drivers that still live in arch specific code. Hopefully someday, those will get moved into drivers/pci as well. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Jingoo Han <jingoohan1@gmail.com>
* | PCI: Rework of_pci_get_host_bridge_resources() to ↵Jan Kiszka2018-05-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | devm_of_pci_get_host_bridge_resources() of_pci_get_host_bridge_resources() allocates the resource structures it fills dynamically, but none of its callers care to release them so far. Rather than requiring everyone to do this explicitly, convert the existing function to a managed version. Tested-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com> Acked-by: Joao Pinto <jpinto@synopsys.com> Acked-by: Jingoo Han <jingoohan1@gmail.com> CC: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
* | PCI: Pass struct device to of_pci_get_host_bridge_resources()Jan Kiszka2018-05-301-2/+2
|/ | | | | | | | | | | | | | Another step towards a managed version of of_pci_get_host_bridge_resources(): Feed in the underlying device, rather than just the OF node. This will allow us to use managed resource allocation internally later on. Tested-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com> Acked-by: Jingoo Han <jingoohan1@gmail.com> CC: Joao Pinto <Joao.Pinto@synopsys.com> CC: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
* PCI: Add SPDX GPL-2.0+ to replace GPL v2 or later boilerplateBjorn Helgaas2018-01-281-5/+1
| | | | | | | | | | | | Add SPDX GPL-2.0+ to all PCI files that specified the GPL and allowed either GPL version 2 or any later version. Remove the boilerplate GPL version 2 or later language, relying on the assertion in b24413180f56 ("License cleanup: add SPDX GPL-2.0 license identifier to files with no license") that the SPDX identifier may be used instead of the full boilerplate text. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* Merge branch 'pci/trivial' into nextBjorn Helgaas2017-09-071-1/+1
|\ | | | | | | | | | | | | * pci/trivial: PCI: Fix typos and whitespace errors PCI: Remove unused "res" variable from pci_resource_io() PCI: Correct kernel-doc of pci_vpd_srdt_size(), pci_vpd_srdt_tag()
| * PCI: Fix typos and whitespace errorsBjorn Helgaas2017-09-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix various typos and whitespace errors: s/Synopsis/Synopsys/ s/Designware/DesignWare/ s/Keystine/Keystone/ s/gpio/GPIO/ s/pcie/PCIe/ s/phy/PHY/ s/confgiruation/configuration/ No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | PCI: rockchip: Fix platform_get_irq() error handlingFabio Estevam2017-09-051-3/+3
| | | | | | | | | | | | | | | | When platform_get_irq() fails we should propagate the real error value instead of always returning -EINVAL. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Shawn Lin <shawn.lin@rock-chips.com>
* | PCI: rockchip: Umap IO space if probe failsJeffy Chen2017-08-291-3/+5
| | | | | | | | | | | | | | Call pci_unmap_iospace() to clean up if probe fails. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | PCI: rockchip: Remove IRQ domain if probe failsJeffy Chen2017-08-291-1/+3
| | | | | | | | | | | | | | Call irq_domain_remove() to clean up if probe fails. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | PCI: rockchip: Disable vpcie0v9 if resume_noirq failsJeffy Chen2017-08-291-1/+4
| | | | | | | | | | | | | | Disable vpcie0v9 regulator if resume_noirq fails. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | PCI: rockchip: Clean up PHY if driver probe or resume failsShawn Lin2017-08-291-17/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We observed that the clk_pciephy_ref is still enabled when we fail to probe the driver. root@linaro-alip:~# grep pcie /sys/kernel/debug/clk/clk_summary clk_pciephy_ref 1 1 24000000 0 0 clk_pcie_pm 0 0 24000000 0 0 clk_pcie_core_cru 0 0 125000000 0 0 clk_pciephy_ref100m 0 0 100000000 0 0 aclk_pcie 0 0 148500000 0 0 aclk_perf_pcie 0 0 148500000 0 0 pclk_pcie 0 0 37125000 0 0 clk_pcie_core 0 0 0 0 0 clk_pciephy_ref is used by the PHY driver and we need to properly disable it for this case. Add error handling in rockchip_pcie_init_port() and rockchip_pcie_resume_noirq() to fix this issue. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | PCI: rockchip: Factor out rockchip_pcie_deinit_phys()Shawn Lin2017-08-291-14/+15
| | | | | | | | | | | | | | | | Factor out rockchip_pcie_deinit_phys() so it can be reused by rockchip_pcie_suspend_noirq() and rockchip_pcie_remove(). No functional change intended. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | PCI: rockchip: Factor out rockchip_pcie_disable_clocks()Shawn Lin2017-08-291-16/+14
| | | | | | | | | | | | | | | | | | | | | | Factor out rockchip_pcie_disable_clocks() so it can be reused by other functions. No functional change intended, but it does change the order of unpreparing clocks in the rockchip_pcie_resume_noirq() error path so it matches the other paths. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | PCI: rockchip: Factor out rockchip_pcie_enable_clocks()Shawn Lin2017-08-291-45/+45
| | | | | | | | | | | | | | | | | | | | Factor out rockchip_pcie_enable_clocks() so it can be reused by rockchip_pcie_resume_noirq() and rockchip_pcie_probe(). No functional change intended, but it does change the order of unpreparing clocks in the rockchip_pcie_resume_noirq() error path. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | PCI: rockchip: Factor out rockchip_pcie_setup_irq()Shawn Lin2017-08-291-35/+47
| | | | | | | | | | | | | | Factor out rockchip_pcie_setup_irq() to prepare for future bug fixes. No functional change intended. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | PCI: rockchip: Use gpiod_set_value_cansleep() to allow reset via expandersFabio Estevam2017-08-291-2/+2
| | | | | | | | | | | | | | | | | | The reset GPIO can be connected to a I2C or SPI IO expander, which may sleep, so it is safer to use the gpiod_set_value_cansleep() variant instead. Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Shawn Lin <shawn.lin@rock-chips.com>
* | PCI: rockchip: Use PCI_NUM_INTXPaul Burton2017-08-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | Use the PCI_NUM_INTX macro to indicate the number of PCI INTx interrupts rather than the magic number 4. This makes it clearer where the number comes from & what it relates to. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Shawn Lin <shawn.lin@rock-chips.com>
* | PCI: rockchip: Explicitly request exclusive reset controlPhilipp Zabel2017-08-291-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | Commit a53e35db70d1 ("reset: Ensure drivers are explicit when requesting reset lines") started to transition the reset control request API calls to explicitly state whether the driver needs exclusive or shared reset control behavior. Convert all drivers requesting exclusive resets to the explicit API call so the temporary transition helpers can be removed. No functional changes. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Shawn Lin <shawn.lin@rock-chips.com>
* | PCI: rockchip: Idle inactive PHY(s)Shawn Lin2017-08-281-2/+38
| | | | | | | | | | | | | | | | | | | | Check the status of all lanes and idle the inactive one(s). Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> [bhelgaas: always set lanes_map, even for legacy_phy case] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
* | PCI: rockchip: Add per-lane PHY supportShawn Lin2017-08-281-20/+58
| | | | | | | | | | | | | | | | | | | | | | | | We distinguish the legacy PHY from newer per-lane PHYs by adding legacy_phy flag. Note that the legacy PHY is still the first option to be searched in order not to break the backward compatibility of DTB. Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> [bhelgaas: tidy rockchip_pcie_get_phys()] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
* | PCI: rockchip: Factor out rockchip_pcie_get_phys()Shawn Lin2017-08-161-6/+16
| | | | | | | | | | | | | | | | | | | | We plan to introduce per-lane PHYs, so factor out rockchip_pcie_get_phys() to make it easier in the future. No functional change intended. Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
* | PCI: rockchip: Control optional 12v power supplyShawn Lin2017-08-161-1/+24
|/ | | | | | Get vpcie12v from DT and control it if available. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* PCI: rockchip: Check for pci_scan_root_bus_bridge() failure correctlyShawn Lin2017-07-121-1/+1
| | | | | | | | | | | | | pci_scan_root_bus_bridge() returns zero for success, or a negative errno. A typo in ae13cb9b1926 ("PCI: rockchip: Convert PCI scan API to pci_scan_root_bus_bridge()") treated zero as a failure. Fix the typo. Fixes: ae13cb9b1926 ("PCI: rockchip: Convert PCI scan API to pci_scan_root_bus_bridge()") Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> [bhelgaas: changelog] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
* PCI: rockchip: Use normal register bank for config accessorsShawn Lin2017-07-031-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | Rockchip's RC has two banks of registers for the root port: a normal bank that is strictly compatible with the PCIe spec, and a privileged bank that can be used to change RO bits of root port registers. When probing the RC driver, we use the privileged bank to do some basic setup work as some RO bits are hw-inited to wrong value. But we didn't change to the normal bank after probing the driver. This leads to a serious problem when the PME code tries to clear the PME status by writing PCI_EXP_RTSTA_PME to the register of PCI_EXP_RTSTA. Per PCIe 3.0 spec, section 7.8.14, the PME status bit is RW1C. So the PME code is doing the right thing to clear the PME status but we find the RC doesn't clear it but actually setting it to one. So finally the system trap in pcie_pme_work_fn() as PCI_EXP_RTSTA_PME is true now forever. This issue can be reproduced by booting kernel with pci=nomsi. Use the normal register bank for the PCI config accessors. The privileged bank is used only internally by this driver. Fixes: e77f847d ("PCI: rockchip: Add Rockchip PCIe controller support") Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: stable@vger.kernel.org Cc: Jeffy Chen <jeffy.chen@rock-chips.com> Cc: Brian Norris <briannorris@chromium.org>
* PCI: rockchip: Use local struct device pointer consistentlyShawn Lin2017-07-021-3/+2
| | | | | | | We have a local "struct device *dev" in rockchip_pcie_probe(). Use it consistently throughout the function. No functional change intended. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* PCI: rockchip: Check for clk_prepare_enable() errors during resumeArvind Yadav2017-07-021-6/+28
| | | | | | | | clk_prepare_enable() can fail here and we must check its return value. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Shawn Lin <shawn.lin@rock-chips.com>
* PCI: rockchip: Configure RC's MPS settingShawn Lin2017-07-021-0/+8
| | | | | | | The default value of MPS for RC is 128 bytes, but actually it could support 256 bytes. So this patch fixes this issue. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* PCI: rockchip: Reconfigure configuration space header typeShawn Lin2017-07-021-0/+14
| | | | | | | | | Per PCIe base specification (Revision 3.1a), section 7.5.3, type 1 configuration space header should be used when accessing PCIe switch. So we need to reconfigure the header according to the bus number we are accessing. Otherwise we could not visit the buses behind the switch. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* PCI: rockchip: Split out rockchip_pcie_cfg_configuration_accesses()Shawn Lin2017-07-021-10/+25
| | | | | | We need to reconfigure the header type later, so split out a new function. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* PCI: rockchip: Move configuration accesses into rockchip_pcie_cfg_atu()Shawn Lin2017-07-021-10/+11
| | | | | | | Configuration accesses is also part of ATU settings, so let's keep all of them inside rockchip_pcie_cfg_atu(). Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* PCI: rockchip: Rename rockchip_cfg_atu() to rockchip_pcie_cfg_atu()Shawn Lin2017-07-021-3/+3
| | | | | | | Rename rockchip_cfg_atu() to keep the name consistent with other functions in pcie-rockchip.c. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* PCI: rockchip: Control vpcie0v9 for system PMShawn Lin2017-07-021-0/+11
| | | | | | | | | | | vpcie0v9 is used for PHY, so we could disable it as we don't need PHY to work then in S3 if folks assign it DT. But we should note that there is a side effect that we could not support beacon wakeup if we disable vpcie0v9 for aggressive power-saving. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Brian Norris <briannorris@chromium.org> Cc: Jeffy Chen <jeffy.chen@rock-chips.com>
* PCI: rockchip: Move to struct pci_host_bridge IRQ mapping functionsLorenzo Pieralisi2017-07-021-0/+2
| | | | | | | | | | | | | | | | | struct pci_host_bridge gained hooks to map/swizzle IRQs, so that the IRQ mapping can be done automatically by PCI core code through the pci_assign_irq() function instead of resorting to arch-specific implementation callbacks to carry out the same task which force PCI host bridge drivers implementation to implement per-arch kludges to carry out a task that is inherently architecture agnostic. Add map/swizzle IRQs hooks to the rockchip PCI host driver to move the IRQ allocation into core code and stop relying on arch-specific callbacks. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Wenrui Li <wenrui.li@rock-chips.com> Cc: Shawn Lin <shawn.lin@rock-chips.com>
* PCI: rockchip: Convert PCI scan API to pci_scan_root_bus_bridge()Lorenzo Pieralisi2017-07-021-6/+16
| | | | | | | | | | | | | | | | The introduction of pci_scan_root_bus_bridge() provides a PCI core API to scan a PCI root bus backed by an already initialized struct pci_host_bridge object, which simplifies the bus scan interface and makes the PCI scan root bus interface easier to generalize as members are added to the struct pci_host_bridge. Convert PCI rockchip host code to pci_scan_root_bus_bridge() to improve the PCI root bus scanning interface. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Wenrui Li <wenrui.li@rock-chips.com> Cc: Shawn Lin <shawn.lin@rock-chips.com>
* Merge branch 'pci/ioremap' into nextBjorn Helgaas2017-04-281-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * pci/ioremap: PCI: versatile: Update PCI config space remap function PCI: keystone-dw: Update PCI config space remap function PCI: layerscape: Update PCI config space remap function PCI: hisi: Update PCI config space remap function PCI: tegra: Update PCI config space remap function PCI: xgene: Update PCI config space remap function PCI: armada8k: Update PCI config space remap function PCI: designware: Update PCI config space remap function PCI: iproc-platform: Update PCI config space remap function PCI: qcom: Update PCI config space remap function PCI: rockchip: Update PCI config space remap function PCI: spear13xx: Update PCI config space remap function PCI: xilinx-nwl: Update PCI config space remap function PCI: xilinx: Update PCI config space remap function PCI: ECAM: Map config region with pci_remap_cfgspace() PCI: Implement devm_pci_remap_cfgspace() devres: fix devm_ioremap_*() offset parameter kerneldoc description ARM: Implement pci_remap_cfgspace() interface ARM64: Implement pci_remap_cfgspace() interface linux/io.h: Add pci_remap_cfgspace() interface PCI: Remove __weak tag from pci_remap_iospace()
| * PCI: rockchip: Update PCI config space remap functionLorenzo Pieralisi2017-04-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | PCI configuration space should be mapped with a memory region type that generates on the CPU host bus non-posted write transations. Update the driver to use the devm_pci_remap_cfg* interface to make sure the correct memory mappings for PCI configuration space are used. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Wenrui Li <wenrui.li@rock-chips.com> Cc: Shawn Lin <shawn.lin@rock-chips.com>
* | PCI: rockchip: ModularizeBrian Norris2017-04-211-1/+7
| | | | | | | | | | | | | | | | Now that we've exported pci_remap_iospace() and added proper remove() support, there's no reason this can't be a loadable module. Signed-off-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Shawn Lin <shawn.lin@rock-chips.com>
* | PCI: rockchip: Add remove() supportBrian Norris2017-04-211-2/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, if we try to unbind the platform device, the remove will succeed, but the removal won't undo most of the registration, leaving partially-configured PCI devices in the system. This allows, for example, a simple 'lspci' to crash the system, as it will try to touch the freed (via devm_*) driver structures, e.g., on RK3399: # echo f8000000.pcie > /sys/bus/platform/drivers/rockchip-pcie/unbind # lspci So let's implement device remove(). Signed-off-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Shawn Lin <shawn.lin@rock-chips.com>
* | PCI: rockchip: Set PCI_EXP_LNKSTA_SLC in the Root PortShawn Lin2017-04-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | All platforms using Rockchip use a common clock for the Root Port and the slot connected to it. Indicate this by setting the Slot Clock Configuration (PCI_EXP_LNKSTA_SLC) bit in the Root Port's Link Status. Per the Implementation Note in the spec (PCIe r3.1, sec 7.8.7), if the downstream component also sets PCI_EXP_LNKSTA_SLC, software may set the Common Clock Configuration (PCI_EXP_LNKCTL_CCC) bits on both ends of the Link. This is done by pcie_aspm_configure_common_clock(). Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Cc: Brian Norris <briannorris@chromium.org> Cc: jeffy.chen <jeffy.chen@rock-chips.com>
* | PCI: rockchip: Advertise 128-byte Read Completion Boundary supportShawn Lin2017-04-031-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | Rockchip Root Ports support either 64 or 128 byte Read Completion Boundary (RCB). Set the RCB bit in the Link Control register to indicate this. A 128 byte RCB significantly improves performance of NVMe with libaio. [bhelgaas: changelog] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Brian Norris <briannorris@chromium.org> Cc: Jeffy Chen <jeffy.chen@rock-chips.com>
* | PCI: rockchip: Make 'return 0' more obvious in probe()Brian Norris2017-03-231-1/+1
| | | | | | | | | | | | | | | | There's no way to get here with 'err != 0'. Just return 0 to be more obvious and prevent future changes from accidentally erroring out here without going through the right error paths. Signed-off-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | PCI: rockchip: Unindent rockchip_pcie_set_power_limit()Bjorn Helgaas2017-03-231-16/+17
| | | | | | | | | | | | | | If regulator_get_current_limit() returns 0 or error, return early so the body of the function doesn't have to be indented as the body of an "if" statement. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | PCI: rockchip: Handle regulator_get_current_limit() failure correctlyBrian Norris2017-03-231-1/+2
|/ | | | | | | | | | | | | | | | regulator_get_current_limit() can return negative error codes. We saved the return value in an unsigned "curr", and a subsequent check interpreted a negative error code as a positive (invalid) current limit. Save the return code as a signed value, which avoids messages like this, seen on Samsung Chromebook Plus: rockchip-pcie f8000000.pcie: invalid power supply [bhelgaas: changelog] Fixes: 4816c4c7b82b ("PCI: rockchip: Provide captured slot power limit and scale") Signed-off-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Shawn Lin <shawn.lin@rock-chips.com>
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