summaryrefslogtreecommitdiffstats
path: root/drivers/pci/host/pci-mvebu.c
Commit message (Collapse)AuthorAgeFilesLines
* Merge tag 'driver-core-3.19-rc1' of ↵Linus Torvalds2014-12-141-1/+0
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core Pull driver core update from Greg KH: "Here's the set of driver core patches for 3.19-rc1. They are dominated by the removal of the .owner field in platform drivers. They touch a lot of files, but they are "simple" changes, just removing a line in a structure. Other than that, a few minor driver core and debugfs changes. There are some ath9k patches coming in through this tree that have been acked by the wireless maintainers as they relied on the debugfs changes. Everything has been in linux-next for a while" * tag 'driver-core-3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core: (324 commits) Revert "ath: ath9k: use debugfs_create_devm_seqfile() helper for seq_file entries" fs: debugfs: add forward declaration for struct device type firmware class: Deletion of an unnecessary check before the function call "vunmap" firmware loader: fix hung task warning dump devcoredump: provide a one-way disable function device: Add dev_<level>_once variants ath: ath9k: use debugfs_create_devm_seqfile() helper for seq_file entries ath: use seq_file api for ath9k debugfs files debugfs: add helper function to create device related seq_file drivers/base: cacheinfo: remove noisy error boot message Revert "core: platform: add warning if driver has no owner" drivers: base: support cpu cache information interface to userspace via sysfs drivers: base: add cpu_device_create to support per-cpu devices topology: replace custom attribute macros with standard DEVICE_ATTR* cpumask: factor out show_cpumap into separate helper function driver core: Fix unbalanced device reference in drivers_probe driver core: fix race with userland in device_add() sysfs/kernfs: make read requests on pre-alloc files use the buffer. sysfs/kernfs: allow attributes to request write buffer be pre-allocated. fs: sysfs: return EGBIG on write if offset is larger than file size ...
| * pci: host: drop owner assignment from platform_driversWolfram Sang2014-10-201-1/+0
| | | | | | | | | | | | | | A platform_driver does not need to set an owner, it will be populated by the driver core. Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
* | Merge tag 'pci-v3.19-changes' of ↵Linus Torvalds2014-12-101-0/+2
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI changes from Bjorn Helgaas: "Here are the PCI changes intended for v3.19. I don't think there's anything very exciting here, but there was a lot of MSI-related stuff coming via Thomas. Details: NUMA - Allow numa_node override via sysfs (Prarit Bhargava) Resource management - Restore detection of read-only BARs (Myron Stowe) - Shrink decoding-disabled window while sizing BARs (Myron Stowe) - Add informational printk for invalid BARs (Myron Stowe) - Remove fixed parameter in pci_iov_resource_bar() (Myron Stowe) MSI - Add pci_msi_ignore_mask to prevent writes to MSI/MSI-X Mask Bits (Yijing Wang) - Revert "PCI: Add x86_msi.msi_mask_irq() and msix_mask_irq()" (Yijing Wang) - s390/MSI: Use __msi_mask_irq() instead of default_msi_mask_irq() (Yijing Wang) Virtualization - xen: Process failure for pcifront_(re)scan_root() (Chen Gang) - Make FLR and AF FLR reset warning messages different (Gavin Shan) Generic host bridge driver - Allocate config space windows after limiting bus number range (Lorenzo Pieralisi) - Convert to DT resource parsing API (Lorenzo Pieralisi) Freescale Layerscape - Add Freescale Layerscape PCIe driver (Minghuan Lian) NVIDIA Tegra - Do not build on 64-bit ARM (Thierry Reding) - Add Kconfig help text (Thierry Reding) Renesas R-Car - Make rcar_pci static (Jingoo Han) Samsung Exynos - Add exynos prefix to add_pcie_port(), pcie_init() (Jingoo Han) ST Microelectronics SPEAr13xx - Add spear prefix to add_pcie_port(), pcie_init() (Jingoo Han) - Make spear13xx_add_pcie_port() __init (Jingoo Han) - Remove unnecessary OOM message (Jingoo Han) TI DRA7xx - Add dra7xx prefix to add_pcie_port() (Jingoo Han) - Make dra7xx_add_pcie_port() __init (Jingoo Han) TI Keystone - Make ks_dw_pcie_msi_domain_ops static (Jingoo Han) - Remove unnecessary OOM message (Jingoo Han) Miscellaneous - Delete unnecessary NULL pointer checks (Markus Elfring) - Remove unused to_hotplug_slot() (Gavin Shan) - Whitespace cleanup (Jingoo Han) - Simplify if-return sequences (Quentin Lambert)" * tag 'pci-v3.19-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (28 commits) PCI: Remove fixed parameter in pci_iov_resource_bar() PCI: Add informational printk for invalid BARs PCI: tegra: Add Kconfig help text PCI: tegra: Do not build on 64-bit ARM PCI: spear: Remove unnecessary OOM message PCI: mvebu: Add a blank line after declarations PCI: designware: Add a blank line after declarations PCI: exynos: Remove unnecessary return statement PCI: imx6: Use tabs for indentation PCI: keystone: Remove unnecessary OOM message PCI: Remove unused and broken to_hotplug_slot() PCI: Make FLR and AF FLR reset warning messages different PCI: dra7xx: Add __init annotation to dra7xx_add_pcie_port() PCI: spear: Add __init annotation to spear13xx_add_pcie_port() PCI: spear: Rename add_pcie_port(), pcie_init() to spear13xx_add_pcie_port(), etc. PCI: dra7xx: Rename add_pcie_port() to dra7xx_add_pcie_port() PCI: layerscape: Add Freescale Layerscape PCIe driver PCI: Simplify if-return sequences PCI: Delete unnecessary NULL pointer checks PCI: Shrink decoding-disabled window while sizing BARs ...
| * | PCI: mvebu: Add a blank line after declarationsJingoo Han2014-11-131-0/+2
| |/ | | | | | | | | | | | | | | | | | | This patch fixes the following checkpatch warning: WARNING: Missing a blank line after declarations [bhelgaas: drop mvebu_pcie_add_bus() change because it's going away anyway] Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jason Cooper <jason@lakedaemon.net>
* | PCI: mvebu: Save MSI controller in pci_sys_dataYijing Wang2014-11-211-7/+4
| | | | | | | | | | | | | | Save MSI controller in pci_sys_data instead of assigning MSI controller pointer to every PCI bus in .add_bus(). Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | PCI/MSI: Rename "struct msi_chip" to "struct msi_controller"Yijing Wang2014-11-121-1/+1
|/ | | | | | | | | | | | "msi_chip" isn't very descriptive, so rename it to "msi_controller". That tells a little more about what it does and is already used in device tree bindings. No functional change. [bhelgaas: changelog, change *only* the struct name so it's reviewable] Suggested-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* PCI: mvebu: Fix uninitialized variable in mvebu_get_tgt_attr()Thomas Petazzoni2014-09-221-3/+3
| | | | | | | | | | | | | | | | | | | | Geert Uytterhoeven reported a warning when building pci-mvebu: drivers/pci/host/pci-mvebu.c: In function 'mvebu_get_tgt_attr': drivers/pci/host/pci-mvebu.c:887:39: warning: 'rtype' may be used uninitialized in this function [-Wmaybe-uninitialized] if (slot == PCI_SLOT(devfn) && type == rtype) { ^ And indeed, the code of mvebu_get_tgt_attr() may lead to the usage of rtype when being uninitialized, even though it would only happen if we had entries other than I/O space and 32 bits memory space. This commit fixes that by simply skipping the current DT range being considered, if it doesn't match the resource type we're looking for. Reported-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: stable@vger.kernel.org # v3.12+
* PCI: mvebu: Fix GPL v2 license string typoThierry Reding2014-07-151-1/+1
| | | | | | | | | | | Per license_is_gpl_compatible(), the MODULE_LICENSE() string for GPL v2 is "GPL v2", not "GPLv2". Use "GPL v2" so this module doesn't taint the kernel. [bhelgaas: changelog] Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* PCI: Whitespace cleanupRyan Desfosses2014-06-101-8/+9
| | | | | | | | | Fix various whitespace errors. No functional change. [bhelgaas: fix other similar problems] Signed-off-by: Ryan Desfosses <ryan@desfo.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* PCI: mvebu: Use '%pa' for printing 'phys_addr_t' typeFabio Estevam2014-04-291-2/+4
| | | | | | | | | | | | | | | Fix the following build warning that happens when building multi_v7_defconfig with CONFIG_ARM_LPAE=y: drivers/pci/host/pci-mvebu.c:334:5: warning: format '%x' expects argument of type 'unsigned int', but argument 3 has type 'phys_addr_t' [-Wformat=] Fix the warning by using '%pa' to printing 'phys_addr_t' type. While at it, also use the more standard notation [mem 0x-0x] for memory region. [bhelgaas: make end address inclusive, remove extra spaces] Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jason Cooper <jason@lakedaemon.net> Reviewed-by: Jingoo Han <jg1.han@samsung.com>
* PCI: mvebu: Remove unnecessary use of 'conf_lock' spinlockAndrew Murray2014-04-291-8/+0
| | | | | | | | | Serialization of configuration accesses is provided by 'pci_lock' in drivers/pci/access.c thus making the driver's 'conf_lock' superfluous. Signed-off-by: Andrew Murray <amurray@embedded-bits.co.uk> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jason Cooper <jason@lakedaemon.net>
* PCI: mvebu: split PCIe BARs into multiple MBus windows when neededThomas Petazzoni2014-04-241-14/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | MBus windows are used on Marvell platforms to map certain peripherals in the physical address space. In the PCIe context, MBus windows are needed to map PCIe I/O and memory regions in the physical address. However, those MBus windows can only have power of two sizes, while PCIe BAR do not necessarily guarantee this. For this reason, the current pci-mvebu breaks on platforms where PCIe devices have BARs that don't sum up to a power of two size at the emulated bridge level. This commit fixes this by allowing the pci-mvebu driver to create multiple contiguous MBus windows (each having a power of two size) to cover a given PCIe BAR. To achieve this, two functions are added: mvebu_pcie_add_windows() and mvebu_pcie_del_windows() to respectively add and remove all the MBus windows that are needed to map the provided PCIe region base and size. The emulated PCI bridge code now calls those functions, instead of directly calling the mvebu-mbus driver functions. Fixes: 45361a4fe446 ('pci: PCIe driver for Marvell Armada 370/XP systems') Cc: <stable@vger.kernel.org> # v3.11+ Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1397823593-1932-8-git-send-email-thomas.petazzoni@free-electrons.com Tested-by: Neil Greatorex <neil@fatboyfat.co.uk> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* PCI: mvebu: fix off-by-one in the computed size of the mbus windowsWilly Tarreau2014-04-241-2/+2
| | | | | | | | | | | | | | | | | | | | | | mvebu_pcie_handle_membase_change() and mvebu_pcie_handle_iobase_change() do not correctly compute the window size. PCI uses an inclusive start/end address pair, which requires a +1 when converting to size. This only worked because a bug in the mbus driver allowed it to silently accept and round up bogus sizes. Fix this by adding one to the computed size. Fixes: 45361a4fe446 ('PCIe driver for Marvell Armada 370/XP systems') Cc: <stable@vger.kernel.org> # v3.11+ Signed-off-by: Willy Tarreau <w@1wt.eu> Reviewed-By: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1397823593-1932-5-git-send-email-thomas.petazzoni@free-electrons.com Tested-by: Neil Greatorex <neil@fatboyfat.co.uk> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* PCI: mvebu: Call request_resource() on the aperturesJason Gunthorpe2014-02-181-1/+23
| | | | | | | | | | | | | | | | | | It is typical for host drivers to request a resource for the aperture; once this is done the PCI core will properly populate resources for all BARs in the system. With this patch cat /proc/iomem will now show: e0000000-efffffff : PCI MEM 0000 e0000000-e00fffff : PCI Bus 0000:01 e0000000-e001ffff : 0000:01:00.0 Tested on Kirkwood. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jason Cooper <jason@lakedaemon.net>
* PCI: mvebu: Fix potential issue in range parsingJean-Jacques Hiblot2014-02-141-1/+1
| | | | | | | | | | | | | The second parameter of of_read_number() is not the index, but a size. As it happens, in this case it may work just fine because of the conversion to u32 and the favorable endianness on this architecture. Fixes: 11be65472a427 ("PCI: mvebu: Adapt to the new device tree layout") Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@traphandler.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Jason Cooper <jason@lakedaemon.net> Cc: stable@vger.kernel.org # v3.12+
* PCI: mvebu: Use Device ID and revision from underlying endpointAndrew Lunn2014-02-121-9/+2
| | | | | | | | | | | | | | | | | | | | | Marvell SoCs place the SoC number into the PCIe endpoint device ID. The SoC stepping is placed into the PCIe revision. The old plat-orion PCIe driver allowed this information to be seen in user space with a simple lspci command. The new driver places a virtual PCI-PCI bridge on top of these endpoints. It has its own hard coded PCI device ID. Thus it is no longer possible to see what the SoC is using lspci. When initializing the PCI-PCI bridge, set its device ID and revision from the underlying endpoint, thus restoring this functionality. Debian would like to use this in order to aid installing the correct DTB file. Fixes: 45361a4fe4464 ("pci: PCIe driver for Marvell Armada 370/XP systems") Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Jason Cooper <jason@lakedaemon.net> Cc: stable@vger.kernel.org # v3.11+
* Merge branch 'pci/host-mvebu' into nextBjorn Helgaas2014-01-071-4/+6
|\ | | | | | | | | | | * pci/host-mvebu: PCI: mvebu: Use max_t() instead of max(resource_size_t,) PCI: mvebu: Call pci_ioremap_io() at startup instead of dynamically
| * PCI: mvebu: Use max_t() instead of max(resource_size_t,)Jingoo Han2014-01-021-2/+2
| | | | | | | | | | | | | | | | | | | | | | Use max_t() instead of max(resource_size_t,) in order to fix the following checkpatch warning. WARNING: max() should probably be max_t(resource_size_t, SZ_64K, size) WARNING: max() should probably be max_t(resource_size_t, SZ_1M, size) Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jason Cooper <jason@lakedaemon.net>
| * PCI: mvebu: Call pci_ioremap_io() at startup instead of dynamicallyThomas Petazzoni2014-01-021-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mvebu PCI host controller driver uses an emulated PCI-to-PCI bridge to leverage the core PCI kernel enumeration logic to dynamically create and remove the MBus windows needed to access the memory and I/O regions of each PCI interface. In the context of this PCI-to-PCI bridge emulation, the driver emulates all reads and writes to the PCI bridge registers. Upon a write to the registers configuring the I/O base and limit, the driver was creating the MBus window and calling pci_ioremap_io() to setup the mapping. However, it turns out that accesses to these registers are made in an IRQ disabled context, while pci_ioremap_io() is a potentially sleeping function. Not only this is wrong, but it is causing fairly loud warnings at boot time when the appropriate kernel hacking options are enabled. This patch solves this by moving the pci_ioremap_io() call to the startup of the driver. At this point, we don't know how many PCI interfaces will be enabled, so we are simply remapping the entire PCI I/O space to virtual addresses. This is reasonable since this I/O space is limited to 1 MB in size, and also because the MBus windows continue to be created in a dynamic fashion only when devices need them. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | Merge branch 'pci/host-mvebu' into nextBjorn Helgaas2013-12-201-2/+1
|\ \ | |/ | | | | | | * pci/host-mvebu: PCI: mvebu: Remove redundant of_match_ptr
| * PCI: mvebu: Remove redundant of_match_ptrSachin Kamat2013-12-191-2/+1
| | | | | | | | | | | | | | | | mvebu_pcie_of_match_table is always compiled in. Hence of_match_ptr is not required. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* | Merge branch 'pci/host-mvebu' into nextBjorn Helgaas2013-12-181-31/+55
|\ \ | |/ | | | | | | | | | | | | * pci/host-mvebu: PCI: mvebu: Remove duplicate of_clk_get_by_name() call PCI: mvebu: Support a bridge with no IO port window PCI: mvebu: Obey bridge PCI_COMMAND_MEM and PCI_COMMAND_IO bits PCI: mvebu: Drop writes to bridge Secondary Status register
| * PCI: mvebu: Remove duplicate of_clk_get_by_name() callAndrew Lunn2013-12-091-8/+0
| | | | | | | | | | | | | | | | | | Probably due to a merge conflict resolution gone bad, the PCI clock is got twice. Remove the redundant call of of_clk_get_by_name(). Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Jason Cooper <jason@lakedaemon.net>
| * PCI: mvebu: Support a bridge with no IO port windowJason Gunthorpe2013-11-261-20/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make pcie-io-aperture and the IO port MBUS ID in ranges optional. If not provided the bridge reports to Linux that IO space mapping is not supported and refuses to configure an IO MBUS window. This allows both complete disable (do not specify pcie-io-aperture) and per-port disable (do not specify a IO target ranges entry for the port). Most PCIe devices these days do not require IO support to function, so having an option to disable it in the driver is useful. Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jason Cooper <jason@lakedaemon.net>
| * PCI: mvebu: Obey bridge PCI_COMMAND_MEM and PCI_COMMAND_IO bitsJason Gunthorpe2013-11-261-2/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When PCI_COMMAND_MEMORY/PCI_COMMAND_IO are cleared, the bridge should not allocate windows or even look at the window limit/base registers. Otherwise we may set up bogus windows while the PCI core code performs discovery. The core will leave PCI_COMMAND_IO cleared if it doesn't need an IO window. Have mvebu_pcie_handle_*_change respect the bits, and call the change function whenever the bits changes. Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jason Cooper <jason@lakedaemon.net>
| * PCI: mvebu: Drop writes to bridge Secondary Status registerJason Gunthorpe2013-11-261-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | There are no writable bits in the secondary status register, only RO and RW1C (write-1-to-clear) bits. The driver never sets any of the RW1C bits, so the status register should always be 0, just remove the set from the write path. Someday the RW1C bits should be copied/cleared directly from registers in the HW. [bhelgaas: changelog tweaks] Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jason Cooper <jason@lakedaemon.net>
* | PCI: mvebu: Return 'unsupported' for Interrupt Line and Interrupt PinJason Gunthorpe2013-11-261-0/+5
|/ | | | | | | | | | | | | | | | | | | | | | The emulated bridge does not support interrupts, so it should return the value 0 for Interrupt Line and Interrupt Pin. This indicates that interrupts are not supported. Since Max_Lat and Min_Gnt are also in the same 32-bit word, we return 0 for them, which means "do not care." This corrects an error message from the kernel: pci 0000:00:01.0: of_irq_parse_pci() failed with rc=135 Which is due to the default return of 0xFFFFFFFF indicating that interrupts are supported. The error message regression was caused by 16b84e5a505 ("of/irq: Create of_irq_parse_and_map_pci() to consolidate arch code.") Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jason Cooper <jason@lakedaemon.net>
* Merge tag 'devicetree-for-3.13' of ↵Linus Torvalds2013-11-121-14/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux Pull devicetree updates from Rob Herring: "DeviceTree updates for 3.13. This is a bit larger pull request than usual for this cycle with lots of clean-up. - Cross arch clean-up and consolidation of early DT scanning code. - Clean-up and removal of arch prom.h headers. Makes arch specific prom.h optional on all but Sparc. - Addition of interrupts-extended property for devices connected to multiple interrupt controllers. - Refactoring of DT interrupt parsing code in preparation for deferred probe of interrupts. - ARM cpu and cpu topology bindings documentation. - Various DT vendor binding documentation updates" * tag 'devicetree-for-3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (82 commits) powerpc: add missing explicit OF includes for ppc dt/irq: add empty of_irq_count for !OF_IRQ dt: disable self-tests for !OF_IRQ of: irq: Fix interrupt-map entry matching MIPS: Netlogic: replace early_init_devtree() call of: Add Panasonic Corporation vendor prefix of: Add Chunghwa Picture Tubes Ltd. vendor prefix of: Add AU Optronics Corporation vendor prefix of/irq: Fix potential buffer overflow of/irq: Fix bug in interrupt parsing refactor. of: set dma_mask to point to coherent_dma_mask of: add vendor prefix for PHYTEC Messtechnik GmbH DT: sort vendor-prefixes.txt of: Add vendor prefix for Cadence of: Add empty for_each_available_child_of_node() macro definition arm/versatile: Fix versatile irq specifications. of/irq: create interrupts-extended property microblaze/pci: Drop PowerPC-ism from irq parsing of/irq: Create of_irq_parse_and_map_pci() to consolidate arch code. of/irq: Use irq_of_parse_and_map() ...
| * of/irq: Create of_irq_parse_and_map_pci() to consolidate arch code.Grant Likely2013-10-241-13/+1
| | | | | | | | | | | | | | | | | | | | | | | | Several architectures open code effectively the same code block for finding and mapping PCI irqs. This patch consolidates it down to a single function. Signed-off-by: Grant Likely <grant.likely@linaro.org> Acked-by: Michal Simek <monstr@monstr.eu> Cc: Russell King <linux@arm.linux.org.uk> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| * of/irq: simplify args to irq_create_of_mappingGrant Likely2013-10-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All the callers of irq_create_of_mapping() pass the contents of a struct of_phandle_args structure to the function. Since all the callers already have an of_phandle_args pointer, why not pass it directly to irq_create_of_mapping()? Signed-off-by: Grant Likely <grant.likely@linaro.org> Acked-by: Michal Simek <monstr@monstr.eu> Acked-by: Tony Lindgren <tony@atomide.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Russell King <linux@arm.linux.org.uk> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| * of/irq: Replace of_irq with of_phandle_argsGrant Likely2013-10-241-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | struct of_irq and struct of_phandle_args are exactly the same structure. This patch makes the kernel use of_phandle_args everywhere. This in itself isn't a big deal, but it makes some follow-on patches simpler. Signed-off-by: Grant Likely <grant.likely@linaro.org> Acked-by: Michal Simek <monstr@monstr.eu> Acked-by: Tony Lindgren <tony@atomide.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| * of/irq: Rename of_irq_map_* functions to of_irq_parse_*Grant Likely2013-10-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The OF irq handling code has been overloading the term 'map' to refer to both parsing the data in the device tree and mapping it to the internal linux irq system. This is probably because the device tree does have the concept of an 'interrupt-map' function for translating interrupt references from one node to another, but 'map' is still confusing when the primary purpose of some of the functions are to parse the DT data. This patch renames all the of_irq_map_* functions to of_irq_parse_* which makes it clear that there is a difference between the parsing phase and the mapping phase. Kernel code can make use of just the parsing or just the mapping support as needed by the subsystem. The patch was generated mechanically with a handful of sed commands. Signed-off-by: Grant Likely <grant.likely@linaro.org> Acked-by: Michal Simek <monstr@monstr.eu> Acked-by: Tony Lindgren <tony@atomide.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | PCI: mvebu: make local functions staticJingoo Han2013-10-081-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | mvebu_pcie_add_bus(), mvebu_pcie_align_resource() are used only in this file. Thus, these local functions should be staticized in order to fix the following sparse warnings: drivers/pci/host/pci-mvebu.c:684:6: warning: symbol 'mvebu_pcie_add_bus' was not declared. Should it be static? drivers/pci/host/pci-mvebu.c:690:17: warning: symbol 'mvebu_pcie_align_resource' was not declared. Should it be static? Signed-off-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* | PCI: mvebu: add I/O access wrappersSeungwon Jeon2013-10-081-42/+55
| | | | | | | | | | | | | | | | This change adds wrapper functions for MMIO access to PCIe IP block. And some 8/16-bit access are replaced by 32-bit. Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* | PCI: mvebu: Dynamically detect if the PEX link is up to enable hot plugJason Gunthorpe2013-10-081-11/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | Otherwise hotplugging the PEX doesn't work at all since the driver detects the link state at probe time. Simply replacing the two tests of haslink with a register read is enough to fix it. Tested on kirkwood with repeated plug/unplug of the link partner. Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* | PCI: mvebu: add support for Marvell Dove SoCsSebastian Hesselbarth2013-09-301-0/+1
| | | | | | | | | | | | | | | | This patch adds a compatible for the PCIe controller found on Marvell Dove SoCs. Binding documentation and Kconfig entry are also updated. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* | PCI: mvebu: add support for reset on GPIOSebastian Hesselbarth2013-09-301-1/+32
| | | | | | | | | | | | | | | | | | This patch adds a check for DT passed reset-gpios property and deasserts/ asserts reset pin on probe/remove with configurable delay. Corresponding binding documentation is also updated. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* | PCI: mvebu: remove subsys_initcallSebastian Hesselbarth2013-09-301-19/+14
| | | | | | | | | | | | | | | | | | | | This removes the subsys_initcall from the driver and converts it to a normal platform_driver. Also, drvdata is set and a remove functions is added to disable the clock and free resources. As pci driver removal currently is not supported, set .suppress_bind_attrs to permit unbinding. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* | PCI: mvebu: increment nports only for registered portsSebastian Hesselbarth2013-09-301-3/+4
| | | | | | | | | | | | | | | | | | | | | | The number of ports is probed by counting the number of available child nodes. Later on, the registration of a port can fail and cause a mismatch between the ->nports counter and registered ports. This patch modifies the counting strategy, to make ->nports represent the number of registered ports instead of the number of available childs. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* | PCI: mvebu: move clock enable before register accessSebastian Hesselbarth2013-09-301-13/+12
| | | | | | | | | | | | | | | | | | | | The clock passed to PCI controller found on MVEBU SoCs may come from a clock gate. This requires the clock to be enabled before any registers are accessed. Therefore, move the clock enable before register iomap to ensure it is enabled. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* | PCI: mvebu: add support for MSIThomas Petazzoni2013-09-301-0/+26
|/ | | | | | | | | | | | | | This commit adds support for Message Signaled Interrupts in the Marvell PCIe host controller. The work is very simple: it simply gets a reference to the msi_chip associated to the PCIe controller thanks to the msi-parent DT property, and stores this reference in the pci_bus structure. This is enough to let the Linux PCI core use the functions of msi_chip to setup and teardown MSIs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Thierry Reding <thierry.reding@gmail.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* Merge tag 'soc-for-linus' of ↵Linus Torvalds2013-09-061-29/+86
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC platform changes from Olof Johansson: "This branch contains mostly additions and changes to platform enablement and SoC-level drivers. Since there's sometimes a dependency on device-tree changes, there's also a fair amount of those in this branch. Pieces worth mentioning are: - Mbus driver for Marvell platforms, allowing kernel configuration and resource allocation of on-chip peripherals. - Enablement of the mbus infrastructure from Marvell PCI-e drivers. - Preparation of MSI support for Marvell platforms. - Addition of new PCI-e host controller driver for Tegra platforms - Some churn caused by sharing of macro names between i.MX 6Q and 6DL platforms in the device tree sources and header files. - Various suspend/PM updates for Tegra, including LP1 support. - Versatile Express support for MCPM, part of big little support. - Allwinner platform support for A20 and A31 SoCs (dual and quad Cortex-A7) - OMAP2+ support for DRA7, a new Cortex-A15-based SoC. The code that touches other architectures are patches moving MSI arch-specific functions over to weak symbols and removal of ARCH_SUPPORTS_MSI, acked by PCI maintainers" * tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (266 commits) tegra-cpuidle: provide stub when !CONFIG_CPU_IDLE PCI: tegra: replace devm_request_and_ioremap by devm_ioremap_resource ARM: tegra: Drop ARCH_SUPPORTS_MSI and sort list ARM: dts: vf610-twr: enable i2c0 device ARM: dts: i.MX51: Add one more I2C2 pinmux entry ARM: dts: i.MX51: Move pins configuration under "iomuxc" label ARM: dtsi: imx6qdl-sabresd: Add USB OTG vbus pin to pinctrl_hog ARM: dtsi: imx6qdl-sabresd: Add USB host 1 VBUS regulator ARM: dts: imx27-phytec-phycore-som: Enable AUDMUX ARM: dts: i.MX27: Disable AUDMUX in the template ARM: dts: wandboard: Add support for SDIO bcm4329 ARM: i.MX5 clocks: Remove optional clock setup (CKIH1) from i.MX51 template ARM: dts: imx53-qsb: Make USBH1 functional ARM i.MX6Q: dts: Enable I2C1 with EEPROM and PMIC on Phytec phyFLEX-i.MX6 Ouad module ARM i.MX6Q: dts: Enable SPI NOR flash on Phytec phyFLEX-i.MX6 Ouad module ARM: dts: imx6qdl-sabresd: Add touchscreen support ARM: imx: add ocram clock for imx53 ARM: dts: imx: ocram size is different between imx6q and imx6dl ARM: dts: imx27-phytec-phycore-som: Fix regulator settings ARM: dts: i.MX27: Remove clock name from CPU node ...
| * Merge tag 'omap-for-v3.12/dra7xx' of ↵Kevin Hilman2013-08-191-26/+1
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc From Tony Lindgren: Minimal DRA7xx based SoC core support via Rajendra Nayak <rnayak@ti.com> * tag 'omap-for-v3.12/dra7xx' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (849 commits) ARM: DRA7: Add the build support in omap2plus ARM: DRA7: hwmod: Reuse the soc_ops used for OMAP4/5 ARM: DRA7: id: Add cpu detection support for DRA7xx based SoCs' ARM: DRA7: Kconfig: Make ARCH_NR_GPIO default to 512 ARM: DRA7: board-generic: Add basic DT support ARM: DRA7: Resue the clocksource, clockevent support ARM: DRA7: Reuse io tables and add a new .init_early ARM: DRA7: Reuse all of PRCM and MPUSS SMP infra Linux 3.11-rc5 btrfs: don't loop on large offsets in readdir Btrfs: check to see if root_list is empty before adding it to dead roots Btrfs: release both paths before logging dir/changed extents Btrfs: allow splitting of hole em's when dropping extent cache Btrfs: make sure the backref walker catches all refs to our extent Btrfs: fix backref walking when we hit a compressed extent Btrfs: do not offset physical if we're compressed Btrfs: fix extent buffer leak after backref walking Btrfs: fix a bug of snapshot-aware defrag to make it work on partial extents btrfs: fix file truncation if FALLOC_FL_KEEP_SIZE is specified dlm: kill the unnecessary and wrong device_close()->recalc_sigpending() ... Signed-off-by: Kevin Hilman <khilman@linaro.org>
| * | PCI: mvebu: Check valid base address before port setupEzequiel Garcia2013-08-061-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver does not fail to probe when it cannot obtain a port base address. Therefore, add a check for NULL base address before setting up the port, which prevents a kernel panic in such cases. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * | PCI: mvebu: Adapt to the new device tree layoutThomas Petazzoni2013-08-061-29/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new device tree layout encodes the window's target ID and attribute in the PCIe controller node's ranges property. This allows to parse such entries to obtain such information and use the recently introduced MBus API to create the windows, instead of using the current name based scheme. Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* | | Merge tag 'pci-v3.12-changes' of ↵Linus Torvalds2013-09-031-3/+4
|\ \ \ | |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI changes from Bjorn Helgaas: PCI device hotplug: - Use PCIe native hotplug, not ACPI hotplug, when possible (Neil Horman) - Assign resources on per-host bridge basis (Yinghai Lu) MPS (Max Payload Size): - Allow larger MPS settings below hotplug-capable Root Port (Yijing Wang) - Add warnings about unsafe MPS settings (Yijing Wang) - Simplify interface and messages (Bjorn Helgaas) SR-IOV: - Return -ENOSYS on non-SR-IOV devices (Stefan Assmann) - Update NumVFs register when disabling SR-IOV (Yijing Wang) Virtualization: - Add bus and slot reset support (Alex Williamson) - Fix ACS (Access Control Services) issues (Alex Williamson) Miscellaneous: - Simplify PCIe Capability accessors (Bjorn Helgaas) - Add pcibios_pm_ops for arch-specific hibernate stuff (Sebastian Ott) - Disable decoding during BAR sizing only when necessary (Zoltan Kiss) - Delay enabling bridges until they're needed (Yinghai Lu) - Split Designware support into Synopsys and Exynos parts (Jingoo Han) - Convert class code to use dev_groups (Greg Kroah-Hartman) - Cleanup Designware and Exynos I/O access wrappers (Seungwon Jeon) - Fix bridge I/O window alignment (Bjorn Helgaas) - Add pci_wait_for_pending_transaction() (Casey Leedom) - Use devm_ioremap_resource() in Marvell driver (Tushar Behera) * tag 'pci-v3.12-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (63 commits) PCI/ACPI: Fix _OSC ordering to allow PCIe hotplug use when available PCI: exynos: Add I/O access wrappers PCI: designware: Drop "addr" arg from dw_pcie_readl_rc()/dw_pcie_writel_rc() PCI: Remove pcie_cap_has_devctl() PCI: Support PCIe Capability Slot registers only for ports with slots PCI: Remove PCIe Capability version checks PCI: Allow PCIe Capability link-related register access for switches PCI: Add offsets of PCIe capability registers PCI: Tidy bitmasks and spacing of PCIe capability definitions PCI: Remove obsolete comment reference to pci_pcie_cap2() PCI: Clarify PCI_EXP_TYPE_PCI_BRIDGE comment PCI: Rename PCIe capability definitions to follow convention PCI: Warn if unsafe MPS settings detected PCI: Fix MPS peer-to-peer DMA comment syntax PCI: Disable decoding for BAR sizing only when it was actually enabled PCI: Add comment about needing pci_msi_off() even when CONFIG_PCI_MSI=n PCI: Add pcibios_pm_ops for optional arch-specific hibernate functionality PCI: Don't restrict MPS for slots below Root Ports PCI: Simplify MPS test for Downstream Port PCI: Remove unnecessary check for pcie_get_mps() failure ...
| * | PCI: mvebu: Convert to use devm_ioremap_resourceTushar Behera2013-08-061-3/+4
| |/ | | | | | | | | | | | | | | | | | | | | Commit 75096579c3ac ("lib: devres: Introduce devm_ioremap_resource()") introduced devm_ioremap_resource() and deprecated the use of devm_request_and_ioremap(). While at it, modify mvebu_pcie_map_registers() to propagate error code. Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
* | PCI: mvebu: Disable prefetchable memory support in PCI-to-PCI bridgeThomas Petazzoni2013-08-011-26/+1
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Marvell PCIe driver uses an emulated PCI-to-PCI bridge to be able to dynamically set up MBus address decoding windows for PCI I/O and memory regions depending on the PCI devices enumerated by Linux. However, this emulated PCI-to-PCI bridge logic makes the Linux PCI core believe that prefetchable memory regions are supported (because the registers are read/write), while in fact no adress decoding window is ever created for such regions. Since the Marvell MBus address decoding windows do not distinguish memory regions and prefetchable memory regions, this patch takes a simple approach: change the PCI-to-PCI bridge emulation to let the Linux PCI core know that we don't support prefetchable memory regions. To achieve this, we simply make the prefetchable memory base a read-only register that always returns 0. Reading/writing all the other prefetchable memory related registers has no effect. This problem was originally reported by Finn Hoffmann <finn@uni-bremen.de>, who couldn't get a RTL8111/8168B PCI NIC working on the NSA310 Kirkwood platform after updating to 3.11-rc. The problem was that the PCI-to-PCI bridge emulation was making the Linux PCI core believe that we support prefetchable memory, so the Linux PCI core was only filling the prefetchable memory base and limit registers, which does not lead to a MBus window being created. The below patch has been confirmed by Finn Hoffmann to fix his problem on Kirkwood, and has otherwise been successfully tested on the Armada XP GP platform with a e1000e PCIe NIC and a Marvell SATA PCIe card. Reported-by: Finn Hoffmann <finn@uni-bremen.de> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* Merge tag 'pcie_bridge-3.11' of git://git.infradead.org/users/jcooper/linux ↵Olof Johansson2013-05-311-11/+44
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into next/soc From Jason Cooper: mvebu pcie driver (bridge) for v3.11 - mvebu - allow enumeration of devices beyond physical bridges - remove faking the slot location - fix status register emulation Signed-off-by: Olof Johansson <olof@lixom.net> * tag 'pcie_bridge-3.11' of git://git.infradead.org/users/jcooper/linux: pci: mvebu: fix the emulation of the status register pci: mvebu: allow the enumeration of devices beyond physical bridges pci: mvebu: no longer fake the slot location of downstream devices
| * pci: mvebu: fix the emulation of the status registerThomas Petazzoni2013-05-271-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The status register of the PCI configuration space of PCI-to-PCI bridges contain some read-only bits, and so write-1-to-clear bits. So, the Linux PCI core sometimes writes 0xffff to this status register, and in the current PCI-to-PCI bridge emulation code of the Marvell driver, we do take all those 1s being written. Even the read-only bits are being overwritten. For now, all the read-only bits should be emulated to have the zero value. The other bits, that are write-1-to-clear bits are used to report various kind of errors, and are never set by the emulated bridge, so there is no need to support this write-1-to-clear bits mechanism. As a conclusion, the easiest solution is to simply emulate this status register by returning zero when read, and ignore the writes to it. This has two visible effects: * The devsel is no longer 'unknown' in, i.e Flags: bus master, 66MHz, user-definable features, ?? devsel, latency 0 becomes: Flags: bus master, 66MHz, user-definable features, fast devsel, latency 0 in lspci -v. This was caused by a value of 11b being read for devsel, which is an invalid value. This 11b value being read was due to a previous write of 0xffff into the status register. * The capability list is no longer broken, because we indicate to the Linux PCI core that we don't have a Capabilities Pointer in the PCI configuration space of this bridge. The following message is therefore no longer visible in lspci -v: Capabilities: [fc] <chain broken> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
OpenPOWER on IntegriCloud