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path: root/drivers/net/wireless/ath/ath10k/pci.c
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* treewide: Fix printk() message errorsMasanari Iida2016-12-141-1/+1
| | | | | | | | This patch fix spelling typos in printk and kconfig. Signed-off-by: Masanari Iida <standby24x7@gmail.com> Acked-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
* ath10k: remove unused variable ar_pciChaehyun Lim2016-09-131-2/+0
| | | | | | | | | | Trival fix to remove unused variable ar_pci in ath10k_pci_tx_pipe_cleanup when building with W=1: drivers/net/wireless/ath/ath10k/pci.c:1696:21: warning: variable 'ar_pci' set but not used [-Wunused-but-set-variable] Signed-off-by: Chaehyun Lim <chaehyun.lim@gmail.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: fix memory leak on caldata on error exit pathColin Ian King2016-09-131-1/+1
| | | | | | | | | | | | caldata is not being free'd on the error exit path, causing a memory leak and data definitely should not be freed. Free caldata instead of data. Thanks to Kalle Valo for spotting that data should not be free'd. Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* Merge branch 'ath-current' into ath-nextKalle Valo2016-09-091-1/+0
|\ | | | | | | | | | | | | | | Commit 3c97f5de1f28 ("ath10k: implement NAPI support") conflicts with ath-current. To avoid any merge problems merge ath-current to ath-next already now. Conflicts: drivers/net/wireless/ath/ath10k/htt_rx.c
| * ath10k: Remove driver log suggesting QCA9887 support is experimentalMohammed Shafi Shajakhan2016-08-311-1/+0
| | | | | | | | | | | | | | | | Support for QCA9887 is no longer experimental and if there are any issues we need to address them Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* | ath10k: implement NAPI supportRajkumar Manoharan2016-09-091-26/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add NAPI support for rx and tx completion. NAPI poll is scheduled from interrupt handler. The design is as below - on interrupt - schedule napi and mask interrupts - on poll - process all pipes (no actual Tx/Rx) - process Rx within budget - if quota exceeds budget reschedule napi poll by returning budget - process Tx completions and update budget if necessary - process Tx fetch indications (pull-push) - push any other pending Tx (if possible) - before resched or napi completion replenish htt rx ring buffer - if work done < budget, complete napi poll and unmask interrupts This change also get rid of two tasklets (intr_tq and txrx_compl_task). Measured peak throughput with NAPI on IPQ4019 platform in controlled environment. No noticeable reduction in throughput is seen and also observed improvements in CPU usage. Approx. 15% CPU usage got reduced in UDP uplink case. DL: AP DUT Tx UL: AP DUT Rx IPQ4019 (avg. cpu usage %) ======== TOT +NAPI =========== ============= TCP DL 644 Mbps (42%) 645 Mbps (36%) TCP UL 673 Mbps (30%) 675 Mbps (26%) UDP DL 682 Mbps (49%) 680 Mbps (49%) UDP UL 720 Mbps (28%) 717 Mbps (11%) Signed-off-by: Rajkumar Manoharan <rmanohar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* | ath10k: hide kernel addresses from logs using %pK format specifierMaharaja Kennadyrajan2016-09-021-1/+1
|/ | | | | | | | | | | With the %pK format specifier we hide the kernel addresses with the help of kptr_restrict sysctl. In this patch, %p is changed to %pK in the driver code. The sysctl is documented in Documentation/sysctl/kernel.txt. Signed-off-by: Maharaja Kennadyrajan <c_mkenna@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: enable support for QCA9888Anilkumar Kolli2016-07-081-0/+13
| | | | | | | | QCA9888 shares the same configuration with QCA99X0 with NSS=2. Signed-off-by: Anilkumar Kolli <akolli@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: fix crash during card removalMohammed Shafi Shajakhan2016-06-301-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Usually when the firmware crashes we check for the value 'FW_IND_EVENT_PENDING' in 'FW_INDICATOR_ADDRESS' and proceed with disabling the irq and dumping firmware 'crash dump'. Now when the PCI card is unplugged from the device the PCI controller seems to generate a spurious interrupt after some time which was as treated a firmware crash and resulting in the below race condition (and eventually crashing the system) ath10k_core_unregister -> ath10k_core_free_board_files ...... device unplug spurious interrupt ......... ath10k_pci_taklet -> ath10k_pci_fw_crashed_dump ...etc Clearly even after the firmware board files related data structure is freed up we are getting a spurious interrupt from PCI with 0xfffffff in the 'FW_INDICATOR_ADDRESS' resulting in scheduling of the pci tasklet and doing a crash dump, printing f/w board related info resulting in the below crash. Fix this by detecting this spurious interrupt in ath10k PCI irq handler itself and return IRQ_NONE. Thanks to Michal Kazior for helping us conclude the most appropriate fix. Call trace: EIP is at ath10k_debug_print_board_info+0x39/0xb0 [ath10k_core] EAX: 00000000 EBX: d4de15a0 ECX: 00000000 EDX: 00000064 ESI: f615ddd0 EDI: f8530000 EBP: f615de3c ESP: f615ddbc DS: 007b ES: 007b FS: 00d8 GS: 0000 SS: 0068 CR0: 80050033 CR2: 00000004 CR3: 01c0a000 CR4: 000006f0 Stack: f615ddd0 00000064 f8b4ecdd 00000000 00000000 00412f4e 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Call Trace: [<f8b1f517>] ath10k_print_driver_info+0x17/0x30 [ath10k_core] [<f875463a>] ath10k_pci_fw_crashed_dump+0x7a/0xe0 [ath10k_pci] [<f87549d0>] ath10k_pci_tasklet+0x70/0x90 [ath10k_pci] [<c106151e>] tasklet_action+0x9e/0xb0 Cc: Michal Kazior <michal.kazior@tieto.com> Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: add board data download from targetSven Eckelmann2016-06-071-0/+139
| | | | | | | | | | The QCA9887 stores its calibration data (board.bin) inside the EEPROM of the target. This has to be downloaded manually to allow the device to initialize correctly. Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com> [kvalo@qca.qualcomm.com: handle -EOPNOTSUPP and s/fetch_board_data/fetch_cal_eeprom] Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: add QCA9887 chipset supportSven Eckelmann2016-06-071-0/+18
| | | | | | | | | | | | Add the hardware name, revision, firmware names and update the pci_id table. QA9887 HW1.0 is supposed to be similar to QCA988X HW2.0 . Details about he firmware interface are currently unknown. Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com> [kvalo@qca.qualcomm.com: add a warning about experimental support] Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: update module descriptionRajkumar Manoharan2016-06-021-1/+1
| | | | | | | Update module description to advertise all supported QCA 802.11ac devices. Signed-off-by: Rajkumar Manoharan <rmanohar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: fix diag_read to collect data for larger memoryAshok Raj Nagarajan2016-06-021-12/+16
| | | | | | | | | | | | | | | | | diag_read uses dma_alloc_coherent to allocate memory requested by the caller. If this memory requested is larger, more than DIAG_TRANSFER_LIMIT (2K), then it is likely that we may not get the requested memory and we would fail. To solve this, request dma_alloc_coherent for only DIAG_TRANSFER_LIMIT, and reuse this buffer multiple times as needed to copy the data requested in smaller chunks of size not more than DIAG_TRANSFER_LIMIT. Previously we were reading into the caller's only after getting the complete requested data. Fixes: 68c03249f388 ('ath10k: convert pci_alloc_consistent() to dma_alloc_coherent()') Signed-off-by: Ashok Raj Nagarajan <arnagara@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: enable support for QCA9984Vasanthakumar Thiagarajan2016-05-241-0/+14
| | | | | | | QCA9984 shares the same configuration with QCA99X0. Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: clean up growing hw checks during safe and full resetVasanthakumar Thiagarajan2016-05-241-16/+28
| | | | | | | | | | | | | | Store pci chip secific reset funtions in struct ath10k_pci as callbacks during early ath10k_pci_probe() and use the callback to perform chip specific resets. This patch essentially adds two callback in ath10k_pci, one for doing soft reset and the other for hard reset. By using callbacks we can get rid of those hw revision checks in ath10k_pci_safe_chip_reset() and ath10k_pci_chip_reset(). As such this patch does not fix any issue. Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: remove deprecated firmware API 1 supportKalle Valo2016-04-201-1/+0
| | | | | | | This has ben deprecated years ago, I haven't heard anyone using it since and most likely it won't even work anymore. So just remove all of it. Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: remove MSI range supportRajkumar Manoharan2016-04-121-148/+16
| | | | | | | | | | | MSI-X is never well-tested, might contain bugs and generally isn't really all that useful to maintain. Also ath10k is mainly used with shared/singly-MSI interrupt systems. Hence removing MSI range support. This change will be useful for further cleanup in copy engine lock and to add NAPI support. Signed-off-by: Rajkumar Manoharan <rmanohar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: reuse copy engine 5 (htt rx) descriptorsRajkumar Manoharan2016-04-041-2/+61
| | | | | | | | | | | | | | | | | | Whenever htt rx indication i.e target to host messages are received on rx copy engine (CE5), the message will be freed after processing the response. Then CE 5 will be refilled with new descriptors at post rx processing. This memory alloc and free operations can be avoided by reusing the same descriptors. During CE pipe allocation, full ring is not initialized i.e n-1 entries are filled up. So for CE 5 full ring should be filled up to reuse descriptors. Moreover CE 5 write index will be updated in single shot instead of incremental access. This could avoid multiple pci_write and ce_ring access. From experiments, It improves CPU usage by ~3% in IPQ4019 platform. Signed-off-by: Rajkumar Manoharan <rmanohar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: cleanup copy engine receive next completionRajkumar Manoharan2016-04-041-26/+17
| | | | | | | | | | | The physical address necessary to unmap DMA ('bufferp') is stored in ath10k_skb_cb as 'paddr'. For diag register read and write operations, 'paddr' is stored in transfer context. ath10k doesn't rely on the meta/transfer_id. So the unused output arguments {bufferp, nbytesp and transfer_idp} are removed from CE recv_next completion. Signed-off-by: Rajkumar Manoharan <rmanohar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: fix erroneous return valueAnton Protopopov2016-03-031-1/+1
| | | | | | | | The ath10k_pci_hif_exchange_bmi_msg() function may return the positive value EIO instead of -EIO in case of error. Signed-off-by: Anton Protopopov <a.s.protopopov@gmail.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: add basic skeleton to support ahbRaja Mani2016-01-281-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | qca4019 uses ahb instead of pci where it slightly differs in device enumeration, clock control, reset control, etc. Good thing is that ahb also uses copy engine for the data transaction. So, the most of the stuff implemented in pci.c/ce.c are reusable in ahb case too. Device enumeration in ahb case comes through platform driver/device model. All resource details like irq, memory map, clocks, etc for qca4019 can be fetched from of_node of platform device. Simply flow would look like, device tree => platform device (kernel) => platform driver (ath10k) Device tree entry will have all qca4019 resource details and the same info will be passed to kernel. Kernel will prepare new platform device for that entry and expose DT info to of_node in platform device. Later, ath10k would register platform driver with unique compatible name and then kernels binds to corresponding compatible entry & calls ath10k ahb probe functions. From there onwards, ath10k will take control of it and move forward. New bool flag CONFIG_ATH10K_AHB is added in Kconfig to conditionally enable ahb support in ath10k. On enabling this flag, ath10k_pci.ko will have ahb support. This patch adds only basic skeleton and few macros to support ahb in the context of qca4019. Signed-off-by: Raja Mani <rmani@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: pull reusable code from pci probe and remove for ahbRaja Mani2016-01-281-22/+42
| | | | | | | | | | Some of the code present in ath10k_pci_{probe|remove} are reusable in ahb case too. To avoid code duplication, move reusable code to new functions. Later, those new functions can be called from ahb module's probe and exit functions. Signed-off-by: Raja Mani <rmani@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: make ath10k_pci_read32/write32() ops more genericRaja Mani2016-01-281-3/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | ath10k_pci_read32/write32() does work more specific to PCI by ensuring pci wake/sleep for every read and write. There is a plan to use most of stuff available in pci.c (irq stuff, copy engine, etc) for AHB case. Such kind of pci wake/sleep for every read/write is not required in AHB case (qca4019). All those reusable areas in pci.c and ce.c calls ath10k_pci_read32/write32() for low level read and write. In fact, ath10k_pci_read32/write32() should do what it does today for PCI case. But for AHB, it has to do differently. To make ath10k_pci_read32/write32() more generic, new function pointers are added in ar_pci for the function which does operation more close to the bus. Later, corresponding bus specific read and write function will be mapped to that. ath10k_pci_read32/write32() are changed to call directly those function pointers without worrying which bus underlying to it. Also, the function to get number of bank is changed in the same way. Signed-off-by: Raja Mani <rmani@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: make some of ath10k_pci_* func reusableRaja Mani2016-01-281-32/+31
| | | | | | | | | | | | Some of static functions present in pci.c file are reusable in ahb (qca4019) case. Remove static word for those reusable functions and have those function prototype declaration in pci.h file. So that, pci.h header file can be included in ahb module and reused. There is no functionality changes done in this patch. Signed-off-by: Raja Mani <rmani@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: reduce indentation by moving powersave check within functionRajkumar Manoharan2015-12-311-19/+15
| | | | | | | | | For devices that does not support PCI power save, force wake up API is used. So move powersave check inside force wakeup to reduce one level indentation. Signed-off-by: Rajkumar Manoharan <rmanohar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: wake up device before accessing registersRajkumar Manoharan2015-12-311-3/+3
| | | | | | | | | | | | | | commit 1aaf8efba0ae ("ath10k: disable PCI PS for QCA988X and QCA99X0") partially reverts pci soc powersave support added by commit 77258d409ce4 ("ath10k: enable pci soc powersaving"). While reverting the change, pci wake up function is called after accessing pci registers instead of prior to access. The assumption is that chip is woken up before accessing its registers.Though this change does not fix any known issues, this might help to avoid unknown or low power platform specific issues. Signed-off-by: Rajkumar Manoharan <rmanohar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* Merge tag 'wireless-drivers-next-for-davem-2015-12-07' of ↵David S. Miller2015-12-081-0/+11
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/wireless-drivers-next Kalle Vallo says: ==================== brcfmac * support bcm4359 which can operate in two bands concurrently * disable runtime pm for USB avoiding issues * use generic pm callback in PCIe driver * support wowlan wake indication reporting * add beamforming support * unified handling of firmware files ath10k * support Manegement Frame Protection (MFP) * add thermal throttling support for 10.4 firmware * add support for pktlog in QCA99X0 * add debugfs file to enable Bluetooth coexistence feature * use firmware's native mesh interface type instead of raw mode iwlwifi * BT coex improvements * D3 operation bugfixes * rate control improvements * firmware debugging infra improvements * ground work for multi Rx * various security fixes ==================== Conflicts: drivers/net/wireless/ath/ath10k/pci.c The conflict resolution at: http://article.gmane.org/gmane.linux.kernel.next/37391 by Stephen Rothwell was used. Signed-off-by: David S. Miller <davem@davemloft.net>
| * ath10k: add support for pktlog in QCA99X0Vivek Natarajan2015-11-041-0/+11
| | | | | | | | | | | | | | This patch adds pktlog support for 10.4 fw versions. Signed-off-by: Vivek Natarajan <nataraja@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* | ath10k: poll HTT send completion when CE 5 is unusedRajkumar Manoharan2015-11-161-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | commit a70587b3389a ("ath10k: configure copy engine 5 for HTT messages") moved send completion polling under HTT Rx (CE 5) service routine. For QCA6174 based devices copy engine 1 (CE 1) is used for HTT Rx instead of CE 5. So send completion never be called. This is causing "failed to transmit packet, dropping: -105" errors. Fix this by processing send completion from CE 1 service routine instead of CE 5. Fixes: a70587b3389a ("ath10k: configure copy engine 5 for HTT messages") Tested-by: Ryan Hsu <ryanhsu@qca.qualcomm.com> Signed-off-by: Rajkumar Manoharan <rmanohar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* | ath10k: override CE5 configuration for QCA6147 deviceRyan Hsu2015-11-121-3/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit a70587b3389a ("ath10k: configure copy engine 5 for HTT messages") introduced to use the unused CE5 for target to host message. For the device like QCA6174, CE5 already assigned for other feature. So for QCA6174, override the CE5 configuration and use the CE1 instead. This patch is based on Rajkumar's earlier patch. Fixes: a70587b3389a ("ath10k: configure copy engine 5 for HTT messages") Signed-off-by: Ryan Hsu <ryanhsu@qca.qualcomm.com> Signed-off-by: Rajkumar Manoharan <rmanohar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* | ath10k: add QCA9377 hw1.0 supportBartosz Markowski2015-11-121-0/+2
| | | | | | | | | | | | | | | | Add new BMI target version and chip id revision. Register it on supported chips list. Signed-off-by: Bartosz Markowski <bartosz.markowski@tieto.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* | ath10k: introduce dev_id to hw_paramsBartosz Markowski2015-11-121-6/+0
| | | | | | | | | | | | | | | | | | | | | | A follow up patch introducing a QCA9377 hw1.0 support will need this device identification helper for an explicit distinction of HWs, as apparently both QCA6174 hw3.0 and QCA9377 share the same BMI target version (0x0502000x). For the QCA9377 hw1.1 previously added we were just lucky we did not overlap with the same chip_id_rev. Signed-off-by: Bartosz Markowski <bartosz.markowski@tieto.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* | ath10k: fix the currently supported QCA9377 target version nameBartosz Markowski2015-11-121-1/+1
|/ | | | | | | | | | When introducing the original QCA9377 support, the chip target version was wrongly picked. The chip advertising itself with bmi target value equal to 0x05020001 is in fact a 1.1 revision. I realized this once I got a real 1.1 hw to play with. Signed-off-by: Bartosz Markowski <bartosz.markowski@tieto.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: add QCA9377 chipset supportBartosz Markowski2015-10-291-0/+18
| | | | | | | | | | | | | | Add the hardware name, revision and update the pci_id table. Currently there're two HW ref. designs available I'm aware of, with 1.0.2 and 1.1 chip revisions. I've access and been using the first one so far and this patch cover only it. QCA9377 inherits most of the stuff (e.g. fw interfaces) from QCA61x4 design, so the integration was pretty straightforward. Signed-off-by: Bartosz Markowski <bartosz.markowski@tieto.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: remove shadow copy of CE descriptors for source ringRajkumar Manoharan2015-10-291-5/+0
| | | | | | | | | | | | For the messages from host to target, shadow copy of CE descriptors are maintained in source ring. Before writing actual CE descriptor, first shadow copy is filled and then it is copied to CE address space. To optimize in download path and to reduce d-cache pressure, removing shadow copy of CE descriptors. This will also reduce driver memory consumption by 33KB during on device probing. Signed-off-by: Rajkumar Manoharan <rmanohar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: cleanup copy engine send completionRajkumar Manoharan2015-10-291-21/+7
| | | | | | | | | | | | The physical address necessary to unmap DMA ('bufferp') is stored in ath10k_skb_cb as 'paddr'. ath10k doesn't rely on the meta/transfer_id when handling send completion (htc ep id is stored in sk_buff control buffer). So the unused output arguments {bufferp, nbytesp and transfer_idp} are removed from CE send completion. This change is needed before removing the shadow copy of copy engine (CE) descriptors in follow up patch. Signed-off-by: Rajkumar Manoharan <rmanohar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: remove send completion validation in diag read/writeRajkumar Manoharan2015-10-291-20/+0
| | | | | | | | | CE diag window access is serialized (it has to be by design) so there's no way to get a different send completion. so there's no need for post completion validation. Signed-off-by: Rajkumar Manoharan <rmanohar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: disable PCI PS for QCA988X and QCA99X0Anilkumar Kolli2015-10-191-1/+82
| | | | | | | | | | | | | | | | | | This patch disables PCI PS for QCA988X and QCA99X0, Since PCI PS is validated for QCA6174, let it be enabled only for QCA6174. It would be better to execute PCI PS related functions only for the supported devices. PCI time out issue is observed with QCA99X0 on x86 platform, We will disable PCI PS for QCA988X and QCA99X0 until PCI PS is properly implemented. Taking and releasing ps_lock is causing higher CPU consumption. Michal Kazior suggested ps_lock overhead to be reworked so that ath10k_pci_wake/sleep functions are called less often, i.e. move the powersave logic up (only during irq handling, tx path, submitting fw commands) but that's a bigger change and can be implemented later. Signed-off-by: Anilkumar Kolli <akolli@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: remove htc polling for tx completionRajkumar Manoharan2015-10-161-11/+3
| | | | | | | | | | Since polling for tx completion is handled whenever target to host messages are received, removing the unnecessary polling mechanism for send completion at HTC level. Reviewed-by: Michal Kazior <michal.kazior@tieto.com> Signed-off-by: Rajkumar Manoharan <rmanohar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: remove unused dl_is_polledRajkumar Manoharan2015-10-161-8/+3
| | | | | | | | | Since polling for received messages not supported, remove unused dl_is_polled. Reviewed-by: Michal Kazior <michal.kazior@tieto.com> Signed-off-by: Rajkumar Manoharan <rmanohar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: configure copy engine 5 for HTT messagesRajkumar Manoharan2015-10-161-11/+59
| | | | | | | | | | | | | | | | | | | | | | Currently target to host (T2H) HTT messages are received at copy engine 1. These messages are processed by HTC layer in both host and target. To avoid HTC level processing overhead in both host and target, the unused copy engine 5 is being used for receiving HTT T2H messages. This will speedup the receive data processing as well as htt tx completion. Hence host and target copy engine configuration tables are updated to enable CE5 pipe. The in-direction HTT mapping is now pointing to CE5 for all HTT T2H. Moreover HTT send completion messages are polled from HTC handler as CE 4 is not interrupt-driven. For faster tx completion, CE4 polling needs to be done whenever CE pipe which transports HTT Rx (target->host) is processed. This avoids overhead of polling HTT messages from HTC layer. Servicing CE 4 faster is helping to solve "failed to transmit packet, dropping: -105". Reviewed-by: Michal Kazior <michal.kazior@tieto.com> Signed-off-by: Rajkumar Manoharan <rmanohar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: register per copy engine receive callbacksRajkumar Manoharan2015-10-161-17/+6
| | | | | | | | | | | | Register receive callbacks for every copy engines (CE) separately instead of having common receive handler. Some of the copy engines receives different type of messages (i.e HTT/HTC/pktlog) from target. Hence to service them accordingly, register per copy engine receive callbacks. Reviewed-by: Michal Kazior <michal.kazior@tieto.com> Signed-off-by: Rajkumar Manoharan <rmanohar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: register per copy engine send completion callbacksRajkumar Manoharan2015-10-161-6/+7
| | | | | | | | | | | Register send completion callbacks for every copy engines (CE) separately instead of having common completion handler. Since some of the copy engines delivers different type of messages, per-CE callbacks help to service them differently. Reviewed-by: Michal Kazior <michal.kazior@tieto.com> Signed-off-by: Rajkumar Manoharan <rmanohar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: add board 2 API supportManikanta Pubbisetty2015-10-141-6/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | QCA6174 needs different board files based on board type. To make it easier to distribute multiple board files and automatically choose correct board file create a simple TLV file format following the same principles as with FW IEs. The file is named board-2.bin and contain multiple board files. Each board file then can have multiple names. ath10k searches for file board-N.bin (where N is the interface version number for the board file, just like we for firmware files) in /lib/firmware/*, for example for qca99x0 it will try to find it here: /lib/firmware/ath10k/QCA99X0/hw2.0/board-2.bin If ath10k doesn't find board-2.bin then it will fallback to the old board.bin file. This patch adds a simple name scheme using pci device id which for now will be used by qca6174: bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x This removes the old method of having subsystem ids in ar->spec_board_id and using that in the board file name. Signed-off-by: Manikanta Pubbisetty <c_mpubbi@qti.qualcomm.com> [kvalo@qca.qualcomm.com: simplified the file format, rewrote commit log, other smaller changes] Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: optimize ce_lock on post rx buffer processingRajkumar Manoharan2015-10-091-19/+8
| | | | | | | | | | | | | | | | | | | After processing received packets from copy engine, host will allocate new buffer and queue them back to copy engine ring for further packet reception. On post rx processing path, skb allocation and dma mapping are unnecessarily handled within ce_lock. This is affecting peak throughput and also causing more CPU consumption. Optimize this by acquiring ce_lock only when accessing copy engine ring and moving skb allocation out of ce_lock. In AP148 platform with QCA99x0 in conducted environment, UDP uplink peak throughput is improved from ~1320 Mbps to ~1450 Mbps and TCP uplink peak throughput is increased from ~1240 Mbps (70% host CPU load) to ~1300 Mbps (71% CPU load). Similarly ~40Mbps improvement is observed in downlink path. Signed-off-by: Rajkumar Manoharan <rmanohar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: increase pci wakeup timeout to 30 msMaharaja Kennadyrajan2015-10-091-1/+5
| | | | | | | | | It is noticed that pci wakeup time is exceeding current timeout (10ms) randomly which is tested on QCA988x. So, the wake up time is increased to 30 ms and added debug prints to log total timeout. Signed-off-by: Maharaja Kennadyrajan <c_mkenna@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: fix whitespace usageKalle Valo2015-10-061-0/+1
| | | | | | | | | | | | checkpatch found: drivers/net/wireless/ath/ath10k/core.c:574: Blank lines aren't necessary before a close brace '}' drivers/net/wireless/ath/ath10k/mac.c:4067: Missing a blank line after declarations drivers/net/wireless/ath/ath10k/mac.c:4083: Missing a blank line after declarations drivers/net/wireless/ath/ath10k/mac.c:4084: spaces required around that '>>=' (ctx:WxV) drivers/net/wireless/ath/ath10k/pci.c:1507: Missing a blank line after declarations Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: indentation fixesKalle Valo2015-10-061-1/+1
| | | | | | | | | | | | | | | | checkpatch found: drivers/net/wireless/ath/ath10k/core.c:513: Alignment should match open parenthesis drivers/net/wireless/ath/ath10k/core.c:1266: code indent should use tabs where possible drivers/net/wireless/ath/ath10k/core.c:1267: code indent should use tabs where possible drivers/net/wireless/ath/ath10k/core.c:1268: code indent should use tabs where possible drivers/net/wireless/ath/ath10k/core.c:1269: code indent should use tabs where possible drivers/net/wireless/ath/ath10k/mac.c:4659: Alignment should match open parenthesis drivers/net/wireless/ath/ath10k/mac.c:6271: Alignment should match open parenthesis drivers/net/wireless/ath/ath10k/pci.c:2260: Alignment should match open parenthesis drivers/net/wireless/ath/ath10k/wmi.c:3510: Alignment should match open parenthesis Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: fix MSI-X registering for qca99x0Janusz Dziedzic2015-09-271-13/+5
| | | | | | | | | | | | In case of qca99x0 and MSI-X supported/enabled we failed during interrupts registering with message: ath10k_pci 0000:04:00.0: failed to request MSI-X ce irq 50: -22 Issue/fix was reproduced/tested using Dell Latitude E6430 laptop. Signed-off-by: Janusz Dziedzic <janusz.dziedzic@tieto.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: add qca6164 supportMichal Kazior2015-08-261-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | This adds additional 0x0041 PCI Device ID definition to ath10k for QCA6164 which is a 1 spatial stream sibling of the QCA6174 (which is 2 spatial stream chip). The QCA6164 needs a dedicated board.bin file which is different than the one used for QCA6174. If the board.bin is wrong the device will crash early while trying to boot firmware. The register dump will look like this: ath10k_pci 0000:02:00.0: firmware register dump: ath10k_pci 0000:02:00.0: [00]: 0x05010000 0x000015B3 0x000A012D 0x00955B31 ... Note the value 0x000A012D. Special credit goes to Alan Liu <alanliu@qca.qualcomm.com> for providing support help which enabled me to come up with this patch. Signed-off-by: Michal Kazior <michal.kazior@tieto.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
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