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* [PATCH] drivers/net/tg3: Use the DMA_{32,64}BIT_MASK constantsTobias Klauser2005-10-291-3/+4
| | | | | | | | | | | | | | This one from my DMA_{32,64}BIT_MASK series did not seem to make it through to upstream. Use the DMA_{32,64}BIT_MASK constants from dma-mapping.h when calling pci_set_dma_mask() or pci_set_consistent_dma_mask() This patch includes dma-mapping.h explicitly because it caused errors on some architectures otherwise. See http://marc.theaimsgroup.com/?t=108001993000001&r=1&w=2 for details Signed-off-by: Tobias Klauser <tklauser@nuerscht.ch> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
* drivers/net: Remove pointless checks for NULL prior to calling kfree()Jesper Juhl2005-10-281-4/+2
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* [PATCH] tg3: update version and minor fixesMichael Chan2005-10-281-4/+14
| | | | | | | | | Update version and reldate and add more sanity checking to tg3_set_settings(). Signed-off-by: Gary Zambrano <zambrano@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
* [PATCH] tg3: fix ASF heartbeatMichael Chan2005-10-281-5/+16
| | | | | | | | | | | | | | Change the ASF heart beat to 5 seconds for faster detection of system crash. The driver sends the heartbeat every 2 seconds and the ASF firmware will timeout and reset the device if no heartbeat is received after 5 seconds. The old scheme of 2 minutes is ineffective. tg3_write_mem_fast() is added to speed up the IO to send the heartbeat. When no workaround is needed, it will use direct MMIO to memory space to write to memory. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
* [PATCH] tg3: add 5714/5715 supportMichael Chan2005-10-281-14/+25
| | | | | | | | | Add complete support for 5714/5715. These chips are very similar to 5780 so the changes are very trivial. A TG3_FLG2_5780_CLASS flag is added to identify these chips. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
* [TG3]: Update driver version and release date.David S. Miller2005-10-031-2/+2
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Refine AMD K8 write-reorder chipset test.Michael Chan2005-10-031-11/+12
| | | | | | | | | | | | | | | Test for VIA K8T800 north bridge instead of AMD K8 HyperTransport bridge based on new information from Andi Kleen. The AMD HyperTransport interface is not responsible for PCI transactions and so the re-ordering is more likely done by the VIA north bridge. This code is subject to change if we get more information from AMD or VIA. PCI Express devices are excluded from doing the read flush since all chipsets in the write_reorder list are PCI chipsets. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Update driver version and release date.David S. Miller2005-09-271-2/+2
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: misc. fixesMichael Chan2005-09-271-7/+46
| | | | | | | | | | | | | | Fix interrupt test handler by adding check for IRQ assertion in PCI_STATE register in addition to the status block updated bit. Add test for valid ethernet address in tg3_set_mac_addr(). Add tg3_bus_string() to setup the PCI bus speed/width string for all PCI/PCIX/PCI Express devices. This is used to print the bus type during init_one(). Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: 5780 PHY fixesMichael Chan2005-09-271-6/+31
| | | | | | | | | | | | | | | | | | | | | | | | Fix 5780 PHY related problems: 1. MAC_RX_MODE reset must be done before setting up the MAC_MODE register on 5705_PLUS chips or the chip will stop receiving after a while. The MAC_RX_MODE reset is needed to prevent intermittently losing the first receive packet on serdes chips. 2. Skip MAC loopback test on 5780 because of hardware errata. Normal traffic including PHY loopback is not affected by the errata. 3. PHY loopback fails intermittently on 5708S and this is fixed by putting the PHY in loopback mode first before programming the MAC mode register. A MAC_RX_MODE reset is also added. 4. Return -EINVAL in tg3_nway_reset() if device is in TBI mode. Allow nway_reset if 5780S is in parallel detect mode. 5. Add missing PHY IDs in KNOWN_PHY_ID() macro. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Fix 4GB boundary tx handlingMichael Chan2005-09-171-55/+39
| | | | | | | | | | | | | | | | | | | | Fix and simplify the workaround code for the 4GB boundary tx buffer hardware bug. 1. Need to unmap the original SKB's dma addresses if a new SKB cannot be allocated. 2. Need to pass the base flag to tigon3_4gb_hwbug_workaround() or TSO won't work properly. 3. The guilty entry and length parameters for tigon3_4gb_hwbug_workaround() are removed as they are not necessary. 4. Remove assumption that only one fragment can hit the 4GB boundary. Another fragment can hit 8GB for example. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Sparse fixes for tg3Peter Hagervall2005-09-161-3/+3
| | | | | | | | Change 0 to NULL where appropriate. Signed-off-by: Peter Hagervall <hager@cs.umu.se> Acked-by: Jeff Garzik <jgarzik@pobox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Add AMD K8 to list of write-reorder chipsets.David S. Miller2005-09-161-3/+5
| | | | | | | Thanks to Andy Stewart for the report and testing debug patches from Michael Chan. Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Add support for ETHTOOL_GPERMADDR.John W. Linville2005-09-121-0/+4
| | | | | Signed-off-by: John W. Linville <linville@tuxdriver.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Do not count non-error frames dropped by the hardware as rx_errors.John W. Linville2005-09-121-2/+4
| | | | | | | Instead, count them as part of rx_missed_errors. Signed-off-by: John W. Linville <linville@tuxdriver.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Update driver version and release date.David S. Miller2005-09-051-2/+2
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Use status tag to check for new eventsMichael Chan2005-09-051-17/+15
| | | | | | | | | | | | | | Use the status tag to determine if there are new events in tg3_interrupt_tagged(). We discussed about this a while ago with Grant Grundler and DaveM. This scheme makes it unnecessary to clear the updated bit in the status block when using tagged mode, and only a simple comparison is needed to determine if there are new events. The tp->lock around netif_rx_complete() and tg3_restart_ints() is also removed. It is unnecessary with DaveM's new locking scheme. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Remove status block access in tg3_msi() and add prefetchesMichael Chan2005-09-051-17/+11
| | | | | | | | | | | | | | | | | | | Remove unnecessary status block accesses in tg3_msi(). Since MSI is not shared, it is unnecessary to read the status block to determine if there are any new events in the MSI handler. It is also unnecessary to clear the updated bit in the status block. Since the poll list is per-cpu, tg3_poll() will be scheduled to run on the same CPU that received the MSI. Prefetches for the status block and the next rx descriptors are added in tg3_msi() to improve their access times when tg3_poll() runs. In the non-MSI irq handlers, we need to check the status block because interrupts may be shared. Only prefetches for the next rx descriptors are added. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Add PHY loopback testMichael Chan2005-09-051-20/+53
| | | | | | | | Improve ethtool loopback self test by adding PHY loopback to the existing MAC loopback test. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Add ethtool -p supportMichael Chan2005-09-051-0/+33
| | | | | | Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Minor 5780 and 5752 fixesMichael Chan2005-09-051-5/+7
| | | | | | | | Minor SerDes bug fixes for 5780S and nvram bug fixes for 5780 and 5752. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Update driver version and release date.David S. Miller2005-09-011-2/+2
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Minimize locking in TX path.Michael Chan2005-09-011-11/+13
| | | | | | | | | This is similar to Eric Dumazet's tx_lock patch for tg3 but takes it one step further to eliminate the tx_lock in the tx_completion path when the tx queue is not stopped. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Fix bug in setting a tg3_flagMichael Chan2005-08-291-8/+6
| | | | | | | | | | | Found a bug while reviewing the patches the second time. The TG3_FLAG_TXD_MBOX_HWBUG flag is set after the register access methods have been determined. This patch fixes it by moving it up before the various access methods are assigned. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Eliminate one register write in tg3_restart_ints()Michael Chan2005-08-291-2/+0
| | | | | | | | | The register write to register 0x68 to restart interrupts is unnecessary as the interrupt wasn't masked in that register by the irq handler. This will save one register write in the fast path. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Add indirect register method for 5703 behind ICHMichael Chan2005-08-291-28/+162
| | | | | | | | | | | | | | | | | | | | This patch adds the new workaround for 5703 A1/A2 if it is behind certain ICH bridges. The workaround disables memory and uses config. cycles only to access all registers. The 5702/03 chips can mistakenly decode the special cycles from the ICH chipsets as memory write cycles, causing corruption of register and memory space. Only certain ICH bridges will drive special cycles with non-zero data during the address phase which can fall within the 5703's address range. This is not an ICH bug as the PCI spec allows non-zero address during special cycles. However, only these ICH bridges are known to drive non-zero addresses during special cycles. The indirect_lock is also changed to spin_lock_irqsave from spin_lock_bh because it is used in irq handler when using the indirect method to disable interrupts. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Add mailbox read methodMichael Chan2005-08-291-18/+23
| | | | | | | | This patch adds the mailbox read method and also adds an inline function tw32_mailbox_f() for mailbox writes that require read flush. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Add various register methodsMichael Chan2005-08-291-33/+33
| | | | | | | | | | This patch adds various dedicated register read/write methods for the existing workarounds, including PCIX target workaround, write with read flush, etc. The chips that require these workarounds will use these dedicated access functions. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Add basic register access function pointersMichael Chan2005-08-291-11/+23
| | | | | | | | | | | | | | This patch adds the basic function pointers to do register accesses in the fast path. This was suggested by David Miller. The idea is that various register access methods for different hardware errata can easily be implemented with these function pointers and performance will not be degraded on chips that use normal register access methods. The various register read write macros (e.g. tw32, tr32, tw32_mailbox) are redefined to call the function pointers. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Fix ethtool loopback test lockupMichael Chan2005-08-251-4/+2
| | | | | | | | | | | | | | The tg3_abort_hw() call in tg3_test_loopback() is causing lockups on some devices. tg3_abort_hw() disables the memory arbiter, causing tg3_reset_hw() to hang when it tries to write the pre-reset signature. tg3_abort_hw() should only be called after the pre-reset signature has been written. This is all done in tg3_reset_hw() so the tg3_abort_hw() call is unnecessary and can be removed. [ Also bump driver version and release date. -DaveM ] Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Update driver version and reldate.David S. Miller2005-08-191-2/+2
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Fix SerDes detectionMichael Chan2005-08-191-0/+2
| | | | | | | | | | | | | | | | | | | | | | | A problem was reported by Grant Grundler on an HP rx8620 using IOX Core LAN partno(A7109-6) 5701 copper NIC. The tg3 driver mistakenly detects this NIC as having a SerDes PHY and link does not come up as a result. The problem was caused by an incorrectly programmed eeprom that set the NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER bit in the NIC_SRAM_DATA_CFG location. This patch will override the NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER bit if a valid PHY ID is read from the MII registers on older 570x chips where the MII interface is not used on SerDes chips. On newer chips such as the 5780 that use MII for both copper and SerDes, SerDes detection must rely on the eeprom. This patch will make the SerDes detection identical to versions 3.25 and older. Signed-off-by: Michael Chan <mchan@broadcom.com> Acked-by: Grant Grundler <iod00d@hp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Save initial PCI state before registering the netdevice.David S. Miller2005-08-061-8/+8
| | | | | | | | Else on SMP systems it is possible for hotplug to execute, invoke tg3_open(), and end up loading the uninitialized PCI register save area into the card. Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Update driver version and reldate.David S. Miller2005-07-251-2/+2
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: add 5780 fiber supportMichael Chan2005-07-251-7/+249
| | | | | | | | | | Add 5780S support by adding a new tg3_setup_fiber_mii_phy() function and a timer function for parallel link detection. 5780S uses standard MII registers for 1000BaseX and runs in GMII mode as opposed to TBI mode on older serdes chips. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: disallow jumbo TSO on 5780Michael Chan2005-07-251-3/+11
| | | | | | | Disallow jumbo TSO on 5780 due to hardware restrictions. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: consolidate all DMA water mark settingsMichael Chan2005-07-251-23/+30
| | | | | | | | Consolidate all DMA watermark settings for standard and jumbo frames on all chips in tg3_init_bufmgr_config() and add new settings for 5780. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: add variable buffer size for standard ringMichael Chan2005-07-251-3/+8
| | | | | | | | Add a new rx_pkt_buf_sz to the tg3 structure to support variable buffer sizes on the standard ring. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: add 5780 basic jumbo frame supportMichael Chan2005-07-251-12/+18
| | | | | | | | | | | | Add basic jumbo frames support for 5780. This chip supports jumbo frames on the standard receive ring without the jumbo ring. The TG3_FLAG_JUMBO_ENABLE is changed to TG3_FLAG_JUMBO_RING_ENABLE to indicate using the jumbo ring on 5704 and older chips. A new TG3_FLG2_JUMBO_CAPABLE flag is added to indicate jumbo frames support with or without the jumbo ring. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: add 5780 basic supportMichael Chan2005-07-251-5/+48
| | | | | | | Add 5780 PCI IDs, chip IDs, and other basic support. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Update driver version and reldate.David S. Miller2005-07-051-2/+2
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: support for ethtool -CMichael Chan2005-07-051-2/+63
| | | | | | | Add support for ethtool -C with verification of user parameters. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Update driver version and reldate.David S. Miller2005-06-241-2/+2
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Refinements to new locking strategy.Michael Chan2005-06-241-14/+20
| | | | | | | | | | | | | | | | | | | 1. Move tp->irq_sync = 0 to before the interrupt mailbox IO in tg3_enable_ints() so that the interrupt handler will always see irq_sync == 0 when interrupts are enabled. 2. Remove the tg3_enable_ints() call in tg3_reset_hw(). Interrupts are always enabled explicitly or through tg3_netif_start(). This is to prevent interrupts being enabled while poll is disabled. 3. Update trans_start with jiffies in tg3_netif_stop() to prevent false NETDEV WATCHDOG. 4. Pass in the proper irq_sync parameter to tg3_full_lock() depending on netif_running() in some of the ethtool set calls. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Eliminate all hw IRQ handler spinlocks.David S. Miller2005-06-241-174/+130
| | | | | | | | | | | | | | | | | | | | | Move all driver spinlocks to be taken at sw IRQ context only. This fixes the skb_copy() we were doing with hw IRQs disabled (which is illegal and triggers a BUG() with HIGHMEM enabled). It also simplifies the locking all over the driver tremendously. We accomplish this feat by creating a special sequence to synchronize with the hw IRQ handler using a binary state and synchronize_irq(). This idea is from Herbert Xu. Thanks to Michael Chan for helping to track down all of the race conditions in initial versions of this code. Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Fix missing memory barriers and SD_STATUS_UPDATED bit clearing.David S. Miller2005-06-241-0/+3
| | | | | | | | | | | | | | | There must be a rmb() between reading the status block tag and calling tg3_has_work(). This was missing in tg3_mis() and tg3_interrupt_tagged(). tg3_poll() got it right. Also, SD_STATUS_UPDATED must be cleared in the status block right before we call tg3_has_work(). Only tg3_poll() got this wrong. Based upon patches and commentary from Grant Grundler and Michael Chan. Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Update driver version and release date.David S. Miller2005-06-081-2/+2
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Fix 5700/5701 DMA corruption on Apple G4.Michael Chan2005-06-081-2/+16
| | | | | | | | | | | | Fix 5700/5701 DMA write corruption on Apple G4 by detecting the Apple UniNorth PCI 1.5 chipset and adjusting the DMA write boundary to 16. DMA test fails to detect the problem with this chipset. Thanks to Manuel Perez Ayala for reporting the problem and helping to debug it. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Update driver version and release date.David S. Miller2005-06-061-2/+2
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3] Fix link failure in 5701Michael Chan2005-06-061-0/+10
| | | | | | | | | | | | | | | | | | | On some 5701 devices with older bootcode, the LED configuration bits in SRAM may be invalid with value zero. The fix is to check for invalid bits (0) and default to PHY 1 mode. Incorrect LED mode will lead to error in programming the PHY. Thanks to Grant Grundler for debugging the problem. >From Grant: | In May, 2004, tg3 v3.4 changed how MAC_LED_CTRL (0x40c) was getting | programmed and how to determine what to program into LED_CTRL. The new | code trusted NIC_SRAM_DATA_CFG (0x00000b58) to indicate what to write | to LED_CTRL and MII EXT_CTRL registers. On "IOX Core Lan", SRAM was | saying MODE_MAC (0x0) and that doesn't work. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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