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* mtd: nand: remove kerneldoc for removed function parameterBrian Norris2016-03-111-1/+0
| | | | | | | | | | The 'getchip' parameter is gone as of commit 9f3e04297b08 ("mtd: nand: don't select chip in nand_chip's block_bad op"), so kill the doc with it. Reported-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
* mtd: nand: Qualcomm NAND controller driverArchit Taneja2016-03-103-0/+2231
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Qualcomm NAND controller is found in SoCs like IPQ806x, MSM7xx, MDM9x15 series. It exists as a sub block inside the IPs EBI2 (External Bus Interface 2) and QPIC (Qualcomm Parallel Interface Controller). These IPs provide a broader interface for external slow peripheral devices such as LCD and NAND/NOR flash memory or SRAM like interfaces. We add support for the NAND controller found within EBI2. For the SoCs of our interest, we only use the NAND controller within EBI2. Therefore, it's safe for us to assume that the NAND controller is a standalone block within the SoC. The controller supports 512B, 2kB, 4kB and 8kB page 8-bit and 16-bit NAND flash devices. It contains a HW ECC block that supports BCH ECC (4, 8 and 16 bit correction/step) and RS ECC(4 bit correction/step) that covers main and spare data. The controller contains an internal 512 byte page buffer to which we read/write via DMA. The EBI2 type NAND controller uses ADM DMA for register read/write and data transfers. The controller performs page reads and writes at a codeword/step level of 512 bytes. It can support up to 2 external chips of different configurations. The driver prepares register read and write configuration descriptors for each codeword, followed by data descriptors to read or write data from the controller's internal buffer. It uses a single ADM DMA channel that we get via dmaengine API. The controller requires 2 ADM CRCIs for command and data flow control. These are passed via DT. The ecc layout used by the controller is syndrome like, but we can't use the standard syndrome ecc ops because of several reasons. First, the amount of data bytes covered by ecc isn't same in each step. Second, writing to free oob space requires us writing to the entire step in which the oob lies. This forces us to create our own ecc ops. One more difference is how the controller accesses the bad block marker. The controller ignores reading the marker when ECC is enabled. ECC needs to be explicity disabled to read or write to the bad block marker. The nand_bbt helpers library hence can't access BBMs for the controller. For now, we skip the creation of BBT and populate chip->block_bad and chip->block_markbad helpers instead. Reviewed-by: Andy Gross <agross@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Archit Taneja <architt@codeaurora.org> Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: don't select chip in nand_chip's block_bad opArchit Taneja2016-03-104-25/+22
| | | | | | | | | | | | | | | | | | | | | | | | One of the arguments passed to struct nand_chip's block_bad op is 'getchip', which, if true, is supposed to get and select the nand device, and later unselect and release the device. This op is intended to be replaceable by drivers. The drivers shouldn't be responsible for selecting/unselecting chip. Like other ops, the chip should already be selected before the block_bad op is called. Remove the getchip argument from the block_bad op and nand_block_checkbad. Move the chip selection to nand_block_isbad, since it is the only caller to nand_block_checkbad which requires chip selection. Modify nand_block_bad (the default function for the op) such that it doesn't select the chip. Remove the getchip argument from the bad_block funcs in cafe_nand, diskonchip and docg4 drivers. Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: simplify nand_bch_init() usageBoris BREZILLON2016-03-073-30/+31
| | | | | | | | | | | | nand_bch_init() requires several arguments which could directly be deduced from the mtd device. Get rid of those useless parameters. nand_bch_init() is also requiring the caller to provide a proper eccbytes value, while this value could be deduced from the ecc.size and ecc.strength value. Fallback to eccbytes calculation when it is set to 0. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: create an mtd_oobavail() helper and make use of itBoris BREZILLON2016-03-071-12/+4
| | | | | | | | | | | Currently, all MTD drivers/sublayers exposing an OOB area are doing the same kind of test to extract the available OOB size based on the mtd_info and mtd_oob_ops structures. Move this common logic into an inline function and make use of it. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Suggested-by: Priit Laes <plaes@plaes.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: kill the ecclayout->oobavail fieldBoris BREZILLON2016-03-074-14/+10
| | | | | | | | | | ecclayout->oobavail is just redundant with the mtd->oobavail field. Moreover, it prevents static const definition of ecc layouts since the NAND framework is calculating this value based on the ecclayout->oobfree field. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: check status before reporting timeoutBrian Norris2016-03-071-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | In commit b70af9bef49b ("mtd: nand: increase ready wait timeout and report timeouts"), we increased the likelihood of scheduling during nand_wait(). This makes us more likely to hit the time_before(...) condition, since a lot of time may pass before we get scheduled again. Now, the loop was already buggy, since we don't check if the NAND is ready after exiting the loop; we simply print out a timeout warning. Fix this by doing a final status check before printing a timeout message. This isn't actually a critical bug, since the only effect is a false warning print. But too many prints never hurt anyone, did they? :) Side note: perhaps I'm not smart enough, but I'm not sure what the best policy is for this kind of loop; do we busy loop (i.e., no cond_resched()) to keep the lowest I/O latency (it's not great if the resched is delaying Richard's system ~400ms)? Or do we allow rescheduling, to play nice with the rest of the system (since some operations can take quite a while)? Reported-by: Richard Weinberger <richard@nod.at> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com> Reviewed-by: Richard Weinberger <richard@nod.at> Reviewed-by: Harvey Hunt <harvey.hunt@imgtec.com>
* mtd: nand: pxa3xx_nand: kill unused field 'drcmr_cmd'Brian Norris2016-03-071-10/+0
| | | | | | | | | With this removal, we don't need to 'get' the second DMA resource either, as it's also unused. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: pxa3xx_nand: fix dmaengine initializationRobert Jarzmik2016-03-041-1/+1
| | | | | | | | | | | | | | | | | | When the driver is initialized in a pure device-tree platform, the driver's probe fails allocating the dma channel : [ 525.624435] pxa3xx-nand 43100000.nand: no resource defined for data DMA [ 525.632088] pxa3xx-nand 43100000.nand: alloc nand resource failed The reason is that the DMA IO resource is not acquired through platform resources but by OF bindings. Fix this by ensuring that DMA IO resources are only queried in the non device-tree case. Fixes: 8f5ba31aa565 ("mtd: nand: pxa3xx-nand: switch to dmaengine") Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Acked-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: sunxi: remove direct mtd->priv accessesBoris BREZILLON2016-03-041-3/+3
| | | | | | | | | mtd->priv is no longer pointing to the struct nand_chip it is attached to. Replace those accesses by mtd_to_nand() calls. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Fixes: 4be4e03efc7f ("mtd: nand: sunxi: add randomizer support") Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: brcmnand: Fix v7.1 register offsetsFlorian Fainelli2016-02-291-1/+33
| | | | | | | | | | | The BRCMNAND controller revision 7.1 is almost 100% compatible with the previous v6.0 register offset layout, except for the Correctable Error Reporting Threshold registers. Fix this by adding another table with the correct offsets for CORR_THRESHOLD and CORR_THRESHOLD_EXT. Fixes: 27c5b17cd1b1 ("mtd: nand: add NAND driver "library" for Broadcom STB NAND controller") Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: pxa3xx_nand: add support for partial chunksThomas Petazzoni2016-02-121-56/+101
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit is needed to properly support the 8-bits ECC configuration with 4KB pages. When pages larger than 2 KB are used on platforms using the PXA3xx NAND controller, the reading/programming operations need to be split in chunks of 2 KBs or less because the controller FIFO is limited to about 2 KB (i.e a bit more than 2 KB to accommodate OOB data). Due to this requirement, the data layout on NAND is a bit strange, with ECC interleaved with data, at the end of each chunk. When a 4-bits ECC configuration is used with 4 KB pages, the physical data layout on the NAND looks like this: | 2048 data | 32 spare | 30 ECC | 2048 data | 32 spare | 30 ECC | So the data chunks have an equal size, 2080 bytes for each chunk, which the driver supports properly. When a 8-bits ECC configuration is used with 4KB pages, the physical data layout on the NAND looks like this: | 1024 data | 30 ECC | 1024 data | 30 ECC | 1024 data | 30 ECC | 1024 data | 30 ECC | 64 spare | 30 ECC | So, the spare area is stored in its own chunk, which has a different size than the other chunks. Since OOB is not used by UBIFS, the initial implementation of the driver has chosen to not support reading this additional "spare" chunk of data. Unfortunately, Marvell has chosen to store the BBT signature in the OOB area. Therefore, if the driver doesn't read this spare area, Linux has no way of finding the BBT. It thinks there is no BBT, and rewrites one, which U-Boot does not recognize, causing compatibility problems between the bootloader and the kernel in terms of NAND usage. To fix this, this commit implements the support for reading a partial last chunk. This support is currently only useful for the case of 8 bits ECC with 4 KB pages, but it will be useful in the future to enable other configurations such as 12 bits and 16 bits ECC with 4 KB pages, or 8 bits ECC with 8 KB pages, etc. All those configurations have a "last" chunk that doesn't have the same size as the other chunks. In order to implement reading of the last chunk, this commit: - Adds a number of new fields to the pxa3xx_nand_info to describe how many full chunks and how many chunks we have, the size of full chunks and partial chunks, both in terms of data area and spare area. - Fills in the step_chunk_size and step_spare_size variables to describe how much data and spare should be read/written for the current read/program step. - Reworks the state machine to accommodate doing the additional read or program step when a last partial chunk is used. This commit has been tested on a Marvell Armada 398 DB board, with a 4KB page NAND, tested in both 4 bits ECC and 8 bits ECC configurations. Robert Jarzmik has tested on some PXA platforms. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Acked-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: atmel_nand: Support 32-bit ECC strengthRomain Izard2016-02-122-2/+18
| | | | | | | | | | | | | | | | As the SAMA5D2 controller supports the 32-bit ECC strength, accept it as a valid setting when required by the device tree or the NAND parameter page. Then configure the controller to use this new setting. For the binding: Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Romain Izard <romain.izard.pro@gmail.com> Tested-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: atmel_nand: Support PMECC on SAMA5D2Romain Izard2016-02-122-3/+28
| | | | | | | | | | | | | | | | | | Starting with the SAMA5D2, there is a new revision of the Atmel PMECC controller that can correct 32 bits in each sector. This controller is not 100% compatible with the previous revision that corrected a maximum of 24 bits by sector, as some register addresses overlap. Using information from the device tree, we can configure the driver to work with both versions. For the binding: Acked-by: Rob Herring <robh@kernel.org> Tested-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Romain Izard <romain.izard.pro@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: atmel_nand: Support variable RB_EDGE interruptsRomain Izard2016-02-122-9/+29
| | | | | | | | | | | | | | | | The NFC controller used to accelerate the NAND transfers on SAMA5 chips can use either RB_EDGE0 or RB_EDGE3 as its ready/busy interrupt bit. Use the controller's compatible string to select the correct bit. For the binding: Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Wenyou Yang <Wenyou.yang@atmel.com> Tested-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Romain Izard <romain.izard.pro@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: pxa3xx_nand: add register access debugRobert Jarzmik2016-02-011-5/+17
| | | | | | | | | Add verbose debug for register accesses. This enables easier debugging by following where and how hardware is stimulated, and how it answers. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Acked-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: cs553x: Fix dependencies for !HAS_IOMEM archsRichard Weinberger2016-02-011-0/+1
| | | | | | | | | Not every arch has io memory nor can this driver ever work on UML/i386. So, unbreak the build by fixing the dependencies. Signed-off-by: Richard Weinberger <richard@nod.at> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: Fix dependencies for !HAS_IOMEM archsRichard Weinberger2016-01-261-0/+2
| | | | | | | | | Not every arch has io memory. So, unbreak the build by fixing the dependencies. Signed-off-by: Richard Weinberger <richard@nod.at> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: vf610: remove useless mtd->ecclayout assignmentBoris BREZILLON2016-01-261-2/+0
| | | | | | | | | The NAND core layer is already taking care of ecclayout propagation. Remove this useless assignment. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: lpc32xx_mlc: fix ecc.sizeBoris BREZILLON2016-01-261-1/+1
| | | | | | | | According to the ECC layout description the actual ecc.size is 512 bytes and not mtd->writesize. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: kill unused ->ecclayout field in platform_nand_chip structBoris BREZILLON2016-01-261-1/+0
| | | | | | | This field is not set in any board file and can thus be dropped. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: jz4740: kill the ->ecc_layout fieldBoris BREZILLON2016-01-261-3/+0
| | | | | | | | | ->ecc_layout is not used by any board file. Kill this field to avoid any confusion. New boards are encouraged to use the default ECC layout defined in NAND core. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: s3c2410: kill the ->ecc_layout fieldBoris BREZILLON2016-01-261-3/+0
| | | | | | | | | | | | The s3c2410 is allowing board data to overload the default ECC layout defined inside the driver, but this feature is not used by board specific definitions. Kill this field so that we can easily move to a model where ecclayout are dynamically allocated by the NAND controller driver. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: atmel_nand: Use of_device_get_match_dataRomain Izard2016-01-231-3/+1
| | | | | | | | | Remove the need for forward declaration and the risk for a null pointer when accessing the private part of the compatible match table, by using the newly introduced of_device_get_match_data function. Signed-off-by: Romain Izard <romain.izard.pro@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: atmel_nand: Simplify error messagesRomain Izard2016-01-231-2/+2
| | | | | | | | | | | The error messages when the ECC controller is misconfigured through the device tree are very precise. As a result they can (and will) get obsolete when new revisions of the controller appear. Simplify them before adding the support for the new revision. Signed-off-by: Romain Izard <romain.izard.pro@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: gpmi: may use minimum required ecc for 744 oobsize NANDHan Xu2016-01-231-12/+14
| | | | | | | | | | | | | | | By default NAND driver will choose the highest ecc strength that oob could contain, in this case, for some 8K+744 NAND flash, the ecc strength will be up to 52bit, which beyonds the i.MX6QDL BCH capability (40bit). This patch allows the NAND driver try to use minimum required ecc strength if it failed to use the highest ecc, even without explicitly claiming "fsl,use-minimum-ecc" in dts. Signed-off-by: Han Xu <b45815@freescale.com> Acked-by: Huang Shijie <shijie.huang@arm.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: gpmi: add gpmi dsm supend/resume supportHuang Shijie2016-01-231-1/+46
| | | | | | | | | | | | | | | i.MX6SX supports deep sleep mode(DSM) that may turn off GPMI/BCH power during suspend, add gpmi nand suspend/resume function to release DMA channel in suspend function and re-init GPMI/BCH controller during resume function. Although it is not necessary to restore GPMI/BCH registers value for i.MX6QDL, the code doesn't distinguish different platforms to keep the code simple. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Han Xu <han.xu@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: remove EXPORT_SYMBOL of nand_scan_bbt()Thomas Petazzoni2016-01-231-2/+0
| | | | | | | | | | | | | Since commit 17799359e7b3fa6ef4f2bf926cd6821cf7903ecf ("mtd: nand_bbt: make nand_scan_bbt() static"), the nand_scan_bbt() function is marked as static but is still exported using EXPORT_SYMBOL(), which doesn't make much sense. This commit gets rid of the useless EXPORT_SYMBOL. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: sunxi: use mtd_div_by_ws() helperBrian Norris2016-01-231-1/+1
| | | | | | Suggested-by: Richard Weinberger <richard@nod.at> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
* mtd: atmel_nand: Do not warn on bitflipsRomain Izard2016-01-231-2/+2
| | | | | | | | | | | | | | | When using multi-bit ECC, it is normal for the NAND Flash driver to correct bit errors during the life of the product. Those errors will only be cleared once a threshold has been reached, and corrections can occur regularly before this. Use only dev_dbg and not dev_info to report the bitflips, to keep the system log clean when everything works correctly. Signed-off-by: Romain Izard <romain.izard.pro@gmail.com> Acked-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: sunxi: add randomizer supportBoris BREZILLON2016-01-221-26/+261
| | | | | | | | | | | | | | Add support for the randomizer engine available in Allwinner's NFC IP. Randomization is useful to support modern NAND chips which are sensitive to repeated patterns. On such NANDs you might experience an unexpectedly high number of bitflips when you repeat the same pattern all over a given NAND block. Randomizing input data mitigate this problem by avoiding such repeated patterns. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: add NAND_NEED_SCRAMBLING flag to the H27UCG8T2ATR-BC definitionBoris BREZILLON2016-01-221-2/+2
| | | | | | | | The H27UCG8T2ATR-BC requires an external data scrambler. Reflect this constraint in the nand_flash_ids definition. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: mpc5121: use 'of_machine_is_compatible' to simplify codeChristophe Jaillet2016-01-221-5/+2
| | | | | | | | | | The current code is the same as 'of_machine_is_compatible'. So use it in order to remove a few lines of code and to be more consistent with other parts of the kernel. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nuc900_nand: read correct SMISR registerArnd Bergmann2016-01-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | The nuc900_nand driver has always passed an incorrect register address in its nuc900_check_rb() function, which cannot possibly work, and in some configurations gives us a build warning: drivers/mtd/nand/nuc900_nand.c: In function 'nuc900_check_rb': drivers/mtd/nand/nuc900_nand.c:27:23: warning: passing argument 1 of '__raw_readl' makes pointer from integer without a cast [-Wint-conversion] #define REG_SMISR 0xac drivers/mtd/nand/nuc900_nand.c:118:20: note: in expansion of macro 'REG_SMISR' val = __raw_readl(REG_SMISR); This makes sure we actually read from the register rather than from (void *)0x000000ac in user space. I suspect nobody noticed this before because the nuc900_nand_devready() function never gets called, or nobody uses this driver on an upstream kernel. Possibly even both. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: jz4780_nand: replace if/else blocks with switch/caseBrian Norris2016-01-081-15/+19
| | | | | | | | | | | | | | | | | Using switch/case helps make this logic more clear and more robust. With this structure: * it's clear that this driver only support ECC_{HW,SOFT,SOFT_BCH}; and * we can sanely handle new ECC unsupported modes (right now, this code makes incorrect assumptions about the possible values in the nand_ecc_modes_t enum; e.g., what happens with NAND_ECC_HW_OOB_FIRST?) Signed-off-by: Brian Norris <computersforpeace@gmail.com> Cc: Alex Smith <alex@alex-smith.me.uk> Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com> Tested-by: Harvey Hunt <harvey.hunt@imgtec.com> Acked-by: Harvey Hunt <harvey.hunt@imgtec.com>
* mtd: nand: jz4780: Update ecc correction error codesHarvey Hunt2016-01-081-4/+4
| | | | | | | | | | | | Update jz4780_bch_ecc_correct's return codes with appropriate values, as specified in /include/linux/mtd/nand.h. Signed-off-by: Harvey Hunt <harvey.hunt@imgtec.com> Cc: Alex Smith <alex@alex-smith.me.uk> Cc: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: linux-kernel@vger.kernel.org Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nandsim: use nand_get_controller_data()Brian Norris2016-01-071-6/+12
| | | | | | | | | Commit d699ed250c07 ("mtd: nand: make use of nand_set/get_controller_data() helpers") overlooked some uses of nand_chip::priv. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
* mtd: jz4780_nand: remove useless mtd->priv = chip assignmentBrian Norris2016-01-071-1/+0
| | | | | | | | | | | As of commit 2d3b77bac34b ("mtd: nand: update mtd_to_nand()"), this assignment isn't necessary, since struct mtd_info is embedded in struct nand_chip. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Cc: Harvey Hunt <harvey.hunt@imgtec.com> Cc: Alex Smith <alex@alex-smith.me.uk> Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
* mtd: nand: make use of nand_set/get_controller_data() helpersBoris BREZILLON2016-01-0726-257/+260
| | | | | | | | | New helpers have been added to avoid directly accessing chip->field. Use them where appropriate. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> [Brian: fixed a few rebase conflicts] Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: jz4780: driver for NAND devices on JZ4780 SoCsAlex Smith2016-01-075-0/+857
| | | | | | | | | | | | | | | | | | | Add a driver for NAND devices connected to the NEMC on JZ4780 SoCs, as well as the hardware BCH controller. DMA is not currently implemented. While older 47xx SoCs also have a BCH controller, they are incompatible with the one in the 4780 due to differing register/bit positions, which would make implementing a common driver for them quite messy. Signed-off-by: Alex Smith <alex.smith@imgtec.com> Cc: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Cc: David Woodhouse <dwmw2@infradead.org> Cc: linux-mtd@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Harvey Hunt <harvey.hunt@imgtec.com> Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com> [Brian: fixed a few small mistakes] Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: jz4740: remove custom 'erased check' implementationBoris BREZILLON2016-01-061-18/+1
| | | | | | | | | | The jz4740 driver is manually checking for 'erased pages' while correcting ECC bytes. This logic can now done by the core infrastructure, and can thus be removed from this driver. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: diskonchip: remove custom 'erased check' implementationBoris BREZILLON2016-01-061-35/+3
| | | | | | | | | | The diskonchip driver is manually checking for 'erased pages' while correcting ECC bytes. This logic can now done by the core infrastructure, and can thus be removed from this driver. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: davinci: remove custom 'erased check' implementationBoris BREZILLON2016-01-061-8/+1
| | | | | | | | | | | The davinci driver is manually checking for 'erased pages' while correcting ECC bytes. This logic can now done by the core infrastructure, and can thus be removed from this driver. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Tested-by: Franklin S Cooper Jr. <fcooper@ti.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: use nand_check_erased_ecc_chunk in default ECC read functionsBoris BREZILLON2016-01-061-7/+46
| | | | | | | | | | | | The default NAND read functions are relying on the underlying controller driver to correct bitflips, but some of those controllers cannot properly fix bitflips in erased pages. Check for bitflips in erased pages in default core functions if the driver delegated the this check by setting the NAND_ECC_GENERIC_ERASED_CHECK flag. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Tested-by: Franklin S Cooper Jr. <fcooper@ti.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: return consistent error codes in ecc.correct() implementationsBoris BREZILLON2016-01-069-21/+29
| | | | | | | | | | | | | | | The error code returned by the ecc.correct() are not consistent over the all implementations. Document the expected behavior in include/linux/mtd/nand.h and fix offending implementations. [Brian: this looks like a bugfix for the ECC reporting in the bf5xx_nand driver, but we haven't seen any testing results for it] Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Tested-by: Franklin S Cooper Jr. <fcooper@ti.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: assign reasonable default name for NAND driversBrian Norris2016-01-061-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commits such as commit 853f1c58c4b2 ("mtd: nand: omap2: show parent device structure in sysfs") attempt to rely on the core MTD code to set the MTD name based on the parent device. However, nand_base tries to set a different default name according to the flash name (e.g., extracted from the ONFI parameter page), which means NAND drivers will never make use of the MTD defaults. This is not the intention of commit 853f1c58c4b2. This results in problems when trying to use the cmdline partition parser, since the MTD name is different than expected. Let's fix this by providing a default NAND name, where possible. Note that this is not really a great default name in the long run, since this means that if there are multiple MTDs attached to the same controller device, they will have the same name. But that is an existing issue and requires future work on a better controller vs. flash chip abstraction to fix properly. Fixes: 853f1c58c4b2 ("mtd: nand: omap2: show parent device structure in sysfs") Reported-by: Heiko Schocher <hs@denx.de> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com> Tested-by: Heiko Schocher <hs@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Frans Klaver <fransklaver@gmail.com> Cc: <stable@vger.kernel.org>
* mtd: nand: fix for drop unnecessary partition parser dataStephen Rothwell2016-01-051-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | From Stephen: Hi Brian, After merging the l2-mtd tree, today's linux-next build (powerpc ppc44x_defconfig) failed like this: drivers/mtd/nand/ndfc.c: In function 'ndfc_chip_init': drivers/mtd/nand/ndfc.c:177:2: error: 'ppdata' undeclared (first use in this function) ppdata.of_node = flash_np; ^ Caused by commit a61ae81a1907 ("mtd: nand: drop unnecessary partition parser data") The flash node is already correctly assigned using the new helper (nand_set_flash_node()) so the correct fix is indeed to simply drop this line. Fixes: a61ae81a1907 ("mtd: nand: drop unnecessary partition parser data") Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: sh_flctl: pass FIFO as physical addressArnd Bergmann2015-12-181-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | By convention, the FIFO address we pass using dmaengine_slave_config is a physical address in the form that is understood by the DMA engine, as a dma_addr_t, phys_addr_t or resource_size_t. The sh_flctl driver however passes a virtual __iomem address that gets cast to dma_addr_t in the slave driver. This happens to work on shmobile because that platform sets up an identity mapping for its MMIO regions, but such code is not portable to other platforms, and prevents us from ever changing the platform mapping or reusing the driver on other architectures like ARM64 that might not have the mapping. We also get a warning about a type mismatch for the case that dma_addr_t is wider than a pointer, i.e. when CONFIG_LPAE is set: drivers/mtd/nand/sh_flctl.c: In function 'flctl_setup_dma': drivers/mtd/nand/sh_flctl.c:163:17: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] cfg.dst_addr = (dma_addr_t)FLDTFIFO(flctl); This changes the driver to instead pass the physical address of the FIFO that is extracted from the MMIO resource, making the code more portable and avoiding the warning. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: denali: make MTD_NAND_DENALI_DT dependent on OFMasahiro Yamada2015-12-181-1/+1
| | | | | | | | The build passes even if CONFIG_OF is undefined, but it makes sense to let it depend on OF. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: Disable subpage writes for drivers without ecc->hwctlHelmut Schaa2015-12-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | nand_write_subpage_hwecc causes a crash if the driver did not register ecc->hwctl or ecc->calculate. Fix this by disabling subpage writes if ecc->hwctl or ecc->calculate is not provided by the driver. This behavior was introduced in commit 837a6ba4f3b6d23026674e6af6b6849a4634fff9 "mtd: nand: subpage write support for hardware based ECC schemes". This fixes a crash with fsl_elbc_nand and maybe others: Unable to handle kernel paging request for instruction fetch Faulting instruction address: 0x00000000 Oops: Kernel access of bad area, sig: 11 [#1] SMP NR_CPUS=2 P1020 RDB Modules linked in: ath9k ath9k_common pppoe ppp_async option iptable_nat ath9k_hw ath usb_wwan pppox ppp_generic nf_nat_ipv4 nf_conntrack_ipv4 mac80211 ipt_MASQUERADE cfg80211 xt_time xt_tcpudp xt_state xt_quota xt_policy xt_pkttype xt_owner xt_nat xt_multiport xt_mh CPU: 1 PID: 2161 Comm: ubiformat Not tainted 3.10.26 #6 task: efbc2700 ti: c7950000 task.ti: c7950000 NIP: 00000000 LR: c01a495c CTR: 00000000 REGS: c7951cb0 TRAP: 0400 Not tainted (3.10.26) MSR: 00029000 <CE,EE,ME> CR: 24002028 XER: 00000000 GPR00: c01a4b6c c7951d60 efbc2700 ef84b000 00000001 00000000 000001ff c7800500 GPR08: 00000000 00000000 efae5e40 c01a4ae4 24002022 10023418 c7951e5c c7800500 GPR16: c017b6a8 00000000 0000003f c053404c 00000000 00000004 00000000 00000003 GPR24: 00000010 00000200 ef84b000 c7800d00 c7800000 c7800500 ef84b1c8 00000000 NIP [00000000] (null) LR [c01a495c] nand_write_subpage_hwecc+0x74/0x174 Call Trace: [c7951d60] [c7951d64] 0xc7951d64 (unreliable) [c7951da0] [c01a4b6c] nand_write_page+0x88/0x198 [c7951dd0] [c01a5f7c] nand_do_write_ops+0x2f4/0x39c [c7951e40] [c01a61e0] nand_write+0x58/0x84 [c7951e80] [c019e29c] mtdchar_write+0x1dc/0x28c [c7951ef0] [c00aba84] vfs_write+0xcc/0x1ac [c7951f10] [c00ac04c] SyS_write+0x4c/0x90 [c7951f40] [c000cd84] ret_from_syscall+0x0/0x3c --- Exception: c01 at 0x48050ed8 LR = 0x100071b8 Instruction dump: XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ---[ end trace 161d3c65a2a15cb8 ]--- Kernel panic - not syncing: Fatal exception [Brian: editorial note - we've applied a previous fix for the driver in question (fsl_elbc_nand) long ago: commit f034d87def51 ("mtd: eLBC NAND: fix subpage write support") but this still makes sense, and it could solve issues on some other unforseen driver.] Cc: Pekon Gupta <pekon.gupta@gmail.com> Cc: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Cc: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Helmut Schaa <helmut.schaa@googlemail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
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