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path: root/drivers/mtd/nand/denali.h
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* mtd: denali: detect the number of banksJamie Iles2011-05-251-1/+1
| | | | | | | | | | Not all configurations of the Denali controller support 4 banks. The controller can support between 1 and 16 banks. Detect this from the design features register. Signed-off-by: Jamie Iles <jamie@jamieiles.com> Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: denali: remove nearly-duplicated register definitionsJamie Iles2011-05-251-314/+57
| | | | | | | | | | | The controller has interrupt enable/status register pairs for each bank (along with ECC and status registers) that differ only in address offset. Rather than providing definitions for each register, make the address a macro so that it scales for devices with different numbers of banks. Signed-off-by: Jamie Iles <jamie@jamieiles.com> Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: denali: convert to generic DMA APIJamie Iles2011-05-251-1/+1
| | | | | | | | | | Rather than using the PCI specific DMA API, convert to the generic DMA API so that we can use the Denali NAND controller on other bus types. Signed-off-by: Jamie Iles <jamie@jamieiles.com> Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* nand/denali: use dev_xx debug function to replace nand_dbg_print and some printkChuanxiao Dong2010-08-111-18/+0
| | | | | Signed-off-by: Chuanxiao Dong <chuanxiao.dong@intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: denali: Add multi connected NAND supportChuanxiao Dong2010-08-061-0/+1
| | | | | Signed-off-by: Chuanxiao Dong <chuanxiao.dong@intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: denali: Remove set_ecc_config functionChuanxiao Dong2010-08-061-0/+1
| | | | | | | | | | set_ecc_config function only set ECC_CORRECTION register, so move register setting to probe function. Since controller only support 15bit and 8bit ecc correction, updated nand ecc layout information. Signed-off-by: Chuanxiao Dong <chuanxiao.dong@intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: denali: Remove device_info_tag structureChuanxiao.Dong2010-08-061-39/+4
| | | | | | | | | | | | | | | | | | | | Hi David, I sent 4 patches using my intel email account. If there is any problem about the format of these patches, I will resend them after I arrived at home by using my gmail account, and I will keep on using gmail account to send patches. Thanks. >From 242e3bf5e17f54b1df8cf285154a7c7a61ff62e9 Mon Sep 17 00:00:00 2001 From: Chuanxiao Dong <chuanxiao.dong@intel.com> Date: Fri, 6 Aug 2010 15:29:41 +0800 Subject: [PATCH 1/4] mtd: denali: Remove device_info_tag structure. Most of the variables in this structure are useless, so just remove this structure and relevant codes. Signed-off-by: Chuanxiao Dong <chuanxiao.dong@intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: denali: rename functions which is named by using capitalsChuanxiao Dong2010-08-051-5/+0
| | | | | | | | rename these functions' name and remove additional declarations in header file Signed-off-by: Chuanxiao Dong <chuanxiao.dong@intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: denali.h: fixed checkpatch errorsDong, Chuanxiao2010-08-021-82/+78
| | | | | | | | | | | | Fix all checkpatch.pl complaints. Artem: tweaked a little and fix tab indentations, so now this is not only about checkpatch, but also about making indentations look sane. Signed-off-by: Chuanxiao Dong <chuanxiao.dong@intel.com> Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd/nand: Add Intel Moorestown/Denali NAND supportJason Roberts2010-05-131-0/+816
There is more work to be done on this but it is basically working now. Signed-off-by: Jason Roberts <jason.e.roberts@intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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