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* mmc: sdhci-cadence: fix bit shift of read data from PHY portMasahiro Yamada2017-02-151-1/+1
| | | | | | | | | | This macro is currently unused, but it may be useful for debug use. Fix it just in case. Fixes: ff6af28faff5 ("mmc: sdhci-cadence: add Cadence SD4HC support") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: meson-gx: add support for HS400 modeHeiner Kallweit2017-02-141-0/+11
| | | | | | | | | | | | | | | Add support for HS400 mode. The driver still misses support for tuning, therefore highspeed modes like HS400 might not work under all circumstances yet. Successfully tested on a Odroid C2 (S905 GXBB). Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: meson-gx: remove unneeded checks in removeHeiner Kallweit2017-02-141-6/+2
| | | | | | | | | | The remove callback is called only if probe finished successfully. Therefore these checks are not needed. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: meson-gx: reduce bounce buffer sizeHeiner Kallweit2017-02-141-1/+1
| | | | | | | | | | A bounce buffer of 512K isn't needed as the max request size is 511 * 512 byte. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: meson-gx: set max block count and request sizeHeiner Kallweit2017-02-141-0/+3
| | | | | | | | | | | | | | | So far max_blk_count isn't set what results in a default of value 8 to be used (PAGE_SIZE / block size). Block length field has 9 bits, so set max_blk_count to 2^9-1 = 511. In addition set max_req_size because max_blk_count is also limited by max_req_size / block_size. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Acked-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: meson-gx: improve interrupt handlingHeiner Kallweit2017-02-141-5/+4
| | | | | | | | | | Disabling and immediately re-enabling interrupts in meson_mmc_request doesn't provide a benefit. Instead enable interrupts in probe already. And disable interrupts in remove, this was missing so far. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: meson-gx: improve meson_mmc_irq_threadHeiner Kallweit2017-02-141-9/+6
| | | | | | | | Remove unneeded variable ret and simplify the if block. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Acked-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: meson-gx: improve meson_mmc_clk_setHeiner Kallweit2017-02-141-18/+24
| | | | | | | | | | | | | | | | | | | | | The following changes are quite small, therefore I combined them in one patch. - ret doesn't need to be initialized with 0 - use standard !clk_rate notation to check for a zero value - If clk_rate is zero we return here. Therefore all further checks in this function for clk_rate != 0 are not needed. - switch from dev_warn to dev_err if the clock can't be set - If due to clock source and available divider values the requested frequency isn't matched exactly (always the case if requested frequency is 52 MHz), then just print the differing values as debug message and not as warning. - Also remove ret from the message as it is always 0. - Set member current_clock to the current requested rate and mmc->actual_clock to the current actual rate Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: meson-gx: minor improvements in meson_mmc_set_iosHeiner Kallweit2017-02-141-2/+0
| | | | | | | | | | | | | | | | val isn't used in the switch clause and afterwards there's an identical statement. So remove it. In case of an unexpected bus width the error message indicates the intention to set the bus width to 4 and to go on. So remove the return statement. This return statement also conflicts with "setting to 4" because nothing would be set actually before returning. 4bit bus width are chosen as default as the vendor driver does it too. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Acked-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: meson: Assign the minimum clk rate as close to 400KHz as possibleUlf Hansson2017-02-141-14/+6
| | | | | | | | | | | | | | The current code dealing with calculating mmc->f_min is a bit complicated. Additionally, the attempt to set an initial clock rate should explicitly use a rate between 100KHz to 400 KHz, according the (e)MMC/SD specs, which it doesn't. Fix the problem and clean up the code by using clk_round_rate() to pick the nearest minimum rate to 400KHz (rounded down from 400kHz). Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> [Heiner: Changed from 100KHz to 400KHz to get a proper rounded rate] Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
* mmc: host: omap_hsmmc: avoid possible overflow of timeout valueRavikumar Kattekola2017-02-131-4/+5
| | | | | | | | | | | | | Fixes: a45c6cb81647 ("[ARM] 5369/1: omap mmc: Add new omap hsmmc controller for 2430 and 34xx, v3") when using really large timeout (up to 4*60*1000 ms for bkops) there is a possibility of data overflow using unsigned int so use 64 bit unsigned long long. Signed-off-by: Ravikumar Kattekola <rk@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: host: omap_hsmmc: use generic_cmd6_time to program timeout value for CMD6Kishon Vijay Abraham I2017-02-131-6/+14
| | | | | | | | | | | | | | | | | | | | commit e2bf08d643a244ccb ("omap_hsmmc: set a large data timeout for commands with busy signal") sets an arbitrary timeout value (100ms) for commands like CMD6 (MMC SWITCH). However extended CSD register defined in the eMMC standard has a field for GENERIC_CMD6_TIME which indicates the default maximum timeout for a SWITCH command. Use busy_timeout of cmd structure (populated with GENERIC_CMD6_TIME in the case of SWITCH command) to program the data timeout value in omap_hsmmc driver. SWITCH command to turn the cache on took more than 100ms to complete with MICRON eMMC card present in AM572x IDK REV 1.3A resulting in timeout and failed enumeration. It is fixed here by programming the timeout with the value advertised in GENERIC_CMD6_TIME. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Ravikumar Kattekola <rk@ti.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: host: omap_hsmmc: reset cmd line on ceb errorRavikumar Kattekola2017-02-131-1/+1
| | | | | | | | | | | | | When CEB (command end bit error) occurs reset CMD line to avoid system ending up in erroneous state. While command line is reset for CTO and CCRC errors, it's not done for CEB error. Fix it here. Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Ravikumar Kattekola <rk@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: dw_mmc: silent verbose log when calling from PM contextShawn Lin2017-02-131-5/+7
| | | | | | | | | | | | When deploying runtime PM, it's quite verbose to print the log of ios setting. Also it's useless to print it from system PM as it should be the same with booting time. We also have sysfs to get all these information from ios attribute, so let's skip this print from PM context. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: core/mmci: restore pre/post_req behaviourLinus Walleij2017-02-132-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 64b12a68a9f74bb32d8efd7af1ad8a2ba02fc884 "mmc: core: fix prepared requests while doing bkops" is fixing a bug in the wrong way. A bug in the MMCI device driver is fixed by amending the MMC core. Thinking about it: what the pre- and post-callbacks are doing is to essentially map and unmap SG lists for DMA transfers. Why would we not be able to do that just because a BKOPS command is sent inbetween? Having to unprepare/prepare the next asynchronous request for DMA seems wrong. Looking the backtrace in that commit we can see what the real problem actually is: mmci_data_irq() is calling mmci_dma_unmap() twice which is goung to call arm_dma_unmap_sg() twice and v7_dma_inv_range() twice for the same sglist and that will crash. This happens because a request is prepared, then a BKOPS is sent. The IRQ completing the BKOPS command goes through mmci_data_irq() and thinks that a DMA operation has just been completed because dma_inprogress() reports true. It then proceeds to unmap the sglist. But that was wrong! dma_inprogress() should NOT be true because no DMA was actually in progress! We had just prepared the sglist, and the DMA channel dma_current has been configured, but NOT started! Because of this, the sglist is already unmapped when we get our actual data completion IRQ, and we are unmapping the sglist once more, and we get this crash. Therefore, we need to revert this solution pushing the problem to the core and causing problems, and instead augment the implementation such that dma_inprogress() only reports true if some DMA has actually been started. After this we can keep the request prepared during the BKOPS and we need not unprepare/reprepare it. Fixes: 64b12a68a9f7 ("mmc: core: fix prepared requests while doing bkops") Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Tested-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sunxi: Add more debug informationsMaxime Ripard2017-02-131-4/+19
| | | | | | | | | | | | | Add a bit more debug messages that can be helpful when debugging the clock setup. Also fill the actual_clock field in struct mmc_host to report properly the current frequency in debugfs. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Tested-by: Florian Vaussard <florian.vaussard@heig-vd.ch> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sunxi: Add EMMC (MMC2) controller compatibleMaxime Ripard2017-02-131-0/+8
| | | | | | | | | | | | | | | | | | | | The MMC2 controller on the A64 is kind of a special beast. While the general controller design is the same than the other MMC controllers in the SoC, it also has a bunch of features and changes that prevent it to be driven in the same way. It has for example a different bus width limit, a different maximum frequency, and, for some reason, the maximum buffer size of a DMA descriptor. Add a new compatible specifically for this controller. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Tested-by: Florian Vaussard <florian.vaussard@heig-vd.ch> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sunxi: Mask DATA0 when updating the clockMaxime Ripard2017-02-131-1/+13
| | | | | | | | | | | | | | The A64 MMC controllers need DATA0 to be masked while updating the clock, otherwise any subsequent command will result in a timeout. It's not really clear at this point what DATA0 is exactly, but this behaviour is present in Allwinner's tree, and has been suggested by Allwinner engineers as fixes for the timeout. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Tested-by: Florian Vaussard <florian.vaussard@heig-vd.ch> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sunxi: Enable the new timings for the A64 MMC controllersMaxime Ripard2017-02-131-0/+6
| | | | | | | | | | | | | | The A64 MMC controllers need to set a "new timings" bit when a new rate is set. The actual meaning of that bit is not clear yet, but not setting it leads to some corner-case issues, like the CMD53 failing, which is used to implement SDIO packet aggregation. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Tested-by: Florian Vaussard <florian.vaussard@heig-vd.ch> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sunxi: Always set signal delay to 0 for A64Maxime Ripard2017-02-131-33/+17
| | | | | | | | | | | | | | | Experience have shown that the using the autocalibration could severely degrade the performances of the MMC bus. Allwinner is using in its BSP a delay set to 0 for all the modes but HS400. Remove the calibration code for now, and add comments to document our findings. Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Tested-by: Florian Vaussard <florian.vaussard@heig-vd.ch> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sunxi: Gate the clock when rate is 0Maxime Ripard2017-02-131-1/+4
| | | | | | | | | | | | The MMC core assumes that the code will gate the clock when the bus frequency is set to 0, which we've been ignoring so far. Handle that. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Tested-by: Florian Vaussard <florian.vaussard@heig-vd.ch> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sunxi: Fix clock frequency change sequenceMaxime Ripard2017-02-131-4/+4
| | | | | | | | | | | | | | | | | The SD specification documents that the clock frequency should only be changed once gated (Section 3.2.3 - SD Clock Frequency Change Sequence). The current code first modifies the parent clock, gates it and then modifies the internal divider. This means that since the parent clock rate might be changed, the bus clock might be changed as well before it is gated, which breaks the specification. Move the gating before the parent rate modification. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Tested-by: Florian Vaussard <florian.vaussard@heig-vd.ch> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci-msm: Remove unnecessary comments of CDC init sequenceRitesh Harjani2017-02-131-13/+1
| | | | | | | | | This removes CDC init sequence comments which are not useful anyway. Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci-msm: Remove platform_execute_tuning from sdhci_msm_opsRitesh Harjani2017-02-131-3/+4
| | | | | | | | | | | | | | | platform_execute_tuning should not really exist as it does not do anything useful. So remove this ops and directly plug sdhci_msm_execute_tuning with mmc_host_ops. Also in case of HS400 tuning clear SDHCI_HS400_TUNING flag once HS400 related mode selection is done. Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sh_mobile_sdhi: add support for 2 clocksChris Brandt2017-02-131-0/+23
| | | | | | | | | | Some controllers have 2 clock sources instead of 1. The 2nd clock is for the internal card detect logic and must be enabled/disabled along with the main core clock for proper operation. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
* mmc: meson: cleanup stray debug messagesKevin Hilman2017-02-131-3/+4
| | | | | | | | Cleanup some debug prints that cause needless noise during normal usage. Signed-off-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci-s3c: use the bitops API for bit operationJaehoon Chung2017-02-131-20/+21
| | | | | | | Use the bitops API instead of shifting directly. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci-s3c: remove the sdhci-s3c-regs header fileJaehoon Chung2017-02-132-88/+69
| | | | | | | | Remove the sdhci-s3c-regs.h file. Instead, it located those defined values into sdhci-s3c.c. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: tmio: discard obsolete SDIO irqs before enabling irqsWolfram Sang2017-02-132-2/+13
| | | | | | | | | Before enabling SDIO irqs, clear the status bit, so we discard old and stale interrupts. Needed to get two wireless cards working. Use the newly introduced macro in all places. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: host: tmio: SDIO_STATUS_QUIRK is rather SDIO_STATUS_SETBITSWolfram Sang2017-02-132-5/+3
| | | | | | | | QUIRK sounds like there is something wrong, but actually there are just some bits which need to be 1. Rename it to be more clear. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: host: tmio: refactor calls to sdio irqWolfram Sang2017-02-131-3/+2
| | | | | | | | | | | | tmio_mmc_sdio_irq() is not used as a seperate irq handler anymore, so we can make it similar to the other irq helper functions, namely: * only give the host as argument function which is what it really needs * prefix function name with __ Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: host: tmio: disable clocks when unbindingWolfram Sang2017-02-131-2/+9
| | | | | | | | | | Create a helper function to disable clocks and use it in remove(), too. Now, clk_summary in debugfs reports the clocks as disabled and unprepared after unbinding. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci-msm: Provide enhanced_strobe mode feature supportRitesh Harjani2017-02-131-9/+25
| | | | | | | | | | This provides enhanced_strobe mode feature support in sdhci-msm driver. Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org> Tested-by: Jeremy McNicoll <jeremymc@redhat.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci-msm: Make HS400 tuning follow as per recommeneded HW sequenceRitesh Harjani2017-02-131-2/+14
| | | | | | | | | | | | During tuning execution for HS400 mode, HW sequence recommends to select MCLK_SEL/2(0x3) in VENDOR_SPEC & sdhc msm clock at GCC to be 400MHZ (nearest supported clk). Add this change in tuning sequence during HS400 tuning. Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org> Tested-by: Jeremy McNicoll <jeremymc@redhat.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci: Clear SDHCI_HS400_TUNING flag after platform_execute_tuningRitesh Harjani2017-02-131-2/+4
| | | | | | | | | | Clear SDHCI_HS400_TUNING flag after platform_execute_tuning so that platform_execute_tuning may use it if needed. Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org> Tested-by: Jeremy McNicoll <jeremymc@redhat.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci-msm: configure CORE_CSR_CDC_DELAY_CFG to recommended valueSubhash Jadavani2017-02-131-1/+1
| | | | | | | | | | | | Program CORE_CSR_CDC_DELAY_CFG for hardware recommended 1.25ns delay. We may see data CRC errors if it's programmed for any other delay value. Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org> Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org> Tested-by: Jeremy McNicoll <jeremymc@redhat.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci-msm: Reset vendor specific func register on probeVenkat Gopalakrishnan2017-02-131-11/+4
| | | | | | | | | | | | | The vendor specific func register doesn't get reset when using the software reset register. The various bootloader's could leave this in an unknown state, hence reset this register to it's power on reset value during probe. Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org> Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org> Tested-by: Jeremy McNicoll <jeremymc@redhat.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci-msm: Factor out sdhci_msm_hs400Ritesh Harjani2017-02-131-6/+26
| | | | | | | | | | Factor out sdhci_msm_hs400 used for DLL calibration in HS400 modes. This function will be needed for enhanced_strobe as well. Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org> Tested-by: Jeremy McNicoll <jeremymc@redhat.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci-msm: Factor out function to set/get msm clock rateRitesh Harjani2017-02-131-24/+40
| | | | | | | | | | | Factor out msm_set/get_clock_rate_for_bus_mode for it's later use in changing the tuning sequence for selecting HS400 bus speed mode. Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org> Tested-by: Jeremy McNicoll <jeremymc@redhat.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci-msm: Factor out sdhci_msm_hc_select_modeRitesh Harjani2017-02-131-87/+114
| | | | | | | | | | | | | This factors out sdhci_msm_hc_select_mode to later use it during enhanced_strobe mode select. It also further breaks sdhci_msm_hc_select_mode into separate functions for configuring HS400 mode or other modes. Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org> Tested-by: Jeremy McNicoll <jeremymc@redhat.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: mxs-mmc: Implement CMD23 supportStefan Wahren2017-02-131-4/+12
| | | | | | | | This patch implements support for multiblock transfers bounded by SET_BLOCK_COUNT (CMD23) on the MXS MMC host driver. Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: wbsd: safer check if dma_addr is valid DMA addressAlexey Khoroshilov2017-02-131-2/+5
| | | | | | | | host->dma_addr can store a value that is not returned by the DMA API, so it is safer to check if is a valid DMA address indirectly. Signed-off-by: Alexey Khoroshilov <khoroshilov@ispras.ru> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci-acpi: support deferred probeZhang Rui2017-02-131-1/+4
| | | | | | | | | | | | | | | | | With commit 67bf5156edc4 ("gpio / ACPI: fix returned error from acpi_dev_gpio_irq_get()"), mmc_gpiod_request_cd() returns -EPROBE_DEFER if GPIO is not ready when sdhci-acpi driver is probed, and sdhci-acpi driver should be probed again later in this case. This fixes an order issue when both GPIO and sdhci-acpi drivers are built as modules. CC: stable@vger.kernel.org # v4.9 Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=177101 Tested-by: Jonas Aaberg <cja@gmx.net> Signed-off-by: Zhang Rui <rui.zhang@intel.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: vub300: Don't use mmc_card_present() when validating for inserted cardUlf Hansson2017-02-131-4/+2
| | | | | | | | | | | The mmc_card_present() function helps the mmc core to track an internal state of the card device. More importantly, it's not intended to be used by mmc host drivers to check for an inserted card. Therefore, let's stop using it and instead rely on checking for a valid pointer to a struct mmc_card, as it should be good enough. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
* mmc: omap: Don't use mmc_card_present() when validating for inserted cardUlf Hansson2017-02-131-1/+1
| | | | | | | | | | | | | | | The mmc_card_present() function helps the mmc core to track an internal state of the card device. More importantly, it's not intended to be used by mmc host drivers to check for an inserted card. Therefore, let's stop using it and instead rely on checking for a valid pointer to a struct mmc_card, as it should be good enough. Cc: linux-omap@vger.kernel.org Cc: Tony Lindgren <tony@atomide.com> Cc: Jarkko Nikula <jarkko.nikula@bitmer.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
* mmc: s3cmci: include linux/interrupt.h for tasklet_structArnd Bergmann2017-02-131-0/+1
| | | | | | | | | | | | | | | | I got this new build error on today's linux-next drivers/mmc/host/s3cmci.h:69:24: error: field 'pio_tasklet' has incomplete type struct tasklet_struct pio_tasklet; drivers/mmc/host/s3cmci.c: In function 's3cmci_enable_irq': drivers/mmc/host/s3cmci.c:390:4: error: implicit declaration of function 'enable_irq';did you mean 'enable_imask'? [-Werror=implicit-function-declaration] While I haven't found out why this happened now and not earlier, the solution is obvious, we should include the header that defines the structure. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: tmio: Remove redundant check of mmc->slot.cd_irqUlf Hansson2017-02-131-2/+1
| | | | | | | | | | | | | | To validate whether native hotplug needs to be used, the tmio driver checks whether the mmc->slot.cd_irq has been successfully assigned. This check is redundant at its current place in tmio_mmc_host_probe(), as the mmc core assigns mmc->slot.cd_irq a valid value first when mmc_gpiod_request_cd_irq() is called. Therefore, let's just remove the check for now, as that also removes a layering violation of the tmio driver accessing core specific data via ->slot.cd_irq. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
* mmc: sdhci-of-esdhc: avoid clock glitch when frequency is changingyangbo lu2017-02-132-3/+23
| | | | | | | | | | | | | The eSDHC_PRSSTAT[SDSTB] bit indicates whether the internal card clock is stable. This bit is for the host driver to poll clock status when changing the clock frequency. It is recommended to clear eSDHC_SYSCTL[SDCLKEN] to remove glitch on the card clock when the frequency is changing. This patch is to disable SDCLKEN bit before changing frequency and enable it after SDSTB bit is set. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci-pci: Add support for HS200 tuning mode on AMD, eMMC-4.5.1Shyam Sundar S K2017-02-131-3/+91
| | | | | | | | | | | This patch adds support for HS200 tuning mode on AMD eMMC-4.5.1 Reviewed-by: Sen, Pankaj <Pankaj.Sen@amd.com> Reviewed-by: Shah, Nehal-bakulchandra <Nehal-bakulchandra.Shah@amd.com> Reviewed-by: Agrawal, Nitesh-kumar <Nitesh-kumar.Agrawal@amd.com> Signed-off-by: S-k, Shyam-sundar <Shyam-sundar.S-k@amd.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: vub300: Remove bogus check of irqs_queuedShawn Lin2017-02-131-2/+0
| | | | | | | | It's unnecessary to check the irqs_queued value as it always needs to queue one if irq isn't enabled. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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