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* Merge branch 'irq-core-for-linus' of ↵Linus Torvalds2014-02-053-2/+130
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull irq updates from Thomas Gleixner: "This lot provides: * Bugfixes for armada irq controller * Updates to renesas irq chip * Support for the TI-NSPIRE irq controller Not strictly a bug fix only pull request, but important updates for some of the arm Socs which I completely forgot to send last week. Seems like my obliviousness is getting worse, I just can't remember when it started" * 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: irqchip: Add support for TI-NSPIRE irqchip irqchip: renesas-irqc: Enable mask on suspend irqchip: renesas-irqc: Use lazy disable irqchip: armada-370-xp: fix MSI race condition irqchip: armada-370-xp: fix IPI race condition
| * Merge tag 'mvebu-irqchip-fixes-3.13' of git://git.infradead.org/linux-mvebu ↵Thomas Gleixner2014-01-221-2/+2
| |\ | | | | | | | | | | | | | | | | | | | | | | | | into irq/core mvebu irqchip fixes for v3.13 - armada-370-xp - fix races is MSI and IPI
| | * irqchip: armada-370-xp: fix MSI race conditionLior Amsalem2013-12-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the Armada 370/XP driver, when we receive an IRQ 1, we read the list of doorbells that caused the interrupt from register ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS. This gives the list of MSIs that were generated. However, instead of acknowledging only the MSIs that were generated, we acknowledge *all* the MSIs, by writing ~MSI_DOORBELL_MASK in the ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS register. This creates a race condition: if a new MSI that isn't part of the ones read into the temporary "msimask" variable is fired before we acknowledge all MSIs, then we will simply loose it. It is important to mention that this ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS register has the following behavior: "A CPU write of 0 clears the bits in this field. A CPU write of 1 has no effect". This is what allows us to simply write ~msimask to acknoledge the handled MSIs. Notice that the same problem is present in the IPI implementation, but it is fixed as a separate patch, so that this IPI fix can be pushed to older stable versions as appropriate (all the way to 3.8), while the MSI code only appeared in 3.13. Signed-off-by: Lior Amsalem <alior@marvell.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| | * irqchip: armada-370-xp: fix IPI race conditionLior Amsalem2013-12-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the Armada 370/XP driver, when we receive an IRQ 0, we read the list of doorbells that caused the interrupt from register ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS. This gives the list of IPIs that were generated. However, instead of acknowledging only the IPIs that were generated, we acknowledge *all* the IPIs, by writing ~IPI_DOORBELL_MASK in the ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS register. This creates a race condition: if a new IPI that isn't part of the ones read into the temporary "ipimask" variable is fired before we acknowledge all IPIs, then we will simply loose it. This is causing scheduling hangs on SMP intensive workloads. It is important to mention that this ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS register has the following behavior: "A CPU write of 0 clears the bits in this field. A CPU write of 1 has no effect". This is what allows us to simply write ~ipimask to acknoledge the handled IPIs. Notice that the same problem is present in the MSI implementation, but it will be fixed as a separate patch, so that this IPI fix can be pushed to older stable versions as appropriate (all the way to 3.8), while the MSI code only appeared in 3.13. Signed-off-by: Lior Amsalem <alior@marvell.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: stable@vger.kernel.org # v3.8+ Fixes: 344e873e5657e8dc0 'arm: mvebu: Add IPI support via doorbells' Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * | irqchip: Add support for TI-NSPIRE irqchipDaniel Tang2014-01-222-0/+128
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the interrupt controllers found in some TI-Nspire models. FIQ support was taken out to simplify the driver code and may be added in later. Since Linux on this platform doesn't really use FIQs, this wasn't really that important in the first place. [ tglx: Made zevio_handle_irq static and reordered __init functions ] Signed-off-by: Daniel Tang <dt.tangr@gmail.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Link: http://lkml.kernel.org/r/1386223937-12189-1-git-send-email-dt.tangr@gmail.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
| * | irqchip: renesas-irqc: Enable mask on suspendMagnus Damm2014-01-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now when lazy interrupt disable has been enabled in the driver then extend the code to set IRQCHIP_MASK_ON_SUSPEND which tells the core that only IRQs marked as wakeups need to stay enabled during Suspend-to-RAM. Signed-off-by: Magnus Damm <damm@opensource.se> Cc: rob.herring@calxeda.com Cc: grant.likely@secretlab.ca Cc: horms@verge.net.au Link: http://lkml.kernel.org/r/20131204120556.29642.27021.sendpatchset@w520 Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
| * | irqchip: renesas-irqc: Use lazy disableMagnus Damm2014-01-221-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set the ->irq_enable() and ->irq_disable() methods to NULL to enable lazy disable of interrupts. This by itself provides some level of optimization, but is mainly enabled as ground work for future Suspend-to-RAM wake up support. Signed-off-by: Magnus Damm <damm@opensource.se> Cc: rob.herring@calxeda.com Cc: grant.likely@secretlab.ca Cc: horms@verge.net.au Link: http://lkml.kernel.org/r/20131204120546.29642.15772.sendpatchset@w520 Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* | | Merge tag 'mvebu-fixes-3.13-2' of git://git.infradead.org/linux-mvebu into fixesOlof Johansson2014-01-311-2/+2
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mvebu fixes for v3.13 (incremental #2) - allow building and booting DT and non-DT plat-orion SoCs - catch proper return value for kirkwood_pm_init() - properly check return of of_iomap to solve boot hangs (mirabox, others) - remove a compile warning on Armada 370 with non-SMP. * tag 'mvebu-fixes-3.13-2' of git://git.infradead.org/linux-mvebu: ARM: mvebu: fix compilation warning on Armada 370 (i.e. non-SMP) ARM: mvebu: Fix kernel hang in mvebu_soc_id_init() when of_iomap failed ARM: kirkwood: kirkwood_pm_init() should return void ARM: orion: provide C-style interrupt handler for MULTI_IRQ_HANDLER Signed-off-by: Olof Johansson <olof@lixom.net>
| * | | ARM: mvebu: fix compilation warning on Armada 370 (i.e. non-SMP)Arnaud Ebalard2014-01-211-2/+2
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following appears during compilation for an Armada 370 target because 'irq_controller_lock' is used only when CONFIG_SMP is enabled: drivers/irqchip/irq-armada-370-xp.c:62:8: warning: 'irq_controller_lock' defined but not used [-Wunused-variable] Fix that warning by moving declaration of 'irq_controller_lock' inside existing #ifdef. Signed-off-by: Arnaud Ebalard <arno@natisbad.org> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* | | Merge tag 'xtensa-next-20140123' of git://github.com/czankel/xtensa-linuxLinus Torvalds2014-01-254-0/+278
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull Xtensa patches from Chris Zankel: "The major changes are adding support for SMP for Xtensa, fixing and cleaning up the ISS (simulator) network driver, and better support for device trees" * tag 'xtensa-next-20140123' of git://github.com/czankel/xtensa-linux: (40 commits) xtensa: implement ndelay xtensa: clean up udelay xtensa: enable HAVE_PERF_EVENTS xtensa: remap io area defined in device tree xtensa: support default device tree buses xtensa: initialize device tree clock sources xtensa: xtfpga: fix definitions of platform devices xtensa: standardize devicetree cpu compatible strings xtensa: avoid duplicate of IO range definitions xtensa: fix ATOMCTL register documentation xtensa: Enable irqs after cpu is set online xtensa: ISS: raise network polling rate to 10 times/sec xtensa: remove unused XTENSA_ISS_NETWORK Kconfig parameter xtensa: ISS: avoid simple_strtoul usage xtensa: Switch to sched_clock_register() xtensa: implement CPU hotplug xtensa: add SMP support xtensa: add MX irqchip xtensa: clear timer IRQ unconditionally in its handler xtensa: clean up do_interrupt/do_IRQ ...
| * | | xtensa: add MX irqchipMax Filippov2014-01-143-0/+169
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MX is an interrupt distributor used in some SMP-capable xtensa configurations. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net>
| * | | xtensa: move built-in PIC to drivers/irqchipMax Filippov2014-01-142-0/+109
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | Extract xtensa built-in interrupt controller implementation from xtensa/kernel/irq.c and move it to other irqchips, providing way to instantiate it from the device tree. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net>
* | | Merge tag 'drivers-for-linus' of ↵Linus Torvalds2014-01-233-27/+24
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM driver updates from Olof Johansson: "Updates of SoC-near drivers and other driver updates that makes more sense to take through our tree. The largest part of this is a conversion of device registration for some renesas shmobile/sh devices over to use resources. This has required coordination with the corresponding arch/sh changes, and we've agreed to merge the arch/sh changes through our tree. Added in this branch is support for Trusted Foundations secure firmware, which is what is used on many of the commercial Nvidia Tegra products that are in the market, including the Nvidia Shield. The code is local to arch/arm at this time since it's uncertain whether it will be shared with arm64 longer-term, if needed we will refactor later. A couple of new RTC drivers used on ARM boards, merged through our tree on request by the RTC maintainer. ... plus a bunch of smaller updates across the board, gpio conversions for davinci, etc" * tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (45 commits) watchdog: davinci: rename platform driver to davinci-wdt tty: serial: Limit msm_serial_hs driver to platforms that use it mmc: msm_sdcc: Limit driver to platforms that use it usb: phy: msm: Move mach dependent code to platform data clk: versatile: fixup IM-PD1 clock implementation clk: versatile: pass a name to ICST clock provider ARM: integrator: pass parent IRQ to the SIC irqchip: versatile FPGA: support cascaded interrupts from DT gpio: davinci: don't create irq_domain in case of unbanked irqs gpio: davinci: use chained_irq_enter/chained_irq_exit API gpio: davinci: add OF support gpio: davinci: remove unused variable intc_irq_num gpio: davinci: convert to use irqdomain support. gpio: introduce GPIO_DAVINCI kconfig option gpio: davinci: get rid of DAVINCI_N_GPIO gpio: davinci: use {readl|writel}_relaxed() instead of __raw_* serial: sh-sci: Add OF support serial: sh-sci: Add device tree bindings documentation serial: sh-sci: Remove platform data mapbase and irqs fields serial: sh-sci: Remove platform data scbrr_algo_id field ...
| * \ \ Merge tag 'integrator-for-v3.14' of ↵Olof Johansson2014-01-031-2/+13
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into next/drivers From Linus Walleij: Some Integrator patches that matured for v3.14: - Use PATCH_PHYS_TO_VIRT and AUTO_ZRELADDR. - Support cascaded interrupts on the SIC. - Complete clock implementation for the IM-PD1. * tag 'integrator-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator: clk: versatile: fixup IM-PD1 clock implementation clk: versatile: pass a name to ICST clock provider ARM: integrator: pass parent IRQ to the SIC irqchip: versatile FPGA: support cascaded interrupts from DT ARM: integrator: Default enable ARM_PATCH_PHYS_VIRT, AUTO_ZRELADDR Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | | irqchip: versatile FPGA: support cascaded interrupts from DTLinus Walleij2014-01-031-2/+13
| | | |/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Versatile FPGA interrupt controller supports cascading interrupts, i.e. that its output is connected to the input of another interrupt controller. This makes it possible to pass a parent interrupt from the device tree and print it in the boot log if applicable. Acked-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | Merge tag 'davinci-for-v3.14/gpio' of ↵Olof Johansson2014-01-021-4/+5
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/drivers From Sekhar Nori: DaVinci GPIO driver updates --------------------------- This pull request contains updates to DaVinci GPIO driver and the resultant platform code changes. The updates include DT-conversion and changes to make the driver cross-platform ready. * tag 'davinci-for-v3.14/gpio' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci: gpio: davinci: don't create irq_domain in case of unbanked irqs gpio: davinci: use chained_irq_enter/chained_irq_exit API gpio: davinci: add OF support gpio: davinci: remove unused variable intc_irq_num gpio: davinci: convert to use irqdomain support. gpio: introduce GPIO_DAVINCI kconfig option gpio: davinci: get rid of DAVINCI_N_GPIO gpio: davinci: use {readl|writel}_relaxed() instead of __raw_* Signed-off-by: Olof Johansson <olof@lixom.net>
| * \ \ \ Merge tag 'renesas-irqc-for-v3.14' of ↵Olof Johansson2013-12-291-13/+8
| |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/drivers From Simon Horman: Renesas ARM based SoC IRQC Driver Updates for v3.14 * Simplify irq_set_type() method * Enable mask on suspend * Use lazy disable * tag 'renesas-irqc-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: irq-renesas-irqc: simplify irq_set_type() method irqchip: renesas-irqc: Enable mask on suspend irqchip: renesas-irqc: Use lazy disable Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | | | irq-renesas-irqc: simplify irq_set_type() methodSergei Shtylyov2013-12-231-10/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Value 0 of the sense selection field of CONFIG_n register means "disable event detection" and serves in irqc_sense[] for marking the invalid values of the IRQ type (by just omitting initializers). There is no need for INTC_IRQ_SENSE_VALID and hence INTC_IRQ_SENSE() as all field values matching to the valid IRQ types are non-zero anyway. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| | * | | | irqchip: renesas-irqc: Enable mask on suspendMagnus Damm2013-12-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now when lazy interrupt disable has been enabled in the driver then extend the code to set IRQCHIP_MASK_ON_SUSPEND which tells the core that only IRQs marked as wakeups need to stay enabled during Suspend-to-RAM. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| | * | | | irqchip: renesas-irqc: Use lazy disableMagnus Damm2013-12-121-2/+0
| | | |/ / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set the ->irq_enable() and ->irq_disable() methods to NULL to enable lazy disable of interrupts. This by itself provides some level of optimization, but is mainly enabled as ground work for future Suspend-to-RAM wake up support. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | | | irqchip: exynos-combiner: remove hard-coded irq_base valueChander Kashyap2013-12-021-12/+3
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace irq_domain_add_simple with "irq_domain_add_linear" in order to use linear irq domain, and to remove hardcoded irq_base_value. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* | | | Merge tag 'soc-for-linus' of ↵Linus Torvalds2014-01-233-0/+155
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC platform changes from Olof Johansson: "New core SoC-specific changes. New platforms: * Introduction of a vendor, Hisilicon, and one of their SoCs with some random numerical product name. * Introduction of EFM32, embedded platform from Silicon Labs (ARMv7m, i.e. !MMU). * Marvell Berlin series of SoCs, which include the one in Chromecast. * MOXA platform support, ARM9-based platform used mostly in industrial products * Support for Freescale's i.MX50 SoC. Other work: * Renesas work for new platforms and drivers, and conversion over to more multiplatform-friendly device registration schemes. * SMP support for Allwinner sunxi platforms. * ... plus a bunch of other stuff across various platforms" * tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (201 commits) ARM: tegra: fix tegra_powergate_sequence_power_up() inline ARM: msm_defconfig: Update for multi-platform ARM: msm: Move MSM's DT based hardware to multi-platform support ARM: msm: Only build timer.c if required ARM: msm: Only build clock.c on proc_comm based platforms ARM: ux500: Enable system suspend with WFI support ARM: ux500: turn on PRINTK_TIME in u8500_defconfig ARM: shmobile: r8a7790: Fix I2C controller names ARM: msm: Simplify ARCH_MSM_DT config ARM: msm: Add support for MSM8974 SoC ARM: sunxi: select ARM_PSCI MAINTAINERS: Update Allwinner sunXi maintainer files ARM: sunxi: Select RESET_CONTROLLER ARM: imx: improve the comment of CCM lpm SW workaround ARM: imx: improve status check of clock gate ARM: imx: add necessary interface for pfd ARM: imx_v6_v7_defconfig: Select CONFIG_REGULATOR_PFUZE100 ARM: imx_v6_v7_defconfig: Select MX35 and MX50 device tree support ARM: imx: Add cpu frequency scaling support ARM i.MX35: Add devicetree support. ...
| * \ \ \ Merge branch 'efm32/soc' into next/socKevin Hilman2013-12-201-4/+5
| |\ \ \ \ | | | |/ / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From Uwe Kleine-König: * efm32/soc: (1003 commits) ARM: device trees for Energy Micro's EFM32 Cortex-M3 SoCs ARM: new platform for Energy Micro's EFM32 Cortex-M3 SoCs +Linux 3.13-rc4 Signed-off-by: Kevin Hilman <khilman@linaro.org>
| * | | | irqchip: add DesignWare APB ICTL interrupt controllerSebastian Hesselbarth2013-12-133-0/+155
| | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds an irqchip driver and corresponding devicetree binding for the secondary interrupt controllers based on Synopsys DesignWare IP dw_apb_ictl. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Jisheng Zhang <jszhang@marvell.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
* | | | Merge tag 'omap-for-v3.14/fixes-not-urgent-signed' of ↵Kevin Hilman2014-01-141-3/+5
|\ \ \ \ | | |_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/fixes-non-critical From Tony Lindgren: Some non-urgent fixes to enable am335x features, update documentation, and to remove unnecessary double initialization for the GPMC code. * tag 'omap-for-v3.14/fixes-not-urgent-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (238 commits) ARM: OMAP2+: gpmc: Move legacy GPMC width setting ARM: OMAP2+: gpmc: Introduce gpmc_set_legacy() ARM: OMAP2+: gpmc: Move initialization outside the gpmc_t condition ARM: OMAP2+: board-generic: update SoC compatibility strings Documentation: dt: OMAP: explicitly state SoC compatible strings ARM: OMAP2+: enable AM33xx SOC EVM audio ARM: OMAP2+: Select USB PHY for AM335x SoC +Linux 3.13-rc5
| * | | Merge tag 'renesas-fixes-for-v3.13' of ↵Kevin Hilman2013-12-201-3/+5
| |\ \ \ | | |_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into fixes From Simon Horman: Renesas ARM based SoC fixes for v3.13 * r8a7790 (R-Car H1) SoC - Correct GPIO resources in DT. This problem has been present since GPIOs were added to the r8a7790 SoC by f98e10c88aa95bf7 ("ARM: shmobile: r8a7790: Add GPIO controller devices to device tree") in v3.12-rc1. * irqchip renesas-intc-irqpin - Correct register bitfield shift calculation This bug has been present since the renesas-intc-irqpin driver was introduced by 443580486e3b9657 ("irqchip: Renesas INTC External IRQ pin driver") in v3.10-rc1 * Lager board - Do not build the phy fixup unless CONFIG_PHYLIB is enabled This problem was introduced by 48c8b96f21817aad * tag 'renesas-fixes-for-v3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: r8a7790: Fix GPIO resources in DTS irqchip: renesas-intc-irqpin: Fix register bitfield shift calculation ARM: shmobile: lager: phy fixup needs CONFIG_PHYLIB Signed-off-by: Kevin Hilman <khilman@linaro.org>
| | * | irqchip: renesas-intc-irqpin: Fix register bitfield shift calculationLaurent Pinchart2013-11-241-3/+5
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SENSE register bitfield position is incorrectly computed for SoCs that use 2-bit IRQ sense fields. Fix it. This has been tested on the Marzen (H1) and Bockw (M1) boards. This bug has been present since the renesas-intc-irqpin driver was introduced by 443580486e3b9657 ("irqchip: Renesas INTC External IRQ pin driver") in v3.10-rc1. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Magnus Damm <damm@opensource.se> Tested-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | | irqchip: sirf: set IRQ_LEVEL status_flagsBarry Song2014-01-081-1/+2
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SiRF internal interrupts are using level trigger. we need to tell the irq core this information. otherwise, we might get some problems as below 1. disable_irq(n) here irq core will mark the disabled flag but still keep the irq enabled due to involved lazy-disable 2. doing someting after disable_irq(n) in step 2, if one interrupt n comes, irq core will mark it as pending and mask the HW interrupt really. we name the coming interrupt as "X". 3. enable_irq(n) this will unmask the interrupt, so the level-trigger HW interrupt will come again, irq_handler will enter as "E1". after that, irq core will also check whether irq n is pending, if yes, and pending interrupt is not level-trigger, irq core will execute the pending irq_handler. so if we don't set the IRQ_LEVEL flag here, irq core will execute pending X again as "E2", but actually the pending interrupt has been handled by "E1". that makes a level-trigger HW interrupt is executed twice. here we fix the issue to avoid redundant interrupt overload. Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Huayi Li <Huayi.Li@csr.com> Signed-off-by: Olof Johansson <olof@lixom.net>
* | Merge branch 'irq-urgent-for-linus' of ↵Linus Torvalds2013-12-021-4/+5
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull irq fixes from Thomas Gleixner: - Correction of fuzzy and fragile IRQ_RETVAL macro - IRQ related resume fix affecting only XEN - ARM/GIC fix for chained GIC controllers * 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: irqchip: Gic: fix boot for chained gics irq: Enable all irqs unconditionally in irq_resume genirq: Correct fuzzy and fragile IRQ_RETVAL() definition
| * irqchip: Gic: fix boot for chained gicsMark Rutland2013-11-281-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As of c0114709ed: "irqchip: gic: Perform the gic_secondary_init() call via CPU notifier", booting on a platform with chained gics (e.g. Realview EB ARM11MPCore) will result in the gic_cpu_notifier being registered twice, corrupting the cpu notifier list and rendering the platform unbootable. This patch ensures that we only register the notifier for the first gic, allowing platforms with chained gics to boot. At the same time we limit the pointlessly duplicated calls to set_smp_cross_call and set_handle_irq to the first gic registered. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: marc.zyngier@arm.com Cc: rob.herring@calxeda.com Cc: olof@lixom.net Link: http://lkml.kernel.org/r/1385648500-29048-1-git-send-email-mark.rutland@arm.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* | Merge branch 'for-linus' of git://git.linaro.org/people/rmk/linux-armLinus Torvalds2013-11-141-3/+148
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull ARM updates from Russell King: "Included in this series are: 1. BE8 (modern big endian) changes for ARM from Ben Dooks 2. big.Little support from Nicolas Pitre and Dave Martin 3. support for LPAE systems with all system memory above 4GB 4. Perf updates from Will Deacon 5. Additional prefetching and other performance improvements from Will. 6. Neon-optimised AES implementation fro Ard. 7. A number of smaller fixes scattered around the place. There is a rather horrid merge conflict in tools/perf - I was never notified of the conflict because it originally occurred between Will's tree and other stuff. Consequently I have a resolution which Will forwarded me, which I'll forward on immediately after sending this mail. The other notable thing is I'm expecting some build breakage in the crypto stuff on ARM only with Ard's AES patches. These were merged into a stable git branch which others had already pulled, so there's little I can do about this. The problem is caused because these patches have a dependency on some code in the crypto git tree - I tried requesting a branch I can pull to resolve these, and all I got each time from the crypto people was "we'll revert our patches then" which would only make things worse since I still don't have the dependent patches. I've no idea what's going on there or how to resolve that, and since I can't split these patches from the rest of this pull request, I'm rather stuck with pushing this as-is or reverting Ard's patches. Since it should "come out in the wash" I've left them in - the only build problems they seem to cause at the moment are with randconfigs, and since it's a new feature anyway. However, if by -rc1 the dependencies aren't in, I think it'd be best to revert Ard's patches" I resolved the perf conflict roughly as per the patch sent by Russell, but there may be some differences. Any errors are likely mine. Let's see how the crypto issues work out.. * 'for-linus' of git://git.linaro.org/people/rmk/linux-arm: (110 commits) ARM: 7868/1: arm/arm64: remove atomic_clear_mask() in "include/asm/atomic.h" ARM: 7867/1: include: asm: use 'int' instead of 'unsigned long' for 'oldval' in atomic_cmpxchg(). ARM: 7866/1: include: asm: use 'long long' instead of 'u64' within atomic.h ARM: 7871/1: amba: Extend number of IRQS ARM: 7887/1: Don't smp_cross_call() on UP devices in arch_irq_work_raise() ARM: 7872/1: Support arch_irq_work_raise() via self IPIs ARM: 7880/1: Clear the IT state independent of the Thumb-2 mode ARM: 7878/1: nommu: Implement dummy early_paging_init() ARM: 7876/1: clear Thumb-2 IT state on exception handling ARM: 7874/2: bL_switcher: Remove cpu_hotplug_driver_{lock,unlock}() ARM: footbridge: fix build warnings for netwinder ARM: 7873/1: vfp: clear vfp_current_hw_state for dying cpu ARM: fix misplaced arch_virt_to_idmap() ARM: 7848/1: mcpm: Implement cpu_kill() to synchronise on powerdown ARM: 7847/1: mcpm: Factor out logical-to-physical CPU translation ARM: 7869/1: remove unused XSCALE_PMU Kconfig param ARM: 7864/1: Handle 64-bit memory in case of 32-bit phys_addr_t ARM: 7863/1: Let arm_add_memory() always use 64-bit arguments ARM: 7862/1: pcpu: replace __get_cpu_var_uses ARM: 7861/1: cacheflush: consolidate single-CPU ARMv7 cache disabling code ...
| * ARM: GIC: interface to send a SGI directlyNicolas Pitre2013-09-231-0/+14
| | | | | | | | | | | | | | | | | | The regular gic_raise_softirq() takes as input a CPU mask which is not adequate when we need to send an IPI to a CPU which is not represented in the kernel to GIC mapping. That is the case with the b.L switcher when GIC migration to the inbound CPU has not yet occurred. Signed-off-by: Nicolas Pitre <nico@linaro.org>
| * ARM: GIC: function to retrieve the physical address of the SGIRNicolas Pitre2013-09-231-0/+29
| | | | | | | | | | | | | | | | | | | | In order to have early assembly code signal other CPUs in the system, we need to get the physical address for the SGIR register used to send IPIs. Because the register will be used with a precomputed CPU interface ID number, there is no need for any locking in the assembly code where this register is written to. Signed-off-by: Nicolas Pitre <nico@linaro.org>
| * Merge branch 'iks_for_rmk' of git://git.linaro.org/people/nico/linux into ↵Russell King2013-09-171-3/+105
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | devel-stable Nicolas Pitre writes: This is the first part of the patch series adding IKS (In-Kernel Switcher) support for big.LITTLE system architectures. This consists of the core patches only. Extra patches to come later will introduce various optimizations and tracing support. Those patches were posted on the list a while ago here: http://news.gmane.org/group/gmane.linux.ports.arm.kernel/thread=253942
| | * ARM: bL_switcher: do not hardcode GIC IDs in the codeNicolas Pitre2013-07-301-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, GIC IDs are hardcoded making the code dependent on the 4+4 b.L configuration. Let's allow for GIC IDs to be discovered upon switcher initialization to support other b.L configurations such as the 1+1 one, or 2+3 as on the VExpress TC2. Signed-off-by: Nicolas Pitre <nico@linaro.org>
| | * ARM: gic: add CPU migration supportNicolas Pitre2013-07-301-3/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is required by the big.LITTLE switcher code. The gic_migrate_target() changes the CPU interface mapping for the current CPU to redirect SGIs to the specified interface, and it also updates the target CPU for each interrupts to that CPU interface if they were targeting the current interface. Finally, pending SGIs for the current CPU are forwarded to the new interface. Because Linux does not use it, the SGI source information for the forwarded SGIs is not preserved. Neither is the source information for the SGIs sent by the current CPU to other CPUs adjusted to match the new CPU interface mapping. The required registers are banked so only the target CPU could do it. Signed-off-by: Nicolas Pitre <nico@linaro.org>
* | | Merge branch 'irq-core-for-linus' of ↵Linus Torvalds2013-11-121-12/+10
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull IRQ changes from Ingo Molnar: "The biggest change this cycle are the softirq/hardirq stack interaction and nesting fixes, cleanups and reorganizations from Frederic. This is the longer followup story to the softirq nesting fix that is already upstream (commit ded797547548: "irq: Force hardirq exit's softirq processing on its own stack")" * 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: irqchip: bcm2835: Convert to use IRQCHIP_DECLARE macro powerpc: Tell about irq stack coverage x86: Tell about irq stack coverage irq: Optimize softirq stack selection in irq exit irq: Justify the various softirq stack choices irq: Improve a bit softirq debugging irq: Optimize call to softirq on hardirq exit irq: Consolidate do_softirq() arch overriden implementations x86/irq: Correct comment about i8259 initialization
| * | | irqchip: bcm2835: Convert to use IRQCHIP_DECLARE macroAxel Lin2013-11-071-12/+10
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch converts irq-bcm2835 driver to use the new IRQCHIP_DECLARE and irqchip_init. Signed-off-by: Axel Lin <axel.lin@ingics.com> Tested-by: Stephen Warren <swarren@wwwdotorg.org> Cc: Simon Arlott <simon@fire.lp0.eu> Cc: Olof Johansson <olof@lixom.net> Cc: Arnd Bergmann <arnd@arndb.de> Cc: linux-rpi-kernel@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* | | Merge tag 'dt-for-linus' of ↵Linus Torvalds2013-11-111-1/+6
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC DT updates from Olof Johansson: "Most of this branch consists of updates, additions and general churn of the device tree source files in the kernel (arch/arm/boot/dts). Besides that, there are a few things to point out: - Lots of platform conversion on OMAP2+, with removal of old board files for various platforms. - Final conversion of a bunch of ux500 (ST-Ericsson) platforms as well - Some updates to pinctrl and other subsystems. Most of these are for DT-enablement of the various platforms and acks have been collected" * tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (385 commits) ARM: dts: bcm11351: Use GIC/IRQ defines for sdio interrupts ARM: dts: bcm: Add missing UARTs for bcm11351 (bcm281xx) ARM: dts: bcm281xx: Add card detect GPIO ARM: dts: rename ARCH_BCM to ARCH_BCM_MOBILE (dt) ARM: bcm281xx: Add device node for the GPIO controller ARM: mvebu: Add Netgear ReadyNAS 104 board ARM: tegra: fix Tegra114 IOMMU register address ARM: kirkwood: add support for OpenBlocks A7 platform ARM: dts: omap4-panda: add DPI pinmuxing ARM: dts: AM33xx: Add RNG node ARM: dts: AM33XX: Add hwspinlock node ARM: dts: OMAP5: Add hwspinlock node ARM: dts: OMAP4: Add hwspinlock node ARM: dts: use 'status' property for PCIe nodes ARM: dts: sirf: add missed address-cells and size-cells for prima2 I2C ARM: dts: sirf: add missed cell, cs and dma channel for SPI nodes ARM: dts: sirf: add missed graphics2d iobg in atlas6 dts ARM: dts: sirf: add missed chhifbg node in prima2 and atlas6 dts ARM: dts: sirf: add missed memcontrol-monitor node in prima2 and atlas6 dts ARM: mvebu: Add the core-divider clock to Armada 370/XP ...
| * | | irqchip: vic: Parse interrupt and resume masks from device treeTomasz Figa2013-09-171-1/+6
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch extends vic_of_init to parse valid interrupt sources and resume sources masks from device tree. If mask values are not specified in device tree, all sources are assumed to be valid, as before this patch. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* | | irqchip: armada-370-xp: implement MSI supportThomas Petazzoni2013-09-301-1/+181
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit introduces the support for the MSI interrupts in the armada-370-xp interrupt controller driver. It registers an MSI chip to the MSI chip registry, which will be used by the Marvell PCIe host controller driver. The MSI interrupts use the 16 high doorbells, and are therefore notified using IRQ1 of the main interrupt controller. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* | | irqchip: armada-370-xp: properly request resourcesThomas Petazzoni2013-09-301-4/+16
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of using of_iomap(), we now use of_address_to_resource(), request_mem_region() and ioremap(). This allows the corresponding I/O regions to be properly requested and visible in /proc/iomem. The main motivation for this change is that the introduction of the MSI support requires us to get the physical address of the main interrupt controller registers, so we will need the corresponding 'struct resource' anyway. We also take this opportunity to change a panic() to BUG_ON(), in order to be consistent with the rest of the driver. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Daniel Price <daniel.price@gmail.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* | Merge tag 'late-for-linus' of ↵Linus Torvalds2013-09-092-0/+496
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC late changes from Kevin Hilman: "These are changes that arrived a little late before the merge window, or had dependencies on previous branches. Highlights: - ux500: misc. cleanup, fixup I2C devices - exynos: DT updates for RTC; PM updates - at91: DT updates for NAND; new platforms added to generic defconfig - sunxi: DT updates: cubieboard2, pinctrl driver, gated clocks - highbank: LPAE fixes, select necessary ARM errata - omap: PM fixes and improvements; OMAP5 mailbox support - omap: basic support for new DRA7xx SoCs" * tag 'late-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (60 commits) ARM: dts: vexpress: Add CCI node to TC2 device-tree ARM: EXYNOS: Skip C1 cpuidle state for exynos5440 ARM: EXYNOS: always enable PM domains support for EXYNOS4X12 ARM: highbank: clean-up some unused includes ARM: sun7i: Enable the A20 clocks in the DTSI ARM: sun6i: Enable clock support in the DTSI ARM: sun5i: dt: Use the A10s gates in the DTSI ARM: at91: at91_dt_defconfig: enable rm9200 support ARM: dts: add ADC device tree node for exynos5420/5250 ARM: dts: Add RTC DT node to Exynos5420 SoC ARM: dts: Update the "status" property of RTC DT node for Exynos5250 SoC ARM: dts: Fix the RTC DT node name for Exynos5250 irqchip: mmp: avoid to include irqs head file ARM: mmp: avoid to include head file in mach-mmp irqchip: mmp: support irqchip irqchip: move mmp irq driver ARM: OMAP: AM33xx: clock: Add RNG clock data ARM: OMAP: TI81XX: add always-on powerdomain for TI81XX ARM: OMAP4: clock: Lock PLLs in the right sequence ARM: OMAP: AM33XX: hwmod: Add hwmod data for debugSS ...
| * \ Merge tag 'mmp-irq' of ↵Olof Johansson2013-08-292-0/+496
| |\ \ | | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/hzhuang1/linux into late/all From Haojian Zhuang: Move irq driver out of mach-mmp to support multiplatform * tag 'mmp-irq' of git://git.kernel.org/pub/scm/linux/kernel/git/hzhuang1/linux: irqchip: mmp: avoid to include irqs head file ARM: mmp: avoid to include head file in mach-mmp irqchip: mmp: support irqchip irqchip: move mmp irq driver
| | * irqchip: mmp: avoid to include irqs head fileHaojian Zhuang2013-08-241-24/+21
| | | | | | | | | | | | | | | | | | | | | Since <mach/irqs.h> in irq-mmp.c blocks the multiplatform build, remove it instead. Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
| | * ARM: mmp: avoid to include head file in mach-mmpHaojian Zhuang2013-08-241-14/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | pxa910_set_wake() & mmp2_set_wake() are both declared in head files of arch/arm/mach-mmp/include/mach directory. If we include these head files in irq-mmp driver, it blocks the multiplatform build. So adjust the code. Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
| | * irqchip: mmp: support irqchipHaojian Zhuang2013-08-241-115/+165
| | | | | | | | | | | | | | | | | | | | | Support IRQCHIP & CONFIG_MULTI_IRQ_HANDLER in irq-mmp driver. Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com> Reviewed-by: Daniel Drake <dsd@laptop.org>
| | * irqchip: move mmp irq driverHaojian Zhuang2013-08-242-0/+462
| | | | | | | | | | | | | | | | | | | | | Move irq-mmp driver from mach-mmp directory into irqchip directory. It's used to support multiple platform. Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
* | | Merge tag 'drivers-for-linus' of ↵Linus Torvalds2013-09-091-0/+6
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver update from Kevin Hilman: "This contains the ARM SoC related driver updates for v3.12. The only thing this cycle are core PM updates and CPUidle support for ARM's TC2 big.LITTLE development platform" * tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: cpuidle: big.LITTLE: vexpress-TC2 CPU idle driver ARM: vexpress: tc2: disable GIC CPU IF in tc2_pm_suspend drivers: irq-chip: irq-gic: introduce gic_cpu_if_down()
| * | | drivers: irq-chip: irq-gic: introduce gic_cpu_if_down()Nicolas Pitre2013-08-281-0/+6
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When processors are about to hit low power states, the assertion of standbywfi signal, triggered by the wfi instruction, is essential to entering low power modes. If an IRQ is pending on the processor at the time wfi is issued, the wfi instruction completes and the processor restarts execution without asserting the standbywfi signal. Depending on the platform power controller HW this behaviour can be acceptable or not; if this behaviour must be prevented software should be provided with a way to disable the routing of interrupts to the core IRQ pins. On systems where raw GIC distributor interrupts are connected to the power controller as wake-up events (hence the power controller still senses IRQs and can wake up cores upon IRQ pending), the GIC CPU interface can be disabled on power down, so that the GIC CPU IF output is gated and wfi cannot complete, thereby preventing the standbywfi issue. This patch adds a simple function to the GIC driver that allows to disable the GIC CPU IF from power down procedures. Signed-off-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> [rewrote commit log] Signed-off-by: Olof Johansson <olof@lixom.net>
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