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path: root/drivers/irqchip/irq-dw-apb-ictl.c
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* irqchip: dw-apb-ictl: Add PM supportJisheng Zhang2014-11-261-0/+19
| | | | | | | | | | | | This patch adds in support for S2R for dw-apb-ictl irqchip driver. We can used relaxed variants in the resume hook because there's no DMA at all here, the device type memory attribute can ensure the operations order and relaxed version imply compiler barrier. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Link: https://lkml.kernel.org/r/1415773374-4629-4-git-send-email-jszhang@marvell.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* irqchip: dw-apb-ictl: Enable IRQ_GC_MASK_CACHE_PER_TYPEJisheng Zhang2014-11-261-0/+1
| | | | | | | | | | The irq_chip_type instances have separate mask registers, so we need to enable IRQ_GC_MASK_CACHE_PER_TYPE to actually handle separate mask registers. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Link: https://lkml.kernel.org/r/1415773374-4629-3-git-send-email-jszhang@marvell.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* irqchip: dw-apb-ictl: Always use use {readl|writel}_relaxedJisheng Zhang2014-11-261-6/+6
| | | | | | | | | | | There's no DMA at all, the device type memory attribute can ensure the operations order and relaxed version imply compiler barrier, so we are safe to use relaxed version to improve the performance a bit. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Link: https://lkml.kernel.org/r/1415773374-4629-2-git-send-email-jszhang@marvell.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* irqchip: add DesignWare APB ICTL interrupt controllerSebastian Hesselbarth2013-12-131-0/+150
This adds an irqchip driver and corresponding devicetree binding for the secondary interrupt controllers based on Synopsys DesignWare IP dw_apb_ictl. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Jisheng Zhang <jszhang@marvell.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
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