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* i2c: mt65xx: add 4GB DMA mode support in i2c driverLiguo Zhang2016-02-121-0/+42
| | | | | | | | | | | If 4GB mode is enabled, we should add 4GB DMA mode support in i2c driver. Set 4GB mode register to support 4GB mode. Signed-off-by: Liguo Zhang <liguo.zhang@mediatek.com> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-by: Yingjoe Chen <yingjoe.chen@mediatek.com> [wsa: updated commit message] Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
* i2c: mediatek: fix i2c multi transfer issue in high speed modeLiguo Zhang2016-01-031-2/+19
| | | | | | | | | | For mt8173 platform with auto restart support, when doing i2c multi transfer in high speed, we should ignore the first restart irq after the master code, otherwise the first transfer will be discarded. Signed-off-by: Liguo Zhang <liguo.zhang@mediatek.com> Reviewed-by: Eddie Huang <eddie.huang@mediatek.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
* i2c: mediatek: add i2c first write then read optimizationLiguo Zhang2015-12-011-6/+27
| | | | | | | | | | | | For platform with auto restart support, between every transfer, i2c controller will trigger an interrupt and SW need to handle it to start new transfer. When doing write-then-read transfer, instead of restart mechanism, using WRRD mode to have controller send both transfer in one request to reduce latency. Signed-off-by: Liguo Zhang <liguo.zhang@mediatek.com> Reviewed-by: Eddie Huang <eddie.huang@mediatek.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
* i2c: mediatek: add i2c resume supportLiguo Zhang2015-10-231-0/+16
| | | | | | | | | mt65xx i2c controller initial setting will be cleared after system suspend, so we should init mt65xx i2c controller again when system resume. Signed-off-by: Liguo Zhang <liguo.zhang@mediatek.com> Signed-off-by: Eddie Huang <eddie.huang@mediatek.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
* i2c: mediatek: Fixup i2c ack error interrupt handlingEddie Huang2015-08-111-4/+11
| | | | | | | | | | | | When occur i2c ack error, i2c controller generate two interrupts, first is the ack error interrupt, then the complete interrupt. i2c interrupt handler should keep the two interrupt value, and only call complete() for the complete interrupt. Signed-off-by: Liguo Zhang <liguo.zhang@mediatek.com> Signed-off-by: Eddie Huang <eddie.huang@mediatek.com> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
* i2c: mediatek: Reset DMA engine in hardware init functionEddie Huang2015-08-111-0/+6
| | | | | | | | | | Reset DMA in hardware init function to avoid unknown hardware state before do any I2C operation. Signed-off-by: Liguo Zhang <liguo.zhang@mediatek.com> Signed-off-by: Eddie Huang <eddie.huang@mediatek.com> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
* I2C: mediatek: Add driver for MediaTek MT8173 I2C controllerEddie Huang2015-06-011-29/+74
| | | | | | | | | | | | Add mediatek MT8173 I2C controller driver. Compare to I2C controller of earlier mediatek SoC, MT8173 fix write-then-read limitation, and also increase message size to 64kb. Signed-off-by: Xudong Chen <xudong.chen@mediatek.com> Signed-off-by: Liguo Zhang <liguo.zhang@mediatek.com> Signed-off-by: Eddie Huang <eddie.huang@mediatek.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
* I2C: mediatek: Add driver for MediaTek I2C controllerXudong Chen2015-06-011-0/+686
The mediatek SoCs have I2C controller that handle I2C transfer. This patch include common I2C bus driver. This driver is compatible with I2C controller on mt65xx/mt81xx. Signed-off-by: Xudong Chen <xudong.chen@mediatek.com> Signed-off-by: Liguo Zhang <liguo.zhang@mediatek.com> Signed-off-by: Eddie Huang <eddie.huang@mediatek.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
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