| Commit message (Collapse) | Author | Age | Files | Lines |
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git://people.freedesktop.org/~airlied/linux
Pull nouveau destaging + Kelper modesetting support from Dave Airlie:
"This pull request is unexpected and not something I had mentioned
previously.
So NVIDIA announced new Kepler GPUs this morning, and Ben has killed
himself getting modesetting support for them together to have on
launch day. Most of the code to support the new chips has already
gone in, however this pull contains a few more pieces along with the
final enables so the driver binds to the new Kepler cards. Its quite
amazing that nouveau can support a GPU on its launch day even if its
just unaccelerated modesetting, and I'd like to have support in the
next kernel.
In order to sweeten the deal, Ben has also requested nouveau destage
and become ABI stable, the only change is the version number bump
which he prepared userspace for quite a long time ago. The driver
hasn't broken ABI since that one big break that caused a lot of fuss.
It's also quite a small set of code, and not likely to break anything."
* 'drm-nouveau-destage' of git://people.freedesktop.org/~airlied/linux:
drm/nouveau/dp: support version 4.0 of DP table
drm/nve0/disp: nvidia randomly decided to move the dithering method
drm/nve0: initial modesetting support for kepler chipsets
drm/nouveau: add bios connector type for dms59
drm/nouveau: move out of staging drivers
drm/nouveau: bump version to 1.0.0
drm/nvd0/disp: ignore clock set if no pclk
drm/nouveau: oops, increase channel dispc_vma to 4
drm/nouveau: inform userspace of new kernel subchannel requirements
drm/nouveau: remove m2mf creation on userspace channels
drm/nvc0-/disp: reimplement flip completion method as fifo method
drm/nouveau: move fence sequence check to start of loop
drm/nouveau: remove subchannel names from places where it doesn't matter
drm/nouveau/ttm: always do buffer moves on kernel channel
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git://git.freedesktop.org/git/nouveau/linux-2.6 into drm-next
* 'drm-nouveau-next' of git://git.freedesktop.org/git/nouveau/linux-2.6:
drm/nouveau/dp: support version 4.0 of DP table
drm/nve0/disp: nvidia randomly decided to move the dithering method
drm/nve0: initial modesetting support for kepler chipsets
drm/nouveau: add bios connector type for dms59
drm/nouveau: move out of staging drivers
drm/nouveau: bump version to 1.0.0
drm/nvd0/disp: ignore clock set if no pclk
drm/nouveau: oops, increase channel dispc_vma to 4
drm/nouveau: inform userspace of new kernel subchannel requirements
drm/nouveau: remove m2mf creation on userspace channels
drm/nvc0-/disp: reimplement flip completion method as fifo method
drm/nouveau: move fence sequence check to start of loop
drm/nouveau: remove subchannel names from places where it doesn't matter
drm/nouveau/ttm: always do buffer moves on kernel channel
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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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There's really no good reason for us to be in here anymore, we have to
maintain this ABI anyway to avoid angering people.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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The time has come to get a proper version number that we can change to
indicate new features etc, rather than the lock-step 0.0.XX that we
previously had.
libdrm has recognised this version as compatible with 0.0.16 since 2.4.22,
so hopefully any breakage people see should be very minimal.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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This happens somehow during init on a machine I have, and leads to a
divide-by-zero.
Lets avoid that...
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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All available subchannels are now available for userspace to do with as it
pleases on NVC0+.
On all earlier chipsets, the kernel still uses a software object on subc 0
to implement the page flip completion method. I hope to find some decent
way of addressing this too, but it's a tad tricker prior to fermi.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Removes need for M2MF subchannel usage on NVC0+.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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I want to be able to use REF_CNT from other places in the kernel without
pushing a fence object onto the list of emitted fences.
The current code makes an assumption that every time the acked sequence is
bumped that there's at least one fence on the list that'll be signalled.
This will no longer be true in the near future.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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These are FIFO methods, it doesn't matter what subchannel is being used.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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There was once good reasons for wanting the drm to be able to use M2MF etc
on user channels, but they're not relevant anymore. For the general
buffer move case, we've already lost by transferring between vram/sysmem
already so the context switching overhead is minimal in comparison.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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git://people.freedesktop.org/~airlied/linux
Pull radeon southern islands / trinity support from Dave Airlie:
"This is support from AMD for their newest GPU and APUs. The products
called RadeonHD 7xxx, and the Trinity APU series.
This did come in a bit late, due to some over-complicated AMD internal
review process, which from the outside seems unnecessary once the
company has decided it wants to support open source. However as I
said previously I'd rather not put the people who've got this hw for 3
months now being forced to use fglrx on it if there is open code.
Its pretty well self contained and just plugs into the driver in
various places."
* 'drm-radeon-sitn-support' of git://people.freedesktop.org/~airlied/linux: (48 commits)
drm/radeon/kms: update duallink checks for DCE6
drm/radeon/kms: add trinity pci ids
drm/radeon/kms: add radeon_asic struct for trinity
drm/radeon/kms: add support for ucode loading on trinity (v2)
drm/radeon/kms/vm: set vram base offset properly for TN
drm/radeon/kms: Update evergreen functions for trinity
drm/radeon/kms: cayman gpu init updates for trinity
drm/radeon/kms: Add checks for TN in the DP bridge code
drm/radeon/kms/DCE6.1: ss is not supported on the internal pplls
drm/radeon/kms: disable PPLL0 on DCE6.1 when not in use
drm/radeon/kms: Adjust pll picker for DCE6.1
drm/radeon/kms: DCE6.1 disp eng pll updates
drm/radeon/kms: DCE6.1 watermark updates for TN
drm/radeon/kms: no support for internal thermal sensor on TN yet
drm/radeon/kms: add trinity (TN) chip family
drm/radeon/kms: Add SI pci ids
drm/radeon: Update radeon_info_ioctl for SI. (v2)
drm/radeon/kms: add radeon_asic struct for SI
drm/radeon/kms: add support for compute rings in CS ioctl on SI
drm/radeon/kms: fill in startup/shutdown callbacks for SI
...
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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Trinity (TN) is an APU with:
- Cayman 3D
- DCE6.1 display
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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v2: fix check for MC ucode from Tom.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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TN (trinity) uses DP bridges for LVDS and VGA just like llano.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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It's handled via external clock. It should already be protected
by the external ss flag, but add an explicit check just in case.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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On TN, UNIPHYA always uses PPLL2, UNIPHYB/C/D/E/F
can use either PPLL1 or PPLL0.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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DCE6.1 uses EXT_PLL1 for disp eng.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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v2: agd5f: add new MAX_PIPES param
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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Very basic implementation for picking the ring priority.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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This is mostly identical to evergreen/ni, however
there are some additional fields in the IV vector
for RINGID and VMID.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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RLC handles the interrupt controller and other tasks
on the GPU.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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Support both IBs (DE) and CONST IBs (CE).
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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Currently the driver required 5 sets of ucode:
1. pfp - pre-fetch parser, part of the CP
2. me - micro engine, part of the CP
3. ce - constant engine, part of the CP
4. rlc - interrupt controller
5. mc - memory controller
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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v2: avoid double free.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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This adds a new chunk id to the CS ioctl to support the
INDIRECT_BUFFER_CONST packet.
On SI, the CP adds a new engine called the CE (Constant Engine)
which runs simulatenously with the DE (Drawing Engine, formerly
called the ME). This allows the CP to process two related IBs
simultaneously. The CE is tasked with loading the constant data
(constant buffers, resource descriptors, samplers, etc.) while
the DE loads context register state and issues drawing commands.
It's up to the userspace application to sychronize the CE and the
DE using special synchronization packets.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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Sets up the VM and adds support for the new VM ioctls.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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