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* Merge tag 'drm-intel-next-2018-05-14' of git://anongit.freedesktop.org/drm/dr...Dave Airlie2018-05-1693-1889/+4487
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| * drm/i915: Update DRIVER_DATE to 20180514Jani Nikula2018-05-141-2/+2
| * drm/i915: Mark up nested spinlocksChris Wilson2018-05-141-1/+1
| * drm/i915/execlists: Relax CSB force-mmio for VT-dChris Wilson2018-05-141-8/+0
| * Revert "drm/i915/gvt: set max priority for gvt context"Weinan Li2018-05-141-3/+0
| * Merge branch 'drm-intel-next-queued' into gvt-nextZhi Wang2018-05-14305-4823/+13274
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| | * drm/i915/gen9: Add WaClearHIZ_WM_CHICKEN3 for bxt and glkMichel Thierry2018-05-132-0/+7
| | * drm/i915/selftests: scrub 64KMatthew Auld2018-05-133-0/+25
| | * drm/i915/oa: Check that OA is disabled before unpinningChris Wilson2018-05-111-0/+8
| | * Revert "drm/i915/cnl: Use mmio access to context status buffer"Chris Wilson2018-05-111-3/+0
| | * drm/i915/execlists: Use rmb() to order CSB readsChris Wilson2018-05-111-0/+1
| | * drm/i915/icl: WaForwardProgressSoftResetOscar Mateo2018-05-112-0/+12
| | * drm/i915/icl: Wa_1406838659Oscar Mateo2018-05-112-0/+9
| | * drm/i915/icl: Wa_1604302699Oscar Mateo2018-05-112-1/+8
| | * drm/i915/icl: Wa_1406680159Oscar Mateo2018-05-111-0/+5
| | * drm/i915/icl: Wa_1405779004Oscar Mateo2018-05-112-0/+7
| | * drm/i915/icl: WaDisCtxReloadOscar Mateo2018-05-112-0/+9
| | * drm/i915/icl: WaCL2SFHalfMaxAllocOscar Mateo2018-05-112-0/+11
| | * drm/i915/icl: WaDisableCleanEvictsOscar Mateo2018-05-112-2/+9
| | * drm/i915/icl: WaModifyGamTlbPartitioningOscar Mateo2018-05-112-0/+10
| | * drm/i915/icl: WaL3BankAddressHashingOscar Mateo2018-05-112-0/+16
| | * drm/i915/icl: WaGAPZPrioritySchemeOscar Mateo2018-05-112-2/+9
| | * drm/i915/icl: Enable Sampler DFROscar Mateo2018-05-112-1/+11
| | * drm/i915/icl: Introduce initial Icelake WorkaroundsOscar Mateo2018-05-117-6/+69
| | * drm/i915/gtt: Trust the uncached store to flush wcbMika Kuoppala2018-05-111-10/+8
| | * drm/i915: Add NV12 as supported format for sprite planeChandra Konduru2018-05-111-2/+22
| | * drm/i915: Add NV12 as supported format for primary planeChandra Konduru2018-05-112-2/+50
| | * drm/i915: Add NV12 support to intel_framebuffer_initChandra Konduru2018-05-111-0/+22
| | * drm/i915: Add skl_check_nv12_surface for NV12Maarten Lankhorst2018-05-112-3/+29
| | * drm/i915: Enable Display WA 0528Vidya Srinivas2018-05-111-3/+19
| | * drm/i915: Enable display workaround 827 for all planes, v2.Maarten Lankhorst2018-05-113-18/+33
| | * drm/i915/psr: Check if VBT says PSR can be enabled.Dhinakaran Pandiyan2018-05-093-2/+7
| | * drm/i915/guc: Make submission tasklet hardirq safeChris Wilson2018-05-091-9/+25
| | * drm/i915/execlists: Make submission tasklet hardirq safeChris Wilson2018-05-091-13/+29
| | * drm/i915/selftests: Only switch to kernel context when lockedChris Wilson2018-05-091-1/+2
| | * drm/i915/selftests: Create mock_engine() under struct_mutexChris Wilson2018-05-091-3/+6
| | * drm/i915: Annotate timeline lock nestingChris Wilson2018-05-081-1/+1
| | * drm/i915: Remove unused i915_flip tracepointsChris Wilson2018-05-081-36/+0
| | * drm/i915: Disable tasklet scheduling across initial schedulingChris Wilson2018-05-081-3/+2
| | * drm/i915: Flush submission tasklet after bumping priorityChris Wilson2018-05-081-1/+3
| | * drm/i915/selftests: Return to kernel context after each testChris Wilson2018-05-081-0/+5
| | * drm/i915: don't leak the pin_map on errorMatthew Auld2018-05-081-4/+6
| | * drm/i915/selftests: Flush GPU activity before completing live_contextsChris Wilson2018-05-081-0/+3
| | * drm/i915/selftests: Refactor common flush_test()Chris Wilson2018-05-085-122/+93
| | * drm/i915/userptr: reject zero user_sizeMatthew Auld2018-05-081-0/+3
| | * drm/i915/execlists: Cache the priolist when reschedulingChris Wilson2018-05-081-3/+10
| | * drm/i915/execlists: Drop unused parameter to lookup_priolist()Chris Wilson2018-05-081-5/+3
| | * drm/i915: Don't request a bug report for unsafe module parametersChris Wilson2018-05-081-1/+7
| | * drm/i915/icl: compute the MG PLL registersPaulo Zanoni2018-05-071-1/+222
| | * drm/i915/icl: compute the combo PHY (DPLL) DP registersPaulo Zanoni2018-05-071-1/+86
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