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* drm/radeon/kms: add ARGB2101010 colorbuffer support for r500Marek Olšák2010-12-222-1/+8
| | | | | | | This should be part of DRM 2.8.0. Signed-off-by: Marek Olšák <maraeo@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* Merge remote branch 'intel/drm-intel-next' of /ssd/git/drm-next into ↵Dave Airlie2010-12-2243-4808/+6870
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | drm-core-next * 'intel/drm-intel-next' of /ssd/git/drm-next: (771 commits) drm/i915: Undo "Uncouple render/power ctx before suspending" drm/i915: Allow the application to choose the constant addressing mode drm/i915: dynamic render p-state support for Sandy Bridge drm/i915: Enable EI mode for RCx decision making on Sandybridge drm/i915/sdvo: Border and stall select became test bits in gen5 drm/i915: Add Guess-o-matic for pageflip timestamping. drm/i915: Add support for precise vblank timestamping (v2) drm/i915: Add frame buffer compression on Sandybridge drm/i915: Add self-refresh support on Sandybridge drm/i915: Wait for vblank before unpinning old fb Revert "drm/i915: Avoid using PIPE_CONTROL on Ironlake" drm/i915: Pass clock limits down to PLL matcher drm/i915: Poll for seqno completion if IRQ is disabled drm/i915/ringbuffer: Make IRQ refcnting atomic agp/intel: Fix missed cached memory flags setting in i965_write_entry() drm/i915/sdvo: Only use the SDVO pin if it is in the valid range drm/i915: Enable RC6 autodownclocking on Sandybridge drm/i915: Terminate the FORCE WAKE after we have finished reading drm/i915/gtt: Clear the cachelines upon resume drm/i915: Restore GTT mapping first upon resume ...
| * drm/i915: Undo "Uncouple render/power ctx before suspending"Chris Wilson2010-12-201-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Manaul revert of 0cdab21f9a1fca50dd27e488839f5a6578e333b2, just to remove the call to disable the clock gatings and powerctx before suspend. Peter Clifton bisected a suspend failure on his gme45 and found this to be the culprit. As this was intended to be a fix for a similar suspend failure for Ironlake (it didn't work), undoing this patch should have no other side-effects. Reported-and-tested-by: Peter Clifton <pcjc2@cam.ac.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * drm/i915: Allow the application to choose the constant addressing modeChris Wilson2010-12-204-1/+40
| | | | | | | | | | | | | | | | | | | | The relative-to-general state default is useless as it means having to rewrite the streaming kernels for each batch. Relative-to-surface is more useful, as that stream usually needs to be rewritten for each batch. And absolute addressing mode, vital if you start streaming state, is also only available by adjusting the register... Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * drm/i915: dynamic render p-state support for Sandy BridgeJesse Barnes2010-12-187-20/+137
| | | | | | | | | | | | | | | | | | Add an interrupt handler for switching graphics frequencies and handling PM interrupts. This should allow for increased performance when busy and lower power consumption when idle. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * drm/i915: Enable EI mode for RCx decision making on SandybridgeChris Wilson2010-12-171-0/+1
| | | | | | | | | | | | | | And no I have no idea what the difference is either, just that is the recommendation. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * drm/i915/sdvo: Border and stall select became test bits in gen5Chris Wilson2010-12-161-2/+5
| | | | | | | | | | | | This is even more important as those bits will be moved in future. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * drm/i915: Add Guess-o-matic for pageflip timestamping.Mario Kleiner2010-12-161-14/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch changes the strategy for pageflip completion timestamping. It detects if the pageflip completion routine gets executed before or after drm_handle_vblank, and thereby decides if the returned vblank count and timestamp must be incremented by 1 frame(duration) or not. It compares the current system time at invocation against the current vblank timestamp. If the difference is more than 0.9 video refresh interval durations then it assumes the vblank timestamp and count are outdated and need to be incremented and does so. Otherwise it assumes a delayed pageflip irq and doesn't correct the timestamp and count. Advantage of this patch: Pageflip timestamping becomes more robust against implementation errors and is maintenance free for future GPU's. Disadvantage: A few dozen (hundred?) nsecs extra time spent in pageflip irq handler for each flip, compared to hard-coded per-gpu settings? Signed-off-by: Mario Kleiner <mario.kleiner@tuebingen.mpg.de> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * drm/i915: Add support for precise vblank timestamping (v2)Mario Kleiner2010-12-165-6/+119
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | v2: Change IS_IRONLAKE to IS_GEN5 to adapt to 2.6.37 This patch adds new functions for use by the drm core: .get_vblank_timestamp() provides a precise timestamp for the end of the most recent (or current) vblank interval of a given crtc, as needed for the DRI2 implementation of the OML_sync_control extension. It is a thin wrapper around the drm function drm_calc_vbltimestamp_from_scanoutpos() which does almost all the work. .get_scanout_position() provides the current horizontal and vertical video scanout position and "in vblank" status of a given crtc, as needed by the drm for use by drm_calc_vbltimestamp_from_scanoutpos(). The patch modifies the pageflip completion routine to use these precise vblank timestamps as the timestamps for pageflip completion events. This code has been only tested on a HP-Mini Netbook with Atom processor and Intel 945GME gpu. The codepath for (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev)) gpu's has not been tested so far due to lack of hardware. Signed-off-by: Mario Kleiner <mario.kleiner@tuebingen.mpg.de> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * Merge remote branch 'airlied/drm-core-next' into drm-intel-nextChris Wilson2010-12-16105-5084/+10693
| |\
| * | drm/i915: Add frame buffer compression on SandybridgeYuanhan Liu2010-12-154-3/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add frame buffer compression on Sandybridge. The method is similar to Ironlake, except that two new registers of type GTTMMADR must be written with the right fence info. Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | drm/i915: Add self-refresh support on SandybridgeYuanhan Liu2010-12-153-18/+334
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the support of memory self-refresh on Sandybridge, which is now support 3 levels of watermarks and the source of the latency values for watermarks has changed. On Sandybridge, the LP0 WM value is not hardcoded any more. All the latency value is now should be extracted from MCHBAR SSKPD register. And the MCHBAR base address is changed, too. For the WM values, if any calculated watermark values is larger than the maximum value that can be programmed into the associated watermark register, that watermark must be disabled. Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com> [ickle: remove duplicate compute routines and fixup for checkpatch] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | drm/i915: Wait for vblank before unpinning old fbChris Wilson2010-12-151-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | Be paranoid and ensure that the vblank has passed and the scanout has switched to the new fb, before unpinning the old one and possibly tearing down its PTEs. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | Revert "drm/i915: Avoid using PIPE_CONTROL on Ironlake"Chris Wilson2010-12-152-3/+162
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Restore PIPE_CONTROL once again just for Ironlake, as it appears that MI_USER_INTERRUPT does not have the same coherency guarantees, that is on Ironlake the interrupt following a GPU write is not guaranteed to arrive after the write is coherent from the CPU, as it does on the other generations. Reported-by: Zhenyu Wang <zhenyuw@linux.intel.com> Reported-by: Shuang He <shuang.he@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=32402 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | drm/i915: Pass clock limits down to PLL matcherChris Wilson2010-12-141-18/+16
| | | | | | | | | | | | | | | | | | | | | As we already know the limits for the hardware clock, pass it down rather than recomputing them for each match. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | drm/i915: Poll for seqno completion if IRQ is disabledChris Wilson2010-12-141-2/+4
| | | | | | | | | | | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=32288 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | drm/i915/ringbuffer: Make IRQ refcnting atomicChris Wilson2010-12-144-46/+56
| | | | | | | | | | | | | | | | | | | | | In order to enforce the correct memory barriers for irq get/put, we need to perform the actual counting using atomic operations. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson2010-12-0910-69/+79
| |\ \
| | * | drm/i915/sdvo: Only use the SDVO pin if it is in the valid rangeChris Wilson2010-12-091-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BIOSes. Can't live without them (apparently), definitely can't live with them. Reported-by: Ben Gamari <bgamari@gmail.com> Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=24312 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * | drm/i915/ringbuffer: Handle wrapping of the autoreported HEADChris Wilson2010-12-092-13/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the tail advances beyond the autoreport HEAD value, then we need to fallback to an uncached read of the HEAD register in order to ascertain the correct amount of remaining space in the ringbuffer. Reported-by: Fang, Xun <xunx.fang@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=32259 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * | drm/i915/dp: Fix I2C/EDID handling with active DisplayPort to DVI converterDavid Flynn2010-12-081-7/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DisplayPort standard (1.1a) states that: The I2C-over-AUX Reply field is valid only when Native AUX CH Reply field is AUX_ACK (00). When Native AUX CH Reply field is not 00, then, I2C-over-AUX Reply field must be 00 and be ignored. This fixes broken EDID reading when using an active DisplayPort to duallink DVI converter. If the AUX CH replier chooses to defer the transaction, a short read occurs and erroneous data is returned as the i2c reply due to a lack of length checking and failure to check for AUX ACK. As a result, broken EDIDs can look like: 0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef 00: bc bc bc ff bc bc bc ff bc bc bc ac bc bc bc 45 ???.???.???????E 10: bc bc bc 10 bc bc bc 34 bc bc bc ee bc bc bc 4c ???????4???????L 20: bc bc bc 50 bc bc bc 00 bc bc bc 40 bc bc bc 00 ???P???.???@???. 30: bc bc bc 01 bc bc bc 01 bc bc bc a0 bc bc bc 40 ???????????????@ 40: bc bc bc 00 bc bc bc 00 bc bc bc 00 bc bc bc 55 ???.???.???.???U 50: bc bc bc 35 bc bc bc 31 bc bc bc 20 bc bc bc fc ???5???1??? ???? 60: bc bc bc 4c bc bc bc 34 bc bc bc 46 bc bc bc 00 ???L???4???F???. 70: bc bc bc 38 bc bc bc 11 bc bc bc 20 bc bc bc 20 ???8??????? ??? 80: bc bc bc ff bc bc bc ff bc bc bc ff bc bc bc ff ???.???.???.???. ... which can lead to: [drm:drm_edid_block_valid] *ERROR* EDID checksum is invalid, remainder [drm:drm_edid_block_valid] *ERROR* Raw EDID: <3>30 30 30 30 30 30 30 32 38 32 30 32 63 63 31 61 000000028202cc1a <3>28 00 02 8c 00 00 00 00 18 00 00 00 00 00 00 00 (............... <3>20 4c 61 73 74 20 62 65 61 63 6f 6e 3a 20 33 32 Last beacon: 32 <3>32 30 6d 73 20 61 67 6f 46 00 05 8c 00 00 00 00 20ms agoF....... <3>36 00 00 00 00 00 00 00 00 0c 57 69 2d 46 69 20 6.........Wi-Fi <3>52 6f 75 74 65 72 01 08 82 84 8b 96 24 30 48 6c Router......$0Hl <3>03 01 01 06 02 00 00 2a 01 00 2f 01 00 32 04 0c .......*../..2.. <3>12 18 60 dd 09 00 10 18 02 00 00 01 00 00 18 00 ..`............. Signed-off-by: David Flynn <davidf@rd.bbc.co.uk> [ickle: fix up some surrounding checkpatch warnings] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org
| | * | drm/i915: i915 cannot provide switcher services.Dave Airlie2010-12-081-34/+0
| | | | | | | | | | | | | | | | | | | | | | | | it has a DSM but the switcher is done via WMI. Signed-off-by: Dave Airlie <airlied@redhat.com>
| | * | drm/radeon/kms: fix vram base calculation on rs780/rs880Alex Deucher2010-12-081-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Avoid overflowing a 32 bit value. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Cc: stable@kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
| | * | drm/radeon/kms: fix formatting of vram and gtt infoAlex Deucher2010-12-081-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | print the full 64 bit values. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
| | * | drm/radeon/kms: forbid big bo allocation (fdo 31708) v3Jerome Glisse2010-12-081-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Forbid allocating buffer bigger than visible VRAM or GTT, also properly set lpfn field. v2 - use max macro - silence warning v3 - don't explicitly set range limit - use min macro Cc: stable <stable@kernel.org> Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
| | * | drm: Don't try and disable an encoder that was never enabledChris Wilson2010-12-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Prevents code that assumes that the encoder is active when asked to be disabled from dying a horrible death. Reported-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Dave Airlie <airlied@redhat.com>
| | * | drm: Add missing drm_vblank_put() along queue vblank error pathChris Wilson2010-12-081-5/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Kristian Høgsberg <krh@bitplanet.net> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Dave Airlie <airlied@redhat.com>
| * | | drm/i915: Enable RC6 autodownclocking on SandybridgeChris Wilson2010-12-092-0/+148
| | | | | | | | | | | | | | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | drm/i915: Terminate the FORCE WAKE after we have finished readingChris Wilson2010-12-093-9/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Once we have read the value out of the GT power well, we need to remove the FORCE WAKE bit to allow the system to auto-power down. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | drm/i915/gtt: Clear the cachelines upon resumeChris Wilson2010-12-091-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | Required for my pineview system to not barf after resuming. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | drm/i915: Restore GTT mapping first upon resumeChris Wilson2010-12-091-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | As suggested by Daniel Vetter, this is a safeguard should any of the registers cause reference to PTE entries. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | drm/i915: driver.suspend and .resume are always setChris Wilson2010-12-091-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | So we can remove the repeated initialisation. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | drm/i915: Mark the user reloc error paths as unlikelyChris Wilson2010-12-091-9/+8
| | | | | | | | | | | | | | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | drm/i915: Eliminate drm_gem_object_lookup during relocationChris Wilson2010-12-092-27/+129
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As we provide a list of all objects that will be accessed from the batchbuffer, we can build a lut of the handles associated with those objects for this invocation and use that to avoid the overhead of looking up those objects again for every relocation. The cost of building and searching a small hash table is much less than that of acquiring a spinlock, searching a radix tree and manipulating an atomic refcnt per relocation. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | drm/i915: Re-arm the idle timers if the device is still busyChris Wilson2010-12-091-2/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Don't post a downclocking task if the device is still active when the idle timer fires. A pathological process could queue up several seconds worth of processing and then go to sleep, during which time the idle timer would kick in and downclock the GPU. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | drm/i915: Disable renderctx powersaving support for IronlakeChris Wilson2010-12-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | ... still causes a failure during suspend. Reported-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson2010-12-074-61/+91
| |\ \ \ | | |/ / | | | | | | | | | | | | | | | | Conflicts: drivers/gpu/drm/i915/i915_gem.c drivers/gpu/drm/i915/intel_dp.c
| | * | drm/i915/dp: Only apply the workaround if the select is still activeChris Wilson2010-12-071-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As we may try to power down the link at various times, it is not necessarily still coupled with an encoder and so we must be careful not to depend upon an operation that is only valid when the link is still attached to a pipe. Fixes regression in 5bddd17. Reported-and-tested-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org [after applying 5bddd17]
| | * | drm/i915: Emit a request to clear a flushed and idle ring for unbusy boChris Wilson2010-12-071-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order for bos to retire eventually, a request must be sent down the ring. This is expected, for example, by occlusion queries for which mesa will wait upon (whilst running glean) before issuing more batches and so the normal activity upon the ring is suspended and we need to emit a request to clear the idle ring. Reported-by: Jinjin, Wang <jinjin.wang@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=30380 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * | drm/i915/lvds: Always restore panel-fitter when enabling the LVDSChris Wilson2010-12-051-44/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Linus Torvalds pointed out that our code was unbalanced when powering on the panel with respect to the power off sequence in that we were failing to restore the panel-fitter. The consequence of this would be that across a simple DPMS off/on for a non-native mode, without an intervening modeset, the panel fitter would remain disabled and the output would shift on the panel. Reported-by: Linus Torvalds <torvalds@linux-foundation.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * | drm/i915/ringbuffer: Only print an error on the second attempt to reset headChris Wilson2010-12-051-14/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There's not much we can do here but hope for the best. However the first failure happens quite frequently and if often remedied by the second attempt to reset HEAD. So only print the error if that attempt also fails. Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=19802 Reported-by: Thomas Meyer <thomas@m3y3r.de> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org
| * | | drm/i915: Wait for the bo if a display flip is pipelined on the other ringChris Wilson2010-12-061-1/+1
| | | | | | | | | | | | | | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | drm/i915: Only emit a flush if there is an outstanding gpu writeChris Wilson2010-12-061-2/+3
| | | | | | | | | | | | | | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | drm/i915: Completely disable fence pipelining.Chris Wilson2010-12-051-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | I'm still seeing tiling corruption of PutImage and CopyArea (I think) under mutter on pnv, so obviously the pipelining logic is deeply flawed. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | drm/i915: Uncouple render/power ctx before suspendingChris Wilson2010-12-053-26/+36
| | | | | | | | | | | | | | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | drm/i915: Ignore fenced commands for gpu access on gen4Chris Wilson2010-12-051-11/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Userspace should not have been declaring that it needed fenced GPU access with gen4+ as those GPUs have no fenced commands, but to be on the safe side it is easier to ignore userspace in case they did. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | drm/i915: caps.has_rc6 is no longer used, remove it.Chris Wilson2010-12-053-6/+3
| | | | | | | | | | | | | | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | drm/i915: Power Context register is only available for gen4 mobilesChris Wilson2010-12-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The ability to save the hardware context upon powering down the render clock through PWRCTXA is only available on a couple of gen4 chipsets. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | drm/i915: Avoid using PIPE_CONTROL on IronlakeChris Wilson2010-12-052-159/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The workaround is hideous and we are using the STORE_DWORD on all other generations on all other rings, so use for the gen5 render ring as well. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | drm/i915/dp: Trivial code tidyChris Wilson2010-12-051-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Locally scope the crtc to where it is used. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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