summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/tegra
Commit message (Collapse)AuthorAgeFilesLines
* drm/tegra: dc: Select root window for event dispatchSean Paul2014-12-171-2/+22
| | | | | | | | | | | | | In finish pageflip, the driver was not selecting the root window when dispatching events. This exposed a race where a plane update would change the window selection and cause tegra_dc_finish_page_flip to check the wrong base address. This patch also protects access to the window selection register as well as the registers affected by it. Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: gem: Use the proper size for GEM objectsThierry Reding2014-12-171-7/+7
| | | | | | | | | | | If the requested buffer size wasn't a multiple of the page size, the IOMMU code would round down the size to the next multiple of the page size, thereby causing translation errors. To fix this we no longer pass around the requested size but reuse the computed size of the GEM object. This is already rounded to the next page boundary, so mapping that size works out fine. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: gem: Flush buffer objects upon allocationThierry Reding2014-12-171-4/+32
| | | | | | | | Buffers obtained via shmem may still have associated cachelines. If they aren't properly flushed they may cause framebuffer corruption if the cache gets flushed after the application has drawn to it. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dc: Fix a potential race on page-flip completionThierry Reding2014-12-171-3/+7
| | | | | | | | Page-flip completion could race with page-flip submission, so extend the critical section to include all accesses to page-flip related data. Reported-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dc: Consistently use the same pipeThierry Reding2014-12-172-13/+17
| | | | | | | | | | | | | The hardware pipe numbers don't always match the DRM CRTC indices. This can happen for example if the first display controller defers probe, causing it to be registered with DRM after the second display controller. When that happens the hardware pipe numbers and DRM CRTC indices become different. Make sure that the CRTC index is always used when accessing per-CRTC VBLANK data. This can be ensured by using the drm_crtc_vblank_*() API, which will do the right thing automatically given a struct drm_crtc *. Signed-off-by: Thierry Reding <treding@nvidia.com>
* Merge tag 'v3.18-rc7' into drm-nextDave Airlie2014-12-021-4/+4
|\ | | | | | | | | | | | | | | | | | | | | | | This fixes a bunch of conflicts prior to merging i915 tree. Linux 3.18-rc7 Conflicts: drivers/gpu/drm/exynos/exynos_drm_drv.c drivers/gpu/drm/i915/i915_drv.c drivers/gpu/drm/i915/intel_pm.c drivers/gpu/drm/tegra/dc.c
| * drm/tegra: dc: Add missing call to drm_vblank_on()Thierry Reding2014-11-131-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When the CRTC is enabled, make sure the VBLANK machinery is enabled. Failure to do so will cause drm_vblank_get() to not enable the VBLANK on the CRTC and VBLANK-synchronized page-flips won't work. While at it, get rid of the legacy drm_vblank_pre_modeset() and drm_vblank_post_modeset() calls that are replaced by drm_vblank_on() and drm_vblank_off(). Reported-by: Alexandre Courbot <acourbot@nvidia.com> Tested-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* | Merge tag 'drm/tegra/for-3.19-rc1' of ↵Dave Airlie2014-11-1510-414/+1536
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://people.freedesktop.org/~tagr/linux into drm-next drm/tegra: Changes for v3.19-rc1 The highlights in this pull request are: * IOMMU support: The Tegra DRM driver can now deal with discontiguous buffers if an IOMMU exists in the system. That means it can allocate using drm_gem_get_pages() and will map them into IOVA space via the IOMMU API. Similarly, non-contiguous PRIME buffers can be imported from a different driver, which allows better integration with gk20a (nouveau) and less hacks. * Universal planes: This is precursory work for atomic modesetting and will allow hardware cursor support to be implemented on pre-Tegra114 where RGB cursors were not supported. * DSI ganged-mode support: The DSI controller can now gang up with a second DSI controller to drive high resolution DSI panels. Besides those bigger changes there is a slew of fixes, cleanups, plugged memory leaks and so on. * tag 'drm/tegra/for-3.19-rc1' of git://people.freedesktop.org/~tagr/linux: (44 commits) drm/tegra: gem: Check before freeing CMA memory drm/tegra: fb: Add error codes to error messages drm/tegra: fb: Properly release GEM objects on failure drm/tegra: Detach panel when a connector is removed drm/tegra: Plug memory leak drm/tegra: gem: Use more consistent data types drm/tegra: fb: Do not destroy framebuffer drm/tegra: gem: dumb: pitch and size are outputs drm/tegra: Enable the hotplug interrupt only when necessary drm/tegra: dc: Universal plane support drm/tegra: dc: Registers are 32 bits wide drm/tegra: dc: Factor out DC, window and cursor commit drm/tegra: Add IOMMU support drm/tegra: Fix error handling cleanup drm/tegra: gem: Use dma_mmap_writecombine() drm/tegra: gem: Remove redundant drm_gem_free_mmap_offset() drm/tegra: gem: Cleanup tegra_bo_create_with_handle() drm/tegra: gem: Extract tegra_bo_alloc_object() drm/tegra: dsi: Set up PHY_TIMING & BTA_TIMING registers earlier drm/tegra: dsi: Replace 1000000 by USEC_PER_SEC ...
| * | drm/tegra: gem: Check before freeing CMA memoryThierry Reding2014-11-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dma_free_writecombine() must not be called on a buffer that couldn't be allocated. Check for a valid virtual address before attempting to free the memory to avoid a crash. Reported-by: Sean Paul <seanpaul@chromium.org> Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: fb: Add error codes to error messagesThierry Reding2014-11-131-4/+7
| | | | | | | | | | | | | | | | | | | | | This helps in determining what errors happened at specifics points in the initialization sequence. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: fb: Properly release GEM objects on failureThierry Reding2014-11-131-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | When fbdev initialization fails, make sure to unreference the GEM objects properly. Note that we can't do this in the general error unwinding path because ownership of the GEM object references is transferred to the framebuffer upon creation. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: Detach panel when a connector is removedThierry Reding2014-11-131-0/+3
| | | | | | | | | | | | | | | | | | | | | When the DRM device is torn down and the connector is removed, make sure to detach the panel to make sure there are no dangling pointers. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: Plug memory leakThierry Reding2014-11-131-0/+2
| | | | | | | | | | | | | | | | | | | | | Free the DRM device-private memory upon driver unload to make sure the memory doesn't leak. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: gem: Use more consistent data typesThierry Reding2014-11-132-8/+8
| | | | | | | | | | | | | | | | | | | | | Use size_t consistently for sizes and u32/u64 instead of uint32_t and uint64_t. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: fb: Do not destroy framebufferThierry Reding2014-11-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Drop a reference instead of directly calling the framebuffer .destroy() callback at fbdev free time. This is necessary to make sure the object isn't destroyed if anyone else still has a reference. Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: gem: dumb: pitch and size are outputsThierry Reding2014-11-131-7/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When creating a dumb buffer object using the DRM_IOCTL_MODE_CREATE_DUMB IOCTL, only the width, height, bpp and flags parameters are inputs. The caller is not guaranteed to zero out or set handle, pitch and size, so the driver must not treat these values as possible inputs. Fixes a bug where running the Weston compositor on Tegra DRM would cause an attempt to allocate a 3 GiB framebuffer to be allocated. Fixes: de2ba664c30f ("gpu: host1x: drm: Add memory manager and fb") Cc: stable@vger.kernel.org Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: Enable the hotplug interrupt only when necessaryThierry Reding2014-11-131-1/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The hotplug handling needs access to the DRM device, which only appears at ->init() time. Disable interrupts up until that time. Similarly, when an output is removed, disable the hotplug interrupt again because the DRM device (and with it the hotplug infrastructure) is going away. Also make sure to only access the DRM device if it's available. Given the above change for the hotplug interrupt this should really never happen, but the extra check doesn't hurt either. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: dc: Universal plane supportThierry Reding2014-11-131-157/+330
| | | | | | | | | | | | | | | | | | | | | | | | This allows the primary plane and cursor to be exposed as regular DRM/KMS planes, which is a prerequisite for atomic modesetting and gives userspace more flexibility over controlling them. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: dc: Registers are 32 bits wideThierry Reding2014-11-132-7/+6
| | | | | | | | | | | | | | | | | | | | | | | | Using an unsigned long type will cause these variables to become 64-bit on 64-bit SoCs. In practice this should always work, but there's no need for carrying around the additional 32 bits. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: dc: Factor out DC, window and cursor commitThierry Reding2014-11-131-24/+28
| | | | | | | | | | | | | | | | | | | | | | | | The sequence to commit changes to the DC, window or cursor configuration is repetitive and can be extracted into separate functions for ease of use. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: Add IOMMU supportThierry Reding2014-11-136-34/+309
| | | | | | | | | | | | | | | | | | | | | | | | | | | When an IOMMU device is available on the platform bus, allocate an IOMMU domain and attach the display controllers to it. The display controllers can then scan out non-contiguous buffers by mapping them through the IOMMU. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: Fix error handling cleanupThierry Reding2014-11-133-7/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DRM driver's ->load() implementation didn't do a good job (no job at all really) cleaning up on failure. Fix that by undoing any prior setup when an error occurs. This requires a bit of rework to make it possible to clean up fbdev midway. This was tested by injecting errors at various points during the initialization sequence and verifying that error cleanup didn't crash and no memory leaked (using kmemleak). Reported-by: Stéphane Marchesin <marcheu@chromium.org> Reported-by: Sean Paul <seanpaul@chromium.org> Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: gem: Use dma_mmap_writecombine()Thierry Reding2014-11-131-4/+12
| | | | | | | | | | | | | | | | | | | | | Use the existing API rather than open-coding equivalent functionality in the driver. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: gem: Remove redundant drm_gem_free_mmap_offset()Thierry Reding2014-11-131-2/+0
| | | | | | | | | | | | | | | | | | | | | The drm_gem_object_release() function already performs this cleanup, so there is no reason to do it explicitly. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: gem: Cleanup tegra_bo_create_with_handle()Thierry Reding2014-11-131-8/+6
| | | | | | | | | | | | | | | | | | | | | | | | There is only a single location where the function needs to do cleanup. Skip the error unwinding path and call the cleanup function directly instead. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: gem: Extract tegra_bo_alloc_object()Thierry Reding2014-11-131-39/+38
| | | | | | | | | | | | | | | | | | | | | This function implements the common buffer object allocation used for both allocation and import paths. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: dsi: Set up PHY_TIMING & BTA_TIMING registers earlierSean Paul2014-11-131-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make sure the DSI PHY_TIMING and BTA_TIMING registers are initialized when the clocks are set up as opposed to when the output is enabled. This makes sure that the PHY timings are properly set up when the panel is prepared and that DCS commands sent at that time use the appropriate timings. Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: dsi: Replace 1000000 by USEC_PER_SECThierry Reding2014-11-131-1/+1
| | | | | | | | | | | | | | | | | | Using the symbolic constant instantly provides a lot more context. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: dsi: Replace 1000000000UL by NSEC_PER_SECThierry Reding2014-11-131-1/+1
| | | | | | | | | | | | | | | | | | Using the symbolic constant instantly provides a lot more context. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: dsi: Implement host transfersThierry Reding2014-11-132-1/+279
| | | | | | | | | | | | | | | | | | | | | | | | Add support for sending MIPI DSI command packets from the host to a peripheral. This is required for panels that need configuration before they accept video data. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: dsi: Add ganged mode supportThierry Reding2014-11-132-29/+193
| | | | | | | | | | | | | | | | | | | | | | | | | | | Implement ganged mode support for the Tegra DSI driver. The DSI host controller to gang up with is specified via a phandle in the device tree and the resolved DSI host controller used for the programming of the ganged-mode registers. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: dsi: Split out tegra_dsi_set_timeout()Thierry Reding2014-11-131-15/+23
| | | | | | | | | | | | | | | | | | | | | | | | In preparation for adding ganged-mode support, this commit splits out the tegra_dsi_set_timeout() function so that it can be reused for the slave DSI controller. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: dsi: Add command mode supportThierry Reding2014-11-131-19/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for DC-driven command mode. This is a mode where the video stream sent by the display controller is packed into DCS command packets (write_memory_start and write_memory_continue) by the DSI controller. It can be used for panels with a remote framebuffer and is useful to save power when used with a dynamic refresh rate (not yet supported by the driver). Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: dsi: Refactor in preparation for command modeThierry Reding2014-11-131-19/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For command mode panels, the DSI controller needs to be enabled and configured so that panel drivers can send commands prior to the video stream being enabled. Move code from the monolithic output enable/disable functions into smaller, reusable units to allow more fine-grained control over the controller state. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: dsi: Properly cleanup on probe failureThierry Reding2014-11-131-15/+37
| | | | | | | | | | | | | | | | | | | | | | | | The driver wasn't even attempting to do any cleanup when probing failed. Fix this by releasing any resources acquired up to the point of failure and putting the device back into the original state (reset, clocks off). Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: dsi: Mark connector hotpluggableThierry Reding2014-11-131-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DSI panels can always be hotplugged via the DSI bus' attach/detach infrastructure, so unconditionally mark the connector hotpluggable. While at it, also make sure that when a panel is detached the connector is marked unconnected before calling into the DRM hotplug helpers to reflect the correct state. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: dsi: Leave parent clock aloneThierry Reding2014-11-131-7/+0
| | | | | | | | | | | | | | | | | | | | | The common clock framework will take care of preparing and enabling the parent of the DSI clock automatically. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: dsi: Do not manage clock on enable/disableThierry Reding2014-11-131-15/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In preparation for supporting command mode panels, don't disable the clock when the output is disabled. The output will be enabled only after the panel has been programmed in command mode, so the clock must always remain on. As a side-effect, pad calibration now only needs to be done at driver probe time, since neither power nor controller state will go away before driver removal. While at it, use a 32-bit variable to store register content because the registers are 32-bit even on 64-bit Tegra. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: dsi: Make FIFO depths host parametersThierry Reding2014-11-131-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than hardcoding them as macros, make the host and video FIFO depths parameters so that they can be more easily adjusted if a new generation of the Tegra SoC changes them. While at it, set the depth of the video FIFO to the correct value of 1920 *words* rather than *bytes*. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: DPMS off/on in encoder prepare/commitSean Paul2014-11-131-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously the panel and output were only enabled on encoder->dpms(). If userspace called dpms on before doing a modeset, the driver would get into a state where the connector had a dpms state of ON, but the encoder and output were not enabled (because the encoder is not yet attached to the connector). Subsequent dpms ON calls are ignored b/c the connector's state already matches the desired state. This patch enables/disables the panel and output on modeset as well, so we can catch the above case. Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: Do not enable output on .mode_set()Thierry Reding2014-11-131-6/+0
| | | | | | | | | | | | | | | | | | | | | The output is already enabled in .dpms(), doing it in .mode_set() too can cause noticeable flicker. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: dc: Add powergate supportThierry Reding2014-11-132-3/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | Both display controllers are in their own power partition. Currently the driver relies on the assumption that these partitions are on (which is the hardware default). However some bootloaders may disable them, so the driver must make sure to turn them back on to avoid hangs. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/tegra: Depend on COMMON_CLKThierry Reding2014-11-131-0/+1
| |/ | | | | | | | | | | | | | | | | | | The introduction of the COMPILE_TEST dependency in commit 158b50aefa14 (drm/tegra: Increase compile test coverage) removes the dependency on COMMON_CLK (implicitly selected via ARCH_TEGRA, ARCH_MULTI_V7 and ARCH_MULTIPLATFORM). Reported-by: Russell King <linux@arm.linux.org.uk> Signed-off-by: Thierry Reding <treding@nvidia.com>
* | drm: Move drm_crtc_init from drm_crtc.h to drm_plane_helper.hDaniel Vetter2014-11-051-0/+2
|/ | | | | | | | | | | | | | | | | | | Just a bit of OCD cleanup on headers - this function isn't the core interface any more but just a helper for drivers who haven't yet transitioned to universal planes. Put the declaration at the right spot and sprinkle necessary #includes over all drivers. Maybe this helps to encourage driver maintainers to do the switch. v2: Fix #include ordering for tegra, reported by 0-day builder. v3: Include required headers, reported by Thierry. Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Thierry Reding <treding@nvidia.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
* drm: Extract <drm/drm_gem.h>Daniel Vetter2014-09-241-0/+1
| | | | | | | | | | | v2: Don't forget git add, noticed by David. Cc: David Herrmann <dh.herrmann@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Acked-by: David Herrmann <dh.herrmann@gmail.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/tegra: Renaming DP training vswing pre emph definesSonika Jindal2014-09-031-2/+2
| | | | | | | | | | | | | | | | | | | | Rename the defines to have levels instead of values for vswing and pre-emph levels as the values may differ in other scenarios like low vswing of eDP1.4 where the values are different. Done using following cocci patch for each define: @@ @@ # define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0) + # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0) ... Signed-off-by: Sonika Jindal <sonika.jindal@intel.com> Acked-by: Dave Airlie <airlied@gmail.com> Acked-by: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* Merge tag 'cleanup-for-3.17' of ↵Linus Torvalds2014-08-082-2/+4
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC cleanups from Olof Johansson: "This merge window brings a good size of cleanups on various platforms. Among the bigger ones: - Removal of Samsung s5pc100 and s5p64xx platforms. Both of these have lacked active support for quite a while, and after asking around nobody showed interest in keeping them around. If needed, they could be resurrected in the future but it's more likely that we would prefer reintroduction of them as DT and multiplatform-enabled platforms instead. - OMAP4 controller code register define diet. They defined a lot of registers that were never actually used, etc. - Move of some of the Tegra platform code (PMC, APBIO, fuse, powergate) to drivers/soc so it can be shared with 64-bit code. This also converts them over to traditional driver models where possible. - Removal of legacy gpio-samsung driver, since the last users have been removed (moved to pinctrl) Plus a bunch of smaller changes for various platforms that sort of dissapear in the diffstat for the above. clps711x cleanups, shmobile header file refactoring/moves for multiplatform friendliness, some misc cleanups, etc" * tag 'cleanup-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (117 commits) drivers: CCI: Correct use of ! and & video: clcd-versatile: Depend on ARM video: fix up versatile CLCD helper move MAINTAINERS: Add sdhci-st file to ARCH/STI architecture ARM: EXYNOS: Fix build breakge with PM_SLEEP=n MAINTAINERS: Remove Kirkwood ARM: tegra: Convert PMC to a driver soc/tegra: fuse: Set up in early initcall ARM: tegra: Always lock the CPU reset vector ARM: tegra: Setup CPU hotplug in a pure initcall soc/tegra: Implement runtime check for Tegra SoCs soc/tegra: fuse: fix dummy functions soc/tegra: fuse: move APB DMA into Tegra20 fuse driver soc/tegra: Add efuse and apbmisc bindings soc/tegra: Add efuse driver for Tegra ARM: tegra: move fuse exports to soc/tegra/fuse.h ARM: tegra: export apb dma readl/writel ARM: tegra: Use a function to get the chip ID ARM: tegra: Sort includes alphabetically ARM: tegra: Move includes to include/soc/tegra ...
| * ARM: tegra: Convert PMC to a driverThierry Reding2014-07-172-2/+2
| | | | | | | | | | | | | | | | This commit converts the PMC support code to a platform driver. Because the boot process needs to call into this driver very early, also set up a minimal environment via an early initcall. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * ARM: tegra: Move includes to include/soc/tegraThierry Reding2014-07-172-2/+4
| | | | | | | | | | | | | | In order to not clutter the include/linux directory with SoC specific headers, move the Tegra-specific headers out into a separate directory. Signed-off-by: Thierry Reding <treding@nvidia.com>
* | Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linuxLinus Torvalds2014-08-0714-73/+404
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull DRM updates from Dave Airlie: "Like all good pull reqs this ends with a revert, so it must mean we tested it, [ Ed. That's _one_ way of looking at it ] This pull is missing nouveau, Ben has been stuck trying to track down a very longstanding bug that revealed itself due to some other changes. I've asked him to send you a direct pull request for nouveau once he cleans things up. I'm away until Monday so don't want to delay things, you can make a decision on that when he sends it, I have my phone so I can ack things just not really merge much. It has one trivial conflict with your tree in armada_drv.c, and also the pull request contains some component changes that are already in your tree, the base tree from Russell went via Greg's tree already, but some stuff still shows up in here that doesn't when I merge my tree into yours. Otherwise all pretty standard graphics fare, one new driver and changes all over the place. New drivers: - sti kms driver for STMicroelectronics chipsets stih416 and stih407. core: - lots of cleanups to the drm core - DP MST helper code merged - universal cursor planes. - render nodes enabled by default panel: - better panel interfaces - new panel support - non-continuous cock advertising ability ttm: - shrinker fixes i915: - hopefully ditched UMS support - runtime pm fixes - psr tracking and locking - now enabled by default - userptr fixes - backlight brightness fixes - MST support merged - runtime PM for dpms - primary planes locking fixes - gen8 hw semaphore support - fbc fixes - runtime PM on SOix sleep state hw. - mmio base page flipping - lots of vlv/chv fixes. - universal cursor planes radeon: - Hawaii fixes - display scalar support for non-fixed mode displays - new firmware format support - dpm on more asics by default - GPUVM improvements - uncached and wc GTT buffers - BOs > visible VRAM exynos: - i80 interface support - module auto-loading - ipp driver consolidated. armada: - irq handling in crtc layer only - crtc renumbering - add component support - DT interaction changes. tegra: - load as module fixes - eDP bpp and sync polarity fixed - DSI non-continuous clock mode support - better support for importing buffers from nouveau msm: - mdp5/adq8084 v1.3 hw enablement - devicetree clk changse - ifc6410 board working tda998x: - component support - DT documentation update vmwgfx: - fix compat shader namespace" * 'drm-next' of git://people.freedesktop.org/~airlied/linux: (551 commits) Revert "drm: drop redundant drm_file->is_master" drm/panel: simple: Use devm_gpiod_get_optional() drm/dsi: Replace upcasting macro by function drm/panel: ld9040: Replace upcasting macro by function drm/exynos: dp: Modify driver to support drm_panel drm/exynos: Move DP setup into commit() drm/panel: simple: Add AUO B133HTN01 panel support drm/panel: simple: Support delays in panel functions drm/panel: simple: Add proper definition for prepare and unprepare drm/panel: s6e8aa0: Add proper definition for prepare and unprepare drm/panel: ld9040: Add proper definition for prepare and unprepare drm/tegra: Add support for panel prepare and unprepare routines drm/exynos: dsi: Add support for panel prepare and unprepare routines drm/exynos: dpi: Add support for panel prepare and unprepare routines drm/panel: simple: Add dummy prepare and unprepare routines drm/panel: s6e8aa0: Add dummy prepare and unprepare routines drm/panel: ld9040: Add dummy prepare and unprepare routines drm/panel: Provide convenience wrapper for .get_modes() drm/panel: add .prepare() and .unprepare() functions drm/panel: simple: Remove simple-panel compatible ...
OpenPOWER on IntegriCloud