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* Merge tag 'drm/tegra/for-3.17-rc1' of ↵Dave Airlie2014-08-0713-50/+359
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://anongit.freedesktop.org/tegra/linux into drm-next drm/tegra: Changes for v3.17-rc1 Mostly some cleanup all over the place. Pitch alignment limitations of the display controller are now honored and job submission is 64-bit safe. The SOR output (used for eDP) properly configures sync signal polarities according to the display mode rather than hard-coding them to some value and the number of bits per color is now taken from the panel rather than hard-coded to properly support 24-bit vs. 18-bit panels. The DSI controller now properly supports non-continuous clock mode. GEM objects can now have their flags and tiling mode modified via IOCTLs to allow buffers imported from Nouveau to be properly displayed. Newer generations of the Tegra display controller can also detile block linear buffers at scan-out time. Finally the driver now properly exports MODULE_DEVICE_TABLEs to allow it to be automatically loaded when built as a module. * tag 'drm/tegra/for-3.17-rc1' of git://anongit.freedesktop.org/tegra/linux: drm/tegra: add MODULE_DEVICE_TABLEs drm/tegra: dc - Reset controller on driver remove drm/tegra: Properly align stride for framebuffers drm/tegra: sor - Configure proper sync polarities drm/tegra: sor - Use bits-per-color from panel drm/tegra: Make job submission 64-bit safe drm/tegra: Allow non-authenticated processes to create buffer objects drm/tegra: Add SET/GET_FLAGS IOCTLs drm/tegra: Add SET/GET_TILING IOCTLs drm/tegra: Implement more tiling modes drm/tegra: dsi - Handle non-continuous clock flag drm/tegra: sor - missing unlock on error
| * drm/tegra: add MODULE_DEVICE_TABLEsStephen Warren2014-08-047-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When tegra-drm.ko is built as a module, these MODULE_DEVICE_TABLEs allow the module to be auto-loaded since the module will match the devices instantiated from device tree. (Notes for stable: in 3.14+, just git rm any conflicting file, since they are added in later kernels. For 3.13 and below, manual merging will be needed) Cc: <stable@vger.kernel.org> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: dc - Reset controller on driver removeThierry Reding2014-08-041-0/+1
| | | | | | | | | | | | | | | | Since the device will no longer be used, may as well keep it in reset to potentially save some power and make sure it is in a clean state the next time it's probed. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: Properly align stride for framebuffersThierry Reding2014-08-044-1/+27
| | | | | | | | | | | | | | | | | | | | | | Tegra20 and Tegra30 both required the buffer line stride to be aligned on 8 byte boundaries. Tegra114 and Tegra124 increased the alignment to 64 bytes. Introduce a parameter to specify the alignment requirements for each display controller and round up the pitch of newly allocated framebuffers appropriately. Originally-by: Stéphane Marchesin <marcheu@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: sor - Configure proper sync polaritiesThierry Reding2014-08-041-3/+13
| | | | | | | | | | | | Program the sync signal polarities according to the display mode. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: sor - Use bits-per-color from panelStéphane Marchesin2014-08-041-1/+1
| | | | | | | | | | | | | | | | This change uses the value of bits-per-color from panel to remove one more hardcoded value. Signed-off-by: Stéphane Marchesin <marcheu@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: Make job submission 64-bit safeThierry Reding2014-08-041-18/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Job submission currently relies on the fact that struct drm_tegra_reloc and struct host1x_reloc are the same size and uses a simple call to the copy_from_user() function to copy them to kernel space. This causes the handle to be stored in the buffer object field, which then needs a cast to a 32 bit integer to resolve it to a proper buffer object pointer and store it back in the buffer object field. On 64-bit architectures that will no longer work, since pointers are 64 bits wide whereas handles will remain 32 bits. This causes the sizes of both structures to because different and copying will no longer work. Fix this by adding a new function, host1x_reloc_get_user(), that copies the structures field by field. While at it, use substructures for the command and target buffers in struct host1x_reloc for better readability. Also use unsized types to make it more obvious that this isn't part of userspace ABI. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: Allow non-authenticated processes to create buffer objectsThierry Reding2014-08-041-1/+1
| | | | | | | | | | | | | | | | This matches what other drivers do for equivalent IOCTLs. Reviewed-by: Stéphane Marchesin <marcheu@chromium.org> Tested-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: Add SET/GET_FLAGS IOCTLsThierry Reding2014-08-041-0/+49
| | | | | | | | | | | | | | | | | | | | | | The DRM_TEGRA_GEM_SET_FLAGS IOCTL can be used to set the flags of a buffer object after it has been allocated or imported. Flags associated with a buffer object can be queried using the DRM_TEGRA_GEM_GET_FLAGS IOCTL. Reviewed-by: Stéphane Marchesin <marcheu@chromium.org> Tested-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: Add SET/GET_TILING IOCTLsThierry Reding2014-08-041-0/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the tiling parameters of buffer objects can only be set at allocation time, and only a single tiled mode is supported. This new DRM_TEGRA_GEM_SET_TILING IOCTL allows more modes to be set and also allows the tiling mode to be changed after the allocation. This will enable the Tegra DRM driver to import buffers from a GPU and directly scan them out by configuring the display controller appropriately. To complement this, the DRM_TEGRA_GEM_GET_TILING IOCTL can query the current tiling mode of a buffer object. This is necessary when importing buffers via handle (as is done in Mesa for example) so that userspace can determine the proper parameters for the 2D or 3D engines. Reviewed-by: Stéphane Marchesin <marcheu@chromium.org> Tested-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: Implement more tiling modesThierry Reding2014-08-046-24/+118
| | | | | | | | | | | | | | | | | | Tegra124 supports a block-linear mode in addition to the regular pitch linear and tiled modes. Add support for these by moving the internal representation into a structure rather than a simple flag. Tested-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: dsi - Handle non-continuous clock flagAlexandre Courbot2014-08-041-1/+2
| | | | | | | | | | | | | | | | | | Handle the MIPI_DSI_CLOCK_NONCONTINUOUS flag and only set TX-only clock behavior when this flag is present to allow panels requiring continuous clock mode to operate with this driver. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: sor - missing unlock on errorDan Carpenter2014-08-041-1/+1
| | | | | | | | | | | | | | We should unlock before returning the error code. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* | Merge tag 'drm/panel/for-3.17-rc1' of ↵Dave Airlie2014-08-071-0/+2
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://anongit.freedesktop.org/tegra/linux into drm-next drm/panel: Changes for v3.17-rc1 Panels can now be more finely controlled via .prepare() and .unprepare() callbacks in addition to .enable() and .disable(). New kerneldoc details what they are supposed to do and when they should be called. The simple panel driver gained support for a couple of new panels and it is now possible to specify additional delays during power up and power down sequences if panels require it. DSI devices can now advertise that they support non-continuous clock mode which will allow DSI host controllers to disable the high speed clock after transmissions to save power. * tag 'drm/panel/for-3.17-rc1' of git://anongit.freedesktop.org/tegra/linux: (30 commits) drm/panel: simple: Use devm_gpiod_get_optional() drm/dsi: Replace upcasting macro by function drm/panel: ld9040: Replace upcasting macro by function drm/exynos: dp: Modify driver to support drm_panel drm/exynos: Move DP setup into commit() drm/panel: simple: Add AUO B133HTN01 panel support drm/panel: simple: Support delays in panel functions drm/panel: simple: Add proper definition for prepare and unprepare drm/panel: s6e8aa0: Add proper definition for prepare and unprepare drm/panel: ld9040: Add proper definition for prepare and unprepare drm/tegra: Add support for panel prepare and unprepare routines drm/exynos: dsi: Add support for panel prepare and unprepare routines drm/exynos: dpi: Add support for panel prepare and unprepare routines drm/panel: simple: Add dummy prepare and unprepare routines drm/panel: s6e8aa0: Add dummy prepare and unprepare routines drm/panel: ld9040: Add dummy prepare and unprepare routines drm/panel: Provide convenience wrapper for .get_modes() drm/panel: add .prepare() and .unprepare() functions drm/panel: simple: Remove simple-panel compatible drm/panel: simple: Add Innolux N116BGE panel support ...
| * drm/tegra: Add support for panel prepare and unprepare routinesAjay Kumar2014-08-061-0/+2
| | | | | | | | | | | | | | | | Modify tegra output driver to support the new panel calls: prepare and unprepare. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* | drm/tegra: Implement race-free hotplug detectionThierry Reding2014-07-083-17/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A race condition currently exists on Tegra, where it can happen that a monitor attached via HDMI isn't detected during the initial FB helper setup, but the hotplug event happens too early to be processed by the poll helpers because they haven't been initialized yet. This happens because on some boards the HDMI driver can control the regulator that supplies the +5V pin on the HDMI connector. Therefore depending on the timing between the initialization of the HDMI driver and the rest of DRM, it's possible that the monitor returns the hotplug signal right within the window where we would miss it. Unfortunately, drm_kms_helper_poll_init() will wreak havoc when called before at least some parts of the FB helpers have been set up. This commit fixes this by splitting out the minimum of initialization required to make drm_kms_helper_poll_init() work into a separate function that can be called early. It is then safe to move all of the poll helper initialization to an earlier point in time (before the HDMI output driver has a chance to enable the +5V supply). That way if the hotplug signal is returned before the initial FB helper setup, the monitor will be forcefully detected at that point, and if the hotplug signal is returned after that it will be properly handled by the poll helpers. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* | drm: Introduce drm_fb_helper_prepare()Thierry Reding2014-07-081-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To implement hotplug detection in a race-free manner, drivers must call drm_kms_helper_poll_init() before hotplug events can be triggered. Such events can be triggered right after any of the encoders or connectors are initialized. At the same time, if the drm_fb_helper_hotplug_event() helper is used by a driver, then the poll helper requires some parts of the FB helper to be initialized to prevent a crash. At the same time, drm_fb_helper_init() requires information that is not necessarily available at such an early stage (number of CRTCs and connectors), so it cannot be used yet. Add a new helper, drm_fb_helper_prepare(), that initializes the bare minimum needed to allow drm_kms_helper_poll_init() to execute and any subsequent hotplug events to be processed properly. Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* | drm: Constify struct drm_fb_helper_funcsThierry Reding2014-07-081-1/+1
| | | | | | | | | | | | | | | | | | | | There's no need for this to be modifiable. Make it const so that it can be put into the .rodata section. Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Dave Airlie <airlied@redhat.com>
* | drm: add register and unregister functions for connectorsThomas Wood2014-06-191-2/+2
|/ | | | | | | | | | Introduce generic functions to register and unregister connectors. This provides a common place to add and remove associated user space interfaces. Signed-off-by: Thomas Wood <thomas.wood@intel.com> Reviewed-by: David Herrmann <dh.herrmann@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/tegra: sor - Remove obsolete commentThierry Reding2014-06-091-1/+1
| | | | | | | | | According to the DP specification the disparity of the first symbol should always be negative. It is therefore safe to assume that panels will conform to that and therefore parameterizing this field should never be necessary. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: sor - Enable only the necessary number of lanesThierry Reding2014-06-091-1/+1
| | | | | | | Instead of always enabling all four lanes, enable only the number probed from the link. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: sor - Power on only the necessary lanesThierry Reding2014-06-091-3/+17
| | | | | | Power on only those lanes required for the specified link. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: sor - Do not program interlaced mode registersThierry Reding2014-06-091-3/+0
| | | | | | | Interlaced mode is currently not supported on the SOR, so don't program any associated registers. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: sor - Do not hardcode link speedThierry Reding2014-06-091-2/+2
| | | | | | | Use the speed probed from the link at runtime rather than relying on a hardcoded default. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: sor - Do not hardcode number of blank symbolsThierry Reding2014-06-091-3/+23
| | | | | | | | | | | The number of HBLANK and VBLANK symbols can be computed at runtime so that they can be set appropriately depending on the video mode and DP link. These values are used by the packet generation logic to determine how many audio samples can be transferred during the blanking intervals. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: sor - Don't hardcode link parametersThierry Reding2014-06-091-10/+213
| | | | | | | | | | | | | | | The currently hardcoded link parameters don't work on all eDP panels, so compute the parameters at runtime depending on the mode and panel type to allow the driver to cope with a wider variety of panels. Note that the number of bits per pixel of the panel is still hardcoded, but this can be addressed in a separate patch. This is largely based on a patch by Stéphane Marchesin but the algorithm was largely rewritten to be more readable and concise. Signed-off-by: Stéphane Marchesin <marcheu@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: sor - Change power down orderingStéphane Marchesin2014-06-091-1/+1
| | | | | | | | Lanes are powered up in decreasing order. Power them down in increasing order for consistency. Signed-off-by: Stéphane Marchesin <marcheu@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: sor - Fix copy/paste errorStéphane Marchesin2014-06-091-1/+1
| | | | | | | | The comment above mentions link A/B but this isn't what the code does, so let's fix that. Signed-off-by: Stéphane Marchesin <marcheu@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: sor - Remove pixel clock roundingStéphane Marchesin2014-06-091-3/+0
| | | | | | | | | | The code currently rounds up the clock to the next MHZ, which is rounding up a 69.5MHz clock to 70MHz on my machine. This in turn prevents the display from syncing. Removing this rounding fixes eDP for me. Signed-off-by: Stéphane Marchesin <marcheu@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: sor - Make debugfs setup consistentThierry Reding2014-06-061-6/+5
| | | | | | | Other output drivers set up debugfs slightly differently. Bring the SOR driver in line with those for consistency. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: sor - Recursively remove debugfs treeThierry Reding2014-06-061-1/+1
| | | | | | | | Removing only the root directory will fail when there are still files in it. Instead of manually removing all files, remove the whole directory recursively. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dp - Mark the connector as hotplug capableThierry Reding2014-06-051-0/+1
| | | | | | | Doing so allows the hotplug events generated by the connector to be properly handled by the DRM poll helpers. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dp - Implement hotplug detection in work queueThierry Reding2014-06-051-10/+20
| | | | | | | | Calling the drm_helper_hpd_irq_event() helper can sleep, so instead of invoking it directly from the interrupt handler, schedule a work queue and run it from there. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: Add hardware cursor supportThierry Reding2014-06-052-3/+138
| | | | | | | | Enable hardware cursor support on Tegra124. Earlier generations support the hardware cursor to some degree as well, but not in a way that can be generically exposed. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: Remove host1x drm_bus implementationThierry Reding2014-06-0510-96/+52
| | | | | | | The DRM core can now cope with drivers that don't have an associated struct drm_bus, so the host1x implementation is no longer useful. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: gem - Make tegra_bo_import() staticThierry Reding2014-06-051-1/+2
| | | | | | | The function is never used outside of the source file and therefore can be locally scoped. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: hdmi - Add Tegra124 supportThierry Reding2014-06-052-0/+89
| | | | | | | | Tegra124 is mostly backwards-compatible with Tegra114. However, Tegra124 supports a few more features (e.g. interlacing, ...). Introduce a new compatible string and TMDS tables to cope with these differences. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: sor - Protect CRC debugfs against enable stateThierry Reding2014-06-051-24/+45
| | | | | | | | Accessing the CRC debugfs file will hang the system if the SOR is not enabled, so make sure that it is stays enabled until the CRC has been read. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dsi - Do not needlessly recompute pclkThierry Reding2014-06-051-1/+0
| | | | | | | | | In some cases the pixel clock used to not be correct, which is why it had to be recomputed. It turns out that the reason why it wasn't correct is that it was used wrongly. If used correctly there's not need for the recomputation. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dc - Compute shift clock divider in output driversThierry Reding2014-06-056-41/+82
| | | | | | | | The shift clock divider is highly dependent on the type of output, so push computation of it down into the output drivers. The old code used to work merely by accident. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dc - Move around shift clock programmingThierry Reding2014-06-051-9/+10
| | | | | | | Program the shift clock divider in tegra_crtc_setup_clk() since that's where the divider is computed, so passing it around can be avoided. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dsi - Reset controller on driver unloadThierry Reding2014-06-051-0/+1
| | | | | | | | Assert the DSI controller's reset when the driver is unloaded to reduce power consumption and to put the controller into a known state for subsequent driver reloads. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dsi - Fix typo when disabling controllerThierry Reding2014-06-051-1/+1
| | | | | | | When disabling the DSI controller, the code wasn't really doing what it was supposed to. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dsi - Add enable guardThierry Reding2014-06-051-0/+11
| | | | | | | | To prevent the enable or disable operations to potentially be run multiple times, add guards to return early when the output is already in the targetted state. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dsi - Initialize proper packet sequencesThierry Reding2014-06-051-4/+46
| | | | | | | | | The packet sequencer needs to be programmed depending on the video mode of the attached peripheral. Add support for non-burst video modes with sync events (as opposed to sync pulses) and select either sequence depending on the video mode. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dsi - Implement VDD supply supportThierry Reding2014-06-051-0/+17
| | | | | | | | | The DSI controllers are powered by a (typically 1.2V) regulator. Usually this is always on, so there was no need to support enabling or disabling it thus far. But in order not to consume any power when DSI is inactive, give the driver a chance to enable or disable the supply as needed. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dsi - Remove unneeded codeThierry Reding2014-06-051-85/+0
| | | | | | | | A bunch of registers are initialized to 0 upon during driver probe. It turns out that none of these are actually needed, so they can simply be dropped. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dsi - Use internal pixel formatThierry Reding2014-06-052-1/+43
| | | | | | | | The pixel format enumeration values used by the Tegra DSI controller don't match those defined by the DSI framework. Make sure to convert them to the internal format before writing it to the register. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: hdmi - Fix disable sequenceThierry Reding2014-06-051-0/+8
| | | | | | | | | | | For some reason when the PW*_ENABLE and PM*_ENABLE fields are cleared during disable, the HDMI output stops working properly. Resetting and initializing doesn't help. Comment out those accesses for now until it has been determined what to do about them. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: hdmi - Disable LVDS modeThierry Reding2014-06-052-1/+10
| | | | | | | | Disable LVDS mode according to register documentation. It seems like this has no effect on the operation of HDMI, but it's probably a good idea to do this anyway. Signed-off-by: Thierry Reding <treding@nvidia.com>
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