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path: root/drivers/gpu/drm/radeon/si_dpm.c
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* drm/radeon/dpm: drop clk/voltage dependency filters for SIAlex Deucher2014-10-011-24/+0
| | | | | | | | | | | Not sure this was ever necessary for SI, was just done to be on the safe side. bug: https://bugs.freedesktop.org/show_bug.cgi?id=69721 Reviewed-by: Alexandre Demers <alexandre.f.demers@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/dpm: add support for SVI2 voltage for SIAlex Deucher2014-08-051-44/+108
| | | | | | | Some newer boards use SVI2 for voltage control rather than GPIO. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/dpm: powertune updates for SIAlex Deucher2014-06-091-3/+10
| | | | | | Updated powertune settings for certain SI asics. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* Merge branch 'drm-next-3.15' of ↵Dave Airlie2014-02-271-3/+4
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://people.freedesktop.org/~deathsimple/linux into drm-next So this is the initial pull request for radeon drm-next 3.15. Highlights: - VCE bringup including DPM support - Few cleanups for the ring handling code * 'drm-next-3.15' of git://people.freedesktop.org/~deathsimple/linux: drm/radeon: cleanup false positive lockup handling drm/radeon: drop radeon_ring_force_activity drm/radeon: drop drivers copy of the rptr drm/radeon/cik: enable/disable vce cg when encoding v2 drm/radeon: add support for vce 2.0 clock gating drm/radeon/dpm: properly enable/disable vce when vce pg is enabled drm/radeon/dpm: enable dynamic vce state switching v2 drm/radeon: add vce dpm support for KV/KB drm/radeon: enable vce dpm on CI drm/radeon: add vce dpm support for CI drm/radeon: fill in set_vce_clocks for CIK asics drm/radeon/dpm: fetch vce states from the vbios drm/radeon/dpm: fill in some initial vce infrastructure drm/radeon/dpm: move platform caps fetching to a separate function drm/radeon: add callback for setting vce clocks drm/radeon: add VCE version parsing and checking drm/radeon: add VCE ring query drm/radeon: initial VCE support v4 drm/radeon: fix CP semaphores on CIK
| * drm/radeon/dpm: move platform caps fetching to a separate functionAlex Deucher2014-02-181-3/+4
| | | | | | | | | | | | | | It's needed by by both the asic specific functions and the extended table parser. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/radeon/si: fix typo in dpm sq ramping setupAlex Deucher2014-02-181-1/+1
|/ | | | | | | | inverted logic. Noticed-by: Sylvain BERTRAND <sylware@legeek.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
* drm/radeon/dpm: use the driver state for dpm debugfsAlex Deucher2014-02-061-1/+2
| | | | | | | | For btc and newer, we may modify the power state depending on the circumstances. Use the modified state rather than the base state. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: set si_notify_smc_display_change properlyAlex Deucher2014-01-291-3/+2
| | | | | | | | | | | | | | | | | | This is effectively a revert of 4573388c92ee60b4ed72b8d95b73df861189988c. Forcing a display active when there is none causes problems with dpm on some SI boards which results in improperly initialized dpm state and boot failures on some boards. As for the bug commit 4573388c92ee tried to address, one can manually force the state to high for better performance when using the card as a headless compute node until a better fix is developed. bugs: https://bugs.freedesktop.org/show_bug.cgi?id=73788 https://bugs.freedesktop.org/show_bug.cgi?id=69395 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> cc: stable@vger.kernel.org
* drm/radeon: fix minor typos in si_dpm.cAlex Deucher2014-01-201-2/+2
| | | | | | | Copy/paste typos from the ni code. Should not have any functional change. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/pm: move pm handling into the asic specific codeAlex Deucher2013-12-241-0/+7
| | | | | | | | | | | | | | We need more control over the ordering of dpm init with respect to the rest of the asic. Specifically, the SMC has to be initialized before the rlc and cg/pg. The pm code currently initializes late in the driver, but we need it to happen much earlier so move pm handling into the asic specific callbacks. This makes dpm more reliable and makes clockgating work properly on CIK parts and should help on SI parts as well. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/dpm: switch on new late_enable callbackAlex Deucher2013-12-241-15/+0
| | | | | | | | | | Right now it's called right after enable, but after reworking the dpm init order, it will get called later to accomodate loading the smc early, but enabling thermal interrupts and block powergating later after the ring tests are complete. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/dpm: add late_enable for SIAlex Deucher2013-12-241-0/+22
| | | | | | | Make sure interrupts are enabled before we enable thermal interrupts. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/si: drop cg_update from dpm codeAlex Deucher2013-12-241-38/+0
| | | | | | | I'm not entirely sure this is required and it won't work with the dpm restructing anyway. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* Merge tag 'drm-intel-fixes-2013-11-07' of ↵Dave Airlie2013-11-081-3/+3
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://people.freedesktop.org/~danvet/drm-intel into drm-next Bit a bit -fixes pull request in the merge window than usual dua to two feauture-y things: - Display CRCs are now enabled on all platforms, including the odd DP case on gm45/vlv. Since this is a testing-only feature it should ever hurt, but I figured it'll help with regression-testing -fixes. So I left it in and didn't postpone it to 3.14. - Display power well refactoring from Imre. Would have caused major pain conflict with the bdw stage 1 patches if I'd postpone this to -next. It's only an relatively small interface rework, so shouldn't cause pain. It's also been in my tree since almost 3 weeks already. That accounts for about two thirds of the pull, otherwise just bugfixes: - vlv backlight fix from Jesse/Jani - vlv vblank timestamp fix from Jesse - improved edp detection through vbt from Ville (fixes a vlv issue) - eDP vdd fix from Paulo - fixes for dvo lvds on i830M - a few smaller things all over Note: This contains a backmerge of v3.12. Since the -internal branch always applied on top of -nightly I need that unified base to merge bdw patches. So you'll get a conflict with radeon connector props when pulling this (and nouveau/master will also conflict a bit when Ben doesn't rebase). The backmerge itself only had conflicts in drm/i915. There's also a tiny conflict between Jani's backlight fix and your sysfs lifetime fix in drm-next. * tag 'drm-intel-fixes-2013-11-07' of git://people.freedesktop.org/~danvet/drm-intel: (940 commits) drm/i915/vlv: use per-pipe backlight controls v2 drm/i915: make backlight functions take a connector drm/i915: move opregion asle request handling to a work queue drm/i915/vlv: use PIPE_START_VBLANK interrupts on VLV drm/i915: Make intel_dp_is_edp() less specific drm/i915: Give names to the VBT child device type bits drm/i915/vlv: enable HDA display audio for Valleyview2 drm/i915/dvo: call ->mode_set callback only when the port is running drm/i915: avoid unclaimed registers when capturing the error state drm/i915: Enable DP port CRC for the "auto" source on g4x/vlv drm/i915: scramble reset support for DP port CRC on vlv drm/i915: scramble reset support for DP port CRC on g4x drm/i916: add "auto" pipe CRC source ... Conflicts: MAINTAINERS drivers/gpu/drm/i915/intel_panel.c drivers/gpu/drm/nouveau/core/subdev/mc/base.c drivers/gpu/drm/radeon/atombios_encoders.c drivers/gpu/drm/radeon/radeon_connectors.c
| * drm/radeon/dpm: off by one in si_set_mc_special_registers()Dan Carpenter2013-10-091-3/+3
| | | | | | | | | | | | | | | | | | | | These checks should be ">=" instead of ">". j is used as an offset into the table->mc_reg_address[] array and that has SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE (16) elements. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
* | drm/radeon/dpm: fix typo in setting smc flagAlex Deucher2013-11-011-1/+1
| | | | | | | | | | | | | | | | PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH should be set in extraFlags, not systemFlags. Noticed-by: Sylvain BERTRAND <sylware@legeek.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/radeon/si: tell dpm there is a display connectedAlex Deucher2013-11-011-1/+6
|/ | | | | | | | | | | | | | | On SI asics, the SMC will automatically force the performance level to the lowest level if there are no displays active. This prevents automatic performance scaling on PowerXpress systems or for offscreen rendering or compute when displays are disabled. Going forward, it would be best to dynamically change this, but for now leave scaling enabled. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=69395 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/dpm/si: filter clocks based on voltage/clk dep tablesAlex Deucher2013-09-231-0/+24
| | | | | | | | | | | Filter out mclk and sclk levels higher than listed in the clk voltage dependency tables. Supporting these clocks will require additional driver tweaking that isn't supported yet. See bug: https://bugs.freedesktop.org/show_bug.cgi?id=68235 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/dpm: rework auto performance level enableAlex Deucher2013-09-151-6/+0
| | | | | | | | | | | | | Calling force_performance_level() from set_power_state() doesn't work on some asics because the current power state pointer has not been properly updated at that point. Move the calls to force_performance_level() out of the asic specific set_power_state() functions and into the main power state sequence. Fixes dpm resume on SI. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/dpm: make sure dc performance level limits are valid (BTC-SI) (v2)Alex Deucher2013-08-301-0/+6
| | | | | | | | | | | | | | | | Check to make sure the dc limits are valid before using them. Some systems may not have a dc limits table. In that case just use the ac limits. This fixes hangs on systems when the power state is changed when on battery (dc) due to invalid performance state parameters. Should fix: https://bugs.freedesktop.org/show_bug.cgi?id=68708 v2: fix up limits in dpm_init() Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
* drm/radeon: gcc fixes for si dpmAlex Deucher2013-08-301-2/+5
| | | | | | | | | | | | | | Newer versions of gcc seem to wander off into the weeds when dealing with variable sizes arrays in structs. Rather than indexing the arrays, use pointer arithmetic. See bugs: https://bugs.freedesktop.org/show_bug.cgi?id=66932 https://bugs.freedesktop.org/show_bug.cgi?id=66972 https://bugs.freedesktop.org/show_bug.cgi?id=66945 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: handle cg in SI dpm codeAlex Deucher2013-08-301-0/+38
| | | | | | | | Clockgating needs to be disabled around certain parts of dpm setup otherwise the smc gets into a bad state and dpm doesn't work properly. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: add dpm support for CI dGPUs (v2)Alex Deucher2013-08-301-5/+5
| | | | | | | | | | | | | | | This adds dpm support for btc asics. This includes: - dynamic engine clock scaling - dynamic memory clock scaling - dynamic voltage scaling - dynamic pcie gen switching Set radeon.dpm=1 to enable. v2: remove unused radeon_atombios.c changes, make missing smc ucode non-fatal Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: adjust si_dpm function for code sharingAlex Deucher2013-08-301-7/+14
| | | | Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/dpm: adjust power state properly for UVD on SIAlex Deucher2013-08-071-12/+32
| | | | | | | | | There are some hardware issue with reclocking on SI when UVD is active, so use a stable power state when UVD is active. Fixes possible hangs and performance issues when using UVD on SI. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/dpm: fix spread spectrum setup (v2)Alex Deucher2013-08-071-13/+1
| | | | | | | | | | | | | | | | | | Need to check for engine and memory clock ss separately and only enable dynamic ss if either of them are found. This should fix systems which have a ss table, but do not have entries for engine or memory. On those systems we may enable dynamic spread spectrum without enabling it on the engine or memory clocks which can lead to a hang in some cases. fixes some systems reported here: https://bugs.freedesktop.org/show_bug.cgi?id=66963 v2: fix typo Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/dpm: adjust thermal protection requirementsAlex Deucher2013-08-071-2/+1
| | | | | | | | On rv770 and newer, clock gating is not required for thermal protection. The only requirement is that the design utilizes a thermal sensor. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: fix 64 bit divide in SI spm codeAlex Deucher2013-08-041-1/+1
| | | | | | | Forgot to use the appropriate math64 function. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@gmail.com>
* drm/radeon/dpm: re-enable cac control on SIAlex Deucher2013-07-301-2/+1
| | | | | | | Now that the fixed point functions are fixed we can re-enable cac support. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/dpm: fix calculations in si_calculate_leakage_for_v_and_t_formulaAlex Deucher2013-07-301-3/+5
| | | | | | | Need to make some slight adjustments for the fixed point math to work properly. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/dpm: fix and enable reclocking on SIAlex Deucher2013-07-291-10/+4
| | | | | | | | The SMC interface changed compared to Cayman and previous asics. Set the enabled levels properly and enable reclocking by default when dpm is enabled. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/dpm: disable cac setup on SIAlex Deucher2013-07-291-1/+3
| | | | | | | | | | | Disable cac setup on SI for now since it causes strange performance level restrictions on certain cards. I suspect there may be issues with some of the 64 bit fixed point double emulation that is used to set up those parameters. I need to double check the math before this can be re-enabled. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/dpm: fix powertune handling for pci id 0x6835Alex Deucher2013-07-291-0/+1
| | | | | | 0x6835 should be treated as a cape verde pro. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/dpm: fix si_calculate_memory_refresh_rate()Alex Deucher2013-07-291-6/+3
| | | | | | Update alogorithm as per internal advice. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/dpm: fix display gap programming on SIAlex Deucher2013-07-291-1/+5
| | | | | | | Need to set the DISP*_GAP fields as well as the DISP*_GAP_MCHG fields. Same as on previous asics. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/dpm: implement vblank_too_short callback for siAlex Deucher2013-07-081-1/+2
| | | | | | | Check if we can switch the mclk during the vblank time otherwise we may get artifacts on the screen when the mclk changes. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/dpm: implement force performance level for SIAlex Deucher2013-07-051-9/+33
| | | | | | Allows you to force the selected performance level via sysfs. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/dpm: fix compilation with certain versions of gccMike Lothian2013-07-021-0/+1
| | | | | | Add #include <linux/seq_file.h> to *_dpm.c files Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/dpm: add debugfs support for SIAlex Deucher2013-07-011-0/+19
| | | | | | | This allows you to look at the current DPM state via debugfs. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/SI: fix TDP adjustment in set_power_stateAlex Deucher2013-06-271-37/+32
| | | | | | Fixes hangs with DPM in some cases. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/dpm: fix UVD clock setting on SIAlex Deucher2013-06-271-2/+2
| | | | Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/dpm: add dpm_set_power_state failure output (si)Alex Deucher2013-06-271-19/+54
| | | | Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/dpm: add dpm_enable failure output (si)Alex Deucher2013-06-271-14/+42
| | | | Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/kms: add dpm support for SI (v7)Alex Deucher2013-06-271-0/+6329
This adds dpm support for SI asics. This includes: - dynamic engine clock scaling - dynamic memory clock scaling - dynamic voltage scaling - dynamic pcie gen1/gen2/gen3 switching - power containment - shader power scaling Set radeon.dpm=1 to enable. v2: enable hainan support, rebase v3: guard acpi stuff v4: fix 64 bit math v5: fix 64 bit div harder v6: fix thermal interrupt check noticed by Jerome v7: attempt fix state enable Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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