summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/radeon/rv770.c
Commit message (Collapse)AuthorAgeFilesLines
* drm/radeon: consolidate UVD clock programmingChristian König2013-05-021-93/+17
| | | | | | | | Instead of duplicating the code over and over again, just use a single function to handle the clock calculations. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/7xx: add support for golden register initAlex Deucher2013-04-231-0/+652
| | | | Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: put UVD PLLs in bypass modeChristian König2013-04-221-7/+13
| | | | | | | | | Just power down the PLL when we get a VCLK or DCLK of zero. Enabling the bypass mode early should also allow us to switch UVD clocks on the fly. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/kms: replace *REG32_PCIE_P with *REG32_PCIE_PORTAlex Deucher2013-04-091-16/+16
| | | | | | Avoid confusion with the *REG32_P mask macro. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: add UVD tiling addr config v2Christian König2013-04-091-0/+5
| | | | | | | | v2: set UVD tiling config for rv730 Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com>
* drm/radeon: add set_uvd_clocks callback for r7xx v3Christian König2013-04-091-0/+156
| | | | | | | | | v2: avoid 64bit divide v3: rv740 uses the evegreen upll configuration Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com>
* drm/radeon: UVD bringup v8Christian König2013-04-091-0/+132
| | | | | | | | | | | | | Just everything needed to decode videos using UVD. v6: just all the bugfixes and support for R7xx-SI merged in one patch v7: UVD_CGC_GATE is a write only register, lockup detection fix v8: split out VRAM fallback changes, remove support for RV770, add support for HEMLOCK, add buffer sizes checks Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: clean up vram/gtt location handlingAlex Deucher2013-04-091-1/+1
| | | | | | | | | Add a per-asic MC (memory controller) mask which holds the mak address mask the asic is capable of. Use this when calculating the vram and gtt locations rather using asic specific functions or limiting everything to 32 bits. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: add a asic callback to get the xclkAlex Deucher2013-02-201-0/+25
| | | | | | | | | This is required to get the reference clock used by the gfx engine for things like timestamps. Fixes support for GL extensions the use timestamps on certain boards. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: split r6xx and r7xx copy_dma functionsAlex Deucher2013-01-041-0/+74
| | | | | | | | - r6xx actually uses a slightly different packet format, although both formats seem to work ok. - r7xx doesn't have the count multiple of 2 limitation. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/kms: Add initial support for async DMA on r6xx/r7xxAlex Deucher2012-12-101-2/+29
| | | | | | | Uses the new multi-ring infrastucture. 6xx/7xx has a single async DMA ring. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linuxLinus Torvalds2012-10-031-5/+5
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull drm merge (part 1) from Dave Airlie: "So first of all my tree and uapi stuff has a conflict mess, its my fault as the nouveau stuff didn't hit -next as were trying to rebase regressions out of it before we merged. Highlights: - SH mobile modesetting driver and associated helpers - some DRM core documentation - i915 modesetting rework, haswell hdmi, haswell and vlv fixes, write combined pte writing, ilk rc6 support, - nouveau: major driver rework into a hw core driver, makes features like SLI a lot saner to implement, - psb: add eDP/DP support for Cedarview - radeon: 2 layer page tables, async VM pte updates, better PLL selection for > 2 screens, better ACPI interactions The rest is general grab bag of fixes. So why part 1? well I have the exynos pull req which came in a bit late but was waiting for me to do something they shouldn't have and it looks fairly safe, and David Howells has some more header cleanups he'd like me to pull, that seem like a good idea, but I'd like to get this merge out of the way so -next dosen't get blocked." Tons of conflicts mostly due to silly include line changes, but mostly mindless. A few other small semantic conflicts too, noted from Dave's pre-merged branch. * 'drm-next' of git://people.freedesktop.org/~airlied/linux: (447 commits) drm/nv98/crypt: fix fuc build with latest envyas drm/nouveau/devinit: fixup various issues with subdev ctor/init ordering drm/nv41/vm: fix and enable use of "real" pciegart drm/nv44/vm: fix and enable use of "real" pciegart drm/nv04/dmaobj: fixup vm target handling in preparation for nv4x pcie drm/nouveau: store supported dma mask in vmmgr drm/nvc0/ibus: initial implementation of subdev drm/nouveau/therm: add support for fan-control modes drm/nouveau/hwmon: rename pwm0* to pmw1* to follow hwmon's rules drm/nouveau/therm: calculate the pwm divisor on nv50+ drm/nouveau/fan: rewrite the fan tachometer driver to get more precision, faster drm/nouveau/therm: move thermal-related functions to the therm subdev drm/nouveau/bios: parse the pwm divisor from the perf table drm/nouveau/therm: use the EXTDEV table to detect i2c monitoring devices drm/nouveau/therm: rework thermal table parsing drm/nouveau/gpio: expose the PWM/TOGGLE parameter found in the gpio vbios table drm/nouveau: fix pm initialization order drm/nouveau/bios: check that fixed tvdac gpio data is valid before using it drm/nouveau: log channel debug/error messages from client object rather than drm client drm/nouveau: have drm debugging macros build on top of core macros ...
| * drm/radeon: Mark all possible functions / structs as staticLauri Kasanen2012-09-201-5/+5
| | | | | | | | | | | | | | | | | | Let's allow GCC to optimize better. This exposed some five unused functions, but this patch doesn't remove them. Signed-off-by: Lauri Kasanen <cand@gmx.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | UAPI: (Scripted) Convert #include "..." to #include <path/...> in drivers/gpu/David Howells2012-10-021-2/+2
|/ | | | | | | | | | | Convert #include "..." to #include <path/...> in drivers/gpu/. Signed-off-by: David Howells <dhowells@redhat.com> Acked-by: Dave Airlie <airlied@redhat.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com> Acked-by: Dave Jones <davej@redhat.com>
* drm/radeon/kms: auto detect pcie link speed from root portDave Airlie2012-07-191-0/+11
| | | | | | | | | This check the root ports supported link speeds and enables GEN2 mode if the 5.0 GT link speed is available. The first 3.0 cards are SI so they will probably need more investigation. Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/radeon: record what is next valid wptr for each ring v4Christian König2012-07-171-1/+3
| | | | | | | | | | | | | | Before emitting any indirect buffer, emit the offset of the next valid ring content if any. This allow code that want to resume ring to resume ring right after ib that caused GPU lockup. v2: use scratch registers instead of storing it into memory v3: skip over the surface sync for ni and si as well v4: use SET_CONFIG_REG instead of PACKET0 Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: move radeon_ib_ring_tests out of chipset codeChristian König2012-07-171-4/+0
| | | | | | | | Making it easier to control when it is executed. Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: remove r600_blit_suspendChristian König2012-07-171-1/+0
| | | | | | | Just reinitialize the shader content on resume instead. Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: remove ip_pool start/suspendChristian König2012-07-171-11/+6
| | | | | | | | The IB pool is in gart memory, so it is completely superfluous to unpin / repin it on suspend / resume. Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: remove FIXME comment from chipset suspendChristian König2012-07-171-1/+0
| | | | | | | | | | | For a normal suspend/resume we allready wait for the rings to be empty, and for a suspend/reasume in case of a lockup we REALLY don't want to wait for anything. Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: add some additional 6xx/7xx/EG register initAlex Deucher2012-06-161-1/+4
| | | | | | | | | | - SMX_SAR_CTL0 needs to be programmed correctly to prevent problems with memory exports in certain cases. - VC_ENHANCE needs to be initialized on 6xx/7xx. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/radeon: make audio_init consistent across asicsAlex Deucher2012-06-051-12/+6
| | | | | | | | | | | Call it in the asic startup callback on all asics. Previously r600 and rv770 called it in the startup and resume callbacks while all the other asics called it in the startup callback. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/radeon: fixup tiling group size and backendmap on r6xx-r9xx (v4)Alex Deucher2012-06-011-216/+48
| | | | | | | | | | | | | | | | | Tiling group size is always 256bits on r6xx/r7xx/r8xx/9xx. Also fix and simplify render backend map. This now properly sets up the backend map on r6xx-9xx which should improve 3D performance. Vadim benchmarked also: Some benchmarks on juniper (5750), fullscreen 1920x1080, first result - kernel 3.4.0+ (fb21affa), second - with these patches: Lightsmark: 91 fps => 123 fps +35% Doom3: 74 fps => 101 fps +36% Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/radeon: properly program gart on rv740, juniper, cypress, barts, hemlockAlex Deucher2012-06-011-0/+2
| | | | | | | | | | | Need to program an additional VM register. This doesn't not currently cause any problems, but allows us to program the proper backend map in a subsequent patch which should improve performance on these asics. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/radeon: fix bank information in tiling configAlex Deucher2012-06-011-2/+6
| | | | | | | | | | | | | While there are cards with more than 8 mem banks, the max number of banks from a tiling perspective is 8, so cap the tiling config at 8 banks. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=43448 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/radeon: make use of radeon_gem_init() consistentAlex Deucher2012-05-171-4/+0
| | | | | | | | | | | | | | | | All radeon_gem_init() does is initialize the gem objects list. radeon_device.c does this explicitly. r600+ calls radeon_gem_init() so the list gets initialized twice. Older asics don't call it at all and rely on the the init in radeon_device.c. Just call radeon_gem_init() in radeon_device.c and remove the explicit calls from all the newer asics. All asics call radeon_gem_fini() in their fini pathes. That could possibly be cleaned up too. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/radeon: simplify semaphore handling v2Jerome Glisse2012-05-091-1/+0
| | | | | | | | | | | Directly use the suballocator to get small chunks of memory. It's equally fast and doesn't crash when we encounter a GPU reset. v2: rebased on new SA interface. Signed-off-by: Christian König <deathsimple@vodafone.de> Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* Merge branch 'for-airlied' of git://people.freedesktop.org/~danvet/drm-intel ↵Dave Airlie2012-05-071-2/+2
|\ | | | | | | | | | | | | into drm-core-next Daniel prepared this branch with a back-merge as git was getting very confused about changes in intel_display.c
| * radeon: fix r600/agp when vram is after AGP (v3)Jerome Glisse2012-04-191-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | If AGP is placed in the middle, the size_af is off-by-one, it results in VRAM being placed at 0x7fffffff instead of 0x8000000. v2: fix the vram_start setup. v3: also fix r7xx & newer ASIC Reported-by: russiane39 on #radeon Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* | drm/radeon: use central function for IB testingChristian König2012-05-031-5/+2
|/ | | | | | | | | | | Removing all the different error messages and having just one standard behaviour over all chipset generations. Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm: Merge tag 'v3.3-rc7' into drm-core-nextDave Airlie2012-03-151-0/+1
|\ | | | | | | | | | | | | | | Merge the fixes so far into core-next, needed to test intel driver. Conflicts: drivers/gpu/drm/i915/intel_ringbuffer.c
| * drm/radeon/kms: properly set accel working flag and bailout when falseJerome Glisse2012-02-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | If accel is not working many subsystem such as the ib pool might not be initialized properly that can lead to segfault inside kernel when cs ioctl is call with non working acceleration. To avoid this make sure the accel working flag is false when an error in GPU startup happen and return EBUSY from cs ioctl if accel is not working. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* | drm/radeon/kms: make ring_start, ring_test, and ib_test per ringAlex Deucher2012-02-291-1/+1
| | | | | | | | | | | | | | | | | | | | Each ring type may need a different variant. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König<christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* | drm/radeon/kms: reorganize copy callbacksAlex Deucher2012-02-291-1/+1
|/ | | | | | | | | | | tidy up the radeon_asic struct, handle multiple rings better. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König<christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/radeon: introduce a sub allocator and convert ib pool to it v4Jerome Glisse2011-12-201-21/+22
| | | | | | | | | | | | | | | | | Somewhat specializaed sub-allocator designed to perform sub-allocation for command buffer not only for current cs ioctl but for future command submission ioctl as well. Patch also convert current ib pool to use the sub allocator. Idea is that ib poll buffer can be share with other command buffer submission not having 64K granularity. v2 Harmonize pool handling and add suspend/resume callback to pin/unpin sa bo (tested on rv280, rv370, r420, rv515, rv610, rv710, redwood, cayman, rs480, rs690, rs880) v3 Simplify allocator v4 Fix radeon_ib_get error path to properly free fence Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/radeon/kms: add some new ring params to better handle other ring typesAlex Deucher2011-12-201-1/+2
| | | | | | | | | Some rptr/wptrs fields have different offsets and not all rings are pm4 so add a new nop field. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Christian König <deathsimple@vodafone.de> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/radeon: precompute fence cpu/gpu addr once v3Jerome Glisse2011-12-201-1/+7
| | | | | | | | | | | | | | | | | | | | | | Add a start fence driver helper function which will be call once for each ring and will compute cpu/gpu addr for fence depending on wether to use wb buffer or scratch reg. This patch replace initialize fence driver separately which was broken in regard of GPU lockup. The fence list for created, emited, signaled must be initialize once and only from the asic init callback not from the startup call back which is call from the gpu reset. v2: With this in place we no longer need to know the number of rings in fence_driver_init, also writing to the scratch reg before knowing its offset is a bad idea. v3: rebase on top of change to previous patch in the serie Signed-off-by: Christian König <deathsimple@vodafone.de> Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/radeon: rename struct radeon_cp to radeon_ringChristian König2011-12-201-6/+6
| | | | | | | | | That naming seems to make more sense, since we not only want to run PM4 rings with it. Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/radeon: make cp variable an arrayChristian König2011-12-201-5/+5
| | | | | | | | | Replace cp, cp1 and cp2 members with just an array of radeon_cp structs. Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/radeon: make ring rptr and wptr register offsets variableChristian König2011-12-201-1/+2
| | | | | | | | | | Every ring seems to have the concept of read and write pointers. Make the register offset variable so we can use the functions for different types of rings. Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/radeon: make all functions work with multiple rings.Christian König2011-12-201-5/+6
| | | | | | | | | Give all asic and radeon_ring_* functions a radeon_cp parameter, so they know the ring to work with. Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/radeon/kms: add support for semaphores v3Christian König2011-12-201-0/+1
| | | | | | | | | | | | | | | They are used to sync between rings, while fences sync between a ring and the cpu. v2 Fix radeon_semaphore_driver_fini when no semaphore were allocated. v3 Initialize list early on to avoid issue in case or early error Signed-off-by: Christian König <deathsimple@vodafone.de> Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/radeon/kms: add support for multiple fence queues v2Alex Deucher2011-12-201-1/+1
| | | | | | | | | | | | | | For supporting multiple CP ring buffers, async DMA engines and UVD. We still need a way to synchronize between engines. v2 initialize unused fence driver ring to avoid issue in suspend/unload Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/radeon/kms: add some loop timeouts in pageflip codeAlex Deucher2011-12-011-1/+6
| | | | | | | | | | | | | | Avoid infinite loops waiting for surface updates if a GPU reset happens while waiting for a page flip. See: https://bugs.freedesktop.org/show_bug.cgi?id=43191 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@kernel.org Reviewed-by: Mario Kleiner <mario.kleiner@tuebingen.mpg.de> Tested-by: Simon Farnsworth <simon.farnsworth@onelan.co.uk> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/radeon/kms: consolidate GART code, fix segfault after GPU lockup V2Jerome Glisse2011-11-041-10/+3
| | | | | | | | | | | | | | After GPU lockup VRAM gart table is unpinned and thus its pointer becomes unvalid. This patch move the unpin code to a common helper function and set pointer to NULL so that page update code can check if it should update GPU page table or not. That way bo still bound to GART can be unbound (pci_unmap_page for all there page) properly while there is no need to update the GPU page table. V2 move the test for null gart out of the loop, small optimization Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/radeon/kms: allocate vram scratch page on 6xx+Alex Deucher2011-11-011-53/+7
| | | | | | | | | | | The vram scratch was originally only used on some 7xx asics to work around a hw bug. Allocate the scratch page on all 6xx+ radeons and set the MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR to point to it. We shouldn't ever hit it since we limit the system aperture to vram or vram and AGP, but better safe than sorry. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* Merge tag 'v3.1-rc10' into drm-core-nextDave Airlie2011-10-181-51/+0
|\ | | | | | | | | | | | | | | | | | | | | | | There are a number of fixes in mainline required for code in -next, also there was a few conflicts I'd rather resolve myself. Signed-off-by: Dave Airlie <airlied@redhat.com> Conflicts: drivers/gpu/drm/radeon/evergreen.c drivers/gpu/drm/radeon/r600.c drivers/gpu/drm/radeon/radeon_asic.h
| * drm/radeon/kms: fix channel_remap setup (v2)Alex Deucher2011-10-041-51/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most asics just use the hw default value which requires no explicit programming. For those that need a different value, the vbios will program it properly. As such, there's no need to program these registers explicitly in the driver. Changing MC_SHARED_CHREMAP requires a reload of all data in vram otherwise its contents will be scambled. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=40103 v2: drop now unused channel_remap functions. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Cc: stable@kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
* | drm/radeon/kms: make r600-NI blit suspend code commonAlex Deucher2011-10-181-10/+2
| | | | | | | | | | | | | | | | | | r600-NI shared the same blit suspend code. Clean it up and make it a shared function. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Ilija Hadzic <ihadzic@research.bell-labs.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* | drm/radeon: Print gart initialization details on all chipsetsTormod Volden2011-09-061-0/+3
|/ | | | | | | | | | | This was previously done for r300 only. Use %016llX instead of %08X for printing the table address. Also fix typos in gart warning messages. Signed-off-by: Tormod Volden <debian.tormod@gmail.com> Reviewed-by: Michel Dänzer <michel@daenzer.net> Signed-off-by: Dave Airlie <airlied@redhat.com>
OpenPOWER on IntegriCloud