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path: root/drivers/gpu/drm/radeon/atombios_crtc.c
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* Revert "drm/radeon: rework pll selection (v3)"Alex Deucher2012-09-171-129/+34
| | | | | | | | | | | This reverts commit 985f61f7ee647ad570c05eab0b74915da2ac8e19. This commit fixed certain cases, but ended up regressing others due to limitations in the current KMS API. A proper fix is too invasive for 3.6. Push it back to 3.7. Reported-by: Andres Freund <andres@anarazel.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: rework pll selection (v3)Alex Deucher2012-09-131-34/+129
| | | | | | | | | | | | | | | | | | | | For DP we can use the same PPLL for all active DP encoders. Take advantage of that to prevent cases where we may end up sharing a PPLL between DP and non-DP which won't work. Also clean up the code a bit. v2: - fix missing pll_id assignment in crtc init v3: - fix DP PPLL check - document functions - break in main encoder search loop after matching. no need to keep checking additional encoders. fixes: https://bugs.freedesktop.org/show_bug.cgi?id=54471 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
* drm/radeon/atom: powergating fixes for DCE6Alex Deucher2012-08-291-20/+2
| | | | | | | | | | | | | Power gating is per crtc pair, but the powergating registers should be called individually. The hw handles power up/down properly. The pair is powered up if either crtc in the pair is powered up and the pair is not powered down until both crtcs in the pair are powered down. This simplifies programming and should save additional power as the previous code never actually power gated the crtc pair. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
* drm/radeon: don't disable plls that are in use by other crtcsAlex Deucher2012-08-291-0/+14
| | | | | | | | Some plls are shared for DP. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* drm/radeon/ss: use num_crtc rather than hardcoded 6Alex Deucher2012-08-211-1/+1
| | | | | | | When checking if a pll is in use. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
* drm/radeon: avoid turning off spread spectrum for used pllJerome Glisse2012-08-201-4/+21
| | | | | | | | | | | If spread spectrum is enabled and in use for a given pll we should not turn it off as it will lead to turning off display for crtc that use the pll (this behavior was observed on chelsea edp). Signed-off-by: Jerome Glisse <jglisse@redhat.com> Cc: stable@vger.kernel.org Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: fix ordering in pll picking on dce4+Alex Deucher2012-08-131-4/+4
| | | | | | | | | No functional change, but re-order the cases so they evaluate properly due to the way the DCE macros work. Noticed by kallisti5 on IRC. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: properly handle crtc powergatingAlex Deucher2012-08-131-2/+12
| | | | | | | | | | | | Need to make sure the crtc is gated on before modesetting. Explicitly gate the crtc on in prepare() and set a flag so that the dpms functions don't gate it off during mode set. Noticed by sylware on IRC. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
* drm: Make the .mode_fixup() operations mode argument a const pointerLaurent Pinchart2012-07-191-1/+1
| | | | | | | | The passed mode must not be modified by the operation, make it const. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/radeon: fix SS setup for DCPLLAlex Deucher2012-07-181-12/+4
| | | | | | | Need to actually set the SS parameters rather than just 0. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
* drm/radeon: fix up pll selection on DCE5/6Alex Deucher2012-07-181-1/+5
| | | | | | | | | | | Selecting ATOM_PPLL_INVALID should be equivalent as the DCPLL or PPLL0 are already programmed for the DISPCLK, but the preferred method is to always specify the PLL selected. SetPixelClock will check the parameters and skip the programming if the PLL is already set up. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
* drm/radeon: SI tiling fixes for displayAlex Deucher2012-06-201-1/+9
| | | | | | | | | - Use the correct union for getting the tiling info - Properly init the PIPE_CONFIG field for SI Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* Merge tag 'v3.4-rc6' into drm-intel-nextDaniel Vetter2012-05-071-2/+5
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: drivers/gpu/drm/i915/intel_display.c Ok, this is a fun story of git totally messing things up. There /shouldn't/ be any conflict in here, because the fixes in -rc6 do only touch functions that have not been changed in -next. The offending commits in drm-next are 14415745b2..1fa611065 which simply move a few functions from intel_display.c to intel_pm.c. The problem seems to be that git diff gets completely confused: $ git diff 14415745b2..1fa611065 is a nice mess in intel_display.c, and the diff leaks into totally unrelated functions, whereas $git diff --minimal 14415745b2..1fa611065 is exactly what we want. Unfortunately there seems to be no way to teach similar smarts to the merge diff and conflict generation code, because with the minimal diff there really shouldn't be any conflicts. For added hilarity, every time something in that area changes the + and - lines in the diff move around like crazy, again resulting in new conflicts. So I fear this mess will stay with us for a little longer (and might result in another backmerge down the road). Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/radeon/kms: need to set up ss on DP bridges as wellAlex Deucher2012-04-281-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Makes Nutmeg DP to VGA bridges work for me. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=42490 Noticed by Jerome Glisse (after weeks of debugging). Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
| * drm/radeon/kms: use frac fb div on APUsAlex Deucher2012-04-271-0/+3
| | | | | | | | | | | | | | | | | | | | | | Seems to be more stable on certain monitors. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=48880 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
* | drm/radeon/kms: improve bpc handling (v2)Alex Deucher2012-04-241-5/+2
|/ | | | | | | | | | | Improve handling of bpc (bits per color) in radeon. In most cases we want 8 except for HDMI, DP, LVDS, and eDP. v2: handle DP better. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Tested-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/radeon/kms/atom: force bpc to 8 for nowAlex Deucher2012-03-261-3/+5
| | | | | | | | | | | Using the bpc (bits per color) specified by the monitor can cause problems in some cases. Until we get a better handle on how to deal with those cases, just use a bpc of 8. Reported-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/radeon/kms/DCE6.1: ss is not supported on the internal ppllsAlex Deucher2012-03-211-1/+1
| | | | | | | | It's handled via external clock. It should already be protected by the external ss flag, but add an explicit check just in case. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/radeon/kms: disable PPLL0 on DCE6.1 when not in useAlex Deucher2012-03-211-0/+8
| | | | | Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/radeon/kms: Adjust pll picker for DCE6.1Alex Deucher2012-03-211-1/+30
| | | | | | | | On TN, UNIPHYA always uses PPLL2, UNIPHYB/C/D/E/F can use either PPLL1 or PPLL0. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/radeon/kms: DCE6.1 disp eng pll updatesAlex Deucher2012-03-211-1/+3
| | | | | | | DCE6.1 uses EXT_PLL1 for disp eng. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/radeon/kms: DCE6 disp eng pll updatesAlex Deucher2012-03-211-5/+10
| | | | | | | | Rename the function to better match the functionality. DCPLL became PLL0 on DCE6. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/radeon/kms/atom: add support for crtc power gatingAlex Deucher2012-03-211-0/+38
| | | | | | | | | Each pair of crtcs (0/1, 2/3, 4/5) can be power gated. Make sure the power is applied when the crtc is in use and only power down the pair when both are off. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/radeon/kms/atom: DCE6 no longer has crtcmemreq bitsAlex Deucher2012-03-211-2/+2
| | | | | | | The hw no longer has the bits and the table is removed. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/radeon: add support for evergreen/ni tiling informations v11Jerome Glisse2012-02-131-13/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | evergreen and northern island gpu needs more informations for 2D tiling than previous r6xx/r7xx. Add field to tiling ioctl to allow userspace to provide those. The v8 cs checking change to track color view on r6xx/r7xx doesn't affect old userspace as old userspace always emited 0 for this register. v2 fix r6xx/r7xx 2D tiling computation v3 fix r6xx/r7xx height align for untiled surface & add support for tile split on evergreen and newer v4 improve tiling debugging output v5 fix tile split code for evergreen and newer v6 set proper tile split for crtc register v7 fix tile split limit value v8 add COLOR_VIEW checking to r6xx/r7xx checker, add evergreen cs checking, update safe reg for r600, evergreen and cayman. Evergreen checking need some work around for stencil alignment issues v9 fix tile split value range, fix compressed texture handling and mipmap calculation, allow evergreen check to be silencious in front of current broken userspace (depth/stencil alignment issue) v10 fix eg 3d texture and compressed texture, fix r600 depth array, fix r600 color view computation, add support for evergreen stencil split v11 more verbose debugging in some case Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/radeon: Set DESKTOP_HEIGHT register to the framebuffer (not mode) height.Michel Dänzer2012-02-011-2/+2
| | | | | | | | | | | | | | | | | | The value of this register is transferred to the V_COUNTER register at the beginning of vertical blank. V_COUNTER is the reference for VLINE waits and goes from VIEWPORT_Y_START to VIEWPORT_Y_START+VIEWPORT_HEIGHT during scanout, so if VIEWPORT_Y_START is not 0, V_COUNTER actually went backwards at the beginning of vertical blank, and VLINE waits excluding the whole scanout area could never finish (possibly only if VIEWPORT_Y_START is larger than the length of vertical blank in scanlines). Setting DESKTOP_HEIGHT to the framebuffer height should prevent this for any kind of VLINE wait. Fixes https://bugs.freedesktop.org/show_bug.cgi?id=45329 . CC: stable@vger.kernel.org Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/radeon/kms: refine TMDS dual link checksAlex Deucher2012-01-241-1/+3
| | | | | | | | | | | | | HDMI 1.3 defines single link clocks up to 340 Mhz. Refine the current dual link checks to only enable dual link for DVI > 165 Mhz or HDMI > 340 Mhz if the hw supports HDMI 1.3 (DCE3+). Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=44755 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/radeon/kms: move disp eng pll setup to init pathAlex Deucher2012-01-241-29/+27
| | | | | | | | We really only need to set it up once on init or resume rather than on every mode set. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/radeon/kms: don't use 0 bpc for adjusting hdmi clockDave Airlie2011-12-201-1/+1
| | | | | | | | | | | | | | | If the bpc is set from the connector is 0, we then use it later to adjust in a special case the HDMI pixel clock, however if the bpc is 0, we end up passing a 0 pixel clock into the code. I'm not sure if this is the correct answer or if we should avoid the HDMI clock adjustment for 0 values. This fixes a divide by 0 on my Llano system with a HDMI monitor and hdmi audio enabled. Reviewed-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* Merge tag 'v3.2-rc6' of /home/airlied/devel/kernel/linux-2.6 into drm-core-nextDave Airlie2011-12-201-8/+33
|\ | | | | | | | | | | | | | | Merge in the upstream tree to bring in the mainline fixes. Conflicts: drivers/gpu/drm/exynos/exynos_drm_fbdev.c drivers/gpu/drm/nouveau/nouveau_sgdma.c
| * drm/radeon/kms: fix scanout of 2D tiled buffers on EG/CMAlex Deucher2011-12-021-2/+33
| | | | | | | | | | | | | | | | Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=43191 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
| * drm/radeon/kms: remove extraneous calls to radeon_pm_compute_clocks()Alex Deucher2011-11-111-6/+0
| | | | | | | | | | | | | | It's already called via the DPMS functions. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* | drm: Replace pitch with pitches[] in drm_framebufferVille Syrjälä2011-12-201-2/+2
|/ | | | | | | | | | Otherwise each driver would need to keep the information inside their own framebuffer object structure. Also add offsets[]. BOs on the other hand are driver specific, so those can be kept in driver specific structures. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/radeon/kms: check for DP MST mode in a few more places (v2)Alex Deucher2011-11-011-2/+3
| | | | | | | | | DP MST is DP multi-stream support, part of DP 1.2. v2: switch to a helper macro as suggested by Michel. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/radeon/kms: rework DP bridge checksAlex Deucher2011-11-011-6/+6
| | | | | | | | Return the encoder id rather than a boolean. This is needed for differentiate between multiple DP bridge chips. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/radeon/kms: cleanup atombios_adjust_pll()Alex Deucher2011-11-011-28/+13
| | | | | | | The logic was messy and hard to follow. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/radeon/kms/DCE4.1: ss is not supported on the internal ppllsAlex Deucher2011-10-181-1/+1
| | | | | | | | It's handled via external clock. It should already be protected by the external ss flag, but add an explicit check just in case. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/radeon: ATOM Endian fix for atombios_crtc_program_pll()Benjamin Herrenschmidt2011-07-251-3/+2
| | | | | | | | | | | | | | v6 of the structure was programmed incorrectly: args.v6.ulCrtcPclkFreq.ulPixelClock = cpu_to_le32(clock / 10); ulPixelClock is a 24-bit bitfield. This statement would thus do a 32-bit swap of (clock / 10) and drop the top 8 bits which are ... the LSB. Not what we want. Instead use masks & shifts. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/radeon/kms/atom: AdjustPixelClock fixes for DP bridgesAlex Deucher2011-06-171-0/+7
| | | | | | | | Need to set the external transmitter type properly in AdjustPixelClock to get the properly output. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/radeon/kms: viewport height has to be evenAlex Deucher2011-06-021-4/+8
| | | | | | | | | | Otherwise, no vblank interrupts. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=37522 Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Cc: stable@kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/radeon/kms: fix typo in spread spectrum codeAlex Deucher2011-05-241-1/+1
| | | | | Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/radeon/kms: the SS_Id field in the LCD table if for LVDS onlyAlex Deucher2011-05-221-30/+12
| | | | | | | For DP/eDP, always use the standard DP SS indices. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@gmail.com>
* drm/radeon/kms: properly set the CLK_REF bit for DCE3 devicesAlex Deucher2011-05-221-0/+2
| | | | | | | | | If the ss clock is external, the CLK_REF bit needs to be set in the SetPixelClock parameters. This should fix DP failures in the channel equalization loop. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@gmail.com>
* drm/radeon/kms: handle DP bridgesAlex Deucher2011-05-201-2/+4
| | | | | | | | | Fusion hardware often has DP to VGA/LVDS/TMDS bridges to handle non-DP encoders. Internally we treat them mostly like DP. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/radeon/kms: fix up DP clock programming on DCE4/5Alex Deucher2011-05-201-2/+10
| | | | | | | | | | | | | | | | In DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock, depending on the asic. The crtc virtual pixel clock is derived from the DP ref clock. - DCE4: PPLL or ext clock - DCE5: DCPLL or ext clock Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip PPLL/DCPLL programming and only program the DP DTO for the crtc virtual pixel clock. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/radeon/kms: spread spectrum fixesAlex Deucher2011-05-201-16/+36
| | | | | | | | | | | - properly mask the ss type - don't enable ss if type is external or percentage is 0 - if ss enabled and type is external, set ref_div_src to ext clock - prefer ASIC_INTERNAL_SS_ON_DP to LCD_Info SS_Id for eDP - fix ss amount calculation Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/radeon/kms: properly handle bpc >8 in atom command tablesAlex Deucher2011-05-201-4/+34
| | | | | Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/radeon/kms: pll tweaks for r7xxAlex Deucher2011-04-201-5/+1
| | | | | | | | | | | Prefer min m to max p only on pre-r7xx asics. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=36197 Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Cc: stable@kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/radeon/kms: pll tweaks for rv6xxAlex Deucher2011-04-091-0/+6
| | | | | | | | | | | Prefer minm over maxp. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=35994 Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Cc: stable@kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/radeon/kms: pageflipping cleanup for avivo+Alex Deucher2011-04-041-0/+20
| | | | | | | | | | | | | | Avoid touching the flip setup regs while acceleration is running. Set them at modeset rather than during pageflip. Touching these regs while acceleration is active caused hangs on pre-avivo chips. These chips do not seem to be affected, but better safe than sorry, plus it avoids repeatedly reprogramming the regs every flip. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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