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path: root/drivers/gpu/drm/nouveau/nvc0_fb.c
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* drm/nouveau: restructure source tree, split core from drm implementationBen Skeggs2012-10-031-135/+0
| | | | | | | | | | | | | | Future work will be headed in the way of separating the policy supplied by the nouveau drm module from the mechanisms provided by the driver core. There will be a couple of major classes (subdev, engine) of driver modules that have clearly defined tasks, and the further directory structure change is to reflect this. No code changes here whatsoever, aside from fixing up a couple of include file pathnames. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nvc0/ltcg: mask off intr 0x10Ben Skeggs2012-09-261-0/+1
| | | | | | | | | | | | | | NVIDIA do that at startup too on Fermi, so perhaps the heap of 0x10 intrs we receive are normal and we can ignore them. On Kepler NVIDIA *don't* do this, but the hardware appears to come up with the bit masked off by default - so that's probably why :) This should silence some interrupt spam seen on Fermi+ boards. Backported patch from reworked nouveau kernel tree. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* nvc0/fb: shut up PMFB interrupt after the first occurrenceChristoph Bumiller2012-04-301-0/+5
| | | | | Signed-off-by: Christoph Bumiller <e0425955@student.tuwien.ac.at> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nvc0/fb: slightly improve PMFB intr handling, move out of nvc0_graph.cBen Skeggs2011-09-201-0/+27
| | | | | | | I'm still not certain how to determine the number of SUBPs are present on a given board. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nvc0/fb: allocate page for some unknown PFFB objectBen Skeggs2011-06-231-2/+66
| | | | | | | Fixes DMAR faults during accel, more than likely a similar problem to what was solved on nv50 previously. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nvc0: starting point for GF100 support, everything stubbedBen Skeggs2010-08-061-0/+38
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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