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* drm/nouveau: s/mem/reg/ for struct ttm_mem_reg variablesBen Skeggs2017-02-171-6/+6
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: allocate device object for every clientBen Skeggs2017-02-171-1/+1
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: rename nouveau_drm.h to nouveau_drv.hBen Skeggs2016-05-201-1/+1
| | | | | | | Fixes out-of-tree build issue where uapi/drm/nouveau_drm.h gets picked up instead. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: finalise nvkm namespace switch (no binary change)Ben Skeggs2015-01-221-5/+5
| | | | | | | | | | | | | | | | The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: sgdma: add comment around suspiscious error handlerAlexandre Courbot2015-01-221-0/+5
| | | | | | | | | | | | Common programming sense dictates that resources allocated by a function are freed by this function should it fails, but this is not the case for the allocated structure of nouveau_sgdma_create_ttm(). It seems that n00b contributors attempt to fix this one like bugs flying towards a bug zapper, so add a comment to hopefully prevent this from happening anymore. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: sgdma: remove unused nouveau_sgdma_be::devAlexandre Courbot2015-01-221-2/+0
| | | | | | | | nouveau_sgdma_be::dev is only set once during init and never used anywhere, so remove it. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: port to nvif client/device/objectsBen Skeggs2014-08-101-2/+0
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: initial pass at moving to struct nvif_deviceBen Skeggs2014-08-101-1/+1
| | | | | | | This is an attempt at isolating some of the changes necessary to port to NVIF in a separate commit. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/vm: reduce number of entry-points to vm_map()Ben Skeggs2014-01-231-6/+11
| | | | | | | | Pretty much everywhere had to make the decision which to use, so it makes a lot more sense to just have one entrypoint decide the path to take instead. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/ttm: prevent double-free in nouveau_sgdma_create_ttm() failure pathBen Skeggs2013-09-181-3/+1
| | | | | | TTM calls the destructor on its own already... Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: port all engines to new engine module formatBen Skeggs2012-10-031-58/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a HUGE commit, but it's not nearly as bad as it looks - any problems can be isolated to a particular chipset and engine combination. It was simply too difficult to port each one at a time, the compat layers are *already* ridiculous. Most of the changes here are simply to the glue, the process for each of the engine modules was to start with a standard skeleton and copy+paste the old code into the appropriate places, fixing up variable names etc as needed. v2: Marcin Slusarz <marcin.slusarz@gmail.com> - fix find/replace bug in license header v3: Ben Skeggs <bskeggs@redhat.com> - bump indirect pushbuf size to 8KiB, 4KiB barely enough for userspace and left no space for kernel's requirements during GEM pushbuf submission. - fix duplicate assignments noticed by clang v4: Marcin Slusarz <marcin.slusarz@gmail.com> - add sparse annotations to nv04_fifo_pause/nv04_fifo_start - use ioread32_native/iowrite32_native for fifo control registers v5: Ben Skeggs <bskeggs@redhat.com> - rebase on v3.6-rc4, modified to keep copy engine fix intact - nv10/fence: unmap fence bo before destroying - fixed fermi regression when using nvidia gr fuc - fixed typo in supported dma_mask checking Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/instmem: completely new implementation, as a subdev moduleBen Skeggs2012-10-031-301/+14
| | | | | | | | v2 (Ben Skeggs): - some fixes for 64KiB PAGE_SIZE - fix porting issues in (currently unused) nv41/nv44 pciegart code Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: give a slightly larger pci(e)gart aperture on all chipsetsBen Skeggs2012-05-241-2/+2
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* nouveau: add PRIME supportDave Airlie2012-05-231-1/+4
| | | | | | | | | | | | This adds prime->fd and fd->prime support to nouveau, it passes the SG object to TTM, and then populates the GART entries using it. v2: add stubbed kmap + use new function to fill out pages array for faulting + add reimport test. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/ttm: isolate dma data from ttm_tt V4Jerome Glisse2011-12-061-8/+14
| | | | | | | | | | | | | | Move dma data to a superset ttm_dma_tt structure which herit from ttm_tt. This allow driver that don't use dma functionalities to not have to waste memory for it. V2 Rebase on top of no memory account changes (where/when is my delorean when i need it ?) V3 Make sure page list is initialized empty V4 typo/syntax fixes Signed-off-by: Jerome Glisse <jglisse@redhat.com> Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com>
* drm/nouveau: enable the ttm dma pool when swiotlb is active V3Konrad Rzeszutek Wilk2011-12-061-59/+1
| | | | | | | | | | | | | | | | | | If the card is capable of more than 32-bit, then use the default TTM page pool code which allocates from anywhere in the memory. Note: If the 'ttm.no_dma' parameter is set, the override is ignored and the default TTM pool is used. V2 use pci_set_consistent_dma_mask V3 Rebase on top of no memory account changes (where/when is my delorean when i need it ?) CC: Ben Skeggs <bskeggs@redhat.com> CC: Francisco Jerez <currojerez@riseup.net> CC: Dave Airlie <airlied@redhat.com> Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com>
* drm/ttm: merge ttm_backend and ttm_tt V5Jerome Glisse2011-12-061-103/+85
| | | | | | | | | | | | | | | | | ttm_backend will only exist with a ttm_tt, and ttm_tt will only be of interest when bound to a backend. Merge them to avoid code and data duplication. V2 Rebase on top of memory accounting overhaul V3 Rebase on top of more memory accounting changes V4 Rebase on top of no memory account changes (where/when is my delorean when i need it ?) V5 make sure ttm is unbound before destroying, change commit message on suggestion from Tormod Volden Signed-off-by: Jerome Glisse <jglisse@redhat.com> Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com>
* drm/nouveau: remove allocations from gart populate() hookBen Skeggs2011-09-201-45/+21
| | | | | | | | | | | | | | | Since some somewhat questionable changes a while back, TTM provides a completely empty array of struct dma_address that stays around for the entire lifetime of the TTM object. Lets use this array, *always*, rather than wasting yet more memory on another array who's purpose is identical, as well as yet another bool array of the same size saying *which* of the previous two arrays to use... This change will also solve the high order allocation failures seen by some people while using nouveau. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: fix nv04_sgdma_bind on non-"4kB pages" archsMarcin Slusarz2011-09-091-1/+1
| | | | | | | | | nv04_sgdma_bind binds the same page multiple times on architectures where PAGE_SIZE != 4096. Let's fix it. Signed-off-by: Marcin Slusarz <marcin.slusarz@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: properly handle allocation failure in nouveau_sgdma_populateMarcin Slusarz2011-09-091-1/+4
| | | | | | | | | | Not cleaning after alloc failure would result in crash on destroy, because nouveau_sgdma_clear assumes "ttm_alloced" to be not null when "pages" is not null. Signed-off-by: Marcin Slusarz <marcin.slusarz@gmail.com> Cc: stable@kernel.org Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* DRM: remove drm_pci_device_is_pcieJon Mason2011-07-131-2/+2
| | | | | | | | | | | | drm_pci_device_is_pcie duplicates the funcationality of pci_is_pcie. Convert callers of the former to the latter. This has the side benefit of removing an unnecessary search in the PCI configuration space due to using a saved PCIe capability offset. [airlied: update for new callsite] Signed-off-by: Jon Mason <jdmason@kudzu.us> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/nv40: fall back to paged dma object for the momentBen Skeggs2011-06-071-1/+1
| | | | | | | PCI(E)GART isn't quite stable it seems, fall back to old method until I get the time to sort it out properly. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/radeon/nouveau: fix build regression on alpha due to Xen changes.Dave Airlie2011-05-111-1/+2
| | | | | | | | | | | | | | The Xen changes were using DMA_ERROR_CODE which isn't defined on a few platforms, however we reverted the Xen patch that caused use to try and use this code path earlier in 2.6.39 cycle, so for now lets just force the code to never take this path and allow it to build again on alpha. The proper long term answer is probably to store if the dma_addr has been assigned to alongside the dma_addr in the higher level code, though I think Thomas wanted to rewrite most of this anyways properly. Acked-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/nouveau: populate ttm_alloced with false, when it's notBen Skeggs2011-04-201-0/+1
| | | | | | Caught with kmemcheck on unrelated business. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: fix nv30 pcie boardsBen Skeggs2011-04-201-2/+2
| | | | | | | | Wasn't aware they even existed, apparently they do! They're actually AGP chips with a bridge as far as I can tell, which puts them in the same boat as nv40/nv45. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv40: attempt to reserve just enough vram for all 32 channelsBen Skeggs2011-03-141-2/+1
| | | | | | | | This also makes the fact we're giving 512MiB of GART space to all PCIE boards explicit, although the vast majority (if not all) of them will now have a ramin_rsvd_vram larger than 2MiB anyway. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv50-nvc0: delay GART binding until move_notify timeBen Skeggs2011-02-251-21/+9
| | | | | | | | The immediate benefit of doing this is that on NV50 and up, the GPU virtual address of any buffer is now constant, regardless of what memtype they're placed in. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv40: implement support for on-chip PCIEGARTBen Skeggs2011-02-251-20/+270
| | | | | | | v2. moved nv44 pciegart table back to instmem, where it's not accessible by userspace clients. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: introduce new gart type, and name _SGDMA more appropriatelyBen Skeggs2011-02-251-1/+2
| | | | | | | In preparation for the addition of a new nv40 backend, we'll need to be able to distinguish between a paged dma object and the on-chip GART. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: move + rename some stuff in nouveau_sgdma.cBen Skeggs2011-02-251-39/+38
| | | | | | In preparation for the addition of a new nv40 pcie backend. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* Merge branch 'stable/ttm.pci-api.v5' of ↵Dave Airlie2011-02-231-8/+23
|\ | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/konrad/xen into drm-next * 'stable/ttm.pci-api.v5' of git://git.kernel.org/pub/scm/linux/kernel/git/konrad/xen: ttm: Include the 'struct dev' when using the DMA API. nouveau/ttm/PCIe: Use dma_addr if TTM has set it. radeon/ttm/PCIe: Use dma_addr if TTM has set it. ttm: Expand (*populate) to support an array of DMA addresses. ttm: Utilize the DMA API for pages that have TTM_PAGE_FLAG_DMA32 set. ttm: Introduce a placeholder for DMA (bus) addresses.
| * nouveau/ttm/PCIe: Use dma_addr if TTM has set it.Konrad Rzeszutek Wilk2011-02-181-7/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the TTM layer has used the DMA API to setup pages that are TTM_PAGE_FLAG_DMA32 (look at patch titled: "ttm: Utilize the DMA API for pages that have TTM_PAGE_FLAG_DMA32 set"), lets use it when programming the GART in the PCIe type cards. This patch skips doing the pci_map_page (and pci_unmap_page) if there is a DMA addresses passed in for that page. If the dma_address is zero (or DMA_ERROR_CODE), then we continue on with our old behaviour. [v2: Added a review-by tag] Reviewed-by: Thomas Hellstrom <thomas@shipmail.org> Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Tested-by: Ian Campbell <ian.campbell@citrix.com>
| * ttm: Expand (*populate) to support an array of DMA addresses.Konrad Rzeszutek Wilk2011-01-271-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We pass in the array of ttm pages to be populated in the GART/MM of the card (or AGP). Patch titled: "ttm: Utilize the DMA API for pages that have TTM_PAGE_FLAG_DMA32 set." uses the DMA API to make those pages have a proper DMA addresses (in the situation where page_to_phys or virt_to_phys do not give use the DMA (bus) address). Since we are using the DMA API on those pages, we should pass in the DMA address to this function so it can save it in its proper fields (later patches use it). [v2: Added reviewed-by tag] Reviewed-by: Thomas Hellstrom <thellstrom@shipmail.org> Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Tested-by: Ian Campbell <ian.campbell@citrix.com>
* | drm/nv04-nv40: Fix up PCI(E) GART DMA object bus address calculation.Francisco Jerez2010-12-081-10/+6
| | | | | | | | | | Signed-off-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* | drm/nv50: tidy up PCIEGART implementationBen Skeggs2010-12-081-76/+71
| | | | | | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* | drm/nv04-nv40: Give "gpuobj->cinst" the same meaning as on nv50.Francisco Jerez2010-12-081-6/+0
| | | | | | | | | | | | | | No functional changes, just simplify some code paths a bit. Signed-off-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* | drm/nouveau: tidy up and extend dma object creation interfacesBen Skeggs2010-12-031-5/+2
| | | | | | | | | | Reviewed-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* | drm/nouveau: remove dummy page use from PCI(E)GART, use PTE present insteadBen Skeggs2010-12-031-35/+3
| | | | | | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* | drm/nouveau: Make PCIE GART size depend on the available RAMIN space.Francisco Jerez2010-11-181-5/+5
| | | | | | | | | | | | Reported-by: Tomas Miljenovic <tomasmiljenovic@gmail.com> Signed-off-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* | drm/nv50: implement possible workaround for NV86 PGRAPH TLB flush hangBen Skeggs2010-11-181-4/+4
| | | | | | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* | drm/nouveau: fix nv40 pcie gart sizeLucas Stach2010-11-181-1/+5
|/ | | | | | | | | | Nouveau sets the PCIE GART size to 64MiB for all cards before nv50, but nv40 has enough RAMIN space to support 512MiB GART size. This patch fixes this value to make use of this hardware capability. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/ttm: restructure to allow driver to plug in alternate memory managerBen Skeggs2010-10-051-2/+2
| | | | | | | | | Nouveau will need this on GeForce 8 and up to account for the GPU reordering physical VRAM for some memory types. Reviewed-by: Jerome Glisse <jglisse@redhat.com> Acked-by: Thomas Hellström <thellstrom@vmware.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: zero dummy pageBen Skeggs2010-09-241-1/+1
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv50: mark PCIEGART pages non-present rather than using dummy pageBen Skeggs2010-09-241-4/+3
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: remove nouveau_gpuobj_ref completely, replace with sanityBen Skeggs2010-09-241-4/+9
| | | | | Reviewed-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: modify object accessors, offset in bytes rather than dwordsBen Skeggs2010-09-241-23/+27
| | | | | Reviewed-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: check for error when allocating/mapping dummy pageBen Skeggs2010-08-171-1/+11
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv50: move tlb flushing to a helper functionBen Skeggs2010-07-131-30/+4
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: add instmem flush() hookBen Skeggs2010-07-131-9/+3
| | | | | | | | | | This removes the previous prepare_access() and finish_access() hooks, and replaces it with a much simpler flush() hook. All the chipset-specific code before nv50 has its use removed completely, as it's not required there at all. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* Merge branch 'drm-linus' of ↵Linus Torvalds2010-04-091-0/+18
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6 * 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (29 commits) drm/nouveau: bail out of auxch transaction if we repeatedly recieve defers drm/nv50: implement gpio set/get routines drm/nv50: parse/use some more de-magiced parts of gpio table entries drm/nouveau: store raw gpio table entry in bios gpio structs drm/nv40: Init some tiling-related PGRAPH state. drm/nv50: Add NVA3 support in ctxprog/ctxvals generator. drm/nv50: another dodgy DP hack drm/nv50: punt hotplug irq handling out to workqueue drm/nv50: preserve an unknown SOR_MODECTRL value for DP encoders drm/nv50: Allow using the NVA3 new compute class. drm/nv50: cleanup properly if PDISPLAY init fails drm/nouveau: fixup the init failure paths some more drm/nv50: fix instmem init on IGPs if stolen mem crosses 4GiB mark drm/nv40: add LVDS table quirk for Dell Latitude D620 drm/nv40: rework lvds table parsing drm/nouveau: detect vram amount once, and save the value drm/nouveau: remove some unused members from drm_nouveau_private drm/nouveau: Make use of TTM busy_placements. drm/nv50: add more 0x100c80 flushy magic drm/nv50: fix fbcon when framebuffer above 4GiB mark ...
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