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* drm/nouveau/core: rework event interfaceBen Skeggs2014-08-103-25/+23
| | | | | | | | | | | | | | | This is a lot of prep-work for being able to send event notifications back to userspace. Events now contain data, rather than a "something just happened" signal. Handler data is now embedded into a containing structure, rather than being kmalloc()'d, and can optionally have the notify routine handled in a workqueue. Various races between suspend/unload with display HPD/DP IRQ handlers automagically solved as a result. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv50-/sw: use nv50_software_context_dtor....Ben Skeggs2014-08-102-2/+2
| | | | | | You would not believe the troubles this caused me... Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/core: allow event source to handle multiple event types per indexBen Skeggs2014-06-113-4/+4
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/sw: fix oops if gpu has its display block disabledBen Skeggs2013-12-031-1/+1
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/core: convert event handler apis to split create/enable semanticsBen Skeggs2013-11-083-54/+51
| | | | | | | | | | | This is a necessary step towards being able to work with the insane locking requirements of the DRM core's vblank routines, and a nice cleanup as a side-effect. This is similar in spirit to the interfaces that Peter Hurley arrived at with his nouveau_event rcu conversion series. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv50-/sw: share engine/channel constructor between implementationsBen Skeggs2013-11-083-51/+37
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/sw: prepare for the sharing of constructors between implementationsBen Skeggs2013-11-085-14/+18
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv50-/sw: make vblank tracking data private to the implementationsBen Skeggs2013-11-083-18/+25
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv50-/sw: share engine/channel struct definitions between implementationsBen Skeggs2013-11-083-24/+25
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nvc0/gr: add software methods to control some MP regsChristoph Bumiller2013-04-261-0/+29
| | | | | Signed-off-by: Christoph Bumiller <e0425955@student.tuwien.ac.at> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/disp: port vblank handling to event interfaceBen Skeggs2013-02-202-17/+52
| | | | | | | | | This removes the nastiness with the interactions between display and software engines when handling vblank semaphore release interrupts. Now, all the semantics are handled in one place (sw) \o/. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/core: allow representing method ranges in nouveau_omthdsBen Skeggs2012-11-294-13/+13
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/sw: trap and clear PMC_INTR_0_SOFTWAREBen Skeggs2012-10-034-0/+10
| | | | | | Came in useful for debugging another issue earlier, so keep it around. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: port all engines to new engine module formatBen Skeggs2012-10-034-0/+646
This is a HUGE commit, but it's not nearly as bad as it looks - any problems can be isolated to a particular chipset and engine combination. It was simply too difficult to port each one at a time, the compat layers are *already* ridiculous. Most of the changes here are simply to the glue, the process for each of the engine modules was to start with a standard skeleton and copy+paste the old code into the appropriate places, fixing up variable names etc as needed. v2: Marcin Slusarz <marcin.slusarz@gmail.com> - fix find/replace bug in license header v3: Ben Skeggs <bskeggs@redhat.com> - bump indirect pushbuf size to 8KiB, 4KiB barely enough for userspace and left no space for kernel's requirements during GEM pushbuf submission. - fix duplicate assignments noticed by clang v4: Marcin Slusarz <marcin.slusarz@gmail.com> - add sparse annotations to nv04_fifo_pause/nv04_fifo_start - use ioread32_native/iowrite32_native for fifo control registers v5: Ben Skeggs <bskeggs@redhat.com> - rebase on v3.6-rc4, modified to keep copy engine fix intact - nv10/fence: unmap fence bo before destroying - fixed fermi regression when using nvidia gr fuc - fixed typo in supported dma_mask checking Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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