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path: root/drivers/gpu/drm/nouveau/core/engine/dmaobj
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* drm/nouveau/fifo: audit and version fifo channel classesBen Skeggs2014-08-102-8/+7
| | | | | | | | The full object interfaces are about to be exposed to userspace, so we need to check for any security-related issues and version the structs to make it easier to handle any changes we may need in the future. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/dma: audit and version NV_DMA classesBen Skeggs2014-08-105-74/+152
| | | | | | | | The full object interfaces are about to be exposed to userspace, so we need to check for any security-related issues and version the structs to make it easier to handle any changes we may need in the future. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/dmaobj: switch to a slightly saner designBen Skeggs2014-08-106-178/+355
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/dmaobj: update to an improved style of class definitionBen Skeggs2014-08-106-124/+87
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/device: audit and version NV_DEVICE classBen Skeggs2014-08-101-1/+1
| | | | | | | | The full object interfaces are about to be exposed to userspace, so we need to check for any security-related issues and version the structs to make it easier to handle any changes we may need in the future. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/gm107/disp: initial implementationBen Skeggs2014-03-261-0/+3
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nvf0/disp: expose display class 2.2Ben Skeggs2013-05-021-0/+3
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nvd0-nve0/disp: initial implementation of evo channel classesBen Skeggs2012-11-291-0/+6
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv50/disp: initial implementation of the various channel object classesBen Skeggs2012-11-292-0/+19
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nvd0/dmaobj: initial bind() method implementationBen Skeggs2012-11-291-1/+34
| | | | | | | Currently unused, and rudimentary. Lots to figure out here still, but this is sufficient for what disp will need. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nvc0/dmaobj: implement initial bind() methodBen Skeggs2012-11-291-1/+58
| | | | | | Currently unused. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv50/dmaobj: extend class to allow gpu-specific attributes to be definedBen Skeggs2012-11-292-14/+30
| | | | | | | disp is going to need to be able to create more specific dma objects than was previously possible. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nvd0/dmaobj: duplicate fermi class, will diverge real soon nowBen Skeggs2012-11-291-0/+83
| | | | | | | The hardware dmaobj format completely changed in GF119, so these will need a separate implementation. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nvc0/dmaobj: stub bind function for now so we can call unconditionallyBen Skeggs2012-11-291-0/+23
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/dmaobj: move parent class check to bind() methodBen Skeggs2012-11-293-12/+30
| | | | | | | | | | | Otherwise when nvc0- gains a bind() method (disp needs it), the fifo engine will attempt to create a dma object for the push buffer, which is unnecessary on fermi. The only sane place to put these checks is in the bind method itself, and have it unconditionally called from wherever it might be needed. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/dmaobj: merge everything except ctor and bind togetherBen Skeggs2012-11-294-171/+61
| | | | | | | Simplifies things a little, and currently no reason to need chipset-specific dmaobj constructors. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv04/dmaobj: fixup vm target handling in preparation for nv4x pcieBen Skeggs2012-10-031-7/+10
| | | | | | | We don't need to pull the page address out of the page tables on nv4x chips that have a real GART. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/dmaobj: reject unsupported parent types instead of half-succeedingBen Skeggs2012-10-032-10/+16
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv50/fifo: add support for dma channel classBen Skeggs2012-10-031-0/+1
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv84/fifo: add support for dma channel classBen Skeggs2012-10-031-0/+1
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fifo: separate object classes for dma channelsBen Skeggs2012-10-031-0/+3
| | | | | | | Future code will use the object class rather than chipset checks in order to identify available channel features. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: port all engines to new engine module formatBen Skeggs2012-10-034-0/+530
This is a HUGE commit, but it's not nearly as bad as it looks - any problems can be isolated to a particular chipset and engine combination. It was simply too difficult to port each one at a time, the compat layers are *already* ridiculous. Most of the changes here are simply to the glue, the process for each of the engine modules was to start with a standard skeleton and copy+paste the old code into the appropriate places, fixing up variable names etc as needed. v2: Marcin Slusarz <marcin.slusarz@gmail.com> - fix find/replace bug in license header v3: Ben Skeggs <bskeggs@redhat.com> - bump indirect pushbuf size to 8KiB, 4KiB barely enough for userspace and left no space for kernel's requirements during GEM pushbuf submission. - fix duplicate assignments noticed by clang v4: Marcin Slusarz <marcin.slusarz@gmail.com> - add sparse annotations to nv04_fifo_pause/nv04_fifo_start - use ioread32_native/iowrite32_native for fifo control registers v5: Ben Skeggs <bskeggs@redhat.com> - rebase on v3.6-rc4, modified to keep copy engine fix intact - nv10/fence: unmap fence bo before destroying - fixed fermi regression when using nvidia gr fuc - fixed typo in supported dma_mask checking Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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