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* drm: bridge: Link encoder and bridge in core codeLaurent Pinchart2016-12-181-6/+11
| | | | | | | | | | | | | | | | | | | Instead of linking encoders and bridges in every driver (and getting it wrong half of the time, as many drivers forget to set the drm_bridge encoder pointer), do so in core code. The drm_bridge_attach() function needs the encoder and optional previous bridge to perform that task, update all the callers. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Stefan Agner <stefan@agner.ch> # For DCU Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> # For atmel-hlcdc Acked-by: Vincent Abriou <vincent.abriou@st.com> # For STI Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> # For sun4i Acked-by: Xinliang Liu <z.liuxinliang@hisilicon.com> # For hisilicon Acked-by: Jyri Sarha <jsarha@ti.com> # For tilcdc Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Archit Taneja <architt@codeaurora.org> Link: http://patchwork.freedesktop.org/patch/msgid/1481709550-29226-4-git-send-email-laurent.pinchart+renesas@ideasonboard.com
* Merge branch 'msm-next' of git://people.freedesktop.org/~robclark/linux into ↵Dave Airlie2016-12-014-5/+5
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | drm-next On the userspace side, all the basics are working, and most of glmark2 is working. I've been working through deqp, and I've got a couple more things to fix (but we've gone from 70% to 80+% pass in last day, and current deqp run that is going should pick up another 5-10%). I expect to push the mesa patches today or tomorrow. There are a couple more a5xx related patches to take the gpu out of secure mode (for the devices that come up in secure mode, like the hw I have), but those depend on an scm patch that would come in through another tree. If that can land in the next day or two, there might be a second late pull request for drm/msm. In addition to the new-shiny, there have also been a lot of overlay/ plane related fixes for issues found using drm-hwc2 (in the process of testing/debugging the atomic/kms fence patches), resulting in rework to assign hwpipes to kms planes dynamically (as part of global atomic state) and also handling SMP (fifo) block allocation atomically as part of the ->atomic_check() step. All those patches should also help out atomic weston (when those patches eventually land). * 'msm-next' of git://people.freedesktop.org/~robclark/linux: (36 commits) drm/msm: gpu: Add support for the GPMU drm/msm: gpu: Add A5XX target support drm/msm: Disable interrupts during init drm/msm: Remove 'src_clk' from adreno configuration drm/msm: gpu: Add OUT_TYPE4 and OUT_TYPE7 drm/msm: Add adreno_gpu_write64() drm/msm: gpu Add new gpu register read/write functions drm/msm: gpu: Return error on hw_init failure drm/msm: gpu: Cut down the list of "generic" registers to the ones we use drm/msm: update generated headers drm/msm/adreno: move scratch register dumping to per-gen code drm/msm/rd: support for 64b iova drm/msm: convert iova to 64b drm/msm: set dma_mask properly drm/msm: Remove bad calls to of_node_put() drm/msm/mdp5: move LM bounds check into plane->atomic_check() drm/msm/mdp5: dump smp state on errors too drm/msm/mdp5: add debugfs to show smp block status drm/msm/mdp5: handle SMP block allocations "atomically" drm/msm/mdp5: dynamically assign hw pipes to planes ...
| * drm/msm: update generated headersRob Clark2016-11-283-3/+3
| | | | | | | | | | | | Pull in a5xx registers. Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm: convert iova to 64bRob Clark2016-11-281-2/+2
| | | | | | | | | | | | | | | | | | For a5xx the gpu is 64b so we need to change iova to 64b everywhere. On the display side, iova is still 32b so it can ignore the upper bits. (Although all the armv8 devices have an iommu that can map 64b pa to 32b iova.) Signed-off-by: Rob Clark <robdclark@gmail.com>
* | drm/msm: Set CLK_IGNORE_UNUSED flag for PLL clocksArchit Taneja2016-11-022-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DSI/HDMI PLLs in MSM require resources like interface clocks, power domains to be enabled before we can access their registers. The clock framework doesn't have a mechanism at the moment where we can tie such resources to a clock, so we make sure that the KMS driver enables these resources whenever a PLL is expected to be in use. One place where we can't ensure the resource dependencies are met is when the clock framework tries to disable unused clocks. The KMS driver doesn't know when the clock framework calls the is_enabled clk_op, and hence can't enable interface clocks/power domains beforehand. We set the CLK_IGNORE_UNUSED flag for PLL clocks for now. This needs to be revisited, since bootloaders can enable display, and we would want to disable the PLL clocks if there isn't a display driver using them. Cc: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Archit Taneja <architt@codeaurora.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* | drm/msm/dsi: Queue HPD helper work in attach/detach callbacksArchit Taneja2016-11-021-2/+12
|/ | | | | | | | | | | | | The msm/dsi host drivers calls drm_helper_hpd_irq_event in the mipi_dsi_host attach/detatch callbacks. mipi_dsi_attach()/mipi_dsi_detach() from a panel/bridge driver could be called from a context where the drm_device's mode_config.mutex is already held, resulting in a deadlock. Queue it as work instead. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/dsi: Fix return value check in msm_dsi_host_set_display_mode()Wei Yongjun2016-07-161-2/+2
| | | | | | | | | | In case of error, the function drm_mode_duplicate() returns NULL pointer not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Reviewed-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: change gem->vmap() to get/putRob Clark2016-07-161-1/+4
| | | | | | | | Before we can add vmap shrinking, we really need to know which vmap'ings are currently being used. So switch to get/put interface. Stubbed put fxns for now. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/dsi: Don't get DSI index from DTArchit Taneja2016-07-168-12/+75
| | | | | | | | | | | | | | | | | | | | The DSI host and PHY driver currently expects the DT bindings to provide custom properties "qcom,dsi-host-index" and "qcom,dsi-phy-index" so that the driver can identify which DSI instance it is. The binding isn't acceptable, but the driver still needs to figure out what its instance id. This is now done by storing the mmio starting addresses for each DSI instance in every SoC version in the driver. The driver then identifies the index number by trying to match the stored address with comparing the resource start address we get from DT. We don't have compatible strings for DSI PHY on each SoC, but only the DSI PHY type. We only support one SoC version for each PHY type, so we get away doing the same thing above for the PHY driver. We can revisit this when we support two SoCs with the same DSI PHY. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/dsi: Use a standard DT binding for data lanesArchit Taneja2016-07-161-3/+14
| | | | | | | | | | | | | | | | A more standard DT binding describing data lanes already exists here: Documentation/devicetree/bindings/media/video-interfaces.txt Use this binding instead of "qcom,data-lane-map". One difference in the standard binding w.r.t to the existing binding is that it provides a logical to physical mapping instead of the other way round. Tweak the code to translate the data the way we want it. The MSM DSI DT bindings aren't used anywhere at the moment, so it's okay to update this property. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/dsi: Use generic PHY bindingsArchit Taneja2016-07-161-1/+1
| | | | | | | | | The DSI host links to the DSI PHY device using a custom binding. Switch to the generic PHY bindings. The DSI PHY driver itself doesn't use the common PHY framework for now. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/dsi: Modify port parsingArchit Taneja2016-07-161-5/+5
| | | | | | | | | | | | | | | | | | The DSI interface is going to have two ports defined in its device node. The first port is always going to be the link between the MDP output and the input to DSI, the second port is going to be the link between the DSI output and the connected panel/bridge: ----- ----- ------- | MDP | ------> | DSI | ------> | Panel | ----- ----- ------- (Port 0) (Port 1) Until now, there was only one Port representing the output. Update the DSI host driver such that it parses Port #1 for a connected device. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: Centralize connector registration/unregistrationArchit Taneja2016-05-081-18/+9
| | | | | | | | | | | | | | | | Move the drm_connector registration from the encoder(HDMI/DSI etc) drivers to the msm platform driver. This will simplify the task of ensuring that the connectors are registered only after the drm_device itself is registered. The connectors' destroy ops are made to use kzalloc instead of devm_kzalloc to ensure that that the connectors can be successfully unregistered when the msm driver module is removed. The memory for the connectors is unallocated when drm_mode_config_cleanup() is called during either during an error or during driver remove. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/dsi: Fix regulator API abuseArchit Taneja2016-05-087-49/+22
| | | | | | | | | | | | | | | | | | | | | | | | | The voltage changing code in this driver is broken and should be removed. The driver sets a single, exact voltage on probe. Unless there is a very good reason for this (which should be documented in comments) constraints like this need to be set via the machine constraints, voltage setting in a driver is expected to be used in cases where the voltage varies at runtime. In addition client drivers should almost never be calling regulator_can_set_voltage(), if the device needs to set a voltage it needs to set the voltage and the regulator core will handle the case where the regulator is fixed voltage. If the driver simply skips setting the voltage if it doesn't have permission then it should just not bother in the first place. Originally authored by Mark Brown <broonie@kernel.org> Remove the min/max voltage data entries per SoC managed by the driver. These aren't needed as we don't try to set voltages any more. Mention in comments the voltages that each regulator expects. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: update generated headersRob Clark2016-03-033-6/+9
| | | | | | Pull in additional regs needed for a430, etc. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/dsi: fix definition of msm_dsi_pll_28nm_8960_init()Luis Henriques2016-03-031-2/+2
| | | | | | | | | | | | This fixes the following build failure: drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.o: In function `msm_dsi_pll_28nm_8960_init': dsi_pll_28nm.c:(.text+0x1198): multiple definition of `msm_dsi_pll_28nm_8960_init' drivers/gpu/drm/msm/dsi/pll/dsi_pll.o:dsi_pll.c:(.text+0x0): first defined here Signed-off-by: Luis Henriques <luis.henriques@canonical.com> Acked-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/dsi: Parse DSI lanes via DTArchit Taneja2016-03-031-20/+96
| | | | | | | | | | | | | | | | | | | | | | The DSI driver is currently unaware of how the DSI physical data lanes are mapped to the logical lanes provided by the DSI controller. Create a DT binding "qcom,data-lane-map" that provides this information on a given platform. The MSM DSI controller is restricted in terms of what all mappings it can support. The lane polarity is fixed for all the lanes, the clock lanes are fixed, and the data lanes can be swapped among each other only for a few combinations. Apply these restrictions when we parse the DT data. Cc: devicetree@vger.kernel.org Cc: Rob Herring <robh@kernel.org> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com> Acked-by: Rob Herring <robh@kernel.org>
* drm/msm/dsi: Drop VDD regulator for MSM8916Archit Taneja2016-03-021-2/+1
| | | | | | | | | | VDD regulator input was specified for MSM8916. It turns our that this regulator is used for the display panels used on MSM8916 platforms, but not the DSI controller itself. Drop this regulator from the list. Reported-by: Vinay Simha <vinaysimha@inforcecomputing.com> Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/dsi: Remove incorrect warning on host attachArchit Taneja2016-03-021-2/+0
| | | | | | | | | | | | With the implementation of of_graph parsing, it isn't any longer necessary for msm_host->device node to be same as dsi->dev.of_node. This only holds true when the connected device is also a child of the dsi_host. In the case of external bridge chips belonging to a different control bus, these are guaranteed to be different. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/dsi: Added missing mutex_unlocksaurabh2015-12-141-1/+1
| | | | | | | | in case of failed to get iova, function was returning without releasing the mutex. Added it. Signed-off-by: Saurabh Sengar <saurabh.truth@gmail.com> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/dsi: Enable MMSS SPFB port via sysconArchit Taneja2015-12-141-0/+33
| | | | | | | | | For DSIv2 to work, we need to enable MMSS_AHB_ARB_MASTER_PORT in MMSS_SFPB. We enable the required bitfield by retrieving MMSS_SFPB regmap pointer via syscon. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/dsi: Don't use iommu for command TX buffer for DSIv2Archit Taneja2015-12-143-41/+79
| | | | | | | | | | | We currently use iommu allocated DMA buffers for sending DSI commands. DSIv2 doesn't have a port connected to the MDP iommu. Therefore, it can't use iommu allocated buffers to fetch DSI commands. Use a regular contiguous DMA buffer if we are DSIv2. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/dsi: Add dsi_cfg for APQ8064Archit Taneja2015-12-142-3/+18
| | | | | | | | | Add a dsi_cfg entry for APQ8064. Since this is the first DSIv2 chip to be supported, add a list of bus clocks that are required by the DSIv2 block. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/dsi: Set up link clocks for DSIv2Archit Taneja2015-12-141-5/+186
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | DSIv2 (DSI on older A family chips) has slightly different link clock requirements. First, we have an extra clock called src_clk (with a dedicated RCG). This is required by the DSI controller to process the pixel data coming from MDP. It needs to be set at the rate "pclk * bytes_per_pixel". We also need to explicitly configure esc_clk. On DSI6G chips, we don't need to set a rate to esc_clk because its RCG is always sourced from crystal clock (19.2 Mhz in all cases), which is within the escape clock frequency range in the mipi DSI spec. For chips with DSIv2, the crystal clock rate may not be within the required range (27Mhz on APQ8064). Therefore, we derive it from the DSI byte clock. We calculate an esc_clck rate that is within the mipi spec and also divisible by the byte clock rate. When setting rate and enabling the link clocks, we make sure that byte_clk is configured before esc_clk, and src_clk before pixel_clk. We create two different link_enable funcs for DSI6G and DSIv2 since the sequences are different. We also obtain two extra source clocks (dsi_src_clk and esc_src_clk) and set their parent to the clocks provided by DSI PLL. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/dsi: Parse bus clocks from a listArchit Taneja2015-12-144-73/+53
| | | | | | | | | | | | | | | DSI bus clocks seem to vary between different DSI host versions, and the SOC to which they belong. Even the enable/disable sequence varies. Provide a list of bus clock names in dsi_cfg. The driver will use this to retrieve the clocks, and enable/disable them. Add bus clock lists for DSI6G, and DSI for MSM8916(this is DSI6G too, but there is no MMSS_CC specific clock since there is no MMSS clock controller on 8916). Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/dsi: Delay dsi_clk_initArchit Taneja2015-12-141-10/+22
| | | | | | | | | | | | | Initialize clocks only after we get the DSI host version. This will allow us to get clocks using a pre-defined list based on the DSI major/minor version of the host. This is required since clock requirements of different major DSI revisions(v2 vs 6g) aren't the same. Modify dsi_get_version to get the interface clock, and then put it after it is used. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/dsi: Use a better way to figure out DSI versionArchit Taneja2015-12-141-6/+18
| | | | | | | | | | | | | | | | | | | | | The current version checking mechanism works fine for DSI6G blocks. It doesn't work so well for older generation DSIv2 blocks. The initial read of REG_DSI_6G_HW_VERSION(offset 0x0) would result in a read of REG_DSI_CTRL for DSIv2. This register won't necessarily be 0 on DSIv2. It can be non zero if DSI was previously initialized by the bootloader. Instead of reading offset 0x0, we now read offset 0x1f0. For DSIv2, this register is DSI_VERSION, and is bound to be non-zero. On DSI6G, this register(offset 0x1f0) is SCRATCH_REGISTER_0, which no one ever seems to touch, and from all register dumps I'vc seen, holds 0 all the time. Modify dsi_get_version to read REG_DSI_VERSION to determine whether we are DSI6G or DSIv2. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/dsi: Add DSI PLL for 28nm 8960 PHYArchit Taneja2015-12-143-0/+546
| | | | | | | | | | | | | | | | | | | | | | | | Add DSI PLL common clock framework clocks for 8960 PHY. The PLL here is different from the ones found in B family msm chips. As before, the DSI provides two clocks to the outside world. dsixpll and dsixpllbyte (x = 1, 2). dsixpll is a regular clock divider, but dsixpllbyte is modelled as a custom clock divider. dsixpllbyte is the starting point of the PLL configuration. It is the one that sets up the VCO clock rate. We need the VCO clock rate in the form: F * byteclk, where F is a multiplication factor that varies on the byte clock the DSI driver is trying to set. We use the custom clk_ops for dsixpllbyte to ensure that the parent (VCO) is set at this rate. An additional divider (POSTDIV1) generates the bitclk. Since bit clock can be derived from byteclock, we calculate it internally, and don't expose it as a clock. Cc: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/dsi: Add support for 28nm PHY on 8960Archit Taneja2015-12-144-0/+201
| | | | | | | | | | DSI PHY on MSM8960 and APQ8064 is a 28nm PHY that's different from the supported 28nm LP PHY found in newer chips. Add support for the new PHY. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/dsi: Don't get byte/pixel source clocks from DTArchit Taneja2015-12-141-9/+6
| | | | | | | | | | | | | | | | | | | | We retrieve the byte and pixel source clocks (RCG clocks) in the dsi driver via DT. These are needed so that we can re-parent these source clocks if we want to drive it using a different DSI PLL. We shouldn't get these via DT because they aren't clocks that directly serve as inputs to the dsi host. Fortunately, there is a static parent-child link between the byte_clk_src/pixel_clk_src and byte_clk/pixel_clk clocks. So, we can retrieve the source clocks via clk_get_parent. Do this instead of retrieving via DT. Cc: Rob Herring <robh@kernel.org> Cc: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/dsi: Updata LNn_CFG4 register settings for 28nm PHYHai Li2015-10-221-4/+2
| | | | | | | | | The current settings for 28nm PHY data lane CFG4 registers do not work with certain panels. This change is to modify them to hw recommended values. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm: msm: dsi: Don't attempt changing voltage of switchesBjorn Andersson2015-10-222-2/+2
| | | | | | | | | | In some configurations the supplies are voltage switches and not LDOs, making the set voltage call to fail. Check with the regulator framework if the supply can change voltage before attempting. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Reviewed-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: update generated headersRob Clark2015-10-223-68/+199
| | | | Signed-off-by: Rob Clark <robdclark@gmail.com>
* Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linuxLinus Torvalds2015-09-0416-603/+1283
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull drm updates from Dave Airlie: "This is the main pull request for the drm for 4.3. Nouveau is probably the biggest amount of changes in here, since it missed 4.2. Highlights below, along with the usual bunch of fixes. All stuff outside drm should have applicable acks. Highlights: - new drivers: freescale dcu kms driver - core: more atomic fixes disable some dri1 interfaces on kms drivers drop fb panic handling, this was just getting more broken, as more locking was required. new core fbdev Kconfig support - instead of each driver enable/disabling it struct_mutex cleanups - panel: more new panels cleanup Kconfig - i915: Skylake support enabled by default legacy modesetting using atomic infrastructure Skylake fixes GEN9 workarounds - amdgpu: Fiji support CGS support for amdgpu Initial GPU scheduler - off by default Lots of bug fixes and optimisations. - radeon: DP fixes misc fixes - amdkfd: Add Carrizo support for amdkfd using amdgpu. - nouveau: long pending cleanup to complete driver, fully bisectable which makes it larger, perfmon work more reclocking improvements maxwell displayport fixes - vmwgfx: new DX device support, supports OpenGL 3.3 screen targets support - mgag200: G200eW support G200e new revision support - msm: dragonboard 410c support, msm8x94 support, msm8x74v1 support yuv format support dma plane support mdp5 rotation initial hdcp - sti: atomic support - exynos: lots of cleanups atomic modesetting/pageflipping support render node support - tegra: tegra210 support (dc, dsi, dp/hdmi) dpms with atomic modesetting support - atmel: support for 3 more atmel SoCs new input formats, PRIME support. - dwhdmi: preparing to add audio support - rockchip: yuv plane support" * 'drm-next' of git://people.freedesktop.org/~airlied/linux: (1369 commits) drm/amdgpu: rename gmc_v8_0_init_compute_vmid drm/amdgpu: fix vce3 instance handling drm/amdgpu: remove ib test for the second VCE Ring drm/amdgpu: properly enable VM fault interrupts drm/amdgpu: fix warning in scheduler drm/amdgpu: fix buffer placement under memory pressure drm/amdgpu/cz: fix cz_dpm_update_low_memory_pstate logic drm/amdgpu: fix typo in dce11 watermark setup drm/amdgpu: fix typo in dce10 watermark setup drm/amdgpu: use top down allocation for non-CPU accessible vram drm/amdgpu: be explicit about cpu vram access for driver BOs (v2) drm/amdgpu: set MEC doorbell range for Fiji drm/amdgpu: implement burst NOP for SDMA drm/amdgpu: add insert_nop ring func and default implementation drm/amdgpu: add amdgpu_get_sdma_instance helper function drm/amdgpu: add AMDGPU_MAX_SDMA_INSTANCES drm/amdgpu: add burst_nop flag for sdma drm/amdgpu: add count field for the SDMA NOP packet v2 drm/amdgpu: use PT for VM sync on unmap drm/amdgpu: make wait_event uninterruptible in push_job ...
| * drm/msm/dsi: Introduce DSI configuration moduleHai Li2015-08-153-146/+176
| | | | | | | | | | | | | | | | | | With more platforms supported, the DSI host configuration array keeps expanding. This change moves those to a separate dsi_cfg module. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm/dsi: Make each PHY type compilation independentHai Li2015-08-152-0/+12
| | | | | | | | | | | | | | | | | | On a certain platform, only one type of DSI PHY is used. This change allows the user to only compile the PHY type which is being used. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm/dsi: Split PHY drivers to separate filesHai Li2015-08-155-756/+853
| | | | | | | | | | | | | | | | This change moves each PHY type specific code into separate files. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm/dsi: Return void from msm_dsi_phy_disable()Hai Li2015-08-152-12/+6
| | | | | | | | | | | | | | | | We are not checking the return value from msm_dsi_phy_disable(). Change the return type to void. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm/dsi: Specify bitmask to set source PLLHai Li2015-08-151-5/+11
| | | | | | | | | | | | | | | | | | The bit position to configure source PLL will change on new types of PHYs. The caller should pass down this information. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm/dsi: Modify dsi manager bridge ops to work with external bridgesArchit Taneja2015-08-151-15/+28
| | | | | | | | | | | | | | | | | | The dsi bridge ops call drm_panel functions to set up the connected drm_panel. Add checks to make sure these aren't called when we're connected to an external bridge. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm/dsi: Allow dsi to connect to an external bridgeArchit Taneja2015-08-154-8/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are platforms where the DSI output can be connected to another encoder bridge chip (DSI to HDMI, DSI to LVDS etc). Add support for external bridge support to the dsi driver. We assume that the external bridge chip would be of the type drm_bridge. The dsi driver's internal drm_bridge (msm_dsi->bridge) is linked to the external bridge's drm_bridge struct. In the case we're connected to an external bridge, we don't need to create and manage a connector within our driver, it's the bridge driver's responsibility to create one. v2: - Move the external bridge attaching stuff to dsi manager to make things cleaner. - Force the bridge to connect to a video mode encoder for now (the dsi mode flags may have not been populated by modeset_init) Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm/dsi: Create a helper to check if there is a connected deviceArchit Taneja2015-08-153-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Create a helper msm_dsi_device_connected() which checks whether we have a device connected to the dsi host or not. This check gets messy when we have support external bridges too. Having an inline function makes it more legible. For now, the check only consists of msm_dsi->panel being non-NULL. Later, this will check if we have an external bridge or not. This helper isn't used in dsi_connector related code as that's specific to only when a drm_panel is connected. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm/dsi: Refer to connected device as 'device' instead of 'panel'Archit Taneja2015-08-154-16/+16
| | | | | | | | | | | | | | | | | | | | | | | | We currently support only panels connected to dsi output. We're going to also support external bridge chips now. Change 'panel_node' to 'device_node' in the struct msm_dsi_host and 'panel_flags' to 'device_flags' in msm_dsi. This makes things sound a bit more generic. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm/dsi: Make TE gpio optionalArchit Taneja2015-08-151-1/+2
| | | | | | | | | | | | | | | | Platforms containing only DSI video mode devices don't need a TE gpio. Make TE gpio optional. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm: dsi host: Use device graph parsing to parse connected panelArchit Taneja2015-08-151-19/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The dsi host looks for the connected panel node by parsing for a child named 'panel'. This hierarchy isn't very flexible. The connected panel is forced to be a child to the dsi host, and hence, a mipi dsi device. This isn't suitable for dsi devices that don't use mipi dsi as their control bus. Follow the of_graph approach of creating ports and endpoints to represent the connections between the dsi host and the panel connected to it. In our case, the dsi host will only have one output port, linked to the panel's input port. Update DT binding documentation with device graph usage info. v3: - Fix return value checks of of_graph_* calls. - Don't make port a mandatory DT property - Fix defer check when no panel node specified - Rename parse_dt func to align with other dsi_host funcs Reviewed-by: Hai Li <hali@codeaurora.org> Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm: dsi host: add missing of_node_put()Archit Taneja2015-08-151-1/+5
| | | | | | | | | | | | | | | | Decrement device node refcount if of_get_child_by_name is successfully called. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm/dsi: Save/Restore PLL status across PHY resetHai Li2015-08-155-36/+68
| | | | | | | | | | | | | | | | | | | | | | | | Reset DSI PHY silently changes its PLL registers to reset status, which will make cached status in clock driver invalid and result in wrong output rate of link clocks. The current restore mechanism in DSI PLL does not cover all the cases. This change is to recover PLL status after PHY reset to match HW status with cached status in clock driver. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm/dsi: One function call less in dsi_init() after error detectionMarkus Elfring2015-08-151-13/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The dsi_destroy() function was called in two cases by the dsi_init() function during error handling even if the passed variable contained a null pointer. * This implementation detail could be improved by adjustments for jump targets according to the Linux coding style convention. * Drop an unnecessary initialisation for the variable "msm_dsi" then. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> [add couple missing ERR_PTR()'s] Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm/dsi: Delete an unnecessary check before the function call "dsi_destroy"Markus Elfring2015-08-151-3/+1
| | | | | | | | | | | | | | | | | | | | The dsi_destroy() function tests whether its argument is NULL and then returns immediately. Thus the test around the call is not needed. This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm/dsi: Report PHY errors only when they really occurArchit Taneja2015-08-151-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | DSI PHY errors are falsely reported whenever a dsi error occurs. This is because DSI_DLN0_PHY_ERR isn't only used as a status register, but also used to mask PHY errors. Currently, we end up reading the mask bits too and therefore always report errors. Ignore the register mask bits and check for only the status/clear bits. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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