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path: root/drivers/gpu/drm/i915
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* Merge tag 'drm-intel-next-2014-08-08' of git://anongit.freedesktop.org/drm-in...Dave Airlie2014-08-2623-397/+1260
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| * drm/i915: Update DRIVER_DATE to 20140808Daniel Vetter2014-08-081-1/+1
| * drm/i915: No busy-loop wait_for in the ring init codeDaniel Vetter2014-08-081-2/+2
| * drm/i915: Add sprite watermark programming for VLV and CHVGajanan Bhat2014-08-082-6/+36
| * drm/i915: Round-up clock and limit drain latencyGajanan Bhat2014-08-081-1/+4
| * drm/i915: Generalize drain latency computationGajanan Bhat2014-08-082-37/+51
| * drm/i915: Free pending page flip events at .preclose()Ville Syrjälä2014-08-083-0/+26
| * drm/i915: clean up PPGTT checking logicJesse Barnes2014-08-083-14/+2
| * drm/i915: Polish the chv cmnlane resrt macrosVille Syrjälä2014-08-082-9/+6
| * drm/i915: Hack to tie both common lanes together on chvVille Syrjälä2014-08-081-2/+12
| * drm/i915: Add cherryview_update_wm()Ville Syrjälä2014-08-081-1/+80
| * drm/i915: Update DDL only for current CRTCGajanan Bhat2014-08-081-16/+9
| * drm/i915: Parametrize VLV_DDL registersVille Syrjälä2014-08-082-70/+36
| * drm/i915: Fill out the FWx watermark register definesVille Syrjälä2014-08-082-19/+130
| * drm/i915: Add rotation property for spritesVille Syrjälä2014-08-081-1/+40
| * drm/i915: Make intel_plane_restore() return an errorVille Syrjälä2014-08-082-8/+8
| * drm/i915: Add 180 degree sprite rotation supportVille Syrjälä2014-08-083-0/+42
| * drm/i915: Introduce a for_each_intel_encoder() macroDamien Lespiau2014-08-086-49/+31
| * drm/i915: Demote the DRRS messages to debug messagesDamien Lespiau2014-08-081-3/+3
| * drm/i915: remove duplicate register definesPaulo Zanoni2014-08-081-2/+0
| * drm/i915: Remove now useless comments about the translation valuesDamien Lespiau2014-08-081-5/+5
| * drm/i915/bdw: Remove the HDMI/DVI entry from the DP/eDP/FDI tablesDamien Lespiau2014-08-081-3/+0
| * drm/i915/bdw: Provide the BDW specific HDMI buffer translation tableDamien Lespiau2014-08-081-5/+23
| * drm/i915: Gather the HDMI level shifter logic into one placeDamien Lespiau2014-08-083-9/+24
| * drm/i915: Introduce FBC False Color for debug purposes.Rodrigo Vivi2014-08-084-0/+48
| * drm/i915: Align intel_dsi*.c files a bitDaniel Vetter2014-08-083-17/+17
| * drm/i915: Add support for Video Burst Mode for MIPI DSIShobhit Kumar2014-08-085-17/+57
| * drm/i915: Clarify CHV swing margin/deemph bitsVille Syrjälä2014-08-083-6/+10
| * drm/i915: Call intel_{dp, hdmi}_prepare for chvVille Syrjälä2014-08-082-0/+4
| * drm/i915: Split chv_update_pll() apartVille Syrjälä2014-08-081-11/+19
| * drm/i915: Leave DPLL ref clocks onVille Syrjälä2014-08-081-1/+1
| * drm/i915: Disable cdclk changes for chv until Punit is readyVille Syrjälä2014-08-081-0/+8
| * drm/i915: Add cdclk change support for chvVille Syrjälä2014-08-082-2/+52
| * d rm/i915: freeze display before the interrupts and GTPaulo Zanoni2014-08-081-1/+1
| * drm/i915: Make ddi_clock_gate() HSW/BDW specificDaniel Vetter2014-08-081-3/+9
| * drm/i915: Split the CDCLK retrieval per-platformDamien Lespiau2014-08-081-17/+38
| * drm/i915: Make intel_ddi_calculate_wrpll() HSW/BDW specificDamien Lespiau2014-08-081-7/+8
| * drm/i915: Split the BDW/HSW specific shared pll selectionDamien Lespiau2014-08-081-16/+23
| * drm/i915: Fix stale comment for intel_ddi_pll_select()Damien Lespiau2014-08-081-4/+5
| * drm/i915: Restrict hsw_dp_set_ddi_pll_sel() to HSW/BDWDamien Lespiau2014-08-081-1/+1
| * drm/i915: Extract the HSW/BDW shared dpll init codeDamien Lespiau2014-08-081-3/+9
| * drm/i915: Extract the HSW DDI selection code into its own functionDamien Lespiau2014-08-081-10/+17
| * drm/i915: Add a space to the shared DPLL debug messageDamien Lespiau2014-08-081-1/+1
| * drm/i915: Specify when the PLL hw state fields are validDamien Lespiau2014-08-081-0/+3
| * drm/i915: Add DP training pattern 3 for CHVVille Syrjälä2014-08-082-4/+16
| * drm/i915: Split a few long debug printsVille Syrjälä2014-08-081-2/+4
| * drm/i915: Fix read back of plane stride registerRafael Barbalho2014-08-081-2/+2
| * drm/i915: Add chv port D TX wellsVille Syrjälä2014-08-082-0/+27
| * drm/i915: Add chv port B and C TX wellsVille Syrjälä2014-08-081-0/+30
| * drm/i915: Add per-pipe power wells for chvVille Syrjälä2014-08-082-0/+138
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