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op-kernel-dev
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Development kernel branch for OpenPOWER systems
Raptor Engineering, LLC
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path:
root
/
drivers
/
gpu
/
drm
/
i915
/
intel_runtime_pm.c
Commit message (
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Author
Age
Files
Lines
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drm/i915/skl: don't toggle PW1 and MISC power wells on-demand
Imre Deak
2015-11-17
1
-27
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+9
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drm/i915/skl: init/uninit display core as part of the HW power domain state
Imre Deak
2015-11-17
1
-2
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+54
*
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drm/i915: rename intel_power_domains_resume to *_sync_hw
Imre Deak
2015-11-17
1
-2
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+2
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drm/i915: Make turning on/off PW1 and Misc I/O part of the init/fini sequences
Damien Lespiau
2015-11-17
1
-0
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+28
*
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drm/i915: fix lookup_power_well for power wells without any domain
Imre Deak
2015-11-17
1
-2
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+4
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drm/i915: fix the power well ID for always on wells
Imre Deak
2015-11-17
1
-0
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+2
*
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drm/i915/skl: Removed assert for csr-fw-loading check during disabling dc6
Animesh Manna
2015-11-12
1
-1
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+0
*
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drm/i915/gen9: Remove csr.state, csr_lock and related code.
Daniel Vetter
2015-11-12
1
-15
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+2
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drm/i915/gen9: move assert_csr_loaded into intel_rpm.c
Daniel Vetter
2015-11-12
1
-0
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+8
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drm/i915: Kill intel_runtime_pm_disable()
Ville Syrjälä
2015-11-11
1
-17
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+0
*
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drm/i915/kbl: Introduce Kabylake platform defition.
Rodrigo Vivi
2015-10-28
1
-1
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+1
*
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drm/i915/skl: Making DC6 entry is the last call in suspend flow.
Animesh Manna
2015-10-19
1
-12
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+7
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drm/i915: Skip CHV PHY asserts until PHY has been fully reset
Ville Syrjälä
2015-10-06
1
-1
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+45
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drm/i915: fixup runtime PM handling v2
Jesse Barnes
2015-09-30
1
-3
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+0
*
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drm/i915/skl: Block disable call for pw1 if dmc firmware is present.
Animesh Manna
2015-09-30
1
-3
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+9
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*
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drm/i915: make CSR firmware messages less verbose
Jesse Barnes
2015-09-14
1
-18
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+18
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Merge tag 'drm-intel-next-fixes-2015-09-02' into drm-intel-next-queued
Daniel Vetter
2015-09-02
1
-0
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+2
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\
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drm/i915/skl: Adding DDI_E power well domain
Xiong Zhang
2015-08-31
1
-0
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+2
*
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drm/i915: Add CHV PHY LDO power sanity checks
Ville Syrjälä
2015-09-01
1
-17
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+109
*
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drm/i915: Add some CHV DPIO lane power state asserts
Ville Syrjälä
2015-09-01
1
-0
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+54
*
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drm/i915: Force CL2 off in CHV x1 PHY
Ville Syrjälä
2015-08-26
1
-0
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+9
*
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drm/i915: Enable DPIO SUS clock gating on CHV
Ville Syrjälä
2015-08-26
1
-1
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+2
*
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drm/i915: Trick CL2 into life on CHV when using pipe B with port B
Ville Syrjälä
2015-08-26
1
-0
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+29
*
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drm/i915: Implement PHY lane power gating for CHV
Ville Syrjälä
2015-08-26
1
-9
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+114
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drm/i915: Move DPLL ref/cri/VGA mode frobbing to the disp2d well enable
Ville Syrjälä
2015-08-26
1
-21
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+24
*
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drm/i915: Add locking around chv_phy_control_init()
Ville Syrjälä
2015-08-26
1
-0
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+2
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/
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drm/i915: Extract a intel_power_well_disable() function
Damien Lespiau
2015-08-05
1
-5
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+10
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drm/i915: Extract a intel_power_well_enable() function
Damien Lespiau
2015-08-05
1
-5
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+10
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drm/i915: Refactor VLV display power well init/deinit
Ville Syrjälä
2015-07-13
1
-29
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+23
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drm/i915: Simplify CHV pipe A power well code
Ville Syrjälä
2015-07-13
1
-27
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+20
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drm/i915: Apply OCD to VLV/CHV DPLL defines
Ville Syrjälä
2015-07-13
1
-4
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+4
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drm/i915: Keep GMCH DPLL VGA mode always disabled
Ville Syrjälä
2015-07-13
1
-4
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+4
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drm/i915: Throw out WIP CHV power well definitions
Ville Syrjälä
2015-05-28
1
-94
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+4
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drm/i915: Use the default 600ns LDO programming sequence delay
Ville Syrjälä
2015-05-28
1
-0
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+2
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drm/i915: Fix typo in intel_runtime_pm.c
Masanari Iida
2015-05-20
1
-2
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+2
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Revert "drm/i915: Hack to tie both common lanes together on chv"
Ville Syrjälä
2015-05-08
1
-12
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+2
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drm/i915: Work around DISPLAY_PHY_CONTROL register corruption on CHV
Ville Syrjälä
2015-05-08
1
-5
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+31
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drm/i915/skl: Make the Misc I/O power well part of the PLLS domain
Damien Lespiau
2015-05-08
1
-0
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+1
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drm/i915/skl: Add the INIT power domain to the MISC I/O power well
Damien Lespiau
2015-05-08
1
-1
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+2
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drm/i915/skl: Assert the requirements to enter or exit DC6.
Suketu Shah
2015-05-08
1
-4
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+36
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Implement enable/disable for Display C6 state
A.Sunil Kamath
2015-05-08
1
-2
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+25
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drm/i915/skl: Add DC6 Trigger sequence.
Suketu Shah
2015-05-08
1
-7
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+36
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drm/i915/skl: Assert the requirements to enter or exit DC5.
Suketu Shah
2015-05-08
1
-5
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+46
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drm/i915/skl: Implement enable/disable for Display C5 state.
A.Sunil Kamath
2015-05-08
1
-2
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+39
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drm/i915/skl: Add DC5 Trigger Sequence
Suketu Shah
2015-05-08
1
-0
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+33
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drm/i915/bxt: Implement enable/disable for Display C9 state
A.Sunil Kamath
2015-04-16
1
-0
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+66
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drm/i915/bxt: Define BXT power domains
Satheeshakrishna M
2015-04-14
1
-0
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+55
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drm/i915: Spelling s/auxilliary/auxiliary/
Geert Uytterhoeven
2015-03-17
1
-3
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+3
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drm/i915/skl: Restore the DDI translation tables when enabling PW1
Damien Lespiau
2015-03-17
1
-1
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+3
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drm/i915: Remove unused condition in hsw_power_well_post_enable()
Damien Lespiau
2015-03-17
1
-1
/
+1
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