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path: root/drivers/gpu/drm/i915/intel_runtime_pm.c
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* | | | drm/i915/skl: don't toggle PW1 and MISC power wells on-demandImre Deak2015-11-171-27/+9
* | | | drm/i915/skl: init/uninit display core as part of the HW power domain stateImre Deak2015-11-171-2/+54
* | | | drm/i915: rename intel_power_domains_resume to *_sync_hwImre Deak2015-11-171-2/+2
* | | | drm/i915: Make turning on/off PW1 and Misc I/O part of the init/fini sequencesDamien Lespiau2015-11-171-0/+28
* | | | drm/i915: fix lookup_power_well for power wells without any domainImre Deak2015-11-171-2/+4
* | | | drm/i915: fix the power well ID for always on wellsImre Deak2015-11-171-0/+2
* | | | drm/i915/skl: Removed assert for csr-fw-loading check during disabling dc6Animesh Manna2015-11-121-1/+0
* | | | drm/i915/gen9: Remove csr.state, csr_lock and related code.Daniel Vetter2015-11-121-15/+2
* | | | drm/i915/gen9: move assert_csr_loaded into intel_rpm.cDaniel Vetter2015-11-121-0/+8
* | | | drm/i915: Kill intel_runtime_pm_disable()Ville Syrjälä2015-11-111-17/+0
* | | | drm/i915/kbl: Introduce Kabylake platform defition.Rodrigo Vivi2015-10-281-1/+1
* | | | drm/i915/skl: Making DC6 entry is the last call in suspend flow.Animesh Manna2015-10-191-12/+7
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* | | drm/i915: Skip CHV PHY asserts until PHY has been fully resetVille Syrjälä2015-10-061-1/+45
* | | drm/i915: fixup runtime PM handling v2Jesse Barnes2015-09-301-3/+0
* | | drm/i915/skl: Block disable call for pw1 if dmc firmware is present.Animesh Manna2015-09-301-3/+9
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* | drm/i915: make CSR firmware messages less verboseJesse Barnes2015-09-141-18/+18
* | Merge tag 'drm-intel-next-fixes-2015-09-02' into drm-intel-next-queuedDaniel Vetter2015-09-021-0/+2
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| * drm/i915/skl: Adding DDI_E power well domainXiong Zhang2015-08-311-0/+2
* | drm/i915: Add CHV PHY LDO power sanity checksVille Syrjälä2015-09-011-17/+109
* | drm/i915: Add some CHV DPIO lane power state assertsVille Syrjälä2015-09-011-0/+54
* | drm/i915: Force CL2 off in CHV x1 PHYVille Syrjälä2015-08-261-0/+9
* | drm/i915: Enable DPIO SUS clock gating on CHVVille Syrjälä2015-08-261-1/+2
* | drm/i915: Trick CL2 into life on CHV when using pipe B with port BVille Syrjälä2015-08-261-0/+29
* | drm/i915: Implement PHY lane power gating for CHVVille Syrjälä2015-08-261-9/+114
* | drm/i915: Move DPLL ref/cri/VGA mode frobbing to the disp2d well enableVille Syrjälä2015-08-261-21/+24
* | drm/i915: Add locking around chv_phy_control_init()Ville Syrjälä2015-08-261-0/+2
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* drm/i915: Extract a intel_power_well_disable() functionDamien Lespiau2015-08-051-5/+10
* drm/i915: Extract a intel_power_well_enable() functionDamien Lespiau2015-08-051-5/+10
* drm/i915: Refactor VLV display power well init/deinitVille Syrjälä2015-07-131-29/+23
* drm/i915: Simplify CHV pipe A power well codeVille Syrjälä2015-07-131-27/+20
* drm/i915: Apply OCD to VLV/CHV DPLL definesVille Syrjälä2015-07-131-4/+4
* drm/i915: Keep GMCH DPLL VGA mode always disabledVille Syrjälä2015-07-131-4/+4
* drm/i915: Throw out WIP CHV power well definitionsVille Syrjälä2015-05-281-94/+4
* drm/i915: Use the default 600ns LDO programming sequence delayVille Syrjälä2015-05-281-0/+2
* drm/i915: Fix typo in intel_runtime_pm.cMasanari Iida2015-05-201-2/+2
* Revert "drm/i915: Hack to tie both common lanes together on chv"Ville Syrjälä2015-05-081-12/+2
* drm/i915: Work around DISPLAY_PHY_CONTROL register corruption on CHVVille Syrjälä2015-05-081-5/+31
* drm/i915/skl: Make the Misc I/O power well part of the PLLS domainDamien Lespiau2015-05-081-0/+1
* drm/i915/skl: Add the INIT power domain to the MISC I/O power wellDamien Lespiau2015-05-081-1/+2
* drm/i915/skl: Assert the requirements to enter or exit DC6.Suketu Shah2015-05-081-4/+36
* Implement enable/disable for Display C6 stateA.Sunil Kamath2015-05-081-2/+25
* drm/i915/skl: Add DC6 Trigger sequence.Suketu Shah2015-05-081-7/+36
* drm/i915/skl: Assert the requirements to enter or exit DC5.Suketu Shah2015-05-081-5/+46
* drm/i915/skl: Implement enable/disable for Display C5 state.A.Sunil Kamath2015-05-081-2/+39
* drm/i915/skl: Add DC5 Trigger SequenceSuketu Shah2015-05-081-0/+33
* drm/i915/bxt: Implement enable/disable for Display C9 stateA.Sunil Kamath2015-04-161-0/+66
* drm/i915/bxt: Define BXT power domainsSatheeshakrishna M2015-04-141-0/+55
* drm/i915: Spelling s/auxilliary/auxiliary/Geert Uytterhoeven2015-03-171-3/+3
* drm/i915/skl: Restore the DDI translation tables when enabling PW1Damien Lespiau2015-03-171-1/+3
* drm/i915: Remove unused condition in hsw_power_well_post_enable()Damien Lespiau2015-03-171-1/+1
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