summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/i915/intel_dsi_pll.c
Commit message (Collapse)AuthorAgeFilesLines
* drm/i915/dsi: Using the bpp value wrt the pixel formatDeepak M2016-02-191-1/+1
| | | | | | | | | | | | | | | | The bpp value which is used while calulating the txbyteclkhs values should be wrt the pixel format value. Currently bpp is coming from pipe config to calculate txbyteclkhs. Fix it in this patch. V2: dsi_pixel_format_bpp is used to retrieve the bpp from pixel_format [Review: Jani] Signed-off-by: Deepak M <m.deepak@intel.com> Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com> Signed-off-by: Ramalingam C <ramalingam.c@intel.com> Tested-by: Mika Kahola <mika.kahola@intel.com> # BYT Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1455203007-10850-1-git-send-email-ramalingam.c@intel.com
* drm/i915/dsi: remove unused dsi_rr_formula()Jani Nikula2016-01-081-81/+0
| | | | | | | | | | | | | | | | | | | The dsi_rr_formula() function has been unused for almost two years, since commit 44d4c6eebb2ef04f698c292bb6eda5f2e80c663b Author: Shobhit Kumar <shobhit.kumar@intel.com> Date: Tue Dec 10 12:14:56 2013 +0530 drm/i915: Compute dsi_clk from pixel clock citing the reason as pixel clock based calculation being recommended in the MIPI host controller documentation. Remove the dead code, we can always bring it back if it's needed. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1452249940-2605-2-git-send-email-jani.nikula@intel.com
* drm/i915/dsi: abstract get pclk platform differencesJani Nikula2016-01-081-2/+10
| | | | | | | | | Hide away the platform differences in intel_dsi_get_pckl() within intel_dsi_pll.c. No functional changes. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1452249940-2605-1-git-send-email-jani.nikula@intel.com
* drm/i915: Separate cherryview from valleyviewWayne Boyer2015-12-101-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | The cherryview device shares many characteristics with the valleyview device. When support was added to the driver for cherryview, the corresponding device info structure included .is_valleyview = 1. This is not correct and leads to some confusion. This patch changes .is_valleyview to .is_cherryview in the cherryview device info structure and simplifies the IS_CHERRYVIEW macro. Then where appropriate, instances of IS_VALLEYVIEW are replaced with IS_VALLEYVIEW || IS_CHERRYVIEW or equivalent. v2: Use IS_VALLEYVIEW || IS_CHERRYVIEW instead of defining a new macro. Also add followup patches to fix issues discovered during the first review. (Ville) v3: Fix some style issues and one gen check. Remove CRT related changes as CRT is not supported on CHV. (Imre, Ville) v4: Make a few more optimizations. (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Wayne Boyer <wayne.boyer@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1449692975-14803-1-git-send-email-wayne.boyer@intel.com Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com>
* drm/i915/bxt: vlv_dsi_reset_clocks() can be statickbuild test robot2015-10-061-2/+2
| | | | | | Signed-off-by: Fengguang Wu <fengguang.wu@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915/bxt: get DSI pixelclockShashank Sharma2015-10-021-0/+35
| | | | | | | | | | | | | | | BXT's DSI PLL is different from that of VLV. So this patch adds a new function to get the current DSI pixel clock based on the PLL divider ratio and lane count. This function is required for intel_dsi_get_config() function. v2: Fixed Jani's review comments. Signed-off-by: Shashank Sharma <shashank.sharma@intel.com> Signed-off-by: Uma Shankar <uma.shankar@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915/bxt: DSI disable and post-disableShashank Sharma2015-10-021-0/+39
| | | | | | | | | | | | | | | | | | | | | | This patch contains changes to support DSI disble sequence in BXT. The changes are: 1. BXT specific changes in clear_device_ready function. 2. BXT specific changes in DSI disable and post-disable functions. 3. Add a new function to reset BXT Dphy clock and dividers (bxt_dsi_reset_clocks). 4. Moved some part of the vlv clock reset code, in a new function (vlv_dsi_reset_clocks) maintaining the exact same sequence. 5. Wrapper function to call corresponding reset clock function. v2: Fixed Jani's review comments. v3: Removed the GET_DSI_PORT_CTRL Macro for consistency with earlier implementations as per Jani's suggestion. Signed-off-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915/bxt: Program Tx Rx and Dphy clocksShashank Sharma2015-10-021-0/+42
| | | | | | | | | | | | | | | | | | | | | | | BXT DSI clocks are different than previous platforms. So adding a new function to program following clocks and dividers: 1. Program variable divider to generate input to Tx clock divider (Output value must be < 39.5Mhz) 2. Select divide by 2 option to get < 20Mhz for Tx clock 3. Program 8by3 divider to generate Rx clock v2: Fixed Jani's review comments. Adjusted the Macro definition as per convention. Simplified the logic for bit definitions for MIPI PORT A and PORT C in same registers. v3: Refactored the macros for TX, RX Escape and DPHY clocks as per Jani's suggestion. v4: Addressed Jani's review comments. Signed-off-by: Shashank Sharma <shashank.sharma@intel.com> Signed-off-by: Uma Shankar <uma.shankar@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915/bxt: Disable DSI PLL for BXTShashank Sharma2015-09-231-1/+31
| | | | | | | | | | | | | | | | | | | | This patch adds two new functions: - disable_dsi_pll. BXT DSI disable sequence and registers are different from previous platforms. - intel_disable_dsi_pll wrapper function to re-use the same code for multiple platforms. It checks platform type and calls appropriate core pll disable function. v2: Fixed Jani's review comments. v3: Rebased on latest drm-nightly branch. Signed-off-by: Shashank Sharma <shashank.sharma@intel.com> Signed-off-by: Uma Shankar <uma.shankar@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915/bxt: Enable BXT DSI PLLShashank Sharma2015-09-231-1/+94
| | | | | | | | | | | | | | | | | | | | | | This patch adds new functions for BXT clock and PLL programming. They are: 1. configure_dsi_pll for BXT. This function does the basic math and generates the divider ratio based on requested pixclock, and program clock registers. 2. enable_dsi_pll function. This function programs the calculated clock values on the PLL. 3. intel_enable_dsi_pll Wrapper function to use same code for multiple platforms. It checks the platform and calls appropriate core pll enable function. v2: Fixed Jani's review comments. Macros are adjusted as per convention. v3: Removed a redundant change wrt code comment. Signed-off-by: Shashank Sharma <shashank.sharma@intel.com> Signed-off-by: Uma Shankar <uma.shankar@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Changes required to enable DSI Video Mode on CHTGaurav K Singh2015-07-031-6/+20
| | | | | | | | | | | | | | | | | On CHT, changes are required for calculating the correct m,n & p with minimal error +/- for the required DSI clock, so that the correct dividor & ctrl values are written in cck regs for DSI. This patch has been tested on CHT RVP with 1200 x 1920 panel. v2 by Jani, rebased on earlier refactoring, original at [1]. [1] http://mid.gmane.org/1431368400-1942-5-git-send-email-rodrigo.vivi@intel.com Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Support for higher DSI clkGaurav K Singh2015-07-031-2/+2
| | | | | | | | | | | | | For MIPI panels requiring higher DSI clk, values needs to be added in lfsr_converts table for getting the correct values of pll ctrl and dividor values which gets programmed in cck regs, otherwise DSI PLL does not get locked leading to no display on the MIPI panel. Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915/dsi: abstract dsi bpp derivation from pixel formatJani Nikula2015-07-031-43/+24
| | | | | | | | | | | Nuke three copies of the same switch case. Hopefully we can switch to a drm generic function later on, but that will require us to swich to enum mipi_dsi_pixel_format first. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: s/dpio_lock/sb_lock/Ville Syrjälä2015-05-281-7/+7
| | | | | | | | | | Rename dpio_lock to sb_lock to inform the reader that its primary purpose is to protect the sideband mailbox rather than some DPIO state. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915/dsi: add support for DSI PLL N1 divisor valuesJani Nikula2015-05-201-6/+11
| | | | | | | | | | | Currently DSI PLL N1 is hardcoded off. Make it possible to use it later. This should have no functional changes for now. v2: s/ffz(~(n))/ffs(n) - 1/ (Ville) Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: clean up dsi pll calculationJani Nikula2015-05-201-36/+17
| | | | | | | | | | Improve readability. No functional changes. v2: use more rational types (Ville) Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Use DSI Pll1 for enabling MIPI DSI on Port CGaurav K Singh2014-12-101-2/+3
| | | | | | | | | | | DSI Pll1 is used for enabling DSI on Port C. v2: Addressed review comments of Jani - Used & operator instead of == for intel_dsi->ports Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: cck reg used for checking DSI Pll lockedGaurav K Singh2014-12-051-2/+4
| | | | | | | | | | | | Instead of pipe configuration reg, cck reg to be used for checking whether DSI Pll is getting locked or not. v2: dpio_lock unlocked now in case DSI PLL lock fails Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com> Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Enable DSI PLL for both DSI0 and DSI1 in case of dual linkGaurav K Singh2014-12-051-0/+3
| | | | | | | | | | | | | | For Dual link MIPI Panels, dsipll clock for both DSI0 and DSI1 needs to be enabled. v2: Address review comments by Jani - Added wait time for PLL to be locked. v3: separate patch created for cck read for checking PLL to be locked Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com> Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Align intel_dsi*.c files a bitDaniel Vetter2014-08-081-4/+4
| | | | | | | | | | I'm not really that insisting on checkpath compliance, but ragged function paramter alignment does get me. Please adjust your editor to just do this for you. Cc: Shobhit Kumar <shobhit.kumar@intel.com> Cc: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Add support for Video Burst Mode for MIPI DSIShobhit Kumar2014-08-081-6/+3
| | | | | | | | v2: Updated the error log as suggested by Imre Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Add correct hw/sw config check for DSI encoderShobhit Kumar2014-08-071-0/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | Check in vlv_crtc_clock_get if DPLL is enabled before calling dpio read. It will not be enabled for DSI and avoid dpio read WARN dumps. Absence of ->get_config was causing other WARN dumps as well. Update dpll_hw_state as well correctly v2: Address review comments by Daniel - Check if DPLL is enabled rather than checking pipe output type - set adjusted_mode->flags to 0 in compute_config rather than using pipe_config->quirks - Add helper function in intel_dsi_pll.c and use that in intel_dsi.c - updated dpll_hw_state correctly - Updated commit message and title v3: Address review comments by Imre - Proper masking of P1, M1 fields while computing divisors - assert in case of bpp mismatch - guard for divide by 0 while computing pclk - Use ARRAY_SIZE instead of direct calculation Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Try harder to get best m, n, p values with minimal errorShobhit Kumar2013-12-111-10/+20
| | | | | | | | | | | | | Basically check for both +ive and -ive deviation from target clock and pick the one with minimal error. If we get a direct match, break from loop to acheive some optimization. v2: Use signed variable for target and calculated dsi clock values Signed-off-by: Vijayakumar Balakrishnan <vijayakumar.balakrishnan@intel.com> Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Compute dsi_clk from pixel clockShobhit Kumar2013-12-111-58/+31
| | | | | | | | | | | | | | | | | | | Pixel clock based calculation is recommended in the MIPI host controller documentation v2: Based on review comments from Jani and Ville - Use dsi_clk in KHz rather than converting in Hz and back to MHz - RR formula is retained though not used but return dsi_clk in KHz now - Moved the m-n-p changes into a separate patch - Removed the parameter check for intel_dsi->dsi_clock_freq. This will be bought back in if needed when appropriate panel drivers are done v3: Removed the unused mnp calculation from static table Signed-off-by: Vijayakumar Balakrishnan <vijayakumar.balakrishnan@intel.com> Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Use adjusted_mode in DSI PLL calculationsVille Syrjälä2013-09-161-2/+2
| | | | | | | | | | | adjusted_mode contains our real timings, not requested_mode. Use the correct thing in DSI PLL code. Also constify adjusted_mode since we don't change it. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: add VLV DSI PLL Calculationsymohanma2013-09-041-0/+317
v2: - Grab dpio_lock mutex in vlv_enable_dsi_pll(). - Add and call vlv_disable_dsi_pll(). v3: Mostly based on Ville's review comments. - Only pipe A has DSI PLL lock bit. - Add more of CCK REG bit definitions for DSI PLL. - Make tables static. - Move clock gating out of the clock calculation functions. - DSI PLL LDO power gating. - Put alternative MNP from table calc behind #ifdef. v4: s/CKK/CLK/ in the CCK REG bit definitions (Ville). Signed-off-by: ymohanma <yogesh.mohan.marimuthu@intel.com> Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
OpenPOWER on IntegriCloud