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path: root/drivers/gpu/drm/i915/i915_suspend.c
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* Merge tag 'v3.5-rc7' into drm-nextDave Airlie2012-07-201-1/+4
|\ | | | | | | | | | | | | | | | | | | | | | | Merge Linus tree into drm to fixup conflicts in radeon code for further testing before upstream merge. Signed-off-by: Dave Airlie <airlied@redhat.com> Conflicts: drivers/gpu/drm/i915/i915_dma.c drivers/gpu/drm/i915/intel_display.c drivers/gpu/drm/radeon/radeon_gart.c
| * drm/i915: Fix eDP blank screen after S3 resume on HP desktopsTakashi Iwai2012-06-231-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes the problem on some HP desktop machines with eDP which give blank screens after S3 resume. It turned out that BLC_PWM_CPU_CTL must be written after BLC_PWM_CPU_CTL2. Otherwise it doesn't take effect on these SNB machines. Tested with 3.5-rc3 kernel. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=49233 Cc: <stable@vger.kernel.org> Signed-off-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: wrap up gt powersave enabling functionsDaniel Vetter2012-06-251-4/+1
|/ | | | | | | | | | | | ... instead of calling each one for each generation indiviudally. Notice that we've already managed to be inconsistent, the resume path is missing an IS_VLV check. As a nice benefit we can mark all the platform specific enable/disable functions as static and hide them in intel_pm.c Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com> Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: gen6_enable_rps() wants to be called after ring initialisationChris Wilson2012-05-191-6/+0
| | | | | | | | | | | | | | | Currently we call gen6_enable_rps() (which writes into the per-ring register mmio space) from intel_modeset_init_hw() which is called before we initialise the rings. If we defer intel_modeset_init_hw() until afterwards (in the intel_modeset_gem_init() phase) all is well. v2: Rectify ordering of gem vs display HW init upon resume. (Daniel) v3: Fix up locking. (Paulo) Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> [danvet: Smash Paulo's locking fix onto Chris' patch.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: manage PCH PLLs separately from pipesJesse Barnes2012-05-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | PCH PLLs aren't required for outputs on the CPU, so we shouldn't just treat them as part of the pipe. So split the code out and manage PCH PLLs separately, allocating them when needed or trying to re-use existing PCH PLL setups when the timings match. v2: add num_pch_pll field to dev_priv (Daniel) don't NULL the pch_pll pointer in disable or DPMS will fail (Jesse) put register offsets in pll struct (Chris) v3: Decouple enable/disable of PLLs from get/put. v4: Track temporary PLL disabling during modeset v5: Tidy PLL initialisation by only checking for num_pch_pll == 0 (Eugeni) v6: Avoid mishandling allocation failure by embedding the small array of PLLs into the device struct Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=44309 Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> (up to v2) Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> (v3+) Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com> Tested-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: re-init modeset hw state after gpu resetDaniel Vetter2012-04-121-11/+1
| | | | | | | | | | | | | | | | | | | | | | | | After a gpu reset we need to re-init some of the hw state we only initialize when modeset is enabled, like rc6, hw contexts or render/GT core clock gating and workaround register settings. Note that this patch has a small change in the resume code: - rc6 on gen6+ is only restored for the modeset case (for more consistency with other callsites). This is no problem because recent kernels refuse to load drm/i915 without kms on gen6+ - rc6/emon on ilk is only restored for the modeset case. This is no problem because rc6 is disabled by default on ilk, and ums on ilk has never really been a supported option outside of horrible rhel backports. v2: Chris Wilson noticed that we not only fail to restore the clock gating settings after gpu reset. v3: Move the call to modeset_init_hw in _reset out of the struct_mutext protected area - other callers don't hold it, too. Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Re-enable gen7 RC6 and GPU turbo after resume.Eric Anholt2012-01-241-2/+2
| | | | | | | | | Signed-off-by: Eric Anholt <eric@anholt.net> Cc: stable@vger.kernel.org Reviewed-by: Keith Packard <keithp@keithp.com> Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Keith Packard <keithp@keithp.com>
* drm/i915: handle 3rd pipeEugeni Dodonov2012-01-091-0/+4
| | | | | | | | | We don't need to check 3rd pipe specifically, as it shares PLL with some other one. Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Keith Packard <keithp@keithp.com>
* drm/i915: simplify pipe checkingEugeni Dodonov2012-01-091-1/+2
| | | | | | | | | | This is also handled by i915_reg.h, so just reuse this trick to reduce universe entropy. Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Cyril Brulebois <kibi@debian.org> Signed-off-by: Keith Packard <keithp@keithp.com>
* drm/i915: Ivybridge still has fences!Daniel Vetter2011-11-031-0/+2
| | | | | | | | | | So don't forget to restore them on resume and dump them into the error state. Cc: stable@kernel.org Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Keith Packard <keithp@keithp.com>
* Drivers: i915: Fix all space related issues.Akshay Joshi2011-09-191-4/+4
| | | | | | | | | Various issues involved with the space character were generating warnings in the checkpatch.pl file. This patch removes most of those warnings. Signed-off-by: Akshay Joshi <me@akshayjoshi.com> Signed-off-by: Keith Packard <keithp@keithp.com>
* drm/i915: Cannot set clock gating under UMSKeith Packard2011-08-151-1/+2
| | | | | | | | The clock gating functions are only assigned under KMS, so don't try to call them under UMS. Signed-off-by: Keith Packard <keithp@keithp.com> Tested-by: Justin P. Mattock <justinmattock@gmail.com>
* Merge branch 'drm-intel-fixes' into drm-intel-nextKeith Packard2011-07-291-0/+2
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| * drm/i915/pch: Save/restore PCH_PORT_HOTPLUG across suspendAdam Jackson2011-07-291-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At least on a Lenovo X220 the HPD bits of this are enabled at boot but cleared after resume, which means plug interrupts stop working. This also happens to fix DP displays re-lighting on resume. I'm quite certain that's an accident: the first DP link train inevitably fails on that machine, and it's only serendipity that we're getting multiple plug interrupts and the second train works. But I shall take my victories where I get them. Signed-off-by: Adam Jackson <ajax@redhat.com> Tested-by: Keith Packard <keithp@keithp.com> Reviewed-by: Keith Packard <keithp@keithp.com> Signed-off-by: Keith Packard <keithp@keithp.com>
* | drm/i915: Only export the generic intel_disable_fbc() interfaceChris Wilson2011-07-081-3/+1
| | | | | | | | | | | | | | | | | | | | | | As the enable/disable routines will be gain additional complexity in future patches, it is necessary that all callers do not bypass the generic interface by calling into the chipset routines directly. to do this we make the chipset routines static, so there is no choice. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Keith Packard <keithp@keithp.com>
* | Merge branch 'drm-intel-fixes' into drm-intel-nextKeith Packard2011-06-291-6/+13
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| * drm/i915: Hold struct_mutex during i915_save_state/i915_restore_stateKeith Packard2011-06-291-6/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Lots of register access in these functions, some of which requires the struct mutex. These functions now hold the struct mutex across the calls to i915_save_display and i915_restore_display, and so the internal mutex calls in those functions have been removed. To ensure that no-one else was calling them (and hence violating the new required locking invarient), those functions have been made static. gen6_enable_rps locks the struct mutex, and so i915_restore_state unlocks the mutex around calls to that function. Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Keith Packard <keithp@keithp.com>
* | drm/i915: load a ring frequency scaling table v3Jesse Barnes2011-06-281-1/+3
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | The ring frequency scaling table tells the PCU to treat certain GPU frequencies as if they were a given CPU frequency for purposes of scaling the ring frequency. Normally the PCU will scale the ring frequency based on the CPU P-state, but with the table present, it will also take the GPU frequency into account. The main downside of keeping the ring frequency high while the CPU is at a low frequency (or asleep altogether) is increased power consumption. But then if you're keeping your GPU busy, you probably want the extra performance. v2: - add units to debug table header (from Eric) - use tsc_khz as a fallback if the cpufreq driver doesn't give us a freq (from Chris) v3: - fix comments & debug output - remove unneeded force wake get/put Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Tested-by: Eric Anholt <eric@anholt.net> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Keith Packard <keithp@keithp.com>
* drm/i915: save/resume forcewake lock fixesBen Widawsky2011-06-221-0/+5
| | | | | | | | | | The lock must be held for the saving and restoring of VGA state. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> CC: Alexander Zhaunerchyk <alex.vizor@gmail.com> CC: Andrey Rahmatullin <wrar@wrar.name> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Keith Packard <keithp@keithp.com>
* drm/i915: split PCH clock gating initJesse Barnes2011-05-131-2/+1
| | | | | | | | | Ibex Peak and CougarPoint already require a different setting (added here), and future chips will likely follow that precedent. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Keith Packard <keithp@keithp.com> Signed-off-by: Keith Packard <keithp@keithp.com>
* drm/i915: split clock gating init into per-chipset functionsJesse Barnes2011-05-131-1/+1
| | | | | | | | This helps contain the mess to init_display() instead. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Keith Packard <keithp@keithp.com> Signed-off-by: Keith Packard <keithp@keithp.com>
* Revert "drm/i915: Don't save/restore hardware status page address register"Chris Wilson2011-03-231-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit a7a75c8f70d6f6a2f16c9f627f938bbee2d32718. There are two different variations on how Intel hardware addresses the "Hardware Status Page". One as a location in physical memory and the other as an offset into the virtual memory of the GPU, used in more recent chipsets. (The HWS itself is a cacheable region of memory which the GPU can write to without requiring CPU synchronisation, used for updating various details of hardware state, such as the position of the GPU head in the ringbuffer, the last breadcrumb seqno, etc). These two types of addresses were updated in different locations of code - one inline with the ringbuffer initialisation, and the other during device initialisation. (The HWS page is logically associated with the rings, and there is one HWS page per ring.) During resume, only the ringbuffers were being re-initialised along with the virtual HWS page, leaving the older physical address HWS untouched. This then caused a hang on the older gen3/4 (915GM, 945GM, 965GM) the first time we tried to synchronise the GPU as the breadcrumbs were never being updated. Reported-and-tested-by: Linus Torvalds <torvalds@linux-foundation.org> Reported-by: Jan Niehusmann <jan@gondor.com> Reported-by: Justin P. Mattock <justinmattock@gmail.com> Reported-and-tested-by: Michael "brot" Groh <brot@minad.de> Cc: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* drm/i915: Don't save/restore hardware status page address registerZhenyu Wang2011-03-021-6/+0
| | | | | | | | | It's cleaned before saving and re-initialized after restoring. So don't need to save/restore it. And also new chip has new address for hardware status page register, don't write to old address. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: cleanup per-pipe reg usageJesse Barnes2011-02-071-215/+214
| | | | | | | | | | | | | We had some conversions over to the _PIPE macros, but didn't get everything. So hide the per-pipe regs with an _ (still used in a few places for legacy) and add a few _PIPE based macros, then make sure everyone uses them. [update: remove usage of non-existent no-op macro] [update 2: keep modesetting suspend/resume code, update to new reg names] Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> [ickle: stylistic cleanups for checkpatch and taste] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: cleanup rc6 codeJesse Barnes2011-01-111-4/+3
| | | | | | | | | | | | | | Cleanup several aspects of the rc6 code: - misnamed intel_disable_clock_gating function (was only about rc6) - remove commented call to intel_disable_clock_gating - rc6 enabling code belongs in its own function (allows us to move the actual clock gating enable call back into restore_state) - allocate power & render contexts up front, only free on unload (avoids ugly lazy init at rc6 enable time) Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> [ickle: checkpatch cleanup] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: fix rc6 enabling around suspend/resumeJesse Barnes2011-01-111-3/+0
| | | | | | | | | Enabling RC6 implies setting a graphics context. Make sure we do that only after the ring has been enabled, otherwise our ring commands will hang. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: re-enable rc6 support for Ironlake+Jesse Barnes2011-01-111-2/+2
| | | | | | | | | | | | | Re-enable rc6 support on Ironlake for power savings. Adds a debugfs file to check current RC state, adds a missing workaround for Ironlake MI_SET_CONTEXT instructions, and renames MCHBAR_RENDER_STANDBY to RSTDBYCTL to match the docs. Keep RC6 and the power context disabled on pre-ILK. It only seems to hang and doesn't save any power. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Undo "Uncouple render/power ctx before suspending"Chris Wilson2010-12-201-0/+2
| | | | | | | | | | | | | | Manaul revert of 0cdab21f9a1fca50dd27e488839f5a6578e333b2, just to remove the call to disable the clock gatings and powerctx before suspend. Peter Clifton bisected a suspend failure on his gme45 and found this to be the culprit. As this was intended to be a fix for a similar suspend failure for Ironlake (it didn't work), undoing this patch should have no other side-effects. Reported-and-tested-by: Peter Clifton <pcjc2@cam.ac.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: dynamic render p-state support for Sandy BridgeJesse Barnes2010-12-181-2/+7
| | | | | | | | | Add an interrupt handler for switching graphics frequencies and handling PM interrupts. This should allow for increased performance when busy and lower power consumption when idle. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Uncouple render/power ctx before suspendingChris Wilson2010-12-051-1/+3
| | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Only save and restore fences for UMSChris Wilson2010-11-251-43/+46
| | | | | | | With KMS, we can simply relinquish the fence when we idle the GPU and reassign it upon first use. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Only save/restore cursor regs if !KMSChris Wilson2010-11-211-20/+20
| | | | | | | | | | | | | | | | Under KMS, restoring the cursor is handled upon modeswitch in order to avoid enabling an undefined set of registers. At the moment, the cursor is restored before the aperture and modes are fully setup causing some invalid access during resume, such as: PGTBL_ER: 0x00040000 Invalid GTT entry during Cursor Fetch Fix this by only performing cursor register save/restore under UMS where it is done in the correct sequence. Reported-by: Arkadiusz Miskiewicz <arekm@maven.pl> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* i915: reprogram power monitoring registers on resumeKyle McMartin2010-11-031-1/+3
| | | | | | | | | | | Fixes issue where i915_gfx_val was reporting values several orders of magnitude higher than physically possible (without leaving scorch marks on my thighs at least.) Signed-off-by: Kyle McMartin <kyle@redhat.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Cc: stable@kernel.org Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: INTEL_INFO->gen supercedes i8xx, i9xx, i965gChris Wilson2010-09-211-12/+12
| | | | | | | Avoid confusion between i965g meaning broadwater and the gen4+ chipset families. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* Merge branch 'drm-intel-fixes' into HEADChris Wilson2010-09-211-9/+27
|\ | | | | | | | | | | Conflicts: drivers/char/agp/intel-agp.c drivers/gpu/drm/i915/intel_crt.c
| * drm/i915: Fix Sandybridge fence registersChris Wilson2010-09-171-9/+27
| | | | | | | | | | | | | | | | | | | | | | With 5 places to update when adding handling for fence registers, it is easy to overlook one or two. Correct that oversight, but fence management should be improved before a new set of registers is added. Bugzilla: https://bugs.freedesktop.org/show_bug?id=30199 Original patch by: Yuanhan Liu <yuanhan.liu@intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org
* | drm/i915: use GMBUS to manage i2c linksChris Wilson2010-09-181-3/+1
|/ | | | | | | | | | | | | | Use the GMBUS interface rather than direct bit banging to grab the EDID over DDC (and for other forms of auxiliary communication with external display controllers). The hope is that this method will be much faster and more reliable than bit banging for fetching EDIDs from buggy monitors or through switches, though we still preserve the bit banging as a fallback in case GMBUS fails. Based on an original patch by Jesse Barnes. Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915/suspend: s/IS_IRONLAKE/HAS_PCH_SPLIT/Chris Wilson2010-08-211-37/+37
| | | | | | | For the shared paths on the next generation chipsets. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915/suspend: Flush register writes before busy-waiting.Chris Wilson2010-08-211-9/+18
| | | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Add frame buffer compression support on Ironlake mobileZhao Yakui2010-08-011-2/+7
| | | | | | | | About 0.2W power can be saved on one HP laptop. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Only save/restore FBC on the platform that supports FBCZhao Yakui2010-04-121-19/+22
| | | | | Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
* drm/i915: Deobfuscate the render p-state obfuscationMatthew Garrett2010-02-221-2/+4
| | | | | | | | The ironlake render p-state support includes some rather odd variable names. Clean them up in order to improve the readability of the code. Signed-off-by: Matthew Garrett <mjg@redhat.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: add dynamic performance control support for IronlakeJesse Barnes2010-02-221-0/+8
| | | | | | | | | | | | | | | | | Ironlake (and 965GM, which this patch doesn't support) supports a hardware performance and power management feature that allows it to adjust to changes in GPU load over time with software help. The goal if this is to maximize performance/power for a given workload. This patch enables that feature, which is also a requirement for supporting Intelligent Power Sharing, a feature which allows for dynamic budgeting of power between the CPU and GPU in Arrandale platforms. Tested-by: ykzhao <yakui.zhao@intel.com> [anholt: Resolved against the irq handler loop removal] Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Fix RC6 suspend/resumeAndrew Lutomirski2010-01-061-12/+0
| | | | | | | | | We restored RC6 twice on resume, even with modesetting off. Instead, only restore it once and skip RC6 initialization entirely in non-KMS mode. Signed-off-by: Andy Lutomirski <luto@mit.edu> Tested-by: Jeff Chua <jeff.chua.linux@gmail.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* Merge remote branch 'anholt/drm-intel-next' into drm-linusDave Airlie2009-12-101-6/+1
|\ | | | | | | Pull more Intel changes in, especially one to init the GTT properly
| * drm/i915: restore render clock gating on resumeAndrew Lutomirski2009-12-081-6/+1
| | | | | | | | | | | | | | | | | | Rather than restoring just a few clock gating registers on resume, just reinitialize the whole thing. Signed-off-by: Andy Lutomirski <luto@mit.edu> [anholt: Fixed up for RC6 support landed since the patch was written] Signed-off-by: Eric Anholt <eric@anholt.net>
* | Merge remote branch 'anholt/drm-intel-next' into drm-linusDave Airlie2009-12-081-36/+43
|\ \ | |/ | | | | | | | | | | | | | | | | | | This merges the upstream Intel tree and fixes up numerous conflicts due to patches merged into Linus tree later in -rc cycle. Conflicts: drivers/char/agp/intel-agp.c drivers/gpu/drm/drm_dp_i2c_helper.c drivers/gpu/drm/i915/i915_irq.c drivers/gpu/drm/i915/i915_suspend.c
| * drm/i915: Fix product names and #definesAdam Jackson2009-12-071-30/+30
| | | | | | | | | | | | | | | | | | IGD* isn't a useful name. Replace with the codenames, as sourced from pci.ids. Signed-off-by: Adam Jackson <ajax@redhat.com> [anholt: Fixed up for merge with pineview/ironlake changes] Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Fix DDC on some systems by clearing BIOS GMBUS setup.Eric Anholt2009-12-011-1/+4
| | | | | | | | | | | | | | | | This is a sync of a fix I made in the old UMS code. If the BIOS uses the GMBUS and doesn't clear that setup, then our bit-banging I2C can fail, leading to monitors not being detected. Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: add render standby supportJesse Barnes2009-11-051-2/+6
| | | | | | | | | | | | | | | | | | | | Render standy allows the GPU to power down the render unit when idle. In order for this to work, it needs a page of graphics memory to save state. This patch allocates that page and enables the feature on supported chipsets. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
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