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path: root/drivers/gpu/drm/i915/i915_reg.h
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* drm/i915: Add eDP support on IGDNG mobile chipZhenyu Wang2009-07-291-0/+16
| | | | | | | | | | | | | This adds embedded DisplayPort support on next mobile chip which aims to replace origin LVDS port. VBT's driver feature block has been used to determine the type of current internal panel for eDP or LVDS. Currently no panel fitting support for eDP and backlight control would be added in future. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: enable DisplayPort support on IGDNGZhenyu Wang2009-07-291-0/+25
| | | | | Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: fix issue in display pipe setup on IGDNGZhenyu Wang2009-07-291-0/+2
| | | | | | | | | | | During pipe DPMS off, instead of busy waiting pipe off, insert delays during wait and don't loop after enough tries which matches spec requirement. Also try to match DPMS on path by disable FDI TX PLL in DPMS off. Disable PF by writing PF_WIN_SZ which really trigger the update. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: FIFO watermark calculation fixesJesse Barnes2009-07-141-1/+1
| | | | | | | | | | | | | | | | | | | | | I discovered several bugs in the FIFO code that was recently applied. Some of them fell into the "how did this ever work" category, since in some cases we were using the wrong FIFO size values, and the calculations ended up being way off. This patch fixes all the bugs I found, and works well on my GM45, 915GM and 855GM test machines; but as usual with these sorts of patches broader testing is definitely requested (in particular this patch affects 830, 845 and 865 for which I don't have test hardware). Overall, the patch clarifies the watermark calculation function by adding some comments and debug info, and making the variable names a bit clearer. The "get FIFO size" portion of the code has also been corrected, so we should be able to properly detect the FIFO allocations for each pipe, for use in the watermark calculation. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: add FIFO watermark supportShaohua Li2009-07-011-4/+42
| | | | | | | | | | | | | | | This patch from jbarnes and myself adds FIFO watermark control to the driver. This is needed for both power saving features on new platforms with the so-called "big FIFO" and for controlling FIFO allocation between pipes in multi-head configurations. It's also necessary infrastructure to support things like framebuffer compression and configuration supportability checks (i.e. checking a configuration against available bandwidth). Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: enable error detection & state collectionJesse Barnes2009-07-011-0/+14
| | | | | | | | | | | | This patch enables error detection by enabling several types of error interrupts. When an error interrupt is received, the interrupt handler captures the error state; hopefully resulting in an accurate set of error data (error type, active head pointer, etc.). The new record is then available from sysfs. The current code will also dump the error state to the system log. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Add support for changing LVDS panel fitting using an output property.Zhao Yakui2009-06-221-0/+16
| | | | | | | | | | | Previously the driver would always scale the chosen video mode to fill the panel. This adds 1:1 and maintain-aspect-ratio scaling modes. v2: the drm_calloc/drm_free is replaced by kzalloc/kfree based on Eric's suggestion. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Add CLKCFG register definitionKeith Packard2009-06-181-0/+13
| | | | | | | The CLKCFG register holds information about the GMCH plls and input clock values. Signed-off-by: Keith Packard <keithp@keithp.com>
* drm/i915: Add Display Port register definesKeith Packard2009-06-051-0/+163
| | | | | | | | | This adds the register definitions for the display port enable register along with those for the GMCH and Link M/N ratios required to drive display port outputs. Signed-off-by: Keith Packard <keithp@keithp.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Set correct TV detection voltage level override valuesMa Ling2009-06-051-3/+3
| | | | | | | | | | | We detect TV connect status by setting DAC voltage level override values as 0.7 voltage for DAC_A/B/C. The corresponding 2-bits shold be 0x2, In order correctly to set last bit as 0, at first we must clean it. It fixed freedesktop.org bug #21204 Signed-off-by: Ma Ling <ling.ma@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Add new chipset register definitionsZhenyu Wang2009-06-051-0/+447
| | | | | Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Fix tiling pitch handling on 8xx.Eric Anholt2009-05-261-1/+2
| | | | | | | | | | | | | The pitch field is an exponent on pre-965, so we were rejecting buffers on 8xx that we shouldn't have. 915 got lucky in that the largest legal value happened to match (8KB / 512 = 0x10), but 8xx has a smaller tile width. Additionally, we programmed that bad value into the register on 8xx, so the only pitch that would work correctly was 4096 (512-1023 pixels), while others would probably give bad rendering or hangs. Signed-off-by: Eric Anholt <eric@anholt.net> fd.o bug #20473.
* i915: support 8xx desktop cursorsJesse Barnes2009-05-221-0/+17
| | | | | | | | | | For some reason we never added 8xx desktop cursor support to the kernel. This patch fixes that. [krh: Also set the size on pre-i915 hw.] Tested-by: Kristian Høgsberg <krh@redhat.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: workaround IGD i2c bus issue in kernel side (v2)Shaohua Li2009-05-141-0/+1
| | | | | | | | | | In IGD, DPCUNIT_CLOCK_GATE_DISABLE bit should be set, otherwise i2c access will be wrong. v2: Disable CLOCK_GATE_DISABLE bit after bit bashing as suggested by Eric. Signed-off-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: allow tiled front buffers on 965+Jesse Barnes2009-04-161-0/+1
| | | | | | | | | | | | | This patch corrects a pretty big oversight in the KMS code for 965+ chips. The current code is missing tiled surface register programming, so userland can allocate a tiled surface and use it for mode setting, resulting in corruption. This patch fixes that, allowing for tiled front buffers on 965+. Cc: stable@kernel.org Tested-by: Arkadiusz Miskiewicz <arekm@maven.pl> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: add VGA hotplug support for 945+Jesse Barnes2009-04-011-0/+8
| | | | | | | | | | | Add VGA port hotplug detection to the i915 driver. When KMS is enabled, plugging in or removing a VGA cable from the VGA connector will generate a uevent, which indicates to userspace that it should re-probe outputs on this device (to determine modes, etc.). Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> [anholt: dropped extra PORT_HOTPLUG_STAT clear with ack from jbarnes] Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: fix up tiling/fence reg setup on i8xx class hwDaniel Vetter2009-04-011-0/+3
| | | | | | | | | | | | | | | | | | | This fixes all the tiling problems with the 2d ddx. glxgears still doesn't work. Changes: - fix a copy&paste error in i8xx fence reg setup. It resulted in an at most a 512KB offset of the fence reg window, so was only visible sometimes. - add tests for stride and object size constrains (also for i915 and 1965 class hw). Userspace seems to have an of-by-one bug there, which changes the fence size by at most 512KB due to an overflow. - because i8xx hw is quite old (and therefore not as well-tested) I left 2 debug WARN_ONs in the i8xx fence reg setup code to hopefully catch any further overflows in the bit-fields. Lastly there's one small change to make the alignment checks more consistent. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=20289 Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: TV mode_set sync up with 2D driverZhenyu Wang2009-03-271-1/+1
| | | | | | | | Fix TV control save register for untouched bits, and color knobs different definition for 945 and 965 chips. Signed-off-by: Zhenyu Wang <zhenyu.z.wang@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Sync crt hotplug detection with intel video driverZhao Yakui2009-03-271-0/+16
| | | | | | | | This covers: Use long crt hotplug activation time on GM45. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* agp/intel: Add support for new intel chipset.Shaohua Li2009-03-271-0/+4
| | | | | | | This is a G33-like desktop and mobile chipset. Signed-off-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: fix 945 fence register writes for fence 8 and above.Eric Anholt2009-03-111-0/+1
| | | | | | | | | | | The last 8 fence registers sit at a different offset, so when we went to set fence number 8 in the lower offset, we instead set PGETBL_CTL, and the GPU got all sorts of angry at us. fd.o bug #20567. Easily reproducible by running glxgears and killing it about 6 times. Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: add get_vblank_counter function for GM45Jesse Barnes2009-02-081-0/+6
| | | | | | | | | | | As discussed in the long thread about vblank related timeouts, it turns out GM45 has different frame count registers than previous chips. This patch adds support for them, which prevents us from waiting on really stale sequence values in drm_wait_vblank (which rather than returning immediately ends up timing out or getting interrupted). Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Dave Airlie <airlied@linux.ie>
* drm/i915: add fence register management to execbufJesse Barnes2009-02-081-2/+2
| | | | | | | | | | | | Adds code to set up fence registers at execbuf time on pre-965 chips as necessary. Also fixes up a few bugs in the pre-965 tile register support (get_order != ffs). The number of fences available to the kernel defaults to the hw limit minus 3 (for legacy X front/back/depth), but a new parameter allows userspace to override that as needed. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Dave Airlie <airlied@linux.ie>
* drm/i915: Respect the other stolen memory sizes we know of.Eric Anholt2009-01-071-1/+7
| | | | | | | fd.o bug #19336. Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Dave Airlie <airlied@linux.ie>
* drm/i915: Add support for integrated HDMI on G4X hardware.Eric Anholt2009-01-071-0/+17
| | | | | | | | This is ported directly from the userland 2D driver code. The HDMI audio bits aren't hooked up yet. Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Dave Airlie <airlied@linux.ie>
* drm/i915: add GEM GTT mapping supportJesse Barnes2008-12-291-1/+19
| | | | | | | | | | Use the new core GEM object mapping code to allow GTT mapping of GEM objects on i915. The fault handler will make sure a fence register is allocated too, if the object in question is tiled. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/i915: Respect GM965/GM45 bit-17-instead-of-bit-11 option for swizzling.Eric Anholt2008-12-041-0/+1
| | | | | | | | | | | | | This fixes readpixels and buffer corruption when swapped out and in by disabling tiling on them. Now that we know that the bit 17 mode isn't just a mistake of older chipsets, we'll need to work on a clever fix so that we can get the performance of tiling on these chipsets, but that will require intrusive changes targeted at the next kernel release, not this one. Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Dave Airlie <airlied@redhat.com>
* i915: Save/restore MCHBAR_RENDER_STANDBY on GM965/GM45Keith Packard2008-11-111-0/+3
| | | | | | | | | This register is set by the 2D driver to prevent lockups, and so it needs to be preserved across suspend/resume too. This makes my X200s work. Signed-off-by: Keith Packard <keithp@keithp.com> Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Dave Airlie <airlied@linux.ie>
* drm: Add GEM ("graphics execution manager") to i915 driver.Eric Anholt2008-10-181-13/+24
| | | | | | | | | | | | | | | | GEM allows the creation of persistent buffer objects accessible by the graphics device through new ioctls for managing execution of commands on the device. The userland API is almost entirely driver-specific to ensure that any driver building on this model can easily map the interface to individual driver requirements. GEM is used by the 2d driver for managing its internal state allocations and will be used for pixmap storage to reduce memory consumption and enable zero-copy GLX_EXT_texture_from_pixmap, and in the 3d driver is used to enable GL_EXT_framebuffer_object and GL_ARB_pixel_buffer_object. Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Dave Airlie <airlied@redhat.com>
* Add Intel ACPI IGD OpRegion supportMatthew Garrett2008-10-181-0/+1
| | | | | | | | | This adds the support necessary for allowing ACPI backlight control to work on some newer Intel-based graphics systems. Tested on Thinkpad T61 and HP 2510p hardware. Signed-off-by: Matthew Garrett <mjg@redhat.com> Signed-off-by: Dave Airlie <airlied@linux.ie>
* i915: Use more consistent names for regs, and store them in a separate file.Jesse Barnes2008-10-181-0/+1405
Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Dave Airlie <airlied@redhat.com>
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