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path: root/drivers/gpu/drm/i915/i915_reg.h
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* drm/i915/cnl: WaPushConstantDereferenceHoldDisableOscar Mateo2017-08-231-0/+1
* drm/i915/cnl: Apply large line width optimizationRodrigo Vivi2017-08-181-0/+1
* drm/i915/cnl: Introduce initial Cannonlake Workarounds.Rodrigo Vivi2017-08-181-0/+6
* drm/i915/cnl: Setup PAT Index.Rodrigo Vivi2017-08-151-0/+1
* drm/i915/hsw+: Add support for multiple power well regsImre Deak2017-08-151-7/+25
* drm/i915: add register macro definition style guideJani Nikula2017-08-101-0/+91
* drm/i915: enum i915_power_well_id is not proper kernel-docJani Nikula2017-08-101-1/+1
* drm/i915: Add render decompression supportVille Syrjälä2017-08-101-0/+23
* drm/i915/psr: Preserve SRD_CTL bit 29 on PSR initJim Bride2017-08-091-0/+1
* drm/i915/perf: Implement I915_PERF_ADD/REMOVE_CONFIG interfaceLionel Landwerlin2017-08-031-3/+67
* drm/i915: reorder NOA register definition to follow addressesLionel Landwerlin2017-08-031-106/+106
* drm/i915: cleanup the CHICKEN_MISC_2 (re)definitionsPaulo Zanoni2017-07-271-5/+3
* drm/i915: prepare pipe for YCBCR420 outputShashank Sharma2017-07-271-0/+3
* drm/i915/hsw+: Add has_fuses power well attributeImre Deak2017-07-271-4/+10
* drm/i915/hsw+: Unify the hsw/bdw and gen9+ power well req/state macrosImre Deak2017-07-271-5/+3
* drm/i915/hsw, bdw: Add an ID for the global display power wellImre Deak2017-07-271-0/+6
* drm/i915/gen2: Add an ID for the display pipes power wellImre Deak2017-07-271-0/+6
* drm/i915: Unify power well ID enumsImre Deak2017-07-271-14/+28
* drm/i915/chv: Add unique power well ID for the pipe A power wellImre Deak2017-07-271-0/+2
* drm/i915/cnl: Get DDI clock based on PLLs.Rodrigo Vivi2017-07-071-0/+2
* drm/i915/cnl: Inherit RPS stuff from previous platforms.Rodrigo Vivi2017-07-071-2/+2
* drm/i915/cnl: Fix the CURSOR_COEFF_MASK used in DDI Vswing ProgrammingNavare, Manasi D2017-06-301-1/+1
* drm/i915/cnl: Fix RMW on ddi vswing sequence.Rodrigo Vivi2017-06-191-0/+9
* drm/i915/perf: Add OA unit support for Gen 8+Robert Bragg2017-06-141-0/+22
* drm/i915/cnl: Implement voltage swing sequence.Rodrigo Vivi2017-06-121-0/+1
* drm/i915/cnl: Add registers related to voltage swing sequences.Rodrigo Vivi2017-06-121-0/+140
* drm/i915: Add MMIO helper for 6 ports with different offsets.Rodrigo Vivi2017-06-121-0/+3
* drm/i915/cnl: Initialize PLLsRodrigo Vivi2017-06-121-0/+48
* drm/i915/cnl: DDI - PLL mappingRodrigo Vivi2017-06-121-0/+9
* drm/i915/cnl: Implement CNL display init/unit sequenceVille Syrjälä2017-06-121-0/+23
* drm/i915/cnl: Implement .get_display_clock_speed() for CNLVille Syrjälä2017-06-121-0/+5
* drm/i915: Remove unnecessary PORT3 definition.Rodrigo Vivi2017-06-071-4/+2
* drm/i915/cnl: Add power wells for CNLVille Syrjälä2017-06-071-0/+5
* drm/i915: Implement fbc_status "Compressing" info for all platformsVille Syrjälä2017-06-061-5/+5
* drm/i915/cnp: add CNP gmbus supportRodrigo Vivi2017-06-021-1/+2
* drm/i915/cnp: Get/set proper Raw clock frequency on CNP.Rodrigo Vivi2017-06-021-0/+5
* drm/i915: Remove decoupled MMIO codeKai Chen2017-05-301-7/+0
* drm/i915: Fix new -Wint-in-bool-context gcc compiler warningHans de Goede2017-05-181-1/+1
* drm/i915: Support variable cursor height on ivb+Ville Syrjälä2017-05-101-1/+4
* drm/i915: Parametrize cursor/primary pipe select bitsVille Syrjälä2017-05-101-5/+2
* drm/i915: Fix rawclk readout for g4xVille Syrjälä2017-05-051-3/+7
* drm/i915: Sanitize engine context sizesJoonas Lahtinen2017-04-281-10/+0
* drm/i915: Classify the engines in class + instanceDaniele Ceraolo Spurio2017-04-111-0/+8
* drm/i915: enable scramblingShashank Sharma2017-03-281-0/+7
* drm/i915: Use ktime to calculate rc0 residencyMika Kuoppala2017-03-161-2/+0
* drm/i915: Rename REDIRECT_TO_GUC bitChris Wilson2017-03-131-1/+1
* drm/i915: Initialize pm_intr_keep during intel_irq_init for GuCSagar Arun Kamble2017-03-091-1/+2
* Merge tag 'drm-intel-next-2017-03-06' of git://anongit.freedesktop.org/git/dr...Dave Airlie2017-03-081-12/+90
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| * drm/i915: Don't use enums for hardware engine idMichal Wajdeczko2017-03-031-0/+6
| * drm/i915: Tighten mmio arrays for MIPI_PORTChris Wilson2017-03-011-1/+1
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